commit d439638ea4ec412d3b59a4fd7990d9a1d1b17a3c Author: benoa Date: Fri May 25 20:45:09 2018 +0200 Initial import of HatariWii 0.0.5 diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 0000000..ab51033 --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,361 @@ + +cmake_minimum_required(VERSION 2.6 FATAL_ERROR) + +if(POLICY CMP0026) + # Should be removed if cmake_minimum_required >= 2.8.8 + cmake_policy(SET CMP0026 OLD) +endif(POLICY CMP0026) + +project(Hatari C) + +SET(APP_NAME "Hatari") + +set(CMAKE_MODULE_PATH "${CMAKE_SOURCE_DIR}/cmake") + +include(CheckIncludeFiles) +include(CheckFunctionExists) +include(CheckStructHasMember) +include(CheckCCompilerFlag) +include(DistClean) + +# Set build type to "Release" if user did not specify any build type yet +# Other possible values: Debug, Release, RelWithDebInfo and MinSizeRel +if(NOT CMAKE_BUILD_TYPE) + set(CMAKE_BUILD_TYPE Release) +endif(NOT CMAKE_BUILD_TYPE) + +# set(CMAKE_VERBOSE_MAKEFILE 1) + +# ########################## +# Conditional build features +# ########################## + +set(ENABLE_SDL2 0 + CACHE BOOL "Enable building with libSDL2 instead of v1.2") +set(ENABLE_DSP_EMU 1 + CACHE BOOL "Enable DSP 56k emulator for Falcon mode") +set(ENABLE_TRACING 1 + CACHE BOOL "Enable tracing messages for debugging") +set(ENABLE_SMALL_MEM 0 + CACHE BOOL "Enable to use less memory - at the expense of emulation speed") +set(ENABLE_WINUAE_CPU 0 + CACHE BOOL "Enable WinUAE CPU core (experimental!)") + +# Run-time checks with GCC "mudflap" etc features: +# - stack protection +# - checking of pointer accesses +# +# Before running CMake, install "mudflap" library development package +# (libmudflap0-4.4-dev in Debian Squeeze and libmudflap-devel in Fedora). +# +# After this you can configure Hatari with Mudflap: +# cd build; make clean; cmake -D ENABLE_MUDFLAP:BOOL=1 -D .. +# If everything's fine, CMake output should include: +# Performing Test MUDFLAP_AVAILABLE - Success" +# +# After (re-)building Hatari, run it with something like this: +# MUDFLAP_OPTIONS="-viol-gdb" src/hatari --sound off --mic off +# (sound&mic are disabled because threading doesn't work well with Mudflap) +# +# For more info: +# http://gcc.gnu.org/wiki/Mudflap_Pointer_Debugging +# +set(CMAKE_REQUIRED_LIBRARIES "mudflap") +CHECK_C_COMPILER_FLAG("-fmudflapth" MUDFLAP_AVAILABLE) +set(CMAKE_REQUIRED_LIBRARIES "") +if(MUDFLAP_AVAILABLE) + set(ENABLE_MUDFLAP 0 + CACHE BOOL "Enable GCC run-time stack/pointer debugging - with huge slowdown") +endif(MUDFLAP_AVAILABLE) + +if(APPLE) + set(ENABLE_OSX_BUNDLE 1 + CACHE BOOL "Built Hatari as Mac OS X application bundle") + # set(CMAKE_OSX_ARCHITECTURES "i386" CACHE STRING "Target architectures" FORCE) + # set(CMAKE_OSX_SYSROOT "/Developer/SDKs/MacOSX10.6.sdk" CACHE STRING "10.6 SDK" FORCE) + # set(CMAKE_OSX_DEPLOYMENT_TARGET "10.5" CACHE STRING "Target Min 10.5" FORCE) + set(ADDITIONAL_INCLUDES ${FRAMEWORKS}) + set_source_files_properties(${FRAMEWORKS} PROPERTIES MACOSX_PACKAGE_LOCATION Frameworks) +else() + set(ENABLE_OSX_BUNDLE 0 + CACHE BOOL "Built Hatari as Mac OS X application bundle") +endif(APPLE) + +# #################### +# Check for libraries: +# #################### + +if(ENABLE_SDL2) + find_package(SDL2 REQUIRED) + if(NOT SDL2_FOUND) + message(FATAL_ERROR "SDL2 library not found!") + endif(NOT SDL2_FOUND) + set(SDL_INCLUDE_DIR ${SDL2_INCLUDE_DIR}) + set(SDL_LIBRARY ${SDL2_LIBRARY}) + set(SDLMAIN_LIBRARY ${SDL2MAIN_LIBRARY}) +else(ENABLE_SDL2) + find_package(SDL REQUIRED) + if(NOT SDL_FOUND) + message(FATAL_ERROR "SDL library not found!") + endif(NOT SDL_FOUND) +endif(ENABLE_SDL2) + +find_package(Math) + +find_package(Readline) +if(READLINE_FOUND) + set(HAVE_LIBREADLINE 1) +endif(READLINE_FOUND) + +find_package(ZLIB) +if(ZLIB_FOUND) + set(HAVE_LIBZ 1) + set(HAVE_ZLIB_H 1) +endif(ZLIB_FOUND) + +find_package(PNG) +if(PNG_FOUND) + set(HAVE_LIBPNG 1) +endif(PNG_FOUND) + +if (NOT ENABLE_OSX_BUNDLE) + find_package(X11) + if(X11_FOUND) + set(HAVE_X11 1) + endif(X11_FOUND) +endif() + +find_package(PortAudio) +if(PORTAUDIO_FOUND) + set(HAVE_PORTAUDIO 1) +endif(PORTAUDIO_FOUND) + +find_package(CapsImage) +if(CAPSIMAGE_FOUND) + set(HAVE_CAPSIMAGE 1) +endif(CAPSIMAGE_FOUND) + +# ################ +# CPP Definitions: +# ################ + +# Test for large file support: +execute_process(COMMAND getconf LFS_CFLAGS + OUTPUT_VARIABLE DETECTED_LFS_CFLAGS + ERROR_QUIET OUTPUT_STRIP_TRAILING_WHITESPACE) +if(DETECTED_LFS_CFLAGS) + add_definitions(${DETECTED_LFS_CFLAGS}) + # message(STATUS "Large filesystem flags: ${DETECTED_LFS_CFLAGS}") +endif(DETECTED_LFS_CFLAGS) + +# Additional CFLAGS suggested by the SDL library: +if(ENABLE_SDL2) + add_definitions(-DWITH_SDL2) + execute_process(COMMAND pkg-config --cflags-only-other sdl2 + OUTPUT_VARIABLE DETECTED_SDL_CFLAGS + ERROR_QUIET OUTPUT_STRIP_TRAILING_WHITESPACE) +else(ENABLE_SDL2) + execute_process(COMMAND pkg-config --cflags-only-other sdl + OUTPUT_VARIABLE DETECTED_SDL_CFLAGS + ERROR_QUIET OUTPUT_STRIP_TRAILING_WHITESPACE) +endif(ENABLE_SDL2) +if(DETECTED_SDL_CFLAGS) + add_definitions(${DETECTED_SDL_CFLAGS}) + # message(STATUS "Additional CFLAGS of SDL: ${DETECTED_SDL_CFLAGS}") +endif(DETECTED_SDL_CFLAGS) + +if(ENABLE_OSX_BUNDLE) + # Use OSX native alert windows + add_definitions(-DALERT_HOOKS=1) + if(ENABLE_SDL2) + # We still want to use our SDLMain.m with SDL2 + add_definitions(-DSDL_MAIN_NEEDED=1) + endif(ENABLE_SDL2) +endif(ENABLE_OSX_BUNDLE) + +# ########################### +# Check for optional headers: +# ########################### + +check_include_files(termios.h HAVE_TERMIOS_H) +check_include_files(strings.h HAVE_STRINGS_H) +check_include_files(malloc.h HAVE_MALLOC_H) +check_include_files(${SDL_INCLUDE_DIR}/SDL_config.h HAVE_SDL_CONFIG_H) +check_include_files(sys/times.h HAVE_SYS_TIMES_H) +check_include_files("sys/socket.h;sys/un.h" HAVE_UNIX_DOMAIN_SOCKETS) + +# ############################# +# Check for optional functions: +# ############################# + +check_function_exists(cfmakeraw HAVE_CFMAKERAW) +check_function_exists(setenv HAVE_SETENV) +check_function_exists(select HAVE_SELECT) +check_function_exists(posix_memalign HAVE_POSIX_MEMALIGN) +check_function_exists(memalign HAVE_MEMALIGN) +check_function_exists(gettimeofday HAVE_GETTIMEOFDAY) +check_function_exists(nanosleep HAVE_NANOSLEEP) +check_function_exists(alphasort HAVE_ALPHASORT) +check_function_exists(scandir HAVE_SCANDIR) +check_function_exists(statvfs HAVE_STATVFS) +check_function_exists(fseeko HAVE_FSEEKO) +check_function_exists(ftello HAVE_FTELLO) +check_function_exists(flock HAVE_FLOCK) +check_function_exists(strlcpy HAVE_LIBC_STRLCPY) +check_struct_has_member("struct dirent" d_type dirent.h HAVE_DIRENT_D_TYPE) + +# ############# +# Other CFLAGS: +# ############# + +# GCC pointer debugging, huge run-time slowdown +if(ENABLE_MUDFLAP) + # SDL mixer threads so have to use threaded mudflap version + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -g -fstack-protector-all -fmudflapth") + set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -fmudflapth -lmudflap") +endif(ENABLE_MUDFLAP) + +# Warning flags: +if(CMAKE_COMPILER_IS_GNUCC) + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wcast-qual -Wbad-function-cast -Wpointer-arith") + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wmissing-prototypes -Wstrict-prototypes") + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -Wwrite-strings -Wsign-compare") + #set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wextra -Wno-unused-parameter -Wno-empty-body") + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wformat-security") + #set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wshadow -D_FORTIFY_SOURCE=2 -Werror") +endif(CMAKE_COMPILER_IS_GNUCC) + +# Building Hatari w/o optimization is no fun... +IF (CMAKE_BUILD_TYPE STREQUAL "Debug") + set(CMAKE_C_FLAGS "-O ${CMAKE_C_FLAGS}") +ENDIF (CMAKE_BUILD_TYPE STREQUAL "Debug") + +# #################### +# Paths configuration: +# #################### + +if(NOT BINDIR) + set(BINDIR bin) +endif() + +if(NOT DATADIR) + set(DATADIR share/hatari) +endif() + +if(NOT BIN2DATADIR) + if(WIN32) + set(BIN2DATADIR "." + CACHE STRING "Relative path from bindir to datadir") + elseif(ENABLE_OSX_BUNDLE) + set(BIN2DATADIR "../Resources" + CACHE STRING "Relative path from bindir to datadir") + else() + set(BIN2DATADIR "../share/hatari" + CACHE STRING "Relative path from bindir to datadir") + endif(WIN32) + mark_as_advanced(BIN2DATADIR) +endif() + +if(NOT MANDIR) + set(MANDIR share/man/man1) +endif() + +if(NOT DOCDIR) + set(DOCDIR share/doc/hatari) +endif() + +if(NOT ETCDIR) + if(WIN32) + set(ETCDIR .) + else() + set(ETCDIR /etc) + endif() +endif() + +if(NOT ICONDIR) + set(ICONDIR share/icons/hicolor) +endif() + +if(ENABLE_OSX_BUNDLE) + # put the config files in the app's bundle + add_definitions(-DCONFDIR=\"../Resources\") +else() + add_definitions(-DCONFDIR=\"${ETCDIR}\") +endif() + +# ######################################### +# Create config.h and recurse into subdirs: +# ######################################### + +configure_file(${CMAKE_SOURCE_DIR}/cmake/config-cmake.h + ${CMAKE_BINARY_DIR}/config.h) + +add_subdirectory(src) +add_subdirectory(doc) +add_subdirectory(tools) + +include(FindPythonInterp) +if(PYTHONINTERP_FOUND) + add_subdirectory(python-ui) +endif(PYTHONINTERP_FOUND) + +if(UNIX AND NOT ENABLE_OSX_BUNDLE) + add_subdirectory(share) +endif() + +add_custom_target(uninstall + COMMAND ${CMAKE_COMMAND} -P ${CMAKE_SOURCE_DIR}/cmake/Uninstall.cmake) + + +# ################################################################### +# Print a summary of the optional libraries with a short explanation: +# ################################################################### + +message( " +Libraries summary : +------------------- +") + +if(SDL2_FOUND) + message(" - sdl :\tusing SDL2 v${SDL2_VERSION_STRING}") +else() + if(SDL_VERSION_STRING) + message(" - sdl :\tusing SDL v${SDL_VERSION_STRING}") + else() + message(" - sdl :\tusing SDL1") + endif(SDL_VERSION_STRING) +endif(SDL2_FOUND) + +if(READLINE_FOUND) + message( " - readline :\tfound, enables history/completion in the debugger" ) +else() + message( " - readline :\tnot found, install it to enable debugger history/completion" ) +endif(READLINE_FOUND) + +if(ZLIB_FOUND) + message( " - zlib :\tfound, allows to use zip/gz files directly" ) +else() + message( " - zlib :\tnot found, install it to use zip/gz files" ) +endif(ZLIB_FOUND) + +if(PNG_FOUND) + message( " - png :\tfound, allows to compress screenshot/avi files using png" ) +else() + message( " - png :\tnot found, install it to compress screenshot/avi files using png" ) +endif(PNG_FOUND) + +if(PORTAUDIO_FOUND) + message( " - portaudio :\tfound, enables the microphone input in Falcon mode" ) +else() + message( " - portaudio :\tnot found, install it to enable the Falcon microphone input" ) +endif(PORTAUDIO_FOUND) + +if(CAPSIMAGE_FOUND) + message( " - capsimage :\tv${CAPSIMAGE_VERSION} found, allow to use .IPF, .RAW and .CTR disk images" ) +else() + message( " - capsimage :\tv${CAPSIMAGE_VERSION} not found, install it to use .IPF, .RAW and .CTR disk images" ) +endif(CAPSIMAGE_FOUND) + +message( "" ) + + diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..37fd05e --- /dev/null +++ b/Makefile @@ -0,0 +1,6 @@ +all: + cd src; $(MAKE) -f Makefile.wii +clean: + cd src; $(MAKE) -f Makefile.wii clean +run: + cd src; wiiload hatari.dol diff --git a/Makefile-default.cnf b/Makefile-default.cnf new file mode 100755 index 0000000..387827d --- /dev/null +++ b/Makefile-default.cnf @@ -0,0 +1,132 @@ +# Makefile configuration for Hatari. +# +# Use of '?=' for assignment allows overriding the given value with +# an environment variable, like this: +# HOSTCC=my-hostcc make +# or: +# export HOSTCC=my-hostcc +# make +# +# Following variables can be overridden like that: +# CPPFLAGS, LDFLAGS, LIBS, HOSTCC, DATADIR, CONFDIR, BINDIR, MANDIR, DOCDIR +# +# GNU make itself supports overriding CC like this: +# make CC=my-cc + +# Set the C compiler (e.g. gcc) +CC = gcc + +OPTFLAGS = -O2 + +# Architecture specific settings +# +# Omap2/ARMv6: +# OPTFLAGS += -mfpu=vfp -mfloat-abi=softfp -march=armv6 -finline-limit=64 +# +# Wii/Gekko: +# OPTFLAGS = -MMD -MP -MF -O3 -mrvl -mcpu=750 -meabi -mhard-float +# CPPFLAGS = -DGEKKO -I$(DEVKITPRO)/libogc/include -I$(DEVKITPRO)/libogc/include/sdl +# LDFLAGS = -L$(DEVKITPRO)/libogc/lib/wii -Wl,-Map,hatari.map +# LIBS = -lz -lfat -lwiiuse -lbte -lasnd -logc -lm + +# What warnings to use +WARNFLAGS = -Wmissing-prototypes -Wstrict-prototypes -Wsign-compare \ + -Wbad-function-cast -Wcast-qual -Wpointer-arith \ + -Wall -Wwrite-strings # -Wshadow -Wcast-align -Werror + + +ifneq ($(MUDFLAP),) +# Run-time checks with GCC "mudflap" etc: +# - stack protection +# - checking of pointer accesses (AFAIK works only on x86) +# +# Before build, install "libmudflap--dev" +# package (libmudflap0-4.3-dev in Debian Lenny). +# +# To build, use: +# make clean; make MUDFLAP=1 +# +# To run, use something like (disable sound as it can break things): +# MUDFLAP_OPTIONS="-viol-gdb" ./hatari --sound off +# +# For more info, see (for now, works properly only for x86 gcc): +# http://gcc.gnu.org/wiki/Mudflap_Pointer_Debugging +# +RUNCHECKS = -fstack-protector-all -fmudflapth #-fmudflapir +LDRUNCHECKS = -fmudflapth -lmudflap +endif + + +# Set flags passed to the compiler (e.g. optimization flags) +CFLAGS := -g $(WARNFLAGS) $(OPTFLAGS) $(RUNCHECKS) + +# Set flags passed to the preprocessor (e.g. -I) +CPPFLAGS ?= + +# Additional libraries and linker flags: +LIBS ?= -lz -lm # -lreadline +LDFLAGS ?= $(LDRUNCHECKS) + +# Ranlib - for generating an index of an archive +RANLIB = ranlib + + +# The native C compiler. +# This is normally the same as $(CC) unless you are using a cross compiler. +HOSTCC ?= $(CC) + +# Native C compiler flags: +HOSTCFLAGS = -g -O -Wall + +# Native linker flags: +HOSTLDFLAGS = + + +# SDL-Library configuration (compiler flags and linker options) - you normally +# don't have to change this if you have correctly installed the SDL library! +SDL_CFLAGS := $(shell sdl-config --cflags) +SDL_LIBS := $(shell sdl-config --libs) + +# libpng configuration (for PNG format screenshots) +PNG_LIBS := $(shell pkg-config --silence-errors --libs libpng) +ifneq ($(PNG_LIBS),) +PNG_CFLAGS := -DHAVE_LIBPNG=1 $(shell pkg-config --cflags libpng) +endif + +# X11 configuration (for SDL window embedding) +X11_LIBS := $(shell pkg-config --silence-errors --libs x11) +ifneq ($(X11_LIBS),) +X11_CFLAGS := -DHAVE_X11=1 $(shell pkg-config --cflags x11) +endif + +# PORTAUDIO configuration (to support Falcon microphone) +PORTAUDIO_LIBS := $(shell pkg-config --silence-errors --libs portaudio-2.0) +ifneq ($(PORTAUDIO_LIBS),) +PORTAUDIO_CFLAGS := -DHAVE_PORTAUDIO=1 $(shell pkg-config --cflags portaudio-2.0) +endif + +# Here you can define the default data directory for Hatari. +# The emulator looks there for the default TOS image etc. +# For example you can use the local directory with "." or if you want +# a system-wide installation, use something like "/usr/share/hatari". +DATADIR ?= . + +# In this folder, Hatari searches the global configuration file. +# /etc or /usr/local/etc is a good place for this. +CONFDIR ?= /etc + +# The executable will be installed in BINDIR +#BINDIR ?= /usr/local/bin + +# The man-page will be install in MANDIR +#MANDIR ?= /usr/local/share/man/man1 + +# All other documentation will be installed in DOCDIR +#DOCDIR ?= /usr/local/share/doc/hatari + +# Program used for "make install" +#INSTALL = install -c +#INSTALL_PROGRAM = $(INSTALL) -s -m 755 +#INSTALL_SCRIPT = $(INSTALL) -m 755 +#INSTALL_DATA = $(INSTALL) -m 644 + diff --git a/Makefile-wii.cnf b/Makefile-wii.cnf new file mode 100755 index 0000000..13816b6 --- /dev/null +++ b/Makefile-wii.cnf @@ -0,0 +1,62 @@ +# Makefile configuration for Hatari. +# +# Use of '?=' for assignment allows overriding the given value with +# an environment variable, e.g. like this "make CC=my-gcc" +# +# Following variables can be overridden: +# CC, CPPFLAGS, LDFLAGS, HOSTCC, DATADIR, CONFDIR, BINDIR + +# Set the C compiler (e.g. gcc) +CC = powerpc-eabi-gcc + +# Include directories +INCLUDE = -I$(DEVKITPRO)/libogc/include -I$(DEVKITPRO)/libogc/include/SDL + +DEFINES = -DHAVE_DIRENT_D_TYPE + +# Architecture specific optimizations +# +# Omap2/ARMv6: +# OPTFLAGS += -mfpu=vfp -mfloat-abi=softfp -march=armv6 -finline-limit=64 + +OPTFLAGS = -MMD -MP -MF -flto -O2 -DGEKKO -mrvl -mcpu=750 -meabi -mhard-float + +# What warnings to use +WARNFLAGS = -Wsign-compare \ + -Wbad-function-cast -Wcast-qual -Wpointer-arith \ + -Wall -Wwrite-strings # -Wshadow -Wcast-align -Werror + +# Set flags passed to the compiler (e.g. optimization flags) +CFLAGS := -g $(WARNFLAGS) $(INCLUDE) $(OPTFLAGS) $(DEFINES) + +# Set flags passed to the preprocessor (e.g. -I) +CPPFLAGS ?= + +# Additional libraries and linker flags: +LIBS = -lz # -lreadline +LDFLAGS ?= -g -DGEKKO -mrvl -mcpu=750 -meabi -mhard-float -Wl,-Map,hatari.map + +# Ranlib - for generating an index of an archive +RANLIB = ranlib + +# The native C compiler. +# This is normaly the same as $(CC) unless you are using a cross compiler. +HOSTCC ?= gcc + +# Native C compiler flags: +HOSTCFLAGS = -g -O -Wall + +# Native linker flags: +HOSTLDFLAGS = + +# SDL-Library configuration (compiler flags and linker options) - you normally +# don't have to change this if you have correctly installed the SDL library! +#SDL_CFLAGS := -I$(DEVKITPRO)/libogc/include +SDL_LIBS := -L$(DEVKITPRO)/libogc/lib/wii -lSDL_ttf -lSDL_image -lsmpeg -lSDL -lpng -ljpeg -lvorbisidec -lfat -lwiiuse -lbte -lz -logc -lm -lwiikeyboard + +# Here you can define the default data directory for Hatari. +# The emulator looks there for the default TOS image etc. +# For example you can use the local directory with "." or if you want +# a system-wide installation, use something like "/usr/share/hatari". +#BIN2DATADIR ?= /apps/hatari + diff --git a/Visual.Studio/VisualStudioFix.c b/Visual.Studio/VisualStudioFix.c new file mode 100644 index 0000000..3b4a6c8 --- /dev/null +++ b/Visual.Studio/VisualStudioFix.c @@ -0,0 +1,80 @@ + /* + * Hatari - Fix for compliation using Visual Studio 6 + * + * This file is distributed under the GNU General Public License, version 2 + * or at your option any later version. Read the file gpl.txt for details. + */ + +#if defined(_VCWIN_) +#pragma comment(lib, ".\\SDL\\lib\\sdl.lib") // sdl.lib +#pragma comment(lib, ".\\zlib\\win32\\zlib1.lib") // zlib1.lib +#endif + +#if defined(_VCWIN_) + #include + #include + #include +#endif + +#include "log.h" + +extern FILE *TraceFile; + +#if defined(_VCWIN_) + #ifndef _INC_HATARI_TRACE + #define _INC_HATARI_TRACE + + #if ENABLE_TRACING + void LOG_TRACE(int level, const char* format, ...) + { + va_list x; + va_start(x,format); + if ( HatariTraceFlags & level ) _vftprintf(TraceFile,format, x); + va_end (x); + }; + #else /* ENABLE_TRACING */ + void LOG_TRACE(int level, ...) + { + } + + #endif /* ENABLE_TRACING */ + + void LOG_TRACE_PRINT(char* strFirstString, ...) + { + va_list x; + va_start(x,strFirstString); + _vftprintf(TraceFile,strFirstString, x); + va_end (x); + }; + + #endif + +#endif + + +#define WIN32_LEAN_AND_MEAN // Exclude rarely-used stuff from Windows headers + +// Windows Header Files: +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +extern int SDL_main(int argc, char *argv[]); + +int main(int argc, char *argv[]) +{ + return SDL_main(argc,argv); +} + +int APIENTRY WinMain(HINSTANCE hInstance, HINSTANCE hPrevInstance, + LPSTR lpCmdLine, int nCmdShow) +{ + return SDL_main(1,&lpCmdLine); +} + +#ifdef __cplusplus +} +#endif diff --git a/Visual.Studio/VisualStudioFix.h b/Visual.Studio/VisualStudioFix.h new file mode 100644 index 0000000..1ca116e --- /dev/null +++ b/Visual.Studio/VisualStudioFix.h @@ -0,0 +1,135 @@ + /* + * Hatari - Fix for compliation using Visual Studio 6 + * + * This file is distributed under the GNU General Public License, version 2 + * or at your option any later version. Read the file gpl.txt for details. + * + * This file tells Visual Studio to ignore a number of relatively minor "warnings" that have found their + * way into the HAtari source. None of the "warnings" will hamper the running or compliation or HAtari + * but it is possible not addressing them may make it difficult for other developers to be sure of the + * intentions of the original coders against whos code these warnings are raised. + * As long as the original coder was aware of the warnings and of the implicit result of adding no + * explicit casts to remove them then things are good. + * + * 2009 Vaughan Kaufman + * + */ + +#if defined(_VCWIN_) // Stop Visual Studio complaining about all the implicit type conversions (wish we would make them explict guys/girls) + #pragma warning (disable:4244) // conversion with potential data loss + #pragma warning (disable:4761) // integral size mismatch in argument + #pragma warning (disable:4146) // unary minus operator applied to unsigned type + #pragma warning (disable:4018) // signed / unsigned mismatch + #pragma warning (disable:4102) // ignore unused label warning + #pragma warning (disable:4049) // (this one is silly, its not important) compiler limit, end of line numbering + #pragma warning (disable:4800) // Performance Warning on Conversion of bool to int + #pragma warning (disable:4805) // warning C4805: '|=' : unsafe mix of type 'int' and type 'bool' in operation +#endif + + /* + * KVK - Fix for compliation using Visual Studio 6 + * + * Microsoft have created multiple versions of the standard C calls, a specific version exists for each type of string encoding + * format (in this case UNICODE (Wide) and ANSI (Ascii) versions. This has lead to there being versions with a A or a W after + * the name to signify the encoding. There are other additional reasons why they have these different versions (something to + * do with the change from BSTR to string class passing I think, anyone?). The upshot is, we need to add a _ to the beginning of + * some of the function names for HAtari to compile.. + * + * 2009 Vaughan Kaufman + * + */ + +#if defined(_VCWIN_) + #define STATIC_INLINE static __inline + #define GLOB_ONLYDIR 0 + + #include + #include + #include + #include + + #include + + #define stat _stat + #define S_IRUSR _S_IREAD + #define S_IWUSR _S_IWRITE + #define S_ISDIR(val) (_S_IFDIR & val) + #define S_IFDIR _S_IFDIR + + #define strncasecmp _strnicmp + #ifndef strcasecmp + #define strcasecmp _stricmp + #endif + #define chdrive _chdrive + #define strdup _strdup + #define getcwd _getcwd + #define fileno _fileno + #define unlink _unlink + #define access _access + #ifndef mkdir + #define mkdir(name,mode) _mkdir(name) + #endif + #define rmdir _rmdir + #define chmod _chmod + #define itoa _itoa + #define stricmp _stricmp + #define snprintf _snprintf + #define vsnprintf _vsnprintf + + #define __attribute__(x) /* x */ + + // For new UI + + typedef unsigned short mode_t; + + #ifndef _NEW_UI_TYPES + #define _NEW_UI_TYPES + typedef signed __int8 int8; + typedef unsigned __int8 uint8; + typedef signed __int16 int16; + typedef unsigned __int16 uint16; + typedef signed __int32 int32; + typedef unsigned __int32 uint32; + typedef signed __int64 int64; + typedef unsigned __int64 uint64; + typedef void* memptr; + #endif + + typedef signed __int8 int8_t; + typedef unsigned __int8 uint8_t; + typedef signed __int16 int16_t; + typedef unsigned __int16 uint16_t; + typedef signed __int32 int32_t; + typedef unsigned __int32 uint32_t; + typedef signed __int64 int64_t; + typedef unsigned __int64 uint64_t; + + #ifndef __inline__ + #define __inline__ __inline + #endif + + /* The variable-types used in the CPU core: */ + typedef uint8_t uae_u8; + typedef int8_t uae_s8; + + typedef uint16_t uae_u16; + typedef int16_t uae_s16; + + typedef uint32_t uae_u32; + typedef int32_t uae_s32; + + typedef uae_u32 uaecptr; + + extern void LOG_TRACE(int level, ...); + extern void LOG_TRACE_PRINT(char* strFirstString, ...); + + #ifdef JOY_BUTTON1 + #undef JOY_BUTTON1 + #endif + #ifdef JOY_BUTTON2 + #undef JOY_BUTTON2 + #endif + + extern void Win_OpenCon(void); + +#endif diff --git a/cmake/DistClean.cmake b/cmake/DistClean.cmake new file mode 100644 index 0000000..bf8e776 --- /dev/null +++ b/cmake/DistClean.cmake @@ -0,0 +1,27 @@ +# +# "distclean" target for removing the generated files from CMake +# + +if(UNIX) + add_custom_target(distclean COMMENT "Cleaning up for distribution") + # Clean up Hatari specific files: + foreach(CLEAN_FILE config.h install_manifest.txt src/hatari + src/cpu/build68k src/cpu/cpudefs.c src/cpu/cpuemu_*.c + src/cpu/cpustbl.c src/cpu/cputbl.h src/cpu/gencpu + src/uae-cpu/build68k src/uae-cpu/gencpu + src/uae-cpu/cpudefs.c src/uae-cpu/cpuemu.c + src/uae-cpu/cpustbl.c src/uae-cpu/cputbl.h + tools/hmsa/hmsa tools/debugger/gst2ascii + python-ui/conftypes.py) + add_custom_command(TARGET distclean POST_BUILD + COMMAND rm -f ${CLEAN_FILE} + DEPENDS clean) + endforeach(CLEAN_FILE) + # Clean up files that can appear at multiple places: + foreach(CLEAN_FILE CMakeFiles CMakeCache.txt '*.a' '*.1.gz' + cmake_install.cmake Makefile) + add_custom_command(TARGET distclean POST_BUILD + COMMAND find . -depth -name ${CLEAN_FILE} | xargs rm -rf + DEPENDS clean) + endforeach(CLEAN_FILE) +endif(UNIX) diff --git a/cmake/FindCapsImage.cmake b/cmake/FindCapsImage.cmake new file mode 100644 index 0000000..982e528 --- /dev/null +++ b/cmake/FindCapsImage.cmake @@ -0,0 +1,31 @@ + +IF (CAPSIMAGE_INCLUDE_DIR) + # Already in cache, be silent + SET(CAPSIMAGE_FIND_QUIETLY TRUE) +ENDIF (CAPSIMAGE_INCLUDE_DIR) + + +# Choose the library version to use : 4 or 5 +SET(CAPSIMAGE_VERSION 4) + + +if(CAPSIMAGE_VERSION STREQUAL 4) + SET(CAPSIMAGE_DIR caps) + FIND_PATH(CAPSIMAGE_INCLUDE_DIR ${CAPSIMAGE_DIR}/capsimage.h) +else() + SET(CAPSIMAGE_DIR caps5) + FIND_PATH(CAPSIMAGE_INCLUDE_DIR ${CAPSIMAGE_DIR}/CapsAPI.h) +endif() + +if(WIN32) + FIND_LIBRARY(CAPSIMAGE_LIBRARY NAMES capsimg PATH_SUFFIXES ${CAPSIMAGE_DIR} ) +else() + FIND_LIBRARY(CAPSIMAGE_LIBRARY NAMES capsimage PATH_SUFFIXES ${CAPSIMAGE_DIR} ) +endif(WIN32) + +INCLUDE(FindPackageHandleStandardArgs) +FIND_PACKAGE_HANDLE_STANDARD_ARGS(CAPSIMAGE DEFAULT_MSG + CAPSIMAGE_LIBRARY CAPSIMAGE_INCLUDE_DIR) + + +MARK_AS_ADVANCED(CAPSIMAGE_LIBRARY CAPSIMAGE_INCLUDE_DIR) diff --git a/cmake/FindMath.cmake b/cmake/FindMath.cmake new file mode 100644 index 0000000..b6ea939 --- /dev/null +++ b/cmake/FindMath.cmake @@ -0,0 +1,15 @@ + +if(MATH_INCLUDE_DIR) + # Already in cache, be silent + set(MATH_FIND_QUIETLY TRUE) +endif(MATH_INCLUDE_DIR) + +find_path(MATH_INCLUDE_DIR math.h) + +find_library(MATH_LIBRARY NAMES m) + +include(FindPackageHandleStandardArgs) +find_package_handle_standard_args(MATH DEFAULT_MSG + MATH_LIBRARY MATH_INCLUDE_DIR) + +mark_as_advanced(MATH_LIBRARY MATH_INCLUDE_DIR) diff --git a/cmake/FindPortAudio.cmake b/cmake/FindPortAudio.cmake new file mode 100644 index 0000000..35a57e6 --- /dev/null +++ b/cmake/FindPortAudio.cmake @@ -0,0 +1,35 @@ +# +# Find the native PORTAUDIO (version 2) includes and library +# +# PORTAUDIO_INCLUDE_DIR - where to find portaudio.h, etc. +# PORTAUDIO_LIBRARY - List of libraries when using portaudio. +# PORTAUDIO_FOUND - True if portaudio found. + +include(FindPackageHandleStandardArgs) +include(CheckFunctionExists) + +if(PORTAUDIO_INCLUDE_DIR) + # Already in cache, be silent + set(PORTAUDIO_FIND_QUIETLY TRUE) +endif(PORTAUDIO_INCLUDE_DIR) + +find_path(PORTAUDIO_INCLUDE_DIR portaudio.h) + +find_library(PORTAUDIO_LIBRARY NAMES portaudio) + +# handle the QUIETLY and REQUIRED arguments and set PORTAUDIO_FOUND to TRUE if +# all listed variables are TRUE +find_package_handle_standard_args(PORTAUDIO DEFAULT_MSG + PORTAUDIO_LIBRARY PORTAUDIO_INCLUDE_DIR) + +# Check if it's really a portaudio2 installation... +if(PORTAUDIO_FOUND) + set(CMAKE_REQUIRED_LIBRARIES ${PORTAUDIO_LIBRARY}) + check_function_exists(Pa_GetDefaultInputDevice HAVE_PA_GETDEFAULTINPUTDEVICE) + if (NOT HAVE_PA_GETDEFAULTINPUTDEVICE) + unset (PORTAUDIO_FOUND) + endif(NOT HAVE_PA_GETDEFAULTINPUTDEVICE) + set(CMAKE_REQUIRED_LIBRARIES "") +endif(PORTAUDIO_FOUND) + +mark_as_advanced(PORTAUDIO_LIBRARY PORTAUDIO_INCLUDE_DIR) diff --git a/cmake/FindReadline.cmake b/cmake/FindReadline.cmake new file mode 100644 index 0000000..ef06fea --- /dev/null +++ b/cmake/FindReadline.cmake @@ -0,0 +1,53 @@ + +IF (READLINE_INCLUDE_DIR) + # Already in cache, be silent + SET(READLINE_FIND_QUIETLY TRUE) +ENDIF (READLINE_INCLUDE_DIR) + +FIND_PATH(READLINE_INCLUDE_DIR readline.h PATH_SUFFIXES readline) + +FIND_LIBRARY(READLINE_LIBRARY NAMES readline) + +INCLUDE(FindPackageHandleStandardArgs) +FIND_PACKAGE_HANDLE_STANDARD_ARGS(READLINE DEFAULT_MSG + READLINE_LIBRARY READLINE_INCLUDE_DIR) + +MARK_AS_ADVANCED(READLINE_LIBRARY READLINE_INCLUDE_DIR) + +if(READLINE_FOUND) + set(CMAKE_REQUIRED_LIBRARIES "readline") + check_function_exists(rl_filename_completion_function + HAVE_RL_COMPLETION_FUNCTION) + # If linking did not work, we might have to link + # explicitely against libtermcap or libncurses + if(NOT HAVE_RL_COMPLETION_FUNCTION) + unset(READLINE_FOUND) + find_package(Termcap) + if(TERMCAP_FOUND) + set(CMAKE_REQUIRED_LIBRARIES "readline" "termcap") + check_function_exists(rl_filename_completion_function + HAVE_RL_COMPLETION_FUNCTION_TERMCAP) + endif(TERMCAP_FOUND) + if(HAVE_RL_COMPLETION_FUNCTION_TERMCAP) + set(READLINE_LIBRARY ${READLINE_LIBRARY} ${TERMCAP_LIBRARY}) + set(READLINE_FOUND TRUE) + else(HAVE_RL_COMPLETION_FUNCTION_TERMCAP) + find_package(Curses) + if(CURSES_FOUND) + if(CURSES_NCURSES_LIBRARY) + set(CMAKE_REQUIRED_LIBRARIES "readline" "ncurses") + else() + set(CMAKE_REQUIRED_LIBRARIES "readline" "curses") + endif() + check_function_exists(rl_filename_completion_function + HAVE_RL_COMPLETION_FUNCTION_CURSES) + if(HAVE_RL_COMPLETION_FUNCTION_CURSES) + set(READLINE_LIBRARY + ${READLINE_LIBRARY} ${CURSES_LIBRARIES}) + set(READLINE_FOUND TRUE) + endif(HAVE_RL_COMPLETION_FUNCTION_CURSES) + endif(CURSES_FOUND) + endif(HAVE_RL_COMPLETION_FUNCTION_TERMCAP) + endif(NOT HAVE_RL_COMPLETION_FUNCTION) + set(CMAKE_REQUIRED_LIBRARIES "") +endif(READLINE_FOUND) diff --git a/cmake/FindSDL2.cmake b/cmake/FindSDL2.cmake new file mode 100644 index 0000000..9bb2d8e --- /dev/null +++ b/cmake/FindSDL2.cmake @@ -0,0 +1,177 @@ +# Locate SDL2 library +# This module defines +# SDL2_LIBRARY, the name of the library to link against +# SDL2_FOUND, if false, do not try to link to SDL2 +# SDL2_INCLUDE_DIR, where to find SDL.h +# +# This module responds to the the flag: +# SDL2_BUILDING_LIBRARY +# If this is defined, then no SDL2main will be linked in because +# only applications need main(). +# Otherwise, it is assumed you are building an application and this +# module will attempt to locate and set the the proper link flags +# as part of the returned SDL2_LIBRARY variable. +# +# Don't forget to include SDLmain.h and SDLmain.m your project for the +# OS X framework based version. (Other versions link to -lSDL2main which +# this module will try to find on your behalf.) Also for OS X, this +# module will automatically add the -framework Cocoa on your behalf. +# +# +# Additional Note: If you see an empty SDL2_LIBRARY_TEMP in your configuration +# and no SDL2_LIBRARY, it means CMake did not find your SDL2 library +# (SDL2.dll, libsdl2.so, SDL2.framework, etc). +# Set SDL2_LIBRARY_TEMP to point to your SDL2 library, and configure again. +# Similarly, if you see an empty SDL2MAIN_LIBRARY, you should set this value +# as appropriate. These values are used to generate the final SDL2_LIBRARY +# variable, but when these values are unset, SDL2_LIBRARY does not get created. +# +# +# $SDL2DIR is an environment variable that would +# correspond to the ./configure --prefix=$SDL2DIR +# used in building SDL2. +# l.e.galup 9-20-02 +# +# Modified by Eric Wing. +# Added code to assist with automated building by using environmental variables +# and providing a more controlled/consistent search behavior. +# Added new modifications to recognize OS X frameworks and +# additional Unix paths (FreeBSD, etc). +# Also corrected the header search path to follow "proper" SDL guidelines. +# Added a search for SDL2main which is needed by some platforms. +# Added a search for threads which is needed by some platforms. +# Added needed compile switches for MinGW. +# +# On OSX, this will prefer the Framework version (if found) over others. +# People will have to manually change the cache values of +# SDL2_LIBRARY to override this selection or set the CMake environment +# CMAKE_INCLUDE_PATH to modify the search paths. +# +# Note that the header path has changed from SDL2/SDL.h to just SDL.h +# This needed to change because "proper" SDL convention +# is #include "SDL.h", not . This is done for portability +# reasons because not all systems place things in SDL2/ (see FreeBSD). + +#============================================================================= +# Copyright 2003-2009 Kitware, Inc. +# +# Distributed under the OSI-approved BSD License (the "License"); +# see http://www.cmake.org/cmake/project/license.html for details. +# +# This software is distributed WITHOUT ANY WARRANTY; without even the +# implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the License for more information. +#============================================================================= + +SET(SDL2_SEARCH_PATHS + ~/Library/Frameworks + /Library/Frameworks + /usr/local + /usr + /sw # Fink + /opt/local # DarwinPorts + /opt/csw # Blastwave + /opt +) + +FIND_PATH(SDL2_INCLUDE_DIR SDL_scancode.h + HINTS + $ENV{SDL2DIR} + PATH_SUFFIXES include/SDL2 include + PATHS ${SDL2_SEARCH_PATHS} +) + +FIND_LIBRARY(SDL2_LIBRARY_TEMP + NAMES SDL2 + HINTS + $ENV{SDL2DIR} + PATH_SUFFIXES lib64 lib + PATHS ${SDL2_SEARCH_PATHS} +) + +IF(NOT SDL2_BUILDING_LIBRARY) + IF(NOT ${SDL2_INCLUDE_DIR} MATCHES ".framework") + # Non-OS X framework versions expect you to also dynamically link to + # SDL2main. This is mainly for Windows and OS X. Other (Unix) platforms + # seem to provide SDL2main for compatibility even though they don't + # necessarily need it. + FIND_LIBRARY(SDL2MAIN_LIBRARY + NAMES SDL2main + HINTS + $ENV{SDL2DIR} + PATH_SUFFIXES lib64 lib + PATHS ${SDL2_SEARCH_PATHS} + ) + ENDIF(NOT ${SDL2_INCLUDE_DIR} MATCHES ".framework") +ENDIF(NOT SDL2_BUILDING_LIBRARY) + +# SDL2 may require threads on your system. +# The Apple build may not need an explicit flag because one of the +# frameworks may already provide it. +# But for non-OSX systems, I will use the CMake Threads package. +IF(NOT APPLE) + FIND_PACKAGE(Threads) +ENDIF(NOT APPLE) + +# MinGW needs an additional library, mwindows +# It's total link flags should look like -lmingw32 -lSDL2main -lSDL2 -lmwindows +# (Actually on second look, I think it only needs one of the m* libraries.) +IF(MINGW) + SET(MINGW32_LIBRARY mingw32 CACHE STRING "mwindows for MinGW") +ENDIF(MINGW) + +IF(SDL2_LIBRARY_TEMP) + # For SDL2main + IF(NOT SDL2_BUILDING_LIBRARY) + IF(SDL2MAIN_LIBRARY) + SET(SDL2_LIBRARY_TEMP ${SDL2MAIN_LIBRARY} ${SDL2_LIBRARY_TEMP}) + ENDIF(SDL2MAIN_LIBRARY) + ENDIF(NOT SDL2_BUILDING_LIBRARY) + + # For OS X, SDL2 uses Cocoa as a backend so it must link to Cocoa. + # CMake doesn't display the -framework Cocoa string in the UI even + # though it actually is there if I modify a pre-used variable. + # I think it has something to do with the CACHE STRING. + # So I use a temporary variable until the end so I can set the + # "real" variable in one-shot. + IF(APPLE) + SET(SDL2_LIBRARY_TEMP ${SDL2_LIBRARY_TEMP} "-framework Cocoa") + ENDIF(APPLE) + + # For threads, as mentioned Apple doesn't need this. + # In fact, there seems to be a problem if I used the Threads package + # and try using this line, so I'm just skipping it entirely for OS X. + IF(NOT APPLE) + SET(SDL2_LIBRARY_TEMP ${SDL2_LIBRARY_TEMP} ${CMAKE_THREAD_LIBS_INIT}) + ENDIF(NOT APPLE) + + # For MinGW library + IF(MINGW) + SET(SDL2_LIBRARY_TEMP ${MINGW32_LIBRARY} ${SDL2_LIBRARY_TEMP}) + ENDIF(MINGW) + + # Set the final string here so the GUI reflects the final state. + SET(SDL2_LIBRARY ${SDL2_LIBRARY_TEMP} CACHE STRING "Where the SDL2 Library can be found") + # Set the temp variable to INTERNAL so it is not seen in the CMake GUI + SET(SDL2_LIBRARY_TEMP "${SDL2_LIBRARY_TEMP}" CACHE INTERNAL "") +ENDIF(SDL2_LIBRARY_TEMP) + +if(SDL2_INCLUDE_DIR AND EXISTS "${SDL2_INCLUDE_DIR}/SDL_version.h") + file(STRINGS "${SDL2_INCLUDE_DIR}/SDL_version.h" SDL2_VERSION_MAJOR_LINE REGEX "^#define[ \t]+SDL_MAJOR_VERSION[ \t]+[0-9]+$") + file(STRINGS "${SDL2_INCLUDE_DIR}/SDL_version.h" SDL2_VERSION_MINOR_LINE REGEX "^#define[ \t]+SDL_MINOR_VERSION[ \t]+[0-9]+$") + file(STRINGS "${SDL2_INCLUDE_DIR}/SDL_version.h" SDL2_VERSION_PATCH_LINE REGEX "^#define[ \t]+SDL_PATCHLEVEL[ \t]+[0-9]+$") + string(REGEX REPLACE "^#define[ \t]+SDL_MAJOR_VERSION[ \t]+([0-9]+)$" "\\1" SDL2_VERSION_MAJOR "${SDL2_VERSION_MAJOR_LINE}") + string(REGEX REPLACE "^#define[ \t]+SDL_MINOR_VERSION[ \t]+([0-9]+)$" "\\1" SDL2_VERSION_MINOR "${SDL2_VERSION_MINOR_LINE}") + string(REGEX REPLACE "^#define[ \t]+SDL_PATCHLEVEL[ \t]+([0-9]+)$" "\\1" SDL2_VERSION_PATCH "${SDL2_VERSION_PATCH_LINE}") + set(SDL2_VERSION_STRING ${SDL2_VERSION_MAJOR}.${SDL2_VERSION_MINOR}.${SDL2_VERSION_PATCH}) + unset(SDL2_VERSION_MAJOR_LINE) + unset(SDL2_VERSION_MINOR_LINE) + unset(SDL2_VERSION_PATCH_LINE) + unset(SDL2_VERSION_MAJOR) + unset(SDL2_VERSION_MINOR) + unset(SDL2_VERSION_PATCH) +endif() + +INCLUDE(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(SDL2 REQUIRED_VARS SDL2_LIBRARY SDL2_INCLUDE_DIR) diff --git a/cmake/FindTermcap.cmake b/cmake/FindTermcap.cmake new file mode 100644 index 0000000..a8e22ff --- /dev/null +++ b/cmake/FindTermcap.cmake @@ -0,0 +1,14 @@ + +if(TERMCAP_INCLUDE_DIR) + # Already in cache, be silent + set(TERMCAP_FIND_QUIETLY TRUE) +endif(TERMCAP_INCLUDE_DIR) + +find_path(TERMCAP_INCLUDE_DIR termcap.h) +find_library(TERMCAP_LIBRARY NAMES termcap) + +include(FindPackageHandleStandardArgs) +find_package_handle_standard_args(TERMCAP DEFAULT_MSG + TERMCAP_LIBRARY TERMCAP_INCLUDE_DIR) + +mark_as_advanced(TERMCAP_LIBRARY TERMCAP_INCLUDE_DIR) diff --git a/cmake/Toolchain-mingw32-win64_32.cmake b/cmake/Toolchain-mingw32-win64_32.cmake new file mode 100644 index 0000000..0d9df48 --- /dev/null +++ b/cmake/Toolchain-mingw32-win64_32.cmake @@ -0,0 +1,48 @@ +# This Toolchain file is used to cross compile the Windows 32 bit +# version of Hatari under linux using mingw32 +# use : cmake -DCMAKE_TOOLCHAIN_FILE=Toolchain-mingw32-win64_32.cmake + + +# mingw32 versions of the different tools +# (change these depending on your system settings) +set (MINGW_EXE_PREFIX "i686-w64-mingw32") +set (MINGW_ROOT_PATH "mingw") + + +#-- Changes should not be required below this point + +# The name of the target operating system +SET(CMAKE_SYSTEM_NAME Windows) + +# Use the value provided to set mingw's tools +SET(CMAKE_C_COMPILER ${MINGW_EXE_PREFIX}-gcc) +SET(CMAKE_CXX_COMPILER ${MINGW_EXE_PREFIX}-g++) +SET(CMAKE_RC_COMPILER ${MINGW_EXE_PREFIX}-windres) + +# Base directory for the target environment +# We use the output from '-print-sysroot' +EXECUTE_PROCESS( + COMMAND ${CMAKE_C_COMPILER} -print-sysroot + OUTPUT_VARIABLE CMAKE_FIND_ROOT_PATH + OUTPUT_STRIP_TRAILING_WHITESPACE +) +# bin/, include/, lib/ and share/ are often in "mingw/" +# You might need to adjust the path for your system +SET(CMAKE_FIND_ROOT_PATH ${CMAKE_FIND_ROOT_PATH}/${MINGW_ROOT_PATH}) + +# Make the path absolute, a relative path could confuse some systems +get_filename_component ( CMAKE_FIND_ROOT_PATH ${CMAKE_FIND_ROOT_PATH} ABSOLUTE ) + +#message ( "MINGW_ROOT_PATH ${MINGW_ROOT_PATH} MINGW_EXE_PREFIX ${MINGW_EXE_PREFIX} CMAKE_FIND_ROOT_PATH ${CMAKE_FIND_ROOT_PATH}" ) + +# FindSDL.cmake doesn't search correctly in CMAKE_FIND_ROOT_PATH +# so we force SDLDIR here +set ( ENV{SDLDIR} ${CMAKE_FIND_ROOT_PATH}/include/SDL ) + +# Adjust the default behaviour of the FIND_XXX() commands: +# search headers and libraries in the target environment, search +# programs in the host environment +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + diff --git a/cmake/Toolchain-mingw32-win64_64.cmake b/cmake/Toolchain-mingw32-win64_64.cmake new file mode 100644 index 0000000..eadcb16 --- /dev/null +++ b/cmake/Toolchain-mingw32-win64_64.cmake @@ -0,0 +1,48 @@ +# This Toolchain file is used to cross compile the Windows 64 bit +# version of Hatari under linux using mingw32 +# use : cmake -DCMAKE_TOOLCHAIN_FILE=Toolchain-mingw32-win64_64.cmake + + +# mingw32 versions of the different tools +# (change these depending on your system settings) +set (MINGW_EXE_PREFIX "x86_64-w64-mingw32") +set (MINGW_ROOT_PATH "mingw") + + +#-- Changes should not be required below this point + +# The name of the target operating system +SET(CMAKE_SYSTEM_NAME Windows) + +# Use the value provided to set mingw's tools +SET(CMAKE_C_COMPILER ${MINGW_EXE_PREFIX}-gcc) +SET(CMAKE_CXX_COMPILER ${MINGW_EXE_PREFIX}-g++) +SET(CMAKE_RC_COMPILER ${MINGW_EXE_PREFIX}-windres) + +# Base directory for the target environment +# We use the output from '-print-sysroot' +EXECUTE_PROCESS( + COMMAND ${CMAKE_C_COMPILER} -print-sysroot + OUTPUT_VARIABLE CMAKE_FIND_ROOT_PATH + OUTPUT_STRIP_TRAILING_WHITESPACE +) +# bin/, include/, lib/ and share/ are often in "mingw/" +# You might need to adjust the path for your system +SET(CMAKE_FIND_ROOT_PATH ${CMAKE_FIND_ROOT_PATH}/${MINGW_ROOT_PATH}) + +# Make the path absolute, a relative path could confuse some systems +get_filename_component ( CMAKE_FIND_ROOT_PATH ${CMAKE_FIND_ROOT_PATH} ABSOLUTE ) + +#message ( "MINGW_ROOT_PATH ${MINGW_ROOT_PATH} MINGW_EXE_PREFIX ${MINGW_EXE_PREFIX} CMAKE_FIND_ROOT_PATH ${CMAKE_FIND_ROOT_PATH}" ) + +# FindSDL.cmake doesn't search correctly in CMAKE_FIND_ROOT_PATH +# so we force SDLDIR here +set ( ENV{SDLDIR} ${CMAKE_FIND_ROOT_PATH}/include/SDL ) + +# Adjust the default behaviour of the FIND_XXX() commands: +# search headers and libraries in the target environment, search +# programs in the host environment +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + diff --git a/cmake/Uninstall.cmake b/cmake/Uninstall.cmake new file mode 100644 index 0000000..a5695fc --- /dev/null +++ b/cmake/Uninstall.cmake @@ -0,0 +1,32 @@ +# +# "uninstall" target for reverting "make install" +# + +# cmake_policy(SET CMP0007 NEW) + +if (NOT EXISTS "${CMAKE_CURRENT_BINARY_DIR}/install_manifest.txt") + message(FATAL_ERROR "Cannot find install manifest: \"${CMAKE_CURRENT_BINARY_DIR}/install_manifest.txt\"") +endif() + +file(READ "${CMAKE_CURRENT_BINARY_DIR}/install_manifest.txt" files) +string(REGEX REPLACE "\n" ";" files "${files}") +# list(REVERSE files) +foreach (file ${files}) + message(STATUS "Uninstalling \"$ENV{DESTDIR}${file}\"") + if (EXISTS "$ENV{DESTDIR}${file}") + execute_process( + COMMAND ${CMAKE_COMMAND} -E remove "$ENV{DESTDIR}${file}" + OUTPUT_VARIABLE rm_out + RESULT_VARIABLE rm_retval + ) + if(NOT ${rm_retval} EQUAL 0) + message(FATAL_ERROR "Problem when removing \"$ENV{DESTDIR}${file}\"") + endif (NOT ${rm_retval} EQUAL 0) + else (EXISTS "$ENV{DESTDIR}${file}") + message(STATUS "File \"$ENV{DESTDIR}${file}\" does not exist.") + endif (EXISTS "$ENV{DESTDIR}${file}") +endforeach(file) + +execute_process( + COMMAND ${CMAKE_COMMAND} -E remove ${CMAKE_CURRENT_BINARY_DIR}/install_manifest.txt +) diff --git a/cmake/config-cmake.h b/cmake/config-cmake.h new file mode 100644 index 0000000..c7ff7c3 --- /dev/null +++ b/cmake/config-cmake.h @@ -0,0 +1,101 @@ +/* CMake config.h for Hatari */ + +/* Define if you have a PNG compatible library */ +#cmakedefine HAVE_LIBPNG 1 + +/* Define if you have a readline compatible library */ +#cmakedefine HAVE_LIBREADLINE 1 + +/* Define if you have the PortAudio library */ +#cmakedefine HAVE_PORTAUDIO 1 + +/* Define if you have the capsimage library */ +#cmakedefine HAVE_CAPSIMAGE 1 +#cmakedefine CAPSIMAGE_VERSION @CAPSIMAGE_VERSION@ + +/* Define if you have a X11 environment */ +#cmakedefine HAVE_X11 1 + +/* Define to 1 if you have the `z' library (-lz). */ +#cmakedefine HAVE_LIBZ 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_ZLIB_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_TERMIOS_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_GLOB_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_STRINGS_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_SDL_CONFIG_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_SYS_TIMES_H 1 + +/* Define to 1 if you have the `cfmakeraw' function. */ +#cmakedefine HAVE_CFMAKERAW 1 + +/* Define to 1 if you have the 'setenv' function. */ +#cmakedefine HAVE_SETENV 1 + +/* Define to 1 if you have the `select' function. */ +#cmakedefine HAVE_SELECT 1 + +/* Define to 1 if you have unix domain sockets */ +#cmakedefine HAVE_UNIX_DOMAIN_SOCKETS 1 + +/* Define to 1 if you have the 'posix_memalign' function. */ +#cmakedefine HAVE_POSIX_MEMALIGN 1 + +/* Define to 1 if you have the 'memalign' function. */ +#cmakedefine HAVE_MEMALIGN 1 + +/* Define to 1 if you have the 'gettimeofday' function. */ +#cmakedefine HAVE_GETTIMEOFDAY 1 + +/* Define to 1 if you have the 'nanosleep' function. */ +#cmakedefine HAVE_NANOSLEEP 1 + +/* Define to 1 if you have the 'alphasort' function. */ +#cmakedefine HAVE_ALPHASORT 1 + +/* Define to 1 if you have the 'scandir' function. */ +#cmakedefine HAVE_SCANDIR 1 + +/* Define to 1 if you have the 'statvfs' function. */ +#cmakedefine HAVE_STATVFS 1 + +/* Define to 1 if you have the 'fseeko' function. */ +#cmakedefine HAVE_FSEEKO 1 + +/* Define to 1 if you have the 'ftello' function. */ +#cmakedefine HAVE_FTELLO 1 + +/* Define to 1 if you have the 'flock' function. */ +#cmakedefine HAVE_FLOCK 1 + +/* Define to 1 if you have the 'strlcpy' function. */ +#cmakedefine HAVE_LIBC_STRLCPY 1 + +/* Define to 1 if you have the 'd_type' member in the 'dirent' struct */ +#cmakedefine HAVE_DIRENT_D_TYPE 1 + +/* Relative path from bindir to datadir */ +#define BIN2DATADIR "@BIN2DATADIR@" + +/* Define to 1 to enable DSP 56k emulation for Falcon mode */ +#cmakedefine ENABLE_DSP_EMU 1 + +/* Define to 1 to enable WINUAE cpu */ +#cmakedefine ENABLE_WINUAE_CPU 1 + +/* Define to 1 to use less memory - at the expense of emulation speed */ +#cmakedefine ENABLE_SMALL_MEM 1 + +/* Define to 1 to enable trace logs - undefine to slightly increase speed */ +#cmakedefine ENABLE_TRACING 1 diff --git a/config.h b/config.h new file mode 100644 index 0000000..394700f --- /dev/null +++ b/config.h @@ -0,0 +1,86 @@ +/* Default config.h for Hatari */ + +/* Define to 1 if you have the header file, and it defines `DIR'. */ +//#define HAVE_DIRENT_H 1 + +/* Define if you have a readline compatible library */ +#undef HAVE_LIBREADLINE + +/* Define to 1 if you have the `z' library (-lz). */ +#define HAVE_LIBZ 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_ZLIB_H 1 + +/* Define to 1 if you have the header file. */ +//#if defined(WIN32) +# undef HAVE_TERMIOS_H +//#else +//# define HAVE_TERMIOS_H 1 +//#endif + +/* Define to 1 if you have the header file. */ +//#if defined(WIN32) +# undef HAVE_GLOB_H +//#else +//# define HAVE_GLOB_H 1 +//#endif + +/* Define to 1 if you have the header file. */ +//#if defined(__CEGCC__) +# undef HAVE_STRINGS_H +//#else +//# define HAVE_STRINGS_H 1 +//#endif + +/* Define to 1 if you have the `strcasecmp' function. */ +#define HAVE_STRCASECMP 1 + +/* Define to 1 if you have the `strncasecmp' function. */ +#define HAVE_STRNCASECMP 1 + +/* Define to 1 if you have the `cfmakeraw' function. */ +# undef HAVE_CFMAKERAW + +/* Define to 1 if you have the 'setenv' function. */ +//#if defined(WIN32) || (defined(__sun) && defined(__SVR4)) +# undef HAVE_SETENV +//#else +//# define HAVE_SETENV 1 +//#endif + +/* Define to 1 if you have unix domain sockets */ +//#if defined(WIN32) || defined(__CEGCC__) +# undef HAVE_UNIX_DOMAIN_SOCKETS +//#else +//# define HAVE_UNIX_DOMAIN_SOCKETS 1 +//#endif + +/* Relative path from bindir to datadir */ +#define BIN2DATADIR "/apps/hatari" + +/* configuration file path */ +#define CONFDIR "/apps/hatari" + +/* games folder */ +#define DATADIR "/hatari" + +/* Define to 1 to use less memory - at the expense of emulation speed */ +//#if defined(__CEGCC__) +#define ENABLE_SMALL_MEM 1 +//#else +//# undef ENABLE_SMALL_MEM +//#endif + + +//#define ENABLE_WINUAE_CPU 1 + +/* Define to the full name of this package. */ +#define PACKAGE_NAME "hatari" + +/* Define to the full name and version of this package. */ +#define PACKAGE_STRING "hatari CVS" + +/* Define to the version of this package. */ +#define PACKAGE_VERSION "CVS" + diff --git a/configure b/configure new file mode 100755 index 0000000..6d004b9 --- /dev/null +++ b/configure @@ -0,0 +1,115 @@ +#!/bin/sh + +# NOTE: this is a simple script wrapper around the cmake command line tools, +# for those used to the autotools configure script conventions + +if ! which cmake > /dev/null; then + echo "ERROR: You need the 'cmake' program to configure the Hatari build process." + echo "Please install 'cmake' first, then try again." + exit 1 +fi + +print_help() +{ + echo "This is a simple configure script wrapper around cmake build system." + echo "Parameters are:" + echo " --prefix= Set the install prefix to path" + echo " --enable-debug Enable debug (non-optimized) build" + echo " --enable-small-mem Use less memory - at the expense of emulation speed" + echo " --disable-dsp Disable DSP emulation for Falcon mode." + echo " --disable-tracing Disable tracing messages for debugging" + echo " --enable-winuae-cpu Enable WinUAE CPU core (experimental!)" + echo " --disable-osx-bundle Disable application bundling on Mac OS X" + echo " --enable-sdl2 Compile with libsdl 2.0 instead of 1.2" + echo " --cross-compile-win64_32 Build the 32 bit Windows version under linux using mingw-w64" + echo " --cross-compile-win64_64 Build the 64 bit Windows version under linux using mingw-w64" + echo + echo "Please run cmake directly for full control over the build." + echo +} + +cmake_args="" +build_type="Release" + +while [ $# -gt 0 ] +do + preq=${1%=*} # get part before = + case $preq + in + --help) + print_help + exit 0 + ;; + --prefix) + prefix=${1##*=} # get part after = + cmake_args="$cmake_args -DCMAKE_INSTALL_PREFIX:PATH=$prefix" + ;; + --enable-debug) + build_type="Debug" + cmake_args="$cmake_args -DCMAKE_BUILD_TYPE:STRING=Debug" + ;; + --disable-debug) + build_type="Release" + cmake_args="$cmake_args -DCMAKE_BUILD_TYPE:STRING=Release" + ;; + --enable-dsp) + cmake_args="$cmake_args -DENABLE_DSP_EMU:BOOL=1" + ;; + --disable-dsp) + cmake_args="$cmake_args -DENABLE_DSP_EMU:BOOL=0" + ;; + --enable-tracing) + cmake_args="$cmake_args -DENABLE_TRACING:BOOL=1" + ;; + --disable-tracing) + cmake_args="$cmake_args -DENABLE_TRACING:BOOL=0" + ;; + --enable-small-mem) + cmake_args="$cmake_args -DENABLE_SMALL_MEM:BOOL=1" + ;; + --disable-small-mem) + cmake_args="$cmake_args -DENABLE_SMALL_MEM:BOOL=0" + ;; + --enable-winuae-cpu) + cmake_args="$cmake_args -DENABLE_WINUAE_CPU:BOOL=1" + ;; + --disable-winuae-cpu) + cmake_args="$cmake_args -DENABLE_WINUAE_CPU:BOOL=0" + ;; + --enable-osx-bundle) + cmake_args="$cmake_args -DENABLE_OSX_BUNDLE:BOOL=1" + ;; + --disable-osx-bundle) + cmake_args="$cmake_args -DENABLE_OSX_BUNDLE:BOOL=0" + ;; + --enable-sdl2) + cmake_args="$cmake_args -DENABLE_SDL2:BOOL=1" + ;; + --disable-sdl2) + cmake_args="$cmake_args -DENABLE_SDL2:BOOL=0" + ;; + --cross-compile-win64_32) + cmake_args="$cmake_args -DCMAKE_TOOLCHAIN_FILE=cmake/Toolchain-mingw32-win64_32.cmake" + ;; + --cross-compile-win64_64) + cmake_args="$cmake_args -DCMAKE_TOOLCHAIN_FILE=cmake/Toolchain-mingw32-win64_64.cmake" + ;; + *) + echo "Invalid argument: $preq" + echo "Run $0 --help for a list of valid parameters." + exit 2 + ;; + esac + shift 1 +done + +# remove previous cmake's cache +rm -f `dirname $0`/CMakeCache.txt +rm -rf `dirname $0`/CMakeFiles/ + +cmake `dirname $0` $cmake_args || exit 1 + +echo +echo "Now you must type: make; make install" +echo "to actually build and install the software" +echo diff --git a/doc/CMakeLists.txt b/doc/CMakeLists.txt new file mode 100644 index 0000000..d6f1e3b --- /dev/null +++ b/doc/CMakeLists.txt @@ -0,0 +1,18 @@ + +INSTALL(FILES authors.txt emutos.txt keymap-sample.txt memory-usage.txt + midi-linux.txt release-notes.txt todo.txt + DESTINATION ${DOCDIR}) + +INSTALL(FILES compatibility.html manual.html + DESTINATION ${DOCDIR}) + +INSTALL(DIRECTORY images + DESTINATION ${DOCDIR}) + +# if(UNIX) + add_custom_target(manpages ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/hatari.1.gz) + add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/hatari.1.gz + COMMAND gzip -c -9 ${CMAKE_CURRENT_SOURCE_DIR}/hatari.1 > ${CMAKE_CURRENT_BINARY_DIR}/hatari.1.gz + DEPENDS hatari.1) + INSTALL(FILES ${CMAKE_CURRENT_BINARY_DIR}/hatari.1.gz DESTINATION ${MANDIR}) +# endif(UNIX) diff --git a/doc/authors.txt b/doc/authors.txt new file mode 100644 index 0000000..b63d474 --- /dev/null +++ b/doc/authors.txt @@ -0,0 +1,198 @@ + + Active Hatari developers: + ------------------------- + +- Nicolas Pomarede : Project admin, + improving CPU, video, sound, IKBD and floppy emulation. + +- Thomas Huth : Project initiator and + admin, currently more or less in hibernation mode. + +- Eero Tamminen : Speed improvements & code + cleanup, small parts of the STE emulation, Python CLI, UI & TOS + tester + Hatari window embedding & remote control API, pause & auto + frameskip support, statusbar & overlay led, conditional breakpoints + and other debugger features, GEMDOS HD emulation improvements, PNG + saving. + +- Laurent Sallafranque: Many fixes and speedups to DSP emulation, + DSP debugging support, crossbar emulation, falcon microphone + emulation, STE LMC1992/microwire emulation, Videl emulation. + + + Contributors: + ------------- + +Following people contributed code or patches to this projects and/or +helped to find bugs in Hatari (listed in random order - and if someone +is missing here, please remind me!): + +- Jean-Baptiste Berlioz : Cycle accurate + Blitter emulation. + +- David Savinkoff : More accurate printer emulation, LMC1992 emulation + patches, IIR/Low Pass filters and many improvements to the YM2149 model + to get a close emulation of the circuit used to merge and filter the + output of the 3 YM2149 voices. + Great work to enhance the sound quality. + +- Matthias Arndt : Wrote the original version + of the Hatari user manual, fixed the printer emulation functions. + +- Sébastien Molines : Wrote the main part of the + Mac OS X GUI of Hatari. + +- Marco Herrn : Wrote the initial version of the + "man" page of Hatari and maintained the Hatari Debian packages until + Hatari was included into Debian. + +- Sven de Marothy : Screenshot functions, the initial CLI debugger, + the ACSI emulation and added support for ZIPed and GZIPed disk images. + +- Emmanuel Anne : Contributed lots of patches, + RTC emulation. + +- Tuduri Benoît : French man-page, + support for Doxygen. + +- Markus Oberhumer : fixed a problem with ZIPed disk images, routine for + loading the configuration file from the $HOME directory. + +- Philippe Gerin : Fixed a bug in the CPU core (bus errors problem). + +- Steve Kemp : Found some possible buffer overflows. + +- George Nakos : Helped to track down a bug in the GEMDOS HD emulation. + +- Pieter van der Meer : Traced a bug in the VIDEL emulation. + +- Patrice Mandin : Some improvements of the autoconf build system files, + original author of the DSP emulation core. + +- Martin Doering : Code for compiling the font data into the executable + and some other ideas for cleaning up the source code. + +- Matthias Alles : He initiated the port of Hatari to MiNT and helped + with a lot of technical questions about the ST. + +- Ventzislav Tzvetkov : Joystick closing patch, Hatari for AmigaOS. + +- "Jo" (?) : Patches for compiling Hatari on a 64-bit Alpha machine. + +- Stefan Berndtsson : Patches to get Hatari + running on big endian machines. + +- Anatol Paruntik (?) : Patches for compiling Hatari on QNX. + +- Claus Windeler : BeOS adaption. + +- James Lampard : Adapted Hatari to Acorn RISC OS machines. + +- Mark Keates : Patches for compiling Hatari with MinGW. + +- Fredrik Noring : Tracked down a bug in the blitter emulation and a + bug in the PSG shadow register emulation. + +- Volker Seebode: Fix to ASCI emulation to get other than AHDI drivers + working. + +- Cyprian Konador: Found some bugs in the blitter cycles emulation, + duochrome and samplehold modes for TT video emulation. + +- Jerome Vernet: Some updates to the OS X Xcode project file and OS X + GUI, supplied a french keymapping file for OS X. + +- Kenneth Kaufman: MS VC6 & C++ compiler and multiple GEMDOS HD + partition support patches. + +- Uwe Seimet: IDE emulation improvements and GEMDOS HD emulation + improvement suggestions. + +- Anders Eriksson (Evil/DHS): Helped improving STE's emulation by + running many tests programs and providing the source code for some + non-working demos. + +- Markus Fritze: New m68k disassembler with more Motorola like syntax + and options for controlling how the output looks. + +- Deniz Turkoglu: Patches for the Max OS X GUI. + +- Markus Heiden: SCSI class 1 (ICD) command support for drives > 1 GB + +- nash67: tested hundreds (!) of games from various CD compilations + and reported the non working ones on atari-forum.com. Huge thanks for + that tedious work, it helped tracking down some less common cases + not used in demos (keyboard, joystick, FDC, tos, ...). + +- Gilles Fetis: fixes to MMU emulation (from NeXT emulator project + using Hatari code). + +- Peter Putnik (Petari, AtariZoll): for helping with tracking the cause + of the crash in Microprose Golf (FDC emulation). Also wrote some useful tools + to handle floppies (flofor, floimg), as well as opcovat.tos to report + valid/invalid opcodes with a real CPU and under emulation by testing all possible + opcode combinations. + +- Jean Louis Guerin (DrCoolZic): for the 'Panzer' program, very useful to test + some FDC behaviours and timings on real hardware and to compare them + with the emulated system. Also wrote some nice docs on WD1772 + and methods commonly used for games' protections. + +- Christer Solskogen: for setting up an automatic build script on his site, + with up to date binary versions for Linux and Windows in 32 and 64 bit mode. + Very useful for end users wishing to try the devel version of Hatari, and + lots of interesting build logs too for various cpu architectures. + See http://antarctica.no/~hatari/latest + +- Max Böhm: host <-> Atari filename encoding conversion routines and + related changes needed to gemdos.c. + + + Code from other projects + ------------------------ + +As a true open source project, Hatari also uses some code from other +projects which we would like to acknowledge here: + +- Most of the original ST hardware emulation comes from the WinSTon + source code which has been written by Paul Bates. + (http://www.sourceforge.net/projects/winston/) + +- The original CPU core has been taken from UAE which has been written + by Bernd Schmidt and others. (http://uae.coresystems.de/) + +- The new alternative CPU core has been taken from WinUAE which is + maintained by Toni Wilen. Huge thanks to Toni for accepting ideas + and patches not specific to Amiga emulation, as well as keeping on + improving the accuracy of 68000/20/30 CPU. (http://www.winuae.net/) + +- Some parts have been taken from the emulator STonX that has been + written by Marinos Yannikos and Martin Griffiths. + (http://stonx.sourceforge.net/) + +- A lot of code (e.g. the scancode keyboard mapping, Videl, NVRAM and + DSP emulation) has been adapted from the sources of the emulator + Aranym. (http://aranym.atari.org/) + +- The code for decompressing ZIP files (unzip.c) has been taken from + Gilles Vollant's miniunzip program. + (http://www.winimage.com/zLibDll/unzip.html) + +- The routines for saving and loading the ASCII configuration file + (cfgopts.c) have originally been written by Jeffry J. Brickley. + +- The new sound core uses (or used) some code/ideas from the following GPL + projects : + * 5 bits volume table and 16*16*16 combinations of all volume are + from Sc68 by Benjamin Gerard. + * 4 bits to 5 bits volume interpolation from 16*16*16 to 32*32*32 + are from YM blep synthesis by Antti Lankila. + * Since Hatari 1.7, volume table based on measures by Paulo Simoes + +- The IDE hard disk emulation is based on code from QEMU. + (http://www.qemu.org/) + +- The MMU emulation for the 68030 has been taken from the NeXT emulator + Previous (thanks to Andreas Grabher!). Since Hatari 1.9, this is now + taken from WinUAE which uses the same code base. + diff --git a/doc/changelog.txt b/doc/changelog.txt new file mode 100644 index 0000000..7d1519b --- /dev/null +++ b/doc/changelog.txt @@ -0,0 +1,35504 @@ +2015-09-10 : *** Version 1.9.0 *** + +2015-09-10 Nicolas Pomarede + + * doc/compatibility.html, doc/doxygen/Doxyfile, doc/manual.html, doc + /release-notes.txt, hatari.spec, readme.txt, src/gui-osx/Info- + Hatari.plist, src/includes/version.h, src/memorySnapShot.c: + New release 1.9.0, increase version in corresponding files + [f89638264376] [tip] + +2015-09-09 Nicolas Pomarede + + * src/cpu/newcpu.c: + Disable debug for 68030's cache + [196f9d3877d0] + +2015-09-08 Eero Tamminen + + * doc/authors.txt: + authors.txt update from Uwe + [4fa5a272ae68] + +2015-08-28 Eero Tamminen + + * src/falcon/nvram.c, src/falcon/nvram.h, src/falcon/videl.c: + Improved NVRAM logging + comment fix + [be7c2f9f4594] + +2015-08-27 Nicolas Pomarede + + * doc/release-notes.txt, src/blitter.c: + When blitter transfer ends, we must also clear hog bit, not just + busy bit (fix BLTBENCH.TOS and BBENCH3.TOS by Franck B on www.atari- + forum.com) + [86e2caf1d1a5] + +2015-08-26 Eero Tamminen + + * src/falcon/videl.c: + Fix crash with bad Videl reg values + + For some reason Falcon screen width is now always zero ($ff8210 is + set to 0x0c00 at TOS4 boot and as this value is ORed with 0x3ff to + get sensible values -> zero width). + + Videl Zoom code will then allocate zero sized buffer and tries to + write there at least 16 values which naturally segfaults. -> Added + check and Videl trace logging to catch & prevent that. + + The check earlier catches cases where screen size + borders is too + small, added logging there too and updated comments. + [d1b01a6bf36f] + +2015-08-18 Nicolas Pomarede + + * src/video.c: + On STE, fix a rare case when reading video counter at end of line + and $FF820F is != 0 + [00c86eb22297] + +2015-08-12 Eero Tamminen + + * doc/compatibility.html, doc/release-notes.txt: + Update compatibility notes / regressions + [e5fe9faa83b8] + +2015-08-12 Nicolas Pomarede + + * src/cpu/gencpu.c, src/cpu/newcpu.c: + Small 68020/30 prefetch update (from WinUAE 3.2.0 b7) + [ab6b0d0ce386] + +2015-08-12 Eero Tamminen + + * src/gui-sdl/dlgHalt.c: + Keyboard shortcuts to Halt dialog + [64b9afcd4e69] + +2015-08-07 Eero Tamminen + + * doc/compatibility.html, doc/emutos.txt: + Update compatibility docs + [f27b0711f92b] + +2015-08-04 Nicolas Pomarede + + * src/cpu/cpummu.c, src/cpu/cpummu.h, src/cpu/newcpu.c: + Fix MMU ATC flag for 68040/68060 (from WinUAE 3.2.0 b3) + [56f8d28da7bc] + +2015-08-02 Nicolas Pomarede + + * doc/release-notes.txt: + Add more changes to WinUAE's CPU release notes + [b241b6b4c051] + + * src/cpu/build68k.c, src/cpu/cpu_prefetch.h, src/cpu/gencpu.c, + src/cpu/newcpu.c, src/cpu/newcpu.h: + Better handling of the 68020/30's prefetch pipeline in CE mode (from + WinUAE 3.2.0 b7) When the 68020/30 prefetches 3 words for the next + instructions, it will stop prefetching when one of the prefetched + word can trigger a branch (bsr, bra, jmp, ...). This removes + unnecessary bus accesses by not prefetching code after a branch. + Since less words can be prefetched, this will impact the state of + the instruction cache. (Fix the Falcon game Tautology II by + Reservoir Gods when using 68030 in cycle exact mode with + instruction/data caches (music replay uses self modified init code)) + [c5d5a2da7181] + + * doc/authors.txt: + Add more credits for Toni Wilen / WinUAE + [921d9c8bf7be] + +2015-07-29 Nicolas Pomarede + + * doc/release-notes.txt: + Update doc for War Heli + [51e6ae64a5f0] + + * src/uae-cpu/gencpu.c: + For old UAE CPU, add refill_prefetch for i_Bcc (fix the protection + in War Heli) + [cb666724984a] + + * src/uae-cpu/newcpu.c: + For old UAE CPU, add a special case to correct the stacked PC when + an address error happens during a move.l dx,(ax) (fix the protection + in War Heli) + [d81edd421446] + + * src/uae-cpu/gencpu.c: + For old UAE CPU, correctly set last_writeaccess_for_exception_3 to 0 + (read) or 1 (write) (fix stack frame for War Heli) + [3dbfcc95bf1c] + +2015-07-05 Eero Tamminen + + * doc/compatibility.html: + Update chainz/jewelz notes after Nicolas fix + [6b739ea6352a] + +2015-07-04 Nicolas Pomarede + + * src/cpu/newcpu.c: + For WinUAE CPU, 68010 cpu was not correctly handled in the main cpu + loop + [5c0832d7d899] + +2015-07-04 Thomas Huth + + * src/psg.c: + Fix comment about PSG port A bit 3 + [b1ddf8a3b706] + +2015-07-03 Nicolas Pomarede + + * src/falcon/dsp_core.h: + In DSP emulation, remove useless 'volatile' keywords Those are not + needed since DSP doesn't run in a separate thread anymore + [de916d772ef2] + +2015-07-02 Eero Tamminen + + * doc/compatibility.html: + Minor compatibility updates + + - Consistent terminology for WinUAE hangs + - As some Capy versions have problems on TT and neither the program + nor its documentation have version number for identification, move + Capy under Falcon + - Updates to few WinUAE issues + [38c58edbf86b] + +2015-07-01 Nicolas Pomarede + + * doc/release-notes.txt: + Add DSP changes to release notes + [97f82fa232b5] + + * src/falcon/dsp.c, src/falcon/dsp_core.c, src/falcon/dsp_core.h: + Improve the DSP's HREQ signal, it was not correctly handled to work + with WinUAE CPU core + [4704feb5ea9d] + + * src/cpu/newcpu.c: + debug log + [186460b2dad8] + + * src/cpu/CMakeLists.txt: + Add some rules to silence some WinUAE cpu warnings + [e0a93fd2820b] + + * src/cpu/debug.h: + Add missing prototype + [5db0e962d27a] + +2015-06-30 Eero Tamminen + + * doc/compatibility.html: + Fix ChainZ/JewelZ RAM reqs, update few others + [1c14ea97750a] + + * src/debug/profilecpu.c: + Increase profiler data cache hits max + + Teknoballs Falcon game had even more hits than cases I had tested + before. + [e0f98be8ca92] + +2015-06-30 Nicolas Pomarede + + * src/cpu/gencpu.c, src/cpu/newcpu.c: + For WinUAE CPU, fix a bug in movep, pack and unpack when 68030 data + cache is enabled (fix the game Corsair by Impulse when running in + cycle exact mode with data cache) + [40461e70f59c] + +2015-06-29 Nicolas Pomarede + + * src/cpu/newcpu.c: + Remove WinUAE's specific code that conflicts with Hatari's DSP + interrupt SPCFLAG_TRAP had the same value as SPCFLAG_DSP, which + triggered unwanted exception(3) + [283e62ea16fc] + + * src/blitter.c, src/cpu/memory.c, src/cpu/memory.h, + src/includes/stMemory.h, src/stMemory.c, src/uae-cpu/memory.c, src + /uae-cpu/memory.h: + Blitter should not cause a bus error exception when accessing + regions that cause a bus error for the CPU Fix bad blitter accesses + in the games Chainz and Jewelz by Paradize + [e5ad66def36c] + + * src/cpu/newcpu.c: + Remove old/unused code for 68030 data cache + [4cb229caf61a] + + * doc/release-notes.txt: + Add note about fix for SDL UI caused by the file selector + [c2c7bfb2337e] + +2015-06-29 Eero Tamminen + + * doc/compatibility.html: + Add compat links for few Falcon games + [2575adbed54d] + +2015-06-28 Nicolas Pomarede + + * src/m68000.c: + Add pairing for ABCD/SBCD and DBcc + [ae864f71ccd3] + +2015-06-28 Eero Tamminen + + * src/debug/profilecpu.c: + reduce max d-hits + + Only half needed after Nicolas' d-cache counting fix. + [dc4cecd0e782] + +2015-06-28 Thomas Huth + + * doc/compatibility.html: + Fix URLs for valid HTML + [ed273e672304] + +2015-06-28 Nicolas Pomarede + + * src/gui-sdl/dlgAbout.c, src/gui-sdl/dlgAlert.c, src/gui- + sdl/dlgDevice.c, src/gui-sdl/dlgFileSelect.c, src/gui- + sdl/dlgFloppy.c, src/gui-sdl/dlgHalt.c, src/gui-sdl/dlgHardDisk.c, + src/gui-sdl/dlgJoystick.c, src/gui-sdl/dlgKeyboard.c, src/gui- + sdl/dlgMain.c, src/gui-sdl/dlgMemory.c, src/gui-sdl/dlgNewDisk.c, + src/gui-sdl/dlgRom.c, src/gui-sdl/dlgScreen.c, src/gui- + sdl/dlgSound.c, src/gui-sdl/dlgSystem.c, src/gui-sdl/sdlgui.c, + src/includes/sdlgui.h: + Fix a possible out of bound access in the SDL UI and the file + selector The fileselector maintains the value of current_object to + keep track of the scrollbar position, but in all other cases + current_object should be reset before displaying a new dialog (else + some dialogs will behave as if exiting automatically) + [009b993e57b3] + +2015-06-28 Eero Tamminen + + * tests/tosboot/readme.txt, tests/tosboot/tos_tester.py: + Add TT-RAM support to TOS bootup tester + + Relies on hconsole version that can tell whether Hatari is WinUAE + version. + [cc27da2001fc] + + * tests/tosboot/tos_tester.py: + Fix error message arg + + ...by making size a local variable. + [d41163f9d600] + + * tests/tosboot/tos_tester.py: + Better method names + [1bf7089c149a] + +2015-06-27 Eero Tamminen + + * tests/tosboot/tos_tester.py: + misc tos tester updates + + - disable mouse warping + - increase TOS v2 timeouts, earlier ones weren't enough with VDI mode + and lots of memory + - update copyright accordingly + [5d1e852dff8a] + +2015-06-26 Eero Tamminen + + * src/debug/profilecpu.c: + Fix compiler warning with olduae CPU core + [a097778ccc34] + +2015-06-25 Eero Tamminen + + * tools/hconsole/hconsole.py: + Check whether Hatari instance is WinUAE CPU core one + + This will be used in next TOS boot tester commit + [8d724798059b] + +2015-06-24 Eero Tamminen + + * src/tos.c: + Allow 32-addressing only for systems supporting it + + Previous code checked just for TT & Falcon machine types, but TOS v2 + supports TT, but not 32-bit addressing. So, check also TOS version. + [6cd639704349] + + * tests/tosboot/disk/ahcc-gemdos, tests/tosboot/disk/ahcc-minimal: + EmuCON startup has gotten slower, compensate + [48d8b150d3ff] + +2015-06-23 Nicolas Pomarede + + * src/gui-osx/AlertHooks.h, src/gui- + osx/English.lproj/InfoPlist.strings, src/gui- + osx/English.lproj/SDLMain.nib/designable.nib, src/gui- + osx/English.lproj/SDLMain.nib/keyedobjects.nib, src/gui- + osx/English.lproj/SDLMain.xib, src/gui- + osx/French.lproj/InfoPlist.strings, src/gui- + osx/French.lproj/SDLMain.nib/designable.nib, src/gui- + osx/French.lproj/SDLMain.nib/keyedobjects.nib, src/gui- + osx/French.lproj/SDLMain.xib, src/gui-osx/Info-Hatari Winuae.plist, + src/gui-osx/Info-Hatari.plist, src/gui-osx/PrefsController.h, src + /gui-osx/PrefsController.m: + Update OSX UI (changes by Jerome Vernet) + [a9bc04038ce6] + +2015-06-22 Nicolas Pomarede + + * doc/manual.html: + Update a few items in the manual + [2c1915231311] + + * src/debug/profilecpu.c: + Don't shift cycles by nCpuFreqShift when profiling CPU Cycles should + not be shifted, else we don't get the same values as displayed when + using --trace cpu_disasm + [67824e87dc4e] + +2015-06-21 Nicolas Pomarede + + * doc/emutos.txt: + EmuTOS 0.9.4 is included with Hatari 1.9.0 + [c355dc4af8b3] + +2015-06-19 Nicolas Pomarede + + * src/video.c: + For now, don't use STE's LineWidth when reading video counter in + high res + [97de55da9132] + + * doc/release-notes.txt: + Update release notes + [a5a28a79b7e3] + + * src/video.c: + For STF/STE, handle a special/simplified case when reading video + pointer in high res (fix high res sync protection in the demo 'My + Socks Are Weapons' by 'Legacy') + [0a27e6c8bd5a] + +2015-06-17 Nicolas Pomarede + + * src/cpu/newcpu.c: + For WinUAE CPU, fix write to 68030 data cache for misaligned long + word + [a632893c2cbb] + +2015-06-15 Nicolas Pomarede + + * src/cpu/newcpu.c: + For WinUAE CPU, fix write to 68030 data cache when Write Allocate=0 + [11bb50fa507f] + +2015-06-15 Eero Tamminen + + * doc/compatibility.html, doc/todo.txt: + Update Falcon compatibility notes + + - Aazohm needs 8MB + - update auto-start notes + - use auto-start spelling consistently + [d72e45998bd2] + +2015-06-14 Eero Tamminen + + * doc/compatibility.html: + Falcon compatibility doc updates + Voxel demo entry + [dae634098bcb] + +2015-06-14 Nicolas Pomarede + + * src/uae-cpu/newcpu.c: + Don't call Dialog_HaltDlg() directly, call it from cpu_halt() + [1a2c5455a57b] + +2015-06-13 Eero Tamminen + + * doc/compatibility.html, doc/todo.txt: + Falcon compatibility doc updates + [fb8bfdf825a6] + + * src/gui-sdl/dlgScreen.c: + remove rendundant macro + [834ce9230511] + + * doc/release-notes.txt, src/CMakeLists.txt, src/cpu/newcpu.c, src + /gui-sdl/CMakeLists.txt, src/gui-sdl/dlgHalt.c, + src/includes/dialog.h, src/uae-cpu/newcpu.c: + Fix problems with CPU halt dialog + + Problems: + + * Some programs (like Falcon DryEgg with <4MB RAM) can get emulation + into a state where warm reset doesn't fix the issue and you get halt + dialog immediately again. + + * Worse problem is that if user clicks to Hatari close button when + this dialog is open, dialog gets canceled which invokes console + debugger. If user didn't run Hatari from console, Hatari is + completely non-responsive after that. + + If user continues emulation or tries to quit it from debugger, he + just gets back to debugger (due to bQuitProgram state canceling + dialog). Only way to exit from debugger is to cold reset emulation + from it, but user doesn't know that. + + Fix: + + * Create separate dialog with more buttons from which user can warm + and cold reset emulation, invoke debugger or quit Hatari. + + * Check SDLGUI_QUIT and bQuitProgram being already set, and if they + are, cold reset emulation so that Hatari gets back to emulation main + loop and can quit itself. + [8cf52d2503e9] + +2015-06-11 Eero Tamminen + + * doc/release-notes.txt, src/configuration.c, src/main.c: + fix: default IDs for joysticks were invalid + + Joysticks are verified only in SDL GUI joystick dialog. As result, + statusbar information and switching joystick types through keyboard + shortcuts could show joystick being enabled although it was mapped + to non-existing one. + + Fixes to joystick defaults in configuration.c: + - if there are no joysticks, don't enable joystick + - limit default joystick ID assignments to valid values + [94856b97b69e] + +2015-06-11 Nicolas Pomarede + + * src/cpu/custom.h, src/cpu/debug.c, src/cpu/options_cpu.h, + src/cpu/winuae_readme.txt: + Update remaining parts of WinUAE cpu core from 3.1.0 b16 to 3.1.0 + final + [6184cf97bacd] + +2015-06-10 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + fix: no prefetch interrupt 2 is first one was a single word + instruction + [ef7ac6c24efe] + +2015-06-10 Eero Tamminen + + * doc/hatari.1, doc/release-notes.txt, src/configuration.c, src/gui- + sdl/dlgHardDisk.c, src/includes/configuration.h, src/includes/str.h, + src/options.c, src/str.c: + 8-bit file name Atari <-> host charset conversion option + + - both command line and SDL GUI options + - there are now so many disk options that I also split floppy and + harddisk options under their own headings in --help and in manual + page + [75285830e52b] + +2015-06-09 Eero Tamminen + + * doc/compatibility.html, doc/todo.txt: + updates to Falcon games compatibility + + More updates to follow after I've had time to test them... + [cdb25779f25f] + +2015-06-08 Nicolas Pomarede + + * src/cpu/newcpu.c: + For WinUAE CPU, correctly invalidates entries in data cache during a + 'write miss' + [c09e046fe65b] + +2015-06-06 Nicolas Pomarede + + * src/gemdos.c, src/includes/m68000.h, src/m68000.c, src/stMemory.c: + Add functions to flush instructions cache, data cache, or both + [a7c02de3c842] + +2015-06-05 Eero Tamminen + + * doc/compatibility.html, doc/todo.txt: + update docs: packers are causing autostart issues + + pouet.net version of Virtual City works fine and isn't packed. + [0b7583105c28] + +2015-06-04 Nicolas Pomarede + + * src/cpu/newcpu.c, src/cpu/newcpu.h, src/gemdos.c, + src/includes/m68000.h, src/m68000.c, src/stMemory.c: + With Gemdos HD emulation, we must also flush the instruction cache + after writing to memory + [3925f1033acd] + + * src/cpu/newcpu.c: + Reorder some code + [698c3eede17d] + +2015-06-03 Eero Tamminen + + * src/debug/debugcpu.c: + Add TODO on debugger binary -> memory read command + [d2eb6ddf4c52] + + * src/gemdos.c, src/stMemory.c: + move flush before memory update + + This doesn't matter with current 030 cache which seems to be write + through. But doing flush afterwards would be a problem with 040 + cache copyback mode, so it's better to do it right from start. + + Corrected also flush args for fread() memory update. + [e5f37e57240a] + +2015-06-02 Eero Tamminen + + * doc/compatibility.html: + compatiblity version update: 1.9.0 -> 1.9, 1.8+ -> 1.9 + + - for consistency with other version numbers in compat list, use 1.9 + instead of 1.9.0 + - change 1.8+ to 1.9 for things which clearly require 1.9 features + (MMU or TT-RAM) + + Other 1.8+ items need re-testing before their version number can be + updated. + [9a1edfdc93b9] + +2015-06-02 Nicolas Pomarede + + * src/cpu/newcpu.c: + For WinUAE CPU, currpc was not initialized when intercepting VDI & + AES + [1483ea908f40] + + * src/cpu/newcpu.c: + In printf, use portable PRIX64 macro instead of llX (for Windows) + [31a81ac44940] + + * src/cpu/fpp.c: + 6888x NULL frame undocumented feature (from WinUAE 3.1.0 b23) + [90209c14abb2] + + * src/gemdos.c: + For Gemdos HD emulation, flush CPU's data cache in Fread function + (Gemdos $3F) + [62772e248aa3] + + * doc/compatibility.html, doc/release-notes.txt: + Update the devel version from 1.8.1 to 1.9.0 + [226316b15e38] + +2015-06-01 Nicolas Pomarede + + * src/cpu/memory.c: + Remove unused old call that set IO region to cachable and broke + blitter with TOS 4 + [67c89576874e] + + * src/stMemory.c: + Add missing include + [1f8942765c59] + + * src/stMemory.c: + In STMemory_Write(), call M68000_Flush_DCache() in case CPU >= 68030 + [f699090b64a6] + + * src/cpu/newcpu.c: + 68030 cache hits were counted twice + [b9821eaeb3b8] + +2015-06-01 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [3b323478a219] + + * doc/hatari.1, src/configuration.c, src/falcon/hostscreen.c, src/gui- + sdl/dlgAlert.c, src/gui-sdl/dlgMain.c, src/includes/configuration.h, + src/includes/main.h, src/main.c, src/options.c, src/reset.c: + Add "--mousewarp " option + + By default, Hatari warps mouse position on following events: + - Cold reset + - Falcon resolution change + - Dialog exit (restore mouse where it was when emulation was paused) + + Regardless of whether Hatari window is even visible. + + This can be pretty annoying, so now there's "--mousewarp " + option with which one can disable warping on reset & resolution + changes. + [01043c9a9d53] + +2015-06-01 Nicolas Pomarede + + * src/includes/version.h: + Use devel information string to identify the version + [bbea99d3c377] + +2015-05-31 Nicolas Pomarede + + * src/gemdos.c, src/includes/m68000.h, src/m68000.c: + We need to flush the CPU's data cache when Gemdos HD emulation + directly modifies the memory + [b00f2acfe58b] + +2015-05-31 Eero Tamminen + + * src/debug/profile_priv.h, src/debug/profiledsp.c: + separate counters field for DSP specific cycles diff + + Add new counters field for cycles diffs instead of re-using i_misses + field which name doesn't relate to the stored value. This is OK + because it's not used in caller counts, just for final statistics. + [6d161e98538f] + + * src/debug/profile.c, src/debug/profile_priv.h, + src/debug/profilecpu.c: + Add "profile caches" command for cache hit histograms + + Histogram data can be for all hits & misses (whereas per address + stats need to be limited to i-misses & d-hits to save memory). + [e0dedbcd9dfc] + + * src/debug/68kDisass.c, src/debug/profile.c, src/debug/profile.h, + src/debug/profile_priv.h, src/debug/profilecpu.c: + track data cache hits instead of misses + + Not really any functional changes, just renamings. + [d9724d4192b3] + +2015-05-29 Nicolas Pomarede + + * src/cpu/cpummu030.c, src/cpu/cpummu030.h, src/cpu/newcpu.c: + For WinUAE CPU, better handling of the "fake prefetch" used in 68030 + MMU (patch by Tony Wilen) + [6044e8f77b71] + +2015-05-28 Nicolas Pomarede + + * src/cpu/memory.c, src/cpu/memory.h: + Factorize some code for memory regions + [860ddb4806c8] + +2015-05-27 Nicolas Pomarede + + * CMakeLists.txt, cmake/FindCapsImage.cmake, src/mfp.c: + Revert bad commit + [bb90e3ca7750] + + * src/cpu/newcpu.c: + For WinUAE CPU, fix 68030 data cache where 'hit' returned random + data + [8cb677c12d3e] + + * CMakeLists.txt, cmake/FindCapsImage.cmake, src/cpu/memory.c, + src/cpu/newcpu.c, src/mfp.c: + More init for each memory region in CE mode (16 or 32 bits, + cachable, ...) This is needed to enable data cache in 68030 CE mode + [a606de221b42] + + * src/bios.c, src/blitter.c, src/debug/debugInfo.c, + src/debug/history.c, src/debug/history.h, src/falcon/crossbar.c, + src/falcon/crossbar.h, src/falcon/dsp.c, src/falcon/dsp.h, + src/falcon/videl.c, src/falcon/videl.h, src/gemdos.c, + src/includes/bios.h, src/includes/blitter.h, src/includes/gemdos.h, + src/includes/psg.h, src/includes/vdi.h, src/includes/video.h, + src/includes/xbios.h, src/psg.c, src/vdi.c, src/video.c, + src/xbios.c: + Use a variable 'FILE *fp' instead of 'stderr' for some debugger + outputs + [f6c3a5eb0cf6] + +2015-05-26 Eero Tamminen + + * src/debug/console.c: + normal conout output should go to stdout + + only warnings should go to stderr + [a57267f31ac9] + + * doc/release-notes.txt: + note os_base in release notes + [d0a261f73de6] + + * src/debug/log.c: + enable xoncount console redirection with "os_base" trace + + - only if xconout redirection isn't already specified + - "os_all" includes "os_base" so that gets it too + [4af816ed4893] + + * src/gemdos.c: + add Pexec() & Pterm*() tracking to "os_base" traces + [6b87749a1647] + + * src/cart.c, src/debug/log.c, src/debug/log.h, src/gemdos.c: + rename: fopen->os_base / TRACE_GEMDOS_FOPEN -> TRACE_OS_BASE + [42c8d985cd8d] + +2015-05-23 Thomas Huth + + * doc/compatibility.html, doc/manual.html: + Fix warnings from HTML validator + [1db9b45663db] + +2015-05-22 Eero Tamminen + + * src/debug/profilecpu.c: + add info needed for d-cache data by profile post-processor + [7f7803c8b605] + + * src/debug/68kDisass.c, src/debug/profile.c, src/debug/profile.h, + src/debug/profile_priv.h, src/debug/profilecpu.c, + src/debug/profiledsp.c: + add profiler support for D-cache miss information + + in addition to already existing I-cache information. + [41566a21b565] + +2015-05-19 Nicolas Pomarede + + * src/cpu/newcpu.c: + Typo, ifndef -> ifdef + [0a8a0153a185] + + * src/cpu/newcpu.c, src/debug/profilecpu.c, src/includes/m68000.h: + For WinUAE CPU, update hit/miss stats for instruction and data + caches + [bb76ad9f2fac] + + * src/cpu/newcpu.c: + For WinUAE, we must call do_specialties() after bus_error() in case + spcflags was modified + [34a2afb30697] + +2015-05-18 Eero Tamminen + + * python-ui/TODO, python-ui/hatariui, python-ui/hatariui.1, python- + ui/hatariui.py, python-ui/release-notes.txt: + update Hatari Python GUI documentation + [134e4392cff3] + + * doc/emutos.txt: + update emutos compat + + - EmuTOS has few line-A improvements which fix games + - Entombed freezes with EmuTOS v0.9.4 was probably Hatari issue as it + works now + [369057a5c6c2] + +2015-05-18 Thomas Huth + + * src/debug/evaluate.c: + Silence compiler warning + [40bf3176f555] + +2015-05-18 Eero Tamminen + + * python-ui/debugui.py: + Support WinUAE CPU core regs output in Python GUI + + Without this the Python GUI debug window doesn't work. + [6d8c578ef393] + + * src/debug/debugInfo.c: + show warnings only for "info" commands, not for debugger variables + + If one sets breakpoint for something like pc=text at boot, it would + generated warning on every instruction because: + -> system header isn't there + -> basepage cannot be located + -> basepage variables are undefined So don't generated warnings for + such debugger variables, only when system header and basepage are + requested as part of info command. + [7a07ef63c51c] + +2015-05-17 Eero Tamminen + + * doc/compatibility.html, doc/todo.txt: + doc updates to autostart issues + + Tested Falcon demos. Firestarter is one more demo that doesn't work + if autostarted. Interestingly some of such demos can be autostarted + with EmuTOS. + [fd4c11fcef76] + + * src/debug/profilecpu.c: + 2 minor fixes to profile code + + - TEXT variable is zero when there's no program loaded, check for + that + - use successive instructions zero cycles check only for old UAE CPU + core, with WinUAE CPU core such things are valid + [fa97a7fbb469] + +2015-05-15 Nicolas Pomarede + + * src/cpu/memory.c, src/uae-cpu/memory.c: + Fix check when reading/writing to SysMem RAM < $800 (mask first, + then compare) For example, in 24 bit mode, a read to $1000008 in + user mode or a write to $1000004 would not cause the expected bus + error + [36820c297f10] + +2015-05-14 Nicolas Pomarede + + * src/cpu/compat.h, src/cpu/newcpu.c, src/cpu/newcpu.h: + In WinUAE CPU core, m68k_dumpstate_file() didn't redirect to the + correct file + [96bafa507c39] + +2015-05-13 Eero Tamminen + + * python-ui/CMakeLists.txt, python-ui/hatari-logo.png, python- + ui/hatari.png, python-ui/uihelpers.py: + rename logo image + update python GUI info + + Hatari icon is named hatari.png, so rename Python GUI Hatari logo to + hatari-logo.png. Update also some other Hatari UI info. + [1d85c8f7218f] + + * python-ui/dialogs.py, python-ui/hatari.py: + add Python GUI support for --ttram (sets --addr24 too) + [448a7db72a88] + + * doc/release-notes.txt: + update release notes now that python gui supports --gemdos-drive + [66dda7eab116] + + * python-ui/dialogs.py: + add new trace options + [325eae85432c] + + * python-ui/dialogs.py, python-ui/hatari.py: + Python GUI support for GEMDOS HD drive option + [2e7be4afaacd] + +2015-05-13 Nicolas Pomarede + + * doc/release-notes.txt: + Add note about reset/debug dialog when CPU is in 'halt' state + [9024c27b77d0] + + * src/cpu/newcpu.c, src/uae-cpu/newcpu.c: + In case CPU is halted (double bus/address errors), show a dialog to + reset or debug + [029d05b0db8e] + +2015-05-13 Eero Tamminen + + * src/change.c, src/configuration.c, src/gemdos.c, src/gui- + sdl/dlgHardDisk.c, src/includes/configuration.h, src/options.c: + better config name: nHardDiskDrive -> nGemdosDrive + + It's not about harddisks in general, just about GEMDOS HD emulation. + [d826b6d63cb2] + +2015-05-12 Eero Tamminen + + * src/debug/natfeats.c: + allow natfeats from ROM + + necessary for EmuTOS debugging + [0097eb037404] + + * src/debug/breakcond.c: + fix nasty breakpoint removal thinko + + this came with changes adding delayed removal support + [461798402693] + +2015-05-11 Nicolas Pomarede + + * src/ioMemTabTT.c: + Contrary to some unofficial documentations, the TT doesn't have + hardware scrolling similar to the STE + [49f838ec4381] + +2015-05-10 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Update release notes + [99cb6dddd5d4] + + * src/video.c: + Temporary fix for the STE demo RGBeast by Aggression (modification + of video counter) + [7878849e8098] + +2015-05-09 Nicolas Pomarede + + * src/blitter.c: + Typo + [bc24cd991dbe] + + * doc/manual.html, doc/release-notes.txt, tools/CMakeLists.txt: + Fix more typos + [f0cf4f4aa804] + +2015-05-08 Nicolas Pomarede + + * src/blitter.c: + Typo + [0bc50f8dad2d] + + * src/blitter.c: + Rewrite the bus arbitration when blitter is started This is mostly + hardcoded specific cases for now, it would require cycle accurate + emulation to handle each prefetch done by the cpu instruction (fix + overscan plasma in 'Graphics Sound 2' part in 'Relapse' by + Cybernetic) + [14e465064f9a] + +2015-05-06 Eero Tamminen + + * doc/emutos.txt: + emutos notes update + [02ba6644bdc0] + + * doc/release-notes.txt: + list debian bugs in release notes + [42c607a5b8d7] + +2015-05-06 Nicolas Pomarede + + * src/debug/evaluate.c: + In printf, use portable PRIx64 macro instead of llx (for Windows) + [8e00c7a077c4] + +2015-05-06 Eero Tamminen + + * src/joy.c: + use true/false for bool return values instead of 1/0 + [a6814e666db1] + + * src/options.c: + Fix: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=716536 + + Release are compiled with NDEBUG, so assert didn't catch the issue, + and asserts are anyway no-no in user input handling. + -> replace assert with real check. + + Additionally, reject option name if it has anything else than single + digit at end. + [2be138d236d5] + + * src/includes/str.h: + local includes should be in "", system ones in <> + [f2a604486e1d] + + * src/includes/configuration.h: + Fix: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=688594 + + If header's struct contents depend on configuration options, header + must include config.h. Anything else is too fragile (wrong include + order doesn't necessarily cause warnings and bugs resulting from + struct offset differences can be hard to track down). + [b31b00ff5f50] + + * src/debug/breakcond.c, src/includes/main.h: + better fix to assert() variable compiler warning + [618cf09920d3] + +2015-05-05 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Update MIDI state in release notes + [40b357f09ac5] + + * src/midi.c: + Update save/restore for MIDI + clean debug code + [5253f6ae3f0a] + + * src/debug/breakcond.c: + Temporarily rollback change #5689 as it can break compilation + [4696b88f5e66] + +2015-05-05 Eero Tamminen + + * src/debug/breakcond.c, src/includes/main.h: + fix compiler warning about variable used only by assert + + adds macro that outputs its contents only when asserts are enabled + [a7c2862a45e6] + +2015-05-04 Nicolas Pomarede + + * src/midi.c: + Better accuracy for MIDI's TDRE bit at $fffc04 Handle the case where + a new byte is written at $fffc06 while the previous byte is still + not completely transferred (fix overflow indicator in Notator) + [158dad8c6f0f] + +2015-05-03 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [7f67e8a74f2e] + + * tools/debugger/gst2ascii.c: + Windows/DOS requires binary files to be opened with "rb" + [090c85c879e5] + + * src/debug/profilecpu.c: + disable profiler DEBUG + + Besides causing large amount of (zero cycles) warnings with new + WinUAE CPU core, DEBUG does things that can in some circumstances + trigger asserts, so it's not good to have it enabled by default. + [488279f1db9c] + + * src/debug/breakcond.c: + breakpoints: fix corner-case + optimize + + Corner-case needs to abort, it can cause invalid accesses, not just + leaks. + + Optimize few additional check by specifying how likely they're to + happen. + [95fd50438763] + + * doc/compatibility.html: + add few programs requiring TT-RAM to compatibility list + [57cda279cd30] + + * tests/debugger/makefile, tests/debugger/test-breakcond.c, + tests/debugger/test-dummies.c: + update debugger tests accordingly + [e71b9f97dceb] + + * src/debug/breakcond.c, src/debug/breakcond.h, src/debug/debugcpu.c, + src/debug/debugdsp.c: + fix breakpoint array traversal with chained breakpoints + + Chained breakpoints can parse arbitrate debugger files when hit, and + user could in those add and remove breakpoints. This parsing & + resulting modifications happen while breakpoint array is being + traversed, which means that traversal code can return invalid + breakpoint indexes. + + Solution is suspending existing breakpoint array modifications + during array traversal, doing the modification after it and + correcting the index. This required adding several new variables + both for CPU & DSP breakpoints to indicate that deletes need to be + delayed and what needs then to be deleted. + + This which was easier to handle by refactoring the code so that + these variable sets are in their own structures. Use of the new high + level structures required changes in many places, but allowed making + rest of the code both simpler & more flexible. + + It also allowed getting rid of the ugly bForDsp argument in many + internal functions. At the same time I added separate CPU & DSP + variants of the exported BreakCond_BreakPointCount() wrapper. + [3fb8e0ececbc] + +2015-05-02 Eero Tamminen + + * src/debug/breakcond.c: + use temporary var for readability (shorter lines) + [c799a25720b8] + +2015-05-02 Nicolas Pomarede + + * src/floppy_ipf.c: + For IPF, update pointers to prevent crash before calling + CAPSFdcInvalidateTrack() + [0eec73b08511] + +2015-05-02 Eero Tamminen + + * src/debug/symbols.c, src/debug/symbols.h, src/gemdos.c, + src/includes/options.h, src/options.c: + use common code for identifying Atari programs + + symbols.c had mostly duplicate code for detecting whether given file + is an Atari program, compared to what was used by options.c. As + symbols.c detection apparently doesn't work on Windows although + options.c one does, use latter also for former. + + Only functional diffs are use of "rb" mode instead of "b". As Hatari + is just reading first two chars of the file and neither is CR or LF, + I don't see how that could fail, but hopefully it works now also on + Windows... + [528947b85ee3] + +2015-04-30 Thomas Huth + + * src/includes/msa.h, src/msa.c, src/zip.c: + Make the MSA image loading more robust by checking the remaining + file size + [9dcc6b5b5c70] + +2015-04-28 Nicolas Pomarede + + * src/cpu/fpp.c, src/cpu/gencpu.c, src/cpu/newcpu.h: + Fix prefetch refilling for FPU instructions fpuop_bcc and fpuop_dbcc + (patch by Tony Wilen) + [570b8949f415] + +2015-04-27 Nicolas Pomarede + + * src/cpu/cpummu.c, src/cpu/debug.c, src/cpu/fpp.c, src/cpu/newcpu.c, + src/cpu/newcpu.h, src/cpu/options_cpu.h, src/cpu/winuae_readme.txt: + Update WinUAE cpu core from 3.1.0 b15 to 3.1.0 b16 (mostly + compilation warnings) + [cf5573e84cf2] + +2015-04-27 Thomas Huth + + * src/msa.c: + Add more sanity checks to MSA header verification + [1e38234ccc06] + + * src/msa.c: + Get rid of some indentation levels in MSA_UnCompress + [e2357a53c594] + +2015-04-26 Eero Tamminen + + * src/stMemory.c: + add TODO for memtop + + (move setting it beside phystop as they're related) + [d906c3e5394a] + + * doc/compatibility.html, doc/emutos.txt: + update compatibility notes / improve texts slightly + [b008c0d4fa0e] + + * doc/hatari.1, doc/release-notes.txt, tools/CMakeLists.txt, tools + /atari-hd-image.1, tools/atari-hd-image.sh, tools/zip2st.1: + use atari-convert-dir in atari-hd-image + refer to it in docs + [ce383be348a7] + + * tools/atari-convert-dir.1, tools/atari-convert-dir.py: + add script for converting long file names to Atari names + [7849d38d9f57] + +2015-04-25 Thomas Huth + + * doc/todo.txt, src/cartData.c, src/cart_asm.s: + Add Pexec7 support (to allocate in TT RAM) to the cartridge, 2nd try + [364a45dedd0a] + +2015-04-25 Eero Tamminen + + * src/debug/symbols.c, tools/debugger/gst2ascii.c: + show program header info even when it has no symbols + + both in Hatari debugger & gst2ascii: + - parse program flags and name them for user + - show header info before checking whether symbols are present + + These are useful to know now that Hatari supports TT-RAM & MMU. + [20bbad707c06] + +2015-04-19 Thomas Huth + + * doc/todo.txt, src/cartData.c, src/cart_asm.s: + Undo last commit, there is still something broken in there + [3538e73c2aa6] + +2015-04-20 Eero Tamminen + + * src/debug/debugInfo.c: + fix debugger "info" commands for data in TT-RAM + + basepage & cookiejar subcommands assumed all addresses are within + ST-RAM and used STram[] offsets. Fixed by using STMemory_Read*() + accessors instead. + [325400bb4258] + +2015-04-19 Thomas Huth + + * doc/todo.txt, src/cartData.c, src/cart_asm.s: + Add Pexec7 support (to allocate in TT RAM) to the cartridge + [f5096d163a31] + +2015-04-17 Thomas Huth + + * src/printer.c: + Open printer file in binary mode + [cc2fbaf159b6] + +2015-04-15 Eero Tamminen + + * doc/todo.txt: + add links to toshyp + [da4696e8dfaf] + + * doc/todo.txt: + update TODO / add item for GEMDOS EMU program header flags support + [3470e5c5aa8c] + +2015-04-09 Nicolas Pomarede + + * src/m68000.c: + When using WinUAE CPU in CE mode, we need to call ipl_fetch() after + each call to doint() + [3aa2a2cdf7ab] + +2015-04-09 Eero Tamminen + + * src/debug/profilecpu.c: + fix formatting & update copyright + [dbfe41794772] + + * doc/release-notes.txt, src/debug/profilecpu.c: + add profiler support for TT-RAM + + - add new TT-RAM area: update address checks, allocate memory for + it, process data & output new area info + - remove redundant WINUAE ifdefs (code builds fine without them on + oldUAE and isn't in perf critical path) + [a077b4eeb861] + +2015-04-09 Nicolas Pomarede + + * src/mfp.c: + When an interrupt happens on timers A/B/C/D, use PendingCyclesOver + to determine if a 4 cycle delay is needed + [31ca65029761] + +2015-04-06 Nicolas Pomarede + + * src/cpu/custom.c, src/cpu/custom.h: + Remove duplicated code also present in debug.c + [be78790417ca] + +2015-04-06 Eero Tamminen + + * src/cart.c, src/gemdos.c: + allow fopen tracing without GEMDOS HD emulation + [083639e6a0b2] + +2015-04-06 Nicolas Pomarede + + * src/cpu/cpummu.c, src/cpu/newcpu.c, src/cpu/newcpu.h, + src/cpu/newcpu_common.c: + Remove some warnings in WinUAE CPU (printf, signed/unsigned) + [40b7a4ae202e] + +2015-04-05 Nicolas Pomarede + + * src/cpu/newcpu.c, src/cpu/options_cpu.h, src/cpu/winuae_readme.txt: + Update WinUAE cpu core from 3.1.0 b14 to 3.1.0 b15 + [8d5f90ee8d73] + + * src/cpu/cpummu.c, src/cpu/cpummu030.c, src/cpu/debug.c, + src/cpu/debug.h, src/cpu/fpp.c, src/cpu/memory.c, src/cpu/memory.h, + src/cpu/newcpu.c, src/cpu/newcpu_common.c, src/cpu/options_cpu.h, + src/cpu/sysdeps.h, src/cpu/winuae_readme.txt: + Update WinUAE cpu core from 3.1.0 b10 to 3.1.0 b14 + [39b723be23e0] + +2015-03-30 Eero Tamminen + + * doc/release-notes.txt, src/debug/log.c, src/debug/log.h, + src/gemdos.c: + "fopen" trace option to trace just Fopen() calls + + This is useful for debugging missing files (and file accesses done + by programs in general), when full GEMDOS trace produces too much + output (from fseeks, text output single letter at the time etc). + [731b871f5935] + +2015-03-29 Thomas Huth + + * src/change.c, src/gui-sdl/dlgScreen.c: + Add missing checks for WITH_SDL2 + [da2eac4f4404] + + * src/change.c, src/falcon/hostscreen.c, src/falcon/hostscreen.h, + src/falcon/videl.c, src/falcon/videl.h, src/includes/screen.h, + src/screen.c, src/video.c: + Make sure that screen mode gets refreshed when options changed + [b0c187865904] + + * src/change.c, src/configuration.c, src/gui-sdl/dlgScreen.c, + src/includes/configuration.h, src/screen.c: + Add the possibility to set SDL2 scale quality and Vsync option + [6b901d175829] + +2015-03-25 Nicolas Pomarede + + * src/floppy_ipf.c: + Remove some warnings during compilation when using caps library v4 + [cd3d4007f820] + +2015-03-24 Eero Tamminen + + * doc/compatibility.html, doc/emutos.txt: + add Chorensha + [123713bb0896] + +2015-03-20 Nicolas Pomarede + + * src/midi.c: + Don't change MIDI's frequency when CPU's frequency is changed + [49fcdf652bb1] + +2015-03-20 Eero Tamminen + + * src/midi.c: + remove obsolete midi comment & fix typo + [23a8f973b85c] + +2015-03-20 Nicolas Pomarede + + * src/midi.c: + Improve state of TDRE bit in MIDI's status register fffc04 + [139a73f2a112] + +2015-03-19 Nicolas Pomarede + + * src/midi.c: + In default TOS config, transferring 1 byte over MIDI requires 10 + bits, not 9 + [b070f44137c6] + +2015-03-17 Eero Tamminen + + * doc/release-notes.txt: + note multiple ACSI device support in release notes + [fb5a89465e84] + + * doc/hatari.1, src/options.c: + change ACSI ID/filename divider from ':' to '=' + + It's less likely to conflict with Windows path names. + [cddc54241874] + +2015-03-16 Thomas Huth + + * src/cpu/cpummu030.c: + Silence compiler warnings in cpummu030.c + [cee2b3db08c0] + + * src/cpu/newcpu.c: + Silence some compiler warnings in newcpu.c (sync with upstream + WinUAE repository) + [d3c4fee7349e] + +2015-03-16 Nicolas Pomarede + + * doc/release-notes.txt: + EmuTOS 0.9.4 was released, remove mention of devel version + [c9ca4f05a190] + +2015-03-15 Nicolas Pomarede + + * src/midi.c: + Don't disable internal MIDI's timer when MIDI is disabled If MIDI is + disabled, we should not try to read/write bytes from the MIDI's + filehandlers, but we should still flush bytes regularly and update + ACIA's status register, else some programs will not work (which + would not be the case on a real STF) (fix lock in Notator when MIDI + is disabled) + [f4171b289fa4] + +2015-03-14 Eero Tamminen + + * doc/hatari.1, src/options.c: + support optional BUS ID for --acsi option + [a8b6d94454ea] + + * src/debug/debugInfo.c: + nicer "info osheader" output + [b6097a3f6bd5] + +2015-03-13 Eero Tamminen + + * doc/emutos.txt: + document STVidPlay issue + [30304fcaecb1] + + * doc/emutos.txt: + align notes + list NeoChrome Master line-A functions + [285382059133] + +2015-03-12 Eero Tamminen + + * doc/emutos.txt: + update to EmuTOS 0.9.4 + some re-ordering / header changes + [6a34d8f1f087] + +2015-03-06 Thomas Huth + + * share/CMakeLists.txt, share/applications/hatari.desktop, + share/mime/packages/hatari.xml: + Switch to the official .msa and .dim mime-types + [bc9d0c053c6e] + +2015-03-04 Eero Tamminen + + * src/memorySnapShot.c: + fix compiler warning + [31401714f1e2] + +2015-03-04 Nicolas Pomarede + + * src/includes/midi.h, src/memorySnapShot.c, src/midi.c: + Save/restore MIDI state + [bf3b39c17ea3] + + * src/midi.c: + Use MIDI_TRANSFER_CYCLE cpu cycles to transfer 1 byte over MIDI + [8381de89ce03] + +2015-03-03 Nicolas Pomarede + + * src/midi.c: + Use MIDI_UpdateIRQ() to factorize code + [6cd1874e321f] + + * doc/release-notes.txt: + Update release notes for MIDI + [abe274b0257b] + + * src/cpu/newcpu.c, src/includes/m68000.h: + Add more notes about IACK cycles + [bc81c16dc3a1] + + * src/midi.c: + Fix for interrupts' condition when using MIDI (some bitmasks were + wrong/incomplete) (fix the MIDI programs Realtime and M by Eric + Ameres, and possibly many others) + [189b8a768901] + +2015-03-01 Eero Tamminen + + * src/debug/debugcpu.c: + fix DBCC mask in debugger instruction type check + + Thanks to Thomas for reporting this! + [88862aae6620] + +2015-03-01 Thomas Huth + + * src/paths.c: + Make sure to leave space for NUL byte in buffer when calling + readlink + [6f4a0e03ecbd] + + * src/gemdos.c: + Check return value of ftello for errors, too + [df420b628309] + +2014-08-04 Thomas Huth + + * src/cfgopts.c: + Refactor input_config() for better readability + [8b3d8a7c05d7] + +2015-02-28 Nicolas Pomarede + + * doc/release-notes.txt: + Update release notes for MFP + [dc6407cd08e4] + + * src/cpu/newcpu.c, src/cpu/newcpu.h: + Improve I/N bit in stack frame for bus/address error (from WinUAE + 3.1.0 b11) + [fa93c0ace5ec] + +2015-02-28 Thomas Huth + + * src/gui-sdl/dlgFileSelect.c: + Make sure to always free all resources when leaving the file + selection dialog + [de141456b59f] + + * src/xbios.c: + Do not blindly trust XBIOS parameters when accessing arrays + [5d030aacd4d7] + +2015-02-27 Nicolas Pomarede + + * doc/compatibility.html: + Add notes for MIDI programs Realtime and M by Eric Ameres + [28322a51a850] + + * src/mfp.c: + In MFP, better support for GPIP/AER/DDR and trigerring an interrupt + when AER is changed (fix the MIDI programs Realtime and M by Eric + Ameres, which toggle bit 0 in AER) + [0222ffc11be1] + + * src/midi.c: + Add missing clear to GPIP in Midi_Data_WriteByte + [bc79337d2ce8] + +2015-02-25 Nicolas Pomarede + + * doc/compatibility.html: + Add notes about the game 'Antago' + [bd0558525e01] + +2015-02-25 Thomas Huth + + * src/falcon/crossbar.c: + Cosmetic clean-up in crossbar.c + [c7064597b5c9] + +2015-02-25 Nicolas Pomarede + + * src/mfp.c: + In MFP_CheckPendingInterrupts(), check all 16 possible interrupts + Even if some printer interrupts can't happen because Hatari can't be + connected to a real printer, it's possible to trigger them by + writing into AER + [fcc4138d34c4] + + * src/mfp.c: + Improve GPIP reading/writing at $fffa01 by taking DDR into account + [823af3aa7922] + + * src/blitter.c, src/includes/mfp.h: + Correctly set GPIP bit 3 depending on whether blitter is busy or not + [ee52d8ad3ddc] + + * src/mfp.c: + MFP's GPIP should be 0x00 after a reset (according to Motorola's + doc) + [d906530c849a] + + * src/acia.c, src/fdc.c, src/ide.c, src/includes/mfp.h, src/mfp.c, + src/midi.c: + Use MFP_GPIP_Set_Line_Input() instead of direct access for + components connected to MFP's GPIP (ACIA, FDC, HDC) + [1df843dfcfef] + +2015-02-23 Nicolas Pomarede + + * src/cpu/winuae_readme.txt: + Update WinUAE's version file + [e5313b487165] + + * src/cpu/cpummu.c, src/cpu/cpummu.h, src/cpu/cpummu030.c, + src/cpu/debug.c, src/cpu/fpp.c, src/cpu/gencpu.c, src/cpu/newcpu.c, + src/cpu/options_cpu.h: + Update WinUAE cpu core from 3.1.0 b3 to 3.1.0 b10 + [b074837a5751] + +2015-02-22 Nicolas Pomarede + + * src/cpu/gencpu.c, src/cpu/newcpu.c: + Fix STOP timing for WinUAE's CPU Minimal number of cycles was 2 in + CE mode, it should be 4. We should also exit the STOP state + immediately and don't add 2 or 4 cycles if an interrupt is already + pending + [0da8f0baf677] + + * src/cpu/newcpu.c: + Don't use 'goto' before ENDTRY macro, else internal stack will + overflow + [6a5061274090] + +2015-02-21 Thomas Huth + + * src/cpu/build68k.c, src/cpu/gencpu.c: + Silence compiler warnings in gencpu.c and build68k.c + [cc896cabea86] + +2015-02-20 Thomas Huth + + * src/cpu/fpp.c: + Silence some of the compiler warnings in fpp.c + [44bd8d568a99] + + * src/cpu/fpp.c: + Fix the FPU revision numbers in stack frames + [19f1a0600cff] + + * src/vdi.c: + Do not blindly trust the line-a cell height value (it could be zero, + which would cause a division by zero bug in Hatari). + [b2d4baa39fe2] + +2015-02-22 Nicolas Pomarede + + * src/cpu/gencpu.c, src/cpu/newcpu.c, src/cpu/newcpu.h: + Improve PC value pushed in stack frame for bus/address error (from + WinUAE 3.1.0 b10) For bus/address errors, the stacked PC will depend + on prefetch and addressing mode of the current instruction + [22f9f9a6837f] + + * src/cpu/cpummu.c: + Add more logs in CATCH/TRY macros + [a1b741cde710] + +2015-02-19 Nicolas Pomarede + + * src/audio.c: + Apply STF low pass filter for any audio freq >= 40 kHz + [84d651306df7] + +2015-02-18 Nicolas Pomarede + + * src/uae-cpu/gencpu.c, src/uae-cpu/newcpu.c, src/uae-cpu/newcpu.h: + In UAE CPU, use last_writeaccess_for_exception_3 (as in WinUAE CPU) + [3adc26838673] + +2015-02-15 Eero Tamminen + + * doc/release-notes.txt: + update + [fa0d73d69f60] + + * doc/emutos.txt: + update EmuTOS Falcon notes (sound matrix support) + [44788c0ada6e] + + * doc/video-recording.txt: + add atari-forum guide lines for getting best video recordings + [d9fc8f7754e2] + +2015-02-13 Nicolas Pomarede + + * src/cpu/debug.c, src/debug/68kDisass.c: + Prevent bus error when using external disassembler with WinUAE CPU + in region requiring bit S in SR + [2cdb745d3386] + +2015-02-11 Thomas Huth + + * src/zip.c: + Fixed stupid bug introduced with zip code cleanup three days ago + [4bd49dd0e269] + +2015-02-11 Nicolas Pomarede + + * src/cycles.c, src/includes/m68000.h, src/m68000.c, src/uae- + cpu/newcpu.c: + In old UAE's CPU, store the current opcode in regs structure and add + M68000_CurrentOpcode macro + [ac048bdd4a38] + + * src/cycles.c, src/includes/m68000.h, src/m68000.c, src/uae- + cpu/newcpu.c, src/uae-cpu/newcpu.h: + In old UAE's CPU, replace BusErrorPC by regs.instruction_pc to share + more code and remove some #ifdef + [0218bff2413b] + + * src/cpu/newcpu.c, src/cycles.c: + Use regs.instruction_pc instead of BusErrorPC in WinUAE's CPU + [59b53f5064d0] + + * src/cpu/memory.c, src/cpu/newcpu.c, src/debug/natfeats.c, src/fdc.c, + src/ide.c, src/includes/m68000.h, src/ioMem.c, src/m68000.c, src + /uae-cpu/memory.c: + Update M68000_BusError() to be able to use WinUAE's CPU bus error + functions + [0ba4a8208998] + +2015-02-10 Thomas Huth + + * src/ikbd.c: + Use bitwise 'or' in IKBD_SendAutoJoysticksMonitoring (issue + discovered with 'smatch') + [b4c2f65d9d6c] + + * src/acia.c, src/audio.c, src/debug/68kDisass.c, src/debug/debugui.c, + src/dmaSnd.c, src/falcon/videl.c, src/fdc.c, src/file.c, + src/floppy.c, src/gui-sdl/dlgFileSelect.c, src/hdc.c, src/mfp.c, + src/psg.c, src/screen.c, src/unzip.c, src/video.c: + Fix style issues discovered by sparse: Mark file-local variables as + 'static' etc. + [e8c4a33a00f0] + + * src/floppy_stx.c, tools/hmsa/hmsa.c: + Fix style issues discovered by sparse: Remove 'extern' keyword from + non-extern functions + [902f2d455876] + +2015-02-08 Thomas Huth + + * src/avi_record.c, src/gemdos.c, src/gui-sdl/dlgFileSelect.c, + src/hdc.c, src/ide.c, src/wavFormat.c: + Make sure to check return value of library functions that may fail + [38bbcf70f357] + + * src/floppy.c, src/tos.c, src/zip.c: + Fixed potential resource leaks (discovered with Coverity) + [cf22ec2d2e14] + +2015-02-07 Thomas Huth + + * CMakeLists.txt, cmake/config-cmake.h, src/debug/debugui.c, + src/ide.c, src/includes/str.h, src/paths.c: + Introduce strlcpy to avoid non-terminated string buffers + [e9145497f0db] + + * src/hdc.c, src/ide.c, src/screenSnapShot.c: + Fix some issues discovered with Coverity + [56600f8a9ba7] + + * src/tos.c: + Improve the checks for valid TOS versions a little bit and make sure + that RAM TOS images get loaded into the STRam (for SMALL_MEM). + [74e42795a099] + +2015-02-05 Nicolas Pomarede + + * src/cpu/newcpu.c: + Remove logs for Line-A and Line-F calls + [8cbca7247d33] + + * src/m68000.c: + Split M68000_Exception() into 2 parts for old and new CPU core for + better readability + [cd68d86dc5c0] + + * src/cpu/cpummu030.c, src/cpu/fpp.c, src/cpu/gencpu.c, + src/cpu/newcpu.c, src/cpu/newcpu.h, src/cpu/newcpu_common.c, + src/debug/natfeats.c, src/m68000.c: + For the new WinUAE's CPU, don't use ExceptionSource anymore when + calling Exception() + [7603ad5ea12e] + + * src/mfp.c: + Keep old MFP interrupt code when using old uae cpu (bis) + [dc97e84a3756] + + * src/mfp.c: + Keep old MFP interrupt code when using old uae cpu + [8b9463fca7fc] + + * src/cpu/compat.h, src/cpu/hatari-glue.c, src/cpu/newcpu.c, + src/m68000.c, src/mfp.c: + For WinUAE's cpu, remove old code that handled MFP/DSP interrupts by + calling Exception() directly + [25c5e5bcc31b] + + * src/cpu/newcpu.c: + For WinUAE's cpu, more accurate emulation of the E clock delay for + autovectored interrupts Instead of using some tables with different + jitter patterns for HBL and VBL interupts in InterruptAddJitter(), + we really measure the delay to the next E clock and use it in + iack_cycle(), as it is done on a real 68000 + [dbc702b3ca12] + + * src/video.c: + Update temporary hack for 'Panic' by Paulo Simoes to work with new + WinUAE CPU too See changeset #5160 for details + [23b6759d3328] + +2015-02-05 Eero Tamminen + + * doc/compatibility.html, doc/emutos.txt: + add more SillyVenture 2014 demos + [d9570c4cb61e] + +2015-02-04 Eero Tamminen + + * doc/hatari.1, doc/manual.html: + add SDL GUI keyboard shortcuts section also to manual + [097901d55330] + +2015-02-03 Eero Tamminen + + * src/gui-sdl/sdlgui.c: + improve keyboard shortcut indicator + + - on 2x mode, use black underline like PC desktops do + - on 1x mode, move underline higher so that it doesn't go: + - over next line text + - over button borders and make it purple so that it's easier to + distinguish from font + [7348e7f52bf6] + +2015-02-02 Nicolas Pomarede + + * src/fdc.c: + Typo + [62d8d2acd33c] + + * doc/release-notes.txt, src/fdc.c: + When using 'read address' and 'read track' on ST/MSA, check the + track number is valid If track is beyond limit, we return RNF for + 'read address' and random data for 'read track' + [d68ecd523850] + +2015-01-29 Thomas Huth + + * src/cpu/CMakeLists.txt: + Disable -Wno-unused-but-set-variable for old GCCs + [024f52440267] + +2015-01-28 Eero Tamminen + + * doc/compatibility.html: + add sillyventure 2014 Falcon demos + update TBL info + [e8255fec795b] + +2015-01-27 Laurent Sallafranque + + * src/falcon/dsp_core.c, src/falcon/dsp_core.h, src/falcon/dsp_cpu.c: + revert DSP ea pipeline change + [5741681e7d9f] + +2015-02-02 Nicolas Pomarede + + * src/cpu/compat.h, src/cpu/hatari-glue.c, src/cpu/newcpu.c, + src/falcon/dsp.c, src/falcon/dsp.h, src/includes/m68000.h, + src/includes/mfp.h, src/m68000.c, src/mfp.c, src/uae-cpu/newcpu.c: + For WinUAE's cpu, handle MFP/DSP interrupts as level 6 interrupts + instead of calling Exception() directly Unlike HBL and VBL + interrupts, MFP/DSP interrupts were handled by calling directly + Exception() with the new vector number from 0xfffa17 and 0xffa203, + but this was not the correct way to do it because it required + special code for the IACK sequence and lot of changes to the + original WinUAE's code, making it harder to merge code's change with + WinUAE + [5894fc89f59b] + +2015-02-01 Nicolas Pomarede + + * src/uae-cpu/gencpu.c: + Cancel change #5515 from 7/1/2015 : extra cycles for JSR/JMP with + Ad8r and PC8r were already counted (fix 'European Demos' Main Menu) + [7c7d08d97add] + +2015-01-25 Nicolas Pomarede + + * src/includes/m68000.h, src/m68000.c, src/video.c: + Use exceptions's number instead of their vector + [c585c7b4549a] + +2015-01-24 Eero Tamminen + + * doc/compatibility.html: + add No Extra's STE demos to compat list + [03db4765be12] + +2015-01-22 Nicolas Pomarede + + * src/blitter.c, src/mfp.c: + During blitter transfer, also increase main cycle counter used for + MFP timing Fix "Infinite Live of the Blitter" by "No Extra" that + crashed after the dot tunnel part due to an MFP interrupt being + delayed after the VBL interrupt + [aa35fd01aec6] + +2015-01-21 Nicolas Pomarede + + * src/cpu/cpummu030.h, src/cpu/custom.c, src/cpu/debug.c, + src/cpu/debug.h, src/cpu/mmu_common.h, src/cpu/newcpu.c: + Remove some compilation's warnings + [a26201a9a581] + + * src/cpu/newcpu.c: + Call iack_cycle() for all CPU modes + [e043575d9815] + +2015-01-19 Nicolas Pomarede + + * src/cpu/newcpu.c: + Move some old UAE code for interrupts into WinUAE's cpu + [5dffd6ed9f86] + +2015-01-18 Eero Tamminen + + * doc/compatibility.html, doc/emutos.txt: + update info on few other TT programs + [48fb080b0fbd] + + * doc/compatibility.html, doc/emutos.txt: + update tSCc demo info + [c009099270fb] + +2015-01-16 Nicolas Pomarede + + * src/cpu/newcpu.c: + Use a different variable 'vector_nr' to store the return value of + iack_cycle() Vectored interrupts can return a new value for 'nr', + but we need to keep the old and the new value to correctly process + the exception + [bbe3cf0b8c34] + +2015-01-15 Nicolas Pomarede + + * src/cpu/newcpu.c: + Add some default cycles values for interrupts in 68000 CE mode These + are not accurate timings, but they work with many demos and allows + to improve other parts of the CPU when in CE mode + [7003152c5da6] + + * src/cpu/cpu_prefetch.h: + Add preliminary memory access timing : count 4 cycles per byte/word + access in 68000 CE mode This already fixes a lot of instructions' + timings for most EA, but real HW is more complex and requires to add + 2 extra cycles on non-aligned accesses + [b93313999f16] + + * src/cpu/gencpu.c: + Fix bad cycles count for divu/divs with WinUAE's cpu in prefetch + mode + [89f486d595ba] + +2015-01-14 Eero Tamminen + + * doc/hatari.1, doc/manual.html: + updates to VDI mode descriptions (limits etc) + [bd63ce2672a8] + + * doc/release-notes.txt, src/stMemory.c: + change VDI mode phystop again, NVDI crashes if gap is too large + [1ce6289afd51] + +2015-01-13 Nicolas Pomarede + + * src/cpu/compat.h, src/cpu/newcpu.c, src/cpu/sysdeps.h: + Define macro for gui_message + [6e90f8af89e8] + +2015-01-13 Nicolas Pomarede + + * src/cpu/cpummu030.c, src/cpu/cpummu030.h, src/cpu/debug.c, + src/cpu/newcpu.c, src/cpu/options_cpu.h, src/cpu/savestate.h, + src/cpu/winuae_readme.txt: + Update WinUAE cpu core from 3.1.0 b1 to 3.1.0 b3 + - DBcc cycles in 68000 compatible/prefetch mode were wrong + - Set unused bits of "mode" in bus/address errors stack frame + - update prefetch when turning MMU on/off + [24ef75d87e13] + +2015-01-13 Nicolas Pomarede + + * src/cpu/hatari-glue.c, src/uae-cpu/hatari-glue.c: + Use a NOP to return from opcodes used to intercept gemdos/natfeats + [fb489428c6a4] + +2015-01-12 Nicolas Pomarede + + * src/cpu/newcpu.c, src/m68000.c: + Fix bad cycles count in 68000 cycle exact mode + [9d5fc7282180] + +2015-01-12 Eero Tamminen + + * tests/natfeats/natfeats.c, tests/natfeats/natfeats.h: + fix natfeats test-code for 16-bit compilers + + AHCC sizeof() returns word and probably so does e.g. "gcc -mshort". + Thanks & apologies to Nicolas for needing to debug this! + [57811c1ded3c] + +2015-01-12 Nicolas Pomarede + + * src/cpu/hatari-glue.c: + Fix NatFeat_ID and NatFeat_Call with new WinUAE's cpu + [e396d9e06353] + +2015-01-12 Eero Tamminen + + * doc/manual.html: + update HD Driver / EmuTOS HD image notes + + info was 5 years out of date... + [25e72df09123] + + * src/stMemory.c: + give warning about VDI mode <-> mem detection incompatibility + [a4df9ed6f7c7] + +2015-01-11 Nicolas Pomarede + + * src/main.c: + Call STX_Init from Main_Init_HW, not from Main_Init else it breaks + some options STX_Init should be called before parsing --disk-X + options, else the STX file won't be loaded. + [0270ca2b7603] + +2015-01-11 Eero Tamminen + + * src/stMemory.c: + VDI mode mem gap limit is needed for TOS v3 + [f2d14d9da099] + + * src/stMemory.c: + debug output of VDI mode memtop/physbase + + to help debugging people's issues with VDI mode + [684e34e2f9d1] + + * doc/release-notes.txt, src/stMemory.c: + improved memtop/phystop values for VDI mode + + Situation was more complicated, it depends on TOS version what + works. + [036a41cfbc56] + + * doc/release-notes.txt, src/stMemory.c: + align memtop to 32k for better compatibility between VDI mode & TT- + RAM + [74ab45ad6356] + +2015-01-10 Eero Tamminen + + * doc/manual.html: + improve wording + [abda03557db5] + + * doc/manual.html: + IDE works also with older TOS version, they just don't boot from IDE + [6d03929f9aa9] + +2015-01-09 Thomas Huth + + * src/cpu/hatari-glue.c, src/debug/68kDisass.c, + src/debug/debug_priv.h, src/floppy_stx.c, src/includes/unzip.h, + src/main.c, src/str.c, src/unzip.c: + Fixed issues discovered with cppcheck + [e3e7d488159d] + +2015-01-09 Eero Tamminen + + * tools/hatari-prg-args.sh: + finally fix hatari-prg-args.sh argument parsing (shell bug) + + Debian LTS builtin /bin/sh echo command is borked, it by default + interprets backslashes with letters from different variables when + they're concatenated. And it doesn't support -E option to disable + this. Fix by forcing use of separate echo command. + + Fixed by using system echo command. Converting path string to upper + case before concatenating + [e209b01e628b] + + * doc/compatibility.html: + update + [e1cbb3fa0401] + +2015-01-08 Nicolas Pomarede + + * src/cpu/gencpu.c, src/cycles.c: + Backport MovepByteNbr in MOVEP from old UAE cpu to new WinUAE cpu + [465bc4286ffa] + +2015-01-07 Nicolas Pomarede + + * src/cpu/gencpu.c: + Fix JMP timing in prefetch mode, broken in change #5514 + [4893bab43a87] + + * src/uae-cpu/gencpu.c: + Add 2 extra cycles for JSR/JMP with Ad8r and PC8r in old UAE cpu + [01195fa93771] + + * src/cpu/gencpu.c: + Update special case for Ad8r and PC8r when using 68000 prefetch mode + [c88976657f73] + +2015-01-07 Eero Tamminen + + * src/debug/profilecpu.c: + fix profile stats with different TOS & CART addr order + [26ec40203078] + +2015-01-06 Eero Tamminen + + * src/debug/profilecpu.c: + fix: save whole profile + + TOS area was left out if it was in lower address than CART + [0e499189303d] + + * src/debug/debugui.c: + fix recursion + segfault with profiler DEBUG option + [c823ec94eb84] + +2015-01-06 Nicolas Pomarede + + * src/m68000.c, src/uae-cpu/options_cpu.h: + Also define cpu_cycle_exact with old UAE cpu, but always force it to + false + [b351fab701c6] + + * CMakeLists.txt: + Cancel adding '-g' option to gcc in previous commit + [795218a43886] + + * CMakeLists.txt, src/cpu/gencpu.c: + In WinUAE's cpu, add 2 cycles for Ad8r and PC8r only when using + 68000 prefetch mode + [25ffdf027488] + + * src/cpu/gencpu.c: + Backport some ST specific cycles values from old UAE cpu to new + WinUAE cpu Unaligned memory accesses take 2 more cycles on ST when + using Ad8r and PC8r adressing mode ; we need to handle this in + prefetch mode. + [3bf5f18f12e0] + +2015-01-05 Nicolas Pomarede + + * src/cpu/gencpu.c: + Fix DBF cycles in 68000 prefetch mode (from WinUAE 3010b2) + [87430a54b1c2] + + * src/cpu/options_cpu.h: + Disable WinUAE's specific variables in struct uae_prefs + [b7e38145f4f1] + +2015-01-05 Eero Tamminen + + * src/gemdos.c: + fix Pexec() cmdline trace output + [37dce586933d] + + * src/configuration.c: + fix compile warning from DSP change + [28eff0256b5e] + +2015-01-04 Eero Tamminen + + * doc/hatari.1, doc/manual.html: + sync hatari input sections better between manuals + [7e4a38a5610e] + + * doc/hatari.1: + add info on middle button -> double click, fix AltGr+Fx notes + [0f54313c31c8] + +2015-01-04 Nicolas Pomarede + + * src/cpu/debug.c, src/cpu/newcpu.c: + Factorize code with WinUAE : use get_long_debug() instead of direct + STMemory_ReadLong() + [c2892dc90598] + + * src/cpu/debug.c, src/cpu/gencpu.c, src/cpu/memory.h, + src/cpu/newcpu.c, src/cpu/options_cpu.h, src/cpu/winuae_readme.txt: + Update WinUAE cpu core from 3.0.0 to 3.1.0b1 + [ed23098b5c91] + + * src/cpu/cpummu.c: + Fix movem stack frame in mmu_bus_error from WinUAE 3010b1 + [f62246905caf] + +2015-01-03 Nicolas Pomarede + + * src/change.c, src/configuration.c, src/falcon/dsp.c, + src/falcon/dsp.h: + Fix restoring DSP state after loading a memory snapshot DSP_Init() + should be called only at start, during emulation we only call + DSP_Enable() or DSP_Disable(). Also remove a call to DSP_Reset() + which seems useless. + [a6a3ac3ab02f] + + * src/falcon/dsp.c: + Fix crash when restoring a memory snapshot where DSP was enabled + DSP_Init should be called after restoring the snapshot, else if + defaut value for nDSPType==0, then dsp_core_init won't be called at + start and dsp_core_hostport_update_hreq will crash when calling + dsp_host_interrupt (null pointer) + [cde42d1f28c7] + +2015-01-02 Eero Tamminen + + * doc/compatibility.html: + update compatibility notes for problematic sound apps + [75fd99dbafea] + + * src/gemdos.c: + fix gemdos hex number showing + [214fc1ea33ed] + +2015-01-01 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [6a734f53ee49] + + * tools/hatari-prg-args.sh: + fix path + [3a25e7967b23] + + * tools/hatari-prg-args.sh: + improve host path removal from Atari prg args + + shell replace syntax didn't work reliably, so replaced it with + otherwise equivivalent, but (hopefully) more robust 'sed' + incantation. + [4ac9c4299837] + + * tools/hatari-prg-args.sh: + add script to autorun Atari programs with arguments using Hatari + [0913059a34a0] + + * src/debug/breakcond.c, src/debug/debugInfo.c, src/debug/debugInfo.h: + expose basepage address as variable to debugger + [087f0d29ad62] + +2014-12-30 Eero Tamminen + + * doc/compatibility.html: + add TLB/oceanmachine + [3d4b72482cda] + +2014-12-29 Eero Tamminen + + * doc/compatibility.html: + update Falcon compatibility info for new WinUAE CPU core + [56c9eda446ae] + +2014-12-28 Nicolas Pomarede + + * src/cpu/newcpu.c: + Fix cycles counting when using 68040/68060 in compatible/prefetch + mode + [dc392dc09a2e] + +2014-12-28 Eero Tamminen + + * doc/release-notes.txt: + add Nicolas' updates to release notes + [03c949a41e8b] + +2014-12-28 Nicolas Pomarede + + * src/ioMemTabFalcon.c: + For Falcon, change cpu freq when writing to 0xff8007 only if CPU is + 68030 TOS 4 forces CPU freq to 16 MHz at boot, but we don't want to + apply this when running in 68040 or 68060 mode at 32 MHz + [0b30df2dccee] + + * src/statusbar.c: + Correctly display 68060 CPU type in the statusbar + [80b765ce56ab] + + * src/gui-sdl/dlgSystem.c: + Correctly init cpu frequencies when displaying System dialog + [94cc75e2c029] + + * src/options.c: + Allow --cpulevel 6 to use 68060 with new cpu core + [23aa98f8dd71] + + * src/video.c: + Don't save a memory pointer, save the video address in ST memory + space + [71cb37d475ee] + +2014-12-28 Laurent Sallafranque + + * src/falcon/dsp_core.c, src/falcon/dsp_core.h, src/falcon/dsp_cpu.c: + fix 1 bug in dsp parallel move + dsp code simplification + ea + pipeline preparation + [8b371afc21f2] + +2014-12-27 Nicolas Pomarede + + * src/gemdos.c: + Gemdos DTA was not correctly restored when using extra TT RAM + [a5d3a8fb52f0] + + * src/cart.c, src/includes/cart.h, src/memorySnapShot.c, src/reset.c: + Fix a crash when accessing HD after restoring a memory snapshot with + new WinUAE cpu When restoring a snapshot, patching cpu opcodes + should only be done at the end, after rebuilding the cpu tables + (else the patches in the cartridge used for HD gemdos emulation + could be overwritten) + [49ff2d95519c] + +2014-12-24 Nicolas Pomarede + + * tests/buserror/results/mste4_b.txt, + tests/buserror/results/mste4_w.txt: + Add bus error results for the Mega STE4. We need to add a separate + machine type "Mega STE" (thanks to Cyprian Konador for the tests) + [3d940f5465a3] + + * src/tos.c: + Update the messages when adding TT RAM and 24 bit addressing is used + - For TT, we force to 32 bit addressing + - For Falcon, we just warn the user and let him choose if he really + wants 24 bit without extra RAM or 32 bit with extra RAM + [4920d05c6b34] + + * src/blitter.c: + Allow blitter to use 32 bit for src/dst addresses in Falcon mode + with TT RAM As TOS 4.04 is supposed to be limited to 24 bit + addressing with the Falcon's 68030, there's no check in TOS to + ensure the blitter is not used with addresses above the 24 bits + limit and the TOS will try to blit between ST RAM and TT RAM, which + will crash is addresses are masked to 24 bits. + [c3e62d91bd68] + + * src/tos.c: + Patch TOS 4.04 to automatically call maddalt() when TT RAM is added + to the Falcon As TOS 4.04 is only supposed to run in 24 bit mode, it + doesn't expect extra memory to be present at address $01000000. Even + if this extra memory is validated in $5A4/$5A8, we must add it to + the TOS ourselves. We patch the TOS to call maddalt() just before + booting on the 1st drive (same method as in the CT60 extension + board) + [94f3f814e673] + +2014-12-22 Nicolas Pomarede + + * src/tos.c: + Remove another PMOVE when using TOS4.04 with 68060 As the patch + can't be stored in place, we put it in an unused memory region at + the end of the TOS 512 kB region + [3d3dab04db7b] + +2014-12-21 Nicolas Pomarede + + * src/cpu/memory.c, src/includes/stMemory.h, src/stMemory.c, src/uae- + cpu/memory.c: + Validate TT RAM at 0x01000000 when using fast boot or Falcon mode + [409aa73bd325] + + * src/cpu/newcpu.c: + In the CPU, remove some remaining get_long in log messages + [d949670441a9] + + * src/stMemory.c: + When using fast boot on TT, set bit0=1 at $ff8e09 to simulate a warm + start Else memory detection is not skipped after a cold start/reset + This worked so far, because reading $ff8e09 is not emulated yet and + always returns 0xff ; with this we're safe if emulation improves for + $ff8e09 + [4052b43e33c9] + + * src/stMemory.c: + When using fast boot on Falcon, set bit6=1 at $ff8007 to simulate a + warm start Else memory detection is not skipped after a cold + start/reset + [cc55446ed1d2] + +2014-12-20 Eero Tamminen + + * src/debug/breakcond.c: + improve debugger breakpoint address checks + + use already available function with 24/32-bit support and take also + address size into account. + [c84704b8581a] + + * tests/debugger/makefile, tests/debugger/test-breakcond.c, + tests/debugger/test-dummies.c, tests/debugger/test-evaluate.c: + better debugger tests update/fix + + when using real stMemory.c, memory banks would need to be enabled + with lots of variables (without that tests just segfault like with + previous commit). Better just to write minimal needed mem read & + write functions. To test those, changed tests to use them too. + [1226b9c04e27] + + * tests/debugger/makefile, tests/debugger/test-dummies.c: + changes needed to get debugger tests compile again + [db0e3054e3ec] + +2014-12-19 Nicolas Pomarede + + * src/debug/symbols.c: + Handle 32 bit addressing to load CPU symbols table + [8be4491463f9] + +2014-12-19 Nicolas Pomarede + + * src/cpu/newcpu.c: + In the CPU, don't use get_long in log messages as it can trigger a + bus error + [7e20d7ea48e1] + +2014-12-19 Nicolas Pomarede + + * src/debug/profilecpu.c: + In profiler, only mask PC if 24 bit addressing mode is enabled + [1e3a41c54920] + + * src/debug/68kDisass.c, src/debug/debugcpu.c: + Display memory ranges with 8 digits instead of 6 + [0ef09e455dce] + + * src/debug/breakcond.c: + Don't mask to 24 bits in BreakCond_ReadSTMemory(), this is handled + in STMemory_Read() + [345e027d98fb] + + * src/debug/debugcpu.c: + In debugger, don't limit address ranges to 24 bits in memdump/disasm + [6a262668b417] + + * src/includes/stMemory.h, src/stMemory.c: + Rewrite STMemory_Read / STMemory_Write functions to be 32 bit + compliant Previous version was limited to 24 bit addresses and + RAM/ROM. This new version can handle 32 bit accesses and any kind of + memory (including TT RAM) This fixes non working gemdos HD emulation + with TT in 32 bit modei and TOS 3.06 when DTA was located in TT RAM. + [4c53e5764c52] + + * src/cpu/memory.c, src/uae-cpu/memory.c: + Set the infos about allocated memory pointers for each mem bank This + allows direct access to a memory region in stMemory.c + [ba731ace4b37] + + * src/uae-cpu/memory.h: + Backport from new cpu core : add baseaddr/start/mask to addrbank to + directly access a memory region + [9f1020c0f470] + +2014-12-18 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [58066a7b6408] + + * src/cpu/memory.c, src/includes/stMemory.h, src/statusbar.c, + src/tos.c, src/uae-cpu/memory.c: + expose TTmemory so that statusbar knows whether TT-RAM is in use + + With this, TT-RAM config value doesn't need to be zeroed to avoid + bogus statusbar info. + [0ca5f3fbd5f0] + +2014-12-18 Nicolas Pomarede + + * src/cpu/winuae_readme.txt: + Keep track of the WinUAE's version used for the CPU : 3.0.0 + (17/12/2014) + [d4c6ff9b39aa] + +2014-12-18 Eero Tamminen + + * src/change.c, src/statusbar.c, src/tos.c: + less strict TT-RAM forcing, add WINUAE define checks + [0d39dda86acb] + +2014-12-17 Eero Tamminen + + * src/debug/debugInfo.c, src/stMemory.c: + fix recently changed "info" command CheckAreaType() calls, tell why + it fails + + CheckAreaType() is called so rarely that I think it's fine to output + from it what kind of type mismatch caused the failure. + [9c12ec4dd52e] + + * src/tos.c: + disable 24-bit addressing & fastboot for TT-RAM + [929ba85ae849] + + * src/gui-sdl/dlgMemory.c: + prefix defines (requested by Nicolas) + [7c71877c214a] + +2014-12-17 Nicolas Pomarede + + * src/configuration.c: + By default, don't patch TOS for faster boot + [c6c916adab81] + + * src/cpu/memory.c, src/tos.c: + Add support for extra TT RAM starting at address $01000000 This + requires machine to be TT and to not use 24 bit addressing. 'Patch + TOS for faster boot' should also be disabled. TOS and EmuTOS will + detect up to 2047 MB, but it seems expansion boards didn't use more + than 256 MB. + [a48cd15812ee] + + * src/configuration.c: + Fix saving of TT RAM size + [dfd4dbcce715] + +2014-12-16 Eero Tamminen + + * src/gui-sdl/dlgMemory.c, src/options.c: + TT-RAM options are available only with WinUAE CPU core + [0ec3bf9d9fae] + + * doc/hatari.1, src/change.c, src/configuration.c, src/gui- + sdl/dlgMemory.c, src/includes/configuration.h, src/options.c, + src/statusbar.c: + GUI/config/option support for specifying TT-RAM amount + + (CPU core side implementation will be provided by Nicolas soon.) + [0fd1a6f1f2f8] + +2014-12-15 Nicolas Pomarede + + * src/cpu/memory.c: + Remap memory 00xxxxxx to FFxxxxxx if MMU is disabled in 32 bit + TT/Falcon mode Some IO registers are sometimes accessed at addresses + $FFFFxxxx instead of $00FFxxxx, so we need to point our internal + memory banks to the same location. + [fbd1d8cb45c8] + + * tests/buserror/results/mst4_b.txt, + tests/buserror/results/mst4_w.txt: + Add bus error results for the Mega ST4. We need to add a separate + machine type "Mega ST" (thanks to MasterOfGizmo for the tests) + [5c79d8e481da] + + * src/fdc.c: + FDC's "Step Out" command was not correctly displayed in the status + bar + [3006e3fef00f] + + * src/cpu/debug.c: + Update cpu to latest WinUAE 3.00b28 + [6b1469ba5eba] + +2014-12-15 Eero Tamminen + + * src/debug/profilecpu.c: + enable debug for successive zero cycles, until issue is + fixed/clarified + [08a8ef685667] + + * src/debug/profilecpu.c: + fix CPU cycle counting for new WinUAE CPU core + + Patch from Nicolas for using global cycle counter. + + Now all CPU cores behave the same in regards to cycle counting, and + regardless of whether DSP is enabled or not. + [a18a7066cc71] + +2014-12-12 Eero Tamminen + + * src/hdc.c: + better error messages on ACSI image lenght check + [7524a2f7ea70] + +2014-12-12 Nicolas Pomarede + + * src/includes/stMemory.h, src/stMemory.c: + Use more generic addrbank functions in STMemory_CheckAreaType() and + STMemory_STAddrToPointer() Also take bAddressSpace24 into account + when converting ST address to direct pointer + [631d5aa8f3c6] + + * src/debug/debugInfo.c, src/debug/natfeats.c, src/gemdos.c, + src/hdc.c, src/vdi.c: + Replace STMemory_ValidArea with STMemory_CheckAreaType + [bdca7e5f4378] + + * src/includes/stMemory.h, src/stMemory.c: + Add STMemory_CheckAreaType to check that memory access are within a + valid range/memory type + [cc43421926a3] + + * src/cpu/memory.c, src/uae-cpu/memory.c, src/uae-cpu/memory.h: + Backport from new cpu core : add a flag to addrbank to store its + memory type (RAM, ROM, IO, ...) + [1bfda33e793d] + +2014-12-11 Laurent Sallafranque + + * src/falcon/dsp_core.c, src/falcon/dsp_core.h: + cosmetic change : remove all spaces at end of lines + [8e3167621f4b] + +2014-12-11 Nicolas Pomarede + + * src/debug/natfeats.c, src/gemdos.c, src/includes/stMemory.h, + src/stMemory.c, src/vdi.c, src/xbios.c: + Replace STRAM_ADDR with STMemory_STAddrToPointer + [1bb2510b7a53] + + * src/bios.c: + In debug for Bios(4), it's more useful to have the ST address than a + pointer + [e5bddf7c1093] + + * src/configuration.c, src/includes/configuration.h: + Also define bAddressSpace24 with old UAE cpu, but always force it to + true + [f9402fce04df] + +2014-12-11 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + rewrite of the loop condition according to the motorola DSP + documentation. This won't change anything, but it like it should be. + [5277eb03cc8c] + +2014-12-10 Nicolas Pomarede + + * src/floppy_stx.c, src/includes/floppy_stx.h: + Correctly check the 4 first bytes of STX files + [ea193083ff75] + + * src/cpu/CMakeLists.txt: + Fix CMakeLists.txt for new WinUAE's cpu + [aca63031cc09] + +2014-12-08 Nicolas Pomarede + + * src/cpu/CMakeLists.txt, src/cpu/build68k.c, src/cpu/compat.h, + src/cpu/cpu_prefetch.h, src/cpu/cpummu.c, src/cpu/cpummu.h, + src/cpu/cpummu030.c, src/cpu/cpummu030.h, src/cpu/custom.c, + src/cpu/custom.h, src/cpu/debug.c, src/cpu/events.c, + src/cpu/events.h, src/cpu/fpp.c, src/cpu/gencpu.c, + src/cpu/jit/compemu.h, src/cpu/jit/compemu_support.c, + src/cpu/jit/gencomp.c, src/cpu/md-fpp.h, src/cpu/memory.c, + src/cpu/memory.h, src/cpu/mmu_common.h, src/cpu/newcpu.c, + src/cpu/newcpu.h, src/cpu/newcpu_common.c, src/cpu/options_cpu.h, + src/cpu/savestate.h, src/cpu/sysconfig.h, src/cpu/table68k, + src/m68000.c: + Update WinUAE cpu core from 2.8.1 to 3.00b7 + - fixes a few MMU bugs + - fixes 68000 cycles in compatible/prefetch mode to match those of old + UAE cpu core + - fixes bug when EmuTOS would not boot with 68030 in compatible or CE + mode + - various small changes in some opcodes + [d5d4a5daa92b] + +2014-12-08 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [c63f3b8c068f] + +2014-12-08 Nicolas Pomarede + + * src/floppy_stx.c: + Remove compiler's warning with strncmp when checking STX files + [cd5d6789291d] + +2014-12-07 Thomas Huth + + * share/icons/hicolor/scalable/mimetypes/application-x-st-disk- + image.svg: + Replaced the scalable floppy icon with a repainted, cleaner version + [9448801c7660] + +2014-12-06 Eero Tamminen + + * src/gui-sdl/dlgScreen.c, src/includes/options.h, src/includes/vdi.h, + src/options.c, src/screen.c, src/vdi.c: + long overdue VDI_Limit -> Opt_ValueAlignMinMax rename/move + + - VDI_Limit() function has been used for a long time for + aligning/limiting other than VDI related configuration values. + Rename & move this functionality to options.c (it will be used there + later by TT-RAM function) + - Lines got really long in SDL dialog code, added there shorter local + variable for readability while doing the rename + - removed outdated VDI_Limit() comment in screen.c + [523c59a9db47] + + * src/statusbar.c: + change statusbar info format slightly for later TT-RAM info + [55740bea3fdf] + + * src/statusbar.c: + Fix: Statusbar msg len didn't accommodate WinUAE/FPU/MMU info + [218cf9063047] + +2014-12-06 Nicolas Pomarede + + * src/floppy_stx.c, src/includes/floppy_stx.h: + A valid .stx file should have a "RSY\0" header + [0b97ec041b6b] + +2014-12-02 Nicolas Pomarede + + * src/video.c: + Add a temporary hack for 'Gen 4 Demo' by Overlanders, don't trigger + 'left+2' on 1st line The timing used in this demo is similar to the + left+2 case on the 1st line that normally require a 2 cycle + precision. This hack is required because we only have 4 cycle + precision, but should be removed later (similar to 'Panic' by Paulo + Simoes) + [2eb9303988b3] + +2014-12-01 Nicolas Pomarede + + * src/uae-cpu/savestate.h: + Add missing prototypes + [c63e23a35f16] + + * src/cpu/CMakeLists.txt, src/cpu/build68k.c, src/cpu/compat.h, + src/cpu/cpu_prefetch.h, src/cpu/cpummu.c, src/cpu/cpummu.h, + src/cpu/cpummu030.c, src/cpu/cpummu030.h, src/cpu/custom.c, + src/cpu/custom.h, src/cpu/debug.c, src/cpu/debug.h, + src/cpu/events.c, src/cpu/events.h, src/cpu/events_jit.h, + src/cpu/events_normal.h, src/cpu/falcon_cycle030.h, src/cpu/fpp.c, + src/cpu/gencpu.c, src/cpu/hatari-glue.c, src/cpu/hatari-glue.h, + src/cpu/jit/compemu.h, src/cpu/jit/compemu_fpp.c, + src/cpu/jit/compemu_raw_x86.c, src/cpu/jit/compemu_support.c, + src/cpu/jit/comptbl.h, src/cpu/jit/gencomp.c, src/cpu/maccess.h, + src/cpu/md-fpp.h, src/cpu/memory.c, src/cpu/memory.h, + src/cpu/mmu_common.h, src/cpu/newcpu.c, src/cpu/newcpu.h, + src/cpu/newcpu_common.c, src/cpu/options_cpu.h, src/cpu/readcpu.c, + src/cpu/readcpu.h, src/cpu/rpt.h, src/cpu/savestate.h, + src/cpu/sysconfig.h, src/cpu/sysdeps.h, src/cpu/table68k, + src/debug/68kDisass.c, src/debug/debugcpu.c, src/debug/natfeats.c, + src/m68000.c, src/memorySnapShot.c, src/tos.c: + Update WinUAE's cpu from the old 2.3 version to the more recent + 2.8.1 This new core features MMU emulation for 68030/40, as well as + many improvements in "cycle exact" mode for 68000 and 68020/30. + [ac537e1d80f4] + +2014-11-28 Thomas Huth + + * src/hdc.c: + Put the hard disk response data into a separate buffer first to + separate the DMA logic from the SCSI command logic. + [ca7bdb0452db] + + * src/hdc.c: + NCR5380 is work-in-progress, so disable the code by default + [c78faf684355] + +2014-11-27 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt, src/uae-cpu/gencpu.c: + Improve exception's stack for address error and JMP (fix the game + The Teller) + [5eb411120e81] + +2014-11-26 Thomas Huth + + * src/tos.c: + Patch TOS 4.04 to work without MOVEP when running with 68060 + [71d063d22f23] + +2014-11-23 Thomas Huth + + * src/hdc.c: + Factor device init into a separate function so that it can be later + used for SCSI, too + [ddde028f2981] + +2014-07-24 Thomas Huth + + * src/configuration.c, src/includes/configuration.h: + Add SCSI devices to the configuration settings + [d81828b67d19] + +2014-11-22 Thomas Huth + + * src/fdc.c, src/hdc.c, src/includes/fdc.h: + Make sure that HDC IRQ gets cleared before analyzing a new byte + [6044e451ec4c] + +2014-11-20 Nicolas Pomarede + + * doc/release-notes.txt, src/fdc.c: + For STX disks, fix type I commands with verify bit on tracks with no + sector (fix the game 'Obitus', seek command never completed) + [26ddec584e48] + +2014-11-16 Eero Tamminen + + * doc/hatari.1, doc/manual.html, src/avi_record.c, + src/includes/avi_record.h, src/options.c: + add --png-level option + [5449e91a3e3f] + + * doc/emutos.txt: + update etos compat info + [57b38a3c0c7a] + + * src/gui-sdl/dlgJoystick.c, src/includes/configuration.h, + src/includes/joy.h, src/joy.c: + fix: potential initial statusbar & GUI joy state mismatch + + Same check needs to be done at startup as is done in Joystick + dialog, otherwise statusbar and dialog will show different Joy + settings when Joy Id has changed from configured. + [8e52c3ed2e93] + + * src/statusbar.c: + remove redundant flag set/check + [edaa7c4d2738] + +2014-11-14 Thomas Huth + + * share/CMakeLists.txt, share/applications/hatari.desktop, + share/icons/hicolor/128x128/mimetypes/application-x-msa-disk- + image.png, share/icons/hicolor/256x256/mimetypes/application-x-msa- + disk-image.png, share/icons/hicolor/32x32/mimetypes/application-x + -msa-disk-image.png, + share/icons/hicolor/48x48/mimetypes/application-x-msa-disk- + image.png, share/icons/hicolor/64x64/mimetypes/application-x-msa- + disk-image.png, share/icons/hicolor/scalable/mimetypes/application-x + -msa-disk-image.svg, share/mime/packages/hatari.xml: + All disk types (MSA, STX and DIM) now use the same icon as the .ST + images + [b5b83b218ef3] + +2014-11-10 Thomas Huth + + * share/CMakeLists.txt, + share/icons/hicolor/128x128/mimetypes/application-x-msa-disk- + image.png, share/icons/hicolor/128x128/mimetypes/application-x-st- + disk-image.png, share/icons/hicolor/256x256/mimetypes/application-x + -msa-disk-image.png, + share/icons/hicolor/256x256/mimetypes/application-x-st-disk- + image.png, share/icons/hicolor/32x32/mimetypes/application-x-msa- + disk-image.png, share/icons/hicolor/32x32/mimetypes/application-x + -st-disk-image.png, + share/icons/hicolor/48x48/mimetypes/application-x-msa-disk- + image.png, share/icons/hicolor/48x48/mimetypes/application-x-st- + disk-image.png, share/icons/hicolor/64x64/mimetypes/application-x + -msa-disk-image.png, + share/icons/hicolor/64x64/mimetypes/application-x-st-disk-image.png, + share/icons/hicolor/scalable/mimetypes/application-x-msa-disk- + image.svg, share/icons/hicolor/scalable/mimetypes/application-x-st- + disk-image.svg, share/mime/packages/hatari.xml: + Add icons and mimetype definitions for .ST and .MSA disk images + [894108a79865] + + * share/CMakeLists.txt, share/applications/hatari.desktop: + Add hatari.desktop file for the main executable + [af5b141a53f0] + +2014-11-08 Thomas Huth + + * share/CMakeLists.txt, share/icons/hicolor/64x64/apps/hatari.png: + Add a 64x64 icon, too + [0962705bb8ea] + + * share/CMakeLists.txt, share/icons/hicolor/scalable/apps/hatari.svg: + Add a scalable version of the H icon + [312d19370bc6] + +2014-11-07 Thomas Huth + + * CMakeLists.txt, python-ui/CMakeLists.txt, python- + ui/hatariui.desktop, share/CMakeLists.txt, + share/icons/hicolor/128x128/apps/hatari.png, + share/icons/hicolor/256x256/apps/hatari.png, + share/icons/hicolor/32x32/apps/hatari.png, + share/icons/hicolor/48x48/apps/hatari.png: + Provide desktop icons with higher resolutions + [a25e74f89132] + +2014-11-03 Eero Tamminen + + * src/hdc.c: + partition is valid only if bit 1 is set + [1fc4d1648073] + + * src/hdc.c: + add TODOs for partition counting + [20ccea07781f] + + * doc/manual.html: + update hard disk section in manual + [4ef2d8b0ff5b] + + * CMakeLists.txt, cmake/config-cmake.h, doc/release-notes.txt, + src/file.c, src/hdc.c, src/ide.c, src/includes/file.h: + add advisory locking for HD images on systems with flock() + [ed60df214f1b] + +2014-11-02 Eero Tamminen + + * doc/emutos.txt: + add laserball + [1a9e6ef5fa16] + +2014-10-28 Nicolas Pomarede + + * src/memorySnapShot.c, src/zip.c: + Fix compilation when zlib is not available + [0118399fa0cd] + +2014-10-26 Nicolas Pomarede + + * src/cpu/hatari-glue.c, src/uae-cpu/hatari-glue.c: + Don't restore SR after a natfeat command + [52d443f2f240] + +2014-10-20 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [d3c31721816d] + +2014-10-19 Eero Tamminen + + * doc/emutos.txt: + improve wording + more consistent line wrapping + [17cfea04a29f] + +2014-10-17 Thomas Huth + + * src/gemdos.c, src/includes/gemdos.h, src/vdi.c: + Use GemDOS_IsDriveEmulated() to check for GEMDOS C: drive + [0bf4ab820d62] + +2014-10-16 Thomas Huth + + * src/ide.c: + Silence compiler warnings + [1ce41134a291] + + * src/gemdos.c: + GemDOS_CreateHardDriveFileName should only be called with valid + drives so use assert() here instead + [bfd4047209b5] + +2014-10-14 Eero Tamminen + + * doc/keymap-sample.txt: + update keymap comments for --trace keymap + [a6ea14519c7a] + +2014-10-13 Eero Tamminen + + * src/change.c, src/gui-sdl/dlgHardDisk.c: + add SDL GUI option for GEMDOS HD to skip ACSI/IDE partitions + [02093c7e2c2e] + + * src/options.c: + add option to specify GEMDOS HD drive + + Either directly with drive letter, or asking GEMDOS HD letter + assignation to skip known partitions. + [e84738287305] + + * src/configuration.c, src/gemdos.c, src/includes/configuration.h: + make GEMDOS HD skipping ACSI/IDE drives configurable + + - rename (previously unused) nHardDiskDir configuration variable to + more appropriate nHardDiskDrive and save it with config + + - add DRIVE_SKIP define and only if nHardDiskDrive option has that + value, skip ACSI/IDE partitions detected from drive images MBR [1] + + - by default assign GEMDOS drive to C: + + [1] This parses only Atari & DOS 4 primary partitions table, not the + extended ICD 8 one, no or logical partitions. Neither will it (yet) + handle IDE MBR created with non-host byte order. + + Additionally, native Atari HD drivers can parse partition table + information differently from each other, even when they're installed + and get run succesfully at boot, so automatic skipping is just a + "best effort" convenience feature. + [9428148df300] + +2014-10-12 Eero Tamminen + + * src/options.c: + improve error message + + (permissions aren't necessarily wrong :)) + [c8892e1e2725] + +2014-10-12 Thomas Huth + + * src/file.c: + Fix File_Exists() for block devices + [6ff33df519ca] + + * src/vdi.c: + Modify DESKTOP.INF only when using GEMDOS C: drive + [bcebaaebc880] + + * src/gemdos.c: + Make sure that we really operate on a GEMDOS HD when creating a file + name + [64922e31475f] + + * src/gemdos.c: + Avoid initializing GEMDOS HD emulation with illegal host folders + [7e4fd87bfaae] + +2014-10-12 Eero Tamminen + + * tests/readme.txt: + document natfeats subdir in tests readme + [08360856dd61] + +2014-10-11 Eero Tamminen + + * src/gemdos.c: + fix: file writability check was inverted + [3635572fe94a] + + * doc/manual.html: + improve debugger doc wording + [8070bf77b9b2] + +2014-10-03 Thomas Huth + + * src/fdc.c, src/hdc.c: + Revert the ff8604 longword hack, and rather ignore the A1 line for + the second byte + [d910217ea576] + + * src/hdc.c: + Fix the newlines of the scsi_cmd log statements + [069aefb0968f] + + * src/fdc.c, src/ioMem.c: + Add the possibility to access ff8604 and ff8606 with one longword + access + [8ed1d7ad9175] + +2014-10-02 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [26ee49bf32ad] + +2014-09-30 Eero Tamminen + + * src/ide.c: + remove IDE trace output from bus error paths + + According to Nicolas, other (HW) trace options don't do that either. + [02fde9d52a29] + + * src/gemdos.c, src/hdc.c, src/ide.c, src/includes/hdc.h, + src/includes/ide.h: + skip IDE partitions when assiging GEMDOS HD drive + + This required: + - adding partition counting also for IDE + - supporting DOS MBR as those are more common with IDE images than + Atari MBR + + This was done by adding DOS MBR support to current hdc.c (ACSI) + Atari MBR parsing and generalizing it so that IDE code can use the + same function. + + ACSI partition count was renamed to differentiate it from IDE one, + and gemdos.c GEMDOS HD drive assignment changed to take into account + both partition counts. + + NOTE:: only primary partitions are counted, but drives can use also + extended partitions. ICD drivers supports up to 8, and DOS MBR has + several extension mechanisms. + [084bf14534ec] + +2014-09-29 Eero Tamminen + + * src/debug/log.c, src/debug/log.h, src/ide.c: + add IDE tracing support + [c1276a988b1b] + +2014-09-27 Nicolas Pomarede + + * src/blitter.c: + Allow blitter to access any memory, not just RAM and IO registers + Fix IDE driver for Falcon by Peter Putnik which accesss + $ff0000-$ff0040 using the blitter + [7a5973eb8ae1] + + * src/m68000.c: + As verified on STE, there's no bus error when read or write access + is made by the blitter + [1178558c213f] + +2014-09-26 Eero Tamminen + + * src/hdc.c: + add OK/ERROR output to HDC traces + [48335f968c57] + +2014-09-25 Eero Tamminen + + * src/gemdos.c: + fix typo in Fopen() trace info array + [44fb1b64d3a0] + +2014-09-22 Eero Tamminen + + * doc/manual.html: + improve multi-partition GEMDOS HD emu docs + [63f5d2d9d1d3] + + * doc/release-notes.txt: + update release notes + [9d347bef38d7] + + * src/memorySnapShot.c: + make snapshot save/restore more robust + + - version match should be exact + - store & check which CPU core is used + - store & check state data end marker + - tell user that he should reboot if state restore fails + - update snapshot version + [64eb1fad5e56] + + * src/cpu/fpp.c, src/cpu/savestate.h, src/m68000.c: + fix: WinUAE CPU FPU state save/restore + + Depending on whether FPU happened to be enabled at restore time, + WinUAE CPU code could save different amount of data, which naturally + mismatches what got read with the default Falcon state of FPU being + disable. + + Fix this by removing FPU model check and the redundant differences + to oldUAE FPU state/restore API. + [ec394d4daadb] + +2014-09-21 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Update notes for buggy version of Blood Money on Superior 65 + compilation + [3f75b6bfdf4e] + +2014-09-20 Thomas Huth + + * src/gui-sdl/font10x16.bmp, src/gui-sdl/font10x16.h, src/gui- + sdl/font5x8.bmp, src/gui-sdl/font5x8.h: + Added missing characters for cp1252. + [4143fb064bb9] + +2014-09-19 Eero Tamminen + + * doc/emutos.txt: + EmuTOS Falcon resolution <-> mouse issue was fixed few months ago + [820d892d41e4] + +2014-09-13 Thomas Huth + + * CMakeLists.txt: + Switch to SDL_MAIN_NEEDED, seems to work better + [1d477ef60566] + +2014-09-12 Thomas Huth + + * CMakeLists.txt: + Fixed stupid typo in CMakeLists.txt + [b1343f9ad56a] + +2014-09-11 Thomas Huth + + * CMakeLists.txt, src/main.c: + Only redefine main on OS X if bundle is enabled + [63c19ea1a91f] + +2014-09-09 Nicolas Pomarede + + * doc/release-notes.txt: + Update release notes + [e092c395d703] + +2014-09-07 Nicolas Pomarede + + * src/uae-cpu/gencpu.c, src/uae-cpu/newcpu.c, src/uae-cpu/newcpu.h: + Improve 'special status' word in the stack after an address error + (fix Blood Money on Superior 65) + [eb085b1e3f9e] + + * src/uae-cpu/newcpu.c: + If fetching the next opcode triggers a bus error, we must call the + bus error handler immediately + [8c9481b8253b] + +2014-09-02 Nicolas Pomarede + + * src/uae-cpu/newcpu.c: + Correctly increment address when disassembling in a bus error region + [2b668dbb98d4] + + * src/uae-cpu/memory.c: + Don't put debugging message in memory _check functions used by + valid_address() valid_address() is only used internally before + accessing a memory region, so there's no point in printing debug + messages, else it will print text in the middle of the disassembly + when accessing memory in a bus error region + [2836b20cae95] + + * src/m68000.c: + Print PC value when a bus error occurs + [802f09c0a069] + + * src/debug/68kDisass.c, src/uae-cpu/newcpu.c: + When disassembling, don't call get_word if the region is not valid + (bus error) This would create extra bus errors when disassembling, + which is not correct, only cpu execution should create bus error, + not debugger functions + [0b3da84ca6b4] + +2014-08-29 Eero Tamminen + + * src/midi.c: + trace message also about MIDI error stop + [462c37311fd1] + + * doc/release-notes.txt, src/debug/log.c, src/debug/log.h, src/midi.c: + add tracing support for MIDI + [f579dd7a6793] + + * tools/hatari-local-midi-ring.sh, tools/hatari-local-rs232.sh: + improve midi/rs232 test script error handling + [ec5970417e24] + +2014-08-28 Eero Tamminen + + * doc/release-notes.txt: + add note of joystick changes to release notes + [502c2a0c5501] + + * src/gui-sdl/sdlgui.c: + add joystick navigation to SDL GUI + [c3e65996ee22] + +2014-08-27 Eero Tamminen + + * doc/hatari.1, src/configuration.c, src/includes/configuration.h, + src/includes/joy.h, src/joy.c, src/shortcut.c: + shortcuts for switching joystick/pad types + [52c341fd1b5b] + +2014-08-26 Eero Tamminen + + * doc/compatibility.html: + add notes about Kronos and Statistician + [744674c23462] + +2014-08-26 Thomas Huth + + * src/gui-sdl/sdlgui.c: + Fixed compilation problem with SDL2 + [28bad458b7f4] + +2014-08-25 Eero Tamminen + + * src/gui-sdl/dlgJoystick.c: + fix: SDL GUI joy dialog tab switching + [6ba71e551a80] + + * doc/hatari.1, src/gui-sdl/dlgFileSelect.c, src/gui- + sdl/dlgJoystick.c, src/gui-sdl/dlgNewDisk.c, src/gui- + sdl/dlgScreen.c, src/gui-sdl/sdlgui.c, src/includes/sdlgui.h: + keyboard shortcut handling improvements / SDL2 compatibility + + - Underlined shortcuts are triggered with Alt, like on Desktop + - Fileselector button texts change so that shortcuts are normal + letters + - Arrow shortcuts specified separately to avoid need for SDL1 specific + key event unicode field + - Separate field in structs for shortcut key + + All current SDL GUI shortcuts will now hopefully work also with + SDL2. + [5b2d1e868a69] + +2014-08-25 Thomas Huth + + * src/debug/log.c, src/debug/log.h, src/keymap.c: + Added tracing for keymapping + [6e3df1ed4636] + +2014-08-24 Eero Tamminen + + * src/debug/debugui.c: + improve setopt command help + [8d9f81e380ef] + + * doc/release-notes.txt, src/debug/debugui.c: + add reset debugger command + [4eb64c7284a0] + +2014-08-24 Nicolas Pomarede + + * readme.txt: + Hatari can be linked with capslib 4.2 or 5.1 + [deff43c32640] + + * doc/release-notes.txt: + Update release notes + [85c0bf412b9e] + + * src/configuration.c, src/debug/68kDisass.c, src/debug/68kDisass.h: + When CPU/FPU change, update mask for the external disassembler For + example, when in 68000 mode, only show valid 68000 opcodes, not all + 680x0 opcodes + [bf64da7bbd44] + +2014-08-19 Thomas Huth + + * src/gui-osx/PrefsController.m, src/gui-osx/Shared.m: + Correction for the last correction for deprecated OS X functions. + Thanks to Miguel Saro for the patch. + [0880434ab725] + +2014-08-18 Thomas Huth + + * src/gui-osx/PrefsController.m, src/gui-osx/SDLMain.m, src/main.c: + Some more fixes for compiling with SDL2 on Mac OS X + [1a3adb1b3152] + +2014-08-17 Eero Tamminen + + * doc/release-notes.txt, src/gui-sdl/sdlgui.c, src/includes/str.h, + src/str.c: + use same logic for UTF-8 conversion as Max' GEMDOS code + + Currently only file names will / can have non-ASCII letters in the + SDL GUI. + + It's not possible to reliably know what encoding file names use as + that's a mount option user can specify. However: + - On linux distros UTF-8 is nowadays the default + - According to Max, it works also on OSX + + So, similarly to Max' GEMDOS HD conversion code, assume UTF-8 unless + we're on Windows or UTF-8 conversion is explicitly overridden with + USE_LOCALE_CHARSET. + + In latter case code assumes that charset is 8-bit one and closer to + latin1 encoding used by the font, than what UTF-8 conversion would + produce, and does no conversion (font encoding is latin1). + + If / when translations are added, UTF-8 conversion will be + unconditional, but there's conditional conversion needed from host + to UTF-8 encoding when file names are read in. + [18803a9273a7] + + * src/gui-sdl/sdlgui.c, src/includes/sdlgui.h: + fix shortcut bit clearing + [902cea24b3ff] + + * src/gui-sdl/sdlgui.c: + initial UTF-8 -> latin1 SDL GUI font index conversion + + Based on Thomas' code in SDL Ballerburg. + + Currently only file paths can be anything else than ASCII, but if + translations are added for the GUI, they should be UTF-8. + [7741ebfc1fc2] + + * src/gui-sdl/dlgDevice.c, src/gui-sdl/dlgFileSelect.c, src/gui- + sdl/dlgFloppy.c, src/gui-sdl/dlgHardDisk.c, src/gui- + sdl/dlgJoystick.c, src/gui-sdl/dlgKeyboard.c, src/gui-sdl/dlgMain.c, + src/gui-sdl/dlgMemory.c, src/gui-sdl/dlgNewDisk.c, src/gui- + sdl/dlgRom.c, src/gui-sdl/dlgScreen.c, src/gui-sdl/dlgSound.c, src + /gui-sdl/dlgSystem.c: + remove (now redundant) SG_SHORTCUT_KEY macro use + + leave them for arrow shortcuts as those don't have text which could + specify the shortcut. + [a64001c77c60] + + * src/gui-sdl/sdlgui.c: + get shortcut keys from item texts at run-time + + This way key doesn't need to be specified twice in dialog structs + (using macro and into text), and it will work also if translations + are (at some time in future) loaded into GUI instead of texts being + hardcoded. + [64d3aba1fee1] + +2014-08-17 Thomas Huth + + * CMakeLists.txt: + Set ENABLE_SDL2 as proper build feature variable + [d60cb6a7f8c2] + + * src/gui-sdl/sdlgui.c: + Use symbolic KEYDOWN events for shortcuts on SDL2 + [77e0ed6a118e] + +2014-08-17 Eero Tamminen + + * src/gui-sdl/sdlgui.c: + hopefully fix SDL2 build issue + + (don't have setup to test it) + [721bbe637221] + + * doc/hatari.1, src/gui-sdl/dlgDevice.c, src/gui-sdl/dlgFileSelect.c, + src/gui-sdl/dlgFloppy.c, src/gui-sdl/dlgHardDisk.c, src/gui- + sdl/dlgJoystick.c, src/gui-sdl/dlgKeyboard.c, src/gui- + sdl/dlgMemory.c, src/gui-sdl/dlgNewDisk.c, src/gui-sdl/dlgRom.c, src + /gui-sdl/dlgScreen.c, src/gui-sdl/dlgSound.c, src/gui- + sdl/dlgSystem.c: + add keyboard shortcuts to rest of dialogs + [b1932dba3bea] + +2014-08-16 Eero Tamminen + + * doc/hatari.1, src/gui-sdl/dlgFileSelect.c, src/gui-sdl/sdlgui.c: + add special character key shortcuts to filesel buttons + + So that normal letters can be used to shortcut positions in file + list... + [61db0b679df0] + + * src/gui-sdl/dlgScreen.c: + add keyboard navigation to atari & hatari screen dialogs + [9bad0cf14cea] + + * doc/hatari.1, src/gui-sdl/sdlgui.c: + keyboard navigation improvements + + - also space activates focused item + - numbers can be used as shortcuts + - update these & previous filesel change to manpage + [401134bc99dc] + + * doc/compatibility.html: + add note about Cybernetics demos / writer.prg + [90ab7cd0a865] + +2014-08-16 Thomas Huth + + * src/resolution.c: + Slightly improve resolution code for SDL2 + [0866e0e6dc84] + + * src/falcon/hostscreen.c: + Fix height scaling in window size calculation + [54625828c180] + + * src/screen.c: + Check for bit depth 24 in SDL2 code, just in case + [b4877277e312] + + * src/gui-sdl/dlgFileSelect.c: + Use OK instead of Okay, as it is used in the other dialogs already + [cd45340a92f8] + + * src/gui-sdl/dlgFileSelect.c: + A hack to get rid of GCC warning + [3b57a6469661] + + * src/gui-sdl/dlgFileSelect.c, src/gui-sdl/sdlgui.c: + Add the possibility to control the entries in the file selector with + the cursor keys + [e6c1fa40624e] + + * src/gui-sdl/sdlgui.c: + Use a better color for the focus + [4d32bd2595e1] + + * src/cycInt.c, src/fdc.c: + Include inttypes.h for definition of PRIu64. Thanks to Max Böhm for + the hint. + [76f880338d72] + +2014-08-15 Nicolas Pomarede + + * doc/release-notes.txt: + Update cpu's changes in release notes + [417436f606b9] + + * src/uae-cpu/gencpu.c: + CPU fix : generate an address error if return PC is odd for RTE, RTS + and RTR + [f98d8d4d760f] + +2014-08-15 Eero Tamminen + + * doc/hatari.1, src/gui-sdl/sdlgui.c: + SDL GUI focus can be changed also with TAB + [d0ef89465bc0] + + * doc/release-notes.txt, src/gemdos.c: + fix GEMDOS trace crash without GEMDOS HD emulation + [f03e35d6cbaf] + +2014-08-15 Nicolas Pomarede + + * src/cpu/table68k, src/uae-cpu/table68k: + CPU fix : RTD does not exist for 68000, only for >= 68010 (thanks to + Peter Putnik for his opcodes validator program) + [de73e8810d6f] + + * src/uae-cpu/gencpu.c, src/uae-cpu/readcpu.c: + CPU fix : cancel change from 2008/04/26, MOVE.B is not valid with An + as source (thanks to Peter Putnik for his opcodes validator program) + [f9e0ce5ab276] + + * doc/authors.txt: + Update notes in contributors' list + [15eea4f58b31] + + * src/cpu/table68k, src/uae-cpu/table68k: + CPU fix : TST is not allowed with #imm, An and d(PC) in 68000 mode + (thanks to Peter Putnik for his opcodes validator program) + [6451175cd5d0] + +2014-08-14 Thomas Huth + + * src/gui-osx/English.lproj/SDLMain.nib/designable.nib, src/gui- + osx/English.lproj/SDLMain.nib/keyedobjects.nib: + Update the language in the SDLMain.nib, too + [7a9ba58915f7] + +2014-08-14 Eero Tamminen + + * doc/hatari.1, src/gui-sdl/sdlgui.c: + improvements to SDL GUI keyboard navigation + + - Remove Space key, Enter is now exclusively for selecting the + focused item. By default it's on default item so if user doesn't + navigate keyboard, it works like earlier. + - Add Home / End key for moving to first & last item + - Update manual page + [5e325e1f73de] + +2014-08-14 Thomas Huth + + * src/gui-osx/English.lproj/SDLMain.xib: + Switch language of English.lproj/SDLMain.xib back to english + [b8c5257bc758] + + * src/screen.c: + Stop recording before changing the resolution + [da5495966100] + + * src/gui-sdl/dlgFileSelect.c: + White space cleanup + [6552e7c31363] + +2014-08-14 Eero Tamminen + + * src/str.c: + fix compile warning + [2ef14c72d27c] + +2014-08-13 Eero Tamminen + + * src/gemdos.c: + define for value + typo fix + [0cd0941339cb] + + * doc/authors.txt, doc/release-notes.txt, src/gemdos.c, + src/includes/str.h, src/str.c: + code from Max Böhm for mapping host<->Atari file name encodings + [5c2218f0e65f] + +2014-08-13 Nicolas Pomarede + + * src/fdc.c: + Use LOG_TRACE instead of fprintf (after Log_Default() was called) + [e78511035a79] + + * src/debug/log.c, src/debug/log.h, src/main.c: + Logs default to stderr at start Without this, we had some segfaults + in case --trace was used in Main_Init_HW() before options/parameters + were parsed + [85e6fcaa80b0] + + * src/gemdos.c: + Don't print directly to TraceFile, use LOG_TRACE_PRINT + [79b775027654] + +2014-08-13 Eero Tamminen + + * doc/hatari.1, doc/manual.html: + add Windows console info to more places + [f6d0d9eb98b5] + + * doc/release-notes.txt: + add note of host->gemdos error mapping improvement + + (which went in accidentally in my previous commit) + [447a419156cf] + +2014-08-13 Nicolas Pomarede + + * CMakeLists.txt, cmake/config-cmake.h, src/gui-sdl/dlgFileSelect.c: + In cmake, check if the 'dirent' struct has a 'd_type' member The + d_type member is not mandatory in the dirent struct and some OSes / + toolchains don't provide it (mingw for example) + [5c66eb71ade9] + +2014-08-13 Eero Tamminen + + * src/gemdos.c, src/gui-sdl/dlgFileSelect.c: + support folder sorting for system without d_type field + [93dc9f007c29] + +2014-08-12 Eero Tamminen + + * doc/release-notes.txt, src/gui-sdl/dlgFileSelect.c: + sort file selector items case-insensitively with folders first + [f45e3bf27f6c] + + * src/gui-sdl/sdlgui.c: + fix button text centering with underlines + [ff197d8a5b59] + +2014-08-12 Thomas Huth + + * src/gui-osx/SDLMain.m: + White space cleanup + [1a7bb5ca1173] + + * src/gui-osx/SDLMain.m: + Mac OS X 10.9 no longer uses the -psn_XXX command line arg for + Finder launches. Patch based on upstream SDL 1.2 fixes. Thanks to + Bob Carpenter for testing it with Hatari. + [6f049907b727] + +2014-08-11 Nicolas Pomarede + + * doc/release-notes.txt: + Add cpu changes to release notes + [7883a194008d] + +2014-08-11 Thomas Huth + + * src/gui-sdl/dlgJoystick.c: + Fixed joystick dialog problem (keyboard and real joystick were + swapped) + [65153a724f39] + +2014-08-11 Nicolas Pomarede + + * src/cpu/table68k, src/uae-cpu/table68k: + CPU fix : BTST #n is not allowed with immediate value as destination + [2d5ed9d288b4] + + * src/cpu/table68k, src/uae-cpu/table68k: + CPU fix : CMPI is not allowed with d(PC) ea in 68000 mode, only in + 68020+ (fix 'Pole Position' preview on atari-forum, game should + crash in 68000 mode) + [e388b8dd4d0a] + +2014-08-11 Eero Tamminen + + * src/gui-sdl/dlgJoystick.c: + fixes to SDL GUI joystick dialog + + - fix radio buttons my previous commit broken (group needs to be + consecutive) + - fix for first key definition, need to drain queue from keys coming + e.g. from keyboard navigation + [5f50b6909a70] + +2014-08-10 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [1497c32143bc] + + * src/gui-sdl/sdlgui.c: + fix: don't draw underline for editfield (content) + [c0add4b2e3b3] + + * src/gui-sdl/dlgMain.c: + indicate Q shortcut + [7af7b0eab675] + + * doc/hatari.1: + update SDL GUI key documentation + [73e919759e40] + + * src/gui-sdl/sdlgui.c: + set focus at dialog start only if it's missing + + This makes file selector to behave sensibly and using interactive + buttons like arrows doesn't reset focus back to default button. + [a3ab39e34721] + + * src/gui-sdl/dlgJoystick.c: + order joy dialog widgets in visual order + + Otherwise focus changes works illogically + [319659d58f7c] + + * src/gui-sdl/dlgMain.c, src/gui-sdl/sdlgui.c: + support keyboard shortcuts also for other than button widgets + [bc33d55a1ba2] + + * src/gui-sdl/sdlgui.c: + indent switch similarly to other one in same function + [9a8a61192ece] + + * src/gui-sdl/dlgNewDisk.c: + enable keyboard navigation for dialog + [5ae44dbb033b] + + * doc/manual.html: + document -W + [d8bd02be059d] + + * src/gui-sdl/dlgDevice.c, src/gui-sdl/dlgFileSelect.c, src/gui- + sdl/dlgFloppy.c, src/gui-sdl/dlgHardDisk.c, src/gui-sdl/dlgMain.c, + src/gui-sdl/dlgMemory.c, src/gui-sdl/dlgScreen.c, src/gui- + sdl/dlgSound.c, src/gui-sdl/dlgSystem.c: + correct object widths for focus highlighting + [4aaf8636caba] + + * doc/hatari.1, src/gui-sdl/sdlgui.c, src/includes/sdlgui.h: + major improvements to keyboard SDL GUI navigation + + - less weird MOUSEUP handling + - focus is in state member, not in flags + - space selects focused item, enter the default + - support radio buttons & checkboxes + + Last one required quite a bit of refactoring, but now it's easier to + add other widget types for keyboard navigation. + [363ef7e04f42] + + * src/gui-sdl/sdlgui.c, src/includes/sdlgui.h: + add SDL GUI button focus keyboard navigation + [e1b65a2943cd] + + * src/gui-sdl/dlgMain.c: + add shorcut also for Quit button + [664360fb6d0e] + + * src/gui-sdl/sdlgui.c: + move color specifications into single place + + With this whole GUI color scheme changes get easier, they could + later even be made configurable. + [a793d852dc52] + + * doc/hatari.1: + fix previous commit + [8f543d01efbd] + + * doc/hatari.1: + improve manual page + + - add empty lines before section headings so that it's easier to + notice them when scrolling + - add information for SDL GUI keyboard shortcuts + - re-order keyboard section & update its subsection headings for + clarity + [569b85a87bd0] + +2014-08-10 Thomas Huth + + * src/joy.c: + Fixed extended firebuttons for joypad B + [0544623c0ebe] + +2014-08-09 Eero Tamminen + + * src/gui-sdl/dlgDevice.c, src/gui-sdl/dlgFileSelect.c, src/gui- + sdl/dlgFloppy.c, src/gui-sdl/dlgHardDisk.c, src/gui- + sdl/dlgKeyboard.c, src/gui-sdl/dlgMain.c, src/gui-sdl/dlgMemory.c, + src/gui-sdl/dlgNewDisk.c, src/gui-sdl/dlgRom.c, src/gui- + sdl/dlgSound.c, src/includes/sdlgui.h, src/shortcut.c: + Add title to SDL GUI file selector + + This has annoyed me for a long time. With SDL GUI keyboard shortcuts + user is even less sure what he (e.g. accidentally) invoked, so it's + better to have it stated in fsel explicitly. + [e579332ce3a8] + + * src/gui-sdl/dlgMain.c, src/gui-sdl/sdlgui.c, src/includes/sdlgui.h: + keyboard shorcut support for SDL GUI + [b4486db91003] + + * src/joy.c: + add joypad debug + use Uint16 to avoid overflow + [200bda94b48b] + + * src/joy.c: + fix: STE pad A Option button value + [99eafbac245c] + + * src/debug/debugui.c, src/debug/history.c: + add save subcommand to history + [b6544652fa09] + + * doc/compatibility.html: + tymewarp issue is minor + + There's now bus error handling hack in Hatari to get demo started, + so downgrading the issue to minor. + [593d687f4dbd] + +2014-08-08 Thomas Huth + + * src/gui-osx/French.lproj/Localizable.strings: + Update for the French OS X localization. Thanks to Miguel & Jerome + for the patch. + [c1180f88a852] + + * src/gui-osx/English.lproj/InfoPlist.strings, src/gui- + osx/English.lproj/Localizable.strings, src/gui- + osx/English.lproj/SDLMain.nib/designable.nib, src/gui- + osx/English.lproj/SDLMain.xib, src/gui- + osx/French.lproj/InfoPlist.strings, src/gui- + osx/French.lproj/Localizable.strings, src/gui- + osx/French.lproj/SDLMain.nib/designable.nib, src/gui- + osx/French.lproj/SDLMain.xib, src/gui-osx/PrefsController.m, src + /gui-osx/Shared.m: + Three corrections for the OS X part of Hatari. 1- correction of + values sent back by NSAlert 2- Resolving differences between + localized files: InfoPlist.strings, Localizable.strings, SDLMain.nib + 3- "default folder choice" correction (for config file). cfg file + can be read-writed anywhere, but you can select the default folder + directly. Thanks to Miguel Saro for the patch! + [a624e0eabc05] + +2014-08-07 Nicolas Pomarede + + * doc/compatibility.html: + Update Tyme Warp in compatibility list + [c91dd6fda5f4] + +2014-08-07 Eero Tamminen + + * src/configuration.c, src/includes/screen.h, + src/includes/statusbar.h, src/options.c, src/resolution.c, + src/statusbar.c: + fix incorrect screen size values for 2-line statusbar + + - add defines for magic values (max Atari screen width, max + statusbar height) so they're easier to find & replace + - correct max window size for 2-line statusbar + - output optimal size to console so that bad config values are easier + to notice + [a7737fb8db39] + + * src/convert/low320x8.c, src/convert/vdi16.c: + remove redundant initializations + + continuing Thomas' earlier conversion code cleanup... + [033af68ffe17] + +2014-08-07 Thomas Huth + + * doc/emutos.txt, doc/hatari.1, doc/release-notes.txt: + Fix some typos + [96c591ecf684] + + * src/screen.c: + Free SDL2 resources during shutdown + [0528e5f3228c] + + * src/gui-osx/PrefsController.m: + Include keymap.h for SDLK_* compatibility definitions + [2b8d610f56e4] + + * src/includes/keymap.h, src/keymap.c: + Reworked symbolic key mapping so that it works with SDL2, too + [520ba958ed9b] + +2014-08-05 Thomas Huth + + * src/control.c: + Enable window reparenting with SDL2 + [748dc5bc13cf] + +2014-08-04 Thomas Huth + + * doc/release-notes.txt: + Add information about SDL2 to the release notes + [1f0fcab409b9] + + * src/gui-osx/SDLMain.h, src/gui-osx/SDLMain.m: + Clean up comments in SDLMain.m and SDLMain.h + [9c94a6e88ac1] + + * CMakeLists.txt, cmake/FindSDL2.cmake: + Print information about SDL version during build configuration + [3bf84191a21e] + +2014-08-03 Thomas Huth + + * CMakeLists.txt: + Reworked the library summary to fit in 80 columns and to be aligned + with tabs + [235d95f4d17f] + + * src/gui-osx/AlertHooks.m, src/gui-osx/CreateFloppyController.m, src + /gui-osx/English.lproj/Localizable.strings, src/gui- + osx/PrefsController.m, src/gui-osx/SDLMain.m, src/gui-osx/Shared.h, + src/gui-osx/Shared.m: + Method NSRunAlertPAnel is deprecated since OSx 10.6. Must be + replaced by alertWithMessageText:defaultButton:alternateButton:other + Button:informativeTextWithFormat: which is deprecated in OSx 10.9. + So change all in agreement with Apple documentation into [[NSAlert + alloc] init]. Thanks to Miguel Saro for the patch! + [372eb808cd31] + + * src/configuration.c: + Save/load the SDL2 keyboard shortcuts from/to a different section + [fc13186d7ced] + +2014-06-26 Thomas Huth + + * src/dialog.c, src/gui-sdl/dlgAlert.c: + Make sure that SDL2 relative mouse mode is disabled in GUI + [6bbb339008be] + +2014-06-17 Thomas Huth + + * src/main.c, src/shortcut.c: + Remaining minor fixes for compiling with libSDL2 + [14434f878d29] + +2014-07-02 Thomas Huth + + * src/includes/keymap.h, src/keymap.c: + A quick hack to get the keyboard code running with libSDL2 + [3466e53d9db3] + +2014-07-24 Thomas Huth + + * src/control.c, src/falcon/hostscreen.c, src/includes/screen.h, + src/resolution.c, src/screen.c: + Adapt screen code to work with libSDL2, too + [676be1c07802] + +2014-07-02 Thomas Huth + + * src/gui-sdl/dlgFileSelect.c, src/gui-sdl/sdlgui.c: + Rework the sdl-gui to be compilable with libSDL2 + [438d9dd0c3d5] + +2014-06-26 Thomas Huth + + * src/gui-sdl/dlgJoystick.c, src/includes/joy.h, src/joy.c: + Fixed the joystick code to work with libSDL2 + [9b7ae20910bc] + +2014-06-17 Thomas Huth + + * src/rs232.c: + Reworked rs232 code for libSDL2 + [a7dfc3a50db8] + +2014-08-01 Thomas Huth + + * CMakeLists.txt, cmake/FindSDL2.cmake, cmake/config-cmake.h, + configure, src/control.c: + Prepare the build-system for compiling with libSDL2 + [18af7e4c069a] + +2014-06-17 Thomas Huth + + * src/falcon/hostscreen.c, src/includes/screen.h, src/screen.c: + Consolidate the code around SDL_SetVideoMode in a separate function. + SDL_SetVideoMode will be gone with libSDL2. Let's merge the two code + paths that use SDL_SetVideoMode into a separate function, so that it + can be replaced easier at a later point in time. + [387b612f9ca7] + +2014-07-31 Eero Tamminen + + * src/gemdos.c: + fix: matching of 8 chars long filenames with a dot + + If GEMDOS was given 8 chars long file name with a dot and extension + shorter than 3 letters, which didn't exist, same file name with + longer extension would be matched. + + Instead, only requests for files with 8 chars long part before the + extension, should be matched using 'string*' pattern if there was no + exact match. This is to match cases where host name gets clipped to + 8+3 chars. + [45943c124bcc] + +2014-07-30 : *** Version 1.8.0 *** + +2014-07-30 Nicolas Pomarede + + * doc/compatibility.html, doc/doxygen/Doxyfile, doc/manual.html, doc + /release-notes.txt, hatari.spec, readme.txt, src/gui- + osx/English.lproj/InfoPlist.strings, src/gui- + osx/French.lproj/InfoPlist.strings, src/gui-osx/Info-Hatari.plist, + src/includes/version.h, src/memorySnapShot.c: + New release 1.8.0, increase version in corresponding files + [b825febc915f] [tip] + +2014-07-28 Nicolas Pomarede + + * src/gui-osx/PrefsController.m: + Fix path selection in OSX UI + [e2f26eddece2] + +2014-07-25 Nicolas Pomarede + + * readme.txt: + Add notes about compiling with capsimage library + [dd55accfa1ed] + +2014-07-22 Nicolas Pomarede + + * src/fdc.c: + Add more log when using 'write track' on ST/MSA files + [b12055468cdb] + + * src/fdc.c: + Correctly terminates 'restore' command if track 0 is not reached + after 255 attempts + [99f9c9c8cb69] + +2014-07-22 Thomas Huth + + * src/debug/debugui.c, src/debug/evaluate.c, src/file.c, src/gui- + sdl/dlgFileSelect.c, src/paths.c, src/zip.c: + More fixes for Xcode Analyze warnings (possible memory leaks, etc.). + Thanks to Miguel for the list. + [549fdc042774] + + * src/convert/low320x16_spec.c, src/convert/low320x32_spec.c, + src/convert/low640x16_spec.c, src/convert/low640x32_spec.c, + src/debug/68kDisass.c, src/debug/profiledsp.c, src/statusbar.c: + Fixed Xcode Analyze warnings about values stored to variables which + are never read. Thanks to Miguel for the list with warnings. + [c7014d062b64] + + * CMakeLists.txt, src/cpu/CMakeLists.txt, src/uae-cpu/CMakeLists.txt: + Revert changeset 7b110dcc02bf, set policy CMP0026 instead + [880a388cc05b] + +2014-07-16 Thomas Huth + + * tests/natfeats/Makefile, tests/natfeats/makefile: + Renamed Makefile so that it does not get clobbered by 'make + distclean' + [3d3e1faf1cd8] + + * src/floppy_stx.c: + Make sure that SaveSectorIndex gets initialized properly. This fixes + a problem with the Xenon II STX disk image. + [058dad3b7a71] + + * src/floppy_stx.c: + Switch off verbose debug messages by default + [2f8e4cae80ae] + +2014-07-15 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + fix: bug in DSP dsp_macr_p_x1_y0_b instruction + [62d0cd38c8fc] + +2014-07-13 Thomas Huth + + * src/cpu/CMakeLists.txt, src/uae-cpu/CMakeLists.txt: + Fix build warning with CMake 3.0 + [7b110dcc02bf] + +2014-07-12 Thomas Huth + + * doc/de/tastatur-windows.txt: + Added mapping file for German keyboard on Windows. Thanks to Max + Boehm for the listing. + [be70d7305be4] + +2014-07-07 Thomas Huth + + * src/gui-osx/English.lproj/InfoPlist.strings, src/gui- + osx/English.lproj/SDLMain.nib/keyedobjects.nib, src/gui- + osx/French.lproj/InfoPlist.strings, src/gui- + osx/French.lproj/SDLMain.nib/keyedobjects.nib: + Update the gui-osx binary files. Thanks to Jerome Vernet for the + files. + [3bb756a1ebbd] + +2014-07-06 Nicolas Pomarede + + * src/ikbd.c: + Ignore command 0x13 IKBD_Cmd_StopKeyboardTransfer during ikbd's + reset (fix for the loader of 'Just Bugging' by ACF ; need better + timings for the IKBD) + [cd7602644734] + + * src/fdc.c: + Fix FDC_ClearIRQ() when forced IRQ was set with command 0xD8 + [8e11ec8bd7b5] + +2014-07-04 Nicolas Pomarede + + * src/fdc.c, src/floppy_ipf.c, src/hdc.c, src/includes/fdc.h: + Store the source of the IRQ in FDC_SetIRQ() + don't set IRQ if + already set + [53fd36d70561] + +2014-07-06 Thomas Huth + + * doc/release-notes.txt, readme.txt: + Two small typo fixes. Thanks to Teemu Hukkanen for the patch. + [3b47db946648] + +2014-07-04 Eero Tamminen + + * doc/compatibility.html: + fix link + update descriptions + [383ae6a393e9] + +2014-07-03 Nicolas Pomarede + + * src/floppy_stx.c: + When saving a 'write track', free all the sectors previously saved + for that track + [6809539c776e] + +2014-07-02 Nicolas Pomarede + + * doc/release-notes.txt: + Add note about support for 'write track' to STX disk image + [18c0d28729c4] + + * src/fdc.c, src/floppy_stx.c, src/includes/floppy_stx.h: + Add support for 'write track' on STX disk image (using a .wd1772 + file) Result of 'write track' will be saved to an additional file + with the extension .wd1772 For now, data are not used for a 'read + track' but in many cases it already allows programs to format a + track without error before writing sectors (fix saving high scores + with 'write track' + 'write sectors' in the game 'Platoon') + [00ff406961f2] + +2014-07-01 Thomas Huth + + * doc/manual.html: + Mention the extended ACSI host adapter protocol in the feature list + [bab4db90974a] + +2014-06-29 Nicolas Pomarede + + * src/memorySnapShot.c: + In memory snapshot, Cycles_MemorySnapShot_Capture should be called + before FDC_MemorySnapShot_Capture FDC_IndexPulse_Init needs + CyclesGlobalClockCounter when the motor starts ; if + CyclesGlobalClockCounter was not correctly restored before, then + wait for index didn't complete and disk operation failed with RNF + [8f581755d7f4] + +2014-06-27 Eero Tamminen + + * python-ui/TODO, python-ui/dialogs.py, python-ui/gentypes.py, python- + ui/hatari.py, python-ui/release-notes.txt, python-ui/uihelpers.py: + add support for many new Hatari options + [59acd84c751e] + + * doc/hatari.1, doc/manual.html: + update gemdos case doc + [ad2cfb273b9d] + +2014-06-26 Thomas Huth + + * doc/manual.html: + Fixed error reported by HTML validator + [81b2f87098e5] + + * src/falcon/videl.c: + Always do the host color sync when writing to a color register (also + in monochrome mode). This fixes the "red monochrome" bug. + [8ade25e27c6b] + + * doc/manual.html: + Added comment about ACSI hard disk size constraints + [c77697bd9ffd] + + * .hgignore, src/gui-osx/AlertHooks.m, src/gui- + osx/CreateFloppyController.m, src/gui- + osx/English.lproj/SDLMain.nib/designable.nib, src/gui- + osx/French.lproj/SDLMain.nib/designable.nib, src/gui-osx/Info- + Hatari.plist, src/gui-osx/PrefsController.m, src/gui-osx/SDLMain.m, + src/gui-osx/Shared.h, src/gui-osx/Shared.m: + Some updates for the OS X GUI, mostly code cosmetics. Thanks to + Jerome Vernet for the patch. + [69ed960496b2] + +2014-06-25 Nicolas Pomarede + + * doc/release-notes.txt: + Add note about write support for STX files + [63e906f748b0] + +2014-06-25 Eero Tamminen + + * doc/release-notes.txt: + update release note + [c31b439be985] + + * doc/release-notes.txt, tools/atari-hd-image.1, tools/atari-hd- + image.sh: + raise atari-hd-image image size limit to 512MB + [e45c012ca214] + +2014-06-24 Nicolas Pomarede + + * doc/authors.txt: + Update contributors' list + [bd89502d86e3] + + * doc/compatibility.html, doc/todo.txt: + Update todo / compatibility list + [145ac9e842b8] + + * src/floppy_stx.c: + Warn that writes to an STX file will be saved into a .wd1772 file + [21071f9b661f] + + * src/floppy_stx.c, src/includes/floppy_stx.h: + Minor changes to the structures used to save STX sectors/tracks + [15df3dc586b6] + +2014-06-24 Eero Tamminen + + * src/gemdos.c: + update link + [058a0fbb82a6] + +2014-06-24 Nicolas Pomarede + + * cmake/FindCapsImage.cmake: + Revert change about IPF version used to compile + [f10e4fafbecc] + + * cmake/FindCapsImage.cmake, src/floppy.c: + When ejecting a disk, we don't need to check if it's write protected + to save changes If changes were made, it means WP was OFF earlier + when data were written to disk, so even if WP is ON at the time of + ejecting the disk, we must save changes anyway because writing was + enabled at the time of the writes + [8b99e7b54a5f] + + * src/createBlankImage.c, src/dim.c, src/floppy.c, src/floppy_ipf.c, + src/floppy_stx.c, src/includes/dim.h, src/includes/floppy_ipf.h, + src/includes/floppy_stx.h, src/includes/msa.h, src/includes/st.h, + src/includes/zip.h, src/msa.c, src/st.c, src/zip.c, + tools/hmsa/hmsa.c: + When using 'write sector' with STX images, save changes to an + external file Writes made to an STX image will be saved to a file + whose extension is .wd1772 instead of .stx ; when a .stx file is + loaded later, we look for a matching .wd1772 file to restore the + changes made to the .stx file For now, only 'write sector' commands + are saved, not 'write track' + [5c976e0be162] + + * src/file.c, src/includes/file.h: + Add the function File_ChangeFileExtension() + [7a121fdb20a1] + +2014-06-22 Nicolas Pomarede + + * doc/compatibility.html: + Add a note about the game "Platoon" + [cf92866b3e67] + +2014-06-20 Nicolas Pomarede + + * src/avi_record.c: + Fix type in comment + [053e20ddc3d5] + +2014-06-24 Eero Tamminen + + * doc/emutos.txt: + improve & update emutos documentation + [ba1a55d7d0ac] + + * doc/compatibility.html: + update hextracker & bad mood information + [687b4dc4f617] + +2014-06-18 Thomas Huth + + * src/gui-osx/SDLMain.m: + Disabled gFinderLaunch in OS X GUI + [335fed22fd2e] + +2014-06-18 Nicolas Pomarede + + * src/str.c: + Fix a remaining cast to unsigned char for ctype functions + [39cde6dcadad] + +2014-06-17 Thomas Huth + + * src/change.c, src/control.c, src/debug/68kDisass.c, + src/debug/breakcond.c, src/debug/debugInfo.c, src/debug/debugcpu.c, + src/debug/debugdsp.c, src/debug/debugui.c, src/debug/evaluate.c, + src/debug/log.c, src/debug/symbols.c, src/falcon/dsp.c, + src/gemdos.c, src/keymap.c, src/options.c, src/str.c, + tools/debugger/gst2ascii.c: + Typecast arguments of ctype functions to unsigned char. The ctype + functions need an unsigned char, or the behaviour is "undefined" + with certain compilers and C-libraries. Thanks to Vincent Rivière + for the hint. + [c9d60725e5d8] + +2014-06-17 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Add notes about "Lethal Xcess Beta" + [1b22ad17f046] + +2014-06-15 Nicolas Pomarede + + * doc/release-notes.txt: + Add some fixed demos/games + sort list + [6a12a4efff6f] + +2014-06-13 Nicolas Pomarede + + * doc/release-notes.txt: + Update release notes + [e4a4a0547e27] + + * src/video.c: + Add a temporary hack for 'Panic' by Paulo Simoes, don't trigger + 'left+2' on 1st line The timing used in this demo is similar to the + left+2 case on the 1st line that normally require a 2 cycle + precision. This hack is required because we only have 4 cycle + precision, but should be removed later + [5d6e584891dd] + +2014-06-13 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [f67ccfcfe8a3] + + * tools/debugger/gst2ascii.c: + generalize similarly to debugger symbols command + + It seems that whether offsets are from section start or from TEXT + section start is not just VBCC vlink issue, so try TEXT offset if + section offset fails regarless of compiler identification. + [5b3c643b3d8e] + + * src/debug/symbols.c: + support also text-relative data & bss symbol offsets + + AFAIK there's no indication of whether compiler/assembler uses + section or TEXT relative symbol offsets in its DRI compatible symbol + table. And which one should be used, doesn't seem to be documented + anywhere either. So, if offsets are invalid for section relative + ones, try whether loading them as TEXT relative would succeed. + [3c2362d06ab5] + +2014-06-12 Eero Tamminen + + * src/debug/symbols.c: + improve symbol loading error messages + + allow using "symbols prg" after symbols autoloading fails, so that + user gets the same errors instead of misleading error about HD + emulation. + [4b878cb43cd6] + +2014-06-12 Nicolas Pomarede + + * src/fdc.c, src/floppy_stx.c, src/includes/floppy_stx.h: + Add support for 'write sector' command with STX images For now, + modified sectors are only stored in RAM and in memory snapshot, they + will be lost when exiting Hatari + [c877476e1d39] + +2014-06-10 Thomas Huth + + * src/gui-sdl/dlgAlert.c: + Fix hooked alert dialog in Mac OS X fullscreen mode. Thanks to + Jerome Vernet for the patch. + [74abdf3146c1] + +2014-06-09 Nicolas Pomarede + + * src/fdc.c: + Improve ID field's timings for 'read sector' and 'write sector' + [d03be9edeef3] + + * src/fdc.c, src/includes/fdc.h: + Update the 'write sector' command to use the same logic as 'read + sector' + [62adc4f2d286] + +2014-06-08 Nicolas Pomarede + + * doc/manual.html: + Add more details about STX, IPF, RAW and CTR disk images + [b5572c218299] + + * src/fdc.c: + Update comment + [70c02017c87d] + + * src/floppy.c: + When restoring a memory snapshot, call FDC_InsertFloppy() in + Floppy_MemorySnapShot_Capture() Due to the order used when restoring + snapshot, some restored FDC variables were overwritten when + restoring the floppy.c part : FDC had no more inserted floppy, which + made disk accesses fail + [4b20d3f90ae8] + +2014-06-07 Thomas Huth + + * doc/manual.html: + Added comment about IPF support library in the manual. Thanks to + David Savinkoff for the hint. + [26a11e910add] + + * src/gui-osx/SDLMain.m: + Wire up the endCaptureAnimation action in the OS X GUI. Thanks to + Bob Carpenter for the patch. + [af3caef1a6d6] + +2014-06-07 Eero Tamminen + + * doc/manual.html: + improvements to disk related documentions + + - fix it's genetives -> its + - fix --harddisk -> --harddrive + - use consistent terminology: + - harddisk/drive -> hard disk/drive + - GEMDOS harddisk/drive -> GEMDOS HD + - *drive* emulation/activity, *disk* partition/image + - improve wording in floppy drive section + [fba1cbf20911] + +2014-06-07 Nicolas Pomarede + + * doc/manual.html: + Fix image's size in manual.html + [ba1da0b793c4] + + * doc/images/fileselector.png, doc/images/floppydisks.png, + doc/images/harddisks.png, doc/manual.html: + Update manual's screenshots for floppy and harddisk + [6c180aa3935f] + +2014-06-06 Nicolas Pomarede + + * doc/hatari.1, doc/manual.html, src/options.c: + Update manuals with new drive's options + [b1f7b7409b05] + + * src/dmaSnd.c: + If we get a bad command in microwire's data, check the remaining + bits for a valid command + [da8aa0fd76d1] + +2014-06-05 Nicolas Pomarede + + * doc/release-notes.txt: + Update release notes for LMC1992 decoding + [c6deb6f0c2f5] + + * src/dmaSnd.c: + Fix Microwire's decoding according to the LMC1992's datasheet + (Atari's doc is wrong) Decoding should start with the first "1" bit + received in the mask and ends when a "0" bit is received. Address + should always be "10" and should be followed by at least 9 command + bits (if more bits are received, only the last ones should be + checked). (fix "Pacemaker" by Paradox, mask/data 0xc1ff/0x8000 is + not a valid command and should be ignored instead of setting + mixer=0) + [81e4370ed4b5] + +2014-06-05 Thomas Huth + + * src/configuration.c: + Use SDL_keyboard.h instead of SDL_keysym.h since SDL_keysym.h will + be gone with SDL2. + [d0d7b3195235] + +2014-06-03 Thomas Huth + + * src/CMakeLists.txt: + Use XCode CONFIGURATION variable to determine location of the bundle + [c3cbcdcad5d3] + + * src/CMakeLists.txt: + Don't use wildcards for the docs + [0a115441f885] + +2014-06-02 Eero Tamminen + + * doc/release-notes.txt, src/includes/str.h: + use INVALID_CHAR that is better for autostarted programs + [03d5a4992d0b] + + * doc/release-notes.txt, tests/natfeats/natfeats.c, + tests/natfeats/natfeats.h, tests/natfeats/nf_vbcc.tos, + tests/natfeats/readme.txt: + add examples on all NF APIs + + - move/add documentation to test header + - add examples/tests for rest of NF APIs + - doc update + [c9a9a4ff68bf] + + * src/debug/natfeats.c: + NF_FASTFORWARD: show & return old value + [71e6892d6e3a] + + * doc/release-notes.txt, src/debug/debugui.c: + quit debugger command: no confirmation dialog, exit code argument + [0e3d00c8d979] + + * src/debug/debug_priv.h, src/debug/debugcpu.c, src/debug/debugdsp.c, + src/debug/debugui.c, src/debug/history.c, src/debug/symbols.c: + simplify debugger command help usage a bit + + after command help output, caller always exits with same return + value, so that value can as well be returned by the command help + function itself. + [5bc528584cbd] + +2014-06-02 Thomas Huth + + * src/CMakeLists.txt: + Set source file properties for OS X bundle doc files + [6c691dbc5852] + + * src/gui-osx/PrefsController.m: + Main_RequestQuit() now takes a parameter + [37c259194168] + + * src/paths.c: + Use a better place for the Hatari home directory on Mac OS X + [6a375a99f32d] + +2014-06-02 Laurent Sallafranque + + * src/cpu/falcon_cycle030.h: + fix: change 5007 removed 12 instructions that still were in the + falcon cycle table. All the instructions cycles were shifted in the + table. + [41bf6248411f] + +2014-06-01 Thomas Huth + + * src/gui-osx/PrefsController.m, src/gui-osx/Shared.h, src/gui- + osx/Shared.m: + More gui-osx updates from Jerome Vernet + [05798b674176] + +2014-06-01 Eero Tamminen + + * tests/tosboot/tos_tester.py: + improve TOS tester + + - fix: 192k EmuTOS needs 1s longer boot time + - adapt to hconsole Hatari command line option handling change + [2cc3c760ad48] + + * tests/tosboot/disk/ahcc-gemdos, tests/tosboot/disk/ahcc-minimal: + build needs longer wait + [78e4c964d79f] + + * doc/release-notes.txt, tools/hconsole/example-commands, + tools/hconsole/example.py, tools/hconsole/hconsole.py: + improve hconsole re-usability + + - hconsole.Main() constructor takes Hatari command line options as + argument, and another (optional) option for whether Hatari + disappearing will terminate the process + - run() method returns False if Hatari disappears (or given command + was missing/unrecogized) + [84f4434afd02] + + * tests/tosboot/disk/ahcc-gemdos, tests/tosboot/disk/ahcc-minimal: + improve comments + speed up + + - more info on how to use hconsole input script + - disabling statusbar can speed things slightly + [551a2adb7464] + + * tests/natfeats/Makefile, tests/natfeats/natfeats.h, + tests/natfeats/nf_ahcc.prj, tests/natfeats/nf_asma.s, + tests/natfeats/readme.txt: + add NF example for AHCC + [3c8b906b6cc8] + + * tests/natfeats/Makefile, tests/natfeats/Makefile.gcc, + tests/natfeats/Makefile.vbc, tests/natfeats/readme.txt: + add makefile for gcc & update NF readme + [bcf0831e931c] + + * tests/natfeats/nf_asm.s, tests/natfeats/nf_asmg.s: + rename & fix NF bindings GCC assembly file + + - fix: GCC 2.x Gas doesn't like C++ comments + - fix: exported symbol name + [9c754dfc888d] + + * tests/natfeats/natfeats.c: + fix test's compiler warnings + [b0592e0252a6] + + * tests/natfeats/natfeats.h: + add missing declaration + [24eacb253637] + + * doc/release-notes.txt, src/debug/log.c, src/debug/log.h, + src/debug/natfeats.c: + add support for natfeats tracing + [e3b7a3159288] + + * tests/natfeats/natfeats.c, tests/natfeats/nf_vbcc.tos: + improve nf usage in test + + (gives nicer natfeats trace output) + [8e2ff7fbe6c4] + + * doc/release-notes.txt, src/debug/natfeats.c: + improve natfeats comments + [0356144286b9] + + * doc/release-notes.txt, src/debug/natfeats.c, src/dialog.c, + src/includes/main.h, src/main.c, src/shortcut.c: + add Hatari support for NF_EXIT command + [d87347bbf89c] + + * tests/natfeats/natfeats.c, tests/natfeats/nf_asmv.s, + tests/natfeats/nf_vbcc.tos: + add example code / test for NF_EXIT + [4e0203287f42] + + * tests/natfeats/readme.txt: + more info on NatFeats example + [a00cbbaa55b2] + +2014-06-01 Thomas Huth + + * doc/compatibility.html, doc/manual.html: + Updates according to W3 validator and codespell + [666c95f2267b] + + * src/CMakeLists.txt, src/gui- + osx/English.lproj/AideHatari/compatibility.html, src/gui- + osx/English.lproj/AideHatari/images/callgraph.png, src/gui- + osx/English.lproj/AideHatari/images/callgraph.svg, src/gui- + osx/English.lproj/AideHatari/images/devices.png, src/gui- + osx/English.lproj/AideHatari/images/fileselector.png, src/gui- + osx/English.lproj/AideHatari/images/floppydisks.png, src/gui- + osx/English.lproj/AideHatari/images/harddisks.png, src/gui- + osx/English.lproj/AideHatari/images/joystick.png, src/gui- + osx/English.lproj/AideHatari/images/kcachegrind.png, src/gui- + osx/English.lproj/AideHatari/images/keyboard.png, src/gui- + osx/English.lproj/AideHatari/images/main.png, src/gui- + osx/English.lproj/AideHatari/images/memory.png, src/gui- + osx/English.lproj/AideHatari/images/monitor.png, src/gui- + osx/English.lproj/AideHatari/images/newfloppy.png, src/gui- + osx/English.lproj/AideHatari/images/screen.png, src/gui- + osx/English.lproj/AideHatari/images/sound.png, src/gui- + osx/English.lproj/AideHatari/images/system.png, src/gui- + osx/English.lproj/AideHatari/images/tos.png, src/gui- + osx/English.lproj/AideHatari/manual.html, src/gui- + osx/French.lproj/AideHatari/compatibility.html, src/gui- + osx/French.lproj/AideHatari/images/callgraph.png, src/gui- + osx/French.lproj/AideHatari/images/callgraph.svg, src/gui- + osx/French.lproj/AideHatari/images/devices.png, src/gui- + osx/French.lproj/AideHatari/images/fileselector.png, src/gui- + osx/French.lproj/AideHatari/images/floppydisks.png, src/gui- + osx/French.lproj/AideHatari/images/harddisks.png, src/gui- + osx/French.lproj/AideHatari/images/joystick.png, src/gui- + osx/French.lproj/AideHatari/images/kcachegrind.png, src/gui- + osx/French.lproj/AideHatari/images/keyboard.png, src/gui- + osx/French.lproj/AideHatari/images/main.png, src/gui- + osx/French.lproj/AideHatari/images/memory.png, src/gui- + osx/French.lproj/AideHatari/images/monitor.png, src/gui- + osx/French.lproj/AideHatari/images/newfloppy.png, src/gui- + osx/French.lproj/AideHatari/images/screen.png, src/gui- + osx/French.lproj/AideHatari/images/sound.png, src/gui- + osx/French.lproj/AideHatari/images/system.png, src/gui- + osx/French.lproj/AideHatari/images/tos.png, src/gui- + osx/French.lproj/AideHatari/manual.html, src/gui-osx/SDLMain.m: + Copy docs via build system into the OS X bundle + [dbce7135ea8a] + + * src/gui-osx/AlertHooks.m, src/gui-osx/CreateFloppyController.h, src + /gui-osx/CreateFloppyController.m, src/gui- + osx/English.lproj/AideHatari/.DS_Store, src/gui- + osx/English.lproj/Localizable.strings, src/gui- + osx/English.lproj/SDLMain.nib/designable.nib, src/gui- + osx/English.lproj/SDLMain.nib/keyedobjects.nib, src/gui- + osx/English.lproj/SDLMain.xib, src/gui- + osx/French.lproj/AideHatari/.DS_Store, src/gui- + osx/French.lproj/Localizable.strings, src/gui- + osx/French.lproj/SDLMain.nib/designable.nib, src/gui- + osx/French.lproj/SDLMain.nib/keyedobjects.nib, src/gui- + osx/French.lproj/SDLMain.xib, src/gui-osx/Info-Hatari Winuae.plist, + src/gui-osx/Info-Hatari.plist, src/gui-osx/PrefsController.h, src + /gui-osx/PrefsController.m, src/gui-osx/SDLMain.h, src/gui- + osx/SDLMain.m, src/gui-osx/Shared.h, src/gui-osx/Shared.m: + Updated the OS X GUI code to Jerome Vernet's latest version + [92bb776c7198] + + * cmake/DistClean.cmake: + Remove generated WinUAE CPU core files during distclean + [9ee0a367d940] + + * .hgignore: + Updated hgignore with WinUAE CPU core files + [8ef4c93531d7] + + * src/configuration.c: + Do not save the advanced ACSI configs, it's still experimental + [620d88f339e8] + + * src/keymap.c: + Simplified Keymap_DebounceAllKeys + [6c002ece6705] + +2014-05-31 Thomas Huth + + * src/includes/ikbd.h, src/includes/keymap.h, src/keymap.c, + src/memorySnapShot.c: + Track ST scancodes instead of host PC keycodes in KeyStates array. + The size of the KeyStates array depended on SDLK_LAST which could + differ between different SDL releases - and since the KeyStates + array was saved along with the memory snapshots, this meant that the + snapshots depended on the SDL version, too. Since SDLK_LAST will + also be gone with SDL 2.0, let's track the ST scancodes instead to + avoid these problems. + [bc80267dc16c] + + * cmake/FindReadline.cmake: + Fixed typo in new libreadline detection code + [f7dcf5df7170] + +2014-05-31 Eero Tamminen + + * doc/emutos.txt: + tt info update to emutos + [9ecb519c8c1b] + + * doc/release-notes.txt, src/debug/debugui.c, src/falcon/hostscreen.c, + src/falcon/hostscreen.h, src/falcon/videl.c, src/gui- + sdl/dlgScreen.c, src/includes/statusbar.h, src/main.c, src/screen.c, + src/statusbar.c, src/video.c: + do only 1 SDL_UpdateRect(s) call per screen update + + - change Statusbar_Update() to return SDL_Rect* for the area which + need an update, and change all screen update functions (ST & Videl + have separate ones) to add that rect to their own SDL_UpdateRects() + calls, so that there's only one call per normal screen update + + - change Statusbar_Update() to do SDL_UpdateRects() by itself only + if so requested by new do_update arg. That will be used when + statusbar update is done outside of normal screen updates. + + This should fix Hatari's OSX performance issue. + [bb571e6912ff] + + * src/blitter.c, src/debug/debugInfo.c, src/psg.c: + improve info/lock command output + + make the descriptions & output more consistent + + if it's obvious what the values are, header for them is redundant + and just wastes screen space (e.g. in YM case). + [db74a9c791ac] + + * doc/release-notes.txt, src/debug/debugInfo.c, src/includes/psg.h, + src/psg.c: + add "ym" subcommand to "info" for showing YM-2149 register values + + Based on slightly modified patch from Matthias Arndt. + [3dd80e99327d] + + * src/debug/debugInfo.c, src/falcon/crossbar.c, src/falcon/crossbar.h, + src/falcon/videl.c, src/falcon/videl.h, src/includes/video.h, + src/video.c: + move crossbar/videl/video functions from debuginfo to their own + files + [19d2e20e6b88] + +2014-05-31 Thomas Huth + + * CMakeLists.txt, cmake/FindReadline.cmake: + Check whether libreadline has to be linked along with libtermcap or + lib(n)curses + [9e7dd5ebf9a5] + + * cmake/FindTermcap.cmake: + Added cmake file for finding libtermcap + [8ccbd14b6286] + +2014-05-31 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt, src/video.c: + Ensure pVideoRaster always points into a 24 bit space region (fix + "Leavin' Teramis" which sets video address to $ffe100 to display + "loading please wait" ; in that case, we must display + $ffe100-$ffffff then $0-$5e00) + [8475b286c5d2] + +2014-05-30 Thomas Huth + + * src/joy.c: + Fix joystick axis mapping for recent Linux kernels The joystick axis + mapping is kernel dependant and thus not always necessary. Until a + rewrite of the joystick subsystem is done, this patch simply takes + out the currently defined auto remap. (Patch by Matthias Arndt) + [925683d7089c] + +2014-05-30 Nicolas Pomarede + + * src/fdc.c, src/floppy_ipf.c, src/includes/floppy_ipf.h: + For IPF, set a drive to single or double sided mode (need capslib >= + 5.1) + [25a0ff6a9ada] + + * src/fdc.c: + Fori type II commands 'read sector' and 'write sector', the ID field + should also have a correct CRC + [f7643bd42235] + + * src/mfp.c: + Increase MFP jitter for Lethal Xcess + [27af91f80131] + +2014-05-29 Eero Tamminen + + * doc/emutos.txt: + update emutos compatibility lists + + Add things that were fixed in Hatari, and ones that started working + with EmuTOS memory usage reductions. + + As EmuTOS works now with most ST programs, started adding also lists + of non-working ST color games. + + Update info for few other games. + [2b50561c3bac] + + * src/fdc.c, src/includes/fdc.h, src/statusbar.c: + optimize FDC updates + + FDC track information addition to statusbar changed statusbar + updates to happen on every screen update. This made Hatari on OSX + (at least with SDL 1.x) unbearably slow. Optimize by calling + SDL_UpdateRect(s) only once per statusbar update. + + Additionally, avoid potential future memory overwrites by changing + FDC statusbar string function to use C99 snprintf instead of + sprintf. + [2f1717590c94] + + * doc/release-notes.txt: + re-organize release notes a bit + + + add note about PC being added to OS call traces + [5b2a9b316919] + + * tools/hmsa/hmsa.c: + make sure both GUI wrappers output newline + [6f9890d0d0cd] + + * src/debug/evaluate.c: + correct comment + [4fbd89d20463] + +2014-05-29 Thomas Huth + + * src/cpu/cpummu030.c, src/cpu/gencpu.c, src/cpu/newcpu.c, src/mfp.c, + src/video.c: + Fixed more typos (discovered with codespell) + [32ca06d7aa77] + +2014-05-29 Nicolas Pomarede + + * src/cycInt.c: + In CycInt_ModifyInterrupt, remove assert on CycleTime + [153ae18226da] + + * src/debug/evaluate.c: + Typos + [2ecaf8e10259] + + * doc/release-notes.txt: + Update release notes + [73e7ac6af699] + + * doc/compatibility.html: + Update games' compatibility list with some specific settings + [2644645a86a4] + +2014-05-28 Nicolas Pomarede + + * src/fdc.c, src/floppy_stx.c, src/includes/floppy_stx.h: + Add FDC_NextSectorID_CRC_OK_ST / FDC_NextSectorID_CRC_OK_STX + [78e8098e9712] + + * src/fdc.c: + For 'write sector' check that track and sector registers match the + current ID field + [2d5e2c8fe28c] + + * src/fdc.c: + Add comments for statusbar's messages + [65d27e19437b] + + * src/mfp.c: + Add a small jitter in the MFP's timers (Temporary fix for Lethal + Xcess calibration routine to remove top border) + [30883e3337e0] + +2014-05-27 Nicolas Pomarede + + * src/cycInt.c: + Fix compiler warning in 64 bit mode : remove unnecessary casts + [0c7ff28c0d6a] + +2014-05-28 Thomas Huth + + * src/debug/evaluate.c: + Fixed format string - value is long long, so use llx + [de81bc9b67e5] + + * src/cycInt.c: + Silenced compiler warnings of clang. Now that the code uses the + PRId64 format macro, it is not necessary to typecast the arguments + to (long long) anymore. + [3a0ed1bae556] + +2014-05-27 Nicolas Pomarede + + * src/gui-sdl/dlgAbout.c: + Fix compiler warning : comparison between signed and unsigned int + [93567b8e8dce] + + * src/msa.c: + Use our internal 'Uint16' type instead of 'short int' + [a2ff2ee272c6] + + * src/msa.c: + Remove warning in 64 bit mode : cast from pointer to integer of + different size + [9c563164cc28] + +2014-05-27 Thomas Huth + + * src/floppy_ipf.c: + Fixed build w/o capslibrary + [d1e046fa38b9] + +2014-05-27 Nicolas Pomarede + + * cmake/FindCapsImage.cmake: + Default to capslib v4 (until v5 is released) + [c06e112d7bff] + + * src/uae-cpu/newcpu.c: + Disable DEBUG_PREFETCH by default + [ebfcac89a977] + +2014-05-26 Nicolas Pomarede + + * cmake/Toolchain-mingw32-win64_32.cmake, cmake/Toolchain- + mingw32-win64_64.cmake, cmake/Toolchain-mingw32.cmake, configure: + Remove old --cross-compile-win32 and add toolchain files for Windows + 32 and 64 bit We use 2 different toolchain files, because passing + parameters with -D is causing problem in cmake when handling a + toolchain file + [9e5e60b02f0e] + +2014-05-23 Nicolas Pomarede + + * src/cycInt.c: + Fix compiler warning : return a pointer to a void function, instead + of a void pointer + [453202cd4a59] + + * src/uae-cpu/newcpu.c: + Fix pointer's type + [ecaab2ec026e] + + * src/debug/68kDisass.c, src/debug/history.h: + Fix compiler warning : remove last ',' in enum + [4841e2f6cb26] + + * src/debug/68kDisass.c: + Fix compiler warning : don't use return in a 'void' function + [64443d5ca57e] + +2014-05-21 Nicolas Pomarede + + * src/fdc.c, src/floppy_ipf.c, src/includes/floppy_ipf.h: + Print some FDC's informations in the statusbar also when using IPF + mode + [2f8c3bc50b6f] + + * src/statusbar.c: + Move frameskip's info on the right of the statusbar + [1eb6ca2170ec] + + * src/fdc.c, src/includes/fdc.h, src/statusbar.c: + Print some FDC's informations in the statusbar (command, head, + track, sector, side) + [a626c2bb2586] + + * cmake/Toolchain-mingw32.cmake: + Add debug message + [bab8c2820516] + + * src/shortcut.c: + Fix autoinsert in drive B when using shortcut alt+d Filename was + changed for drive B, but Floppy_InsertDiskIntoDrive(1) was not + called + [00565af93d1a] + +2014-05-19 Nicolas Pomarede + + * src/floppy_ipf.c: + For IPF, correctly set drives ON or OFF in IPF_Init() when restoring + a memory snapshot + [2029ecf51aed] + + * src/fdc.c, src/floppy_ipf.c, src/includes/floppy_ipf.h: + For IPF, allow to turn drive B ON or OFF to have only drive A + enabled With current capslib, it's not possible to turn drive A OFF + [88f78670ecfe] + + * src/bios.c, src/gemdos.c, src/xbios.c: + Print PC in all gemdos/bios/xbios traces + [db7d5f0149a4] + +2014-05-18 Nicolas Pomarede + + * src/floppy_ipf.c: + When inserting IPF/CTR images, invalidate track/side used for + CAPSSetRevolution() + [fa0766d3d0bf] + + * src/stMemory.c, src/tos.c: + Don't force drive A and B at $4c2, keep the values detected by TOS + FDC emulation will correctly detect if a drive is ON or OFF, so + there's no need anymore to force $4c2, we keep the values at $4a6.w + and $4c2.l, we only update $4c2.l with the harddrives. + [04404dc1fbc0] + +2014-05-12 Nicolas Pomarede + + * src/floppy_ipf.c, src/uae-cpu/newcpu.c: + Update includes for capslib v5 + [6874cd63e9e0] + +2014-05-11 Nicolas Pomarede + + * src/floppy_stx.c: + Remove warning on 64bit architecture + [8134e4391ed5] + +2014-05-10 Nicolas Pomarede + + * src/fdc.c, src/floppy_ipf.c, src/includes/fdc.h: + For CTR images, we must call CAPSSetRevolution() when track/side + changed before accessing data For example, this is required for CTR + version of "Turrican" + [486c241f111a] + +2014-05-08 Nicolas Pomarede + + * cmake/FindCapsImage.cmake: + Correct search path for capsimg.dll.a for mingw + [565388d903a1] + + * src/video.c: + When 50Hz and 60Hz lines are mixed, we must update the position of + the next VBL's interrupt (fix "ikbd no jitter" test program by Nyh + in atari-forum.com, using a 160240 cycles VBL) + [e9be9924618a] + + * src/cycInt.c, src/includes/cycInt.h: + Add CycInt_ModifyInterrupt to modify the counter without restarting + the interrupt + [7d52fee555fc] + +2014-05-07 Nicolas Pomarede + + * CMakeLists.txt: + Print the version of caps library in ./configure + [d167086412d5] + + * src/m68000.c: + In M68000_WaitEClock, use CyclesGlobalClockCounter instead of + CYCLES_COUNTER_VIDEO + [c671abf267d5] + +2014-05-01 Nicolas Pomarede + + * src/fdc.c: + Fix wait states when accessing $ff8604/$ff8606 (verified on real + STF) + [8bd6daf483cf] + +2014-04-29 Nicolas Pomarede + + * src/main.c: + Add missing include for WIN32 + [acff11858e34] + + * src/includes/main.h: + Don't redefine ARRAYSIZE if already defined (for mingw) + [33ecc9c49c0b] + +2014-04-28 Nicolas Pomarede + + * src/cycInt.c, src/debug/evaluate.c: + Replace %lld by C99 macros + [c3cd4a021ef3] + + * src/fdc.c: + FDC params for drive 1 were not correctly saved + [671444681612] + +2014-04-27 Nicolas Pomarede + + * src/fdc.c: + Force Int command should set the motor bit and clear spinup bit only + when FDC is idle + [3ae90c9a441c] + +2014-04-25 Nicolas Pomarede + + * src/fdc.c: + When reading FDC status register for a type I command, always unset + bit 3 (fix "Macadam Bumper", "Crafton & Xunk", "L'Ange de Cristal") + [eeadd203345b] + +2014-04-23 Nicolas Pomarede + + * CMakeLists.txt: + Update comment for caps library + [c26a54c40ba3] + + * cmake/FindCapsImage.cmake, src/floppy_ipf.c, src/uae-cpu/newcpu.c: + Allow compilation with caps library v4 or v5 + [660791f07e4c] + +2014-04-22 Nicolas Pomarede + + * cmake/FindCapsImage.cmake, cmake/config-cmake.h, src/uae- + cpu/newcpu.c: + Define CAPSIMAGE_VERSION in FindCapsImage.cmake + [fdf94bbd88ee] + + * src/floppy_ipf.c, src/includes/floppy_ipf.h, src/main.c: + Don't call capslib functions directly in main.c + [5302a199b98f] + +2014-04-21 Nicolas Pomarede + + * src/floppy_ipf.c, src/uae-cpu/newcpu.c: + Update includes to work with capslib 4 and 5 + [3efa2eb52910] + +2014-04-19 Nicolas Pomarede + + * src/fdc.c: + In FDC, starting a Force Int command should set the motor bit (fix + the games "Saint Dragon" and "Knightmare") + [5c3e6bdb1f90] + + * src/fdc.c, src/floppy.c, src/floppy_stx.c, src/includes/floppy.h, + src/includes/floppy_stx.h: + In Floppy_ReadSectors, return a pointer to the data instead of doing + a memcpy + [6e4bee7173b8] + +2014-04-17 Nicolas Pomarede + + * src/options.c: + Add options --drive-a-heads and --drive-b-heads to select + single/double sided drive + [89183bd3658c] + + * src/change.c, src/configuration.c, src/fdc.c, src/gui- + sdl/dlgFloppy.c, src/includes/configuration.h, src/includes/fdc.h: + For floppy drives, handle "Double Sided" option in the UI + config + file + [cb1ebd4444c6] + + * src/change.c, src/configuration.c, src/fdc.c, src/floppy_ipf.c, + src/includes/fdc.h: + Rename some FDC functions + [1b2cc4fcdf34] + +2014-04-16 Nicolas Pomarede + + * src/fdc.c, src/floppy_stx.c, src/includes/floppy_stx.h: + Add support for single sided or double sided floppy drive Some + games/demos could have a different behaviour depending on the + drive's settings (F29 Retaliator, Captive, Union Demo, ...) + [60371e2bd037] + +2014-04-11 Nicolas Pomarede + + * src/uae-cpu/gencpu.c: + Improve prefetch order for "move.l Dn,(An)" (fix the game + "International 3D Tennis" protection : move.l d0,(a0)) + [e739810dec77] + +2014-04-09 Nicolas Pomarede + + * src/uae-cpu/gencpu.c: + Fix i_Scc to do a read before the write in 68000 mode (similar to + i_CLR) (fix Chart Attack compilation by Gremlin) + [49ecdaf93b59] + +2014-04-07 Nicolas Pomarede + + * src/floppy_ipf.c: + For IPF, set the write protect state depending on the UI + [7c2dd342f3f0] + +2014-04-06 Nicolas Pomarede + + * src/uae-cpu/newcpu.c: + Add (disabled) code to trigger breakpoint in capsimg library for + debug + [8bc526312eb2] + + * src/uae-cpu/newcpu.c: + In Exception(), add a special case for last_addr_for_exception_3 + (fix the game Batman The Movie) + [b55a6581a4fc] + +2014-04-05 Nicolas Pomarede + + * src/fdc.c: + In FDC_GetEmulationMode(), default to the latest mode when no drive + are selected (fix "Saint Dragon" in IPF, sending D0 command when no + drive are selected) + [05567c2b657b] + +2014-03-28 Nicolas Pomarede + + * src/fdc.c: + For FDC_NextSectorID_TR_ST() value should be the latest HeadTrack + [3fb081402359] + +2014-03-25 Nicolas Pomarede + + * src/floppy_ipf.c: + Use CAPSGetImageTypeMemory() to check if the disk image is IPF, + CTRAW, ... + [7a370e33d50c] + + * cmake/FindCapsImage.cmake, cmake/Toolchain-mingw32.cmake: + When compiling the Windows version, use capsimg.dll instead of + capsimage.dll + [8c0d9ed08ca2] + + * src/uae-cpu/newcpu.h: + In refill_prefetch(), read 2 words instead of 1 long, for better bus + error detection When reading only one long, the bus error is not + detected if the address overlaps a valid region and a bus error + region. (fix "Union Demo" and "To Be On Top" protections) + [f82b1c8269a7] + +2014-03-22 Nicolas Pomarede + + * src/floppy.c, src/floppy_ipf.c, src/zip.c: + Associate .ctr extension to capsimage library for CT RAW dump + [3667c1b168e8] + +2014-03-20 Nicolas Pomarede + + * src/floppy.c, src/floppy_ipf.c, src/includes/floppy.h, src/zip.c: + Also handle .raw files with capsimage library (CT RAW dump or + Kryoflux RAw dump) + [16b930cd89b3] + + * configure: + Clear cmake's cache when running ./configure + [06895af2bc4b] + + * cmake/Toolchain-mingw32.cmake: + For Windows cross compilation, use newer i686-w64-mingw32-gcc + instead of i586-pc-mingw32-gcc + [fc4142341770] + +2014-03-19 Nicolas Pomarede + + * src/uae-cpu/newcpu.c: + During Bus Error when reading $ff8e21, add a specific case to + restore the correct value of the dest part (fix Tymewarp by YM + Rockerz) + [12a7c1faf651] + + * src/cpu/table68k, src/uae-cpu/table68k: + bset.b d0,8(pc) is not a valid 680xx instruction, but an illegal one + (fix the game Dragon Flight) + [7a4948830aee] + + * src/uae-cpu/newcpu.c: + Temporarily enable report of self modified code combined with + prefetch + [2c1ad490970e] + + * src/uae-cpu/newcpu.c: + During Bus Error, add a specific case to restore the correct value + of the dest part (fix the game Dragon Flight) + [e972ceaa0786] + + * src/zip.c: + Update error message + [9828918c7b64] + +2014-03-15 Nicolas Pomarede + + * src/floppy_stx.c, src/includes/floppy_stx.h: + Text formatting + [8da553e4ceaf] + + * src/ikbd.c, src/includes/ikbd.h: + Add support for the IKBD commands 0x11 and 0x13 (resume/pause + output) (fix protection in the game "Warp") + [5425c070b763] + + * src/ikbd.c, src/includes/ikbd.h: + Add support for the IKBD command 0x17 (joystick monitoring) (fix + protection in the game "Warp" (sectors decoding)) + [89dd316a9ef1] + +2014-03-11 Nicolas Pomarede + + * src/fdc.c: + For Read Sector, update next state after motor on + [95ef0003f247] + + * src/fdc.c: + If Read Address doesn't find any ID after 5 index pulses, return RNF + [17c76ef317ec] + +2014-03-08 Nicolas Pomarede + + * src/fdc.c, src/floppy_stx.c, src/includes/floppy_stx.h: + For STX image, the number of cycles per revolution is variable and + depends on drive/track/side + [21973cdd8f4c] + + * src/fdc.c: + Reset IndexPulse_Time when FDC motor stops, to get a new one when + motor starts again + [aaca67502d5e] + +2014-03-07 Nicolas Pomarede + + * src/uae-cpu/gencpu.c: + Improve prefetch order for "move" (only prefetch 1 word instead of + 2) (fix protections for "Union Demo", "Titan", "Xenon 2", "Darkman", + "Parasol Stars") + [58e6b63cf9ad] + + * src/uae-cpu/gencpu.c: + Improve prefetch order for "eor.x Dn,xxx.L" (fix "Xenon 2" + protection : eor.w d0,$40760) + [177ca1e2fcb7] + +2014-03-06 Nicolas Pomarede + + * src/fdc.c: + Fix copy/paste error in FDC_NextSectorID_TR_ST + [d3dbd0a69282] + +2014-03-05 Nicolas Pomarede + + * src/floppy_stx.c: + For STX, build a standard track if we do a Read Track on a non- + imaged track The track is made of the available sectors and some + standard GAP values + [5c790bfe4afc] + + * src/fdc.c, src/includes/fdc.h: + Add FDC_Buffer_Get_Size () + [97ca5c4c0ee8] + +2014-03-04 Nicolas Pomarede + + * src/floppy_ipf.c: + For IPF, invalidate previous track when ejecting/inserting a new + floppy (fix floppy's change detection in some cases after + eject/insert) + [ecb1a36cad81] + +2014-02-26 Nicolas Pomarede + + * src/floppy_ipf.c: + Remove log in IPF_Emulate() + [ba19661fee92] + + * src/fdc.c, src/floppy_stx.c, src/includes/fdc.h, + src/includes/floppy_stx.h: + Put some common constants in fdc.h + [132deabd45a4] + + * src/floppy_stx.c, src/includes/floppy_stx.h: + Build some default values for STX track with only sector data and no + sector info + [def1afe4ee56] + +2014-02-25 Nicolas Pomarede + + * src/uae-cpu/gencpu.c: + Improve prefetch order for "move.l #$xxxx,(An)" (fix the game + "Titan" protection : move.l #$b0b0caca,(a4)) + [0894acf129cb] + +2014-02-23 Nicolas Pomarede + + * src/acia.c: + Add debug printf + [f481195d4974] + +2014-02-22 Nicolas Pomarede + + * src/cycles.c: + In Cycles_GetInternalCycleOnReadAccess, don't read the opcode if PC + is in the IO region This can create recursive calls of + Video_Color0_ReadWord and a crash for the rare cases where code is + run from the $ff8240-$ff8260 region (eg "Union Demo" protection) + [e3c46824a512] + + * src/video.c: + When reading color regs, set unused STF bits to rand() only if PC is + in RAM (fix "Union Demo" protection code running at address $ff8240) + [96d81e777962] + + * src/uae-cpu/gencpu.c: + Improve prefetch order for "move.x Dn,xxx.L" (fix "Union Demo" + protection : move.w d1,$4c) + [69ecb2613426] + + * src/uae-cpu/newcpu.c, src/uae-cpu/newcpu.h: + In refill_prefetch(), check for bus error when reading next + word/long to prefetch (fix "Union Demo" protection) + [89bbaf2a1c56] + + * src/uae-cpu/newcpu.c: + In Exception(), call valid_address() before reading the opcode at + BusErrorPC Doing get_word(BusErrorPC) directly could cause an + unwanted double bus error if PC was in bus error region + [7137389461e8] + +2014-02-20 Nicolas Pomarede + + * src/fdc.c: + When a new FDC command starts, we should stop generating IRQ on each + IP (fix ReadTrack after a $D4 command in "Damocles", "Driving + Force", "Lethal Xcess") + [77d3694a8b48] + +2014-02-17 Nicolas Pomarede + + * src/fdc.c: + Add log for ReadSector with multi=on + [7c33338d131b] + +2014-02-15 Nicolas Pomarede + + * src/fdc.c, src/floppy_stx.c, src/includes/floppy_stx.h: + For ReadSector, check that FDC.TR matches the track number in the ID + Field + [3cb68fa541dc] + + * src/floppy_stx.c, src/includes/floppy_stx.h: + Complete STX emulation of ReadSector, ReadAddress and ReadTrack : + some games are working Successfully tested games : Arkanoid, Bomb + Jack, Gauntlet II, Rampage, Turrican + [d7293faed987] + + * src/fdc.c: + Call FDC_NextSectorID_SR_STX when the floppy is an STX image + [02238d20fc65] + +2014-02-08 Nicolas Pomarede + + * src/fdc.c: + Call FDC_NextSectorID_FdcCycles_STX when the floppy is an STX image + [26727e721a2e] + +2014-02-07 Nicolas Pomarede + + * src/fdc.c, src/includes/fdc.h: + Fix return value in FDC_NextIndexPulse_FdcCycles + declare some + functions as extern + [81bd7d9d34cb] + +2014-02-06 Nicolas Pomarede + + * src/fdc.c: + FDC_NextSectorID_FdcCycles_ST must return an int, not an Uint32 + [1189873bfd79] + + * src/fdc.c: + Call STX functions for ReadSector, ReadAddress and ReadTrack + [4466bf1bb269] + +2014-01-30 Nicolas Pomarede + + * src/fdc.c: + Check CRC error after reading a sector (for STX) + [ff68321ffd70] + + * src/fdc.c: + Return an error code in FDC_ReadAddress_ST and FDC_ReadTrack_ST, + instead of a bool + [473eda19bf2f] + +2014-01-28 Nicolas Pomarede + + * src/fdc.c: + Return an error code in FDC_ReadSector_ST, instead of a bool + [4bade8cca27e] + + * src/fdc.c, src/includes/fdc.h: + Use Uint16 for FDC_Buffer's Timing + [326c568f903d] + +2014-01-26 Nicolas Pomarede + + * src/fdc.c: + Replace FDC_TransferByte_FdcCycles with FDC_TransferByte_FdcCycles + [6af685392352] + +2014-01-24 Nicolas Pomarede + + * src/floppy_stx.c, src/includes/floppy_stx.h: + Correctly handle STX track with only a track image and O sector + [855140cabc80] + +2014-01-23 Nicolas Pomarede + + * src/fdc.c: + Remove old code for ReadTrack + [622322985b1e] + + * src/fdc.c: + Remove unnecessary variable in FDC_BUFFER + [c5eb340c5f52] + + * src/fdc.c: + Rewrite ReadTrack to use FDC_ReadTrack_ST() and FDC_BUFFER + [e221563412e9] + + * src/fdc.c: + Rewrite ReadAddress to use FDC_ReadAddress_ST() and FDC_BUFFER + [9eb6109a7101] + + * src/fdc.c: + Removed unused FDC_ReadSectorFromFloppy() + [067d73ae9da7] + + * src/fdc.c: + Separate CRC and multi bit states for ReadSector/WriteSector + [44e3e8b05b1a] + + * src/fdc.c, src/includes/fdc.h: + Add FDC_BUFFER to associate a specific timing to each FDC byte to + transfer ; use it for type II ReadSector + [475833f68b17] + +2014-01-20 Nicolas Pomarede + + * tools/hmsa/hmsa.c: + Add an empty STX_FileNameIsSTX function to be able to build without + linking all floppy related files + [f6d64a8059f2] + + * src/floppy_stx.c: + Add a debug flag to print the hexdump of the sector/fuzzy/timing + data of STX files + [bf45684d69ea] + + * src/includes/str.h, src/str.c: + Add Str_Dump_Hex_Ascii() + [189a42078727] + +2014-01-15 Nicolas Pomarede + + * src/floppy_stx.c, src/includes/floppy_stx.h: + For STX with revision=0, add default timings table + [7bd44f62dd5d] + +2014-01-14 Nicolas Pomarede + + * src/floppy_stx.c, src/includes/floppy_stx.h: + In STX, parse the optional timings block for variable bitrate + sectors + [e7b82fba5832] + +2014-01-12 Nicolas Pomarede + + * src/fdc.c: + Add define FDC_SECTOR_SIZE_MASK + [afa8c0c665cd] + + * src/floppy_stx.c, src/includes/floppy_stx.h: + Parse the STX file, alloc buffers and init internal variables + [805c07f60c83] + +2014-01-03 Nicolas Pomarede + + * src/CMakeLists.txt, src/fdc.c, src/floppy.c, src/floppy_stx.c, + src/includes/floppy.h, src/includes/floppy_stx.h, + src/memorySnapShot.c, src/zip.c: + Add default file operations to handle .STX disk images + [386880c9cf66] + +2014-05-24 Thomas Huth + + * src/gui-sdl/dlgAbout.c: + Shorten program name in about dialog if necessary + [d12be261e0c9] + +2014-05-20 Eero Tamminen + + * doc/compatibility.html: + add missing STE programs + + There are so few of them that they can be all listed in the + compatibility list. + [555afec40f4e] + +2014-05-19 Eero Tamminen + + * doc/compatibility.html: + better link to zip + + (link on HTML page didn't work) + [c05d9c90b1d3] + + * doc/compatibility.html: + fix/add STE links + + some of the linked sites have disappeared, link to Atarimania + instead. Add some links. + [d77806a6f147] + +2014-05-11 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Add note about disabling real time clock by default + [71835e317152] + + * src/configuration.c: + Don't enable MegaST's real time clock by default (at + $fffc20-$fffc40) This can make some STF/STE programs fail as it will + change some TOS variables (fix "Stax Compilation #65") + [899afbd08e40] + +2014-05-09 Eero Tamminen + + * doc/manual.html, src/debug/profile.c: + fixes to profile command help text + [48d5edfcc567] + +2014-05-08 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [068e8856917c] + + * tools/debugger/gst2ascii.1, tools/debugger/gst2ascii.c: + gst2ascii: handle symbols both from fixed & buggy VBCC/vlink + + Improve also advice on what to do when symbol loading fails or when + it succeeds. + [43e30e0a6223] + + * src/debug/symbols.c: + remove VBCC specific code, bail out if too many offset issues + + It seems that VBCC vlink was buggy and Frank will fix that, so + removed VBCC checks. + + In case there's still binaries with old buggy symbol table offset, + bail out after whole screen is spammed with them. + [2261eb4503e9] + + * doc/manual.html: + profiler documentation typo fixes & improvements + [958d51ab1723] + + * doc/hatari.1, doc/manual.html: + docs command and option categorization update + [27a5a365843f] + +2014-05-08 Nicolas Pomarede + + * src/configuration.c: + Set default value of nSpec512Threshold to "1" instead of "16" + [a7bdb4fcbe4d] + +2014-05-07 Eero Tamminen + + * doc/emutos.txt: + more emutos updates + [82a5e822211b] + +2014-05-06 Laurent Sallafranque + + * src/falcon/crossbar.c: + Fix my previous crossbar patch: I forgot to remove the old zeroing + [7de791745520] + + * src/falcon/crossbar.c: + Little sound fix: zero the dac values only when the step is not 0 + [83a097320c9f] + +2014-05-05 Laurent Sallafranque + + * CMakeLists.txt: + old cpu by default. + [edd1717f8566] + + * CMakeLists.txt, src/falcon/videl.c, src/falcon/videl.h, + src/ioMemTabFalcon.c: + Videl fix: the ST palette is now correctly masked. + [de67aba99091] + +2014-05-05 Eero Tamminen + + * doc/emutos.txt: + added new games working with EmuTOS 2014-05-03 + + Latest EmuTOS CVS snapshot fixed IKBD initilization (not to disable + joy & mouse), this fixed several games. Some other games were also + found to be working with latest version (maybe because it uses less + memory and some line-A bugs were fixed). + [10418f44834c] + +2014-05-04 Eero Tamminen + + * src/gemdos.c: + TOS filename 8+3 clipping must be done at first '.' + + While host filename matching is better done at last '.' so that file + types are preserved for too long host filenames, TOS filenames + coming through GEMDOS calls, *must* be clipped at first '.'. + + Fixes MAZE game. + [e7c95390131f] + + * src/cpu/memory.c, src/uae-cpu/memory.c: + include correct header (instead of using extra extern) + [81b5df99e008] + +2014-05-03 Thomas Huth + + * src/cpu/falcon_cycle030.h, src/cpu/memory.c, src/hdc.c: + Fixed some more possible compiler warnings from GCC and Clang + [cbbda4eec686] + +2014-05-04 Eero Tamminen + + * doc/manual.html: + improvements to debugger section + [77fa694beed1] + +2014-05-03 Thomas Huth + + * src/debug/symbols.c, tools/debugger/gst2ascii.c: + Fixed compiler warning about ignored return value of fread + [4127b89981f7] + +2014-05-03 Eero Tamminen + + * src/debug/breakcond.c: + fix build with DSP disabled + [32664b5d98fe] + +2014-05-02 Eero Tamminen + + * src/debug/debugui.c: + fix valgrind warning + [2f6293e82533] + +2014-05-02 Nicolas Pomarede + + * src/includes/version.h: + For devel version, add build date into version string + [19a4fe9e1f2c] + +2014-05-02 Eero Tamminen + + * src/includes/version.h: + add CPU core type to devel version string + + and don't use release version string in development version... + [1c4f565a7ba6] + + * src/joy.c, src/statusbar.c: + add monitor, joystick and WinUAE specific info to statusbar + + Now that information is on separate line from indicators, there's + space to add a bit more info statusbar messages. + [482280d45147] + + * src/statusbar.c: + split statusbar information to 2 lines + [3b2da96211d0] + + * src/main.c: + decrease startup help message timeout 6s -> 5s + [b4db2b5e17d8] + + * doc/manual.html: + section on debugger invocation + debugger documentation improvements + [fd82387b7f3e] + + * doc/manual.html, doc/release-notes.txt, src/debug/debugui.c, + src/debug/symbols.c, src/debug/symbols.h, src/gemdos.c, + src/includes/gemdos.h: + load debug symbols for current program when entering debugger + + - move last program (path) handling from gemdos.c to symbols.c (and + do Last->Current rename) + - move Atari program identification to its own function there + - on entering debugger, load debug symbols for currently running + program, if there's such thing and no CPU symbols are yet loaded + - remove CPU symbols for a program when it terminates + - update documentation + [34e26ac54dbf] + +2014-05-01 Eero Tamminen + + * doc/manual.html, src/debug/log.c, src/debug/log.h, src/tos.c: + "autostart" flag for --debug-except option + [2e04bebb1160] + + * src/xbios.c: + clearer function return handling + [8cad687cc185] + + * doc/hatari.1, doc/manual.html, doc/release-notes.txt, src/bios.c, + src/cpu/newcpu.c, src/debug/log.c, src/includes/options.h, + src/includes/xbios.h, src/options.c, src/uae-cpu/newcpu.c, + src/xbios.c: + remove need for --bios-intercept on Bios/XBios tracing + + Reason for bBiosIntercept variable usage in CPU core code was that + in addition to tracing, it and --bios-intercept option were (still) + used to enabled other XBios command interceptions, of which + Xbios(255) has also some security implications. + + This commit fixes that by: + + * removing bBiosIntercept variable. CPU cores call now bios.c and + xbios.c code unconditionally on relevant traps + + * xbios.c now deciding itself whether XBios(255) etc are enabled + - move --bios-intercept toggling code from options.c to xbios.c (to + new XBios_ToggleCommands() function) and change it to affect only + enabling of special XBios() features + - bios.c doesn't do anything besides tracing so it didn't need any + functionality changes + + Documentation is also updated. + [14ac4fe7418e] + + * doc/hatari.1, doc/manual.html, doc/release-notes.txt, + src/includes/main.h, src/main.c, src/options.c: + add --slowdown option + [a7895426300e] + +2014-04-30 Nicolas Pomarede + + * doc/release-notes.txt, src/debug/natfeats.c: + Add NatFeats command NF_FASTFORWARD + [81f661051d00] + + * doc/release-notes.txt: + Update release notes + [68711efbea2b] + + * src/dmaSnd.c: + Remove whitespaces + [1567bcf1ab11] + +2014-04-30 Nicolas Pomarede + + * src/dmaSnd.c: + Correct STE sound mixing using LMC1192 when mixer=0 Atari's docs are + wrong, mixer=0 will not mix DMA with YM2149-12dB, it will only + output DMA sound. Only mixer=1 allows to hear YM2149 sound. + [c5661fed2d4f] + +2014-04-30 Eero Tamminen + + * src/debug/symbols.c, tools/debugger/gst2ascii.c: + special-case VBCC symbols + + it seems that VBCC may be an exception in giving offsets for all + symbol types relative to TEXT section, so code now checks for VBCC + compiled binary identification and special-cases them + [10f3c2cc8640] + +2014-04-25 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [1955f8adcb1a] + + * tools/debugger/gst2ascii.1, tools/debugger/gst2ascii.c: + update gst2ascii similarly, and recommend using 'nm' on problems + + (main purpose for gst2ascii is easier debugging of undocumented + symbol table features by being able to do it outside of Hatari / + emulation.) + [61eb58b4a8e4] + +2014-04-24 Eero Tamminen + + * src/debug/symbols.c: + more info on binary symbols and issues, 2 different offset + calculations + + It seems that GCC symbol offsets are from given section start (TEXT, + DATA or BSS), but with VBCC, DATA and BSS symbols can be mixed also + within TEXT section, so their offsets start from TEXT section start. + + Add also some extra information to symbol loading outputs. + [dcb2cdcc0e05] + + * src/debug/symbols.c: + separate helper function + + will in next commit use it from several places + [c79b82180868] + + * src/debug/debugcpu.c, src/debug/symbols.c, src/debug/symbols.h: + add TAB-completion for symbols command + [9530e1bcd651] + +2014-04-23 Eero Tamminen + + * doc/emutos.txt: + major EmuTOS compat update in preparation to new Hatari release + [e25751834176] + +2014-04-22 Eero Tamminen + + * src/options.c: + change run-time exception debugging mask if it's already enabled + + I.e. make "-D --debug-except bus" equal to "--debug-except bus -D". + + Run-time exception mask is changed only if it's non-zero, this way + mask can be changed without enabling it (yet), to support use-case + where mask is given on command line, but toggled later at run-time. + [2b43a48622a1] + +2014-04-17 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [c6386064c587] + + * src/debug/breakcond.c, tests/debugger/test-breakcond.c: + allocate conditional breakpoints and their conditions dynamically + + - This removes limits on how many of them user can use + - Minor improvements to breakpoint debug output + - Updated debugger breakpoint tests + [eb27e0426f5a] + +2014-04-15 Nicolas Pomarede + + * doc/compatibility.html: + Treasure Trap loads correctly only with Hatari >= 1.8 + [937112472c43] + +2014-04-08 Eero Tamminen + + * src/debug/debugcpu.c, src/debug/debugdsp.c: + fix: use explicit base prefix in case user had changed number base + [f8a3f7f657ee] + +2014-04-07 Eero Tamminen + + * src/debug/debugInfo.c: + by default, show next instruction when entering debugger + [aa9c56e355c5] + + * doc/manual.html, src/debug/debugcpu.c, src/debug/debugdsp.c: + support for "n return" (run until next subroutine/exception return) + [40bb46adbf11] + +2014-03-23 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Update docs for HighResMode demo by Paradox + [6378cc9d7d31] + + * src/video.c: + Correctly align bitmap and colors for STE in med res overscan at 60 + Hz (fix 'HighResMode' by Paradox) + [79a25dd40bec] + +2014-03-05 Eero Tamminen + + * src/screen.c: + (disabled) debug output for ST screen resolution debugging + [d357cecf4a86] + +2014-02-23 Eero Tamminen + + * doc/hatari.1, doc/images/screen.png, doc/manual.html, doc/release- + notes.txt: + update documentation to screen option changes + [9488d40040dc] + + * src/options.c: + -z 1 to allow border, max size is generic option, description + improvements + [a19fee326303] + + * src/falcon/hostscreen.c, src/gui-sdl/dlgScreen.c, + src/includes/resolution.h, src/resolution.c: + add KeepResolutionST option support to SDL GUI + code improvements + [fc9325492709] + + * src/statusbar.c: + fix indent + [1df027b151d6] + +2014-02-21 Thomas Huth + + * doc/manual.html: + Initial text in Falcon/TT display options should not be bold + [a444de3c124f] + +2014-02-21 Eero Tamminen + + * doc/manual.html, doc/release-notes.txt: + document "next" command update + [97517b26e4e1] + + * src/debug/debugcpu.c, src/debug/debugdsp.c: + improve next command to work like with other debuggers + + "next" skips subroutine/exception calls, for all other instructions + it works like "step" command + [2aa969814a5a] + +2014-02-20 Eero Tamminen + + * src/debug/natfeats.c: + add ifdeffed out "command" NF + NF debug output fine-tuning + + Use the correct (capitalized) native feature names in debug output. + + "command" NF can be used to replace XBios(255) feature. Disabling + XBios(255) would make --bios-intercept safe to enable automatically + when BIOS or XBIOS OS calls are traced. + [41f045f853ef] + +2014-02-18 Nicolas Pomarede + + * src/fdc.c: + Change FDC_DMA.BytesInSector to signed int + [922d26631521] + + * src/fdc.c: + Fix FDC_DMA.SectorCount update in FDC_DMA_FIFO_Pull(), causing data + loss when writing a sector FDC_DMA.SectorCount was set to 0 too + early, which caused the last 15 bytes of a sector to be written as + '0' and also set DMA error in bit 0 of DMA status + [b05fda81592a] + +2014-02-11 Eero Tamminen + + * doc/manual.html: + fix typo + [20f6b4914ce0] + +2014-02-09 Eero Tamminen + + * doc/manual.html: + separate section for stepping + next command instruction type option + documentation + [fa10ba478685] + +2014-01-28 Eero Tamminen + + * doc/hatari.1, doc/manual.html, doc/release-notes.txt: + update documentation + + - add --debug-trace option description + - update --trace option description + - wrap too long release notes lines to 80 cols + [b5513f2448a7] + +2014-01-27 Eero Tamminen + + * src/configuration.c, src/cpu/newcpu.c, src/debug/debugui.c, + src/debug/debugui.h, src/debug/log.c, src/debug/log.h, + src/falcon/dsp_cpu.c, src/includes/configuration.h, src/options.c, + src/uae-cpu/newcpu.c: + exception debugging support rewrite + + - log.c trace option handling generalization to support parsing of + also exception flags + - user can select which exceptions invoke debugger with --debug-except + option and this selection is saved with configuration + - --debug is still used to toggle exception debugging on/off, but it + now sets mask instead of boolean + - related API changes in old UAE newcpu.c & dsp_cpu.c + - added preliminary support for exception debugging to WinUAE CPU core + [cb711d0112c3] + +2014-01-20 Eero Tamminen + + * doc/emutos.txt: + add floppy-only games, remove duplicates + [32fe6f0bf5c3] + + * doc/todo.txt: + add bug about Videl screen address counter + [0de6113c9f95] + +2014-01-19 Thomas Huth + + * src/cpu/memory.c, src/uae-cpu/memory.c: + Limit information about illegal memory accesses to avoid flooding of + the console. + [bc7f7a3ee890] + +2014-01-12 Nicolas Pomarede + + * src/fdc.c: + FDC DMA address must be word-aligned, always force bit 0 to 0 + [f87a9c7c9751] + +2014-01-11 Thomas Huth + + * src/cpu/newcpu.c, src/uae-cpu/newcpu.c: + Unused bits in CAAR register should not be tied to zero. Thanks to + Douglas Little for the hint. + [a6bde357021a] + +2014-01-08 Eero Tamminen + + * tests/natfeats/nf_asm.s, tests/natfeats/readme.txt: + add readme and preliminary GCC / Gas ASM version + [baa7ca42b28c] + + * tests/natfeats/Makefile.vbc, tests/natfeats/natfeats.c, + tests/natfeats/natfeats.h, tests/natfeats/nf_asmv.s, + tests/natfeats/nf_vbcc.tos: + add VBCC example on using Native Features from Atari code + [685b1b4ea51a] + +2014-01-02 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Update doc/release notes + [b8adae9deace] + + * src/spec512.c: + Update write cycle's position when using 'add' to change a color + register (fix 'add d1,(a0)' in '4-pixel plasma screen' by TOS Crew) + [19bdb54f05bb] + +2014-01-01 Nicolas Pomarede + + * src/cycles.c: + Modify write timings for opcodes AND, OR and EOR (prefetch, then + write) + [c02c2cf9da2f] + + * src/cycles.c: + Modify write timings for opcodes ADD and SUB (prefetch, then write) + (Used in 4-pixel plasma screen by TOS Crew) + [5aef63763463] + + * src/cycles.c: + Opcodes NEG, NEGX and NOT have the same write timing as CLR + [9c5c8eeb5345] + +2013-12-28 Nicolas Pomarede + + * src/debug/68kDisass.c: + Fix out of bounds memory access that could result in bad disassembly + output + [f1cd5433e51a] + + * doc/release-notes.txt: + Update release notes + [ea0b3001c01e] + + * src/video.c: + Adjust 50 Hz max position for bottom border removal on a 60 Hz + screen (fix "It's a girl 2" by Paradox) + [7211814b4e3e] + + * src/fdc.c: + Use PRIu64 to print Uint64 values 32/64 bits mode without gcc's + warnings + [92a723bcadfb] + +2013-12-27 Laurent Sallafranque + + * src/cpu/falcon_cycle030.h: + 68030 timings fix: LEA instructions timings were wrong. + [730a8d185629] + + * src/falcon/dsp_cpu.c: + DSP fix: SR was not correctly restored at the end of a loop. + [ff3a16527500] + +2013-12-27 Thomas Huth + + * readme.txt: + Clarified one sentence in the license statement, according to Eero's + suggestion + [4b38f9e34b8c] + +2013-12-27 Nicolas Pomarede + + * src/fdc.c: + Also update unused bits of $ff8604 when DMA sector count is 0 + [1e50c3b9b2bb] + +2013-12-26 Nicolas Pomarede + + * src/fdc.c: + On STF/STE machines, FDC DMA addresses are limited to 0x3fffff + [7511460e8ba1] + + * src/fdc.c: + Remove old define for DMA transfers + [081c7e921408] + +2013-12-25 Nicolas Pomarede + + * src/fdc.c: + Typos + [b74b3710fb21] + + * src/fdc.c: + Report an error in DMA Status if DMA sector count is 0 when we get + some DRQ to process + [f84eb81fa309] + + * src/fdc.c: + Improve the content of unused bits in DMA Status at $ff8606 + [7d3c0e127206] + + * src/video.c: + Force unused "random" bits to 0 in STF color regs when building our + conversion palette + [b801f13a53d8] + + * src/fdc.c: + For FDC tranfers, use the more accurate FDC_DMA_FIFO_Push() and + FDC_DMA_FIFO_Pull() + [6bb6bd3bae4f] + +2013-12-24 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt, src/video.c: + Update docs about unused bits in STF's color registers + [b3e255dcc424] + + * src/video.c: + In STF mode, bits 4, 7 and 11 of color registers are not always 0 + when read The exact value of these 3 bits depends on the latest word + access on the BUS, so we use random for now as a tradeoff (fix 'UMD + 8730' by PHF, as noted in Steem SSE 3.5.5) + [c30a36557db7] + + * src/includes/video.h, src/ioMemTabST.c, src/ioMemTabSTE.c, + src/video.c: + Use a specific handler to intercept reads in the color registers + $ff8240-$ff825e + [e31a1e5bd3c9] + +2013-12-22 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [118f73f76602] + + * src/debug/natfeats.c: + add debugger invocation native feature + [c065da1168ab] + + * src/cart.c, src/gemdos.c: + allow GEMDOS/VDI/AES to be traced without GEMDOS emu / VDI + interception + [daa503e19a71] + + * doc/compatibility.html: + more links to listed SW + [4f53ecf04802] + +2013-12-22 Nicolas Pomarede + + * src/fdc.c: + Fix typo in change #4835 affecting drives' led color + [964347d84dbd] + +2013-12-21 Thomas Huth + + * readme.txt: + Added information about the IPF library to the readme.txt + [36bc5c4cc8b0] + +2013-12-21 Eero Tamminen + + * doc/emutos.txt: + update emutos compat list + [163d2e77e8de] + +2013-12-18 Thomas Huth + + * src/gui-osx/PrefsController.m: + Fixed the ACSI hard disk settings in OS X PrefsController + [aed7d99deea1] + +2013-12-17 Nicolas Pomarede + + * src/fdc.c, src/floppy_ipf.c, src/includes/fdc.h: + Update drives' led color also when using IPF disks + [0d05a6a79837] + + * src/floppy_ipf.c: + Display a warning dialog for IPF disks not yet correctly emulated + [9c9b2082868d] + +2013-12-17 Thomas Huth + + * src/change.c, src/configuration.c, src/gui-sdl/dlgHardDisk.c, + src/hdc.c, src/includes/configuration.h, src/options.c: + Changed the configuration infrastructure for supporting multiple + ACSI devices + [8599264183e3] + +2013-12-17 Nicolas Pomarede + + * src/fdc.c, src/hdc.c, src/includes/hdc.h: + For FDC/HDC, improve DMA sector count (which can't be read) and DMA + status As observed on a real STF, we set the unused bits depending + on the latest access made at $ff8604 + [dff3a89fd82e] + +2013-12-11 Nicolas Pomarede + + * CMakeLists.txt: + Print a summary of the optional libraries detected with a short + explanation + [c6f8afe201db] + +2013-12-06 Thomas Huth + + * src/hdc.c: + Cleaned up the setting of DMA status and IRQ + [39eb3b14f586] + +2013-11-25 Thomas Huth + + * src/debug/log.c, src/debug/log.h, src/hdc.c: + Added proper tracing support for SCSI/ACSI commands + [3f33266cb872] + +2013-03-17 Nicolas Pomarede + + * src/uae-cpu/gencpu.c: + Add refill_prefetch for i_SUB, i_NEG, i_NEGX, i_NOT (similar to + i_ADD/i_EOR) + [a8415000a35a] + + * src/uae-cpu/newcpu.c, src/uae-cpu/newcpu.h: + In refill_prefetch(), reload only one new word in regs.prefetch if + low word is still valid (fix EOR/ADD self modified code in the + protection for the game Damocles) + [0f3958daef4b] + +2012-09-24 Nicolas Pomarede + + * src/fdc.c: + Use the IPF mode for an empty drive if the other drive contains an + IPF image + [269f6caa460d] + + * src/includes/fdc.h: + Fix GPL text + [0013a29520df] + +2012-09-01 Nicolas Pomarede + + * src/uae-cpu/newcpu.c: + Add a special case to correct the stacked PC when a bus error + happens during a movem (fix the original protection in the IPF + version of the game Blood Money) + [895c71bd97bb] + + * src/floppy_ipf.c: + When restoring snapshots with IPF data, some internal pointers must + be recomputed + [41fc480183f4] + +2012-08-26 Nicolas Pomarede + + * src/floppy_ipf.c: + Improve checks when restoring a memory snapshot with IPF data + [216cd9e2bc03] + +2012-08-25 Nicolas Pomarede + + * src/floppy_ipf.c: + Use MemorySnapShot_Skip to skip unsupported IPF data instead of + using a temp buffer + [4bd542743135] + + * src/includes/memorySnapShot.h, src/memorySnapShot.c: + Add MemorySnapShot_Skip to skip some parts of a snapshot when + restoring it + [78a2aa91f721] + + * src/floppy_ipf.c: + Handle restoring snapshot with different IPF built options than + Hatari + [dcf6968e468d] + + * src/memorySnapShot.c: + Correct order when saving/restoring snapshots with IPF + [a15a0c75a60e] + +2012-08-24 Nicolas Pomarede + + * tools/hmsa/hmsa.c: + Add an empty IPF_FileNameIsIPF function to be able to build without + IPF support + [8696d2afcf2e] + + * src/fdc.c: + Automatically choose the FDC mode depending on the selected drive + and the image type + [769e641e68ec] + + * src/floppy_ipf.c: + Print ImageId when inserting an IPF image + [35a5ba6d59a4] + + * src/floppy.c: + More detailed comments for Floppy_SetDriveSide + [54dcddbcc0d6] + +2012-08-23 Nicolas Pomarede + + * src/floppy_ipf.c: + Remove unnecessary include + [a2997a678de6] + +2012-08-20 Nicolas Pomarede + + * src/floppy_ipf.c: + If compiling without capsimage support, IPF_STRUCT should be empty + [b6990053baaa] + + * src/floppy_ipf.c, src/includes/floppy_ipf.h, src/memorySnapShot.c: + Add support for saving IPF state in memory snapshots + [ecd01e65bda5] + + * src/floppy_ipf.c: + Store capsimage library's version into IPF_State structure + [d0190f3ddfb9] + + * src/floppy_ipf.c: + After changing drive/side, call IPF_Emulate to take the change into + account immediatly + [049ab355f462] + + * src/floppy_ipf.c: + Add more infos in IPF logs + [f5f0fcaa08bf] + + * src/floppy_ipf.c: + Call IPF_Emulate before accessing an FDC's register + [44860a1ed98d] + + * src/floppy_ipf.c, src/includes/floppy_ipf.h, src/video.c: + In IPF_Emulate, use IPF_State.FdcClock to compute the requested + number of cycles to emulate + [d7f7ced27ff7] + + * src/reset.c: + FDC_Reset should be called for cold and warm reset + [802a0e03c0d9] + + * src/fdc.c, src/floppy_ipf.c, src/includes/floppy_ipf.h: + Call IPF_Reset from FDC_Reset + [b03a86b90ed2] + + * src/floppy_ipf.c: + Add FdcCLock / CyclesGlobalClockCounter + [0bdf74b05090] + + * src/reset.c: + Reset master clock counter during a cold/warm reset + [6ad92ca089d4] + +2012-08-19 Nicolas Pomarede + + * src/cycles.c, src/includes/cycles.h: + Add a global counter to count cpu cycles and give a master clock + since last reset + [c8043d7b3336] + + * src/cycles.c: + Split code in Cycles_GetCounterOnReadAccess / + Cycles_GetCounterOnWriteAccess + [3343413cebf0] + +2012-08-09 Nicolas Pomarede + + * src/floppy_ipf.c: + Fix comment + [8023fed82408] + + * src/floppy_ipf.c: + IPF disk images are write protected (writing to IPF is not supported + yet) + [f08b4aacd7cf] + +2012-08-08 Nicolas Pomarede + + * src/fdc.c: + Add FDC_GetEmulationMode in FDC_DiskControllerStatus_ReadWord to use + internal or ipf emulation + [9c13166a9e12] + + * src/fdc.c: + Add FDC_GetEmulationMode in FDC_DiskController_WriteWord to use + internal or ipf emulation + [8ac165f2de31] + +2012-08-05 Nicolas Pomarede + + * src/floppy_ipf.c: + Don't add IPF callback functions if capslibrary is not used + [14cead05ca62] + + * src/zip.c: + Add support for loading IPF images directly from ZIP files + [7c18e9e67fe4] + + * src/floppy.c, src/includes/zip.h, src/zip.c: + Return ImageType in ZIP_ReadDisk, also uses FLOPPY_IMAGE_TYPE_xxx + instead of ZIP_FILE_xxx + [4998ef631f6d] + +2012-08-03 Nicolas Pomarede + + * src/fdc.c: + Add some notes on the timings required for precise FDC's emulation + [d5c9b9b4ea6b] + +2012-08-02 Nicolas Pomarede + + * src/floppy_ipf.c: + In IPF_Insert, call CAPSLoadImage to cache all tracks earlier + [916055a44d1c] + + * src/fdc.c, src/floppy_ipf.c: + In IPF_CallBack_Trk, call CAPSLockTrack to update the track data -> + emulation is working First tests with Virus and The Pawn are good, + games are working + [56d8737cb303] + +2012-07-31 Nicolas Pomarede + + * src/floppy_ipf.c: + Add VBL number to IPF traces + [91a732d5a84d] + + * src/floppy_ipf.c: + Add more traces + [f5de019b9d2c] + + * src/video.c: + Temporary call IPF_Emulate on each HBL + [da99f8f174c9] + + * src/floppy_ipf.c: + Change CAPSDRIVE_DA_IN attribute when an IPF image is + inserted/ejected + [c7dc61257a4a] + + * src/fdc.c: + Replace read / write to $ff8604 with call to IPF_FDC_ReadReg / + IPF_FDC_WriteReg + [8d8bc16c90d7] + + * src/floppy_ipf.c, src/includes/floppy_ipf.h: + Add IPF_FDC_WriteReg and IPF_FDC_ReadReg + [a9860453a064] + +2012-07-29 Nicolas Pomarede + + * src/fdc.c: + Typo + [b7b20873aa27] + + * src/fdc.c: + On DMA reset, reset sector count + add some notes about DMA + [9a923296a884] + + * src/fdc.c, src/floppy_ipf.c, src/includes/fdc.h: + Complete the DMA FIFO to be used by external fdc emulation libraries + (IPF support) + [e24072d32dcb] + + * src/fdc.c, src/floppy_ipf.c, src/includes/fdc.h: + Add FDC_DMA_FIFO_Pull/FDC_DMA_FIFO_Push to IPF_CallBack_Drq + [b31b7af68fcf] + + * src/fdc.c, src/includes/fdc.h: + Add FDC_DMA_GetModeControl_R_WR + [973b08a6d13b] + + * src/floppy_ipf.c: + Indent spaces -> tabs + [fafd38d655c2] + + * src/floppy_ipf.c: + In IPF_Insert, returns false if CAPSLockImageMemory fails + [e0eaf024e664] + + * src/fdc.c: + Typo + [03d24b9d234a] + + * src/floppy_ipf.c, src/includes/floppy_ipf.h: + Add IPF_Emulate to run the FDC's emulation for a given number of + cycles + [4adde785550d] + + * src/floppy.c, src/floppy_ipf.c, src/includes/floppy.h, + src/includes/floppy_ipf.h, src/psg.c: + Call Floppy_SetDriveSide / IPF_SetDriveSide for each write to reg $E + in $ff8802 (IO_PORTA) + [137124191412] + +2012-07-22 Nicolas Pomarede + + * src/floppy_ipf.c, src/includes/floppy_ipf.h: + Add IPF_SetDriveSide + [e28b91658024] + + * src/floppy.c, src/floppy_ipf.c, src/includes/floppy_ipf.h, + src/main.c: + Improve IPF_Init, IPF_Insert and IPF_Eject + [18cb5adca07f] + + * src/fdc.c, src/includes/fdc.h: + Add FDC_ClearIRQ + [d02d972cacf0] + +2012-07-18 Nicolas Pomarede + + * src/floppy.c, src/floppy_ipf.c, src/includes/floppy_ipf.h: + Move some parts of IPF_ReadDisk into IPF_Insert + [1955637efa2b] + +2012-07-17 Nicolas Pomarede + + * src/dim.c, src/floppy.c, src/includes/floppy.h, src/msa.c, src/st.c: + Don't set ImageType if the disk image can't be loaded + [97f53814200a] + +2012-07-15 Nicolas Pomarede + + * src/floppy_ipf.c, src/main.c: + Init CAPS library and print some debug infos about the IPF file + [c7a5c034c8cf] + + * src/floppy_ipf.c: + If Hatari is built without capsimage lib, print an error message + when opening IPF files + [789d9957708c] + + * src/CMakeLists.txt, src/floppy.c, src/floppy_ipf.c, + src/includes/floppy.h, src/includes/floppy_ipf.h: + Add .ipf as a valid disk image extension and load data into a buffer + [2249b57dbfec] + + * src/dim.c, src/floppy.c, src/includes/dim.h, src/includes/floppy.h, + src/includes/msa.h, src/includes/st.h, src/msa.c, src/st.c, + tools/hmsa/hmsa.c: + Add ImageType (ST, MSA, DIM) to the floppy drive's emulation + structure + [7d33d795eacd] + +2012-07-14 Nicolas Pomarede + + * CMakeLists.txt, cmake/FindCapsImage.cmake, cmake/config-cmake.h, + src/CMakeLists.txt: + Add support for the capsimage library in the build process + [3153973a34e3] + +2013-12-06 Nicolas Pomarede + + * doc/hatari.1, doc/manual.html, doc/release-notes.txt, src/options.c: + Add --drive-a and --drive-b options to enable/disable a floppy drive + (this is better than giving an empty file name to --disk-a and + --disk-b) + [38f7941cb87f] + +2013-12-03 Nicolas Pomarede + + * doc/release-notes.txt: + Update release note + [8bd2066835b9] + + * src/video.c: + When $ff8260 is set to 3 (which is not a valid resolution mode), use + 2 instead (high res) Cancel wrong change from 2008/07/19 and fix + 'The World Is My Oyster - Convention Report Part' by Aura + [658807f42b3a] + +2013-11-29 Nicolas Pomarede + + * src/configuration.c: + Correctly calls FDC_EnableDrive() for each drive when the + configuration is applied + [70ece9b17fcf] + + * src/fdc.c: + Don't use LOG_TRACE in FDC_EnableDrive for now as Log_Init was not + called yet + [e396188b8ddf] + + * doc/release-notes.txt: + Update release notes with FDC's changes + [dd8a758aa23b] + + * src/fdc.c: + Regroup code for FDC's cycles per revolution and handle Falcon's 16 + MHz FDC case + [17bd4b5f4574] + +2013-11-28 Eero Tamminen + + * doc/emutos.txt: + add few new demos to emutos compat list + [454f7685ea92] + +2013-11-27 Nicolas Pomarede + + * src/fdc.c: + Fix CPU<->FDC cycles' conversion when x2 or x4 CPU speed is used + [3d9ac7227e5d] + + * src/fdc.c: + Use unsigned int to convert FDC/CPU cycles + [53f94c7fad17] + + * src/fdc.c: + For FDC's cycles per revolution, use cycles in FDC units instead of + CPU units This gives the same results, it's just clearer to have as + much values in FDC units as possible and convert them to CPU units + when needed. + [f844a3cbd64f] + +2013-11-24 Thomas Huth + + * doc/compatibility.html, doc/manual.html: + Switched docs to UTF-8 as recommended by the W3 validator + [322ddc3c81b9] + +2013-11-23 Thomas Huth + + * doc/images/system.png, doc/manual.html: + Updated the system dialog in the manual + [693d6f84250b] + +2013-11-23 Nicolas Pomarede + + * doc/hatari.1, doc/manual.html: + Update manuals about giving an empty string for a floppy/HD image to + disable it + [74ce1640aaf3] + + * src/hdc.c: + Rename functions used to set FDC/HDC's IRQ + [a67415932281] + +2013-11-17 Thomas Huth + + * src/gui-sdl/dlgSystem.c: + Merged the the system settings dialogs. The two different system + settings dialogs, one for the UAE and one for the WinUAE CPU, + already started to diverge (fast boot option was missing in the + latter). I've merged the two now to avoid this problem in the + future. + [d85c6a0f8b4c] + +2013-11-16 Thomas Huth + + * doc/manual.html: + Replaced the wrong dashes in the manual with proper '-' characters. + Thanks to David Savinkoff for the hint. + [826fb2530bbe] + +2013-11-16 Eero Tamminen + + * src/debug/debugui.c: + release mouse when debugger is invoked + + Unfullscreening was also already handled at debugger invocation, but + mouse grab was only released if user invoked debugger with a key + shortcut. + + Now mouse is released regardless of where the debugger gets called + from. + + Note: grab isn't automatically re-taken an exiting from debugger + except when user invokes debugger with keyboard shortcut. Fullscreen + isn't restored either, but as that hasn't been an issue, I assume + this isn't either. User can always re-invoke grab & fullscreen after + emulation continues. + [1096f01e8ebf] + +2013-11-03 Thomas Huth + + * src/hdc.c: + ACSI/SCSI: Moved status variables into device and controller + structures to get ready for supporting multiple devices and buses + later. + [ffd21fefd093] + + * src/main.c: + Added now a proper fix for the problem when nDelay gets too big + [60d552d65368] + +2013-11-02 Thomas Huth + + * src/main.c: + Coding style: Indent with tabs, not with spaces + [a16df835c29a] + + * src/main.c: + Fix time overflow problem when DestTicks overlowed to negative + numbers. Thanks to David Savinkoff for the patch. + [2575b119b058] + +2013-11-23 Nicolas Pomarede + + * src/fdc.c: + Fix error in FDC_GetCmdType + [e4399fbf8667] + +2013-11-18 Nicolas Pomarede + + * src/fdc.c: + Update some comments + [df4f7ae4d4bc] + + * src/fdc.c: + Remove FDC_SIDE macro + [35d70d033f7a] + + * src/fdc.c: + Better code to simulate HD/ED floppies with higher density + [28f763e56186] + +2013-11-17 Nicolas Pomarede + + * src/fdc.c: + Don't ignore FDC commands when no drive is selected + [b937a2f98b14] + + * src/fdc.c: + Remove macro FDC_DRIVE and FDC_FindFloppyDrive() + [9ff2b55bcdd8] + +2013-11-15 Nicolas Pomarede + + * src/fdc.c: + Remove old FDC_DRIVE macro + [6cbd2f41f37b] + + * src/fdc.c: + Rewrite some FDC functions regarding drive/floppy geometry + [0be5ae158dbb] + +2013-11-14 Nicolas Pomarede + + * src/fdc.c: + Add notes and update code about the replace command case in the FDC + [ba9e20afe2dd] + +2013-11-13 Nicolas Pomarede + + * src/fdc.c: + Update the FDC's state machine to handle sub-states of 0 cycle + [37fdd926b971] + +2013-11-12 Nicolas Pomarede + + * src/fdc.c: + Update the location to replace a running command in the FDC + [8f74e3d53eea] + + * src/fdc.c: + Remove old/unused parts of the FDC's emulation + [d07953a01aac] + +2013-11-11 Nicolas Pomarede + + * src/fdc.c: + Rewrite the FDC 'force interrupt' type IV command using index pulses + counter Also improve the IRQ behaviour when 'force interrupt + immediate' is used. + [f3cdc653ce84] + + * src/fdc.c, src/hdc.c, src/includes/fdc.h: + Rename functions used to set/clear FDC's IRQ + [40f4125a395c] + + * src/fdc.c: + Adjust the duration of the FDC's index pulse signal + [c86395f53e70] + + * src/ioMem.c: + Put PC address at the end of IO read/write traces + [7514383e69a9] + + * src/fdc.c: + Rewrite the FDC 'read next address ID' sequence using index pulses + counter This is used in the 'verify' sequence for type I commands, + in type II commands when looking for the sector FDC.SR and in type + III command 'read address'. We now also correctly handles the cases + where the drive is not enabled or empty (wait for a valid + drive/floppy instead of aborting the command) + [7e1172a8bfef] + +2013-11-09 Nicolas Pomarede + + * src/fdc.c: + Remove old unused functions + [911e4ff93129] + + * src/fdc.c: + Improve the content of the FDC's status register for type I mode + Some bits were not correctly updated in some cases when drive was + off or empty + [9bbbb1c05620] + +2013-11-06 Nicolas Pomarede + + * src/fdc.c: + Rewrite the FDC 'motor stop' sequence using index pulses counter + [da40a0eaba0a] + +2013-11-05 Nicolas Pomarede + + * src/fdc.c: + Improve head settle delay sequence for FDC's type I commands + [ff3cb1d245ef] + + * src/fdc.c: + Move the head settle delay at the correct place for FDC's type II + and III commands + [f6e4457d81d9] + + * src/fdc.c: + Rewrite the FDC spin up sequence using proper index pulses counter + This now uses the same logic as the WD1772 to count floppy's + rotation using index pulses, and will also give accurate behaviour + when there's no drive or floppy available during the spin up + sequence. + [92935aced61a] + +2013-11-01 Nicolas Pomarede + + * src/fdc.c: + Improve FDC's accuracy when drive is switched off or no floppy is + inserted + [4fc90e3c9f7a] + +2013-10-31 Eero Tamminen + + * src/debug/profilecpu.c: + keep CPU profiles address indexes in order + + Previous code assumed that TOS is always before cartridge area. + However, TOS can be mapped either before or after cartridge area. + Take that into account when mapping addresses to indexes and back. + This fixes profiler data post-processor assert. + + Use symbolic names for cartridge area start and end addresses. + [fdbddd89d916] + +2013-10-31 Nicolas Pomarede + + * doc/release-notes.txt, src/change.c, src/configuration.c, src/gui- + sdl/dlgFloppy.c, src/includes/configuration.h, src/options.c: + Update the UI and the configuration file to store if a drive is + enabled/disabled + [407c7e71ebd1] + +2013-10-30 Nicolas Pomarede + + * doc/release-notes.txt, src/fdc.c, src/includes/fdc.h, src/options.c: + Giving empty string as a disk's image disables the corresponding + drive + [a93f5feade35] + + * src/configuration.c: + Use MAX_FLOPPYDRIVES instead of a constant + [4eb5a3952f93] + +2013-10-27 Nicolas Pomarede + + * src/fdc.c: + Improve physical head accuracy for FDC type I commands We should + update the head's position only if the selected drive is enabled + [ff892bb490df] + + * src/main.c: + Initialise emulation sooner for some hardware components For + example, we must init FDC before inserting some floppy + [6531c6be3f78] + + * src/fdc.c: + Store head's position in the drive's structure + [bcebef4f4eed] + + * src/fdc.c: + When FDC's motor stops, spinup bit should not be cleared + [28fc77bf6428] + +2013-10-27 Thomas Huth + + * doc/release-notes.txt: + Updated release notes with recent ACSI changes + [00128c83c010] + + * src/hdc.c, src/includes/hdc.h: + ACSI/SCSI: Changed wording from 'device' to 'LUN' to avoid + confusions and fixed the handling of REQUEST SENSE for illegal LUNs. + [11342f1d688a] + + * src/hdc.c: + ACSI/SCSI: Fixed handling of unsupported commands + [e463249b57b4] + +2013-10-27 Nicolas Pomarede + + * src/cpu/hatari-glue.c, src/fdc.c, src/includes/fdc.h, src/reset.c, + src/uae-cpu/hatari-glue.c: + Don't reset TR and DR when the FDC is warm reset As verified on a + real STF, these registers are not affected by a warm reset (if the + RESET instruction is used for example). Only STR and SR are reset. + [52c722346da6] + +2013-10-27 Thomas Huth + + * src/hdc.c: + ACSI/SCSI: Reject reads/writes with illegal sector numbers. Thanks + to Uwe Seimet for the hint. + [d92cf1c0bee8] + + * src/hdc.c: + ACSI: Reset command counters when A1 pin is zero + [bdace53e5a21] + + * src/hdc.c: + ACSI: Get size of image via the size of the file instead of using + the MBR. Thanks to Uwe Seimet for the hint. + [8a7cab1466fd] + +2013-10-26 Thomas Huth + + * src/hdc.c: + Fixed the nLastBlockAddr mess, and use fseeko for ACSI hd images + [50cc837fe038] + + * CMakeLists.txt, cmake/config-cmake.h, src/file.c, src/ide.c, + src/includes/file.h: + Use fseeko instead of fseek for IDE image files + [2eccafefe46e] + +2013-10-26 Nicolas Pomarede + + * src/sound.c: + Update comment + [078cc3391541] + +2013-10-26 Thomas Huth + + * src/hdc.c: + ACSI/SCSI: Fill INQUIRY buffer with more sane values. Thanks to Uwe + Seimet for the hint. + [2c93a1fd65bf] + +2013-10-25 Nicolas Pomarede + + * src/fdc.c: + Update drive's density each time a floppy is inserted + [04408abd8aea] + +2013-10-24 Nicolas Pomarede + + * src/fdc.c, src/floppy.c, src/includes/fdc.h: + Update drives' state when a floppy is inserted/ejected from the UI + [3402e429164b] + + * src/fdc.c: + Don't directly access ff8802 to change the busy led of a drive + [17d4a0a1693c] + + * src/fdc.c: + Don't directly access ff8802 to check if a drive is selected + [4d0c7bb1512c] + + * src/fdc.c: + Don't directly access ff8802 to get the side used by the FDC + [a3e477165f38] + + * src/fdc.c: + Add FDC's drives to the memory snapshot + [ecd7ec7e1c0b] + + * src/fdc.c: + Store the density of the floppy inserted in each drive (DD/HD/ED) + [677663677ab6] + + * src/fdc.c: + Remove old variable in FDC's emulation + [52192df634e9] + + * src/fdc.c, src/includes/fdc.h, src/psg.c: + Report side/drive changes in porta register directly to the FDC's + emulation + [ed63b7394987] + +2013-10-06 Thomas Huth + + * src/fdc.c, src/hdc.c, src/includes/hdc.h, src/reset.c: + SCSI: First steps towards Falcon NCR5380 register handling + [ca5439819515] + + * src/tos.c: + Skip some delays during TOS 4.04 boot + [519fb3b63eb0] + +2013-10-22 Eero Tamminen + + * doc/compatibility.html, doc/emutos.txt: + add note for couple of newish STE demos + [fd77306de99c] + +2013-10-21 Thomas Huth + + * src/hdc.c: + Fix the handling of SCSI commands with opcode >= 0x40. Thanks to Uwe + Seimet for the hint. + [52b90cb51ad6] + + * src/hdc.c: + READ CAPACITY updated the DMA counter to a wrong value. Thanks to + Uwe Seimet for the patch. + [488bceeea054] + + * src/hdc.c: + According to the SCSI standard, INQUIRY must also be handled for + unknown LUNs. Thanks to Uwe Seimet for the patch. + [ac4f7a925ebd] + +2013-10-13 Eero Tamminen + + * doc/release-notes.txt: + update + fix typo + [8a61bbeb6b39] + +2013-10-12 Eero Tamminen + + * src/control.c: + newline for errmsg + [74a83f54e46c] + + * src/control.c, src/includes/control.h, src/xbios.c: + fix: XBios(255) modified its argument + [4a6e97653e32] + + * doc/manual.html: + add ":once" option to breakpoint chaining examples + + While that option isn't needed in that specific example, people can + use those examples for breakpoints where they could be hit several + times, but shouldn't, so it's better to have ":once" in the + examples. + [7aba54c1dbd5] + +2013-10-11 Eero Tamminen + + * doc/emutos.txt: + more music apps work with EmuTOS + [58c36336b070] + +2013-10-07 Nicolas Pomarede + + * src/fdc.c: + Remove old unused FDC code + [558497b06d63] + +2013-10-07 Laurent Sallafranque + + * doc/release-notes.txt: + Added Reeking rumber as working game + [1100567cbf16] + +2013-10-06 Nicolas Pomarede + + * doc/release-notes.txt: + Add changes about FDC (index pulses, RPM) + [dc4f209a5d3d] + +2013-10-01 Eero Tamminen + + * doc/emutos.txt: + degas elite & spofl work + [1b0e45e97718] + +2013-09-29 Eero Tamminen + + * doc/emutos.txt: + add few ste demos to emutos compat list + [cfaae0aefe04] + +2013-09-28 Eero Tamminen + + * src/fdc.c: + fix compiler warning + [adcecb6c42ba] + + * src/debug/profilecpu.c: + improve comment, collect callgraphs also for exception calls + [a613cf9864d4] + + * doc/emutos.txt: + update EmuTOS notes for latest CVS version with line-A support + [4f605eea0bb2] + + * doc/release-notes.txt: + update release notes + [a14fe758629a] + +2013-09-27 Thomas Huth + + * src/hdc.c: + Fixed READ CAPACITY command for ACSI hard disk images. Thanks to + Roger Burrows for the detailed bug report. + [a1ed85f1db31] + +2013-10-06 Nicolas Pomarede + + * src/fdc.c: + Also update the status register in $ff8604 when there's no busy + command (this is required to correctly report the index bit after a + force int command on index succeeded) + [30a6ef27fea1] + + * src/fdc.c: + Add support for the Force Int on Index Pulse command in the FDC + (this command is often used by programs to measure the RPM speed of + a floppy drive. For example, this will fix PANZER.PRG and + FLRPMM.PRG) + [a7cbb6cb0981] + + * src/fdc.c: + Use the drives' RPM speed to get better accuracy for the index + signal + [56c7d5f41388] + +2013-09-26 Nicolas Pomarede + + * configure: + Add more options to build 32 or 64 bit Windows versions using + mingw-w64 + [95e0fc177a8f] + +2013-09-25 Nicolas Pomarede + + * cmake/Toolchain-mingw32.cmake: + Allow the user to override mingw's default values This allows to use + mingw32 or mingw-w64 by giving -D parameters to cmake + [f2d61ea289d2] + +2013-09-21 Nicolas Pomarede + + * cmake/Toolchain-mingw32.cmake: + For cross compilation, ensure CMAKE_FIND_ROOT_PATH does not contain + relative parts Having "/../" in the path seems to prevent SDL from + being correctly detected with some mingw environments + [8c2097f11fff] + +2013-09-19 Nicolas Pomarede + + * src/fdc.c: + Don't reset drives' head position when resetting the FDC Doing so + will confuse TOS or others program (if the RESET instruction is used + for example) + [fb28bfa335b0] + +2013-09-18 Nicolas Pomarede + + * src/fdc.c: + Fix HD or ED disks for ST/MSA images (18 or 36 sectors per track) + This was not correctly handled since the new fdc.c in Hatari 1.7.0. + We need to simulate a x2 or x4 track buffer to compute the correct + address field for each sector. + [b7ba0c4b6739] + + * src/fdc.c: + Fix typos + [d8a680d64627] + +2013-09-15 Eero Tamminen + + * src/gemdos.c: + show Pterm*() value as signed + [14f37d475326] + +2013-09-11 Thomas Huth + + * src/cpu/compat.h, src/cpu/custom.h, src/cpu/newcpu.c: + Removed some WinUAE specific stuff + [5a26aba30bfe] + +2013-09-09 Thomas Huth + + * src/cpu/cpummu030.c, src/cpu/newcpu.c: + Silenced some debug messages by default + [9beadacc5c4f] + + * .hgignore: + Added gst2ascii to hgignore list + [78c04b40c0ad] + + * doc/compatibility.html, src/falcon/videl.c, src/falcon/videl.h, + src/ioMemTabFalcon.c: + Fix for Reeking Rubber: Mask away unused bits in Falcon palette + [c6432898db1e] + +2013-09-09 Eero Tamminen + + * tests/debugger/test-dummies.c: + update test dummies to reflect latest debugger code + [267ba9719c95] + +2013-09-08 Thomas Huth + + * tests/debugger/Makefile, tests/debugger/makefile, + tests/tosboot/Makefile, tests/tosboot/makefile: + Renamed Makefiles so that they do not get clobbered by the distclean + target + [b86444662804] + + * cmake/DistClean.cmake: + Remove gst2ascii during distclean + [64c79549c3f8] + + * CMakeLists.txt: + Do not link against X11 libs when building an OS X application + [581c7060a3eb] + + * src/cpu/newcpu.c: + Fixed problem with MFP exceptions in MMU mode + [304e10fe5bcc] + + * CMakeLists.txt, src/dim.c, src/file.c, src/memorySnapShot.c, + src/zip.c: + Allow Hatari to be compiled without libz + [157d006c32c8] + + * src/screen.c: + SDL_HWPALETTE should only be set when using a palette resolution + [dda7920d786d] + + * src/cpu/build68k.c, src/cpu/gencpu.c: + Silenced compiler warnings that occured with GCC 4.7.2 + [ae59e8ef33ad] + +2013-09-03 Eero Tamminen + + * src/debug/profilecpu.c: + fix comment typos + [0041adb8aca1] + +2013-08-28 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [1d3a32fc00ff] + + * src/debug/debugui.c, src/debug/history.c, src/debug/history.h: + number of instructions in history is now configurable + [6138d03fc94e] + +2013-08-24 Eero Tamminen + + * src/debug/symbols.c: + fix corner case symbols command crash + + "pc = text" breakpoint gives false hits *during bootup*. While + "symbols prg" guards against this, giving symbols command the file + path to program crashed to NULL pointer check before trying to load + the symbols from program (which would fail to TEXT section size + mismatch). + [3c018be03536] + +2013-08-11 Eero Tamminen + + * tools/debugger/hatari_spinloop.py: + initial spinloop information post-processor + [d2092a842881] + + * src/debug/profile.c, src/debug/profile_priv.h, + src/debug/profilecpu.c, src/debug/profiledsp.c: + initial version of spinloop profiling + [7339722615e2] + + * src/debug/debugui.c: + add rename command to debugger + + this will be needed when doing worst frame profiling with spinloop + profiling. + [87f231f7321e] + + * src/debug/debugcpu.c, src/debug/debugdsp.c: + update "next" and "dspnext" commands help + [1eca538b4d78] + + * src/debug/breakcond.c, src/debug/debugdsp.c, src/debug/debugdsp.h: + add instruction type argument to DSP "next" command + [7ca23f8014ff] + +2013-08-10 Eero Tamminen + + * src/ioMem.c: + prefix IO read/write trace output with PC address + + It helps debugging to know where that access was done from... + [086b2e645bd2] + +2013-08-06 Eero Tamminen + + * doc/release-notes.txt: + document "next" command change to release notes + [3956db89e44b] + +2013-09-18 Nicolas Pomarede + + * src/fdc.c: + Remove old function to handle FDC delays in microsec + [8e3e7dbe560a] + + * src/fdc.c: + Use cycles instead of microsec for all internal delays used by the + FDC + [8d3c39da24a9] + +2013-07-19 Nicolas Pomarede + + * src/fdc.c, src/includes/fdc.h, src/main.c: + Add FDC_DRIVE_STRUCT to store the attributes of a physical floppy + drive This allows to turn a floppy drive on/off or change its RPM + speed. + [9e549beea4f0] + +2013-07-19 Eero Tamminen + + * src/debug/breakcond.c, src/debug/debugcpu.c, src/debug/debugcpu.h, + src/debug/profile.h, src/debug/profile_priv.h: + initial support for "n " + [d49fac089c39] + +2013-07-18 Eero Tamminen + + * src/debug/debug_priv.h, src/debug/debugcpu.c, src/debug/debugdsp.c, + src/debug/debugui.c, src/debug/profile.c: + use common code for readline matching + + There are places where matching is done differently, either by + matching from several arrays, or from array of structures (used also + for other things), but these use just simple string array and can + therefore use a common helper function. + + Readline matcher needs also some static variables, but it seems + enough that they're in the helper, instead of specific to each + string list. + [a06f827d3cf7] + +2013-07-18 Laurent Sallafranque + + * src/falcon/dsp_disasm.c: + dsp disasm fix : the opcode decoder must detect an illegal + instruction if the decoded opcode doesn't exist. In this case, the + disasm opcode must be displayed as "dc value" + [2572fbd7ea47] + +2013-07-18 Nicolas Pomarede + + * src/video.c: + Handle a special case when writing only in lower byte of a color reg + This case was forgotten in changeset #1546 from 16/1/2009 + [49c1585d0190] + +2013-07-17 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + dsp fix : the opcode decoder must return a illegal instruction if + the decoded opcode doesn't exist. + [3f61be7bb49e] + +2013-07-13 Thomas Huth + + * src/debug/debugInfo.c, src/debug/debugcpu.c, src/debug/debugdsp.c, + src/falcon/dsp.c, src/falcon/dsp_core.c, src/falcon/dsp_cpu.c, + src/falcon/dsp_disasm.c, src/hd6301_cpu.c, src/spec512.c, src/str.c: + Added necessary includes for compiling with emscripten + [de23b5ea9505] + + * src/includes/scandir.h, src/scandir.c: + Fixed the prototypes of alphasort and scandir + [cccee916a8d8] + +2013-07-08 Eero Tamminen + + * doc/release-notes.txt, src/debug/breakcond.c: + also "<" and ">" breakpoint conditions can store checked value + + With previous commit, this allows me to automate e.g. detecting + worst frames for Douglas' Doom port and take profiles of them. + [465fdda57a9b] + + * doc/release-notes.txt, src/debug/breakcond.c, src/debug/debugcpu.c, + src/debug/debugcpu.h, src/debug/debugdsp.c, src/debug/debugdsp.h, + tests/debugger/test-dummies.c: + Add "CpuInstr" and "DspInstr" debugger variables + + These can be used e.g. to check how many instructions emulation ran + since a breakpoint / using "next". + [bef7e9bc8cb3] + +2013-07-05 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [e8b182860a4a] + + * src/debug/debugdsp.c: + support same syntax for 'dm' as what's in DSP disassembly + + requested by Laurent. + [ca1624cf9896] + +2013-07-05 Nicolas Pomarede + + * doc/release-notes.txt: + Update release notes with fix for IACK + [d40dad0cb2ee] + + * src/cpu/newcpu.c, src/uae-cpu/newcpu.c: + During the HBL/VBL IACK, update MFP's state if needed An MFP's IRQ + happening during the IACK for HBL/VBL was not processed immediately + but delayed to the next time where PendingInterruptCount<=0 (fix + regression in top border's removal in Sommarhack 2011 Invitro by + DHS) + [2c206ff96fed] + +2013-07-04 Nicolas Pomarede + + * src/cpu/newcpu.c, src/uae-cpu/newcpu.c: + Remove debug code + [1053d9e84b86] + + * src/cpu/newcpu.c, src/uae-cpu/newcpu.c: + Cancel change #4610, wrong description, extra cycles were not added + [d7e3d88271cd] + + * src/cpu/newcpu.c, src/uae-cpu/newcpu.c: + Remove IACK cycles that were wrongly added for all exceptions, not + just interrupts This added 20 cycles to TRAP, CHK, Bus Error, ... + [11af1b202cf8] + +2013-07-02 Eero Tamminen + + * tests/debugger/test-dummies.c: + fix debugger test dummy + [e39b67886f17] + +2013-07-02 Nicolas Pomarede + + * doc/release-notes.txt: + Update release notes, clock speed was sometimes not updated in the + status bar + [1b829aac2897] + + * src/ioMemTabFalcon.c: + In Falcon mode, update the clock's speed in the status bar when + writing to $ff8007 During the boot, the TOS will set the clock speed + to 16 MHz, even if Hatari was started in 32 MHz mode. We should + update the status bar to show the new clock's speed. + [38ff82b964fd] + +2013-06-30 Nicolas Pomarede + + * CMakeLists.txt: + Update compilation flags for the OSX version to use native alert + windows + [55f10ff1a0d3] + +2013-06-27 Nicolas Pomarede + + * src/cpu/memory.c, src/uae-cpu/memory.c: + Add a note about the values returned when reading a 'void' region of + memory + [4cea40de88f9] + +2013-06-26 Nicolas Pomarede + + * doc/release-notes.txt: + Update release notes + [136440d53fbe] + + * src/video.c: + Add blank line detection in STE mode when switching 60/50 Hz at + cycles 40/52 (fix shforstv by Paulo Simoes when running in STE mode) + [1b1314d4d21f] + +2013-06-24 : *** Version 1.7.0 *** + +2013-06-24 Nicolas Pomarede + + * doc/doxygen/Doxyfile, doc/emutos.txt, doc/release-notes.txt, + doc/todo.txt, hatari.spec, readme.txt, src/gui- + osx/English.lproj/InfoPlist.strings, src/gui- + osx/French.lproj/InfoPlist.strings, src/gui-osx/Info-Hatari.plist, + src/includes/version.h, src/memorySnapShot.c: + New release 1.7.0, increase version in corresponding files + [63c1d7c59d25] [tip] + + * src/gui-osx/English.lproj/AideHatari/compatibility.html, src/gui- + osx/English.lproj/AideHatari/manual.html, src/gui- + osx/French.lproj/AideHatari/compatibility.html, src/gui- + osx/French.lproj/AideHatari/manual.html: + Update help files in OSX build + [9211d018684e] + +2013-06-24 Eero Tamminen + + * doc/compatibility.html: + 1.6.2+ -> 1.7 + [88c0f2ef958a] + + * readme.txt: + update readme version to 1.7 + add note about cmake + [0d1e4d663d5f] + + * doc/manual.html: + fix typo in manual and add space after "NOTE:" + [b8286828eea5] + +2013-06-23 Nicolas Pomarede + + * doc/manual.html: + Remove extra tag + [b821841c45c6] + + * src/gui-osx/English.lproj/SDLMain.nib/designable.nib, src/gui- + osx/English.lproj/SDLMain.nib/keyedobjects.nib, src/gui- + osx/English.lproj/SDLMain.xib, src/gui- + osx/French.lproj/SDLMain.nib/designable.nib, src/gui- + osx/French.lproj/SDLMain.nib/keyedobjects.nib: + Update xib/nib files for OSX + [ab91ed70e773] + +2013-06-22 Nicolas Pomarede + + * src/cpu/compat.h, src/cpu/newcpu.c: + Don't define variables in .h files for WinUAE cpu core Variables + should be defined only in .c, not in common .h files, else linker + will complain about multiple definitions of the same variable. + [3188b6c70ae4] + +2013-06-21 Nicolas Pomarede + + * src/gui-osx/Hatari Help Folder/.DS_Store, src/gui-osx/Hatari Help + Folder/clavier-exemple.txt, src/gui-osx/Hatari Help + Folder/compatibility.html, src/gui-osx/Hatari Help + Folder/images/devices.png, src/gui-osx/Hatari Help + Folder/images/fileselector.png, src/gui-osx/Hatari Help + Folder/images/floppydisks.png, src/gui-osx/Hatari Help + Folder/images/harddisks.png, src/gui-osx/Hatari Help + Folder/images/joystick.png, src/gui-osx/Hatari Help + Folder/images/keyboard.png, src/gui-osx/Hatari Help + Folder/images/main.png, src/gui-osx/Hatari Help + Folder/images/memory.png, src/gui-osx/Hatari Help + Folder/images/monitor.png, src/gui-osx/Hatari Help + Folder/images/newfloppy.png, src/gui-osx/Hatari Help + Folder/images/screen.png, src/gui-osx/Hatari Help + Folder/images/sound.png, src/gui-osx/Hatari Help + Folder/images/system.png, src/gui-osx/Hatari Help + Folder/images/tos.png, src/gui-osx/Hatari Help Folder/manual.html: + Remove unneeded OSX directory + [2f16dc981108] + +2013-06-20 Nicolas Pomarede + + * doc/compatibility.html, doc/manual.html: + Remove link to W3 validator in html files + [abc96cb92103] + + * src/gemdos.c: + Change conflicting variable's name for mingw When compiling the + Windows version with mingw, 'environ' is already used as a variable, + which causes an error : /usr/i586-pc-mingw32/sys- + root/mingw/include/stdlib.h:149: note: previous declaration of + '__p__environ' was here + [6711c061eede] + +2013-06-19 Nicolas Pomarede + + * src/gui-osx/English.lproj/AideHatari/compatibility.html, src/gui- + osx/English.lproj/AideHatari/manual.html, src/gui- + osx/French.lproj/AideHatari/compatibility.html, src/gui- + osx/French.lproj/AideHatari/manual.html, src/gui-osx/Hatari Help + Folder/compatibility.html, src/gui-osx/Hatari Help + Folder/manual.html: + Update help files in OSX version + [a1be6a9ceb38] + + * src/gui-osx/English.lproj/AideHatari/.DS_Store, src/gui- + osx/English.lproj/AideHatari/compatibility.html, src/gui- + osx/English.lproj/AideHatari/images/callgraph.png, src/gui- + osx/English.lproj/AideHatari/images/callgraph.svg, src/gui- + osx/English.lproj/AideHatari/images/devices.png, src/gui- + osx/English.lproj/AideHatari/images/fileselector.png, src/gui- + osx/English.lproj/AideHatari/images/floppydisks.png, src/gui- + osx/English.lproj/AideHatari/images/harddisks.png, src/gui- + osx/English.lproj/AideHatari/images/joystick.png, src/gui- + osx/English.lproj/AideHatari/images/kcachegrind.png, src/gui- + osx/English.lproj/AideHatari/images/keyboard.png, src/gui- + osx/English.lproj/AideHatari/images/main.png, src/gui- + osx/English.lproj/AideHatari/images/memory.png, src/gui- + osx/English.lproj/AideHatari/images/monitor.png, src/gui- + osx/English.lproj/AideHatari/images/newfloppy.png, src/gui- + osx/English.lproj/AideHatari/images/screen.png, src/gui- + osx/English.lproj/AideHatari/images/sound.png, src/gui- + osx/English.lproj/AideHatari/images/system.png, src/gui- + osx/English.lproj/AideHatari/images/tos.png, src/gui- + osx/English.lproj/AideHatari/manual.html, src/gui- + osx/English.lproj/SDLMain.nib/designable.nib, src/gui- + osx/English.lproj/SDLMain.nib/keyedobjects.nib, src/gui- + osx/English.lproj/SDLMain.xib, src/gui- + osx/French.lproj/AideHatari/.DS_Store, src/gui- + osx/French.lproj/AideHatari/compatibility.html, src/gui- + osx/French.lproj/AideHatari/images/callgraph.png, src/gui- + osx/French.lproj/AideHatari/images/callgraph.svg, src/gui- + osx/French.lproj/AideHatari/images/devices.png, src/gui- + osx/French.lproj/AideHatari/images/fileselector.png, src/gui- + osx/French.lproj/AideHatari/images/floppydisks.png, src/gui- + osx/French.lproj/AideHatari/images/harddisks.png, src/gui- + osx/French.lproj/AideHatari/images/joystick.png, src/gui- + osx/French.lproj/AideHatari/images/kcachegrind.png, src/gui- + osx/French.lproj/AideHatari/images/keyboard.png, src/gui- + osx/French.lproj/AideHatari/images/main.png, src/gui- + osx/French.lproj/AideHatari/images/memory.png, src/gui- + osx/French.lproj/AideHatari/images/monitor.png, src/gui- + osx/French.lproj/AideHatari/images/newfloppy.png, src/gui- + osx/French.lproj/AideHatari/images/screen.png, src/gui- + osx/French.lproj/AideHatari/images/sound.png, src/gui- + osx/French.lproj/AideHatari/images/system.png, src/gui- + osx/French.lproj/AideHatari/images/tos.png, src/gui- + osx/French.lproj/AideHatari/manual.html, src/gui- + osx/French.lproj/InfoPlist.strings, src/gui- + osx/French.lproj/Localizable.strings, src/gui- + osx/French.lproj/SDLMain.nib/designable.nib, src/gui- + osx/French.lproj/SDLMain.nib/keyedobjects.nib, src/gui- + osx/French.lproj/SDLMain.xib, src/gui-osx/Hatari Help + Folder/.DS_Store, src/gui-osx/Hatari Help Folder/clavier- + exemple.txt, src/gui-osx/Hatari Help Folder/compatibility.html, src + /gui-osx/Hatari Help Folder/images/devices.png, src/gui-osx/Hatari + Help Folder/images/fileselector.png, src/gui-osx/Hatari Help + Folder/images/floppydisks.png, src/gui-osx/Hatari Help + Folder/images/harddisks.png, src/gui-osx/Hatari Help + Folder/images/joystick.png, src/gui-osx/Hatari Help + Folder/images/keyboard.png, src/gui-osx/Hatari Help + Folder/images/main.png, src/gui-osx/Hatari Help + Folder/images/memory.png, src/gui-osx/Hatari Help + Folder/images/monitor.png, src/gui-osx/Hatari Help + Folder/images/newfloppy.png, src/gui-osx/Hatari Help + Folder/images/screen.png, src/gui-osx/Hatari Help + Folder/images/sound.png, src/gui-osx/Hatari Help + Folder/images/system.png, src/gui-osx/Hatari Help + Folder/images/tos.png, src/gui-osx/Hatari Help Folder/manual.html, + src/gui-osx/Info-Hatari.plist, src/gui-osx/PrefsController.m, src + /gui-osx/SDLMain.h, src/gui-osx/SDLMain.m, src/gui-osx/disk.icns: + Update OSX version with latest changes from Jerome Vernet + [f3c14938bfc6] + + * src/mfp.c: + MFP's int 0 was not taken into account, which broke printer's output + [6a1a8966dba0] + + * src/mfp.c: + Remove old debug printf's + [48501858737f] + +2013-06-18 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Add 'Spidertronic' to the fixed games + [2d1291155ba7] + + * doc/release-notes.txt: + Update fixed game + [c2e9be647df9] + +2013-06-17 Nicolas Pomarede + + * doc/authors.txt: + Update contributors' list + [9253dbabe414] + +2013-06-16 Eero Tamminen + + * tools/debugger/hatari_profile.py: + rename "Calls" heading + + The first column is really about how many times given symbol is + visited (e.g. by loop that starts from first instruction in a + routine), it's not about subroutine calls, which can be confusing. + + Hopefully renaming it to "Visits/calls" reminds about this. + [a261d955c2cd] + + * doc/manual.html: + usage example on exception debugging + text improvements + [6edd77f3857b] + + * doc/manual.html, doc/release-notes.txt, src/debug/debugcpu.c, + src/debug/debugdsp.c, src/debug/debugui.c, src/debug/history.c, + src/debug/history.h: + user can specify whether CPU or DSP history is tracked + + On Falcon DSP runs much more instructions than CPU, so history can + get totally swamped with DSP activity although typically it's CPU + activity user's interested about. + [ee9e5e296b63] + +2013-06-16 Nicolas Pomarede + + * src/fdc.c: + Fine tune prepare phase for FDC's type I commands This was measured + on a 520 STF by doing a 'restore' + 'seek 0' + [168537a625ed] + +2013-06-15 Eero Tamminen + + * tools/debugger/hatari_profile.py: + profiler postprocessor: fix div by zero when call count = 0 + [01487650e282] + + * doc/release-notes.txt: + better MIDI error description + [b4b83168c624] + + * doc/emutos.txt: + update emutos panic debugging notes + [19183ab522d6] + +2013-06-14 Nicolas Pomarede + + * doc/release-notes.txt: + Update notes about drives' led color + [af5517558d48] + + * src/fdc.c, src/gemdos.c, src/hdc.c, src/includes/statusbar.h, + src/psg.c, src/statusbar.c: + Use a brighter green for the drive led when the FDC is executing a + command + [40b5822ecb5d] + + * src/fdc.c, src/gemdos.c, src/hdc.c, src/includes/statusbar.h, + src/psg.c, src/statusbar.c: + Use a brighter green for the drive led when the FDC is executing a + command + [cad8414ec370] + +2013-06-13 Nicolas Pomarede + + * src/acia.c: + Remove possible gcc warning about uninitialized variable + [3d67ed3da52f] + + * src/includes/cfgopts.h, src/includes/configuration.h, + src/includes/joy.h, src/includes/m68000.h: + Remove extra ',' at the end of the enum definition (silence compiler + warnings) + [3e93cd424b75] + + * src/fdc.c: + In the FDC's status register, correctly report the state of the + index pulse signal (fix FLRPMM.PRG by P. Putnik and reports 300 RPM + for the drive speed) + [a6a58812be57] + +2013-06-12 Nicolas Pomarede + + * src/acia.c: + ACIA's RTS could be 0 after a master reset, instead of 1 (this is + harmless, as RTS is not connected on ST anyway) + [13fc5b1410fc] + + * src/acia.c, src/ikbd.c: + When the IKBD reset on cold start, don't send bytes until the ACIA's + serial line is initialized This should fixes problem with EmuTos < + 0.91 where a reset was sometimes needed to move the mouse + [4e3319ec8aa2] + +2013-06-10 Thomas Huth + + * src/dmaSnd.c, src/includes/dmaSnd.h, src/main.c: + Fixed crash that occured when compiling with ENABLE_SMALL_MEM + defined. DmaSnd_Init() called DmaSnd_Reset() which in turn accessed + IoMem before it has been initialized. Since DmaSnd_Reset() is called + during Reset_ST() anyways, the problem could easily be solved by + removing DmaSnd_Init() completely. + [669b0aa4c072] + +2013-06-09 Nicolas Pomarede + + * src/acia.c: + Default IKBD's ACIA to 9600 baud after a reset On real hardware, it + seems tx/rx are working after a reset, but the ACIA's reference doc + is not precise on this default behaviour. Some EmuTos versions + tested on a real ST need this to work under Hatari + [47e45c9937d3] + + * src/fdc.c: + typo + [1fcc83575127] + +2013-06-09 Eero Tamminen + + * doc/release-notes.txt, src/options.c: + Giving empty string as GEMDOS HD dir disables GEMDOS HD emulation + [127879ca3b0b] + +2013-06-09 Thomas Huth + + * src/bios.c, src/falcon/videl.c: + Silenced compiler warnings that occured when ENABLE_TRACING was not + defined + [3262b3f3501a] + + * src/falcon/dsp.c: + Silenced compiler warnings that occured when ENABLE_DSP_EMU was not + defined + [56b84ca73536] + +2013-06-03 Eero Tamminen + + * src/debug/debugui.c: + fix FD leak in debugger script parsing + [a15b283f83fe] + + * doc/release-notes.txt: + update release notes + [28053da8a50c] + + * src/gemdos.c: + fix args in Mshrink trace message + + - there's reserved zero word before args in C-bindings + - optimize couple of other memory related trace messages slightly + [6e11115a6199] + +2013-06-02 Eero Tamminen + + * tools/debugger/hatari_profile.py: + profile post-processor: error -> warning + + this case (caller net being boundable to any symbol) can be valid in + the very beginning of a program run, not necessarily an error + [0665979151a5] + +2013-06-01 Eero Tamminen + + * src/debug/profilecpu.c: + fix profiler PC access corner case + + On some rare cases (e.g. Hatari cartridge linea_init jump address) + PC addresses have extra bits that are masked out when emulation uses + them. Profiler needs to do same instead of complaining & asserting. + [693fa4a2a49c] + + * src/gemdos.c: + show args for rest of non-mint gemdos calls when tracing + + All (3) of these were memory allocation related functions, so now + it's possible to track memory allocated from TOS. + [42dfaec46d3f] + + * doc/release-notes.txt: + update release notes + [9649f256a4d0] + + * doc/manual.html: + document "profile stack" subcommand and ":noinit" bt option + [ac186ce8e3fe] + + * src/debug/breakcond.c, src/debug/debugInfo.c, + src/debug/debug_priv.h, src/debug/debugui.c, src/debug/debugui.h: + add "NextPC" variable and bt option that doesn't re-initialize + debugging on hit + + These are needed for getting useful information from "profile stack" + command: + --- outside Hatari --- $ cat > profile-stack.ini << EOF profile stack + b pc="NextPC" :once :quiet :noinit :file profile-d0.ini EOF $cat > + profile-d0.ini << EOF e d0 EOF + --- in Hatari debugger --- > profile on > symbols prg > b + GemdosOpcode = 0x3f :quiet :noinit :file profile-stack.ini + -------------------------- + + (shows backtraces to all Fread() calls and their return values.) + [c8cc6daa7dfc] + + * src/debug/profile.c, src/debug/profile_priv.h, + src/debug/profilecpu.c, src/debug/profiledsp.c: + add profile "stack" subcommand + + This is useful for getting backtraces during profiling. + [916df38ea409] + + * src/change.c, src/midi.c: + MIDI change triggers emu reset, MIDI IRQ disable if MIDI not enabled + + This will hopefully fix Cubase not working after enabling MIDI + during run-time. + [1d25e2cff695] + +2013-05-29 Eero Tamminen + + * readme.txt: + recommend CMake version with which we build Hatari version + + Frank reported that Hatari build doesn't succeed with CMake v2.6, + but it works with v2.8. + [98383366f85d] + + * doc/todo.txt: + add todo note about FPU precision + [fc0c02a96e62] + +2013-05-26 Eero Tamminen + + * src/gemdos.c: + fix fread return value compiler warning + [5eb9c15f48a0] + + * tests/debugger/Makefile, tests/debugger/makefile: + rename makefile + [2bd1ad275505] + + * src/debug/evaluate.c: + fix LLVM warning + [4d5b87077f7f] + +2013-05-25 Eero Tamminen + + * doc/manual.html: + document profile call stack showing and update debugger usage + examples + + (also use in usage examples section consistently 2 spaces between + command and its arguments, this will hopefully make examples + slightly more readable.) + [19b6b37b01d3] + +2013-05-24 Eero Tamminen + + * src/gemdos.c: + fix matching of host names with multiple '.' within first 8 chars + + When host names are read to DTA, extra dots before last dot are + converted to "invalid" characters ("@") in str.c. However, when + matching converted names back to host names, '*' in match glob + pattern expanded only to first dot. + + Now '*' expansion stops only at last dot. + [8c5e22f3b42e] + + * src/str.c: + fix Fsnext() 8+3 GEMDOS name clipping + + This str.c function didn't clip 9+2 file name to 8+2 like is done in + gemdos.c for other GEMDOS file functions. + [55cfaac16cc8] + +2013-05-21 Eero Tamminen + + * doc/release-notes.txt, src/gemdos.c: + fix Dfree() success return value + [3559fb7fb060] + +2013-06-09 Nicolas Pomarede + + * src/fdc.c: + Comment debug printf + [2ed15aaffcb3] + + * doc/compatibility.html, doc/release-notes.txt: + Update notes with FDC's changes + [bc70e24e8098] + + * src/fdc.c: + Add correct delay for FDC's type I commands when "verify" bit is set + Although ST/MSA disk images can't have "verify" errors, we still + need to emulate the delay it would take to settle the head and check + the next address field, else some FDC commands will run faster than + expected. (fix STNICCC by Oxygene, which was running slower than on + real HW) + [23e482740944] + +2013-06-08 Nicolas Pomarede + + * src/fdc.c: + Improve logs for FDC type I commands + [33587d9db223] + + * src/fdc.c: + Add debug printf and alternatives timings in FDC + [1f1342909218] + +2013-05-26 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + updates notes for mouse issues in Spectrum 512 and The Sentinel + [9f28de798d0a] + + * src/ikbd.c: + When mouse is in absolute mode in the IKBD, correctly apply scaling + factor to deltaX/Y (fix slow mouse in the game 'The Sentinel' and in + the painting program 'Spectrum 512') + [a7b1c237cab9] + +2013-05-24 Nicolas Pomarede + + * src/fdc.c: + After reading/writing a sector, we must also transfer 2 CRC bytes + for better timings + [72901f621820] + + * src/fdc.c: + FDC's internal timer was not correct, resulting in slower timings + DMA transfers were accumulating some extra cycles, taking more than + the expected 4096 cycles for 16 bytes (~141000 cycles to read a + sector, instead of 131072) + [98c3962a4793] + +2013-05-21 Nicolas Pomarede + + * src/fdc.c: + For Read Address and Read Track, correctly returns if no disk is + inserted + [a1106f3f4f4c] + + * src/fdc.c: + For the FDC type III Read Address command, use + FDC_NextSectorID_NbBytes() to get the correct delay Depending on the + current position in the track, this will compute the number of bytes + to skip to reach the next address field while the disk is spinning. + [4ae931cfe766] + +2013-05-20 Nicolas Pomarede + + * src/fdc.c: + For the FDC type III Read Track command, add a delay to wait for the + next index pulse + [a59c49f72f27] + + * src/fdc.c: + For the WD1772, head settling time is 15 ms, not 30 ms + [35d01b6e69bb] + + * src/fdc.c: + Add more traces for FDC's type II/III commands + [c5f634e0e04b] + + * doc/compatibility.html, doc/release-notes.txt: + Add notes for Microprose Golf + [cfbb3c045ac5] + + * src/fdc.c: + Don't do an extra test after the last DMA transfer with read/write + sector When the last 16 bytes block was transferred, we didn't + immediatly check that it was the last one, which added another 4096 + cycles loop before completing the read/write sector command ; the + command was 3% slower than expected which could mess with some + programs' timings. (fix crash during Microprose Golf's intro) + [79be95d1aed8] + + * src/fdc.c: + In the FDC, take the disk's spin into acccount to compute the + angular position of a byte in a track Depending on the current + position above the track and the next position we want to reach, we + need to add a corresponding delay to skip the bytes inbetwen (for + example, adding an extra spin if the next sector is not directly + located after the current sector) + [bdcbb40ca86f] + +2013-05-19 Nicolas Pomarede + + * src/fdc.c: + For FDC Read / Write Sector commands, add a delay to reach the data + after the ID field was read With standard formatting, there're 41 + bytes to skip to get the right timings (else we were too fast) (fix + garbage pixels after the countdown in the Decade Demo Intro) + [2344225d674f] + + * src/fdc.c: + Use some constants for the FDC's GAPs used in a track's layout + [5a0f32b723d9] + +2013-05-18 Eero Tamminen + + * tools/debugger/gst2ascii.c: + Windows doesn't support endian.h either + + (left-over from BIG_ENDIAN tests) + [fb8cb07bb6d4] + +2013-05-16 Nicolas Pomarede + + * doc/compatibility.html: + Fuzion CD 161's intro doesn't work on a real STF + [04496807357c] + +2013-05-16 Eero Tamminen + + * tools/debugger/gst2ascii.c: + Windows doesn't support POSIX headers, revert part of previous + commit + + Add dummy defines for MiNTlib builds instead (all machines on which + they run, should be big-endian). + [43cdd6471ec8] + +2013-05-16 Nicolas Pomarede + + * src/includes/mfp.h, src/mfp.c: + Remove old unused test code to improve MFP's interrupt processing + [032e36117b46] + +2013-05-15 Eero Tamminen + + * doc/release-notes.txt, src/debug/debugui.h, src/falcon/dsp_cpu.c: + Also undefined/illegal DSP instructions & stack under/overflow + invoke debugger with -D + [9b76d896bef4] + +2013-05-13 Eero Tamminen + + * doc/release-notes.txt, src/gemdos.c: + if host returns invalid datetime, use default one instead of + returning GEMDOS error + + - This is Windows specific problem. Its localtime() doesn't support + all timestamps returned by stat() calls. Error return caused TOS + to ignore files with such dates, and all the following files (e.g. + Fsnext()). + - 1980-01-01 is used as the default date, it's earliest one supported + by TOS. + [1a53619931fb] + +2013-05-11 Eero Tamminen + + * doc/manual.html: + improve profiler doc a bit + [2a1d59da0849] + +2013-05-10 Eero Tamminen + + * src/debug/profiledsp.c: + profiler: one of the DSP JSSET instruction opcodes was incorrect + + Incorrect opcode matched JSET i.e. several things that were marked + as subroutine calls were actually (conditional) branches. + [d5ce6fd49b41] + +2013-05-08 Nicolas Pomarede + + * src/mfp.c: + More consistent naming for MFP's vector number + [51b0f42111bd] + + * src/cpu/newcpu.c, src/includes/video.h, src/uae-cpu/newcpu.c, + src/video.c: + Remove old unused code to handle simultaneous HBL exceptions + [75c38879ba4f] + +2013-05-07 Eero Tamminen + + * src/debug/breakcond.c: + fix: newline missing from breakpoint trace output + [73176379c2f7] + +2013-05-06 Eero Tamminen + + * doc/emutos.txt: + emutos compat update + [574114cab1ae] + +2013-05-05 Eero Tamminen + + * doc/todo.txt: + add todo for GST parsing + + (which I may not have time to fix before release) + [76e50d3a9367] + + * doc/manual.html: + manual updates + + - update version to 1.7 as manual mentions lot of things not in + 1.6.2 yet + - add another note for gst2ascii + - fix HTML validator issues + [a60c12ea30d3] + + * doc/images/callgraph.png, doc/images/callgraph.svg, + doc/images/kcachegrind.png, doc/manual.html, + tools/debugger/hatari_profile.py: + document callgrind generation + notes on profiler accuracy + + Also: + - add some example images + - remove some duplicate info from post-processor usage output + [bee121a75114] + + * tools/debugger/hatari_profile.py: + indicate costs with potentially missing symbols, reduce name lenght + + - if inclusive cost is < in-between-symbols cost, there may be + symbols missing + - don't give so much space for symbol names. DRI/GST limits name + len to 22, use something similar + [4904c232755b] + +2013-05-04 Eero Tamminen + + * src/debug/profile.c, src/debug/profilecpu.c: + fix corner case issue mentioned in previous commit + [14b4574e222b] + + * tools/debugger/hatari_profile.py: + fix couple of post-processing corner cases + better messages + + - owncounts can be zero although totalcounts aren't + - it's easy to get error if symbols don't from some reason match + (e.g. because you re-compiled binary without re-generating + symbols), error message now comments about this. + [12ce06b00b0e] + + * src/debug/profilecpu.c: + improve debugging of wierd profile PC values + + For some reason profiling (BadMood) CPU & DSP while creating and + removing breakpoints causes in one case IO address $ffffff accesses. + They don't happen without profiling&breakpoints. Valgrind, mudflap + & Duma don't find any problems, so this is still a mystery. :-/ + [fff12307d134] + + * src/debug/profile.c: + fix CPU profiling corner case assert + + Case was with first (or second?) profiled instruction being tracked + function entry point, which therefore gets undefined return address. + Cost finalization at profile end asserts on unrecognized addresses. + [96d1097307f7] + + * tools/debugger/gst2ascii.c: + update also gst2ascii message + [b99a15708773] + + * tools/debugger/gst2ascii.c: + -o option ignores also useless GCC v2 symbols + [62cfaa95ec53] + + * tools/debugger/gst2ascii.c: + use standard C headers & types instead of SDL ones + + This way gst2ascii can be easily built also for Atari with MiNTlib. + [b2e5f43589d1] + +2013-05-03 Eero Tamminen + + * doc/compatibility.html: + update zero-5 note + [a28b0fef6beb] + +2013-05-03 Nicolas Pomarede + + * doc/release-notes.txt: + Update releases note for CPU's IACK + [23d6a98e44fc] + + * src/cpu/hatari-glue.c, src/cpu/newcpu.c, src/includes/m68000.h, src + /uae-cpu/hatari-glue.c, src/uae-cpu/newcpu.c, src/video.c: + Handle IACK for simultaneous HBL/VBL exceptions This removes some + previous uncomplete/wrong support for this and correctly handles + Super Monaco GP, Super Hang On, Monster Business, European Demo's + Intro, BBC Menu 52. + [bc11f8639f03] + +2013-04-30 Nicolas Pomarede + + * src/cpu/newcpu.c, src/includes/m68000.h, src/m68000.c, src/mfp.c, + src/uae-cpu/newcpu.c: + Use the more generic variable CPU_IACK instead of MFP_IACK + [c1ed5f55f85a] + +2013-04-28 Nicolas Pomarede + + * src/video.c: + Change debug printf + [2fdf9586b877] + +2013-04-26 Nicolas Pomarede + + * doc/compatibility.html: + Update notes for 'Musical Wonders 1990' demo + [6fd24bc14db5] + + * src/video.c: + Cancel changes #3902, 'Musical Wonders 1990' doesn't work correctly + on a real STF + [a95880358570] + +2013-04-24 Nicolas Pomarede + + * src/acia.c, src/cycInt.c, src/includes/acia.h, + src/includes/cycInt.h: + Don't use an additional 4 cycle timer in the ACIA, this is now + automatically handled in mfp.c + [4c26e8526d44] + + * src/cpu/newcpu.c, src/uae-cpu/newcpu.c: + Remove old/unused interrupt code + [16cc224edc98] + +2013-04-23 Nicolas Pomarede + + * src/uae-cpu/newcpu.c: + RTE is $4e73, not $4e72 + [586d90231775] + +2013-04-22 Eero Tamminen + + * tools/debugger/hatari_profile.py: + 10 digits for larger counts + [e182fef31c33] + +2013-04-21 Nicolas Pomarede + + * doc/release-notes.txt: + Update notes with latest MFP changes + [fd59ad8d46b7] + + * src/cpu/newcpu.c, src/includes/mfp.h, src/mfp.c, src/uae- + cpu/newcpu.c: + In the MFP, handle multiple interrupts in chronological order during + a single CPU instruction + [e882662b6c90] + +2013-04-22 Eero Tamminen + + * tools/debugger/hatari_profile.py: + more info on -i & -p profile post-processor options + + -i: show also total time for cycles and per call instructions & time + -p: show both inclusive & exclusive costs, and both percentage & + counts for them (only inclusive for calls, as for those + exclusive values are always same as default counts) + [3249112c7143] + +2013-04-19 Eero Tamminen + + * src/debug/symbols.c, tools/debugger/gst2ascii.c: + ignore global equated define types on GST symbol import + [4ece37d8e8a4] + + * src/debug/symbols.c: + it's enough to do fclose once (earlier) + [2ee6667b05fc] + + * tools/debugger/CMakeLists.txt: + build & install gst2acii + [1f95b924d24c] + + * doc/release-notes.txt, tools/debugger/gst2ascii.1, + tools/debugger/gst2ascii.c, tools/debugger/hatari_profile.1: + add gst2ascii tool + + This can output DRI/GST format symbol table from Atari program in + ASCII format which is understood by the profile data post-processor + (and Hatari debugger 'symbols' command in case you want to modify + the symbol information before giving it to the debugger). + [8efb89d152f4] + +2013-04-17 Eero Tamminen + + * src/xbios.c: + trace support for vsetscreen + + i.e. same as setscreen, just with extra arg + [9d3d518db356] + +2013-04-16 Eero Tamminen + + * src/debug/symbols.c: + improve messages + remove error msg about GCC _etext symbol (TEXT + symbol which is just outside of TEXT section) + [ef5a9eb1248e] + + * src/debug/symbols.c: + ignore also symbols with normal object file names + [9fcc967c3568] + + * src/debug/symbols.c: + fix executable type messages on symbol loading + [8c9fc52bed0c] + + * src/debug/symbols.c: + ignore object file names with paths + [8bf0cc6df06f] + + * src/debug/symbols.c: + fix GST long name detection + [d688f5ff0eae] + + * src/debug/symbols.c: + ignore .L* local symbols in DRI/GST table as useless + + GCC can put tens of thousands of them into symbol table which can + result in thousands of name conflicts.. + [6c5c2fe89d00] + +2013-04-16 Thomas Huth + + * src/file.c: + Fixed problem with latest zlib version (gzeof is only set when using + gzread) + [f6b563b9b44f] + +2013-04-16 Eero Tamminen + + * tools/CMakeLists.txt, tools/debugger/CMakeLists.txt: + CMake stuff to install profiler post-processor + [b7fd854a9a04] + + * tools/debugger/hatari_profile.1: + add basic manual page for profiler post-processor + [a62022268410] + +2013-04-15 Eero Tamminen + + * tools/ahcc-symbols-convert.sh, tools/debugger/ahcc-symbols- + convert.sh: + move also ahcc script + [87ca47dfe841] + + * tools/debugger/devpac3-symbols-convert.sh, tools/debugger/dsp-lod- + symbols-convert.sh, tools/debugger/hatari_profile.py, tools/debugger + /nm-symbols-cleanup.sh, tools/devpac3-symbols-convert.sh, tools/dsp- + lod-symbols-convert.sh, tools/hatari-profile.py, tools/nm-symbols- + cleanup.sh: + move debugger scripts to their own directory under tools/ + + also rename hatari-profile.py to hatari_profile.py, pylink complains + about that (as files with dashes in them cannot be imported). + [60c50326f40e] + + * tools/hatari-profile.py: + fix pylint warning for profile post-processor + [694f5518e8cf] + + * doc/manual.html: + manual: update profiler section + other minor updates + [90d0aee12a64] + + * src/debug/profilecpu.c, src/debug/profiledsp.c: + right align percentages in profile list outputs + [1041944ccd9b] + + * doc/manual.html: + update debugger section + + subsections: + - symbols + - breakpoints + - tracing + + (profiling still needs to be updated.) + [8697b194f679] + +2013-04-14 Nicolas Pomarede + + * src/mfp.c: + Update debug traces + [3bdaa5bc0ce8] + +2013-04-13 Nicolas Pomarede + + * doc/release-notes.txt: + Add 'Atomix' to the list of fixed games + [85fd918bbfb3] + +2013-04-13 Thomas Huth + + * src/debug/profiledsp.c, src/falcon/dsp_disasm.c: + Silenced compiler warnings about bad format strings for 64-bit + values + [ac1b3f50e777] + + * src/cpu/falcon_cycle030.h, src/debug/debugui.c, src/debug/profile.c, + src/debug/symbols.c, src/falcon/dsp_core.c, src/falcon/dsp_core.h, + src/falcon/dsp_cpu.c, src/falcon/microphone.c, src/falcon/nvram.c, + src/gemdos.c, src/gui-sdl/dlgFileSelect.c, src/gui-sdl/dlgSystem.c, + src/gui-sdl/sdlgui.c, src/includes/m68000.h, src/includes/unzip.h, + src/uae-cpu/newcpu.c: + Fixed more typos (discovered with the codespell utility) + [fe1b43592c8f] + +2013-04-12 Eero Tamminen + + * doc/release-notes.txt, src/blitter.c, src/debug/debugInfo.c, + src/includes/blitter.h: + add "blitter" subcommand to debugger "info" command + [cd966a53283e] + + * doc/release-notes.txt, src/debug/breakcond.c: + fix: tracking breakpoints didn't work with other conditions + + Earlier tracking breakpoint comparison value was updated only if + whole breakpoint matched. This meant that they didn't work + correctly (or at all) when coupled with other breakpoints. + + Now tracking breakpoint values are updated whenever the tracked + value changes which means that they will now work also when coupled + with other breakpoint conditions. + + HOWEVER: because breakpoint condition evaluation is optimized with + short-circuiting (similarly to conditions in C with '&&', skipping + rest of checks if something doesn't match), tracking condition needs + to be given before other conditions and you can still have only one + such condition per breakpoint. + [40a67f5fa58b] + + * tests/debugger/makefile, tests/debugger/test-dummies.c: + update debugger test dummies + [bb6fcbd34d22] + + * doc/todo.txt: + add note about VIDEL reg handling to todo.txt + [c9d34bcfb572] + +2013-04-12 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Update notes + [e80c0062adb2] + + * src/mfp.c: + Typo + [df87ba37393c] + +2013-04-11 Nicolas Pomarede + + * src/cpu/newcpu.c, src/includes/mfp.h, src/mfp.c, src/uae- + cpu/newcpu.c: + Handle MFP's changes during an ongoing exception before the IACK + (fix Anomaly Demo Menu by Oxygene and sample intro in the game The + Final Conflict) + [87276b828e07] + +2013-04-10 Eero Tamminen + + * tools/hatari-profile.py: + silence post-processor warning + [0227a8a7dd35] + + * tools/hatari-profile.py: + improve profiler data post-processor callgraph options + + These make the graph options behave in more expected way: + * nodes connected to ones specified for --ignore option are relinked + * emphasis limit isn't affected by count option + * --only-subroutines option removes all nodes that aren't called as + subroutines, regardless of their cost + * improve --compact option documentation + [563f336ae028] + + * src/debug/profile.c, src/debug/profile_priv.h, + src/debug/profilecpu.c, src/debug/profiledsp.c: + Fix caller address for symbol called right after subroutine call + + foo: jsr -> bar: <- rts + + Logically this should be indicated as "bar" symbol following the + preceeding instruction, not "foo"s return instruction calling it, + like was the case before. + [6fe99fd4aeb9] + + * tools/hatari-profile.py: + profile post-processor: handle PC_UNDEFINED, add --only-subroutines + option + + * Use caller->callee call type to add some type identification for + the called symbol/function. Use that info to: + + - Handle PC_UNDEFINED introduced by previous patch, and mark such + node(s) in callgraphs separately, as it implies it being the first + symbol called during profiling. + + - Add preliminary --only-subroutines option that leaves to + callgraph only symbols that either are called as subroutines, or + which costs exceed the given limit. + [0ff09731c197] + + * src/debug/profile.c, src/debug/profile_priv.h, + src/debug/profilecpu.c, src/debug/profiledsp.c: + fix several corner case issues in caller info collecting + + * Use impossible PC value as default (PC_UNDEFINED), so that + uninitialized PC values can be detected (previously they were + initialized to zero). + + These caused warnings output by "profile callers" command and errors + with profile post-processing script, for some very specific + profiles: + + * Caller information was collected for current PC instruction, + profiling data for previous PC instruction, this caused small + mismatch in the data. + -> Change caller info also to be about the previous instruction. + + * Function's own costs were wrong (subroutine call instruction + cost isn't assigned for the caller). + -> Total statistics used for calculating caller totals are now + updated after caller info is processed, not before. + + * DSP code didn't check for new subroutine call if another call + returned on that same address (unlike CPU side did). + -> This is now fixed. + [8ef24f412a22] + +2013-04-09 Eero Tamminen + + * src/debug/profiledsp.c: + Fix DSP caller info call type for conditional subroutine calls + + This uses heuristic that if previous instruction was conditional + subroutine call, condition failed and there was no subroutine call, + just normal advancement to next PC address. It should be safe + assumption for most of the cases. + [82f8df0b1b54] + +2013-04-07 Eero Tamminen + + * src/debug/profile.c, src/debug/profilecpu.c, src/debug/profiledsp.c: + use C99 inttypes.h macros to fix printfs with Uint64 values + [cfad9b1735c5] + + * src/debug/symbols.c, src/gemdos.c: + get rid of "fread() return value ignored" warnings + [e5b14c7d3f78] + + * tools/devpac3-symbols-convert.sh: + fix: devpac listing symbol lines have different format for GST + binaries + [525e447db18a] + + * doc/emutos.txt: + add new demo to emutos.txt + [60b272f42895] + +2013-04-06 Thomas Huth + + * src/gui-sdl/CMakeLists.txt: + Use -Wno-write-strings for GCC only + [979a828622f1] + + * src/debug/68kDisass.c, src/falcon/videl.c, src/hdc.c, src/xbios.c: + Variables must be defined at the beginning of a block + [cccc482cfce2] + +2013-04-05 Nicolas Pomarede + + * src/cpu/newcpu.c: + Process interrupts and STOP instruction in the same way as in uae- + cpu/newcpu.c + [8a2f641ef512] + +2013-04-04 Eero Tamminen + + * src/debug/symbols.c: + one more sanity check for making sure program in RAM & file match + [95dd03950e60] + +2013-04-04 Nicolas Pomarede + + * src/uae-cpu/newcpu.c: + With new mfp.c and delayed IRQ, update interrupt processing during a + STOP (fix stop 2500 in Sowatt - Sync screen) + [f75e9f752397] + + * src/mfp.c: + Update debug traces + [1b8ecf003999] + +2013-04-04 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [deaba12c1406] + + * src/debug/symbols.c, src/gemdos.c, src/includes/gemdos.h: + add debugger "symbols" "prg" subcommand to load symbols from last + program + + This requires also GEMDOS HD emulation to be patched, to store what + it thinks to be the last started program. + [cc818b771cdc] + + * src/debug/symbols.c: + minor fixes to error cases in previous 2 commits + [e4254bcc7c50] + + * src/debug/symbols.c: + check and ignore symbols that go outside of their sections + [1046fcbc917e] + + * src/debug/symbols.c: + add support for reading DRI/GST symbols from programs + [b88fa69544c4] + +2013-04-03 Eero Tamminen + + * doc/release-notes.txt, src/debug/68kDisass.c, + src/debug/profilecpu.c: + Profiler top instruction count/cycles/misses lists show the related + instructions + [5ed803739011] + + * tools/hatari-profile.py: + change -p option to use Hatari provided total costs instead of + estimating them + + Unlike the new Hatari provided subroutine call costs, the estimated + costs were just estimates, and could be completely wrong, that's why + this is changed. + + The patch is messier than I would like, besause besides: + - adding support for actually using the new Hatari information (that + was parsed already by previous commit(s)) + - removing code for estimated cost propagation + - removing kcachegrind call info for nodes that don't have (anymore) + total costs + - documenting the new -p option + - updating comments + + it also does some other changes: + - class method and member name changes: + - propagate -> subcost + - total -> subtotal + - data/value -> cost + - add "str" postfix to local variable names that are in other + methods used for integers/tuples instead of strings + - add "bold" attribute to callgraph nodes & arrows for things that + are over the given limit + - couple of minor, unrelated doc updates + + (they were too intermixed with the other changes.) + [defe703dab23] + +2013-04-02 Eero Tamminen + + * src/debug/profile.c: + improved profiler warning messages + [f28325deae84] + + * src/debug/profilecpu.c, src/debug/profiledsp.c: + fix to profiler subroutine call return address handling + + return address can be address for another function/symbol, so return + addresses and entering a symbol address need to be checked + separately. + + (or at least return address should be checked first if one doesn't + care about missing "next" type of "call" to an address.) + [432641afa5ac] + + * src/debug/68kDisass.c: + profile data overrides asm comments + + parsing the profile data can fail if disassembly has "random" + comment strings in it, so comments should appear only when there's + no profile data + [9bda2cb44e4a] + +2013-04-01 Nicolas Pomarede + + * doc/release-notes.txt: + Update notes on joystick's axes detection bug + [cf9058ad4689] + + * src/joy.c: + Use the correct index, fix bad bug in the joystick's + detection/mapping code Joystick certainly failed for a lot of people + before because of that ... + [bbf8825e680f] + + * src/dmaSnd.c: + Typo in comment + [df235ab97bce] + +2013-03-27 Eero Tamminen + + * doc/release-notes.txt, src/gemdos.c: + Fix: cut file and dir names to 8+3 chars like all TOS versions do + [caa6d6c99cb4] + +2013-03-26 Eero Tamminen + + * python-ui/TODO: + update python ui TODOs + [da6a4fbb78f6] + + * python-ui/dialogs.py: + update python ui trace list + [b27043d2b1e3] + +2013-03-20 Eero Tamminen + + * src/debug/profile.c: + profile call counts were off by one / function, more info on call + stack contents + [23071411337b] + + * src/debug/profile.c, src/debug/profile_priv.h, + src/debug/profilecpu.c, src/debug/profiledsp.c: + call cost tracking fixes and improvements + + - calculate costs also for functions that hadn't returned yet at + the end of the profiling + - RTE on JSR return address means same as RTS, it's return from + interrupt that happened during instruction at return address + - add special hack for EmuTOS AES task switcher (it messes profiler + call tracking with its stack return address manipulation) + - better variable name: runcosts -> totalcost + - add more documentation / comments + [833b8c7dbe51] + + * src/debug/symbols.c, src/debug/symbols.h: + use Uint32 both in CPU & DSP symbol functions so that their + signatures are same + + I.e. pointers to them can be passed as args to common functions. + [84cdc03d5bbe] + +2013-03-20 Nicolas Pomarede + + * doc/compatibility.html: + Small changes to compat list + - Devpac, not DevPac (too much time spent coding with, name must be + preserved :) ) + - Hextracker requires Hatari 1.5 for proper STE DMA sound + [dba71bf49266] + +2013-03-19 Eero Tamminen + + * src/debug/profile.c, src/debug/profile_priv.h, + src/debug/profilecpu.c, src/debug/profiledsp.c: + speed up subroutine cost calculations & checks + + By moving some of the checks from generic code to CPU/DSP code, some + heavier operations need to be done less frequently. + + With this, frameskip went with DSP emulation caller profiling below + max value on my machine (Intel i3). + [cf9741d79062] + + * src/debug/profiledsp.c: + clearer to re-calculate all counters when one of them needs to be + anyway + + (in this part of code this isn't relevant for performance.) + [de98338e94f6] + + * src/debug/profile.c: + minor fixes to profile output + + - when call type info is missing, no letters are output + - address can be zero at least for DSP, so check call count instead + [7246fc9d7051] + + * src/debug/profiledsp.c: + add initial DSP call type identification support + [af2283311280] + +2013-03-18 Eero Tamminen + + * src/debug/profilecpu.c, src/debug/profiledsp.c: + 3 small fixes to previous commit + + bugs introduced in refactoring... + [c336876e19a1] + + * src/debug/profile.c, src/debug/profile_priv.h, + src/debug/profilecpu.c, src/debug/profiledsp.c, tools/hatari- + profile.py: + initial profiler support for getting full costs for subroutine calls + + includes: + - common code for collecting, processing and outputting the data + about the full costs + - full CPU side support + - related structure changes in DSP code + - some extra refactoring to improve code CPU/DSP profiling code + - post-processor support for parsing the new data and storing it + internally + + missing: + - DSP side code (opcode classification) needed for getting the full + costs + - post-processor actually using the new data + - testing the new data correctness + [eac31396971b] + +2013-03-18 Thomas Huth + + * src/cart.c: + Do not use cartridge with TOS 0.00 + [ca7febbe6b72] + +2013-03-18 Eero Tamminen + + * doc/compatibility.html: + add puet.net links for trackers + [0d3d1effa4f9] + + * doc/compatibility.html: + add Devpac 3 and Hextracker notes to compatibility list + [d274a54ebb37] + +2013-03-17 Eero Tamminen + + * tools/hatari-profile.py: + show different call types with different arrows in callgraphs + [8d8ea115e4cf] + + * src/debug/profile.c, src/debug/profile_priv.h, + src/debug/profilecpu.c, src/debug/profiledsp.c, src/debug/symbols.c, + src/debug/symbols.h: + remove unnecessary unsigned usage in profiler + + Some of the unsigned usage in profiler was redundant and required + few extra casts. + + (Usage of signed in loop counters may also allow some extra + optimizations by compiler.) + [7f24d5e6e7f9] + + * src/debug/profile.c, src/debug/profile_priv.h, + src/debug/profilecpu.c, src/debug/profiledsp.c: + fix OpcodeFamily use + small optimization + + LastOpcodeFamily variable is set only by 68000 instruction pairing + code and that isn't called by WinUE 030 core. OpcodeFamily variable + already contains last instruction's family when profiler is called, + so that can be used instead. + + Doing the symbol index checks direcly in profiler CPU/DSP update + function avoids running some extra code for most instructions (as + symbols should match only to relatively few instructions). + [89266f5f9a98] + +2013-03-17 Nicolas Pomarede + + * src/dmaSnd.c, src/sound.c: + Avoid overflow when mixing STE DMA sound and YM2149 in some cases + (patch by David Savinkoff) + [b701e19484ce] + +2013-03-16 Nicolas Pomarede + + * doc/release-notes.txt: + Change wording on IKBD's clock + [d65baa8a7686] + +2013-03-15 Eero Tamminen + + * src/debug/profilecpu.c: + Use OpcodeFamily(Last) in evaluating last instruction for profile + + (Now that also WinUAE CPU core updates it) + + Additionally this moves DEBUG checks to be after profile information + is updated, so that the added disassembly call will show up to date + information. + [df9c46d6eeba] + + * src/cpu/gencpu.c: + set OpcodeFamily also for the WinUAE CPU core + [8b344d863ff3] + + * doc/emutos.txt: + ramses will never work with emutos + [07185874b9cb] + + * doc/emutos.txt: + compatibility updates for latest EmuTOS snapshot + [7c8501b67e68] + + * doc/manual.html, doc/release-notes.txt, src/gemdos.c: + implement Fforce() and open file handle closing on Pterm*() + + Saving current program basepage address to opened file handles, + removing handles that have current program basepage when the program + exits, and checking that Fforced handle basepage either matches + current program or one of its parents should make Fforce() safe + enough. + + If process crashes without GEMDOS emu noticing and removing + Fforcing, the basebase check should catch that, so that stale forced + handle can be removed. + + Process crash can still leak internal handles, but that problem is + now *much* smaller than it was with previous code. + + Patch has also few -> ARRAYSIZE(array) changes for + consistency reasons. + [02a9995a2e57] + + * src/debug/profilecpu.c: + correct cycles values & Disasm FILE* pointer + + According to Nicolas, cycles are 8Mhz based, so for higher machines + they need to be scaled to give correct values. + [4ee9ea5ccf51] + +2013-03-14 Eero Tamminen + + * src/debug/CMakeLists.txt, src/debug/profile.c, src/debug/profile.h, + src/debug/profile_priv.h, src/debug/profilecpu.c, + src/debug/profiledsp.c: + split CPU and DSP profiling code from profile.c + + CPU and DSP profiling code has diverged and grown so much that it's + better to split them to separate files. Except for splitup, there + are no other changes. + [19ec8bd1f280] + + * doc/release-notes.txt: + update release notes + [8a94c074fc01] + + * doc/manual.html: + note additional GEMDOS emu limitations in manual + [93fe01d77a47] + + * src/gemdos.c: + give warnings on GEMDOS emu unimplemented features + + Unlike in real TOS: + - Fforce() isn't implemented (code comment explains why) + - Files opened by a program aren't implicitly closed on program + termination (as emu doesn't know which of the currently open files + belong to which of the resident programs) + [1c285132d2ac] + + * src/gemdos.c: + GEMDOS handle validation changes to help Fforce() implementation + + Validation changes also slightly reduced code duplication. + + Couple of other (trivial) changes in patch: + - more uniform white-space use + - use TOS handle ID also in "info gemdos" output + [e729944325e8] + +2013-03-14 Nicolas Pomarede + + * src/mfp.c: + When writing to the MFP's registers, take the write cycles into + acccount (properly fix Super Hang On) + [cc247cb8acf4] + + * src/cycles.c, src/includes/cycles.h: + Move Read/Write access cycles in separate functions and use them + with CyclesGlobalClockCounter too (backport from another 2012/08 dev + branch) + [9f57cdf8c0eb] + +2013-03-13 Eero Tamminen + + * src/gemdos.c: + whitespace fixes/consistency + [30de442830c5] + + * src/gemdos.c: + show TOS file handle on trace, not internal handle index + + + some white space & comment location fixes + [b9b746ca34c9] + + * src/includes/stMemory.h, src/stMemory.c: + make STMemory_Clear() static as it's used only in stMemory.c + [9c1e22f519ab] + + * tools/hatari-profile.py: + propagated call costs are estimated too, if they had multiple + callees + [3081026c95c5] + + * tools/hatari-profile.py: + initial callgrind/kcachegrind file format output support + [d32951f4a4bf] + +2013-03-12 Eero Tamminen + + * tools/hatari-profile.py: + separate title line for --no-limited removed nodes + [354266654003] + + * src/gemdos.c: + flush gemdos writes + + (Assumed fix to Douglas Devpac compilation issue.) + + Real TOS is unlikely to buffer the writes, so opening the same file + without closing earlier handle to it, may result getting data from + the new file handle that is out of date (not written out yet by host + C-library). + [ec09c54fd25b] + +2013-03-10 Thomas Huth + + * src/falcon/crossbar.c, src/falcon/crossbar.h, src/ioMemTabFalcon.c: + Fixed FF893A (attenuation) register - its size is word, not byte + [81bb536bac58] + + * src/uae-cpu/newcpu.c: + Silenced compiler warning + [1848e6b45e19] + + * src/stMemory.c: + Fixed indentation + [e4636ea7a925] + + * src/xbios.c: + Fixed trace format string for Devconnect + [d0738105d84c] + +2013-03-10 Eero Tamminen + + * tools/hatari-profile.py: + add --mark and --no-limited callgraph options + + These are helpers for really large graphs + * With --mark one can specify substrings for node names which should + be separately highhlighted in graph. This is useful when you're + interested in something that's below normal highlight limit + * With --no-limited, all nodes below limit are removed from graph. + This is something one could try if using "--compact --no-leafs + --no-intermediate" still leaves too many nodes to the graph for it + to be readable + [19ac64897554] + + * src/debug/profile.c, tools/hatari-profile.py: + add some emulator info to profile data and show it by post-processor + [17ae7390c3ff] + + * src/avi_record.c, src/debug/natfeats.c, src/gui-sdl/dlgAbout.c, + src/includes/main.h, src/includes/version.h, src/main.c, + src/options.c: + fix PROG_NAME and move it to new version.h header + [2ffdc3786b34] + + * tools/hatari-profile.py: + callgraph fine-tuning + + - show also node's own cost if main one is estimated from cost- + propagation + - use red arrow only when called function has significant costs, not + if only the caller has + [0cbc9ee49dad] + +2013-03-08 Eero Tamminen + + * tools/hatari-profile.py: + fix typo + [f4dd4b7c6496] + + * tools/hatari-profile.py: + callgraph improvements: + + * --no-leafs removes now also nodes that don't have any + connections (if they are below limit) + * fix: show nodes that don't have any connections (unless --no-leafs + is used) + * --no-leafs and --no-intermediate check that node isn't referring + to itself, such references are ignored when considering whether + node should be removed + * added (textual) information about limits and filtering to the + callgraph + [7a1e67e0c51b] + + * tools/hatari-profile.py: + callgraph improvements: + + - remove nodes with --no-leafs & --no-intermediate options only if + their percentage of total is below given limit + - update documentation accordingly + hopefully make it slightly + clearer + - improve warnings & callgraph title + [f78954043af6] + + * tools/hatari-profile.py: + fix: show arrows for all calls from given location + + Even if the same instruction jumped to different addresses, only one + of them was indicated with an arrow in the callgraph. + [ba140c684341] + + * tools/hatari-profile.py: + report profile line numbers as starting from 1 + [78eef1b65609] + +2013-03-07 Eero Tamminen + + * src/debug/profile.c, tools/hatari-profile.py: + move field names & regexps from post-processor to profiler + + Profiler code outputs the profile data and therefore knows better + what are the fields and how to parse them from disassembly, than the + post-processor. + + Moving them and removing the setup dict from post-processor required + "hard-coding" remaining two things in that dict to appropriate + classes: + - name for program code memory area (PROGRAM_TEXT) + - cycles field position (after instructions) (it didn't anymore make + sense to keep the subclass/dict) + [a7df48cae159] + + * tools/hatari-profile.py: + improve profile post-processor documentation + [056a18107821] + + * doc/todo.txt, src/includes/vdi.h, src/vdi.c: + Fix: text size setting in VDI mode + + This was broken for ST/STE 2-plane mode by previous VDI code change. + + Now screen height is always aligned to 16 pixels (largest possible + TOS font height) and screen related TOS variables are set based on + font height calculated by TOS itself, on not font height forced by + Hatari. + [101056dea3d4] + + * tests/tosboot/readme.txt: + update tos boot tester readme for the last changes + [df02965f158f] + +2013-03-05 Eero Tamminen + + * src/debug/profile.c: + avoid profiler warning on save + [47e8851e3b1c] + + * tools/hatari-profile.py: + override parsed symbols with given symbols with caller info + + Hatari debugger and profiler post-processor parse symbols a bit + differently. Post-processor has better rules for this, so if + resolved caller name differs from one parsed from the file output by + profiler, override it with post-processor one. + [b0945df83c63] + +2013-03-10 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt, src/mfp.c: + Update releases notes and comments + [6e9e7bea1c86] + + * src/includes/mfp.h, src/mfp.c, src/video.c: + Take PendingCycles into account when calling + MFP_TimerB_EventCount_Interrupt (fix bottom border removal in Decade + Demo - Reset part, flickering rasters in High Fidelity Dreams by + Aura) + [19d7efbbb8af] + + * src/mfp.c: + Better sub-instruction's cycles handling in MFP_UpdateIRQ and + MFP_ProcessIRQ + [712875d548e8] + + * src/cycles.c, src/includes/cycles.h: + CyclesGlobalClockCounter should be Uint64, not Sint64 + [c7fc5aafdb3f] + + * src/acia.c, src/blitter.c, src/dmaSnd.c, src/falcon/crossbar.c, + src/fdc.c, src/ide.c, src/includes/mfp.h, src/mfp.c, src/midi.c, + src/psg.c, src/rs232.c: + Simplify MFP_InputOnChannel() to pass only the interrupt number and + the delayed cyles The caller should not have to know which + bits/registers are involved in the MFP when an MFP interrupt happens + [e68b379022ff] + + * src/mfp.c: + Add MFP_ConvertIntNumber() to avoid duplicating some code + [bb358470c19d] + + * src/includes/mfp.h, src/mfp.c: + Rename the MFP's interrupt sources from MFP_EXCEPT_xxx to + MFP_INT_xxx + [7d9d7c2250a5] + + * src/cycles.c, src/includes/cycles.h, src/includes/m68000.h: + Add a global counter to count cpu cycles and act as a master clock + [7e8da8bb4cac] + +2013-03-06 Nicolas Pomarede + + * src/includes/video.h, src/video.c: + Change TIMERB_VIDEO_CYCLE_OFFSET to 24 cycles (due to 4 cycle delay + in MFP's IRQ) + [3e1eb42dc599] + +2013-03-05 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Update release notes and compatibility with recent MFP changes + [f1f2ad74b259] + +2013-03-04 Eero Tamminen + + * tools/hatari-profile.py: + change --ignore-to, add --compact & --no-calls, fix --no- + leafs/-intermediate options + + * --ignore-to option acts now when internal callgraph information is + constructed and it will remove calls to given nodes completely i.e. + it affects function call counts and therefore cost propagation. + This is to avoid mis-assigning interrupt handler costs (declaring + them is the purpose of this option) + + * --no-calls option allows specifying which *types* of calls + are ignored. By default calls of unknown and exception return + type are ignored as call when constructing callgraph information. + This is based on the new flags profiler adds to the caller + information, and intended to give more readable graphs by default, + with less need for use of --ignore-to option. + + * --compact option will show just one arrow between same nodes, + regarless of from how many places in the caller the callee is + called from. + + * --no-leafs/-intermediate options were broken. Then didn't + relink parents & children of the removed node. This should be now + fixed. + [44833374b2d5] + +2013-03-03 Eero Tamminen + + * src/debug/profile.h: + commit also header change + [8db7c9893126] + + * src/debug/debugcpu.c, src/debug/debugdsp.c, src/debug/profile.c: + profiler: make "addresses" behave like other disassembly commands, + add "save" command + + - "addresses" disassembly argument is now address/range from where + one want disassembly with profiling data. + - by default configured number of dissassembly lines is shown, but + user can give also a range, like for other disassembly commands. + - "addresses" command is continued by pressing enter, like other + disassembly commands. + - profile saving isn't anymore done with "addresses" command, but + separate "save" profiler subcommand. + [1097366f8f9a] + + * src/gemdos.c, src/xbios.c: + add missing TOS4 gemdos/xbios OS call names + + TOS4 does these calls at bootup. + [374c2e6d3fbc] + + * doc/compatibility.html: + add link to no-fragments + [fed2e34d9099] + +2013-03-01 Eero Tamminen + + * doc/emutos.txt: + update emutos compatibility for v0.9.0 + [af5937e37037] + + * tests/tosboot/bootauto.st.gz, tests/tosboot/bootdesk.st.gz, + tests/tosboot/disk/GEMDOS.PRG, tests/tosboot/disk/MINIMAL.PRG: + boot test programs rebuilt with newer AHCC version + [d51feee676da] + + * tests/tosboot/disk/ahcc-gemdos, tests/tosboot/disk/ahcc-minimal: + increase AHCC script EmuTOS boot wait for EmuTOS v0.9.0 + [25cb788f1574] + + * tests/tosboot/tos_tester.py: + bootup tester updates, mainly for new EmuTOS v0.9.0 features + + - add support for testing ACSI and IDE disks, but allow that only + for EmuTOS as others require driver to be installed on HD image + - add VDI testing for Falcon, but allow that only for EmuTOS as TOS + 4.x doesn't work with VDI screens. Increase VDI screen sizes used + for testing slightly (to catch TOS 4.x type issues) + - change EmuTOS feature checks to be based on image sizes as EmuTOS + reported TOS version may increase when it gets new features, but + EmuTOS compatibility to Hatari features (like IDE) differs from + real TOS with similar TOS version + - fix pylint complains, mainly with docstring updates + [8cc612171c94] + + * doc/manual.html: + update GEMDOS emu information in manual + [12284fdc3f43] + +2013-02-27 Eero Tamminen + + * src/debug/profile.c: + sort caller info by calls + better comparison function names + [0fa9f7d4d7f0] + + * src/debug/profile.c: + fix DSP caller info and improve profiler warnings + [604e08566a94] + +2013-02-26 Eero Tamminen + + * src/debug/profile.c: + fix DSP calltype info and add legend to profile disassembly output + [bd5489c8d4b6] + + * src/debug/profile.c, tools/hatari-profile.py: + add caller type to profile callers information + + - heuristics based on instruction type at previous PC address to + decide what type of "call" is being done + - output of that information, with legend explaining it + - some warning check changes + - post-processor changes to accept this new information and profile + file comments (accept=ignore) + [49416318c2ac] + +2013-02-25 Eero Tamminen + + * tools/hatari-profile.py: + several new profiler post-processor options and output changes + + - addresses and cycles time is shown only if new -i/--info option + is specified. This way output fits to normal sized console and + can be pasted easier to mails etc + - add --no-leafs/--no-intermediate callgraph options to reduce + callgraph nodes (done before --ignore-* option parsing) + - add --emph-limit option for callgraph node highlighting + - lists show now both normal and propagated values when + -p option is used, IMHO this makes it more readable + - some changes to how verbosity is handled internally + [77745da7466a] + +2013-02-24 Eero Tamminen + + * src/debug/symbols.c: + fix typos in DSP symbol lookup (cpu -> dsp) + [ae633ffb9c8a] + + * src/debug/profile.c: + fix typos in DSP symbol lookup (cpu -> dsp) + [2eaa46770138] + + * src/debug/profile.c: + fix: used CPU sites member for DSP sites + [cb3e2a1394a5] + +2013-02-23 Eero Tamminen + + * tools/hatari-profile.py: + add --propagate options and arrow coloring in callgraphs + + Propagate option propagates estimated function costs based on call + counts, upwards in the graph to callers. Output is visible both in + callgraph and lists. + + Callgraph arrows to nodes which have high costs are red, so that + it's easier to track them within other arrows. + [67ea321dfd0e] + +2013-02-22 Eero Tamminen + + * tools/hatari-profile.py: + add & use parent/child info from function instances + + This is easier to use than separate callinfo and easier to extend. + [76689d8f3841] + +2013-02-21 Eero Tamminen + + * tools/hatari-profile.py: + use line number info in totals output + + (line info was added with FunctionStats change.) + [2e4f329a417b] + + * tools/hatari-profile.py: + use better variable name ProfileStats + [a599211362c4] + + * tools/hatari-profile.py: + separate function statistics to its own class + + FunctionStats class was added in preparation for further callgraph + processing and accounts for most changes. Additionally: + - changed profile items to be indexed by address, not symbol + - used also addresses for graphviz dot node names + - hopefully clarified the profile parsing code more + [4f8ecca20133] + + * src/debug/debugInfo.c: + revert previous commit, it's redundant + + All calls (from conditional breakpoints and debugui.c) to this + function already init session. + [0f071c45b319] + + * src/debug/debugInfo.c: + lock file subcommand needs to init CPU & DSP sessions too + + similarly to breakpoint file actions, CPU & DSP debug sessions need + to be initialized before file is parsed, for things to be correctly + setup for the parsed commands. + [0fef0b07c15a] + +2013-02-20 Eero Tamminen + + * tools/hatari-profile.py: + remove dead code + [84ce27eafc73] + + * tools/hatari-profile.py: + symbol parsing improvements + + - instead of checking whether address is within TEXT section and + making it relative before looking it up from symbols (on each + parsed address), have separate option for giving relative symbols + and relocate them once after memory areas have been parsed + - fix for handling symbols parsed from profile which needed to be + renamed because those symbols were already used for another + address + - fix couple of bugs in symbol resolving when switching from one + memory area to another (i.e. corner cases) + - give real addresses for RAM/TOS/etc area symbol (used when no + normal symbol matches), not just address for first executed + instruction in them + + Symbol handling is hopefully now bug free. + [17781c5ee1a5] + + * src/debug/profile.c: + allow profiler output file overwrites + [78fbae9e06eb] + + * tools/hatari-profile.py: + refactor, remove ugliest InstructionStats object innards poking + [7c7dd827c5d8] + + * tools/hatari-profile.py: + fix for "no functions" case, improve verbosity + [ffbd88e8a2d0] + +2013-02-19 Eero Tamminen + + * tools/hatari-profile.py: + fix area offset return value + [5de796942e20] + + * tools/hatari-profile.py: + fixes to symbol processing and make profile parsing sequential + + Symbol processing has following improvements: + - function could have changed between disassembly discontinuations, + get the correct function name in those cases + - resolve first address in profile to preceeding symbol (as profile + file doesn't necessarily have name of that) + - when adding symbols from profile file, they may need to be made + relative [1] + - symbols with same name but different address are renamed so that + information for them gets assigned right + - symbols with illegal chars for Graphviz node names are renamed + (for now, later I will use separate node IDs) + + [1] For now. Profile file parsing was changed to parse each profile + data part separately before moving to next data types. This was + made so that memory area information can be guaranteed to be + available when symbol resolving needs to be done. + + With that change, text-relative symbols could be "relocated" + at start of profile parsing, instead of needing to do that for + all the addresses parsed from the profile itself (when checking + whether there's a symbol corresponding to that address) + [7606e17450c2] + + * src/debug/profile.c: + support disassembly while profiling, with DEBUG show zero cycle + instructions + [096b44f1c1c4] + + * tools/hatari-profile.py: + limits work similarly to both callgraphs & lists + usage update + [7a69fdf6a9b7] + +2013-02-18 Eero Tamminen + + * tools/hatari-profile.py: + refactor callgraph code, create separate callgraph for each profile + item + [3fb64a6d9d56] + + * tools/hatari-profile.py: + refactor statistics output, replace -c -e -i -m options with -t + + This refactoring cleaned out duplicate code and I think single + options is nicer. There were also couple of unrelated argument + changes elsewhere. + [a810fe9e4894] + + * tools/hatari-profile.py: + minor output improvements + [dab21ae1b46e] + + * tools/hatari-profile.py: + improve output handling and remove dead code + [813c0e02087b] + + * tools/hatari-profile.py: + refactor symbol & memory area handling to separate class + [d96f9b5fc13b] + + * tools/hatari-profile.py: + add second method for call address resolving + + - instruction count for first instruction in function can be used + as a call count, with that one can provide call count lists also + without caller profile information + - fixed resolving address to a preceeding symbol (visible in stats + and callgraphs) + - continued item field handling generalization, dsp cycle + differences field has now correct heading + [0b16216700d8] + +2013-02-17 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + fix 2 DSP timings problems: + - L access to external memory was taking 2 cycles too much + - jmp with immediate adress in external memory too + [b8a5a1f287d1] + +2013-02-17 Eero Tamminen + + * src/debug/profile.c, src/falcon/dsp.c: + profiling info is collected after instruction has been executed + + This is to be able to collect all relevant information. At that + point PC is on next instruction and profiling code needs to store + and deal with previous PC value. + + Change DSP update also to be called like that + do related profiling + code changes. + [0e39ef4c0f60] + + * doc/release-notes.txt, src/debug/breakcond.c, src/debug/profile.c: + Fix profiler usage in debugger files invoked by breakpoints + + Allows profiling automation by chaining breakpoints. + [c422aff63049] + +2013-02-16 Eero Tamminen + + * doc/release-notes.txt: + update release notes (and capitalize all items for consistency) + [342be5cd19f4] + + * src/debug/profile.c, tools/hatari-profile.py: + add processor speed to profile data & post-process it + + *INCOMPATIBLE PROFILE DATA CHANGE* + -> profiler and post-processor need to be both either older or + newer than this commit + + Post-processing: + - generalize code for handling memory areas and move really Hatari + specific options (disassembly format & memory areas) to a subclass + - start generalizing profile item count handling + - parse and store processor speed information + - based on that, add time information to callgraph nodes and symbol + lists + + Profile data saving: + - output processor speed info + - change memory area identifiers to such that they can be used as + symbols (no spaces) and remove RAM area + [80ce1e22bfd5] + + * src/debug/profile.c: + fix profiler's suspicious cycles warnings: + + - give correct (=previous) PC address in message + - STOP instruction can have arbitrary cycles values, don't report + large values for that + [15bfd1841794] + +2013-02-15 Eero Tamminen + + * src/debug/profile.c: + add time info to profile stats + + (and show the memory areas in the address order) + [9a9c44adb88f] + + * src/debug/profile.c: + Fix CPU cycle counting when DSP enabled + some code cleanup + [f97aba0cd462] + + * src/debug/debugInfo.c, src/falcon/dsp.c, src/falcon/dsp.h: + add "info dsp" command (shows e.g. stack content) + [3ddc10dc970f] + +2013-02-14 Eero Tamminen + + * tools/hatari-profile.py: + major improvements to the profile data post-processor + + - add callgraph output and some filtering options to control it + - add top function call count list + - add --limit option to limit lists based on function percentages + (and what gets emphatized in callgraphs) + [03da50aaed18] + +2013-02-12 Eero Tamminen + + * tools/hatari-profile.py: + improve symbol handling and don't list empty values + + symbol handling: + - GCC local symbols can be prefixed with [$.] + - object file name symbols can have [.-] in them + - more robust object file name test + - don't show warnings when changing symbol: + - to a one with or without (short) prefix + - for object file name + [0a61a075c21b] + + * src/debug/profile.c: + fix compiler warnings / DSP value overflow check + + max_cycles needs to be 64-bit as cycles counter for DSP is 64-bit + (it's 32-bit for CPU to save memory). + + Added ifdef as cache misses are stored only for WinUAE. + [c50c2840640c] + +2013-02-11 Eero Tamminen + + * tools/hatari-profile.py: + pylint warning fixes & profile doc updates + [520bf534286b] + + * src/debug/68kDisass.c: + fix disassembly column changing function + + Not all of the new column values were initialized. + + Depending on stack content, this could cause disassembly to segfault + with profile disassembly output (which is currently only thing + changing the columns). + [3aaa293359f0] + + * doc/release-notes.txt: + update release notes + [05cdba686ddd] + + * src/falcon/hostscreen.c, src/includes/resolution.h, + src/resolution.c, src/screen.c: + fix max resolution handling for ST mode + [49221d1651bc] + + * doc/release-notes.txt: + update release notes + [672934113016] + + * src/falcon/nvram.c, src/reset.c, src/vdi.c: + setup NVRAM video mode based on VDI mode, when in VDI mode + + Based on patch by Vincent Rivire which makes VDI mode work properly + with EmuTOS under Falcon emulation. + + It doesn't change the situation for real TOS: + - TOS v3 still doesn't work with monochrome VDI modes with height < + 480. + - TOS v4 still doesn't work with VDI mode which sizes are >32kB. + [285a171457c1] + + * tools/hatari-profile.py: + make usage info also whole script doc + [155a2f47cfa6] + + * tools/hatari-profile.py: + prepare post-processor for callgraph addition + + - add callee/caller information parsing + - move statistics to separate class + - move totals summing to instructions class + [8e219c54209b] + +2013-02-06 Eero Tamminen + + * src/debug/profile.c, src/debug/symbols.c, src/debug/symbols.h: + symbol address caller tracking for CPU & DSP profiler + + Callers to addresses which have symbols associated with them, are + tracked and separate call counts are kept for each. This + information is output if profiler 'addresses' command output goes to + a file, and with the separate 'callers' command. + + Caller information is required for being able to get callgraphs for + the executed code. + [b0b3855641a0] + +2013-02-05 Eero Tamminen + + * src/falcon/nvram.c: + remove (now redundant) nvram.c Dprintf defines + [d1a5fd7673d7] + +2013-02-04 Eero Tamminen + + * src/includes/vdi.h, src/vdi.c: + prevent bad ratio still giving too large values + + also, with VDI size alignment, smallest size can be ST-low. + [568b370ceb03] + + * src/includes/vdi.h, src/screen.c, src/vdi.c: + limit VDI screen size to 300kB + + This allows slightly larger resolutions while reducing Hatari memory + usage and making sure that selected VDI resolution works e.g. in + EmuTOS and older TOSes. + [3d35685fbce3] + +2013-02-03 Eero Tamminen + + * src/debug/log.c, src/debug/log.h, src/falcon/nvram.c: + add run-time trace support for NVRAM reads & writes + [187c3f4ba6fa] + + * src/vdi.c: + fix comment + [aa960e04a9aa] + +2013-02-02 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + fix: simultaneous access to external X and Y memory cycles was wrong + (thanks to Doug For this) + [f9b90a3c6529] + +2013-02-01 Eero Tamminen + + * src/debug/profile.c: + correct CPU area calculations + + (should have been updated when TOS data was moved before Cartridge + data, several commits ago.) + [76cf815555ee] + + * src/debug/profile.c, src/debug/profile.h, src/falcon/dsp_disasm.c: + use 64-bit variables for DSP instruction & cycle counts + + because this needed adding separate DSP area function, I could add + also the cycle diff sum information to statistics output. + [e162c2712aca] + +2013-02-01 Laurent Sallafranque + + * src/cpu/newcpu.c, src/includes/m68000.h: + change: take into account the 68030 cycles in cache mode ON + [5a63aa977dfb] + + * src/falcon/dsp_cpu.c: + fix: extra access to external memory after the first one cost 2 + cycles instead of one (thanks to Doug Little for the TIP) + [622e01afef0b] + +2013-02-01 Eero Tamminen + + * doc/release-notes.txt, src/debug/breakcond.c, src/debug/debugcpu.c, + src/debug/debugdsp.c: + make breakpoints silent on 'n' command + [71e0b614e44c] + + * tests/debugger/test-dummies.c: + update debugger tests to recent changes + [5e6e15d9c82b] + + * doc/release-notes.txt: + update release notes, put profiler and windows changes under their + own headings + [50ab066f2872] + + * src/debug/profile.c: + try at working around wrong cycles diff value + [85e65361fd09] + + * src/gui-win/opencon.c: + update includes also + [0aef18a3c0cf] + + * src/configuration.c, src/gui-win/opencon.c, + src/includes/configuration.h, src/options.c: + add -W for opening log window on Windows, fixed(?) Windows stderr + redirection + [bc086ca89534] + + * src/debug/profile.c, src/debug/profile.h, src/falcon/dsp_disasm.c: + instead of min/max DSP cycles, show diff of them + + post-processor can output DSP cycle diffs (use of different memory + areas/registers) as "cache misses". + [331dbec754bf] + +2013-01-31 Eero Tamminen + + * src/debug/profile.c, src/debug/profile.h, src/falcon/dsp_disasm.c: + separate CPU & DSP profile data structures, add min/max DSP cycles + info + + using separate structures allows providing different info for CPU + and DSP + [cc810af306ca] + + * tools/hatari-profile.py: + adapt to any number of items in profile + + (currently processes up to 3 of them, but doesn't throw exception if + there are more) + [7849c0f07658] + + * tools/nm-symbols-cleanup.sh: + helper script to cleanup MiNT 'nm' output for symbols command + [d9c87d1f668d] + + * tools/hatari-profile.py: + fix memory area symbol assignment + + (depends on previous profile.c update) + [46e0dc036194] + + * src/debug/profile.c: + output profile addresses in memory order + + (previously cartridge area came before ROM TOS) + [fc24052241c7] + + * tools/hatari-profile.py: + fix post-processor exceptions + [66ec14d4ad90] + + * src/debug/symbols.c: + object file symbol names can contain '-' characters + [8c3d7588c70a] + + * tools/hatari-profile.py: + symbol check improvements + + - silently ignore duplicate symbol info + - warn about consequences of having same symbol name for multiple + addresses (= overriding symbol info) + [c4a4ec506735] + + * tools/hatari-profile.py: + skip memory area checks for DSP profiles + [0f25b499decd] + + * tools/hatari-profile.py: + profile file and output handling imporovements + + - automatically identify whether profile is for DSP or CPU based + on new profile header + -> removed "-d" option + - separate class for handling file & user output + - exit on first error + - if there's no other symbol, collect stats under generic memory + area (RAM, text section, TOS ROM, Cartridge ROM) symbols + [e675970e0a39] + + * src/debug/profile.c: + add profile identifier to profile file + [12a6da6a7d56] + +2013-01-30 Eero Tamminen + + * doc/release-notes.txt: + add recent changes to release notes + [4668dded703c] + + * tools/hatari-profile.py: + support DSP profile output, with -d option + [618eb9d430d0] + + * tools/hatari-profile.py: + improve symbol addresses handling + + - accept hex addresses with and without 0x prefix (EmuTOS .sym + files have prefixes) + - igore object file names if there's already symbol name for that + address + - take note which symbols were taken from symbols file, which ones + from profile data + - add function addresses to lists for functions which names were not + in the profile data + [273fb1e47588] + + * tools/hatari-profile.py: + remove mins as useless and add max value address + [e7d7ec1b0923] + + * tools/hatari-profile.py: + add instruction statistics output + [cadc03ee0983] + + * src/debug/profile.c: + cycles information is for previous instruction, compensate + [fc43c1919409] + + * tools/dsp-lod-symbols-convert.sh: + preliminary DSP LOD -> symbols file convertor + [391d95be4c57] + + * src/debug/profile.c: + fix define check + [4f7726c1cfaf] + + * src/debug/profile.c: + cycles counter seems cumulative, compensate in profiler + [9f32e52a9eff] + + * tools/hatari-profile.py: + fix profiler exception + disable debug output + [c673c9554622] + + * tools/hatari-profile.py: + first version of Hatari profile data post-processor + [91159729a47f] + + * src/debug/profile.c: + output TOS/RAM/TEXT/Cartridge addresses to profile data + + profile data post-processing assume TOS addresses are absolute and + program TEXT segment addresses are relative so it needs to know + where those are. + [841b62a4ec5c] + + * src/debug/breakcond.c, src/debug/debugInfo.c, src/debug/debugInfo.h: + add TEXTEnd debugger variable (last address of program text segment) + [91c34a9c6134] + +2013-01-29 Eero Tamminen + + * src/debug/symbols.c: + symbols command: offsets can be given for data and bss in addition + to text + [ae2a024e97aa] + +2013-01-28 Eero Tamminen + + * src/debug/profile.c: + assign DSP cycles cost to previous instruction + + this is because debugger is called before DSP instruction is + executed i.e. cycles information is for the previously executed + instruction + [82fb7d79f349] + + * src/joy.c: + fix const warning introduce by previous joy.c commit + [801c9f81debd] + + * src/debug/68kDisass.c: + minor improvements to disassembler text file reading + + - correct ftell() error checking + - free buffer on error exit + - remove redundant frees on file read function fail + - ANSI-C variable declarations + [a2f0dc4f1d12] + + * src/includes/joy.h, src/joy.c: + fix mudflap warning in joy axis mapping code + + With some rewriting: + - Moved the structs to joy.c as they aren't used by anything else + - Used const char pointers for name string + - Used array size as loop exit condition instead of string checking + [49285266aa38] + + * src/debug/68kDisass.c: + fix mudflap warning: stack buffer accessed from outer scope + + additionally, remove sp variable shadowing (which confused the issue + how much up the stack buffer usage goes). + [1db010f1f13e] + + * tools/devpac3-symbols-convert.sh: + Devpac 3 listing symbol table -> Hatari debugger symbols convertor + [a8658c94d48c] + +2013-01-27 Eero Tamminen + + * src/debug/profile.c: + use Cycles_GetCounter() to get CPU cycles + + It works for everything else except non-cycle exact WinUAE CPU core + option. The main thing is getting this working for cycle exact CPU + core... + [6d8054f1cd9c] + +2013-01-26 Eero Tamminen + + * src/debug/breakcond.c, src/debug/debugdsp.c, src/debug/history.c, + src/debug/profile.c, src/falcon/dsp.c, src/falcon/dsp.h, + src/falcon/dsp_cpu.c, src/falcon/dsp_cpu.h: + support for specifying profile addresses output file + + This required adding FILE* option for DSP disassembly functions + which caused updates in several places. + [031e2313bd32] + + * src/cpu/newcpu.c, src/debug/68kDisass.c, src/debug/profile.c, + src/debug/profile.h, src/includes/m68000.h, src/m68000.c: + add CPU instruction cache miss profiling + + Note: CPU cache is supported only by WinUAE CPU core. + [09178bc26b9d] + +2013-01-26 Thomas Huth + + * src/acia.c, src/cart.c, src/cfgopts.c, src/cycInt.c, src/dmaSnd.c, + src/fdc.c, src/gemdos.c, src/hd6301_cpu.c, src/hdc.c, src/ide.c, + src/ikbd.c, src/ioMemTabFalcon.c, src/main.c, src/mfp.c, src/psg.c, + src/screen.c, src/sound.c, src/unzip.c, src/video.c, src/xbios.c, + src/zip.c: + Fixed typos reported by codespell + [5f752775d03e] + +2013-03-05 Nicolas Pomarede + + * src/cpu/newcpu.c, src/cpu/newcpu.h, src/falcon/dsp.c, + src/falcon/dsp.h, src/mfp.c, src/uae-cpu/newcpu.c, src/uae- + cpu/newcpu.h: + Remove DSP's IRQ from mfp.c and call DSP_ProcessIRQ() from the CPU + emulation + [8a53f5849c9b] + +2013-03-04 Nicolas Pomarede + + * src/mfp.c: + Clear IRQ in MFP_Reset() + [b9e7a1f3b2b1] + + * src/includes/mfp.h, src/mfp.c: + Remove MFP debug code and change VR description + [12297107d383] + +2013-03-03 Nicolas Pomarede + + * src/mfp.c: + Add new interrupt related variables to the memory snapshot + [df99d056cd97] + + * src/mfp.c: + Remove old wrong/commented code + [df216ace9fa0] + + * src/mfp.c: + More compact versions of MFP_CheckPendingInterrupts() and + MFP_InterruptRequest() + [088c3385ad19] + + * src/uae-cpu/newcpu.c: + Remove debug printfs + [877d09d67cf2] + + * src/mfp.c: + Indent comments + [88b96b7c242f] + + * src/mfp.c: + When an MFP interrupt happens, a delay of 4 cycles is needed before + the CPU receives it (fix Audio Artistic Demo and the games Super + Hang On, Super Monaco GP, Bolo) + [aed047c66614] + + * src/uae-cpu/newcpu.c: + Remove debug printf + [e55dcee66530] + +2013-02-25 Nicolas Pomarede + + * src/cpu/newcpu.c, src/includes/mfp.h, src/mfp.c, src/uae- + cpu/newcpu.c: + In the main CPU loop, use MFP_ProcessIRQ instead of + MFP_CheckPendingInterrupts The MFP must only set IRQ to 0 or 1, + without taking SR into account. That's up to the CPU emulation part + to call MFP_Exception if MFP_IRQ=1 and SR allows it. + [e4d838d59eb1] + +2013-02-24 Nicolas Pomarede + + * src/m68000.c: + Add comment about useless test to remove later + [acbf9a5092fd] + + * src/mfp.c: + Remove useless check for unused MFP bits + [8b1f68189385] + + * src/mfp.c: + MFP_UpdateIRQ should also be called when ISRx and IMRx are modified + [c078b28a777b] + + * src/mfp.c: + Rename MFP_UpdateFlags to MFP_UpdateIRQ and use + MFP_CheckPendingInterrupts() + [339d45cf4226] + + * src/cpu/newcpu.c, src/includes/mfp.h, src/mfp.c, src/uae- + cpu/newcpu.c: + In MFP_CheckPendingInterrupts, return the MFP interrupt number + instead of true/false + [4f0c947a8149] + + * src/uae-cpu/newcpu.c: + Call do_specialties() only once per opcode, not for every expired + internal timer + [d2bc5a7d2362] + + * src/mfp.c: + There can be only one MFP interrupt source at a time Only the + highest priority pending interrupt should cause an exception The + previous code was wrong as it would called several exceptions at the + same time and stack them in the reverse order (lower prioriry first + !) + [cafa412936da] + +2013-01-24 Eero Tamminen + + * src/debug/profile.c, src/debug/profile.h: + fix typo, make functions static (as they aren't called outside of + profile.c) + [dffe52d0aef1] + +2013-01-21 Eero Tamminen + + * doc/manual.html: + LMC emu is stable, not experimental + [ee1104daa49e] + + * src/debug/breakcond.c: + fix copyright line + [663a551f6e35] + +2013-01-20 Nicolas Pomarede + + * doc/compatibility.html: + Update notes for the demo 'V8 Music System' + [25a5efed0eec] + + * src/acia.c: + When ACIA's IRQ is set, the MFP IRQ should happen 4 cycles later + This delay was measured on a real STF. + [fa948c81a521] + +2013-01-17 Thomas Huth + + * src/cpu/cpummu030.c: + MMU030: Minor fixes (taken from upstream Previous emulator) + [22b7347cd5d7] + +2013-01-13 Thomas Huth + + * doc/compatibility.html, doc/manual.html: + Final HTML clean-up: Documentation files are now valid HTML5. + [bfd8c62a896a] + +2013-01-13 Nicolas Pomarede + + * src/ikbd.c, src/includes/ikbd.h: + Remove redundant variable KeyboardProcessor.bReset We always have + bReset = !bDuringResetCriticalTime, so bDuringResetCriticalTime is + enough + [a32d1ace5c43] + + * doc/release-notes.txt: + Update notes for ACIA/IKBD changes + [5873a5709ead] + + * src/ikbd.c: + Better timings for the $F1 byte returned by IKBD's reset command $80 + $01 This delay was accurately measured on a real STF with a custom + program + [b889b39f7d58] + +2013-01-12 Thomas Huth + + * doc/compatibility.html, doc/manual.html: + HTML cleanup: Replaced obsolete tags + [2f70d2774044] + + * doc/compatibility.html, doc/manual.html: + HTML cleanup: Now using proper table headers + [fe5e9775d00a] + +2013-01-13 Nicolas Pomarede + + * src/ikbd.c, src/includes/ikbd.h: + For hardware and software reset, use the common code in + IKBD_Boot_ROM() + [801bd44a41ab] + +2013-01-12 Nicolas Pomarede + + * src/cpu/hatari-glue.c, src/uae-cpu/hatari-glue.c: + Call IKBD_Reset() when the RESET instruction is used + [29e79b0f5c7b] + +2013-01-08 Eero Tamminen + + * src/vdi.c: + bugfix: show also appl_init() in AES traces + [437a388e93e3] + +2013-01-06 Nicolas Pomarede + + * src/ikbd.c: + During IKBD reset, use the define IKBD_ROM_VERSION instead of 0xF1 + [7edf5a1632c6] + + * doc/compatibility.html: + Add notes for the game "F29 Retaliator" + [c3a2292fc972] + +2013-01-05 Nicolas Pomarede + + * doc/compatibility.html: + Add notes for the game "Warlock's Quest" + [4e562d54ee91] + +2013-01-04 Nicolas Pomarede + + * src/gui-sdl/dlgFileSelect.c: + Fix a bug when remembering the fileselector scrollbar's position + When using the fileselector in a large directory, then going to a + small directory with <= 16 entries, the scrollbar was drawn at the + wrong position. + [b05f51174cd3] + +2013-01-02 Nicolas Pomarede + + * src/ikbd.c: + For the IKBD's output buffer, fix the check to send a new byte in + TDR + [f31979234f79] + + * src/ikbd.c: + In the IKBD, don't ignore a new byte in RDR if the output buffer is + not empty The IKBD can handle new byte asynchronously, even if the + current command is not completed and still has some bytes to send + (fix a regression in the game 'Zombi') + [798aa5a0b334] + + * src/ikbd.c: + Correctly check the IKBD's output buffer is not full when adding one + byte + [3fb423fda660] + + * src/ikbd.c: + Remove old special case for the game 'Downfall' and update comments + [982565195a9e] + + * src/ikbd.c, src/includes/ikbd.h: + When the IKBD sends a packet, check there's enough room in the + output buffer Some programs can crash or lock if the received packet + is truncated or malformed due to the output buffer being full + [0d37b6f36006] + +2012-12-31 Nicolas Pomarede + + * src/ikbd.c: + Prevent a possible buffer overflow when sending commands to the IKBD + [38b507da21cb] + +2012-12-30 Nicolas Pomarede + + * cmake/Toolchain-mingw32.cmake: + Autodetect mingw's sysroot path + [1d91985e1e45] + +2012-12-30 Eero Tamminen + + * tools/zip2st.sh: + zip2st: check that given zipfile exists + [ed8fec2932c5] + +2012-12-27 Nicolas Pomarede + + * src/dmaSnd.c: + Add more traces when accessing dma sound / microwire + [ba74a5ac5d5c] + +2012-12-25 Nicolas Pomarede + + * src/ikbd.c: + Update traces for IKBD's clock + [01ff9c5f8a26] + + * src/ikbd.c: + Add more traces for non supported IKBD commands + [385ee0236e29] + + * src/ikbd.c: + Return the correct number of bytes for IKBD's ReadMemory ($21), even + if not implemented We can't return the real content of the IKBD's + RAM, but at least we return the correct header + 6 empty bytes. + [56a46f3b7eeb] + +2012-12-24 Nicolas Pomarede + + * src/ikbd.c, src/includes/ikbd.h, src/video.c: + Rewrite SetClock ($1B) and ReadClock ($1C) commands to behave like + the real IKBD We don't use time()/locatime() anymore to update the + clock ; it was not very portable on some OS and gave wrong results + sometimes anyway. This new code is based on the HD6301 disassembly + of the IKBD's ROM. + [a5438d3f91c7] + +2012-12-23 Thomas Huth + + * src/gui-sdl/dlgSystem.c: + Fixed the length of dialog objects + [06c7da4de001] + + * doc/compatibility.html: + Added more Falcon demos that require an FPU. Thanks to Anders + Eriksson for the hints! + [8285e9fad0f6] + + * src/bios.c: + Fixed format string (Clang compiler issued a warning) + [be12eb28ae60] + +2012-12-23 Nicolas Pomarede + + * src/ikbd.c: + Better timings for the bytes returned by IKBD's commands $16, $1C, + $87-$9A This delays were accurately measured on a real STF with a + custom program + [e0e2dd72877a] + +2012-12-23 Thomas Huth + + * doc/compatibility.html: + Added Captain Blood and Zombi to the compatibility list + [fd71f9af7301] + + * doc/toc.js: + Scroll to the right section in manual, second try + [06b506a2bc1a] + +2012-12-22 Thomas Huth + + * src/cpu/newcpu.c: + MMU030: The MMU configuration exception must generate stackframe + type 0x2. Thanks to Andreas Grabher for the hint! + [3f7e214b3bf5] + + * src/cpu/cpummu030.c: + MMU030: Reworked debugging messages + [7cd019393a09] + +2012-12-22 Nicolas Pomarede + + * src/midi.c: + Also uses ACIA_AddWaitCycles when accessing MIDI, to take E Clock + into account + [8cbcceb56d6f] + + * src/acia.c, src/includes/acia.h: + Use E Clock to correctly emulate the number of cycles when accessing + ACIA This E Clock delay was accurately measured on a real STF with a + custom program + [e425ec2302fc] + + * src/includes/m68000.h, src/m68000.c: + Add M68000_WaitEClock to count cycles needed to reach the next E + Clock's edge When procesing HBL/VBL interrupts or ACIA accesses, the + CPU needs to be synchronised with the E Clock, which is 1/10th of + the CPU frequency. + [80732d4a020e] + + * src/cycles.c: + Add a comment for the case where MovepByteNbr==0 + [3b501f24cb5b] + + * src/cpu/gencpu.c, src/uae-cpu/gencpu.c: + Also uses MovepByteNbr=0..4 for MOVEP M->R + [8c723ae84390] + +2012-12-22 Thomas Huth + + * doc/manual.html: + Some more HTML fixes + [4902c8ed0e69] + +2012-12-22 Nicolas Pomarede + + * src/cpu/gencpu.c, src/uae-cpu/gencpu.c: + For MOVEP R->M, set MovepByteNbr=0 after the last byte access This + means that if MovepByteNbr=1..4, we're emulating a movep + instruction. If MovepByteNbr=0 we're not emulating another opcode + than movep. + [347591bae8e9] + +2012-12-22 Thomas Huth + + * doc/toc.js: + Added a hack to force the browsers to show the right section when + coming from an external link + [dc5739a3e2b1] + + * doc/manual.html: + Fixed bad HTML + [c5381004050e] + +2012-12-21 Eero Tamminen + + * doc/manual.html: + test for external linkage to manual + [c65baecb6a03] + +2012-12-21 Nicolas Pomarede + + * src/acia.c, src/midi.c: + Access to the ACIA's registers add a delay of 6 cycles per valid + register This 6 cycles delay was accurately measured on a real STF + with a custom program. + [bc25b3804359] + +2012-12-17 Eero Tamminen + + * doc/manual.html: + update manual: + + - printer/RS-232/MIDI work fine, so remove experimental comment + - finetune mouse and printer descriptions a bit + [46a075ccf9fb] + +2012-12-16 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [3f0d182f1b20] + + * src/gui-sdl/dlgFileSelect.c: + add CWD button to SDL fileselector + [0becbbc32f54] + + * doc/hatari.1, doc/manual.html, src/options.c: + fix -c option description and add more docs on Hatari configuration + [d090fa137db8] + +2012-12-13 Eero Tamminen + + * doc/emutos.txt: + update doc to latest EmuTOS state (fsel_ex support/fix) + [b061dd3b7905] + + * python-ui/CMakeLists.txt: + only hatariui and debugui need to be installed executable + + (Debian Sid patch for Hatari set only conftypes as non-executable, + but actually most of the python files don't need to be executable) + [12fde5ca8a67] + + * doc/hatari.1: + apply dash patch from debian sid + + (+ add blackslashes also to args added after that) + [be69ef61b275] + +2012-12-12 Nicolas Pomarede + + * src/ikbd.c: + Fix an ACIA timing problem for IKBD commands returning more than one + byte The 1st byte was returned immediatly, the delay was ignored. + [e003f0053c3d] + +2012-11-25 Thomas Huth + + * src/cpu/cpummu030.c: + MMU030: Added MMU Configuration Exceptions. Sync'ed source code with + Previous. Thanks to Andreas Grabher for the changes! + [4fe8fcddbb63] + +2012-11-20 Eero Tamminen + + * doc/release-notes.txt: + release note about Pexec() fix, fit lines to 80 cols + [577eaa8b1262] + +2012-11-17 Eero Tamminen + + * doc/hatari.1, doc/manual.html: + document new debugger commands and new disasm option + [d965351b4ae6] + +2012-11-16 Thomas Huth + + * src/cartData.c, src/cart_asm.s: + Reworked pexec code in cartridge so that it does not destroys the + command line + [cb04d6e08831] + +2012-11-16 Eero Tamminen + + * doc/release-notes.txt, src/debug/68kDisass.c: + fix signedness issue in disassembler + + breaks disassembly output when compiled with PowerPC NetBSD using + GCC 4.1.3 + [b7f62ef99f25] + +2012-11-15 Thomas Huth + + * src/cpu/mmu_common.h: + Disabled the THROW + CATCH debug messages + [ef4abac4845f] + + * doc/compatibility.html: + Bumped version number for X-Tasie in compatibility list + [34e100dbd399] + +2012-11-14 Thomas Huth + + * doc/compatibility.html: + Updated X-Tasie in the compatibility list + [e013fb5f16fd] + + * src/debug/log.h: + TRACE_IOMEM_WR has to be declared as long-long to avoid bad sign + extension + [9b8489f75522] + + * src/falcon/videl.c: + Make sure that Videl display height does not get negative + [c53508439caf] + + * src/cpu/cpummu030.c: + MMU030: The unaligned access functions must not destroy the fault + address + [402fa9c51afa] + + * src/cpu/cpummu030.c, src/cpu/cpummu030.h: + MMU030: Improving try-catch in table search function. Patch taken + from Previous (thanks to Andreas Grabher) + [2ad6d8a9baee] + +2012-11-13 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [d389911ca1bb] + + * src/debug/debugcpu.c: + better comment + [b7ddf8c231b5] + + * src/debug/debugInfo.c: + fix corner cases for "lock regaddr" command DSP handling + [d261df121774] + + * src/debug/evaluate.c: + handle 16-bit DSP register names correctly in evaluate command + [badaf95300c7] + + * src/debug/debugui.c: + fix: recognize DSP shortcut commands correctly + + otherwise expression evaluation can expand "PC" to CPU PC register + instead of DSP one in DSP command. + [4b5546684b5f] + +2012-11-12 Nicolas Pomarede + + * src/includes/ym2149_fixed_vol.h: + Add missing end of line at end of file (fix compiler warning) + [ec535aca9caa] + +2012-11-12 Eero Tamminen + + * src/debug/debugcpu.c: + correct 'w' command info + [71bb145bdcee] + + * src/debug/debugInfo.c: + under MiNT, OS header differs from ROM one -> adapt info commands + [e885fb6b6324] + + * src/gemdos.c: + give info on GEMDOS vector + + (needed if one wants to re-enable GEMDOS redirection in debugger + after MiNT overwrites it.) + [15cfe34c3d3c] + +2012-11-10 Nicolas Pomarede + + * doc/authors.txt: + Add Paulo Simoes to list of contributors + [7762f8c0116e] + + * doc/release-notes.txt, src/includes/ym2149_fixed_vol.h: + Slightly better volume table for YM2149 emulation This table was + measured by Paulo Simoes on a real ST, and converted to Hatari's + format by David Savinkoff. + [ca407fdf9e15] + + * doc/release-notes.txt: + Add details for fixed games + [84a21f5c8c06] + +2012-11-09 Eero Tamminen + + * doc/release-notes.txt: + add info no recent improvements to release notes + + (and rephrase some things better) + [e5756e37b31c] + + * src/debug/68kDisass.c, src/debug/68kDisass.h, src/debug/debugui.c, + src/options.c: + add --disasm option + + Move flag parsing code from debugui.c to 68kDisass.c where the new, + more extensive disassembly option parsing resides. + [616b56695cb2] + + * src/configuration.c, src/debug/68kDisass.c, src/debug/68kDisass.h, + src/includes/configuration.h: + change nDisasmEngine to bDisasmUAE and add nDisasmOptions config + options + + We're not going to have more disassembly engines, so bool is enough + for engine selection and allows simplifying the checks. + [d898bc092749] + + * src/debug/68kDisass.c, src/debug/68kDisass.h, src/debug/breakcond.c, + src/debug/debugcpu.c, src/debug/history.c, src/debug/profile.c, src + /uae-cpu/newcpu.c: + simplify, check DisasmEngine option only in Disasm() + [5f0f93c98eea] + +2012-11-08 Eero Tamminen + + * src/configuration.c, src/debug/68kDisass.c, src/debug/breakcond.c, + src/debug/debugcpu.c, src/debug/history.c, src/debug/profile.c, + src/includes/configuration.h, src/uae-cpu/newcpu.c: + add "nDisasmEngine" configuration option + + Markus' disassembly engine has nicer looking output than the UAE + internal disassembler, and it's (now) also possible to configure its + output to some extent within debugger. + + However, Markus' engine doesn't output all instructions correctly + (MMU related ones, divul, maybe others), so it's better to leave the + selection between them to user. + [aff1f4f71ce3] + + * src/debug/debugcpu.c, src/debug/debugdsp.c: + Fix: after breakpoint, debugger runs one step too few + + Breakpoints need to be checked before stepping count, so that it's + breakpoint that hits on an address instead of first stepping + dropping you to debugger and then breakpoint. + + However, when continuing from breakpoint, step count shouldn't be + decreased before returning to emulation. Fix this by increasing + count after breakpoint. + + When using "next" command to continue with a set breakpoint, zero + any remaining step count. + [a86d44425c89] + + * src/debug/breakcond.c: + although breakpoint matches, rest of the breakpoints need to be + checked too + + Breakpoint matching code returned after first breakpoint match. This + had several problems: + - if the first matching one was "trace" breakpoint, user wasn't + dropped into debugger although other existing breakpoints would + have done that + - information for the other breakpoints that match at the same point + wasn't updated (for counted breakpoints) or shown (for trace + breakpoints) + - "once" breakpoints wouldn't have been removed if something else + was matched first + + This change will go check all breakpoints before returning (index + for the last matched one). + + Logic for counted breakpoints was inverted, that's also fixed. + [e1f7488a9601] + +2012-11-07 Eero Tamminen + + * src/gemdos.c: + output Pexec() args when tracing GEMDOS + [08aa8ef2588b] + + * src/change.c: + Also Blitter and CPU level changes require reset + + Otherwise things already using them and relying them can crash + [e2fd8b15f0ce] + + * src/tos.c: + fixes to TOS/machine/CPU type matching: + - TOS 1.62 works only with 68000 (unlike TOS 1.06) + - TOS v3(.06) doesn't work with 020, only 030/040 + - CPU level change requires call to M68000_CheckCpuSettings() + [ffd5f66b87f8] + +2012-11-06 Thomas Huth + + * src/cpu/cpummu.c: + Fixed TRY-CATCH-THROW_AGAIN so that it now should work without try- + stack underflow + [148506c580a3] + + * src/debug/68kDisass.c: + Fixed possible crash in disassembler (NULL pointer dereferenciation) + [c83bf5ed8d98] + +2012-11-05 Eero Tamminen + + * doc/release-notes.txt, doc/todo.txt: + update release notes & todo for last debugger improvements + [aba8fc7cb467] + + * src/debug/debugcpu.c, src/debug/debugdsp.c: + "next" debugger command for CPU and DSP, using new CPU/DSP + GetNextPC() functions + + This uses temporary conditional breakpoints so it's a bit verbose. + [071fef422e96] + + * src/falcon/dsp.c, src/falcon/dsp.h: + support for returning next DSP PC without disasm output + [97d057207ac2] + + * src/debug/68kDisass.c, src/debug/68kDisass.h: + support for returning next CPU PC without disasm output + [4148340604fb] + + * src/debug/68kDisass.c, src/debug/profile.c, src/debug/profile.h, + src/falcon/dsp_disasm.c: + add percentage to profiling info in disassembly + + - this should make it more readable as numbers are aligned and + smaller so they are easier to compare + - counts and cycles are now shown in parenthesis + [085e349a4e94] + + * src/debug/profile.c: + remove hexdump column from profiler disassembly output (in an effort + to try to fit it into normal console width) + [535baf72ea6a] + + * src/debug/debugui.c: + add 'setopt' command 'disasm' subcommand for setting output flags + [cc0e2004a10d] + + * src/debug/68kDisass.c, src/debug/68kDisass.h: + make disassembly output flags and columns internally configurable + [f349cb3cae10] + +2012-11-04 Nicolas Pomarede + + * src/acia.c: + In ACIA's init, define Set_Timers callback only for IKBD, MIDI is + not used yet + [1dee6e90e31e] + +2012-11-04 Thomas Huth + + * src/cpu/gencpu.c: + Fixed bug in RTE: format must be unsigned to avoid that 'frame' + value is calculated wrong. + [47b8c4b79bca] + + * src/cpu/cpummu030.c, src/cpu/cpummu030.h, src/m68000.c: + MMU030: Always use THROW for bus errors when MMU is enabled (patch + mostly taken from Previous emulator - thanks to Andreas Grabher) + [ee9e5ae15aa9] + +2012-11-04 Eero Tamminen + + * src/debug/debugcpu.c, src/debug/debugdsp.c: + add CPU and DSP single stepping commands 's' & 'ds' + [9486bdbe2d63] + + * src/debug/debugui.c: + improve debugger history handling: + - don't duplicate entries taken from history + - store also command continuing emulation + [5f1f41ca5932] + +2012-11-04 Thomas Huth + + * configure: + Fixed bug in configure script + [151a3e2a7c6d] + +2012-11-03 Eero Tamminen + + * src/debug/debugInfo.c: + fix array access in debug info command + [3b84036044a3] + +2012-11-04 Nicolas Pomarede + + * src/acia.c: + For ACIA's timer, use a 8 MHz CPU reference clock and nCpuFreqShift + We should not use MachineClocks.CPU_Freq, as Hatari currently relies + on a fixed 8MHz CPU clock for all its timings. + [f432a58f881e] + +2012-11-02 Eero Tamminen + + * src/debug/profile.c: + profiler improvements: + + - add "address" subcommand for CPU & DSP that shows all addresses + and their instructions that were executed during profiling (in + address-order, upto requested number of instructions) + - remove max counts/cycles instruction stats info as (now) redundant + - fix overflow detection for CPU cycles + [7cb52df179dc] + +2012-10-31 Nicolas Pomarede + + * doc/release-notes.txt: + Add new ACIA to the release notes + [3f6ab55cff74] + +2012-10-30 Nicolas Pomarede + + * src/debug/log.c, src/debug/log.h, src/ikbd.c: + Update trace levels for ACIA/IKBD + [7c0ee75971d7] + + * src/acia.c, src/ikbd.c: + Comment debug printf's + [892f32e86d40] + + * src/acia.c, src/ikbd.c: + Update acia/ikbd notes + [b5720e34ccd8] + +2012-10-29 Nicolas Pomarede + + * src/ikbd.c: + Remove unused code + [6ecba79f687a] + + * src/cycInt.c, src/ikbd.c, src/includes/cycInt.h, + src/includes/ikbd.h: + Remove old IKBD/ACIA's interrupt handlers + [ee920a5f3d50] + + * src/ikbd.c: + Remove old ACIA code included in ikbd.c, now we use acia.c + [f48f1439c44c] + + * src/ikbd.c: + Adapt IKBD's custom code for Froggies Over The Fence to the new + acia/ikbd code + [37e81c884d34] + + * src/acia.c: + Change some ACIA's LOG + [b2837526b8ad] + +2012-10-27 Nicolas Pomarede + + * src/acia.c, src/includes/acia.h: + In ACIA_Read_RDR, clear OVRN bit if SR was read + [a8939fbca144] + + * src/acia.c: + In ACIA_Write_CR, set new CR before updating IRQ + [b01679329839] + +2012-10-23 Nicolas Pomarede + + * src/acia.c, src/ikbd.c, src/includes/acia.h, src/includes/ikbd.h, + src/reset.c: + Restore ACIA's timer after a reset (fix Reset part in Dragonnels + Demo) + [1ae8dc236957] + +2012-10-22 Nicolas Pomarede + + * src/ikbd.c: + Fix IKBD's custom code for Dragonnels + add debug code to dump data + sent with LoadMemory + [740ea45b3d3a] + +2012-10-21 Nicolas Pomarede + + * src/acia.c: + Use the callback function instead of the direct call to start the + ACIA's timer + [086b8e72a092] + + * src/ikbd.c: + Add the new IKBD's SCI part to the memory snapshot + [b419cb82228f] + + * src/ikbd.c: + In IKBD_SCI_Get_Line_RX, when an overrun happens try to process the + current unread TDR + [5288963622a0] + + * src/acia.c: + In ACIA_Write_TDR, don't prepare a new transfer if we're in idle + state, wait for next clock bit (fix the game USS John Young / FOF54) + [7350e5200bf5] + + * src/acia.c, src/ikbd.c: + In ACIA_Clock_RX, check for overrun after the last stop bit, not + after the last data bit + [ffa86562c108] + +2012-10-19 Nicolas Pomarede + + * src/acia.c: + Only prepare a new TX in ACIA if in idle state and TSR has not just + been loaded + [5a2ed5c116a5] + + * src/ikbd.c: + Improve IKBD's SCI : send buffered TDR over TX line and init SCI + during reset + [e1b5023a456d] + + * src/acia.c: + Fix IRQ bit after reading ACIA's RDR + [9cebc4db8d2c] + +2012-10-18 Nicolas Pomarede + + * src/acia.c: + Fix IRQ bit in ACIA_UpdateIRQ + [aaa7e52c10eb] + +2012-10-14 Nicolas Pomarede + + * src/acia.c, src/includes/acia.h, src/memorySnapShot.c: + Include ACIA data in the memory snapshot + [95667e47c2a9] + +2012-10-13 Nicolas Pomarede + + * src/acia.c, src/cycInt.c, src/includes/acia.h, + src/includes/cycInt.h: + In ACIA_Set_Line_IRQ_MFP, update MFP_GPIP and trigger an interrupt + [358c39356777] + +2012-10-12 Nicolas Pomarede + + * src/ikbd.c: + Complete ACIA TX->IKBD RX and pass RDR to the commands' emulation + layer + [8ff71ecabdc8] + + * src/acia.c: + Fix shifting in ACIA TSR and RSR + [ece860b369e1] + +2012-10-11 Nicolas Pomarede + + * src/ikbd.c: + Add support for the IKBD's Serial Communication Interface and handle + RX bit from the ACIA The SCI is similar to the ACIA, but with less + parameters. + [0c555439310e] + +2012-10-09 Nicolas Pomarede + + * src/acia.c, src/ikbd.c, src/includes/ikbd.h, src/main.c: + In IKBD_Init, connect the IKBD to the ACIA RX/TX lines + [a9a7b0498895] + +2012-10-08 Nicolas Pomarede + + * src/debug/log.c, src/debug/log.h: + Add 'acia' and 'ikbd' keyword for the traces + [e285f8c49158] + + * src/acia.c: + Typo + [85a6e5821e07] + +2012-10-07 Nicolas Pomarede + + * src/ioMemTabFalcon.c, src/ioMemTabST.c, src/ioMemTabSTE.c, + src/ioMemTabTT.c: + Change ioMemTab* to use the new IKBD ACIA's handler for $fffc00/02 + [fe9b09c68ae1] + + * src/acia.c, src/includes/acia.h: + Add read/write functions for the IKBD's ACIA at $fffc00/02 + [66c1af8c4b04] + + * src/main.c: + Call ACIA_Init from Main_Init + [207bdde675b9] + + * src/acia.c, src/includes/acia.h: + Make ACIA_Array an extern variable + [16cbcc30a30e] + + * src/acia.c: + More traces for ACIA's RX + [949b3e51e8e0] + + * src/acia.c, src/debug/log.h: + Add traces for the ACIA + [175ba1f68d47] + + * src/acia.c, src/includes/acia.h: + Add Set_Timers callback function in ACIA_STRUCT + [ffbdcb020150] + +2012-10-06 Nicolas Pomarede + + * src/acia.c, src/cycInt.c, src/includes/acia.h, + src/includes/cycInt.h: + Add ACIA_Start_InterruptHandler_IKBD to start a timer at the + expected baud rate + [d6fdec366ea3] + + * src/acia.c: + In ACIA_UpdateIRQ, complete the TX/RX conditions to set IRQ bit + [143f72339ac5] + +2012-10-04 Nicolas Pomarede + + * src/acia.c, src/includes/acia.h: + In ACIA, improve RTS and CTS handling + [0066fd64b356] + + * src/acia.c, src/includes/acia.h: + ACIA : add Init, Master Reset, CR handling, default callback + functions + [6c07e390dc2e] + +2012-09-29 Nicolas Pomarede + + * src/acia.c, src/includes/acia.h: + Initial version of the ACIA's RX process + [e1d52a7e8415] + +2012-09-28 Nicolas Pomarede + + * src/acia.c, src/includes/acia.h: + Initial version of the TX process + [46fc27c94ce9] + + * src/CMakeLists.txt: + Add acia.c + [20dac429131f] + +2012-10-29 Thomas Huth + + * src/cpu/cpummu030.c: + MMU030: Flush ATC during cold reset + [dab3dd4e3a38] + + * src/cpu/cpummu030.c, src/cpu/cpummu030.h, src/cpu/newcpu.c: + Sync'ed the MMU030 reset function with Previous + [79c2d80c6695] + +2012-10-27 Eero Tamminen + + * src/vdi.c: + fix debug output, AES intin/intout array sizes are in words + [8cadaf4fa795] + +2012-10-26 Eero Tamminen + + * doc/compatibility.html: + add adebug reloaded. sort TT/falcon utilities by name + [a4320ccb7ed2] + +2012-10-23 Thomas Huth + + * src/cpu/cpummu030.c, src/cpu/cpummu030.h, src/cpu/newcpu.c, + src/m68000.c: + MMU030: Disable translation after reset. Address translation of the + 68030 is automatically disabled during reset. Now TOS can reboot + again properly. + [f21cce8515d9] + +2012-10-23 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [7bebc3a31f9d] + + * src/debug/profile.c: + fix profiler assert + + One entry after profiler.size is allocated for counting invalid Pc + entries, getting those shouldn't assert. + [03e3437b8dac] + +2012-10-22 Thomas Huth + + * doc/compatibility.html: + Fixed the link for GEM-demo + [339681bed8ec] + +2012-10-22 Eero Tamminen + + * src/cpu/hatari-glue.c, src/debug/natfeats.c, src/debug/natfeats.h, + src/uae-cpu/hatari-glue.c: + bus error / priviledge exception when natfeats is used improperly + [4ba39af76d46] + +2012-10-21 Thomas Huth + + * doc/compatibility.html: + Added some DHS demos that require an FPU + [efba0c52654b] + +2012-10-20 Eero Tamminen + + * doc/todo.txt: + LMC1992/Microwire is done + [1321d493b6f2] + + * src/cpu/hatari-glue.c: + add VDI opcode check to WinUAE core similar to one in old UAE core + [c3e35edaae93] + + * src/cpu/hatari-glue.c, src/cpu/hatari-glue.h: + add natfeats support to WinUAE core (fixes its build) + [00753ff2f8fd] + + * doc/todo.txt: + update TODOs + [ffaebb1838cd] + +2012-10-20 Thomas Huth + + * src/hdc.c: + Fixed ACSI debug print statement + [8c66ab9ebad3] + + * doc/todo.txt: + Removed the TT special shifter modes from the TODO list + [15070741d6b1] + +2012-10-20 Eero Tamminen + + * doc/hatari.1, doc/manual.html, doc/release-notes.txt, + src/CMakeLists.txt, src/cart.c, src/configuration.c, + src/debug/CMakeLists.txt, src/debug/natfeats.c, + src/debug/natfeats.h, src/includes/configuration.h, + src/includes/m68000.h, src/options.c, src/uae-cpu/hatari-glue.c, src + /uae-cpu/hatari-glue.h: + support for basic Native Features and config/option to + enable/disable it + [50958d336a1a] + +2012-10-19 Eero Tamminen + + * doc/compatibility.html, doc/midi-linux.txt: + add more links to docs + [e43c5b34578d] + + * doc/release-notes.txt, src/vdi.c: + show string arguments in AES traces + [fe0320d25faa] + +2012-10-14 Thomas Huth + + * src/cpu/cpummu030.c, src/cpu/cpummu030.h: + MMU: Merged latest changes from Previous + [b48c787ef1b0] + + * src/ikbd.c: + Improved error checking in IKBD clock functions. localtime() and + mktime() can return error codes which should be checked. + [e91ff87020f5] + + * src/cpu/cpummu030.c: + MMU: PTEST must return the physical address of the descriptor, not + its content + [06e1bdcd4dea] + + * src/cpu/newcpu.c: + MMU: Fixed decoding of PLOAD and PFLUSH. + [35659b714fe8] + +2012-10-12 Thomas Huth + + * src/cpu/cpummu030.c, src/cpu/newcpu.c: + Implemented bus error stack frame for 68030 MMU mode + [07a1b76011a5] + +2012-10-11 Thomas Huth + + * src/gui-sdl/sdlgui.c: + Use unsigned char in text blitting function to avoid negative values + for characters >= 128 + [4c45c5a1e52f] + +2012-10-10 Thomas Huth + + * src/cpu/cpummu030.c: + MMU: Another bugfix for PTEST. Cleaning debugging output. Thanks to + Andreas Grabher for the patch. + [a77ac3870fad] + +2012-10-11 Eero Tamminen + + * python-ui/README: + improve python ui readme + [ffe4eb32057b] + + * doc/compatibility.html: + add xmoon, ats works only with old core + [fbdafca342e4] + +2012-10-10 Eero Tamminen + + * src/cpu/newcpu.c: + fix WinUAE CPU core write_log() debug output memory accesses + + use STMemory_Read* functions instead of get_long/get_byte functions + because latter are subject to memory bank access restrictions and + can trigger exceptions inside emulation. + [6d3b55e1b0e5] + + * doc/release-notes.txt: + add missing note for 1.6.2 release + [a5f8e687fc55] + +2012-10-05 Thomas Huth + + * src/cpu/cpummu030.c: + MMU: Minor fix for PTEST and debugging messages. Thanks to Andreas + Grabher for the patch. + [13c4c9530359] + +2012-10-04 Eero Tamminen + + * doc/compatibility.html: + improve DSP comments, add comments about FPU, add Sweety Things + [e9a1a4a887e7] + + * doc/emutos.txt: + update EmuTOS compatiblity list + [0700874bc3e4] + +2012-10-03 Thomas Huth + + * doc/release-notes.txt: + Added MMU030 to the release notes + [199b1a9135e8] + + * src/cpu/cpummu030.c: + Hack for using the MMU with our 'supervisor' SysMem. TOS places the + MMU tables at address 0x700 - and for this address our + implementation for SysMem currently always requires supervisor mode. + Thus to get the MMU code working again, it now temporarily switches + to supervisor mode. However, this is a hack and needs more + investigation on a real Falcon to see what's happening there. + [9d45b07de881] + + * src/cpu/cpummu030.c, src/cpu/cpummu030.h: + Improved function code handling for 68030 MMU. Thanks to Andreas + Grabher for the patch. + [3699a903ccd5] + +2012-09-27 Eero Tamminen + + * doc/manual.html: + note about GEMDOS emulation dir sorting + [3faa5ab1dfcf] + +2012-10-03 Nicolas Pomarede + + * doc/release-notes.txt: + Update release notes + [1c66cb06f047] + +2012-09-23 Eero Tamminen + + * doc/manual.html: + update file selector usage info in manual + [12c7adbc05d1] + +2012-09-22 Nicolas Pomarede + + * src/sound.c: + Use a 17 stage LFSR for the pseudo random noise generation (patch by + David Savinkoff) + [83ccf2853249] + +2012-09-21 Nicolas Pomarede + + * doc/release-notes.txt: + Update notes with fileselector's changes + [9ed2e2241470] + + * src/gui-sdl/dlgFileSelect.c: + In file selector, ensure scrollbar remains visible for large + directory (this is a dirty fix, in that case the last files of a + directory could still be difficult to reach using the mouse) + [87155424986a] + + * src/gui-sdl/dlgFileSelect.c: + Start from the previous Y position in the file selector when calling + SDLGui_FileSelect() + [fbb01995565e] + + * src/cpu/hatari-glue.c, src/uae-cpu/hatari-glue.c: + When the RESET instruction is called, we must also reset the MFP and + the FDC + [35c8f4ef893f] + +2012-09-20 Thomas Huth + + * doc/release-notes.txt, src/ikbd.c: + Fixed IKBD set-clock function for Captain Blood. Apparently we've + got to take care of the setting the "daylight saving time" field in + the tm structure. + [3d488c2a74b4] + +2012-09-17 Thomas Huth + + * src/gui-sdl/dlgSystem.c: + Removed the 040 from the MMU option + [0a976075cf93] + + * src/cpu/newcpu.c: + Use the right memory access functions in Exception_mmu + [a797561062b0] + + * src/cpu/newcpu.c: + Fixed the check for the MMU model. Thanks to Andreas Grabher for the + hint! + [4267d8f6063b] + +2012-09-13 Eero Tamminen + + * doc/release-notes.txt: + update release notes & fix typo + [a9cbfa43e337] + + * doc/hatari.1, doc/manual.html, src/configuration.c, src/gemdos.c, + src/includes/configuration.h, src/options.c: + add --gemdos-case option for forcing file name case + [242d3bdeada4] + + * doc/emutos.txt: + update emutos compat list + [a98c3ba0042b] + +2012-09-10 Thomas Huth + + * src/cpu/cpummu030.c: + Fixing limit check in MMU table search function. TOS 4.04 should now + be bootable. Big thanks to Andreas Grabher for the patch! + [07cd788b4fcb] + +2012-09-10 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [7737842efdfd] + + * src/gemdos.c: + give warning if dir or pathname exceeds 8+3 chars + [d1a2c4154d11] + +2012-09-09 Thomas Huth + + * src/cpu/newcpu.c: + Set BusErrorPC in new CPU core, too + [9bf0bd25dbde] + + * src/cpu/cpummu030.c, src/cpu/cpummu030.h: + Merged latest changes from Previous MMU branch + [095995a024a2] + + * src/tos.c: + Fixed the check for the MMU patch + [db8551602eec] + +2012-09-08 Thomas Huth + + * src/cpu/cpummu030.c: + Fixed the copyright statement + [2d79aa62d4a4] + + * src/cpu/newcpu.c: + Use the right m68k_run function when MMU is enabled + [b8c82046d4d4] + +2012-09-07 Thomas Huth + + * doc/authors.txt, src/options.c, src/tos.c: + Some more hacks needed for the 68030 MMU + [e0c7c12b16b7] + + * src/cpu/CMakeLists.txt, src/cpu/cpummu.h, src/cpu/cpummu030.c, + src/cpu/cpummu030.h, src/cpu/custom.c, src/cpu/gencpu.c, + src/cpu/mmu_common.h, src/cpu/newcpu.c, src/cpu/newcpu.h, + src/cpu/sysconfig.h: + Integrated the 68030 MMU (unfortunately it is not working yet) + [8521076211a3] + + * src/cpu/cpummu030.c, src/cpu/cpummu030.h: + Added the basic code for the 68030 MMU emulation (not integrated + yet). Thanks to Andreas Grabher for the code! + [f4bf564cc1d9] + + * src/cpu/fpp.c: + Silenced GCC 4.4 warnings about uninitialized variables + [33ef4e7de43a] + +2012-09-04 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [917e036ddf4e] + + * doc/emutos.txt: + update emutos debugging info + [1fcf3b88fa75] + + * src/debug/console.c: + xconout redirection handles characters with high bit set + + They seem to have high byte as 0xff, at least in Gulam, maybe due to + sign extension. + [264b71ac6c0c] + + * doc/emutos.txt: + couple of extra demos compatible with emutos + [15fe8e53e995] + + * doc/compatibility.html: + couple of extra links to compatibility list + [ab45e22f062b] + +2012-09-01 Thomas Huth + + * .hgignore: + Added conftypes.py to hgignore file + [7af4dc590813] + + * Visual.Studio/VisualStudioFix.c, Visual.Studio/VisualStudioFix.h, + src/audio.c, src/avi_record.c, src/bios.c, src/blitter.c, + src/cart.c, src/cartData.c, src/change.c, src/clocks_timings.c, + src/configuration.c, src/control.c, src/convert/high640x8.c, + src/convert/low320x16.c, src/convert/low320x16_spec.c, + src/convert/low320x32.c, src/convert/low320x32_spec.c, + src/convert/low320x8.c, src/convert/low640x16.c, + src/convert/low640x16_spec.c, src/convert/low640x32.c, + src/convert/low640x32_spec.c, src/convert/low640x8.c, + src/convert/macros.h, src/convert/med640x16.c, + src/convert/med640x16_spec.c, src/convert/med640x32.c, + src/convert/med640x32_spec.c, src/convert/med640x8.c, + src/convert/routines.h, src/convert/vdi16.c, src/convert/vdi2.c, + src/convert/vdi4.c, src/cpu/compat.h, src/cpu/hatari-glue.c, src/cpu + /hatari-glue.h, src/cpu/maccess.h, src/cpu/memory.c, + src/cpu/memory.h, src/cpu/options_cpu.h, src/cpu/sysconfig.h, + src/createBlankImage.c, src/cycInt.c, src/cycles.c, + src/debug/68kDisass.c, src/debug/68kDisass.h, src/debug/breakcond.c, + src/debug/breakcond.h, src/debug/console.c, src/debug/console.h, + src/debug/debugInfo.c, src/debug/debugInfo.h, + src/debug/debug_priv.h, src/debug/debugcpu.c, src/debug/debugcpu.h, + src/debug/debugdsp.c, src/debug/debugdsp.h, src/debug/debugui.c, + src/debug/debugui.h, src/debug/evaluate.c, src/debug/evaluate.h, + src/debug/history.c, src/debug/history.h, src/debug/log.c, + src/debug/log.h, src/debug/profile.c, src/debug/profile.h, + src/debug/symbols.c, src/debug/symbols.h, src/dialog.c, src/dim.c, + src/dmaSnd.c, src/falcon/crossbar.c, src/falcon/crossbar.h, + src/falcon/hostscreen.c, src/falcon/hostscreen.h, + src/falcon/microphone.c, src/falcon/microphone.h, + src/falcon/nvram.c, src/falcon/nvram.h, src/falcon/videl.c, + src/falcon/videl.h, src/fdc.c, src/file.c, src/floppy.c, + src/gemdos.c, src/gui-osx/AlertHooks.h, src/gui-osx/AlertHooks.m, + src/gui-osx/CreateFloppyController.h, src/gui- + osx/CreateFloppyController.m, src/gui-osx/PrefsController.h, src + /gui-osx/PrefsController.m, src/gui-osx/Shared.h, src/gui- + osx/Shared.m, src/gui-sdl/dlgAbout.c, src/gui-sdl/dlgDevice.c, src + /gui-sdl/dlgFileSelect.c, src/gui-sdl/dlgFloppy.c, src/gui- + sdl/dlgHardDisk.c, src/gui-sdl/dlgJoystick.c, src/gui- + sdl/dlgKeyboard.c, src/gui-sdl/dlgMain.c, src/gui-sdl/dlgMemory.c, + src/gui-sdl/dlgNewDisk.c, src/gui-sdl/dlgRom.c, src/gui- + sdl/dlgScreen.c, src/gui-sdl/dlgSound.c, src/gui-sdl/dlgSystem.c, + src/gui-sdl/sdlgui.c, src/gui-win/opencon.c, src/hd6301_cpu.c, + src/hd6301_cpu.h, src/hdc.c, src/ide.c, src/ikbd.c, + src/includes/audio.h, src/includes/avi_record.h, + src/includes/blitter.h, src/includes/cart.h, src/includes/change.h, + src/includes/clocks_timings.h, src/includes/configuration.h, + src/includes/control.h, src/includes/createBlankImage.h, + src/includes/cycInt.h, src/includes/cycles.h, src/includes/dialog.h, + src/includes/dim.h, src/includes/dmaSnd.h, src/includes/fdc.h, + src/includes/file.h, src/includes/floppy.h, src/includes/gemdos.h, + src/includes/gemdos_defines.h, src/includes/hdc.h, + src/includes/ide.h, src/includes/ikbd.h, src/includes/ioMem.h, + src/includes/ioMemTables.h, src/includes/joy.h, + src/includes/keymap.h, src/includes/m68000.h, src/includes/main.h, + src/includes/memorySnapShot.h, src/includes/mfp.h, + src/includes/midi.h, src/includes/msa.h, src/includes/options.h, + src/includes/paths.h, src/includes/pixel_convert.h, + src/includes/psg.h, src/includes/reset.h, src/includes/resolution.h, + src/includes/rs232.h, src/includes/rtc.h, src/includes/scandir.h, + src/includes/screen.h, src/includes/screenSnapShot.h, + src/includes/sdlgui.h, src/includes/shortcut.h, + src/includes/sound.h, src/includes/spec512.h, src/includes/st.h, + src/includes/stMemory.h, src/includes/statusbar.h, + src/includes/str.h, src/includes/tos.h, src/includes/utils.h, + src/includes/vdi.h, src/includes/video.h, src/includes/wavFormat.h, + src/includes/xbios.h, src/includes/ymFormat.h, src/includes/zip.h, + src/ioMem.c, src/ioMemTabFalcon.c, src/ioMemTabST.c, + src/ioMemTabSTE.c, src/ioMemTabTT.c, src/joy.c, src/keymap.c, + src/m68000.c, src/main.c, src/memorySnapShot.c, src/mfp.c, + src/midi.c, src/msa.c, src/options.c, src/paths.c, src/printer.c, + src/psg.c, src/reset.c, src/resolution.c, src/rs232.c, src/rtc.c, + src/scandir.c, src/screen.c, src/screenSnapShot.c, src/shortcut.c, + src/sound.c, src/spec512.c, src/st.c, src/stMemory.c, + src/statusbar.c, src/str.c, src/tos.c, src/uae-cpu/build68k.c, src + /uae-cpu/fpp.c, src/uae-cpu/gencpu.c, src/uae-cpu/hatari-glue.c, src + /uae-cpu/hatari-glue.h, src/uae-cpu/maccess.h, src/uae-cpu/memory.c, + src/uae-cpu/memory.h, src/uae-cpu/newcpu.c, src/uae-cpu/newcpu.h, + src/uae-cpu/options_cpu.h, src/uae-cpu/readcpu.c, src/uae- + cpu/readcpu.h, src/uae-cpu/sysdeps.h, src/utils.c, src/vdi.c, + src/video.c, src/wavFormat.c, src/xbios.c, src/ymFormat.c, + src/zip.c, tests/tosboot/disk/common.c, tests/tosboot/disk/common.h, + tests/tosboot/disk/gemdos.c, tests/tosboot/disk/minimal.c, + tools/hmsa/floppy.c, tools/hmsa/floppy.h, tools/hmsa/hmsa.c, + tools/hmsa/hmsa.h: + Replaced 'GNU Public License' with the correct 'GNU General Public + License'. Thanks to Teemu Hukkanen for the hint! + [e39f2ac97eb5] + +2012-08-18 Eero Tamminen + + * src/vdi.c: + add intin array info to AES function traces + [4a8eeaa12138] + +2012-07-29 Eero Tamminen + + * tests/tosboot/disk/ahcc-gemdos, tests/tosboot/disk/ahcc-minimal, + tools/hconsole/example-commands, tools/hconsole/hconsole.py: + add "--conout 2" to Hatari remote API usage + [9c996dcf4338] + + * doc/manual.html: + add --conout to manual + [7736a22fe593] + + * doc/hatari.1: + fix typo + [a5f84db3b84f] + + * doc/emutos.txt: + emutos doc updates + [fd70815b9f3d] + + * src/options.c, src/resolution.c: + output what value was set by options if it's not otherwise shown by + UI + + CPU level etc are shown in statusbar and window size is visible + there too, but for several other options there's no feedback whether + Hatari got correct values. + + This is important because their values are typically parsed with + atoi(), but that stops parsing at first unrecognized value (e.g. 0x2 + is interpreted as 0). + + I noticed this when testing expression evaluation with debugger + "setopt" command, "1+1" yields "$2" which is interpreted as 0... + [82f318fac54d] + + * src/bios.c: + fix Bios trace args parsing and be more verbose about Bios Setexe() + args + [cb56a1f6103e] + + * src/debug/debugui.c: + fix illegal memory access in previous expression evaluation fix + + If none of given chars is found, strcspn() seems to return string + len, not zero, this was undocumented in its the manual page. + [ec2687b79c82] + +2012-07-26 Eero Tamminen + + * tests/debugger/makefile, tests/debugger/test-dummies.c: + fix broken debugger test building + + - add config.h and history.c for makefile + - added needed extra fake stuff to test-dummies + [afdfe859e066] + + * tests/debugger/test-breakcond.c, tests/debugger/test-evaluate.c: + improved test comment + [4ba906589f74] + +2012-07-22 Eero Tamminen + + * doc/release-notes.txt: + add --conout to release notes + [cd248423871e] + + * src/debug/console.c, src/options.c: + improved option descriptions + [fe4db7ac4562] + + * doc/hatari.1, src/bios.c, src/debug/CMakeLists.txt, + src/debug/console.c, src/debug/console.h, src/debug/debugcpu.c, + src/includes/options.h, src/options.c: + Much improved console output re-direction support + + - Instead of catching redirected bconout() BIOS function, catch + calls to xcounout vector function directly as this will catch also + EmuTOS panic and MiNT console messages, not just TOS Bios calls. + + - Add separate --conout Hatari command line option and internal + (non-configurable) ConOutDevice variable for this. + + - Move VT52 emulation and other relevant functionality from bios.c + to new console.[ch]file and enable/call this in/from debugcpu.c + when a ConOutDevice is specified by user. + [0388a39cc923] + + * doc/authors.txt, doc/release-notes.txt: + update authors & release notes + [0b5eabe36557] + + * src/control.c, src/debug/debugui.c, src/debug/debugui.h: + Debugger expression evaluation improvements + + - Fix: expression expansion doesn't mess lines in command line + history, expression evaluation always allocs new buffer + + - Rename DebugUI_RemoteParse() to more apt DebugUI_ParseLine(), as + it can be used also internally in Hatari (mainly when temporarily + asking Hatari C-code to output disassembly etc output with + debugger at appropriate points) + + - Support expression expansion also in DebugUI_ParseLine(). + -> means that they can be used also through the control socket, + not just when using Hatari directly + + - Either single or double quotes can be used to mark expressions + (as quoting double quotes from C-code is pain) + [2de215cbb3af] + +2012-07-22 Thomas Huth + + * doc/compatibility.html: + Converted the compatibility list to HTML 4.01 Strict + [7c42145da62c] + + * doc/manual.html: + Sync'ed the parameter list with the manual, using the latest version + of groff which generates somewhat better HTML than the version we + used in the past (no more ugly HTML tables here). Also fixed some + more transitional HTML so that the manual is now "HTML 4.01 Strict". + [832fda8e31f7] + +2012-07-21 Thomas Huth + + * doc/compatibility.html, doc/manual.html, doc/toc.js: + Switched to a better TOC script and fixed internal links. + [c2f5c1a30a07] + +2012-07-20 Eero Tamminen + + * src/statusbar.c: + fix titlebar max message len ("REC" text got overdrawn with low res + no-borders) + [4bf3634f7160] + + * src/CMakeLists.txt: + fix comment typos + [13e7758592b2] + +2012-07-20 Thomas Huth + + * doc/compatibility.html, doc/manual.html, doc/toc.js, doc/update- + index.sh: + The index of the HTML documentation is now generated via a small + JavaScript program. This way the index is always up-to-date, and we + get rid of the old-fashioned named anchors in the HTML files. + [72e48df295c7] + +2012-07-17 Thomas Huth + + * src/video.c: + Save new TT video settings to memory snapshots, too. Thanks to + Cyprian Konador for the patch! + [e7ac16e1aec0] + +2012-07-14 Thomas Huth + + * src/falcon/videl.c, src/memorySnapShot.c: + Fixed crash in Videl mode when loading memory snapshots. The + videl_zoom structure must _not_ be saved, it contains malloc'ed + pointers that became invalid when loading a snapshot. The + information in this structure is regenerated during a resolution + switch anyway, so we can simply omit it from the snapshots. + [34c01e9910bc] + + * src/falcon/videl.c, src/includes/screen.h, src/video.c: + Improved TT video emulation. + - Extend the ST palette registers from 9bit to 12bit for ST modes + - Duochrome mode instead monochrome for ST High; + - Implementation of TT SampleHold i TT Hypermono video mode Thanks to + Cyprian Konador for the patch! + [5ae66837962d] + +2012-06-24 : *** Version 1.6.2 *** + +2012-06-24 Nicolas Pomarede + + * doc/compatibility.html, doc/doxygen/Doxyfile, doc/emutos.txt, + doc/manual.html, doc/release-notes.txt, doc/todo.txt, hatari.spec, + readme.txt, src/gui-osx/English.lproj/InfoPlist.strings, src/gui- + osx/French.lproj/InfoPlist.strings, src/gui-osx/Info-Hatari.plist, + src/includes/main.h: + New release 1.6.2, increase version in corresponding files + [84390a6f7417] [tip] + +2012-06-23 Nicolas Pomarede + + * src/debug/breakcond.c, tests/debugger/test-dummies.c: + typo AUE -> UAE + [a7ec17bc2684] + +2012-06-21 Eero Tamminen + + * doc/emutos.txt: + update comments to v0.8.7 release + [13f27005ff37] + +2012-06-19 Eero Tamminen + + * src/gui-sdl/dlgFileSelect.c: + fix potential double cursor on file selector errors + + (when it's called directly from keyboard shortcut, not from options + dialog) + [c36a1c3cbfe1] + + * doc/release-notes.txt, src/gui-sdl/dlgMain.c: + fix double mouse pointer on snashot restore + + Thanks to Charlie Nolan for notifying about the issue and pointing + out where the bug is! + [e07eea78ad20] + +2012-06-17 Nicolas Pomarede + + * src/sound.c: + Improve YM2149's output with an anti-alias piecewise selective + filter (patch by David Savinkoff) + [65243a46bf4d] + +2012-06-16 Eero Tamminen + + * readme.txt: + add (build verification) note about TOS tester to readme + [dffd611d2de7] + + * tests/tosboot/bootauto.st.gz, tests/tosboot/bootdesk.st.gz, + tests/tosboot/disk/GEMDOS.PRG, tests/tosboot/disk/MINIMAL.PRG, + tests/tosboot/disk/common.c, tests/tosboot/tos_tester.py: + make sure all tester output gets to screen before screenshot + [3859ba93e9f0] + +2012-06-10 Nicolas Pomarede + + * doc/images/sound.png, doc/manual.html, doc/release-notes.txt: + Update release notes and manual with --sound-sync option + [426af0760de1] + + * doc/hatari.1, doc/manual.html, src/audio.c, src/configuration.c, src + /gui-sdl/dlgSound.c, src/includes/audio.h, + src/includes/configuration.h, src/main.c, src/options.c: + Add --sound-sync option to synchronize video with OS audio if needed + (patch by David Savinkoff) In case your OS audio's driver has some + latency issues, this option can help keeping video and audio + synchronized by speeding up or slowing down video emulation by very + small amounts of microseconds. + [0c0d05fc9480] + +2012-06-09 Nicolas Pomarede + + * doc/todo.txt: + For the todo : possible crashes with dma sound are only in Falcon + mode, not STE. + [ca7b99d807f7] + +2012-06-09 Thomas Huth + + * src/cpu/newcpu.c, src/cpu/sysdeps.h: + Fix cycle-exact counting in WinUAE CPU mode + [77967f0f9102] + +2012-06-09 Eero Tamminen + + * doc/manual.html: + update features list + [cf3679648104] + + * doc/todo.txt: + todo note about DMA segfault + [a7e8f429a978] + + * src/debug/symbols.c: + accept "." in symbol names[1], tell addresses on multiple matches + + [1] useful when symbol list contains also object file names + [74c4a402c2c3] + + * tests/tosboot/bootauto.st.gz, tests/tosboot/bootdesk.st.gz, + tests/tosboot/disk/GEMDOS.PRG, tests/tosboot/disk/MINIMAL.PRG: + update test binaries correspondingly + [e893a3129213] + + * tests/tosboot/disk/common.c, tests/tosboot/disk/common.h, + tests/tosboot/disk/gemdos.c, tests/tosboot/disk/minimal.c: + wait for Enter, not any key + + Otherwise (space) keypress TOS tester uses to dismiss startup memory + check can dismiss the test program when fast-forward is being used. + [f32f0e185eec] + + * tests/tosboot/readme.txt: + update TOS tester readme + [0eb24ca73a50] + +2012-06-06 Eero Tamminen + + * doc/compatibility.html, doc/release-notes.txt, doc/todo.txt: + add misc missing items from mailing list to docs + [6cb54e08e04e] + + * src/configuration.c: + enable cycle exact by default for WinUAE + + user typically doesn't have this on his hatari config, and without + this it would get eventually saved as false, which would be pretty + bad for Falcon compatibility... + [9649e5cea16f] + + * src/includes/unzip.h: + remove the silly OF macros from unzip.h + [c5da2828cefd] + +2012-06-05 Eero Tamminen + + * doc/release-notes.txt: + release notes update: + + - split DSP/WinUAE/oldCore changes + - formatting improvements + - add couple of new items + [e66232c46ca7] + + * src/options.c, src/tos.c: + WinUAE: when machine type changes, set FPU for TT, disable it for + others + + Set also 24-bit addressing and disable 040 MMU when ST/STE/TT/Falcon + machine type is set. + [7336d2d8fb72] + + * src/change.c: + reset emulation if FPU type changes + [df7a2400f845] + + * src/configuration.c: + default to Falcon with WinUAE, old CPU still defaults to ST + [95f03eda407e] + +2012-06-04 Eero Tamminen + + * tests/tosboot/tos_tester.py: + test also (one) VDI mode + [a312e1bc0937] + +2012-05-31 Eero Tamminen + + * tests/tosboot/tos_tester.py: + update tester checks as latest emutos snapshot fixed serial output + [f8b7da6c61de] + +2012-06-04 Thomas Huth + + * src/cpu/hatari-glue.c, src/cpu/newcpu.c, src/cpu/newcpu.h: + Fixed Hatari's illegal opcodes in WinUAE mode + [5b749a42805d] + +2012-05-31 Thomas Huth + + * CMakeLists.txt: + Abort build-configuration when zlib is missing + [080d65ac4659] + +2012-05-30 Eero Tamminen + + * tools/zip2st.1, tools/zip2st.sh: + skip intermediate dirs in zip2st + [00ff7f1f17b6] + + * tools/hmsa/hmsa.c: + only last . in extension name should matter for hmsa + [0644105db272] + +2012-05-28 Eero Tamminen + + * src/includes/configuration.h: + fix FPU type values (patch from Previous emulator) + [6ccc4727441f] + + * src/gemdos.c: + show drive mask with "info gemdos" + [06bf8c690bed] + +2012-05-28 Nicolas Pomarede + + * doc/release-notes.txt: + Reorder changes into groups + [b92c56fbca4e] + + * src/dmaSnd.c, src/sound.c: + On STE, make DMA sound's volume louder compared to YM2149's volume + (patch by David Savinkoff) + [34b3666bd4c8] + +2012-05-28 Thomas Huth + + * src/cpu/custom.c, src/cpu/newcpu.c: + Hacked the plain 68000 modes of the WinUAE core to work with Hatari, + too + [a941332bd17b] + + * src/cpu/cpummu.c, src/cpu/gencpu.c, src/cpu/memory.h, + src/cpu/newcpu.c: + Fixed compiler warnings + [fc374d482642] + + * src/m68000.c: + Fix for GEMDOS HD not working anymore when changing WinUAE CPU + level. The currprefs.cpu_level variable was not updated in WinUAE + mode, causing GemDOS_OpCode() to read the wrong parameters from the + stack. + [4c9d176dbc37] + +2012-05-28 Nicolas Pomarede + + * src/dmaSnd.c: + Don't output any sound when LMC mixing is set to DMA, but DMA is OFF + (patch by David Savinkoff) + [f18ffd270c98] + +2012-05-27 Nicolas Pomarede + + * doc/authors.txt: + Add more items to David Savinkoff's list of contribution + [08974ef4b727] + + * src/sound.c: + Add comments describing the filtering at the output of the YM2149 + [75cfad140461] + +2012-05-26 Nicolas Pomarede + + * src/sound.c: + Better model when samples are played using "Quartet mode" (patch by + David Savinkoff) In "Quartet Mode", samples are played by modulating + the volume of the 3 YM2149 voices after setting the period to 0 and + enabling tones on the 3 voices. + [1ae3882984ca] + +2012-05-25 Thomas Huth + + * src/cpu/cpu_prefetch.h, src/cpu/cpummu.c, src/cpu/cpummu.h, + src/cpu/gencpu.c, src/cpu/m68k.h, src/cpu/newcpu.c, + src/cpu/newcpu.h, src/cpu/sysconfig.h: + Changed CR-LF line endings to normal LF mode + [3340674305cb] + + * src/cpu/custom.c, src/cpu/custom.h, src/cpu/events.h, + src/cpu/events_jit.h, src/cpu/events_normal.h, src/cpu/rpt.h: + Removed/disabled some unused code + [74f3e837b511] + +2012-05-23 Eero Tamminen + + * tests/tosboot/disk/common.c: + fix test variable name + [5340f289e88c] + +2012-05-22 Eero Tamminen + + * tests/tosboot/tos_tester.py: + 512kB isn't valid memsize to test for Falcon/TT + [5962562d2f49] + + * python-ui/dialogs.py, python-ui/hatari.py, python-ui/release- + notes.txt: + python GUI support for --desktop-st and --force-max + [90395a13fe6e] + + * python-ui/README: + fix path comment + [5ab09a1ca6a8] + +2012-05-21 Eero Tamminen + + * python-ui/dialogs.py, src/gui-sdl/dlgScreen.c, src/gui- + sdl/dlgSystem.c: + update gui strings + [8700e4f0a095] + + * tests/tosboot/tos_tester.py: + add tester TODO + [3dcb45c12e68] + + * doc/release-notes.txt: + update release notes + [8424fdd93df5] + + * tools/hatari-local-midi-ring.sh: + fix script arg parsing + [3f7d4a13b0ea] + +2012-05-20 Eero Tamminen + + * tests/tosboot/disk/TEXT, tests/tosboot/disk/gemdos.c, + tests/tosboot/tos_tester.py: + check either serial or printer output depending on TOS version + add + fast option + + Printer doesn't work for autostarted programs with some normal TOS + version whereas serial works for all normal TOS versions, but not + for EmuTOS. So added serial support and checking different device + output based on TOS version. + + Added --fast option to run tests faster. If there are failures, one + should check them without that (i.e. --fastfdc/--fast-forward). + + Fix to cleanup device output files before running next test. Old + files were causing some fails. + [e614612d5543] + + * tests/tosboot/bootauto.st.gz, tests/tosboot/bootdesk.st.gz, + tests/tosboot/disk/GEMDOS.PRG, tests/tosboot/disk/MINIMAL.PRG: + update test binaries accordingly + [cd5254e62550] + + * tests/tosboot/disk/common.c, tests/tosboot/disk/common.h, + tests/tosboot/disk/gemdos.c, tests/tosboot/disk/minimal.c: + add console and serial output testing + [6bb6a6d9d966] + + * tests/tosboot/readme.txt: + minor tos-tester readme improvements + [351618263bc9] + + * doc/todo.txt: + add note about TOS startup printer issue + trivial text improvements + [b4a5c8971302] + + * src/change.c, src/includes/rs232.h, src/rs232.c: + allow just one of RS232 directions to be configured + + This is similar to the other devices and allows disabling device by + giving empty path. + + With this, we need to create the RS232 input thread (which + redundantly wakes up at 5Hz interval) only if RS232 input is + actually configured in. + + Removed (now) redundant bConnectedRS232 variable. + [7e01cbc6c2c9] + + * tools/hatari-local-rs232.sh: + fix rs232 script arg passing and show hatari path + [99fc2dacb6b5] + +2012-05-19 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Update docs with 'The Musical Wonders 1990' by Offbeat + [63aabf41135a] + + * src/video.c: + Allow bottom border to be removed when switch back to 50 Hz is made + at cycle 504 (fix 'Musical Wonders 1990' by Offbeat) + [941912e2e872] + + * src/video.c: + Fix a potential wrong border removal when freq switch was at cycle + 512/0 + [a2b5d438fd4e] + +2012-05-18 Eero Tamminen + + * src/xbios.c: + fix Devconnect trace arg, add args for more DSP and palette XBios + call traces + [6d08a3d50c34] + + * doc/emutos.txt: + more info on debugging + other doc improvements + [0ca5bffa065b] + + * doc/emutos.txt: + reason for Cubase crash from Vincent + [424184e995c7] + + * doc/emutos.txt: + update for latest emutos CVS snapshot state + [aa64c85aa6be] + + * doc/compatibility.html: + bragg256 doesn't anymore work with TT emu + [6f1445443b19] + +2012-05-17 Eero Tamminen + + * doc/release-notes.txt: + add note about videl borders + [9829f168f45b] + + * doc/midi-linux.txt: + correct midi option name + [f95069503e49] + +2012-05-11 Thomas Huth + + * src/video.c: + Removed the redundant VideoShifterByte variable + [c6258e39d861] + + * doc/release-notes.txt, src/ikbd.c, src/memorySnapShot.c: + Implemented IKBD set-clock function (fixes the game 'Zombi') + [666085b99271] + +2012-05-08 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Update release notes for The Wave Of the Future by ICE and + Electrocution I by Sphere + [7b8d44ea6076] + + * src/cycles.c: + For BCLR/BSET/BCHG, the write is effective at the end of the + instruction, not 4 cycles before like MOVE (fix bclr/bset #1,$ff820a + used for bottom border removal in Electrocution I by Sphere in Stax + Menu 66 and top border removal in The Wave Of The Future by ICE) + [ab6c12ce3253] + +2012-05-05 Nicolas Pomarede + + * doc/release-notes.txt: + Typo + [e576d359ead0] + + * doc/release-notes.txt: + Update release notes for JMP with illegal address exception + [714d109e08d4] + + * src/uae-cpu/gencpu.c: + Fix return PC when JMP generates an illegal address exception (fix + Sherman Cracktro by The Ivisibles in No Extra V2 compilation) + [c88d85808e2e] + +2012-04-16 Eero Tamminen + + * doc/emutos.txt: + update emutos compatilibity to latest CVS snapshot state + [04da9da24462] + + * doc/compatibility.html: + add gemdemo url + [8501a44a9071] + +2012-04-09 Nicolas Pomarede + + * src/includes/ym2149_fixed_vol.h, src/sound.c: + For the volumes table [32][32][32] uses geometric mean interpolation + (patch by David Savinkoff) Also fix a possible overflow when + building the linear mixing table. + [28e1fec33c79] + +2012-04-07 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Add 'Antiques' by Dune/Sector One to the docs + [4b6cd4e92fdc] + +2012-03-28 Nicolas Pomarede + + * doc/release-notes.txt: + Update video changes for STE overscan + [b50bd7f1194a] + +2012-03-27 Thomas Huth + + * src/ioMemTabTT.c: + 0xff8783 should rather return 0 instead of 0xff. Thanks to Uwe + Seimet for the hint. + [55a80bd4b855] + +2012-03-27 Laurent Sallafranque + + * src/falcon/videl.c: + fix: videl borders can be negative. In this case, I fix them to 0 + [f1f5e40ef7dc] + +2012-03-28 Nicolas Pomarede + + * src/video.c: + On STE, hi/lo switch at cycles 508/4 is also adding 20 bytes to left + border The switches at pos 504/4 and 508/4 are both giving 20 bytes + more in the left border and a total of 224 bytes for an overscan + line without stabilizer (instead of the usual 230 bytes with + stabilizer on STF/STE) + [cd9ff82e11a4] + +2012-03-25 Eero Tamminen + + * doc/manual.html: + improve manual's debugger & perf section texts a bit + [b2305af6d946] + +2012-03-17 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [b57dd4f9eabb] + + * src/change.c, src/includes/printer.h, src/printer.c: + remove double buffering from printer output + + simplified the code by removing the buffering code in Hatari and + relying on C-library FILE buffering, which can easily be disabled + with setvbuf(fp, NULL, _IONBF, 0); + + handle output file similarly to midi & rs232, allow disabling it by + setting filename empty in Hatari command line. + [4fdb81e989c8] + +2012-03-15 Nicolas Pomarede + + * doc/release-notes.txt: + Update release notes with Delirious Demos IV + [d47f6ea98dea] + +2012-03-13 Nicolas Pomarede + + * doc/compatibility.html: + Update notes for the Delirious Demos IV + [7b65acb88010] + + * src/video.c: + On STE when writing to video address hi byte $ff8205, the value is + masked with $3f (fix STE detection in the Delirious Demo IV) + [73a4e06e5b7c] + +2012-03-11 Eero Tamminen + + * src/bios.c, src/debug/log.c, src/xbios.c: + fix warnings & errors when tracing is disabled + [357c9f49ad7b] + + * src/debug/68kDisass.c: + const offset variables to remove compiler warning from disassember + + (apparently then gcc can verify that array offsets are valid) + [11e73a29f8fb] + +2012-03-09 Laurent Sallafranque + + * src/falcon/videl.c: + fix TT rendering. + [e4412685ff0c] + +2012-03-08 Eero Tamminen + + * src/statusbar.c: + more debug/backtrace support to find out what things are telling + statusbar conflicting info on screen size + [8d28b0f3124c] + +2012-03-07 Laurent Sallafranque + + * src/falcon/videl.c: + fix a bug when displaying true color 40 colums and switching from + borders to no borders. + [1bf31f9f68e8] + +2012-03-07 Thomas Huth + + * src/cpu/fpp.c, src/uae-cpu/fpp.c: + Fixed format string for long doubles. + [6c9f5bca4cae] + + * src/bios.c, src/xbios.c: + Fixed compiler warnings. Clang complained about bad format + parameters. + [42931ca96f0c] + +2012-03-07 Laurent Sallafranque + + * src/falcon/videl.c: + fix left/right borders. This seems correct except for ST Low and med + res. + [9737e7bade6f] + + * src/falcon/videl.c, src/falcon/videl.h, src/ioMemTabFalcon.c, + src/video.c: + Move all IOmem Falcon registers into Videl + code cleaning. + [22d3c9f30097] + +2012-03-05 Laurent Sallafranque + + * src/cpu/falcon_cycle030.h, src/cpu/table68k: + MMU patch for Motorola undocumented MMU instructions. Thanks to + Andreas for the patch. + [f96e0cfe4c43] + + * src/cpu/md-fpp.h: + fix to_exten code. Thanks to Andreas for the patch. + [e644515445ae] + +2012-03-04 Eero Tamminen + + * doc/manual.html, doc/release-notes.txt: + update release notes and manual in regards to debugging improvements + [14ec78d97dd0] + + * src/falcon/dsp.c, src/falcon/dsp.h, src/falcon/dsp_cpu.c, + src/falcon/dsp_cpu.h, src/falcon/dsp_disasm.c: + DSP PC is 16-bit, propagate it and instruction len as such when + disassembling + [d9a5b4d00c64] + + * src/debug/debugdsp.c, src/falcon/dsp_disasm.c: + move DSP profile output to end of disassembly instead of its own + line + + This way it's more readable and dsp_symbols trace works ok with + profiling data + [f2fccbb456c9] + + * src/debug/68kDisass.c, src/debug/debugcpu.c: + move profile output to end of disassembly instead of its own line + + The result is much more readable and with this dsp_symbols trace + works correctly also when profiling is enabled. + [f8cfd15f0bd9] + +2012-03-04 Nicolas Pomarede + + * doc/release-notes.txt: + Update release notes with FDC changes + [0811192a2361] + +2012-03-04 Eero Tamminen + + * src/bios.c, src/debug/debugInfo.c, src/includes/bios.h, + src/includes/xbios.h, src/xbios.c: + add "info" command opcode table otputs for BIOS & XBIOS too + + (gemdos, vdi & aes already had those.) + [79c36bc180df] + + * src/gemdos.c: + remove ifdeffed gemdos code and add hex opcodes to remaining trace + output + + - the code has been ifdeffed out for years, it's time for it to go + - all gemdos, bios and xbios calls traces show now hex opcodes, + similarly to the "info" command opcode tables + [8745c01c2717] + + * src/gemdos.c: + show args for all gemdos calls with none, word or long arg, as hex + [92c146e4b0fc] + + * src/xbios.c: + show args for most XBIOS calls when tracing + refactoring: + - do Params+=SIZE_WORD once in caller instead of everywhere + - instead of build time XBIOS_DEBUG, do same with run-time tracing + - show opcodes as hex + + Full call signature is shown for all XBios functions that take + either: + - no args + - single word + - single long/pointer + - two words + [8d35a4b59922] + + * src/bios.c: + show args for all BIOS functions when tracing + refactoring: + - +=SIZE_WORD is done in caller, once + - everything returns false, so do it only in caller + - show opcodes as hex + [4cebf4f74d12] + + * doc/emutos.txt: + update EmuTOS STE/Falcon compatibility for CVS version 20120301 + [1e213ce33af9] + +2012-03-04 Nicolas Pomarede + + * src/psg.c: + After a reset, there should be no drive selected FDC commands after + a reset are supposed to be ignored until a drive is selected, for + example we should ignore the 'step without update' command 0x20 in + the middle of the 'Rising Force' demo (buggy loader) (fix 'Rising + Force' by Holocaust) + [93cf6e440bf9] + + * src/fdc.c: + Print logical track and physical track in FDC traces + [399b1457081e] + + * src/fdc.c: + When no drive is selected, we should ignore FDC type I, II and III + commands Hatari previously defaulted to drive A: in that case, which + was wrong as seen with the 'Step without update' command used in + Japtro's loader. (fix 'Japtro' by Holocaust) + [f0dd0e53981a] + +2012-03-03 Laurent Sallafranque + + * src/falcon/videl.c: + add correct values for left/right borders. + [51510dd89a00] + +2012-03-03 Eero Tamminen + + * src/bios.c, src/xbios.c: + show in traces arg for all bios & xbios calls taking WORD arg + + - Doing this generically allows removing the separate functions + for that + - I changed also args in Rwabs() output to be in the order they're + in the that Bios() call, otherwise people don't know what the args + are without looking into Hatari code + - Add (visually aligned) call opcode to all bios&xbios trace outputs + [b2f3384406d2] + + * doc/compatibility.html, doc/emutos.txt: + update EmuTOS notes based on latest 20120301 CVS snapshot + [db55a21ee3be] + + * doc/compatibility.html: + fix notes on what falcon progs need + [5c699eb0dfd8] + +2012-02-28 Laurent Sallafranque + + * src/falcon/videl.c, src/falcon/videl.h, src/ioMemTabFalcon.c: + added register $ff820a to Videl. + [e31fccbd8947] + + * src/falcon/videl.c: + fix VIDEL borders display bug when displaying in fullscreen + add no + border with monochrome monitor. + [b989bc1c9f87] + +2012-02-27 Eero Tamminen + + * doc/manual.html, doc/release-notes.txt, doc/todo.txt, + src/debug/debugcpu.c, src/debug/debugdsp.c, src/debug/log.c, + src/debug/log.h: + add tracing of debugger (CPU & DSP) symbol addresses + + If you have symbol output for your program, this can be used e.g. to + get complete function trace for your program + [823f998c121a] + + * doc/compatibility.html: + typo + [01baf1548ad9] + +2012-02-26 Eero Tamminen + + * doc/compatibility.html: + update compatiblity according mails on hatari-devel 2/2012 + [5bb19c725a99] + +2012-02-26 Nicolas Pomarede + + * doc/release-notes.txt, src/ikbd.c: + Update release notes with ACIA TX IRQ + [0a241b3444e2] + + * src/ikbd.c: + Handle TX interrupt in the ACIA (eg by sendding 0xb6 instead of 0x96 + after resetting the ACIA) (fix the game 'Hades Nebula') + [accdc01d11b4] + +2012-02-24 Laurent Sallafranque + + * src/falcon/videl.c: + VIDEL: all borders are optimized now. + [0d47e40bdf08] + + * src/falcon/videl.c: + VIDEL: upper and lower borders optimisations in rendering zoom mode. + Still to optimize: left/right borders + [964ce681efcf] + +2012-02-23 Laurent Sallafranque + + * src/falcon/videl.c: + add left/right borders for the falcon + code optimized + + ConfigureParams.Screen.bAllowOverscan + [34160d3d5191] + +2012-02-23 Eero Tamminen + + * doc/authors.txt, doc/release-notes.txt: + update authors and release notes + [b3e12d0149ce] + + * src/debug/profile.c: + fix cycles profiling not to modify CPU state + [3cc8936a504d] + +2012-02-22 Laurent Sallafranque + + * src/falcon/videl.c: + code cleaning, warnings removed. + [faa81e9509f8] + +2012-02-21 Laurent Sallafranque + + * src/falcon/videl.c: + add upper and lower borders for VIDEL. + [39c21bc81d17] + +2012-02-20 Eero Tamminen + + * doc/compatibility.html: + Fungle Beats needs WinUAE + [b75097826a3c] + + * doc/emutos.txt: + update EmuTOS falcon demo compatibility list + add notes for falcon + games + [29bdd07e0a68] + +2012-02-19 Eero Tamminen + + * src/bios.c: + interpret Bios VT52 clearscreen+home escape code as newline + [05162b003e58] + + * src/xbios.c: + add XBios VsetMode tracing and convert rest of XBios debug output to + tracing + [f8b620524b03] + +2012-02-18 Eero Tamminen + + * doc/emutos.txt: + update EmuTOS falcon games & apps compatibility list + [b42f170e119b] + + * doc/compatibility.html: + update falcon apps compatibility + [dac5bcddc82f] + +2012-02-17 Eero Tamminen + + * doc/compatibility.html: + POV 136 comment + [9a97c614746f] + +2012-02-16 Eero Tamminen + + * doc/emutos.txt: + update EmuTOS compat for ST, add note about EmuTOS version + requirements + + For ST/STE emulation the 512kB version of EmuTOS shipped with Hatari + isn't the best alternative. E.g. Checksum/Equinox Protracker 2 STE + crashes with it while it works fine with 256kB version... + [94d26c4b07ad] + + * doc/emutos.txt: + update for latest EmuTOS CVS snapshot (with floppy fix) + more STE + updates + [c73797635c00] + +2012-02-15 Eero Tamminen + + * doc/emutos.txt: + update EmuTOS compat for STE + [1db1470fc413] + +2012-02-05 Laurent Sallafranque + + * src/reset.c: + fix: DSP was not resetted after a Reset. + [e9fa6df86f6a] + + * src/cpu/cpummu.c, src/cpu/cpummu.h, src/cpu/newcpu.c: + Major add: 68040 MMU is now running like in WinUae or Aranym. Mega + Thanks to Gilles Fetis for the patch. + [20e3a5efb249] + +2012-02-05 Nicolas Pomarede + + * src/includes/psg.h, src/psg.c: + Rename NUM_PSG_REGISTERS (=16) to MAX_PSG_REGISTERS + [80387355a06a] + +2012-02-04 Laurent Sallafranque + + * src/cycInt.c, src/dmaSnd.c, src/falcon/crossbar.c, + src/falcon/crossbar.h, src/includes/cycInt.h, src/ioMemTabFalcon.c: + remove the new internal interrupt. I let dmaSnd.c multiplex the + Microwire interrupt between dmasnd.c (Ste/TT emulation) and crossbar + (Falcon emulation). + [de0cefac4f14] + +2012-02-03 Eero Tamminen + + * src/includes/psg.h: + + psg.h + [be02d6922a06] + + * src/psg.c: + replace PSG magic values with corresponding defines + [2109a764bd07] + +2012-02-03 Laurent Sallafranque + + * src/cycInt.c, src/falcon/crossbar.c, src/falcon/crossbar.h, + src/includes/cycInt.h, src/ioMemTabFalcon.c: + Correctly handle the Microwire emulation for Falcon. + [2e9b38929fd2] + +2012-02-03 Eero Tamminen + + * tests/tosboot/tos_tester.py: + increase test startup timeouts to cover all boot configs + [cde0ff986a65] + +2012-02-02 Eero Tamminen + + * src/statusbar.c: + fix statusbar assert + shorten machine names so they fit statusbar + [a5696d38b5d7] + + * tests/tosboot/Makefile, tests/tosboot/bootauto.st.gz, + tests/tosboot/bootdesk.st.gz, tests/tosboot/disk/TEST, + tests/tosboot/disk/TEXT, tests/tosboot/disk/test, + tests/tosboot/disk/text, tests/tosboot/floppy.st.gz, + tests/tosboot/readme.txt, tests/tosboot/tos_tester.py: + have separate floppy images for testing TOS <1.04 and newer + + floppy image for TOS <1.04 runs tester from autofolder, the one for + newer TOS versions from DESKTOP.INF. + + To avoid potential issues with Mtools & FAT format, make the names + of files copied to images upppercase. + + Minor Makefile improvements. + [8098e3ad88c7] + + * tests/tosboot/disk/GEMDOS.PRG, tests/tosboot/disk/MINIMAL.PRG, + tests/tosboot/disk/ahcc-gemdos: + updated binaries + [6bd3f1a7a964] + + * tests/tosboot/disk/ahcc-gemdos, tests/tosboot/readme.txt: + update readme for previous TOS Tester changes + [118411ec7034] + + * tests/tosboot/Makefile, tests/tosboot/disk/ahcc-build, + tests/tosboot/disk/ahcc-gemdos, tests/tosboot/disk/ahcc-minimal, + tests/tosboot/disk/common.c, tests/tosboot/disk/common.h, + tests/tosboot/disk/gemdos.c, tests/tosboot/disk/gemdos.prj, + tests/tosboot/disk/minimal.c, tests/tosboot/disk/minimal.prj, + tests/tosboot/floppy/DESKTOP.INF, tests/tosboot/floppy/EMUDESK.INF: + use separate program for non-gemdos testing to avoid modifying the + floppy image: + + - the new test program name is MINIMAL.PRG + - move code common to that and GEMDOS.PRG to common.[ch]files + - adapt project files, hconsole scripts, *.INF files and Makefile + accordingly + - in Makefile check whether AHCC builds succeeded + [308a2e0b60d9] + + * tests/tosboot/tos_tester.py: + verify test program output files + [f770347c18c2] + +2012-02-01 Thomas Huth + + * doc/release-notes.txt: + Updated release notes + [b3e35352b8d7] + + * src/ioMemTabFalcon.c: + Changed behavior of 0xff8924 - it's possible to write a value to + this register + [eed7d83c253a] + +2012-01-31 Thomas Huth + + * src/ioMem.c: + IO registers can only be read in supervisor mode. Thanks to Roger + Burrows for the hint! + [24e5558c93ee] + + * src/ioMemTabFalcon.c: + The register ff8922 returns zeros on Falcon + [810f251f3b79] + +2012-01-31 Eero Tamminen + + * tests/tosboot/Makefile: + don't update binaries when just the empty 'test' file timestamp + updates + [873560f8873b] + + * tests/tosboot/disk/GEMDOS.PRG, tests/tosboot/floppy.st.gz: + update binaries + [ed5117389a91] + + * tests/tosboot/disk/gemdos.c, tests/tosboot/tos_tester.py: + fix midi fifo message handling, fix TOS tester outputs + [e7fffd9b28ab] + + * tests/tosboot/disk/gemdos.c: + add file copy, file access mode and truncate tests, update TODOs + [14bddcaf3c7e] + + * tests/tosboot/Makefile, tests/tosboot/disk/test: + add Makefile to generate test files and to run the tests + + (and empty "test" file used by test the test code) + [dabbaa67db7c] + +2012-01-30 Eero Tamminen + + * tests/tosboot/disk/ahcc-build, tests/tosboot/hdimage/DESKTOP.INF, + tests/tosboot/hdimage/EMUDESK.INF: + convert floppy ones when creating HD image + [cdc91f004db2] + + * tests/tosboot/blank-a.st.gz, tests/tosboot/disk/GEMDOS.PRG, + tests/tosboot/disk/ahcc-build, tests/tosboot/floppy.st.gz: + update generated Atari binary content for the tester + [64d3d9259e01] + + * tests/tosboot/disk/ahcc-build, tests/tosboot/readme.txt: + add files section and otherwise update TOS tester readme + [28a864b5e9fc] + + * tests/tosboot/disk/ahcc-build, tests/tosboot/tos_tester.py: + support for floppy testing, save&output TOS test result report at + end + [549d95692b33] + + * tests/tosboot/disk/ahcc-build, tests/tosboot/disk/gemdos.c: + output success only if everything done succeeds + + There's also some comments about what full program will do and some + stubs that are ifdeffed out. For testing purposes it currently + outputs failure. + [a8dda2a555ff] + + * tests/tosboot/.hgignore, tests/tosboot/disk/.hgignore, + tests/tosboot/disk/ahcc-build: + ignore local/generated test files + [6dd53157aaa2] + +2012-01-29 Eero Tamminen + + * tests/tosboot/ahcc-build, tests/tosboot/disk/ahcc-build: + move ahcc-build to disk/ where rest of build files are + + (additionally simplify it to AHCC being linked under disk/) + [ce7c7a04877b] + + * tests/tosboot/hdimage/DESKTOP.INF, + tests/tosboot/hdimage/EMUDESK.INF: + add tester startup files for booting from HD image file + [a394a97e087b] + + * tests/tosboot/floppy/DESKTOP.INF, tests/tosboot/floppy/EMUDESK.INF: + add tester startup files for booting from floppy + [df9a2c4857aa] + + * tests/tosboot/disk/text: + add test text for future tester features + [ce7e8564ea42] + +2012-01-29 Nicolas Pomarede + + * doc/release-notes.txt: + Update 'Operation Clean Streets' in the 'fixed games' list + [ec839b480c06] + + * src/uae-cpu/gencpu.c: + Add refill_prefetch for i_EOR to fix Operation Clean Streets self + modified code This is an ugly hack, we need better prefetch + emulation (switch to winuae gencpu.c) + [9380ec22a5a3] + +2012-01-29 Laurent Sallafranque + + * src/falcon/crossbar.c: + add some more infos in crossbar traces. + [b99c5536269e] + +2012-01-29 Eero Tamminen + + * tests/tosboot/blank-a.st: + sorry, didn't mean to add the uncompressed one, removing + [6fdeb2366dd3] + + * tests/tosboot/blank-a.st: + add blank floppy image needed by tos tester + [9114dcb13ad3] + + * tests/tosboot/readme.txt, tests/tosboot/tos-tester.py, + tests/tosboot/tos_tester.py: + rewrite TOS tester: + - what is tested is configurable with options and these sets are + filtered through valid configs for given TOS versions + - test success is checked based on test app succesfully writing to + (MIDI) fifo, screenshot is just extra to verify the end results + (e.g. error messages) + [61c311cea94a] + + * tests/tosboot/ahcc-build, tests/tosboot/disk/GEMDOS.PRG, + tests/tosboot/disk/gemdos.c, tests/tosboot/disk/gemdos.prj: + add initial version of the Atari side of TOS tester + [5cb89686fac5] + + * src/cfgopts.c: + empty config option values: support for string types, warn for + others + + With this improvement empty config string can be used to disable + default midi input file setting and just set midi output file. + + It's also good to have warning for non-string config fields which + are empty instead of just ignoring them like was done previously. + [62ce5e32e03b] + + * tools/hconsole/hconsole.py: + get rid of IOError exception also on hconsole's startup + [aa7604915bc5] + +2012-01-28 Laurent Sallafranque + + * src/gui-sdl/dlgSystem.c: + MMU is only for the 68040 (added to the GUI) + [3baf5edd0ac2] + + * src/cpu/newcpu.c: + MMU=1 is only for the 68040 CPU. MMU is always active for the 68030. + [62f69a0a4957] + +2012-01-28 Eero Tamminen + + * src/change.c, src/configuration.c, src/includes/configuration.h: + remove unused "bPrintToFile" config option + [7a016a3a03c4] + + * doc/release-notes.txt: + add some changes from hg shortlog to release notes + [4d40621395cd] + +2012-01-27 Eero Tamminen + + * python-ui/hatari.py: + remove pipe close exception on Hatari UI startup + + On most distros Python handles that fine, it's just ugly output on + console, but apparently on Fedora 16, it causes startup issues: + http://www.atari-forum.com/viewtopic.php?f=51&t=22623 + [5c3e9eb201c7] + + * doc/release-notes.txt, python-ui/hatari.py, python-ui/release- + notes.txt, src/change.c, src/control.c: + hatari UI and hatari control socket support for file paths with + spaces + + (UI code quotes spaces in filenames with '\' and Hatari option + setting supports that now for control socket and debugger.) + [a9d44fa21072] + +2012-01-26 Eero Tamminen + + * doc/memory-usage.txt, doc/release-notes.txt, src/includes/vdi.h: + Change max allowed VDI resolution from 1280x960 to 1920x1200 + [62fc48984d70] + + * doc/compatibility.html: + update compat list + [502031513c3f] + + * doc/release-notes.txt: + update compat list + [c6e22ccdcfee] + + * src/gemdos.c: + handle special device names (CON:, AUX:, PRN:) in GEMDOS HD emu + + - pass them to TOS + - add trace output for this + - remove redundant parenthesis & slightly simplify drive check code + [171fab783c00] + + * src/configuration.c: + revert to v1.4 zoomed Videl window size preference which is close to + ST window size + [e2fbeb4c60df] + +2012-01-24 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + fix: Stack pointer is reitialized when a stack error occurs. This + fix : Build in obsolescence, Llamazap cracked version, Yephya demo + (which bugs later), Moktar Demo (which bugs later too). + [5610e571f350] + +2012-01-24 Eero Tamminen + + * tools/hconsole/hconsole.py: + reduce 100ms wait between successive keypresses to 50ms + [506f37c96501] + +2012-01-24 Laurent Sallafranque + + * src/falcon/dsp_core.c: + fix: DSP SSI was not completly reinitialized after a reset. + [dd50700dc1b8] + +2012-01-23 Nicolas Pomarede + + * doc/release-notes.txt: + Update release notes for Hammerfist + [924abb3aee3e] + +2012-01-23 Eero Tamminen + + * tools/hconsole/example-commands, tools/hconsole/example-debugger: + example script fixes for current Hatari + [9550d7532e99] + +2012-01-23 Nicolas Pomarede + + * src/ikbd.c: + Enable mouse+joystick when commands 0x12 and 0x14 are received + during IKBD's reset (fix fire button in the game Hammerfist) + [49ba623cd264] + +2012-01-22 Nicolas Pomarede + + * src/ikbd.c: + Add some traces when bytes are sent to the IKBD during its reset + phase + [bd9256d2524d] + +2012-01-22 Thomas Huth + + * src/gui-osx/CreateFloppyController.m, src/gui- + osx/English.lproj/SDLMain.nib/designable.nib, src/gui- + osx/French.lproj/SDLMain.nib/designable.nib, src/gui-osx/Info- + Hatari.plist, src/gui-osx/PrefsController.h, src/gui- + osx/PrefsController.m, src/gui-osx/SDLMain.h, src/gui-osx/SDLMain.m: + Updating the OS X GUI to Jerome Vernet's latest level + [0b930e4c32b8] + +2012-01-22 Eero Tamminen + + * src/control.c, tools/hconsole/hconsole.py: + improve hconsole / hatari control socket keypress handling for non- + alphanumeric characters + [eccfa00052c8] + +2012-01-22 Nicolas Pomarede + + * src/ikbd.c: + Add more traces for the IKBD reset command + [09d1d98811e6] + +2012-01-20 Eero Tamminen + + * src/cpu/md-fpp.h, src/cpu/newcpu.c: + fix missing WinUAE prototype warning + [27c02b434166] + + * src/cpu/cpummu.c: + fix cpummu.c compiler warnings not related to format strings + [b8c3d3800050] + + * doc/compatibility.html: + more WinUAE/old UAE test results + [038948d2a5e9] + +2012-01-18 Eero Tamminen + + * doc/compatibility.html: + updated compatibility list falcon programs list + [80a23bb670f6] + + * src/cpu/md-fpp.h: + fix compiler's variable aliasing warning in double conversion + + (can produce wrong code, especially with -O3) + [97b34cd8c6df] + + * src/cpu/custom.c, src/cpu/custom.h, src/cpu/memory.h: + move custom.c function declarations to custom.h, make things not + used outside it static + + Added also TODO/info about moving also custom.c variable + declarations to custom.h and for checking is_cycle_ce() + [e4ea3e6c9ff7] + + * src/cpu/memory.c: + remove redundant SDL_Quit() prototype from C-file + [6767180b19f6] + + * tests/debugger/makefile: + update mudflap comment in tests + [efb1e75268d8] + + * src/gui-sdl/sdlgui.c: + fix potential wrong memory access in GUI code + + (I think this is hard to trigger issue reported by mudflap.) + [2acda29da368] + +2012-01-17 Laurent Sallafranque + + * src/cpu/newcpu.c, src/m68000.c: + fix : changing of CPU or computer via the GUI is now possible with + WINUAE core + [a2cf942c5ebd] + +2012-01-15 Nicolas Pomarede + + * src/video.c: + Remove another possible read above array's limit (see rev 3741) + [f23414c121ab] + + * doc/release-notes.txt: + Set release notes to 'development' version + [893fc641cba4] + + * src/debug/debugui.c: + Remove explicit variables initialization (bug was fixed in rev 3741) + The out of array accesses in Video_StoreResolution were corrupting + some variables in debugui. + [2fe619ef95f2] + + * src/includes/screen.h, src/video.c: + Remove a potential buffer overflow when storing resolution for each + HBL When Hatari runs in color mode but switches to hi res for more + than 1 VBL, Video_StoreResolution() would access memory outside + HBLPaletteMasks[] and possibly overwrite other variables, eventually + leading to some crashes (this is the case with the protection code + used in the 'European Demos' and the 'Transbeauce 2' demo) + [0b77816c4a8d] + +2012-01-15 Eero Tamminen + + * src/includes/video.h, src/video.c: + specify jitter array sizes in header to avoid mudflap warnings + + (unlike couple of UAE specific and ioMemST/STE/TT/Falcon arrays of + which muflap also complains about, they have clear fixed size.) + [6b8902d95711] + + * CMakeLists.txt: + update mudflap package names in comments + [1676d6c57da4] + + * src/main.c: + fix mudflap warning by cast + [9eecdd9c3c6b] + +2012-01-14 Nicolas Pomarede + + * src/statusbar.c: + When using 512 KB, prints 0.5MB instead of 1/2MB in the status bar + "8MHz/0.5MB" is much more readable than the double slashes + "8MHz/1/2MB" + [bc2a87c53230] + + * doc/release-notes.txt: + Typo + [1f70e33b7c26] + +2012-01-14 Laurent Sallafranque + + * src/falcon/crossbar.c: + simplify the code like in dmasnd.c by using Sint64. + [9835809e904b] + + * src/falcon/dsp_core.c: + Host interface registers are all taken into account after a reset or + first init. + [9b176b322ed3] + +2012-01-13 : *** Version 1.6.1 *** + +2012-01-13 Nicolas Pomarede + + * doc/compatibility.html, doc/manual.html, readme.txt: + New release 1.6.1, increase version in corresponding files + [da2ba745065a] [tip] + + * doc/compatibility.html: + Add 'Vodka Demo' by Equinox to the compatibility list + [a37994f79290] + + * doc/doxygen/Doxyfile, doc/release-notes.txt, hatari.spec, src/gui- + osx/English.lproj/InfoPlist.strings, src/gui- + osx/French.lproj/InfoPlist.strings, src/includes/main.h: + New release 1.6.1, increase version in corresponding files + [ccf66d5e509e] + + * doc/release-notes.txt: + Update release notes for 1.6.1 + [135479058419] + +2012-01-12 Nicolas Pomarede + + * src/debug/debugui.c: + Ensure debugger is not called by default when a cpu exception + happens When not explicitly set to 'false', some programs' + protection cause the debugger to be called, which can confuse the + user (eg The Transbeauce Demos and The European Demos) + [5651a4bfdf0e] + + * src/video.c: + Don't remove left border when the hi/lo switch is made after cycle + 12 (fix 'Kill The Beast 2' in the Vodka Demo by Equinox) + [58c6879369f5] + + * src/debug/debugui.c: + Set default debugOutput to NULL (fix segfault) When DebugUI is + called from Exception(), debugOutput was not initialized and + DebugUI_SetLogDefault would call File_Close with an invalid (FILE *) + [b9e92dc09385] + +2012-01-10 Laurent Sallafranque + + * src/cpu/gencpu.c: + added DIVU.L, DIVS.L, MOVEC and DBcc cycles (falcon mode only) + [69c937803d82] + +2012-01-09 Eero Tamminen + + * tests/tosboot/readme.txt, tests/tosboot/tos-tester.py: + add tos-tester readme, change memory amounts to cover more, tt uses + vga + [878ee4a29373] + + * python-ui/CMakeLists.txt: + Fix conftypes.py to be generated where the other python files are so + that Hatari UI can be tested without installation (as stated in the + readme). Depend on the generator. + [816df9843667] + +2012-01-09 Thomas Huth + + * python-ui/CMakeLists.txt, python-ui/Makefile, python- + ui/conftypes.py: + Added proper CMake rule to generate conftypes.py + [ec17f4642694] + +2012-01-09 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [8aec7bfc3e49] + + * python-ui/hatari.py: + patch from David: fix HZ order + [be49fa9e4b72] + + * tests/tosboot/screenshot-report.sh: + more typos + [06ddf47ce60d] + +2012-01-08 Nicolas Pomarede + + * tests/tosboot/screenshot-report.sh: + Typo + [e5db4cc9690a] + +2012-01-09 Eero Tamminen + + * tests/tosboot/tos-tester.py: + limit screen (shot) sizes to reasonable ones, improve comments + [f6c285de94f0] + + * tests/tosboot/screenshot-report.sh: + disable "compare" as it seems to get stuck with larger screenshots + [20f4774f6c96] + +2012-01-08 Eero Tamminen + + * python-ui/conftypes.py: + forgot to add the new, generated conftypes.py + [0b650f38e106] + + * python-ui/README, python-ui/release-notes.txt, python- + ui/uihelpers.py: + update UI version to v1.1 + docs on recent changes + [f80e19acc065] + + * python-ui/dialogs.py, python-ui/hatari.py: + add YM voice mixing & microphone options, simplify sound HZ option + handling + [5a524be7aafa] + + * python-ui/config.py: + one more assert to config handling + [2ec1907c02d6] + + * python-ui/dialogs.py, python-ui/hatari.py: + fix minor Hatari UI issues: + - use correct upper limit on max preferred size (=desktop size) + - fix harmless exception on first tracepoints load + - note that keep desktop option concerns only Falcon/TT + - fix typo + [b2fdb97e94c9] + +2012-01-08 Thomas Huth + + * src/video.c: + Fix for Falcon monochrome mode, second try + [4049a3986f83] + +2012-01-08 Eero Tamminen + + * python-ui/CMakeLists.txt, python-ui/config.py: + Fix assert and resulting empty hatari config file: + + * This was caused by Hatari v1.6 config variable name changes and + those new variable names missing type prefixes. + + * Fix is using variable type mapping (conftypes.py) generated from + Hatari configuration.c file instead of inferring the types from + the (missing) name prefixes. + [b77642db06b7] + + * python-ui/Makefile, python-ui/gentypes.py: + add code for generating conftypes.py from configuration.c + [8a332bf2e195] + +2012-01-08 Thomas Huth + + * src/gui-osx/Shared.h, src/gui-osx/Shared.m: + Updated wrong file header comments + [03d39c13e9a5] + + * src/gui-osx/Shared.h: + A little modification to allow to build Hatari on Xcode 3.1.3/OS X + 10.5.8 PPC. Patch by Andreas Grabher + [d513d264f450] + + * src/video.c: + Fix for Falcon monochrome mode. TOS 4.04 temporarily switches to low + resolution in its early boot sequence. For this we only should look + at ff8260 and not at bUseHighRes. + [ecafd650bb9e] + + * src/video.c: + Source code beautification (indentation with tabs) + [22eac7640d7b] + + * src/video.c: + Fixed the problem with version 1.6.0 not booting in monochrome mode + anymore. bUseHighRes, VideoShifterByte and IoMem[0xff8260] were out + of sync, causing the monochrome screen mode to fail. + [3944430235ef] + +2012-01-08 Eero Tamminen + + * python-ui/hatari.py, tools/hconsole/hconsole.py: + less console warnings on Hatari restart in hconsole & hatariui + [36d8922fba7f] + +2012-01-07 Laurent Sallafranque + + * src/cpu/newcpu.c: + revert last patch as it's not relevant. + [3fbb1188bd4f] + +2012-01-07 Eero Tamminen + + * tests/tosboot/tos-tester.py: + tos-tester: document how to test un-installed Hatari version + [e5917358e2df] + + * doc/authors.txt, python-ui/README, python-ui/config.py, python- + ui/debugui.py, python-ui/dialogs.py, python-ui/hatari.py, python- + ui/hatariui.1, python-ui/hatariui.py, python-ui/uihelpers.py, tools + /atari-hd-image.1, tools/hconsole/hconsole.1, + tools/hconsole/hconsole.py, tools/hmsa/hmsa.1: + remove / replace remaining berlios references + [dac7d5a7c1e5] + + * readme.txt: + readme: known problems -> known distro problems + + (add also a link to David's Python UI patches) + [dc407f1f2001] + + * tests/tosboot/tos-tester.py: + find hconsole if this is run within Hatari sources + + (and add the standard hconsole install locations to module import + path as a fallback) + [e1357631b384] + + * doc/keymap-sample.txt: + add note about keymap test programs to keymap example too + [672d88983485] + + * doc/todo.txt: + update todo list: + - 32Mhz issue was fixed already for v1.6 + - add more info to the Kronos bug (before BerliOS goes down) + - add note about VDI/TOS4 + - fix typo + [2f2598bdccc3] + + * doc/release-notes.txt, tests/readme.txt: + add notes of new test programs to other docs + [62019825e4c5] + + * tests/keymap/checkkeys.c, tests/keymap/keytest.c, + tests/keymap/keytest.mak, tests/keymap/keytest.prg, + tests/keymap/keytest.prj, tests/keymap/keytest.rsc, + tests/keymap/keytest.rso, tests/keymap/listkeys.c, + tests/keymap/readme.txt: + add test programs for finding out Atari & SDL keycodes needed in + Hatari keymap files + [650e47fc2f0a] + + * tests/tosboot/blank-a.st.gz, tests/tosboot/screenshot-report.sh, + tests/tosboot/tos-tester.py: + add TOS bootup tester and screenshot comparison script + intended to + be used before new Hatari release + there's also blank disk image + used by tester + [f1586c166aed] + + * tools/hconsole/hconsole.py: + close control socket when Hatari is killed to avoid warning when + hconsole object is destroyed + [1293353ddcc7] + +2012-01-06 Laurent Sallafranque + + * src/cpu/newcpu.c: + add: split 68030 instructions bigger than 20 cycles to allow the + "internal interrupts" and the DSP to execute. + [b86fbed6e0a8] + + * src/falcon/dsp_cpu.c: + dsp fix+add : externel memory access taken into account I've + refactored the cycle counting by taking into account the multi + external memory access. I've also removed a few if here and there. + I've also reorganized the Ea if to optimise a little (change may not + be noticeable). + [3279d337e8a1] + +2012-01-06 Eero Tamminen + + * src/tos.c: + fix comment typos + [2cc236c511bd] + + * tools/hconsole/hconsole.py: + update Hatari options & debugger commands list for hconsole + [636019d9c454] + + * python-ui/README, python-ui/release-notes.txt: + fix python & gtk version numbers in docs + [7ff82325804b] + +2012-01-04 Laurent Sallafranque + + * src/falcon/dsp.c: + added the addresses mnemonics in the X peripheral memory. When one + disasm the x peripheral memory (dm x $ffc0 to dm x $ffff), the + address mnemonic is added at the end of the disasm. + [2d9daa1bb182] + + * CMakeLists.txt: + New CPU musn't be the default CPU yet. + [5b61a5a23a75] + + * CMakeLists.txt, src/cpu/gencpu.c: + add: LSR, LSL ADR Dx,Dy 68030 cycles. + [96fbfe482ec9] + +2012-01-03 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + code refactoring + DSP memory map comment. + + I've rewritten some parts of the DSP code. It's more readable like + this. I've optimised a little some A and B registers access (this + optimisation shouldn't be noticeable) I've added a DSP memory map in + comments at the beginning of the file. + [26c2ac01a10b] + +2012-01-01 : *** Version 1.6.0 *** + +2012-01-01 Nicolas Pomarede + + * doc/doxygen/Doxyfile, doc/release-notes.txt, hatari.spec, src/gui- + osx/English.lproj/InfoPlist.strings, src/gui- + osx/French.lproj/InfoPlist.strings, src/gui-osx/Info-Hatari.plist, + src/includes/main.h, src/memorySnapShot.c: + New release 1.6, increase version in corresponding files + [12780dca66b3] [tip] + +2012-01-01 Eero Tamminen + + * doc/compatibility.html, doc/release-notes.txt: + update 32Mhz clock and MMU notes + [4f6c6b3402b6] + +2011-12-30 Nicolas Pomarede + + * src/debug/68kDisass.c: + Use FILENAME_MAX instead of PATH_MAX (not POSIX compliant) (Clang + error) + [2b435d434331] + + * src/unzip.c: + Remove extraneous parentheses (Clang warning) + [f42762ce7f7c] + +2011-12-30 Thomas Huth + + * doc/hatari.1, doc/manual.html: + Documented the --patch-tos option + [30e111d3f6d3] + +2011-12-28 Eero Tamminen + + * doc/todo.txt: + typo + [fdd332ee69a1] + + * doc/release-notes.txt: + release note about TT/mono double click fix + [e020d24a1c78] + +2011-12-28 Thomas Huth + + * src/video.c: + Always set nCyclesPerLine = CYCLES_PER_LINE_71HZ in monochrome mode + [ce618cc0d7f5] + +2011-12-27 Nicolas Pomarede + + * src/ikbd.c: + Handle a special case when sending bytes to the ikbd while a byte is + already in transfer In that case, we should replace the byte + currently being transfered, but we should not restart the TX + interrupt, nor change the TX_BUFFER_EMPTY bit (fix 'Pandemonium + Demos' Intro by Chaos) + [3a9a73e114d2] + + * src/fdc.c: + Allow an FDC command to be replaced by another command during the + prepare+spinup delay This feature is not described in the original + WD1772 documentation, it would need to be correctly measured on a + real ST. (fix buggy loader in Overdrive Demos by Phalanx) + [c284aa5611e8] + +2011-12-26 Eero Tamminen + + * readme.txt: + update readme for v1.6 & notes on WinUAE vs. old UAE core + [dcef12a6ca3f] + + * doc/release-notes.txt, src/debug/log.h: + flush trace output so that it's not buffered (and therefore + potentially misleading) + [1b1af950067c] + +2011-12-26 Nicolas Pomarede + + * src/fdc.c: + For The FDC Restore command, set track=255 after the spinup + sequence, not before (fix buggy loader in Overdrive Demos by + Phalanx) + [666341f96bec] + + * doc/release-notes.txt, src/cycInt.c, src/ikbd.c, + src/includes/cycInt.h, src/includes/ikbd.h, src/memorySnapShot.c: + For ACIA transfers, split internal RX/TX interrupt handler in 2 + separate handlers (fix the game 'Alien Storm') + [b71fc05b3e31] + + * src/fdc.c: + Fix typo in comment + [d97cede2f9f1] + + * src/fdc.c: + Fix FDC delays on Falcon, they were 2 times bigger than expected (16 + Mhz clock instead of 8) + [89b2158446eb] + +2011-12-25 Nicolas Pomarede + + * doc/emutos.txt: + Latest EmuTOS version is now 0.8.6 + [1c6e2b4f4447] + + * doc/compatibility.html: + Add notes about Whitewater Madness video issues on STE + [4d27a1702fb4] + + * doc/compatibility.html, doc/todo.txt: + Update docs for sound in RBI Baseball 2 and joystick in Warlock's + Quest + [0c59db5fb37a] + +2011-12-25 Thomas Huth + + * doc/todo.txt, src/video.c: + Fixed VBL timing problem in monochrom TT mode. VBL timings were + wrong because we used nScanlinesPerFrame from monochrome mode but + nCyclesPerLine from color mode. This caused mouse double click + problems and some other oddities. + [073804e4887e] + + * src/configuration.c, src/includes/configuration.h, src/options.c, + src/tos.c: + Added a new (expert) option to skip TOS patches completely. As seen + in the game "Yolanda" (when we skipped the memory test of TOS), + bypassing parts of TOS can cause incompatibilites. To be able to + switch of some more "patching" by Hatari, I added now a new option + --patch-tos to be able to disable the TOS ROM patches, too. + [13054082085f] + + * doc/compatibility.html: + Updated information about RS232 settings in some games + [2c123aa7ccab] + + * doc/compatibility.html, doc/todo.txt, src/configuration.c, + src/stMemory.c: + Enabled the "memvalid" system variables patching by default again. + There were too many new problems when this was disabled by default. + [7857da6acbc7] + +2011-12-24 Nicolas Pomarede + + * src/fdc.c: + In FDC traces, add current track for type I commands + [70799cf90538] + +2011-12-23 Nicolas Pomarede + + * src/cpu/gencpu.c, src/cycles.c, src/includes/cycles.h, src/uae- + cpu/gencpu.c: + Improve cycle accuracy for each byte access in movep R->M (fix + Moving Earth part in E605 by Light, uses movep.l d0,$ffc3(a1) to + change video counter) + [ed0a93e92d17] + +2011-12-22 Thomas Huth + + * python-ui/hatariui.py, python-ui/uihelpers.py: + Replaced remaining URLs that still pointed to berlios.de + [c1047c7e3c87] + + * doc/release-notes.txt: + Updated release notes + [8c887fc2aa75] + + * doc/todo.txt: + Added some bug reports + [2f24a844609f] + +2011-12-22 Laurent Sallafranque + + * src/falcon/crossbar.c: + fix: hanshake mode transfers. One variable was not correctly + initialized when running crossbar in handshake mode. This patch + fixes wait demo (it now runs with sound) on both old and new cpu. + [c80c19152ced] + +2011-12-22 Nicolas Pomarede + + * src/gui-sdl/dlgScreen.c: + Radio button 'none' was never checked in Screen dialog + [99716d346b1b] + + * src/gui-sdl/dlgSound.c: + Reduce Sound dialog's height to work when Atari screen's borders are + not shown + [269f66c7453c] + + * doc/authors.txt, doc/hatari.1, doc/manual.html, doc/release- + notes.txt, src/configuration.c, src/gui-sdl/dlgSound.c, + src/includes/sound.h, src/options.c, src/sound.c: + Add a new mixing method for the YM2149 using a mathematical model + (patch by David Savinkoff) Use --ym-mixing model to use this method. + Unlike the "table" method which is based on many measures on a real + STF, this method aims to create a correct mixing table using an + accurate model of the 3 YM2149 voices. The result should be similar + or better when compared to "table" mixing. + [47e6d95ffb79] + +2011-12-21 Nicolas Pomarede + + * src/audio.c: + Turns on low pass filter in STF mode for 44.1 and 48 kHz replay + frequencies See sound.c for more details on the low pass filter + characteristics used in the STF + [2fa859d3a7c1] + + * src/sound.c: + Improve the low pass filter to better mimic the STF's one (patch by + David Savinkoff) + [459fe6c8a77f] + +2011-12-20 Nicolas Pomarede + + * doc/todo.txt: + Add some examples of programs not working correctly for now + [3aaa8701ec32] + + * doc/release-notes.txt: + Update release notes with a list of working programs since previous + release + [63b14cd56c91] + + * doc/emutos.txt: + Add note about EmuTOS before 0.8.6 requiring the FastBoot option + [95f3524966a3] + +2011-12-14 Nicolas Pomarede + + * src/joy.c: + Correct joystick axis mapping patch by Matthias Arndt + - use 'false' instead of 'NULL' for bool + - use #define for max numbers of joysticks instead of '6' + [5a85ee82b748] + +2011-12-14 Laurent Sallafranque + + * src/cpu/newcpu.c: + fix: take all 68030 cycles into account for better 68030 <-> DSP + synchro. + [be37bc3851b5] + + * src/falcon/dsp.c: + fix: DSP access to host port are made in Bytes. I add 4 cycles for + each word access or 3*4 cycles for a long access. + [df60a705cf0e] + + * src/uae-cpu/newcpu.c: + fix oldcpu : fixed ratio between 68030 and DSP speed. As to simulate + a 16Mhz CPU, all cycles are divided by 2, we have to mul them back + by 2 while calling run_dsp to have the DSP runnning at 32 Mhz. + [a896dbbe512b] + +2011-12-13 Nicolas Pomarede + + * src/includes/joy.h, src/joy.c: + Add patch by Matthias Arndt to specify axis mapping for different + joysticks' model + [d64a2a131720] + +2011-12-11 Nicolas Pomarede + + * src/m68000.c: + Add pairing for MUL/JSR (Lemmings Compilation 40's Intro) + [4f072f87472f] + +2011-12-10 Nicolas Pomarede + + * src/cpu/hatari-glue.c, src/uae-cpu/hatari-glue.c: + When using the RESET instruction, we should call PSG_Reset() to stop + any sound + [03cb4ea7445f] + + * src/psg.c: + In PSG_Reset, also clear sound's emulation registers + [0a69612b8028] + + * src/ikbd.c: + If a byte is written to $fffc02 it cancels the current transfer from + ACIA to IKBD Some buggy programs send several bytes to $fffc02 + without checking TX bit is ready ; in that case the most recent byte + written to $fffc02 cancels any transfer in progress. (fix the games + 'Yogi Bear' and 'Platoon') + [ba1cf5f0573f] + + * src/includes/ikbd.h: + ACIA's RX overrun is bit 5, not 6 + [78292ff0323b] + +2011-12-09 Laurent Sallafranque + + * src/cpu/gencpu.c: + more instruction cycles completes. Added : movem, Bcc, CHK, CHK2, + CAS. + [05c247a0b2e6] + +2011-12-07 Thomas Huth + + * src/keymap.c: + The special hack for sending a second caps lock key press is now not + required anymore. + [4e880042ff90] + + * src/main.c: + Set SDL_DISABLE_LOCK_KEYS for correct behavior of the Caps Lock key + [23f03cb0da3f] + +2011-12-06 Nicolas Pomarede + + * src/rs232.c: + When reading $fffa2d and RS232 is not enabled, return 0x80 (empty + buffer) This allow some games to work when they don't require + complete send/receive support on the RS232 port (eg : 'Treasure + Trap' and 'The Deep' write some debug informations to RS232) + [7c486c7f7d01] + +2011-12-04 Laurent Sallafranque + + * src/cpu/newcpu.c: + cosmetic change + [f7d6209fd12d] + + * src/cpu/falcon_cycle030.h, src/cpu/gencpu.c, src/cpu/newcpu.c: + Movem is complete. RTE is complete but simplified. Code is now + complete to add all other cycles that are not in the generic table. + [0425f878b6cc] + +2011-12-04 Thomas Huth + + * src/falcon/nvram.c, src/falcon/nvram.h: + Fixed inital monitor settings in the NVRAM (the VGA bit was wrong). + Thanks to Vincent Riviere for the hint! + [71606731ce9c] + + * src/convert/med640x16_spec.c, src/convert/med640x32_spec.c, + src/file.c, src/ide.c, src/uae-cpu/build68k.c, src/uae-cpu/fpp.c: + Fixed some compiler warnings about set but not used variables. These + warnings only occured with GCC 4.6 which now also checks for these + set-but-not-used variables. + [08ac98ddea8a] + +2011-12-04 Nicolas Pomarede + + * doc/compatibility.html: + Add notes about games that need RS232 to be enabled Some games write + debug informations to the RS232 port ('Treasure Trap' and 'The + Deep') They will loop forever until bytes can be sent to the RS232. + [665e2d76c821] + + * src/video.c: + Check for 4 pixel hardware scrolling on STF/STE only during the + first 40 cycles + [2805f848aeeb] + + * src/video.c: + Timer B's position could be wrong with overscan lines stopping at + cycle 160 (fix 'Bye bye Lester' in the 'O-Demo' by Oxygene) + [8cfe13db1d53] + +2011-12-02 Laurent Sallafranque + + * src/cpu/custom.c, src/cpu/events.h, src/cpu/events_normal.h, + src/cpu/falcon_cycle030.h, src/cpu/gencpu.c, src/cpu/newcpu.c, + src/cpu/newcpu.h: + add: first 68030 version with the cycle exact table. There's still a + lot of work to do : + - include all special cycles like movem, Bcc, ... + - finish to compute the MMU and FPU cycles + [e5cf006c1b7d] + +2011-12-01 Thomas Huth + + * doc/authors.txt, doc/compatibility.html, doc/fr/hatari.1, + doc/hatari.1, doc/manual.html, etc/README, hatari.spec, python- + ui/README, python-ui/dialogs.py, readme.txt, src/gui-osx/SDLMain.m, + tools/hmsa/hmsa.1, tools/hmsa/readme-hmsa.txt, tools/zip2st.1: + Updated the URLs to point to tuxfamily.org instead of berlios.de. + [0f070880f088] + + * website/backgnd.png, website/contact.html, website/docs.html, + website/download.html, website/favicon.ico, website/hatari- + small.png, website/hatari.css, website/hatari.png, + website/index.html, website/links.html, website/news.shtml, + website/scrshots.html, website/scrshots1.html, + website/scrshots2.html, website/scrshots3.html, + website/scrshots4.html, website/scrshots5.html, + website/scrshots6.html: + Removed website from main repository (it's tracked in a new + repository instead) + [31893f13f668] + +2011-12-01 Nicolas Pomarede + + * src/fdc.c: + Add drive number in FDC's traces + [7d196104f18b] + +2011-11-30 Laurent Sallafranque + + * src/cpu/falcon_cycle030.h: + more cycles added. Only FPU/MMU cycles are not yet in the table. + [7c30b0cd111c] + +2011-11-29 Nicolas Pomarede + + * doc/authors.txt: + Update contributors' list + [43e4d22bef3d] + +2011-11-27 Laurent Sallafranque + + * src/cpu/falcon_cycle030.h: + added more cycles. 92% completed. + [6d6cf05d9763] + +2011-11-27 Nicolas Pomarede + + * src/stMemory.c: + Allow to bypass TOS' memory tests only for EmuTOS or if more than 4 + MB of ram are used Some programs rely on those (unofficial) values + written to RAM when the memory tests were run. We should not bypass + those tests in the common STF/STE cases with < 4MB (fix the game + Yolanda on Pompey Pirates 46, which expects $100 to contain a value + != 0) + [4721f2381c07] + + * src/configuration.c: + Set system/fastboot to false by default as it can be less accurate + emulation-wise + [a44926c1f69b] + +2011-11-26 Nicolas Pomarede + + * src/fdc.c: + For FDC type I commands, set RNF error in SR when verify is set and + TR != physical track Some programs change the head's position before + returning to TOS. In that case, the logical track stored in the TOS + will not be the same as the physical one. The TOS uses the verify + bit to detect this situation and corrects it using a 'restore'. (fix + the game Demon Blue on Adrenaline CD 24b, where the game's + protection seeks to track 0x4f and returns to TOS without restoring + head's position) + [c45ba921c4ee] + +2011-11-25 Laurent Sallafranque + + * src/cpu/falcon_cycle030.h: + add some MUL and DIV cycles. 83% completed + [9c3ae9c6ec9c] + + * src/cpu/falcon_cycle030.h: + add more falcon cycles. 80% completed + [1e5a8f93497a] + +2011-11-24 Nicolas Pomarede + + * src/dmaSnd.c, src/includes/sound.h, src/sound.c: + Improve YM/DMA sound by using IIR filter instead of FIR (patch by + David Savinkoff) + [38717dc41991] + +2011-11-23 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Updates docs with FDC and shifter changes + [7a107455d23b] + +2011-11-24 Eero Tamminen + + * src/uae-cpu/hatari-glue.c: + fix typo in previous commit + [4f9596596a83] + +2011-11-23 Nicolas Pomarede + + * src/fdc.c: + Allow modifying Sector Register and Track Register while the FDC is + busy Contrary to what is written in the WD1772 doc, it's possible to + modify these registers while a command is running (but it could have + no effect depending on when it's done) (fix Delirious Demo IV's + loader routines that change SR just after the Read Sector command) + [a8a68c625e17] + + * src/fdc.c: + For FDC Read / Write Sector commands, add a minimum delay to find + the sector's header Depending on the spinning speed, finding the + expected sector's header will never be immediate and will always + require at least 6 bytes to be read by the FDC. During that time, + Sector Register can still be modified. (fix Delirious Demo IV's + loader routines) + [96451d1d3585] + +2011-11-23 Eero Tamminen + + * src/includes/vdi.h, src/reset.c, src/uae-cpu/hatari-glue.c, + src/vdi.c: + handle illegal opcode matching one used by Hatari internally during + VDI emulation + + Fixes: Union demo from POV disk 112 causing Hatari abort with EmuTOS + 0.8.6. + [d0cd30767492] + +2011-11-21 Laurent Sallafranque + + * src/cpu/falcon_cycle030.h: + added: some more falcon cycles. 75% completed. + [5d27277dde7a] + +2011-11-20 Nicolas Pomarede + + * src/fdc.c: + Bit 6 of FDC's SR should be 0 after a read command when the disk is + not write protected In the case of a type II/III command doing a + read, the WPRT bit of the Status Register should not be kept + unchanged but should be set to 0. (fix Madness by Cream, the loader + would not work when disk was write protected) + [7cc9290540d4] + +2011-11-20 Eero Tamminen + + * doc/hatari.1, doc/manual.html, doc/release-notes.txt: + document --force-max option. update --desktop* options. remove some + trailing whitespaces from hatari.1 + [16854e348d64] + +2011-11-20 Nicolas Pomarede + + * src/video.c: + Correct screen's alignment with 4 pixel hardware scrolling + [7de6a128dc82] + +2011-11-19 Nicolas Pomarede + + * src/video.c: + Adjust borders' removal when empty lines with no signal are used + (fix NGC screen in Delirious Demo IV) + [76e88fba127c] + +2011-11-18 Laurent Sallafranque + + * src/cpu/falcon_cycle030.h: + add: more falcon instructions cycles. 70% completed. + [7075240efea8] + +2011-11-18 Nicolas Pomarede + + * src/video.c: + Add support for another method to do 4 pixel hardware scrolling on + STF/STE (fix NGC screen in Delirious Demo IV) + [51c2c0d6e00a] + +2011-11-17 Nicolas Pomarede + + * src/video.c: + Improve timings used for the 0 byte line when switching hi/lo at the + end of the line (fix NGC screen in Delirious Demo IV) + [5aac202026f4] + +2011-11-16 Laurent Sallafranque + + * src/cpu/falcon_cycle030.h: + fix: add.l Ea,Dn was shifted. + [a5d3992cb542] + + * src/cpu/falcon_cycle030.h: + fix: all LONG instruction cycles recomputed. + [9f5195037d6e] + +2011-11-14 Nicolas Pomarede + + * src/cycles.c: + For CLR, the write is effective at the end of the instruction, not 4 + cycles before like MOVE (fix clr.b $ff820a used for bottom border + removal in Delirious Demo IV / No Scroll) + [3812f0e1e8c7] + +2011-11-14 Laurent Sallafranque + + * doc/compatibility.html: + added DownFall game (Falcon) into the compatibility list. + [95adcd60a4e6] + + * src/cpu/falcon_cycle030.h: + added more instructions cycles : 59% completed. + [a858d6516037] + +2011-11-13 Laurent Sallafranque + + * src/cpu/falcon_cycle030.h: + added more instruction cycles : 49% completed + [90a23eb577a1] + +2011-11-13 Nicolas Pomarede + + * src/floppy.c: + Recognize ST disk images with 83 or 84 tracks + [ba4e13a4e194] + +2011-11-12 Laurent Sallafranque + + * src/cpu/falcon_cycle030.h: + add more instructions cycles. 40% done. + [7fbbba6274cf] + + * src/cpu/falcon_cycle030.h: + add all simple MOVE instruction's cycles. + [615da1b85b5a] + +2011-11-12 Nicolas Pomarede + + * src/video.c: + When reading $ff820f in STE mode, returns the last value written + there, not LineWidth + [cc761ddcda16] + +2011-11-11 Thomas Huth + + * doc/manual.html: + Updated OS list in manual + [5a5c057a9494] + +2011-11-11 Laurent Sallafranque + + * src/cpu/falcon_cycle030.h: + add new file for falcon030 cycles. + [252da25d0565] + +2011-11-10 Eero Tamminen + + * src/configuration.c, src/includes/configuration.h, src/options.c, + src/resolution.c: + add option to force resolution to be fixed to given max resolution: + - like --desktop option, affects only Falcon/TT (as ST/STE modes + aren't scalable, they can be only doubled) + - useful e.g. when recording video of Falcon demos that switch + resolution + [1a19e303f3b2] + + * doc/emutos.txt: + more things work with EmuTOS 0.8.6, update compat list + [415959b04874] + +2011-11-08 Nicolas Pomarede + + * doc/todo.txt: + Remove FDC from the todo list, all commands/timings are now emulated + [d6d56d753405] + +2011-11-02 Laurent Sallafranque + + * src/cpu/gencpu.c, src/cpu/newcpu.c, src/cpu/newcpu.h: + Code preparation for 68030 cycle exact. + [2fe9ab72f13c] + +2011-10-31 Laurent Sallafranque + + * src/cpu/custom.c, src/cpu/events.h, src/cpu/events_normal.h, + src/cpu/newcpu.c: + fix new core to allow 68030 cycle exact run. It's less accurante + than the generic 68030 emulation for now, but it runs. + [83307e177bdb] + +2011-11-06 Nicolas Pomarede + + * doc/release-notes.txt: + Update changes in FDC's emulation + [6f6644b91e56] + + * src/fdc.c, src/floppy.c, src/includes/floppy.h, + src/memorySnapShot.c, src/reset.c: + Add correct emulation of the WPRT bit when a disk is inserted or + ejected As the ST doesn't use the Disk Change signal available on + the floppy drive, the TOS uses a different method to detect changes + by monitoring the WPRT bit in the FDC's Status Register. When a disk + is inserted or ejected, this bit should be updated to 0 or 1 during + a minimum number of VBLs. + [274895220444] + +2011-10-30 Nicolas Pomarede + + * src/includes/psg.h, src/psg.c: + Handle the case when reading $ff8800 just after a write to $ff8802 + There's a special case when reading a register from $ff8800 : if the + register number was not changed since the last write (by writing to + $ff8800), then we must return the value that was written to $ff8802 + without masking the unused bit. Else, unused bits should be set to 0 + when reading a register. (fix the game Murders In Venice, which + expects to read $10 from reg 3). + [d3f6185dcbd3] + + * src/memorySnapShot.c: + Change version in memory snapshot ('devel' versions are not always + compatible with each other) + [4b4070102351] + + * src/configuration.c: + In the memory snapshot, include the name of the disk image and zip + path for each floppy drive + [ff0ec8e9f809] + +2011-10-17 Nicolas Pomarede + + * src/fdc.c: + Set the WPRT bit in FDC Status Register when there's no disk + inserted + [67ca42a71612] + +2011-10-15 Eero Tamminen + + * doc/release-notes.txt: + add missing items to release notes + [d8dc72a4d858] + + * doc/compatibility.html: + note Spectrum 512 & Hextracter mouse issues + [5224e8e7365e] + + * doc/authors.txt: + add Markus Heiden to contributors + [ac2437441bb6] + +2011-10-16 Nicolas Pomarede + + * src/video.c: + Fix medres overscan detection (line was rendered in low res) (fix + Greeting screen in the 'No Cooper' demo : because of the freq switch + to remove the bottom border, switch to medres was made 16 cycles + later and line 263 was in low res) + [980585cb4037] + +2011-10-13 Nicolas Pomarede + + * doc/compatibility.html: + Update comments for the demo Illusion by Dune + [9f321f0f6b17] + +2011-10-12 Laurent Sallafranque + + * src/cpu/custom.c, src/cpu/gencpu.c, src/cpu/newcpu.c: + 3 major changes in newcpu.c (new core) + + This patch concerns 3 important changes in the WinUAE new core : + + 1) I've reintroduced the nCurInstrCycPos variable to allow the + pairing detection with the 68000 core 2) I've patched the cycle + exact cores to let them run (of course, cycle exact is not yet + implemented into each componant for now), but the cores are running + now 3) The most important : I've found and corrected the problem + with all the falcon demos that needed to run at 32 Mhz only + (EkoSystem, are you experienced, lostBlubb, ...) + [632d356ebd40] + +2011-10-12 Nicolas Pomarede + + * src/fdc.c: + Correct the FDC step rates, they were not the correct ones for + WD1772 The 1989 book I used from Data Becker / Micro Application + gave the values 2, 3, 5 and 6 ms, which are wrong, the correct ones + are 6, 12, 2 and 3 ms. (fix Knightmare (on DBUG #24), the loader + waits 41000 cycles before 2 Step In commands without testing + $fffa01, with 6 ms delay instead of 3 ms, some commands were ignored + because the FDC stayed in busy state for too long) + [a9ae22f1c449] + + * src/fdc.c: + When Force Int is called, set Motor ON if FDC was idle or busy with + a type I command (fix Knightmare (on DBUG #24), an extra delay was + added to start the motor when doing a Step In, which prevented + following FDC comamnds to be executed) + [93d450978e0b] + +2011-10-10 Laurent Sallafranque + + * src/cpu/cpummu.c: + cosmetic issue Reformatted source code to be closer to the original + WinUae's code + [420388d34b87] + +2011-10-09 Thomas Huth + + * src/tos.c: + Switch to ST mode when using TOS <= 1.04 + [ada1ca9cea15] + +2011-10-09 Nicolas Pomarede + + * src/fdc.c: + In the FDC, clear Spin Up bit during the time needed to start the + motor + [fd968928f2c4] + +2011-10-07 Markus Heiden + + * src/fdc.c, src/hdc.c, src/includes/hdc.h: + API-only access to hdc.c + [3d5607cf69b2] + + * src/hdc.c: + Used macros for reading words + [c5554b424b4b] + +2011-10-08 Nicolas Pomarede + + * doc/images/floppydisks.png, doc/manual.html: + Update the Floppy Disk Dialog section in the manual with "Fast + floppy" mode + [b679d73bad89] + +2011-10-06 Thomas Huth + + * src/hdc.c, src/includes/hdc.h: + SCSI class 1 command support for drives > 1 GB. Thanks to Markus + Heiden for the patch. + [d33662b5c5c1] + +2011-10-06 Nicolas Pomarede + + * doc/fr/hatari.1, doc/hatari.1, doc/manual.html, etc/n810.cfg, + etc/wiz.cfg, python-ui/dialogs.py, python-ui/hatari.py, python-ui + /release-notes.txt, src/configuration.c, src/fdc.c, src/gui- + osx/English.lproj/SDLMain.nib/designable.nib, src/gui- + osx/French.lproj/SDLMain.nib/designable.nib, src/gui- + osx/PrefsController.h, src/gui-osx/PrefsController.m, src/gui- + sdl/dlgFloppy.c, src/includes/configuration.h, src/options.c, + tools/hconsole/hconsole.py: + Replace --slowfdc by --fastfdc (speed up FDC delays by x10) For + maximum compatibility, the default mode for Hatari is now to run the + FDC at the same speed as a real ST. The option --fastfdc can be used + to speed up most FDC delays (this should works with most of the + games/demos, but can lead sometimes to incompatibilities when the + programis expect some precise timings) + [ccd6752560e3] + + * src/fdc.c: + Remove debugging printf's + [dbc85c253d94] + +2011-10-03 Eero Tamminen + + * src/includes/configuration.h: + allow GEMDOS drives up to Z: not Y: + [3552d1f414af] + +2011-09-28 Thomas Huth + + * doc/manual.html: + Fixed bad HTML + [6c89f9913bad] + + * src/gui-osx/SDLMain.m: + Fixed compile error for OSX by adding missing parameter to DebugUI + call. Thanks to Mikael Degerfalt for the patch! + [b740701a441c] + +2011-09-18 Eero Tamminen + + * src/debug/symbols.c: + fix some cosmetic issues in AHCC SYM symbols format compatibility + [e75d74de4671] + +2011-09-07 Laurent Sallafranque + + * doc/release-notes.txt: + added microwire clock better accuracy to the emulator release notes + [dec600e761b6] + + * src/dmaSnd.c: + better accuracy for microwire emulation : remove a specific test for + xmas2004 (no more useful with the latest microwire code) and cycles + consumed by the 68000 are taken into account in a better way to + generate a more precise 8 cycles clock. + [c2a659c51883] + +2011-09-04 Eero Tamminen + + * python-ui/hatari.py, python-ui/hatariui.py: + hatariui: hatari max window size defaults now to desktop size + + (affects initial window size i.e. avoids resize at beginning) + [679aca45fb45] + + * src/main.c: + fix bug 18340: check window embedding before creating window + [a99c28bacadd] + + * doc/emutos.txt, readme.txt: + add links to EmuTOS versions used in different Hatari version, + correct DATADIR note + [7f173c0891c1] + +2011-08-31 Eero Tamminen + + * doc/release-notes.txt, doc/todo.txt: + update release notes & todo + [deffe87f548f] + + * doc/hatari.1, doc/manual.html: + update hd emu docs, minor cleanup + [a041f4d2ae8c] + + * CMakeLists.txt, cmake/config-cmake.h, src/gemdos.c: + return real free space for GEMDOS HD emulated partion: + - limited to a partition size that used TOS version supports + - supported only if statvfs() function is found + [92bf5e6df087] + + * src/gemdos.c: + return unique name for each HD emulated partition + [94784b65464a] + + * src/gemdos.c: + fix bug 18310: use fake HD Dfree() only for emulated drives + + related refactoring + + refactoring: + - remove commented out GEMDOS_IsHDDPresent() + - refactor similar GemDOS_IsDriveEmulated() functionality to its own + function from GemDOS_IsFileNameAHardDrive() + - Fix: Use GemDOS_IsDriveEmulated() function in Dfree() & Dgetpath() + instead of their current half-broken code + - Rename GemDOS_IsFileNameAHardDrive() to a more correct + GemDOS_FileName2HardDriveID() as it returns drive ID, not bool + [9977e0152019] + + * src/gemdos.c: + fix: HD emu multipartition support didn't handled mixed case + partition names + + Multipartition directory name counting function expected scandir() + to return directory entries in alphabetical order, but it does that + only if they're of same case. When upper and lower case drive + identifies are mixed, counting didn't work. + + Instead of adding case insensitive alphasort, I decided just to + correct the maximum drive counting. + [5bf4e8f4c2b6] + +2011-08-29 Eero Tamminen + + * tools/atari-hd-image.sh: + Latest sfdisk is broken. Write suitable MBR with inlined Python + code + [6dd08c14968a] + +2011-08-28 Eero Tamminen + + * src/debug/breakcond.c: + reorder breakpoint hit output order to: + - info about there being a hit + - "lock"ed information, if any (e.g. history) + - parsed debugger "file" output, if any + - info about breakpoint itself + - new value for traced item, if something traced + - info about breakpoint removal, if it's removed + [f0b8c2b8e2dc] + + * src/debug/breakcond.c, src/debug/debugui.h, src/debug/history.c: + improvements/fixes to how instruction execution history is shown + with breakpoints + [4e2ab4a67ac2] + +2011-08-22 Eero Tamminen + + * src/paths.c: + fix bug 18297: Windows needs also HOMEDRIVE for full home path + [a67dcb6ad345] + +2011-08-21 Eero Tamminen + + * tools/atari-hd-image.sh: + show suitable error message at exit, force Bash as echo escape + sequence interpretation differs between shells + [9dd8749a5d8b] + + * src/debug/breakcond.c, src/debug/history.c, src/debug/history.h: + remove new prevCpu/DspPC history variable as useless + [55d820210133] + + * tools/atari-hd-image.sh, tools/hatari-local-midi-ring.sh: + fix: handle case when string is given instead of numeric argument in + helper scripts + [a85204f3b546] + +2011-08-17 Thomas Huth + + * src/stMemory.c: + Disabled memvalid patching for EmuTOS + [c8a06df9ca70] + +2011-08-16 Thomas Huth + + * src/screen.c: + Improved color convertion table so that colors are a little bit + brighter now + [b1e5be1dda12] + +2011-08-14 Eero Tamminen + + * doc/manual.html: + add history info to Manual's Debugger "Usage examples" section + [96f13af8e511] + + * src/debug/history.c: + history fix: use 32-bit PC for CPU, show breaking reason after + instruction + [2e844ec44581] + + * src/debug/debugInfo.c, src/debug/history.c, src/debug/history.h: + support history also for the lock command + [bd92e46c8cf0] + + * src/debug/breakcond.c, src/debug/debugcpu.c, src/debug/debugdsp.c, + src/debug/debugui.c, src/debug/history.c, src/debug/history.h: + history 3/3: integrate history functionality to debugger + [f1f3b514592a] + + * src/debug/CMakeLists.txt, src/debug/history.c, src/debug/history.h: + history 2/3: add new history functionality source code files + [f78832aa167a] + + * src/debug/debugcpu.c, src/debug/debugdsp.c, src/debug/debugui.c, + src/debug/debugui.h, src/shortcut.c, src/uae-cpu/newcpu.c: + history 1/3: add reason why debugger was invoked + + Is needed by debugger history functionality, but can be useful also + for debugger UI later on. + [5c966dad28ef] + + * src/falcon/videl.c: + fix: crash with a Videl resolution of 2460x200 + + (NVDI 2.5 set that after it failed to load a sys file) + [8253ac221f06] + +2011-08-13 Thomas Huth + + * doc/hatari.1, doc/manual.html: + Added the fast-boot option to the manual + [b677e1cfcb36] + + * doc/hatari.1, doc/manual.html, src/options.c: + Moved sound options to a separate section + [2fa15fc14bb6] + +2011-08-13 Eero Tamminen + + * doc/hatari.1, src/options.c: + add option for controlling desktop option for ST/E + [c0d0f7e7d1af] + + * src/configuration.c, src/includes/configuration.h, src/screen.c: + add bKeepResolutionST configuration option + [ff951f2b4a67] + +2011-08-12 Thomas Huth + + * src/configuration.c, src/gui-sdl/dlgSystem.c, + src/includes/configuration.h, src/options.c, src/stMemory.c, + src/tos.c: + Added fast-boot option + [19442ce2ea1f] + +2011-10-06 Nicolas Pomarede + + * src/fdc.c: + When using Read Track on a side that doesn't exist, return random + bytes instead of Record Not Found + [4805fbc91418] + + * src/fdc.c: + Improve the 3 possible cases in FDC's Force Int command + [a4b17799b472] + + * src/fdc.c: + Set ID_FieldLastSector to 0 to simulate an index pulse + improve + timings for Read Address Some copy / disk analyzer programs require + very precise timings when combining Read Track and Read Address to + analyze the layout of a track. Read Address needs to return ID + fields at the same time interval/position they're returned by Read + Track to allow this program to work. This implementation should be + precise enough for ST/MSA disk images. (fix ProCopy 1.50 in Analyze + mode) + [727368dd7dbf] + +2011-09-30 Nicolas Pomarede + + * src/fdc.c: + Fix delay error for FDC Read Address (bad macro expansion) + [5abe5ea82767] + + * src/fdc.c: + Update ID_FieldLastSector during the Read Track command When a Read + Track command is followed by some Read Address commands, we must + return each ID Fields in the same order they appeared during the + Read Track command (fix Terminators Copy in Analyze mode) + [08da7a4a7cbc] + + * src/fdc.c: + Correctly reset FDC_DMA.BytesToTransfer in case the revious DMA + transfer did not finish (fix X-Out on Pompey Pirates 27, does a read + address after an interrupted read sector command) + [faac32aa681f] + +2011-09-29 Nicolas Pomarede + + * src/fdc.c: + Improve timing for FDC's Read Address by adding a delay to find the + next sector Before the FDC can read the ID Field, it must first let + the disk spin until it reaches the start of the next sector. We can + approximate this delay to an average 600 bytes (512 bytes per sector + + GAPs) (fix "analyze disk" in Terminators Copy 1.68 which expects + Read Address to take several 1/200 sec) + [d977f5941bf6] + +2011-09-26 Nicolas Pomarede + + * src/fdc.c: + Update FDC's Write Protect bit after a Type I command + [0e609cfbd51c] + + * src/fdc.c: + Include call to FDC_AcknowledgeInterrupt into FDC_CmdCompleteCommon + [847db30c7ceb] + +2011-09-25 Nicolas Pomarede + + * src/fdc.c: + More comments' updates in the FDC code + [0da3393fe674] + + * src/fdc.c, src/hdc.c, src/includes/fdc.h: + Reorder FDC functions and add prototypes, update comments + [76a6c9e94cfc] + + * src/fdc.c: + Replace FDC_SetReadWriteParameters with FDC_GetSectorsPerTrack Also + remove useless calls to FDC_SetDiskControllerStatus and to + FDC_UpdateDiskDrive + [99b5bb872666] + +2011-09-23 Nicolas Pomarede + + * src/fdc.c: + Update comments + [3162ca399613] + + * src/fdc.c, src/includes/fdc.h, src/mfp.c: + Remove old fast floppy mode triggered when reading bit 5 of MFP_GPIP + register + [ff64688e23e4] + + * src/fdc.c: + Success/failure in FDC commands should not change DMA status' bit 0 + (DMA error) + [32e4c45ad897] + +2011-09-22 Nicolas Pomarede + + * src/fdc.c: + Rename FDC DMA Status/Mode variables + FDC_ResetDMA should only + reset DMA buffer, not sectors count Bit 0 (DMA error) in + FDC_DMA.Status ($ff8606) seems to be always 1 on ST (no DMA error), + so we always set it to 1 on reset and don't update it later anymore. + [cafae3b0677d] + +2011-09-21 Nicolas Pomarede + + * src/fdc.c: + Remove old variable DiskControllerStatus_ff8604rd, use FDC.STR + instead + [4f30b21b2c43] + + * src/fdc.c, src/hdc.c, src/includes/fdc.h, src/ioMemTabFalcon.c, + src/ioMemTabST.c, src/ioMemTabSTE.c, src/ioMemTabTT.c: + Intercept read/write of hi/med/low DMA address bytes at + $ff8609/0b/0d (add traces) + [8b523edc2722] + + * src/fdc.c: + FDC 'Write Protect' bit should only be updated after a write command + [f6c97ffeba1c] + +2011-09-20 Nicolas Pomarede + + * src/fdc.c: + Remove old case for read/write sectors with multi bit=1 + [31bd713e1ba8] + + * src/fdc.c: + FDC_VerifyTrack should be called when the Verify bit in type I + commands is 0 + [1f108ef7f21f] + + * src/fdc.c: + Not all commands set RNF bit when no disk is inserted, don't set it + in all cases + [d67296474659] + + * src/fdc.c: + In FDC, merge Step, Step In and Step Out into one common Step + function (with a direction) + [044eb8fe2bcb] + +2011-09-19 Nicolas Pomarede + + * src/memorySnapShot.c: + Change snapshot version, new FDC structure is no more compatible + with Hatari 1.5 + [725106d8ea5a] + + * src/fdc.c: + In FDC_VerifyTrack, set RNF if not disk is inserted + [1e767edad856] + + * src/fdc.c, src/hdc.c, src/includes/fdc.h: + Clean up FDC code, reorder, rename variables + - Use names from the datasheet for the WD1772 registers + - Group FDC and DMA variables into some structures + - Remove useless intermediate variables from old FDC code + - Update memory snapshot to correctly restore FDC/DMA states + [c3f731b9247c] + +2011-09-17 Nicolas Pomarede + + * src/fdc.c: + Remove unnecessary intermediate variables and old DMA transfer + function + [10cf8366c12e] + + * src/fdc.c, src/floppy.c, src/includes/floppy.h: + In FDC, add accurate DMA transfer for Write Sector (512 bytes per + sector for ST/MSA) + [0e61679c440e] + +2011-09-15 Nicolas Pomarede + + * src/fdc.c: + Improve DMA transfer function to never write outside of the + DMADiskWorkSpace buffer + [4212862c8982] + +2011-09-14 Nicolas Pomarede + + * src/fdc.c: + In FDC, add accurate DMA transfer for Read Track This will fix a lot + of cracked games in ST/MSA where the protection that uses Read Track + was not disabled, only the result of the test is ignored by the + crack. In that case, we need a correct Read Track, even if the + content of the track is ignored later. + [360f6e46908f] + + * src/fdc.c, src/floppy.c, src/includes/floppy.h: + Return the sector's size in Floppy_ReadSectors (512 bytes for ST/MSA + images) + [580ecaa3c572] + + * doc/compatibility.html: + Remove FDC issues for 'ST-NICCC 2000' by Oxygene + [bce0608352db] + + * src/fdc.c: + In FDC, add accurate DMA transfer for Read Address + correct DMA + transfer routine + [3c469d058484] + +2011-09-11 Nicolas Pomarede + + * src/fdc.c: + For FDC 'Read Sector' command, transfer data between DMA and RAM by + blocks of 16 bytes The DMA has an internal 16 bytes buffer which is + transfered to RAM once 16 bytes have been received from the FDC. DMA + address at $ff8609/0b/0d is updated each time 16 bytes are + transfered while reading a sector. + [a055899d2cc7] + +2011-09-06 Nicolas Pomarede + + * src/fdc.c: + In FDC, correct CRC in the Read Address command and add support for + the Read Track command. Read Track will return 6250 bytes containing + the sectors data, as well as all the GAPs, Index fields and Sync + bytes present in a track. Those 6250 bytes are built by reading the + sectors of an ST/MSA disk image and adding some standard GAPs. This + should fix a lot of games were protection code is run, but the + result is ignored by the crack. + [65faad71a2a4] + +2011-08-30 Nicolas Pomarede + + * src/fdc.c: + Add support for the FDC Type III command Read Address The returned + ID Fields are built from the ST/MSA disk image (512 bytes per + sector, 9 or 10 sectors for all tracks). + [0ee5e33c3a2a] + + * src/includes/utils.h, src/utils.c: + Add functions to compute a CCITT CRC16 (used by the FDC) + [07a6c305af6a] + +2011-08-28 Nicolas Pomarede + + * src/fdc.c: + Rewrite FDC Type II command Write Sector, with correct support for + multi sectors bit and DMA transfer Fix bug in + FDC_ReadSectorFromFloppy / FDC_WriteSectorToFloppy : they should not + increase track/sector themselves + [42c7f2da845d] + + * src/fdc.c: + Update TR00 bit in the FDC's Status Register after a type I command + [e0bd9c4cf8d4] + + * doc/compatibility.html: + Remove FDC issues for 'Just Buggin' by ACF and 'Super Monaco GP' + [fd52d4d9726c] + + * src/fdc.c: + Rewrite FDC Type II command Read Sector, with correct support for + multi sectors bit and DMA transfer The Read Sector command with + multiple sectors mode is used in many games and the previous wrong + version prevented a lot of them to work. DMA transfer was not + correctly handled too. (fix 'Just Buggin' by ACF, 'Super Monaco GP' + on Superior 65, 'Pang' on Fuzion 32, 'The Simpsons' on Fuzion 108) + [9435f0c056d1] + +2011-08-27 Nicolas Pomarede + + * src/fdc.c: + Rewrite FDC Type I commands to be closer to the behaviour described + in the official documentation This takes into account bit 4 (Update + Track) for Step/Step In/Step Out, as well as bit 2 (Verify Track). + The physical track of the head (which can be different from the + Track Register) is also emulated now and used to read/write sectors + from the disk image. + [94e36f1c363d] + + * src/fdc.c: + When FDC is busy, Track Register and Sector register can't be + modified + [c19b865a739d] + + * src/fdc.c: + When FDC receives 'Force Interrupt', remove busy bit and stop the + motor + [808786d9cf4d] + +2011-08-26 Nicolas Pomarede + + * src/fdc.c: + When FDC is busy, the only possible command is 'Force Interrupt' + [d8ddbe092005] + + * src/fdc.c: + Split some FDC define's between type I and II/III + [4b74ad7887c3] + +2011-08-25 Nicolas Pomarede + + * src/fdc.c: + Add correct delay for starting/stopping the motor before/after each + fdc command The motor can take 6 spins to start if it was not + already ON, and it will stop 2 seconds after the last command is + completed. + [b80d83522015] + +2011-08-10 Nicolas Pomarede + + * src/fdc.c: + Improve FDC by adding more accurate timings for each commands (seek, + read sector, ...) Not all timings are completly correct for now, but + this should greatly improve many cracked games that still perform + the FDC operations to check the protection and expect the result to + take a certain amount of time. Also temporarily disable "fast fdc" + mode. (fix Knightmare / DBUG 24) + [87b873bf5ab0] + +2011-08-07 Eero Tamminen + + * src/change.c: + trigger emulation reset if user changes WinUAE address mode + [ba1a54c9cda2] + + * src/convert/high640x8.c: + fix: take SDL buffer pitch (full width) into account + + (Mono conversion was the only one missing this. Even if code gets + requested resolution, pitch could in theory be larger than the + requested width.) + [d71e42ccfdb6] + +2011-08-07 Nicolas Pomarede + + * src/gui-sdl/sdlgui.c, src/includes/sdlgui.h: + Variables should not be defined in the header file, else the linker + will complain As 2 variables were defined in the header, this + created multiple copies of these 2 variables in each file that + included sdlgui.h and this gave warnings when using "ld --warn- + common" Those variables should be declared as extern in the header + and defined only once in sdlgui.c + [8fd078a49e75] + +2011-08-04 Eero Tamminen + + * src/tos.c: + improve the gemdos HD emu message + [3606bc6391d0] + + * src/tos.c: + warn if using HD emu with TOS <1.04, fix typos in other messages + [501b88f0e1c9] + +2011-07-30 Eero Tamminen + + * src/statusbar.c: + more debug to statusbar code + + (was needed to find out why keepDesktopResolution for ST/E triggered + statusbar assert on reboot.) + [5872d98814da] + +2011-07-31 Nicolas Pomarede + + * src/ikbd.c: + Don't clear bytes in transit in the ACIA when the IKBD is reset This + was a regression introduced since rev 3315. (fix Overdrive by + Phalanx, could lock when returning to the menu) + [421d25ee4214] + +2011-07-30 Nicolas Pomarede + + * src/video.c: + Add blank line detection in STF mode when switching 60/50 Hz at + cycle 28 (fix/improve Spectrum 512 scrolling in Overscan Demos and + shforstv by Paulo Simoes) + [cb105e3f19f3] + +2011-07-19 : *** Version 1.5.0 *** + +2011-07-19 Nicolas Pomarede + + * doc/doxygen/Doxyfile, doc/release-notes.txt, hatari.spec, src/gui- + osx/English.lproj/InfoPlist.strings, src/gui- + osx/French.lproj/InfoPlist.strings, src/gui-osx/Info-Hatari.plist, + src/includes/main.h, src/memorySnapShot.c: + New release 1.5, increase version in corresponding files + [d03e4a887e3a] [tip] + + * src/avi_record.c: + Use 65536 for Fps_Scale instead of 16777216, as some video players + don't support values above 100000 For example, this fixes some + warnings/errors ("timebase is very high") when using ffmpeg to + convert the .avi file to a .mov quicktime file. + [62353df26531] + +2011-07-18 Laurent Sallafranque + + * doc/compatibility.html: + Rainbow2 and moai96 comments changed + [05c21ae0c497] + + * src/falcon/videl.c, src/falcon/videl.h, src/ioMemTabFalcon.c, + src/video.c: + fix: added VFC counter in video.c. This allows rainbow2 multimedia + to work. This patch will be removed when Videl emulation is ready. + [100e3be38f40] + +2011-07-18 Nicolas Pomarede + + * src/memorySnapShot.c: + Typo + [f5841e11232b] + + * src/memorySnapShot.c: + Remove conflicting mkdir declaration when building Windows binary + with WinUAE cpu + [3fd84456e225] + + * src/ide.c: + Remove possible conflicting TCHAR declaration when building Windows + binary + [21624f2f76c9] + +2011-07-17 Nicolas Pomarede + + * src/video.c: + Temporary fix for simultaneous HBL case not completly handled in rev + 1624 (fix European Demos Intro screen) + [d6e419fb0f47] + + * src/dmaSnd.c: + Don't reset LCM1992 on warm reset (the chip has no reset pin) + [a11ea38fd26b] + + * src/dmaSnd.c: + Add more traces when changing microwire's values + [7ee1f7b47b3e] + +2011-07-16 Nicolas Pomarede + + * src/dmaSnd.c: + If DMA audio is enabled with frame start = frame end, stop it if + loop mode is off + [6c12214cddfb] + + * src/dmaSnd.c: + When pulling a byte from the FIFO, check DmaSnd_FIFO_Refill() really + added some new byte In the case where DMA is disabled or frame start + = frame end, no new bytes will be added to the FIFO, so we must play + empty samples. (fix 'Brace' by Diamond Design) + [98e6f156a2e3] + + * src/dmaSnd.c: + Clear DMA audio registers even on warm reset + clear frame start/end + addresses When started in STE mode, the demo 'Brace' by Diamond + Design starts the DMA audio without setting frame start/end + addresses, which can result in bad samples if those registers are + not cleared during the reset (this looks like a bug in the demo + anyway). + [dc39860bc47a] + + * src/sound.c: + Remove old code previously used to compute number of samples per VBL + [92bc52e0fe2e] + + * src/change.c: + Remove redundant call, init function is already called in + Configuration_Apply() + [d52b7742dba4] + + * src/gui-sdl/dlgSystem.c: + Clocks' init function should not be called from the dialog, it's + done when new config is applied + [5f05f0779940] + + * src/change.c: + Remove redundant call, init function is already called in + Configuration_Apply() + [51913c0eeded] + + * doc/release-notes.txt: + Add note about more precise frame per sec values + [071c7867a542] + + * doc/todo.txt: + Remove STE's DMA sound from the todo list, sound should be correct + now + [0bf7ced4269f] + + * src/gui-sdl/dlgScreen.c: + Use a define instead of a direct value + [8700e730d3fb] + + * src/cycInt.c, src/dmaSnd.c, src/includes/cycInt.h, + src/includes/dmaSnd.h: + Remove INTERRUPT_DMASOUND, this is not needed as DMA sound is + updated on each HBL + [8110561b47a9] + + * src/dmaSnd.c: + Add more info in some traces + [3dca683da1b5] + + * src/dmaSnd.c: + Remove unnecessary mask + [e30e78e2ae02] + + * src/dmaSnd.c: + Remove old DMA code, add new variables to the memory snapshot + [458ae0b8c3db] + + * src/dmaSnd.c: + Removed unused FIFO functions + [e63d06f680dc] + +2011-07-15 Nicolas Pomarede + + * src/ikbd.c: + Include ACIATxDataRegister in memory snapshot + [19b7369a62fb] + + * src/clocks_timings.c, src/gui-osx/SDLMain.m, + src/includes/clocks_timings.h, src/main.c, src/shortcut.c: + Use a more explicit define to shift number of VBL per sec + [ab7ac15839ec] + + * src/avi_record.c, src/gui-osx/SDLMain.m, src/gui-sdl/dlgScreen.c, + src/includes/avi_record.h, src/main.c, src/shortcut.c: + Add support for non integer frame rate when recording video A real + STF/STE/... doesn't produce video at exactly 50 or 60 HZ, the avi + recording functions now support such non integer rate (eg 50.053 FPS + for STE PAL) This should give the most accurate way to record + video/audio output at the exact timing it was played on a real + machine. + [ef43fd8cd5b1] + +2011-07-15 Laurent Sallafranque + + * src/cpu/newcpu.c: + fix: take into account do_cycle cycles in do_specialties. This allow + STOP instruction to work with the new cpu and this let some demos + work again with the new cpu + [644b422a7c2f] + +2011-07-14 Nicolas Pomarede + + * src/includes/ioMem.h: + Add function for IO regs that return $OO instead of $ff + [60ff3344f1a8] + + * src/ioMem.c, src/ioMemTabFalcon.c, src/ioMemTabSTE.c, + src/ioMemTabTT.c: + Some unused video registers return $00 instead of $ff when read For + STE and Falcon, this was verified on real machine. For TT, use the + same behaviour as Falcon for now (not verified) + [41f4bfcbf897] + + * src/main.c: + Correct multiplication overflow due to bad cast, this could cause + Hatari to freeze after an hour or so + [6b0218bf0e52] + + * src/sound.c: + Don't print warnings about slow sound if audio's output is disabled + [390e1e4a4de3] + + * src/ikbd.c: + Don't clear bytes in transit when ACIA_Reset is called Since rev + 3315, this is needed by Froggies Over The Fence's menu to exit + properly, but official 6850 datasheet is not very clear about this, + could be something wrong somewhere else in the acia's emulation. + [3969372e9ebb] + +2011-07-12 Nicolas Pomarede + + * src/ioMemTabSTE.c: + Add 'todo' note about some STE's video registers that should return + 0 when read + [4b1dfb03b2cb] + + * src/video.c: + Update comments about bits 2-7 when reading $ff8260 + [7d36e14be668] + +2011-07-11 Nicolas Pomarede + + * src/gui-osx/SDLMain.m, src/gui-osx/Shared.h, src/gui-osx/Shared.m: + Patch by Deniz Turkoglu to remove some warnings when compiling under + OS X + [cc422de3973a] + + * src/video.c: + Only set unused bits of $ff8260 to 1 in STF mode, not in STE mode + (fix running BITS intro #54 in STE mode) + [92dbad2b1772] + + * src/dmaSnd.c: + For DMA sound, remove anti-aliasing from the low pass filter (patch + dy D. Savinkoff) + [7c9f63c03fcf] + +2011-07-10 Nicolas Pomarede + + * doc/compatibility.html: + Fix html typo + [b0f5bb5b8b5a] + + * src/dmaSnd.c: + Correct STE's DMA sound when user chooses a low frequency for the + sound's output + [c49f7bdf11ee] + +2011-07-09 Nicolas Pomarede + + * doc/compatibility.html, src/sound.c: + Better handling of internal audio's buffer when fast forward or + slowdown happen In fast forward mode, the audio's indexes were + incorrectly reset, which could cause some errors in the number of + generated samples per VBL, and could cause some programs to crash + (especially those using STE's DMA audio counters) (fix Music Dreams + II by Electronic Images and Songs Of The Unexpected by OUCH) + [a9c736a221ca] + +2011-07-05 Nicolas Pomarede + + * doc/release-notes.txt: + typo + [627f18ae3eb3] + +2011-07-05 Nicolas Pomarede + + * doc/release-notes.txt: + Add some notes about sound/dma audio improvements + [d2a689f19190] + + * src/main.c: + Fix problem when Hatari would not react if paused for more than 2147 + seconds. + [375fcc611859] + +2011-07-04 Nicolas Pomarede + + * src/clocks_timings.c: + Add more explicit TODO in the comments regarding Mega STE/TT/Falcon + [3b62e5d277c9] + +2011-07-05 Eero Tamminen + + * doc/emutos.txt: + more demos compatible with EmuTOS + [c2f327699ace] + +2011-07-04 Nicolas Pomarede + + * src/clocks_timings.c: + Fix comment + [3a569a5e50e0] + + * doc/compatibility.html: + spec512 mode is now working in med res too + [2e625b262b00] + + * doc/compatibility.html: + The issues where combining STE's 224 bytes overscan with horizontal + scrolling are gone + [a60cc4ce3ca4] + +2011-07-02 Nicolas Pomarede + + * src/sound.c: + For YM2149 clock's frequency, use the value defined in + clocks_timings + [c73fce901308] + + * src/includes/clocks_timings.h: + MachineClocks structure should be declared as 'extern' + [753e433dcf17] + + * src/dmaSnd.c, src/video.c: + Mega STE's DMA sound and video shifter are working like the STE's + ones + [b8f966115ddd] + + * src/statusbar.c: + Handle Mega STE in status bar + [ab42f051b090] + +2011-07-01 Nicolas Pomarede + + * src/dmaSnd.c: + On STE, Sound Mode Control for DMA audio should be 0 after a reset + [7609d8d1711e] + +2011-06-26 Thomas Huth + + * cmake/DistClean.cmake: + Remove install_manifest.txt during distclean + [f097454f15cb] + + * CMakeLists.txt, cmake/Uninstall.cmake: + Added 'uninstall' target + [d9963ef43aee] + + * .hgignore: + Ignore all packed manual pages + [acff8c137c33] + +2011-06-20 Eero Tamminen + + * doc/manual.html: + fixes for debugger variables documentation + [da8e4993c8a5] + + * doc/manual.html: + fix manual w3c validator errors and internal links + [aa09199892bd] + + * readme.txt: + add some notes to readme.txt on packaging Hatari for Linux + [92878536a690] + +2011-06-20 Thomas Huth + + * tests/debugger/Makefile, tests/debugger/makefile: + Renamed Makefile to makefile so that this file does not get removed + anymore during 'make distclean' from the main directory + [e10b50045a1a] + + * src/configuration.c: + A non-existing configuration file is not fatal, so down-graded the + message level to debug + [4c6217e63292] + +2011-06-19 Thomas Huth + + * CMakeLists.txt: + Introduced ETCDIR so that the path for the global configuration file + can be set by the user + [e14ce1d98bb1] + +2011-06-19 Eero Tamminen + + * doc/todo.txt: + update winuae/debugger todos + + (reorder a bit to more likely implementation order) + [d5b64161ac84] + + * src/debug/debug_priv.h, src/debug/debugcpu.h, src/debug/debugdsp.h, + src/reset.c: + re-set CPU&DSP debugger flags after reset if there are breakpoints + etc + [687830a03e51] + + * doc/manual.html: + add debugger Usage examples section, update build instructions for + CMake (+ some misc changes) + [946df9d55e44] + +2011-06-18 Eero Tamminen + + * doc/emutos.txt: + more items to emutos compat list + [b64303176318] + + * doc/manual.html, src/debug/breakcond.c: + rewrite/update/reorder/expand debugger documentation, especially for + breakpoints + [9a915e6c05bf] + + * src/debug/breakcond.c: + update & improve breakpoint help texts, remove overlapping info + [ced7137d31db] + + * doc/manual.html, doc/release-notes.txt, doc/todo.txt, + src/debug/debugcpu.c, src/debug/debugdsp.c, src/debug/evaluate.c, + src/debug/evaluate.h: + accept register/symbol/variable names for ranges to allow them for + memdump & disasm commands + [b59a4d2d5017] + + * tests/debugger/test-dummies.c: + add new test dummies for the new debugInfo.c functions + [ac144e6cbbc4] + +2011-06-15 Laurent Sallafranque + + * doc/compatibility.html: + change mouse trap game compatibility with new winuae core. + [327ceee69cd3] + +2011-06-15 Eero Tamminen + + * doc/manual.html: + polish debugger section, remove now redundant LEDs info + [d251bad249ec] + +2011-06-14 Eero Tamminen + + * doc/todo.txt: + add list of missing debugger features from Steem + update other + todos + [c7e0b38c1058] + +2011-06-13 Nicolas Pomarede + + * doc/compatibility.html, src/ikbd.c: + Add custom IKBD routine for Chaos A.D. by DNT Crew (used to decode + the protection) + [c6d92e5087e6] + +2011-07-01 Nicolas Pomarede + + * src/dmaSnd.c: + New STE's DMA audio engine with much improved accuracy and sound + quality This new version emulates the DMA's 8 bytes FIFO and gives + results nearly identical to a real STE when comparing the DMA audio + address counter, resulting in an almost perfect sound emulation with + no more noise/clicks sounds. (fix Hextracker by Paulo Simoee) + [12cc0d539ef8] + +2011-06-24 Nicolas Pomarede + + * src/main.c: + Use ClocksTimings_GetVBLDuration_micro to accurately compute the + duration of the emulated VBL + [4a810e2dbaa4] + +2011-06-23 Nicolas Pomarede + + * src/dmaSnd.c: + Remove unnecessary '|1', both values are even + [c0b498085f4d] + + * src/dmaSnd.c: + Use 64 bits counter to increase the precision of the emulated DMA + audio's frequency Upper 32 bits are used for the integer part ; this + also simplifies the code + [94fd2ffdae6a] + +2011-06-21 Nicolas Pomarede + + * src/sound.c: + Major accuracy improvements for STE DMA sound + - In Sound_Update_VBL(), use the functions from clocks_timings.c to + precisely determine the number of samples needed to emulate one + VBL of audio data (a real PAL STE doesn't have a fixed video freq + of 50 Hz, but of 50.053 Hz) We take into account the CPU clock as + well as the number of cycles per VBL for each type of emulated + machine to compute SamplesPerFrame. + - In Sound_SetSamplesPassed, the returned number of samples to + generate for the current call of Sound_Update_VBL could sometimes + create more than SamplesPerFrame samples per emulated VBL, which + could create a very noisy sound output. This results in a much + better sound quality, as well as nearly perfect CPU/video/audio dma + synchronisation under STE. Hatari's DMA frame counter should now be + identical to the one measured on a real STE (except the 8 bytes DMA + FIFO which is not emulated yet) (fix Audio/Video sync issues in + 'More Or Less Zero' by DHS, 'Hextracker' by Paulo Simoes) + [e136600b88ce] + + * src/clocks_timings.c: + Add example in comment + [f225c5697540] + + * src/dmaSnd.c: + Add debugging trace + [d89332839af2] + +2011-06-19 Nicolas Pomarede + + * src/dmaSnd.c: + Always call Sound_Update() when changing DMA sound control register + $ff8900 Previous versions were calling Sound_Update() only when DMA + audio was stopped but not when it was started, which means that if + DMA was started at the middle of a VBL, we would generate DMA + samples for the whole VBL instead of first generating no sound for + 0.5 VBL followed by 0.5 VBL of sound where DMA is enabled. This + would play more DMA samples than expected and create bad sound + because current DMA address would be beyond its expected value at + the end of the VBL (end of DMA frame would happens sooner than + expected) + [950e18dc2295] + +2011-06-13 Nicolas Pomarede + + * src/clocks_timings.c: + Remove debug printf + [21429ca2bc2d] + +2011-06-12 Nicolas Pomarede + + * src/clocks_timings.c: + Remove useless #include + [4a4d5ea043fc] + + * src/change.c, src/configuration.c, src/gui-sdl/dlgSystem.c, + src/main.c, src/tos.c: + Call ClocksTimings_InitMachine() when the emulated machine type is + changed (STF, STE, Falcon, ...) + [df8c0a09d846] + + * src/CMakeLists.txt, src/clocks_timings.c, + src/includes/clocks_timings.h: + Add clocks_timings.c to the source tree + [065cb494bb3f] + +2011-06-12 Eero Tamminen + + * src/debug/evaluate.c: + match order = variables, registers, symbols order like for + breakpoints + [7a63ea3ae030] + +2011-06-11 Eero Tamminen + + * etc/README, etc/n810.cfg, etc/win-ce.cfg, etc/wiz.cfg: + update example etc/ files for latest configuration state + [7dbae8189806] + + * doc/todo.txt, readme.txt: + slightly more info on missing WinUAE stuff + [27cc2b0d685e] + + * doc/manual.html, doc/release-notes.txt, src/debug/breakcond.c, + src/debug/debugInfo.c, src/debug/debugInfo.h: + Add DATA & BSS debugger variables and rename BasepageTextSegment to + TEXT + [3bd5e0430cf7] + +2011-06-09 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [93382453133e] + + * src/debug/debugInfo.c: + countrycode: cz->cs, see http://en.wikipedia.org/wiki/.cs + + (and the language code is "cs" too.) + [f71818912d5b] + +2011-06-07 Eero Tamminen + + * src/debug/debugInfo.c: + move cookiejar address to cookiejar subcommand + [38ab3cd89828] + + * src/debug/debugInfo.c: + add cookiejar & language info to debugger OS information + [a93f5734577e] + + * doc/manual.html, doc/release-notes.txt: + document BasepageTextSegment debugger variable + [a1642b4315ff] + + * src/debug/breakcond.c, src/debug/debugInfo.c, src/debug/debugInfo.h: + add BasepageTextSegment debugger/breakpoint variable + [39d322def718] + +2011-06-05 Nicolas Pomarede + + * doc/compatibility.html: + Update status for Pandemonium Demos by Chaos + [f78b37f28b2e] + +2011-06-01 Eero Tamminen + + * doc/compatibility.html: + explain WinAUE issue slightly better in compat list + + (There are actually quite a lot of DSP programs that happened to + work in v1.4 with the old AUE core that aren't anymore working with + it and which need WinAUE core.) + [10c8205b6d35] + + * doc/compatibility.html: + Ultimate Arena works now: + + It crashed occasionally with earlier Hatari versions, assumably + because DMA register $ff8901 wasn't handled correctly in Crossbar + [6187d1f6a629] + +2011-06-01 Laurent Sallafranque + + * src/falcon/crossbar.c: + fix bus error ($ff8901) in falcon mode. (this let voice.prg, + conquest of elysium and some other programs to work now). + [72087e7307f8] + +2011-05-31 Nicolas Pomarede + + * src/includes/configuration.h: + Add a specific machine type for 'Mega STe' Although mostly similar + to the STe, the Mega STe has a few differences : 8/16 MHz 68000 cpu, + CPU cache, optional FPU, HD floppy, ... + [c05696155ecc] + +2011-05-25 Nicolas Pomarede + + * src/main.c: + Rename Clock_GetTicks/Clock_Delay to Time_GetTicks/Time_Delay It's + better to keep "clock" to refer to the MHz frequencies of the + different components of an Atari computer + [cc8f153cbbe3] + +2011-05-24 Laurent Sallafranque + + * doc/todo.txt: + Update todo list. + [cf52ae8a1f1c] + +2011-05-23 Eero Tamminen + + * src/includes/stMemory.h, src/stMemory.c: + fix printf warning from newer gcc (hopefully, I have only older gcc) + [0d575f03c4a6] + + * src/debug/debugui.c, src/includes/options.h, src/main.c, + src/options.c: + more option parsing arg consting to get rid of gcc 4.6 const + warnings + [3f1abe99f26e] + +2011-05-22 Eero Tamminen + + * src/debug/debugInfo.c: + overscan mode has ORed flags, fix + [d34fdaa2442e] + + * src/cfgopts.c: + cleanup / fix configuration file handling: + + * fgets() returns NULL both on errors & EOF and that NULL is passed + through by Str_Trim(), so check Str_Trim() return value instead of + relying on feof() to fix error handling. + + * use string returned from Str_Trim() instead of string that's given + to it as argument (both work as Str_Trim() modifies the arg, but + the idiom is to use its return value and that fixes Clang warning) + + * as fgets() reads only a single line and string trimming removes + white space at both ends of the string, there's no point in giving + \n & \r as delimeters for strtok(), so use just "=" + - supporting multiple delimeters would also be confusing + + * check "next" validity returned by further strtok()s calls to + avoid potential segfaults when checking token types and values. + - don't anymore accept "key" as equivalent of "key=" (which the + previous code did, but only for string types) + + * Remove redundant & broken strtok() call and resulting redundant + "next" variable from update_config() + - Fixes Clang & GCC 4.6 warning + [0b10ee3dd607] + + * src/debug/breakcond.c: + show also locked info after breakpoint info (same change as for + "file" option) + [50e2938d85d2] + + * doc/release-notes.txt, src/debug/debugInfo.c: + "video" subcommand for the debugger "info" command (for showing + video related Hatari variable values/info) + [2bdb8e92e050] + +2011-05-22 Nicolas Pomarede + + * src/video.c: + Remove unused variable bScreenChanged + [29578450ae82] + +2011-05-22 Eero Tamminen + + * src/video.c: + set global variables that aren't used outside of video.c as static + [4512065d5a03] + + * src/gemdos.c: + fix Clang reported uninitialized variable and potential NULL pointer + use in gemdos.c + [1f7cb302c349] + + * src/floppy.c: + move unused debug variables inside ifdef + + (Clang complainment) + [616e3e78a36d] + + * src/hdc.c: + fix undefined hdc.c variable value use reported by Clang + [c6556b8be41c] + + * src/xbios.c: + update xbios debug stuff (complained by Clang) + [2a4a2def2908] + + * src/debug/profile.c, src/falcon/videl.c: + remove redundant assignments reported by Clang + [247607093b75] + + * src/gui-sdl/dlgFileSelect.c, src/gui-sdl/sdlgui.c: + remove redundant variables from SDL GUI code reported by Clang + [0352da822910] + + * src/ioMem.c: + silence (theoretical) NULL pointer access warning from Clang for + ioMem + [55e5664e5560] + + * src/screenSnapShot.c: + remove Clang reported redundant variable from screenshot code + [434c5a11fb91] + + * tools/hmsa/hmsa.c: + fix clang reported hmsa warning output bug + [45dbe40fb4a2] + + * doc/compatibility.html, doc/release-notes.txt, doc/todo.txt: + minor doc updates/fixes in preparation to release + [cea57563a4ef] + +2011-05-21 Eero Tamminen + + * doc/manual.html: + add documentation on chaining breakpoints & other debugger actions + [fa3ef1b2976b] + + * src/debug/breakcond.c: + show :file action output last on breakpoint hit + + (otherwise it's confusing, first you get note about hit, them file + action output, then breakpoint name etc) + [8d310c58db96] + + * tests/debugger/test-evaluate.c: + add test for evaluting internal variables + [d8f472afed09] + + * src/debug/breakcond.c, src/debug/breakcond.h, src/debug/evaluate.c: + allow use of Hatari internal variables in debugger expressions (e.g. + "VBL+4" in breakpoints) + [16a02567b5f1] + +2011-05-20 Nicolas Pomarede + + * src/ikbd.c: + Fix a weird bug in tos 1.02/1.04 when ACIA's TX delay is too big + Although theorical value should be above 7000 cpu cycles, such value + is causing some memory being overwritten by the stack for tos + 1.02/1.04, which can prevent restoring the correct resolution from + desktop.inf (and certainly mess with other things in the memory) ! + Lower the value to 1000 cycles for now, this needs better tests on a + real ST. + [2a7f3d1f3052] + +2011-05-15 Nicolas Pomarede + + * src/dmaSnd.c: + Improved LMC1992 filtering for DMA sound by David Savinkoff + - The IIR filters for bass/treble now control the volume + - Anti-alias filtering is not performed at the 50066 Hz sampling rate + ; better sound and performance + [3947643d642a] + + * src/sound.c: + Remove debug printf + [7ec7998ade7a] + +2011-05-14 Eero Tamminen + + * src/falcon/hostscreen.c, src/resolution.c: + ignore user configured max resolution when --desktop yes is set + + Fixes case where Falcon monochrome isn't zoomed on fullscreen with + the default configuration max window size. + + Add more debug statements to resolution handling + fix one + hostscreen.c one. + [f1e11759798a] + +2011-05-14 Nicolas Pomarede + + * doc/compatibility.html: + 'BBS Intro 3' is now working + [134df05ab3fd] + + * src/uae-cpu/gencpu.c: + Correctly handle address error in UAE's cpu core for JSR and JMP + (fix 'BBS Intro 3' by Lynx which uses this in the 3D routines) + [59d01aea8b52] + + * doc/compatibility.html: + Add note for 'BBS Intro 3' by Lynx not working for now + [a38e173a6574] + + * configure: + Remove previous CmakeCache.txt before running cmake If we run for + example './configure --enable-winuae-cpu' then './configure', the + build will still use winuae's cpu instead of the default uae's one, + which is not the intended behaviour. Removing CMake's cache fixes + the problem + [1329ce80c86f] + +2011-05-13 Eero Tamminen + + * src/resolution.c: + fix: do not force default bitdepth for fullscreen with --desktop + option + + (This breaks ST monochrome mode and isn't needed to get rid of LCD + resolution switch delay for which the --desktop option helps.) + [18e8754365b8] + +2011-05-13 Nicolas Pomarede + + * readme.txt: + Add note about "./configure --enable-winuae-cpu" to use the new + WinUAE's cpu core + [ef39f174a08d] + +2011-05-11 Laurent Sallafranque + + * src/debug/debugInfo.c: + add some video registers to debuginfo videl. Also add size of + registers for videl and crossbar. + [25fe689e6055] + +2011-05-11 Nicolas Pomarede + + * src/ikbd.c: + Better support of bit 1 (TX buffer empty) in ACIA's status register + when writing to $fffc02 When a byte is written in $fffc02 (to be + sent to the ikbd), bit 1 of SR is set to 0 to indicate a serial + transfer is happening. Once the byte has been completly transfered + to the ikbd, bit 1 of SR should be turn back to 1. We use an + internal timer of ACIA_CYCLES to emulate this transfer's delay and + correctly emulate the behaviour of bit 1. (fix 'Pandemonium Demo' by + Chaos) + [ce7891104e5b] + +2011-05-10 Nicolas Pomarede + + * src/debug/log.h: + Trace ikbd_all should not include VDI calls + [1cba95fa459f] + +2011-05-09 Nicolas Pomarede + + * doc/compatibility.html: + Add note for DNT screen in Snork Demo + [e5ba3424a692] + +2011-05-09 Eero Tamminen + + * tests/readme.txt: + add readme for tests + [338a65fc1cb5] + + * doc/compatibility.html, doc/hatari.1, doc/manual.html, doc/release- + notes.txt, readme.txt: + update docs for coming v1.5 release and add notes about WinUAE + [0b6c3f872bb9] + + * doc/midi-linux.txt: + update linux midi notes + [4e53915d0f43] + +2011-05-09 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Typo : AUE -> UAE + [c81447ad3d45] + +2011-05-08 Nicolas Pomarede + + * doc/compatibility.html: + Add note for 'Tyme Warp' not working yet + [271e7e19215b] + + * doc/compatibility.html: + Add note for 'Music Dream II' on STE + [9e71213555e5] + + * src/includes/sound.h, src/main.c, src/shortcut.c, src/sound.c: + Sound_ResetBufferIndex() should only be called just after the sound + was generated for the whole VBL Calling Sound_ResetBufferIndex() + will set CurrentSamplesNb=0, which can interfere with the way we + compute current dma sound address ($ff8909/0b/0d). To avoid problems + in that case, the call to Sound_ResetBufferIndex() should be defered + just after Sound_Update(true) was called to complete the sound + buffer for the VBL. (fix 'Music Dream II' crashing on a red screen + when exiting pause or fast forward) + [4607b3227e3a] + +2011-05-08 Thomas Huth + + * src/CMakeLists.txt: + Use the right variable for linking the variables from the FindX11 + CMake module + [d5cabe4adc87] + +2011-05-01 Eero Tamminen + + * src/fdc.c, src/includes/fdc.h: + cleanup: move things that can be static and aren't needed in fdc.h + to fdc.c + [75b86c628507] + + * src/gemdos.c: + fix to gemdos emu DST handling (bug reported by Uwe on hatari-devel) + [2a595cb7f677] + +2011-04-30 Eero Tamminen + + * src/fdc.c, src/hdc.c, src/includes/fdc.h: + validate fdc.c & hdc.c memory copy address validities + + (fdc.c one fixes Hatari crash with Mental Hangover demo) + [64062150d486] + + * src/includes/stMemory.h, src/stMemory.c: + add stMemory_SafeCopy() + [cf281e76c391] + + * doc/release-notes.txt: + add release notes about Laurent's DSP changes + [45f36c071227] + +2011-04-22 Eero Tamminen + + * src/ikbd.c: + revert IKBD date change, TOS v2 requires BCD with overflow (to show + this century dates correctly) + [3fb2bdaf0487] + +2011-04-30 Nicolas Pomarede + + * doc/compatibility.html: + Fix url on pouet.net + [764788ceaab4] + + * doc/compatibility.html: + 'Bird Mad Girl Show' requires Hatari 1.5 + [4e6e92a24e1b] + +2011-04-29 Nicolas Pomarede + + * doc/compatibility.html: + Add Gen4 demo by Overlanders to compatibility list + [299232266a02] + + * src/uae-cpu/newcpu.c: + While processing an exception, raise an address error exception if + the new PC is not even (fix Gen 4 Demo by Ziggy Stardust / OVR) + [e177e0529b24] + +2011-04-23 Thomas Huth + + * CMakeLists.txt, cmake/config-cmake.h, src/includes/scandir.h, + src/scandir.c: + Added proper CMake tests for alphasort() and scandir() + [fa6f8f180d0e] + +2011-04-22 Thomas Huth + + * src/ikbd.c: + Reverted Eero's bad BCD calculation change + [672bac9e16df] + + * src/ioMemTabTT.c: + TT does not have an Mega-ST(E) compatible RTC chip + [e0bca488de6f] + +2011-04-21 Eero Tamminen + + * python-ui/TODO, python-ui/dialogs.py, python-ui/hatari.py, python-ui + /release-notes.txt: + add --desktop support to Python UI + update TODO + [a705fa981aa4] + + * python-ui/README, python-ui/config.py, python-ui/debugui.py, python- + ui/hatariui.py, python-ui/uihelpers.py: + update python UI copyrights & doc + [ffb75703039f] + + * python-ui/dialogs.py, python-ui/hatari.py, python-ui/release- + notes.txt: + add RTC support to python UI + [5fad5d46a324] + + * doc/hatari.1, doc/manual.html, src/options.c: + add option for enabling/disabling RTC + [f6e55ff31842] + +2011-04-20 Eero Tamminen + + * src/ikbd.c: + fix BCD calculation for IKBD date + [41c79174127b] + +2011-04-14 Eero Tamminen + + * tools/hconsole/hconsole.py: + fix one more python v2 vs. v3 issue in hconsole + [ca8cfadca146] + +2011-04-13 Eero Tamminen + + * doc/emutos.txt, doc/manual.html, doc/release-notes.txt: + minor doc updates + [0217e51b257c] + +2011-04-12 Nicolas Pomarede + + * src/sound.c: + Set default YM Mixing method to 'STF table' instead of 'linear' 'STF + table' is giving much better results when the 3 voices of the YM2149 + are used to play samples. + [fc530888f2b2] + + * src/configuration.c, src/includes/sound.h, src/sound.c: + Call Sound_SetYmVolumeMixing when YM Mixing is changed (rebuild + conversion table) + [0747ee3412a3] + +2011-04-11 Eero Tamminen + + * doc/hatari.1, doc/images/sound.png, doc/manual.html, src/options.c: + add documentation for YM mixing option + [51d2f4cafd46] + + * src/gui-sdl/dlgSound.c: + add YM mixing options to SDL GUI sound dialog + [38649699b323] + +2011-04-10 Nicolas Pomarede + + * src/dmaSnd.c: + Remove unused variable + [c1688c3a9ec8] + + * src/dmaSnd.c, src/includes/dmaSnd.h, src/video.c: + Rename DmaSnd_HBL_Update to DmaSnd_STE_HBL_Update and update DMA + sound on every HBL only for STE (not Falcon) + [377809d1b3f3] + +2011-04-07 Eero Tamminen + + * src/options.c: + add --ym-mixing option + [b0101f140f87] + +2011-04-06 Nicolas Pomarede + + * src/configuration.c, src/includes/configuration.h: + Add YmVolumeMixing to the [sound] section of the config file + [7333e43ffef0] + +2011-04-05 Eero Tamminen + + * etc/README: + add links to info about device mentioned in README + [8e1eabd3d313] + + * etc/README: + update comments for CMake + [a7d993c1b04f] + +2011-04-05 Matthias Arndt + + * etc/GP2X_Wiz/crossdefs.wiz, etc/GP2X_Wiz/hatari-wrapper.gpe, + etc/wiz.cfg: + - initial support for crosscompiling for GP2X Wiz target + (Crossdefs for CMake, config and target wrapper script) + [f0d5387b765c] + +2011-04-03 Eero Tamminen + + * doc/images/screen.png, doc/manual.html, src/gui-sdl/dlgScreen.c: + add "keep desktop resolution" and "drive led" options to screen + dialog + [369f3a3e22eb] + + * doc/manual.html: + split & re-order options in manual similarly to man page + [f536a0a48a56] + +2011-04-02 Eero Tamminen + + * doc/compatibility.html, doc/emutos.txt: + correct Octalyser info from Anders + [8df9f4c43181] + + * doc/compatibility.html, doc/emutos.txt: + update emutos compat list + [6e3652cf0596] + + * doc/compatibility.html: + Protracker STE OK according to Matthias, Octalyzer still flickers + [7c92d1fea7f9] + +2011-04-07 Nicolas Pomarede + + * doc/compatibility.html: + Update DMA sound status for 'Power Up Plus' and 'Mental Hangover' + [18ef05fc8a91] + + * src/dmaSnd.c: + Since DMA sound is updated on each HBL, we don't need an internal + timer anymore to detect the end of frame + [0ac9d5f616ad] + +2011-04-04 Nicolas Pomarede + + * src/dmaSnd.c: + Remove Hatari's internal interrupt when DMA sound is stopped + [4c5ac7bd582c] + + * src/dmaSnd.c: + Create a common function to apply bass/treble filters + [d9ef79bfd0a9] + +2011-04-03 Nicolas Pomarede + + * src/dmaSnd.c, src/includes/dmaSnd.h, src/video.c: + Reorder code, more log, missing include + [9713bc7c2581] + + * src/dmaSnd.c, src/video.c: + On STE, call Sound_Update on each HBL to handle programs that modify + the samples data while DMA sound is ON Some programs are using + single buffer method to build the next sample to be played in the + same buffer used to play the current sample. We need to update the + DMA output on each HBL to be sure to take the correct bytes into + account (generating the whole output only once per VBL would not + work) (fix the game 'Power Up Plus' and the demo 'Mental Hangover' + by The Pixel Twins) + [8f208db51825] + + * src/dmaSnd.c: + Use constant values, DMA sound frequencies are not related to the + CPU's clock + [6e8cbaf128e4] + +2011-04-01 Nicolas Pomarede + + * doc/compatibility.html: + Add comment for 'Bad Taste' not working yet + [4803f9b9c55a] + +2011-04-01 Laurent Sallafranque + + * src/falcon/dsp_disasm.c: + remplace "0x" by $ in all DSP addresses and values when debugging. + [dcaebf6c99d4] + +2011-03-31 Nicolas Pomarede + + * doc/compatibility.html: + Add comment for 'Mental Hangover' by Pixel Twins + [3a9230cb56fc] + +2011-03-29 Eero Tamminen + + * src/debug/log.h: + use GCC "unlikely" feature for the other trace log level check too + [f5a30d4d2d03] + +2011-03-29 Laurent Sallafranque + + * src/falcon/dsp_cpu.c, src/falcon/dsp_disasm.c: + change LogTraceFlags by log.h macro LOG_TRACE_LEVEL(). Made + write_memory inline. Better readability for a and b registers in + disasm mode. + [40fc47accfba] + + * src/falcon/dsp_cpu.c: + remove 2 unuseful defines + [c8d83e1589f7] + + * src/debug/log.c, src/debug/log.h, src/falcon/dsp_cpu.c, + src/falcon/dsp_disasm.c: + add: dsp_disasm_reg and dsp_disasm_mem trace. Now, you can trace DSP + instructions + see the modified registers and the modified memory + fields. To allow dsp_disasm_reg and/or dsp_disasm_mem, dsp_disasm + must be enabled. + [356d537374d5] + +2011-03-27 Nicolas Pomarede + + * src/debug/68kDisass.c, src/sound.c: + Cancel unwanted commit + [9786a1d21efc] + + * doc/authors.txt, src/debug/68kDisass.c, src/sound.c: + StSound's routines for tone/noise are not used anymore + [32325dbe6ab0] + +2011-03-27 Thomas Huth + + * doc/authors.txt: + Updated the authors.txt file. + - Added Deniz Turkoglu + - Added WinUAE + - Make sure that all lines fit the 80 columns limit + [b1170dc78d62] + + * src/gui-osx/English.lproj/SDLMain.nib/designable.nib, src/gui- + osx/English.lproj/SDLMain.nib/keyedobjects.nib, src/gui- + osx/PrefsController.m, src/gui-osx/SDLMain.h, src/gui-osx/SDLMain.m: + Changes to the OS X GUI so that it hopefully compiles again... ... + thanks to Deniz Turkoglu for the patch. + [20b46807e5d6] + +2011-03-26 Nicolas Pomarede + + * src/dmaSnd.c: + When reading DMA sound address at $ff8909/0b/0d, call SoundUpdate + first to update current address (fix 'Music Dream II' by Electronic + Images) + [6aea892b11b1] + + * src/cycles.c, src/uae-cpu/newcpu.c: + Correct video timing for 'move.b $ffff8209.w,xxx.w' (fix 'Bird Mad + Girl Show' loader/protection) + [903c21c349ae] + +2011-03-25 Nicolas Pomarede + + * doc/compatibility.html: + Add note for RGB Plasma by Omega (wrong boot sector caused bus + error) + [a45a874a4040] + + * src/floppy.c: + Fix wrong SectorsPerTrack value when boot sector doesn't match + ST/MSA disk image's size In the case where the boot sector doesn't + contain the correct values for side, sector per track or total + number of sectors, the number of tracks was not taken into account + to guess the correct parameters, which could lead to some errors. + For example, if the BS reported 1600 sectors/10 sectors per track + but the real number of sectors was 1440, then corrected number of + sectors was set to 10 instead of 9 (which means an unlikely 72 + tracks/10 sectors disk was prefered instead of 80 tracks/9 sectors) + This could cause some disk loaders to crash. (fix RGB Plasma by + Omega) + [4afa0450587f] + +2011-03-24 Eero Tamminen + + * src/resolution.c: + check "*width && *height", not "*width && *width" + [4acf972755f9] + +2011-03-23 Eero Tamminen + + * doc/hatari.1, doc/release-notes.txt, src/configuration.c, + src/includes/configuration.h, src/options.c, src/resolution.c: + keep desktop resolution is now enabled by default and a bool option + [1d6e2110addb] + +2011-03-22 Eero Tamminen + + * doc/compatibility.html: + updated compat list according to Nicolas' & Matthias' comments, + tested Mgif DSP functionality + [574d08ce7ed0] + +2011-03-21 Eero Tamminen + + * doc/manual.html: + update manual breakpoint options information + [b5d42e6778f0] + + * doc/release-notes.txt, tests/debugger/Makefile, + tests/debugger/data/test.ini, tests/debugger/test-breakcond.c, + tests/debugger/test-dummies.c: + update breakpoint tests & release notes for new breakpoint options + (+ fix minor issue in test Makefile automation) + [7273375b2a70] + + * src/debug/breakcond.c: + allow multiple options / breakpoint, add ":file" option, rename + ":info" to ":lock" + [818533555b43] + +2011-03-20 Eero Tamminen + + * doc/manual.html: + improve manual debugger texts + [3a9349360a2a] + + * src/debug/debugui.c: + better "lock" debugger command explanation + [2662c2dca1dc] + + * src/falcon/hostscreen.c, src/falcon/hostscreen.h, + src/falcon/videl.c: + fix videl palette[1] on OSX resolution switch by remapping colors: + - I'm not sure whether the updatePalette() call is (still) needed + - patch tries also to speed up videl 32-bit updates by removing an + intermediate function and calling SDL_MapRGB directly + - added HostScreen_getFormat() method for that + - correct some of the used variable types + + [1]It appears that OSX uses different data format for fullscreen + and windowed surfaces. Remapping native color values on resolution + switch was reported to fix the handling for Falcon modes with + palette, but apparently HiColor -> 32-bit conversion has still + some problem. + + (The patch also tries to speed up videl updates a bit by removing + one intermediate hostscreen function call per pixel.) + [1de05185b8ab] + + * doc/hatari.1: + better manual page explanation for window size options + [b93a50f6d0d3] + + * src/debug/debugui.c: + better trace command debugger help + [e55940b3cab8] + +2011-03-20 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + fix: dsp56k_disasm must be called before instruction execution + because some instructions like jmp, jsr, ... change the stack value. + Then, it must be called after instruction execution to get the + number of cycles taken by the instruction. + [79262e80799e] + +2011-03-19 Laurent Sallafranque + + * src/falcon/dsp.c, src/falcon/dsp_cpu.c, src/falcon/dsp_cpu.h: + renamed one function for better understanding + [fc537719c47b] + + * src/falcon/dsp.c, src/falcon/dsp_cpu.c, src/falcon/dsp_cpu.h, + src/falcon/dsp_disasm.c, src/falcon/dsp_disasm.h: + fix and improve DSP trace and DSP disams mode. + [c579c7be51e1] + +2011-03-16 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + add: dsp disasm trace + [1ccac6897d8f] + +2011-03-09 Eero Tamminen + + * src/falcon/hostscreen.c, src/falcon/hostscreen.h: + hostscreen fix/optimization, SDL color channel values are Uint8, not + Uint32 + [59a80cc1f617] + +2011-03-09 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + fix: when dsp encounters an unknown instruction, it loops forever, + and there's no way to stop it but killing the cession. I've added + 100 cycles to allow the user to be able to quit hatari normally. + [f1c25744b93b] + +2011-03-08 Laurent Sallafranque + + * src/cpu/cpummu.c: + fix: change D(bug( ... messages by fprintf messages. This generates + a lot warnings. + [394a26c5da86] + + * src/cpu/newcpu.c: + fix: Hatari now boots in MMU emulation mode (68040 only + MMU). MMU + itself still doesn't work for now. + [8db37b9a0cc5] + +2011-03-05 Thomas Huth + + * doc/manual.html: + Fixed invalid HTML + [36a4450a376d] + +2011-03-04 Eero Tamminen + + * src/options.c: + typo: WinAUE -> WinUAE + [73bb9d7d4ba9] + + * doc/hatari.1, src/options.c: + move WinAUE options under their own heading, improve option + descriptions & order + + WinAUE options being under their own heading (and the options + themselves) may be temporary, we don't know yet which ones they will + be or will we in next release have one or two CPU cores. + [5b84a830651b] + +2011-03-03 Eero Tamminen + + * doc/compatibility.html: + mark keff demo as broken, add (back) info which demos use DSP + Mp2-playback + [22b20535f062] + +2011-03-02 Eero Tamminen + + * doc/hatari.1, doc/release-notes.txt, src/options.c: + add --desktop option + split display options to common, ST/E and + Falcon/TT options + [aec78c031aee] + + * src/configuration.c, src/falcon/hostscreen.c, + src/includes/configuration.h, src/resolution.c: + Add option for using Desktop resolution in fullscreen + + This way one can avoid the long delay LCDs have in resolution + switching and problems it causes with multihead etc. setups. + + This is Falcon/TT (hostscreen/videl) specific because only those + support arbitrary integer scaling values unlike the ST/STE screen + code. + [68abf6896aaa] + +2011-02-23 Laurent Sallafranque + + * src/cpu/custom.c, src/cpu/fpp.c, src/cpu/gencpu.c: + fix: some more likely and unlikely warnings removed + [0e633492235c] + + * doc/compatibility.html: + Update compatibility list : MP2 sound is now OK (except for wait + demo). (I've tagged hatari's version as 1.4+) + [ab36922aed27] + + * src/falcon/videl.c: + fix Videl monochrome monitor from Eero. + [87461cda72e5] + + * src/cpu/cpummu.c, src/cpu/cpummu.h, src/cpu/gencpu.c, + src/cpu/newcpu.c: + fix: remove likely and unlikely warnings + [0734213b4d0b] + +2011-02-21 Eero Tamminen + + * doc/coding.txt: + add coding guideline for "magic" value, update notes on coding style + [32a0384b59bf] + +2011-02-20 Laurent Sallafranque + + * CMakeLists.txt: + return back to old CPU for now + [879e8d126262] + + * CMakeLists.txt, src/ioMem.c: + Changed variable to enum + [0d5edb7c6ea7] + +2011-02-20 Eero Tamminen + + * src/cpu/newcpu.c, src/cpu/newcpu.h: + remove redundant code related to wide-char buf_out() function + + WinUAE has several new functions which use wide-char. buf_out() + buffers the output before it's printed, but it's not used nor + implemented in Hatari port of WinAUE code. As Hatari code prints + information just with printf, buf_out() usage related local + variables, allocations etc can be removed. + + Additionally this fixes the disassembly functions so that they write + the disassembly to correct FILE* given by debugger and it makes + m68k_disasm_2() static as it's not used outside of newcpu.c. + [885a607022eb] + +2011-02-20 Laurent Sallafranque + + * src/ioMem.c: + added a comment + [b87fc4bb6601] + + * src/ioMem.c: + rename variable + [26cb69744a4a] + + * src/includes/ioMem.h, src/ioMem.c, src/ioMemTabFalcon.c, + src/memorySnapShot.c: + add: saving isFalconInSteBusMode variable in snapshots. I've also + renamed it and the function called to change it. + [4a91c73cd3e3] + + * src/ioMemTabFalcon.c: + remove: obsolete comment + [b91c9476ee01] + +2011-02-19 Laurent Sallafranque + + * src/includes/ioMem.h, src/ioMem.c, src/ioMemTabFalcon.c: + code cleaning: only one function for STe compatible bus or Falcon + only bus emulation (relative to register $ff8007.b) + [1c1d95173487] + + * src/ioMemTabFalcon.c: + fix: use correct value for nCpuFreqShift when register $ff8007.b is + changed. + [faa2dc624bb7] + +2011-02-19 Eero Tamminen + + * doc/release-notes.txt, python-ui/release-notes.txt, tools/hconsole + /release-notes.txt: + update release notes + [0c6b32289aa3] + + * python-ui/dialogs.py: + hatari UI: support also AES, Videl, Crossbar & DSP tracing + [1e5891d9d700] + + * python-ui/debugui.py: + debug UI: disassembly is now prefixed with '$', adapt + [a84b3df6ffc3] + + * python-ui/config.py, python-ui/debugui.py, python-ui/dialogs.py, + python-ui/hatari.py, python-ui/hatariui.py, python-ui/uihelpers.py: + hatari UI: partial/preliminary Python v3 support + [aa318a50e4d5] + + * tools/hconsole/hconsole.py: + hconsole: support both python v2 & v3 + [6ec63dd08c0d] + + * src/falcon/videl.c: + videl fix: ST shifter is byte, not word register. Fix typos in + comments + [1c17e5953630] + + * src/falcon/videl.c: + add videl trace point on video mode changes + [cf0c1f7a96ea] + +2011-02-19 Laurent Sallafranque + + * src/ioMemTabFalcon.c: + add : switch from 8Mhz to 16 Mhz or from 169 Mhz to 8 Mhz + ($ff8007.b) + [ef2322597285] + + * src/includes/ioMem.h, src/ioMem.c, src/ioMemTabFalcon.c, + src/stMemory.c: + add: STE bus control compatibility for Falcon. All registers are now + set / unset according to Thomas's tests on Bus error. + [7becc35a0e80] + +2011-02-18 Laurent Sallafranque + + * src/debug/log.c, src/debug/log.h, src/falcon/dsp_core.c, + src/falcon/dsp_cpu.c: + add trace for DSP. Already implemented : dsp host interface + (transmit, receive and host commands), SSI (transmit, receive, + handshake mode), dsp state and dsp_interrupts. Still to do : dsp + instructions, dsp memory and dsp register changes. + [4d1078fb574c] + +2011-02-15 Nicolas Pomarede + + * src/dmaSnd.c: + Fix from David Savinkoff : allows low sample rates to work with the + treble step filter + [99cb3cf237d1] + +2011-02-15 Laurent Sallafranque + + * src/cpu/compat.h, src/cpu/custom.c, src/cpu/newcpu.c, + src/cpu/newcpu.h, src/cpu/sysdeps.h: + fix f_out to allow disasm register with new CPU. Thanks to Eero to + the tip. + [c1aa6b34077b] + + * src/stMemory.c: + Add all memory size allowed by tos 4.04. As register $ff8006 is not + well documented, I believe in TOS code. + [2158985d7c9e] + + * src/audio.c, src/falcon/crossbar.c, src/falcon/crossbar.h: + fix: DMA filters is only for STE/TT. Add for Falcon mode: take into + account the new sound frequency while sound plays. Rendering is OK + now if one change the sound frequency while hatari runs. + [92a98c558c21] + +2011-02-15 Nicolas Pomarede + + * src/audio.c: + Rebuild STE's bass/treble filters when output sound freq is changed + while Hatari is running Previously, the tables were not changed and + remained relative to the old sound freq + [70aa55493b4d] + +2011-02-14 Laurent Sallafranque + + * src/falcon/crossbar.c: + add: test is DSP Play is not tristated before doing a tranfer + between DSP_PLAY and crossbar. + [1783abb0373f] + + * src/stMemory.c: + Added comment about $ffff8006.b register. returned back to Thomas's + original code + [e888217e90b3] + +2011-02-13 Nicolas Pomarede + + * src/dmaSnd.c: + Fix from David Savinkoff : better Bass/Treble filter for output + audio freq < 22 kHz With previous version, there was no audible + sound when Hatari's output freq was < 22 kHz + [68216516bda8] + +2011-02-13 Laurent Sallafranque + + * src/video.c: + fix: call VIDEL function to set correctly bUseSTShifter value. + [e71e0eeeab08] + + * src/falcon/crossbar.c: + rollback to previous code : my patch breaks mouse.prg (conquest of + elysium doesn't work anymore now). + [c5f107e0a777] + +2011-02-12 Nicolas Pomarede + + * src/dmaSnd.c: + Fix typo + [0a3c5c9e763e] + + * src/dmaSnd.c, src/includes/dmaSnd.h, src/ioMemTabSTE.c, + src/ioMemTabTT.c: + Add write logs for all DMA sound registers + [ac6bd12ae9d0] + +2011-02-11 Laurent Sallafranque + + * src/falcon/crossbar.c: + temporary fix: remove bad test in 8 bits mono DMA sound transfer. + This allow Conquest of Elysium to work (without sound for now) + [766657968771] + +2011-02-09 Laurent Sallafranque + + * src/falcon/videl.c, src/falcon/videl.h, src/ioMemTabFalcon.c: + add screen base write to Videl. + [6a7ab1af01fc] + +2011-02-06 Nicolas Pomarede + + * src/ioMemTabFalcon.c, src/uae-cpu/newcpu.c: + merge + [3d4f3f2d8a6f] + + * CMakeLists.txt, cmake/config-cmake.h, src/main.c: + Add detection of gettimeofday() and nanosleep() into cmake. Enable + microsec precise delays in Main_WaitOnVbl This improves VBL + synchronisation with sound when 1/nScreenRefreshRate is not an + integer (eg 60 Hz) + [d003c9e2c365] + + * src/main.c: + In Main_WaitOnVbl, use micro sec instead of milli sec to measure all + delays (Clock_GetTicks and Clock_Delay) If the OS is precise enough, + we use native micro sec precision to get the current clock tick, + else we default to SDL_Delay*1000. + [d482b9b49307] + +2011-02-06 Laurent Sallafranque + + * src/uae-cpu/newcpu.c: + fix typo error. + [a6ea5411b20d] + +2011-02-04 Laurent Sallafranque + + * src/ioMemTabFalcon.c: + Restore old paramter as long as Videl code is not complete. + [f13f9c8bf524] + + * src/ioMemTabFalcon.c: + fix: addresses in videl memory that are not mapped musn't generate + bus errors. + [823b34dea930] + +2011-02-02 Laurent Sallafranque + + * src/falcon/videl.c, src/falcon/videl.h, src/ioMemTabFalcon.c: + add monitor and memory register + some more comments about Videl + registers (this time, I think all registers are referenced) + [352b356e2531] + + * src/stMemory.c: + fix: no need to copy monitor info ($ff8006 bits 6 and 7) into + $ff82c0 register (bits 1-0), because the TOS does it on startup. + [75985302390e] + +2011-02-01 Laurent Sallafranque + + * src/falcon/videl.c, src/falcon/videl.h, src/ioMemTabFalcon.c: + Some more changes for Videl emulation : added all "vertical" + registers + [0a11c3813bc3] + + * src/debug/log.c, src/debug/log.h, src/falcon/videl.c, + src/falcon/videl.h, src/includes/configuration.h, + src/ioMemTabFalcon.c, src/memorySnapShot.c, src/stMemory.c: + more changes to videl code. + [e5264a0c1688] + +2011-01-31 Laurent Sallafranque + + * src/falcon/videl.c, src/falcon/videl.h, src/includes/video.h, + src/ioMemTabFalcon.c, src/memorySnapShot.c, src/video.c: + First changes to videl emulation : prepared some code, removed + bUseSTShifter variable from video.c as this is a Falcon specific + variable. Added snapshot save/restore to videl. + [9c1811f935b7] + +2011-01-31 Eero Tamminen + + * doc/todo.txt: + add some TODOs + [4be4b4316e1c] + +2011-01-30 Laurent Sallafranque + + * src/falcon/crossbar.c: + fix: clear dac (left/right) value when read. Else, some programs + stop feeding this buffer, but it loops with the last datas. This + also solve the "diesel engine" sound generated by some programs or + when one reset hatari. + [734bd666377b] + +2011-01-30 Eero Tamminen + + * python-ui/dialogs.py, python-ui/hatari.py, python-ui/release- + notes.txt: + add capture crop support to python UI + finetune other options + [17583c685208] + + * src/configuration.c, src/includes/m68000.h, src/m68000.c, src/tos.c: + CPU frequency shift setting needs to be in M68000_CheckCpu*() that + it's applied on TOS switch too + + - this way there isn't different results when using --machine st + --tos tos4 + - as also other things than CPU Level are set, renamed function to + Settings + - reordered lines in tos.c so that it's clearer which are affected by + call to M68000_CheckCpuSettings() + [c7bcd788727c] + + * python-ui/hatariui, python-ui/hatariui.1: + fastforward -> forward + [978e5914d7c5] + + * python-ui/hatariui.py: + simplify tooltips more + [0675efd19ddf] + + * python-ui/hatariui: + fix hatariui examples + [3605e1842e28] + + * python-ui/README, python-ui/dialogs.py, python-ui/hatariui.py, + python-ui/release-notes.txt: + switch to new Gtk v2.12 tooltips API (as older one is deprecated) + [578551bd102b] + +2011-01-30 Laurent Sallafranque + + * src/falcon/videl.c: + some comments added in videl.c (just not to forget them) + [13bfdc16b95b] + + * src/dmaSnd.c: + fix from David : apply volume and tone filters also when there's + only Yamaha sound. + [de80b70874d9] + +2011-01-30 Eero Tamminen + + * src/falcon/hostscreen.c: + fix: crash & updates stopping when switching from same size VDI to + TT hostscreen rez + + - the redundant hostscreen.c SDL surface variable aliases weren't + in sync with sdlscrn, so removed them and used sdlscrn everywhere + - doUpdate flag needs to be updated even if resolution is same (the + surface could have been created by screen.c for VDI rez) + - remove redundant HostScreen_update5() for partial screen updates + [c0d6a3ecdf31] + +2011-01-29 Nicolas Pomarede + + * src/sound.c: + Remove global variable and reorder code accordingly + [12457bf85ec2] + +2011-01-29 Laurent Sallafranque + + * src/falcon/crossbar.c: + Little change in comments + [b01e8707a1c7] + +2011-01-28 Laurent Sallafranque + + * src/falcon/crossbar.c: + fix DMA_Play -> DSP_Record in handshake mode synchronization. MP2 + musics are now playing correctly, music is synchro, sound is clean. + This fix at least 5 demos (revert, Amanita, Dont break the oath, + beam, MP2 player and probably some more. + [0fac8290581a] + +2011-01-28 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [0908146515e9] + + * src/options.c: + enable DSP for --machine falcon option + + (One can still disable it using "--dsp none" after that option) + [cd9474f4cbf8] + + * src/change.c: + add optional debug prints to config change code + [1baee7eb9b6f] + +2011-01-26 Eero Tamminen + + * doc/compatibility.html: + cebit93 works fine with v1.4 release when using --cpuclock 32 + [c860aa763033] + + * src/memorySnapShot.c: + memory snapshots: increase version for Crossbar addition + minor + improvements: + - ask user before overwriting an existing memory snapshot + - slightly improved error message on snapshot version mismatches + - use sizeof() instead of define for version string + [cc19392df219] + + * src/debug/breakcond.c: + breakpoints: remove redundant error + clarify output on memory + snapshot re/store + [9688717c8a59] + +2011-01-26 Laurent Sallafranque + + * src/memorySnapShot.c: + fix: crossbar was not saved/restored in memory snapshot + [d475461f19b2] + + * src/falcon/crossbar.c: + add: special undocumented transfer between DMA play and DSP Record + in handshake mode added. In this special mode, datas are shifted 2 + bits on the left after the transfer. Now, demos using the Mpeg2 + player from nocrew (amanita, ...)) are playing the good datas. + There's still a big problem : for now, the music plays really too + fast (it should plays for 3 minutes, but it plays for 20 secondes + for now). + [13e8c031bbc3] + +2011-01-25 Laurent Sallafranque + + * src/debug/debugInfo.c: + fixed HandShack mode detection for DAC + added sound frequency for + STE compatible mode, 25 Mhz mode and 32 Mhz mode. + [b593829bee85] + + * src/falcon/dsp.c: + DSP must run at exactly 2 times CPU speed. I upload this patch as a + basis to improve DSP <-> CPU synchro + [a27531db9db0] + +2011-01-24 Nicolas Pomarede + + * src/sound.c: + Fix new tone step introduced in rev 2934, it was wrong for Per=0 + When tone per=0, the produced square wave should be a constant '1', + not '0'. Some recent replays are setting per=0 when playing samples + or when doing sid effect (it gives better results), a constant + output of '0' gave no audible sound (fix Blubber Sound Demo by + Paradox) + [c68bb85c3c63] + + * src/sound.c: + Typo in comment + [52a04b03aefe] + + * src/sound.c: + Disable debug printf + [20f4e72b26c2] + + * src/dmaSnd.c, src/falcon/crossbar.c, src/includes/sound.h, + src/psg.c, src/sound.c: + Take care of rounding errors when computing SamplesPerFrame, much + higher precision now Depending on the output sound freq and the + emulated video freq (VBL rate), the number of samples to generate + for each VBL will not always be an integer. This new code simulates + a floating point number of samples per VBL and adjusts the number of + generated samples per VBL to obtain an exact number of samples per + second, precisely matching the chosen output sound frequency. + [d7b19dc20219] + +2011-01-23 Nicolas Pomarede + + * src/sound.c: + Don't use SamplePerVbl save an avi audio frame, it can gives + rounding error Instead, we use the difference between the 2 indexes, + which allows to have audio frames of different sizes when handling + rounding errors. + [833c96a8fa82] + +2011-01-20 Eero Tamminen + + * src/ikbd.c: + fix: remove AUTOSEND interrupt only after UI events have been + processed + [484ae01c9e29] + +2011-01-19 Laurent Sallafranque + + * src/falcon/crossbar.c: + fix: ADC memset was wrong + [d914bd472a7d] + + * src/change.c: + fix: changing to prefetch mode (with the new core) needs to reset + the computer + [8ca496ebcd5b] + + * src/cpu/newcpu.c: + added DSP in prefetch mode. Both "simple" and prefetch emulation are + now working + [982801288ef4] + +2011-01-17 Laurent Sallafranque + + * src/cpu/newcpu.c: + DSP added to newcpu + [79a95c89e722] + +2011-01-16 Eero Tamminen + + * src/tos.c: + on switch to TOS4, DSP needs to be initialized too + [d264f083bc0a] + + * src/falcon/dsp.c, src/falcon/dsp_core.c, src/falcon/dsp_core.h, + src/falcon/dsp_cpu.c, src/falcon/dsp_cpu.h, src/falcon/dsp_disasm.c, + src/falcon/dsp_disasm.h: + converted dsp_core to a directly accessible struct instead of + pointer on Laurent's request + [216fa5b71acb] + + * src/dialog.c, src/memorySnapShot.c, src/statusbar.c: + update statusbar info also when memory snapshot loaded with + --memstate + [319fb2bbf5e4] + +2011-01-15 Eero Tamminen + + * src/falcon/videl.c: + do Videl resolution change immediately, not 3 VBLs late (and don't + skip drawing frames during those 3 VBLs either) + [997e6d747e3a] + + * readme.txt, src/configuration.c, src/falcon/hostscreen.c, src/gui- + sdl/dlgScreen.c, src/includes/resolution.h, src/main.c, + src/resolution.c: + User's desktop size as max limit for Videl resolution: + - add Resolution_Init() & Resolution_GetDesktopSize() functions to + get and query desktop size + - call the Resolution_Init from appropriate place in main.c + - set the Videl max zoom limit from desktop size there, if it's not + yet set + - change SDL GUI to use that also as max zoom limit + - change hostscreen.c to limit max SDL resolution to desktop size + - videl.c should then be clipping the output to that... + - resolution limit may prevent crashes with buggy video drivers + - fix resolution.c debug prints This requires at least SDL v1.2.10. + [43bae6606a2e] + + * src/falcon/dsp_disasm.c: + const non-modified DSP disasm arrays too + [d303f1028b57] + + * src/tos.c: + TOS4 should enable DSP emulation + [d3f9975a8932] + + * src/options.c: + fix WinAUE option error option ID + [583c68ba1511] + +2011-01-14 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + fix: SR U bit was still wrong (the test occurs on bits 23-24 not + 12-13) + [fa0d0b619185] + + * src/falcon/dsp_cpu.c: + fix: After 6 instructions, interrupts are allowed again, and we must + test immediatly if there's a pending interrupt to process. + [e0701509f4ee] + + * src/falcon/dsp_cpu.c: + fix: SR U bit was inverted + [2c9f3708b3e5] + +2011-01-12 Eero Tamminen + + * src/change.c, src/dialog.c: + enabling DSP needs reboot. Verify reboot from user unless only + fatal alerts shown + [9502c8049edf] + + * src/falcon/dsp_cpu.h: + really add BITMASK to header + [7070c1f6068f] + + * src/falcon/dsp.c, src/falcon/dsp_cpu.c, src/falcon/dsp_disasm.c: + move identical BITMASK macros from dsp*.c files to commonly used + dsp_cpu.h + [040e305d4d3b] + + * src/falcon/dsp_cpu.c: + DSP CPU arrays values aren't modified so they can be const + [5eeb1ba00bff] + + * doc/compatibility.html: + super hang-on issue still in v1.4 + [187fa7010c44] + + * doc/emutos.txt: + more info on EmuTOS issue with RG Falcon games + [95b1f88c525a] + + * src/falcon/dsp.c: + fix: allow DSP to be disabled + [ec71583f8331] + +2011-01-11 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + fix: DSP external memory timings were wrong. DSP external memory is + 0 waitstate, not 1. This fix at least the music in "illusion" demo. + [1ea504dede73] + +2011-01-04 Nicolas Pomarede + + * src/CMakeLists.txt: + When building a Windows .exe, set the subsystem to "windows GUI" + instead of "console" + [365c5443c708] + +2011-01-04 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + update_e_u_n_z function optimization. + [4e2e6759fa21] + +2011-01-04 Eero Tamminen + + * src/falcon/dsp.c: + simplify DSP main loop (use one variable less) + [b348e15c5724] + +2010-12-31 Eero Tamminen + + * src/cpu/build68k.c, src/cpu/cpu_prefetch.h, src/cpu/cpummu.c, + src/cpu/cpummu.h, src/cpu/custom.h, src/cpu/events.h, + src/cpu/events_jit.h, src/cpu/events_normal.h, src/cpu/fpp-ieee- + be.h, src/cpu/fpp-unknown.h, src/cpu/fpp.c, src/cpu/gencpu.c, + src/cpu/jit/codegen_x86.c, src/cpu/jit/codegen_x86.h, + src/cpu/jit/compemu.h, src/cpu/jit/compemu_codegen.h, + src/cpu/jit/compemu_fpp.c, src/cpu/jit/compemu_optimizer_x86.c, + src/cpu/jit/compemu_raw_x86.c, src/cpu/jit/compemu_support.c, + src/cpu/jit/compemu_support_codegen.c, src/cpu/jit/comptbl.h, + src/cpu/jit/gencomp.c, src/cpu/m68k.h, src/cpu/maccess.h, + src/cpu/memory.c, src/cpu/memory.h, src/cpu/newcpu.h, + src/cpu/readcpu.c, src/cpu/readcpu.h, src/cpu/savestate.h, + src/cpu/sysdeps.h, src/cpu/table68k: + fix winuae cpu/ dir files access rights (644, same as for uae-cpu/ + files) + [fab687e10ec7] + + * doc/emutos.txt: + typo in prev commit + [5aed5f9bded3] + + * doc/emutos.txt: + more things working with EmuTOS, more info on RG Falcon games EmuTOS + freeze + [8aa40c7ba412] + + * doc/compatibility.html: + vircity needs >4MB + [80803111d796] + + * doc/hatari.1, doc/manual.html: + add note about autostarting failing if there's floppy disk with .inf + file + [16108604a28a] + +2010-12-28 Thomas Huth + + * CMakeLists.txt: + Hatari only needs a C compiler, there is no need for testing for + C++, too + [5c48ae424012] + +2010-12-28 Eero Tamminen + + * python-ui/uihelpers.py: + make class declaration python 2.4 compatible (fix from David + Savinkoff) + [0312d68fa824] + + * src/ikbd.c, src/includes/ikbd.h: + stuff used only in ikbd.c can/should be static + [554f69ffb668] + + * src/rs232.c: + rs232: saner thread delays, move if inside RS232_OpenCOMPort(), + better comments + [ef3346b2c059] + +2010-12-24 Thomas Huth + + * src/ikbd.c: + Print error message when IKBD buffer is full + [9c055064c9ef] + + * src/ikbd.c: + Fixed the JOYSTICK INTERROGATE IKBD command for the game "Downfall". + This game continually issues this IKBD command during the title + screen, faster than processing the 3 bytes from the ACIA, so it + floods our Keyboard.Buffer ... in the end, we were not able not put + the whole packet into the buffer anymore, and the game hang due to + these incomplete answers. To avoid this situation, only execute this + command if there is enough space left in our Keyboard.Buffer! + [a6aa1cc75949] + +2010-12-22 Eero Tamminen + + * doc/authors.txt, doc/emutos.txt, doc/release-notes.txt: + update release notes and other docs + [ac3f150400e1] + +2010-12-22 Laurent Sallafranque + + * src/falcon/dsp_disasm.c: + fix+little optim : fixed some wrong opcode texts + little optim in + registers changes tracing + [2f855c8ed625] + +2010-12-20 Eero Tamminen + + * src/avi_record.c, src/includes/main.h, src/main.c, src/screen.c: + show AVI recording time in the titlebar + [471fa4eb4bd5] + +2010-12-18 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + Rewrite of all parallel decoding part (hardcoding of each 256 + instructions) + full rewrite and simplification of parallel move + decoder. + [f783a9abe4e1] + + * src/falcon/dsp_disasm.c: + major optim: removed all 256 parallel instructions decoding and + hardcoded all of them in a table. + [f97c8da3372f] + +2010-12-13 Thomas Huth + + * src/CMakeLists.txt: + Fixed link_directories for newer versions of CMake + [454bfe8bb953] + +2010-12-13 Nicolas Pomarede + + * src/video.c: + More generic way to handle the last 16 pixels of the line for STE's + horizontal scrolling (works for any line's length) Previously, when + using STE's 224 bytes overscan and hscroll, the last 16 pixels were + not correctly displayed (fix More Or Less Zero and Cernit Trandafir + by DHS, Save The Earth by Defence Force) + [463a4198b55f] + +2010-12-12 Laurent Sallafranque + + * src/falcon/dsp_disasm.c: + fix : 2 bugs fixed in dsp_lua and dsp_tcc disasm code + [feff3d5cda04] + +2010-12-05 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Update release note and compatibility list + [927e055352fe] + +2010-12-04 Nicolas Pomarede + + * src/video.c: + In med res overscan, correctly shift the screen 4 pixels to the left + This was not correctly handled in rev 2334 and worked only for low + res (fix regression in 'Best Part Of The World' by Delta Force and + 'No Cooper Greetings screen' by 1984) + [39e80ad361c0] + + * src/convert/low320x16_spec.c, src/convert/low320x32_spec.c, + src/convert/low640x16_spec.c, src/convert/low640x32_spec.c, + src/convert/spec320x16.c, src/convert/spec320x32.c, + src/convert/spec640x16.c, src/convert/spec640x32.c, src/screen.c: + Rename conversion files for low res spec512 to explicitly contain + 'low' + [ee9561787699] + +2010-12-03 Nicolas Pomarede + + * src/convert/med640x16_spec.c, src/convert/med640x32_spec.c, + src/convert/routines.h, src/convert/spec320x16.c, + src/convert/spec320x32.c, src/convert/spec640x16.c, + src/convert/spec640x32.c, src/screen.c: + Explicitly add LowRes into functions' names since spec512 mode is + now available in low res and med res + [c986a85c6009] + + * src/convert/macros.h, src/convert/med640x16_spec.c, + src/convert/routines.h, src/screen.c: + Add support for spec512 mode in med res for 16 bit screen + [0211d900e8ac] + +2010-12-01 Nicolas Pomarede + + * src/convert/routines.h, src/convert/spec640x16.c: + Split ConvertSpec512_640x16Bit() in 2 parts to allow low/med lines + mixing in spec512 mode + [4869ec3eacf0] + + * src/convert/med640x32_spec.c: + In spec512 mode, don't call AdjustLinePaletteRemap() to test for + low/med res on each line. Doing so would override the colors changed + by Spec512_UpdatePaletteSpan and give wrong/flickering palette. + [701bd4b0ad0c] + + * src/spec512.c: + Add debug printf + [383e4b60dd2b] + +2010-11-28 Nicolas Pomarede + + * src/convert/med640x32_spec.c, src/convert/routines.h, + src/convert/spec640x32.c: + Split ConvertSpec512_640x32Bit() in 2 parts to allow low/med lines + mixing in spec512 mode + [3dc2c6f9e8c3] + + * src/convert/macros.h, src/convert/med640x32_spec.c, + src/convert/routines.h, src/screen.c, src/spec512.c: + Add support for spec512 mode in med res for 32 bit screen (fixes + 'Best Part Of The Creation' by Delta Force in 'Punish Your Machine' + and 'HighResMode' demo for STE by Paradox) + [b27039df718b] + + * src/convert/med640x32.c: + Reorder functions (main loop first) + [98eb75095d86] + + * src/convert/macros.h: + PLOT_SPEC512_MID_320_16BIT should be PLOT_LOW_640_16BIT not + PLOT_MED_640_16BIT (harmless because both macros do the same) + [62265417b077] + + * src/convert/spec320x16.c, src/convert/spec320x32.c, + src/convert/spec640x16.c, src/convert/spec640x32.c: + Correct comment about plotting order in spec512 mode + [8ad268e6c9b3] + + * src/convert/high640x8.c, src/convert/low320x16.c, + src/convert/low320x32.c, src/convert/low320x8.c, + src/convert/low640x16.c, src/convert/low640x32.c, + src/convert/low640x8.c, src/convert/med640x16.c, + src/convert/med640x32.c, src/convert/med640x8.c, + src/convert/spec320x16.c, src/convert/spec320x32.c, + src/convert/spec640x16.c, src/convert/spec640x32.c, + src/convert/vdi16.c, src/convert/vdi2.c, src/convert/vdi4.c: + Correct wrong/misleading comments about pixels' order in + SDL_BIG_ENDIAN mode + [8548dc8868c3] + + * src/convert/spec320x16.c, src/convert/spec320x32.c, + src/convert/spec640x16.c, src/convert/spec640x32.c: + Use the same order/logic as in other convert routines (compare with + SDL_BIG_ENDIAN first) + [f19602329319] + +2010-11-26 Nicolas Pomarede + + * src/convert/macros.h: + PLOT_SPEC512_MID_320_32BIT should be PLOT_LOW_320_32BIT not + PLOT_MED_640_32BIT (harmless because both macros do the same) + [c18de3976685] + +2010-12-01 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + last fix: external memories extra cycles returned back to 1. + [d4006369e18f] + + * src/falcon/dsp_cpu.c: + fix again: x: or y: memory are always in internal RAM (immediate + value is between 0 and $3f). So cycles = 4. + [7379a7cec69d] + +2010-11-30 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + fix: correct wrong cycles computing for BCLR_aa, BCHG_aa, BSET_aa. + According to the doc, cycles = 4 + ea + 2*X_YWaitState (Ea = 0) + [f5ed4f860c10] + +2010-11-24 Eero Tamminen + + * doc/hatari.1, doc/manual.html, src/configuration.c, src/gui- + sdl/dlgScreen.c, src/includes/configuration.h, src/main.c, + src/options.c, src/screenSnapShot.c, src/shortcut.c: + Add GUI crop option, apply it both to screenshots & AVI recording + + This adds Screen.bCrop / --crop option, removes the --avi-crop + option and removes also previously redundant Screen.bCaptureChange + config option. + [295f069d3644] + +2010-11-23 Laurent Sallafranque + + * src/cpu/compat.h, src/cpu/hatari-glue.c, src/cpu/options_cpu.h, + src/m68000.c: + fix: configuration allows to choose all cpus. Falcon 68030 is + running (at least to the desktop) + [f64cbf057a16] + + * src/options.c: + added bLoadAutoSave = false to the 6 new optional parameters added + for the new WinUae CPU + [0185e4ef3c24] + + * src/gui-sdl/dlgMain.c, src/gui-sdl/dlgSystem.c: + fixed wrong upload last time (I swapped 2 files) + [7d82ad1d1ee8] + +2010-11-22 Laurent Sallafranque + + * src/change.c: + fix: forgot to add the ENABLE_WINUAE_CPU compilation test (the 2 + tests are only for new WinUae CPU) + [b95015554020] + + * src/change.c, src/configuration.c, src/cpu/hatari-glue.c, src/gui- + sdl/dlgMain.c, src/includes/configuration.h, src/m68000.c, + src/options.c: + add: new system panel for WinUae cpu, new hatari options, changed + preference's saving and memory snapshot saving and restoring + [3590c879ba21] + +2010-11-21 Nicolas Pomarede + + * src/debug/68kDisass.c: + Use doptNoBrackets by default to remove "()" around absolute + addresses in the new disassembler + [a20648f2ce4e] + +2010-11-21 Eero Tamminen + + * src/avi_record.c: + fix avi recording compiler warning + simplify its error handling + [6b3cc63fa29f] + + * src/tos.c: + comments to 80 cols, fix Uwe's compiler warning, remove ifdeffed + debug code + [62f215d63e7e] + + * src/debug/profile.c: + fix compiler printf %d / sizeof() mismatch warnings for 64-bit OSes + [bf3986953b56] + + * doc/hatari.1, python-ui/hatariui.1, tools/CMakeLists.txt, tools + /atari-hd-image.1, tools/hconsole/hconsole.1, tools/hmsa/hmsa.1, + tools/zip2st.1: + remove script extension on install, add manual pages for all + installed tools + + This was requested by Hatari Fedora maintainer, new manual pages + could be mostly taken from Debian. Mentioned other tools in "SEE + ALSO" sections. + [81326134540c] + + * src/debug/68kDisass.c: + fix compiler warnings and improved[1] previous fixes + + [1] global function protos belong to headers whereas local functions + should be static & things should be of correct type instead of + casted. + [64704aa3bf80] + +2010-11-20 Nicolas Pomarede + + * src/debug/68kDisass.c, src/debug/68kDisass.h, src/debug/breakcond.c, + src/debug/debugcpu.c, src/uae-cpu/newcpu.c: + Add new wrapper function Disasm() to choose between UAE or new + disassembler + - create 68kDisass.h, reorder includes for consistency + - replace calls to m68k_disasm() by Disasm() (except in + m68k_dumpstate() ) + [a0c9f2c7bb17] + +2010-11-19 Nicolas Pomarede + + * src/debug/68kDisass.c: + Remove more warnings : suggest parenthesis at line 72 + set same + 'const' qualifier for target and dest when assigning 'sp' + [030b6ed2cb51] + + * src/debug/68kDisass.c: + Cast variables to remove warning about signed/unsigned comparisons + [369a112a5b43] + +2010-11-18 Nicolas Pomarede + + * src/debug/68kDisass.c: + Add missing prototypes to prevent warnings from gcc + [ed6908775368] + + * src/debug/68kDisass.c: + Remove variables' declaration in 'for' loop : this is C99 only + syntax and doesn't compile with our flags + [8350d9b5ee3d] + + * src/debug/68kDisass.c, src/debug/CMakeLists.txt: + Add new 68k disassembler by Markus Fritze + [65462ed13440] + +2010-11-19 Laurent Sallafranque + + * src/cpu/memory.c, src/cpu/memory.h: + added infos to bank memories to let hatari run in compatible = 1 + mode. This will have to be reworked a little to take care of lgeti + and wgeti. + [d639f4ca2320] + + * src/cpu/newcpu.c: + fix: quit hatari is now available + [dee4f47e7052] + +2010-11-18 Laurent Sallafranque + + * src/cpu/cpu_prefetch.h: + add newline at end of file + [772303b02250] + +2010-11-18 Thomas Huth + + * src/cpu/newcpu.c: + Disable some Amiga-specific code in exception function and make sure + that MFP interrupts are handled. + [ab01e980a47a] + + * src/cpu/custom.c, src/cpu/custom.h, src/cpu/newcpu.c, + src/cpu/newcpu.h: + Fixed compiler warnings + [be977402a9d6] + +2010-11-14 Nicolas Pomarede + + * src/avi_record.c, src/configuration.c, src/gui-sdl/dlgScreen.c, + src/includes/configuration.h, src/main.c, src/options.c, + src/shortcut.c: + Store AVI recording parameters into hatari.cfg under [Video] section + [79c34f4689cb] + +2010-11-13 Matthias Arndt + + * src/includes/joy.h, src/joy.c: + initial patch to allow variable SDL joystick axis IDs instead of + hardcoded axis values + [9e2869935d52] + +2010-11-12 Laurent Sallafranque + + * src/cpu/fpp.c, src/cpu/gencpu.c, src/cpu/newcpu.c, src/cpu/newcpu.h, + src/m68000.c: + reintroduced interrupts and MFP to newcpu + [0afc21af98cb] + +2010-11-11 Eero Tamminen + + * CMakeLists.txt: + correct name: -DFORTIFY_SOURCE -> -D_FORTIFY_SOURCE + + (enables extra Glibc function checks) + [eefec2ba436b] + +2010-11-08 Thomas Huth + + * src/cpu/compat.h: + Replaced bad '#define bool' by stdbool.h - that should hopefully fix + the address_space_24 problem in the currprefs structure. + [8c6b545d99de] + +2010-11-08 Laurent Sallafranque + + * src/cpu/custom.c, src/cpu/custom.h, src/cpu/newcpu.c: + reintegrated trace CPU disasm + [ffb54014718c] + +2010-11-07 Nicolas Pomarede + + * doc/compatibility.html: + Update some non fully working demos on STF/STE + [2c0c314e10cf] + + * src/m68000.c: + Add pairing for LSL/JMP (and all variants) (Fullparts demo by + Hemoroids) + [07ede30deb3e] + +2010-11-07 Laurent Sallafranque + + * src/cpu/compat.h, src/cpu/newcpu.c: + reintroduced do_specialties code from old uae core and CPU_TRACE + [44efc8180b6c] + +2010-11-06 Thomas Huth + + * src/cpu/newcpu.c: + Supervisor mode must be switched on before accessing low memory + [bb21af6a6bd2] + + * src/cpu/CMakeLists.txt: + Simplified build rules + [c86dec2ced94] + +2010-11-06 Laurent Sallafranque + + * src/cpu/custom.c, src/cpu/events.h, src/cpu/gencpu.c, + src/cpu/newcpu.c, src/cpu/newcpu.h: + everything compiles and links. + [6c79f7df4c85] + + * src/cpu/CMakeLists.txt, src/cpu/gencpu.c: + major fix : nearly everything is fixed now (thanks Thomas) + [28b2c10b3ac8] + + * src/cpu/compat.h, src/cpu/custom.c, src/cpu/custom.h, + src/cpu/memory.c, src/cpu/newcpu.c, src/cpu/sysconfig.h: + fixed some more warnings and linking problems + [7677b5764ae8] + + * src/cpu/cpummu.c, src/cpu/custom.c, src/cpu/fpp.c, src/cpu/newcpu.h: + some more fixes (warnings + linking problems) + [052812f53ef7] + +2010-11-06 Eero Tamminen + + * src/debug/debugui.c: + debugger: fix chdir compile warning, don't mess input line when + parsing it. + + (Last one is needed because of the earlier change which saves the + previous line to history only when next line is input.) + [5ec17068c226] + +2010-11-05 Eero Tamminen + + * src/includes/main.h, src/main.c, src/options.c: + allow use of --run-vbls also after bootup + + (i.e. zero also VBL count when VBL limit is set) + [6d76ec449aaa] + +2010-11-05 Laurent Sallafranque + + * src/cpu/build68k.c, src/cpu/cpummu.c, src/cpu/custom.c, + src/cpu/events.h, src/cpu/gencpu.c, src/cpu/hatari-glue.c, + src/cpu/readcpu.c: + Winuae core : some more compiling warning and linking errors fixed + [a5b8ed064879] + + * src/cpu/custom.c, src/cpu/newcpu.c, src/cpu/newcpu.h: + 2 more linking problems fixed + [118dccc92d31] + + * src/cpu/CMakeLists.txt, src/cpu/compat.h, src/cpu/custom.c, + src/cpu/custom.h, src/cpu/events.h, src/cpu/hatari-glue.h, + src/cpu/memory.c, src/cpu/memory.h, src/cpu/newcpu.c, + src/cpu/options_cpu.h, src/cpu/sysconfig.h, src/m68000.c: + Many fixes to let WinUae core link. Still some work to do. + [b3e885ebd08d] + +2010-11-05 Eero Tamminen + + * CMakeLists.txt: + comment -Wextra stuff out, -Wno-empty-body isn't supported on GCC + v<4.3 + [7e02e97c6c22] + +2010-11-04 Thomas Huth + + * tools/hmsa/CMakeLists.txt: + Fixed zlib include path for hmsa tool + [77c28685083e] + +2010-11-02 Eero Tamminen + + * tests/Makefile, tests/debugui/console.ini, + tests/debugui/debugger.ini, tests/debugui/dsp-test.sym, + tests/debugui/etos512.sym, tests/os-header.sym, tests/test- + breakcond.c, tests/test-dummies.c, tests/test-evaluate.c, tests + /test-scripting.sh, tests/test-symbols.c: + remove the moved files + + (seems that both destination & source files need to be commited + separately) + [9f6d5d8814e5] + + * tests/debugger/Makefile, tests/debugger/data/console.ini, + tests/debugger/data/debugger.ini, tests/debugger/data/dsp-test.sym, + tests/debugger/data/etos512.sym, tests/debugger/data/os-header.sym, + tests/debugger/test-breakcond.c, tests/debugger/test-dummies.c, + tests/debugger/test-evaluate.c, tests/debugger/test-scripting.sh, + tests/debugger/test-symbols.c: + Move all debugger tests to a tests/debugger subdirectory + [99889a63402e] + + * tools/hconsole/hconsole.py: + tab-complete also hconsole internal commands + [d00ed8c1751d] + + * tests/debugui/console.ini, tests/test-scripting.sh: + update scripting tests for hconsole changes + [50130e1f7bf0] + + * tests/Makefile: + add test target and comments on how to run tests to tests/Makefile + [c01b09f8620c] + + * tests/test-dummies.c, tests/test-evaluate.c: + update test code for debugger changes + [352055a6482b] + + * src/debug/debugui.c, src/debug/evaluate.c: + update debugger evaluate command help (parenthesis = RAM fetch) + [2aaf4d591fd6] + +2010-11-02 Laurent Sallafranque + + * src/cpu/savestate.h: + savestate compiles now. Everything compiles but doesn't link yet + [f0bc85ccc2cd] + + * src/m68000.c: + fixed compilation warning in WINUAE mode + [584eca106c24] + + * cmake/config-cmake.h, src/m68000.c: + m68000.c now compiles + [b2028acb9bee] + + * src/cpu/fpp.c, src/cpu/md-fpp.h, src/cpu/sysconfig.h: + fpp.c compiles + [7e34c70797d2] + +2010-11-01 Laurent Sallafranque + + * src/cpu/compat.h, src/cpu/cpummu.c, src/cpu/memory.h, + src/cpu/newcpu.c, src/cpu/newcpu.h, src/cpu/options_cpu.h, + src/cpu/sysconfig.h: + newcpu.c is now compiling + [29f756017ae4] + +2010-11-01 Nicolas Pomarede + + * doc/release-notes.txt: + Update changes for YM sound and STE's 224 bytes overscan + [7a3454f1504b] + + * src/video.c: + On STE, correctly align pixels 8 pixels to the left when doing a 224 + bytes overscan. The hi/lo switch at position 504/4 will make the + display starts 8 pixels earlier. For 230 bytes overscan on STE, the + next value for pVideoRaster depends on whether scrolling's + prefetching is used or not. (fix various pixels alignment when + compared with a real STE) + [c41f86ceacf4] + +2010-10-22 Laurent Sallafranque + + * src/cpu/events.h: + returned to original STATIC_INLINE + [5b8cee333670] + + * src/includes/m68000.h: + Comment fixed + [0718b543b46a] + + * src/cpu/custom.h: + This file contains nothing needed by WinUae Cpu. We keep it empty + here to reduce changes in WinUae cpu code + [1f4386c8ca97] + +2010-10-22 Eero Tamminen + + * src/debug/breakcond.c: + show breakpoint variable values in help as hex instead of decimal + + Tracing breakpoints already show memory & variable values as hex so + this was inconsistent. + [6b025442121d] + + * src/debug/debugui.c: + prevent duplicate readline history entries, make input buffer + free()s closer to their malloc()s + + Former is a fix (needed to use previous_history(), not + current_history()). + + Latter change implies also that command that exits debugger isn't + stored into command history and that non-readline/history command + editing needs to do less allocs. + [0dcb55af21ef] + +2010-10-21 Laurent Sallafranque + + * src/cpu/CMakeLists.txt, src/cpu/build68k.c, src/cpu/compat.h, + src/cpu/cpummu.c, src/cpu/cpummu.h, src/cpu/custom.h, + src/cpu/events.h, src/cpu/gencpu.c, src/cpu/maccess.h, + src/cpu/memory.c, src/cpu/memory.h, src/cpu/newcpu.c, + src/cpu/newcpu.h, src/cpu/options_cpu.h, src/cpu/readcpu.c, + src/cpu/readcpu.h, src/cpu/rpt.h, src/cpu/sysconfig.h, + src/cpu/sysdeps.h, src/includes/m68000.h: + Temporary save : this version compiles until newcpu.c + [6eeb9583fed9] + +2010-10-21 Eero Tamminen + + * doc/manual.html: + manual/debugger: update for indirect addressing + re- + org/improvements + [8bf49591ca4f] + + * src/debug/evaluate.c: + support indirect addressing in evaluate debugger command + [abb759b5c038] + +2010-10-20 Eero Tamminen + + * src/debug/breakcond.c: + breakpoints: bios & xbios trap number were swapped, fix + [7661f5c8e5ec] + +2010-10-16 Eero Tamminen + + * doc/manual.html: + add debugger profile command documentation to the manual + [7efba68d58a5] + + * doc/manual.html: + update manual for tracing, breakpoint and info/lock command + improvements, fix typos + [f2abeb494acd] + + * doc/hatari.1: + mention in man page what docs /usr/share/doc/ contains + [39185c4b79d6] + + * doc/release-notes.txt: + update release notes + [1d7521e91b74] + + * src/debug/debugui.c: + remove the ifdeffed out debugger "exec" command support + + This was already ifdeffed out in previous release, didn't have a + CMake config option to enable it and is AFAIK unused. hconsole can + be used to achieve something similar from outside the Hatari and + more specific commands can be added to debugger if really needed. + [839c6abc24c4] + + * src/debug/debugInfo.c: + add "lock file" command, tune lock/info help texts + + The given file will them be parsed by debugger and commands in it + executed whenever the locked commands are normally done (i.e. + entering debugger or hitting ":info" breakpoint). + [e60f8be20cd7] + + * src/debug/debugui.c, src/debug/debugui.h: + export DebugUI_ParseFile(), chdir() back to previous dir after + parsing + + chdir() to file's dir before parsing is needed so that relative file + references in that file work. chdir() back to previous dir are + needed so that other things depending on (other) file paths work. + [9b0d4320f9e3] + + * src/ide.c, src/includes/m68000.h, src/ioMem.c, src/m68000.c, src + /uae-cpu/memory.c: + Use correct defines for bus error, show the error type, more + sensible bool arg name + + - Half of M68000_BusError callers were using defines on the calls, + half just magic numbers. Changed magic numbers to defines. + - bReadWrite doesn't make sense as bool arg. Bool's name is supposed + to indicated what "true" value stands for! + - Showing of the BusError read/write type is one-liner improvement + from Markus. + [8a62f551ad7b] + + * src/vdi.c: + fix AES/VDI info command output spacing + [9973b37a4329] + +2010-10-15 Eero Tamminen + + * src/gemdos.c: + remove pattern matching debug output from GEMDOS tracing + [5d77dde29cc5] + + * src/debug/debugInfo.c: + add "aes", "gemdos" and "vdi" subcommands to debugger info command + [6846fd7615b2] + + * src/gemdos.c, src/includes/gemdos.h: + add GEMDOS info & opcode function + + (and remove non-existing functions from gemdos.h) + [b6d0d9175b0f] + +2010-10-14 Eero Tamminen + + * src/configuration.c, src/debug/log.c, src/debug/log.h, + src/includes/vdi.h, src/tos.c, src/uae-cpu/newcpu.c, src/vdi.c: + add AES tracing and AES & VDI info+opcode functions + + This required: + - 32 -> 64-bit trace flag change and adding aes to trace flags in + log.c/h + - adding flag for Trap#2 AES/VDI interception for newcpu.c + -> this is enabled automatically when either aes or vdi tracing + is enabled (in log.c) or user selects extended VDI resolution + (in configuration.c) + - function for AES opcode/name mappings (vdi.c) + - functions for listing AES & VDI opcodes and listing the last + parameter block values (vdi.c) + - storing the parameter block values in the intercept function (vdi.c) + + The VDI_OpCode stuff is now called only when things are needed to be + done at VDI_Complete() in Trap exit i.e. for VDI workstation open. + [419c41200c8d] + + * src/debug/breakcond.c: + VDI breakpoints: -2 = 0xFFFE, not 0xFFFD + [1e0bbbc5f0c8] + +2010-10-13 Eero Tamminen + + * src/gemdos.c, src/tos.c: + minor improvements to TOS autostart feature + [9fbb5504ae25] + +2010-10-12 Thomas Huth + + * src/CMakeLists.txt: + Fixed include and library path problem when WinUAE CPU is enabled + [f0699d2dc876] + +2010-10-12 Eero Tamminen + + * tools/hconsole/example-commands, tools/hconsole/example.py: + hconsole examples output finetuning + [b925c317e86c] + + * src/debug/debugui.c: + fix comment handling in debugger input files + [95f3e17d9fbd] + + * tools/hconsole/release-notes.txt: + update hconsole notes + [dc3b30f1519f] + + * tools/hconsole/CMakeLists.txt, tools/hconsole/hconsole.1: + install hconsole under /usr/share + add new example + + example.py needs hconsole.py to be in same directory (or in Python + module path) to be able to import it. + + Hconsole also isn't that useful in itself, it's more of something on + top of which one can build things (or test Hatari remote API), so it + doesn't need to be installed to binary directory. The Hatari data + directory is enough. + [9e1672780bbb] + + * tools/hconsole/example-debugger, tools/hconsole/example.py: + example.py can/loads commands from the separate hconsole input file + + Therefore removed the duplication functionality from this. Added + also debugger input file example calling for this. + [9b65e79733d0] + + * tools/hconsole/example-commands: + add useful scancode numbers to hconsole example + other updates + [c942a1275270] + + * tools/hconsole/hconsole.py: + hconsole: add symbolic scancodes, script command and speed key + inserting + + Did also some small refactoring, command name changes and help text + modifications. + [fc63d979565d] + + * src/debug/breakcond.c: + ":info" flag for giving info specified with "lock" command also + while tracing breakpoints + + (previously they were shown only when breakpoint causes entering + into debugger) + [fe1528adace5] + +2010-10-11 Thomas Huth + + * CMakeLists.txt, configure, src/CMakeLists.txt: + Added CMake switch to enable WinUAE CPU core + [48ae28c0f7ac] + + * src/gui-osx/SDLMain.m: + Fixed compiliation problem on OS X. Thanks to Christer Solskogen for + the patch! + [2b05780e256c] + +2010-10-11 Eero Tamminen + + * python-ui/CMakeLists.txt, tools/CMakeLists.txt, + tools/hconsole/CMakeLists.txt: + add hconsole to build scripts + [67a40404e966] + + * python-ui/FILES, python-ui/README, python-ui/hatariui.1, python-ui + /release-notes.txt, tools/hconsole/hconsole.1, tools/hconsole + /release-notes.txt: + add hconsole documentation and update hatariui docs accordingly + [dce2fd55e0ca] + + * tools/hconsole/example-commands, tools/hconsole/example.py: + add hconsole scripting examples + [d25c1c76a2f8] + + * python-ui/hatari-console.py, tools/hconsole/hconsole.py: + rename hatari-console.py to hconsole.py and move it under tools + + - python scripts included by others cannot have dashes in names + - it's better to have it in its own file as I'm going to add quite a + bit of stuff to this. It might even be used for automatic some of + hatari testing... + [6e78faa70d74] + +2010-10-10 Eero Tamminen + + * src/gui-sdl/dlgAlert.c: + fix struct member initialization for Notice Alert + [42dc90087cae] + + * CMakeLists.txt: + remove -Wfloat-equal, we're not going to change FPU emulation code + to avoid float == 0 comparisons + [a2417b16afa8] + + * src/gemdos.c: + show the converted result in GEMDOS trace, not host one for GetDir + + (also, leave out the hatari's internal function name like elsewhere) + [bd360f8a6dc6] + + * python-ui/hatari-console.py: + re-fix hatari-console hatari arg handling, helper for hatari-console + importers + [e44b84900111] + +2010-10-09 Eero Tamminen + + * python-ui/hatari-console.py: + hatari-console: add verbose & text insert commands, fix Hatari + argument handling + [af0427325bf9] + + * python-ui/dialogs.py, python-ui/hatariui.py, python-ui/uihelpers.py: + fix/improve hatari UI button/key press simulation + + - update to event name change, use press instead of down&up where + appropriate + - special case space key on text insert, it needs scancode + - add button for Enter key simulation + [45ef37c6bd4b] + + * src/control.c: + improve remote API key & mouse button press/release handling + + - have separate "keypress" event that does both press & release + - rename button & key press & release to *down & *up + - update help and tell key code is actually ST key scancode... + [427f6432277d] + + * python-ui/hatariui.1, python-ui/hatariui.py: + update hatari UI docs for new hatari argument handling + [d2cde1d711f3] + + * doc/hatari.1, doc/manual.html, doc/release-notes.txt: + update --bios-intercept info in docs + [e56e0cd83dec] + + * src/options.c: + allow --bios-intercept to be toggled (from debugger), not just + enabled + [89a531b5f297] + + * src/bios.c: + Sensible Bios CON: output also when line is being edited under + emulation + [38e0f1adc231] + +2010-10-09 Laurent Sallafranque + + * src/cpu/CMakeLists.txt, src/cpu/build68k.c, src/cpu/cpu_prefetch.h, + src/cpu/cpummu.c, src/cpu/cpummu.h, src/cpu/custom.h, + src/cpu/events.h, src/cpu/events_jit.h, src/cpu/events_normal.h, + src/cpu/fpp-ieee-be.h, src/cpu/fpp-unknown.h, src/cpu/fpp.c, + src/cpu/gencpu.c, src/cpu/hatari-glue.c, src/cpu/hatari-glue.h, + src/cpu/jit/codegen_x86.c, src/cpu/jit/codegen_x86.h, + src/cpu/jit/compemu.h, src/cpu/jit/compemu_codegen.h, + src/cpu/jit/compemu_fpp.c, src/cpu/jit/compemu_optimizer_x86.c, + src/cpu/jit/compemu_raw_x86.c, src/cpu/jit/compemu_support.c, + src/cpu/jit/compemu_support_codegen.c, src/cpu/jit/comptbl.h, + src/cpu/jit/gencomp.c, src/cpu/m68k.h, src/cpu/maccess.h, + src/cpu/memory.c, src/cpu/memory.h, src/cpu/newcpu.c, + src/cpu/newcpu.h, src/cpu/readcpu.c, src/cpu/readcpu.h, + src/cpu/savestate.h, src/cpu/sysdeps.h, src/cpu/table68k: + add : first version of WinUae cpu for Hatari. WinUae source is + v2.3.0. I've just renamed .cpp to .c + [026e498bd040] + +2010-10-09 Eero Tamminen + + * doc/hatari.1, doc/manual.html, doc/release-notes.txt, tools/hatari- + tos-register.sh: + document autostarting, script to register Hatari as TOS program + runner + + Script uses Linux binfmt_misc feature. + [52a4548b896a] + + * src/gemdos.c, src/includes/str.h, src/includes/tos.h, src/options.c, + src/str.c, src/tos.c: + Add Atari program autostart support to Hatari + + - Move TOS filename conversion from gemdos.c to str.c and use it + from tos.c + - Hatari argument can be an atari program or a directory in addition + to a disk image + - In atari program case, create a temporary/virtual desktop.inf file + to which TOS is redirected when it first accesses desktop.inf + after boot (with separate files for emutos and normal tos) + [01dfa7471e21] + +2010-10-08 Eero Tamminen + + * src/file.c, src/gemdos.c, src/includes/file.h, src/paths.c: + remove duplicate directory existence check function + [93577018e105] + + * doc/emutos.txt: + Kruse's early demo works with EmuTOS except for some issues with + fonts + [4caa32b7e92e] + + * CMakeLists.txt: + add more GCC warning options + + Added -Wextra minus options that cause spurious warnings and some + security & float options recommended on Debian source code fortify + page. + [91a6d1226c77] + + * CMakeLists.txt: + apply GCC warning flags in order they're given + + (otherwise one gets confusing results when one sets a generic + warning option and then tries to disable parts of those warning.) + [106bbe51b8a8] + + * src/gemdos.c: + simplify GemDOS_OpCode() code, convert if's to assignments + + (object file .text size decreases 40 bytes) + [9b44adc2ac28] + + * src/gemdos.c: + move GemDOS_Opcode2Name() closer to function where it's called + [bf5470b86796] + +2010-10-07 Eero Tamminen + + * doc/hatari.1, doc/manual.html, doc/release-notes.txt, src/options.c: + update/improve --bios-intercept documentation + [bd4583ff1455] + + * src/bios.c: + --bios-intercept prints CON: output on host console + [45df55c03900] + +2010-10-06 Eero Tamminen + + * src/gemdos.c: + add missing address range validity checks, change their debug level + to warnings + [a5d05ca2bb86] + +2010-10-05 Thomas Huth + + * doc/authors.txt: + Added remark about Qemu + [4076e47cb17d] + +2010-09-26 Thomas Huth + + * doc/coding.txt: + Added coding guideline document. + [3e0a64efb750] + +2010-09-23 Eero Tamminen + + * src/gui-sdl/dlgNewDisk.c: + fix segfault on disk create/insert + + First creating new disk then canceling creating another new disk and + doing insert crashed to accessing freed memory. + [bd2a7ed713e2] + + * src/uae-cpu/CMakeLists.txt: + fix: check for GCC when adding GCC options + + and ignore only relevant "unused" warnings + [994a0949b1c2] + + * src/main.c: + fix: float comparisons shouldn't use equality checks + + (floats are inaccurate and those can fail due to rounding issues.) + [391a4bdb8118] + +2010-09-22 Laurent Sallafranque + + * src/gui-sdl/dlgFileSelect.c, src/gui-sdl/sdlgui.c, + src/includes/sdlgui.h: + scrollbar code cleaning + [6aa7ea1f3428] + +2010-09-18 Eero Tamminen + + * src/debug/breakcond.c: + fix -Wextra compiler warning, show help for dsp/address command with + no args + [c6451a06698c] + + * tools/hmsa/hmsa.c: + fix -Wformat-security compiler warning + [97f3e909547c] + +2010-09-14 Laurent Sallafranque + + * src/gui-sdl/dlgFileSelect.c, src/gui-sdl/sdlgui.c: + fix : mouse and scrollbar are completly synchronized in all + situations + [dae63f06a9cc] + + * src/gui-sdl/dlgFileSelect.c, src/gui-sdl/sdlgui.c, + src/includes/sdlgui.h: + Add : scrollbar can be moved with the mouse Removed : return to + previous scrollbar look and feel TODO: there's still a bug with the + mouse grabbing, if you use the mousewheel before grabbing the + scrollbar + [f0e07ee4d964] + +2010-09-10 Laurent Sallafranque + + * src/gui-sdl/dlgFileSelect.c, src/gui-sdl/sdlgui.c, + src/includes/sdlgui.h: + Reworked fileselector : add a 1 pixel precise scrollbar, applied GEM + look and feel + [54083f8c95cd] + +2010-09-08 Eero Tamminen + + * python-ui/dialogs.py, python-ui/uihelpers.py: + refactor HD & floppy file selection code to common class in + uihelpers + [d60b74fd9e73] + + * python-ui/dialogs.py: + fix floppy protection setting to use correct Hatari option + [4390c33dcfbf] + + * python-ui/uihelpers.py: + simplify uihelper win/nix path splitting + [db4bcf307d47] + +2010-09-04 Nicolas Pomarede + + * src/sound.c: + - Correct case where a noise per < 3 produced no noise output at all + - Rewrite tone and noise step compute to use the same logic as env's + step + [4b5f4b81ab6f] + +2010-08-30 Nicolas Pomarede + + * src/sound.c: + On a real STF, when envper==0, envelope's frequency is the same as + when envper==1, not half of it + [eaf1bc14fa6f] + +2010-08-08 Nicolas Pomarede + + * src/cycInt.c: + When adding a new internal interrupt, call CycInt_UpdateInterrupt + also if PendingInterruptCount < 0 In some rare cases (mostly when + using dma sound), CycInt_AddxxxxInterrupt functions can be called at + the exact same time when another interrupt is already elapsed (ie + PendingInterruptCount < 0). In that case, content of + PendingInterruptCount was reset without calling the handler for this + available interrupt first, which could result in lost hbl/timer + interrupt and possible crash. Calling CycInt_UpdateInterrupt in all + case when ActiveInterrupt>0 fixes the problem, as the available + interrupt will keep a negative value in InterruptHandlers[].Cycles + (fix possible crash in TalkTalk 2 readme.prg). + [a169698b4670] + +2010-07-26 Nicolas Pomarede + + * src/mfp.c: + When timers A or B are in pulse width mode, clear bit 3 of the ctrl + reg to emulate it as in delay mode. This is not completly correct as + we should also emulate GPIO 3/4, but it helps running some programs + (fix the game Erik) + [7b887fce4315] + +2010-07-13 Eero Tamminen + + * doc/manual.html: + document OS-call opcode breakpoint variables (and move continue + explanation under tracing) + [32b8a993ec4c] + + * doc/manual.html: + add comment about --parse option to manual debugger section + [3bf824840ae8] + +2010-07-12 Eero Tamminen + + * doc/manual.html: + restructure performance section and add OSX notes to manual + [71ee6366f6d1] + + * tools/hatari-local-rs232.sh: + add helper script for joining two hatari instances with serial + (rs232) + [97ed0b557530] + +2010-07-05 Nicolas Pomarede + + * src/video.c: + When removing left border, allow up to 32 cycles between hi and low + res switching (fix Megabeer by Invizibles) + [4f7824267536] + +2010-06-29 Eero Tamminen + + * doc/release-notes.txt: + update release notes + [29b3be7312f3] + + * src/debug/debugcpu.c, src/debug/debugdsp.c, src/debug/profile.c, + src/debug/profile.h: + add collected profiling information also to CPU & DSP disassembly + output + [1ffa3c7ac592] + + * src/debug/debugInfo.c: + add GEMDOS memory pool address for TOS 1.0 (from Gerhard Stoll) + [16e9204f916e] + +2010-06-25 Eero Tamminen + + * src/debug/breakcond.c: + fix breakpoint opcode variables for appl_yield & vq_gdos. make + line-A/F variable code clearer. + [4174ef707bf2] + + * CMakeLists.txt, doc/hatari.1: + document --mic option + [82f24fbae97b] + + * src/configuration.c, src/falcon/microphone.c, + src/includes/configuration.h, src/options.c: + add config & command line option for enabling/disabling mic + [28100d5e19f6] + + * src/falcon/microphone.c, src/falcon/microphone.h: + microphone.[ch]: int/0/1 -> bool/true/false for functions return + values + [514660bb2511] + + * src/CMakeLists.txt: + createBlankImage.c is already in Floppy lib, remove duplicate + [e90ea57be5c7] + +2010-06-16 Eero Tamminen + + * doc/release-notes.txt, doc/todo.txt: + update todo/notes to last changes + [8c59af69a7ac] + + * src/debug/breakcond.c: + add BIOS/XBIOS/GEMDOS/VDI/AES/Line-A/Line-F opcode breakpoint + support + [e31b534184f5] + + * CMakeLists.txt: + add GCC Mudflap (pointer debugging) support for CMake build + [dc37dc8db847] + + * doc/compatibility.html: + fix previous Hatari compat update + [165dd8feb0d4] + + * doc/emutos.txt: + update emutos compatibility list (after testing new line-A + breakpoints features) + [f945bae498bb] + +2010-06-15 Eero Tamminen + + * doc/compatibility.html: + add couple of missing STE games to compat list + [1a5599dcc352] + + * src/debug/debugui.c: + leave duplicate entries out of debugger readline history + [240767936317] + + * tests/test-dummies.c, tests/test-symbols.c: + update test sources for profiler addition & cleanup + [edb374413751] + + * tests/Makefile: + update tests Makefile for the profiler addition and clean up a bit + [c7f3cb19b26b] + +2010-06-14 Thomas Huth + + * tests/Makefile: + Added the Makefile for the tests again (deleted it a little bit + overhasty) + [c6bf86c60f22] + +2010-06-13 Thomas Huth + + * src/tos.c: + Allow the early TOS 0.00, too. + [72de08464b29] + + * cmake/DistClean.cmake: + Improved distclean target + [273e4064d494] + + * .hgignore: + Updated hg ignore file + [8bd5f224e167] + + * Makefile, Makefile-MinGW.cnf, Makefile-default.cnf, config- + default.h, python-ui/Makefile, src/Makefile, src/debug/Makefile, + src/falcon/Makefile, src/gui-sdl/Makefile, src/gui-win/Makefile, src + /uae-cpu/Makefile, tests/Makefile, tools/hmsa/Makefile: + Removed the old Makefiles. Use CMake now to generate the build files + of your choice. + [49640ff19f1c] + + * website/index.html, website/links.html: + Website update + [c7275f697c69] + +2010-06-12 Eero Tamminen + + * doc/release-notes.txt, src/debug/debugcpu.c, src/debug/debugdsp.c: + add DSP and CPU profiling commands to the debugger + [ad6756190967] + + * src/debug/CMakeLists.txt, src/debug/Makefile, src/debug/profile.c, + src/debug/profile.h: + add profiling functionality (using new symbol count & DSP + instructions APIs) + [a917c1a05461] + + * src/debug/symbols.c, src/debug/symbols.h: + API for getting DSP & CPU symbols counts + [cd1c60a3186f] + + * src/falcon/dsp.c, src/falcon/dsp.h: + API for getting last DSP instruction cycles + [f9fe56697d0b] + + * src/blitter.c, src/cycInt.c, src/debug/breakcond.c, + src/debug/debugInfo.c, src/fdc.c, src/ikbd.c, src/includes/screen.h, + src/includes/video.h, src/ioMemTabFalcon.c, src/ioMemTabST.c, + src/ioMemTabSTE.c, src/ioMemTabTT.c, src/joy.c, + src/memorySnapShot.c, src/mfp.c, src/psg.c, src/sound.c, + src/statusbar.c, src/uae-cpu/hatari-glue.c, src/uae-cpu/newcpu.c, + src/video.c: + Add HBL_PALETTE_LINES & HBL_PALETTE_MASKS defines to screen.h & use + them in video.h. + + This helps with GCC Mudflap pointer debugging as GCC now knows the + sizes of the related palette arrays. + + Because video.h now needs defines from screen.h, I had to add + includes for it to files that were including only video.h. + [d6839550659b] + + * src/includes/ioMemTables.h: + const ioMemTab struct members which won't change + [583cf75f5072] + + * Makefile, doc/release-notes.txt, src/CMakeLists.txt, + tools/hmsa/CMakeLists.txt, tools/hmsa/Makefile, tools/hmsa/hmsa.1, + tools/hmsa/hmsa.c, tools/hmsa/readme-hmsa.txt: + rewrite hmsa to support also empty disk creation + add manual page + (readme is now autogenerated from manual page in Makefile) + [774149db8bd4] + +2010-06-12 Thomas Huth + + * .hgtags: + Cleaned up hg tags file + [bbd691c40719] + +2010-06-12 : *** Version 1.4.0 *** + +2010-06-12 Nicolas Pomarede + + * doc/compatibility.html, doc/doxygen/Doxyfile, doc/manual.html, doc + /release-notes.txt, hatari.spec, src/includes/main.h, + src/memorySnapShot.c: + Update version to 1.4.0 + [98f234293466] [tip] + +2010-06-04 Thomas Huth + + * src/gui-osx/SDLMain.h: + Fixed Stop-Recording problem in Mac OS X GUI + [881291439adc] + +2010-06-03 Thomas Huth + + * src/avi_record.c, src/includes/pixel_convert.h, + src/screenSnapShot.c: + Take pixel layout into account when converting screen for PNG + snapshots. This hopefully fixes the endianess problem on Macs with + Intel processors. + [d1b6f581e22e] + +2010-06-03 Nicolas Pomarede + + * src/video.c: + Temporarily disable "cosmetic" patch from changesets 2823/2830 in + Video_ConvertPosition where FrameCycles >= CyclesPerVBL This causes + problem when $ff8209 is read during first 64 cycles of the VBL + (regression in Enchanted Land) + [595783001b0b] + +2010-06-02 Thomas Huth + + * src/falcon/dsp.c: + Silenced another possible compiler warning + [7e370fc1ffbe] + +2010-06-02 Eero Tamminen + + * src/debug/debugui.c: + fix compile warning on 64-bit + [f56efc333891] + + * src/zip.c: + fix zip.c free (should free array, not array count). + [4c735f028828] + +2010-06-02 Laurent Sallafranque + + * src/falcon/crossbar.c, src/falcon/dsp_core.c, src/falcon/dsp_core.h, + src/falcon/dsp_cpu.c, src/falcon/dsp_cpu.h: + dsp interrups should be in dsp_cpu.c code, not in dsp_core.c. I've + moved code to the correct place. Crossbar frame counter code update + (not yet finished) + [62685a040f60] + +2010-06-01 Eero Tamminen + + * doc/manual.html: + move debugger symbols documentation to its own section + [e43d74476894] + +2010-05-30 Eero Tamminen + + * python-ui/README, python-ui/release-notes.txt: + minor hatari doc update + [bdc2570f62e2] + + * python-ui/CMakeLists.txt, python-ui/Makefile, python-ui/hatariui.1: + add manual page for hatariui + [a901658fa667] + + * python-ui/hatariui.py: + fix hatariui help control/action description generation + [01b79c77d388] + +2010-05-30 Thomas Huth + + * CMakeLists.txt: + The poseAsClass problem has been fixed, no need to force a 32-bit + build anymore + [49c57d8cc01d] + + * src/gui-osx/AlertHooks.m, src/gui- + osx/English.lproj/InfoPlist.strings, src/gui- + osx/English.lproj/Localizable.strings, src/gui- + osx/English.lproj/SDLMain.nib/designable.nib, src/gui- + osx/English.lproj/SDLMain.nib/keyedobjects.nib, src/gui- + osx/French.lproj/InfoPlist.strings, src/gui- + osx/French.lproj/Localizable.strings, src/gui- + osx/French.lproj/SDLMain.nib/designable.nib, src/gui- + osx/French.lproj/SDLMain.nib/keyedobjects.nib, src/gui-osx/Info- + Hatari.plist, src/gui-osx/PrefsController.h, src/gui- + osx/PrefsController.m, src/gui-osx/SDLMain.h, src/gui-osx/SDLMain.m: + Fixed the poseAsClass problem by adapting SDLMain.m to the latest + version from SDL 1.2.14. Thanks to Jerome Vernet for the patch. + [2071b56221db] + +2010-05-29 Thomas Huth + + * CMakeLists.txt: + Universal binaries caused troubles during built - and since the OS X + GUI does not work on Mac OS X 10.4 anymore, I've disabled the + PowerPC support now. + [2d45f531ae53] + + * src/gui-osx/PrefsController.m: + Do not force color depth to 16 bpp, use default depth instead. + [174f5a1212bb] + + * src/gui-osx/CreateFloppyController.m: + Fix for compiling with older XCode + [5915bab9acb7] + + * src/gui-osx/AlertHooks.m, src/gui-osx/CreateFloppyController.m, src + /gui-osx/English.lproj/SDLMain.nib/designable.nib, src/gui- + osx/French.lproj/SDLMain.nib/designable.nib: + Jerome's latest update + [f23ba86b69c5] + +2010-05-28 Laurent Sallafranque + + * src/falcon/crossbar.c: + sorry, removed the 2 fprintf. Precedent comment must be read as + "corrects 25Mhz and 32 Mhz ..." + [82edeecbe0c3] + + * src/falcon/crossbar.c: + add: increase 258Mhz and 32 Mhz interrupts by taking into account + the pending cycles + [2b08d56579e6] + +2010-05-24 Thomas Huth + + * src/gui-osx/English.lproj/SDLMain.nib/designable.nib, src/gui- + osx/English.lproj/SDLMain.nib/keyedobjects.nib, src/gui- + osx/French.lproj/SDLMain.nib/designable.nib, src/gui- + osx/French.lproj/SDLMain.nib/keyedobjects.nib, src/gui- + osx/SDLMain.h, src/gui-osx/SDLMain.nib/classes.nib, src/gui- + osx/SDLMain.nib/info.nib, src/gui-osx/SDLMain.nib/keyedobjects.nib: + Jerome's latest update to the .nib files + [9b6af41ac267] + +2010-05-24 Eero Tamminen + + * doc/release-notes.txt, src/createBlankImage.c, src/gui- + sdl/CMakeLists.txt, src/gui-sdl/Makefile, src/gui-sdl/dlgFloppy.c, + src/gui-sdl/dlgNewDisk.c, src/includes/dialog.h: + ask whether newly created floppy image should be mounted to A: or B: + [8195baf82d1b] + + * doc/compatibility.html: + minor updates + [0455c652b45c] + +2010-05-23 Eero Tamminen + + * doc/emutos.txt: + latest DHS STE demos work with EmuTOS + [c03622269240] + +2010-05-23 Thomas Huth + + * CMakeLists.txt, src/CMakeLists.txt: + CMakeLists.txt updates for building on OS X + [1dc598df076b] + +2010-05-18 Eero Tamminen + + * python-ui/hatari.py: + fix Hatari UI ST/E borders size calculation for max screen size + change + [6f04fdd8bb0a] + + * src/screen.c: + max doubled res for ST/STE is 640x400 (before adding borders & + statusbar) + [2bca525abfdc] + +2010-05-17 Eero Tamminen + + * src/configuration.c, src/gui-sdl/dlgMain.c: + retain name of config file user loaded, fix the name leak and + correct error message + [83d8b64aa42d] + +2010-05-16 Thomas Huth + + * src/CMakeLists.txt: + Updates for building on Mac OS X + [3a2583110465] + + * src/hd6301_cpu.c, src/hd6301_cpu.h: + Fixed compiler warnings and moved variables to .c file + [89fbba6bba67] + +2010-05-16 Eero Tamminen + + * src/configuration.c: + fix python UI assert, add correct prefix to SdlAudioBufferSize + [4d50b6e82780] + +2010-05-16 Thomas Huth + + * doc/release-notes.txt: + Added LMC1992 emulation to release notes + [ac022682f790] + + * doc/images/main.png: + Updated the main dialog screenshot + [db9f7f6b9ddd] + + * src/gui-sdl/dlgMain.c: + Show file selection dialog when loading and saving configuration + files. + [d9630fde56a6] + +2010-05-15 Nicolas Pomarede + + * src/video.c: + Fix a potential bug/crash when running in monochrome and VBL was + delayed too much. In monochrome (71 Hz) a line is 224 cycles, which + means if the VBL is delayed by 160 cycles (DIVS) we will already be + on line 1 when adding first hbl/timer B interrupts for line 0. If we + detect VBL was delayed too much, we now add hbl/timer b immediatly + in the next 4 cpu cycles to be sure line 0 is processed. + [9dd6c5c12177] + +2010-05-13 Nicolas Pomarede + + * src/gui-osx/English.lproj/InfoPlist.strings, src/gui- + osx/English.lproj/SDLMain.nib/designable.nib, src/gui- + osx/English.lproj/SDLMain.nib/keyedobjects.nib, src/gui- + osx/French.lproj/InfoPlist.strings, src/gui- + osx/French.lproj/SDLMain.nib/designable.nib, src/gui- + osx/French.lproj/SDLMain.nib/keyedobjects.nib: + Update localized files for english and french + [1cae24a9621a] + + * src/gui-osx/CreateFloppyController.m, src/gui-osx/Info-Hatari.plist, + src/gui-osx/PrefsController.h, src/gui-osx/PrefsController.m, src + /gui-osx/SDLMain.h, src/gui-osx/SDLMain.m: + Apply Jerome Vernet's patch to update OSX version of the GUI + [73035156f3d4] + + * doc/hatari.1, doc/manual.html: + Add --sound-buffer-size to the man and html versions of the + documentation + [76bef71735d4] + + * src/options.c: + Add the option --sound-buffer-size to specify SLD sound buffer size + in ms + [2e0df51e1f6c] + + * src/sound.c: + Comment debug traces + [783c3f1c502a] + + * src/configuration.c, src/includes/configuration.h: + Save/restore SdlAudioBufferSize in the [Sound] section of hatari.cfg + [2e758ee7de3e] + +2010-05-12 Nicolas Pomarede + + * src/audio.c, src/includes/audio.h: + Allow to specify the size of SDL's sound buffer in ms using + SdlAudioBufferSize. Instead of specifying a fixed value of 1024, + which can confuse some faulty sound driver and create a hearable + delay, it's possible to use SdlAudioBufferSize to specify the size + of SDL's buffer. Default value of 1024 samples will give a 20-30 ms + sound buffer. Users having sound delay should try to force + SdlAudioBufferSize to 20 ms. + [bf1c8ace3386] + + * src/sound.c: + Add some debug traces + [232728040217] + +2010-05-12 Eero Tamminen + + * doc/emutos.txt: + update emutos.txt for new emutos v0.8.5 + [1557ec961677] + +2010-05-11 Eero Tamminen + + * python-ui/TODO: + add pygui TODO from Anders on config file selection + [a9e92b404ab6] + + * src/createBlankImage.c, src/includes/createBlankImage.h: + const unmodified path arg, return whether disk creation succeeded + [e0ce4e7bc587] + + * src/dim.c, src/includes/dim.h, src/includes/msa.h, + src/includes/st.h, src/msa.c, src/st.c: + const unmodified path argument for DIM/MSA/ST functions + [0049b3309f76] + +2010-05-10 Eero Tamminen + + * src/tos.c: + when claiming to switch to some machine mode, switch all CPU + parameters too (this is convenient and doing otherwise would confuse + users, especially if they don't notice that Hatari didn't switch all + parameters). + [9d00b382eb24] + +2010-05-09 Nicolas Pomarede + + * src/audio.c: + Align comments + [437e4eedb5f7] + + * src/audio.c: + After calling SDL_OpenAudio(), SoundBufferSize should be converted + in number of samples (not bytes) + [43a438bdc231] + +2010-05-09 Eero Tamminen + + * src/tos.c: + Correct ROM checks/switches for Falcon->TOS1.62 and 030/STE->TOS + 1.4. + [084f0f029518] + + * python-ui/dialogs.py, python-ui/uihelpers.py: + update Hatari UI copyright & version (now v1.0) + [591e79b730d7] + +2010-05-08 Nicolas Pomarede + + * doc/authors.txt: + Add Anders Eriksson to the contributors list + [22ff20072888] + + * src/includes/m68000.h, src/m68000.c: + Add a possibility for ADD/MOVE to pair when combined with d8(an,ix) + addressing mode. The bus cycle penalty caused by d8(an,ix) can cause + some instructions to pair, even if they wouldn't pair with some + other addressing modes. For example, add.l (a5,d1.w),d0 + move.b + 7(a5,d1.w),d5 will pair to take a total of 36 cycles (fix Sommarhack + 2010 Invitation by DHS) + [c5071f17020c] + +2010-05-05 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + ooops: I forgot to remove the debug flags + [c89fae547982] + + * src/falcon/dsp_cpu.c, src/falcon/dsp_disasm.c, + src/falcon/dsp_disasm.h: + reworked dsp disasm code. fix mem disasm order (mem changes were + displayed before the instruction in disasm mode). Optimized disasm + code + [4e94a6d38fc5] + +2010-05-04 Nicolas Pomarede + + * src/falcon/crossbar.c: + Use a scaling factor of 2.66 instead of 3 for mixing PSG (patch by + David Savinkoff) + [d1b385bdfcb4] + + * src/video.c: + Improve Video_ConvertPosition, use CyclesPerVBL instead of + evaluating CYCLES_PER_FRAME + [e9815654c3a8] + +2010-05-03 Thomas Huth + + * etc/win-ce.cfg: + Updated Win-CE sample config file. + [70ec266b3826] + +2010-05-02 Eero Tamminen + + * python-ui/hatari-console.py: + hatari console: mount-changes -> protect-floppy/hd + [253afcfdd198] + + * doc/todo.txt: + todo on ASCI/IDE write protection + [cc8fc0afa05f] + + * python-ui/README: + update python UI readme + [9c14727e1aa4] + + * python-ui/TODO, python-ui/dialogs.py, python-ui/hatari.py: + support --protect-floppy/-hd in python UI + [592dc1e015a4] + + * doc/hatari.1, doc/manual.html, doc/release-notes.txt, + src/configuration.c, src/gemdos.c, src/gui-sdl/dlgHardDisk.c, + src/includes/configuration.h, src/options.c: + unify how floppy and (GEMDOS) harddisk write protection is used: + - rename bGemdosChanges -> nWriteProtection + - add "auto" option also for GEMDOS emulation (disables Fattrib()) + - add --protect-floppy command line option + - rename --mount-changes to --protect-hd + - update documentation + [4e2e821c95ce] + +2010-05-02 Nicolas Pomarede + + * src/video.c: + In Video_ConvertPosition, handle the case where we read the position + between the last HBL and the start of the next VBL. During 64 cycles + FrameCycles can be >= CYCLES_PER_FRAME (harmless fix, only useful + when using --trace to get correct positions in the logs). + [eaaaa1b449be] + +2010-05-02 Eero Tamminen + + * doc/compatibility.html: + update falcon compat notes + [0fbf0ee26b62] + + * doc/compatibility.html: + trivial compat update + [febc000f3db6] + +2010-05-02 Thomas Huth + + * doc/compatibility.html, doc/manual.html: + Some more HTML fixes and improvements + [5d956e94783f] + +2010-05-01 Eero Tamminen + + * etc/README, etc/n810.cfg: + update config example for Nokia Maemo tablets (not tested) + [a46d4c3bd0c7] + +2010-05-01 Thomas Huth + + * doc/manual.html: + Fixed HTML bug + [b0699e8d1ad2] + +2010-05-01 Eero Tamminen + + * doc/manual.html: + add instructions on debugging normal AHCC compiled TOS/GEM programs + with symbols + [dc9326accf5c] + + * src/debug/symbols.c: + fix symbols double free and load address offset handling + [960bb0c2426a] + + * src/debug/debugInfo.c: + show all env vars and cli args with the "info basepage" command + [6073d340e13b] + +2010-04-28 Laurent Sallafranque + + * src/falcon/crossbar.c: + When crossbar dma sound is stopped, we must call Sound_Update() to + update the samples buffer + [adcacc92d016] + +2010-04-28 Thomas Huth + + * CMakeLists.txt: + Fixed stupid typo ... forgot an else() statement + [9ab74fbc50ec] + +2010-04-28 Eero Tamminen + + * src/vdi.c: + VDI opcode & subcode are unsigned, fix (tracing) checks against them + [c7610ef027d1] + + * src/xbios.c: + opcode is of unsigned type, so comparing it with >= 0 is redundant. + [724488e0900f] + +2010-04-28 Nicolas Pomarede + + * src/falcon/crossbar.c: + For crossbar sound, check end address is greater than start address + [789764c08ff4] + +2010-04-27 Thomas Huth + + * CMakeLists.txt: + unset READLINE_FOUND in case it's not a good readline library, so + that the src/CMakeLists.txt does not try to link against this + library + [6fa60c3dfd05] + + * src/bios.c: + The BiosCall variable is of unsigned type, so comparing it with >= 0 + is redundant. + [20efcdbaf5b2] + +2010-04-27 Eero Tamminen + + * readme.txt: + fix RHEL problem section, add contents + [fa08d4b913d0] + +2010-04-27 Nicolas Pomarede + + * src/dmaSnd.c: + When dma sound is stopped, we must call Sound_Update() to update the + samples buffer In case dma is turned off during the vbl, we must + fill the sample buffer with all the samples that were generated + before stopping sound. This could cause some sound bugs in EPSS by + Unit 17 (and sometimes a complete crash of Hatari) because the dma + interrupt won't happen at the expected place (EPSS is doing clr.b + $ff8901 + move.b #3,$ff8901 to force an immediate start of the + sound) + [41a7ad85ef6a] + + * src/dmaSnd.c: + Fix typo in log message + [adc1fc83ebdb] + + * src/dmaSnd.c: + For DMA sound, check end address is greater than start address + (testing dma.frameLen <= 0 is wrong because dma.frameLen is + unsigned) + [f0970768a021] + +2010-04-26 Thomas Huth + + * CMakeLists.txt, cmake/FindPortAudio.cmake: + Clean up CMAKE_REQUIRED_LIBRARIES after test has been done or other + unrelated tests later might fail. + [483d790192eb] + + * src/includes/gemdos_defines.h: + Error code for write-protected is -13, not -12 + [9d4d83be9e40] + +2010-04-26 Eero Tamminen + + * readme.txt: + note the RHEL readline issue in installation instructions + [d803a2d91018] + + * doc/manual.html, doc/release-notes.txt: + tracing documentation improvements + [4babcc5a30f7] + +2010-04-25 Eero Tamminen + + * doc/compatibility.html, doc/emutos.txt: + compat updates: keff doesn't work on falcon, emperor works with + emutos + [d47ab4973210] + + * src/xbios.c: + add names for all XBIOS calls when tracing + [068170b0544b] + + * src/bios.c: + give names for all bios functions when tracing + [34a3d33db441] + +2010-04-24 Thomas Huth + + * cmake/FindPortAudio.cmake: + Removed bad quotations in portaudio detection file + [be0f922c0d0b] + + * CMakeLists.txt: + Use the additional CFLAGS from SDL for compilation + [5e21a8c46d8b] + +2010-04-24 Eero Tamminen + + * src/vdi.c: + add more verbose VDI tracing (sub-opcode + VDI function name) + [6a5adae76732] + +2010-04-22 Laurent Sallafranque + + * src/falcon/crossbar.c: + applied David's patch (it corrects some bugs and fix attenuation and + gain values) + [2785c5912789] + +2010-04-21 Eero Tamminen + + * python-ui/TODO: + more python-UI debugger TODOs + [9ab9d0009a95] + +2010-04-19 Eero Tamminen + + * python-ui/debugui.py, python-ui/release-notes.txt: + Option for whether Hatari UI debugger will change to new PC address + (whenever emulation is stopped again) + [ffe2d43c8f25] + + * python-ui/config.py, python-ui/hatariui.py: + fixes for Hatari UI missing config saving + [c2d0f3becc1f] + +2010-04-18 Nicolas Pomarede + + * src/dmaSnd.c: + Patch by David Savinkoff : fix possible memory corruption that could + alter video/sound + [ae01f13d72de] + +2010-04-18 Eero Tamminen + + * python-ui/TODO, python-ui/release-notes.txt, python-ui/uihelpers.py: + update python UI docs + [bc7df15c5776] + + * python-ui/dialogs.py, python-ui/hatari.py, python-ui/hatariui.py: + Add new settings dialog for configuring HD images and dir. Also + remove get/set_usehd stuff, as it's not handled properly, setting + the image/dir option already should do what's needed... + [dd66431fe4f3] + + * doc/todo.txt: + todo for partition counting + [084d2b4978d4] + + * src/options.c: + improve missing file handling for option setting: + - "none" as file name can be used to disable functionality even when + file existence check is requested. This is needed for Hatari UI + hard disk settings + - midi and rs232 create their output files so the files don't need + to pre-exist + - midi input file needs to pre-exist + [77038f38c219] + + * doc/manual.html: + for v1.4, passes still HTML validation + [1a7c135147db] + + * python-ui/dialogs.py, python-ui/hatari.py: + Support max size in Hatari UI, remove aspect ratio & spec512 + controls from it (they work fine so they're redundant options for + the UI) + [492a52adc4c5] + + * python-ui/config.py, python-ui/debugui.py, python-ui/hatari.py, + python-ui/hatariui: + fix debugger UI config loading + - move config path handling from hatari.py back to config.py for this + - rename HATARI_CONFDIR to more correct HATARI_SYSTEM_CONFDIR + [c87dd379aa02] + + * doc/authors.txt: + update authors list and make sure its text fits into 80 cols + [a12f5bf9cc53] + +2010-04-17 Eero Tamminen + + * doc/compatibility.html: + jam-cols works fine + [0b014d7939e1] + +2010-04-16 Eero Tamminen + + * doc/images/monitor.png, doc/images/screen.png, doc/manual.html: + split manual screen section to Atari monitor and Hatari screen + sections (with new screenshots etc). + [9883146ec514] + + * src/gui-sdl/dlgScreen.c: + remove aspect correction option from GUI as unnecessary: + - disabling it can produce really strang Falcon resolutions + - it works as fine + [969c4439ba72] + +2010-04-15 Nicolas Pomarede + + * website/scrshots6.html: + For Falcon, remove 'higly experimental' from the description + [d05718701223] + +2010-04-15 Eero Tamminen + + * doc/release-notes.txt: + mention fullscreen/pause fix + [b0fec3c1469d] + +2010-04-15 Nicolas Pomarede + + * website/links.html: + Fix type in url + [a939a65b2cb5] + +2010-04-14 Nicolas Pomarede + + * website/docs.html, website/index.html, website/links.html: + Small changes in description regarding TT/Falcon, add link to + todo.txt + [36a74890f71e] + +2010-04-13 Eero Tamminen + + * doc/compatibility.html, doc/emutos.txt, python-ui/release-notes.txt: + trivial doc updates + [aff5593c4dda] + +2010-04-12 Nicolas Pomarede + + * src/video.c: + Improve timings when writing to $ff8205/07/09 when hscroll is used + The MMU starts reading video data 16 cycles earlier in that case + (fix Pacemaker's Bump Part by Paradox) + [1c6984f95830] + +2010-04-11 Eero Tamminen + + * doc/compatibility.html: + compatibility: 1.3.1+ -> 1.4, add AHCC/Pure-C/MP2 + [2a880c46ea75] + +2010-04-09 Nicolas Pomarede + + * src/sound.c: + Use the same indent style as the rest of the file + [45557987d41a] + +2010-04-09 Eero Tamminen + + * python-ui/Makefile, python-ui/config.py, python-ui/hatari.py, + python-ui/hatariui: + use and handle Hatari system configuration file correctly (if one + exists, but saved user configuration is missing) + [9f81b10fef96] + +2010-04-07 Eero Tamminen + + * doc/manual.html: + update manual feature list based on Laurent's comments + [9a217ffeee4d] + +2010-04-06 Eero Tamminen + + * doc/manual.html, doc/release-notes.txt, doc/todo.txt: + minor updates to manual, release notes and todo + [fe7f031388d2] + +2010-04-06 Laurent Sallafranque + + * src/dmaSnd.c, src/sound.c: + add David's latest patches for DMA sound. Thanks again David. + [9ffac230e9cf] + + * doc/todo.txt: + update the falcon and STe Dma sound TODO list + [baa046aeefdf] + +2010-04-06 Eero Tamminen + + * doc/images/harddisks.png, doc/images/main.png, + doc/images/newfloppy.png, doc/images/system.png, doc/manual.html: + update manual screenshots and texts for options dialogs (except for + screen dialog which I update later) + [c7121754c80a] + +2010-04-05 Eero Tamminen + + * doc/manual.html: + improve/update perforance section in manual + [38b661d0da92] + + * doc/compatibility.html: + update falcon compatiblity reasons + [9e77fd74d470] + + * src/debug/evaluate.c, src/debug/log.h: + set LOG_TRACE() debug stuff as unlikely to speed emulation when + tracing isn't enabled + [8af4ed017568] + + * src/convert/macros.h, src/convert/spec320x16.c, + src/convert/spec320x32.c, src/convert/spec640x16.c, + src/convert/spec640x32.c: + fix x86 past-array-end read for spec512 conversion + [2a02fa8735e3] + +2010-04-05 Nicolas Pomarede + + * src/m68000.c: + Correctly initialize LastOpcodeFamily with a valid opcode. + [72fe4de1a4b6] + + * src/includes/m68000.h, src/m68000.c, src/uae-cpu/gencpu.c, src/uae- + cpu/newcpu.c, src/uae-cpu/newcpu.h: + Better handling of d8(an,ix) addressing mode on ST (including + pairing). On ST, d8(An,Xn) is causing a misaligned bus access and + will generate a 2 cycles penalty on every use (can be 4 cycles if + used as both source and dest in a move). Due to this particular bus + access, an instruction using d8(An,Xn) will usually take 4n+2 cycles + and could pair with a previous compatible instruction. We use + BusCyclePenalty to count the number of cycles lost by d8(an,ix) and + we add this value to the current number of cycles depending on + whether pairing is used or not. This code should handle all possible + cases (previous code only handled some special cases with add/sub) + (verified with various combinations on a real STF, as well as in ULM + Demo Menu, Anomaly Demo Intro, DHS Sommarhack 2010). + [9eb34ca61590] + +2010-04-04 Eero Tamminen + + * tools/hmsa/Makefile: + hmsa build needs LDFLAGS too + [619ab05097ba] + + * Makefile-default.cnf, src/falcon/hostscreen.c, src/main.c, + src/screen.c, tests/Makefile, tests/test-scripting.sh: + add GCC "mudflap" instrumentation support: + http://gcc.gnu.org/wiki/Mudflap_Pointer_Debugging + [604cc0ae1597] + + * src/screen.c: + make it more explicit that double buffering isn't used, and why + [9f3bc3edeb1c] + + * doc/hatari.1, src/includes/options.h, src/main.c, src/options.c: + add option to disable SDL parachute to get Hatari core dumps. (and + remove redundant comments from headers and redundant var + initialization to zero) + [7e9a24db3756] + + * src/debug/symbols.c, tests/debugui/debugger.ini, tests/test- + symbols.c: + allow removing symbols + make tests use that (will get rid of + unfreed allocs messages in tests) + [739add946452] + +2010-04-01 Laurent Sallafranque + + * src/dmaSnd.c: + added David's latest patch. Thanks David !! :) + [bad1e1cc5b85] + +2010-03-31 Laurent Sallafranque + + * src/audio.c, src/includes/dmaSnd.h: + fix headers in audio.c + [e285a9dad08e] + +2010-03-31 Eero Tamminen + + * src/debug/breakcond.c: + fix !_GNU_SOURCE compilation warning / remove redundant isblank() + [6b53c0bfa595] + + * doc/emutos.txt: + add few programs working with emutos + [068e7d0dc668] + + * doc/compatibility.html: + add URLs for STE compat list games + [f181a61fc3fb] + +2010-03-30 Laurent Sallafranque + + * src/dmaSnd.c: + I uploaded the wrong David's patch yesterday. Here is the correct + one. + [b8d5235fb3ed] + +2010-03-29 Laurent Sallafranque + + * src/dmaSnd.c: + fix mono divider value + [12b5519f1d06] + +2010-03-29 Laurent Sallafranque + + * src/audio.c, src/dmaSnd.c: + add David's patch + [0b698d74de5a] + +2010-03-27 Thomas Huth + + * doc/CMakeLists.txt: + Fixed manpages target for CMake version 2.6.0 + [a799659c1e53] + +2010-03-24 Laurent Sallafranque + + * src/dmaSnd.c: + David's optimizations and improvements's patch for LCM1992 + bass/treble emulation. He also added anti aliasing for 50 Khz + frequency. + [74f20f88d57e] + +2010-03-21 Laurent Sallafranque + + * src/dmaSnd.c: + fix: mix correctly Yamaha's sound and DMA's sound together. Phazer + by 505 from Blubber demo runs well now + [4a7cc38aa498] + +2010-03-21 Eero Tamminen + + * src/falcon/hostscreen.c: + remove debug stuff that makes paused text disappear after fullscreen + toggling (hostscreen render end function call results in an extra + statusbar update) + [5e82d68ba1b0] + + * src/includes/video.h, src/screen.c, src/video.c: + keep emulation paused while toggling fullscreen: + - when emulation is paused, screen needs to be redrawn after the + toggle, add internal screen.c function for this + - for redrawing TT screen, a function needs to be exported from + video.c for screen.c + [3bf843d5ae90] + +2010-03-21 Thomas Huth + + * src/debug/debugui.c: + Disable the risky system call by default. + [2dbd35845115] + + * src/gui-sdl/dlgFileSelect.c, src/zip.c, tools/hmsa/hmsa.c: + Free allocated memory in case of errors. Thanks to Christoph Fritz + for the patch. + [10aca286b32a] + + * src/printer.c: + Make sure that Printer_ResetInternalBuffer is always called, also + when pPrinterHandle is invalid + [aa25ee217ceb] + +2010-03-21 Laurent Sallafranque + + * src/dmaSnd.c, src/sound.c: + applied David's patches. + [db609c138814] + +2010-03-21 Eero Tamminen + + * src/CMakeLists.txt, src/Makefile, src/falcon/hostscreen.c, + src/falcon/hostscreen.h, src/includes/resolution.h, + src/resolution.c, src/screen.c: + Fix: limit max zoom size to largest video mode available to SDL: + - move video mode search and selection functions to new resolution.c + file + - add Resolution_GetLimits() function for getting largest resolution + from configuration which is clipped to largest SDL video mode + - use int as args instead of Uint32 as that's what the SDL functions + accept + - change screen.c and hostscreen.c to use these new functions + - add resolution.c to C/Makefile and document its functions + [db1c0fd41108] + +2010-03-20 Eero Tamminen + + * doc/release-notes.txt, doc/todo.txt: + note in docs: options for how many lines to disasm & memdump + [4ea11a28275f] + + * src/configuration.c, src/includes/configuration.h, src/screen.c: + clip low/med rez borders according to max size, remove border size + config settings (can be done now that Nicolas fixed video.c in + revision 3e393cb7ebad) + [6e41b2bbd122] + + * doc/compatibility.html: + last Braindamage demo difference has disappeared + [5d64a2028858] + + * src/falcon/hostscreen.c: + remove hostscreen save&restore on fullscreen toggling, it doesn't + work properly (when SDL/host screen is larger than Atari one, + hostscreen was restoring it in different position (0,0) than where + Videl will draw the Atari screen). + [e829357ea79a] + + * src/falcon/hostscreen.c: + don't use SDL_WM_ToggleFullScreen() if Atari screen size differs + from SDL screen rename: sizeChanged -> sizeDiffers + [051a9ab85188] + +2010-03-20 Laurent Sallafranque + + * src/dmaSnd.c: + add : 25, 12, and 6KH frequencies for IIR filter LMC1992 emulation + should be complete now + [4dbb8ef7b1e7] + +2010-03-19 Laurent Sallafranque + + * src/dmaSnd.c: + renamed all IIR functions to Dma_ + [650eef50dca5] + + * doc/authors.txt, src/dmaSnd.c: + update and fix BASS / Treble code (again, thanks to David) + [04cb09f32043] + +2010-03-19 Nicolas Pomarede + + * src/video.c: + Ensure left border is large enough to copy video bytes when display + starts 2 or 8 bytes earlier + [3e393cb7ebad] + +2010-03-18 Laurent Sallafranque + + * src/dmaSnd.c, src/includes/dmaSnd.h, src/main.c: + add: first try to implement LMC1992 bass / Treble. Mega thanks to + david for his FIR code and his help. + [e8ca39fd9666] + +2010-03-18 Eero Tamminen + + * src/falcon/crossbar.c: + fix portaudio crash (it was being re-initialized on every reboot and + didn't like that) + [0b6213fafb93] + +2010-03-17 Eero Tamminen + + * src/falcon/hostscreen.c: + fix Falcon screen size changes on fullscreen which don't cause video + mode change (need to clear screen, especially in case new Atari + screen size is smaller, otherwise parts of old Atari screen contents + are left there.) + [90364f0ccb43] + + * src/falcon/hostscreen.c: + fix: modes returned by SDL_ListModes() are not sorted + [1f3ad505fdc2] + +2010-03-16 Nicolas Pomarede + + * configure: + Add '--cross-compile-win32' to the configure script + [812a579a7df5] + + * src/CMakeLists.txt: + Set "windres" as a default rc compiler under windows + [f8183de23ae4] + +2010-03-16 Eero Tamminen + + * src/gui-sdl/dlgMain.c, src/gui-sdl/dlgScreen.c: + use dialog names suggested by Thomas, "Doubled" -> "Zoomed" + [1d0beb94f741] + + * readme.txt: + update build instructions + [24caa8e05f2d] + + * CMakeLists.txt: + glob isn't used anymore, remove + [1215f644921f] + +2010-03-15 Eero Tamminen + + * src/configuration.c, src/options.c: + set default/zoomed size according to 2x (ST-low + max borders) + [098ef1c548ec] + +2010-03-13 Eero Tamminen + + * python-ui/hatari-console.py: + hatari-console sleep command + [67bb4ba9ff1f] + + * src/control.c: + fix compiler warning + [40d829845d49] + +2010-03-13 Nicolas Pomarede + + * cmake/Toolchain-mingw32.cmake: + Add a toolchain file to cross compile the Windows version under + another OS using mingw32 To use this toolchain, you should have a + working mingw setup (with all required devel sources for sdl, png, + ...) Then run : cmake -DCMAKE_TOOLCHAIN_FILE=cmake/Toolchain- + mingw32.cmake . + [057aaadff2b1] + + * src/CMakeLists.txt: + Add support for .rc ressouce files when compiling a Windows + executable using cmake + [f2056d29f15b] + +2010-03-12 Eero Tamminen + + * tests/debugui/console.ini, tests/debugui/debugger.ini, tests/test- + scripting.sh: + add test script for debugger and console scripting features + [277621041d3e] + + * python-ui/hatari-console.py, python-ui/release-notes.txt: + hatari-console can be scripted. + + (moved also the code around so that now all functions are methods in + some suitable class) + [ee1b16f9aa30] + + * src/debug/breakcond.c: + fix: segfault when using debugger "da" command without DSP being + enabled + [2d7d9a4a31a5] + + * src/debug/debugui.c: + Error message at startup when exiting due to debug input file being + not found. + [6cd62826f8fb] + + * src/debug/debugui.c: + fix: double free in debugger input file parsing + [ff3f2ef09a8d] + + * src/configuration.c, src/includes/configuration.h, src/shortcut.c: + MOUSEMODE -> MOUSEGRAB (more accurate name) + [7e6b8db90464] + + * src/debug/debugui.c, src/file.c: + fix: File_MakeValidPathName() could write past the string end. + [14fe17ede6e1] + + * python-ui/hatari-console.py, python-ui/release-notes.txt: + update Hatari UI release notes and hatari-console options. + [94f4a1212c64] + + * doc/hatari.1, python-ui/hatari.py, python-ui/hatariui.py, + src/options.c: + add --saveconfig option for Hatari UI so that user doesn't need + manually save/sync Hatari config for it. + + Also added configuration validation function to Hatari UI so that it + can know early at its startup when to ask Hatari to do --saveconfig. + Previously it could die to exeption somewhat later on where it + wasn't (at least easily) catchable. + + If --saveconfig doesn't help, Hatari UI will still get exeption + which tells what part of the configuration is out of sync between + Hatari & UI. + [46baf24808d4] + +2010-03-11 Eero Tamminen + + * python-ui/config.py, python-ui/dialogs.py: + improved UI button type & warning message + [ebc41ec53b80] + + * python-ui/config.py, python-ui/debugui.py, python-ui/dialogs.py, + python-ui/hatari.py, python-ui/hatariui.py, python-ui/uihelpers.py: + fix for previous Hatari-UI zooming update, update Hatari UI sources + copyright & email info + [0863026d395b] + +2010-03-10 Eero Tamminen + + * python-ui/TODO, python-ui/dialogs.py, python-ui/hatari.py: + adapt Hatari-UI for bZoomLowRes changing to max window size options + [32868e9249af] + + * doc/hatari.1, doc/manual.html, doc/release-notes.txt, doc/todo.txt, + src/options.c: + add options for aspect ratio correction and max window size + doc + update + [6fa083381fca] + + * src/falcon/hostscreen.c: + fix: hostscreen resolution changing while in fullscreen + [7251e7f708fb] + + * Makefile-default.cnf: + Makefile.cnf template: make LIBS overridable, update comments + [59626bc22808] + +2010-03-10 Laurent Sallafranque + + * src/falcon/crossbar.c: + fix 32 MHz timer + [74aad0454f93] + + * src/debug/debugInfo.c: + add: implemented Iphigeny into "info crossbar" code. Infos are + easier to read. + [483089def6ee] + +2010-03-09 Nicolas Pomarede + + * Makefile-MinGW.cnf: + Makes HOSTCC overridable by env variable + [f1e336b35380] + + * Makefile-MinGW.cnf: + When crosscompiling, HOSTCC must be 'gcc', not CC (else it will use + mingw and will fail) + [c784976559db] + +2010-03-08 Laurent Sallafranque + + * src/dmaSnd.c, src/falcon/crossbar.c: + fix: replace linear volume tables by logarythmics ones. Volume is + now correctly emulated. + [2bf8f18d7eb7] + +2010-03-07 Laurent Sallafranque + + * src/dmaSnd.c: + fix: remove compiler warning + [9c97eaa78e25] + + * src/dmaSnd.c: + add: LMC1992 volume emulation : left, right and master volumes are + emulated now. Todo: the bass and treble emulation + [944b4ac97377] + +2010-03-06 Thomas Huth + + * python-ui/hatariui: + Make python-ui wrapper relocatable + [c0ced9cd7d58] + +2010-03-06 Eero Tamminen + + * src/falcon/hostscreen.c: + fix statusbar assert when running Alive Falcon demo on fullscreen + [7bf314510939] + +2010-03-05 Eero Tamminen + + * src/falcon/hostscreen.c: + do aspect ratio & max window size scaling in hostscreen + [d0a6ebcf9d36] + + * src/change.c, src/configuration.c, src/falcon/videl.c, src/gui- + sdl/dlgMain.c, src/gui-sdl/dlgScreen.c, + src/includes/configuration.h, src/includes/dialog.h, src/options.c, + src/screen.c, src/video.c: + split screen to separate monitor and window dialogs, replace zoom + option with aspect ratio and max size options + [b7002300be19] + + * src/includes/statusbar.h, src/statusbar.c: + add statusbar function needed by new zooming code. + [75793f762686] + + * src/falcon/hostscreen.c, src/falcon/hostscreen.h, + src/falcon/videl.c, src/includes/video.h, src/screen.c, src/video.c: + doing aspect correction based on Videl values not feasible (yet), + revert. + - instead do simple 2^ aspect correction in hostscreen + - remove the old zooming that was ifdeffed out by previous comment + [e4d73a152c2f] + +2010-03-04 Eero Tamminen + + * src/falcon/hostscreen.c, src/falcon/hostscreen.h, + src/falcon/videl.c, src/includes/video.h, src/screen.c, src/video.c: + preliminary support for Falcon/TT Monitor aspect ratio correction, + also + - disable Falcon/TT zooming so that issues with aspect ratio can be + found + - do video mode change only when needed + [87b9c628b6c2] + +2010-03-04 Thomas Huth + + * src/uae-cpu/CMakeLists.txt: + Fixed cross-compiling with CMake + [1fcbc2dc96a5] + +2010-03-04 Eero Tamminen + + * src/falcon/hostscreen.c: + make sure that Falcon fullscreen toggling doesn't mess window size: + - SDL_WM_ToggleFullScreen() should use requested WinSize, not the + resulting one that's modified by scaling and whichever screen + resolutions SDL had available as fullscreen + - user might even change scaling settings while in fullscreen + [048a8d8a136d] + + * python-ui/TODO, python-ui/dialogs.py, python-ui/hatari.py: + Hatari UI: support --slowfdc, update CPU types, update TODO + [ce4aef90bb02] + +2010-03-02 Eero Tamminen + + * python-ui/hatari-console.py: + add new command line options & debugger commands to hatari-console + and update the help text. + [566647b13866] + + * src/options.c: + fix option error case for previous fix, improve comments (for + --option case) + [1044462d3587] + + * src/options.c: + fix: segfault when using --joyX option without argument + [dc6253fc79e5] + + * src/debug/debug_priv.h, src/debug/debugcpu.c, src/debug/debugdsp.c, + src/debug/debugui.c: + don't save disasm/memdump addresses to emulated state as they aren't + part of that. change debugger state file extension from .break to + .debug. + [fac24f29b4b1] + + * src/configuration.c, src/debug/debugcpu.c, src/debug/debugdsp.c, + src/debug/debugui.c, src/debug/evaluate.c, + src/includes/configuration.h: + Make debugger disasm and memdump lines configurable from Hatari + config, move number base variable from Log section to new Debugger + section (as it's only used by debugger). + [ce0769a48e1f] + +2010-03-01 Laurent Sallafranque + + * src/dmaSnd.c: + fixed switch condition + [d7b955eebd4d] + + * src/dmaSnd.c: + Added some code for Microwire & LMC 1992 emulation. + [f62c25f2259c] + +2010-03-01 Eero Tamminen + + * src/debug/breakcond.c: + fix: trimmed string needs separate var from the one that will be + freed. It may also be useful to be able to remove or list + breakpoints from DSP although it would be disabled (e.g. from the + UI). + [b3b48c24fb89] + + * src/debug/breakcond.c, src/debug/breakcond.h, src/debug/debugcpu.c, + src/debug/debugdsp.c, src/debug/debugui.c, src/debug/debugui.h, + src/memorySnapShot.c: + breakpoints aren't part of emulated state, save them to separate + file from memory snapshot + [9df6a9492eff] + +2010-02-28 Eero Tamminen + + * doc/hatari.1, doc/manual.html, doc/release-notes.txt, src/options.c: + document "parse" command and "--parse" & --trace-file options + [1c80553f257c] + + * doc/compatibility.html: + link to right Protracker STE, add Amiga Demo 2 (has also 50kHz + replay) + [aaae80b005f5] + + * src/debug/debugui.c: + fix Thomas' compile warnings: check system() & chdir() return values + [c9608ebcd966] + +2010-02-28 Nicolas Pomarede + + * Makefile-MinGW.cnf: + BUILD_HOST should default to windows + [291725574b78] + + * Makefile-MinGW.cnf, src/gui-win/Makefile: + Add BUILD_HOST to allow to build the windows binary from windows or + from linux + [1937af63f511] + +2010-02-28 Thomas Huth + + * src/CMakeLists.txt, tools/CMakeLists.txt, tools/hmsa/CMakeLists.txt: + Build hmsa with CMake build system, too + [9aa93eb03a75] + +2010-02-28 Eero Tamminen + + * src/debug/debug_priv.h, src/debug/debugcpu.c, src/debug/debugdsp.c, + src/debug/debugui.c: + move readline match callback names to where function names are, add + completion for registers + [f0e6d62b4f0e] + +2010-02-28 Thomas Huth + + * CMakeLists.txt, tools/CMakeLists.txt: + Install shell script tools + [52cb1e9b5f67] + + * src/CMakeLists.txt: + Install hatari-icon.bmp and tos.img, too + [5ada12e52cd2] + + * CMakeLists.txt, cmake/config-cmake.h: + Make BIN2DATADIR configurable + [2727597f95be] + + * cmake/config-cmake.h, config-default.h: + Removed unused defines + [074ece69c9dd] + + * Makefile-default.cnf: + Link against libm in old Makefile build system, too. This is + required for upcoming Fedora core 13, see bug #16851 for details. + [2b4b8d88d702] + + * CMakeLists.txt, cmake/FindMath.cmake, src/CMakeLists.txt: + Added Math library to CMake build system. This should fix bug + #16851. + [265723760fde] + +2010-02-27 Thomas Huth + + * cmake/FindPortAudio.cmake: + We need portaudio version 2, so check for a unique function of that + version + [188556c9d3b9] + +2010-02-28 Eero Tamminen + + * tests/debugui/debugger.ini, tests/debugui/dsp-test.sym, + tests/debugui/etos512.sym, tests/etos512.sym: + add/move test files for debugger commands file parsing + [0389f04be522] + + * src/debug/debugui.c: + fix reading commands file: evaluate expressions, fix leak, skip + empty & comment lines + [e536598dc9df] + +2010-02-27 Eero Tamminen + + * src/debug/debugui.c, src/debug/debugui.h, src/main.c, src/options.c: + fix: debugger commands file needs to be read after CPU & DSP are + initialized, otherwise breakpoints (and possibly some other + commands) given from it won't work when the file is given as a + command line option. + [48909f343ec9] + + * src/debug/breakcond.c: + conditional breakpoints: allow DSP breakpoints only if DSP enabled, + fix symbol matching + [09c8a67127f4] + + * tests/os-header.sym, tests/test-symbols.c: + add os-header.sym symbols file and use that in debugger symbol + handling tests (those values don't change like etos ones may and the + file is smaller) + [c956d8971d48] + + * src/debug/debugui.c, src/debug/debugui.h, src/options.c: + option and command to parse debugger commands from a file + [bc41eaec8c6a] + + * doc/compatibility.html: + Alive demo issues were in use of frameskip, it works fine + [9ca5cbeffd75] + +2010-02-26 Eero Tamminen + + * src/debug/debugcpu.c, src/debug/debugdsp.c: + continue dumping from previously given DSP memory space/address if + none specified (+ add <> to DSP & CPU address ranges) + [2844eca06783] + + * config-default.h, src/main.c: + glob.h doesn't need to checked. add missing sys/times.h check, warn + if it's used + [d771fd1a63d9] + + * doc/release-notes.txt, src/main.c: + Fix VBLs/s counting to work also when --run-vbls isn't used + [725ecd4cbe42] + +2010-02-26 Laurent Sallafranque + + * doc/compatibility.html: + add : bound 42 (MJJ Prod) to compatibility list + [d3ff24644059] + +2010-02-25 Laurent Sallafranque + + * doc/compatibility.html: + added : Ishar3 (CD version) + [9a0f61053f6b] + + * src/falcon/crossbar.c: + fix: clear DAC (L+R) buffers when DMA play sound stops. Else, the + buffers loops forever. + [37aa7a6a572b] + + * src/falcon/dsp_cpu.c: + optimisation of MAC, MACR, MPY and MPYR + [1d6526e3d2f8] + +2010-02-25 Eero Tamminen + + * doc/manual.html, doc/release-notes.txt: + mention "cd" & "exec" commands in docs + [cdca9b046255] + + * src/debug/debugui.c: + fix usage output for debug commands with no short name. + [6b2adc395285] + + * src/debug/debugui.c: + add "exec" debugger command + [0ef75733965b] + + * src/debug/symbols.c: + output symbols list in the same format as they're input + [96820ec60642] + + * src/debug/debugui.c: + add "cd" debugger command + [ff4187f89ac2] + + * src/debug/debugdsp.c: + fix DSP symbols in disasm output + minor DSP debugger output + improvements + [945d40e7eaef] + + * src/gemdos.c: + fix gemdos.c compiler warning + [8c1e08f1ec6a] + +2010-02-25 Laurent Sallafranque + + * src/falcon/dsp.c, src/falcon/dsp.h: + add a define for CPU/DSP ratio + [e4e5fa7e003e] + + * src/falcon/dsp.c: + fix: changed DSP cycles tuning to be compatible with Nicolas's last + patch + [8ea0648ccf91] + +2010-02-24 Eero Tamminen + + * doc/compatibility.html, doc/emutos.txt: + add: 20 years Atari STE megademo + [f7f27561eb16] + +2010-02-23 Nicolas Pomarede + + * src/includes/cycles.h, src/uae-cpu/newcpu.c: + When DSP is enabled, use CYCLES_COUNTER_CPU to get the total number + of cycles used by the CPU. We need to compute all cycles spent in + the CPU, including the time needed to process exceptions, before + calling DSP_Run (else the DSP won't run for the correct number of + cycles) + [3519b02affa0] + +2010-02-21 Eero Tamminen + + * doc/compatibility.html: + risk works ok + [4a0c21b49fb4] + + * doc/compatibility.html: + correct pouet.net id + [f0b688097d7a] + + * config-default.h: + add HAVE_MALLOC_H & HAVE_POSIX_MEMALIGN to config-default.h (for + Glibc) + [317b150f171c] + + * doc/compatibility.html: + add several Falcon games/demos + [4e793ee2901f] + + * doc/todo.txt: + remove configure.ac todo + [4aab39a4be09] + +2010-02-21 Thomas Huth + + * readme.txt: + Rewrote the instructions for compiling with CMake + [e6588e9ef7a1] + + * .hgignore, Makefile.cnf.in, acsite.m4, configure.ac: + Removed the autoconf files since nobody wants to maintain these + files anymore. For configuring the build process, you can now use + "cmake" instead. + [2d05fee42afb] + + * .hgtags: + Added tag before_removing_autoconf_files for changeset 50b9dfdcc014 + [b20eb20251fa] + +2010-02-21 Nicolas Pomarede + + * CMakeLists.txt: + For cmake, ensure readline detection is correctly linked with + libreadline + [50b9dfdcc014] [before_removing_autoconf_files] + +2010-02-21 Eero Tamminen + + * doc/compatibility.html: + add Team & Epi-lepsie + [db449c77e9b2] + +2010-02-20 Eero Tamminen + + * doc/compatibility.html: + add Aniplayer to compatibility list (and move AFM to sorted + position) + [1f0fb9eeb455] + +2010-02-20 Laurent Sallafranque + + * src/falcon/crossbar.c: + finished to optimize crossbar code. Sound problem is clearly in + crossbar <---> DSP transfers. I'll check this. + [b277f94e5575] + +2010-02-19 Laurent Sallafranque + + * src/falcon/crossbar.c: + add: sound volume for both adc and dac. Remove double variables for + readDacBuffer. Sound seems better under Whip, but not under AFM + [efcc3ab3f9e8] + + * src/falcon/crossbar.c: + add: first preview of sound volume control. + [8cd6bc72d014] + +2010-02-18 Eero Tamminen + + * src/falcon/crossbar.c: + silence crossbar.c compiler warning (it doesn't know + codecInputSource max value is 3) + [aad85ef530cd] + +2010-02-18 Laurent Sallafranque + + * src/falcon/crossbar.c: + remove some double variable. Rewrite of 25 Mhz and 32 Mhz + frequencies. Optimize microphone code. Code cleaning + [65d8be280806] + +2010-02-17 Eero Tamminen + + * src/debug/debugInfo.c, src/debug/debugInfo.h, + src/debug/debug_priv.h, src/debug/debugcpu.c, src/debug/debugdsp.c, + src/debug/debugui.c: + reset disasm address to PC whenever re-entering the debugger. + [6e3ff0505fb7] + +2010-02-16 Eero Tamminen + + * doc/release-notes.txt, doc/todo.txt: + docs: symbols are shown in DSP disassembly too + [c789f016bd92] + + * src/debug/debugdsp.c, src/falcon/dsp.c, src/falcon/dsp.h: + handle DSP memdump similarly to disasm. + [2897107093d7] + + * src/debug/debugdsp.c: + support symbols in DSP "disasm" command output + [8f436371bfc1] + + * src/debug/symbols.c: + fix comment + [b03453b54c3d] + + * src/debug/debugdsp.c: + use stderr for remaining debugdsp.c error messages + [5de119d8f389] + + * doc/manual.html, doc/release-notes.txt: + trivial doc improvement + [92a43491524a] + + * doc/todo.txt: + breaking out of loops can now be done with "b pc > pc :once" + [78e776b112a4] + + * src/debug/breakcond.c, src/debug/debugcpu.c: + fix typos in help texts + [2aef8d1f60ae] + + * doc/manual.html: + major update to manual debugger section to get it upto date + [197e2d50ad48] + +2010-02-15 Eero Tamminen + + * tests/TODO: + remove done tests TODO + [a339ba45c935] + + * doc/release-notes.txt: + update release notes for debugger stuff + [5072b59b54eb] + + * src/debug/breakcond.c: + fix issue and improve output revealed by updated breakcond tests + [b1c44c46f849] + + * tests/test-breakcond.c: + add tests for new conditional breakcond features + [1855b5e80666] + + * src/debug/breakcond.c, src/debug/breakcond.h, tests/test- + breakcond.c: + make breakcond tests to use the public BreakCond_Command() API, so + that extra functions don't need to be exported just for tests. + [5a6462ef9c63] + + * tests/Makefile, tests/test-breakcond.c, tests/test-dummies.c, tests + /test-evaluate.c: + update test code, split common "dummy" stuff to test-dummies.c + [91954e86415c] + + * src/debug/breakcond.c, src/debug/debugui.c, src/debug/evaluate.c, + src/debug/evaluate.h: + interpret in "evaluate" CPU or DSP regs&symbols where appropriate, + not both CPU and DSP. + [954f37932500] + +2010-02-14 Nicolas Pomarede + + * src/cycles.c, src/includes/cycles.h, src/memorySnapShot.c: + Add nCyclesCounter[] to the memory snapshot. Without this, some + snapshots would cause an error in Cycles_GetCounter() when restored + and some possible crashes. + [ffb8bd5c49c3] + +2010-02-14 Eero Tamminen + + * src/debug/breakcond.c, src/debug/debugcpu.c, src/debug/debugdsp.c, + src/debug/debugui.c, src/debug/symbols.c, src/debug/symbols.h: + update and improve several debugger help texts. + [986bac9e218a] + + * doc/todo.txt, src/debug/breakcond.c, src/debug/breakcond.h, + src/debug/debugcpu.c, src/debug/debugdsp.c: + Make address & dspaddress commands wrappers for conditional + breakpoints. This way there's only one list of breakpoints for user + to manage, options for them are the same and code doesn't need to be + duplicated. + [4178c971bf22] + + * src/includes/str.h, src/str.c: + Str_EndsWith() not needed anymore with breakcond.c update, remove. + [a21a0f598310] + + * src/debug/breakcond.c: + conditional breakpoint options separated with ':', support for skip + option (breakpoint features are now on par with address + breakpoints). + [5b2bb41f6142] + + * src/debug/debugcpu.c: + simplify "disasm" command implementation (remove also breakpoint + showing, that won't be possible once address breakpoints are + implemented with conditional ones.) + [8f4fedbd8dff] + + * doc/release-notes.txt, doc/todo.txt: + update todo & release-notes to latest debugger improvements + [b859f30276af] + + * src/debug/debugui.c: + remove "value" command and more number base setting to "setopt" + command + [139c5bae1af8] + + * src/debug/debugui.c: + TAB-completion for "evaluate" command and quoted expressions. Update + help. + [8e18f70b46c5] + + * src/debug/debugui.c, src/debug/log.c, src/debug/log.h: + disable normal GUI alerts while on debugger/console + [7d2d89129fd3] + +2010-02-13 Eero Tamminen + + * src/debug/debugui.c: + TAB-complete last "evaluate" result for $ + [d86ea4664eb6] + + * src/debug/breakcond.c, src/debug/debugui.c: + allow quoted expression evaluation for everything in debugger + [6f7e04f791c0] + + * src/debug/evaluate.c: + support register and symbol values in evaluate command + [123f11b2f33c] + + * src/falcon/dsp.c: + don't return DSP register addresses unless DSP is running + [c4075863947d] + +2010-02-13 Laurent Sallafranque + + * doc/compatibility.html, src/ioMemTabFalcon.c: + compatibility list update + [de9af48c14d1] + +2010-02-12 Eero Tamminen + + * src/debug/debugInfo.c: + add register address disasm/memdump support to lock command + [2072bf3b4667] + +2010-02-12 Laurent Sallafranque + + * src/falcon/crossbar.c, src/falcon/crossbar.h, src/ioMemTabFalcon.c: + crossbar code cleaning + [53bbc968eee2] + +2010-02-11 Laurent Sallafranque + + * src/falcon/crossbar.c: + add: ADC->DAC direct connexion. Whip and Audio Fun Machine are + playing sound now. $FF8937 and $FF8938 are correctly taken into + account. + [eb80a1b35d16] + +2010-02-11 Eero Tamminen + + * doc/release-notes.txt, src/debug/debugInfo.c, src/debug/debugInfo.h, + src/debug/debugui.c: + make "lock" separate command instead of "info" option, add + dspmemdump handling for the lock command (additional parameter + require more extensive changes, but will be useful also for register + locking) + [ae3fc0f4ac6f] + +2010-02-10 Eero Tamminen + + * src/debug/breakcond.c: + evaluate quoted expressions in conditional breakpoints + [eec2aad8e73e] + + * src/debug/breakcond.c: + change current value only for non-tracked values + [41c1b3e73fed] + +2010-02-10 Laurent Sallafranque + + * src/falcon/crossbar.c: + add: crossbar ASCIIart schematic. + [f262e337c7b7] + +2010-02-09 Eero Tamminen + + * src/debug/debugcpu.c, src/debug/debugdsp.c, src/debug/debugui.c: + add subheadings to debugger help + [890976a0458b] + + * src/debug/debugInfo.c, src/debug/debugdsp.c, src/debug/debugdsp.h: + support DSP disasm/regs for debugger info/lock command, fix info + help + [a938235faf79] + + * doc/release-notes.txt, src/debug/debugInfo.c, src/debug/debugInfo.h, + src/debug/debugcpu.c, src/debug/debugcpu.h, src/debug/debugui.c: + possibility to "lock" info command to be output when entering + debugger. info commands for disasm, memdump & registers. + [91184cbe5fbf] + +2010-02-08 Eero Tamminen + + * src/debug/debugcpu.c: + simplify DebugCpu_MemDump() code + [4519881bce20] + + * doc/release-notes.txt, src/debug/debugui.c: + add statesave & stateload debugger commands, update release notes + [709c4eddbf60] + + * src/debug/breakcond.c: + if comparing identical expressions, evaluate right side when + condition entered (change tracking is done only for the inequality + condition) + [d0d88fc2990b] + +2010-02-07 Nicolas Pomarede + + * doc/compatibility.html, doc/release-notes.txt: + Update docs regarding video counter emulation on STE + [074e7692eb0a] + + * src/video.c: + Better support for modifying $ff8205/07/09 while display is on (fix + EPSS demo by Unit 17) + [5b413e37d514] + +2010-02-06 Nicolas Pomarede + + * src/video.c: + In Video_CalculateAddress, take STE's LineWidth into account On STE, + the content of $ff820f is added to the current video address as soon + as display enters the right border (cycle 376 for a normal line). We + should not wait for Video_EndHBL (cycle 512) to add $ff820f when + reading $ff8205/07/09 (fix the game Utopos) + [0b5d2ef08b6f] + +2010-02-06 Eero Tamminen + + * tests/TODO: + add tests TODO + [7f06f219864c] + + * tests/test-symbols.c: + update to latest symbols changes + [ab29e3b5fa9f] + + * src/debug/debugui.c: + add symbol name completion and symbol address showing to value + command + [dc3ca2bf4478] + + * src/debug/debugui.c: + add conditional breakpoint symbol completion + update address + breakpoint completion (address breakpoints should match only code + addresses) + [e3ea0894fc9f] + + * src/debug/breakcond.c, src/debug/breakcond.h: + add symbols support to conditional breakpoints + [2aac4498dc3d] + + * src/debug/debugcpu.c, src/debug/debugdsp.c, src/debug/symbols.c, + src/debug/symbols.h: + finish supporting separate text/code and data/bss symbols matching + [b4a6f6e27269] + +2010-02-05 Eero Tamminen + + * src/debug/breakcond.c: + better conditional break message, have "once" bp removal code in one + place + [13ced9619b75] + + * src/debug/symbols.c, src/debug/symbols.h: + show symbol type on listings and make symbols type a bitmask (in + preparation for separate TEXT and DATA symbol access) + [6acfa9079697] + + * src/debug/breakcond.c, src/debug/breakcond.h: + test needs to give breakcond.c ro strings, make parse function args + const + [9038726e3c34] + + * tests/test-breakcond.c: + update test-breakcond.c + [4ee566abf67f] + +2010-02-03 Eero Tamminen + + * src/debug/breakcond.c, src/debug/breakcond.h, src/debug/debugcpu.c, + src/debug/debugdsp.c: + move breakpoint command description to breakcond.c + [e38d8fda585c] + +2010-02-02 Laurent Sallafranque + + * src/debug/debugInfo.c: + add: scroll register added to VIDEL info (debug mode) + [ffbd105e8c15] + +2010-02-02 Eero Tamminen + + * src/file.c: + when splitting path, remove separator from end of path (Windows-only + issue, patch courtesy of Konador, Cyprian) + [ed206c749ea7] + + * src/gui-sdl/dlgFileSelect.c: + use paths.c utility function for getting home dir (has better + fallbacks) + [5d2ee6cfc13d] + + * src/paths.c: + support Windows homedir path variable + [bd60753ae67d] + + * src/createBlankImage.c: + better error message when floppy image creation fails + [bcbeac5da8e3] + +2010-02-01 Eero Tamminen + + * src/debug/breakcond.c: + correct printf message + [4b6524794b14] + +2010-01-31 Eero Tamminen + + * doc/release-notes.txt, src/debug/breakcond.c, src/debug/breakcond.h, + src/debug/debugcpu.c, src/debug/debugdsp.c: + memory change tracking suport, once & trace keywords, hit counting + to conditional breakpoints + [1a659fed336b] + + * src/includes/str.h, src/str.c: + Add Str_EndsWith() function for new debugger feature. + [fb419c815edd] + +2010-01-31 Laurent Sallafranque + + * src/falcon/crossbar.c: + add: correct crossbar intial values (after boot). This let me remove + the temporary "bad hack" I wrote in function + "Crossbar_FrameCountLow_WriteByte" to let "Eko system" demo work. It + may fix some other programs, I haven't tested deeply. + + fix: crossbar sound buffer size to reduce the delay when sound is + playing. + [48d329bc3579] + +2010-01-29 Eero Tamminen + + * doc/manual.html: + HTML validator and readability fixes ("−" -> "-", """ -> + '"') + [dc14ad141f96] + + * doc/compatibility.html: + fix HTML-validator issues, update several Falcon compat items (and + change "dummy/emu" -> "dummy emu" in tables so that it can wrap) + [0dc511796685] + +2010-01-29 Laurent Sallafranque + + * doc/compatibility.html: + update compatibility list + [edd98f6f757f] + +2010-01-26 Thomas Huth + + * CMakeLists.txt, cmake/config-cmake.h: + Check for posix_memalign() and memalign() functions + [dca761fc16ac] + + * Info-Hatari.plist, src/CMakeLists.txt, src/gui-osx/Info- + Hatari.plist: + Moved Info-Hatari.plist file to src/gui-osx/ folder since this file + is for Mac OS X only. + [2709cf75ed8e] + + * Hatari.xcodeproj/project.pbxproj: + Removed old Xcode project. Use the new CMake build system instead to + generate project files for Xcode. + [2e1df3a8df6c] + + * .hgtags: + Added tag before_removing_xcode_project for changeset 5f5002de02bb + [b82d2b234f62] + +2010-01-26 Eero Tamminen + + * src/gemdos.c: + replace magic GEMDOS values with appropriate defines + [5f5002de02bb] [before_removing_xcode_project] + + * src/gemdos.c: + set FileHandles[].szActualName in Fcreate() too when file open + succeeds. (and in Fopen() set it only _if_ file open succeeds) + [ad0b98dad6f0] + + * src/gemdos.c: + gemdos improvements: check dest size, use file.c util function + [f387bce13a46] + + * src/gemdos.c: + fix case: Fcreate() given dir\filename of which neither exists. (the + new code created file with shortened name of "dir\filename") + [35b58807ba76] + + * doc/release-notes.txt, src/gemdos.c: + Fixed and much improved host file name support for GEMDOS drive + emulation: + - convert host filename chars that are invalid in TOS to valid ones + ('@') (main thing is that extra dots don't break TOS fileselector + etc). + - cut file basename and extension separately to 8+3 size (gives more + readable TOS filenames). + - support long host directory names in addition to filenames + (earlier they might be visible in TOS, but files in them weren't). + - first try matching exact (non-casesensitive) name first, only if + that fails, use a pattern for long names (fixes renaming name.prg + to name.pr). + - get rid of glob() and use opendir()/readdir()/closedir() and TOS + pattern matching instead (unlike TOS, glob() interprets []as + ranges). + [4a58031dd34c] + + * doc/manual.html: + minor manual improvements (mainly language) + [707323a092dd] + + * doc/compatibility.html: + tron2001 is from ICE + [df03e216c986] + + * src/ide.c: + ide.c: assert on alloc errors. free everything on uninit. I used + asserts as the earlier code was incorrect: if + (!opaque_ide_if || !hd_table[0] || !hd_table[1]) { + perror("Ide_Init"); (errno is undefined after a succesful library + call i.e. check + perror() would need to be separately for each + malloc.) + [2603bc3ea79f] + + * src/debug/debugcpu.c: + show symbols in disasm trace when: nCpuActiveBPs || nCpuActiveCBs || + nCpuSteps + [11500183bf54] + + * doc/release-notes.txt, src/createBlankImage.c, src/gui- + sdl/dlgNewDisk.c: + add support for creating blank HD & ED floppy images + [7cf3e651c547] + + * src/gui-sdl/dlgMain.c: + fix Hatari GUI reset button active area width + [fcb2e17e9175] + +2010-01-25 Laurent Sallafranque + + * doc/compatibility.html: + update compatibility list : Wotanoid is now working + [f16c13621f0d] + + * src/gemdos.c, src/ioMemTabFalcon.c: + fix: gemdos Fread accept size > $7fffffff with Tos > 4.0. fix: + iomemTabFalcon address $FF9206 Wotanoid game is now working + [6bfd3046f74d] + +2010-01-25 Eero Tamminen + + * doc/todo.txt: + add myself todo about configure.ac update or removal before next + release. + [46d58a22104b] + +2010-01-24 Thomas Huth + + * CMakeLists.txt, cmake/DistClean.cmake: + Added 'distclean' target + [312e81e718bb] + +2010-01-24 Eero Tamminen + + * doc/release-notes.txt, doc/todo.txt: + Note new debugger features, list possible debugger TODOs (Monst + features) + [5ea6ffb477d1] + + * src/debug/debugcpu.c: + Counted CPU breakpoint support. Show symbols & breakpoints with CPU + disasm trace (only if there are CPU breakpoints) + [051e73aca8d8] + + * doc/todo.txt, src/floppy.c, src/gui-sdl/dlgFloppy.c: + Give error dialog when user tries to insert same floppy image to + multiple drives. GUI code changes required for handling error from + name setting correctly (easiest was just removing the unused return + value). + [057572bb031f] + + * src/ide.c: + IDE sector read/write error handling + [2e629f22c22b] + +2010-01-23 Thomas Huth + + * src/CMakeLists.txt: + Added libraries SDLmain and ws2_32 for compiling on Windows + [eb729b557f53] + + * configure: + Added '--disable-osx-bundle' parameter + [6e085d951d66] + + * src/CMakeLists.txt, src/gui-osx/CMakeLists.txt: + OS X GUI classes must not be built as library, but linked directly + into the executable. Some classes are referenced only from the .nib + file and thus discarded when linked into a library first. + [47e1795527bf] + + * CMakeLists.txt, src/CMakeLists.txt: + Made the OS X bundling optional + [2c585943af19] + + * CMakeLists.txt: + Only use libreadline if the completion functions are available. This + fixes the problems with older versions of editline on Mac OS X + [614a54d1cd84] + + * src/gui-osx/CMakeLists.txt: + Make sure that CMake does not use C++ compiler for Objective-C + files. + [ed7f5f178540] + + * CMakeLists.txt, src/CMakeLists.txt, src/gui-osx/CMakeLists.txt, src + /gui-osx/SDLMain.m: + The CMake build system can now also create a working Xcode project. + [857657c8fd05] + + * src/gui-osx/Shared.h, src/gui-osx/Shared.m: + Silenced some compiler warnings + [024f9c788433] + + * src/gui-osx/PrefsController.m: + Made OS X GUI compilable again + [5fa35ca71eff] + + * src/debug/symbols.c: + Fixed compiler warning about unitialized variable + [21cfc83f14ab] + + * Hatari.xcodeproj/project.pbxproj: + Updated old Xcode project with new files. + [42dd9ca0d40c] + +2010-01-22 Thomas Huth + + * src/uae-cpu/CMakeLists.txt: + Do not assume that executable is in current dir, use + get_target_property instead. This helps a little bit with the build + process on Xcode... + [ebc4d432fc2e] + +2010-01-21 Eero Tamminen + + * src/xbios.c: + fix previous xbios.c ARRAYSIZE commit + [eefe4b5c73a5] + +2010-01-20 Eero Tamminen + + * src/gemdos.c: + Make GEMDOS multipartition subdir name check stricter. isalpha() is + locale aware, so check for A-Z explicitly. + [5cf051595b42] + + * src/floppy.c, src/gemdos.c, src/includes/gemdos.h, src/stMemory.c: + name driver number variable as such instead of calling it hd letter. + [d438fe62b105] + + * src/gemdos.c: + 2 missing gemdos call names to trace table + [1de07126a354] + + * src/includes/rs232.h, src/rs232.c, src/xbios.c: + use SDL types for rs232 stuff too. + [754d0d4336c5] + + * src/rs232.c: + both set functions should take FILE*, configured device file open + should give warning, change direct printf warnings to use log + functions so that they they can be controlled. + [3716234546c4] + + * src/change.c, src/falcon/dsp.c, src/hdc.c, src/includes/hdc.h, + src/main.c: + move HDC and DSP config values checking from main to respective Init + functions like with the rest of the Init functions. + [ae2c8925403d] + + * src/debug/debugInfo.c: + validate sysbase against TosAddress too + [6f0550c3e7c9] + +2010-01-20 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + clean: remove debug fprintf + [d000a5f56edf] + + * src/falcon/dsp_cpu.c: + fix: 2nd vectored instruction test for a JSR must be done only when + we're on the second fetched instruction. (if the first instruction + was a jmp, no need to test if the second one is a JSR) + [71fdd94ba633] + + * doc/todo.txt, src/falcon/dsp_core.c, src/falcon/dsp_core.h, + src/falcon/dsp_cpu.c: + fix: rewrite of DSP interrupts code. Interrupts are now "fetched" + correctly. fix: stack interrupt is now raised with movec instruction + too. + [13c5e580ea46] + +2010-01-20 Eero Tamminen + + * doc/manual.html, doc/release-notes.txt: + Major updates to manual hard disk sections. Update manual and + release notes to latest Hatari changes. + [9dcfe732e857] + +2010-01-18 Thomas Huth + + * tests/buserror/buserr_b.prg, tests/buserror/buserr_b.s, + tests/buserror/buserr_w.prg, tests/buserror/buserr_w.s, + tests/buserror/readme.txt, tests/buserror/results/fal_c_b.txt, + tests/buserror/results/fal_c_w.txt, + tests/buserror/results/fal_n_b.txt, + tests/buserror/results/fal_n_w.txt, tests/buserror/results/st_b.txt, + tests/buserror/results/st_w.txt, tests/buserror/results/ste_b.txt, + tests/buserror/results/ste_w.txt, tests/buserror/results/tt_b.txt, + tests/buserror/results/tt_w.txt: + Added programs for testing the bus errors in the IO memory + [b50b0dac2306] + +2010-01-17 Eero Tamminen + + * doc/hatari.1, doc/manual.html: + doc: add info on debugger symbols command; --ide to --ide-master & + --ide-slave + [e60bf40e5ac6] + + * src/debug/debugcpu.c: + show symbol names in the CPU disassembly + [db4504b80eb3] + + * src/debug/debugdsp.c: + list symbols for dsp breakpoints, not CPU + [51d1c5002cd5] + + * src/gui-sdl/dlgAbout.c, src/gui-sdl/dlgAlert.c, src/gui- + sdl/dlgDevice.c, src/gui-sdl/dlgFileSelect.c, src/gui- + sdl/dlgJoystick.c, src/gui-sdl/dlgNewDisk.c, src/gui-sdl/dlgRom.c, + src/gui-sdl/dlgSound.c, src/gui-sdl/dlgSystem.c, src/gui- + sdl/sdlgui.c: + convert rest of SDL-GUI function comments to format needed by Hatari + API documentation + [d1bef2c23342] + + * src/debug/debugcpu.c, src/debug/debugcpu.h, src/debug/debugdsp.c, + src/debug/debugui.c, src/debug/symbols.c, src/debug/symbols.h: + improve & generalize symbols/address support to work with DSP too: + - move CPU address & symbol matching functionality to symbols.c, + generalize it and add minimal wrappers also for DSP + - this allowed hiding implementation details to symbols.c and keep + changes to already existing DSP and CPU debug code minimal + - add support for loading DSP symbols and TAB-completing them + - add symbol name showing to breaked, listed and deleted breakpoints, + both for DSP and CPU + [044bd9c612bb] + +2010-01-17 Thomas Huth + + * CMakeLists.txt: + check_function_exists is optional, so let's include the + corresponding module. + [d85726352bbc] + + * CMakeLists.txt, python-ui/CMakeLists.txt: + Install python UI with CMake, too + [9c90712b2ac3] + + * CMakeLists.txt: + Include module CheckIncludeFiles to make sure that + check_include_files is always available + [486a7fe708c3] + +2010-01-16 Thomas Huth + + * cmake/FindReadline.cmake: + Added missing INCLUDE(FindPackageHandleStandardArgs) + [61e66376af6e] + + * src/debug/CMakeLists.txt: + Added new file symbols.c to CMakeLists + [6e0658f20a21] + + * CMakeLists.txt, cmake/FindPortAudio.cmake, cmake/FindReadline.cmake, + configure, src/CMakeLists.txt, src/debug/CMakeLists.txt, + src/falcon/CMakeLists.txt: + CMake build system should now also work if one of the optional + libraries has not been found. + [28f5378b45b7] + +2010-01-16 Eero Tamminen + + * src/debug/debugInfo.c: + allow leaving basepage address out, default then to current process + address + [9b128d4dbf32] + + * src/debug/debugInfo.c: + add "info" subcommands "osheader" and "basepage" + arg handling for + last one + [df1f3440eae7] + +2010-01-15 Eero Tamminen + + * doc/compatibility.html: + compat list: Aura's illusion and Tron2001 work. + [1c07e5fc2b35] + +2010-01-14 Eero Tamminen + + * src/debug/debugInfo.c, src/debug/debugInfo.h, src/debug/debugui.c: + bind debug info stuff to debugger. + [5f17219fb4c0] + +2010-01-13 Laurent Sallafranque + + * src/ioMemTabFalcon.c: + fix: added address $FF800A as voidRead and voidWrite. Illusion Demo + (Aura) is now working. + [a512d1ef2d7e] + +2010-01-12 Laurent Sallafranque + + * src/debug/debugInfo.c, src/debug/debugInfo.h: + add: new debugInfo function (I forgot it in my upload) + [7fb18e8814e5] + + * src/debug/CMakeLists.txt, src/debug/Makefile, src/falcon/crossbar.c, + src/falcon/crossbar.h, src/falcon/videl.c, src/falcon/videl.h: + add: debugInfo to get informations of the atari components. (First + components added : Videl and Crossbar) + [eb6065eb8a68] + +2010-01-12 Eero Tamminen + + * src/debug/Makefile, src/debug/debugcpu.c, src/debug/debugcpu.h, + src/debug/debugui.c, src/debug/symbols.c, src/debug/symbols.h, + tests/Makefile, tests/etos512.sym, tests/test-symbols.c, tools/ahcc- + symbols-convert.sh: + Hatari debugger symbol/address handling; parsing, sorting, matching, + TAB completion support, test code/data etc. Initial version. + [307730a3cf2d] + + * src/file.c: + remove all slashes from filename end, not just one + [1a54a53f7fc6] + + * src/gemdos.c: + fix: gemdos call tracing crash when program does MiNT gemdos calls + on TOS + [d6b5961b20f6] + +2010-01-11 Laurent Sallafranque + + * src/falcon/crossbar.c, src/falcon/crossbar.h, src/falcon/videl.c, + src/falcon/videl.h: + add: info functions for Videl and Crossbar components (to be used in + debugger mode) + [42461614fd89] + +2010-01-10 Nicolas Pomarede + + * src/video.c: + In Video_CalculateAddress, take HWScrollPrefetch into account When + $ff8265 is used to scroll, shifter starts reading memory 16 pixels + earlier. (fix EPSS demo by Unit 17) + [cd8bc4c67033] + +2010-01-10 Eero Tamminen + + * src/str.c: + improve str.c comment + [f9cb14192c0c] + + * src/debug/evaluate.h: + correct comment/define name + [e85c769b7516] + + * src/debug/debugui.c: + debugger help: handle command short version missing or empty. + [1ca8b28fe054] + + * src/debug/debugcpu.c, src/debug/debugdsp.c: + Show hex values as hex (%x -> 0x%x) + [a4c67b95fb2f] + + * src/gemdos.c: + fix fsfirst_match() end of string matching with '*' (it should match + also zero chars). + [84b8989f28fb] + + * src/gemdos.c: + simplify fsfirst_dirmask() + [f274eb600602] + +2010-01-10 Thomas Huth + + * .hgignore, configure: + Added configure wrapper script for the CMake build system + [24a1ac46674e] + +2010-01-10 Nicolas Pomarede + + * src/video.c: + In Video_CalculateAddress, take bSteBorderFlag into account (+16 + pixels in left border on STE) (fix Intro (spec512 pictures) and + Direct Color Zoomer in Atari STe 20 year megademo) + [c269e5c8852d] + +2010-01-09 Thomas Huth + + * CMakeLists.txt, cmake/config-cmake.h, src/debug/CMakeLists.txt, + src/falcon/CMakeLists.txt: + Added conditional build features to CMake build system + [b212d9045d40] + + * src/gui-sdl/CMakeLists.txt, src/uae-cpu/CMakeLists.txt: + Fine tuning of compiler warning flags + [98eb5d35845d] + + * cmake/FindReadline.cmake: + Improved cmake check for libreadline + [84b57b79fcbc] + + * doc/authors.txt: + Nicolas is now admin, too + [22cd2947a1a2] + +2010-01-09 Eero Tamminen + + * tests/Makefile: + rm built tests on clean + [b61880a70217] + +2010-01-07 Eero Tamminen + + * src/gemdos.c: + add appropriate consts to string pointers, rename match() -> + fsfirst_match() + [cfc0cbcbbf33] + + * src/falcon/dsp_disasm.c: + workaround compiler warning (sprintf("") -> *str=0) + [ca56d09f84cd] + +2010-01-06 Thomas Huth + + * CMakeLists.txt: + Set default build type to 'Release' and add more CFLAGS + [fb341d4e9359] + + * src/uae-cpu/gencpu.c: + Changed 'char *' to 'const char *' to avoid compiler warnings when + this file is being compiled with the -Wall flag. + [ca0ae9af2791] + +2010-01-05 Laurent Sallafranque + + * src/falcon/hostscreen.c: + fix: mouse pointer position is now correctly initialized. Thanks to + thomas for the fix. + [3f7bb012e3a0] + +2010-01-04 Thomas Huth + + * CMakeLists.txt, cmake/FindPortAudio.cmake, cmake/config-cmake.h, + src/CMakeLists.txt, src/falcon/microphone.c: + Added PortAudio test to cmake build system + [a6f92ea876f6] + +2010-01-01 Thomas Huth + + * CMakeLists.txt, doc/CMakeLists.txt, src/CMakeLists.txt: + Added cmake rules for installing + [daab4fb7864d] + +2009-12-30 Thomas Huth + + * CMakeLists.txt, cmake/FindReadline.cmake, cmake/config-cmake.h, + config-cmake.h, src/CMakeLists.txt: + Added proper checks for optional libraries, headers and functions to + the cmake build system. + [7642453a7eda] + + * src/uae-cpu/CMakeLists.txt: + Fixed cmake rules for cross-compiling. + [9033b969eca5] + + * CMakeLists.txt, config-cmake.h, src/CMakeLists.txt: + Added config.h for cmake build. + [685283b4f563] + + * src/CMakeLists.txt: + Forgot to rename int.c to cycInt.c in CMakeList.txt + [a90b3bb0ddb8] + + * src/falcon/dsp_cpu.c: + Disable DSP disassembling by default + [a6fc6d82fb80] + + * src/gemdos.c: + Print real file handles instead of negative numbers + [8160a1f32356] + +2009-12-29 Laurent Sallafranque + + * doc/authors.txt, doc/release-notes.txt, doc/todo.txt: + update TODO and release notes + [fe9c1e8bd2c8] + + * src/falcon/dsp.c, src/falcon/dsp_cpu.c, src/falcon/dsp_disasm.c, + src/falcon/dsp_disasm.h: + add: display DSP cycles for each instruction in debug mode + [8fffff71d733] + +2009-12-29 Eero Tamminen + + * src/gemdos.c: + Fix gemdos path error check that prevented TOS from copying new file + to GEMDOS HDD. Update gemdos comments. + [db7e0c784268] + + * doc/emutos.txt: + add realtime to emutos compatible ste demos + [fe054432c6e9] + +2009-12-22 Thomas Huth + + * Makefile: + Automatically use Makefile-MinGW.cnf when compiling with MinGW. + Thanks to Cyprian Konador for the patch. + [df62ff0dde52] + + * src/file.c, src/gui-win/opencon.c: + Fix for compiling with MinGW. + [12e67c2d6de4] + +2009-12-21 Thomas Huth + + * src/gemdos.c: + Ignore all hidden files when scanning for GEMDOS partition mode + [14bd1149a232] + + * src/blitter.c, src/cycInt.c, src/dmaSnd.c, src/falcon/crossbar.c, + src/fdc.c, src/ikbd.c, src/includes/cycInt.h, src/memorySnapShot.c, + src/mfp.c, src/midi.c, src/reset.c, src/video.c: + Renamed 'Int' prefix to 'CycInt' to match the new name of the file. + [d0c337dbee13] + +2009-12-21 Laurent Sallafranque + + * src/falcon/crossbar.c, src/falcon/crossbar.h, + src/falcon/microphone.c: + fix: detect when there's no input device for microphone emulation. + (SIGSEGV error removed in this case). + [b47570526969] + +2009-12-20 Thomas Huth + + * src/uae-cpu/fpp-unknown.h: + Fixed compiler warning from GCC 4.4 + [fc8dfad533d6] + + * src/ide.c: + Do not try to open an IDE slave image when only a master image is + configured. Thanks to Uwe Seimet for the patch. + [2fd881b39956] + + * src/file.c, src/includes/file.h: + Replaced ftell with ftello for large file support + [aea86db254d6] + +2009-12-19 Thomas Huth + + * src/hdc.c: + Fixed print-out of LBA (should be block address instead of byte + address). Thanks to Uwe Seimet for the hint. + [6f35d71d120b] + + * src/video.c: + Fixed compiler warning + [1ebf3f73783e] + + * doc/manual.html: + Added note about size of hard disk images. + [f8ab6e212eb6] + + * src/file.c, src/includes/file.h: + Changed return type of File_Length to long for big files on 64-bit + systems. Thanks to Uwe Seimet for the hint. + [9dec5f799366] + +2009-12-19 Laurent Sallafranque + + * src/falcon/dsp_disasm.c: + code beautification + preparation for dsp cycle instruction display + [3c29e583f7d1] + + * doc/release-notes.txt, doc/todo.txt: + todo and release-notes update + [65209a078628] + + * src/falcon/crossbar.c, src/falcon/crossbar.h, + src/falcon/microphone.c, src/ioMemTabFalcon.c: + fix: compiler warnings, code beautification, added variables for + gain ans attenuation control. + [b51ed0dfa2a1] + +2009-12-17 Thomas Huth + + * src/cycInt.c, src/gemdos.c: + Fixed compiler warnings + [35ba7999853b] + +2009-12-14 Laurent Sallafranque + + * src/falcon/crossbar.c, src/falcon/crossbar.h, + src/falcon/microphone.c: + fix: remove microphone warning during compilation + [e174abde168a] + +2009-12-13 Laurent Sallafranque + + * src/falcon/dsp_core.h, src/falcon/dsp_cpu.c: + fix: SR IPL test was wrong. SR must mask only lower interrupt level, + not same level code cleaning + [99916d9c84dc] + +2009-12-13 Eero Tamminen + + * doc/compatibility.html: + really set Moai as working + [942100792db9] + +2009-12-13 Nicolas Pomarede + + * src/video.c: + Fix small error on STE when using hardware scrolling in overscan + (introduced in rev 2334) When using overscan, the whole screen is + shifted 4 pixels to the left as the display starts earlier. When + combined with STE's $ff8264 we must first scroll the pixels in the + displayed area, then we shift the whole line by STF_PixelScrol + pixels (doing it the other way around introduced 4 color-0 pixels in + the right border). The STE will scroll the pixels in the displayed + area ; the hi/lo switch will shift the whole displayed area. + [0eac85b8f5f8] + + * src/video.c: + Improve STE 224 bytes overscan lines + - correctly set leftmost 16 pixels to color 0 (taking into account how + many bytes are displayed by Hatari in left border) + - remove small glitches when combined with hscroll ($ff8264) + [32bfc6f4f89b] + +2009-12-12 Eero Tamminen + + * src/change.c: + do statusbar update always after config changes. (CPU speed etc + settings can be changed without emulation reset) + [7fffd28bbd28] + + * doc/compatibility.html: + chosneck supplement demo works almost completely + [2b12fc156793] + +2009-12-11 Eero Tamminen + + * src/statusbar.c: + Add CPU type+speed and FastForward mode indicator to statusbar. + Based on patch from Cyprian Konador, thanks! + [43dbf4ce5a11] + + * doc/compatibility.html: + add winrec & STEarth + links and software sites section. + [20888c89dc1a] + + * doc/emutos.txt: + stearth demo works with emutos + [f5145d9e2be8] + +2009-12-10 Laurent Sallafranque + + * src/falcon/crossbar.c: + fix: DMA interrupts must be LOG_TRACE, not LOG_Printf. Removed + PORTAUDIO #ifdefs. + [dc7b305dd39a] + + * src/falcon/crossbar.c, src/falcon/crossbar.h, + src/falcon/microphone.c, src/falcon/microphone.h: + add: microphone jack emulation is now running. Just listen to winrec + in cyborg mode. + [1ee9524711ab] + +2009-12-08 Eero Tamminen + + * src/gemdos.c: + Fdatime fix: unix month starts from 0, need to subtract 1 from from + GEMDOS month + [5a9f911240aa] + +2009-12-07 Nicolas Pomarede + + * src/includes/video.h, src/video.c: + Add support for STE 224 bytes overscan by switching hi/lo at cycle + 504/4 to remove left border This line doesn't need a stabiliser and + displays less pixels in the left border than the usual method (fix + More Or Less Zero and Cernit Trandafir by DHS, as well as Save The + Earth by Defence Force) + [c84981869f5c] + +2009-12-06 Thomas Huth + + * src/debug/Makefile, src/falcon/Makefile, src/gui-sdl/Makefile, src + /uae-cpu/Makefile: + Sub-makefiles dependency generation should depend on the main + Makefile + [0b1cfe22631f] + +2009-12-05 Thomas Huth + + * src/Makefile, src/cycInt.c, src/dmaSnd.c, src/falcon/crossbar.c, + src/ikbd.c, src/includes/cycInt.h, src/includes/int.h, + src/includes/m68000.h, src/int.c, src/m68000.c, + src/memorySnapShot.c, src/mfp.c, src/reset.c, src/sound.c, + src/spec512.c, src/uae-cpu/hatari-glue.c, src/uae-cpu/newcpu.c, + src/video.c: + Renamed int.c to cycInt.c + [ad9ae70a9d0c] + + * Makefile-default.cnf: + Do not print out annoying error messages when an optional library is + missing + [1d9f153e0f89] + +2009-12-05 Eero Tamminen + + * python-ui/README: + note on how to run non-installed version of Hatari with python-ui + [c5cb0154f684] + + * python-ui/TODO: + update python-ui TODO + [ee58791f8b29] + + * python-ui/hatari-console.py, python-ui/release-notes.txt: + support new hatari options in hatari-console + [11a03b1a8862] + + * src/gui-sdl/dlgHardDisk.c: + SDL GUI part for --mount-changes option + [22b9721283fd] + + * src/control.c, src/debug/debugui.c, src/debug/debugui.h: + restore support for remote/parallel Hatari debugging + [2c98fcb1e792] + +2009-12-04 Eero Tamminen + + * src/gemdos.c: + File stream should be flushed before setting its modifications time. + (Change also FileInfo function arg from file name to handle for + this.) + [25c544f10bf6] + + * doc/authors.txt, doc/release-notes.txt, doc/todo.txt: + add notes about IDE & GEMDOS emulation improvements + [9c8c4dc96472] + +2009-12-03 Nicolas Pomarede + + * src/includes/video.h, src/video.c: + Add support for a 3rd empty line method by switching res hi/lo at + cycle 464 This is another effect of the switch used in Enchanted + Lands, but without removing right border (fix Pax Plax Parralax in + Beyond by Kruz) + [4218a86c81d1] + +2009-12-03 Eero Tamminen + + * src/gemdos.c: + add GEMDOS file date/time setting, fix time&date word order for + getting them + [0d62b7c99357] + +2009-11-30 Thomas Huth + + * src/hdc.c: + Update DMA address after transfering bytes to the memory. + [dfba429e3328] + + * src/hdc.c, src/includes/hdc.h: + Added "Test Unit Ready" command. Thanks to Uwe Seimet for the patch. + [339bab06acf6] + +2009-11-29 Eero Tamminen + + * src/gemdos.c: + refactor+fix GEMDOS date & time getting: + - GemDOS_GetFileInformation() got both date & time fields wrong, + however, they're done right for DTA setting, so use that + functionality + - date & time are both set at the same time, so join getting them to a + new function and use DATETIME* as arg instead handling them + separately + - rename DATETIME struct fields to something more descriptive + [3201c6e4d2e6] + + * src/ide.c: + logging: printf doesn't support variables that are 64-bit both on 32 + & 64-bit host. + [6d21b81b7538] + + * src/gemdos.c: + add SIZE_WORD to Params in GemDOS_OpCode() so that all emulated + functions don't need to do it. + [049b5b20088e] + + * src/gemdos.c: + Fold 2 identical & trivial functions to GemDOS_Pexec() calling them + [c4a74da32799] + + * src/ide.c: + ide.c logging should identify it's from IDE (and be consistent) + [a18086790451] + + * src/gemdos.c: + fix remaining inconsistent logging in gemdos.c + [b48c321bfc81] + + * src/gemdos.c: + when tracing gemdos calls, tell all of their names, not just + emulated ones + [1030ec6179e1] + + * src/gemdos.c: + all GEMDOS log & trace messages should identify they're GEMDOS + messages (and to be consistent, change GemDOS in some messages to + GEMDOS too) + [0880411636e9] + + * src/gemdos.c: + check that DTA addresses are on valid ST-RAM area (Hatari's internal + memory can get corrupted if it's not) + [572cbacc6a43] + + * src/gemdos.c: + improvements to Fread/Fwrite: + - check that given address range is valid + - use more correct variable types (size is signed, negative value -> + 0) + - identify log/trace messages as coming from GEMDOS + [316002c87c69] + + * src/includes/ioMem.h, src/includes/stMemory.h: + use function documentation comment format for static inlines in + includes + [8cc463301644] + + * src/includes/stMemory.h: + add function to check that address range is on valid ST memory area + [f16daded3d12] + +2009-11-29 Thomas Huth + + * src/hdc.c, src/includes/hdc.h: + Reworked ACSI emulation so that it also works with HDDriver. + HDCCommand.byteCount must only be increased when accesssing a valid + target. + [415dfe04f359] + +2009-11-28 Thomas Huth + + * src/ide.c: + Fix for detection of ejected IDE slave. This patch ensures that an + ejected IDE slave is not present anymore after Hatari was reset. + Before, even after the slave was ejected it was still found as long + as a master was present. Thanks to Uwe Seimet for the patch. + [be4b554e8d0c] + +2009-11-28 Eero Tamminen + + * tests/Makefile, tests/test-breakcond.c: + use real register parsing functions instead of fake ones in test + code (to catch issues in register name->address mapping I just had + to fix) + [ed903bc85603] + + * src/gemdos.c: + Fix GEMDOS Fcreate(), read-only flag has effect only after file is + closed! When tracing GEMDOS, log the created and opened file FD and + mode. + [3b90c5617b6d] + + * src/debug/evaluate.c: + improve debugger value parsing error messages + [9d68bab35286] + + * src/debug/debugcpu.c, src/debug/debugdsp.c, src/falcon/dsp.c, + src/falcon/dsp.h: + allow white space in DSP & CPU register set command, unify error + messages + [9429bbf0f00c] + + * src/falcon/dsp.c: + fix debugger DSP register name parsing + [ecaaf781a86f] + +2009-11-25 Thomas Huth + + * src/change.c, src/configuration.c, src/floppy.c, src/gui- + sdl/dlgHardDisk.c, src/ide.c, src/includes/configuration.h, + src/options.c, src/tos.c: + Support for IDE slave drive. Thanks to Uwe Seimet for the patch! + [9d4856b3f8f8] + +2009-11-22 Eero Tamminen + + * src/gemdos.c: + GEMDOS Fseek() fixes: + - use Sint32 offset instead of long one, otherwise wrong value on + 64-bit + - offset is negative for mode 2 (from-end-of-file), so *add* it + [1fdc5061f139] + +2009-11-22 Laurent Sallafranque + + * src/falcon/crossbar.c: + fix: change in generate_sound, cast from (double) to (int) correctly + computed. Thanks to Nicolas for the hint. + [44dddd5cdff0] + + * src/falcon/dsp_core.c, src/falcon/dsp_cpu.c: + optim: Remove host_process after every DSP instruction. Transfer + host datas only when needed. Big thanks to Thomas for the hint. + [f68dbfc202f8] + +2009-11-22 Eero Tamminen + + * doc/compatibility.html: + Moai+Doomino work, HDDriver works with TOS4, better sound support + for ACE apps & GEMPlay (First thanks to Thomas' 030 setting, latter + to Laurent's DSP improvements) + [5bd9a528fc25] + + * src/floppy.c: + give note to user when floppy contents are discarded. + [c7a0bf177c02] + +2009-11-21 Laurent Sallafranque + + * src/falcon/dsp.c: + optim : dsp_run optimisation + [5a256b490cf5] + +2009-11-21 Thomas Huth + + * src/gui-sdl/dlgSystem.c: + Changed "68020 + FPU" to "68EC030 + FPU". + [ec373a648cfa] + + * src/uae-cpu/newcpu.c: + Fake 68030 by supporting the right mask in the CACR register. TOS + uses this register to detect the 68030 for setting up the _CPU + cookie. By supporting a right mask for this register, TOS now + detects a 68030 instead of 68020 CPU. + [1312264d9285] + +2009-11-19 Eero Tamminen + + * doc/compatibility.html: + Music works in many games & demos after Laurent's DSP<->DMA fixes. + Changed some Falcon issues from minor to major. + [0728b56a62be] + +2009-11-18 Laurent Sallafranque + + * src/falcon/crossbar.c, src/falcon/dsp.c, src/falcon/dsp.h, + src/falcon/dsp_core.c, src/falcon/dsp_core.h, src/falcon/dsp_cpu.c: + optimizations + code cleaning. + [a46201ee51b1] + +2009-11-17 Eero Tamminen + + * doc/compatibility.html: + Illusion was working already in 1.2 + [869cd3d546bf] + + * src/gemdos.c: + fix stupid mistakes from previous commit + [06de2e824554] + + * src/gemdos.c: + Fix/improve Fcreate()/Fopen() attribute and error handling: + - instead of creating Fcreate() files with fopen() write-only flag, + use that just to truncate and then re-open them (correctly) using + read-only flag. Also chmod() the file to be read-only + - check and report access errors as such to TOS, both in Fcreate() & + Fopen() + - in Fcreate() check path miss from errno too and add path miss + check & reporting also to Fopen() + - log access errors to user (so that one can correct them outside + Hatari) + - force Fopen() to read-only when "--mount-changes no" is used + (otherwise programs opening read-only files as RW fails although + program wouldn't be writing to them) + [8ade08d9021c] + +2009-11-16 Eero Tamminen + + * doc/compatibility.html: + add to compat list: zero-5 STE gamedemo, KillingImpact Falcon game, + 2 NoCrew Falcon demos + [be1fee1130f3] + + * doc/hatari.1, doc/manual.html, doc/release-notes.txt, src/options.c: + Change --do-changes to more descriptive --mount-changes option name + [48ce1ddaed60] + +2009-11-16 Laurent Sallafranque + + * src/falcon/crossbar.c, src/falcon/crossbar.h, src/falcon/dsp.c, + src/falcon/dsp.h, src/falcon/dsp_core.c, src/falcon/dsp_core.h: + fix: DspPlay -> DMA Record in handshake mode is working. (Look at 4k + aggressive party 2 demo from Nocrew) + [73dd485d5536] + +2009-11-15 Eero Tamminen + + * doc/hatari.1, doc/manual.html, src/options.c: + document AVI recording options + move them after VDI ones (it's more + logical for VDI ones to be after Display options) + [d8e8660bbebc] + + * src/gemdos.c: + Reduce gemdos.c indenting in rest of the functions by using "early + returns" like in the other refactored functions + add some comments. + (Change is best viewed with "diff -ub", not with Mercurial.) + [1bb28a355d2f] + + * src/gemdos.c: + gemdos: Add Fcreate() Handle result to trace and improve logging + [8fe209bda5ea] + + * src/gemdos.c: + fix redundant console noise from GemDOS_CreateHardDriveFileName() + (make it understand ".\" and "\.." like code using this function) + [c90ff3b74885] + + * src/gemdos.c: + gemdos.c cleanup: use Uint8 & Uint16 instead of unsigned char & + unsigned short int as elsewhere in code + [b385f55e5d07] + + * src/gemdos.c: + simplify GemDOS_IsInvalidFileHandle() code + [1cab3d17671f] + + * doc/release-notes.txt: + add GEMDOS emu changes + WIN_FORMAT support to release-notes + [033f312cf377] + + * doc/hatari.1, doc/manual.html, src/configuration.c, src/gemdos.c, + src/includes/configuration.h, src/options.c: + add option for whether Hatari can change GEMDOS HDD dir contents, + log prevented modification attempts + [0eb2ae84c030] + +2009-11-15 Thomas Huth + + * doc/todo.txt: + New TODO item: IDE slave + [10822cff3747] + +2009-11-15 Eero Tamminen + + * doc/manual.html: + update HD Driver comment in manual too + [33564e550205] + + * src/ide.c: + IDE WIN_FORMAT command support from Uwe Seimet to get formatting + work with HD Driver + [18636b909666] + + * doc/compatibility.html: + fix class + update hddriver comment + [0b784f5586eb] + + * doc/emutos.txt: + add Cecile + [b653070efad9] + + * doc/compatibility.html: + update TT/Falcon utilities compat list + [186a208ebb1b] + +2009-11-14 Eero Tamminen + + * doc/manual.html: + HD Driver doesn't work with TOS v4 + [35cbf6afbb9f] + + * doc/manual.html: + document how to access both IDE & GEMDOS partitions with HD Driver + [d4bbda3ce96d] + + * python-ui/FILES, python-ui/Makefile: + python-ui: update FILES list / fix installation + [a2c4217b1ac2] + +2009-11-14 Laurent Sallafranque + + * src/falcon/crossbar.c, src/falcon/crossbar.h, src/falcon/dsp_core.c, + src/includes/int.h, src/int.c: + crossbar refactoring : code is now closer to reality and easier to + read. Aggressive Party 2 4Ko demo is giving some results now. (Dsp + -> DMA record in handshake mode) Still many things to do + [52753ac78dfd] + +2009-11-08 Eero Tamminen + + * doc/compatibility.html, doc/hatari.1, doc/manual.html, doc/memory- + usage.txt, src/includes/vdi.h, src/options.c: + Increase max VDI rez to TT-hi (1280x960) + related doc updates + [34c75b4caa48] + +2009-11-08 Laurent Sallafranque + + * src/falcon/crossbar.c, src/falcon/crossbar.h, src/falcon/dsp.c, + src/falcon/dsp_core.c, src/ioMemTabFalcon.c, src/mfp.c: + add: Dma Record. First attempt to include DSP out --> Dma record + mode in handshake mode. I Still have to do: + - customize handshake mode for both DSP -> DMA and DMA -> DSP + - finish to map the codecs attenuation and amplifications + - change generate_sound algo to interpolate sound better + [b1b5fc038906] + +2009-11-08 Thomas Huth + + * CMakeLists.txt, src/CMakeLists.txt: + Added PNG and ZLIB tests to cmake configuration files. + [d8ab3a669a94] + + * src/uae-cpu/CMakeLists.txt: + Little fix for cmake out of source builds. + [d8a5057e71c8] + +2009-11-06 Nicolas Pomarede + + * src/video.c: + Harmless correction for DisplayEndCycle when right border is + removed. + [0c8990796a1b] + +2009-11-05 Thomas Huth + + * CMakeLists.txt, src/CMakeLists.txt, src/debug/CMakeLists.txt, + src/falcon/CMakeLists.txt, src/gui-sdl/CMakeLists.txt, src/uae- + cpu/CMakeLists.txt: + Something to play with: Added experimental cmake configuration + files. Hatari recently got a modern version control system + (Mercurial instead of CVS). Maybe it's also time now to get rid of + the old and error prone Makefiles and "autopain" configure script + and switch to a more modern build system. So here are some + experimental CMake files for evaluation. + [6ca3b85c415b] + +2009-11-03 Laurent Sallafranque + + * src/falcon/crossbar.c: + add: connexions between devices, DMA_Play -> DSP_Record handshaking + mode (Wait is running, sound still have problems for now). + [20458c3d05bf] + + * src/falcon/crossbar.c, src/falcon/crossbar.h: + crossbar rewritten : added structures, opimized cycles computing, + simplified code + [fb621eb6bb7b] + +2009-11-01 Nicolas Pomarede + + * doc/compatibility.html, src/video.c: + Correctly align pixels when left border is removed. The switch to + high resolution to remove left border will make the display starts 4 + pixels earlier ; when emulating, the whole line should be shifted 4 + pixels to the left to keep pixels aligned with a normal line. + - fixes fullscreen spectrum512 images in the Overscan Demos by Paulo + Simoes + - fixes mixed normal/overscan screen where gfx in the overscan part + were not correctly aligned with the rest of the screen (ULM hidden + screen in Ooh Crikey Wot a Scorcher, FullBall by Next in the + Phaleon Demo) + [a830cfdf159f] + +2009-10-30 Laurent Sallafranque + + * src/falcon/crossbar.c, src/falcon/crossbar.h, src/falcon/dsp.c, + src/falcon/dsp.h, src/falcon/dsp_core.c, src/falcon/dsp_core.h, + src/falcon/dsp_cpu.c, src/int.c: + add: first try to implement DMA Play <-> DSP-IN handshaking mode + [f827bb5ec694] + +2009-10-26 Eero Tamminen + + * src/hdc.c, src/includes/hdc.h: + couple of functions and variable were needlessly exported in hdc.c + [e1c9f8c406c0] + +2009-10-26 Laurent Sallafranque + + * src/falcon/crossbar.c: + fix : correct 16 bit sound in DMA mode. I've removed the temporary + hack from yesterday. Pinball Dreams and Ishar 3 are now playing + correct 16 bit DMA sound + [cf9b89cf3a85] + + * src/falcon/crossbar.c: + add+fix : reintegrated direct DMA buffer rendering if DMA play is + connected to the DAC. (No need in this case to play the samples one + by one). Sound is not very nice, but all DMA_play musics are + rendering correctly (in 8 and 16 bits). + [9e29561f018d] + +2009-10-25 Eero Tamminen + + * doc/compatibility.html: + add DHS altParty STE demo and two new STE games to compatibility + list + [2632d3ea4085] + +2009-10-24 Thomas Huth + + * src/avi_record.c: + Fixed compiler warning about missing check for return type. + [aa9052b412c3] + + * src/includes/main.h, src/includes/stMemory.h, src/m68000.c, + src/main.c, src/memorySnapShot.c, src/stMemory.c: + Reworked loading and saving of ST RAM in the memory snapshots. + [ba671e341f6c] + + * src/includes/m68000.h, src/m68000.c, src/main.c: + Init instruction pairing only once, not every time during a reset. + [cd59599e602b] + + * src/m68000.c: + Clear all registers during cold reset. + [d46182f40a3d] + +2009-10-24 Eero Tamminen + + * src/debug/debugui.c, src/debug/evaluate.c, src/debug/evaluate.h, + tests/test-evaluate.c: + Parse Uint32 instead of long long to get rid of C99 LLONG_* defines, + show also signed value in DebubUI when highest bit is set. + [fca981bbcf23] + + * src/scandir.c: + fix BeOS/Sun scandir() implementation dir & alloc leaks on errors + [a01ea2fc82bb] + +2009-10-22 Eero Tamminen + + * tests/test-breakcond.c: + remove obsolete comments, return error code on program failure + [770c04f19333] + + * tests/Makefile, tests/test-evaluate.c: + add test code for expression evaluation + [c4428ffb20fa] + + * src/debug/evaluate.c: + more correct error message on erronous unary operation. + [c8ad66b5c5af] + +2009-10-21 Eero Tamminen + + * doc/compatibility.html: + add TOYS wait demo and notes about NoCrew MP2-player use in demos. + [4fbcfe9fa0d6] + + * src/debug/evaluate.c: + fix: include stdio.h + [b5eaec51a1b0] + +2009-10-21 Laurent Sallafranque + + * src/falcon/crossbar.c: + fix: reduced DAC buffer size to MIXBUFFERSIZE value. + [08714537482e] + +2009-10-18 Laurent Sallafranque + + * src/falcon/crossbar.c: + add: separated left and right channel in the DAC device. Added + correct destination tests for each device of the crossbar (except + DMA for now). To fix : frequencies are still not always correct, DAC + buffer size is too big and generates a delay. + [b43a271fe1de] + +2009-10-18 Eero Tamminen + + * src/screenSnapShot.c: + fix compile warning: remove unused bGrabWhenChange + [7c26b9a20cc0] + + * src/avi_record.c, src/includes/avi_record.h, src/main.c, + src/sound.c, src/statusbar.c, src/video.c: + consistent recording bool names: AviRecording -> bRecordingAvi + [2e67ce9082ce] + +2009-10-18 Nicolas Pomarede + + * src/includes/screenSnapShot.h, src/screenSnapShot.c, src/video.c: + Screenshots animation recording is replaced by AVI recording, remove + old code + [41eb5a61af19] + + * src/statusbar.c: + Update status bar when AVI recording is ON + [961d2772abcf] + +2009-10-17 Nicolas Pomarede + + * src/gui-osx/SDLMain.m: + Use AVI recording instead of screenshots animation + [6dea328884e5] + + * src/shortcut.c: + Associate 'record anim' key (alt+a) to avi recording instead of + screenshots recording + [74c9d173c3f0] + + * src/avi_record.c, src/includes/pixel_convert.h, + src/screenSnapShot.c: + Group in a single file the functions used to convert pixels from + 8/16/32 to 24 bits + [464fcf2b17dc] + +2009-10-15 Nicolas Pomarede + + * src/avi_record.c, src/gui-sdl/dlgScreen.c, + src/includes/avi_record.h, src/main.c, src/sound.c, src/video.c: + Use Avi_ instead of Avi for all functions in avi_record.c + [7c7a5a6b3c61] + +2009-10-14 Eero Tamminen + + * doc/manual.html, src/main.c: + Allow --run-vbls to be used also without --fast-forward mode. + [000e5e041d4a] + +2009-10-12 Laurent Sallafranque + + * src/falcon/crossbar.c: + Fix: don't reload the dsp xmit handler is DSP becomes tri-stated + Add: 32 Mhz frequencies + [26e992496b4b] + +2009-10-11 Eero Tamminen + + * src/avi_record.c: + AVI: functions declared static should be static, return error on + unsupported codecs. + [528ebd601339] + + * src/main.c: + show note about AVI also on Hatari exit + [0161ff0e83a6] + + * src/gui-sdl/dlgScreen.c: + AVI indexing can take while, show note in statusbar about what's + going on. + [a9bae891eddd] + + * src/debug/calculate.c, src/debug/calculate.h: + Aarg. Commit removed files too... + [f6f8a5c4017e] + + * src/debug/Makefile: + update also Makefile + [e2e53cb27d55] + + * src/debug/breakcond.c, src/debug/debugcpu.c, src/debug/debugdsp.c, + src/debug/debugui.c, src/debug/evaluate.c, src/debug/evaluate.h: + rename calculate.* to (now) more appropriate evaluate.*. + [535fc59eea0c] + + * src/debug/breakcond.c, src/debug/calculate.c, src/debug/calculate.h, + src/debug/debug_priv.h, src/debug/debugcpu.c, src/debug/debugdsp.c, + src/debug/debugui.c: + evaluate command uses same number base & parsing as rest of debug + commands: + - Moved number and range parsing functions to calculate.c so that it + it can split to functionality used by expression evaluation and a + wrapper for rest of the debug commands (which parse NULL terminated + arguments). + - Added support for parsing 0x/0b/0d/0o prefixes and improved number + parsing error messages. + - Those functions prefix is now Eval_*. + - Removed calculate.c own number parsing functionality and + simplified it otherwise a bit. + [6fb7ce170fa0] + +2009-10-10 Nicolas Pomarede + + * src/avi_record.c, src/gui-sdl/dlgScreen.c, + src/includes/avi_record.h: + Fix avi record/stop button in sdl gui + [4d34780721f1] + + * src/avi_record.c: + Thomas committed before me :) Merge my changes for libpng + [731942c00582] + +2009-10-10 Thomas Huth + + * src/avi_record.c: + Check for availability of libpng, so that Hatari now compiles w/o + libpng again. + [8452d61aa756] + + * Hatari.xcodeproj/project.pbxproj: + Updated Xcode project so that Hatari can be compiled again. + [7f41257ebc84] + +2009-10-10 Eero Tamminen + + * Makefile-default.cnf, src/Makefile, src/debug/Makefile, + src/falcon/Makefile, src/gui-sdl/Makefile: + improve CFLAGS & LIBS handling in Makefiles: + - current Makefile-default.cnf was forcing X11, PNG & portaudio to + be linked to hmsa, fixed that + - use X11, PNG & portaudio CFLAGS only when needed + - move CFLAGS place in falcon & debug Makefiles later as they were + adding values that were changed later in Makefile (it worked + because '=' assignment is deferred one, but it would have broken + if one would have used ':=' immediate assignment for CFLAGS) + [f3588d680201] + +2009-10-10 Laurent Sallafranque + + * src/falcon/crossbar.c: + add: added the monitored track in the DAC. bobTracker delivers sound + now. fix: correct computing of the DSP Xmit and receive frame + + Still strange : (bobTracker and willi's adventure) are playing 2 + times slower than normal, but "graoumf tracker is no so damn slow" + plays at correct speed). They all seem to have the same parameters. + [dbbaa5c550e8] + +2009-10-09 Nicolas Pomarede + + * src/screenSnapShot.c: + Restore erroneously removed surface's locking + [3c04a252d946] + + * doc/release-notes.txt, doc/todo.txt: + Update todo/release-notes with AVI recording + [dee90d30dc64] + + * src/options.c: + Change syntax for avi related options on the command line + [56bfcb1719a1] + + * src/avi_record.c, src/screenSnapShot.c: + Fix some compiler warnings with type casting. + [d2d47c1a7534] + +2009-10-08 Nicolas Pomarede + + * src/avi_record.c: + Add missing include for SDL_SwapLE16 (for old SDL versions) + [f043794931e6] + +2009-10-08 Eero Tamminen + + * src/Makefile, src/crossbar.c, src/falcon/Makefile, + src/falcon/crossbar.c, src/falcon/crossbar.h, + src/falcon/microphone.c, src/falcon/microphone.h, + src/includes/crossbar.h, src/includes/microphone.h, + src/microphone.c: + move crossbar.* and microphone.* under falcon/ as they're Falcon + specific + [cb6b6e5d97a0] + +2009-10-07 Laurent Sallafranque + + * src/crossbar.c: + fix : new crossbar frequencies calculations. Big thanks to Thomas + for his help. Sound is now perfect with some programs, but still + wrong with some others. Still some work to do. + [dcc0ebb28344] + +2009-10-07 Nicolas Pomarede + + * src/gui-sdl/dlgScreen.c, src/includes/options.h, src/main.c, + src/options.c, src/sound.c, src/video.c: + Plug avi recording into Hatari. Command line and GUI are now usable + to record avi. + [8d951eb1b448] + + * src/Makefile, src/avi_record.c, src/includes/avi_record.h: + Add avi recording capabilities Support BMP or PNG compression for + the video stream and 16 bits stereo PCM for the audio stream. + [e433fdf1ea20] + + * src/includes/screenSnapShot.h, src/screenSnapShot.c: + Split ScreenSnapShot_SavePNG(), to reuse the png image compression + in avi_record.c Also add some parameters to choose compression level + and cropping. + [4cc2e4917740] + +2009-10-07 Eero Tamminen + + * src/debug/calculate.c, src/debug/calculate.h, src/debug/debugui.c: + more calculator simplification / cleanup: + - use long longs instead of doubles -> allowed removing bitwise op + functions + - removal of power operation (^) allowed adding XOR bitwise operation + (^) + - return is not a function, remove parenthesis + [09300aec3ffa] + + * src/debug/debugui.c: + no eval arguments should give help, not crash. update eval help. + [30eb0d0005eb] + + * src/debug/calculate.c: + simplify/clean calculator: + - remove modulo & power operations + - remove octal and ascii support + - change int/TRUE/FALSE to bool/true/false + - change < & > to more familiar << & >> + [f553a6284af8] + +2009-10-07 Laurent Sallafranque + + * src/crossbar.c: + crossbar fix : some changes shouldn't have been uploaded. I've + return to the previous code. + [52e7e21dc4eb] + + * src/crossbar.c, src/falcon/dsp_core.c, src/falcon/dsp_core.h, + src/falcon/dsp_cpu.c: + fix : correct bug in DSP interrupts. Rewrote of this part of code. + And interrupt at a certain level can't interrupt the DSP is the SR + mask is at the same level. This corrects AFM and Are you sitting + comfortably demo. + [0ea1ced6a427] + +2009-10-06 Eero Tamminen + + * src/debug/Makefile, src/falcon/Makefile, src/gui-sdl/Makefile: + clean also created *.a files + [bd1235dfa19c] + + * readme.txt: + note in readme that Hatari is also STE/TT/Falcon emu + [bb3e08d8c9d1] + +2009-10-02 Laurent Sallafranque + + * src/microphone.c: + fixed a stupid include mistake :) + [e82bf51861dd] + +2009-10-01 Laurent Sallafranque + + * src/crossbar.c, src/falcon/dsp.c, src/falcon/dsp.h, + src/falcon/dsp_core.c, src/falcon/dsp_core.h: + add: separate DSP Xmit and DSP Receive (SSI mode). Add SCK transmit + and receive. Add frame for Tx and RX relative to the number of + tracks played or recorded in the crossbar. + [0de41927746a] + + * src/crossbar.c, src/includes/microphone.h, src/microphone.c: + code cleaning + [854cd6be3fee] + +2009-09-30 Laurent Sallafranque + + * src/crossbar.c, src/includes/microphone.h, src/includes/portaudio.h, + src/microphone.c: + fix : remove portaudio.h from hatari. check HAVE_PORTAUDIO in the + microphone.c and its header file + in crossbar.c + [8141d4cc8e34] + +2009-09-30 Eero Tamminen + + * Makefile-default.cnf: + improve make config settings comments + [e36af331096d] + + * doc/emutos.txt: + trivial update to emutos compat list + [700a133e0c0e] + +2009-09-30 Laurent Sallafranque + + * src/includes/microphone.h, src/includes/portaudio.h, + src/microphone.c: + fix : added microphone files, sorry :) + [a636661d7e2a] + + * Makefile-default.cnf, src/Makefile, src/crossbar.c, + src/falcon/dsp_core.c, src/includes/crossbar.h, src/includes/int.h, + src/int.c: + add : included portaudio library to emulate the falcon Jack input. + Many problems to solve in crossbar. + [2e0358b30785] + +2009-09-28 Thomas Huth + + * src/gui-sdl/dlgSound.c: + Fixed 50 kHz sound radio button. + [6da8f6ac92b1] + +2009-09-28 Eero Tamminen + + * readme.txt: + mention optional libraries in the readme + [18061864ade5] + +2009-09-26 Laurent Sallafranque + + * src/crossbar.c, src/includes/sound.h, src/reset.c: + fix : added crossbar in reset.c + [bdfcba8d4dd3] + + * src/crossbar.c: + applied Eero's patch : DAC out sound buffer size declared in a + define + [33559e39c942] + + * src/crossbar.c: + increased DAC out buffer size : DSP sound is perfect now + [84d088d4121f] + +2009-09-25 Laurent Sallafranque + + * src/crossbar.c, src/includes/sound.h: + put back MIXBUFFER_SIZE 8192 in sound.h resize up the DAC out + buffer. Now, DSP sound is nearly perfect (there's still an artefact + I'd like to correct) DSP out frequency is now correct. (Test with + Willi's adventure for example) + [324b9837caca] + +2009-09-24 Eero Tamminen + + * doc/compatibility.html: + Willie has music with DSP + [c0b416549855] + + * src/screenSnapShot.c: + fix surface locking + [b64ca1e4a908] + +2009-09-23 Laurent Sallafranque + + * src/crossbar.c, src/includes/crossbar.h, src/includes/int.h, + src/includes/sound.h, src/int.c: + fixed 16 bit stereo mode and 8 bits mono mode. Renames carefully DMA + functions into DMA sound. Code beautification and comments added + [2d6a05bb0ef7] + +2009-09-22 Laurent Sallafranque + + * src/crossbar.c, src/includes/sound.h: + DMA sound is nearly perfect now (no more freezing) and quality is + much better than before. + [985dc15cb2e5] + +2009-09-23 Eero Tamminen + + * src/debug/calculate.c: + fix indenting in calculate.c + [b6dd9e2869a5] + +2009-09-22 Eero Tamminen + + * doc/manual.html, src/debug/calculate.c, src/debug/debugui.c: + fix evaluate command parenthesis handling + document it. Don't + repeat shown value. + [61556cc8e1ac] + + * src/debug/calculate.h: + add header + [86e101dda8ac] + +2009-09-22 Laurent Sallafranque + + * src/crossbar.c, src/includes/crossbar.h, src/ioMemTabFalcon.c: + Dma sound work again (but freezes randomly for now) Dma sound is + really much better quality than before (listen to Eko system demo + for example) Everything is not yet coded. Still a lot of work to do + :) + + removed DmaSnd from iomemtabfalcon definively + [fadb6c35e332] + +2009-09-22 Eero Tamminen + + * doc/release-notes.txt, doc/todo.txt, src/debug/Makefile, + src/debug/calculate.c, src/debug/debugui.c: + add first version of "evaluate" calculation command to debugger + (parenthesis handling doesn't work yet). + [edc5be98f4a5] + +2009-09-21 Laurent Sallafranque + + * src/crossbar.c, src/falcon/dsp.c, src/falcon/dsp.h, + src/falcon/dsp_core.c, src/falcon/dsp_core.h, + src/includes/crossbar.h, src/includes/int.h, src/int.c: + - Prepared SC0, SC1, SC2 (set and get) for DSP SSI + - Rewrite of DSP sound interrupt (sound is much better now, listen to + willi's adventure for example) + - prepared DMA sound (still not working for now) + [532ea8e569df] + +2009-09-20 Eero Tamminen + + * src/debug/breakcond.c, src/debug/debug_priv.h, src/debug/debugcpu.c, + src/debug/debugdsp.c, src/debug/debugui.c, src/includes/str.h, + src/str.c: + move Number and Range parsing back to DebugUI from str.c (as DebugUI + got refactored and these are only used by debug code) + [7b0a0c8b3565] + + * python-ui/Changelog, python-ui/release-notes.txt: + rename changelog to (user visible) release-notes.txt as suggest by + Thomas + [420608d20b01] + + * python-ui/Changelog, python-ui/TODO, python-ui/debugui.py, python- + ui/dialogs.py, python-ui/hatari.py, python-ui/uihelpers.py: + Support for setting CPU level & clock and Falcon DSP type: + - table dialog helper supports multiple columns + - table helper for radio button group items + - use above in machine config dialog + - add CPU level & clock and Falcon DSP support to machine config + dialog and configuration handler + [527f82ec2c12] + +2009-09-20 Thomas Huth + + * src/crossbar.c, src/dmaSnd.c, src/includes/main.h: + Introduced CPU_FREQ define. + [0a9811e224a5] + +2009-09-20 Eero Tamminen + + * python-ui/Changelog, python-ui/README, python-ui/TODO: + update python-ui docs to latest state + [d618edea3f6b] + + * doc/todo.txt: + add rs323, update directory todo + [7d5bd8df4703] + + * src/falcon/dsp_core.c, src/falcon/dsp_core.h: + fix compiler warnings + [071d8b90a864] + + * src/crossbar.c, src/includes/crossbar.h: + fix again compiler warnings + [ec5a1ad2cd7d] + +2009-09-19 Laurent Sallafranque + + * src/sound.c: + fix: change arnaud carre by arnaud carr + [123f2f3736b9] + + * src/dmaSnd.c: + fix: use the correct 68000 frequency for Dma sound frequency. + [e4c6b52e35c1] + + * src/crossbar.c, src/dmaSnd.c, src/includes/crossbar.h, + src/includes/dmaSnd.h, src/ioMemTabFalcon.c, src/mfp.c, src/sound.c: + added the crossbar to the falcon. finished to separate Ste/TT Dma + sound and crossbar sound Added comments to crossbar code + [a986d6a12211] + +2009-09-19 Thomas Huth + + * src/m68000.c, src/mfp.c, src/uae-cpu/fpp.c, src/uae-cpu/gencpu.c, + src/uae-cpu/newcpu.c, src/uae-cpu/newcpu.h, src/video.c: + Shortened the M68000_EXCEPTION_SRC_... defines a little bit for + better readability. + [29bd51d3d671] + + * src/falcon/dsp.c, src/falcon/dsp.h, src/falcon/dsp_core.c, + src/falcon/dsp_core.h, src/m68000.c, src/mfp.c, src/uae- + cpu/newcpu.c, src/uae-cpu/newcpu.h: + Added HREQ DSP interrupt (needed for Graoumpf Tracker). + [260eda49da65] + + * src/includes/m68000.h, src/mfp.c: + Removed the old FIND_IPL macro. + [be6f90f8c666] + +2009-09-19 Laurent Sallafranque + + * src/dmaSnd.c, src/ioMemTabSTE.c, src/ioMemTabTT.c: + little fixes. + [5194b5938839] + +2009-09-17 Eero Tamminen + + * src/includes/crossbar.h: + remove inappropriate static function declarations from header + [e33a17c47759] + +2009-09-16 Laurent Sallafranque + + * src/crossbar.c, src/debug/log.c, src/debug/log.h: + add : crossbar logs + [fcdefddec4c2] + + * src/crossbar.c, src/dmaSnd.c, src/includes/dmaSnd.h: + rename DmaSnd_GetsoundFromDAC() in DmaSnd_ReceiveSoundFromDAC() + [a4734dbd723a] + + * src/Makefile, src/crossbar.c, src/dmaSnd.c, src/includes/crossbar.h, + src/includes/dmaSnd.h, src/int.c, src/ioMemTabFalcon.c, + src/ioMemTabSTE.c, src/ioMemTabTT.c: + add : crossbar.c for falcon sound matrice management. transfered + access to dsp from dmaSnd.c to crossbar.c + [8b4585b74986] + +2009-09-15 Eero Tamminen + + * tools/hmsa/Makefile: + update hmsa include paths after debug code splitup + [287b9da8dc91] + +2009-09-15 Laurent Sallafranque + + * src/falcon/dsp.c, src/falcon/dsp.h, src/falcon/dsp_core.h: + add Dsp_get_HREQ to get the state of HREQ bit for mfp/combel + interrupts + [195d02b5f536] + +2009-09-15 Eero Tamminen + + * doc/release-notes.txt, doc/todo.txt, src/debug/debugui.c, + src/debug/log.c, src/debug/log.h, src/includes/options.h, + src/options.c: + add argument completion support to debugger h, o, t, f, l, s + commands + [d6d6432d1b23] + + * doc/manual.html, src/debug/debugui.c: + add separate "trace" debugger command + improve manual debugger + section + [c2bd9568ffd7] + + * tests/test-breakcond.c: + really fix for debugui split + [0326938b4dd0] + + * src/debug/Makefile, src/debug/breakcond.c, src/debug/debug_priv.h, + src/debug/debugcpu.c, src/debug/debugcpu.h, src/debug/debugdsp.c, + src/debug/debugdsp.h, src/debug/debugui.c, src/debug/debugui.h, + src/falcon/dsp.c, src/uae-cpu/newcpu.c, tests/test-breakcond.c: + split DSP and CPU debugging code to separate files from debugui.c. + [05c907fa0b58] + +2009-09-14 Eero Tamminen + + * src/debug/breakcond.c, src/debug/breakcond.h, tests/Makefile, tests + /test-breakcond.c: + move breakcond.c test code to new tests/ directory at top level + - export some of the static parsing functions for the test code + [961aa7d45504] + + * src/uae-cpu/Makefile, src/uae-cpu/hatari-glue.c, src/uae-cpu/hatari- + glue.h, src/uae-cpu/memory.c, src/uae-cpu/newcpu.c: + Use Hatari includes in uae-cpu/* without paths like in all other + files + [a8315a5c6b23] + +2009-09-13 Laurent Sallafranque + + * src/falcon/dsp_core.c: + very little optim in HREQ computing + [9cdd9fb11f46] + +2009-09-13 Eero Tamminen + + * src/Makefile, src/breakcond.c, src/debug/Makefile, + src/debug/breakcond.c, src/debug/breakcond.h, src/debug/debugui.c, + src/debug/debugui.h, src/debug/log.c, src/debug/log.h, + src/debugui.c, src/falcon/Makefile, src/includes/breakcond.h, + src/includes/debugui.h, src/includes/log.h, src/log.c, src/uae- + cpu/Makefile, src/uae-cpu/newcpu.c: + move debugui[ch], breakcond.[ch] and log.[ch]to debug/ + -subdirectory + [f631b702fad3] + +2009-09-10 Eero Tamminen + + * doc/release-notes.txt, doc/todo.txt, src/breakcond.c, src/debugui.c, + src/includes/breakcond.h: + finish initial version of debugger readline completion + functionality: + - ifdef completion out when readline isn't available + - complete first word as command regardless of whitespace + - complete breakcond variables after command + [cb61d96a261b] + +2009-09-09 Laurent Sallafranque + + * src/hd6301_cpu.c: + lot's of bugs corrected + major rewrite of the code + add of ccr bit + H management + [c0dd22f00a40] + +2009-09-10 Eero Tamminen + + * doc/todo.txt, src/debugui.c: + add readline completion for debugger commands + [79f02cbc159d] + +2009-09-07 Eero Tamminen + + * src/log.c, src/options.c: + fix "--trace help": + - terminate opt parsing at Hatari startup + - still don't show extra usage in debugger + [0862918946da] + +2009-09-06 Nicolas Pomarede + + * src/uae-cpu/newcpu.c: + Preserve SPCFLAG_DEBUGGER (for checking breakpoints) after a + cold/warm reset. + [db291f43ea1e] + +2009-09-05 Laurent Sallafranque + + * src/hd6301_cpu.c, src/hd6301_cpu.h: + code beautification + [ad73d91f8d8d] + +2009-09-05 : *** Version 1.3.1 *** + +2009-09-05 Thomas Huth + + * doc/release-notes.txt: + Updated release notes for version 1.3.1 + [9fb9dc477e75] + + * Info-Hatari.plist, configure.ac, doc/doxygen/Doxyfile, hatari.spec, + readme.txt, src/gui-osx/English.lproj/InfoPlist.strings, + src/includes/main.h: + Increased version number to 1.3.1 + [0ffa580c704d] + +2009-09-03 Thomas Huth + + * src/floppy.c: + Fixed HD boot drive when drive C: does not exist. TOS 2.06 was + crashing during the boot process when drive C: did not exist, but + Hatari wrongly declared this drive as boot drive. + [7763d64c36aa] + + * src/gemdos.c: + Fixed drive enumeration of GEMDOS HD emulation. Single partition + GEMDOS HD emulation did not work anymore when an ACSI HD image was + also used, due to some problems with the automatic drive letter + detection. + [3bfce602e42a] + + * src/stMemory.c: + Fix ConnectedDriveMask with multiple, non-contiguous GEMDOS + partitions. + [ac7bbcfe1801] + +2009-08-25 Eero Tamminen + + * python-ui/Makefile: + Fix to incorrect use of DESTDIR in python-ui installation + [915340642fd3] + +2009-08-17 Eero Tamminen + + * src/debugui.c: + more compact debugger output (return to emulation msg) + [240c39b890ef] + + * python-ui/dialogs.py: + update copyright, fix trace settings names + [e8ba0d2c79c9] + + * python-ui/debugui.py: + fix: debugger memdump/disasm show/save/load need now to use '$' for + hex + [5a1592749444] + +2009-08-17 Thomas Huth + + * doc/compatibility.html, doc/manual.html: + Improved the CSS of the manual and compatibility list. The "font- + family:Fixed" did not work at all on Windows. Also cleaned up the + CSS in general. + [21687104622b] + + * src/Makefile, src/gui-win/Makefile: + The hatari icons for the Windows executable must not be put into an + archive for linking. + [1d35342eb1bc] + +2009-08-16 : *** Version 1.3.0 *** + +2009-08-16 Thomas Huth + + * python-ui/dialogs.py: + Changed the website URL to the new home of Hatari at berlios.de + [05a83cb7f76a] + + * python-ui/Makefile: + Fixed installation of the python-ui + [feb0ae323aff] + + * src/falcon/dsp_core.c: + Silenced compiler warning about unused variables. + [f6a3ccc303ea] + + * doc/release-notes.txt: + Updated release notes for version 1.3.0 + [a07860a61bf8] + + * doc/doxygen/Doxyfile: + Removed obsolete Doxygen settings. + [7afaa1d83324] + + * src/screenSnapShot.c: + Reworked a comment that confused Doxygen. + [492d9e10a519] + + * Info-Hatari.plist, configure.ac, doc/doxygen/Doxyfile, hatari.spec, + readme.txt, src/gui-osx/English.lproj/InfoPlist.strings, + src/includes/main.h, src/memorySnapShot.c: + Increased version number to 1.3.0 + [0c734b1a5776] + + * .hgignore: + Added generated Doxygen files to .hgignore file + [126cb8fe341c] + + * doc/manual.html: + Added a note about changing the DSP option + [1ff74562f62c] + + * src/sound.c: + Don't save sound configuration options in memory snapshots. + [cf1faf50cd4b] + + * src/dmaSnd.c: + Scale DMA samples by factor 0.5 instead of 0.707. Since the YM + samples are now pretty much normalized, we have to adapt the volume + level of the DMA samples accordingly. + [650448480c94] + + * src/sound.c: + Always remove the DC part of the YM samples. Normalizing the level + of the YM samples makes it easier to mix them with the DMA samples + later. + [2ff4776b0954] + +2009-08-16 Eero Tamminen + + * doc/compatibility.html: + rg demo needs 14MB to work reliably + [5e34df26eba3] + + * doc/manual.html: + mention DSP continue in addition to CPU continue + [f385812ca925] + + * src/breakcond.c: + update breakpoint condition test code to latest changes + [184b729a4db0] + +2009-08-16 Thomas Huth + + * src/debugui.c: + Silenced compiler warning that happened with GCC 4.3 + [6e5ea9bddbac] + +2009-08-16 Eero Tamminen + + * doc/emutos.txt: + more emutos compatible gem/mono games + [1f6717b6c6bd] + +2009-08-15 Eero Tamminen + + * src/uae-cpu/newcpu.c: + if exceptions aren't catched in debugger, show user a dialog about + CPU halting + [c7f84096ce48] + + * doc/manual.html: + tell about Hatari variables support in conditional breakpoints + [cdc24363bf70] + + * doc/release-notes.txt: + note regs/vars showing on entering debugger + [bdfa8de0865f] + + * doc/todo.txt: + add calculator, indentation fix + [bfde57ccc9be] + + * src/debugui.c: + make debugger output more concise + add regs/vars info: + - values command output as one-liner + - show reg/var one-liner on entering debugger + - show welcome only on first time + [90a940da8090] + + * src/breakcond.c, src/debugui.c: + fix PC and SR access for conditional breakpoints, add size to + FUNCTION type define + [d5b1fe5c67e7] + +2009-08-15 Thomas Huth + + * src/dmaSnd.c: + Scale DMA sound samples by factor 0.707 instead of 0.5. This factor + seems to be closer to a real STE. Thanks to Per Almered for the + hint! + [1ea9d6316474] + + * src/configuration.c: + Renamed LogDebug section back to Log to avoid breaking old config + files. + [87b63b6bde51] + +2009-08-15 Eero Tamminen + + * doc/hatari.1, doc/manual.html, src/options.c: + remove toggling of Pause key functionality with -D (it's redundant + as one can set the Pause & Debug keys in config file) + [8bbc44eefb33] + +2009-08-15 Thomas Huth + + * src/gui-win/Makefile, src/gui-win/opencon.c: + Fixed compiling on MinGW + [f808a3b0eb81] + + * src/debugui.c, src/shortcut.c: + Always return to window mode when entering the debugger. This fixes + the problem that the emulator freezes in fullscreen mode when it + enters the debugger due to a breakpoint. + [279cc4fe485c] + + * doc/todo.txt: + Added LMC1992 to the TODO list. + [aa72ccab20d9] + +2009-08-14 Thomas Huth + + * src/video.c: + Fixed palette problem in VDI mode. The code did not call + Video_StoreFirstLinePalette() anymore - which is called from the HBL + function, but since the HBLs have been disabled in VDI mode, this + does not happen anymore. So HBLPalettes did not get initialized + correctly in monochrome and TT/Falcon mode, and + Screen_CreatePalette() then set the wrong colors. + [0522887d10fc] + +2009-08-13 Thomas Huth + + * website/scrshots1.html, website/scrshots4.html, + website/scrshots5.html: + Updated website with Eero's latest screenshots (mainly STE). + [42b221c535d5] + +2009-08-11 Eero Tamminen + + * doc/compatibility.html: + update badmood & pmheretic/pmdoom notes + [bc223a10adad] + +2009-08-11 Nicolas Pomarede + + * src/video.c: + No need to handle $ff820a in VDI mode + [9df6f34751a8] + +2009-08-10 Eero Tamminen + + * doc/emutos.txt: + add rebirth + [4ecf57e23895] + + * doc/memory-usage.txt: + fix typos + [5a84fb52fc77] + + * doc/compatibility.html: + minor updates to 3 falcon program compatibility + [a48834359d9a] + + * doc/todo.txt: + indent all subitems the same way + wrap to 80 columns + [279e75ce47f6] + +2009-08-10 Laurent Sallafranque + + * src/falcon/dsp_cpu.c: + FIX : some parts of SS stack (SSH+SSL). SSH moves are now + increasing/decreasing correctly the stack. I've also masked to 16 + bits the SSH/SSL values. + [766b69f99367] + +2009-08-10 Nicolas Pomarede + + * src/includes/video.h, src/mfp.c, src/video.c: + Use Video_AddInterruptTimerB when Timer B positions is changed in + MFP_ActiveEdge_WriteByte. + [e53ed3601bf5] + +2009-08-09 Eero Tamminen + + * doc/todo.txt: + add debugger TODOs, collect screen TODOs together + list Kåre's + stuff + [25fd3fb29bcd] + +2009-08-09 Nicolas Pomarede + + * src/video.c: + Don't update HBL / Timer B interrupt's position when VDI mode is + used. + [2f7cb88dd314] + +2009-08-09 Eero Tamminen + + * doc/release-notes.txt: + tune DSP notes based on todo, update/add debugging notes, add note + about doc updates + [dbce71211d73] + + * doc/manual.html: + large debugger section update, nice box for 
 tags, minor fixes
+	[0bb4ca03093a]
+
+	* src/breakcond.c:
+	value accessor function/variable support in breakcond.c -> possible
+	to break on specific place on screen:
+	- changed regsize member to valuetype and define few enum values for
+	it
+	- names for Hatari variables and functions can now be of arbitrary
+	lenght
+	- support selecting value helper functions by name and calling them
+	when checking for breakpoints.
+	- help lists also the function variable names and values. This and
+	above is a bit ugly as it requires casts which compiler cannot
+	check for type safety
+	- updated test code accordingly + fixed earlier breakage
+	[5a4ab49cb9c1]
+
+	* src/configuration.c, src/debugui.c, src/includes/configuration.h,
+	src/str.c:
+	add support for configuring default number base (in debugger):
+	- nNumberBase config setting added to configuration
+	- Config file Log section renamed to LogDebug because of this
+	- debugui value command can now change the default number base
+	- in Str_GetNumber() the number prefix can be left out from values
+	in the selected/default number base. When it's other than
+	10-based, decimals need to be prefixed with '#'
+	[79ec43f49b78]
+
+	* doc/compatibility.html:
+	add links for games which still have homepages, note about newer
+	Calamus
+	[68bdd767f40e]
+
+2009-08-08  Eero Tamminen
+
+	* doc/hatari.1, doc/manual.html, src/configuration.c, src/debugui.c,
+	src/includes/configuration.h, src/includes/debugui.h,
+	src/includes/main.h, src/main.c, src/options.c, src/shortcut.c, src
+	/uae-cpu/newcpu.c:
+	Add always available shortcut for debugger:
+	- rename config file keyDebug setting to keyPause and add new
+	keyDebugger for the Debugger shortcut. By default debugger needs
+	AltGr with Pause
+	- as debugger is always available, rename bEnableDebug to
+	bExceptionDebugging and move it from main.c to debugui.c
+	- besides toggling bExceptionDebugging on -D option, switch whether
+	pause or debugger functionality needs AltGr modifier when Pause key
+	is pressed for easier debugger use
+	- show in statusbar when console debugger is invoked
+	- update -D option & shortcuts documentation
+	[2d9abff9bcd7]
+
+	* src/includes/log.h, src/log.c, src/options.c:
+	improve option error and usage messages, especially for --trace in
+	debugger
+	[7c74d8e01476]
+
+2009-08-07  Thomas Huth
+
+	* doc/manual.html:
+	Added chapter about the debugger and cleaned up for version 1.3
+	[07169ee30e7f]
+
+2009-08-06  Nicolas Pomarede
+
+	* doc/todo.txt:
+	Add item on avi recording
+	[75a6394d54b8]
+
+	* doc/release-notes.txt, doc/todo.txt:
+	Update release's notes for video changes
+	[ba8925d2094a]
+
+	* src/video.c:
+	Don't update HBL/Timer B interrupt's position on the last line when
+	freq or res are changed. This completes the patch from rev 2116 : as
+	we don't call Video_StartHBL on the last visible line, we should
+	also ensure that when frequency or resolution are changed on the
+	last HBL (312 at 50 Hz) we don't update the HBL or Timer B position,
+	else we'll get a crash as ShifterLines[ nHBL+1 ] is not initialized.
+	(fix hatari's crash in TCB Guest Screen in Nostalgic-o-demo by
+	Oxygene)
+	[b7b9271c6bad]
+
+2009-08-05  Nicolas Pomarede
+
+	* src/video.c:
+	Correct wrong 'right-2' border detection when switching to 50Hz at
+	cycle 372 (fix self calibration routine used in Lethal Xcess
+	hardscroll).
+	[5937371a8c73]
+
+2009-08-04  Thomas Huth
+
+	* website/scrshots6.html:
+	Added Laurent's new screenshots of Falcon DSP programs.
+	[95a743903385]
+
+	* .hgignore:
+	Added *.pyc file to .hgignore.
+	[5324f1d21b5b]
+
+2009-08-04  Laurent Sallafranque
+
+	* doc/todo.txt:
+	Update the DSP TODO list
+	[bc9a3582dc20]
+
+2009-08-03  Eero Tamminen
+
+	* src/breakcond.c:
+	allow breaking on specific internal Hatari variable values, show
+	breakpoint number
+	[a1c4958a68b4]
+
+	* src/falcon/dsp.c:
+	catch also too long dsp register names
+	[5ca5523b738d]
+
+2009-08-01  Thomas Huth
+
+	* src/dmaSnd.c:
+	Fixed Falcon 16-bit DMA samples on little endian machines.
+	[8954826a112d]
+
+	* doc/compatibility.html:
+	Updated 'Slayer' and 'Alive'
+	[a8f9c92b0f58]
+
+	* doc/todo.txt:
+	Added some more TODO items.
+	[4b9514f24e44]
+
+	* src/fdc.c, src/hdc.c:
+	Removed redundant double-checking for ACSI commands.
+	[6f75e9a0a810]
+
+2009-08-01  Nicolas Pomarede
+
+	* src/spec512.c, src/video.c:
+	Remove unused code from previous video.c
+	[215d12217dda]
+
+2009-07-31  Thomas Huth
+
+	* doc/todo.txt:
+	Updated the DSP TODO list.
+	[11ae0615a158]
+
+2009-07-30  Eero Tamminen
+
+	* doc/compatibility.html:
+	Use "Hatari version" column for Falcon games&demo compatibility
+	tables too. Correct Hatari version for some Falcon apps (when first
+	working/last tested not to work).
+	[8eb94c4e215b]
+
+2009-07-28  Nicolas Pomarede
+
+	* src/spec512.c:
+	Better timings when changing colors with movem.l and movem.w Fix
+	small glitches in Dragonnels Menu and in No Cooper Plasma, as well
+	as spec512 slideshow in The Place To Be Again Demo.
+	[15770b3f9aa9]
+
+2009-07-26  Matthias Arndt
+
+	* src/str.c:
+	* added missing include of stdio.h to make it compilable
+	[2350172692fd]
+
+2009-07-26  Thomas Huth
+
+	* src/video.c:
+	Fixed buffer overflow at the last HBL in monochrome screen mode.
+	This buffer overlow caused performance problems and other side
+	effects, especially on Mac OS X. Thanks to Kåre Andersen for the
+	patch.
+	[52e6916c3c3d]
+
+	* src/control.c:
+	Fixed compilation when HAVE_UNIX_DOMAIN_SOCKETS is not defined.
+	[036bcf1a82f6]
+
+2009-07-22  Nicolas Pomarede
+
+	* src/video.c:
+	Set default value for nFrameSkips to 0 (fix problem with OS X's
+	compiler)
+	[c314199d5bac]
+
+	* src/video.c:
+	Correct an error in Video_ConvertPosition (rare case when reading
+	video counter, mostly harmless)
+	[26def8a3f566]
+
+2009-07-21  Eero Tamminen
+
+	* src/statusbar.c:
+	Fix: overlay drive-led did save&restore blits although showing it
+	was disabled (when statusbar was also disabled)
+	[d3a4698a13ff]
+
+	* doc/release-notes.txt:
+	add note about debugger value prefixes (user visible change)
+	[e98bac15417e]
+
+	* doc/manual.html:
+	perf note about earlier versions
+	[5e4962fe5508]
+
+2009-07-19  Eero Tamminen
+
+	* src/debugui.c:
+	add new "value" DebugUI command for showing given value in
+	bin/dec/hex base
+	[b6df11082ec6]
+
+	* src/debugui.c:
+	Support number / address range prefixes in DebugUI:
+	- use the new Str_GetNumber()/Str_ParseRange() instead of own
+	functions
+	- change remainging unsigned longs to (more correct) Uint32 for this
+	- rename nBreakPoint variable to more descriptive BreakAddr
+	[dbcd7f526435]
+
+	* src/breakcond.c:
+	Change to using the new Str_GetNumber() instead of own function
+	[603318ac9a20]
+
+	* src/includes/str.h, src/str.c:
+	Add Str_GetNumber() and Str_ParseRange() for parsing numbers +
+	address ranges with prefixes
+	[5058c97a5b70]
+
+	* doc/manual.html:
+	add perf note about spec512 mode and statusbar
+	[0aa7d7934c11]
+
+2009-07-18  Thomas Huth
+
+	* src/gui-osx/PrefsController.m, src/gui-osx/Shared.m,
+	src/includes/main.h:
+	Removed the obsolete defines FALSE and TRUE.
+	[5fa1544f1dee]
+
+2009-07-18  Eero Tamminen
+
+	* src/debugui.c:
+	remove non-ASCII chars from debugui output
+	[15375a75c494]
+
+	* src/breakcond.c, src/debugui.c, src/includes/breakcond.h:
+	Breakpoints: proper condition match testing, fix multiple condition
+	handling, RemoveAll function, improve comments&output
+	[ff2d4b960826]
+
+2009-07-18  Thomas Huth
+
+	* src/dmaSnd.c:
+	Check for illegal DMA sound buffer sizes.
+	[6c657b951606]
+
+	* src/control.c, src/includes/control.h, src/xbios.c:
+	Added XBIOS remote control interface (for development only)
+	[c19cba83586f]
+
+	* website/docs.html:
+	Reworked the FAQ section.
+	[5d00c5cd4329]
+
+2009-07-18  Eero Tamminen
+
+	* python-ui/Changelog, python-ui/hatariui.py, python-ui/uihelpers.py:
+	add Hatari UI help items to Hatari docs and Hatari & Hatari UI www-
+	pages
+	[33818b9876c5]
+
+	* doc/compatibility.html:
+	move Capy to TT games, update two items
+	[d587b1227aa6]
+
+2009-07-18  Thomas Huth
+
+	* doc/compatibility.html:
+	Cleaned up the Falcon applications table and added some more
+	comments about Apex.
+	[48a6a5813b5c]
+
+	* src/falcon/hostscreen.c, src/falcon/hostscreen.h,
+	src/falcon/videl.c:
+	Removed the unused 24 bpp converters.
+	[1bfbd0accca5]
+
+	* src/main.c:
+	Ignore mouse motion when position has changed right after a reset.
+	TOS (especially version 4.04) might get confused when it receives a
+	mouse event right after a reset and then play annoying key clicks.
+	[1c4f97d5767f]
+
+2009-07-16  Nicolas Pomarede
+
+	* src/video.c:
+	When spec512 mode is off and color is changed after cycle 460, we
+	consider the change should be applied on next line. This fixes old
+	automation menu 002, where color is changed on each line on a med
+	res screen ; as spec512 mode is not supported in med res yet, we
+	must consider that any change after the maximum right border (cycle
+	460) should be applied to line nHBL+1. Else, in the case where the
+	colors are changed just before/after cycle 512, the result will
+	flicker as the change will be applied to line nHBL or nHBL+1 instead
+	of always using nHBL+1
+	[3db6c876bba5]
+
+2009-07-15  Eero Tamminen
+
+	* doc/compatibility.html:
+	compat updates: 32Mhz makes couple of demos work, add EKO demos,
+	remove 2 of 7 Lazer demos
+	[680ea7a2b358]
+
+2009-07-14  Eero Tamminen
+
+	* doc/manual.html, doc/todo.txt, python-ui/dialogs.py:
+	update docs: RS232 & MIDI I/O stable, IDE supported, GEMDOS multiple
+	dirs etc
+	[3b463b37967a]
+
+	* doc/compatibility.html:
+	add (fake?) Pinball Dreams
+	[65fb856e104e]
+
+	* src/options.c:
+	bLoadAutoSave not needed for bSlowFloppy as that's not in memory
+	save file
+	[1163e317ec07]
+
+	* doc/hatari.1, doc/manual.html, python-ui/TODO, python-ui/dialogs.py,
+	python-ui/hatari.py, src/options.c:
+	add --timer-d option, document it and support it in the python-UI
+	[41390733378a]
+
+2009-07-13  Eero Tamminen
+
+	* doc/manual.html:
+	add a section on improving Hatari performance
+	[ccacdecf0b70]
+
+2009-07-11  Eero Tamminen
+
+	* doc/authors.txt, doc/release-notes.txt:
+	update notes to latest Hatari version
+	[cd9b32d130bb]
+
+	* doc/compatibility.html:
+	went through rest of none/non-working programs + updated (DSP)
+	compatibility
+	[631c373ca734]
+
+	* src/falcon/dsp.c:
+	support PC and fix DSP_REG_SSH/SSL defines in
+	DSP_GetRegisterAddress().
+	[043f4d638127]
+
+	* doc/compatibility.html:
+	compatibility doc updates for latest DSP
+	[49352e1286e0]
+
+2009-07-10  Eero Tamminen
+
+	* src/breakcond.c:
+	Warn if given address 23th bit isn't extended properly. Finetune
+	warnings.
+	[a539291cfc84]
+
+2009-07-09  Thomas Huth
+
+	* src/video.c:
+	Fixed the "--memstate is not working" bug. Shortcuts must be
+	processed after the video interrupts have been re-started or the VBL
+	interrupt might be marked as inactive in the memory snapshot.
+	[0657f8f5778f]
+
+2009-07-08  Thomas Huth
+
+	* src/includes/control.h, src/uae-cpu/newcpu.c:
+	Use 'true' and 'false' from stdbool.h instead of the obsolete
+	defines.
+	[f963e7c5c046]
+
+	* src/convert/high640x8.c, src/convert/low320x16.c,
+	src/convert/low320x32.c, src/convert/low320x8.c,
+	src/convert/low640x16.c, src/convert/low640x32.c,
+	src/convert/low640x8.c, src/convert/med640x16.c,
+	src/convert/med640x32.c, src/convert/med640x8.c,
+	src/convert/spec320x16.c, src/convert/spec320x32.c,
+	src/convert/spec640x16.c, src/convert/spec640x32.c,
+	src/convert/vdi16.c, src/convert/vdi2.c, src/convert/vdi4.c:
+	In the screen convert code, use 'true' and 'false' from stdbool.h
+	instead of the obsolete defines.
+	[ff1cb2d5610c]
+
+2009-07-07  Laurent Sallafranque
+
+	* src/falcon/dsp.c, src/falcon/dsp_core.h, src/falcon/dsp_cpu.c:
+	add : dsp instruction cycle count. Now DSP and 68030 are more
+	accurate to each other.
+	[bc5e211a2c28]
+
+2009-07-07  Thomas Huth
+
+	* src/int.c:
+	Added assertions to make sure that no invalid parameters get passed
+	to the Int_AddInterrupt functions.
+	[2f3013fe9848]
+
+2009-07-06  Thomas Huth
+
+	* src/int.c:
+	Disabled unused function Int_AddRelativeInterruptNoOffset()
+	[80f65ef43835]
+
+2009-07-04  Thomas Huth
+
+	* src/debugui.c, src/dialog.c, src/dmaSnd.c, src/hdc.c, src/ikbd.c,
+	src/int.c, src/joy.c, src/keymap.c, src/log.c, src/m68000.c,
+	src/main.c, src/memorySnapShot.c, src/mfp.c, src/midi.c, src/msa.c,
+	src/options.c, src/printer.c, src/psg.c, src/reset.c, src/rs232.c,
+	src/screen.c, src/screenSnapShot.c, src/shortcut.c, src/sound.c,
+	src/spec512.c, src/st.c, src/statusbar.c, src/tos.c, src/vdi.c,
+	src/video.c, src/xbios.c, src/ymFormat.c, src/zip.c:
+	Use 'true' and 'false' from stdbool.h instead of the obsolete
+	defines.
+	[48f78c1be4ee]
+
+	* src/falcon/hostscreen.c, src/falcon/nvram.c, src/falcon/videl.c:
+	In the Falcon code, now also use 'true' and 'false' from stdbool.h
+	instead of the obsolete defines.
+	[2fcc1fb9d486]
+
+	* src/gui-sdl/dlgAlert.c, src/gui-sdl/dlgDevice.c, src/gui-
+	sdl/dlgFileSelect.c, src/gui-sdl/dlgFloppy.c, src/gui-
+	sdl/dlgHardDisk.c, src/gui-sdl/dlgJoystick.c, src/gui-
+	sdl/dlgKeyboard.c, src/gui-sdl/dlgNewDisk.c, src/gui-sdl/dlgRom.c,
+	src/gui-sdl/dlgScreen.c, src/gui-sdl/dlgSound.c, src/gui-
+	sdl/sdlgui.c:
+	For the SDL GUI code, now also use 'true' and 'false' from stdbool.h
+	instead of the obsolete defines.
+	[895bdc9d587a]
+
+2009-07-04  Eero Tamminen
+
+	* src/debugui.c:
+	use Uint32 for (parsing) addresses in debugui.c like elsewhere in
+	Hatari (as unsigned long would be unnecessarily 64-bits on 64-bit
+	OSes)
+	[ac5dab1e6c2c]
+
+	* src/breakcond.c, src/debugui.c, src/includes/breakcond.h,
+	src/includes/debugui.h, src/memorySnapShot.c:
+	store also debugging session state to memory snapshot (if needed,
+	it's easy to disable this from debugui.c even at run-time)
+	[823582903643]
+
+2009-07-03  Eero Tamminen
+
+	* src/breakcond.c:
+	dummy DSP_ReadMemory() function for breakcond test code
+	[542b36e95579]
+
+	* src/breakcond.c:
+	Inherit bit width & mask from the other side if not set, derive mask
+	from bit width if not set. This removes the (worst) redundant
+	warnings about mask mismatches.
+	[910298ca48e9]
+
+	* python-ui/README:
+	add Hatari UI www-page URL
+	[1073baaf53cc]
+
+	* python-ui/TODO:
+	update Hatari UI TODO to latest Hatari version
+	[9fbdbfcf5b49]
+
+	* python-ui/FILES:
+	describe all Hatari UI source etc files
+	[a9b9a7b61391]
+
+	* python-ui/hatari-console.py:
+	update to latest hatari:
+	- add missing command line options
+	- use new long debugger commands instead of short ones for clarity
+	- wait 0.2s before showing prompt so that Hatari output gets first
+	[49ce14ff8770]
+
+	* src/debugui.c:
+	debugOutput needs to be initialized also when commands are called
+	from control.c
+	[ededf28d8a56]
+
+	* src/breakcond.c, src/falcon/dsp.c:
+	add/improve debugging code comments/documentation
+	[37a08b139cf8]
+
+	* src/breakcond.c, src/falcon/dsp.c, src/falcon/dsp.h:
+	add DSP memory support to conditional breakpoints
+	[79927961d6ae]
+
+2009-07-03  Nicolas Pomarede
+
+	* src/breakcond.c:
+	Allow IO addresses between $ff8000 and $ffffff to be used as
+	indirect breakpoint addresses
+	[48fddaf04e7e]
+
+2009-07-02  Eero Tamminen
+
+	* src/breakcond.c:
+	quote '%'
+	[bbea51741eac]
+
+2009-06-27  Thomas Huth
+
+	* src/video.c:
+	Clear framecycles counter during reset. This fixes the problem on
+	Mac OS X where the video endline interrupt timings suddenly went
+	crazy after a reset or resolution switch from color to mono.
+	[3a66f38db0ad]
+
+2009-06-27  Laurent Sallafranque
+
+	* src/falcon/dsp_core.c:
+	fix : ssi.cra_wordmask value in 24 bits mode fix : remove swap
+	receive and transmit datas (crb_shifter defines the hardware way to
+	get or send the data, but at end, the data is always MSB.....LSB)
+	added some comments + code cleaning
+	[12bc6849cc7d]
+
+2009-06-27  Thomas Huth
+
+	* Hatari.xcodeproj/project.pbxproj:
+	Added breakcond.c to OS-X project file.
+	[6b767a67c566]
+
+	* src/gui-osx/PrefsController.m:
+	Fixed typo
+	[a0ce6502cee2]
+
+2009-06-24  Thomas Huth
+
+	* src/gemdos.c:
+	Fixed bug in Fopen when access mode was 3. Due to a missing comma,
+	two strings were merged in the access mode table.
+	[671c4e00a188]
+
+2009-06-21  Thomas Huth
+
+	* doc/compatibility.html:
+	Added Super Skweek.
+	[1261bf120ba6]
+
+	* src/m68000.c:
+	Do not print bus error message when program probes for FPU co-
+	processor since a lot of users got confused by the "Bus error at
+	address $fffa42" message when a program tried to detect this co-
+	processor.
+	[355775dcd624]
+
+	* src/file.c:
+	The header sys/time.h is required for compiling on Cygwin. Without
+	sys/time.h the struct timeval is not declared.
+	[2f8dcc346f2d]
+
+2009-06-20  Nicolas Pomarede
+
+	* src/blitter.c, src/fdc.c, src/ikbd.c, src/mfp.c, src/psg.c,
+	src/spec512.c, src/uae-cpu/newcpu.c:
+	Use Video_GetPosition in LOG_TRACE
+	[2d9d737fa9b7]
+
+	* doc/compatibility.html:
+	Update some STF demos for Hatari 1.3
+	[59f4cf99481c]
+
+2009-06-19  Nicolas Pomarede
+
+	* src/int.c:
+	Fix a rare bug in Int_AddAbsoluteInterrupt that could cause Hatari
+	to go in and endless loop. Int_AddAbsoluteInterrupt was not calling
+	Int_UpdateInterrupt as it didn't seem necessary in real case, but if
+	an interrupt is added to the list at the same time another interrupt
+	is ready to be served, this interrupt will be lost, because
+	PendingInterruptCount value will be lost. This fixes Dark Side Of
+	The Spoon's loader by ULM, where an FDC command (implying
+	Int_AddAbsoluteInterrupt) could sometimes happen at cycle 404 where
+	Timer B interrupt should trigger. Timer B int would be lost and
+	Hatari would enter an endless loop taking 100% CPU.
+	[257fb9b8f62f]
+
+	* src/video.c:
+	Replace remaining HATARI_TRACE with LOG_TRACE
+	[5ae3c4a862ad]
+
+2009-06-18  Nicolas Pomarede
+
+	* src/video.c:
+	Save/Restore ShifterFrame structure in memory's snapshot
+	[22d50f19c8d0]
+
+2009-06-17  Nicolas Pomarede
+
+	* src/includes/video.h, src/reset.c, src/video.c:
+	Change Video_StartInterrupts to use Video_AddInterruptTimerB and
+	Video_AddInterruptHBL instead of Int_AddAbsoluteInterrupt. Also
+	starts the VBL's int with Int_AddRelativeInterrupt and
+	PendingCyclesOver, as Int_AddAbsoluteInterrupt could be called from
+	reset.c with an incorrect value for nCyclesOver (because
+	Video_StartInterrupts has no defined value for nCyclesOver when not
+	called from an interrupt handler).
+	[f3051bd6f969]
+
+2009-06-13  Nicolas Pomarede
+
+	* src/ikbd.c:
+	Fix merge conflict
+	[589c17590a03]
+
+	* src/ikbd.c:
+	Test increasing int's cycles for sendind data
+	[73b11856dcdd]
+
+	* src/includes/video.h, src/mfp.c, src/video.c:
+	More fixes to the new code, no more regression so far ; reorganize
+	some parts to use common functions.
+	[13f92beab170]
+
+2009-05-28  Nicolas Pomarede
+
+	* src/uae-cpu/newcpu.c, src/video.c:
+	More generic tests to handle writes to $ff8260 Update Timer B's int
+	position each time res/freq is changed
+	[878e2478c8ee]
+
+2009-05-08  Nicolas Pomarede
+
+	* src/includes/video.h, src/video.c:
+	Update HBL's int position and nCyclesPerLine each time res/freq is
+	changed at a compatible position. HBL and nCyclesPerLine are now
+	fully dynamic and can have different values on different lines.
+	[0b0f82ea2e4f]
+
+2009-04-21  Nicolas Pomarede
+
+	* src/includes/video.h, src/spec512.c, src/video.c:
+	More generic tests to handle writes to ff820a
+	 - Start replacing FrameCycles by HBL/LineCycles in border tests
+	 - Always update DisplayStartCycle/DisplayEndCycle
+	 - Rewrite top/bottom border removal detection code to work with mixed
+	50/60 Hz lines
+	 - Use Video_ConvertPosition in spec512 mode
+	[fd0a5ecb2120]
+
+2009-04-15  Nicolas Pomarede
+
+	* src/includes/video.h, src/video.c:
+	Start rewritting HBL handling and add correct video address
+	calculation when mixing 50 and 60 Hz lines. (fix Omega Full
+	Overscan, TCB overscan in Swedish New Year, DI screen in MindBomb,
+	TEX screen in Syntax Terror)
+	[46d4edf4ab53]
+
+	* src/psg.c:
+	Read to the YM data register ff8800 was taking 4 more cycles than
+	expected.
+	[a3c1e1e1f66d]
+
+2009-06-20  Thomas Huth
+
+	* tools/zip2st.sh:
+	Quote input file name so that script also works with spaces in file
+	names.
+	[1cf90a0c007b]
+
+2009-06-18  Eero Tamminen
+
+	* src/breakcond.c:
+	document binary decimal %-prefix. proper string-as-value support too
+	complicated, remove it
+	[c29efdc1f81c]
+
+2009-06-18  Thomas Huth
+
+	* src/audio.c, src/bios.c, src/cart.c, src/cfgopts.c, src/change.c,
+	src/configuration.c, src/control.c, src/createBlankImage.c,
+	src/dim.c, src/fdc.c, src/file.c, src/floppy.c, src/gemdos.c:
+	Use 'true' and 'false' from stdbool.h instead of the obsolete
+	defines.
+	[17a9da3aaa54]
+
+	* src/gemdos.c:
+	Tracing of the GEMDOS function now also shows the parameters of the
+	functions.
+	[6d05caa3bfbd]
+
+2009-06-18  Eero Tamminen
+
+	* src/breakcond.c:
+	parse binary (%10101) and ascii ("ICE) values
+	[8c0414ab86bc]
+
+	* src/breakcond.c:
+	parse DSP address spaces. address type can be checked for regsize
+	and whether to use dsp from dsp_space
+	[4e10dcfa00c6]
+
+2009-06-16  Eero Tamminen
+
+	* src/breakcond.c:
+	make two mask checks warnings instead of errors, tigher other mask
+	checks
+	[fc8039e504de]
+
+2009-06-16  Thomas Huth
+
+	* Visual.Studio/VisualStudioFix.c, Visual.Studio/VisualStudioFix.h,
+	src/bios.c, src/blitter.c, src/dmaSnd.c, src/fdc.c, src/gemdos.c,
+	src/ikbd.c, src/includes/log.h, src/includes/m68000.h, src/int.c,
+	src/ioMem.c, src/log.c, src/mfp.c, src/psg.c, src/spec512.c, src
+	/uae-cpu/newcpu.c, src/vdi.c, src/video.c, src/xbios.c:
+	Simplified the macros for tracing. The trace macros all started with
+	a prefix "HATARI_", which is quite meaningless when the whole
+	project is called Hatari... So the functional macros now have got
+	the prefix "LOG_" (since they are defined in log.h) and the constant
+	macros use now simply the prefix "TRACE_".
+	[073072bf6e27]
+
+	* src/includes/breakcond.h:
+	Added missing header file breakcond.h
+	[1d466aa50b58]
+
+2009-06-15  Eero Tamminen
+
+	* src/breakcond.c, src/debugui.c, src/falcon/dsp.c, src/falcon/dsp.h,
+	src/includes/debugui.h:
+	support all registers for conditional breakpoints + fix DSP reg name
+	matching
+	[1638a1f3f0f2]
+
+	* src/Makefile, src/debugui.c:
+	integrate breakcond.c & conditional breakpoints with DebugUI and
+	rest of Hatari
+	[c3a9910371bf]
+
+	* src/falcon/dsp.c, src/falcon/dsp.h:
+	move DSP register code to separate GetRegisterAddress function for
+	breakcond.c
+	[94e72d78ab67]
+
+	* src/debugui.c, src/includes/debugui.h:
+	move CPU register code to separate GetRegisterAddress function for
+	breakcond.c
+	[45ae1917865c]
+
+2009-06-14  Eero Tamminen
+
+	* src/breakcond.c:
+	Add BreakCond_Command/Help(), CPU/DSP register parsing support &
+	test code
+	[701192eb7a7b]
+
+	* src/breakcond.c:
+	.size -> .bits (reg support preparation), crosscheck width/mask,
+	make funcs static
+	[d5e8cc3de5c3]
+
+	* src/falcon/dsp_core.h, src/falcon/dsp_cpu.h,
+	src/falcon/dsp_disasm.h, src/falcon/nvram.h, src/gui-win/opencon.h,
+	src/includes/midi.h, src/includes/rtc.h, src/includes/str.h,
+	src/includes/utils.h, src/uae-cpu/hatari-glue.h, src/uae-
+	cpu/savestate.h:
+	add 'extern' keywords to 11 headers (out of the 93) missing them
+	[73c7326779d0]
+
+2009-06-14  Thomas Huth
+
+	* doc/compatibility.html:
+	Added Super Sprint.
+	[f26374ac147b]
+
+2009-06-13  Eero Tamminen
+
+	* src/breakcond.c:
+	trivial test for triggering breakpoints, fix addr size check
+	[f3bc75b64fd5]
+
+	* src/breakcond.c:
+	Except for registers, BC parsing works now. Added parsing function
+	tracing/debug
+	[cda62e4215e9]
+
+	* src/breakcond.c:
+	fix tokenizing crasher, fix breakpoint removal crasher, code
+	tidying:
+	- move comparison matching to its own function
+	- remove use of pstate member aliases argv/arg
+	[a05dc2190037]
+
+2009-06-12  Eero Tamminen
+
+	* src/breakcond.c:
+	initial/buggy size/mask/register parsing (doesn't pass tests),
+	args->argv
+	[b4feacca2e84]
+
+	* src/breakcond.c:
+	use '&&' for boolean AND instead of '&', improved test & error
+	reporting
+	[ae9d8defe818]
+
+	* src/breakcond.c:
+	indicate which parsed arg had the error, test output readability
+	improvements
+	[291e6549d54c]
+
+2009-06-11  Thomas Huth
+
+	* src/gemdos.c:
+	Handle illegal Fseek modes.
+	[6358f1616639]
+
+2009-06-10  Eero Tamminen
+
+	* src/breakcond.c:
+	more parsing and testing functionality, bp listing/removing, var
+	name finetuning
+	[a0460fd47a6c]
+
+2009-06-10  Laurent Sallafranque
+
+	* src/falcon/dsp_cpu.c:
+	removed 2 usued defines
+	[e38e43a8527a]
+
+	* src/falcon/dsp_cpu.c:
+	DSP condition code simplify. Code is easier to read and faster to
+	execute
+	[ab6f61afe0ee]
+
+	* src/falcon/dsp.c:
+	dsp memory dump fix: correct X and Y memory dump in debug mode
+	[17e9cbbafe36]
+
+2009-06-10  Thomas Huth
+
+	* src/gemdos.c:
+	Fixed return value of Fseek when end of file has been reached. TOS
+	returns -64 when a program tries to seek beyond the end of a file.
+	This behavior is now emulated in the GEMDOS HD code of Hatari, too.
+	This fixes the "EOF bug" in the program GFASHELL.
+	[6fac76c656d4]
+
+2009-06-10  Eero Tamminen
+
+	* src/breakcond.c:
+	switch to array of breakpoints having array of conditions, pass
+	(most) parsing args in struct, move test code to end
+	[8cd480bbef70]
+
+2009-06-09  Eero Tamminen
+
+	* src/debugui.c:
+	Expect 'dm' DSP memspace arg to be separated from address. Improve
+	help text.
+	[ca6e50b103f2]
+
+	* src/breakcond.c:
+	"complete" checking side, flesh out parsing code, start on test
+	code, more docs
+	[cb3c5c5d8926]
+
+2009-06-08  Eero Tamminen
+
+	* src/debugui.c:
+	fix: debugger input needs to be trimmed of newline when not using
+	readline
+	[fc1cbb6fae4d]
+
+	* src/breakcond.c:
+	add preliminary code for handling conditional breakpoints
+	[563bfb8807ae]
+
+2009-06-07  Eero Tamminen
+
+	* src/debugui.c, src/falcon/dsp.c, src/falcon/dsp.h,
+	src/includes/debugui.h, src/includes/main.h:
+	Add DSP breakpoints & single stepping + minor DebugUI changes:
+	- Add command shortcut to the main help
+	- Finetune of some of the messages (state whether it's DSP or CPU etc)
+	- Change DSP debug shortcuts back to 2 letters
+	- typedef dbgcommand_t And add likely/unlikely gcc extension macros to
+	main.h & use them in dsp.c when checking for whether to call
+	DebugUI.
+	[58443694fb87]
+
+2009-06-07  Thomas Huth
+
+	* src/debugui.c:
+	Fixed the help text of the 'continue' command.
+	[b5c49fa1ef55]
+
+	* src/debugui.c, src/includes/debugui.h, src/uae-cpu/newcpu.c, src
+	/uae-cpu/newcpu.h:
+	Added simple CPU breakpoint and single-step debugging possibilities.
+	[f6b7b33bf84d]
+
+	* src/log.c:
+	Added 'none' trace option to be able to disable tracing from the
+	debug UI.
+	[8687a80691ea]
+
+2009-06-07  Eero Tamminen
+
+	* doc/hatari.1, doc/manual.html, python-ui/hatari.py, python-
+	ui/hatariui, src/options.c:
+	change sound freq limits to 6000-50066 and explain them in
+	documentation
+	[c3b998d94821]
+
+2009-06-06  Thomas Huth
+
+	* src/debugui.c, src/includes/debugui.h:
+	Reworked debugger command parsing. Commands are now gather in a
+	proper jump table instead of one ugly huge switch() statement.
+	Parameter list is now generated with strtok() so that the commands
+	can easier access them.
+	[298398234a57]
+
+	* src/includes/main.h:
+	Added ARRAYSIZE macro for calculating the size of an array.
+	[da66ef81e05f]
+
+	* Visual.Studio/VisualStudioFix.c, Visual.Studio/VisualStudioFix.h,
+	config-default.h, configure.ac, src/gemdos.c, src/includes/log.h,
+	src/log.c:
+	Renamed HATARI_TRACE_ACTIVATED to ENABLE_TRACING since this naming
+	is more consistant with the other defines from config.h. Also
+	enabled this option by default in config-default.h
+	[d53e422be120]
+
+	* src/gui-sdl/dlgSound.c:
+	Fixed compiler warning about comparison between signed and unsigned
+	[9bbc7539b927]
+
+2009-06-03  Thomas Huth
+
+	* website/links.html:
+	Replaced defunct Pangaelin Willow link with AtariWorld.org
+	[417e1160625d]
+
+2009-06-03  Laurent Sallafranque
+
+	* src/debugui.c, src/falcon/dsp.c, src/falcon/dsp.h:
+	added : dsp memory debug mode. (dm [x,y,p]addr)
+	[eacd30856dac]
+
+2009-06-03  Thomas Huth
+
+	* src/falcon/videl.c:
+	Removed wrong and unused VIDEL_COLOR_REGS_END constant.
+	[ef2ab9b1727b]
+
+2009-06-02  Laurent Sallafranque
+
+	* src/falcon/dsp_cpu.c:
+	simplified and optimized ccr E, U, N, Z computing. One call is
+	suffisant to compute the 4 bits.
+	[cf8241df8eb1]
+
+	* src/falcon/dsp.c:
+	Changed the registers display in dsp debug mode
+	[ac7212190edb]
+
+	* src/falcon/dsp_cpu.c:
+	new code : added read SSH and write management
+	[79a496454120]
+
+2009-06-02  Eero Tamminen
+
+	* doc/compatibility.html:
+	Aazohm needs joypad
+	[c8f75d834d11]
+
+2009-06-01  Eero Tamminen
+
+	* doc/manual.html:
+	add note about --grab and pause to mouse section
+	[61e94eb0172e]
+
+	* doc/hatari.1, doc/manual.html, src/main.c, src/options.c,
+	src/screen.c:
+	add --grab option and release mouse grab when emulation is paused
+	[76f8f4b9cbc6]
+
+	* doc/compatibility.html:
+	cryview doesn't work with TT-emu
+	[66579a94f31d]
+
+	* src/video.c:
+	fix ST colreg address in comment
+	[08aad2778d44]
+
+2009-06-01  Thomas Huth
+
+	* src/ikbd.c:
+	Increase the amount of cycles for sending keyboard data
+	automatically. This fixes the mouse cursor in "Froggies over the
+	fence" and "Dragonnels" demo.
+	[5cc6980b42b8]
+
+2009-06-01  Laurent Sallafranque
+
+	* src/falcon/dsp.c:
+	added PC to dsp debugger
+	[fecec9b10035]
+
+2009-06-01  Thomas Huth
+
+	* src/ikbd.c:
+	The byte which is sent by the IKBD after a reset command has to be
+	delayed by 50000 cycles. Lotus Turbo Esprit 2 now does not crash
+	anymore during its buggy start up sequence.
+	[ef5d7d38c404]
+
+2009-05-31  Eero Tamminen
+
+	* Makefile, python-ui/Makefile:
+	install also python-ui
+	[266bdbbbb153]
+
+	* python-ui/dialogs.py:
+	convert string underlines (interpreted as kbd-shortcuts) to dashes
+	[4dd6ffe7ad2e]
+
+	* python-ui/debugui.py, python-ui/dialogs.py, python-ui/hatari-
+	console.py, python-ui/hatari.py, python-ui/hatariui.py:
+	support arbitrary sound frequency. scripts should be executable
+	[51752f7cfff8]
+
+2009-05-31  Thomas Huth
+
+	* src/dmaSnd.c:
+	Calculate frame position only once instead of two times when playing
+	stereo sound.
+	[95e5a9d63265]
+
+	* src/dmaSnd.c:
+	Scale down DMA samples before mixing with PSG sound so that they are
+	at the same level. The song "On behalf of the Queen" by 505 should
+	now sound better.
+	[e27e82952a01]
+
+	* src/Makefile:
+	Avoid linking the main executable if nothing has been changed at
+	all.
+	[7ee334a132f0]
+
+2009-05-29  Eero Tamminen
+
+	* doc/hatari.1, doc/manual.html, src/options.c:
+	playback frequency can now be set to "any" value, update --sound
+	accordingly
+	[eaabb21ef451]
+
+	* python-ui/hatari-icon.png, python-ui/hatari.png:
+	add missing / necessary images back
+	[68709f44956d]
+
+2009-05-28  Laurent Sallafranque
+
+	* src/falcon/dsp_core.h, src/falcon/dsp_cpu.c,
+	src/falcon/dsp_disasm.c:
+	removed X and Y external ram buffers (gain 64 ko) some code rewrote
+	minor bug fixes
+	[054e541ac3b3]
+
+2009-05-24  Eero Tamminen
+
+	* python-ui/TODO, python-ui/dialogs.py, python-ui/hatari.py:
+	update python-ui TODO, fix Midi config names, update trace flags
+	list
+	[6a9db0e5723d]
+
+2008-10-19  Eero Tamminen
+
+	* python-ui/Changelog, python-ui/TODO, python-ui/dialogs.py, python-
+	ui/hatari.py, python-ui/hatariui.py, python-ui/uihelpers.py:
+	- Implement peripherals dialog
+	- Check sound output file extension as required by Hatari
+	- disk -> floppy dialog
+	- update TODO&Changelog
+	[d98dc87b9415]
+
+2008-09-29  Eero Tamminen
+
+	* python-ui/TODO, python-ui/debugui.py, python-ui/dialogs.py, python-
+	ui/hatari.py, python-ui/uihelpers.py:
+	Implement support for paths and update TODO
+	[0ce48441def7]
+
+2008-09-28  Eero Tamminen
+
+	* python-ui/TODO, python-ui/dialogs.py, python-ui/hatari.py, python-
+	ui/hatariui.py, python-ui/uihelpers.py:
+	- add support for auto frameskip, statusbar and overlay led and
+	simplify the display dialog code a bit
+	- remove support for multiple machine setups now that Hatari config
+	loading (after startup) works, this makes the dialog easier to use
+	- fix memory size setting
+	- other minor changes
+	[eadf8aca0f3a]
+
+2008-08-28  Eero Tamminen
+
+	* python-ui/Changelog, python-ui/TODO:
+	- make changelog more readable
+	- remove Hatari stuff from TODO list (some of is now implemented and
+	rest discussed with Thomas)
+	[aad379ed7f16]
+
+2008-07-30  Eero Tamminen
+
+	* python-ui/hatari-console.py:
+	- support for older Pythons (non-derived class syntax)
+	- check whether Hatari supports --control-socket option
+	- support Hatari remote path setting and device toggling
+	- add hatari-console help
+	[69a5288ff975]
+
+2008-07-26  Eero Tamminen
+
+	* python-ui/Changelog, python-ui/Makefile, python-ui/README, python-
+	ui/TODO:
+	- Moved feature TODOs from source to new TODO file and added there
+	also some issues found from Hatari too + things that Steem has
+	- Added Changelog
+	- README update
+	[727560b53cd6]
+
+	* python-ui/config.py, python-ui/debugui.py, python-ui/dialogs.py,
+	python-ui/hatari.py, python-ui/hatariui, python-ui/hatariui.py,
+	python-ui/uihelpers.py:
+	- Added recanim, recsound, config load/save and memory snapshot
+	load/save features. If config changed in UI, give a temporary
+	config file to Hatari whenever it's re-run
+	- Fullscreen isn't anymore a toggle as user cannot use this option
+	if Hatari is fullscreen... Removed fullscreen config option
+	handling as it will be changed also directly from Hatari
+	- To support drag&drop for the UI, it forwards non-option args
+	(floppy name) to Hatari from the UI command line
+	- Disk image and joystick settings to separate dialogs
+	- Add dummy paths and peripherals settings dialogs
+	- Check that Hatari supports --control-socket argument
+	- Make dialog run() methods more consistent
+	- Python code compatible to Python 2.4 (I'm testing with 2.5 which
+	accepts '()' for classes not inheriting anything) and wrapper
+	scripts to older SH (use exit when outside func body)
+	[492d35446e43]
+
+2008-07-11  Eero Tamminen
+
+	* python-ui/Makefile, python-ui/hatariui, python-ui/hatariui.desktop:
+	add desktop file, minor tweaks
+	[0b4f154621f6]
+
+2008-07-10  Eero Tamminen
+
+	* python-ui/.cvsignore, python-ui/Makefile, python-ui/README, python-
+	ui/hatariui, python-ui/setup.py:
+	- Add Makefile for installing and make script installable
+	- Update README and add .cvsignore for local bytecompiled .py files
+	- remove useless setup.py
+	[8b89b8ff559c]
+
+2008-07-07  Eero Tamminen
+
+	* python-ui/hatariui, python-ui/hatariui.py:
+	fix single row panel with actions
+	[08119e0ee4cc]
+
+2008-07-06  Eero Tamminen
+
+	* python-ui/hatari-ui, python-ui/hatari-ui.py:
+	old UI is now redundant
+	[bee8da661e8d]
+
+	* python-ui/dialogs.py, python-ui/hatariui, python-ui/hatariui.py,
+	python-ui/uihelpers.py:
+	- fix: create_toolbutton utility
+	- fix: make sound settings into a dialog
+	- fix: fastforward & fullscreen initial state in actions
+	- add new hatariui helper script
+	- enable keyboard shortcuts when Hatari isn't embedded
+	- make panels into actions and if user gives any on command line,
+	add them to menu too
+	- close by itself on a row is enough as a button, no need for
+	toolbar + toolitem
+	[2924cd3efb20]
+
+2008-07-05  Eero Tamminen
+
+	* python-ui/hatariui.py:
+	GtkSocket embedding the Hatari window needs to do Gtk focus grab for
+	key events to go to Hatari (at all) when toolbars are used.
+	[28e9210f925c]
+
+	* python-ui/hatariui.py:
+	Large refactoring for the new hatariui.py:
+	- get menus working + option to disable them
+	- converted all buttons to toolbars and toolbar items and it mostly
+	works, but it steals focus from Hatari!
+	- slightly improved Hatari window resize handling
+	[656cf0873578]
+
+2008-07-03  Eero Tamminen
+
+	* python-ui/dialogs.py, python-ui/hatari-ui, python-ui/hatari-ui.py,
+	python-ui/hatariui.py, python-ui/uihelpers.py:
+	- move text/click input buttons to separate dialog
+	- move menu/actions stuff to new hatariui.py file which will
+	eventually replace hatari-ui.py
+	[fbed1df56baf]
+
+2008-07-01  Eero Tamminen
+
+	* python-ui/dialogs.py, python-ui/hatari-ui, python-ui/hatari-ui.py,
+	python-ui/hatari.py:
+	- add borders, st-low zoom and fullscreen options support
+	  - controls for first two to display dialog, fullscreen as
+	action/button
+	- fine-tune dummy menu texts
+	[bd1218b8145f]
+
+	* python-ui/dialogs.py, python-ui/hatari-ui, python-ui/hatari-ui.py:
+	- add dummy (for now) Hatari UI menu
+	- move run-time display settings into dialog of their own as it's
+	impossible to have slider in menu (for frameskip)
+	[6392e4d610d3]
+
+2008-06-26  Eero Tamminen
+
+	* python-ui/hatari.py:
+	better check for required Hatari support
+	[e6db36811654]
+
+	* python-ui/hatari.py:
+	assert that Hatari supports the required --control-socket option
+	[53394dd57397]
+
+2008-06-25  Eero Tamminen
+
+	* python-ui/dialogs.py:
+	- allow user to eject disks in peripherals dialog
+	- support "use HD" option in machine config dialog
+	- in both of these dialogs, batch the changes in one go to Hatari
+	[9df61e51ff51]
+
+	* python-ui/hatari-ui.py:
+	make new Hatari window size reading more robust against Hatari
+	reboots and re-running (previously it could get stuck sometimes when
+	Hatari was asked to reboot itself after re-running Hatari).
+	[f83da3dc70fd]
+
+	* python-ui/config.py:
+	- empty string key values should be shown and saved as "", not
+	"None"
+	[f6cc4bfd3a49]
+
+	* python-ui/hatari.py:
+	- more robustness for the case when user terminates Hatari
+	- support for batching Hatari option changes
+	- support for g/setting floppydir and whether to use HD
+	[7ad0ebf97c65]
+
+2008-06-24  Eero Tamminen
+
+	* python-ui/hatari-ui.py, python-ui/hatari.py, python-ui/uihelpers.py:
+	request and process Hatari window size change messages from Hatari
+	[9686a111db9a]
+
+2008-06-18  Eero Tamminen
+
+	* python-ui/config.py, python-ui/dialogs.py, python-ui/hatari-ui.py:
+	warn if Hatari configuration is missing and bail out
+	[2266d934ae10]
+
+2008-06-16  Eero Tamminen
+
+	* python-ui/uihelpers.py:
+	bump version number
+	[a9d7d64779ec]
+
+	* python-ui/hatari-ui.py:
+	smarter control resize policy
+	[c7372558145f]
+
+2008-06-15  Eero Tamminen
+
+	* python-ui/debugui.py, python-ui/dialogs.py, python-ui/hatari.py,
+	python-ui/uihelpers.py:
+	- "finish" configuration setup dialog and add support for all the
+	required hatari variables
+	- list (in comment) which Hatari variables are not yet supported
+	- disable Hatari internal quit confirmation when starting Hatari
+	[3b8dfceaa4d7]
+
+	* python-ui/hatari-console.py, python-ui/hatari-ui, python-ui/hatari-
+	ui.py:
+	- UI: support taking screenshots
+	- console: add support for "savemem"
+	[80f10c5db6ec]
+
+2008-06-14  Eero Tamminen
+
+	* python-ui/dialogs.py, python-ui/hatari-ui, python-ui/hatari-ui.py:
+	add warm/cold reset/reboot button and dialog
+	[e84454e94777]
+
+2008-06-13  Eero Tamminen
+
+	* python-ui/config.py, python-ui/debugui.py, python-ui/dialogs.py:
+	- fix debugui.py default config value type (without saved config
+	you got exception when trying to switch to disasm or memory dump
+	mode)
+	- hide peripherals dialog faster
+	- correct ConfigStore() constructor __doc__ method
+	[d11eaedd1b9b]
+
+2008-06-11  Eero Tamminen
+
+	* python-ui/dialogs.py, python-ui/hatari.py:
+	fix initial disk name
+	[16a0d6faadc7]
+
+	* python-ui/README, python-ui/dialogs.py:
+	README improvements, note that UI needs saved hatari.cfg
+	[664f3909c53f]
+
+2008-06-10  Eero Tamminen
+
+	* python-ui/debugui.py, python-ui/dialogs.py, python-ui/hatari-ui,
+	python-ui/hatari-ui.py, python-ui/hatari.py, python-ui/uihelpers.py:
+	- move table helper functions from debugui.py to uihelpers.py
+	- adapt to the new Hatari joystick settings option
+	- add handling for the new Hatari disk options
+	- add Hatari peripherals dialog (uses table helpers) and move disk &
+	joystick settings there
+	- refactor hatari.py a bit so that debugui.py can be given options
+	with which it should run Hatari
+	- comment code more
+	[fdb1eadf31d6]
+
+2008-06-08  Eero Tamminen
+
+	* python-ui/hatari-console.py, python-ui/hatari.py:
+	add disk support now that Hatari got options for them
+	[f6b798f96abc]
+
+2008-06-07  Eero Tamminen
+
+	* python-ui/dialogs.py:
+	decided on different/simpler setup dialog structure (still dummy
+	though)
+	[91b3491419b8]
+
+	* python-ui/config.py, python-ui/debugui.py, python-ui/dialogs.py,
+	python-ui/hatari-ui, python-ui/hatari-ui.py, python-ui/hatari.py:
+	- stupid oversight, Hatari configuration has after all sections
+	with keys named the same (shortcut and joystick sections), needed
+	to rewrite config handling to take this into account
+	- added joystick emu selection
+	- apply doesn't close trace settings dialog, only close will do
+	[56be835accd0]
+
+2008-06-06  Eero Tamminen
+
+	* python-ui/hatari-ui, python-ui/hatari-ui.py, python-ui/uihelpers.py:
+	- ">" can be used to put controls in multiple rows/columns
+	- close button allowed only in panels
+	[66dd8855b1e8]
+
+2008-06-03  Eero Tamminen
+
+	* python-ui/dialogs.py, python-ui/hatari-ui.py:
+	- add blitter trace setting
+	- shorten "Spec512 support" checkbox name (now that tooltips work)
+	[cead7a5a4376]
+
+	* python-ui/hatari-console.py, python-ui/hatari.py:
+	- USER isn't always defined, use PID instead in socket/file names
+	[0a8a14745494]
+
+2008-06-02  Eero Tamminen
+
+	* python-ui/dialogs.py, python-ui/hatari-ui, python-ui/hatari-ui.py:
+	small screen / N8x0 improvements
+	- trace options are in three columns, not two
+	- if close button is given for a panel, set its type as dialog
+	[84ea0787f41a]
+
+2008-05-30  Eero Tamminen
+
+	* python-ui/README, python-ui/debugui.py, python-ui/hatari-ui, python-
+	ui/hatari-ui.py, python-ui/uihelpers.py:
+	- add README
+	- allow running the UI and debugger scripts from elsewhere than
+	where the scripts themselves (and icon/logo images) are
+	[fc71ccb1ab75]
+
+2008-05-28  Eero Tamminen
+
+	* python-ui/dialogs.py, python-ui/hatari-ui.py:
+	add support for trace settings loading and saving
+	[fdbc9535c239]
+
+	* python-ui/config.py, python-ui/dialogs.py:
+	- fix cosmetic bugs in config file output (newlines between
+	sections and capitalized True/False)
+	- add checkpointing to configuration and change changed config
+	variable checking/listing to use that. Checkpointing will be
+	useful for Hatari configuration dialogs
+	[ee214fb50318]
+
+	* python-ui/dialogs.py, python-ui/hatari-ui.py, python-ui/hatari.py:
+	code documentation improvements:
+	- prefixing more private methods with "_"
+	- adding docstrings to more public methods
+	[aeee34e6a18c]
+
+2008-05-27  Eero Tamminen
+
+	* python-ui/dialogs.py, python-ui/hatari-ui.py:
+	code cleanup:
+	- add docstrings to methods
+	- prefix internal methods with "_" as is python convention
+	- all dialogs take same __init__ constructor arguments and same
+	number of run() method arguments
+	[6c8a807a4815]
+
+	* python-ui/debugui.py:
+	code cleanup:
+	- don't derive from HatariUIDialog unnecessarily
+	- change helper methods that don't use other class methods or object
+	variables into functions
+	- prefix internal methods with "_" is is python convention
+	- add docstrings to methods
+	[b072ff6ce493]
+
+2008-05-26  Eero Tamminen
+
+	* python-ui/hatari-ui, python-ui/hatari-ui.py:
+	- fix panel button tooltips
+	- another panel example to the hatari-ui script
+	[564bb863b8c0]
+
+	* python-ui/debugui.py, python-ui/dialogs.py, python-ui/hatari-ui.py,
+	python-ui/uihelpers.py:
+	More refactoring inspired by Pylint OO-style warnings:
+	- move common / helper functions from dialogs.py to new uihelpers.py
+	file
+	- add there create_toggle() and create_button() and use these in
+	debugger and hatari UI instead of methods
+	- move class variable constants to their own Constants and UInfo
+	classes, this makes sharing them more explicit
+	- associate HatariControls instead of inheriting it in HatariUI,
+	this makes the class roles more explicit (but there are some less
+	clean things still)
+	- prefix all internal callback methods in HatariControls with "_"
+	(which is a Python idiom)
+	[c9a730067c5a]
+
+2008-05-25  Eero Tamminen
+
+	* python-ui/debugui.py:
+	- refactor address handling to MemoryAddress class from DebugUI
+	class in preparation for additional memory area monitoring windows
+	requested by Nicolas
+	- ask user whether Hatari should be killed instead of just killing it
+	- fix OO-style issues reported by pylint
+	[f873f3288642]
+
+	* python-ui/dialogs.py, python-ui/hatari-ui.py:
+	- fix few errors
+	- move killdailog functionality to dialogs.py so that Debug UI can use
+	it too
+	- make paste timeout callback to a function from method (I'm
+	assuming this guarantees the text paste object is not leaked)
+	- fix OO-style issues reported by pylint
+	[c93b449a3539]
+
+	* python-ui/config.py, python-ui/hatari.py, python-ui/setup.py:
+	- improve documentation (comments)
+	- fix issues reported by pylint
+	- take hatari configuration border settings into account when
+	deciding on Hatari cli option
+	[59459d1d3670]
+
+	* python-ui/hatari-ui, python-ui/hatari-ui.py:
+	- refactor widgets to new HatariUIWidgets class from HatariUI
+	- user can now specify that control are in separate panel windows
+	- updated Hatari frameskip only when users releases mouse button
+	[09ca1c525a93]
+
+	* python-ui/hatari-console.py:
+	- fix TAB completion I broke earlier
+	- fix more pylint warnings (put main code inside a function)
+	[74698a1cfb3f]
+
+	* python-ui/debugui.py:
+	- nicer resizing for dialogs
+	- leave 0x prefix out from addresses in dialogs
+	- kill Hatari on exit
+	[fbfa8dbc287b]
+
+	* python-ui/dialogs.py:
+	UI improvements:
+	- trace settings to two rows
+	- config changes list has scrollbars only when needed
+	[d6932761b57f]
+
+2008-05-24  Eero Tamminen
+
+	* python-ui/debugui.py:
+	- add memory load and save dialogs & functionality
+	- refactor the existing classes for this a bit
+	[a148f18c41ed]
+
+	* python-ui/dialogs.py:
+	add note and question dialogs, some improvements
+	[06780b0a5584]
+
+2008-05-21  Eero Tamminen
+
+	* python-ui/hatari-console.py:
+	- add event and debugger shortcut handling to hatari-console
+	- resolve few pylint warnings
+	[b55f5d6a0f10]
+
+2008-05-20  Eero Tamminen
+
+	* python-ui/config.py, python-ui/debugui.py:
+	config.py:
+	- improve doc strings
+	- enable configuration file saving
+	- create config file on save if it doesn't exits (under ~/.hatari)
+	debugui.py:
+	- read/write Debug UI options from/to configuration file
+	- bind enter to applying options in options dialog
+	[0a79104ae5c9]
+
+	* python-ui/config.py, python-ui/hatari-ui.py, python-ui/hatari.py:
+	Prepare for DebugUI and HatariUI configuration handling:
+	- generalize Hatari configuration handling code and move it to to a
+	new config.py file
+	- split Config class to ConfigStore and ConfigVariables classes
+	- ConfigVariables class makes accessing the configuration variables
+	nicer as they are now class attributes and have proper types
+	instead of being just strings. The code checks/enforces the Hatari
+	types (bool, int, string) on them
+	- ConfigStore class then takes care of loading/saving of
+	configuration and its changes
+	- Renamed ConfigMapping class left to hatari.py into
+	HatariConfigMapping and adapted it to the configuration handling
+	changes
+	[607cc4333fcc]
+
+2008-05-19  Eero Tamminen
+
+	* python-ui/dialogs.py:
+	make changed settings dialog text area size itself sensibly
+	[d74c86889411]
+
+2008-05-17  Eero Tamminen
+
+	* python-ui/debugui.py, python-ui/hatari.py:
+	- use todo and error dialogs in debug UI
+	- add options dialog for number of lines on screen
+	- use different address skips in memdump & disasm modes
+	- get distinct lines from hatari instead of concatenated data
+	- remove "Default" button as useless (when monitor windows are added)
+	and set Registers as default mode (+ get address from PC register)
+	- lots of fixes to how address changes are calculated
+	[da385300c4e2]
+
+	* python-ui/dialogs.py:
+	- add TodoDialog and ErrorDialog
+	- baseclass improvements
+	[63394af0224f]
+
+2008-05-13  Eero Tamminen
+
+	* python-ui/debugui.py:
+	- Support arrow keys and page up/down as Nicolas requested
+	- Added buttons corresponding to page up/down address change
+	- fixed TODO dialog close button
+	- fixed address entry size
+	[421558cf7504]
+
+	* python-ui/debugui.py, python-ui/hatari-ui.py, python-ui/hatari.py:
+	- make debug UI work also as standalone
+	- move Hatari output file open and read from debugui.py to hatari.py
+	[f3744a49335e]
+
+2008-05-11  Eero Tamminen
+
+	* python-ui/debugui.py:
+	remove extra space
+	[5e3c71f3304a]
+
+	* python-ui/debugui.py:
+	when Hatari is stopped again, let Hatari decide from which address
+	to do the disassemble/memdump (hopefully that's PC)
+	[9bdf763029f8]
+
+	* python-ui/debugui.py:
+	- <<, <, >, >> buttons work now
+	- user can set the address also
+	- add button for default address and option
+	- show dialogs for all TODOs
+	[d3744f5a657e]
+
+	* python-ui/debugui.py:
+	- fix debugui startup, try deleting the log file only if it exists
+	- make register dump just one of the dump modes
+	- fix the dump widget to monospace font and make it not to resize
+	the debugui window if the widget is smaller than the available
+	space, only when there's too little space
+	[4b162eb0c9fb]
+
+	* python-ui/hatari-ui:
+	convenience script for launching hatari-ui.py with all options
+	[129e3f12ad94]
+
+	* python-ui/hatari.py:
+	improvements to embed window size option matching
+	[ab111e92c4ec]
+
+2008-05-10  Eero Tamminen
+
+	* python-ui/debugui.py:
+	fix text to monospaced
+	[0fd47415f3fc]
+
+	* python-ui/debugui.py:
+	- add code for reading Hatari debugger output. fifo had problems,
+	but a regular file seems to work as well for now
+	- the window hide/show works now properly and there are labels for
+	showing the debugger output and address, but they need still a lot
+	of fixes and almost none of the buttons do anything yet
+	[733761addf28]
+
+	* python-ui/hatari.py:
+	fix hatari-stop/cont
+	[e60b244afc85]
+
+2008-05-09  Eero Tamminen
+
+	* python-ui/hatari-ui.py:
+	improve text/key insert button tooltips
+	[d8a88a8be675]
+
+	* python-ui/debugui.py, python-ui/hatari-ui.py, python-ui/hatari.py:
+	- add initial dummy debugger UI
+	- instead of using SIGSTOP on Hatari process, use the new hatari-
+	stop and hatari-cont remote commands, this allows Hatari to
+	receive debugging commands while emulations itself is disabled
+	- fix bug from paste dialog refactoring
+	- other minor changes
+	[3cfcdbb78edf]
+
+2008-05-08  Eero Tamminen
+
+	* python-ui/dialogs.py, python-ui/hatari-ui.py:
+	- support inserting strings in addition to keycodes
+	  - refactored code in paste dialog to a class of its own for this
+	- allow user to specify separators between controls
+	- add tooltips automatically to controls
+	- improved help
+	- some other minor changes
+	[e4fc51a5afa9]
+
+2008-05-07  Eero Tamminen
+
+	* python-ui/dialogs.py, python-ui/hatari-ui.py:
+	- do dialog hide in dialog classes instead of caller
+	- add dialog for pasting text to Hatari (after fixing that at Hatari
+	side...)
+	[627f04a4b48b]
+
+2008-05-05  Eero Tamminen
+
+	* python-ui/dialogs.py, python-ui/hatari-ui.py, python-ui/hatari.py:
+	- complete configuration change support for now
+	  - show at exit which configuration options were changed and allow
+	user to select whether to save or discard them
+	- fix frameskip value (Gtk scale widget returns float instead of int)
+	[4786f799493f]
+
+2008-04-30  Eero Tamminen
+
+	* python-ui/dialogs.py, python-ui/hatari-ui.py, python-ui/hatari.py:
+	- refactored all the configuration variable handling/mapping from
+	Hatari and HatariUI classes to the new ConfigMapping class. This
+	way the other classes don't need to know anything about the config
+	variable names etc.
+	  - when Hatari options having corresponding config variable are
+	changed, using ConfigMapping sets the new value also to internal
+	config variables hash
+	- take a copy of the original config vars and add functions for
+	listing what was changed and to revert the changes. These can be
+	used from the QuitSaveDialog
+	- config variable names are uniq, so simplified their handling a
+	bit, section->variable mapping is needed only when saving the
+	configuration
+	[0171c125ceb3]
+
+2008-04-28  Eero Tamminen
+
+	* python-ui/hatari-ui.py:
+	add controls for Spec512 and Sound
+	[7ef6c74e15a1]
+
+	* python-ui/dialogs.py, python-ui/hatari-ui.py, python-ui/hatari.py:
+	start on setup dialog (currently dummy one) and some other minor
+	changes
+	[8e0f2db91d8e]
+
+2008-04-27  Eero Tamminen
+
+	* python-ui/dialogs.py, python-ui/hatari-ui.py:
+	- move all dialogs to their own .py file as separate classes
+	- fix latest command line parsing changes and improve its error
+	messages
+	[388f7e659269]
+
+	* python-ui/hatari-ui.py, python-ui/hatari.py:
+	- add support for buttons that simulate doubleclick, rightclick and
+	keypress (requires my patch from hatari-devel to Hatari)
+	[c27553931493]
+
+2008-04-26  Eero Tamminen
+
+	* python-ui/hatari-ui.glade:
+	removed the glade file too
+	[7b3bf52cd325]
+
+	* python-ui/hatari-ui.py, python-ui/hatari.py:
+	- moved Hatari socket writing from hatari-ui.py to hatari.py
+	- glade doesn't really help that much and gives less control, so I
+	just wrote code for all the dialogs I created earlier with glade
+	and discarded the glade stuff
+	- rewrote how the UI is created; user can now specify all controls
+	in the UI (from the provided set of them) and whether they are at
+	left/right/top/bottom. Got rid of the Shortcuts & HatariUI
+	separation at the same time
+	[bf2e8899173a]
+
+	* python-ui/hatari-ui.py:
+	fix frameskips config var name
+	[41e698aa0e5b]
+
+	* python-ui/hatari-console.py, python-ui/hatari-ui.py:
+	- hatari commands are separated by newlines
+	- add buttons for debug and trace to the UI
+	- add dialog for selecting which tracings options are enabled
+	[9e144b72d869]
+
+2008-04-24  Eero Tamminen
+
+	* python-ui/hatari-ui.py, python-ui/hatari.py:
+	- add UI support for actually controlling hatari when it's running
+	- maxspeed Hatari option was renamed to fast-forward
+	- fix GtkRange stealing Hatari keyboard focus
+	[9427957741ed]
+
+2008-04-22  Eero Tamminen
+
+	* python-ui/hatari-console.py:
+	allow multiple options and their parameters on same line
+	[62b2d79dee3a]
+
+	* python-ui/hatari-console.py, python-ui/hatari.py:
+	socket should be user specific
+	[967da9d6801f]
+
+	* python-ui/hatari-console.py:
+	console, not ui
+	[35eb6c9a2ff7]
+
+	* python-ui/hatari.py:
+	add support for Hatari control socket
+	[ff33ad56a1d0]
+
+	* python-ui/hatari-console.py:
+	This is now about ready:
+	- Added support for all Hatari command line options
+	- Args given when console is invoked are forwarded to Hatari
+	- Hatari is started immediately and console exits if Hatari isn't
+	anymore running
+	[d456f469dccc]
+
+	* python-ui/hatari-console.py:
+	add readline using hatari-console test program
+	[c65500f14987]
+
+2008-03-30  Eero Tamminen
+
+	* python-ui/hatari-ui.py:
+	finish UI side of the first shortcut widgets. (it's best to do some
+	modifications to Hatari to get them actually to do something as
+	synthetizing Hatari shortcut keyevents wouldn't be that reliable)
+	[a7fdc8520d13]
+
+2008-03-29  Eero Tamminen
+
+	* python-ui/hatari.py:
+	fix
+	[e8b50a48fcb6]
+
+	* python-ui/hatari-ui.py:
+	start adding shortcut button support + better command line parsing
+	[085e1b348ac8]
+
+	* python-ui/hatari-ui.py, python-ui/hatari.py:
+	give Hatari options that make best out of the space it's embedded
+	[140ef6fa7561]
+
+	* python-ui/hatari-ui.glade, python-ui/hatari-ui.py, python-
+	ui/setup.py:
+	- about dialog should be dialog and dialogs are not resizable
+	- configure dialog updates
+	- change layout so that hatari container window size is not changed
+	and if it is, resize it
+	  -> TODO: larger window should be OK... (works fine on N810 now)
+	[4abd35d17ce2]
+
+2008-03-12  Eero Tamminen
+
+	* python-ui/hatari.py:
+	remove TODO that's done
+	[42462e006d0c]
+
+2008-03-08  Eero Tamminen
+
+	* python-ui/hatari-ui.py, python-ui/hatari.py:
+	hatari.py:
+	- neither hatari nor config classes are singletons anymore
+	- configuration loading, saving and showing
+	- setting and getting of config key values
+	  - they work as strings as there's no map of the key types like in
+	Hatari itself
+	- when embedding the window, guarantee that emulated machine is
+	either ST or STE to make sure window size will be correct hatari-
+	ui.py:
+	- fix to closing of the UI
+	[6f9781f6e1f7]
+
+2008-03-04  Eero Tamminen
+
+	* python-ui/hatari.py:
+	support different embed window sizes, hatari supports now borders
+	off
+	[7c525f9ad7b6]
+
+2008-03-03  Eero Tamminen
+
+	* python-ui/hatari.py:
+	get correct Hatari config path
+	[d8afba486a1f]
+
+2008-02-25  Eero Tamminen
+
+	* python-ui/hatari-ui.py, python-ui/hatari.py:
+	Embedding of Hatari window is now optional
+	[4d9002828347]
+
+2008-02-23  Eero Tamminen
+
+	* python-ui/hatari-ui.glade, python-ui/hatari-ui.py:
+	add configure dialog for Hatari with non-working content
+
+	(pretty far from working... First is needed conf loading, creating
+	rest of the conf UI in glade, then backend code for that, saving new
+	config, creating suitable Hatari config lines from the configuration
+	in case its not saved etc.)
+	[affbdc70ca17]
+
+	* python-ui/hatari-ui.py, python-ui/hatari.py:
+	* email address
+	* handle window close button & Hatari exit question correctly
+	[bfd5de45075f]
+
+	* python-ui/hatari-ui.py, python-ui/hatari.py:
+	* Refactor Hatari instance and configuration handling to new
+	hatari.py file
+	* Change button orders and change dummy maxspeed button to
+	pause/unpause
+	  * Do Hatari pause/unpause functionality
+	* Add fullscreen option and usage to the UI
+	* Add icon & title back to mainwin
+	* Set Hatari socket widget bg to black and remove bg image stuff
+	* Fix Hatari restart handling
+	[aa348e9f5c84]
+
+	* python-ui/tests/README:
+	update, embedding works
+	[d9eab119b5d4]
+
+	* python-ui/hatari-ui.glade, python-ui/hatari-ui.py:
+	* Mainwin:
+	  - write in python as Glade cannot handle it properly
+	  - remove it from the glade file
+	* Update glade file from glade-2 to glade-3
+	* Add configure and maxspeed placeholder buttons
+	[761c1db11973]
+
+2008-02-22  Eero Tamminen
+
+	* python-ui/hatari-ui.glade, python-ui/tests/pygtk-hatari-embed-
+	test.py:
+	Widget embedding Hatari needs to be GtkSocket (which Glade doesn't
+	support) and CAN_FOCUS needs to be *unset* for any other widgets
+	taking input. Then keyboard works in Hatari.
+	[d05e700b49dd]
+
+	* python-ui/tests/pygtk-hatari-embed-test.py:
+	support testing the Hatari itself embedding and more widgets
+	[090c0e22f5d3]
+
+	* python-ui/hatari-ui.glade, python-ui/hatari-ui.py:
+	some testing changes...
+	[22fc0ec2f17b]
+
+2008-01-27  Eero Tamminen
+
+	* python-ui/hatari-ui.glade, python-ui/hatari-ui.py, python-
+	ui/setup.py, python-ui/tests/README, python-ui/tests/pygtk-hatari-
+	embed-test.py, python-ui/tests/pygtk-hello-world.py:
+	Telling the SDL to embed itself didn't work, neither did work
+	embedding the Hatari window from PyGtk code. Results of these tests
+	are in the tests/ subdirectory.
+
+	I added some "meat" to the hatari-ui and next I'm going to try doing
+	the embedding from the Hatari code itself...
+	[2f971a884306]
+
+	* python-ui/hatari-ui.glade, python-ui/hatari-ui.py, python-
+	ui/setup.py:
+	add original Hatari pygtk UI to CVS
+	[ab9d9e6e207d]
+
+2009-05-24  Eero Tamminen
+
+	* doc/compatibility.html:
+	fix typo
+	[7b4b687ce8c6]
+
+2009-05-24  Thomas Huth
+
+	* src/falcon/videl.c:
+	Clear horizontal scrolling HW registers during reset. This fixes the
+	distorted screen after doing a warm reset in the "Fever week" demo.
+	[a3b8503348b2]
+
+2009-05-22  Eero Tamminen
+
+	* doc/compatibility.html, doc/emutos.txt:
+	compatibility updates. New "TT/Falcon utilities" section
+	[0eed0c8dbef7]
+
+2009-05-21  Thomas Huth
+
+	* website/links.html:
+	Added link to Hatari for the Wii
+	[373580a30a9c]
+
+2009-05-20  Eero Tamminen
+
+	* doc/compatibility.html:
+	more URLs for Falcon games. Couple of extra DSP demos work
+	[21759b081b7b]
+
+2009-05-20  Laurent Sallafranque
+
+	* src/falcon/dsp_cpu.c:
+	Scaling mode added into read_accu (A or B) and limiting improving.
+	This increase a lot ApexJpeg picture rendering (colors are much
+	better now)
+	[6dd935623534]
+
+2009-05-17  Laurent Sallafranque
+
+	* src/falcon/dsp_cpu.c:
+	fix : display correct write value in dsp->host transfer ($FFEB) in
+	debug mode
+	[6d3b2f8835c2]
+
+2009-05-15  Laurent Sallafranque
+
+	* src/falcon/dsp_cpu.c:
+	Optimization in move l: decoding
+	[387817d4a78b]
+
+	* src/falcon/dsp_cpu.c:
+	fix : correct move S,D register masking (this corrects a move a,n5)
+	for example
+	[2c484706bd0d]
+
+2009-05-14  Eero Tamminen
+
+	* configure.ac, doc/manual.html, src/main.c:
+	optionally measure performance using user time (time spent only by
+	Hatari process) which provides
+	*much* more accurate results than the use of SDL_GetTicks() "wall
+	clock".
+	[9b1022403d88]
+
+	* doc/compatibility.html:
+	add Logitron Falcon games to list
+	[227bab467929]
+
+2009-05-13  Eero Tamminen
+
+	* doc/compatibility.html:
+	madness is STe demo, add links to Falcon games + other updates
+	[7f04894eba20]
+
+2009-05-12  Eero Tamminen
+
+	* doc/compatibility.html:
+	some things work now better, update falcon compatibility
+	[225d3d5a2149]
+
+2009-05-06  Laurent Sallafranque
+
+	* src/falcon/dsp.c, src/falcon/dsp.h, src/falcon/dsp_core.c,
+	src/falcon/dsp_core.h:
+	first implementation of SSI receive data. Lot's of code to add here
+	[e227e326e129]
+
+	* src/falcon/dsp.c, src/falcon/dsp_core.c, src/falcon/dsp_core.h,
+	src/falcon/dsp_cpu.c:
+	Temporary fix : reinsert internal detection of frame sync. This
+	should be set by the DMA crossbar. Temporary fix : remove of
+	TX_INTERRUPTION_WITH_ERROR Willie's adventure works again
+	[075b35ec6cec]
+
+2009-05-05  Laurent Sallafranque
+
+	* src/dmaSnd.c, src/falcon/dsp.c, src/falcon/dsp.h,
+	src/falcon/dsp_core.c, src/falcon/dsp_core.h, src/falcon/dsp_cpu.c:
+	rewrite of SSI emulation. Added external frame sync from DMA (pin
+	SC2), prepared receive data
+	[89613911d9f1]
+
+2009-05-03  Eero Tamminen
+
+	* src/debugui.c:
+	check length of string scanf reads to prevent stack smashing, remove
+	redundant code (scanf appends zero) + use standard strchr()
+	[7ba7c4520f9b]
+
+	* website/links.html:
+	fix typo & funet link
+	[fd7285ae3a8e]
+
+2009-05-02  Thomas Huth
+
+	* doc/images/discs.png, doc/images/floppydisks.png,
+	doc/images/harddisks.png, doc/images/main.png,
+	doc/images/newfloppy.png, doc/images/sound.png,
+	doc/images/system.png, doc/manual.html:
+	Updated 'System', 'Floppy', 'Hard disks' and 'Sound' dialog
+	descriptions in the manual.
+	[bfb2b3b7d340]
+
+	* src/gui-sdl/dlgSystem.c:
+	DSP emulation mode can now be chosen in the GUI.
+	[e1a889623eb6]
+
+	* src/configuration.c, src/fdc.c, src/gui-osx/PrefsController.m, src
+	/gui-sdl/dlgFloppy.c, src/gui-sdl/dlgSystem.c,
+	src/includes/configuration.h, src/options.c:
+	Moved the 'Slow down FDC' option from the 'system' configuration
+	section to the 'floppy disk' configuration section (where it belongs
+	to).
+	[758caec3306d]
+
+	* src/gui-sdl/dlgSound.c:
+	Support more sample sound frequencies in GUI.
+	[a9c27faa9da7]
+
+2009-05-02  Laurent Sallafranque
+
+	* src/debugui.c, src/falcon/dsp.c, src/falcon/dsp.h:
+	added : dsp debug set register (option dr reg=value)
+	[acdb65155786]
+
+2009-05-01  Thomas Huth
+
+	* src/audio.c, src/configuration.c:
+	Make sure that nAudioFrequency has always a valid value, also when
+	sound is disabled (thanks to Kåre Andersen for the hint).
+	[c1cec2ff235d]
+
+	* Hatari.xcodeproj/project.pbxproj:
+	Removed araglue.h from Xcode project and enabled DSP emulation.
+	[ee811cc9c7e3]
+
+	* website/links.html:
+	Revised the hyperlinks and added some new links
+	[64a657c5f56a]
+
+2009-05-01  Laurent Sallafranque
+
+	* src/debugui.c, src/falcon/dsp.c:
+	removed the TODO for dsp disasm Eero removed yesterday and I readded
+	by mistake tonight.
+	[fb476efad98a]
+
+	* src/debugui.c, src/falcon/dsp.c, src/falcon/dsp.h,
+	src/falcon/dsp_core.c, src/falcon/dsp_disasm.c:
+	fixed some minor bugs added dsp disasm dump registers (command dr in
+	the debugger) modified dsp disasm program to display correctly
+	instructions in 2 words added some comments
+	[b2135292468d]
+
+2009-04-30  Thomas Huth
+
+	* src/falcon/dsp.c:
+	Made dsp.c compilable again when ENABLE_DSP_EMU is not set
+	[eb140e8c06a2]
+
+	* src/gui-osx/PrefsController.m:
+	Made OS X Prefs compilable again (fixed issue with sound playback
+	frequency variable).
+	[5f6030a47474]
+
+	* src/gui-sdl/dlgFileSelect.c:
+	Use PATHSEP instead of hard-coded (forward) slash.
+	[bbbe5262222c]
+
+2009-04-30  Eero Tamminen
+
+	* doc/release-notes.txt:
+	add more things into devel version release notes
+	[e58c5b92462a]
+
+	* doc/authors.txt:
+	list Laurent's and Kenneth's latest work in authors.txt
+	[c7e916e675b8]
+
+2009-04-29  Eero Tamminen
+
+	* src/debugui.c:
+	DSP disasm completed, remove TODO
+	[40db54c671f3]
+
+2009-04-29  Laurent Sallafranque
+
+	* src/falcon/dsp_core.c, src/falcon/dsp_cpu.c:
+	temporary fix : remove stack pointer management to let Build in
+	Obsolescence "run". It bugs anyway.
+	[38250a0a4700]
+
+	* src/falcon/dsp_core.c:
+	Bug corrected in defines for debugging mode + added
+	DSP_DISASM_HOSTCVR for host commands.
+	[80d6bb442f92]
+
+	* src/falcon/dsp_disasm.c:
+	dsp disasm : change the way traces are displayed. We now display
+	"pc: opcode disassembled_instruction"
+	[3ddae76bdf78]
+
+2009-04-28  Laurent Sallafranque
+
+	* src/falcon/dsp_cpu.c:
+	fixed register masking in parallal move + A and B registers in BCHG,
+	BCLR, BSET, BTST, JCLR, JSCLR, JSEt, JSSET + code optimisations. At
+	least 2 more demos are working : HMMMM and _ demo.
+	[33fb845310f5]
+
+2009-04-26  Eero Tamminen
+
+	* src/debugui.c, src/falcon/dsp.c, src/falcon/dsp.h:
+	make DSP disassembly continue work, use consistent CamelCaps
+	[6d51f52d5174]
+
+2009-04-26  Laurent Sallafranque
+
+	* src/falcon/dsp.c, src/falcon/dsp_disasm.c, src/falcon/dsp_disasm.h:
+	dsp.c added : use of dsp_disasm instruction length to disasemble
+	correctly the memory.
+	[15efd8208354]
+
+	* src/debugui.c, src/falcon/dsp.c, src/falcon/dsp.h,
+	src/falcon/dsp_disasm.c:
+	compil bug correction + added instruction length in DSP disasm code
+	[0f4b1d578fa8]
+
+	* src/debugui.c:
+	Added : DSP debug dd command.
+	[3e115632ea82]
+
+2009-04-26  Thomas Huth
+
+	* src/control.c, src/uae-cpu/build68k.c, src/uae-cpu/gencpu.c:
+	Fixed compiler warnings about ignored return values.
+	[d8bc37558f2c]
+
+	* src/audio.c, src/change.c, src/configuration.c, src/dmaSnd.c, src
+	/gui-sdl/dlgSound.c, src/includes/audio.h,
+	src/includes/configuration.h, src/options.c, src/sound.c,
+	src/wavFormat.c:
+	Directly save audio frequency in configuration structure instead of
+	saving an index into a fixed table. This way it will be easier to
+	support more frequencies later.
+	[485575733677]
+
+2009-04-26  Eero Tamminen
+
+	* doc/hatari.1, doc/manual.html:
+	add --run-vbls to documentation + a section on performance measuring
+	[359af9c50fbe]
+
+	* src/includes/main.h, src/main.c, src/options.c, src/statusbar.c:
+	add simple support for Hatari performance measuring:
+	- count VBLs when fast-forward is used; output speed when Hatari's
+	paused
+	- add option to exit Hatari after given number of VBLs is reached
+	- remove frame-skip max limit (useful with above when skip=VBLs)
+	[4cbfe65d3781]
+
+2009-04-23  Eero Tamminen
+
+	* doc/memory-usage.txt:
+	updated memory usage doc to latest Hatari
+	[177a5c87d1a6]
+
+	* doc/compatibility.html:
+	sonol. demo works, tron2 doesn't always start with dsp
+	[e5816e3aeb2e]
+
+2009-04-22  Laurent Sallafranque
+
+	* src/falcon/dsp_core.c:
+	compil error in DSP trace mode fix
+	[f88ccb556db4]
+
+	* src/falcon/dsp_cpu.c:
+	Fixed again SR register restoring after a DO loop.
+	[da485562a661]
+
+	* src/falcon/dsp_cpu.c:
+	bug fixed in SR restoring at end of do loop. Only bit LF must be
+	restored.
+	[3091cb3404e7]
+
+2009-04-21  Laurent Sallafranque
+
+	* src/falcon/dsp_core.h, src/falcon/dsp_cpu.c, src/falcon/dsp_cpu.h:
+	Fixed stack pointer (push, pull and exception). When dream become
+	reality demo now works.
+	[a0eb8a9a442d]
+
+2009-04-19  Eero Tamminen
+
+	* src/debugui.c:
+	address increase TODOs for DSP stubs
+	[e2d160b1ca5f]
+
+	* src/debugui.c:
+	get rid of compiler warnings and isRange boolean
+	[244f68fd27fe]
+
+	* src/debugui.c, src/falcon/dsp.c, src/falcon/dsp.h:
+	parse DSP addresses for DSP debugger stubs:
+	- generalize range parsing to a new parseRange() function
+	- add range parsing to DSP stubs
+	- improve the parsing error and DSP stubs TODO messages a bit
+	- in the stubs check whether DSP is enabled
+	- add new DSP_GetPC() function for the DSP disassemly stub
+	- add example for outputting DSP regs/disasm/memdump on debugger
+	invoking
+	[2add94104300]
+
+2009-04-19  Laurent Sallafranque
+
+	* src/falcon/dsp_disasm.c:
+	fixed move and movem in debugger + code optimization
+	[110b67c90449]
+
+2009-04-19  Eero Tamminen
+
+	* src/debugui.c:
+	add stubs for DSP debugging commands
+	[0d94c937e429]
+
+	* src/debugui.c:
+	trivial debugger enhancements:
+	- simplify memdumping code by allowing a default address for it
+	- add example+comment for setting disasm/memdump address and
+	outputting them whenever debugger is invoked
+	- do default log setting only once per session
+	[192592ffeac6]
+
+	* doc/compatibility.html:
+	Quickly tested most of the Falcon games & updated info:
+	- moved Capy under TT as it's (supposed) to work there too
+	- hexagon and cavemania regressed
+	- added info on sound to many games
+	- added gemplay & great programs
+	- other updates
+	[d63bb60fa2f3]
+
+2009-04-18  Laurent Sallafranque
+
+	* src/falcon/dsp_cpu.c, src/falcon/dsp_disasm.c:
+	Fixed A and B registers tests in functions xxx_reg( (like
+	jsclr_reg). Solonuminezcenz demo is full working now.
+	[fe321b769ef9]
+
+2009-04-18  Eero Tamminen
+
+	* doc/compatibility.html:
+	Several games and demos started working with Laurent's latest
+	update. Checked which (DSP needing) games/demos have working sound
+	with Thomas' DSP/sound support addition.
+	[0bddb4f9f0ff]
+
+2009-04-17  Eero Tamminen
+
+	* doc/compatibility.html:
+	Compatibility list updates for Laurent's DSP/sound fixes
+	[364de6bf79a6]
+
+2009-04-17  Laurent Sallafranque
+
+	* src/falcon/dsp.c, src/falcon/dsp_core.c, src/falcon/dsp_core.h:
+	Some SSI Code cleaning.
+	[1f674c43c267]
+
+	* src/falcon/dsp_core.c, src/falcon/dsp_core.h, src/falcon/dsp_cpu.c:
+	Double buffering of HostPort Transmit and Receive (TXhml, RXhml,
+	HTX, RTX). Sonoluminezcenz fractal mountains are working now.
+	[e27c36526cc6]
+
+2009-04-17  Eero Tamminen
+
+	* src/options.c:
+	update descriptions for IDE and GEMDOS hd emu options.
+	[389d6c01d98b]
+
+	* src/dmaSnd.c:
+	*DspOut* variables don't need to be global
+	[c08f8d3fd91d]
+
+2009-04-15  Thomas Huth
+
+	* src/falcon/videl.c:
+	Added Videl horizontal fine scrolling for 16 bpp and 32 bpp.
+	[dd88e7c3a694]
+
+	* src/falcon/videl.c:
+	Use default target color depth instead of always 8 bpp for Videl
+	emulation.
+	[e69fdef33e90]
+
+	* src/falcon/hostscreen.c:
+	Fixed Dprintf debugging statements
+	[55c6249a7382]
+
+	* src/falcon/hostscreen.c, src/falcon/hostscreen.h,
+	src/falcon/videl.c:
+	Moved bitplaneToChunky funtion to videl.c and made it static so that
+	compiler can optimize better.
+	[2d3f670f6a47]
+
+2009-04-14  Laurent Sallafranque
+
+	* src/falcon/dsp.c, src/falcon/dsp_core.c, src/falcon/dsp_core.h,
+	src/falcon/dsp_cpu.c, src/falcon/dsp_cpu.h:
+	remove of threaded code.
+	[acee96cea84e]
+
+2009-04-13  Thomas Huth
+
+	* src/falcon/dsp_core.h, src/falcon/dsp_cpu.c:
+	Moved the pc_on_rep variable into the dsp_core_t structure.
+	[742e4ae7b735]
+
+2009-04-12  Thomas Huth
+
+	* src/falcon/Makefile:
+	Fixed build with DSP disabled (ENABLE_DSP_EMU=0)
+	[28cf22dd3723]
+
+	* src/falcon/Makefile, src/falcon/dsp.c, src/falcon/dsp.h:
+	Replaced DSP_EMULATION macro with ENABLE_DSP_EMU
+	[99a16773d922]
+
+	* src/falcon/hostscreen.c:
+	Forgot to remove some remains from araglue.h ...
+	[fc9d076344be]
+
+	* src/dmaSnd.c, src/falcon/dsp.c, src/falcon/dsp.h,
+	src/falcon/dsp_core.c, src/falcon/dsp_core.h, src/memorySnapShot.c:
+	DSP state is now saved to the memory snapshots, too. Also moved to
+	the SSI struct variable into the dsp_core_s structure so that it can
+	be accessed from outside of dsp_core.c, too (needed for saving the
+	SSI data to the snapshots).
+	[8c39afe317e1]
+
+	* src/gemdos.c, src/memorySnapShot.c:
+	Fixed memory snapshot which was broken by new multiple GEMDOS
+	partitions code.
+	[e15d761298ff]
+
+	* src/gemdos.c:
+	Fixed bug in the new single-/multi-partition detection code.
+	[e06154edd641]
+
+	* src/falcon/hostscreen.h:
+	Removed obsolete file araglue.h
+	[b5601cbe997e]
+
+	* src/falcon/araglue.h, src/falcon/dsp.c, src/falcon/nvram.c:
+	Removed obsolete file araglue.h
+	[e611b8cbe1f9]
+
+	* src/falcon/dsp.c:
+	Added proper Doxygen-like function comments.
+	[36f91f5658e0]
+
+	* src/gemdos.c, src/includes/configuration.h:
+	Detect GEMDOS HDD single-/multi-partition mode automatically.
+	[b96e8ea06788]
+
+2009-04-11  Thomas Huth
+
+	* src/falcon/dsp_core.c:
+	Shift DSP SSI data according to word size. First DSP based sound
+	applications are working now (e.g. DSP MOD player from bITmASTER)!
+	[b3f12c4333ae]
+
+2009-04-10  Sébastien Molines
+
+	* src/gui-osx/SDLMain.m, src/gui-osx/Shared.h, src/gui-osx/Shared.m,
+	src/gui-sdl/dlgAlert.c:
+	MacOS: Made alerts always display in Cocoa rather than SDL
+	[a50ff16197d4]
+
+	* src/gui-osx/PrefsController.h, src/gui-osx/PrefsController.m, src
+	/gui-osx/SDLMain.nib/classes.nib, src/gui-osx/SDLMain.nib/info.nib,
+	src/gui-osx/SDLMain.nib/keyedobjects.nib:
+	MacOS: Added IDE HD control in prefs window
+	[c40460cd7f9c]
+
+2009-04-10  Thomas Huth
+
+	* src/uae-cpu/hatari-glue.c:
+	Sourcecode beautification
+	[2df2f71e4ad6]
+
+	* src/gemdos.c, src/includes/configuration.h, src/includes/gemdos.h,
+	src/stMemory.c, src/tos.c, src/uae-cpu/hatari-glue.c:
+	Patch #2713 : Multiple GEMDOS HDD Drives. GEMDOS HD emulation can
+	now support multiple partitions. It's still disabled by default, set
+	MAX_HARDDRIVES in configuration.h to 23 to enable it. Thanks to K.V.
+	Kaufman for the original version of this patch!
+	[673d3403389a]
+
+	* src/scandir.c:
+	Fixed bug in scandir() on Windows. Thanks to K.V. Kaufman for the
+	patch.
+	[bb7f0c96b4e9]
+
+	* src/gemdos.c:
+	Cleaned up superfluous white spaces
+	[0e912a3c92fc]
+
+2009-04-10  Sébastien Molines
+
+	* src/falcon/dsp.c:
+	Fixed build break when DSP_EMULATION is not defined
+	[ee98a33b3cfd]
+
+	* Hatari.xcodeproj/project.pbxproj, src/gui-
+	osx/SDLMain.nib/classes.nib, src/gui-osx/SDLMain.nib/info.nib, src
+	/gui-osx/SDLMain.nib/keyedobjects.nib:
+	MacOS: Updated XCode project, updated prefs dialog to open on 1st
+	tab and tidied it up
+	[d6e0b25bc9af]
+
+2009-04-10  Thomas Huth
+
+	* src/dmaSnd.c:
+	Mix SSI transmit samples into sound output buffer.
+	[3dca3a59b329]
+
+	* src/falcon/dsp.c, src/falcon/dsp.h, src/falcon/dsp_core.c,
+	src/falcon/dsp_core.h:
+	Added interface for reading SSI TX values.
+	[cb2fa4943666]
+
+	* src/falcon/dsp_cpu.c:
+	Silenced compiler warnings
+	[f9167210ffcd]
+
+2009-04-08  Laurent Sallafranque
+
+	* src/falcon/dsp_cpu.c:
+	dsp : bug correct in fast interrupt. HMMM runs better (but still not
+	displays correctly)
+	[46f637376808]
+
+2009-04-07  Laurent Sallafranque
+
+	* src/falcon/dsp_core.c, src/falcon/dsp_cpu.c:
+	dsp : 2 bugs corrected in dsp_jsclr and jsset + 1 bug in ssi code
+	(frame divider value must be incremented by 1) + some code clean up
+	[90a64f433863]
+
+	* src/falcon/dsp_core.c, src/falcon/dsp_cpu.c,
+	src/falcon/dsp_disasm.c:
+	rewrite of dsp opcode decoder and split of many function to increase
+	dsp speed
+	[78197ae22e38]
+
+2009-04-02  Nicolas Pomarede
+
+	* doc/compatibility.html:
+	Update note for "No Buddies Land".
+	[329260f894dc]
+
+	* src/video.c:
+	Add support for another empty line method by switching res hi/lo
+	(fix the game No Buddies Land)
+	[142371d9c9ff]
+
+2009-04-02  Eero Tamminen
+
+	* src/includes/log.h:
+	VC6 fixes from Kenneth for tracing (VC6 doesn't support C99 /
+	variadic macros)
+	[a25a16dbe505]
+
+	* Visual.Studio/VisualStudioFix.c:
+	VC6 fixes from Kenneth for tracing
+	[76cdc8784edf]
+
+2009-04-01  Laurent Sallafranque
+
+	* src/dmaSnd.c, src/falcon/dsp_core.c, src/falcon/dsp_core.h,
+	src/falcon/dsp_cpu.c:
+	First implement of SSI transmit data in network mode. Few more
+	programs which were freezing at startup are running now. Still lot's
+	of code to write.
+	[a21c20b09575]
+
+2009-03-31  Eero Tamminen
+
+	* doc/authors.txt:
+	Move Laurent to developers, add Kenneth as contributor, fix my
+	email.
+	[3244dad9af5f]
+
+2009-03-30  Laurent Sallafranque
+
+	* src/falcon/dsp_cpu.c:
+	Rework of DSP alu opcode decoder to increase speed
+	[c4a1d65f20ec]
+
+2009-03-30  Thomas Huth
+
+	* src/gui-sdl/dlgJoystick.c, src/gui-sdl/dlgScreen.c, src/gui-
+	sdl/dlgSystem.c, src/int.c, src/joy.c, src/shortcut.c:
+	Uses enum types instead of normal integers. (Thanks to K.V. Kaufman
+	for the patch)
+	[eea95cfa165d]
+
+	* src/keymap.c:
+	Fixed simulated SHIFT key modifier. (Thanks to K.V. Kaufman for the
+	patch)
+	[db54d1f88296]
+
+	* src/Makefile:
+	Fixed Makefile for building with MinGW.
+	[77d5f466a555]
+
+2009-03-29  Laurent Sallafranque
+
+	* src/falcon/dsp_core.c, src/falcon/dsp_core.h, src/falcon/dsp_cpu.c:
+	added first (still empty) functions and code for SSI support
+	[9befc816c6cb]
+
+2009-03-29  Thomas Huth
+
+	* doc/compatibility.html:
+	Patch Timer-D must be disabled for Jambala
+	[868da09ca56e]
+
+2009-03-28  Thomas Huth
+
+	* src/change.c:
+	Reset when changing IDE hard disk images
+	[e2930480f92d]
+
+	* website/index.html:
+	Fixed typo in the text of the website. (Thanks to Christoph Fritz
+	for the patch)
+	[9258fca627d5]
+
+	* src/gui-sdl/Makefile, src/gui-sdl/dlgDisk.c, src/gui-
+	sdl/dlgFloppy.c, src/gui-sdl/dlgHardDisk.c, src/gui-sdl/dlgMain.c,
+	src/includes/dialog.h:
+	Split disk dialog into two, one dialog for floppies and one for hard
+	disks. This way there was now enough space in the hard disks dialog
+	to add configuration entries for the IDE hard disk image, too.
+	[6cda61c854d4]
+
+	* src/gui-sdl/dlgMain.c:
+	Reworked main dialog to gain additional space for new buttons.
+	[4d336694d3b2]
+
+2009-03-28  Nicolas Pomarede
+
+	* doc/compatibility.html, doc/release-notes.txt, src/includes/video.h,
+	src/mfp.c, src/video.c:
+	When timer B is in event count mode, add support for start of line
+	events. This very rare mode depends on MFP's AER and allows to
+	trigger a signal when display starts on each active line. (fix Seven
+	Gates Of Jambala by Thalion)
+	[d72baab75803]
+
+	* src/includes/log.h, src/log.c:
+	Add 'io_all' option for --trace
+	[5101bbc00845]
+
+2009-03-27  Thomas Huth
+
+	* src/dmaSnd.c, src/includes/dmaSnd.h, src/includes/int.h, src/int.c:
+	Added framework for DSP transmit timer.
+	[b381efcab1f8]
+
+	* src/dmaSnd.c, src/includes/log.h, src/log.c:
+	Added tracing support for DMA / Falcon sound.
+	[fedb06eefb3c]
+
+2009-03-26  Thomas Huth
+
+	* src/dmaSnd.c, src/includes/dmaSnd.h, src/ioMemTabFalcon.c:
+	Added (still empty) wrapper functions for Falcon sound subsystem.
+	[dc2892aa3ecb]
+
+2009-03-25  Laurent Sallafranque
+
+	* src/falcon/dsp_core.c, src/falcon/dsp_core.h, src/falcon/dsp_cpu.c:
+	DSP interrupts code optimisations.
+	[c6567e2a430d]
+
+2009-03-25  Eero Tamminen
+
+	* doc/manual.html:
+	more info on HD drivers. Instead of HTML list, have separate
+	sections for Mtools and loop device HD image host access.
+	[ec68ff8f75cb]
+
+2009-03-24  Eero Tamminen
+
+	* tools/atari-hd-image.sh:
+	major hd image creation updates:
+	- use "sfdisk" instead of "parted" as for that the partition type
+	can be specified exactly (DOS FAT16, not VFAT)
+	  -> partitions are now compatible with Cecile
+	- Create files originally as sparse to reduce disk churn
+	- More error checks and verbosity
+	- minimum working disk size can be 5MB
+	[51eadd98f313]
+
+2009-03-23  Thomas Huth
+
+	* doc/manual.html:
+	Corrected some typos
+	[757012e03486]
+
+2009-03-22  Eero Tamminen
+
+	* doc/compatibility.html, doc/emutos.txt:
+	Added a couple of working and non-working (Falcon) games.
+	[d3c5fcbeb10b]
+
+	* doc/manual.html:
+	move GEMDOS HD emu first, add new section on accessing HD image on
+	Linux as the last section on hard disk support.
+	[fb998e979134]
+
+	* doc/emutos.txt:
+	2 gem games to emutos list
+	[03b30cca2ffb]
+
+2009-03-21  Eero Tamminen
+
+	* tools/atari-hd-image.sh:
+	check that disk size is sensible, align partition size for mtools
+	[0d219ec5e708]
+
+2009-03-20  Thomas Huth
+
+	* src/ide.c:
+	Removed debugging code (not required anymore).
+	[4bb75a9aea2c]
+
+	* tools/atari-hd-image.sh:
+	Use 'mklabel' command instead of 'mktable' for older versions of
+	'parted'.
+	[1b523b07b50b]
+
+	* doc/compatibility.html:
+	Added Jaguar XJ220 to compatibility list
+	[ca8082ecc121]
+
+	* tools/zip2st.sh:
+	zip2st script does not need 'rename' anymore
+	[321dad1bcaa5]
+
+2009-03-18  Eero Tamminen
+
+	* tools/atari-hd-image.sh:
+	better variable names + partition size sanity check
+	[e5363b15af0b]
+
+	* tools/atari-hd-image.sh:
+	add HD image creation usage examples
+	[9795b4918314]
+
+	* Makefile:
+	more informative Makefile error messages
+	[c3a77387e34a]
+
+2009-03-18  Laurent Sallafranque
+
+	* src/falcon/dsp_cpu.c:
+	dsp code synch with aranym
+	[b8144299f76e]
+
+	* src/falcon/dsp_cpu.c:
+	fix for update Rn with modulo : Modulo mode must take care of
+	multiple buffers when Nx register = modulo
+	[8be9b7fbe77a]
+
+2009-03-18  Eero Tamminen
+
+	* tools/atari-hd-image.sh, tools/zip2st.sh:
+	support POSIX shell syntax subset implemented by Ubuntu's Dash shell
+	[5015f10733e7]
+
+2009-03-16  Thomas Huth
+
+	* .hgignore:
+	Added 'missing' file to ignore list.
+	[68e3d5f82aac]
+
+	* config-default.h, configure.ac, src/file.c:
+	Added test for availability of select() function
+	[f8163f4167b1]
+
+	* Makefile-default.cnf, config-default.h, src/file.c:
+	Some changes for compiling Hatari on the Wii. (based on the patch
+	from Yohanes)
+	[1fb906d9e8e0]
+
+	* src/Makefile:
+	Ensure that Makefile.cnf exists before trying to compile anything.
+	[3361c2e9f336]
+
+2009-03-15  Thomas Huth
+
+	* src/falcon/hostscreen.c, src/falcon/hostscreen.h:
+	Removed unused code and cleaned up.
+	[fa79930577df]
+
+	* src/gui-sdl/dlgAlert.c, src/gui-sdl/dlgDevice.c, src/gui-
+	sdl/dlgDisk.c, src/gui-sdl/dlgFileSelect.c, src/gui-
+	sdl/dlgJoystick.c, src/gui-sdl/dlgKeyboard.c, src/gui-
+	sdl/dlgNewDisk.c, src/gui-sdl/dlgRom.c, src/gui-sdl/dlgScreen.c, src
+	/gui-sdl/dlgSound.c, src/gui-sdl/dlgSystem.c, src/gui-sdl/sdlgui.c,
+	src/main.c, src/psg.c, src/reset.c, src/rs232.c, src/rtc.c,
+	src/scandir.c, src/screen.c, src/screenSnapShot.c, src/shortcut.c,
+	src/sound.c, src/spec512.c, src/st.c, src/statusbar.c, src/str.c,
+	src/tos.c, src/uae-cpu/build68k.c, src/uae-cpu/fpp.c, src/uae-
+	cpu/gencpu.c, src/uae-cpu/memory.c, src/uae-cpu/readcpu.c,
+	src/unzip.c, src/utils.c, src/vdi.c, src/xbios.c, src/ymFormat.c:
+	Replaced obsolete RCS IDs
+	[8916d1d5cd6b]
+
+2009-03-15  Laurent Sallafranque
+
+	* src/falcon/dsp_disasm.c:
+	Sync DSP disasm code from aranym
+	[a577781adf90]
+
+2009-03-13  Thomas Huth
+
+	* src/falcon/dsp_cpu.c:
+	Missing type for parallel move 0
+	[66bd06d31f37]
+
+2009-03-12  Eero Tamminen
+
+	* doc/emutos.txt:
+	4gewinnt compatible with EmuTOS
+	[58630f745787]
+
+	* doc/compatibility.html:
+	Parallel move fix fixes grid on DSP JPEG decoded images.
+	[2b4a84c8a194]
+
+	* src/falcon/dsp_cpu.c, src/falcon/dsp_disasm.c:
+	sync parallel move fix from aranym.
+	[15e357b4268c]
+
+	* src/falcon/dsp_cpu.c:
+	Sync interrupt functions simplification from aranym. Includes also
+	hi interrupt host transmit/receice data interrupt updates.
+	[a857126fca79]
+
+	* src/falcon/dsp_cpu.c:
+	Sync read_memory*() functions simplification from aranym.
+	[659477db055a]
+
+2009-03-11  Thomas Huth
+
+	* src/falcon/dsp_cpu.c:
+	dsp56k: Deal with the JMP in interrupt case
+	[34204469420b]
+
+	* src/falcon/dsp_cpu.c, src/falcon/dsp_disasm.c:
+	dsp56k: Fix case for a X:R parallel move which has nearly same
+	opcode as MOVEP
+	[9777bfde0486]
+
+2009-03-10  Eero Tamminen
+
+	* doc/compatibility.html:
+	Papa Was a Bladerunner uses DSP
+	[baa3bee4d5c0]
+
+2009-03-08  Eero Tamminen
+
+	* doc/compatibility.html:
+	Falcon demo sorting by group like elsewhere. Minor corrections to
+	group names from pouet.net.
+	[2f5fb3035a18]
+
+	* doc/compatibility.html:
+	more falcon demos
+	[e8ee852712a6]
+
+2009-03-07  Eero Tamminen
+
+	* doc/compatibility.html, doc/emutos.txt:
+	Add more TT demos & organize them like other demos. Couple of other
+	minor updates too.
+	[3bc8a8da185d]
+
+2009-03-04  Thomas Huth
+
+	* Visual.Studio/VisualStudioFix.c:
+	Patch #2689: The main() handling on Visual Studio needs some more
+	minor tweaks.
+	[70e4fef0ded3]
+
+2009-03-04  Eero Tamminen
+
+	* tools/atari-hd-image.sh, tools/zip2st.sh:
+	Show user what scripts are doing, do cleanup in exit handler (exit
+	handler is able to do cleanup also in error cases). Also, create
+	harddisk image with single "parted" command.
+	[fff8a2c3543c]
+
+	* tools/atari-hd-image.sh:
+	add initial script for creating a harddisk image
+	[483b197df7f0]
+
+2009-03-03  Thomas Huth
+
+	* src/gui-sdl/dlgAbout.c:
+	Center program name in title dialog
+	[0611bc9eec2b]
+
+	* src/sound.c:
+	Cleaned up white spaces.
+	[84ceddf1abbb]
+
+2009-03-01  Eero Tamminen
+
+	* src/falcon/dsp_cpu.c:
+	separate read_memory_p() function for reading DSP_SPACE_P memory
+	addresses to improve performance.
+	[3683d7d0ffef]
+
+2009-03-01  Thomas Huth
+
+	* src/falcon/dsp_cpu.c:
+	Fixed scaling mode tests
+	[6dae8244f236]
+
+	* src/falcon/dsp_cpu.c:
+	dsp56k: RND instruction properly used with scaling modes. (fix from
+	Laurent Sallafranque)
+	[c4424c71be8d]
+
+	* doc/compatibility.html:
+	Added Exterminator and No Buddies Land
+	[991275dcf8be]
+
+2009-02-28  Thomas Huth
+
+	* tools/zip2st.sh:
+	No need to change file names to uppercase when using
+	MTOOL_NO_VFAT=1. Mtools can be instructed to _not_ create VFAT
+	entries by setting the MTOOL_NO_VFAT environment variable.
+	[aa612eb9ed6a]
+
+	* Visual.Studio/VisualStudioFix.c, src/main.c:
+	Added WinMain handling
+	[0babecf01f61]
+
+	* Visual.Studio/VisualStudioFix.c, Visual.Studio/VisualStudioFix.h:
+	Updated file header with license information
+	[7c1d62fe72b8]
+
+	* config-default.h:
+	Include VisualStudio.h in default config.h
+	[e05fedb3dc6d]
+
+	* Visual.Studio/VisualStudioFix.c, Visual.Studio/VisualStudioFix.h:
+	Added files for compiling with Visual-C. Thanks to Kenneth Kaufman
+	for the patch!
+	[358e51279a85]
+
+	* src/falcon/dsp.c:
+	Assert that dsp_core is always initialized, also without explicit
+	reset.
+	[74e9f851778f]
+
+2009-02-27  Nicolas Pomarede
+
+	* src/includes/video.h, src/video.c:
+	Support 0 byte line when switching hi/lo res on STE (different
+	timing than STF) (fix Lemmings screen in Nostalgic-o-demo)
+	[57654482b592]
+
+2009-02-27  Thomas Huth
+
+	* src/falcon/dsp_disasm.c:
+	Merged DSP disassembler changes from Aranym repository:
+	- Fix register update in parallel move
+	- We really don't care about count on same instruction
+	[16c96a901960]
+
+2009-02-25  Thomas Huth
+
+	* src/falcon/dsp_cpu.c:
+	Small optimization for DSP movec instruction. The sixth bit is
+	always set in the movec instructions, so the code can be simplified
+	a little bit. Thanks to Laurent for the hint!
+	[a696a1a8b125]
+
+2009-02-25  Nicolas Pomarede
+
+	* src/video.c:
+	Correct missing end of line timer B interrupt in the case where
+	display is stopped with a hi/lo switch. (fix flickering raster in
+	Dragon Ball part in Blood disk 2 by Holocaust).
+	[f8bd1e7d7f89]
+
+2009-02-25  Eero Tamminen
+
+	* src/falcon/dsp_core.c, src/falcon/dsp_core.h:
+	make dsp_core_dsp2host & dsp_core_host2dsp static, they're used only
+	in dsp_core.c.
+	[15d7f006ad8c]
+
+2009-02-24  Thomas Huth
+
+	* src/falcon/dsp_cpu.c:
+	Optimized dsp_movec() a little bit. (Thanks to Laurent for the
+	patch)
+	[4cf2cde1293f]
+
+	* src/falcon/dsp_core.c, src/falcon/dsp_core.h, src/falcon/dsp_cpu.c:
+	Removed SCI code (not used on Falcon) and cleaned code. Thanks to
+	Laurent Sallafranque for the patch!
+	[dd8699967ab6]
+
+2009-02-22  Eero Tamminen
+
+	* doc/emutos.txt:
+	tested new Falcon stuff with EmuTOS
+	[9896a6714d19]
+
+2009-02-22  Thomas Huth
+
+	* src/falcon/dsp_cpu.c:
+	dsp56k: write_memory functions use 16 bits addressing, no need to
+	mask or use 32 bits value
+	[075525d24a35]
+
+2009-02-22  Matthias Arndt
+
+	* src/joy.c:
+	Tabified joy.c again
+	[a9c85f1a86e4]
+
+2009-02-22  Thomas Huth
+
+	* src/falcon/videl.c:
+	Mask out unused bits of the resolution registers instead of clipping
+	the resolution artificially.
+	[4e96540d6f0a]
+
+	* src/falcon/dsp_cpu.c:
+	Some trivial optimizations to the read_memory and write_memory
+	functions.
+	[2fcdff19bec0]
+
+	* .hgignore, src/Makefile, src/falcon/Makefile, src/gui-sdl/Makefile,
+	src/gui-win/Makefile:
+	Always execute "make" in the sub-folders. So far the sub-folders
+	were only entered by make when one of the *.c files changed. Now
+	they are always tested, to be able to re-built files also when there
+	has been a change to a header file. To ease this built environment,
+	all object files are now linked into an archive in the subfolders.
+	[b4f4dfd39802]
+
+	* src/falcon/dsp_core.c:
+	Remove FORCE_EXEC hack, should buffer host interface transfers
+	instead
+	[b79513012415]
+
+	* src/falcon/dsp_core.c, src/falcon/dsp_core.h, src/falcon/dsp_cpu.c:
+	dsp56k: Use function pointers also for checking semaphore
+	[682ba84ac738]
+
+2009-02-22  Nicolas Pomarede
+
+	* src/includes/m68000.h, src/mfp.c, src/uae-cpu/newcpu.c, src/video.c:
+	Add better traces for timer B in event count mode.
+	[fb8e82c80bd3]
+
+2009-02-21  Eero Tamminen
+
+	* doc/compatibility.html:
+	add couple of falcon games & demos more and update others
+	[8b0cde312a35]
+
+2009-02-21  Thomas Huth
+
+	* src/change.c:
+	Re-initialize the IDE subsystem if necessary. Thanks to Jerome
+	Vernet for the patch.
+	[b95cde21b946]
+
+	* src/configuration.c:
+	Save the IDE settings to the configuration file, too. Thanks to
+	Jerome Vernet for the patch.
+	[f744bbb4ac7f]
+
+2009-02-21  Eero Tamminen
+
+	* doc/compatibility.html:
+	added couple of falcon demos and names for all groups
+	[45f2172dcf0c]
+
+2009-02-20  Eero Tamminen
+
+	* src/change.c:
+	cosmetic: do both DSP checks the same
+	[70bc76957815]
+
+	* src/statusbar.c:
+	fix assert. SDL_Gui decides font size based on screen+statusbar
+	height
+	[d79c80f86339]
+
+2009-02-19  Matthias Arndt
+
+	* src/configuration.c, src/includes/configuration.h,
+	src/includes/joy.h, src/joy.c:
+	Small joystick handling patch
+
+	- added constants ATARIJOY_BITMASK_UP etc to make code more readable
+	- added configuration option bEnableJumpOnFire2 per joystick
+	- Joystick button 2 can now optionally act as JOY UP instead of
+	pressing SPACE
+	[89c331db884f]
+
+2009-02-18  Eero Tamminen
+
+	* doc/compatibility.html:
+	couple of additional (non-working) demos
+	[b0f616c85378]
+
+2009-02-17  Eero Tamminen
+
+	* doc/compatibility.html:
+	added links to rest of falcon demos and checked their DSP
+	compatibility
+	[91905b9790b0]
+
+	* doc/compatibility.html:
+	more links, demo name corrections
+	[d19786f4718d]
+
+2009-02-16  Eero Tamminen
+
+	* doc/compatibility.html:
+	added some links, newbeat apps work now better with DSP
+	[b8f50848009c]
+
+2009-02-14  Thomas Huth
+
+	* src/falcon/dsp.c, src/falcon/dsp_core.c, src/falcon/dsp_core.h,
+	src/falcon/dsp_cpu.c, src/falcon/dsp_cpu.h:
+	Merged changes from Aranym: Add flag to run with/without thread
+	[61c488b6ec0b]
+
+	* src/scandir.c:
+	INVALID_HANLDE_VALUE is already defined in winbase.h on MinGW, too,
+	so there is no need to re-define it.
+	[a5895e8ff0b4]
+
+	* src/falcon/hostscreen.c, src/falcon/videl.c:
+	Added some sanity screen size checks to the VIDEL emulation.
+	[1f28cff55246]
+
+	* src/falcon/dsp.c:
+	Temporary hack to get ROT3DBMP.PRG and BOUND2.PRG running, too.
+	[fe93c308cea1]
+
+2009-02-13  Eero Tamminen
+
+	* doc/compatibility.html:
+	updated games/demos that work (better) with latest DSP upates
+	[64a84148af16]
+
+2009-02-13  Thomas Huth
+
+	* src/change.c:
+	Only re-initialize the DSP if really necessary
+	[4e564f30474e]
+
+	* src/falcon/dsp_core.c, src/falcon/dsp_core.h, src/falcon/dsp_cpu.c:
+	More DSP patches by Laurent Sallafranque.
+	- Changed C++ comments to normal C style
+	- Removed some debugging code
+	- Preparation of the functions for DMA, SSI and SCI
+	[f41a8b6f3495]
+
+2009-02-12  Thomas Huth
+
+	* src/falcon/dsp.c, src/falcon/dsp.h, src/falcon/dsp_core.c,
+	src/falcon/dsp_core.h, src/uae-cpu/newcpu.c:
+	Glued the new single-threaded DSP code to the 68k CPU emulation
+	[4ff8fe7b11b7]
+
+	* src/falcon/dsp_core.c, src/falcon/dsp_cpu.c:
+	Fixed compiler warnings
+	[429ca01bc56d]
+
+	* src/falcon/dsp_cpu.c:
+	Sourcecode beautification: Changed indentation in dsp_add56 and
+	dsp_sub56
+	[f493646a1b4a]
+
+	* src/falcon/dsp.c, src/falcon/dsp.h, src/falcon/dsp_core.c,
+	src/falcon/dsp_core.h, src/falcon/dsp_cpu.c, src/falcon/dsp_cpu.h,
+	src/falcon/dsp_disasm.c:
+	Big bunch of DSP fixes from Laurent Sallafranque. DSP thread has
+	been removed (will run from main thread), no more Mutex and
+	Semaphores. This should help to get the host interface timing
+	sensitive DSP programs working, too. Also added DSP interrupts.
+	[c23aa941a486]
+
+	* src/change.c:
+	Reverted the last patch (argv can remain const char **) and applied
+	a proper fix for the problem (free() takes a void* as argument)
+	[00d7933c3b6a]
+
+2009-02-13  Nicolas Pomarede
+
+	* src/rs232.c:
+	Fix crash 'division by 0' when timer D data register $fffa25 is 0
+	and rs232 is enabled. A data value of 0 should be interpreted as 256
+	(same as in mfp.c)
+	[2b92a014c1f5]
+
+2009-02-11  Eero Tamminen
+
+	* src/file.c:
+	use matching return type
+	[bf0e678ff536]
+
+	* src/mfp.c:
+	int -> interrupt_id in mfp.c functions calling interrupts
+	[430b4c04dff2]
+
+2009-02-10  Eero Tamminen
+
+	* src/gemdos.c:
+	remove redundant code, check for missing PATHSEP
+	[8ed54bb0e952]
+
+	* src/gemdos.c:
+	"new" is reserved word in C++
+	[6feceb34afa2]
+
+	* src/msa.c:
+	use SDL types in msa.c like code elsewhere does
+	[6dc1cfa5d394]
+
+	* src/scandir.c:
+	replace ifdef with TODO. Code should include correct header,
+	whatever that is for Windows.
+	[02aa27df94a4]
+
+	* src/gemdos.c, src/scandir.c:
+	move INVALID_HANDLE_VALUE where it's needed (Windows code) and
+	define it only if needed (Cygwin, not VC?).
+	[4e1303932aa5]
+
+2009-02-08  Nicolas Pomarede
+
+	* doc/todo.txt:
+	Add note for spec512 mode in mid res.
+	[b3af44cf67af]
+
+	* src/includes/video.h, src/uae-cpu/newcpu.c, src/video.c:
+	Handle a very rare case of simultaneous HBL exceptions. If a pending
+	HBL triggers an exception because SR becomes < $2200, then any new
+	HBL signal occuring during the 56 first cycles used by the 68000 to
+	prepare the exception for this pending hbl should be ignored. (fixes
+	top border flickering in Monster Business and colors flickering in
+	Super Monaco GP)
+	[07bf4fcf2013]
+
+2009-02-08  Thomas Huth
+
+	* src/spec512.c:
+	Fixed Spec512 palette bug that occured when CurrentInstrCycles were
+	not a multiple of 4. This fixes the color bugs in the scroller
+	screen of the Fuzion CD 02.
+	[866e81cb0327]
+
+2009-02-07  Thomas Huth
+
+	* src/gui-sdl/Makefile:
+	Extend list of include paths so that gui-sdl files can find
+	config.h, too.
+	[c004ad225ff3]
+
+	* src/file.c, src/ide.c, src/includes/control.h,
+	src/includes/stMemory.h, src/memorySnapShot.c, src/paths.c,
+	src/stMemory.c, src/zip.c:
+	Cleaned up header file include statements. config.h is now included
+	from main.h, so there is often no need anymore to include it
+	directly from other files.
+	[c5fb5114bb9c]
+
+	* src/includes/main.h:
+	Switched version string back to development string
+	[3ba1a34c6fd6]
+
+	* config-default.h:
+	Define inline to __inline for Visual-C
+	[51c6d792fc19]
+
+	* src/change.c, src/falcon/araglue.h, src/falcon/dsp_core.c,
+	src/file.c, src/gemdos.c, src/gui-win/hatari-winicon.rc, src/ide.c,
+	src/includes/log.h, src/includes/main.h, src/main.c, src/paths.c,
+	src/sound.c:
+	Applied some patches from Kenneth Kaufman to make Hatari better
+	compilable with Visual-C
+	[353a1f354ce0]
+
+	* src/falcon/dsp.c:
+	Replaced call to non-existant function showPC with m68k_getpc()
+	[f0c2dde0081e]
+
+	* src/falcon/nvram.c:
+	Do not redefine debug macro. The D(x) macro is already defined in
+	araglue.h, so there is no need to redefine it in the nvram.c file.
+	[badbfb72b03a]
+
+	* src/falcon/dsp_cpu.c:
+	Fixed parallel X: Y: move "Read S2" register access (thanks to
+	Laurent Sallafranque for the patch)
+	[30c192747154]
+
+2009-02-04  Eero Tamminen
+
+	* doc/emutos.txt, doc/manual.html:
+	Update EmuTOS notes to new Hatari features, improve text
+	[220bc2ddac37]
+
+	* doc/manual.html:
+	Add Thomas' IDE usage instructions to manual with some additional
+	information.
+	[916afea2024f]
+
+	* src/psg.c, src/spec512.c, src/uae-cpu/newcpu.c:
+	';;' -> ';' (clean out extra ';' characters)
+	[5211af90b1e1]
+
+2009-02-03  Thomas Huth
+
+	* website/scrshots6.html:
+	Added more DSP screenshots by Laurent Sallafranque
+	[26405a8a4f18]
+
+2009-01-31  Nicolas Pomarede
+
+	* doc/release-notes.txt, src/includes/video.h, src/mfp.c, src/video.c:
+	Handle a rare case where 'move.b #8,$fffa1f' to start the timer B
+	overlaps the end of line signal. In the case where the write is made
+	just a few cycles before the actual signal for end of line, we must
+	ensure that the write was really effective before the end of line,
+	else we should not generate a timer B interrupt for this line.
+	(fixes Pompey Pirate Menu #57)
+	[dbcb5752a40b]
+
+2009-01-30  Thomas Huth
+
+	* src/falcon/dsp_disasm.c:
+	Replaced sprintf with strcpy to get rid of compiler warnings with
+	newest GCC versions
+	[4fb3ecf5a226]
+
+	* src/hdc.c, src/includes/hdc.h:
+	Added proper error checking for fwrite and fread in the HDC code.
+	[56e19d4f070c]
+
+	* src/wavFormat.c:
+	Reworked WAV recording code. 1) Simplified the writing of the header
+	structure. 2) Bytes per second value was wrong, it's fixed now. 3)
+	Added proper return value checks for all calls to fwrite().
+	[642e98bb94d8]
+
+	* doc/todo.txt:
+	Added DSP emulation TODOs by Laurent Sallafranque
+	[36dbe6688153]
+
+2009-01-29  Jean-Baptiste Berlioz
+
+	* src/blitter.c:
+	fix blitter_fileid and comments overwritten by mistake.
+	[395c57c7e3ec]
+
+2009-01-29  Eero Tamminen
+
+	* configure.ac, src/control.c:
+	Test SDL_config.h presense.
+
+	If SDL_config.h is missing, just assume SDL doesn't support X11.
+	[f9fcdb59f6a9]
+
+	* src/control.c:
+	SDL_config.h isn't always present, include it only if HAVE_X11
+	defined
+	[b083806536a6]
+
+	* src/main.c:
+	ignore all unnecessary events, not just joystick motion
+	[b728a18285f0]
+
+2009-01-28  Thomas Huth
+
+	* src/debugui.c, src/paths.c:
+	Check return values to avoid possible errors.
+	[b01c62e8dc95]
+
+	* website/news.shtml:
+	Display the news from the BerliOS project page, too.
+	[10ec838dae1f]
+
+2009-01-28  Jean-Baptiste Berlioz
+
+	* src/blitter.c:
+	Fix blitter.c version.
+	[b1f24941e3dc]
+
+	* src/blitter.c:
+	Improve blitter implementation and cycles counting.
+	[86ca15e7a297]
+
+2009-01-27  Eero Tamminen
+
+	* doc/compatibility.html, doc/emutos.txt:
+	links to TT demos + TT-highres slideshow. Updates
+	[2bb9b1b5519d]
+
+2009-01-26  Eero Tamminen
+
+	* doc/compatibility.html:
+	update
+	[6433d756212f]
+
+	* src/main.c:
+	Process all motion events before returning from event handler.
+
+	This way analog joystick movements don't slow down Hatari input
+	event processing and emulated mouse behaves more responsively on
+	slow machines (or e.g. under Valgrind).
+	[1ca8ebe2324a]
+
+2009-01-25  Eero Tamminen
+
+	* src/control.c:
+	X11 stuff isn't enough, SDL X11 videodriver is also needed
+	[2da10bf03a1b]
+
+2009-01-24  Nicolas Pomarede
+
+	* src/video.c:
+	Remove test code
+	[b0ebc16ea81b]
+
+	* src/video.c:
+	Better detection of lines with 2 bytes removed on the right by
+	switching to 60 Hz before the end of a 50 HZ line. Some old demos
+	are not restoring 50 Hz immediatly (which could distort the image on
+	some TV/monitor), but at the start of the next line (fixes menu in
+	BBC 10 games compilation).
+	[791a781c0083]
+
+2009-01-24  Eero Tamminen
+
+	* website/docs.html:
+	alsa-midi.txt -> midi-linux.txt rename
+	[c7832763f00f]
+
+	* tools/hatari-local-midi-ring.sh:
+	add usage example
+	[d68cde3eff04]
+
+	* doc/alsa-midi.txt, doc/midi-linux.txt:
+	rename alsa-midi.txt to midi-linux.txt, add contents, better titles
+	[af26b93db51a]
+
+	* doc/images/devices.png, doc/manual.html:
+	update manual devices section
+	[32fabe424170]
+
+2009-01-24 : *** Version 1.2.0 ***
+
+2009-01-24  Thomas Huth
+
+	* doc/release-notes.txt:
+	Updated release-notes for version 1.2.0
+	[cb68d9e26e92]
+
+	* src/gui-sdl/dlgAbout.c:
+	Adjusted About-dialog title (version number is longer nowadays)
+	[a160c28cffca]
+
+	* doc/authors.txt:
+	Added Tobe to authors.txt
+	[97109e1d79f6]
+
+	* doc/local-hatari-midi-ring.sh, tools/hatari-local-midi-ring.sh:
+	Moved MIDI ring shell script to tools folder
+	[ec5ff5914128]
+
+	* src/dialog.c, src/gui-sdl/dlgMain.c, src/gui-sdl/dlgMemory.c,
+	src/includes/dialog.h:
+	Fixed inappropriate "Emulator must be reset..." dialogs when loading
+	memory snapshots. The dialogs occured when loading a memory snapshot
+	with a different machine type than the previous one. To avoid these,
+	the emulator must not do the normal configuration post-processing
+	when loading a memory snapshot.
+	[89be70b9fdff]
+
+	* doc/todo.txt:
+	Updated TODO list.
+	[f595f5da4b71]
+
+	* src/audio.c, src/bios.c, src/blitter.c, src/cart.c, src/cartData.c,
+	src/cfgopts.c, src/configuration.c, src/control.c,
+	src/createBlankImage.c, src/cycles.c, src/debugui.c, src/dialog.c,
+	src/dim.c, src/dmaSnd.c, src/fdc.c, src/file.c, src/gemdos.c,
+	src/hdc.c, src/ikbd.c, src/int.c, src/ioMem.c, src/ioMemTabFalcon.c,
+	src/ioMemTabST.c, src/ioMemTabSTE.c, src/ioMemTabTT.c, src/joy.c,
+	src/keymap.c, src/log.c, src/m68000.c, src/memorySnapShot.c,
+	src/mfp.c, src/msa.c, src/options.c, src/paths.c, src/printer.c, src
+	/uae-cpu/hatari-glue.c:
+	Replaced the obsolete RCSIDs with new file-ID strings
+	[4f62ef3707c1]
+
+	* Info-Hatari.plist, src/gui-osx/English.lproj/InfoPlist.strings:
+	Increased version number in the Mac OS X files to 1.2.0, too
+	[02d5ef64a08e]
+
+	* configure.ac, doc/doxygen/Doxyfile, hatari.spec, readme.txt,
+	src/includes/main.h, src/memorySnapShot.c:
+	Increased version number to 1.2.0
+	[ab6a74b1f638]
+
+	* src/falcon/dsp_cpu.c:
+	dsp56k: Fix decoding for NORM instruction (thanks to Matthias
+	Alles).
+	[63d282ebc118]
+
+2009-01-24  Nicolas Pomarede
+
+	* src/psg.c:
+	No need to test for 'movep', as this already implies byte access ;
+	testing for SIZE_BYTE is enough.
+	[60748ca51e0f]
+
+2009-01-24  Thomas Huth
+
+	* tools/hmsa/Makefile:
+	Use LIBS from main Makefile.cnf
+	[97710f162f97]
+
+	* src/ide.c:
+	Added memalign function for MinGW
+	[a56f7d9fa956]
+
+	* Makefile-MinGW.cnf, src/file.c:
+	select() requires extra header and libws2_32 on MinGW
+	[50d9c2f4e9e6]
+
+2009-01-23  Eero Tamminen
+
+	* doc/release-notes.txt:
+	mention midi option change in release notes
+	[936b6c375ed0]
+
+2009-01-22  Nicolas Pomarede
+
+	* src/video.c:
+	Allow to mix low/mid res lines on the same screen when STE
+	horizontal scroll is used
+	[95ef7304d20a]
+
+2009-01-21  Nicolas Pomarede
+
+	* doc/release-notes.txt:
+	Update release notes for 1.2
+	[a6b349946167]
+
+	* src/video.c:
+	Implement STE horizontal scroll using $ff8264/65 for medium res too.
+	(fixes cool_ste.prg from http://www.atari-
+	forum.com/viewtopic.php?f=5&t=15795#p137656)
+	[e0f04de6f8fe]
+
+	* src/video.c:
+	Update comment
+	[bb75889b4563]
+
+2009-01-21  Eero Tamminen
+
+	* src/gui-sdl/dlgDisk.c, src/shortcut.c:
+	fix potential zip_path leak
+	[3e717d4e6d9c]
+
+	* doc/compatibility.html, doc/manual.html:
+	err, 1.2, not 1.3
+	[443ddef9cbe7]
+
+	* doc/hatari.1, doc/manual.html:
+	update midi/rs232/ide option docs
+	[b553686af78c]
+
+	* doc/compatibility.html:
+	version update: devel -> 1.2/1.3
+	[0ae9bfac6ea9]
+
+	* doc/alsa-midi.txt, doc/local-hatari-midi-ring.sh:
+	update for midi option changes
+	- separate options for input and output
+	- add example on how to create a local midi ring with fifos
+	[8071f5dc579d]
+
+	* src/midi.c:
+	try open only if filename, error dialog if open fails
+	[b8b1795b3436]
+
+	* src/options.c:
+	Replace midi/rs232 options with separate input & output options.
+	Remove redundant change comments & update fileid string.
+	[9267a283c741]
+
+	* src/file.c:
+	special-case empty filename
+	[16df9ea66a7b]
+
+2009-01-20  Eero Tamminen
+
+	* tools/hmsa/Makefile, tools/hmsa/hmsa.c:
+	include Makefile.cnf, fix warning
+	[f670b872f288]
+
+2009-01-19  Eero Tamminen
+
+	* src/floppy.c, src/includes/floppy.h:
+	Floppy_EjectBothDrives() can be static, PhysicalSector functions
+	don't exist, log about disk flush on Eject.
+	[0504bf5d33fc]
+
+2009-01-18  Thomas Huth
+
+	* tools/zip2st.sh:
+	Restrict disk image sizes to Atari ST compatible ones.
+	[cbce42fb2566]
+
+	* src/ide.c:
+	Cleaned up IDE code.
+	- Declared local variables as static.
+	- Removed unused code.
+	- Rewrote the Init and UnInit functions to only (de-)allocate
+	ressources if really necessary.
+	[632579d64f93]
+
+	* src/floppy.c, src/includes/floppy.h:
+	Fixed ugly bug that could write data to the wrong disk image. When
+	exchanging floppy disk images, and the old image has been modified,
+	Hatari accidentially wrote the old image to the new file, thus
+	destroying the new image.
+	[9728630c7e12]
+
+2009-01-18  Eero Tamminen
+
+	* doc/alsa-midi.txt:
+	update/correct midi networking instructions
+	[5aad3a1ad4f4]
+
+2009-01-18  Nicolas Pomarede
+
+	* src/includes/video.h, src/uae-cpu/hatari-glue.c, src/video.c:
+	Add the function Video_Reset_Glue(). When the 68000 RESET
+	instruction is called, the GLUE chip responsibles for generating the
+	H/V sync signals should be reset, which means video freq and video
+	res should be set to 0 (fixes Pompey Pirate 44 which jump to the
+	start of the tos and expect the resolution to be set to low res, not
+	mid res)
+	[70dd352e89dd]
+
+2009-01-16  Thomas Huth
+
+	* src/midi.c:
+	Do not consider it as fatal anymore when the MIDI input file can not
+	be opened.
+	[765aa8904021]
+
+2009-01-16  Nicolas Pomarede
+
+	* src/video.c:
+	Handle a special "strange" case when writing only to the upper byte
+	of the color reg (instead of writing 16 bits at once with .W/.L). In
+	that case, the byte written to address x is automatically written to
+	address x+1 too. So : move.w #0,$ff8240 -> color 0 is now
+	$000 move.b #7,$ff8240 -> color 0 is now $707, not
+	$700 ! move.b #$55,$ff8241 -> color 0 is now $755
+	($ff8240 remains unchanged)
+	[bb853f7e7fb8]
+
+2009-01-16  Thomas Huth
+
+	* src/change.c:
+	Re-initialize MIDI subsystem if user has change MIDI settings.
+	[9937ef203026]
+
+	* src/midi.c:
+	ACIA GPIP bit is now emulated for the MIDI input, too. This fixes
+	Oxyd 2 in MIDI two player mode.
+	[04e709013704]
+
+	* Makefile.cnf.in:
+	Added missing INSTALL_SCRIPT variable
+	[cdbb660c700b]
+
+2009-01-13  Eero Tamminen
+
+	* doc/compatibility.html, doc/release-notes.txt, doc/todo.txt:
+	note that MIDI input works now
+	[87990958bdea]
+
+2009-01-13  Thomas Huth
+
+	* src/midi.c:
+	Fixed MIDI output emulation. If the second bit in the MIDI ACIA
+	status register is set, this means that the transfer register is
+	empty, _not_ that it is full. This fixes the sound output problems
+	with "Sequencer ONE" for example.
+	[d2d97c8d0916]
+
+2009-01-12  Eero Tamminen
+
+	* doc/alsa-midi.txt, src/midi.c:
+	updates about GUIs & fixed sound SW issues
+	[5bdbbf815a26]
+
+2009-01-12  Thomas Huth
+
+	* configure.ac, src/ide.c:
+	Added autoconf test for malloc.h (it's not available on all systems)
+	[a715a992d992]
+
+2009-01-11  Eero Tamminen
+
+	* tools/zip2st.sh:
+	use suitable disk size, more error checks, exclude .zip from .st
+	name
+	[a57c0fd5c845]
+
+2009-01-10  Thomas Huth
+
+	* configure.ac, src/ide.c:
+	Added autoconf tests for posix_memalign, memalign and valloc
+	[5ac0d1f31756]
+
+2009-01-09  Thomas Huth
+
+	* src/ide.c:
+	ENOMEDIUM was not defined on Mac OS X
+	[6b6f38ff09cf]
+
+2009-01-07  Thomas Huth
+
+	* src/ide.c:
+	Support read-only IDE hard disk images, too.
+	[8999884be039]
+
+2009-01-10  Thomas Huth
+
+	* src/gui-osx/PrefsController.m:
+	Fixes to make the OS X GUI compilable again.
+	[b5037cf442f0]
+
+2009-01-09  Thomas Huth
+
+	* config-default.h:
+	Avoid to re-define BIN2DATADIR. On Mac OS X, BIN2DATADIR is already
+	defined in the XCode project file, so it should not be defined in
+	config.h again.
+	[2d49ec0c4911]
+
+	* src/falcon/dsp_cpu.c:
+	dsp56k: Cleanup for MOVEC instruction parameter decoding
+	[cba3d8ab0541]
+
+2009-01-06  Eero Tamminen
+
+	* Makefile, Makefile-default.cnf:
+	install zip2st
+	[8ad784574afb]
+
+	* src/reset.c:
+	add midi.h include to fix compile warning
+	[fa750f3970f6]
+
+2009-01-05  Eero Tamminen
+
+	* website/links.html:
+	link to Hatari UI page + update on my page desc
+	[ece1ccce0dea]
+
+	* website/index.html:
+	n770,n800,n810
+	[2c1c1724f2d6]
+
+	* website/docs.html:
+	- libpng is optional, development files are needed for building
+	- more notes about things to configure to get more performance
+	[61f5daf11021]
+
+	* etc/README:
+	note about paths in n810.cfg
+	[4a9a00f16d68]
+
+	* doc/alsa-midi.txt:
+	add Debian package names and link to kaconnect
+	[0f3c9ba5bf0b]
+
+2009-01-05  Thomas Huth
+
+	* src/ide.c, src/includes/ide.h, src/main.c:
+	Added IDE hard disk emulation. The code is based on the IDE
+	emulation code of QEMU. Tested successfully with AHDI 6, Cecile and
+	HD-Driver demo version, however partitioning seems only to work with
+	Cecile so far.
+	[0aa2196d97cc]
+
+	* tools/zip2st.sh:
+	Fix access rights after unpacking since .zip files created with
+	STZip sometimes have the rights messed up
+	[2c09bdc31988]
+
+	* src/configuration.c:
+	Allow special file names for RS232 emulation, too.
+	[97a53484dd03]
+
+2009-01-04  Thomas Huth
+
+	* tools/zip2st.sh:
+	Added a simple script for converting .ZIP files into .ST disk
+	images.
+	[f453ff6ac1e1]
+
+2009-01-03  Thomas Huth
+
+	* src/gui-sdl/dlgDevice.c:
+	MIDI input can now be configured in the GUI, too.
+	[b933fd402a86]
+
+2009-01-01  Thomas Huth
+
+	* src/configuration.c, src/control.c, src/includes/configuration.h,
+	src/includes/int.h, src/includes/midi.h, src/int.c, src/midi.c,
+	src/options.c, src/reset.c:
+	Added basic MIDI input support.
+	[425a961bd2a6]
+
+	* src/file.c, src/includes/file.h:
+	Added a new function which can be used to poll a file descriptor for
+	input.
+	[922cb75dc394]
+
+2008-12-31  Thomas Huth
+
+	* doc/alsa-midi.txt:
+	Added information about how to use soundcards with built-in MIDI
+	synthesis capability
+	[4580e079f856]
+
+2008-12-29  Thomas Huth
+
+	* website/contact.html:
+	General update of the contact web page.
+	[8a3fa6b7e0ca]
+
+	* doc/authors.txt:
+	Replaced '@' character with 'at' to confuse spam-bots
+	[44bf905b1326]
+
+	* doc/compatibility.html, doc/manual.html:
+	Fixed HTML code so that it passes the HTML validator again.
+	[46ee1c8e8e24]
+
+	* website/backgnd.png, website/contact.html, website/docs.html,
+	website/download.html, website/favicon.ico, website/hatari-
+	small.png, website/hatari.css, website/hatari.png,
+	website/index.html, website/links.html, website/news.shtml,
+	website/scrshots.html, website/scrshots1.html,
+	website/scrshots2.html, website/scrshots3.html,
+	website/scrshots4.html, website/scrshots5.html,
+	website/scrshots6.html:
+	The website is now tracked in the HG repository, too.
+	[a0efc9e93050]
+
+2008-12-29  Jean-Baptiste Berlioz
+
+	* src/blitter.c, src/cycles.c, src/spec512.c:
+	improve blitter timings improved blitter timings when accessing
+	hardware registers.
+	[4f5ac6ad2a21]
+
+2008-12-29  Thomas Huth
+
+	* doc/todo.txt:
+	HBLs have now been disabled in VDI extended resolution mode, thus
+	removing the corresponding item from the TODO list.
+	[8dd0823686e1]
+
+2008-12-28  Thomas Huth
+
+	* src/uae-cpu/newcpu.c:
+	Do not continuesly call main event handler when CPU has been
+	stopped. When the emulated CPU was stopped, Hatari used up to 99% of
+	the resources of the host CPU because Main_EventHandler was called
+	continuesly. This has now been removed since it was also not
+	required anymore.
+	[909b04e93755]
+
+2008-12-27  Thomas Huth
+
+	* src/ikbd.c, src/includes/ikbd.h, src/includes/int.h, src/int.c,
+	src/video.c:
+	Introduced a new Int event handler which takes care of sending
+	keyboard, joystick and mouse events regularly. This way the IKBD
+	code is now independend from the HBL and VBL timings (on which it
+	depended before).
+	[5f7b3e42e756]
+
+	* src/mfp.c, src/video.c:
+	Disabled HBL emulation in extended VDI resolution mode for better
+	performance.
+	[c8440d223814]
+
+	* src/includes/log.h, src/ioMem.c, src/log.c:
+	Added traces for generic IO memory accesses.
+	[da220d747c4d]
+
+2008-12-26  Thomas Huth
+
+	* src/falcon/dsp_cpu.c:
+	More dsp56k fixes (from the Aranym repository): Immediate value for
+	REP is 12bit wide. Simplified REP and DO instruction parameter
+	decoding.
+	[b49cbba9c4df]
+
+2008-12-26  Nicolas Pomarede
+
+	* src/video.c:
+	On ST/STE, set unused bits to 1 when reading $ff820a.
+	[76a55836b2a2]
+
+	* src/video.c:
+	On ST/STE, set unused bits to 1 when reading $ff8260 (fix Awesome
+	Menu 16)
+	[422d0df3257d]
+
+2008-12-26  Thomas Huth
+
+	* src/ikbd.c:
+	Fixed IKBD mouse + joystick enabling during IKBD reset time. If only
+	joystick reporting has been enabled during reset time, the mouse is
+	not turned on, too. Now both sensitive games are working right,
+	Barbarian 1 and Super Cars II.
+	[ca7492cecad9]
+
+	* .cvsignore, src/.cvsignore, src/falcon/.cvsignore, src/gui-
+	sdl/.cvsignore, src/uae-cpu/.cvsignore, tools/hmsa/.cvsignore:
+	Removed old .cvsignore files
+	[15fc6b07ccdb]
+
+	* .hgignore:
+	Added more generated files to the .hgignore list.
+	[4363b80a4640]
+
+	* .hgignore:
+	Extended .hgignore file
+	[8035836146b9]
+
+	* hatari.spec:
+	Changed URL from sourceforge.net to berlios.de
+	[a3878f0177c2]
+
+2008-12-23  Nicolas Pomarede
+
+	* doc/compatibility.html:
+	Add note for Illusion Demo by Dune.
+	[193f7aa2ec27]
+
+2008-12-22  Thomas Huth
+
+	* src/ikbd.c:
+	Fixed fire button problem in 'New Zealand Story' and added some more
+	trace debug output.
+	[eea4fb4bf961]
+
+2008-12-21  Nicolas Pomarede
+
+	* src/blitter.c, src/cycles.c, src/includes/m68000.h, src/m68000.c,
+	src/spec512.c:
+	Add a simple BusMode variable to store when the bus is owned by the
+	blitter (for better cycle accuracy when the blitter accesses video
+	registers).
+	[8fd466ed996c]
+
+	* src/includes/fdc.h:
+	Update comment : hbl -> cpu cycles
+	[84657579fd42]
+
+	* src/includes/psg.h, src/ioMemTabFalcon.c, src/ioMemTabST.c,
+	src/ioMemTabSTE.c, src/ioMemTabTT.c, src/psg.c:
+	Better emulation of read/write accesses to $ff8801/03 (fixes music
+	in the game X-Out).
+	[f68f588beac1]
+
+2008-12-20  Nicolas Pomarede
+
+	* src/uae-cpu/newcpu.c:
+	Typo in comment
+	[abcfcd83ec66]
+
+	* src/uae-cpu/newcpu.c:
+	Faster evaluation for 'while' in m68k_run_1
+	[d6c34d200823]
+
+2008-12-20  Nicolas Pomarede
+
+	* src/includes/log.h, src/log.c, src/psg.c:
+	Change trace types for read/write access
+	[2025b1a9ab2b]
+
+2008-12-20  Thomas Huth
+
+	* doc/compatibility.html, doc/manual.html, src/gui-osx/SDLMain.m:
+	Changed the URL from hatari.sourceforge.net to hatari.berlios.de
+	[ef8e17f0f47c]
+
+	* doc/authors.txt, tools/hmsa/readme-hmsa.txt:
+	Updated my e-mail address
+	[de856335e45a]
+
+2008-12-19  Thomas Huth
+
+	* doc/fr/hatari.1, doc/hatari.1, readme.txt:
+	Changed the URL from sourceforge.net to berlios.de
+	[1ea96b7976f8]
+
+2008-12-15  Nicolas Pomarede
+
+	* src/fdc.c, src/includes/fdc.h:
+	Add a dummy function for the type III command Read Address which set
+	status as if the command succeeded (but does nothing in fact). Fix
+	loader routines used in Pompey Pirates compilations (23, 27, ...)
+	that uses Read Address only to update the status register.
+	[92e123a23cb2]
+
+	* src/mfp.c:
+	Add trace when reading gpip in $fffa01
+	[9303debc1250]
+
+2008-12-14  Eero Tamminen
+
+	* doc/compatibility.html:
+	VGA slideshow works now (some issues are still there, but they could
+	be bug in the program, not Hatari...)
+	[6cc356cec16b]
+
+2008-12-14  Nicolas Pomarede
+
+	* src/spec512.c:
+	Improve cycle position when writing to color registers (by comparing
+	with a real STF). This should give less artefacts with multipalettes
+	pictures (fix Froggies Over The Fence Main Menu).
+	[410fe08cf34c]
+
+	* src/video.c:
+	Remove no more used variable.
+	[f690fe8d7eef]
+
+	* src/uae-cpu/newcpu.c:
+	No need to check for pending interrupt in m68k_run_1 if the cpu is
+	in STOP state, this will be handled in do_specialties() (else, the
+	call to do_specialties_interrupt() could acknowledge the int too
+	soon and prevent exiting the STOP state). Fix regression introduced
+	in 2008/12/11 for Oh Crickey's hidden screen by ULM.
+	[4670f94b1738]
+
+2008-12-13  Nicolas Pomarede
+
+	* src/blitter.c:
+	Small change on NFSR by Tobé
+	[c3feee8716db]
+
+	* doc/compatibility.html:
+	No more crash in Mindbomb's 3D Balls screen since Hatari 1.1.0
+	[77f13249f224]
+
+2008-12-13  Eero Tamminen
+
+	* doc/compatibility.html, doc/emutos.txt:
+	Wolf3D (even v0.8a) has started to work both with GEMDOS HD emu and
+	EmuTOS
+	[10f542325c1c]
+
+2008-12-12  Eero Tamminen
+
+	* doc/compatibility.html:
+	- As far as I can see, Next:Illusion screen doesn't have issues
+	anymore (due to latest Blitter updates I assume)
+	- Utopos statusbar doesn't flicker anymore for v1.12 demo nor v1.61
+	full version as it did earlier. I was able to get latter to flicker
+	once, but couldn't repeat it and the v1.50 demo statusbar still
+	flickers, but I assume those are bugs in the programs, not Hatari.
+	[9bb9826cb2a4]
+
+2008-12-12  Nicolas Pomarede
+
+	* doc/compatibility.html:
+	Suretrip 49% by Checkpoint and digi-sound in Swedish New Year's TCB
+	screen are now OK.
+	[6cc7aa2a1ccc]
+
+2008-12-12  Thomas Huth
+
+	* src/blitter.c, src/includes/blitter.h, src/ioMemTabFalcon.c,
+	src/ioMemTabST.c, src/ioMemTabSTE.c:
+	Improved blitter emulation from Tobé:
+
+	This new code try to emulate the internal blitter processes as
+	described in the official documentation. It does not perform any
+	operation if it's not necessary, so it doesn't need a cycle table,
+	the timings are accurate because the logic is accurate. The
+	registers are kept up to date, the words-per-line never reach zero,
+	and the source and destination registers are incremented as
+	described in the docs. When started with 0 in either words-per-lines
+	or lines-per-block, the value stored in these registers is set to
+	65536.
+	[ba8cbab3da98]
+
+2008-12-11  Nicolas Pomarede
+
+	* src/includes/mfp.h, src/mfp.c, src/uae-cpu/newcpu.c:
+	Return TRUE of FALSE in MFP_CheckPendingInterrupts() instead of
+	void. Create do_specialties_interrupt() to check only the special
+	flags related to MFP/video interrupts and factorize some code. When
+	testing for simultaneous interrupts, call do_specialties_interrupt()
+	not do_specialties().
+	[2fb5c83c8a8a]
+
+	* src/includes/main.h:
+	Change window's title from 1.1.0 to devel
+	[0e81594ffcf5]
+
+2008-12-10  Nicolas Pomarede
+
+	* src/video.c:
+	Add 4 cycles tolerance for the 60/50 switch used to produce a 0 byte
+	line.
+	[73b0becf4327]
+
+	* src/memorySnapShot.c:
+	Change version number. Latest snapshots are no more compatible with
+	1.1.0
+	[75d589785f53]
+
+	* src/includes/video.h, src/uae-cpu/newcpu.c, src/video.c:
+	Much more accurate behaviour for HBL/VBL : handle 8 cycles HBL/VBL
+	jitter as on a real STF and allow VBL to interrupt HBL 312 at the
+	same point as on STF too. Fix Fullscreen in Suretrip 49% by
+	Checkpoint and digi sound in Swedish New Year's TCB screen.
+	[cc80273b5fbc]
+
+2008-12-01  Thomas Huth
+
+	* Hatari.xcodeproj/project.pbxproj:
+	Added missing files to OS X target
+	[171b0a9a5f7f]
+
+2008-11-29  Nicolas Pomarede
+
+	* doc/compatibility.html:
+	European Demos by Overlander won't run if HD emulation is ON
+	[f9764c21b319]
+
+2008-11-29 : *** Version 1.1.0 ***
+
+2008-11-29 12:29  Thomas Huth
+
+	* Info-Hatari.plist, configure.ac, hatari.spec,
+	  doc/doxygen/Doxyfile, src/memorySnapShot.c,
+	  src/gui-osx/English.lproj/InfoPlist.strings, src/includes/main.h:
+	  Increased version number to 1.1.0
+
+2008-11-29 12:21  Thomas Huth
+
+	* readme.txt, doc/authors.txt, doc/release-notes.txt: Updated docs
+	  for version 1.1.0
+
+2008-11-28 22:26  Thomas Huth
+
+	* etc/: README, win-ce.cfg: Added win-ce.cfg file for Hatari on
+	  Windows Mobile devices
+
+2008-11-28 22:02  Thomas Huth
+
+	* doc/emutos.txt: Rearranged paragraphs and wordings a little bit,
+	  and corrected debug section.
+
+2008-11-28 18:54  Thomas Huth
+
+	* src/floppy.c: Fixed the bug that floppy B: was not ejected and
+	  saved at exit when floppy A: was also inserted.
+
+2008-11-27 21:17  Eero Tamminen
+
+	* doc/compatibility.html: latest DSP changes improved Bad Mood
+	  graphics a lot, but made the game *much* slower (at least to
+	  react to user input).
+
+2008-11-26 21:26  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Merged changes from Aranym repository: More
+	  fixes from Laurent Sallafranque.  - Fix calculation of overflow
+	  bit in add56/sub56.  - Fix registers S2,D2 for TCC instruction.
+
+2008-11-25 22:25  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Fixed dsp_div calculation. Thanks to
+	  Laurent Sallafranque for the patch.
+
+2008-11-25 22:17  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Fixed SR calculation in LSL and LSR of the
+	  DSP56k emulation. Thanks to Laurent Sallafranque for the patch.
+
+2008-11-25 21:51  Thomas Huth
+
+	* src/: configuration.c, joy.c, includes/configuration.h: Enable
+	  the real joystick by default now instead of the
+	  joystick-with-cursor-keys emulation.
+
+2008-11-24 21:46  Eero Tamminen
+
+	* doc/manual.html: minor tweaks
+
+2008-11-23 20:21  Eero Tamminen
+
+	* doc/manual.html: simplify/clarify the joyemu paragraphs
+
+2008-11-23 16:09  Thomas Huth
+
+	* doc/manual.html: Updated some more obsolte sections in the manual
+
+2008-11-23 13:49  Eero Tamminen
+
+	* doc/: manual.html, images/devices.png, images/discs.png,
+	  images/sound.png, images/tos.png: - crop all screenshots to have
+	  just the dialog content + update their   sizes accordingly.  make
+	  them floats unless they're longer than   the associated text -
+	  PNG screenshot support - minor platform list update - build
+	  instructions updates - fix "--trace help" - re-order/clarify fsel
+	  text a bit - improve frameskip explanation - be explicit about
+	  the sound record file name extension effect - shortcut
+	  explanations improvements + consistency - joy keys are
+	  configurable - emphatize GEMDOS emu issue
+
+2008-11-23 13:44  Eero Tamminen
+
+	* doc/: compatibility.html, emutos.txt: - note about dynabusters+
+	  screen flicker - add sudoku to emutos lists & sort ST program
+	  names like others are
+
+2008-11-23 13:13  Nicolas Pomarede
+
+	* doc/release-notes.txt: Some improvements were made for STE video
+	  registers
+
+2008-11-23 12:49  Nicolas Pomarede
+
+	* src/: sound.c, includes/sound.h: Bye bye old sound core :)
+
+2008-11-23 12:43  Eero Tamminen
+
+	* doc/images/memory.png: old memory screenshot missed autosave
+	  checkbox, update
+
+2008-11-23 12:36  Eero Tamminen
+
+	* doc/hatari.1: fix: --trace help
+
+2008-11-23 11:48  Thomas Huth
+
+	* doc/manual.html: Updated the screen and keyboard dialog and the
+	  GEMDOS HD sections.
+
+2008-11-23 11:27  Thomas Huth
+
+	* src/: main.c, control.c: Silenced debug output in normal log mode
+
+2008-11-23 10:48  Thomas Huth
+
+	* doc/compatibility.html: DMA sound is distorted in 'Systematic
+	  error' demo
+
+2008-11-22 19:21  Eero Tamminen
+
+	* src/shortcut.c: - Boss key also pauses emulation (so that Hatari
+	  CPU use and sound stop) - Pause&unpause emulation before&after
+	  disk dialog as is done for options - Unpause emulation for
+	  warn&cold reset
+
+2008-11-22 18:04  Eero Tamminen
+
+	* src/main.c: Not safe to ignore events.  Seems to stop also SDL
+	  processing them internally, not just propagating them to the
+	  application.	By default SDL enables all events execpt for
+	  SYSWMEVENT, so setting the event states can be just removed.
+
+2008-11-22 17:01  Thomas Huth
+
+	* Hatari.xcodeproj/project.pbxproj: Cleaned up the Xcode project
+	  file a little bit.
+
+2008-11-22 16:59  Thomas Huth
+
+	* src/gui-osx/: PrefsController.h, PrefsController.m,
+	  SDLMain.nib/classes.nib, SDLMain.nib/info.nib,
+	  SDLMain.nib/keyedobjects.nib: Fixed the 'Load config' and 'Save
+	  Config' buttons and removed the non-working Spec512 Slider from
+	  the OS X GUI.
+
+2008-11-22 15:31  Thomas Huth
+
+	* src/gui-osx/: PrefsController.m, Shared.m: Made the OS X GUI
+	  compilable again.
+
+2008-11-22 11:43  Thomas Huth
+
+	* src/gui-osx/SDLMain.m: Removed the obsolete screen snapshot FPS
+	  parameter also from the OS X GUI.
+
+2008-11-21 22:27  Eero Tamminen
+
+	* doc/compatibility.html: finetuning
+
+2008-11-21 22:14  Eero Tamminen
+
+	* doc/: compatibility.html, emutos.txt: more things found working
+
+2008-11-21 19:28  Eero Tamminen
+
+	* src/gui-sdl/sdlgui.c: dialog processing should ignore all motion
+	  events
+
+2008-11-20 22:46  Eero Tamminen
+
+	* src/: main.c, screen.c: Move event selection from screen.c to
+	  main.c and ignore unneeded events.  Fixes internal GUI
+	  fileselector CPU usage with analog joysticks (that haven't been
+	  properly centered) that caused it to constantly poll doDialog().
+
+2008-11-20 22:34  Eero Tamminen
+
+	* src/keymap.c: Ignore empty keymap file names (Keymap_Init() calls
+	  Keymap_LoadRemapFile() unconditionally).
+
+2008-11-19 00:17  Thomas Huth
+
+	* src/dmaSnd.c: Decrement nMwTransferSteps _before_ writing the
+	  registers in DmaSnd_InterruptHandler_Microwire(). If not the
+	  shifting finished 8 cycles too late compared to a real STE.
+	  (Thanks to David Savinkoff for the hint)
+
+2008-11-18 22:14  Eero Tamminen
+
+	* etc/: README, n810.cfg: Use directories that exist already and
+	  are user visible in the normal 770/N8x0 UI.  Remove irrelevant
+	  settings.
+
+2008-11-18 21:12  Eero Tamminen
+
+	* src/gui-sdl/dlgNewDisk.c: Fix the case when the configured disk
+	  path doesn't end in slash.
+
+2008-11-18 21:10  Eero Tamminen
+
+	* src/gui-sdl/dlgFileSelect.c: * Use File_DirExists() instead of
+	  statting directly.
+
+	  * Handle existing path with non-existing file better. Earlier
+	  File	 selector moved to CWD in this case, now it keeps in the
+	  directory and   just suggest the given filename.
+
+	    This doesn't change the normal Hatari behaviour as Hatari paths
+	    default to CWD, but it helps packages providing Hatari config
+	  files
+	    with pre-defined file save paths.
+
+2008-11-18 20:57  Eero Tamminen
+
+	* src/: file.c, includes/file.h: add File_DirExists() function
+
+2008-11-18 20:56  Eero Tamminen
+
+	* src/keymap.c: Use more correct File_Exists() in
+	  Keymap_LoadRemapFile() instead of File_DoesFileNameEndWithSlash()
+	  and give warning &return also when that check fails & indent rest
+	  of the function appropriately.
+
+2008-11-18 20:53  Eero Tamminen
+
+	* src/: shortcut.c, gui-sdl/dlgDisk.c: remove redundant
+	  File_DoesFileNameEndWithSlash() calls as File_Exists() already
+	  checks that the given thing isn't a directory.
+
+2008-11-18 00:13  Nicolas Pomarede
+
+	* src/uae-cpu/newcpu.c: Improve interrupts' precision when multiple
+	  ints happened at the same time during the STOP instruction (HBL
+	  could be wrongly delayed of 4 cycles)
+
+2008-11-17 23:13  Nicolas Pomarede
+
+	* doc/compatibility.html: Add the No Cooper demo to the STF list
+
+2008-11-16 20:02  Eero Tamminen
+
+	* doc/: release-notes.txt, todo.txt: More TODOs done by Thomas
+
+2008-11-16 19:52  Eero Tamminen
+
+	* doc/compatibility.html: - According to pouet.net Badger isn't STE
+	  demo so remove it from list - Tribute to Rainbow Tos works now
+	  fine
+
+2008-11-16 19:01  Thomas Huth
+
+	* doc/compatibility.html: Updated V8 music demo and Songs Of The
+	  Unexpected
+
+2008-11-16 17:27  Eero Tamminen
+
+	* doc/compatibility.html, src/ikbd.c: - Thomas' Utopos fix fixed
+	  also DB2000 - Added pouet.net links + some other minor updates
+
+2008-11-16 16:48  Thomas Huth
+
+	* src/gui-sdl/dlgFileSelect.c: Do not show hidden files by default
+
+2008-11-16 15:56  Thomas Huth
+
+	* gpl.txt: Updated license text to the latest version of the GPL 2
+	  (from http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt)
+
+2008-11-16 15:51  Eero Tamminen
+
+	* doc/: manual.html, images/fileselector.png, images/keyboard.png,
+	  images/screen.png: update fileselector, screen and keyboard
+	  screenshots
+
+2008-11-16 15:21  Eero Tamminen
+
+	* doc/: hatari.1, manual.html: Update command line options and
+	  keyboard shortcuts.  Use hatari.1 HTML version of command line
+	  options also for manual.html
+
+2008-11-16 11:23  Thomas Huth
+
+	* src/gui-sdl/dlgScreen.c: Removed unused FPS code in the screen
+	  dialog
+
+2008-11-16 11:19  Thomas Huth
+
+	* src/: screen.c, video.c, falcon/videl.c, falcon/videl.h,
+	  includes/screen.h: Recording an animation now also works in TT
+	  and Falcon mode.
+
+2008-11-16 10:42  Thomas Huth
+
+	* src/: configuration.c, screenSnapShot.c, shortcut.c,
+	  gui-sdl/dlgScreen.c, includes/configuration.h,
+	  includes/screenSnapShot.h: Removed the obsolete nFramesPerSecond
+	  setting - it is possible to use the frame-skip option instead.
+
+2008-11-15 22:53  Thomas Huth
+
+	* src/: configuration.c, shortcut.c, includes/configuration.h:
+	  Added shortcut for inserting floppy disk A:
+
+2008-11-15 22:02  Thomas Huth
+
+	* src/ikbd.c: If both, joystick and mouse, are enabled, always
+	  report button as mouse event. This is needed for the game 'Big
+	  Run'
+
+2008-11-15 21:41  Thomas Huth
+
+	* doc/: hatari.1, fr/hatari.1: Replaced ~/.hatari.cfg with
+	  ~/.hatari/hatari.cfg
+
+2008-11-15 21:39  Thomas Huth
+
+	* doc/compatibility.html: Added 'Death of the left border' and
+	  'Swedish new year' demos
+
+2008-11-15 21:03  Thomas Huth
+
+	* src/gui-sdl/dlgKeyboard.c: The 'Disable key repeat in fast
+	  forward mode' option can now be configured in the SDL GUI.
+
+2008-11-15 20:04  Thomas Huth
+
+	* src/change.c: When looking for a disk change, check also for a
+	  change within a ZIP file
+
+2008-11-15 19:55  Thomas Huth
+
+	* src/: floppy.c, gui-sdl/dlgDisk.c, includes/floppy.h: Removed the
+	  obsolete EmulationDrives[].szFileName since the floppy file name
+	  is now stored in the ConfigureParams structure.
+
+2008-11-15 16:37  Nicolas Pomarede
+
+	* src/video.c: Fix regression introduced in rev 1.125 that affected
+	  Braindamage Demo.
+
+2008-11-15 15:17  Thomas Huth
+
+	* src/: dmaSnd.c, int.c, includes/dmaSnd.h, includes/int.h:
+	  Shift/rotate the microwire registers automatically within 16
+	  usec. This fixes the hang at the end of the 2nd screen in the
+	  Paradox XMAS 2004 demo.
+
+2008-11-15 15:00  Nicolas Pomarede
+
+	* src/: ioMemTabFalcon.c, ioMemTabSTE.c, ioMemTabTT.c: Add specific
+	  handler for register $ff820d (video screen low)
+
+2008-11-15 14:58  Nicolas Pomarede
+
+	* src/video.c: More traces for STE registers
+
+2008-11-15 11:00  Thomas Huth
+
+	* src/blitter.c: Improved blitter timings (thanks to Tobé for the
+	  patch)
+
+2008-11-15 10:42  Thomas Huth
+
+	* src/change.c: The emulator must be reset when the user changes
+	  the size of the RAM
+
+2008-11-13 23:57  Eero Tamminen
+
+	* doc/compatibility.html: Utopos works with Thomas latest change
+
+2008-11-13 23:14  Thomas Huth
+
+	* src/ikbd.c: Hack for the he game Utopos (>= v1.5): It expects the
+	  joystick data to be sent within a certain amount of time after
+	  the IKBD_Cmd_ReturnJoystickAuto command, without checking the
+	  ACIA control register first
+
+2008-11-13 22:16  Thomas Huth
+
+	* src/dmaSnd.c: Do not reset the microwire data register shifting
+	  index when a program continuesly writes to the data register.
+	  This fixes the initial problem with the X-Mas 2004 demo by
+	  Paradox.
+
+2008-11-12 23:46  Eero Tamminen
+
+	* etc/: README, n810.cfg: add etc/ subdirectory for device specific
+	  configuration files
+
+2008-11-12 23:08  Eero Tamminen
+
+	* src/gui-sdl/dlgFileSelect.c: If fileselector is given
+	  non-existing path, use CWD instead of just not showing the file
+	  select at all (user doesn't understand it, especially as there's
+	  no warning/error about it).
+
+2008-11-12 23:06  Eero Tamminen
+
+	* src/configuration.c: User should be given warning if
+	  configuration changes saving fails.
+
+2008-11-12 21:36  Eero Tamminen
+
+	* src/str.c: Thomas noted that indexed accesses are slower (I had
+	  to check the assembler output to believe that GCC really cannot
+	  better optimize indexed accesses in functions that don't call
+	  other functions with pointers) and that without them he prefers
+	  use of while loops so changing functions closer to what they were
+	  earlier.  Sorry for the code churn.
+
+2008-11-10 20:23  Nicolas Pomarede
+
+	* src/mfp.c: Non important typo
+
+2008-11-10 01:13  Thomas Huth
+
+	* src/ikbd.c: Fix for Utopos: Reset internal joystick state so that
+	  a new joystick packet is send each time the ReturnJoystickAuto
+	  command is send to the IKBD
+
+2008-11-10 00:25  Thomas Huth
+
+	* src/main.c: Fixed crash that occured when pressing F12 in Falcon
+	  mode: Statusbar tried to update the SDL surface with
+	  Screen_Draw(), but this function can only be used in ST/STE mode.
+
+2008-11-09 21:20  Eero Tamminen
+
+	* src/main.c: take into account that options key might be
+	  configured only with a modifier key or not at all.
+
+2008-11-09 21:04  Eero Tamminen
+
+	* src/main.c: User can configure options key (F12) to something
+	  else, ask SDL for the key name (this uses the previous "str-funcs
+	  return a string" change).
+
+2008-11-09 21:02  Eero Tamminen
+
+	* src/: str.c, includes/str.h: - Str_Trunc() doesn't need to zero
+	  rest of string, ending it is enough - str functions return the
+	  modified string.    This allows for nicer code in caller  - make
+	  code more idiomatic C (for loops instead of whiles)...
+
+2008-11-08 00:18  Eero Tamminen
+
+	* doc/compatibility.html: oops, fix
+
+2008-11-08 00:08  Eero Tamminen
+
+	* doc/compatibility.html: comment updates + link to froggies demo
+
+2008-11-07 23:30  Thomas Huth
+
+	* src/: cartData.c, cart_asm.s: Check 0x601A program header magic
+	  before trying to load and execute a program from the GEMDOS
+	  harddisk. Hatari now no longer crashes when trying to Pexec a
+	  file that was not a valid PRG.
+
+2008-11-07 23:17  Nicolas Pomarede
+
+	* doc/compatibility.html: More pouet.net links and sort STF demos
+
+2008-11-06 22:35  Eero Tamminen
+
+	* doc/compatibility.html: - Game updates from Matthias & Thomas &
+	  my own testing - Demo status updates and new demos checked by
+	  Nicolas - Started changing ST demos to be listed according to
+	  group like STE ones - Added pouet.net links some STE demos and
+	  demos Nicolas listed - Armada demos are actually Agression...
+
+2008-11-05 19:23  Thomas Huth
+
+	* src/joy.c: Left + Right (and Up + Down) can't be enabled at the
+	  same time. This patch fixes the crashes in Robocop 2.
+
+2008-11-04 22:05  Eero Tamminen
+
+	* src/: configuration.c, screen.c, includes/configuration.h: Make
+	  also top border configurable and add sanity checks for border
+	  values.
+
+2008-11-04 21:59  Eero Tamminen
+
+	* doc/compatibility.html: - ST games to alphabetical order - next
+	  release is 1.1 (1.? -> 1.1) - checked sound issues in noise
+	  tracker / powerup
+
+2008-11-04 21:39  Eero Tamminen
+
+	* doc/: authors.txt, compatibility.html, release-notes.txt: -
+	  compatibility list updates from Nicolas - draft list of changes
+	  for release notes - update authors list
+
+2008-11-03 23:29  Nicolas Pomarede
+
+	* src/spec512.c: Removed unused modifications ; correct fix for the
+	  palette problem on the 1st line is in video.c >= 1.127
+
+2008-11-03 21:48  Thomas Huth
+
+	* src/gemdos.c: Do not intercept GEMDOS trap calls to the printer
+	  anymore. All printer data is now handled in hardware emulation.
+	  Thanks to David Savinkoff for the patch.
+
+2008-11-03 21:46  Thomas Huth
+
+	* src/: mfp.c, psg.c, includes/mfp.h: Add Falcon Centronics ACK
+	  interrupt capability (Thanks to David Savinkoff for the patch).
+
+2008-11-03 21:24  Thomas Huth
+
+	* src/: bios.c, xbios.c: Removed obsolete BIOS interception code.
+
+2008-11-03 20:34  Thomas Huth
+
+	* src/video.c: The first palette must be saved at the beginning of
+	  the very first visible line, not at the end. This fixes the
+	  graphical glitches that appear in the Coreflakes demo in the very
+	  first visible line on the screen.
+
+2008-11-02 23:18  Thomas Huth
+
+	* src/uae-cpu/memory.c: Call SDL_Quit() before exit() to make sure
+	  that the old video mode is restored properly
+
+2008-11-02 17:27  Eero Tamminen
+
+	* Makefile: install also "hmsa"
+
+2008-11-02 17:06  Eero Tamminen
+
+	* doc/compatibility.html: - More accurate list of Molz issues from
+	  Anders - Some updates to current emulation state
+
+2008-11-02 16:28  Thomas Huth
+
+	* src/: configuration.c, includes/screen.h: Allow up to 47 lines in
+	  the bottom border (but use only 45 by default since some demos
+	  show garbage in the last 2 lines)
+
+2008-11-02 16:19  Thomas Huth
+
+	* src/screen.c: Fixed STScreenEndHorizLine initialization
+
+2008-11-01 17:53  Nicolas Pomarede
+
+	* src/spec512.c: Revert previous patch for now, not the correct
+	  solution to this bug, more work needed
+
+2008-11-01 16:25  Nicolas Pomarede
+
+	* src/spec512.c: Fix a long standing bug : the 1st visible line of
+	  the screen could have a wrong palette (fix Text Zoomer in Core
+	  Flakes demo by New Core)
+
+2008-10-30 21:25  Eero Tamminen
+
+	* doc/: compatibility.html, emutos.txt: minor finetuning for EmuTOS
+	  texts, add DHS "More or Less Zero" demo
+
+2008-10-30 20:01  Eero Tamminen
+
+	* src/includes/control.h: Control_CheckUpdates() returns now bool,
+	  se define needs too
+
+2008-10-29 21:41  Thomas Huth
+
+	* src/includes/stMemory.h: Fixed crash that occured with GEMDOS HD
+	  emulation when ENABLE_SMALL_MEM was set. The STRAM_ADDR macro did
+	  not distinguish between ST-Ram and ROM/IO memory yet.
+
+2008-10-29 21:12  Eero Tamminen
+
+	* src/log.c: exit() -> return, trace options can nowadays changed
+	  at run-time so exit() is wrong (and returning FALSE is handled
+	  correctly by options.c calling this).
+
+2008-10-28 21:43  Eero Tamminen
+
+	* Makefile-default.cnf: add arch specific optimization flag
+	  examples
+
+2008-10-28 21:37  Eero Tamminen
+
+	* src/dialog.c: forgot to commit this with other
+	  Main_PauseEmulation() changes
+
+2008-10-28 21:24  Eero Tamminen
+
+	* src/Makefile: make ENABLE_DSP_EMU overridable with env variable +
+	  update its comment
+
+2008-10-27 22:44  Eero Tamminen
+
+	* doc/: emutos.txt, todo.txt: split Hatari TODOs to emulation and
+	  other todos and remove things that have already been done.
+
+2008-10-26 23:39  Eero Tamminen
+
+	* src/: change.c, control.c, main.c, screen.c, shortcut.c,
+	  statusbar.c, includes/main.h, includes/statusbar.h: - don't show
+	  paused message when switching between fullscreen/windowed mode
+	  -> add option to PauseEmulation() for this - get rid of paused
+	  message faster when unpausing   -> change AddMessage() timeout
+	  from secs for msecs - some comment updates
+
+2008-10-26 20:15  Eero Tamminen
+
+	* src/: control.c, main.c, includes/control.h: Get back into
+	  battery saving (remote) pause (not SDL one) if such had been
+	  requested.
+
+2008-10-26 12:06  Eero Tamminen
+
+	* src/control.c: have link to actual bug in comment
+
+2008-10-26 01:29  Eero Tamminen
+
+	* src/statusbar.c: - more accurate name: .timeout	->
+	  .expire - add .expire member to message to clear the code -
+	  fix the message timeout when there are multiple messages
+
+2008-10-26 00:34  Nicolas Pomarede
+
+	* src/sound.c: Save/restore all variables used by the new sound
+	  engine in Sound_MemorySnapShot_Capture
+
+2008-10-26 00:32  Eero Tamminen
+
+	* src/debugui.c: add missing newline
+
+2008-10-26 00:31  Eero Tamminen
+
+	* src/uae-cpu/newcpu.c: remove duplicate bEnableDebug check
+
+2008-10-26 00:20  Eero Tamminen
+
+	* src/statusbar.c: Cannot assert if screen size doesn't match
+	  requested one as in fullscreen mode Hatari may not get the
+	  requested size.  If available video mode is smaller, disable
+	  statusbar; if larger, re-calculate variables.
+
+2008-10-25 23:25  Nicolas Pomarede
+
+	* src/sound.c: Use doxygen style comments for functions
+
+2008-10-25 22:55  Eero Tamminen
+
+	* src/control.c: - Use Main_Un/PauseEmulation() for stopping the
+	  emulation more cleanly - Add Control_GetUISocket() and check the
+	  X socket for events so that	Hatari window expose events can be
+	  processed even when the remote UI   has asked Hatari/SDL to be
+	  completely stopped (to save battery) - ControlSendEmbedInfo ->
+	  bSendEmbedInfo
+
+2008-10-25 22:31  Eero Tamminen
+
+	* src/: main.c, shortcut.c: - Debug "UI" should do clean
+	  pause/unpause too
+
+2008-10-25 22:19  Eero Tamminen
+
+	* src/: configuration.c, main.c, shortcut.c,
+	  includes/configuration.h, includes/main.h: - Pause key acts as
+	  "pause" unless --debug is used when it invokes   the Debug UI
+
+2008-10-25 19:42  Nicolas Pomarede
+
+	* src/: sound.c, includes/sound.h: Cosmetic changes in new engine :
+	  remove unused code, indent, add more comments, ...
+
+2008-10-24 00:16  Eero Tamminen
+
+	* doc/emutos.txt: Checked/added Falcon games
+
+2008-10-24 00:16  Eero Tamminen
+
+	* doc/compatibility.html: - With latest DSP change, Bad Mood
+	  actually draws something half sensible - Tank Blaster works
+
+2008-10-23 18:50  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Latest updates from Aranym: - Fixes in
+	  L:xxx,register parallel move, both directions.  - Fixes in
+	  register,L:xxx when limiting occurs.	-  Fixes for LSL,BCHG
+	  instructions.
+
+2008-10-22 22:55  Eero Tamminen
+
+	* doc/: compatibility.html, emutos.txt: - correct state of couple
+	  Falcon demos & apps	(some Whip! effects actually work) - list
+	  some EmuTOS compatible Falcon demos and apps
+
+2008-10-22 20:56  Thomas Huth
+
+	* src/gemdos.c: Improved check for file attributes during
+	  Fsfirst/Fsnext. This fixes FSELECT.PRG by M. Patzel. Thanks to
+	  Thomas Schaerer for the hint.
+
+2008-10-21 23:15  Eero Tamminen
+
+	* src/: screen.c, statusbar.c, falcon/hostscreen.c,
+	  gui-sdl/dlgScreen.c, includes/statusbar.h: - Statusbar shows also
+	  in fullscreen - Statusbar height calculation needs to take into
+	  account screen width	 because the the gui-sdl font selection
+	  does - Toggling Statusbar from Display options doesn't toggle
+	  overlay LED	(even when it's enabled, it's shown only when
+	  statusbar isn't)
+
+2008-10-21 21:04  Eero Tamminen
+
+	* src/statusbar.c: all SDL_UpdateRect calls here have now debug
+	  prints
+
+2008-10-20 22:56  Eero Tamminen
+
+	* doc/compatibility.html: Remove the exlamation marks now that I've
+	  checked the required DSP modes.
+
+2008-10-20 22:31  Thomas Huth
+
+	* src/psg.c: Save LastStrobe to memory snapshots, too (just in
+	  case...)
+
+2008-10-20 22:23  Thomas Huth
+
+	* src/: mfp.c, printer.c, psg.c, includes/mfp.h: These patches make
+	  Hatari emulate printer port capture more accurately.
+
+	  In psg.c : Centronics STROBE is used Exclusively, LastWriteToIOB
+	  PORTB checking is Removed.
+
+	  In mfp.c : MFP_EXCEPT_GPIP0 interrupt is added to
+	  MFP_CheckPendingInterrupts() to create BUSY interrupt capability
+	  in hatari.
+
+	  In printer.c : All data presented to PORTB will now be passed
+	  unfiltered to the printer, the same as Atari hardware would do
+	  it. Thus, filtering, tab expanding, and associated code is
+	  removed.
+
+	  Thanks to David Savinkoff for the patch!
+
+2008-10-20 22:15  Eero Tamminen
+
+	* doc/compatibility.html: add Illusion 64 (one more demo that works
+	  only when DSP emu is disabled)
+
+2008-10-19 22:52  Eero Tamminen
+
+	* doc/compatibility.html: add couple of New Beat demos (work fine)
+	  and music applications (don't work) + few other demos
+
+2008-10-19 15:06  Nicolas Pomarede
+
+	* src/: sound.c, includes/sound.h: Remove unused float code.
+
+2008-10-16 23:30  Nicolas Pomarede
+
+	* src/psg.c: Register select in $ff8800 should not be masked with
+	  0xf, but further read/write when register >= 16 should be
+	  ignored.  (fix long standing bug in European Demo Intro)
+
+2008-10-16 20:25  Nicolas Pomarede
+
+	* src/sound.c: Remove gcc warning
+
+2008-10-16 00:14  Nicolas Pomarede
+
+	* src/mfp.c: Revert useless test when data reg for timer A/B is
+	  decremented from a previous 0 value (as we use Uint8)
+
+2008-10-15 23:06  Nicolas Pomarede
+
+	* src/sound.c: Set sample to 0 instead of 0x9a when volume is 0
+	  (this way the volume 0 of the ym is aligned with the sample 0
+	  level)
+
+2008-10-14 23:34  Nicolas Pomarede
+
+	* src/sound.c: Full support for 5 bits volume when computing
+	  envelopes. All internal volumes operations are made with 5 bits
+	  for maximum accuracy (as on a real YM-2149)
+
+2008-10-14 22:00  Eero Tamminen
+
+	* doc/compatibility.html: Went through all games & demos marked as
+	  none/dummy and checked whether they work with DSP emulation
+	  enabled. Almost none did, added more info about that.  Updated a
+	  couple of other games/demos.
+
+2008-10-13 22:29  Eero Tamminen
+
+	* doc/compatibility.html: Falcon updates: - Add Bad Mood & ChainZ
+	  games (not working) - Add a few working and not working demos and
+	  apps - Some things that worked earlier only when DSP emulation
+	  is disabled, work now also when it's enabled
+
+2008-10-13 22:26  Eero Tamminen
+
+	* doc/emutos.txt: add more STE and debugging info
+
+2008-10-11 00:10  Thomas Huth
+
+	* src/gui-osx/: PrefsController.h, PrefsController.m,
+	  SDLMain.nib/classes.nib, SDLMain.nib/info.nib,
+	  SDLMain.nib/keyedobjects.nib, SDLMain.nib/objects.nib: Merged
+	  some of the OS X GUI updates from Jerome Vernet
+
+2008-10-11 00:01  Thomas Huth
+
+	* Hatari.xcodeproj/project.pbxproj: Cleaned up the sources list in
+	  the Mac OS X project file.
+
+2008-10-10 20:21  Thomas Huth
+
+	* src/falcon/: dsp_core.c, dsp_core.h, dsp_cpu.c: Merged dsp56k
+	  changes from Aranym: - Recode sub/add on 56bits in a simpler way.
+	  - BSET/BCLR were not clearing/setting A2/B2 when changing bit in
+	  A/B	accumulator (from Laurent Sallafranque).  - try to fix
+	  detection of end of loop for DO instruction.
+
+2008-10-09 00:34  Nicolas Pomarede
+
+	* src/uae-cpu/newcpu.c: Fix special case for MFP exception handling
+	  with cpu >= 68020
+
+2008-10-05 22:42  Nicolas Pomarede
+
+	* src/ikbd.c: Remove double ';'
+
+2008-10-05 22:41  Nicolas Pomarede
+
+	* src/utils.c: Add rcsid
+
+2008-10-05 22:31  Nicolas Pomarede
+
+	* src/uae-cpu/newcpu.h: Add a parameter ExceptionSource to
+	  Exception(). This allows to remove the possible ambiguity when
+	  MFP vector base is changed in $fffa17 and the resulting exception
+	  number could conflict with a 'normal' cpu exception.	Fix High
+	  Fidelity Dreams by Aura which set MFP vector base to $c0 instead
+	  of $100.
+
+2008-10-05 21:55  Thomas Huth
+
+	* src/configuration.c: Set bDisableKeyRepeat = FALSE by default.
+
+2008-10-05 19:55  Nicolas Pomarede
+
+	* src/: m68000.c, mfp.c, video.c, includes/m68000.h, uae-cpu/fpp.c,
+	  uae-cpu/gencpu.c, uae-cpu/newcpu.c: Add a parameter
+	  ExceptionSource to Exception(). This allows to remove the
+	  possible ambiguity when MFP vector base is changed in $fffa17 and
+	  the resulting exception number could conflict with a 'normal' cpu
+	  exception.  Fix High Fidelity Dreams by Aura which set MFP vector
+	  base to $c0 instead of $100.
+
+2008-10-04 13:41  Nicolas Pomarede
+
+	* src/mfp.c: Fix reading $fffa21 while timer B occurs in some rare
+	  cases (Wolfenstein 3D intro)
+
+2008-10-04 13:35  Nicolas Pomarede
+
+	* src/includes/video.h: Fix reading $fffa21 while timer B occurs in
+	  some rare cases (Wolfenstein 3D intro)
+
+2008-10-03 10:27  Thomas Huth
+
+	* src/falcon/dsp_disasm.c: Mark all instructions that may change
+	  SR. (Code from Patrice Mandin)
+
+2008-10-03 10:25  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Try again to fix carry bit computation.
+	  (Code from Patrice Mandin)
+
+2008-10-03 00:01  Nicolas Pomarede
+
+	* src/fdc.c: FDCTrackRegister, FDCSectorRegister and
+	  FDCDataRegister are 8 bits registers. When writing to $ff8604,
+	  only keep the lowest 8 bits.	(fix High Fidelity Dreams by Aura)
+
+2008-09-29 22:44  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: dsp56k fixes: SUB/ADD/CMP: Simply set carry
+	  bit if MSB changed, clear otherwise. (Thanks to Patrice Mandin
+	  for this)
+
+2008-09-29 22:15  Thomas Huth
+
+	* src/: cartData.c, cart_asm.s: Fixed a bug in the 68k part of the
+	  GEMDOS HD emulation: The stack got messed up when a program tried
+	  to run pexec with a program name that did not existed on the
+	  emulated GEMDOS HD.
+
+2008-09-28 18:56  Eero Tamminen
+
+	* doc/: compatibility.html, emutos.txt: minor updates
+
+2008-09-28 16:13  Eero Tamminen
+
+	* doc/hatari.1: Add documentation for missing command line options
+	  and files + other improvements
+
+2008-09-27 21:01  Thomas Huth
+
+	* Hatari.xcodeproj/project.pbxproj: Added ym2149_fixed_vol.h to
+	  Xcode project file.
+
+2008-09-27 16:51  Thomas Huth
+
+	* doc/fr/clavier-exemple.txt: No need to remap the function keys
+
+2008-09-27 16:43  Thomas Huth
+
+	* src/gemdos.c: Work-around for the file selector bug in TOS 1.02
+	  (Bug #1648169)
+
+2008-09-27 15:36  Thomas Huth
+
+	* src/fdc.c: According to Volker Seebode, HDCCommand.byteCount must
+	  not be reset during FDC_ResetDMAStatus(). (Bug #2130450)
+
+2008-09-27 15:21  Thomas Huth
+
+	* src/hdc.c: DMA counter wasn't updated after HDC commands (Bug
+	  #2130480). Thanks to Volker Seebode for the patch
+
+2008-09-27 13:09  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: MAC/MACR should not change Carry bit (from
+	  Laurent Sallafranque)
+
+2008-09-26 21:29  Eero Tamminen
+
+	* doc/emutos.txt: Add separate section on how to debug EmuTOS
+	  issues based on info from Thomas.
+
+2008-09-26 18:39  Thomas Huth
+
+	* src/falcon/hostscreen.c: Removed unused code.
+
+2008-09-26 00:23  Nicolas Pomarede
+
+	* src/video.c: On STE, allow to change video address, hw scroll and
+	  linewidth when line >= nLastVisibleHbl (fix Power Rise / Xtrem D
+	  demo)
+
+2008-09-25 22:05  Thomas Huth
+
+	* src/keymap.c: Added some more keycodes, this time for german Mac
+	  keyboards.
+
+2008-09-25 20:36  Nicolas Pomarede
+
+	* src/sound.c: Correctly stop sound after a reset when using old
+	  sound engine
+
+2008-09-24 22:01  Eero Tamminen
+
+	* doc/emutos.txt: added STE (enhanced) demos
+
+2008-09-23 01:22  Eero Tamminen
+
+	* doc/emutos.txt: - add STE programs working after Thomas' EmuTOS
+	  DMA sound cookie fix - fine-tune the texts
+
+2008-09-21 23:59  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: DSP56k cpu fix: DIV instruction calculation
+	  (from Laurent Sallafranque)
+
+2008-09-21 23:57  Thomas Huth
+
+	* src/falcon/dsp_disasm.c: DSP56k disasm fix:  mask out address
+	  bits to 32K, to read current instruction
+
+2008-09-20 14:06  Thomas Huth
+
+	* Makefile: Build hmsa from the main Makefile, too.
+
+2008-09-20 14:05  Thomas Huth
+
+	* tools/hmsa/Makefile: Added distclean target
+
+2008-09-20 14:01  Thomas Huth
+
+	* src/options.c: Fixed rcsid label
+
+2008-09-20 13:33  Thomas Huth
+
+	* doc/: hatari.1, fr/hatari.1: Fixed more unquoted dashes in
+	  manpages
+
+2008-09-20 13:28  Thomas Huth
+
+	* src/main.c: Oops, reverted last change, didn't want to commit
+	  that...
+
+2008-09-20 13:25  Thomas Huth
+
+	* doc/hatari.1, src/main.c: Fixed unquoted dashes in manpage (patch
+	  taken from the Debian package, thanks to Teemu Hukkanen)
+
+2008-09-19 20:55  Nicolas Pomarede
+
+	* src/sound.c: Allow to mix volumes with a table (as measured on a
+	  real ST) or with a linear mean of the 3 volumes.  Default to
+	  linear mixing for now as it gives better results.  Don't center
+	  the samples, keep them 16 bits signed but in the range [0,32767]
+	  (suppress small sounds when pausing/resuming audio device)
+
+2008-09-16 23:14  Eero Tamminen
+
+	* doc/compatibility.html: - sort STE demos by group/author - add
+	  one STE game and several STE demos
+
+2008-09-16 22:31  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Fixed lua with a Ny destination register,
+	  and parallel move, fix B,A as it is not a full 56bit transfer
+	  (Thanks to Patrice and Laurent for the patch)
+
+2008-09-15 23:08  Thomas Huth
+
+	* src/falcon/: dsp_cpu.c, dsp_disasm.c: Merged changes from Aranym
+	  CVS: - dsp56k fixes:	 -LUA instruction must not change source
+	  register.    -Parallel moves: disasm for dsp_pm_4, fixes in
+	  dsp_pm_1.  (Thanks to Laurent Sallafranque for the patches)
+
+2008-09-14 23:45  Eero Tamminen
+
+	* doc/emutos.txt: add STE games and update notes
+
+2008-09-14 21:33  Nicolas Pomarede
+
+	* src/uae-cpu/newcpu.c: TRAP was returning 38 cycles instead of 34
+	  (Phaleon/Illusion Demo by Next)
+
+2008-09-14 19:53  Eero Tamminen
+
+	* Makefile-MinGW.cnf, config-default.h, src/Makefile: Cygwin
+	  improvements from Guillaume D: - src/Makefile: ALLOBJS was added
+	  twice under Cygwin - config-default.h: Cygwin doesn't have the
+	  "cfmakerow" function - Makefile-MinGW.cnf: overridable SDL_CFLAGS
+	  & SDL_LIBS
+
+2008-09-14 13:01  Nicolas Pomarede
+
+	* src/mfp.c: Add more traces Apply Timer D patch only if ctrl reg
+	  is != 0
+
+2008-09-14 12:43  Nicolas Pomarede
+
+	* src/uae-cpu/newcpu.c: Improve log
+
+2008-09-13 00:27  Eero Tamminen
+
+	* doc/: compatibility.html, emutos.txt: - Added Super Hang-On to
+	  compatibility list - Added compatibility information to
+	  emutos.txt along   with lots of other information I had in old
+	  mails etc
+
+2008-09-11 22:38  Thomas Huth
+
+	* src/main.c: Removed unnecessary header file includes
+
+2008-09-11 22:33  Thomas Huth
+
+	* src/main.c: Fixed the problem that loading the global
+	  configuration file only worked on UNIX-style operating systems
+	  which use a '/' as path seperator.
+
+2008-09-07 21:24  Eero Tamminen
+
+	* src/statusbar.c: - Fix TOS version string - Move messages after
+	  FS, that looks better in screen with borders
+
+2008-09-07 00:18  Nicolas Pomarede
+
+	* src/: sound.c, includes/ym2149_fixed_vol.h: Use a table to
+	  convert the 3 voices' volume to a sample. New mixing for
+	  tone/volume/enveloppe using this table.
+
+2008-09-06 23:08  Eero Tamminen
+
+	* src/statusbar.c: - Fix frameskip text Rect width - Add drawing of
+	  recording led   - In overlay mode, this overrides the floppy led
+	  (color)
+
+2008-09-06 21:14  Eero Tamminen
+
+	* src/statusbar.c: - center the text on drawing instead of
+	  centering the string to char array - Add frameskip showing ("FS:
+	  0")
+
+2008-09-05 23:40  Eero Tamminen
+
+	* src/statusbar.c: fix/improve docs
+
+2008-09-05 23:29  Eero Tamminen
+
+	* src/: change.c, main.c, statusbar.c, tos.c, includes/statusbar.h,
+	  includes/tos.h: Statusbar improvements: - show by default RAM,
+	  machine and TOS information - functionality to show other
+	  messages (with timeout) - optional debug printf()s - all
+	  variables static Other files: - tos.c: change info about etos
+	  into extern - main.c: ask statusbar to update default info in
+	  suitable   place (after TOS loaded) and show initial help text if
+	  default shortcut is used for Options - change.c: ask statusbar
+	  to update info when needed
+
+2008-09-05 23:10  Eero Tamminen
+
+	* src/int.c: fix compiler warnings on TRACE() calls for Sint64
+	  changes
+
+2008-09-05 20:39  Nicolas Pomarede
+
+	* src/video.c: No need to test 60/50 Hz switch if display has not
+	  started yet.
+
+2008-09-04 23:26  Thomas Huth
+
+	* src/mfp.c: Fixed mask for TX buffer empty interrupt.
+
+2008-09-04 23:18  Thomas Huth
+
+	* src/: blitter.c, mfp.c, includes/mfp.h: Added Blitter-done
+	  interrupt
+
+2008-09-04 19:52  Thomas Huth
+
+	* src/: int.c, includes/int.h: Changed type of CycleTime back to
+	  32-bit so that the 64 bits are only used internally. Also removed
+	  the assert statements.
+
+2008-09-04 12:53  Thomas Huth
+
+	* src/int.c: Set cycle counters to INT_MAX during reset (just in
+	  case...).
+
+2008-09-04 12:41  Thomas Huth
+
+	* src/: int.c, includes/int.h: Increased size of internal interrupt
+	  cycle counter variables to 64 bit. This fixes Sedma's
+	  Blittermania for example since the internal DMA sound cycle
+	  counter does not overflow anymore.
+
+2008-09-03 23:25  Eero Tamminen
+
+	* doc/compatibility.html: add new demos + update info on some
+	  others
+
+2008-09-02 21:46  Nicolas Pomarede
+
+	* src/hdc.c: Update HD led when processing a command
+
+2008-09-02 21:26  Thomas Huth
+
+	* Hatari.xcodeproj/project.pbxproj: Updated the Xcode project file
+
+2008-09-02 20:56  Eero Tamminen
+
+	* src/: gemdos.c, psg.c, statusbar.c, includes/statusbar.h: - add
+	  timeout based HD led and separate function for enabling it
+	  (floppy leds API remains ON/OFF toggling which is needed for
+	  more accurate control that the PSG emulation can provide) -
+	  gemdos.c enables HD led when HD emu calls are used - rename "C:"
+	  to "HD:", one led is enough for all HDs
+
+2008-09-02 13:10  Thomas Huth
+
+	* src/int.c: Added some assertions to be able to detect overflows
+	  in the Int_AddXXXInterrupt functions
+
+2008-09-02 13:08  Thomas Huth
+
+	* src/: ikbd.c, video.c: Decreased IKBD_RESET_CYCLES since the old
+	  value caused an overflow in Int_AddRelativeInterrupt(). Now the
+	  mouse in Barbarian (from Psygnosis) is working again.
+
+2008-09-02 12:09  Thomas Huth
+
+	* src/: blitter.c, dmaSnd.c, fdc.c, ikbd.c, int.c, mfp.c, video.c,
+	  includes/int.h: Removed the offset parameter from
+	  Int_AddRelativeInterrupt() since the function
+	  Int_AddRelativeInterruptWithOffset() is already used for starting
+	  a relative Int with offset
+
+2008-09-02 11:53  Thomas Huth
+
+	* src/: blitter.c, dmaSnd.c, fdc.c, ikbd.c, video.c: Cleaned up
+	  superfluous white spaces
+
+2008-08-21 18:05  Thomas Huth
+
+	* src/ikbd.c: Added a workaround for a problem with the game USS
+	  John Young / FOF54: It checks whether the transmit-buffer-empty
+	  bit is cleared after writing a byte to the IKBD.
+
+2008-08-20 20:01  Eero Tamminen
+
+	* Makefile-default.cnf: - Add check for X11 - move CFLAGS check
+	  inside ifneq to speedup non-matching case - use the expanded :=
+	  notation so that shell commands are run only once
+
+2008-08-19 22:53  Eero Tamminen
+
+	* src/screenSnapShot.c: Invert RGB byte order for little endian
+	  32-bits in PNG saving.
+
+2008-08-19 22:36  Eero Tamminen
+
+	* doc/alsa-midi.txt: minor update
+
+2008-08-19 22:05  Eero Tamminen
+
+	* src/: change.c, gui-sdl/dlgScreen.c: * Change screen options
+	  "force 8-bpp" option to statusbar/led toggle	 - Checkbox value
+	  taken just from statusbar state, but it sets both	statusbar
+	  and led state * Support in change.c for toggling statusbar (+
+	  comment improvements)
+
+2008-08-19 21:47  Eero Tamminen
+
+	* src/: configuration.c, options.c, screen.c, statusbar.c,
+	  includes/configuration.h, includes/statusbar.h: * add support for
+	  overlay drive led to statusbar.c   - and appropriate small update
+	  to screen.c * config file and commandline option for
+	  enabling/disabling it * enable statusbar & drive-led by default
+	  so they get more testing
+
+2008-08-19 21:43  Eero Tamminen
+
+	* src/gui-sdl/dlgScreen.c: align VDI checkbox and texts
+	  horizontally with other checkboxes and texts
+
+2008-08-19 21:15  Eero Tamminen
+
+	* src/: configuration.c, main.c, options.c, video.c,
+	  gui-sdl/dlgScreen.c, includes/video.h: add support for automatic
+	  frameskip and enable it by default
+
+2008-08-19 02:09  Thomas Huth
+
+	* src/: audio.c, dmaSnd.c, sound.c, wavFormat.c, includes/sound.h,
+	  includes/wavFormat.h: Changed sound sample type from 8-bit mono
+	  unsigned to 16-bit stereo signed.
+
+2008-08-18 22:53  Thomas Huth
+
+	* Makefile-default.cnf: Automatic libpng default configuration
+
+2008-08-18 21:13  Eero Tamminen
+
+	* src/screenSnapShot.c: fix include order and use if instead of
+	  ifdef like other config.h checks do
+
+2008-08-18 20:35  Eero Tamminen
+
+	* src/screenSnapShot.c: add support for saving PNGs
+
+2008-08-18 20:16  Thomas Huth
+
+	* src/sound.c: Added workaround for a problem with the GCC 4.2
+	  compiler.
+
+2008-08-18 20:12  Thomas Huth
+
+	* configure.ac: Added simple check for libpng
+
+2008-08-18 19:39  Thomas Huth
+
+	* doc/keymap-sample.txt: SDL headers are usually in
+	  /usr/include/SDL, not in /usr/share/SDL
+
+2008-08-18 19:35  Thomas Huth
+
+	* doc/fr/clavier-exemple.txt: Added french keymapping file. Thanks
+	  to Jerome Vernet for the mappings!
+
+2008-08-16 17:49  Eero Tamminen
+
+	* src/: screen.c, statusbar.c, falcon/hostscreen.c,
+	  includes/statusbar.h: Simplify statusbar code by moving the SDL
+	  update call to statusbar.c (which also fixes hostscreen.c
+	  update).  SDL_UpdateRects() requires Statusbar_Update() to be
+	  done outside screen locks, move that.
+
+2008-08-15 19:08  Matthias Arndt
+
+	* src/includes/sound.h: cleanup of sound.h - moved common definitions
+	  for both cores out of the #ifdef OLD_SOUND block
+
+2008-08-14 00:26  Nicolas Pomarede
+
+	* src/sound.c: More cast changes
+
+2008-08-14 00:01  Nicolas Pomarede
+
+	* src/sound.c: Add more explicit casts, as reported by
+	  -Wconversion. Might help with gcc 4.2 on OS X.
+
+2008-08-13 20:44  Eero Tamminen
+
+	* src/: psg.c, statusbar.c, includes/statusbar.h: - Set led on
+	  drive B: access - Enums for different drives - Comment about
+	  things that statusbar could also show
+
+2008-08-13 00:14  Nicolas Pomarede
+
+	* src/sound.c: Fix StSound to generate samples in the range -32768
+	  - 32767 instead of 0 - 32767. Much better result.
+
+2008-08-12 21:40  Eero Tamminen
+
+	* src/: Makefile, configuration.c, leds.c, options.c, psg.c,
+	  screen.c, statusbar.c, falcon/hostscreen.c,
+	  includes/configuration.h, includes/leds.h, includes/statusbar.h:
+	  - Replace leds (over Atari screen) with NoSTalgia style statusbar
+	  - As statusbar increases the SDL screen size, change:   -
+	  screen.c updates to use an SDL_Rect that doesn't contain the
+	  statusbar   - hostscreen.c screen height variable to ignore
+	  statusbar part
+
+2008-08-12 21:36  Eero Tamminen
+
+	* src/: gui-sdl/sdlgui.c, includes/sdlgui.h: Prepare SDL GUI
+	  functions for statusbar support: - Add small SDLGui_GetFontSize()
+	  function - Change SDLGui_Text() to extern - Allow calling
+	  SDLGui_Init() multiple times
+
+2008-08-12 21:00  Nicolas Pomarede
+
+	* src/: includes/sound.h, sound.c: Frequency change between 44, 22
+	  and 11 kHz was not correctly handled in new StSound method.
+
+2008-08-10 16:32  Nicolas Pomarede
+
+	* src/: sound.c, includes/sound.h: Import StSound 1.2 rendering
+	  engine to replace the current method.
+
+2008-08-10 12:39  Nicolas Pomarede
+
+	* src/sound.c: Revert modif : don't set per=1 when per=0, this
+	  cause sharp sound with some sample replay routines.
+
+2008-08-07 23:19  Eero Tamminen
+
+	* src/screen.c: - revert earlier 32->24 change and comment why the
+	  surface   needs to be re-created - rename leds related variables
+	  and add comments to clarify	how it works
+
+2008-08-07 22:18  Eero Tamminen
+
+	* src/: leds.c, includes/configuration.h: move main.h inclusion to
+	  .c
+
+2008-08-07 21:41  Eero Tamminen
+
+	* src/: leds.c, screen.c: remove dummy led light blinking, fix
+	  partial screen update for led
+
+2008-08-07 20:39  Nicolas Pomarede
+
+	* src/psg.c: Set drive light ON if drive A is selected
+
+2008-08-07 20:16  Eero Tamminen
+
+	* src/screen.c: - Add support for leds/indicators for ST/e screen
+	  modes - Change unused bSwapScreen argument (for fullscreen) in
+	  Screen_Blit()   to SDL_Rect * for led update area (in case only
+	  leds are updated) - Instead of re-creating SDL screen surface as
+	  32-bits when 24-bits	 is selected in Screen_SetResolution(),
+	  just set 32-bits to 24
+
+2008-08-07 20:07  Eero Tamminen
+
+	* src/falcon/hostscreen.c: add led/indicator show/hide to render
+	  begin/end for TT and Falcon video modes
+
+2008-08-07 20:05  Eero Tamminen
+
+	* src/: configuration.c, options.c: add configuration option for
+	  leds/indicators like floppy light
+
+2008-08-07 20:04  Eero Tamminen
+
+	* src/: Makefile, leds.c, includes/leds.h: add gfx side of floppy
+	  light support
+
+2008-08-06 21:28  Eero Tamminen
+
+	* src/includes/configuration.h: add include files needed by this
+
+2008-08-06 01:42  Thomas Huth
+
+	* src/falcon/: dsp_core.c, dsp_core.h, dsp_cpu.c: Merged changes
+	  from Aranym repository: - Use proper SDL function to wait for
+	  thread to finish - rewrite of dsp_core - Remove states - Simply
+	  unlock semaphore on read/write - Defined stuff shared between cpu
+	  and dsp thread as volatile - It seems most dsp programs always
+	  handshake when reading from dsp host port
+
+2008-08-06 01:26  Thomas Huth
+
+	* src/falcon/: araglue.h, dsp_disasm.c, hostscreen.c, hostscreen.h,
+	  nvram.c, videl.c: Replaced Aranym integer types with SDL integer
+	  types
+
+2008-08-05 21:23  Eero Tamminen
+
+	* doc/compatibility.html: use CSS class instead of bgcolor
+	  attribute for colors
+
+2008-08-02 21:25  Eero Tamminen
+
+	* doc/compatibility.html: sort ST games alphabetically similarly to
+	  STE and Falcon games lists
+
+2008-08-02 20:53  Eero Tamminen
+
+	* doc/compatibility.html: mark issues with color instead of .
+	  Move Ray's TT/Falcon intros to TT section as that has less
+	  entries.
+
+2008-08-01 19:14  Thomas Huth
+
+	* src/falcon/: dsp.c, dsp_core.c: Replaced old uint8 types
+
+2008-08-01 01:31  Thomas Huth
+
+	* src/falcon/: dsp_core.c, dsp_core.h, dsp_cpu.c: Merged Patrice's
+	  latest changes: - Move around mutex lock/unlock - Replace uae
+	  data type by SDL data types
+
+2008-07-31 22:45  Thomas Huth
+
+	* src/falcon/dsp_core.h: SDL_thread.h must be included, too,
+	  because it is missing in SDL.h on older SDL versions like 1.2.7
+
+2008-07-31 21:43  Thomas Huth
+
+	* src/falcon/araglue.h: DSP code needs some functions from
+	  string.h, so this header file must be included, too.
+
+2008-07-31 21:23  Thomas Huth
+
+	* doc/compatibility.html: Added V8 music system and Songs of the
+	  Unexpected
+
+2008-07-31 01:09  Eero Tamminen
+
+	* doc/compatibility.html: update info
+
+2008-07-30 18:48  Eero Tamminen
+
+	* src/control.c: - add support for remotely:   - toggling devices
+	  - setting paths - remove support for using "stdin" for control
+	  socket.  hatari-console.py   is nicer and e.g. WinSock wouldn't
+	  support select with stdin
+
+2008-07-30 18:45  Eero Tamminen
+
+	* doc/compatibility.html: update compatibility list as discussed on
+	  hatari-devel
+
+2008-07-30 00:12  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Patch from Aranym: Calculate how many
+	  instructions we executed per second, seem we are very far from
+	  real hw
+
+2008-07-30 00:10  Thomas Huth
+
+	* src/falcon/: Makefile, dsp.c: Forgot to define DSP_EMULATION=1
+	  when DSP was enabled.
+
+2008-07-29 23:56  Thomas Huth
+
+	* src/Makefile: Added the new file dsp_core.c to the main Makefile
+
+2008-07-29 23:38  Eero Tamminen
+
+	* src/screen.c: ; after CALL_VAR macro like elsewhere, fix
+	  following code indenting
+
+2008-07-29 23:32  Thomas Huth
+
+	* src/falcon/: Makefile, araglue.h, dsp.c, dsp.h, dsp_core.c,
+	  dsp_core.h, dsp_cpu.c, dsp_cpu.h, dsp_disasm.c, dsp_disasm.h:
+	  Merged Patrice's latest changes to the DSP emulation code in
+	  Aranym: Implementation of DSP emulation in plain C. Thanks a lot
+	  Patrice!
+
+2008-07-29 23:27  Eero Tamminen
+
+	* src/options.c: shorter and more consistent option descriptions
+
+2008-07-28 22:38  Thomas Huth
+
+	* src/ikbd.c: Added missing IKBD commands for status inquiries.
+
+2008-07-28 21:49  Thomas Huth
+
+	* src/ikbd.c: Some IKBD commands like 0x0d, 0x16 and 0x1c need an
+	  additional delay until the first byte is sent back from the IKBD.
+	  The 'Unlimited bobs' screen from the Dragonnels demo is working
+	  now.
+
+2008-07-28 00:37  Thomas Huth
+
+	* src/falcon/: dsp_cpu.c, dsp_disasm.c, dsp_disasm.h: Patches from
+	  Aranym: Add function so we know when LC was decremented.
+
+2008-07-27 23:44  Thomas Huth
+
+	* src/falcon/: dsp.c, dsp.h, dsp_cpu.c: Reworked state change for
+	  dsp thread, and always force execution of dsp when cpu read/write
+	  from host port
+
+2008-07-27 22:36  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Patch from Aranym: Fixed wrong calculation
+	  of E bit in SR and added missing masking of ZUE value for CC
+	  calculation
+
+2008-07-27 20:33  Nicolas Pomarede
+
+	* src/includes/sound.h: Remove unnecessary 'extern' variables
+
+2008-07-27 20:26  Nicolas Pomarede
+
+	* src/: sound.c, ymFormat.c, includes/sound.h, psg.c: Better
+	  separation between accesses to the YM hardware registers and the
+	  sound rendering routines (to ease replacement by another sound
+	  rendering module)
+
+2008-07-25 20:15  Eero Tamminen
+
+	* tools/hmsa/hmsa.c: fix build
+
+2008-07-24 00:00  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Merged some more changes from Aranym
+	  repository
+
+2008-07-23 23:20  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Patch from Aranym: Change detection of
+	  polling loop
+
+2008-07-23 23:12  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Patch from Aranym: Split write_memory in
+	  disasm/non disasm version
+
+2008-07-23 23:11  Thomas Huth
+
+	* src/falcon/dsp_disasm.c: Patch from Aranym: Fix disasm to match
+	  memory mapping changes
+
+2008-07-23 00:26  Thomas Huth
+
+	* src/falcon/: dsp.c, dsp_cpu.c: Sync'ed DSP sources with Aranym
+	  repository: Change X, Y and P memory mapping to match what
+	  happens on Falcon.
+
+2008-07-22 23:45  Thomas Huth
+
+	* src/falcon/: dsp.c, dsp.h, dsp_cpu.c, dsp_disasm.c: Put the DSP
+	  variables in a struct and introduced the getDSP function for
+	  Hatari, too, so that the code gets much closer to the original
+	  Aranym sources again. This helps a lot when sync'ing the sources
+	  with Aranym.
+
+2008-07-22 22:55  Thomas Huth
+
+	* src/: includes/ikbd.h, includes/int.h, ikbd.c, int.c: When a byte
+	  arrives at our virtual ACIA, do not trigger the corresponding MFP
+	  interrupt immediately but some cycles later. This fixes the V8
+	  music system demo.
+
+2008-07-22 22:34  Thomas Huth
+
+	* src/control.c: Fixed compiler warning
+
+2008-07-21 22:39  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Copied new DSP update-Rn-modulo function
+	  from the Aranym CVS repository.
+
+2008-07-19 15:51  Nicolas Pomarede
+
+	* src/video.c: If using an invalid resolution value 0x03 in
+	  $ff8260, use 0x00 (low res) instead (fix Omegakul screen in Omega
+	  Demo from 1988)
+
+2008-07-19 00:15  Thomas Huth
+
+	* src/falcon/: dsp_cpu.c, dsp_disasm.c: Synced DSP sources with
+	  Aranym repository. This fixes the register encoding of the
+	  following DSP instructions: Tcc, AND, EOR & OR (cheers to Patrice
+	  Mandin for the changes)
+
+2008-07-18 21:02  Thomas Huth
+
+	* src/falcon/dsp.c: When using DSP_HOST_FORCEEXEC we've got delay a
+	  little bit to free some CPU cycles for the DSP thread.
+
+2008-07-16 23:12  Thomas Huth
+
+	* src/: ikbd.c, log.c, includes/log.h: Introduced more IKBD trace
+	  levels and replaced old WinSTon IKBD debug code with HATARI_TRACE
+	  calls.
+
+2008-07-15 00:52  Thomas Huth
+
+	* src/falcon/dsp_disasm.c: Fixed the register encoding of the ADD,
+	  SUB and TFR instructions of the DSP disassembler (Y0 and X1 were
+	  swapped).
+
+2008-07-14 19:42  Thomas Huth
+
+	* src/main.c: Fixed bug: HostScreen_UnInit was only called when
+	  also DSP emulation was enabled.
+
+2008-07-14 17:03  Nicolas Pomarede
+
+	* src/video.c: Left border removal in 60 Hz gives a total line size
+	  of 184 bytes instead of 186.
+
+2008-07-13 00:26  Nicolas Pomarede
+
+	* doc/compatibility.html: All parts of the B.I.G. Demo are working
+	  fine
+
+2008-07-12 23:51  Nicolas Pomarede
+
+	* src/ikbd.c: Faster mouse in Dragonnels and Froggies Over The
+	  Fence
+
+2008-07-12 17:55  Nicolas Pomarede
+
+	* src/: ikbd.c, includes/ikbd.h, uae-cpu/hatari-glue.c: Add support
+	  for custom 6301 programs. This is not a 6301 emulator, we're just
+	  replacing the read/write functions with some customs one, based
+	  on the CRC of the bytes sent to the 6301 RAM.  This fixes
+	  'Froggies Over The Fence', 'Transbeauce 2' and 'Dragonnels'.
+
+2008-07-12 15:17  Nicolas Pomarede
+
+	* src/mfp.c: Correct a rare case when stopping a timer and the
+	  internal data counter is already < 1 (fix Froggies Over The Fence
+	  Menu)
+
+2008-07-10 23:19  Nicolas Pomarede
+
+	* src/: Makefile, utils.c, includes/utils.h: Add utils.c to store
+	  various utility functions (crc32, ...)
+
+2008-07-08 23:17  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Ooops, DSP_DISASM should not be defined by
+	  default.
+
+2008-07-08 23:13  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Fixed the DSP_CHECK_MEM_ACCESS defines
+	  (#endifs were placed at the wrong lines).
+
+2008-07-08 22:55  Eero Tamminen
+
+	* doc/compatibility.html: updates to Falcon compatibility
+
+2008-07-08 22:26  Nicolas Pomarede
+
+	* src/m68000.c: Add pairing for LSL/ABCD (and all variants)
+	  (Rainbow Wall part in Dragonnels Demo)
+
+2008-07-08 00:14  Thomas Huth
+
+	* Hatari.xcodeproj/project.pbxproj: Refreshed Xcode project file.
+	  Thanks to Jerome Vernet for the update
+
+2008-07-07 23:34  Thomas Huth
+
+	* doc/authors.txt, src/Makefile, src/falcon/dsp_cpu.c: Fixed bug in
+	  the DSP modulo addressing mode. The first two Falcon DSP programs
+	  (SPHERE.PRG and Virtual City) are working now! Big thanks to
+	  Laurent Sallafranque for the patch!
+
+2008-07-07 23:22  Nicolas Pomarede
+
+	* src/video.c: Better timer B position when right border is removed
+	  (fix Oxygene screen in Transbeauce 2)
+
+2008-06-29 23:33  Thomas Huth
+
+	* src/blitter.c, doc/compatibility.html: During blitter operations,
+	  check for pending interrupts even more often. This fixes the
+	  Doughnut screen in Just Musix 2 and the the bouncing vector ball
+	  screen in Braindamage demo.
+
+2008-06-28 13:22  Nicolas Pomarede
+
+	* src/: video.c, ioMemTabSTE.c, includes/video.h: On STE, add
+	  support for $ff8264 (horizontal scrolling with no prefetch) and
+	  refactor the scrolling routines in a more generic way (fix
+	  Digiworld 2 by ICE)
+
+2008-06-27 00:00  Thomas Huth
+
+	* src/gui-osx/PrefsController.m: Restore ConfigureParams when the
+	  user selected 'Cancel' in the emulator-must-be-reset alert
+	  dialog.
+
+2008-06-26 23:33  Thomas Huth
+
+	* src/tos.c: Assert that we are using at least a 68020 CPU for TOS
+	  versions > 3.00
+
+2008-06-26 22:00  Eero Tamminen
+
+	* src/options.c: - show --control-socket option only if it's
+	  available - remove redundant "This is" from front of Hatari
+	  name/version
+
+2008-06-26 01:01  Thomas Huth
+
+	* doc/compatibility.html: Added EPSS demo, and corrected Obsession
+	  and Braindamage description.
+
+2008-06-23 22:56  Eero Tamminen
+
+	* src/: change.c, control.c, dialog.c, main.c, screen.c,
+	  falcon/hostscreen.c, includes/control.h, includes/main.h: -
+	  implicit reboot after settings change should be OKed from   user
+	  even if alerts are shown only for warnings/errors - fix (reboot
+	  requiring) configuration changes canceling   (broken by
+	  configuration handling refactoring) - move Hatari window
+	  embedding from main.c to control.c - external UI can now ask to
+	  be notified about Hatari   SDL window size changes - support
+	  window embedding also in Falcon/TT screen modes
+
+2008-06-17 23:17  Eero Tamminen
+
+	* src/: floppy.c, includes/floppy.h: support ejecting floppy from
+	  command line
+
+2008-06-17 08:10  Thomas Huth
+
+	* src/gui-osx/PrefsController.m: Fixed comment
+
+2008-06-16 22:24  Thomas Huth
+
+	* src/gui-osx/: PrefsController.m, SDLMain.m: Fixed the OS X GUI so
+	  that it is compilable again.
+
+2008-06-16 21:34  Nicolas Pomarede
+
+	* src/video.c: Ensure unused lines are cleared in 60 Hz when Hatari
+	  is configured to display the screen's borders.
+
+2008-06-16 21:22  Thomas Huth
+
+	* src/rs232.c: Fixed RS232 baud rate setting (always use the by-16
+	  prescaler)
+
+2008-06-16 19:10  Thomas Huth
+
+	* src/ioMem.c: Writing to IO space is not allowed in user mode.
+	  Thanks to George Nakos for the hint!
+
+2008-06-15 14:02  Eero Tamminen
+
+	* src/shortcut.c: - add savemem shortcut parsing - remove parsing
+	  for debug interface shortcut (debug commands can   be invoked
+	  nowadays directly without the debug interface)
+
+2008-06-13 23:43  Eero Tamminen
+
+	* src/main.c: add note about the MinGW issue
+
+2008-06-13 23:09  Eero Tamminen
+
+	* src/: floppy.c, includes/floppy.h: - Change floppy eject alert to
+	  printf (the alert wasn't triggered   earlier as bInformUser
+	  wasn't used anywhere) - unsigned short (int) -> Uint16
+
+2008-06-13 19:44  Thomas Huth
+
+	* src/main.c: Fixed the prototype of main() so that Hatari compiles
+	  on Windows and Mac OS X again. Also removed saving of the current
+	  working directory in memory snap shots (it is not really
+	  required).
+
+2008-06-13 08:36  Thomas Huth
+
+	* src/blitter.c: Blitter runs at 16 MHz in the Falcon
+
+2008-06-12 23:16  Eero Tamminen
+
+	* configure.ac: note about getting install-sh complained by
+	  configure
+
+2008-06-12 22:51  Eero Tamminen
+
+	* src/options.c: use standard strchr() instead of BSD index()
+
+2008-06-12 20:03  Thomas Huth
+
+	* src/blitter.c: According to Cyprian's blitter test program, the
+	  blitter starts 4 cycles earlier already.
+
+2008-06-12 19:55  Thomas Huth
+
+	* src/blitter.c: Fix for the game Obsession: Update the pending
+	  interrupt functions regularly, also in blitter hog mode.
+
+2008-06-11 22:01  Eero Tamminen
+
+	* src/: main.c, options.c: fix compile warning
+
+2008-06-10 21:53  Eero Tamminen
+
+	* src/options.c: - add "--vdi " option - add support for
+	  options postfixed with a digit - add "--joy " option
+	  - remove "-a" shortcut for --disk-a (not really needed)
+
+2008-06-08 22:09  Eero Tamminen
+
+	* src/floppy.c: Should the filenames be absolute (in config file)?
+
+2008-06-08 22:04  Eero Tamminen
+
+	* src/: change.c, floppy.c, gui-sdl/dlgDisk.c, includes/floppy.h: -
+	  dialog may not eject disk directly, just set the file name to
+	  none,   otherwise ejecting doesn't work - remove unused
+	  bInformUser from floppy eject - add bool return value on whether
+	  there was a floppy that was ejected - 0 -> '\0' is a bit more
+	  explicit (readable) for strings
+
+2008-06-08 21:30  Eero Tamminen
+
+	* src/: change.c, dialog.c, includes/change.h: change.c can apply
+	  changes regardless of whether the new values are in
+	  ConfigureParams or some other struct.  This makes it easier to
+	  have configuration changes editing (or calling some that edits)
+	  ConfigureParams directly.
+
+2008-06-08 19:37  Eero Tamminen
+
+	* src/: change.c, configuration.c, floppy.c, log.c, main.c,
+	  options.c, paths.c, gui-sdl/dlgDisk.c, includes/configuration.h,
+	  includes/floppy.h, includes/options.h: * Add floppy disk image
+	  file names (and their zip paths)   to Hatari configuration *
+	  Insert the floppies in Change_CopyChangedParamsToConfiguration()
+	  based on changes in these * Separated in floppy.c setting disk
+	  image names from actually   inserting them * Above three allow
+	  fixing the gui-sdl/dlgDisk.c FIXMEs.	  Changes to floppy
+	  settings are now cancellable like all other settings	* Remove
+	  bootdisk stuff from Opt_ParseParameters() arguments,	 main.c and
+	  change.c as it's now unnecessary * Add following options:
+	  --disk-a    Disk image in floppy drive A   --disk-b 
+	  Disk image in floppy drive B * Fixed log level name in level
+	  parsing * Cleaned up some old comments and how main.c handles
+	  working dir  (latter still ugly) and added few more Log lines to
+	  floppy.c
+
+2008-06-08 18:07  Eero Tamminen
+
+	* src/: dialog.c, gui-sdl/dlgDevice.c, includes/dialog.h,
+	  gui-sdl/dlgDisk.c, gui-sdl/dlgJoystick.c, gui-sdl/dlgKeyboard.c,
+	  gui-sdl/dlgMain.c, gui-sdl/dlgMemory.c, gui-sdl/dlgNewDisk.c,
+	  gui-sdl/dlgRom.c, gui-sdl/dlgScreen.c, gui-sdl/dlgSound.c,
+	  gui-sdl/dlgSystem.c: prepare for being able to cancel floppy
+	  changes: - backup ConfigureParams before opening Hatari dialogs -
+	  use ConfigureParams directly from the dialog Currently code needs
+	  additional Params struct and copying it, I'll fix that after
+	  fixing the floppy disk code.
+
+2008-06-07 20:42  Nicolas Pomarede
+
+	* src/: video.c, includes/screen.h, includes/video.h: Rename some
+	  video constants to avoid confusion with the values used in
+	  screen.h
+
+2008-06-04 01:06  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Return value was also wrong in JSCLR.
+	  Thanks to Laurent Sallafranque for the patch.
+
+2008-06-04 01:01  Thomas Huth
+
+	* src/blitter.c: 1) Blitter uses the bus for 64 _bus_ cycles, not
+	  64 CPU cycles. 2) Added cycle timings for FXSR and NFSR. Big
+	  thanks to Cyprian Konador for the hints and his blitter test
+	  programs!
+
+2008-06-03 21:41  Eero Tamminen
+
+	* src/: main.c, screen.c, includes/main.h: fix window embedding
+	  when Hatari returns from the fullscreen mode
+
+2008-06-03 20:10  Nicolas Pomarede
+
+	* src/: blitter.c, log.c, includes/log.h: Add tracing options for
+	  the blitter
+
+2008-06-02 22:07  Eero Tamminen
+
+	* src/: change.c, keymap.c, main.c, options.c, paths.c,
+	  includes/options.h, includes/paths.h: add missing consts and
+	  ctype.h includes
+
+2008-06-01 23:38  Thomas Huth
+
+	* src/falcon/dsp_cpu.c: Fixed bug in the DSP instruction JSSET: The
+	  saved PC was 1 instruction wrong after the RTS (the next
+	  instruction was jumped). Thanks to Laurent Sallafranque for the
+	  patch.
+
+2008-06-01 23:33  Thomas Huth
+
+	* src/falcon/dsp.c: Fixed compilation bug when DSP_HOST_FORCEEXEC
+	  was set to 1 (thanks to Laurent Sallafranque for the hint)
+
+2008-06-01 12:26  Nicolas Pomarede
+
+	* src/: screen.c, includes/screen.h: Display 45 lines instead of 47
+	  in bottom overscan, else some demos will show garbages in the
+	  last 2 lines.
+
+2008-05-31 19:57  Nicolas Pomarede
+
+	* src/video.c: Ignore consecutive writes of the same value to
+	  freq/res register
+
+2008-05-26 21:09  Thomas Huth
+
+	* src/gui-osx/AlertHooks.h: useAlertHooks is now bool instead of
+	  BOOL.
+
+2008-05-25 21:58  Thomas Huth
+
+	* src/: int.c, joy.c, keymap.c, m68000.c, memorySnapShot.c, mfp.c,
+	  options.c, printer.c, psg.c, reset.c, rs232.c, rtc.c, screen.c,
+	  screenSnapShot.c, shortcut.c, spec512.c, tos.c, video.c, xbios.c,
+	  zip.c, gui-sdl/dlgAlert.c, gui-sdl/dlgDisk.c,
+	  gui-sdl/dlgFileSelect.c, gui-sdl/dlgMain.c, includes/int.h,
+	  includes/joy.h, includes/m68000.h, includes/main.h,
+	  includes/memorySnapShot.h, includes/mfp.h, includes/options.h,
+	  includes/printer.h, includes/psg.h, includes/rs232.h,
+	  includes/screen.h, includes/screenSnapShot.h, includes/sdlgui.h,
+	  includes/shortcut.h, includes/spec512.h, includes/tos.h,
+	  includes/video.h, includes/xbios.h, includes/zip.h: BOOL ==> bool
+
+2008-05-25 12:54  Eero Tamminen
+
+	* src/: configuration.c, options.c: fix bFastForward config
+	  variable type and improve -D option description
+
+2008-05-25 11:18  Thomas Huth
+
+	* src/blitter.c: Call IO mem handlers when the blitter writes to
+	  the IO registers. This is required for Protracker STE (by
+	  Equinox) for example.
+
+2008-05-23 17:10  Thomas Huth
+
+	* src/blitter.c: Ugly hack for the game Obsession: When the blitter
+	  is running in HOG mode, it seems to have a lower priority than
+	  DMA sound.
+
+2008-05-23 16:44  Thomas Huth
+
+	* src/main.c: Got to use RomMem instead of STRam for
+	  ENABLE_SMALL_MEM
+
+2008-05-23 16:18  Thomas Huth
+
+	* src/cart.c: Got to use RomMem instead of STRam for
+	  ENABLE_SMALL_MEM
+
+2008-05-21 21:46  Eero Tamminen
+
+	* doc/compatibility.html: re-test 20 years
+
+2008-05-21 19:50  Eero Tamminen
+
+	* doc/compatibility.html: Sierpinski overdose works
+
+2008-05-20 20:31  Eero Tamminen
+
+	* doc/compatibility.html: update for latest Blitter fixes
+
+2008-05-20 00:35  Thomas Huth
+
+	* src/blitter.c: The  Do_Blit function can now abort and resume
+	  exactly after 64 cycles. Also changed the way the blitting is
+	  started (not directly anymore when writing to the control
+	  register - it is now started after some few CPU cycles like on
+	  the real hardware)
+
+2008-05-19 23:00  Thomas Huth
+
+	* src/falcon/: hostscreen.c, hostscreen.h, nvram.c, videl.c:
+	  Replaced 'BOOL' by 'bool'
+
+2008-05-19 22:34  Thomas Huth
+
+	* src/: bios.c, cfgopts.c, configuration.c, createBlankImage.c,
+	  dialog.c, dim.c, dmaSnd.c, fdc.c, floppy.c, gemdos.c, hdc.c,
+	  ikbd.c, includes/bios.h, includes/configuration.h,
+	  includes/dialog.h, includes/dim.h, includes/dmaSnd.h,
+	  includes/fdc.h, includes/floppy.h, includes/gemdos.h,
+	  includes/hdc.h, includes/ikbd.h: Replaced 'BOOL' by 'bool'
+
+2008-05-19 22:12  Thomas Huth
+
+	* src/gui-osx/PrefsController.m: Made OS X GUI compilable again
+
+2008-05-19 02:07  Thomas Huth
+
+	* src/blitter.c: Enabled cycle accurate blitter emulation after
+	  fixing two remaining bugs. The game 'Roger' from Tobe works now
+	  with the right speed.
+
+2008-05-19 01:33  Thomas Huth
+
+	* src/: blitter.c, int.c, includes/blitter.h, includes/int.h: First
+	  steps towards cycle accurate blitter emulation (not working yet)
+
+2008-05-18 22:45  Thomas Huth
+
+	* src/blitter.c: Some more source code simplifications
+
+2008-05-10 19:42  Thomas Huth
+
+	* src/includes/control.h: Fixing some problems that occured when
+	  compiling Hatari with MinGW
+
+2008-05-10 00:38  Eero Tamminen
+
+	* src/control.c: improve remote control help + debugging
+
+2008-05-10 00:37  Eero Tamminen
+
+	* src/debugui.c: more places where flushing is needed
+
+2008-05-09 22:57  Eero Tamminen
+
+	* src/debugui.c: debug log needs to be flushed to get to file
+
+2008-05-09 22:55  Thomas Huth
+
+	* src/: blitter.c, ioMemTabFalcon.c, ioMemTabST.c, ioMemTabSTE.c,
+	  includes/blitter.h: More blitter code clean-up
+
+2008-05-09 21:11  Eero Tamminen
+
+	* src/: debugui.c, options.c: Allow setting command line options
+	  from the debugger with 'o' command.  If you still want to disable
+	  debugger from within the debugger, use "o -D" instead of "o".
+
+2008-05-09 20:25  Eero Tamminen
+
+	* src/: Makefile, change.c, control.c, main.c, options.c,
+	  includes/change.h, includes/control.h: control socket code
+	  changes: - move control socket code to its own control.c file -
+	  if sockets are not available, disable all control socket   socket
+	  related code instead of just functions using socket/select - add
+	  debugger remote control support - add support for stopping and
+	  continuing Hatari emulation	(needed for remote debugging) - add
+	  help also for top level remote commands (when   encountering
+	  command that it doesn't recognize)
+
+2008-05-09 20:19  Eero Tamminen
+
+	* src/debugui.c: - make debug logging robust also when calling
+	  input parser	 directly instead of through the debugger prompt
+
+2008-05-08 22:41  Eero Tamminen
+
+	* src/: debugui.c, includes/debugui.h: - BOOL -> bool - Prepare for
+	  external debug UI:   - make log file handling more robust (also
+	  renamed the variable)   - split command parsing out of the
+	  function reading it from user
+
+2008-05-07 22:53  Eero Tamminen
+
+	* src/: change.c, keymap.c, includes/change.h, includes/keymap.h: -
+	  support both ASCII chars and keycodes for key press/release
+	  simulation - move ASCII->keycode key simulation to keymap.c -
+	  change BOOL to bool in change.c
+
+2008-05-06 23:09  Eero Tamminen
+
+	* src/change.c: in the key press/release synthetizing: - ASCII
+	  characters need to be converted to ST keycodes - Uppercase
+	  characters need simulating also SHIFT press/release
+
+2008-05-06 20:05  Eero Tamminen
+
+	* configure.ac: - enable tracing by default - fix --disable-tracing
+	  and --disable-small-mem
+
+2008-05-05 21:39  Nicolas Pomarede
+
+	* src/sound.c: When setting period to 0, the YM seems to produce
+	  the same sound as if period was in fact set to 1 (fix ESwat buggy
+	  replay)
+
+2008-05-04 22:03  Thomas Huth
+
+	* src/: change.c, mfp.c, scandir.c: Fixed compiler warnings
+
+2008-05-04 21:21  Thomas Huth
+
+	* src/: Makefile, bios.c, fdc.c, gemdos.c, ikbd.c, keymap.c,
+	  main.c, misc.c, msa.c, reset.c, screen.c, sound.c, xbios.c,
+	  includes/misc.h: Removed misc.c and misc.h
+
+2008-05-04 21:08  Thomas Huth
+
+	* src/blitter.c: Removed the macro-mania from blitter.c ... the new
+	  code might be somewhat slower, but is hopefully much better
+	  maintainable and extensible now
+
+2008-05-04 19:43  Thomas Huth
+
+	* src/: debugui.c, str.c, includes/str.h: Moved string functions to
+	  str.c
+
+2008-05-04 19:30  Thomas Huth
+
+	* src/debugui.c: Fixed return value of function getRange()
+
+2008-05-03 22:20  Nicolas Pomarede
+
+	* src/fdc.c: More infos in the traces and add some 'FIXME' notes on
+	  type II read sector with bit 'm' set
+
+2008-05-03 21:09  Thomas Huth
+
+	* src/options.c: Boot always from floppy if it is specified after
+	  the hard disk directory
+
+2008-05-03 20:58  Thomas Huth
+
+	* src/: audio.c, blitter.c, file.c, log.c, main.c, msa.c, sound.c,
+	  st.c, vdi.c, wavFormat.c, ymFormat.c, includes/audio.h,
+	  includes/blitter.h, includes/file.h, includes/log.h,
+	  includes/main.h, includes/msa.h, includes/sound.h, includes/st.h,
+	  includes/vdi.h, includes/wavFormat.h, includes/ymFormat.h: The
+	  BOOL typedef in main.h always clashed with the definintion
+	  somewhere in windows.h - and something similar also happens on
+	  Mac OS X ... instead of always fixing the header inclusion order,
+	  it's maybe better to get rid of BOOL and use the defines from
+	  stdbool.h instead. These are now the first steps into this
+	  direction.
+
+2008-05-03 20:29  Thomas Huth
+
+	* config-default.h, configure.ac, src/change.c: Added autoconf
+	  check for unix domain sockets
+
+2008-04-28 23:26  Eero Tamminen
+
+	* src/: change.c, shortcut.c, includes/change.h,
+	  includes/shortcut.h: - disable control socket when WIN32 is
+	  defined   (--no-cygwin would require Winsock use) - add support
+	  for synthetizing rightclick/doubleclick/keyevent   through the
+	  control socket - change related functions to return error (FALSE)
+	  when they fail
+
+2008-04-28 22:22  Nicolas Pomarede
+
+	* src/fdc.c: Add more detailled traces for all commands
+
+2008-04-27 13:22  Nicolas Pomarede
+
+	* src/uae-cpu/: gencpu.c, readcpu.c: "strange" mode : Areg is
+	  possible as a source in move.b, eg move.b a1,(a0) (dc.w $1089)
+	  (Blood Money in Superior Compil 65)
+
+2008-04-26 00:17  Eero Tamminen
+
+	* src/change.c: - fix command debug output - read can include
+	  several commands send by the other end.    use newline to
+	  separate the commands
+
+2008-04-26 00:15  Eero Tamminen
+
+	* src/log.c: allow run-time disabling of all traces with 'none'
+
+2008-04-23 22:55  Eero Tamminen
+
+	* src/: Makefile, change.c, dialog.c, main.c, options.c,
+	  shortcut.c, includes/change.h, includes/options.h,
+	  includes/shortcut.h: - Move configuration change code from
+	  dialog.c to new change.c file - Return FALSE instead of exiting
+	  or errors in options.c option parsing - Exit in main.c if option
+	  parsing returns FALSE - Add new --control-socket Hatari option to
+	  options.c - call change.c socket/stdin checking function from
+	  main.c event loop - Receive command line options through socket
+	  or stdin in change.c	 and with help of option.c, change the co.
+	  settings - Add function to do shortcut actions based on their
+	  name to shortcut.c - call that from change.c
+
+2008-04-23 19:59  Nicolas Pomarede
+
+	* src/psg.c: Mask for noise period is 0x1f, not 0x3f ...
+
+2008-04-21 22:49  Eero Tamminen
+
+	* src/cfgopts.c: try fixing for Str_Trim() that really removes all
+	  whitespace
+
+2008-04-20 18:04  Eero Tamminen
+
+	* src/str.c: trim all white space instead of just spaces and tabs
+
+2008-04-20 15:11  Nicolas Pomarede
+
+	* src/psg.c: Mask bit 0-5 of reg 6 (noise period) in case a program
+	  would read it.
+
+2008-04-20 14:16  Nicolas Pomarede
+
+	* src/mfp.c: In TRACE call, replace get_long by STMemory_ReadLong,
+	  else we could get bus error when restoring a gemdos snapshot and
+	  --trace mfp_exception was used (because get_long checks we're in
+	  supervisor mode, which is not necessarily the case)
+
+2008-04-19 10:04  Nicolas Pomarede
+
+	* src/uae-cpu/newcpu.c: Add wait states extra cycles before testing
+	  pending interrupts
+
+2008-04-18 22:35  Nicolas Pomarede
+
+	* src/mfp.c: Handle read at $fffa21 occuring at the same time the
+	  Timer B counter is decremented by the end of line interrupt (fix
+	  flickering bottom border in B.I.G. Demo screen 1)
+
+2008-04-18 22:31  Nicolas Pomarede
+
+	* src/: cycles.c, video.c, includes/video.h: Handle read at $fffa21
+	  occuring at the same time the Timer B counter is decremented by
+	  the end of line interrupt (fix flickering bottom border in B.I.G.
+	  Demo screen 1)
+
+2008-04-18 19:02  Nicolas Pomarede
+
+	* src/uae-cpu/table68k: extb.l (8 bits -> 32 bits) is only
+	  available on CPUs >= 68020
+
+2008-04-16 20:49  Nicolas Pomarede
+
+	* src/m68000.c: Add pairing for LSR/ADD (and all variants) (Zoolook
+	  part in ULM New Year Demo)
+
+2008-04-15 23:51  Nicolas Pomarede
+
+	* src/: m68000.c, includes/m68000.h: Add some pairing combinations
+	  (verified on STF) : BTST/Bcc, MUL/DIV, MUL/MOVE, EXG/MOVE
+
+2008-04-14 00:11  Thomas Huth
+
+	* src/: Makefile, cfgopts.c, gemdos.c, keymap.c, misc.c, str.c,
+	  includes/misc.h, includes/str.h: Moved string functions to new
+	  file str.c
+
+2008-04-13 20:08  Nicolas Pomarede
+
+	* src/mfp.c: Add traces for Timer A/B in event count mode (ctrl=8)
+
+2008-04-12 17:41  Nicolas Pomarede
+
+	* src/video.c: Correct position of end of line / timer B interrupt
+	  when detecting a 'right-2' line.
+
+2008-04-11 22:24  Nicolas Pomarede
+
+	* src/: video.c, includes/video.h: Cycle precise position for the
+	  end of line / timer B interrupt, depending on the current freq
+	  (50 or 60 Hz) (slightly improve bottom border in B.I.G. Demo
+	  screen 1)
+
+2008-04-09 21:55  Eero Tamminen
+
+	* src/video.c: debug output to stderr if using printf
+
+2008-04-09 00:11  Thomas Huth
+
+	* src/gemdos.c: The emudrives structure is now saved into memory
+	  snapshots, too, so that the memory snapshots should now work
+	  better when GEMDOS HD emulation is turned on.
+
+2008-04-08 00:08  Nicolas Pomarede
+
+	* src/: video.c, includes/video.h: Use different values for
+	  VblVideoCycleOffset if system is STF or STE (4 cycles
+	  difference).	With the specific value of LineRemoveTopCycle on
+	  STE, this fixes the end part of Pacemaker by Paradox (which
+	  missed 8 cycles to work in STE mode)
+
+2008-04-07 23:47  Thomas Huth
+
+	* src/: gemdos.c, memorySnapShot.c: Added missing GEMDOS variable
+	  to memory snapshots
+
+2008-04-07 22:40  Eero Tamminen
+
+	* src/: options.c, includes/options.h, uae-cpu/newcpu.c: add bios +
+	  xbios interception debug option
+
+2008-04-07 21:49  Thomas Huth
+
+	* src/log.c: Fixed compiler warning
+
+2008-04-07 21:43  Thomas Huth
+
+	* src/: cart.c, includes/m68000.h, includes/main.h: Moved the 68k
+	  related #defines from main.h to m68000.h
+
+2008-04-07 21:04  Eero Tamminen
+
+	* configure.ac: fix HATARI_TRACE_ACTIVATED define name
+
+2008-04-06 21:20  Eero Tamminen
+
+	* src/: ikbd.c, mfp.c, psg.c, spec512.c, video.c: - revert some
+	  tracing changes, Nicolas likes the earlier way better   (when
+	  HATARI_TRACE_PRINT is defined always to printf, compiler
+	  warnings about unused variables go away)
+
+2008-04-06 21:16  Eero Tamminen
+
+	* src/includes/log.h: fix AHATARI_TRACE_PRINT issue
+
+2008-04-06 20:38  Eero Tamminen
+
+	* src/includes/log.h: add gcc format parameter checks for logging
+
+2008-04-06 20:37  Eero Tamminen
+
+	* src/includes/ikbd.h: remove protos for static functions
+
+2008-04-06 14:57  Eero Tamminen
+
+	* src/ikbd.c: declare locally used functions static
+
+2008-04-06 14:39  Eero Tamminen
+
+	* src/: ikbd.c, log.c, mfp.c, psg.c, spec512.c, video.c,
+	  includes/log.h, uae-cpu/newcpu.c: - make sure nothing of tracing
+	  is left in code when it's disabled - as tracing help code is
+	  still there, allow seeing it when tracing   is otherwise disabled
+
+2008-04-06 13:58  Eero Tamminen
+
+	* src/includes/log.h: fix include
+
+2008-04-06 13:20  Eero Tamminen
+
+	* configure.ac, src/includes/log.h: Move HATARI_TRACE_ACTIVATED
+	  from src/includes/log.h to top level config.h and add configure
+	  option for enabling tracing to configure.ac.	By default tracing
+	  is disabled, you need to use configure or enable tracing from
+	  config.h now.
+
+2008-04-06 12:33  Eero Tamminen
+
+	* src/: log.c, vdi.c, includes/log.h: add VDI tracing
+
+2008-04-06 11:07  Eero Tamminen
+
+	* src/: bios.c, gemdos.c, log.c, options.c, xbios.c,
+	  includes/log.h: - add tracing to bios, xbios and gemdos (what
+	  functions are called) - better log option parsing function names
+	  & returntype
+
+2008-04-06 11:01  Eero Tamminen
+
+	* src/shortcut.c: adding missing include
+
+2008-04-04 23:18  Eero Tamminen
+
+	* src/: configuration.c, keymap.c, shortcut.c,
+	  includes/configuration.h: make debug interface shorcut
+	  configurable
+
+2008-04-04 22:57  Eero Tamminen
+
+	* src/: configuration.c, log.c, main.c, options.c,
+	  includes/configuration.h, includes/log.h: add options for: - text
+	  and alert log levels - trace file (also new config option) if log
+	  or trace file open fails, exit
+
+2008-04-04 00:17  Nicolas Pomarede
+
+	* src/: video.c, includes/video.h: Use different values for
+	  RestartVideoCounterCycle if system is STF or STE.
+
+2008-04-03 23:15  Eero Tamminen
+
+	* src/gemdos.c: ERROR -> WARN (not serious enough to need a dialog)
+
+2008-04-03 23:11  Eero Tamminen
+
+	* src/: configuration.c, fdc.c, hdc.c, main.c, memorySnapShot.c,
+	  tos.c, ymFormat.c, falcon/nvram.c, includes/log.h: - add LOG_TODO
+	  log level for features that are not yet emulated   and convert
+	  some LOG_DEBUGs to it - finetune log levels in preparation of
+	  joining of Log_Printf()   and Log_AlertDlg()
+
+2008-04-03 22:35  Eero Tamminen
+
+	* src/: log.c, includes/log.h: HatariTraceLevel -> HatariTraceFlags
+	  (more correct name)
+
+2008-04-03 22:30  Eero Tamminen
+
+	* src/: Makefile, fdc.c, ikbd.c, int.c, log.c, mfp.c, options.c,
+	  psg.c, spec512.c, trace.c, video.c, includes/log.h,
+	  includes/m68000.h, includes/trace.h, uae-cpu/newcpu.c: - join
+	  trace.c/h to log.c/h - improve make depend
+
+2008-04-03 22:27  Eero Tamminen
+
+	* src/falcon/nvram.c: one more missing nMonitorType change
+
+2008-04-03 22:19  Eero Tamminen
+
+	* src/gui-sdl/dlgScreen.c: missed nFrameSkips & nMonitorType
+	  changes
+
+2008-04-03 19:42  Nicolas Pomarede
+
+	* src/video.c: Remove fprintf used for debug
+
+2008-04-02 22:55  Nicolas Pomarede
+
+	* src/video.c: Correct a wrong value of nStartHBL when going 60Hz
+	  between cycles 508 and 512 on line 33.
+
+2008-04-02 20:02  Eero Tamminen
+
+	* src/ymFormat.c: failure needs WARN, not INFO
+
+2008-03-31 19:28  Eero Tamminen
+
+	* src/: video.c, includes/configuration.h, configuration.c,
+	  dialog.c, keymap.c, main.c, options.c, screen.c, shortcut.c,
+	  stMemory.c: - add "n" (numeric) prefix to FrameSkips &
+	  MonitorType for consistency - rename nMinMaxSpeed to more correct
+	  bFastForward option and make it bool - add --fast-forward command
+	  line option
+
+2008-03-31 00:24  Nicolas Pomarede
+
+	* src/int.c: ActiveInterrupt was not saved in the snapshot, which
+	  randomly caused errors when restoring a snapshot doing video/cpu
+	  synchronization.  Call Int_SetNewInterrupt() after loading the
+	  snapshot to correctly set internal state.
+
+2008-03-30 22:47  Eero Tamminen
+
+	* src/log.c: if \n missing, add it like in the other function
+
+2008-03-30 : *** Version 1.0.1 ***
+
+2008-03-30 12:38  Thomas Huth
+
+	* Info-Hatari.plist, configure.ac, hatari.spec, readme.txt,
+	  doc/release-notes.txt, doc/doxygen/Doxyfile,
+	  src/gui-osx/English.lproj/InfoPlist.strings, src/includes/main.h:
+	  Changes for bug-fixed version 1.0.1
+
+2008-03-30 12:08  Thomas Huth
+
+	* src/trace.c: Print an error message when trace code has not been
+	  compiled in, but the user still wants to use it.
+
+2008-03-30 00:03  Thomas Huth
+
+	* src/uae-cpu/add_cycles.pl: add_cycles.pl is not required anymore
+	  (it's done in gencpu.c already).
+
+2008-03-30 00:01  Thomas Huth
+
+	* src/memorySnapShot.c: Video_SetSystemTimings is already done
+	  during reset, no need to do it here again.
+
+2008-03-29 21:33  Thomas Huth
+
+	* src/convert/: macros.h, spec320x16.c, spec320x32.c, spec640x16.c,
+	  spec640x32.c: The spec512 conversion routines did not work on
+	  little endian ARM CPUs yet due to an unaligned memory access.
+	  Introduced GET_SPEC512_OFFSET_PIXELS macro to fix this problem.
+
+2008-03-29 17:59  Thomas Huth
+
+	* src/rs232.c: Replaced STRam with IoMem
+
+2008-03-29 12:05  Nicolas Pomarede
+
+	* src/: video.c, memorySnapShot.c, includes/video.h: Use different
+	  video timings depending on the machine type. For example on STE,
+	  top/bottom border removal can occur at cycle 500 instead of 504
+	  on STF (fix bottom border in the game 'Skulls')
+
+2008-03-28 23:33  Eero Tamminen
+
+	* src/main.c: for some reason (race condition?) destroying SDL
+	  wmwindow can cause an X error when the actual SDL window is
+	  reparented.  It works better if the wmwindow is just unmapped.
+
+2008-03-28 18:48  Eero Tamminen
+
+	* src/trace.c: stdlib.h needed for free()
+
+2008-03-26 23:31  Thomas Huth
+
+	* doc/authors.txt: Added Fredrik Noring
+
+2008-03-26 23:15  Thomas Huth
+
+	* src/: ioMem.c, psg.c: Rewrote the PSG mirror register code to
+	  handle the case when a program writes a long-word to 0xff8802
+	  (MOVE.L #xyz,$ffff8802). Before this change the PSG shadow
+	  register at 0xff8804 was not used yet (happens e.g. in sampling
+	  screens in the Lost Boys "Ooh Crikey Wot A Scorcher"). Big thanks
+	  to Fredrik Noring for the hint!
+
+2008-03-26 21:16  Eero Tamminen
+
+	* src/screen.c: Thomas noted that windowed mode used SW_SURFACE
+	  whereas fullscreen uses HW_SURFACE.  On my machine it didn't make
+	  any difference...  I suspect SDL just doesn't use HW_SURFACE if
+	  one isn't available (on my machine & SDL version?), but I'll
+	  revert the this part to be sure it doesn't break anything.
+
+2008-03-26 20:19  Eero Tamminen
+
+	* src/screen.c: remove rendundant check, clearer fullscreen check
+
+2008-03-26 20:17  Nicolas Pomarede
+
+	* src/video.c: Clear unused pixels for border tricks left+2, left+8
+	  and right-106
+
+2008-03-26 19:45  Thomas Huth
+
+	* src/screen.c: Use the right rendering functions when the SDL
+	  suggests bit depth = 8.
+
+2008-03-25 22:50  Eero Tamminen
+
+	* src/options.c: restore 15-bit support option
+
+2008-03-25 20:26  Nicolas Pomarede
+
+	* src/video.c: On STE, add 16 pixels to the left border instead of
+	  the right one when doing move.w #1,$ffff8264 / clr.b $ffff8264
+	  (Just Musix 2 Menu by DHS)
+
+2008-03-25 19:06  Thomas Huth
+
+	* src/blitter.c: Do not increment source address when using Blitter
+	  operation mode 0 or 15. This fixes the Grotesque demo by Omega.
+	  Thanks to Fredrik Noring for the hint!
+
+2008-03-19 01:24  Thomas Huth
+
+	* src/spec512.c: Make sure that scan line count does not get higher
+	  than max amount of allowed scanlines. (This fix is needed for Dan
+	  Dare 3, for example)
+
+2008-03-19 00:56  Thomas Huth
+
+	* src/uae-cpu/: .cvsignore, Makefile: Automatic dependencies for
+	  the UAE CPU core Makefile
+
+2008-03-18 01:56  Thomas Huth
+
+	* Makefile-MinGW.cnf, src/file.c, src/paths.c,
+	  src/gui-sdl/dlgDisk.c: Fixing some problems that occured when
+	  compiling Hatari with MinGW
+
+2008-03-17 17:27  Thomas Huth
+
+	* src/main.c: Full screen resolution is already set correctly
+	  during screen init, there is no need anymore to do it here again.
+
+2008-03-17 : *** Version 1.0.0 ***
+
+2008-03-17 15:15  Thomas Huth
+
+	* configure.ac, src/main.c: Fixed X11 window reparenting checks
+
+2008-03-17 12:40  Thomas Huth
+
+	* Info-Hatari.plist, readme.txt, doc/release-notes.txt,
+	  doc/doxygen/Doxyfile, src/includes/main.h: Update for version
+	  1.0.0
+
+2008-03-14 21:13  Nicolas Pomarede
+
+	* src/video.c: Handle writes to ff8205/07/09, linewidth and hw
+	  scroll that overlaps the end of the line.  Apply linewidth before
+	  changing video address.  (bump mapping part in Pacemaker by
+	  Paradox and maze part in Braindamage by Agression)
+
+2008-03-14 10:42  Thomas Huth
+
+	* doc/: hatari.1, manual.html, fr/hatari.1: Updated the command
+	  line options to match the current executable again.
+
+2008-03-14 00:17  Thomas Huth
+
+	* src/: fdc.c, reset.c: Slightly improved FDC update interrupt
+	  handling. This fixes the NO COOPER demo loader problem.
+
+2008-03-13 23:08  Thomas Huth
+
+	* configure.ac: Added comment about autoreconf
+
+2008-03-13 21:32  Eero Tamminen
+
+	* Makefile.cnf.in, configure.ac, src/main.c: * Makefile.cnf.in,
+	  configure.ac: add optional X11 support for embedding * main.c: if
+	  PARENT_WIN_ID environment variable is set,   embed Hatari SDL
+	  window inside the indicated window
+
+2008-03-13 20:26  Thomas Huth
+
+	* Hatari.xcodeproj/project.pbxproj: Building Hatari without
+	  optimization is a _very_ bad idea... enabled -O2 for XCode builds
+	  now.
+
+2008-03-13 13:32  Thomas Huth
+
+	* src/options.c: --debug is only used for turning debugging on,
+	  since there is no need to turn this off (it's not saved in the
+	  config file)
+
+2008-03-11 21:11  Eero Tamminen
+
+	* src/: configuration.c, options.c, spec512.c,
+	  includes/configuration.h: * Add --spec512 option controlling the
+	  compromize between color   display accuracy with spec512 tricks
+	  and (huge) performance   penalty.  * remove redundant check from
+	  --bpp option
+
+2008-03-11 15:31  Thomas Huth
+
+	* src/screen.c: Screen must be updated completely when switching
+	  back from Spec512 rendering to normal mode. This fixes some gfx
+	  glitches in Paul Simoes Overscan demo for example.
+
+2008-03-11 14:50  Thomas Huth
+
+	* src/: includes/m68000.h, uae-cpu/newcpu.c: Cycle pairing is now
+	  only taken into consideration in the function m68k_run, between
+	  two opcodes.
+
+2008-03-10 23:36  Thomas Huth
+
+	* src/: options.c, screen.c: Allow to use the 32 bpp screen
+	  rendering functions
+
+2008-03-10 22:57  Thomas Huth
+
+	* src/convert/: macros.h, routines.h, spec320x32.c, spec640x32.c:
+	  Added 32 bpp screen conversion functions for Spec512 screens
+
+2008-03-10 19:53  Thomas Huth
+
+	* src/convert/: low320x32.c, low640x32.c, macros.h, med640x32.c:
+	  Added 32 bpp screen conversion functions for low and medium
+	  resolution
+
+2008-03-09 13:53  Nicolas Pomarede
+
+	* src/: mfp.c, m68000.c, video.c, includes/m68000.h: Fix exception
+	  processing when MFP vector base $fffa17 is changed to $10 ('Toki'
+	  end part fullscreen)
+
+2008-03-09 02:42  clafou
+
+	* Hatari.xcodeproj/project.pbxproj: Updated XCode Project file
+
+2008-03-08 14:12  Nicolas Pomarede
+
+	* src/: mfp.c, trace.c, includes/trace.h: Add trace when writing to
+	  MFP registers
+
+2008-03-07 01:41  Thomas Huth
+
+	* src/reset.c: Start FDC 'update interrupt' after reset.
+
+2008-03-03 22:08  Thomas Huth
+
+	* src/gui-osx/PrefsController.m: Made the OS X preferences dialog
+	  compilable again
+
+2008-03-03 21:01  Thomas Huth
+
+	* src/gui-osx/SDLMain.m: Updated calls to
+	  Floppy_InsertDiskIntoDrive and MemorSnapShot_Capture/Restore
+	  (they have additional parameters now)
+
+2008-03-02 21:14  Eero Tamminen
+
+	* doc/hatari.1, src/options.c: move TOS under memory options
+
+2008-03-02 21:09  Eero Tamminen
+
+	* doc/hatari.1: split system options to further memory and CPU
+	  options, and otherwise re-order options according to Hatari help
+
+2008-03-02 21:03  Eero Tamminen
+
+	* src/options.c: * -m is still useful, we're not going to remove it
+	  for v1.0 * split system options to:	- memory options   - cpu
+	  options   - misc system options * reorder sections a bit so that
+	  more commonly used items are first
+
+2008-03-02 20:45  Eero Tamminen
+
+	* src/options.c: - fix the option ID given to help/exit function -
+	  don't assume things, exit on all parsing issues (joystick &
+	  memsize)
+
+2008-03-01 23:56  Eero Tamminen
+
+	* doc/hatari.1, src/options.c: separate section for VDI options
+
+2008-03-01 23:40  Eero Tamminen
+
+	* doc/hatari.1: update options
+
+2008-03-01 23:37  Eero Tamminen
+
+	* src/: configuration.c, dialog.c, options.c, screen.c,
+	  gui-sdl/dlgScreen.c, includes/configuration.h: As discussed on
+	  the devel list: * convert --force8bpp (boolean) to --bpp
+	  (integer) option * --sound supports now off/low/mid/hi for
+	  enabling/disabling   sound and setting it's quality * added
+	  --cpuclock option
+
+2008-03-01 22:49  Eero Tamminen
+
+	* src/options.c: move --slowfdc to disk options
+
+2008-03-01 22:13  Eero Tamminen
+
+	* doc/hatari.1: split options to categories, similarly as in hatari
+	  -h add missing options and capitalize option descriptions
+
+2008-03-01 21:54  Eero Tamminen
+
+	* src/options.c: add true/false to bool alternatives
+
+2008-03-01 21:47  Eero Tamminen
+
+	* src/options.c: - "none" can be used as filename to disable
+	  devices and HDs - fix to sound bool
+
+2008-03-01 21:00  Eero Tamminen
+
+	* src/options.c: set the order of options in the parsing fuction to
+	  same as in the option output sections
+
+2008-03-01 20:33  Eero Tamminen
+
+	* src/: Makefile, main.c: Oops... Revert embed testing code
+
+2008-03-01 20:27  Eero Tamminen
+
+	* src/: Makefile, main.c, options.c: * These were now converted to
+	  take a  argument so that they	can also be disabled:
+	  --borders    --force8bpp 	--compatible 
+	  --blitter    --slowfdc    --sound    (was earlier
+	  --nosound) * If floppy is given, but no HD (dir), disable booting
+	  from HD
+
+2008-03-01 18:59  Eero Tamminen
+
+	* src/options.c: add support for option sections and split options
+	  to sections
+
+2008-02-29 23:42  Thomas Huth
+
+	* doc/manual.html: Some minor improvements
+
+2008-02-29 22:12  Thomas Huth
+
+	* doc/todo.txt: Updated the TODO list
+
+2008-02-29 22:11  Thomas Huth
+
+	* src/: fdc.c, int.c, video.c, includes/fdc.h, includes/int.h: The
+	  FDC update is now done with a dedicated 'interrupt' function
+	  instead of using the HBL (which is no longer hardwired to 512
+	  cycles, so this was quite a way to update the FDC nowadays).
+
+2008-02-29 21:24  Thomas Huth
+
+	* src/: gui-sdl/dlgAlert.c, gui-sdl/dlgFileSelect.c,
+	  gui-sdl/dlgMain.c, gui-sdl/sdlgui.c, includes/sdlgui.h: Cancel
+	  buttons can now be activated by pressing the ESC key.
+
+2008-02-29 20:22  Thomas Huth
+
+	* src/convert/: spec320x16.c, spec640x16.c: Fixed Spec512 plotting
+	  on big endian machines.
+
+2008-02-26 21:50  Eero Tamminen
+
+	* src/options.c: fix -j description, fit --trace description to 80
+	  chars
+
+2008-02-24 23:34  Thomas Huth
+
+	* src/configuration.c: Use compatible CPU and high sound quality as
+	  default settings
+
+2008-02-24 23:28  Thomas Huth
+
+	* src/configuration.c: Disable auto-save by default
+
+2008-02-24 21:56  Eero Tamminen
+
+	* doc/manual.html: Minor updates for 1.0 and couple of typo fixes
+
+2008-02-24 21:45  Thomas Huth
+
+	* doc/hatari.1, src/m68000.c, src/options.c,
+	  src/includes/options.h: Added --memstate command line option.
+
+2008-02-24 21:10  Thomas Huth
+
+	* src/: configuration.c, m68000.c, main.c, memorySnapShot.c,
+	  shortcut.c, gui-sdl/dlgMemory.c, includes/configuration.h,
+	  includes/m68000.h, includes/memorySnapShot.h,
+	  uae-cpu/hatari-glue.c, uae-cpu/hatari-glue.h: It is now possible
+	  to automatically load/save memory snap-shots at start/exit
+
+2008-02-23 23:16  Thomas Huth
+
+	* src/gui-sdl/: dlgKeyboard.c, dlgMain.c, dlgMemory.c, dlgScreen.c,
+	  dlgSound.c, sdlgui.c: Sourcecode beautification
+
+2008-02-23 23:14  Thomas Huth
+
+	* src/: Makefile, gui-sdl/Makefile, gui-sdl/dlgDisc.c,
+	  gui-sdl/dlgDisk.c, gui-sdl/dlgNewDisc.c, gui-sdl/dlgNewDisk.c:
+	  Renamed dlg*Disc.c into dlg*Disk.c
+
+2008-02-23 22:15  Thomas Huth
+
+	* src/falcon/nvram.c: Fix compiler warning
+
+2008-02-23 22:15  Thomas Huth
+
+	* src/convert/: high640x8.c, low320x16.c, low320x8.c, low640x16.c,
+	  low640x8.c, med640x16.c, med640x8.c, spec320x16.c, spec640x16.c,
+	  vdi16.c, vdi2.c, vdi4.c: Sourcecode beautification
+
+2008-02-23 17:51  Thomas Huth
+
+	* src/: configuration.c, paths.c, printer.c, falcon/nvram.c:
+	  Introduced ~/.hatari directory. Configuration file, hatari.nvram
+	  and some other files are now loaded from this directory instead
+	  of $HOME.
+
+2008-02-23 16:30  Thomas Huth
+
+	* src/: configuration.c, screen.c, includes/configuration.h,
+	  includes/screen.h: The size of the left and right border can now
+	  be configured in the configuration file of Hatari.
+
+2008-02-21 23:34  Thomas Huth
+
+	* src/: Makefile, screen.c, convert/high640x1.c,
+	  convert/routines.h, convert/vdi2.c: Removed unused convert
+	  functions
+
+2008-02-21 23:24  Thomas Huth
+
+	* doc/todo.txt: Added some more TODO items
+
+2008-02-20 23:47  Thomas Huth
+
+	* src/: Makefile, configuration.c, main.c, paths.c, screen.c,
+	  screenSnapShot.c, includes/main.h, includes/paths.h: Moved path
+	  handling to a separate file, paths.c
+
+2008-02-20 22:03  Eero Tamminen
+
+	* doc/compatibility.html: update
+
+2008-02-20 21:31  Nicolas Pomarede
+
+	* src/video.c: Fix typo.
+
+2008-02-20 21:07  Nicolas Pomarede
+
+	* src/: ioMem.c, video.c, includes/ioMem.h, includes/video.h:
+	  Better support for writing to ff8205/07/09 on STE.
+
+2008-02-19 22:19  Eero Tamminen
+
+	* doc/compatibility.html: major improvements on Coreflakes and
+	  minor one on Braindamage demo
+
+2008-02-19 19:51  Eero Tamminen
+
+	* src/memorySnapShot.c: Add missing include for FPU save/restore
+	  functions
+
+2008-02-19 00:24  Nicolas Pomarede
+
+	* src/: ioMemTabFalcon.c, ioMemTabST.c, ioMemTabSTE.c,
+	  ioMemTabTT.c, video.c: Improve reading/writing video counter and
+	  apply LineWidth in the correct order on STE.
+
+2008-02-17 17:40  Eero Tamminen
+
+	* doc/compatibility.html: E605 demo works now
+
+2008-02-16 19:05  Nicolas Pomarede
+
+	* src/m68000.c: FPU save/restore was removed by mistake
+
+2008-02-16 15:04  Nicolas Pomarede
+
+	* src/m68000.c: Add pairing for MULS/DIVS (needs to be checked on a
+	  real ST)
+
+2008-02-15 23:31  Eero Tamminen
+
+	* doc/compatibility.html: update 2 ST demos
+
+2008-02-12 23:05  Nicolas Pomarede
+
+	* src/m68000.c: Add pairing for LSR/MOVEA (and all other bit
+	  shifting instructions)
+
+2008-02-11 23:35  Nicolas Pomarede
+
+	* src/m68000.c: Add pairing for MULS/MOVEA
+
+2008-02-11 00:22  Thomas Huth
+
+	* src/gui-osx/English.lproj/InfoPlist.strings: Increased version
+	  number
+
+2008-02-10 20:42  Thomas Huth
+
+	* doc/fr/hatari.1: Updated the french translation of the man page
+	  (thanks to Tudori Benoit for the update)
+
+2008-02-09 22:39  Thomas Huth
+
+	* doc/todo.txt, src/includes/screen.h: Set SCREENBYTES_LEFT again
+	  to 16 so that the Hatari screen fits into a 800x600 fullscreen
+	  resolution again. This really should be made more flexible one
+	  day...
+
+2008-02-09 12:15  Thomas Huth
+
+	* src/: m68000.c, memorySnapShot.c, uae-cpu/fpp.c,
+	  uae-cpu/savestate.h: Save FPU register in memory snapshots, too
+
+2008-02-09 11:42  Thomas Huth
+
+	* src/video.c: Silenced compiler warning
+
+2008-02-09 09:35  Thomas Huth
+
+	* src/video.c: Fixed STE hw scrolling of last pixels in a line when
+	  the right border has been opened (Mind Rewind and E605 demos).
+
+2008-02-08 21:15  Nicolas Pomarede
+
+	* src/video.c: Handle overscan lines combined with horizontal
+	  scroll on STE
+
+2008-02-08 20:02  Nicolas Pomarede
+
+	* src/m68000.c: Add pairing for LSL/LEA (and all other bit shifting
+	  instructions)
+
+2008-02-07 00:15  Nicolas Pomarede
+
+	* src/mfp.c: Handle "fast" MFP timer, no more need to patch the
+	  TOS's timer D
+
+2008-02-06 23:14  Thomas Huth
+
+	* doc/images/screen.png: Updated screenshot of screen dialog
+
+2008-02-06 22:35  Eero Tamminen
+
+	* doc/compatibility.html: - update compatibility notes for few of
+	  the programs - add generic status notes for ST & STE
+	  compatibility
+
+2008-02-06 01:05  Thomas Huth
+
+	* doc/compatibility.html: Added Pirates, some HTML cleanup
+
+2008-02-05 23:31  Thomas Huth
+
+	* Makefile, Makefile-default.cnf: 'make install' must fail if the
+	  user did not configured the Makefile.cnf properly
+
+2008-02-04 23:09  Nicolas Pomarede
+
+	* src/video.c: Better handling of writes to hwscroll on STE
+
+2008-02-04 22:41  Thomas Huth
+
+	* src/uae-cpu/: Makefile, gencpu.c: Found a nice way to patch-in
+	  the CurrentInstructionCycles without using the perl script (so
+	  there is one dependency less for building Hatari)
+
+2008-02-04 22:01  Eero Tamminen
+
+	* doc/compatibility.html: update
+
+2008-02-04 19:11  Thomas Huth
+
+	* src/gui-sdl/sdlgui.c: When editing a text field in a dialog,
+	  enable the SDL unicode translation to be able to also get the
+	  non-alphanumerical characters from the keyboard
+
+2008-02-04 00:36  Thomas Huth
+
+	* src/video.c: Do not set pNewVideoRaster before first visible line
+	  on the screen
+
+2008-02-03 23:52  Thomas Huth
+
+	* src/options.c: --vdi-planes takes a parameter, so show this in
+	  the help text
+
+2008-02-03 23:00  Nicolas Pomarede
+
+	* src/video.c: Better handling of writes to video counter addr on
+	  STE
+
+2008-02-03 20:29  Thomas Huth
+
+	* doc/emutos.txt: Added a short note about the tos.img that is
+	  shipped with the official releases of Hatari. (text is based on
+	  the README.tos file which is part of the Fedora RPM of Hatari)
+
+2008-02-03 19:31  Eero Tamminen
+
+	* doc/compatibility.html: - add compatibility notes section - note
+	  which items need Hatari v1.0 and/or TOS 1.2
+
+2008-02-03 15:33  Thomas Huth
+
+	* doc/hatari.1: Updated the man-page
+
+2008-02-03 15:04  Thomas Huth
+
+	* doc/: authors.txt, compatibility.html: Updated the documentation
+
+2008-02-02 19:18  Nicolas Pomarede
+
+	* src/: trace.c, includes/trace.h: Add a trace option for STE video
+	  registers (video_ste)
+
+2008-02-02 18:33  Nicolas Pomarede
+
+	* src/: video.c, includes/video.h: Improve detection of left border
+	  removal and 0 byte line by switching res
+
+2008-02-02 18:30  Nicolas Pomarede
+
+	* src/m68000.c: Add pairing for CMP/Bcc
+
+2008-02-02 18:20  Nicolas Pomarede
+
+	* src/uae-cpu/add_cycles.pl: Change comments
+
+2008-02-01 23:08  Thomas Huth
+
+	* doc/: compatibility.html, todo.txt: Updated the compatibility
+	  list a little bit
+
+2008-02-01 07:03  Thomas Huth
+
+	* src/uae-cpu/newcpu.c: Run all pending interrupt functions after
+	  each instruction to avoid starvation of lesser frequent functions
+	  (this fixes the problems that occured recently when 'patch
+	  timer-d' was disabled)
+
+2008-01-31 16:49  Eero Tamminen
+
+	* doc/todo.txt: put disk image format todos under one heading
+
+2008-01-28 23:20  Thomas Huth
+
+	* doc/release-notes.txt, doc/todo.txt, src/dmaSnd.c, src/ikbd.c,
+	  src/int.c, src/memorySnapShot.c, src/mfp.c, src/screen.c,
+	  src/spec512.c, src/video.c, src/includes/ikbd.h,
+	  src/includes/int.h, src/includes/m68000.h, src/includes/screen.h:
+	  Merged the remaining patches from Nicolas Pomarede: Improved MFP
+	  emulation, better support for sync-scrolling and other video
+	  tricks, ACIA reset emulation, and improved Int_* functions
+
+2008-01-28 08:46  Thomas Huth
+
+	* src/uae-cpu/gencpu.c: More cycle fixes from Nicolas (BCLR timings
+	  and d8(An,Xn) address mode timings, fixes Anomaly demo)
+
+2008-01-28 08:40  Thomas Huth
+
+	* src/m68000.c: Add pairing for LSR/MOVE (and all other bit
+	  shifting instructions). Thanks to Nicolas for the patch
+
+2008-01-26 21:29  Thomas Huth
+
+	* src/: m68000.c, includes/m68000.h: The next set of Nicolas'
+	  patches: Support for CPU instruction cycles pairing
+
+2008-01-26 17:44  Thomas Huth
+
+	* src/cart.c: Initialize Hatari's illegal opcodes only if really
+	  necessary (thanks to Nicolas Pomarede for this patch)
+
+2008-01-25 23:43  Thomas Huth
+
+	* src/uae-cpu/: Makefile, add_cycles.pl, gencpu.c, hatari-glue.h,
+	  newcpu.c, newcpu.h, readcpu.h: Added Nicolas Pomarede's CPU
+	  patches: Improved cycles emulation, exception stack frames,
+	  illegal opcodes, etc.
+
+2008-01-25 23:36  Thomas Huth
+
+	* src/uae-cpu/table68k: chk.l is only available on CPUs >= 68020
+	  (thanks to Nicolas Pomarede for the patch)
+
+2008-01-24 22:41  Thomas Huth
+
+	* src/: cycles.c, video.c, includes/cycles.h, includes/video.h:
+	  Some more of Nicolas Pomarede's patches: Preparation for CPU
+	  cycles and video updates
+
+2008-01-24 22:21  Thomas Huth
+
+	* src/: ioMemTabFalcon.c, ioMemTabST.c, ioMemTabSTE.c,
+	  ioMemTabTT.c, psg.c, includes/psg.h: Added Nicolas Pomarede's
+	  patch for improved PSG wait state cycles emulation
+
+2008-01-24 19:53  Thomas Huth
+
+	* src/: Makefile, fdc.c, options.c, trace.c, includes/fdc.h,
+	  includes/trace.h: Added Nicolas Pomarede's trace code (required
+	  for his upcoming other patches)
+
+2008-01-23 20:32  Thomas Huth
+
+	* src/xbios.c: Use the new M68000_GetPC() wrapper instead of
+	  m68k_getpc()
+
+2008-01-12 20:14  Eero Tamminen
+
+	* src/: file.c, gui-sdl/dlgDisc.c, gui-sdl/dlgFileSelect.c,
+	  gui-sdl/dlgNewDisc.c, includes/file.h, includes/sdlgui.h:
+	  Bugfixes to: - DlgFileSelect_HandleSdlEvents() caused invalid
+	  memory access - dlgNewDisc.c:Dialog_BrowseDisk() used the new
+	  filename even   when inserting the co. disk image failed
+
+	  Refactor SDLGui_FileSelect() completely: - make path arguments
+	  const and return the path instead of modifying   the arguments
+	  (making assumptions of their size)   - Modify dlgNewDisc.c
+	  functions and SDLGui_FileConfSelect() accordingly - split four
+	  functions out of it, two to file.c
+
+2008-01-12 19:22  Eero Tamminen
+
+	* src/zip.c: add missing newlines to Log_Printf()s
+
+2008-01-12 18:44  Eero Tamminen
+
+	* src/: zip.c, includes/zip.h: - fix string length assumption -
+	  const ZIP_GetFilesDir() args
+
+2008-01-12 03:04  Thomas Huth
+
+	* src/keymap.c: Added some more keymaps, useful on the MacBook
+	  (Thanks to Desty for the keymap list on atari-forum.com)
+
+2008-01-10 00:34  Thomas Huth
+
+	* src/: file.c, gemdos.c, includes/file.h: Fcreate must return
+	  PATH-NOT-FOUND when a program like ST-Zip 2.6 tries to create a
+	  file in a directory that does not exist yet.
+
+2008-01-07 22:54  Eero Tamminen
+
+	* src/floppy.c: return in correct place, otherwise you get disk
+	  inserted regardless of whether it actually succeeded or not (+
+	  zero/-1 malloc for driveB)
+
+2008-01-06 22:27  Eero Tamminen
+
+	* src/: screen.c, video.c, includes/screen.h: use defines for TT
+	  resolutions similarly to ST resolutions
+
+2008-01-06 21:43  Thomas Huth
+
+	* src/: screen.c, video.c, includes/screen.h, includes/video.h:
+	  Initialize the TTRes variable during reset. Also moved the STRes
+	  variable to video.c (it suits better to that file).
+
+2008-01-06 19:31  Eero Tamminen
+
+	* src/main.c: > The readlink function does not append a zero to the
+	  string, so we have
+	  > to zero the whole string memory before using readlink...
+
+	  It returns the number of bytes written, so just set terminator
+	  (still, a bad/ugly/inconsistent API)
+
+2008-01-06 17:42  Thomas Huth
+
+	* src/main.c: The readlink function does not append a zero to the
+	  string, so we have to zero the whole string memory before using
+	  readlink... (Thanks to Eero for the hint)
+
+2008-01-05 21:26  Thomas Huth
+
+	* src/video.c: Moved code that updates the TT palette into a new
+	  function. Also added special handling for monochrome TT video
+	  modes (palette seems to be hardwired to black and white there).
+
+2008-01-04 20:28  Thomas Huth
+
+	* src/main.c: The GetModuleFileName stuff does not work as
+	  expected... disabled it again.
+
+2008-01-04 12:13  Thomas Huth
+
+	* src/main.c: Some small improvements to the new datadir
+	  determination code.
+
+2008-01-03 20:32  Thomas Huth
+
+	* hatari.spec: Added 'Prefix:' line to create a relocatable RPM
+	  package.
+
+2008-01-03 20:13  Thomas Huth
+
+	* tools/hmsa/: Makefile, hmsa.c: hmsa is now compilable again.
+
+2008-01-03 13:09  Thomas Huth
+
+	* src/: includes/main.h, Makefile, configuration.c, main.c,
+	  scandir.c, screen.c, falcon/Makefile, gui-sdl/Makefile: Determine
+	  the locatation of the executable at runtime. The datadir is then
+	  calculated relative the the path of the executable. This way the
+	  Hatari package gets relocatable since there are no more absolute
+	  path names in the executable.
+
+2008-01-03 13:04  Thomas Huth
+
+	* .cvsignore: Added hatari.1.gz to cvsignore file.
+
+2008-01-02 22:48  Thomas Huth
+
+	* src/gemdos.c: Added missing defines for compiling with MinGW
+
+2008-01-02 21:55  Thomas Huth
+
+	* src/configuration.c: Fixed bug in config file handling: keyboard
+	  shortcuts without modifiers for loading and saving memory
+	  snapshots have been mapped to the wrong configuration variable.
+
+2008-01-02 21:33  Thomas Huth
+
+	* hatari.spec: Updated the RPM spec file to suit the latest version
+	  of the Makefiles.
+
+2008-01-02 21:30  Thomas Huth
+
+	* configure.ac: The @docdir@ autoconf variable is only available
+	  since autoconf 2.60. So this version is now the minimum
+	  prerequisite for the configure script of Hatari.
+
+2008-01-02 21:01  Thomas Huth
+
+	* src/rs232.c: Silenced 'uninitialized variable' warning that only
+	  occured when compiling with -O3 on GCC 4.1
+
+2008-01-02 13:51  Thomas Huth
+
+	* src/configuration.c: Removed special configuration for CeGCC
+	  again - this can be handled with a proper configuration file, so
+	  there is no need for this in the source code.
+
+2007-12-31 15:54  Thomas Huth
+
+	* src/joy.c: No need to include dialog.h in joy.c
+
+2007-12-31 15:23  Thomas Huth
+
+	* src/scandir.c: The scandir() function now also works with CeGCC.
+
+2007-12-31 14:05  Thomas Huth
+
+	* src/screen.c: Correctly set up bInFullScreen before setting the
+	  very first screen resolution.
+
+2007-12-31 13:21  Thomas Huth
+
+	* src/: ikbd.c, printer.c: Cleaned up #includes
+
+2007-12-30 21:43  Thomas Huth
+
+	* src/configuration.c: Added special configuration for Windows
+	  Mobile / CeGCC
+
+2007-12-30 21:02  Thomas Huth
+
+	* config-default.h, configure.ac, src/stMemory.c,
+	  src/falcon/Makefile, src/includes/ioMem.h,
+	  src/includes/stMemory.h, src/uae-cpu/Makefile,
+	  src/uae-cpu/memory.c: Added ENABLE_SMALL_MEM hack to force Hatari
+	  to use less memory (this is required for Windows Mobile / CeGCC
+	  which does not like things like the 16 MiB STRam array, causing a
+	  really huge BSS segment)
+
+2007-12-24 16:56  Thomas Huth
+
+	* config-default.h, configure.ac, src/main.c: Added proper check
+	  for setenv() function (required for Solaris)
+
+2007-12-23 19:54  Thomas Huth
+
+	* src/: debugui.c, uae-cpu/build68k.c, uae-cpu/readcpu.c:
+	  Parameters for functions from ctype.h should be unsigned (this is
+	  required for Solaris where the functions from ctype.h are
+	  implemented as macros which directly use the parameter as index
+	  into an array)
+
+2007-12-23 18:30  Thomas Huth
+
+	* src/scandir.c: Need to include stdlib.h for proper prototype of
+	  malloc when compiling for Solaris
+
+2007-12-21 22:41  Eero Tamminen
+
+	* Makefile: check for the case when Makefile-default.cnf or
+	  config-default.h file is newer than the user's own configuration
+	  and complain
+
+2007-12-20 13:12  Thomas Huth
+
+	* src/gemdos.c: Use HAVE_GLOB_H define instead of WIN32 define for
+	  testing for the availability of glob.h
+
+2007-12-20 13:11  Thomas Huth
+
+	* acsite.m4, config-default.h, configure.ac: Added BIN2DATADIR
+	  macro to be able to determine the datadir from the bindir (this
+	  is needed for relocatable RPMs etc.)
+
+2007-12-20 13:01  Thomas Huth
+
+	* src/file.c: Also handle a '.' when it is located at the very end
+	  of the path string (without trailing slash)
+
+2007-12-20 12:41  Thomas Huth
+
+	* src/file.c: Handle a '..' also when it is located at the very end
+	  of the path string (without trailing slash)
+
+2007-12-20 12:39  Thomas Huth
+
+	* config-MinGW.h, config-default.h: Merging the settings from
+	  config-MinGW.h into config-default.h, so that config-MinGW.h is
+	  not needed any longer.
+
+2007-12-20 01:37  Thomas Huth
+
+	* src/: vdi.c, video.c: More sourcecode beautification...
+
+2007-12-20 01:15  Thomas Huth
+
+	* src/: screen.c, shortcut.c, sound.c: More sourcecode
+	  beautification...
+
+2007-12-19 12:54  Thomas Huth
+
+	* src/: reset.c, rtc.c, screenSnapShot.c, xbios.c: Sourcecode
+	  beautification
+
+2007-12-19 12:13  Thomas Huth
+
+	* src/: mfp.c, misc.c, msa.c: Sourcecode beatification + clean-up
+
+2007-12-18 21:55  Thomas Huth
+
+	* config-default.h, configure.ac, src/rs232.c: Added checks for
+	  cfmakeraw and strings.h
+
+2007-12-18 21:35  Thomas Huth
+
+	* src/falcon/videl.c: videl.c uses STRam ... let's include
+	  stMemory.h
+
+2007-12-18 21:35  Thomas Huth
+
+	* src/: cfgopts.c, file.c, gemdos.c, memorySnapShot.c, scandir.c,
+	  unzip.c, zip.c: Put some pre-processor tests for strings.h into
+	  the include sections since some systems like CeGCC do not have
+	  strings.h.
+
+2007-12-18 19:56  Thomas Huth
+
+	* src/: cart.c, tos.c, includes/stMemory.h: Introduced RomMem
+	  'variable' to be able to separate the ROM accesses from the STRam
+	  accesses (sometimes in the future).
+
+2007-12-18 19:36  Thomas Huth
+
+	* src/rtc.c: Replaced STRam by IoMem
+
+2007-12-18 18:24  Thomas Huth
+
+	* src/dmaSnd.c: dmaSnd.c uses STRam, so let's include stMemory.h
+
+2007-12-18 18:09  Thomas Huth
+
+	* src/: reset.c, stMemory.c, tos.c: Moved memory init code to tos.c
+	  - we really should not touch the STRam before we've called
+	  memory_init().
+
+2007-12-18 00:42  Thomas Huth
+
+	* src/: m68000.c, main.c: Sourcecode beautification
+
+2007-12-18 00:03  Thomas Huth
+
+	* src/: ikbd.c, int.c, keymap.c: Sourcecode beautification
+
+2007-12-16 23:09  Eero Tamminen
+
+	* src/: file.c, floppy.c, main.c, gui-sdl/dlgFileSelect.c,
+	  includes/file.h, includes/floppy.h: next self-conttained set of
+	  patches that get rid of the assumption that all file strings are
+	  FILE_MAX sized: * Rename file.c functions to CamelCaps for
+	  consistency	* File_splitpath -> File_SplitPath   *
+	  File_makepath -> File_MakePath * File_MakePath() and
+	  File_FindPossibleExtFileName() return   an allocated path instead
+	  of modifying their arguments * Adopt floppy.c and dlgFileSelect.c
+	  to file.c changes * make Floppy_CreateDiskBFileName() and
+	  Floppy_ZipInsertDiskIntoDrive()   args const and to return the
+	  result instead of modifying the args *
+	  Floppy_InsertDiskIntoDrive() takes size arg for the argument it
+	  modifies -> Give that arg in main.c
+
+2007-12-16 22:47  Eero Tamminen
+
+	* doc/compatibility.html: update to latest CVS: addsub works,
+	  cavemania partially
+
+2007-12-14 03:09  Thomas Huth
+
+	* doc/compatibility.html: Added 'Stretch' STE screen  extender. And
+	  the Bird demo seems to be working again.
+
+2007-12-11 20:02  Eero Tamminen
+
+	* src/: gui-sdl/dlgDevice.c, gui-sdl/dlgDisc.c,
+	  gui-sdl/dlgFileSelect.c, gui-sdl/dlgKeyboard.c,
+	  gui-sdl/dlgMemory.c, gui-sdl/dlgRom.c, gui-sdl/dlgSound.c,
+	  includes/sdlgui.h: Clean up the SDL GUI code by adding a new
+	  function for file selection and removing the corresponding
+	  (slightly differing) codes from the other SDL GUI files. Refactor
+	  the large dlgDisc.c function at the same time.
+
+2007-12-11 01:41  Thomas Huth
+
+	* src/zip.c: Fixed off-by-one malloc bug (thanks to Eero for the
+	  hint!)
+
+2007-12-09 22:25  Eero Tamminen
+
+	* src/: video.c, includes/video.h: Add defines for mono/71Hz
+
+2007-12-04 00:56  Thomas Huth
+
+	* Makefile, Makefile.cnf.in: Also install the documentation files
+	  during a 'make install'
+
+2007-12-03 23:11  Thomas Huth
+
+	* src/: dialog.c, includes/dialog.h: Dialog_DoNeedReset is required
+	  for the Mac OS X GUI, too, so this function must not be static.
+
+2007-11-29 12:29  Thomas Huth
+
+	* src/stMemory.c: memtop and phystop must _always_ be dividable by
+	  512 or certain TOS versions might crash during boot.
+
+2007-11-29 12:13  Thomas Huth
+
+	* src/: vdi.c, includes/vdi.h, gui-sdl/dlgScreen.c: Allow a more
+	  fine granular stepping in the VDI screen resolution dialog.
+
+2007-11-25 16:14  Thomas Huth
+
+	* src/: gemdos.c, vdi.c, includes/gemdos.h: Check destination
+	  buffer length in GemDOS_CreateHardDriveFileName
+
+2007-11-25 15:31  Thomas Huth
+
+	* src/: configuration.c, dialog.c, memorySnapShot.c, options.c,
+	  vdi.c, gui-sdl/dlgScreen.c, includes/configuration.h,
+	  includes/vdi.h: Getting rid of the inflexible fixed-size VDI
+	  screen resolutions.
+
+2007-11-25 15:23  Thomas Huth
+
+	* src/stMemory.c: Screen size must _always_ be at least 32 kiB
+
+2007-11-25 15:05  Thomas Huth
+
+	* src/gui-sdl/dlgAlert.c: Fixed off-by-one bug in alert dialog
+	  formatting function
+
+2007-11-24 20:45  Thomas Huth
+
+	* src/stMemory.c: The VDI resolution screen size is now calculated
+	  in a more flexible way.
+
+2007-11-20 23:11  Thomas Huth
+
+	* src/gui-sdl/dlgAlert.c: Cosmetic changes for the source code and
+	  the alert dialog
+
+2007-11-19 22:20  Thomas Huth
+
+	* src/file.c: Fixed another bug: File_SplitPath did not work right
+	  anymore (path string was too short).
+
+2007-11-19 22:19  Thomas Huth
+
+	* src/: ikbd.c, memorySnapShot.c: Some IKBD variables were not
+	  saved in the memory snapshot file (caused problems with Airball)
+	  - this has been fixed now.
+
+2007-11-01 13:51  Thomas Huth
+
+	* src/options.c: Improved options parsing functions (nicer
+	  printout, and all strings are now copied with the new Opt_StrCpy
+	  function to simplify the code and to always avoid buffer
+	  overflows)
+
+2007-11-01 12:03  Thomas Huth
+
+	* src/zip.c: Set pointers to NULL after free'ing memory (to avoid
+	  the possibility of dangling pointers)
+
+2007-10-31 22:43  Eero Tamminen
+
+	* src/: file.c, includes/file.h: ...and File_Save() gets Uint8*
+	  too...
+
+2007-10-31 22:31  Eero Tamminen
+
+	* src/: cart.c, dim.c, file.c, main.c, msa.c, reset.c, st.c, tos.c,
+	  vdi.c, ymFormat.c, zip.c, includes/file.h, includes/ymFormat.h,
+	  includes/zip.h: * Add missing checks to file.c function   (and
+	  remove irrelevant "security lenght check" in Clean function) * In
+	  File_QueryOverwrite() alloc suitable sized buffer instead   of
+	  using FILENAME_MAX stack array * Const things that can be consted
+	  in file.c and zip.c	(and change one elseif construction to
+	  switch-case there too) * Remove the dangerous and unused pAddress
+	  argument from File_Read()   (it didn't have corresponding buffer
+	  size argument) * Remove casts in several files by setting
+	  File_Read() and File_Save   buffers to Uint8* and change unsigned
+	  int/char in msa.c to Uint8 & Uint16 * Set ymFormat.c global
+	  variables as static * Calling YMFormat_EndRecording() called
+	  YMFormat_FreeRecording(), so	 "inlined" latter (in main.c it's
+	  already called through Sound_EndRecording()) * ymFormat already
+	  gets filename in YMFormat_BeginRecording(),	so use that instead
+	  of getting it again from config in EndRecording.
+	  (Dialog_CopyDialogParamsToConfiguration() calls EndRecording()
+	  if recording is enabled so it cannot change in middle)
+
+2007-10-31 22:01  Eero Tamminen
+
+	* src/gui-sdl/dlgAlert.c: fix dialog text centering when there's
+	  only one line of text
+
+2007-10-31 00:33  Thomas Huth
+
+	* src/cfgopts.c: Add a newline after each section when creating new
+	  hatari.cfg files.
+
+2007-10-31 00:22  Thomas Huth
+
+	* src/configuration.c: Only convert keyboard MappingFileName string
+	  to absolute path if it really contains a valid string
+
+2007-10-30 02:13  Thomas Huth
+
+	* src/spec512.c: Fixed buffer overflow in ST high so that this mode
+	  now works stable again.
+
+2007-10-25 01:19  Thomas Huth
+
+	* src/video.c: Use 224 cycles per line in monochrome mode - seems
+	  to be a more reasonable value than 226 cycles.
+
+2007-10-23 23:02  Thomas Huth
+
+	* src/video.c: Monochrome mode now runs in 71 Hz, and 60 Hz color
+	  mode now also really runs with 60 Hz refresh rate
+
+2007-10-23 22:00  Thomas Huth
+
+	* src/: configuration.c, main.c, options.c,
+	  includes/configuration.h: Moved bConfirmQuit from System to Log
+	  section
+
+2007-10-21 16:50  Eero Tamminen
+
+	* src/: video.c, includes/video.h: more global variables that can
+	  be static
+
+2007-10-21 14:21  Eero Tamminen
+
+	* src/: includes/vdi.h, vdi.c: - min VDI size 320x200 - align up
+	  from min limit, down from max limit
+
+2007-10-20 21:01  Eero Tamminen
+
+	* src/gui-sdl/dlgAlert.c: center query dialog text horizontally
+
+2007-10-19 23:56  Eero Tamminen
+
+	* src/: sound.c, wavFormat.c, ymFormat.c, includes/ymFormat.h: -
+	  convertStreams in ymformat can be static - calls to wav recording
+	  function show up in profiler (ARM, frameskip 8)   although
+	  recording is not enabled so check the bRecordWav before calling
+	  that function (it would be nice if GCC could already do whole
+	  program   optimization instead of just object level ones)
+
+2007-10-19 21:54  Eero Tamminen
+
+	* src/: main.c, options.c: fix compiler warning, better quit
+	  message
+
+2007-10-16 22:41  Eero Tamminen
+
+	* doc/manual.html: document --confirm-quit
+
+2007-10-16 22:39  Eero Tamminen
+
+	* src/: configuration.c, dialog.c, main.c, options.c, shortcut.c,
+	  gui-sdl/dlgAlert.c, includes/configuration.h, includes/dialog.h,
+	  includes/main.h: Show user a confirmation dialog when Hatari is
+	  quit through: - the window close button, - the options dialog
+	  quit button, or - quit shortcut key.	It's enabled by default
+	  (except when quit is invoked from the internal debugger).
+
+	  There's also a --confirm-quit command line option and
+	  corresponding configuration option for disabling (and
+	  re-enabling) this query dialog.
+
+2007-10-16 00:00  Thomas Huth
+
+	* src/: includes/fdc.h, fdc.c, ioMemTabFalcon.c: The register
+	  0xff860f is now emulated in Falcon mode. Writing to floppy disk
+	  images works now also with TOS 4.0x.
+
+2007-10-11 23:37  Thomas Huth
+
+	* src/uae-cpu/fpp-unknown.h: Now using the conversion functions
+	  from Aranym in the FPU core to convert between integer and
+	  single/double floats. This fixes for example some rendering bugs
+	  in NeoN Grafix. Thanks to Ole Dittmann for the hint!
+
+2007-10-07 16:21  Thomas Huth
+
+	* Makefile-MinGW.cnf, Makefile-default.cnf, Makefile.cnf.in,
+	  configure.ac, src/uae-cpu/Makefile: Support for ranlib
+
+2007-10-07 16:09  Thomas Huth
+
+	* src/: rs232.c, scandir.c, includes/scandir.h: Hack for compiling
+	  Hatari with cegcc
+
+2007-10-07 16:07  Thomas Huth
+
+	* src/: gemdos.c, uae-cpu/sysdeps.h: Do not include errno.h by
+	  default in sysdeps.h
+
+2007-10-04 22:22  Thomas Huth
+
+	* src/uae-cpu/hatari-glue.c: Added missing call to
+	  build_cpufunctbl()
+
+2007-10-04 22:08  Thomas Huth
+
+	* src/dialog.c: Query user if it is OK to reset the emulator after
+	  changing certain options in the setup dialog.
+
+2007-09-29 23:54  Thomas Huth
+
+	* src/m68000.c: Fixed stupid typo: SPCFLAG_STOP must be cleared of
+	  course when an interrupt happened.
+
+2007-09-26 23:42  Thomas Huth
+
+	* src/: m68000.c, uae-cpu/newcpu.c, uae-cpu/newcpu.h: Renamed
+	  reg_caar and reg_cacr back to caar and cacr (like in the original
+	  UAE CPU core)
+
+2007-09-22 11:30  Thomas Huth
+
+	* src/uae-cpu/fpp.c: Use the IEEE big endian header file where
+	  possible
+
+2007-09-17 22:32  Thomas Huth
+
+	* src/: gemdos.c, m68000.c, uae-cpu/fpp.c, uae-cpu/hatari-glue.c,
+	  uae-cpu/hatari-glue.h, uae-cpu/memory.c, uae-cpu/newcpu.c,
+	  uae-cpu/options_cpu.h: To be closer to the original CPU core
+	  sources again, the variables address_space_24, cpu_level and
+	  cpu_compatible are now everywhere handled like in UAE again.
+
+2007-09-09 22:49  Thomas Huth
+
+	* Makefile-MinGW.cnf, Makefile-default.cnf, src/Makefile,
+	  src/configuration.c, src/debugui.c, src/dialog.c, src/gemdos.c,
+	  src/ide.c, src/ioMem.c, src/m68000.c, src/main.c, src/mfp.c,
+	  src/msa.c, src/options.c, src/shortcut.c, src/stMemory.c,
+	  src/tos.c, src/vdi.c, src/video.c, src/falcon/Makefile,
+	  src/includes/m68000.h, src/includes/main.h, src/uae-cpu/Makefile:
+	  Merged common changes from WINUAE_CPU_BRANCH back to HEAD.
+
+2007-09-07 13:31  Eero Tamminen
+
+	* doc/manual.html, src/configuration.c, src/options.c, src/vdi.c,
+	  src/includes/configuration.h, src/includes/vdi.h: - fix: VDI
+	  screen alignment is dependent on width in bytes, not pixels -
+	  fix: fixed-sized VDI resolutions need to be constrained in
+	  monochrome - add --vdi-planes command line argument - rename
+	  --vdix & --vdiy arguments to --vdi-x and --vdi-y -
+	  KeyLoadMem/keySaveMem are configurable like other shortcuts -
+	  have configuration values in .cfg file in same order as they
+	  are in Hatari structs (makes cross-checking them easier) - give
+	  all VDI settings to VDI_SetResolution() as arguments
+
+2007-08-26 21:54  Eero Tamminen
+
+	* src/: gemdos.c, includes/gemdos_defines.h: Fix GemDOS Open, it
+	  shouldn't truncate like it did with "wb" mode (write only).  Use
+	  "rb+" mode instead (read/write), that's the best we can using
+	  fopen(). (only open() would allow open write-only without
+	  truncating).
+
+	  Use chmod() in GemDOS Fattrib function so that it can set files
+	  read-only.
+
+	  Complain in Create and Fattrib if volume label attrib is used and
+	  add some FIXMEs for rest of attribs.
+
+	  (Change also these functions to bail out on errors instead of
+	  using else clauses, this way they don't need to be indented as
+	  much and it's easier to see the function exit point.)
+
+2007-08-26 19:56  Eero Tamminen
+
+	* doc/manual.html: describe --vdix and --vdiy options
+
+2007-08-26 19:16  Eero Tamminen
+
+	* src/: configuration.c, options.c, vdi.c,
+	  includes/configuration.h, includes/vdi.h, uae-cpu/hatari-glue.c:
+	  Add support for specifying VDI mode width and height from command
+	  line (makes memory earlier snapshots incompatible).
+
+	  Make a couple of variables in vdi.c static (required changing
+	  hatari-glue.c slightly).
+
+2007-08-22 01:28  Thomas Huth
+
+	* src/: configuration.c, m68000.c, tos.c, includes/m68000.h: Added
+	  wrapper function for checking cpu_level and cpu_compatible
+	  variables.
+
+2007-08-15 01:18  Thomas Huth
+
+	* src/: gemdos.c, m68000.c: Adapted gemdos.c and m68000.c for the
+	  new CPU core
+
+2007-08-15 00:38  Thomas Huth
+
+	* Makefile-MinGW.cnf, Makefile-default.cnf: Disabled -Wshadow since
+	  the WinUAE CPU core heavily (ab)uses shadowed variables
+
+2007-08-09 23:17  Thomas Huth
+
+	* src/: includes/main.h, dialog.c, main.c, mfp.c, shortcut.c,
+	  video.c, includes/m68000.h, debugui.c: Added wrappers for
+	  m68k_getpc, m68k_setpc, MakeSR, MakeFromSR, set_special and
+	  unset_special
+
+2007-08-09 23:05  Thomas Huth
+
+	* src/: ide.c, ioMem.c, msa.c, options.c, stMemory.c, vdi.c: CPU
+	  headers are not hard-coded to the uae-cpu folder anymore.
+
+2007-08-07 02:39  Thomas Huth
+
+	* src/: Makefile, falcon/Makefile, uae-cpu/Makefile: Now it is
+	  easier to choose the CPU core in the Makefiles
+
+2007-07-29 23:17  Eero Tamminen
+
+	* src/cfgopts.c: refactor and cleanup configuration update a bit
+
+2007-06-29 22:01  Thomas Huth
+
+	* src/gui-sdl/dlgScreen.c: The 'Frame Skip 8' option could not be
+	  selected - fixed now.
+
+2007-06-29 21:54  Thomas Huth
+
+	* src/cfgopts.c: Do not abort with an error if the end of the file
+	  has been reached.
+
+2007-05-18 19:53  Thomas Huth
+
+	* src/screen.c: Do not scale mouse in VDI screen mode
+
+2007-05-14 22:25  Eero Tamminen
+
+	* doc/manual.html: fix typos
+
+2007-05-14 22:07  Eero Tamminen
+
+	* doc/alsa-midi.txt: add link to wikipedia/midimaze
+
+2007-05-14 13:25  clafou
+
+	* Hatari.xcodeproj/project.pbxproj: XCode project: Updated nvram
+	  file references
+
+2007-05-13 11:23  Thomas Huth
+
+	* configure.ac: Handling of datadir variable has changed in
+	  autoconf 2.60.
+
+2007-05-12 14:12  Thomas Huth
+
+	* src/unzip.c: Fixed some 'variable might be used uninitialized'
+	  warnings
+
+2007-05-12 14:04  Thomas Huth
+
+	* Makefile.cnf.in: Added datarootdir to make autoconf 2.60 happy
+
+2007-05-12 : *** Version 0.95 ***
+
+2007-05-12 13:29  Thomas Huth
+
+	* doc/release-notes.txt: Added hmsa tool
+
+2007-05-12 13:22  Thomas Huth
+
+	* doc/release-notes.txt: Added release notes for version 0.95
+
+2007-05-12 13:16  Thomas Huth
+
+	* doc/: hatari.1, manual.html: Added keyboard shortcuts for loading
+	  and saving memory snapshots into the documentation files
+
+2007-05-12 13:08  Thomas Huth
+
+	* src/memorySnapShot.c: Bumped version number to 0.95
+
+2007-05-12 12:46  Thomas Huth
+
+	* Makefile-default.cnf: CC seems always to be predefined by make -
+	  so don't use the '?=' operator to assign this variable in
+	  Makefile.cnf
+
+2007-05-12 12:17  Thomas Huth
+
+	* Info-Hatari.plist, configure.ac, readme.txt,
+	  doc/doxygen/Doxyfile, src/includes/main.h: Bumped version number
+	  to 0.95
+
+2007-05-12 12:06  Thomas Huth
+
+	* doc/: compatibility.html, manual.html: Updated documentation
+
+2007-05-12 11:24  Thomas Huth
+
+	* src/cfgopts.c: tmpfile() does not work on some exotic systems.
+	  Added a workaround for this situation.
+
+2007-05-06 16:11  Thomas Huth
+
+	* hatari.spec: Added spec file for building RPMs
+
+2007-04-16 21:42  Thomas Huth
+
+	* src/ioMemTabTT.c: Re-ordered VME / SCC entries
+
+2007-04-04 17:23  Thomas Huth
+
+	* src/falcon/: hostscreen.c, videl.c: Disable videl debug output by
+	  default.
+
+2007-04-03 19:31  Thomas Huth
+
+	* doc/: manual.html, images/screen.png: Updated the screen setup
+	  dialog
+
+2007-04-03 00:35  Thomas Huth
+
+	* src/ioMemTabFalcon.c: Falcon IO memory table is now much closer
+	  to the original Falcon than before.
+
+2007-04-02 22:26  Thomas Huth
+
+	* doc/: manual.html, images/system.png: Updated the system dialog
+	  documentation.
+
+2007-04-02 21:46  Thomas Huth
+
+	* src/falcon/: hostscreen.c, videl.c: Workarounds for old C
+	  compilers
+
+2007-04-02 20:42  Thomas Huth
+
+	* src/includes/main.h: Use build date as version number for CVS
+	  builds.
+
+2007-03-10 18:49  Thomas Huth
+
+	* src/options.c: Added (very) short description what Hatari is all
+	  about.
+
+2007-03-10 18:46  Thomas Huth
+
+	* doc/authors.txt, src/gui-sdl/dlgAbout.c: Updated authors
+	  information.
+
+2007-03-05 23:19  Thomas Huth
+
+	* src/keymap.c: Improved error handling
+
+2007-02-27 21:53  Eero Tamminen
+
+	* src/: configuration.c, file.c: - add absolute file naming to
+	  other paths requiring it   (and remove special handling from
+	  rs232 as it doesn't use File_Open() - add stdin special handling
+	  to File_Open() just in case somebody in   the future wants to
+	  give some configuration from stdin ;-)
+
+2007-02-25 23:14  Eero Tamminen
+
+	* src/: file.c, options.c, printer.c: - fix stupid bugs from file.c
+	  - move trivial printer.c functions so that ancient compilers know
+	  to inline them too + fix comment typo
+
+2007-02-25 22:34  Eero Tamminen
+
+	* src/file.c: typo
+
+2007-02-25 22:33  Eero Tamminen
+
+	* doc/: alsa-midi.txt, manual.html: alsa-midi.txt: midi networking
+	  example manual.html:	 update options
+
+2007-02-25 22:20  Eero Tamminen
+
+	* src/: configuration.c, file.c, log.c, midi.c, options.c,
+	  printer.c, includes/file.h, includes/printer.h: allow setting the
+	  output file for log, midi and printer and special-case
+	  stdout/stderr: - move file open / close with stdout/stderr
+	  checking from log.c to file.c - wrapper function which
+	  shortcircuits absolute path function when   filename is
+	  stdout/stderr - use the new File_Open() and File_Close()
+	  functions in log.c, midi.c   and printer.c Cleanup printer.c a
+	  bit: - change functions to static - replace "unsigned char" with
+	  Uint8 - remove redundant code
+
+2007-02-22 22:25  Thomas Huth
+
+	* src/ioMemTabFalcon.c: There is no TT palette in Falcon mode
+
+2007-02-19 00:55  Thomas Huth
+
+	* doc/compatibility.html: Added Humans, TT-Wars and Oxyd-TT.
+
+2007-02-17 23:19  Eero Tamminen
+
+	* doc/compatibility.html: - replace "no" with "-" as that makes
+	  tables more readable - check which programs really require dummy
+	  and which none emu
+
+2007-02-17 23:14  Eero Tamminen
+
+	* src/: dmaSnd.c, includes/dmaSnd.h: make casts to double
+	  unnecessary + add one more define
+
+2007-02-17 19:43  Thomas Huth
+
+	* src/dmaSnd.c: Initial support for Falcon DMA sample sound
+	  frequencies.
+
+2007-02-16 20:31  Eero Tamminen
+
+	* doc/alsa-midi.txt: link to one more nice article
+
+2007-02-13 21:44  Matthias Arndt
+
+	* src/falcon/: nvram.c, nvram.h: added symbolic labels for NVRAM
+	  cells
+
+2007-02-13 20:32  Thomas Huth
+
+	* src/: Makefile, nvram.c, falcon/nvram.c, falcon/nvram.h,
+	  includes/nvram.h, falcon/Makefile: Moved nvram.c and nvram.h to
+	  falcon folder.
+
+2007-02-12 00:04  Thomas Huth
+
+	* tools/hmsa/.cvsignore: Added cvsignore file
+
+2007-02-12 00:00  Thomas Huth
+
+	* src/tos.c: Don't check the machine type when running with EmuTOS
+	  (since it can handle all types)
+
+2007-02-10 00:55  Eero Tamminen
+
+	* doc/compatibility.html: added some more demos and gfx programs
+
+2007-02-07 22:50  Thomas Huth
+
+	* doc/todo.txt: Updated TODO list
+
+2007-02-07 19:25  Thomas Huth
+
+	* tools/hmsa/hmsa.c: Added missing #include 
+
+2007-02-07 01:54  Thomas Huth
+
+	* src/nvram.c: Cleaned up NVRAM emulation a little bit.
+
+2007-02-04 22:38  Eero Tamminen
+
+	* doc/: compatibility.html, todo.txt: LS2 Roland-MT32 midi driver
+	  works just fine with ALSA
+
+2007-02-04 21:41  Eero Tamminen
+
+	* doc/: alsa-midi.txt, compatibility.html: Add instructions how to
+	  setup MIDI output on Linux with ALSA
+
+2007-02-04 15:10  Eero Tamminen
+
+	* doc/manual.html: add "usage" to command line options
+
+2007-02-02 00:23  Thomas Huth
+
+	* tools/hmsa/: Makefile, floppy.c, floppy.h, hmsa.c, hmsa.h,
+	  readme-hmsa.txt: New tool: MSA disk image converter.
+
+2007-02-01 23:03  Eero Tamminen
+
+	* doc/compatibility.html: added STE highresmode demo
+
+2007-02-01 22:37  Eero Tamminen
+
+	* doc/compatibility.html: added all falcon apps, games and demos
+	  from the ASCII list
+
+2007-01-30 22:45  Eero Tamminen
+
+	* doc/: compatibility.html, manual.html: - split the software
+	  compatibility list to a separate HTML page from   the Hatari
+	  manual, the list was getting pretty long - some updates to
+	  emulated HW support cli options
+
+2007-01-30 21:33  Eero Tamminen
+
+	* src/: Makefile, configuration.c, dialog.c, ioMem.c,
+	  ioMemTabFalcon.c, main.c, options.c, psg.c, falcon/Makefile,
+	  includes/configuration.h, includes/ioMemTables.h: - user can now
+	  specify one of none/dummy/emu DSP emulation types - changed
+	  ENABLE_DSP to ENABLE_DSP_EMU define - fix Makefile
+	  CPPFLAGS/CFLAGS usage
+
+2007-01-29 21:50  Eero Tamminen
+
+	* src/falcon/videl.c: add missing SDL_endian.h include
+
+2007-01-29 00:05  Thomas Huth
+
+	* src/video.c: Variable bUseSTShifter must be stored in memory
+	  snapshots, too.
+
+2007-01-28 23:59  Thomas Huth
+
+	* src/tos.c: Added TOS version check to prevent the user from
+	  running TOS 1.0x in TT or Falcon mode (which is an invalid
+	  combination)
+
+2007-01-28 23:41  Thomas Huth
+
+	* src/: configuration.c, m68000.c, memorySnapShot.c,
+	  includes/configuration.h, includes/main.h: Hatari now saves
+	  system configuration to memory snapshots, too.
+
+2007-01-23 21:34  Eero Tamminen
+
+	* src/: video.c, falcon/videl.c, includes/video.h: Fix Falcon/Videl
+	  code ST/E palette handling.  ST/E palette is used if ST shifter
+	  register is written after Falcon one (which should be set to
+	  4-bit color mode).
+
+2007-01-19 00:37  Thomas Huth
+
+	* src/video.c: Must also set TT resolution when writing to ST
+	  shifter mode register.
+
+2007-01-19 00:21  Thomas Huth
+
+	* src/: dialog.c, gui-sdl/dlgSystem.c: Changing the machine type
+	  now works as expected (thanks to Sebastien Molines for the hint)
+
+2007-01-18 10:27  Eero Tamminen
+
+	* src/: ioMemTabTT.c, video.c, includes/video.h: commit yesterdays
+	  work: - ST palette accesses on TT are diverted to another
+	  callback - overwrite part of TT palette with ST-palette as
+	  required The TT palette support should now be complete.
+
+2007-01-18 10:24  Eero Tamminen
+
+	* src/: Makefile, dialog.c, dmaSnd.c, ioMem.c, ioMemTabFalcon.c,
+	  main.c, options.c, psg.c, reset.c, screen.c, video.c,
+	  falcon/Makefile, includes/ioMemTables.h: commit yesterdays work:
+	  - remove ENABLE_FALCON (Falcon support works well enough) - add
+	  ENABLE_DSP instead (by default disabled)
+
+2007-01-16 22:14  Eero Tamminen
+
+	* src/: ioMemTabTT.c, video.c, includes/video.h: Added support for
+	  the TT-palette handling on top of Thomas' Videl usage for TT
+	  resolutions. TT-support for ST-palette setting is still to do.
+
+2007-01-16 20:00  clafou
+
+	* Hatari.xcodeproj/project.pbxproj, src/gui-osx/PrefsController.h,
+	  src/gui-osx/PrefsController.m,
+	  src/gui-osx/SDLMain.nib/classes.nib,
+	  src/gui-osx/SDLMain.nib/info.nib,
+	  src/gui-osx/SDLMain.nib/objects.nib: Updated Cocoa UI to match
+	  changes to the SDL UI
+
+2007-01-16 19:42  Thomas Huth
+
+	* doc/doxygen/Doxyfile, src/audio.c, src/bios.c, src/blitter.c,
+	  src/cart.c, src/cfgopts.c, src/configuration.c,
+	  src/createBlankImage.c, src/cycles.c, src/debugui.c,
+	  src/dialog.c, src/dim.c, src/dmaSnd.c, src/fdc.c, src/file.c,
+	  src/floppy.c, src/gemdos.c, src/hdc.c, src/ide.c, src/ikbd.c,
+	  src/int.c, src/ioMem.c, src/ioMemTabFalcon.c, src/joy.c,
+	  src/keymap.c, src/log.c, src/m68000.c, src/main.c,
+	  src/memorySnapShot.c, src/mfp.c, src/midi.c, src/misc.c,
+	  src/msa.c, src/nvram.c, src/options.c, src/printer.c, src/psg.c,
+	  src/reset.c, src/rs232.c, src/rtc.c, src/scandir.c, src/screen.c,
+	  src/screenSnapShot.c, src/shortcut.c, src/sound.c, src/spec512.c,
+	  src/st.c, src/stMemory.c, src/tos.c, src/unzip.c, src/vdi.c,
+	  src/video.c, src/wavFormat.c, src/xbios.c, src/ymFormat.c,
+	  src/zip.c: The source code now features comments that can be
+	  parsed with Doxygen to generate a nice source code documentation.
+	  (Thanks to Tuduri Benoit for the patch)
+
+2007-01-15 18:42  Thomas Huth
+
+	* src/: memorySnapShot.c, video.c, includes/main.h: TT resolution
+	  must be saved in memory snapshot files, too. (Also increased
+	  version number now that snapshot file layout has been changed)
+
+2007-01-15 14:50  Thomas Huth
+
+	* src/falcon/videl.c: Implemented horizontal fine scrolling for
+	  Videl emulation in 8bpp mode.
+
+2007-01-13 12:57  Thomas Huth
+
+	* src/: gui-sdl/dlgAbout.c, gui-sdl/dlgAlert.c,
+	  gui-sdl/dlgDevice.c, gui-sdl/dlgDisc.c, gui-sdl/dlgFileSelect.c,
+	  gui-sdl/dlgJoystick.c, gui-sdl/dlgKeyboard.c, gui-sdl/dlgMain.c,
+	  gui-sdl/dlgMemory.c, gui-sdl/dlgRom.c, gui-sdl/dlgScreen.c,
+	  gui-sdl/dlgSound.c, gui-sdl/dlgSystem.c, gui-sdl/sdlgui.c,
+	  includes/sdlgui.h: Default button can now be selected by pressing
+	  RETURN
+
+2007-01-13 11:00  Thomas Huth
+
+	* src/: reset.c, screen.c, video.c: Take also care of VDI extended
+	  resolution mode when emulator is running in TT or Falcon mode.
+
+2007-01-12 00:01  Thomas Huth
+
+	* src/spec512.c: Lowered threshold for detecting a spec512 screen
+
+2007-01-09 18:26  ggnkua
+
+	* src/Makefile: My first test commit! Modified Makefile and
+	  src/makefile slightly to allow compilation under Cygwin
+
+2007-01-09 01:07  Thomas Huth
+
+	* src/: screen.c, video.c, falcon/videl.c, falcon/videl.h,
+	  includes/video.h: Low-res zooming now works in TT mode, too.
+
+2007-01-08 21:25  Thomas Huth
+
+	* Makefile-default.cnf: libreadline disabled by default.
+
+2007-01-07 22:42  Eero Tamminen
+
+	* src/: options.c, gui-sdl/dlgScreen.c: - sync frameskips in
+	  options.c and dlgScreen.c code, the max. framesync   is now 8
+	  everywhere - GUI supports now frameskips of 0,1,2,4,8 and won't
+	  crash   if the frameskips variable has some other value - trivial
+	  cleanup for --monitor option
+
+2007-01-07 12:06  Thomas Huth
+
+	* doc/fr/hatari.1: Added french man-page (thanks to Benoit Tuduri)
+
+2007-01-06 12:15  Thomas Huth
+
+	* src/dialog.c: When changing the monitor type, only reset if
+	  emulator is in Falcon mode or if the user changes between color
+	  and mono monitor.
+
+2007-01-06 11:47  Thomas Huth
+
+	* src/: configuration.c, options.c, screen.c, video.c,
+	  gui-sdl/dlgScreen.c, includes/configuration.h: The frames that
+	  should be skipped after each displayed frame can now be set up in
+	  the GUI, too. Also removed the 'interleave' option in the GUI, it
+	  has now been replaced by the monitor settings (TV or RGB)
+
+2007-01-02 23:20  Thomas Huth
+
+	* src/: gui-win/opencon.c, gui-win/opencon.h, Makefile, main.c,
+	  gui-win/Makefile: The debugger now also works when Hatari is
+	  built on MinGW
+
+2007-01-02 22:11  Thomas Huth
+
+	* Makefile-MinGW.cnf, config-MinGW.h, src/Makefile: Improved MinGW
+	  build system
+
+2007-01-02 22:05  Thomas Huth
+
+	* src/gui-win/: Makefile, hatari-winicon.ico, hatari-winicon.rc:
+	  Icon for Windows build. (Thanks to ggn for the icon and .rc file)
+
+2007-01-02 21:27  Thomas Huth
+
+	* src/main.c: setenv is not available on MinGW
+
+2006-12-29 16:22  Thomas Huth
+
+	* src/debugui.c: Debugger now uses config.h to check if readline is
+	  available
+
+2006-12-29 15:20  Thomas Huth
+
+	* .cvsignore, Makefile, config-default.h, configure.ac,
+	  src/Makefile, src/rs232.c: Introduced config.h file
+
+2006-12-28 22:28  Thomas Huth
+
+	* Makefile: Also delete Makefile.cnf when doing a distclean
+
+2006-12-28 22:25  Thomas Huth
+
+	* acsite.m4, configure.ac, src/debugui.c: The built-in debugger now
+	  supports readline() for a higher convenience.
+
+2006-12-28 22:22  Thomas Huth
+
+	* .cvsignore: Ignore variable Makefile.cnf
+
+2006-12-28 21:48  Thomas Huth
+
+	* Makefile, Makefile-default.cnf, Makefile.cnf: Introduced
+	  Makefile-default.cnf
+
+2006-12-28 20:07  Thomas Huth
+
+	* src/gemdos.c: Changed some functions to use FILENAME_MAX instead
+	  of MAX_GEMDOS_PATH.
+
+2006-12-28 19:33  Thomas Huth
+
+	* src/debugui.c: Changed debugger commands: 'q' now quits the
+	  emulator, 'c' can be used to continue the current program
+
+2006-12-27 22:28  Thomas Huth
+
+	* src/: configuration.c, shortcut.c, includes/configuration.h:
+	  Added keyboard shortcuts for saving and restoring memory
+	  snapshots
+
+2006-12-23 20:45  Thomas Huth
+
+	* src/: configuration.c, vdi.c: Set up the VDI emulation variables
+	  and DESKTOP.INF file only when VDI resolution emulation is really
+	  enabled.
+
+2006-12-21 00:27  Thomas Huth
+
+	* src/rs232.c: By default, there is no termios.h on Windows
+
+2006-12-20 15:14  Thomas Huth
+
+	* src/: main.c, screen.c, falcon/hostscreen.c, includes/screen.h:
+	  Improved mouse movement scaling so that the ST mouse cursor
+	  movements are now always in sync with the host mouse (also when
+	  the zoomed Videl emulation is being used).
+
+2006-12-19 22:54  Thomas Huth
+
+	* src/: nvram.c, zip.c: Fixed compiler warnings from GCC 4.1
+
+2006-12-19 12:00  Thomas Huth
+
+	* src/gui-sdl/dlgFileSelect.c: Fixed typo
+
+2006-12-19 11:56  Thomas Huth
+
+	* src/falcon/hostscreen.c: Improved Videl screen zooming a little
+	  bit
+
+2006-12-19 11:55  Thomas Huth
+
+	* src/gui-sdl/: dlgDevice.c, dlgDisc.c, dlgFileSelect.c,
+	  dlgJoystick.c, dlgKeyboard.c, dlgMain.c, dlgMemory.c,
+	  dlgNewDisc.c, dlgRom.c, dlgScreen.c, dlgSound.c, sdlgui.c: The
+	  SDL GUI now tests if the screen size is big enough to display the
+	  dialogs
+
+2006-12-18 22:27  Eero Tamminen
+
+	* src/: dialog.c, main.c, screen.c, vdi.c, includes/screen.h: -
+	  cleaned up screen.c functions by changing then to return (med)
+	  rez	mode instead of messing with global STRes variable -
+	  removed separate mixed low/med rez mode, the rest of code handles
+	  mixed low/med fine without it - added Sreen_ModeChange() i.e.
+	  explicit screen size change function - removed PrevSTRes global
+	  (it was redundant with above)
+
+2006-12-18 21:19  Thomas Huth
+
+	* src/spec512.c: Changed the way how spec512 pictures are detected
+	  - now also screens with less than 32 changes per line can be
+	  detected as color cycling screens.
+
+2006-12-18 11:57  Thomas Huth
+
+	* src/uae-cpu/newcpu.c: Copied movec_illg function from WinUAE
+
+2006-12-18 11:22  Thomas Huth
+
+	* src/gemdos.c: Added error message when permissions for reading a
+	  file are missing
+
+2006-12-17 11:21  Eero Tamminen
+
+	* src/: Makefile, configuration.c, dialog.c, ioMem.c,
+	  ioMemTabFalcon.c, main.c, options.c, psg.c, falcon/Makefile,
+	  includes/configuration.h, includes/ioMemTables.h: - Build DSP
+	  emulation if ENABLE_FALCON is set - add configuration and command
+	  line option for enabling the DSP   (overwrites some
+	  IoMemTable_Falcon[] entries with suitable values)
+
+2006-12-11 21:17  Eero Tamminen
+
+	* doc/manual.html: - add new command line options - update other
+	  options - --slowfdc isn't anymore needed with demos nor games -
+	  Thomas' latest updates fixed scrolling in a couple of:   -
+	  overscan ST demos   - STE game demos
+
+2006-12-11 19:06  Eero Tamminen
+
+	* src/: configuration.c, dialog.c, main.c, options.c, screen.c,
+	  video.c, falcon/hostscreen.c, falcon/videl.c,
+	  gui-sdl/dlgScreen.c, includes/configuration.h: - Removes usage of
+	  the now redundant Configuration.Screen.bUseHighRes - Separates
+	  the confusing ChosenDisplayMode configuration to   more explicit
+	  bForce8Bpp and bZoomLowRes variables everywhere   -> This makes
+	  the related ifs in screen.c, videl.c, main.c etc. clearer   - Now
+	  furher changing the zoom boolean to zoom factor integer would be
+	  much easier especially as Videl supports more than just
+	  doubling - Changes bFrameSkip boolean to FrameSkips integer	->
+	  Videl code is slow, with e.g. "--frameskips 4" the Falcon
+	  emulation	 with zoomed screen takes much less CPU   -> Could
+	  be better supported in Hatari screen dialog, currently      I've
+	  mapped the checkbox to frameskip 1 and 2 - Added command line
+	  options for --borders, --force8bpp, --zoom, --frameskips - Move
+	  cpu_level and cpu_compatible variable settings from
+	  Opt_ParseParameters(), Dialog_CopyDialogParamsToConfiguration()
+	  and	Configuration_Load() to Configuration_WorkOnDetail() as all
+	  those   first three functions were anyway calling the last one.
+	  (TOS loading still does CPU settings by itself)  - Move STRes
+	  setting from Opt_ParseParameters() to
+	  Configuration_WorkOnDetail() - Rename
+	  Configuration_WorkOnDetails() to more clear/appropriate
+	  Configuration_Apply() and call it explicitly from main.c and
+	  dialog.c   instead of also from Configuration_Load() as loading
+	  and applying config	are different actions.	I also removed call
+	  to it from option parsing,   it's IMHO cleaner to have it in
+	  main.c - Fix doing zoom on, low -> med-res, zoom off, med ->
+	  low-res   (previously screen size didn't get smaller in last
+	  step) - Set --slow-fdc and mono option deprecated (monitor should
+	  be used instead   of mono) and remove "experimental" from blitter
+	  option descriptions.	- use setenv() instead of putenv() in
+	  main() as I was mailed that nowadays	 former is more standard
+	  (despite Linux manual page...) - Indentation fixes
+
+2006-12-10 22:00  Thomas Huth
+
+	* src/: reset.c, video.c, includes/video.h: Cleaned up the
+	  HBL/Timer B interrupt code a little bit.
+
+2006-12-07 21:23  Thomas Huth
+
+	* src/video.c: Disabled debug output
+
+2006-12-05 22:58  Thomas Huth
+
+	* src/psg.c: Silenced debug output
+
+2006-12-04 00:33  Thomas Huth
+
+	* src/: reset.c, video.c, includes/video.h, uae-cpu/newcpu.c:
+	  Changed horizontal screen timings to be much closer to the
+	  original shifter
+
+2006-12-03 16:35  Thomas Huth
+
+	* src/gemdos.c: Check for valid return values when calling
+	  localtime()
+
+2006-12-01 20:42  Eero Tamminen
+
+	* src/falcon/videl.c: - fix compiler warning about local variable
+	  shadowing global one - replace some shifts with SDL_SwapBE16()
+	  calls and remove related   BYTEORDER ifdefs as SDL_SwapBE16()
+	  already handles that
+
+2006-12-01 20:39  Eero Tamminen
+
+	* src/falcon/Makefile: Add CPPFLAGS like into other Makefiles
+
+2006-11-26 18:50  Thomas Huth
+
+	* src/: screen.c, video.c: Moved printer check from screen.c to
+	  video.c.
+
+2006-11-25 12:26  Thomas Huth
+
+	* src/: ioMemTabTT.c, video.c, falcon/videl.c, falcon/videl.h,
+	  includes/video.h: The TT shifter modes are now handled, too.
+
+2006-11-21 23:40  Thomas Huth
+
+	* src/falcon/videl.c: Adjust line length when register FF8265 is
+	  set.
+
+2006-11-20 22:43  Thomas Huth
+
+	* src/screenSnapShot.c: Added missing closedir() - leaving the
+	  directory handles open caused problems after a while when
+	  recording animations.
+
+2006-11-20 01:21  Thomas Huth
+
+	* src/ioMemTabFalcon.c: Registers 0xff820e and 0xff8264 are present
+	  on the Falcon so do not do a 'void read' there.
+
+2006-11-20 01:20  Thomas Huth
+
+	* src/falcon/videl.c: Size of register ff8260 is only byte, not
+	  word.
+
+2006-11-17 19:08  Matthias Arndt
+
+	* src/: dmaSnd.c, psg.c: * added some minor Falcon specifics to PSG
+	  and DMA Audio code
+
+2006-11-15 20:34  Eero Tamminen
+
+	* src/gemdos.c: make glob/globfree static so that MinGW GCC doesn't
+	  complain on Windows
+
+2006-11-14 22:08  Eero Tamminen
+
+	* src/: hatari-icon.bmp, screen.c: - convert icon to 8-bit so that
+	  color keying can make it transparent - free the icon after use so
+	  that it doesn't leak
+
+2006-11-13 23:25  Thomas Huth
+
+	* src/hatari-icon.bmp, Makefile, src/screen.c: Added icon.
+
+2006-11-13 21:41  Eero Tamminen
+
+	* Makefile.cnf, src/Makefile, src/gui-sdl/Makefile,
+	  src/uae-cpu/Makefile: handle CPPFLAGS (consistently) in Makefiles
+	  and make it overridable
+
+2006-11-13 00:34  Thomas Huth
+
+	* src/: Makefile, gemdos.c: Patches for MinGW (GEMDOS HD emu now
+	  does not crash the emulator anymore)
+
+2006-11-12 19:48  Eero Tamminen
+
+	* src/: reset.c, includes/reset.h: Reset_ST is called only from
+	  reset.c, so make it static
+
+2006-11-12 16:09  Eero Tamminen
+
+	* doc/manual.html: Add "20 years" demo to the list
+
+2006-11-01 21:29  Eero Tamminen
+
+	* src/nvram.c: make global nvram array static
+
+2006-11-01 12:05  Thomas Huth
+
+	* src/gui-sdl/dlgScreen.c: Screen dialog now shows all Falcon
+	  monitor types.
+
+2006-10-29 12:00  Thomas Huth
+
+	* src/ioMemTabTT.c: Enabled NVRAM/RTC emulation for TT mode, too.
+
+2006-10-29 10:25  Thomas Huth
+
+	* src/: Makefile, ioMemTabFalcon.c, main.c, nvram.c, tos.c,
+	  includes/nvram.h: Added NVRAM/RTC emulation for the Falcon mode.
+
+2006-10-28 21:13  Eero Tamminen
+
+	* src/main.c: set SDL_VIDEO_X11_WMCLASS to help (X11) window
+	  managers in window grouping
+
+2006-10-28 21:07  Eero Tamminen
+
+	* Makefile: note about DESTDIR
+
+2006-10-25 21:00  Eero Tamminen
+
+	* src/: configuration.c, options.c, stMemory.c,
+	  includes/configuration.h: Add monitor type command line option
+	  and support for all Falcon monitor types.
+
+2006-10-23 19:56  Eero Tamminen
+
+	* src/video.c: include missing videl.h
+
+2006-10-22 22:51  Eero Tamminen
+
+	* src/options.c: machine: st/ste -> 8Mhz
+
+2006-10-20 22:12  Eero Tamminen
+
+	* doc/manual.html: Add STE STrEet Fighter 2 from Patrice Mandin
+
+2006-10-20 13:49  Eero Tamminen
+
+	* src/options.c: Fix st/ste command line setting in case user had
+	  saved tt/falcon setting
+
+2006-10-19 22:09  Eero Tamminen
+
+	* src/falcon/: hostscreen.c, hostscreen.h, videl.c, videl.h: makes
+	  some thing static that are not called from outside the object
+	  file and remove their prototypes from header
+
+2006-10-19 22:08  Eero Tamminen
+
+	* src/reset.c: #include "falcon/videl.h"
+
+2006-10-18 02:08  Thomas Huth
+
+	* src/tos.c: Added support for TOS 4.00 and 4.01.
+
+2006-10-15 23:35  Thomas Huth
+
+	* src/falcon/hostscreen.c: Fixed problem with the SDL-GUI using the
+	  wrong screen surface when the Videl emulation was active (Thanks
+	  to Emmanuel Anne for the hint).
+
+2006-10-15 23:24  Thomas Huth
+
+	* src/tos.c: Added support for TOS 4.02 and 4.92.
+
+2006-10-15 23:21  Thomas Huth
+
+	* src/: stMemory.c, includes/tos.h: Do not erase RAM TOS images
+	  during memory initialization.
+
+2006-10-15 23:20  Thomas Huth
+
+	* src/uae-cpu/newcpu.c: Jump to debug interface when encountering
+	  an uninitialized exception handler.
+
+2006-10-12 22:56  Thomas Huth
+
+	* src/ioMemTabFalcon.c: Some programs poll the DSP registers for a
+	  change. Simulate some action there to get these programs running.
+
+2006-10-10 22:14  Thomas Huth
+
+	* src/gemdos.c: Improved error output in the GEMDOS HD emulation a
+	  little bit.
+
+2006-10-10 22:13  Thomas Huth
+
+	* src/: screen.c, falcon/hostscreen.c, falcon/hostscreen.h:
+	  Toggling between fullscreen and window mode now also works with
+	  the Videl emulation.
+
+2006-10-09 19:41  Thomas Huth
+
+	* doc/todo.txt: Updated the TODO file.
+
+2006-10-08 14:11  Thomas Huth
+
+	* src/falcon/hostscreen.h: hostscreen.h now also uses araglue.h
+
+2006-10-08 14:10  Thomas Huth
+
+	* src/: ioMemTabFalcon.c, main.c, psg.c, falcon/.cvsignore,
+	  falcon/araglue.h, falcon/dsp.c, falcon/dsp.h, falcon/dsp_cpu.c,
+	  falcon/dsp_cpu.h, falcon/dsp_disasm.c, falcon/dsp_disasm.h: Made
+	  the DSP code compilable for Hatari
+
+2006-10-08 13:53  Thomas Huth
+
+	* src/falcon/: dsp.c, dsp.h, dsp_cpu.c, dsp_cpu.h, dsp_disasm.c,
+	  dsp_disasm.h: Copied DSP emulation code from Aranym to Hatari.
+	  (Thanks to the Aranym developers, especially Patrice Mandin, for
+	  this code)
+
+2006-10-07 15:32  Thomas Huth
+
+	* src/: dialog.c, falcon/hostscreen.c, falcon/videl.c,
+	  falcon/videl.h: Enabled zooming function of the Videl emulation
+	  code.
+
+2006-10-07 14:22  Thomas Huth
+
+	* src/screen.c: Disabled resolution switching in screen.c when
+	  Videl emulation is running.
+
+2006-10-07 13:41  Thomas Huth
+
+	* src/falcon/: hostscreen.c, hostscreen.h, videl.c, videl.h:
+	  Cleaned up the videl code a little bit (thanks to Eero for the
+	  patch).
+
+2006-10-07 13:01  Thomas Huth
+
+	* src/options.c: Slightly improved text output strings.
+
+2006-10-06 01:31  Thomas Huth
+
+	* src/falcon/hostscreen.c: Fixed Videl palette color problem and
+	  cleaned up a little bit (removed backgroundSurf)
+
+2006-10-04 22:34  Thomas Huth
+
+	* src/: Makefile, ioMemTabFalcon.c, main.c, reset.c, video.c,
+	  falcon/Makefile, falcon/hostscreen.c, falcon/hostscreen.h,
+	  falcon/videl.c, falcon/videl.h: Integrated the Videl emulation
+	  into Hatari.
+
+2006-10-04 20:39  Thomas Huth
+
+	* src/falcon/: hostscreen.c, videl.c: Copied Falcon Videl emulation
+	  code from Aranym 0.9.4. Many thanks to the Aranym authors for
+	  their code!
+
+2006-10-03 12:38  Thomas Huth
+
+	* src/: configuration.c, file.c: Some more changes for Amiga OS.
+	  Thanks to Ventzislav Tzvetkov for the patches!
+
+2006-10-03 12:07  Thomas Huth
+
+	* src/: memorySnapShot.c, includes/main.h: Increased version number
+	  to 0.91
+
+2006-10-03 11:59  Thomas Huth
+
+	* src/gui-sdl/dlgSystem.c: Added TT and Falcon checkbox to the
+	  system dialog
+
+2006-09-29 13:20  Thomas Huth
+
+	* src/stMemory.c: The Falcon memory (and monitor) configuration
+	  register is now initialized to make TOS 4.04 happy.
+
+2006-09-29 12:45  Thomas Huth
+
+	* src/tos.c: Disabled ROM CRC check for TOS 4.04
+
+2006-09-29 03:07  Thomas Huth
+
+	* src/: ioMemTabFalcon.c, tos.c: Some more patches to get TOS 4.04
+	  finally booting :-).
+
+2006-09-29 00:58  Thomas Huth
+
+	* src/ioMem.c: Added missing break statement
+
+2006-09-28 20:27  Eero Tamminen
+
+	* src/: main.c, misc.c, sound.c, includes/misc.h: Random is only
+	  used when generating the noise sound channel, so move all random
+	  stuff to sound.c
+
+2006-09-28 17:21  Thomas Huth
+
+	* src/st.c: Added flag for RISC OS to prevent it from interfering
+	  with the .ST disk image files (Thanks to James Lampard for the
+	  patch).
+
+2006-09-27 10:58  Thomas Huth
+
+	* src/: Makefile, configuration.c, ide.c, options.c, tos.c,
+	  includes/configuration.h, includes/ide.h, uae-cpu/memory.c:
+	  Infrastructure for intercepting read/write accesses to IDE IO
+	  memory region.
+
+2006-09-27 00:01  Thomas Huth
+
+	* src/file.c: Slightly improved Files_Exists(): The function now
+	  works with block/character devices again.
+
+2006-09-26 21:12  Eero Tamminen
+
+	* src/: int.c, m68000.c, mfp.c, video.c, includes/int.h,
+	  includes/m68000.h, uae-cpu/newcpu.c: - move the
+	  PendingInterruptFunction & PendingInterruptCount   from m68000.c
+	  to int.c, this allows making some functions static   (used only
+	  by memory snapshot though and it makes the memory   snapshots
+	  from earlier version uncompatible) - add new
+	  Int_AddRelativeInterruptNoOffset() and use it in mfp.c   so that
+	  nCyclesOver variable can be static - typedef the interrupt types
+	  enum and use that type in the public	 interrupt functions - use
+	  interrupt define in video.c call instead of "magic NULL" - remove
+	  redundant type casts and initial zero values for static variables
+	  - return is not a function...
+
+2006-09-26 21:04  Eero Tamminen
+
+	* src/convert/: high640x8.c, low320x16.c, low320x8.c, low640x16.c,
+	  low640x8.c, macros.h, med640x16.c, med640x8.c, spec640x16.c,
+	  vdi16.c, vdi2.c, vdi4.c: Optimize by calculating some values
+	  before loop: - Screen4BytesPerLine = PCScreenBytesPerLine/4 -
+	  Screen2BytesPerLine = PCScreenBytesPerLine/2 - update =
+	  ScrUpdateFlag & PALETTEMASK_UPDATEMASK
+
+2006-09-26 17:16  Thomas Huth
+
+	* doc/authors.txt: Added James Lampard to the list of contributors
+
+2006-09-26 17:13  Thomas Huth
+
+	* src/rs232.c: cfmakeraw was missing on RiscOS, too. Thanks to
+	  James Lampard for the hint.
+
+2006-09-26 15:52  Thomas Huth
+
+	* src/rs232.c: tcgetattr, tcsetattr, cfsetospeed and cfsetispeed
+	  need to be defined on AmigaOS
+
+2006-09-13 22:21  Eero Tamminen
+
+	* src/: mfp.c, includes/mfp.h: - optimize:   - MFP timer lookup
+	  table; integer fraction calculation is faster     than use of
+	  floats   - one more function can be static and MFP_StartTimer_*
+	  args fit into Uint16 - cleanup: return is not a function
+
+2006-09-12 23:43  Thomas Huth
+
+	* src/tos.c: Since we have to patch TOS 3.06 for Hatari, the
+	  useless ROM CRC code in TOS 3.06 is now ignored, too.
+
+2006-09-12 23:21  Thomas Huth
+
+	* src/: Makefile, ioMem.c, ioMemTabFalcon.c, options.c, tos.c,
+	  includes/configuration.h, includes/ioMemTables.h: Added some
+	  experimental code (not working yet)
+
+2006-09-12 19:55  Eero Tamminen
+
+	* src/file.c: fix to infinite loop when Hatari cmdline option
+	  taking a file is given a directory instead
+
+2006-09-12 19:22  Thomas Huth
+
+	* doc/manual.html: Some minor improvements to the manual
+
+2006-09-02 15:13  Eero Tamminen
+
+	* Makefile.cnf: Allow user to override following Makefile variables
+	  with environment variables: CC, HOSTCC, BINDIR, DATADIR, CONFDIR
+
+2006-08-31 21:24  Thomas Huth
+
+	* src/: Makefile, ioMemTabST.c, ioMemTabSTE.c, ioMemTabTT.c,
+	  ioMemTables.c: ioMemTables.c has been split up into smaller,
+	  better maintainable parts.
+
+2006-08-30 21:54  Thomas Huth
+
+	* src/: spec512.c, ymFormat.c: Sourcecode beautification
+
+2006-08-27 19:20  clafou
+
+	* Hatari.xcodeproj/project.pbxproj,
+	  src/gui-osx/SDLMain.nib/objects.nib: For v.0.90 OSX version:
+	  Xcode project file updated (added new files scandir.h and
+	  scandir.c), prefs window edited to make the 1st tab open first
+
+2006-08-22 : *** Version 0.90 ***
+
+2006-08-24 19:34  Thomas Huth
+
+	* doc/release-notes.txt: Forgot to mention some items
+
+2006-08-22 20:39  Thomas Huth
+
+	* configure.ac, readme.txt, src/memorySnapShot.c,
+	  src/includes/main.h: Increased version number to 0.90
+
+2006-08-22 20:37  Thomas Huth
+
+	* doc/: hatari.1, release-notes.txt, todo.txt: Updated the docs for
+	  the new public version.
+
+2006-08-16 22:14  Thomas Huth
+
+	* doc/: authors.txt, manual.html: Updated the documentation files.
+
+2006-08-14 20:32  Thomas Huth
+
+	* src/gui-sdl/dlgDevice.c: Printer file browse button now works
+	  again.
+
+2006-08-14 01:33  Thomas Huth
+
+	* src/: fdc.c, hdc.c, includes/hdc.h: Debugged and improved the
+	  ACSI emulation code. Creating (formating and partitioning) new
+	  hard disk images with AHDI v5.0 should be working fine now.
+
+2006-08-11 11:25  Eero Tamminen
+
+	* src/hdc.c: - add more info on the hd root sector partition table
+	  - in GetInfo, get only the data for partition table	(reading 64
+	  bytes did go unnecessarily to 2d sector in the image)
+
+2006-08-10 21:10  Thomas Huth
+
+	* src/: hdc.c, includes/hdc.h: Added 'MODE SENSE' and 'FORMAT
+	  DRIVE' commands to make HDX from AHDI 5.0 happy. Also had to set
+	  the FDC/HDC GPIP bit for non-existing controllers when HDX scans
+	  for available hard disks.
+
+2006-08-10 19:26  Thomas Huth
+
+	* src/: fdc.c, hdc.c, includes/hdc.h: Removed annoying check for
+	  existing partitions and added stub for 'REQUEST SENSE' ACSI
+	  command.
+
+2006-08-10 14:14  Eero Tamminen
+
+	* doc/memory-usage.txt: updated/fixed the analysis
+
+2006-08-09 10:16  Eero Tamminen
+
+	* doc/manual.html: minor updates for: - configurable shortcut keys
+	  - change in how joystick cursor key emu works - keymap handling
+
+2006-08-09 10:14  Eero Tamminen
+
+	* src/: configuration.c, keymap.c, shortcut.c, video.c,
+	  includes/configuration.h, includes/shortcut.h: Shortcut keys can
+	  now be configured from the Hatari configuration file.  There are
+	  separate sections for shortcut keybindings with and without a
+	  modifier key.  Same shortcut action can be bound both to a key
+	  with and without a modifier (e.g. F12 & Modifier+o are bound for
+	  the the options dialog by default).
+
+2006-08-09 10:11  Eero Tamminen
+
+	* doc/keymap-sample.txt: improved comments
+
+2006-08-09 10:10  Eero Tamminen
+
+	* src/: joy.c, options.c, includes/joy.h: Joystick shortcut
+	  (Altgr+j): - toggles cursor emu between port 0, port 1 and being
+	  disabled from those, - it doesn't disable cursor emu from any
+	  other port, and - it restores the previous joystick value
+	  (disabled/real) to the port when   the cursor emu is toggled off
+	  from the port I.e. it affects only cursor emulation and only in
+	  ports 0 & 1.	The -j  option doesn't disable the cursor emu
+	  from other ports anymore either (like it did with the patch I had
+	  commited earlier).
+
+2006-08-08 09:19  Thomas Huth
+
+	* src/: file.c, floppy.c, hdc.c: Source code beautification
+
+2006-08-05 22:56  Eero Tamminen
+
+	* doc/manual.html: add name of the keymap example file
+
+2006-08-05 10:33  Thomas Huth
+
+	* src/: hdc.c, includes/hdc.h: Improved HDC debugging output.
+
+2006-08-02 22:09  Eero Tamminen
+
+	* doc/manual.html, src/options.c: - added option -k/--keymap for
+	  setting the keyboard mapping file - documented this and the
+	  updated -j option in manual
+
+2006-08-02 13:51  Eero Tamminen
+
+	* src/: configuration.c, joy.c, options.c, gui-sdl/dlgJoystick.c,
+	  includes/configuration.h: add port parameter to the -j option +
+	  use JOYSTICK_COUNT where appropriate
+
+2006-08-02 12:54  Eero Tamminen
+
+	* src/file.c: add 'else' missing from previous change to
+	  File_makepath()
+
+2006-08-02 11:53  Eero Tamminen
+
+	* doc/manual.html: updated STE right border stuff
+
+2006-08-02 09:45  Thomas Huth
+
+	* src/main.c: Improved mouse handling in ST-Medium and zoomed
+	  ST-Low resolutions: The ST mouse cursor is now better in sync
+	  with the mouse cursor of the host system.
+
+2006-08-01 22:18  Thomas Huth
+
+	* src/gui-sdl/dlgFileSelect.c: The user can now choose wether
+	  hidden files should be displayed in the file selector or not.
+
+2006-08-01 11:23  Thomas Huth
+
+	* src/: audio.c, sound.c, includes/sound.h: Fixed problems with
+	  sound buffer synchronization in fast-forward mode
+
+2006-08-01 11:19  Thomas Huth
+
+	* src/zip.c: Header file sys/dir.h is only needed on QNX
+
+2006-07-31 00:49  Thomas Huth
+
+	* src/gui-sdl/: dlgFileSelect.c, font10x16.bmp, font10x16.h,
+	  font5x8.bmp, font5x8.h: In the SDL-GUI file selector, a button
+	  for the home folder has been added.
+
+2006-07-30 22:42  Thomas Huth
+
+	* Makefile, src/Makefile, src/gui-sdl/Makefile,
+	  src/uae-cpu/Makefile: Added 'distclean' target to Makefiles and
+	  improved creation of Makefile.dep
+
+2006-07-30 22:17  Thomas Huth
+
+	* src/uae-cpu/: Makefile, sysdeps.h: The host compiler should not
+	  use the SDL_CFLAGS from the target system. So the UAE variables
+	  types are now mapped to the types from stdint.h instead of
+	  SDL_types.h
+
+2006-07-27 22:00  Thomas Huth
+
+	* src/zip.c: Patch for compiling on QNX
+
+2006-07-27 21:57  Thomas Huth
+
+	* src/rs232.c: 230400 are not supported on all systems
+
+2006-07-23 17:44  Thomas Huth
+
+	* Makefile-MinGW.cnf: Added Makefile configuration for MinGW
+
+2006-07-23 17:32  Thomas Huth
+
+	* src/: configuration.c, file.c, gui-sdl/dlgFileSelect.c,
+	  includes/main.h: Better support for MingW: Hatari now basically
+	  supports backslashes as path separators, too.
+
+2006-07-22 18:25  Thomas Huth
+
+	* src/: Makefile, gui-sdl/Makefile, uae-cpu/Makefile: Updated
+	  Makefiles so that they work better with MinGW
+
+2006-07-22 17:49  Thomas Huth
+
+	* src/: gemdos.c, scandir.c: Made Hatari really compilable with
+	  MinGW
+
+2006-07-20 23:43  Thomas Huth
+
+	* src/: Makefile, file.c, gemdos.c, scandir.c,
+	  gui-sdl/dlgFileSelect.c, includes/file.h, includes/scandir.h:
+	  Moved scandir code to a separate file and also added scandir for
+	  Windows (Thanks to Mark Keates for the scandir code for Windows).
+
+2006-07-20 23:00  Thomas Huth
+
+	* src/keymap.c: Now using proper SDLKey type.
+
+2006-07-15 12:41  clafou
+
+	* Hatari.xcodeproj/project.pbxproj,
+	  src/gui-osx/CreateFloppyController.m,
+	  src/gui-osx/PrefsController.h, src/gui-osx/PrefsController.m,
+	  src/gui-osx/SDLMain.h, src/gui-osx/SDLMain.m,
+	  src/gui-osx/SDLMain.nib/classes.nib,
+	  src/gui-osx/SDLMain.nib/info.nib,
+	  src/gui-osx/SDLMain.nib/objects.nib: Fullscreen now a menu item,
+	  Create Floppy window bug fixed
+
+2006-07-12 23:12  clafou
+
+	* Info-Hatari.plist, Hatari.xcodeproj/project.pbxproj: Added
+	  Universal Binary compilation for MacOS X
+
+2006-07-11 20:52  Thomas Huth
+
+	* src/: cfgopts.c, file.c, gemdos.c, memorySnapShot.c, unzip.c,
+	  zip.c: strcasecmp is defined in strings.h, not in string.h!
+	  (Thanks to Anatol for the hint)
+
+2006-07-05 20:08  clafou
+
+	* Hatari.xcodeproj/project.pbxproj, src/gui-osx/hatari.x32: Removed
+	  obsolete file
+
+2006-07-03 23:00  clafou
+
+	* Hatari.xcodeproj/project.pbxproj: Added Cocoa UI for MacOSX
+
+2006-07-03 22:54  clafou
+
+	* src/gui-osx/: AlertHooks.h, AlertHooks.m,
+	  CreateFloppyController.h, CreateFloppyController.m, Hatari.icns,
+	  PrefsController.h, PrefsController.m, SDLMain.h, SDLMain.m,
+	  Shared.h, Shared.m, hatari.x32, English.lproj/InfoPlist.strings,
+	  SDLMain.nib/classes.nib, SDLMain.nib/info.nib,
+	  SDLMain.nib/objects.nib: Added Cocoa UI for MacOSX
+
+2006-07-03 22:36  clafou
+
+	* src/: dialog.c, gui-sdl/dlgAlert.c, gui-sdl/dlgMain.c,
+	  includes/dialog.h, includes/main.h: Added Cocoa UI for MacOSX
+
+2006-06-27 01:03  Thomas Huth
+
+	* src/: int.c, m68000.c, screen.c, includes/ikbd.h, includes/int.h,
+	  includes/ioMemTables.h, includes/m68000.h: Now using correct
+	  variable types for variables that store a pointer to a function
+	  (Thanks to Mark Keates for the patch)
+
+2006-06-22 22:03  Eero Tamminen
+
+	* doc/manual.html: fix typo
+
+2006-06-13 22:26  Thomas Huth
+
+	* src/main.c: Slightly improved the wait-on-vbl function. Should
+	  now result in a better tradeoff between speed accuracy and CPU
+	  time consumption on Mac OS X.
+
+2006-06-13 22:22  Thomas Huth
+
+	* src/sound.c: Added additional check to avoid the creation of too
+	  many new samples (e.g. when running in max. speed mode)
+
+2006-05-21 11:13  Eero Tamminen
+
+	* doc/manual.html: updated the command line options in regards to
+	  memory and TT support, updated the STE demo list, added new table
+	  for 68030 software compatibility and added note about the
+	  scrollwheel to the mouse section.
+
+2006-05-20 10:05  Thomas Huth
+
+	* src/: gemdos.c, includes/gemdos.h: Fixed GEMDOS-HD Dsetpath
+	  emulation: No more buffer overruns and crashes when a program
+	  does a lot Dsetpath("..") calls.
+
+2006-05-04 21:36  Thomas Huth
+
+	* src/gemdos.c: Renamed variable name 'Char' to 'c' since 'Char' is
+	  a pre-defined name on AmigaOS (Thanks to Ventzislav Tzvetkov for
+	  the hint).
+
+2006-04-19 23:46  Thomas Huth
+
+	* src/: includes/joy.h, joy.c, main.c: Joysticks are now closed at
+	  exit.
+
+2006-04-05 17:34  Thomas Huth
+
+	* src/: ioMemTables.c, memorySnapShot.c, video.c, includes/main.h,
+	  includes/video.h: Hatari can now emulate the STE shifter bug that
+	  is used in some games like Obsession to enhance the resolution to
+	  336x200.
+
+2006-03-23 23:03  Thomas Huth
+
+	* src/ioMemTables.c: Moved wrongly placed entry in IO-mem-table to
+	  correct location.
+
+2006-03-23 21:56  Eero Tamminen
+
+	* src/includes/main.h: Remove obsolete variable definition from
+	  main.h (produced error with gcc v4)
+
+2006-03-03 00:17  Thomas Huth
+
+	* src/video.c: Added basic support for shortening a screen line by
+	  2 bytes: Some few sync-scrolling screens are now working.
+
+2006-03-02 23:20  Thomas Huth
+
+	* src/: video.c, includes/video.h: Fixed byte size of left and
+	  right border: Programs that only open one of these two borders
+	  should be working fine now (e.g. the overscan screen in the
+	  'Amiga demo' from TEX)
+
+2006-03-02 10:17  Thomas Huth
+
+	* src/cart.c: Forgot to free allocated memory in case of an error.
+
+2006-03-02 10:06  Thomas Huth
+
+	* src/: cart.c, configuration.c, gui-sdl/dlgRom.c: Slightly
+	  improved cartridge loading (now checking correctly for illegal
+	  file names etc.).
+
+2006-03-02 09:42  Thomas Huth
+
+	* src/file.c: File_Read now returns the correct number of bytes
+	  that have been read.
+
+2006-03-01 21:54  Thomas Huth
+
+	* src/unzip.c: Fixed typo.
+
+2006-03-01 21:46  Thomas Huth
+
+	* src/: tos.c, unzip.c: Sourcecode beautification.
+
+2006-03-01 17:31  Thomas Huth
+
+	* src/includes/video.h: Removed unused legacy defines.
+
+2006-02-27 12:07  Thomas Huth
+
+	* src/: cart_asm.s, cart_mus.x32, hatari.x32: Renamed hatari.x32 to
+	  cart_mus.x32
+
+2006-02-23 22:00  Thomas Huth
+
+	* src/spec512.c: Improved Spectrum512 picture generation - many
+	  Spec512 pictures look now much better! (Thanks to Emmanuel Anne
+	  for this patch)
+
+2006-02-21 22:45  Thomas Huth
+
+	* src/uae-cpu/memory.c: Speed optimization: Use STRam array
+	  directly instead of using it indirectly via a pointer
+	  (*STmemory).
+
+2006-02-21 20:09  Eero Tamminen
+
+	* src/keymap.c: use Log_Printf() instead of fprintf(stderr...)
+
+2006-02-21 15:15  Thomas Huth
+
+	* src/: reset.c, stMemory.c, tos.c, includes/stMemory.h: Moved
+	  memory initialization to stMemory.c. The memory is now also
+	  cleared up to STRamEnd, not only up to 4MiB.
+
+2006-02-21 14:47  Thomas Huth
+
+	* Makefile.cnf: Disabled -Wcast-align again
+
+2006-02-21 14:41  Thomas Huth
+
+	* src/gemdos.c: Fixed GCC compiler warnings.
+
+2006-02-19 22:48  Eero Tamminen
+
+	* src/options.c: improved comments
+
+2006-02-17 22:01  Eero Tamminen
+
+	* src/keymap.c: - bugfix: keycode variables need to be signed for
+	  check about undefined   key (value < 0) to work - tell use if
+	  keycode opening failed
+
+2006-02-17 22:00  Eero Tamminen
+
+	* src/options.c: add missing array initializer
+
+2006-02-17 21:59  Eero Tamminen
+
+	* src/blitter.c: remove unused skew argument
+
+2006-02-16 23:19  Eero Tamminen
+
+	* src/gemdos.c: use ferror(), fwrite() doesn't return an error code
+
+2006-02-16 23:07  Eero Tamminen
+
+	* src/dim.c: fix cast warning
+
+2006-02-16 22:51  Eero Tamminen
+
+	* doc/memory-usage.txt: added document on Hatari memory usage
+
+2006-02-15 20:16  Thomas Huth
+
+	* src/screen.c: STE color table can be used for both modes, ST and
+	  STE. This change fixes a problem when running Hatari with
+	  '--machine st --tos tos106.rom'
+
+2006-02-13 22:18  Eero Tamminen
+
+	* src/: fdc.c, includes/m68000.h: added defines for two magic
+	  values
+
+2006-02-13 22:18  Eero Tamminen
+
+	* src/: ikbd.c, gemdos.c, ioMem.c, spec512.c, vdi.c,
+	  includes/ikbd.h, includes/ioMem.h, includes/spec512.h: -
+	  "unsigned char" -> Uint8 - "unsigned short" -> Uint16 - Made some
+	  global variables static - Moved CYCLEPALETTE definition to
+	  spec512.c as it's not used elsewhere
+
+2006-02-12 22:35  Eero Tamminen
+
+	* src/misc.c: typo fixes for comments
+
+2006-02-12 22:28  Eero Tamminen
+
+	* src/: audio.c, blitter.c, cart.c, cartData.c, dmaSnd.c, file.c,
+	  floppy.c, ikbd.c, int.c, ioMem.c, ioMemTables.c, keymap.c,
+	  rs232.c, screen.c, sound.c, tos.c, vdi.c, xbios.c, zip.c,
+	  convert/macros.h, includes/audio.h, includes/file.h,
+	  includes/ioMemTables.h, includes/zip.h: Make some predefined
+	  arrays into const.  This required adding consts to some other
+	  places too (e.g. few public file.h functions)
+
+2006-02-12 22:24  Eero Tamminen
+
+	* src/Makefile: add options.c
+
+2006-02-12 22:23  Eero Tamminen
+
+	* src/: gemdos.c, includes/gemdos.h, includes/gemdos_defines.h: -
+	  minor cleanup in gemdos.h:   - move defines and structs used only
+	  in gemdos.c, to there   - move error and file attribute defines
+	  to internal gemdos_define.h - renamed badly/misleadingly named
+	  defines:   - MAX_PATH -> MAX_GEMDOS_PATH     (was used wrong in
+	  main.c option parsing) - make some gemdos.c variables static /
+	  const
+
+2006-02-12 19:53  Eero Tamminen
+
+	* src/: main.c, options.c, includes/options.h: - Move the Hatari
+	  option parsing from main.c to its own options.c file	 and
+	  rewrite it to be more automatic (at the same time fixes a few
+	  bugs	 in sizeof<->strlen comparison strncpy usage).	- Add const
+	  and static keywords where appropiate
+
+2006-02-09 23:02  Eero Tamminen
+
+	* src/uae-cpu/: build68k.c, fpp.c, gencpu.c, newcpu.c, newcpu.h,
+	  readcpu.c, readcpu.h: make the large opcode tables const, also
+	  some other array
+
+2006-02-09 22:55  Eero Tamminen
+
+	* src/gui-sdl/: font10x16.h, font5x8.h, sdlgui.c: Make font data
+	  const
+
+2006-02-08 23:51  Eero Tamminen
+
+	* src/memorySnapShot.c: const all rscids
+
+2006-02-08 23:49  Eero Tamminen
+
+	* src/: audio.c, bios.c, blitter.c, cart.c, cartData.c, cfgopts.c,
+	  configuration.c, createBlankImage.c, cycles.c, debugui.c,
+	  dialog.c, dim.c, dmaSnd.c, fdc.c, file.c, floppy.c, hdc.c,
+	  ikbd.c, int.c, ioMem.c, ioMemTables.c, joy.c, keymap.c, log.c,
+	  m68000.c, mfp.c, midi.c, misc.c, msa.c, printer.c, psg.c,
+	  reset.c, rs232.c, rtc.c, screen.c, screenSnapShot.c, shortcut.c,
+	  sound.c, spec512.c, st.c, stMemory.c, tos.c, unzip.c, vdi.c,
+	  video.c, wavFormat.c, xbios.c, ymFormat.c, zip.c: const all
+	  rscids + MFP float table
+
+2006-02-08 23:46  Eero Tamminen
+
+	* src/: gui-sdl/dlgAbout.c, gui-sdl/dlgAlert.c,
+	  gui-sdl/dlgDevice.c, gui-sdl/dlgDisc.c, gui-sdl/dlgFileSelect.c,
+	  gui-sdl/dlgJoystick.c, gui-sdl/dlgKeyboard.c, gui-sdl/dlgMain.c,
+	  gui-sdl/dlgMemory.c, gui-sdl/dlgNewDisc.c, gui-sdl/dlgRom.c,
+	  gui-sdl/dlgScreen.c, gui-sdl/dlgSound.c, gui-sdl/dlgSystem.c,
+	  gui-sdl/sdlgui.c, uae-cpu/build68k.c, uae-cpu/fpp.c,
+	  uae-cpu/gencpu.c, uae-cpu/hatari-glue.c, uae-cpu/memory.c,
+	  uae-cpu/newcpu.c, uae-cpu/readcpu.c: const all rscid's
+
+2006-02-08 10:17  Thomas Huth
+
+	* src/: memorySnapShot.c, includes/main.h: Increased version number
+	  to 0.82.
+
+2006-02-08 10:17  Thomas Huth
+
+	* src/video.c: Improved overscan emulation - e.g. the Level 16
+	  fullscreen in the union demo is working now.
+
+2006-02-08 10:16  Thomas Huth
+
+	* src/includes/screen.h: Increased the size of the bottom border.
+
+2006-02-07 17:32  Thomas Huth
+
+	* src/: video.c, includes/screen.h, includes/video.h: Added support
+	  for 60 Hz screen timings. Spectrum512 pictures that require 60 Hz
+	  are now working.
+
+2006-02-04 22:34  Eero Tamminen
+
+	* src/: cycles.c, includes/cycles.h: make Cycles_UpdateCounters
+	  static
+
+2006-02-04 17:44  Eero Tamminen
+
+	* src/: rs232.c, includes/rs232.h: - Made global funcs and
+	  variables that could be into static - This required moving the
+	  static function earlier in the code	(made the diff much larger)
+
+2006-01-30 23:26  Thomas Huth
+
+	* src/convert/: low320x16.c, low320x8.c, low640x16.c, low640x8.c,
+	  med640x16.c, med640x8.c, spec320x16.c, spec640x16.c, vdi16.c,
+	  vdi2.c, vdi4.c: Removed unnecessary casts to (void *).
+
+2006-01-30 23:06  Thomas Huth
+
+	* src/: cart.c, cartData.c: Rewrote the comments at the top of the
+	  file a little bit.
+
+2006-01-30 22:53  Thomas Huth
+
+	* doc/todo.txt: Added new items to the TODO list.
+
+2006-01-29 20:54  Eero Tamminen
+
+	* src/: mfp.c, includes/mfp.h: made several MFP variables and
+	  functions static
+
+2006-01-29 20:07  Eero Tamminen
+
+	* src/dmaSnd.c: make DmaSoundMode static
+
+2006-01-29 18:44  Eero Tamminen
+
+	* src/video.c: fix typo in comment
+
+2006-01-26 22:52  Thomas Huth
+
+	* src/: Makefile, cycles.c, int.c, memorySnapShot.c, sound.c,
+	  spec512.c, video.c, includes/cycles.h, includes/int.h,
+	  includes/m68000.h, includes/sound.h: Started new framework for
+	  better cycle counting.
+
+2006-01-23 22:08  Thomas Huth
+
+	* src/: reset.c, spec512.c, video.c, includes/main.h,
+	  includes/screen.h, includes/video.h: First steps towards 60 Hz
+	  video timing: cycles-per-line and scanlines-per-frame values are
+	  now stored in a variable instead of a fix define.
+
+2006-01-23 21:54  Eero Tamminen
+
+	* src/fdc.c: () -> (void)
+
+2006-01-23 20:47  Thomas Huth
+
+	* src/uae-cpu/gencpu.c: Improved PEA and LEA cycles again (thanks
+	  to Ijor for the explanation)
+
+2006-01-20 18:42  Thomas Huth
+
+	* src/: fdc.c, mfp.c, includes/fdc.h: Smarter FDC timings: Delay is
+	  aborted when a program reads the FDC interrupt bit in the GPIP
+	  register. (Thanks to Emmanuel Anne for the idea)
+
+2006-01-12 21:35  Thomas Huth
+
+	* src/convert/: low640x16.c, low640x8.c: Removed redundant
+	  AdjustLinePaletteRemap() function calls (Thanks to Emmanuel Anne
+	  for the patch).
+
+2006-01-02 21:55  Thomas Huth
+
+	* src/: cart.c, reset.c, includes/cart.h: Improved cartridge image
+	  loading: Hatari now supports ZIPed cartridges and .STC
+	  cartridges.
+
+2005-12-25 20:59  Thomas Huth
+
+	* src/screen.c: Added additional check if a resolution change is
+	  really necessary.
+
+2005-12-25 19:30  Thomas Huth
+
+	* src/uae-cpu/gencpu.c: Corrected cycles for LEA and PEA
+	  instructions (e.g. this is needed for the Level-16 fullscreen in
+	  the 'Union demo')
+
+2005-12-19 00:20  Thomas Huth
+
+	* src/: file.c, tos.c, zip.c, includes/file.h, includes/zip.h:
+	  Improved ZIP file reading: E.g. Hatari can now also load ROM
+	  images from a ZIP file.
+
+2005-12-18 19:50  Thomas Huth
+
+	* src/zip.c: Sourcecode beautification.
+
+2005-12-18 19:02  Thomas Huth
+
+	* src/: fdc.c, ikbd.c, m68000.c, mfp.c, midi.c, psg.c, rs232.c,
+	  includes/m68000.h, uae-cpu/newcpu.c: Improved the emulation of
+	  wait state cycles for certain IO memory registers.
+
+2005-12-17 11:22  Thomas Huth
+
+	* src/joy.c: Made some variables static.
+
+2005-12-02 22:08  Eero Tamminen
+
+	* src/: int.c, includes/int.h: Set a few variables and
+	  Int_SetNewInterrupt() function static.
+
+	  Hopefully this helps to make faster the UpdateInterrupt and
+	  SetNewInterrupt functions which are in top 10 slowest functions
+	  when profiling Posh demo with valgrind+callgrind.
+
+2005-11-30 21:50  Eero Tamminen
+
+	* doc/manual.html: added popstars and overdose demos
+
+2005-11-30 21:18  Eero Tamminen
+
+	* doc/manual.html: add hallucinations demo, pooz game and update
+	  info on wolf3d v0.8
+
+2005-11-30 18:01  Matthias Arndt
+
+	* doc/manual.html: small corrections in manual.html
+
+2005-11-23 20:08  Thomas Huth
+
+	* src/main.c: Added mouse wheel support by simulating a curser
+	  keypress.
+
+2005-11-23 18:43  Thomas Huth
+
+	* src/gemdos.c: The Pexec function now detects hard drive file
+	  names in a better way. Now you can drag and drop a file from a
+	  floppy to an application on the hard drive, or launch an
+	  associated application by clicking on a data file on a floppy.
+	  Thanks to Emmanuel Anne for the patch!
+
+2005-11-23 18:20  Thomas Huth
+
+	* src/dim.c: Updated comment about the .DIM headers.
+
+2005-11-15 13:24  Thomas Huth
+
+	* src/: main.c, video.c, includes/main.h: Improved the delay loop
+	  for systems where SDL_Delay is very inaccurate.
+
+2005-11-07 20:22  Thomas Huth
+
+	* doc/todo.txt: Added some more items to the TODO list
+
+2005-11-03 21:46  Eero Tamminen
+
+	* doc/manual.html: update on Pacemaker demo
+
+2005-11-01 22:16  Eero Tamminen
+
+	* doc/manual.html: minor updates, added chaos engine
+
+2005-11-01 21:21  Thomas Huth
+
+	* src/blitter.c: In smudge mode, the halftone offset is now
+	  determined before _each_ halftone access, not only once before
+	  the blitting operations starts. This fixes some screens in the
+	  Pacemaker demo by Paradox.
+
+2005-10-29 12:37  Eero Tamminen
+
+	* doc/manual.html: add ZX Spectrum emu
+
+2005-10-28 17:40  Matthias Arndt
+
+	* doc/manual.html: added Badger Badger by MjjProd to working STE
+	  demos
+
+2005-10-24 22:42  Eero Tamminen
+
+	* doc/manual.html: - added a few more apps - noted which of the
+	  tested apps/games were demos
+
+2005-10-22 00:00  Eero Tamminen
+
+	* src/blitter.c: oops, disable debug output
+
+2005-10-21 23:58  Eero Tamminen
+
+	* src/: blitter.c, ioMemTables.c, includes/blitter.h: Do changes to
+	  the blitter.c code: - LineNum -> Control register name change
+	  (line number is just low nibble of the control register) -
+	  Convert types and helper functions to SDL and Hatari ones - Add
+	  defines for register addresses (IMHO nicer) - Fix (one) bug with
+	  Smudge mode - Add documentation comments
+
+2005-10-21 11:23  Thomas Huth
+
+	* src/mfp.c: Due to a small bug, interrupt-in-service registers
+	  where not cleared when a program entered automatic MFP EOI mode.
+	  Fixed now. Popstars and Spinning-Wheels by YM-Rockerz are working
+	  now.
+
+2005-10-20 23:04  Eero Tamminen
+
+	* doc/manual.html: Added many applications and a few demos to ST &
+	  STE compatibility lists
+
+2005-10-20 09:52  Thomas Huth
+
+	* src/: ioMem.c, ioMemTables.c, main.c, includes/configuration.h,
+	  includes/ioMemTables.h: Added IO memory table for the Atari TT.
+
+2005-10-19 10:16  Thomas Huth
+
+	* src/tos.c: Patch TOS 3.06 to disable PMMU CPU access.
+
+2005-10-16 01:02  Eero Tamminen
+
+	* src/: blitter.c, includes/blitter.h: blitter.c cleanup: - make
+	  Do_Blit static - remove 'register' keywords (with today's C
+	  compilers they are redundant)
+
+2005-10-15 16:00  Thomas Huth
+
+	* src/gui-sdl/dlgJoystick.c: Fixed stupid bug that prevented proper
+	  SDL joystick selection.
+
+2005-10-14 22:28  Eero Tamminen
+
+	* doc/hatari.1: - Add stuff relevant for the new STE support - Wrap
+	  all text to 80 columns - Add FILES section
+
+2005-10-14 22:27  Eero Tamminen
+
+	* doc/manual.html: Add Pacemaker STE demo
+
+2005-10-12 : *** Version 0.80 ***
+
+2005-10-12 11:35  Thomas Huth
+
+	* readme.txt: Changes for Hatari version 0.80.
+
+2005-10-12 11:06  Thomas Huth
+
+	* configure.ac, doc/authors.txt, doc/release-notes.txt,
+	  src/memorySnapShot.c, src/includes/main.h: Changes for Hatari
+	  version 0.80.
+
+2005-10-12 11:05  Thomas Huth
+
+	* doc/todo.txt: Added TODO list.
+
+2005-10-11 22:43  Eero Tamminen
+
+	* doc/manual.html: added Accompanist ST app
+
+2005-10-11 19:13  Thomas Huth
+
+	* doc/: authors.txt, manual.html: Updated the documentation a
+	  little bit to suit the latest version of Hatari.
+
+2005-10-09 00:15  Eero Tamminen
+
+	* doc/manual.html: added hero STE game
+
+2005-10-08 11:48  Eero Tamminen
+
+	* doc/manual.html: update ST demo section
+
+2005-10-08 09:32  Eero Tamminen
+
+	* doc/manual.html: improved the ST applications section
+
+2005-10-08 08:53  Eero Tamminen
+
+	* doc/manual.html: added ultimate arena STE game
+
+2005-10-06 23:28  Eero Tamminen
+
+	* doc/manual.html: sort STE games, add Astrodia
+
+2005-10-06 20:47  Thomas Huth
+
+	* doc/: manual.html, images/joystick.png, images/main.png: Updated
+	  the main menu and the joystick setup dialog in the manual.
+
+2005-10-05 16:14  Thomas Huth
+
+	* src/: joy.c, includes/joy.h: Hatari supports more than one fire
+	  button for STE joypads.
+
+2005-10-04 23:44  Thomas Huth
+
+	* src/: debugui.c, dialog.c: Sourcecode beautification.
+
+2005-10-04 17:31  Thomas Huth
+
+	* src/: configuration.c, dialog.c, gemdos.c, hdc.c,
+	  memorySnapShot.c, tos.c, gui-sdl/dlgDisc.c,
+	  includes/configuration.h, includes/main.h, includes/tos.h:
+	  Improved hard disk emulation: Adding and removing a GEMDOS or
+	  ACSI hard disk should now work right.
+
+2005-10-04 15:13  Thomas Huth
+
+	* src/tos.c: Improved TOS patches: Anti-STE patches are now only
+	  applied when running in plain ST emulation and DMA boot patches
+	  are now also applied when only GEMDOS HD emulation is turned on.
+
+2005-10-04 14:43  Thomas Huth
+
+	* src/: mfp.c, includes/mfp.h: Changed type of variables from
+	  'unsigned char' to 'Uint8'.
+
+2005-10-04 11:45  Thomas Huth
+
+	* src/: screen.c, includes/video.h: Fixed SDL header includes.
+
+2005-10-04 11:24  Thomas Huth
+
+	* src/main.c: Sound buffer index variables are now reset after
+	  pausing the emulation.
+
+2005-09-29 10:36  Thomas Huth
+
+	* src/: gui-sdl/dlgJoystick.c, gui-sdl/sdlgui.c, includes/sdlgui.h:
+	  It is now possible to re-define the keys for the joystick
+	  emulation in the GUI.
+
+2005-09-28 23:44  Thomas Huth
+
+	* src/gui-sdl/dlgJoystick.c: SDL joystick name is now displayed in
+	  the GUI, too.
+
+2005-09-27 10:53  Thomas Huth
+
+	* src/: shortcut.c, sound.c, includes/sound.h: When switching from
+	  maximum to normal speed mode, do not reset complete sound
+	  emulation anymore, only the needed sound buffer index variable.
+
+2005-09-26 20:24  Thomas Huth
+
+	* src/keymap.c: When releasing a short-cut key, a key scan code was
+	  still sent to the emulated ST. Fixed now.
+
+2005-09-26 17:20  Thomas Huth
+
+	* src/: dmaSnd.c, fdc.c, floppy.c, rs232.c, wavFormat.c, zip.c,
+	  gui-sdl/sdlgui.c, includes/floppy.h, includes/wavFormat.h,
+	  uae-cpu/fpp.c: Fixed GCC 4.0 compiler warnings.
+
+2005-09-25 23:32  Thomas Huth
+
+	* src/: configuration.c, ioMemTables.c, joy.c, keymap.c, main.c,
+	  mfp.c, psg.c, gui-sdl/dlgJoystick.c, includes/configuration.h,
+	  includes/joy.h: Added support for STE joypads and parallel port
+	  joysticks.
+
+2005-09-15 11:42  Thomas Huth
+
+	* src/keymap.c: Removed some keys from the scancode detection
+	  function that are on different locations on qwertz and azerty
+	  keyboards.
+
+2005-09-15 02:11  Thomas Huth
+
+	* src/: dmaSnd.c, ioMemTables.c, includes/dmaSnd.h: Emulation of
+	  shifting/rotating microwire registers. Needed for some games like
+	  'Clogged up' that check the microwire registers for end of
+	  transfer.
+
+2005-09-13 22:55  Eero Tamminen
+
+	* doc/manual.html: updates to the STE games
+
+2005-09-13 03:10  Thomas Huth
+
+	* doc/manual.html, doc/release-notes.txt, src/bios.c, src/cart.c,
+	  src/configuration.c, src/createBlankImage.c, src/dialog.c,
+	  src/dim.c, src/fdc.c, src/file.c, src/floppy.c, src/gemdos.c,
+	  src/hdc.c, src/ioMemTables.c, src/main.c, src/memorySnapShot.c,
+	  src/msa.c, src/printer.c, src/st.c, src/tos.c, src/unzip.c,
+	  src/zip.c, src/gui-sdl/dlgDisc.c, src/gui-sdl/dlgMain.c,
+	  src/gui-sdl/dlgNewDisc.c, src/includes/configuration.h,
+	  src/includes/dialog.h, src/includes/dim.h, src/includes/fdc.h,
+	  src/includes/file.h, src/includes/floppy.h,
+	  src/includes/gemdos.h, src/includes/main.h, src/includes/msa.h,
+	  src/includes/printer.h, src/includes/st.h, src/includes/unzip.h,
+	  src/includes/zip.h: Changed "disc" to "disk" (the correct
+	  spelling for floppy and hard disk).
+
+2005-09-09 22:40  Eero Tamminen
+
+	* doc/manual.html: add powerup to STE enhanced games
+
+2005-09-01 22:53  Eero Tamminen
+
+	* doc/: manual.html, update-index.sh: - added script helping in
+	  html index creation - added index to the manual
+
+2005-09-01 21:38  Eero Tamminen
+
+	* doc/images/memory.png: updated memory dialog
+
+2005-09-01 21:20  Eero Tamminen
+
+	* src/video.c: fix comment on videobase alignment on TT
+
+2005-08-31 09:33  Matthias Arndt
+
+	* doc/manual.html: added initial STE compatibility list to the
+	  manual
+
+2005-08-29 22:13  Thomas Huth
+
+	* src/: joy.c, video.c, includes/video.h: Removed redundant
+	  variable VBLCounter. Changed frame skip code so that VDI screen
+	  rendering should now be a little bit faster. Removed the
+	  confusing and redundant BORDERMASK_TOP/BOTTOM code.
+
+2005-08-29 21:29  Thomas Huth
+
+	* src/: video.c, includes/video.h: Made some functions static.
+
+2005-08-22 00:20  Thomas Huth
+
+	* src/floppy.c: Code now checks if HD emulation is enabled before
+	  it tries to boot from hard drive.
+
+2005-08-21 23:15  Thomas Huth
+
+	* src/dmaSnd.c: Forgot to add a #include "memorySnapShot.h"
+
+2005-08-21 23:13  Thomas Huth
+
+	* src/: dmaSnd.c, memorySnapShot.c, reset.c, includes/dmaSnd.h: DMA
+	  sound variables are now cleared by ST reset and saved to memory
+	  snapshot files, too.
+
+2005-08-15 00:41  Thomas Huth
+
+	* src/ioMemTables.c: Fixed a stupid bug: IO-Memory handler for
+	  0xff8265 must not be IoMem_VoidRead since this returns 0xff
+	  (which is completely wrong here).
+
+2005-08-14 21:51  Eero Tamminen
+
+	* src/video.c: ScanLineWidth => ScanLineSkip
+
+2005-08-14 20:29  Eero Tamminen
+
+	* src/uae-cpu/memory.c: fix typo in comment
+
+2005-08-13 13:21  Thomas Huth
+
+	* src/: configuration.c, main.c, tos.c, gui-sdl/dlgMemory.c,
+	  includes/configuration.h, includes/tos.h, uae-cpu/memory.c,
+	  uae-cpu/memory.h: Improved the RAM size setting: Up to 14 MiB ST
+	  RAM are now possible.
+
+2005-08-13 10:59  Thomas Huth
+
+	* doc/manual.html, src/main.c: Added --machine command line option
+	  to select ST or STE mode.
+
+2005-08-11 09:55  Thomas Huth
+
+	* src/keymap.c: Added key with symbolic code 223.
+
+2005-08-08 16:10  Thomas Huth
+
+	* src/: ioMemTables.c, video.c, includes/video.h: STE Screen base
+	  address low register is now set to zero if a program writes to
+	  med or high register. Also improved the video address calculation
+	  function Video_CalculateAddress().
+
+2005-08-08 14:08  Thomas Huth
+
+	* src/: video.c, includes/main.h: STE fine scrolling now also works
+	  with overscan screens (see e.g. the MIND REWIND demo). It should
+	  now also work on little endian machines (not tested yet).
+
+2005-08-06 20:34  Thomas Huth
+
+	* doc/images/: fileselector.png, keyboard.png, system.png: Added
+	  new screenshots.
+
+2005-08-06 20:33  Thomas Huth
+
+	* doc/images/: fileselector.png, keyboard.png, system.png: Removed
+	  old screenshots.
+
+2005-08-06 20:30  Thomas Huth
+
+	* doc/manual.html: Updated the manual: Added STE features, updated
+	  some screenshots, etc.
+
+2005-08-06 14:32  Thomas Huth
+
+	* src/: Makefile, dmaSnd.c, int.c, ioMemTables.c, mfp.c, sound.c,
+	  video.c, includes/dmaSnd.h, includes/int.h, includes/sound.h:
+	  Added experimental STE DMA sound emulation.
+
+2005-08-05 21:45  Thomas Huth
+
+	* src/fdc.c: Decreased FDC time of waiting so that --slowfdc also
+	  works with TOS 1.06.
+
+2005-08-03 14:36  Thomas Huth
+
+	* src/video.c: Implemented STE monochrome fine scrolling.
+
+2005-08-03 02:55  Thomas Huth
+
+	* src/: includes/video.h, video.c: Added experimental STE
+	  horizontal fine scrolling.
+
+2005-07-30 16:02  Eero Tamminen
+
+	* src/: Makefile, screen.c, screenConvert.c, convert/high640x1.c,
+	  convert/high640x8.c, convert/low320x16.c, convert/low320x8.c,
+	  convert/low640x16.c, convert/low640x8.c, convert/macros.h,
+	  convert/med640x16.c, convert/med640x8.c, convert/routines.h,
+	  convert/spec320x16.c, convert/spec640x16.c, convert/vdi16.c,
+	  convert/vdi2.c, convert/vdi4.c, includes/screen.h,
+	  includes/screenConvert.h: Huge re-factoring to screenConvert.c
+	  and associated files: - Moved lookup tables and macros from
+	  screenConvert.c to   convert/macros.h   - Cleaned up the macros
+	  so that there's less than half of code left - Moved functions and
+	  variables from screenConvert.c to screen.c   - I also cleaned up
+	  these functions   - As a result, I removed screenConvert.c -
+	  Moved includes/screenConvert.h to includes/routines.h - Included
+	  convert/macros.h and convert/routines.h to screen.c As a result,
+	  I could do following: - Declare all convert/*.c functions static
+	  - Hide half of includes/screen.h variables to screen.c
+	  exclusively Additionally I: - Removed the global PixelWorkspace,
+	  ScrX and ScrY variables and used   local variables in convert/*.c
+	  functions instead (I pass the vertical   value to palette adjust
+	  function as argument) For Spec512 I didn't have a test-case,
+	  everything else is tested and "should" work
+
+2005-07-30 14:27  Eero Tamminen
+
+	* src/screen.c: fix STe palette for 8-bit screen
+
+2005-07-30 12:09  Eero Tamminen
+
+	* src/: screen.c, includes/screen.h, includes/vdi.h: cleanup: -
+	  Make screen.c functions that are not called elsewhere static	 -
+	  changed their order for this a bit - Fix typos in comments (+
+	  reformat some of them to fit 80-columns)
+
+2005-07-30 11:26  Eero Tamminen
+
+	* src/: ioMemTables.c, video.c, includes/video.h: Add STe Video
+	  Address Counter write support: - video.c:
+	  Video_ScreenCounter_WriteByte() and entries for it to to
+	  ioMemTables for STe (From Thomas, not me)
+
+2005-07-30 11:19  Eero Tamminen
+
+	* src/: video.c, includes/video.h: video.[ch]: Add support for for
+	  STe hardware scrolling registers: - Writing Video Base address
+	  low byte (checked in VBL) - Writing Line-Offset and Video Base
+	  Address Pixel Offset registers   (ScanLineWidth & HWScrollCount,
+	  checked in HBL)
+
+2005-07-30 11:07  Eero Tamminen
+
+	* src/: screen.c, screenConvert.c, spec512.c, video.c,
+	  includes/screen.h: Add STe palette support to Hatari: - Add STe
+	  palette masking to:	- video.c:Video_ColorReg_WriteWord() -
+	  Remove ST color value masking from:	-
+	  screenConvert.c:AdjustLinePaletteRemap()   - spec512.c   I'm
+	  assuming it's enough to do masking in video.c - In screen.[hc]:
+	  - Increase ST2RGB table size to STe palette size   -
+	  Screen_SetupRGBTable() handles now also STe palette bits   -
+	  Screen_CreatePalette() handles now also STe palette bits
+
+2005-07-30 10:44  Eero Tamminen
+
+	* Makefile.cnf, src/memorySnapShot.c, src/gui-sdl/Makefile,
+	  src/includes/memorySnapShot.h: - add more warnings in CFLAGS	 -
+	  disable them for gui-sdl/* - Add more consts to
+	  memorySnapShot.[ch]
+
+2005-07-26 10:41  Thomas Huth
+
+	* src/ioMemTables.c: Changed joypad interception functions so that
+	  Dynabusters+ can now be started.
+
+2005-07-20 11:30  Thomas Huth
+
+	* src/gemdos.c: Added Fattrib() GEMDOS call.
+
+2005-07-15 21:30  Thomas Huth
+
+	* src/: fdc.c, gemdos.c, m68000.c, screen.c, spec512.c, stMemory.c,
+	  vdi.c, video.c, xbios.c, ymFormat.c, includes/fdc.h,
+	  includes/m68000.h, includes/screen.h, includes/spec512.h,
+	  includes/stMemory.h, includes/vdi.h, includes/video.h: Changed
+	  some variable types to more sane ones (e.g. unsigned long to
+	  Uint32).
+
+2005-06-07 17:10  Matthias Arndt
+
+	* doc/: manual.html, images/devices.png, images/discs.png,
+	  images/fileselector.png, images/joystick.png,
+	  images/keyboard.png, images/main.png, images/memory.png,
+	  images/screen.png, images/sound.png, images/system.png,
+	  images/tos.png: added some explanatory pictures of the GUI to the
+	  manual
+
+2005-06-07 00:29  Thomas Huth
+
+	* src/: floppy.c, includes/floppy.h: Some cosmetic changes.
+
+2004-06-05 : *** Version 0.70 ***
+
+2005-06-05 19:36  Thomas Huth
+
+	* readme.txt: Changes for version 0.70.
+
+2005-06-05 19:29  Thomas Huth
+
+	* gpl.txt, doc/manual.html, src/gui-sdl/dlgAlert.c: Update FSF
+	  postal address.
+
+2005-06-05 19:01  Thomas Huth
+
+	* configure.ac, doc/manual.html, doc/release-notes.txt,
+	  src/memorySnapShot.c, src/includes/main.h: Changes for version
+	  0.70.
+
+2005-06-05 16:56  Thomas Huth
+
+	* src/shortcut.c: Added additional shortcut keys for options dialog
+	  and fullscreen (for systems which do not have F11 and F12)
+
+2005-06-05 16:19  Thomas Huth
+
+	* src/: cfgopts.c, configuration.c, createBlankImage.c, floppy.c,
+	  log.c, main.c, memorySnapShot.c, screenSnapShot.c, sound.c,
+	  tos.c, wavFormat.c, ymFormat.c, includes/cfgopts.h,
+	  includes/configuration.h, includes/log.h, includes/main.h,
+	  uae-cpu/newcpu.c: Improved the logging functions.
+
+2005-06-01 15:44  Thomas Huth
+
+	* src/: createBlankImage.c, file.c, includes/file.h: Fixed some
+	  compiler warnings when building Hatari on Solaris 8.
+
+2005-05-11 10:09  Thomas Huth
+
+	* src/dialog.c: Hatari does not temporarily leave the fullscreen
+	  mode anymore when the user changes the display mode options.
+
+2005-04-14 15:22  Thomas Huth
+
+	* src/gemdos.c: Removed unnecessary debugging code.
+
+2005-04-07 12:15  Thomas Huth
+
+	* src/: fdc.c, gemdos.c, printer.c, wavFormat.c, includes/fdc.h:
+	  Sourcecode beautification.
+
+2005-04-05 16:41  Thomas Huth
+
+	* src/: Makefile, audio.c, bios.c, debug.c, dialog.c, errlog.c,
+	  fdc.c, floppy.c, gemdos.c, hdc.c, ikbd.c, int.c, ioMem.c, joy.c,
+	  keymap.c, log.c, m68000.c, main.c, memorySnapShot.c, mfp.c,
+	  printer.c, rs232.c, sound.c, tos.c, video.c, xbios.c, zip.c,
+	  includes/debug.h, includes/errlog.h, includes/log.h,
+	  includes/main.h: Replaced the obsolete errlog.c and debug.c by
+	  the new log.c.
+
+2005-04-05 16:20  Thomas Huth
+
+	* src/gui-sdl/dlgMain.c: Added the new additional parameter for
+	  Configuration_Load.
+
+2005-04-04 17:27  Thomas Huth
+
+	* src/: file.c, includes/file.h: Cleaned up: Changed some "char *"
+	  to "const char *" and removed the unused File_Delete() function.
+
+2005-04-04 17:26  Thomas Huth
+
+	* Makefile.cnf, Makefile.cnf.in, src/Makefile, src/configuration.c,
+	  src/main.c, src/includes/configuration.h: Hatari can now also
+	  load a global configuration file (e.g. /etc/hatari.cfg).
+
+2005-04-04 13:38  Thomas Huth
+
+	* src/gemdos.c: Some code cleaned up. Added READ-ONLY bit to
+	  GemDOS_ConvertAttribute().
+
+2005-04-01 13:14  Thomas Huth
+
+	* src/: audio.c, bios.c, blitter.c, cfgopts.c, configuration.c,
+	  gemdos.c: Sourcecode beautification (indentation with tabs
+	  instead of spaces etc.).
+
+2005-03-17 10:01  Thomas Huth
+
+	* src/: cartData.c, cart_asm.s: The pexec code in the cartridge now
+	  works with 68010 - 68040 CPUs, too.
+
+2005-03-15 11:23  Thomas Huth
+
+	* src/ioMem.c: Added some boundary checks to avoid crashes when a
+	  program does a 'move.l $fffffe,d0' for example. Thanks to Eero for
+	  the hint.
+
+2005-03-14 14:08  Thomas Huth
+
+	* src/gemdos.c: Fixed some memory leaks in the Gemdos drive
+	  emulation functions (thanks to Eero Tamminen for the patch!).
+
+2005-03-11 11:10  Thomas Huth
+
+	* src/: gemdos.c, msa.c, includes/ioMem.h, includes/stMemory.h,
+	  uae-cpu/maccess.h, uae-cpu/memory.c, uae-cpu/newcpu.h: Fixed some
+	  GCC compiler warnings on certain architectures when compiling
+	  with the -Wcast-align parameter.
+
+2005-03-10 10:45  Thomas Huth
+
+	* src/file.c: Corrected a typo
+
+2005-03-10 10:41  Thomas Huth
+
+	* src/: file.c, floppy.c: Now using malloc instead of local arrays
+	  to avoid possible buffer overflows.
+
+2005-03-09 23:54  Thomas Huth
+
+	* src/: video.c, includes/video.h: Cleaned up the variables of
+	  video.c (removed unused, declared some as static, fixed types)
+	  and added support for the video address low byte in STE mode.
+
+2005-03-08 00:44  Thomas Huth
+
+	* src/unzip.c: Fixed GCC compiler warnings for compiling with
+	  -Wstrict-prototypes.
+
+2005-03-08 00:15  Thomas Huth
+
+	* Makefile.cnf, src/cfgopts.c, src/configuration.c, src/errlog.c,
+	  src/file.c, src/floppy.c, src/gemdos.c, src/ikbd.c, src/ioMem.c,
+	  src/main.c, src/memorySnapShot.c, src/mfp.c, src/screen.c,
+	  src/spec512.c, src/tos.c, src/ymFormat.c,
+	  src/gui-sdl/dlgFileSelect.c, src/gui-sdl/sdlgui.c,
+	  src/includes/cfgopts.h, src/includes/errlog.h,
+	  src/includes/file.h, src/includes/floppy.h,
+	  src/includes/gemdos.h, src/includes/ikbd.h, src/includes/main.h,
+	  src/includes/tos.h, src/includes/video.h,
+	  src/includes/ymFormat.h, src/uae-cpu/Makefile,
+	  src/uae-cpu/newcpu.c, src/uae-cpu/readcpu.c: Another Hatari code
+	  cleanup patch from Eero Tamminen: It makes more things that can
+	  be static, into static.  It makes more things that can be const,
+	  into const.  It removes some unused variables and declaration.
+	  It fixes a couple of prototypes.  It fixes a couple of signed vs.
+	  unsigned comparisons.  And it renames some local variables that
+	  shadow global variables.
+
+2005-02-28 09:47  Matthias Arndt
+
+	* doc/manual.html: documented most recent options like optional
+	  writeprotection for disk images and the updated System dialogue
+
+2005-02-25 14:56  Thomas Huth
+
+	* src/: spec512.c, includes/main.h: Cleaned up a little bit.
+
+2005-02-25 14:28  Thomas Huth
+
+	* src/: configuration.c, fdc.c, floppy.c, gui-sdl/dlgDisc.c,
+	  includes/configuration.h, includes/floppy.h: The user can now
+	  choose wether a floppy disk image should be write protected or
+	  not.
+
+2005-02-25 10:17  Thomas Huth
+
+	* src/gui-sdl/dlgSystem.c: Added STE mode warning.
+
+2005-02-24 21:26  Thomas Huth
+
+	* src/: configuration.c, file.c, main.c, gui-sdl/dlgDisc.c,
+	  gui-sdl/dlgFileSelect.c, gui-sdl/dlgRom.c, includes/file.h: Added
+	  some safety checks to avoid problems with invalid paths.
+
+2005-02-24 18:16  Thomas Huth
+
+	* doc/authors.txt, src/includes/stMemory.h, src/gemdos.c,
+	  src/tos.c, src/sound.c: Patches for compiling Hatari on a 64-bit
+	  Alpha machine (thanks to "Jo" for the patches!).
+
+2005-02-13 17:18  Thomas Huth
+
+	* src/: Makefile, audio.c, configuration.c, dim.c, file.c,
+	  gemdos.c, int.c, keymap.c, main.c, memAlloc.c, misc.c, msa.c,
+	  screen.c, screenSnapShot.c, shortcut.c, sound.c, tos.c, vdi.c,
+	  video.c, ymFormat.c, zip.c, gui-sdl/dlgDevice.c,
+	  gui-sdl/dlgDisc.c, gui-sdl/dlgKeyboard.c, gui-sdl/dlgMemory.c,
+	  gui-sdl/dlgNewDisc.c, gui-sdl/dlgSound.c, includes/main.h,
+	  includes/memAlloc.h, includes/misc.h: Code cleanup: Removed some
+	  unused and some redundant functions (especially from memAlloc.c)
+
+2005-02-13 00:11  Thomas Huth
+
+	* src/: includes/sdlgui.h, gui-sdl/dlgAbout.c, gui-sdl/dlgAlert.c,
+	  gui-sdl/dlgDevice.c, gui-sdl/dlgDisc.c, gui-sdl/dlgFileSelect.c,
+	  gui-sdl/dlgJoystick.c, gui-sdl/dlgKeyboard.c, gui-sdl/dlgMain.c,
+	  gui-sdl/dlgMemory.c, gui-sdl/dlgNewDisc.c, gui-sdl/dlgRom.c,
+	  gui-sdl/dlgScreen.c, gui-sdl/dlgSound.c, gui-sdl/dlgSystem.c,
+	  gui-sdl/sdlgui.c: It is now possible to scroll the file list in
+	  the file selection dialog with the mouse wheel and with the
+	  cursor keys.
+
+2005-02-12 18:04  Thomas Huth
+
+	* src/: configuration.c, m68000.c, gui-sdl/dlgSystem.c,
+	  includes/configuration.h, includes/m68000.h: Added support for 16
+	  and 32 MHz CPU clock.
+
+2005-02-12 17:15  Thomas Huth
+
+	* src/gui-sdl/sdlgui.c: Fixed a small bug - now checking for valid
+	  object number before accessing the dialog object flags.
+
+2005-02-11 20:57  Thomas Huth
+
+	* src/blitter.c: Changed the blitter behaviour: Bitblits are now
+	  executed immediately when a program writes to .
+
+2005-02-11 00:01  Thomas Huth
+
+	* src/gemdos.c: A small patch to Fsfirst: Now we only return the
+	  volume name if the program does not search for other file types,
+	  too. This fixes a problem with the game Mortar.
+
+2005-02-10 01:11  Thomas Huth
+
+	* src/: configuration.c, dialog.c, ioMem.c, ioMemTables.c, main.c,
+	  tos.c, gui-sdl/dlgSystem.c, includes/configuration.h,
+	  includes/ioMem.h, includes/ioMemTables.h: Added basic STE support
+	  (just enough to run TOS 1.06 and 1.62) and improved the "System"
+	  setup dialog.
+
+2005-02-02 22:53  Thomas Huth
+
+	* src/: fdc.c, ioMem.c, ioMemTables.c, m68000.c, includes/ioMem.h,
+	  includes/m68000.h, uae-cpu/newcpu.c: Added "void IO memory"
+	  handler and renamed some variables.
+
+2005-01-31 23:15  Thomas Huth
+
+	* src/: ioMemTables.c, Makefile, fdc.c, ioMem.c, includes/ioMem.h,
+	  includes/ioMemTables.h: Moved IO memory handler table to a
+	  separate file, improved its accuracy and split it into two
+	  tables, one for plain ST and one for Mega-ST (with blitter and
+	  RTC enabled).
+
+2005-01-29 23:42  Thomas Huth
+
+	* src/: ioMem.c, includes/ioMem.h: Rewrote the IO memory access
+	  function logic. Now it is possible to correctly emulate the
+	  addresses in the IO memory region that cause a bus error only in
+	  certain circumstances (e.g. access to 0xff8202). And the code is
+	  now a little bit less confusing, I hope ;-)
+
+2005-01-19 00:32  Thomas Huth
+
+	* src/: Makefile, blitter.c, configuration.c, debugui.c, dialog.c,
+	  fdc.c, ikbd.c, intercept.c, ioMem.c, m68000.c, main.c,
+	  memorySnapShot.c, mfp.c, midi.c, psg.c, video.c,
+	  includes/blitter.h, includes/fdc.h, includes/ikbd.h,
+	  includes/intercept.h, includes/ioMem.h, includes/m68000.h,
+	  includes/main.h, includes/mfp.h, includes/midi.h, includes/psg.h,
+	  includes/video.h, uae-cpu/memory.c: Cleaned up IO hardware
+	  register emulation: Moved functions from intercept.c to other
+	  files, especially the new file ioMem.c.Rewrote some functions and
+	  got rid of unused old code.
+
+2005-01-09 10:55  Thomas Huth
+
+	* src/: cart.c, cartData.c, cart_asm.s, hatari.x32,
+	  includes/cart.h: Added a cartridge program that shows some
+	  information about the keyboard shortcuts.
+
+2005-01-04 17:12  Thomas Huth
+
+	* src/floppy.c: Added some checks for illegal sector numbers to
+	  avoid crashes (thanks to Eero Tamminen for the hint).
+
+2004-12-27 01:03  Thomas Huth
+
+	* src/: includes/screen.h, includes/screenDraw.h, screen.c, vdi.c:
+	  More clean up in screen.c - finally got completely rid of the
+	  obsolete screenDraw.h
+
+2004-12-26 20:22  Thomas Huth
+
+	* src/: screen.c, includes/screen.h, includes/screenDraw.h: Rewrote
+	  the Screen_SetConvertDetails() function
+
+2004-12-19 : *** Version 0.60 ***
+
+2004-12-19 14:46  Thomas Huth
+
+	* configure.ac, readme.txt, doc/manual.html, doc/release-notes.txt,
+	src/cart.c, src/includes/main.h: Changes for version 0.60
+
+2004-12-19 11:59  Thomas Huth
+
+	* Makefile: Added DESTDIR for 'make install'
+
+2004-12-18 18:28  Matthias Arndt
+
+	* doc/manual.html: added cartridge documentation and altered video
+	dialog to the manual
+
+2004-12-14 22:29  Thomas Huth
+
+	* doc/hatari.1: Added --cartridge and --window options in the man
+	file.
+
+2004-12-09 22:06  Thomas Huth
+
+	* src/: cart.c, main.c, tos.c, gui-sdl/dlgRom.c: Added the
+	possibility to load an alternative cartridge image file.
+
+2004-12-08 11:27  Thomas Huth
+
+	* src/: cart.c, cart_asm.s, cartimg.c, gemdos.c, tos.c,
+	includes/cart.h, includes/main.h, uae-cpu/hatari-glue.c,
+	uae-cpu/hatari-glue.h, uae-cpu/newcpu.c: Improved, fixed and
+	cleaned up the cartridge code.
+
+2004-12-06 00:30  Thomas Huth
+
+	* src/: Makefile, configuration.c, dialog.c, main.c, screen.c,
+	tos.c, gui-sdl/Makefile, gui-sdl/dlgMain.c, gui-sdl/dlgRom.c,
+	gui-sdl/dlgScreen.c, gui-sdl/dlgTosGem.c, includes/configuration.h,
+	includes/dialog.h, includes/main.h, includes/screen.h: Cleaned up
+	the screen options: Moved VDI resolution setup to the "Screen"
+	dialog and renamed the "interlaced mode" to "interleaved mode".
+
+2004-12-03 21:42  Thomas Huth
+
+	* src/: main.c, reset.c, screen.c, gui-sdl/dlgMain.c,
+	includes/main.h: PC mouse pointer is now better in sync with the ST
+	mouse pointer.
+
+2004-12-01 00:05  Thomas Huth
+
+	* src/: screen.c, includes/screen.h, includes/screenDraw.h: Started
+	to clean up the screen resolution setup code mess.
+
+2004-11-14 17:47  Matthias Arndt
+
+	* doc/manual.html: added --windowed option to manual
+
+2004-11-14 03:34  Thomas Huth
+
+	* src/: ikbd.c, main.c, screen.c, includes/main.h: First mouse
+	movement is now ignored to avoid problems with certain ST programs
+	(e.g. Serenade disk 54). ikbd.c is now independent from
+	bInitGemDOS.
+
+2004-10-31 18:32  Thomas Huth
+
+	* Makefile.cnf.in, src/Makefile, src/file.c, src/int.c, src/main.c,
+	src/memorySnapShot.c, src/reset.c, src/gui-sdl/Makefile,
+	src/gui-sdl/dlgAbout.c, src/gui-sdl/dlgAlert.c,
+	src/includes/dialog.h, src/includes/int.h, src/includes/main.h,
+	src/includes/sdlgui.h: Added alert box to the GUI (based on code
+	taken from ARAnyM - cheers!) and cleaned up some files (e.g.
+	removed obsolete USE_DEBUGGER code lines)
+
+2004-10-01 10:49  Thomas Huth
+
+	* src/: file.c, includes/file.h: Cleaned up the scandir() function
+	a little bit.
+
+2004-09-24 18:06  Thomas Huth
+
+	* src/configuration.c: Added missing #include "audio.h"
+
+2004-09-24 14:55  Thomas Huth
+
+	* src/: configuration.c, dialog.c, main.c, screen.c,
+	includes/configuration.h, includes/dialog.h, includes/screen.h:
+	Cleaned up configuration options. Window/fullscreen mode is now
+	correctly initialized from the configuration file. Added --window
+	command line option to force a start in window mode. (Thanks to wwp
+	for the hint)
+
+2004-09-24 13:19  Thomas Huth
+
+	* src/audio.c: Fixed a bug in the initialization phase of the sound
+	subsystem that caused the sound init to fail when the user
+	specified another sound rate than 22050 in the configuration file
+	(thanks to wwp for the patch).
+
+2004-08-11 16:41  Matthias Arndt
+
+	* doc/manual.html: sorted Appendix C into 3 sections: games, demos
+	and applications, some cleanup
+
+2004-08-03 23:18  Thomas Huth
+
+	* src/rs232.c: BeOS seems to lack cfmakeraw(), so we use our own
+	cfmakeraw() now there, too
+
+2004-07-26 23:32  Thomas Huth
+
+	* doc/release-notes.txt: Adjusted release date.
+
+2004-07-26 23:32  Thomas Huth
+
+	* src/rs232.c: Added correct type cast for system where speed_t is
+	a typedef to unsigned int.
+
+2004-07-26 : *** Version 0.50 ***
+
+2004-07-26 14:12  Thomas Huth
+
+	* src/rs232.c: Fixed a little typing error.
+
+2004-07-26 13:39  Thomas Huth
+
+	* src/rs232.c: Added a cfmakeraw() function for Solaris.
+
+2004-07-25 15:50  Thomas Huth
+
+	* doc/authors.txt, src/intercept.c, src/rs232.c, src/xbios.c,
+	src/includes/rs232.h: RS232 baud rate is now set up directly from
+	the ST hardware registers, so there is no more need to patch the
+	XBIOS to read the values from Rsconf().
+
+2004-07-23 10:41  Thomas Huth
+
+	* src/: file.c, includes/file.h: Enabled scandir() and alphasort()
+	for Solaris so that Hatari now also compiles on this OS.
+
+2004-07-20 16:46  Thomas Huth
+
+	* doc/: hatari.1, manual.html, release-notes.txt: Updated the
+	documentation files.
+
+2004-07-16 22:06  Thomas Huth
+
+	* src/gui-sdl/: font10x16.bmp, font10x16.h: Added missing "="
+	character.
+
+2004-07-15 22:33  Thomas Huth
+
+	* src/rs232.c: Added semaphore to sync free space in input buffer.
+
+2004-07-13 19:29  Thomas Huth
+
+	* src/unzip.c: zlib.h is now included in a correct way.
+
+2004-07-13 18:38  Thomas Huth
+
+	* readme.txt, src/includes/main.h: Increased version number to 0.50
+
+2004-07-13 18:33  Thomas Huth
+
+	* src/screen.c: Disabled double buffering because the GUI is not
+	yet ready for it.
+
+2004-07-08 10:52  Matthias Arndt
+
+	* doc/manual.html: fixed some manual glitches
+
+2004-07-08 10:50  Matthias Arndt
+
+	* doc/manual.html: documented serial support in the manual
+
+2004-07-06 22:14  Thomas Huth
+
+	* src/: rs232.c, xbios.c, includes/rs232.h: Fixed RS232 emulation
+	and added termios code for setting the device parameters.
+
+2004-07-05 22:06  Thomas Huth
+
+	* src/: configuration.c, dialog.c, main.c, rs232.c,
+	gui-sdl/dlgDevice.c, includes/configuration.h, includes/rs232.h:
+	The RS232 settings can now be configured in the GUI.
+
+2004-07-05 19:23  Thomas Huth
+
+	* doc/authors.txt: Added new contributors.
+
+2004-07-05 18:53  Thomas Huth
+
+	* src/cfgopts.c: Improved the configuration saving function: New
+	configuration options / options that are not yet listed in the
+	config file are now correctly saved, too
+
+2004-07-05 17:38  Thomas Huth
+
+	* src/gui-sdl/dlgDisc.c: Added buttons to eject the floppies and
+	the hard disc image.
+
+2004-07-01 22:56  Thomas Huth
+
+	* src/: fdc.c, main.c, includes/configuration.h: Added option
+	--slowfdc to slow down the FDC emulation for certain games/demos.
+
+2004-07-01 22:54  Thomas Huth
+
+	* src/floppy.c: Added a check if the track that should be
+	read/written is still on the disk image, so that Hatari does not
+	crash anymore with misbehaving ST programs.
+
+2004-06-24 21:29  Thomas Huth
+
+	* src/floppy.c: Cleaned up Floppy_FindDiscDetails() so that it
+	should now also work on CPUs that do not support unaligned memory
+	access.
+
+2004-06-24 16:52  Thomas Huth
+
+	* src/: main.c, includes/audio.h, audio.c, dialog.c, shortcut.c:
+	Enabling/disabling the sound should now work as expected.
+
+2004-06-18 20:07  Thomas Huth
+
+	* src/gui-sdl/sdlgui.c: Saving the background graphics before
+	displaying a dialog now also works with 8 BPP screen surfaces.
+
+2004-06-17 15:00  Matthias Arndt
+
+	* doc/manual.html: Manual: fixed some typing bugs, added URL,
+	general cleanup
+
+2004-06-15 23:49  Thomas Huth
+
+	* src/dim.c: Added support for writing DIM images (but it is still
+	disabled by default).
+
+2004-06-11 14:48  Thomas Huth
+
+	* src/gui-sdl/: dlgDevice.c, dlgKeyboard.c, dlgMain.c, dlgMemory.c,
+	dlgScreen.c, dlgTosGem.c, sdlgui.c: SDLGui_DoDialog() now saves and
+	restores the background graphics, so calling Screen_SetFullUpdate()
+	and Screen_Draw() in the dialogs is no longer necessary. This fixes
+	an ugly redrawing bug that appeared when loading memory snap shots
+	from a different screen resolution.
+
+2004-06-11 12:04  Thomas Huth
+
+	* src/: dialog.c, m68000.c, main.c, mfp.c, shortcut.c, video.c,
+	includes/m68000.h, uae-cpu/Makefile, uae-cpu/events.h,
+	uae-cpu/newcpu.c, uae-cpu/newcpu.h: Some speed optimization: Now
+	using regs.spcflags in a better way (for MFP interrupts and for
+	quitting the emulator).
+
+2004-05-25 13:36  Matthias Arndt
+
+	* doc/manual.html: slight corrections to the manual including
+	project credits
+
+2004-05-05 11:23  Thomas Huth
+
+	* Makefile.cnf, Makefile.cnf.in, configure.ac, src/Makefile,
+	src/uae-cpu/Makefile: Added some more configuration variables to
+	the build files to improve the compilation process (especially
+	cross compilation).
+
+2004-05-03 17:34  Thomas Huth
+
+	* src/zip.c: Changed a variable from signed to unsigned type
+	(Thanks to Eero for the patch).
+
+2004-04-30 21:23  Thomas Huth
+
+	* src/createBlankImage.c: Added #include dim.h
+
+2004-04-28 11:04  Thomas Huth
+
+	* src/: Makefile, createBlankImage.c, dim.c, file.c, floppy.c,
+	main.c, msa.c, st.c, zip.c, gui-sdl/dlgFileSelect.c,
+	includes/dim.h, includes/file.h, includes/floppy.h,
+	includes/main.h, includes/msa.h, includes/st.h, includes/zip.h: 1)
+	Hatari now supports reading of .DIM disk images.  2) Buffers for
+	the disk images are now allocated dynamically, it is now save	 to
+	use disk images with a size greater than 1.5MB.  3) Reading and
+	writing of GZipped files is now supported in the basic	  functions
+	in file.c ==> The emulator can now save to GZipped MSA disk images,
+	   too.
+
+2004-04-24 13:25  Thomas Huth
+
+	* doc/hatari.1: Added man-page for Hatari written by Marco Herrn
+	(Thanks!).
+
+2004-04-24 09:55  Thomas Huth
+
+	* src/uae-cpu/maccess.h: Fixed a stupid typo.
+
+2004-04-24 09:53  Thomas Huth
+
+	* src/uae-cpu/Makefile: Fixed a cross-compiling problem: HOSTCC
+	must not use the cross compilers CFLAGS!
+
+2004-04-23 17:33  Thomas Huth
+
+	* src/: bios.c, cart.c, debugui.c, fdc.c, gemdos.c, hdc.c, ikbd.c,
+	int.c, intercept.c, m68000.c, main.c, mfp.c, reset.c, rs232.c,
+	rtc.c, sound.c, spec512.c, stMemory.c, tos.c, vdi.c, video.c,
+	xbios.c, includes/decode.h, includes/intercept.h,
+	includes/m68000.h, includes/main.h, includes/stMemory.h,
+	uae-cpu/events.h, uae-cpu/memory.c, uae-cpu/newcpu.c: Removed
+	obsolete header file decode.h (Thanks to Eero for the patch). Fixed
+	a bug with double bus errors that caused a crash of the emulator.
+
+2004-04-22 10:40  Thomas Huth
+
+	* src/uae-cpu/maccess.h: Moved byte access functions to the end of
+	the file because they are the same in all cases. (Thanks to Eero
+	for the patch)
+
+2004-04-20 18:53  Thomas Huth
+
+	* src/uae-cpu/: maccess-non-aligned.h, maccess-big.h,
+	maccess-i86.h, maccess.h, memory.h: Cleaned up the memory access
+	functions.
+
+2004-04-20 15:58  Thomas Huth
+
+	* Makefile.cnf, configure.ac: Adjusted CFLAGS.
+
+2004-04-19 10:53  Thomas Huth
+
+	* Makefile.cnf, src/audio.c, src/bios.c, src/blitter.c,
+	src/cfgopts.c, src/configuration.c, src/createBlankImage.c,
+	src/debug.c, src/debugui.c, src/dialog.c, src/errlog.c, src/fdc.c,
+	src/file.c, src/floppy.c, src/gemdos.c, src/hdc.c, src/ikbd.c,
+	src/int.c, src/intercept.c, src/joy.c, src/keymap.c, src/main.c,
+	src/memorySnapShot.c, src/mfp.c, src/midi.c, src/misc.c, src/msa.c,
+	src/printer.c, src/reset.c, src/rtc.c, src/screen.c,
+	src/screenConvert.c, src/screenSnapShot.c, src/shortcut.c,
+	src/sound.c, src/st.c, src/stMemory.c, src/tos.c, src/unzip.c,
+	src/vdi.c, src/video.c, src/wavFormat.c, src/xbios.c, src/zip.c,
+	src/gui-sdl/dlgAbout.c, src/gui-sdl/dlgDisc.c,
+	src/gui-sdl/dlgJoystick.c, src/gui-sdl/dlgMain.c,
+	src/gui-sdl/dlgScreen.c, src/gui-sdl/sdlgui.c,
+	src/includes/cfgopts.h, src/includes/createBlankImage.h,
+	src/includes/debugui.h, src/includes/fdc.h, src/includes/file.h,
+	src/includes/gemdos.h, src/includes/hdc.h,
+	src/includes/screenConvert.h, src/includes/screenSnapShot.h,
+	src/includes/sdlgui.h, src/includes/sound.h,
+	src/includes/stMemory.h, src/uae-cpu/Makefile,
+	src/uae-cpu/build68k.c, src/uae-cpu/fpp.c, src/uae-cpu/gencpu.c,
+	src/uae-cpu/hatari-glue.c, src/uae-cpu/maccess-non-aligned.h,
+	src/uae-cpu/maccess.h, src/uae-cpu/newcpu.c, src/uae-cpu/readcpu.c:
+	General source code improvements: Declared a lot of functions and
+	variables as static that are only used in one file.  Functions
+	without parameters now use correct ANSI prototypes.  Added
+	accelerated memory access functions for systems that can do
+	non-aligned memory access.  (Thanks to Eero Tamminen for the huge
+	patch!)
+
+2004-04-15 00:36  Thomas Huth
+
+	* src/: gemdos.c, intercept.c, main.c, msa.c, stMemory.c, tos.c,
+	video.c, includes/decode.h, includes/main.h, includes/stMemory.h,
+	uae-cpu/maccess-big.h, uae-cpu/maccess-i86.h, uae-cpu/maccess.h,
+	uae-cpu/memory.c, uae-cpu/memory.h: Made a lot of functions static
+	(Thanks to Eero Tamminen for the patch).  The memory access
+	functions from stMemory.c have been made "static inline" for better
+	performance.  The STMemory_Swap68000* functions have been replaced
+	by the SDL_SwapBE* functions.  Removed some old code from the
+	maccess*.h files.
+
+2004-04-07 12:24  Thomas Huth
+
+	* src/: screen.c, includes/screen.h: Fixed SDL screen flipping in
+	full screen mode (e.g. for Mac OS X). And the mouse pointer is now
+	initially warped to the middle of the screen.
+
+2004-04-06 18:20  Thomas Huth
+
+	* src/: configuration.c, main.c, includes/configuration.h: Added a
+	command line option to load an alternative configuration file.
+
+2004-04-06 18:16  Thomas Huth
+
+	* src/createBlankImage.c: Fixed disc creation function so that it
+	now creates MS-DOS compatible disc images.
+
+2004-04-06 12:38  Thomas Huth
+
+	* src/gui-sdl/dlgFileSelect.c: Cleaned up the file selector code
+	and enlarged the dialog window.
+
+2004-04-05 20:52  Thomas Huth
+
+	* Makefile: Replaced the old 8x8 font by two new fonts (5x8 and
+	10x16). The fonts are now also compiled into the executable (thanks
+	to Martin Doering and the Aranym developers for that code).
+
+2004-04-05 20:49  Thomas Huth
+
+	* src/: font8.bmp, gui-sdl/Makefile, gui-sdl/dlgAbout.c,
+	gui-sdl/font10x16.bmp, gui-sdl/font10x16.h, gui-sdl/font5x8.bmp,
+	gui-sdl/font5x8.h, gui-sdl/sdlgui.c, includes/sdlgui.h: Replaced
+	the old 8x8 font by two new fonts (5x8 and 10x16). The fonts are
+	now also compiled into the executable (thanks to Martin Doering and
+	the Aranym developers for that code).
+
+2004-04-02 21:57  Thomas Huth
+
+	* src/fdc.c: Increased the motor slowing down count so that TOXIS
+	(the virus killer program) is now working with Hatari, too.
+
+2004-03-26 10:45  Matthias Arndt
+
+	* doc/manual.html: added documentation of the Timer-D patch to the
+	manual
+
+2004-03-25 11:32  Matthias Arndt
+
+	* doc/manual.html: updated the manual to include documentation for
+	the disk image creation
+
+2004-03-01 14:57  Thomas Huth
+
+	* src/: configuration.c, intercept.c, mfp.c, gui-sdl/dlgSystem.c,
+	includes/configuration.h, includes/main.h, includes/mfp.h,
+	uae-cpu/hatari-glue.c: Improved Timer-D handling: - Timer-D is now
+	patched correctly (Dragons Breath is working again).  - The Timer-D
+	patch can now be switched on or off in the GUI.  - Removed the
+	unused code of the old Timer-D patch (Hatari version <= 0.30).
+
+2004-02-29 20:01  Thomas Huth
+
+	* src/uae-cpu/newcpu.c: Added some code to detect double bus
+	errors.
+
+2004-02-22 10:35  Thomas Huth
+
+	* src/: ikbd.c, mfp.c, midi.c, includes/mfp.h: Fixed a little bug
+	in mfp.c and renamed MFP_KEYBOARD_BIT to MFP_ACIA_BIT etc.
+
+2004-02-21 20:51  Thomas Huth
+
+	* src/: intercept.c, mfp.c, rs232.c, includes/mfp.h,
+	includes/rs232.h: Improved RS232 emulation: Now the MFP hardware
+	registers are intercepted to receive and to send the bytes of the
+	serial line.
+
+2004-02-21 14:24  Thomas Huth
+
+	* src/keymap.c: Added some more shorcut key modifiers (Thanks to
+	Tony Smolar for the hint about KMOD_RALT on US-keyboards).
+
+2004-02-21 11:01  Thomas Huth
+
+	* src/rs232.c: Improved RS232 emulation: Now using two file
+	handles, one for input and one for output data transfer.
+
+2004-02-19 16:22  Thomas Huth
+
+	* src/: intercept.c, m68000.c, includes/m68000.h, uae-cpu/memory.c,
+	uae-cpu/newcpu.c: Improved emulation of the special status word in
+	the exception stack frames of bus and address errors and fixed a
+	bug that caused an bus error when executing an illegal instruction
+	in user mode.
+
+2004-02-12 16:56  Thomas Huth
+
+	* src/: main.c, printer.c: Added some security checks to avoid
+	possible buffer overflows (Thanks to Steve Kemp for finding the
+	problematical code lines).
+
+2004-02-11 12:08  Thomas Huth
+
+	* src/: sound.c, includes/sound.h: Declared some functions and
+	variables as static for better compiler optimizations (Thanks to
+	Eero Tamminen for his patch).
+
+2004-02-10 12:49  Thomas Huth
+
+	* src/: audio.c, sound.c, includes/audio.h: Speed improvement:
+	Audio functions do not use float calculations any more (Thanks to
+	Eero Tamminen for his patch).
+
+2004-02-10 12:45  Thomas Huth
+
+	* configure.ac: Added some more checks to configure.ac (Thanks to
+	Patrice Mandin for his patch).
+
+2004-02-05 16:06  Thomas Huth
+
+	* src/: bios.c, fdc.c, floppy.c, includes/floppy.h: Replaced
+	bFloppyChanged by EmulationDrives.bMediaChanged
+
+2004-01-13 12:07  Thomas Huth
+
+	* src/: zip.c, gui-sdl/dlgFileSelect.c, includes/zip.h: Fixed some
+	small memory leaks.
+
+2004-01-12 13:21  Thomas Huth
+
+	* src/: main.c, rs232.c, includes/rs232.h: The RS232 code has been
+	rewritten to use portable functions (SDL threads and file functions
+	from stdio.h).
+
+2003-12-29 21:10  Thomas Huth
+
+	* src/: Makefile, gui-sdl/Makefile, gui-sdl/dlgDisc.c,
+	gui-sdl/dlgNewDisc.c: Added a dialog for creating new (blank)
+	floppy disc images.
+
+2003-12-28 23:32  Thomas Huth
+
+	* src/: intercept.c, m68000.c, includes/m68000.h, uae-cpu/newcpu.c,
+	uae-cpu/newcpu.h: Added experimental wait state cycles emulation.
+
+2003-12-25 19:45  Thomas Huth
+
+	* src/: file.c, gui-sdl/dlgTosGem.c, includes/file.h: Added a
+	function called File_MakeAbsoluteName to create absolute file names
+	from relative file names (thanks to Martin Doering for the idea).
+
+2003-12-25 15:19  Thomas Huth
+
+	* src/: configuration.c, createBlankImage.c, errlog.c, file.c,
+	floppy.c, main.c, memorySnapShot.c, screenSnapShot.c, vdi.c,
+	gui-sdl/dlgDevice.c, gui-sdl/dlgDisc.c, gui-sdl/dlgFileSelect.c,
+	gui-sdl/dlgKeyboard.c, gui-sdl/dlgMemory.c, gui-sdl/dlgSound.c,
+	gui-sdl/dlgTosGem.c, includes/configuration.h, includes/floppy.h,
+	includes/main.h: Replaced MAX_FILENAME_LENGTH by FILENAME_MAX
+	(thanks to Martin Doering for the hint)
+
+2003-11-05 19:20  Thomas Huth
+
+	* src/main.c: Added the --frameskip option again (it had been
+	removed by accident).
+
+2003-10-30 18:36  Thomas Huth
+
+	* Makefile: "make install" now also installs a tos.img if possible.
+
+2003-10-30 : *** Version 0.45 ***
+
+2003-10-30 17:03  Thomas Huth
+
+	* doc/release-notes.txt: Added changes for version 0.45
+
+2003-10-29 18:14  Matthias Arndt
+
+	* doc/manual.html: manual: documentation for build system updated
+
+2003-10-28 17:44  Matthias Arndt
+
+	* doc/manual.html: * updated the manual
+
+2003-10-25 14:26  Thomas Huth
+
+	* src/: blitter.c, m68000.c, memorySnapShot.c, gui-sdl/dlgMemory.c,
+	  includes/blitter.h, includes/main.h, uae-cpu/newcpu.c,
+	  uae-cpu/newcpu.h: Improved the memory snap shot function.
+
+2003-10-25 14:19  Thomas Huth
+
+	* readme.txt: Removed some text that describes how to use the
+	  emulator since this is now located in the manual.html
+
+2003-10-23 17:27  Thomas Huth
+
+	* doc/manual.html: Added new keyboard shortcuts.
+
+2003-10-23 16:30  Matthias Arndt
+
+	* src/printer.c: * cleaned up main comment block in printer.c
+
+2003-10-18 09:46  Thomas Huth
+
+	* src/: configuration.c, shortcut.c, sound.c, video.c, ymFormat.c,
+	  includes/shortcut.h: Added more shortcuts and removed old code
+	  from shortcut.c
+
+2003-10-18 09:41  Thomas Huth
+
+	* src/: createBlankImage.c, includes/createBlankImage.h: Started to
+	  clean up the "Create Blank Disc image" function.
+
+2003-10-18 09:38  Thomas Huth
+
+	* src/printer.c: Removed a fixed FIXME comment about printer file
+	  name.
+
+2003-10-18 09:36  Thomas Huth
+
+	* src/includes/main.h: Removed unused defines.
+
+2003-10-18 09:31  Thomas Huth
+
+	* src/debugui.c: The SR can now be set in the debugger.
+
+2003-10-17 11:48  Matthias Arndt
+
+	* src/psg.c: * corrected a few ugly typing bugs * better
+	  readability of the remarks for the printer dispatcher
+
+2003-10-11 22:59  Thomas Huth
+
+	* ChangeLog: Removed old ChangeLog - use a tool like cvs2cl to
+	  create an up-to-date ChangeLog file!
+
+2003-10-11 22:14  Thomas Huth
+
+	* src/floppy.c: Added a check for valid disc side -
+	  Floppy_ReadSectors now reports an error when a program tries to
+	  read from side 2 of a single sided disc.
+
+2003-10-10 18:41  Thomas Huth
+
+	* src/uae-cpu/: events.h, newcpu.c, newcpu.h: Removed two unused
+	  variables (broken_in and lastInstructionCycles).
+
+2003-10-09 21:48  Thomas Huth
+
+	* authors.txt, doc/authors.txt: Updated authors.txt and moved the
+	  file to the doc/ subdirectory
+
+2003-10-07 22:57  Thomas Huth
+
+	* src/: intercept.c, video.c, includes/syncTables.h,
+	  includes/video.h: Border opening is not done with the
+	  syncTables.h anymore, but with a more generic code so that some
+	  demos now also correctly show graphics in the right and left
+	  border
+
+2003-10-07 12:47  Matthias Arndt
+
+	* doc/manual.html: * completed features list in the manual * added
+	  documentation of the printer emulation to the manual * added
+	  documentation of the memory snapshots to the manual
+
+2003-09-28 21:57  Thomas Huth
+
+	* src/: dialog.c, m68000.c, memorySnapShot.c, video.c,
+	  gui-sdl/dlgMemory.c, includes/m68000.h,
+	  includes/memorySnapShot.h: Re-activated the memory snap shot
+	  functions.
+
+2003-09-28 21:50  Thomas Huth
+
+	* src/: configuration.c, includes/configuration.h: Midi, Printer
+	  and RS232 are now saved to the configuration file, too.
+
+2003-09-27 21:28  Thomas Huth
+
+	* src/: Makefile, createDiscImage.c, main.c, misc.c,
+	  includes/createDiscImage.h, includes/main.h, includes/misc.h:
+	  Cleaned up files: Removed unused functions and variables.
+
+2003-09-26 20:08  Thomas Huth
+
+	* src/: bios.c, xbios.c, uae-cpu/newcpu.c: Updated BIOS and XBIOS
+	  interception code.
+
+2003-09-02 23:56  Thomas Huth
+
+	* src/: main.c, uae-cpu/hatari-glue.c: Hatari now correctly
+	  de-initialized the UAE CPU core.
+
+2003-09-02 23:54  Thomas Huth
+
+	* src/: gui-sdl/dlgDisc.c, zip.c: Fixed a problem that sometimes
+	  caused a crash when browsing ZIPed disk images.
+
+2003-08-15 18:09  Thomas Huth
+
+	* src/: intercept.c, main.c, midi.c, includes/configuration.h,
+	  includes/midi.h: Added initial midi emulation.
+
+2003-08-12 16:44  Thomas Huth
+
+	* src/: printer.c, gui-sdl/dlgDevice.c: The file name for printer
+	  emulation can now be selected with the GUI.
+
+2003-08-11 21:37  Thomas Huth
+
+	* src/: configuration.c, ymFormat.c, gui-sdl/dlgDisc.c,
+	  gui-sdl/dlgFileSelect.c, gui-sdl/dlgKeyboard.c,
+	  gui-sdl/dlgSound.c, gui-sdl/dlgTosGem.c, gui-sdl/sdlgui.c,
+	  includes/sdlgui.h: Added editable text fields to the SDL-GUI. It
+	  is now also possible to select a destination file name for the
+	  sound grabbing in the sound setup dialog
+
+2003-08-10 19:08  Matthias Arndt
+
+	* src/printer.c: corrected stupid string bug in printer.c, $HOME no
+	  longer gets overwritten
+
+2003-08-10 16:44  Thomas Huth
+
+	* src/gui-sdl/.cvsignore: Added cvsignore file in the gui-sdl/
+	  directory
+
+2003-08-10 10:09  Matthias Arndt
+
+	* doc/manual.html, src/gemdos.c, src/main.c, src/printer.c,
+	  src/psg.c:
+	  * fixed bit bug in psg.c - STROBE bit detection used wrong bit *
+	  reenabled printer handling in gemdos.c * added commandline option
+	  --printer to activate (experimental) printer	 support * added
+	  Hatari User's Manual to doc/
+
+2003-08-09 17:54  Matthias Arndt
+
+	* src/: printer.c, psg.c:
+	  - rewrote printer interception in psg.c  (to solve the problem
+	  "music playing results in printing characters") - simple
+	  emulation of STROBE signal for printing
+
+2003-08-09 16:00  Matthias Arndt
+
+	* Makefile.cnf, src/printer.c: [no log message]
+
+2003-08-09 15:58  Matthias Arndt
+
+	* Makefile.cnf, src/keymap.c, src/mfp.c, src/printer.c, src/psg.c,
+	  src/includes/printer.h:
+	  - added simple printer support (printing to file) - added printer
+	  hook to psg.c - added flag correction to mfp.c
+
+	  Todo: Configuration for printing support (filename, enabled)
+
+2003-08-06 18:17  Thomas Huth
+
+	* src/msa.c: Fixed a bug in the MSA compression function that could
+	  create corrupted MSA disk images in some rare cases.
+
+2003-08-05 18:39  Thomas Huth
+
+	* src/uae-cpu/build68k.c: Now including string.h - this fixes a
+	  compiler warning with GCC 3.0
+
+2003-08-05 18:37  Thomas Huth
+
+	* src/includes/sdlgui.h: Moved some define from sdlgui.c to
+	  sdlgui.h
+
+2003-08-05 18:36  Thomas Huth
+
+	* src/includes/screen.h: Added prototype for
+	  Screen_DidResolutionChange()
+
+2003-08-05 18:34  Thomas Huth
+
+	* src/uae-cpu/cpuopti.c: Removed unused file cpuopti.c
+
+2003-08-05 18:33  Thomas Huth
+
+	* src/: dialog.c, sdlgui.c, gui-sdl/dlgFileSelect.c,
+	  gui-sdl/sdlgui.c: Moved sdlgui.c to the src/gui-sdl/ folder and
+	  created a new file for the file selection dialog.
+
+2003-08-05 18:29  Thomas Huth
+
+	* .cvsignore, Makefile, Makefile.cnf, Makefile.cnf.in,
+	  configure.ac, src/gui-sdl/Makefile, src/Makefile,
+	  src/uae-cpu/Makefile: Added new build system: Now there is a top
+	  level makefile configuration file and a configure.ac to create a
+	  configure script.
+
+2003-08-04 21:37  Thomas Huth
+
+	* src/gui-sdl/: dlgAbout.c, dlgDevice.c, dlgDisc.c, dlgJoystick.c,
+	  dlgKeyboard.c, dlgMain.c, dlgMemory.c, dlgScreen.c, dlgSound.c,
+	  dlgSystem.c, dlgTosGem.c: Separated the SDL GUI dialogs from
+	  dialog.c and put each dialog in a new file.
+
+2003-08-02 17:45  Thomas Huth
+
+	* src/uae-cpu/: maccess-big.h, maccess.h: Added accelerated memory
+	  access functions.
+
+2003-07-30 00:25  Thomas Huth
+
+	* ChangeLog: Fixed some typos
+
+2003-07-29 14:01  Thomas Huth
+
+	* src/: int.c, m68000.c, mfp.c, video.c, includes/int.h,
+	  includes/m68000.h, uae-cpu/hatari-glue.c, uae-cpu/hatari-glue.h,
+	  uae-cpu/newcpu.c: Changed M68000_Exception(), intlev() and
+	  do_specialties() and some other interrupt related parts: Pending
+	  interrupts are now handled in the UAE CPU core.
+
+2003-07-28 18:42  Thomas Huth
+
+	* src/uae-cpu/maccess-i86.h: Revived old accelerated maccess.h for
+	  i86 computers.
+
+2003-07-21 00:52  Thomas Huth
+
+	* src/gemdos.c: emudrives[0]->fs_currpath is now correctly
+	  initialized - this fixes a problem with HD emulation on EmuTOS.
+
+2003-07-11 17:48  Thomas Huth
+
+	* doc/release-notes.txt: Added release notes file
+
+2003-07-11 : *** Version 0.40 ***
+
+2003-07-04 14:40  Thomas Huth
+
+	* src/uae-cpu/newcpu.c: Disabled MFP interrupt cycles again since
+	they currently seem to make some things running worse.
+
+2003-07-04 14:38  Thomas Huth
+
+	* src/configuration.c: bFrameSkip is now saved to the configuration
+	file, too.
+
+2003-06-28 16:42  Thomas Huth
+
+	* doc/keymap-sample.txt: Added keymap sample file.
+
+2003-06-28 16:36  Thomas Huth
+
+	* readme.txt: Added comment about how to use incompatible MSA disk
+	images.
+
+2003-06-28 16:32  Thomas Huth
+
+	* src/video.c: Main_EventHandler is now called every 64th hbl event
+	so that the mouse moves smoother in VDI resolutions again.
+
+2003-06-28 16:29  Thomas Huth
+
+	* src/keymap.c: Fixed a little bug: Switching back to symbolic
+	keymapping mode from loaded keymapping mode did not work right.
+
+2003-06-23 20:49  Thomas Huth
+
+	* src/: fdc.c, floppy.c, includes/floppy.h: When the user changes a
+	floppy disk image, the write-protection signal of the FDC is now
+	raised for a short time since some programs use this behaviour to
+	check for changed disks.
+
+2003-06-22 22:20  Thomas Huth
+
+	* src/main.c: Now booting from harddrive when using the -d
+	parameter (Thanks to Sven for the patch)
+
+2003-06-20 15:13  Thomas Huth
+
+	* src/: cartimg.c, reset.c, includes/main.h, uae-cpu/hatari-glue.c,
+	uae-cpu/hatari-glue.h, uae-cpu/newcpu.c: Now using a separate
+	illegal opcode for system initialization (setting the connected
+	drive mask etc.), so that warm resets are working right again.
+	(Thanks to Matthias Arndt for the hint)
+
+2003-06-17 21:37  Thomas Huth
+
+	* src/gemdos.c: Fixed a problem with Fsfirst and Fsnext so that HD
+	emulation is now working with EmuTOS, too.
+
+2003-06-17 20:03  Thomas Huth
+
+	* src/: screen.c, uae-cpu/newcpu.c: Fixed two bugs that appeared in
+	the extended VDI resolution emulation
+
+2003-06-15 21:15  Thomas Huth
+
+	* src/includes/main.h: Updated version number to 0.40
+
+2003-06-15 21:14  Thomas Huth
+
+	* src/dialog.c: Cosmetic changes to the screen setup dialog.
+
+2003-06-12 22:41  Thomas Huth
+
+	* src/: sdlgui.c, zip.c: It is now also possible to select a ZIP
+	file in the file selector without choosing a disk image in the ZIP
+	package (the first ST or MSA file will be used then)
+
+2003-06-10 18:45  Thomas Huth
+
+	* src/vdi.c: GemDOS_CreateHardDriveFileName() needs backslash as
+	path seperator instead of a normal slash while creating the
+	filename for /DESKTOP.INF or /NEWDESK.INF
+
+2003-06-09 20:20  Thomas Huth
+
+	* readme.txt: Updated readme.txt to suit the current version of
+	Hatari (-> version 0.40)
+
+2003-06-09 18:11  Thomas Huth
+
+	* src/screen.c: 8 bpp mode is now working in windowed mode, too
+
+2003-06-08 19:12  Thomas Huth
+
+	* src/: intercept.c, rtc.c, includes/intercept.h, includes/rtc.h:
+	Real time clock now also works with TOS 1.02 and 1.04
+
+2003-06-08 15:54  Thomas Huth
+
+	* src/main.c: The order of --hdimage and --harddrive does not
+	matter anymore and there is now also a command line parameter to
+	specify the emulated RAM size.
+
+2003-06-08 15:49  Thomas Huth
+
+	* src/: configuration.c, gemdos.c, hdc.c, includes/configuration.h:
+	Hard disc image and directory can now be saved in the configuration
+	file, too
+
+2003-06-07 19:36  Thomas Huth
+
+	* authors.txt: Added contributors to the file authors.txt
+
+2003-06-07 15:43  Thomas Huth
+
+	* src/floppy.c: Floppy_ReadSectors() now correctly returns FALSE if
+	something went wrong
+
+2003-06-02 18:20  Thomas Huth
+
+	* src/uae-cpu/newcpu.c: Mode-change specialflag won't be cleared
+	during reset anymore so that you can now change the compatibility
+	cpu mode and reset the cpu at the same time
+
+2003-06-02 18:18  Thomas Huth
+
+	* src/keymap.c: Added more symbolic key mapping values (e.g. the
+	pipe character key)
+
+2003-06-02 18:17  Thomas Huth
+
+	* src/gemdos.c: Pexec(6) is only available on TOS >= 1.04
+
+2003-06-01 22:04  Thomas Huth
+
+	* src/: dialog.c, keymap.c: Enabled the possibility to load an
+	alternative keyboard mapping from a file.
+
+2003-06-01 18:23  Thomas Huth
+
+	* src/uae-cpu/newcpu.c: Corrected MFP interrupt cycle timing.
+
+2003-05-25 00:12  Thomas Huth
+
+	* src/ikbd.c: In Lotus Turbo Esprit Challange and some other games,
+	the second joystick was not working so that two player mode was not
+	usable. This has been fixed now.
+
+2003-05-05 19:53  Thomas Huth
+
+	* src/sdlgui.c: ypos wasn't reset when entering a ZIP directory for
+	browsing.
+
+2003-04-29 18:17  Thomas Huth
+
+	* src/: dialog.c, configuration.c, main.c: Added buttons to load
+	and save the configuration file. It is now no longer saved
+	automatically when you quit Hatari. The configuration file is now
+	also stored in the users home directory when the HOME environment
+	variable has been set.
+
+2003-04-29 18:12  Thomas Huth
+
+	* src/includes/main.h: Corrected comment about scan lines per VBL
+	in 60Hz
+
+2003-04-28 19:48  Thomas Huth
+
+	* src/: configuration.c, dialog.c, m68000.c, mfp.c,
+	includes/main.h, includes/mfp.h: Removed the high-speed-CPU code.
+	It wasn't working very well and I currently don't have the time and
+	motivation to fix it.  Support for CPU emulation with more than
+	8MHz will probably be included again later.
+
+2003-04-25 23:11  Thomas Huth
+
+	* src/dialog.c: The memory for zip_path was sometimes freed twice
+	what caused Hatari to crash or hang.
+
+2003-04-16 14:49  Thomas Huth
+
+	* src/video.c: Disabled setting of the screen refresh rate again
+	since it was currently breaking the sound in monochrome mode
+
+2003-04-12 18:31  Thomas Huth
+
+	* src/: dialog.c, sdlgui.c, includes/sdlgui.h: Moved call to
+	SDLGui_PrepareFont() back to dialog.c, where it belongs to. Also
+	removed unused debugging function SDLGui_OverlayText().
+
+2003-04-12 18:28  Thomas Huth
+
+	* src/: audio.c, sound.c, includes/sound.h: Slightly improved the
+	sound callback function. It now tries to correctly fill up the
+	sound buffer when not enough samples have been created
+
+2003-04-12 18:26  Thomas Huth
+
+	* src/: main.c, video.c, includes/video.h: Now using SDL_GetTicks
+	instead of a SDL timer to sync the emulator with the VBL since SDL
+	timers are not working right on some systems (MiNT).
+
+2003-04-12 18:23  Thomas Huth
+
+	* src/m68000.c: CYCLES_PER_SEC are now set correctly to 8MHz timing
+	again.
+
+2003-04-12 13:29  Thomas Huth
+
+	* src/zip.c: Fixed a little bug: ZIPped .ST disk images were not
+	loadable from the command line. Thanks to Markus Oberhumer for the
+	patch.
+
+2003-04-08 13:38  Emmanuel Anne
+
+	* src/: configuration.c, dialog.c, m68000.c, mfp.c,
+	includes/main.h, includes/mfp.h:
+	add a setting to choose the cpu speed (in the gui, and nMinMax in
+	the configuration file).
+
+2003-04-08 13:37  Emmanuel Anne
+
+	* src/: main.c, sdlgui.c, includes/sdlgui.h:
+	add SDLGui_OverlayText to be able to display some text on overlay
+	over the current screen, and call sdlgui_init at the end of
+	main_init to prepare the font here (usefull for the overlay)
+
+2003-04-07 13:34  Thomas Huth
+
+	* src/cfgopts.c: Improved the configuration file loading/saving:
+	Included the function trim() to allow white spaces in the cfg file
+	(taken from Aranym - cheers); the temporary file name is now
+	created properly with tmpfile(); changed the C++ comments to plain
+	ANSI-C comments.
+
+2003-04-06 20:52  Thomas Huth
+
+	* src/: .cvsignore, Makefile: Added 'make depend' target to the
+	Makefile
+
+2003-04-06 15:05  Emmanuel Anne
+
+	* src/: cart_asm.s, cartimg.c:
+	patch from Paul Bates (winston author) which fixes the bus error
+	problem in the gfabasic when run from a gemdos hd drive.
+
+2003-04-06 00:25  Thomas Huth
+
+	* src/: m68000.c, memorySnapShot.c, misc.c, video.c,
+	includes/decode.h, includes/m68000.h, uae-cpu/memory.c,
+	uae-cpu/newcpu.c: Improved bus errors (M68000_BusError) and added
+	exception cycles
+
+2003-04-04 18:28  Thomas Huth
+
+	* src/: Makefile, audio.c, cfgopts.c, configuration.c,
+	createBlankImage.c, dialog.c, fdc.c, file.c, floppy.c, gemdos.c,
+	hdc.c, keymap.c, main.c, screen.c, video.c, includes/cfgopts.h,
+	includes/configuration.h, includes/dialog.h: Added ASCII
+	configuration file and moved configuration structs from dialog.h to
+	configuration.h (where they belong to).
+
+2003-04-04 14:48  Emmanuel Anne
+
+	* src/: m68000.c, uae-cpu/newcpu.c, uae-cpu/memory.c:
+	new bus error handling : the exception must be called AFTER the
+	memory handler so that the rte returns to the instruction AFTER the
+	cause of the bus error (or debugers might enter infinite loops).
+
+2003-04-03 23:16  Thomas Huth
+
+	* src/uae-cpu/: hatari-glue.c, memory.c: Setting the connected
+	drive mask is now done in Opcode_GemDos()
+
+2003-04-03 23:14  Thomas Huth
+
+	* src/uae-cpu/: newcpu.c, newcpu.h: Now using special flag
+	SPCFLAG_BUSERROR for correction PC after bus error. This should
+	speed up the emulation a little bit
+
+2003-04-03 23:13  Emmanuel Anne
+
+	* src/fdc.c:
+	this test works better to filter hdc, sorry.
+
+2003-04-03 22:06  Emmanuel Anne
+
+	* src/fdc.c:
+	make the hdc fix more specific (it helped the hdc images from
+	working !)
+
+2003-04-03 22:05  Emmanuel Anne
+
+	* src/keymap.c:
+	try a reasonable default offset instead of -1 when the offset is
+	unknown. It helps a lot with my french keyboard when the 1st key I
+	press is 1 or 2 (both unknown !).
+
+2003-04-03 22:04  Emmanuel Anne
+
+	* src/ikbd.c:
+	fix bad passing of command keyboards. This fixes bad keys when
+	sr=$600 in adebug, so it might fix a few other things too...
+
+2003-04-03 19:10  Emmanuel Anne
+
+	* src/fdc.c:
+	fix the crash when booting with a floppy and a gemdos directory
+
+2003-04-02 22:54  Emmanuel Anne
+
+	* src/gemdos.c:
+	fix the bus error problem in gfa : it was because of a forgoten ";"
+	! Also change ifdefs to make debuging easier (FILE_DEBUG and
+	GEMDOS_VERBOSE)
+
+2003-04-02 22:53  Emmanuel Anne
+
+	* src/: intercept.c, tos.c, uae-cpu/hatari-glue.c,
+	uae-cpu/hatari-glue.h, uae-cpu/memory.c, uae-cpu/newcpu.c:
+	timer d and connected drives patches are not applied anymore to the
+	tos. Instead the relevant memory addresses are intercepted. It
+	should be as fast as before and it allows to boot ram tos and to be
+	able to mount hd directories on them. Also it fixes the timer d
+	problem on foreign toses (swedish...)
+
+2003-04-01 23:02  Thomas Huth
+
+	* src/tos.c: Now RAM TOS 1.00 can be loaded, too
+
+2003-04-01 22:59  Thomas Huth
+
+	* src/uae-cpu/memory.c: ROMmem_start --> f_RomMemStart
+
+2003-04-01 18:11  Thomas Huth
+
+	* src/: intercept.c, m68000.c, main.c, tos.c, uae-cpu/memory.c,
+	uae-cpu/memory.h, includes/decode.h, uae-cpu/hatari-glue.c,
+	uae-cpu/hatari-glue.h, includes/intercept.h: Improved memory
+	mapping - The memory regions should now behave much more like on a
+	real ST
+
+2003-04-01 13:18  Emmanuel Anne
+
+	* src/tos.c:
+	allow to load "ram tos", that is tos at address $ad00 (in ram !)
+	That's because I never found any french tos 1.04. most of the
+	patches fail, but it allows to boot a floppy image anyway...
+
+2003-03-31 15:34  Thomas Huth
+
+	* src/uae-cpu/hatari-glue.c: Added SPCFLAG_MODE_CHANGE when CPU
+	settings are changed
+
+2003-03-31 15:32  Thomas Huth
+
+	* src/zip.c: Sven's patch to use ZIP files from the command line
+
+2003-03-31 13:05  Emmanuel Anne
+
+	* src/uae-cpu/memory.c:
+	writing to rom trigers a bus error (exception 2).  Notice : it
+	might not be the Right Way to do it... but at least it allows crazy
+	boy cd 24 to boot !
+
+2003-03-31 13:04  Emmanuel Anne
+
+	* src/uae-cpu/newcpu.h:
+	prefetch buffer is aligned on word boundaries, not long word
+	boundaries
+
+2003-03-30 15:35  Thomas Huth
+
+	* src/: Makefile, dialog.c, file.c, floppy.c, sdlgui.c, ymFormat.c,
+	unzip.c, zip.c, includes/unzip.h, includes/zip.h, includes/file.h,
+	includes/floppy.h, includes/sdlgui.h: Added Sven's patch for ZIPped
+	and GZIPped disk images
+
+2003-03-30 13:32  Thomas Huth
+
+	* src/: configuration.c, dialog.c, keymap.c, main.c, screen.c,
+	includes/dialog.h, includes/keymap.h: Keyboard mapping is now
+	possible via both, scancode and ascii mapping
+
+2003-03-29 14:09  Thomas Huth
+
+	* src/: gemdos.c, misc.c, includes/misc.h: Renamed strupr to
+	Misc_strupr since the old name conflicted with a library function
+	when compiling for MiNT
+
+2003-03-29 14:06  Thomas Huth
+
+	* src/uae-cpu/Makefile: Introduced HOSTCC variable to be able to
+	cross compile Hatari
+
+2003-03-28 17:20  Thomas Huth
+
+	* src/uae-cpu/: compiler.c, Makefile, compiler.h, gencpu.c,
+	hatari-glue.c, memory.h, newcpu.c, newcpu.h, sysdeps.h: Removed
+	compiler.c and compiler.h. compiler.h genereted a conflict with the
+	system header compiler.h on MiNT, the necessary functions are now
+	in newcpu.h.
+
+2003-03-28 17:10  Emmanuel Anne
+
+	* src/gemdos.c:
+	fix for GemDos_GetDir (so that adebug can find its files when
+	launched from the hd), and use GEMDOS_VERBOSE for debuging
+
+2003-03-28 08:14  Emmanuel Anne
+
+	* src/main.c:
+	revert to previous version : we don't need --fd since "hatari
+	" does the job ! Sorry !
+
+2003-03-27 16:55  Emmanuel Anne
+
+	* src/floppy.c:
+	fix bad reading of little images (too paranoid - didn't trust
+	enough the bootsector !).
+
+2003-03-27 16:54  Emmanuel Anne
+
+	* src/main.c:
+	added --fd  comand line option to insert a floppy image
+	in drive a
+
+2003-03-27 12:24  Emmanuel Anne
+
+	* src/: screen.c, dialog.c, includes/screen.h,
+	includes/screenDraw.h, includes/syncTables.h:
+	lots of video changes (borders, and same options for windowed and
+	fullscreen modes)
+
+2003-03-27 12:23  Emmanuel Anne
+
+	* src/intercept.c:
+	top and bottom borders handling is now here (and much simpler than
+	before)
+
+2003-03-27 12:21  Emmanuel Anne
+
+	* src/video.c:
+	disable synctables for top and bottom borders (handled in
+	intercept.c now)
+
+2003-03-27 12:15  Emmanuel Anne
+
+	* src/dialog.c:
+	800x600 mode disappears, fullscreen and windowed modes share the
+	same options
+
+2003-03-27 12:15  Emmanuel Anne
+
+	* src/spec512.c:
+	a screen must have at least 150 lines with more than 1 palette to
+	be recognized as a spc512 screen. It's because this code does not
+	know how to display 1 palette/line, very bad for some demos...
+
+2003-03-27 11:55  Emmanuel Anne
+
+	* src/gemdos.c:
+	remove a debug message, add a fix for SFirst to avoid a malloc(0)
+	when there is no match
+
+2003-03-25 22:03  Emmanuel Anne
+
+	* src/gemdos.c: Fix 2 bugs in GemDOS_CreateHardDriveFileName : the
+	form "path\filename" was not recognised, and a filename < 8 chars
+	like "abc" could be chosen while looking for "ab".  These fixes now
+	allow to run the Maggie disk mags directly from the disk without
+	creating disk images.
+
+2003-03-25 08:53  Emmanuel Anne
+
+	* src/: dialog.c, screen.c, includes/screenDraw.h:
+	re-enables the "use borders" option in the configuration dialog,
+	and allow borders in fullscreen. Also, resize window/screen when
+	borders are enabled/disabled.
+
+2003-03-24 18:24  Emmanuel Anne
+
+	* src/: keymap.c, main.c, includes/keymap.h:
+	keyboard now uses scancodes instead of ascii codes.
+
+2003-03-24 18:24  Emmanuel Anne
+
+	* src/gemdos.c:
+	when you double click on a file in a mounted hd directory with tos
+	1.0, you don't receive the path, and the file was not converted
+	properly.  Also, fix chdir when the path does not exist (correctly
+	returns error code)
+
+2003-03-24 14:30  Thomas Huth
+
+	* src/configuration.c: Commented out saving/loading of number of
+	drives - ACSI HD emulation wasn't working when this was
+	saved/loaded, too
+
+2003-03-24 12:00  Emmanuel Anne
+
+	* src/: intercept.c, includes/intercept.h, uae-cpu/memory.c,
+	uae-cpu/memory.h:
+	add a hack to trick the tos to believe an ide controller is really
+	present.  It makes the boot with tos 2.06 and a mounted hd
+	directory much faster.
+
+2003-03-24 11:59  Emmanuel Anne
+
+	* src/uae-cpu/hatari-glue.c:
+	fix a possible crash if check_prefs_changed_cpu is called too early
+	(to restore parameters for example)
+
+2003-03-24 11:31  Emmanuel Anne
+
+	* src/: misc.c, ikbd.c:
+	fix year in rtc (see the comments in ikbd.c).
+
+2003-03-24 00:11  Thomas Huth
+
+	* ChangeLog: Patches for monochrome mode, RTC, GEMDOS HD emulation
+	and configuration files
+
+2003-03-24 00:08  Thomas Huth
+
+	* src/gemdos.c: Improved GEMDOS HD emulation
+
+2003-03-24 00:07  Thomas Huth
+
+	* src/: configuration.c, main.c: Re-enabled configuration file
+	saving/loading
+
+2003-03-23 22:13  Thomas Huth
+
+	* src/: Makefile, intercept.c, rtc.c, includes/intercept.h,
+	  includes/rtc.h: Added real time clock
+
+2003-03-23 20:22  Thomas Huth
+
+	* src/: misc.c, includes/misc.h: Fixed buggy BCD convertion
+	  function
+
+2003-03-23 20:20  Thomas Huth
+
+	* src/: screen.c, includes/screen.h: Fixed problems with monochrome
+	  resolution
+
+2003-03-17 14:19  Thomas Huth
+
+	* ChangeLog, src/stMemory.c, src/includes/stMemory.h: Hatari now
+	  works on Sparc machines
+
+2003-03-12 : *** Version 0.30 ***
+
+2003-03-12 18:25  Thomas Huth
+
+	* ChangeLog, readme.txt, src/includes/main.h, src/includes/tos.h,
+	  src/uae-cpu/memory.c: Version 0.30 changes
+
+2003-03-12 15:15  Thomas Huth
+
+	* src/sound.c: Added Audio_Lock around critical variables
+
+2003-03-12 15:13  Thomas Huth
+
+	* src/audio.c: Changed samples format to unsigned again
+
+2003-03-10 19:46  Thomas Huth
+
+	* ChangeLog, src/audio.c, src/sound.c, src/wavFormat.c,
+	  src/includes/audio.h, src/includes/sound.h,
+	  src/includes/wavFormat.h: Fixed ugly sound problem
+
+2003-03-09 16:39  Thomas Huth
+
+	* ChangeLog, src/ikbd.c: IKBD_Cmd_ReadClock now works
+
+2003-03-09 16:37  Thomas Huth
+
+	* src/tos.c: Fixed problem on little endian systems
+
+2003-03-08 12:29  Thomas Huth
+
+	* src/m68000.c, src/mfp.c, src/video.c, ChangeLog: Fixed problem
+	  with SR (IPL)
+
+2003-03-07 18:10  Thomas Huth
+
+	* src/: m68000.c, uae-cpu/hatari-glue.c, uae-cpu/hatari-glue.h,
+	  uae-cpu/newcpu.c: Interrupts are handled now in the UAE's way
+
+2003-03-07 18:08  Thomas Huth
+
+	* src/floppy.c: Added warning when inserting disk with Pacifist bug
+
+2003-03-06 18:41  Thomas Huth
+
+	* src/dialog.c: Added possibility to choose fullscreen resolution
+
+2003-03-04 20:28  Thomas Huth
+
+	* ChangeLog, src/ikbd.c: Fixed bug with duplicated firebutton
+
+2003-03-04 20:27  Thomas Huth
+
+	* src/: audio.c, main.c, sound.c, video.c, wavFormat.c,
+	  includes/audio.h, includes/sound.h, includes/main.h: Improved
+	  audio timer function
+
+2003-03-03 19:40  Thomas Huth
+
+	* src/uae-cpu/build68k.c, src/uae-cpu/fpp.c, src/uae-cpu/gencpu.c,
+	  src/uae-cpu/newcpu.c, src/uae-cpu/newcpu.h,
+	  src/uae-cpu/readcpu.c, src/uae-cpu/readcpu.h,
+	  src/uae-cpu/sysdeps.h, src/uae-cpu/table68k, ChangeLog: Synced
+	  CPU core with UAE 0.8.22
+
+2003-03-03 15:23  Thomas Huth
+
+	* src/tos.c: Patches for TOS 2.05
+
+2003-03-02 16:14  Thomas Huth
+
+	* src/audio.c: Now only resetting sound system when really needed
+
+2003-02-28 16:34  Thomas Huth
+
+	* ChangeLog: Improved TOS patching routine
+
+2003-02-28 16:31  Thomas Huth
+
+	* src/: gemdos.c, m68000.c, main.c, reset.c, tos.c,
+	  includes/reset.h, includes/tos.h: Improved TOS patching routine
+
+2003-02-27 11:47  Thomas Huth
+
+	* src/: cartimg.c, uae-cpu/hatari-glue.c, uae-cpu/newcpu.c: Removed
+	  0xa0ff opcode
+
+2003-02-02 23:41  Thomas Huth
+
+	* ChangeLog, src/screen.c, src/screenConvert.c,
+	  src/convert/low320x8.c, src/convert/low640x8.c,
+	  src/convert/med640x8.c, src/convert/spec640x16.c,
+	  src/includes/screenConvert.h: Rewrote some screen convertion
+	  functions in C
+
+2003-02-02 14:01  Thomas Huth
+
+	* authors.txt: Added author of blitter emulator
+
+2003-02-02 14:00  Thomas Huth
+
+	* ChangeLog, src/tos.c, src/includes/tos.h: Fixed MMU RAM size bug
+
+2003-01-30 21:51  Thomas Huth
+
+	* src/uae-cpu/newcpu.c: Enabled bus/address error PC hack for
+	  m68k_run1, too
+
+2003-01-29 00:49  Thomas Huth
+
+	* ChangeLog, src/uae-cpu/newcpu.c: Fixed bus/address error PC bug:
+	  When a bus or address error occurred, the PC was often not set to the
+	  right exception handler routine. This has been fixed now - thanks to
+	  Philippe Gerin for finding the bug and the patch for solving it!
+
+2002-12-30 18:44  Thomas Huth
+
+	* src/uae-cpu/gencpu.c: Fixed compiler warning (with GCC 3.1)
+
+2002-12-30 : *** Version 0.25 ***
+
+2002-12-30 01:54  Thomas Huth
+
+	* ChangeLog, readme.txt: Changes for version 0.25
+
+2002-12-25 22:15  Thomas Huth
+
+	* src/intercept.c: Added some more bus error regions
+
+2002-12-24 15:47  Thomas Huth
+
+	* src/: Makefile, m68000.c, includes/decode.h, includes/main.h,
+	  includes/vdi.h, uae-cpu/Makefile, uae-cpu/events.h,
+	  uae-cpu/gencpu.c, uae-cpu/hatari-glue.c, uae-cpu/hatari-glue.h,
+	  uae-cpu/maccess.h, uae-cpu/memory.c, uae-cpu/memory.h,
+	  uae-cpu/newcpu.c, uae-cpu/newcpu.h, uae-cpu/readcpu.c,
+	  uae-cpu/readcpu.h, uae-cpu/sysdeps.h: Cleaned up headers & fixed
+	  compiler warnings with -Wall
+
+2002-12-23 15:54  Thomas Huth
+
+	* src/cartimg.c, src/m68000.c, src/screen.c, src/tos.c, src/vdi.c,
+	  src/includes/vdi.h, ChangeLog: Improved VDI resolution modes
+
+2002-12-22 17:09  Thomas Huth
+
+	* src/dialog.c, src/screen.c, src/screenConvert.c, src/vdi.c,
+	  src/video.c, src/convert/vdi4.c, src/includes/screen.h,
+	  ChangeLog: Added 4 color VDI screen mode
+
+2002-12-01 00:18  Thomas Huth
+
+	* ChangeLog, src/dialog.c, src/screen.c, src/vdi.c,
+	  src/convert/vdi2.c: Improved VDI resolution modes
+
+2002-11-28 22:28  Thomas Huth
+
+	* src/: screen.c, screenConvert.c: Some patches for big endian
+	  systems
+
+2002-11-28 22:26  Thomas Huth
+
+	* src/: dialog.c, vdi.c: Added resolution choice to TOS/GEM dialog
+
+2002-10-13 16:47  Thomas Huth
+
+	* ChangeLog, src/m68000.c, src/main.c, src/screen.c,
+	  src/screenConvert.c, src/vdi.c, src/convert/vdi16.c,
+	  src/includes/dialog.h, src/includes/m68000.h,
+	  src/includes/screen.h, src/includes/vdi.h,
+	  src/uae-cpu/hatari-glue.c, src/uae-cpu/hatari-glue.h,
+	  src/uae-cpu/newcpu.c: Enabled big VDI screen resolutions in
+	  Hatari
+
+2002-10-01 23:48  Thomas Huth
+
+	* src/: floppy.c, keymap.c: Some small bugs fixed
+
+2002-10-01 23:47  Thomas Huth
+
+	* src/: timer.c, includes/timer.h: Deleted unused files
+
+2002-10-01 23:44  Thomas Huth
+
+	* src/: Makefile, debugui.c, main.c: Removed timer.c
+
+2002-09-28 16:32  Thomas Huth
+
+	* src/wavFormat.c: Patches for big endian systems
+
+2002-09-21 01:14  Thomas Huth
+
+	* src/: configuration.c, main.c, includes/dialog.h: Introduced
+	  System dialog
+
+2002-09-21 01:13  Thomas Huth
+
+	* ChangeLog, src/dialog.c, src/sound.c, src/wavFormat.c: Added
+	  YM/WAV sound recording
+
+2002-09-01 20:51  Thomas Huth
+
+	* src/: configuration.c, dialog.c, intercept.c, main.c,
+	  includes/dialog.h, includes/intercept.h: Blitter now configurable
+	  via GUI
+
+2002-08-11 23:04  Thomas Huth
+
+	* ChangeLog, src/blitter.c, src/includes/blitter.h: Fixed blitter
+	  bug
+
+2002-07-08 23:11  Thomas Huth
+
+	* ChangeLog, src/convert/spec320x16.c: Endianess patches
+
+2002-07-08 23:08  Thomas Huth
+
+	* src/: dialog.c, sdlgui.c: Check if font has been loaded
+
+2002-07-05 00:03  Thomas Huth
+
+	* ChangeLog, authors.txt, src/Makefile, src/blitter.c,
+	  src/intercept.c, src/main.c, src/includes/blitter.h,
+	  src/includes/intercept.h: Added blitter emulation
+
+2002-07-03 18:51  Thomas Huth
+
+	* ChangeLog, src/keymap.c: Patches for Macs
+
+2002-07-03 18:50  Thomas Huth
+
+	* src/: spec512.c, convert/spec320x16.c: Patch for spec512 on big
+	  endian machines
+
+2002-07-03 18:48  Thomas Huth
+
+	* src/: audio.c, joy.c, main.c: Changed init of joystick and audio
+
+2002-06-23 22:03  Thomas Huth
+
+	* src/tos.c: Added extra-check if able to patch TOS 2.06
+
+2002-04-27 16:59  Thomas Huth
+
+	* src/includes/syncTables.h: Fixed GCC warnings
+
+2002-03-21 18:28  Thomas Huth
+
+	* src/: Makefile, audio.c, configuration.c, createBlankImage.c,
+	  createDiscImage.c, debugui.c, dialog.c, errlog.c, file.c,
+	  gemdos.c, hdc.c, ikbd.c, intercept.c, keymap.c, m68000.c, main.c,
+	  memorySnapShot.c, mfp.c, printer.c, rs232.c, screen.c,
+	  screenConvert.c, shortcut.c, sound.c, tos.c, video.c,
+	  wavFormat.c, ymFormat.c, convert/low640x16.c,
+	  convert/med640x16.c, includes/decode.h, includes/fdc.h,
+	  includes/hdc.h, includes/intercept.h, includes/screenConvert.h,
+	  includes/syncTables.h, uae-cpu/hatari-glue.h: Fixed compiler
+	  warnings with -Wall
+
+2002-02-25 18:19  Thomas Huth
+
+	* readme.txt, src/screen.c, src/shortcut.c, src/includes/screen.h:
+	  Added mouse grabbing
+
+2002-02-22 16:50  Stefan Berndtsson
+
+	* src/screenConvert.c: Using the SDL endian routines instead.
+
+2002-02-21 16:04  Thomas Huth
+
+	* ChangeLog, src/m68000.c, src/sound.c, src/includes/decode.h,
+	  src/includes/m68000.h, src/includes/sound.h,
+	  src/uae-cpu/events.h: Cleaned up
+
+2002-02-21 16:03  Thomas Huth
+
+	* src/tos.c: TOS 1.00 has been wrongly patched - fixed now
+
+2002-02-21 15:06  Stefan Berndtsson
+
+	* src/screenConvert.c: Big endian fix for monochrome display. I
+	  hope it still works on little endian.
+
+2002-02-18 : *** Version 0.20 ***
+
+2002-02-18 18:07  Thomas Huth
+
+	* ChangeLog, readme.txt, src/audio.c, src/dialog.c, src/file.c,
+	  src/gemdos.c, src/main.c, src/sdlgui.c, src/includes/gemdos.h,
+	  src/includes/main.h: Version 0.20 changes
+
+2002-02-16 18:28  Thomas Huth
+
+	* gpl.txt: Fixed Y2K bug
+
+2002-02-11 18:38  Thomas Huth
+
+	* src/: configuration.c, dialog.c, main.c, includes/dialog.h: HD
+	  image now selectable in the GUI
+
+2002-02-05 20:49  Thomas Huth
+
+	* ChangeLog, src/file.c: Small bugfix for BeOS
+
+2002-02-04 22:24  Thomas Huth
+
+	* src/: Makefile, debugui.c, fdc.c, gemdos.c, hdc.c, main.c,
+	  reset.c, tos.c, includes/gemdos.h, includes/hdc.h,
+	  uae-cpu/hatari-glue.c: Added Svens HD-image patch
+
+2002-02-02 15:57  Thomas Huth
+
+	* src/: configuration.c, dialog.c, intercept.c, main.c, sdlgui.c,
+	  includes/dialog.h, uae-cpu/hatari-glue.c, uae-cpu/hatari-glue.h,
+	  uae-cpu/newcpu.c: Added CPU dialog
+
+2002-02-02 15:53  Thomas Huth
+
+	* authors.txt, readme.txt: Some minor changes
+
+2002-01-14 19:40  Thomas Huth
+
+	* ChangeLog, src/joy.c, src/main.c, src/includes/joy.h: Added real
+	  joystick support
+
+2002-01-10 09:01  Thomas Huth
+
+	* src/: Makefile, gemdos.c, includes/file.h, uae-cpu/sysdeps.h:
+	  Cleaned up/Patch for BeOS
+
+2002-01-02 18:08  Thomas Huth
+
+	* ChangeLog, src/dialog.c, src/m68000.c, src/main.c,
+	  src/shortcut.c, src/includes/m68000.h, src/includes/main.h,
+	  src/uae-cpu/events.h, src/uae-cpu/hatari-glue.c,
+	  src/uae-cpu/memory.c, src/uae-cpu/memory.h, src/uae-cpu/newcpu.c:
+	  Fixed some ST reset problems
+
+2002-01-01 18:44  Thomas Huth
+
+	* src/: audio.c, dialog.c, main.c, sdlgui.c, shortcut.c, sound.c,
+	  includes/audio.h, includes/dialog.h, includes/main.h: Updated the
+	  dialogs
+
+2001-12-27 14:13  Thomas Huth
+
+	* ChangeLog, src/dialog.c, src/main.c, src/sdlgui.c,
+	  src/shortcut.c, src/uae-cpu/newcpu.c, src/uae-cpu/newcpu.h: First
+	  working version of the GUI.
+
+2001-12-26 19:24  Thomas Huth
+
+	* src/: configuration.c, dialog.c, file.c, sdlgui.c,
+	  includes/file.h, includes/sdlgui.h: Better gui, selecting discs
+	  now works.
+
+2001-12-25 17:24  Thomas Huth
+
+	* src/file.c: Splitpath, makepath, scandir and alphasort added
+	  here.
+
+2001-12-25 17:21  Thomas Huth
+
+	* src/: dialog.c, sdlgui.c, includes/sdlgui.h: Added some more
+	  dialogs.
+
+2001-12-25 17:19  Thomas Huth
+
+	* ChangeLog, src/floppy.c, src/gemdos.c, src/main.c, src/misc.c,
+	  src/ymFormat.c, src/includes/file.h, src/includes/main.h,
+	  src/includes/misc.h: Cleaned up some files
+
+2001-12-23 14:29  Thomas Huth
+
+	* src/: ikbd.c, main.c, includes/ikbd.h: Better relative mouse
+	  support.
+
+2001-12-21 19:27  Thomas Huth
+
+	* src/: statusBar.c, view.c, includes/statusBar.h, includes/view.h:
+	  Cleaned up and removed view.c and statusbar.c
+
+2001-12-21 19:25  Thomas Huth
+
+	* ChangeLog, src/Makefile, src/audio.c, src/configuration.c,
+	  src/dialog.c, src/floppy.c, src/gemdos.c, src/ikbd.c,
+	  src/keymap.c, src/m68000.c, src/main.c, src/memorySnapShot.c,
+	  src/mfp.c, src/printer.c, src/rs232.c, src/screen.c,
+	  src/screenSnapShot.c, src/shortcut.c, src/video.c,
+	  src/wavFormat.c, src/ymFormat.c, src/convert/high640x8.c,
+	  src/includes/ikbd.h, src/includes/keymap.h: Relative SDL mouse
+	  mode added, view.c and statusbar.c removed.
+
+2001-12-16 21:27  Thomas Huth
+
+	* src/: dialog.c, sdlgui.c: Designed some dialogs.
+
+2001-12-10 22:43  Thomas Huth
+
+	* src/includes/dialog.h: Cleaned up file.
+
+2001-12-10 22:41  Thomas Huth
+
+	* src/: .cvsignore, errlog.txt: errlog.txt removed.
+
+2001-12-10 22:40  Thomas Huth
+
+	* src/audio.c: Check for right sound init.
+
+2001-12-10 22:38  Thomas Huth
+
+	* src/font8.bmp, ChangeLog, src/.cvsignore, src/Makefile,
+	  src/configuration.c, src/dialog.c, src/main.c, src/sdlgui.c,
+	  src/shortcut.c, src/includes/sdlgui.h: First version of the GUI.
+
+2001-12-09 13:16  Thomas Huth
+
+	* src/: Makefile, audio.c, configuration.c, dialog.c, floppy.c,
+	  main.c, includes/dialog.h: Cleaned up some files.
+
+2001-11-02 22:45  Thomas Huth
+
+	* src/tos.c: Made TOS loading more flexible.
+
+2001-10-24 21:27  Thomas Huth
+
+	* src/gemdos.c: scandir and alphasort for BeOS.
+
+2001-10-12 19:23  Thomas Huth
+
+	* src/debugui.c: Update to newest version of the debugger.
+
+2001-10-11 18:29  Thomas Huth
+
+	* src/screenSnapShot.c: Fixed bug that only allowed 8 snapshots.
+
+2001-10-10 : *** Version 0.11 ***
+
+2001-10-10 20:43  Thomas Huth
+
+	* src/uae-cpu/.cvsignore: cvsignore for generated files.
+
+2001-10-10 20:41  Thomas Huth
+
+	* ChangeLog, readme.txt, src/gemdos.c, src/includes/main.h: Version
+	  0.11 changes
+
+2001-10-09 19:32  Thomas Huth
+
+	* src/: Makefile, createBlankImage.c, debug.c, errlog.c, fdc.c,
+	  floppy.c, ikbd.c, int.c, keymap.c, m68000.c, memAlloc.c, mfp.c,
+	  misc.c, msa.c, printer.c, psg.c, reset.c, spec512.c, st.c,
+	  timer.c, vdi.c, xbios.c, ymFormat.c, convert/high640x8.c,
+	  includes/m68000.h: Changed a lot of C++ comments into C comments
+	  (for plain ANSI-C compilers).
+
+2001-10-09 19:29  Thomas Huth
+
+	* src/: disass.c, includes/disass.h: no longer needed.
+
+2001-09-28 20:30  Thomas Huth
+
+	* src/: screen.c, screenConvert.c, convert/high640x8.c: Enhanced
+	  the monochrome mode.
+
+2001-09-24 19:32  Thomas Huth
+
+	* src/: main.c, uae-cpu/hatari-glue.c, uae-cpu/newcpu.c: Added
+	  compatible 68000 CPU mode.
+
+2001-09-24 14:21  Thomas Huth
+
+	* src/: screen.c, uae-cpu/hatari-glue.c: Some code cleaned up.
+
+2001-09-20 18:54  Thomas Huth
+
+	* ChangeLog, src/intercept.c, src/main.c, src/screen.c,
+	  src/screenConvert.c, src/convert/low320x16.c,
+	  src/convert/low640x16.c, src/convert/med640x16.c,
+	  src/convert/spec320x16.c, src/includes/screenConvert.h: Added
+	  screen flipping and mixed mode resolution.
+
+2001-09-18 19:18  Thomas Huth
+
+	* authors.txt, src/configuration.c, src/file.c, src/main.c,
+	  src/screenConvert.c, src/stMemory.c, src/tos.c, src/view.c,
+	  src/includes/file.h, src/uae-cpu/m68k.h_i86,
+	  src/uae-cpu/maccess-i86.h: Added BeOS patches, new options and
+	  cleaned up some files.
+
+2001-09-16 17:05  Thomas Huth
+
+	* src/ikbd.c: Enabled second test for bInitGemDOS, too.
+
+2001-09-09 16:03  Sven de Marothy
+
+	* src/main.c: Added HD emulation options
+
+2001-09-09 16:02  Sven de Marothy
+
+	* ChangeLog: Add HD emulation changes
+
+2001-09-09 16:01  Sven de Marothy
+
+	* src/uae-cpu/newcpu.c: Fixd gemdos_opcode & runoldgemdos_opcode
+	  for HD emulation
+
+2001-09-09 16:00  Sven de Marothy
+
+	* src/uae-cpu/hatari-glue.h: Fixed HD emulation
+
+2001-09-09 16:00  Sven de Marothy
+
+	* src/uae-cpu/hatari-glue.c: Gemdos_opcode & oldgemdos_opcode
+	  implemented for HD emulation
+
+2001-09-09 15:58  Sven de Marothy
+
+	* src/ikbd.c: Fixed annoying key clicks - bInitGemDos is now set
+
+2001-09-09 15:57  Sven de Marothy
+
+	* src/: cart.c, cartimg.c, gemdos.c, includes/cart.h,
+	  includes/gemdos.h: Fixed HD emulation
+
+2001-09-09 14:03  Thomas Huth
+
+	* src/: screen.c, screenSnapShot.c, includes/screen.h,
+	  includes/screenSnapShot.h: Enabled screen snapshots in
+	  fullscreen, too.
+
+2001-09-07 21:32  Thomas Huth
+
+	* src/includes/m68000.h: Removed M68000_FindLastInstructionCycles.
+
+2001-09-07 21:29  Thomas Huth
+
+	* src/includes/ikbd.h: Increased KeyStates array.
+
+2001-08-16 : *** Version 0.10a ***
+
+2001-08-16 19:19  Thomas Huth
+
+	* ChangeLog, readme.txt, src/Makefile, src/ikbd.c, src/shortcut.c,
+	  src/view.c, src/includes/main.h: Version 0.10 changes.
+
+2001-08-16 19:16  Thomas Huth
+
+	* src/: m68000.c, video.c, uae-cpu/events.h, uae-cpu/gencpu.c,
+	  uae-cpu/newcpu.c, uae-cpu/newcpu.h: Improved CPU cycles
+	  emulation.
+
+2001-08-15 21:25  Thomas Huth
+
+	* src/: screenConvert.c, spec512.c, convert/high640x1.c,
+	  convert/spec320x16.c, includes/spec512.h: Added Spec512 support.
+
+2001-08-06 20:10  Thomas Huth
+
+	* src/: debugui.c, shortcut.c: Added Svens debugger update.
+
+2001-08-06 18:05  Thomas Huth
+
+	* src/ikbd.c: Set IKBD_RESET_CYCLES back to 400000
+
+2001-07-22 13:35  Thomas Huth
+
+	* src/: ikbd.c, intercept.c, m68000.c, tos.c: Fixed some bugs.
+
+2001-07-21 19:47  Thomas Huth
+
+	* src/uae-cpu/: events.h, gencpu.c, hatari-glue.c, hatari-glue.h,
+	  newcpu.c, newcpu.h, sysdeps.h: Improved cpu cycles a little bit.
+
+2001-07-21 19:40  Thomas Huth
+
+	* ChangeLog, readme.txt, src/configuration.c, src/m68000.c,
+	  src/main.c, src/screen.c, src/shortcut.c, src/view.c,
+	  src/includes/decode.h, src/includes/screen.h: Added shortcuts and
+	  better fullscreen.
+
+2001-07-11 22:54  Thomas Huth
+
+	* authors.txt: Added Sven.
+
+2001-07-11 22:51  Thomas Huth
+
+	* ChangeLog, src/screen.c, src/screenConvert.c,
+	  src/convert/low320x16.c, src/convert/med640x16.c: Added ST medium
+	  resolution emulation.
+
+2001-07-10 22:56  Thomas Huth
+
+	* ChangeLog, src/Makefile, src/debugui.c, src/ikbd.c, src/main.c,
+	  src/screen.c, src/screenConvert.c, src/shortcut.c, src/video.c,
+	  src/view.c, src/convert/low320x16.c, src/convert/med640x16.c,
+	  src/includes/debugui.h, src/includes/main.h: Cleaned up some
+	  files and added Svens debugger patch.
+
+2001-06-26 21:07  Thomas Huth
+
+	* src/: Makefile, main.c, pcx.c, screen.c, screenSnapShot.c,
+	  shortcut.c, view.c, includes/pcx.h, includes/shortcut.h: Added
+	  Svens screenshot patch.
+
+2001-06-12 21:22  Thomas Huth
+
+	* src/: audio.c, screen.c, video.c, includes/screen.h,
+	  includes/video.h: Fixed sound sync problems.
+
+2001-06-10 16:15  Thomas Huth
+
+	* ChangeLog, readme.txt, src/audio.c, src/configuration.c,
+	  src/main.c, src/screen.c, src/shortcut.c, src/sound.c,
+	  src/video.c, src/includes/audio.h, src/includes/configuration.h,
+	  src/includes/main.h, src/includes/sound.h: Added sound support.
+
+
+2001-06-01 : *** Version 0.05a ***
+	* Created CVS Repository at SourceForge.net
+	* Added joystick emulation.
+	* Added Stefan's patch for ST-LOW res on big-endian machines,
+	  his patch for also leaving Hatari by pressing F12, and
+	  his fullscreen patch.
+	* Changed all tabulator characters in the source to spaces.
+
+2001-05-27 : *** Version 0.04a ***
+	* Added Stefan Berndtsson's patch for big-endian machines.
+	  Hatari now runs also with non-x86 Linux machines! Thanks Stefan!
+	* Rewrote the ST-LOW resolution conversion routines in C
+	  => ST-LOW now works!
+	* Added some of the WinSTon patches Paul Bates recently published
+	  at the WinSTon BBS (Thanks to Ladislav Adamec for the hint).
+	* Cleaned up the source tree a little bit.
+
+2001-04-03 : *** Version 0.03a ***
+	* Rewrote some more assembler functions. FDC emulation now works!
+
+2001-04-02  T. Huth
+	* SDL Keyboard code finished and included a SDL-Key -> ST-Scancode table.
+
+2001-03-29  T. Huth
+	* Added mouse support.
+
+2001-03-28 : *** Version 0.02a ***
+	* Added very simple SDL support.
+	* Rewrote a lot of assembler functions in C (e.g. intercept.c).
+	* Adapted the UAE CPU. Now Hatari is able to boot a TOS 1.0x ROM, the
+	  Desktop shows up, but no mouse and keyboard interaction yet.
+
+2001-03-21 : *** Version 0.01a ***
+	* Made the WinSTon source code compilable.
+	* Added the UAE CPU sources.
diff --git a/doc/coding.txt b/doc/coding.txt
new file mode 100644
index 0000000..3710b1f
--- /dev/null
+++ b/doc/coding.txt
@@ -0,0 +1,37 @@
+
+	Hatari coding guidelines
+	========================
+
+Before writing new code or changing existing files, please read through these
+coding guidelines to make sure that your changes are in harmony with the
+existing source code.
+
+- all source text files have to use Unix Line ending convention (line-feed only)
+  (exception: Code like cart_asm.s which has to be compiled from the Atari TOS
+  side should have DOS line endings (CR-LF) instead).
+
+- Avoid non-ASCII characters in source code. Use UTF-8 encoding for non-english
+  documentation files if necessary.
+
+- Use TABs for indentation at the beginning of a line. Default TAB width is 8,
+  but your source code should also look fine with other TAB width (e.g. 4).
+
+- Use doxygen-style comments to document what each function is doing.
+
+- No "magic" variable values.  Use either defines or enums to name the
+  values and document what they mean if it's not obvious.
+
+- Hatari uses code from many projects, e.g. the UAE CPU files, which
+  use another coding style than the main source code. We keep the
+  original coding style there for compatibility with the origin. So
+  always try to adapt to the coding style of the file that you're
+  currently editing.
+
+- For new files, pick one of the existing coding styles, don't add a new one.
+
+- Try to avoid including a header file from within another header file.
+  Include all necessary header files in the right order in the *.c files
+  instead. Including a header file from within another header file easily leads
+  to a dependency hell which can become very painful when one of the header
+  files clashes with a system header for example and must only be included
+  in certain .c files only.
diff --git a/doc/compatibility.html b/doc/compatibility.html
new file mode 100644
index 0000000..bc972c5
--- /dev/null
+++ b/doc/compatibility.html
@@ -0,0 +1,3983 @@
+
+
+
+  Hatari Atari Software Compatibility List
+  
+  
+  
+  
+  
+  
+
+
+
+
+
Hatari Atari Software Compatibility List

+
+

+Version 1.9, September 2015
+

+

+This list has been written by: Thomas Huth, Eero Tamminen
+ & Nicolas Pomarède
+

+

+Hatari on the WWW:
+
+http://hatari.tuxfamily.org/
+
+

+
+
Index

+
+

+
+

+
+
+
Introduction

+
+
Here are lists of Atari software that have been tested with
+different Hatari versions and configurations.

+
+
First is listed software (games, demos and applications) for normal
+STs, after them is listed STE software.  Then there are a few TT-only
+games and demos, and finally a list of somewhat working Falcon games,
+demos and applications.

+
+
Technical details and any known issues in the software are described
+in the "Notes" column of the lists.  Software having issues has different
+"Hatari version" column background color; orange
+for minor and red for major issues.  The first
+known/tested Hatari version with which a program worked (perfectly)
+or with which it was last tested still to have issues, is given in
+the version field.

+
+
+
Reporting compatibility issues

+
+
If something that works on the real hardware doesn't work properly
+in Hatari (or something has started working in latest Hatari version)
+and this information is missing from these lists, please mail
+hatari-devel mailing list so that we can update the list.

+
+
Before reporting something not working as expected, please
+check few things:
+
    
+
+
  • That you have enabled the "Slower but more compatible CPU"
+Hatari system option and that the machine type (ST/STe/TT/Falcon)
+is correct.
    • 
+
+
  • Amount of memory. Some games and demos may not work if you have
+specified too little or too much memory.  For ST, 1MB memory size
+is usually fairly safe.
    • 
+
+
  • Some games/demos can refuse to run when GEMDOS HD emulation is
+enabled (due to presence of Hatari cartridge image needed for that).
+In STF/STE mode, it's also better to disable the MegaST's real time
+clock.
+
    • 
+
+
  • TOS version: ST demos and games may require a specific TOS
+version and fail to work with all other versions. If you notice that
+this information is missing for some listed game or demo, please send
+mail to the hatari-devel mailing list.
+
      
+
    • Note that many games and demos (especially floppy based ones),
+don't work with the free EmuTOS TOS. For more information, see
+emutos.txt.
      • 
+
    
+
    • 
+
+

+
+

+Also note that since Hatari 1.8, support is included also for STX, IPF and CTR
+floppy image formats. They allow storing disk contents in an unaltered form,
+without requiring a crack to remove the copy-protection. Some complex
+protections rely on precise CPU/FDC timings provided with these
+formats, and a specific TOS version.

+
    
+
  • For STF protected games, it is recommended to use TOS 1.02 or 1.04 and
+1MB RAM, as well as turning HD emulation OFF for maximum compatibility
+(but most games will run fine with different settings).
    • 
+

+
+

+(More
+information on games compatibility on Atari forum.)
+

+
+
+
ST software compatibility list

+
+
These aren't comprehensive lists. The lists concentrate
+mainly on software that has (historically had) problems working in
+Hatari or provide good regression test-cases for some specific
+technical emulation issues, but some well known other programs
+are also listed.

+
+
By default everything that works on a real ST should work also in Hatari.
+
+
ST games

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+
Tested ST games
GameHatari versionNotes
4 Wheel Drive compilation1.8Requires TOS 1.04
A320 Airbus1.8Does not work with cartridge / HD emulation
Alien Worldbefore 1.0 
Antago1.8Write protection should be OFF
Arkanoid1.8Requires TOS 1.02 for mouse input
Armalytebefore 1.0 
Baal1.8Does not work with cartridge / HD emulation
Bio Challenge1.8Does not work with cartridge / HD emulation
Blood Money - Superior 651.9The file version of this game has some serious bugs and will crash with TOS 1.04 or 1.62, and maybe
+	  in other conditions too. Avoid it, use another version of this game
Bolo1.7This game works in medium resolution and in monochrome
Bubble Bobblebefore 1.0 
Captain Blood1.7Uses the IKBD set-clock command to set a custom time for game-internal
+          time measurement
Defenders Of The Earthbefore 1.0 
Dragon Ninja1.8Requires TOS ≤ 1.04. Does not work with cartridge / HD emulation
Eco1.8Write protection should be OFF
Eliminatorbefore 1.0 
Exterminator1.2The "Patch Timer-D" option must be disabled to avoid color
+          raster problems
Enchanted Land1.3This game uses heavily sync-scrolling techniques!
F15 Strike Eagle 21.3 
F29 Retaliator1.6Under some badly cracked versions (Pompey Pirate 38), joystick doesn't work
Fire And Forget II1.8Requires UK or US TOS
Fuzion CD 1611.6Menu's intro is buggy, top border is not correctly removed even on a real STF, due to timer C
+	  not correctly initialized to play digidrums. Use STE mode instead.
Garfield Winter's Tail1.8Requires TOS ≤ 1.04 and ≤ 1MB RAM. Does not work with cartridge / HD emulation
Grimblood1.8Requires TOS ≤ 1.02
Hover Sprint1.8Write protection should be OFF
Jaguar XJ220 (development demo)1.2Only loads correctly when "Fast floppy" option is disabled
Knightmare1.8Does not work with cartridge / HD emulation
Leisure Suit Larry 2before 1.0Everything works, even Roland-MT32 MIDI music
Leanderbefore 1.0 
Lethal Xcess Beta1.8The STX version requires Hatari ≥ 1.8 to handle the protection
Lethal Xcess1.0Uses sync-scrolling in ST mode and STE HW scrolling in STE mode.
Microprose Golf1.7Requires Hatari ≥ 1.7 to avoid a crash during the game's intro
Metal Mutant1.0 
Monster Business1.8Does not work with cartridge / HD emulation
Mr. Heli1.8Does not work with cartridge / HD emulation
Navy Sealsbefore 1.0 
Nebulus1.1Disappearing platform tiles sound dodgy
No Buddies Land1.3Uses "0-byte" vertical sync-scrolling
Oids1.8Write protection should be OFF
Pirates!before 1.0Game also supports MIDI music
Populous US version of the game requires US TOS to work
Populous1.8Requires TOS ≤ 1.04. Does not work with cartridge / HD emulation
Prehistoric Tale1.8Does not work with cartridge / HD emulation
R.B.I. Baseball 21.6On STE, the game will play sounds with the DMA audio, but with
+	a different freq than the STF mode (6258 vs 7675 Hz). On STF, the sound
+	fx don't sound correct because of that, but that's not an emulation bug
Rick Dangerousbefore 1.0 
Robocop II1.1 
Running Man1.6When running on Hatari versions before 1.6, the RS232 emulation must
+          be enabled for the game to work (since it writes some debug
+          informations to the serial port)
Seven Gates Of Jambala1.3Uses a very rare mode for timer B to count start of line. Disable the
+        "Patch Timer-D" option to avoid color raster problems.
Skweekbefore 1.0Does not work with cartridge / HD emulation
Slayer1.3Uses color raster FX at highscore and main screen
Speedballbefore 1.0 
Spherical1.8Requires ≤ 1MB RAM
Spidertronic1.7Crashed before the 50/60 Hz selection screen with Hatari < 1.7
Star Goose1.1 
Subbuteo1.7 
Super Hang-On1.7Requires Hatari ≥ 1.7 to avoid flickering rasters
Super Monaco GP1.7Requires Hatari ≥ 1.6 for correct FDC emulation
+	  and Hatari ≥ 1.7 to avoid flickering rasters
Super Sprint1.3The "Patch Timer-D" must be disabled or the music will
+          play too fast
Super Skweek1.3Disable the "Fast floppy" option if your version
+          fails to load
The Deep1.1When running on Hatari versions before 1.6, the RS232 emulation must
+          be enabled for the game to work (since it writes some debug
+          informations to the serial port)
The Final Conflict1.7Buggy samples replay during the intro, requires Hatari ≥ 1.7
The Sentinel1.7Mouse moved too slowly before Hatari 1.7
The Teller1.9Does not work with cartridge / HD emulation
The Ultimate Ride The game has a bug and will crash if drive B is empty. Either disable drive B or insert
+	  disk 2 in drive B to make it work
To Be On Top1.8Does not work with cartridge / HD emulation. Although it works on real ST with 512 kB of RAM,
+	  current emulation requires to use ≥ 1MB RAM
Tokibefore 1.0 
Total Eclipse1.8Does not work with cartridge / HD emulation
Treasure Trap1.8When running on Hatari versions before 1.6, the RS232 emulation must
+          be enabled for the game to work (since it writes some debug
+          informations to the serial port)
Warlock's Quest1.7The game has some IKBD bugs, it doesn't work with TOS 1.04, but works
+	  fine with TOS 1.02 or 1.62. The keyboard mode is also less responsive
+	  than the joystick mode, but that's the same on a real ST
Wings Of Death1.0works in STE mode too
Xenon1.1 
Xenon 2 - Megablastbefore 1.0 
Yolanda1.6This game expects random data from the TOS memory test in low RAM,
+          so the emulator has to be started with "fast boot" disabled
+          or the game will freeze after a few seconds
Zombi1.6.2Uses the IKBD set-clock command to set a custom time for game-internal
+          time measurement

+
+
ST demos

+
+
Some (very) rare demos try to install IKBD code.  Hatari doesn't have
+full 6301 emulator, but has specific code to handle these particular demos.
+They are marked with '*'.  Few remaining screen sync issues are related to
+hi/lo frequency switching or switching to 60 Hz for too long (used
+for border removal).

+
+
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+  
+
Tested ST demos
DemoHatari versionNotes
1984:
+      No Cooper1.0Many very good plasma effects, mid res overscan, ... The loader's protection
+        requires exact cpu/shifter sync, as well as cpu pairing
ACF:
+      Just Buggin'1.6Requires at least Hatari 1.6 for correct FDC emulation
Acid Team:
+      Dragonnels*1.1
+        Uses its own IKBD 6301 routine. The "Unlimited Bobs"
+        screen is very sensitive to proper IKBD timings.
+      
Aggression:
+      Overdosebefore 1.0Does not work with cartridge / HD emulation
Big Alec:
+      Audio Artistic Demo1.7 
BushWacKers:
+      Transbeauce II*1.1Uses its own IKBD 6301 routine. Does not work with HD emulation.
Chaos:
+      Pandemonium1.5The Mega-3D screen exits prematuraly (crash due to a cpu timing problem ?)
Checkpoint:
+      Poshbefore 1.0 
Checkpoint:
+      Suretrip 49%1.9Crashes in fullscreen screen.  Worked with Hatari v1.6.2.
+      Depends on very complex VBL/HBL timing when both instructions
+      happens at the same time on line 0
Delta Force:
+      Punish Your Machine1.5Sync-scroll, overscan... ST Connexion's screen features 4 pixels hardware scrolling on STF.
+          "Best Part Of The Creation" uses spec512 mode in med res
Delta Force:
+      Syntax Terror1.3Planes are shifted in TCB screen (missing stabilizer). Tex screen works since 1.3
+          (mixes 50/60 HZ lines)
DHS:
+      Sweetybefore 1.0Does not work with HD emulation
Diamond Design:
+      Brace1.5Use spec512 mode in med res in the mixed low/med res horizontal scrolltext
Dune:
+      Illusion1.0Very nice demo. Some rasters are sometimes flickering, this is a bug
+	in the demo, not in Hatari. Using --fastfdc can cause problems
+	with some parts of this demo
Dune/Sector One:
+      Fantasiabefore 1.0 
Dune/Sector One:
+      Odd Stuffbefore 1.0In STF mode, some screens tries to simulate more colors by changing the
+          palette on each VBL, which creates an unpleasant flickering effect
+          (this is not a bug in Hatari). Use STE mode for better results
Equinox:
+      Virtual Escapebefore 1.0 
Equinox:
+      Vodka Demo1.6.1The 'Kill The Beast 2' part requires Hatari 1.6.1 to work
Fraggle's:
+      Bird Mad Girl Show1.5 
Futur Minds:
+      Snork1.5DNT screen 1 is mixing low/med res on the same line, which is not supported
+	  by Hatari at the moment
Inner Circle:
+      Decade Demo1.7Very good demo. Reset part requires Hatari ≥ 1.7 to avoid flickering
+	  bottom border
Lynx:
+      BBS Intro 31.5Good 3D (voluntarily uses some address errors in the 3D routines)
M.C.S:
+      Delirious Demos IV1.6Requires at least Hatari 1.6 for correct FDC emulation and for
+	some of the overscan screens. Some screens are not working or not
+	correctly emulated yet (Vodka, Fulltrax, Tekila, La Miga Demo)
MJJ Prod:
+      Anomaly1.7Requires Hatari ≥ 1.7 to avoid glitches in the main menu
+	  when playing digidrums
Next:
+      Phaleon Giga Demo1.04 disks.  Some overscan screens have small sync issues
+          (in Future Minds screen, planes are shifted in the lower part)
Offbeat:
+      The Musical Wonders 19901.7This demo requires STE mode. With STF mode, bottom border is not correctly
+	  removed (this is the same on a real STF)
Omega:
+      Omega1.3In full overscan screen, planes are shifted due to missing hi/lo stabilizer
Omega:
+      RGB Plasma1.5Boot sector doesn't match the physical disk layout, which caused bus error in Hatari < 1.5
Overlanders:
+      European Demos1.1Does not work with cartridge / HD emulation
Overlanders:
+      Gen4 Demo1.5Does not work with cartridge / HD emulation. Uses illegal/address error
+	exceptions to decode the program
Overlanders:
+      Ventura1.1In Ultimate Dist screen planes are shifted in the upper logo
Oxygene:
+      Flip-o-demobefore 1.0 
Oxygene:
+      ST-NICCC 2000 Demo1.7Due to a bug in the FDC's emulation, the demo ran slower than expected
+	with Hatari < 1.7
Paulo Simoes (ljkb):
+      The Overscan Demos1.0All demos are running in overscan, including some spectrum 512 pictures.
Paulo Simoes (ljkb):
+      shforstv1.3Small technical demo posted on www.atari-forum.com.
+          It features the most advanced hardscroll on STF, using only 4 raster lines
+          and all possible borders's removal (including 162 bytes 50 Hz line).
Phalanx:
+      Overdrive1.1In Dragon screen planes are shifted in the upper part
PHF:
+      UMD 87301.8The Ultimate Music Disc for Atari. This demo doesn't work in STF mode
+	  with Hatari < 1.8, due to the non standard fading colors routine
+	  used at the start of the demo
Reservoir Gods:
+      Hallucinationsbefore 1.0 
Sector One:
+      Oh no!! More Froggies1.0Works only with <4MB of RAM.  It doesn't support SID sound with timers
+          during the overscan parts, so it stops music (it's not a bug).
ST Connexion/Overlanders/Legacy:
+      Froggies over the Fence*1.1Uses its own IKBD 6301 routine
The CareBears:
+      SoWatt1.0Sync-scroll, overscan...
The CareBears:
+      Swedish New Year1.3Fullscreen in the first TCB screen is mixing 50/60 HZ lines
The Exceptions:
+      B.I.G. Demo1.0 
The Lost Boys:
+      Mindbomb1.3"DI No Shit" is mixing 50/60 Hz lines.
+          Does not work with cartridge / HD emulation
The Marvellous V8:
+      V8 Music System1.1The keyboard detection at the beginning is buggy and it's sometimes
+	necessary to retry several times (this is the same on a real STF)
+      
The Syndicate:
+      If Pigs Could Flybefore 1.0 
The Union:
+      The Union Demo1.8One of the most famous ST demos. Does not work with cartridge / HD emulation. Although it works on real ST with 512 kB of RAM,
+	  current emulation requires to use ≥ 1MB RAM
TNT Crew:
+      Death of the left border1.1Planes are shifted
TOS Crew:
+      4-pixel plasma screen1.8This demo features some 4 pixels color changes on STF, instead of the usual
+	8 pixels minimum width
Unlimited Matricks:
+      Dark Side Of The Spoon1.0Lots of fullscreens and sync-scrolling
X-Troll:
+      Long Screenbefore 1.0 
Ym Rockerz:
+      Popstarsbefore 1.0 

+
+
ST applications

+
+
Note that some applications can even crash at startup if their
+configuration or data files are not writable.

+
+
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+      
+      
+      
+    
+  
+
Tested applications
ApplicationHatari versionNotes
Programming
AHCC1.3Open Source Pure-C compatible C-compiler and IDE
Pure-C1.4Debugger had issues with GEMDOS HD emulation before Hatari v1.4
Devpac 2.21.2 
Devpac 31.7Earlier GEMDOS HD emu flushed writes only when file was
+          closed or its metadata was changed.  Before Hatari v1.7
+	  tools run by Devpac could get incomplete file contents
Turbo Assemblerbefore 1.0
+        Due to a bug you need to have a proper disk image inserted into drive A.
+      
GFABASIC 3.6TTbefore 1.0MENU.PRG does not like harddisks. Use disk images for compiling.
ST Basicbefore 1.0 
Gulam shellbefore 1.0 
Orcs Resource editorbefore 1.0 
Graphics
Crackartbefore 1.0
+        Harddisk access does not work with GEMDOS emulation
+         - fine with disk images
+      
ImConbefore 1.0 
Mgif1.4Convolutions can use Falcon DSP and JPEG loading Brainstorm
+          DSP decoder
Neochrome1.3 
OCRbefore 1.0Didn't try scanning
Spectrum 5121.7Mouse moved too slowly before Hatari 1.7
Speed Of Lightbefore 1.0 
Sound
Hextracker1.5Uses non-standard mouse event scaling factor.
+          Mouse cannot traverse whole Hatari window unless
+          mouse grab or fullscreen mode is used
M1.9MIDI program, use a weird way to trigger interrupt by changing MFP's AER
MusicMon 2before 1.0 
Noise Tracker1.1 
Notator1.9MIDI program, very sensitive to the timings when writing to the MIDI's ACIA
Protrackerbefore 1.0 
Quartetbefore 1.0 
Realtime1.9MIDI program, use a weird way to trigger interrupt by changing MFP's AER
SidSound Designerbefore 1.0 
Accompanist
(Henry Cosh Sequencer)		1.2MIDI input/output works
Cubase Lite1.2MIDI input/output works
Sequencer One1.2Both MIDI input/output
+          and sampled sound work
Text Editors
Tempusbefore 1.0 
Qed editorbefore 1.0 
Everest editorbefore 1.0 
Business applications
Opus spreadsheetbefore 1.0 
SBase databasebefore 1.0 
Sheet spreadsheetbefore 1.0 
Calamus v1.0.9before 1.0 
Outline Art 3 (demo)before 1.0 
Communications
CAB browserbefore 1.0 
Connectbefore 1.0 
Kivi QWK Readerbefore 1.0 
Desktops
Teradesk desktopbefore 1.0 
Thing desktopbefore 1.0 
Science
Eulerbefore 1.0 
Minidraftbefore 1.0 
Molsysbefore 1.0 
Benchmarks/statistics
Kronosbefore 1.6Disk speed check is really slow under GEMDOS HD emulation, use disk images instead
Statistician1.8Program crashes if disk info is requested for GEMDOS HD
+      emulated drive, or a floppy drive without a disk, because
+      program doesn't check BIOS GetBPB() function return value
Utilities
Revenge Document Displayerbefore 1.0 
ST-Guidebefore 1.0 
ST-Zipbefore 1.0 
STCatbefore 1.0 
Lharc Shellbefore 1.0 
TwoInOnebefore 1.0 
Sagrotan viruskillerbefore 1.0 
Others
ZX Spectrum emulatorbefore 1.0Installer needs to be run from a floppy image and (HD)
+      install directory needs to be already present. After installing,
+      use unzip to get zero byte sized files from the original
+      self-extracting zip files.  Both 68000 and 68030 versions work
+      both in color and mono.

+
+
Midi setup

+
+
If you don't have a MIDI sequencer, on Linux you can use
+a softsynth like Timidity or FluidSynth instead (if your distribution
+supports ALSA). For instructions, see the
+midi-linux.txt file.

+
+
+
STE software compatibility list

+
+
By default everything should work with the STE emulation.  The lists
+below contain nearly all the STE specific software that the developers
+could get their hands on...

+
+
+
STE games

+
+
First are some STE games that do work with the STE features
+in Hatari.  Most of these games work only on STE, but here are also some
+games which work (or have a version that works) also on ST, i.e. they
+are just STE enhanced.  These are marked with '*'.

+
+
+  
+  
+    
+      
+      
+      
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+  
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+    
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+    
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+    
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+    
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+    
+    
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+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
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+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+  
+
Tested STE games
TitleHatari versionNotes
4K Pacman1.4 
Aerial Combat 31.4 
Alien Blastbefore 1.0 
Alien Thing1.2"Director's cut" preview. Needs to be run from atdcdemo/-folder in root
AttackWave*1.3Uses blitter and DMA sound on STE
Astrodia*before 1.0Blitter
Battletris+before 1.0 
Blat!before 1.0 
Bombamanbefore 1.0 
Breakdancebefore 1.0THE ultimate scene game
Chronicles of Omega*before 1.0 
Chaos Engine (demo)before 1.0 
ChuChu Rocket*before 1.0needs to be run from disk image
Dynabusters+1.1Hi-score screen flickers
Frantick1.0 
H.E.R.O. 2before 1.0Requires 4MB RAM
Giana Sisters STE rewritebefore 1.6.2 
Leavin' Teramis* Loader text was not correctly displayed with Hatari < 1.8
Manga Puzzlebefore 1.0 
No Limit IIbefore 1.0 
Obsession (demo)before 1.0Opens top, left (with STE shifter bug) and bottom borders
Operation Garfieldbefore 1.0 
Pacman on Ebefore 1.0 
Pacmania STE rewrite1.6.2 
Penta*before 1.0Blitter, DMA audio and STE fadings do work properly
Pooz*before 1.0Uses STE DMA, blitter and palette
Power Up*1.5Very weird sound routine in STE mode : play a 2 bytes sample in a loop with
+	  DMA sound and update the content of this sample with an MFP timer
R0X1.3Some "DMA snd: Illegal buffer size (from 0x0 to 0x0)" messages
Roger1.1Needs to be run from a disk image
Skullsbefore 1.0Opens right border
Starball*before 1.0Uses DMA sound
Stardust (tunnel demo)before 1.0 
STrEet Fighter 2before 1.0Uses blitter, HW scrolling and DMA sound
Stupid Balloon gamebefore 1.0 
Substation (demo)before 1.0 
Team1.0HW scrolling, DMA sound, overscan
TomTarbefore 1.0 
Utopos1.4Screen was flickering with previous version of Hatari
Ultimate Arenabefore 1.0 
Whitewater Madness1.6Bottom part of the screen is not correct, due to changing video address
+	when display is already on
Wolfenstein 3D*1.2Uses DMA sound on STE
Zool (demo)1.0 
Zero-5 (demo)1.4STE DMA sound, Blitter and palette.  STE joypad works, but
+      there are issues in mouse control. With Hatari versions earlier
+      than v1.7 there's flicker and wrong colors on the bottom part
+      of the in-game screen

+
+
STE demos

+
+
Blitter emulation cycle-accuracy is an issue for some demos.

+
+
+  
+  
+    
+      
+      
+      
+    
+  
+  
+    
+      
+      
+      
+    
+    
+      
+      
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+    
+    
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+    
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+    
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+    
+    
+      
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+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+  
+
Tested STE demos
DemoHatari versionNotes
Aggression:
+      Armada is dead1.0 
Aggression:
+      Braindamage1.3 
Aggression:
+      RGBeast1.9Overscan + blitter. Requires Hatari ≥ 1.9
Anatomica:
+      Extreme Rage1.1Bad blitter timings cause timer B to occur at wrong time
Atari scene collective:
+      20 years*1.1You may need to reset between screens
Brainless Institute:
+      Bad Taste1.4Demo crashes during the vector balls at the beginning. This is due to
+	the blitter overwriting some code (due to a bug in the sprite routine)
+	but the reason why it happens only under Hatari was not found yet
Checkpoint:
+      ATM 10 Years1.8Streamed music, voxels
Cream: Madness1.2Music demo with Amiga Paula soundchip emulation + tunes
Cybernetics: New Stream
+      1.8WRITER.PRG doesn't work due to FDC "write track" command,
+      but demos work fine if you convert IMG files to ST floppy images
+      by removing their 8 byte header.
+    
Cybernetics: Relapse
+      1.9WRITER.PRG doesn't work due to FDC "write track" command (same as 'New Stream').
+      The Graphix Sound 2 part uses blitter with overscan and requires Hatari ≥ 1.9.
+    
Defence Force:
+      Save The Eearth1.5Right border switches, blitter, extended palette, HW
+          scrolling/screen splitting, DMA music + microwire/lmc control.
DHS:
+      Cernit Trandafir1.5 
DHS:
+      Just Musix 21.0 
DHS:
+      More or Less Zero1.5 
DHS:
+      Tyranny &
+      Massacrebefore 1.0 
Dune/Sector One:
+      Antiques1.6.2The Greeting Parts requires Hatari 1.6.2 to work, it will flicker sometimes
+	  but that's a bug in the demo, not in Hatari
Dune/Sector One:
+      UFO1.7Requires --fastfdc off
Electronic Images:
+      Music Dream II1.5This demo requires accurate values when reading dma sound address ($ff8909/0b/0d)
+	  and won't work correctly with Hatari < 1.5
GGN:
+      The Sierpinski overdose 4K1.0Uses blitter, requires med-rez
ICE:
+      Ecstacy Abefore 1.0 
ICE:
+      Jam-Cols1.4Changes background color using blitter
ICE:
+      Kryos &
+      Intruding1.1Planes are shifted
ICE:
+      Space Tale1.4In the part with 3 horizontal scrolltexts, bottom border is not removed
+          due to bad blitter timing
ICE:
+      The Wave Of The Future1.6.2
Imagina:
+      Xmas demo 92before 1.0Flickers without frameskip
Imagina:
+      Systematic error1.4
Light:
+      E605before 1.0 
Light:
+      Power Rise1.1 
Light:
+      VGA slideshow1.2Some vertical bad pixels stripes and one of the images broken, otherwise fine.
Masters of Electric City:
+      Unbeatable1.8Monochrome.  Claims to work in ST, but due to bug in demo,
+does only on STE
MJJ-Prod:
+      1st Stepbefore 1.0 
MJJ-Prod:
+      Tribute to Rainbow TOS1.1 
New Core:
+      Beyond Deadlinebefore 1.0 
New Core:
+      Coreflakes1.1 
Next: Illusion1.2Part of the Phaleon Gigademo
N.L.C:
+      Techno Drugsbefore 1.0 
No Extra:
+      0OMPA1.8 
No Extra:
+      Infinite Live of the Blitter1.8+Demo crashes in Hatari v1.7/v1.8 due to Blitter / MFP timings issue. Needs floppy in drive A
Omega:
+      Grotesquebefore 1.0 
OUCH:
+      Songs Of The Unexpected1.5 
Oxygene:
+      Amiga Demo 21.450kHz DMA sound
Paradox:
+      20 years Atari STE megademo1.4Sound is broken in Paradox color zoomer screen
Paradox:
+      X-mas 2004 demo1.4The last (4th) screen horizontal scroll texts don't look right
+      and are jerky. It also needs frameskip even on 1.4Gz Athlon XP
Paradox:
+      Pacemaker1.1
+        Some garbage in the end screen when the demo has been started from
+        hard disk.
+      
Paradox:
+      HighResMode1.5Use spec512 mode in med res. Requires Hatari ≥ 1.8 for correct
+	alignment between bitmaps and color changes
POV:
+      POV 1361.6Hatari doesn't support modifying $ff8205 and reading it back
+      while display is enabled.  Without VBL sync, there's a only 10%
+      chance of STE HW detection working
Reservoir Gods:
+      Mind Rewindbefore 1.0Opens all borders, heavily abuses horizontal STE HW scrolling
Reservoir Gods:
+      Grimeybefore 1.0 
Sedma:
+      Blitter Mania1.1 
Syntax:
+      Reanimationbefore 1.0 
Stax:
+      Compact Disk #65Requires TOS ≥ 1.06. MegaST's real time clock should be disabled
T. Barker:
+      Fantasiabefore 1.0For any other than TOS 1.06, you need to use fantfix.prg first
The Pixels Twins:
+      Mental Hangover1.5Does not work with cartridge / HD emulation. Real Time Clock should
+	  also be disabled to prevent a bug in the boot sector's loader (depends
+	  on the TOS version used). Sound requires Hatari ≥ 1.5 to work
+	  (the routines write in the sample buffer while it's played by the dma)
Unit 17:
+      Dynamite1.2 
Unit 17:
+      E.P.S.S. Demo1.4Video counter is modified while display is ON
Ym-Rockerz:
+      Tyme Warp1.8The demo tries to detect/restore $ff8e21 (cpu control on Mega STE) in a way
+	that isn't (properly) supported by current bus error handling. The demo also
+	crashes on a real STF, although pouet.net wrongly lists it as STF compatible
Zeal:
+      Birdie 2 &
+      Lethal Trash1.0 

+
+
STE applications

+
+
Finally some STE only or STE enhanced applications.

+
+  
+  
+    
+      
+      
+      
+    
+  
+  
+    
+      
+      
+      
+     
+    
+      
+      
+      
+     
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+     
+  
+
tested STE applications
ApplicationHatari versionNotes
Hextracker1.7Uses non-standard mouse event scaling factor.
+          Mouse cannot (vertically) traverse whole Hatari window
+          unless mouse grab or fullscreen mode is used
MaxYMiser DMAbefore 1.0 
Octalyser STE1.0Opens left and bottom border, screen flickers when playing
+          mods if Octalyser isn't configured correctly for the machine
Protracker STE1.4Opens bottom border, 50kHz DMA replay
Stretchbefore 1.0Screen extender (like the famous Bigscreen). One of the few programs
+          which uses STE hardware scrolling also in monochrome mode

+
+
+
TT software compatibility list

+
+
Most programs that work on TT work also in the Falcon emulation and
+as all 1-8 bit GEM programs work without problems under TT emulation
+this section lists only TT-specific games and demos.

+
+
TT games

+
+
+  
+  
+    
+      
+      
+      
+    
+  
+  
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+  
+
TT games
GameHatari versionNotes
OpenTTD1.9"hatari-prg-args --machine tt --tos tos306uk.img  -s 4 --ttram 256 --
+./openttd-m68020.gtp -m null -s null -b 8bpp-optimized", select
+"original" as "Land generator" at game start.  Works also on Falcons
+with FPU
Oxyd 2 TTbefore 1.0Oxyd 2 in color

+
+
TT demos

+
+
+  
+  
+    
+      
+      
+      
+    
+  
+  
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+  
+
TT demos
DemoHatari versionNotes
Brainstorm:
+      Adebug 3DTT demo1.2(Works also on Falcon)
gwEm:
+      4getful1.0TT-version of gwEm's 4K demo
Moving Pixels:
+      TT-Warsbefore 1.0 
Omega:
+      Swing, Vinjett, Xitkul1.2TT demos included to XiTEC presentation. Xitkul colors flicker
tSCc:
+      256mbrot, Bragg256, Glasstro, Orion-B, Yabt1.8TT/Falcon intros, Bragg256 requires WinUAE CPU core
tSCc:
+      Beams1.8TT-version.  Doesn't work, stops at startup screen!
tSCc:
+      CrY image viewer1.9Needs TT-RAM.  interlaced 16bpp CrY mode flickers badly + colors are wrong
tSCc:
+      TC fish1.8Flickers badly
tSCc:
+      TT-hires1.8Needs 8MB. Slideshow flickers badly + graphics and colors are wrong
Xanth FX:
+      Shiny Bubbles TT1.2 

+
+
+
Falcon software compatibility list

+
+
You can select between three different DSP emulation modes with
+the Hatari "--dsp" option:
+
    
+  
  • none: No emulation.
+      If program doesn't need/use DSP, this is the best option.
    • 
+  
  • emu: Experimental DSP emulation.  Needed if program
+      requires DSP. On by default for Falcon. Slow.
    • 
+  
  • dummy: Faked DSP response to DSP commands.
+      Some rare programs that need DSP may also work with faked DSP.
+      This is much faster than the real DSP emulation.
    • 
+

+
+
The "dsp" column in tables below tells which DSP emulation mode
+needs to be used for the given program to work.  If it doesn't matter,
+the column contains "-". The column for whether the program works and
+for whether it has (working) sound have "yes" when this is true and
+otherwise "-".

+
+
Note: many timing critical demos (for example ones using
+NoCrew's DSP MP2-player) that are marked as working in the list below,
+work only with the experimental WinUAE CPU core. Please see
+Hatari readme.txt on how to enable that.  If program works only with
+old UAE core, that's noted separately.

+
+
Due to incomplete VIDEL emulation and some remaining emulation
+cycle accuracy issues, some Falcon programs don't work yet.

+
+
+
Falcon games

+
+
+  
+  
+    
+      
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+     
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+     
+    
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+     
+    
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+    
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+    
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+    
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+    
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+    
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+      
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+     
+    
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+    
+    
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+      
+     
+    
+      
+      
+      
+      
+      
+     
+    
+      
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+      
+      
+      
+     
+    
+      
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+      
+     
+    
+      
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+      
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+      
+     
+    
+      
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+      
+      
+     
+    
+      
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+      
+      
+      
+     
+   
+      
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+      
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+    
+    
+      
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+      
+     
+    
+      
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+     
+    
+      
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+    
+    
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+    
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+    
+    
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+    
+    
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+      
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+    
+    
+      
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+      
+      
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+    
+    
+      
+      
+      
+      
+      
+     
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+     
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+     
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
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+    
+    
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+    
+    
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+      
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+    
+    
+      
+      
+      
+      
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+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
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+      
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+    
+    
+      
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+      
+      
+      
+    
+    
+      
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+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+     
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
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+    
+    
+      
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+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+  
+
Falcon games
TitleHatari versionSoundDSPComment
Aazohm Krypth1.3-emuUse joypad. 8MB RAM. Black screen without DSP emu
Aces High preview1.3--
Addsub1.6--Exits when joystick is used
Bad Mood (game)1.7yesemuEnhanced Doom I/II port and engine rewrite.  Requires WinUAE
+      CPU core, DSP and 14 MB RAM. Statusbar doesn't show due to Videl
+      emulation omissions, unless "--natfeats yes" is used to tell
+      game to use Hatari specific/heavier statusbar drawing mode.
+      Some parts have clear speed differences to real Falcon due to
+      CPU, FPU (instruction too fast) and Videl emulation
+      (screen updated only at VBL) inaccuracies
Bad Mood (old viewer)1.3-emuOld Doom level viewer. All tested versions (v2.14a, v307a)
+          work with Doom wad, but look wrong with Heretic wad
Blackhole1.0yes-640x400@256 mode only
Block Blizzard (preview)1.0--
Blum1.4yes-Background music if DSP emu enabled
Bomb Squad1.0yes-
Boom preview1.3yesemu
Bugger1.4yesemuIf DSP emulation is disabled, game play pauses randomly
Bunion1.4yesemuIf DSP emulation is disabled, game play pauses randomly
Capy1.9yesemuTT-medium/VGA (640x480x16) only. Some version(s) bus error
+	  on TT due to DSP register check (although they should support
+	  TT with chip music).  Main menu works unreliably (doesn't
+	  always react to indicated keys).
Cavemania (demo)1.9yes-Some menus are black (space gets through them).
+          Screen bottom has garbage. Background music with DSP emu
ChainZ1.9yes-Background music with DSP emu (keep space pressed while game is
+          starting to disable that). VGA only
Chorensha1.8yes-Needs 14MB
Conquest of Elysium II1.0yes-
Columns by Deadheart (demo)1.0yes-Nice. Background music if DSP emu enabled
Confusion (demo)1.3yes-Background music if DSP emu enabled.  Both demos 1 & 2 work
Corsair1.0yes-Background music if DSP emu enabled. Multiplayer
Crown of Creation 3D1.3yesemuNon-interactive pre-preview
DB 4K1.0--DB in 4KB
Double Bobble 20001.9yesemuWith earlier Hatari versions (1.4) worked also without DSP emulation
DownFall1.5yes-Music is rather noisy.
Epi-Lepsie1.4yesemu
Evolution Dino Dudes
(aka. Humans)		1.3--Intro and menu work, but graphics are distorted in game.

+          (Game writes twice to the $ff820e register during one VBL!)
Falcon Fighter II1.0yes-ST low version has problems with scrolling (which doesn't
+          happen with with STe emulation). In TC version parts of sprites
+	  get stuck to top of screen
FalcTron1.3yes-
Ganymed1.3yes-Use F1 to start game. With DSP emu there's bg music
Galaga 881.9--Needs 14MB RAM
Golden Island (demo)1.9yes-VGA only.  Freezes with WinUAE CPU core due to CPU-DSP
+      emulation cycle accuracy. Works with OldUAE and worked with
+      v1.8 WinUAE CPU core
Gravon (demo)1.4yesemu3D hovercraft.  Slow
Great1.3yes-Atoms clone
H2O1.4yesemuNice.
Hexogan (v0.6)1.4yes-Use number keypad to play
Impulse1.3yes-Nice breakout clone.  Background music if DSP emu enabled
Ishar 3 (CD)1.3yes-Nice adventure game.
Jewelz1.9yes-Background music with DSP emu (game F1 / Falcon option). VGA only
"K"1.6yesemuPreview for a Karting game by EXA.  First entry in Training menu allows playing
Killing Impact1.6yes-Modern version of Joust, up to 4 players.  Sound with DSP.
+          Game screen colors etc are all wrong.
+    
Kwiks.pd1.9yes-Nice Quix clone
Lamemine1.0yesdummy emuBackground music if DSP emu enabled
Lasers and Hommes (DLDH2)1.6yesemuSlow
Les Dinosaures (demo)1.6yesemu
Llamazap1.6--Requires joypad.  Linked version doesn't have (DSP) music, others have
Madtris1.0yes-
Masters of Chaos1.1--2-4 player "Dungeon Master". 4 players needs MIDI. Works only with 1-2MB of RAM
Men at War (preview)1.9yesemuRequires now both WinUAE CPU core and DSP to be enabled. Bullets
+          aren't visible. Cannot be auto-started (freezes like without DSP).
+	  Separate intro program flickers, and double bus errors at end
Milanopol1.0--
Mini F1 demo1.8--Freezes when the game would start.  Sound is just noise.
+          Constant "crossbar DMA Play: Illegal buffer size" messages
Moongame1.6-emuPointer cannot be moved in the game menu
Moonspeeder (preview 2)1.8-emulst*.* files need to be renamed as game searches them with
+          different name (space before dot).  Pointer cannot be moved
+	  in the game menu (preview 1 works, but is non-interactive)
Mouse trap1.8yes-Initial game screen looks OK, then suddenly screen mode gets wrong
Multi Briques1.6yesemuSome versions work, some get stuck at start with white screen
Neurobot.1081.0yes-
Nibe21.4--Videl emu doesn't support rasters in title screen
Offworld Security1.8+yes-In earlier Hatari versions startup screen was black
Operation Skuum1.3yes-
Pac Them1.0yes-Nice
Pacmania X680001.9--Needs 14MB RAM.  Original resolution version flickers, PM*.TOS versions don't
Painium Disaster1.0yes-Some display problems
Pinball Dreams1.6yes-Main menu works only with WinUAE core.  Actual game screen is scrambled / doesn't work.
Pingo981.6yesemuColors wrong in classic version, TC version just exits.
+          DSP used for background music
PMHeretic & PMDoom1.0yes-Very slow
Poker1.3yes-Works only in VGA
Pong 2K (demo)1.3yes-Background music with DSP. A bit unstable
Pouspous1.0--Image puzzle. HiColor only
Push It1.4yes-Crashes if auto-started. Background music if DSP emu enabled
Q-Blue1.0--Hicolor / VGA only
Radical Race (demo)1.0--Nice
Raiden1.0yes-Use joypad, needs over 4MB
Rave1.0yesdummy emuBackground music with DSP
Reeking Rubber1.8yes-(required proper emulation of Videl palette registers at startup)
Risk 0301.3.1--VGA (640x480) only.  If auto-started, resolution isn't correct
Running1.3yesemuA Doom like game.  Both the 1996 preview and 1997 shareware
+          versions work fine.  Doesn't work if auto-started.
SBM v0.81.0--Nice Bomberman clone
SBM v1.031.6--Requires WinUAE CPU core
Shangai (demo)1.3--
Sheer Agony1.3yes-
Snatch by FUN1.3yes-VGA 640x480x16 mode only. Background music with DSP
Sky Fall1.9yesemuIf auto-started, wants to access also A: and B: drives
Slippery Sam1.6yesdummyNeeds 14MB of RAM. Background music if DSP emu enabled
Sokoban by FUN1.6yesemuVGA 640x480x16 only, Exception 2 + Pterm(-1) after loading data
Space Taxi1.0--
Spice1.0yes-Nice Defender clone
Static1.0--Play solitaire against computer
Steinbruch1.0yes-Use STE joypad. Background music if DSP emu enabled
Sweety Thingies1.6yes-Background music if DSP emu enabled
Switch1.0yes-Background music if DSP emu enabled
Sworm1.9yesemuIf auto-started, wants to access also A: and B: drives
Tank Blaster1.3yes-
TeknoBalls1.4yesemuBreakout clone
Tautology1.9yes-
Tautology II1.9yes-Nice Mahjongg variant. Supports Joypad (configurable).
+          Background music with DSP emu enabled.
Tetrhex1.0--
Towers 21.3yesemu
ToyMan1.0--Pacman
Tron 21.6yesdummy emuScreen scrambled in v1.6, worked fine in v1.0 - v1.4. Background music if DSP emu enabled
TsccTron (preview)1.6yes-Works only occasionally, bottom screen black.
+          Background music if DSP emu enabled
TUM1.0yes-GEM minesweeper
Ufo War1.6yes-Screen scrambled. With DSP emu, bg music for a while
Ultimate Arena (demo)1.5yesyesFalcon version of the game
Vertical Mayhem(+)1.0yes-Works perfectly, nice columns clone
Watership1.6yesemuSome glitches at the bottom of the screen
Willie Adventurer1.0yes-Both 1st and 2nd preview versions work, but 1st one has
+          scrolling/display issues. Background music if DSP emu enabled
Wotanoid1.4yesemuAsteroids clone
X-moon1.7yes-Works only with WinUAE core. Needs Joypad. Background music if DSP emu enabled
Zodiax (demo)1.0yes-Nice R-type game clone

+
+
+
Falcon demos

+
+
Some demos require FPU, although normal Falcon's don't have a one.
+Old UAE CPU core always emulates FPU both for TT and Falcon machines.
+With WinUAE CPU core you need to enable FPU separately if demo is
+stated to require that.

+
+
+  
+  
+    
+      
+      
+      
+      
+      
+    
+  
+  
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+     
+   
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+    
+  
+
Falcon demos
TitleHatari versionSoundDSPComment
Aggression:
+      Aggressive II party info1.4yesemuGraphics don't look same as on pouet.net screenshot
Aggression:
+      Motion1.3-emuUnfinished Aggression demo with 030 and DSP source code.
+          Almost all screens work now, some have visual glitches.
An cool:
+      The Keff demo1.8+yes-gets stuck after dragons pic with circle on black screen
Aura:
+      E.X.Illusion1.6yesemuNeeds WinUAE core in Hatari v1.6
Avena:
+      Sonolumineszenz1.3yesemuNice
Avena:
+      Weltschmerz1.3yesemu
Black Scorpion Software:
+      Atari UK demos1.3yesemuplasma50.prg has screen update issues
Brainstorm:
+      Mouse1.4yes-AVR animation/music with Brainstorm player.
+          Background music with DSP emu
Cerebral Vortex / Dune / Sector One
+      Tere Ra'I1.8yes-Music with DSP
Collapze:
+      Sidetracked1.4-emuMusicdemo GFA interface looks completely broken + mouse doesn't work properly
Crac:
+      Bound,
+      Bound 2,
+      Bound 3
+      1.3yesemu
Crac:
+      Bound 4,
+      Bound 5
+      1.8yesemuExpect Videl screen address counter to change
Cream:
+      Binliner preview1.6yesemuFreaky screen works. Land & Worship screens die to illegal instruction 4afc
Cruor:
+      96ktro1.3yesemu
Cruor:
+      The mountains flight1.3yesemu
DHS:
+      128dist1.7--Requires FPU
Dekadence:
+      Payback 20151.8+--Doesn't continue from startup logo
DHS:
+      128 krawl1.7--Requires FPU
DHS:
+      4ever1.7--Requires FPU
DHS:
+      4orce1.7yes-Requires FPU
DHS:
+      A.T.S1.0yes-Fast. Needs FPU. Background music with DSP emu
DHS:
+      Don't Break The Oath1.5--Needs 14MB RAM and FPU. Uses NoCrew DSP MP2-player
DHS:
+      Dream Dimension1.7yesemuRequires FPU
DHS:
+      Echos1.7yesemuRequires FPU. Uses DSP for the music
DHS:
+      GEM-demo1.3--Needs to be started in HiColor mode to work properly
DHS:
+      Outline 2006 invite1.5--Needs 14MB RAM, uses NoCrew DSP MP2-player
+      (recommended: --memory 14 --cpuclock 32 --dsp none --monitor vga
+      --sound off --fast-forward yes)
Digital Chaos:
+      Built-in Obsolescence1.6.2yesemuRequires WinUAE CPU core, gives DSP stack overflows
DNT Crew:
+      Agony1.4yesemuAfter few screens freezes with black screen
DNT Crew:
+      Chaos A.D.*1.5yesemuUses its own IKBD 6301 routine to decode the demo's protection.
+	Demo runs correctly but sound is rather noisy
DrTypo:
+      Voxel1.9-emuAt least 4MB RAM, FPU and VGA monitor
EKO:
+      Are You Experienced?1.6yesemuRequires WinUAE CPU core
EKO:
+      E.K.O System1.6yesemuRequires WinUAE CPU core
EKO:
+      Epidemic musicdisk1.4yes-Bombs out when it comes to the menu
EKO:
+      Geranium1.3yesemu
EKO:
+      Papa was a Bladerunner1.3yesemuTexture mapping uses DSP, but otherwise works fine also without DSP
Escape:
+      _1.6yesemuFreezes or exits after few screens to illegal DSP instructions
Escape:
+      Hmmm...1.3yesemu"Classic" from 2001
Escape:
+      Illness1.3yesemu
EXA:
+      Entcarte1.8--Bombs immediately
Extream:
+      Old Stuff1.8yes-Music with DSP
Extream:
+      Whirlpool 128k1.3yesemuTransitions look a bit strange
Fit:
+      Hex Pistols1.9yesemu14MB + MMU + FPU, .tSCc port from Amiga
Fit:
+      Mahabharata1.3yesemuBombay-style...
Fit:
+      Stercus Accidit1.8+yesemu8MB + FPU, .tSCc port from Amiga
Fun Industries:
+      Alive1.3yes-Background music with DSP emu
Fun Industries:
+      Fungle Beats1.6yes-Needs WinUAE CPU core.  Background music with DSP emu
Gaston:
+      Earth1.0--Texturemapped ball
ICE:
+      Cooler than ever1.0yes-Background music with DSP emu
ICE:
+      Tron20011.4yes-Bus error at startup unless IDE enabled. Screen resolution or
+          update issues. Non-interactive game(?) demo.
Impulse:
+      Bugs from Outer Space1.1yes-
Lazer:
+      Autowaschen Verboten1.3yesemu
Lazer:
+      Gurkensalad1.3-emu4K
Lazer:
+      Lost Blubb1.6yesemuRequires WinUAE CPU core
Lazer:
+      Oergs1.3yesemuBarely an intro
Lazer:
+      Warum1.3yesemuNice
Light:
+      680xx1.3yesemuMusic is broken
Lineout:
+      Delta1.3yesemuNice (+ almost half an hour long + includes sources)
Lineout:
+      Hurry1.3yesemu
Lineout:
+      Out1.3yesemu
Mind Design:
+      4some1.9--Requires FPU. Hangs/crashes in plasma screen with WinUAE CPU core and also with VGA version
MJJ Prod:
+      Bound 421.4yesemuCrashes at cyan millstone screen
Mugwumps:
+      Cycedelic knockout1.8+yesemuNice techno + color cycling
Mystic bytes:
+      Chosneck Supplement (e5)1.4yesemuNeeds 14MB RAM.  Music notes screen colors aren't right
+          (Hatari Videl emu doesn't support palette cycling?)
Mystic bytes:
+      Moai 96kB1.4yesemu14MB RAM + (EC)030 + FPU. Works only with old CPU.
Mystic bytes:
+      Time Out1.6yesemuRequires WinUAE CPU core
Mystic bytes:
+      Virtual Dream1.7--Requires FPU. Crashes with bus error after a few seconds
New Beat:
+      Blue1.1--Very nice 4K demo from New Beat
New Beat:
+      Flu1.1yes-Very nice 4K demo from New Beat. Flu requires FPU
New Beat:
+      Maggie 24 intro1.3-emu
NoCrew:
+      Aggressive Party 2 4k1.4-emuUses DSP play / DMA record in handshake mode.  Doesn't work if auto-started.
NoCrew:
+      Stocasto1.6yesemuBombs on startup (in v1.5 it froze, but in later stage)
Opium:
+      Chrome Dragon1.0yes-With Hatari v1.6, needs WinUAE core
Opium:
+      Falcon Flight1.0yes-
Orion_:
+      Unexpected Fun1.9yes-needs 8 MB TT ram, music with DSP.  Colors are wrong
Paranoia:
+      Illusion 641.3yes-Background music with DSP emu
POV:
+      JESTERday1.4yesemu256 colors DSP+DMA MOD music demo
Psychosis:
+      FOG-intro1.3yesemu
Reservoir Gods:
+      Are you sitting comfortably?1.3yesemuNeeds 14MB to work properly (otherwise bombs or gets Dsp overflow)
Reservoir Gods:
+      Ascii, SnowStorm, HongTron1.0--Intros by RG
Shadows:
+      Firestarter1.0yes-Background music with DSP emu, slow otherwise. Doesn't work if auto-started
STAX:
+      Doomino1.4-emuDoesn't work with 020 CPU
TBL:
+      Ocean Machine, Rift, Silkcut, Startstruck1.9yes-Require 060 + FPU + 4MB / 32MB TT-RAM (DSP + sound can be disabled to speed up emulation)
The Respectables:
+      Cebit 93 demo1.9yes-Requires WinUAE CPU core for screen to be drawn correctly
Trio:
+      124 beers later1.6yes-
Trio:
+      X-tasie1.7--Demo requires 030 MMU, i.e. it only runs with WinUAE CPU core and when
+          MMU has been enabled. There is a Videl emulation problem left when
+          the user moves the mouse during the first screen.
tSCc:
+      30L Coke &
+      A Rh positive1.3-emu4K demos. Rh positive flickers a bit
tSCc:
+      Beams
+      (Falcon version)1.5--Nice demo, NoCrew DSP MP2-music
tSCc:
+      Six Sievert1.3--
tSCc:
+      Terrorize your soul1.3yesemu
Tony Benett:
+      Virtual City1.1-emuHiColor, drawing the city requires DSP emulation
Toons:
+      Yepyha1.6yes-Strange screen sizes, stops in middle.  With DSP, has
+          background music, but stops earlier to DSP stack overflow
T.O.Y.S:
+      wait1.6yesemuUses NoCrew DSP MP2-player
Wildfire:
+      4kbtro1.3-emuJulia fractals
Wildfire:
+      4tune1.7-emuRequires FPU and DSP
Unknown:
+      Birdshow1.0--A simple FLE animation player
Unknown:
+      ROT3DBMP1.8+-emuStreams data to DSP without synchronization

+
+
More Falcon demos can be found e.g. from the Atari.Org
+Falcon demos archive
+and demo tools from the dhs.nu demoscene
+site.

+
+
+
Falcon applications

+
+
Here are listed some Falcon specific applications:

+
+  
+  
+    
+      
+      
+      
+      
+    
+  
+  
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+  
+
Falcon applications
TitleHatari versionDSPComment
AceMidi
+          (demo)1.6emuDSP generated softsynth sounds need Hatari at least v1.6 to sound OKish
AceTracker v21.8emuIndividual synthetized sounds are fine with WinUAE CPU core,
+          but full AM module playback audio quality is bad
AFM (audio fun machine)1.4emu
Apex (demo)1.8+-Crashes with a "MOVE.W $fff20000,D0" instruction.
+        It's unclear why this works on a real Falcon.
+        The separate imageviewers work fine.
Aniplayer1.8+emuDSP stack underflow on switching JPG images, synchronization
+          doesn't work when DSP used with DMA transfers to play MP3
AVI 0301.8+-Worked with Hatari v1.1, freezes with v1.6, TTP exits with v1.8+
Centview1.3emuRemember to run included JPEGD.PRG first (or put it to AUTO-folder)
Centurbo bench1.9emuNew WinUAE CPU core: FPU 812 Mhz, DSP 56 Mhz, CPU 26 Mhz

+          Old WinUAE CPU core: FPU 221 Mhz, DSP 32 Mhz, CPU 15 Mhz

+          Old UAE CPU core: FPU 403 Mhz, DSP 32 Mhz, CPU 78 Mhz

+	  (moving mouse drops FPU and CPU numbers slightly)
Chronos 3D player1.8+-Complains about wrong resolution, requires 15-bit
Delmpaint1.0-Errors at exit if started in other than 256-color low rez
Escapepaint1.1-Very nice
FalcAMP1.6emuMOD playing works fine, MP3s have no sound / complain about DSP timeout
FlaySID (v3.01)1.8+emuNo sound from SID playback with DSP engine, only with YM engine
FlexTrax1.8+emuFreezes with old UAE core, but even with WinUAE core, sounds is noise.
+          Startup graphics look OK only in VGA mode
GemPLAY1.8+emuSomewhat unstable.  Sound quality depends on which CPU core is used,
+          AM module is complete noise with old UAE CPU core.
+          Fileselector dir selection doesn't work with v1.92 or newer (GemPlay bug)
Godpaint1.0-
Hextracker1.7-Freezes at start waiting Videl screen address counter to change
Indypaint1.0-Errors at exit if started in other than HiColor mode.
MP2 player1.5emuNoCrew MP2 sound player
Rainbow II multimedia1.5emuWorks only with the new WinUAE CPU core. With old UAE core,
+          bombs immediately at startup (MMU not emulated in old UAE).
+          Mouse cannot traverse whole screen unless mouse grab or
+          fullscreen mode is used
ScummVm1.9-Very slow, needs FPU, a lot of TT-RAM and user-specified config file name
+          ("hatari-prg-args.sh -s 14 --ttram 256 --machine falcon --tos tos404.img
+          --dsp none --addr24 off --fpu-type internal -- ./scummvm-m68020-olivier.ttp
+          -c scummvm.cfg")
Whip1.4emuEffects are working
WinRec1.4emuDirect-to-disk recording with DSP sound effects processing

+
+
+
TT/Falcon utilities

+
+
Here are some utilities that either have specific TT and/or Falcon
+support or work only on them.

+
+
+  
+  
+    
+      
+      
+      
+    
+  
+  
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+  
+
TT/Falcon utilities
UtilityHatari versionNotes
Adebug (reloaded)1.7Debugger supporting 68000 - 68030.  On Falcon and TT this
+          uses MMU i.e. requires WinUAE CPU core
Calamus SL (1991 demo)1.0Nice with Hatari TT or 32Mhz Falcon emulation at
+          e.g. 1024x768x1 VDI resolution...
Calamus SL lite 20xx1.9Newer versions work only with EmuTOS (2015-04-26 git version or newer),
+          FPU, lot of both ST and TT-RAM and at least 800x600 resolution.
+	  ("--machine tt -m -s 14 --ttram 32 --tos etos512k.img", or
+	   "--machine falcon --dsp none --fpu-type 68882
+	    --vdi-width 896 --vdi-height 608 --vdi-planes 4
+	    -s 14 --addr24 off --ttram 32 --tos etos512k.img")
Cecile1.2Hard disk driver.  In Hatari works only with IDE emulation.
+          Supports only TT and Falcon
FreeMiNT1.2Needs to be installed/booted from an ACSI or IDE HD image and
+      memory protection needs to be disabled (Hatari old UAE core doesn't
+      emulate MMU)
HD Driver1.4Hard disk driver.  In Hatari works only with IDE emulation. With TOS v4,
+      CPU needs to be set to EC030 or better, with TOS v3 works also with 020 CPU
+      (used by earlier Hatari versions for TOS ≥ v3)
ROMSPEED1.9Utility to copy and run ROM from Fast-RAM to accelerate its working.
+      Requires TT-RAM / WinUAE CPU core to work.  Different memory
+      timings on different memory areas aren't emulated yet, so no
+      speed changes are visible

+
+
+
Software sites

+
+
In case you're new to the Atari scene or an old-timer who's forgotten
+where all the freely available software is, these file archive sites
+still retain their Atari sections:

+
+
+
Demos (for many platforms) can be found from pouet.net and
+besides Atari scene news, Dead Hackers Society provides descriptions,
+screenshots and files for tools to create music, graphics and code on
+Atari:
+

+
+
There are also couple of sites dedicated to STE and Falcon specific
+software:

+
+
+

+
+
+
diff --git a/doc/de/tastatur-windows.txt b/doc/de/tastatur-windows.txt
new file mode 100644
index 0000000..2e8126d
--- /dev/null
+++ b/doc/de/tastatur-windows.txt
@@ -0,0 +1,8 @@
+# Below is a keymap file for Hatari running on Windows, which maps the SDL
+# keys of a German PC keyboard to the corresponding Atari ST scancodes.
+
+45,12     # ß
+91,26     # Ü
+93,27     # +
+92,41     # #
+96,43     # ~
diff --git a/doc/doxygen/Doxyfile b/doc/doxygen/Doxyfile
new file mode 100644
index 0000000..29357c6
--- /dev/null
+++ b/doc/doxygen/Doxyfile
@@ -0,0 +1,240 @@
+# Doxyfile 1.5.1-p1
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+PROJECT_NAME           = Hatari
+PROJECT_NUMBER         = 1.9.0
+OUTPUT_DIRECTORY       = .
+CREATE_SUBDIRS         = NO
+OUTPUT_LANGUAGE        = English
+BRIEF_MEMBER_DESC      = YES
+REPEAT_BRIEF           = YES
+ABBREVIATE_BRIEF       = "The $name class" \
+                         "The $name widget" \
+                         "The $name file" \
+                         is \
+                         provides \
+                         specifies \
+                         contains \
+                         represents \
+                         a \
+                         an \
+                         the
+ALWAYS_DETAILED_SEC    = NO
+INLINE_INHERITED_MEMB  = NO
+FULL_PATH_NAMES        = YES
+STRIP_FROM_PATH        =
+STRIP_FROM_INC_PATH    =
+SHORT_NAMES            = NO
+JAVADOC_AUTOBRIEF      = NO
+MULTILINE_CPP_IS_BRIEF = NO
+INHERIT_DOCS           = YES
+SEPARATE_MEMBER_PAGES  = NO
+TAB_SIZE               = 8
+ALIASES                =
+OPTIMIZE_OUTPUT_FOR_C  = YES
+OPTIMIZE_OUTPUT_JAVA   = NO
+BUILTIN_STL_SUPPORT    = NO
+DISTRIBUTE_GROUP_DOC   = NO
+SUBGROUPING            = YES
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL            = YES
+EXTRACT_PRIVATE        = YES
+EXTRACT_STATIC         = YES
+EXTRACT_LOCAL_CLASSES  = YES
+EXTRACT_LOCAL_METHODS  = NO
+HIDE_UNDOC_MEMBERS     = NO
+HIDE_UNDOC_CLASSES     = NO
+HIDE_FRIEND_COMPOUNDS  = NO
+HIDE_IN_BODY_DOCS      = NO
+INTERNAL_DOCS          = NO
+CASE_SENSE_NAMES       = NO
+HIDE_SCOPE_NAMES       = NO
+SHOW_INCLUDE_FILES     = YES
+INLINE_INFO            = YES
+SORT_MEMBER_DOCS       = YES
+SORT_BRIEF_DOCS        = NO
+SORT_BY_SCOPE_NAME     = NO
+GENERATE_TODOLIST      = YES
+GENERATE_TESTLIST      = YES
+GENERATE_BUGLIST       = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS       =
+MAX_INITIALIZER_LINES  = 30
+SHOW_USED_FILES        = YES
+SHOW_DIRECTORIES       = NO
+FILE_VERSION_FILTER    =
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET                  = NO
+WARNINGS               = YES
+WARN_IF_UNDOCUMENTED   = YES
+WARN_IF_DOC_ERROR      = YES
+WARN_NO_PARAMDOC       = NO
+WARN_FORMAT            = "$file:$line: $text"
+WARN_LOGFILE           =
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT                  = ../../src
+FILE_PATTERNS          = *.c \
+                         *.cc \
+                         *.cxx \
+                         *.cpp \
+                         *.c++ \
+                         *.h \
+                         *.hh \
+                         *.hxx \
+                         *.hpp \
+                         *.h++
+RECURSIVE              = YES
+EXCLUDE                =
+EXCLUDE_SYMLINKS       = NO
+EXCLUDE_PATTERNS       =
+EXAMPLE_PATH           =
+EXAMPLE_PATTERNS       = *
+EXAMPLE_RECURSIVE      = NO
+IMAGE_PATH             =
+INPUT_FILTER           =
+FILTER_PATTERNS        =
+FILTER_SOURCE_FILES    = NO
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER         = YES
+INLINE_SOURCES         = NO
+STRIP_CODE_COMMENTS    = NO
+REFERENCED_BY_RELATION = YES
+REFERENCES_RELATION    = YES
+REFERENCES_LINK_SOURCE = YES
+USE_HTAGS              = NO
+VERBATIM_HEADERS       = YES
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX     = NO
+COLS_IN_ALPHA_INDEX    = 5
+IGNORE_PREFIX          =
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML          = YES
+HTML_OUTPUT            = html
+HTML_FILE_EXTENSION    = .html
+HTML_HEADER            =
+HTML_FOOTER            =
+HTML_STYLESHEET        =
+HTML_ALIGN_MEMBERS     = YES
+GENERATE_HTMLHELP      = YES
+CHM_FILE               =
+HHC_LOCATION           =
+GENERATE_CHI           = NO
+BINARY_TOC             = NO
+TOC_EXPAND             = NO
+DISABLE_INDEX          = NO
+ENUM_VALUES_PER_LINE   = 4
+GENERATE_TREEVIEW      = NO
+TREEVIEW_WIDTH         = 250
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX         = NO
+LATEX_OUTPUT           = latex
+LATEX_CMD_NAME         = latex
+MAKEINDEX_CMD_NAME     = makeindex
+COMPACT_LATEX          = NO
+PAPER_TYPE             = a4wide
+EXTRA_PACKAGES         =
+LATEX_HEADER           =
+PDF_HYPERLINKS         = NO
+USE_PDFLATEX           = NO
+LATEX_BATCHMODE        = NO
+LATEX_HIDE_INDICES     = NO
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF           = NO
+RTF_OUTPUT             = rtf
+COMPACT_RTF            = NO
+RTF_HYPERLINKS         = NO
+RTF_STYLESHEET_FILE    =
+RTF_EXTENSIONS_FILE    =
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN           = NO
+MAN_OUTPUT             = man
+MAN_EXTENSION          = .3
+MAN_LINKS              = NO
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML           = NO
+XML_OUTPUT             = xml
+XML_SCHEMA             =
+XML_DTD                =
+XML_PROGRAMLISTING     = YES
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF   = NO
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD       = NO
+PERLMOD_LATEX          = NO
+PERLMOD_PRETTY         = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING   = YES
+MACRO_EXPANSION        = NO
+EXPAND_ONLY_PREDEF     = NO
+SEARCH_INCLUDES        = YES
+INCLUDE_PATH           =
+INCLUDE_FILE_PATTERNS  =
+PREDEFINED             =
+EXPAND_AS_DEFINED      =
+SKIP_FUNCTION_MACROS   = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+TAGFILES               =
+GENERATE_TAGFILE       =
+ALLEXTERNALS           = NO
+EXTERNAL_GROUPS        = YES
+PERL_PATH              = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS         = NO
+HIDE_UNDOC_RELATIONS   = YES
+HAVE_DOT               = NO
+CLASS_GRAPH            = YES
+COLLABORATION_GRAPH    = YES
+GROUP_GRAPHS           = YES
+UML_LOOK               = NO
+TEMPLATE_RELATIONS     = NO
+INCLUDE_GRAPH          = YES
+INCLUDED_BY_GRAPH      = YES
+CALL_GRAPH             = NO
+CALLER_GRAPH           = NO
+GRAPHICAL_HIERARCHY    = YES
+DIRECTORY_GRAPH        = YES
+DOT_IMAGE_FORMAT       = png
+DOT_PATH               =
+DOTFILE_DIRS           =
+MAX_DOT_GRAPH_DEPTH    = 1000
+DOT_TRANSPARENT        = NO
+DOT_MULTI_TARGETS      = NO
+GENERATE_LEGEND        = YES
+DOT_CLEANUP            = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to the search engine
+#---------------------------------------------------------------------------
+SEARCHENGINE           = NO
diff --git a/doc/emutos.txt b/doc/emutos.txt
new file mode 100644
index 0000000..ac2dd3f
--- /dev/null
+++ b/doc/emutos.txt
@@ -0,0 +1,1218 @@
+
+Contents:
+- Hatari and EmuTOS
+- What is EmuTOS
+- EmuTOS usage
+- EmuTOS compatibility notes
+- Debugging issues with EmuTOS
+  - EmuTOS debug output and debug symbols
+  - Debugging OS calls, Line-A usage and panics
+  - Debugging freezes
+- EmuTOS free/shareware compatibility lists
+  - Working Atari ST demos and games
+  - Non-working Atari ST games
+  - Atari ST applications (including commercial)
+  - Working Atari STE programs
+  - Non-working Atari STE programs
+  - Atari TT programs
+  - Falcon programs
+    - Falcon demos
+    - Falcon games
+    - Falcon applications
+
+
+Hatari and EmuTOS
+=================
+
+To run the emulator, a TOS ROM image is needed.  EmuTOS, a free
+implementation of TOS, is shipped with the official releases of
+Hatari.
+
+This tos.img ROM image is identical to the official binary package of
+EmuTOS, which is available at the SourceForge website of EmuTOS.  For
+downloading other versions or the source code of EmuTOS, please visit
+the EmuTOS website.
+
+The tos.img file included with the latest Hatari releases is
+the etos512k.img[1] from a preceding EmuTOS release:
+- Hatari v1.9.0:
+  http://sourceforge.net/projects/emutos/files/emutos/0.9.4/
+- Hatari v1.8.0:
+  http://sourceforge.net/projects/emutos/files/emutos/0.9.3/
+- Hatari v1.7.0:
+  http://sourceforge.net/projects/emutos/files/emutos/0.9.0/
+- Hatari v1.6.2:
+  http://sourceforge.net/projects/emutos/files/emutos/0.8.7/
+- Hatari v1.6.0:
+  http://sourceforge.net/projects/emutos/files/emutos/0.8.6/
+- Hatari v1.4.0, v1.5.0:
+  http://sourceforge.net/projects/emutos/files/emutos/0.8.5/
+- Hatari v1.1.0, v1.2.0, v1.3.0, v1.3.1:
+  http://sourceforge.net/projects/emutos/files/emutos/0.8.4/
+- Hatari v1.0.0, v1.0.1:
+  http://sourceforge.net/projects/emutos/files/emutos/0.8.3/
+- Hatari v0.95:
+  http://sourceforge.net/projects/emutos/files/emutos/0.8.2/
+
+Earlier Hatari binary releases have included one of the smaller
+EmuTOS image files.
+
+[1] the "all languages" version intended mainly for TT & Falcon.
+    While the 192k and 256k version on some cases work better
+    for ST and STE programs, only the 512k image contains
+    support for all the hardware and languages.
+
+Note for EmuTOS before 0.8.6:
+  In order to work with Hatari, EmuTOS 0.8.5 and earlier require
+  the FastBoot option to be enabled. This is used to skip some memory
+  tests (that Hatari doesn't support yet) when EmuTOS tries to
+  determine the available RAM size.
+
+
+What is EmuTOS
+==============
+
+EmuTOS is a single-user single-tasking operating system for the 32-bit
+Atari computers and emulators.  It can be used as a replacement for
+the TOS images typically needed today for using the emulators and it is
+also running on some real hardware, like the Atari Mega STE and Atari
+ColdFire.  All the source code is open and free, licensed under the
+GNU General Public License (GPL).  A copy of the GNU GPL can be found
+in the gpl.txt file.
+
+EmuTOS has its home at SourceForge:
+       http://sourceforge.net/projects/emutos
+
+
+EmuTOS usage
+============
+
+There are various reasons for using EmuTOS instead of the original
+TOS ROM images:
+
+* Users who don't have Atari HW or other legal means to obtain the
+  original Atari TOS ROMs (for all of the Hatari supported Atari
+  versions: ST/STE/TT/Falcon), but would like to try out Hatari and
+  see what kind of software the Atari machines had.  EmuTOS gives
+  them a legal way to test Hatari with free demos, games etc.
+
+* Users who want to continue using Atari compatible operating systems
+  and need an open source replacement of TOS for modifications. Beside
+  EmuTOS they typically also use FreeMiNT, XaAES and fVDI as operating
+  system replacements/improvements.
+
+* This includes users of Atari FPGA clones, such as MiST:
+	http://code.google.com/p/mist-board/
+  and users of new "Atari" machines, like Atari ColdFire Project:
+	http://acp.atari.org/
+
+* EmuTOS also allows using ACSI disk images with Hatari TT/Falcon
+  emulation, whereas TOS 3 & 4 support only IDE and SCSI disks.
+  Hard disk images are needed mainly for running MiNT.
+
+
+EmuTOS compatibility notes
+==========================
+
+These comments apply to EmuTOS v0.9.x.
+
+Many commercial games and applications work fine with EmuTOS. This is
+because games (like Bombjack, Nebulus, Oids, Super Hang-On, Turrican,
+Xenon...) use directly the hardware which Hatari emulates just fine,
+and GEM applications use the correct higher level APIs (AES/VDI) for
+which EmuTOS has implementations.
+
+EmuTOS AES support is somewhat buggy (mouse clicks and dragging
+doesn't always work properly) and VDI & line-A support is slowish.
+Anybody wanting better AES/VDI support should install replacement for
+these, either the free XaAES + fVDI, or commercial solutions like
+NVDI (v2.5 doesn't work with EmuTOS, newer NVDI versions do).
+
+Because (even 192k version of) EmuTOS uses more memory than normal
+TOS, badly written (typically floppy-only) games may blindly overwrite
+EmuTOS memory and it will then crash when the program calls an OS
+function depending on overwritten values.  ST/STE games that work from
+HD and/or with newer TOS versions, should be fine.
+
+Input (e.g. joystick) doesn't work in original (STOS) games that
+access it through other means than XBIOS function Kbdvbase() or by
+hooking into the IKBD interrupt vector.  They use unofficial system
+variables which location depends on the TOS version.  Try fixed
+version of STOS games.
+
+Support for large part of additional TT and Falcon features is missing.
+
+Additionally, older EmuTOS versions (up to v0.9.1) lacked support for
+the (deprecated) line-A graphics functions which are used in many
+free/shareware games (ones done with GFA basic etc).  This isn't an
+issue with new EmuTOS versions.
+
+
+Debugging issues with EmuTOS
+============================
+
+EmuTOS debug output and debug symbols
+-------------------------------------
+
+To get extra debug output from EmuTOS, or to add your own debug
+statements, you need to recompile it from the source, after enabling
+the MIDI debug output in its config.h header file. Then start Hatari
+with the "--midi-out /dev/stderr" option and you will see EmuTOS debug
+output on Hatari's standard error (such as calls to missing OS
+functions).
+
+Some debug output can be gotten also from the pre-built 512k
+EmuTOS images by using Hatari "--natfeats on" option.
+
+By loading the etos512k.sym EmuTOS debug symbols file coming with the
+512k EmuTOS image, you can also ask debugger to "trace cpu_symbols",
+to get trace of all the function calls EmuTOS does.
+
+For smaller EmuTOS versions, there's a script[1] you can use to convert
+the emutos2.map file (produced during EmuTOS build) to a format you
+can load to Hatari debugger with its "symbols" command[2].
+
+[1] http://sourceforge.net/mailarchive/message.php?msg_id=29381777
+[2] http://hg.tuxfamily.org/mercurialroot/hatari/hatari/raw-file/tip/doc/manual.html#Debug_symbols
+
+If you've compiled EmuTOS with AHCC[3] instead of GCC, you can get
+suitable symbols with AHCC "-n" linker flag, or you can use a script
+coming with Hatari (ahcc-symbols-convert.sh) to convert AHCC *.map
+file to a format supported by the Hatari debugger.
+
+[3] AHCC: http://members.chello.nl/h.robbers/
+
+After loading the symbols to the Hatari debugger, disassembling the
+problematic address should provide more clues for the problem.  Or you
+can just look up the program counter value given in the EmuTOS panic
+message from the map file.
+
+
+Debugging OS calls, Line-A usage and panics
+-------------------------------------------
+
+When debugging EmuTOS panics, the best option is to start Hatari with
+"--natfeats on --conout 2" (to get extra debug output and redirect
+EmuTOS panic etc messages to console) and then ask Hatari debugger to
+stop when the program is started:
+-----------
+> b pc=TEXT
+CPU condition breakpoint 1 with 1 condition(s) added:
+pc = TEXT
+> c
+Returning to emulation...
+-----------
+(In above example '>' indicates what you type to debugger.)
+
+Then when the debugger is invoked at program startup, you can ask it to:
+- collect CPU instruction history,
+- break on exceptions that trigger the panic,
+- load symbols and profile what happens as this will
+  provide EmuTOS callstack when debugger is entered, and
+- trace all OS calls and line-A opcodes leading to the panic
+with:
+-----------
+> history on
+> setopt -D
+Exception debugging enabled.
+> symbols etos512k.sym
+> profile on
+> trace os_all
+> b LineAOpcode ! LineAOpcode :trace
+CPU condition breakpoint 2 with 1 condition(s) added:
+LineAOpcode ! LineAOpcode
+-> Track value changes, show value(s) when matched.
+-> Trace instead of breaking, but show still hits.
+> c
+Returning to emulation...
+-----------
+
+With above, when the exception causing the panic triggers the debugger,
+you see EmuTOS callstack and the OS calls & line-A opcodes leading to it,
+and have a panic message on console from which you can copy & paste
+relevant parts.
+
+You can then ask what the register values are at that point and what
+are the CPU instructions leading to it with the "r" and "history"
+commands. Memory state and addresses accessed by the instructions can
+be inspected with the "m" command.
+
+For more info on Hatari debugger usage, see the Hatari manual section
+on it:
+http://hg.tuxfamily.org/mercurialroot/hatari/hatari/raw-file/tip/doc/manual.html#The_debugger
+
+
+Debugging freezes
+-----------------
+
+Hatari profiling support can be used to debug OS freezes.  If EmuTOS
+gets stuck, just profile it for a while and then ask debugger for a
+profile that tells where it's looping.  Then disassemble that part
+with EmuTOS symbols directly in Hatari.
+
+
+EmuTOS free/shareware compatibility lists
+=========================================
+
+The compatibility lists below cater mainly for users who don't have
+Atari HW and therefore won't have (legal) version of commercial Atari
+software and most likely lack motivation to investigate applications
+very deeply (Linux offers better alternatives nowadays for most of
+that). I.e. the lists skip commercial software and concentrate on
+EmuTOS compatibility of freely available games and demos (including
+commercial games that have been released later on for free
+distribution).
+
+Games that are considered good quality & fun, are marked with "*".
+All the listed demos are quite OK. Most demos can be downloaded from:
+	http://pouet.net/
+
+First are listed ST demos, games, graphics & MIDI applications,
+then STE demos, games and music applications, then TT programs
+and last Falcon demos, games and applications.
+
+
+Working Atari ST demos and games
+--------------------------------
+
+Floppy-only games and programs using Line-A need EmuTOS v0.9.3 or
+newer.  For best compatibility with ST emulation, one should use 192kB
+or 256kB version of EmuTOS.
+
+Some old, floppy only games expect certain memory areas occupied by
+EmuTOS, to be over-writable without issues.  Some of them may (by
+blind luck) work with 512k EmuTOS or can be gotten to work by using
+EmuTOS cartridge image (as it uses less memory than normal EmuTOS),
+like this:
+	hatari --tos etos192uk.img --cartridge etoscart.img floppy.img
+
+Mostly the non-working games "Panic" EmuTOS during their startup,
+but it can happen also later on.
+
+
+Demos:
+- 2011 (by Positivity & Sector One, 4kB intro)
+- 4getful (by gwEm, 4KB intro)
+- 4kker (by Checkpoint, 4KB intro)
+- Ambience (by Chaos)
+- Anomaly (by MMJ-Prod)
+- Breath (by Mystic Bytes)
+- Beyond Imagination (by NLC), in GFA basic
+- Calimer-o-demo (by Oxygene)
+- Charts Compilation (by Next)
+- Coast II Coast (by Sector One, 4kB intro)
+- Crisis (by Joska)
+- Cuddly Demos (by CareBears)
+- Darktrip (by Legend), doesn't work with >2MB of RAM
+- Dark Side of the Spoon (by ULM)
+- Death of the Clock Cycles (by Aggression)
+- Dimensio (by Condemned)
+- Eat my bollocks (by Equinox)
+- Fantasia (by Dune & Sector One)
+- Flashback (by Carebears)
+- Flipo (by Oxygene, needs 512k EmuTOS)
+- Frenchies (by Frenchies, 96KB intro)
+- Grafik -und Sounddemo (by Eckhard Kruse), font issues
+- Hallucinations (by Reservoir Gods)
+- If pigs could fly (by Syndicate)
+- Illusion (by Dune)
+- Lots of Dots (by Acid Maker & Friends)
+- Music Disc 1 (by G. Gaubatz)
+- No Cooper (by 1984)
+- O-demo (by Oxygene)
+- Odd Stuff (by Dune & Sector One)
+- Oh no!! more froggies (by Sector One, needs <4MB RAM)
+- Ooh Crikey (by Lost Boys)
+- Outline 2008 invite (by DHS)
+- Outline 2010 invite (by Checkpoint)
+- Overdose (by Aggression)
+- Overdrive (by Phalanx)
+- Pandemonium (by Chaos)
+- Panic (Paolo Simoes)
+- Paradise (by Dune Design)
+- Phaleon Gigademo (by Next), select "fast loader"
+- Posh (by Checkpoint)
+- POV disk 165 (except for EiL 99 invite)
+- Punish your machine (by Delta Force)
+- Rebirth (by MMJ production)
+- RGB plasma (by Omega, panic at return to desktop)
+- Save The Earth (by Defence Force)
+- Second Reality 2013 (by Checkpoint, crash at end)
+- SillyVenture 2k10 & 2k11 (invitros by Mystic Bytes & Aggression)
+- Sommarhack 2011 (invite by DHS)
+- Soundtracker (by Equinox)
+- SoWatt (by CareBears)
+- Sowatt sprite record (rec16e, by Oxygene)
+- ST NICCC 2000 (by Oxygene)
+- ST soccer (intro by Exceptions)
+- Stone tower (by FUN)
+- Superstar! (intro by Positivity/Dma-Sc/Ukko)
+- Suretrip (by Checkpoint, works until overscan screen)
+- Sweety (by DHS)
+- Synergy megademo (by Synergy)
+- Syntax Terror (by Delta Force)
+- Transbeauce II (by BushWacKers)
+- Tut! (by Wildfire)
+- Twelve (by Paulo Simoes)
+- Two in One (by DHS)
+- Virtual (by Equinox)
+- Visualize (by Checkpoint)
+- Vodka demo (by Equinox, needs 512k EmuTOS)
+- Yanartas (by Checkpoint)
+- YmRockerz musicdisks from "Wave upon Wave" to "Seven"
+- Xmas2000 (by Paranoid)
+
+Color toys:
+- Fplanet
+- Schnapfl
+
+Color games:
+- Alterra
+- Archon 4KB
+- Alien Blockade* (quixx)
+- Atax (minor gfx issues)
+- Baby Jo demo (floppy only)
+- Babel demo
+- Beast II demo
+- Bellum*
+- Blaster
+- Blind labyrinth (mouse input has minor issues, needs EmuTOS >v0.9.3)
+- Bloodwych demo (floppy only, needs cartridge image)
+- Bodyshop (line-A bitblits)
+- Bold (floppy only)
+- Bolo demo (floppy only)
+- Bombs Away
+- Bombzai
+- Boom
+- Bugs* (line-A bitblits)
+- Bug-Bash demo
+- Cadaver demos 1 & 2
+- Candyman (line-A bitblits)
+- Captive demo
+- Celica GT4 Rally demo (needs EmuTOS >v0.9.3)
+- Chips Challenge demo
+- ChuChu Rocket* (Lite version for STFM)
+- Civilization demo
+- Clogged Up
+- Cloud Kingdoms demo
+- Conqueror demo*
+- Cops and Robbers Too! (line-A bitblits)
+- Crapman*
+- Creatures demo
+- Cybernetix
+- Dave Munsie games* (shareware)
+  http://www.atarimania.com/list_games_atari-st-munsie-dave_team_950_S_G.html
+- Defender II (playable demo, needs EmuTOS >v0.9.3)
+- Donkey Island (adventure)
+- Dot 2 Dots (for kids)
+- Droid (bootsector has 0 for reserved sectors)*
+- Entombed
+- Fire & Ice demo
+- Flimbo's Quest demo
+- Flip'em* (4KB puzzle)
+- Flood demo
+- French adaptations of classic games:
+  Boulderdash, Demineur, Jewel, Qbert, Sokoban
+- Fuzzball*
+- GodPey (floppy only, by Reservoir Gods)
+- Golden Ax demo
+- Golgafrincham (mod compile with 2-player minigame)
+- Grav*
+- Grav2*
+- Hackman II*
+- Hang About (4KB mountain climbing, joy 0)
+- Happy Worm
+- Hardcore preview
+- Haywire (joy 0)
+- Hector*
+- Helter Skelter demo
+- Hero (RPG)
+- Hexmines*
+- Hunter demo
+- Interphase demo (floppy only)
+- James Pond demo
+- Jetpac
+- Jupiter's Masterdrive demo
+- Killing Game Show demo
+- Knightmare demo (needs <4MB RAM)
+- Laserball 2014
+- Leander demo
+- LeMans (uses line-A)
+- LLamasoft games
+  http://minotaurproject.co.uk/lc-16bit.php
+- Mad Professor demo
+- Magicboy demo (floppy only)
+- Magic Pockets demo
+- Manix preview (needs EmuTOS >v0.9.3)
+- Master Breakout
+- Maze*
+- Megalonmania demo (needs 512k version)
+- Mem* (line-A bitblits)
+- Mig29 Super Fulcrum demo
+- Missile Alert
+- Monkeys and Balloons
+- Monopoly
+- Moonshine Racers demo
+- Nibe 2
+- Nitro demo
+- Nova
+- Oids demo*
+- Out of this Word* (typing game)
+- Panic
+- Paradize games (line-A bitblits):
+  http://paradize.final-memory.org/games.shtml
+- Parasol Stars demo
+- Photon Storm demo
+- Picross ST* (floppy only)
+- Pipemania demo
+- Populous II demo
+- Punt II
+- Pushover demo (3 playable levels, needs EmuTOS >v0.9.3)
+- Puzznic demo (needs floppy in drive A:)
+- Rampage demo
+- Rayoid*
+- Recoil
+- Revenge of the mutant camels (shareware)
+- Robert in the Fire Factory
+- Robin Hood demo
+- Robokid demo
+- Robotz
+- Rockfall*
+- Rolling Ronny demo
+- Rotoplex demo
+- Santafly
+- Sideways
+- Sinister development games (shareware)
+- Snowball Fight
+- Space Crusade demo
+- Spacewar
+- Starball* (shareware)
+- Stormball demo (needs 512k version)
+- Super Pac-Man* (use joystick 0)
+- Super Stario Land demo
+- Superfly (floppy only)
+- Sweeper
+- Tanx*
+- Time Bandit
+- Teserae*
+- The lost world (line-A bitblits)
+- Thunderstrike demo
+- Trace
+- Turrican II demo (bus errors during game)
+- Unheart
+- Video poker (shareware)
+- Videokid demo (floppy only)
+- WalZ (breakout)
+- Warzone
+- Whip Snapper's race
+- Wolf3d (floppy version, Fread()s files opened as write-only)*
+- Yak (4KB gridrunner)
+- Xenon (4KB shooter)
+- Zap (needs 192k build, 2014-05-03 CVS or newer)
+
+Med-rez games:
+- Poker solitaire
+
+GEM games:
+- 4 Gewinnt* (Connect four)
+- Awele v1.02 (in v1.01 menus close immediately after opening)
+- Ballerburg* (bug: mouse-over acts like click)
+- Centi
+- Chess* (works only from floppy)
+- Clicks* (needs wdialog)
+- Corewar (needs EmuTOS >= 0.8.7)
+- Daleks*
+- Dame
+- DBWH
+- Drachen
+- Flipside (fs, othello)
+- Frix
+- Gem_mind
+- GEMcell
+- Gemamigo* (needs EmuTOS >= 0.8.7)
+- Gnuchess
+- Gobang* (needs EmuTOS >= v0.8.6)
+- Halma (needs EmuTOS >= 0.8.7)
+- Invers
+- Isola
+- Kensington
+- Magic Stones* (m_stones: tetris, 2x tetris, columns)
+- Mars (corewars)
+- Mathmaze
+- Megaroid*
+- Mines*
+- Mosaik
+- Nanjing
+- Nethack*
+- Never Mind
+- Orb
+- Pacman
+- Shanghai
+- Ship Combat (battleships, line-A calls)
+- Sixteen (puzzle)
+- Sliders
+- Snake
+- Solitair*
+- Spiegel ("mirrormagic")
+- Stello*
+- ST Concentration*
+- Sudoku*
+- Tartan* (chess)
+- Thor (Othello, unstable)
+- Thrust
+- Tricky yahoo
+- Verrueck (labyrinth)
+- WindowBall (breakout)
+- Wormania
+- zSudoku
+
+Monochrome games:
+- Backgammon    (line-A bitblits under GEM menu)
+- Big Blow      (line-A bitblit)
+- Balloons
+- Bolo          (demo levels, floppy only)
+- Bouncing boubles
+- Columns*      (needs EmuTOS >= 0.8.6, text input positioning issue)
+- CW Puzzle     (line-A bitblit + line & point draw in start)
+- Delta patrol
+- Diamond miner
+- Domino	(line-A bitblit)
+- Emperor       (v1.0 & v1.5)
+- Fun Face      (playable demo)
+- Gluckrad      (line-A bitblit)
+- Go UP
+- HASCS
+- Lasermon      (laser "chess", there's also color version)
+- Lokomotive	(line-A bitblit)
+- MacPan*	(line-A draw/clear sprite)
+- MineFeld	(line-A draw/clear sprite)
+- Minigolf*     (line-A draw/clear sprite)
+- Monkey Business
+- Mr Dash
+- Pipeline*	(line-A line and filled rectangle, works also in color)
+- Pling II	(line-A bitblit, draw/clear sprite and filled rectangle)
+- Poolmono*
+- Punssi
+- Puzzlepuzzle
+- Qix
+- Roll X	(line-A bitblit and set/get pixel)
+- Sbreak*       (by Mark Overmars)
+- Sherlock*     (texts overlap slightly)
+- Skull diggery
+- Slither       (line-A draw/clear sprite, works also in color)
+- Space war     (bug: score missing)
+- Take2*        (line-A bitblit)
+- Wallball
+
+Text games:
+- Advent (Colossal Cave)
+- Eliza
+- Hack
+- Larn
+- Omega
+- Quix
+
+Mono/GEM toys:
+- Biglife*
+- Fishes (line-A line and filled rectangle, works also in color)
+- Mandala
+- Planet (celectial body calculations)
+- Pyro
+- Robugs* (GEM UI, line-A fillrect + spritedraw)
+- ST life
+- Wator (slow)
+- Worm farm
+
+
+Non-working color/mono/GEM Atari ST games
+-----------------------------------------
+
+These are all games that work with normal TOS from Hatari GEMDOS HD
+emulated drive, i.e. aren't hardcoded to run from a floppy.  Floppy
+only games aren't listed as main reason for them not working is larger
+memory usage of EmuTOS (which is too awkward to debug).
+
+Non-working color STOS games (as expected):
+- Balls Up          (mouse input doesn't work)
+- Color Clash*      (fire doesn't work)
+- Dice II           (mouse doesn't work)
+- Mr Dice*          (gets spurious joy input)
+- Nostram           (input doesn't work)
+- Pipetris          (gets spurious joy input)
+- Prehistorik3 demo (input doesn't work)
+- Reflection*       (key input doesn't work)
+- Smash hit         (input doesn't work)
+- Sudoku Universe*  (mouse input doesn't work)
+- Trackball         (mouse doesn't work)
+
+Commercial color game demos:
+- Brain Blaster / The Teller demo (input doesn't work)
+- Cauldron demo     (freezes at during start)
+- Gods demo         (address error after Fclose() on startup, EmuTOS memory overwrite)
+- Flip & Magnose / Up an' Away demo (bus error panic)
+- Hudson Hawk demo  (in game beginning, bus Error reading $ffc230)
+- Striker demo      (input doesn't work)
+
+Free/shareware color games:
+- Douglas Rockmoor  (joystick input doesn't work)
+- Downfall          (fire doesn't work)
+- Entombed          (doesn't show title, copyright, hiscore nor help after v0.8.6,
+                     TOS v2 shows title but not others and sound is wrong)
+- Fokker            (input doesn't work)
+- Japlish           (line-A polygon lines, joystick input doesn't work)
+- Space invaders    (up works as fire, no other input works)
+
+Mono games:
+- Crystal Caves*    (line-A bitblit and draw/clear sprite, input doesn't work)
+- Macrowar          (line-A bitblit, joystick doesn't work)
+- Midimaze*         (joystick doesn't work)
+- Pacballs          (line-A bitblit + panic)
+- Ramses*           (causes panic as it tries to do crazy things with v_hide_c)
+
+GEM games:
+- Abalone   (dragging doesn't work)
+- Anduril   ('h' and 'j' keys don't work)
+- Bombs     (minesweeper, mouse clicks almost never work)
+- Checkers  (dragging doesn't work)
+- Dte       (mouse gets stuck)
+- Invaders* (needs EmuTOS >= 0.8.7, '-' key doesn't work)
+- Minds     (minesweeper, mouse clicks almost never work)
+- Patience* (dragging doesn't work, dialog selection persists)
+- Risky*    (dragging doesn't work)
+- Yams      (minesweeper, mouse clicks don't work)
+- Yukon*    (dragging doesn't work)
+
+
+Atari ST applications (including commercial)
+--------------------------------------------
+
+Working drawing / image viewing programs:
+- Degas Elite, see http://www.youtube.com/watch?v=G4st-x4-BJg (at 16:30)
+- Iffcnv, IFF convertor/viewer
+- ImCon v1.1, image converter/viewer
+- Neochrome master (line-A bitblk, text, line)
+- Photochrome v4 (all buttons don't work)
+- Speed of Light v3.8
+- Spslide, Spec512 viewer
+
+Not working:
+- Spectrum512 (address error on XBios Kbdvbase() return value handling)
+
+Not working video / HD access programs:
+- STVidPlay (expects certain 2-byte HD driver sequence at hdv_rw ($476))
+
+Working MIDI programs:
+- Dr T's KCS v4
+- Dr T's Tiger Cub v2.0
+- EditTrack
+- EZ-Score
+- Henry Cosh's Accompanist
+- Ludwig
+- Miditree (floppy only, press "P" to play Xmas carrols)
+- Music Mouse (uses line-A hline for cursor)
+- Sequencer One
+
+Not working:
+- Cubase lite (guesses etv_timer vector wrong -> panic)
+- FinalCut Pro demo (panic on MIDI play)
+
+MIDI programs are available from Tim's MIDI world:
+	http://tamw.atari-users.net/
+
+
+Working Atari STE programs
+--------------------------
+
+There are not that many STE specific (or even STE enhanced) programs:
+    http://atari-ste.anvil-soft.com/html/archivapps.htm
+
+But following STE specific & enhanced demos, games and apps work
+fine with EmuTOS.
+
+Note: STE emulation needs 256kB version of EmuTOS.  If you use 60Hz
+EmuTOS version (etos256us.img), you may get screen flicker and music
+playback issues with demos and games.
+
+Demos:
+- 1st Step (by Tobe/MJJ Prod)
+- 32768 colors showdown (by Tronic of Effect)
+- 3D full (by Oxygene)
+- Again (by Paradox)
+- AltParty 2008 intro (by Paradox)
+- Amiga Demo 2 (by Oxygene), music disk
+- Antiques (by Dune & Sector Oen)
+- An Cool on STE
+- Another kid story (MMJ prod 2009)
+- Appendix (by DHS)
+- Armada is dead (by Aggression)
+- ATM 10 Years (by Checkpoint)
+- Azed/Jungle demo (by Atari)
+- Beat Demo (by Frontline)
+- Bird Mad Girl Show (by Fraggle's)
+- Birdie (by Zeal)
+- Blue Period (by Paradox)
+- BoingSTE
+- CD-player (by Light)
+- Cernit Trandafir (by DHS)
+- Circus BackSTage (by BlaBLa)
+- Core Flakes (by New Core)
+- Devotion (by Excellence in Art)
+- Dynamite (by Unit 17)
+- E605 (by Light)
+- Ecstacy (by ICE)
+- French Kiss (by DHS)
+- Gobi Toons (by Dune)
+- Grimey (by Reservoir Gods)
+- High Fidelity Dreams (by Aura)
+- HighResMode (by Paradox)
+- Illusion (by Next)
+- Jam-Cols (by ICE)
+- Just Musix 2 (by DHS)
+- Kick my ass'embler (cpp_edit by Paradize & Cerebral Vortex)
+- Lavalamp (by Tobe)
+- Lovetro (by Paradize & Sector One)
+- Madness (by Cream)
+- Massacre (by DHS)
+- Mathematica (by Aura)
+- Maxymizer compo 2006 (by gwEm)
+- Meshake (by Spice Boys)
+- Mind Rewind (by Reservoir Gods)
+- Monogatari (monochrome, by Cerebral Vortex)
+- More or Less Zero (by DHS)
+- MovieSTE (by Tony Barker)
+- Muda (by Live!)
+- Necrosys (by Hemoroids)
+- New Year -94 Intro (by Extream)
+- No Monkey (by Tomchi)
+- Pacemaker (by Paradox), end part works only from floppy image
+- Paracon 6 & 7 remindtros (by Paradox)
+- Power Rise (by Light)
+- Reanimation (by Syntax)
+- Realtime (by MJJ Prod)
+- Riverside (by DHS)
+- RGBeast (by Aggression)
+- SaboTagE Teaser (by Paradox)
+- Save the Earth (by Defence Force)
+- Sinfull Sinuses (by Chronicle)
+- Sierpinski overdose 4K (by GGN), med-rez+blitter only
+- Sommarhack (by DHS)
+- Songs Of The Unexpected (by OUCH)
+- Steroid (Metroid remake demo)
+- STE slideshow (by DHS)
+- STE Wars (by Tony Barker)
+- STePS (by XiA/CPT)
+- STrange RoboTS (by Blabla)
+- Summer Delights (by DHS)
+- Sventure intro (by Paradox)
+- Takeover (by Lamers)
+- TalkTalk2 (by XiA)
+- Techno drugs (by NLC)
+- Tribute to Rainbow TOS
+- Tyranny (by DHS)
+- UFO (by Dune & Sector1)
+- Unbeatable (by Masters of Electric City)
+- Vision (by POV)
+- XiTEC Presentation (by Omega)
+
+Color games:
+- 4K Pacman
+- Aerial Combat 3
+- Alien Blast (demo)
+- Alien Thing preview
+- Atari Scene Card Battle (line-A bitblit)
+- Astrodia
+- Battletris+
+- Blat (line-A bitblit)
+- Boom (screen flashes during scrolling messages)
+- Breakdance (scene game, STOS, needs EmuTOS >v0.9.3)
+- ChuChu Rocket* (full version)
+- Dynabusters+*
+- Frantick
+- Giana Sisters STE rewrite: (needs EmuTOS >v0.9.3)
+  http://www.atari-forum.com/viewtopic.php?f=3&t=26360
+- H Mec 2 (line-A bitblit)
+- Micromachines preview (by .tscc)
+- Mr Boomer (line-A bitblit)
+- No Limit II (shareware pinball)
+- Obsession* (demo of commercial pinball)
+- Operation Garfield
+- Pacman on E
+- Pacmania* STE/overscan rewrite: (needs EmuTOS >v0.9.3)
+  http://www.atari-forum.com/viewtopic.php?f=3&t=24635
+- Power Up
+- R0x (line-A bitblit, screen sync issue)
+- Roger (line-A bitblit)
+- Skulls (shareware "minesweeper")
+- Spy 4k
+- Stardust* (tunnel sequence demo)
+- STEtris
+- STrEet Fighter II (incomplete)
+- Stupid balloon game (joysticks swapped?)
+- Substation* (demo)
+- The chronicles of Omega
+- Tomtar
+- Ultimate Arena v1.3 light (slow with EmuTOS)
+- Utopos* (demo)
+- Wolfenstein3D v0.8a* (a bit unstable)
+- Zero-5 (demo)
+- Zool (demo)
+
+Additionally, also all STe enhanced Paradize games work
+(attackwave, kolmik, mangapuzzle, nwdump, pairs, penta, pokersq,
+pooz, snax, spacebattle), and they all use line-A bitblits:
+	http://paradize.final-memory.org/games.shtml
+
+
+STE (enhanced) music applications:
+- Blipp Blopper
+- EPSS
+- DeskTracker MT
+- Hextracker
+- MaxYMizer
+- MusicPlayer
+- Octalyzer
+- Paula
+- Protracker 2 STE
+- Sirius Player
+
+Most of the non-GEM ST tracker & chip music composer programs work
+also with EmuTOS too (not just STe ones), most even with the 512kB
+EmuTOS version.
+
+
+Non-working Atari STE programs
+------------------------------
+
+Partially working STE demos:
+- 20 years megademo (by Atari scene collective)
+  - issues in some screens
+- 20 years Atari STE megademo (by Paradox)
+  - some screen don't work
+- Ecstasy part A (by Inner Circuit Explorers)
+  - stops in middle, after 3D flight part
+
+Non-working games and music programs:
+- Art for Kids (Bus error at $6, after vro_cpyfm)
+- Bombaman (joystick input doesn't work in game itself):
+  http://homepage.ntlworld.com/kevcallahan/bombaman/
+- Cameleon (line-A bitblit, exits when starting game)
+- Hero (STOS, input doesn't work)
+- Protracker STE, Equinox version, NULL pointer crash on disk ops
+- Zaptastic (freezes at start after few Line-A 7 bitblits)
+
+
+Atari TT programs
+-----------------
+
+Working applications:
+- Mandelbrot playtime (fracplay, uses FPU)
+
+Working demos:
+- 256mbrot, Bragg, Glasstro, Orion-B, Yabt (TT/Falcon intros by ray//.tSCc)
+- 4getful (by gwEm, 4KB intro TT-version)
+- Adebug 3DTT demo (by Brainstorm)
+- CrY image viewer (by .tSCc)
+- Mandelbrot explorer (by .tSCc)
+- TC fish (by .tSCc)
+- TT highres slideshow (by .tSCc)
+- Shiny Bubbles TT (by Xanth FX)
+- XiTEC demos (by Omega)
+  - On exiting Swing EmuTOS panics with privilege violation
+    (TOS bombs and continues)
+
+Working games:
+- Capy (by YesCREW)
+- GEM NetHack v3.4.3 (VDI colors wrong)
+- GEM Slashem v3.3.1 (VDI colors wrong)
+- Oxyd (Falcon version)
+
+Broken programs:
+- PixArt4
+  - colors wrong, clicks to windows down draw anything (on Falcon colors are OK)
+  - http://www.1632systems.co.uk/www/html/Product/pixart.htm
+- OpenTTD:
+  - Needs lots of TT-RAM
+  - EmuTOS doesn't support TT 256 color mode yet
+ (- works on Falcon with FPU)
+
+
+Falcon programs
+---------------
+
+Falcon emulation requires 512kB version of EmuTOS
+(the one shipped with Hatari).
+
+Latest EmuTOS missing:
+- HiColor support
+- XBios functions for DSP
+
+probably explains partly why graphics in many of the demos & games
+look broken, their sound or music doesn't work, or why they freeze at
+startup.
+
+Following Falcon only demos, games and apps work (mostly) fine though.
+
+
+Falcon demos
+............
+
+Working demos:
+- 1600x600
+- 30l coke, needs DSP
+- A Rh Positive 4k (by tSCc), needs DSP
+- Ascii (by Reservoir Gods), disable DSP
+- ATS (by DHS)
+- Autowachen Verboten (by Lazer)
+- Birdshow
+- Bugs from outer space (by Impulse)
+  - bad sound
+- Cebit 93 (by Respectables)
+  - needs WinUAE CPU core
+- Cooler than ever (by ICE)
+  - bad sound
+- DBA Magazine 14 intro (by Lazer)
+- Earth (by Gaston)
+- Falcon Flight (by Opium)
+- Firestarter (by Shadows)
+- Flu 4k (by New Beat), needs FPU
+- Fungle beats (by FUN)
+  - needs WinUAE CPU core
+- Game of Life 4k (by Aggression)
+- Gourand triangles demos (by ray//.tSCc)
+  - these have asm sources!
+- Illusion 64 (by Paranoia)
+  - plasma screen has garbage on right side,
+    end screen at top & bottom
+- Mouse (animation + music)
+- Old Stuff (by Extream)
+- RGB Reine (by New Beat)
+- Rock Solid (by Paranoia)
+- Six Sievert (by tSCc)
+- Snowstorm (by Reservoir Gods), disable DSP
+- Sonolumineszenz (by Avena)
+  - works before v0.9.1, but without sounds
+- Terrorize Your Soul (by tSCc)
+  - fonts and colors aren't right on all screens
+- Videl visions slideshow
+- Virtual City, needs DSP
+  - freezes at exit
+- Warum (by Lazer)
+- Weltchmerz (by Avena)
+- ZZ 9 Plural Z Alpha (by tSCc)
+
+Demos regressed in EmuTOS v0.8.7, working again in EmuTOS >0.9.3:
+- Blue 4k (by New Beat)
+  - Ikbdws() stack usage compared to TOS4 was issue
+
+Partly working demos:
+- Agony (by DNT crew)
+  - freezes after a while
+    XBIOS 109 (Dsp_ExecProg)
+    Bus error bget at 00400000
+- Built-in Obsolescence (by Digital Chaos)
+  - requires WinUAE core
+  - Eventually dies to Dsp Stack Over/underflow  
+- Motion (unfinished demo by Aggression)
+  - only writer screens work
+- Gurkensalat (by Lazer)
+  - freezes after a while
+- Illness (by Escape)
+  - freezes after a while to
+    Bus error lget at 4e700cb9
+- Jesterday (by POV)
+  - Music demo, but no music as it needs DSP
+- Oergs (by Lazer)
+  - Music is bad
+- Schlumpf invtro (by Lazer)
+  - Music is bad
+  - Colors are wrong
+  - Input doesn't work to advance next screen
+- Yepyha (by Toons)
+  - Music is missing (needs DSP?)
+
+Demos that with normal TOS work without DSP HW,
+but don't work with EmuTOS at all:
+- GEM demo (by DHS & AssemSoft):
+  - needs HiColor mode
+- Beams (by .tscc):
+  panic with bus error:
+  M68000 Bus Error reading at address $3b4.
+- Tere Ra'I (by Cerebral Vortex / Dune / Sector One)
+- Unexpected Fun (by Orion_)
+  - these exit as Dsp_Lock() fails
+
+
+Falcon games
+............
+
+Games regressed in EmuTOS v0.8.x (not working anymore):
+- Columns by Deadheart* (demo)
+  -  colors/graphics are wrong
+    (in v0.8.7 screen was just black with music on background)
+- Rave*
+  - colors/graphics are wrong
+    (in v0.8.6, only at actual game lower half)
+- SBM v0.8 (Bomberman clone)*
+  - Bus error wget at 00400000
+
+Games working in EmuTOS >=v0.9.0:
+- Aces High (preview)
+- Blum
+- Cavemania (demo version)
+- Corsair
+- DB 4K
+- Double Bobble 2000* (by Reservoir Gods), disable DSP
+- Dry Egg (needs >4MB RAM)
+- FalcTron
+- Ganymed (start with F1)
+- Heretic (very slow)
+- Hexogan (use number pad)
+- Impulse (Breakout clone)*
+- Lamemine
+- Les Dinosaures (demo)
+- LlamaZap free version (requires joypad, not joystick)
+- Madtris
+- Nibe
+- Running (demo)*
+- Radical Race (demo)*
+- Spice (Defender clone)*
+- Static (Patience by Reservoir Gods), disable DSP
+- Steinbruch
+- Switch
+- Tank Blaster
+- Tautology (by Reservoir Gods)
+- Tautology II* (by Reservoir Gods)
+- Toy Man
+- Willie's Adventure (preview1), disable DSP
+- Willie's Adventure* (preview2)
+
+Games working in EmuTOS >v0.9.0:
+- GEM breakout
+  - problems with clicks
+- Jeu de Poker
+  - needs 640x480@256 VGA mode
+- Landmine (GEM minesweeper)
+- Let's play Shanghai
+  - needs 640x400@256 mode
+- Manga Puzzle
+  - needs 256 color mode
+- Pac Them*
+- Santarun (GEM, slowish)
+- The Ultimate Minesweeper (16-color GEM game)
+  - Problems with clicks
+- Vertical Mayhem(+) (Columns clone)*
+- Zodiax (Falcon "R-type")
+  - No sound (EmuTOS doesn't enabled sound matrix on boot)
+
+Games working in EmuTOS >v0.9.3:
+- Chainz:
+  - vga, press space at start to disable DSP use
+- Jewelz
+  - vga, select hatari mode (F2)
+- Risk 030 demo
+  - Needs 640x480@16 VGA mode
+- Sweety Things
+- Ultimate Arena Falcon edition:
+  - doesn't recognize it's on Falcon -> select "Test"
+  - crashes sometimes
+
+Chainz, Jewels, Sweety and Poker games need to be started from 640x480
+mode, otherwise EmuTOS constrains mouse movements to too small area.
+
+Games working with extra hacks:
+- Bugger, Bunion, SkyFall, Sworm games by Resorvoir Gods:
+  - use an undocumented TOS4 vector for keyboard input instead of accessing
+    kbdvec correctly which use causes EmuTOS to panic.  This can be worked
+    around with the following hack.prg:
+    http://sourceforge.net/mailarchive/message.php?msg_id=26841274
+  - with EmuTOS, enabling DSP freezes the games right at startup
+    (with normal TOS4, DSP is used for background music)
+
+Games that might be possible to get working (they show something
+and/or don't use DSP XBios calls or DSP sound matrix):
+- Block Blizzard preview: stops when loading
+- Bomb Squad: crashes to bus error wget at 00fc0002
+- Chorensha: works except for joystick directions
+- Confusion (demos 1 & 2): title screen doesn't come up
+- Conquest of Elysium: screen with garbage
+- Gold island (demo, vga only), parts of blits are missing
+- Des Lazers & des Hommes: game area graphics are missing
+  (they're rendered with DSP)
+- It's Great (start from st-med rez): mouse doesn't work
+- Masters of Chaos: starts, but then doesn't react to input
+- Men at War: freezes at startup
+- Multibriques: colors are wrong
+- Neurobot: just exits
+- Painium: Intro works, but game itself exits to corrupted desktop
+- Tetrhex: panics after trying to set 256 color mode
+- Tron 2: M68000 Bus Error reading at address $4.
+- TsccTron: M68000 Bus Error reading at address $0.
+
+
+Falcon applications
+...................
+
+Working applications:
+- Aniplayer v2.22
+- BIQ codec / player (by .tscc, has sources)
+- Cecile hard disk (image) driver
+- DSP-debug debugger
+- Godpaint (by Reservoir Gods)
+- ICDraw, .ICO and .IB3 GEM viewer
+- Kronos v1.91 benchmark
+- Rainbow 2 multimedia, needs WinUAE CPU core for MMU
+- Smurf (GEM image viewer)
+
+Partly working applications:
+- Centurbo benchmark:
+  - DSP speed 0, with normal TOS the correct 32Mhz
+   (bogus speed values for FPU & CPU as with normal TOS)
+- Delmpaint (GFA)
+   - some draw operations do black on black
+   - file selector in wrong size if program is started
+     from some other resolution than 320x200@256
+- Escape paint (GEM)
+  - Icons don't show in image operations window, and their
+    places are inverted on mouse-over, image names show in
+    image list window only on highlight, some UI elements
+    flicker
+- Fractal Playground
+  - DSP needs to be disabled, keyboard input doesn't work
+- Whip! (virtual light machine)
+  - Cursor is frozen unless DSP is disabled,
+    non-DSP effects work
+- Winrec (direct to disk GEM audio recorder/effects)
+  - Starts fine and GUI works, but I didn't try recording,
+    may actually work fine
+
+Broken applications:
+- AceMidi demo (softsynth sounds need DSP)
+  - freezes after loading sound bank
+- AceTracker:
+  - exits after starting
+- Centview (GEM image viewer)
+  - For JPG images, requires running jpegd.prg first
+  - Says "Ce fichier n'a pu etre ouvert"
+- DSPdit (by .tscc)
+  - panic with bus error
+- FalcAMP (GEM)
+  - buttons aren't drawn in window 
+  - complains about DSP
+- FlaySID
+  - says "cannot connect with DSP matrix" when playing
+    (has no sound with Hatari even with real TOS)
+- Flextracker
+  - black screen after pressing space at startup at Dsp_LoadProg()
+  - Needs WinUAE Hatari CPU core (with normal TOS)
+- Gemplay v1.49, v1.92 and v1.95
+  - Says "needs Falcon 030 to run"
+- Indypaint
+  - cursor moves, but screen is black, F1-F4 keys don't work
+  - needs HiColor mode
+- MP2 player:
+  - Says that DSP and audio subsystem are already in use
+  - When playing is forced, there's no sound
+  - Time runs in large jumps
+
+
+	- Eero
diff --git a/doc/fr/clavier-exemple.txt b/doc/fr/clavier-exemple.txt
new file mode 100644
index 0000000..62b6ed4
--- /dev/null
+++ b/doc/fr/clavier-exemple.txt
@@ -0,0 +1,36 @@
+# This is an example for a keyboard mapping file that can be used in Hatari
+# by loading it from the keyboard setup dialog.
+#
+# Lines starting with a '#' or with a ';' are comments.
+# All other lines should contain exactly two numbers separated by a comma.
+# The first number is the symbolic PC key code (see the SDL_keysym.h file
+# from the SDL library header files usually in /usr/include/SDL/).
+# The corresponding key will be mapped to the ST key which is specified by
+# second number - the ST scan code of the key (see src/keymap.c in the Hatari
+# sources).
+#
+# Here is an example for a french keymap for the MacBook:
+97,16
+122,17
+113,30
+109,39
+119,44
+38,2
+160,3
+34,4
+39,5
+40,6
+161,7
+163,8
+33,9
+162,10
+164,11
+29,12
+45,13
+94,26
+36,27
+165,40
+44,50
+59,51
+58,52
+61,53
diff --git a/doc/fr/hatari.1 b/doc/fr/hatari.1
new file mode 100644
index 0000000..6a02a70
--- /dev/null
+++ b/doc/fr/hatari.1
@@ -0,0 +1,277 @@
+.\" Hey, EMACS: -*- nroff -*-
+.\" First parameter, NAME, should be all caps
+.\" Second parameter, SECTION, should be 1-8, maybe w/ subsection
+.\" other parameters are allowed: see man(7), man(1)
+.TH "HATARI" "1" "2008-03-14" "Hatari" ""
+.\" Please adjust this date whenever revising the manpage.
+
+.SH "NAME"
+Hatari \- emulateur Atari ST(e)
+.SH "SYNOPSIS"
+.B hatari
+.RI  [options]
+.RI  [diskimage]
+.SH "DESCRIPTION"
+Hatari est un emulateur d'Atari ST(e) pour Linux, FreeBSD, BeOS ainsi
+que tout systemes d'exploitation supportant la bibliotheque SDL.
+.PP
+Avec Hatari vous pouvez lancer des jeux, demos ou des applications
+ecrites pour l'Atari ST ou STE.
+Il supporte egalement les images de disquettes les plus couramment
+utilisees a savoir *.st et *.msa. Il permet aussi l'emulation de
+disque dur.
+.PP
+Pour lancer l'emulateur une image ROM du TOS est requise. EmuTOS
+est une implementation libre du TOS fournie avec Hatari.
+Malheureusement cette derniere n'est pas entierement compatible avec
+le TOS original donc certains programmes risquent de ne pas
+fonctionner correctement. Pour cela, il est recommande d'utiliser
+une ROM TOS issue d'un veritable Atari.
+.SH "OPTIONS"
+Les options sont classées en sous catégories:
+.SH "Options générale"
+.TP
+.B \-h, \-\-help
+affiche les options de la ligne de commande
+.TP
+.B \-v, \-\-version
+affiche les informations sur la version
+.TP 
+.B \-\-confirm-quit 
+Whether Hatari confirms quitting
+.TP
+.B \-c, \-\-configfile 
+utilise un fichier nomme explicitement comme fichier de configuration
+en lieu et place du ~/.hatari/hatari.cfg
+.SH "Options d'écran
+.TP
+.B \-\-monitor 
+selectionne le type de moniteur (x = mono/rgb/vga/tv)
+.TP
+.B \-f, \-\-fullscreen
+demarre l'emulateur en mode plein ecran
+.TP
+.B \-w, \-\-window
+demarre l'emulateur en mode fenetre
+.TP
+.B \-z, \-\-zoom 
+agrandir les petites résolutions (1=non, 2=oui)
+.TP
+.B \-\-frameskips 
+Saute  images apres chaque image affichees pour accelerer l'emulation
+(0 <= x <= 8)
+.TP 
+.B \-\-borders 
+Show screen borders (for overscan demos etc)
+.TP
+.B \-\-spec512 
+Hatari uses this threshold to decide when to render a screen with
+the slower but more accurate Spectrum512 screen conversion functions
+(0 <= x <= 512, 0=disable)
+.TP
+.B \-\-bpp 
+Force given internal bitdepth (x=8/16/32, x=0 for autodetection).
+8-bit color depth may be useful for older host computers
+.SH "Options de VDI"
+.TP
+.B \-\-vdi\-planes 
+utilise une resolution VDI etendue avec une profondeur de bit de 
+(x = 1, 2 or 4)
+.TP
+.B \-\-vdi\-width 
+utilise une resolution VDI etendue avec une largeur de  (384 <= w <= 1024)
+.TP
+.B \-\-vdi\-height 
+utilise une resolution VDI etendue avec une hauteur de  (200 < h <= 768)
+.SH "Options d'interface"
+.TP
+.B \-j, \-\-joystick 
+emule le joystick ST sur le  0 ou 1 avec le clavier
+.TP
+.B \-\-printer 
+active le support de l'imprimante et ecrit les donnees dans le fichier 
+.TP
+.B \-\-midi 
+active la sortie MIDI experimentale vers un fichier mentionne par un nom
+.TP
+.B \-\-rs232 
+active l'emulation experimentale du RS232 via un fichier/device
+nomme explicitement
+.SH "Options des disques"
+.TP
+.B \-d, \-\-harddrive 
+utilise  comme un disque dur emule
+.TP
+.B \-\-acsi 
+emule un disque dur ACSI avec un fichier image 
+.TP
+.B \-\-fastfdc 
+accelere l'emulation du FDC (peut entrainer des erreurs dans certains jeux ou demos)
+.SH "Options de mémoire"
+.TP
+.B \-s, \-\-memsize 
+fixe une quantite de memoire pour la RAM emulee, x = 1 a 14 MiB,
+ou 0 pour 512 Ko
+.TP
+.B \-t, \-\-tos 
+specifie une image ROM TOS a utiliser
+.TP
+.B \-\-cartridge 
+utilise une image ROM de cartouche  (fonctionne uniquement si
+l'emulation de disque dur et VDI etendue sont desactivee)
+.TP 
+.B \-\-memstate 
+Load memory snap-shot 
+.SH "Option du processeur"
+.TP
+.B \-\-cpulevel 
+specifie un CPU (680x0) a utiliser (TOS 2.06 uniquement!!)
+.TP 
+.B \-\-cpuclock 
+Set the CPU clock (8, 16 or 32 Mhz)
+.TP
+.B \-\-compatible 
+utilise le mode de compatibilite plus fidele mais plus lent
+que le mode 68000
+.SH "Options diverses du système"
+.TP
+.B \-\-machine 
+selectionne un type de machine (x = st, ste, tt ou falcon)
+.TP
+.B \-\-blitter 
+active l'emulation du blitter
+.TP
+.B \-\-dsp 
+emulation du DSP du Falcon (x = aucune, factice ou emulee)
+.TP
+.B \-\-sound 
+Régle le son (x=off/low/med/hi)
+.TP
+.B \-\-keymap 
+charge un fichier de refinition du clavier de 
+.SH "Options de déboguer"
+.TP
+.B \-D, \-\-debug
+active le deboggueur integre
+.TP
+.B \-\-log 
+Sauvegarde le rapport vers le fichier  (peut aussi etre "stdout" ou
+"stderr")
+.TP
+.B \-\-trace 
+Activate debug traces, see \-\-trace help for tracing options
+
+.SH "COMMANDS"
+
+Les touches de raccourcis peuvent etre parametrees dans le fichier
+de configurations.
+Par defaut, les parametres sont:
+.TP
+.B AltGr + a
+enregistre l'animation
+.TP
+.B AltGr + g
+fait une capture d'ecran
+.TP
+.B AltGr + i
+touche patron: quitte le mode plein ecran et met la fenetre en icone
+.TP
+.B AltGr + j
+active l'emulation joystick via les touches de directions
+.TP
+.B AltGr + m
+(active/desactive) la souris dans la fenetre
+.TP
+.B AltGr + r
+eteint le ST (a chaud)
+.TP
+.B AltGr + c
+eteint le ST a froid (comme le bouton original d'allumage)
+.TP
+.B AltGr + s
+active/desactive le son
+.TP
+.B AltGr + q
+quitte l'emulateur
+.TP
+.B AltGr + x
+change la vitesse normale/maximum
+.TP
+.B AltGr + y
+active/desactive l'enregistrement du son
+.TP
+.B AltGr + k
+sauvegarde l'etat de la memoire
+.TP
+.B AltGr + l
+restaure l'etat de la memoire
+.TP
+.B F11
+change le mode entre plein ecran et fenetre
+.TP
+.B F12
+active les commandes GUI de Hatari
+.br
+Vous pouvez avoir besoin de tenir la touche SHIFT en mode fenetre
+.TP
+.B Pause
+Ouvrira le deboggueur, s'il etait active avec l'option \-\-debug
+
+.SH Clavier d'Atari ST emule
+Toutes les autres touches du clavier PC agissent comme celles de Atari ST
+donc si vous appuyez sur ESPACE sur votre PC il en resultera sur
+le clavier d'Atari ST un appuis sur la touche ESPACE. Les touches suivantes
+ont une signification speciales :
+.TP
+.B  Alt
+Agira comme la touche ALTERNATE du clavier ST
+.TP
+.B  left Ctrl
+Agira comme la touche CONTROL du clavier ST
+.TP
+.B  Page Up
+Emulera la touche HELP du clavier ST
+.TP
+.B  Page Down
+Emulera la touche UNDO du clavier ST
+.PP
+.B AltGr
+Agira comme
+.B Alternate
+tel sauf si vous appuyez sur les touches speciales d'Hatari.
+
+La touche
+.B right Ctrl
+est utilisee comme le bouton feu d'un joystick emule
+que vous aurez active precedement par l'emulation du joystick via
+les touches du clavier.
+
+Le touche de directions agiront comme les touches de directions sur
+l'Atari ST tant que l'emulation du joystick par le clavier est inactive.
+.SH "VOIR AUSSI"
+La documentation originale du programme, habituellement
+en /usr/share/doc/.
+.PP
+La page d'accueil d'Hatari : http://hatari.tuxfamily.org/
+
+.SH "FICHIERS"
+.TP
+/etc/hatari.cfg (ou /usr/local/etc/hatari.cfg)
+le fichier de configuration global d'Hatari
+.TP
+~/.hatari/hatari.cfg
+Le fichier de configuration de l'utilisateur personnel
+d'Hatari
+.TP
+tos.img
+L'image ROM du TOS qui sera charge a partir du repertoire de donnees d'Hatari
+si aucun argument n'est specifie sur la ligne de commande ou dans le fichier
+de configuration.
+
+.SH "AUTEURS"
+Cette page du manuel a ete ecrite par Marco Herrn ,
+pour le projet Debian et modifiee par la suite par Thomas Huth pour les
+versions plus recentes d'Hatari
+
+.SH "TRADUCTEUR"
+Benoît TUDURI 
diff --git a/doc/hatari.1 b/doc/hatari.1
new file mode 100644
index 0000000..bd872bb
--- /dev/null
+++ b/doc/hatari.1
@@ -0,0 +1,647 @@
+.\" Hey, EMACS: -*- nroff -*-
+.\" First parameter, NAME, should be all caps
+.\" Second parameter, SECTION, should be 1-8, maybe w/ subsection
+.\" other parameters are allowed: see man(7), man(1)
+.TH "HATARI" "1" "2014-05-08" "Hatari" ""
+.\" Please adjust this date whenever revising the manpage.
+
+.SH "NAME"
+hatari \- Atari ST/STE/TT/Falcon emulator
+
+.SH "SYNOPSIS"
+.B hatari
+.RI  [options]
+.RI  [directory|diskimage|program]
+
+.SH "DESCRIPTION"
+Hatari is an Atari ST/STE/TT/Falcon emulator for Linux, FreeBSD, BeOS and
+other Systems which are supported by the SDL library.
+.PP
+With hatari one can run games, demos or applications written for Atari
+ST, STE or Falcon.  Atari TT support is experimental.  Hatari supports
+the commonly used *.st and *.msa disk images and hard disk emulation.
+.PP
+To run the emulator a TOS ROM image is needed. EmuTOS, a free
+implementation of TOS is shipped with hatari. Since it is not yet
+fully compatible with the original TOS, some programs won't run
+correctly with it. Because of this it is recommended to use a TOS
+ROM from a real Atari.
+.PP
+As an argument one can give either a name of a directory that should
+be emulated as a virtual GEMDOS hard disk, a floppy disk image or an
+Atari program that should be autostarted.  In the last case the
+program's directory will be used as the C: drive from where this
+program will be started.
+.PP
+Booting will be done from the disk image or directory that's given
+last on the command line as an option or the argument (and which
+corresponds to A: or C:). If you want to give floppy image name with
+an autostarting program name, give it with --disk-a option before the
+program name.
+
+.SH "OPTIONS"
+Hatari options are split into several categories:
+
+.SH "General options"
+.TP 
+.B \-h, \-\-help
+Print command line options and terminate
+.TP 
+.B \-v, \-\-version
+Print version information and terminate
+.TP 
+.B \-\-confirm\-quit 
+Whether Hatari confirms quitting
+.TP 
+.B \-c, \-\-configfile 
+Read additional configuration values from , these
+override values read from the global and user configuration
+files
+.TP
+.B \-k, \-\-keymap 
+Load keyboard mapping from 
+.TP 
+.B \-\-fast\-forward 
+On fast machine helps skipping (fast forwarding) Hatari output
+
+.SH "Common display options"
+.TP 
+.B \-m, \-\-mono
+Start in monochrome mode instead of color
+.TP 
+.B \-\-monitor 
+Select monitor type (x = mono/rgb/vga/tv)
+.TP 
+.B \-f, \-\-fullscreen
+Start the emulator in fullscreen mode
+.TP 
+.B \-w, \-\-window
+Start the emulator in windowed mode
+.TP 
+.B \-\-grab
+Grab mouse (also) in windowed mode
+.TP 
+.B \-\-borders 
+Show ST/STE/Falcon screen borders (for low/med resolution overscan demos)
+.TP 
+.B \-\-frameskips 
+Skip  frames after each displayed frame to accelerate emulation
+(0=disabled, >4 uses automatic frameskip with given value as maximum)
+.TP
+.B \-\-slowdown 
+Slow down emulation by factor of x (used as multiplier for VBL wait time)
+.TP
+.B \-\-mousewarp 
+To keep host mouse better in sync with Atari mouse pointer, center it
+to Hatari window on cold reset and resolution changes
+.TP
+.B \-\-statusbar 
+Show statusbar (with floppy leds etc etc)
+.TP 
+.B \-\-drive\-led 
+Show overlay drive led when statusbar isn't shown
+.TP
+.B \-\-max\-width 
+Preferred / maximum window width for borders / zooming
+.TP
+.B \-\-max\-height 
+Preferred / maximum window height for borders / zooming
+.TP
+.B \-\-bpp 
+Force internal bitdepth (x = 8/15/16/32, 0=disable)
+
+.SH "ST/STE specific display options"
+.TP
+.B \-\-desktop\-st 
+Whether fullscreen mode uses desktop resolution to avoid: messing
+multi-screen setups, several seconds delay needed by LCD monitors
+resolution switching and the resulting sound break. As Hatari ST/E
+display code doesn't support zooming (except low-rez doubling), it
+doesn't get scaled (by Hatari or monitor) when this is enabled.
+Therefore this is mainly useful only if you suffer from the described
+effects, but still want to grab mouse and remove other distractions
+from the screen just by toggling fullscreen mode. (disabled by default)
+.TP 
+.B \-\-spec512 
+Hatari uses this threshold to decide when to render a screen with
+the slower but more accurate Spectrum512 screen conversion functions
+(0 <= x <= 512, 0=disable)
+.TP 
+.B \-z, \-\-zoom 
+Zoom (double) low resolution (1=no, 2=yes)
+
+.SH "TT/Falcon specific display options"
+Zooming to sizes specified below is internally done using integer scaling
+factors. This means that different Atari resolutions may show up with
+different sizes, but they are never blurry.
+.TP 
+.B \-\-desktop 
+Whether to use desktop resolution on fullscreen to avoid issues
+related to resolution switching. Otherwise fullscreen will use
+a resolution that is closest to the Hatari window size.
+(enabled by default)
+.TP
+.B \-\-force\-max 
+Hatari window size is forced to specified maximum size and black borders
+used when Atari resolution doesn't scale evenly to it.  This is most
+useful when recording videos of Falcon demos that change their
+resolution. (disabled by default)
+.TP
+.B \-\-aspect 
+Whether to do monitor aspect ratio correction (enabled by default)
+
+.SH "VDI options"
+.TP
+.B \-\-vdi 
+Whether to use VDI screen mode.  Doesn't work with TOS v4.
+TOS v3 memory detection isn't compatible with larger VDI modes
+(i.e. you need to skip the detection at boot)
+.TP
+.B \-\-vdi\-planes 
+Use extended VDI resolution with bit depth  (x = 1, 2 or 4)
+.TP
+.B \-\-vdi\-width 
+Use extended VDI resolution with width  (320 < w <= 1280)
+.TP
+.B \-\-vdi\-height 
+Use extended VDI resolution with height  (200 < h <= 960)
+
+.SH "Screen capture options"
+.TP
+.B \-\-crop 
+Remove statusbar from the screen captures
+.TP
+.B \-\-avirecord
+Start AVI recording.  Note: recording will automatically
+stop when emulation resolution changes.
+.TP
+.B \-\-avi\-vcodec 
+Select AVI video codec (x = bmp/png).  PNG compression can
+be \fImuch\fP slower than using the uncompressed BMP format,
+but uncompressed video content takes huge amount of space.
+.TP
+.B \-\-png\-level 
+Select PNG compression level for AVI video (x = 0-9).
+Both compression efficiency and speed depend on the compressed
+screen content. Highest compression level (9) can be \fIreally\fP
+slow with some content. Levels 3-6 should compress nearly as well
+with clearly smaller CPU overhead.
+.TP
+.B \-\-avi\-fps 
+Force AVI frame rate (x = 50/60/71/...)
+.TP
+.B \-\-avi\-file 
+Use  to record AVI
+
+.SH "Devices options"
+.TP 
+.B \-j, \-\-joystick 
+Emulate joystick with cursor keys in given port (0-5)
+.TP 
+.B \-\-joy 
+Set joystick type (none/keys/real) for given port
+.TP 
+.B \-\-printer 
+Enable printer support and write data to 
+.TP 
+.B \-\-midi\-in 
+Enable MIDI support and write MIDI data to 
+.TP 
+.B \-\-midi\-out 
+Enable MIDI support and read MIDI data from 
+.TP 
+.B \-\-rs232\-in 
+Enable serial port support and use  as the input device
+.TP 
+.B \-\-rs232\-out 
+Enable serial port support and use  as the output device
+
+.SH "Floppy drive options"
+.TP
+.B \-\-drive\-a 
+Enable/disable drive A (default is on)
+.TP
+.B \-\-drive\-b 
+Enable/disable drive B (default is on)
+.TP
+.B \-\-drive\-a\-heads 
+Set number of heads for drive A (1=single sided, 2=double sided)
+.TP
+.B \-\-drive\-b\-heads 
+Set number of heads for drive B (1=single sided, 2=double sided)
+.TP
+.B \-\-disk\-a 
+Set disk image for floppy drive A
+.TP
+.B \-\-disk\-b 
+Set disk image for floppy drive B
+.TP 
+.B \-\-fastfdc 
+speed up FDC emulation (can cause incompatibilities)
+.TP
+.B \-\-protect\-floppy 
+Write protect floppy image contents (on/off/auto). With "auto" option
+write protection is according to the disk image file attributes
+
+.SH "Hard drive options"
+.TP
+.B \-d, \-\-harddrive 
+Emulate harddrive partition(s) with  contents.  If directory
+contains only single letter (C-Z) subdirectories, each of these
+subdirectories will be treated as a separate partition, otherwise the
+given directory itself will be assigned to drive "C:". In the multiple
+partition case, the letters used as the subdirectory names will
+determine to which drives/partitions they're assigned. If  is
+an empty string, then harddrive's emulation is disabled
+.TP
+.B \-\-protect\-hd 
+Write protect harddrive  contents (on/off/auto). With "auto" option
+the protection can be controlled by setting individual files attributes
+as it disables the file attribute modifications for the GEMDOS hard disk
+emulation
+.TP
+.B \-\-gemdos\-case 
+Specify whether new dir/filenames are forced to be in upper or lower case
+with the GEMDOS HD emulation. Off/upper/lower, off by default
+.TP
+.B \-\-gemdos\-conv 
+Whether GEMDOS file names with 8-bit (non-ASCII) characters are
+converted between Atari and host character sets. On Linux, host file
+name character set is assumed to be UTF-8. This option is disabled by
+default, in case you've transferred files from Atari machine without
+proper file name conversion (e.g. by zipping them on Atari and
+unzipping on PC).
+.TP
+.B \-\-acsi =
+Emulate an ACSI hard disk with given BUS ID (0-7) using image .
+If just filename is given, it's assigned to BUS ID 0.
+.TP 
+.B \-\-ide\-master 
+Emulate an IDE master hard disk with an image 
+.TP 
+.B \-\-ide\-slave 
+Emulate an IDE slave hard disk with an image 
+
+.SH "Memory options"
+.TP 
+.B \-\-memstate 
+Load memory snap-shot 
+.TP 
+.B \-s, \-\-memsize 
+Set amount of emulated ST RAM, x = 1 to 14 MiB, or 0 for 512 KiB
+.TP
+.B \-s, \-\-ttram 
+Set amount of emulated TT RAM, x = 0 to 256 MiB (in 4MB steps)
+
+.SH "ROM options"
+.TP 
+.B \-t, \-\-tos 
+Specify TOS ROM image to use
+.TP 
+.B \-\-patch\-tos 
+Use this option to enable/disable TOS ROM patching. Experts only! Leave
+this enabled unless you know what you are doing!
+.TP 
+.B \-\-cartridge 
+Use ROM cartridge image  (only works if GEMDOS HD emulation and
+extended VDI resolution are disabled)
+
+.SH "CPU options"
+.TP 
+.B \-\-cpulevel 
+Specify CPU (680x0) to use (use x >= 1 with EmuTOS or TOS >= 2.06 only!)
+.TP 
+.B \-\-cpuclock 
+Set the CPU clock (8, 16 or 32 Mhz)
+.TP 
+.B \-\-compatible 
+Use a more compatible, but slower 68000 CPU mode with
+better prefetch accuracy and cycle counting
+
+.SH "Misc system options"
+.TP 
+.B \-\-machine 
+Select machine type (x = st, ste, tt or falcon)
+.TP 
+.B \-\-blitter 
+Enable blitter emulation (ST only)
+.TP 
+.B \-\-dsp 
+Falcon DSP emulation (x = none, dummy or emu, Falcon only)
+.TP 
+.B \-\-timer\-d 
+Patch redundantly high Timer-D frequency set by TOS.  This about doubles
+Hatari speed (for ST/e emulation) as the original Timer-D frequency causes
+most of the interrupts.
+.TP
+.B \-\-fast\-boot 
+Patch TOS and initialize the so-called "memvalid" system variables to by-pass
+the memory test of TOS, so that the system boots faster.
+.TP
+.B \-\-rtc 
+Enable real-time clock
+
+.SH "Sound options"
+.TP 
+.B \-\-mic 
+Enable/disable (Falcon only) microphone
+.TP 
+.B \-\-sound 
+Sound frequency: 6000-50066. "off" disables the sound and speeds up
+the emulation. To prevent extra sound artifacts, the frequency should be
+selected so that it either matches evenly with the STE/TT/Falcon sound
+DMA (6258, 12517, 250033, 50066 Hz) or your sound card frequencies
+(11025, 22050, 44100 or 6000...48000 Hz).  Check what your sound card
+supports.
+.TP 
+.B \-\-sound\-buffer\-size 
+SDL's sound buffer size: 10-100, or 0 to use default buffer size.
+By default Hatari uses an SDL buffer size of 1024 samples, which
+gives approximatively 20-30 ms of sound depending on the chosen sound
+frequency. Under some OS or with not fully supported sound card, this
+default setting can cause a bigger delay at lower frequency (nearly 0.5 sec).
+In that case, you can use this option to force the size of the sound
+buffer to a fixed number of milliseconds of sound (using 20 is often
+a good choice if you have such problems). Most users will not need this option.
+.TP 
+.B \-\-sound\-sync 
+The emulation rate is nudged by +100 or 0 or \-100 micro-seconds on occasion.
+This prevents the sound buffer from overflowing (long latency and
+lost samples) or underflowing (short latency and repeated samples).
+The emulation rate smoothly deviates by a maximum of 0.58% until
+synchronized, while the emulator continuously generates every sound
+sample and the crystal controlled sound system consumes every sample.
+.br
+(on|off, off=default)
+.TP 
+.B \-\-ym\-mixing 
+Select a method for mixing the three YM2149 voice volumes together.
+"model" uses a mathematical model of the YM voices,
+"table" uses a lookup table of audio output voltage values measured
+on STF and "linear" just averages the 3 YM voices.
+
+.SH "Debug options"
+.TP
+.B \-W, \-\-wincon
+Open console window (Windows only)
+.TP 
+.B \-D, \-\-debug
+Toggle whether CPU exceptions invoke the debugger
+.TP 
+.B \-\-debug\-except 
+Specify which exceptions invoke debugger, see
+.B \-\-debug\-except help
+for available (comma separated) exception flags.
+.TP 
+.B \-\-bios\-intercept
+Toggle XBios command parsing. Allows Atari programs to use all Hatari
+functionality and change Hatari state through Hatari specifit
+XBios(255) calls. XBios(20) printscreen calls produce also Hatari
+screenshots.
+.TP
+.B \-\-conout 
+Enable console (xconout vector functions) output redirection for given
+ to host terminal.  Device 2 is for the (CON:) VT52 console,
+which vector function catches also EmuTOS panic messages and MiNT
+console output, not just normal BIOS console output.
+.TP
+.B \-\-disasm 
+Set disassembly options.  'uae' and 'ext' select the dissasembly engine
+to use, bitmask sets output options for the external disassembly engine
+and 'help' lists them.
+.TP 
+.B \-\-natfeats 
+Enable/disable (basic) Native Features support.
+E.g. EmuTOS uses it for debug output.
+.TP
+.B \-\-trace 
+Activate debug traces, see
+.B \-\-trace help
+for available (comma separated) tracing flags
+.TP
+.B \-\-trace\-file 
+Save trace output to  (default=stderr)
+.TP
+.B \-\-parse 
+Parse/execute debugger commands from 
+.TP
+.B \-\-saveconfig
+Save Hatari configuration and exit. Hatari UI needs Hatari configuration
+file to start, this can be used to create it automatically.
+.TP
+.B \-\-no\-parachute
+Disable SDL parachute to get Hatari core dumps. SDL parachute is enabled
+by default to restore video mode in case Hatari terminates abnormally
+while using non-standard screen resolution.
+.TP
+.B \-\-control\-socket 
+Hatari reads options from given socket at run-time
+.TP
+.B \-\-log\-file 
+Save log output to  (default=stderr)
+.TP
+.B \-\-log\-level 
+Log output level (x=debug/todo/info/warn/error/fatal)
+.TP
+.B \-\-alert\-level 
+Show dialog for log messages above given level
+.TP
+.B \-\-run\-vbls 
+Exit after X VBLs
+
+.SH "INPUT HANDLING"
+Hatari provides special input handling for different purposes.
+
+.SH "Emulated Atari ST joystick"
+Joystick can be emulated either with keyboard or any real joystick
+supported by your kernel / SDL library.  First joystick button
+acts as FIRE, second as SPACE key.
+
+.SH "Emulated Atari ST mouse"
+Middle button mouse click is interpreted as double click, this
+is especially useful in Fast Forward mode.
+.PP
+Mouse scrollwheel will act as cursor up and down keys.
+
+.SH "Emulated Atari ST keyboard"
+Keys on the keyboard act as the normal Atari ST keys so pressing SPACE
+on your PC will result in an emulated press of the SPACE key on the
+ST. How the PC keys are mapped to Atari key codes, can be changed
+with keyboard config file (-k option).
+.PP
+The following keys have special meanings:
+.TP
+.B  Alt
+will act as the ST's ALTERNATE key
+.TP
+.B  left Ctrl
+will act as the ST's CONTROL key
+.TP
+.B  Page Up
+will emulate the ST's HELP key
+.TP
+.B  Page Down
+will emulate the ST's UNDO key
+.PP
+.B AltGr
+will act as
+.B Alternate
+as well as long as you do not press it together with a Hatari hotkey
+combination.
+.PP
+The 
+.B right Ctrl
+key is used as the fire button of the emulated joystick when you turn
+on joystick emulation via keyboard. 
+.PP
+The cursor keys will act as the cursor keys on the Atari ST as long as
+joystick emulation via keyboard has been turned off.
+
+.SH "Keyboard shortcuts during emulation"
+The shortcut keys can be configured in the configuration file.
+The default settings are:
+.TP
+.B AltGr + a
+record animation
+.TP
+.B AltGr + g
+grab a screenshot
+.TP
+.B AltGr + i
+boss key: leave full screen mode and iconify window
+.TP
+.B AltGr + m
+(un-)lock the mouse into the window
+.TP
+.B AltGr + r
+warm reset the ST (same as the reset button)
+.TP
+.B AltGr + c
+cold reset the ST (same as the power switch)
+.TP
+.B AltGr + d
+open dialog to select/change disk A
+.TP
+.B AltGr + s
+enable/disable sound
+.TP
+.B AltGr + q
+quit the emulator
+.TP
+.B AltGr + x
+toggle normal/max speed
+.TP
+.B AltGr + y
+enable/disable sound recording
+.TP
+.B AltGr + k
+save memory snapshot
+.TP
+.B AltGr + l
+load memory snapshot
+.TP
+.B AltGr + j
+toggle joystick emulation via cursor keys
+.TP
+.B AltGr + F1
+switch joystick type on joy port 0
+.TP
+.B AltGr + F2
+switch joystick type on joy port 1
+.TP
+.B AltGr + F3
+switch joystick type for joypad A
+.TP
+.B AltGr + F4
+switch joystick type for joypad B
+.TP
+.B F11
+toggle between fullscreen and windowed mode
+.TP
+.B F12 
+activate the hatari options GUI
+.br
+You may need to hold SHIFT down while in windowed mode.
+.TP
+.B Pause
+Pauses the emulation
+.TP
+.B AltGr + Pause
+Invokes the internal Hatari debugger
+
+.SH "Keyboard shortcuts for the SDL GUI"
+There are multiple ways to interact with the SDL GUI.
+.PP
+TAB and cursor keys change focus between UI elements.  Additionally
+Home key moves focus to first item, End key to last one.  Initially
+focus is on default UI element, but focus changes are remembered
+between dialog invocations. Enter and Space invoke focused item. UI
+elements with underlined characters can be invoked directly with Alt +
+key with that character.  Alt + arrow keys will act on arrow buttons.
+.PP
+Most importantly:
+.TP
+.B Options GUI main view
+Enter accepts configuration, ESC cancels it.
+.TP
+.B Options GUI dialogs
+Enter (or End+Enter if focus was moved) returns back to main view.
+.TP
+.B Fileselector
+Page up and down keys scroll the file list.  Enter on focused file
+name selects it.  Enter on OK button accepts the selected file. ESC
+cancels the dialog/selection.
+.TP
+.B Alert dialogs
+Enter accepts and ESC cancels the dialog.
+
+.SH "SEE ALSO"
+The main program documentation, usually in /usr/share/doc/.
+Among other things it contains an extensive usage manual,
+software compatibility list and release notes.
+.PP
+The homepage of hatari: http://hatari.tuxfamily.org/
+.PP
+Other Hatari programs and utilities:
+.br
+.IR hmsa (1),
+.IR zip2st (1),
+.IR atari\-convert\-dir (1),
+.IR atari\-hd\-image (1),
+.IR hatariui (1),
+.IR hconsole (1),
+.IR gst2ascii (1),
+.IR hatari_profile (1)
+
+.SH "FILES AND DIRECTORIES"
+.TP
+/etc/hatari.cfg (or /usr/local/etc/hatari.cfg)
+The global configuration file of Hatari.
+.TP
+~/.hatari/
+The (default) directory for user's personal Hatari files;
+.B hatari.cfg
+(configuration file),
+.B hatari.nvram
+(NVRAM content file),
+.B hatari.sav
+(Hatari memory state snapshot file which Hatari can load/save automatically
+when it starts/exits),
+.B hatari.prn
+(printer output file),
+.B hatari.wav
+(recorded sound output in WAV format),
+.B hatari.ym
+(recorded sound output in YM format).
+.TP
+/usr/share/hatari/ (or /usr/local/share/hatari/)
+The global data directory of Hatari.
+.TP
+tos.img
+The TOS ROM image will be loaded from the data directory of Hatari unless it
+is specified on the command line or the configuration file.
+
+.SH "AUTHOR"
+This manual page was written by Marco Herrn  for the
+Debian project and later modified by Thomas Huth and Eero Tamminen to
+suit the latest version of Hatari.
diff --git a/doc/images/callgraph.png b/doc/images/callgraph.png
new file mode 100644
index 0000000..3a79a68
Binary files /dev/null and b/doc/images/callgraph.png differ
diff --git a/doc/images/callgraph.svg b/doc/images/callgraph.svg
new file mode 100644
index 0000000..d17a714
--- /dev/null
+++ b/doc/images/callgraph.svg
@@ -0,0 +1,715 @@
+
+
+
+
+
+
+profile
+
+Executed instructions
+for badmood-1-frame-CPU.txt
+(Hatari v1.6.2+ (May  4 2013), WinUAE CPU core)
+own cost emphasis (gray bg) & total cost emphasis (red) limit = 2.00%
+nodes which are subroutines and have accurate total costs, have diamond shape
+24 leaf and/or intermediate nodes below 0.20% were removed
+
+N_48100
+
+4.30%
+(own: 0.25%)
+5819
+visplane_tryflush
+(15 calls)
+
+
+N_480B2
+
+4.05%
+(own: 0.05%)
+5486
+flush_visplanes
+(7 calls)
+
+
+N_48100->N_480B2
+
+
+visplane_tryflush+86
+($48156)
+
+
+N_48780
+
+0.98%
+1326
+R_BSPHyperPlane_RHS
+(587 calls)
+
+
+N_48780->N_48780
+
+
+R_BSPHyperPlane_RHS+4
+($48784)
+567 calls
+=96.59%
+
+
+N_48728
+
+0.03%
+46
+R_PopBSPNode
+(23 calls)
+
+
+N_48780->N_48728
+
+
+R_BSPHyperPlane_RHS+18
+($48792)
+3 calls
+=13.04%
+
+
+N_4872E
+
+3.82%
+5170
+R_BSPHyperPlane
+(36 calls)
+
+
+N_48780->N_4872E
+
+
+R_BSPHyperPlane_RHS+24
+($48798)
+11 calls
+=30.56%
+
+
+N_481F8
+
+0.06%
+77
+ssector_node
+(16 calls)
+
+
+N_48780->N_481F8
+
+
+R_BSPHyperPlane_RHS+26
+($4879a)
+6 calls
+=37.50%
+
+
+N_48206
+
+0.41%
+550
+build_ssector
+(15 calls)
+
+
+N_48206->N_48100
+
+
+build_ssector+116
+($4827a)
+
+
+N_482A0
+
+2.04%
+2766
+segment_loop
+(50 calls)
+
+
+N_48206->N_482A0
+
+
+build_ssector+150
+($4829c)
+15 calls
+=30.00%
+
+
+N_4A3E8
+
+0.47%
+630
+process_lighting
+(15 calls)
+
+
+N_48206->N_4A3E8
+
+
+build_ssector+112
+($48276)
+
+
+N_48716
+
+0.07%
+96
+R_RenderBSPNode
+(16 calls)
+
+
+N_48716->N_48728
+
+
+R_RenderBSPNode+16
+($48726)
+16 calls
+=69.57%
+
+
+N_4819C
+
+0.01%
+20
+finish_tree
+(1 calls)
+
+
+N_48BDC
+
+0.63%
+(own: 0.05%)
+857
+get_flat_floor
+(2 calls)
+
+
+N_4819C->N_48BDC
+
+
+finish_tree+64
+($481dc)
+1 calls
+=50.00%
+
+
+N_48B74
+
+0.35%
+(own: 0.08%)
+470
+get_flat_ceiling
+(3 calls)
+
+
+N_4819C->N_48B74
+
+
+finish_tree+40
+($481c4)
+1 calls
+=33.33%
+
+
+N_4879E
+
+0.75%
+1015
+R_BSPHyperPlane_LHS
+(449 calls)
+
+
+N_4879E->N_4879E
+
+
+R_BSPHyperPlane_LHS+4
+($487a2)
+433 calls
+=96.44%
+
+
+N_4879E->N_48728
+
+
+R_BSPHyperPlane_LHS+18
+($487b0)
+4 calls
+=17.39%
+
+
+N_4879E->N_4872E
+
+
+R_BSPHyperPlane_LHS+26
+($487b8)
+8 calls
+=22.22%
+
+
+N_4879E->N_481F8
+
+
+R_BSPHyperPlane_LHS+30
+($487bc)
+4 calls
+=25.00%
+
+
+N_483BA
+
+0.26%
+357
+seg_prelight_done
+(21 calls)
+
+
+N_482A0->N_483BA
+
+
+segment_loop+-498
+($480ae)
+1 calls
+=4.76%
+
+
+N_482A0->N_483BA
+
+
+segment_loop+278
+($483b6)
+20 calls
+=95.24%
+
+
+N_486CC
+
+0.03%
+36
+sector_window
+(36 calls)
+
+
+N_482A0->N_486CC
+
+
+segment_loop+248
+($48398)
+15 calls
+=41.67%
+
+
+N_486D0
+
+0.20%
+270
+seg_invisible
+(50 calls)
+
+
+N_482A0->N_486D0
+
+
+segment_loop+118
+($48316)
+14 calls
+=28.00%
+
+
+N_48728->N_4872E
+
+
+R_PopBSPNode+2
+($4872a)
+17 calls
+=47.22%
+
+
+N_48728->N_481F8
+
+
+R_PopBSPNode+2
+($4872a)
+6 calls
+=37.50%
+
+
+N_48C74
+
+2.41%
+3264
+stack_visplane_area
+(13 calls)
+
+
+N_48BDC->N_48C74
+
+
+get_flat_floor+90
+($48c36)
+2 calls
+=15.38%
+
+
+N_49C2C
+
+39.97%
+54144
+render_wall_1x1
+(18 calls)
+
+
+N_4872E->N_48780
+
+
+R_BSPHyperPlane+80
+($4877e)
+20 calls
+=3.41%
+
+
+N_4872E->N_4879E
+
+
+R_BSPHyperPlane+80
+($4877e)
+16 calls
+=3.56%
+
+
+N_480B2->N_48BDC
+
+
+flush_visplanes+42
+($480dc)
+1 calls
+=50.00%
+
+
+N_480B2->N_48B74
+
+
+flush_visplanes+62
+($480f0)
+2 calls
+=66.67%
+
+
+N_48B00
+
+3.25%
+(own: 1.69%)
+4401
+get_ssector
+(4 calls)
+
+
+N_480B2->N_48B00
+
+
+flush_visplanes+10
+($480bc)
+
+
+N_494B4
+
+34.82%
+(own: 27.62%)
+47161
+render_flats
+(1 calls)
+
+
+N_494CC
+
+27.56%
+37335
+render_flats_1x1
+(1 calls)
+
+
+N_494B4->N_494CC
+
+
+render_flats+20
+($494c8)
+
+
+N_47438
+
+0.28%
+378
+cache_resource
+(21 calls)
+
+
+N_48B74->N_48C74
+
+
+get_flat_ceiling+86
+($48bca)
+3 calls
+=23.08%
+
+
+N_483BA->N_486CC
+
+
+seg_prelight_done+456
+($48582)
+6 calls
+=16.67%
+
+
+N_48650
+
+0.33%
+450
+sector_wall
+(15 calls)
+
+
+N_483BA->N_48650
+
+
+seg_prelight_done+64
+($483fa)
+
+
+N_48C44
+
+2.28%
+3086
+init_stategroups
+(1 calls)
+
+
+N_486CC->N_486D0
+
+
+sector_window
+36 calls
+=72.00%
+
+
+N_494CC->N_47438
+
+
+render_flats_1x1+62
+($4950a)
+3 calls
+=14.29%
+
+
+N_49438
+
+7.16%
+9701
+stream_texture
+(3 calls)
+
+
+N_494CC->N_49438
+
+
+render_flats_1x1+66
+($4950e)
+
+
+N_486D0->N_482A0
+
+
+seg_invisible+18
+($486e2)
+35 calls
+=70.00%
+
+
+N_486E6
+
+0.21%
+278
+do_ssector
+(15 calls)
+
+
+N_486D0->N_486E6
+
+
+seg_invisible+12
+($486dc)
+
+
+N_4815C
+
+59.72%
+(own: 9.63%)
+80888
+descend_bsp
+(1 calls)
+
+
+N_4815C->N_48716
+
+
+descend_bsp+60
+($48198)
+1 calls
+=6.25%
+
+
+N_48B00->N_48C74
+
+
+get_ssector+100
+($48b64)
+8 calls
+=61.54%
+
+
+N_48650->N_486CC
+
+
+sector_wall+120
+($486c8)
+15 calls
+=41.67%
+
+
+N_486E6->N_48716
+
+
+do_ssector+46
+($48714)
+15 calls
+=93.75%
+
+
+N_49B28
+
+42.19%
+(own: 1.70%)
+57144
+add_wall_segment
+(18 calls)
+
+
+N_486E6->N_49B28
+
+
+do_ssector+20
+($486fa)
+
+
+N_49ACC
+
+2.84%
+3851
+add_partition_segment
+(6 calls)
+
+
+N_486E6->N_49ACC
+
+
+do_ssector+20
+($486fa)
+
+
+N_49BEA
+
+40.49%
+(own: 40.25%)
+54844
+render_wall
+(18 calls)
+
+
+N_49BEA->N_49C2C
+
+
+render_wall+62
+($49c28)
+
+
+N_49BEA->N_47438
+
+
+render_wall+26
+($49c04)
+18 calls
+=85.71%
+
+
+N_47A6C
+
+100.00%
+(own: 0.09%)
+135449
+display_engine
+(1 calls)
+
+
+N_47A6C->N_494B4
+
+
+display_engine+302
+($47b9a)
+
+
+N_47A6C->N_48C44
+
+
+display_engine+286
+($47b8a)
+
+
+N_47A6C->N_4815C
+
+
+display_engine+294
+($47b92)
+
+
+N_491EA
+
+3.04%
+4120
+initialise_freetable
+(2 calls)
+
+
+N_47A6C->N_491EA
+
+
+display_engine+6010
+($491e6)
+
+
+N_49B28->N_49BEA
+
+
+add_wall_segment+186
+($49be2)
+
+
+N_481F8->N_48206
+
+
+ssector_node+12
+($48204)
+
+
+N_481F8->N_4819C
+
+
+ssector_node+2
+($481fa)
+
+
+
diff --git a/doc/images/devices.png b/doc/images/devices.png
new file mode 100644
index 0000000..5cd5cf4
Binary files /dev/null and b/doc/images/devices.png differ
diff --git a/doc/images/fileselector.png b/doc/images/fileselector.png
new file mode 100644
index 0000000..d35e546
Binary files /dev/null and b/doc/images/fileselector.png differ
diff --git a/doc/images/floppydisks.png b/doc/images/floppydisks.png
new file mode 100644
index 0000000..b42a528
Binary files /dev/null and b/doc/images/floppydisks.png differ
diff --git a/doc/images/harddisks.png b/doc/images/harddisks.png
new file mode 100644
index 0000000..a765fc5
Binary files /dev/null and b/doc/images/harddisks.png differ
diff --git a/doc/images/joystick.png b/doc/images/joystick.png
new file mode 100644
index 0000000..8654edf
Binary files /dev/null and b/doc/images/joystick.png differ
diff --git a/doc/images/kcachegrind.png b/doc/images/kcachegrind.png
new file mode 100644
index 0000000..761c5d9
Binary files /dev/null and b/doc/images/kcachegrind.png differ
diff --git a/doc/images/keyboard.png b/doc/images/keyboard.png
new file mode 100644
index 0000000..f8585fa
Binary files /dev/null and b/doc/images/keyboard.png differ
diff --git a/doc/images/main.png b/doc/images/main.png
new file mode 100644
index 0000000..a6753ef
Binary files /dev/null and b/doc/images/main.png differ
diff --git a/doc/images/memory.png b/doc/images/memory.png
new file mode 100644
index 0000000..1c523b0
Binary files /dev/null and b/doc/images/memory.png differ
diff --git a/doc/images/monitor.png b/doc/images/monitor.png
new file mode 100644
index 0000000..1766ce2
Binary files /dev/null and b/doc/images/monitor.png differ
diff --git a/doc/images/newfloppy.png b/doc/images/newfloppy.png
new file mode 100644
index 0000000..30f2ccb
Binary files /dev/null and b/doc/images/newfloppy.png differ
diff --git a/doc/images/screen.png b/doc/images/screen.png
new file mode 100644
index 0000000..cb46745
Binary files /dev/null and b/doc/images/screen.png differ
diff --git a/doc/images/sound.png b/doc/images/sound.png
new file mode 100644
index 0000000..cdb727f
Binary files /dev/null and b/doc/images/sound.png differ
diff --git a/doc/images/system.png b/doc/images/system.png
new file mode 100644
index 0000000..295b430
Binary files /dev/null and b/doc/images/system.png differ
diff --git a/doc/images/tos.png b/doc/images/tos.png
new file mode 100644
index 0000000..4448887
Binary files /dev/null and b/doc/images/tos.png differ
diff --git a/doc/keymap-sample.txt b/doc/keymap-sample.txt
new file mode 100644
index 0000000..8aa3c8c
--- /dev/null
+++ b/doc/keymap-sample.txt
@@ -0,0 +1,22 @@
+# This is an example for a keyboard mapping file that can be used in Hatari
+# by loading it from the keyboard setup dialog.
+#
+# Lines starting with a '#' or with a ';' are comments.
+# All other lines should contain exactly two numbers separated by a comma.
+#
+# The first number is the libSDL symbolic PC key code.
+# See the "--trace keymap" output from Hatari.
+#
+# The corresponding key will be mapped to the ST key which is specified by
+# second number - the ST scan code of the key.  "--trace keymap" output
+# shows the already mapped scan code.
+#
+# tests/keymap/ directory contains programs to discover/test the PC SDL
+# and Atari scan code values.  Hatari's default PC key code -> ST scan
+# code mappings are in src/keymap.c source file.
+#
+# Example: If you want to get the 'y' and 'z' keys right with a german TOS
+# ROM, you can use the following two lines to map the PC keys to the right
+# ST scan codes:
+121,44
+122,21
diff --git a/doc/manual.html b/doc/manual.html
new file mode 100644
index 0000000..325c2ca
--- /dev/null
+++ b/doc/manual.html
@@ -0,0 +1,4309 @@
+
+
+
+  Hatari User's Manual
+  
+  
+  
+  
+  
+  
+  
+
+
+
+
+
Hatari User's Manual

+
+

+Version 1.9.0, September 2015
+

+

+Manual written by: Thomas Huth, Matthias Arndt
+ & Eero Tamminen
+

+

+Hatari on the WWW:
+
+http://hatari.tuxfamily.org/
+
+

+
+
Index

+
+

+
+

+
+
Introduction

+
+
General description

+

+Hatari is an Atari ST, STE, TT and Falcon emulator for Linux, OSX,
+Windows and other Systems which are supported by the SDL library.
+The emulator is open source software and is distributed under the terms of the
+GNU General
+Public License (GPL).
+

+

+The Atari ST was a 16/32 bit computer system which was first released by Atari
+in 1985. Using the Motorola 68000 CPU, it was a very popular computer having
+quite a lot of CPU power at that time. See Appendix B for details on emulation
+in general.
+

+

+Unlike many other Atari ST emulators which try to give you a good
+environment for running GEM applications, Hatari tries to emulate the hardware
+of a ST as close as possible so that it is able to run most of the old ST games
+and demos. Of course you can run normal GEM applications with Hatari, too.
+Recent versions of Hatari even feature STE, Falcon and basic TT emulation.
+

+
+
Features

+
    
+  
  • 68000 - 68040 emulation via the UAE CPU core
+      (68060 and MMU emulation only with the WinUAE CPU core)
    • 
+  
  • ST RAM size variable (from 512kiB up to 14MiB are possible)
    • 
+  
  • TT RAM size variable (from 0 up to 256MiB are possible)
    • 
+  
  • optional cartridge images for the ST ROM port
    • 
+  
  • most of the ST specific hardware
    • 
+  
  • ST Shifter with ST-High, ST-Medium and ST-Low resolutions,
+    overscan effects for all borders in color resolutions
    • 
+  
  • 512 color ST palette
    • 
+  
  • Spec512 mode support for low and medium resolutions
    • 
+  
  • many raster effects 
    • 
+  
  • scaling of low resolutions by factor two
    • 
+  
  • interleaved lines rendering of ST-medium and (scaled) ST-low
+    resolutions for the TV "monitor type"
    • 
+  
  • Blitter chip emulation
    • 
+  
  • PSG YM2149 emulation (soundchip) including STFM samples
    • 
+  
  • Printer port emulation on hardware level (print to file)
    • 
+  
  • RS232 emulation
    • 
+  
  • MIDI input/output/through emulation
    • 
+  
  • Mega ST real time clock
    • 
+  
  • IKBD emulation (keyboard, mouse and joystick) with custom
+    keyboard mapping
    • 
+  
  • joystick emulation via cursor keys and joystick emulation via a
+    connected PC joystick
    • 
+  
  • FDC (floppy disk controller) emulation using floppy disk images
+    in standard formats (*.ST, *.MSA, *.DIM and *.STX)
    • 
+  
  • FDC emulation via the IPF support library for using
+    *.IPF, *.RAW and *.CTR images
    • 
+  
  • support for packed disk images (PkZip and Gzip)
    • 
+  
  • optional write-protection for floppy disk images
    • 
+  
  • ACSI emulation for hard drive support (with basic support for extended
+    host adapter protocol to access disks > 1 GB)
    • 
+  
  • GEMDOS interface driver to mount directories as hard drives
+    with optional write-protection
    • 
+  
  • support for memory snapshots (save whole system state)
    • 
+  
  • driver for extended VDI resolutions
    • 
+  
  • recording of sound as .WAV and .YM files
    • 
+  
  • screenshots in PNG or BMP format
    • 
+  
  • AVI animation capturing with sound
    • 
+  
  • TOS versions 1.00, 1.02, 1.04 and 2.06 (and EmuTOS) can be used in ST mode.
    • 
+

+
+
STE hardware emulation

+
There is support for following additional STE features:

+
    
+  
  • horizontal and vertical hardware fine scrolling
    • 
+  
  • split screen techniques / in-screen video address manipulations
    • 
+  
  • (STE specific) left border opening
    • 
+  
  • 4096 colors STE palette
    • 
+  
  • Stereo DMA sample sound
    • 
+  
  • Microwire/LMC1992 emulation
    • 
+  
  • STE joypads
    • 
+  
  • TOS versions 1.06, 1.62, 2.05 and 2.06 (and EmuTOS) can be used in STE mode.
    • 
+

+
+
Experimental TT hardware emulation

+
There is support for following additional TT features:

+
    
+  
  • TT low/med/high resolution support
    • 
+  
  • ST/TT palette switching and video shifter
    • 
+  
  • RAM up to 14MiB (ST-RAM) and up to 256 MiB (TT-RAM)
    • 
+  
  • Only TOS version 3.06 (and EmuTOS) can be used in TT mode.
    • 
+

+
+
Falcon hardware emulation

+
There is support for following additional Falcon features:

+
    
+  
  • Partial Videl and Videl borders emulation for all Falcon screen modes
    • 
+  
  • Aspect correction and scaling of small resolutions by an integer factor
    • 
+  
  • STE/Falcon palette switching and shifter
    • 
+  
  • Mono/RGB/VGA/TV monitor types
    • 
+  
  • DSP co-processor emulation
    • 
+  
  • RAM up to 14MiB (ST-RAM) and up to 256 MiB (TT-RAM)
    • 
+  
  • Experimental microphone (jack) emulation
    • 
+  
  • Experimental Crossbar sound matrix (ADC (mic & PSG), DAC, DMA, DSP)
+      interconnect emulation + support for the additional DMA sound
+      sample rates
    • 
+  
  • Experimental IDE master and slave emulation for hard drive support
    • 
+  
  • TOS versions 4.00, 4.02, 4.04 and 4.92 (and EmuTOS) can be used in Falcon mode.
    • 
+

+
+
See the developers' doc/todo.txt file
+(included with Hatari sources) for the details on the few remaining
+emulation gaps and the Hatari Atari
+Software Compatibility List for which Atari programs are known
+to be affected by them.

+
+
+
System requirements

+
+
 Hatari currently has the following minimum system requirements:

+
+
+

+In the course of time Hatari has successfully been tested by various people on
+the following systems:
+

+
    
+  
  • Linux/i86 with Kernel 2.4.x and 2.6.x
    • 
+  
  • Linux/PPC with Kernel 2.4.x and 2.6.x
    • 
+  
  • BeOS/i86
    • 
+  
  • Apple Mac OS X on PowerPC and i86
    • 
+  
  • NetBSD 1.6 on i86
    • 
+  
  • NetBSD on a Digital Alpha
    • 
+  
  • FreeBSD 4.1 on an i486, FreeBSD 4.8 on a Pentium 4 and FreeBSD 5.1
    • 
+  
  • OpenBSD 3.5 and 5.0
    • 
+  
  • Solaris 8 on a SUN UltraSparc 1
    • 
+  
  • Linux/ARM (oabi) on Sharp Zaurus SL-C760 PDA
    • 
+  
  • Linux/ARM (eabi) on Nokia Maemo Internet Tablets and N900 phone
    • 
+  
  • Windows XP
    • 
+

+
+
Compiling and running

+
+
Compiling Hatari

+
+
Required:

+
+
+
Optional:

+
    
+
  • The PNG image library for PNG format screenshots and to
+decrease AVI video recording file sizes. You can get it from
+http://www.libpng.org/.
    • 
+
  • The GNU Readline library for Hatari debugger command line editing.
    • 
+
  • The Xlib library to support Hatari Python UI window embedding
+on systems with the X window system (Linux and other unixes).
    • 
+
  • The portaudio library for Falcon microphone recording support
    • 
+

+

+The versions available in your Linux distribution will be sufficient
+in most cases, but make sure you have also the header files installed
+for the libraries as well! Typically they're in a corresponding -dev
+package.
+

+
+

+After you've verified that you have the required libraries and their
+development files, change to the hatari/
+directory.  Create a build/ directory under
+it and configure the build system for your environment:
+
+mkdir -p build
+cd build
+cmake ..
+

+

+Then compile Hatari by typing make.
+If all works fine, you'll get the executable hatari
+in the src/ subdirectory.
+

+

+Note: Instead of calling CMake directly, you can also use the supplied
+configure script to run CMake and to give the arguments (like install
+prefix) in a format familiar from GNU Autotools using programs.  Type
+"./configure --help"
+to see all the options supported by this script.
+

+
+
Installation of a TOS ROM

+
+

+Before you can start Hatari, you have to copy a TOS ROM image to the data
+directory (<prefix>/share/hatari/, by
+default /usr/local/share/hatari/) and
+rename it to tos.img, or use the
+--tos command line option to tell
+Hatari where to find a TOS ROM.
+Hatari needs a TOS ROM image because this contains the operating system
+of the emulated Atari.
+

+

+Unfortunately it is not possible to ship an original ROM
+image with the Hatari package since these images are still copyrighted.
+But you can easily create an image with a real ST and one of those various
+ROM-image programs for the ST (search for "TOSDUMP" with your
+favourite internet search engine). If your old ST does not work anymore, you
+can also try to search the internet directly for corresponding TOS ROM image,
+but don't ask the Hatari team where to get one. 

+
 Another solution is EmuTOS, which is also shipped with the official
+release versions of Hatari. EmuTOS is an open-source TOS clone. You can find
+it at:
+http://emutos.sourceforge.net/.
+It is not the best solution for playing games or running other old software
+due to compatibility issues (see emutos.txt for
+more details), but it's free and compatible with Hatari.

+
If you do not specify a TOS image on the commandline nor can Hatari
+find a suitable TOS image in the default dir, you'll get the chance to
+select a TOS image file from the GUI. 

+
+
Installation of the binary

+
+
 Type make install as "root" user to
+do a systemwide installation.

+
Assuming you didn't change the default installation prefix and that
+/usr/local/bin/ is in your PATH, you should
+be now able to start the Hatari executable from anywhere.

+
 When you finally have got a TOS image, try starting Hatari with the
+option --help to find out more about
+its command line parameters. 

+
+
Running Hatari for the first time

+
+
 Now type hatari to run the
+emulator for the first time. If all goes
+well, you should now be presented with a window showing you the
+familiar
+little green desktop of the Atari ST. Press F12
+to turn on the GUI to
+configure Hatari to suit your needs, press F11
+to toggle windowed and fullscreen mode. 

+
+
Configuration options precedence

+
+
Hatari settings can come from several sources, with later ones
+overriding the earlier given ones:
+
    
+
  • Builtin Hatari default options (which are different for old UAE and WinUAE
+    CPU core builds, former defaults to ST, latter to Falcon)
    • 
+
  • Global /etc/hatari.cfg
+    (or /usr/local/etc/hatari.cfg)
+    configuration file
    • 
+
  • User specific ~/.hatari/hatari.cfg
+    configuration file
    • 
+
  • Command line arguments
+
  • Option changes done at run-time in Hatari options GUI, with debugger "setopt"
+    command or through the (optionally enabled) Hatari control socket.
+

+
+
Some of the run-time changes require emulation to be reset for them
+to take effect.

+
+
+
Command line options and arguments

+
+
Usage:

+
+ hatari [options] [disk image | directory | Atari program ]
+

+
+
As an argument one can give either a name of:

+
    
+
  • A floppy disk image,
+
  • A directory that should be emulated as a virtual GEMDOS HD, or
    • 
+
  • An Atari program that should be autostarted.  In this case
+    the program's directory will be used as the C: drive from
+    where this program will be started.
+    (Note that autostarting a program might not work if you've also
+    specified a floppy image for drive A: on command line or in config
+    file which contains a desktop.inf/newdesk.inf/emutos.inf file on
+    it.)
    • 
+

+
+
Booting will be done from the disk image or directory that's given
+last on the command line as an option or the argument (and which
+corresponds to A: or C:).

+
+
Hatari command line options are split into several categories:

+
+
+
+
General options

+
-h,
+--help

+
Print command line options and
+terminate

+
-v,
+--version

+
Print version information and
+terminate

+
--confirm-quit
+<bool>

+
Whether Hatari confirms quitting

+
-c, --configfile
+<filename>

+
Read additional configuration values from
+<file>, these override values read from the global and
+user configuration files
+

+
-k, --keymap
+<file>

+
load keyboard mapping from
+<file>

+
--fast-forward
+<bool>

+
On fast machine helps skipping (fast
+forwarding) Hatari output

+
+
Common display options

+
-m,
+--mono

+
Start in monochrome mode instead of
+color

+
--monitor
+<x>

+
Select monitor type (x =
+mono/rgb/vga/tv)

+
-f,
+--fullscreen

+
Start the emulator in fullscreen
+mode

+
-w, --window

+
Start the emulator in windowed mode

+
--grab

+
Grab mouse (also) in windowed mode

+
--borders <bool>

+
Show ST/STE/Falcon screen borders
+(for low/med resolution overscan demos)

+
--frameskips
+<x>

+
Skip <x> frames after each
+displayed frame to accelerate emulation (0=disabled, >4 uses
+automatic frameskip with given value as maximum)

+
--slowdown <x>

+
Slow down emulation by factor of x
+(used as multiplier for VBL wait time)

+
--statusbar
+<bool>

+
Show statusbar (with floppy leds etc
+etc)

+
--drive-led
+<bool>

+
Show overlay drive led when statusbar
+isn’t shown

+
--max-width
+<x>

+
Preferred / maximum window width
+for borders / zooming

+
--max-height
+<x>

+
Preferred / maximum window height
+for borders / zooming

+
--bpp
+<bool>

+
Force internal bitdepth (x =
+8/15/16/32, 0=disable)

+
+
ST/STE specific display options

+
--desktop-st
+<bool>

+
Whether fullscreen mode uses desktop
+resolution to avoid: messing multi-screen setups, several seconds
+delay needed by LCD monitors resolution switching and the resulting
+sound break. As Hatari ST/E display code doesn’t support
+zooming (except low-rez doubling), it doesn’t get scaled (by
+Hatari or monitor) when this is enabled. Therefore this is mainly
+useful only if you suffer from the described effects, but still
+want to grab mouse and remove other distractions from the screen
+just by toggling fullscreen mode. (disabled by default)

+
--spec512
+<x>

+
Hatari uses this threshold to decide
+when to render a screen with the slower but more accurate
+Spectrum512 screen conversion functions (0 <= x <= 512,
+0=disable)

+
-z, --zoom
+<x>

+
Zoom (double) low resolution (1=no,
+2=yes)

+
+
TT/Falcon specific display options

+

+Zooming to sizes specified below is internally done using integer scaling
+factors. This means that different Atari resolutions may show up with
+different sizes, but they are never blurry.
+
--desktop <bool>

+
Whether to use desktop resolution on
+fullscreen to avoid issues related to resolution switching.
+Otherwise fullscreen will use a resolution that is closest to the
+Hatari window size. (enabled by default)

+
--force-max
+<bool>

+
Hatari window size is forced to
+specified maximum size and black borders used when Atari resolution
+doesn’t scale evenly to it. This is most useful when
+recording videos of Falcon demos that change their resolution.
+(disabled by default)

+
--aspect
+<bool>

+
Whether to do monitor aspect ratio
+correction (enabled by default)

+
+
VDI options

+
--vdi
+<bool>

+
Whether to use VDI screen mode

+
--vdi-planes
+<x>

+
Use extended VDI resolution with bit
+depth <x> (x = 1, 2 or 4)

+
--vdi-width
+<w>

+
Use extended VDI resolution with width
+<w> (320 < w <= 1280)

+
--vdi-height
+<h>

+
Use extended VDI resolution with height
+<h> (200 < h <= 960)

+
+
Screen capture options

+
--crop
+<bool>

+
Remove statusbar from the screen
+captures

+
--avirecord

+
Start AVI recording. Note: recording will
+automatically stop when emulation resolution changes.

+
--avi-vcodec <x>

+
Select AVI video codec (x = bmp/png).
+PNG compression can be much slower than using the uncompressed BMP
+format, but uncompressed video content takes huge amount of space.

+
--png-level <x>

+
Select PNG compression level for AVI video (x = 0-9).
+Both compression efficiency and speed depend on the compressed
+screen content. Highest compression level (9) can be really
+slow with some content. Levels 3-6 should compress nearly as well
+with clearly smaller CPU overhead.

+
--avi-fps <x>

+
Force AVI frame rate (x = 50/60/71/...)

+
--avi-file <file>

+
Use <file> to record AVI

+
+
Devices options

+
-j,
+--joystick <port>

+
Emulate joystick with cursor keys in
+given port (0-5)

+
--joy<port>
+<type>

+
Set joystick type (none/keys/real) for
+given port

+
--printer
+<file>

+
Enable printer support and write data
+to <file>

+
--midi-in
+<filename>

+
Enable MIDI support and write MIDI data
+to <file>

+
--midi-out
+<filename>

+
Enable MIDI support and read MIDI data
+from <file>

+
--rs232-in
+<filename>

+
Enable serial port support and use
+<file> as the input device

+
--rs232-out
+<filename>

+
Enable serial port support and use
+<file> as the output device

+
+
Disk options

+
--drive-a
+<bool>

+
Enable/disable drive A (default is on)

+
--drive-b
+<bool>

+
Enable/disable drive B (default is on)

+
--drive-a-heads
+<x>

+
Set number of heads for drive A (1=single sided, 2=double sided)

+
--drive-b-heads
+<x>

+
Set number of heads for drive B (1=single sided, 2=double sided)

+
--disk-a
+<file>

+
Set disk image for floppy drive A

+
--disk-b
+<file>

+
Set disk image for floppy drive B

+
--protect-floppy
+<x>

+
Write protect floppy image contents
+(on/off/auto). With "auto" option write protection is according to
+the disk image file attributes

+
--protect-hd
+<x>

+
Write protect hard drive <dir>
+contents (on/off/auto). With "auto" option the protection can be
+controlled by setting individual files attributes as it disables
+the file attribute modifications for the GEMDOS HD
+emulation

+
--gemdos-case <x>

+
Specify whether new dir/filenames are forced to be
+in upper or lower case with the GEMDOS HD emulation. Off/upper/lower, off by default
+

+
-d, --harddrive
+<dir>

+
Emulate hard disk partition(s) with
+<dir> contents. If directory contains only single letter
+(C-Z) subdirectories, each of these subdirectories will be treated
+as a separate partition, otherwise the given directory itself will
+be assigned to drive "C:". In the multiple partition case, the
+letters used as the subdirectory names will determine to which
+drives/partitions they’re assigned. If <dir> is
+an empty string, then harddrive's emulation is disabled

+
--acsi
+<file>

+
Emulate an ACSI hard drive with an image
+<file>

+
--ide-master
+<file>

+
Emulate an IDE master hard drive with an
+image <file>

+
--ide-slave
+<file>

+
Emulate an IDE slave hard drive with an
+image <file>

+
--fastfdc
+<bool>

+
Speed up FDC emulation (can cause
+incompatibilities)

+
+
Memory options

+

+--memstate <file>

+
Load memory snap-shot <file>

+
-s, --memsize
+<x>

+
Set amount of emulated RAM, x = 1 to 14
+MiB, or 0 for 512 KiB

+
+
ROM options

+
-t,
+--tos <imagefile>

+
Specify TOS ROM image to use

+
--patch-tos
+<bool>

+
Use this option to enable/disable TOS
+ROM patching. Experts only! Leave this enabled unless you know what
+you are doing!

+
--cartridge
+<imagefile>

+
Use ROM cartridge image <file>
+(only works if GEMDOS HD emulation and extended VDI resolution are
+disabled)

+
+
CPU options

+

+--cpulevel <x>

+
Specify CPU (680x0) to use (use x >=
+1 with EmuTOS or TOS >= 2.06 only!)

+
--cpuclock
+<x>

+
Set the CPU clock (8, 16 or 32 Mhz)

+
--compatible
+<bool>

+
Use a more compatible, but slower 68000
+CPU mode with better prefetch accuracy and cycle counting

+
+
Misc system options

+

+--machine <x>

+
Select machine type (x = st, ste, tt or
+falcon)

+
--blitter
+<bool>

+
Enable blitter emulation (ST only)

+
--dsp <x>

+
Falcon DSP emulation (x = none, dummy
+or emu, Falcon only)

+
--timer-d
+<bool>

+
Patch redundantly high Timer-D
+frequency set by TOS. This about doubles Hatari speed (for ST/e
+emulation) as the original Timer-D frequency causes most of the
+interrupts.

+
--fast-boot
+<bool>

+
Patch TOS and initialize the so-called
+"memvalid" system variables to by-pass the memory test of TOS, so
+that the system boots faster.

+
--rtc
+<bool>

+
Enable real-time clock

+
+
Sound options

+
--mic
+<bool>

+
Enable/disable (Falcon only)
+microphone

+
--sound
+<x>

+
Sound frequency: 6000-50066. "off"
+disables the sound and speeds up the emulation. To prevent extra
+sound artifacts, the frequency should be selected so that it either
+matches evenly with the STE/TT/Falcon sound DMA (6258, 12517,
+250033, 50066 Hz) or your sound card frequencies (11025, 22050,
+44100 or 6000...48000 Hz). Check what your sound card supports.

+
--sound-buffer-size
+<x>

+
SDL’s sound buffer size: 10-100,
+or 0 to use default buffer size. By default Hatari uses an SDL
+buffer size of 1024 samples, which gives approximatively 20-30 ms
+of sound depending on the chosen sound frequency. Under some OS or
+with not fully supported sound card, this default setting can cause
+a bigger delay at lower frequency (nearly 0.5 sec). In that case,
+you can use this option to force the size of the sound buffer to a
+fixed number of milliseconds of sound (using 20 is often a good
+choice if you have such problems). Most users will not need this
+option.

+
--sound-sync
+<bool>

+
The emulation rate is nudged by +100 or
+0 or -100 micro-seconds on occasion. This prevents the sound buffer
+from overflowing (long latency and lost samples) or underflowing
+(short latency and repeated samples). The emulation rate smoothly
+deviates by a maximum of 0.58% until synchronized, while the
+emulator continuously generates every sound sample and the crystal
+controlled sound system consumes every sample.

+(on|off, off=default)

+
--ym-mixing
+<x>

+
Select a method for mixing the three
+YM2149 voice volumes together. "model" uses a mathematical model of
+the YM voices, "table" uses a lookup table of audio output voltage
+values measured on STF and "linear" just averages the 3 YM
+voices.

+
+
Debug options

+
-W, --wincon

+
Open console window (Windows only)

+
-D,
+--debug

+
Toggle whether CPU exceptions invoke
+the debugger

+
--debug-except <flags>

+
Specify which exceptions invoke debugger, see
+"--debug-except help" for available (comma separated) exception
+flags.

+
--bios-intercept

+

+Toggle XBios command parsing. Allows Atari programs to use all Hatari
+functionality and change Hatari state through Hatari specifit
+XBios(255) calls. XBios(20) printscreen calls produce also Hatari
+screenshots.

+
--conout <device>

+
Enable console (xconout vector functions) output
+redirection for given <device> to host terminal.  Device 2 is for
+the (CON:) VT52 console, which vector function catches also EmuTOS panic
+messages and MiNT console output, not just normal BIOS console output.

+
--disasm <x>

+
Set disassembly options.  'uae' and 'ext' select
+the dissasembly engine to use, bitmask sets output options for the
+external disassembly engine and 'help' lists them.

+
--natfeats <bool>

+
Enable/disable (basic) Native Features support.
+E.g. EmuTOS uses it for debug output.

+
--trace
+<flags>

+
Activate debug traces, see
+"--trace help" for available tracing flags

+
--trace-file
+<file>

+
Save trace output to <file>
+(default=stderr)

+
--parse
+<file>

+
Parse/execute debugger commands from
+<file>

+
--saveconfig

+
Save Hatari configuration and exit.
+Hatari UI needs Hatari configuration file to start, this can be
+used to create it automatically.

+
--no-parachute

+
Disable SDL parachute to get Hatari
+core dumps. SDL parachute is enabled by default to restore video
+mode in case Hatari terminates abnormally while using non-standard
+screen resolution.

+
--control-socket
+<file>

+
Hatari reads options from given socket
+at run-time

+
--log-file
+<file>

+
Save log output to <file>
+(default=stderr)

+
--log-level
+<x>

+
Log output level
+(x=debug/todo/info/warn/error/fatal)

+
--alert-level
+<x>

+
Show dialog for log messages above
+given level

+
--run-vbls
+<x>

+
Exit after X VBLs

+
+
Type hatari --help to list all
+the command line options supported by a given version of Hatari.

+
+
+
Using the emulated system

+
+
 Once you've started Hatari successfully, you can use the emulator as
+an almost complete Atari ST computer system. 

+
+
The GUI

+
+
Press F12 to enter the GUI. Navigate it
+with the mouse.
+The GUI is rather self explanatory.

+
+
The Main Menu

+
+

+  Hatari's GUI - the main menu
+

+
+

+You can reach the other setup dialogs from the main menu by clicking on
+the appropriate buttons.
+

+

+You can load the current settings from a configuration file by clicking
+on Load config. and you can save
+the current settings to a configuration file by clicking on
+Save config..
+

+

+Click OK to go back and continue the emulation.
+All changed options will be applied.
+

+

+Select the Reset machine option if you
+want the emulated machine to perform a cold reset. This is equal to
+switching the power off and on again on a real Atari machine.
+

+

+Click Quit to terminate Hatari
+and return to the host OS.
+

+

+Click Cancel to abandon any
+changes that you have made.
+

+
+
+
The File Selector Dialog

+
+

+  Hatari's GUI - the fileselector
+

+
+

+ The file selector dialog appears whenever you are prompted to choose a file
+ or folder.
+

+

+ To enter a folder or choose a file, simply click on the entry in the
+ main box of the dialog. To navigate in the file list, you can use the
+ scrollbar on the right with mouse, or use keyboard up + down arrow,
+ page up + down, Home and End keys.
+

+

+ You can use the three buttons in the upper right corner for additional folder
+ navigation. Click the .. button to go up one level
+ in the directory tree. Click the ~ button to return
+ to your home directory. The / button can be clicked
+ to go to the root directory of the file system.
+

+
+
+
The System Dialog

+
+

+  Hatari's GUI - the system dialog
+

+
+

+ The system dialog can be used to define the basic hardware attributes of
+ the machine that should be emulated.
+

+

+ The machine type option is used to select the type of Atari computer to
+ be emulated. The ST was the very first 16/32-bit computer from Atari.
+ Most older games and demos require an ST. The STE was introduced some years
+ later and had some more advanced hardware features. There are not that many
+ demos or games that really require an STE but since most normal ST games/demos
+ also work with an STE, it's normally safe to always work in STE mode.
+ 

+ TT and Falcon are more advanced, but they are not as compatible to the ST as
+ the STE was. Therefore many old games and demos do not work with these machine
+ types anymore. There were only very few programs that were made for the TT
+ exclusively, while there were some interesting games and demos specially made
+ for the Falcon.
+ 

+ Note: Falcon and especially TT emulation are still considered as
+ experimental and incomplete.
+ Quite a bunch of programs do not work very well yet.
+

+

+ For STE emulation a STE compatible TOS image, e.q. version 1.06, 1.62 or
+ 2.x, is strongly recommended. For TT emulation you need TOS 3.0x and for Falcon
+ emulation you need TOS 4.0x. EmuTOS can be used on all machine types.
+

+
+

+ The CPU type option can be used to select the level of the central processing
+ unit. If you are not sure what to use, simply select 68000 for ST and STE
+ machines and 68030 for TT and Falcon emulation, since this were the original
+ configurations used in the Atari computers. In case you want to vary
+ the CPU type, you have got to be aware of some constraints:
+

+
    
+ 
  • 
+  Atari ST and STE have only been shipped with a 68000 CPU, so for best
+  compatibility with old programs, you should choose this CPU type.
+ 
    • 
+ 
  • 
+  If you are going to use TOS 1.0x, you also have to select the 68000 CPU,
+  since these TOS versions are not aware of the higher CPU levels yet.
+  If you want to use a higher CPU level with the ST or STE machine type,
+  you've got to use TOS 2.0x instead.
+ 
    • 
+ 
  • 
+  Atari TT and Falcon computers were using the 68030 CPU, so you should select
+  the 68030 CPU type for these machines.
+ 
    • 
+ 
  • 
+  TOS 3.0x and 4.0x also only work with a CPU >= 68020.
+ 
    • 
+ 
  • 
+  68010 and 68040, 68060 have never been used in official Atari computers,
+  so don't use these CPU types unless you've got some good reasons.
+ 
    • 
+ 
  • 
+  The 68060 option is only available in the "WinUAE" builds of
+  Hatari, and is currently also considered as experimental, so do not use
+  this option unless you know what you are doing.
+ 
    • 
+

+
+

+ The CPU clock option can be used to select the frequency that is used
+ to clock the CPU. 8 Mhz is the standard for ST and STE and the most
+ compatible frequency for old software.
+ Use 16 MHz for Mega STE and Falcon emulation.
+ The CPU in the TT was clocked with 32 MHz.
+

+

+ For Falcon mode, you can choose whether you want to disable DSP emulation,
+ fake it or enable full emulation. Most Falcon programs only play sound or work
+ correctly when you enable the DSP emulation, but it needs a lot of host CPU
+ power (more than 2 GHz) for full emulation. So if you have a slow host CPU,
+ you can try if your Falcon program also runs with DSP disabled or in
+ the "dummy" fake mode.
+ Note that you can not change this option while the DSP based program already
+ runs.
+

+

+ The check boxes in the "CPU and system parameters" section can
+ be used to fine-tune the machine and CPU types.
+

+

+ If you enable the "Real time clock emulation" switch, a RTC (like the ones
+ that could be found in the Mega-ST and Mega-STE computers) will be emulated
+ based on the time of the host computer.
+ This option is only affects the emulation of ST and STE machines. TT and
+ Falcon used a different kind of RTC (which is not optional and thus always
+ enabled in Hatari).
+ Note: You need at least TOS 1.02 for proper RTC emulation, TOS 1.00 does
+ not support this.
+

+

+ The next check box can be used to enable/disable Blitter emulation.
+ The Blitter is a custom chip that accelerates some graphical operations.
+ This switch only toggles the Blitter in plain ST mode. In STE and Falcon mode,
+ the Blitter is always enabled (since these machines have always been sold
+ with a Blitter chip). The TT was always shipped without the Blitter chip.
+

+

+ The "Patch Timer-D" option changes the Timer-D initialization from
+ TOS. TOS uses the MFP timer D as a baudrate generator for RS232. However, the
+ TOS default value slows down the emulation. The patch gives you a better
+ performance.  It is normally safe to enable the patch, but if you encounter a
+ program that does not work, you can try to disable the patch to see if it
+ works better.
+

+

+ With the "Boot faster" option, Hatari patches the TOS ROM and some
+ system variables, to speed up the boot process of the emulated system, e.g.
+ by simulating a warm reset. This is a convenient option, but some very few old
+ programs rely on an unmodified boot process, so in rare cases this option has
+ to be switched off to get those programs running.
+

+

+ The "Prefetch mode" option is used to enable the emulation of 68k
+ address errors and the so-called CPU prefetch buffer. This is needed for best
+ compatibility, but it slows down emulation a little bit so you can disable it
+ if you don't need it and if you have a slow host system.
+

+

+ The "Cycle exact", the "MMU emulation" and
+ "24-bit addressing" option are only available in the
+ "WinUAE" builds
+ of Hatari. They are considered as experimental and should be switched off
+ unless you know what you are doing.
+

+

+ The FPU settings are also only available with the "WinUAE" builds
+ of Hatari. They can be used to select the type of floating point unit of CPUs
+ >= 68020. In the normal builds of Hatari, the FPU is always enabled for
+ 68030 and 68040 CPUs.
+

+

+ NOTE: The emulated Atari system is very very sensitive to all of
+ these options and it is strongly recommended to reset the emulation after
+ changing them (for most things that's done automatically).
+ The correct CPU type and clock are automatically selected when one uses the
+ --machine command line option.
+

+
+
+
The Floppy Disks Dialog

+
+

+  Hatari's GUI - the floppy disks dialog
+

+
+

+ This dialog can be used to choose which floppy disks should be emulated
+ in the disk drives. You can use most standard Atari ST disk image files.
+ You may select and browse also zipped disk images. See the chapter
+ "Floppy disk images" for details.
+

+

+ Each drive can be enabled or disabled (as if it was not connected or turned
+ off). You can also choose to emulate a single sided drive instead of a double
+ sided one (some games or demos will have a different behaviour in single sided
+ mode).
+

+

+ Click on the button Browse next to the
+ A: and B: option to go to the fileselector to choose a disk image for the
+ corresponding drive.
+

+
Click on Eject to eject a disk image
+from the emulated drive. The emulated ST will act as if had no floppy
+disk in its drive.

+
You can specify a default directory where Hatari will start to
+browse the filesystem.

+

+Check the "Auto insert B" option if you want Hatari to be smart and
+insert the second disk of a two disk game automatically.
+Some games then use the second drive automatically.
+In the case that a game is not able to find the disk in the second drive,
+you have to insert the second disk in drive A: manually when prompted.
+

+NOTE: This option only works properly if the file name of the
+first disks ends with an 'a' before the extension and the second disk name
+ends with a 'b'.
+

+

+ Select if you want to use fast FDC (Floppy Disk Controller) emulation.
+
+ "Fast floppy access" option will speed up disk accesses, but this can
+ cause incompatibilities with programs that expect correct delays
+ (some games/demos don't expect data to be read too fast from the
+ disk). For example, when using STX images, most protections will fail
+ if fast floppy access is enabled.
+

+

+ If you want, you can set Hatari to write-protect your disks. Atari ST
+ virii can spread on disk images, so that can be a good idea. However,
+ note that some programs won't work correctly (or at all) with write
+ protected disks, and things like saving highscores in games will fail.
+

+
+

+  Hatari's GUI - the new floppy dialog
+

+
+

+ If you need to create a new blank disk image, click on
+ Create blank image.
+ Parameters for the new image can be set in the following dialog. HD
+ and ED disk sector counts are for larger, non-Atari disk sizes, they
+ can be useful with programs that don't work from hard drive, or with
+ with GEMDOS HD emulation.
+ Click on Create to save the new image or on
+ Back to return to the disk dialog.
+

+

+ After clicking Create, a fileselector
+ appears. You can browse the filesystem now. Select the target directory,
+ click beside "File:" and type in a name for the new disk image.
+ The name should terminate with .st or .msa.
+

+

+ Hatari can currently create plain .ST and .MSA disk images exclusively.
+ hmsa command line utility can be used
+ to convert disk images between .ST and .MSA formats.
+

+
+
+
The Hard Disks Dialog

+
+

+  Hatari's GUI - the hard disks dialog
+

+
+

+ This dialog can be used to change the hard disk settings.
+

+

+ Here you can select a hard disk image file for ACSI, IDE master or
+ slave hard drive emulation, or you can select a host directory to be
+ emulated as the Atari hard drive.
+

+

+ Check "Boot from HD" if you want Hatari to execute the AUTO folder on
+ the hard disk. This option is checked by default if you specify a
+ hard disk image or a directory via the command line.
+

+

+ Removing the check from the "Allow GEMDOS drive modification" option
+ will prevent Atari programs from modifying the files in GEMDOS HD
+ emulation directory or creating new files under it.
+

+

+ Note that you need TOS version >= 2.05 to boot from IDE hard drive.
+ And ACSI hard drive emulation does not work with TOS 4.0x in Falcon mode.
+

+
+
+
The Memory Dialog

+
+

+  Hatari's GUI - the memory dialog
+

+
+
You can select the amount of RAM for the emulated ST here. Only
+amounts that were valid on a real unmodified STFM can be selected.

+
Note: This option is critical and you are strongly advised
+to reset the emulated ST
+when changing this option.

+
Here you will find the options to save memory snapshots as well.

+
Click on Save to save a memory snapshot
+to file. You can select a new filename here.

+
Click on Restore to restore a memory
+snapshot from a file. Use the fileselector to select the snapshot to be
+restored.

+
NOTE: Memory snapshots are not interchangeable between
+different versions of Hatari. E.q. if you compile a newer Hatari, you
+cannot load your old memory snapshots back.

+
+
+
The ROM Dialog

+
+

+  Hatari's GUI - the ROM dialog
+

+
+
Here you can select the TOS image to use. Click on Browse to select it via the fileselector.
+You can also select an optional cartridge image to use. Click on Browse to select one via the fileselector. Click on Eject to disconnect the custom cartridge image.
+

+

+For ST mode, use TOS 1.00, 1.02, 1.04 or 2.06.
+For STE mode, use TOS 1.06, 1.62, 2.05 or 2.06.
+If you want to use the TT mode, you must specify a TOS 3.06 image here.
+And in Falcon mode, you have to use either TOS 4.00, 4.02, 4.04 or 4.92.
+However, you should always use TOS 4.04 for Falcon mode, it's the most common one.
+Also note that TOS 4.92 can not be booted from a boot disk (like it's done on a
+real Falcon), you have to specify it directly in the TOS ROM setup dialog here.
+

+

+Keep in mind that any custom cartridge image will not work together with
+GEMDOS HD emulation or the VDI extended resolution emulation
+since some additional driver code will be used in the cartridge memory
+space for these emulations.
+

+

+Note: These options are critical and you are strongly
+advised to reset the emulated ST
+when changing one of these option.
+

+
+
+
The Joystick Dialog

+
+

+  Hatari's GUI - the joystick dialog
+

+
+
In this dialog, you can configure the emulated joysticks.
+With the upper two arrows, you can choose the joystick which you want to
+configure.

+
Joystick 1 is the normal ST joystick port and 99.9% of all ST games
+use this port.
+Joystick 0 emulates a joystick plugged into the ST mouse port
+and is often used in games for two players.

+
With STE joypad A and B, you can enable the emulation of Jaguar joypads
+which are plugged in the enhanced joystick ports of the Atari STE.
+Only very few STE games support these joypads, so you often won't need this.

+
Finally, Hatari also emulates joysticks which were plugged on the parallel
+port with a special adapter on a real ST. These were used in some few
+multi-player games like "Gauntlet 2".

+
For each ST joystick, choose whether you want to disable it,
+use the keyboard for emulation or use a real PC joystick.

+
For keyboard emulation, you can select the keys by pressing the
+Define keys button. You will be prompted to press
+the keys for up, down, left, right and fire.

+
If you want to use a real PC joystick for the emulation, you should connect
+it to your PC before you start Hatari. Then you can choose the joystick with
+the two lower arrows.

+
Check the "Enable autofire" option if you are too lazy to pound
+on the fire button in shoot'em-up games. However, this option only works with
+certain games. In some other games, it gets worse if you enable this option.

+
See also the chapter "Emulated Joystick" for details.

+
+
+
The Atari Monitor Dialog

+
+

+  Hatari's GUI - the Atari monitor dialog
+

+
+

+ Here you control the video output of the emulated Atari.
+

+

+ You can select which sort of monitor to use. This option depends on
+ the machine type which you have selected in the "System options"
+ dialog. In ST and STE mode, you can choose between monochrome mode
+ (select "Mono") and color mode (select one of the other monitor types).
+ Note that when you select "TV" and use zoomed low resolution or
+ switch to ST medium resolution, you will get a TV-like screen rendering
+ which is a little bit faster but darker compared to the normal "RGB"
+ monitor mode. Switching between mono and a color monitor acts like a monitor
+ switch on a real ST - so beware, this will reboot your emulated system!

+ In TT mode, you can only choose between TT-high resolution ("Mono")
+ and normal modes (select one of the other monitor types).
+ Finally the Falcon mode supports all four types of monitors. Note that most
+ Falcon demos/games require a RGB or TV mode, and do not work with
+ VGA, although there are also few VGA-only games and demos.
+

+

+ "Show ST/STE borders" toggles the displaying of the borders around the ST /
+ STE. Some demos and games use the screen borders for displaying
+ additional graphics. As enabling this option increases CPU computing time,
+ don't enable it if you have a very slow computer.
+ Borders are shown also in Falcon emulation, but Videl emulation doesn't
+ yet support palette effects.
+ This option doesn't affect TT screen mode or extended VDI resolutions.
+

+

+Extended VDI resolutions will emulate a sort of extended graphics card
+in the emulated machine, which gives you larger (2-16 color)
+resolutions for GEM. Select a resolution and color depth. Check to
+activate. This mode isn't affect by the other video options mentioned
+above. Uncheck to get back to a normal ST behaviour.

+

+
Note that there are several gotches with extended VDI
+resolutions:

+
    
+
  • Only GEM conformant applications work with them, 99% of all games
+and demos don't.
    • 
+
  • Several GEM programs accessing screen directly (like NVDI) crash
+with large enough screen sizes.
    • 
+
  • Memory reserved for (larger) extended resolutions breaks TOS v3 memory
+detection, so you need to interrupt boot up memory detection.
    • 
+
  • TOS v4 isn't compatible with them. In Falcon emulation you need to
+use EmuTOS with extended resolutions.
    • 
+

+

+Because TT and Falcon support natively larger resolutions,
+VDI mode is most useful with ST / STE emulation.
+

+
+
+
The Hatari Screen Dialog

+
+

+  Hatari's GUI - the Hatari screen dialog
+

+
+

+Here you control how the video output of the emulated Atari appears
+on your screen.
+

+
+

+ Check "Fullscreen" to run Hatari in fullscreen.  By default Hatari
+ runs in windowed mode.
+

+

+ The "Frame Skip" option can be used to speed up the emulator
+ if it is running too slow on your system. Disable frame-skip if you have
+ a fast computer. When selecting 1, 2 or 4, drawing of corresponding number
+ of frames will be skipped after each frame actually shown by Hatari.
+ Select "Auto" to let the emulator to decide whether, and
+ how many frames will be skipped.

+ Note: The frameskip option also affects the frame rate of the
+ screen animation recording!
+

+

+Indicators that you can have on the Hatari window:
+

+
    
+
  • "Statusbar" at the bottom of the screen.
+The statusbar shows the floppy drive LEDs, the current frameskip value,
+the machine type including TOS version and memory size, and whether
+recording is currently active.
    • 
+
  • "Drive led" is a colored rectangle shown on top of the Hatari window
+contents. It will show any disk (floppy or hard drive) activity.
    • 
+
  • "None" turns both of above options off.
    • 
+

+

+"Keep desktop resolution" option will use your desktop resolution
+for fullscreen to avoid issues related to resolution switching,
+especially on LCD monitors (they're slow).  If this isn't enabled,
+values from the "Max zoomed win" option are used in selecting
+a suitable resolution.
+

+"Max zoomed win" option controls up to which size Hatari tries to scale
+the Atari resolutions and how much of the borders (enabled in Atari
+Monitor dialog) will be shown.  Note that there are several limitations
+in this and the "Keep desktop resolution" option, partly because Hatari
+has different implementations for different video modes:
+

+
    
+
  • VDI resolutions (selectable in Atari Monitor dialog) aren't scaled.
    • 
+
  • ST and STE video emulation supports only doubling of the ST-low
+    resolution.
    • 
+
  • Hatari doesn't support downscaling. If the original Atari resolution
+    is larger than the specified size (e.g. TT-high), the Hatari screen
+    size will also be larger than requested.  Hatari Falcon/TT window size
+    will be limited to the Desktop size though.
    • 
+
  • TT and Falcon resolutions support only integer scaling ratios.
+    If the scaling ratio cannot match the requested size exactly, Hatari
+    will use a ratio that will produce smaller size closest to the
+    requested one.
    • 
+

+

+You should set these values to a size that suits best your monitor
+resolution. It's intended to help in getting Hatari to best use your
+monitor space on a windowed mode and in fullscreen avoiding "fuzzy"
+scaling done by your LCD monitor.
+

+

+Giving "-z 2" option on command line will reset max zoomed size to
+default values and "-z 1" will disable all zooming.
+Note that zooming takes additional CPU computing time and should
+not be enabled on very slow computers.
+

+
Click the Screenshot button to create
+a screenshot in PNG (or BMP) format to the current working directory
+or click the Record AVI button to
+record an AVI format video of Hatari screen (and audio) output.
+

+

+Selecting "Crop statusbar" option will leave statusbar out from
+the screenshots and recorded videos.
+

+
+
The Keyboard Dialog

+
+

+  Hatari's GUI - the keyboard dialog
+

+
+
Here you can select the keyboard mapping to use. Two different mappings
+ called "Symbolic" and "Scancode" are predefined.

+
"Symbolic" tries to map the symbolic values of your PC keys
+ to the ST keys. It should be working pretty good on all systems as long
+ as your keyboard layout looks close to the standard english keyboard
+ layout. However, you might experience some problems with special keys like
+ brackets etc.

+
"Scancode" uses the scancode values of your PC keys for keyboard
+ mapping. This only works on certain architectures like Linux where the
+ scancodes are similar to the ST scancodes (e.g. it does not work on Mac OS X).
+ If it works on your system, this often gives better results than the symbolic
+ mapping. Note that you also need a TOS version with the right language
+ (e.g. use a French TOS if you are using a French keyboard).

+
You can also load a custom keyboard mapping file here if you wish. Please
+ note that the custom keyboard mapping will use the "symbolic"
+ mapping for all keys that are not defined by your map file. Have a look
+ at the supplied example mapfile (keymap-sample.txt) to see how to create
+ your own keyboard mapping.

+

+ When the emulator runs in fast forward mode, and you want to type text,
+ it can be annoying that the emulated system detects multiple key events
+ due to the key repetition of the emulated system. To avoid this you can
+ disable the key repetition in fast forward mode here.
+

+
+
+
The Sound Dialog

+
+

+  Hatari's GUI - the sound dialog
+

+
+
Here you can control the sound subsystem.

+
Check "Enabled" if you want emulated sound at all. Emulation is faster if
+sound emulation is turned off.

+
If you experiment latency issues with your OS audio's output, you
+can check the "Synchronize" option to adjust Hatari's video emulation to match
+your OS audio.

+

+ Nine frequencies from low to high quality are available. Experiment a
+ little bit to find out which fits best for your setup.
+ For most modern computers, 44100 Hz or 48000 Hz should be fine.
+ For older or slower host systems, you should use a lower frequency.
+ 12517, 250033 and 50066 Hz are frequencies supported by
+ the STE/TT/Falcon sound DMA.
+

+

+YM voices volume mixing "ST table" method uses a lookup table of audio output
+voltage values measured on STF, "Math model" uses a complex model to mix the
+3 YM voices and "Linear" just averages the 3 YM voices. Use "ST table" or "Math model"
+for accurate sound's emulation.
+

+

+ You can select to record a piece of sound here.
+ Use the Browse button to choose a file.
+ The file name extension that you use (.WAV or .YM) determines in which format
+ the sound is recorded in. The Record sound button
+ is a toggle so you will need to return to the GUI to switch sound recording off
+ again (or to use the keyboard shortcut for that).
+

+
+
+
The Devices Dialog

+
+

+  Hatari's GUI - the device dialog
+

+
+
Check the first checkmark to enable printer support.
+See the Emulated printer section for
+details.

+
+
As Hatari currently only supports printing to file, click on Browse to select the file to print to. You can
+enter a new filename as well.

+
Check the second checkmark to enable RS232 support.
+The RS232 device is configured according to the settings of
+the emulated RS232 of the Atari ST. This means Hatari will
+automatically use baudrate and handshaking as configured for the
+emulated ST.

+
Click on Browse to select suitable
+device files for serial input and output.  On Linux a good choice is
+/dev/ttyS0 or /dev/ttyS1.
+

+
Check the third checkmark to enable MIDI support.
+Click on Browse to select a suitable
+MIDI device files for MIDI input and output.

+
midi-linux.txt file explains how to
+select the correct MIDI device file, how to set up software sound
+synthetizing on Linux (using Alsa) if your sound card/driver doesn't
+support MIDI, and how to set up MIDI networking e.g. between multiple
+Hatari instances.
+

+
+
+
Keyboard shortcuts for the SDL GUI

+
+
There are multiple ways to interact with the SDL GUI.

+
+
TAB and cursor keys change focus between UI elements.  Additionally
+Home key moves focus to first item, End key to last one.  Initially
+focus is on default UI element, but focus changes are remembered
+between dialog invocations. Enter and Space invoke focused item. UI
+elements with underlined characters can be invoked directly with Alt +
+key with that character.  Alt + arrow keys will act on arrow
+buttons.

+
+
Most importantly:

+
    
+
  • Options GUI main view: Enter accepts configuration, ESC
+cancels it.
    • 
+
  • Options GUI dialogs: Enter (or End+Enter if focus was moved)
+returns back to main view.
    • 
+
  • Fileselector: Page up and down keys scroll the file list.
+Enter on focused file name selects it.  Enter on OK button accepts
+the selected file. ESC cancels the dialog/selection.
    • 
+
  • Alert dialogs: Enter accepts and ESC cancels the dialog.
    • 
+

+
+
+
Keyboard shortcuts during emulation

+
+
 While the emulator is running, you can activate or toggle various
+features via Hatari keyboard shortcuts. Below are listed the default
+shortcut key bindings:

+
+  
+    
+      
+      
+    
+  
+  
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+  
+
ShortcutPurpose
ALTGR+arecord animation
ALTGR+ggrab a screenshot
ALTGR+iboss key: leave full screen mode, pause Hatari
+          and iconify its window
ALTGR+m(un-)lock the mouse into the window
ALTGR+r(warm) reset the ST
ALTGR+ccoldreset the ST (same as the original power switch)
ALTGR+dopen dialog to select/change disk A
ALTGR+senable/disable sound
ALTGR+qquit the emulator
ALTGR+xtoggle normal speed/fast forward
ALTGR+yenable/disable sound recording
ALTGR+ksave memory snapshot
ALTGR+lload memory snapshot
ALTGR+jtoggle joystick emulation via cursor keys
+          on/off between ports 0 and 1
ALTGR+F1switch joystick type on joy port 0
ALTGR+F2switch joystick type on joy port 1
ALTGR+F3switch joystick type for joypad A
ALTGR+F4switch joystick type for joypad B
ALTGR+f or F11toggle between fullscreen and windowed mode
ALTGR+o or F12activate the options GUI
PAUSEpause emulation
AltGr+PAUSEinvoke the internal Hatari debugger

+
+
You can change the key bindings from the Hatari configuration file.
+See keymap-sample.txt file for instructions.

+
+
+
Emulated Atari ST keyboard

+
+
 All other keys on the keyboard act as the normal Atari ST keys so
+pressing SPACE on your PC will result in an emulated press of the SPACE
+key on the ST. The following keys have special meanings: 

+
+
+  
+    
+      
+      
+    
+  
+  
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+  
+
KeyMeaning
Altwill act as the ST's ALTERNATE key
left CTRLwill act as the ST's CONTROL key
Print Screenwill emulate the ST's HELP key
Scroll Lockwill emulate the ST's UNDO key
Page Upwill emulate the ST's ( key in the keypad
Page Downwill emulate the ST's ) in the keypad

+
+
If joystick emulation via keyboard is enabled, by default cursor keys
+are used for the directions and right CTRL key
+as the fire button. Otherwise they act as corresponding keys of the emulated
+Atari ST.

+
+
NOTE: Problems with simultenous keypresses most likely aren't an
+issue in Hatari as many modern keyboards report/support only three
+simultenous key presses (or even just two depending on which keys
+are in question).  Expensive gaming keyboards support more.

+
+
+
Emulated mouse

+
+
For obvious reasons your PC mouse will act as the emulated Atari ST
+mouse. In fullscreen mode it will act as expected, directly controlling
+the ST mouse pointer. 

+
However it is a little bit different in windowed mode as
+mouse cursor positions between host and emulated Atari can get
+out of sync. This can be worked around by constraining the mouse
+to the Hatari window. Pressing the ALTGR+m
+hotkey combination or starting Hatari with the
+--grab command line option
+grabs the mouse i.e. locks its movements to the Hatari window.
+Press the shortcut key (again) to go back to normal mouse behaviour
+which allows you to move mouse outside outside the Hatari window while
+Hatari is up and running. Note: pausing the emulation will also
+(temporarily) release the mouse grab.

+
Middle button click emulates double click, which is very useful
+in Fast Forward mode (where normal double clicking is nearly
+impossible).

+
Mouse scrollwheel will act as cursor up and down keys. 

+
+
Emulated joystick

+
+
The Atari ST joysticks are emulated ofcourse allowing you to play
+your favourite games with Hatari. 

+
The default mode is to use a connected PC joystick. You can use any
+joystick that is supported by your kernel / SDL library. If your joystick works
+with other applications, it will likely work with Hatari as well. Make sure
+it is calibrated and then off you go. Move the stick to point into the
+desired direction. Please note that Hatari will not detect analogue
+movement as the Atari ST only had digital joysticks. The first
+firebutton will act as the normal firebutton on the Atari ST while the
+second
+firebutton will emulate a keypress of the SPACE
+key on the ST as many ST
+games utilize the SPACE bar for secondary game functions. (Xenon for
+example)

+
If you do not have a PC joystick or joypad, then you do not need to
+desperate. You can emulate one of the two Atari ST joysticks via the
+cursor keys. Just activate it in the GUI. Then the cursor keys will act
+as the joystick directions, the right CTRL key will act as the
+firebutton. You can still use the cursor keys as the ST's
+cursorkeys in this mode as long as you press SHIFT
+along with the cursorkeys.  You can also configure these keys from the
+joystick options.

+
+
Emulated video

+
+
Hatari emulates all screen modes of the original machine.

+

+ST/STE shifter overscan effects are emulated, but due to the fact
+that these effects are achieved by using quirks and glitches in the
+original chips to do things beyond their specification, emulation is
+a bit tricky for these effects. As a result, some demos using these
+techniques might not be displayed correctly in Hatari, known ones are
+listed in the compatibility.html file.
+

+
Beside that you can setup extended VDI modes. These only work with
+GEM-compliant applications and they are equal to fitting a videocard
+into your Mega ST.

+
Make sure to disable extended VDI modes for playing games as 99% of
+all ST games will not be able to make use of higher resolutions.

+
+
Emulated printer

+
+
Due to the fact that printer handling is different on Atari and
+current machines, emulation of the printer is achieved by writing all
+printer output to a file.

+
The file will contain a sequence of data, the same that would appear
+on the data pins of the Atari ST printer port.
+That would include control characters and commands for graphic
+printing. Clicking "Print desktop" on the GEM desktop would result
+in a messy data dump in the printer output.

+
Printer emulation works best for plain text files or programs that
+do not format the output for a specific printer.
+The file contents can be used with your favourite text editor for
+further processing and printing to a real printer.

+
To get real direct printing out of Hatari you may set up a suitable
+(e.g. PostScript) GDOS or NVDI printer driver on the emulated Atari and
+set your printer device file as Hatari's printer output.

+NOTE: If the driver doesn't match or there's some other problem,
+this can cause your printer to print out hundreds of pages of garbage.

+
+
Emulated RS232

+
+
Serial communications in Hatari is designed to directly use a serial
+port on your PC.

+
Communications parameters are set automatically upon the settings of
+the emulated ST. This means all you do is to set
+the communication parameters like baudrate from your ST communications
+software. Hatari will do the rest and handle
+the serial input and output for you.

+
+
Floppy disk images

+
+
Hatari does not use floppy disks directly but disk images due to
+differences between the floppy disk controllers of the ST and the PC.
+Several types of disk images are currently supported :
+

+
+
    
+
  • 
+the raw "ST" type
+
    • 
+
  • 
+the similar "DIM" type (not widely used)
+
    • 
+
  • 
+the compressed "MSA" (Magic-Shadow-Archiver) type
+
    • 
+
  • 
+the "STX" type that can store low level disk layout. This format is mainly
+used to dump original games with their protection. Those images are created
+on a real ST using pasti.prg
+
    • 
+
  • 
+the "IPF", "RAW" and "CTR" types require the caps library. Similar to STX, they
+record disk layout, but at a much precise level by storing MFM data. Most of
+these dumps are made with the Kryoflux board
+
    • 
+

+
+
 The raw type (file suffix should be "*.st") is simply a sector by
+sector image of a real floppy disk. You can easily create such an image
+with the dd program which should
+normally be pre-installed on every
+Unix-like system. Simply type something like dd
+if=/dev/fd0 of=myimage.st to create a disk image. Of course you
+need access to
+/dev/fd0, and depending on your system and the type of floppy disk you
+might have to use another device name here (for example I use
+/dev/fd0u720 for 720kB disks). However, if the disk is copy-protected
+or
+doesn't use a MSDOS compatible file system, this might fail. So be very
+careful if you are not sure about the disk format. 

+
 The other possibility is to image the disk on a real Atari ST.
+For non-protected disk, there
+are programs like the Magic Shadow Archiver for this task. Hatari
+supports this slightly compressed MSA disk images, too. Note that
+Hatari
+only supports the "old" MSA format, there are some Magic Shadow
+Archiver
+clones (like Jay-MSA) that create better compressed but
+Hatari-incompatible disk images. However, if you have got such a MSA
+disk and want to use it with Hatari, you can still run the
+corresponding
+MSA program within Hatari to extract the incompatible disk image to a
+normal floppy disk image.
+

+For protected disk, the most widely used method is to run pasti.prg on
+a real Atari ST and get a .STX image.
+

+For more complex protections or altered disk, one can use *.IPF or *.CTR
+which include tools to check MFM data and possible problems when dumping a disk.
+

+
 While *.ST, *.MSA and *.STX are more or less the "standard" types of Atari
+disk images, you might sometimes also find STT or ADF images on the
+internet. These currently do not work with Hatari. 

+
Hatari can now also utilize *.DIM images just as *.ST ones without
+any problems.
+Note that DIM images are nearly the same as the raw ST images
+(they only have an additional 32 bytes header), so you can easily
+transform
+the DIM images into ST images by stripping the header from the files.
+For example try something like:
+dd if=input.dim of=output.st bs=32 skip=1
+

+
 If you've got a disk image that has been created with the old ST
+emulator PaCifiST (for DOS) or with early versions of the program
+Makedisk, and the disk image does not work with Hatari, then the disk
+probably suffers from the "PaCifiST bootsector bug" (Hatari will
+display a
+warning message then). In this case, the bootsector of the disk
+contains some illegal data, so that the disk even does not work on a
+real ST any more. However, if it is a .ST and not a .MSA disk, you can
+easily fix it by using a hex-editor to change the byte at offset $D
+(13)
+from 0 to 1 (don't forget to backup your disk image first, since you
+can also easily destroy your disk image when changing a wrong byte
+there). If the disk contains a bootsector program, you probably have to
+adjust the boot sector check sum, too (it can be found at offset $1FE +
+$1FF). 

+
Hatari supports disk images that are compressed with (Pk-)ZIP
+(file suffix must be ".zip") or GZip (file suffix must be ".st.gz" or
+".msa.gz"), so you can archive your disk images into zip archives.
+You can also directly run the zip archives you may download from the
+net as long as the archive contains a disk image in .ST or .MSA format.

+
Note: Hatari does not save disk images back to *.ZIP files
+so
+your highscores and savegames are lost if you load the game from such
+a zipped disk image.

+
+
+
Hard disk support

+
+

+Hatari supports three ways of emulating Atari hard drives: The
+low-level ACSI and IDE hard drive emulation and a GEMDOS based HD
+emulation. In most cases the GEMDOS HD emulation is best as it allows
+exchanging files easily between the emulated and the host environment.
+

+

+Please note that changing the HD-image or the GEMDOS HD-folder will reset
+the emulated Atari since it is not possible to switch the hard drive
+while the emulator is running.
+

+

+On a 32-bit host system, the size of a hard disk image is limited to 2 GB.
+On 64-bit host systems, bigger images might be possible but the support
+for bigger images is not tested very well yet.
+

+

+The maximum size of partitions inside the hard disk (images) depends on the
+TOS version. TOS 1.00 and 1.02 support up to 256 MB, TOS 1.04 to 3.06 up to
+512 MB and TOS 4.0x supports up to 1 GB partitions.
+

+

+NOTE: you need to be careful when mounting device files.  Depending on
+the system setup (e.g. udev settings) partitions on memory cards etc.
+can be mounted automatically. When Hatari is started and uses a device
+file with partitions that are already mounted, data can be destroyed
+(when several programs independently write to the same device).
+Disable your desktop automount, or remember to manually unmount
+devices before giving them to Hatari.
+

+
+
+
GEMDOS based hard drive emulation

+

+With the GEMDOS HD emulation, you can easily "mount" a folder from the
+host file system to a drive of the emulated Atari.
+

+

+If you provide Hatari a directory containing only single letter (C-Z)
+subdirectories, each of these subdirectories will be treated as a
+separate partition, otherwise the given directory itself will be
+assigned to drive "C:". In the multiple partition case, the letters
+used as the subdirectory names will determine to which
+drives/partitions they're assigned.  For example following
+directory setup:
+

+
+partitions/
+  + C/
+  + D/
+

+

+That is given to Hatari as "hatari -d partitions", will give you
+GEMDOS HD emulated C: and D: drives.
+

+

+GEMDOS HD emulation is an easy way to share files between the
+host system and the emulated Atari, but there are also some known
+limitations which are due to the way the GEMDOS HD emulation is
+implemented:
+

+
    
+
  • Directory entries are returned in a (case-insensitively) sorted
+order, for consistency.  E.g. moving files to a different directory and
+back (without changing their names) like AUTOSORT does, doesn't change
+that order. You need to rename the files.
    • 
+
  • Names which aren't valid TOS directory or file names, are converted
+to a valid format.  If there are multiple files which converted
+names are identical in TOS-format, you see only one of those.
    • 
+
  • It is not possible to use a cartridge image at the same time
+with the GEMDOS HD emulation (Hatari has its own cartridge code
+that is used for GEMDOS HD emulation).
    • 
+
  • Anything that installs its own GEMDOS handler, like MiNT, doesn't work
+with the GEMDOS HD emulation.  Such things need to be run from a real
+hard disk image.
    • 
+
  • GEMDOS HD C: drive conflicts with the ACSI and IDE hard drives.
+If you want to use GEMDOS HD directory and ACSI/IDE disk images together,
+either use the GEMDOS HD option for skipping ACSI & IDE partitions, or
+use a multiple partition GEMDOS HD emulation setup and select the partition
+subdirectories (see above) so that they don't conflict with the ACSI/IDE
+partitions (drive letters).  With HD Driver you have also another option,
+see Using HD Driver
+with GEMDOS HD partitions.
    • 
+
  • The GEMDOS HD emulation does not work (very well) with TOS
+1.00 and 1.02.  Use at least TOS 1.04 if you want the GEMDOS HD
+emulation to work properly.
    • 
+

+

+If your programs complain that they could not find/read/write
+files on the GEMDOS emulated drive, you can copy and use them
+from a floppy disk image or a real hard disk image instead.
+

+
+
+
ACSI & IDE hard drive emulation with EmuTOS

+
+

+Accessing HD image files is easiest with EmuTOS.  It supports both
+ASCI and IDE interfaces, regardless of emulated machine type, and
+understands DOS partition tables without additional drivers.
+atari-hd-image.sh script coming
+with Hatari can be used to create such image files and to copy
+initial data to them.
+

+

+If you have an hard drive (image) with Atari format partition table,
+that should already have hard disk driver on it and work fine.
+Partitioning/formatting them is the problem.  Creating such images
+from scratch is described in following sections.
+

+
+
+
ACSI hard drive emulation

+

+To use the ACSI hard drive emulation, you need a hard disk image file
+with a pre-installed HD driver in it. You can try to get an image of
+your old ST hard disk or grab one from the internet (e.g. from the
+Hatari website).
+Please note that the size of ACSI hard drive is normally limited to 1 GB
+due to some addressing constraints of the ACSI bus. Bigger disks were only
+possible with certain host adapters – this behaviour is emulated by
+Hatari, too, but you need a hard disk driver that supports these extensions.
+

+

+To create a new ACSI hard disk image, you can start with an empty
+image that you have created for example with the following command:
+dd if=/dev/zero of=hd.img bs=512 count=xxx
+(where 'xxx' is size in 512 byte blocks).  Copy the complete AHDI 5.0
+package to a floppy disk image, then boot Hatari with this floppy disk
+image and the fresh hard disk image like this:
+--acsi hd.img ahdi.st.
+Then start HDX.PRG from the floppy disk and format + partition the hard
+disk image with it.
+

+

+Formatting and partitioning works currently only with AHDI 5, but you
+can install the AHDI 6 driver to the hard disk after it's formatted.
+Restart the emulated system, run AHDI.PRG from the floppy disk to access
+the hard disk image from the emulated Atari and then run HINSTALL.PRG.
+After installing the hard disk driver to the fresh HD image with
+HINSTALL.PRG, you can boot directly from the hard disk image.
+

+

+HD Driver (v9) partitioning is also compatible with Hatari ACSI
+emulation. CBHD and ICDPro AdSCSI drivers work on images which have
+been partitioned elsewhere.
+

+
+
+
IDE hard drive emulation

+

+

+As the IDE disk format (little endian) differs from the ACSI disk format
+(big endian), you need separate disk images for them.  Hatari doesn't
+currently support partitioning IDE disks with AHDI, but you can do it with
+Cecile.
+

+

+First create an empty image file with the size of your choice with:
+dd if=/dev/zero of=hd.img bs=1k count=xxx.
+Then get the Cecile hard disk driver from
+http://centek.free.fr/atari/softs/s_cecile.htm
+and put it on a floppy disk image (e.g. to one named "cecile.st" using:
+zip2st.sh cecile.zip).
+

+

+Run Hatari with
+hatari --machine falcon --tos tos404.rom
+--ide-master hd.img cecile.st, switch to larger color resolution
+and warm up your French language skills. Then start the Cecile hard
+disk driver CECILE.PRG and run CC_TOOLS.APP to partition your hard
+disk image. Click the "Partition" button, select "Hatari IDE disk" and set
+suitable partition size with the arrows (below type field). Then click
+"Valider".
+

+

+If you only want to use your HD image in Falcon mode, you can install
+the Cecile hard disk driver to the image from the Cecile CC_TOOLS.APP:
+Click the "Installer" button and save the Cecile driver to the
+1st partition on "Hatari IDE disk". If you want to also use your HD
+image in ST/STE mode, you need to get and install either HD Driver or
+AHDI 6 driver on it instead (see ASCI
+hard drive emulation section).
+

+

+Then you can boot from your hard disk image by simply specifying it
+with the --ide-master parameter.
+

+
+
+
Moving files to/from hard disk images

+
+
Moving files to and from Atari hard disk images can be done
+either through GEMDOS HD partitions (host directories mounted inside
+Hatari emulation) or accessing the images directly on the host
+(outside the emulation).  Both have their own limitations.

+
+
If it's fine for the IDE/ACSI partitions to be first, you can
+either use ACSI/IDE partition skip option, or a multipartition GEMDOS
+HD setup as described in above sections.
+

+
+
If you want to boot from a GEMDOS HD partition i.e. such to be
+before hard disk image partitions, and still to be able to access all
+the IDE/ACSI partitions, you need to use HD Driver.  Note: this is the
+preferred method with EmuTOS (v0.9.x), because it doesn't run/use
+driver installed to the IDE/ACSI image directly although its own
+partition table/type support is very limited.

+
+
Using HD Driver with GEMDOS partitions

+
+
Uwe Seimet's HD
+Driver works fine with both the Hatari GEMDOS HD partitions and normal
+hard disk images.
+

+
+
First copy the HDDRIVER.PRG binary into your GEMDOS HD emulation
+directory AUTO folder. Then start the HDDRUTIL.APP configuration utility,
+locate HDDRIVER.PRG, open the
+"Devices
+and Partitions" dialog and select the "Preserve Existing Partitions"
+option.  Then you can just start Hatari with your hard disk image and
+this GEMDOS HD directory, for example like this:
+"hatari --harddrive gemdos-hd/ --ide-master
+ide-hd.image".

+
+
If you're using
+the demo version
+of HD Driver, you can write files only to the C: partition, i.e. in
+above case only copy files from the hard disk image partition to the
+GEMDOS HD partition (with some write slowndowns included into the demo
+version). If you want to copy files to the hard disk image with
+the demo version of the HD Driver, you need to set the hard disk
+image as drive C:.

+
+
To accomplish this, set the GEMDOS HD partitions to be from D: forward,
+i.e. have a directory which contains only single letter subdirectories,
+starting from "D" like in "mkdir gemdos-hd;
+mkdir gemdos-hd/D". Then give Hatari (as the last parameter)
+a boot floppy image containing the demo version of HDDRIVER.PRG in
+its AUTO folder, like this: "hatari
+--ide-master ide-hd.image --harddrive gemdos-hd/ hd-driver-floppy.st".
+You can convert HD Driver ZIP package to floppy image with the
+zip2st utility.

+
+
+
Accessing HDD image partitions outside of Hatari

+
+

+If you want to access the hard disk image partitions also outside
+the emulation, the disk image needs to have a DOS partition table.
+The atari-hd-image script included
+with Hatari can be used to create such an image.
+

+

+Inside the Hatari emulator, EmuTOS can access partition(s) on these
+kind of images directly without any driver software.  Of the Atari HD
+drivers mentioned above, Centek's Cecile and Uwe Seimet's HD Driver
+(demo) work fine with these partitions. E.g. AHDI and CBHD don't.
+Cecile works only with TT or Falcon.
+

+

+To summarise; if EmuTOS is enough, use that. Otherwise, if you want to
+use TT or Falcon emulation, use Cecile (or full HD Driver version if
+you have it), otherwise use HD Driver (demo).
+

+

+To access the content of the partitions on Linux host, there are two
+possibilities:
+
+
Using Mtools

+

+For this you need to add an entry for the hard disk
+image to your ~/.mtoolsrc and
+specify which partition you want to access from the image. For
+an image created with the above mentioned script, the line in
+the configuration file should look something like this:
+

+
+MTOOLS_NO_VFAT=1
+drive c: file="/home/user/hatari/hd.img" partition=1
+

+

+Note that Mtools is instructed to use FAT compatibility mode because
+EmuTOS cannot deal properly with VFAT file information.  If you don't
+want this setting for all your Mtools drives, you can set it also via
+the environment like this ("::" refers to the drive image given with
+the "-i" option):
+

+
+MTOOLS_NO_VFAT=1 mcopy -spmv -i hd.img files/* ::
+

+
+
Using a loopback device

+

+This is recommended even by Mtools documentation, but it's less
+convenient as it requires root rights. First you need to "loop"
+mount the image:
+

+
+$ su
+# image="hd.img"; mountdir="hd"
+# start=$(parted $image unit s print | awk '/ 1 /{print $2}' | tr -d s)
+# losetup -f $image -o $((512*$start))
+# loop=$(losetup -a | tail -1 | cut -d: -f1)
+# mkdir -p $mountdir
+# mount -t msdos $loop $mountdir
+

+

+This uses parted to find out the first
+partition offset in sectors and then tells losetup
+to bind the first free loop device to a corresponding offset from
+the hd.img image.
+mount is then used to mount the file system
+from the loop device on top of the "hd" directory.
+

+

+After you've copied the relevant files to the "hd" directory, you need
+unmount the file system and remove the loop device binding before using
+the disk image from Hatari:
+

+
+# umount $mountdir
+# losetup -d $loop
+

+
+
+
The debugger

+
+

+Hatari has a built-in debugging interface which can be used for
+analyzing code that runs in the emulated system.
+

+
+

+On Unix (Linux / OSX) debugger uses Hatari's parent console window, so
+make sure you run Hatari from the command line when you want to use
+the debugger.  On Windows you need to use "-W" option to get console
+window.  You can add an icon to your desktop that does it.  On Linux
+it should do something like this (replace "xterm" with your favorite
+terminal program):
+

+
+xterm -T "Hatari debug window" -e hatari
+

+
+

+To run debugger commands at Hatari startup, one can use the "--parse
+<file>" command line option.  This is useful e.g. for debugging
+TOS or some demo startup code, or if you always want to use some
+specific debugger setup (breakpoints etc).
+

+
+
+
Invoking the debugger

+
+

+You can invoke the debugger manually by pressing the
+AltGr + Pause key combination.
+

+
+

+With the "-D" command line option, you can toggle whether m68k
+exceptions will also invoke the debugger.  Which exceptions cause
+this, can be controlled with the "--debug-except" option.  
+

+
+

+Giving "-D" option at Hatari startup is not advised because TOS HW
+checks generate some exceptions at every TOS boot.  It's better to
+toggle exception catching later from the debugger with the "setopt -D"
+command. 
+

+
+

+Alternatively, you can give "--debug-except" option "autostart" flag
+(e.g. "--debug-except all,autostart").  This will enable catching of
+(specified) exceptions after TOS boot, when Atari program given on
+Hatari command line is autostarted.
+

+
+
+
General debugger use

+
+

+At the debugger prompt, type "help" to get a list of all
+the available commands and their shortcuts:
+

+
+Generic commands:
+           cd (  ) : change directory
+     evaluate ( e) : evaluate an expression
+         help ( h) : print help
+      history (hi) : show last CPU & DSP PC values & executed instructions
+         info ( i) : show machine/OS information
+         lock (  ) : specify information to show on entering the debugger
+      logfile ( f) : open or close log file
+        parse ( p) : get debugger commands from file
+       setopt ( o) : set Hatari command line and debugger options
+    stateload (  ) : restore emulation state
+    statesave (  ) : save emulation state
+        trace ( t) : select Hatari tracing settings
+         quit ( q) : quit emulator
+
+CPU commands:
+      address ( a) : set CPU PC address breakpoints
+   breakpoint ( b) : set/remove/list conditional CPU breakpoints
+       disasm ( d) : disassemble from PC, or given address
+      profile (  ) : profile CPU code
+       cpureg ( r) : dump register values or set register to value
+      memdump ( m) : dump memory
+     memwrite ( w) : write bytes to memory
+      loadbin ( l) : load a file into memory
+      savebin (  ) : save memory to a file
+      symbols (  ) : load CPU symbols & their addresses
+         step ( s) : single-step CPU
+         next ( n) : step CPU, proceeding through subroutine calls
+         cont ( c) : continue emulation / CPU single-stepping
+
+DSP commands:
+   dspaddress (da) : set DSP PC address breakpoints
+     dspbreak (db) : set/remove/list conditional DSP breakpoints
+    dspdisasm (dd) : disassemble DSP code
+   dspmemdump (dm) : dump DSP memory
+   dspsymbols (  ) : load DSP symbols & their addresses
+   dspprofile (dp) : profile DSP code
+       dspreg (dr) : read/write DSP registers
+      dspstep (ds) : single-step DSP
+      dspnext (dn) : step DSP, proceeding through subroutine calls
+      dspcont (dc) : continue emulation / DSP single-stepping
+

+
+
+
Entering arguments to debugger commands

+
+

+After writing (with TAB completion) one of the above command names,
+pressing TAB will (for most commands) show all the available subcommands.
+

+
+

+If you want to give numbers in other number bases
+than the default/selected one, they need to be prefixed with a
+character indicating this.  For decimals this prefix is "#" (#15),
+for hexadecimals "$" ($F), and for binary values it's "%" (%1111).
+

+
+

+By default debugger expects all numbers without a prefix to be
+decimals, but you can change the default number base with the "setopt"
+command, just give it the desired default number base (bin/dec/hex).
+When using the hexadecimal number base, remember still to prefix
+hexadecimal numbers with '$' if they could be confused with register
+names (a0-7, d0-7)!  Otherwise results from expressions and
+conditional breakpoints can be unexpected.
+

+
+
+
Calculations and immediate evaluation

+
+

+Instead of a number, you can also use an arithmetic expression, by
+surrounding it with quotes ("").  An expression can contain
+calculations with CPU and DSP register, symbol and Hatari variable
+values in addition to numbers. For example to give a sum of A0 and
+D0 register values to a command, use "a0+d0".
+

+
+

+Within arithmetic expressions parenthesis are used both to change
+the order of precendence and to indicate indirect addressing.
+Unlike with conditional breakpoint expressions (explained below), you
+cannot give size for the indirect addressing, a long value is always
+read from the RAM address given within parenthesis.  For example to
+get a long value pointed by stack pointer + 2, use "(a7+2)".
+

+
+

+Values of arithmetic expressions are always evaluated before being
+given to a command.  Except for "evaluate" and "address" commands,
+they always need to be marked with quotes (""). Besides arithmetics,
+this can be used also to give symbol/register/variable values to
+commands that don't otherwise interpret them.  If command complains
+that it didn't recognize e.g. a register name, just put it to quotes
+and it will be "evaluated" before being given to the command.
+

+
+

+With command argument completion (see build
+notes), result from the last "evaluate" command can be inserted
+by typing '$' and pressing TAB.
+

+
+
+
Inspecting emulation state

+
+

+In the beginning, probably the most interesting commands are "m" and "d"
+for dumping and disassembling memory regions.  You can use "dm" and "dd"
+commands to do the same for the DSP.
+

+
+> help memdump
+'memdump' or 'm' - dump memory
+Usage:  m [start address-[end address]]
+        dump memory at address or continue dump from previous address.
+

+
+> help disasm
+'disasm' or 'd' - disassemble from PC, or given address
+Usage:  d [start address-[end address]]
+        If no address is given, this command disassembles from the last
+        position or from current PC if no last position is available.
+

+
+> disasm pc
+$00aa6e : 2f08                                 move.l    a0,-(sp)
+$00aa70 : 0241 0fff                            andi.w    #$fff,d1
+$00aa74 : 207c 00fe 78c0                       movea.l   #$fe78c0,a0
+$00aa7a : 2070 1000                            movea.l   (a0,d1.w),a0
+$00aa7e : 4ed0                                 jmp       (a0)
+

+
+

+Both commands accept in addition to numeric addresses also register
+and symbol names, like in above example.  If you don't specify an
+address, the commands continue showing from an address that comes
+after the previously shown data.  "disasm" command default address
+will be reset to PC address every time you re-enter the debugger.
+

+
+

+Use "setopt --disasm help" if you want to set options controlling
+the disassembly output.
+

+
+

+You can use the "info" command to see state of specific sets of HW
+registers (e.g. "info videl") and Atari OS structures (e.g. "info gemdos").
+

+
+
+
Selecting what information is shown on entering the debugger

+
+

+By using the "lock" command, you can ask Hatari to show specific
+information whenever you enter the debugger / hit a breakpoint. For
+example to see disassembly from current PC address, use "lock disasm".
+

+
+

+With the "regaddr" subcommand, you see disassembly or memory
+dump of an address pointed by a given register ("lock regaddr disasm
+a0"). Of the DSP registers, only Rx ones are valid for this
+subcommand.
+

+
+

+"file" subcommand can be used to get (arbitrary number of) commands
+parsed and executed from a given debugger input file whenever debugger
+is entered.  With this you can output any information you need:
+

+
+lock file debugger.ini
+

+
+

+To disable showing of this extra information, use "lock default".
+Without arguments "lock" command will show the available options
+(like the "info" command does).
+

+
+
+
Debug symbols

+
+

+You can load debugging symbols to the debugger with the "symbols"
+command (and with "dspsymbols" for DSP). These symbolic names can be
+used in arithmetic expressions and conditional breakpoint expressions.
+They also show up in the "disasm" command output and you can trace
+calls to them with "trace cpu_symbols" (and DSP symbols with "trace
+dsp_symbols").
+

+
+
+
For a program under GEMDOS HD emulation

+
+

+If currently running program contains symbol table in DRI/GST format,
+and it's started from GEMDOS HD emulated drive, its symbol names /
+addresses are automatically loaded when debugger is entered, and
+removed when program terminates.

+
+

+Above happens only if there are no symbols loaded when the program
+starts. If there are, you can load program symbol data manually with
+the following command, after program has been loaded to the memory by
+TOS (see setting breakpoint at program
+startup):
+

+
+symbols prg
+

+

+
+

+The options you need to add suitable symbol table to your programs,
+depend on which toolchain you use to build it:
+

+

+
Devpac:

+
"OPT D+,X+"

+
AHCC:

+
"-g", and "-l" option for local symbols, both for linking

+
GCC:

+
"-Wl,--traditional-format" option for linking,
+    and "-g" for compilation to get local symbols

+
VBCC:

+
"-g" (can only be used at linking phase), when VBCC
+    configuration file uses "-bataritos" option for
+    the linker

+

+
+
You can view the generated symbols (and convert them to debugger
+ASCII format) with tool installed with Hatari:

+
+$ gst2ascii -l -o program.tos > program.sym
+

+(Options -l and -o are used to exclude useless symbols from the output.)
+
+
+
For a program on a (disk) image

+
+

+If the program isn't run from a GEMDOS HD emulated drive, but from a
+cartridge, floppy or HD image, you need to have the corresponding
+program also as normal host file which location you can give to the
+debugger:
+

+
+symbols /path/to/the/program.tos
+

+
+
+
ASCII debug symbol files

+
+

+If Hatari complains that your program doesn't have DRI/GST format
+symbol table, or its symbols are in some other format, and you
+cannot re-compile it to have them, you have two options:
+

+
    
+
  • Convert the symbols to ASCII format understood by the Hatari debugger.
+    Writing converters for other ASCII formats is easy, and Hatari already
+    contains covertors for DSP LOD files, nm
+    output for MiNT/a.out binaries and AHCC map files.
+
  • Create the ASCII symbols file by hand while you're debugging a program.
+

+
+
ASCII symbols file format is following:

+
+e01034 T random
+e01076 T kbdvbase
+e0107e T supexec
+

+

+Where 'T' means text (code), 'D' means data and 'B' means BSS section
+type of address.  The hexadecimal address, address type letter and the
+symbol name are separated by white space.  Empty lines and lines
+starting with '#' (comments) are ignored.
+

+
+

+Debugger will automatically "relocate" the symbol addresses when it
+loads them from a program binary, but with ASCII symbol files you need
+to give the relocation offset(s) separately, unless the symbol names
+are for fixed adresses (like is the case e.g. with EmuTOS):
+

+
+symbols program.sym TEXT DATA BSS
+

+

+If you're interested only about code symbols, you can leave DATA and
+BSS offsets out (the values of the above virtual debugger variables
+like TEXT come from the currently loaded program's basepage, they're
+set after the program is loaded by TOS, see "info basepage" output).
+

+
+
+
Breakpoints

+
+

+There are two ways to specify breakpoints for Hatari. First, there are
+the simple address breakpoints which trigger when the CPU (or DSP)
+program counter hits a given address. Use "a" (or "da" for the DSP)
+to create them, for example:
+

+
+a $e01034
+a some_symbol
+

+
+

+Note that address breakpoints are just wrappers for conditional
+breakpoints so you need to use "b" command to remove or list them.
+

+
+

+Then there are the conditional breakpoints which can handle much more
+complex break condition expressions; they can track changes to
+register and memory values with bitmasks, include multiple conditions
+for triggering a breakpoint and so on.  Use "b" (or "db" for the DSP) 
+to manage them.
+

+
+
Help explains the general syntax:

+
+> help b
+'breakpoint' or 'b' - set/remove/list conditional CPU breakpoints
+Usage:  b <condition> [&& <condition> ...] [:<option>] | <index> | help | all
+
+Set breakpoint with given <conditions>, remove breakpoint with
+given <index>, remove all breakpoints with 'all' or output
+breakpoint condition syntax with 'help'.  Without arguments,
+lists currently active breakpoints.
+

+
+

+Unless you give breakpoint one of the pre-defined subcommands ('all',
+'help'), index for a breakpoint to remove or no arguments (to list
+breakpoints), the arguments are interpreted as a new breakpoint
+definition.
+

+
+

+Each conditional breakpoint can have (currently up to 4) conditions
+which are separated by "&&".  All of the breakpoint's
+conditions need to be true for a breakpoint to trigger.
+

+
+
+
Breakpoint options

+
+

+Normally when a breakpoint is triggered, emulation is stopped and you
+get to the debugger. Breakpoint options can be used to affect what
+happens when a breakpoint is triggered.  These options are given after
+the conditions and are prefixed with ':'. 
+

+
+

+
<count>

+
Break only on every <count> hit. For example, to stop
+on every other time PC is at given address, use:
+
+a $1234 :2
+

+

+
+
once

+

+Delete the breakpoint when it's hit i.e. trigger it only once. It may
+be useful if you just want to get a specific address. Or if you're on
+an instruction that jumps back to a start of the loop and you want to
+finish the loop, you could use:
+
+b pc > "pc" :once
+continue
+

+

+
+
trace

+

+Continue emulation without stopping after printing the value that
+triggered the breakpoint and doing other possible option actions.
+This is most useful when investigating memory or register value
+changes (explained below).
+

+
+
lock

+

+Show the same information on breakpoint hit as you see when entering
+the debugger (see the "lock" command in
+Inspecting emulation state
+above).  This enables also trace option as you would anyway see this
+information if debugger would be entered.
+

+
+
file <file>

+

+Execute debugger commands from given <file> when this breakpoint
+is hit.  With this you have complete control over what information is
+show when the debugger is hit, you can even chain breakpoints (as
+explained in
+Chaining breakpoints later on)
+etc.  Use this if "lock" option isn't enough or you want different
+information show on breakpoints and when entering the debugger.
+

+
+
noinit

+

+Hitting breakpoint doesn't re-initialize debugger which would e.g.
+cause profiling data to be reset.  This implies trace option as
+entering debugger would also re-initialize debugger state. This option
+is mainly intended for breakpoints that use :file option to show
+backtraces with "profile stack" command during
+profiling.  See
+Usage examples section for an example.
+

+

+
+

+Note: you can give multiple options for conditional breakpoints, but
+for address breakpoints you can give only one these options.  And
+"file" option is supported only for conditional breakpoints.
+

+
+
+
Breakpoint conditions

+
+

+"b help" explains very briefly the breakpoint condition syntax:
+

+
+> b help
+condition = <value>[.mode] [& <mask>] <comparison> <value>[.mode]
+
+where:
+        value = [(] <register/symbol/variable name | number> [)]
+        number/mask = [#|$|%]<digits>
+        comparison = '<' | '>' | '=' | '!'
+        addressing mode (width) = 'b' | 'w' | 'l'
+        addressing mode (space) = 'p' | 'x' | 'y'
+

+
+

+For CPU breakpoints, mode is the address width; it can be byte ("b"),
+word ("w") or long ("l", default).  For DSP breakpoints, mode specifies
+the address space: "P", "X" or "Y". Note that on DSP only R0-R7
+registers can be used for memory addressing.  For example;
+
+db (r0).x = 1 && (r0).y = 2
+

+
+

+If the value is in parenthesis like in '($ff820)' or '(a0)', then the
+used value will be read from the memory address pointed by it.  Note
+that this conditional breakpoint expression value is checked at
+run-time whereas quoted arithmetic expressions (mentioned in
+Entering arguments
+to debugger commands above) are evaluated already when
+adding a breakpoint.  For example, to break when a value in an address
+(later) pointed by A0 matches the value currently in D0, one
+would use:
+

+
+b (a0) = "d0"
+

+
+

+If you're interested only on certain bits in the value, you can use
+'&' and a numeric mask on either side of comparison operator to
+mask the coresponding value, like this:
+
+b ($ff820).w & 3 = (a0)  &&  (a1) = d0 & %1100
+

+
+

+Comparison operators should be familiar and obvious, except for '!'
+which indicates inequality ("is not") comparison.  For example:
+

+
+b d0 > $20  &&  d0 < $40  &&  d0 ! $30
+

+
+
+
Tracking breakpoint conditions

+
+

+As a convenience, if the both sides of the comparison are exactly the
+same (i.e. condition is redundant as it's always either true or
+false), the right side of the comparison is replaced with
+its current value.  This way you can give something like this:
+

+
+b pc > "pc"
+

+
As:

+
+b pc > pc
+

+
+

+That in itself isn't so useful, but for inequality ('!') comparison,
+conditional breakpoint will additionally track and output all further
+changes for the given address/register expression. This can be used
+for example to find out all value changes in a given memory address,
+like this:
+

+
+b ($ffff9202).w ! ($ffff9202).w :trace
+

+

+Because tracking breakpoint conditions will print the evaluated
+value when it changes, they're typically used with the trace option
+to track changes e.g. to some IO register.
+

+
+
+
Breakpoint condition notes

+
+
    
+
  • 
+Any '!' condition should be given as the first condition. Because
+breakpoint evaluation is stopped ("short-circuited") when any of the
+conditions fails, the tracked value would not be updated correctly
+unless tracking condition is given as the first one.
+
    • 
+
+
  • 
+Hatari will internally update some register values without immediately
+updating the corresponding IO address range memory addresses.  For
+example the Busy bit for the internal Blitter control register is
+(internally) cleared when Blitter activity stops, but the actual IO
+address for that control register gets updated only when something
+actually writes or reads that IO address.  Many HW registers behave
+like this (status registers in FDC, ACIA, MFP, Blitter...).
+
    
+For breakpoints that track just a single IO register memory address, or
+multiple ones of which none are modified by Hatari,
+only by emulated code, this is not a problem, they get triggered as
+expected.
+
    
+However, if you have a breakpoint that tracks multiple IO registers
+where some of them are updated by Hatari, for example to check that
+other Blitter registers aren't updated while control register
+indicates Blitter to be active (busy), things don't work as expected!
+
    • 
+

+
+
+
Breakpoint variables

+
+

+In addition to loaded symbols, the debugger supports also setting
+conditional breakpoints on values of some "virtual" variables listed
+by "b help". For example:
+

+
    
+
  • If you want the emulation to stop on the first instruction of
+    next program; after TOS desktop is up, set a breakpoint on
+    the TEXT segment address given in a program basepage:
+
    +b  pc = TEXT :once
+
    
+Note1: It's better to trigger it only once because if you'd leave it on,
+during reboot you would get a warning for every instruction until TOS sets
+a valid basepage.
+
    
+Note2: you cannot use an address breakpoint for this because value of
+a variable given to address breakpoint is evaluated when it's set, not
+at run-time, so it cannot get the new value that the TEXT variable
+gets when you start a program.
+
    • 
+
  • To view current program DATA and BSS segment contents,
+    use the corresponding variables:
+
    +m  DATA
+m  BSS
+
    
+
    • 
+
  • If you want to stop at a specific cycle within a frame (that is,
+    PC relative to the current VBL/HBL in cycles), set breakpoints to
+    specific "HBL" and "FrameCycles" variable values.  If you for
+    example want to break after 20 HBLs, use:
+
    +b  HBL = "HBL+20"
+
    
+
    • 
+
  • Aes/Bios/Gemdos/LineA/LineF/Vdi/XbiosOpcode variables can be used
+    to catch AES, BIOS, GEMDOS, Line-A, Line-F, VDI and XBIOS OS-calls.
+    By default they contain the 0xffff value, so to trace e.g. all AES
+    calls, instead of a specific one, one needs to use something like this:
+
    +b  AesOpcode ! AesOpcode  &&  AesOpcode < 0xffff  :trace
+
    
+
    • 
+

+
+

+Hint: "info" command "aes", "bios", "gemdos", "vdi" and "xbios"
+subcommands for can be used to list the corresponding OS-call opcodes.
+For example, to see the GEMDOS opcodes, use:

+
+info gemdos 1
+

+
+
+
Chaining breakpoints and other actions

+
+

+As the file pointed by the breakpoint ":file" option (see
+Breakpoint options) can contain any
+debugger commands, it can also be used to do automatic "chaining" of
+debugger and breakpoint actions so that after one breakpoint is hit,
+another one is set.
+

+
+
For example if you have these input files:

+
    
+
  • "break.ini":
+
    +b GemdosOpcode = 0x3D :trace :once :file program.ini
+
    
+
    • 
+
  • "program.ini":
+
    +b pc = TEXT :trace :once :file trace.ini
+
    
+
    • 
+
  • "trace.ini":
+
    +symbols prg
+trace gemdos,cpu_symbols
+b VBL = "VBL+4" :trace :once :file disable.ini
+
    
+
    • 
+
  • "disable.ini":
+
    +trace none
+b all
+
    
+
    • 
+

+
+

+And then start Hatari with the first debugger input file and a GEMDOS
+HD directory containing "desktop.inf" file:
+

+
+hatari --parse break.ini /path/to/your/program.tos
+

+
+
    
+
  1. "break.ini" input file will break when TOS opens
+    the "desktop.inf" file (it's the first Fopen() i.e. GEMDOS call
+    0x3D done by TOS at boot) and the breakpoint will run
+    the debugger commands from the "symbols.ini" file
+
  2. "program.ini" will setup breakpoint to program startup
+    (because TEXT variable cannot be used before TOS has booted)
+
  3. "trace.ini" input file loads symbols for the run program, sets Hatari
+    to trace several things (see Tracing section
+    below) in the emulated system for few VBLs until breakpoint runs
+    commands from the "disable.ini" file
+
  4. "disable.ini" input file will disable tracing and remove
+    all (remaining) breakpoints
+

+
+
Note:

+
    
+
  • Because debugger input files cannot "continue"
+emulation, ":trace" option needs to be used for the breakpoint(s)
+if you want emulation to continue after the breakpoint action(s).
    • 
+
  • In simpler breakpoint chain (like above), new breakpoint just
+replaces the previous one, ":once" option tells that breakpoint
+isn't needed after it's hit.
+
    • 
+

+
+

+Hint: It's better to test each input file separate before testing the
+whole chain.  Besides the ":file" breakpoint option, these debugger
+input files can be also read with the debugger "file" command, "lock"
+command "file" option and with the Hatari "--parse" command line
+option.
+

+
+
Stepping through code

+
+

+After analyzing the emulation state and/or setting new breakpoints,
+you can continue the emulation with the "c" command. You can continue
+for a given number of CPU instructions (or DSP instructions when "dc"
+is used), or you can continue forever (until a non-tracing breakpoint
+triggers) if you omit the instruction count.
+

+
+

+If you want to continue just to the next instruction, use "s" (step)
+command to continue for exactly one instruction, or "n" (next), if you
+want to skip subroutine and exception calls.  "ds" and "dn" commands
+do the same for DSP.
+

+
+

+You can also continue with the "n" until instruction of certain
+type is encountered, by giving it the instruction type:
+
    
+
  • "branch" matches branch instructions: BCC, BRA, DBCC, JMP
    • 
+
  • "subcall" matches subroutine calls: BSR, JSR
    • 
+
  • "subreturn" matches return from subroutine: RTD, RTR, RTS
    • 
+
  • "exception" matches exceptions: BKPT, ILLG, STOP, TRAP, TRAPV
    • 
+
  • "exreturn" matches return from exception: RTE
    • 
+
  • "return" matches both subroutine and exception returns
    • 
+

+
+

+For example: "n branch", or "dn branch".
+

+
+

+(Note: CHK, CHK2, FBCC, FDBCC, & FTRAPCC exception / branch CPU
+instructions aren't supported currently.)
+

+
+
+
Tracing

+
+

+If you want e.g. to continue with real-time disassembling, you can
+enable it with "trace cpu_disasm" (or "trace dsp_disasm" for DSP) at
+the debugger prompt before continuing.
+

+

+Disable tracing with "trace none" when you enter the debugger again.
+"trace help" (or TAB) can be used to list all the (over 40) supported
+traceable things, from HW events to OS functions.
+

+

+Notes:
+

+
    
+
  • 
+If GEMDOS HD emulation isn't enabled, GEMDOS call tracing needs to be
+enabled at Hatari command line, it's not possible to enable it after
+TOS has initialized GEMDOS.
+
    • 
+
  • 
+AES, BIOS, GEMDOS and XBIOS traces show arguments for (most of) the
+calls, VDI trace shows only function calls (parsing the arguments
+would be too complicated).
+
    • 
+
  • 
+Tracing options can be set even from a program within the emulation,
+if you enable the Hatari "--bios-intercept" option and call XBios 255
+from the program with a suitable trace options string.
+
    • 
+
  • 
+Note that the trace output file can be set only when Hatari starts,
+it cannot be changed from within the debugger (or emulation).
+
    • 
+

+

+If there isn't a trace option for something you'd like to track,
+you may be able to use tracing breakpoints, explained above.
+For example, following tracks Line-A calls:
+

+
+b  LineAOpcode ! LineAOpcode  &&  LineAOpcode < 0xffff  :trace
+

+
+
+
Profiling

+
+

+Profiling tells where the emulated code spends most of its (emulated)
+time.  It can be used to find out where a program is (apparently)
+stuck, or what are the largest performance bottlenecks for a program.
+

+
+
Collecting the profile data

+
+

+Profiling is used by first enabling the profiler (use "dp" for DSP):
+

+
+> profile on
+Profiling enabled.
+

+

+And profiling will start once you continue the emulation:
+

+
+> c
+Returning to emulation...
+Allocated CPU profile buffer (27 MB).
+

+
+

+When you get back to the debugger, the collected profiling information
+is processed and a summary of in which parts of memory the execution
+happened, and how long it took, is shown:
+

+
+Allocated CPU profile address buffer (57 KB).
+ROM TOS (0xE00000-0xE80000):
+- active address range:
+  0xe00030-0xe611a4
+- active instruction addresses:
+  14240 (100.00% of all)
+- executed instructions:
+  4589668 (100.00% of all)
+- used cycles:
+  56898472 (100.00% of all)
+  = 7.09347s
+Cartridge ROM (0xFA0000-0xFC0000):
+  - no activity
+
+= 7.09347s
+

+

+(DSP RAM will be shown only as single area in profile information.)
+

+
+
+
Investigating the profile data

+
+

+When you're back in debugger, you can inspect the collected profile data:
+

+
+> h profile
+'profile' - profile CPU code
+Usage:  profile <subcommand> [parameter]
+
+        Subcommands:
+	        - on
+		- off
+		- counts [count]
+		- cycles [count]
+		- misses [count]
+		- symbols [count]
+		- addresses [address]
+		- callers
+		- stack
+		- stats
+		- save <file>
+		- loops <file> [CPU limit] [DSP limit]
+
+        'on' & 'off' enable and disable profiling.  Data is collected
+	until debugger is entered again at which point you get profiling
+	statistics ('stats') summary.
+
+	Then you can ask for list of the PC addresses, sorted either by
+	execution 'counts', used 'cycles' or cache 'misses'. First can
+	be limited just to named addresses with 'symbols'.  Optional
+	count will limit how many items will be shown.
+
+	'addresses' lists the profiled addresses in order, with the
+	instructions (currently) residing at them.  By default this
+	starts from the first executed instruction, or you can
+	specify the starting address.
+
+	'callers' shows (raw) caller information for addresses which
+	had symbol(s) associated with them.  'stack' shows the current
+	profile stack (this is useful only with :noinit breakpoints).
+
+	Profile address and callers information can be saved with
+	'save' command.
+
+	Detailed (spin) looping information can be collected by
+	specifying to which file it should be saved, with optional
+	limit(s) on how many bytes first and last instruction
+	address of the loop can differ (0 = no limit).
+

+
+
For example, to see which memory addresses were executed most
+and what instructions those have at the end of profiling, use:

+
+> profile counts 8
+addr:           count:
+0xe06f10        12.11%  555724  move.l    $4ba,d1
+0xe06f16        12.11%  555724  cmp.l     d1,d0
+0xe06f18        12.11%  555724  bgt.s     $e06f06
+0xe06f06        12.11%  555708  move.b    $fffffa01.w,d1
+0xe06f0a        12.11%  555708  btst      #5,d1
+0xe06f0e        12.11%  555708  beq.s     $e06f1e
+0xe00ed8         1.66%  76001   subq.l    #1,d0
+0xe00eda         1.66%  76001   bpl.s     $e00ed8
+8 CPU addresses listed.
+

+
+

+Then, to see what the executed code and its costs look like
+around top addresses:
+
+> profile addresses 0xe06f04
+# disassembly with profile data:
+# <instructions percentage>% (<sum of instructions>, <sum of cycles>, <sum of i-cache misses>)
+$e06f04 :             bra.s     $e06f10                    0.00% (48, 576, 0)
+$e06f06 :             move.b    $fffffa01.w,d1            12.11% (555708, 8902068, 0)
+$e06f0a :             btst      #5,d1                     12.11% (555708, 6685268, 0)
+$e06f0e :             beq.s     $e06f1e                   12.11% (555708, 4457312, 0)
+$e06f10 :             move.l    $4ba,d1                   12.11% (555724, 11125668, 0)
+$e06f16 :             cmp.l     d1,d0                     12.11% (555724, 4461708, 0)
+$e06f18 :             bgt.s     $e06f06                   12.11% (555724, 4455040, 0)
+$e06f1a :             moveq     #1,d0                      0.00% (16, 64, 0)
+Disassembled 8 (of active 14240) CPU addresses.
+

+

+Unlike normal disassembly, "profile addresses" command shows only
+memory addresses which instructions were executed during profiling.
+You get instruction cache misses only when using cycle-accurate 030
+emulation with a Hatari version configured to use WinUAE CPU core.
+

+If you have loaded symbol information, symbol names are shown above
+the corresponding addresses.  With the "profile symbols" command you
+get a list of how many times the code execution passed through the
+defined symbol addresses.
+

+
+
+
Profile data accuracy

+
+
Profile data accuracy depends on Hatari emulation accuracy.
+Profile data accuracy from most to least accurate when Hatari's
+default emulation options are used is following:

+
    
+
  • Executed CPU and DSP instruction counts are accurate.
    • 
+
  • DSP cycles counts (and their variance information) should be accurate.
+    
    • 
+
  • 030 CPU instruction cache miss information (provided by WinUAE CPU core)
+    is assumed to be accurate.
    • 
+
  • Cycles used by a given CPU instruction depend to some extent on what
+    instruction(s), and data in case of 030, was processed before it.
+    While Hatari has some (instruction pairing) heuristics to take
+    that into account for 68000, in general instruction cycles are
+    averages.  For 68000, cycles (provided by OldUAE CPU core) should
+    be fairly accurate, for 68030 they aren't (yet) not very accurate.
    • 
+

+
+
+
Caller information

+
+

+If you have loaded symbols (see Debug symbols)
+before continuing emulation/profiling, additional caller information
+will be collected for all the code symbol addresses which are called
+as subroutines.  This information includes callstack, call counts,
+calling instruction type (subroutine call, branch, return etc), and
+costs for those calls, both including costs for further subroutine
+calls and without them.
+

+
+
When debugger is re-entered, current callstack is output before
+profiling information:

+
+> a _P_LineAttack
+CPU condition breakpoint 1 with 1 condition(s) added:
+        pc = $30f44
+$030f44 : 48e7 3820                            movem.l   d2-d4/a2,-(sp)
+> c
+...
+CPU breakpoint condition(s) matched 1 times.
+        pc = $30f44
+Finalizing costs for 12 non-returned functions:
+- 0x32a3c: _P_GunShot (return = 0x32b7e)
+- 0x32b18: _A_FireShotgun (return = 0x3229a)
+- 0x3223a: _P_SetPsprite (return = 0x32e86)
+- 0x32e4e: _P_MovePsprites (return = 0x38070)
+- 0x37f44: _P_PlayerThink (return = 0x36ea0)
+- 0x36e44: _P_Ticker (return = 0x260e0)
+- 0x25dcc: _G_Ticker (return = 0x1e4c6)
+- 0x1e29e: _TryRunTics (return = 0x239fa)
+- 0x238e8: _D_DoomLoop (return = 0x2556a)
+- 0x24d7a: _D_DoomMain (return = 0x44346)
+...
+

+
+
("profile stack" command can be used in breakpoints with :noinit
+option to show backtraces during caller profiling.)

+
+
Other information collected during profiling is shown with
+following command:

+
+> profile callers
+# <callee>: <caller1> = <calls> <types>[ <inclusive/totals>[ <exclusive/totals>]], <caller2> ..., <callee name>
+# types: s = subroutine call, r = return from subroutine, e = exception, x = return from exception,
+#        b = branch/jump, n = PC moved to next instruction, u = unknown PC change
+# totals: calls/instructions/cycles/misses
+0xe00030: 0xffffff = 1 e, _main
+0xe000fe: 0xe00a0c = 1 b, memdone
+0xe0010a: 0xe04e34 = 1 s 1/5/72 1/5/72, _run_cartridge_applications
+0xe00144: 0xe04dbe = 1 s 4/118/1512 1/27/444, _init_acia_vecs
+0xe001ea: 0xe00ec6 = 1 b, _int_acia
+0xe0038c: 0xe04c28 = 1 s 1/191/2052 1/191/2052, _init_exc_vec
+0xe003a6: 0xe04c2e = 1 s 1/388/4656 1/388/4656, _init_user_vec
+...
+

+
+

+For example, if you don't know all the places from which a certain
+function is called, or in what context a certain interrupt handler can
+be called during the period you're profiling, profile caller
+information will tell you:
+

+
+callee: caller: calls: calltype:
+  |       |       |   /
+0x379:  0x155 = 144 r, 0x283 = 112 b, 0x2ef = 112 b, 0x378 = 72 s
+583236/359708265/1631189180 72/4419020/19123430, dsp_interrupt
+           |                       |                 |
+    inclusive costs         exclusive costs     callee name
+  (of calls from 0x378)
+
+Calltypes:
+- b: jump/branch
+- n: PC  just moved to next address
+- r: subroutine return
+- s: subroutine call
+

+

+(Most "calls" to "dsp_interrupt" were subroutine call returns (=r)
+to it from address 0x155.)
+

+
+

+With the execution counts in normal profiling data, caller information
+can actually be used to have complete picture of what exactly the code
+did during profiling.  Main/overview work for this analysis is best done
+automatically, by the profiler data post-processor (documented below).
+

+
+
+
Caller data accuracy

+
+
Everything about profile data accuracy applies also to caller costs,
+but there are additional things to take into account, mainly because
+profiler cannot determine when exceptions are being handled:

+
    
+
  • If there are exception(s) during a subroutine call, costs for
+    the exception handling will also be accounted for that subroutine.
+    This shouldn't be a problem unless those costs are very large,
+    i.e. check how much CPU your exception handlers take.
    • 
+
  • Indicated exception handler call type can be incorrect.
    • 
+
  • Profiled code doing return address related stack manipulations
+    confuses call tracking and produces incorrect results (profiler
+    has special code to handle EmuTOS AES switcher because of this).
+    Typically this produces large list of functions that are finalized
+    at profile end, so it should be easy to detect.
    • 
+
  • Compilicated recursive calls seem to sometimes cause inclusive
+    costs (ones including costs of further subroutine calls) to be
+    incorrect.  Sometimes this can be noticed by them being even
+    >100%.
    • 
+
  • On DSP, profiler heuristics assume (for speed reasons) that
+    conditional subroutine calls never call the very next
+    instruction (as that would be very bad/inefficient code).
    • 
+

+
+
+
Saving profile data to a file

+
+
It's useful to save the profile data to a file:
+
+> profile save program-profile.txt
+

+
+
With the saved profile disassembly (and optional caller information)
+you can more easily investigate what your program did during
+profiling, search symbols & addresses in it, and compare the
+results to profiles you've saved from earlier versions of your code.

+
+
You may even create your own post-processing tools for
+investigating the profiling data more closely, e.g. to
+find
+CPU/DSP communication bottlenecks.

+
+
+
Profile data post-processing

+
+
Saved profile data can be post-processed with (Python) script
+installed by Hatari, to:

+
    
+
  • Get lists of functions/symbols with highest costs.
    • 
+
  • Get callgraphs of what functions/symbols cause those
+    costs and what kind of call hierarchy the profiled code
+    has.
    • 
+
  • Export profile data in Valgrind's
+    Callgrind format
+    for viewing it in
+    Kcachegrind
+    GUI.
    • 
+

+
+
+
Providing symbols for the post-processor

+
+
When the data is post-processed, you should always provide
+the post-processor symbols for the profile code!  Relying just on the
+symbol in the profile data can cause costs to be asssigned to wrong
+symbol, if symbol's code wasn't called through symbol's own address,
+but by jumping inside its code.

+
+
If your code is in fixed location, you should tell
+post-processor to handle symbol addresses as absolute (-a):

+
+$ hatari_profile.py -a etos512k.sym emutos-profile.txt
+

+
+
Normal programs are relocated and you should instead give
+the symbols as TEXT (code) section relative ones (-r):

+
+$ hatari_profile.py -r program.sym program-profile.txt
+

+
+
If symbols are included to your binary in DRI/GST format, first they
+need to be extracted to the ASCII format
+understood by the post-processor:

+
+$ gst2ascii -l -o program.prg > program.sym
+

+
+
If there are some extra symbols that you don't want to see
+separately in profiles, because they aren't real functions,
+but e.g. loop labels, you can either remove them manually
+from the ASCII *.sym file, or filter them out with grep:
+

+
+$ gst2ascii -l -o program.prg | grep -v -e useless1 -e useless2 > program.sym
+

+
+
+
Post-processor provided statistics

+
+
Above post-processor examples just parse + verify the given data
+and produce output like this:

+
+Hatari profile data processor
+
+Parsing TEXT relative symbol address information from program.sym...
+[...]
+3237 lines with 1550 code symbols/addresses parsed, 0 unknown.
+
+Parsing profile information from program-profile.txt...
+[...]
+9575 lines processed with 368 functions.
+
+CPU profile information from 'program-profile.txt':
+- Hatari v1.6.2+ (May  4 2013), WinUAE CPU core
+

+
+
To get statistics (-s) and list of top (-t) CPU users in profile,
+add "-st" option:

+
+$ hatari_profile.py -st -r program.sym program-profile.txt
+[...]
+CPU profile information from 'program-profile.txt':
+- Hatari v1.6.2+ (May  4 2013), WinUAE CPU core
+
+Time spent in profile = 34.49539s.
+
+Calls:
+- max = 187738, in __toupper at 0x52b88, on line 8286
+- 1585901 in total
+Executed instructions:
+- max = 1900544, in flat_remap_mips+14 at 0x47654, on line 7020
+- 64499351 in total
+Used cycles:
+- max = 15224620, in flat_remap_mips+18 at 0x47658, on line 7022
+- 553392132 in total
+Instruction cache misses:
+- max = 184308, in _BM_T_GetTicks at 0x43b90, on line 4772
+- 4941307 in total
+
+Calls:
+  11.84%      187698  __toupper
+  11.48%      182105  _BM_T_GetTicks
+  11.48%      182019  _I_GetTime
+[...]
+Executed instructions:
+  34.83%    22462729  flat_generate_mips
+  14.08%     9080215  flat_remap_mips
+   8.55%     5515945  render_patch_direct
+   5.09%     3283328  _TryRunTics
+[...]
+Used cycles:
+  23.62%   130702768  flat_generate_mips
+  12.42%    68735832  flat_remap_mips
+   9.77%    54041148  _TryRunTics
+   5.80%    32111536  correct_element
+[...]
+Instruction cache misses:
+  37.03%     1829764  _TryRunTics
+  11.20%      553314  _BM_T_GetTicks
+   9.44%      466319  _NetUpdate
+   9.27%      457899  _HGetPacket
+[...]
+

+
+
If you want to see also symbol addresses and what is per call
+cost, add -i option:

+
+$ hatari_profile.py -st -i -r program.sym program-profile.txt
+[...]
+Executed instructions:
+  34.83%    22462729  flat_generate_mips   (0x04778a, 774576 / call)
+  14.08%     9080215  flat_remap_mips      (0x047646, 313110 / call)
+   8.55%     5515945  render_patch_direct  (0x047382, 29977 / call)
+   5.09%     3283328  _TryRunTics          (0x042356, 19660 / call)
+[...]
+Used cycles:
+  23.62%   8.14728s  130702768  flat_generate_mips  (0x04778a, 0.28094s / call)
+  12.42%   4.28461s   68735832  flat_remap_mips     (0x047646, 0.14775s / call)
+   9.77%   3.36863s   54041148  _TryRunTics         (0x042356, 0.02017s / call)
+   5.80%   2.00165s   32111536  correct_element     (0x04a658, 0.00001s / call)
+[...]
+Instruction cache misses:
+  37.03%     1829764  _TryRunTics          (0x042356, 10956 / call)
+  11.20%      553314  _BM_T_GetTicks       (0x043b90, 3 / call)
+   9.44%      466319  _NetUpdate           (0x041bcc, 5 / call)
+   9.27%      457899  _HGetPacket          (0x041754, 5 / call)
+[...]
+

+
+
(For cycles the "per call" information is in seconds, not as
+a cost count.)

+
+
If your profile file contains caller information, you should
+add -p option to see it, as that will also help in detecting symbol
+issues (see Interpreting
+the numbers):

+
+$ hatari_profile.py -st -p -r program.sym program-profile.txt
+[...]
+9575 lines processed with 368 functions.
+[...]
+Of all 1570498 switches, ignored 581 for type(s) ['r', 'u', 'x'].
+
+CPU profile information from 'badmood-level-load-CPU.txt':
+- Hatari v1.6.2+ (May  4 2013), WinUAE CPU core
+[...]
+Calls:
+  11.84%  11.84%      187698    187698  __toupper
+  11.48%  11.48%      182105    182105  _BM_T_GetTicks
+  11.48%  22.95%      182019    364038  _I_GetTime
+[...]
+Executed instructions:
+  34.83%  34.86%  34.86%    22462729  22484024  22484024  flat_generate_mips
+  14.08%  14.10%  14.10%     9080215   9091270   9091676  flat_remap_mips
+   8.55%                     5515945                      render_patch_direct
+   5.09%   5.11%  94.96%     3283328   3294022  61247717  _TryRunTics
+[...]
+Used cycles:
+  23.62%  23.69%  23.69%   130702768 131100604 131100604  flat_generate_mips
+  12.42%  12.46%  12.46%    68735832  68928816  68930904  flat_remap_mips
+   9.77%   9.80%  95.66%    54041148  54238744 529368824  _TryRunTics
+   5.80%   5.82%   5.82%    32111536  32193664  32193664  correct_element
+[...]
+Instruction cache misses:
+  37.03%  37.14%  98.57%     1829764   1835261   4870573  _TryRunTics
+  11.20%  11.24%  11.24%      553314    555191    555191  _BM_T_GetTicks
+   9.44%   9.49%  29.13%      466319    468782   1439340  _NetUpdate
+   9.27%   9.29%   9.37%      457899    459197    463217  _HGetPacket
+[...]
+

+
+
Now there's a message telling that some of the calls were ignored
+because according to their "call type", they were actually returns from
+exceptions, not real calls (this is mainly important for callgraph
+generation, discussed below).

+
+
+
Interpreting the results

+
+
In addition to accuracy issues mentioned in previous Profiling
+sections, function/symbol level costs have gotchas of their own.

+
+
The first cost percentage and count columns are sums for all
+the instructions that were in profile data file between
+the indicated symbol's address and the address of the next symbol
+(= "between-symbols" cost).

+
+
NOTE: If your symbol file doesn't contain addresses
+for all the relevant symbols, results from this can be misleading because
+instructions costs get assigned to whatever symbol's address
+happened to precede those instructions.  And you don't see which
+caller is causing it from caller info or callgraph either, as entry
+point for that time sink lacking a symbol means profiler hadn't
+tracked calls to it...

+
+
The next two cost percentage and count columns are for subroutine
+calls costs, first one for exclusive and latter for inclusive cost
+i.e. including costs for further subroutine calls.  Values are based on
+caller information documented above.

+
+
Reasons why between-symbol costs, and subroutine call costs can
+differ, are following:

+
    
+
  • Subroutine terminates before next symbol address: exclusive
+    cost is smaller than in-between cost because of missing
+    symbol information
+    (these are indicated with '*' in statistics).
    • 
+
  • Subroutine is called more through jumps/branches than through
+    subroutine calls: inclusive call count may be smaller than
+    in-between call count which includes branches/jumps.
    • 
+
  • Subroutine jumps/branches to another function instead of
+    using subroutine call, or function contains additional
+    (non-function) labels: exclusive cost is larger than
+    in-between cost.
    • 
+
  • Exception happening during subroutine call: exclusive cost is
+    (slightly) larger than in-between cost.
    • 
+

+
+
In the first case, you should check the profile data to find out
+whether there are missing symbols for executed function entry points.
+You can notice function entry points as address gap and/or code
+retrieving arguments from stack. Exit points can be seen from RTS
+instructions.

+
+
Second case can also be seen from the profile data.  Call count
+is same as count for how many times first instruction is executed
+(worst case: large loop on subroutine's first instruction).

+
+
While subroutine costs should be more accurate and relevant, due to
+code optimizations many of the functions are not called as subroutines
+(on m68k, using JSR/BSR), but just jumped or branced to.  Because of
+this, it's useful to compare both subroutine and between-symbols
+costs.  One should be able to see from the profile disassembly which
+of the above cases is cause for the discrepancy in the values.

+
+
NOTE: Before starting to do any serious source
+level optimizations, you should always verify from profile
+data (disassembly) where exactly the costs are in a function, to make
+sure your optimization efforts can actually help the performance.

+
+
+
Generating and viewing callgraphs

+
+
Callgraphs require that saved profile data contains caller
+function address information, i.e. symbols for the code should
+be loaded before starting profiling it (see
+loading symbol data).

+
+
Separate callgraphs will be created for each of the costs
+(0=calls, 1=instructions, 2=cycles) with the -g option:

+
+$ hatari_profile.py -p -g -r program.sym program-profile.txt
+[...]
+Generating 'program-profile-0.dot' DOT callgraph file...
+
+Generating 'program-profile-1.dot' DOT callgraph file...
+
+Generating 'program-profile-2.dot' DOT callgraph file...
+[...]
+

+
+
Callgraphs are saved in GraphViz
+"dot" format.  Dot files can be viewed:

+
    
+
  • With "dotty" program included with GraphViz
    • 
+
  • With XDot
+    Python GUI (best option on Linux), or some platform specific viewer
    • 
+
  • By converting dot file to PostScript or SVG format before
+    viewing it with viewers for those:
+
    +$ dot -Tsvg program-profile-1.dot > program-profile-1.svg
+
    
+    (problem with most PS/PDF and SVG viewers is that either they
+    don't allow zooming large callgraphs enough or they use huge
+    amounts of memory and get very slow)
+    
    • 
+

+
+
Produced callgraph will look like this:

+
+
+
Interpreting the callgraph:

+
    
+
  • Diamond shaped nodes are symbols called as subroutines.
+    Values listed in them are subroutine call costs; inclusive
+    (total) cost with exclusive (own) cost in parenthesis,
+    followed by inclusive cost count.  Exclusive cost is
+    shown only if it differs from inclusive one.
    • 
+
  • Ellipse shaped nodes are for other symbols (functions
+    called using jumps/branches, loop labels etc).  Values
+    listed in them are between-symbols costs, i.e. normally
+    they're included to inclusive (total) costs shown in
+    subroutine call node somewhere higher in call hierarchy.
    • 
+
  • Nodes which exclusive (own) or between-symbols costs
+    exceed default or explicitly given threshold value,
+    have gray background.
    • 
+
  • Both nodes, which inclusive or between-symbols cost exceeds
+    the threshold value, and the arrows to & from them,
+    are marked red.
+
  • Arrow types indicate call types; normal arrows subroutine
+    calls, circles branches/jumps, backarrows returns.
+    Exception calls and returns are indicated with dashed lines,
+    unknown calls with dotted lines.
    • 
+
  • Arrow text tells from which address (within the caller)
+    the call originated.  If symbol had multiple callers, text
+    includes count of calls from that particular address, and its
+    percentage is of all calls done to that symbol.
    • 
+

+
+
+
Making large callgraphs readable

+
+
If profile is for larger and more varied amount of code
+(e.g. program startup), the resulting callgraph can be so
+huge it's unreadable.

+
+
If your code has interrupt handlers, they can get called
+at any point, which can show in callgraph as "explicit" calls
+from the interrupted functions.  To get rid of such incorrect
+calls, give interrupt handler names to --ignore-to option:

+
+$ hatari_profile.py -p -g --ignore-to handler1,handler2 -r program.sym program-profile.txt
+

+
+
In large callgraph most of the functions aren't really interesting,
+because their contribution to the cost is insignificant. You can
+remove large number of them with --no-leafs and --no-intermediate
+options, those options act only on on nodes which costs are below
+given threshold.  Leaf nodes are ones which don't have any parents
+and/or children. Intermediate ones have only single parent and
+children (node calling itself is not taken into account).
+
+
Threshold for this is given with the --limit (-l) option.  With
+that it typically makes also sense to change the node emphasis
+threshold with --emph-limit (-e) option:

+
+$ hatari_profile.py -p -g -l 0.5 -e 2.0 -r program.sym program-profile.txt
+

+
+
If you're not interested in from how many different addresses
+a given function calls another function, use --compact option.  If you
+still see multiple calls between two nodes with it, the reason is that
+they happened through different call paths which were removed from
+the callgraph after --compact option was applied:

+
+$ hatari_profile.py -p -g -l 1.0 -e 2.0 --no-leafs --no-intermediate --compact -r program.sym program-profile.txt
+

+
+
If even this doesn't help, you can remove all nodes below
+the given cost threshold limit with --no-limited option, but this
+often doesn't leave much of a call hierarchy.  Instead you may
+consider removing all nodes except for subroutine call ones, with the
+--only-subroutines option.

+
+
If you have trouble locating nodes you're specially interested
+about, you can either color them differently with the --mark option,
+or exclude everything else from the callgraph except those nodes and
+their immediate callers & callees, with the --only option:

+
+$ hatari_profile.py -p -g --only func1,func2 -r program.sym program-profile.txt
+

+
+
Last option for reading the callgraph is using -k option to
+export the data for use in (Linux) Kcachegrind UI. Kcachegrind generates
+callgraphs on the fly, and just for the area around the function
+you selected, so navigating in callgraph may be easier.  It also
+shows the related profile disassembly, which can make verifying
+matters easier:

+
+$ hatari_profile.py -p -k -r program.sym program-profile.txt
+[...]
+Generating callgrind file 'program-profile.cg'...
+[...]
+$ kcachegrind program-profile.cg
+

+

+  Kcachegrind screenshot
+

+
+
+
Usage examples

+
+

+Here's a list of some common debugging tasks and how to do them
+with the Hatari debugger:
+

+
+

+
Stopping on program startup and examining its data

+
Please see Breakpoint variables
+and Inspecting emulation state
+sections.
+

+
+
Tracing specific things in the system

+
To trace e.g. all GEMDOS calls and IO operations, use:
+
+trace  gemdos,io_all
+

+Please see Tracing section for more information
+on tracing, what's possible with it and what are its limitations.
+

+
+
Stopping when certain PC address is passed Nth time

+
To stop e.g. after function/subroutine at $12345 is called for
+the 6th time:
+
+a  $12345 :6
+

+

+
+
Stopping when specific exception happens

+
Hatari's -D option doesn't invoke debugger on all exceptions and
+doesn't allow invoking debugger just for specific exceptions.  To
+stop at specific exception, one can check when it's called.
+At the start of memory is the CPU exception table for exception
+handler addresses, so to stop e.g. at bus error with some extra
+information, one can use following:
+
+history  on
+b  pc=($8)
+

+After bus error invokes debugger, 'history' command can then be used
+to see (executed memory addresses with their current) instructions
+leading to the error.  The most interesting vector addresses are:
+$8 (Bus error), $C (Address error), $10 (Illegal instruction),
+$14 (Division by zero).  See also --debug-except option.
+

+
+
Stopping when register has a specific value

+
To stop when e.g. D1 register contains value 5, set a breakpoint on:
+
+b  d1 = 5
+

+

+
+
Stopping when a register value changes

+
To stop when e.g. D1 register value changes, set a breakpoint on:
+
+b  d1 ! d1
+

+

+
+
Stopping when register value is within some range

+
To stop when e.g. D1 register value is within range of 10-30,
+set a breakpoint on:
+
+b  d1 > 9  &&  d1 < 31
+

+

+
+
Stopping when memory location has a specific value

+
To stop when e.g. bit 1 of the Video Shifter Sync Mode byte at
+IO address $ff820a is set i.e. video frequency is 60Hz, set
+a breakpoint on:
+
+b  ($ff820a).b & 2 = 2
+

+

+
+
Stopping when a memory value changes

+
To stop when above bit changes, set a breakpoint on its value
+being different from the current value ('!' compares for inequality):
+
+b  ($ff820a).b & 2 ! ($ff820a).b & 2
+

+

+
+
Tracing all changes in specific memory location

+
To see the new values and continue without stopping, add
+the ":trace" breakpoint option:
+
+b  ($ff820a).b & 2 ! ($ff820a).b & 2  :trace
+

+

+
+
Stopping at specific screen position

+
To stop e.g. when VBL is 100, HBL is 40 and line cycles is 5,
+use the corresponding debugger variables:
+
+b  VBL = 100  &&  HBL = 40  &&  FrameCycles = 5
+

+

+
+
Stopping after value increases/decreases by certain amount

+
To stop e.g. after D0 value has increased by 10, set breakpoint on:
+
+b  d0 = "d0 + 10"
+

+

+
+
Examining specific system call return value

+
To check e.g. what's the Fopen() GEMDOS call return value,
+check with "info gemdos 1" its opcode, set a breakpoint for that
+and step to next (n) instruction from the trap call when breakpoint
+is hit. GEMDOS call return value is then in register D0:
+
+> trace  gemdos
+> b  GemdosOpcode = $3D
+> c
+[...continue until breakpoint...]
+1. CPU breakpoint condition(s) matched 1 times.
+        GemdosOpcode = $3D
+> n
+GEMDOS 0x3D Fopen("TEST.TXT", read-only)
+> e  d0
+= %1000000 (bin), #64 (dec), $40 (hex)
+

+

+
+
Seeing code leading to a breakpoint

+
To see CPU instructions executed before debugger was entered,
+you need to enabled history tracking before it. Whenever
+debugger is entered, you can then request given number (here 16) of
+past instructions to be shown:
+
+history  cpu
+c
+[breakpoint is hit and debugger entered]
+history  16
+

+

+
+
Getting instruction execution history for every breakpoint

+

+To see last 16 instructions for both CPU and DSP whenever
+(a normal or tracing) breakpoint is hit:
+
+history  on
+lock  history 16
+c
+

+

+
+
Single stepping so that new register values are shown after each step

+

+
+lock  registers
+s
+[new register values]
+s
+[new register values]
+...
+

+

+
+
Showing current stack contents

+
To see first 64 bytes on top of the stack, use:
+
+m  "a7-64"-a7
+

+

+
+
Seeing specific information each time debugger is entered

+
To see above information whenever some breakpoint is hit,
+you enter debugger manually etc, write that command to e.g.
+stack.ini file and then use:
+
+lock  file stack.ini
+

+Please see also Chaining breakpoints
+section for more examples on what you can do with the debugger input files.
+

+
+
Finding where a program or the OS is stuck

+
Profiling tells from which addresses CPU is executing the instructions:
+
+profile  on
+c
+[after a while, use AltGr+Pause to get back to debugger]
+profile  counts
+

+Please see Profiling section for more info.
+

+
+
Seeing program callstack when breakpoint is hit

+
Profiler caller data includes
+callstack information (with some limitations).
+

+
+
Seeing call backtraces whenever given function is called

+
Enable profiling, load symbols for the program and set breakpoint
+for the function you're interested about, in the following way:
+
+profile on
+symbols prg
+b  pc = _my_function  :quiet :noinit :file showstack.ini
+

+I.e. whenever 'my_function' address is called, quietly trigger a
+breakpoint without reseting profiling (callstack) information and run
+debugger command(s) from the 'showstack.ini' debugger script file,
+which contains following command:
+
+profile stack
+

+

+
+
Seeing how program functions/symbols call each other

+
Profile data
+post-processing can provide execution callgraphs.
+

+
+

+
+

+Hint: for most of the above commands, one just needs to prefix them with
+"d" (or "dsp" when using full command names) to do similar operation on
+the DSP.
+

+
+
+
Build notes

+
+

+Lastly, the debugger is much nicer to use with the command line
+history, editing and especially the completion support for the
+command, command argument and symbol names.
+

+

+If you're building Hatari yourself, please make sure that you have the
+GNU readline development files installed (on Debian / Ubuntu these
+come from the libreadline5-dev package). Otherwise the name completion
+and other features don't get enabled when you configure Hatari.
+

+

+ENABLE_TRACING define needs to be set for tracing to work.
+By default it should be enabled.
+

+
+
+
Performance

+
+
Hatari performance varies between Atari programs, depending on what
+features Hatari needs to emulate for them.  Less accurate Atari
+emulators may be faster as emulation accuracy has a performance
+overhead.

+
+
The operating system and libraries below Hatari can also sometimes
+have a noticeable effect on performance.

+
+
+
Improving Hatari performance

+
+

+Hatari currently runs best in 16 or 32 bits per pixel color depth
+mode, so try to avoid 24 bits per pixel display modes if possible.
+16-bit mode is fastest.
+

+
+

+On OSX, frame skipping, zooming and drive LED options (listed below)
+seem to have a large effect on performance in the windowed mode.
+This is apparently due to issues in the SDL OSX backend and how OSX
+itself composites non-fullscreen window contents. OSX uses always
+32-bit mode.
+

+
+

+Unless you've disabled compiler optimizations (like GCC's -O2 or -O3
+options) in the Hatari build, the extra optimization flags (like GCC's
+"-mtune=i686") don't seem to have very large effect on Hatari
+performance.  Using GCC -O3 option instead of -O2 can give minor
+(5-10%) performance improvements for things (demos) that use very
+heavily interrupts.
+

+
+

+However, Hatari can be sped up considerably by giving up some
+emulation or emulator accuracy.  Except for DSP, these options
+should be needed only on very slow devices like handhelds. See below.
+

+
+

+If nothing else helps, try an earlier Hatari version.  More accurate
+emulation or emulator output in newer Hatari versions means that they
+can be slower despite optimizations.
+

+
+
+
Emulation options

+
+

+Emulation options have the largest impact on performance.
+These options can be changed from the Hatari GUI System dialog and
+the emulation needs to be rebooted for any of these changes to take
+an effect!  They're enabled by default.
+

+
+
DSP

+

+Emulating the Falcon DSP is performance-wise several times more demanding
+than emulating the m68k; DSP runs at higher frequency, executes many
+instructions for each m68k instruction and emulation isn't as mature
+and optimized.  Unless some Falcon program needs DSP, none or
+dummy DSP emulation mode could be used.  Even of the programs
+that do use DSP, many use it only for background music and work
+fine without the real DSP emulation.
+

+
+
Timer-D

+

+The single largest factor contributing to general Hatari emulation
+performance is the handling of interrupts.  Enabling Timer-D patching
+option (about) doubles Hatari ST/STE emulation performance as it
+significantly reduces the number of interrupts generated by the emulated
+Atari machine. Using this has adverse effect only for very rare programs.
+

+
+
FDC

+

+While accurate FDC emulation doesn't take that much CPU, it slows down
+floppy image accesses (and Hatari startup) a lot.  Only very
+few demos and games require accurate FDC emulation for their copy protection,
+so enabling fast floppy access is fairly safe.
+

+
+
Compatible CPU

+

+After the DSP and  interrupts, m68k emulation takes most time.
+Disabling the "Slower but more compatible CPU" option will speed up
+the emulation a lot, but it won't anymore be cycle accurate.  This can
+be fine for many games and other programs, but won't work e.g. for demos
+using overscan or rasters.
+

+
+

+Roughly speaking, for DSP emulation, one needs at least 2Ghz machine.
+For normal (unpatched) Timer-D frequency on some specific cases (like
+demos with overscan 512 color animations) one may need over 1GHz
+machine, but some rare ST/STE demos may require over 1GHz machine even
+with Timer-D patching.  For "Compatible CPU" one needs at least 1/2Ghz
+machine.
+

+
+

+NOTE: Above options may cause some programs to work in correctly.
+The Hatari Software Compatibility List
+lists programs known to need real real Falcon DSP emulation, Timer-D
+frequency or accurate FDC timings.  Disabling "Compatible CPU" option
+is recommended only as a last resort.
+

+
+
+
Emulator options

+
+

+Emulator options don't usually have as large effect on performance as
+emulation options, but they don't affect the emulated programs at all,
+just the quality of the emulation "output". These options can also
+be toggled at run-time without rebooting the emulation.
+

+
+
Sound

+

+Internal Hatari sound handling and the SDL_mixer sound thread
+libALSA sound processing can account up to 1/3 of the Hatari CPU usage
+in normal ST/STE emulation. Disabling sound will get rid of that.
+Using low sound frequency or one matching your sound card may also help.
+Best is if you disable also background music from the programs you run
+in Hatari as this can significantly reduce the number of generated
+interrupts.
+

+
+
Frame skipping

+

+Screen rendering can take noticeable amount of CPU time. The default
+Hatari "auto" frame skipping should be used unless there's a good
+reason not to.  It will skip converting and showing some of the frames
+if there's not enough time for them.
+

+

+Also, if your monitor refresh frequency is lower than the selected
+Hatari monitor frequency (e.g. LCD monitors usually use 60Hz whereas
+Atari monochrome monitor uses 71Hz), you should use frameskip of one.
+The reason is that if your SDL library uses VSync to synchronize the
+output to screen (like OSX one?), with zero frame skip that forces the
+emulation to run slower than a real Atari.  If SDL doesn't use VSync,
+Hatari does redundant work to convert frames you can't see.
+

+
+
Zooming

+

+If you are not using frame skip, disabling zooming can have
+noticeable improvement on performance.  You can do this by specifying
+suitably low "Max zoomed" resolution (--zoom
+1 command line option sets it to 320x200).  If you still want to
+have a nice fullscreen mode, you should rather add the right resolution
+mode-lines (e.g. "320x200") to your xorg.conf file.  If you still want
+to use zooming, disabling borders may help a bit.
+

+
+
Spec512 color handling

+

+Handling Spec512 color modes which change the ST/e palette constantly
+takes some extra CPU.  If you have problems with CPU usage in such
+screens and you care more e.g. from the sound quality than visuals, you
+can either increase the threshold or disable the Spec512 mode handling
+completely by zeroing the threshold for that with the
+--spec512 0 option.
+

+
+
Statusbar and drive LED

+

+If your version of the SDL library uses VSync to synchronize the screen
+output, drawing of the statusbar or the drive LED may have some minor
+impact on performance too.  Normally they shouldn't.
+

+
+
+
Measuring the performance

+
+

+There are a couple of ways to monitor and measure Hatari performance.
+

+

+By default Hatari has Statusbar visible and automatic frameskip
+enabled. When Hatari has enough time that it can sleep a little each
+frame, the statusbar frame skip ("FS") value keeps at zero.  If Hatari
+is completely busy, it will increase to the maximum specified
+(automatic) frame skip value.
+

+

+Hatari has also a facility to measure FPS i.e. Frames Per Second.
+Just enable the --fast-forward option
+on command line (or use the corresponding keyboard shortcut), and
+after a while, press the "Pause" key.  Whenever Hatari emulation is
+paused, Hatari will output on console how many VBLs it could show per
+second along with some other numbers.
+

+

+It depends on what you want to measure, but usually it's best to
+disable sound and set high frame skip like
+--sound off --frameskips 60 so that
+the associated external overheads are minimized.  E.g. video output
+can on some platforms do VSync and measurements would then show your
+monitor refresh frequency instead of the actual Hatari performance.
+

+

+On Unix systems with times() function
+call, only the time spent by the Hatari process itself is measured.
+On other systems, much less accurate SDL "wall clock" timings are
+used.  To make latter more accurate you could use also
+--run-vbls option to specify how many
+VBLs Hatari should run before it exits.  In this case it's best to
+either have the test-case run automatically from the AUTO-folder or
+given as memory snapshot to Hatari with the frame skip set equal to
+the VBL count.
+

+

+Note that these numbers can fluctuate quite a bit, especially
+when the SDL timings are used, so for (statistically) reliable numbers
+you may need to repeat the measurement several times.  You should of
+course make also sure that the system doesn't have any other activity
+at the same time you're making the measurements.
+

+
+
+
Appendix

+
+
Copying

+
+

+
This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the
+Free Software Foundation; either version 2 of the License, or (at your
+option) any later version. 

+
This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
+Public License for more details. 

+

+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation,
+Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA
+

+

+
The GNU Project and the Free Software
+Foundation | The
+GNU General Public License

+
+
Introduction to Emulation

+
+
Emulation via software is an art and Hatari is an example of this.

+
Emulation is to make a computer behave like a (probably) completely
+different machine on the lowest possible niveau.
+This includes CPU and custom chip emulation allowing software written
+for the emulated machine to be run without notice.
+A good emulator will run most of the software intended for the emulated
+platform without trouble.
+

+

+The key to emulation is to simply do those things with a software
+program, the emulator, that normally chips would perform.
+So you have an CPU emulator that basically consists of a large loop
+that does exactly what the real thing would do:
+

+
    
+  
  • fetch an instruction from virtual memory
    • 
+  
  • interpret this instruction
    • 
+  
  • fetch operands from the emulated registers and memory
    • 
+  
  • perform the operation like addition or changing the program
+counter on a jump instruction
    • 
+  
  • writes results back into the intended registers or memory
+locations
    • 
+  
  • increment of the program counter and loop
    • 
+

+

+The typical von-Neumann CPU can be emulated very fast, stable and
+error-free using such a simple loop system.
+

+

+But in most cases the CPU emulation is the simplest part. Correct
+emulation of the various custom chips and hardware
+parts of the emulated system is much trickier.
+

+
+

+
+
+
diff --git a/doc/memory-usage.txt b/doc/memory-usage.txt
new file mode 100644
index 0000000..71ad49b
--- /dev/null
+++ b/doc/memory-usage.txt
@@ -0,0 +1,145 @@
+
+HATARI MEMORY USAGE
+
+Here are some stats on Hatari v1.2+ memory usage (on Linux) and what
+could be done to decrease it.
+
+First the binary size from "size ./hatari":
+   text    data      bss       dec
+1489120   12828 18799688  20301636
+
+I.e. the Hatari binary size is 1.4MB, it has 12KB of non-const/pre-defined
+arrays and 18MB of uninitialized (at build-time) fixed size arrays.
+The names of latter are listed below.
+
+To decrease the binary size slightly, disable DSP from src/Makefile,
+don't enabled tracing in config.h (latter may have trivial improvement
+on speed too).  You may also try the gcc "-Os" or "-O3 -finline-limit=..."
+options, their effect depends on the architecture for which Hatari is
+being compiled.
+
+
+To see the objects in the Hatari 18MB BSS section, get the datadump
+script from here:
+     http://live.gnome.org/MemoryReduction_2fTools
+
+Compile Hatari without stripping, and use:
+     datadump.py -n -s .bss -r ./hatari
+
+As a result you see these array variables:
+16777216 STRam hatari
+  404400 dsp_core hatari
+  324048 CyclePalettes hatari
+  262144 mem_banks hatari
+  262144 cpufunctbl hatari
+  176612 ConfigureParams hatari
+  131072 pInterceptWriteTable hatari
+  131072 pInterceptReadTable hatari
+   69632 InternalDTAs hatari
+   65536 ymout5_u16 hatari
+   32768 MixBuffer hatari
+   32768 DspOutBuffer hatari
+   ...
+
+These empty arrays aren't an issue unless Hatari actually writes to
+them, but that will happen as Hatari uses them.  Here are some ways
+to minimize dirtying of the related memory i.e. use of the arrays
+in Hatari:
+
+* Enabling only required amount of memory for the emulation.
+  Hatari doesn't dirty (zero) all of STRam, just the part of the ST ram
+  that user has configured (accessible as ST ram, 0.5-14MB) and 2MB
+  at the top (used as IO-memory, TOS and cartridge memory).
+
+* Disabling DSP from build gets rid of dsp_core
+
+* Modifying Video_ClearOnVBL() and Video_ColorReg_WriteWord()
+  to call Spec512 functions only when nSpec512Threshold configuration
+  value is non-zero and run Hatari with spec512 support disabled.
+  This gets rid of CyclePalettes dirtying
+
+* ConfigureParams size can be decreased 22*4KB by setting
+  MAX_HARDDRIVES in configuration.h to one (or by removing
+  memset from Configuration_SetDefault() as static variables in .bss
+  are zeroed already by kernel, memset()ting them just makes them
+  dirty and Configuration_SetDefault() is called only at Hatari startup).
+
+
+When I profiled Hatari with Valgrind (valgrind.kde.org) Massif plugin,
+it tells that Hatari does about 3MB of memory worth of dynamic
+allocations. The allocations and ways to make them smaller are:
+
+* In includes/vdi.h decrease MAX_VDI_WIDTH and MAX_VDI_HEIGHT
+  to 640 and 400. As Hatari allocates 2*2 framebuffers (of size
+  width*height/8) for page flipping in Screen_Init(), decreasing
+  their size can have have a large effect.
+
+* Do not load bigfont in gui-sdl/sdlgui.c, especially if the device
+  screen is smaller than VGA.  Both fonts together take about 1/3 MB.
+
+* Change uncompressed file read to use mmap() instead, currently
+  memory is allocated for the whole disk image before reading it.
+  - With normal DD floppy image Hatari would use that amount which
+    might be acceptable, but with e.g. 2MB disk needed for running
+    Wolf3D v0.8, mmap() sounds much better
+  - For compressed disk images memory needs to be allocated for
+    uncompressed image data, i.e. there we cannot save memory.
+
+* Check whether the m86k instruction table could be made smaller:
+        #include "uae-cpu/readcpu.h"
+        printf("%d -> %d\n", sizeof(struct instr), sizeof(struct instr) * 65536);
+  On x86 it's slightly over 1MB.
+
+You can also Massif Hatari yourself, its allocation calltrees
+are very short & the allocations are easy to find in the Hatari
+source code.
+
+
+From /proc/sysvipc/shm one can see how much shared memory Hatari/libSDL
+has allocated and that it shares it with the X server:
+- >100KB in lowrez
+- ~200KB in lowrez with borders
+- ~500KB in monochrome or zoomed lowrez
+- >800KB in zoomed lowrez with borders
+
+I don't think these could be made smaller from the code. Besides,
+user can just use a the smaller Hatari screen mode in fullscreen and
+let the display scale it to fullscreen.
+
+
+According to Xrestop, Hatari doesn't keep any Pixmap resources
+at the X server side.
+
+
+Finally when looking at the Hatari process with "pmap", you can
+see that the libraries Hatari links don't use so much private
+(writable) memory, only couple of hundred KB:
+    pmap $(pidof hatari) | grep / | grep rw
+
+To see how much from the memory pmap tells Hatari to have allocated is
+actually used/dirtied, take a peek at: /proc/$(pidof hatari)/smaps.
+
+Of the rest of the 40MB Hatari VMSIZE you see in "top" (about 16MB),
+half is unused/clean 8MB memory (allocated by kernel for the SDL sound
+thread stack) and half goes to shared library code (their .text
+sections with "r-x" rights) that Hatari links against.  The libraries
+are most likely used also by other programs and even if they aren't,
+it's memory mapped read-only / read in on-demand pages & pagable back
+to disk so it's shouldn't be much of a problem either.
+
+
+Unmodified Hatari runs on (Linux) systems having about 20MB of _free_
+memory (e.g. according to /proc/meminfo free+buffers+cached fields)
+and more RAM in total than the Hatari VMSIZE.
+
+Using low-rez without borders nor zooming, setting emulated ST memory
+amount to <=1MB, limiting the VDI screen size, disabling DSP and
+removing bigfont (discussed with Massif findings above) should enable
+running Hatari well on a system with only 10MB free memory, if it's
+otherwise fast enough.
+
+
+	- Eero Tamminen
+
+PS. Any device fast enough to run Hatari at reasonable speed
+should already have enough memory for it...
diff --git a/doc/midi-linux.txt b/doc/midi-linux.txt
new file mode 100644
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+
+Getting (Linux) ALSA midi support and MIDI networking working with Hatari
+=========================================================================
+
+If you don't have a real MIDI sequencer, you can use the MIDI synthesizer
+of your sound card (if available) or use a software synthetizer.
+
+For (Debian) package names and links to software referenced in this
+text, see end of the text. Most of the distros should have in their
+repositories packages at least for some of them though.
+
+Contents:
+- Using a soundcard with built-in MIDI synthesis capability 
+- Making MIDI soft-synthetizer to work with ALSA
+- Using FluidSynth instead of Timidity
+- Other software synthetizers
+- Making it all to work with Hatari
+- MIDI and networking
+- Linux & Atari MIDI related software
+- Additional documentation
+
+
+Using a soundcard with built-in MIDI synthesis capability 
+---------------------------------------------------------
+
+If your soundcard is capable of playing MIDI sound (i.e. you can play a .mid
+file with the "aplaymidi" command using the appropriate port), you can use this
+synthesis device for Hatari, too. However, you still might have to install and
+connect a virtual midi device, so that Hatari can access it through a
+/dev/snd/midiC*D* device file (see instructions below).
+
+Please note that you might also have to load instrument patches into your sound
+card first, for example with the program "sfxload" for AWE64 based sound cards,
+or with the program "sbiload" for OPL3 based sound cards.
+
+
+Making MIDI soft-synthetizer to work with ALSA
+-----------------------------------------------
+
+Make Timidity into an ALSA output device with:
+  timidity -Os -iA
+(-O: output=alsa, -i: interface=alsa)
+
+To make it use less CPU and be more responsive, use:
+  timidity -Os -iA -B2,8 -EFreverb=0 -EFchorus=0
+(-B: 2,8=set small buffers, -EFx=0: disable effects)
+
+Make vkeybd (virtual midi keyboard app) into an ALSA input device with:
+  vkeybd
+Or  use the newer & nicer looking "Virtual MIDI Piano Keyboard":
+  vmpk
+
+View the resulting (software) ALSA input and output devices:
+  aconnect -i -o
+
+Then connect the vkeybd output port to the timidity input port with:
+  aconnect  
+Or use one of the GUI programs for this like kaconnect, aconnectgui etc.
+
+Now you can use the virtual midi keyboard for testing the sound
+synthesis.
+
+
+Finally you can test how well midi files are played.
+Check which ALSA port Timidity provides:
+  aplaymidi -l
+
+And use that port for playing a midi file:
+  aplaymidi -p  test.mid
+(or use 'pmidi')
+
+Note: Remember that you need to re-connect the (virtual) device
+ports each time you restart them.
+
+
+Using FluidSynth instead of Timidity
+------------------------------------
+
+Instead of Timidity, you also use other soft-synthetizers,
+like FluidSynth:
+  fluidsynth --audio-driver=alsa --midi-driver=alsa_seq soundfont.sf2
+
+You could play a bit with other options to get more performance,
+sound volume etc:
+  --reverb=no --chorus=no -o synth.polyphony=16 --gain=0.6
+
+And if you don't like the FluidSynth shell, use:
+  --no-shell --server
+
+Qsynth provides a GUI for above:
+  qsynth 
+
+Note: FluidSynth v1.0.7a in older (obsolete) Linux distros has buffer
+overruns, but they're fixed in v1.0.8 or newer that are in the current
+Linux distros.
+
+
+Other software synthetizers
+---------------------------
+
+Of the other soft-synthetizers, I like also Horgand organ emulator
+as it has pretty good organ sound, but it needs Jack connection kit
+(+ e.g. qjackctl) for sound to work properly (not have sound underruns).
+
+
+Making it all to work with Hatari
+---------------------------------
+
+Hatari requires midi hardware devices to work, it doesn't support
+ALSA directly.  To get the software synth ALSA devices to appear
+as HW midi devices, run following as *root*:
+  modprobe snd-virmidi
+
+When you list your ALSA output devices with:
+  aconnect -o
+You should see in addition to the soft-synth also 4 virtual hardware
+devices.
+
+Then connect (with aconnect or one of the GUIs) the first virtual
+HW port to the same soft-synth port where you connected the virtual
+midi keyboard.
+
+Check which number was assigned by ALSA to the new virtual midi card:
+  cat /proc/asound/cards
+
+And give to Hatari the corresponding ALSA midi device.  In my case
+VirMidi was Card 1 and as the port used above was first one, I give
+Hatari the following midi device:
+  hatari --midi-out /dev/snd/midiC1D0
+
+(For the virtual midi keyboard, give same device with --midi-in option.)
+
+Note: In older (obsolete) Linux distros SDL_mixer may take exclusive
+access to the PCM (sound) device, but as the soft synthetizer is
+already connected to it, one may need to use --nosound option to get
+MIDI sound working. In recent distros this shouldn't anymore be
+a problem thanks to Pulseaudio.
+
+
+MIDI and networking
+-------------------
+
+If you direct the MIDI data to stdout, you can use just ssh to
+forward the MIDI output over network:
+  hatari --midi-in "" --midi-out /dev/stdout --log /dev/stderr |\
+    ssh user@remote.site "cat>/dev/snd/midiC1D0"
+
+(Note that logging is re-directed to stderr so that it doesn't
+mess the MIDI output to standard output and --midi-in is set
+empty in case you don't have MIDI input device locally.)
+
+
+MIDI-networking two Hatari emulators can be most easily done with socat.
+
+MIDI networking over normal TCP/IP network:
+  @remote.site:
+    socat -b1 PTY,raw,echo=0,link=/tmp/midi1 TCP4-LISTEN:33333 &
+    hatari --midi-in /tmp/midi1 --midi-out /tmp/midi1 &
+  @local.site:
+    socat -b1 PTY,raw,echo=0,link=/tmp/midi2 TCP4:remote.site:33333 &
+    hatari --midi-in /tmp/midi2 --midi-out /tmp/midi2 &
+
+Buffer size (-b) is set to one just in case (by default socat buffer
+size is 8K, but all the MIDI communication is done byte at the time).
+
+You may need to open a hole into your firewall for the given port
+(here 33333).  Usually there's a hole for the www-traffic in firewalls,
+but the port for that (80) is below 1000, so if you use "www" as
+the port, most likely you need to run "socat" as root.  To test this
+with a single machine, use "localhost" as the "remote.site".
+
+Local MIDI network:
+  socat -b1 PTY,raw,echo=0,link=/tmp/midi1 PTY,raw,echo=0,link=/tmp/midi2 &
+  hatari --midi-in /tmp/midi1 --midi-out /tmp/midi1 &
+  hatari --midi-in /tmp/midi2 --midi-out /tmp/midi2 &
+
+If you don't have "socat" installed, local-midi-ring.sh script shows how
+to join several (local) Hatari emulators into a MIDI ring using fifos.
+
+
+Linux & Atari MIDI related Software
+-----------------------------------
+
+In Debian, the tools mentioned above come from following packages:
+- alsa-utils (aconnect, aplaymidi)
+- alsa-tools (sbiload)
+- awesfx (sfxload)
+- pmidi
+- vkeybd
+- vmpk
+- aconnectgui
+- qsynth
+- fluidsynth
+- fluid-soundfont-* (soundfonts)
+- timidity
+- horgand
+- qjackctl
+- socat
+See http://packages.debian.org/ for more details on them.
+
+Below are upstream links to some of these tools.
+
+Vkeybd:
+  http://alsa.opensrc.org/Vkeybd
+
+Virtual MIDI Piano Keyboard (vmpk):
+  http://vmpk.sourceforge.net/
+
+Patch (ALSA connecting) utilities:
+  http://alsa.opensrc.org/AlsaMidiPatchbays    
+
+FluidSynth:
+  http://www.iiwu.org/fluidsynth/
+
+Horgand:
+  http://horgand.berlios.de/
+
+Soundfonts:
+  http://alsa.opensrc.org/SoundFontHandling
+
+List of some soft-synthetizers:
+  http://alsa.opensrc.org/SoftSynths
+
+Kaconnect:
+  http://alsamodular.sourceforge.net/
+
+QjackCtl:
+  http://qjackctl.sourceforge.net/
+
+socat:
+  http://www.dest-unreach.org/socat/
+
+
+As to Atari MIDI programs, here's an incomplete list
+of games supporting MIDI music:
+http://www.atari-forum.com/viewtopic.php?f=3&t=21473&start=25#p195632
+
+MidiMaze supports up to 16 players over MIDI network:
+  http://en.wikipedia.org/wiki/MIDI_Maze
+
+
+Additional documentation
+------------------------
+
+ALSA midi overview:
+  http://alsa.opensrc.org/AlsaMidiOverview
+
+How to set up soundcards with hardware MIDI synthesis capability (AWE & OPL3):
+  https://help.ubuntu.com/community/Midi/HardwareSynthesisSetup
+
+Virtual midi hardware setup:
+  http://www.tldp.org/HOWTO/MIDI-HOWTO-10.html
+
+Timidity Howto:
+  http://lau.linuxaudio.org/TiMidity-howto.html
+
+Midi with ALSA (old):
+  http://www.linuxfocus.org/English/September2002/article259.shtml
+
+Midi on Linux:
+  http://www.linuxjournal.com/article/7773
+
+MIDI, Musical Instrument Digital Interface protocol:
+  http://en.wikipedia.org/wiki/Midi
diff --git a/doc/release-notes.txt b/doc/release-notes.txt
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+
+                                    Hatari
+                                   --------
+                                Release Notes
+
+ Version 1.9.0 (2015-09-10):
+ ---------------------------
+
+Emulation:
+- STE Joypads:
+  - Fix: Joypad A Option button
+  - Fix: Joypad B extended buttons
+- ACSI / IDE:
+  - Fix: image file attribute check when using device files
+  - Fix: v1.8 ACSI regression with A1=0 case
+- GEMDOS HD:
+  - Fix: matching exactly 8 chars long file names containing '.'
+  - Better mapping of host errors to GEMDOS error codes
+  - Support for mapping file names with 8-bit characters
+    between host and Atari encodings (umlauted chars etc)
+  - Program header (TT-RAM) allocate flags support
+- CPU:
+  - update WinUAE CPU core version from 2.3 -> 2.8.1 -> 3.0 -> 3.1
+    - MMU emulation fixed
+    - instruction/data cache emulation
+    - better 68020/30 prefetch pipeline
+    - cycle accuracy, etc.
+  - in 68000 mode, remove some un-allowed  for CMPI, BTST and TST
+  - check for address error when new PC is set at the end of RTE, RTS and RTR
+  - fix "move.b an,", it's not allowed and should give illegal instruction
+  - improve stack frame for bus error and address error
+  - allow bus control only for 030
+    (i.e. prevent TOS forcing 16Mhz at boot with higher CPU levels)
+- Memory:
+  - TT-RAM / 32-bit addressing support both for TT & Falcon emulation
+    (when using EmuTOS, this requires version 0.9.4 or later)
+- FDC changes:
+  - for STX disks, fix type I commands with verify bit on tracks with no sector
+  - for ST/MSA, check read address and read track are not beyond max track
+- MFP:
+  - better emulation of GPIP, AER and DDR
+- MIDI:
+  - some RX/TX interrupt conditions were not correctly handled
+  - TDRE bit is status register more accurately handled
+- Video:
+  - fix value when reading video counter $FF8205/07/09 in high res
+- Blitter:
+  - when transfer ends, hog bit should be cleared in control register
+- DSP:
+  - better emulation of the HREQ signal
+
+Emulator:
+- Support for compiling with libSDL2 (experimental)
+  - SDL2 supports other than 2x scaling factors for ST/e emulation
+- Misc fixes:
+  - Fix: WinUAE CPU core (FPU) memory state restore
+  - Fix: chrash with VDI extended resolution emulation when
+         C: isn't GEMDOS HD emulated drive
+  - Fix: invalid defaults for real joysticks
+  - Fix: compilation when zlib is missing
+  - Fix: bugs from Debian bug tracker:
+	 https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=716536
+	 https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=688594
+- Additional TOS run-time patching:
+  - Support fast boot also with TOS v3 & v4
+  - Support 32-bit addressing also with TOS v4
+  - Replace TOS v4 instructions unsupported on 060
+  - HW specific phystop value in VDI mode
+- Options:
+  - Fast boot (warm boot / memory check bypass) is disabled by default
+  - 68060 CPU level and --ttram support with new WinUAE CPU core
+  - New --png-level option to decrease AVI compression CPU load
+  - Mouse warping on reset & resolution change can be controlled
+    with new --mousewarp option
+- Hard drive emulation:
+  - BUS ID for ACSI drive can be specified with --acsi
+  - GUI and command line options to enable 8-bit file name
+    Atari <-> host charset conversion for GEMDOS HD
+  - GUI and command line options to specify GEMDOS HD emulation drive
+    (default = C:), or to skip recognized drives used by partitions
+    on ACSI & IDE images
+    - Partition count parsed by Hatari might not match count used by
+      Atari HD driver due to driver differences in interpreting disk MBR
+  - Refuse to mount same HD image from multiple Hatari instances
+    (on platforms supporting BSD flock()), to avoid corrupting them
+- SDL GUI:
+  - joystick navigation in options GUI
+  - keyboard navigation & shortcuts in options GUI
+  - sort file selector items case-insensitively with folders first
+  - Partial support for showing Latin1 chars from UTF-8 file names
+  - AltGr+F<1-4> keyboard shortcuts to switch mode/type for emulated
+    joysticks and joypads
+  - User can reset or quit emulation from CPU halt dialog
+  - Fix: sync joystick changes with statusbar
+  - Fix: update default max window size for 2-line statusbar
+         NOTE: size would need to be updated in Hatari config files too!
+  - Fix: statusbar assert when FPU/MMU/TT-RAM are enabled in WinUAE CPU core
+  - When cpu enters 'halt' state in case of double bus/address errors,
+    show a dialog window to reset or call the debugger
+  - Fix bug in the filesector dialog that could create bug in other
+    dialogs used in Hatari
+- Debugger:
+  - Fix: crash when GEMDOS tracing is used without GEMDOS HD emulation
+  - Fix: update external disassembler's CPU mask when CPU type is changed
+         (it wasn't restricted to opcodes valid for given CPU type)
+  - Fix: breakpoint addition/removal within chained breakpoints
+  - Fix: Atari program detection on Windows for "symbols" command
+  - Profiler support for TT-RAM (uses *ton* of memory)
+  - Profiler support for (030) data cache and new "profile caches"
+    command to show i/d-cache hit/miss histograms
+  - Add trace support for IDE, MIDI and keymaps.  ACSI (SCSI) and IDE
+    trace output shows primary partition tables for ACSI & IDE images
+    (both Atari and DOS MBRs are supported)
+  - Add "os_base" trace option to trace Fopen/Fclose/Pexec/Pterm*.
+    That and "os_all" will now enable also xconout console redirection
+  - Output from --conout goes now to stdout instead of stderr
+  - Add "reset " command
+  - Add "save" subcommand to "history" command
+  - Add "basepage" address variable
+
+Other changes:
+- Add script to convert long host file names to Atari file names,
+  use that in atari-hd-image script
+- Add hatari-prg-args script for providing arguments to autostarted programs
+- Fix Atari program detection on Windows in "gst2ascii" tool
+- Hatari & disk image icons in SVG & PNG formats (multiple sizes)
+- Remaining Hatari OSX UI changes for Hatari v1.8.0 (localization)
+- Add video-recording.txt doc on video recording/uploading best practices
+
+Fixed demos:
+- Graphix Sound 2 in Relapse by Cybernetics (blitter+cpu, bus arbitration)
+- RGBeast by Aggression (video, writing to video counter during active display)
+- My Socks Are Weapons by Legacy (video, reading video counter in high res)
+
+Fixed games:
+- Superior 65 - Blood Money (cpu, exception stack and bus error)
+  (note that this version is bugged and will crash with TOS 1.04 or 1.62)
+- Obitus (STX version) (fdc, seek+verify on a track with no sector)
+- The Teller (STX/CTR version) (cpu, exception stack and address error)
+- War Heli (cpu, exception stack for address error and prefetch)
+
+Fixed programs:
+- Realtime and M by Eric Ameres (midi + mfp, toggle bit 0 of AER)
+- Notator (midi, more precise TDRE bit in status register)
+
+Known regressions (see compatibility list):
+- Suretrip demo by Checkpoint
+- Golden Island game demo with WinUAE CPU core
+
+
+ Version 1.8.0 (2014-07-30):
+ ---------------------------
+
+Emulation:
+- ST video changes :
+  - Handle 0 byte line by switching freq in STE mode
+  - Use high res when ff8260 is set to 3
+  - Randomly return 0 or 1 when reading unused bits 3,7 and 11 of
+    color registers (except when running from ROM)
+  - Better detection of bottom border removal on a 60 Hz screen
+  - support for color change during only 4 cycles
+  - better bitmap/color alignment for STE med res overscan at 60 Hz
+  - Set default value of nSpec512Threshold to "1" instead of "16"
+  - Update the position of the next VBL when 50Hz and 60Hz lines are mixed
+  - When video address is set into IO region, keep the video pointer on 24 bits
+- Videl changes :
+  - correct masking of the true color palette registers
+- CPU changes :
+  - Fix a case when MFP's interrupt happens during the IACK sequence
+    for HBL/VBL
+  - Many prefetch changes required by some game's protection
+- Sound changes :
+  - Fix STE sound mixing using LMC when mixer=0 (DMA sound only)
+  - Fix some crossbar's sound errors for Falcon
+  - Fix Microwire's decoding of mask/data (based on official LMC1992's doc)
+- FDC changes :
+  - Add configurable RPM speed for each floppy drive, the possibility
+    to turn each drive ON/OFF and the choice between single or double
+    sided drive
+  - Correct timings, behaviour and status register for all commands
+    when a drive is OFF or empty.
+  - Rewrite the index pulse part and all the delays expressed as disk's
+    revolution
+  - Add support for the "Force Int on Index Pulse" command
+  - Rewrite the DMA functions for better accuracy
+  - Add support for IPF/CTR files by using the capsimage library
+  - Add open source support for Pasti STX files, including random/fuzzy bits
+    and variable length bits. Also allow to save writes to a .stx file
+    into an additional .wd1772 file (store 'write sector' and 'write track' data)
+  - Don't force drives A and B at $4c2, keep the values detected by TOS
+  - Many other timing / status register improvements
+- GEMDOS HD emulation:
+  - Fix: clip filenames given through GEMDOS calls to 8+3 length
+    using first '.'
+  - Fix: autostarting programs with GEMDOS-illegal host characters
+    in their names
+- ACSI hard disk changes:
+  - Support multiple ACSI devices
+  - Fixed/improved READ CAPACITY and INQUIRY commands
+  - Unsupported commands are now handled correctly
+  - Now using fseeko() instead of fseek() for supporting large images
+- Other changes:
+  - Don't enable MegaST's real time clock by default, it can cause some
+    crashes in STF/STE mode
+  - Improve ACIA's wait state with E clock
+  - Add support for IKBD commands 0x11 and 0x13 (resume/pause output)
+    and 0x17 (joystick monitoring)
+
+Emulator:
+- SDL GUI:
+  - Update clock speed in the status bar when changing bus speed
+    in Falcon mode
+  - In the floppy dialog, use a checkbox to enable/disable drives A and B
+    and another checkbox to choose single/double sided drive
+  - In the screen dialog, add checkbox for --desktop-st option
+  - Add a 2nd line in the status bar, with infos on FDC, joysticks, monitor
+  - Fix OSX performance issue caused by statusbar and overlay LED
+    doing their own SDL_UpdateRects() calls
+- New command line options:
+  - Options --drive-a and --drive-b to enable/disable drives A and B
+  - Options --drive-a-heads and --drive-b-heads to select single or
+    double sided drives A and B
+  - --slowdown option to increase (multiply) VBL wait times
+- New Native Features commands:
+  - NF_EXIT exits emulator with given exit code
+  - NF_DEBUGGER invokes Hatari debugger from native program
+  - NF_FASTFORWARD sets fast forward on/off
+- Tracing improvements:
+  - Add option for tracing NatFeats calls
+  - Fix: Xbios(255) modified the given argument string
+  - Allow BIOS, XBIOS, GEMDOS, VDI and AES tracing to be enabled without
+    enabling also X/BIOS interception, GEMDOS HD emulation or extended
+    VDI mode
+  - Show PC value for traced Bios/XBios/GemDOS calls
+- Debugger:
+  - Fix: release mouse in all cases where debugger can be invoked
+  - Fix: DSP disassembler didn't in all cases show illegal opcodes correctly
+  - Fix: "symbols" command crash when it was used during TOS bootup
+  - Fix: TOS and cartridge addresses weren't (with all TOS versions)
+    in address order which asserted in profile data post-processor
+  - Fix: "next" command didn't work correctly in "hex" number base
+  - Fix: depending on compiler/linker/assembler, DATA/BSS debug symbol
+    offsets can in programs be either relative to their own, or to TEXT
+    section start.  If former fails, try latter when loading symbols.
+  - New "ym" info subcommand to show YM register values
+  - "quit" command by-passes exit confirmation dialog and takes
+    an optional Hatari exit code value
+  - removed limits on breakpoints and their conditions
+  - when entering debugger, current program's DRI/GST format debug
+    symbols are automatically read from it, if such are available
+  - new --debug-except option to specify which exceptions invoke
+    the debugger, and WinUAE CPU core support for -D toggle option
+  - "next"/"dspnext" commands work like in other debuggers, they
+    skip subroutine/exception calls, for all other instructions
+    they works like "step" command (earlier they always moved to
+    next instruction in memory)
+  - "next" and "dspnext" commands support optional "instruction type"
+    argument, which can be used (for example) to continue emulation
+    until subroutine returns
+  - "history" command takes optional parameter specifying how many
+    instructions of history will be tracked
+  - CPU & DSP profile commands have now subcommand for profiling loops
+  - "CpuInstr" and "DspInstr" variables for count of instructions
+    executed since emulation was last continued from debugger
+  - In addition to "!" condition, also "<" and ">" conditions can store
+    the checked value (when both sides of conditions are identical).
+    With above change, this can be e.g. used to detect and profile
+    what are worst frames in games and why
+  - New "rename" command to rename files.  Useful for scripted
+    worst frame and spinloop profiling
+  - Address space in 'dm' command can be given like in DSP disassembly,
+    "dm x:$100", in addition to earlier "dm x $100" syntax
+  - Fix out of bounds memory access that could result in bad disassembly
+    output when using the external disassembler (only "dc.w" were printed)
+
+Tools:
+- Increased max partition size in atari-hd-image script to 512MB.
+- New hatari_spinloop.py script for post-processing loop profile data.
+  It can tell how many times loops were executed, how many times they
+  spinned at minimum and maximum, at which VBL those happened, and what
+  was the standard deviation of that.
+- gst2ascii supports now both section relative and TEXT section relative
+  DATA/BSS symbol offsets
+- hconsole.Main() takes now Hatari command line options as argument
+- AHCC/GCC/VBCC examples on using (all) Native Features APIs
+- Improved mingw cross-compilation support
+
+Fixed demos :
+- 4-pixel plasma screen by TOS Crew (video, color change during only 4 cycles)
+- HighResMode by Paradox (video, color changes in overscan med res at 60 Hz)
+- It's A Girl 2 by Paradox (video, bottom border removal on a 60 Hz screen)
+- Pacemaker by Paradox (microwire, YM sound was muted)
+- Panic by Paulo Simoes (video, was broken since Hatari 1.7)
+- Shforstv.exe by Paulo Simoes (video, did not work in STE mode)
+- Sommarhack 2011 Invitro by DHS (CPU/MFP, top border not removed)
+- Stax Compilation #65 (conflict with Mega ST's RTC)
+- The Union Demo (cpu, memory access, ikbd, protection)
+- The World Is My Oyster - Convention Report Part by Aura (video, res=3)
+- Tymewarp (cpu, bus error)
+- UMD 8730 by PHF (video, unused bits in STF color registers)
+- IKBD no jitter by Nyh (acia/video, use a VBL of 160240 cycles)
+
+Fixed games :
+- Batman The Movie (cpu, exception stack)
+- Chart Attack Compilation (cpu, prefetch)
+- Darkman (cpu, prefetch)
+- Dragon Flight (cpu, illegal instruction)
+- International 3D Tennis (cpu, prefetch)
+- Leavin' Teramis loader text (video address at $ffe100)
+- Lethal Xcess Beta (cpu, bus error, code running at $ff8800)
+- Lethal Xcess (mfp, top border not removed sometimes)
+- Maze (by Martin Dennett & John Parker)
+- Parasol Stars (cpu, prefetch)
+- Reeking Rubber (by Nature), Falcon game
+- Titan (cpu, prefetch)
+- To Be On Top (cpu, memory access, ikbd, protection)
+- Warp (ikbd, interrupt used for decoding sectors)
+- Xenon 2 (cpu, prefetch)
+
+
+ Version 1.7.0 (2013-06-24):
+ ---------------------------
+
+Emulation:
+- TT video emulation :
+  - Extend the ST palette registers from 9bit to 12bit for ST modes
+  - Duochrome mode instead of monochrome for ST High
+  - Implementation of SampleHold in TT Hypermono video mode
+- Sound changes :
+  - Better model of the YM2149 noise generation (no noticeable audible impact)
+  - Slightly better volume table (measured by Paulo Simoes on a real ST)
+- CPU changes :
+  - Added experimental MMU emulation for the 68030 mode
+  - Handle the IACK cycles during an exception for HBL/VBL
+- ACIA/IKBD changes :
+  - Full implementation of the MC6850 ACIA, giving much more robust
+    IKBD emulation
+  - Better timings for all IKBD commands (measured on a real STF)
+  - Clock is handled internally in IKBD, host date/time is used
+    only to initialize RTC at boot.  I.e. pausing emulation doesn't
+    cause time skips when unpausing
+  - Fix slow mouse when absolute mode is used with scale values
+- MFP changes :
+  - Fixed priority errors when simultaneous interrupts happened
+  - MFP's IRQ should be delayed by 4 cycles before reaching the CPU
+  - MFP's IRQ signal was not correctly updated in some cases
+  - Handle the IACK cycles between CPU and MFP during an exception
+- FDC changes :
+  - Better delays for all the GAPs inside a track
+  - Emulate the disk's rotation and its angular position to get
+    accurate delays when accessing a sector header
+  - Internal timer for FDC was wrong and sometimes slower than expected
+  - Correct delay for type I commands with "verify" bit=1
+- GEMDOS HD emulation changes :
+  - Support Fforce() for GEMDOS HD emulated files and close at Pterm*()
+    all internal handles to emulated files program had left open
+  - Fix: cut file and dir names to 8+3 chars like all TOS versions do
+  - Fix: GEMDOS HD emulation overwrote last 28 bytes of basepage space
+    for the started process command line (with the program header)
+  - Fix: Fwrite() content wasn't flushed to disk on each write, so later
+    Fopen() + Fread()s calls on such files (if they were not closed
+    in the meanwhile) could get data that was out of date.
+  - Fix: Dfree() return value
+
+Emulator:
+- Fix: problems with run-time CPU type changing
+- Fix: MIDI IRQs were not enabled if MIDI was enabled at run-time.
+  MIDI toggling will now imply reset
+- Much improved console redirection functionality and a separate --conout
+  option for it (--bios-intercept doesn't anymore imply console redirection)
+- Fixed a bug with the axes' mapping in the joystick's detection
+- Display handling:
+  - Fix: max resolution limit wasn't handled properly for ST mode.
+  - Don't change TOS-calculated font size for VDI mode.
+  - Setup NVRAM video mode based on VDI mode, when in VDI mode.
+    This makes VDI mode work with EmuTOS also under Falcon emulation
+    which is useful as EmuTOS doesn't support native VIDEL expanders
+  - Limit VDI screen memory usage to 300kB, this allows up to 2048x1200
+    monochrome and 1024x600/800x768 16-color VDI screens
+- GEMDOS HD emulation:
+  - Fix: to DTA host filename cutting to 8+3 chars when whole filename
+    was < 12 chars (caused EmuTOS crash)
+  - Give warning if GEMDOS dir/file path exceeds 8+3 characters
+    (as those won't work with real TOS)
+  - New --gemdos-case option to specify whether new dir/filenames
+    are forced to be created in upper (default) or lower case
+  - Giving empty string as GEMDOS HD dir disables GEMDOS HD emulation
+- SDL GUI:
+  - Fileselector has "CWD" button for changing to Hatari's work directory
+  - Fileselector remembers previous position which is nicer with
+    large directories
+  - Make the drive leds blink with a brighter green when the FDC is executing
+    a command
+- Profiler:
+  - Fix: profiler assert on invalid PC register values
+  - Fix: profiler usage in debugger files invoked by breakpoints
+  - Fix: profiler CPU & DSP cycles information is for previous instruction
+  - Fix: WinUAE CPU requires cycles counter usage for getting current
+    CPU instruction cycles
+  - Profiler provides timing information, based on used cycles
+  - Profiler provides CPU instruction cache misses information when using
+    cycle-exact WinUAE CPU core (which is Falcon emu default)
+  - Profiler top instruction count/cycles/misses lists show
+    the related instructions
+  - For DSP, profiler adds min/max cycle difference info to disassembly
+  - New "addresses" subcommand can be used to see addresses through which
+    code passed during profiling (e.g. while program seems frozen, this
+    gives much better overview of code that is being run, than cpu trace)
+  - New "callers" subcommand lists all addresses from which loaded
+    symbols' addresses were "called" from.  This way one can e.g. find
+    in which contexts interrupt handlers were called and it can be
+    used to construction program execution callgraph
+  - New "save" subcommand saves profile address and caller information
+    to given file, with extra information needed for post-processing
+  - New "stack" subcommand that can be used to get backtraces during
+    profiling with symbols, for ':noinit' backtraces
+- Debugger:
+  - New ':noinit' and ':quiet' breakpoint options.  Quiet option
+    removes most of breakpoint matching "noise" and ':noinit' breakpoints
+    can be used with "profile stack" command, to prevent profile data and
+    related callstack information from being reset on breakpoint match
+  - "blitter" and "dsp" subcommand added to "info" command, to show
+    blitter register values and DSP state (e.g. stack content)
+  - "prg" subcommand added to "symbols" command, for loading debug
+    symbols from DRI/GST symbol table in last started program
+  - "step" and "next" commands added for single stepping CPU and DSP code
+    -> 's' shortcut is now for "step", not "save"
+  - "--disasm" option for selecting between UAE core and external CPU
+    code dissassembler and setting output option flags for latter
+  - When -D option is used, also undefined/illegal DSP instructions and
+    DSP stack under/overflows invoke debugger, not just CPU issues
+  - Fix: when several breakpoints should have triggered
+         on the same address, only first was handled
+  - Fix: after breakpoint, 'c ' continues one instruction too little
+  - Fix: tracking breakpoint values were updated only when all conditions
+    matched, now they can be also used together with other conditions
+  - Fix: info command crash (triggered on NetBSD)
+  - Fix: disassember output bug on NetBSD (usigned char < -1 test)
+  - Fix: info osheader and basebase subcommands under MiNT
+  - Fix: debugger history duplicates removal
+  - Fix: expression expanding CPU "pc" for DSP shortcut commands
+  - Fix: expression expansion messing lines in command line history
+  - Remote API debugger commands can also use expression expansion
+  - Both single and double quotes can be used to mark expressions
+  - In addition to text section offset, data and bss section offsets
+    can be given when loading symbols (useful for Devpac symbols)
+  - Output what value was set by options if it's not otherwise shown by UI
+  - New 'cpu' and 'dsp' options to 'history' command for tracing just
+    one of these processors on Falcon
+  - Function arguments are shown in traces for all non-MiNT GEMDOS calls
+    and subset of arguments are now shown also for AES calls (values in
+    intin array and strings in addrin array)
+  - Add NVRAM read & write tracing
+  - Support for the basic Native Features and --natfeats option to control it:
+    http://wiki.aranym.org/natfeats/proposal
+
+Windows specific changes:
+- "-W" option added for opening a console window.  Like on all other platforms,
+  "-D" will now just toggle CPU exception handling
+- Fix: console stderr redirection (used invalid "wr" mode)
+- Fix Windows localtime() not supporting dates before 1970:
+  - TOS not being able to access files with such dates, or further files
+  - causing IKBD emulation crashes (wasn't problem with Cygwin,
+    just with Mingw builds)
+
+Tool updates:
+- New hatari-profiler.py script for post-processing output from
+  profiler's CPU and DSP profiling "save" commands:
+	profile save 
+	dspprofile save 
+  - With symbol address information it can provide function level
+    instruction, processor cycle & i-cache miss statistics
+  - With callers information it can create function call callgraphs
+    and create callgrind format files for Kcachegrind GUI
+- New gst2ascii tool to extract DRI/GST symbol table from Atari program,
+  for use with the profile data post-processor
+- Added scripts for converting symbol tables in Devpac 3 listings and DSP LOD
+  files to a format understood by Hatari debugger 'symbols' command,
+  and to clean 'nm' output of GCC & VBCC built a.out binaries for it
+
+Other changes:
+- HTML documentation indeces generated dynamically with JS
+- Debugger tests building fixed
+
+Fixed Games:
+  Atomix (MFP, flickering bottom of the screen during samples)
+  BBC 52 Menu (Video/CPU, top border not removed)
+  Bolo (MFP, couldn't start a game)
+  Captain Blood (IKBD, fixed problem when setting the clock)
+  Fokker and Downfall (ACIA/IKBD, had regressed in Hatari v1.6.x)
+  Fuzion CD 77/78/84 Menu (MFP, random crash with digidrums in STF mode)
+  James Pond (Fuzion CD 25) (FDC, game stuck during the intro)
+  Microprose Golf (FDC, crash during the intro)
+  Spidertronic (Zuul CD 84) (crashed before 50/60 Hz screen)
+  Super Hang On and Super Monaco GP (MFP, flickering rasters)
+  The Final Conflict (MFP, locked during the sampled intro music)
+  The Sentinel (IKBD, mouse much too slow)
+  Zuul 100/101 Menu (MFP, flickering top border)
+
+Fixed demos :
+  Anomaly Demo Main Menu by MJJ Prod (MFP, flickering top/bottom borders)
+  Audio Artistic Demo by Big Alec (MFP, bad sample speed at start)
+  Decade Demo - Reset (MFP, flickering bottom border)
+  High Fidelity Dreams by Aura (MFP, flickering left rasters)
+  ST-NICCC 2000 Demo by Oxygene (FDC, demo ran slower than expected)
+
+Fixed apps :
+  Monst v1.x
+  Spectrum 512 (IKBD, mouse too slow)
+  Cubase (when MIDI was enabled after Hatari startup)
+
+
+ Version 1.6.2 (2012-06-24):
+ ---------------------------
+
+Emulation:
+- ST video changes :
+  - Fixes a rare potential crash when running in color mode and switching
+    to monochrome mode for more than one VBL (eg : protection code used
+    in The European Demos and The Transbeauce II Demo)
+  - add more timings for the 224 bytes overscan detection on STE
+  - Correct write timing for BCHG/BCLR/BSET when removing borders
+  - Fix to top/bottom border removal in a rare case
+- IKBD/ACIA changes :
+  - Handle commands 0x12 and 0x14 sent during the IKBD reset
+    (enable both mouse and joystick reporting at the same time)
+  - Handle the TX IRQ in the ACIA (bits CR6+CR5=0x01)
+  - Implemented IKBD set-clock function
+- Sound changes :
+  - Improve YM2149 sound filtering to be closer to a real STF
+  - Increase output volume for STE DMA sound (compared to the YM2149's volume)
+- DSP changes :
+  - Fix to DSP stack overflow handling
+  - Fix DSP to be reset on emulation reset
+- Old UAE core specific changes :
+  - Changes in the prefetch code for some instructions
+  - Correct PC in stack when JMP generates an illegal address exception
+- WinUAE core specific changes :
+  - 68040 MMU emulation fixes
+  - Fix GEMDOS/VDI emulation (illegal opcode) handling
+  - Fix WinUAE core to work with ST emulation (boot TOS 1.x)
+  - Fix FPU to be enabled when switching to TT emulation
+  - Fixes to FPU register value conversion
+- Falcon changes :
+  - Support for Falcon/Videl screen borders
+  - Fixes to few Falcon IO registers
+  - Changed behavior of the Microwire registers in Falcon mode
+- Misc changes :
+  - IO registers can only be read in supervisor mode
+  - Ignore FDC commands when no drive is selected
+  - Fix TT SCSI register reads to return all bits zero instead of set
+  - Fix for GEMDOS HD emu to direct special CON:/AUX:/PRN: device files
+    to TOS instead of trying to handle them as normal files
+  - printer output is single, not double buffered
+
+Emulator:
+- RS232 input&output and printer output can be disabled from command
+  line by specifying an empty path
+- Fix loading of memory snapshot from SDL GUI not to leave host cursor
+  enabled
+- Video changes:
+  - Increase max allowed VDI resolution from 1280x960 to 1920x1200
+  - Revert preferred Videl resolution max zooming size setting from
+    host desktop resolution back to 832x576 it was in Hatari v1.4,
+    so that Falcon/TT emulation window sizes by default are closer
+    to ST/STE ones on larger resolution monitors
+  - Fix statusbar assert
+  - Add --sound-sync option to keep video synchronized with the audio
+    in case the OS audio's driver has some latency issues
+- WinUAE core specific changes:
+  - Default to Falcon with WinUAE core (old CPU core still defaults to ST)
+  - Support run-time changing of CPU level, FPU type and machine type
+    from the GUI (also) with WinUAE CPU core
+- Debugging improvements:
+  - Fix to debugger CPU cycle profiling modifying CPU state
+  - Profiling info is shown at end of disassembly lines
+  - Support for tracing all symbols loaded to the debugger,
+    this can be used to get function traces for both CPU and DSP
+  - Show args for all Bios and most XBios & Gemdos calls when tracing
+  - "info" command can output opcode tables for BIOS & XBIOS too
+  - More info to FDC, IKBD, Videl and Crossbar traces
+
+Other changes:
+- Hatari OSX UI updated for Hatari v1.6.1 changes
+- Hatari Python UI supports file paths with spaces in them and spaces in
+  Hatari options given through its control socket can be quoted with '\'.
+- Support for alpha-numeric characters in Hconsole "text" command
+- Fixes to Hatari UI and hconsole error handling and examples
+- Fixed hatari-local-midi-ring.sh & hatari-local-rs232.sh arg handling
+- zip2st removes intermediate directories from created floppy
+- Fixed hmsa to handle files with multiple "." characters in their names
+- TOS tester testing covers more GEMDOS functionality, works with
+  all Hatari supported TOS versions and HW configurations and it's
+  fully automated 
+
+Fixed Games :
+  Hammerfist (fire button),
+  Automation 168 - Operation Clean Streets (prefetch in the CPU emulation)
+  Impossible Mission II (some versions had the same prefetch issue in the CPU)
+  Hades Nebula (fire button)
+  Zombi (IKBD set-clock was missing)
+
+Fixed demos :
+  Built-in Obsolescence (DSP stack overflow)
+  Japtro and Rising Force by Holocaust (FDC, buggy loader)
+  Delirious Demos IV (video, STE detection)
+  Antiques by Dune/Sector One (224 bytes STE overscan)
+  The Wave Of the Future by ICE (STE flickering top border)
+  Electrocution I by Sphere on Stax Menu 66 (STE flickering bottom border)
+  Musical Wonders 1990 by Offbeat (video, bottom border not removed)
+
+
+ Version 1.6.1 (2012-01-13):
+ ---------------------------
+
+This version is mainly a bugfix for 1.6.0, where monochrome mode
+gave a black screen and was not usable.
+
+Emulation:
+- Fixes to bootup issues in monochrome mode
+- Better left border removal timings
+- DSP external memory access cycles taken into account
+
+Other changes:
+- Fix to allow build with Xcode 3.1.3/OS X 10.5.8 PPC
+- Several fixes & updates needed to Hatari UI & hconsole
+  for them to work correctly with Hatari v1.6.x
+- Test programs added for testing TOS booting with different
+  HW configurations and for finding out values needed in
+  Hatari keymaps
+
+Fixed Demos :
+  Vodka Demo - Kill The Beast 2 (left border removal)
+
+
+ Version 1.6.0 (2012-01-01):
+ ---------------------------
+
+The Hatari project has been moved from hatari.berlios.de to
+http://hatari.tuxfamily.org/. Please update all bookmarks!
+
+Emulation:
+- More accurate FDC emulation (correct status bits and commands' timings,
+  DMA transfer by blocks of 16 bytes, floppy change detection). This should
+  fix a lot of non working games
+- More accurate microwire clock emulation
+- SCSI class 1 (ICD) command support for drives > 1 GB
+- Improved color conversion table so that colors are a little bit brighter
+- Improve shifter (add another method to do 4 pixel hardware scrolling,
+    better emulation for 0 byte blank line)
+- Some fixes to the IKBD emulation
+- Better filters and model for sound emulation
+- Correct VBL timings in TT monochrome (double clicking works now)
+- More cycle accurate Falcon DSP <-> CPU emulation.  All the demos that
+  needed 32Mhz CPU with the old CPU core in Hatari v1.5, work now at
+  correct 16Mhz with the WinUAE CPU core
+- 030 MMU emulation with the WinUAE CPU core
+
+
+Emulator:
+- Switch to ST mode when using TOS <= 1.04
+- Replace "--slowfdc" with "--fastfdc" option and default to fast FDC being OFF
+- "--fast-boot" option to initialize "memvalid" system variables to
+  by-pass the memory test of TOS, so that the system boots faster
+- "--force-max" option to force Hatari use specified maximum resolution
+  to avoid window size changes messing up Hatari video recording
+- "--desktop-st" option to keep desktop resolution also for ST/STE modes
+  (unfortunately without scaling besides the low-res doubling)
+- GEMDOS HD emulation:
+  - Allow drives up to Z: (not Y:)
+  - Unique name for each partition
+  - Warn user when using too old TOS version
+  - Dfree() reports host disk total and free size if they're below
+    value understood by TOS and unlike earlier, it forwards Dfree()
+    requests  for other (IDE/ACSI image) partitions to TOS
+- Debugger improvements:
+  - "history" command to list instructions executed before entering
+    debugger
+  - each trace output line is flushed to avoid it being buffered
+- Fixed behavior of the Caps Lock key
+
+Other changes:
+- Fixes to Hatari UI Hatari window embedding
+- Latest Linux sfdisk is borked so atari-hd-image script creates
+  HD image partition table now itself (experimental)
+- Windows needs also HOMEDRIVE for full home path in case Hatari
+  isn't installed on C:, bug 18297
+- Minor fixes
+
+
+Fixed Demos :
+  Overscan Demos and Shforstv.exe by Paulo Simoes (black line at top),
+  ACF - Just Bugging (FDC), Delirious Demo IV (FDC, shifter),
+  Overdrive Demos - Snirkel Screen (IKBD), Oxygene - Stniccc2000 (FDC),
+  Cream - Madness (FDC)
+
+Fixed Games :
+  Superior 65 - Super Monaco GP, DBug 24 - Knightmare, Pompey Pirates 27 - X-Out,
+  Fuzion 32 - Pang, Fuzion 108 - The Simpson, Fuzion 40 - Super Grand Prix,
+  Fuzion 46 - Warlock, Fuzion 51 - Navy Seals, Fuzion 61 - Gods, Fuzion 78 -
+  Carmen Sandiego, Fuzion 82 - Flight Of The Intruder, Fuzion 83 - RBI Baseball 2,
+  Fuzion 102 - Exile, PP46 - Yolanda, Medway Boys 15 - Murders In Venice,
+  Medway Boys 83 - Yogi Bear, BBC 2 - Platoon, BBC 39 - The Deep, Superior 71 - The
+  Running Man, Adrenaline 24 - Demon Blue, Superior 93 - Alien Storm
+
+Fixed Misc Programs :
+  Procopy 1.50, Terminators Copy 1.68, maxYMizer (caps lock key)
+
+
+ Version 1.5.0 (2011-07-19):
+ ---------------------------
+
+Emulation:
+- Alternative CPU core based on WinUAE for more accurate future
+  HW interaction emulation (see readme.txt on how to enable it)
+- Use precise clocks values (as described in Atari's official schematics)
+  for better video/dma audio synchronisation (e.g. More Or Less Zero by DHS)
+- DSP:
+  - Some DSP-timing sensitive Falcon demos that by luck happened to work
+    with Hatari v1.4, don't work anymore in v1.5 with the default UAE CPU
+    core.  This is because while DSP cycle accuracy has been improved,
+    the default UAE CPU core isn't fully cycle accurate.  The experimental
+    WinUAE core is needed to run them
+  - Undocumented 2 bit shift special case for DSP SSI <-> crossbar exchanges
+    in hanshake mode with 32 Mhz clock (fixes DSP MP2 player used in many
+    demos & programs, but that requires also using WinUAE core)
+- Sound improvements:
+  - Major rewrite and accuracy improvements in STE DMA sound, including
+    emulation of the 8 bytes FIFO, giving results nearly identical to
+    a real STE (e.g. HexTracker by Paulo Simoes)
+  - Improved precision in sound emulation, with nearly no rounding errors
+    over successive VBL (correct sound latency on US TOS running at 60 Hz)
+  - By default mix 3 YM voices using a lookup table of values
+    measured on real STF to improve digisound (e.g. Flashback demo sound)
+  - Remove old ST Sound's code used for tone and noise step compute
+    (some low period values were not correctly emulated)
+- Video emulation on STF/STE:
+  - On STE, correctly shift display 8 pixels to the left when using
+    224 bytes overscan
+  - Add support for spec512 mode in med res (fixes 'Best Part Of The
+    Creation' in 'Punish Your Machine', 'HighRes Mode' demo by Paradox)
+  - Correctly shift the screen 4 pixels to the left when left border is removed
+    in med res overscan (Hatari 1.4 handled only low res, fixes 'No Cooper'
+    by 1984, 'Best Part Of The Creation' by Delta Force)
+  - Precisely emulate the number of frames per sec (eg 50.053 fps in PAL
+    instead of the usual 50 Hz)
+
+Emulator:
+- Atari program given as argument to Hatari will be automatically
+  started after TOS boots. GEMDOS hard disk directory can now be
+  give also as an argument, not just as a (-d) option
+- TOS4 or --machine falcon option use enables DSP emulation now
+  (follow them with --dsp none to disable DSP emulation)
+- Memory state saving and restoring fixes, especially for Falcon
+  - Crossbar state is included -> state file ABI break
+- AVI recording options can be set in the new [Video] config file section
+- AVI recording supports non integer frame rates.
+- Falcon/TT Videl/hostscreen improvements:
+  - New setting/option for using Desktop resolution & scaling
+    in fullscreen instead of changing the resolution. On by default
+  - User's desktop size is used as max limit for Videl zooming.
+    Requires SDL >= 1.2.10
+  - Videl resolution change is done immediately, not 3 VBLs late
+  - Fix issues in switching between same sized VDI & TT resolutions
+- SDL GUI improvements:
+  - DSP can be disabled from the GUI without needing to restart Hatari
+  - Disk access LED and desktop-resolution options
+  - AVI video length (mins:secs) is shown in titlebar during recording
+  - Option for cropping statusbar from videos & screenshots
+  - Fileselector scrollbar can be used with mouse
+  - YM mixing method selection
+- Debugging improvements:
+  - New disassembler with more Motorola like syntax
+  - CPU & DSP "disasm" and "memdump" commands accept register & symbol
+    names in addition to numeric addresses / address ranges
+  - Option to disable Falcon mic
+    ("--mic off" is needed for Mudflap debugging)
+  - "--run-vbls" can be set also at run-time
+  - "--bios-intercept" can be toggled from debugger (not just enabled)
+  - BIOS CON: output is converted to ASCII and redirected to host console
+    with the --bios-intercept option
+  - Support for tracing DSP, Videl and Crossbar
+  - Support for tracing AES calls.  VDI calls can now be traced
+    also without using an extended VDI resolution
+  - BIOS/XBIOS/GEMDOS/VDI/AES/Line-A/Line-F opcode breakpoint support
+  - TEXT, DATA and BSS variables for addresses of corresponding segments
+    in currently loaded program
+  - "aes", "vdi" and "gemdos" subcommands for "info".  Without arguments
+    they will output information about corresponding OS part state,
+    with (a non-zero) argument, opcode/call name table is shown.
+    "video" subcommand for showing video related information.
+    "cookiejar" subcommand for showing cookiejar contents.
+  - "file" subcommand to "lock" that executes debugger commands from
+    given file when debugger is entered (or ":lock" breakpoint is hit)
+  - ":lock" option to breakpoints that will show (without stopping the
+    emulation) the same output as what's shown on entering the debugger
+  - ":file" option to breakpoints that executes the commands from
+    given file when the breakpoint is hit. This can be used to chain
+    debugger actions
+  - multiple breakpoints options can be specified per breakpoint
+  - parenthesis in "evaluate" command are used to indicate memory
+    accesses (instead of operator precedence like earlier)
+  - DSP and CPU code profiling functionality.  Provides statistics about
+    profiled code (executed code address ranges, max and total counts
+    and cycles), lists addresses/instructions taking most cyles and if
+    symbols are loaded, what were the most used symbol addresses.
+  - Profiling information is also shown in disassembly output
+
+Other changes:
+- hmsa tool can create empty disk images in addition to converting
+  disks between ST & MSA formats
+- Minimal hatari-tos-register.sh Linux init script (example)
+  to register Hatari as binfmt_misc handler/runner for TOS programs
+- hatari-console.py renamed to hconsole.py, documented and made extensible
+  (hconsole is command line Python interface for Hatari remote API)
+- Support for plain Makefiles removed (except for internal tests),
+  only CMake is used for configuring and building Hatari
+- CMake doesn't require anymore working C++, C-compiler is enough
+
+
+ Version 1.4.0 (2010-06-12):
+ ---------------------------
+
+Emulation:
+- IDE improvements:
+  - Support for second drive (IDE slave)
+  - WIN_FORMAT command (allows HD Driver to format IDE drives)
+- GEMDOS HDD emulation:
+  - Minor fixes to Fseek(), Fopen(), Fdatime() (e.g. Pure debugger works)
+  - On TOS v4 Fread() size arg is unsigned, on earlier TOS its signed
+    (bad code can use -1L to read whole file instead getting fail on TOS4)
+  - Prevent DTA and read/write functions accessing invalid memory areas
+  - Programs can now change read-only files to be writable
+- Falcon sound emulation:
+  - Microphone (jack) emulation in Falcon mode (requires portaudio library)
+  - SSI direct sound entrance ("Audio Fun Machine" and winrec are working)
+  - DMA sound recording
+  - Crossbar handshake mode transfers
+- Max VDI rez increased to TT-hi size (1280x960)
+- 68020+FPU changed to 68EC030+FPU (no MMU 030) for Falcon and TT modes
+  (Some Falcon programs didn't work with 020)
+- Video emulation on STF/STE:
+  - correctly shift the screen 4 pixels to the left when left border is removed
+  - add support for STE's 224 bytes overscan line without stabilizer
+  - when reading $ff8205/07/09 on STE, take into account the value
+    of horizontal scrolling/prefetch and linewidth
+  - when writing to $ff8205/07/09 on STE, correctly handle the case
+    where the write is made while display in ON
+- LMC1992 emulation / STE sound filtering
+
+Emulator:
+- Host mouse is centered to Hatari window on Falcon resolution changes
+  (helps in synchronizing host and emulated mouse positions)
+- Toggling fullscreen doesn't unpause paused emulation
+- Falcon/TT resolution zooming is now controlled by separate options for
+  monitor aspect ratio correction and maximum zoomed Hatari window size.
+  This can reduce Hatari window resolution size changes significantly and
+  makes e.g. FUN's Alive demo viewable in fullscreen mode.  Limits for
+  window size are also checked to see whether ST/STE low rez should be
+  zoomed and how much of borders can be shown (when borders enabled)
+- Split the Screen dialog into two separate dialogs, one for Atari
+  monitor emulation setup and one for Hatari window setup
+- GEMDOS drive emulation:
+  - support long host directory names and much improved long filename support
+  - convert host filename chars invalid in TOS to valid ones ('@')
+  - use TOS filename matching instead of glob() (can match names with [])
+- Options for preventing floppy image (--protect-floppy) and GEMDOS
+  emulated drive directory (--protect-hd) modifications
+- AVI file recording:
+  - video can be stored as BMP or as PNG images
+  - audio is stored as 16 bits stereo PCM
+- Statusbar shows CPU type & speed
+- Can create blank 2.88MB (ED) and 1.44MB (HD) floppy images
+  from the GUI in addition to DD & SD images.  After creating
+  new floppy image, one can directly insert it to A: or B:.
+- Tracing for BIOS, XBIOS, GEMDOS and VDI traps gives in addition
+  to the opcode, also the name of the corresponding OS function
+- Major debugger improvements:
+  - TAB-completion for debugger commands, command arguments and
+    symbol names. Requires readline library
+  - "parse" command and --parse Hatari command line option to
+    execute debugger commands from a file
+  - "stateload" and "statesave" commands for memory snapshots
+  - "trace" command for tracing what the emulated code does
+  - "symbols" command for loading and listing CPU & DSP code & data
+    symbols/addresses.  Code symbols are shown on CPU & DSP disassembly
+    and code & data symbols can be used in breakpoints
+  - "evaluate" command for doing calculations. Register and symbol
+    names in expressions are replaced by their values. '$' will be
+    TAB-completed to last 'evaluate' command result
+  - "cd" command to change Hatari work directory
+  - "exec" command to execute shell commands (ENABLE_SYSTEM_DEBUG_CALL)
+  - "info" command for showing Atari HW and OS information
+  - "lock" command for setting what information is shown every time on
+    entering the debugger, e.g. disassembly or memdump from given address.
+    "regaddr" argument does that from address pointed by given register
+  - improved register name handling + fixed DSP reg name matching
+  - if both sides of conditional breakpoint condition are identical, replace
+    right side with current value of given expression (e.g. if it's "d0",
+    use current D0 value).  If the comparison is for inequality ("!"),
+    output the value & break only when the value changes from the previous
+    value (not original like with other comparisons).  Symbols support
+  - ":trace" option to trace/output breakpoint hits without breaking
+  - breakpoints count hits and can be optionally removed after first hit
+    (":once" option) or triggered only on every Nth hit (":" option)
+  - dsp/address command is a shortcut for conditional breakpoints and its
+    argument can be an expression (see "evaluate" above)
+  - Display DSP instructions cycle timings in disasm mode (in cycles)
+  - Configuration options for how many lines to disasm & memdump
+- Fix VBLs/s counting to work also when --run-vbls isn't used
+
+Other changes:
+- Considerably expanded debugging and hard disk sections in manual
+- CMake build support, this fixes OSX building and adds support
+  for building Hatari in different directory from the sources
+- Removed autotools usage/support, added CMake "configure" script
+- Hatari remote control programs updates (see their own release notes
+  for details)
+
+
+ Version 1.3.1 (2009-09-05):
+ ---------------------------
+
+This is only a bug fix release:
+- GEMDOS HD emulation works together with ACSI HD image again
+- Fix incorrect use of DESTDIR in python-ui installation
+- Fix memdump/disasm in python-ui
+
+
+ Version 1.3.0 (2009-08-16):
+ ---------------------------
+
+Emulation:
+- Hugely improved DSP emulation:
+  - Many more DSP using games/demos/apps work now
+  - Preliminary sound support (e.g. most DSP based .MOD-playback works)
+  - Better cycle counting / accuracy
+  - Many speed improvements
+- Major rewrite of the internal work/structures of video.c :
+  - Allow to mix 50/60 Hz lines of 508/512 cycles and to keep correct
+    video/cpu sync (fixes TCB in SNY, DI in MindBomb, TEX in Syntax Terror).
+    This also adds support for dynamic calculation of HBL/Timer B positions
+    when freq/res are changed (fixes SHFORSTV by Paulo Simoes)
+  - Improved Timer B accuracy when starting it in a rare case
+  - Handle end of line as well as start of line for Timer B
+    in event count mode (using MFP's AER) (fixes Seven Gates Of Jambala)
+  - Add another 'O byte' line method (fixes No Buddies Land)
+  - Some more color alignment with the shifter when using movem.w/movem.l
+    (for spectrum512 like images)
+- Improved Blitter timings / cycles counting
+- GEMDOS emulation can emulate appropriately named host subdirectories
+  as separate partitions
+- Bug fixes for GEMDOS HD emulation Fopen and Fseek calls
+
+Emulator:
+- DSP changes:
+  - DSP state saved to memory snapshots
+  - Threading support removed from DSP emulation (for better synchronization)
+- "keyDebug" configuration file setting was renamed to "keyPause"
+- Major debugger improvements:
+  - Invoked with AltGR+Pause. New "keyDebugger" configuration file setting can
+    be used to change this
+  - Show PC/HBL/VBL/cycles when entering debugger
+  - Support multiple number bases. By default values are expected in
+    decimals; $-prefix is needed for hexadecimal and %-prefix for binary
+    values.  Default number base can be changed
+  - Internal debugger can be used to debug also DSP code
+  - Support for (PC) address breakpoints and conditional breakpoints
+    (watchpoints), both on CPU and DSP. Watchpoints support multiple
+    conditions, register & memory values and some internal Hatari
+    variables like VBL, HBL, LineCycles, FrameCycles
+  - Support for stepping CPU and DSP code
+- Emulated programs can now change Hatari options like --fast-forward,
+  --trace etc. by giving a suitable Hatari command line string to
+  XBios call 255.  This is enabled when Hatari is started with
+  the --bios-intercept enabled
+- Support Videl horizontal fine scrolling for 16 bpp and 32 bpp host screens
+- Process successive motion events before returning from event handler
+  (to fix analog joystick jitter slowing Hatari input processing)
+- FPS measurement shown when emulation is paused & --run-vbls option
+- Mouse grab option (--grab)
+- Some fixes for building Hatari with MS-VC6 and for the Wii
+- Statusbar assert (bug #15512) fixed
+- Reworked the main dialog of the GUI and split the disk dialog into two
+  separate dialogs, one for floppy setup and one for hard disk setup
+
+Utilities:
+- New atari-hd-image.sh script for creating HD image files
+- External Python GUI and CLI interfaces for Hatari in main repo
+
+Documentation:
+- Debugging and performance sections added to manual
+
+
+ Version 1.2.0 (2009-01-24):
+ ---------------------------
+
+- The Hatari project has been moved from hatari.sourceforge.net to
+  http://hatari.berlios.de. Please update all bookmarks!
+- New zip2st.sh shell script for converting .ZIP files into .ST disk images
+- Fixed a bug that could write data to the wrong disk image (resulting
+  in data loss)
+
+Emulation:
+- MIDI input supported in addition to output; --midi option is now
+  replaced with separate --midi-in and --midi-out options
+- Support for STE hardware horizontal scrolling in medium res
+- Make the FDC Read Address command always return success, even if
+  we don't really return the correct bytes for now (fixes a few game loaders)
+- Improved shadow register when writing to the YM2149 (fixes X-Out music)
+- Cleaner blitter code with improved timings
+- Emulation of interrupts jitter for HBL and VBL + improved timing accuracy
+- Improve color alignment with the shifter (for spectrum512 like images)
+- Fix to the fire button detection reported in some games
+- Added IDE hard disk emulation
+
+Emulator:
+- Pause/unpause shortcut
+
+
+ Version 1.1.0 (2008-11-29):
+ ---------------------------
+
+Emulation:
+- Falcon DSP emulation good enough to improve some few games/demos, e.g.
+  Virtual City. (most still work better with emulation disabled, though)
+- New sound engine that fixes all problems with the old one
+- 16-bit stereo sound (instead of 8-bit mono)
+- Improved blitter emulation (blitter cycles emulation, blitter interrupt)
+- Improved STE support for some video registers (hscroll, linewidth, ...)
+- Improved printer emulation
+- Improved STE microwire emulation
+- Improved support for games & demos which are accessing IKBD directly
+  (including a fake 6301 emulation for the known IKBD programs)
+- ACSI emulation fix to get HDDriver working
+- Some other minor bugfixes to ST/STe emulation (FDC, MFP, PSG, RS-232)
+- Improved MFP emulation
+- Improved 68k emulation (move.b Ax,(Ay) and extb.l)
+- Fixed bugs in the GEMDOS HD emulation (Pexec() etc.)
+
+Emulator:
+- Statusbar and overlay led features
+- Screenshots work also in VDI/TT/Falcon mode and are saved as PNGs
+- Support for automatic frameskip and pausing emulation
+- Support for embedding Hatari window (on X11) and control socket
+- Improved memory snapshot function
+- Improved the "trace" debug function
+
+
+ Version 1.0.1 (2008-03-30):
+ ---------------------------
+
+- This is just a bug-fix release, without new features.
+- Fixed some compile problems on non-unix-like systems (like MingW).
+- Fixed crashes in Spec512 emulation code ("Dan Dare 3" and little endian ARM).
+- Blitter source address is not incremented anymore in operation mode 0 and 15.
+- STE small overscan video effect is now displayed on the left side instead
+  of the right side (fixes "Just Musix 2" menu for example).
+- Hatari now works on 256 color displays right again.
+- Fixed PSG mirror register emulation (fixes e.g. sample sound in "Ooh Crikey
+  Wot A Scorcher" demo).
+
+
+ Version 1.0.0 (2008-03-17):
+ ---------------------------
+
+- The user's configuration files are now located in the directory ~/.hatari/
+  instead of the $HOME directory itself.
+- Improved VDI resolution mode (resolution can now be change in small steps).
+- The 'Frame Skip 8' option can now be correctly selected, too.
+- Fixed some bugs/problems in the GEMDOS HD emulation (with Fopen & Fcreate).
+- Keyboard shortcuts for saving and restoring memory snapshots.
+- Hatari can now be compiled with CeGCC, too.
+- Fixed some problems with the FPU emulation. NeoN Grafix renders now right.
+- Writing to floppy disk images works now also with TOS 4.0x.
+- A lot of source code clean-up and beautification.
+- Monochrome mode now runs in 71 Hz, and 60 Hz color mode now also really runs
+  with 60 Hz refresh rate.
+- Fixed memory snapshot files (some important data has not been saved before).
+- It is now possible to automatically load/save memory snapshots at start/exit.
+- Fixed some bugs in the file selection dialog.
+- Some minor improvements in the GUI: Improved text edit fields, "Cancel"
+  buttons can now be activated by pressing the ESC key, and Hatari asks the
+  user before resetting and quitting the emulator.
+- The Hatari executable is now relocatable (so the RPM can be relocated, too).
+- It's now possible to enable special trace output with the "--trace" option.
+- The size of the borders can now be specified in the hatari.cfg file.
+- Fixed Spec512 screen plotting on big endian machines.
+- Native screen conversion functions for 32 bpp host display mode.
+- Reworked the command line options.
+- Added missing read for "clr" in 68000 CPU mode.
+- Cycle correct MULU/MULS/DIVU/DIVS in 68000 CPU mode.
+- Support for 68000 instructions pairing
+- Better emulation of exception stack frame (bus/address error), used in some
+  protections.
+- Don't change illegal 68000 opcodes $8, $a and $c if no cartridge is inserted.
+- Ensure ACIA has consistent values when reset.
+- More precise interrupt handling, allowing to mix CPU cycles and MFP cycles
+  with greater precision.
+- Various improvements in MFP emulation (stop/start timer without writing to
+  data register, reading data register, handle pending cycles when timer
+  "wraps" (i.e. data register reaches 0), ...). Supports programs using some
+  very "fast" timers (Overscan Demos, ULM Demos) and requiring nearly cycle
+  exact synchronisation with the 68000.
+- Mostly correct wait states when accessing sound registers (add wait state for
+  $ff8801/ff8803 when needed).
+- Correct values of cycle counters read & write accesses for the most common
+  cases used for fullscreen/hardscroll.
+- Correct values for Video_CalculateAddress, taking into account frequency and
+  left/right borders' state, needed for correct synchronisation between video
+  and cpu.
+- Improve top/bottom border removal, including 60 Hz bottom border, as well as
+  "short" 50 Hz screen (171 lines)
+- Support for all left/right border removal, including 0 byte lines.
+- Support for hardscroll on STF, including the most recent ones using 4/5 lines.
+- Support for 4 pixels horizontal hardscroll on STF (ST Connexion in Punish
+  Your Machine)
+- Small adjustements in cycle precise color handling (spec512.c)
+
+
+ Version 0.95 (2007-05-12):
+ --------------------------
+
+- This release brings you basic Atari TT and Falcon emulation!
+  Please note that both new emulation modes are still highly experiemental,
+  some few games and demos work, but most still have more or less big
+  problems.
+- Basic emulation of Falcon video shifter (Videl), NVRAM and DMA sound is in
+  place. The biggest drawback: There is no working Falcon DSP emulation yet.
+- Screen/Shifter emulation timings have slightly been changed. Some things
+  now work better, some others work worse...
+- Some patches for compiling on RiscOS and AmigaOS have been included.
+- Compiling Hatari for Windows now works better.
+- Added Hatari icon (hatari-icon.bmp).
+- Fixed "movec" bug in 68020 CPU mode.
+- Keyboard shortcuts for loading & saving memory snapshots (AltGr+k & AltGr+l).
+- The built-in debugger has been slightly improved to be more user-friendly.
+- Added "hmsa" tool - a little program for converting .MSA files to .ST and
+  vice versa.
+
+
+ Version 0.90 (2006-08-22):
+ --------------------------
+
+- Better Spectrum 512 support (60Hz support, improved I/O memory waitstates).
+- STE right border opening support (used in Obsession, Pacemaker).
+- Blitter Smudge mode support (used in Pacemaker demo).
+- Wheel-mouse simulates cursor up and down.
+- Work-around to FDC handling, --slow-fdc option is not anymore needed.
+- Bugfix to MFP, sound works now in more YMRockerz releases.
+- Bugfix to GEMDOS path handling (Hatari SIGSEGV).
+- Bugfix to emulated memory initialization (4MB was cleared earlier, now
+  exactly the amount set up for Hatari.  Saves memory on embedded systems
+  if less than 4MB is specified.)
+- Re-written command-line option handling.
+- (Again) lots of code const/static, type usage and indentation cleanup.
+- Preliminary support for TOS 3.0x and 030 TT software that runs in ST
+  resolutions and doesn't need PMMU.
+- Native GUI for Mac OSX.
+- ACSI emulation fixes to get HD formatting to work with AHDI 5. HD emulation
+  now works quite fine with AHDI 5 (but other HD drivers are currently not
+  supported).
+- Joystick shortcut changed to toggle cursor emulation between ports 0 and 1.
+- Keys for all Hatari shortcuts can now be configured from hatari.cfg.
+- Added command line option for setting ST keyboard mapping.
+- Joystick command line option requires now parameter for a port for which
+  the joystick cursor emu is enabled.
+- Fixed relative mouse event handling in zoomed low-rez.
+- Hatari shows now more of the bottom borden (screen size is now 384x276
+  instead of 384x267).
+- Fixed sync delay timings - sound should now be better (e.g. on Mac OS X).
+- Added basic support for compiling Hatari with MinGW.
+
+
+ Version 0.80 (2005-10-12):
+ --------------------------
+
+- Support for STE hardware emulation: STE palette, STE shifter (horizontal fine
+  scrolling, split screen effects), DMA sound and STE joypads.
+  See the manual for a list of working STE applications/games/demos.
+- Hatari can now emulate up to 14 MiB ST RAM instead of only 4 MiB.
+- Support for parallel port joysticks.
+- Improved GEMDOS HD emulation (added Fattrib() call).
+- Adding and removing a GEMDOS or ACSI hard disk should now work correctly.
+- Re-factoring of the screen conversion functions.
+- Improved manual: Now with screenshots of the options dialogs.
+
+
+ Version 0.70 (2005-06-05):
+ --------------------------
+
+- As always: Code cleanup and bug fixes.
+- No more crashes when a program tries to access illegal sector numbers.
+- Improved built-in ROM cartridge.
+- Rewrote the IO memory emulation code -> Better compatibility.
+- Support for TOS 1.06 and TOS 1.62
+- Emulated CPU can now also be run at 16 MHz or 32 MHz.
+- File selection dialog scrollable with mouse wheel or cursor keys, too.
+- Hatari now works on 64-bit host CPUs, too.
+- Floppy disk images can now be set writable/write-protected in the GUI.
+- Hatari can now also load a global configuration file (e.g. /etc/hatari.cfg).
+- Configurable logging functions.
+
+
+ Version 0.60 (2004-12-19):
+ --------------------------
+
+- Again some code cleanup and bug fixes.
+- Window/fullscreen mode is now correctly initialized from the configuration
+  file.
+- Added --window command line option to force a start in window mode.
+- Added alert boxes to show warnings, errors and information messages.
+- PC mouse pointer is now better in sync with the ST mouse pointer.
+- It's now possible to load an alternative cartridge image file.
+
+
+ Version 0.50 (2004-07-26):
+ --------------------------
+
+- A lot of internal code cleanup and bug fixes.
+- Added a dialog for creating new blank floppy disk images.
+- The source code has been optimized for better emulation speed.
+- Added RS232 emulation (still very experimental and not very well tested! It
+  seems not to work reliable yet. Help for debugging is very appreciated!).
+- Some bugs in the 68000 emulation have been fixed.
+- The emulator now checks for double bus errors and stops the emulation if
+  necessary (instead of crashing the emulator).
+- Timer-D is now patched correctly again.
+- The old font has been replaced by two new fonts so that the GUI now looks
+  better in high resolutions.
+- The fonts are now linked into the executable.
+- Added support for DIM floppy disk images.
+
+
+ Version 0.45 (2003-10-30):
+ --------------------------
+
+- This is just a minor release on the way to version 0.50. It is not very
+  well tested, so be warned!
+- New build system (with a "configure" shell script).
+- A disk image destroying bug in the MSA compression function has been fixed.
+- It is now possible to redirect the printer output into a file.
+- Experimental MIDI output support.
+- Added the possibility to save memory snap shots.
+- Pending HBL and VBL interrupts are now emulated correctly (I hope).
+- Some speed improvements.
+- GEMDOS HD emulation now also works with EmuTOS.
+
+
+ Version 0.40 (2003-07-11):
+ --------------------------
+
+- Support for ZIP and GZIP compressed disk images!
+- Configuration file support for loading and saving the emulator settings.
+- Hatari now works on machines with Sparc CPUs, too.
+- Fixed a problem that slowed down the emulator in monochrome mode when using
+  TOS 2.06.
+- Inverted monochrome mode is now supported, too (some games like Maniac
+  Mansion use this).
+- Added Mega-ST compatible real time clock (RTC) emulation.
+- The GEMDOS HD emulation has been improved (it now also works with lower-case
+  file names) and many bugs have been fixed there.
+- Improved keyboard mapping (added mapping via PC keyboard scancode and via
+  reloadable mapping files).
+- The screen rendering routines have been generalized (less differences between
+  windowed and fullscreen mode).
+- Hatari can now be cross-compiled, too. You can even compile it for MiNT now.
+  However, it does not run very well there yet.
+- Support for RAM TOS images.
+- Improved memory mapping (the different memory regions should now behave much
+  more like on a real ST).
+- Improved M68k exceptions (bus errors and exception cycle timings).
+- Fixed some bugs in the extended VDI resolution mode (now it is working with
+  EmuTOS, too).
+- Some games that poll the write-protection signal of the FDC to check for
+  disk changes should now be working, too.
+
+
+ Version 0.30 (2003-03-12):
+ --------------------------
+
+- Some parts of the code accessed the SR directly to read the IPL -
+  however the UAE CPU core only updates the SR when doing a MakeSR() first.
+  So this is done in the affected code parts now, too.
+- The IPL wasn't raised when a MFP interrupt occurred - fixed now.
+- Full screen resolution for ST-Low can now be selected from the screen setup
+  dialog.
+- The IKBD emulation does not longer duplicate joystick fire buttons when
+  a game tries to use both, joystick and mouse
+- Improved audio timer function - the code should now be a little bit faster.
+- Resynced Hatari's UAE CPU core with UAE 0.8.22 - this fixes some bugs in 68k
+  instructions like ABCD and SBCD.
+- Added patches for TOS 2.05 so that this TOS version should now work, too.
+- Rewrote TOS patching routine. It is much more flexible now.
+- Removed 0xa0ff opcode for VDI resolutions; using GEMDOS_OPCODE now instead.
+- Fixed MMU RAM size configuration bug.
+- Rewrote some more screen conversion functions in C.
+- When a bus or address error occurred, the PC was often not set to the
+  right exception handler routine. This has been fixed now.
+
+
+ Version 0.25 (2002-12-30):
+ --------------------------
+
+- Patches for big endian systems (Spectrum 512 pictures are now working there).
+- Hatari now also compiles and runs under Mac OS X.
+- Blitter emulation has been added.
+- There is now the possibility to save YM or WAV sounds.
+- Big VDI resolutions (e.g. 800x600) are now supported, too.
+
+
+ Version 0.20 (2002-02-18):
+ --------------------------
+
+- Added graphical user interface for configuration of the emulator settings.
+- Real joysticks can now also be used to simulate the ST joysticks.
+- Yet another bugfix for BeOS (lseek again...)
+- Support for hard disk images.
+
+
+ Version 0.11 (2001-10-10):
+ --------------------------
+
+- High level (GEMDOS) harddisk emulation.
+- ST-Med/ST-Low mixed mode now works.
+
+
+ Version 0.10 (2001-08-16):
+ --------------------------
+
+- Improved CPU cycles emulation.
+- Added Spec512 support.
+- Some keyboard shortcuts.
+- Added the possibility to switch between fullscreen and window mode.
+- ST Medium resolution conversion routine.
+- Built-in debugger.
+- Added possibility to grab screenshots.
+- Sound support (not working very well yet).
+
+
+ Version 0.05 (2001-06-01):
+ --------------------------
+
+- Joystick emulation via cursor keys.
+- ST-LOW resolution conversion routine is now working on big-endian machines.
+
+
+ Version 0.04 (2001-05-27):
+ --------------------------
+
+- Added Stefan Berndtsson's patch for big-endian machines.
+  Hatari now runs also with non-x86 Linux machines! Thanks Stefan!
+- Rewrote the ST-LOW resolution conversion routines in C ==> ST-LOW now works!
+- Added some of the WinSTon patches Paul Bates recently published
+  at the WinSTon BBS (Thanks to Ladislav Adamec for the hint).
+- Cleaned up the source tree a little bit.
+
+
+ Version 0.03 (2001-04-03):
+ --------------------------
+
+- Rewrote some more assembler functions. FDC emulation now works!
+- SDL Keyboard code finished and included a SDL-Key -> ST-Scancode table.
+- Added mouse support.
+
+
+ Version 0.02 (2001-03-28):
+ --------------------------
+
+- Added very simple SDL support.
+- Rewrote a lot of assembler functions in C (e.g. intercept.c).
+- Adapted the UAE CPU. Now Hatari is able to boot a TOS 1.0x ROM, the
+  Desktop shows up, but no mouse and keyboard interaction yet.
+
+
+ Version 0.01 (2001-03-21):
+ --------------------------
+- Made the WinSTon source code compilable with GNU-C.
+- Added the UAE CPU sources.
diff --git a/doc/toc.js b/doc/toc.js
new file mode 100644
index 0000000..d08baa2
--- /dev/null
+++ b/doc/toc.js
@@ -0,0 +1,220 @@
+/** toc.js
+
+    This is a simplified version of the scipt "generated_toc.js" written by:
+            Stuart Langridge, July 2007
+
+    The script is licensed under the terms of the MIT license.
+    See the following page for details:
+            http://www.kryogenix.org/code/browser/generated-toc/
+
+    Generate a table of contents, based on headings in the page.
+
+    To place the TOC on the page, add
+
+    

+
+    to the page where you want the TOC to appear. If this element
+    is not present, the TOC will not appear.
+
+*/
+
+generated_toc = {
+  generate: function() {
+    // Identify our TOC element, and what it applies to
+    generate_from = '2';
+    tocparent = document.getElementById('generated-toc');
+    if (!tocparent) {
+      // They didn't specify a TOC element; exit
+      return;
+    }
+
+    // set top_node to be the element in the document under which
+    // we'll be analysing headings
+    top_node = document.getElementsByTagName('body')[0];
+
+    // If there isn't a specified header level to generate from, work
+    // out what the first header level inside top_node is
+    // and make that the specified header level
+    if (generate_from == 0) {
+      first_header_found = generated_toc.findFirstHeader(top_node);
+      if (!first_header_found) {
+        // there were no headers at all inside top_node!
+        return;
+      } else {
+        generate_from = first_header_found.toLowerCase().substr(1);
+      }
+    }
+
+    // add all levels of heading we're paying attention to to the
+    // headings_to_treat dictionary, ready to be filled in later
+    headings_to_treat = {"h6":''};
+    for (var i=5; i>= parseInt(generate_from); i--) {
+      headings_to_treat["h" + i] = '';
+    }
+
+    // get headings. We can't say
+    // getElementsByTagName("h1" or "h2" or "h3"), etc, so get all
+    // elements and filter them ourselves
+    // need to use .all here because IE doesn't support gEBTN('*')
+    nodes = top_node.all ? top_node.all : top_node.getElementsByTagName('*');
+
+    // put all the headings we care about in headings
+    headings = [];
+    for (var i=0; i cur_head_lvl) {
+        // this heading is at a lower level than the last one;
+        // create additional nested lists to put it at the right level
+
+        // get the *last* LI in the current list, and add our new UL to it
+        var last_listitem_el = null;
+        for (var j=0; j]+>/g, '');
+  },
+
+  findFirstHeader: function(node) {
+    // a recursive function which returns the first header it finds inside
+    // node, or null if there are no functions inside node.
+    var nn = node.nodeName.toLowerCase();
+    if (nn.match(/^h[1-6]$/)) {
+      // this node is itself a header; return our name
+      return nn;
+    } else {
+      for (var i=0; i for counted
+	  ones, ? for conditional ones, * for others)
+	- Shortcut command for telling to run until given
+	  (temporary) conditional breakpoint is hit
+	- Running until code returns from ROM (exiting from super mode?)
+	- Single stepping that skips Traps, Line-A, Line-F. And one that
+	  skips also BSRs and JSRs.  Run until RTS/RTE command
+	- Saving full machine status (like registers) to history buffer
+	  each time debugger is entered (exception or breakpoint is hit)
+	  and viewing of that history
+	- SP & SSP as CPU register names (active & supervisor stack)
+	- Fill and copy memory command
+	- Search for an address which disassembly output matches
+	  given instruction substring
+	- User variables which values can be set & used in expressions
+
+- Improved screen handling:
+	- Direct 16-bit & 32-bit support for monochrome and VDI modes
+	  (currently they're converted through 8-bit surface)
+	- Line based screen change detection/checks:
+		- blit only changed lines
+		- simpler / faster (LED) overlay handling
+	- x3 and x4 zooming routines for ST-Low resolution
+	- Include some fancy zooming routines like 2xSaI or Super-Eagle
+	- Add support for hardware accelerated zooming with
+	  SDL YUV overlays or OpenGL
+
+- Check/clean RS232 code:
+	- polls at 2/20ms intervals and reads data byte at the time.
+	  SDL_Delay()s & fgetc() could be replaced (at least on unix)
+	  with select() and fread().  Or just remove the rs232 thread
+	  and use an interrupt for it...
+	- The commented out rs232 stuff could be removed from gemdos.c
+	  (RS emulation is done at HW, not Gemdos level).
+
+- Improve directory handling:
+	- Currently screenshots & anim go always to current dir,
+	  whereas memsave, sound recording, printer & midi & serial &
+	  output and log output go to file specified in config file.
+	  There should be support for setting also anim/screenshot
+	  directory / file name from config file (needs change also
+	  in screenSnapShot.c).
+	- By default the directory config values should be empty in
+	  which case the code will at run-time decide to use current
+	  directory, but not modify the path config setting.
+
+
+Bug reports
+-----------
+
+- Hextracker freezes at start with Falcon emulation because Videl
+  screen address counter doesn't advance (its read & write are no-ops).
+
+- Atari programs can crash Hatari in Falcon mode because sound DMA code isn't robust
+  against bad register values:
+  http://listengine.tuxfamily.org/lists.tuxfamily.org/hatari-devel/2012/02/msg00082.html
+
+- When playing Tautology 2 I noticed the mod player sound goes in and out of
+  sync. fading into crackle and back. (Using Hatari 1.4 with TOS 4.04 on Mac
+  OS X 10.6.5)
+  http://developer.berlios.de/bugs/?func=detailbug&bug_id=17781&group_id=10436
+
+- Problem: On real Falcon there is a minor feature in videl. You can simply
+  fade whole screen to black, if you just clear the Horizontal Border End
+  ($ffff8286) and start fading colors from 0 to 255 to $ffff9800 or vice versa.
+	test 
+	move.w #255-1,d7
+	moveq #0,d6
+	.loop 
+	clr.w $ffff8286.w
+	move.l d6,$ffff9800.w
+	addq.l #1,d6
+	dbf d7,.loop
+  Now it does this exactly opposite direction, it fades bgcolor from 0 to 255.
+  http://developer.berlios.de/bugs/?func=detailbug&bug_id=18002&group_id=10436
+
+- To compare my real Falcon with Hatari on my Windows 7 PC, I make some short
+  benchmarks with Kronos. The disk benchmark in Kronos runs in 1-2 minutes on
+  my real Falcon. The same disk benchmark in Kronos under Hatari 1.5 runs
+  longer than 20 minutes with GEMDOS emulation.  Only when I use the AltGr + X
+  option, before the benchmark runs, then the disk benchmark in kronos is
+  comparable fast as my 16MHz Falcon.
+  http://developer.berlios.de/bugs/?func=detailbug&bug_id=18298&group_id=10436
+
+  -> Hatari GEMDOS emulation needs to do a lot of extra kernel file & directory
+     accesses which with current code seem unavoidable.  They're a problem only
+     with test programs like Kronos, for those one should consider using
+     harddisk image files instead.
diff --git a/doc/video-recording.txt b/doc/video-recording.txt
new file mode 100644
index 0000000..6df56cb
--- /dev/null
+++ b/doc/video-recording.txt
@@ -0,0 +1,66 @@
+How to record Atari videos with Hatari
+======================================
+
+Getting best output from Hatari
+-------------------------------
+
+* Do NOT use external recorders (such as Quicktime X on OSX), as they
+  won't get perfect framerate and sound sync like Hatari itself does.
+
+* Disable (default) frame skip, either from the Hatari GUI, or with
+  following command line option:
+  	--frameskips 0
+
+* For STe you could set audio to 50066 Hz using ST table, either from
+  the Hatari GUI, or with following command line options:
+	--sound 50066 --ym-mixing table
+
+* If you have enough free disk space, ask Hatari to use uncompressed
+  AVI format for the recording with the following command line option:
+	--avi-vcodec bmp
+
+
+Hatari AVI compression notes
+----------------------------
+
+If Hatari is configured/built with PNG development installed headers
+(normal case with Linux distros and pre-built binaries), Hatari will
+use PNG compression to produce smaller AVI recordings.
+
+Additionally, by default Hatari will use the highest PNG compression
+level (same as with screenshots), but this is *really* CPU intensive.
+
+Because of the PNG compression CPU usage, it's better to use
+uncompressed BMP format.  If you don't have enough disk space for
+this, next best option is to ask Hatari to use lower compression
+level, e.g. with:
+	--png-level 4
+
+Valid compression levels are 0-9, with 9 being default/highest/slowest.
+
+
+Preparing videos for uploading
+------------------------------
+
+If the end goal is Youtube, it's recommended to run Hatari's AVI
+output through ffmpeg to do nearest neighbor upscale to 1080p. Then
+Youtube will keep the 50 FPS and you have non-fuzzy pixels in the
+recording.
+
+This ffmpeg line should do the trick for a 320x200 stream (5x scale):
+  ffmpeg -i hatari.avi -vf "scale=1600:1000, \
+    pad=1920:1080:160:40:black" -sws_flags neighbor \
+    -vcodec png -acodec copy youtube1080p.mov
+
+And for a 416x276 stream (so you get the overscan area as well, 4x scale):
+  ffmpeg -i hatari.avi -vf "crop=400:270:8:0, scale=1600:1080, \
+    pad=1920:1080:160:0:black" -sws_flags neighbor -vcodec png \
+    -acodec copy youtube1080p.mov
+
+Above adds padding to 1920*1080 size, that can be removed if you trust
+the re-encoder/player to scale properly (which has been known to
+fail). It also saves the stream as PNG so it's manageable to upload
+and store for future.
+
+(Upload information is based on atari-forum post by "evil":
+http://atari-forum.com/viewtopic.php?f=51&t=27595#p268185 )
diff --git a/etc/GP2X_Wiz/crossdefs.wiz b/etc/GP2X_Wiz/crossdefs.wiz
new file mode 100644
index 0000000..d20cc50
--- /dev/null
+++ b/etc/GP2X_Wiz/crossdefs.wiz
@@ -0,0 +1,27 @@
+#
+# CMake crossdefs for GP2X Wiz target for Hatari
+# (c) by 2011 by Matthias Arndt 
+#
+#
+# USE AT YOUR OWN RISK and tweak as required!
+#
+# 2011-04-05 v0.01
+#
+
+# this one is important
+SET(CMAKE_SYSTEM_NAME Linux)
+#this one not so much
+SET(CMAKE_SYSTEM_VERSION 1)
+
+# specify the cross compiler
+SET(CMAKE_C_COMPILER   /opt/arm-openwiz-linux-gnu/bin/arm-openwiz-linux-gnu-gcc)
+SET(CMAKE_CXX_COMPILER /opt/arm-openwiz-linux-gnu/bin/arm-openwiz-linux-gnu-g++)
+
+# where is the target environment 
+SET(CMAKE_FIND_ROOT_PATH  /opt/arm-openwiz-linux-gnu/arm-openwiz-linux-gnu/sys-root-newsdl)
+
+# search for programs in the build host directories
+SET(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
+# for libraries and headers in the target directories
+SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
+SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
diff --git a/etc/GP2X_Wiz/hatari-wrapper.gpe b/etc/GP2X_Wiz/hatari-wrapper.gpe
new file mode 100755
index 0000000..6c83061
--- /dev/null
+++ b/etc/GP2X_Wiz/hatari-wrapper.gpe
@@ -0,0 +1,8 @@
+#!/bin/sh
+#
+# experimental Hatari launcher for GP2X Wiz
+cd hatari
+./hatari.gpe -f --bpp 16 -c ./wiz.cfg | tee ./hatari-log.txt
+sync
+cd /usr/gp2x
+exec /usr/gp2x/gp2xmenu
diff --git a/etc/README b/etc/README
new file mode 100644
index 0000000..99a4920
--- /dev/null
+++ b/etc/README
@@ -0,0 +1,57 @@
+
+Hatari on constrained devices
+-----------------------------
+
+In this directory are Hatari configurations files for mobile etc
+devices on which the builtin Hatari defaults aren't appropriate.
+Just copy suitable config file to the device /etc/ directory as
+'hatari.cfg'.
+
+Below are some comments about the configuration files. Some comments
+about suitable compiler options for these platforms can be found from
+the Hatari v1.4 default Makefile (which is now replaced with CMake):
+http://hg.tuxfamily.org/mercurialroot/hatari/hatari/file/dabb65b541c9/Makefile-default.cnf
+
+Hatari v1.5 gets screen size automatically, so setting that shouldn't
+anymore be necessary, but shouldn't harm either.
+
+If these configuration settings don't provide sufficient performance,
+use of an earlier Hatari version such as v0.95 (or even earlier)
+should be considered. Their emulation wasn't as accurate as in latest
+Hatari versions and therefore they're somewhat faster.
+
+
+n810.cfg
+--------
+
+Configuration file for the Nokia 770/N800/N810 TI Omap2/ARMv6 based devices:
+- Shortcut keys adapted for the device keys:
+  - Menu, Increase, Decrease, Fullscreen, Joystick keyemu fire
+- Max Hatari screen size set to device screen size
+- Options that are more suitable for the device performance:
+  - Non-compatible, but faster CPU mode (works fine with most things)
+  - No Falcon DSP emulation
+  - High spec512 threshold
+  - Automatic frameskip
+- Sensible default paths even for things that don't yet exist (to minimize
+  typing when they're enabled as N770 & N800 don't have a keyboard and N810
+  keyboard is very small so typing is quite awkward)
+
+For more information on these devices, see e.g:
+	http://en.wikipedia.org/wiki/Nokia_N800
+
+
+win-ce.cfg
+----------
+
+Configuration file for Windows Mobile based devices:
+- Start in fullscreen mode
+- Smaller border values / screen size limited to 320x240 resolution
+- Options that are more suitable for the device performance:
+  - Non-compatible (but faster) CPU mode
+  - Frameskip enabled
+  - High spec512 threshold
+  - 11kHz sound
+
+For more information on Windows CE and device based on it, see:
+	http://en.wikipedia.org/wiki/Windowsce
diff --git a/etc/n810.cfg b/etc/n810.cfg
new file mode 100644
index 0000000..648a9e6
--- /dev/null
+++ b/etc/n810.cfg
@@ -0,0 +1,200 @@
+[Floppy]
+bAutoInsertDiskB = TRUE
+nWriteProtection = 2
+szDiskAFileName =
+szDiskBFileName =
+szDiskImageDirectory = /home/user/MyDocs/.games
+szDiskAZipPath =
+szDiskBZipPath =
+
+[HardDisk]
+bBootFromHardDisk = TRUE
+bUseHardDiskDirectory = TRUE
+bUseHardDiskImage = FALSE
+szHardDiskDirectory = /home/user/MyDocs
+szHardDiskImage = /home/user/MyDocs/acsi.img
+bUseIdeMasterHardDiskImage = FALSE
+bUseIdeSlaveHardDiskImage = FALSE
+szIdeMasterHardDiskImage = /home/user/MyDocs/ide-master.img
+szIdeSlaveHardDiskImage = /home/user/MyDocs/ide-slave.img
+
+[Joystick0]
+bEnableAutoFire = FALSE
+nJoyId = 1
+nJoystickMode = 0
+# 5-way rocker keys (arrows + enter)
+nKeyCodeDown = 274
+nKeyCodeFire = 13
+nKeyCodeLeft = 276
+nKeyCodeRight = 275
+nKeyCodeUp = 273
+
+[Joystick1]
+bEnableAutoFire = FALSE
+nJoyId = 0
+nJoystickMode = 0
+nKeyCodeDown = 274
+nKeyCodeFire = 13
+nKeyCodeLeft = 276
+nKeyCodeRight = 275
+nKeyCodeUp = 273
+
+[Joystick2]
+bEnableAutoFire = FALSE
+nJoyId = 2
+nJoystickMode = 0
+nKeyCodeDown = 274
+nKeyCodeFire = 13
+nKeyCodeLeft = 276
+nKeyCodeRight = 275
+nKeyCodeUp = 273
+
+[Joystick3]
+bEnableAutoFire = FALSE
+nJoyId = 3
+nJoystickMode = 0
+nKeyCodeDown = 274
+nKeyCodeFire = 13
+nKeyCodeLeft = 276
+nKeyCodeRight = 275
+nKeyCodeUp = 273
+
+[Joystick4]
+bEnableAutoFire = FALSE
+nJoyId = 4
+nJoystickMode = 0
+nKeyCodeDown = 274
+nKeyCodeFire = 13
+nKeyCodeLeft = 276
+nKeyCodeRight = 275
+nKeyCodeUp = 273
+
+[Joystick5]
+bEnableAutoFire = FALSE
+nJoyId = 5
+nJoystickMode = 0
+nKeyCodeDown = 274
+nKeyCodeFire = 13
+nKeyCodeLeft = 276
+nKeyCodeRight = 275
+nKeyCodeUp = 273
+
+[Memory]
+bAutoSave = FALSE
+nMemorySize = 1
+szAutoSaveFileName = /home/user/.hatari/auto.sav
+szMemoryCaptureFileName = /home/user/MyDocs/.games/hatari.sav
+
+[Midi]
+bEnableMidi = FALSE
+sMidiInFileName = /dev/snd/midiC1D0
+sMidiOutFileName = /dev/snd/midiC1D0
+
+[Printer]
+bEnablePrinting = FALSE
+bPrintToFile = TRUE
+szPrintToFileName = /home/user/MyDocs/.documents/hatari-printer.txt
+
+[ROM]
+szCartridgeImageFileName =
+szTosImageFileName = /usr/share/hatari/tos.img
+
+[RS232]
+bEnableRS232 = FALSE
+szOutFileName = /dev/modem
+szInFileName = /dev/modem
+
+[Screen]
+bAllowOverscan = FALSE
+bFullScreen = FALSE
+bUseExtVdiResolutions = FALSE
+nForceBpp = 0
+nSpec512Threshold = 128
+nFrameSkips = 5
+nMonitorType = 1
+nVdiColors = 0
+nVdiWidth = 800
+nVdiHeight = 480
+bShowStatusbar = TRUE
+bShowDriveLed = FALSE
+bAspectCorrect = TRUE
+nMaxWidth = 800
+nMaxHeight = 480
+
+[ShortcutsWithModifiers]
+# check /usr/include/SDL/SDL_keysyms.h for numeric key values
+keyOptions = 111
+keyFullScreen = 102
+keyMouseMode = 109
+keyColdReset = 99
+keyWarmReset = 114
+keyScreenShot = 103
+keyBossKey = 105
+keyCursorEmu = 106
+keyRecAnim = 97
+keyRecSound = 121
+keySound = 115
+keyQuit = 113
+keyFastForward = 120
+keyPause = 0
+keyDebugger = 19
+keyLoadMem = 108
+keySaveMem = 107
+keyInsertDiskA = 100
+
+[ShortcutsWithoutModifiers]
+# 285: F4 (menu)
+keyOptions = 285
+# 287: F6 (fullsceen)
+keyFullScreen = 287
+keyMouseMode = 0
+keyColdReset = 0
+keyWarmReset = 0
+keyScreenShot = 0
+keyBossKey = 0
+# 289: F8 (+ increase)
+keyCursorEmu = 289
+keyRecAnim = 0
+keyRecSound = 0
+# 288: F7 (- decrease)
+keySound = 288
+keyQuit = 0
+keyFastForward = 0
+keyPause = 19
+keyDebugger = 0
+keyLoadMem = 0
+keySaveMem = 0
+keyInsertDiskA = 0
+
+[Sound]
+bEnableSound = TRUE
+szYMCaptureFileName = /home/user/MyDocs/.sounds/hatari.wav
+nPlaybackFreq = 44100
+
+[System]
+bBlitter = FALSE
+bCompatibleCpu = FALSE
+bFastForward = FALSE
+bPatchTimerD = TRUE
+bRealTimeClock = TRUE
+nCpuFreq = 8
+nCpuLevel = 0
+nDSPType = 0
+nMachineType = 0
+
+[Log]
+sLogFileName = stderr
+sTraceFileName = stderr
+nTextLogLevel = 4
+nAlertDlgLogLevel = 1
+bConfirmQuit = TRUE
+
+[Debugger]
+nNumberBase = 10
+nDisasmLines = 8
+nMemdumpLines = 8
+
+[Keyboard]
+bDisableKeyRepeat = FALSE
+nKeymapType = 0
+szMappingFileName =
diff --git a/etc/win-ce.cfg b/etc/win-ce.cfg
new file mode 100644
index 0000000..3656a63
--- /dev/null
+++ b/etc/win-ce.cfg
@@ -0,0 +1,52 @@
+[Log]
+sLogFileName = hatarilog.txt
+nTextLogLevel = 3
+nAlertDlgLogLevel = 3
+bConfirmQuit = TRUE
+
+[Screen]
+bFullScreen = TRUE
+bAllowOverscan = FALSE
+nForceBpp = 0
+nSpec512Threshold = 128
+bUseExtVdiResolutions = FALSE
+nVdiWidth = 320
+nVdiHeight = 240
+nVdiColors = 2
+nMonitorType = 1
+nFrameSkips = 5
+bAspectCorrect = TRUE
+bShowStatusbar = FALSE
+bShowDriveLed = FALSE
+nMaxWidth = 320
+nMaxHeight = 240
+
+[Joystick1]
+nJoystickMode = 2
+bEnableAutoFire = FALSE
+nJoyId = 0
+nKeyCodeUp = 273
+nKeyCodeDown = 274
+nKeyCodeLeft = 276
+nKeyCodeRight = 275
+nKeyCodeFire = 305
+bEnableJumpOnFire2 = FALSE
+
+[Keyboard]
+bDisableKeyRepeat = TRUE
+nKeymapType = 0
+szMappingFileName =
+
+[ShortcutsWithoutModifiers]
+keyOptions = 282
+
+[Sound]
+bEnableSound = TRUE
+nPlaybackFreq = 22050
+
+[Memory]
+nMemorySize = 1
+bAutoSave = FALSE
+
+[System]
+bCompatibleCpu = FALSE
diff --git a/etc/wiz.cfg b/etc/wiz.cfg
new file mode 100755
index 0000000..bdea32a
--- /dev/null
+++ b/etc/wiz.cfg
@@ -0,0 +1,200 @@
+[Floppy]
+bAutoInsertDiskB = TRUE
+nWriteProtection = 2
+szDiskAFileName = /mnt/sd/game/hatari/FANTASIA.st
+szDiskBFileName =
+szDiskImageDirectory = /mnt/sd/game/hatari/
+szDiskAZipPath =
+szDiskBZipPath =
+
+[HardDisk]
+bBootFromHardDisk = FALSE
+bUseHardDiskDirectory = FALSE
+bUseHardDiskImage = FALSE
+szHardDiskDirectory = 
+szHardDiskImage = 
+bUseIdeMasterHardDiskImage = FALSE
+bUseIdeSlaveHardDiskImage = FALSE
+szIdeMasterHardDiskImage = 
+szIdeSlaveHardDiskImage = 
+
+[Joystick0]
+bEnableAutoFire = FALSE
+nJoyId = 0
+nJoystickMode = 0
+# 5-way rocker keys (arrows + enter)
+nKeyCodeDown = 274
+nKeyCodeFire = 13
+nKeyCodeLeft = 276
+nKeyCodeRight = 275
+nKeyCodeUp = 273
+
+[Joystick1]
+bEnableAutoFire = FALSE
+nJoyId = 1
+nJoystickMode = 0
+nKeyCodeDown = 274
+nKeyCodeFire = 13
+nKeyCodeLeft = 276
+nKeyCodeRight = 275
+nKeyCodeUp = 273
+
+[Joystick2]
+bEnableAutoFire = FALSE
+nJoyId = 2
+nJoystickMode = 0
+nKeyCodeDown = 274
+nKeyCodeFire = 13
+nKeyCodeLeft = 276
+nKeyCodeRight = 275
+nKeyCodeUp = 273
+
+[Joystick3]
+bEnableAutoFire = FALSE
+nJoyId = 3
+nJoystickMode = 0
+nKeyCodeDown = 274
+nKeyCodeFire = 13
+nKeyCodeLeft = 276
+nKeyCodeRight = 275
+nKeyCodeUp = 273
+
+[Joystick4]
+bEnableAutoFire = FALSE
+nJoyId = 4
+nJoystickMode = 0
+nKeyCodeDown = 274
+nKeyCodeFire = 13
+nKeyCodeLeft = 276
+nKeyCodeRight = 275
+nKeyCodeUp = 273
+
+[Joystick5]
+bEnableAutoFire = FALSE
+nJoyId = 5
+nJoystickMode = 0
+nKeyCodeDown = 274
+nKeyCodeFire = 13
+nKeyCodeLeft = 276
+nKeyCodeRight = 275
+nKeyCodeUp = 273
+
+[Memory]
+bAutoSave = FALSE
+nMemorySize = 1
+szAutoSaveFileName = /mnt/sd/game/hatari/auto.sav
+szMemoryCaptureFileName = /mnt/sd/game/hatari/hatari.sav
+
+[Midi]
+bEnableMidi = FALSE
+sMidiInFileName = /dev/snd/midiC1D0
+sMidiOutFileName = /dev/snd/midiC1D0
+
+[Printer]
+bEnablePrinting = FALSE
+bPrintToFile = TRUE
+szPrintToFileName = /mnt/sd/game/hatari/hatari-printer.txt
+
+[ROM]
+szCartridgeImageFileName =
+szTosImageFileName = /mnt/sd/game/hatari/tos.img
+
+[RS232]
+bEnableRS232 = FALSE
+szOutFileName = /dev/modem
+szInFileName = /dev/modem
+
+[Screen]
+bAllowOverscan = FALSE
+bFullScreen = TRUE
+bUseExtVdiResolutions = FALSE
+nForceBpp = 16
+nSpec512Threshold = 128
+nFrameSkips = 2
+nMonitorType = 1
+nVdiColors = 0
+nVdiWidth = 320
+nVdiHeight = 240
+bShowStatusbar = FALSE
+bShowDriveLed = FALSE
+bAspectCorrect = FALSE
+nMaxWidth = 320
+nMaxHeight = 240
+
+[ShortcutsWithModifiers]
+# check /usr/include/SDL/SDL_keysyms.h for numeric key values
+keyOptions = 111
+keyFullScreen = 102
+keyMouseMode = 109
+keyColdReset = 99
+keyWarmReset = 114
+keyScreenShot = 103
+keyBossKey = 105
+keyCursorEmu = 106
+keyRecAnim = 97
+keyRecSound = 121
+keySound = 115
+keyQuit = 113
+keyFastForward = 120
+keyPause = 0
+keyDebugger = 19
+keyLoadMem = 108
+keySaveMem = 107
+keyInsertDiskA = 100
+
+[ShortcutsWithoutModifiers]
+# 285: F4 (menu)
+keyOptions = 285
+# 287: F6 (fullsceen)
+keyFullScreen = 287
+keyMouseMode = 0
+keyColdReset = 0
+keyWarmReset = 0
+keyScreenShot = 0
+keyBossKey = 0
+# 289: F8 (+ increase)
+keyCursorEmu = 289
+keyRecAnim = 0
+keyRecSound = 0
+# 288: F7 (- decrease)
+keySound = 288
+keyQuit = 0
+keyFastForward = 0
+keyPause = 19
+keyDebugger = 0
+keyLoadMem = 0
+keySaveMem = 0
+keyInsertDiskA = 0
+
+[Sound]
+bEnableSound = TRUE
+szYMCaptureFileName = /mnt/sd/game/hatari/hatari.wav
+nPlaybackFreq = 22050
+
+[System]
+bBlitter = FALSE
+bCompatibleCpu = FALSE
+bFastForward = FALSE
+bPatchTimerD = TRUE
+bRealTimeClock = FALSE
+nCpuFreq = 8
+nCpuLevel = 0
+nDSPType = 0
+nMachineType = 0
+
+[Log]
+sLogFileName = stderr
+sTraceFileName = stderr
+nTextLogLevel = 4
+nAlertDlgLogLevel = 1
+bConfirmQuit = FALSE
+
+[Debugger]
+nNumberBase = 10
+nDisasmLines = 8
+nMemdumpLines = 8
+
+[Keyboard]
+bDisableKeyRepeat = FALSE
+nKeymapType = 0
+szMappingFileName =
diff --git a/gpl.txt b/gpl.txt
new file mode 100644
index 0000000..d511905
--- /dev/null
+++ b/gpl.txt
@@ -0,0 +1,339 @@
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it.  (Some other Free Software Foundation software is covered by
+the GNU Lesser General Public License instead.)  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
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+
+  , 1 April 1989
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+This General Public License does not permit incorporating your program into
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diff --git a/hatari.spec b/hatari.spec
new file mode 100644
index 0000000..02e6392
--- /dev/null
+++ b/hatari.spec
@@ -0,0 +1,108 @@
+#
+# RPM spec file for Hatari
+#
+# This file and all modifications and additions to the pristine
+# package are under the same license as the package itself.
+#
+
+BuildRequires: bash coreutils cpio cpp diffutils file filesystem findutils glibc glibc-devel grep groff gzip libgcc m4 make man mktemp patch readline sed tar unzip util-linux zlib zlib-devel SDL SDL-devel autoconf binutils gcc libtool rpm
+
+Name:         hatari
+URL:          http://hatari.tuxfamily.org/
+License:      GPL
+Group:        System/Emulators/Other
+Autoreqprov:  on
+Version:      1.9.0
+Release:      1
+Summary:      an Atari ST emulator suitable for playing games
+Source:       %{name}-%{version}.tar.gz
+#Patch:        %{name}-%{version}.dif
+BuildRoot:    %{_tmppath}/%{name}-%{version}-build
+Prefix:       /usr
+
+%description
+Hatari is an emulator for the Atari ST, STE, TT and Falcon computers.
+The Atari ST was a 16/32 bit computer system which was first released by Atari
+in 1985. Using the Motorola 68000 CPU, it was a very popular computer having
+quite a lot of CPU power at that time.
+Unlike many other Atari ST emulators which try to give you a good environment
+for running GEM applications, Hatari tries to emulate the hardware of a ST as
+close as possible so that it is able to run most of the old ST games and demos.
+
+%prep
+%setup
+#%patch
+
+%build
+# LDFLAGS="-static" LIBS=`sdl-config --static-libs` \
+CFLAGS="-O3 -fomit-frame-pointer" \
+ ./configure --prefix=/usr --sysconfdir=/etc
+make
+
+%install
+rm -rf $RPM_BUILD_ROOT
+make install DESTDIR=$RPM_BUILD_ROOT
+
+%clean
+rm -rf $RPM_BUILD_ROOT
+
+%files
+%defattr(-,root,root)
+/usr/bin/hatari
+/usr/share/hatari
+%doc %_mandir/man1/hatari.1*
+%dir %_docdir/%{name}
+%_docdir/%{name}/*.txt
+%_docdir/%{name}/*.html
+%dir %_docdir/%{name}/images
+%_docdir/%{name}/images/*.png
+
+%changelog -n hatari
+
+* Thu Sep 10 2015 - Nicolas Pomarede
+- Hatari version 1.9.0
+
+* Wed Jul 30 2014 - Nicolas Pomarede
+- Hatari version 1.8.0
+
+* Sun Jun 24 2013 - Nicolas Pomarede
+- Hatari version 1.7.0
+
+* Sun Jun 24 2012 - Nicolas Pomarede
+- Hatari version 1.6.2
+
+* Fri Jan 13 2012 - Nicolas Pomarede
+- Hatari version 1.6.1
+
+* Sun Jan 1st 2012 - Nicolas Pomarede
+- Hatari "Happy New Year 2012" version 1.6.0
+
+* Tue Jul 19 2011 - Nicolas Pomarede
+- Hatari version 1.5.0
+
+* Sat Jun 12 2010 - Nicolas Pomarede
+- Hatari version 1.4.0
+
+* Sat Sep 05 2009 - Thomas Huth
+- Hatari version 1.3.1
+
+* Sun Aug 16 2009 - Thomas Huth
+- Hatari version 1.3.0
+
+* Sat Jan 24 2009 - Thomas Huth
+- Hatari version 1.2.0
+
+* Sat Nov 29 2008 - Thomas Huth
+- Hatari version 1.1.0
+
+* Wed Jan 02 2008 - Thomas Huth
+- Adapted RPM to the latest source code level (aiming at version 1.0.0)
+
+* Sun May 06 2007 - Thomas Huth
+- Adapted spec file to be able to build Hatari with RedHat, too
+
+* Sun Aug 27 2006 - Thomas Huth
+- Upgraded to version 0.90
+
+* Tue Oct 18 2005 - Thomas Huth
+- initial package
diff --git a/python-ui/.cvsignore b/python-ui/.cvsignore
new file mode 100644
index 0000000..9f51738
--- /dev/null
+++ b/python-ui/.cvsignore
@@ -0,0 +1,7 @@
+config.pyc
+debugui.pyc
+dialogs.pyc
+hatari-console.pyc
+hatari.pyc
+hatariui.pyc
+uihelpers.pyc
diff --git a/python-ui/CMakeLists.txt b/python-ui/CMakeLists.txt
new file mode 100644
index 0000000..e770bf9
--- /dev/null
+++ b/python-ui/CMakeLists.txt
@@ -0,0 +1,28 @@
+# conftypes.py is created to source directory (instead of build directory)
+# so that Hatari UI can be tested directly from the source directory
+add_custom_command(OUTPUT ${CMAKE_CURRENT_SOURCE_DIR}/conftypes.py
+	COMMAND ${CMAKE_CURRENT_SOURCE_DIR}/gentypes.py < ${CMAKE_CURRENT_SOURCE_DIR}/../src/configuration.c > ${CMAKE_CURRENT_SOURCE_DIR}/conftypes.py
+	DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/../src/configuration.c ${CMAKE_CURRENT_SOURCE_DIR}/gentypes.py)
+add_custom_target(conftypes ALL DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/conftypes.py)
+
+INSTALL(PROGRAMS hatariui
+	DESTINATION ${BINDIR})
+
+INSTALL(PROGRAMS hatariui.py debugui.py
+	DESTINATION ${DATADIR}/hatariui/)
+
+INSTALL(FILES README TODO release-notes.txt hatari-icon.png hatari-logo.png
+	config.py dialogs.py hatari.py uihelpers.py
+	${CMAKE_CURRENT_SOURCE_DIR}/conftypes.py
+	DESTINATION ${DATADIR}/hatariui/)
+
+INSTALL(FILES hatariui.desktop
+	DESTINATION share/applications)
+
+# if(UNIX)
+	add_custom_target(hatariui_man ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/hatariui.1.gz)
+	add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/hatariui.1.gz
+		COMMAND gzip -c -9 ${CMAKE_CURRENT_SOURCE_DIR}/hatariui.1 > ${CMAKE_CURRENT_BINARY_DIR}/hatariui.1.gz
+		DEPENDS hatariui.1)
+	INSTALL(FILES ${CMAKE_CURRENT_BINARY_DIR}/hatariui.1.gz DESTINATION ${MANDIR})
+# endif(UNIX)
diff --git a/python-ui/FILES b/python-ui/FILES
new file mode 100644
index 0000000..d37f456
--- /dev/null
+++ b/python-ui/FILES
@@ -0,0 +1,20 @@
+Code:
+- config.py	- Hatari configuration INI file handling
+- debugui.py	- Debugger UI (works also as standalone)
+- dialogs.py	- Different dialogs shown by Hatari UI
+- hatari.py	- Communication with Hatari and config option handling
+- hatariui	- Wrapper script for hatariui.py with suitable default options
+- hatariui.py	- Hatari UI main: option handling, main window etc
+- Makefile	- Rules for installing
+- uihelpers.py	- Misc helpers for Hatari UI
+
+Data files:
+- hatari-icon.png	- Window icon
+- hatari.png		- About dialog image
+- hatariui.desktop	- Hatari UI .desktop file for application launchers
+
+Documentation:
+- release-notes.txt	- UI & code changes
+- FILES			- This file
+- README		- Hatari UI intro / description
+- TODO			- missing features etc
diff --git a/python-ui/README b/python-ui/README
new file mode 100644
index 0000000..5b363f4
--- /dev/null
+++ b/python-ui/README
@@ -0,0 +1,78 @@
+Hatari UI
+---------
+
+Hatari UI is an out-of-process user interface for the Hatari Atari
+ST/STe/TT/Falcon emulator and its built-in debugger which can
+(optionally) embed the Hatari emulator window.
+
+Having the UI in another process allows doing it with a higher level
+language while avoiding adding GUI toolkit dependencies to Hatari
+itself. The UI is done with PyGtk i.e. in Python language, using the
+Gtk widget set.
+
+The main points of this new UI over the Hatari internal one are its
+configurability, more usable file selector, internationalization
+support and providing a GUI for the (console based) debugger included
+with the Hatari emulator.
+
+Note: this is an additional UI, the built-in Hatari SDL UI isn't being
+replaced or going anywhere!
+
+
+Requirements
+------------
+
+My guess at the required versions for the dependencies are:
+- Python >= 2.6
+- PyGtk >= 2.12   (on Debian/Ubuntu PyGtk is in python-gtk2 package)
+
+Hatari UI is included with the Hatari sources:
+	http://hg.tuxfamily.org/mercurialroot/hatari/hatari/file/tip/python-ui
+
+Hatari UI has been tested on several Linux versions.  I would assume
+it to work also on other unix systems such as Apple OSX. It may work
+with the Hatari Windows version, as long as it is built with socket
+support.
+
+Embedding the Hatari emulator window is currently supported only for
+systems using an X window system (from libSDL sources it would seem
+that Windows would also support window embedding, but support for that
+would need to be added both to Hatari and Hatari UI because SDL's
+own embedding disables all keyboard events in SDL program).
+
+Here are instructions on installing the dependencies for non-Linux
+platforms (neither tested nor supported as I don't use/have them):
+	http://pygtk.org/downloads.html
+
+
+Running
+-------
+
+Being a Python program, Hatari UI doesn't need to be built.
+You can just run it from where you extracted it (or checked
+it out of TuxFamily HG repo) by calling its wrapper script:
+	/path/to/script/hatariui
+
+Or you can run just the debugger:
+	/path/to/script/debugui.py
+
+But you can also install it to system along with Hatari:
+	make install
+
+
+Notes
+-----
+
+Hatari UI runs a Hatari version found on $PATH.  If you want
+to use a version of Hatari that hasn't been installed, you
+need to modify the search path, for example like this:
+	PATH=../build/src:.:$PATH hatariui
+
+If UI is started without the embedding option, the actions
+(in menus and toolbars) have also shortcuts.  They cannot
+be used when Hatari window is embedded because then those
+shortcuts couldn't be used with Hatari.
+
+
+A www-page with more information about Hatari UI is here:
+	http://koti.mbnet.fi/tammat/hatari/hatari-ui.shtml
diff --git a/python-ui/TODO b/python-ui/TODO
new file mode 100644
index 0000000..4924ad8
--- /dev/null
+++ b/python-ui/TODO
@@ -0,0 +1,61 @@
+TODO
+====
+
+This lists potential TODO items that aren't listed in the Hatari/UI
+sources.
+
+* Separate "Atari monitor" and "Hatari window" settings dialogs
+  (move options from "Display" and monitor setting from "Machine"
+  dialogs to here and add VDI options to Atari Monitor dialog)
+
+* Features for Help menu:
+  - Create empty floppy images (+ convert directories to hard disks?)
+  - MSA<->ST converter
+  - ZIP->ST converter
+
+* Add more Hatari debugger features to the debug UI:
+  - DSP support
+  - History support
+  - Profiling support
+  - DSP symbols loading
+    (CPU symbols are loaded automatically from programs)
+  - Support for stepping the emulation (both step & next commands)
+  - multiple views to memory (refreshed whenever emulation is stopped)
+    - supporting also register relative views (register values
+      parsing should move to common functionality first)
+  - breakpoint support (issue: how to stop emulation on breakpoint
+    but still allow Hatari to process remote commands?)
+  - trace & debug log viewers?
+
+* Put all configuration stuff into single notebook dialog?
+
+* Translation support for the UI:
+  - use gettext
+  - build needs to build & install message catalogs
+  - some way for Hatari to forward dialog ID to the remote UI
+    with dialog string parameters (filenames etc) which then
+    need to be localized too & shown...
+
+* Hatari UI specific configuration which stores:
+  - list of last used configuration files which would be shown
+    either in their own menu or dialog
+  - list of last used memory snapshots (10?)
+  - disk image dir (uses Hatari config value as default)
+  - trace settings
+    - remove dialog specific load/save stuff
+  - screenshot name
+    - needs support also to Hatari src/screenSnapShot.c
+
+* Supporting other, less important Hatari configuration options:
+  - HD booting, toggling disk-b autoinsertion
+  - something for multiple GEMDOS partition directories
+  - separate A/B disk paths for images that are within ZIP archives
+  - joystick autofire toggling, defining the keys for joyemu
+  - keyboard repeat, key mapping type and file, mouse grabbing
+  - vdi planes and size, SDL bpp forcing, spec512 threshold, ST blitter
+  - cartridge image (where? it has many limitations)
+  - log file and levels, console output, bios intercept, run-VBLs
+(Many of these aren't supported by the internal Hatari UI either, or
+are missing corresponding command line options so they will require
+additional support on the Hatari control.c side too or they can
+be only enabled at boot, not disabled.)
diff --git a/python-ui/config.py b/python-ui/config.py
new file mode 100644
index 0000000..a1233ee
--- /dev/null
+++ b/python-ui/config.py
@@ -0,0 +1,270 @@
+#!/usr/bin/env python
+#
+# Class and helper functions for handling (Hatari) INI style
+# configuration files: loading, saving, setting/getting variables,
+# mapping them to sections, listing changes
+#
+# Copyright (C) 2008-2012 by Eero Tamminen
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+import os
+# mapping from Hatari config variable name to type id (Bool, Int, String)
+from conftypes import conftypes
+
+# ------------------------------------------------------
+# Helper functions for type safe Hatari configuration variable access.
+# Map booleans, integers and strings to Python types, and back to strings.
+
+def value_to_text(key, value):
+    "value_to_text(key, value) -> text, convert Python type to string"
+    assert(key in conftypes)
+    valtype = type(value)
+    if valtype == bool:
+        assert(conftypes[key] == "Bool")
+        if value:
+            text = "TRUE"
+        else:
+            text = "FALSE"
+    elif valtype == int:
+        assert(conftypes[key] == "Int")
+        text = str(value)
+    else:
+        assert(conftypes[key] == "String")
+        if value == None:
+            text = ""
+        else:
+            text = value
+    return text
+
+def text_to_value(text):
+    "text_to_value(text) -> value, convert INI file values to real types"
+    # bool?
+    upper = text.upper()
+    if upper == "FALSE":
+        value = False
+    elif upper == "TRUE":
+        value = True
+    else:
+        try:
+            # integer?
+            value = int(text)
+        except ValueError:
+            # string
+            value = text
+    return value
+
+
+# ------------------------------------------------------
+# Handle INI style configuration files as used by Hatari
+
+class ConfigStore:
+    def __init__(self, userconfdir, defaults = {}, miss_is_error = True):
+        "ConfigStore(userconfdir, fgfile[,defaults,miss_is_error])"
+        self.defaults = defaults
+        self.userpath = self._get_full_userpath(userconfdir)
+        self.miss_is_error = miss_is_error
+    
+    def _get_full_userpath(self, leafdir):
+        "get_userpath(leafdir) -> config file default save path from HOME, CWD or their subdir"
+        # user's hatari.cfg can be in home or current work dir,
+        # current dir is used only if $HOME fails
+        for path in (os.getenv("HOME"), os.getenv("HOMEPATH"), os.getcwd()):
+            if path and os.path.exists(path) and os.path.isdir(path):
+                if leafdir:
+                    hpath = "%s%c%s" % (path, os.path.sep, leafdir)
+                    if os.path.exists(hpath) and os.path.isdir(hpath):
+                        return hpath
+                return path
+        return None
+
+    def get_filepath(self, filename):
+        "get_filepath(filename) -> return correct full path to config file"
+        # user config has preference over system one
+        for path in (self.userpath, os.getenv("HATARI_SYSTEM_CONFDIR")):
+            if path:
+                file = "%s%c%s" % (path, os.path.sep, filename)
+                if os.path.isfile(file):
+                    return file
+        # writing needs path name although it's missing for reading
+        return "%s%c%s" % (self.userpath, os.path.sep, filename)
+    
+    def load(self, path):
+        "load(path) -> load given configuration file"
+        if os.path.isfile(path):
+            sections = self._read(path)
+            if sections:
+                self.sections = sections
+            else:
+                print("ERROR: configuration file loading failed!")
+                return
+        else:
+            print("WARNING: configuration file missing!")
+            if self.defaults:
+                print("-> using dummy 'defaults'.")
+            self.sections = self.defaults
+        self.path = path
+        self.cfgfile = os.path.basename(path)
+        self.original = self.get_checkpoint()
+        self.changed = False
+
+    def is_loaded(self):
+        "is_loaded() -> True if configuration loading succeeded"
+        if self.sections:
+            return True
+        return False
+
+    def get_path(self):
+        "get_path() -> configuration file path"
+        return self.path
+    
+    def _read(self, path):
+        "_read(path) -> (all keys, section2key mappings)"
+        print("Reading configuration file '%s'..." % path)
+        config = open(path, "r")
+        if not config:
+            return ({}, {})
+        name = "[_orphans_]"
+        seckeys = {}
+        sections = {}
+        for line in config.readlines():
+            line = line.strip()
+            if not line or line[0] == '#':
+                continue
+            if line[0] == '[':
+                if line in sections:
+                    print("WARNING: section '%s' twice in configuration" % line)
+                if seckeys:
+                    sections[name] = seckeys
+                    seckeys = {}
+                name = line
+                continue
+            if line.find('=') < 0:
+                print("WARNING: line without key=value pair:\n%s" % line)
+                continue
+            key, text = [string.strip() for string in line.split('=')]
+            seckeys[key] = text_to_value(text)
+        if seckeys:
+            sections[name] = seckeys
+        return sections
+
+    def get_checkpoint(self):
+        "get_checkpoint() -> checkpoint, get the state of variables at this point"
+        checkpoint = {}
+        for section in self.sections.keys():
+            checkpoint[section] = self.sections[section].copy()
+        return checkpoint
+    
+    def get_checkpoint_changes(self, checkpoint):
+        "get_checkpoint_changes() -> list of (key, value) pairs for later changes"
+        changed = []
+        if not self.changed:
+            return changed
+        for section in self.sections.keys():
+            if section not in checkpoint:
+                for key, value in self.sections[section].items():
+                    changed.append((key, value))
+                continue
+            for key, value in self.sections[section].items():                    
+                if (key not in checkpoint[section] or
+                value != checkpoint[section][key]):
+                    text = value_to_text(key, value)
+                    changed.append(("%s.%s" % (section, key), text))
+        return changed
+    
+    def revert_to_checkpoint(self, checkpoint):
+        "revert_to_checkpoint(checkpoint), revert to given checkpoint"
+        self.sections = checkpoint
+
+    def get(self, section, key):
+        return self.sections[section][key]
+
+    def set(self, section, key, value):
+        "set(section,key,value), set given key to given section"
+        if section not in self.sections:
+            if self.miss_is_error:
+                raise AttributeError("no section '%s'" % section)
+            self.sections[section] = {}
+        if key not in self.sections[section]:
+            if self.miss_is_error:
+                raise AttributeError("key '%s' not in section '%s'" % (key, section))
+            self.sections[section][key] = value
+            self.changed = True
+        elif self.sections[section][key] != value:
+            self.changed = True
+        self.sections[section][key] = value
+        
+    def is_changed(self):
+        "is_changed() -> True if current configuration is changed"
+        return self.changed
+
+    def get_changes(self):
+        "get_changes(), return (key, value) list for each changed config option"
+        return self.get_checkpoint_changes(self.original)
+    
+    def write(self, fileobj):
+        "write(fileobj), write current configuration to given file object"
+        sections = list(self.sections.keys())
+        sections.sort()
+        for name in sections:
+            fileobj.write("%s\n" % name)
+            keys = list(self.sections[name].keys())
+            keys.sort()
+            for key in keys:
+                value = value_to_text(key, self.sections[name][key])
+                fileobj.write("%s = %s\n" % (key, value))
+            fileobj.write("\n")
+
+    def save(self):
+        "save() -> path, if configuration changed, save it"
+        if not self.changed:
+            print("No configuration changes to save, skipping")
+            return None
+        fileobj = None
+        if self.path:
+            try:
+                fileobj = open(self.path, "w")
+            except:
+                pass
+        if not fileobj:
+            print("WARNING: non-existing/writable configuration file, creating a new one...")
+            if not os.path.exists(self.userpath):
+                os.makedirs(self.userpath)
+            self.path = "%s%c%s" % (self.userpath, os.path.sep, self.cfgfile)
+            fileobj = open(self.path, "w")
+        if not fileobj:
+            print("ERROR: opening '%s' for saving failed" % self.path)
+            return None
+        self.write(fileobj)
+        print("Saved configuration file:", self.path)
+        self.changed = False
+        return self.path
+    
+    def save_as(self, path):
+        "save_as(path) -> path, save configuration to given file and select it"
+        assert(path)
+        if not os.path.exists(os.path.dirname(path)):
+            os.makedirs(os.path.dirname(path))
+        self.path = path
+        self.changed = True
+        return self.save()
+
+    def save_tmp(self, path):
+        "save_tmp(path) -> path, save configuration to given file without selecting it"
+        if not os.path.exists(os.path.dirname(path)):
+            os.makedirs(os.path.dirname(path))
+        fileobj = open(path, "w")
+        if not fileobj:
+            print("ERROR: opening '%s' for saving failed" % path)
+            return None
+        self.write(fileobj)
+        print("Saved temporary configuration file:", path)
+        return path
diff --git a/python-ui/debugui.py b/python-ui/debugui.py
new file mode 100755
index 0000000..be1a6dd
--- /dev/null
+++ b/python-ui/debugui.py
@@ -0,0 +1,571 @@
+#!/usr/bin/env python
+#
+# A Debug UI for the Hatari, part of PyGtk Hatari UI
+#
+# Copyright (C) 2008-2011 by Eero Tamminen
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+import os
+# use correct version of pygtk/gtk
+import pygtk
+pygtk.require('2.0')
+import gtk
+import pango
+
+from config import ConfigStore
+from uihelpers import UInfo, create_button, create_toggle, \
+     create_table_dialog, table_add_entry_row, table_add_widget_row, \
+     get_save_filename, FselEntry
+from dialogs import TodoDialog, ErrorDialog, AskDialog, KillDialog
+
+
+def dialog_apply_cb(widget, dialog):
+    dialog.response(gtk.RESPONSE_APPLY)
+
+
+# -------------
+# Table dialogs
+
+class SaveDialog:
+    def __init__(self, parent):
+        table, self.dialog = create_table_dialog(parent, "Save from memory", 3, 2)
+        self.file = FselEntry(self.dialog)
+        table_add_widget_row(table, 0, "File name:", self.file.get_container())
+        self.address = table_add_entry_row(table, 1, "Save address:", 6)
+        self.address.connect("activate", dialog_apply_cb, self.dialog)
+        self.length = table_add_entry_row(table, 2, "Number of bytes:", 6)
+        self.length.connect("activate", dialog_apply_cb, self.dialog)
+    
+    def run(self, address):
+        "run(address) -> (filename,address,length), all as strings"
+        if address:
+            self.address.set_text("%06X" % address)
+        self.dialog.show_all()
+        filename = length = None
+        while 1:
+            response = self.dialog.run()
+            if response == gtk.RESPONSE_APPLY:
+                filename = self.file.get_filename()
+                address_txt = self.address.get_text()
+                length_txt = self.length.get_text()
+                if filename and address_txt and length_txt:
+                    try:
+                        address = int(address_txt, 16)
+                    except ValueError:
+                        ErrorDialog(self.dialog).run("address needs to be in hex")
+                        continue
+                    try:
+                        length = int(length_txt)
+                    except ValueError:
+                        ErrorDialog(self.dialog).run("length needs to be a number")
+                        continue
+                    if os.path.exists(filename):
+                        question = "File:\n%s\nexists, replace?" % filename
+                        if not AskDialog(self.dialog).run(question):
+                            continue
+                    break
+                else:
+                    ErrorDialog(self.dialog).run("please fill the field(s)")
+            else:
+                break
+        self.dialog.hide()
+        return (filename, address, length)
+
+
+class LoadDialog:
+    def __init__(self, parent):
+        chooser = gtk.FileChooserButton('Select a File')
+        chooser.set_local_only(True)  # Hatari cannot access URIs
+        chooser.set_width_chars(12)
+        table, self.dialog = create_table_dialog(parent, "Load to memory", 2, 2)
+        self.file = table_add_widget_row(table, 0, "File name:", chooser)
+        self.address = table_add_entry_row(table, 1, "Load address:", 6)
+        self.address.connect("activate", dialog_apply_cb, self.dialog)
+
+    def run(self, address):
+        "run(address) -> (filename,address), all as strings"
+        if address:
+            self.address.set_text("%06X" % address)
+        self.dialog.show_all()
+        filename = None
+        while 1:
+            response = self.dialog.run()
+            if response == gtk.RESPONSE_APPLY:
+                filename = self.file.get_filename()
+                address_txt = self.address.get_text()
+                if filename and address_txt:
+                    try:
+                        address = int(address_txt, 16)
+                    except ValueError:
+                        ErrorDialog(self.dialog).run("address needs to be in hex")
+                        continue
+                    break
+                else:
+                    ErrorDialog(self.dialog).run("please fill the field(s)")
+            else:
+                break
+        self.dialog.hide()
+        return (filename, address)
+
+
+class OptionsDialog:
+    def __init__(self, parent):
+        self.dialog = gtk.Dialog("Debugger UI options", parent,
+            gtk.DIALOG_MODAL | gtk.DIALOG_DESTROY_WITH_PARENT,
+            (gtk.STOCK_APPLY,  gtk.RESPONSE_APPLY,
+             gtk.STOCK_CLOSE, gtk.RESPONSE_CLOSE))
+
+        self.lines = gtk.Adjustment(0, 5, 50)
+        scale = gtk.HScale(self.lines)
+        scale.set_digits(0)
+        
+        self.follow_pc = gtk.CheckButton("On stop, set address to PC")
+
+        vbox = self.dialog.vbox
+        vbox.add(gtk.Label("Memdump/disasm lines:"))
+        vbox.add(scale)
+        vbox.add(self.follow_pc)
+        vbox.show_all()
+
+    def run(self, lines, follow_pc):
+        "run(lines,follow_pc) -> (lines,follow_pc)"
+        self.follow_pc.set_active(follow_pc)
+        self.lines.set_value(lines)
+        self.dialog.show_all()
+        response = self.dialog.run()
+        if response == gtk.RESPONSE_APPLY:
+            lines = int(self.lines.get_value())
+            follow_pc = self.follow_pc.get_active()
+        self.dialog.hide()
+        return (lines, follow_pc)
+
+
+# ----------------------------------------------------
+
+# constants for the other classes
+class Constants:
+    # dump modes
+    DISASM = 1
+    MEMDUMP = 2
+    REGISTERS = 3
+    # move IDs
+    MOVE_MIN = 1
+    MOVE_MED = 2
+    MOVE_MAX = 3
+
+
+# class for the memory address entry, view (label) and
+# the logic for memory dump modes and moving in memory
+class MemoryAddress:
+    # class variables
+    debug_output = None
+    hatari = None
+
+    def __init__(self, hatariobj):
+        # hatari
+        self.debug_output = hatariobj.open_debug_output()
+        self.hatari = hatariobj
+        # widgets
+        self.entry, self.memory = self.create_widgets()
+        # settings
+        self.dumpmode = Constants.REGISTERS
+        self.follow_pc = True
+        self.lines = 12
+        # addresses
+        self.first = None
+        self.second = None
+        self.last = None
+        
+    def clear(self):
+        if self.follow_pc:
+            # get first address from PC when next stopped
+            self.first = None
+        self.second = None
+        self.last  = None
+
+    def create_widgets(self):
+        entry = gtk.Entry(6)
+        entry.set_width_chars(6)
+        entry.connect("activate", self._entry_cb)
+        memory = gtk.Label()
+        mono = pango.FontDescription("monospace")
+        memory.modify_font(mono)
+        entry.modify_font(mono)
+        return (entry, memory)
+
+    def _entry_cb(self, widget):
+        try:
+            address = int(widget.get_text(), 16)
+        except ValueError:
+            ErrorDialog(widget.get_toplevel()).run("invalid address")
+            return
+        self.dump(address)
+
+    def reset_entry(self):
+        self.entry.set_text("%06X" % self.first)
+        
+    def get(self):
+        return self.first
+
+    def get_memory_label(self):
+        return self.memory
+    
+    def get_address_entry(self):
+        return self.entry
+
+    def get_follow_pc(self):
+        return self.follow_pc
+    
+    def set_follow_pc(self, follow_pc):
+        self.follow_pc = follow_pc
+
+    def get_lines(self):
+        return self.lines
+    
+    def set_lines(self, lines):
+        self.lines = lines
+    
+    def set_dumpmode(self, mode):
+        self.dumpmode = mode
+        self.dump()
+        
+    def dump(self, address = None, move_idx = 0):
+        if self.dumpmode == Constants.REGISTERS:
+            output = self._get_registers()
+            self.memory.set_label("".join(output))
+            return
+
+        if not address:
+            if not self.first:
+                self._get_registers()
+            address = self.first
+
+        if not address:
+            print("ERROR: address needed")
+            return
+        
+        if self.dumpmode == Constants.MEMDUMP:
+            output = self._get_memdump(address, move_idx)
+        elif self.dumpmode == Constants.DISASM:
+            output = self._get_disasm(address, move_idx)
+        else:
+            print("ERROR: unknown dumpmode:", self.dumpmode)
+            return
+        self.memory.set_label("".join(output))
+        if move_idx:
+            self.reset_entry()
+    
+    def _get_registers(self):
+        self.hatari.debug_command("r")
+        output = self.hatari.get_lines(self.debug_output)
+        if not self.first:
+            # 2nd last line has first PC in 1st column, last line next PC in 2nd column
+            self.second = int(output[-1][output[-1].find(":")+2:], 16)
+            # OldUAE CPU core has ':' in both
+            offset = output[-2].find(":")
+            if offset < 0:
+                # WinUAE CPU core only in one
+                offset = output[-2].find(" ")
+            if offset < 0:
+                print("ERROR: unable to parse register dump line:\n\t'%s'", output[-2])
+                return output
+            self.first = int(output[-2][:offset], 16)
+            self.reset_entry()
+        return output
+
+    def _get_memdump(self, address, move_idx):
+        linewidth = 16
+        screenful = self.lines*linewidth
+        # no move, left/right, up/down, page up/down (no overlap)
+        offsets = [0, 2, linewidth, screenful]
+        offset = offsets[abs(move_idx)]
+        if move_idx < 0:
+            address -= offset
+        else:
+            address += offset
+        self._set_clamped(address, address+screenful)
+        self.hatari.debug_command("m $%06x-$%06x" % (self.first, self.last))
+        # get & set debugger command results
+        output = self.hatari.get_lines(self.debug_output)
+        self.second = address + linewidth
+        return output
+        
+    def _get_disasm(self, address, move_idx):
+        # TODO: uses brute force i.e. ask for more lines that user has
+        # requested to be sure that the window is filled, assuming
+        # 6 bytes is largest possible instruction+args size
+        # (I don't remember anymore my m68k asm...)
+        screenful = 6*self.lines
+        # no move, left/right, up/down, page up/down
+        offsets = [0, 2, 4, screenful]
+        offset = offsets[abs(move_idx)]
+        # force one line of overlap in page up/down
+        if move_idx < 0:
+            address -= offset
+            if address < 0:
+                address = 0
+            if move_idx == -Constants.MOVE_MAX and self.second:
+                screenful = self.second - address
+        else:
+            if move_idx == Constants.MOVE_MED and self.second:
+                address = self.second
+            elif move_idx == Constants.MOVE_MAX and self.last:
+                address = self.last
+            else:
+                address += offset
+        self._set_clamped(address, address+screenful)
+        self.hatari.debug_command("d $%06x-$%06x" % (self.first, self.last))
+        # get & set debugger command results
+        output = self.hatari.get_lines(self.debug_output)
+        # cut output to desired length and check new addresses
+        if len(output) > self.lines:
+            if move_idx < 0:
+                output = output[-self.lines:]
+            else:
+                output = output[:self.lines]
+        # with disasm need to re-get the addresses from the output
+        self.first  = int(output[0][1:output[0].find(":")], 16)
+        self.second = int(output[1][1:output[1].find(":")], 16)
+        self.last   = int(output[-1][1:output[-1].find(":")], 16)
+        return output
+
+    def _set_clamped(self, first, last):
+        "set_clamped(first,last), clamp addresses to valid address range and set them"
+        assert(first < last)
+        if first < 0:
+            last = last-first
+            first = 0
+        if last > 0xffffff:
+            first = 0xffffff - (last-first)
+            last = 0xffffff
+        self.first = first
+        self.last = last
+
+
+# the Hatari debugger UI class and methods
+class HatariDebugUI:
+    
+    def __init__(self, hatariobj, do_destroy = False):
+        self.address = MemoryAddress(hatariobj)
+        self.hatari = hatariobj
+        # set when needed/created
+        self.dialog_load = None
+        self.dialog_save = None
+        self.dialog_options = None
+        # set when UI created
+        self.keys = None
+        self.stop_button = None
+        # set on option load
+        self.config = None
+        self.load_options()
+        # UI initialization/creation
+        self.window = self.create_ui("Hatari Debug UI", do_destroy)
+        
+    def create_ui(self, title, do_destroy):
+        # buttons at top
+        hbox1 = gtk.HBox()
+        self.create_top_buttons(hbox1)
+
+        # disasm/memory dump at the middle
+        align = gtk.Alignment()
+        # top, bottom, left, right padding
+        align.set_padding(8, 0, 8, 8)
+        align.add(self.address.get_memory_label())
+
+        # buttons at bottom
+        hbox2 = gtk.HBox()
+        self.create_bottom_buttons(hbox2)
+
+        # their container
+        vbox = gtk.VBox()
+        vbox.pack_start(hbox1, False)
+        vbox.pack_start(align, True, True)
+        vbox.pack_start(hbox2, False)
+        
+        # and the window for all of this
+        window = gtk.Window(gtk.WINDOW_TOPLEVEL)
+        window.set_events(gtk.gdk.KEY_RELEASE_MASK)
+        window.connect("key_release_event", self.key_event_cb)
+        if do_destroy:
+            window.connect("delete_event", self.quit)
+        else:
+            window.connect("delete_event", self.hide)
+        window.set_icon_from_file(UInfo.icon)
+        window.set_title(title)
+        window.add(vbox)
+        return window
+    
+    def create_top_buttons(self, box):
+        self.stop_button = create_toggle("Stop", self.stop_cb)
+        box.add(self.stop_button)
+
+        monitor = create_button("Monitor...", self.monitor_cb)
+        box.add(monitor)
+        
+        buttons = (
+            ("<<<", "Page_Up",  -Constants.MOVE_MAX),
+            ("<<",  "Up",       -Constants.MOVE_MED),
+            ("<",   "Left",     -Constants.MOVE_MIN),
+            (">",   "Right",     Constants.MOVE_MIN),
+            (">>",  "Down",      Constants.MOVE_MED),
+            (">>>", "Page_Down", Constants.MOVE_MAX)
+        )
+        self.keys = {}
+        for label, keyname, offset in buttons:
+            button = create_button(label, self.set_address_offset, offset)
+            keyval = gtk.gdk.keyval_from_name(keyname)
+            self.keys[keyval] =  offset
+            box.add(button)
+
+        # to middle of <<>> buttons
+        address_entry = self.address.get_address_entry()
+        box.pack_start(address_entry, False)
+        box.reorder_child(address_entry, 5)
+
+    def create_bottom_buttons(self, box):
+        radios = (
+            ("Registers", Constants.REGISTERS),
+            ("Memdump", Constants.MEMDUMP),
+            ("Disasm", Constants.DISASM)
+        )
+        group = None
+        for label, mode in radios:
+            button = gtk.RadioButton(group, label)
+            if not group:
+                group = button
+            button.connect("toggled", self.dumpmode_cb, mode)
+            button.unset_flags(gtk.CAN_FOCUS)
+            box.add(button)
+        group.set_active(True)
+
+        dialogs = (
+            ("Memload...", self.memload_cb),
+            ("Memsave...", self.memsave_cb),
+            ("Options...", self.options_cb)
+        )
+        for label, cb in dialogs:
+            button = create_button(label, cb)
+            box.add(button)
+
+    def stop_cb(self, widget):
+        if widget.get_active():
+            self.hatari.pause()
+            self.address.clear()
+            self.address.dump()
+        else:
+            self.hatari.unpause()
+
+    def dumpmode_cb(self, widget, mode):
+        if widget.get_active():
+            self.address.set_dumpmode(mode)
+
+    def key_event_cb(self, widget, event):
+        if event.keyval in self.keys:
+            self.address.dump(None, self.keys[event.keyval])
+
+    def set_address_offset(self, widget, move_idx):
+        self.address.dump(None, move_idx)
+    
+    def monitor_cb(self, widget):
+        TodoDialog(self.window).run("add register / memory address range monitor window.")
+
+    def memload_cb(self, widget):
+        if not self.dialog_load:
+            self.dialog_load = LoadDialog(self.window)
+        (filename, address) = self.dialog_load.run(self.address.get())
+        if filename and address:
+            self.hatari.debug_command("l %s $%06x" % (filename, address))
+
+    def memsave_cb(self, widget):
+        if not self.dialog_save:
+            self.dialog_save = SaveDialog(self.window)
+        (filename, address, length) = self.dialog_save.run(self.address.get())
+        if filename and address and length:
+            self.hatari.debug_command("s %s $%06x $%06x" % (filename, address, length))
+        
+    def options_cb(self, widget):
+        if not self.dialog_options:
+            self.dialog_options = OptionsDialog(self.window)
+        old_lines = self.config.get("[General]", "nLines")
+        old_follow_pc = self.config.get("[General]", "bFollowPC")
+        lines, follow_pc = self.dialog_options.run(old_lines, old_follow_pc)
+        if lines != old_lines:
+            self.config.set("[General]", "nLines", lines)
+            self.address.set_lines(lines)
+        if follow_pc != old_follow_pc:
+            self.config.set("[General]", "bFollowPC", follow_pc)
+            self.address.set_follow_pc(follow_pc)
+
+    def load_options(self):
+        # TODO: move config to MemoryAddress class?
+        # (depends on how monitoring of addresses should work)
+        lines = self.address.get_lines()
+        follow_pc = self.address.get_follow_pc()
+        miss_is_error = False # needed for adding windows
+        defaults = {
+            "[General]": {
+            	"nLines": lines,
+                "bFollowPC": follow_pc
+            }
+        }
+        userconfdir = ".hatari"
+        config = ConfigStore(userconfdir, defaults, miss_is_error)
+        configpath = config.get_filepath("debugui.cfg")
+        config.load(configpath) # set defaults
+        try:
+            self.address.set_lines(config.get("[General]", "nLines"))
+            self.address.set_follow_pc(config.get("[General]", "bFollowPC"))
+        except (KeyError, AttributeError):
+            ErrorDialog(None).run("Debug UI configuration mismatch!\nTry again after removing: '%s'." % configpath)
+        self.config = config
+    
+    def save_options(self):
+        self.config.save()
+    
+    def show(self):
+        self.stop_button.set_active(True)
+        self.window.show_all()
+        self.window.deiconify()
+
+    def hide(self, widget, arg):
+        self.window.hide()
+        self.stop_button.set_active(False)
+        self.save_options()
+        return True
+
+    def quit(self, widget, arg):
+        KillDialog(self.window).run(self.hatari)
+        gtk.main_quit()
+
+
+def main():
+    import sys
+    from hatari import Hatari
+    hatariobj = Hatari()
+    if len(sys.argv) > 1:
+        if sys.argv[1] in ("-h", "--help"):
+            print("usage: %s [hatari options]" % os.path.basename(sys.argv[0]))
+            return
+        args = sys.argv[1:]
+    else:
+        args = None
+    hatariobj.run(args)
+
+    info = UInfo()
+    debugui = HatariDebugUI(hatariobj, True)
+    debugui.window.show_all()
+    gtk.main()
+    debugui.save_options()
+
+    
+if __name__ == "__main__":
+    main()
diff --git a/python-ui/dialogs.py b/python-ui/dialogs.py
new file mode 100644
index 0000000..8eea35b
--- /dev/null
+++ b/python-ui/dialogs.py
@@ -0,0 +1,1024 @@
+#!/usr/bin/env python
+#
+# Classes for the Hatari UI dialogs
+#
+# Copyright (C) 2008-2015 by Eero Tamminen
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+import os
+# use correct version of pygtk/gtk
+import pygtk
+pygtk.require('2.0')
+import gtk
+import pango
+
+from uihelpers import UInfo, HatariTextInsert, create_table_dialog, \
+     table_add_entry_row, table_add_widget_row, table_add_separator, \
+     table_add_radio_rows, table_set_col_offset, create_button, FselEntry, \
+     FselAndEjectFactory
+
+
+# -----------------
+# Dialog base class
+
+class HatariUIDialog:
+    def __init__(self, parent):
+        "Dialog(parent) -> object"
+        self.parent = parent
+        self.dialog = None
+    
+    def run(self):
+        """run() -> response. Shows dialog and returns response,
+subclasses overriding run() require also an argument."""
+        response = self.dialog.run()
+        self.dialog.hide()
+        return response
+
+
+# ---------------------------
+# Note/Todo/Error/Ask dialogs
+
+class NoteDialog(HatariUIDialog):
+    button = gtk.BUTTONS_OK
+    icontype = gtk.MESSAGE_INFO
+    textpattern = "\n%s"
+    def run(self, text):
+        "run(text), show message dialog with given text"
+        dialog = gtk.MessageDialog(self.parent,
+        gtk.DIALOG_MODAL | gtk.DIALOG_DESTROY_WITH_PARENT,
+        self.icontype, self.button, self.textpattern % text)
+        dialog.run()
+        dialog.destroy()
+
+class TodoDialog(NoteDialog):
+    textpattern = "\nTODO: %s"
+
+class ErrorDialog(NoteDialog):
+    button = gtk.BUTTONS_CLOSE
+    icontype = gtk.MESSAGE_ERROR
+    textpattern = "\nERROR: %s"
+
+
+class AskDialog(HatariUIDialog):
+    def run(self, text):
+        "run(text) -> bool, show question dialog and return True if user OKed it"
+        dialog = gtk.MessageDialog(self.parent,
+        gtk.DIALOG_MODAL | gtk.DIALOG_DESTROY_WITH_PARENT,
+        gtk.MESSAGE_QUESTION, gtk.BUTTONS_YES_NO, text)
+        response = dialog.run()
+        dialog.destroy()
+        return (response == gtk.RESPONSE_YES)
+
+
+# ---------------------------
+# About dialog
+
+class AboutDialog(HatariUIDialog):
+    def __init__(self, parent):
+        dialog = gtk.AboutDialog()
+        dialog.set_transient_for(parent)
+        dialog.set_name(UInfo.name)
+        dialog.set_version(UInfo.version)
+        dialog.set_website("http://hatari.tuxfamily.org/")
+        dialog.set_website_label("Hatari emulator www-site")
+        dialog.set_authors(["Eero Tamminen"])
+        dialog.set_artists(["The logo is from Hatari"])
+        dialog.set_logo(gtk.gdk.pixbuf_new_from_file(UInfo.logo))
+        dialog.set_translator_credits("translator-credits")
+        dialog.set_copyright(UInfo.copyright)
+        dialog.set_license("""
+This software is licenced under GPL v2 or later.
+
+You can see the whole license at:
+    http://www.gnu.org/licenses/info/GPLv2.html""")
+        self.dialog = dialog
+
+
+# ---------------------------
+# Input dialog
+
+class InputDialog(HatariUIDialog):
+    def __init__(self, parent):
+        dialog = gtk.Dialog("Key/mouse input", parent,
+            gtk.DIALOG_MODAL | gtk.DIALOG_DESTROY_WITH_PARENT,
+            ("Close", gtk.RESPONSE_CLOSE))
+        
+        entry = gtk.Entry()
+        entry.connect("activate", self._entry_cb)
+        insert = create_button("Insert", self._entry_cb)
+        insert.set_tooltip_text("Insert given text to Hatari window")
+        enter = create_button("Enter key", self._enter_cb)
+        enter.set_tooltip_text("Simulate Enter key press")
+
+        hbox1 = gtk.HBox()
+        hbox1.add(gtk.Label("Text:"))
+        hbox1.add(entry)
+        hbox1.add(insert)
+        hbox1.add(enter)
+        dialog.vbox.add(hbox1)
+
+        rclick = gtk.Button("Right click")
+        rclick.connect("pressed", self._rightpress_cb)
+        rclick.connect("released", self._rightrelease_cb)
+        rclick.set_tooltip_text("Simulate Atari right button press & release")
+        dclick = create_button("Double click", self._doubleclick_cb)
+        dclick.set_tooltip_text("Simulate Atari left button double-click")
+
+        hbox2 = gtk.HBox()
+        hbox2.add(dclick)
+        hbox2.add(rclick)
+        dialog.vbox.add(hbox2)
+
+        dialog.show_all()
+        self.dialog = dialog
+        self.entry = entry
+    
+    def _entry_cb(self, widget):
+        text = self.entry.get_text()
+        if text:
+            HatariTextInsert(self.hatari, text)
+            self.entry.set_text("")
+
+    def _enter_cb(self, widget):
+        self.hatari.insert_event("keypress 28") # Enter key scancode
+
+    def _doubleclick_cb(self, widget):
+        self.hatari.insert_event("doubleclick")
+
+    def _rightpress_cb(self, widget):
+        self.hatari.insert_event("rightdown")
+
+    def _rightrelease_cb(self, widget):
+        self.hatari.insert_event("rightup")
+
+    def run(self, hatari):
+        "run(hatari), do text/mouse click input"
+        self.hatari = hatari
+        self.dialog.run()
+        self.dialog.hide()
+
+
+# ---------------------------
+# Quit and Save dialog
+
+class QuitSaveDialog(HatariUIDialog):
+    def __init__(self, parent):
+        dialog = gtk.Dialog("Quit and Save?", parent,
+            gtk.DIALOG_MODAL | gtk.DIALOG_DESTROY_WITH_PARENT,
+            ("Save changes",    gtk.RESPONSE_YES,
+             "Discard changes", gtk.RESPONSE_NO,
+             gtk.STOCK_CANCEL,  gtk.RESPONSE_CANCEL))
+        dialog.vbox.add(gtk.Label("You have unsaved configuration changes:"))
+        viewport = gtk.Viewport()
+        viewport.add(gtk.Label())
+        scrolledwindow = gtk.ScrolledWindow()
+        scrolledwindow.set_policy(gtk.POLICY_AUTOMATIC, gtk.POLICY_AUTOMATIC)
+        scrolledwindow.add(viewport)
+        dialog.vbox.add(scrolledwindow)
+        dialog.show_all()
+        self.scrolledwindow = scrolledwindow
+        self.viewport = viewport
+        self.dialog = dialog
+        
+    def run(self, config):
+        "run(config) -> False if canceled, True otherwise or if no changes"
+        changes = []
+        for key, value in config.get_changes():
+            changes.append("%s = %s" % (key, str(value)))
+        if not changes:
+            return True
+        child = self.viewport.get_child()
+        child.set_text(config.get_path() + ":\n" + "\n".join(changes))
+        width, height = child.get_size_request()
+        if height < 320:
+            self.scrolledwindow.set_size_request(width, height)
+        else:
+            self.scrolledwindow.set_size_request(-1, 320)
+        self.viewport.show_all()
+        
+        response = self.dialog.run()
+        self.dialog.hide()
+        if response == gtk.RESPONSE_CANCEL:
+            return False
+        if response == gtk.RESPONSE_YES:
+            config.save()
+        return True
+
+
+# ---------------------------
+# Kill Hatari dialog
+
+class KillDialog(HatariUIDialog):
+    def __init__(self, parent):
+        self.dialog = gtk.MessageDialog(parent,
+        gtk.DIALOG_MODAL | gtk.DIALOG_DESTROY_WITH_PARENT,
+        gtk.MESSAGE_QUESTION, gtk.BUTTONS_OK_CANCEL,
+        """\
+Hatari emulator is already/still running and it needs to be terminated first. However, if it contains unsaved data, that will be lost.
+
+Terminate Hatari anyway?""")
+
+    def run(self, hatari):
+        "run(hatari) -> True if Hatari killed, False if left running"
+        if not hatari.is_running():
+            return True
+        # Hatari is running, OK to kill?
+        response = self.dialog.run()
+        self.dialog.hide()
+        if response == gtk.RESPONSE_OK:
+            hatari.kill()
+            return True
+        return False
+
+    
+# ---------------------------
+# Reset Hatari dialog
+
+class ResetDialog(HatariUIDialog):
+    COLD = 1
+    WARM = 2
+    def __init__(self, parent):
+        self.dialog = gtk.Dialog("Reset Atari?", parent,
+            gtk.DIALOG_MODAL | gtk.DIALOG_DESTROY_WITH_PARENT,
+            ("Cold reset", self.COLD, "Warm reset", self.WARM,
+             gtk.STOCK_CANCEL,  gtk.RESPONSE_CANCEL))
+        label = gtk.Label("\nRebooting will lose changes in currently\nrunning Atari programs.\n\nReset anyway?\n")
+        self.dialog.vbox.add(label)
+        label.show()
+
+    def run(self, hatari):
+        "run(hatari) -> True if Hatari rebooted, False if canceled"
+        if not hatari.is_running():
+            return False
+        # Hatari is running, how to reboot?
+        response = self.dialog.run()
+        self.dialog.hide()
+        if response == self.COLD:
+            hatari.trigger_shortcut("coldreset")
+        elif response == self.WARM:
+            hatari.trigger_shortcut("warmreset")
+        else:
+            return False
+        return True
+
+
+# ----------------------------------
+# Floppy image dialog
+
+class FloppyDialog(HatariUIDialog):
+    def _create_dialog(self, config):
+        table, self.dialog = create_table_dialog(self.parent, "Floppy images", 4, 2)
+        factory = FselAndEjectFactory()
+
+        row = 0
+        self.floppy = []
+        path = config.get_floppydir()
+        for drive in ("A", "B"):
+            label = "Disk %c image:" % drive
+            fname = config.get_floppy(row)
+            fsel, box = factory.get(label, path, fname, gtk.FILE_CHOOSER_ACTION_OPEN)
+            table_add_widget_row(table, row, label, box)
+            self.floppy.append(fsel)
+            row += 1
+
+        protect = gtk.combo_box_new_text()
+        for text in config.get_protection_types():
+            protect.append_text(text)
+        protect.set_active(config.get_floppy_protection())
+        protect.set_tooltip_text("Write protect floppy image contents")
+        table_add_widget_row(table, row, "Write protection:", protect)
+        row += 1
+
+        ds = gtk.CheckButton("Double sided drives")
+        ds.set_active(config.get_doublesided())
+        ds.set_tooltip_text("Whether drives are double or single sided. Can affect behavior of some games")
+        table_add_widget_row(table, row, None, ds)
+        row += 1
+        
+        driveb = gtk.CheckButton("Drive B connected")
+        driveb.set_active(config.get_floppy_drives()[1])
+        driveb.set_tooltip_text("Wheter drive B is connected. Can affect behavior of some demos & games")
+        table_add_widget_row(table, row, None, driveb)
+        row += 1
+
+        fastfdc = gtk.CheckButton("Fast floppy access")
+        fastfdc.set_active(config.get_fastfdc())
+        fastfdc.set_tooltip_text("Can cause incompatibilities with some games/demos")
+        table_add_widget_row(table, row, None, fastfdc)
+
+        table.show_all()
+
+        self.protect = protect
+        self.fastfdc = fastfdc
+        self.driveb = driveb
+        self.ds = ds
+    
+    def run(self, config):
+        "run(config), show disk image dialog"
+        if not self.dialog:
+            self._create_dialog(config)
+        response = self.dialog.run()
+        self.dialog.hide()
+        
+        if response == gtk.RESPONSE_APPLY:
+            config.lock_updates()
+            for drive in range(2):
+                config.set_floppy(drive, self.floppy[drive].get_filename())
+            config.set_floppy_protection(self.protect.get_active())
+            config.set_doublesided(self.ds.get_active())
+            config.set_fastfdc(self.fastfdc.get_active())
+            drives = (config.get_floppy_drives()[0], self.driveb.get_active())
+            config.set_floppy_drives(drives)
+            config.flush_updates()
+
+
+# ----------------------------------
+# Hard disk dialog
+
+class HardDiskDialog(HatariUIDialog):
+    def _create_dialog(self, config):
+        table, self.dialog = create_table_dialog(self.parent, "Hard disks", 4, 4, "Set and reboot")
+        factory = FselAndEjectFactory()
+
+        row = 0
+        label = "ASCI HD image:"
+        path = config.get_acsi_image()
+        fsel, box = factory.get(label, None, path, gtk.FILE_CHOOSER_ACTION_OPEN)
+        table_add_widget_row(table, row, label, box, True)
+        self.acsi = fsel
+        row += 1
+
+        label = "IDE HD master image:"
+        path = config.get_idemaster_image()
+        fsel, box = factory.get(label, None, path, gtk.FILE_CHOOSER_ACTION_OPEN)
+        table_add_widget_row(table, row, label, box, True)
+        self.idemaster = fsel
+        row += 1
+
+        label = "IDE HD slave image:"
+        path = config.get_ideslave_image()
+        fsel, box = factory.get(label, None, path, gtk.FILE_CHOOSER_ACTION_OPEN)
+        table_add_widget_row(table, row, label, box, True)
+        self.ideslave = fsel
+        row += 1
+
+        table_add_widget_row(table, row, " ", gtk.HSeparator(), True)
+        row += 1
+
+        label = "GEMDOS drive directory:"
+        path = config.get_hd_dir()
+        fsel, box = factory.get(label, None, path, gtk.FILE_CHOOSER_ACTION_SELECT_FOLDER)
+        table_add_widget_row(table, row, label, box, True)
+        self.hddir = fsel
+        row += 1
+
+        hddrive = gtk.combo_box_new_text()
+        for text in config.get_hd_drives():
+            hddrive.append_text(text)
+        hddrive.set_tooltip_text("Whether GEMDOS HD emulation uses fixed drive letter, or first free drive letter after ASCI & IDE drives (detection unreliable)")
+        table_add_widget_row(table, row, "GEMDOS HD drive:", hddrive)
+        self.hddrive = hddrive
+        row += 1
+
+        protect = gtk.combo_box_new_text()
+        for text in config.get_protection_types():
+            protect.append_text(text)
+        protect.set_tooltip_text("Whether/how to write protect (GEMDOS HD) emulation files, 'auto' means using host files' own properties")
+        table_add_widget_row(table, row, "Write protection:", protect)
+        self.protect = protect
+        row += 1
+        
+        lower = gtk.combo_box_new_text()
+        for text in config.get_hd_cases():
+            lower.append_text(text)
+        lower.set_tooltip_text("What to do with names of files created by Atari programs through GEMDOS HD emulation")
+        table_add_widget_row(table, row, "File names:", lower)
+        self.lower = lower
+
+        table.show_all()
+    
+    def _get_config(self, config):
+        path = config.get_acsi_image()
+        if path:
+            self.acsi.set_filename(path)
+        path = config.get_idemaster_image()
+        if path:
+            self.idemaster.set_filename(path)
+        path = config.get_ideslave_image()
+        if path:
+            self.ideslave.set_filename(path)
+        path = config.get_hd_dir()
+        if path:
+            self.hddir.set_filename(path)
+        self.hddrive.set_active(config.get_hd_drive())
+        self.protect.set_active(config.get_hd_protection())
+        self.lower.set_active(config.get_hd_case())
+
+    def _set_config(self, config):
+        config.lock_updates()
+        config.set_acsi_image(self.acsi.get_filename())
+        config.set_idemaster_image(self.idemaster.get_filename())
+        config.set_ideslave_image(self.ideslave.get_filename())
+        config.set_hd_dir(self.hddir.get_filename())
+        config.set_hd_drive(self.hddrive.get_active())
+        config.set_hd_protection(self.protect.get_active())
+        config.set_hd_case(self.lower.get_active())
+        config.flush_updates()
+
+    def run(self, config):
+        "run(config) -> bool, whether to reboot"
+        if not self.dialog:
+            self._create_dialog(config)
+
+        self._get_config(config)
+        response = self.dialog.run()
+        self.dialog.hide()
+        if response == gtk.RESPONSE_APPLY:
+            self._set_config(config)
+            return True
+        return False
+
+
+# ---------------------------
+# Display dialog
+
+class DisplayDialog(HatariUIDialog):
+
+    def _create_dialog(self, config):
+
+        skip = gtk.combo_box_new_text()
+        for text in config.get_frameskip_names():
+            skip.append_text(text)
+        skip.set_active(config.get_frameskip())
+        skip.set_tooltip_text("Set how many frames are skipped to speed up emulation")
+
+        slow = gtk.combo_box_new_text()
+        for text in config.get_slowdown_names():
+            slow.append_text(text)
+        slow.set_active(0)
+        slow.set_tooltip_text("VBL wait multiplier to slow down emulation. Breaks sound and large enough slowdown causes mouse clicks not to work.")
+
+        maxw, maxh = config.get_max_size()
+        topw, toph = config.get_desktop_size()
+        maxadjw = gtk.Adjustment(maxw, 320, topw, 8, 40)
+        maxadjh = gtk.Adjustment(maxh, 200, toph, 8, 40)
+        scalew = gtk.HScale(maxadjw)
+        scaleh = gtk.HScale(maxadjh)
+        scalew.set_digits(0)
+        scaleh.set_digits(0)
+        scalew.set_tooltip_text("Preferred/maximum zoomed width")
+        scaleh.set_tooltip_text("Preferred/maximum zoomed height")
+
+        force_max = gtk.CheckButton("Force max resolution (Falcon)")
+        force_max.set_active(config.get_force_max())
+        force_max.set_tooltip_text("Whether to force maximum resolution to help recording videos of demos which do resolution changes")
+
+        desktop = gtk.CheckButton("Keep desktop resolution (Falcon/TT)")
+        desktop.set_active(config.get_desktop())
+        desktop.set_tooltip_text("Whether to keep screen resolution in fullscreen and (try to) scale Atari screen by an integer factor instead")
+
+        desktop_st = gtk.CheckButton("Keep desktop resolution (ST/STE)")
+        desktop_st.set_active(config.get_desktop_st())
+        desktop_st.set_tooltip_text("Whether to keep screen resolution in fullscreen to avoid potential sound skips + delay (NO SCALING)")
+
+        borders = gtk.CheckButton("Atari screen borders")
+        borders.set_active(config.get_borders())
+        borders.set_tooltip_text("Whether to show overscan borders in ST/STE low/mid-rez or in Falcon color resolutions. Visible border area is affected by max. zoom size")
+
+        statusbar = gtk.CheckButton("Show statusbar")
+        statusbar.set_active(config.get_statusbar())
+        statusbar.set_tooltip_text("Whether to show statusbar with floppy leds etc")
+
+        led = gtk.CheckButton("Show overlay led")
+        led.set_active(config.get_led())
+        led.set_tooltip_text("Whether to show overlay drive led when statusbar isn't visible")
+
+        crop = gtk.CheckButton("Remove statusbar from screen capture")
+        crop.set_active(config.get_crop())
+        crop.set_tooltip_text("Whether to crop statusbar from screenshots and video recordings")
+
+        dialog = gtk.Dialog("Display settings", self.parent,
+            gtk.DIALOG_MODAL | gtk.DIALOG_DESTROY_WITH_PARENT,
+            (gtk.STOCK_APPLY,  gtk.RESPONSE_APPLY,
+             gtk.STOCK_CANCEL,  gtk.RESPONSE_CANCEL))
+
+        dialog.vbox.add(gtk.Label("Max zoomed size:"))
+        dialog.vbox.add(scalew)
+        dialog.vbox.add(scaleh)
+        dialog.vbox.add(force_max)
+        dialog.vbox.add(desktop)
+        dialog.vbox.add(desktop_st)
+        dialog.vbox.add(borders)
+        dialog.vbox.add(gtk.Label("Frameskip:"))
+        dialog.vbox.add(skip)
+        dialog.vbox.add(gtk.Label("Slowdown:"))
+        dialog.vbox.add(slow)
+        dialog.vbox.add(statusbar)
+        dialog.vbox.add(led)
+        dialog.vbox.add(crop)
+        dialog.vbox.show_all()
+
+        self.dialog = dialog
+        self.skip = skip
+        self.slow = slow
+        self.maxw = maxadjw
+        self.maxh = maxadjh
+        self.force_max = force_max
+        self.desktop = desktop
+        self.desktop_st = desktop_st
+        self.borders = borders
+        self.statusbar = statusbar
+        self.led = led
+        self.crop = crop
+ 
+    def run(self, config):
+        "run(config), show display dialog"
+        if not self.dialog:
+            self._create_dialog(config)
+        response = self.dialog.run()
+        self.dialog.hide()
+        if response == gtk.RESPONSE_APPLY:
+            config.lock_updates()
+            config.set_frameskip(self.skip.get_active())
+            config.set_slowdown(self.slow.get_active())
+            config.set_max_size(self.maxw.get_value(), self.maxh.get_value())
+            config.set_force_max(self.force_max.get_active())
+            config.set_desktop(self.desktop.get_active())
+            config.set_desktop_st(self.desktop_st.get_active())
+            config.set_borders(self.borders.get_active())
+            config.set_statusbar(self.statusbar.get_active())
+            config.set_led(self.led.get_active())
+            config.set_crop(self.crop.get_active())
+            config.flush_updates()
+
+
+# ----------------------------------
+# Joystick dialog
+
+class JoystickDialog(HatariUIDialog):
+    def _create_dialog(self, config):
+        table, self.dialog = create_table_dialog(self.parent, "Joystick settings", 9, 2)
+        
+        joy = 0
+        self.joy = []
+        joytypes = config.get_joystick_types()
+        for label in config.get_joystick_names():
+            combo = gtk.combo_box_new_text()
+            for text in joytypes:
+                combo.append_text(text)
+            combo.set_active(config.get_joystick(joy))
+            widget = table_add_widget_row(table, joy, "%s:" % label, combo)
+            self.joy.append(widget)
+            joy += 1
+
+        table.show_all()
+    
+    def run(self, config):
+        "run(config), show joystick dialog"
+        if not self.dialog:
+            self._create_dialog(config)
+        response = self.dialog.run()
+        self.dialog.hide()
+        
+        if response == gtk.RESPONSE_APPLY:
+            config.lock_updates()
+            for joy in range(6):
+                config.set_joystick(joy, self.joy[joy].get_active())
+            config.flush_updates()
+
+
+# ---------------------------------------
+# Peripherals (midi,printer,rs232) dialog
+
+class PeripheralDialog(HatariUIDialog):
+    def _create_dialog(self, config):
+        midi = gtk.CheckButton("Enable MIDI")
+        midi.set_active(config.get_midi())
+
+        printer = gtk.CheckButton("Enable printer output")
+        printer.set_active(config.get_printer())
+
+        rs232 = gtk.CheckButton("Enable RS232")
+        rs232.set_active(config.get_rs232())
+
+        dialog = gtk.Dialog("Peripherals", self.parent,
+            gtk.DIALOG_MODAL | gtk.DIALOG_DESTROY_WITH_PARENT,
+            (gtk.STOCK_APPLY,  gtk.RESPONSE_APPLY,
+             gtk.STOCK_CANCEL,  gtk.RESPONSE_CANCEL))
+        dialog.vbox.add(midi)
+        dialog.vbox.add(printer)
+        dialog.vbox.add(rs232)
+        dialog.vbox.show_all()
+
+        self.dialog = dialog
+        self.printer = printer
+        self.rs232 = rs232
+        self.midi = midi
+    
+    def run(self, config):
+        "run(config), show peripherals dialog"
+        if not self.dialog:
+            self._create_dialog(config)
+        response = self.dialog.run()
+        self.dialog.hide()
+        
+        if response == gtk.RESPONSE_APPLY:
+            config.lock_updates()
+            config.set_midi(self.midi.get_active())
+            config.set_printer(self.printer.get_active())
+            config.set_rs232(self.rs232.get_active())
+            config.flush_updates()
+
+
+# ---------------------------------------
+# Path dialog
+
+class PathDialog(HatariUIDialog):
+    def _create_dialog(self, config):
+        paths = config.get_paths()
+        table, self.dialog = create_table_dialog(self.parent, "File path settings", len(paths), 2)
+        paths.sort()
+        row = 0
+        self.paths = []
+        for (key, path, label) in paths:
+            fsel = FselEntry(self.dialog, self._validate_fname, key)
+            fsel.set_filename(path)
+            self.paths.append((key, fsel))
+            table_add_widget_row(table, row, label, fsel.get_container())
+            row += 1
+        table.show_all()
+    
+    def _validate_fname(self, key, fname):
+        if key != "soundout":
+            return True
+        if fname.rsplit(".", 1)[-1].lower() in ("ym", "wav"):
+            return True
+        ErrorDialog(self.dialog).run("Sound output file name:\n\t%s\nneeds to end with '.ym' or '.wav'." % fname)
+        return False
+    
+    def run(self, config):
+        "run(config), show paths dialog"
+        if not self.dialog:
+            self._create_dialog(config)
+        response = self.dialog.run()
+        self.dialog.hide()
+
+        if response == gtk.RESPONSE_APPLY:
+            paths = []
+            for key, fsel in self.paths:
+                paths.append((key, fsel.get_filename()))
+            config.set_paths(paths)
+
+
+# ---------------------------
+# Sound dialog
+
+class SoundDialog(HatariUIDialog):
+
+    def _create_dialog(self, config):
+        enabled, curhz = config.get_sound()
+
+        self.enabled = gtk.CheckButton("Sound enabled")
+        self.enabled.set_active(enabled)
+
+        hz = gtk.combo_box_new_text()
+        for text in config.get_sound_values():
+            hz.append_text(text)
+        hz.set_active(curhz)
+        self.hz = hz
+
+        ymmixer = gtk.combo_box_new_text()
+        for text in config.get_ymmixer_types():
+            ymmixer.append_text(text)
+        ymmixer.set_active(config.get_ymmixer())
+        self.ymmixer = ymmixer
+
+        adj = gtk.Adjustment(config.get_bufsize(), 0, 110, 10, 10, 10)
+        bufsize = gtk.HScale(adj)
+        bufsize.set_digits(0)
+        bufsize.set_tooltip_text("0 = use default value. In some situations, SDL default may cause large (~0.5s) sound delay at lower frequency.  If you have this problem, try with e.g. 20 ms, otherwise keep at 0.")
+        self.bufsize = bufsize
+
+        self.sync = gtk.CheckButton("Emulation speed synched to sound output")
+        self.sync.set_tooltip_text("Constantly adjust emulation screen update rate to match sound output. Can help if you suffer from sound buffer under/overflow.")
+        self.sync.set_active(config.get_sync())
+
+        self.mic = gtk.CheckButton("Enable (Falcon) microphone")
+        self.mic.set_active(config.get_mic())
+
+        dialog = gtk.Dialog("Sound settings", self.parent,
+            gtk.DIALOG_MODAL | gtk.DIALOG_DESTROY_WITH_PARENT,
+            (gtk.STOCK_APPLY,  gtk.RESPONSE_APPLY,
+             gtk.STOCK_CANCEL,  gtk.RESPONSE_CANCEL))
+        dialog.vbox.add(self.enabled)
+        dialog.vbox.add(gtk.Label("Sound frequency::"))
+        dialog.vbox.add(hz)
+        dialog.vbox.add(gtk.Label("YM voices mixing method:"))
+        dialog.vbox.add(ymmixer)
+        dialog.vbox.add(gtk.Label("SDL sound buffer size (ms):"))
+        dialog.vbox.add(bufsize)
+        dialog.vbox.add(self.sync)
+        dialog.vbox.add(self.mic)
+        dialog.vbox.show_all()
+        self.dialog = dialog
+
+    def run(self, config):
+        "run(config), show sound dialog"
+        if not self.dialog:
+            self._create_dialog(config)
+        response = self.dialog.run()
+        self.dialog.hide()
+        if response == gtk.RESPONSE_APPLY:
+            config.lock_updates()
+            config.set_mic(self.mic.get_active())
+            config.set_sync(self.sync.get_active())
+            config.set_bufsize(self.bufsize.get_value())
+            config.set_ymmixer(self.ymmixer.get_active())
+            enabled = self.enabled.get_active()
+            hz = self.hz.get_active()
+            config.set_sound(enabled, hz)
+            config.flush_updates()
+        
+
+# ---------------------------
+# Trace settings dialog
+
+class TraceDialog(HatariUIDialog):
+    # you can get this list with:
+    # hatari --trace help 2>&1|awk '/all$/{next} /^  [^-]/ {printf("\"%s\",\n", $1)}'
+    tracepoints = [
+        "video_sync",
+        "video_res",
+        "video_color",
+        "video_border_v",
+        "video_border_h",
+        "video_addr",
+        "video_hbl",
+        "video_vbl",
+        "video_ste",
+        "mfp_exception",
+        "mfp_start",
+        "mfp_read",
+        "mfp_write",
+        "psg_read",
+        "psg_write",
+        "cpu_pairing",
+        "cpu_disasm",
+        "cpu_exception",
+        "int",
+        "fdc",
+        "acia",
+        "ikbd_cmds",
+        "ikbd_acia",
+        "ikbd_exec",
+        "blitter",
+        "bios",
+        "xbios",
+        "gemdos",
+        "vdi",
+        "aes",
+        "io_read",
+        "io_write",
+        "dmasound",
+        "crossbar",
+        "videl",
+        "dsp_host_interface",
+        "dsp_host_command",
+        "dsp_host_ssi",
+        "dsp_interrupt",
+        "dsp_disasm",
+        "dsp_disasm_reg",
+        "dsp_disasm_mem",
+        "dsp_state",
+        "dsp_symbols",
+        "cpu_symbols",
+        "nvram",
+        "scsi_cmd",
+        "natfeats",
+        "keymap",
+        "midi",
+        "ide",
+    ]
+    def __init__(self, parent):
+        self.savedpoints = None
+        hbox1 = gtk.HBox()
+        hbox1.add(create_button("Load", self._load_traces))
+        hbox1.add(create_button("Clear", self._clear_traces))
+        hbox1.add(create_button("Save", self._save_traces))
+        hbox2 = gtk.HBox()
+        vboxes = []
+        for idx in (0,1,2,3):
+            vboxes.append(gtk.VBox())
+            hbox2.add(vboxes[idx])
+
+        count = 0
+        per_side = (len(self.tracepoints)+3)/4
+        self.tracewidgets = {}
+        for trace in self.tracepoints:
+            name = trace.replace("_", "-")
+            widget = gtk.CheckButton(name)
+            self.tracewidgets[trace] = widget
+            vboxes[count/per_side].pack_start(widget, False, True)
+            count += 1
+        
+        dialog = gtk.Dialog("Trace settings", parent,
+            gtk.DIALOG_MODAL | gtk.DIALOG_DESTROY_WITH_PARENT,
+            (gtk.STOCK_APPLY,  gtk.RESPONSE_APPLY,
+             gtk.STOCK_CLOSE, gtk.RESPONSE_CLOSE))
+        dialog.vbox.add(hbox1)
+        dialog.vbox.add(gtk.Label("Select trace points:"))
+        dialog.vbox.add(hbox2)
+        dialog.vbox.show_all()
+        self.dialog = dialog
+
+    def _get_traces(self):
+        traces = []
+        for trace in self.tracepoints:
+            if self.tracewidgets[trace].get_active():
+                traces.append(trace)
+        if traces:
+            return ",".join(traces)
+        return "none"
+
+    def _set_traces(self, tracepoints):
+        self._clear_traces()
+        if not tracepoints:
+            return
+        for trace in tracepoints.split(","):
+            if trace in self.tracewidgets:
+                self.tracewidgets[trace].set_active(True)
+            else:
+                print("ERROR: unknown trace setting '%s'" % trace)
+
+    def _clear_traces(self, widget = None):
+        for trace in self.tracepoints:
+            self.tracewidgets[trace].set_active(False)
+
+    def _load_traces(self, widget):
+        # this doesn't load traces, just sets them from internal variable
+        # that run method gets from caller and sets. It's up to caller
+        # whether the saving or loading happens actually to disk
+        self._set_traces(self.savedpoints)
+    
+    def _save_traces(self, widget):
+        self.savedpoints = self._get_traces()
+
+    def run(self, hatari, savedpoints):
+        "run(hatari,tracepoints) -> tracepoints, caller saves tracepoints"
+        self.savedpoints = savedpoints
+        while 1:
+            response = self.dialog.run()
+            if response == gtk.RESPONSE_APPLY:
+                hatari.change_option("--trace %s" % self._get_traces())
+            else:
+                self.dialog.hide()
+                return self.savedpoints
+
+
+# ------------------------------------------
+# Machine dialog for settings needing reboot
+
+class MachineDialog(HatariUIDialog):
+    def _machine_cb(self, widget, data):
+        if not widget.get_active():
+            return
+        machine = data.lower()
+        if machine == "ste" or machine == "st":
+            self.clocks[0].set_active(True)
+            self.cpulevel.set_active(0)
+        elif machine == "falcon":
+            self.clocks[1].set_active(True)
+            self.dsps[2].set_active(True)
+            self.cpulevel.set_active(3)
+        elif machine == "tt":
+            self.clocks[2].set_active(True)
+            self.cpulevel.set_active(3)
+
+    def _create_dialog(self, config):
+        table, self.dialog = create_table_dialog(self.parent, "Machine configuration", 6, 4, "Set and reboot")
+        
+        row = 0
+        self.machines = table_add_radio_rows(table, row, "Machine:",
+                        config.get_machine_types(), self._machine_cb)
+        row += 1
+
+        self.dsps = table_add_radio_rows(table, row, "DSP type:", config.get_dsp_types())
+        row += 1
+
+        # start next table column
+        row = 0
+        table_set_col_offset(table, 2)
+        self.monitors = table_add_radio_rows(table, row, "Monitor:", config.get_monitor_types())
+        row += 1
+
+        self.clocks = table_add_radio_rows(table, row, "CPU clock:", config.get_cpuclock_types())
+        row += 1
+
+        # fullspan at bottom
+        fullspan = True
+
+        combo = gtk.combo_box_new_text()
+        for text in config.get_cpulevel_types():
+            combo.append_text(text)
+        self.cpulevel = table_add_widget_row(table, row, "CPU type:", combo, fullspan)
+        row += 1
+
+        combo = gtk.combo_box_new_text()
+        for text in config.get_memory_names():
+            combo.append_text(text)
+        self.memory = table_add_widget_row(table, row, "Memory:", combo, fullspan)
+        row += 1
+
+        self.ttram = gtk.Adjustment(config.get_ttram(), 0, 260, 4, 4, 4)
+        ttram = gtk.HScale(self.ttram)
+        ttram.set_digits(0)
+        ttram.set_tooltip_text("TT-RAM needs Falcon/TT with WinUAE CPU core and implies 32-bit addressing.  0 = disabled, 24-bit addressing.")
+        table_add_widget_row(table, row, "TT-RAM", ttram, fullspan)
+        row += 1
+        
+        label = "TOS image:"
+        fsel = self._fsel(label, gtk.FILE_CHOOSER_ACTION_OPEN)
+        self.tos = table_add_widget_row(table, row, label, fsel, fullspan)
+        row += 1
+
+        vbox = gtk.VBox()
+        self.compatible = gtk.CheckButton("Compatible CPU")
+        self.rtc = gtk.CheckButton("Real-time clock")
+        self.timerd = gtk.CheckButton("Patch Timer-D")
+        self.compatible.set_tooltip_text("Needed for overscan and other timing sensitive things to work correctly")
+        self.rtc.set_tooltip_text("Some rare games and demos don't work with this")
+        self.timerd.set_tooltip_text("Improves ST/STE emulation performance, but some rare demos/games don't work with this")
+        vbox.add(self.compatible)
+        vbox.add(self.timerd)
+        vbox.add(self.rtc)
+        table_add_widget_row(table, row, "Misc.:", vbox, fullspan)
+        row += 1
+
+        table.show_all()
+
+    def _fsel(self, label, action):
+        fsel = gtk.FileChooserButton(label)
+        # Hatari cannot access URIs
+        fsel.set_local_only(True)
+        fsel.set_width_chars(12)
+        fsel.set_action(action)
+        return fsel
+    
+    def _get_config(self, config):
+        self.machines[config.get_machine()].set_active(True)
+        self.monitors[config.get_monitor()].set_active(True)
+        self.clocks[config.get_cpuclock()].set_active(True)
+        self.dsps[config.get_dsp()].set_active(True)
+        self.cpulevel.set_active(config.get_cpulevel())
+        self.memory.set_active(config.get_memory())
+        self.ttram.set_value(config.get_ttram())
+        tos = config.get_tos()
+        if tos:
+            self.tos.set_filename(tos)
+        self.compatible.set_active(config.get_compatible())
+        self.timerd.set_active(config.get_timerd())
+        self.rtc.set_active(config.get_rtc())
+
+    def _get_active_radio(self, radios):
+        idx = 0
+        for radio in radios:
+            if radio.get_active():
+                return idx
+            idx += 1
+        
+    def _set_config(self, config):
+        config.lock_updates()
+        config.set_machine(self._get_active_radio(self.machines))
+        config.set_monitor(self._get_active_radio(self.monitors))
+        config.set_cpuclock(self._get_active_radio(self.clocks))
+        config.set_dsp(self._get_active_radio(self.dsps))
+        config.set_cpulevel(self.cpulevel.get_active())
+        config.set_memory(self.memory.get_active())
+        config.set_ttram(self.ttram.get_value())
+        config.set_tos(self.tos.get_filename())
+        config.set_compatible(self.compatible.get_active())
+        config.set_timerd(self.timerd.get_active())
+        config.set_rtc(self.rtc.get_active())
+        config.flush_updates()
+
+    def run(self, config):
+        "run(config) -> bool, whether to reboot"
+        if not self.dialog:
+            self._create_dialog(config)
+
+        self._get_config(config)
+        response = self.dialog.run()
+        self.dialog.hide()
+        if response == gtk.RESPONSE_APPLY:
+            self._set_config(config)
+            return True
+        return False
diff --git a/python-ui/gentypes.py b/python-ui/gentypes.py
new file mode 100755
index 0000000..9ce9aca
--- /dev/null
+++ b/python-ui/gentypes.py
@@ -0,0 +1,32 @@
+#!/usr/bin/env python
+#
+# Utility to generate from Hatari C-code Python code for mapping
+# Hatari configuration variable names and types of those variables.
+#
+# Copyright (C) 2012 by Eero Tamminen
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+import os, re, sys
+
+# match first two items (variable name and type) from lines like:
+# { "bConfirmQuit", Bool_Tag, &ConfigureParams.Log.bConfirmQuit }
+reg = re.compile("\"([a-zA-Z0-9_]+)\",\s*([BIS][a-z]+)_Tag\s*,")
+
+print "# content generated by %s" % os.path.basename(sys.argv[0])
+print "conftypes = {"
+
+for line in sys.stdin.readlines():
+    match = reg.search(line)
+    if match:
+        print """    "%s": "%s",""" % match.groups()
+
+print "}"
diff --git a/python-ui/hatari-icon.png b/python-ui/hatari-icon.png
new file mode 100644
index 0000000..2858f83
Binary files /dev/null and b/python-ui/hatari-icon.png differ
diff --git a/python-ui/hatari-logo.png b/python-ui/hatari-logo.png
new file mode 100644
index 0000000..9a2e84e
Binary files /dev/null and b/python-ui/hatari-logo.png differ
diff --git a/python-ui/hatari.py b/python-ui/hatari.py
new file mode 100644
index 0000000..14732df
--- /dev/null
+++ b/python-ui/hatari.py
@@ -0,0 +1,903 @@
+#!/usr/bin/env python
+#
+# Classes for Hatari emulator instance and mapping its congfiguration
+# variables with its command line option.
+#
+# Copyright (C) 2008-2015 by Eero Tamminen
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+import os
+import sys
+import time
+import signal
+import socket
+import select
+from config import ConfigStore
+
+
+# Running Hatari instance
+class Hatari:
+    "running hatari instance and methods for communicating with it"
+    basepath = "/tmp/hatari-ui-" + str(os.getpid())
+    logpath = basepath + ".log"
+    tracepath = basepath + ".trace"
+    debugpath = basepath + ".debug"
+    controlpath = basepath + ".socket"
+    server = None # singleton due to path being currently one per user
+
+    def __init__(self, hataribin = None):
+        # collect hatari process zombies without waitpid()
+        signal.signal(signal.SIGCHLD, signal.SIG_IGN)
+        if hataribin:
+            self.hataribin = hataribin
+        else:
+            self.hataribin = "hatari"
+        self._create_server()
+        self.control = None
+        self.paused = False
+        self.pid = 0
+
+    def is_compatible(self):
+        "check Hatari compatibility and return error string if it's not"
+        error = "Hatari not found or it doesn't support the required --control-socket option!"
+        pipe = os.popen(self.hataribin + " -h")
+        for line in pipe.readlines():
+            if line.find("--control-socket") >= 0:
+                error = None
+                break
+        try:
+            pipe.close()
+        except IOError:
+            pass
+        return error
+
+    def save_config(self):
+        os.popen(self.hataribin + " --saveconfig")
+
+    def _create_server(self):
+        if self.server:
+            return
+        self.server = socket.socket(socket.AF_UNIX, socket.SOCK_STREAM)
+        if os.path.exists(self.controlpath):
+            os.unlink(self.controlpath)
+        self.server.bind(self.controlpath)
+        self.server.listen(1)
+        
+    def _send_message(self, msg):
+        if self.control:
+            self.control.send(msg)
+            return True
+        else:
+            print("ERROR: no Hatari (control socket)")
+            return False
+        
+    def change_option(self, option):
+        "change_option(option), changes given Hatari cli option"
+        return self._send_message("hatari-option %s\n" % option)
+        
+    def set_path(self, key, path):
+        "set_path(key, path), sets path with given key"
+        return self._send_message("hatari-path %s %s\n" % (key, path))
+
+    def set_device(self, device, enabled):
+        # needed because CLI options cannot disable devices, only enable
+        "set_path(device, enabled), sets whether given device is enabled or not"
+        if enabled:
+            return self._send_message("hatari-enable %s\n" % device)
+        else:
+            return self._send_message("hatari-disable %s\n" % device)
+        
+    def trigger_shortcut(self, shortcut):
+        "trigger_shortcut(shortcut), triggers given Hatari (keyboard) shortcut"
+        return self._send_message("hatari-shortcut %s\n" % shortcut)
+
+    def insert_event(self, event):
+        "insert_event(event), synthetizes given key/mouse Atari event"
+        return self._send_message("hatari-event %s\n" % event)
+
+    def debug_command(self, cmd):
+        "debug_command(command), runs given Hatari debugger command"
+        return self._send_message("hatari-debug %s\n" % cmd)
+
+    def pause(self):
+        "pause(), pauses Hatari emulation"
+        return self._send_message("hatari-stop\n")
+
+    def unpause(self):
+        "unpause(), continues Hatari emulation"
+        return self._send_message("hatari-cont\n")
+    
+    def _open_output_file(self, hataricommand, option, path):
+        if os.path.exists(path):
+            os.unlink(path)
+        # TODO: why fifo doesn't work properly (blocks forever on read or
+        #       reads only byte at the time and stops after first newline)?
+        #os.mkfifo(path)
+        #raw_input("attach strace now, then press Enter\n")
+        
+        # ask Hatari to open/create the requested output file...
+        hataricommand("%s %s" % (option, path))
+        wait = 0.025
+        # ...and wait for it to appear before returning it
+        for i in range(0, 8):
+            time.sleep(wait)
+            if os.path.exists(path):
+                return open(path, "r")
+            wait += wait
+        return None
+
+    def open_debug_output(self):
+        "open_debug_output() -> file, opens Hatari debugger output file"
+        return self._open_output_file(self.debug_command, "f", self.debugpath)
+
+    def open_trace_output(self):
+        "open_trace_output() -> file, opens Hatari tracing output file"
+        return self._open_output_file(self.change_option, "--trace-file", self.tracepath)
+
+    def open_log_output(self):
+        "open_trace_output() -> file, opens Hatari debug log file"
+        return self._open_output_file(self.change_option, "--log-file", self.logpath)
+    
+    def get_lines(self, fileobj):
+        "get_lines(file) -> list of lines readable from given Hatari output file"
+        # wait until data is available, then wait for some more
+        # and only then the data can be read, otherwise its old
+        print("Request&wait data from Hatari...")
+        select.select([fileobj], [], [])
+        time.sleep(0.1)
+        print("...read the data lines")
+        lines = fileobj.readlines()
+        print("".join(lines))
+        return lines
+
+    def enable_embed_info(self):
+        "enable_embed_info(), request embedded Hatari window ID change information"
+        self._send_message("hatari-embed-info\n")
+
+    def get_embed_info(self):
+        "get_embed_info() -> (width, height), get embedded Hatari window size"
+        width, height = self.control.recv(12).split("x")
+        return (int(width), int(height))
+
+    def get_control_socket(self):
+        "get_control_socket() -> socket which can be checked for embed ID changes"
+        return self.control
+        
+    def is_running(self):
+        "is_running() -> bool, True if Hatari is running, False otherwise"
+        if not self.pid:
+            return False
+        try:
+            os.waitpid(self.pid, os.WNOHANG)
+        except OSError as value:
+            print("Hatari PID %d had exited in the meanwhile:\n\t%s" % (self.pid, value))
+            self.pid = 0
+            if self.control:
+                self.control.close()
+                self.control = None
+            return False
+        return True
+    
+    def run(self, extra_args = None, parent_win = None):
+        "run([parent window][,embedding args]), runs Hatari"
+        # if parent_win given, embed Hatari to it
+        pid = os.fork()
+        if pid < 0:
+            print("ERROR: fork()ing Hatari failed!")
+            return
+        if pid:
+            # in parent
+            self.pid = pid
+            if self.server:
+                print("WAIT hatari to connect to control socket...")
+                (self.control, addr) = self.server.accept()
+                print("connected!")
+        else:
+            # child runs Hatari
+            env = os.environ
+            if parent_win:
+                self._set_embed_env(env, parent_win)
+            # callers need to take care of confirming quitting
+            args = [self.hataribin, "--confirm-quit", "off"]
+            if self.server:
+                args += ["--control-socket", self.controlpath]
+            if extra_args:
+                args += extra_args
+            print("RUN:", args)
+            os.execvpe(self.hataribin, args, env)
+
+    def _set_embed_env(self, env, parent_win):
+        if sys.platform == 'win32':
+            win_id = parent_win.handle
+        else:
+            win_id = parent_win.xid
+        # tell SDL to use given widget's window
+        #env["SDL_WINDOWID"] = str(win_id)
+
+        # above is broken: when SDL uses a window it hasn't created itself,
+        # it for some reason doesn't listen to any events delivered to that
+        # window nor implements XEMBED protocol to get them in a way most
+        # friendly to embedder:
+        #   http://standards.freedesktop.org/xembed-spec/latest/
+        #
+        # Instead we tell hatari to reparent itself after creating
+        # its own window into this program widget window
+        env["PARENT_WIN_ID"] = str(win_id)
+
+    def kill(self):
+        "kill(), kill Hatari if it's running"
+        if self.is_running():
+            os.kill(self.pid, signal.SIGKILL)
+            print("killed hatari with PID %d" % self.pid)
+            self.pid = 0
+        if self.control:
+            self.control.close()
+            self.control = None
+
+
+# Mapping of requested values both to Hatari configuration
+# and command line options.
+#
+# By default this doesn't allow setting any other configuration
+# variables than the ones that were read from the configuration
+# file i.e. you get an exception if configuration variables
+# don't match to current Hatari.  So before using this the current
+# Hatari configuration should have been saved at least once.
+#
+# Because of some inconsistencies in the values (see e.g. sound),
+# this cannot just do these according to some mapping table, but
+# it needs actual method for (each) setting.
+class HatariConfigMapping(ConfigStore):
+    _paths = {
+        "memauto": ("[Memory]", "szAutoSaveFileName", "Automatic memory snapshot"),
+        "memsave": ("[Memory]", "szMemoryCaptureFileName", "Manual memory snapshot"),
+        "midiin":  ("[Midi]", "sMidiInFileName", "Midi input"),
+        "midiout": ("[Midi]", "sMidiOutFileName", "Midi output"),
+        "rs232in": ("[RS232]", "szInFileName", "RS232 I/O input"),
+        "rs232out": ("[RS232]", "szOutFileName", "RS232 I/O output"),
+        "printout": ("[Printer]", "szPrintToFileName", "Printer output"),
+        "soundout": ("[Sound]", "szYMCaptureFileName", "Sound output")
+    }
+    "access methods to Hatari configuration file variables and command line options"
+    def __init__(self, hatari):
+        userconfdir = ".hatari"
+        ConfigStore.__init__(self, userconfdir)
+        conffilename = "hatari.cfg"
+        self.load(self.get_filepath(conffilename))
+
+        self._hatari = hatari
+        self._lock_updates = False
+        self._desktop_w = 0
+        self._desktop_h = 0
+        self._options = []
+
+    def validate(self):
+        "exception is thrown if the loaded configuration isn't compatible"
+        for method in dir(self):
+            if '_' not in method:
+                continue
+            # check class getters
+            starts = method[:method.find("_")]
+            if starts != "get":
+                continue
+            # but ignore getters for other things than config
+            ends = method[method.rfind("_")+1:]
+            if ends in ("types", "names", "values", "changes", "checkpoint", "filepath"):
+                continue
+            if ends in ("floppy", "joystick"):
+                # use port '0' for checks
+                getattr(self, method)(0)
+            else:
+                getattr(self, method)()
+
+    def _change_option(self, option, quoted = None):
+        "handle option changing, and quote spaces for quoted part of it"
+        if quoted:
+            option = "%s %s" % (option, quoted.replace(" ", "\\ "))
+        if self._lock_updates:
+            self._options.append(option)
+        else:
+            self._hatari.change_option(option)
+
+    def lock_updates(self):
+        "lock_updates(), collect Hatari configuration changes"
+        self._lock_updates = True
+    
+    def flush_updates(self):
+        "flush_updates(), apply collected Hatari configuration changes"
+        self._lock_updates = False
+        if not self._options:
+            return
+        self._hatari.change_option(" ".join(self._options))
+        self._options = []
+
+    # ------------ paths ---------------
+    def get_paths(self):
+        paths = []
+        for key, item in self._paths.items():
+            paths.append((key, self.get(item[0], item[1]), item[2]))
+        return paths
+    
+    def set_paths(self, paths):
+        for key, path in paths:
+            self.set(self._paths[key][0], self._paths[key][1], path)
+            self._hatari.set_path(key, path)
+
+    # ------------ midi ---------------
+    def get_midi(self):
+        return self.get("[Midi]", "bEnableMidi")
+
+    def set_midi(self, value):
+        self.set("[Midi]", "bEnableMidi", value)
+        self._hatari.set_device("midi", value)
+
+    # ------------ printer ---------------
+    def get_printer(self):
+        return self.get("[Printer]", "bEnablePrinting")
+
+    def set_printer(self, value):
+        self.set("[Printer]", "bEnablePrinting", value)
+        self._hatari.set_device("printer", value)
+
+    # ------------ RS232 ---------------
+    def get_rs232(self):
+        return self.get("[RS232]", "bEnableRS232")
+
+    def set_rs232(self, value):
+        self.set("[RS232]", "bEnableRS232", value)
+        self._hatari.set_device("rs232", value)
+
+    # ------------ machine ---------------
+    def get_machine_types(self):
+        return ("ST", "STE", "TT", "Falcon")
+
+    def get_machine(self):
+        return self.get("[System]", "nMachineType")
+
+    def set_machine(self, value):
+        self.set("[System]", "nMachineType", value)
+        self._change_option("--machine %s" % ("st", "ste", "tt", "falcon")[value])
+
+    # ------------ CPU level ---------------
+    def get_cpulevel_types(self):
+        return ("68000", "68010", "68020", "68EC030+FPU", "68040")
+
+    def get_cpulevel(self):
+        return self.get("[System]", "nCpuLevel")
+
+    def set_cpulevel(self, value):
+        self.set("[System]", "nCpuLevel", value)
+        self._change_option("--cpulevel %d" % value)
+
+    # ------------ CPU clock ---------------
+    def get_cpuclock_types(self):
+        return ("8 MHz", "16 MHz", "32 MHz") 
+
+    def get_cpuclock(self):
+        clocks = {8:0, 16: 1, 32:2}
+        return clocks[self.get("[System]", "nCpuFreq")]
+
+    def set_cpuclock(self, value):
+        clocks = [8, 16, 32]
+        if value < 0 or value > 2:
+            print("WARNING: CPU clock idx %d, clock fixed to 8 Mhz" % value)
+            value = 8
+        else:
+            value = clocks[value]
+        self.set("[System]", "nCpuFreq", value)
+        self._change_option("--cpuclock %d" % value)
+
+    # ------------ DSP type ---------------
+    def get_dsp_types(self):
+        return ("None", "Dummy", "Emulated")
+
+    def get_dsp(self):
+        return self.get("[System]", "nDSPType")
+
+    def set_dsp(self, value):
+        self.set("[System]", "nDSPType", value)
+        self._change_option("--dsp %s" % ("none", "dummy", "emu")[value])
+
+    # ------------ compatible ---------------
+    def get_compatible(self):
+        return self.get("[System]", "bCompatibleCpu")
+
+    def set_compatible(self, value):
+        self.set("[System]", "bCompatibleCpu", value)
+        self._change_option("--compatible %s" % str(value))
+
+    # ------------ Timer-D ---------------
+    def get_timerd(self):
+        return self.get("[System]", "bPatchTimerD")
+
+    def set_timerd(self, value):
+        self.set("[System]", "bPatchTimerD", value)
+        self._change_option("--timer-d %s" % str(value))
+
+    # ------------ RTC ---------------
+    def get_rtc(self):
+        return self.get("[System]", "bRealTimeClock")
+
+    def set_rtc(self, value):
+        self.set("[System]", "bRealTimeClock", value)
+        self._change_option("--rtc %s" % str(value))
+
+    # ------------ fastforward ---------------
+    def get_fastforward(self):
+        return self.get("[System]", "bFastForward")
+
+    def set_fastforward(self, value):
+        self.set("[System]", "bFastForward", value)
+        self._change_option("--fast-forward %s" % str(value))
+        
+    # ------------ sound ---------------
+    def get_sound_values(self):
+        # 48kHz, 44.1kHz and STE/TT/Falcon DMA 50066Hz divisable values
+        return ("6000", "6258", "8000", "11025", "12000", "12517",
+                "16000", "22050", "24000", "25033", "32000",
+                "44100", "48000", "50066")
+    
+    def get_sound(self):
+        enabled = self.get("[Sound]", "bEnableSound")
+        hz = str(self.get("[Sound]", "nPlaybackFreq"))
+        idx = self.get_sound_values().index(hz)
+        return (enabled, idx)
+
+    def set_sound(self, enabled, idx):
+        # map get_sound_values() index to Hatari config
+        hz = self.get_sound_values()[idx]
+        self.set("[Sound]", "nPlaybackFreq", int(hz))
+        self.set("[Sound]", "bEnableSound", enabled)
+        # and to cli option
+        if enabled:
+            self._change_option("--sound %s" % hz)
+        else:
+            self._change_option("--sound off")
+    
+    def get_ymmixer_types(self):
+        return ("linear", "table", "model")
+    
+    def get_ymmixer(self):
+        # values for types are start from 1, not 0
+        return self.get("[Sound]", "YmVolumeMixing")-1
+    
+    def set_ymmixer(self, value):
+        self.set("[Sound]", "YmVolumeMixing", value+1)
+        self._change_option("--ym-mixing %s" % self.get_ymmixer_types()[value])
+    
+    def get_bufsize(self):
+        return self.get("[Sound]", "nSdlAudioBufferSize")
+    
+    def set_bufsize(self, value):
+        value = int(value)
+        if value < 10: value = 10
+        if value > 100: value = 100
+        self.set("[Sound]", "nSdlAudioBufferSize", value)
+        self._change_option("--sound-buffer-size %d" % value)
+    
+    def get_sync(self):
+        return self.get("[Sound]", "bEnableSoundSync")
+    
+    def set_sync(self, value):
+        self.set("[Sound]", "bEnableSoundSync", value)
+        self._change_option("--sound-sync %s" % str(value))
+
+    def get_mic(self):
+        return self.get("[Sound]", "bEnableMicrophone")
+    
+    def set_mic(self, value):
+        self.set("[Sound]", "bEnableMicrophone", value)
+        self._change_option("--mic %s" % str(value))
+
+    # ----------- joystick --------------
+    def get_joystick_types(self):
+        return ("Disabled", "Real joystick", "Keyboard")
+    
+    def get_joystick_names(self):
+        return (
+        "ST Joystick 0",
+        "ST Joystick 1",
+        "STE Joypad A",
+        "STE Joypad B",
+        "Parport stick 1",
+        "Parport stick 2"
+        )
+
+    def get_joystick(self, port):
+        # return index to get_joystick_values() array
+        return self.get("[Joystick%d]" % port, "nJoystickMode")
+
+    def set_joystick(self, port, value):
+        # map get_sound_values() index to Hatari config
+        self.set("[Joystick%d]" % port, "nJoystickMode", value)
+        joytype = ("none", "real", "keys")[value]
+        self._change_option("--joy%d %s" % (port, joytype))
+
+    # ------------ floppy handling ---------------
+    def get_floppydir(self):
+        return self.get("[Floppy]", "szDiskImageDirectory")
+    
+    def set_floppydir(self, path):
+        return self.set("[Floppy]", "szDiskImageDirectory", path)
+
+    def get_floppy(self, drive):
+        return self.get("[Floppy]", "szDisk%cFileName" % ("A", "B")[drive])
+    
+    def set_floppy(self, drive, filename):
+        self.set("[Floppy]", "szDisk%cFileName" %  ("A", "B")[drive], filename)
+        self._change_option("--disk-%c" % ("a", "b")[drive], str(filename))
+
+    def get_floppy_drives(self):
+        return (self.get("[Floppy]", "EnableDriveA"), self.get("[Floppy]", "EnableDriveB"))
+
+    def set_floppy_drives(self, drives):
+        idx = 0
+        for drive in ("A", "B"):
+            value = drives[idx]
+            self.set("[Floppy]", "EnableDrive%c" % drive, value)
+            self._change_option("--drive-%c %s" % (drive.lower(), str(value)))
+            idx += 1
+
+    def get_fastfdc(self):
+        return self.get("[Floppy]", "FastFloppy")
+
+    def set_fastfdc(self, value):
+        self.set("[Floppy]", "FastFloppy", value)
+        self._change_option("--fastfdc %s" % str(value))
+
+    def get_doublesided(self):
+        driveA = self.get("[Floppy]", "DriveA_NumberOfHeads")
+        driveB = self.get("[Floppy]", "DriveB_NumberOfHeads")
+        if driveA > 1 or driveB > 1:
+            return True
+        return False
+    
+    def set_doublesided(self, value):
+        if value: sides = 2
+        else:     sides = 1
+        for drive in ("A", "B"):
+            self.set("[Floppy]", "Drive%c_NumberOfHeads" % drive, sides)
+            self._change_option("--drive-%c-heads %d" % (drive.lower(), sides))
+
+    # ------------- disk protection -------------
+    def get_protection_types(self):
+        return ("Off", "On", "Auto")
+
+    def get_floppy_protection(self):
+        return self.get("[Floppy]", "nWriteProtection")
+
+    def get_hd_protection(self):
+        return self.get("[HardDisk]", "nWriteProtection")
+
+    def set_floppy_protection(self, value):
+        self.set("[Floppy]", "nWriteProtection", value)
+        self._change_option("--protect-floppy %s" % self.get_protection_types()[value])
+
+    def set_hd_protection(self, value):
+        self.set("[HardDisk]", "nWriteProtection", value)
+        self._change_option("--protect-hd %s" % self.get_protection_types()[value])
+
+    # ------------ GEMDOS HD (dir) emulation ---------------
+    def get_hd_cases(self):
+        return ("No conversion", "Upper case", "Lower case")
+
+    def get_hd_case(self):
+        return self.get("[HardDisk]", "nGemdosCase")
+
+    def set_hd_case(self, value):
+        values = ("off", "upper", "lower")
+        self.set("[HardDisk]", "nGemdosCase", value)
+        self._change_option("--gemdos-case %s" % values[value])
+
+    def get_hd_drives(self):
+        return ['skip ACSI/IDE'] + [("%c:" % x) for x in range(ord('C'), ord('Z')+1)]
+
+    def get_hd_drive(self):
+        return self.get("[HardDisk]", "nGemdosDrive") + 1
+
+    def set_hd_drive(self, value):
+        value -= 1
+        self.set("[HardDisk]", "nGemdosDrive", value)
+        drive = chr(ord('C') + value)
+        if value < 0:
+            drive = "skip"
+        self._change_option("--gemdos-drive %s" % drive)
+
+    def get_hd_dir(self):
+        self.get("[HardDisk]", "bUseHardDiskDirectory") # for validation
+        return self.get("[HardDisk]", "szHardDiskDirectory")
+
+    def set_hd_dir(self, dirname):
+        if dirname and os.path.isdir(dirname):
+            self.set("[HardDisk]", "bUseHardDiskDirectory", True)
+        self.set("[HardDisk]", "szHardDiskDirectory", dirname)
+        self._change_option("--harddrive", str(dirname))
+
+    # ------------ ACSI HD (file) ---------------
+    def get_acsi_image(self):
+        self.get("[HardDisk]", "bUseHardDiskImage") # for validation
+        return self.get("[HardDisk]", "szHardDiskImage")
+
+    def set_acsi_image(self, filename):
+        if filename and os.path.isfile(filename):
+            self.set("[HardDisk]", "bUseHardDiskImage", True)
+        self.set("[HardDisk]", "szHardDiskImage", filename)
+        self._change_option("--acsi", str(filename))
+
+    # ------------ IDE master (file) ---------------
+    def get_idemaster_image(self):
+        self.get("[HardDisk]", "bUseIdeMasterHardDiskImage") # for validation
+        return self.get("[HardDisk]", "szIdeMasterHardDiskImage")
+
+    def set_idemaster_image(self, filename):
+        if filename and os.path.isfile(filename):
+            self.set("[HardDisk]", "bUseIdeMasterHardDiskImage", True)
+        self.set("[HardDisk]", "szIdeMasterHardDiskImage", filename)
+        self._change_option("--ide-master", str(filename))
+
+    # ------------ IDE slave (file) ---------------
+    def get_ideslave_image(self):
+        self.get("[HardDisk]", "bUseIdeSlaveHardDiskImage") # for validation
+        return self.get("[HardDisk]", "szIdeSlaveHardDiskImage")
+
+    def set_ideslave_image(self, filename):
+        if filename and os.path.isfile(filename):
+            self.set("[HardDisk]", "bUseIdeSlaveHardDiskImage", True)
+        self.set("[HardDisk]", "szIdeSlaveHardDiskImage", filename)
+        self._change_option("--ide-slave", str(filename))
+
+    # ------------ TOS ROM ---------------
+    def get_tos(self):
+        return self.get("[ROM]", "szTosImageFileName")
+    
+    def set_tos(self, filename):
+        self.set("[ROM]", "szTosImageFileName", filename)
+        self._change_option("--tos", str(filename))
+
+    # ------------ memory ---------------
+    def get_memory_names(self):
+        # empty item in list shouldn't be shown, filter them out
+        return ("512kB", "1MB", "2MB", "4MB", "8MB", "14MB")
+
+    def get_memory(self):
+        "return index to what get_memory_names() returns"
+        sizemap = (0, 1, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 5)
+        memsize = self.get("[Memory]", "nMemorySize")
+        if memsize >= 0 and memsize < len(sizemap):
+            return sizemap[memsize]
+        return 1 # default = 1BM
+
+    def set_memory(self, idx):
+        # map memory item index to memory size
+        sizemap = (0, 1, 2, 4, 8, 14)
+        if idx >= 0 and idx < len(sizemap):
+            memsize = sizemap[idx]
+        else:
+            memsize = 1
+        self.set("[Memory]", "nMemorySize", memsize)
+        self._change_option("--memsize %d" % memsize)
+
+    def get_ttram(self):
+        return self.get("[Memory]", "nTTRamSize")
+
+    def set_ttram(self, memsize):
+        # guarantee correct type (Gtk float -> config int)
+        memsize = int(memsize)
+        self.set("[Memory]", "nTTRamSize", memsize)
+        self._change_option("--ttram %d" % memsize)
+        if memsize:
+            # TT-RAM need 32-bit addressing (i.e. disable 24-bit)
+            self.set("[System]", "bAddressSpace24", False)
+            self._change_option("--addr24 off")
+        else:
+            # switch 24-bit addressing back for compatibility
+            self.set("[System]", "bAddressSpace24", True)
+            self._change_option("--addr24 on", False)
+
+    # ------------ monitor ---------------
+    def get_monitor_types(self):
+        return ("Mono", "RGB", "VGA", "TV")
+
+    def get_monitor(self):
+        return self.get("[Screen]", "nMonitorType")
+
+    def set_monitor(self, value):
+        self.set("[Screen]", "nMonitorType", value)
+        self._change_option("--monitor %s" % ("mono", "rgb", "vga", "tv")[value])
+
+    # ------------ frameskip ---------------
+    def get_frameskip_names(self):
+        return (
+            "Disabled",
+            "1 frame",
+            "2 frames",
+            "3 frames",
+            "4 frames",
+            "Automatic"
+        )
+    
+    def get_frameskip(self):
+        fs = self.get("[Screen]", "nFrameSkips")
+        if fs < 0 or fs > 5:
+            return 5
+        return fs
+    
+    def set_frameskip(self, value):
+        value = int(value) # guarantee correct type
+        self.set("[Screen]", "nFrameSkips", value)
+        self._change_option("--frameskips %d" % value)
+
+    # ------------ VBL slowdown ---------------
+    def get_slowdown_names(self):
+        return ("Disabled", "2x", "3x", "4x", "5x", "6x", "8x")
+    
+    def set_slowdown(self, value):
+        value = 1 + int(value)
+        self._change_option("--slowdown %d" % value)
+
+    # ------------ spec512 ---------------
+    def get_spec512threshold(self):
+        return self.get("[Screen]", "nSpec512Threshold")
+
+    def set_spec512threshold(self, value):
+        value = int(value) # guarantee correct type
+        self.set("[Screen]", "nSpec512Threshold", value)
+        self._change_option("--spec512 %d" % value)
+
+    # --------- keep desktop res -----------
+    def get_desktop(self):
+        return self.get("[Screen]", "bKeepResolution")
+    
+    def set_desktop(self, value):
+        self.set("[Screen]", "bKeepResolution", value)
+        self._change_option("--desktop %s" % str(value))
+
+    # --------- keep desktop res - st ------
+    def get_desktop_st(self):
+        return self.get("[Screen]", "bKeepResolutionST")
+    
+    def set_desktop_st(self, value):
+        self.set("[Screen]", "bKeepResolutionST", value)
+        self._change_option("--desktop-st %s" % str(value))
+
+    # ------------ force max ---------------
+    def get_force_max(self):
+        return self.get("[Screen]", "bForceMax")
+    
+    def set_force_max(self, value):
+        self.set("[Screen]", "bForceMax", value)
+        self._change_option("--force-max %s" % str(value))
+
+    # ------------ show borders ---------------
+    def get_borders(self):
+        return self.get("[Screen]", "bAllowOverscan")
+    
+    def set_borders(self, value):
+        self.set("[Screen]", "bAllowOverscan", value)
+        self._change_option("--borders %s" % str(value))
+
+    # ------------ show statusbar ---------------
+    def get_statusbar(self):
+        return self.get("[Screen]", "bShowStatusbar")
+    
+    def set_statusbar(self, value):
+        self.set("[Screen]", "bShowStatusbar", value)
+        self._change_option("--statusbar %s" % str(value))
+
+    # ------------ crop statusbar ---------------
+    def get_crop(self):
+        return self.get("[Screen]", "bCrop")
+    
+    def set_crop(self, value):
+        self.set("[Screen]", "bCrop", value)
+        self._change_option("--crop %s" % str(value))
+
+    # ------------ show led ---------------
+    def get_led(self):
+        return self.get("[Screen]", "bShowDriveLed")
+    
+    def set_led(self, value):
+        self.set("[Screen]", "bShowDriveLed", value)
+        self._change_option("--drive-led %s" % str(value))
+
+    # ------------ monitor aspect ratio ---------------
+    def get_aspectcorrection(self):
+        return self.get("[Screen]", "bAspectCorrect")
+    
+    def set_aspectcorrection(self, value):
+        self.set("[Screen]", "bAspectCorrect", value)
+        self._change_option("--aspect %s" % str(value))
+
+    # ------------ max window size ---------------
+    def set_desktop_size(self, w, h):
+        self._desktop_w = w
+        self._desktop_h = h
+        
+    def get_desktop_size(self):
+        return (self._desktop_w, self._desktop_h)
+
+    def get_max_size(self):
+        w = self.get("[Screen]", "nMaxWidth")
+        h = self.get("[Screen]", "nMaxHeight")
+        # default to desktop size?
+        if not (w or h):
+            w = self._desktop_w
+            h = self._desktop_h
+        return (w, h)
+
+    def set_max_size(self, w, h):
+        # guarantee correct type (Gtk float -> config int)
+        w = int(w); h = int(h)
+        self.set("[Screen]", "nMaxWidth", w)
+        self.set("[Screen]", "nMaxHeight", h)
+        self._change_option("--max-width %d" % w)
+        self._change_option("--max-height %d" % h)
+
+    # TODO: remove once UI doesn't need this anymore
+    def set_zoom(self, value):
+        print("Just setting Zoom, configuration doesn't anymore have setting for this.")
+        if value:
+            zoom = 2
+        else:
+            zoom = 1
+        self._change_option("--zoom %d" % zoom)
+
+    # ------------ configured Hatari window size ---------------
+    def get_window_size(self):
+        if self.get("[Screen]", "bFullScreen"):
+            print("WARNING: don't start Hatari UI with fullscreened Hatari!")
+
+        # VDI resolution?
+        if self.get("[Screen]", "bUseExtVdiResolutions"):
+            width = self.get("[Screen]", "nVdiWidth")
+            height = self.get("[Screen]", "nVdiHeight")
+            return (width, height)
+        
+        # window sizes for other than ST & STE can differ
+        if self.get("[System]", "nMachineType") not in (0, 1):
+            print("WARNING: neither ST nor STE machine, window size inaccurate!")
+            videl = True
+        else:
+            videl = False
+
+        # mono monitor?
+        if self.get_monitor() == 0:
+            return (640, 400)
+
+        # no, color
+        width = 320
+        height = 200
+        # statusbar?
+        if self.get_statusbar():
+            sbar = 12
+            height += sbar
+        else:
+            sbar = 0
+        # zoom?
+        maxw, maxh = self.get_max_size()
+        if 2*width <= maxw and 2*height <= maxh:
+            width *= 2
+            height *= 2
+            zoom = 2
+        else:
+            zoom = 1
+        # overscan borders?
+        if self.get_borders() and not videl:
+            # properly aligned borders on top of zooming
+            leftx = (maxw-width)/zoom
+            borderx = 2*(min(48,leftx/2)/16)*16
+            lefty = (maxh-height)/zoom
+            bordery = min(29+47, lefty)
+            width += zoom*borderx
+            height += zoom*bordery
+
+        return (width, height)
diff --git a/python-ui/hatariui b/python-ui/hatariui
new file mode 100755
index 0000000..0bda794
--- /dev/null
+++ b/python-ui/hatariui
@@ -0,0 +1,42 @@
+#!/bin/sh
+#
+# Don't modify the 'path' or 'conf' variable names or initial values,
+# those will be replaced by Makefile when this script is installed.
+
+path=${0%/*}
+name=${0##*/}
+
+if [ ! -e $path/$name.py ]; then
+	# Assume package has been relocated, try relative data directory:
+	path=${0%/*}/../share/hatari/hatariui
+fi
+
+# Assume hatari system configuration file dir is relative to hatariui dir
+# (usually system config file isn't installed, but if defaults need to be
+# configured differently from Hatari source code defaults, they're better
+# done with system config file than patching sources).
+conf=${path%/*}/../etc
+# checked by hatari UI
+export HATARI_SYSTEM_CONFDIR=$conf
+
+# example setup for Hatari UI
+$path/$name.py --right "about,|,run,pause,forward,|,reset,|,quit" --embed $*
+exit 0
+
+# test setup without embedding, duplicate toggles
+$path/$name.py --top "about,run,pause,quit" \
+--panel "Testpanel,pause,>,close" \
+--bottom "sound,|,forward,pause,|,Testpanel" \
+$*
+exit 0
+
+# test setup with embedding and all available controls
+$path/$name.py --embed \
+--top "about,|,run,pause,|,reset,debug,|,quit" \
+--left "run,pause,reset,machine,about" \
+--panel "Keys,F1=59,F2=60,F3=61,F4=62,F5=63,F6=64,F7=65,F8=66,F9=67,F10=68,>,Macro=Test,Undo=97,Help=98,Enter=114,>,close" \
+--panel "Misc,|,forward,full,|,sound,>,shot,>,close" \
+--bottom "forward,full,Misc,Keys,input,display,debug,trace" \
+--right "forward,full,Misc,Keys,input,display,Help=98" \
+$*
+exit 0
diff --git a/python-ui/hatariui.1 b/python-ui/hatariui.1
new file mode 100644
index 0000000..70e3f71
--- /dev/null
+++ b/python-ui/hatariui.1
@@ -0,0 +1,227 @@
+.\" Hey, EMACS: -*- nroff -*-
+.\" First parameter, NAME, should be all caps
+.\" Second parameter, SECTION, should be 1-8, maybe w/ subsection
+.\" other parameters are allowed: see man(7), man(1)
+.TH "hatariui" "1" "2010-05-30" "Hatari" "Hatari UI"
+.SH "NAME"
+hatariui \- Python/Gtk UI for Hatari
+.SH "SYNOPSIS"
+.B hatariui | hatariui.py
+.RI [options]
+.RI  [directory|diskimage|program]
+.SH "DESCRIPTION"
+.I hatariui
+is a Python/Gtk UI for Hatari which can either embed the Hatari window
+(on X11 systems) or run in a separate window.  By default it provides
+a normal application menu and some extra button for faster access to
+fast\-forward etc. functionality, but these are fully configurable
+with the command line options. While it lacks support for some of
+the Hatari configuration options that Hatari's SDL GUI has, it also
+supports some options that the Hatari's built\-in SDL UI doesn't.
+.PP
+Besides the UI configurability, some of the other advantages hatariui has
+over the SDL interface included with Hatari itself are use of a normal
+Gtk file selector with all of its features (directory shortcuts etc),
+support for UTF\-8 (in file names) and in general blending better to
+the user's desktop environment.
+.PP
+Additionally, Hatari can run while one uses UI configuration dialogs,
+and it can stop Hatari completely to better save the battery on mobile
+computers.  For devices without a keyboard, it offers a a text input
+dialog and one can configure (from command line) buttons for often used
+strings.
+.SH "HATARIUI / HATARIUI.PY"
+.I hatariui
+is actually a shell script wrapper for the hatariui.py Python script.
+It's used to run the Python script with suitable options for default
+usage and to set up the correct installation directory for the rest
+of the Hatari UI Python scripts and data files.
+.PP
+Options below are actually for hatariui.py script.  If you want to
+change options given for it, modify the hatariui shell script or
+make your own based on the installed one.
+.\" following command line helps in updating the options:
+.\" hatariui.py --help|sed -e 's/^\t\+/.TP\n.B /' -e 's/\t\+/\n/g' -e 's/-/\\-/g' >> hatariui.1
+.SH "OPTIONS"
+.TP
+.B \-h, \-\-help
+Hatari UI command line help
+.TP
+.B \-n, \-\-nomenu
+Omit menubar from the window
+.TP
+.B \-e, \-\-embed
+Embed Hatari window (to middle of controls)
+.TP
+.B \-f, \-\-fullscreen
+Start in fullscreen
+.TP
+.B \-l, \-\-left 
+Add a toolbar at left
+.TP
+.B \-r, \-\-right 
+Add a toolbar at right
+.TP
+.B \-t, \-\-top 
+Add a toolbar at top
+.TP
+.B \-b, \-\-bottom 
+Add a toolbar at bottom
+.TP
+.B \-p, \-\-panel ,
+Add a separate window with given name and controls
+.PP
+You can have only one toolbar on each side of the Hatari window.
+Panels are separate windows and you can has as many of them as you wish.
+For each panel you need to add a control with the name of the panel
+(see "MyPanel" in examples).
+.PP
+Following controls can are available for toolbars and panels:
+.TP
+.B |
+Separator between controls
+.TP
+.B >
+Start next toolbar row in panel windows
+.TP
+.B compatibility
+Hatari compatibility list
+.TP
+.B harddisk
+Hard disk images and directories
+.TP
+.B reset
+Warm or cold reset Hatari
+.TP
+.B sconfig
+Save configuration
+.TP
+.B bugs
+Report a bug
+.TP
+.B display
+Display settings
+.TP
+.B authors
+Hatari authors
+.TP
+.B forward
+Whether to fast forward Hatari (needs fast machine)
+.TP
+.B debug
+Activate Hatari debugger
+.TP
+.B quit
+Quit Hatari UI
+.TP
+.B hatari
+Hatari home page
+.TP
+.B recanim
+Record animation
+.TP
+.B recsound
+Record YM/Wav
+.TP
+.B mails
+Hatari mailing lists
+.TP
+.B floppy
+Floppy images
+.TP
+.B device
+Toggle Midi, Printer, RS232 peripherals
+.TP
+.B load
+Load emulation snapshot
+.TP
+.B lconfig
+Load configuration
+.TP
+.B path
+Device & save file paths
+.TP
+.B machine
+Hatari st/e/tt/falcon configuration
+.TP
+.B todo
+Hatari TODO
+.TP
+.B hatariui
+Hatari UI home page
+.TP
+.B save
+Save emulation snapshot
+.TP
+.B joystick
+Joystick settings
+.TP
+.B trace
+Hatari tracing setup
+.TP
+.B pause
+Pause Hatari to save battery
+.TP
+.B about
+Hatari UI information
+.TP
+.B release
+Hatari release notes
+.TP
+.B full
+Toggle whether Hatari is fullscreen
+.TP
+.B manual
+Hatari manual
+.TP
+.B input
+Simulate text input and mouse clicks
+.TP
+.B sound
+Sound settings
+.TP
+.B changes
+Latest Hatari changes
+.TP
+.B run
+(Re\-)run Hatari
+.TP
+.B shot
+Grab a screenshot
+.TP
+.B 
+Button for the specified panel window
+.TP
+.B =
+Synthetize string or single key 
+.PP
+If no options are given, the UI uses basic controls.
+.SH "EXAMPLES"
+Example on how to add top, right and bottom toolbars and a separate
+"MyPanel" panel window:
+.nf
+	hatariui.py \-\-embed \\
+	\-t "about,run,pause,quit" \\
+	\-p "MyPanel,Macro=Test,Undo=97,Help=98,>,F1=59,F2=60,>,close" \\
+	\-r "paste,debug,trace,machine,MyPanel" \\
+	\-b "sound,|,forward,|,fullscreen"
+.fi
+.PP
+For more examples on Hatari UI options usage, see the hatariui shell
+script.
+.SH "SEE ALSO"
+.IR hmsa (1),
+.IR hatariui (1),
+.IR hconsole (1)
+.SH "COPYRIGHT"
+Hatari UI is written by Eero Tamminen .
+.PP
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or (at
+your option) any later version.
+.PP
+This program is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
diff --git a/python-ui/hatariui.desktop b/python-ui/hatariui.desktop
new file mode 100644
index 0000000..b73456a
--- /dev/null
+++ b/python-ui/hatariui.desktop
@@ -0,0 +1,7 @@
+[Desktop Entry]
+Encoding=UTF-8
+Version=1.0
+Type=Application
+Name=Hatari UI
+Exec=hatariui
+Icon=hatari
diff --git a/python-ui/hatariui.py b/python-ui/hatariui.py
new file mode 100755
index 0000000..c21c61a
--- /dev/null
+++ b/python-ui/hatariui.py
@@ -0,0 +1,763 @@
+#!/usr/bin/env python
+#
+# A PyGtk UI for Hatari that can embed the Hatari emulator window.
+#
+# Requires PyGtk (python-gtk2) package and its dependencies to be present.
+#
+# Copyright (C) 2008-2011 by Eero Tamminen
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+import os
+import sys
+import getopt
+
+# use correct version of pygtk/gtk
+import pygtk
+pygtk.require('2.0')
+import gtk
+import gobject
+
+from debugui import HatariDebugUI
+from hatari import Hatari, HatariConfigMapping
+from uihelpers import UInfo, UIHelp, create_button, create_toolbutton, \
+     create_toggle, HatariTextInsert, get_open_filename, get_save_filename
+from dialogs import AboutDialog, TodoDialog, NoteDialog, ErrorDialog, \
+     InputDialog, KillDialog, QuitSaveDialog, ResetDialog, TraceDialog, \
+     FloppyDialog, HardDiskDialog, DisplayDialog, JoystickDialog, \
+     MachineDialog, PeripheralDialog, PathDialog, SoundDialog
+
+
+# helper functions to match callback args
+def window_hide_cb(window, arg):
+    window.hide()
+    return True
+
+
+# ---------------------------------------------------------------
+# Class with Hatari and configuration instances which methods are
+# called to change those (with additional dialogs or directly).
+# Owns the application window and socket widget embedding Hatari.
+class UICallbacks:
+    tmpconfpath = os.path.expanduser("~/.hatari/.tmp.cfg")
+    def __init__(self):
+        # Hatari and configuration
+        self.hatari = Hatari()
+        error = self.hatari.is_compatible()
+        if error:
+            ErrorDialog(None).run(error)
+            sys.exit(-1)
+            
+        self.config = HatariConfigMapping(self.hatari)
+        try:
+            self.config.validate()
+        except (KeyError, AttributeError):
+            NoteDialog(None).run("Loading Hatari configuration failed!\nRetrying after saving Hatari configuration.")
+            self.hatari.save_config()
+            self.config = HatariConfigMapping(self.hatari)
+            self.config.validate()
+        
+        # windows are created when needed
+        self.mainwin = None
+        self.hatariwin = None
+        self.debugui = None
+        self.panels = {}
+
+        # dialogs are created when needed
+        self.aboutdialog = None
+        self.inputdialog = None
+        self.tracedialog = None
+        self.resetdialog = None
+        self.quitdialog = None
+        self.killdialog = None
+
+        self.floppydialog = None
+        self.harddiskdialog = None
+        self.displaydialog = None
+        self.joystickdialog = None
+        self.machinedialog = None
+        self.peripheraldialog = None
+        self.sounddialog = None
+        self.pathdialog = None
+        
+        # used by run()
+        self.memstate = None
+        self.floppy = None
+        self.io_id = None
+
+        # TODO: Hatari UI own configuration settings save/load
+        self.tracepoints = None
+
+    def _reset_config_dialogs(self):
+        self.floppydialog = None
+        self.harddiskdialog = None
+        self.displaydialog = None
+        self.joystickdialog = None
+        self.machinedialog = None
+        self.peripheraldialog = None
+        self.sounddialog = None
+        self.pathdialog = None
+        
+    # ---------- create UI ----------------
+    def create_ui(self, accelgroup, menu, toolbars, fullscreen, embed):
+        "create_ui(menu, toolbars, fullscreen, embed)"
+        # add horizontal elements
+        hbox = gtk.HBox()
+        if toolbars["left"]:
+            hbox.pack_start(toolbars["left"], False, True)
+        if embed:
+            self._add_uisocket(hbox)
+        if toolbars["right"]:
+            hbox.pack_start(toolbars["right"], False, True)
+        # add vertical elements
+        vbox = gtk.VBox()
+        if menu:
+            vbox.add(menu)
+        if toolbars["top"]:
+            vbox.pack_start(toolbars["top"], False, True)
+        vbox.add(hbox)
+        if toolbars["bottom"]:
+            vbox.pack_start(toolbars["bottom"], False, True)
+        # put them to main window
+        mainwin = gtk.Window(gtk.WINDOW_TOPLEVEL)
+        mainwin.set_title("%s %s" % (UInfo.name, UInfo.version))
+        mainwin.set_icon_from_file(UInfo.icon)
+        if accelgroup:
+            mainwin.add_accel_group(accelgroup)
+        if fullscreen:
+            mainwin.fullscreen()
+        mainwin.add(vbox)
+        mainwin.show_all()
+        # for run and quit callbacks
+        self.killdialog = KillDialog(mainwin)
+        mainwin.connect("delete_event", self.quit)
+        self.mainwin = mainwin
+    
+    def _add_uisocket(self, box):
+        # add Hatari parent container to given box
+        socket = gtk.Socket()
+        # without this, closing Hatari would remove the socket widget
+        socket.connect("plug-removed", lambda obj: True)
+        socket.modify_bg(gtk.STATE_NORMAL, gtk.gdk.color_parse("black"))
+        socket.set_events(gtk.gdk.ALL_EVENTS_MASK)
+        socket.set_flags(gtk.CAN_FOCUS)
+        # set max Hatari window size = desktop size
+        self.config.set_desktop_size(gtk.gdk.screen_width(), gtk.gdk.screen_height())
+        # set initial embedded hatari size
+        width, height = self.config.get_window_size()
+        socket.set_size_request(width, height)
+        # no resizing for the Hatari window
+        box.pack_start(socket, False, False)
+        self.hatariwin = socket
+
+    # ------- run callback -----------
+    def _socket_cb(self, fd, event):
+        if event != gobject.IO_IN:
+            # hatari process died, make sure Hatari instance notices
+            self.hatari.kill()
+            return False
+        width, height = self.hatari.get_embed_info()
+        print("New size = %d x %d" % (width, height))
+        oldwidth, oldheight = self.hatariwin.get_size_request()
+        self.hatariwin.set_size_request(width, height)
+        if width < oldwidth or height < oldheight:
+            # force also mainwin smaller (it automatically grows)
+            self.mainwin.resize(width, height)
+        return True
+    
+    def run(self, widget = None):
+        if not self.killdialog.run(self.hatari):
+            return
+        if self.io_id:
+            gobject.source_remove(self.io_id)
+        args = ["--configfile"]
+        # whether to use Hatari config or unsaved Hatari UI config?
+        if self.config.is_changed():
+            args += [self.config.save_tmp(self.tmpconfpath)]
+        else:
+            args += [self.config.get_path()]
+        if self.memstate:
+            args += self.memstate
+        # only way to change boot order is to specify disk on command line
+        if self.floppy:
+            args += self.floppy
+        if self.hatariwin:
+            size = self.hatariwin.window.get_size()
+            self.hatari.run(args, self.hatariwin.window)
+            # get notifications of Hatari window size changes
+            self.hatari.enable_embed_info()
+            socket = self.hatari.get_control_socket().fileno()
+            events = gobject.IO_IN | gobject.IO_HUP | gobject.IO_ERR
+            self.io_id = gobject.io_add_watch(socket, events, self._socket_cb)
+            # all keyboard events should go to Hatari window
+            self.hatariwin.grab_focus()
+        else:
+            self.hatari.run(args)
+
+    def set_floppy(self, floppy):
+        self.floppy = floppy
+
+    # ------- quit callback -----------
+    def quit(self, widget, arg = None):
+        # due to Gtk API, needs to return True when *not* quitting
+        if not self.killdialog.run(self.hatari):
+            return True
+        if self.io_id:
+            gobject.source_remove(self.io_id)
+        if self.config.is_changed():
+            if not self.quitdialog:
+                self.quitdialog = QuitSaveDialog(self.mainwin)
+            if not self.quitdialog.run(self.config):
+                return True
+        gtk.main_quit()
+        if os.path.exists(self.tmpconfpath):
+            os.unlink(self.tmpconfpath)
+        # continue to mainwin destroy if called by delete_event
+        return False
+
+    # ------- pause callback -----------
+    def pause(self, widget):
+        if widget.get_active():
+            self.hatari.pause()
+        else:
+            self.hatari.unpause()
+
+    # dialogs
+    # ------- reset callback -----------
+    def reset(self, widget):
+        if not self.resetdialog:
+            self.resetdialog = ResetDialog(self.mainwin)
+        self.resetdialog.run(self.hatari)
+
+    # ------- about callback -----------
+    def about(self, widget):
+        if not self.aboutdialog:
+            self.aboutdialog = AboutDialog(self.mainwin)
+        self.aboutdialog.run()
+
+    # ------- input callback -----------
+    def inputs(self, widget):
+        if not self.inputdialog:
+            self.inputdialog = InputDialog(self.mainwin)
+        self.inputdialog.run(self.hatari)
+
+    # ------- floppydisk callback -----------
+    def floppydisk(self, widget):
+        if not self.floppydialog:
+            self.floppydialog = FloppyDialog(self.mainwin)
+        self.floppydialog.run(self.config)
+
+    # ------- harddisk callback -----------
+    def harddisk(self, widget):
+        if not self.harddiskdialog:
+            self.harddiskdialog = HardDiskDialog(self.mainwin)
+        self.harddiskdialog.run(self.config)
+
+    # ------- display callback -----------
+    def display(self, widget):
+        if not self.displaydialog:
+            self.displaydialog = DisplayDialog(self.mainwin)
+        self.displaydialog.run(self.config)
+
+    # ------- joystick callback -----------
+    def joystick(self, widget):
+        if not self.joystickdialog:
+            self.joystickdialog = JoystickDialog(self.mainwin)
+        self.joystickdialog.run(self.config)
+
+    # ------- machine callback -----------
+    def machine(self, widget):
+        if not self.machinedialog:
+            self.machinedialog = MachineDialog(self.mainwin)
+        if self.machinedialog.run(self.config):
+            self.hatari.trigger_shortcut("coldreset")
+
+    # ------- peripheral callback -----------
+    def peripheral(self, widget):
+        if not self.peripheraldialog:
+            self.peripheraldialog = PeripheralDialog(self.mainwin)
+        self.peripheraldialog.run(self.config)
+
+    # ------- sound callback -----------
+    def sound(self, widget):
+        if not self.sounddialog:
+            self.sounddialog = SoundDialog(self.mainwin)
+        self.sounddialog.run(self.config)
+
+    # ------- path callback -----------
+    def path(self, widget):
+        if not self.pathdialog:
+            self.pathdialog = PathDialog(self.mainwin)
+        self.pathdialog.run(self.config)
+
+    # ------- debug callback -----------
+    def debugger(self, widget):
+        if not self.debugui:
+            self.debugui = HatariDebugUI(self.hatari)
+        self.debugui.show()
+
+    # ------- trace callback -----------
+    def trace(self, widget):
+        if not self.tracedialog:
+            self.tracedialog = TraceDialog(self.mainwin)
+        self.tracepoints = self.tracedialog.run(self.hatari, self.tracepoints)
+
+    # ------ snapshot load/save callbacks ---------
+    def load(self, widget):
+        path = os.path.expanduser("~/.hatari/hatari.sav")
+        filename = get_open_filename("Select snapshot", self.mainwin, path)
+        if filename:
+            self.memstate = ["--memstate", filename]
+            self.run()
+            return True
+        return False
+
+    def save(self, widget):
+        self.hatari.trigger_shortcut("savemem")
+
+    # ------ config load/save callbacks ---------
+    def config_load(self, widget):
+        path = self.config.get_path()
+        filename = get_open_filename("Select configuration file", self.mainwin, path)
+        if filename:
+            self.hatari.change_option("--configfile %s" % filename)
+            self.config.load(filename)
+            self._reset_config_dialogs()
+            return True
+        return False
+
+    def config_save(self, widget):
+        path = self.config.get_path()
+        filename = get_save_filename("Save configuration as...", self.mainwin, path)
+        if filename:
+            self.config.save_as(filename)
+            return True
+        return False
+
+    # ------- fast forward callback -----------
+    def set_fastforward(self, widget):
+        self.config.set_fastforward(widget.get_active())
+
+    def get_fastforward(self):
+        return self.config.get_fastforward()
+
+    # ------- fullscreen callback -----------
+    def set_fullscreen(self, widget):
+        # if user can select this, Hatari isn't in fullscreen
+        self.hatari.change_option("--fullscreen")
+
+    # ------- screenshot callback -----------
+    def screenshot(self, widget):
+        self.hatari.trigger_shortcut("screenshot")
+
+    # ------- record callbacks -----------
+    def recanim(self, widget):
+        self.hatari.trigger_shortcut("recanim")
+
+    def recsound(self, widget):
+        self.hatari.trigger_shortcut("recsound")
+
+    # ------- insert key special callback -----------
+    def keypress(self, widget, code):
+        self.hatari.insert_event("keypress %s" % code)
+
+    def textinsert(self, widget, text):
+        HatariTextInsert(self.hatari, text)
+
+    # ------- panel callback -----------
+    def panel(self, action, box):
+        title = action.get_name()
+        if title not in self.panels:
+            window = gtk.Window(gtk.WINDOW_TOPLEVEL)
+            window.set_transient_for(self.mainwin)
+            window.set_icon_from_file(UInfo.icon)
+            window.set_title(title)
+            window.add(box)
+            window.set_type_hint(gtk.gdk.WINDOW_TYPE_HINT_DIALOG)
+            window.connect("delete_event", window_hide_cb)
+            self.panels[title] = window
+        else:
+            window = self.panels[title]
+        window.show_all()
+        window.deiconify()
+
+
+# ---------------------------------------------------------------
+# class for creating menus, toolbars and panels
+# and managing actions bound to them
+class UIActions:
+    def __init__(self):
+        cb = self.callbacks = UICallbacks()
+
+        self.help = UIHelp()
+        
+        self.actions = gtk.ActionGroup("All")
+        
+        # name, icon ID, label, accel, tooltip, callback
+        self.actions.add_toggle_actions((
+        # TODO: how to know when these are changed from inside Hatari?
+        ("recanim", gtk.STOCK_MEDIA_RECORD, "Record animation", "A", "Record animation", cb.recanim),
+        ("recsound", gtk.STOCK_MEDIA_RECORD, "Record sound", "W", "Record YM/Wav", cb.recsound),
+        ("pause", gtk.STOCK_MEDIA_PAUSE, "Pause", "P", "Pause Hatari to save battery", cb.pause),
+        ("forward", gtk.STOCK_MEDIA_FORWARD, "Forward", "F", "Whether to fast forward Hatari (needs fast machine)", cb.set_fastforward, cb.get_fastforward())
+        ))
+        
+        # name, icon ID, label, accel, tooltip, callback
+        self.actions.add_actions((
+        ("load", gtk.STOCK_OPEN, "Load snapshot...", "L", "Load emulation snapshot", cb.load),
+        ("save", gtk.STOCK_SAVE, "Save snapshot", "S", "Save emulation snapshot", cb.save),
+        ("shot", gtk.STOCK_MEDIA_RECORD, "Grab screenshot", "G", "Grab a screenshot", cb.screenshot),
+        ("quit", gtk.STOCK_QUIT, "Quit", "Q", "Quit Hatari UI", cb.quit),
+        
+        ("run", gtk.STOCK_MEDIA_PLAY, "Run", "R", "(Re-)run Hatari", cb.run),
+        ("full", gtk.STOCK_FULLSCREEN, "Fullscreen", "U", "Toggle whether Hatari is fullscreen", cb.set_fullscreen),
+        ("input", gtk.STOCK_SPELL_CHECK, "Inputs...", "N", "Simulate text input and mouse clicks", cb.inputs),
+        ("reset", gtk.STOCK_REFRESH, "Reset...", "E", "Warm or cold reset Hatari", cb.reset),
+        
+        ("display", gtk.STOCK_PREFERENCES, "Display...", "Y", "Display settings", cb.display),
+        ("floppy", gtk.STOCK_FLOPPY, "Floppies...", "D", "Floppy images", cb.floppydisk),
+        ("harddisk", gtk.STOCK_HARDDISK, "Hard disks...", "H", "Hard disk images and directories", cb.harddisk),
+        ("joystick", gtk.STOCK_CONNECT, "Joysticks...", "J", "Joystick settings", cb.joystick),
+        ("machine", gtk.STOCK_HARDDISK, "Machine...", "M", "Hatari st/e/tt/falcon configuration", cb.machine),
+        ("device", gtk.STOCK_PRINT, "Peripherals...", "V", "Toggle Midi, Printer, RS232 peripherals", cb.peripheral),
+        ("sound", gtk.STOCK_PROPERTIES, "Sound...", "O", "Sound settings", cb.sound),
+
+        ("path", gtk.STOCK_DIRECTORY, "Paths...", None, "Device & save file paths", cb.path),
+        ("lconfig", gtk.STOCK_OPEN, "Load config...", "C", "Load configuration", self.config_load),
+        ("sconfig", gtk.STOCK_SAVE_AS, "Save config as...", None, "Save configuration", cb.config_save),
+        
+        ("debug", gtk.STOCK_FIND, "Debugger...", "B", "Activate Hatari debugger", cb.debugger),
+        ("trace", gtk.STOCK_EXECUTE, "Trace settings...", "T", "Hatari tracing setup", cb.trace),
+        
+        ("manual", None, "Hatari manual", None, None, self.help.view_hatari_manual),
+        ("compatibility", None, "Hatari compatibility list", None, None, self.help.view_hatari_compatibility),
+        ("release", None, "Hatari release notes", None, None, self.help.view_hatari_releasenotes),
+        ("todo", None, "Hatari TODO", None, None, self.help.view_hatari_todo),
+        ("mails", None, "Hatari mailing lists", None, None, self.help.view_hatari_mails),
+        ("changes", None, "Latest Hatari changes", None, None, self.help.view_hatari_repository),
+        ("authors", None, "Hatari authors", None, None, self.help.view_hatari_authors),
+        ("hatari", None, "Hatari home page", None, None, self.help.view_hatari_page),
+        ("hatariui", None, "Hatari UI home page", None, None, self.help.view_hatariui_page),
+        ("about", gtk.STOCK_INFO, "Hatari UI info", "I", "Hatari UI information", cb.about)
+        ))
+        self.action_names = [x.get_name() for x in self.actions.list_actions()]
+
+        # no actions set yet to panels or toolbars
+        self.toolbars = {}
+        self.panels = []
+
+    def config_load(self, widget):
+        # user loads a new configuration?
+        if self.callbacks.config_load(widget):
+            print("TODO: reset toggle actions")
+
+    # ----- toolbar / panel additions ---------
+    def set_actions(self, action_str, place):
+        "set_actions(actions,place) -> error string, None if all OK"
+        actions = action_str.split(",")
+        for action in actions:
+            if action in self.action_names:
+                # regular action
+                continue
+            if action in self.panels:
+                # user specified panel
+                continue
+            if action in ("close", ">"):
+                if place != "panel":
+                    return "'close' and '>' can be only in a panel"
+                continue
+            if action == "|":
+                # divider
+                continue
+            if action.find("=") >= 0:
+                # special keycode/string action
+                continue
+            return "unrecognized action '%s'" % action
+
+        if place in ("left", "right", "top", "bottom"):
+            self.toolbars[place] = actions
+            return None
+        if place == "panel":
+            if len(actions) < 3:
+                return "panel has too few items to be useful"
+            return None
+        return "unknown actions position '%s'" % place
+
+    def add_panel(self, spec):
+        "add_panel(panel_specification) -> error string, None if all is OK"
+        offset = spec.find(",")
+        if offset <= 0:
+            return "invalid panel specification '%s'" % spec
+
+        name, panelcontrols = spec[:offset], spec[offset+1:]
+        error = self.set_actions(panelcontrols, "panel")
+        if error:
+            return error
+
+        if ",>," in panelcontrols:
+            box = gtk.VBox()
+            splitcontrols = panelcontrols.split(",>,")
+            for controls in splitcontrols:
+                box.add(self._get_container(controls.split(",")))
+        else:
+            box = self._get_container(panelcontrols.split(","))
+            
+        self.panels.append(name)
+        self.actions.add_actions(
+            ((name, gtk.STOCK_ADD, name, None, name, self.callbacks.panel),),
+            box
+        )
+        return None
+
+    def list_actions(self):
+        yield ("|", "Separator between controls")
+        yield (">", "Start next toolbar row in panel windows")
+        # generate the list from action information
+        for act in self.actions.list_actions():
+            note = act.get_property("tooltip")
+            if not note:
+                note = act.get_property("label")
+            yield(act.get_name(), note)
+        yield ("", "Button for the specified panel window")
+        yield ("=", "Synthetize string or single key ")
+
+    # ------- panel special actions -----------
+    def _close_cb(self, widget):
+        widget.get_toplevel().hide()
+
+    # ------- key special action -----------
+    def _create_key_control(self, name, textcode):
+        "Simulate Atari key press/release and string inserting"
+        if not textcode:
+            return None
+        widget = gtk.ToolButton(gtk.STOCK_PASTE)
+        widget.set_label(name)
+        try:
+            # part after "=" converts to an int?
+            code = int(textcode, 0)
+            widget.connect("clicked", self.callbacks.keypress, code)
+            tip = "keycode: %d" % code
+        except ValueError:
+            # no, assume a string macro is wanted instead
+            widget.connect("clicked", self.callbacks.textinsert, textcode)
+            tip = "string '%s'" % textcode
+        widget.set_tooltip_text("Insert " + tip)
+        return widget
+
+    def _get_container(self, actions, horiz = True):
+        "return Gtk container with the specified actions or None for no actions"
+        if not actions:
+            return None
+
+        #print("ACTIONS:", actions)
+        if len(actions) > 1:
+            bar = gtk.Toolbar()
+            if horiz:
+                bar.set_orientation(gtk.ORIENTATION_HORIZONTAL)
+            else:
+                bar.set_orientation(gtk.ORIENTATION_VERTICAL)
+            bar.set_style(gtk.TOOLBAR_BOTH)
+            # disable overflow menu to get toolbar sized correctly for panels
+            bar.set_show_arrow(False)
+        else:
+            bar = None
+        
+        for action in actions:
+            #print(action)
+            offset = action.find("=")
+            if offset >= 0:
+                # handle "=" action specification
+                name = action[:offset]
+                text = action[offset+1:]
+                widget = self._create_key_control(name, text)
+            elif action == "|":
+                widget = gtk.SeparatorToolItem()
+            elif action == "close":
+                if bar:
+                    widget = create_toolbutton(gtk.STOCK_CLOSE, self._close_cb)
+                else:
+                    widget = create_button("Close", self._close_cb)
+            else:
+                widget = self.actions.get_action(action).create_tool_item()
+            if not widget:
+                continue
+            if bar:
+                if action != "|":
+                    widget.set_expand(True)
+                bar.insert(widget, -1)
+        if bar:
+            return bar
+        return widget
+
+    # ------------- handling menu -------------
+    def _add_submenu(self, bar, title, items):
+        submenu = gtk.Menu()
+        for name in items:
+            if name:
+                action = self.actions.get_action(name)
+                item = action.create_menu_item()
+            else:
+                item = gtk.SeparatorMenuItem()
+            submenu.add(item)
+        baritem = gtk.MenuItem(title, False)
+        baritem.set_submenu(submenu)
+        bar.add(baritem)
+
+    def _get_menu(self):
+        allmenus = (
+        ("File", ("load", "save", None, "shot", "recanim", "recsound", None, "quit")),
+        ("Emulation", ("run", "pause", "forward", None, "full", None, "input", None, "reset")),
+        ("Devices", ("display", "floppy", "harddisk", "joystick", "machine", "device", "sound")),
+        ("Configuration", ("path", None, "lconfig", "sconfig")),
+        ("Debug", ("debug", "trace")),
+        ("Help", ("manual", "compatibility", "release", "todo", None, "mails", "changes", None, "authors", "hatari", "hatariui", "about",))
+        )
+        bar = gtk.MenuBar()
+
+        for title, items in allmenus:
+            self._add_submenu(bar, title, items)
+
+        if self.panels:
+            self._add_submenu(bar, "Panels", self.panels)
+
+        return bar
+
+    # ------------- run the whole UI -------------
+    def run(self, floppy, havemenu, fullscreen, embed):
+        accelgroup = None
+        # create menu?
+        if havemenu:
+            # this would steal keys from embedded Hatari
+            if not embed:
+                accelgroup = gtk.AccelGroup()
+                for action in self.actions.list_actions():
+                    action.set_accel_group(accelgroup)
+            menu = self._get_menu()
+        else:
+            menu = None
+
+        # create toolbars
+        toolbars = { "left":None, "right":None, "top":None, "bottom":None}
+        for side in ("left", "right"):
+            if side in self.toolbars:
+                toolbars[side] = self._get_container(self.toolbars[side], False)
+        for side in ("top", "bottom"):
+            if side in self.toolbars:
+                toolbars[side] = self._get_container(self.toolbars[side], True)
+
+        self.callbacks.create_ui(accelgroup, menu, toolbars, fullscreen, embed)
+        self.help.set_mainwin(self.callbacks.mainwin)
+        self.callbacks.set_floppy(floppy)
+
+        # ugly, Hatari socket window ID can be gotten only
+        # after Socket window is realized by gtk_main()
+        gobject.idle_add(self.callbacks.run)
+        gtk.main()
+
+
+# ------------- usage / argument handling --------------
+def usage(actions, msg=None):
+    name = os.path.basename(sys.argv[0])
+    uiname = "%s %s" % (UInfo.name, UInfo.version)
+    print("\n%s" % uiname)
+    print("=" * len(uiname))
+    print("\nUsage: %s [options] [directory|disk image|Atari program]" % name)
+    print("\nOptions:")
+    print("\t-h, --help\t\tthis help")
+    print("\t-n, --nomenu\t\tomit menus")
+    print("\t-e, --embed\t\tembed Hatari window in middle of controls")
+    print("\t-f, --fullscreen\tstart in fullscreen")
+    print("\t-l, --left \ttoolbar at left")
+    print("\t-r, --right \ttoolbar at right")
+    print("\t-t, --top \ttoolbar at top")
+    print("\t-b, --bottom \ttoolbar at bottom")
+    print("\t-p, --panel ,")
+    print("\t\t\t\tseparate window with given name and controls")
+    print("\nAvailable (panel/toolbar) controls:")
+    for action, description in actions.list_actions():
+        size = len(action)
+        if size < 8:
+            tabs = "\t\t"
+        elif size < 16:
+            tabs = "\t"
+        else:
+            tabs = "\n\t\t\t"
+        print("\t%s%s%s" % (action, tabs, description))
+    print("""
+You can have as many panels as you wish.  For each panel you need to add
+a control with the name of the panel (see "MyPanel" below).
+
+For example:
+\t%s --embed \\
+\t-t "about,run,pause,quit" \\
+\t-p "MyPanel,Macro=Test,Undo=97,Help=98,>,F1=59,F2=60,F3=61,F4=62,>,close" \\
+\t-r "paste,debug,trace,machine,MyPanel" \\
+\t-b "sound,|,fastforward,|,fullscreen"
+
+if no options are given, the UI uses basic controls.
+""" % name)
+    if msg:
+        print("ERROR: %s\n" % msg)
+    sys.exit(1)
+
+
+def main():
+    info = UInfo()
+    actions = UIActions()
+    try:
+        longopts = ["embed", "fullscreen", "nomenu", "help",
+            "left=", "right=", "top=", "bottom=", "panel="]
+        opts, floppies = getopt.getopt(sys.argv[1:], "efnhl:r:t:b:p:", longopts)
+        del longopts
+    except getopt.GetoptError as err:
+        usage(actions, err)
+
+    menu = True
+    embed = False
+    fullscreen = False
+
+    error = None
+    for opt, arg in opts:
+        print(opt, arg)
+        if opt in ("-e", "--embed"):
+            embed = True
+        elif opt in ("-f", "--fullscreen"):
+            fullscreen = True
+        elif opt in ("-n", "--nomenu"):
+            menu = False
+        elif opt in ("-h", "--help"):
+            usage(actions)
+        elif opt in ("-l", "--left"):
+            error = actions.set_actions(arg, "left")
+        elif opt in ("-r", "--right"):
+            error = actions.set_actions(arg, "right")
+        elif opt in ("-t", "--top"):
+            error = actions.set_actions(arg, "top")
+        elif opt in ("-b", "--bottom"):
+            error = actions.set_actions(arg, "bottom")
+        elif opt in ("-p", "--panel"):
+            error = actions.add_panel(arg)
+        else:
+            assert False, "getopt returned unhandled option"
+        if error:
+            usage(actions, error)
+
+    if len(floppies) > 1:
+        usage(actions, "multiple floppy images given: %s" % str(floppies))
+    if floppies:
+        if not os.path.exists(floppies[0]):
+            usage(actions, "floppy image '%s' doesn't exist" % floppies[0])
+
+    actions.run(floppies, menu, fullscreen, embed)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/python-ui/release-notes.txt b/python-ui/release-notes.txt
new file mode 100644
index 0000000..d27e4ec
--- /dev/null
+++ b/python-ui/release-notes.txt
@@ -0,0 +1,111 @@
+
+User visible changes in Hatari (Python Gtk) UI
+----------------------------------------------
+
+2015-05:
+- Add support for --gemdos-drive, --ttram option features
+  and new tracepoints
+- Debugger window supports WinUAE CPU core
+- Updated UI version to 1.3
+
+2014-06:
+- Add support for --sound-sync, --sound-buffer-size,
+  --slowdown, --gemdos-case, --drive-*-heads and
+  --drive-* option features and new tracepoints
+- Improved option names & descriptions
+- update UI version to 1.2
+
+2012-05:
+- Add --desktop-st and --force-max options support
+  (latter helps video recording of Falcon demos
+   doing lots of resolution changes)
+
+2012-01:
+- Add microphone and YM voice mixing sound options
+- Fix asserts and empty hatari config file caused by
+  Hatari v1.6 config variable names changes by changing
+  how Hatari config variable types are handled
+- Update UI version to v1.1 (mainly due to config change)
+- Support spaces in file paths/names
+
+2011-10:
+- Replace --slowfdc with --fastfdc
+
+2011-04:
+- Support RTC and "keep desktop resolution" options
+
+2011-02:
+- Support new tracepoints (AES, DSP, Videl, Crossbar)
+- Disasm update for new Hatari disassembly output
+
+2011-01:
+- Use new Gtk v2.12 tooltip API
+- Support capture cropping
+
+2010-10:
+- Improvements to text & key inserting
+- Move hatari-console.py elsewhere
+
+2010-05:
+- Manual page for Hatari UI
+
+2010-04:
+- UI handles Hatari system configuration properly
+- New settings dialog for HD dir and image configuration
+- Maximum/preferred zoom support to display settings dialog
+- Removed --spec512 support
+- Option for whether debugger will change to new PC address
+  whenever emulation is stopped again
+
+2010-03:
+- With the new Hatari --saveconfig option Hatari UI can ask Hatari
+  to save its configuration (required by the UI) before the UI itself
+  starts, user doesn't need to do it manually anymore
+  (if user config is missing or out of date)
+- Added --slowfdc support to Floppy settings dialog
+
+2009-09:
+- Support for setting CPU level & clock and Falcon DSP type
+
+2009-08:
+- Update to latest Hatari 1.3.0:
+  - Debug/trace fixes (Hatari 1.3.1 includes these)
+
+2009-07:
+- Add Help menu items pointing to Hatari docs & site
+- --timer-d support + doc updates
+
+2009-06:
+- Move to BerliOS Hatari repo
+- Update to latest Hatari 1.2.0:
+  - midi in/out, sound freq etc
+
+2008-10:
+- Support paths & peripherals settings
+
+2008-09:
+- Support for auto frameskip, statusbar and overlay led
+- Remove support for multiple machine setups
+  (now that run-time Hatari config/saving loading works)
+
+2008-07:
+- Support recanim/sound, config load/save and memory snapshot load/save
+- First properly working with menus and toolbars instead of buttons
+- Can adapt properly also to Hatari window getting smaller
+  (works on desktop, maemo/Matchbox WM have still issues)
+- Makefile for installation
+
+2008-06:
+- Fairly usable version with configurable buttons
+- Can adapt to Hatari window size changes
+
+2008-05:
+- Loading & saving Hatari configuration and checking
+  changes against saved configuration works
+
+2008-04:
+- First version with debugger UI
+
+2008-02:
+- First version that can embed Hatari window (needed quite
+  a lot of testing to find method that works well enough)
diff --git a/python-ui/tests/README b/python-ui/tests/README
new file mode 100644
index 0000000..46d22f2
--- /dev/null
+++ b/python-ui/tests/README
@@ -0,0 +1,6 @@
+
+Files
+-----
+
+pygtk-hatari-embed-test.py -- Several tries at embedding Hatari window
+pygtk-hello-world.py -- simplest PyGtk program
diff --git a/python-ui/tests/pygtk-hatari-embed-test.py b/python-ui/tests/pygtk-hatari-embed-test.py
new file mode 100644
index 0000000..a40254d
--- /dev/null
+++ b/python-ui/tests/pygtk-hatari-embed-test.py
@@ -0,0 +1,200 @@
+#!/usr/bin/python
+#
+# Tests embedding hatari with three different methods:
+# "hatari": ask Hatari to reparent to given window
+# "sdl": Give SDL window into which it should reparent
+#   -> SDL doesn't handle (mouse, key, expose) events
+#      although according to "xev" it's window receives them!
+#      Bug in SDL (not one of the originally needed features?)?
+# "reparent": Find Hatari window and reparent it into pygtk widget in python
+#   - Needs "xwininfo" and "awk"
+#
+# Using three alternative widgets:
+#   "drawingarea"
+#   "eventbox"
+#   "socket"
+#
+# Results:
+#   reparent+eventbox
+#     -> PyGtk reparents Hatari under something on rootwindow instead
+#        (reparening eventbox under Hatari window works fine though...)
+#   reparent+socket
+#     -> Hatari seems to be reparented back to where it was
+#   sdl+anything
+#     -> all events are lost
+#   hatari+socket
+#     -> seems to work fine
+import os
+import sys
+import gtk
+import time
+import gobject
+
+def usage(error):
+    print "\nusage: %s  \n" % sys.argv[0].split(os.path.sep)[-1]
+    print "Opens window with given , runs Hatari and tries to embed it"
+    print "with given \n"
+    print " can be "
+    print " can be \n"
+    print "ERROR: %s\n" % error
+    sys.exit(1)
+
+
+class AppUI():
+    hatari_wd = 640
+    hatari_ht = 400
+    
+    def __init__(self, widget, method):
+        if method in ("hatari", "reparent", "sdl"):
+            self.method = method
+        else:
+            usage("unknown  '%s'" % method)
+        if widget == "drawingarea":
+            widgettype = gtk.DrawingArea
+        elif widget == "eventbox":
+            widgettype = gtk.EventBox
+        elif widget == "socket":
+            # XEMBED socket for Hatari/SDL
+            widgettype = gtk.Socket
+        else:
+            usage("unknown  '%s'" % widget)
+        self.window = self.create_window()
+        self.add_hatari_parent(self.window, widgettype)
+        gobject.timeout_add(1*1000, self.timeout_cb)
+        
+    def create_window(self):
+        window = gtk.Window(gtk.WINDOW_TOPLEVEL)
+        window.connect("destroy", self.do_quit)
+        return window
+    
+    def do_quit(self, widget):
+        if self.hatari_pid:
+            os.kill(self.hatari_pid, 9)
+            print "killed Hatari PID %d" % self.hatari_pid
+            self.hatari_pid = 0
+        gtk.main_quit()
+    
+    def add_hatari_parent(self, parent, widgettype):
+        # Note: CAN_FOCUS has to be set for the widget embedding Hatari
+        # and *unset* for everything else, otherwise Hatari doesn't
+        # receive *any* keyevents.
+        self.hatari_pid = 0
+        vbox = gtk.VBox()
+        button = gtk.Button("Test Button")
+        button.unset_flags(gtk.CAN_FOCUS)
+        vbox.add(button)
+        widget = widgettype()
+        widget.set_size_request(self.hatari_wd, self.hatari_ht)
+        widget.set_events(gtk.gdk.ALL_EVENTS_MASK)
+        widget.set_flags(gtk.CAN_FOCUS)
+        self.hatariparent = widget
+        # TODO: when running 320x200, parent could be centered to here
+        vbox.add(widget)
+        # test focus
+        label = gtk.Label("Test SpinButton:")
+        vbox.add(label)
+        spin = gtk.SpinButton()
+        spin.set_range(0, 10)
+        spin.set_digits(0)
+        spin.set_numeric(True)
+        spin.set_increments(1, 2)
+        # otherwise Hatari doesn't receive keys!!!
+        spin.unset_flags(gtk.CAN_FOCUS)
+        vbox.add(spin)
+        parent.add(vbox)
+    
+    def timeout_cb(self):
+        self.do_hatari_method()
+        return False # only once
+    
+    def do_hatari_method(self):
+        pid = os.fork()
+        if pid < 0:
+            print "ERROR: fork()ing Hatari failed!"
+            return
+        if pid:
+            # in parent
+            if self.method == "reparent":
+                hatari_win = self.find_hatari_window()
+                if hatari_win:
+                    self.reparent_hatari_window(hatari_win)
+                    self.hatari_pid = pid
+                else:
+                    os.kill(pid, signal.SIGKILL)
+                    print "killed process with PID %d" % pid
+                    self.hatari_pid = 0
+            else:
+                # method == "sdl" or "hatari"
+                self.hatari_pid = pid
+        else:
+            # child runs Hatari
+            args = ("hatari", "-m", "-z", "2")
+            os.execvpe("hatari", args, self.get_hatari_env())
+
+    def get_hatari_env(self):
+        if self.method == "reparent":
+            return os.environ
+        # tell SDL to use (embed itself inside) given widget's window
+        win_id = self.hatariparent.window.xid
+        env = os.environ
+        if self.method == "sdl":
+            env["SDL_WINDOWID"] = str(win_id)
+        elif self.method == "hatari":
+            env["HATARI_PARENT_WIN"] = str(win_id)
+        return env
+    
+    def find_hatari_window(self):
+        # find hatari window by its WM class string and reparent it
+        cmd = """xwininfo -root -tree|awk '/"hatari" "hatari"/{print $1}'"""
+        counter = 0
+        while counter < 8:
+            pipe = os.popen(cmd)
+            windows = []
+            for line in pipe.readlines():
+                windows.append(int(line, 16))
+            try:
+                pipe.close()
+            except IOError:
+                # handle child process exiting silently
+                pass
+            if not windows:
+                counter += 1
+                print "WARNING: no Hatari window found yet, retrying..."
+                time.sleep(1)
+                continue
+            if len(windows) > 1:
+                print "WARNING: multiple Hatari windows, picking first one..."
+            return windows[0]
+        print "ERROR: no windows with the 'hatari' WM class found"
+        return None
+    
+    def reparent_hatari_window(self, hatari_win):
+        window = gtk.gdk.window_foreign_new(hatari_win)
+        if not window:
+            print "ERROR: Hatari window (ID: 0x%x) reparenting failed!" % hatari_win
+            return False
+        if not self.hatariparent.window:
+            print "ERROR: where hatariparent disappeared?"
+            return False
+        print "Found Hatari window ID: 0x%x, reparenting..." % hatari_win
+        print "...to container window ID: 0x%x" % self.hatariparent.window.xid
+        window.reparent(self.hatariparent.window, 0, 0)
+        #window.reparent(self.hatariparent.get_toplevel().window, 0, 0)
+        #window.reparent(self.hatariparent.get_root_window(), 0, 0)
+        #window.show()
+        #window.raise_()
+        # If python would destroy the Gtk widget when it goes out of scope,
+        # the foreign window widget destructor would delete Hatari window.
+        # So, keep a reference
+        #self.hatariwindow = window
+        return True
+
+    def run(self):
+        self.window.show_all()
+        gtk.main()
+
+
+if len(sys.argv) != 3:
+    usage("wrong number of arguments")
+app = AppUI(sys.argv[1], sys.argv[2])
+app.run()
diff --git a/python-ui/tests/pygtk-hello-world.py b/python-ui/tests/pygtk-hello-world.py
new file mode 100644
index 0000000..a238914
--- /dev/null
+++ b/python-ui/tests/pygtk-hello-world.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python
+
+import gtk
+
+class AppUI():
+    def __init__(self):
+        self.window = gtk.Window(gtk.WINDOW_TOPLEVEL)
+        self.window.connect("destroy", gtk.main_quit)
+        
+        label = gtk.Label("Hello World!")
+        self.window.add(label)
+        
+    def run(self):
+        self.window.show_all()
+        gtk.main()
+        
+app = AppUI()
+app.run()
diff --git a/python-ui/uihelpers.py b/python-ui/uihelpers.py
new file mode 100644
index 0000000..b37c8fc
--- /dev/null
+++ b/python-ui/uihelpers.py
@@ -0,0 +1,417 @@
+#!/usr/bin/env python
+#
+# Misc common helper classes and functions for the Hatari UI
+#
+# Copyright (C) 2008-2012 by Eero Tamminen
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+import os
+import sys
+# use correct version of pygtk/gtk
+import pygtk
+pygtk.require('2.0')
+import gtk
+import gobject
+
+
+# leak debugging
+#import gc
+#gc.set_debug(gc.DEBUG_UNCOLLECTABLE)
+
+
+# ---------------------
+# Hatari UI information
+
+class UInfo:
+    """singleton constants for the UI windows,
+    one instance is needed to initialize these properly"""
+    version = "v1.3"
+    name = "Hatari UI"
+    logo = "hatari-logo.png"
+    # TODO: use share/icons/hicolor/*/apps/hatari.png instead
+    icon = "hatari-icon.png"
+    copyright = "UI copyright (C) 2008-2015 by Eero Tamminen"
+
+    # path to the directory where the called script resides
+    path = os.path.dirname(sys.argv[0])
+    
+    def __init__(self, path = None):
+        "UIinfo([path]), set suitable paths for resources from CWD and path"
+        if path:
+            self.path = path
+        if not os.path.exists(UInfo.icon):
+            UInfo.icon = self._get_path(UInfo.icon)
+        if not os.path.exists(UInfo.logo):
+            UInfo.logo = self._get_path(UInfo.logo)
+
+    def _get_path(self, filename):
+        sep = os.path.sep
+        testpath = "%s%s%s" % (self.path, sep, filename)
+        if os.path.exists(testpath):
+            return testpath
+
+
+# --------------------------------------------------------
+# functions for showing HTML files
+
+class UIHelp:
+    def __init__(self):
+        """determine HTML viewer and where docs are"""
+        self._view = self.get_html_viewer()
+        self._path = self.get_doc_path()
+
+    def get_html_viewer(self):
+        """return name of html viewer or None"""
+        path = self.get_binary_path("xdg-open")
+        if path:
+            return path
+        path = self.get_binary_path("firefox")
+        if path:
+            return path
+        return None
+        
+    def get_binary_path(self, name):
+        """return true if given binary is in path"""
+        # could also try running the binary with "--version" arg
+        # and check the exec return value
+        if os.sys.platform == "win32":
+            splitter = ';'
+        else:
+            splitter = ':'
+        for i in os.environ['PATH'].split(splitter):
+                fname = os.path.join(i, name)
+                if os.access(fname, os.X_OK) and not os.path.isdir(fname):
+                    return fname
+        return None
+
+    def get_doc_path(self):
+        """return path or URL to Hatari docs or None"""
+        # first try whether there are local Hatari docs in standard place
+        # for this Hatari/UI version
+        sep = os.sep
+        path = self.get_binary_path("hatari")
+        path = sep.join(path.split(sep)[:-2]) # remove "bin/hatari"
+        path = path + sep + "share" + sep + "doc" + sep + "hatari" + sep
+        if os.path.exists(path + "manual.html"):
+            return path
+        # if not, point to latest Hatari HG version docs
+        print("WARNING: Hatari manual not found at:", path + "manual.html")
+        return "http://hg.tuxfamily.org/mercurialroot/hatari/hatari/raw-file/tip/doc/"
+
+    def set_mainwin(self, widget):
+        self.mainwin = widget
+
+    def view_url(self, url, name):
+        """view given URL or file path, or error use 'name' as its name"""
+        if self._view and "://" in url or os.path.exists(url):
+            print("RUN: '%s' '%s'" % (self._view, url))
+            os.spawnlp(os.P_NOWAIT, self._view, self._view, url)
+            return
+        if not self._view:
+            msg = "Cannot view %s, HTML viewer missing" % name
+        else:
+            msg = "Cannot view %s,\n'%s' file is missing" % (name, url)
+        from dialogs import ErrorDialog
+        ErrorDialog(self.mainwin).run(msg)
+
+    def view_hatari_manual(self, dummy=None):
+        self.view_url(self._path + "manual.html", "Hatari manual")
+
+    def view_hatari_compatibility(self, dummy=None):
+        self.view_url(self._path + "compatibility.html", "Hatari compatibility list")
+
+    def view_hatari_releasenotes(self, dummy=None):
+        self.view_url(self._path + "release-notes.txt", "Hatari release notes")
+
+    def view_hatari_todo(self, dummy=None):
+        self.view_url(self._path + "todo.txt", "Hatari TODO items")
+
+    def view_hatari_mails(self, dummy=None):
+        self.view_url("http://hatari.tuxfamily.org/contact.html", "Hatari mailing lists")
+
+    def view_hatari_repository(self, dummy=None):
+        self.view_url("http://hg.tuxfamily.org/mercurialroot/hatari/hatari", "latest Hatari changes")
+
+    def view_hatari_authors(self, dummy=None):
+        self.view_url(self._path + "authors.txt", "Hatari authors")
+
+    def view_hatari_page(self, dummy=None):
+        self.view_url("http://hatari.tuxfamily.org/", "Hatari home page")
+
+    def view_hatariui_page(self, dummy=None):
+        self.view_url("http://koti.mbnet.fi/tammat/hatari/hatari-ui.shtml", "Hatari UI home page")
+
+
+# --------------------------------------------------------
+# auxiliary class+callback to be used with the PasteDialog
+
+class HatariTextInsert:
+    def __init__(self, hatari, text):
+        self.index = 0
+        self.text = text
+        self.pressed = False
+        self.hatari = hatari
+        print("OUTPUT '%s'" % text)
+        gobject.timeout_add(100, _text_insert_cb, self)
+
+# callback to insert text object to Hatari character at the time
+# (first key down, on next call up), at given interval
+def _text_insert_cb(textobj):
+    char = textobj.text[textobj.index]
+    if char == ' ':
+        # white space gets stripped, use scancode instead
+        char = "57"
+    if textobj.pressed:
+        textobj.pressed = False
+        textobj.hatari.insert_event("keyup %s" % char)
+        textobj.index += 1
+        if textobj.index >= len(textobj.text):
+            del(textobj)
+            return False
+    else:
+        textobj.pressed = True
+        textobj.hatari.insert_event("keydown %s" % char)
+    # call again
+    return True
+
+
+# ----------------------------
+# helper functions for buttons
+
+def create_button(label, cb, data = None):
+    "create_button(label,cb[,data]) -> button widget"
+    button = gtk.Button(label)
+    if data == None:
+        button.connect("clicked", cb)
+    else:
+        button.connect("clicked", cb, data)
+    return button
+
+def create_toolbutton(stock_id, cb, data = None):
+    "create_toolbutton(stock_id,cb[,data]) -> toolbar button with stock icon+label"
+    button = gtk.ToolButton(stock_id)
+    if data == None:
+        button.connect("clicked", cb)
+    else:
+        button.connect("clicked", cb, data)
+    return button
+
+def create_toggle(label, cb, data = None):
+    "create_toggle(label,cb[,data]) -> toggle button widget"
+    button = gtk.ToggleButton(label)
+    if data == None:
+        button.connect("toggled", cb)
+    else:
+        button.connect("toggled", cb, data)
+    return button
+
+
+# -----------------------------
+# Table dialog helper functions
+
+def create_table_dialog(parent, title, rows, cols, oktext = gtk.STOCK_APPLY):
+    "create_table_dialog(parent,title,rows, cols, oktext) -> (table,dialog)"
+    dialog = gtk.Dialog(title, parent,
+        gtk.DIALOG_MODAL | gtk.DIALOG_DESTROY_WITH_PARENT,
+        (oktext,  gtk.RESPONSE_APPLY,
+        gtk.STOCK_CANCEL, gtk.RESPONSE_CANCEL))
+
+    table = gtk.Table(rows, cols)
+    table.set_data("col_offset", 0)
+    table.set_col_spacings(8)
+    dialog.vbox.add(table)
+    return (table, dialog)
+
+def table_set_col_offset(table, offset):
+    "set column offset for successive table_* ops on given table"
+    table.set_data("col_offset", offset)
+
+def table_add_entry_row(table, row, label, size = None):
+    "table_add_entry_row(table,row,label,[entry size]) -> entry"
+    # add given label to given row in given table
+    # return entry for that line
+    label = gtk.Label(label)
+    align = gtk.Alignment(1) # right aligned
+    align.add(label)
+    col = table.get_data("col_offset")
+    table.attach(align, col, col+1, row, row+1, gtk.FILL)
+    col += 1
+    if size:
+        entry = gtk.Entry(size)
+        entry.set_width_chars(size)
+        align = gtk.Alignment(0) # left aligned (default is centered)
+        align.add(entry)
+        table.attach(align, col, col+1, row, row+1)
+    else:
+        entry = gtk.Entry()
+        table.attach(entry, col, col+1, row, row+1)
+    return entry
+
+def table_add_widget_row(table, row, label, widget, fullspan = False):
+    "table_add_widget_row(table,row,label,widget) -> widget"
+    # add given label right aligned to given row in given table
+    # add given widget to the right column and returns it
+    # return entry for that line
+    if fullspan:
+        col = 0
+    else:
+        col = table.get_data("col_offset")
+    if label:
+        label = gtk.Label(label)
+        align = gtk.Alignment(1)
+        align.add(label)
+        table.attach(align, col, col+1, row, row+1, gtk.FILL)
+    if fullspan:
+        col = table.get_data("col_offset")
+        table.attach(widget, 1, col+2, row, row+1)
+    else:
+        table.attach(widget, col+1, col+2, row, row+1)
+    return widget
+
+def table_add_radio_rows(table, row, label, texts, cb = None):
+    "table_add_radio_rows(table,row,label,texts[,cb]) -> [radios]"
+    # - add given label right aligned to given row in given table
+    # - create/add radio buttons with given texts to next row, set
+    #   the one given as "active" as active and set 'cb' as their
+    #   "toggled" callback handler
+    # - return array or radiobuttons
+    label = gtk.Label(label)
+    align = gtk.Alignment(1)
+    align.add(label)
+    col = table.get_data("col_offset")
+    table.attach(align, col, col+1, row, row+1, gtk.FILL)
+
+    radios = []
+    radio = None
+    box = gtk.VBox()
+    for text in texts:
+        radio = gtk.RadioButton(radio, text)
+        if cb:
+            radio.connect("toggled", cb, text)
+        radios.append(radio)
+        box.add(radio)
+    table.attach(box, col+1, col+2, row, row+1)
+    return radios
+
+def table_add_separator(table, row):
+    "table_add_separator(table,row)"
+    widget = gtk.HSeparator()
+    endcol = table.get_data("n-columns")
+    # separator for whole table width
+    table.attach(widget, 0, endcol, row, row+1, gtk.FILL)
+
+
+# -----------------------------
+# File selection helpers
+
+def get_open_filename(title, parent, path = None):
+    buttons = (gtk.STOCK_OK, gtk.RESPONSE_OK, gtk.STOCK_CANCEL, gtk.RESPONSE_CANCEL)
+    fsel = gtk.FileChooserDialog(title, parent, gtk.FILE_CHOOSER_ACTION_OPEN, buttons)
+    fsel.set_local_only(True)
+    if path:
+        fsel.set_filename(path)
+    if fsel.run() == gtk.RESPONSE_OK:
+        filename = fsel.get_filename()
+    else:
+        filename = None
+    fsel.destroy()
+    return filename
+
+def get_save_filename(title, parent, path = None):
+    buttons = (gtk.STOCK_OK, gtk.RESPONSE_OK, gtk.STOCK_CANCEL, gtk.RESPONSE_CANCEL)
+    fsel = gtk.FileChooserDialog(title, parent, gtk.FILE_CHOOSER_ACTION_SAVE, buttons)
+    fsel.set_local_only(True)
+    fsel.set_do_overwrite_confirmation(True)
+    if path:
+        fsel.set_filename(path)
+        if not os.path.exists(path):
+            # above set only folder, this is needed to set
+            # the file name when the file doesn't exist
+            fsel.set_current_name(os.path.basename(path))
+    if fsel.run() == gtk.RESPONSE_OK:
+        filename = fsel.get_filename()
+    else:
+        filename = None
+    fsel.destroy()
+    return filename
+
+
+# File selection button with eject button
+class FselAndEjectFactory:
+    def __init__(self):
+        pass
+
+    def get(self, label, path, filename, action):
+        "returns file selection button and box having that + eject button"
+        fsel = gtk.FileChooserButton(label)
+        # Hatari cannot access URIs
+        fsel.set_local_only(True)
+        fsel.set_width_chars(12)
+        fsel.set_action(action)
+        if filename:
+            fsel.set_filename(filename)
+        elif path:
+            fsel.set_current_folder(path)
+        eject = create_button("Eject", self._eject, fsel)
+
+        box = gtk.HBox()
+        box.pack_start(fsel)
+        box.pack_start(eject, False, False)
+        return (fsel, box)
+
+    def _eject(self, widget, fsel):
+        fsel.unselect_all()
+
+
+# Gtk is braindead, there's no way to set a default filename
+# for file chooser button unless it already exists
+# - set_filename() works only for files that already exist
+# - set_current_name() works only for SAVE action,
+#   but file chooser button doesn't support that
+# i.e. I had to do my own (less nice) container widget...
+class FselEntry:
+    def __init__(self, parent, validate = None, data = None):
+        self._parent = parent
+        self._validate = validate
+        self._validate_data = data
+        entry = gtk.Entry()
+        entry.set_width_chars(12)
+        entry.set_editable(False)
+        hbox = gtk.HBox()
+        hbox.add(entry)
+        button = create_button("Select...", self._select_file_cb)
+        hbox.pack_start(button, False, False)
+        self._entry = entry
+        self._hbox = hbox
+    
+    def _select_file_cb(self, widget):
+        fname = self._entry.get_text()
+        while True:
+            fname = get_save_filename("Select file", self._parent, fname)
+            if not fname:
+                # assume cancel
+                return
+            if self._validate:
+                # filename needs validation and is valid?
+                if not self._validate(self._validate_data, fname):
+                    continue
+            self._entry.set_text(fname)
+            return
+    
+    def set_filename(self, fname):
+        self._entry.set_text(fname)
+        
+    def get_filename(self):
+        return self._entry.get_text()
+
+    def get_container(self):
+        return self._hbox
diff --git a/readme.txt b/readme.txt
new file mode 100644
index 0000000..890bb57
--- /dev/null
+++ b/readme.txt
@@ -0,0 +1,255 @@
+
+
+                                    Hatari
+
+                             Version 1.9, September 2015
+
+                          http://hatari.tuxfamily.org/
+
+
+Contents:
+---------
+1. License
+2. What is Hatari?
+3. Compiling and installing
+   3.1 WinUAE and "old" UAE CPU cores
+   3.2 IPF support using capsimage library
+   3.3 Notes for Linux distribution packagers
+       3.3.1 Known distro problems
+4. Running Hatari
+5. Contact
+
+
+ 1) License
+ ----------
+
+This program is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Soft-
+ware Foundation; either version 2 of the License, or (at your option) any
+later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along with
+this program; if not, write to the
+ Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston,
+ MA  02110-1301, USA
+
+Linking Hatari statically or dynamically with other modules is making a
+combined work based on Hatari. Thus, the terms and conditions of the GNU
+General Public License cover the whole combination.
+
+In addition, as a special exception, the copyright holders of Hatari give you
+permission to combine Hatari with free software programs or libraries that are
+released under the GNU LGPL and with code included in the standard release
+of the IPF support library (a.k.a. libcapsimage, see http://www.softpres.org/
+for more information) under the Software Preservation Society Licence Agreement
+as it has been defined for IPF library version 4.2 and 5.1. Linking against modified
+versions of the IPF library is also allowed, as long as neither the license
+nor the purpose of the library (accessing .ipf or .ctr disk images) was changed.
+You may copy and distribute such a system following the terms of the GNU GPL
+for Hatari and the licenses of the other code concerned.
+
+
+ 2) What is Hatari?
+ ------------------
+
+Hatari is an Atari ST/STE/TT/Falcon emulator for Linux, FreeBSD, NetBSD,
+BeOS, Mac-OSX and other Systems which are supported by the SDL library.
+Unlike most other open source ST emulators which try to give you a good
+environment for running GEM applications, Hatari tries to emulate the hardware
+as close as possible so that it is able to run most of the old Atari games
+and demos.  Because of this, it may be somewhat slower than less accurate
+emulators.
+
+
+ 3) Compiling and installing
+ ---------------------------
+
+For using Hatari, you need to have installed the following libraries:
+
+Required:
+- The SDL library v1.2.10 or newer (http://www.libsdl.org)
+- The zlib compression library (http://www.gzip.org/zlib/)
+
+Optional:
+- The PNG image library for PNG format screenshots and to decrease
+  AVI video recording file sizes (http://www.libpng.org/)
+- The GNU Readline library for Hatari debugger command line editing
+- The Xlib library to support Hatari Python UI window embedding on
+  systems with the X window system (Linux and other unixes) 
+- The portaudio library for Falcon microphone handling
+- The IPF support library (http://www.softpres.org/download)
+
+Don't forget to also install the header files of these libraries for compiling
+Hatari (some Linux distributions use separate development packages for these
+header files)!
+
+For compiling Hatari, you need a C compiler (preferably GNU C), and a working
+CMake (v2.8 or newer) installation, see http://www.cmake.org/ for details.
+
+CMake can generate makefiles for various flavours of "Make" (like GNU-Make)
+and various IDEs like Xcode on Mac OS X. To run CMake, you've got to pass the
+path to the sources of Hatari as parameter, for example run the following if
+you are in the topmost directory of the Hatari source tree:
+	cmake .
+
+If you're tracking Hatari version control, it's preferable to do
+the build in a separate build directory as above would overwrite
+the (non-CMake) Makefiles coming with Hatari:
+	mkdir -p build
+	cd build
+	cmake ..
+
+Have a look at the manual of CMake for other options. Alternatively, you can
+use the "cmake-gui" program to configure the sources with a graphical
+application or "ccmake" to configure them with ncurses UI.
+
+For your convenience we also ship an old-fashioned configure script which can
+be used as a wrapper for running cmake. Type "./configure --help" to see the
+options of this script.
+
+Assuming that you've used the Makefile generator of CMake, and cmake finished
+the configuration successfully, you can compile Hatari by typing "make". If all
+works fine, you'll get the executable "hatari" in the src/ subdirectory of the
+build tree. You can then install the emulator by typing "make install".
+
+
+ 3.1) WinUAE and "old" UAE CPU cores
+
+By default Hatari is built with the "old" UAE CPU core used in the
+earlier Hatari releases, but versions starting from v1.5 support also
+new & experimental WinUAE CPU core which offers more cycle accurate
+030 & DSP emulation and from v1.6 onwards also working 030 MMU
+emulation.
+
+The WinUAE CPU core can be enabled by toggling the ENABLE_WINUAE_CPU
+variable in the Hatari CMake configuration (e.g. with the interactive
+"ccmake" program).  Alternatively, you can run "./configure
+--enable-winuae-cpu", which will run cmake with the correct
+parameters.
+
+The plan is to eventually have WinUAE CPU core enabled by default and
+deprecate the "old" UAE CPU core, but currently WinUAE CPU core:
+- is lacking all the ST/STE specific tweaks and proper testing
+  for ST/STE compatibility
+- despite better emulation, it still doesn't run all the Falcon
+  programs that run with the "old" core although it works better
+  for most of them
+- doesn't have full debugger support
+
+It's recommended to use Hatari built with the "old" (default) UAE CPU
+core for ST/STE emulation and the new WinUAE core for Falcon emulation.
+And test also the old core if Falcon programs don't work with the new
+one...
+
+
+ 3.2) IPF support using capsimage library
+
+Hatari can use the optionnal capsimage library to access IPF and CTR
+files. Those files are created using the Kryoflux board and allow to
+record MFM exact copies of original games, including the protection.
+
+Version 4.2 of the library allows to access IPF files, while the more recent
+version 5.1 fixes some bugs, as well as adding support for CTR files.
+
+Since version 5.1 is not yet available for all OSes in binary form, Hatari
+still default to version 4.2 (but you can compile capsimage 5.1 sources
+to build your library). You can change this by modifying "SET(CAPSIMAGE_VERSION 4)"
+into cmake/FindCapsImage.cmake
+
+Refer to http://softpres.org/download and get the corresponding file
+from the "User Distribution" section that matches your OS.
+
+For version 4.2, you should have the following files in your include path :
+/usr/local/include/caps/
+	capsimage.h
+	fdc.h
+	form.h
+
+For version 5.1, you should have the following files in your include path :
+/usr/local/include/caps5/
+	CapsAPI.h
+	CapsFDC.h
+	CapsForm.h
+	CapsLibAll.h
+	CapsLib.h
+	CapsLibVersion.h
+	ComLib.h
+	CommonTypes.h
+
+You should also copy the libcapsimage.so* files in your library path,
+for example in /usr/local/lib/caps/ or /usr/local/lib/caps5/
+
+
+ 3.3) Notes for Linux distribution packagers
+
+TOS tester in tests/tosboot/ directory can be used to verify that
+Hatari was built fine enough that it's able to boot all tested TOS
+versions in various different HW configurations and run some GEMDOS
+based tests.  For EmuTOS, use version v0.8.7 or newer, older versions
+are buggy and fail the GEMDOS tests.
+
+If Hatari package will have two application menu entries for Hatari,
+one for the Python UI embedding Hatari, and another one for the plain
+SDL version, the latter could open also a terminal window for Hatari
+command line debugger and its console messages:
+x-terminal-emulator -T "Hatari debug window, invoke debugger with AltGr+Pause" -e hatari
+
+tools/hatari-tos-register.sh is a minimal example of Linux init script
+registering Hatari as a (binfmt_misc) handler for TOS binaries.
+
+Alternatively one could add a mime type for TOS binaries with xdg-mime:
+  http://portland.freedesktop.org/xdg-utils-1.0/xdg-mime.html
+But registering handlers for mime-types seems desktop specific.
+
+
+ 3.3.1) Known distro problems
+
+Old RHEL 5 and the derived CentOS v5.x Linux distributions ship
+with a broken readline library:
+	https://bugzilla.redhat.com/show_bug.cgi?id=499837
+
+To get CMake readline detection and linking working on them,
+you need to give these as extra arguments to the "cmake" command:
+   -DCMAKE_C_FLAGS=-lncurses -DCMAKE_EXE_LINKER_FLAGS=-lncurses
+
+They also have too old Python/PyGtk version for the python based
+Hatari scripts.  Here are patches for Hatari v1.5/v1.6 Python UI:
+http://listengine.tuxfamily.org/lists.tuxfamily.org/hatari-devel/2012/01/msg00008.html
+
+
+ 4) Running Hatari
+ -----------------
+
+For information about how to use the running emulator, please read the file
+doc/manual.html. Here are just some hints for the impatient people:
+
+* Before you can run the emulator, you need a TOS ROM image.  If one
+  named as "tos.img" is neither in the data directory of the emulator
+  (DATADIR variable in CMake configuration), or in the current
+  directory, Hatari will ask you to select one.
+
+  - Hatari binary packages ship unmodified EmuTOS ROM image with them
+    (renamed as tos.img), but you need an original Atari TOS ROM image
+    for best compatibility.  For more information on EmuTOS, see
+    doc/emutos.txt.
+
+* While the emulator is running, you can open the configuration menu
+  by pressing F12, the F11 key will toggle fullscreen/windowed mode.
+  Pressing ALTGR-q will quit the emulator.
+
+
+ 5) Contact
+ ----------
+
+If you want to contact the authors of Hatari, please have a look at the file
+doc/authors.txt for the e-mail addresses or use the Hatari mailing list.
+
+Visit the website of Hatari on Tuxfamily.org for more details:
+
+ http://hatari.tuxfamily.org/contact.html
+
diff --git a/share/CMakeLists.txt b/share/CMakeLists.txt
new file mode 100644
index 0000000..44a1437
--- /dev/null
+++ b/share/CMakeLists.txt
@@ -0,0 +1,25 @@
+
+foreach(size 32x32 48x48 64x64 128x128 256x256)
+	install(FILES icons/hicolor/${size}/apps/hatari.png
+		DESTINATION ${ICONDIR}/${size}/apps)
+	install(FILES icons/hicolor/${size}/mimetypes/application-x-st-disk-image.png
+		DESTINATION ${ICONDIR}/${size}/mimetypes)
+	foreach(type vnd.msa vnd.fastcopy x-stx)
+		install(CODE "execute_process(COMMAND ln -sf application-x-st-disk-image.png
+				${CMAKE_INSTALL_PREFIX}/${ICONDIR}/${size}/mimetypes/application-${type}-disk-image.png)
+				")
+	endforeach()
+endforeach()
+
+install(FILES icons/hicolor/scalable/apps/hatari.svg
+	DESTINATION ${ICONDIR}/scalable/apps)
+install(FILES icons/hicolor/scalable/mimetypes/application-x-st-disk-image.svg
+	DESTINATION ${ICONDIR}/scalable/mimetypes)
+foreach(type vnd.msa vnd.fastcopy x-stx)
+	install(CODE "execute_process(COMMAND ln -sf application-x-st-disk-image.svg
+			${CMAKE_INSTALL_PREFIX}/${ICONDIR}/scalable/mimetypes/application-${type}-disk-image.svg)
+			")
+endforeach()
+install(FILES mime/packages/hatari.xml DESTINATION share/mime/packages)
+
+install(FILES applications/hatari.desktop DESTINATION share/applications)
diff --git a/share/applications/hatari.desktop b/share/applications/hatari.desktop
new file mode 100644
index 0000000..d13b3a5
--- /dev/null
+++ b/share/applications/hatari.desktop
@@ -0,0 +1,11 @@
+[Desktop Entry]
+Version=1.0
+Type=Application
+Name=Hatari
+GenericName=ST emulator
+Comment=Run old ST/STE/TT/Falcon software
+Exec=hatari %f
+Icon=hatari
+MimeType=application/x-st-disk-image;application/vnd.msa-disk-image;application/vnd.fastcopy-disk-image;application/x-stx-disk-image
+Categories=Game;Emulator;
+Terminal=false
diff --git a/share/icons/hicolor/128x128/apps/hatari.png b/share/icons/hicolor/128x128/apps/hatari.png
new file mode 100644
index 0000000..7f5f42e
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diff --git a/share/icons/hicolor/128x128/mimetypes/application-x-st-disk-image.png b/share/icons/hicolor/128x128/mimetypes/application-x-st-disk-image.png
new file mode 100644
index 0000000..c4474a1
Binary files /dev/null and b/share/icons/hicolor/128x128/mimetypes/application-x-st-disk-image.png differ
diff --git a/share/icons/hicolor/256x256/apps/hatari.png b/share/icons/hicolor/256x256/apps/hatari.png
new file mode 100644
index 0000000..dc1a65d
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diff --git a/share/icons/hicolor/256x256/mimetypes/application-x-st-disk-image.png b/share/icons/hicolor/256x256/mimetypes/application-x-st-disk-image.png
new file mode 100644
index 0000000..ccea972
Binary files /dev/null and b/share/icons/hicolor/256x256/mimetypes/application-x-st-disk-image.png differ
diff --git a/share/icons/hicolor/32x32/apps/hatari.png b/share/icons/hicolor/32x32/apps/hatari.png
new file mode 100644
index 0000000..be748ce
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diff --git a/share/icons/hicolor/32x32/mimetypes/application-x-st-disk-image.png b/share/icons/hicolor/32x32/mimetypes/application-x-st-disk-image.png
new file mode 100644
index 0000000..0ccfa1d
Binary files /dev/null and b/share/icons/hicolor/32x32/mimetypes/application-x-st-disk-image.png differ
diff --git a/share/icons/hicolor/48x48/apps/hatari.png b/share/icons/hicolor/48x48/apps/hatari.png
new file mode 100644
index 0000000..b6b7910
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diff --git a/share/icons/hicolor/48x48/mimetypes/application-x-st-disk-image.png b/share/icons/hicolor/48x48/mimetypes/application-x-st-disk-image.png
new file mode 100644
index 0000000..e37ff3a
Binary files /dev/null and b/share/icons/hicolor/48x48/mimetypes/application-x-st-disk-image.png differ
diff --git a/share/icons/hicolor/64x64/apps/hatari.png b/share/icons/hicolor/64x64/apps/hatari.png
new file mode 100644
index 0000000..b05d54c
Binary files /dev/null and b/share/icons/hicolor/64x64/apps/hatari.png differ
diff --git a/share/icons/hicolor/64x64/mimetypes/application-x-st-disk-image.png b/share/icons/hicolor/64x64/mimetypes/application-x-st-disk-image.png
new file mode 100644
index 0000000..179af26
Binary files /dev/null and b/share/icons/hicolor/64x64/mimetypes/application-x-st-disk-image.png differ
diff --git a/share/icons/hicolor/scalable/apps/hatari.svg b/share/icons/hicolor/scalable/apps/hatari.svg
new file mode 100644
index 0000000..35f6ce7
--- /dev/null
+++ b/share/icons/hicolor/scalable/apps/hatari.svg
@@ -0,0 +1,16 @@
+
+  
+    
+      
+        image/svg+xml
+        
+      
+    
+  
+  
+  
+  
+  
+  
+  
+
diff --git a/share/icons/hicolor/scalable/mimetypes/application-x-st-disk-image.svg b/share/icons/hicolor/scalable/mimetypes/application-x-st-disk-image.svg
new file mode 100644
index 0000000..c183cd3
--- /dev/null
+++ b/share/icons/hicolor/scalable/mimetypes/application-x-st-disk-image.svg
@@ -0,0 +1,63 @@
+
+  
+    
+      
+        image/svg+xml
+        
+        
+      
+    
+  
+  
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+    
+    
+    
+    
+    
+    
+    
+    
+  
+  
+  
+  
+  
+  
+  
+  
+  
+
diff --git a/share/mime/packages/hatari.xml b/share/mime/packages/hatari.xml
new file mode 100644
index 0000000..947782d
--- /dev/null
+++ b/share/mime/packages/hatari.xml
@@ -0,0 +1,32 @@
+
+
+	
+		
+		ST disk image
+		
+	
+	
+		
+		Magic Shadow Archiver disk image
+		
+		
+			
+		
+	
+	
+		
+		FastCopy DIM disk image
+		
+		
+			
+		
+	
+	
+		
+		Pasti STX disk image
+		
+		
+			
+		
+	
+
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
new file mode 100644
index 0000000..d31d831
--- /dev/null
+++ b/src/CMakeLists.txt
@@ -0,0 +1,165 @@
+
+set(SOURCES
+	acia.c audio.c avi_record.c bios.c blitter.c cart.c cfgopts.c
+	clocks_timings.c configuration.c options.c change.c
+	control.c cycInt.c cycles.c dialog.c dmaSnd.c fdc.c file.c
+	floppy.c floppy_ipf.c floppy_stx gemdos.c hd6301_cpu.c hdc.c ide.c ikbd.c ioMem.c
+	ioMemTabST.c ioMemTabSTE.c ioMemTabTT.c ioMemTabFalcon.c joy.c
+	keymap.c m68000.c main.c midi.c memorySnapShot.c mfp.c
+	paths.c  psg.c printer.c resolution.c rs232.c reset.c rtc.c
+	scandir.c stMemory.c screen.c screenSnapShot.c shortcut.c sound.c
+	spec512.c statusbar.c str.c tos.c unzip.c utils.c vdi.c
+	video.c wavFormat.c xbios.c ymFormat.c)
+
+# Disk image code is shared with the hmsa tool, so we put it into a library:
+add_library(Floppy createBlankImage.c dim.c msa.c st.c zip.c)
+
+# When building for OSX, define specific sources for gui and ressources
+if(ENABLE_OSX_BUNDLE)
+	set(GUIOSX_SOURCES
+	    gui-osx/AlertHooks.m gui-osx/PrefsController.m gui-osx/Shared.m
+	    gui-osx/CreateFloppyController.m gui-osx/SDLMain.m)
+	set_source_files_properties(${GUIOSX_SOURCES} PROPERTIES LANGUAGE C)
+	set(GUIOSX_RSRCS
+	    gui-osx/Hatari.icns gui-osx/English.lproj gui-osx/French.lproj)
+	set(GUIOSX_DOCS
+	    ${CMAKE_SOURCE_DIR}/doc/manual.html ${CMAKE_SOURCE_DIR}/doc/images
+	    ${CMAKE_SOURCE_DIR}/doc/compatibility.html)
+endif(ENABLE_OSX_BUNDLE)
+
+# When building for Windows, define specific sources for gui and resources
+# and set the subsystem of the resulting .exe to "windows GUI" instead of "console"
+if(WIN32)
+	set(GUIWIN_SOURCES gui-win/opencon.c)
+	set(GUIWIN_RES gui-win/hatari-winicon.rc)
+	set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -mwindows")
+endif(WIN32)
+
+if(ENABLE_WINUAE_CPU)
+	set(CPUDIR cpu)
+else()
+	set(CPUDIR uae-cpu)
+endif(ENABLE_WINUAE_CPU)
+
+include_directories(${CMAKE_BINARY_DIR} ${SDL_INCLUDE_DIR} ${CPUDIR}
+		    includes debug falcon)
+
+if(ZLIB_FOUND)
+	include_directories(${ZLIB_INCLUDE_DIR})
+endif(ZLIB_FOUND)
+
+if(PNG_FOUND)
+	include_directories(${PNG_INCLUDE_DIR})
+endif(PNG_FOUND)
+
+if(X11_FOUND)
+	include_directories(${X11_INCLUDE_DIR})
+endif(X11_FOUND)
+
+
+link_directories(${CMAKE_CURRENT_BINARY_DIR}/debug
+		 ${CMAKE_CURRENT_BINARY_DIR}/falcon
+		 ${CMAKE_CURRENT_BINARY_DIR}/gui-sdl
+		 ${CMAKE_CURRENT_BINARY_DIR}/${CPUDIR})
+
+add_subdirectory(debug)
+add_subdirectory(falcon)
+add_subdirectory(gui-sdl)
+add_subdirectory(${CPUDIR})
+
+# When building for OSX, add specific sources
+if(ENABLE_OSX_BUNDLE)
+	add_executable(hatari MACOSX_BUNDLE ${GUIOSX_RSRCS} ${GUIOSX_DOCS} ${SOURCES} ${GUIOSX_SOURCES})
+	set_target_properties(hatari PROPERTIES MACOSX_BUNDLE_INFO_PLIST
+			      ${CMAKE_CURRENT_SOURCE_DIR}/gui-osx/Info-Hatari.plist)
+	set(MACOSX_BUNDLE_ICON_FILE Hatari.icns)
+	if(CMAKE_GENERATOR MATCHES "Xcode")
+		set(BUNDLE_CONTENTS ${CMAKE_CURRENT_BINARY_DIR}/\${CONFIGURATION}/Hatari.app/Contents)
+	else()
+		set(BUNDLE_CONTENTS ${CMAKE_CURRENT_BINARY_DIR}/Hatari.app/Contents)
+	endif()
+	# Create Hatari.app bundle
+	add_custom_target(osx_bundle_dirs
+			COMMAND mkdir -p ${BUNDLE_CONTENTS}/Resources
+			COMMAND mkdir -p ${BUNDLE_CONTENTS}/MacOS
+			COMMAND cp ${CMAKE_CURRENT_SOURCE_DIR}/gui-osx/${MACOSX_BUNDLE_ICON_FILE}
+				   ${BUNDLE_CONTENTS}/Resources/${MACOSX_BUNDLE_ICON_FILE}
+			# Copy Localized .nib to Bundle
+			COMMAND cp -R ${CMAKE_CURRENT_SOURCE_DIR}/gui-osx/*.lproj ${BUNDLE_CONTENTS}/Resources/
+			COMMAND mkdir -p ${BUNDLE_CONTENTS}/Resources/English.lproj/HatariHelp
+			COMMAND cp -R ${GUIOSX_DOCS} ${BUNDLE_CONTENTS}/Resources/English.lproj/HatariHelp/
+			COMMAND mkdir -p ${BUNDLE_CONTENTS}/Resources/French.lproj/HatariHelp
+			COMMAND cp -R ${GUIOSX_DOCS} ${BUNDLE_CONTENTS}/Resources/French.lproj/HatariHelp/
+	)
+	add_dependencies(hatari osx_bundle_dirs)
+	set_source_files_properties(${GUIOSX_RSRCS} PROPERTIES
+				    MACOSX_PACKAGE_LOCATION Resources)
+	set_source_files_properties(${GUIOSX_DOCS} PROPERTIES
+				    MACOSX_PACKAGE_LOCATION Resources/English.lproj/HatariHelp)
+
+# When building for Windows, add specific sources + method to compile .rc files
+elseif(WIN32)
+	# Set a default rc compiler if it was not defined yet
+	if(NOT CMAKE_RC_COMPILER)
+		set(CMAKE_RC_COMPILER windres)
+	endif(NOT CMAKE_RC_COMPILER)
+	ENABLE_LANGUAGE(RC)
+	set(CMAKE_RC_COMPILE_OBJECT " -Ocoff -o  ")
+	set_source_files_properties(${GUIWIN_RES} PROPERTIES LANGUAGE RC)
+	add_executable(hatari ${GUIWIN_RES} ${SOURCES} ${GUIWIN_SOURCES})
+
+# Other targets, use default sources
+else()
+	add_executable(hatari ${SOURCES})
+endif(ENABLE_OSX_BUNDLE)
+
+target_link_libraries(hatari Falcon UaeCpu GuiSdl Floppy Debug ${SDL_LIBRARY})
+
+if(MATH_FOUND AND NOT APPLE)
+	target_link_libraries(hatari ${MATH_LIBRARY})
+endif()
+
+if(SDLMAIN_LIBRARY)
+	target_link_libraries(hatari ${SDLMAIN_LIBRARY})
+endif(SDLMAIN_LIBRARY)
+
+if(READLINE_FOUND)
+	target_link_libraries(hatari ${READLINE_LIBRARY})
+endif(READLINE_FOUND)
+
+if(ZLIB_FOUND)
+	target_link_libraries(hatari ${ZLIB_LIBRARY})
+endif(ZLIB_FOUND)
+
+if(PNG_FOUND)
+	target_link_libraries(hatari ${PNG_LIBRARY})
+endif(PNG_FOUND)
+
+if(X11_FOUND)
+	target_link_libraries(hatari ${X11_LIBRARIES})
+endif(X11_FOUND)
+
+if(PORTAUDIO_FOUND)
+	target_link_libraries(hatari ${PORTAUDIO_LIBRARY})
+endif(PORTAUDIO_FOUND)
+
+if(CAPSIMAGE_FOUND)
+	target_link_libraries(hatari ${CAPSIMAGE_LIBRARY})
+endif(CAPSIMAGE_FOUND)
+
+if(WIN32)
+	# Needed for socket() on Windows
+	target_link_libraries(hatari ws2_32)
+endif(WIN32)
+
+
+if(ENABLE_OSX_BUNDLE)
+	install(TARGETS hatari BUNDLE DESTINATION /Applications)
+else()
+	install(TARGETS hatari RUNTIME DESTINATION ${BINDIR})
+	install(FILES hatari-icon.bmp DESTINATION ${DATADIR})
+	file(GLOB TOS_IMG_FILE tos.img)
+	if(TOS_IMG_FILE)
+		install(FILES tos.img DESTINATION ${DATADIR})
+	endif(TOS_IMG_FILE)
+endif(ENABLE_OSX_BUNDLE)
diff --git a/src/Makefile.dep b/src/Makefile.dep
new file mode 100644
index 0000000..e69de29
diff --git a/src/Makefile.wii b/src/Makefile.wii
new file mode 100755
index 0000000..22f394f
--- /dev/null
+++ b/src/Makefile.wii
@@ -0,0 +1,113 @@
+# Main Makefile for Hatari.
+
+# Use "export ENABLE_DSP_EMU=0" & "make clean"
+# to disable experimental DSP emulation code.
+ENABLE_DSP_EMU ?= 0
+
+# Select CPU directory:
+CPUDIR = uae-cpu
+
+# Include settings
+include ../Makefile-wii.cnf
+
+# Additional include directories:
+CPPFLAGS += $(CFLAGS) -I.. -I./includes -I$(CPUDIR) -I./debug -I./falcon 
+
+ifeq ($(ENABLE_DSP_EMU),1)
+CPPFLAGS += -DENABLE_DSP_EMU=1
+endif
+
+GUIOBJS = ./gui-sdl/dlgAbout.o ./gui-sdl/dlgAlert.o ./gui-sdl/dlgDevice.o \
+  ./gui-sdl/dlgJoystick.o ./gui-sdl/dlgKeyboard.o ./gui-sdl/dlgWiiMapper.o \
+  ./gui-sdl/dlgMain.o ./gui-sdl/dlgMemory.o ./gui-sdl/dlgNewDisk.o \
+  ./gui-sdl/dlgRom.o ./gui-sdl/dlgScreen.o ./gui-sdl/dlgSound.o  \
+  ./gui-sdl/dlgSystem.o ./gui-sdl/dlgFileSelect.o ./gui-sdl/sdlgui.o
+
+GUIWINOBJS = ./gui-win/hatari-winicon.o ./gui-win/opencon.o
+
+SRCS = acia.c audio.c avi_record.c bios.c blitter.c cart.c cfgopts.c \
+  clocks_timings.c configuration.c options.c  createBlankImage.c change.c control.c \
+  cycInt.c cycles.c dialog.c dim.c dmaSnd.c fdc.c file.c floppy.c  floppy_ipf.c floppy_stx.c  \
+  gemdos.c hd6301_cpu.c hdc.c ide.c ikbd.c ioMem.c ioMemTabST.c \
+  ioMemTabSTE.c ioMemTabTT.c ioMemTabFalcon.c joy.c keymap.c m68000.c \
+  main.c midi.c memorySnapShot.c mfp.c msa.c paths.c  psg.c printer.c \
+  resolution.c rs232.c reset.c rtc.c scandir.c st.c stMemory.c screen.c \
+  screenSnapShot.c shortcut.c sound.c spec512.c statusbar.c str.c tos.c \
+  unzip.c utils.c vdi.c video.c wavFormat.c xbios.c ymFormat.c zip.c keyboard.c snap_empty.c
+
+OBJS = $(SRCS:.c=.o)
+
+
+ALLOBJS = $(OBJS) $(GUIOBJS) $(CPUDIR)/cpu68k.a debug/debug.a falcon/falcon.a gui-sdl/gui-sdl.a
+
+ifeq ($(SYS_WINDOWS),1)
+  ALLOBJS += $(GUIWINOBJS)
+else
+ifneq ($(strip $(shell gcc -v 2>&1 |grep "cygwin")),)
+  ALLOBJS += $(GUIWINOBJS)
+endif 
+endif
+
+
+all: hatari.dol
+
+hatari: $(ALLOBJS)
+	$(CC) $(LDFLAGS) $(ALLOBJS) $(SDL_LIBS) $(LIBS) -o hatari
+
+hatari.dol : $(ALLOBJS)
+	$(CC) $(LDFLAGS) $(ALLOBJS) $(SDL_LIBS) $(LIBS) -o hatari.elf
+	elf2dol hatari.elf hatari.dol
+
+run:
+	wiiload hatari.dol
+
+# Sub-folder dependencies:
+.PHONY : $(CPUDIR)/cpu68k.a
+$(CPUDIR)/cpu68k.a:
+	$(MAKE) -C $(CPUDIR)
+
+gui-sdl/%.o: gui-sdl/%.c
+	$(MAKE) ENABLE_DSP_EMU=$(ENABLE_DSP_EMU) -C gui-sdl/ all
+
+gui-win/%.o:
+	$(MAKE) ENABLE_DSP_EMU=$(ENABLE_DSP_EMU) -C gui-win/ all
+
+debug/debug.a:
+	$(MAKE) -C debug
+
+falcon/falcon.a:
+	$(MAKE) -C falcon
+
+clean:
+	$(RM) *.o hatari
+	$(RM) *.o hatari.elf hatari.dol
+	$(MAKE) -C gui-sdl/ clean
+	#$(MAKE) -C gui-win/ clean
+	$(MAKE) -C $(CPUDIR) clean
+	$(MAKE) -C debug/ clean
+	$(MAKE) -C falcon/ clean
+
+distclean:
+	$(RM) *.o hatari
+	$(RM) Makefile.dep *~ *.bak *.orig
+	$(RM) convert/*~ convert/*.bak
+	$(MAKE) -C gui-sdl/ distclean
+	#$(MAKE) -C gui-win/ distclean
+	$(MAKE) -C $(CPUDIR) distclean
+	$(MAKE) -C debug/ distclean
+	$(MAKE) -C falcon/ distclean
+
+# Use "make depend" to generate file dependencies:
+Makefile.dep: Makefile
+	$(CC) -M $(CPPFLAGS) $(SRCS) > Makefile.dep
+
+depend: cleandeps Makefile.dep
+	$(MAKE) -C gui-sdl/ depend
+	$(MAKE) -C $(CPUDIR) depend
+	$(MAKE) -C falcon/ depend
+	$(MAKE) -C debug/ depend
+
+cleandeps:
+	$(RM) Makefile.dep */Makefile.dep
+
+-include Makefile.dep
diff --git a/src/acia.c b/src/acia.c
new file mode 100644
index 0000000..c3c0b0b
--- /dev/null
+++ b/src/acia.c
@@ -0,0 +1,1122 @@
+/*
+  Hatari - acia.c
+
+  Copyright (C) 2012 by Nicolas Pomarède
+
+  This file is distributed under the GNU Public License, version 2 or at
+  your option any later version. Read the file gpl.txt for details.
+
+  MC6850 ACIA emulation.
+*/
+
+const char ACIA_fileid[] = "Hatari acia.c : " __DATE__ " " __TIME__;
+
+
+/* 2012/09/28	[NP]	Start of the full rewrite of the MC6850 ACIA emulation, using the official	*/
+/*			datasheets for maximum accuracy, as well as bit level serial transfers (start,	*/
+/*			stop and parity bits).								*/
+/* 2012/12/21	[NP]	Add accurate cycles delays when accessing an ACIA register, taking E Clock	*/
+/*			into account.									*/
+/* 2013/04/24	[NP]	Remove INTERRUPT_ACIA_MFP used to add a 4 cycle delay when IRQ is set, as this	*/
+/*			delay is now correctly handled directly in the MFP since 2013/03/01.		*/
+
+
+
+
+/*
+  6850 ACIA (Asynchronous Communications Inferface Apdater)
+
+  References :
+   - MC6850 datasheet by Motorola (DS9493R4, 1985)
+   - A6850 datasheet by Altera (A-DS-A6850-01, 1996) (nearly identical component)
+
+  Others references :
+   - MAME's 6850acia.c for RTS, CTS and DCD behaviour
+
+
+  Pins :
+    Vss
+    RX DATA Receive Data
+    RX CLK Receive Clock
+    TX CLK Transmitter Clock
+    RTS Request To Send
+    TX DATA Transmitter Data
+    IRQ Interrupt Request
+    CS 0,1,2 Chip Select
+    RS Register Select
+    Vcc Voltage
+    R/W Read/Write
+    E Enable
+    D0-D7 Data
+    DCD Data Carrier Detect
+    CTS Clear To Send
+
+  Registers :
+    0xfffc00 Keyboard ACIA Control (write)/Status(read)
+    0xfffc02 Keyboard ACIA Data
+    0xfffc04 MIDI ACIA Control (write)/Status(read)
+    0xfffc06 MIDI ACIA Data
+
+  Control Register (0xfffc00 write) :
+    Bits 0,1 - These bits determine by which factor the transmitter and receiver
+      clock will be divided. These bits also are joined with a master reset
+      function. The 6850 has no separate reset line, so it must be
+      accomplished though software.
+        0 0    RXCLK/TXCLK without division
+        0 1    RXCLK/TXCLK by 16 (MIDI)
+        1 0    RXCLK/TXCLK by 64 (Keyboard)
+        1 1    Master RESET
+    Bits 2,3,4 - These so-called Word Select bits tell whether 7 or 8 data-bits are
+      involved; whether 1 or 2 stop-bits are transferred; and the type of parity
+    Bits 5,6 - These Transmitter Control bits set the RTS output pin, and allow or prevent
+      an interrupt through the ACIA when the send register is emptied. Also, BREAK signals
+      can be sent over the serial output by this line. A BREAK signal is nothing more than
+      a long seqence of null bits
+        0 0    RTS low, transmitter IRQ disabled
+        0 1    RTS low, transmitter IRQ enabled
+        1 0    RTS high, transmitter IRQ disabled
+        1 1    RTS low, transmitter IRQ disabled, BREAK sent
+    Bit 7 - The Receiver Interrupt Enable bit determines whether the receiver interrupt
+      will be on. An interrupt can be caused by the DCD line chaning from low to high, or
+      by the receiver data buffer filling. Besides that, an interrupt can occur from an
+      OVERRUN (a received character isn't properly read from the processor).
+        0 Interrupt disabled
+        1 Interrupt enabled
+
+  Status Register (0xfffc00 read) :
+    Bit 0 - When this bit is high, the RX data register is full. The byte must be read
+      before a new character is received (otherwise an OVERRUN happens)
+    Bit 1 - This bit reflects the status of the TX data buffer. An empty register
+      set the bit.
+    Bit 2 - A low-high change in pin DCD sets bit 2. If the receiver interrupt is allowable, the IRQ
+      is cancelled. The bit is cleared when the status register and the receiver register are
+      read. This also cancels the IRQ. Bit 2 register remains highis the signal on the DCD pin
+      is still high; Bit 2 register low if DCD becomes low.
+    Bit 3 - This line shows the status of CTS. This signal cannot be altered by a mater reset,
+      or by ACIA programming.
+    Bit 4 - Shows 'Frame Errors'. Frame errors are when no stop-bit is recognized in receiver
+      switching. It can be set with every new character.
+    Bit 5 - This bit display the previously mentioned OVERRUN condition. Bit 5 is reset when the
+      RX buffer is read.
+    Bit 6 - This bit recognizes whether the parity of a received character is correct. The bit is
+      set on an error.
+    Bit 7 - This signals the state of the IRQ pins; this bit make it possible to switch several
+      IRQ lines on one interrupt input. In cases where an interrupt is program-generated, bit 7
+      can tell which IC cut off the interrupt.
+
+  ST ACIA :
+    CTS,DCD and RTS are not connected
+    The keyboard ACIA addresses are 0xfffc000 and 0xfffc02.
+    The MIDI ACIA addresses are 0xfffc004 and 0xfffc06.
+    Default keyboard parameters are : 8-bit word, 1 stopbit, no parity, 7812.5 baud; 500KHz/64 (keyboard clock div)
+    Default MIDI parameters are as above but : 31250 baud; 500KHz/16 (MIDI clock div)
+
+
+  CPU cycles in the ST :
+    When accessing an ACIA register, an additional delay will be added to the usual number of
+    cycles for this CPU instruction. This delay is made of 2 parts (for a 68000 at 8 MHz) :
+	- a fixed delay of 6 cycles.
+	- a variable delay of 0 to 8 cycles to synchronise with the E Clock.
+
+    Examples for some common instructions measured on a real 520 STF
+    (with a0=$fffffc00 and 'n' the delay for E Clock) :
+	move.b  (a0),d2 : 14 cycles = 8 + 6 + n
+	move.w  (a0),d2 : 14 cycles = 8 + 6 + n
+	move.l  (a0),d2 : 24 cycles = 12 + 6 + 6 + n
+	movep.w (a0),d2 : 28 cycles = 16 + 6 + 6 + n
+	movep.l (a0),d2 : 48 cycles = 24 + 6 + 6 + 6 + 6 + n
+    (on ST, those values might be rounded to the next multiple of 4 cycles)
+
+    When the ACIA's IRQ signal goes low, the resulting bit in the MFP is visible to the CPU only 4 cycles later.
+    From the hardware point of view, the ACIA's irq signal is immediately propagated to the MFP,
+    but the MFP will then add a 4 cycle delay before generating a 68000 interrupt.
+
+*/
+
+/*-----------------------------------------------------------------------*/
+
+
+#include "main.h"
+#include "log.h"
+#include "memorySnapShot.h"
+#include "configuration.h"
+#include "acia.h"
+#include "m68000.h"
+#include "cycInt.h"
+#include "ioMem.h"
+#include "clocks_timings.h"
+#include "mfp.h"
+#include "screen.h"
+#include "video.h"
+
+
+#define	ACIA_SR_BIT_RDRF			0x01		/* Receive Data Register Full */
+#define	ACIA_SR_BIT_TDRE			0x02		/* Transmit Data Register Empty */
+#define	ACIA_SR_BIT_DCD				0x04		/* Data Carrier Detect */
+#define	ACIA_SR_BIT_CTS				0x08		/* Clear To Send */
+#define	ACIA_SR_BIT_FE				0x10		/* Framing Error */
+#define	ACIA_SR_BIT_OVRN			0x20		/* Receiver Overrun */
+#define	ACIA_SR_BIT_PE				0x40		/* Parity Error */
+#define	ACIA_SR_BIT_IRQ				0x80		/* IRQ */
+
+#define	ACIA_CR_COUNTER_DIVIDE( CR )		( CR & 0x03 )		/* CR1 + CR0 : 0x03 causes a master reset */
+#define	ACIA_CR_WORD_SELECT( CR )		( ( CR >> 2 ) & 0x07 )	/* CR4 + CR3 + CR2 : size, parity, stop bits */
+#define	ACIA_CR_TRANSMITTER_CONTROL( CR )	( ( CR >> 5 ) & 0x03 )	/* CR6 + CR5 : RTS + IRQ on send */
+#define	ACIA_CR_RECEIVE_INTERRUPT_ENABLE( CR )	( ( CR >> 7 ) & 0x01 )	/* CR7 : Receive interrupt enable */
+
+
+static const int ACIA_Counter_Divide[3] = { 1 , 16 , 64 };	/* Used to divide txclock/rxclock to get the correct baud rate */
+
+
+/* Data size, parity and stop bits used for the transfer depending on CR_WORD_SELECT */
+enum
+{
+	ACIA_PARITY_NONE ,
+	ACIA_PARITY_EVEN ,
+	ACIA_PARITY_ODD
+};
+
+
+static struct {
+	int	DataBits;						/* 7 or 8 */
+	int	Parity;							/* EVEN or ODD or NONE */
+	int	StopBits;						/* 1 or 2 */
+} ACIA_Serial_Params [ 8 ] = {
+  { 7 , ACIA_PARITY_EVEN , 2 },
+  { 7 , ACIA_PARITY_ODD ,  2 },
+  { 7 , ACIA_PARITY_EVEN , 1 },
+  { 7 , ACIA_PARITY_ODD ,  1 },
+  { 8 , ACIA_PARITY_NONE , 2 },
+  { 8 , ACIA_PARITY_NONE , 1 },
+  { 8 , ACIA_PARITY_EVEN , 1 },
+  { 8 , ACIA_PARITY_ODD ,  1 }
+};
+
+
+
+/* Possible states when handling TX/RX interrupts */
+enum
+{
+	ACIA_STATE_IDLE = 0,
+	ACIA_STATE_DATA_BIT,
+	ACIA_STATE_PARITY_BIT,
+	ACIA_STATE_STOP_BIT
+};
+
+
+ACIA_STRUCT		ACIA_Array[ ACIA_MAX_NB ];
+ACIA_STRUCT		*pACIA_IKBD;
+ACIA_STRUCT		*pACIA_MIDI;
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Local functions prototypes					*/
+/*--------------------------------------------------------------*/
+
+static void		ACIA_Init_Pointers ( ACIA_STRUCT *pAllACIA );
+
+static void		ACIA_Set_Line_IRQ_MFP ( int bit );
+static Uint8 		ACIA_Get_Line_CTS_Dummy ( void );
+static Uint8 		ACIA_Get_Line_DCD_Dummy ( void );
+static void		ACIA_Set_Line_RTS_Dummy ( int bit );
+
+static void		ACIA_Set_Timers_IKBD ( void *pACIA );
+static void		ACIA_Start_InterruptHandler_IKBD ( ACIA_STRUCT *pACIA , int InternalCycleOffset );
+
+static Uint8		ACIA_MasterReset ( ACIA_STRUCT *pACIA , Uint8 CR );
+
+static void		ACIA_UpdateIRQ ( ACIA_STRUCT *pACIA );
+
+static Uint8		ACIA_Read_SR ( ACIA_STRUCT *pACIA );
+static void		ACIA_Write_CR ( ACIA_STRUCT *pACIA , Uint8 CR );
+static Uint8		ACIA_Read_RDR ( ACIA_STRUCT *pACIA );
+static void		ACIA_Write_TDR ( ACIA_STRUCT *pACIA , Uint8 TDR );
+
+static void		ACIA_Prepare_TX ( ACIA_STRUCT *pACIA );
+static void		ACIA_Prepare_RX ( ACIA_STRUCT *pACIA );
+static void		ACIA_Clock_TX ( ACIA_STRUCT *pACIA );
+static void		ACIA_Clock_RX ( ACIA_STRUCT *pACIA );
+
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Init the 2 ACIAs in an Atari ST.
+ * Both ACIAs have a 500 MHZ TX/RX clock.
+ * This is called only once, when the emulator starts.
+ * NOTE : when testing EmuTos on real hardware, it seems the tx/rx is working
+ * after a cold reset (ST switched on), even if Clock_Divider was not initialized yet.
+ * The default behaviour is not described in the ACIA's ref doc, but bits
+ * seem to be transmitted (maybe with errors ?). So we default
+ * to 9600 bauds to avoid a lock if a program uses tx/rx after a reset.
+ */
+void	ACIA_Init ( ACIA_STRUCT *pAllACIA , Uint32 TX_Clock , Uint32 RX_Clock )
+{
+	int	i;
+
+
+	LOG_TRACE ( TRACE_ACIA, "acia init tx_clock=%d rx_clock=%d\n" , TX_Clock , RX_Clock );
+
+	for ( i=0 ; iSet_Timers = ACIA_Set_Timers_IKBD;
+//	pACIA_MIDI->Set_Timers = ACIA_Set_Timers_MIDI;			/* Not used for now */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * There's no real hardware reset on the ACIA, but as the Reset_ST()
+ * functions turns off all internal interrupts, we must restart the ACIA's
+ * interrupt after a reset.
+ */
+void	ACIA_Reset ( ACIA_STRUCT *pAllACIA )
+{
+	int	i;
+
+
+	LOG_TRACE ( TRACE_ACIA, "acia reset\n" );
+
+	for ( i=0 ; i 0 )				/* Divider already initialized */
+			pAllACIA[ i ].Set_Timers ( &(pAllACIA[ i ]) );		/* Restart the timer */
+	}
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Save/Restore snapshot of local variables ('MemorySnapShot_Store' handles type)
+ */
+void	ACIA_MemorySnapShot_Capture ( bool bSave )
+{
+	MemorySnapShot_Store(&ACIA_Array, sizeof(ACIA_Array));
+
+	if ( !bSave )						/* If restoring */
+		ACIA_Init_Pointers ( ACIA_Array );		/* Restore pointers */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Set or reset the ACIA's IRQ signal.
+ * IRQ signal is inverted (0/low sets irq, 1/high resets irq)
+ * In the ST, the 2 ACIA's IRQ pins are connected to the same MFP input,
+ * so they share the same IRQ bit in GPIP4.
+ */
+static void	ACIA_Set_Line_IRQ_MFP ( int bit )
+{
+	LOG_TRACE ( TRACE_ACIA, "acia set irq line val=%d VBL=%d HBL=%d\n" , bit , nVBLs , nHBL );
+
+	if ( bit == 0 )
+	{
+		/* There's a small delay on a real ST between the point in time
+		* the irq bit is set and the MFP interrupt is triggered - for example
+		* the "V8 music system" demo depends on this behaviour.
+		* This 4 cycle delay is handled in mfp.c */
+		MFP_GPIP_Set_Line_Input ( MFP_GPIP_LINE_ACIA , MFP_GPIP_STATE_LOW );
+	}
+	else
+	{
+		MFP_GPIP_Set_Line_Input ( MFP_GPIP_LINE_ACIA , MFP_GPIP_STATE_HIGH );
+	}
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read the Clear To Send (CTS) pin
+ * When CTS is high, TDRE should always be set to 0
+ * Note : this is not connected on an ST, so we always return 0.
+ */
+static Uint8 	ACIA_Get_Line_CTS_Dummy ( void )
+{
+	Uint8		bit;
+
+	bit = 0;
+	LOG_TRACE ( TRACE_ACIA, "acia get cts=%d VBL=%d HBL=%d\n" , bit , nVBLs , nHBL );
+	return bit;
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read the Data Carrier Detect (DCD) pin
+ * Note : this is not connected on an ST, so we always return 0.
+ */
+static Uint8 	ACIA_Get_Line_DCD_Dummy ( void )
+{
+	Uint8		bit;
+
+	bit = 0;
+	LOG_TRACE ( TRACE_ACIA, "acia get dcd=%d VBL=%d HBL=%d\n" , bit , nVBLs , nHBL );
+	return bit;
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Set the Request To Send (RTS) pin.
+ * Note : this is not connected on an ST, so we ignore it.
+ */
+static void	ACIA_Set_Line_RTS_Dummy ( int bit )
+{
+	LOG_TRACE ( TRACE_ACIA, "acia set rts val=%d VBL=%d HBL=%d\n" , bit , nVBLs , nHBL );
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Set the required timers to handle RX / TX, depending on the CR_DIVIDE
+ * value.
+ * When CR is changed with a new CR_DIVIDE value, we restart the timers.
+ */
+static void	ACIA_Set_Timers_IKBD ( void *pACIA )
+{
+	ACIA_Start_InterruptHandler_IKBD ( (ACIA_STRUCT *)pACIA , 0 );
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Set a timer to handle the RX / TX bits at the expected baud rate.
+ * NOTE : on ST, TX_Clock and RX_Clock are the same, so the timer's freq will be
+ * TX_Clock / Divider and we only need one timer interrupt to handle both RX and TX.
+ * This freq should be converted to CPU_CYCLE : 1 ACIA cycle = 16 CPU cycles
+ * (with cpu running at 8 MHz)
+ * InternalCycleOffset allows to compensate for a != 0 value in PendingInterruptCount
+ * to keep a constant baud rate.
+ * TODO : we use a fixed 8 MHz clock and nCpuFreqShift to convert cycles for our
+ * internal timers in cycInt.c. This should be replaced some days by using
+ * MachineClocks.CPU_Freq and not using nCpuFreqShift anymore.
+ */
+static void	ACIA_Start_InterruptHandler_IKBD ( ACIA_STRUCT *pACIA , int InternalCycleOffset )
+{
+	int		Cycles;
+
+
+//	Cycles = MachineClocks.CPU_Freq / pACIA->TX_Clock;		/* Convert ACIA cycles in CPU cycles */
+	Cycles = 8021247 / pACIA->TX_Clock;				/* Convert ACIA cycles in CPU cycles, for a 8 MHz STF reference */
+	Cycles *= pACIA->Clock_Divider;
+	Cycles <<= nCpuFreqShift;					/* Compensate for x2 or x4 cpu speed */
+
+	LOG_TRACE ( TRACE_ACIA, "acia %s start timer divider=%d cpu_cycles=%d VBL=%d HBL=%d\n" , pACIA->ACIA_Name ,
+		pACIA->Clock_Divider , Cycles , nVBLs , nHBL );
+
+	CycInt_AddRelativeInterruptWithOffset ( Cycles, INT_CPU_CYCLE, INTERRUPT_ACIA_IKBD , InternalCycleOffset );
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Interrupt called each time a new bit must be sent / received with the IKBD.
+ * This interrupt will be called at freq ( 500 MHz / ACIA_CR_COUNTER_DIVIDE )
+ * On ST, RX_Clock = TX_Clock = 500 MHz.
+ * We continuously restart the interrupt, taking into account PendingCyclesOver.
+ */
+void	ACIA_InterruptHandler_IKBD ( void )
+{
+	int	PendingCyclesOver;
+
+
+	/* Number of internal cycles we went over for this timer ( <= 0 ) */
+	/* Used to restart the next timer and keep a constant baud rate */
+	PendingCyclesOver = -PendingInterruptCount;			/* >= 0 */
+
+	LOG_TRACE ( TRACE_ACIA, "acia ikbd interrupt handler pending_cyc=%d VBL=%d HBL=%d\n" , PendingCyclesOver , nVBLs , nHBL );
+
+	/* Remove this interrupt from list and re-order */
+	CycInt_AcknowledgeInterrupt();
+
+	ACIA_Clock_TX ( pACIA_IKBD );
+	ACIA_Clock_RX ( pACIA_IKBD );
+
+	ACIA_Start_InterruptHandler_IKBD ( pACIA_IKBD , -PendingCyclesOver );	/* Compensate for a != 0 value of PendingCyclesOver */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Interrupt called each time a new bit must be sent / received with the MIDI.
+ * This interrupt will be called at freq ( 500 MHz / ACIA_CR_COUNTER_DIVIDE )
+ * On ST, RX_Clock = TX_Clock = 500 MHz.
+ */
+void	ACIA_InterruptHandler_MIDI ( void )
+{
+	ACIA_Clock_TX ( pACIA_MIDI );
+	ACIA_Clock_RX ( pACIA_MIDI );
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * - For each access to an ACIA register, a 6 cycles delay is added to the
+ *   normal 68000 timing for the current CPU instruction. If the instruction
+ *   accesses several registers at once, the delays are cumulated.
+ * - An additional delay will also be added to ensure the 68000 clock and
+ *   the E clock are synchronised ; this delay can add between 0 and 8 cycles
+ *   to reach the next multiple of 10 cycles. This delay is added only once
+ *   per CPU instruction.
+ * These delays are measured for an 8 MHz 68000 CPU.
+ */
+void	ACIA_AddWaitCycles ( void )
+{
+	int	cycles;
+
+	/* Add a default of 6 cycles for each access */
+	cycles = 6;
+
+	/* Wait for E clock only if this is the first ACIA access for this instruction */
+	/* (NOTE : in UAE, movep behaves like several bytes access with different IoAccessBaseAddress, */
+	/* so only the first movep's access should wait for E Clock) */
+	if ( ( ( MovepByteNbr == 0 ) && ( IoAccessBaseAddress == IoAccessCurrentAddress ) )
+	  || ( MovepByteNbr == 1 ) )					/* First access of a movep */
+		cycles += M68000_WaitEClock ();
+	
+	M68000_WaitState ( cycles );
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Return SR for the IKBD's ACIA (0xfffc00)
+ */
+void	ACIA_IKBD_Read_SR ( void )
+{
+	ACIA_AddWaitCycles ();						/* Additional cycles when accessing the ACIA */
+
+	IoMem[0xfffc00] = ACIA_Read_SR ( pACIA_IKBD );
+
+	if (LOG_TRACE_LEVEL(TRACE_ACIA))
+	{
+		int FrameCycles, HblCounterVideo, LineCycles;
+		Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+		LOG_TRACE_PRINT("acia %s read fffc00 sr=0x%02x video_cyc=%d %d@%d pc=%x instr_cycle %d\n", pACIA_IKBD->ACIA_Name ,
+		                IoMem[0xfffc00], FrameCycles, LineCycles, HblCounterVideo, M68000_GetPC(), CurrentInstrCycles);
+	}
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Return RDR for the IKBD's ACIA (0xfffc02) : receive a byte from the IKBD
+ */
+void	ACIA_IKBD_Read_RDR ( void )
+{
+	ACIA_AddWaitCycles ();						/* Additional cycles when accessing the ACIA */
+
+	IoMem[0xfffc02] = ACIA_Read_RDR ( pACIA_IKBD );
+
+	if (LOG_TRACE_LEVEL(TRACE_IKBD_ACIA))
+	{
+		int FrameCycles, HblCounterVideo, LineCycles;
+		Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+		LOG_TRACE_PRINT("acia %s read fffc02 rdr=0x%02x video_cyc=%d %d@%d pc=%x instr_cycle %d\n", pACIA_IKBD->ACIA_Name ,
+				IoMem[0xfffc02], FrameCycles, LineCycles, HblCounterVideo, M68000_GetPC(), CurrentInstrCycles);
+	}
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to CR in the IKBD's ACIA (0xfffc00)
+ */
+void	ACIA_IKBD_Write_CR ( void )
+{
+	int FrameCycles, HblCounterVideo, LineCycles;
+
+	ACIA_AddWaitCycles ();						/* Additional cycles when accessing the ACIA */
+
+	Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+	LOG_TRACE(TRACE_IKBD_ACIA, "acia %s write fffc00 cr=0x%02x video_cyc=%d %d@%d pc=%x instr_cycle %d\n", pACIA_IKBD->ACIA_Name ,
+				IoMem[0xfffc00], FrameCycles, LineCycles, HblCounterVideo, M68000_GetPC(), CurrentInstrCycles);
+
+	ACIA_Write_CR ( pACIA_IKBD , IoMem[0xfffc00] );
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to TDR in the IKBD's ACIA (0xfffc02) : send a byte to the IKBD
+ */
+void	ACIA_IKBD_Write_TDR ( void )
+{
+	int FrameCycles, HblCounterVideo, LineCycles;
+
+	ACIA_AddWaitCycles ();						/* Additional cycles when accessing the ACIA */
+
+	Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+	LOG_TRACE(TRACE_IKBD_ACIA, "acia %s write fffc02 tdr=0x%02x video_cyc=%d %d@%d pc=%x instr_cycle %d\n", pACIA_IKBD->ACIA_Name ,
+				IoMem[0xfffc02], FrameCycles, LineCycles, HblCounterVideo, M68000_GetPC(), CurrentInstrCycles);
+
+	ACIA_Write_TDR ( pACIA_IKBD , IoMem[0xfffc02] );
+}
+
+
+
+
+/*----------------------------------------------------------------------*/
+/* The part below is the real core of the 6850's emulation.		*/
+/*									*/
+/* This core is not correlated to any specific machine. All the specific*/
+/* code between the 6850 and the rest of Hatari is called through some	*/
+/* callback functions (see above).					*/
+/*----------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Reset an ACIA.
+ * There's no RESET pin on the MC6850, so the only way to reset the ACIA
+ * is to set bit 0 an 1 to 0x03 in the CR to force a master reset.
+ * This will clear SR (except CTS and DCD) and halt/initialize both the
+ * receiver and transmitter.
+ * This also returns the new state of the RTS bit, that must be updated
+ * in ACIA_Write_CR.
+ */
+static Uint8	ACIA_MasterReset ( ACIA_STRUCT *pACIA , Uint8 CR )
+{
+	Uint8		dcd_bit;
+	Uint8		cts_bit;
+	Uint8		rts_bit;
+
+
+	LOG_TRACE ( TRACE_ACIA, "acia %s master reset VBL=%d HBL=%d\n" , pACIA->ACIA_Name , nVBLs , nHBL );
+	
+	dcd_bit = pACIA->Get_Line_DCD ();
+	cts_bit = pACIA->Get_Line_CTS ();
+
+	pACIA->SR = ACIA_SR_BIT_TDRE | ( dcd_bit << 2 ) | ( cts_bit << 3 );
+
+	pACIA->TX_State = ACIA_STATE_IDLE;
+	pACIA->TSR = 0;
+	pACIA->TX_Size = 0;
+	pACIA->TX_SendBrk = 0;
+
+	pACIA->RX_State = ACIA_STATE_IDLE;
+	pACIA->RSR = 0;
+	pACIA->RX_Size = 0;
+	pACIA->RX_Overrun = 0;
+
+	/* On Master Reset, IRQ line is high */
+	/* If it's the 1st reset, RTS should be high, else RTS depends on CR bit 5 and 6 */
+	pACIA->Set_Line_IRQ ( 1 );					/* IRQ line goes high */
+	if ( pACIA->FirstMasterReset == 1 )
+	{
+		pACIA->FirstMasterReset = 0;
+		rts_bit = 1;						/* RTS line goes high */
+	}
+	else
+		rts_bit = ( ACIA_CR_TRANSMITTER_CONTROL ( CR ) == 0x02 ) ? 1 : 0;
+
+	return rts_bit;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Check if the IRQ must be changed in SR.
+ * When there's a change, we must change the IRQ line too.
+ */
+static void	ACIA_UpdateIRQ ( ACIA_STRUCT *pACIA )
+{
+	Uint8		irq_bit_new;
+
+	irq_bit_new = 0;
+
+	if ( ACIA_CR_RECEIVE_INTERRUPT_ENABLE ( pACIA->CR ) 		/* Check for RX causes of interrupt */
+	  && ( ( pACIA->SR & ( ACIA_SR_BIT_RDRF | ACIA_SR_BIT_DCD ) )
+	    || ( pACIA->RX_Overrun ) ) )
+	  irq_bit_new = ACIA_SR_BIT_IRQ;
+//fprintf(stderr , "acia irq %x %x %x %d\n" , pACIA->CR , pACIA->SR , pACIA->RX_Overrun , irq_bit_new);
+
+	if ( pACIA->TX_EnableInt					/* Check for TX causes of interrupt */
+	  && ( pACIA->SR & ACIA_SR_BIT_TDRE )
+	  && ( ( pACIA->SR & ACIA_SR_BIT_CTS ) == 0 ) )
+	  irq_bit_new = ACIA_SR_BIT_IRQ;
+	
+	/* Update SR and IRQ line if a change happened */
+	if ( ( pACIA->SR & ACIA_SR_BIT_IRQ ) != irq_bit_new )
+	{
+		LOG_TRACE ( TRACE_ACIA, "acia %s update irq irq_new=%d VBL=%d HBL=%d\n" , pACIA->ACIA_Name , irq_bit_new?1:0 , nVBLs , nHBL );
+
+		if ( irq_bit_new )
+		{
+			pACIA->SR |= ACIA_SR_BIT_IRQ;			/* Set IRQ bit */
+			pACIA->Set_Line_IRQ ( 0 );			/* IRQ line goes low */
+		}
+		else
+		{
+			pACIA->SR &= ~ACIA_SR_BIT_IRQ;			/* Clear IRQ bit */
+			pACIA->Set_Line_IRQ ( 1 );			/* IRQ line goes high */
+		}
+	}
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read SR.
+ * Also update CTS ; when CTS is high, TDRE should always be masked to 0.
+ */
+static Uint8	ACIA_Read_SR ( ACIA_STRUCT *pACIA )
+{
+	Uint8	SR;
+
+
+	if ( pACIA->Get_Line_CTS() == 1 )
+		pACIA->SR |= ACIA_SR_BIT_CTS;
+	else
+		pACIA->SR &= ~ACIA_SR_BIT_CTS;
+
+	SR = pACIA->SR;
+	pACIA->SR_Read = 1;						/* Used in ACIA_Read_RDR to clear Overrun and DCD IRQ */
+
+	if ( SR & ACIA_SR_BIT_CTS )
+		SR &= ~ACIA_SR_BIT_TDRE;				/* Inhibit TDRE when CTS is set */
+
+	LOG_TRACE ( TRACE_ACIA, "acia %s read sr data=0x%02x VBL=%d HBL=%d\n" , pACIA->ACIA_Name , SR , nVBLs , nHBL );
+
+	return SR;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to CR.
+ */
+static void	ACIA_Write_CR ( ACIA_STRUCT *pACIA , Uint8 CR )
+{
+	int	Divide;
+	int	Force_rts_bit;
+	Uint8	rts_bit=0;
+
+	LOG_TRACE ( TRACE_ACIA, "acia %s write cr data=0x%02x VBL=%d HBL=%d\n" , pACIA->ACIA_Name , CR , nVBLs , nHBL );
+
+	/* Bit 0 and 1 : Counter Divide */
+	Divide = ACIA_CR_COUNTER_DIVIDE ( CR );
+	if ( Divide == 0x03 )
+	{
+		Force_rts_bit = ACIA_MasterReset ( pACIA , CR );	/* Special behaviour for RTS after a master reset */
+	}
+	else
+	{
+		if ( ACIA_CR_COUNTER_DIVIDE ( CR ) != ACIA_CR_COUNTER_DIVIDE ( pACIA->CR ) )
+		{
+			pACIA->Clock_Divider = ACIA_Counter_Divide[ Divide ];
+			pACIA->Set_Timers ( pACIA );			/* Set a timer at the baud rate computed from Clock_Divider */
+		}
+		Force_rts_bit = -1;					/* Don't force RTS bit, use bit 5/6 in CR */
+	}
+
+	/* Bits 2, 3 and 4 : word select */
+	/* Don't do anything here, see ACIA_Prepare_TX and ACIA_Prepare_RX */
+
+	/* Bits 5 and 6 : transmitter control */
+	pACIA->TX_EnableInt = 0;
+	pACIA->TX_SendBrk = 0;
+	switch ( ACIA_CR_TRANSMITTER_CONTROL ( CR ) )
+	{
+	  case 0x00 :
+		rts_bit = 0;
+		break;
+	  case 0x01 :
+		rts_bit = 0;
+		pACIA->TX_EnableInt = 1;
+		break;
+	  case 0x02 :
+		rts_bit = 1;
+		break;
+	  case 0x03 :
+		rts_bit = 0;
+		pACIA->TX_SendBrk = 1;					/* We will send break bit until CR is changed */
+		break;
+	}
+
+	if ( Force_rts_bit >= 0 )
+		rts_bit = Force_rts_bit;				/* Use the value from ACIA_MasterReset */
+	pACIA->Set_Line_RTS ( rts_bit );
+
+	/* Bits 7 : receive interrupt enable, see ACIA_UpdateIRQ */
+
+	pACIA->CR = CR;
+
+	ACIA_UpdateIRQ ( pACIA );
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read RDR. This will clear RDRF and PE.
+ * - OVRN / DCD bits are cleared if SR was read before reading RDR.
+ * - OVRN bit is set only when reading RDR, not when the actual overrun happened
+ *   during ACIA_Clock_RX.
+ * - IRQ bit should be updated depending on the new values of BIT_RDRF,
+ *   BIT_DCD and BIT_OVRN.
+ */
+static Uint8	ACIA_Read_RDR ( ACIA_STRUCT *pACIA )
+{
+	pACIA->SR &= ~( ACIA_SR_BIT_RDRF | ACIA_SR_BIT_PE );
+
+	/* If we read RDR after reading SR, we clear OVRN / DCD bits */
+	if ( pACIA->SR_Read == 1 )
+	{
+		pACIA->SR_Read = 0;
+		pACIA->SR &= ~( ACIA_SR_BIT_DCD | ACIA_SR_BIT_OVRN );
+		if ( pACIA->Get_Line_DCD () == 1 )
+			pACIA->SR |= ACIA_SR_BIT_DCD;
+	}
+
+	if ( pACIA->RX_Overrun )
+	{  
+		pACIA->SR |= ACIA_SR_BIT_OVRN;
+		pACIA->RX_Overrun = 0;
+	}
+
+	ACIA_UpdateIRQ ( pACIA );
+
+	LOG_TRACE ( TRACE_ACIA, "acia %s read rdr data=0x%02x new sr=0x%02x overrun=%s VBL=%d HBL=%d\n" , pACIA->ACIA_Name , pACIA->RDR ,
+		pACIA->SR , ( pACIA->SR & ACIA_SR_BIT_OVRN ) ? "yes" : "no" , nVBLs , nHBL );
+
+	return pACIA->RDR;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to TDR.
+ * If the TX process is idle, we should not prepare a new transfer
+ * immediately, to ensure that BIT_TDRE remains clear until the next bit
+ * is sent (BIT_TDRE will be set again in ACIA_Clock_TX).
+ */
+static void	ACIA_Write_TDR ( ACIA_STRUCT *pACIA , Uint8 TDR )
+{
+	LOG_TRACE ( TRACE_ACIA, "acia %s write tdr data=0x%02x overwrite=%s tx_state=%d VBL=%d HBL=%d\n" , pACIA->ACIA_Name , TDR ,
+		( pACIA->SR & ACIA_SR_BIT_TDRE ) ? "no" : "yes" , pACIA->TX_State , nVBLs , nHBL );
+
+	pACIA->TDR = TDR;
+	pACIA->SR &= ~ACIA_SR_BIT_TDRE;					/* TDR is not empty anymore */
+
+	ACIA_UpdateIRQ ( pACIA );
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Prepare a new transfer. Copy TDR to TSR and initialize parity, data size
+ * and stop bits.
+ * Transfer will then start at the next call of ACIA_Clock_TX
+ */
+static void	ACIA_Prepare_TX ( ACIA_STRUCT *pACIA )
+{
+	pACIA->TSR = pACIA->TDR;
+	pACIA->TX_Parity = 0;
+	pACIA->TX_Size = ACIA_Serial_Params[ ACIA_CR_WORD_SELECT ( pACIA->CR ) ].DataBits;
+	pACIA->TX_StopBits = ACIA_Serial_Params[ ACIA_CR_WORD_SELECT ( pACIA->CR ) ].StopBits;
+
+	pACIA->SR |= ACIA_SR_BIT_TDRE;					/* TDR was copied to TSR. TDR is now empty */
+
+	LOG_TRACE ( TRACE_ACIA, "acia %s prepare tx tsr=0x%02x size=%d stop=%d VBL=%d HBL=%d\n" , pACIA->ACIA_Name , pACIA->TSR ,
+		pACIA->TX_Size , pACIA->TX_StopBits , nVBLs , nHBL );
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Prepare a new reception. Initialize parity, data size and stop bits.
+ */
+static void	ACIA_Prepare_RX ( ACIA_STRUCT *pACIA )
+{
+	pACIA->RSR = 0;
+	pACIA->RX_Parity = 0;
+	pACIA->RX_Size = ACIA_Serial_Params[ ACIA_CR_WORD_SELECT ( pACIA->CR ) ].DataBits;
+	pACIA->RX_StopBits = ACIA_Serial_Params[ ACIA_CR_WORD_SELECT ( pACIA->CR ) ].StopBits;
+
+	LOG_TRACE ( TRACE_ACIA, "acia %s prepare rx size=%d stop=%d VBL=%d HBL=%d\n" , pACIA->ACIA_Name ,
+		pACIA->RX_Size , pACIA->RX_StopBits , nVBLs , nHBL );
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write a new bit on the TX line each time the TX clock expires.
+ * This will send TDR over the serial line, using TSR, with additional
+ * parity and start/stop bits.
+ * We send bit 0 of TSR, then TSR is shifted to the right.
+ */
+static void	ACIA_Clock_TX ( ACIA_STRUCT *pACIA )
+{
+	int	StateNext;
+	Uint8	tx_bit;
+
+
+	LOG_TRACE ( TRACE_ACIA, "acia %s clock_tx tx_state=%d VBL=%d HBL=%d\n" , pACIA->ACIA_Name , pACIA->TX_State , nVBLs , nHBL );
+
+	StateNext = -1;
+	switch ( pACIA->TX_State )
+	{
+	  case ACIA_STATE_IDLE :
+		if ( pACIA->TX_SendBrk )
+		{
+			pACIA->Set_Line_TX ( 0 );			/* Send 1 break bit */
+			break;
+		}
+
+		/* If TDR is not empty when we are in idle state, */
+		/* this means we have a new byte to send */
+		if ( ( pACIA->SR & ACIA_SR_BIT_TDRE ) == 0 )
+			ACIA_Prepare_TX ( pACIA );
+
+		if ( pACIA->TX_Size == 0 )				/* TSR is empty */
+			pACIA->Set_Line_TX ( 1 );			/* Send stop bits when idle */
+
+		else							/* TSR has some new bits to transfer */
+		{
+			pACIA->Set_Line_TX ( 0 );			/* Send 1 start bit */
+			StateNext = ACIA_STATE_DATA_BIT;
+		}
+		break;
+
+	  case ACIA_STATE_DATA_BIT :
+		tx_bit = pACIA->TSR & 1;				/* New bit to send */
+		pACIA->Set_Line_TX ( tx_bit );
+		pACIA->TX_Parity ^= tx_bit;
+		pACIA->TSR >>= 1;
+		pACIA->TX_Size--;
+
+		if ( pACIA->TX_Size == 0 )
+		{
+			if ( ACIA_Serial_Params[ ACIA_CR_WORD_SELECT ( pACIA->CR ) ].Parity != ACIA_PARITY_NONE )
+				StateNext = ACIA_STATE_PARITY_BIT;
+			else
+				StateNext = ACIA_STATE_STOP_BIT;	/* No parity */
+		}
+		break;
+
+	  case ACIA_STATE_PARITY_BIT :
+		if ( ACIA_Serial_Params[ ACIA_CR_WORD_SELECT ( pACIA->CR ) ].Parity == ACIA_PARITY_EVEN )
+			pACIA->Set_Line_TX ( pACIA->TX_Parity );
+		else
+			pACIA->Set_Line_TX ( ( ~pACIA->TX_Parity ) & 1 );
+
+		StateNext = ACIA_STATE_STOP_BIT;
+		break;
+
+	  case ACIA_STATE_STOP_BIT :
+		pACIA->Set_Line_TX ( 1 );				/* Send 1 stop bit */
+		pACIA->TX_StopBits--;
+
+		if ( pACIA->TX_StopBits == 0 )				/* All stop bits were sent : transfer is complete */
+		{
+			StateNext = ACIA_STATE_IDLE;			/* Go to idle state to see if a new TDR need to be sent */
+		}
+		break;
+	}
+
+	ACIA_UpdateIRQ ( pACIA );
+
+	if ( StateNext >= 0 )
+		pACIA->TX_State = StateNext;				/* Go to a new state */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Handle a new bit on the RX line each time the RX clock expires.
+ * This will fill RDR with bits received from the serial line, using RSR.
+ * Incoming bits are stored in bit 7 of RSR, then RSR is shifted to the right.
+ */
+static void	ACIA_Clock_RX ( ACIA_STRUCT *pACIA )
+{
+	int	StateNext;
+	Uint8	rx_bit;
+
+
+	rx_bit = pACIA->Get_Line_RX();
+
+	LOG_TRACE ( TRACE_ACIA, "acia %s clock_rx rx_state=%d bit=%d VBL=%d HBL=%d\n" , pACIA->ACIA_Name , pACIA->RX_State , rx_bit , nVBLs , nHBL );
+
+	StateNext = -1;
+	switch ( pACIA->RX_State )
+	{
+	  case ACIA_STATE_IDLE :
+		if ( rx_bit == 0 )					/* Receive 1 start bit */
+		{
+			ACIA_Prepare_RX ( pACIA );
+			StateNext = ACIA_STATE_DATA_BIT;
+		}
+		break;							/* If no start bit, we stay in idle state */
+
+	  case ACIA_STATE_DATA_BIT :
+		if ( rx_bit )
+			pACIA->RSR |= 0x80;
+		pACIA->RX_Parity ^= rx_bit;
+		pACIA->RX_Size--;
+
+		if ( pACIA->RX_Size > 0 )				/* All bits were not received yet */
+		{
+			pACIA->RSR >>= 1;
+		}
+		else
+		{
+// [NP] : MC6850 doc is not very clear "the overrun condition begins at the midpoint of the last bit
+// of the second character received [...]". Is it the last bit of the data word, or the stop bit ?
+// It makes more sense to check for overrun after the stop bit, when RSR should be copied to RDR,
+// because RDR could be read between the last data bit and the stop bit, so RX_Overrun and
+// ACIA_SR_BIT_OVRN would need to be cancelled.
+// 			if ( pACIA->SR & ACIA_SR_BIT_RDRF )
+// 			{
+// 				LOG_TRACE ( TRACE_ACIA, "acia %s clock_rx overrun rsr=0x%02x VBL=%d HBL=%d\n" ,
+// 					pACIA->ACIA_Name , pACIA->RSR , nVBLs , nHBL );
+// 				pACIA->RX_Overrun = 1;			/* Bit in SR will be set when reading RDR */
+// 			}
+			if ( ACIA_Serial_Params[ ACIA_CR_WORD_SELECT ( pACIA->CR ) ].Parity != ACIA_PARITY_NONE )
+				StateNext = ACIA_STATE_PARITY_BIT;
+			else
+				StateNext = ACIA_STATE_STOP_BIT;	/* No parity */
+		}
+		break;
+
+	  case ACIA_STATE_PARITY_BIT :
+		if ( ( ACIA_Serial_Params[ ACIA_CR_WORD_SELECT ( pACIA->CR ) ].Parity == ACIA_PARITY_EVEN )
+		    && ( pACIA->RX_Parity != rx_bit ) )
+			pACIA->SR |= ACIA_SR_BIT_PE;
+
+		else if ( pACIA->RX_Parity == rx_bit )			/* Odd parity */
+			pACIA->SR |= ACIA_SR_BIT_PE;
+
+		if ( pACIA->SR & ACIA_SR_BIT_PE )
+			LOG_TRACE ( TRACE_ACIA, "acia %s clock_rx parity error VBL=%d HBL=%d\n" , pACIA->ACIA_Name , nVBLs , nHBL );
+
+		StateNext = ACIA_STATE_STOP_BIT;
+		break;
+
+	  case ACIA_STATE_STOP_BIT :
+		if ( rx_bit == 1 )					/* Wait for 1 or 2 "1" stop bits */
+		{
+			pACIA->RX_StopBits--;
+			if ( pACIA->RX_StopBits == 0 )			/* All stop bits were received : reception is complete */
+			{
+				pACIA->SR &= ~ACIA_SR_BIT_FE;
+				
+				if ( ( pACIA->SR & ACIA_SR_BIT_RDRF ) == 0 )
+				{
+					pACIA->RDR = pACIA->RSR;
+					pACIA->SR |= ACIA_SR_BIT_RDRF;
+					LOG_TRACE ( TRACE_ACIA, "acia %s clock_rx received rdr=0x%02x VBL=%d HBL=%d\n" ,
+						pACIA->ACIA_Name , pACIA->RDR , nVBLs , nHBL );
+				}
+				else
+				{
+					LOG_TRACE ( TRACE_ACIA, "acia %s clock_rx overrun rsr=0x%02x unread rdr=0x%02x VBL=%d HBL=%d\n" ,
+						pACIA->ACIA_Name , pACIA->RSR , pACIA->RDR , nVBLs , nHBL );
+					pACIA->RX_Overrun = 1;		/* Bit in SR will be set when reading RDR */
+				}
+				StateNext = ACIA_STATE_IDLE;		/* Go to idle state and wait for start bit */
+			}
+		}
+		else							/* Not a valid stop bit */
+		{
+			LOG_TRACE ( TRACE_ACIA, "acia %s clock_rx framing error VBL=%d HBL=%d\n" , pACIA->ACIA_Name , nVBLs , nHBL );
+
+			/* According to the A6850 doc, RSR is copied to RDR in case of a framing error */
+			/* (Should be the same for the MC6850 ?) */
+			pACIA->SR |= ACIA_SR_BIT_FE;
+			pACIA->RDR = pACIA->RSR;
+			StateNext = ACIA_STATE_IDLE;			/* Go to idle state and wait for start bit */
+		}
+		break;
+	}
+
+	ACIA_UpdateIRQ ( pACIA );
+
+	if ( StateNext >= 0 )
+		pACIA->RX_State = StateNext;				/* Go to a new state */
+}
+
+
+
diff --git a/src/audio.c b/src/audio.c
new file mode 100644
index 0000000..f7fc0d6
--- /dev/null
+++ b/src/audio.c
@@ -0,0 +1,292 @@
+/*
+  Hatari - audio.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  This file contains the routines which pass the audio data to the SDL library.
+*/
+const char Audio_fileid[] = "Hatari audio.c : " __DATE__ " " __TIME__;
+
+#include 
+
+#include "main.h"
+#include "audio.h"
+#include "configuration.h"
+#include "log.h"
+#include "sound.h"
+#include "dmaSnd.h"
+#include "falcon/crossbar.h"
+
+#include "screen.h"
+#include "video.h"	/* FIXME: video.h is dependent on HBL_PALETTE_LINES from screen.h */
+
+
+int nAudioFrequency = 44100;			/* Sound playback frequency */
+bool bSoundWorking = false;			/* Is sound OK */
+static volatile bool bPlayingBuffer = false;	/* Is playing buffer? */
+int SoundBufferSize = 1024 / 4;			/* Size of sound buffer (in samples) */
+int CompleteSndBufIdx;				/* Replay-index into MixBuffer */
+int SdlAudioBufferSize = 0;			/* in ms (0 = use default) */
+int pulse_swallowing_count = 0;			/* Sound disciplined emulation rate controlled by  */
+						/*  window comparator and pulse swallowing counter */
+
+/*-----------------------------------------------------------------------*/
+/**
+ * SDL audio callback function - copy emulation sound to audio system.
+ */
+static void Audio_CallBack(void *userdata, Uint8 *stream, int len)
+{
+	Sint16 *pBuffer;
+	int i, window, nSamplesPerFrame;
+
+	pBuffer = (Sint16 *)stream;
+	len = len / 4;  // Use length in samples (16 bit stereo), not in bytes
+
+	/* Adjust emulation rate within +/- 0.58% (10 cents) occasionally,
+	 * to synchronize sound. Note that an octave (frequency doubling)
+	 * has 12 semitones (12th root of two for a semitone), and that
+	 * one semitone has 100 cents (1200th root of two for one cent).
+	 * Ten cents are desired, thus, the 120th root of two minus one is
+	 * multiplied by 1,000,000 to convert to microseconds, and divided
+	 * by nScreenRefreshRate=60 to get a 96 microseconds swallow size.
+	 * (2^(10cents/(12semitones*100cents)) - 1) * 10^6 / nScreenRefreshRate
+	 * See: main.c - Main_WaitOnVbl()
+	 */
+
+	pulse_swallowing_count = 0;	/* 0 = Unaltered emulation rate */
+
+	if (ConfigureParams.Sound.bEnableSoundSync)
+	{
+		/* Sound synchronized emulation */
+		nSamplesPerFrame = nAudioFrequency/nScreenRefreshRate;
+		window = (nSamplesPerFrame > SoundBufferSize) ? nSamplesPerFrame : SoundBufferSize;
+
+		/* Window Comparator for SoundBufferSize */
+		if (nGeneratedSamples < window + (window >> 1))
+		/* Increase emulation rate to maintain sound synchronization */
+			pulse_swallowing_count = -5793 / nScreenRefreshRate;
+		else
+		if (nGeneratedSamples > (window << 1) + (window >> 2))
+		/* Decrease emulation rate to maintain sound synchronization */
+			pulse_swallowing_count = 5793 / nScreenRefreshRate;
+
+		/* Otherwise emulation rate is unaltered. */
+	}
+
+	if (nGeneratedSamples >= len)
+	{
+		/* Enough samples available: Pass completed buffer to audio system
+		 * by write samples into sound buffer and by converting them from
+		 * 'signed' to 'unsigned' */
+		for (i = 0; i < len; i++)
+		{
+			*pBuffer++ = MixBuffer[(CompleteSndBufIdx + i) % MIXBUFFER_SIZE][0];
+			*pBuffer++ = MixBuffer[(CompleteSndBufIdx + i) % MIXBUFFER_SIZE][1];
+		}
+		CompleteSndBufIdx += len;
+		nGeneratedSamples -= len;
+	}
+	else  /* Not enough samples available: */
+	{
+		for (i = 0; i < nGeneratedSamples; i++)
+		{
+			*pBuffer++ = MixBuffer[(CompleteSndBufIdx + i) % MIXBUFFER_SIZE][0];
+			*pBuffer++ = MixBuffer[(CompleteSndBufIdx + i) % MIXBUFFER_SIZE][1];
+		}
+		/* If the buffer is filled more than 50%, mirror sample buffer to fake the
+		 * missing samples */
+		if (nGeneratedSamples >= len/2)
+		{
+			int remaining = len - nGeneratedSamples;
+			memcpy(pBuffer, stream+(nGeneratedSamples-remaining)*4, remaining*4);
+		}
+		CompleteSndBufIdx += nGeneratedSamples;
+		nGeneratedSamples = 0;
+		
+	}
+
+	CompleteSndBufIdx = CompleteSndBufIdx % MIXBUFFER_SIZE;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Initialize the audio subsystem. Return true if all OK.
+ * We use direct access to the sound buffer, set to a unsigned 8-bit mono stream.
+ */
+void Audio_Init(void)
+{
+	SDL_AudioSpec desiredAudioSpec;    /* We fill in the desired SDL audio options here */
+
+	/* Is enabled? */
+	if (!ConfigureParams.Sound.bEnableSound)
+	{
+		/* Stop any sound access */
+		Log_Printf(LOG_DEBUG, "Sound: Disabled\n");
+		bSoundWorking = false;
+		return;
+	}
+
+	/* Init the SDL's audio subsystem: */
+	if (SDL_WasInit(SDL_INIT_AUDIO) == 0)
+	{
+		if (SDL_InitSubSystem(SDL_INIT_AUDIO) < 0)
+		{
+			fprintf(stderr, "Could not init audio: %s\n", SDL_GetError() );
+			bSoundWorking = false;
+			return;
+		}
+	}
+
+	/* Set up SDL audio: */
+	desiredAudioSpec.freq = nAudioFrequency;
+	desiredAudioSpec.format = AUDIO_S16SYS;		/* 16-Bit signed */
+	desiredAudioSpec.channels = 2;			/* stereo */
+	desiredAudioSpec.callback = Audio_CallBack;
+	desiredAudioSpec.userdata = NULL;
+
+	/* In most case, setting samples to 1024 will give an equivalent */
+	/* sdl sound buffer of ~20-30 ms (depending on freq). */
+	/* But setting samples to 1024 for all the freq can cause some faulty */
+	/* OS sound drivers to add an important delay when playing sound at lower freq. */
+	/* In that case we use SdlAudioBufferSize (in ms) to compute a value */
+	/* of samples that matches the corresponding freq and buffer size. */
+	if ( SdlAudioBufferSize == 0 )			/* don't compute "samples", use default value */
+		desiredAudioSpec.samples = 1024;	/* buffer size in samples */
+	else
+	{
+		int samples = (desiredAudioSpec.freq / 1000) * SdlAudioBufferSize;
+		int power2 = 1;
+		while ( power2 < samples )		/* compute the power of 2 just above samples */
+                        power2 *= 2;
+
+//fprintf ( stderr , "samples %d power %d\n" , samples , power2 );
+		desiredAudioSpec.samples = power2;	/* number of samples corresponding to the requested SdlAudioBufferSize */
+	}
+
+
+	if (SDL_OpenAudio(&desiredAudioSpec, NULL))	/* Open audio device */
+	{
+		fprintf(stderr, "Can't use audio: %s\n", SDL_GetError());
+		bSoundWorking = false;
+		ConfigureParams.Sound.bEnableSound = false;
+		SDL_QuitSubSystem(SDL_INIT_AUDIO);
+		return;
+	}
+
+	SoundBufferSize = desiredAudioSpec.size;	/* May be different than the requested one! */
+	SoundBufferSize /= 4;				/* bytes -> samples (16 bit signed stereo -> 4 bytes per sample) */
+	if (SoundBufferSize > MIXBUFFER_SIZE/2)
+	{
+		fprintf(stderr, "Warning: Soundbuffer size is too big!\n");
+	}
+
+	/* All OK */
+	bSoundWorking = true;
+	/* And begin */
+	Audio_EnableAudio(true);
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Free audio subsystem
+ */
+void Audio_UnInit(void)
+{
+	if (bSoundWorking)
+	{
+		/* Stop */
+		Audio_EnableAudio(false);
+
+		SDL_CloseAudio();
+
+		bSoundWorking = false;
+	}
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Lock the audio sub system so that the callback function will not be called.
+ */
+void Audio_Lock(void)
+{
+	SDL_LockAudio();
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Unlock the audio sub system so that the callback function will be called again.
+ */
+void Audio_Unlock(void)
+{
+	SDL_UnlockAudio();
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Set audio playback frequency variable, pass as PLAYBACK_xxxx
+ */
+void Audio_SetOutputAudioFreq(int nNewFrequency)
+{
+	/* Do not reset sound system if nothing has changed! */
+	if (nNewFrequency != nAudioFrequency)
+	{
+		/* Set new frequency */
+		nAudioFrequency = nNewFrequency;
+
+		if (ConfigureParams.System.nMachineType == MACHINE_FALCON)
+		{
+			/* Compute Ratio between host computer sound frequency and Hatari's sound frequency. */
+			Crossbar_Compute_Ratio();
+		}
+		else if (ConfigureParams.System.nMachineType != MACHINE_ST)
+		{
+			/* Adapt LMC filters to this new frequency */			
+			DmaSnd_Init_Bass_and_Treble_Tables();
+		}
+
+		/* Re-open SDL audio interface if necessary: */
+		if (bSoundWorking)
+		{
+			Audio_UnInit();
+			Audio_Init();
+		}
+	}
+
+	if ((ConfigureParams.System.nMachineType == MACHINE_ST) &&
+		(nAudioFrequency >= 40000))
+	{
+		/* Apply YM2149 C10 filter. */
+		UseLowPassFilter = true;
+	}
+	else
+	{
+		UseLowPassFilter = false;
+	}
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Start/Stop sound buffer
+ */
+void Audio_EnableAudio(bool bEnable)
+{
+	if (bEnable && !bPlayingBuffer)
+	{
+		/* Start playing */
+		SDL_PauseAudio(false);
+		bPlayingBuffer = true;
+	}
+	else if (!bEnable && bPlayingBuffer)
+	{
+		/* Stop from playing */
+		SDL_PauseAudio(true);
+		bPlayingBuffer = false;
+	}
+}
diff --git a/src/avi_record.c b/src/avi_record.c
new file mode 100644
index 0000000..18e37f9
--- /dev/null
+++ b/src/avi_record.c
@@ -0,0 +1,1020 @@
+/*
+  Hatari - avi_record.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  AVI File recording
+
+  This allows Hatari to record a video file, with both video and audio
+  streams, at full frame rate.
+  
+  Video frames are saved using the current video frequency of the emulated
+  machine (50 Hz, 60 Hz, 70 Hz, ...). Frames can be stored using different
+  codecs. So far, supported codecs are :
+   - BMP : uncompressed RGB images. Very fast to save, very few cpu needed
+     but requires a lot of disk bandwidth and a lot of space.
+   - PNG : compressed RBG images. Depending on the compression level, this
+     can require more cpu and could slow down Hatari. As compressed images
+     are much smaller than BMP images, this will require less space on disk
+     and much less disk bandwidth. Compression levels 3 or 4 give good
+     tradeoff between cpu usage and file size and should not slow down Hatari
+     with recent computers.
+
+  PNG compression will often give a x20 ratio when compared to BMP and should
+  be used if you have a powerful enough cpu.
+
+  Sound is saved as 16 bits pcm stereo, using the current Hatari sound output
+  frequency. For best accuracy, sound frequency should be a multiple of the
+  video frequency ; this means 44.1 kHz is the best choice for 50/60 Hz video.
+
+  The AVI file is divided into multiple chunks. Hatari will save one video stream
+  and one audio stream, so the overall structure of the file is the following :
+
+  RIFF avi
+      LIST
+	hdrl
+	  avih
+	  LIST
+	    strl
+	      strh (vids)
+	      strf
+	  LIST
+	    strl
+	      strh (auds)
+	      strf
+      LIST
+	INFO
+      LIST
+	movi
+	  00db
+	  01wb
+	  ...
+      idx1
+*/
+
+const char AVIRecord_fileid[] = "Hatari avi_record.c : " __DATE__ " " __TIME__;
+
+#include 
+#include 
+
+#include "main.h"
+#include "version.h"
+#include "audio.h"
+#include "configuration.h"
+#include "log.h"
+#include "screen.h"
+#include "screenSnapShot.h"
+#include "sound.h"
+#include "statusbar.h"
+#include "avi_record.h"
+
+/* after above that brings in config.h */
+#if HAVE_LIBPNG
+#include 
+#endif
+
+#include "pixel_convert.h"				/* inline functions */
+
+
+
+typedef struct
+{
+	Uint8			ChunkName[4];		/* '00db', '01wb', 'idx1' */
+	Uint8			ChunkSize[4];
+} AVI_CHUNK;
+
+
+typedef struct
+{
+	Uint8			identifier[4];		/* '00db', '01wb', 'idx1' */
+	Uint8			flags[4];
+	Uint8			offset[4];
+	Uint8			length[4];
+} AVI_CHUNK_INDEX;
+
+
+typedef struct
+{
+	Uint8			ChunkName[4];		/* 'strh' */
+	Uint8			ChunkSize[4];
+
+	Uint8			stream_type[4];		/* 'vids' or 'auds' */
+	Uint8			stream_handler[4];
+	Uint8			flags[4];
+	Uint8			priority[2];
+	Uint8			language[2];
+	Uint8			initial_frames[4];
+	Uint8			time_scale[4];
+	Uint8			data_rate[4];
+	Uint8			start_time[4];
+	Uint8			data_length[4];
+	Uint8			buffer_size[4];
+	Uint8			quality[4];
+	Uint8			sample_size[4];
+	Uint8			dest_left[2];
+	Uint8			dest_top[2];
+	Uint8			dest_right[2];
+	Uint8			dest_bottom[2];
+} AVI_STREAM_HEADER;
+
+
+typedef struct
+{
+	Uint8			ChunkName[4];		/* 'strf' */
+	Uint8			ChunkSize[4];
+
+	Uint8			size[4];
+	Uint8			width[4];
+	Uint8			height[4];
+	Uint8			planes[2];
+	Uint8			bit_count[2];
+	Uint8			compression[4];
+	Uint8			size_image[4];
+	Uint8			xpels_meter[4];
+	Uint8			ypels_meter[4];
+	Uint8			clr_used[4];
+	Uint8			clr_important[4];
+} AVI_STREAM_FORMAT_VIDS;
+
+typedef struct
+{
+	Uint8			ChunkName[4];		/* 'LIST' */
+	Uint8			ChunkSize[4];
+
+	Uint8			Name[4];		/* 'strl' */
+	AVI_STREAM_HEADER	Header;			/* 'strh' */
+	AVI_STREAM_FORMAT_VIDS	Format;			/* 'strf' */
+} AVI_STREAM_LIST_VIDS;
+
+
+typedef struct
+{
+	Uint8			ChunkName[4];		/* 'strf' */
+	Uint8			ChunkSize[4];
+
+	Uint8			codec[2];
+	Uint8			channels[2];
+	Uint8			sample_rate[4];
+	Uint8			bit_rate[4];
+	Uint8			block_align[2];
+	Uint8			bits_per_sample[2];
+	Uint8			ext_size[2];
+} AVI_STREAM_FORMAT_AUDS;
+
+typedef struct
+{
+	Uint8			ChunkName[4];		/* 'LIST' */
+	Uint8			ChunkSize[4];
+
+	Uint8			Name[4];		/* 'strl' */
+	AVI_STREAM_HEADER	Header;			/* 'strh' */
+	AVI_STREAM_FORMAT_AUDS	Format;			/* 'strf' */
+} AVI_STREAM_LIST_AUDS;
+
+
+typedef struct {
+	Uint8			ChunkName[4];		/* 'avih' */
+	Uint8			ChunkSize[4];
+
+	Uint8			microsec_per_frame[4];
+	Uint8			max_bytes_per_second[4];
+	Uint8			padding_granularity[4];
+	Uint8			flags[4];
+	Uint8			total_frames[4];
+	Uint8			init_frame[4];
+	Uint8			nb_streams[4];
+	Uint8			buffer_size[4];
+	Uint8			width[4];
+	Uint8			height[4];
+	Uint8			scale[4];
+	Uint8			rate[4];
+	Uint8			start[4];
+	Uint8			length[4];
+} AVI_STREAM_AVIH;
+
+typedef struct
+{
+	Uint8			ChunkName[4];		/* 'LIST' */
+	Uint8			ChunkSize[4];
+
+	Uint8			Name[4];		/* 'hdrl' */
+	AVI_STREAM_AVIH		Header;
+} AVI_STREAM_LIST_AVIH;
+
+
+typedef struct {
+	Uint8			ChunkName[4];		/* 'ISFT' (software used) */
+	Uint8			ChunkSize[4];
+
+//	Uint8			Text[2];		/* Text's size should be multiple of 2 (including '\0') */
+} AVI_STREAM_INFO;
+
+typedef struct
+{
+	Uint8			ChunkName[4];		/* 'LIST' */
+	Uint8			ChunkSize[4];
+
+	Uint8			Name[4];		/* 'INFO' */
+	AVI_STREAM_INFO		Info;
+} AVI_STREAM_LIST_INFO;
+
+
+typedef struct
+{
+	Uint8			ChunkName[4];		/* 'LIST' */
+	Uint8			ChunkSize[4];
+
+	Uint8			Name[4];		/* 'movi' */
+} AVI_STREAM_LIST_MOVI;
+
+
+typedef struct
+{
+  Uint8		signature[4];				/* 'RIFF' */
+  Uint8		filesize[4];
+  Uint8		type[4];				/* 'AVI ' */
+  
+} RIFF_HEADER;
+
+
+typedef struct {
+  RIFF_HEADER			RiffHeader;
+
+  AVI_STREAM_LIST_AVIH		AviHeader;
+  
+  AVI_STREAM_LIST_VIDS		VideoStream;
+  AVI_STREAM_LIST_AUDS		AudioStream;
+  
+} AVI_FILE_HEADER;
+
+
+
+#define	AUDIO_STREAM_WAVE_FORMAT_PCM		0x0001
+
+#define	VIDEO_STREAM_RGB			0x00000000			/* fourcc for BMP video frames */
+#define	VIDEO_STREAM_PNG			"MPNG"				/* fourcc for PNG video frames */
+
+#define	AVIF_HASINDEX				0x00000010			/* index at the end of the file */
+#define	AVIF_ISINTERLEAVED			0x00000100			/* data are interleaved */
+#define	AVIF_TRUSTCKTYPE			0x00000800			/* trust chunk type */
+
+#define	AVIIF_KEYFRAME				0x00000010			/* frame is a keyframe */
+
+
+typedef struct {
+  /* Input params to start recording */
+  int		VideoCodec;
+  int		VideoCodecCompressionLevel;					/* 0-9 for png compression */
+
+  SDL_Surface	*Surface;
+
+  int		CropLeft;
+  int		CropRight;
+  int		CropTop;
+  int		CropBottom;
+
+  int		Fps;					/* Fps << 24 */
+  int		Fps_scale;				/* 1 << 24 */
+
+  int		AudioCodec;
+  int		AudioFreq;
+
+  /* Internal data used by the avi recorder */
+  int		Width;
+  int		Height;
+  int		BitCount;
+  FILE		*FileOut;				/* file to write to */
+  int		TotalVideoFrames;			/* number of recorded video frames */
+  int		TotalAudioSamples;			/* number of recorded audio samples */
+  long		MoviChunkPosStart;			/* as returned by ftell() */
+  long		MoviChunkPosEnd;			/* as returned by ftell() */
+} RECORD_AVI_PARAMS;
+
+
+
+bool		bRecordingAvi = false;
+
+
+static RECORD_AVI_PARAMS	AviParams;
+static AVI_FILE_HEADER		AviFileHeader;
+
+
+static void	Avi_StoreU16 ( Uint8 *p , Uint16 val );
+static void	Avi_StoreU32 ( Uint8 *p , Uint32 val );
+static void	Avi_Store4cc ( Uint8 *p , const char *text );
+static Uint32	Avi_ReadU32 ( Uint8 *p );
+
+static int	Avi_GetBmpSize ( int Width , int Height , int BitCount );
+
+static bool	Avi_RecordVideoStream_BMP ( RECORD_AVI_PARAMS *pAviParams );
+#if HAVE_LIBPNG
+static bool	Avi_RecordVideoStream_PNG ( RECORD_AVI_PARAMS *pAviParams );
+#endif
+static bool	Avi_RecordAudioStream_PCM ( RECORD_AVI_PARAMS *pAviParams , Sint16 pSamples[][2], int SampleIndex, int SampleLength );
+
+static void	Avi_BuildFileHeader ( RECORD_AVI_PARAMS *pAviParams , AVI_FILE_HEADER *pAviFileHeader );
+static bool	Avi_BuildIndex ( RECORD_AVI_PARAMS *pAviParams );
+
+static bool	Avi_StartRecording_WithParams ( RECORD_AVI_PARAMS *pAviParams , char *AviFileName );
+static bool	Avi_StopRecording_WithParams ( RECORD_AVI_PARAMS *pAviParams );
+
+
+
+
+static void	Avi_StoreU16 ( Uint8 *p , Uint16 val )
+{
+	*p++ = val & 0xff;
+	val >>= 8;
+	*p = val & 0xff;
+}
+
+
+static void	Avi_StoreU32 ( Uint8 *p , Uint32 val )
+{
+	*p++ = val & 0xff;
+	val >>= 8;
+	*p++ = val & 0xff;
+	val >>= 8;
+	*p++ = val & 0xff;
+	val >>= 8;
+	*p = val & 0xff;
+}
+
+
+static void	Avi_Store4cc ( Uint8 *p , const char *text )
+{
+	memcpy ( p , text , 4 );
+}
+
+
+static Uint32	Avi_ReadU32 ( Uint8 *p )
+{
+	return (p[3]<<24) + (p[2]<<16) + (p[1]<<8) +p[0];
+}
+
+
+static int	Avi_GetBmpSize ( int Width , int Height , int BitCount )
+{
+	return ( Width * Height * BitCount / 8 );						/* bytes in one video frame */
+}
+
+
+
+static bool	Avi_RecordVideoStream_BMP ( RECORD_AVI_PARAMS *pAviParams )
+{
+	AVI_CHUNK	Chunk;
+	int		SizeImage;
+	Uint8		LineBuf[ 3 * pAviParams->Width ];			/* temp buffer to convert to 24-bit BGR format */
+	Uint8		*pBitmapIn , *pBitmapOut;
+	int		y;
+	int		NeedLock;
+	
+	SizeImage = Avi_GetBmpSize ( pAviParams->Width , pAviParams->Height , pAviParams->BitCount );
+
+	/* Write the video frame header */
+	Avi_Store4cc ( Chunk.ChunkName , "00db" );				/* stream 0, uncompressed DIB bytes */
+	Avi_StoreU32 ( Chunk.ChunkSize , SizeImage );					/* max size of RGB image */
+	if ( fwrite ( &Chunk , sizeof ( Chunk ) , 1 , pAviParams->FileOut ) != 1 )
+	{
+		perror ( "Avi_RecordVideoStream_BMP" );
+		Log_AlertDlg ( LOG_ERROR, "AVI recording : failed to write bmp frame header" );
+		return false;
+	}
+
+
+	/* Write the video frame data */
+	NeedLock = SDL_MUSTLOCK( pAviParams->Surface );
+
+	/* Points to the top left pixel after cropping borders */
+	/* For BMP format, frame is stored from bottom to top (origin is in bottom left corner) */
+	/* and bytes are in BGR order (not RGB) */
+	pBitmapIn = (Uint8 *)pAviParams->Surface->pixels
+			+ pAviParams->Surface->pitch * ( pAviParams->CropTop + pAviParams->Height )
+			+ pAviParams->CropLeft * pAviParams->Surface->format->BytesPerPixel;
+
+	for ( y=0 ; yHeight ; y++ )
+	{
+		if ( NeedLock )
+			SDL_LockSurface ( pAviParams->Surface );
+
+		pBitmapOut = LineBuf;
+		switch ( pAviParams->Surface->format->BytesPerPixel ) {
+			case 1 :	PixelConvert_8to24Bits_BGR(LineBuf, pBitmapIn, pAviParams->Width, pAviParams->Surface->format->palette->colors);
+					break;
+			case 2 :	PixelConvert_16to24Bits_BGR(LineBuf, (Uint16 *)pBitmapIn, pAviParams->Width, pAviParams->Surface->format);
+					break;
+			case 3 :	PixelConvert_24to24Bits_BGR(LineBuf, pBitmapIn, pAviParams->Width);
+					break;
+			case 4 :	PixelConvert_32to24Bits_BGR(LineBuf, (Uint32 *)pBitmapIn, pAviParams->Width, pAviParams->Surface->format);
+					break;
+		}
+
+		if ( NeedLock )
+			SDL_UnlockSurface ( pAviParams->Surface );
+
+		if ( (int)fwrite ( pBitmapOut , 1 , pAviParams->Width*3 , pAviParams->FileOut ) != pAviParams->Width*3 )
+		{
+			perror ( "Avi_RecordVideoStream_BMP" );
+			Log_AlertDlg ( LOG_ERROR, "AVI recording : failed to write bmp video frame" );
+			return false;
+		}
+
+		pBitmapIn -= pAviParams->Surface->pitch;			/* go from bottom to top */
+	}
+
+	return true;
+}
+
+
+
+#if HAVE_LIBPNG
+static bool	Avi_RecordVideoStream_PNG ( RECORD_AVI_PARAMS *pAviParams )
+{
+	AVI_CHUNK	Chunk;
+	int		SizeImage;
+	long		ChunkPos;
+	Uint8	TempSize[4];
+	
+
+	/* Write the video frame header */
+	ChunkPos = ftell ( pAviParams->FileOut );
+	Avi_Store4cc ( Chunk.ChunkName , "00dc" );				/* stream 0, compressed DIB bytes */
+	Avi_StoreU32 ( Chunk.ChunkSize , 0 );					/* size of PNG image (-> completed later) */
+	if ( fwrite ( &Chunk , sizeof ( Chunk ) , 1 , pAviParams->FileOut ) != 1 )
+		goto png_error;
+
+	/* Write the video frame data */
+	SizeImage = ScreenSnapShot_SavePNG_ToFile ( pAviParams->Surface , pAviParams->FileOut ,
+		pAviParams->VideoCodecCompressionLevel , PNG_FILTER_NONE ,
+		pAviParams->CropLeft , pAviParams->CropRight , pAviParams->CropTop , pAviParams->CropBottom );
+	if ( SizeImage <= 0 )
+		goto png_error;
+	if ( SizeImage & 1 )
+	{
+		SizeImage++;							/* add an extra '\0' byte to get an even size */
+		fputc ( '\0' , pAviParams->FileOut );				/* next chunk must be aligned on 16 bits boundary */
+	}
+
+	/* Update the size of the video chunk */
+	Avi_StoreU32 ( TempSize , SizeImage );
+	if ( fseek ( pAviParams->FileOut , ChunkPos+4 , SEEK_SET ) != 0 )
+		goto png_error;
+	if ( fwrite ( TempSize , sizeof ( TempSize ) , 1 , pAviParams->FileOut ) != 1 )
+		goto png_error;
+
+	/* Go to the end of the video frame data */
+	if ( fseek ( pAviParams->FileOut , 0 , SEEK_END ) != 0 )
+		goto png_error;
+	return true;
+
+png_error:
+	perror ( "Avi_RecordVideoStream_PNG" );
+	Log_AlertDlg ( LOG_ERROR, "AVI recording : failed to write png frame" );
+	return false;
+}
+#endif  /* HAVE_LIBPNG */
+
+
+
+bool	Avi_RecordVideoStream ( void )
+{
+	if ( AviParams.VideoCodec == AVI_RECORD_VIDEO_CODEC_BMP )
+	{
+		if ( Avi_RecordVideoStream_BMP ( &AviParams ) == false )
+		{
+			return false;
+		}
+	}
+#if HAVE_LIBPNG
+	else if ( AviParams.VideoCodec == AVI_RECORD_VIDEO_CODEC_PNG )
+	{
+		if ( Avi_RecordVideoStream_PNG ( &AviParams ) == false )
+		{
+			return false;
+		}
+	}
+#endif
+	else
+	{
+		return false;
+	}
+
+	if (++AviParams.TotalVideoFrames % ( AviParams.Fps / AviParams.Fps_scale ) == 0)
+	{
+		int secs = AviParams.TotalVideoFrames / ( AviParams.Fps / AviParams.Fps_scale );
+		char str[6] = "00:00";
+		str[0] = '0' + (secs / 60) / 10;
+		str[1] = '0' + (secs / 60) % 10;
+		str[3] = '0' + (secs % 60) / 10;
+		str[4] = '0' + (secs % 60) % 10;
+		Main_SetTitle(str);
+	}
+	return true;
+}
+
+
+
+static bool	Avi_RecordAudioStream_PCM ( RECORD_AVI_PARAMS *pAviParams , Sint16 pSamples[][2] , int SampleIndex , int SampleLength )
+{
+	AVI_CHUNK	Chunk;
+	Sint16		sample[2];
+	int		i;
+
+	/* Write the audio frame header */
+	Avi_Store4cc ( Chunk.ChunkName , "01wb" );				/* stream 1, wave bytes */
+	Avi_StoreU32 ( Chunk.ChunkSize , SampleLength * 4 );			/* 16 bits, stereo -> 4 bytes */
+	if ( fwrite ( &Chunk , sizeof ( Chunk ) , 1 , pAviParams->FileOut ) != 1 )
+	{
+		perror ( "Avi_RecordAudioStream_PCM" );
+		Log_AlertDlg ( LOG_ERROR, "AVI recording : failed to write pcm frame header" );
+		return false;
+	}
+
+	/* Write the audio frame data */
+	for ( i = 0 ; i < SampleLength; i++ )
+	{
+		/* Convert sample to little endian */
+		sample[0] = SDL_SwapLE16 ( pSamples[ (SampleIndex+i) % MIXBUFFER_SIZE ][0]);
+		sample[1] = SDL_SwapLE16 ( pSamples[ (SampleIndex+i) % MIXBUFFER_SIZE ][1]);
+		/* And store */
+		if ( fwrite ( &sample , sizeof ( sample ) , 1 , pAviParams->FileOut ) != 1 )
+		{
+			perror ( "Avi_RecordAudioStream_PCM" );
+			Log_AlertDlg ( LOG_ERROR, "AVI recording : failed to write pcm frame" );
+			return false;
+		}
+	}
+
+	return true;
+}
+
+
+
+bool	Avi_RecordAudioStream ( Sint16 pSamples[][2] , int SampleIndex , int SampleLength )
+{
+	if ( AviParams.AudioCodec == AVI_RECORD_AUDIO_CODEC_PCM )
+	{
+		if ( Avi_RecordAudioStream_PCM ( &AviParams , pSamples , SampleIndex , SampleLength ) == false )
+		{
+			return false;
+		}
+	}
+	else
+	{
+		return false;
+	}
+
+	AviParams.TotalAudioSamples += SampleLength;
+	return true;
+}
+
+
+
+
+static void	Avi_BuildFileHeader ( RECORD_AVI_PARAMS *pAviParams , AVI_FILE_HEADER *pAviFileHeader )
+{
+	int	Width , Height , BitCount , Fps , Fps_scale , SizeImage;
+	int	AudioFreq;
+
+	memset ( pAviFileHeader , 0 , sizeof ( *pAviFileHeader ) );
+
+	Width = pAviParams->Width;
+	Height =pAviParams->Height;
+	BitCount = pAviParams->BitCount;
+	Fps = pAviParams->Fps;
+	Fps_scale = pAviParams->Fps_scale;
+	AudioFreq = pAviParams->AudioFreq;
+
+	SizeImage = 0;
+	if ( pAviParams->VideoCodec == AVI_RECORD_VIDEO_CODEC_BMP )
+		SizeImage = Avi_GetBmpSize ( Width , Height , BitCount );		/* size of a BMP image */
+	else if ( pAviParams->VideoCodec == AVI_RECORD_VIDEO_CODEC_PNG )
+		SizeImage = Avi_GetBmpSize ( Width , Height , BitCount );		/* max size of a PNG image */
+
+
+	/* RIFF / AVI headers */
+	Avi_Store4cc ( pAviFileHeader->RiffHeader.signature , "RIFF" );
+	Avi_StoreU32 ( pAviFileHeader->RiffHeader.filesize , 0 );				/* total file size (-> completed later) */
+	Avi_Store4cc ( pAviFileHeader->RiffHeader.type , "AVI " );
+
+	Avi_Store4cc ( pAviFileHeader->AviHeader.ChunkName , "LIST" );
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.ChunkSize , sizeof ( AVI_STREAM_LIST_AVIH )
+		+ sizeof ( AVI_STREAM_LIST_VIDS ) + sizeof ( AVI_STREAM_LIST_AUDS ) - 8 );
+	Avi_Store4cc ( pAviFileHeader->AviHeader.Name , "hdrl" );
+
+	Avi_Store4cc ( pAviFileHeader->AviHeader.Header.ChunkName , "avih" );
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.ChunkSize , sizeof ( AVI_STREAM_AVIH ) - 8 );
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.microsec_per_frame , (Uint32)( ( 1000000 * (Sint64)Fps_scale ) / Fps ) );
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.max_bytes_per_second , (Uint32)( ( (Sint64)SizeImage * Fps ) / Fps_scale + AudioFreq * 4 ) );
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.padding_granularity , 0 );
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.flags , AVIF_HASINDEX | AVIF_ISINTERLEAVED | AVIF_TRUSTCKTYPE );
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.total_frames , 0 );			/* number of video frames (-> completed later) */
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.init_frame , 0 );
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.nb_streams , 2 );			/* 1 video and 1 audio */
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.buffer_size , SizeImage );
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.width , Width );
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.height , Height );
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.scale , 0 );				/* reserved */
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.rate , 0 );				/* reserved */
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.start , 0 );				/* reserved */
+	Avi_StoreU32 ( pAviFileHeader->AviHeader.Header.length , 0 );				/* reserved */
+
+
+	/* Video Stream */
+	Avi_Store4cc ( pAviFileHeader->VideoStream.ChunkName , "LIST" );
+	Avi_StoreU32 ( pAviFileHeader->VideoStream.ChunkSize , sizeof ( AVI_STREAM_LIST_VIDS ) - 8 );
+	Avi_Store4cc ( pAviFileHeader->VideoStream.Name , "strl" );
+
+	Avi_Store4cc ( pAviFileHeader->VideoStream.Header.ChunkName , "strh" );
+	Avi_StoreU32 ( pAviFileHeader->VideoStream.Header.ChunkSize , sizeof ( AVI_STREAM_HEADER ) - 8 );
+	Avi_Store4cc ( pAviFileHeader->VideoStream.Header.stream_type , "vids" );
+	if ( pAviParams->VideoCodec == AVI_RECORD_VIDEO_CODEC_BMP )
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Header.stream_handler , VIDEO_STREAM_RGB );
+	else if ( pAviParams->VideoCodec == AVI_RECORD_VIDEO_CODEC_PNG )
+		Avi_Store4cc ( pAviFileHeader->VideoStream.Header.stream_handler , VIDEO_STREAM_PNG );
+	Avi_StoreU32 ( pAviFileHeader->VideoStream.Header.flags , 0 );
+	Avi_StoreU16 ( pAviFileHeader->VideoStream.Header.priority , 0 );
+	Avi_StoreU16 ( pAviFileHeader->VideoStream.Header.language , 0 );
+	Avi_StoreU32 ( pAviFileHeader->VideoStream.Header.initial_frames , 0 );
+	Avi_StoreU32 ( pAviFileHeader->VideoStream.Header.time_scale , Fps_scale );
+	Avi_StoreU32 ( pAviFileHeader->VideoStream.Header.data_rate , Fps );
+	Avi_StoreU32 ( pAviFileHeader->VideoStream.Header.start_time , 0 );
+	Avi_StoreU32 ( pAviFileHeader->VideoStream.Header.data_length , 0 );			/* number of video frames (-> completed later) */
+	Avi_StoreU32 ( pAviFileHeader->VideoStream.Header.buffer_size , SizeImage );		/* size of an uncompressed frame */
+	Avi_StoreU32 ( pAviFileHeader->VideoStream.Header.quality , -1 );			/* use default quality */
+	Avi_StoreU32 ( pAviFileHeader->VideoStream.Header.sample_size , 0 );			/* 0 for video */
+	Avi_StoreU16 ( pAviFileHeader->VideoStream.Header.dest_left , 0 );
+	Avi_StoreU16 ( pAviFileHeader->VideoStream.Header.dest_top , 0 );
+	Avi_StoreU16 ( pAviFileHeader->VideoStream.Header.dest_right , Width );
+	Avi_StoreU16 ( pAviFileHeader->VideoStream.Header.dest_bottom , Height );
+
+	Avi_Store4cc ( pAviFileHeader->VideoStream.Format.ChunkName , "strf" );
+	Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.ChunkSize , sizeof ( AVI_STREAM_FORMAT_VIDS ) - 8 );
+	if ( pAviParams->VideoCodec == AVI_RECORD_VIDEO_CODEC_BMP )
+	{
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.size , sizeof ( AVI_STREAM_FORMAT_VIDS ) - 8 );
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.width , Width );
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.height , Height );
+		Avi_StoreU16 ( pAviFileHeader->VideoStream.Format.planes , 1 );			/* always 1 */
+		Avi_StoreU16 ( pAviFileHeader->VideoStream.Format.bit_count , BitCount );
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.compression , VIDEO_STREAM_RGB );
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.size_image , SizeImage );
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.xpels_meter , 0 );
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.ypels_meter , 0 );
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.clr_used , 0 );		/* no color map */
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.clr_important , 0 );		/* no color map */
+	}
+	else if ( pAviParams->VideoCodec == AVI_RECORD_VIDEO_CODEC_PNG )
+	{
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.size , sizeof ( AVI_STREAM_FORMAT_VIDS ) - 8 );
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.width , Width );
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.height , Height );
+		Avi_StoreU16 ( pAviFileHeader->VideoStream.Format.planes , 1 );			/* always 1 */
+		Avi_StoreU16 ( pAviFileHeader->VideoStream.Format.bit_count , BitCount );
+		Avi_Store4cc ( pAviFileHeader->VideoStream.Format.compression , VIDEO_STREAM_PNG );
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.size_image , SizeImage );	/* max size if uncompressed */
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.xpels_meter , 0 );
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.ypels_meter , 0 );
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.clr_used , 0 );		/* no color map */
+		Avi_StoreU32 ( pAviFileHeader->VideoStream.Format.clr_important , 0 );		/* no color map */
+	}
+
+
+	/* Audio Stream */
+	Avi_Store4cc ( pAviFileHeader->AudioStream.ChunkName , "LIST" );
+	Avi_StoreU32 ( pAviFileHeader->AudioStream.ChunkSize , sizeof ( AVI_STREAM_LIST_AUDS ) - 8 );
+	Avi_Store4cc ( pAviFileHeader->AudioStream.Name , "strl" );
+
+	Avi_Store4cc ( pAviFileHeader->AudioStream.Header.ChunkName , "strh" );
+	Avi_StoreU32 ( pAviFileHeader->AudioStream.Header.ChunkSize , sizeof ( AVI_STREAM_HEADER ) - 8 );
+	Avi_Store4cc ( pAviFileHeader->AudioStream.Header.stream_type , "auds" );
+	Avi_StoreU32 ( pAviFileHeader->AudioStream.Header.stream_handler , 0 );			/* not used (or could be 1 for pcm ?) */
+	Avi_StoreU32 ( pAviFileHeader->AudioStream.Header.flags , 0 );
+	Avi_StoreU16 ( pAviFileHeader->AudioStream.Header.priority , 0 );
+	Avi_StoreU16 ( pAviFileHeader->AudioStream.Header.language , 0 );
+	Avi_StoreU32 ( pAviFileHeader->AudioStream.Header.initial_frames , 0 );			/* should be 1 in interleaved ? */
+	Avi_StoreU32 ( pAviFileHeader->AudioStream.Header.time_scale , 1 );
+	Avi_StoreU32 ( pAviFileHeader->AudioStream.Header.data_rate , AudioFreq );
+	Avi_StoreU32 ( pAviFileHeader->AudioStream.Header.start_time , 0 );
+	Avi_StoreU32 ( pAviFileHeader->AudioStream.Header.data_length , 0 );			/* number of audio samples (-> completed later) */
+	Avi_StoreU32 ( pAviFileHeader->AudioStream.Header.buffer_size , AudioFreq * 4 / 50 );	/* min VBL freq is 50 Hz */
+	Avi_StoreU32 ( pAviFileHeader->AudioStream.Header.quality , -1 );			/* use default quality */
+	Avi_StoreU32 ( pAviFileHeader->AudioStream.Header.sample_size , 4 );			/* 2 bytes, stereo */
+	Avi_StoreU16 ( pAviFileHeader->AudioStream.Header.dest_left , 0 );
+	Avi_StoreU16 ( pAviFileHeader->AudioStream.Header.dest_top , 0 );
+	Avi_StoreU16 ( pAviFileHeader->AudioStream.Header.dest_right , 0 );
+	Avi_StoreU16 ( pAviFileHeader->AudioStream.Header.dest_bottom , 0 );
+
+	Avi_Store4cc ( pAviFileHeader->AudioStream.Format.ChunkName , "strf" );
+	Avi_StoreU32 ( pAviFileHeader->AudioStream.Format.ChunkSize , sizeof ( AVI_STREAM_FORMAT_AUDS ) - 8 );
+	if ( pAviParams->AudioCodec == AVI_RECORD_AUDIO_CODEC_PCM )				/* 16 bits stereo pcm */
+	{
+		Avi_StoreU16 ( pAviFileHeader->AudioStream.Format.codec , AUDIO_STREAM_WAVE_FORMAT_PCM );	/* 0x0001 */
+		Avi_StoreU16 ( pAviFileHeader->AudioStream.Format.channels , 2 );
+		Avi_StoreU32 ( pAviFileHeader->AudioStream.Format.sample_rate , AudioFreq );
+		Avi_StoreU32 ( pAviFileHeader->AudioStream.Format.bit_rate , AudioFreq * 2 * 2 );	/* 2 channels * 2 bytes */
+		Avi_StoreU16 ( pAviFileHeader->AudioStream.Format.block_align , 4 );
+		Avi_StoreU16 ( pAviFileHeader->AudioStream.Format.bits_per_sample , 16 );
+		Avi_StoreU16 ( pAviFileHeader->AudioStream.Format.ext_size , 0 );
+	}
+}
+
+
+static bool	Avi_BuildIndex ( RECORD_AVI_PARAMS *pAviParams )
+{
+	AVI_CHUNK	Chunk;
+	long		IndexChunkPosStart;
+	long		Pos , PosWrite;
+	Uint8		TempSize[4];
+	AVI_CHUNK_INDEX	ChunkIndex;
+	Uint32		Size;
+
+	if (fseek(pAviParams->FileOut, 0, SEEK_END) != 0)			/* go to the end of the file */
+		goto index_error;
+
+	/* Write the 'idx1' chunk header */
+	IndexChunkPosStart = ftell ( pAviParams->FileOut );
+	Avi_Store4cc ( Chunk.ChunkName , "idx1" );				/* stream 0, uncompressed DIB bytes */
+	Avi_StoreU32 ( Chunk.ChunkSize , 0 );					/* index size (-> completed later) */
+	if ( fwrite ( &Chunk , sizeof ( Chunk ) , 1 , pAviParams->FileOut ) != 1 )
+		goto index_error;
+	PosWrite = ftell ( pAviParams->FileOut );				/* position to start writing indexes */
+
+	/* Go to the first data chunk in the 'movi' chunk */
+	if (fseek(pAviParams->FileOut, pAviParams->MoviChunkPosStart + sizeof(AVI_STREAM_LIST_MOVI), SEEK_SET) != 0)
+		goto index_error;
+	Pos = ftell ( pAviParams->FileOut );
+
+	/* Build the index : we seek/read one data chunk and seek/write the */
+	/* corresponding infos at the end of the index, until we reach the */
+	/* end of the 'movi' chunk. */
+	while ( Pos < pAviParams->MoviChunkPosEnd )
+	{
+		/* Read the header for this data chunk: ChunkName and ChunkSize */
+		if (fread(&Chunk, sizeof(Chunk), 1, pAviParams->FileOut) != 1)
+			goto index_error;
+		Size = Avi_ReadU32 ( Chunk.ChunkSize );
+
+		/* Write the index infos for this chunk */
+		if (fseek(pAviParams->FileOut, PosWrite, SEEK_SET) != 0)
+			goto index_error;
+		Avi_Store4cc ( ChunkIndex.identifier , (char *)Chunk.ChunkName );	/* 00dc, 00db, 01wb, ... */
+		Avi_StoreU32 ( ChunkIndex.flags , AVIIF_KEYFRAME );		/* AVIIF_KEYFRAME */
+		Avi_StoreU32 ( ChunkIndex.offset , Pos - pAviParams->MoviChunkPosStart - 8  );	/* pos relative to 'movi' */
+		Avi_StoreU32 ( ChunkIndex.length , Size );
+		if (fwrite ( &ChunkIndex , sizeof ( ChunkIndex ) , 1 , pAviParams->FileOut ) != 1)
+			goto index_error;
+		PosWrite = ftell ( pAviParams->FileOut );			/* position for the next index */
+
+		/* Go to the next data chunk in the 'movi' chunk */
+		Pos = Pos + sizeof ( Chunk ) + Size;				/* position of the next data chunk */
+		if (fseek(pAviParams->FileOut, Pos, SEEK_SET) != 0)
+			goto index_error;
+	}
+
+	/* Update the size of the 'idx1' chunk */
+	Avi_StoreU32 ( TempSize , PosWrite - IndexChunkPosStart - 8 );
+	if ( fseek ( pAviParams->FileOut , IndexChunkPosStart+4 , SEEK_SET ) != 0 )
+		goto index_error;
+	if ( fwrite ( TempSize , sizeof ( TempSize ) , 1 , pAviParams->FileOut ) != 1 )
+		goto index_error;
+	return true;
+
+index_error:
+	perror ( "Avi_BuildIndex" );
+	Log_AlertDlg ( LOG_ERROR, "AVI recording : failed to create index header" );
+	return false;
+}
+
+
+static bool	Avi_StartRecording_WithParams ( RECORD_AVI_PARAMS *pAviParams , char *AviFileName )
+{
+	AVI_STREAM_LIST_INFO	ListInfo;
+	char			InfoString[ 100 ];
+	int			Len , Len_rounded;
+	AVI_STREAM_LIST_MOVI	ListMovi;
+
+
+	if ( bRecordingAvi == true )						/* already recording ? */
+		return false;
+
+	/* Compute some video parameters */
+	pAviParams->Width = pAviParams->Surface->w - pAviParams->CropLeft - pAviParams->CropRight;
+	pAviParams->Height = pAviParams->Surface->h - pAviParams->CropTop - pAviParams->CropBottom;
+	pAviParams->BitCount = 24;
+	
+#if !HAVE_LIBPNG
+	if ( pAviParams->VideoCodec == AVI_RECORD_VIDEO_CODEC_PNG )
+	{
+		perror ( "AviStartRecording" );
+		Log_AlertDlg ( LOG_ERROR, "AVI recording : Hatari was not built with libpng support" );
+		return false;
+	}
+#endif
+
+	/* Open the file */
+	pAviParams->FileOut = fopen ( AviFileName , "wb+" );
+	if ( !pAviParams->FileOut )
+	{
+		perror ( "AviStartRecording" );
+		Log_AlertDlg ( LOG_ERROR, "AVI recording : failed to open file" );
+		return false;
+	}
+
+	/* Build the AVI header */
+	Avi_BuildFileHeader ( pAviParams , &AviFileHeader );
+	
+	/* Write the AVI header */
+	if ( fwrite ( &AviFileHeader , sizeof ( AviFileHeader ) , 1 , pAviParams->FileOut ) != 1 )
+	{
+		perror ( "AviStartRecording" );
+		Log_AlertDlg ( LOG_ERROR, "AVI recording : failed to write avi header" );
+		return false;
+	}
+
+	/* Write the INFO header */
+	memset ( InfoString , 0 , sizeof ( InfoString ) );
+	Len = snprintf ( InfoString , sizeof ( InfoString ) , "%s - the Atari ST, STE, TT and Falcon emulator" , PROG_NAME ) + 1;
+	Len_rounded = Len + ( Len % 2 == 0 ? 0 : 1 );				/* round Len to the next multiple of 2 */
+	Avi_Store4cc ( ListInfo.ChunkName , "LIST" );
+	Avi_StoreU32 ( ListInfo.ChunkSize , sizeof ( AVI_STREAM_LIST_INFO ) - 8 + Len_rounded );
+	Avi_Store4cc ( ListInfo.Name , "INFO" );
+	Avi_Store4cc ( ListInfo.Info.ChunkName , "ISFT" );
+	Avi_StoreU32 ( ListInfo.Info.ChunkSize , Len );
+	if ( fwrite ( &ListInfo , sizeof ( ListInfo ) , 1 , pAviParams->FileOut ) != 1 )
+	{
+		perror ( "AviStartRecording" );
+		Log_AlertDlg ( LOG_ERROR, "AVI recording : failed to write info header" );
+		return false;
+	}
+	/* Write the info string + '\0' and write an optional extra '\0' byte to get a total multiple of 2 */
+	if ( fwrite ( InfoString , Len_rounded , 1 , pAviParams->FileOut ) != 1 )
+	{
+		perror ( "AviStartRecording" );
+		Log_AlertDlg ( LOG_ERROR, "AVI recording : failed to write info header" );
+		return false;
+	}
+
+	/* Write the MOVI header */
+	Avi_Store4cc ( ListMovi.ChunkName , "LIST" );
+	Avi_StoreU32 ( ListMovi.ChunkSize , 0 );					/* completed when recording stops */
+	Avi_Store4cc ( ListMovi.Name , "movi" );
+	pAviParams->MoviChunkPosStart = ftell ( pAviParams->FileOut );
+	if ( fwrite ( &ListMovi , sizeof ( ListMovi ) , 1 , pAviParams->FileOut ) != 1 )
+	{
+		perror ( "AviStartRecording" );
+		Log_AlertDlg ( LOG_ERROR, "AVI recording : failed to write movi header" );
+		return false;
+	}
+
+
+	/* We're ok to record */
+	Log_AlertDlg ( LOG_INFO, "AVI recording has been started");
+	bRecordingAvi = true;
+
+	return true;
+}
+
+
+
+static bool	Avi_StopRecording_WithParams ( RECORD_AVI_PARAMS *pAviParams )
+{
+	long	FileSize;
+	Uint8	TempSize[4];
+
+
+	if ( bRecordingAvi == false )						/* no recording ? */
+		return true;
+
+	/* Update the size of the 'movi' chunk */
+	if (fseek(pAviParams->FileOut, 0, SEEK_END) != 0)			/* go to the end of the 'movi' chunk */
+		goto stoprec_error;
+	pAviParams->MoviChunkPosEnd = ftell ( pAviParams->FileOut );
+	Avi_StoreU32 ( TempSize , pAviParams->MoviChunkPosEnd - pAviParams->MoviChunkPosStart - 8 );
+
+	if ( fseek ( pAviParams->FileOut , pAviParams->MoviChunkPosStart+4 , SEEK_SET ) != 0 )
+		goto stoprec_error;
+	if ( fwrite ( TempSize , sizeof ( TempSize ) , 1 , pAviParams->FileOut ) != 1 )
+		goto stoprec_error;
+
+	/* Build the index chunk */
+	if ( ! Avi_BuildIndex ( pAviParams ) )
+	{
+		perror ( "AviStopRecording" );
+		Log_AlertDlg ( LOG_ERROR, "AVI recording : failed to build index" );
+		return false;
+	}
+
+	/* Update the avi header (file size, number of output frames, ...) */
+	if (fseek(pAviParams->FileOut, 0, SEEK_END) != 0)			/* go to the end of the file */
+		goto stoprec_error;
+	FileSize = ftell ( pAviParams->FileOut );
+
+	Avi_StoreU32 ( AviFileHeader.RiffHeader.filesize , FileSize - 8 );	/* 32 bits, limited to 4GB */
+	Avi_StoreU32 ( AviFileHeader.AviHeader.Header.total_frames , pAviParams->TotalVideoFrames );	/* number of video frames */
+	Avi_StoreU32 ( AviFileHeader.VideoStream.Header.data_length , pAviParams->TotalVideoFrames );	/* number of video frames */
+	Avi_StoreU32 ( AviFileHeader.AudioStream.Header.data_length , pAviParams->TotalAudioSamples );	/* number of audio samples */
+
+	if ( fseek ( pAviParams->FileOut , 0 , SEEK_SET ) != 0 )
+		goto stoprec_error;
+	if ( fwrite ( &AviFileHeader , sizeof ( AviFileHeader ) , 1 , pAviParams->FileOut ) != 1 )
+		goto stoprec_error;
+
+	/* Close the file */
+	fclose ( pAviParams->FileOut );
+
+	Log_AlertDlg ( LOG_INFO, "AVI recording has been stopped");
+	bRecordingAvi = false;
+
+	return true;
+
+stoprec_error:
+	fclose (pAviParams->FileOut);
+	perror("AviStopRecording");
+	Log_AlertDlg(LOG_ERROR, "AVI recording : failed to update header");
+	return false;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Are we recording an AVI ?
+ */
+bool	Avi_AreWeRecording ( void )
+{
+        return bRecordingAvi;
+}
+
+
+/* PNG compression level, 0-9 */
+static int compression_level = 9;
+
+/**
+ * Set recording level from given string
+ * return true for valid, false for invalid value
+ */
+bool Avi_SetCompressionLevel(const char *str)
+{
+	char *end;
+	long level = strtol(str, &end, 10);
+	if (*end)
+		return false;
+	if (level < 0 || level > 9)
+		return false;
+	compression_level = level;
+	return true;
+}
+
+
+bool	Avi_StartRecording ( char *FileName , bool CropGui , Uint32 Fps , Uint32 Fps_scale , int VideoCodec )
+{
+	memset ( &AviParams , 0 , sizeof ( AviParams ) );
+
+	AviParams.VideoCodec = VideoCodec;
+	AviParams.VideoCodecCompressionLevel = compression_level;
+	AviParams.AudioCodec = AVI_RECORD_AUDIO_CODEC_PCM;
+	AviParams.AudioFreq = ConfigureParams.Sound.nPlaybackFreq;
+	AviParams.Surface = sdlscrn;
+
+	/* Some video players (quicktime, ...) don't support a value of Fps_scale */
+	/* above 100000. So we decrease the precision from << 24 to << 16 for Fps and Fps_scale */
+	AviParams.Fps = Fps >> 8;			/* refresh rate << 16 */
+	AviParams.Fps_scale = Fps_scale >> 8;		/* 1 << 16 */
+
+	if ( !CropGui )					/* Keep gui's status bar */
+	{
+		AviParams.CropLeft = 0;
+		AviParams.CropRight = 0;
+		AviParams.CropTop = 0;
+		AviParams.CropBottom = 0;
+	}
+	else						/* Record only the content of the Atari's screen */
+	{
+		AviParams.CropLeft = 0;
+		AviParams.CropRight = 0;
+		AviParams.CropTop = 0;
+		AviParams.CropBottom = Statusbar_GetHeight();
+	}
+	
+	
+	if (Avi_StartRecording_WithParams ( &AviParams , FileName ))
+	{
+		Main_SetTitle("00:00");
+		return true;
+	}
+	return false;
+}
+
+
+bool	Avi_StopRecording ( void )
+{
+	if (Avi_StopRecording_WithParams ( &AviParams ))
+	{
+		Main_SetTitle(NULL);
+		return true;
+	}
+	return false;
+}
+
+
diff --git a/src/bios.c b/src/bios.c
new file mode 100644
index 0000000..1a82814
--- /dev/null
+++ b/src/bios.c
@@ -0,0 +1,192 @@
+/*
+  Hatari - bios.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Bios Handler (Trap #13)
+
+  Intercept some Bios calls for tracing/debugging
+*/
+const char Bios__fileid[] = "Hatari bios.c : " __DATE__ " " __TIME__;
+
+#include "main.h"
+#include "configuration.h"
+#include "floppy.h"
+#include "log.h"
+#include "m68000.h"
+#include "printer.h"
+#include "rs232.h"
+#include "stMemory.h"
+#include "bios.h"
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * BIOS Read/Write disk sector
+ * Call 4
+ */
+static void Bios_RWabs(Uint32 Params)
+{
+#if ENABLE_TRACING
+	Uint32 pBuffer;
+	Uint16 RWFlag, Number, RecNo, Dev;
+
+	/* Read details from stack */
+	RWFlag = STMemory_ReadWord(Params);
+	pBuffer = STMemory_ReadLong(Params+SIZE_WORD);
+	Number = STMemory_ReadWord(Params+SIZE_WORD+SIZE_LONG);
+	RecNo = STMemory_ReadWord(Params+SIZE_WORD+SIZE_LONG+SIZE_WORD);
+	Dev = STMemory_ReadWord(Params+SIZE_WORD+SIZE_LONG+SIZE_WORD+SIZE_WORD);
+
+	LOG_TRACE(TRACE_OS_BIOS, "BIOS 0x04 Rwabs(%d,0x%x,%d,%d,%i) at PC 0x%X\n",
+	          RWFlag, pBuffer, Number, RecNo, Dev,
+		  M68000_GetPC());
+#endif
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * BIOS Set/query exception vectors
+ * Call 5
+ */
+static void Bios_Setexe(Uint32 Params)
+{
+#if ENABLE_TRACING
+	Uint16 vec = STMemory_ReadWord(Params);
+	Uint32 addr = STMemory_ReadLong(Params+SIZE_WORD);
+	struct {
+		int vec;
+		const char *name;
+	} *vecname, vecnames[] =
+	{
+		{ 0x002, "BUSERROR" },
+		{ 0x003, "ADDRESSERROR" },
+		{ 0x004, "ILLEGALINSTRUCTION" },
+		{ 0x021, "GEMDOS" },
+		{ 0x022, "GEM" },
+		{ 0x02D, "BIOS" },
+		{ 0x02E, "XBIOS" },
+		{ 0x100, "TIMER" },
+		{ 0x101, "CRITICALERROR" },
+		{ 0x102, "TERMINATE" },
+		{ 0x000, "???" }
+	};
+	for (vecname = &(vecnames[0]); vecname->vec && vec != vecname->vec; vecname++)
+		;
+	LOG_TRACE(TRACE_OS_BIOS, "BIOS 0x05 Setexc(0x%hX VEC_%s, 0x%X) at PC 0x%X\n", vec, vecname->name, addr,
+		  M68000_GetPC());
+#endif
+}
+
+
+/*-----------------------------------------------------------------------*/
+
+#if ENABLE_TRACING
+/**
+ * Map BIOS call opcode to BIOS function name
+ */
+static const char* Bios_Call2Name(Uint16 opcode)
+{
+	/* GCC uses substrings from above trace statements
+	 * where they match, so having them again here
+	 * wastes only a pointer & simplifies things
+	 */
+	static const char* names[] = {
+		"Getmpb", "Bconstat","Bconin", "Bconout",
+		"Rwabs",  "Setexc",  "Tickcal","Getbpb",
+		"Bcostat","Mediach", "Drvmap", "Kbshift"
+	};
+	if (opcode < ARRAYSIZE(names) && names[opcode]) {
+		return names[opcode];
+	}
+	return "???";
+}
+
+void Bios_Info(FILE *fp, Uint32 dummy)
+{
+	Uint16 opcode;
+	for (opcode = 0; opcode <= 0xB; ) {
+		fprintf(fp, "%02x %-9s", opcode,
+			Bios_Call2Name(opcode));
+		if (++opcode % 6 == 0) {
+			fputs("\n", fp);
+		}
+	}
+}
+#else /* !ENABLE_TRACING */
+void Bios_Info(FILE *fp, Uint32 bShowOpcodes)
+{
+	        fputs("Hatari isn't configured with ENABLE_TRACING\n", fp);
+}
+#endif /* !ENABLE_TRACING */
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Check Bios call and see if we need to re-direct to our own routines.
+ * Return true if we've handled the exception, else return false to let
+ * TOS attempt it
+ */
+bool Bios(void)
+{
+	Uint32 Params;
+	Uint16 BiosCall;
+
+	/* Get call */
+	Params = Regs[REG_A7];
+	BiosCall = STMemory_ReadWord(Params);
+	Params += SIZE_WORD;
+
+	/* Intercept? */
+	switch(BiosCall)
+	{
+	case 0x0:
+		LOG_TRACE(TRACE_OS_BIOS, "BIOS 0x00 Getmpb(0x%X) at PC 0x%X\n",
+			  STMemory_ReadLong(Params),
+			  M68000_GetPC());
+		break;
+
+	case 0x3:
+		LOG_TRACE(TRACE_OS_BIOS, "BIOS 0x03 Bconout(%i, 0x%02hX) at PC 0x%X\n",
+			  STMemory_ReadWord(Params),
+			  STMemory_ReadWord(Params+SIZE_WORD),
+			  M68000_GetPC());
+		break;
+
+	case 0x4:
+		Bios_RWabs(Params);
+		break;
+
+	case 0x5:
+		Bios_Setexe(Params);
+		break;
+
+	case 0x1:
+	case 0x2:
+	case 0x7:
+	case 0x8:
+	case 0x9:
+	case 0xB:
+		/* commands taking a single word */
+		LOG_TRACE(TRACE_OS_BIOS, "BIOS 0x%02hX %s(0x%hX) at PC 0x%X\n",
+			  BiosCall, Bios_Call2Name(BiosCall),
+			  STMemory_ReadWord(Params),
+			  M68000_GetPC());
+		break;
+
+	case 0x6:
+	case 0xA:
+		/* commands taking no args */
+		LOG_TRACE(TRACE_OS_BIOS, "BIOS 0x%02hX %s() at PC 0x%X\n",
+			  BiosCall, Bios_Call2Name(BiosCall),
+			  M68000_GetPC());
+		break;
+
+	default:
+		Log_Printf(LOG_WARN, "Unknown BIOS call 0x%x! at PC 0x%X\n", BiosCall,
+			   M68000_GetPC());
+		break;
+	}
+	return false;
+}
diff --git a/src/blitter.c b/src/blitter.c
new file mode 100644
index 0000000..be7afab
--- /dev/null
+++ b/src/blitter.c
@@ -0,0 +1,1074 @@
+/*
+ * Hatari - blitter.c
+ *
+ * This file is distributed under the GNU General Public License, version 2
+ * or at your option any later version. Read the file gpl.txt for details.
+ *
+ * Blitter emulation. The 'Blitter' chip is found in the Mega-ST, STE/Mega-STE
+ * and Falcon. It provides a very fast BitBlit function in hardware.
+ *
+ * This file has originally been taken from STonX, but it has been completely
+ * modified for better maintainability and higher compatibility.
+ *
+ * NOTES:
+ * ----------------------------------------------------------------------------
+ * Strange end mask condition ((~(0xffff>>skew)) > end_mask_1)
+ *
+ * """Similarly the  NFSR (aka  post-flush) bit, when set, will prevent the last
+ * source read of the  line. This read  may not  be necessary  with certain
+ * combinations of end masks and skews."""
+ *     - doesn't mean the blitter will skip source read by itself, just a hint
+ *       for developers as far as i understand it.
+ * ----------------------------------------------------------------------------
+ * Does smudge mode change the line register ?
+ * ----------------------------------------------------------------------------
+ */
+
+const char Blitter_fileid[] = "Hatari blitter.c : " __DATE__ " " __TIME__;
+
+#include 
+#include 
+#include 
+
+#include "main.h"
+#include "blitter.h"
+#include "configuration.h"
+#include "dmaSnd.h"
+#include "ioMem.h"
+#include "m68000.h"
+#include "mfp.h"
+#include "memorySnapShot.h"
+#include "stMemory.h"
+#include "screen.h"
+#include "video.h"
+
+/* Cycles to run for in non-hog mode */
+#define NONHOG_CYCLES	(64*4)
+
+/* BLiTTER registers, incs are signed, others unsigned */
+#define REG_HT_RAM		0xff8a00	/* - 0xff8a1e */
+
+#define REG_SRC_X_INC	0xff8a20
+#define REG_SRC_Y_INC	0xff8a22
+#define REG_SRC_ADDR	0xff8a24
+
+#define REG_END_MASK1	0xff8a28
+#define REG_END_MASK2	0xff8a2a
+#define REG_END_MASK3	0xff8a2c
+
+#define REG_DST_X_INC	0xff8a2e
+#define REG_DST_Y_INC	0xff8a30
+#define REG_DST_ADDR	0xff8a32
+
+#define REG_X_COUNT 	0xff8a36
+#define REG_Y_COUNT 	0xff8a38
+
+#define REG_BLIT_HOP	0xff8a3a	/* halftone blit operation byte */
+#define REG_BLIT_LOP	0xff8a3b	/* logical blit operation byte */
+#define REG_CONTROL 	0xff8a3c
+#define REG_SKEW		0xff8a3d
+
+
+#define	BLITTER_READ_WORD_BUS_ERR	0x0000	/* This value is returned when the blitter try to read a word */
+						/* in a region that would cause a bus error */
+						/* [NP] FIXME : for now we return a constant, but it should depend on the bus activity */
+
+/* Blitter registers */
+typedef struct
+{
+	Uint32	src_addr;
+	Uint32	dst_addr;
+	Uint32	words;
+	Uint32	lines;
+	short	src_x_incr;
+	short	src_y_incr;
+	short	dst_x_incr;
+	short	dst_y_incr;
+	Uint16	end_mask_1;
+	Uint16	end_mask_2;
+	Uint16	end_mask_3;
+	Uint8	hop;
+	Uint8	lop;
+	Uint8	ctrl;
+	Uint8	skew;
+} BLITTERREGS;
+
+/* Blitter vars */
+typedef struct
+{
+	int		pass_cycles;
+	int		op_cycles;
+	Uint32	buffer;
+	Uint32	src_words_reset;
+	Uint32	dst_words_reset;
+	Uint32	src_words;
+	Uint8	hog;
+	Uint8	smudge;
+	Uint8	line;
+	Uint8	fxsr;
+	Uint8	nfsr;
+	Uint8	skew;
+} BLITTERVARS;
+
+/* Blitter state */
+typedef struct
+{
+	Uint16	src_word;
+	Uint16	dst_word;
+	Uint16	end_mask;
+	Uint8	have_src;
+	Uint8	have_dst;
+	Uint8	fxsr;
+	Uint8	nfsr;
+} BLITTERSTATE;
+
+/* Blitter logical op func */
+typedef Uint16 (*BLITTER_OP_FUNC)(void);
+
+static BLITTERREGS	BlitterRegs;
+static BLITTERVARS	BlitterVars;
+static BLITTERSTATE	BlitterState;
+static Uint16		BlitterHalftone[16];
+
+static BLITTER_OP_FUNC Blitter_ComputeHOP;
+static BLITTER_OP_FUNC Blitter_ComputeLOP;
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Count blitter cycles
+ */
+
+static void Blitter_AddCycles(int cycles)
+{
+	int all_cycles = cycles + nWaitStateCycles;
+
+	BlitterVars.op_cycles += all_cycles;
+
+	nCyclesMainCounter += all_cycles >> nCpuFreqShift;
+	CyclesGlobalClockCounter += all_cycles >> nCpuFreqShift;
+	nWaitStateCycles = 0;
+}
+
+static void Blitter_FlushCycles(void)
+{
+	int op_cycles = INT_CONVERT_TO_INTERNAL(BlitterVars.op_cycles, INT_CPU_CYCLE);
+
+	BlitterVars.pass_cycles += BlitterVars.op_cycles;
+	BlitterVars.op_cycles = 0;
+
+	PendingInterruptCount -= op_cycles;
+	while (PendingInterruptCount <= 0 && PendingInterruptFunction)
+		CALL_VAR(PendingInterruptFunction);
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Handle bus arbitration when switching between CPU and Blitter
+ * When a write is made to FF8A3C to start the blitter, it will take a few cycles
+ * before doing the bus arbitration. During this time the CPU will be able to
+ * partially execute the next instruction in parallel to the blitter
+ * (until an access to the BUS is needed by the CPU).
+ *
+ * NOTE [NP] : this is mostly handled with hardcoded cases for now, as it
+ * requires cycle exact emulation to exactly know when bus is accessed
+ * by the CPU to prefetch the next word.
+ * More tests are needed on a real STE to have a proper model of this.
+ *
+ * Based on several examples, possible sequence when starting the blitter seems to be :
+ *  - t+0 : write to FF8A3C
+ *  - t+0 : CPU can still run during 4 cycles and access bus
+ *  - t+4 : bus arbitration takes 4 cycles (no access for cpu and blitter during this time)
+ *  - t+8 : blitter owns the bus and starts tranferring data
+ *
+ * When blitter stops owning the bus in favor of the cpu, this seems to always take 4 cycles
+ */
+static void Blitter_BusArbitration ( int RequestBusMode )
+{
+	int	cycles;
+
+	if ( RequestBusMode == BUS_MODE_BLITTER )	/* Bus is requested by the blitter */
+	{
+//fprintf ( stderr , "blitter start pc %x %x\n" , M68000_GetPC() , M68000_InstrPC );
+		cycles = 4;				/* Default case : take 4 cycles when going from cpu to blitter */
+
+		/* Different timing for some specific cases */
+
+		/* 'Relapse - Graphix Sound 2' by Cybernetics (overscan plasma using blitter) */
+		/* $e764 : move.b  d5,(a4) + dbra d1,$fff2 : 4 cycles of the dbra can be executed while blitter starts */
+		if ( STMemory_ReadLong ( M68000_InstrPC ) == 0x188551c9 )	/* PC = E764 */
+			cycles = 4-4;			/* 4 cycles less than default case */
+	}
+
+	else						/* Bus is requested by the cpu */
+	{
+		cycles = 4;				/* Always 4 cycles ? */
+	}
+
+	/* Add arbitration cycles and update BusMode */
+	if ( cycles > 0 )
+	{
+		Blitter_AddCycles(cycles);
+		Blitter_FlushCycles();
+	}	
+	BusMode = RequestBusMode;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read & Write operations
+ */
+static Uint16 Blitter_ReadWord(Uint32 addr)
+{
+	Uint16 value;
+
+	/* When reading from a bus error region, just return a constant */
+	if ( STMemory_CheckRegionBusError ( addr ) )
+		value = BLITTER_READ_WORD_BUS_ERR;
+	else
+		value = (Uint16)get_word ( addr );
+//fprintf ( stderr , "read %x %x %x\n" , addr , value , STMemory_CheckRegionBusError(addr) );
+
+	Blitter_AddCycles(4);
+
+	return value;
+}
+
+static void Blitter_WriteWord(Uint32 addr, Uint16 value)
+{
+	/* Call put_word only if the address doesn't point to a bus error region */
+	if ( STMemory_CheckRegionBusError ( addr ) == false )
+		put_word ( addr , (Uint32)(value) );
+//fprintf ( stderr , "write %x %x %x\n" , addr , value , STMemory_CheckRegionBusError(addr) );
+
+	Blitter_AddCycles(4);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Blitter emulation - level 1
+ */
+
+static void Blitter_BeginLine(void)
+{
+	BlitterVars.src_words = BlitterVars.src_words_reset;
+}
+
+static void Blitter_SetState(Uint8 fxsr, Uint8 nfsr, Uint16 end_mask)
+{
+	BlitterState.end_mask = end_mask;
+	BlitterState.have_src = false;
+	BlitterState.have_dst = false;
+	BlitterState.fxsr = fxsr;
+	BlitterState.nfsr = nfsr;
+}
+
+static void Blitter_SourceShift(void)
+{
+	if (BlitterRegs.src_x_incr < 0)
+		BlitterVars.buffer >>= 16;
+	else
+		BlitterVars.buffer <<= 16;
+}
+
+static void Blitter_SourceFetch(void)
+{
+	Uint32 src_word = (Uint32)Blitter_ReadWord(BlitterRegs.src_addr);
+
+	if (BlitterRegs.src_x_incr < 0)
+		BlitterVars.buffer |= src_word << 16;
+	else
+		BlitterVars.buffer |= src_word;
+
+	if (BlitterVars.src_words == 1)
+	{
+		BlitterRegs.src_addr += BlitterRegs.src_y_incr;
+	}
+	else
+	{
+		--BlitterVars.src_words;
+		BlitterRegs.src_addr += BlitterRegs.src_x_incr;
+	}
+}
+
+static Uint16 Blitter_SourceRead(void)
+{
+	if (!BlitterState.have_src)
+	{
+		if (BlitterState.fxsr)
+		{
+			Blitter_SourceShift();
+			Blitter_SourceFetch();
+		}
+
+		Blitter_SourceShift();
+
+		if (!BlitterState.nfsr)
+		{
+			Blitter_SourceFetch();
+		}
+
+		BlitterState.src_word = (Uint16)(BlitterVars.buffer >> BlitterVars.skew);
+		BlitterState.have_src = true;
+	}
+
+	return BlitterState.src_word;
+}
+
+static Uint16 Blitter_GetHalftoneWord(void)
+{
+	if (BlitterVars.smudge)
+		return BlitterHalftone[Blitter_SourceRead() & 15];
+	else
+		return BlitterHalftone[BlitterVars.line];
+}
+
+/* HOP */
+
+static Uint16 Blitter_HOP_0(void)
+{
+	return 0xFFFF;
+}
+
+static Uint16 Blitter_HOP_1(void)
+{
+	return Blitter_GetHalftoneWord();
+}
+
+static Uint16 Blitter_HOP_2(void)
+{
+	return Blitter_SourceRead();
+}
+
+static Uint16 Blitter_HOP_3(void)
+{
+	return Blitter_SourceRead() & Blitter_GetHalftoneWord();
+}
+
+static BLITTER_OP_FUNC Blitter_HOP_Table [4] =
+{
+	Blitter_HOP_0,
+	Blitter_HOP_1,
+	Blitter_HOP_2,
+	Blitter_HOP_3
+};
+
+static void Blitter_Select_HOP(void)
+{
+	Blitter_ComputeHOP = Blitter_HOP_Table[BlitterRegs.hop];
+}
+
+/* end HOP */
+
+static Uint16 Blitter_DestRead(void)
+{
+	if (!BlitterState.have_dst)
+	{
+		BlitterState.dst_word = Blitter_ReadWord(BlitterRegs.dst_addr);
+		BlitterState.have_dst = true;
+	}
+
+	return BlitterState.dst_word;
+}
+
+/* LOP */
+
+static Uint16 Blitter_LOP_0(void)
+{
+	return 0;
+}
+
+static Uint16 Blitter_LOP_1(void)
+{
+	return Blitter_ComputeHOP() & Blitter_DestRead();
+}
+
+static Uint16 Blitter_LOP_2(void)
+{
+	return Blitter_ComputeHOP() & ~Blitter_DestRead();
+}
+
+static Uint16 Blitter_LOP_3(void)
+{
+	return Blitter_ComputeHOP();
+}
+
+static Uint16 Blitter_LOP_4(void)
+{
+	return ~Blitter_ComputeHOP() & Blitter_DestRead();
+}
+
+static Uint16 Blitter_LOP_5(void)
+{
+	return Blitter_DestRead();
+}
+
+static Uint16 Blitter_LOP_6(void)
+{
+	return Blitter_ComputeHOP() ^ Blitter_DestRead();
+}
+
+static Uint16 Blitter_LOP_7(void)
+{
+	return Blitter_ComputeHOP() | Blitter_DestRead();
+}
+
+static Uint16 Blitter_LOP_8(void)
+{
+	return ~Blitter_ComputeHOP() & ~Blitter_DestRead();
+}
+
+static Uint16 Blitter_LOP_9(void)
+{
+	return ~Blitter_ComputeHOP() ^ Blitter_DestRead();
+}
+
+static Uint16 Blitter_LOP_A(void)
+{
+	return ~Blitter_DestRead();
+}
+
+static Uint16 Blitter_LOP_B(void)
+{
+	return Blitter_ComputeHOP() | ~Blitter_DestRead();
+}
+
+static Uint16 Blitter_LOP_C(void)
+{
+	return ~Blitter_ComputeHOP();
+}
+
+static Uint16 Blitter_LOP_D(void)
+{
+	return ~Blitter_ComputeHOP() | Blitter_DestRead();
+}
+
+static Uint16 Blitter_LOP_E(void)
+{
+	return ~Blitter_ComputeHOP() | ~Blitter_DestRead();
+}
+
+static Uint16 Blitter_LOP_F(void)
+{
+	return 0xFFFF;
+}
+
+static BLITTER_OP_FUNC Blitter_LOP_Table [16] =
+{
+	Blitter_LOP_0,
+	Blitter_LOP_1,
+	Blitter_LOP_2,
+	Blitter_LOP_3,
+	Blitter_LOP_4,
+	Blitter_LOP_5,
+	Blitter_LOP_6,
+	Blitter_LOP_7,
+	Blitter_LOP_8,
+	Blitter_LOP_9,
+	Blitter_LOP_A,
+	Blitter_LOP_B,
+	Blitter_LOP_C,
+	Blitter_LOP_D,
+	Blitter_LOP_E,
+	Blitter_LOP_F
+};
+
+static void Blitter_Select_LOP(void)
+{
+	Blitter_ComputeLOP = Blitter_LOP_Table[BlitterRegs.lop];
+}
+
+/* end LOP */
+
+static Uint16 Blitter_ComputeMask(void)
+{
+	return (Blitter_ComputeLOP() & BlitterState.end_mask) |
+			(Blitter_DestRead() & ~BlitterState.end_mask);
+}
+
+static void Blitter_ProcessWord(void)
+{
+	/* when NFSR, a read-modify-write is always performed */
+	Uint16 dst_data = ((BlitterState.nfsr || BlitterState.end_mask != 0xFFFF)
+							? Blitter_ComputeMask()
+							: Blitter_ComputeLOP());
+
+	Blitter_WriteWord(BlitterRegs.dst_addr, dst_data);
+
+	if (BlitterRegs.words == 1)
+	{
+		BlitterRegs.dst_addr += BlitterRegs.dst_y_incr;
+	}
+	else
+	{
+		--BlitterRegs.words;
+		BlitterRegs.dst_addr += BlitterRegs.dst_x_incr;
+	}
+}
+
+static void Blitter_EndLine(void)
+{
+	--BlitterRegs.lines;
+	BlitterRegs.words = BlitterVars.dst_words_reset;
+
+	if (BlitterRegs.dst_y_incr >= 0)
+		BlitterVars.line = (BlitterVars.line+1) & 15;
+	else
+		BlitterVars.line = (BlitterVars.line-1) & 15;
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Blitter emulation - level 2
+ */
+
+static void Blitter_SingleWord(void)
+{
+	Blitter_BeginLine();
+	Blitter_SetState(BlitterVars.fxsr, BlitterVars.nfsr, BlitterRegs.end_mask_1);
+	Blitter_ProcessWord();
+	Blitter_EndLine();
+}
+
+static void Blitter_FirstWord(void)
+{
+	Blitter_BeginLine();
+	Blitter_SetState(BlitterVars.fxsr, 0, BlitterRegs.end_mask_1);
+	Blitter_ProcessWord();
+}
+
+static void Blitter_MiddleWord(void)
+{
+	Blitter_SetState(0, 0, BlitterRegs.end_mask_2);
+	Blitter_ProcessWord();
+}
+
+static void Blitter_LastWord(void)
+{
+	Blitter_SetState(0, BlitterVars.nfsr, BlitterRegs.end_mask_3);
+	Blitter_ProcessWord();
+	Blitter_EndLine();
+}
+
+static void Blitter_Step(void)
+{
+	if (BlitterVars.dst_words_reset == 1)
+	{
+		Blitter_SingleWord();
+	}
+	else if (BlitterRegs.words == BlitterVars.dst_words_reset)
+	{
+		Blitter_FirstWord();
+	}
+	else if (BlitterRegs.words == 1)
+	{
+		Blitter_LastWord();
+	}
+	else
+	{
+		Blitter_MiddleWord();
+	}
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Let's do the blit.
+ * Note that in non-HOG mode, the blitter only runs for 64 bus cycles (2 MHz!)
+ * before giving the bus back to the CPU. Due to this mode, this function must
+ * be able to abort and resume the blitting at any time.
+ */
+static void Blitter_Start(void)
+{
+	/* select HOP & LOP funcs */
+	Blitter_Select_HOP();
+	Blitter_Select_LOP();
+
+	/* setup vars */
+	BlitterVars.pass_cycles = 0;
+	BlitterVars.op_cycles = 0;
+	BlitterVars.src_words_reset = BlitterVars.dst_words_reset + BlitterVars.fxsr - BlitterVars.nfsr;
+
+	/* bus arbitration */
+	Blitter_BusArbitration ( BUS_MODE_BLITTER );
+
+	/* Busy=1, set line to high/1 and clear interrupt */
+	MFP_GPIP_Set_Line_Input ( MFP_GPIP_LINE_GPU_DONE , MFP_GPIP_STATE_HIGH );
+
+	/* Now we enter the main blitting loop */
+	do
+	{
+		Blitter_Step();
+		Blitter_FlushCycles();
+	}
+	while (BlitterRegs.lines > 0
+	       && (BlitterVars.hog || BlitterVars.pass_cycles < NONHOG_CYCLES));
+
+	/* bus arbitration */
+	Blitter_BusArbitration ( BUS_MODE_CPU );
+
+	BlitterRegs.ctrl = (BlitterRegs.ctrl & 0xF0) | BlitterVars.line;
+
+	if (BlitterRegs.lines == 0)
+	{
+		/* We're done, clear busy and hog bits */
+		BlitterRegs.ctrl &= ~(0x80|0x40);
+
+		/* Busy=0, set line to low/0 and request interrupt */
+		MFP_GPIP_Set_Line_Input ( MFP_GPIP_LINE_GPU_DONE , MFP_GPIP_STATE_LOW );
+	}
+	else
+	{
+		/* Continue blitting later */
+		CycInt_AddRelativeInterrupt(NONHOG_CYCLES, INT_CPU_CYCLE, INTERRUPT_BLITTER);
+	}
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter halftone ram.
+ */
+static void Blitter_Halftone_ReadWord(int index)
+{
+	IoMem_WriteWord(REG_HT_RAM + index + index, BlitterHalftone[index]);
+}
+
+void Blitter_Halftone00_ReadWord(void) { Blitter_Halftone_ReadWord(0); }
+void Blitter_Halftone01_ReadWord(void) { Blitter_Halftone_ReadWord(1); }
+void Blitter_Halftone02_ReadWord(void) { Blitter_Halftone_ReadWord(2); }
+void Blitter_Halftone03_ReadWord(void) { Blitter_Halftone_ReadWord(3); }
+void Blitter_Halftone04_ReadWord(void) { Blitter_Halftone_ReadWord(4); }
+void Blitter_Halftone05_ReadWord(void) { Blitter_Halftone_ReadWord(5); }
+void Blitter_Halftone06_ReadWord(void) { Blitter_Halftone_ReadWord(6); }
+void Blitter_Halftone07_ReadWord(void) { Blitter_Halftone_ReadWord(7); }
+void Blitter_Halftone08_ReadWord(void) { Blitter_Halftone_ReadWord(8); }
+void Blitter_Halftone09_ReadWord(void) { Blitter_Halftone_ReadWord(9); }
+void Blitter_Halftone10_ReadWord(void) { Blitter_Halftone_ReadWord(10); }
+void Blitter_Halftone11_ReadWord(void) { Blitter_Halftone_ReadWord(11); }
+void Blitter_Halftone12_ReadWord(void) { Blitter_Halftone_ReadWord(12); }
+void Blitter_Halftone13_ReadWord(void) { Blitter_Halftone_ReadWord(13); }
+void Blitter_Halftone14_ReadWord(void) { Blitter_Halftone_ReadWord(14); }
+void Blitter_Halftone15_ReadWord(void) { Blitter_Halftone_ReadWord(15); }
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter source x increment (0xff8a20).
+ */
+void Blitter_SourceXInc_ReadWord(void)
+{
+	IoMem_WriteWord(REG_SRC_X_INC, (Uint16)(BlitterRegs.src_x_incr));
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter source y increment (0xff8a22).
+ */
+void Blitter_SourceYInc_ReadWord(void)
+{
+	IoMem_WriteWord(REG_SRC_Y_INC, (Uint16)(BlitterRegs.src_y_incr));
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter source address (0xff8a24).
+ */
+void Blitter_SourceAddr_ReadLong(void)
+{
+	IoMem_WriteLong(REG_SRC_ADDR, BlitterRegs.src_addr);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter endmask 1.
+ */
+void Blitter_Endmask1_ReadWord(void)
+{
+	IoMem_WriteWord(REG_END_MASK1, BlitterRegs.end_mask_1);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter endmask 2.
+ */
+void Blitter_Endmask2_ReadWord(void)
+{
+	IoMem_WriteWord(REG_END_MASK2, BlitterRegs.end_mask_2);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter endmask 3.
+ */
+void Blitter_Endmask3_ReadWord(void)
+{
+	IoMem_WriteWord(REG_END_MASK3, BlitterRegs.end_mask_3);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter destination x increment (0xff8a2E).
+ */
+void Blitter_DestXInc_ReadWord(void)
+{
+	IoMem_WriteWord(REG_DST_X_INC, (Uint16)(BlitterRegs.dst_x_incr));
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter destination y increment (0xff8a30).
+ */
+void Blitter_DestYInc_ReadWord(void)
+{
+	IoMem_WriteWord(REG_DST_Y_INC, (Uint16)(BlitterRegs.dst_y_incr));
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter destination address.
+ */
+void Blitter_DestAddr_ReadLong(void)
+{
+	IoMem_WriteLong(REG_DST_ADDR, BlitterRegs.dst_addr);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter words-per-line register.
+ */
+void Blitter_WordsPerLine_ReadWord(void)
+{
+	IoMem_WriteWord(REG_X_COUNT, (Uint16)(BlitterRegs.words & 0xFFFF));
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter lines-per-bitblock register.
+ */
+void Blitter_LinesPerBitblock_ReadWord(void)
+{
+	IoMem_WriteWord(REG_Y_COUNT, (Uint16)(BlitterRegs.lines & 0xFFFF));
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter halftone operation register.
+ */
+void Blitter_HalftoneOp_ReadByte(void)
+{
+	IoMem_WriteByte(REG_BLIT_HOP, BlitterRegs.hop);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter logical operation register.
+ */
+void Blitter_LogOp_ReadByte(void)
+{
+	IoMem_WriteByte(REG_BLIT_LOP, BlitterRegs.lop);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter control register.
+ */
+void Blitter_Control_ReadByte(void)
+{
+	/* busy, hog/blit, smudge, n/a, 4bits for line number */
+	IoMem_WriteByte(REG_CONTROL, BlitterRegs.ctrl);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read blitter skew register.
+ */
+void Blitter_Skew_ReadByte(void)
+{
+	IoMem_WriteByte(REG_SKEW, BlitterRegs.skew);
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter halftone ram.
+ */
+static void Blitter_Halftone_WriteWord(int index)
+{
+	BlitterHalftone[index] = IoMem_ReadWord(REG_HT_RAM + index + index);
+}
+
+void Blitter_Halftone00_WriteWord(void) { Blitter_Halftone_WriteWord(0); }
+void Blitter_Halftone01_WriteWord(void) { Blitter_Halftone_WriteWord(1); }
+void Blitter_Halftone02_WriteWord(void) { Blitter_Halftone_WriteWord(2); }
+void Blitter_Halftone03_WriteWord(void) { Blitter_Halftone_WriteWord(3); }
+void Blitter_Halftone04_WriteWord(void) { Blitter_Halftone_WriteWord(4); }
+void Blitter_Halftone05_WriteWord(void) { Blitter_Halftone_WriteWord(5); }
+void Blitter_Halftone06_WriteWord(void) { Blitter_Halftone_WriteWord(6); }
+void Blitter_Halftone07_WriteWord(void) { Blitter_Halftone_WriteWord(7); }
+void Blitter_Halftone08_WriteWord(void) { Blitter_Halftone_WriteWord(8); }
+void Blitter_Halftone09_WriteWord(void) { Blitter_Halftone_WriteWord(9); }
+void Blitter_Halftone10_WriteWord(void) { Blitter_Halftone_WriteWord(10); }
+void Blitter_Halftone11_WriteWord(void) { Blitter_Halftone_WriteWord(11); }
+void Blitter_Halftone12_WriteWord(void) { Blitter_Halftone_WriteWord(12); }
+void Blitter_Halftone13_WriteWord(void) { Blitter_Halftone_WriteWord(13); }
+void Blitter_Halftone14_WriteWord(void) { Blitter_Halftone_WriteWord(14); }
+void Blitter_Halftone15_WriteWord(void) { Blitter_Halftone_WriteWord(15); }
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter source x increment.
+ */
+void Blitter_SourceXInc_WriteWord(void)
+{
+	BlitterRegs.src_x_incr = (short)(IoMem_ReadWord(REG_SRC_X_INC) & 0xFFFE);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter source y increment.
+ */
+void Blitter_SourceYInc_WriteWord(void)
+{
+	BlitterRegs.src_y_incr = (short)(IoMem_ReadWord(REG_SRC_Y_INC) & 0xFFFE);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter source address register (0xff8a24).
+ */
+void Blitter_SourceAddr_WriteLong(void)
+{
+	if ( ConfigureParams.System.bAddressSpace24 == true )
+		BlitterRegs.src_addr = IoMem_ReadLong(REG_SRC_ADDR) & 0x00FFFFFE;	/* Normal STF/STE */
+	else
+		BlitterRegs.src_addr = IoMem_ReadLong(REG_SRC_ADDR) & 0xFFFFFFFE;	/* Falcon with extra TT RAM */
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter endmask 1.
+ */
+void Blitter_Endmask1_WriteWord(void)
+{
+	BlitterRegs.end_mask_1 = IoMem_ReadWord(REG_END_MASK1);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter endmask 2.
+ */
+void Blitter_Endmask2_WriteWord(void)
+{
+	BlitterRegs.end_mask_2 = IoMem_ReadWord(REG_END_MASK2);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter endmask 3.
+ */
+void Blitter_Endmask3_WriteWord(void)
+{
+	BlitterRegs.end_mask_3 = IoMem_ReadWord(REG_END_MASK3);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter destination x increment.
+ */
+void Blitter_DestXInc_WriteWord(void)
+{
+	BlitterRegs.dst_x_incr = (short)(IoMem_ReadWord(REG_DST_X_INC) & 0xFFFE);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter source y increment.
+ */
+void Blitter_DestYInc_WriteWord(void)
+{
+	BlitterRegs.dst_y_incr = (short)(IoMem_ReadWord(REG_DST_Y_INC) & 0xFFFE);
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter destination address register.
+ */
+void Blitter_DestAddr_WriteLong(void)
+{
+	if ( ConfigureParams.System.bAddressSpace24 == true )
+		BlitterRegs.dst_addr = IoMem_ReadLong(REG_DST_ADDR) & 0x00FFFFFE;	/* Normal STF/STE */
+	else
+		BlitterRegs.dst_addr = IoMem_ReadLong(REG_DST_ADDR) & 0xFFFFFFFE;	/* Falcon with extra TT RAM */
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter words-per-line register.
+ */
+void Blitter_WordsPerLine_WriteWord(void)
+{
+	Uint32 words = (Uint32)IoMem_ReadWord(REG_X_COUNT);
+
+	if (words == 0)
+		words = 65536;
+
+	BlitterRegs.words = words;
+	BlitterVars.dst_words_reset = words;
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter lines-per-bitblock register.
+ */
+void Blitter_LinesPerBitblock_WriteWord(void)
+{
+	Uint32 lines = (Uint32)IoMem_ReadWord(REG_Y_COUNT);
+
+	if (lines == 0)
+		lines = 65536;
+
+	BlitterRegs.lines = lines;
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter halftone operation register.
+ */
+void Blitter_HalftoneOp_WriteByte(void)
+{
+	/* h/ware reg masks out the top 6 bits! */
+	BlitterRegs.hop = IoMem_ReadByte(REG_BLIT_HOP) & 3;
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter logical operation register.
+ */
+void Blitter_LogOp_WriteByte(void)
+{
+	/* h/ware reg masks out the top 4 bits! */
+	BlitterRegs.lop = IoMem_ReadByte(REG_BLIT_LOP) & 0xF;
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter control register.
+ */
+void Blitter_Control_WriteByte(void)
+{
+	/* Control register bits:
+	 * 0x80: busy bit
+	 * - Turn on Blitter activity and stay "1" until copy finished
+	 * 0x40: Blit-mode bit
+	 * - 0: Blit mode, CPU and Blitter get 64 clockcycles in turns
+	 * - 1: HOG Mode, Blitter reserves and hogs the bus for as long
+	 *      as the copy takes, CPU and DMA get no Bus access
+	 * 0x20: Smudge mode
+	 * - Which line of the halftone pattern to start with is
+	 *   read from the first source word when the copy starts
+	 * 0x10: not used
+	 * 0x0f
+	 *
+	 * The lowest 4 bits contain the Halftone pattern line number
+	 */
+
+	if (LOG_TRACE_LEVEL(TRACE_BLITTER))
+	{
+		int FrameCycles, HblCounterVideo, LineCycles;
+
+		Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+
+		LOG_TRACE_PRINT("blitter write ctrl=%x video_cyc=%d %d@%d pc=%x instr_cyc=%d\n" ,
+				IoMem_ReadByte(REG_CONTROL) ,
+				FrameCycles, LineCycles, HblCounterVideo, M68000_GetPC(), CurrentInstrCycles );
+	}
+
+	BlitterRegs.ctrl = IoMem_ReadByte(REG_CONTROL) & 0xEF;
+
+	BlitterVars.hog = BlitterRegs.ctrl & 0x40;
+	BlitterVars.smudge = BlitterRegs.ctrl & 0x20;
+	BlitterVars.line = BlitterRegs.ctrl & 0xF;
+
+	/* Remove old pending update interrupt */
+	CycInt_RemovePendingInterrupt(INTERRUPT_BLITTER);
+
+	/* Busy bit set? */
+	if (BlitterRegs.ctrl & 0x80)
+	{
+		if (BlitterRegs.lines == 0)
+		{
+			/* We're done, clear busy and hog bits */
+			BlitterRegs.ctrl &= ~(0x80|0x40);
+		}
+		else
+		{
+			/* Start blitting after some CPU cycles */
+			CycInt_AddRelativeInterrupt((CurrentInstrCycles+nWaitStateCycles)>>nCpuFreqShift,
+							 INT_CPU_CYCLE, INTERRUPT_BLITTER);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write to blitter skew register.
+ */
+void Blitter_Skew_WriteByte(void)
+{
+	BlitterRegs.skew = IoMem_ReadByte(REG_SKEW);
+	BlitterVars.fxsr = (BlitterRegs.skew & 0x80)?1:0;
+	BlitterVars.nfsr = (BlitterRegs.skew & 0x40)?1:0;
+	BlitterVars.skew = BlitterRegs.skew & 0xF;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Handler which continues blitting after 64 bus cycles.
+ */
+void Blitter_InterruptHandler(void)
+{
+	CycInt_AcknowledgeInterrupt();
+
+	if (BlitterRegs.ctrl & 0x80)
+	{
+		Blitter_Start();
+	}
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Save/Restore snapshot of Blitter variables.
+ */
+void Blitter_MemorySnapShot_Capture(bool bSave)
+{
+	/* Save/Restore details */
+	MemorySnapShot_Store(&BlitterRegs, sizeof(BlitterRegs));
+	MemorySnapShot_Store(&BlitterVars, sizeof(BlitterVars));
+	MemorySnapShot_Store(&BlitterHalftone, sizeof(BlitterHalftone));
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Show Blitter register values.
+ */
+void Blitter_Info(FILE *fp, Uint32 dummy)
+{
+	BLITTERREGS *regs = &BlitterRegs;
+
+	fprintf(fp, "src addr:  0x%06x\n", regs->src_addr);
+	fprintf(fp, "dst addr:  0x%06x\n", regs->dst_addr);
+	fprintf(fp, "words:     %u\n", regs->words);
+	fprintf(fp, "lines:     %u\n", regs->lines);
+	fprintf(fp, "src X-inc: %hd\n", regs->src_x_incr);
+	fprintf(fp, "src Y-inc: %hd\n", regs->src_y_incr);
+	fprintf(fp, "dst X-inc: %hd\n", regs->dst_x_incr);
+	fprintf(fp, "dst Y-inc: %hd\n", regs->dst_y_incr);
+	fprintf(fp, "end mask1: 0x%04x\n", regs->end_mask_1);
+	fprintf(fp, "end mask2: 0x%04x\n", regs->end_mask_2);
+	fprintf(fp, "end mask3: 0x%04x\n", regs->end_mask_3);
+	fprintf(fp, "HOP:       0x%02x\n", regs->hop);
+	fprintf(fp, "LOP:       0x%02x\n", regs->lop);
+	fprintf(fp, "control:   0x%02x\n", regs->ctrl);
+	fprintf(fp, "skew:      0x%02x\n", regs->skew);
+	fprintf(fp, "Note: internally changed register values aren't visible to breakpoints\nor in memdump output until emulated code reads or writes them!\n");
+}
diff --git a/src/cart.c b/src/cart.c
new file mode 100644
index 0000000..f73e600
--- /dev/null
+++ b/src/cart.c
@@ -0,0 +1,179 @@
+/*
+  Hatari - cart.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Cartridge program
+
+  To load programs into memory, through TOS, we need to intercept GEMDOS so we
+  can relocate/execute programs via GEMDOS call $4B (Pexec).
+  We have some 68000 assembler, located at 0xFA0000 (cartridge memory), which is
+  used as our new GEMDOS handler. This checks if we need to intercept the call.
+
+  The assembler routine can be found in 'cart_asm.s', and has been converted to
+  a byte array and stored in 'Cart_data[]' (see cartData.c).
+*/
+const char Cart_fileid[] = "Hatari cart.c : " __DATE__ " " __TIME__;
+
+/* 2007/12/09	[NP]	Change the function associated to opcodes $8, $a and $c only if hard drive	*/
+/*			emulation is ON. Else, these opcodes should give illegal instructions (also	*/
+/*			see uae-cpu/newcpu.c).								*/
+
+
+#include "main.h"
+#include "cart.h"
+#include "configuration.h"
+#include "file.h"
+#include "log.h"
+#include "m68000.h"
+#include "stMemory.h"
+#include "tos.h"
+#include "vdi.h"
+#include "hatari-glue.h"
+#include "newcpu.h"
+
+#include "cartData.c"
+
+
+/* Possible cartridge file extensions to scan for */
+static const char * const psCartNameExts[] =
+{
+	".img",
+	".rom",
+	".stc",
+	NULL
+};
+
+static int PatchIllegal = false;
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Load an external cartridge image file.
+ */
+static void Cart_LoadImage(void)
+{
+	Uint8 *pCartData;
+	long nCartSize;
+	char *pCartFileName = ConfigureParams.Rom.szCartridgeImageFileName;
+
+	/* Try to load the image file: */
+	pCartData = File_Read(pCartFileName, &nCartSize, psCartNameExts);
+	if (!pCartData)
+	{
+		Log_Printf(LOG_ERROR, "Failed to load '%s'.\n", pCartFileName);
+		return;
+	}
+
+	if (nCartSize < 40 || (nCartSize > 0x20000 && nCartSize != 0x20004))
+	{
+		Log_Printf(LOG_ERROR, "Cartridge file '%s' has illegal size.\n", pCartFileName);
+		free(pCartData);
+		return;
+	}
+
+	/* There are two type of cartridge images, normal 1:1 images which are
+	 * always smaller than or equal to 0x20000 bytes, and the .STC images,
+	 * which are always 0x20004 bytes (the first 4 bytes are a dummy header).
+	 * So if size is 0x20004 bytes we have to skip the first 4 bytes */
+	if (nCartSize == 0x20004)
+	{
+		memcpy(&RomMem[0xfa0000], pCartData+4, 0x20000);
+	}
+	else
+	{
+		memcpy(&RomMem[0xfa0000], pCartData, nCartSize);
+	}
+
+	free(pCartData);
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Copy ST GEMDOS intercept program image into cartridge memory space
+ * or load an external cartridge file.
+ * The intercept program is part of Hatari and used as an interface to the host
+ * file system through GemDOS. It is also needed for Line-A-Init when using
+ * extended VDI resolutions.
+ */
+void Cart_ResetImage(void)
+{
+	/* "Clear" cartridge ROM space */
+	memset(&RomMem[0xfa0000], 0xff, 0x20000);
+
+	/* Print a warning if user tries to use an external cartridge file
+	 * together with GEMDOS HD emulation or extended VDI resolution: */
+	if (strlen(ConfigureParams.Rom.szCartridgeImageFileName) > 0)
+	{
+		if (bUseVDIRes)
+			Log_Printf(LOG_WARN, "Cartridge can't be used together with extended VDI resolution!\n");
+		if (ConfigureParams.HardDisk.bUseHardDiskDirectories)
+			Log_Printf(LOG_WARN, "Cartridge can't be used together with GEMDOS hard disk emulation!\n");
+		if (LogTraceFlags & (TRACE_OS_GEMDOS | TRACE_OS_BASE | TRACE_OS_VDI | TRACE_OS_AES))
+			Log_Printf(LOG_WARN, "Cartridge can't be used together with GEMDOS/VDI/AES tracing!\n");
+	}
+
+	/* Use internal cartridge trampoline code when user wants extended VDI
+	 * resolution, GEMDOS HD emulation or to trace GEMDOS, VDI or AES.
+	 * (OS_BASE does subset of GEMDOS tracing)
+	 * But don't use it on TOS 0.00, it does not work there. */
+	if ((bUseVDIRes || ConfigureParams.HardDisk.bUseHardDiskDirectories ||
+	    LogTraceFlags & (TRACE_OS_GEMDOS | TRACE_OS_BASE | TRACE_OS_VDI | TRACE_OS_AES))
+	    && TosVersion >= 0x100)
+	{
+		/* Copy built-in cartridge data into the cartridge memory of the ST */
+		memcpy(&RomMem[0xfa0000], Cart_data, sizeof(Cart_data));
+		PatchIllegal = true;
+	}
+	else if (strlen(ConfigureParams.Rom.szCartridgeImageFileName) > 0)
+	{
+		/* Load external image file: */
+		Cart_LoadImage();
+	}
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Patch the cpu tables to intercept some opcodes used for Gemdos HD
+ * emulation or for NatFeats.
+ * We need to split this from Cart_ResetImage(), as the patches should
+ * be applied after building the cpu opcodes tables.
+ */
+void Cart_Patch(void)
+{
+	if (PatchIllegal == true)
+	{
+		//fprintf ( stderr ," Cart_ResetImage patch\n" );
+		/* Hatari's specific illegal opcodes for HD emulation */
+		cpufunctbl[GEMDOS_OPCODE] = OpCode_GemDos;	/* 0x0008 */
+		cpufunctbl[SYSINIT_OPCODE] = OpCode_SysInit;	/* 0x000a */
+		cpufunctbl[VDI_OPCODE] = OpCode_VDI;		/* 0x000c */
+	}
+	else
+	{
+		//fprintf ( stderr ," Cart_ResetImage no patch\n" );
+		/* No built-in cartridge loaded : set same handler as 0x4afc (illegal) */
+		cpufunctbl[GEMDOS_OPCODE] = cpufunctbl[ 0x4afc ];	/* 0x0008 */
+		cpufunctbl[SYSINIT_OPCODE] = cpufunctbl[ 0x4afc ];	/* 0x000a */
+		cpufunctbl[VDI_OPCODE] = cpufunctbl[ 0x4afc ];		/* 0x000c */
+	}
+
+	/* although these don't need cartridge code, it's better
+	 * to configure all illegal opcodes in same place...
+	 */
+	if (ConfigureParams.Log.bNatFeats)
+	{
+		/* illegal opcodes for emulators Native Features */
+		cpufunctbl[NATFEAT_ID_OPCODE] = OpCode_NatFeat_ID;	/* 0x7300 */
+		cpufunctbl[NATFEAT_CALL_OPCODE] = OpCode_NatFeat_Call;	/* 0x7301 */
+	}
+	else
+	{
+		/* No Native Features : set same handler as 0x4afc (illegal) */
+		cpufunctbl[NATFEAT_ID_OPCODE] = cpufunctbl[ 0x4afc ];	/* 0x7300 */
+		cpufunctbl[NATFEAT_CALL_OPCODE] = cpufunctbl[ 0x4afc ];	/* 0x7300 */
+	}
+}
diff --git a/src/cartData.c b/src/cartData.c
new file mode 100644
index 0000000..b4cad26
--- /dev/null
+++ b/src/cartData.c
@@ -0,0 +1,944 @@
+/*
+  Hatari - cartData.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  The assembled cartridge Pexec() program (source code can be found in the
+  file cart_asm.s).
+  NOTE: This file is included by cart.c - do not compile and link this file
+  separately!
+*/
+const char CartData_fileid[] = "Hatari cartData.c : " __DATE__ " " __TIME__;
+
+
+/*
+  This is the assembled code from cart_asm.s with our gemdos handler.
+  NOTE: Remove first 0x1c (PRG_HEADER_SIZE) bytes from the assembled program
+  file or use an assembler like TurboAss that can generate absolute binary images.
+  (I am using TurboAss and  hexdump -v -e ' 16/1 "0x%02x," "\n" '  to create it).
+ */
+const Uint8 Cart_data[] =
+{
+0xab,0xcd,0xef,0x42,0x00,0x00,0x00,0x00,0x08,0xfa,0x02,0xe0,0x00,0xfa,0x02,0xe6,
+0x58,0x00,0x32,0x29,0x00,0x00,0x36,0x9e,0x48,0x41,0x54,0x41,0x52,0x49,0x2e,0x54,
+0x4f,0x53,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0c,0x00,0x08,0x69,0x0a,0x66,0x02,
+0x4e,0x73,0x2f,0x3a,0xff,0xf0,0x4e,0x75,0x4e,0x68,0x08,0x17,0x00,0x05,0x67,0x0c,
+0x41,0xef,0x00,0x06,0x4a,0x78,0x05,0x9e,0x67,0x02,0x54,0x48,0x54,0x48,0x4a,0x50,
+0x66,0x34,0x2f,0x0e,0x2c,0x48,0x61,0x40,0x61,0x00,0x00,0x92,0x42,0xae,0x00,0x02,
+0x42,0xae,0x00,0x0a,0x2d,0x40,0x00,0x06,0x3f,0x3c,0x00,0x30,0x4e,0x41,0x54,0x4f,
+0xe0,0x58,0xb0,0x7c,0x00,0x15,0x6c,0x06,0x3c,0xbc,0x00,0x04,0x60,0x04,0x3c,0xbc,
+0x00,0x06,0x2c,0x5f,0x60,0xac,0x0c,0x50,0x00,0x03,0x66,0xa6,0x2f,0x0e,0x2c,0x48,
+0x61,0x06,0x61,0x58,0x2c,0x5f,0x4e,0x73,0x3f,0x3c,0x00,0x2f,0x4e,0x41,0x54,0x4f,
+0x20,0x40,0x2f,0x18,0x2f,0x18,0x2f,0x18,0x2f,0x18,0x2f,0x18,0x2f,0x18,0x2f,0x18,
+0x2f,0x18,0x2f,0x18,0x2f,0x18,0x2f,0x18,0x2f,0x08,0x3f,0x3c,0x00,0x17,0x2f,0x2e,
+0x00,0x02,0x3f,0x3c,0x00,0x4e,0x4e,0x41,0x50,0x4f,0x20,0x5f,0x21,0x1f,0x21,0x1f,
+0x21,0x1f,0x21,0x1f,0x21,0x1f,0x21,0x1f,0x21,0x1f,0x21,0x1f,0x21,0x1f,0x21,0x1f,
+0x21,0x1f,0x4a,0x80,0x67,0x04,0x58,0x4f,0x60,0xaa,0x4e,0x75,0x48,0xe7,0x02,0x1c,
+0x42,0x67,0x2f,0x2e,0x00,0x02,0x3f,0x3c,0x00,0x3d,0x4e,0x41,0x50,0x4f,0x2c,0x00,
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+0x00,0x82,0x00,0x82
+};
diff --git a/src/cart_asm.s b/src/cart_asm.s
new file mode 100644
index 0000000..b3adc1c
--- /dev/null
+++ b/src/cart_asm.s
@@ -0,0 +1,408 @@
+; Cartridge assembler code.
+; 68000 code that is used for starting programs from the emulated GEMDOS harddisk
+; and for using bigger VDI resolutions
+
+; Hatari's "illegal" (free) opcodes:
+GEMDOS_OPCODE		equ	8
+SYSINIT_OPCODE		equ 10
+VDI_OPCODE			equ	12
+
+; System variables:
+_longframe		equ $059E
+
+
+	org	$fa0000
+
+
+; This is the cartridge header:
+	dc.l	$ABCDEF42					; C-FLAG (magic value)
+	dc.l	$00000000					; C-NEXT
+	dc.l	sys_init+$08000000			; C-INIT - flag has bit 3 set = before disk boot, but after GEMDOS init
+	dc.l	infoprgstart				; C-RUN
+	dc.w	%0101100000000000			; C-TIME
+	dc.w	%0011001000101001			; C-DATE
+	dc.l	infoprgend-infoprgstart		; C-BSIZ, offset: $14
+	dc.b	'HATARI.TOS',0,0			; C-NAME
+
+	.even
+
+
+old_gemdos:		ds.l	1			; has to match the CART_OLDGEMDOS define!
+vdi_opcode:		dc.w	VDI_OPCODE	; Address to call after Trap #2 (VDI), causes illegal instruction
+
+; New GemDOS vector (0x84) - for intercepting Pexec
+new_gemdos:
+	dc.w	GEMDOS_OPCODE	; Returns NEG as run old vector, ZERO to return or OVERFLOW to run pexec
+	bvs.s	pexec
+	bne.s	go_oldgemdos
+	rte
+
+; Branch to old GemDOS
+go_oldgemdos:
+	move.l	old_gemdos(pc),-(sp)	; Set PC to 'old_gemdos' and continue execution, WITHOUT corrupting registers!
+	rts
+
+; Progam Execute
+pexec:
+	move	usp,a0		; Parameters on user stack pointer?
+	btst	#5,(sp)		; Check if program was in user or supervisor mode
+	beq.s	p_ok
+	lea 	6(sp),a0	; Parameters are on SSP
+	tst.w	_longframe.w	; Do we use a CPU > 68000?
+	beq.s	p_ok		; No: A0 is OK
+	addq	#2,a0		; Skip 2 additional stack frame bytes on CPUs >= 68010
+p_ok:
+	addq	#2,a0		; Skip GEMDOS function number
+	tst		(a0)		; Test pexec mode
+	bne.s	no_0
+
+	; Simulate pexec mode 0
+	move.l	a6,-(sp)
+	move.l	a0,a6
+	bsr.s	find_prog
+	bsr	load_n_reloc
+	clr.l	2(a6)
+	clr.l	10(a6)
+	move.l	d0,6(a6)
+
+	move.w	#48,-(sp)	; Sversion: get GEMDOS version
+	trap	#1		; call GEMDOS
+	addq	#2,sp
+	ror.w	#8,d0		; Major version to high, minor version to low byte
+	cmp.w	#$0015,d0
+	bge.s	use_gemdos_015
+	move.w	#4,(a6)		; pexec mode 4 for exec. prepared program
+	bra.s	mode0_ok
+use_gemdos_015:
+	move.w	#6,(a6)		; On GEMDOS 0.15 and higher, we can use mode 6
+mode0_ok:
+
+	move.l	(sp)+,a6
+	bra.s	go_oldgemdos
+
+no_0:
+	cmp		#3,(a0)
+	bne.s	go_oldgemdos
+
+	; Simulate pexec mode 3
+	move.l	a6,-(sp)
+	move.l	a0,a6
+	bsr.s	find_prog
+	bsr.s	load_n_reloc
+gohome:
+	move.l	(sp)+,a6
+	rte
+
+find_prog:
+	move	#$2f,-(sp)	; Fgetdta
+	trap	#1		; Gemdos
+	addq	#2,sp
+	move.l	d0,a0
+	move.l	(a0)+,-(sp)
+	move.l	(a0)+,-(sp)
+	move.l	(a0)+,-(sp)
+	move.l	(a0)+,-(sp)
+	move.l	(a0)+,-(sp)
+	move.l	(a0)+,-(sp)
+	move.l	(a0)+,-(sp)
+	move.l	(a0)+,-(sp)
+	move.l	(a0)+,-(sp)
+	move.l	(a0)+,-(sp)
+	move.l	(a0)+,-(sp)
+	move.l	a0,-(sp)
+	move	#$17,-(sp)
+	move.l	2(a6),-(sp)
+	move	#$4e,-(sp)	; Fsfirst
+	trap	#1		; Gemdos
+	addq	#8,sp
+	move.l	(sp)+,a0
+	move.l	(sp)+,-(a0)
+	move.l	(sp)+,-(a0)
+	move.l	(sp)+,-(a0)
+	move.l	(sp)+,-(a0)
+	move.l	(sp)+,-(a0)
+	move.l	(sp)+,-(a0)
+	move.l	(sp)+,-(a0)
+	move.l	(sp)+,-(a0)
+	move.l	(sp)+,-(a0)
+	move.l	(sp)+,-(a0)
+	move.l	(sp)+,-(a0)
+	tst.l	d0
+	beq.s	findprog_ok
+	addq	#4,sp
+	bra.s	gohome
+findprog_ok:
+	rts
+
+
+load_n_reloc:
+	movem.l	a3-a5/d6,-(sp)
+
+	clr.w	-(sp)
+	move.l	2(a6),-(sp)
+	move.w	#$3d,-(sp)	; Fopen
+	trap	#1		; Gemdos
+	addq	#8,sp
+	move.l	d0,d6		; Keep file handle in d6
+	tst.l	d0
+	bmi	lr_err_out
+
+	clr.w	-(sp)		; Temporary space for prg header magic
+	move.l	sp,-(sp)
+	move.l	#2,-(sp)
+	move	d6,-(sp)
+	move	#$3f,-(sp)	; Fread
+	trap	#1		; Gemdos: Read header magic
+	lea 	12(sp),sp
+	move.w	(sp)+,d1
+	cmp.l	#2,d0
+	bne	load_reloc_error
+
+	cmp.w	#$601a,d1	; Check program header magic
+	beq.s	hdr_magic_ok
+	move.l	#-66,d0		; Error code: Invalid PRG format
+	bra	load_reloc_error
+hdr_magic_ok:
+	clr.w	-(sp)
+	move.w	d6,-(sp)
+	move.l	#22,-(sp)	; offset of the program flags
+	move.w	#66,-(sp)	; Fseek
+	trap	#1		; Gemdos: Seek to program flags
+	lea	10(sp),sp
+	cmp.l	#22,d0
+	bne	load_reloc_error
+
+	clr.l	-(sp)		; Temporary space for program flags
+	move.l	sp,-(sp)
+	move.l	#4,-(sp)
+	move	d6,-(sp)
+	move	#$3f,-(sp)	; Fread
+	trap	#1		; Gemdos: Read program flags
+	lea 	12(sp),sp
+	move.l	(sp)+,a3	; Program flags now in a3
+	cmp.l	#4,d0
+	bne	load_reloc_error
+
+	; Let's call Pexec now to create the basepage, first try
+	; Pexec(7) and if that does not work fall back to mode 5
+	move.l	10(a6),-(sp)
+	move.l	6(a6),-(sp)
+	move.l	a3,-(sp)	; program flags in program header
+	move.w	#7,-(sp)	; Create basepage wrt program flags
+	move.w	#$4b,-(sp)	; Pexec (mode 7)
+	trap	#1		; Gemdos
+	lea	16(sp),sp
+	tst.l	d0
+	bpl.s	pexec_ok
+
+	move.l	10(a6),-(sp)
+	move.l	6(a6),-(sp)
+	clr.l	-(sp)
+	move.w	#5,-(sp)	; Create basepage
+	move.w	#$4b,-(sp)	; Pexec (mode 5)
+	trap	#1		; Gemdos
+	lea	16(sp),sp
+	tst.l	d0
+	bmi	load_reloc_error
+
+pexec_ok:
+	move.l	d0,a5		; Basepage in a5
+
+	clr.w	-(sp)
+	move.w	d6,-(sp)
+	clr.l	-(sp)		; Back to the start of the file
+	move.w	#66,-(sp)	; Fseek
+	trap	#1		; Gemdos: Seek to start of the file
+	lea	10(sp),sp
+	tst.l	d0
+	bne	lr_err_free
+
+	lea	256(a5),a3	; a3 points now to the program header
+	move.l	a3,-(sp)
+	move.l	#$1c,-(sp)
+	move	d6,-(sp)
+	move	#$3f,-(sp)	; Fread
+	trap	#1		; Gemdos: Read full program header
+	lea 	12(sp),sp
+	cmp.l	#$1c,d0
+	bne	lr_err_free
+
+	lea	8(a5),a4
+	move.l	a5,d0
+	add.l	#$100,d0
+	move.l	d0,(a4)+	; text start
+	move.l	2(a3),d0
+	move.l	d0,(a4)+	; text length
+	add.l	8(a5),d0
+	move.l	d0,(a4)+	; data start
+	move.l	6(a3),(a4)+	; data length
+	add.l	6(a3),d0
+	move.l	d0,(a4)+	; bss start
+	move.l	10(a3),(a4)+	; bss length
+
+	add.l	10(a3),d0
+	cmp.l	4(a5),d0	; is the TPA big enough?
+	bhi	tpa_not_ok
+
+	move.l	a5,d0
+	add.l	#$80,d0
+	move.l	d0,32(a5)	; default DTA always points to cmd line space!
+
+	move.l	24(a5),a4
+	add.l	14(a3),a4	; add symtab length => a4 points to reloc table
+	move.w	26(a3),a3	; a3 is now the absflag (0 means reloc)
+
+	pea	256(a5)
+	pea	$7fffffff
+	move	d6,-(sp)
+	move	#$3f,-(sp)	; Fread
+	trap	#1		; Gemdos
+	lea	12(sp),sp
+
+	move	d6,-(sp)
+	move	#$3e,-(sp)	; Fclose
+	trap	#1		; Gemdos
+	addq	#4,sp
+
+	move.w	a3,d1
+	tst.w	d1		; check absflag
+	bne.s	relocdone
+
+	move.l	8(a5),a3
+	move.l	a3,d0
+
+	; Get first offset of the relocation table. Since A4 seems sometimes not
+	; to be word aligned (if symbol table length is uneven), we have to read
+	; byte by byte...
+	move.b	(a4),d1
+	clr.b	(a4)+
+	lsl.w	#8,d1
+	move.b	(a4),d1
+	clr.b	(a4)+
+	swap	d1
+	move.b	(a4),d1
+	clr.b	(a4)+
+	lsl.w	#8,d1
+	move.b	(a4),d1
+	clr.b	(a4)+
+
+	tst.l	d1
+	beq.s	relocdone
+	adda.l	d1,a3
+	moveq	#0,d1
+relloop0:
+	add.l	d0,(a3)
+relloop:
+	move.b	(a4),d1
+	clr.b	(a4)+	; Some programs like GFA-Basic expect a clear memory
+	tst.b	d1
+	beq.s	relocdone
+	cmp.b	#1,d1
+	bne.s	no254
+	lea 	254(a3),a3
+	bra.s	relloop
+no254:
+	adda.w	d1,a3
+	bra.s	relloop0
+
+relocdone:
+	move.l	28(a5),d0
+	beq.s	cleardone
+	move.l	24(a5),a0
+clear:
+	clr.b	(a0)+
+	subq.l	#1,d0
+	bne.s	clear
+cleardone:
+	move.l	a5,d0
+	movem.l	(sp)+,a3-a5/d6
+	rts
+
+tpa_not_ok:
+	move.l	#-39,d0		; Error code: Not enough memory
+lr_err_free:
+	move.l	d0,-(sp)
+	move.l	a5,-(sp)
+	move.w	#$49,-(sp)	; Mfree
+	trap	#1		; Release "pexeced" memory
+	addq.l	#6,sp
+	move.l	(sp)+,d0
+load_reloc_error:
+	move.w	d6,-(sp)
+	move.l	d0,d6		; Save error code
+	move.w	#$3e,-(sp)	; Fclose
+	trap	#1		; Gemdos
+	addq	#4,sp
+	move.l	d6,d0		; Restore error code
+lr_err_out:
+	movem.l	(sp)+,a3-a5/d6
+	addq	#4,sp		; Drop return address
+	bra	gohome		; Abort
+
+
+
+; This code is called during TOS' boot sequence.
+; It gets a pointer to the Line-A variables and uses an illegal opcode
+; to run our system initialization code in OpCode_SysInit().
+sys_init:
+	dc.w	$A000			; Line-A init (needed for VDI resolutions)
+	dc.w	SYSINIT_OPCODE	; Illegal opcode to call OpCode_SysInit()
+	rts
+
+
+
+; This code is run when the user starts the HATARI.PRG
+; in the cartridge. It simply displays some information text.
+infoprgstart:
+	pea 	hatarix32(pc)
+	move.w	#32,-(sp)
+	trap	#14				; Dosound - play some music :-)
+	addq.l	#6,sp
+
+	pea 	infotext(pc)
+	move.w	#9,-(sp)
+	trap	#1				; Cconws - display the information text
+	addq.l	#6,sp
+
+	move.w	#7,-(sp)
+	trap	#1				; Crawcin - wait for a key
+	addq.l	#2,sp
+
+	clr.w	-(sp)
+	trap	#1				; Pterm0
+
+
+infotext:
+	dc.b	27,'E',13,10
+	dc.b	'        =========================',13,10
+	dc.b	'        Hatari keyboard shortcuts',13,10
+	dc.b	'        =========================',13,10
+	dc.b	13,10
+	dc.b	' F11 : toggle fullscreen/windowed mode',13,10
+	dc.b	' F12 : activate the setup GUI of Hatari',13,10
+	dc.b	13,10
+	dc.b	'All other shortcuts are activated by',13,10
+	dc.b	'pressing AltGr or Right-Alt or Meta key',13,10
+	dc.b	'together with one of the following keys:',13,10
+	dc.b	13,10
+	dc.b	' a : Record animation',13,10
+	dc.b	' g : Grab a screenshot',13,10
+	dc.b	' i : Leave full screen & iconify window',13,10
+	dc.b	' j : joystick via key joystick on/off',13,10
+	dc.b	' m : mouse grab',13,10
+	dc.b	' r : warm reset of the ST',13,10
+	dc.b	' c : cold reset of the ST',13,10
+	dc.b	' s : enable/disable sound',13,10
+	dc.b	' q : quit the emulator',13,10
+	dc.b	' x : toggle normal/max speed',13,10
+	dc.b	' y : enable/disable sound recording',13,10
+	dc.b	0
+
+
+hatarix32:
+	ibytes	'cart_mus.x32'
+
+
+infoprgend:
+
+	END
diff --git a/src/cart_mus.x32 b/src/cart_mus.x32
new file mode 100644
index 0000000..b1d2ca3
Binary files /dev/null and b/src/cart_mus.x32 differ
diff --git a/src/cfgopts.c b/src/cfgopts.c
new file mode 100644
index 0000000..4912a7b
--- /dev/null
+++ b/src/cfgopts.c
@@ -0,0 +1,468 @@
+/*
+ * Hatari - cfgopts.c
+ *
+ * The functions in this file are used to load and save the ASCII
+ * configuration file.
+ * Original information text follows:
+ */
+/*<<---------------[         cfgopts.c        ]------------------------/
+/                                                                      /
+/  Functional                                                          /
+/     Description: Configuration file I/O                              /
+/                                                                      /
+/  Input         : Configuration file name                             /
+/                  Configuration parameters in a structure             /
+/                                                                      /
+/  Process       : Interpret information by parameter and read or      /
+/                  write back to the configuration file.               /
+/                                                                      /
+/  Ouput         : updated configuration file or updated structure.    /
+/                                                                      /
+/  Programmer    : Jeffry J. Brickley                                  /
+/                                                                      /
+/                                                                      /
+/---------------------------------------------------------------------*/
+
+/*---------------------------------------------------------------------/
+/
+/  Description:  CfgOpts is based on GETOPTS by Bob Stout.  It will
+/                process a configuration file based one words and
+/                store it in a structure pointing to physical data
+/                area for each storage item.
+/  i.e. ???.CFG:
+/    Port=1
+/    work_space=C:\temp
+/    menus=TRUE
+/    user=Jeffry Brickley
+/  will write to the following structure:
+/    struct Config_Tag configs[] = {
+/    {"port",       Int_Tag,    &port_number},
+/    {"work_space", String_Tag,  &work_space},
+/    {"menus",      Bool_Tag, &menu_flag},
+/    {"user",       String_Tag,  &User_name},
+/    {NULL,         Error_Tag,   NULL}
+/    };
+/  Note that the structure must always be terminated by a NULL row as
+/     was the same with GETOPTS.  This however is slightly more
+/     complicated than scaning the command line (but not by much) for
+/     data as there can be more variety in words than letters and an
+/     number of data items limited only by memory.
+/
+/  Like the original code from which this was taken, this is released
+/  to the Public Domain.  I cannot make any guarantees other than these
+/  work for me and I find them useful.  Feel free to pass these on to
+/  a friend, but please do not charge him....
+/
+/---------------------------------------------------------------------*/
+const char CfgOpts_fileid[] = "Hatari cfgopts.c : " __DATE__ " " __TIME__;
+
+#include 
+#include 
+#include 
+
+#include "main.h"
+#include "cfgopts.h"
+#include "str.h"
+
+
+static int parse_input_config_entry(const struct Config_Tag *ptr)
+{
+	const char *next;
+	int type = ptr->type;
+
+	/* get actual config value */
+	next = Str_Trim(strtok(NULL, "="));
+	if (next == NULL)
+	{
+		if (type == String_Tag)
+			next = ""; /* field with empty string */
+		else
+			type = Error_Tag;
+	}
+
+	switch (type)      /* check type */
+	{
+	 case Bool_Tag:
+		if (!strcasecmp(next,"FALSE"))
+			*(bool *)ptr->buf = false;
+		else if (!strcasecmp(next,"TRUE"))
+			*(bool *)ptr->buf = true;
+		break;
+
+	 case Char_Tag:
+		sscanf(next, "%c", (char *)ptr->buf);
+		break;
+
+	 case Short_Tag:
+		sscanf(next, "%hd", (short *)ptr->buf);
+		break;
+
+	 case Int_Tag:
+		sscanf(next, "%d", (int *)ptr->buf);
+		break;
+
+	 case Long_Tag:
+		sscanf(next, "%ld", (long *)ptr->buf);
+		break;
+
+	 case Float_Tag:
+		sscanf(next, "%g", (float *)ptr->buf);
+		break;
+
+	 case Double_Tag:
+		sscanf(next, "%lg", (double *)ptr->buf);
+		break;
+
+	 case String_Tag:
+		strcpy((char *)ptr->buf, next);
+		break;
+
+	 case Error_Tag:
+	 default:
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * ---------------------------------------------------------------------/
+ * /   reads from an input configuration (INI) file.
+ * /---------------------------------------------------------------------
+ * >>------[   input_config()   ]-------------[ 08-02-95 14:02PM ]------/
+ * / return value:
+ * /     int                     ; number of records read or -1 on error
+ * / parameters:
+ * /     char *filename          ; filename of INI style file
+ * /     struct Config_Tag configs[]; Configuration structure
+ * /     char *header            ; INI header name (i.e. "[TEST]")
+ * /-------------------------------------------------------------------<<
+ */
+int input_config(const char *filename, const struct Config_Tag configs[], const char *header)
+{
+	const struct Config_Tag *ptr;
+	int count = 0, lineno = 0;
+	FILE *file;
+	char *fptr,*tok;
+	char line[1024];
+
+	file = fopen(filename,"r");
+	if (file == NULL)
+		return -1;                 /* return error designation. */
+
+	if (header != NULL)
+	{
+		do
+		{
+			fptr = Str_Trim(fgets(line, sizeof(line), file));  /* get input line */
+			if (fptr == NULL)
+				break;
+		}
+		while (memcmp(fptr,header,strlen(header)));
+	}
+
+	if ( !feof(file) )
+		do
+		{
+			fptr = Str_Trim(fgets(line, sizeof(line), file));   /* get input line */
+			if (fptr == NULL)
+				continue;
+			lineno++;
+			if (fptr[0] == '#')
+				continue;                       /* skip comments */
+			if (fptr[0] == '[')
+				continue;                       /* skip next header */
+			tok = Str_Trim(strtok(fptr, "="));      /* get first token */
+			if (tok == NULL)
+				continue;
+			for (ptr = configs; ptr->buf; ++ptr)    /* scan for token */
+			{
+				if (!strcmp(tok, ptr->code))    /* got a match? */
+				{
+					if (parse_input_config_entry(ptr) == 0)
+						count++;
+					else
+						printf("Error in Config file %s on line %d\n",
+						       filename, lineno);
+				}
+			}
+		}
+		while (fptr != NULL && fptr[0] != '[');
+
+	fclose(file);
+	return count;
+}
+
+
+/**
+ *  Write out an settings line
+ */
+static int write_token(FILE *outfile, const struct Config_Tag *ptr)
+{
+	fprintf(outfile,"%s = ",ptr->code);
+
+	switch (ptr->type)    /* check type */
+	{
+	 case Bool_Tag:
+		fprintf(outfile,"%s\n", *((bool *)(ptr->buf)) ? "TRUE" : "FALSE");
+		break;
+
+	 case Char_Tag:
+		fprintf(outfile, "%c\n", *((char *)(ptr->buf)));
+		break;
+
+	 case Short_Tag:
+		fprintf(outfile, "%hd\n", *((short *)(ptr->buf)));
+		break;
+
+	 case Int_Tag:
+		fprintf(outfile, "%d\n", *((int *)(ptr->buf)));
+		break;
+
+	 case Long_Tag:
+		fprintf(outfile, "%ld\n", *((long *)(ptr->buf)));
+		break;
+
+	 case Float_Tag:
+		fprintf(outfile, "%g\n", *((float *)ptr->buf));
+		break;
+
+	 case Double_Tag:
+		fprintf(outfile, "%g\n", *((double *)ptr->buf));
+		break;
+
+	 case String_Tag:
+		fprintf(outfile, "%s\n",(char *)ptr->buf);
+		break;
+
+	 case Error_Tag:
+	 default:
+		fprintf(stderr, "Error in Config structure (Contact author).\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+
+/**
+ * Write given section header and tokens for that
+ * Return number of written tokens
+ */
+static int write_header_tokens(FILE *fp, const struct Config_Tag *ptr, const char *header)
+{
+	int count = 0;
+
+	if (header != NULL)
+	{
+		fprintf(fp, "%s\n", header);
+	}
+
+	for (; ptr->buf; ++ptr)        /* scan for token */
+	{
+		if (write_token(fp, ptr) == 0)
+			++count;
+	}
+
+	fprintf(fp, "\n");
+
+	return count;
+}
+
+
+/**
+ * ---------------------------------------------------------------------/
+ * /   updates an input configuration (INI) file from a structure.
+ * /---------------------------------------------------------------------
+ * >>------[   update_config()  ]-------------[ 08-02-95 14:02PM ]------/
+ * / return value:
+ * /     int                     ; Number of records read & updated
+ * / parameters:
+ * /     char *filename          ; filename of INI file
+ * /     struct Config_Tag configs[]; Configuration structure
+ * /     char *header            ; INI header name (i.e. "[TEST]")
+ * /-------------------------------------------------------------------<<
+ */
+int update_config(const char *filename, const struct Config_Tag configs[], const char *header)
+{
+	const struct Config_Tag *ptr;
+	int count=0, lineno=0, retval;
+	FILE *cfgfile, *tempfile;
+	char *fptr, *tok;
+	char line[1024];
+	bool bUseTempCfg = false;
+	const char *sTempCfgName = "_temp_.cfg";
+
+	cfgfile = fopen(filename, "r");
+
+	/* If the cfg file does not yet exists, we can create it directly: */
+	if (cfgfile == NULL)
+	{
+		cfgfile = fopen(filename, "w");
+		if (cfgfile == NULL)
+			return -1;                             /* return error designation. */
+		count = write_header_tokens(cfgfile, configs, header);
+		fclose(cfgfile);
+		return count;
+	}
+
+	tempfile = tmpfile();                        /* Open a temporary file for output */
+ 	if (tempfile == NULL)
+ 	{
+		/* tmpfile() failed, let's try a normal open */
+		tempfile = fopen(sTempCfgName, "w+");
+		bUseTempCfg = true;
+	}
+	if (tempfile == NULL)
+	{
+		perror("update_config");
+		fclose(cfgfile);
+		return -1;                         /* return error designation. */
+	}
+
+	if (header != NULL)
+	{
+		int headerlen = strlen(header);
+		do
+		{
+			fptr = Str_Trim(fgets(line, sizeof(line), cfgfile));  /* get input line */
+			if (fptr == NULL)
+				break;
+			fprintf(tempfile, "%s\n", fptr);
+		}
+		while(memcmp(fptr, header, headerlen));
+	}
+
+	if (feof(cfgfile))
+	{
+		count += write_header_tokens(tempfile, configs, header);
+	}
+	else
+	{
+		char *savedtokenflags = NULL;   /* Array to log the saved tokens */
+		int numtokens = 0;              /* Total number of tokens to save */
+
+		/* Find total number of tokens: */
+		for (ptr=configs; ptr->buf; ++ptr)
+		{
+			numtokens += 1;
+		}
+		if (numtokens)
+		{
+			savedtokenflags = malloc(numtokens * sizeof(char));
+			if (savedtokenflags)
+				memset(savedtokenflags, 0, numtokens * sizeof(char));
+		}
+
+		for(;;)
+		{
+			fptr = Str_Trim(fgets(line, sizeof(line), cfgfile));  /* get input line */
+			/* error or eof? */
+			if (fptr == NULL)
+				break;
+			lineno++;
+			if (fptr[0] == '#')
+			{
+				fprintf(tempfile, "%s\n", fptr);
+				continue;                                 /* skip comments */
+			}
+			if (fptr[0] == '[')
+			{
+				break;
+			}
+
+			tok = Str_Trim(strtok(fptr, "="));               /* get first token */
+			if (tok != NULL)
+			{
+				int i = 0;
+				for (ptr = configs; ptr->buf; ++ptr, i++) /* scan for token */
+				{
+					if (!strcmp(tok, ptr->code))           /* got a match? */
+					{
+						if (write_token(tempfile, ptr) == 0)
+						{
+							if (savedtokenflags)
+								savedtokenflags[i] = true;
+							count += 1;
+						}
+					}
+				}
+			}
+		}
+
+		/* Write remaining (new?) tokens that were not in the configuration file, yet */
+		if (count != numtokens && savedtokenflags != NULL)
+		{
+			int i;
+			for (ptr = configs, i = 0; ptr->buf; ++ptr, i++)
+			{
+				if (!savedtokenflags[i])
+				{
+					if (write_token(tempfile, ptr) == 0)
+					{
+						count += 1;
+						fprintf(stderr, "Wrote new token %s -> %s \n", header, ptr->code);
+					}
+				}
+			}
+		}
+
+		if (savedtokenflags)
+		{
+			free(savedtokenflags);
+			savedtokenflags = NULL;
+		}
+
+		if (!feof(cfgfile) && fptr != NULL)
+			fprintf(tempfile, "\n%s\n", line);
+
+		for(;;)
+		{
+			fptr = Str_Trim(fgets(line, sizeof(line), cfgfile));  /* get input line */
+			if (fptr == NULL)
+				break;
+			fprintf(tempfile, "%s\n", fptr);
+		}
+	}
+
+
+	/* Re-open the config file for writing: */
+	fclose(cfgfile);
+	cfgfile = fopen(filename, "wb");
+	if (cfgfile == NULL || fseek(tempfile, 0, SEEK_SET) != 0)
+	{
+		retval = -1;
+		goto cleanup;
+	}
+
+	/* Now copy the temporary file to the configuration file: */
+	retval = count;
+	while(!(feof(tempfile) || ferror(cfgfile)))
+	{
+		size_t copycount;
+		copycount = fread(line, sizeof(char), sizeof(line), tempfile);
+		if (copycount == 0)
+			break;
+		if (fwrite(line, sizeof(char), copycount, cfgfile) != copycount)
+		{
+			retval = -1;
+			break;
+		}
+	}
+cleanup:
+	if (cfgfile)
+	{
+		if (ferror(cfgfile))
+			perror("update_config");
+		fclose(cfgfile);
+	}
+	if (tempfile)
+	{
+		/* tmpfile() is removed automatically on close */
+		fclose(tempfile);
+		if (bUseTempCfg)
+			unlink(sTempCfgName);
+	}
+	return retval;
+}
+
diff --git a/src/change.c b/src/change.c
new file mode 100644
index 0000000..8f9a48f
--- /dev/null
+++ b/src/change.c
@@ -0,0 +1,580 @@
+/*
+  Hatari - change.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  This code handles run-time configuration changes. We keep all our
+  configuration details in a structure called 'ConfigureParams'.  Before
+  doing he changes, a backup copy is done of this structure. When
+  the changes are done, these are compared to see whether emulator
+  needs to be rebooted
+*/
+const char Change_fileid[] = "Hatari change.c : " __DATE__ " " __TIME__;
+
+#include 
+#include "main.h"
+#include "configuration.h"
+#include "audio.h"
+#include "change.h"
+#include "dialog.h"
+#include "floppy.h"
+#include "fdc.h"
+#include "gemdos.h"
+#include "hdc.h"
+#include "ide.h"
+#include "ioMem.h"
+#include "joy.h"
+#include "keymap.h"
+#include "m68000.h"
+#include "midi.h"
+#include "options.h"
+#include "printer.h"
+#include "reset.h"
+#include "rs232.h"
+#include "screen.h"
+#include "sound.h"
+#include "statusbar.h"
+#include "tos.h"
+#include "vdi.h"
+#include "video.h"
+#include "hatari-glue.h"
+#if ENABLE_DSP_EMU
+# include "falcon/dsp.h"
+#endif
+
+#define DEBUG 0
+#if DEBUG
+#define Dprintf(a...) printf(a)
+#else
+#define Dprintf(a...)
+#endif
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Check if user needs to be warned that changes will take place after reset.
+ * Return true if wants to reset.
+ */
+bool Change_DoNeedReset(CNF_PARAMS *current, CNF_PARAMS *changed)
+{
+	int i;
+
+	/* Did we change monitor type? If so, must reset */
+	if (current->Screen.nMonitorType != changed->Screen.nMonitorType
+	    && (changed->System.nMachineType == MACHINE_FALCON
+	        || current->Screen.nMonitorType == MONITOR_TYPE_MONO
+	        || changed->Screen.nMonitorType == MONITOR_TYPE_MONO))
+		return true;
+
+	/* Did change to GEM VDI display? */
+	if (current->Screen.bUseExtVdiResolutions != changed->Screen.bUseExtVdiResolutions)
+		return true;
+
+	/* Did change GEM resolution or color depth? */
+	if (changed->Screen.bUseExtVdiResolutions &&
+	    (current->Screen.nVdiWidth != changed->Screen.nVdiWidth
+	     || current->Screen.nVdiHeight != changed->Screen.nVdiHeight
+	     || current->Screen.nVdiColors != changed->Screen.nVdiColors))
+		return true;
+
+	/* Did change TOS ROM image? */
+	if (strcmp(changed->Rom.szTosImageFileName, current->Rom.szTosImageFileName))
+		return true;
+
+	/* Did change ACSI hard disk image? */
+	for (i = 0; i < MAX_ACSI_DEVS; i++)
+	{
+		if (changed->Acsi[i].bUseDevice != current->Acsi[i].bUseDevice
+		    || (strcmp(changed->Acsi[i].sDeviceFile, current->Acsi[i].sDeviceFile)
+		        && changed->Acsi[i].bUseDevice))
+			return true;
+	}
+
+	/* Did change IDE master hard disk image? */
+	if (changed->HardDisk.bUseIdeMasterHardDiskImage != current->HardDisk.bUseIdeMasterHardDiskImage
+	    || strcmp(changed->HardDisk.szIdeMasterHardDiskImage, current->HardDisk.szIdeMasterHardDiskImage))
+		return true;
+
+	/* Did change IDE slave hard disk image? */
+	if (changed->HardDisk.bUseIdeSlaveHardDiskImage != current->HardDisk.bUseIdeSlaveHardDiskImage
+	    || strcmp(changed->HardDisk.szIdeSlaveHardDiskImage, current->HardDisk.szIdeSlaveHardDiskImage))
+		return true;
+
+	/* Did change GEMDOS drive Atari/host location or enabling? */
+	if (changed->HardDisk.nGemdosDrive != current->HardDisk.nGemdosDrive
+	    || changed->HardDisk.bUseHardDiskDirectories != current->HardDisk.bUseHardDiskDirectories
+	    || (strcmp(changed->HardDisk.szHardDiskDirectories[0], current->HardDisk.szHardDiskDirectories[0])
+	        && changed->HardDisk.bUseHardDiskDirectories))
+		return true;
+
+	/* Did change machine type? */
+	if (changed->System.nMachineType != current->System.nMachineType)
+		return true;
+	/* did change ST Blitter? */
+	else if (current->System.nMachineType == MACHINE_ST &&
+		 current->System.bBlitter != changed->System.bBlitter)
+		return true;
+
+#if ENABLE_DSP_EMU
+	/* enabling DSP needs reset (disabling it not) */
+	if (current->System.nDSPType != DSP_TYPE_EMU &&
+	    changed->System.nDSPType == DSP_TYPE_EMU)
+		return true;
+#endif
+
+	/* did change CPU type? */
+	if (changed->System.nCpuLevel != current->System.nCpuLevel)
+		return true;
+
+#if ENABLE_WINUAE_CPU
+	/* Did change CPU address mode? */
+	if (changed->System.bAddressSpace24 != current->System.bAddressSpace24)
+		return true;
+
+	/* Did change CPU prefetch mode? */
+	if (changed->System.bCompatibleCpu != current->System.bCompatibleCpu)
+		return true;
+
+	/* Did change CPU cycle exact? */
+	if (changed->System.bCycleExactCpu != current->System.bCycleExactCpu)
+		return true;
+
+	/* Did change MMU? */
+	if (changed->System.bMMU != current->System.bMMU)
+		return true;
+ 
+	/* Did change FPU? */
+	if (changed->System.n_FPUType != current->System.n_FPUType)
+		return true;
+
+	/* Did change size of TT-RAM? */
+	if (current->Memory.nTTRamSize != changed->Memory.nTTRamSize)
+		return true;
+#endif
+
+	/* Did change size of memory? */
+	if (current->Memory.nMemorySize != changed->Memory.nMemorySize)
+		return true;
+
+	/* MIDI related IRQs start/stop needs reset */
+	if (current->Midi.bEnableMidi != changed->Midi.bEnableMidi)
+		return true;
+
+	return false;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Copy details back to configuration and perform reset.
+ */
+void Change_CopyChangedParamsToConfiguration(CNF_PARAMS *current, CNF_PARAMS *changed, bool bForceReset)
+{
+	bool NeedReset;
+	bool bReInitGemdosDrive = false;
+	bool bReInitAcsiEmu = false;
+	bool bReInitIDEEmu = false;
+	bool bReInitIoMem = false;
+	bool bScreenModeChange = false;
+	bool bReInitMidi = false;
+	bool bReInitPrinter = false;
+	bool bFloppyInsert[MAX_FLOPPYDRIVES];
+	int i;
+
+	Dprintf("Changes for:\n");
+	/* Do we need to warn user that changes will only take effect after reset? */
+	if (bForceReset)
+		NeedReset = bForceReset;
+	else
+		NeedReset = Change_DoNeedReset(current, changed);
+
+	/* Do need to change resolution? Need if change display/overscan settings
+	 * (if switch between Colour/Mono cause reset later) or toggle statusbar
+	 */
+	if (!NeedReset &&
+	    (changed->Screen.nForceBpp != current->Screen.nForceBpp
+	     || changed->Screen.bAspectCorrect != current->Screen.bAspectCorrect
+	     || changed->Screen.nMaxWidth != current->Screen.nMaxWidth
+	     || changed->Screen.nMaxHeight != current->Screen.nMaxHeight
+	     || changed->Screen.bAllowOverscan != current->Screen.bAllowOverscan
+	     || changed->Screen.bShowStatusbar != current->Screen.bShowStatusbar
+#if WITH_SDL2
+	     || changed->Screen.nRenderScaleQuality != current->Screen.nRenderScaleQuality
+	     || changed->Screen.bUseVsync != current->Screen.bUseVsync
+#endif
+	    ))
+	{
+		Dprintf("- screenmode>\n");
+		bScreenModeChange = true;
+	}
+
+	/* Did set new printer parameters? */
+	if (changed->Printer.bEnablePrinting != current->Printer.bEnablePrinting
+	    || strcmp(changed->Printer.szPrintToFileName,current->Printer.szPrintToFileName))
+	{
+		Dprintf("- printer>\n");
+		Printer_UnInit();
+		bReInitPrinter = true;
+	}
+
+	/* Did set new RS232 parameters? */
+	if (changed->RS232.bEnableRS232 != current->RS232.bEnableRS232
+	    || strcmp(changed->RS232.szOutFileName, current->RS232.szOutFileName)
+	    || strcmp(changed->RS232.szInFileName, current->RS232.szInFileName))
+	{
+		Dprintf("- RS-232>\n");
+		RS232_UnInit();
+	}
+
+	/* Did stop sound? Or change playback Hz. If so, also stop sound recording */
+	if (!changed->Sound.bEnableSound || changed->Sound.nPlaybackFreq != current->Sound.nPlaybackFreq)
+	{
+		Dprintf("- sound>\n");
+		if (Sound_AreWeRecording())
+			Sound_EndRecording();
+		Audio_UnInit();
+	}
+
+	/* Did change floppy (images)? */
+	for (i = 0; i < MAX_FLOPPYDRIVES; i++)
+	{
+		/*
+		Log_Printf(LOG_DEBUG, "Old and new disk %c:\n\t%s\n\t%s", 'A'+i,
+			   current->DiskImage.szDiskFileName[i],
+			   changed->DiskImage.szDiskFileName[i]);
+		 */
+		if (strcmp(changed->DiskImage.szDiskFileName[i],
+			   current->DiskImage.szDiskFileName[i])
+		    || strcmp(changed->DiskImage.szDiskZipPath[i],
+			      current->DiskImage.szDiskZipPath[i]))
+			bFloppyInsert[i] = true;
+		else
+			bFloppyInsert[i] = false;
+	}
+
+	if ( changed->DiskImage.EnableDriveA != current->DiskImage.EnableDriveA )
+		FDC_Drive_Set_Enable ( 0 , changed->DiskImage.EnableDriveA );
+	if ( changed->DiskImage.EnableDriveB != current->DiskImage.EnableDriveB )
+		FDC_Drive_Set_Enable ( 1 , changed->DiskImage.EnableDriveB );
+
+	if ( changed->DiskImage.DriveA_NumberOfHeads != current->DiskImage.DriveA_NumberOfHeads )
+		FDC_Drive_Set_NumberOfHeads ( 0 , changed->DiskImage.DriveA_NumberOfHeads );
+	if ( changed->DiskImage.DriveB_NumberOfHeads != current->DiskImage.DriveB_NumberOfHeads )
+		FDC_Drive_Set_NumberOfHeads ( 1 , changed->DiskImage.DriveB_NumberOfHeads );
+
+	/* Did change GEMDOS drive Atari/host location or enabling? */
+	if (changed->HardDisk.nGemdosDrive != current->HardDisk.nGemdosDrive
+	    || changed->HardDisk.bUseHardDiskDirectories != current->HardDisk.bUseHardDiskDirectories
+	    || (strcmp(changed->HardDisk.szHardDiskDirectories[0], current->HardDisk.szHardDiskDirectories[0])
+	        && changed->HardDisk.bUseHardDiskDirectories))
+	{
+		Dprintf("- gemdos HD>\n");
+		GemDOS_UnInitDrives();
+		bReInitGemdosDrive = true;
+	}
+
+	/* Did change ACSI image? */
+	for (i = 0; i < MAX_ACSI_DEVS; i++)
+	{
+		if (changed->Acsi[i].bUseDevice != current->Acsi[i].bUseDevice
+		    || (strcmp(changed->Acsi[i].sDeviceFile, current->Acsi[i].sDeviceFile)
+		        && changed->Acsi[i].bUseDevice))
+		{
+			Dprintf("- ACSI image %i>\n", i);
+			bReInitAcsiEmu = true;
+		}
+	}
+	if (bReInitAcsiEmu)
+		HDC_UnInit();
+
+	/* Did change IDE HD master image? */
+	if (changed->HardDisk.bUseIdeMasterHardDiskImage != current->HardDisk.bUseIdeMasterHardDiskImage
+	    || (strcmp(changed->HardDisk.szIdeMasterHardDiskImage, current->HardDisk.szIdeMasterHardDiskImage)
+	        && changed->HardDisk.bUseIdeMasterHardDiskImage))
+	{
+		Dprintf("- IDE master>\n");
+		Ide_UnInit();
+		bReInitIDEEmu = true;
+	}
+
+	/* Did change IDE HD slave image? */
+	if (changed->HardDisk.bUseIdeSlaveHardDiskImage != current->HardDisk.bUseIdeSlaveHardDiskImage
+	    || (strcmp(changed->HardDisk.szIdeSlaveHardDiskImage, current->HardDisk.szIdeSlaveHardDiskImage)
+	        && changed->HardDisk.bUseIdeSlaveHardDiskImage))
+	{
+		Dprintf("- IDE slave>\n");
+		Ide_UnInit();
+		bReInitIDEEmu = true;
+	}
+
+	/* Did change blitter, rtc or system type? */
+	if (changed->System.bBlitter != current->System.bBlitter
+#if ENABLE_DSP_EMU
+	    || changed->System.nDSPType != current->System.nDSPType
+#endif
+	    || changed->System.bRealTimeClock != current->System.bRealTimeClock
+	    || changed->System.nMachineType != current->System.nMachineType)
+	{
+		Dprintf("- blitter/rtc/dsp/machine>\n");
+		IoMem_UnInit();
+		bReInitIoMem = true;
+	}
+	
+#if ENABLE_DSP_EMU
+	/* Disabled DSP? */
+	if (current->System.nDSPType == DSP_TYPE_EMU &&
+	    changed->System.nDSPType != DSP_TYPE_EMU)
+	{
+		Dprintf("- DSP>\n");
+		DSP_Disable();
+	}
+#endif
+
+	/* Did change MIDI settings? */
+	if (current->Midi.bEnableMidi != changed->Midi.bEnableMidi
+	    || ((strcmp(changed->Midi.sMidiOutFileName, current->Midi.sMidiOutFileName)
+	         || strcmp(changed->Midi.sMidiInFileName, current->Midi.sMidiInFileName))
+	        && changed->Midi.bEnableMidi))
+	{
+		Dprintf("- midi>\n");
+		Midi_UnInit();
+		bReInitMidi = true;
+	}
+
+	/* Copy details to configuration,
+	 * so it can be saved out or set on reset
+	 */
+	if (changed != &ConfigureParams)
+	{
+		ConfigureParams = *changed;
+	}
+
+	/* Copy details to global, if we reset copy them all */
+	Configuration_Apply(NeedReset);
+
+#if ENABLE_DSP_EMU
+	if (current->System.nDSPType != DSP_TYPE_EMU &&
+	    changed->System.nDSPType == DSP_TYPE_EMU)
+	{
+		Dprintf("- DSP<\n");
+		DSP_Enable();
+	}
+#endif
+
+	/* Set keyboard remap file */
+	if (ConfigureParams.Keyboard.nKeymapType == KEYMAP_LOADED)
+	{
+		Dprintf("- keymap<\n");
+		Keymap_LoadRemapFile(ConfigureParams.Keyboard.szMappingFileName);
+	}
+
+	/* Mount a new HD image: */
+	if (bReInitAcsiEmu)
+	{
+		Dprintf("- HD<\n");
+		HDC_Init();
+	}
+
+	/* Mount a new IDE HD master or slave image: */
+	if (bReInitIDEEmu && (ConfigureParams.HardDisk.bUseIdeMasterHardDiskImage || ConfigureParams.HardDisk.bUseIdeSlaveHardDiskImage))
+	{
+		Dprintf("- IDE<\n");
+		Ide_Init();
+	}
+
+	/* Insert floppies? */
+	for (i = 0; i < MAX_FLOPPYDRIVES; i++)
+	{
+		if (bFloppyInsert[i])
+		{
+			Dprintf("- floppy<\n");
+			Floppy_InsertDiskIntoDrive(i);
+		}
+	}
+
+	/* Mount a new GEMDOS drive? */
+	if (bReInitGemdosDrive && ConfigureParams.HardDisk.bUseHardDiskDirectories)
+	{
+		Dprintf("- gemdos HD<\n");
+		GemDOS_InitDrives();
+	}
+
+	/* Restart audio sub system if necessary: */
+	if (ConfigureParams.Sound.bEnableSound && !bSoundWorking)
+	{
+		Dprintf("- audio<\n");
+		Audio_Init();
+	}
+
+	/* Re-initialize the RS232 emulation: */
+	if (ConfigureParams.RS232.bEnableRS232)
+	{
+		Dprintf("- RS-232<\n");
+		RS232_Init();
+	}
+
+	/* Re-init IO memory map? */
+	if (bReInitIoMem)
+	{
+		Dprintf("- IO mem<\n");
+		IoMem_Init();
+	}
+
+	/* Re-init Printer emulation? */
+	if (bReInitPrinter)
+	{
+		Dprintf("- printer<\n");
+		Printer_Init();
+	}
+
+	/* Re-init MIDI emulation? */
+	if (bReInitMidi)
+	{
+		Dprintf("- midi<\n");
+		Midi_Init();
+	}
+
+	/* Force things associated with screen change */
+	if (bScreenModeChange)
+	{
+		Dprintf("- screenmode<\n");
+		Screen_ModeChanged(true);
+	}
+
+	/* Do we need to perform reset? */
+	if (NeedReset)
+	{
+		Dprintf("- reset\n");
+		Reset_Cold();
+	}
+
+	/* Go into/return from full screen if flagged */
+	if (!bInFullScreen && ConfigureParams.Screen.bFullScreen)
+		Screen_EnterFullScreen();
+	else if (bInFullScreen && !ConfigureParams.Screen.bFullScreen)
+		Screen_ReturnFromFullScreen();
+
+	/* update statusbar info (CPU, MHz, mem etc) */
+	Statusbar_UpdateInfo();
+	Dprintf("done.\n");
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Change given Hatari options
+ * Return false if parsing failed, true otherwise
+ */
+static bool Change_Options(int argc, const char *argv[])
+{
+	bool bOK;
+	CNF_PARAMS current;
+
+	Main_PauseEmulation(false);
+
+	/* get configuration changes */
+	current = ConfigureParams;
+	ConfigureParams.Screen.bFullScreen = bInFullScreen;
+	bOK = Opt_ParseParameters(argc, argv);
+
+	/* Check if reset is required and ask user if he really wants to continue */
+	if (bOK && Change_DoNeedReset(¤t, &ConfigureParams)
+	    && current.Log.nAlertDlgLogLevel > LOG_FATAL) {
+		bOK = DlgAlert_Query("The emulated system must be "
+				     "reset to apply these changes. "
+				     "Apply changes now and reset "
+				     "the emulator?");
+	}
+	/* Copy details to configuration */
+	if (bOK) {
+		Change_CopyChangedParamsToConfiguration(¤t, &ConfigureParams, false);
+	} else {
+		ConfigureParams = current;
+	}
+
+	Main_UnPauseEmulation();
+	return bOK;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Parse given command line and change Hatari options accordingly.
+ * Given string must be stripped and not empty.
+ * Return false if parsing failed or there were no args, true otherwise
+ */
+bool Change_ApplyCommandline(char *cmdline)
+{
+	int i, argc, inarg;
+	const char **argv;
+	bool ret;
+
+	/* count args */
+	inarg = argc = 0;
+	for (i = 0; cmdline[i]; i++)
+	{
+		if (isspace((unsigned char)cmdline[i]) && cmdline[i-1] != '\\')
+		{
+			inarg = 0;
+			continue;
+		}
+		if (!inarg)
+		{
+			inarg++;
+			argc++;
+		}
+	}
+	if (!argc)
+	{
+		return false;
+	}
+	/* 2 = "hatari" + NULL */
+	argv = malloc((argc+2) * sizeof(char*));
+	if (!argv)
+	{
+		perror("command line alloc");
+		return false;
+	}
+
+	/* parse them to array */
+	fprintf(stderr, "Command line with '%d' arguments:\n", argc);
+	inarg = argc = 0;
+	argv[argc++] = "hatari";
+	for (i = 0; cmdline[i]; i++)
+	{
+		if (isspace((unsigned char)cmdline[i]))
+		{
+			if (cmdline[i-1] != '\\')
+			{
+				cmdline[i] = '\0';
+				if (inarg)
+				{
+					fprintf(stderr, "- '%s'\n", argv[argc-1]);
+				}
+				inarg = 0;
+				continue;
+			}
+			else
+			{
+				/* remove quote for space */
+				memcpy(cmdline+i-1, cmdline+i, strlen(cmdline+i)+1);
+				i--;
+			}
+		}
+		if (!inarg)
+		{
+			argv[argc++] = &(cmdline[i]);
+			inarg++;
+		}
+	}
+	if (inarg)
+	{
+		fprintf(stderr, "- '%s'\n", argv[argc-1]);
+	}
+	argv[argc] = NULL;
+	
+	/* do args */
+	ret = Change_Options(argc, argv);
+	free((void *)argv);
+	return ret;
+}
diff --git a/src/clocks_timings.c b/src/clocks_timings.c
new file mode 100644
index 0000000..b820ee3
--- /dev/null
+++ b/src/clocks_timings.c
@@ -0,0 +1,503 @@
+/*
+  Hatari - clocks_timings.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Clocks Timings for the hardware components in each supported machine type,
+  as well as functions taking into account the exact length of a VBL to
+  precisely emulate video/audio parts (number of VBL per sec, number of
+  audio samples per VBL, ...)
+
+  The video freq is not exactly 50 or 60 Hz because the number of cpu cycles
+  per second is not a multiple of the number of cpu cycles per VBL.
+  This can cause synchronisation errors between audio and video effects
+  when both components use different clocks (eg in STE where audio DMA clock
+  is not the same as the cpu clock).
+
+  To get the best results, it's recommanded to set RoundVBLPerSec=false.
+
+  Note that if you do so, the number of VBL won't be exactly 50 or 60 per sec
+  but 50.05 or 60.04 ; if this does not work with your display, set RoundVBLPerSec=true
+  to get an integer number of VBL per sec (but this should not be needed).
+
+
+
+ST :
+  MCLK		= 32 MHz
+  SHIFTER	IN = 32 MHz					OUT = 16 MHz
+  MMU		IN = 16 MHz					OUT = 8 MHz, 4 MHz
+  GLUE		IN = 8 MHz					OUT = 2 MHz, 500 kHz
+  BUS		= 8 MHz
+
+  CPU 68000	IN = 8 MHz
+  DMA		IN = 8 MHz
+  MFP 68901	IN = 4 MHz, 2.4576 MHz (external clock)
+  FDC WD1772	IN = 8 MHz
+  BLITTER	IN = 8 MHz
+  YM2149	IN = 2 MHz
+  ACIA MC6850	IN = 500 kHz
+  IKBD HD6301	IN = 1 MHZ (local clock)
+
+
+STE :
+  MCLK		= 32 MHz
+  EXT OSC	= 8 MHZ						OUT = 8 MHz (SCLK), 2 MHz (CLK2)
+  GST SHIFTER	IN = 32 MHz, 8 MHz (external clock SCLK)	OUT = 16 MHz, 8 MHz (FCLK=SCLK)
+  GST MCU	IN = 16 MHz					OUT = 8 MHz (CLK8), 4 MHz (CLK4), 500 kHz (KHZ500)
+  BUS		= 8 MHz
+
+  CPU 68000	IN = 8 MHz (CLK8)
+  DMA		IN = 8 MHz (CLK8)
+  DMA AUDIO	IN = 8 MHz (SCLK)
+  MFP 68901	IN = 4 MHz (CLK4), 2.4576 MHz (external clock)
+  FDC WD1772	IN = 8 MHz (SCLK)
+  BLITTER	IN = 8 MHz (CLK8)
+  YM2149	IN = 2 MHz (CLK2)
+  ACIA MC6850	IN = 500 kHz (KHZ500)
+  IKBD HD6301	IN = 1 MHZ (local clock)
+
+
+MEGA STE :
+  MCLK		= 32 MHz
+  SCLK		= 8 MHz
+  GST SHIFTER	IN = 32 MHz, 8 MHz (external clock SCLK)	OUT = 16 MHz (CLK16), 8 MHz (FCLK=SCLK)
+  GST MCU	IN = 16 MHz (CLK16)				OUT = 8 MHz (CLK8), 4 MHz (CLK4), 500 kHz (KHZ500)
+  BUS		= 8 MHz
+
+  CPU 68000	IN = 16 MHz (CLK16)
+  FPU 68881	IN = 16 MHz (CLK16)
+  DMA		IN = 8 MHz (CLK8)
+  DMA AUDIO	IN = 8 MHz (SCLK)
+  MFP 68901	IN = 4 MHz (CLK4), 2.4576 MHz (external clock)
+  FDC WD1772	IN = 8 MHz (SCLK)
+  BLITTER	IN = 8 MHz (CLK8)
+  YM2149	IN = 2 MHz (CLK2 = SCLK / 4)
+  ACIA MC6850	IN = 500 kHz (KHZ500)
+  IKBD HD6301	IN = 1 MHZ (local clock)
+
+
+TT :
+  MCLK		= 32 MHz (CLK32)
+  TT VIDEO	IN = 32 MHz (CLK32)				OUT = 16 MHz (CLK16), 4 MHz (CLK4), 2 MHz (CLK2)
+  GST MCU	IN = 16 MHz (CLK16A), 2 MHz (CLK2)		OUT = 8 MHz (CLK8), 8 MHz (FCCLK), 1 MHz (CLKE), 500 kHz (CLKX5)
+  BUS		= 16 MHz
+
+  CPU 68030	IN = 32 MHz (CLK32)
+  FPU 68882	IN = 32 MHz (CLK32)
+  DMA		IN = 8 MHz (CLK8)
+  SND SHIFTER	IN = 16 MHz (CLK16F), 2 MHz (CLK2)		OUT = ? MHz (FCLK)
+  MFP 68901	IN = 4 MHz (CLK4), 2.4576 MHz (external clock)	NOTE : TT has 2 MFPs 68901
+  FDC WD1772	IN = 8 MHz (FCCLK)
+  BLITTER	NOT AVAILABLE
+  YM2149	IN = 2 MHz (CLK2)
+  ACIA MC6850	IN = 500 kHz (CLKX5)
+  IKBD HD6301	IN = 1 MHZ (local clock)
+
+
+FALCON :
+  MCLK		= 32 MHz (CLK32)
+  VIDEL	IN 	= 32 MHz (VID32MHZ), 25 MHz (25K)
+  COMBEL	IN = 32 MHz (CLK32)				OUT = 4 MHz (CLK4), 500 kHz (KHZ500)
+  BUS		= 16 MHz
+
+  CPU 68030	IN = 16 MHz (CPUCLKB)
+  FPU 68882	IN = 16 MHz (CPUCLKA)
+  DMA		IN = 8 MHz (CLK8)
+  CODEC		IN = 25 MHz (25K)
+  MFP 68901	IN = 4 MHz (CLK4), 2.4576 MHz (external clock)
+  FDC AJAX	IN = 16 MHz (FCCLK)
+  BLITTER	IN = 16 MHz
+  YM3439	IN = 2 MHz (CLK2)
+  ACIA MC6850	IN = 500 kHz (KHZ500)
+  IKBD HD6301	IN = 1 MHZ (local clock)
+
+  DSP 56001	IN = 32 MHz (DSP_32M)
+
+*/
+
+
+const char ClocksTimings_fileid[] = "Hatari clocks_timings.c : " __DATE__ " " __TIME__;
+
+#include 
+#include 
+
+#include "main.h"
+#include "configuration.h"
+#include "log.h"
+#include "clocks_timings.h"
+
+
+
+/* The possible master frequencies used in the different machines */
+/* depending on PAL/NTSC version. */
+
+#define ATARI_STF_PAL_MCLK		32084988			/* CPU_Freq = 8.021247 MHz */
+#define ATARI_STF_NTSC_MCLK		32042400			/* CPU_Freq = 8.010600 MHz */
+#define ATARI_STF_CYCLES_PER_VBL_PAL	160256				/* 512 cycles * 313 lines */
+#define ATARI_STF_CYCLES_PER_VBL_NTSC	133604				/* 508 cycles * 263 lines */
+#define ATARI_STF_CYCLES_PER_VBL_HI	112224				/* 224 cycles * 501 lines */
+
+#define ATARI_STE_PAL_MCLK		32084988			/* CPU_Freq = 8.021247 MHz */
+#define ATARI_STE_NTSC_MCLK		32215905			/* CPU_Freq = 8.05397625 MHz */
+#define ATARI_STE_EXT_OSC		8010613				/* OSC U303 */
+#define ATARI_STE_CYCLES_PER_VBL_PAL	160256				/* 512 cycles * 313 lines */
+#define ATARI_STE_CYCLES_PER_VBL_NTSC	133604				/* 508 cycles * 263 lines */
+#define ATARI_STE_CYCLES_PER_VBL_HI	112224				/* 224 cycles * 501 lines */
+
+#define ATARI_MEGA_STE_PAL_MCLK		32084988			/* CPU_Freq = 16.042494 MHz */
+#define ATARI_MEGA_STE_NTSC_MCLK	32215905			/* CPU_Freq = 16.1079525 MHz */
+#define ATARI_MEGA_STE_EXT_OSC		16021226			/* OSC U408 */
+
+#define ATARI_TT_PAL_MCLK		32084988			/* CPU_Freq = 32.084988 MHz */
+#define ATARI_TT_NTSC_MCLK		32215905			/* CPU_Freq = 32.215905 MHz */
+
+#define ATARI_FALCON_PAL_MCLK		32084988			/* CPU_Freq = 16.042494 MHz */
+#define ATARI_FALCON_NTSC_MCLK		32215905			/* CPU_Freq = 16.1079525 MHz */
+#define ATARI_FALCON_25M_CLK		25175000
+
+#define ATARI_MFP_XTAL			2457600				/* external clock for the MFP */
+#define ATARI_IKBD_CLK			1000000				/* clock of the HD6301 ikbd cpu */
+
+
+
+CLOCKS_STRUCT	MachineClocks;
+
+
+bool	RoundVBLPerSec = false;						/* if false, don't round number of VBL to 50/60 Hz */
+									/* but compute the exact value based on cpu/video clocks */
+
+
+
+
+/*--------------------------------------------------------------------------*/
+/**
+ * Initialize all the clocks informations related to a specific machine type.
+ * We consider the machine is running with PAL clocks.
+ */
+
+void	ClocksTimings_InitMachine ( MACHINETYPE MachineType )
+{
+	memset ( (void *)&MachineClocks , 0 , sizeof ( MachineClocks ) );
+
+	if ( MachineType == MACHINE_ST )
+	{
+		int	CLK16, CLK8, CLK4, CLK2, CLK500;
+
+		MachineClocks.MCLK_Freq		= ATARI_STF_PAL_MCLK;			/* 32.084988 MHz */
+
+		MachineClocks.SHIFTER_Freq	= MachineClocks.MCLK_Freq;		/* 32 MHz */
+		CLK16				= MachineClocks.SHIFTER_Freq / 2;
+
+		MachineClocks.MMU_Freq		= CLK16;				/* 16 MHz */
+		CLK8				= MachineClocks.MMU_Freq / 2;
+		CLK4				= MachineClocks.MMU_Freq / 4;
+
+		MachineClocks.GLUE_Freq		= CLK8;					/* 8 MHz */
+		CLK2				= MachineClocks.GLUE_Freq / 4;
+		CLK500				= MachineClocks.GLUE_Freq / 16;
+
+		MachineClocks.BUS_Freq		= CLK8;					/* 8 MHz */
+
+		MachineClocks.CPU_Freq		= CLK8;					/* 8 MHz */
+		MachineClocks.DMA_Freq		= CLK8;					/* 8 MHz */
+		MachineClocks.MFP_Freq		= CLK4;					/* 4 MHz */
+		MachineClocks.MFP_Timer_Freq	= ATARI_MFP_XTAL;			/* 2.4576 MHz (XTAL)*/
+		MachineClocks.FDC_Freq		= CLK8;					/* 8 MHz */
+		MachineClocks.BLITTER_Freq	= CLK8;					/* 8 MHz */
+		MachineClocks.YM_Freq		= CLK2;					/* 2 MHz */;
+		MachineClocks.ACIA_Freq		= CLK500;				/* 500 kHz */
+		MachineClocks.IKBD_Freq		= ATARI_IKBD_CLK;			/* 1 MHz */
+	}
+
+	else if ( MachineType == MACHINE_STE )
+	{
+		int	SCLK, CLK16, CLK8, CLK4, CLK2, KHZ500;
+		//int	FCLK;								/* not used (audio filters) */
+
+		MachineClocks.MCLK_Freq		= ATARI_STE_PAL_MCLK;			/* 32.084988 MHz */
+		SCLK				= ATARI_STE_EXT_OSC;			/* 8.010613 MHz (SCLK) */
+		CLK2				= SCLK / 4;
+
+		MachineClocks.SHIFTER_Freq	= MachineClocks.MCLK_Freq;		/* 32 MHz */
+		CLK16				= MachineClocks.SHIFTER_Freq / 2;
+		//FCLK				= SCLK;
+
+		MachineClocks.MCU_Freq		= CLK16;				/* 16 MHz */
+		CLK8				= MachineClocks.MCU_Freq / 2;
+		CLK4				= MachineClocks.MCU_Freq / 4;
+		KHZ500				= MachineClocks.MCU_Freq / 32;
+
+		MachineClocks.BUS_Freq		= CLK8;					/* 8 MHz (CLK8) */
+
+		MachineClocks.CPU_Freq		= CLK8;					/* 8 MHz (CLK8) */
+		MachineClocks.DMA_Freq		= CLK8;					/* 8 MHz (CLK8) */
+		MachineClocks.DMA_Audio_Freq	= SCLK;					/* 8 MHz (SCLK) */
+		MachineClocks.MFP_Freq		= CLK4;					/* 4 MHz (CLK4) */
+		MachineClocks.MFP_Timer_Freq	= ATARI_MFP_XTAL;			/* 2.4576 MHz (XTAL)*/
+		MachineClocks.FDC_Freq		= SCLK;					/* 8 MHz (SCLK) */
+		MachineClocks.BLITTER_Freq	= CLK8;					/* 8 MHz (CLK8) */
+		MachineClocks.YM_Freq		= CLK2;					/* 2 MHz (CLK2) */
+		MachineClocks.ACIA_Freq		= KHZ500;				/* 500 kHz (KHZ500) */
+		MachineClocks.IKBD_Freq		= ATARI_IKBD_CLK;			/* 1 MHz */
+	}
+
+	else if ( MachineType == MACHINE_MEGA_STE )
+	{
+		int	SCLK, CLK16, CLK8, CLK4, CLK2, KHZ500;
+		//int	FCLK;								/* not used (audio filters) */
+
+		MachineClocks.MCLK_Freq		= ATARI_MEGA_STE_PAL_MCLK;		/* 32.084988 MHz */
+		SCLK				= ATARI_MEGA_STE_EXT_OSC / 2;		/* 16.021226 MHz / 2 = 8.010613 MHz */
+		CLK2				= SCLK / 4;
+
+		MachineClocks.SHIFTER_Freq	= MachineClocks.MCLK_Freq;		/* 32 MHz */
+		CLK16				= MachineClocks.SHIFTER_Freq / 2;
+		//FCLK				= SCLK;
+
+		MachineClocks.MCU_Freq		= CLK16;				/* 16 MHz (CLK16) */
+		CLK8				= MachineClocks.MCU_Freq / 2;
+		CLK4				= MachineClocks.MCU_Freq / 4;
+		KHZ500				= MachineClocks.MCU_Freq / 32;
+
+		MachineClocks.BUS_Freq		= CLK8;					/* 8 MHz (CLK8) */
+
+		MachineClocks.CPU_Freq		= CLK16;				/* 16 MHz (CLK16) */
+		MachineClocks.FPU_Freq		= CLK16;				/* 16 MHz (CLK16) */
+		MachineClocks.DMA_Freq		= CLK8;					/* 8 MHz (CLK8) */
+		MachineClocks.DMA_Audio_Freq	= SCLK;					/* 8 MHz (SCLK) */
+		MachineClocks.MFP_Freq		= CLK4;					/* 4 MHz (CLK4) */
+		MachineClocks.MFP_Timer_Freq	= ATARI_MFP_XTAL;			/* 2.4576 MHz (XTAL)*/
+		MachineClocks.FDC_Freq		= SCLK;					/* 8 MHz (SCLK) */
+		MachineClocks.BLITTER_Freq	= CLK8;					/* 8 MHz (CLK8) */
+		MachineClocks.YM_Freq		= CLK2;					/* 2 MHz (CLK2) */
+		MachineClocks.ACIA_Freq		= KHZ500;				/* 500 kHz (KHZ500) */
+		MachineClocks.IKBD_Freq		= ATARI_IKBD_CLK;			/* 1 MHz */
+	}
+
+	else if ( MachineType == MACHINE_TT )
+	{
+		int	CLK32, CLK16, CLK8, FCCLK, CLK4, CLK2, CLKX5;
+
+		MachineClocks.MCLK_Freq		= ATARI_TT_PAL_MCLK;			/* 32.084988 MHz */
+		CLK32				= MachineClocks.MCLK_Freq;
+
+		MachineClocks.TTVIDEO_Freq	= MachineClocks.MCLK_Freq;		/* 32 MHz */
+		CLK16				= MachineClocks.TTVIDEO_Freq / 2;
+		CLK4				= MachineClocks.TTVIDEO_Freq / 8;
+		CLK2				= MachineClocks.TTVIDEO_Freq / 16;
+
+		MachineClocks.MCU_Freq		= CLK16;				/* 16 MHz (CLK16A) */
+		CLK8				= MachineClocks.MCU_Freq / 2;
+		FCCLK				= MachineClocks.MCU_Freq / 2;
+		CLKX5				= MachineClocks.MCU_Freq / 32;
+
+		MachineClocks.BUS_Freq		= CLK16;				/* 16 MHz (CLK16) */
+
+		MachineClocks.CPU_Freq		= CLK32;				/* 32 MHz (CLK32) */
+		MachineClocks.FPU_Freq		= CLK32;				/* 32 MHz (CLK32) */
+		MachineClocks.DMA_Freq		= CLK8;					/* 8 MHz (CLK8) */
+		MachineClocks.DMA_Audio_Freq	= CLK16;				/* 16 MHz (CLK16) SND SHIFTER */
+		MachineClocks.MFP_Freq		= CLK4;					/* 4 MHz (CLK4) */
+		MachineClocks.MFP_Timer_Freq	= ATARI_MFP_XTAL;			/* 2.4576 MHz (XTAL)*/
+		MachineClocks.FDC_Freq		= FCCLK;				/* 8 MHz (FCCLK) */
+		MachineClocks.BLITTER_Freq	= 0;					/* No blitter in TT */
+		MachineClocks.YM_Freq		= CLK2;					/* 2 MHz (CLK2) */
+		MachineClocks.ACIA_Freq		= CLKX5;				/* 500 kHz (CLKX5) */
+		MachineClocks.IKBD_Freq		= ATARI_IKBD_CLK;			/* 1 MHz */
+	}
+
+	else if ( MachineType == MACHINE_FALCON )
+	{
+		/* TODO : need more docs for Falcon's clocks */
+		int	CLK32, CLK25, CLK16, FCCLK, CLK4, CLK2, KHZ500;
+
+		MachineClocks.MCLK_Freq		= ATARI_FALCON_PAL_MCLK;		/* 32.084988 MHz */
+		CLK32				= MachineClocks.MCLK_Freq;
+		CLK25				= ATARI_FALCON_25M_CLK;
+		CLK16				= CLK32 / 2;
+		CLK2				= CLK32 / 16;
+		FCCLK				= CLK16;
+
+		MachineClocks.VIDEL_Freq	= CLK32;				/* 32 MHz */
+
+		MachineClocks.COMBEL_Freq	= CLK32;				/* 16 MHz (CLK16A) */
+		CLK4				= MachineClocks.COMBEL_Freq / 8;
+		KHZ500				= MachineClocks.COMBEL_Freq / 64;
+
+		MachineClocks.BUS_Freq		= CLK16;				/* 16 MHz (CPUCLK16A) */
+		MachineClocks.CPU_Freq		= CLK16;				/* 16 MHz (CPUCLK16B) */
+		MachineClocks.FPU_Freq		= CLK16;				/* 16 MHz (CLK32) */
+		MachineClocks.DSP_Freq		= CLK32;				/* 32 MHz */
+		MachineClocks.DMA_Freq		= CLK16;				/* 16 MHz (CLK16) ? */
+		MachineClocks.CODEC_Freq	= CLK25;				/* 25 MHz (CLK25) */
+		MachineClocks.MFP_Freq		= CLK4;					/* 4 MHz (CLK4) */
+		MachineClocks.MFP_Timer_Freq	= ATARI_MFP_XTAL;			/* 2.4576 MHz (XTAL)*/
+		MachineClocks.FDC_Freq		= FCCLK;				/* 16 MHz (FCCLK) ? */
+		MachineClocks.BLITTER_Freq	= CLK16;				/* 16 MHz */
+		MachineClocks.YM_Freq		= CLK2;					/* 2 MHz (CLK2) */
+		MachineClocks.ACIA_Freq		= KHZ500;				/* 500 kHz (KHZ500) */
+		MachineClocks.IKBD_Freq		= ATARI_IKBD_CLK;			/* 1 MHz */
+	}
+
+
+}
+
+
+
+
+
+/*-----------------------------------------------------------------------------------------*/
+/**
+ * Return the number of VBL per second, depending on the video settings and the cpu freq.
+ * This value is only known for STF/STE running at 50, 60 or 71 Hz.
+ * For the other machines, we return CPU_Freq / ScreenRefreshRate
+ */
+
+Uint32	ClocksTimings_GetCyclesPerVBL ( MACHINETYPE MachineType , int ScreenRefreshRate )
+{
+	Uint32	CyclesPerVBL;
+
+
+	CyclesPerVBL = MachineClocks.CPU_Freq / ScreenRefreshRate;			/* default value */
+
+	/* STF and STE have the same numbers of cycles per VBL */
+	if ( ( MachineType == MACHINE_ST ) || ( MachineType == MACHINE_STE ) )
+	{
+		if ( ScreenRefreshRate == 50 )
+			CyclesPerVBL = ATARI_STF_CYCLES_PER_VBL_PAL;
+		else if ( ScreenRefreshRate == 60 )
+			CyclesPerVBL = ATARI_STF_CYCLES_PER_VBL_NTSC;
+		else if ( ScreenRefreshRate == 71 )
+			CyclesPerVBL = ATARI_STF_CYCLES_PER_VBL_HI;
+		else
+			CyclesPerVBL = MachineClocks.CPU_Freq / ScreenRefreshRate;	/* should not happen */
+	}
+
+	/* For machines where cpu freq can be changed, we don't know the number of cycles per VBL */
+	/* -> TODO, for now comment code to keep the default value from above */
+	//else if ( ( MachineType == MACHINE_MEGA_STE ) || ( MachineType == MACHINE_TT ) || ( MachineType == MACHINE_FALCON ) )
+	//	CyclesPerVBL = MachineClocks.CPU_Freq / ScreenRefreshRate;
+
+
+	return CyclesPerVBL;
+}
+
+
+
+
+/*-----------------------------------------------------------------------------------------*/
+/**
+ * Return the number of VBL per second, depending on the video settings and the cpu freq.
+ * Since the cpu freq is not an exact multiple of the number of cycles per VBL, the real
+ * value slightly differs from the usual 50/60 Hz.
+ * Precise values are needed in STE mode to synchronize cpu and dma sound (as they both use
+ * 2 different clocks).
+ * example for STF/STE :
+ *	PAL  STF/STE video PAL :	50.053 VBL/sec
+ *	PAL  STF/STE video NTSC :	60.037 VBL/sec
+ *	NTSC STF/STE video PAL :	49.986 VBL/sec
+ *	NTSC STF/STE video NTSC :	59.958 VBL/sec
+ *
+ * The returned number of VBL per sec is << 24 (=CLOCKS_TIMINGS_SHIFT_VBL) to simulate floating point using Uint32.
+ */
+
+Uint32	ClocksTimings_GetVBLPerSec ( MACHINETYPE MachineType , int ScreenRefreshRate )
+{
+	Uint32	VBLPerSec;							/* Upper 8 bits are for int part, 24 lower bits for float part */
+
+
+	VBLPerSec = ScreenRefreshRate << CLOCKS_TIMINGS_SHIFT_VBL;		/* default rounded value */
+
+	if ( RoundVBLPerSec == false )
+	{
+		/* STF and STE have the same numbers of cycles per VBL */
+		if ( ( MachineType == MACHINE_ST ) || ( MachineType == MACHINE_STE ) )
+			VBLPerSec = ( (Sint64)MachineClocks.CPU_Freq << CLOCKS_TIMINGS_SHIFT_VBL ) / ClocksTimings_GetCyclesPerVBL ( MachineType , ScreenRefreshRate );
+
+		/* For machines where cpu freq can be changed, we don't know the number of cycles per VBL */
+		/* -> TODO, for now comment code to keep the default value from above */
+		//else if ( ( MachineType == MACHINE_MEGA_STE ) || ( MachineType == MACHINE_TT ) || ( MachineType == MACHINE_FALCON ) )
+		//	VBLPerSec = ScreenRefreshRate << CLOCKS_TIMINGS_SHIFT_VBL;
+	}
+
+
+	return VBLPerSec;
+}
+
+
+
+
+/*-----------------------------------------------------------------------------------------*/
+/**
+ * Return the length in microsec of a VBL (opposite function of ClocksTimings_GetVBLPerSec)
+ * We use precise values only in STF/STE mode, else we use 1000000 / ScreenRefreshRate.
+ * example for STF/STE :
+ *	PAL  STF/STE video PAL :	19979 micro sec  (instead of 20000 for 50 Hz)
+ *	PAL  STF/STE video NTSC :	16656 micro sec  (instead of 16667 for 60 Hz)
+ */
+
+Uint32	ClocksTimings_GetVBLDuration_micro ( MACHINETYPE MachineType , int ScreenRefreshRate )
+{
+	Uint32	VBLDuration_micro;
+
+
+	VBLDuration_micro = (Uint32) (1000000.0 / ScreenRefreshRate + 0.5);	/* default rounded value, round to closest integer */
+
+	if ( RoundVBLPerSec == false )
+	{
+		/* STF and STE have the same numbers of cycles per VBL */
+		if ( ( MachineType == MACHINE_ST ) || ( MachineType == MACHINE_STE ) )
+			VBLDuration_micro = (Uint32) (1000000.0 * ClocksTimings_GetCyclesPerVBL ( MachineType , ScreenRefreshRate ) / MachineClocks.CPU_Freq + 0.5);
+
+		/* For machines where cpu freq can be changed, we don't know the number of cycles per VBL */
+		/* -> TODO, for now comment code to keep the default value from above */
+		//else if ( ( MachineType == MACHINE_MEGA_STE ) || ( MachineType == MACHINE_TT ) || ( MachineType == MACHINE_FALCON ) )
+		//	VBLDuration_micro = (Uint32) (1000000.0 / ScreenRefreshRate + 0.5);
+	}
+
+
+	return VBLDuration_micro;
+}
+
+
+
+
+/*-----------------------------------------------------------------------------------------*/
+/**
+ * Return the number of samples needed to emulate the sound that was produced during one VBL.
+ * This depends on the chosen audio output frequency, as well as the VBL's duration,
+ *
+ * We use precise values only in STF/STE mode, else we use AudioFreq/ScreenRefreshRate.
+ *
+ * The returned number of samples per VBL is << 28 to simulate maximum precision using
+ * 64 bits integers (lower 28 bits are for the floating point part).
+ * example for STF/STE with emulation's audio freq = 44100 :
+ *	PAL  STF/STE video PAL :	881.07 samples per VBL  (instead of 882 for 50 Hz)
+ *					44053.56 samples for 50 VBLs (instead of 44100 for 1 sec at 50 Hz)
+ */
+
+Sint64	ClocksTimings_GetSamplesPerVBL ( MACHINETYPE MachineType , int ScreenRefreshRate , int AudioFreq )
+{
+	Sint64	SamplesPerVBL;
+
+
+	SamplesPerVBL = ( ((Sint64)AudioFreq) << 28 ) / ScreenRefreshRate;		/* default value */
+
+	if ( RoundVBLPerSec == false )
+	{
+		/* STF and STE have the same numbers of cycles per VBL */
+		if ( ( MachineType == MACHINE_ST ) || ( MachineType == MACHINE_STE ) )
+			SamplesPerVBL = ( ((Sint64)AudioFreq * ClocksTimings_GetCyclesPerVBL ( MachineType , ScreenRefreshRate ) ) << 28 ) / MachineClocks.CPU_Freq;
+
+		/* For machines where cpu freq can be changed, we don't know the number of cycles per VBL */
+		/* -> TODO, for now comment code to keep the default value from above */
+		//else if ( ( MachineType == MACHINE_MEGA_STE ) || ( MachineType == MACHINE_TT ) || ( MachineType == MACHINE_FALCON ) )
+		//	SamplesPerVBL = ( ((Sint64)AudioFreq) << 28 ) / ScreenRefreshRate;
+	}
+
+
+	return SamplesPerVBL;
+}
+
+
diff --git a/src/configuration.c b/src/configuration.c
new file mode 100644
index 0000000..425a66e
--- /dev/null
+++ b/src/configuration.c
@@ -0,0 +1,1172 @@
+/*
+  Hatari - configuration.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Configuration File
+
+  The configuration file is now stored in an ASCII format to allow the user
+  to edit the file manually.
+*/
+const char Configuration_fileid[] = "Hatari configuration.c : " __DATE__ " " __TIME__;
+
+#include 
+
+#include "main.h"
+#include "configuration.h"
+#include "cfgopts.h"
+#include "audio.h"
+#include "sound.h"
+#include "file.h"
+#include "log.h"
+#include "m68000.h"
+#include "memorySnapShot.h"
+#include "paths.h"
+#include "screen.h"
+#include "statusbar.h"
+#include "vdi.h"
+#include "video.h"
+#include "avi_record.h"
+#include "clocks_timings.h"
+#include "68kDisass.h"
+#include "fdc.h"
+#include "dsp.h"
+#include "joy.h"
+
+
+CNF_PARAMS ConfigureParams;                 /* List of configuration for the emulator */
+char sConfigFileName[FILENAME_MAX];         /* Stores the name of the configuration file */
+
+
+/* Used to load/save logging options */
+static const struct Config_Tag configs_Log[] =
+{
+	{ "sLogFileName", String_Tag, ConfigureParams.Log.sLogFileName },
+	{ "sTraceFileName", String_Tag, ConfigureParams.Log.sTraceFileName },
+	{ "nExceptionDebugMask", Int_Tag, &ConfigureParams.Log.nExceptionDebugMask },
+	{ "nTextLogLevel", Int_Tag, &ConfigureParams.Log.nTextLogLevel },
+	{ "nAlertDlgLogLevel", Int_Tag, &ConfigureParams.Log.nAlertDlgLogLevel },
+	{ "bConfirmQuit", Bool_Tag, &ConfigureParams.Log.bConfirmQuit },
+	{ "bNatFeats", Bool_Tag, &ConfigureParams.Log.bNatFeats },
+	{ "bConsoleWindow", Bool_Tag, &ConfigureParams.Log.bConsoleWindow },
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save debugger options */
+static const struct Config_Tag configs_Debugger[] =
+{
+	{ "nNumberBase", Int_Tag, &ConfigureParams.Debugger.nNumberBase },
+	{ "nDisasmLines", Int_Tag, &ConfigureParams.Debugger.nDisasmLines },
+	{ "nMemdumpLines", Int_Tag, &ConfigureParams.Debugger.nMemdumpLines },
+	{ "nDisasmOptions", Int_Tag, &ConfigureParams.Debugger.nDisasmOptions },
+	{ "bDisasmUAE", Bool_Tag, &ConfigureParams.Debugger.bDisasmUAE },
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save screen options */
+static const struct Config_Tag configs_Screen[] =
+{
+	{ "nMonitorType", Int_Tag, &ConfigureParams.Screen.nMonitorType },
+	{ "nFrameSkips", Int_Tag, &ConfigureParams.Screen.nFrameSkips },
+	{ "bFullScreen", Bool_Tag, &ConfigureParams.Screen.bFullScreen },
+	{ "bKeepResolution", Bool_Tag, &ConfigureParams.Screen.bKeepResolution },
+	{ "bKeepResolutionST", Bool_Tag, &ConfigureParams.Screen.bKeepResolutionST },
+	{ "bAllowOverscan", Bool_Tag, &ConfigureParams.Screen.bAllowOverscan },
+	{ "nSpec512Threshold", Int_Tag, &ConfigureParams.Screen.nSpec512Threshold },
+	{ "nForceBpp", Int_Tag, &ConfigureParams.Screen.nForceBpp },
+	{ "bAspectCorrect", Bool_Tag, &ConfigureParams.Screen.bAspectCorrect },
+	{ "bUseExtVdiResolutions", Bool_Tag, &ConfigureParams.Screen.bUseExtVdiResolutions },
+	{ "nVdiWidth", Int_Tag, &ConfigureParams.Screen.nVdiWidth },
+	{ "nVdiHeight", Int_Tag, &ConfigureParams.Screen.nVdiHeight },
+	{ "nVdiColors", Int_Tag, &ConfigureParams.Screen.nVdiColors },
+	{ "bMouseWarp", Bool_Tag, &ConfigureParams.Screen.bMouseWarp },
+	{ "bShowStatusbar", Bool_Tag, &ConfigureParams.Screen.bShowStatusbar },
+	{ "bShowDriveLed", Bool_Tag, &ConfigureParams.Screen.bShowDriveLed },
+	{ "bCrop", Bool_Tag, &ConfigureParams.Screen.bCrop },
+	{ "bForceMax", Bool_Tag, &ConfigureParams.Screen.bForceMax },
+	{ "nMaxWidth", Int_Tag, &ConfigureParams.Screen.nMaxWidth },
+	{ "nMaxHeight", Int_Tag, &ConfigureParams.Screen.nMaxHeight },
+#ifdef GEKKO
+	{ "nWiiOffset", Int_Tag, &ConfigureParams.Screen.nWiiOffset },
+#endif
+#if WITH_SDL2
+	{ "nRenderScaleQuality", Int_Tag, &ConfigureParams.Screen.nRenderScaleQuality },
+	{ "bUseVsync", Int_Tag, &ConfigureParams.Screen.bUseVsync },
+#endif
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save joystick 0 options */
+static const struct Config_Tag configs_Joystick0[] =
+{
+	{ "nJoystickMode", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nJoystickMode },
+	{ "bEnableAutoFire", Bool_Tag, &ConfigureParams.Joysticks.Joy[0].bEnableAutoFire },
+	{ "bEnableJumpOnFire2", Bool_Tag, &ConfigureParams.Joysticks.Joy[0].bEnableJumpOnFire2 },
+	{ "nJoyId", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nJoyId },
+	{ "nKeyCodeUp", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeyCodeUp },
+	{ "nKeyCodeDown", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeyCodeDown },
+	{ "nKeyCodeLeft", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeyCodeLeft },
+	{ "nKeyCodeRight", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeyCodeRight },
+	{ "nKeyCodeFire", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeyCodeFire },
+#ifdef GEKKO
+	{ "nKeytoJoyWii1But1", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii1Button[0] },
+	{ "nKeytoJoyWii1But2", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii1Button[1] },
+	{ "nKeytoJoyWii1ButMinus", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii1Button[2] },
+	{ "nKeytoJoyClass1ButB", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii1Button[3] },
+	{ "nKeytoJoyClass1ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii1Button[4] },
+	{ "nKeytoJoyClass1ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii1Button[5] },
+	{ "nKeytoJoyGc1ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii1Button[6] },
+	{ "nKeytoJoyGc1ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii1Button[7] },
+	{ "nKeytoJoyGc1ButR", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii1Button[8] },
+	{ "nKeytoJoyWii2But1", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii2Button[0] },
+	{ "nKeytoJoyWii2But2", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii2Button[1] },
+	{ "nKeytoJoyWii2ButMinus", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii2Button[2] },
+	{ "nKeytoJoyClass2ButB", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii2Button[3] },
+	{ "nKeytoJoyClass2ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii2Button[4] },
+	{ "nKeytoJoyClass2ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii2Button[5] },
+	{ "nKeytoJoyGc2ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii2Button[6] },
+	{ "nKeytoJoyGc2ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii2Button[7] },
+	{ "nKeytoJoyGc2ButR", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii2Button[8] },
+	{ "nKeytoJoyWii1Left", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii1Hat[0] },
+	{ "nKeytoJoyWii1Up", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii1Hat[1] },
+	{ "nKeytoJoyWii1Right", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii1Hat[2] },
+	{ "nKeytoJoyWii1Down", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii1Hat[3] },
+	{ "nKeytoJoyWii2Left", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii2Hat[0] },
+	{ "nKeytoJoyWii2Up", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii2Hat[1] },
+	{ "nKeytoJoyWii2Right", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii2Hat[2] },
+	{ "nKeytoJoyWii2Down", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nKeytoJoyWii2Hat[3] },
+	{ "nArrowtoJoy", Int_Tag, &ConfigureParams.Joysticks.Joy[0].nArrowtoJoy },
+#endif
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save joystick 1 options */
+static const struct Config_Tag configs_Joystick1[] =
+{
+	{ "nJoystickMode", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nJoystickMode },
+	{ "bEnableAutoFire", Bool_Tag, &ConfigureParams.Joysticks.Joy[1].bEnableAutoFire },
+	{ "bEnableJumpOnFire2", Bool_Tag, &ConfigureParams.Joysticks.Joy[1].bEnableJumpOnFire2 },
+	{ "nJoyId", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nJoyId },
+	{ "nKeyCodeUp", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeyCodeUp },
+	{ "nKeyCodeDown", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeyCodeDown },
+	{ "nKeyCodeLeft", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeyCodeLeft },
+	{ "nKeyCodeRight", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeyCodeRight },
+	{ "nKeyCodeFire", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeyCodeFire },
+#ifdef GEKKO
+	{ "nKeytoJoyWii1But1", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii1Button[0] },
+	{ "nKeytoJoyWii1But2", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii1Button[1] },
+	{ "nKeytoJoyWii1ButMinus", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii1Button[2] },
+	{ "nKeytoJoyClass1ButB", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii1Button[3] },
+	{ "nKeytoJoyClass1ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii1Button[4] },
+	{ "nKeytoJoyClass1ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii1Button[5] },
+	{ "nKeytoJoyGc1ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii1Button[6] },
+	{ "nKeytoJoyGc1ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii1Button[7] },
+	{ "nKeytoJoyGc1ButR", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii1Button[8] },
+	{ "nKeytoJoyWii2But1", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii2Button[0] },
+	{ "nKeytoJoyWii2But2", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii2Button[1] },
+	{ "nKeytoJoyWii2ButMinus", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii2Button[2] },
+	{ "nKeytoJoyClass2ButB", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii2Button[3] },
+	{ "nKeytoJoyClass2ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii2Button[4] },
+	{ "nKeytoJoyClass2ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii2Button[5] },
+	{ "nKeytoJoyGc2ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii2Button[6] },
+	{ "nKeytoJoyGc2ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii2Button[7] },
+	{ "nKeytoJoyGc2ButR", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii2Button[8] },
+	{ "nKeytoJoyWii1Left", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii1Hat[0] },
+	{ "nKeytoJoyWii1Up", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii1Hat[1] },
+	{ "nKeytoJoyWii1Right", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii1Hat[2] },
+	{ "nKeytoJoyWii1Down", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii1Hat[3] },
+	{ "nKeytoJoyWii2Left", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii2Hat[0] },
+	{ "nKeytoJoyWii2Up", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii2Hat[1] },
+	{ "nKeytoJoyWii2Right", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii2Hat[2] },
+	{ "nKeytoJoyWii2Down", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nKeytoJoyWii2Hat[3] },
+	{ "nArrowtoJoy", Int_Tag, &ConfigureParams.Joysticks.Joy[1].nArrowtoJoy },
+#endif
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save joystick 2 options */
+static const struct Config_Tag configs_Joystick2[] =
+{
+	{ "nJoystickMode", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nJoystickMode },
+	{ "bEnableAutoFire", Bool_Tag, &ConfigureParams.Joysticks.Joy[2].bEnableAutoFire },
+	{ "bEnableJumpOnFire2", Bool_Tag, &ConfigureParams.Joysticks.Joy[2].bEnableJumpOnFire2 },
+	{ "nJoyId", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nJoyId },
+	{ "nKeyCodeUp", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeyCodeUp },
+	{ "nKeyCodeDown", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeyCodeDown },
+	{ "nKeyCodeLeft", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeyCodeLeft },
+	{ "nKeyCodeRight", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeyCodeRight },
+	{ "nKeyCodeFire", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeyCodeFire },
+#ifdef GEKKO
+	{ "nKeytoJoyWii1But1", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii1Button[0] },
+	{ "nKeytoJoyWii1But2", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii1Button[1] },
+	{ "nKeytoJoyWii1ButMinus", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii1Button[2] },
+	{ "nKeytoJoyClass1ButB", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii1Button[3] },
+	{ "nKeytoJoyClass1ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii1Button[4] },
+	{ "nKeytoJoyClass1ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii1Button[5] },
+	{ "nKeytoJoyGc1ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii1Button[6] },
+	{ "nKeytoJoyGc1ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii1Button[7] },
+	{ "nKeytoJoyGc1ButR", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii1Button[8] },
+	{ "nKeytoJoyWii2But1", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii2Button[0] },
+	{ "nKeytoJoyWii2But2", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii2Button[1] },
+	{ "nKeytoJoyWii2ButMinus", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii2Button[2] },
+	{ "nKeytoJoyClass2ButB", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii2Button[3] },
+	{ "nKeytoJoyClass2ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii2Button[4] },
+	{ "nKeytoJoyClass2ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii2Button[5] },
+	{ "nKeytoJoyGc2ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii2Button[6] },
+	{ "nKeytoJoyGc2ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii2Button[7] },
+	{ "nKeytoJoyGc2ButR", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii2Button[8] },
+	{ "nKeytoJoyWii1Left", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii1Hat[0] },
+	{ "nKeytoJoyWii1Up", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii1Hat[1] },
+	{ "nKeytoJoyWii1Right", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii1Hat[2] },
+	{ "nKeytoJoyWii1Down", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii1Hat[3] },
+	{ "nKeytoJoyWii2Left", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii2Hat[0] },
+	{ "nKeytoJoyWii2Up", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii2Hat[1] },
+	{ "nKeytoJoyWii2Right", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii2Hat[2] },
+	{ "nKeytoJoyWii2Down", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nKeytoJoyWii2Hat[3] },
+	{ "nArrowtoJoy", Int_Tag, &ConfigureParams.Joysticks.Joy[2].nArrowtoJoy },
+#endif
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save joystick 3 options */
+static const struct Config_Tag configs_Joystick3[] =
+{
+	{ "nJoystickMode", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nJoystickMode },
+	{ "bEnableAutoFire", Bool_Tag, &ConfigureParams.Joysticks.Joy[3].bEnableAutoFire },
+	{ "bEnableJumpOnFire2", Bool_Tag, &ConfigureParams.Joysticks.Joy[3].bEnableJumpOnFire2 },
+	{ "nJoyId", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nJoyId },
+	{ "nKeyCodeUp", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeyCodeUp },
+	{ "nKeyCodeDown", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeyCodeDown },
+	{ "nKeyCodeLeft", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeyCodeLeft },
+	{ "nKeyCodeRight", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeyCodeRight },
+	{ "nKeyCodeFire", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeyCodeFire },
+#ifdef GEKKO
+	{ "nKeytoJoyWii1But1", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii1Button[0] },
+	{ "nKeytoJoyWii1But2", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii1Button[1] },
+	{ "nKeytoJoyWii1ButMinus", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii1Button[2] },
+	{ "nKeytoJoyClass1ButB", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii1Button[3] },
+	{ "nKeytoJoyClass1ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii1Button[4] },
+	{ "nKeytoJoyClass1ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii1Button[5] },
+	{ "nKeytoJoyGc1ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii1Button[6] },
+	{ "nKeytoJoyGc1ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii1Button[7] },
+	{ "nKeytoJoyGc1ButR", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii1Button[8] },
+	{ "nKeytoJoyWii2But1", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii2Button[0] },
+	{ "nKeytoJoyWii2But2", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii2Button[1] },
+	{ "nKeytoJoyWii2ButMinus", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii2Button[2] },
+	{ "nKeytoJoyClass2ButB", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii2Button[3] },
+	{ "nKeytoJoyClass2ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii2Button[4] },
+	{ "nKeytoJoyClass2ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii2Button[5] },
+	{ "nKeytoJoyGc2ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii2Button[6] },
+	{ "nKeytoJoyGc2ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii2Button[7] },
+	{ "nKeytoJoyGc2ButR", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii2Button[8] },
+	{ "nKeytoJoyWii1Left", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii1Hat[0] },
+	{ "nKeytoJoyWii1Up", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii1Hat[1] },
+	{ "nKeytoJoyWii1Right", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii1Hat[2] },
+	{ "nKeytoJoyWii1Down", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii1Hat[3] },
+	{ "nKeytoJoyWii2Left", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii2Hat[0] },
+	{ "nKeytoJoyWii2Up", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii2Hat[1] },
+	{ "nKeytoJoyWii2Right", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii2Hat[2] },
+	{ "nKeytoJoyWii2Down", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nKeytoJoyWii2Hat[3] },
+	{ "nArrowtoJoy", Int_Tag, &ConfigureParams.Joysticks.Joy[3].nArrowtoJoy },
+#endif
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save joystick 4 options */
+static const struct Config_Tag configs_Joystick4[] =
+{
+	{ "nJoystickMode", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nJoystickMode },
+	{ "bEnableAutoFire", Bool_Tag, &ConfigureParams.Joysticks.Joy[4].bEnableAutoFire },
+	{ "bEnableJumpOnFire2", Bool_Tag, &ConfigureParams.Joysticks.Joy[4].bEnableJumpOnFire2 },
+	{ "nJoyId", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nJoyId },
+	{ "nKeyCodeUp", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeyCodeUp },
+	{ "nKeyCodeDown", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeyCodeDown },
+	{ "nKeyCodeLeft", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeyCodeLeft },
+	{ "nKeyCodeRight", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeyCodeRight },
+	{ "nKeyCodeFire", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeyCodeFire },
+#ifdef GEKKO
+	{ "nKeytoJoyWii1But1", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii1Button[0] },
+	{ "nKeytoJoyWii1But2", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii1Button[1] },
+	{ "nKeytoJoyWii1ButMinus", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii1Button[2] },
+	{ "nKeytoJoyClass1ButB", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii1Button[3] },
+	{ "nKeytoJoyClass1ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii1Button[4] },
+	{ "nKeytoJoyClass1ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii1Button[5] },
+	{ "nKeytoJoyGc1ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii1Button[6] },
+	{ "nKeytoJoyGc1ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii1Button[7] },
+	{ "nKeytoJoyGc1ButR", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii1Button[8] },
+	{ "nKeytoJoyWii2But1", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii2Button[0] },
+	{ "nKeytoJoyWii2But2", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii2Button[1] },
+	{ "nKeytoJoyWii2ButMinus", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii2Button[2] },
+	{ "nKeytoJoyClass2ButB", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii2Button[3] },
+	{ "nKeytoJoyClass2ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii2Button[4] },
+	{ "nKeytoJoyClass2ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii2Button[5] },
+	{ "nKeytoJoyGc2ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii2Button[6] },
+	{ "nKeytoJoyGc2ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii2Button[7] },
+	{ "nKeytoJoyGc2ButR", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii2Button[8] },
+	{ "nKeytoJoyWii1Left", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii1Hat[0] },
+	{ "nKeytoJoyWii1Up", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii1Hat[1] },
+	{ "nKeytoJoyWii1Right", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii1Hat[2] },
+	{ "nKeytoJoyWii1Down", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii1Hat[3] },
+	{ "nKeytoJoyWii2Left", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii2Hat[0] },
+	{ "nKeytoJoyWii2Up", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii2Hat[1] },
+	{ "nKeytoJoyWii2Right", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii2Hat[2] },
+	{ "nKeytoJoyWii2Down", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nKeytoJoyWii2Hat[3] },
+	{ "nArrowtoJoy", Int_Tag, &ConfigureParams.Joysticks.Joy[4].nArrowtoJoy },
+#endif
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save joystick 5 options */
+static const struct Config_Tag configs_Joystick5[] =
+{
+	{ "nJoystickMode", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nJoystickMode },
+	{ "bEnableAutoFire", Bool_Tag, &ConfigureParams.Joysticks.Joy[5].bEnableAutoFire },
+	{ "bEnableJumpOnFire2", Bool_Tag, &ConfigureParams.Joysticks.Joy[5].bEnableJumpOnFire2 },
+	{ "nJoyId", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nJoyId },
+	{ "nKeyCodeUp", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeyCodeUp },
+	{ "nKeyCodeDown", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeyCodeDown },
+	{ "nKeyCodeLeft", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeyCodeLeft },
+	{ "nKeyCodeRight", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeyCodeRight },
+	{ "nKeyCodeFire", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeyCodeFire },
+#ifdef GEKKO
+	{ "nKeytoJoyWii1But1", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii1Button[0] },
+	{ "nKeytoJoyWii1But2", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii1Button[1] },
+	{ "nKeytoJoyWii1ButMinus", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii1Button[2] },
+	{ "nKeytoJoyClass1ButB", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii1Button[3] },
+	{ "nKeytoJoyClass1ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii1Button[4] },
+	{ "nKeytoJoyClass1ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii1Button[5] },
+	{ "nKeytoJoyGc1ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii1Button[6] },
+	{ "nKeytoJoyGc1ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii1Button[7] },
+	{ "nKeytoJoyGc1ButR", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii1Button[8] },
+	{ "nKeytoJoyWii2But1", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii2Button[0] },
+	{ "nKeytoJoyWii2But2", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii2Button[1] },
+	{ "nKeytoJoyWii2ButMinus", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii2Button[2] },
+	{ "nKeytoJoyClass2ButB", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii2Button[3] },
+	{ "nKeytoJoyClass2ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii2Button[4] },
+	{ "nKeytoJoyClass2ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii2Button[5] },
+	{ "nKeytoJoyGc2ButX", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii2Button[6] },
+	{ "nKeytoJoyGc2ButY", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii2Button[7] },
+	{ "nKeytoJoyGc2ButR", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii2Button[8] },
+	{ "nKeytoJoyWii1Left", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii1Hat[0] },
+	{ "nKeytoJoyWii1Up", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii1Hat[1] },
+	{ "nKeytoJoyWii1Right", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii1Hat[2] },
+	{ "nKeytoJoyWii1Down", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii1Hat[3] },
+	{ "nKeytoJoyWii2Left", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii2Hat[0] },
+	{ "nKeytoJoyWii2Up", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii2Hat[1] },
+	{ "nKeytoJoyWii2Right", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii2Hat[2] },
+	{ "nKeytoJoyWii2Down", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nKeytoJoyWii2Hat[3] },
+	{ "nArrowtoJoy", Int_Tag, &ConfigureParams.Joysticks.Joy[5].nArrowtoJoy },
+#endif
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save keyboard options */
+static const struct Config_Tag configs_Keyboard[] =
+{
+	{ "bDisableKeyRepeat", Bool_Tag, &ConfigureParams.Keyboard.bDisableKeyRepeat },
+	{ "nKeymapType", Int_Tag, &ConfigureParams.Keyboard.nKeymapType },
+	{ "szMappingFileName", String_Tag, ConfigureParams.Keyboard.szMappingFileName },
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save shortcut key bindings with modifiers options */
+static const struct Config_Tag configs_ShortCutWithMod[] =
+{
+	{ "keyOptions",    Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_OPTIONS] },
+	{ "keyFullScreen", Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_FULLSCREEN] },
+	{ "keyMouseMode",  Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_MOUSEGRAB] },
+	{ "keyColdReset",  Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_COLDRESET] },
+	{ "keyWarmReset",  Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_WARMRESET] },
+	{ "keyScreenShot", Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_SCREENSHOT] },
+	{ "keyBossKey",    Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_BOSSKEY] },
+	{ "keyCursorEmu",  Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_CURSOREMU] },
+	{ "keyFastForward",Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_FASTFORWARD] },
+	{ "keyRecAnim",    Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_RECANIM] },
+	{ "keyRecSound",   Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_RECSOUND] },
+	{ "keySound",      Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_SOUND] },
+	{ "keyPause",      Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_PAUSE] },
+	{ "keyDebugger",   Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_DEBUG] },
+	{ "keyQuit",       Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_QUIT] },
+	{ "keyLoadMem",    Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_LOADMEM] },
+	{ "keySaveMem",    Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_SAVEMEM] },
+	{ "keyInsertDiskA",Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_INSERTDISKA] },
+	{ "keySwitchJoy0", Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_JOY_0] },
+	{ "keySwitchJoy1", Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_JOY_1] },
+	{ "keySwitchPadA", Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_PAD_A] },
+	{ "keySwitchPadB", Int_Tag, &ConfigureParams.Shortcut.withModifier[SHORTCUT_PAD_B] },
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save shortcut key bindings without modifiers options */
+static const struct Config_Tag configs_ShortCutWithoutMod[] =
+{
+	{ "keyOptions",    Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_OPTIONS] },
+	{ "keyFullScreen", Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_FULLSCREEN] },
+	{ "keyMouseMode",  Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_MOUSEGRAB] },
+	{ "keyColdReset",  Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_COLDRESET] },
+	{ "keyWarmReset",  Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_WARMRESET] },
+	{ "keyScreenShot", Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_SCREENSHOT] },
+	{ "keyBossKey",    Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_BOSSKEY] },
+	{ "keyCursorEmu",  Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_CURSOREMU] },
+	{ "keyFastForward",Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_FASTFORWARD] },
+	{ "keyRecAnim",    Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_RECANIM] },
+	{ "keyRecSound",   Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_RECSOUND] },
+	{ "keySound",      Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_SOUND] },
+	{ "keyPause",      Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_PAUSE] },
+	{ "keyDebugger",   Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_DEBUG] },
+	{ "keyQuit",       Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_QUIT] },
+	{ "keyLoadMem",    Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_LOADMEM] },
+	{ "keySaveMem",    Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_SAVEMEM] },
+	{ "keyInsertDiskA",Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_INSERTDISKA] },
+	{ "keySwitchJoy0", Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_JOY_0] },
+	{ "keySwitchJoy1", Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_JOY_1] },
+	{ "keySwitchPadA", Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_PAD_A] },
+	{ "keySwitchPadB", Int_Tag, &ConfigureParams.Shortcut.withoutModifier[SHORTCUT_PAD_B] },
+	{ NULL , Error_Tag, NULL }
+};
+
+
+/* Used to load/save sound options */
+static const struct Config_Tag configs_Sound[] =
+{
+	{ "bEnableMicrophone", Bool_Tag, &ConfigureParams.Sound.bEnableMicrophone },
+	{ "bEnableSound", Bool_Tag, &ConfigureParams.Sound.bEnableSound },
+	{ "bEnableSoundSync", Bool_Tag, &ConfigureParams.Sound.bEnableSoundSync },
+	{ "nPlaybackFreq", Int_Tag, &ConfigureParams.Sound.nPlaybackFreq },
+	{ "nSdlAudioBufferSize", Int_Tag, &ConfigureParams.Sound.SdlAudioBufferSize },
+	{ "szYMCaptureFileName", String_Tag, ConfigureParams.Sound.szYMCaptureFileName },
+	{ "YmVolumeMixing", Int_Tag, &ConfigureParams.Sound.YmVolumeMixing },
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save memory options */
+static const struct Config_Tag configs_Memory[] =
+{
+	{ "nMemorySize", Int_Tag, &ConfigureParams.Memory.nMemorySize },
+	{ "nTTRamSize", Int_Tag, &ConfigureParams.Memory.nTTRamSize },
+	{ "bAutoSave", Bool_Tag, &ConfigureParams.Memory.bAutoSave },
+	{ "szMemoryCaptureFileName", String_Tag, ConfigureParams.Memory.szMemoryCaptureFileName },
+	{ "szAutoSaveFileName", String_Tag, ConfigureParams.Memory.szAutoSaveFileName },
+	{ NULL , Error_Tag, NULL }
+};
+
+
+/* Used to load/save floppy options */
+static const struct Config_Tag configs_Floppy[] =
+{
+	{ "bAutoInsertDiskB", Bool_Tag, &ConfigureParams.DiskImage.bAutoInsertDiskB },
+	{ "FastFloppy", Bool_Tag, &ConfigureParams.DiskImage.FastFloppy },
+	{ "EnableDriveA", Bool_Tag, &ConfigureParams.DiskImage.EnableDriveA },
+	{ "DriveA_NumberOfHeads", Int_Tag, &ConfigureParams.DiskImage.DriveA_NumberOfHeads },
+	{ "EnableDriveB", Bool_Tag, &ConfigureParams.DiskImage.EnableDriveB },
+	{ "DriveB_NumberOfHeads", Int_Tag, &ConfigureParams.DiskImage.DriveB_NumberOfHeads },
+	{ "nWriteProtection", Int_Tag, &ConfigureParams.DiskImage.nWriteProtection },
+	{ "szDiskAZipPath", String_Tag, ConfigureParams.DiskImage.szDiskZipPath[0] },
+	{ "szDiskAFileName", String_Tag, ConfigureParams.DiskImage.szDiskFileName[0] },
+	{ "szDiskBZipPath", String_Tag, ConfigureParams.DiskImage.szDiskZipPath[1] },
+	{ "szDiskBFileName", String_Tag, ConfigureParams.DiskImage.szDiskFileName[1] },
+	{ "szDiskImageDirectory", String_Tag, ConfigureParams.DiskImage.szDiskImageDirectory },
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save HD options */
+static const struct Config_Tag configs_HardDisk[] =
+{
+	{ "nGemdosDrive", Int_Tag, &ConfigureParams.HardDisk.nGemdosDrive },
+	{ "bBootFromHardDisk", Bool_Tag, &ConfigureParams.HardDisk.bBootFromHardDisk },
+	{ "bUseHardDiskDirectory", Bool_Tag, &ConfigureParams.HardDisk.bUseHardDiskDirectories },
+	{ "szHardDiskDirectory", String_Tag, ConfigureParams.HardDisk.szHardDiskDirectories[DRIVE_C] },
+	{ "nGemdosCase", Int_Tag, &ConfigureParams.HardDisk.nGemdosCase },
+	{ "nWriteProtection", Int_Tag, &ConfigureParams.HardDisk.nWriteProtection },
+	{ "bFilenameConversion", Bool_Tag, &ConfigureParams.HardDisk.bFilenameConversion },
+	{ "bUseHardDiskImage", Bool_Tag, &ConfigureParams.Acsi[0].bUseDevice },
+	{ "szHardDiskImage", String_Tag, ConfigureParams.Acsi[0].sDeviceFile },
+	{ "bUseIdeMasterHardDiskImage", Bool_Tag, &ConfigureParams.HardDisk.bUseIdeMasterHardDiskImage },
+	{ "bUseIdeSlaveHardDiskImage", Bool_Tag, &ConfigureParams.HardDisk.bUseIdeSlaveHardDiskImage },
+	{ "szIdeMasterHardDiskImage", String_Tag, ConfigureParams.HardDisk.szIdeMasterHardDiskImage },
+	{ "szIdeSlaveHardDiskImage", String_Tag, ConfigureParams.HardDisk.szIdeSlaveHardDiskImage },
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save ACSI options */
+static const struct Config_Tag configs_Acsi[] =
+{
+	// { "bUseDevice0", Bool_Tag, &ConfigureParams.Acsi[0].bUseDevice },
+	// { "sDeviceFile0", String_Tag, ConfigureParams.Acsi[0].sDeviceFile },
+	{ "bUseDevice1", Bool_Tag, &ConfigureParams.Acsi[1].bUseDevice },
+	{ "sDeviceFile1", String_Tag, ConfigureParams.Acsi[1].sDeviceFile },
+	{ "bUseDevice2", Bool_Tag, &ConfigureParams.Acsi[2].bUseDevice },
+	{ "sDeviceFile2", String_Tag, ConfigureParams.Acsi[2].sDeviceFile },
+	{ "bUseDevice3", Bool_Tag, &ConfigureParams.Acsi[3].bUseDevice },
+	{ "sDeviceFile3", String_Tag, ConfigureParams.Acsi[3].sDeviceFile },
+	{ "bUseDevice4", Bool_Tag, &ConfigureParams.Acsi[4].bUseDevice },
+	{ "sDeviceFile4", String_Tag, ConfigureParams.Acsi[4].sDeviceFile },
+	{ "bUseDevice5", Bool_Tag, &ConfigureParams.Acsi[5].bUseDevice },
+	{ "sDeviceFile5", String_Tag, ConfigureParams.Acsi[5].sDeviceFile },
+	{ "bUseDevice6", Bool_Tag, &ConfigureParams.Acsi[6].bUseDevice },
+	{ "sDeviceFile6", String_Tag, ConfigureParams.Acsi[6].sDeviceFile },
+	{ "bUseDevice7", Bool_Tag, &ConfigureParams.Acsi[7].bUseDevice },
+	{ "sDeviceFile7", String_Tag, ConfigureParams.Acsi[7].sDeviceFile },
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save SCSI options */
+static const struct Config_Tag configs_Scsi[] =
+{
+	{ "bUseDevice1", Bool_Tag, &ConfigureParams.Scsi[1].bUseDevice },
+	{ "sDeviceFile1", String_Tag, ConfigureParams.Scsi[1].sDeviceFile },
+	{ "bUseDevice2", Bool_Tag, &ConfigureParams.Scsi[2].bUseDevice },
+	{ "sDeviceFile2", String_Tag, ConfigureParams.Scsi[2].sDeviceFile },
+	{ "bUseDevice3", Bool_Tag, &ConfigureParams.Scsi[3].bUseDevice },
+	{ "sDeviceFile3", String_Tag, ConfigureParams.Scsi[3].sDeviceFile },
+	{ "bUseDevice4", Bool_Tag, &ConfigureParams.Scsi[4].bUseDevice },
+	{ "sDeviceFile4", String_Tag, ConfigureParams.Scsi[4].sDeviceFile },
+	{ "bUseDevice5", Bool_Tag, &ConfigureParams.Scsi[5].bUseDevice },
+	{ "sDeviceFile5", String_Tag, ConfigureParams.Scsi[5].sDeviceFile },
+	{ "bUseDevice6", Bool_Tag, &ConfigureParams.Scsi[6].bUseDevice },
+	{ "sDeviceFile6", String_Tag, ConfigureParams.Scsi[6].sDeviceFile },
+	{ "bUseDevice7", Bool_Tag, &ConfigureParams.Scsi[7].bUseDevice },
+	{ "sDeviceFile7", String_Tag, ConfigureParams.Scsi[7].sDeviceFile },
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save ROM options */
+static const struct Config_Tag configs_Rom[] =
+{
+	{ "szTosImageFileName", String_Tag, ConfigureParams.Rom.szTosImageFileName },
+	{ "bPatchTos", Bool_Tag, &ConfigureParams.Rom.bPatchTos },
+	{ "szCartridgeImageFileName", String_Tag, ConfigureParams.Rom.szCartridgeImageFileName },
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save RS232 options */
+static const struct Config_Tag configs_Rs232[] =
+{
+	{ "bEnableRS232", Bool_Tag, &ConfigureParams.RS232.bEnableRS232 },
+	{ "szOutFileName", String_Tag, ConfigureParams.RS232.szOutFileName },
+	{ "szInFileName", String_Tag, ConfigureParams.RS232.szInFileName },
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save printer options */
+static const struct Config_Tag configs_Printer[] =
+{
+	{ "bEnablePrinting", Bool_Tag, &ConfigureParams.Printer.bEnablePrinting },
+	{ "szPrintToFileName", String_Tag, ConfigureParams.Printer.szPrintToFileName },
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save MIDI options */
+static const struct Config_Tag configs_Midi[] =
+{
+	{ "bEnableMidi", Bool_Tag, &ConfigureParams.Midi.bEnableMidi },
+	{ "sMidiInFileName", String_Tag, ConfigureParams.Midi.sMidiInFileName },
+	{ "sMidiOutFileName", String_Tag, ConfigureParams.Midi.sMidiOutFileName },
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save system options */
+static const struct Config_Tag configs_System[] =
+{
+	{ "nCpuLevel", Int_Tag, &ConfigureParams.System.nCpuLevel },
+	{ "nCpuFreq", Int_Tag, &ConfigureParams.System.nCpuFreq },
+	{ "bCompatibleCpu", Bool_Tag, &ConfigureParams.System.bCompatibleCpu },
+	{ "nMachineType", Int_Tag, &ConfigureParams.System.nMachineType },
+	{ "bBlitter", Bool_Tag, &ConfigureParams.System.bBlitter },
+	{ "nDSPType", Int_Tag, &ConfigureParams.System.nDSPType },
+	{ "bRealTimeClock", Bool_Tag, &ConfigureParams.System.bRealTimeClock },
+	{ "bPatchTimerD", Bool_Tag, &ConfigureParams.System.bPatchTimerD },
+	{ "bFastBoot", Bool_Tag, &ConfigureParams.System.bFastBoot },
+	{ "bFastForward", Bool_Tag, &ConfigureParams.System.bFastForward },
+	{ "bAddressSpace24", Bool_Tag, &ConfigureParams.System.bAddressSpace24 },
+
+#if ENABLE_WINUAE_CPU
+	{ "bCycleExactCpu", Bool_Tag, &ConfigureParams.System.bCycleExactCpu },
+	{ "n_FPUType", Int_Tag, &ConfigureParams.System.n_FPUType },
+	{ "bCompatibleFPU", Bool_Tag, &ConfigureParams.System.bCompatibleFPU },
+	{ "bMMU", Bool_Tag, &ConfigureParams.System.bMMU },
+#endif
+	{ NULL , Error_Tag, NULL }
+};
+
+/* Used to load/save video options */
+static const struct Config_Tag configs_Video[] =
+{
+	{ "AviRecordVcodec", Int_Tag, &ConfigureParams.Video.AviRecordVcodec },
+	{ "AviRecordFps", Int_Tag, &ConfigureParams.Video.AviRecordFps },
+	{ "AviRecordFile", String_Tag, ConfigureParams.Video.AviRecordFile },
+	{ NULL , Error_Tag, NULL }
+};
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Set default configuration values.
+ */
+void Configuration_SetDefault(void)
+{
+	int i, maxjoy;
+	const char *psHomeDir;
+	const char *psWorkingDir;
+
+	psHomeDir = Paths_GetHatariHome();
+	psWorkingDir = Paths_GetWorkingDir();
+
+	/* Clear parameters */
+	memset(&ConfigureParams, 0, sizeof(CNF_PARAMS));
+
+	/* Set defaults for logging and tracing */
+	strcpy(ConfigureParams.Log.sLogFileName, "stderr");
+	strcpy(ConfigureParams.Log.sTraceFileName, "stderr");
+	ConfigureParams.Log.nExceptionDebugMask = DEFAULT_EXCEPTIONS;
+	ConfigureParams.Log.nTextLogLevel = LOG_TODO;
+	ConfigureParams.Log.nAlertDlgLogLevel = LOG_ERROR;
+	ConfigureParams.Log.bConfirmQuit = true;
+	ConfigureParams.Log.bNatFeats = false;
+	ConfigureParams.Log.bConsoleWindow = false;
+
+	/* Set defaults for debugger */
+	ConfigureParams.Debugger.nNumberBase = 10;
+	ConfigureParams.Debugger.nDisasmLines = 8;
+	ConfigureParams.Debugger.nMemdumpLines = 8;
+	/* external one has nicer output, but isn't as complete as UAE one */
+	ConfigureParams.Debugger.bDisasmUAE = false;
+	ConfigureParams.Debugger.nDisasmOptions = Disasm_GetOptions();
+
+	/* Set defaults for floppy disk images */
+	ConfigureParams.DiskImage.bAutoInsertDiskB = true;
+	ConfigureParams.DiskImage.FastFloppy = false;
+	ConfigureParams.DiskImage.nWriteProtection = WRITEPROT_OFF;
+
+	ConfigureParams.DiskImage.EnableDriveA = true;
+	FDC_Drive_Set_Enable ( 0 , ConfigureParams.DiskImage.EnableDriveA );
+	ConfigureParams.DiskImage.DriveA_NumberOfHeads = 2;
+	FDC_Drive_Set_NumberOfHeads ( 0 , ConfigureParams.DiskImage.DriveA_NumberOfHeads );
+
+	ConfigureParams.DiskImage.EnableDriveB = true;
+	FDC_Drive_Set_Enable ( 1 , ConfigureParams.DiskImage.EnableDriveB );
+	ConfigureParams.DiskImage.DriveB_NumberOfHeads = 2;
+	FDC_Drive_Set_NumberOfHeads ( 1 , ConfigureParams.DiskImage.DriveB_NumberOfHeads );
+
+	for (i = 0; i < MAX_FLOPPYDRIVES; i++)
+	{
+		ConfigureParams.DiskImage.szDiskZipPath[i][0] = '\0';
+		ConfigureParams.DiskImage.szDiskFileName[i][0] = '\0';
+	}
+	strcpy(ConfigureParams.DiskImage.szDiskImageDirectory, psWorkingDir);
+	File_AddSlashToEndFileName(ConfigureParams.DiskImage.szDiskImageDirectory);
+
+	/* Set defaults for hard disks */
+	ConfigureParams.HardDisk.bBootFromHardDisk = false;
+	ConfigureParams.HardDisk.bFilenameConversion = false;
+	ConfigureParams.HardDisk.nGemdosCase = GEMDOS_NOP;
+	ConfigureParams.HardDisk.nWriteProtection = WRITEPROT_OFF;
+	ConfigureParams.HardDisk.nGemdosDrive = DRIVE_C;
+	ConfigureParams.HardDisk.bUseHardDiskDirectories = false;
+	for (i = 0; i < MAX_HARDDRIVES; i++)
+	{
+		strcpy(ConfigureParams.HardDisk.szHardDiskDirectories[i], psWorkingDir);
+		File_CleanFileName(ConfigureParams.HardDisk.szHardDiskDirectories[i]);
+	}
+	ConfigureParams.HardDisk.bUseIdeMasterHardDiskImage = false;
+	strcpy(ConfigureParams.HardDisk.szIdeMasterHardDiskImage, psWorkingDir);
+	ConfigureParams.HardDisk.bUseIdeSlaveHardDiskImage = false;
+	strcpy(ConfigureParams.HardDisk.szIdeSlaveHardDiskImage, psWorkingDir);
+
+	/* ACSI */
+	for (i = 0; i < MAX_ACSI_DEVS; i++)
+	{
+		ConfigureParams.Acsi[i].bUseDevice = false;
+		strcpy(ConfigureParams.Acsi[i].sDeviceFile, psWorkingDir);
+	}
+
+	/* SCSI */
+	for (i = 0; i < MAX_SCSI_DEVS; i++)
+	{
+		ConfigureParams.Scsi[i].bUseDevice = false;
+		strcpy(ConfigureParams.Scsi[i].sDeviceFile, psWorkingDir);
+	}
+
+	/* Set defaults for Joysticks */
+	maxjoy = Joy_GetMaxId();
+	for (i = 0; i < JOYSTICK_COUNT; i++)
+	{
+		ConfigureParams.Joysticks.Joy[i].nJoystickMode = JOYSTICK_DISABLED;
+		ConfigureParams.Joysticks.Joy[i].bEnableAutoFire = false;
+		ConfigureParams.Joysticks.Joy[i].bEnableJumpOnFire2 = false;
+		ConfigureParams.Joysticks.Joy[i].nJoyId = (i > maxjoy ? maxjoy : i);
+		ConfigureParams.Joysticks.Joy[i].nKeyCodeUp = SDLK_UP;
+		ConfigureParams.Joysticks.Joy[i].nKeyCodeDown = SDLK_DOWN;
+		ConfigureParams.Joysticks.Joy[i].nKeyCodeLeft = SDLK_LEFT;
+		ConfigureParams.Joysticks.Joy[i].nKeyCodeRight = SDLK_RIGHT;
+		ConfigureParams.Joysticks.Joy[i].nKeyCodeFire = SDLK_RCTRL;
+	}
+	if (SDL_NumJoysticks() > 0)
+	{
+		/* ST Joystick #1 is default joystick */
+		ConfigureParams.Joysticks.Joy[1].nJoyId = 0;
+		ConfigureParams.Joysticks.Joy[0].nJoyId = (maxjoy ? 1 : 0);
+		ConfigureParams.Joysticks.Joy[1].nJoystickMode = JOYSTICK_REALSTICK;
+	}
+
+	/* Set defaults for Keyboard */
+	ConfigureParams.Keyboard.bDisableKeyRepeat = false;
+	ConfigureParams.Keyboard.nKeymapType = KEYMAP_SYMBOLIC;
+	strcpy(ConfigureParams.Keyboard.szMappingFileName, "");
+  
+	/* Set defaults for Shortcuts */
+	ConfigureParams.Shortcut.withoutModifier[SHORTCUT_OPTIONS] = SDLK_F12;
+	ConfigureParams.Shortcut.withoutModifier[SHORTCUT_FULLSCREEN] = SDLK_F11;
+	ConfigureParams.Shortcut.withoutModifier[SHORTCUT_PAUSE] = SDLK_PAUSE;
+  
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_DEBUG] = SDLK_PAUSE;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_OPTIONS] = SDLK_o;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_FULLSCREEN] = SDLK_f;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_MOUSEGRAB] = SDLK_m;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_COLDRESET] = SDLK_c;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_WARMRESET] = SDLK_r;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_SCREENSHOT] = SDLK_g;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_BOSSKEY] = SDLK_i;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_CURSOREMU] = SDLK_j;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_FASTFORWARD] = SDLK_x;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_RECANIM] = SDLK_a;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_RECSOUND] = SDLK_y;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_SOUND] = SDLK_s;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_QUIT] = SDLK_q;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_LOADMEM] = SDLK_l;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_SAVEMEM] = SDLK_k;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_INSERTDISKA] = SDLK_d;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_JOY_0] = SDLK_F1;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_JOY_1] = SDLK_F2;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_PAD_A] = SDLK_F3;
+	ConfigureParams.Shortcut.withModifier[SHORTCUT_PAD_B] = SDLK_F4;
+
+	/* Set defaults for Memory */
+	ConfigureParams.Memory.nMemorySize = 1;     /* 1 MiB */
+	ConfigureParams.Memory.nTTRamSize = 0;     /* disabled */
+	ConfigureParams.Memory.bAutoSave = false;
+	sprintf(ConfigureParams.Memory.szMemoryCaptureFileName, "%s%chatari.sav",
+	        psHomeDir, PATHSEP);
+	sprintf(ConfigureParams.Memory.szAutoSaveFileName, "%s%cauto.sav",
+	        psHomeDir, PATHSEP);
+
+	/* Set defaults for Printer */
+	ConfigureParams.Printer.bEnablePrinting = false;
+	sprintf(ConfigureParams.Printer.szPrintToFileName, "%s%chatari.prn",
+	        psHomeDir, PATHSEP);
+
+	/* Set defaults for RS232 */
+	ConfigureParams.RS232.bEnableRS232 = false;
+	strcpy(ConfigureParams.RS232.szOutFileName, "/dev/modem");
+	strcpy(ConfigureParams.RS232.szInFileName, "/dev/modem");
+
+	/* Set defaults for MIDI */
+	ConfigureParams.Midi.bEnableMidi = false;
+	strcpy(ConfigureParams.Midi.sMidiInFileName, "/dev/snd/midiC1D0");
+	strcpy(ConfigureParams.Midi.sMidiOutFileName, "/dev/snd/midiC1D0");
+
+	/* Set defaults for Screen */
+	ConfigureParams.Screen.bFullScreen = false;
+	ConfigureParams.Screen.bKeepResolution = true;
+	ConfigureParams.Screen.bKeepResolutionST = false;
+	ConfigureParams.Screen.nFrameSkips = AUTO_FRAMESKIP_LIMIT;
+	ConfigureParams.Screen.bAllowOverscan = true;
+	ConfigureParams.Screen.nSpec512Threshold = 1;
+	ConfigureParams.Screen.nForceBpp = 0;
+	ConfigureParams.Screen.bAspectCorrect = true;
+	ConfigureParams.Screen.nMonitorType = MONITOR_TYPE_RGB;
+	ConfigureParams.Screen.bUseExtVdiResolutions = false;
+	ConfigureParams.Screen.nVdiWidth = 640;
+	ConfigureParams.Screen.nVdiHeight = 480;
+	ConfigureParams.Screen.nVdiColors = GEMCOLOR_16;
+	ConfigureParams.Screen.bMouseWarp = true;
+	ConfigureParams.Screen.bShowStatusbar = true;
+	ConfigureParams.Screen.bShowDriveLed = true;
+	ConfigureParams.Screen.bCrop = false;
+	/* gives zoomed Falcon/TT windows about same size as ST/STE windows */
+	ConfigureParams.Screen.nMaxWidth = 2*NUM_VISIBLE_LINE_PIXELS;
+	ConfigureParams.Screen.nMaxHeight = 2*NUM_VISIBLE_LINES+STATUSBAR_MAX_HEIGHT;
+	ConfigureParams.Screen.bForceMax = false;
+#ifdef GEKKO
+	/* With borders; when enabled it almost shows the whole screen */
+	ConfigureParams.Screen.nWiiOffset = 12;
+#endif
+#if WITH_SDL2
+	ConfigureParams.Screen.nRenderScaleQuality = 0;
+	ConfigureParams.Screen.bUseVsync = false;
+#endif
+
+	/* Set defaults for Sound */
+	ConfigureParams.Sound.bEnableMicrophone = true;
+	ConfigureParams.Sound.bEnableSound = true;
+	ConfigureParams.Sound.bEnableSoundSync = false;
+#ifdef GEKKO
+ConfigureParams.Sound.nPlaybackFreq = 32000;
+#else
+	ConfigureParams.Sound.nPlaybackFreq = 44100;
+#endif
+	sprintf(ConfigureParams.Sound.szYMCaptureFileName, "%s%chatari.wav",
+	        psWorkingDir, PATHSEP);
+	ConfigureParams.Sound.SdlAudioBufferSize = 0;
+	ConfigureParams.Sound.YmVolumeMixing = YM_TABLE_MIXING;
+
+	/* Set defaults for Rom */
+	sprintf(ConfigureParams.Rom.szTosImageFileName, "%s%ctos.img",
+	        Paths_GetDataDir(), PATHSEP);
+	ConfigureParams.Rom.bPatchTos = true;
+	strcpy(ConfigureParams.Rom.szCartridgeImageFileName, "");
+
+	/* Set defaults for System */
+#if ENABLE_WINUAE_CPU
+	/* Default to Falcon with WinUAE CPU core... */
+	ConfigureParams.System.nMachineType = MACHINE_FALCON;
+	ConfigureParams.System.nCpuLevel = 3;
+	ConfigureParams.System.nCpuFreq = 16;
+	ConfigureParams.System.nDSPType = DSP_TYPE_EMU;
+	ConfigureParams.System.bAddressSpace24 = true;
+	ConfigureParams.System.n_FPUType = FPU_NONE;
+	ConfigureParams.System.bCompatibleFPU = true;
+	ConfigureParams.System.bMMU = false;
+	ConfigureParams.System.bCycleExactCpu = true;
+#else
+	/* ...and to ST with old UAE CPU core */
+	ConfigureParams.System.nMachineType = MACHINE_ST;
+ 	ConfigureParams.System.nCpuLevel = 0;
+ 	ConfigureParams.System.nCpuFreq = 8;
+	ConfigureParams.System.nDSPType = DSP_TYPE_NONE;
+	ConfigureParams.System.bAddressSpace24 = true;
+#endif
+	ConfigureParams.System.bCompatibleCpu = true;
+	ConfigureParams.System.bBlitter = false;
+	ConfigureParams.System.bPatchTimerD = true;
+	ConfigureParams.System.bFastBoot = false;
+	ConfigureParams.System.bRealTimeClock = false;
+	ConfigureParams.System.bFastForward = false;
+
+	/* Set defaults for Video */
+#if HAVE_LIBPNG
+	ConfigureParams.Video.AviRecordVcodec = AVI_RECORD_VIDEO_CODEC_PNG;
+#else
+	ConfigureParams.Video.AviRecordVcodec = AVI_RECORD_VIDEO_CODEC_BMP;
+#endif
+	ConfigureParams.Video.AviRecordFps = 0;			/* automatic FPS */
+	sprintf(ConfigureParams.Video.AviRecordFile, "%s%chatari.avi", psWorkingDir, PATHSEP);
+
+	/* Initialize the configuration file name */
+	if (strlen(psHomeDir) < sizeof(sConfigFileName)-13)
+		sprintf(sConfigFileName, "%s%chatari.cfg", psHomeDir, PATHSEP);
+	else
+		strcpy(sConfigFileName, "hatari.cfg");
+
+#if defined(__AMIGAOS4__)
+	/* Fix default path names on Amiga OS */
+	sprintf(ConfigureParams.Rom.szTosImageFileName, "%stos.img", Paths_GetDataDir());
+#endif
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Copy details from configuration structure into global variables for system,
+ * clean file names, etc...  Called from main.c and dialog.c files.
+ */
+void Configuration_Apply(bool bReset)
+{
+	int i;
+
+	if (bReset)
+	{
+		/* Set resolution change */
+		bUseVDIRes = ConfigureParams.Screen.bUseExtVdiResolutions;
+		bUseHighRes = ((!bUseVDIRes) && ConfigureParams.Screen.nMonitorType == MONITOR_TYPE_MONO)
+			|| (bUseVDIRes && ConfigureParams.Screen.nVdiColors == GEMCOLOR_2);
+		if (bUseHighRes)
+		{
+			STRes = ST_HIGH_RES;
+		}
+		if (bUseVDIRes)
+		{
+			VDI_SetResolution(ConfigureParams.Screen.nVdiColors,
+			                  ConfigureParams.Screen.nVdiWidth,
+			                  ConfigureParams.Screen.nVdiHeight);
+			bVdiAesIntercept = true;
+		}
+	}
+	if (ConfigureParams.Screen.nFrameSkips < AUTO_FRAMESKIP_LIMIT)
+	{
+		nFrameSkips = ConfigureParams.Screen.nFrameSkips;
+	}
+
+	/* Init clocks for this machine */
+	ClocksTimings_InitMachine ( ConfigureParams.System.nMachineType );
+
+	/* Sound settings */
+	/* SDL sound buffer in ms */
+	SdlAudioBufferSize = ConfigureParams.Sound.SdlAudioBufferSize;
+	if ( SdlAudioBufferSize == 0 )			/* use default setting for SDL */
+		;
+	else if ( SdlAudioBufferSize < 10 )		/* min of 10 ms */
+		SdlAudioBufferSize = 10;
+	else if ( SdlAudioBufferSize > 100 )		/* max of 100 ms */
+		SdlAudioBufferSize = 100;
+
+	/* Set playback frequency */
+	Audio_SetOutputAudioFreq(ConfigureParams.Sound.nPlaybackFreq);
+
+	/* YM Mixing */
+	if ( ( ConfigureParams.Sound.YmVolumeMixing != YM_LINEAR_MIXING )
+	  && ( ConfigureParams.Sound.YmVolumeMixing != YM_TABLE_MIXING  )
+	  && ( ConfigureParams.Sound.YmVolumeMixing != YM_MODEL_MIXING ) )
+		ConfigureParams.Sound.YmVolumeMixing = YM_TABLE_MIXING;
+
+	YmVolumeMixing = ConfigureParams.Sound.YmVolumeMixing;
+	Sound_SetYmVolumeMixing();
+
+	/* Check/constrain CPU settings and change corresponding
+	 * UAE cpu_level & cpu_compatible variables
+	 */
+	M68000_CheckCpuSettings();
+
+	/* Clean file and directory names */
+	File_MakeAbsoluteName(ConfigureParams.Rom.szTosImageFileName);
+	if (strlen(ConfigureParams.Rom.szCartridgeImageFileName) > 0)
+		File_MakeAbsoluteName(ConfigureParams.Rom.szCartridgeImageFileName);
+	File_CleanFileName(ConfigureParams.HardDisk.szHardDiskDirectories[0]);
+	File_MakeAbsoluteName(ConfigureParams.HardDisk.szHardDiskDirectories[0]);
+	File_MakeAbsoluteName(ConfigureParams.Memory.szMemoryCaptureFileName);
+	File_MakeAbsoluteName(ConfigureParams.Sound.szYMCaptureFileName);
+	if (strlen(ConfigureParams.Keyboard.szMappingFileName) > 0)
+		File_MakeAbsoluteName(ConfigureParams.Keyboard.szMappingFileName);
+	File_MakeAbsoluteName(ConfigureParams.Video.AviRecordFile);
+	for (i = 0; i < MAX_ACSI_DEVS; i++)
+	{
+		File_MakeAbsoluteName(ConfigureParams.Acsi[i].sDeviceFile);
+	}
+	for (i = 0; i < MAX_SCSI_DEVS; i++)
+	{
+		File_MakeAbsoluteName(ConfigureParams.Scsi[i].sDeviceFile);
+	}
+
+	/* make path names absolute, but handle special file names */
+	File_MakeAbsoluteSpecialName(ConfigureParams.Log.sLogFileName);
+	File_MakeAbsoluteSpecialName(ConfigureParams.Log.sTraceFileName);
+	File_MakeAbsoluteSpecialName(ConfigureParams.RS232.szInFileName);
+	File_MakeAbsoluteSpecialName(ConfigureParams.RS232.szOutFileName);
+	File_MakeAbsoluteSpecialName(ConfigureParams.Midi.sMidiInFileName);
+	File_MakeAbsoluteSpecialName(ConfigureParams.Midi.sMidiOutFileName);
+	File_MakeAbsoluteSpecialName(ConfigureParams.Printer.szPrintToFileName);
+
+	/* Enable/disable floppy drives */
+	FDC_Drive_Set_Enable ( 0 , ConfigureParams.DiskImage.EnableDriveA );
+	FDC_Drive_Set_Enable ( 1 , ConfigureParams.DiskImage.EnableDriveB );
+	FDC_Drive_Set_NumberOfHeads ( 0 , ConfigureParams.DiskImage.DriveA_NumberOfHeads );
+	FDC_Drive_Set_NumberOfHeads ( 1 , ConfigureParams.DiskImage.DriveB_NumberOfHeads );
+
+        /* Update disassembler */
+#if ENABLE_WINUAE_CPU
+        Disasm_SetCPUType ( ConfigureParams.System.nCpuLevel , ConfigureParams.System.n_FPUType );
+#else
+        Disasm_SetCPUType ( ConfigureParams.System.nCpuLevel , 0 );
+#endif
+
+#if ENABLE_DSP_EMU
+	/* Enable DSP ? */
+	if ( ConfigureParams.System.nDSPType == DSP_TYPE_EMU )
+		DSP_Enable ();
+	else
+		DSP_Disable ();
+#endif
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Load a settings section from the configuration file.
+ */
+static int Configuration_LoadSection(const char *pFilename, const struct Config_Tag configs[], const char *pSection)
+{
+	int ret;
+
+	ret = input_config(pFilename, configs, pSection);
+
+	if (ret < 0)
+		fprintf(stderr, "Can not load configuration file %s (section %s).\n",
+		        pFilename, pSection);
+
+	return ret;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Load program setting from configuration file. If psFileName is NULL, use
+ * the configuration file given in configuration / last selected by user.
+ */
+void Configuration_Load(const char *psFileName)
+{
+	if (psFileName == NULL)
+		psFileName = sConfigFileName;
+
+	if (!File_Exists(psFileName))
+	{
+		Log_Printf(LOG_DEBUG, "Configuration file %s not found.\n", psFileName);
+		return;
+	}
+
+	Configuration_LoadSection(psFileName, configs_Log, "[Log]");
+	Configuration_LoadSection(psFileName, configs_Debugger, "[Debugger]");
+	Configuration_LoadSection(psFileName, configs_Screen, "[Screen]");
+	Configuration_LoadSection(psFileName, configs_Joystick0, "[Joystick0]");
+	Configuration_LoadSection(psFileName, configs_Joystick1, "[Joystick1]");
+	Configuration_LoadSection(psFileName, configs_Joystick2, "[Joystick2]");
+	Configuration_LoadSection(psFileName, configs_Joystick3, "[Joystick3]");
+	Configuration_LoadSection(psFileName, configs_Joystick4, "[Joystick4]");
+	Configuration_LoadSection(psFileName, configs_Joystick5, "[Joystick5]");
+	Configuration_LoadSection(psFileName, configs_Keyboard, "[Keyboard]");
+#if WITH_SDL2
+	Configuration_LoadSection(psFileName, configs_ShortCutWithMod, "[ShortcutsWithModifiers2]");
+	Configuration_LoadSection(psFileName, configs_ShortCutWithoutMod, "[ShortcutsWithoutModifiers2]");
+#else
+	Configuration_LoadSection(psFileName, configs_ShortCutWithMod, "[ShortcutsWithModifiers]");
+	Configuration_LoadSection(psFileName, configs_ShortCutWithoutMod, "[ShortcutsWithoutModifiers]");
+#endif
+	Configuration_LoadSection(psFileName, configs_Sound, "[Sound]");
+	Configuration_LoadSection(psFileName, configs_Memory, "[Memory]");
+	Configuration_LoadSection(psFileName, configs_Floppy, "[Floppy]");
+	Configuration_LoadSection(psFileName, configs_HardDisk, "[HardDisk]");
+	Configuration_LoadSection(psFileName, configs_Acsi, "[ACSI]");
+	Configuration_LoadSection(psFileName, configs_Scsi, "[SCSI]");
+	Configuration_LoadSection(psFileName, configs_Rom, "[ROM]");
+	Configuration_LoadSection(psFileName, configs_Rs232, "[RS232]");
+	Configuration_LoadSection(psFileName, configs_Printer, "[Printer]");
+	Configuration_LoadSection(psFileName, configs_Midi, "[Midi]");
+	Configuration_LoadSection(psFileName, configs_System, "[System]");
+	Configuration_LoadSection(psFileName, configs_Video, "[Video]");
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Save a settings section to configuration file
+ */
+static int Configuration_SaveSection(const char *pFilename, const struct Config_Tag configs[], const char *pSection)
+{
+	int ret;
+
+	ret = update_config(pFilename, configs, pSection);
+
+	if (ret < 0)
+		fprintf(stderr, "Error while updating section %s in %s\n", pSection, pFilename);
+
+	return ret;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Save program setting to configuration file
+ */
+void Configuration_Save(void)
+{
+	if (Configuration_SaveSection(sConfigFileName, configs_Log, "[Log]") < 0)
+	{
+		Log_AlertDlg(LOG_ERROR, "Error saving config file.");
+		return;
+	}
+	Configuration_SaveSection(sConfigFileName, configs_Debugger, "[Debugger]");
+	Configuration_SaveSection(sConfigFileName, configs_Screen, "[Screen]");
+	Configuration_SaveSection(sConfigFileName, configs_Joystick0, "[Joystick0]");
+	Configuration_SaveSection(sConfigFileName, configs_Joystick1, "[Joystick1]");
+	Configuration_SaveSection(sConfigFileName, configs_Joystick2, "[Joystick2]");
+	Configuration_SaveSection(sConfigFileName, configs_Joystick3, "[Joystick3]");
+	Configuration_SaveSection(sConfigFileName, configs_Joystick4, "[Joystick4]");
+	Configuration_SaveSection(sConfigFileName, configs_Joystick5, "[Joystick5]");
+	Configuration_SaveSection(sConfigFileName, configs_Keyboard, "[Keyboard]");
+#if WITH_SDL2
+	Configuration_SaveSection(sConfigFileName, configs_ShortCutWithMod, "[ShortcutsWithModifiers2]");
+	Configuration_SaveSection(sConfigFileName, configs_ShortCutWithoutMod, "[ShortcutsWithoutModifiers2]");
+#else
+	Configuration_SaveSection(sConfigFileName, configs_ShortCutWithMod, "[ShortcutsWithModifiers]");
+	Configuration_SaveSection(sConfigFileName, configs_ShortCutWithoutMod, "[ShortcutsWithoutModifiers]");
+#endif
+	Configuration_SaveSection(sConfigFileName, configs_Sound, "[Sound]");
+	Configuration_SaveSection(sConfigFileName, configs_Memory, "[Memory]");
+	Configuration_SaveSection(sConfigFileName, configs_Floppy, "[Floppy]");
+	Configuration_SaveSection(sConfigFileName, configs_HardDisk, "[HardDisk]");
+	/*Configuration_SaveSection(sConfigFileName, configs_Acsi, "[ACSI]");*/
+	/*Configuration_SaveSection(sConfigFileName, configs_Scsi, "[SCSI]");*/
+	Configuration_SaveSection(sConfigFileName, configs_Rom, "[ROM]");
+	Configuration_SaveSection(sConfigFileName, configs_Rs232, "[RS232]");
+	Configuration_SaveSection(sConfigFileName, configs_Printer, "[Printer]");
+	Configuration_SaveSection(sConfigFileName, configs_Midi, "[Midi]");
+	Configuration_SaveSection(sConfigFileName, configs_System, "[System]");
+	Configuration_SaveSection(sConfigFileName, configs_Video, "[Video]");
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Save/restore snapshot of configuration variables
+ * ('MemorySnapShot_Store' handles type)
+ */
+void Configuration_MemorySnapShot_Capture(bool bSave)
+{
+	int i;
+
+	MemorySnapShot_Store(ConfigureParams.Rom.szTosImageFileName, sizeof(ConfigureParams.Rom.szTosImageFileName));
+	MemorySnapShot_Store(ConfigureParams.Rom.szCartridgeImageFileName, sizeof(ConfigureParams.Rom.szCartridgeImageFileName));
+
+	MemorySnapShot_Store(&ConfigureParams.Memory.nMemorySize, sizeof(ConfigureParams.Memory.nMemorySize));
+	MemorySnapShot_Store(&ConfigureParams.Memory.nTTRamSize, sizeof(ConfigureParams.Memory.nTTRamSize));
+
+	MemorySnapShot_Store(&ConfigureParams.DiskImage.szDiskFileName[0], sizeof(ConfigureParams.DiskImage.szDiskFileName[0]));
+	MemorySnapShot_Store(&ConfigureParams.DiskImage.szDiskZipPath[0], sizeof(ConfigureParams.DiskImage.szDiskZipPath[0]));
+	MemorySnapShot_Store(&ConfigureParams.DiskImage.EnableDriveA, sizeof(ConfigureParams.DiskImage.EnableDriveA));
+	MemorySnapShot_Store(&ConfigureParams.DiskImage.DriveA_NumberOfHeads, sizeof(ConfigureParams.DiskImage.DriveA_NumberOfHeads));
+	MemorySnapShot_Store(&ConfigureParams.DiskImage.szDiskFileName[1], sizeof(ConfigureParams.DiskImage.szDiskFileName[1]));
+	MemorySnapShot_Store(&ConfigureParams.DiskImage.szDiskZipPath[1], sizeof(ConfigureParams.DiskImage.szDiskZipPath[1]));
+	MemorySnapShot_Store(&ConfigureParams.DiskImage.EnableDriveB, sizeof(ConfigureParams.DiskImage.EnableDriveB));
+	MemorySnapShot_Store(&ConfigureParams.DiskImage.DriveB_NumberOfHeads, sizeof(ConfigureParams.DiskImage.DriveB_NumberOfHeads));
+
+	MemorySnapShot_Store(&ConfigureParams.HardDisk.bUseHardDiskDirectories, sizeof(ConfigureParams.HardDisk.bUseHardDiskDirectories));
+	MemorySnapShot_Store(ConfigureParams.HardDisk.szHardDiskDirectories[DRIVE_C], sizeof(ConfigureParams.HardDisk.szHardDiskDirectories[DRIVE_C]));
+	for (i = 0; i < MAX_ACSI_DEVS; i++)
+	{
+		MemorySnapShot_Store(&ConfigureParams.Acsi[i].bUseDevice, sizeof(ConfigureParams.Acsi[i].bUseDevice));
+		MemorySnapShot_Store(ConfigureParams.Acsi[i].sDeviceFile, sizeof(ConfigureParams.Acsi[i].sDeviceFile));
+	}
+	/* for (i = 0; i < MAX_SCSI_DEVS; i++)
+	{
+		MemorySnapShot_Store(&ConfigureParams.Scsi[i].bUseDevice, sizeof(ConfigureParams.Scsi[i].bUseDevice));
+		MemorySnapShot_Store(ConfigureParams.Scsi[i].sDeviceFile, sizeof(ConfigureParams.Scsi[i].sDeviceFile));
+	}*/
+
+	MemorySnapShot_Store(&ConfigureParams.Screen.nMonitorType, sizeof(ConfigureParams.Screen.nMonitorType));
+	MemorySnapShot_Store(&ConfigureParams.Screen.bUseExtVdiResolutions, sizeof(ConfigureParams.Screen.bUseExtVdiResolutions));
+	MemorySnapShot_Store(&ConfigureParams.Screen.nVdiWidth, sizeof(ConfigureParams.Screen.nVdiWidth));
+	MemorySnapShot_Store(&ConfigureParams.Screen.nVdiHeight, sizeof(ConfigureParams.Screen.nVdiHeight));
+	MemorySnapShot_Store(&ConfigureParams.Screen.nVdiColors, sizeof(ConfigureParams.Screen.nVdiColors));
+
+	MemorySnapShot_Store(&ConfigureParams.System.nCpuLevel, sizeof(ConfigureParams.System.nCpuLevel));
+	MemorySnapShot_Store(&ConfigureParams.System.nCpuFreq, sizeof(ConfigureParams.System.nCpuFreq));
+	MemorySnapShot_Store(&ConfigureParams.System.bCompatibleCpu, sizeof(ConfigureParams.System.bCompatibleCpu));
+	MemorySnapShot_Store(&ConfigureParams.System.nMachineType, sizeof(ConfigureParams.System.nMachineType));
+	MemorySnapShot_Store(&ConfigureParams.System.bBlitter, sizeof(ConfigureParams.System.bBlitter));
+	MemorySnapShot_Store(&ConfigureParams.System.nDSPType, sizeof(ConfigureParams.System.nDSPType));
+	MemorySnapShot_Store(&ConfigureParams.System.bRealTimeClock, sizeof(ConfigureParams.System.bRealTimeClock));
+	MemorySnapShot_Store(&ConfigureParams.System.bPatchTimerD, sizeof(ConfigureParams.System.bPatchTimerD));
+	MemorySnapShot_Store(&ConfigureParams.System.bAddressSpace24, sizeof(ConfigureParams.System.bAddressSpace24));
+
+#if ENABLE_WINUAE_CPU
+	MemorySnapShot_Store(&ConfigureParams.System.bCycleExactCpu, sizeof(ConfigureParams.System.bCycleExactCpu));
+	MemorySnapShot_Store(&ConfigureParams.System.n_FPUType, sizeof(ConfigureParams.System.n_FPUType));
+	MemorySnapShot_Store(&ConfigureParams.System.bCompatibleFPU, sizeof(ConfigureParams.System.bCompatibleFPU));
+	MemorySnapShot_Store(&ConfigureParams.System.bMMU, sizeof(ConfigureParams.System.bMMU));
+#endif
+
+	MemorySnapShot_Store(&ConfigureParams.DiskImage.FastFloppy, sizeof(ConfigureParams.DiskImage.FastFloppy));
+
+	if (!bSave)
+		Configuration_Apply(true);
+}
diff --git a/src/control.c b/src/control.c
new file mode 100644
index 0000000..7461966
--- /dev/null
+++ b/src/control.c
@@ -0,0 +1,615 @@
+/*
+  Hatari - control.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  This code processes commands from the Hatari control socket
+*/
+const char Control_fileid[] = "Hatari control.c : " __DATE__ " " __TIME__;
+
+#include "config.h"
+
+#if HAVE_UNIX_DOMAIN_SOCKETS
+# include 
+# include 
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "main.h"
+#include "change.h"
+#include "configuration.h"
+#include "control.h"
+#include "debugui.h"
+#include "file.h"
+#include "ikbd.h"
+#include "keymap.h"
+#include "log.h"
+#include "midi.h"
+#include "printer.h"
+#include "rs232.h"
+#include "shortcut.h"
+#include "str.h"
+#include "screen.h"
+
+typedef enum {
+	DO_DISABLE,
+	DO_ENABLE,
+	DO_TOGGLE
+} action_t;
+
+/* Whether to send embedded window info */
+static bool bSendEmbedInfo;
+/* Pausing triggered remotely (battery save pause) */
+static bool bRemotePaused;
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Parse key command and synthetize key press/release
+ * corresponding to given keycode or character.
+ * Return false if parsing failed, true otherwise
+ * 
+ * This can be used by external Hatari UI(s) for
+ * string macros, or on devices which lack keyboard
+ */
+static bool Control_InsertKey(const char *event)
+{
+	const char *key = NULL;
+	bool up, down;
+
+	if (strncmp(event, "keypress ", 9) == 0) {
+		key = &event[9];
+		down = up = true;
+	} else if (strncmp(event, "keydown ", 8) == 0) {
+		key = &event[8];
+		down = true;
+		up = false;
+	} else if (strncmp(event, "keyup ", 6) == 0) {
+		key = &event[6];
+		down = false;
+		up = true;
+	}
+	if (!(key && key[0])) {
+		fprintf(stderr, "ERROR: '%s' contains no key press/down/up event\n", event);
+		return false;
+	}
+	if (key[1]) {
+		char *endptr;
+		/* multiple characters, assume it's a keycode */
+		int keycode = strtol(key, &endptr, 0);
+		/* not a valid number or keycode is out of range? */
+		if (*endptr || keycode < 0 || keycode > 255) {
+			fprintf(stderr, "ERROR: '%s' isn't a valid key scancode, got value %d\n",
+				key, keycode);
+			return false;
+		}
+		if (down) {
+			IKBD_PressSTKey(keycode, true);
+		}
+		if (up) {
+			IKBD_PressSTKey(keycode, false);
+		}
+	} else {
+		if (!isalnum((unsigned char)key[0])) {
+			fprintf(stderr, "ERROR: non-alphanumeric character '%c' needs to be given as keycode\n", key[0]);
+			return false;
+		}
+		if (down) {
+			Keymap_SimulateCharacter(key[0], true);
+		}
+		if (up) {
+			Keymap_SimulateCharacter(key[0], false);
+		}
+	}
+#if 0
+	fprintf(stderr, "Simulated key %s of %d\n",
+		(down? (up? "press":"down") :"up"), key);
+#endif
+	return true;
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Parse event name and synthetize corresponding event to emulation
+ * Return false if name parsing failed, true otherwise
+ * 
+ * This can be used by external Hatari UI(s) on devices which input
+ * methods differ from normal keyboard and mouse, such as high DPI
+ * touchscreen (no right/middle button, inaccurate clicks)
+ */
+static bool Control_InsertEvent(const char *event)
+{
+	if (strcmp(event, "doubleclick") == 0) {
+		Keyboard.LButtonDblClk = 1;
+		return true;
+	}
+	if (strcmp(event, "rightdown") == 0) {
+		Keyboard.bRButtonDown |= BUTTON_MOUSE;
+		return true;
+	}
+	if (strcmp(event, "rightup") == 0) {
+		Keyboard.bRButtonDown &= ~BUTTON_MOUSE;
+		return true;
+	}
+	if (Control_InsertKey(event)) {
+		return true;
+	}
+	fprintf(stderr, "ERROR: unrecognized event: '%s'\n", event);
+	fprintf(stderr,
+		"Supported mouse button and key events are:\n"
+		"- doubleclick\n"
+		"- rightdown\n"
+		"- rightup\n"
+		"- keypress \n"
+		"- keydown \n"
+		"- keyup \n"
+		" can be either a single ASCII character or an ST scancode\n"
+		"(e.g. space has scancode of 57 and enter 28).\n"
+		);
+	return false;	
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Parse device name and enable/disable/toggle & init/uninit it according
+ * to action.  Return false if name parsing failed, true otherwise
+ */
+static bool Control_DeviceAction(const char *name, action_t action)
+{
+	/* Note: e.g. RTC would require restarting emulation
+	 * and HD-boot setting emulation reboot.  Devices
+	 * listed here work just with init/uninit.
+	 */
+	struct {
+		const char *name;
+		bool *pvalue;
+		void(*init)(void);
+		void(*uninit)(void);
+	} item[] = {
+		{ "printer", &ConfigureParams.Printer.bEnablePrinting, Printer_Init, Printer_UnInit },
+		{ "rs232",   &ConfigureParams.RS232.bEnableRS232, RS232_Init, RS232_UnInit },
+		{ "midi",    &ConfigureParams.Midi.bEnableMidi, Midi_Init, Midi_UnInit },
+		{ NULL, NULL, NULL, NULL }
+	};
+	int i;
+	bool value;
+	for (i = 0; item[i].name; i++)
+	{
+		if (strcmp(name, item[i].name) == 0)
+		{
+			switch (action) {
+			case DO_TOGGLE:
+				value = !*(item[i].pvalue);
+				break;
+			case DO_ENABLE:
+				value = true;
+				break;
+			case DO_DISABLE:
+			default:
+				value = false;
+				break;
+			}
+			*(item[i].pvalue) = value;
+			if (value) {
+				item[i].init();
+			} else {
+				item[i].uninit();
+			}
+			fprintf(stderr, "%s: %s\n", name, value?"ON":"OFF");
+			return true;
+		}
+	}
+	fprintf(stderr, "WARNING: unknown device '%s'\n\n", name);
+	fprintf(stderr, "Accepted devices are:\n");
+	for (i = 0; item[i].name; i++)
+	{
+		fprintf(stderr, "- %s\n", item[i].name);
+	}
+	return false;
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Parse path type name and set the path to given value.
+ * Return false if name parsing failed, true otherwise
+ */
+static bool Control_SetPath(char *name)
+{
+	struct {
+		const char *name;
+		char *path;
+	} item[] = {
+		{ "memauto",  ConfigureParams.Memory.szAutoSaveFileName },
+		{ "memsave",  ConfigureParams.Memory.szMemoryCaptureFileName },
+		{ "midiin",   ConfigureParams.Midi.sMidiInFileName },
+		{ "midiout",  ConfigureParams.Midi.sMidiOutFileName },
+		{ "printout", ConfigureParams.Printer.szPrintToFileName },
+		{ "soundout", ConfigureParams.Sound.szYMCaptureFileName },
+		{ "rs232in",  ConfigureParams.RS232.szInFileName },
+		{ "rs232out", ConfigureParams.RS232.szOutFileName },
+		{ NULL, NULL }
+	};
+	int i;
+	char *arg;
+	const char *value;
+	
+	/* argument? */
+	arg = strchr(name, ' ');
+	if (arg) {
+		*arg = '\0';
+		value = Str_Trim(arg+1);
+	} else {
+		return false;
+	}
+	
+	for (i = 0; item[i].name; i++)
+	{
+		if (strcmp(name, item[i].name) == 0)
+		{
+			fprintf(stderr, "%s: %s -> %s\n", name, item[i].path, value);
+			strncpy(item[i].path, value, FILENAME_MAX-1);
+			return true;
+		}
+	}
+	fprintf(stderr, "WARNING: unknown path type '%s'\n\n", name);
+	fprintf(stderr, "Accepted paths types are:\n");
+	for (i = 0; item[i].name; i++)
+	{
+		fprintf(stderr, "- %s\n", item[i].name);
+	}
+	return false;
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Show Hatari remote usage info and return false
+ */
+static bool Control_Usage(const char *cmd)
+{
+	fprintf(stderr, "ERROR: unrecognized hatari command: '%s'!\n", cmd);
+	fprintf(stderr,
+		"Supported commands are:\n"
+		"- hatari-debug \n"
+		"- hatari-event \n"
+		"- hatari-option \n"
+		"- hatari-enable/disable/toggle \n"
+		"- hatari-path  \n"
+		"- hatari-shortcut \n"
+		"- hatari-embed-info\n"
+		"- hatari-stop\n"
+		"- hatari-cont\n"
+		"The last two can be used to stop and continue the Hatari emulation.\n"
+		"All commands need to be separated by newlines.  Spaces in command\n"
+		"line option arguments need to be quoted with \\.\n"
+		);
+	return false;
+}
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Parse Hatari debug/event/option/toggle/path/shortcut command buffer.
+ */
+void Control_ProcessBuffer(const char *orig)
+{
+	char *cmd, *cmdend, *arg, *buffer;
+	int ok = true;
+
+	/* this is called from several different places,
+	 * so take a copy of the original buffer so
+	 * that it can be sliced & diced
+	 */
+	buffer = strdup(orig);
+	assert(buffer);
+
+	cmd = buffer;
+	do {
+		/* command terminator? */
+		cmdend  = strchr(cmd, '\n');
+		if (cmdend) {
+			*cmdend = '\0';
+		}
+		/* arguments? */
+		arg = strchr(cmd, ' ');
+		if (arg) {
+			*arg = '\0';
+			arg = Str_Trim(arg+1);
+		}
+		if (arg) {
+			if (strcmp(cmd, "hatari-option") == 0) {
+				ok = Change_ApplyCommandline(arg);
+			} else if (strcmp(cmd, "hatari-debug") == 0) {
+				ok = DebugUI_ParseLine(arg);
+			} else if (strcmp(cmd, "hatari-shortcut") == 0) {
+				ok = Shortcut_Invoke(arg);
+			} else if (strcmp(cmd, "hatari-event") == 0) {
+				ok = Control_InsertEvent(arg);
+			} else if (strcmp(cmd, "hatari-path") == 0) {
+				ok = Control_SetPath(arg);
+			} else if (strcmp(cmd, "hatari-enable") == 0) {
+				ok = Control_DeviceAction(arg, DO_ENABLE);
+			} else if (strcmp(cmd, "hatari-disable") == 0) {
+				ok = Control_DeviceAction(arg, DO_DISABLE);
+			} else if (strcmp(cmd, "hatari-toggle") == 0) {
+				ok = Control_DeviceAction(arg, DO_TOGGLE);
+			} else {
+				ok = Control_Usage(cmd);
+			}
+		} else {
+			if (strcmp(cmd, "hatari-embed-info") == 0) {
+				fprintf(stderr, "Embedded window ID change messages = ON\n");
+				bSendEmbedInfo = true;
+			} else if (strcmp(cmd, "hatari-stop") == 0) {
+				Main_PauseEmulation(true);
+				bRemotePaused = true;
+			} else if (strcmp(cmd, "hatari-cont") == 0) {
+				Main_UnPauseEmulation();
+				bRemotePaused = false;
+			} else {
+				ok = Control_Usage(cmd);
+			}
+		}
+		if (cmdend) {
+			cmd = cmdend + 1;
+		}
+	} while (ok && cmdend && *cmd);
+	free(buffer);
+}
+
+
+#if HAVE_UNIX_DOMAIN_SOCKETS
+
+/* socket from which control command line options are read */
+static int ControlSocket;
+
+/* pre-declared local functions */
+static int Control_GetUISocket(void);
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Check ControlSocket for new commands and execute them.
+ * Commands should be separated by newlines.
+ * 
+ * Return true if remote pause ON (and connected), false otherwise
+ */
+bool Control_CheckUpdates(void)
+{
+	/* just using all trace options with +/- are about 300 chars */
+	char buffer[400];
+	struct timeval tv;
+	fd_set readfds;
+	ssize_t bytes;
+	int status, sock;
+
+	/* socket of file? */
+	if (ControlSocket) {
+		sock = ControlSocket;
+	} else {
+		return false;
+	}
+	
+	/* ready for reading? */
+	tv.tv_usec = tv.tv_sec = 0;
+	do {
+		FD_ZERO(&readfds);
+		FD_SET(sock, &readfds);
+		if (bRemotePaused) {
+			/* return only when there're UI events
+			 * (redraws etc) to save battery:
+			 *   http://bugzilla.libsdl.org/show_bug.cgi?id=323
+			 */
+			int uisock = Control_GetUISocket();
+			if (uisock) {
+				FD_SET(uisock, &readfds);
+				if (uisock < sock) {
+					uisock = sock;
+				}
+			}
+			status = select(uisock+1, &readfds, NULL, NULL, NULL);
+		} else {
+			status = select(sock+1, &readfds, NULL, NULL, &tv);
+		}
+		if (status < 0) {
+			perror("Control socket select() error");
+			return false;
+		}
+		/* nothing to process here */
+		if (status == 0) {
+			return bRemotePaused;
+		}
+		if (!FD_ISSET(sock, &readfds)) {
+			return bRemotePaused;
+		}
+		
+		/* assume whole command can be read in one go */
+		bytes = read(sock, buffer, sizeof(buffer)-1);
+		if (bytes < 0)
+		{
+			perror("Control socket read");
+			return false;
+		}
+		if (bytes == 0) {
+			/* closed */
+			close(ControlSocket);
+			ControlSocket = 0;
+			return false;
+		}
+		buffer[bytes] = '\0';
+		Control_ProcessBuffer(buffer);
+
+	} while (bRemotePaused);
+	
+	return false;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Open given control socket.
+ * Return NULL for success, otherwise an error string
+ */
+const char *Control_SetSocket(const char *socketpath)
+{
+	struct sockaddr_un address;
+	int newsock;
+	
+	newsock = socket(AF_UNIX, SOCK_STREAM, 0);
+	if (newsock < 0)
+	{
+		perror("socket creation");
+		return "Can't create AF_UNIX socket";
+	}
+
+	address.sun_family = AF_UNIX;
+	strncpy(address.sun_path, socketpath, sizeof(address.sun_path));
+	address.sun_path[sizeof(address.sun_path)-1] = '\0';
+	Log_Printf(LOG_INFO, "Connecting to control socket '%s'...\n", address.sun_path);
+	if (connect(newsock, (struct sockaddr *)&address, sizeof(address)) < 0)
+	{
+		perror("socket connect");
+		close(newsock);
+		return "connection to control socket failed";
+	}
+				
+	if (ControlSocket) {
+		close(ControlSocket);
+	}
+	ControlSocket = newsock;
+	Log_Printf(LOG_INFO, "new control socket is '%s'\n", socketpath);
+	return NULL;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Currently works only on X11.
+ * 
+ * SDL_syswm.h automatically includes everything else needed.
+ */
+
+#if HAVE_SDL_CONFIG_H
+#include 
+#endif
+
+/* X11 available and SDL_config.h states that SDL supports X11 */
+#if HAVE_X11 && SDL_VIDEO_DRIVER_X11
+#include 
+
+#if WITH_SDL2
+#define SDL_GetWMInfo(inf) SDL_GetWindowWMInfo(sdlWindow, inf)
+#endif
+
+/**
+ * Reparent Hatari window if so requested.  Needs to be done inside
+ * Hatari because if SDL itself is requested to reparent itself,
+ * SDL window stops accepting any input (specifically done like
+ * this in SDL backends for some reason).
+ * 
+ * 'noembed' argument tells whether the SDL window should be embedded
+ * or not.
+ *
+ * If the window is embedded (which means that SDL WM window needs
+ * to be hidden) when SDL is asked to fullscreen, Hatari window just
+ * disappears when returning back from fullscreen.  I.e. call this
+ * with noembed=true _before_ fullscreening and any other time with
+ * noembed=false after changing window size.  You can do this by
+ * giving bInFullscreen as the noembed value.
+ */
+void Control_ReparentWindow(int width, int height, bool noembed)
+{
+	Display *display;
+	Window parent_win, sdl_win;
+	const char *parent_win_id;
+	SDL_SysWMinfo info;
+#if !WITH_SDL2
+	Window wm_win;
+#endif
+
+	parent_win_id = getenv("PARENT_WIN_ID");
+	if (!parent_win_id) {
+		return;
+	}
+	parent_win = strtol(parent_win_id, NULL, 0);
+	if (!parent_win) {
+		Log_Printf(LOG_WARN, "Invalid PARENT_WIN_ID value '%s'\n", parent_win_id);
+		return;
+	}
+
+	SDL_VERSION(&info.version);
+	if (!SDL_GetWMInfo(&info)) {
+		Log_Printf(LOG_WARN, "Failed to get SDL_GetWMInfo()\n");
+		return;
+	}
+	display = info.info.x11.display;
+	sdl_win = info.info.x11.window;
+#if !WITH_SDL2
+	wm_win = info.info.x11.wmwindow;
+	info.info.x11.lock_func();
+#endif
+	if (noembed)
+	{
+#if !WITH_SDL2
+		/* show WM window again */
+		XMapWindow(display, wm_win);
+#endif
+	}
+	else
+	{
+		char buffer[12];  /* 32-bits in hex (+ '\r') + '\n' + '\0' */
+
+#if !WITH_SDL2
+		/* hide WM window for Hatari */
+		XUnmapWindow(display, wm_win);
+#endif
+		/* reparent main Hatari window to given parent */
+		XReparentWindow(display, sdl_win, parent_win, 0, 0);
+
+		/* whether to send new window size */
+		if (bSendEmbedInfo && ControlSocket)
+		{
+			fprintf(stderr, "New %dx%d SDL window with ID: %lx\n",
+				width, height, sdl_win);
+			sprintf(buffer, "%dx%d", width, height);
+			if (write(ControlSocket, buffer, strlen(buffer)) < 0)
+				perror("Control_ReparentWindow write");
+		}
+	}
+#if !WITH_SDL2
+	info.info.x11.unlock_func();
+#endif
+}
+
+/**
+ * Return the X connection socket or zero
+ */
+static int Control_GetUISocket(void)
+{
+	SDL_SysWMinfo info;
+	SDL_VERSION(&info.version);
+	if (!SDL_GetWMInfo(&info)) {
+		Log_Printf(LOG_WARN, "Failed to get SDL_GetWMInfo()\n");
+		return 0;
+	}
+	return ConnectionNumber(info.info.x11.display);
+}
+
+#else	/* HAVE_X11 */
+
+static int Control_GetUISocket(void)
+{
+	return 0;
+}
+void Control_ReparentWindow(int width, int height, bool noembed)
+{
+	/* TODO: implement the Windows part.  SDL sources offer example */
+	Log_Printf(LOG_TODO, "Support for Hatari window reparenting not built in\n");
+}
+
+#endif /* HAVE_X11 */
+
+#endif /* HAVE_UNIX_DOMAIN_SOCKETS */
diff --git a/src/convert/high640x8.c b/src/convert/high640x8.c
new file mode 100644
index 0000000..b7a220c
--- /dev/null
+++ b/src/convert/high640x8.c
@@ -0,0 +1,68 @@
+/*
+  Hatari - high640x8.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen Conversion, High Res to 640x8Bit
+*/
+
+
+static void ConvertHighRes_640x8Bit(void)
+{
+	Uint16 *edi, *ebp;
+	Uint32 *esi;
+	Uint16 eax, ebx;
+	int y, x, update;
+
+	edi = (Uint16 *)pSTScreen;        /* ST format screen */
+	ebp = (Uint16 *)pSTScreenCopy;    /* Previous ST format screen */
+	esi = (Uint32 *)pPCScreenDest;    /* PC format screen */
+
+	/* NOTE 'ScrUpdateFlag' is already set (to full update or check, no palettes) */
+	update = ScrUpdateFlag & PALETTEMASK_UPDATEMASK;
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+
+		for (x = 0; x < 40; x++)
+		{
+
+			/* Do 16 pixels at one time */
+			ebx = *edi;
+
+			if (update || ebx != *ebp)  /* Does differ? */
+			{
+				bScreenContentsChanged = true;
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+				/* Plot in 'right-order' on big endian systems */
+				HIGH_BUILD_PIXELS_0 ;               /* Generate pixels [12,13,14,15] */
+				PLOT_HIGH_640_8BIT(3) ;
+				HIGH_BUILD_PIXELS_1 ;               /* Generate pixels [8,9,10,11] */
+				PLOT_HIGH_640_8BIT(2) ;
+				HIGH_BUILD_PIXELS_2 ;               /* Generate pixels [4,5,6,7] */
+				PLOT_HIGH_640_8BIT(1) ;
+				HIGH_BUILD_PIXELS_3 ;               /* Generate pixels [0,1,2,3] */
+				PLOT_HIGH_640_8BIT(0) ;
+#else
+				/* Plot in 'wrong-order', as ebx is 68000 endian */
+				HIGH_BUILD_PIXELS_0 ;               /* Generate pixels [4,5,6,7] */
+				PLOT_HIGH_640_8BIT(1) ;
+				HIGH_BUILD_PIXELS_1 ;               /* Generate pixels [0,1,2,3] */
+				PLOT_HIGH_640_8BIT(0) ;
+				HIGH_BUILD_PIXELS_2 ;               /* Generate pixels [12,13,14,15] */
+				PLOT_HIGH_640_8BIT(3) ;
+				HIGH_BUILD_PIXELS_3 ;               /* Generate pixels [8,9,10,11] */
+				PLOT_HIGH_640_8BIT(2) ;
+#endif
+			}
+
+			esi += 4;                               /* Next PC pixels */
+			edi += 1;                               /* Next ST pixels */
+			ebp += 1;                               /* Next ST copy pixels */
+		}
+
+		esi += PCScreenBytesPerLine/4 - 40*4;           /* advance to start of next line */
+	}
+}
diff --git a/src/convert/low320x16.c b/src/convert/low320x16.c
new file mode 100644
index 0000000..8be46d1
--- /dev/null
+++ b/src/convert/low320x16.c
@@ -0,0 +1,76 @@
+/*
+  Hatari - low320x16.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen Conversion, Low Res to 320x16Bit
+*/
+
+static void ConvertLowRes_320x16Bit(void)
+{
+	Uint32 *edi, *ebp;
+	Uint16 *esi;
+	Uint32 eax, edx;
+	Uint32 ebx, ecx;
+	int y, x, update;
+
+	Convert_StartFrame();            /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);       /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);   /* Previous ST format screen */
+		esi = (Uint16 *)pPCScreenDest;                    /* PC format screen */
+
+		update = AdjustLinePaletteRemap(y) & PALETTEMASK_UPDATEMASK;
+
+		x = STScreenWidthBytes>>3; /* Amount to draw across in 16-pixels (8 bytes) */
+
+		do    /* x-loop */
+		{
+			/* Do 16 pixels at one time */
+			ebx = *edi;
+			ecx = *(edi+1);
+
+			if (update || ebx!=*ebp || ecx!=*(ebp+1))    /* Does differ? */
+			{
+				/* copy word */
+
+				bScreenContentsChanged = true;
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;      /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_320_16BIT(12) ;
+				LOW_BUILD_PIXELS_1 ;      /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_320_16BIT(4) ;
+				LOW_BUILD_PIXELS_2 ;      /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_320_16BIT(8) ;
+				LOW_BUILD_PIXELS_3 ;      /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_320_16BIT(0) ;
+#else
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;      /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_320_16BIT(4) ;
+				LOW_BUILD_PIXELS_1 ;      /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_320_16BIT(12) ;
+				LOW_BUILD_PIXELS_2 ;      /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_320_16BIT(0) ;
+				LOW_BUILD_PIXELS_3 ;      /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_320_16BIT(8) ;
+#endif
+			}
+
+			esi += 16;                        /* Next PC pixels */
+			edi += 2;                         /* Next ST pixels */
+			ebp += 2;                         /* Next ST copy pixels */
+		}
+		while (--x);                      /* Loop on X */
+
+		/* Offset to next line: */
+		pPCScreenDest = (((Uint8 *)pPCScreenDest)+PCScreenBytesPerLine);
+	}
+}
diff --git a/src/convert/low320x16_spec.c b/src/convert/low320x16_spec.c
new file mode 100644
index 0000000..46ce565
--- /dev/null
+++ b/src/convert/low320x16_spec.c
@@ -0,0 +1,98 @@
+/*
+  Hatari - low320x16_spec.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen Conversion, Low Res Spec512 to 320x16Bit
+*/
+
+static void ConvertLowRes_320x16Bit_Spec(void)
+{
+	Uint32 *edi, *ebp;
+	Uint16 *esi;
+	Uint32 eax, ebx, ecx, edx;
+	Uint32 pixelspace[5]; /* Workspace to store pixels to so can print in right order for Spec512 */
+	int y, x;
+
+	/* on x86, unaligned access macro touches also
+	 * next byte, zero it for code checkers
+	 */
+	pixelspace[4] = 0;
+
+	Spec512_StartFrame();            /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+
+		Spec512_StartScanLine();        /* Build up palettes for every 4 pixels, store in 'ScanLinePalettes' */
+
+		/* Get screen addresses, 'edi'-ST screen, 'ebp'-Previous ST screen, 'esi'-PC screen */
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);       /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);   /* Previous ST format screen */
+		esi = (Uint16 *)pPCScreenDest;                    /* PC format screen */
+
+		x = STScreenWidthBytes >> 3;    /* Amount to draw across in 16-pixels (8 bytes) */
+
+		do  /* x-loop */
+		{
+			ebx = *edi;                 /* Do 16 pixels at one time */
+			ecx = *(edi+1);
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+			/* Convert planes to byte indices - as works in wrong order store to workspace so can read back in order! */
+			LOW_BUILD_PIXELS_0 ;        /* Generate 'ecx' as pixels [12,13,14,15] */
+			pixelspace[3] = ecx;
+			LOW_BUILD_PIXELS_1 ;        /* Generate 'ecx' as pixels [4,5,6,7] */
+			pixelspace[1] = ecx;
+			LOW_BUILD_PIXELS_2 ;        /* Generate 'ecx' as pixels [8,9,10,11] */
+			pixelspace[2] = ecx;
+			LOW_BUILD_PIXELS_3 ;        /* Generate 'ecx' as pixels [0,1,2,3] */
+			pixelspace[0] = ecx;
+#else
+			LOW_BUILD_PIXELS_0 ;        /* Generate 'ecx' as pixels [4,5,6,7] */
+			pixelspace[1] = ecx;
+			LOW_BUILD_PIXELS_1 ;        /* Generate 'ecx' as pixels [12,13,14,15] */
+			pixelspace[3] = ecx;
+			LOW_BUILD_PIXELS_2 ;        /* Generate 'ecx' as pixels [0,1,2,3] */
+			pixelspace[0] = ecx;
+			LOW_BUILD_PIXELS_3 ;        /* Generate 'ecx' as pixels [8,9,10,11] */
+			pixelspace[2] = ecx;
+#endif
+			/* And plot, the Spec512 is offset by 1 pixel and works on 'chunks' of 4 pixels */
+			/* So, we plot 1_4_4_4_3 to give 16 pixels, changing palette between */
+			/* (last one is used for first of next 16-pixels) */
+			ecx = pixelspace[0];
+			PLOT_SPEC512_LEFT_LOW_320_16BIT(0);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 1);
+			PLOT_SPEC512_MID_320_16BIT(1);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 5);
+			PLOT_SPEC512_MID_320_16BIT(5);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 9);
+			PLOT_SPEC512_MID_320_16BIT(9);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_FINAL_PIXELS(pixelspace);
+			PLOT_SPEC512_END_LOW_320_16BIT(13);
+
+			esi += 16;                  /* Next PC pixels */
+			edi += 2;                   /* Next ST pixels */
+			ebp += 2;                   /* Next ST copy pixels */
+		}
+		while (--x);                    /* Loop on X */
+
+		Spec512_EndScanLine();
+
+		/* Offset to next line */
+		pPCScreenDest = (((Uint8 *)pPCScreenDest) + PCScreenBytesPerLine);
+	}
+
+	bScreenContentsChanged = true;
+}
diff --git a/src/convert/low320x32.c b/src/convert/low320x32.c
new file mode 100644
index 0000000..a692791
--- /dev/null
+++ b/src/convert/low320x32.c
@@ -0,0 +1,76 @@
+/*
+  Hatari - low320x32.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen Conversion, Low Res to 320x32Bit
+*/
+
+static void ConvertLowRes_320x32Bit(void)
+{
+	Uint32 *edi, *ebp;
+	Uint32 *esi;
+	Uint32 eax, edx;
+	Uint32 ebx, ecx;
+	int y, x, update;
+
+	Convert_StartFrame();            /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);       /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);   /* Previous ST format screen */
+		esi = (Uint32 *)pPCScreenDest;                    /* PC format screen */
+
+		update = AdjustLinePaletteRemap(y) & PALETTEMASK_UPDATEMASK;
+
+		x = STScreenWidthBytes>>3; /* Amount to draw across in 16-pixels (8 bytes) */
+
+		do    /* x-loop */
+		{
+			/* Do 16 pixels at one time */
+			ebx = *edi;
+			ecx = *(edi+1);
+
+			if (update || ebx!=*ebp || ecx!=*(ebp+1))    /* Does differ? */
+			{
+				/* copy word */
+
+				bScreenContentsChanged = true;
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;      /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_320_32BIT(12) ;
+				LOW_BUILD_PIXELS_1 ;      /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_320_32BIT(4) ;
+				LOW_BUILD_PIXELS_2 ;      /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_320_32BIT(8) ;
+				LOW_BUILD_PIXELS_3 ;      /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_320_32BIT(0) ;
+#else
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;      /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_320_32BIT(4) ;
+				LOW_BUILD_PIXELS_1 ;      /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_320_32BIT(12) ;
+				LOW_BUILD_PIXELS_2 ;      /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_320_32BIT(0) ;
+				LOW_BUILD_PIXELS_3 ;      /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_320_32BIT(8) ;
+#endif
+			}
+
+			esi += 16;                        /* Next PC pixels */
+			edi += 2;                         /* Next ST pixels */
+			ebp += 2;                         /* Next ST copy pixels */
+		}
+		while (--x);                      /* Loop on X */
+
+		/* Offset to next line: */
+		pPCScreenDest = (((Uint8 *)pPCScreenDest)+PCScreenBytesPerLine);
+	}
+}
diff --git a/src/convert/low320x32_spec.c b/src/convert/low320x32_spec.c
new file mode 100644
index 0000000..e64770d
--- /dev/null
+++ b/src/convert/low320x32_spec.c
@@ -0,0 +1,98 @@
+/*
+  Hatari - low320x32_spec.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen Conversion, Low Res Spec512 to 320x32Bit
+*/
+
+static void ConvertLowRes_320x32Bit_Spec(void)
+{
+	Uint32 *edi, *ebp;
+	Uint32 *esi;
+	Uint32 eax, ebx, ecx, edx;
+	Uint32 pixelspace[5]; /* Workspace to store pixels to so can print in right order for Spec512 */
+	int y, x;
+
+	/* on x86, unaligned access macro touches also
+	 * next byte, zero it for code checkers
+	 */
+	pixelspace[4] = 0;
+
+	Spec512_StartFrame();            /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+
+		Spec512_StartScanLine();        /* Build up palettes for every 4 pixels, store in 'ScanLinePalettes' */
+
+		/* Get screen addresses, 'edi'-ST screen, 'ebp'-Previous ST screen, 'esi'-PC screen */
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);       /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);   /* Previous ST format screen */
+		esi = (Uint32 *)pPCScreenDest;                    /* PC format screen */
+
+		x = STScreenWidthBytes >> 3;    /* Amount to draw across in 16-pixels (8 bytes) */
+
+		do  /* x-loop */
+		{
+			ebx = *edi;                 /* Do 16 pixels at one time */
+			ecx = *(edi+1);
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+			/* Convert planes to byte indices - as works in wrong order store to workspace so can read back in order! */
+			LOW_BUILD_PIXELS_0 ;        /* Generate 'ecx' as pixels [12,13,14,15] */
+			pixelspace[3] = ecx;
+			LOW_BUILD_PIXELS_1 ;        /* Generate 'ecx' as pixels [4,5,6,7] */
+			pixelspace[1] = ecx;
+			LOW_BUILD_PIXELS_2 ;        /* Generate 'ecx' as pixels [8,9,10,11] */
+			pixelspace[2] = ecx;
+			LOW_BUILD_PIXELS_3 ;        /* Generate 'ecx' as pixels [0,1,2,3] */
+			pixelspace[0] = ecx;
+#else
+			LOW_BUILD_PIXELS_0 ;        /* Generate 'ecx' as pixels [4,5,6,7] */
+			pixelspace[1] = ecx;
+			LOW_BUILD_PIXELS_1 ;        /* Generate 'ecx' as pixels [12,13,14,15] */
+			pixelspace[3] = ecx;
+			LOW_BUILD_PIXELS_2 ;        /* Generate 'ecx' as pixels [0,1,2,3] */
+			pixelspace[0] = ecx;
+			LOW_BUILD_PIXELS_3 ;        /* Generate 'ecx' as pixels [8,9,10,11] */
+			pixelspace[2] = ecx;
+#endif
+			/* And plot, the Spec512 is offset by 1 pixel and works on 'chunks' of 4 pixels */
+			/* So, we plot 1_4_4_4_3 to give 16 pixels, changing palette between */
+			/* (last one is used for first of next 16-pixels) */
+			ecx = pixelspace[0];
+			PLOT_SPEC512_LEFT_LOW_320_32BIT(0);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 1);
+			PLOT_SPEC512_MID_320_32BIT(1);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 5);
+			PLOT_SPEC512_MID_320_32BIT(5);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 9);
+			PLOT_SPEC512_MID_320_32BIT(9);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_FINAL_PIXELS(pixelspace);
+			PLOT_SPEC512_END_LOW_320_32BIT(13);
+
+			esi += 16;                  /* Next PC pixels */
+			edi += 2;                   /* Next ST pixels */
+			ebp += 2;                   /* Next ST copy pixels */
+		}
+		while (--x);                    /* Loop on X */
+
+		Spec512_EndScanLine();
+
+		/* Offset to next line */
+		pPCScreenDest = (((Uint8 *)pPCScreenDest) + PCScreenBytesPerLine);
+	}
+
+	bScreenContentsChanged = true;
+}
diff --git a/src/convert/low320x8.c b/src/convert/low320x8.c
new file mode 100644
index 0000000..44b8b39
--- /dev/null
+++ b/src/convert/low320x8.c
@@ -0,0 +1,76 @@
+/*
+  Hatari - low320x8.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen conversion function, Low Res to 320x8Bit
+*/
+
+static void ConvertLowRes_320x8Bit(void)
+{
+	Uint32 *edi, *ebp;
+	Uint32 *esi;
+	Uint32 eax, edx;	/* set & used by macros */
+	Uint32 ebx, ecx;
+	int y, x, update;
+
+	Convert_StartFrame();             /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+
+		/* Get screen addresses, 'edi'-ST screen, 'ebp'-Previous ST screen, 'esi'-PC screen */
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);       /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);   /* Previous ST format screen */
+		esi = (Uint32 *)pPCScreenDest;                    /* PC format screen, byte per pixel 256 colors */
+
+		update = AdjustLinePaletteRemap(y) & PALETTEMASK_UPDATEMASK;
+
+		x = STScreenWidthBytes>>3;   /* Amount to draw across in 16-pixels(8 bytes) */
+
+		do    /* x-loop */
+		{
+			/* Do 16 pixels at one time */
+			ebx = *edi;
+			ecx = *(edi+1);
+
+			if (update || ebx!=*ebp || ecx!=*(ebp+1)) /* Does differ? */
+			{
+				/* copy word */
+
+				bScreenContentsChanged = true;
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;    /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_320_8BIT(3) ;
+				LOW_BUILD_PIXELS_1 ;    /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_320_8BIT(1) ;
+				LOW_BUILD_PIXELS_2 ;    /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_320_8BIT(2) ;
+				LOW_BUILD_PIXELS_3 ;    /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_320_8BIT(0) ;
+#else
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;    /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_320_8BIT(1) ;
+				LOW_BUILD_PIXELS_1 ;    /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_320_8BIT(3) ;
+				LOW_BUILD_PIXELS_2 ;    /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_320_8BIT(0) ;
+				LOW_BUILD_PIXELS_3 ;    /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_320_8BIT(2) ;
+#endif
+			}
+
+			esi += 4;                 /* Next PC pixels */
+			edi += 2;                 /* Next ST pixels */
+			ebp += 2;                 /* Next ST copy pixels */
+		}
+		while (--x);             /* Loop on X */
+
+		pPCScreenDest = (((Uint8 *)pPCScreenDest)+PCScreenBytesPerLine);  /* Offset to next line */
+	}
+}
diff --git a/src/convert/low640x16.c b/src/convert/low640x16.c
new file mode 100644
index 0000000..8d69fe9
--- /dev/null
+++ b/src/convert/low640x16.c
@@ -0,0 +1,121 @@
+/*
+  Hatari - low640x16.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen Conversion, Low Res to 640x16Bit
+*/
+
+static void Line_ConvertLowRes_640x16Bit(Uint32 *edi, Uint32 *ebp, Uint32 *esi, Uint32 eax)
+{
+	Uint32 edx;
+	Uint32 ebx, ecx;
+	int x, update, Screen4BytesPerLine;
+
+	x = STScreenWidthBytes>>3;   /* Amount to draw across in 16-pixels(8 bytes) */
+	Screen4BytesPerLine = PCScreenBytesPerLine/4;
+	update = ScrUpdateFlag & PALETTEMASK_UPDATEMASK;
+
+	do    /* x-loop */
+	{
+		/* Do 16 pixels at one time */
+		ebx = *edi;
+		ecx = *(edi+1);
+
+		if (update || ebx != *ebp || ecx != *(ebp+1))    /* Does differ? */
+		{
+			/* copy word */
+
+			bScreenContentsChanged = true;
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+			/* Plot in 'right-order' on big endian systems */
+			if (!bScrDoubleY)                     /* Double on Y? */
+			{
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_640_16BIT(12) ;
+				LOW_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_640_16BIT(4) ;
+				LOW_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_640_16BIT(8) ;
+				LOW_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_640_16BIT(0) ;
+			}
+			else
+			{
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_640_16BIT_DOUBLE_Y(12) ;
+				LOW_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_640_16BIT_DOUBLE_Y(4) ;
+				LOW_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_640_16BIT_DOUBLE_Y(8) ;
+				LOW_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_640_16BIT_DOUBLE_Y(0)
+			}
+#else
+			/* Plot in 'wrong-order', as ebx is 68000 endian */
+			if (!bScrDoubleY)                  /* Double on Y? */
+			{
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_640_16BIT(4) ;
+				LOW_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_640_16BIT(12) ;
+				LOW_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_640_16BIT(0) ;
+				LOW_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_640_16BIT(8) ;
+			}
+			else
+			{
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_640_16BIT_DOUBLE_Y(4) ;
+				LOW_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_640_16BIT_DOUBLE_Y(12) ;
+				LOW_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_640_16BIT_DOUBLE_Y(0) ;
+				LOW_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_640_16BIT_DOUBLE_Y(8)
+			}
+#endif
+
+		}
+
+		esi += 16;                      /* Next PC pixels */
+		edi += 2;                       /* Next ST pixels */
+		ebp += 2;                       /* Next ST copy pixels */
+	}
+	while (--x);                        /* Loop on X */
+
+}
+
+static void ConvertLowRes_640x16Bit(void)
+{
+	Uint32 *edi, *ebp;
+	Uint32 *esi;
+	Uint32 eax;
+	int y;
+
+	Convert_StartFrame();            /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+
+		/* Get screen addresses */
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);        /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);    /* Previous ST format screen */
+		esi = (Uint32 *)pPCScreenDest;                     /* PC format screen */
+
+		if (AdjustLinePaletteRemap(y) & 0x00030000)        /* Change palette table */
+			Line_ConvertMediumRes_640x16Bit(edi, ebp, (Uint16 *)esi, eax);
+		else
+			Line_ConvertLowRes_640x16Bit(edi, ebp, esi, eax);
+
+		pPCScreenDest = (((Uint8 *)pPCScreenDest)+PCScreenBytesPerLine*2);  /* Offset to next line */
+	}
+}
diff --git a/src/convert/low640x16_spec.c b/src/convert/low640x16_spec.c
new file mode 100644
index 0000000..832d83a
--- /dev/null
+++ b/src/convert/low640x16_spec.c
@@ -0,0 +1,130 @@
+/*
+  Hatari - low640x16_spec.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen conversion, Low Res Spec512 to 640x16Bit
+*/
+
+static void ConvertLowRes_640x16Bit_Spec(void)
+{
+	Uint32 *edi, *ebp;
+	Uint32 *esi;
+	Uint32 eax;
+	int y;
+
+	Spec512_StartFrame();            /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);        /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);    /* Previous ST format screen */
+		esi = (Uint32 *)pPCScreenDest;                     /* PC format screen */
+
+		Line_ConvertLowRes_640x16Bit_Spec(edi, ebp, esi, eax);
+
+		/* Offset to next line (double on Y) */
+		pPCScreenDest = (((Uint8 *)pPCScreenDest) + PCScreenBytesPerLine * 2);
+	}
+
+        bScreenContentsChanged = true;
+}
+
+
+static void Line_ConvertLowRes_640x16Bit_Spec(Uint32 *edi, Uint32 *ebp, Uint32 *esi, Uint32 eax)
+{
+	Uint32 ebx, ecx, edx;
+	int x, Screen4BytesPerLine;
+	Uint32 pixelspace[5]; /* Workspace to store pixels to so can print in right order for Spec512 */
+
+	/* on x86, unaligned access macro touches also
+	 * next byte, zero it for code checkers
+	 */
+	pixelspace[4] = 0;
+
+	Spec512_StartScanLine();        /* Build up palettes for every 4 pixels, store in 'ScanLinePalettes' */
+
+	x = STScreenWidthBytes >> 3;   /* Amount to draw across in 16-pixels (8 bytes) */
+	Screen4BytesPerLine = PCScreenBytesPerLine/4;
+
+	do  /* x-loop */
+	{
+		ebx = *edi;                 /* Do 16 pixels at one time */
+		ecx = *(edi+1);
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+		/* Convert planes to byte indices - as works in wrong order store to workspace so can read back in order! */
+		LOW_BUILD_PIXELS_0 ;        /* Generate 'ecx' as pixels [12,13,14,15] */
+		pixelspace[3] = ecx;
+		LOW_BUILD_PIXELS_1 ;        /* Generate 'ecx' as pixels [4,5,6,7] */
+		pixelspace[1] = ecx;
+		LOW_BUILD_PIXELS_2 ;        /* Generate 'ecx' as pixels [8,9,10,11] */
+		pixelspace[2] = ecx;
+		LOW_BUILD_PIXELS_3 ;        /* Generate 'ecx' as pixels [0,1,2,3] */
+		pixelspace[0] = ecx;
+#else
+		LOW_BUILD_PIXELS_0 ;        /* Generate 'ecx' as pixels [4,5,6,7] */
+		pixelspace[1] = ecx;
+		LOW_BUILD_PIXELS_1 ;        /* Generate 'ecx' as pixels [12,13,14,15] */
+		pixelspace[3] = ecx;
+		LOW_BUILD_PIXELS_2 ;        /* Generate 'ecx' as pixels [0,1,2,3] */
+		pixelspace[0] = ecx;
+		LOW_BUILD_PIXELS_3 ;        /* Generate 'ecx' as pixels [8,9,10,11] */
+		pixelspace[2] = ecx;
+#endif
+		/* And plot, the Spec512 is offset by 1 pixel and works on 'chunks' of 4 pixels */
+		/* So, we plot 1_4_4_4_3 to give 16 pixels, changing palette between */
+		/* (last one is used for first of next 16-pixels) */
+		if (!bScrDoubleY)           /* Double on Y? */
+		{
+			ecx = pixelspace[0];
+			PLOT_SPEC512_LEFT_LOW_640_16BIT(0);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 1);
+			PLOT_SPEC512_MID_640_16BIT(1);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 5);
+			PLOT_SPEC512_MID_640_16BIT(5);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 9);
+			PLOT_SPEC512_MID_640_16BIT(9);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_FINAL_PIXELS(pixelspace);
+			PLOT_SPEC512_END_LOW_640_16BIT(13);
+		}
+		else
+		{
+			ecx = pixelspace[0];
+			PLOT_SPEC512_LEFT_LOW_640_16BIT_DOUBLE_Y(0);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 1);
+			PLOT_SPEC512_MID_640_16BIT_DOUBLE_Y(1);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 5);
+			PLOT_SPEC512_MID_640_16BIT_DOUBLE_Y(5);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 9);
+			PLOT_SPEC512_MID_640_16BIT_DOUBLE_Y(9);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_FINAL_PIXELS(pixelspace);
+			PLOT_SPEC512_END_LOW_640_16BIT_DOUBLE_Y(13);
+		}
+
+		esi += 16;                  /* Next PC pixels */
+		edi += 2;                   /* Next ST pixels */
+		ebp += 2;                   /* Next ST copy pixels */
+	}
+	while (--x);                    /* Loop on X */
+
+	Spec512_EndScanLine();
+}
diff --git a/src/convert/low640x32.c b/src/convert/low640x32.c
new file mode 100644
index 0000000..5ebea29
--- /dev/null
+++ b/src/convert/low640x32.c
@@ -0,0 +1,121 @@
+/*
+  Hatari - low640x32.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen Conversion, Low Res to 640x32Bit
+*/
+
+static void Line_ConvertLowRes_640x32Bit(Uint32 *edi, Uint32 *ebp, Uint32 *esi, Uint32 eax)
+{
+	Uint32 edx;
+	Uint32 ebx, ecx;
+	int x, update, Screen4BytesPerLine;
+
+	x = STScreenWidthBytes>>3;   /* Amount to draw across in 16-pixels (8 bytes) */
+	Screen4BytesPerLine = PCScreenBytesPerLine/4;
+	update = ScrUpdateFlag & PALETTEMASK_UPDATEMASK;
+
+	do    /* x-loop */
+	{
+		/* Do 16 pixels at one time */
+		ebx = *edi;
+		ecx = *(edi+1);
+
+		if (update || ebx != *ebp || ecx != *(ebp+1))    /* Does differ? */
+		{
+			/* copy word */
+
+			bScreenContentsChanged = true;
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+			/* Plot in 'right-order' on big endian systems */
+			if (!bScrDoubleY)                   /* Double on Y? */
+			{
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0;             /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_640_32BIT(24);
+				LOW_BUILD_PIXELS_1;             /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_640_32BIT(8);
+				LOW_BUILD_PIXELS_2;             /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_640_32BIT(16);
+				LOW_BUILD_PIXELS_3;             /* Generate 'ecx' as pixels [0,1,2,3]] */
+				PLOT_LOW_640_32BIT(0);
+			}
+			else
+			{
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0;             /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_640_32BIT_DOUBLE_Y(24);
+				LOW_BUILD_PIXELS_1;             /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_640_32BIT_DOUBLE_Y(8);
+				LOW_BUILD_PIXELS_2;             /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_640_32BIT_DOUBLE_Y(16);
+				LOW_BUILD_PIXELS_3;             /* Generate 'ecx' as pixels [0,1,2,3]] */
+				PLOT_LOW_640_32BIT_DOUBLE_Y(0);
+			}
+#else
+			/* Plot in 'wrong-order', as ebx is 68000 endian */
+			if (!bScrDoubleY)                   /* Double on Y? */
+			{
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0;             /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_640_32BIT(8);
+				LOW_BUILD_PIXELS_1;             /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_640_32BIT(24);
+				LOW_BUILD_PIXELS_2;             /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_640_32BIT(0);
+				LOW_BUILD_PIXELS_3;             /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_640_32BIT(16);
+			}
+			else
+			{
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0;             /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_640_32BIT_DOUBLE_Y(8);
+				LOW_BUILD_PIXELS_1;             /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_640_32BIT_DOUBLE_Y(24);
+				LOW_BUILD_PIXELS_2;             /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_640_32BIT_DOUBLE_Y(0);
+				LOW_BUILD_PIXELS_3;             /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_640_32BIT_DOUBLE_Y(16);
+			}
+#endif
+
+		}
+
+		esi += 32;                      /* Next PC pixels */
+		edi += 2;                       /* Next ST pixels */
+		ebp += 2;                       /* Next ST copy pixels */
+	}
+	while (--x);                        /* Loop on X */
+
+}
+
+static void ConvertLowRes_640x32Bit(void)
+{
+	Uint32 *edi, *ebp;
+	Uint32 *esi;
+	Uint32 eax;
+	int y;
+
+	Convert_StartFrame();            /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+
+		/* Get screen addresses */
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);        /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);    /* Previous ST format screen */
+		esi = (Uint32 *)pPCScreenDest;                     /* PC format screen */
+
+		if (AdjustLinePaletteRemap(y) & 0x00030000)        /* Change palette table */
+			Line_ConvertMediumRes_640x32Bit(edi, ebp, esi, eax);
+		else
+			Line_ConvertLowRes_640x32Bit(edi, ebp, esi, eax);
+
+		pPCScreenDest = (((Uint8 *)pPCScreenDest)+PCScreenBytesPerLine*2);  /* Offset to next line */
+	}
+}
diff --git a/src/convert/low640x32_spec.c b/src/convert/low640x32_spec.c
new file mode 100644
index 0000000..d22e4a0
--- /dev/null
+++ b/src/convert/low640x32_spec.c
@@ -0,0 +1,130 @@
+/*
+  Hatari - low640x32_spec.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen conversion, Low Res Spec512 to 640x32Bit
+*/
+
+static void ConvertLowRes_640x32Bit_Spec(void)
+{
+	Uint32 *edi, *ebp;
+	Uint32 *esi;
+	Uint32 eax;
+	int y;
+
+	Spec512_StartFrame();            /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);        /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);    /* Previous ST format screen */
+		esi = (Uint32 *)pPCScreenDest;                     /* PC format screen */
+
+		Line_ConvertLowRes_640x32Bit_Spec(edi, ebp, esi, eax);
+
+		/* Offset to next line (double on Y) */
+		pPCScreenDest = (((Uint8 *)pPCScreenDest) + PCScreenBytesPerLine * 2);
+	}
+
+        bScreenContentsChanged = true;
+}
+
+
+static void Line_ConvertLowRes_640x32Bit_Spec(Uint32 *edi, Uint32 *ebp, Uint32 *esi, Uint32 eax)
+{
+	Uint32 ebx, ecx, edx;
+	int x, Screen4BytesPerLine;
+	Uint32 pixelspace[5]; /* Workspace to store pixels to so can print in right order for Spec512 */
+
+	/* on x86, unaligned access macro touches also
+	 * next byte, zero it for code checkers
+	 */
+	pixelspace[4] = 0;
+
+	Spec512_StartScanLine();        /* Build up palettes for every 4 pixels, store in 'ScanLinePalettes' */
+
+	x = STScreenWidthBytes >> 3;   /* Amount to draw across in 16-pixels (8 bytes) */
+	Screen4BytesPerLine = PCScreenBytesPerLine/4;
+
+	do  /* x-loop */
+	{
+		ebx = *edi;                 /* Do 16 pixels at one time */
+		ecx = *(edi+1);
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+		/* Convert planes to byte indices - as works in wrong order store to workspace so can read back in order! */
+		LOW_BUILD_PIXELS_0 ;        /* Generate 'ecx' as pixels [12,13,14,15] */
+		pixelspace[3] = ecx;
+		LOW_BUILD_PIXELS_1 ;        /* Generate 'ecx' as pixels [4,5,6,7] */
+		pixelspace[1] = ecx;
+		LOW_BUILD_PIXELS_2 ;        /* Generate 'ecx' as pixels [8,9,10,11] */
+		pixelspace[2] = ecx;
+		LOW_BUILD_PIXELS_3 ;        /* Generate 'ecx' as pixels [0,1,2,3] */
+		pixelspace[0] = ecx;
+#else
+		LOW_BUILD_PIXELS_0 ;        /* Generate 'ecx' as pixels [4,5,6,7] */
+		pixelspace[1] = ecx;
+		LOW_BUILD_PIXELS_1 ;        /* Generate 'ecx' as pixels [12,13,14,15] */
+		pixelspace[3] = ecx;
+		LOW_BUILD_PIXELS_2 ;        /* Generate 'ecx' as pixels [0,1,2,3] */
+		pixelspace[0] = ecx;
+		LOW_BUILD_PIXELS_3 ;        /* Generate 'ecx' as pixels [8,9,10,11] */
+		pixelspace[2] = ecx;
+#endif
+		/* And plot, the Spec512 is offset by 1 pixel and works on 'chunks' of 4 pixels */
+		/* So, we plot 1_4_4_4_3 to give 16 pixels, changing palette between */
+		/* (last one is used for first of next 16-pixels) */
+		if (!bScrDoubleY)           /* Double on Y? */
+		{
+			ecx = pixelspace[0];
+			PLOT_SPEC512_LEFT_LOW_640_32BIT(0);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 1);
+			PLOT_SPEC512_MID_640_32BIT(2);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 5);
+			PLOT_SPEC512_MID_640_32BIT(10);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 9);
+			PLOT_SPEC512_MID_640_32BIT(18);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_FINAL_PIXELS(pixelspace);
+			PLOT_SPEC512_END_LOW_640_32BIT(26);
+		}
+		else
+		{
+			ecx = pixelspace[0];
+			PLOT_SPEC512_LEFT_LOW_640_32BIT_DOUBLE_Y(0);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 1);
+			PLOT_SPEC512_MID_640_32BIT_DOUBLE_Y(2);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 5);
+			PLOT_SPEC512_MID_640_32BIT_DOUBLE_Y(10);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 9);
+			PLOT_SPEC512_MID_640_32BIT_DOUBLE_Y(18);
+			Spec512_UpdatePaletteSpan();
+
+			ecx = GET_SPEC512_OFFSET_FINAL_PIXELS(pixelspace);
+			PLOT_SPEC512_END_LOW_640_32BIT_DOUBLE_Y(26);
+		}
+
+		esi += 32;                  /* Next PC pixels */
+		edi += 2;                   /* Next ST pixels */
+		ebp += 2;                   /* Next ST copy pixels */
+	}
+	while (--x);                    /* Loop on X */
+
+	Spec512_EndScanLine();
+}
diff --git a/src/convert/low640x8.c b/src/convert/low640x8.c
new file mode 100644
index 0000000..6fd4e54
--- /dev/null
+++ b/src/convert/low640x8.c
@@ -0,0 +1,121 @@
+/*
+  Hatari - low640x8.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen conversion function, Low Res to 640x8Bit
+*/
+
+static void Line_ConvertLowRes_640x8Bit(Uint32 *edi, Uint32 *ebp, Uint32 *esi, Uint32 eax)
+{
+	Uint32 edx;
+	Uint32 ebx, ecx, ebpp;
+	int x, update, Screen4BytesPerLine;
+
+	x = STScreenWidthBytes>>3; /* Amount to draw across in 16-pixels (8 bytes) */
+	Screen4BytesPerLine = PCScreenBytesPerLine/4;
+	update = ScrUpdateFlag & PALETTEMASK_UPDATEMASK;
+
+	do  /* x-loop */
+	{
+		/* Do 16 pixels at one time */
+		ebx = *edi;
+		ecx = *(edi+1);
+
+		if (update || ebx!=*ebp || ecx!=*(ebp+1))   /* Does differ? */
+		{
+			/* copy word */
+
+			bScreenContentsChanged = true;
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+			/* Plot in 'right-order' on big endian systems */
+			if (!bScrDoubleY)                   /* Double on Y? */
+			{
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;            /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_640_8BIT(6) ;
+				LOW_BUILD_PIXELS_1 ;            /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_640_8BIT(2) ;
+				LOW_BUILD_PIXELS_2 ;            /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_640_8BIT(4) ;
+				LOW_BUILD_PIXELS_3 ;            /* Generate 'ecx' as pixels [0,1,2,3]] */
+				PLOT_LOW_640_8BIT(0) ;
+			}
+			else
+			{
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;            /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_640_8BIT_DOUBLE_Y(6) ;
+				LOW_BUILD_PIXELS_1 ;            /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_640_8BIT_DOUBLE_Y(2) ;
+				LOW_BUILD_PIXELS_2 ;            /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_640_8BIT_DOUBLE_Y(4) ;
+				LOW_BUILD_PIXELS_3 ;            /* Generate 'ecx' as pixels [0,1,2,3]] */
+				PLOT_LOW_640_8BIT_DOUBLE_Y(0)
+			}
+#else
+			/* Plot in 'wrong-order', as ebx is 68000 endian */
+			if (!bScrDoubleY)                   /* Double on Y? */
+			{
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;            /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_640_8BIT(2) ;
+				LOW_BUILD_PIXELS_1 ;            /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_640_8BIT(6) ;
+				LOW_BUILD_PIXELS_2 ;            /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_640_8BIT(0) ;
+				LOW_BUILD_PIXELS_3 ;            /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_640_8BIT(4) ;
+			}
+			else
+			{
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;            /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_640_8BIT_DOUBLE_Y(2) ;
+				LOW_BUILD_PIXELS_1 ;            /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_640_8BIT_DOUBLE_Y(6) ;
+				LOW_BUILD_PIXELS_2 ;            /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_640_8BIT_DOUBLE_Y(0) ;
+				LOW_BUILD_PIXELS_3 ;            /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_640_8BIT_DOUBLE_Y(4)
+			}
+#endif
+
+		}
+
+		esi += 8;                       /* Next PC pixels */
+		edi += 2;                       /* Next ST pixels */
+		ebp += 2;                       /* Next ST copy pixels */
+	}
+	while (--x);                        /* Loop on X */
+}
+
+
+static void ConvertLowRes_640x8Bit(void)
+{
+	Uint32 *edi, *ebp;
+	Uint32 *esi;
+	Uint32 eax;
+	int y;
+
+	Convert_StartFrame();           /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+
+		/* Get screen addresses */
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);       /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);   /* Previous ST format screen */
+		esi = (Uint32 *)pPCScreenDest;                    /* PC format screen */
+
+		if (AdjustLinePaletteRemap(y) & 0x00030000)       /* Change palette table */
+			Line_ConvertMediumRes_640x8Bit(edi, ebp, esi, eax);
+		else
+			Line_ConvertLowRes_640x8Bit(edi, ebp, esi, eax);
+
+		pPCScreenDest = (((Uint8 *)pPCScreenDest)+PCScreenBytesPerLine*2);  /* Offset to next line */
+	}
+}
diff --git a/src/convert/macros.h b/src/convert/macros.h
new file mode 100644
index 0000000..282f3a7
--- /dev/null
+++ b/src/convert/macros.h
@@ -0,0 +1,549 @@
+/*
+  Hatari - macros.h
+  
+  Lookup tables and macros for screen conversion routines.
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+*/
+
+#ifndef HATARI_CONVERTMACROS_H
+#define HATARI_CONVERTMACROS_H
+
+/* For palette we don't go from colour '0' as the whole background
+ * would change, so go from this value
+ */
+#define  BASECOLOUR       0x0A
+#define  BASECOLOUR_LONG  0x0A0A0A0A
+
+/* Remap tables to convert from plane format to byte-per-pixel
+ * (Upper is for 4-Planes so if shifted by 2)
+ */
+static const Uint32 Remap_2_Planes[256] = {
+  0x00000000,  0x01000000,  0x00010000,  0x01010000,  0x00000100,  0x01000100,  0x00010100,  0x01010100,
+  0x00000001,  0x01000001,  0x00010001,  0x01010001,  0x00000101,  0x01000101,  0x00010101,  0x01010101,
+  0x02000000,  0x03000000,  0x02010000,  0x03010000,  0x02000100,  0x03000100,  0x02010100,  0x03010100,
+  0x02000001,  0x03000001,  0x02010001,  0x03010001,  0x02000101,  0x03000101,  0x02010101,  0x03010101,
+  0x00020000,  0x01020000,  0x00030000,  0x01030000,  0x00020100,  0x01020100,  0x00030100,  0x01030100,
+  0x00020001,  0x01020001,  0x00030001,  0x01030001,  0x00020101,  0x01020101,  0x00030101,  0x01030101,
+  0x02020000,  0x03020000,  0x02030000,  0x03030000,  0x02020100,  0x03020100,  0x02030100,  0x03030100,
+  0x02020001,  0x03020001,  0x02030001,  0x03030001,  0x02020101,  0x03020101,  0x02030101,  0x03030101,
+  0x00000200,  0x01000200,  0x00010200,  0x01010200,  0x00000300,  0x01000300,  0x00010300,  0x01010300,
+  0x00000201,  0x01000201,  0x00010201,  0x01010201,  0x00000301,  0x01000301,  0x00010301,  0x01010301,
+  0x02000200,  0x03000200,  0x02010200,  0x03010200,  0x02000300,  0x03000300,  0x02010300,  0x03010300,
+  0x02000201,  0x03000201,  0x02010201,  0x03010201,  0x02000301,  0x03000301,  0x02010301,  0x03010301,
+  0x00020200,  0x01020200,  0x00030200,  0x01030200,  0x00020300,  0x01020300,  0x00030300,  0x01030300,
+  0x00020201,  0x01020201,  0x00030201,  0x01030201,  0x00020301,  0x01020301,  0x00030301,  0x01030301,
+  0x02020200,  0x03020200,  0x02030200,  0x03030200,  0x02020300,  0x03020300,  0x02030300,  0x03030300,
+  0x02020201,  0x03020201,  0x02030201,  0x03030201,  0x02020301,  0x03020301,  0x02030301,  0x03030301,
+  0x00000002,  0x01000002,  0x00010002,  0x01010002,  0x00000102,  0x01000102,  0x00010102,  0x01010102,
+  0x00000003,  0x01000003,  0x00010003,  0x01010003,  0x00000103,  0x01000103,  0x00010103,  0x01010103,
+  0x02000002,  0x03000002,  0x02010002,  0x03010002,  0x02000102,  0x03000102,  0x02010102,  0x03010102,
+  0x02000003,  0x03000003,  0x02010003,  0x03010003,  0x02000103,  0x03000103,  0x02010103,  0x03010103,
+  0x00020002,  0x01020002,  0x00030002,  0x01030002,  0x00020102,  0x01020102,  0x00030102,  0x01030102,
+  0x00020003,  0x01020003,  0x00030003,  0x01030003,  0x00020103,  0x01020103,  0x00030103,  0x01030103,
+  0x02020002,  0x03020002,  0x02030002,  0x03030002,  0x02020102,  0x03020102,  0x02030102,  0x03030102,
+  0x02020003,  0x03020003,  0x02030003,  0x03030003,  0x02020103,  0x03020103,  0x02030103,  0x03030103,
+  0x00000202,  0x01000202,  0x00010202,  0x01010202,  0x00000302,  0x01000302,  0x00010302,  0x01010302,
+  0x00000203,  0x01000203,  0x00010203,  0x01010203,  0x00000303,  0x01000303,  0x00010303,  0x01010303,
+  0x02000202,  0x03000202,  0x02010202,  0x03010202,  0x02000302,  0x03000302,  0x02010302,  0x03010302,
+  0x02000203,  0x03000203,  0x02010203,  0x03010203,  0x02000303,  0x03000303,  0x02010303,  0x03010303,
+  0x00020202,  0x01020202,  0x00030202,  0x01030202,  0x00020302,  0x01020302,  0x00030302,  0x01030302,
+  0x00020203,  0x01020203,  0x00030203,  0x01030203,  0x00020303,  0x01020303,  0x00030303,  0x01030303,
+  0x02020202,  0x03020202,  0x02030202,  0x03030202,  0x02020302,  0x03020302,  0x02030302,  0x03030302,
+  0x02020203,  0x03020203,  0x02030203,  0x03030203,  0x02020303,  0x03020303,  0x02030303,  0x03030303,
+};
+
+static const Uint32 Remap_2_Planes_Upper[256] = {
+  0x00000000,  0x04000000,  0x00040000,  0x04040000,  0x00000400,  0x04000400,  0x00040400,  0x04040400,
+  0x00000004,  0x04000004,  0x00040004,  0x04040004,  0x00000404,  0x04000404,  0x00040404,  0x04040404,
+  0x08000000,  0x0C000000,  0x08040000,  0x0C040000,  0x08000400,  0x0C000400,  0x08040400,  0x0C040400,
+  0x08000004,  0x0C000004,  0x08040004,  0x0C040004,  0x08000404,  0x0C000404,  0x08040404,  0x0C040404,
+  0x00080000,  0x04080000,  0x000C0000,  0x040C0000,  0x00080400,  0x04080400,  0x000C0400,  0x040C0400,
+  0x00080004,  0x04080004,  0x000C0004,  0x040C0004,  0x00080404,  0x04080404,  0x000C0404,  0x040C0404,
+  0x08080000,  0x0C080000,  0x080C0000,  0x0C0C0000,  0x08080400,  0x0C080400,  0x080C0400,  0x0C0C0400,
+  0x08080004,  0x0C080004,  0x080C0004,  0x0C0C0004,  0x08080404,  0x0C080404,  0x080C0404,  0x0C0C0404,
+  0x00000800,  0x04000800,  0x00040800,  0x04040800,  0x00000C00,  0x04000C00,  0x00040C00,  0x04040C00,
+  0x00000804,  0x04000804,  0x00040804,  0x04040804,  0x00000C04,  0x04000C04,  0x00040C04,  0x04040C04,
+  0x08000800,  0x0C000800,  0x08040800,  0x0C040800,  0x08000C00,  0x0C000C00,  0x08040C00,  0x0C040C00,
+  0x08000804,  0x0C000804,  0x08040804,  0x0C040804,  0x08000C04,  0x0C000C04,  0x08040C04,  0x0C040C04,
+  0x00080800,  0x04080800,  0x000C0800,  0x040C0800,  0x00080C00,  0x04080C00,  0x000C0C00,  0x040C0C00,
+  0x00080804,  0x04080804,  0x000C0804,  0x040C0804,  0x00080C04,  0x04080C04,  0x000C0C04,  0x040C0C04,
+  0x08080800,  0x0C080800,  0x080C0800,  0x0C0C0800,  0x08080C00,  0x0C080C00,  0x080C0C00,  0x0C0C0C00,
+  0x08080804,  0x0C080804,  0x080C0804,  0x0C0C0804,  0x08080C04,  0x0C080C04,  0x080C0C04,  0x0C0C0C04,
+  0x00000008,  0x04000008,  0x00040008,  0x04040008,  0x00000408,  0x04000408,  0x00040408,  0x04040408,
+  0x0000000C,  0x0400000C,  0x0004000C,  0x0404000C,  0x0000040C,  0x0400040C,  0x0004040C,  0x0404040C,
+  0x08000008,  0x0C000008,  0x08040008,  0x0C040008,  0x08000408,  0x0C000408,  0x08040408,  0x0C040408,
+  0x0800000C,  0x0C00000C,  0x0804000C,  0x0C04000C,  0x0800040C,  0x0C00040C,  0x0804040C,  0x0C04040C,
+  0x00080008,  0x04080008,  0x000C0008,  0x040C0008,  0x00080408,  0x04080408,  0x000C0408,  0x040C0408,
+  0x0008000C,  0x0408000C,  0x000C000C,  0x040C000C,  0x0008040C,  0x0408040C,  0x000C040C,  0x040C040C,
+  0x08080008,  0x0C080008,  0x080C0008,  0x0C0C0008,  0x08080408,  0x0C080408,  0x080C0408,  0x0C0C0408,
+  0x0808000C,  0x0C08000C,  0x080C000C,  0x0C0C000C,  0x0808040C,  0x0C08040C,  0x080C040C,  0x0C0C040C,
+  0x00000808,  0x04000808,  0x00040808,  0x04040808,  0x00000C08,  0x04000C08,  0x00040C08,  0x04040C08,
+  0x0000080C,  0x0400080C,  0x0004080C,  0x0404080C,  0x00000C0C,  0x04000C0C,  0x00040C0C,  0x04040C0C,
+  0x08000808,  0x0C000808,  0x08040808,  0x0C040808,  0x08000C08,  0x0C000C08,  0x08040C08,  0x0C040C08,
+  0x0800080C,  0x0C00080C,  0x0804080C,  0x0C04080C,  0x08000C0C,  0x0C000C0C,  0x08040C0C,  0x0C040C0C,
+  0x00080808,  0x04080808,  0x000C0808,  0x040C0808,  0x00080C08,  0x04080C08,  0x000C0C08,  0x040C0C08,
+  0x0008080C,  0x0408080C,  0x000C080C,  0x040C080C,  0x00080C0C,  0x04080C0C,  0x000C0C0C,  0x040C0C0C,
+  0x08080808,  0x0C080808,  0x080C0808,  0x0C0C0808,  0x08080C08,  0x0C080C08,  0x080C0C08,  0x0C0C0C08,
+  0x0808080C,  0x0C08080C,  0x080C080C,  0x0C0C080C,  0x08080C0C,  0x0C080C0C,  0x080C0C0C,  0x0C0C0C0C,
+};
+
+static const Uint32 Remap_1_Plane[16] = {
+  0x00000000+BASECOLOUR_LONG,  0x01000000+BASECOLOUR_LONG,  0x00010000+BASECOLOUR_LONG,  0x01010000+BASECOLOUR_LONG,  0x00000100+BASECOLOUR_LONG,  0x01000100+BASECOLOUR_LONG,  0x00010100+BASECOLOUR_LONG,  0x01010100+BASECOLOUR_LONG,
+  0x00000001+BASECOLOUR_LONG,  0x01000001+BASECOLOUR_LONG,  0x00010001+BASECOLOUR_LONG,  0x01010001+BASECOLOUR_LONG,  0x00000101+BASECOLOUR_LONG,  0x01000101+BASECOLOUR_LONG,  0x00010101+BASECOLOUR_LONG,  0x01010101+BASECOLOUR_LONG,
+};
+
+
+
+/*----------------------------------------------------------------------*/
+/* Macros to convert from Atari's planar mode to chunky mode
+ * (1 byte per pixel). Convert by blocks of 4 pixels.
+ * 16 low res pixels -> 4 planes of 16 bits
+ * 16 med res pixels -> 2 planes of 16 bits
+ * 16 hi  res pixels -> 1 plane of 16 bits
+ */
+
+#define LOW_BUILD_PIXELS_0 \
+{ \
+ ebx &= 0x0f0f0f0f; \
+ ecx &= 0x0f0f0f0f; \
+ eax = (ebx >> 12) | ebx; \
+ edx = (ecx >> 12) | ecx; \
+ ecx = Remap_2_Planes_Upper[edx & 0x00ff]; \
+ ecx +=      Remap_2_Planes[eax & 0x00ff]; \
+}
+
+#define LOW_BUILD_PIXELS_1 \
+{ \
+ ecx = Remap_2_Planes_Upper[(edx >> 8) & 0x00ff]; \
+ ecx +=      Remap_2_Planes[(eax >> 8) & 0x00ff]; \
+}
+
+#define LOW_BUILD_PIXELS_2 \
+{ \
+ ebx = (*edi     & 0xf0f0f0f0) >> 4; \
+ ecx = (*(edi+1) & 0xf0f0f0f0) >> 4; \
+ eax = (ebx >> 12) | ebx; \
+ edx = (ecx >> 12) | ecx; \
+ ecx = Remap_2_Planes_Upper[edx & 0x00ff]; \
+ ecx +=      Remap_2_Planes[eax & 0x00ff]; \
+}
+
+#define LOW_BUILD_PIXELS_3 \
+{ \
+ ecx = Remap_2_Planes_Upper[(edx >> 8) & 0x00ff]; \
+ ecx +=      Remap_2_Planes[(eax >> 8) & 0x00ff]; \
+}
+
+
+#define MED_BUILD_PIXELS_0 \
+{ \
+ ebx &= 0x0f0f0f0f; \
+ eax = (ebx >> 12) | ebx; \
+ ecx = Remap_2_Planes[eax & 0x000000ff]; \
+}
+
+#define MED_BUILD_PIXELS_1 \
+{ \
+ ecx = Remap_2_Planes[(eax >> 8) & 0x000000ff]; \
+}
+
+#define MED_BUILD_PIXELS_2 \
+{ \
+ ebx = (*edi & 0xf0f0f0f0) >> 4; \
+ eax = (ebx >> 12) | ebx; \
+ ecx = Remap_2_Planes[eax & 0x000000ff]; \
+}
+
+#define MED_BUILD_PIXELS_3 \
+{ \
+ ecx = Remap_2_Planes[(eax >> 8) & 0x000000ff]; \
+}
+
+
+/* Routines to create 'ecx' pixels - MUST be called in this order */
+#define HIGH_BUILD_PIXELS_0 \
+{ \
+ eax = (ebx & 0x0000000f); \
+}
+
+#define HIGH_BUILD_PIXELS_1 \
+{ \
+ eax = (ebx >> 4) & 0x0000000f;\
+}
+
+#define HIGH_BUILD_PIXELS_2 \
+{ \
+ eax = (ebx >> 8) & 0x0000000f;\
+}
+
+#define HIGH_BUILD_PIXELS_3 \
+{ \
+ eax = (ebx >> 12) & 0x0000000f;\
+}
+
+
+
+/*----------------------------------------------------------------------*/
+/* Macros to plot Atari's pixels in the emulator's buffer
+ * (the buffer can be 32, 16 or 8 bits per pixel)
+ */
+
+/*
+ * 32 bit screen format
+ */
+
+/* Plot Low Resolution (320xH) 32-Bit pixels */
+#define PLOT_LOW_320_32BIT(offset)  \
+{ \
+	esi[offset]   = (Uint32)STRGBPalette[ecx & 0x00ff]; \
+	esi[offset+1] = (Uint32)STRGBPalette[(ecx >> 8) & 0x00ff]; \
+	esi[offset+2] = (Uint32)STRGBPalette[(ecx >> 16) & 0x00ff]; \
+	esi[offset+3] = (Uint32)STRGBPalette[(ecx >> 24) & 0x00ff]; \
+}
+
+/* Plot Low Resolution (640xH) 32-Bit pixels */
+#define PLOT_LOW_640_32BIT(offset) \
+{ \
+	esi[offset+0] = esi[offset+1] = STRGBPalette[ecx & 0x000000ff]; \
+	esi[offset+2] = esi[offset+3] = STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+	esi[offset+4] = esi[offset+5] = STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+	esi[offset+6] = esi[offset+7] = STRGBPalette[(ecx >> 24) & 0x000000ff]; \
+} 
+
+/* Plot Low Resolution (640xH) 16-Bit pixels (Double on Y) */
+#define PLOT_LOW_640_32BIT_DOUBLE_Y(offset) \
+{ \
+	ebx = STRGBPalette[ecx & 0x000000ff]; \
+	esi[offset+0] = esi[offset+1] = esi[offset+Screen4BytesPerLine+0] \
+	   = esi[offset+Screen4BytesPerLine+1] = ebx; \
+	ebx = STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+	esi[offset+2] = esi[offset+3] = esi[offset+Screen4BytesPerLine+2] \
+	   = esi[offset+Screen4BytesPerLine+3] = ebx; \
+	ebx = STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+	esi[offset+4] = esi[offset+5] = esi[offset+Screen4BytesPerLine+4] \
+	   = esi[offset+Screen4BytesPerLine+5] = ebx; \
+	ebx = STRGBPalette[(ecx >> 24) & 0x000000ff]; \
+	esi[offset+6] = esi[offset+7] = esi[offset+Screen4BytesPerLine+6] \
+	   = esi[offset+Screen4BytesPerLine+7] = ebx; \
+}
+
+/* Plot Medium Resolution(640xH) 32-Bit pixels */
+#define PLOT_MED_640_32BIT(offset) \
+{ \
+	esi[offset+0] = STRGBPalette[ecx & 0x000000ff]; \
+	esi[offset+1] = STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+	esi[offset+2] = STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+	esi[offset+3] = STRGBPalette[(ecx >> 24) & 0x000000ff]; \
+}
+
+/* Plot Medium Resolution(640xH) 32-Bit pixels (Double on Y) */
+#define PLOT_MED_640_32BIT_DOUBLE_Y(offset) \
+{ \
+	esi[offset+0+Screen4BytesPerLine]   = \
+	esi[offset+0] = STRGBPalette[ecx & 0x000000ff]; \
+	esi[offset+1+Screen4BytesPerLine] = \
+	esi[offset+1] = STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+	esi[offset+2+Screen4BytesPerLine] = \
+	esi[offset+2] = STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+	esi[offset+3+Screen4BytesPerLine] = \
+	esi[offset+3] = STRGBPalette[(ecx >> 24) & 0x000000ff]; \
+}
+
+
+/* Plot Spectrum512 Resolution (320xH) 32-Bit pixels */
+#define PLOT_SPEC512_LEFT_LOW_320_32BIT(offset)	\
+{ \
+	esi[offset] = STRGBPalette[ecx & 0x000000ff]; \
+}
+
+/* Plot Spectrum512 Resolution (320xH) 32-Bit pixels */
+#define PLOT_SPEC512_MID_320_32BIT PLOT_LOW_320_32BIT
+
+/* Plot Spectrum512 Resolution(320xH) 32-Bit pixels */
+#define PLOT_SPEC512_END_LOW_320_32BIT(offset) \
+{ \
+	esi[offset]   = STRGBPalette[ecx & 0x000000ff]; \
+	esi[offset+1] = STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+	esi[offset+2] = STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+}
+
+
+/* Plot Spectrum512 Resolution (640xH) 32-Bit pixels */
+#define PLOT_SPEC512_LEFT_LOW_640_32BIT(offset)	\
+{ \
+	esi[offset] = esi[offset+1] = STRGBPalette[ecx & 0x000000ff]; \
+}
+
+/* Plot Spectrum512 Resolution (640xH) 32-Bit pixels */
+#define PLOT_SPEC512_MID_640_32BIT PLOT_LOW_640_32BIT
+
+/* Plot Spectrum512 Resolution (640xH) 32-Bit pixels */
+#define PLOT_SPEC512_END_LOW_640_32BIT(offset)	\
+{ \
+	esi[offset+0] = esi[offset+1] = STRGBPalette[ecx & 0x000000ff]; \
+	esi[offset+2] = esi[offset+3] = STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+	esi[offset+4] = esi[offset+5] = STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+}
+
+/* Plot Spectrum512 Resolution (640xH) 32-Bit pixels (Double on Y) */
+#define PLOT_SPEC512_LEFT_LOW_640_32BIT_DOUBLE_Y(offset)	\
+{ \
+	esi[offset+Screen4BytesPerLine] = esi[offset+Screen4BytesPerLine+1] = \
+	esi[offset] = esi[offset+1] = STRGBPalette[ecx & 0x000000ff]; \
+}
+
+/* Plot Spectrum512 Resolution (640xH) 32-Bit pixels (Double on Y) */
+#define PLOT_SPEC512_MID_640_32BIT_DOUBLE_Y PLOT_LOW_640_32BIT_DOUBLE_Y
+
+/* Plot Spectrum512 Resolution (640xH) 32-Bit pixels (Double on Y) */
+#define PLOT_SPEC512_END_LOW_640_32BIT_DOUBLE_Y(offset)	\
+{ \
+	ebx = STRGBPalette[ecx & 0x000000ff]; \
+	esi[offset+Screen4BytesPerLine] = esi[offset+Screen4BytesPerLine+1] \
+	    = esi[offset] = esi[offset+1] = ebx; \
+	ebx = STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+	esi[offset+2+Screen4BytesPerLine] = esi[offset+3+Screen4BytesPerLine] \
+	    = esi[offset+2] = esi[offset+3] = ebx; \
+	ebx = STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+	esi[offset+4+Screen4BytesPerLine] = esi[offset+5+Screen4BytesPerLine] \
+	    = esi[offset+4] = esi[offset+5] = ebx; \
+}
+
+
+/* Plot Spectrum512 Medium Resolution (640xH) 32-Bit pixels */
+#define PLOT_SPEC512_LEFT_MED_640_32BIT	PLOT_SPEC512_LEFT_LOW_320_32BIT
+
+#define PLOT_SPEC512_MID_MED_640_32BIT PLOT_SPEC512_MID_320_32BIT
+
+#define PLOT_SPEC512_END_MED_640_32BIT PLOT_SPEC512_END_LOW_320_32BIT
+
+
+/* Plot Spectrum512 Medium Resolution (640xH) 32-Bit pixels (Double on Y) */
+#define PLOT_SPEC512_LEFT_MED_640_32BIT_DOUBLE_Y(offset) \
+{ \
+	esi[offset+Screen4BytesPerLine] = esi[offset] = STRGBPalette[ecx & 0x000000ff]; \
+}
+
+#define PLOT_SPEC512_MID_MED_640_32BIT_DOUBLE_Y(offset) \
+{ \
+	esi[offset+0+Screen4BytesPerLine] = esi[offset+0] = STRGBPalette[ecx & 0x000000ff]; \
+	esi[offset+1+Screen4BytesPerLine] = esi[offset+1] = STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+	esi[offset+2+Screen4BytesPerLine] = esi[offset+2] = STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+	esi[offset+3+Screen4BytesPerLine] = esi[offset+3] = STRGBPalette[(ecx >> 24) & 0x000000ff]; \
+}
+
+#define PLOT_SPEC512_END_MED_640_32BIT_DOUBLE_Y(offset) \
+{ \
+	esi[offset+0+Screen4BytesPerLine] = esi[offset+0] = STRGBPalette[ecx & 0x000000ff]; \
+	esi[offset+1+Screen4BytesPerLine] = esi[offset+1] = STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+	esi[offset+2+Screen4BytesPerLine] = esi[offset+2] = STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+}
+
+
+
+/*
+ * 16 bit screen format
+ */
+
+/* Plot Low Resolution (320xH) 16-Bit pixels */
+#define PLOT_LOW_320_16BIT(offset)  \
+{ \
+ esi[offset]   = (Uint16)STRGBPalette[ecx & 0x00ff]; \
+ esi[offset+1] = (Uint16)STRGBPalette[(ecx >> 8) & 0x00ff]; \
+ esi[offset+2] = (Uint16)STRGBPalette[(ecx >> 16) & 0x00ff]; \
+ esi[offset+3] = (Uint16)STRGBPalette[(ecx >> 24) & 0x00ff]; \
+}
+
+/* Plot Low Resolution (320xH) 8-Bit pixels */
+#define PLOT_LOW_320_8BIT(offset) \
+{ \
+  esi[offset] = SDL_SwapLE32(ecx + BASECOLOUR_LONG); \
+}
+
+/* Plot Low Resolution (640xH) 8-Bit pixels */
+#define PLOT_LOW_640_8BIT(offset) \
+{ \
+  ebpp = ecx + BASECOLOUR_LONG; \
+  ecx = ((ebpp & 0x0000ff00) << 8) | (ebpp & 0x000000ff); \
+  esi[offset]   = SDL_SwapLE32((ecx << 8) | ecx); \
+  ecx = ((ebpp & 0x00ff0000) >> 8) | (ebpp & 0xff000000); \
+  esi[offset+1] = SDL_SwapLE32((ecx >> 8) | ecx); \
+}
+
+/* Plot Low Resolution (640xH) 8-Bit pixels (double on Y) */
+#define PLOT_LOW_640_8BIT_DOUBLE_Y(offset)	\
+{ \
+  ebpp = ecx + BASECOLOUR_LONG; \
+  ecx = ((ebpp & 0x0000ff00) << 8) | (ebpp & 0x000000ff); \
+  esi[offset+Screen4BytesPerLine] = \
+  esi[offset]   = SDL_SwapLE32((ecx << 8) | ecx); \
+  ecx = ((ebpp & 0x00ff0000) >> 8) | (ebpp & 0xff000000); \
+  esi[offset+1+Screen4BytesPerLine] = \
+  esi[offset+1] = SDL_SwapLE32((ecx >> 8) | ecx); \
+}
+
+/* Plot Low Resolution (640xH) 16-Bit pixels */
+#define PLOT_LOW_640_16BIT(offset) \
+{ \
+ esi[offset]   = STRGBPalette[ecx & 0x000000ff]; \
+ esi[offset+1] = STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+ esi[offset+2] = STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+ esi[offset+3] = STRGBPalette[(ecx >> 24) & 0x000000ff]; \
+} 
+
+/* Plot Low Resolution (640xH) 16-Bit pixels (Double on Y) */
+#define PLOT_LOW_640_16BIT_DOUBLE_Y(offset) \
+{ \
+ ebx = STRGBPalette[ecx & 0x000000ff]; \
+ esi[offset]   = esi[offset+Screen4BytesPerLine]   = ebx; \
+ ebx = STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+ esi[offset+1] = esi[offset+1+Screen4BytesPerLine] = ebx; \
+ ebx = STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+ esi[offset+2] = esi[offset+2+Screen4BytesPerLine] = ebx; \
+ ebx = STRGBPalette[(ecx >> 24) & 0x000000ff]; \
+ esi[offset+3] = esi[offset+3+Screen4BytesPerLine] = ebx; \
+}
+
+
+/* Plot Medium Resolution (640xH) 8-Bit pixels */
+#define PLOT_MED_640_8BIT(offset) \
+{ \
+  esi[offset] = SDL_SwapLE32(ecx + BASECOLOUR_LONG); \
+}
+
+/* Plot Medium Resolution (640xH) 8-Bit pixels (Double on Y) */
+#define PLOT_MED_640_8BIT_DOUBLE_Y(offset) \
+{ \
+  esi[offset] = esi[offset+Screen4BytesPerLine] =\
+  SDL_SwapLE32(ecx + BASECOLOUR_LONG); \
+}
+
+/* Plot Medium Resolution(640xH) 16-Bit pixels */
+#define PLOT_MED_640_16BIT(offset) \
+{ \
+ esi[offset]   = (Uint16)STRGBPalette[ecx & 0x000000ff]; \
+ esi[offset+1] = (Uint16)STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+ esi[offset+2] = (Uint16)STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+ esi[offset+3] = (Uint16)STRGBPalette[(ecx >> 24) & 0x000000ff]; \
+}
+
+/* Plot Medium Resolution(640xH) 16-Bit pixels (Double on Y) */
+#define PLOT_MED_640_16BIT_DOUBLE_Y(offset) \
+{ \
+ esi[offset+Screen2BytesPerLine]   =\
+ esi[offset]   = (Uint16)STRGBPalette[ecx & 0x000000ff]; \
+ esi[offset+1+Screen2BytesPerLine] =\
+ esi[offset+1] = (Uint16)STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+ esi[offset+2+Screen2BytesPerLine] =\
+ esi[offset+2] = (Uint16)STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+ esi[offset+3+Screen2BytesPerLine] =\
+ esi[offset+3] = (Uint16)STRGBPalette[(ecx >> 24) & 0x000000ff]; \
+}
+
+
+/* Plot High Resolution (640xH) 8-Bit pixels */
+#define PLOT_HIGH_640_8BIT(offset) \
+{ \
+ esi[offset] = SDL_SwapLE32(Remap_1_Plane[eax]); \
+}
+
+
+/* Plot Spectrum512 Resolution(320xH) 16-Bit pixels */
+#define PLOT_SPEC512_LEFT_LOW_320_16BIT(offset)	\
+{ \
+ esi[offset] = (Uint16)STRGBPalette[ecx & 0x000000ff]; \
+}
+
+/* Plot Spectrum512 Resolution(320xH) 16-Bit pixels */
+#define PLOT_SPEC512_MID_320_16BIT PLOT_LOW_640_16BIT
+
+/* Plot Spectrum512 Resolution(320xH) 16-Bit pixels */
+#define PLOT_SPEC512_END_LOW_320_16BIT(offset) \
+{ \
+ esi[offset]   = (Uint16)STRGBPalette[ecx & 0x000000ff]; \
+ esi[offset+1] = (Uint16)STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+ esi[offset+2] = (Uint16)STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+}
+
+
+/* Plot Spectrum512 Resolution (640xH) 16-Bit pixels */
+#define PLOT_SPEC512_LEFT_LOW_640_16BIT(offset)	\
+{ \
+  esi[offset] = STRGBPalette[ecx & 0x000000ff]; \
+}
+
+/* Plot Spectrum512 Resolution (640xH) 16-Bit pixels */
+#define PLOT_SPEC512_MID_640_16BIT PLOT_LOW_640_16BIT
+
+/* Plot Spectrum512 Resolution (640xH) 16-Bit pixels */
+#define PLOT_SPEC512_END_LOW_640_16BIT(offset)	\
+{ \
+  esi[offset]   = STRGBPalette[ecx & 0x000000ff]; \
+  esi[offset+1] = STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+  esi[offset+2] = STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+}
+
+/* Plot Spectrum512 Resolution (640xH) 16-Bit pixels (Double on Y) */
+#define PLOT_SPEC512_LEFT_LOW_640_16BIT_DOUBLE_Y(offset)	\
+{ \
+  esi[offset+Screen4BytesPerLine] = \
+  esi[offset] = STRGBPalette[ecx & 0x000000ff]; \
+}
+
+/* Plot Spectrum512 Resolution (640xH) 16-Bit pixels (Double on Y) */
+#define PLOT_SPEC512_MID_640_16BIT_DOUBLE_Y PLOT_LOW_640_16BIT_DOUBLE_Y
+
+/* Plot Spectrum512 Resolution (640xH) 16-Bit pixels (Double on Y) */
+#define PLOT_SPEC512_END_LOW_640_16BIT_DOUBLE_Y(offset)	\
+{ \
+  ebx = STRGBPalette[ecx & 0x000000ff]; \
+  esi[offset]   = esi[offset+Screen4BytesPerLine]   = ebx; \
+  ebx = STRGBPalette[(ecx >> 8) & 0x000000ff]; \
+  esi[offset+1] = esi[offset+1+Screen4BytesPerLine] = ebx; \
+  ebx = STRGBPalette[(ecx >> 16) & 0x000000ff]; \
+  esi[offset+2] = esi[offset+2+Screen4BytesPerLine] = ebx; \
+}
+
+
+/* Plot Spectrum512 Medium Resolution (640xH) 16-Bit pixels */
+#define PLOT_SPEC512_LEFT_MED_640_16BIT	PLOT_SPEC512_LEFT_LOW_320_16BIT
+
+#define PLOT_SPEC512_MID_MED_640_16BIT PLOT_SPEC512_MID_320_16BIT
+
+#define PLOT_SPEC512_END_MED_640_16BIT PLOT_SPEC512_END_LOW_320_16BIT
+
+
+/* Plot Spectrum512 Medium Resolution (640xH) 16-Bit pixels (Double on Y) */
+#define PLOT_SPEC512_LEFT_MED_640_16BIT_DOUBLE_Y PLOT_SPEC512_LEFT_MED_640_32BIT_DOUBLE_Y
+
+#define PLOT_SPEC512_MID_MED_640_16BIT_DOUBLE_Y PLOT_SPEC512_MID_MED_640_32BIT_DOUBLE_Y
+
+#define PLOT_SPEC512_END_MED_640_16BIT_DOUBLE_Y PLOT_SPEC512_END_MED_640_32BIT_DOUBLE_Y
+
+
+
+/* Get Spec512 pixels which are offset by 1 pixel */
+#if defined(__i386__)    // Unaligned direct access is only supported on i86 platforms
+
+/* on AMD XP, first one is 1/3 faster than aligned access, and
+ * final pixels access ~15% faster than aligned operation below
+ */
+# define GET_SPEC512_OFFSET_PIXELS(pixels, x)  \
+            (*(Uint32 *)(((Uint8 *)pixels) + x))
+# define GET_SPEC512_OFFSET_FINAL_PIXELS(pixels) \
+            (*(Uint32 *)(((Uint8 *)pixels) + 13))
+
+#else
+
+# define GET_SPEC512_OFFSET_PIXELS(pixels, x)  \
+            (((*(Uint32 *)(((Uint8 *)pixels) + x-1)) >> 8) \
+	     | ((*(Uint32 *)(((Uint8 *)pixels) + x+3)) << 24))
+# define GET_SPEC512_OFFSET_FINAL_PIXELS(pixels)  \
+            ((*(Uint32 *)(((Uint8 *)pixels) + 12)) >> 8)
+
+#endif /* __i386__ */
+
+
+#endif /* HATARI_CONVERTMACROS_H */
diff --git a/src/convert/med640x16.c b/src/convert/med640x16.c
new file mode 100644
index 0000000..f3f0379
--- /dev/null
+++ b/src/convert/med640x16.c
@@ -0,0 +1,116 @@
+/*
+  Hatari - low320x8.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen Conversion, Medium Res to 640x16Bit
+*/
+
+static void ConvertMediumRes_640x16Bit(void)
+{
+	Uint32 *edi, *ebp;
+	Uint16 *esi;
+	Uint32 eax;
+	int y;
+
+	Convert_StartFrame();            /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);        /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);    /* Previous ST format screen */
+		esi = (Uint16 *)pPCScreenDest;                     /* PC format screen */
+
+		if (AdjustLinePaletteRemap(y) & 0x00030000)        /* Change palette table */
+			Line_ConvertMediumRes_640x16Bit(edi, ebp, esi, eax);
+		else
+			Line_ConvertLowRes_640x16Bit(edi, ebp, (Uint32 *)esi, eax);
+
+		/* Offset to next line */
+		pPCScreenDest = (((Uint8 *)pPCScreenDest) + PCScreenBytesPerLine * 2);
+	}
+}
+
+
+static void Line_ConvertMediumRes_640x16Bit(Uint32 *edi, Uint32 *ebp, Uint16 *esi, Uint32 eax)
+{
+	Uint32 ebx, ecx;
+	int x, update, Screen2BytesPerLine;
+
+	x = STScreenWidthBytes >> 2;   /* Amount to draw across in 16-pixels (4 bytes) */
+	Screen2BytesPerLine = PCScreenBytesPerLine/2;
+	update = ScrUpdateFlag & PALETTEMASK_UPDATEMASK;
+
+	do  /* x-loop */
+	{
+
+		/* Do 16 pixels at one time */
+		ebx = *edi;
+
+		if (update || ebx != *ebp)      /* Does differ? */
+		{
+			/* copy word */
+
+			bScreenContentsChanged = true;
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+			/* Plot in 'right-order' on big endian systems */
+			if (!bScrDoubleY)                     /* Double on Y? */
+			{
+				MED_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_MED_640_16BIT(12) ;
+				MED_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_MED_640_16BIT(4) ;
+				MED_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_MED_640_16BIT(8) ;
+				MED_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_MED_640_16BIT(0) ;
+			}
+			else
+			{
+				MED_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_MED_640_16BIT_DOUBLE_Y(12) ;
+				MED_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_MED_640_16BIT_DOUBLE_Y(4) ;
+				MED_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_MED_640_16BIT_DOUBLE_Y(8) ;
+				MED_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_MED_640_16BIT_DOUBLE_Y(0) ;
+			}
+#else
+			/* Plot in 'wrong-order', as ebx is 68000 endian */
+			if (!bScrDoubleY)                     /* Double on Y? */
+			{
+				MED_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_MED_640_16BIT(4) ;
+				MED_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_MED_640_16BIT(12) ;
+				MED_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_MED_640_16BIT(0) ;
+				MED_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_MED_640_16BIT(8) ;
+			}
+			else
+			{
+				MED_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_MED_640_16BIT_DOUBLE_Y(4) ;
+				MED_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_MED_640_16BIT_DOUBLE_Y(12) ;
+				MED_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_MED_640_16BIT_DOUBLE_Y(0) ;
+				MED_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_MED_640_16BIT_DOUBLE_Y(8) ;
+			}
+#endif
+		}
+
+		esi += 16;                      /* Next PC pixels */
+		edi += 1;                       /* Next ST pixels */
+		ebp += 1;                       /* Next ST copy pixels */
+	}
+	while (--x);                        /* Loop on X */
+
+}
diff --git a/src/convert/med640x16_spec.c b/src/convert/med640x16_spec.c
new file mode 100644
index 0000000..718f761
--- /dev/null
+++ b/src/convert/med640x16_spec.c
@@ -0,0 +1,118 @@
+/*
+  Hatari - med640x16_spec.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen Conversion, Medium Res Spec512 to 640x16Bit
+*/
+
+static void ConvertMediumRes_640x16Bit_Spec(void)
+{
+	Uint32 *edi, *ebp;
+	Uint16 *esi;
+	Uint32 eax;
+	int y;
+
+	Spec512_StartFrame();            /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);        /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);    /* Previous ST format screen */
+		esi = (Uint16 *)pPCScreenDest;                     /* PC format screen */
+
+		if (HBLPaletteMasks[y] & 0x00030000)               /* Test resolution */
+			Line_ConvertMediumRes_640x16Bit_Spec(edi, ebp, esi, eax);	/* med res line */
+		else
+			Line_ConvertLowRes_640x16Bit_Spec(edi, ebp, (Uint32 *)esi, eax);	/* low res line (double on X) */
+
+		/* Offset to next line (double on Y) */
+		pPCScreenDest = (((Uint8 *)pPCScreenDest) + PCScreenBytesPerLine * 2);
+	}
+
+        bScreenContentsChanged = true;
+}
+
+
+static void Line_ConvertMediumRes_640x16Bit_Spec(Uint32 *edi, Uint32 *ebp, Uint16 *esi, Uint32 eax)
+{
+	Uint32 ebx, ecx;
+	int x, Screen4BytesPerLine;
+	Uint32 pixelspace[5]; /* Workspace to store pixels to so can print in right order for Spec512 */
+
+	/* on x86, unaligned access macro touches also
+	 * next byte, zero it for code checkers
+	 */
+	pixelspace[4] = 0;
+
+	Spec512_StartScanLine();        /* Build up palettes for every 4 pixels, store in 'ScanLinePalettes' */
+
+	x = STScreenWidthBytes >> 2;   /* Amount to draw across in 16-pixels (4 bytes) */
+	Screen4BytesPerLine = PCScreenBytesPerLine/2;
+
+	do  /* x-loop */
+	{
+		/* Do 16 pixels at one time */
+		ebx = *edi;
+
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+		/* Plot in 'right-order' on big endian systems */
+		MED_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+		pixelspace[3] = ecx;
+		MED_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+		pixelspace[1] = ecx;
+		MED_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+		pixelspace[2] = ecx;
+		MED_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+		pixelspace[0] = ecx;
+#else
+		/* Plot in 'wrong-order', as ebx is 68000 endian */
+		MED_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+		pixelspace[1] = ecx;
+		MED_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+		pixelspace[3] = ecx;
+		MED_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+		pixelspace[0] = ecx;
+		MED_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+		pixelspace[2] = ecx;
+#endif
+		/* And plot, the Spec512 is offset by 1 pixel and works on 'chunks' of 4 pixels */
+		/* So, we plot 1_4_4_4_3 to give 16 pixels, changing palette between */
+		/* (last one is used for first of next 16-pixels) */
+		/* NOTE : In med res, we display 16 pixels in 8 cycles, so palette should be */
+		/* updated every 8 pixels, not every 4 pixels (as in low res) */
+		ecx = pixelspace[0];
+		if (!bScrDoubleY)	{ PLOT_SPEC512_LEFT_MED_640_16BIT(0); }
+		else			{ PLOT_SPEC512_LEFT_MED_640_16BIT_DOUBLE_Y(0); }
+//		Spec512_UpdatePaletteSpan();
+
+		ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 1);
+		if (!bScrDoubleY)	{ PLOT_SPEC512_MID_MED_640_16BIT(1); }
+		else			{ PLOT_SPEC512_MID_MED_640_16BIT_DOUBLE_Y(1); }
+		Spec512_UpdatePaletteSpan();
+
+		ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 5);
+		if (!bScrDoubleY)	{ PLOT_SPEC512_MID_MED_640_16BIT(5); }
+		else			{ PLOT_SPEC512_MID_MED_640_16BIT_DOUBLE_Y(5); }
+//		Spec512_UpdatePaletteSpan();
+
+		ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 9);
+		if (!bScrDoubleY)	{ PLOT_SPEC512_MID_MED_640_16BIT(9); }
+		else			{ PLOT_SPEC512_MID_MED_640_16BIT_DOUBLE_Y(9); }
+		Spec512_UpdatePaletteSpan();
+
+		ecx = GET_SPEC512_OFFSET_FINAL_PIXELS(pixelspace);
+		if (!bScrDoubleY)	{ PLOT_SPEC512_END_MED_640_16BIT(13); }
+		else			{ PLOT_SPEC512_END_MED_640_16BIT_DOUBLE_Y(13); }
+
+		esi += 16;                      /* Next PC pixels */
+		edi += 1;                       /* Next ST pixels */
+		ebp += 1;                       /* Next ST copy pixels */
+	}
+	while (--x);                        /* Loop on X */
+
+	Spec512_EndScanLine();
+}
diff --git a/src/convert/med640x32.c b/src/convert/med640x32.c
new file mode 100644
index 0000000..85e3f54
--- /dev/null
+++ b/src/convert/med640x32.c
@@ -0,0 +1,116 @@
+/*
+  Hatari - med640x32.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen Conversion, Medium Res to 640x32Bit
+*/
+
+static void ConvertMediumRes_640x32Bit(void)
+{
+	Uint32 *edi, *ebp;
+	Uint32 *esi;
+	Uint32 eax;
+	int y;
+
+	Convert_StartFrame();            /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);        /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);    /* Previous ST format screen */
+		esi = (Uint32 *)pPCScreenDest;                     /* PC format screen */
+
+		if (AdjustLinePaletteRemap(y) & 0x00030000)        /* Change palette table */
+			Line_ConvertMediumRes_640x32Bit(edi, ebp, esi, eax);
+		else
+			Line_ConvertLowRes_640x32Bit(edi, ebp, esi, eax);
+
+		/* Offset to next line */
+		pPCScreenDest = (((Uint8 *)pPCScreenDest) + PCScreenBytesPerLine * 2);
+	}
+}
+
+
+static void Line_ConvertMediumRes_640x32Bit(Uint32 *edi, Uint32 *ebp, Uint32 *esi, Uint32 eax)
+{
+	Uint32 ebx, ecx;
+	int x, update, Screen4BytesPerLine;
+
+	x = STScreenWidthBytes >> 2;   /* Amount to draw across in 16-pixels (4 bytes) */
+	Screen4BytesPerLine = PCScreenBytesPerLine/4;
+	update = ScrUpdateFlag & PALETTEMASK_UPDATEMASK;
+
+	do  /* x-loop */
+	{
+
+		/* Do 16 pixels at one time */
+		ebx = *edi;
+
+		if (update || ebx != *ebp)      /* Does differ? */
+		{
+			/* copy word */
+
+			bScreenContentsChanged = true;
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+			/* Plot in 'right-order' on big endian systems */
+			if (!bScrDoubleY)                     /* Double on Y? */
+			{
+				MED_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_MED_640_32BIT(12) ;
+				MED_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_MED_640_32BIT(4) ;
+				MED_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_MED_640_32BIT(8) ;
+				MED_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_MED_640_32BIT(0) ;
+			}
+			else
+			{
+				MED_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_MED_640_32BIT_DOUBLE_Y(12) ;
+				MED_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_MED_640_32BIT_DOUBLE_Y(4) ;
+				MED_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_MED_640_32BIT_DOUBLE_Y(8) ;
+				MED_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_MED_640_32BIT_DOUBLE_Y(0) ;
+			}
+#else
+			/* Plot in 'wrong-order', as ebx is 68000 endian */
+			if (!bScrDoubleY)                     /* Double on Y? */
+			{
+				MED_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_MED_640_32BIT(4) ;
+				MED_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_MED_640_32BIT(12) ;
+				MED_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_MED_640_32BIT(0) ;
+				MED_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_MED_640_32BIT(8) ;
+			}
+			else
+			{
+				MED_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_MED_640_32BIT_DOUBLE_Y(4) ;
+				MED_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_MED_640_32BIT_DOUBLE_Y(12) ;
+				MED_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_MED_640_32BIT_DOUBLE_Y(0) ;
+				MED_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_MED_640_32BIT_DOUBLE_Y(8) ;
+			}
+#endif
+		}
+
+		esi += 16;                      /* Next PC pixels */
+		edi += 1;                       /* Next ST pixels */
+		ebp += 1;                       /* Next ST copy pixels */
+	}
+	while (--x);                        /* Loop on X */
+
+}
diff --git a/src/convert/med640x32_spec.c b/src/convert/med640x32_spec.c
new file mode 100644
index 0000000..65ecdc9
--- /dev/null
+++ b/src/convert/med640x32_spec.c
@@ -0,0 +1,118 @@
+/*
+  Hatari - med640x32_spec.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen Conversion, Medium Res Spec512 to 640x32Bit
+*/
+
+static void ConvertMediumRes_640x32Bit_Spec(void)
+{
+	Uint32 *edi, *ebp;
+	Uint32 *esi;
+	Uint32 eax;
+	int y;
+
+	Spec512_StartFrame();            /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);        /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);    /* Previous ST format screen */
+		esi = (Uint32 *)pPCScreenDest;                     /* PC format screen */
+
+		if (HBLPaletteMasks[y] & 0x00030000)               /* Test resolution */
+			Line_ConvertMediumRes_640x32Bit_Spec(edi, ebp, esi, eax);	/* med res line */
+		else
+			Line_ConvertLowRes_640x32Bit_Spec(edi, ebp, esi, eax);		/* low res line (double on X) */
+
+		/* Offset to next line (double on Y) */
+		pPCScreenDest = (((Uint8 *)pPCScreenDest) + PCScreenBytesPerLine * 2);
+	}
+
+        bScreenContentsChanged = true;
+}
+
+
+static void Line_ConvertMediumRes_640x32Bit_Spec(Uint32 *edi, Uint32 *ebp, Uint32 *esi, Uint32 eax)
+{
+	Uint32 ebx, ecx;
+	int x, Screen4BytesPerLine;
+	Uint32 pixelspace[5]; /* Workspace to store pixels to so can print in right order for Spec512 */
+
+	/* on x86, unaligned access macro touches also
+	 * next byte, zero it for code checkers
+	 */
+	pixelspace[4] = 0;
+
+	Spec512_StartScanLine();        /* Build up palettes for every 4 pixels, store in 'ScanLinePalettes' */
+
+	x = STScreenWidthBytes >> 2;   /* Amount to draw across in 16-pixels (4 bytes) */
+	Screen4BytesPerLine = PCScreenBytesPerLine/4;
+
+	do  /* x-loop */
+	{
+		/* Do 16 pixels at one time */
+		ebx = *edi;
+
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+		/* Plot in 'right-order' on big endian systems */
+		MED_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+		pixelspace[3] = ecx;
+		MED_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+		pixelspace[1] = ecx;
+		MED_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+		pixelspace[2] = ecx;
+		MED_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+		pixelspace[0] = ecx;
+#else
+		/* Plot in 'wrong-order', as ebx is 68000 endian */
+		MED_BUILD_PIXELS_0 ;              /* Generate 'ecx' as pixels [4,5,6,7] */
+		pixelspace[1] = ecx;
+		MED_BUILD_PIXELS_1 ;              /* Generate 'ecx' as pixels [12,13,14,15] */
+		pixelspace[3] = ecx;
+		MED_BUILD_PIXELS_2 ;              /* Generate 'ecx' as pixels [0,1,2,3] */
+		pixelspace[0] = ecx;
+		MED_BUILD_PIXELS_3 ;              /* Generate 'ecx' as pixels [8,9,10,11] */
+		pixelspace[2] = ecx;
+#endif
+		/* And plot, the Spec512 is offset by 1 pixel and works on 'chunks' of 4 pixels */
+		/* So, we plot 1_4_4_4_3 to give 16 pixels, changing palette between */
+		/* (last one is used for first of next 16-pixels) */
+		/* NOTE : In med res, we display 16 pixels in 8 cycles, so palette should be */
+		/* updated every 8 pixels, not every 4 pixels (as in low res) */
+		ecx = pixelspace[0];
+		if (!bScrDoubleY)	{ PLOT_SPEC512_LEFT_MED_640_32BIT(0); }
+		else			{ PLOT_SPEC512_LEFT_MED_640_32BIT_DOUBLE_Y(0); }
+//		Spec512_UpdatePaletteSpan();
+
+		ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 1);
+		if (!bScrDoubleY)	{ PLOT_SPEC512_MID_MED_640_32BIT(1); }
+		else			{ PLOT_SPEC512_MID_MED_640_32BIT_DOUBLE_Y(1); }
+		Spec512_UpdatePaletteSpan();
+
+		ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 5);
+		if (!bScrDoubleY)	{ PLOT_SPEC512_MID_MED_640_32BIT(5); }
+		else			{ PLOT_SPEC512_MID_MED_640_32BIT_DOUBLE_Y(5); }
+//		Spec512_UpdatePaletteSpan();
+
+		ecx = GET_SPEC512_OFFSET_PIXELS(pixelspace, 9);
+		if (!bScrDoubleY)	{ PLOT_SPEC512_MID_MED_640_32BIT(9); }
+		else			{ PLOT_SPEC512_MID_MED_640_32BIT_DOUBLE_Y(9); }
+		Spec512_UpdatePaletteSpan();
+
+		ecx = GET_SPEC512_OFFSET_FINAL_PIXELS(pixelspace);
+		if (!bScrDoubleY)	{ PLOT_SPEC512_END_MED_640_32BIT(13); }
+		else			{ PLOT_SPEC512_END_MED_640_32BIT_DOUBLE_Y(13); }
+
+		esi += 16;                      /* Next PC pixels */
+		edi += 1;                       /* Next ST pixels */
+		ebp += 1;                       /* Next ST copy pixels */
+	}
+	while (--x);                        /* Loop on X */
+
+	Spec512_EndScanLine();
+}
diff --git a/src/convert/med640x8.c b/src/convert/med640x8.c
new file mode 100644
index 0000000..bfeb4e9
--- /dev/null
+++ b/src/convert/med640x8.c
@@ -0,0 +1,115 @@
+/*
+  Hatari - med640x8.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen conversion, Medium Res to 640x8Bit
+*/
+
+static void ConvertMediumRes_640x8Bit(void)
+{
+	Uint32 *edi, *ebp;
+	Uint32 *esi;
+	Uint32 eax;
+	int y;
+
+	Convert_StartFrame();          /* Start frame, track palettes */
+
+	for (y = STScreenStartHorizLine; y < STScreenEndHorizLine; y++)
+	{
+
+		eax = STScreenLineOffset[y] + STScreenLeftSkipBytes;  /* Offset for this line + Amount to skip on left hand side */
+		edi = (Uint32 *)((Uint8 *)pSTScreen + eax);       /* ST format screen 4-plane 16 colors */
+		ebp = (Uint32 *)((Uint8 *)pSTScreenCopy + eax);   /* Previous ST format screen */
+		esi = (Uint32 *)pPCScreenDest;                    /* PC format screen */
+
+		if (AdjustLinePaletteRemap(y) & 0x00030000)       /* Change palette table */
+			Line_ConvertMediumRes_640x8Bit(edi, ebp, esi, eax);
+		else
+			Line_ConvertLowRes_640x8Bit(edi, ebp, esi, eax);
+
+		pPCScreenDest = (((Uint8 *)pPCScreenDest)+PCScreenBytesPerLine*2);  /* Offset to next line */
+	}
+}
+
+
+static void Line_ConvertMediumRes_640x8Bit(Uint32 *edi, Uint32 *ebp, Uint32 *esi, Uint32 eax)
+{
+	Uint32 ebx, ecx;
+	int x, update, Screen4BytesPerLine;
+
+	x = STScreenWidthBytes >> 2;    /* Amount to draw across in 16-pixels (4 bytes) */
+	Screen4BytesPerLine = PCScreenBytesPerLine / 4;
+	update = ScrUpdateFlag & PALETTEMASK_UPDATEMASK;
+
+	do  /* x-loop */
+	{
+
+		/* Do 16 pixels at one time */
+		ebx = *edi;
+
+		if (update || ebx != *ebp)      /* Does differ? */
+		{
+			/* copy word */
+
+			bScreenContentsChanged = true;
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+			/* Plot in 'right-order' on big endian systems */
+			if (!bScrDoubleY)                   /* Double on Y? */
+			{
+				MED_BUILD_PIXELS_0 ;            /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_MED_640_8BIT(3) ;
+				MED_BUILD_PIXELS_1 ;            /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_MED_640_8BIT(1) ;
+				MED_BUILD_PIXELS_2 ;            /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_MED_640_8BIT(2) ;
+				MED_BUILD_PIXELS_3 ;            /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_MED_640_8BIT(0) ;
+			}
+			else
+			{
+				MED_BUILD_PIXELS_0 ;            /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_MED_640_8BIT_DOUBLE_Y(3) ;
+				MED_BUILD_PIXELS_1 ;            /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_MED_640_8BIT_DOUBLE_Y(1) ;
+				MED_BUILD_PIXELS_2 ;            /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_MED_640_8BIT_DOUBLE_Y(2) ;
+				MED_BUILD_PIXELS_3 ;            /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_MED_640_8BIT_DOUBLE_Y(0) ;
+			}
+#else
+			/* Plot in 'wrong-order', as ebx is 68000 endian */
+			if (!bScrDoubleY)                   /* Double on Y? */
+			{
+				MED_BUILD_PIXELS_0 ;            /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_MED_640_8BIT(1) ;
+				MED_BUILD_PIXELS_1 ;            /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_MED_640_8BIT(3) ;
+				MED_BUILD_PIXELS_2 ;            /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_MED_640_8BIT(0) ;
+				MED_BUILD_PIXELS_3 ;            /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_MED_640_8BIT(2) ;
+			}
+			else
+			{
+				MED_BUILD_PIXELS_0 ;            /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_MED_640_8BIT_DOUBLE_Y(1) ;
+				MED_BUILD_PIXELS_1 ;            /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_MED_640_8BIT_DOUBLE_Y(3) ;
+				MED_BUILD_PIXELS_2 ;            /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_MED_640_8BIT_DOUBLE_Y(0) ;
+				MED_BUILD_PIXELS_3 ;            /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_MED_640_8BIT_DOUBLE_Y(2) ;
+			}
+#endif
+		}
+
+		esi += 4;                       /* Next PC pixels */
+		edi += 1;                       /* Next ST pixels */
+		ebp += 1;                       /* Next ST copy pixels */
+
+	}
+	while (--x);                        /* Loop on X */
+}
diff --git a/src/convert/routines.h b/src/convert/routines.h
new file mode 100644
index 0000000..df08b05
--- /dev/null
+++ b/src/convert/routines.h
@@ -0,0 +1,43 @@
+/*
+  Hatari - routines.h
+  
+  Definitions for the screen conversion routines
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+*/
+
+#ifndef HATARI_CONVERTROUTINES_H
+#define HATARI_CONVERTROUTINES_H
+
+static void ConvertLowRes_320x8Bit(void);
+static void ConvertLowRes_640x8Bit(void);
+static void Line_ConvertMediumRes_640x8Bit(Uint32 *edi, Uint32 *ebp, Uint32 *esi, Uint32 eax);
+static void ConvertMediumRes_640x8Bit(void);
+static void ConvertHighRes_640x8Bit(void);
+
+static void ConvertLowRes_320x16Bit(void);
+static void ConvertLowRes_640x16Bit(void);
+static void ConvertLowRes_320x16Bit_Spec(void);
+static void Line_ConvertLowRes_640x16Bit_Spec(Uint32 *edi, Uint32 *ebp, Uint32 *esi, Uint32 eax);
+static void ConvertLowRes_640x16Bit_Spec(void);
+static void Line_ConvertMediumRes_640x16Bit(Uint32 *edi, Uint32 *ebp, Uint16 *esi, Uint32 eax);
+static void ConvertMediumRes_640x16Bit(void);
+static void Line_ConvertMediumRes_640x16Bit_Spec(Uint32 *edi, Uint32 *ebp, Uint16 *esi, Uint32 eax);
+static void ConvertMediumRes_640x16Bit_Spec(void);
+
+static void ConvertLowRes_320x32Bit(void);
+static void ConvertLowRes_640x32Bit(void);
+static void ConvertLowRes_320x32Bit_Spec(void);
+static void Line_ConvertLowRes_640x32Bit_Spec(Uint32 *edi, Uint32 *ebp, Uint32 *esi, Uint32 eax);
+static void ConvertLowRes_640x32Bit_Spec(void);
+static void Line_ConvertMediumRes_640x32Bit(Uint32 *edi, Uint32 *ebp, Uint32 *esi, Uint32 eax);
+static void ConvertMediumRes_640x32Bit(void);
+static void Line_ConvertMediumRes_640x32Bit_Spec(Uint32 *edi, Uint32 *ebp, Uint32 *esi, Uint32 eax);
+static void ConvertMediumRes_640x32Bit_Spec(void);
+
+static void ConvertVDIRes_16Colour(void);
+static void ConvertVDIRes_4Colour(void);
+static void ConvertVDIRes_2Colour(void);
+
+#endif /* HATARI_CONVERTROUTINES_H */
diff --git a/src/convert/vdi16.c b/src/convert/vdi16.c
new file mode 100644
index 0000000..3c73f33
--- /dev/null
+++ b/src/convert/vdi16.c
@@ -0,0 +1,75 @@
+/*
+  Hatari - vdi16.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen Conversion, VDI resolution with 16 colors
+*/
+
+static void ConvertVDIRes_16Colour(void)
+{
+	Uint32 *edi, *ebp;
+	Uint32 *esi;
+	Uint32 eax, edx;	/* set & used by macros */
+	Uint32 ebx, ecx;
+	int y, x, update;
+
+	/* Get screen addresses, 'edi'-ST screen, 'ebp'-Previous ST screen,
+	 * 'esi'-PC screen */
+
+	edi = (Uint32 *)pSTScreen;        /* ST format screen 4-plane 16 colors */
+	ebp = (Uint32 *)pSTScreenCopy;    /* Previous ST format screen */
+	update = ScrUpdateFlag & PALETTEMASK_UPDATEMASK;
+
+	for (y = 0; y < VDIHeight; y++)
+	{
+
+		esi = (Uint32 *)pPCScreenDest;  /* PC format screen, byte per pixel 256 colors */
+
+		x = VDIWidth >> 4;              /* Amount to draw across - in 16-pixels (8 bytes) */
+
+		do  /* x-loop */
+		{
+			/* Do 16 pixels at one time */
+			ebx = *edi;
+			ecx = *(edi+1);
+
+			/* Full update? or just test changes? */
+			if (update || ebx != *ebp || ecx != *(ebp+1))   /* Does differ? */
+			{
+				bScreenContentsChanged = true;
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;    /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_320_8BIT(3) ;
+				LOW_BUILD_PIXELS_1 ;    /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_320_8BIT(1) ;
+				LOW_BUILD_PIXELS_2 ;    /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_320_8BIT(2) ;
+				LOW_BUILD_PIXELS_3 ;    /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_320_8BIT(0) ;
+#else
+				/* Plot pixels */
+				LOW_BUILD_PIXELS_0 ;    /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_LOW_320_8BIT(1) ;
+				LOW_BUILD_PIXELS_1 ;    /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_LOW_320_8BIT(3) ;
+				LOW_BUILD_PIXELS_2 ;    /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_LOW_320_8BIT(0) ;
+				LOW_BUILD_PIXELS_3 ;    /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_LOW_320_8BIT(2) ;
+#endif
+			}
+
+			esi += 4;                   /* Next PC pixels */
+			edi += 2;                   /* Next ST pixels */
+			ebp += 2;                   /* Next ST copy pixels */
+		}
+		while (--x);                    /* Loop on X */
+
+		/* Offset to next line */
+		pPCScreenDest = (((Uint8 *)pPCScreenDest) + PCScreenBytesPerLine);
+	}
+}
diff --git a/src/convert/vdi2.c b/src/convert/vdi2.c
new file mode 100644
index 0000000..91b738d
--- /dev/null
+++ b/src/convert/vdi2.c
@@ -0,0 +1,70 @@
+/*
+  Hatari - vdi2.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen Conversion, monochrome VDI resolution
+*/
+
+
+static void ConvertVDIRes_2Colour(void)
+{
+	Uint16 *edi, *ebp;
+	Uint32 *esi;
+	Uint16 eax, ebx;
+	int y, x, update;
+
+	edi = (Uint16 *)pSTScreen;            /* ST format screen */
+	ebp = (Uint16 *)pSTScreenCopy;        /* Previous ST format screen */
+	update = ScrUpdateFlag & PALETTEMASK_UPDATEMASK;
+
+	for (y = 0; y < VDIHeight; y++)
+	{
+
+		esi = (Uint32 *)pPCScreenDest;  /* PC format screen, byte per pixel 256 colors */
+
+		x = VDIWidth >> 4;              /* Amount to draw across in 16-pixels (4 bytes) */
+
+		do  /* x-loop */
+		{
+			/* Do 16 pixels at one time */
+			ebx = *edi;
+
+			if (update || ebx != *ebp)  /* Does differ? */
+			{
+				bScreenContentsChanged = true;
+
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+				/* Plot in 'right-order' on big endian systems */
+				HIGH_BUILD_PIXELS_0 ;   /* Generate pixels [12,13,14,15] */
+				PLOT_HIGH_640_8BIT(3) ;
+				HIGH_BUILD_PIXELS_1 ;   /* Generate pixels [8,9,10,11] */
+				PLOT_HIGH_640_8BIT(2) ;
+				HIGH_BUILD_PIXELS_2 ;   /* Generate pixels [4,5,6,7] */
+				PLOT_HIGH_640_8BIT(1) ;
+				HIGH_BUILD_PIXELS_3 ;   /* Generate pixels [0,1,2,3] */
+				PLOT_HIGH_640_8BIT(0) ;
+#else
+				/* Plot in 'wrong-order', as ebx is 68000 endian */
+				HIGH_BUILD_PIXELS_0 ;   /* Generate pixels [4,5,6,7] */
+				PLOT_HIGH_640_8BIT(1) ;
+				HIGH_BUILD_PIXELS_1 ;   /* Generate pixels [0,1,2,3] */
+				PLOT_HIGH_640_8BIT(0) ;
+				HIGH_BUILD_PIXELS_2 ;   /* Generate pixels [12,13,14,15] */
+				PLOT_HIGH_640_8BIT(3) ;
+				HIGH_BUILD_PIXELS_3 ;   /* Generate pixels [8,9,10,11] */
+				PLOT_HIGH_640_8BIT(2) ;
+#endif
+			}
+
+			esi += 4;                   /* Next PC pixels */
+			edi += 1;                   /* Next ST pixels */
+			ebp += 1;                   /* Next ST copy pixels */
+		}
+		while (--x);                    /* Loop on X */
+
+		/* Offset to next line */
+		pPCScreenDest = (((Uint8 *)pPCScreenDest) + PCScreenBytesPerLine);
+	}
+}
diff --git a/src/convert/vdi4.c b/src/convert/vdi4.c
new file mode 100644
index 0000000..cbb7e8c
--- /dev/null
+++ b/src/convert/vdi4.c
@@ -0,0 +1,70 @@
+/*
+  Hatari - vdi4.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Screen Conversion, VDI resolution with 4 colors
+*/
+
+
+static void ConvertVDIRes_4Colour(void)
+{
+	Uint32 *edi, *ebp;
+	Uint32 *esi;
+	Uint32 eax, ebx, ecx;
+	int y, x, update;
+
+	/* Get screen addresses, 'edi'-ST screen, 'ebp'-Previous ST screen, 'esi'-PC screen */
+	edi = (Uint32 *)pSTScreen;          /* ST format screen 2-plane 4 colors */
+	ebp = (Uint32 *)pSTScreenCopy;      /* Previous ST format screen */
+	update = ScrUpdateFlag & PALETTEMASK_UPDATEMASK;
+
+	for (y = 0; y < VDIHeight; y++)
+	{
+
+		esi = (Uint32 *)pPCScreenDest;  /* PC format screen, byte per pixel 256 colors */
+
+		x = VDIWidth >> 4;              /* Amount to draw across - in 16-pixels (4 bytes) */
+
+		do  /* x-loop */
+		{
+			/* Do 16 pixels at one time */
+			ebx = *edi;
+
+			if (update || ebx != *ebp)  /* Update? */
+			{
+				bScreenContentsChanged = true;
+
+				/* Plot pixels */
+#if SDL_BYTEORDER == SDL_BIG_ENDIAN
+				MED_BUILD_PIXELS_0 ;    /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_MED_640_8BIT(3) ;
+				MED_BUILD_PIXELS_1 ;    /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_MED_640_8BIT(1) ;
+				MED_BUILD_PIXELS_2 ;    /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_MED_640_8BIT(2) ;
+				MED_BUILD_PIXELS_3 ;    /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_MED_640_8BIT(0) ;
+#else
+				MED_BUILD_PIXELS_0 ;    /* Generate 'ecx' as pixels [4,5,6,7] */
+				PLOT_MED_640_8BIT(1) ;
+				MED_BUILD_PIXELS_1 ;    /* Generate 'ecx' as pixels [12,13,14,15] */
+				PLOT_MED_640_8BIT(3) ;
+				MED_BUILD_PIXELS_2 ;    /* Generate 'ecx' as pixels [0,1,2,3] */
+				PLOT_MED_640_8BIT(0) ;
+				MED_BUILD_PIXELS_3 ;    /* Generate 'ecx' as pixels [8,9,10,11] */
+				PLOT_MED_640_8BIT(2) ;
+#endif
+			}
+
+			esi += 4;                   /* Next PC pixels */
+			edi += 1;                   /* Next ST pixels */
+			ebp += 1;                   /* Next ST copy pixels */
+		}
+		while (--x);                    /* Loop on X */
+
+		/* Offset to next line */
+		pPCScreenDest = (((Uint8 *)pPCScreenDest) + PCScreenBytesPerLine);
+	}
+}
diff --git a/src/cpu/CMakeLists.txt b/src/cpu/CMakeLists.txt
new file mode 100644
index 0000000..b86a490
--- /dev/null
+++ b/src/cpu/CMakeLists.txt
@@ -0,0 +1,60 @@
+
+include_directories(. ../.. ../includes ${SDL_INCLUDE_DIR}) 
+
+# Unfortunately we've got to specify the rules for the generated files twice,
+# once for cross compiling (with calling the host cc directly) and once
+# for native compiling so that the rules also work for non-Unix environments...
+if(CMAKE_CROSSCOMPILING)
+
+	add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/build68k
+		COMMAND cc ${CMAKE_CURRENT_SOURCE_DIR}/build68k.c
+		           -o ${CMAKE_CURRENT_BINARY_DIR}/build68k
+		DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/build68k.c)
+
+	add_custom_command(OUTPUT cpudefs.c
+		COMMAND ./build68k < ${CMAKE_CURRENT_SOURCE_DIR}/table68k >cpudefs.c
+		DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/table68k
+			${CMAKE_CURRENT_BINARY_DIR}/build68k)
+
+	add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/gencpu
+		COMMAND cc -I${CMAKE_CURRENT_SOURCE_DIR}
+			   cpudefs.c ${CMAKE_CURRENT_SOURCE_DIR}/gencpu.c
+			   ${CMAKE_CURRENT_SOURCE_DIR}/readcpu.c
+			   -o ${CMAKE_CURRENT_BINARY_DIR}/gencpu
+		DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/gencpu.c
+			${CMAKE_CURRENT_SOURCE_DIR}/readcpu.c cpudefs.c)
+
+	add_custom_command(OUTPUT cpuemu_0.c cpuemu_11.c cpuemu_12.c
+				cpuemu_20.c cpuemu_21.c cpuemu_31.c cpustbl.c
+		COMMAND ${CMAKE_CURRENT_BINARY_DIR}/gencpu
+		DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/gencpu)
+
+else()	# Rules for normal build follow
+
+	add_executable(build68k build68k.c)
+
+	get_target_property(BUILD68K_EXE build68k LOCATION)
+	add_custom_command(OUTPUT cpudefs.c
+		COMMAND ${BUILD68K_EXE} < ${CMAKE_CURRENT_SOURCE_DIR}/table68k >cpudefs.c
+		DEPENDS table68k build68k)
+
+	add_executable(gencpu gencpu.c readcpu.c cpudefs.c)
+
+	get_target_property(GENCPU_EXE gencpu LOCATION)
+	add_custom_command(OUTPUT cpuemu_0.c cpuemu_11.c cpuemu_12.c
+				cpuemu_20.c cpuemu_21.c cpuemu_31.c cpustbl.c
+		COMMAND ${GENCPU_EXE}  DEPENDS gencpu)
+
+endif(CMAKE_CROSSCOMPILING)
+
+
+# Generated cpuemu.c contains a lot of warnings we don't really care about...
+if(CMAKE_COMPILER_IS_GNUCC)
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wno-sign-compare -Wno-shadow")
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wno-unused-variable -Wno-unused-label")
+endif(CMAKE_COMPILER_IS_GNUCC)
+
+add_library(UaeCpu
+	cpudefs.c cpuemu_0.c cpuemu_11.c cpuemu_12.c cpuemu_20.c cpuemu_21.c cpuemu_31.c 
+	cpummu.c cpustbl.c custom.c	hatari-glue.c memory.c newcpu.c readcpu.c fpp.c
+	)
diff --git a/src/cpu/Makefile b/src/cpu/Makefile
new file mode 100755
index 0000000..602ce08
--- /dev/null
+++ b/src/cpu/Makefile
@@ -0,0 +1,94 @@
+# Makefile for Hatari's UAE CPU.
+
+# Include settings
+include ../../Makefile-wii.cnf
+
+
+CFLAGS += -I. -I../.. -I../includes -I../debug -I../gui-sdl -I../falcon $(CPPFLAGS) $(SDL_CFLAGS)
+# disable several warnings for the CPU emu code as it comes from elsewhere
+QUIETCFLAGS = $(CFLAGS) -Wno-unused -Wno-sign-compare -Wno-shadow
+
+
+CPUCSRCS = hatari-glue.c memory.c newcpu.c readcpu.c fpp.c
+
+CPUGENOBS = cpuemu_0.o cpuemu_11.o cpuemu_13.o cpuemu_20.o \
+            cpuemu_21.o cpuemu_22.o cpuemu_23.o cpuemu_24.o cpuemu_31.o cpuemu_32.o cpuemu_33.o cpuemu_40.o \
+            cpudefs.o cpustbl.o
+
+CPU_OBS = $(CPUCSRCS:.c=.o) $(CPUGENOBS)
+
+
+all: libUaeCpu.a
+
+libUaeCpu.a: $(CPU_OBS)
+	$(AR) cru $@ $^
+	$(RANLIB) $@
+
+build68k: build68k.c
+	$(HOSTCC) $(HOSTCFLAGS) -o $@ $<
+
+cpudefs.c: build68k table68k
+	./build68k cpudefs.c
+
+cpudefs-host.o: cpudefs.c
+	$(HOSTCC) $(HOSTCFLAGS) -c -o $@ $<
+
+readcpu-host.o: readcpu.c
+	$(HOSTCC) $(HOSTCFLAGS) -c -o $@ $<
+
+gencpu.o: gencpu.c
+	$(HOSTCC) $(HOSTCFLAGS) -c -o $@ $<
+
+gencpu: gencpu.o readcpu-host.o cpudefs-host.o
+	$(HOSTCC) $(HOSTLDFLAGS) -o $@ $^
+
+cpuemu.c: gencpu
+	./gencpu
+
+
+cpustbl.c: cpuemu.c
+cputbl.h: cpuemu.c
+
+
+# this is for people with low memory (is there a way do do this with a single rule ?)
+cpuemu_0.o: cpuemu.c
+	$(CC) -DPART_1 -c $(QUIETCFLAGS) $< -o $@
+cpuemu_11.o: cpuemu.c
+	$(CC) -DPART_2 -c $(QUIETCFLAGS) $< -o $@
+cpuemu_13.o: cpuemu.c
+	$(CC) -DPART_3 -c $(QUIETCFLAGS) $< -o $@
+cpuemu_20.o: cpuemu.c
+	$(CC) -DPART_4 -c $(QUIETCFLAGS) $< -o $@
+cpuemu_21.o: cpuemu.c
+	$(CC) -DPART_5 -c $(QUIETCFLAGS) $< -o $@
+cpuemu_22.o: cpuemu.c
+	$(CC) -DPART_6 -c $(QUIETCFLAGS) $< -o $@
+cpuemu_23.o: cpuemu.c
+	$(CC) -DPART_7 -c $(QUIETCFLAGS) $< -o $@
+cpuemu_24.o: cpuemu.c
+	$(CC) -DPART_8 -c $(QUIETCFLAGS) $< -o $@
+cpuemu_31.o: cpuemu.c
+	$(CC) -DPART_9 -c $(QUIETCFLAGS) $< -o $@
+cpuemu_32.o: cpuemu.c
+	$(CC) -DPART_10 -c $(QUIETCFLAGS) $< -o $@
+cpuemu_33.o: cpuemu.c
+	$(CC) -DPART_11 -c $(QUIETCFLAGS) $< -o $@
+
+newcpu.o: sysdeps.h hatari-glue.h maccess.h memory.h newcpu.h ../includes/dialog.h
+
+
+clean:
+	$(RM) *.o gencpu build68k libUaeCpu.a
+
+distclean:	clean
+	$(RM) cpudefs.c cpustbl.c cputbl.h cpuemu.c
+	$(RM) *~ *.bak *.orig Makefile.dep
+
+
+# Use "make depend" to generate file dependencies:
+Makefile.dep: Makefile
+	$(CC) -M $(CFLAGS) $(CPUCSRCS) > Makefile.dep
+
+depend: Makefile.dep
+
+-include Makefile.dep
diff --git a/src/cpu/Makefile.dep b/src/cpu/Makefile.dep
new file mode 100644
index 0000000..e69de29
diff --git a/src/cpu/build68k.c b/src/cpu/build68k.c
new file mode 100644
index 0000000..fbfc357
--- /dev/null
+++ b/src/cpu/build68k.c
@@ -0,0 +1,328 @@
+/*
+ * UAE - The Un*x Amiga Emulator
+ *
+ * Read 68000 CPU specs from file "table68k" and build table68k.c
+ *
+ * Copyright 1995,1996 Bernd Schmidt
+ */
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+
+#include 
+//#include 
+#include 
+#include 
+#include 
+
+#define TCHAR char
+
+#include "readcpu.h"
+
+static FILE *tablef;
+static int nextch = 0;
+
+static void getnextch(void)
+{
+    do {
+	nextch = fgetc(tablef);
+	if (nextch == '%') {
+	    do {
+		nextch = fgetc(tablef);
+	    } while (nextch != EOF && nextch != '\n');
+	}
+    } while (nextch != EOF && isspace(nextch));
+}
+
+static int nextchtohex(void)
+{
+    switch (isupper (nextch) ? tolower (nextch) : nextch) {
+     case '0': return 0;
+     case '1': return 1;
+     case '2': return 2;
+     case '3': return 3;
+     case '4': return 4;
+     case '5': return 5;
+     case '6': return 6;
+     case '7': return 7;
+     case '8': return 8;
+     case '9': return 9;
+     case 'a': return 10;
+     case 'b': return 11;
+     case 'c': return 12;
+     case 'd': return 13;
+     case 'e': return 14;
+     case 'f': return 15;
+     default: abort();
+    }
+}
+
+int main(int argc, char **argv)
+{
+    int no_insns = 0;
+
+    printf ("#include \"sysconfig.h\"\n");
+    printf ("#include \"sysdeps.h\"\n");
+    printf ("#include \"readcpu.h\"\n");
+    printf ("struct instr_def defs68k[] = {\n");
+#if 0
+    tablef = fopen("table68k","r");
+    if (tablef == NULL) {
+	fprintf(stderr, "table68k not found\n");
+	exit(1);
+    }
+#else
+    tablef = stdin;
+#endif
+    getnextch();
+    while (nextch != EOF) {
+		int cpulevel, uncpulevel, plevel, sduse;
+		int i;
+
+		char opcstr[256];
+		int bitpos[16];
+		int flagset[5], flaguse[5];
+
+		unsigned int bitmask,bitpattern;
+		int n_variable;
+
+		int head = 0, tail = 0, clocks = 0, fetchmode = 0;
+
+		n_variable = 0;
+		bitmask = bitpattern = 0;
+		memset (bitpos, 0, sizeof(bitpos));
+		for(i=0; i<16; i++) {
+			int currbit;
+			bitmask <<= 1;
+			bitpattern <<= 1;
+
+			switch (nextch) {
+			 case '0': currbit = bit0; bitmask |= 1; break;
+			 case '1': currbit = bit1; bitmask |= 1; bitpattern |= 1; break;
+			 case 'c': currbit = bitc; break;
+			 case 'C': currbit = bitC; break;
+			 case 'f': currbit = bitf; break;
+			 case 'i': currbit = biti; break;
+			 case 'I': currbit = bitI; break;
+			 case 'j': currbit = bitj; break;
+			 case 'J': currbit = bitJ; break;
+			 case 'k': currbit = bitk; break;
+			 case 'K': currbit = bitK; break;
+			 case 's': currbit = bits; break;
+			 case 'S': currbit = bitS; break;
+			 case 'd': currbit = bitd; break;
+			 case 'D': currbit = bitD; break;
+			 case 'r': currbit = bitr; break;
+			 case 'R': currbit = bitR; break;
+			 case 'z': currbit = bitz; break;
+			 case 'p': currbit = bitp; break;
+			 default: abort();
+			}
+			if (!(bitmask & 1)) {
+			bitpos[n_variable] = currbit;
+			n_variable++;
+			}
+
+			if (nextch == '0' || nextch == '1')
+			bitmask |= 1;
+			if (nextch == '1')
+			bitpattern |= 1;
+			getnextch();
+		}
+
+		while (isspace(nextch) || nextch == ':') /* Get CPU level, unimplemented level, and privilege level */
+			getnextch();
+
+		switch (nextch) {
+		 case '0': cpulevel = 0; break;
+		 case '1': cpulevel = 1; break;
+		 case '2': cpulevel = 2; break;
+		 case '3': cpulevel = 3; break;
+		 case '4': cpulevel = 4; break;
+		 case '5': cpulevel = 5; break;
+		 case '6': cpulevel = 6; break;
+		 case '7': cpulevel = 7; break;
+		 default: abort();
+		}
+		getnextch();
+
+		switch (nextch) {
+		 case '0': uncpulevel = 0; break;
+		 case '1': uncpulevel = 1; break;
+		 case '2': uncpulevel = 2; break;
+		 case '3': uncpulevel = 3; break;
+		 case '4': uncpulevel = 4; break;
+		 case '5': uncpulevel = 5; break;
+		 case '6': uncpulevel = 6; break;
+		 case '7': uncpulevel = 7; break;
+		 default: abort();
+		}
+		getnextch();
+
+		switch (nextch) {
+		 case '0': plevel = 0; break;
+		 case '1': plevel = 1; break;
+		 case '2': plevel = 2; break;
+		 case '3': plevel = 3; break;
+		 default: abort();
+		}
+		getnextch();
+
+		while (isspace(nextch))                   /* Get flag set information */
+			getnextch();
+
+		if (nextch != ':')
+			abort();
+
+		for(i = 0; i < 5; i++) {
+			getnextch();
+			switch(nextch){
+			 case '-': flagset[i] = fa_unset; break;
+			 case '/': flagset[i] = fa_isjmp; break;
+			 case '+': flagset[i] = fa_isbranch; break;
+			 case '0': flagset[i] = fa_zero; break;
+			 case '1': flagset[i] = fa_one; break;
+			 case 'x': flagset[i] = fa_dontcare; break;
+			 case '?': flagset[i] = fa_unknown; break;
+			 default: flagset[i] = fa_set; break;
+			}
+		}
+
+		getnextch();
+		while (isspace(nextch))
+			getnextch();
+
+		if (nextch != ':')                        /* Get flag used information */
+			abort();
+
+		for(i = 0; i < 5; i++) {
+			getnextch();
+			switch(nextch){
+			 case '-': flaguse[i] = fu_unused; break;
+			 case '/': flaguse[i] = fu_isjmp; break;
+			 case '+': flaguse[i] = fu_maybecc; break;
+			 case '?': flaguse[i] = fu_unknown; break;
+			 default: flaguse[i] = fu_used; break;
+			}
+		}
+
+		getnextch();
+		while (isspace(nextch))
+			getnextch();
+
+		if (nextch != ':')                        /* Get source/dest usage information */
+			abort();
+
+		getnextch();
+		sduse = nextchtohex() << 4;
+		getnextch();
+		sduse |= nextchtohex();
+
+		getnextch();
+		while (isspace(nextch))
+			getnextch();
+
+		if (nextch != ':')
+			abort();
+
+		if (fgets(opcstr, 250, tablef) != opcstr) {
+			abort();
+		}
+		getnextch();
+
+		if (nextch == '-') {
+			int neg;
+			char fm[20];
+			getnextch();
+			while (isspace(nextch))
+				getnextch();
+			neg = 1;
+			if (nextch == '-') {
+				neg = -1;
+				getnextch();
+			}
+			for (;;) {
+				if (nextch < '0' || nextch > '9')
+					break;
+				head *= 10;
+				head += nextch - '0';
+				nextch = fgetc (tablef);
+			}
+			head *= neg;
+			while (isspace(nextch))
+				getnextch();
+			for (;;) {
+				if (nextch < '0' || nextch > '9')
+					break;
+				tail *= 10;
+				tail += nextch - '0';
+				nextch = fgetc (tablef);
+			}
+			while (isspace(nextch))
+				getnextch();
+			for (;;) {
+				if (nextch < '0' || nextch > '9')
+					break;
+				clocks *= 10;
+				clocks += nextch - '0';
+				nextch = fgetc (tablef);
+			}
+			if (nextch == ' ') {
+				if (fgets(fm, sizeof fm, tablef) != fm) {
+					abort();
+				}
+				if (!strnicmp(fm, "fea", 3))
+					fetchmode = 1;
+				if (!strnicmp(fm, "cea", 3))
+					fetchmode = 2;
+				if (!strnicmp(fm, "fiea", 4))
+					fetchmode = 3;
+				if (!strnicmp(fm, "ciea", 4))
+					fetchmode = 4;
+				if (!strnicmp(fm, "jea", 3))
+					fetchmode = 5;
+			}
+			getnextch();
+		}
+
+		int j;
+		/* Remove superfluous spaces from the string */
+		char *opstrp = opcstr, *osendp;
+		char tmp[100], *p;
+		int slen = 0;
+
+		while (isspace(*opstrp))
+		opstrp++;
+
+		osendp = opstrp;
+		while (*osendp) {
+		if (!isspace (*osendp))
+			slen = osendp - opstrp + 1;
+			osendp++;
+		}
+		opstrp[slen] = 0;
+
+		if (no_insns > 0)
+			printf(",\n");
+		no_insns++;
+		strcpy (tmp, opstrp);
+		strcat (tmp, " ");
+		p = tmp;
+		while (!isspace(*p++));
+		*p = 0;
+		printf("/* %s */\n", tmp);
+		printf("{0x%04X,%2d,{", bitpattern, n_variable);
+		for (j = 0; j < 16; j++) {
+			printf("%2d", bitpos[j]);
+			if (j < 15)
+				printf(",");
+		}
+		printf ("},0x%04X,%d,%d,%d,{", bitmask, cpulevel, uncpulevel, plevel);
+		for(i = 0; i < 5; i++) {
+			printf("{%d,%d}%s", flaguse[i], flagset[i], i == 4 ? "" : ",");
+		}
+		printf("},0x%02x,_T(\"%s\"),%2d,%2d,%2d,%2d}", sduse, opstrp, head, tail, clocks, fetchmode);
+    }
+    printf("};\nint n_defs68k = %d;\n", no_insns);
+    return 0;
+}
diff --git a/src/cpu/compat.h b/src/cpu/compat.h
new file mode 100644
index 0000000..451eb90
--- /dev/null
+++ b/src/cpu/compat.h
@@ -0,0 +1,85 @@
+/*
+  Hatari - compat.h
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  This file contains all the includes and defines specific to windows (such as
+  TCHAR) needed by WinUAE CPU core.
+  The aim is to have minimum changes in WinUae CPU core for next updates.
+*/
+
+#ifndef HATARI_COMPAT_H
+#define HATARI_COMPAT_H
+
+#include 
+
+#include "sysconfig.h"
+
+/* This define is here to remove some Amiga specific code when compiling */
+/* It results in ' #if 0 ' code in newcpu.c code */
+#define AMIGA_ONLY 0
+
+
+#define WINUAE_FOR_HATARI
+
+
+/* this defione is here for newcpu.c compatibility.
+ * In WinUae, it's defined in debug.h" */
+#ifndef MAX_LINEWIDTH
+#define MAX_LINEWIDTH 100
+#endif
+
+#define RTAREA_DEFAULT 0xf00000
+
+/* Laurent */
+/* here only to allow newcpu.c to compile */
+/* Should be removed when newcpu.c 'll be relooked for hatari only*/
+extern int vpos;
+extern int quit_program;  // declared as "int quit_program = 0;" in main.c
+//WinUae ChangeLog: Improve quitting/resetting behaviour: Move quit_program from GUI
+//WinUae ChangeLog: quit_program is now handled in vsync_handler() and m68k_go().
+
+#ifndef REGPARAM
+#define REGPARAM
+#endif
+
+#ifndef REGPARAM2
+#define REGPARAM2
+#endif
+
+#ifndef REGPARAM3
+#define REGPARAM3
+#endif
+
+#ifndef TCHAR
+#define TCHAR char
+#endif
+
+//#ifndef STATIC_INLINE
+//#define STATIC_INLINE static inline
+//#endif
+
+#define _vsnprintf vsnprintf
+#define _tcsncmp strncmp
+#define _istspace isspace
+#define _tcscmp strcmp
+#define _tcslen strlen
+#define _tcsstr strstr
+#define _tcscpy strcpy
+#define _tcsncpy strncpy
+#define _tcscat strcat
+#define _stprintf sprintf
+#define strnicmp strncasecmp
+#define _T(x) x
+
+#define _vsntprintf printf
+
+#define f_out fprintf
+#define console_out printf
+//#define console_out_f printf
+#define console_out_f(...)	{ if ( console_out_FILE ) fprintf ( console_out_FILE , __VA_ARGS__ ); else printf ( __VA_ARGS__ ); }
+#define error_log printf
+#define gui_message console_out_f
+
+#endif
diff --git a/src/cpu/cpu_prefetch.h b/src/cpu/cpu_prefetch.h
new file mode 100644
index 0000000..76f24af
--- /dev/null
+++ b/src/cpu/cpu_prefetch.h
@@ -0,0 +1,530 @@
+
+#ifdef CPUEMU_20
+
+extern uae_u32 get_word_020_prefetch (int);
+extern void continue_020_prefetch(void);
+
+STATIC_INLINE uae_u32 next_iword_020_prefetch (void)
+{
+	uae_u32 r = get_word_020_prefetch (0);
+	m68k_incpci (2);
+	return r;
+}
+STATIC_INLINE uae_u32 next_ilong_020_prefetch (void)
+{
+	uae_u32 r = next_iword_020_prefetch () << 16;
+	r |= next_iword_020_prefetch ();
+	return r;
+}
+
+STATIC_INLINE uae_u32 get_long_020_prefetch (int o)
+{
+	uae_u32 r = get_word_020_prefetch (o) << 16;
+	r |= get_word_020_prefetch (o + 2);
+	return r;
+}
+
+#endif
+
+#ifdef CPUEMU_21
+
+#define CE020_INITCYCLES() \
+	int head = 0, tail = 0, cycles = 0; \
+	unsigned int cu = get_cycles ();
+#define CE020_SAVECYCLES(h,t,c) \
+	head = h; tail = t; cycles = c;
+#define CE020_COUNTCYCLES()
+
+// only for CPU internal cycles
+STATIC_INLINE void do_cycles_ce020_internal(int clocks)
+{
+	if (currprefs.m68k_speed < 0) {
+		regs.ce020extracycles += clocks;
+		return;
+	}
+	int cycs = clocks * cpucycleunit;
+//fprintf ( stderr , "do_cycles_ce020_internal %d %d" , cycs , regs.ce020memcycles );
+	if (regs.ce020memcycles > 0) {
+		if (regs.ce020memcycles >= cycs) {
+			regs.ce020memcycles -= cycs;
+			return;
+		}
+		cycs = cycs - regs.ce020memcycles;
+	}
+//fprintf ( stderr , " -> %d\n" , cycs );
+	regs.ce020memcycles = 0;
+	x_do_cycles (cycs);
+}
+
+STATIC_INLINE void do_cycles_ce020_mem (int clocks, uae_u32 val)
+{
+	x_do_cycles_post (clocks * cpucycleunit, val);
+}
+
+#if 0
+STATIC_INLINE void do_head_cycles_ce020 (int h)
+{
+	if (regs.ce020_tail) {
+		int cycs = regs.ce020_tail_cycles - get_cycles ();
+		if (cycs < 0)
+			cycs = 0;
+		cycs -= h * cpucycleunit;
+		if (cycs)
+			x_do_cycles (cycs < 0 ? -cycs : cycs);
+	} else if (h > 0) {
+		do_cycles_ce020 (h);
+	}
+}
+#endif
+
+void mem_access_delay_long_write_ce020 (uaecptr addr, uae_u32 v);
+void mem_access_delay_word_write_ce020 (uaecptr addr, uae_u32 v);
+void mem_access_delay_byte_write_ce020 (uaecptr addr, uae_u32 v);
+uae_u32 mem_access_delay_byte_read_ce020 (uaecptr addr);
+uae_u32 mem_access_delay_word_read_ce020 (uaecptr addr);
+uae_u32 mem_access_delay_longi_read_ce020 (uaecptr addr);
+uae_u32 mem_access_delay_long_read_ce020 (uaecptr addr);
+
+STATIC_INLINE uae_u32 get_long_ce020 (uaecptr addr)
+{
+	return mem_access_delay_long_read_ce020 (addr);
+}
+STATIC_INLINE uae_u32 get_word_ce020 (uaecptr addr)
+{
+	return mem_access_delay_word_read_ce020 (addr);
+}
+STATIC_INLINE uae_u32 get_byte_ce020 (uaecptr addr)
+{
+	return mem_access_delay_byte_read_ce020 (addr);
+}
+
+STATIC_INLINE void put_long_ce020 (uaecptr addr, uae_u32 v)
+{
+	mem_access_delay_long_write_ce020 (addr, v);
+}
+STATIC_INLINE void put_word_ce020 (uaecptr addr, uae_u32 v)
+{
+	mem_access_delay_word_write_ce020 (addr, v);
+}
+STATIC_INLINE void put_byte_ce020 (uaecptr addr, uae_u32 v)
+{
+	mem_access_delay_byte_write_ce020 (addr, v);
+}
+
+extern void continue_ce020_prefetch(void);
+extern uae_u32 get_word_ce020_prefetch(int);
+
+STATIC_INLINE uae_u32 get_long_ce020_prefetch (int o)
+{
+	uae_u32 v;
+	uae_u16 tmp;
+	v = get_word_ce020_prefetch (o) << 16;
+	tmp = regs.db;
+	v |= get_word_ce020_prefetch (o + 2);
+	regs.db = tmp;
+	return v;
+}
+
+STATIC_INLINE uae_u32 next_iword_020ce (void)
+{
+	uae_u32 r = get_word_ce020_prefetch (0);
+	m68k_incpci (2);
+	return r;
+}
+STATIC_INLINE uae_u32 next_ilong_020ce (void)
+{
+	uae_u32 r = get_long_ce020_prefetch (0);
+	m68k_incpci (4);
+	return r;
+}
+
+STATIC_INLINE void m68k_do_bsr_ce020 (uaecptr oldpc, uae_s32 offset)
+{
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	m68k_incpci (offset);
+}
+STATIC_INLINE void m68k_do_rts_ce020 (void)
+{
+	m68k_setpci (x_get_long (m68k_areg (regs, 7)));
+	m68k_areg (regs, 7) += 4;
+}
+
+
+#endif
+
+#ifdef CPUEMU_22
+
+extern uae_u32 get_word_030_prefetch(int);
+
+STATIC_INLINE void put_long_030(uaecptr addr, uae_u32 v)
+{
+	write_dcache030(addr, v, 2);
+}
+STATIC_INLINE void put_word_030(uaecptr addr, uae_u32 v)
+{
+	write_dcache030(addr, v, 1);
+}
+STATIC_INLINE void put_byte_030(uaecptr addr, uae_u32 v)
+{
+	write_dcache030(addr, v, 0);
+}
+STATIC_INLINE uae_u32 get_long_030(uaecptr addr)
+{
+	return read_dcache030(addr, 2);
+}
+STATIC_INLINE uae_u32 get_word_030(uaecptr addr)
+{
+	return read_dcache030(addr, 1);
+}
+STATIC_INLINE uae_u32 get_byte_030(uaecptr addr)
+{
+	return read_dcache030(addr, 0);
+}
+
+STATIC_INLINE uae_u32 get_long_030_prefetch(int o)
+{
+	uae_u32 v;
+	v = get_word_030_prefetch(o) << 16;
+	v |= get_word_030_prefetch(o + 2);
+	return v;
+}
+
+STATIC_INLINE uae_u32 next_iword_030_prefetch(void)
+{
+	uae_u32 r = get_word_030_prefetch(0);
+	m68k_incpci(2);
+	return r;
+}
+STATIC_INLINE uae_u32 next_ilong_030_prefetch(void)
+{
+	uae_u32 r = get_long_030_prefetch(0);
+	m68k_incpci(4);
+	return r;
+}
+
+STATIC_INLINE void m68k_do_bsr_030(uaecptr oldpc, uae_s32 offset)
+{
+	m68k_areg(regs, 7) -= 4;
+	put_long_030(m68k_areg(regs, 7), oldpc);
+	m68k_incpci(offset);
+}
+STATIC_INLINE void m68k_do_rts_030(void)
+{
+	m68k_setpc(get_long_030(m68k_areg(regs, 7)));
+	m68k_areg(regs, 7) += 4;
+}
+
+#endif
+
+#ifdef CPUEMU_23
+
+extern uae_u32 get_word_ce030_prefetch(int);
+
+STATIC_INLINE void put_long_ce030 (uaecptr addr, uae_u32 v)
+{
+	write_dcache030 (addr, v, 2);
+}
+STATIC_INLINE void put_word_ce030 (uaecptr addr, uae_u32 v)
+{
+	write_dcache030 (addr, v, 1);
+}
+STATIC_INLINE void put_byte_ce030 (uaecptr addr, uae_u32 v)
+{
+	write_dcache030 (addr, v, 0);
+}
+STATIC_INLINE uae_u32 get_long_ce030 (uaecptr addr)
+{
+	return read_dcache030 (addr, 2);
+}
+STATIC_INLINE uae_u32 get_word_ce030 (uaecptr addr)
+{
+	return read_dcache030 (addr, 1);
+}
+STATIC_INLINE uae_u32 get_byte_ce030 (uaecptr addr)
+{
+	return read_dcache030 (addr, 0);
+}
+
+STATIC_INLINE uae_u32 get_long_ce030_prefetch (int o)
+{
+	uae_u32 v;
+	v = get_word_ce030_prefetch (o) << 16;
+	v |= get_word_ce030_prefetch (o + 2);
+	return v;
+}
+
+STATIC_INLINE uae_u32 next_iword_030ce (void)
+{
+	uae_u32 r = get_word_ce030_prefetch (0);
+	m68k_incpci (2);
+	return r;
+}
+STATIC_INLINE uae_u32 next_ilong_030ce (void)
+{
+	uae_u32 r = get_long_ce030_prefetch (0);
+	m68k_incpci (4);
+	return r;
+}
+
+STATIC_INLINE void m68k_do_bsr_ce030 (uaecptr oldpc, uae_s32 offset)
+{
+	m68k_areg (regs, 7) -= 4;
+	put_long_ce030 (m68k_areg (regs, 7), oldpc);
+	m68k_incpci (offset);
+}
+STATIC_INLINE void m68k_do_rts_ce030 (void)
+{
+	m68k_setpc (get_long_ce030 (m68k_areg (regs, 7)));
+	m68k_areg (regs, 7) += 4;
+}
+
+#endif
+
+#ifdef CPUEMU_11
+
+STATIC_INLINE uae_u32 get_word_prefetch (int o)
+{
+	uae_u32 v = regs.irc;
+	regs.irc = regs.db = get_wordi (m68k_getpci () + o);
+	return v;
+}
+STATIC_INLINE uae_u32 get_byte_prefetch (uaecptr addr)
+{
+	uae_u32 v = get_byte (addr);
+	regs.db = (v << 8) | v;
+	return v;
+}
+STATIC_INLINE uae_u32 get_word_prefetch_addr (uaecptr addr)
+{
+	uae_u32 v = get_word (addr);
+	regs.db = v;
+	return v;
+}
+STATIC_INLINE void put_byte_prefetch (uaecptr addr, uae_u32 v)
+{
+	regs.db = (v << 8) | v;
+	put_byte (addr, v);
+}
+STATIC_INLINE void put_word_prefetch (uaecptr addr, uae_u32 v)
+{
+	regs.db = v;
+	put_word (addr, v);
+}
+#endif
+
+#ifdef CPUEMU_13
+
+STATIC_INLINE void do_cycles_ce000_internal(int clocks)
+{
+	if (currprefs.m68k_speed < 0)
+		return;
+	x_do_cycles (clocks * cpucycleunit);
+}
+STATIC_INLINE void do_cycles_ce000 (int clocks)
+{
+	x_do_cycles (clocks * cpucycleunit);
+}
+
+STATIC_INLINE void ipl_fetch (void)
+{
+	regs.ipl = regs.ipl_pin;
+}
+
+STATIC_INLINE uae_u32 mem_access_delay_word_read (uaecptr addr)
+{
+	uae_u32 v;
+#ifndef WINUAE_FOR_HATARI
+	switch (ce_banktype[addr >> 16])
+	{
+	case CE_MEMBANK_CHIP16:
+	case CE_MEMBANK_CHIP32:
+		v = wait_cpu_cycle_read (addr, 1);
+		break;
+	case CE_MEMBANK_FAST16:
+	case CE_MEMBANK_FAST32:
+		v = get_word (addr);
+		x_do_cycles_post (4 * cpucycleunit, v);
+		break;
+	default:
+		v = get_word (addr);
+		break;
+	}
+#else
+	v = get_word (addr);
+	x_do_cycles_post (4 * cpucycleunit, v);
+#endif
+	regs.db = v;
+	return v;
+}
+STATIC_INLINE uae_u32 mem_access_delay_wordi_read (uaecptr addr)
+{
+	uae_u32 v;
+#ifndef WINUAE_FOR_HATARI
+	switch (ce_banktype[addr >> 16])
+	{
+	case CE_MEMBANK_CHIP16:
+	case CE_MEMBANK_CHIP32:
+		v = wait_cpu_cycle_read (addr, 1);
+		break;
+	case CE_MEMBANK_FAST16:
+	case CE_MEMBANK_FAST32:
+		v = get_wordi (addr);
+		x_do_cycles_post (4 * cpucycleunit, v);
+		break;
+	default:
+		v = get_wordi (addr);
+		break;
+	}
+#else
+	v = get_wordi (addr);
+	x_do_cycles_post (4 * cpucycleunit, v);
+#endif
+	regs.db = v;
+	return v;
+}
+
+STATIC_INLINE uae_u32 mem_access_delay_byte_read (uaecptr addr)
+{
+	uae_u32  v;
+#ifndef WINUAE_FOR_HATARI
+	switch (ce_banktype[addr >> 16])
+	{
+	case CE_MEMBANK_CHIP16:
+	case CE_MEMBANK_CHIP32:
+		v = wait_cpu_cycle_read (addr, 0);
+		break;
+	case CE_MEMBANK_FAST16:
+	case CE_MEMBANK_FAST32:
+		v = get_byte (addr);
+		x_do_cycles_post (4 * cpucycleunit, v);
+		break;
+	default:
+		v = get_byte (addr);
+		break;
+	}
+#else
+	v = get_byte (addr);
+	x_do_cycles_post (4 * cpucycleunit, v);
+#endif
+	regs.db = (v << 8) | v;
+	return v;
+}
+STATIC_INLINE void mem_access_delay_byte_write (uaecptr addr, uae_u32 v)
+{
+	regs.db = (v << 8)  | v;
+#ifndef WINUAE_FOR_HATARI
+	switch (ce_banktype[addr >> 16])
+	{
+	case CE_MEMBANK_CHIP16:
+	case CE_MEMBANK_CHIP32:
+		wait_cpu_cycle_write (addr, 0, v);
+		return;
+	case CE_MEMBANK_FAST16:
+	case CE_MEMBANK_FAST32:
+		put_byte (addr, v);
+		x_do_cycles_post (4 * cpucycleunit, v);
+		return;
+	}
+#else
+	put_byte (addr, v);
+	x_do_cycles_post (4 * cpucycleunit, v);
+#endif
+}
+STATIC_INLINE void mem_access_delay_word_write (uaecptr addr, uae_u32 v)
+{
+#ifndef WINUAE_FOR_HATARI
+	regs.db = v;
+	switch (ce_banktype[addr >> 16])
+	{
+	case CE_MEMBANK_CHIP16:
+	case CE_MEMBANK_CHIP32:
+		wait_cpu_cycle_write (addr, 1, v);
+		return;
+	case CE_MEMBANK_FAST16:
+	case CE_MEMBANK_FAST32:
+		put_word (addr, v);
+		x_do_cycles_post (4 * cpucycleunit, v);
+		return;
+	}
+	put_word (addr, v);
+#else
+	put_word (addr, v);
+	x_do_cycles_post (4 * cpucycleunit, v);
+#endif
+}
+
+STATIC_INLINE uae_u32 get_long_ce000 (uaecptr addr)
+{
+	uae_u32 v = mem_access_delay_word_read (addr) << 16;
+	v |= mem_access_delay_word_read (addr + 2);
+	return v;
+}
+STATIC_INLINE uae_u32 get_word_ce000 (uaecptr addr)
+{
+	return mem_access_delay_word_read (addr);
+}
+STATIC_INLINE uae_u32 get_wordi_ce000 (int offset)
+{
+	return mem_access_delay_wordi_read (m68k_getpci () + offset);
+}
+STATIC_INLINE uae_u32 get_byte_ce000 (uaecptr addr)
+{
+	return mem_access_delay_byte_read (addr);
+}
+STATIC_INLINE uae_u32 get_word_ce000_prefetch (int o)
+{
+	uae_u32 v = regs.irc;
+	regs.irc = regs.db = x_get_iword (o);
+	return v;
+}
+
+STATIC_INLINE void put_long_ce000 (uaecptr addr, uae_u32 v)
+{
+	mem_access_delay_word_write (addr, v >> 16);
+	mem_access_delay_word_write (addr + 2, v);
+}
+STATIC_INLINE void put_word_ce000 (uaecptr addr, uae_u32 v)
+{
+	mem_access_delay_word_write (addr, v);
+}
+STATIC_INLINE void put_byte_ce000 (uaecptr addr, uae_u32 v)
+{
+	mem_access_delay_byte_write (addr, v);
+}
+
+STATIC_INLINE void m68k_do_rts_ce (void)
+{
+	uaecptr pc;
+	pc = x_get_word (m68k_areg (regs, 7)) << 16;
+	pc |= x_get_word (m68k_areg (regs, 7) + 2);
+	m68k_areg (regs, 7) += 4;
+	m68k_setpci (pc);
+}
+
+STATIC_INLINE void m68k_do_bsr_ce (uaecptr oldpc, uae_s32 offset)
+{
+	m68k_areg (regs, 7) -= 4;
+	x_put_word (m68k_areg (regs, 7), oldpc >> 16);
+	x_put_word (m68k_areg (regs, 7) + 2, oldpc);
+	m68k_incpci (offset);
+}
+
+STATIC_INLINE void m68k_do_jsr_ce (uaecptr oldpc, uaecptr dest)
+{
+	m68k_areg (regs, 7) -= 4;
+	x_put_word (m68k_areg (regs, 7), oldpc >> 16);
+	x_put_word (m68k_areg (regs, 7) + 2, oldpc);
+	m68k_setpci (dest);
+}
+
+#endif
+
+STATIC_INLINE uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
+{
+	int reg = (dp >> 12) & 15;
+	uae_s32 regd = regs.regs[reg];
+	if ((dp & 0x800) == 0)
+		regd = (uae_s32)(uae_s16)regd;
+	return base + (uae_s8)dp + regd;
+}
diff --git a/src/cpu/cpudefs.c b/src/cpu/cpudefs.c
new file mode 100644
index 0000000..f15086d
--- /dev/null
+++ b/src/cpu/cpudefs.c
@@ -0,0 +1,465 @@
+#include "sysconfig.h"
+#include "sysdeps.h"
+#include "readcpu.h"
+struct instr_def defs68k[] = {
+/* ORSR.B  */
+{0x003C, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,0,{{0,0},{0,0},{0,0},{0,0},{0,0}},0x10,_T("ORSR.B  #1"), 0, 0, 0, 0},
+/* ORSR.W  */
+{0x007C, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,2,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("ORSR.W  #1"), 0, 0, 0, 0},
+/* CHK2.z  */
+{0x00C0, 8,{17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0},0xF9C0,2,5,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x11,_T("CHK2.z  #1,s[!Dreg,Areg,Aipi,Apdi,Immd]"), 0, 0, 0, 0},
+/* OR.z  */
+{0x0000, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("OR.z    #z,d[Dreg]"), 2, 0, 2, 3},
+/* OR.z  */
+{0x0000, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("OR.z    #z,d[!Areg,Dreg]"), 0, 1, 3, 3},
+/* ANDSR.B  */
+{0x023C, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,0,{{0,0},{0,0},{0,0},{0,0},{0,0}},0x10,_T("ANDSR.B #1"), 0, 0, 0, 0},
+/* ANDSR.W  */
+{0x027C, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,2,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("ANDSR.W #1"), 0, 0, 0, 0},
+/* AND.z  */
+{0x0200, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("AND.z   #z,d[Dreg]"), 2, 0, 2, 3},
+/* AND.z  */
+{0x0200, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("AND.z   #z,d[!Areg,Dreg]"), 0, 1, 3, 3},
+/* SUB.z  */
+{0x0400, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("SUB.z   #z,d[Dreg]"), 2, 0, 2, 3},
+/* SUB.z  */
+{0x0400, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("SUB.z   #z,d[!Areg,Dreg]"), 0, 1, 3, 3},
+/* ADD.z  */
+{0x0600, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("ADD.z   #z,d[Dreg]"), 2, 0, 2, 3},
+/* ADD.z  */
+{0x0600, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("ADD.z   #z,d[!Areg,Dreg]"), 0, 1, 3, 3},
+/* CALLM  */
+{0x06C0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,3,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("CALLM   s[!Dreg,Areg,Aipi,Apdi,Immd]"), 0, 0, 0, 0},
+/* RTM  */
+{0x06C0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,3,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("RTM     s[Dreg,Areg]"), 0, 0, 0, 0},
+/* BTST  */
+{0x0800, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x11,_T("BTST    #1,s[Dreg]"), 4, 0, 4, 0},
+/* BTST  */
+{0x0800, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x11,_T("BTST    #1,s[!Areg,Dreg,Immd]"), 0, 0, 4, 3},
+/* BCHG  */
+{0x0840, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x13,_T("BCHG    #1,s[Dreg]"), 6, 0, 6, 0},
+/* BCHG  */
+{0x0840, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x13,_T("BCHG    #1,s[!Areg,Dreg,Immd,PC8r,PC16]"), 0, 0, 6, 3},
+/* BCLR  */
+{0x0880, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x13,_T("BCLR    #1,s[Dreg]"), 6, 0, 6, 0},
+/* BCLR  */
+{0x0880, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x13,_T("BCLR    #1,s[!Areg,Dreg,Immd,PC8r,PC16]"), 0, 0, 6, 3},
+/* BSET  */
+{0x08C0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x13,_T("BSET    #1,s[Dreg]"), 6, 0, 6, 0},
+/* BSET  */
+{0x08C0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x13,_T("BSET    #1,s[!Areg,Dreg,Immd,PC8r,PC16]"), 0, 0, 6, 3},
+/* EORSR.B  */
+{0x0A3C, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,0,{{0,0},{0,0},{0,0},{0,0},{0,0}},0x10,_T("EORSR.B #1"), 0, 0, 0, 0},
+/* EORSR.W  */
+{0x0A7C, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,2,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("EORSR.W #1"), 0, 0, 0, 0},
+/* EOR.z  */
+{0x0A00, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("EOR.z   #z,d[Dreg]"), 2, 0, 2, 3},
+/* EOR.z  */
+{0x0A00, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("EOR.z   #z,d[!Areg,Dreg]"), 0, 1, 3, 3},
+/* CMP.z  */
+{0x0C00, 8,{17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,1},{1,0},{1,0},{1,0},{1,0}},0x11,_T("CMP.z   #z,s[Dreg]"), 2, 0, 2, 3},
+/* CMP.z  */
+{0x0C00, 8,{17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,1},{1,0},{1,0},{1,0},{1,0}},0x11,_T("CMP.z   #z,s[!Areg,Dreg,Immd,PC8r,PC16]"), 0, 0, 2, 3},
+/* CMP.z  */
+{0x0C00, 8,{17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,2,0,0,{{1,1},{1,0},{1,0},{1,0},{1,0}},0x11,_T("CMP.z   #z,s[PC8r,PC16]"), 0, 0, 2, 3},
+/* CAS.B  */
+{0x0AC0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x13,_T("CAS.B   #1,s[!Dreg,Areg,Immd,PC8r,PC16]"), 0, 0, 0, 0},
+/* CAS.W  */
+{0x0CC0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x13,_T("CAS.W   #1,s[!Dreg,Areg,Immd,PC8r,PC16]"), 0, 0, 0, 0},
+/* CAS2.W  */
+{0x0CFC, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,2,5,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("CAS2.W  #2"), 0, 0, 0, 0},
+/* MOVES.z  */
+{0x0E00, 8,{17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,2,0,2,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x13,_T("MOVES.z #1,s[!Dreg,Areg,Immd,PC8r,PC16]"), 0, 0, 0, 0},
+/* CAS.L  */
+{0x0EC0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x13,_T("CAS.L   #1,s[!Dreg,Areg,Immd,PC8r,PC16]"), 0, 0, 0, 0},
+/* CAS2.L  */
+{0x0EFC, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,2,5,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("CAS2.L  #2"), 0, 0, 0, 0},
+/* MVPMR.W  */
+{0x0100, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,5,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x12,_T("MVPMR.W d[Areg-Ad16],Dr"), 0, 0, 0, 0},
+/* MVPMR.L  */
+{0x0140, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,5,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x12,_T("MVPMR.L d[Areg-Ad16],Dr"), 0, 0, 0, 0},
+/* MVPRM.W  */
+{0x0180, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,5,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x12,_T("MVPRM.W Dr,d[Areg-Ad16]"), 0, 0, 0, 0},
+/* MVPRM.L  */
+{0x01C0, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,5,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x12,_T("MVPRM.L Dr,d[Areg-Ad16]"), 0, 0, 0, 0},
+/* BTST  */
+{0x0100, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x11,_T("BTST    Dr,s[Dreg]"), 4, 0, 4, 0},
+/* BTST  */
+{0x0100, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x11,_T("BTST    Dr,s[!Areg,Dreg]"), 0, 0, 4, 1},
+/* BCHG  */
+{0x0140, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x13,_T("BCHG    Dr,s[Dreg]"), 6, 0, 6, 0},
+/* BCHG  */
+{0x0140, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x13,_T("BCHG    Dr,s[!Areg,Dreg,Immd,PC8r,PC16]"), 0, 0, 6, 1},
+/* BCLR  */
+{0x0180, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x13,_T("BCLR    Dr,s[Dreg]"), 6, 0, 6, 0},
+/* BCLR  */
+{0x0180, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x13,_T("BCLR    Dr,s[!Areg,Dreg,Immd,PC8r,PC16]"), 0, 0, 6, 1},
+/* BSET  */
+{0x01C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x13,_T("BSET    Dr,s[Dreg]"), 6, 0, 6, 0},
+/* BSET  */
+{0x01C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,0},{1,1},{1,1}},0x13,_T("BSET    Dr,s[!Areg,Dreg,Immd,PC8r,PC16]"), 0, 0, 6, 1},
+/* MOVE.B  */
+{0x1000,12,{14,14,14,13,13,13,11,11,11,12,12,12, 0, 0, 0, 0},0xF000,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x12,_T("MOVE.B  s,d[!Areg]"), 0, 0, 0, 0},
+/* MOVEA.W  */
+{0x3000,12,{14,14,14,13,13,13,11,11,11,12,12,12, 0, 0, 0, 0},0xF000,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x12,_T("MOVEA.W s,d[Areg]"), 0, 0, 0, 0},
+/* MOVE.W  */
+{0x3000,12,{14,14,14,13,13,13,11,11,11,12,12,12, 0, 0, 0, 0},0xF000,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x12,_T("MOVE.W  s,d[!Areg]"), 0, 0, 0, 0},
+/* MOVEA.L  */
+{0x2000,12,{14,14,14,13,13,13,11,11,11,12,12,12, 0, 0, 0, 0},0xF000,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x12,_T("MOVEA.L s,d[Areg]"), 0, 0, 0, 0},
+/* MOVE.L  */
+{0x2000,12,{14,14,14,13,13,13,11,11,11,12,12,12, 0, 0, 0, 0},0xF000,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x12,_T("MOVE.L  s,d[!Areg]"), 0, 0, 0, 0},
+/* NEGX.z  */
+{0x4000, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{0,0},{1,4},{0,0},{1,4},{1,0}},0x30,_T("NEGX.z  d[Dreg]"), 2, 0, 2, 0},
+/* NEGX.z  */
+{0x4000, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{0,0},{1,4},{0,0},{1,4},{1,0}},0x30,_T("NEGX.z  d[!Areg,Dreg]"), 0, 1, 3, 1},
+/* MVSR2.W  */
+{0x40C0, 6,{13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,1,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("MVSR2.W d[Dreg]"), 2, 0, 4, 0},
+/* MVSR2.W  */
+{0x40C0, 6,{13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,1,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("MVSR2.W d[!Areg,Dreg]"), 2, 0, 4, 2},
+/* CLR.z  */
+{0x4200, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,1},{1,2},{1,3},{1,2},{1,2}},0x20,_T("CLR.z   d[Dreg]"), 2, 0, 2, 0},
+/* CLR.z  */
+{0x4200, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,1},{1,2},{1,3},{1,2},{1,2}},0x20,_T("CLR.z   d[!Areg,Dreg]"), 0, 1, 3, 2},
+/* MVSR2.B  */
+{0x42C0, 6,{13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,1,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("MVSR2.B d[Dreg]"), 2, 0, 4, 0},
+/* MVSR2.B  */
+{0x42C0, 6,{13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,1,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("MVSR2.B d[!Areg,Dreg]"), 2, 0, 4, 2},
+/* NEG.z  */
+{0x4400, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x30,_T("NEG.z   d[Dreg]"), 2, 0, 2, 0},
+/* NEG.z  */
+{0x4400, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x30,_T("NEG.z   d[!Areg,Dreg]"), 0, 1, 3, 1},
+/* MV2SR.B  */
+{0x44C0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x10,_T("MV2SR.B s[Dreg]"), 4, 0, 4, 0},
+/* MV2SR.B  */
+{0x44C0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x10,_T("MV2SR.B s[!Areg,Dreg]"), 0, 0, 4, 1},
+/* NOT.z  */
+{0x4600, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x30,_T("NOT.z   d[Dreg]"), 2, 0, 2, 0},
+/* NOT.z  */
+{0x4600, 8,{17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x30,_T("NOT.z   d[!Areg,Dreg]"), 0, 1, 3, 1},
+/* MV2SR.W  */
+{0x46C0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,2,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("MV2SR.W s[!Areg]"), 0, 0, 8, 1},
+/* LINK.L  */
+{0x4808, 3,{15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,2,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x31,_T("LINK.L  Ar,#2"), 2, 0, 6, 0},
+/* NBCD.B  */
+{0x4800, 6,{13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{0,0},{1,5},{0,0},{1,5},{1,0}},0x30,_T("NBCD.B  d[!Areg]"), 0, 0, 6, 0},
+/* BKPT  */
+{0x4848, 3,{ 9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("BKPT    #k"), 0, 0, 0, 0},
+/* SWAP.W  */
+{0x4840, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x30,_T("SWAP.W  s[Dreg]"), 4, 0, 4, 0},
+/* PEA.L  */
+{0x4840, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x00,_T("PEA.L   s[!Dreg,Areg,Aipi,Apdi,Immd]"), 0, 2, 4, 2},
+/* EXT.W  */
+{0x4880, 6,{13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x30,_T("EXT.W   d[Dreg]"), 4, 0, 4, 0},
+/* MVMLE.W  */
+{0x4880, 6,{13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x02,_T("MVMLE.W #1,d[!Dreg,Areg,Aipi]"), 0, 0, 0, 0},
+/* EXT.L  */
+{0x48C0, 6,{13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x30,_T("EXT.L   d[Dreg]"), 4, 0, 4, 0},
+/* MVMLE.L  */
+{0x48C0, 6,{13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x02,_T("MVMLE.L #1,d[!Dreg,Areg,Aipi]"), 0, 0, 0, 0},
+/* EXT.B  */
+{0x49C0, 6,{13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x30,_T("EXT.B   d[Dreg]"), 4, 0, 4, 0},
+/* TST.z  */
+{0x4A00, 8,{17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x10,_T("TST.z   s[Dreg]"), 0, 0, 2, 0},
+/* TST.z  */
+{0x4A00, 8,{17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x10,_T("TST.z   s[!Areg,Dreg,PC16,PC8r,Immd]"), 0, 0, 2, 1},
+/* TST.z  */
+{0x4A00, 8,{17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,2,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x10,_T("TST.z   s[Areg,PC16,PC8r,Immd]"), 0, 0, 2, 1},
+/* TAS.B  */
+{0x4AC0, 6,{13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x30,_T("TAS.B   d[Dreg]"), 0, 0, 2, 0},
+/* TAS.B  */
+{0x4AC0, 6,{13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x30,_T("TAS.B   d[!Areg,Dreg]"), 0, 0, 2, 1},
+/* ILLEGAL  */
+{0x4AFC, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x00,_T("ILLEGAL"), 0, 0, 0, 0},
+/* MULL.L  */
+{0x4C00, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{1,1},{1,0},{1,0},{1,0},{1,0}},0x13,_T("MULL.L  #1,s[!Areg]"), 2, 0,30, 3},
+/* DIVL.L  */
+{0x4C40, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x13,_T("DIVL.L  #1,s[!Areg]"), 0, 0,50, 3},
+/* MVMEL.W  */
+{0x4C80, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x01,_T("MVMEL.W #1,s[!Dreg,Areg,Apdi,Immd]"), 0, 0, 0, 0},
+/* MVMEL.L  */
+{0x4CC0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x01,_T("MVMEL.L #1,s[!Dreg,Areg,Apdi,Immd]"), 0, 0, 0, 0},
+/* TRAP  */
+{0x4E40, 4,{ 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF0,0,0,0,{{0,1},{0,1},{0,1},{0,1},{0,1}},0x10,_T("TRAP    #J"), 0, 0, 0, 0},
+/* LINK.W  */
+{0x4E50, 3,{15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x31,_T("LINK.W  Ar,#1"), 0, 0, 4, 0},
+/* UNLK.L  */
+{0x4E58, 3,{15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x30,_T("UNLK.L  Ar"), 0, 0, 5, 0},
+/* MVR2USP.L  */
+{0x4E60, 3,{15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,0,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x10,_T("MVR2USP.L Ar"), 4, 0, 4, 0},
+/* MVUSP2R.L  */
+{0x4E68, 3,{15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,0,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x20,_T("MVUSP2R.L Ar"), 4, 0, 4, 0},
+/* RESET  */
+{0x4E70, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x00,_T("RESET"), 0, 0,518, 0},
+/* NOP  */
+{0x4E71, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x00,_T("NOP"), 0, 0, 2, 0},
+/* STOP  */
+{0x4E72, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,2,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x10,_T("STOP    #1"), 0, 0, 8, 0},
+/* RTE  */
+{0x4E73, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,2,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x00,_T("RTE"), 1, 9,18, 0},
+/* RTD  */
+{0x4E74, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,1,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("RTD     #1"), 2, 0,10, 0},
+/* RTS  */
+{0x4E75, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x00,_T("RTS"), 1, 0, 9, 0},
+/* TRAPV  */
+{0x4E76, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,0,{{0,1},{0,1},{0,1},{0,1},{0,1}},0x00,_T("TRAPV"), 0, 0, 0, 0},
+/* RTR  */
+{0x4E77, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x00,_T("RTR"), 1, 0,12, 0},
+/* MOVEC2  */
+{0x4E7A, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,1,0,2,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("MOVEC2  #1"), 6, 0, 6, 0},
+/* MOVE2C  */
+{0x4E7B, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,1,0,2,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("MOVE2C  #1"), 6, 0, 6, 0},
+/* JSR.L  */
+{0x4E80, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{4,6},{4,6},{4,6},{4,6},{4,6}},0x80,_T("JSR.L   s[!Dreg,Areg,Aipi,Apdi,Immd]"), 0, 0, 4, 5},
+/* CHK.L  */
+{0x4100, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x11,_T("CHK.L   s[!Areg],Dr"), 0, 0, 0, 0},
+/* CHK.W  */
+{0x4180, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x11,_T("CHK.W   s[!Areg],Dr"), 0, 0, 0, 0},
+/* JMP.L  */
+{0x4EC0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,0,0,0,{{4,6},{4,6},{4,6},{4,6},{4,6}},0x80,_T("JMP.L   s[!Dreg,Areg,Aipi,Apdi,Immd]"), 4, 0, 4, 5},
+/* LEA.L  */
+{0x41C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x02,_T("LEA.L   s[!Dreg,Areg,Aipi,Apdi,Immd],Ar"), 2, 0, 2, 2},
+/* ADDA.W  */
+{0x5040, 9,{ 7, 7, 7,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x13,_T("ADDA.W  #j,d[Areg]"), 2, 0, 2, 0},
+/* ADDA.L  */
+{0x5080, 9,{ 7, 7, 7,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x13,_T("ADDA.L  #j,d[Areg]"), 2, 0, 2, 0},
+/* ADD.z  */
+{0x5000,11,{ 7, 7, 7,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("ADD.z   #j,d[Dreg]"), 2, 0, 2, 0},
+/* ADD.z  */
+{0x5000,11,{ 7, 7, 7,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("ADD.z   #j,d[!Areg,Dreg]"), 0, 1, 3, 1},
+/* SUBA.W  */
+{0x5140, 9,{ 7, 7, 7,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x13,_T("SUBA.W  #j,d[Areg]"), 2, 0, 2, 0},
+/* SUBA.L  */
+{0x5180, 9,{ 7, 7, 7,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x13,_T("SUBA.L  #j,d[Areg]"), 2, 0, 2, 0},
+/* SUB.z  */
+{0x5100,11,{ 7, 7, 7,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("SUB.z   #j,d[Dreg]"), 2, 0, 2, 0},
+/* SUB.z  */
+{0x5100,11,{ 7, 7, 7,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("SUB.z   #j,d[!Areg,Dreg]"), 0, 1, 3, 1},
+/* DBcc.W  */
+{0x50C8, 7,{ 2, 2, 2, 2,15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xF0F8,0,0,0,{{1,1},{2,1},{2,1},{2,1},{2,1}},0x31,_T("DBcc.W  Dr,#1"),-1, 0, 0, 0},
+/* Scc.B  */
+{0x50C0,10,{ 2, 2, 2, 2,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0},0xF0C0,0,0,0,{{1,1},{2,1},{2,1},{2,1},{2,1}},0x20,_T("Scc.B   d[Dreg]"), 0, 0, 2, 0},
+/* Scc.B  */
+{0x50C0,10,{ 2, 2, 2, 2,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0},0xF0C0,0,0,0,{{1,1},{2,1},{2,1},{2,1},{2,1}},0x20,_T("Scc.B   d[!Areg,Dreg]"), 0, 0, 2, 2},
+/* TRAPcc  */
+{0x50FA, 4,{ 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xF0FF,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("TRAPcc  #1"), 0, 0, 0, 0},
+/* TRAPcc  */
+{0x50FB, 4,{ 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xF0FF,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("TRAPcc  #2"), 0, 0, 0, 0},
+/* TRAPcc  */
+{0x50FC, 4,{ 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xF0FF,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x00,_T("TRAPcc"), 0, 0, 0, 0},
+/* BSR.W  */
+{0x6100, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,0,{{4,6},{4,6},{4,6},{4,6},{4,6}},0x40,_T("BSR.W   #1"), 2, 0, 6, 0},
+/* BSR.B  */
+{0x6100, 8,{ 6, 6, 6, 6, 6, 6, 6, 6, 0, 0, 0, 0, 0, 0, 0, 0},0xFF00,0,0,0,{{4,6},{4,6},{4,6},{4,6},{4,6}},0x40,_T("BSR.B   #i"), 2, 0, 6, 0},
+/* BSR.L  */
+{0x61FF, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,0,0,0,{{4,6},{4,6},{4,6},{4,6},{4,6}},0x40,_T("BSR.L   #2"), 2, 0, 6, 0},
+/* Bcc.W  */
+{0x6000, 4,{ 3, 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xF0FF,0,0,0,{{1,1},{2,1},{2,1},{2,1},{2,1}},0x40,_T("Bcc.W   #1"),-1, 0, 0, 0},
+/* Bcc.B  */
+{0x6000,12,{ 3, 3, 3, 3, 6, 6, 6, 6, 6, 6, 6, 6, 0, 0, 0, 0},0xF000,0,0,0,{{1,1},{2,1},{2,1},{2,1},{2,1}},0x40,_T("Bcc.B   #i"),-1, 0, 0, 0},
+/* Bcc.L  */
+{0x60FF, 4,{ 3, 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xF0FF,0,0,0,{{1,1},{2,1},{2,1},{2,1},{2,1}},0x40,_T("Bcc.L   #2"),-1, 0, 0, 0},
+/* MOVE.L  */
+{0x7000,11,{15,15,15, 5, 5, 5, 5, 5, 5, 5, 5, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x12,_T("MOVE.L  #i,Dr"), 0, 0, 0, 0},
+/* OR.z  */
+{0x8000,11,{15,15,15,17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("OR.z    s[Dreg],Dr"), 2, 0, 2, 0},
+/* OR.z  */
+{0x8000,11,{15,15,15,17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("OR.z    s[!Areg,Dreg],Dr"), 0, 0, 2, 1},
+/* DIVU.W  */
+{0x80C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x13,_T("DIVU.W  s[Dreg],Dr"), 2, 0,54, 0},
+/* DIVU.W  */
+{0x80C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x13,_T("DIVU.W  s[!Areg,Dreg],Dr"), 0, 0,54, 1},
+/* SBCD.B  */
+{0x8100, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{0,0},{1,4},{0,0},{1,4},{1,0}},0x13,_T("SBCD.B  d[Dreg],Dr"), 0, 0, 4, 0},
+/* SBCD.B  */
+{0x8100, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{0,0},{1,4},{0,0},{1,4},{1,0}},0x13,_T("SBCD.B  d[Areg-Apdi],Arp"), 2, 1,13, 0},
+/* OR.z  */
+{0x8100,11,{15,15,15,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("OR.z    Dr,d[!Areg,Dreg]"), 0, 1, 3, 1},
+/* PACK  */
+{0x8140, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x12,_T("PACK    d[Dreg],Dr"), 6, 0, 6, 0},
+/* PACK  */
+{0x8140, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x12,_T("PACK    d[Areg-Apdi],Arp"), 2, 1,11, 0},
+/* UNPK  */
+{0x8180, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x12,_T("UNPK    d[Dreg],Dr"), 8, 0, 8, 0},
+/* UNPK  */
+{0x8180, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x12,_T("UNPK    d[Areg-Apdi],Arp"), 2, 1,11, 0},
+/* DIVS.W  */
+{0x81C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x13,_T("DIVS.W  s[Dreg],Dr"), 2, 0,54, 0},
+/* DIVS.W  */
+{0x81C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x13,_T("DIVS.W  s[!Areg,Dreg],Dr"), 0, 0,54, 1},
+/* SUB.z  */
+{0x9000,11,{15,15,15,17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("SUB.z   s[Areg,Dreg],Dr"), 2, 0, 2, 0},
+/* SUB.z  */
+{0x9000,11,{15,15,15,17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("SUB.z   s[!Areg,Dreg],Dr"), 0, 0, 2, 1},
+/* SUBA.W  */
+{0x90C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x13,_T("SUBA.W  s[Areg,Dreg],Ar"), 4, 0, 4, 0},
+/* SUBA.W  */
+{0x90C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x13,_T("SUBA.W  s[!Areg,Dreg],Ar"), 0, 0, 4, 1},
+/* SUBX.z  */
+{0x9100,11,{15,15,15,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{0,0},{1,0},{0,0},{1,0},{1,0}},0x13,_T("SUBX.z  d[Dreg],Dr"), 2, 0, 2, 0},
+/* SUBX.z  */
+{0x9100,11,{15,15,15,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{0,0},{1,0},{0,0},{1,0},{1,0}},0x13,_T("SUBX.z  d[Areg-Apdi],Arp"), 2, 1, 9, 0},
+/* SUB.z  */
+{0x9100,11,{15,15,15,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("SUB.z   Dr,d[!Areg,Dreg]"), 0, 1, 3, 1},
+/* SUBA.L  */
+{0x91C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x13,_T("SUBA.L  s[Areg,Dreg],Ar"), 2, 0, 2, 0},
+/* SUBA.L  */
+{0x91C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x13,_T("SUBA.L  s[!Areg,Dreg],Ar"), 0, 0, 2, 1},
+/* CMP.z  */
+{0xB000,11,{15,15,15,17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,1},{1,0},{1,0},{1,0},{1,0}},0x11,_T("CMP.z   s[Areg,Dreg],Dr"), 2, 0, 2, 0},
+/* CMP.z  */
+{0xB000,11,{15,15,15,17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,1},{1,0},{1,0},{1,0},{1,0}},0x11,_T("CMP.z   s[!Areg,Dreg],Dr"), 0, 0, 2, 1},
+/* CMPA.W  */
+{0xB0C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,0},{1,0},{1,0},{1,0}},0x11,_T("CMPA.W  s[Areg,Dreg],Ar"), 4, 0, 4, 0},
+/* CMPA.W  */
+{0xB0C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,0},{1,0},{1,0},{1,0}},0x11,_T("CMPA.W  s[!Areg,Dreg],Ar"), 0, 0, 4, 1},
+/* CMPA.L  */
+{0xB1C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,0},{1,0},{1,0},{1,0}},0x11,_T("CMPA.L  s[Areg,Dreg],Ar"), 4, 0, 4, 0},
+/* CMPA.L  */
+{0xB1C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,0},{1,0},{1,0},{1,0}},0x11,_T("CMPA.L  s[!Areg,Dreg],Ar"), 0, 0, 4, 1},
+/* CMPM.z  */
+{0xB100,11,{15,15,15,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,1},{1,0},{1,0},{1,0},{1,0}},0x11,_T("CMPM.z  d[Areg-Aipi],ArP"), 0, 0, 8, 0},
+/* EOR.z  */
+{0xB100,11,{15,15,15,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("EOR.z   Dr,d[Dreg]"), 2, 0, 2, 0},
+/* EOR.z  */
+{0xB100,11,{15,15,15,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("EOR.z   Dr,d[!Areg,Dreg]"), 0, 1, 3, 1},
+/* AND.z  */
+{0xC000,11,{15,15,15,17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("AND.z   s[Dreg],Dr"), 2, 0, 2, 1},
+/* AND.z  */
+{0xC000,11,{15,15,15,17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("AND.z   s[!Areg,Dreg],Dr"), 0, 1, 3, 1},
+/* MULU.W  */
+{0xC0C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("MULU.W  s[!Areg],Dr"), 2, 0,25, 1},
+/* ABCD.B  */
+{0xC100, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{0,0},{1,4},{0,0},{1,4},{1,0}},0x13,_T("ABCD.B  d[Dreg],Dr"), 0, 0, 4, 0},
+/* ABCD.B  */
+{0xC100, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{0,0},{1,4},{0,0},{1,4},{1,0}},0x13,_T("ABCD.B  d[Areg-Apdi],Arp"), 2, 1,13, 0},
+/* AND.z  */
+{0xC100,11,{15,15,15,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("AND.z   Dr,d[!Areg,Dreg]"), 0, 1, 3, 1},
+/* EXG.L  */
+{0xC140, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x33,_T("EXG.L   Dr,d[Dreg]"), 4, 0, 4, 0},
+/* EXG.L  */
+{0xC140, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x33,_T("EXG.L   Ar,d[Areg]"), 4, 0, 4, 0},
+/* EXG.L  */
+{0xC180, 9,{15,15,15,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x33,_T("EXG.L   Dr,d[Areg]"), 4, 0, 4, 0},
+/* MULS.W  */
+{0xC1C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,2}},0x13,_T("MULS.W  s[!Areg],Dr"), 2, 0,25, 1},
+/* ADD.z  */
+{0xD000,11,{15,15,15,17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("ADD.z   s[Areg,Dreg],Dr"), 2, 0, 2, 0},
+/* ADD.z  */
+{0xD000,11,{15,15,15,17,17,11,11,11,12,12,12, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("ADD.z   s[!Areg,Dreg],Dr"), 0, 0, 2, 1},
+/* ADDA.W  */
+{0xD0C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x13,_T("ADDA.W  s[Areg,Dreg],Ar"), 0, 0, 4, 0},
+/* ADDA.W  */
+{0xD0C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x13,_T("ADDA.W  s[!Areg,Dreg],Ar"), 4, 0, 4, 1},
+/* ADDX.z  */
+{0xD100,11,{15,15,15,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{0,0},{1,0},{0,0},{1,0},{1,0}},0x13,_T("ADDX.z  d[Dreg],Dr"), 2, 0, 2, 0},
+/* ADDX.z  */
+{0xD100,11,{15,15,15,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{0,0},{1,0},{0,0},{1,0},{1,0}},0x13,_T("ADDX.z  d[Areg-Apdi],Arp"), 2, 1, 9, 0},
+/* ADD.z  */
+{0xD100,11,{15,15,15,17,17,13,13,13,14,14,14, 0, 0, 0, 0, 0},0xF100,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("ADD.z   Dr,d[!Areg,Dreg]"), 0, 1, 3, 1},
+/* ADDA.L  */
+{0xD1C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x13,_T("ADDA.L  s[Areg,Dreg],Ar"), 2, 0, 2, 0},
+/* ADDA.L  */
+{0xD1C0, 9,{15,15,15,11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0},0xF1C0,0,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x13,_T("ADDA.L  s[!Areg,Dreg],Ar"), 0, 0, 2, 1},
+/* ASf.z  */
+{0xE000, 9,{ 7, 7, 7, 4,17,17,16,16,16, 0, 0, 0, 0, 0, 0, 0},0xF038,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("ASf.z   #j,DR"), 2, 0, 6, 0},
+/* LSf.z  */
+{0xE008, 9,{ 7, 7, 7, 4,17,17,16,16,16, 0, 0, 0, 0, 0, 0, 0},0xF038,0,0,0,{{1,0},{1,0},{1,0},{1,2},{1,0}},0x13,_T("LSf.z   #j,DR"), 4, 0, 4, 0},
+/* ROXf.z  */
+{0xE010, 9,{ 7, 7, 7, 4,17,17,16,16,16, 0, 0, 0, 0, 0, 0, 0},0xF038,0,0,0,{{0,0},{1,0},{1,0},{1,2},{1,0}},0x13,_T("ROXf.z  #j,DR"),10, 0,12, 0},
+/* ROf.z  */
+{0xE018, 9,{ 7, 7, 7, 4,17,17,16,16,16, 0, 0, 0, 0, 0, 0, 0},0xF038,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,0}},0x13,_T("ROf.z   #j,DR"), 4, 0, 6, 0},
+/* ASf.z  */
+{0xE020, 9,{15,15,15, 4,17,17,16,16,16, 0, 0, 0, 0, 0, 0, 0},0xF038,0,0,0,{{0,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("ASf.z   Dr,DR"), 4, 0, 6, 0},
+/* LSf.z  */
+{0xE028, 9,{15,15,15, 4,17,17,16,16,16, 0, 0, 0, 0, 0, 0, 0},0xF038,0,0,0,{{0,0},{1,0},{1,0},{1,2},{1,0}},0x13,_T("LSf.z   Dr,DR"), 6, 0, 6, 0},
+/* ROXf.z  */
+{0xE030, 9,{15,15,15, 4,17,17,16,16,16, 0, 0, 0, 0, 0, 0, 0},0xF038,0,0,0,{{0,0},{1,0},{1,0},{1,2},{1,0}},0x13,_T("ROXf.z  Dr,DR"),10, 0,12, 0},
+/* ROf.z  */
+{0xE038, 9,{15,15,15, 4,17,17,16,16,16, 0, 0, 0, 0, 0, 0, 0},0xF038,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,0}},0x13,_T("ROf.z   Dr,DR"), 6, 0, 8, 0},
+/* ASfW.W  */
+{0xE0C0, 7,{ 4,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFEC0,0,0,0,{{1,0},{1,0},{1,0},{1,0},{1,0}},0x13,_T("ASfW.W  d[!Dreg,Areg]"), 0, 0, 4, 1},
+/* LSfW.W  */
+{0xE2C0, 7,{ 4,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFEC0,0,0,0,{{1,0},{1,0},{1,0},{1,2},{1,0}},0x13,_T("LSfW.W  d[!Dreg,Areg]"), 0, 0, 4, 1},
+/* ROXfW.W  */
+{0xE4C0, 7,{ 4,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFEC0,0,0,0,{{0,0},{1,0},{1,0},{1,2},{1,0}},0x13,_T("ROXfW.W d[!Dreg,Areg]"), 0, 0, 4, 1},
+/* ROfW.W  */
+{0xE6C0, 7,{ 4,13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFEC0,0,0,0,{{1,1},{1,0},{1,0},{1,2},{1,0}},0x13,_T("ROfW.W  d[!Dreg,Areg]"), 0, 0, 6, 1},
+/* BFTST  */
+{0xE8C0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x11,_T("BFTST   #1,s[!Areg,Apdi,Aipi,Immd]"), 0, 0, 0, 0},
+/* BFEXTU  */
+{0xE9C0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x11,_T("BFEXTU  #1,s[!Areg,Apdi,Aipi,Immd]"), 0, 0, 0, 0},
+/* BFCHG  */
+{0xEAC0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x13,_T("BFCHG   #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]"), 0, 0, 0, 0},
+/* BFEXTS  */
+{0xEBC0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x11,_T("BFEXTS  #1,s[!Areg,Apdi,Aipi,Immd]"), 0, 0, 0, 0},
+/* BFCLR  */
+{0xECC0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x13,_T("BFCLR   #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]"), 0, 0, 0, 0},
+/* BFFFO  */
+{0xEDC0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x11,_T("BFFFO   #1,s[!Areg,Apdi,Aipi,Immd]"), 0, 0, 0, 0},
+/* BFSET  */
+{0xEEC0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x13,_T("BFSET   #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]"), 0, 0, 0, 0},
+/* BFINS  */
+{0xEFC0, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x13,_T("BFINS   #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]"), 0, 0, 0, 0},
+/* FPP  */
+{0xF200, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x11,_T("FPP      #1,s"), 0, 0, 0, 0},
+/* FDBcc  */
+{0xF240, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x11,_T("FDBcc    #1,s[Areg-Dreg]"), 0, 0, 0, 0},
+/* FScc  */
+{0xF240, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x11,_T("FScc     #1,s[!Areg,Immd,PC8r,PC16]"), 0, 0, 0, 0},
+/* FTRAPcc  */
+{0xF27A, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("FTRAPcc  #1"), 0, 0, 0, 0},
+/* FTRAPcc  */
+{0xF27B, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("FTRAPcc  #2"), 0, 0, 0, 0},
+/* FTRAPcc  */
+{0xF27C, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x00,_T("FTRAPcc"), 0, 0, 0, 0},
+/* FBcc  */
+{0xF280, 6,{10,10,10,10,10,10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x11,_T("FBcc     #K,#1"), 0, 0, 0, 0},
+/* FBcc  */
+{0xF2C0, 6,{10,10,10,10,10,10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,0,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x11,_T("FBcc     #K,#2"), 0, 0, 0, 0},
+/* FSAVE  */
+{0xF300, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,2,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x20,_T("FSAVE    s[!Dreg,Areg,Aipi,Immd,PC8r,PC16]"), 0, 0, 0, 0},
+/* FRESTORE  */
+{0xF340, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,2,0,2,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("FRESTORE s[!Dreg,Areg,Apdi,Immd]"), 0, 0, 0, 0},
+/* MMUOP030  */
+{0xF000, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,3,4,2,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x11,_T("MMUOP030 s[Dreg,Areg,Apdi,Aipi,Aind,Ad16,Ad8r,absl,absw],#1"), 0, 0, 0, 0},
+/* CINVL  */
+{0xF408, 5,{18,18,15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFF38,4,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x02,_T("CINVL    #p,Ar"), 0, 0, 0, 0},
+/* CINVP  */
+{0xF410, 5,{18,18,15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFF38,4,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x02,_T("CINVP    #p,Ar"), 0, 0, 0, 0},
+/* CINVA  */
+{0xF418, 5,{18,18,15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFF38,4,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x00,_T("CINVA    #p"), 0, 0, 0, 0},
+/* CPUSHL  */
+{0xF428, 5,{18,18,15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFF38,4,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x02,_T("CPUSHL   #p,Ar"), 0, 0, 0, 0},
+/* CPUSHP  */
+{0xF430, 5,{18,18,15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFF38,4,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x02,_T("CPUSHP   #p,Ar"), 0, 0, 0, 0},
+/* CPUSHA  */
+{0xF438, 5,{18,18,15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFF38,4,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x00,_T("CPUSHA   #p"), 0, 0, 0, 0},
+/* PFLUSHN  */
+{0xF500, 3,{15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,4,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x00,_T("PFLUSHN  Ara"), 0, 0, 0, 0},
+/* PFLUSH  */
+{0xF508, 3,{15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,4,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x00,_T("PFLUSH   Ara"), 0, 0, 0, 0},
+/* PFLUSHAN  */
+{0xF510, 3,{15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,4,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x00,_T("PFLUSHAN Ara"), 0, 0, 0, 0},
+/* PFLUSHA  */
+{0xF518, 3,{15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,4,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x00,_T("PFLUSHA  Ara"), 0, 0, 0, 0},
+/* PTESTW  */
+{0xF548, 3,{15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,4,5,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x00,_T("PTESTW   Ara"), 0, 0, 0, 0},
+/* PTESTR  */
+{0xF568, 3,{15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,4,5,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x00,_T("PTESTR   Ara"), 0, 0, 0, 0},
+/* MOVE16  */
+{0xF620, 3,{15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,4,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x12,_T("MOVE16   ArP,AxP"), 0, 0, 0, 0},
+/* MOVE16  */
+{0xF600, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,4,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x12,_T("MOVE16   s[Dreg-Aipi],L"), 0, 0, 0, 0},
+/* MOVE16  */
+{0xF600, 6,{13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,4,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x12,_T("MOVE16   L,d[Areg-Aipi]"), 0, 0, 0, 0},
+/* MOVE16  */
+{0xF600, 6,{11,11,11,12,12,12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,4,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x12,_T("MOVE16   s[Aind],L"), 0, 0, 0, 0},
+/* MOVE16  */
+{0xF600, 6,{13,13,13,14,14,14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFC0,4,0,0,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x12,_T("MOVE16   L,d[Aipi-Aind]"), 0, 0, 0, 0},
+/* LPSTOP  */
+{0xF800, 0,{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFFF,5,0,2,{{3,5},{3,5},{3,5},{3,5},{3,5}},0x10,_T("LPSTOP   #1"), 0, 0, 0, 0},
+/* PLPAW  */
+{0xF588, 3,{15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,5,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x00,_T("PLPAW    Ara"), 0, 0, 0, 0},
+/* PLPAR  */
+{0xF5C8, 3,{15,15,15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},0xFFF8,5,0,2,{{1,1},{1,1},{1,1},{1,1},{1,1}},0x00,_T("PLPAR    Ara"), 0, 0, 0, 0}};
+int n_defs68k = 230;
diff --git a/src/cpu/cpuemu_0.c b/src/cpu/cpuemu_0.c
new file mode 100644
index 0000000..cfab9f1
--- /dev/null
+++ b/src/cpu/cpuemu_0.c
@@ -0,0 +1,46647 @@
+#include "main.h"
+#include "sysdeps.h"
+#include "hatari-glue.h"
+#include "maccess.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "cputbl.h"
+#define CPUFUNC(x) x##_ff
+#define SET_CFLG_ALWAYS(x) SET_CFLG(x)
+#define SET_NFLG_ALWAYS(x) SET_NFLG(x)
+#ifdef NOFLAGS
+#include "noflags.h"
+#endif
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0000_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_dibyte (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0010_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0018_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0020_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0028_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0030_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0038_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0039_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s8 dst = get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_003c_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_diword (2);
+	src &= 0xFF;
+	regs.sr |= src;
+	MakeFromSR();
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0040_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0050_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0058_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0060_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0068_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0070_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0078_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0079_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s16 dst = get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_007c_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_18; }
+{	MakeSR ();
+{	uae_s16 src = get_diword (2);
+	regs.sr |= src;
+	MakeFromSR();
+}}}	m68k_incpc (4);
+l_18: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0080_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0090_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0098_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (6);
+{	uae_s32 dst = get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_00b0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_00b8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (6);
+{	uae_s32 dst = get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_00b9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = get_dilong (6);
+{	uae_s32 dst = get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00d0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte (dsta); upper = (uae_s32)(uae_s8)get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_27; }
+}
+}}}	m68k_incpc (4);
+l_27: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00e8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte (dsta); upper = (uae_s32)(uae_s8)get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_28; }
+}
+}}}	m68k_incpc (6);
+l_28: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte (dsta); upper = (uae_s32)(uae_s8)get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_29; }
+}
+}}}}l_29: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte (dsta); upper = (uae_s32)(uae_s8)get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_30; }
+}
+}}}	m68k_incpc (6);
+l_30: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte (dsta); upper = (uae_s32)(uae_s8)get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_31; }
+}
+}}}	m68k_incpc (8);
+l_31: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc () + 4;
+	dsta += (uae_s32)(uae_s16)get_diword (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte (dsta); upper = (uae_s32)(uae_s8)get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_32; }
+}
+}}}	m68k_incpc (6);
+l_32: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc ();
+	dsta = get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte (dsta); upper = (uae_s32)(uae_s8)get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_33; }
+}
+}}}}l_33: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BTST.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0100_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPMR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0108_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 8;  
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_u16 val;
+	MovepByteNbr=1; val = ((get_byte (memp) & 0xff) << 8);
+	MovepByteNbr=2; val += (get_byte (memp + 2) & 0xff);
+	MovepByteNbr=0;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0110_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0118_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0120_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0128_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0130_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0138_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0139_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_013a_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_getpc () + 2;
+	dsta += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_013b_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	dsta = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,#.B */
+uae_u32 REGPARAM2 CPUFUNC(op_013c_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = get_dibyte (2);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0140_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPMR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0148_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 16; 
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_u32 val;
+	MovepByteNbr=1; val = ((get_byte (memp) & 0xff) << 24);
+	MovepByteNbr=2; val += ((get_byte (memp + 2) & 0xff) << 16);
+	MovepByteNbr=3; val += ((get_byte (memp + 4) & 0xff) << 8);
+	MovepByteNbr=4; val += (get_byte (memp + 6) & 0xff);
+	MovepByteNbr=0;
+	m68k_dreg (regs, dstreg) = (val);
+}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0150_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0158_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0160_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0168_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0170_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0178_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0179_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0180_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPRM.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0188_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	MovepByteNbr=1; 	put_byte (memp, src >> 8);
+	MovepByteNbr=2; 	put_byte (memp + 2, src);
+	MovepByteNbr=0;
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0190_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0198_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01b8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01b9_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_01c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPRM.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	MovepByteNbr=1; 	put_byte (memp, src >> 24);
+	MovepByteNbr=2; 	put_byte (memp + 2, src >> 16);
+	MovepByteNbr=3; 	put_byte (memp + 4, src >> 8);
+	MovepByteNbr=4; 	put_byte (memp + 6, src);
+	MovepByteNbr=0;
+}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_01d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01f8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01f9_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0200_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_dibyte (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0210_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0218_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0220_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0228_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0230_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0238_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0239_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ANDSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_023c_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_diword (2);
+	src |= 0xFF00;
+	regs.sr &= src;
+	MakeFromSR();
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0240_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0250_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0258_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0260_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0268_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0270_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0278_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0279_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s16 dst = get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ANDSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_027c_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_90; }
+{	MakeSR ();
+{	uae_s16 src = get_diword (2);
+	regs.sr &= src;
+	MakeFromSR();
+}}}	m68k_incpc (4);
+l_90: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0280_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0290_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0298_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (6);
+{	uae_s32 dst = get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_02b0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_02b8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (6);
+{	uae_s32 dst = get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_02b9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = get_dilong (6);
+{	uae_s32 dst = get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02d0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word (dsta); upper = (uae_s32)(uae_s16)get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_99; }
+}
+}}}	m68k_incpc (4);
+l_99: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02e8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word (dsta); upper = (uae_s32)(uae_s16)get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_100; }
+}
+}}}	m68k_incpc (6);
+l_100: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word (dsta); upper = (uae_s32)(uae_s16)get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_101; }
+}
+}}}}l_101: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word (dsta); upper = (uae_s32)(uae_s16)get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_102; }
+}
+}}}	m68k_incpc (6);
+l_102: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word (dsta); upper = (uae_s32)(uae_s16)get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_103; }
+}
+}}}	m68k_incpc (8);
+l_103: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc () + 4;
+	dsta += (uae_s32)(uae_s16)get_diword (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word (dsta); upper = (uae_s32)(uae_s16)get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_104; }
+}
+}}}	m68k_incpc (6);
+l_104: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc ();
+	dsta = get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word (dsta); upper = (uae_s32)(uae_s16)get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_105; }
+}
+}}}}l_105: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0400_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_dibyte (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0410_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0418_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0420_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0428_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0430_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0438_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0439_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0440_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0450_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0458_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0460_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0468_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0470_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0478_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0479_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0480_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0490_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0498_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (6);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_04b0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_04b8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (6);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_04b9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = get_dilong (6);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04d0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long (dsta); upper = get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_130; }
+}
+}}}	m68k_incpc (4);
+l_130: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04e8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long (dsta); upper = get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_131; }
+}
+}}}	m68k_incpc (6);
+l_131: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long (dsta); upper = get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_132; }
+}
+}}}}l_132: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long (dsta); upper = get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_133; }
+}
+}}}	m68k_incpc (6);
+l_133: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long (dsta); upper = get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_134; }
+}
+}}}	m68k_incpc (8);
+l_134: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc () + 4;
+	dsta += (uae_s32)(uae_s16)get_diword (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long (dsta); upper = get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_135; }
+}
+}}}	m68k_incpc (6);
+l_135: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc ();
+	dsta = get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long (dsta); upper = get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_136; }
+}
+}}}}l_136: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0600_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_dibyte (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0610_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0618_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0620_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0628_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0630_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0638_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0639_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0640_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0650_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0658_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0660_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0668_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0670_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0678_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0679_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0680_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0690_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0698_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (6);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_06b0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_06b8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (6);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_06b9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = get_dilong (6);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RTM.L Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* RTM.L An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BTST.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0800_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0810_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0818_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0820_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0828_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0830_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0838_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0839_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_083a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc () + 4;
+	dsta += (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_083b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc ();
+	dsta = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0840_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0850_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0858_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0860_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0868_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0870_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0878_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0879_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0880_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0890_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0898_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08b0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08b8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08b9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_08c0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08d0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_08d8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08f0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a00_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_dibyte (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a10_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a18_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a20_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a28_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a30_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a38_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a39_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s8 dst = get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a3c_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_diword (2);
+	src &= 0xFF;
+	regs.sr ^= src;
+	MakeFromSR();
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a40_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a50_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a58_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a60_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a68_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a70_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a78_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a79_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s16 dst = get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a7c_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_221; }
+{	MakeSR ();
+{	uae_s16 src = get_diword (2);
+	regs.sr ^= src;
+	MakeFromSR();
+}}}	m68k_incpc (4);
+l_221: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a80_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a90_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a98_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (6);
+{	uae_s32 dst = get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (6);
+{	uae_s32 dst = get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = get_dilong (6);
+{	uae_s32 dst = get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CAS.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ad0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ad8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ae0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpc (4);
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ae8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
+#ifdef PART_2
+/* CAS.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s8 dst = get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpc (8);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c00_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_dibyte (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c10_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c18_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c20_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c28_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c30_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c38_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c39_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c3a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc () + 4;
+	dsta += (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.B #.B,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c3b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc ();
+	dsta = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c40_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c50_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c58_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c60_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c68_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c70_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c78_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c79_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c7a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc () + 4;
+	dsta += (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c7b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc ();
+	dsta = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c80_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c90_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c98_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (6);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (6);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = get_dilong (6);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (10);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cba_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc () + 6;
+	dsta += (uae_s32)(uae_s16)get_diword (6);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.L #.L,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cbb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (6);
+{	tmppc = m68k_getpc ();
+	dsta = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cd0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (4);
+		op_unimpl (opcode);
+		goto l_267;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpc (4);
+l_267: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cd8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) -= 2;
+	m68k_incpc (4);
+		op_unimpl (opcode);
+		goto l_268;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpc (4);
+l_268: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ce0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) += 2;
+	m68k_incpc (4);
+		op_unimpl (opcode);
+		goto l_269;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpc (4);
+l_269: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ce8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (6);
+		op_unimpl (opcode);
+		goto l_270;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpc (6);
+l_270: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		op_unimpl (opcode);
+		goto l_271;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}}l_271: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 dst = get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (6);
+		op_unimpl (opcode);
+		goto l_272;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpc (6);
+l_272: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s16 dst = get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (8);
+		op_unimpl (opcode);
+		goto l_273;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpc (8);
+l_273: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS2.W #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cfc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 extra;
+	extra = get_dilong (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u16 dst1 = get_word (rn1), dst2 = get_word (rn2);
+{uae_u32 newv = ((uae_u16)(dst1)) - ((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s16)(dst1)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u16)(dst2)) - ((uae_u16)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s16)(dst2)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, extra & 7))) > ((uae_u16)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	put_word (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	put_word (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);
+	m68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);
+	}
+}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e10_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_275; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpc (4);
+l_275: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e18_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_276; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpc (4);
+l_276: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e20_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_277; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpc (4);
+l_277: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e28_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_278; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 src = get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpc (6);
+l_278: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e30_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_279; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	put_byte (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpc (4);
+{	srca = get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s8 src = get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}}l_279: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e38_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_280; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s8 src = get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpc (6);
+l_280: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e39_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_281; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_dilong (4);
+{	uae_s8 src = get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpc (8);
+l_281: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e50_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_282; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpc (4);
+l_282: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e58_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_283; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, dstreg) += 2;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpc (4);
+l_283: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e60_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_284; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpc (4);
+l_284: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e68_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_285; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 src = get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpc (6);
+l_285: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e70_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_286; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	put_word (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpc (4);
+{	srca = get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s16 src = get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}}l_286: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e78_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_287; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s16 src = get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpc (6);
+l_287: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e79_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_288; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_dilong (4);
+{	uae_s16 src = get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpc (8);
+l_288: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e90_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_289; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpc (4);
+l_289: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e98_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_290; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, dstreg) += 4;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpc (4);
+l_290: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ea0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_291; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpc (4);
+l_291: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ea8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_292; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s32 src = get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpc (6);
+l_292: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_293; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	put_long (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpc (4);
+{	srca = get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s32 src = get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}}l_293: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_294; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s32 src = get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpc (6);
+l_294: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_295; }
+{{	uae_s16 extra = get_diword (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_dilong (4);
+{	uae_s32 src = get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpc (8);
+l_295: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ed0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (4);
+		op_unimpl (opcode);
+		goto l_296;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpc (4);
+l_296: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ed8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) -= 4;
+	m68k_incpc (4);
+		op_unimpl (opcode);
+		goto l_297;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpc (4);
+l_297: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ee0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 26; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) += 4;
+	m68k_incpc (4);
+		op_unimpl (opcode);
+		goto l_298;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpc (4);
+l_298: ;
+return 26 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ee8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s32 dst = get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (6);
+		op_unimpl (opcode);
+		goto l_299;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpc (6);
+l_299: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		op_unimpl (opcode);
+		goto l_300;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}}l_300: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s32 dst = get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (6);
+		op_unimpl (opcode);
+		goto l_301;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpc (6);
+l_301: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s32 dst = get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (8);
+		op_unimpl (opcode);
+		goto l_302;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpc (8);
+l_302: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS2.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0efc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 extra;
+	extra = get_dilong (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u32 dst1 = get_long (rn1), dst2 = get_long (rn2);
+{uae_u32 newv = ((uae_u32)(dst1)) - ((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s32)(dst1)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u32)(dst2)) - ((uae_u32)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s32)(dst2)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, extra & 7))) > ((uae_u32)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	put_long (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	put_long (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = dst2;
+	m68k_dreg (regs, (extra >> 22) & 7) = dst1;
+	}
+}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1000_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1010_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1018_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1020_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (2);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1028_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1030_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1038_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1039_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (6);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_dibyte (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1080_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1090_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1098_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10ba_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1100_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1110_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1118_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1120_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1128_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1130_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1138_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1139_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1140_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1150_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1158_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1160_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1168_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1170_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1178_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1179_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1180_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1190_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1198_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11ba_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (10);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (8);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2000_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2008_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2010_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2018_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2020_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2028_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2030_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2038_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2039_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (6);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2040_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2048_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2050_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2058_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2060_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2068_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2070_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2078_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2079_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_207c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (6);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2080_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2088_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2090_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2098_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20ba_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2100_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2108_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2110_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2118_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2120_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2128_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2130_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2138_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2139_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2140_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2148_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2150_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2158_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2160_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2168_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2170_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2178_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2179_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (8);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2180_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2188_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2190_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2198_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_3
+/* MOVE.L -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21ba_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (8);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (10);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = get_dilong (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (10);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3000_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3008_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3010_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3018_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3020_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (2);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3028_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3030_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3038_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3039_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (6);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3040_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3048_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3050_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3058_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3060_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (2);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3068_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3070_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3078_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3079_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (6);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_307c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3080_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3088_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3090_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3098_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30ba_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3100_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3108_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3110_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3118_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3120_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3128_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3130_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3138_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3139_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3140_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3148_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3150_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3158_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3160_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3168_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3170_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3178_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3179_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3180_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3188_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3190_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3198_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31ba_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (10);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (8);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4000_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4010_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte (srca, newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4018_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte (srca, newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4020_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte (srca, newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4028_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte (srca, newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4030_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte (srca, newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4038_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte (srca, newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4039_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte (srca, newv);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4040_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4050_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word (srca, newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4058_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word (srca, newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4060_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word (srca, newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4068_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word (srca, newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4070_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word (srca, newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4078_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word (srca, newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4079_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word (srca, newv);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4080_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4090_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long (srca, newv);
+}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4098_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long (srca, newv);
+}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long (srca, newv);
+}}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long (srca, newv);
+}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long (srca, newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40b8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long (srca, newv);
+}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40b9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long (srca, newv);
+}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_40c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_632; }
+{{	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}}	m68k_incpc (2);
+l_632: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_633; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}}	m68k_incpc (2);
+l_633: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_40d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_634; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}}	m68k_incpc (2);
+l_634: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{if (!regs.s) { Exception (8); goto l_635; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}}	m68k_incpc (2);
+l_635: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_636; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}}	m68k_incpc (4);
+l_636: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_637; }
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}}}l_637: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_638; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}}	m68k_incpc (4);
+l_638: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_639; }
+{{	uaecptr srca;
+	srca = get_dilong (2);
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}}	m68k_incpc (6);
+l_639: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CHK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4100_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_640;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_640;
+	}
+}}}l_640: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4110_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_641;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_641;
+	}
+}}}}l_641: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (An)+,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4118_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_642;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_642;
+	}
+}}}}l_642: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L -(An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4120_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_643;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_643;
+	}
+}}}}l_643: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d16,An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4128_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_644;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_644;
+	}
+}}}}l_644: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d8,An,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4130_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_645;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_645;
+	}
+}}}}}l_645: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (xxx).W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4138_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_646;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_646;
+	}
+}}}}l_646: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (xxx).L,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4139_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_647;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_647;
+	}
+}}}}l_647: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d16,PC),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_648;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_648;
+	}
+}}}}l_648: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d8,PC,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_649;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_649;
+	}
+}}}}}l_649: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L #.L,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_650;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_650;
+	}
+}}}l_650: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4180_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_651;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_651;
+	}
+}}}l_651: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4190_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_652;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_652;
+	}
+}}}}l_652: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4198_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_653;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_653;
+	}
+}}}}l_653: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_654;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_654;
+	}
+}}}}l_654: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_655;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_655;
+	}
+}}}}l_655: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_656;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_656;
+	}
+}}}}}l_656: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_657;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_657;
+	}
+}}}}l_657: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_658;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_658;
+	}
+}}}}l_658: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41ba_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_659;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_659;
+	}
+}}}}l_659: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_660;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_660;
+	}
+}}}}}l_660: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_661;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_661;
+	}
+}}}l_661: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4200_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4210_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4218_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4220_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4228_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4230_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4238_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4239_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4240_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4250_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4258_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4260_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4268_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4270_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4278_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4279_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4280_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4290_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4298_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_42b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_42b8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_42b9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	put_word (srca, regs.sr & 0xff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	put_word (srca, regs.sr & 0xff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	put_word (srca, regs.sr & 0xff);
+}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+	MakeSR ();
+	put_word (srca, regs.sr & 0xff);
+}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	put_word (srca, regs.sr & 0xff);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+	MakeSR ();
+	put_word (srca, regs.sr & 0xff);
+}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+	MakeSR ();
+	put_word (srca, regs.sr & 0xff);
+}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* NEG.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4400_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_4
+/* NEG.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4410_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4418_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4420_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4428_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4430_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (srca, dst);
+}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4438_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4439_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (srca, dst);
+}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4440_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4450_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4458_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4460_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4468_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4470_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (srca, dst);
+}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4478_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4479_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (srca, dst);
+}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4480_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4490_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4498_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (srca, dst);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44b8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44b9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (srca, dst);
+}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_44c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_44d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B #.B */
+uae_u32 REGPARAM2 CPUFUNC(op_44fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4600_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4610_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte (srca, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4618_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte (srca, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4620_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte (srca, dst);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4628_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte (srca, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4630_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte (srca, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4638_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte (srca, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4639_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte (srca, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4640_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4650_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word (srca, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4658_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word (srca, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4660_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word (srca, dst);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4668_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word (srca, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4670_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word (srca, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4678_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word (srca, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4679_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word (srca, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4680_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4690_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long (srca, dst);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4698_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long (srca, dst);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long (srca, dst);
+}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long (srca, dst);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long (srca, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46b8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long (srca, dst);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46b9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long (srca, dst);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_46c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_760; }
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.sr = src;
+	MakeFromSR();
+}}}	m68k_incpc (2);
+l_760: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_761; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpc (2);
+l_761: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_46d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_762; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpc (2);
+l_762: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_763; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpc (2);
+l_763: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_764; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpc (4);
+l_764: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_765; }
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}}l_765: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_766; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpc (4);
+l_766: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_767; }
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpc (6);
+l_767: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_768; }
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpc (4);
+l_768: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_769; }
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}}l_769: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_46fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_770; }
+{{	uae_s16 src = get_diword (2);
+	regs.sr = src;
+	MakeFromSR();
+}}}	m68k_incpc (4);
+l_770: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4800_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LINK.L An,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4808_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 8;  
+{{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 offs;
+	offs = get_dilong (2);
+	put_long (olda, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* NBCD.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4810_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_byte (srca, newv);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4818_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_byte (srca, newv);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4820_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_byte (srca, newv);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4828_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_byte (srca, newv);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4830_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_byte (srca, newv);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4838_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_byte (srca, newv);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4839_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_byte (srca, newv);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SWAP.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4840_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 34;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BKPTQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4848_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 99;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PEA.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4850_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	put_long (dsta, srca);
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4868_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	put_long (dsta, srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4870_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	put_long (dsta, srca);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4878_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	put_long (dsta, srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4879_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	put_long (dsta, srca);
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_487a_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	put_long (dsta, srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_487b_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	put_long (dsta, srca);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* EXT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4880_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u16 dst = (uae_s16)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4890_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_diword (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 6;  
+{	uae_u16 mask = get_diword (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	int type = get_cpu_model () >= 68020;
+	while (amask) {
+		srca -= 2;
+		if (!type || movem_index2[amask] != dstreg)
+			put_word (srca, m68k_areg (regs, movem_index2[amask]));
+		else
+			put_word (srca, m68k_areg (regs, movem_index2[amask]) - 2);
+		amask = movem_next[amask];
+	}
+	while (dmask) { srca -= 2; put_word (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_diword (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48b0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_diword (2);
+{	uaecptr srca;
+	m68k_incpc (4);
+{	srca = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48b8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_diword (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48b9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_diword (2);
+{	uaecptr srca;
+	srca = get_dilong (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}	m68k_incpc (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EXT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_48c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48d0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_diword (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 10; 
+{	uae_u16 mask = get_diword (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	int type = get_cpu_model () >= 68020;
+	while (amask) {
+		srca -= 4;
+		if (!type || movem_index2[amask] != dstreg)
+			put_long (srca, m68k_areg (regs, movem_index2[amask]));
+		else
+			put_long (srca, m68k_areg (regs, movem_index2[amask]) - 4);
+		amask = movem_next[amask];
+	}
+	while (dmask) { srca -= 4; put_long (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_diword (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48f0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_diword (2);
+{	uaecptr srca;
+	m68k_incpc (4);
+{	srca = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_diword (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_diword (2);
+{	uaecptr srca;
+	srca = get_dilong (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXT.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_49c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a00_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a10_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a18_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a20_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a28_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a30_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a38_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a39_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3a_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3b_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B #.B */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3c_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_dibyte (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a40_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a48_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a50_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a58_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a60_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a68_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a70_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a78_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a79_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7a_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7b_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7c_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a80_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.L An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a88_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a90_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a98_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4aba_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4abb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4abc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TAS.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4ac0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((src) & 0xff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_byte (srca, src);
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_byte (srca, src);
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_byte (srca, src);
+}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_byte (srca, src);
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4af0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_byte (srca, src);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4af8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_byte (srca, src);
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4af9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_byte (srca, src);
+}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MULL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c00_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_847;
+}}}l_847: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c10_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_incpc (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_848;
+}}}}l_848: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c18_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpc (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_849;
+}}}}l_849: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c20_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpc (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_850;
+}}}}l_850: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c28_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s32 dst = get_long (dsta);
+	m68k_incpc (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_851;
+}}}}l_851: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c30_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_852;
+}}}}}l_852: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c38_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s32 dst = get_long (dsta);
+	m68k_incpc (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_853;
+}}}}l_853: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c39_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s32 dst = get_long (dsta);
+	m68k_incpc (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_854;
+}}}}l_854: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc () + 4;
+	dsta += (uae_s32)(uae_s16)get_diword (4);
+{	uae_s32 dst = get_long (dsta);
+	m68k_incpc (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_855;
+}}}}l_855: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc ();
+	dsta = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = get_long (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_856;
+}}}}}l_856: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3c_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_diword (2);
+{	uae_s32 dst;
+	dst = get_dilong (4);
+	m68k_incpc (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_857;
+}}}l_857: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c40_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_858;
+}}}l_858: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c50_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_incpc (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_859;
+}}}}l_859: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c58_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpc (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_860;
+}}}}l_860: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c60_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpc (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_861;
+}}}}l_861: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c68_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_s32 dst = get_long (dsta);
+	m68k_incpc (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_862;
+}}}}l_862: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c70_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_863;
+}}}}}l_863: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c78_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_s32 dst = get_long (dsta);
+	m68k_incpc (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_864;
+}}}}l_864: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c79_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_s32 dst = get_long (dsta);
+	m68k_incpc (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_865;
+}}}}l_865: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc () + 4;
+	dsta += (uae_s32)(uae_s16)get_diword (4);
+{	uae_s32 dst = get_long (dsta);
+	m68k_incpc (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_866;
+}}}}l_866: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc ();
+	dsta = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = get_long (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_867;
+}}}}}l_867: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7c_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_diword (2);
+{	uae_s32 dst;
+	dst = get_dilong (4);
+	m68k_incpc (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_868;
+}}}l_868: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVMEL.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4c90_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4c98_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ca8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpc (4);
+{	srca = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_dilong (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cba_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpc () + 4;
+	srca += (uae_s32)(uae_s16)get_diword (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cbb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ce8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpc (4);
+{	srca = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_dilong (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpc () + 4;
+	srca += (uae_s32)(uae_s16)get_diword (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* TRAPQ.L # */
+uae_u32 REGPARAM2 CPUFUNC(op_4e40_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 15);
+	OpcodeFamily = 39;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+	m68k_incpc (2);
+	Exception (src + 32);
+}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* LINK.W An,#.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e50_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 8;  
+{{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	put_long (olda, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* UNLK.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e58_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 48;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	m68k_areg (regs, 7) = src;
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7);
+{	uae_s32 old = get_long (olda);
+	m68k_areg (regs, 7) += 4;
+	m68k_areg (regs, srcreg) = (old);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVR2USP.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e60_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 40;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_888; }
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	regs.usp = src;
+}}}	m68k_incpc (2);
+l_888: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVUSP2R.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e68_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 41;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_889; }
+{{	m68k_areg (regs, srcreg) = (regs.usp);
+}}}	m68k_incpc (2);
+l_889: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RESET.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e70_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 42;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_890; }
+{	cpureset ();
+	m68k_incpc (2);
+}}l_890: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOP.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e71_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 43;
+	CurrentInstrCycles = 4;  
+{}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* STOP.L #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e72_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 44;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_892; }
+{{	uae_s16 src = get_diword (2);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_setstopped ();
+	m68k_incpc (4);
+}}}l_892: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RTE.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e73_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 45;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_893; }
+{	uae_u16 newsr; uae_u32 newpc;
+	for (;;) {
+		uaecptr a = m68k_areg (regs, 7);
+		uae_u16 sr = get_word (a);
+		uae_u32 pc = get_long (a + 2);
+		uae_u16 format = get_word (a + 2 + 4);
+		int frame = format >> 12;
+		int offset = 8;
+		newsr = sr; newpc = pc;
+		if (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }
+		else if (frame == 0x1) { m68k_areg (regs, 7) += offset; }
+		else if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }
+		else if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }
+		else if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }
+		else if (frame == 0x7) { m68k_areg (regs, 7) += offset + 52; break; }
+		else if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }
+		else if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }
+		else if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }
+		else { m68k_areg (regs, 7) += offset; Exception (14); goto l_893; }
+		regs.sr = newsr;
+	MakeFromSR();
+}
+	regs.sr = newsr;
+	MakeFromSR();
+	if (newpc & 1) {
+		exception3i (0x4E73, newpc);
+		goto l_893;
+	}
+	m68k_setpc (newpc);
+}}l_893: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RTD.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e74_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 46;
+	CurrentInstrCycles = 8;  
+{{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = get_long (pca);
+	m68k_areg (regs, 7) += 4;
+{	uae_s16 offs = get_diword (2);
+	m68k_areg (regs, 7) += offs;
+	if (pc & 1) {
+		exception3i (0x4E74, pc);
+		goto l_894;
+	}
+	m68k_setpc (pc);
+}}}}l_894: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* RTS.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e75_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 49;
+	CurrentInstrCycles = 8;  
+{	uaecptr pc = m68k_getpc ();
+	m68k_do_rts ();
+	if (m68k_getpc () & 1) {
+		uaecptr faultpc = m68k_getpc ();
+	m68k_setpc (pc);
+		exception3i (0x4E75, faultpc);
+		goto l_895;
+	}
+}l_895: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TRAPV.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e76_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 50;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	if (GET_VFLG ()) {
+		Exception (7);
+		goto l_896;
+	}
+}l_896: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RTR.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e77_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 51;
+	CurrentInstrCycles = 12; 
+{	uaecptr oldpc = m68k_getpc ();
+	MakeSR ();
+{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+{	uae_s16 sr = get_word (sra);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = get_long (pca);
+	m68k_areg (regs, 7) += 4;
+	regs.sr &= 0xFF00; sr &= 0xFF;
+	regs.sr |= sr;
+	m68k_setpc (pc);
+	MakeFromSR();
+	if (m68k_getpc () & 1) {
+		uaecptr faultpc = m68k_getpc ();
+	m68k_setpc (oldpc);
+		exception3i (0x4E77, faultpc);
+		goto l_897;
+	}
+}}}}}l_897: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEC2.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7a_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 82;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_898; }
+{{	uae_s16 src = get_diword (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_movec2(src & 0xFFF, regp)) goto l_898;
+}}}}	m68k_incpc (4);
+l_898: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE2C.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7b_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 83;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_899; }
+{{	uae_s16 src = get_diword (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_move2c(src & 0xFFF, regp)) goto l_899;
+}}}}	m68k_incpc (4);
+l_899: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* JSR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4e90_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr oldpc = m68k_getpc () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_900;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	put_long (m68k_areg (regs, 7), oldpc);
+}}}l_900: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ea8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uaecptr oldpc = m68k_getpc () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_901;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	put_long (m68k_areg (regs, 7), oldpc);
+}}}l_901: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uaecptr oldpc = m68k_getpc () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_902;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	put_long (m68k_areg (regs, 7), oldpc);
+}}}}l_902: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uaecptr oldpc = m68k_getpc () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_903;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	put_long (m68k_areg (regs, 7), oldpc);
+}}}l_903: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uaecptr oldpc = m68k_getpc () + 6;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_904;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	put_long (m68k_areg (regs, 7), oldpc);
+}}}l_904: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eba_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uaecptr oldpc = m68k_getpc () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_905;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	put_long (m68k_areg (regs, 7), oldpc);
+}}}l_905: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ebb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uaecptr oldpc = m68k_getpc () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_906;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	put_long (m68k_areg (regs, 7), oldpc);
+}}}}l_906: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ed0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_907;
+	}
+	m68k_setpc (srca);
+}}l_907: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ee8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_908;
+	}
+	m68k_setpc (srca);
+}}l_908: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_909;
+	}
+	m68k_setpc (srca);
+}}}l_909: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_910;
+	}
+	m68k_setpc (srca);
+}}l_910: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_911;
+	}
+	m68k_setpc (srca);
+}}l_911: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_912;
+	}
+	m68k_setpc (srca);
+}}l_912: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_913;
+	}
+	m68k_setpc (srca);
+}}}l_913: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5000_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5010_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5018_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5020_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5028_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5030_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5038_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5039_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5040_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5048_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5050_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5058_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5060_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5068_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5070_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5078_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5079_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5080_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5088_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5090_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5098_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_5
+/* ADDQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_50b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_50b8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_50b9_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (0) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (0)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_941;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_941: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (0)) { Exception (7); goto l_949; }
+}}	m68k_incpc (4);
+l_949: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (0)) { Exception (7); goto l_950; }
+}}	m68k_incpc (6);
+l_950: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (0)) { Exception (7); goto l_951; }
+}	m68k_incpc (2);
+l_951: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* SUBQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5100_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5110_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5118_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5120_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5128_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5130_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5138_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5139_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5140_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5148_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5150_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5158_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5160_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5168_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5170_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5178_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5179_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5180_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5188_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5190_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5198_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_51b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_51b8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_51b9_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (1) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (1)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_979;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_979: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (1)) { Exception (7); goto l_987; }
+}}	m68k_incpc (4);
+l_987: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (1)) { Exception (7); goto l_988; }
+}}	m68k_incpc (6);
+l_988: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (1)) { Exception (7); goto l_989; }
+}	m68k_incpc (2);
+l_989: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (2) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (2)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_991;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_991: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (2)) { Exception (7); goto l_999; }
+}}	m68k_incpc (4);
+l_999: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (2)) { Exception (7); goto l_1000; }
+}}	m68k_incpc (6);
+l_1000: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (2)) { Exception (7); goto l_1001; }
+}	m68k_incpc (2);
+l_1001: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (3) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (3)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_1003;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_1003: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (3)) { Exception (7); goto l_1011; }
+}}	m68k_incpc (4);
+l_1011: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (3)) { Exception (7); goto l_1012; }
+}}	m68k_incpc (6);
+l_1012: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (3)) { Exception (7); goto l_1013; }
+}	m68k_incpc (2);
+l_1013: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (4) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (4)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_1015;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_1015: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (4)) { Exception (7); goto l_1023; }
+}}	m68k_incpc (4);
+l_1023: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (4)) { Exception (7); goto l_1024; }
+}}	m68k_incpc (6);
+l_1024: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (4)) { Exception (7); goto l_1025; }
+}	m68k_incpc (2);
+l_1025: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (5) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (5)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_1027;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_1027: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (5)) { Exception (7); goto l_1035; }
+}}	m68k_incpc (4);
+l_1035: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (5)) { Exception (7); goto l_1036; }
+}}	m68k_incpc (6);
+l_1036: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (5)) { Exception (7); goto l_1037; }
+}	m68k_incpc (2);
+l_1037: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (6) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (6)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_1039;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_1039: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (6)) { Exception (7); goto l_1047; }
+}}	m68k_incpc (4);
+l_1047: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (6)) { Exception (7); goto l_1048; }
+}}	m68k_incpc (6);
+l_1048: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (6)) { Exception (7); goto l_1049; }
+}	m68k_incpc (2);
+l_1049: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (7) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (7)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_1051;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_1051: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (7)) { Exception (7); goto l_1059; }
+}}	m68k_incpc (4);
+l_1059: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (7)) { Exception (7); goto l_1060; }
+}}	m68k_incpc (6);
+l_1060: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (7)) { Exception (7); goto l_1061; }
+}	m68k_incpc (2);
+l_1061: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (8) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (8)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_1063;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_1063: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (8)) { Exception (7); goto l_1071; }
+}}	m68k_incpc (4);
+l_1071: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (8)) { Exception (7); goto l_1072; }
+}}	m68k_incpc (6);
+l_1072: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (8)) { Exception (7); goto l_1073; }
+}	m68k_incpc (2);
+l_1073: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (9) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (9)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_1075;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_1075: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (9)) { Exception (7); goto l_1083; }
+}}	m68k_incpc (4);
+l_1083: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (9)) { Exception (7); goto l_1084; }
+}}	m68k_incpc (6);
+l_1084: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (9)) { Exception (7); goto l_1085; }
+}	m68k_incpc (2);
+l_1085: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (10) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (10)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_1087;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_1087: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (10)) { Exception (7); goto l_1095; }
+}}	m68k_incpc (4);
+l_1095: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (10)) { Exception (7); goto l_1096; }
+}}	m68k_incpc (6);
+l_1096: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (10)) { Exception (7); goto l_1097; }
+}	m68k_incpc (2);
+l_1097: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (11) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (11)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_1099;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_1099: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (11)) { Exception (7); goto l_1107; }
+}}	m68k_incpc (4);
+l_1107: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (11)) { Exception (7); goto l_1108; }
+}}	m68k_incpc (6);
+l_1108: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (11)) { Exception (7); goto l_1109; }
+}	m68k_incpc (2);
+l_1109: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (12) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (12)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_1111;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_1111: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (12)) { Exception (7); goto l_1119; }
+}}	m68k_incpc (4);
+l_1119: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (12)) { Exception (7); goto l_1120; }
+}}	m68k_incpc (6);
+l_1120: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (12)) { Exception (7); goto l_1121; }
+}	m68k_incpc (2);
+l_1121: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (13) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (13)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_1123;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_1123: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (13)) { Exception (7); goto l_1131; }
+}}	m68k_incpc (4);
+l_1131: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (13)) { Exception (7); goto l_1132; }
+}}	m68k_incpc (6);
+l_1132: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (13)) { Exception (7); goto l_1133; }
+}	m68k_incpc (2);
+l_1133: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (14) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (14)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_1135;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_1135: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (14)) { Exception (7); goto l_1143; }
+}}	m68k_incpc (4);
+l_1143: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (14)) { Exception (7); goto l_1144; }
+}}	m68k_incpc (6);
+l_1144: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (14)) { Exception (7); goto l_1145; }
+}	m68k_incpc (2);
+l_1145: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (15) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_diword (2);
+	uaecptr oldpc = m68k_getpc ();
+	if (!cctrue (15)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc () + 2 + (uae_s32)offs + 2);
+				goto l_1147;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_1147: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffa_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_diword (2);
+	if (cctrue (15)) { Exception (7); goto l_1155; }
+}}	m68k_incpc (4);
+l_1155: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffb_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_dilong (2);
+	if (cctrue (15)) { Exception (7); goto l_1156; }
+}}	m68k_incpc (6);
+l_1156: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffc_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (15)) { Exception (7); goto l_1157; }
+}	m68k_incpc (2);
+l_1157: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Bcc.W #.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6000_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1158;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1158: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6001_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1159;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1159: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_60ff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1160;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1160: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_6100_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_s16 src = get_diword (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpc () + s, 0, 1, m68k_getpc () + s);
+		goto l_1161;
+	}
+	m68k_do_bsr (m68k_getpc () + 4, s);
+}}l_1161: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSRQ.B # */
+uae_u32 REGPARAM2 CPUFUNC(op_6101_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_u32 src = srcreg;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpc () + s, 0, 1, m68k_getpc () + s);
+		goto l_1162;
+	}
+	m68k_do_bsr (m68k_getpc () + 2, s);
+}}l_1162: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSR.L #.L */
+uae_u32 REGPARAM2 CPUFUNC(op_61ff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_s32 src;
+	src = get_dilong (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpc () + s, 0, 1, m68k_getpc () + s);
+		goto l_1163;
+	}
+	m68k_do_bsr (m68k_getpc () + 6, s);
+}}l_1163: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6200_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1164;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1164: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6201_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1165;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1165: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_62ff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1166;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1166: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6300_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1167;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1167: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6301_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1168;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1168: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_6
+/* Bcc.L #.L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_63ff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1169;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1169: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6400_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1170;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1170: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6401_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1171;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1171: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_64ff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1172;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1172: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6500_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1173;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1173: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6501_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1174;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1174: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_65ff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1175;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1175: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6600_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1176;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1176: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6601_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1177;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1177: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_66ff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1178;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1178: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6700_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1179;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1179: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6701_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1180;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1180: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_67ff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1181;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1181: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6800_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1182;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1182: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6801_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1183;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1183: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_68ff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1184;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1184: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6900_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1185;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1185: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6901_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1186;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1186: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_69ff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1187;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1187: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a00_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1188;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1188: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a01_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1189;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1189: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6aff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1190;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1190: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b00_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1191;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1191: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b01_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1192;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1192: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6bff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1193;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1193: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c00_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1194;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1194: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c01_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1195;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1195: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6cff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1196;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1196: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d00_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1197;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1197: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d01_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1198;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1198: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6dff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1199;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1199: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e00_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1200;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1200: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e01_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1201;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1201: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6eff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1202;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1202: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f00_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_diword (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1203;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_1203: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f01_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1204;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_1204: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6fff_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc () + 2 + (uae_s32)src);
+		goto l_1205;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_1205: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_7000_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8000_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8010_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8018_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8020_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8028_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8030_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8038_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8039_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_dibyte (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8040_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8050_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8058_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8060_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8068_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8070_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8078_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8079_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8080_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8090_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8098_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80ba_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 110;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_1240;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (2);
+	}
+}}}l_1240: ;
+return 110 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_1241;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (2);
+	}
+}}}}l_1241: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_1242;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (2);
+	}
+}}}}l_1242: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_1243;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (2);
+	}
+}}}}l_1243: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_1244;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (4);
+	}
+}}}}l_1244: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (0);
+		Exception (5);
+		goto l_1245;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_1245: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_1246;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (4);
+	}
+}}}}l_1246: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (6);
+		Exception (5);
+		goto l_1247;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (6);
+	}
+}}}}l_1247: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_1248;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (4);
+	}
+}}}}l_1248: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (0);
+		Exception (5);
+		goto l_1249;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_1249: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 114;
+{{	uae_s16 src = get_diword (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_1250;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (4);
+	}
+}}}l_1250: ;
+return 114 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8100_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8108_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_byte (dsta, newv);
+}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8110_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8118_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8120_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8128_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8130_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8138_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8139_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s8 dst = get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PACK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8140_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val = m68k_dreg (regs, srcreg) + get_diword (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);
+}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PACK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8148_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val;
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(get_byte (m68k_areg (regs, srcreg)) & 0xff);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (val | ((uae_u16)(get_byte (m68k_areg (regs, srcreg)) & 0xff) << 8)) + get_diword (2);
+	m68k_areg (regs, dstreg) -= areg_byteinc[dstreg];
+	put_byte (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));
+}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* OR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8150_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8158_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8160_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8168_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 dst = get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8170_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8178_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 dst = get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8179_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s16 dst = get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* UNPK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8180_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val = m68k_dreg (regs, srcreg);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_diword (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);
+}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* UNPK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8188_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val;
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(get_byte (m68k_areg (regs, srcreg)) & 0xff);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_diword (2);
+	m68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];
+	put_byte (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);
+	put_byte (m68k_areg (regs, dstreg), val >> 8);
+}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* OR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8190_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8198_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 dst = get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_81b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_81b8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 dst = get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_81b9_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s32 dst = get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 142;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_1278;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (2);
+}}}l_1278: ;
+return 142 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_1279;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (2);
+}}}}l_1279: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_1280;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (2);
+}}}}l_1280: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_1281;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (2);
+}}}}l_1281: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_1282;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (4);
+}}}}l_1282: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (0);
+		Exception (5);
+		goto l_1283;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_1283: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_1284;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (4);
+}}}}l_1284: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (6);
+		Exception (5);
+		goto l_1285;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (6);
+}}}}l_1285: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_1286;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (4);
+}}}}l_1286: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (0);
+		Exception (5);
+		goto l_1287;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_1287: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 146;
+{{	uae_s16 src = get_diword (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_1288;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (4);
+}}}l_1288: ;
+return 146 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9000_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9010_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9018_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9020_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9028_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9030_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9038_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9039_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_dibyte (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9040_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9048_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9050_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9058_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9060_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9068_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9070_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9078_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9079_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9080_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9088_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9090_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9098_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90ba_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9100_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9108_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9110_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9118_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9120_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9128_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9130_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9138_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9139_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9140_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9148_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9150_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9158_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9160_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9168_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9170_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9178_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9179_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9180_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9188_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 26 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9190_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9198_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_91b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_91b8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_91b9_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b000_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b010_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b018_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b020_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b028_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b030_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b038_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b039_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_dibyte (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b040_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b048_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b050_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b058_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b060_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b068_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b070_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b078_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b079_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b080_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b088_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b090_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b098_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_7
+/* CMP.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0ba_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b100_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b108_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b110_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b118_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b120_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b128_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b130_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b138_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b139_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s8 dst = get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b140_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b148_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b150_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b158_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b160_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b168_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 dst = get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b170_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b178_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 dst = get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b179_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s16 dst = get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b180_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b188_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b190_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b198_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 dst = get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 dst = get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b9_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s32 dst = get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c000_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c010_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c018_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c020_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c028_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c030_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c038_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c039_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_dibyte (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c040_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c050_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c058_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c060_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c068_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c070_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c078_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c079_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c080_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c090_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c098_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0ba_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 58; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (2);
+}}}}return 58 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (2);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (2);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 40; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (2);
+}}}}}return 40 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (4);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (4);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (6);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (4);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 62; 
+{{	uae_s16 src = get_diword (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (4);
+}}}}return 62 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c100_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c108_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_byte (dsta, newv);
+}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c110_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c118_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c120_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c128_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c130_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c138_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c139_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s8 dst = get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c140_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c148_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	m68k_areg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c150_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c158_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c160_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c168_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 dst = get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c170_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c178_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 dst = get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c179_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s16 dst = get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c188_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c190_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c198_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 dst = get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 dst = get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b9_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s32 dst = get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 58; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 58 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 40; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 40 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (6);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 62; 
+{{	uae_s16 src = get_diword (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (4);
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d000_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d010_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d018_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d020_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d028_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d030_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d038_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d039_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_dibyte (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d040_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d048_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d050_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d058_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d060_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d068_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d070_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d078_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d079_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07c_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d080_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d088_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d090_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d098_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0ba_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_diword (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d100_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d108_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d110_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d118_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d120_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d128_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d130_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d138_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d139_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d140_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d148_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d150_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d158_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d160_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d168_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d170_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d178_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d179_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d180_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d188_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 26 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d190_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d198_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b9_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_dilong (2);
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f9_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc ();
+	srca = get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fc_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e000_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e008_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e010_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e018_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e020_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e028_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e030_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e038_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e040_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_8
+/* LSRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e048_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e050_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e058_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e060_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e068_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e070_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e078_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e080_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e088_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e090_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e098_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_dilong (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e100_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e108_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e110_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e118_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e120_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e128_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e130_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e138_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e140_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e148_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e150_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e158_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e160_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e168_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e170_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e178_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e180_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e188_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e190_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e198_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_dilong (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_dilong (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_dilong (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_dilong (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_dilong (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_dilong (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_dilong (2);
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BFTST.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8c0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8d0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8e8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc () + 4;
+	dsta += (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc ();
+	dsta = get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9c0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9d0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9e8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9fa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc () + 4;
+	dsta += (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9fb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc ();
+	dsta = get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eac0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ead0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eae8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebc0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebd0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebe8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebfa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc () + 4;
+	dsta += (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebfb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc ();
+	dsta = get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecc0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecd0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ece8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edc0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edd0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ede8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edfa_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc () + 4;
+	dsta += (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edfb_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc ();
+	dsta = get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eec0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eed0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eee8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efc0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efd0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efe8_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff0_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff8_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff9_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L Dn,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f000_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1788; }
+{	uaecptr pc = m68k_getpc ();
+	uae_u16 extra = get_diword (2);
+	m68k_incpc (4);
+	uae_u16 extraa = 0;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}l_1788: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L An,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f008_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1789; }
+{	uaecptr pc = m68k_getpc ();
+	uae_u16 extra = get_diword (2);
+	m68k_incpc (4);
+	uae_u16 extraa = 0;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}l_1789: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f010_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1790; }
+{	uaecptr pc = m68k_getpc ();
+	uae_u16 extra = get_diword (2);
+	m68k_incpc (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_1790: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (An)+,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f018_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1791; }
+{	uaecptr pc = m68k_getpc ();
+	uae_u16 extra = get_diword (2);
+	m68k_incpc (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_1791: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L -(An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f020_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 6;  
+{if (!regs.s) { Exception (8); goto l_1792; }
+{	uaecptr pc = m68k_getpc ();
+	uae_u16 extra = get_diword (2);
+	m68k_incpc (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) - 4;
+	m68k_areg (regs, srcreg) = extraa;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_1792: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (d16,An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f028_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_1793; }
+{	uaecptr pc = m68k_getpc ();
+	uae_u16 extra = get_diword (2);
+	m68k_incpc (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (0);
+	m68k_incpc (2);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_1793: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (d8,An,Xn),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f030_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_1794; }
+{	uaecptr pc = m68k_getpc ();
+	uae_u16 extra = get_diword (2);
+	m68k_incpc (4);
+{	uaecptr extraa;
+{	extraa = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}}l_1794: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (xxx).W,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f038_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_1795; }
+{	uaecptr pc = m68k_getpc ();
+	uae_u16 extra = get_diword (2);
+	m68k_incpc (4);
+{	uaecptr extraa;
+	extraa = (uae_s32)(uae_s16)get_diword (0);
+	m68k_incpc (2);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_1795: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (xxx).L,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f039_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_1796; }
+{	uaecptr pc = m68k_getpc ();
+	uae_u16 extra = get_diword (2);
+	m68k_incpc (4);
+{	uaecptr extraa;
+	extraa = get_dilong (0);
+	m68k_incpc (4);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_1796: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f200_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f208_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f210_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f218_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f220_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f228_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f230_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f238_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f239_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23a_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23b_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23c_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f240_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FDBcc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f248_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 105;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_dbcc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f250_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f258_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f260_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f268_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f270_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f278_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f279_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27a_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 12; 
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpc ();
+	uae_u16 extra = get_diword (2);
+{	uae_s16 dummy = get_diword (4);
+	m68k_incpc (6);
+	fpuop_trapcc (opcode, oldpc, extra);
+}
+#endif
+}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27b_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 16; 
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpc ();
+	uae_u16 extra = get_diword (2);
+{	uae_s32 dummy;
+	dummy = get_dilong (4);
+	m68k_incpc (8);
+	fpuop_trapcc (opcode, oldpc, extra);
+}
+#endif
+}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L  */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27c_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpc ();
+	uae_u16 extra = get_diword (2);
+	m68k_incpc (4);
+	fpuop_trapcc (opcode, oldpc, extra);
+
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FBccQ.L #,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f280_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+{	uaecptr pc = m68k_getpc ();
+{	uae_s16 extra = get_diword (0);
+	m68k_incpc (2);
+	fpuop_bcc (opcode, pc,extra);
+}}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FBccQ.L #,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f2c0_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+	CurrentInstrCycles = 12; 
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+{	uaecptr pc = m68k_getpc ();
+{	uae_s32 extra;
+	extra = get_dilong (0);
+	m68k_incpc (4);
+	fpuop_bcc (opcode, pc,extra);
+}}
+#endif
+}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f310_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1823; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_1823: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f320_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1824; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_1824: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f328_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1825; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_1825: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f330_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1826; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_1826: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f338_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1827; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_1827: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f339_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1828; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_1828: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f350_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1829; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_1829: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f358_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1830; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_1830: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f368_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1831; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_1831: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f370_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1832; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_1832: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f378_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1833; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_1833: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f379_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1834; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_1834: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f37a_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1835; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_1835: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f37b_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1836; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_1836: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVLQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f408_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 111;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1837; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1837: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVPQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f410_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 112;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1838; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1838: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f418_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1839; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1839: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f419_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1840; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1840: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41a_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1841; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1841: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41b_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1842; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1842: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41c_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1843; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1843: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41d_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1844; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1844: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41e_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1845; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1845: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41f_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1846; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1846: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHLQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f428_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 114;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1847; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1847: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHPQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f430_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 115;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1848; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1848: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f438_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1849; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1849: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f439_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1850; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1850: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43a_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1851; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1851: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43b_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1852; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1852: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43c_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1853; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1853: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43d_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1854; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1854: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43e_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1855; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1855: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43f_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1856; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_1856: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSHN.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f500_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 119;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1857; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_1857: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSH.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f508_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 120;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1858; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_1858: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSHAN.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f510_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 121;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1859; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_1859: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSHA.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f518_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 122;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1860; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_1860: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PTESTW.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f548_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 126;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1861; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_1861: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PTESTR.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f568_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 125;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1862; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_1862: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PLPAW.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f588_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 124;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1863; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_1863: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PLPAR.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f5c8_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 123;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1864; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_1864: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (An)+,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f600_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = m68k_areg (regs, srcreg);
+{	uaecptr memda;
+	memda = get_dilong (2);
+	memsa &= ~15;
+	memda &= ~15;
+	v[0] = get_long (memsa);
+	v[1] = get_long (memsa + 4);
+	v[2] = get_long (memsa + 8);
+	v[3] = get_long (memsa + 12);
+	put_long (memda , v[0]);
+	put_long (memda + 4, v[1]);
+	put_long (memda + 8, v[2]);
+	put_long (memda + 12, v[3]);
+	m68k_areg (regs, srcreg) += 16;
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (xxx).L,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f608_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = get_dilong (2);
+{	uaecptr memda;
+	memda = m68k_areg (regs, dstreg);
+	memsa &= ~15;
+	memda &= ~15;
+	v[0] = get_long (memsa);
+	v[1] = get_long (memsa + 4);
+	v[2] = get_long (memsa + 8);
+	v[3] = get_long (memsa + 12);
+	put_long (memda , v[0]);
+	put_long (memda + 4, v[1]);
+	put_long (memda + 8, v[2]);
+	put_long (memda + 12, v[3]);
+	m68k_areg (regs, dstreg) += 16;
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (An),(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f610_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = m68k_areg (regs, srcreg);
+{	uaecptr memda;
+	memda = get_dilong (2);
+	memsa &= ~15;
+	memda &= ~15;
+	v[0] = get_long (memsa);
+	v[1] = get_long (memsa + 4);
+	v[2] = get_long (memsa + 8);
+	v[3] = get_long (memsa + 12);
+	put_long (memda , v[0]);
+	put_long (memda + 4, v[1]);
+	put_long (memda + 8, v[2]);
+	put_long (memda + 12, v[3]);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (xxx).L,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f618_0)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = get_dilong (2);
+{	uaecptr memda;
+	memda = m68k_areg (regs, dstreg);
+	memsa &= ~15;
+	memda &= ~15;
+	v[0] = get_long (memsa);
+	v[1] = get_long (memsa + 4);
+	v[2] = get_long (memsa + 8);
+	v[3] = get_long (memsa + 12);
+	put_long (memda , v[0]);
+	put_long (memda + 4, v[1]);
+	put_long (memda + 8, v[2]);
+	put_long (memda + 12, v[3]);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (An)+,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f620_0)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = 0;
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 8;  
+{	uae_u32 v[4];
+	uaecptr mems = m68k_areg (regs, srcreg) & ~15, memd;
+	dstreg = (get_diword (2) >> 12) & 7;
+	memd = m68k_areg (regs, dstreg) & ~15;
+	v[0] = get_long (mems);
+	v[1] = get_long (mems + 4);
+	v[2] = get_long (mems + 8);
+	v[3] = get_long (mems + 12);
+	put_long (memd , v[0]);
+	put_long (memd + 4, v[1]);
+	put_long (memd + 8, v[2]);
+	put_long (memd + 12, v[3]);
+	if (srcreg != dstreg)
+		m68k_areg (regs, srcreg) += 16;
+	m68k_areg (regs, dstreg) += 16;
+}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* LPSTOP.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f800_0)(uae_u32 opcode)
+{
+	OpcodeFamily = 127;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_1870; }
+{	uae_u16 sw = get_diword (2);
+	uae_u16 sr;
+	if (sw != (0x100|0x80|0x40)) { Exception (4); goto l_1870; }
+	sr = get_diword (4);
+	if (!(sr & 0x8000)) { Exception (8); goto l_1870; }
+	regs.sr = sr;
+	MakeFromSR();
+	m68k_setstopped();
+	m68k_incpc (6);
+}}l_1870: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+#endif
+
+#ifdef PART_2
+#endif
+
+#ifdef PART_3
+#endif
+
+#ifdef PART_4
+#endif
+
+#ifdef PART_5
+#endif
+
+#ifdef PART_6
+#endif
+
+#ifdef PART_7
+#endif
+
+#ifdef PART_8
+#endif
+
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+#endif
+
+#ifdef PART_2
+#endif
+
+#ifdef PART_3
+#endif
+
+#ifdef PART_4
+/* NBCD.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4800_2)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4810_2)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte (srca, newv);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4818_2)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte (srca, newv);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4820_2)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte (srca, newv);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4828_2)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte (srca, newv);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4830_2)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte (srca, newv);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4838_2)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte (srca, newv);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4839_2)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte (srca, newv);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_5
+#endif
+
+#ifdef PART_6
+/* SBCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8100_2)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8108_2)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte (dsta, newv);
+}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_7
+/* ABCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c100_2)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c108_2)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	put_byte (dsta, newv);
+}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_8
+#endif
+
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+#endif
+
+#ifdef PART_2
+#endif
+
+#ifdef PART_3
+#endif
+
+#ifdef PART_4
+#endif
+
+#ifdef PART_5
+#endif
+
+#ifdef PART_6
+#endif
+
+#ifdef PART_7
+#endif
+
+#ifdef PART_8
+#endif
+
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+/* OR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0030_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s8 dst = get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0070_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s16 dst = get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_00b0_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (6));
+{	uae_s32 dst = get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0130_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_013b_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	tmppc = m68k_getpc () + 2;
+	dsta = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0170_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0230_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s8 dst = get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0270_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s16 dst = get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_02b0_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (6));
+{	uae_s32 dst = get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0430_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0470_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_04b0_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (6));
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0630_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0670_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_06b0_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (6));
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0830_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_083b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	tmppc = m68k_getpc () + 4;
+	dsta = get_disp_ea_000 (tmppc, get_diword (4));
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0870_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08b0_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08f0_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s8 dst = get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a30_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s8 dst = get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a70_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s16 dst = get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab0_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (6));
+{	uae_s32 dst = get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_2
+/* CMP.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c30_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c70_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb0_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (6));
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (8);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1030_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (4);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (4);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1130_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1170_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1180_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1190_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1198_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a8_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b8_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b9_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (6));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11ba_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bc_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = get_dibyte (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fb_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fb_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2030_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2070_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2130_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2170_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2180_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2188_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2190_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2198_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_3
+/* MOVE.L -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a8_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b8_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b9_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (6));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21ba_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bc_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uae_s32 src;
+	src = get_dilong (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (6));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (8);
+}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fb_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fb_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3030_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (4);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (4);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3070_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (4);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (4);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3130_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3170_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3180_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3188_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3190_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3198_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a8_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b8_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b9_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (6));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31ba_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc () + 2;
+	srca += (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bc_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_diword (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fb_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_diword (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fb_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uaecptr dsta;
+	dsta = get_dilong (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4030_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte (srca, newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4070_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word (srca, newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long (srca, newv);
+}}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_40113; }
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+	put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}}	m68k_incpc (4);
+l_40113: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_40114;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_40114;
+	}
+}}}}l_40114: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_40115;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_40115;
+	}
+}}}}l_40115: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4230_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4270_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_42b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.B (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+	MakeSR ();
+	put_word (srca, regs.sr & 0xff);
+}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
+#ifdef PART_4
+/* NEG.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4430_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4470_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpc (4);
+}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fb_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpc (4);
+}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4630_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte (srca, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4670_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word (srca, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long (srca, dst);
+}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_40130; }
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpc (4);
+}}}}l_40130: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fb_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_40131; }
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpc (4);
+}}}}l_40131: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4830_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte (srca, newv);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4870_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	put_long (dsta, srca);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_487b_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	put_long (dsta, srca);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48b0_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 6;  
+{	uae_u16 mask = get_diword (2);
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48f0_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 10; 
+{	uae_u16 mask = get_diword (2);
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a30_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a70_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4ac0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((src) & 0xff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_byte (srca, src);
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad8_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_byte (srca, src);
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_byte (srca, src);
+}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae8_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_byte (srca, src);
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4af0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_byte (srca, src);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4af8_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_byte (srca, src);
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4af9_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_byte (srca, src);
+}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb0_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 6;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cbb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 6;  
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 4;
+	srca = get_disp_ea_000 (tmppc, get_diword (4));
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf0_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 10; 
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (4));
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 10; 
+{	uae_u16 mask = get_diword (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 4;
+	srca = get_disp_ea_000 (tmppc, get_diword (4));
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uaecptr oldpc = m68k_getpc () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_40152;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	put_long (m68k_areg (regs, 7), oldpc);
+}}}l_40152: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ebb_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uaecptr oldpc = m68k_getpc () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_40153;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	put_long (m68k_areg (regs, 7), oldpc);
+}}}l_40153: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_40154;
+	}
+	m68k_setpc (srca);
+}}l_40154: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efb_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_40155;
+	}
+	m68k_setpc (srca);
+}}l_40155: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5030_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5070_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_5
+/* ADDQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_50b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5130_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5170_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_51b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_60ff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (0)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40178;
+	}
+	m68k_incpc (2);
+}l_40178: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BSR.L #.L */
+uae_u32 REGPARAM2 CPUFUNC(op_61ff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+	uae_u32 src = 0xffffffff;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpc () + s, 0, 1, m68k_getpc () + s);
+		goto l_40179;
+	}
+	m68k_do_bsr (m68k_getpc () + 2, s);
+}l_40179: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_62ff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (2)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40180;
+	}
+	m68k_incpc (2);
+}l_40180: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_6
+/* Bcc.L #.L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_63ff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (3)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40181;
+	}
+	m68k_incpc (2);
+}l_40181: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_64ff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (4)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40182;
+	}
+	m68k_incpc (2);
+}l_40182: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_65ff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (5)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40183;
+	}
+	m68k_incpc (2);
+}l_40183: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_66ff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (6)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40184;
+	}
+	m68k_incpc (2);
+}l_40184: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_67ff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (7)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40185;
+	}
+	m68k_incpc (2);
+}l_40185: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_68ff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (8)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40186;
+	}
+	m68k_incpc (2);
+}l_40186: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_69ff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (9)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40187;
+	}
+	m68k_incpc (2);
+}l_40187: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6aff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (10)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40188;
+	}
+	m68k_incpc (2);
+}l_40188: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6bff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (11)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40189;
+	}
+	m68k_incpc (2);
+}l_40189: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6cff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (12)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40190;
+	}
+	m68k_incpc (2);
+}l_40190: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6dff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (13)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40191;
+	}
+	m68k_incpc (2);
+}l_40191: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6eff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (14)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40192;
+	}
+	m68k_incpc (2);
+}l_40192: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6fff_4)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (15)) {
+		exception3i (opcode, m68k_getpc () + 1);
+		goto l_40193;
+	}
+	m68k_incpc (2);
+}l_40193: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8030_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8070_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpc (4);
+		Exception (5);
+		goto l_40200;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (4);
+	}
+}}}}l_40200: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpc (4);
+		Exception (5);
+		goto l_40201;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (4);
+	}
+}}}}l_40201: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8130_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s8 dst = get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8170_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s16 dst = get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_81b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s32 dst = get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpc (4);
+		Exception (5);
+		goto l_40205;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (4);
+}}}}l_40205: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpc (4);
+		Exception (5);
+		goto l_40206;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (4);
+}}}}l_40206: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9030_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9070_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9130_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9170_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_91b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b030_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b070_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_7
+/* CMP.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b130_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s8 dst = get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b170_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s16 dst = get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s32 dst = get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c030_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c070_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 40; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (4);
+}}}}}return 40 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 40; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (4);
+}}}}}return 40 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c130_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s8 dst = get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c170_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s16 dst = get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s32 dst = get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 40; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 40 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 40; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 40 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d030_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d070_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07b_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s16 src = get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d130_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s8 dst = get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d170_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s16 dst = get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_diword (2));
+{	uae_s32 dst = get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fb_4)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc () + 2;
+	srca = get_disp_ea_000 (tmppc, get_diword (2));
+{	uae_s32 src = get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_8
+/* ASRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 data = get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f0_4)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 data = get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+#endif
+
+#ifdef PART_2
+#endif
+
+#ifdef PART_3
+/* MVSR2.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_40c0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40d0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_40d8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+	put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40f0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+	put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40f8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+	put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40f9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+	put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	put_word (srca, regs.sr);
+}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4200_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4210_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4218_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4220_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4228_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4230_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4238_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4239_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte (srca, 0);
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4240_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4250_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4258_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4260_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4268_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4270_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s16 src = get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4278_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s16 src = get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4279_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s16 src = get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word (srca, 0);
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4280_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4290_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4298_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_42b0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s32 src = get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_42b8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s32 src = get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_42b9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s32 src = get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long (srca, 0);
+}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_4
+/* RTE.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e73_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 45;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_50033; }
+{{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+{	uae_s16 sr = get_word (sra);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = get_long (pca);
+	m68k_areg (regs, 7) += 4;
+	regs.sr = sr;
+	if (pc & 1) {
+		exception3i (0x4E73, pc);
+		goto l_50033;
+	}
+	m68k_setpc (pc);
+	MakeFromSR();
+}}}}}}l_50033: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_5
+/* Scc.B Dn (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (0) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (1) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (2) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (3) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (4) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (5) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (6) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (7) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (8) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (9) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (10) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (11) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (12) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (13) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (14) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (15) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe8_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff0_5)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_diword (2));
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff8_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_diword (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff9_5)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_dilong (2);
+{	uae_s8 src = get_byte (srca);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_6
+#endif
+
+#ifdef PART_7
+#endif
+
+#ifdef PART_8
+#endif
+
diff --git a/src/cpu/cpuemu_11.c b/src/cpu/cpuemu_11.c
new file mode 100644
index 0000000..51a88fb
--- /dev/null
+++ b/src/cpu/cpuemu_11.c
@@ -0,0 +1,47370 @@
+#include "main.h"
+#include "sysdeps.h"
+#include "hatari-glue.h"
+#include "maccess.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "cputbl.h"
+#define CPUFUNC(x) x##_ff
+#define SET_CFLG_ALWAYS(x) SET_CFLG(x)
+#define SET_NFLG_ALWAYS(x) SET_NFLG(x)
+#ifdef NOFLAGS
+#include "noflags.h"
+#endif
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0000_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* OR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0010_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* OR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0018_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* OR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0020_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* OR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0028_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* OR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0030_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (6);
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* OR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0038_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* OR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0039_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* ORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_003c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 20; 
+{	MakeSR ();
+{	uae_s16 src = get_word_prefetch (4);
+	src &= 0xFF;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	regs.sr |= src;
+	MakeFromSR();
+}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/0) */
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0040_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* OR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0050_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110011;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_110011: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* OR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0058_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110012;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_110012: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* OR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0060_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110013;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_110013: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* OR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0068_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110014;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (6);
+l_110014: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* OR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0070_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110015;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (6);
+l_110015: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* OR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0078_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110016;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (6);
+l_110016: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* OR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0079_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110017;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (8);
+l_110017: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* ORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_007c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_110018; }
+{	MakeSR ();
+{	uae_s16 src = get_word_prefetch (4);
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	regs.sr |= src;
+	MakeFromSR();
+}}}l_110018: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/0) */
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0080_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* OR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0090_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110020;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_110020: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* OR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0098_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110021;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_110021: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* OR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110022;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_110022: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* OR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110023;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_110023: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* OR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_00b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 34; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110024;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_110024: ;
+return 34 * CYCLE_UNIT / 2 + count_cycles;
+} /* 34 (6/2) */
+
+/* OR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_00b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110025;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_110025: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* OR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_00b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (8) << 16;
+	dsta |= get_word_prefetch (10);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110026;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (12);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (10);
+l_110026: ;
+return 36 * CYCLE_UNIT / 2 + count_cycles;
+} /* 36 (7/2) */
+
+/* BTST.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0100_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* MVPMR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0108_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 16; 
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+{	uae_u16 val;
+	MovepByteNbr=1; val = ((get_byte_prefetch (memp) & 0xff) << 8);
+	MovepByteNbr=2; val += (get_byte_prefetch (memp + 2) & 0xff);
+	MovepByteNbr=0;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* BTST.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0110_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* BTST.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0118_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* BTST.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0120_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* BTST.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0128_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* BTST.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0130_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* BTST.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0138_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* BTST.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0139_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* BTST.B Dn,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_013a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 2;
+	dsta += (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* BTST.B Dn,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_013b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* BTST.B Dn,#.B */
+uae_u32 REGPARAM2 CPUFUNC(op_013c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = (uae_u8)get_word_prefetch (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* BCHG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0140_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 31;
+	if (src > 15) count_cycles += 2 * CYCLE_UNIT / 2;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* MVPMR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0148_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 24; 
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+{	uae_u32 val;
+	MovepByteNbr=1; val = ((get_byte_prefetch (memp) & 0xff) << 24);
+	MovepByteNbr=2; val += ((get_byte_prefetch (memp + 2) & 0xff) << 16);
+	MovepByteNbr=3; val += ((get_byte_prefetch (memp + 4) & 0xff) << 8);
+	MovepByteNbr=4; val += (get_byte_prefetch (memp + 6) & 0xff);
+	MovepByteNbr=0;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (val);
+}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (6/0) */
+
+/* BCHG.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0150_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* BCHG.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0158_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* BCHG.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0160_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* BCHG.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0168_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* BCHG.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0170_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* BCHG.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0178_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* BCHG.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0179_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* BCLR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0180_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 31;
+	if (src > 15) count_cycles += 2 * CYCLE_UNIT / 2;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* MVPRM.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0188_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	MovepByteNbr=1; 	put_byte_prefetch (memp, src >> 8);
+	MovepByteNbr=2; 	put_byte_prefetch (memp + 2, src);
+	MovepByteNbr=0;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* BCLR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0190_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* BCLR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0198_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* BCLR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* BCLR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* BCLR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* BCLR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* BCLR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* BSET.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_01c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 31;
+	if (src > 15) count_cycles += 2 * CYCLE_UNIT / 2;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* MVPRM.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	MovepByteNbr=1; 	put_byte_prefetch (memp, src >> 24);
+	MovepByteNbr=2; 	put_byte_prefetch (memp + 2, src >> 16);
+	MovepByteNbr=3; 	put_byte_prefetch (memp + 4, src >> 8);
+	MovepByteNbr=4; 	put_byte_prefetch (memp + 6, src);
+	MovepByteNbr=0;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (2/4) */
+
+/* BSET.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* BSET.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_01d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* BSET.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* BSET.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* BSET.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* BSET.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* BSET.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0200_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* AND.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0210_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* AND.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0218_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* AND.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0220_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* AND.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0228_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* AND.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0230_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (6);
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* AND.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0238_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* AND.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0239_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* ANDSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_023c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 20; 
+{	MakeSR ();
+{	uae_s16 src = get_word_prefetch (4);
+	src |= 0xFF00;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	regs.sr &= src;
+	MakeFromSR();
+}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/0) */
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0240_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* AND.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0250_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110076;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_110076: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* AND.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0258_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110077;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_110077: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* AND.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0260_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110078;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_110078: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* AND.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0268_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110079;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (6);
+l_110079: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* AND.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0270_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110080;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (6);
+l_110080: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* AND.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0278_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110081;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (6);
+l_110081: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* AND.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0279_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110082;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (8);
+l_110082: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* ANDSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_027c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_110083; }
+{	MakeSR ();
+{	uae_s16 src = get_word_prefetch (4);
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	regs.sr &= src;
+	MakeFromSR();
+}}}l_110083: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/0) */
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0280_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* AND.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0290_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110085;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_110085: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* AND.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0298_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110086;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_110086: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* AND.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110087;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_110087: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* AND.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110088;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_110088: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* AND.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_02b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 34; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110089;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_110089: ;
+return 34 * CYCLE_UNIT / 2 + count_cycles;
+} /* 34 (6/2) */
+
+/* AND.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_02b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110090;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_110090: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* AND.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_02b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (8) << 16;
+	dsta |= get_word_prefetch (10);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110091;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (12);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (10);
+l_110091: ;
+return 36 * CYCLE_UNIT / 2 + count_cycles;
+} /* 36 (7/2) */
+
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0400_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* SUB.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0410_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* SUB.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0418_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* SUB.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0420_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* SUB.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0428_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* SUB.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0430_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* SUB.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0438_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* SUB.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0439_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0440_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* SUB.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0450_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110101;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_110101: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* SUB.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0458_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110102;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_110102: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* SUB.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0460_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110103;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_110103: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* SUB.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0468_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110104;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_110104: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* SUB.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0470_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110105;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_110105: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* SUB.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0478_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110106;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_110106: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* SUB.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0479_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110107;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (8);
+l_110107: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0480_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* SUB.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0490_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110109;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_110109: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* SUB.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0498_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110110;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_110110: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* SUB.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110111;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_110111: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* SUB.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110112;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (8);
+l_110112: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* SUB.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_04b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 34; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110113;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (8);
+l_110113: ;
+return 34 * CYCLE_UNIT / 2 + count_cycles;
+} /* 34 (6/2) */
+
+/* SUB.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_04b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110114;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (8);
+l_110114: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* SUB.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_04b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (8) << 16;
+	dsta |= get_word_prefetch (10);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110115;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (12);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (10);
+l_110115: ;
+return 36 * CYCLE_UNIT / 2 + count_cycles;
+} /* 36 (7/2) */
+
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0600_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* ADD.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0610_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ADD.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0618_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ADD.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0620_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* ADD.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0628_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* ADD.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0630_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* ADD.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0638_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* ADD.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0639_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0640_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* ADD.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0650_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110125;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_110125: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ADD.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0658_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110126;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_110126: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ADD.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0660_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110127;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_110127: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* ADD.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0668_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110128;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_110128: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* ADD.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0670_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110129;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_110129: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* ADD.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0678_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110130;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_110130: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* ADD.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0679_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110131;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (8);
+l_110131: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0680_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* ADD.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0690_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110133;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_110133: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* ADD.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0698_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110134;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_110134: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* ADD.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110135;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_110135: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* ADD.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110136;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (8);
+l_110136: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* ADD.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_06b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 34; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110137;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (8);
+l_110137: ;
+return 34 * CYCLE_UNIT / 2 + count_cycles;
+} /* 34 (6/2) */
+
+/* ADD.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_06b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110138;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (8);
+l_110138: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* ADD.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_06b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (8) << 16;
+	dsta |= get_word_prefetch (10);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110139;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (12);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (10);
+l_110139: ;
+return 36 * CYCLE_UNIT / 2 + count_cycles;
+} /* 36 (7/2) */
+
+/* BTST.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0800_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* BTST.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0810_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* BTST.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0818_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* BTST.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0820_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* BTST.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0828_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* BTST.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0830_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* BTST.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0838_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* BTST.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0839_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (8);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (5/0) */
+
+/* BTST.B #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_083a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* BTST.B #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_083b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	tmppc = m68k_getpci () + 4;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (tmppc, get_word_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* BCHG.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0840_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 31;
+	if (src > 15) count_cycles += 2 * CYCLE_UNIT / 2;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* BCHG.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0850_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* BCHG.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0858_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* BCHG.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0860_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* BCHG.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0868_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* BCHG.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0870_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (6);
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* BCHG.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0878_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* BCHG.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0879_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* BCLR.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0880_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 31;
+	if (src > 15) count_cycles += 2 * CYCLE_UNIT / 2;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (2/0) */
+
+/* BCLR.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0890_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* BCLR.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0898_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* BCLR.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* BCLR.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* BCLR.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (6);
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* BCLR.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* BCLR.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* BSET.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_08c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 31;
+	if (src > 15) count_cycles += 2 * CYCLE_UNIT / 2;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* BSET.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* BSET.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_08d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* BSET.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* BSET.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* BSET.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (6);
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* BSET.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* BSET.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_prefetch (dsta, dst);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* EOR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a00_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* EOR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a10_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* EOR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a18_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* EOR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a20_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* EOR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a28_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* EOR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a30_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (6);
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* EOR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a38_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* EOR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a39_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* EORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a3c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 20; 
+{	MakeSR ();
+{	uae_s16 src = get_word_prefetch (4);
+	src &= 0xFF;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	regs.sr ^= src;
+	MakeFromSR();
+}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/0) */
+
+/* EOR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a40_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* EOR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a50_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110184;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_110184: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* EOR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a58_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110185;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_110185: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* EOR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a60_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110186;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_110186: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* EOR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a68_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110187;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (6);
+l_110187: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* EOR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a70_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110188;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (6);
+l_110188: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* EOR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a78_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110189;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (6);
+l_110189: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* EOR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a79_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110190;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (8);
+l_110190: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* EORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a7c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_110191; }
+{	MakeSR ();
+{	uae_s16 src = get_word_prefetch (4);
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	regs.sr ^= src;
+	MakeFromSR();
+}}}l_110191: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/0) */
+
+/* EOR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a80_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* EOR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a90_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110193;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_110193: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* EOR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a98_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110194;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_110194: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* EOR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110195;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_110195: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* EOR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110196;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_110196: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* EOR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 34; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110197;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_110197: ;
+return 34 * CYCLE_UNIT / 2 + count_cycles;
+} /* 34 (6/2) */
+
+/* EOR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110198;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_110198: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* EOR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (8) << 16;
+	dsta |= get_word_prefetch (10);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110199;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (12);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (10);
+l_110199: ;
+return 36 * CYCLE_UNIT / 2 + count_cycles;
+} /* 36 (7/2) */
+
+#endif
+
+#ifdef PART_2
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c00_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* CMP.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c10_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* CMP.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c18_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* CMP.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c20_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMP.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c28_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* CMP.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c30_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* CMP.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c38_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* CMP.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c39_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (5/0) */
+
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c40_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* CMP.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c50_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110209;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_110209: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* CMP.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c58_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110210;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_110210: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* CMP.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c60_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110211;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_110211: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMP.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c68_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110212;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_110212: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* CMP.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c70_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110213;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_110213: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* CMP.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c78_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110214;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_110214: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* CMP.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c79_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110215;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (8);
+l_110215: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (5/0) */
+
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c80_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMP.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c90_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110217;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_110217: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (5/0) */
+
+/* CMP.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c98_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110218;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_110218: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (5/0) */
+
+/* CMP.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110219;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_110219: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (5/0) */
+
+/* CMP.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110220;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (8);
+l_110220: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (6/0) */
+
+/* CMP.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 26; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110221;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (8);
+l_110221: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (6/0) */
+
+/* CMP.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110222;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (8);
+l_110222: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (6/0) */
+
+/* CMP.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (8) << 16;
+	dsta |= get_word_prefetch (10);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110223;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (12);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (10);
+l_110223: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (7/0) */
+
+/* MOVE.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1000_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* MOVE.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1010_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* MOVE.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1018_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* MOVE.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1020_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* MOVE.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1028_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVE.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1030_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* MOVE.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1038_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVE.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1039_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* MOVE.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVE.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* MOVE.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* MOVE.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1080_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* MOVE.B (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1090_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.B (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1098_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.B -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* MOVE.B (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.B (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.B (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10ba_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* MOVE.B (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.B -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* MOVE.B (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.B (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.B (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1100_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* MOVE.B (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1110_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (2);
+}}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.B (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1118_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (2);
+}}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1120_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (2);
+}}}}return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* MOVE.B (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1128_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1130_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+}}}}return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.B (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1138_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1139_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.B (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+}}}}return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1140_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.B (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1150_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1158_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1160_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.B (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1168_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1170_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.B (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1178_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.B (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1179_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (8);
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* MOVE.B (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1180_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* MOVE.B (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1190_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1198_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.B -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/1) */
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/1) */
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (8));
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (5/1) */
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11ba_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/1) */
+
+/* MOVE.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.B (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.B (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.B (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.B (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (8);
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* MOVE.B (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.B (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.B (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.B -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (6);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.B (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (5/1) */
+
+/* MOVE.B (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* MOVE.B (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (8) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 10;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (10);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (6/1) */
+
+/* MOVE.B (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (5/1) */
+
+/* MOVE.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_prefetch (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2000_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* MOVE.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2008_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* MOVE.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2010_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110314;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110314: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVE.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2018_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110315;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110315: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVE.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2020_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110316;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110316: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* MOVE.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2028_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110317;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110317: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* MOVE.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2030_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110318;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110318: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* MOVE.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2038_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110319;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110319: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* MOVE.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2039_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110320;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110320: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (5/0) */
+
+/* MOVE.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110321;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110321: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* MOVE.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110322;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110322: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* MOVE.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVEA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2040_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* MOVEA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2048_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* MOVEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2050_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110326;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110326: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVEA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2058_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110327;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110327: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVEA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2060_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110328;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110328: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* MOVEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2068_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110329;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110329: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* MOVEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2070_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110330;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110330: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* MOVEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2078_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110331;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110331: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* MOVEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2079_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110332;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110332: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (5/0) */
+
+/* MOVEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110333;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110333: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* MOVEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110334;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110334: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* MOVEA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_207c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVE.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2080_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110336;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110336: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (1/2) */
+
+/* MOVE.L An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2088_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110337;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110337: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (1/2) */
+
+/* MOVE.L (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2090_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110338;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110338;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110338: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* MOVE.L (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2098_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110339;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110339;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110339: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* MOVE.L -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110340;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110340;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110340: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (3/2) */
+
+/* MOVE.L (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110341;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110341;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110341: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110342;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110342;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110342: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* MOVE.L (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110343;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110343;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110343: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110344;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110344;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110344: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MOVE.L (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20ba_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110345;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110345;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110345: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110346;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110346;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110346: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* MOVE.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110347;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110347: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* MOVE.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110348;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110348: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (1/2) */
+
+/* MOVE.L An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110349;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110349: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (1/2) */
+
+/* MOVE.L (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110350;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110350;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110350: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* MOVE.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110351;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110351;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110351: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* MOVE.L -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110352;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110352;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110352: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (3/2) */
+
+/* MOVE.L (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110353;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110353;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110353: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110354;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110354;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110354: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* MOVE.L (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110355;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110355;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110355: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110356;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110356;
+	}
+{	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110356: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MOVE.L (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110357;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110357;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110357: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110358;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110358;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110358: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* MOVE.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110359;
+	}
+{	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110359: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* MOVE.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2100_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110360;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+}}}}l_110360: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (1/2) */
+
+/* MOVE.L An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2108_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110361;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+}}}}l_110361: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (1/2) */
+
+/* MOVE.L (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2110_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110362;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110362;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+}}}}}}l_110362: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* MOVE.L (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2118_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110363;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110363;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+}}}}}}l_110363: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* MOVE.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2120_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110364;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110364;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (2);
+}}}}}}l_110364: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (3/2) */
+
+/* MOVE.L (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2128_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110365;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110365;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+}}}}}}l_110365: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2130_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110366;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110366;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+}}}}}}l_110366: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* MOVE.L (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2138_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110367;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110367;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+}}}}}}l_110367: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2139_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110368;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110368;
+	}
+{	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+}}}}}}l_110368: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MOVE.L (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110369;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110369;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+}}}}}}l_110369: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110370;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110370;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+}}}}}}l_110370: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* MOVE.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110371;
+	}
+{	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+}}}}l_110371: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* MOVE.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2140_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110372;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110372: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* MOVE.L An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2148_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110373;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110373: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* MOVE.L (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2150_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110374;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110374;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110374: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2158_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110375;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110375;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110375: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2160_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110376;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110376;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110376: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* MOVE.L (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2168_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110377;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110377;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110377: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2170_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110378;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110378;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110378: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* MOVE.L (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2178_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110379;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110379;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110379: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MOVE.L (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2179_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110380;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110380;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110380: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* MOVE.L (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110381;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110381;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110381: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110382;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110382;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110382: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* MOVE.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110383;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110383: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2180_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110384;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110384: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (2/2) */
+
+/* MOVE.L An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2188_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110385;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110385: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (2/2) */
+
+/* MOVE.L (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2190_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110386;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110386;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110386: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2198_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110387;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110387;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110387: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+#endif
+
+#ifdef PART_3
+/* MOVE.L -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110388;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110388;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110388: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (4/2) */
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110389;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110389;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110389: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110390;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110390;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110390: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (5/2) */
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110391;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110391;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110391: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 34; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110392;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110392;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110392: ;
+return 34 * CYCLE_UNIT / 2 + count_cycles;
+} /* 34 (6/2) */
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21ba_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110393;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110393;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110393: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110394;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110394;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110394: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (5/2) */
+
+/* MOVE.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110395;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110395: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* MOVE.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110396;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110396: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* MOVE.L An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110397;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110397: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* MOVE.L (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110398;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110398;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110398: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110399;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110399;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110399: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110400;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110400;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110400: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* MOVE.L (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110401;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110401;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110401: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110402;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110402;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110402: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* MOVE.L (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110403;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110403;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110403: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MOVE.L (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110404;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110404;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110404: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* MOVE.L (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110405;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110405;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110405: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110406;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110406;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110406: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* MOVE.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110407;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110407: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* MOVE.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110408;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110408: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* MOVE.L An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110409;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110409: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* MOVE.L (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110410;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110410;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110410: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MOVE.L (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110411;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110411;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110411: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MOVE.L -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110412;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110412;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (6);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110412: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* MOVE.L (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110413;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110413;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110413: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 34; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110414;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110414;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110414: ;
+return 34 * CYCLE_UNIT / 2 + count_cycles;
+} /* 34 (6/2) */
+
+/* MOVE.L (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110415;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110415;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110415: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* MOVE.L (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 36; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110416;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (8) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (10);
+		exception3_write(opcode, dsta);
+		goto l_110416;
+	}
+{	bus_error_offset = 10;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (10);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110416: ;
+return 36 * CYCLE_UNIT / 2 + count_cycles;
+} /* 36 (7/2) */
+
+/* MOVE.L (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110417;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110417;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110417: ;
+return 32 * CYCLE_UNIT / 2 + count_cycles;
+} /* 32 (6/2) */
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 34; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110418;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110418;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110418: ;
+return 34 * CYCLE_UNIT / 2 + count_cycles;
+} /* 34 (6/2) */
+
+/* MOVE.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (8) << 16;
+	dsta |= get_word_prefetch (10);
+	if (dsta & 1) {
+	m68k_incpci (10);
+		exception3_write(opcode, dsta);
+		goto l_110419;
+	}
+{	bus_error_offset = 10;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_word_prefetch (dsta, src >> 16); put_word_prefetch (dsta + 2, src);
+	m68k_incpci (10);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110419: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MOVE.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3000_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* MOVE.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3008_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* MOVE.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3010_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110422;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110422: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* MOVE.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3018_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110423;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110423: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* MOVE.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3020_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110424;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110424: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* MOVE.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3028_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110425;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110425: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVE.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3030_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110426;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110426: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* MOVE.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3038_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110427;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110427: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVE.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3039_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110428;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110428: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* MOVE.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110429;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110429: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVE.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110430;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110430: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* MOVE.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* MOVEA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3040_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* MOVEA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3048_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* MOVEA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3050_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110434;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110434: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* MOVEA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3058_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110435;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110435: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* MOVEA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3060_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110436;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110436: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* MOVEA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3068_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110437;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110437: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVEA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3070_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110438;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110438: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* MOVEA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3078_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110439;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110439: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVEA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3079_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110440;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110440: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* MOVEA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110441;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110441: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MOVEA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110442;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110442: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* MOVEA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_307c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* MOVE.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3080_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110444;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110444: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* MOVE.W An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3088_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110445;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110445: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* MOVE.W (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3090_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110446;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110446;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110446: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.W (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3098_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110447;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110447;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110447: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.W -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110448;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110448;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110448: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* MOVE.W (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110449;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110449;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110449: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110450;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110450;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110450: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.W (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110451;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110451;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110451: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110452;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110452;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110452: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.W (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30ba_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110453;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110453;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110453: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110454;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110454;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110454: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110455;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110455: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110456;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110456: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* MOVE.W An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110457;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110457: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* MOVE.W (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110458;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110458;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110458: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110459;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110459;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110459: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.W -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110460;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110460;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110460: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* MOVE.W (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110461;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110461;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110461: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110462;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110462;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110462: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.W (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110463;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110463;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110463: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110464;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110464;
+	}
+{	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110464: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.W (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110465;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110465;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110465: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110466;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110466;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110466: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110467;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110467: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3100_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110468;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+}}}}l_110468: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* MOVE.W An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3108_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110469;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+}}}}l_110469: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* MOVE.W (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3110_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110470;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110470;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+}}}}}}l_110470: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.W (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3118_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110471;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110471;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+}}}}}}l_110471: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3120_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110472;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110472;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (2);
+}}}}}}l_110472: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* MOVE.W (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3128_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110473;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110473;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+}}}}}}l_110473: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3130_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110474;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110474;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+}}}}}}l_110474: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.W (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3138_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110475;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110475;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+}}}}}}l_110475: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3139_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110476;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110476;
+	}
+{	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+}}}}}}l_110476: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.W (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110477;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110477;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+}}}}}}l_110477: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110478;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110478;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+}}}}}}l_110478: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110479;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+}}}}l_110479: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3140_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110480;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110480: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.W An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3148_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110481;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110481: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.W (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3150_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110482;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110482;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110482: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3158_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110483;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110483;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110483: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3160_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110484;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110484;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110484: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.W (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3168_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110485;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110485;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110485: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3170_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110486;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110486;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110486: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.W (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3178_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110487;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110487;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110487: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.W (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3179_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110488;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110488;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110488: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* MOVE.W (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110489;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110489;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110489: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110490;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110490;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110490: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110491;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110491: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3180_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110492;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110492: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* MOVE.W An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3188_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110493;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110493: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* MOVE.W (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3190_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110494;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110494;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110494: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3198_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110495;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110495;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110495: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.W -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110496;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110496;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110496: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/1) */
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110497;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110497;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110497: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110498;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110498;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110498: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/1) */
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110499;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110499;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110499: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110500;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110500;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110500: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (5/1) */
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31ba_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110501;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110501;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110501: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110502;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110502;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110502: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/1) */
+
+/* MOVE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110503;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110503: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110504;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110504: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.W An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110505;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110505: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* MOVE.W (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110506;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110506;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110506: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110507;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110507;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110507: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110508;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110508;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110508: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* MOVE.W (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110509;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110509;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110509: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110510;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110510;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110510: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.W (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110511;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110511;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110511: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.W (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110512;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110512;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110512: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* MOVE.W (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110513;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110513;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110513: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110514;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110514;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110514: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110515;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110515: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110516;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110516: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110517;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110517: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* MOVE.W (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110518;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110518;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110518: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.W (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110519;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110519;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110519: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* MOVE.W -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110520;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110520;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (6);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110520: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MOVE.W (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110521;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110521;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110521: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110522;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110522;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110522: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (5/1) */
+
+/* MOVE.W (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110523;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110523;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110523: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* MOVE.W (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110524;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (8) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (10);
+		exception3_write(opcode, dsta);
+		goto l_110524;
+	}
+{	bus_error_offset = 10;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (10);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110524: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (6/1) */
+
+/* MOVE.W (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110525;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110525;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110525: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/1) */
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110526;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110526;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (8);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}l_110526: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (5/1) */
+
+/* MOVE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (6) << 16;
+	dsta |= get_word_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110527;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_prefetch (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110527: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* NEGX.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4000_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* NEGX.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4010_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_prefetch (srca, newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* NEGX.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4018_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_prefetch (srca, newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* NEGX.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4020_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_prefetch (srca, newv);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* NEGX.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4028_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_prefetch (srca, newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* NEGX.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4030_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_prefetch (srca, newv);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* NEGX.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4038_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_prefetch (srca, newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* NEGX.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4039_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_prefetch (srca, newv);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* NEGX.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4040_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* NEGX.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4050_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110537;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_prefetch (srca, newv);
+}}}}}}	m68k_incpci (2);
+l_110537: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* NEGX.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4058_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110538;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_prefetch (srca, newv);
+}}}}}}	m68k_incpci (2);
+l_110538: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* NEGX.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4060_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110539;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_prefetch (srca, newv);
+}}}}}}	m68k_incpci (2);
+l_110539: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* NEGX.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4068_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110540;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_prefetch (srca, newv);
+}}}}}}	m68k_incpci (4);
+l_110540: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* NEGX.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4070_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110541;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_prefetch (srca, newv);
+}}}}}}	m68k_incpci (4);
+l_110541: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* NEGX.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4078_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110542;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_prefetch (srca, newv);
+}}}}}}	m68k_incpci (4);
+l_110542: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* NEGX.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4079_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110543;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_prefetch (srca, newv);
+}}}}}}	m68k_incpci (6);
+l_110543: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* NEGX.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4080_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (newv);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* NEGX.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4090_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110545;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_word_prefetch (srca + 2, newv); put_word_prefetch (srca, newv >> 16);
+}}}}}}	m68k_incpci (2);
+l_110545: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* NEGX.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4098_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110546;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_word_prefetch (srca + 2, newv); put_word_prefetch (srca, newv >> 16);
+}}}}}}	m68k_incpci (2);
+l_110546: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* NEGX.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110547;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_word_prefetch (srca + 2, newv); put_word_prefetch (srca, newv >> 16);
+}}}}}}	m68k_incpci (2);
+l_110547: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (3/2) */
+
+/* NEGX.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110548;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_word_prefetch (srca + 2, newv); put_word_prefetch (srca, newv >> 16);
+}}}}}}	m68k_incpci (4);
+l_110548: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* NEGX.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110549;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_word_prefetch (srca + 2, newv); put_word_prefetch (srca, newv >> 16);
+}}}}}}	m68k_incpci (4);
+l_110549: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* NEGX.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110550;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_word_prefetch (srca + 2, newv); put_word_prefetch (srca, newv >> 16);
+}}}}}}	m68k_incpci (4);
+l_110550: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* NEGX.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110551;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_word_prefetch (srca + 2, newv); put_word_prefetch (srca, newv >> 16);
+}}}}}}	m68k_incpci (6);
+l_110551: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MVSR2.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_40c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{if (!regs.s) { Exception (8); goto l_110552; }
+{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}}	m68k_incpci (2);
+l_110552: ;
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* MVSR2.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_110553; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110553;
+	}
+{	bus_error_offset = 4;
+	put_word_prefetch (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr);
+}}}}	m68k_incpci (2);
+l_110553: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (1/2) */
+
+/* MVSR2.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_40d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_110554; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110554;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += 2;
+	put_word_prefetch (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr);
+}}}}	m68k_incpci (2);
+l_110554: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (1/2) */
+
+/* MVSR2.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 14; 
+{if (!regs.s) { Exception (8); goto l_110555; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110555;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+	put_word_prefetch (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr);
+}}}}	m68k_incpci (2);
+l_110555: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (1/2) */
+
+/* MVSR2.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_110556; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110556;
+	}
+{	bus_error_offset = 4;
+	put_word_prefetch (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr);
+}}}}	m68k_incpci (4);
+l_110556: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* MVSR2.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 18; 
+{if (!regs.s) { Exception (8); goto l_110557; }
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110557;
+	}
+{	bus_error_offset = 4;
+	put_word_prefetch (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr);
+}}}}	m68k_incpci (4);
+l_110557: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (2/2) */
+
+/* MVSR2.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_110558; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110558;
+	}
+{	bus_error_offset = 4;
+	put_word_prefetch (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr);
+}}}}	m68k_incpci (4);
+l_110558: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* MVSR2.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_110559; }
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110559;
+	}
+{	bus_error_offset = 6;
+	put_word_prefetch (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr);
+}}}}	m68k_incpci (6);
+l_110559: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* CHK.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4180_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_110560;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_110560;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110560: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/0) */
+
+/* CHK.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4190_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110561;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_110561;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_110561;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110561: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/0) */
+
+/* CHK.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4198_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110562;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_110562;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_110562;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110562: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/0) */
+
+/* CHK.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110563;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_110563;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_110563;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110563: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/0) */
+
+/* CHK.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110564;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_110564;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_110564;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110564: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/0) */
+
+/* CHK.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110565;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_110565;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_110565;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110565: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/0) */
+
+/* CHK.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110566;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_110566;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_110566;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110566: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/0) */
+
+/* CHK.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110567;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_110567;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_110567;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110567: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/0) */
+
+/* CHK.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41ba_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110568;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_110568;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_110568;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110568: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/0) */
+
+/* CHK.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110569;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_110569;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_110569;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110569: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/0) */
+
+/* CHK.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_110570;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_110570;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110570: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/0) */
+
+/* LEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* LEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* LEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/0) */
+
+/* LEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* LEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* LEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* LEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/0) */
+
+/* CLR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4200_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* CLR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4210_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_prefetch (srca, 0);
+}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* CLR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4218_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_prefetch (srca, 0);
+}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* CLR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4220_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_prefetch (srca, 0);
+}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* CLR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4228_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_prefetch (srca, 0);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4230_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_prefetch (srca, 0);
+}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* CLR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4238_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_prefetch (srca, 0);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* CLR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4239_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_prefetch (srca, 0);
+}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* CLR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4240_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* CLR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4250_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110587;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_prefetch (srca, 0);
+}}}	m68k_incpci (2);
+l_110587: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* CLR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4258_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110588;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_prefetch (srca, 0);
+}}}	m68k_incpci (2);
+l_110588: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* CLR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4260_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110589;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_prefetch (srca, 0);
+}}}	m68k_incpci (2);
+l_110589: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* CLR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4268_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110590;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_prefetch (srca, 0);
+}}}	m68k_incpci (4);
+l_110590: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4270_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110591;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_prefetch (srca, 0);
+}}}	m68k_incpci (4);
+l_110591: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* CLR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4278_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110592;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_prefetch (srca, 0);
+}}}	m68k_incpci (4);
+l_110592: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* CLR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4279_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110593;
+	}
+{	bus_error_offset = 6;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_prefetch (srca, 0);
+}}}	m68k_incpci (6);
+l_110593: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* CLR.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4280_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* CLR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4290_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110595;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_word_prefetch (srca + 2, 0); put_word_prefetch (srca, 0 >> 16);
+}}}	m68k_incpci (2);
+l_110595: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (1/2) */
+
+/* CLR.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4298_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110596;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_word_prefetch (srca + 2, 0); put_word_prefetch (srca, 0 >> 16);
+}}}	m68k_incpci (2);
+l_110596: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (1/2) */
+
+/* CLR.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110597;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_word_prefetch (srca + 2, 0); put_word_prefetch (srca, 0 >> 16);
+}}}	m68k_incpci (2);
+l_110597: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (1/2) */
+
+/* CLR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110598;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_word_prefetch (srca + 2, 0); put_word_prefetch (srca, 0 >> 16);
+}}}	m68k_incpci (4);
+l_110598: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_42b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110599;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_word_prefetch (srca + 2, 0); put_word_prefetch (srca, 0 >> 16);
+}}}	m68k_incpci (4);
+l_110599: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (2/2) */
+
+/* CLR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_42b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110600;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_word_prefetch (srca + 2, 0); put_word_prefetch (srca, 0 >> 16);
+}}}	m68k_incpci (4);
+l_110600: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* CLR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_42b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110601;
+	}
+{	bus_error_offset = 6;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_word_prefetch (srca + 2, 0); put_word_prefetch (srca, 0 >> 16);
+}}}	m68k_incpci (6);
+l_110601: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* MVSR2.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
+}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+#endif
+/* MVSR2.B (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110603;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr & 0xff);
+}}}	m68k_incpci (2);
+l_110603: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+#endif
+/* MVSR2.B (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110604;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr & 0xff);
+}}}	m68k_incpci (2);
+l_110604: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+#endif
+/* MVSR2.B -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110605;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr & 0xff);
+}}}	m68k_incpci (2);
+l_110605: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+#endif
+/* MVSR2.B (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110606;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr & 0xff);
+}}}	m68k_incpci (4);
+l_110606: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+#endif
+/* MVSR2.B (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110607;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr & 0xff);
+}}}	m68k_incpci (4);
+l_110607: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+#endif
+/* MVSR2.B (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_110608;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr & 0xff);
+}}}	m68k_incpci (4);
+l_110608: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+#endif
+/* MVSR2.B (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110609;
+	}
+{	bus_error_offset = 6;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr & 0xff);
+}}}	m68k_incpci (6);
+l_110609: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+#endif
+/* NEG.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4400_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+#endif
+
+#ifdef PART_4
+/* NEG.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4410_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* NEG.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4418_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* NEG.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4420_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* NEG.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4428_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* NEG.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4430_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* NEG.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4438_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* NEG.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4439_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (srca, dst);
+}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* NEG.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4440_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* NEG.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4450_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110619;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (srca, dst);
+}}}}}}}	m68k_incpci (2);
+l_110619: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* NEG.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4458_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110620;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (srca, dst);
+}}}}}}}	m68k_incpci (2);
+l_110620: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* NEG.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4460_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110621;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (srca, dst);
+}}}}}}}	m68k_incpci (2);
+l_110621: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* NEG.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4468_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110622;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (srca, dst);
+}}}}}}}	m68k_incpci (4);
+l_110622: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* NEG.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4470_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110623;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (srca, dst);
+}}}}}}}	m68k_incpci (4);
+l_110623: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* NEG.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4478_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110624;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (srca, dst);
+}}}}}}}	m68k_incpci (4);
+l_110624: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* NEG.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4479_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110625;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (srca, dst);
+}}}}}}}	m68k_incpci (6);
+l_110625: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* NEG.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4480_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* NEG.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4490_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110627;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (srca + 2, dst); put_word_prefetch (srca, dst >> 16);
+}}}}}}}	m68k_incpci (2);
+l_110627: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* NEG.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4498_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110628;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (srca + 2, dst); put_word_prefetch (srca, dst >> 16);
+}}}}}}}	m68k_incpci (2);
+l_110628: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* NEG.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110629;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (srca + 2, dst); put_word_prefetch (srca, dst >> 16);
+}}}}}}}	m68k_incpci (2);
+l_110629: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (3/2) */
+
+/* NEG.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110630;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (srca + 2, dst); put_word_prefetch (srca, dst >> 16);
+}}}}}}}	m68k_incpci (4);
+l_110630: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* NEG.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110631;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (srca + 2, dst); put_word_prefetch (srca, dst >> 16);
+}}}}}}}	m68k_incpci (4);
+l_110631: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* NEG.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110632;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (srca + 2, dst); put_word_prefetch (srca, dst >> 16);
+}}}}}}}	m68k_incpci (4);
+l_110632: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* NEG.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110633;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (srca + 2, dst); put_word_prefetch (srca, dst >> 16);
+}}}}}}}	m68k_incpci (6);
+l_110633: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MV2SR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_44c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpci (2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* MV2SR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110635;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpci (2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110635: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* MV2SR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_44d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110636;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpci (2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110636: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* MV2SR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110637;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpci (2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110637: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/0) */
+
+/* MV2SR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110638;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110638: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* MV2SR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110639;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110639: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/0) */
+
+/* MV2SR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110640;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110640: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* MV2SR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110641;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpci (6);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110641: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/0) */
+
+/* MV2SR.B (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110642;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110642: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* MV2SR.B (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 22; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110643;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}l_110643: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/0) */
+
+/* MV2SR.B #.B */
+uae_u32 REGPARAM2 CPUFUNC(op_44fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_prefetch (4);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* NOT.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4600_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* NOT.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4610_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte_prefetch (srca, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* NOT.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4618_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte_prefetch (srca, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* NOT.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4620_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte_prefetch (srca, dst);
+}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* NOT.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4628_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte_prefetch (srca, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* NOT.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4630_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte_prefetch (srca, dst);
+}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* NOT.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4638_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte_prefetch (srca, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* NOT.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4639_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte_prefetch (srca, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* NOT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4640_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* NOT.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4650_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110654;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word_prefetch (srca, dst);
+}}}}}	m68k_incpci (2);
+l_110654: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* NOT.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4658_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110655;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word_prefetch (srca, dst);
+}}}}}	m68k_incpci (2);
+l_110655: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* NOT.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4660_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110656;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word_prefetch (srca, dst);
+}}}}}	m68k_incpci (2);
+l_110656: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* NOT.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4668_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110657;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word_prefetch (srca, dst);
+}}}}}	m68k_incpci (4);
+l_110657: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* NOT.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4670_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110658;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word_prefetch (srca, dst);
+}}}}}	m68k_incpci (4);
+l_110658: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* NOT.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4678_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110659;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word_prefetch (srca, dst);
+}}}}}	m68k_incpci (4);
+l_110659: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* NOT.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4679_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110660;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word_prefetch (srca, dst);
+}}}}}	m68k_incpci (6);
+l_110660: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* NOT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4680_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* NOT.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4690_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110662;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_word_prefetch (srca + 2, dst); put_word_prefetch (srca, dst >> 16);
+}}}}}	m68k_incpci (2);
+l_110662: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* NOT.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4698_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110663;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_word_prefetch (srca + 2, dst); put_word_prefetch (srca, dst >> 16);
+}}}}}	m68k_incpci (2);
+l_110663: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* NOT.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110664;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_word_prefetch (srca + 2, dst); put_word_prefetch (srca, dst >> 16);
+}}}}}	m68k_incpci (2);
+l_110664: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (3/2) */
+
+/* NOT.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110665;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_word_prefetch (srca + 2, dst); put_word_prefetch (srca, dst >> 16);
+}}}}}	m68k_incpci (4);
+l_110665: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* NOT.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110666;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_word_prefetch (srca + 2, dst); put_word_prefetch (srca, dst >> 16);
+}}}}}	m68k_incpci (4);
+l_110666: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* NOT.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110667;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_word_prefetch (srca + 2, dst); put_word_prefetch (srca, dst >> 16);
+}}}}}	m68k_incpci (4);
+l_110667: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* NOT.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110668;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_word_prefetch (srca + 2, dst); put_word_prefetch (srca, dst >> 16);
+}}}}}	m68k_incpci (6);
+l_110668: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MV2SR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_46c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_110669; }
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpci (2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110669: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* MV2SR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_110670; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110670;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpci (2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110670: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* MV2SR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_46d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_110671; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110671;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpci (2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110671: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* MV2SR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 18; 
+{if (!regs.s) { Exception (8); goto l_110672; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110672;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpci (2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110672: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/0) */
+
+/* MV2SR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_110673; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110673;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110673: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* MV2SR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 22; 
+{if (!regs.s) { Exception (8); goto l_110674; }
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110674;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110674: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/0) */
+
+/* MV2SR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_110675; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110675;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110675: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* MV2SR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_110676; }
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110676;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpci (6);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110676: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (5/0) */
+
+/* MV2SR.W (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_110677; }
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110677;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110677: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* MV2SR.W (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 22; 
+{if (!regs.s) { Exception (8); goto l_110678; }
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110678;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110678: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/0) */
+
+/* MV2SR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_46fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_110679; }
+{{	uae_s16 src = get_word_prefetch (4);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110679: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* NBCD.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4800_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* NBCD.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4810_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_prefetch (srca, newv);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* NBCD.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4818_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_prefetch (srca, newv);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* NBCD.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4820_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_prefetch (srca, newv);
+}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* NBCD.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4828_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_prefetch (srca, newv);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* NBCD.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4830_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_prefetch (srca, newv);
+}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* NBCD.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4838_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_prefetch (srca, newv);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* NBCD.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4839_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_prefetch (srca, newv);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* SWAP.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4840_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 34;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* PEA.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4850_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_110689;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta, srca >> 16); put_word_prefetch (dsta + 2, srca);
+}}}}	m68k_incpci (2);
+l_110689: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (1/2) */
+
+/* PEA.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4868_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110690;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, 7) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, srca >> 16); put_word_prefetch (dsta + 2, srca);
+}}}}	m68k_incpci (4);
+l_110690: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* PEA.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4870_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110691;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, 7) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, srca >> 16); put_word_prefetch (dsta + 2, srca);
+}}}}	m68k_incpci (4);
+l_110691: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (2/2) */
+
+/* PEA.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4878_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110692;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, 7) = dsta;
+	put_word_prefetch (dsta, srca >> 16); put_word_prefetch (dsta + 2, srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+}}}}	m68k_incpci (4);
+l_110692: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* PEA.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4879_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_110693;
+	}
+{	bus_error_offset = 8;
+	m68k_areg (regs, 7) = dsta;
+	put_word_prefetch (dsta, srca >> 16); put_word_prefetch (dsta + 2, srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110693: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* PEA.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_487a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110694;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, 7) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, srca >> 16); put_word_prefetch (dsta + 2, srca);
+}}}}	m68k_incpci (4);
+l_110694: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* PEA.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_487b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 22; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_110695;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, 7) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, srca >> 16); put_word_prefetch (dsta + 2, srca);
+}}}}	m68k_incpci (4);
+l_110695: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (2/2) */
+
+/* EXT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4880_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 dst = (uae_s16)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* MVMLE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4890_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_prefetch (4);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110697;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_prefetch (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		put_word_prefetch (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+}}}}	m68k_incpci (4);
+l_110697: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (2/0) */
+
+/* MVMLE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_prefetch (4);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110698;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	while (amask) {
+		srca -= 2;
+		put_word_prefetch (srca, m68k_areg (regs, movem_index2[amask]));
+	amask = movem_next[amask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	while (dmask) {
+		srca -= 2;
+		put_word_prefetch (srca, m68k_dreg (regs, movem_index2[dmask]));
+		dmask = movem_next[dmask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	m68k_areg (regs, dstreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+}}}}	m68k_incpci (4);
+l_110698: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (2/0) */
+
+/* MVMLE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_prefetch (4);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110699;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_prefetch (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		put_word_prefetch (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110699: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (3/0) */
+
+/* MVMLE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 14; 
+{	uae_u16 mask = get_word_prefetch (4);
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110700;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_prefetch (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		put_word_prefetch (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110700: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14+ (3/0) */
+
+/* MVMLE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_prefetch (4);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110701;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_prefetch (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		put_word_prefetch (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110701: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (3/0) */
+
+/* MVMLE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_prefetch (4);
+{	uaecptr srca;
+	srca = get_word_prefetch (6) << 16;
+	srca |= get_word_prefetch (8);
+	if (srca & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, srca);
+		goto l_110702;
+	}
+{	bus_error_offset = 8;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_prefetch (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		put_word_prefetch (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+}}}}	m68k_incpci (8);
+l_110702: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16+ (4/0) */
+
+/* EXT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_48c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 dst = (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* MVMLE.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_prefetch (4);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110704;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_prefetch (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16);
+		put_word_prefetch (srca + 2, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		put_word_prefetch (srca, m68k_areg (regs, movem_index1[amask]) >> 16);
+		put_word_prefetch (srca + 2, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+}}}}	m68k_incpci (4);
+l_110704: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (2/0) */
+
+/* MVMLE.L #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_prefetch (4);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110705;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	while (amask) {
+		srca -= 4;
+		put_word_prefetch (srca, m68k_areg (regs, movem_index2[amask]) >> 16);
+		put_word_prefetch (srca + 2, m68k_areg (regs, movem_index2[amask]));
+		amask = movem_next[amask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	while (dmask) {
+		srca -= 4;
+		put_word_prefetch (srca, m68k_dreg (regs, movem_index2[dmask]) >> 16);
+		put_word_prefetch (srca + 2, m68k_dreg (regs, movem_index2[dmask]));
+		dmask = movem_next[dmask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	m68k_areg (regs, dstreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+}}}}	m68k_incpci (4);
+l_110705: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (2/0) */
+
+/* MVMLE.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_prefetch (4);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110706;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_prefetch (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16);
+		put_word_prefetch (srca + 2, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		put_word_prefetch (srca, m68k_areg (regs, movem_index1[amask]) >> 16);
+		put_word_prefetch (srca + 2, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110706: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (3/0) */
+
+/* MVMLE.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 14; 
+{	uae_u16 mask = get_word_prefetch (4);
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110707;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_prefetch (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16);
+		put_word_prefetch (srca + 2, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		put_word_prefetch (srca, m68k_areg (regs, movem_index1[amask]) >> 16);
+		put_word_prefetch (srca + 2, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110707: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14+ (3/0) */
+
+/* MVMLE.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_prefetch (4);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110708;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_prefetch (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16);
+		put_word_prefetch (srca + 2, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		put_word_prefetch (srca, m68k_areg (regs, movem_index1[amask]) >> 16);
+		put_word_prefetch (srca + 2, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110708: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (3/0) */
+
+/* MVMLE.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_prefetch (4);
+{	uaecptr srca;
+	srca = get_word_prefetch (6) << 16;
+	srca |= get_word_prefetch (8);
+	if (srca & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, srca);
+		goto l_110709;
+	}
+{	bus_error_offset = 8;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_prefetch (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16);
+		put_word_prefetch (srca + 2, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		put_word_prefetch (srca, m68k_areg (regs, movem_index1[amask]) >> 16);
+		put_word_prefetch (srca + 2, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+}}}}	m68k_incpci (8);
+l_110709: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16+ (4/0) */
+
+/* TST.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a00_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* TST.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a10_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* TST.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a18_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* TST.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a20_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* TST.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a28_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* TST.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a30_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* TST.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a38_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* TST.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a39_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* TST.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a40_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* TST.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a50_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110719;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}	m68k_incpci (2);
+l_110719: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* TST.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a58_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110720;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}	m68k_incpci (2);
+l_110720: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* TST.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a60_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110721;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}	m68k_incpci (2);
+l_110721: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* TST.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a68_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110722;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}	m68k_incpci (4);
+l_110722: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* TST.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a70_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110723;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}	m68k_incpci (4);
+l_110723: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* TST.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a78_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110724;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}	m68k_incpci (4);
+l_110724: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* TST.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a79_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110725;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}	m68k_incpci (6);
+l_110725: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* TST.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a80_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* TST.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a90_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110727;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}	m68k_incpci (2);
+l_110727: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* TST.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a98_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110728;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}	m68k_incpci (2);
+l_110728: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* TST.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110729;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}	m68k_incpci (2);
+l_110729: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* TST.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110730;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}	m68k_incpci (4);
+l_110730: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* TST.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_110731;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}	m68k_incpci (4);
+l_110731: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* TST.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_110732;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}	m68k_incpci (4);
+l_110732: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* TST.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_110733;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}	m68k_incpci (6);
+l_110733: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (5/0) */
+
+/* TAS.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4ac0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src |= 0x80;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((src) & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* TAS.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src |= 0x80;
+	put_byte_prefetch (srca, src);
+}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* TAS.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src |= 0x80;
+	put_byte_prefetch (srca, src);
+}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* TAS.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	src |= 0x80;
+	put_byte_prefetch (srca, src);
+}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/1) */
+
+/* TAS.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src |= 0x80;
+	put_byte_prefetch (srca, src);
+}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* TAS.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4af0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src |= 0x80;
+	put_byte_prefetch (srca, src);
+}}}	m68k_incpci (4);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/1) */
+
+/* TAS.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4af8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	src |= 0x80;
+	put_byte_prefetch (srca, src);
+}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* TAS.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4af9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	src |= 0x80;
+	put_byte_prefetch (srca, src);
+}}}	m68k_incpci (6);
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (4/1) */
+
+/* MVMEL.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4c90_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110742;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		amask = movem_next[amask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+}}}}	m68k_incpci (4);
+l_110742: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (3/0) */
+
+/* MVMEL.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4c98_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110743;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		amask = movem_next[amask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	m68k_areg (regs, dstreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+}}}}	m68k_incpci (4);
+l_110743: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (3/0) */
+
+/* MVMEL.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ca8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110744;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		amask = movem_next[amask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110744: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16+ (4/0) */
+
+/* MVMEL.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 18; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110745;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		amask = movem_next[amask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110745: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18+ (4/0) */
+
+/* MVMEL.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110746;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		amask = movem_next[amask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110746: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16+ (4/0) */
+
+/* MVMEL.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 20; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = get_word_prefetch (6) << 16;
+	srca |= get_word_prefetch (8);
+	if (srca & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, srca);
+		goto l_110747;
+	}
+{	bus_error_offset = 8;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		amask = movem_next[amask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+}}}}	m68k_incpci (8);
+l_110747: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20+ (5/0) */
+
+/* MVMEL.W #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cba_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110748;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		amask = movem_next[amask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110748: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16+ (4/0) */
+
+/* MVMEL.W #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cbb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 18; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 4;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (6));
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110749;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_prefetch_addr (srca);
+		srca += 2;
+		amask = movem_next[amask];
+		count_cycles += 4 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110749: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18+ (4/0) */
+
+/* MVMEL.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110750;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+}}}}	m68k_incpci (4);
+l_110750: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (3/0) */
+
+/* MVMEL.L #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110751;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	m68k_areg (regs, dstreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+}}}}	m68k_incpci (4);
+l_110751: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (3/0) */
+
+/* MVMEL.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ce8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110752;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110752: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16+ (4/0) */
+
+/* MVMEL.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 18; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (6));
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110753;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110753: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18+ (4/0) */
+
+/* MVMEL.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110754;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110754: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16+ (4/0) */
+
+/* MVMEL.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 20; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = get_word_prefetch (6) << 16;
+	srca |= get_word_prefetch (8);
+	if (srca & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, srca);
+		goto l_110755;
+	}
+{	bus_error_offset = 8;
+{	while (dmask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (10);
+}}}}	m68k_incpci (8);
+l_110755: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20+ (5/0) */
+
+/* MVMEL.L #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110756;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110756: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16+ (4/0) */
+
+/* MVMEL.L #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 18; 
+{	uae_u16 mask = get_word_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 4;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (6));
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_110757;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	while (amask) {
+		v = get_word_prefetch_addr (srca) << 16;
+		v |= get_word_prefetch_addr (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+		count_cycles += 8 * CYCLE_UNIT / 2;
+	}
+	get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+}}}}	m68k_incpci (6);
+l_110757: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18+ (4/0) */
+
+/* TRAPQ.L # */
+uae_u32 REGPARAM2 CPUFUNC(op_4e40_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 15);
+	OpcodeFamily = 39;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+	m68k_incpci (2);
+	Exception (src + 32);
+}}return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (0/0) */
+
+/* LINK.W An,#.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e50_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 16; 
+{{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	if (olda & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, olda);
+		goto l_110759;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s16 offs = get_word_prefetch (4);
+	put_word_prefetch (olda, src >> 16); put_word_prefetch (olda + 2, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+}}}}}	m68k_incpci (4);
+l_110759: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* UNLK.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e58_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 48;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	m68k_areg (regs, 7) = src;
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7);
+	if (olda & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, olda);
+		goto l_110760;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 old = get_word_prefetch_addr (olda) << 16; old |= get_word_prefetch_addr (olda + 2);
+	m68k_areg (regs, 7) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_areg (regs, srcreg) = (old);
+}}}}}	m68k_incpci (2);
+l_110760: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* MVR2USP.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e60_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 40;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_110761; }
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	regs.usp = src;
+}}}	m68k_incpci (2);
+l_110761: ;
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* MVUSP2R.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e68_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 41;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_110762; }
+{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_areg (regs, srcreg) = (regs.usp);
+}}}	m68k_incpci (2);
+l_110762: ;
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* RESET.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e70_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 42;
+	CurrentInstrCycles = 132;
+{if (!regs.s) { Exception (8); goto l_110763; }
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	cpureset ();
+	m68k_incpci (2);
+	get_word_prefetch (2);
+}}l_110763: ;
+return 132 * CYCLE_UNIT / 2 + count_cycles;
+} /* 132 (1/0) */
+
+/* NOP.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e71_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 43;
+	CurrentInstrCycles = 4;  
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* STOP.L #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e72_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 44;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_110765; }
+{	regs.sr = regs.irc;
+	MakeFromSR();
+	m68k_setstopped ();
+	m68k_incpci (4);
+}}l_110765: ;
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (0/0) */
+
+/* RTE.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e73_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 45;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_110766; }
+{	uae_u16 newsr; uae_u32 newpc;
+	for (;;) {
+		uaecptr a = m68k_areg (regs, 7);
+		uae_u16 sr = get_word_prefetch_addr (a);
+		uae_u32 pc = get_word_prefetch_addr (a + 2) << 16; pc |= get_word_prefetch_addr (a + 4);
+		uae_u16 format = get_word_prefetch_addr (a + 2 + 4);
+		int frame = format >> 12;
+		int offset = 8;
+		newsr = sr; newpc = pc;
+		if (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }
+		else if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }
+		else { m68k_areg (regs, 7) += offset; Exception (14); goto l_110766; }
+		regs.sr = newsr; MakeFromSR ();
+}
+	regs.sr = newsr;
+	MakeFromSR();
+	if (newpc & 1) {
+		exception3i (0x4E73, newpc);
+		goto l_110766;
+	}
+	m68k_setpci (newpc);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110766: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (6/0) */
+
+/* RTD.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e74_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 46;
+	CurrentInstrCycles = 20; 
+{{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+	if (pca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, pca);
+		goto l_110767;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 pc = get_word_prefetch_addr (pca) << 16; pc |= get_word_prefetch_addr (pca + 2);
+	m68k_areg (regs, 7) += 4;
+{	uae_s16 offs = get_word_prefetch (4);
+	m68k_areg (regs, 7) += offs;
+	if (pc & 1) {
+		exception3i (0x4E74, pc);
+		goto l_110767;
+	}
+	m68k_setpci (pc);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}l_110767: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (5/0) */
+
+#endif
+/* RTS.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e75_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 49;
+	CurrentInstrCycles = 16; 
+{	uaecptr pc = m68k_getpci ();
+	m68k_do_rtsi ();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (pc);
+		exception3i (0x4E75, faultpc);
+		goto l_110768;
+	}
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_110768: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* TRAPV.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e76_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 50;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	if (GET_VFLG ()) {
+		Exception (7);
+		goto l_110769;
+	}
+}l_110769: ;
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* RTR.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e77_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 51;
+	CurrentInstrCycles = 20; 
+{	uaecptr oldpc = m68k_getpci ();
+	MakeSR ();
+{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+	if (sra & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, sra);
+		goto l_110770;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 sr = get_word_prefetch_addr (sra);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+	if (pca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, pca);
+		goto l_110770;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 pc = get_word_prefetch_addr (pca) << 16; pc |= get_word_prefetch_addr (pca + 2);
+	m68k_areg (regs, 7) += 4;
+	regs.sr &= 0xFF00; sr &= 0xFF;
+	regs.sr |= sr;
+	m68k_setpci (pc);
+	MakeFromSR();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (oldpc);
+		exception3i (0x4E77, faultpc);
+		goto l_110770;
+	}
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}}l_110770: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (5/0) */
+
+/* MOVEC2.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 82;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_110771; }
+{{	uae_s16 src = get_word_prefetch (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_movec2(src & 0xFFF, regp)) goto l_110771;
+}}}}	m68k_incpci (4);
+l_110771: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+#endif
+/* MOVE2C.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 83;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_110772; }
+{{	uae_s16 src = get_word_prefetch (4);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_move2c(src & 0xFFF, regp)) goto l_110772;
+}}}}	m68k_incpci (4);
+l_110772: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+#endif
+/* JSR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4e90_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr oldpc = m68k_getpci () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_110773;
+	}
+	m68k_setpci (srca);
+	get_word_prefetch (0);
+	m68k_areg (regs, 7) -= 4;
+	put_word_prefetch (m68k_areg (regs, 7), oldpc >> 16);
+	put_word_prefetch (m68k_areg (regs, 7) + 2, oldpc);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110773: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* JSR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ea8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)regs.irc;
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_110774;
+	}
+	m68k_setpci (srca);
+	get_word_prefetch (0);
+	m68k_areg (regs, 7) -= 4;
+	put_word_prefetch (m68k_areg (regs, 7), oldpc >> 16);
+	put_word_prefetch (m68k_areg (regs, 7) + 2, oldpc);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110774: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (2/2) */
+
+/* JSR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), regs.irc);
+{	uaecptr oldpc = m68k_getpci () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_110775;
+	}
+	oldpc += 2;
+	m68k_setpci (srca);
+	get_word_prefetch (0);
+	m68k_areg (regs, 7) -= 4;
+	put_word_prefetch (m68k_areg (regs, 7), oldpc >> 16);
+	put_word_prefetch (m68k_areg (regs, 7) + 2, oldpc);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110775: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (2/2) */
+
+/* JSR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)regs.irc;
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_110776;
+	}
+	m68k_setpci (srca);
+	get_word_prefetch (0);
+	m68k_areg (regs, 7) -= 4;
+	put_word_prefetch (m68k_areg (regs, 7), oldpc >> 16);
+	put_word_prefetch (m68k_areg (regs, 7) + 2, oldpc);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110776: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (2/2) */
+
+/* JSR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= regs.irc;
+{	uaecptr oldpc = m68k_getpci () + 6;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_110777;
+	}
+	m68k_setpci (srca);
+	get_word_prefetch (0);
+	m68k_areg (regs, 7) -= 4;
+	put_word_prefetch (m68k_areg (regs, 7), oldpc >> 16);
+	put_word_prefetch (m68k_areg (regs, 7) + 2, oldpc);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110777: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* JSR.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eba_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)regs.irc;
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_110778;
+	}
+	m68k_setpci (srca);
+	get_word_prefetch (0);
+	m68k_areg (regs, 7) -= 4;
+	put_word_prefetch (m68k_areg (regs, 7), oldpc >> 16);
+	put_word_prefetch (m68k_areg (regs, 7) + 2, oldpc);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110778: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (2/2) */
+
+/* JSR.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ebb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	srca = get_disp_ea_000 (tmppc, regs.irc);
+{	uaecptr oldpc = m68k_getpci () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_110779;
+	}
+	oldpc += 2;
+	m68k_setpci (srca);
+	get_word_prefetch (0);
+	m68k_areg (regs, 7) -= 4;
+	put_word_prefetch (m68k_areg (regs, 7), oldpc >> 16);
+	put_word_prefetch (m68k_areg (regs, 7) + 2, oldpc);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110779: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (2/2) */
+
+/* JMP.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ed0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_110780;
+	}
+	m68k_setpci (srca);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110780: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* JMP.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ee8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)regs.irc;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_110781;
+	}
+	m68k_setpci (srca);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110781: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* JMP.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), regs.irc);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_110782;
+	}
+	m68k_setpci (srca);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110782: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/0) */
+
+/* JMP.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)regs.irc;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_110783;
+	}
+	m68k_setpci (srca);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110783: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* JMP.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= regs.irc;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_110784;
+	}
+	m68k_setpci (srca);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110784: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* JMP.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)regs.irc;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_110785;
+	}
+	m68k_setpci (srca);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110785: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* JMP.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	srca = get_disp_ea_000 (tmppc, regs.irc);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_110786;
+	}
+	m68k_setpci (srca);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110786: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/0) */
+
+/* ADDQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5000_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* ADDQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5010_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ADDQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5018_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ADDQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5020_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* ADDQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5028_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ADDQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5030_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* ADDQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5038_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ADDQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5039_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* ADDQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5040_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* ADDAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5048_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* ADDQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5050_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110797;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_110797: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ADDQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5058_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110798;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_110798: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ADDQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5060_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110799;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_110799: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* ADDQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5068_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110800;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_110800: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ADDQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5070_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110801;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_110801: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* ADDQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5078_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110802;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_110802: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ADDQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5079_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110803;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_110803: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* ADDQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5080_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* ADDAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5088_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* ADDQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5090_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110806;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_110806: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* ADDQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5098_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110807;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_110807: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* ADDQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110808;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_110808: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (3/2) */
+
+#endif
+
+#ifdef PART_5
+/* ADDQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110809;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_110809: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* ADDQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_50b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 26; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110810;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_110810: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* ADDQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_50b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110811;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_110811: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* ADDQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_50b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110812;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_110812: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* Scc.B Dn (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (0)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110814;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110814: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* SUBQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5100_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* SUBQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5110_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* SUBQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5118_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* SUBQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5120_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* SUBQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5128_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* SUBQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5130_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* SUBQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5138_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* SUBQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5139_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* SUBQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5140_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* SUBAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5148_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* SUBQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5150_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110832;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_110832: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* SUBQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5158_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110833;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_110833: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* SUBQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5160_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110834;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_110834: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* SUBQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5168_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110835;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_110835: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* SUBQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5170_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110836;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_110836: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* SUBQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5178_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110837;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_110837: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* SUBQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5179_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110838;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_110838: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* SUBQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5180_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* SUBAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5188_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* SUBQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5190_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110841;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_110841: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* SUBQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5198_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110842;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_110842: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* SUBQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110843;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_110843: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (3/2) */
+
+/* SUBQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110844;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_110844: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* SUBQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_51b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 26; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_110845;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_110845: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* SUBQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_51b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_110846;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_110846: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* SUBQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_51b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_110847;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_110847: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* Scc.B Dn (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (1)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110849;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110849: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (2)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110858;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110858: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (3)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110867;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110867: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (4)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110876;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110876: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (5)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110885;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110885: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (6)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110894;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110894: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (7)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110903;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110903: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (8)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110912;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110912: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (9)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110921;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110921: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (10)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110930;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110930: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (11)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110939;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110939: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (12)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110948;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110948: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (13)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110957;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110957: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (14)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110966;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110966: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	if (!cctrue (15)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_110975;
+			}
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+			return 8 * CYCLE_UNIT / 2 + count_cycles;
+		}
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	} else {
+		count_cycles += 2 * CYCLE_UNIT / 2;
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}l_110975: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* Scc.B (An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Bcc.W #.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6000_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_110983;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110983: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6001_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_110984;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110984: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_60ff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (0)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_110985;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_110985: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* BSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_6100_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 18; 
+{	uae_s32 s;
+{	uae_s16 src = regs.irc;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_110986;
+	}
+	m68k_do_bsri (m68k_getpci () + 4, s);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110986: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (2/2) */
+
+/* BSRQ.B # */
+uae_u32 REGPARAM2 CPUFUNC(op_6101_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 18; 
+{	uae_s32 s;
+{	uae_u32 src = srcreg;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_110987;
+	}
+	m68k_do_bsri (m68k_getpci () + 2, s);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110987: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (2/2) */
+
+/* BSR.L #.L */
+uae_u32 REGPARAM2 CPUFUNC(op_61ff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 18; 
+{	uae_s32 s;
+	uae_u32 src = 0xffffffff;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_110988;
+	}
+	m68k_do_bsri (m68k_getpci () + 2, s);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_110988: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (2/2) */
+
+/* Bcc.W #.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6200_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_110989;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110989: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6201_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_110990;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110990: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_62ff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (2)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_110991;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_110991: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6300_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_110992;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110992: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6301_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_110993;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110993: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+#endif
+
+#ifdef PART_6
+/* Bcc.L #.L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_63ff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (3)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_110994;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_110994: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6400_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_110995;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110995: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6401_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_110996;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110996: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_64ff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (4)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_110997;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_110997: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6500_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_110998;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110998: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6501_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_110999;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_110999: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_65ff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (5)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_111000;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_111000: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6600_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111001;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111001: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6601_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111002;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111002: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_66ff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (6)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_111003;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_111003: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6700_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111004;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111004: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6701_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111005;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111005: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_67ff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (7)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_111006;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_111006: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6800_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111007;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111007: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6801_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111008;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111008: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_68ff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (8)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_111009;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_111009: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6900_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111010;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111010: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6901_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111011;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111011: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_69ff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (9)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_111012;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_111012: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a00_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111013;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111013: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a01_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111014;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111014: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6aff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (10)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_111015;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_111015: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b00_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111016;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111016: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b01_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111017;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111017: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6bff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (11)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_111018;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_111018: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c00_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111019;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111019: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c01_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111020;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111020: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6cff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (12)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_111021;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_111021: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d00_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111022;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111022: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d01_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111023;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111023: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6dff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (13)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_111024;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_111024: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e00_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111025;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111025: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e01_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111026;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111026: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6eff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (14)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_111027;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_111027: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f00_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111028;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111028: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* BccQ.B # (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f01_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_111029;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}l_111029: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6fff_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	if (cctrue (15)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_111030;
+	}
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}l_111030: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* MOVEQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_7000_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* OR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8000_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* OR.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8010_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* OR.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8018_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* OR.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8020_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* OR.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8028_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* OR.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8030_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* OR.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8038_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* OR.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8039_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* OR.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* OR.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* OR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8040_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* OR.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8050_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111044;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (2);
+l_111044: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* OR.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8058_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111045;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (2);
+l_111045: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* OR.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8060_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111046;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (2);
+l_111046: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* OR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8068_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111047;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_111047: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* OR.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8070_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111048;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_111048: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* OR.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8078_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111049;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_111049: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* OR.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8079_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111050;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (6);
+l_111050: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* OR.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111051;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_111051: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* OR.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111052;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_111052: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* OR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8080_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* OR.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8090_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111055;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (2);
+l_111055: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* OR.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8098_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111056;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (2);
+l_111056: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* OR.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111057;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (2);
+l_111057: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* OR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111058;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_111058: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* OR.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111059;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_111059: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* OR.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111060;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_111060: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* OR.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111061;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (6);
+l_111061: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (5/0) */
+
+/* OR.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80ba_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111062;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_111062: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* OR.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111063;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_111063: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* DIVU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_111065;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		count_cycles += ((getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}l_111065: ;
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DIVU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111066;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_111066;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		count_cycles += ((getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}}l_111066: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (2/0) */
+
+/* DIVU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111067;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_111067;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		count_cycles += ((getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}}l_111067: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (2/0) */
+
+/* DIVU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111068;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_111068;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		count_cycles += ((getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}}l_111068: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* DIVU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111069;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_111069;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		count_cycles += ((getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}}l_111069: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (3/0) */
+
+/* DIVU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111070;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_111070;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		count_cycles += ((getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}}l_111070: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14+ (3/0) */
+
+/* DIVU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111071;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_111071;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		count_cycles += ((getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}}l_111071: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (3/0) */
+
+/* DIVU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111072;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (6);
+		Exception (5);
+		goto l_111072;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		count_cycles += ((getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (6);
+	}
+}}}}}l_111072: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16+ (4/0) */
+
+/* DIVU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111073;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_111073;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		count_cycles += ((getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}}l_111073: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (3/0) */
+
+/* DIVU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111074;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_111074;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		count_cycles += ((getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}}l_111074: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14+ (3/0) */
+
+/* DIVU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_111075;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		count_cycles += ((getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}l_111075: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (2/0) */
+
+/* SBCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8100_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* SBCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8108_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* OR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8110_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* OR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8118_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* OR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8120_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* OR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8128_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* OR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8130_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* OR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8138_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* OR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8139_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* OR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8150_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111085;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (2);
+l_111085: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* OR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8158_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111086;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (2);
+l_111086: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* OR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8160_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111087;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (2);
+l_111087: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* OR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8168_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111088;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_111088: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* OR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8170_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111089;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_111089: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* OR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8178_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111090;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_111090: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* OR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8179_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_111091;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (6);
+l_111091: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* OR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8190_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111092;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_111092: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* OR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8198_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111093;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_111093: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* OR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111094;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_111094: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (3/2) */
+
+/* OR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111095;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_111095: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* OR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_81b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 26; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111096;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_111096: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* OR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_81b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111097;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_111097: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* OR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_81b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_111098;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_111098: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* DIVS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_111099;
+	}
+	CLEAR_CZNV ();
+		count_cycles += ((getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}l_111099: ;
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* DIVS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111100;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_111100;
+	}
+	CLEAR_CZNV ();
+		count_cycles += ((getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}}l_111100: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (2/0) */
+
+/* DIVS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111101;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_111101;
+	}
+	CLEAR_CZNV ();
+		count_cycles += ((getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}}l_111101: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (2/0) */
+
+/* DIVS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111102;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_111102;
+	}
+	CLEAR_CZNV ();
+		count_cycles += ((getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}}l_111102: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10+ (2/0) */
+
+/* DIVS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111103;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_111103;
+	}
+	CLEAR_CZNV ();
+		count_cycles += ((getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}}l_111103: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (3/0) */
+
+/* DIVS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111104;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_111104;
+	}
+	CLEAR_CZNV ();
+		count_cycles += ((getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}}l_111104: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14+ (3/0) */
+
+/* DIVS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111105;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_111105;
+	}
+	CLEAR_CZNV ();
+		count_cycles += ((getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}}l_111105: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (3/0) */
+
+/* DIVS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111106;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (6);
+		Exception (5);
+		goto l_111106;
+	}
+	CLEAR_CZNV ();
+		count_cycles += ((getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (6);
+}}}}}l_111106: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16+ (4/0) */
+
+/* DIVS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111107;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_111107;
+	}
+	CLEAR_CZNV ();
+		count_cycles += ((getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}}l_111107: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12+ (3/0) */
+
+/* DIVS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111108;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_111108;
+	}
+	CLEAR_CZNV ();
+		count_cycles += ((getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}}l_111108: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14+ (3/0) */
+
+/* DIVS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_111109;
+	}
+	CLEAR_CZNV ();
+		count_cycles += ((getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4) * CYCLE_UNIT / 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}l_111109: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (2/0) */
+
+/* SUB.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9000_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* SUB.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9010_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* SUB.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9018_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* SUB.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9020_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* SUB.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9028_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* SUB.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9030_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* SUB.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9038_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* SUB.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9039_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* SUB.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* SUB.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* SUB.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9040_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* SUB.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9048_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* SUB.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9050_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111123;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (2);
+l_111123: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* SUB.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9058_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111124;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (2);
+l_111124: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* SUB.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9060_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111125;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (2);
+l_111125: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* SUB.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9068_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111126;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_111126: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* SUB.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9070_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111127;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_111127: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* SUB.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9078_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111128;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_111128: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* SUB.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9079_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111129;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+l_111129: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* SUB.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111130;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_111130: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* SUB.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111131;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_111131: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* SUB.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9080_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* SUB.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9088_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* SUB.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9090_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111135;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (2);
+l_111135: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* SUB.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9098_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111136;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (2);
+l_111136: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* SUB.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111137;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (2);
+l_111137: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* SUB.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111138;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_111138: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* SUB.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111139;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_111139: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* SUB.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111140;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_111140: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* SUB.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111141;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (6);
+l_111141: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (5/0) */
+
+/* SUB.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90ba_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111142;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_111142: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* SUB.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111143;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_111143: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* SUBA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* SUBA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* SUBA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111147;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111147: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* SUBA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111148;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111148: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* SUBA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111149;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111149: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/0) */
+
+/* SUBA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111150;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111150: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* SUBA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111151;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111151: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/0) */
+
+/* SUBA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111152;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111152: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* SUBA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111153;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+l_111153: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* SUBA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111154;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111154: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* SUBA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111155;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111155: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/0) */
+
+/* SUBA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* SUBX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9100_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* SUBX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9108_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* SUB.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9110_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* SUB.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9118_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* SUB.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9120_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* SUB.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9128_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* SUB.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9130_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* SUB.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9138_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* SUB.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9139_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* SUBX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9140_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* SUBX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9148_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111167;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111167;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}}	m68k_incpci (2);
+l_111167: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* SUB.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9150_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111168;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_111168: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* SUB.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9158_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111169;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_111169: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* SUB.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9160_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111170;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_111170: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* SUB.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9168_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111171;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_111171: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* SUB.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9170_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111172;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_111172: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* SUB.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9178_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111173;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_111173: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* SUB.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9179_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_111174;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_111174: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* SUBX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9180_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* SUBX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9188_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111176;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111176;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_word_prefetch (dsta, newv >> 16); put_word_prefetch (dsta + 2, newv);
+}}}}}}}}}	m68k_incpci (2);
+l_111176: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* SUB.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9190_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111177;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_111177: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* SUB.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9198_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111178;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_111178: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* SUB.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111179;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_111179: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (3/2) */
+
+/* SUB.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111180;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_111180: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* SUB.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_91b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 26; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111181;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_111181: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* SUB.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_91b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111182;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_111182: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* SUB.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_91b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_111183;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_111183: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* SUBA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* SUBA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* SUBA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111186;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111186: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* SUBA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111187;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111187: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* SUBA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111188;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111188: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* SUBA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111189;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111189: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* SUBA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111190;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111190: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* SUBA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111191;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111191: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* SUBA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111192;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+l_111192: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (5/0) */
+
+/* SUBA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111193;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111193: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* SUBA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111194;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111194: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* SUBA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* CMP.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b000_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* CMP.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b010_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* CMP.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b018_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* CMP.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b020_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* CMP.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b028_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* CMP.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b030_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMP.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b038_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* CMP.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b039_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* CMP.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* CMP.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* CMP.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b040_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* CMP.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b048_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* CMP.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b050_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111209;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_111209: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* CMP.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b058_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111210;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_111210: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* CMP.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b060_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111211;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_111211: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* CMP.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b068_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111212;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111212: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* CMP.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b070_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111213;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111213: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMP.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b078_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111214;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111214: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* CMP.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b079_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111215;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_111215: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* CMP.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111216;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111216: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* CMP.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111217;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111217: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* CMP.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b080_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* CMP.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b088_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* CMP.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b090_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111221;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_111221: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMP.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b098_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111222;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_111222: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMP.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111223;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_111223: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+#endif
+
+#ifdef PART_7
+/* CMP.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111224;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111224: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* CMP.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111225;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111225: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* CMP.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111226;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111226: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* CMP.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111227;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_111227: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (5/0) */
+
+/* CMP.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0ba_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111228;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111228: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* CMP.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111229;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111229: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMPA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* CMPA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* CMPA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111233;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_111233: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* CMPA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111234;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_111234: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* CMPA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111235;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_111235: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* CMPA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111236;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111236: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMPA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111237;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111237: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* CMPA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111238;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111238: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMPA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111239;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_111239: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* CMPA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111240;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111240: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMPA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111241;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111241: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* CMPA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* EOR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b100_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* CMPM.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b108_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* EOR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b110_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* EOR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b118_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* EOR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b120_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* EOR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b128_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* EOR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b130_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* EOR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b138_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* EOR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b139_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* EOR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b140_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* CMPM.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b148_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111253;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111253;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}}}	m68k_incpci (2);
+l_111253: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* EOR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b150_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111254;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (2);
+l_111254: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* EOR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b158_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111255;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (2);
+l_111255: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* EOR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b160_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111256;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (2);
+l_111256: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* EOR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b168_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111257;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_111257: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* EOR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b170_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111258;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_111258: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* EOR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b178_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111259;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_111259: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* EOR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b179_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_111260;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (6);
+l_111260: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* EOR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b180_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* CMPM.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b188_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111262;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111262;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}}}	m68k_incpci (2);
+l_111262: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (5/0) */
+
+/* EOR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b190_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111263;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_111263: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* EOR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b198_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111264;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_111264: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* EOR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111265;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_111265: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (3/2) */
+
+/* EOR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111266;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_111266: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* EOR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 26; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111267;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_111267: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* EOR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111268;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_111268: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* EOR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_111269;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_111269: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* CMPA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* CMPA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* CMPA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111272;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_111272: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMPA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111273;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_111273: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* CMPA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111274;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_111274: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* CMPA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111275;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111275: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* CMPA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111276;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111276: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* CMPA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111277;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111277: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* CMPA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111278;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_111278: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (5/0) */
+
+/* CMPA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111279;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111279: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* CMPA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111280;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_111280: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* CMPA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* AND.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c000_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* AND.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c010_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* AND.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c018_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* AND.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c020_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* AND.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c028_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* AND.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c030_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* AND.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c038_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* AND.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c039_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* AND.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* AND.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* AND.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c040_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* AND.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c050_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111294;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (2);
+l_111294: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* AND.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c058_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111295;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (2);
+l_111295: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* AND.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c060_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111296;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (2);
+l_111296: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* AND.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c068_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111297;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_111297: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* AND.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c070_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111298;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_111298: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* AND.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c078_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111299;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_111299: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* AND.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c079_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111300;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (6);
+l_111300: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* AND.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111301;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_111301: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* AND.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111302;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_111302: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* AND.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c080_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* AND.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c090_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111305;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (2);
+l_111305: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* AND.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c098_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111306;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (2);
+l_111306: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* AND.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111307;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (2);
+l_111307: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* AND.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111308;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_111308: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* AND.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111309;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_111309: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* AND.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111310;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_111310: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* AND.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111311;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (6);
+l_111311: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (5/0) */
+
+/* AND.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0ba_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111312;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_111312: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* AND.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111313;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_111313: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* MULU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}return 38 * CYCLE_UNIT / 2 + count_cycles;
+} /* 38+ (1/0) */
+
+/* MULU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 42; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111316;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}}l_111316: ;
+return 42 * CYCLE_UNIT / 2 + count_cycles;
+} /* 42+ (2/0) */
+
+/* MULU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 42; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111317;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}}l_111317: ;
+return 42 * CYCLE_UNIT / 2 + count_cycles;
+} /* 42+ (2/0) */
+
+/* MULU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 44; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111318;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}}l_111318: ;
+return 44 * CYCLE_UNIT / 2 + count_cycles;
+} /* 44+ (2/0) */
+
+/* MULU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 46; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111319;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}}l_111319: ;
+return 46 * CYCLE_UNIT / 2 + count_cycles;
+} /* 46+ (3/0) */
+
+/* MULU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 48; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111320;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}}l_111320: ;
+return 48 * CYCLE_UNIT / 2 + count_cycles;
+} /* 48+ (3/0) */
+
+/* MULU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 46; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111321;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}}l_111321: ;
+return 46 * CYCLE_UNIT / 2 + count_cycles;
+} /* 46+ (3/0) */
+
+/* MULU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 50; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111322;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (6);
+}}}}}}l_111322: ;
+return 50 * CYCLE_UNIT / 2 + count_cycles;
+} /* 50+ (4/0) */
+
+/* MULU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 46; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111323;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}}l_111323: ;
+return 46 * CYCLE_UNIT / 2 + count_cycles;
+} /* 46+ (3/0) */
+
+/* MULU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 48; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111324;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}}l_111324: ;
+return 48 * CYCLE_UNIT / 2 + count_cycles;
+} /* 48+ (3/0) */
+
+/* MULU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 42; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}return 42 * CYCLE_UNIT / 2 + count_cycles;
+} /* 42+ (2/0) */
+
+/* ABCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c100_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* ABCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c108_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* AND.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c110_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* AND.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c118_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* AND.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c120_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* AND.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c128_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* AND.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c130_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* AND.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c138_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* AND.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c139_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_byte_prefetch (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* EXG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c140_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* EXG.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c148_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_areg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* AND.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c150_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111337;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (2);
+l_111337: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* AND.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c158_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111338;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (2);
+l_111338: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* AND.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c160_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111339;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (2);
+l_111339: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* AND.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c168_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111340;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_111340: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* AND.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c170_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111341;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_111341: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* AND.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c178_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111342;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (4);
+l_111342: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* AND.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c179_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_111343;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta, src);
+}}}}}	m68k_incpci (6);
+l_111343: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* EXG.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c188_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* AND.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c190_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111345;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_111345: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* AND.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c198_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111346;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_111346: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* AND.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111347;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_111347: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (3/2) */
+
+/* AND.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111348;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_111348: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* AND.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 26; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111349;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_111349: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* AND.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111350;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_111350: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* AND.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_111351;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	put_word_prefetch (dsta + 2, src); put_word_prefetch (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_111351: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* MULS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 38 * CYCLE_UNIT / 2 + count_cycles;
+} /* 38+ (1/0) */
+
+/* MULS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 42; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111353;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111353: ;
+return 42 * CYCLE_UNIT / 2 + count_cycles;
+} /* 42+ (2/0) */
+
+/* MULS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 42; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111354;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111354: ;
+return 42 * CYCLE_UNIT / 2 + count_cycles;
+} /* 42+ (2/0) */
+
+/* MULS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 44; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111355;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111355: ;
+return 44 * CYCLE_UNIT / 2 + count_cycles;
+} /* 44+ (2/0) */
+
+/* MULS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 46; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111356;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111356: ;
+return 46 * CYCLE_UNIT / 2 + count_cycles;
+} /* 46+ (3/0) */
+
+/* MULS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 48; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111357;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111357: ;
+return 48 * CYCLE_UNIT / 2 + count_cycles;
+} /* 48+ (3/0) */
+
+/* MULS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 46; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111358;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111358: ;
+return 46 * CYCLE_UNIT / 2 + count_cycles;
+} /* 46+ (3/0) */
+
+/* MULS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 50; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111359;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+l_111359: ;
+return 50 * CYCLE_UNIT / 2 + count_cycles;
+} /* 50+ (4/0) */
+
+/* MULS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 46; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111360;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111360: ;
+return 46 * CYCLE_UNIT / 2 + count_cycles;
+} /* 46+ (3/0) */
+
+/* MULS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 48; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111361;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111361: ;
+return 48 * CYCLE_UNIT / 2 + count_cycles;
+} /* 48+ (3/0) */
+
+/* MULS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 42; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) count_cycles += 2 * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 42 * CYCLE_UNIT / 2 + count_cycles;
+} /* 42+ (2/0) */
+
+/* ADD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d000_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* ADD.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d010_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* ADD.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d018_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* ADD.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d020_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* ADD.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d028_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* ADD.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d030_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* ADD.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d038_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* ADD.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d039_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* ADD.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* ADD.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* ADD.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d040_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* ADD.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d048_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* ADD.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d050_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111376;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (2);
+l_111376: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* ADD.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d058_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111377;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (2);
+l_111377: ;
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* ADD.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d060_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111378;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (2);
+l_111378: ;
+return 10 * CYCLE_UNIT / 2 + count_cycles;
+} /* 10 (2/0) */
+
+/* ADD.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d068_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111379;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_111379: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* ADD.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d070_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111380;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_111380: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* ADD.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d078_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111381;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_111381: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* ADD.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d079_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111382;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+l_111382: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (4/0) */
+
+/* ADD.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07a_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111383;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_111383: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (3/0) */
+
+/* ADD.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07b_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111384;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_111384: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07c_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (2/0) */
+
+/* ADD.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d080_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* ADD.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d088_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* ADD.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d090_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111388;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (2);
+l_111388: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* ADD.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d098_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111389;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (2);
+l_111389: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* ADD.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111390;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (2);
+l_111390: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* ADD.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111391;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_111391: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* ADD.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111392;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_111392: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* ADD.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111393;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_111393: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* ADD.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111394;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (6);
+l_111394: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (5/0) */
+
+/* ADD.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0ba_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111395;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_111395: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* ADD.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111396;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_111396: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* ADDA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* ADDA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* ADDA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111400;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111400: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* ADDA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111401;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111401: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* ADDA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111402;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111402: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/0) */
+
+/* ADDA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111403;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111403: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* ADDA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111404;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111404: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/0) */
+
+/* ADDA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111405;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111405: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* ADDA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111406;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+l_111406: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* ADDA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111407;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111407: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* ADDA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111408;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111408: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/0) */
+
+/* ADDA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_prefetch (4);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/0) */
+
+/* ADDX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d100_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* ADDX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d108_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* ADD.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d110_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ADD.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d118_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ADD.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d120_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* ADD.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d128_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ADD.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d130_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* ADD.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d138_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ADD.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d139_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = get_byte_prefetch (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_prefetch (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* ADDX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d140_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* ADDX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d148_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111420;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111420;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}}	m68k_incpci (2);
+l_111420: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* ADD.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d150_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111421;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_111421: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ADD.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d158_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111422;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_111422: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ADD.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d160_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111423;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_111423: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* ADD.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d168_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111424;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_111424: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ADD.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d170_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111425;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_111425: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* ADD.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d178_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111426;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_111426: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ADD.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d179_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_111427;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = get_word_prefetch_addr (dsta);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_111427: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* ADDX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d180_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* ADDX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d188_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111429;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111429;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_word_prefetch (dsta, newv >> 16); put_word_prefetch (dsta + 2, newv);
+}}}}}}}}}	m68k_incpci (2);
+l_111429: ;
+return 30 * CYCLE_UNIT / 2 + count_cycles;
+} /* 30 (5/2) */
+
+/* ADD.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d190_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111430;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_111430: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* ADD.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d198_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111431;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_111431: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* ADD.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111432;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_111432: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (3/2) */
+
+/* ADD.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111433;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_111433: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* ADD.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 26; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	BusCyclePenalty += 2;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_111434;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_111434: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* ADD.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_111435;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_111435: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* ADD.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_prefetch (4) << 16;
+	dsta |= get_word_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_111436;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = get_word_prefetch_addr (dsta) << 16; dst |= get_word_prefetch_addr (dsta + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_prefetch (dsta + 2, newv); put_word_prefetch (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_111436: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+/* ADDA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* ADDA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8 (1/0) */
+
+/* ADDA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111439;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111439: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* ADDA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111440;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111440: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (3/0) */
+
+/* ADDA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111441;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_111441: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* ADDA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111442;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111442: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* ADDA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111443;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111443: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* ADDA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_111444;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111444: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* ADDA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_111445;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+l_111445: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (5/0) */
+
+/* ADDA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fa_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111446;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111446: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (4/0) */
+
+/* ADDA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fb_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (tmppc, get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_111447;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_111447: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/0) */
+
+/* ADDA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fc_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_prefetch (4) << 16;
+	src |= get_word_prefetch (6);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/0) */
+
+/* ASRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e000_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* LSRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e008_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ROXRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e010_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* RORQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e018_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ASR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e020_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* LSR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e028_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ROXR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e030_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ROR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e038_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ASRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e040_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+#endif
+
+#ifdef PART_8
+/* LSRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e048_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ROXRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e050_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* RORQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e058_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ASR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e060_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* LSR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e068_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ROXR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e070_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ROR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e078_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ASRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e080_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* LSRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e088_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* ROXRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e090_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* RORQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e098_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* ASR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* LSR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* ROXR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* ROR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* ASRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111473;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111473: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ASRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111474;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111474: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ASRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111475;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111475: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* ASRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111476;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111476: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ASRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	BusCyclePenalty += 2;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111477;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111477: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* ASRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111478;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111478: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ASRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_prefetch (4) << 16;
+	dataa |= get_word_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_111479;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (6);
+l_111479: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* ASLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e100_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* LSLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e108_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ROXLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e110_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ROLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e118_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ASL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e120_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* LSL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e128_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ROXL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e130_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ROL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e138_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ASLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e140_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* LSLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e148_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ROXLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e150_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ROLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e158_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ASL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e160_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* LSL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e168_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ROXL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e170_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ROL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e178_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6+ (1/0) */
+
+/* ASLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e180_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* LSLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e188_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* ROXLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e190_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* ROLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e198_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* ASL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* LSL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* ROXL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* ROL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2 + count_cycles;
+} /* 8+ (1/0) */
+
+/* ASLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111504;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111504: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ASLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111505;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111505: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ASLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111506;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111506: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* ASLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111507;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111507: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ASLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	BusCyclePenalty += 2;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111508;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111508: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* ASLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111509;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111509: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ASLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_prefetch (4) << 16;
+	dataa |= get_word_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_111510;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (6);
+l_111510: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* LSRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111511;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111511: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* LSRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111512;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111512: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* LSRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111513;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111513: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* LSRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111514;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111514: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* LSRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	BusCyclePenalty += 2;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111515;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111515: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* LSRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111516;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111516: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* LSRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_prefetch (4) << 16;
+	dataa |= get_word_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_111517;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (6);
+l_111517: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* LSLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111518;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111518: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* LSLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111519;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111519: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* LSLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111520;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111520: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* LSLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111521;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111521: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* LSLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	BusCyclePenalty += 2;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111522;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111522: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* LSLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111523;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111523: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* LSLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_prefetch (4) << 16;
+	dataa |= get_word_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_111524;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (6);
+l_111524: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* ROXRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111525;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111525: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ROXRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111526;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111526: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ROXRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111527;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111527: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* ROXRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111528;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111528: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ROXRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	BusCyclePenalty += 2;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111529;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111529: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* ROXRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111530;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111530: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ROXRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_prefetch (4) << 16;
+	dataa |= get_word_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_111531;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (6);
+l_111531: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* ROXLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111532;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111532: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ROXLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111533;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111533: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ROXLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111534;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111534: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* ROXLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111535;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111535: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ROXLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	BusCyclePenalty += 2;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111536;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111536: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* ROXLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111537;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111537: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ROXLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_prefetch (4) << 16;
+	dataa |= get_word_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_111538;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (6);
+l_111538: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* RORW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111539;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111539: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* RORW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111540;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111540: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* RORW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111541;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111541: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* RORW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111542;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111542: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* RORW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	BusCyclePenalty += 2;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111543;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111543: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* RORW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111544;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111544: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* RORW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_prefetch (4) << 16;
+	dataa |= get_word_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_111545;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (6);
+l_111545: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* ROLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111546;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111546: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ROLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111547;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111547: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* ROLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111548;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (2);
+l_111548: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* ROLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111549;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111549: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ROLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f0_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	BusCyclePenalty += 2;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_111550;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111550: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* ROLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f8_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_111551;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (4);
+l_111551: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* ROLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f9_11)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_prefetch (4) << 16;
+	dataa |= get_word_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_111552;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = get_word_prefetch_addr (dataa);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word_prefetch (dataa, val);
+}}}}}	m68k_incpci (6);
+l_111552: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+#endif
+
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+#endif
+
+#ifdef PART_2
+#endif
+
+#ifdef PART_3
+/* MVSR2.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_40c0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* MVSR2.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40d0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_120002;
+	}
+{	bus_error_offset = 4;
+	put_word_prefetch (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_120002: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (1/2) */
+
+/* MVSR2.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_40d8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_120003;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += 2;
+	put_word_prefetch (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_120003: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (1/2) */
+
+/* MVSR2.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_120004;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+	put_word_prefetch (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_120004: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (1/2) */
+
+/* MVSR2.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_120005;
+	}
+{	bus_error_offset = 4;
+	put_word_prefetch (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_120005: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* MVSR2.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40f0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_120006;
+	}
+{	bus_error_offset = 4;
+	put_word_prefetch (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_120006: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (2/2) */
+
+/* MVSR2.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40f8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_120007;
+	}
+{	bus_error_offset = 4;
+	put_word_prefetch (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_120007: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (2/2) */
+
+/* MVSR2.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40f9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_120008;
+	}
+{	bus_error_offset = 6;
+	put_word_prefetch (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	MakeSR ();
+	put_word_prefetch (srca, regs.sr);
+}}}	m68k_incpci (6);
+l_120008: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* CLR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4200_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* CLR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4210_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_prefetch (srca, 0);
+}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* CLR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4218_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_prefetch (srca, 0);
+}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* CLR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4220_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_prefetch (srca, 0);
+}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* CLR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4228_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_prefetch (srca, 0);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4230_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_prefetch (srca, 0);
+}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* CLR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4238_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_prefetch (srca, 0);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* CLR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4239_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_prefetch (srca, 0);
+}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* CLR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4240_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4 (1/0) */
+
+/* CLR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4250_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_120018;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_prefetch (srca, 0);
+}}}}	m68k_incpci (2);
+l_120018: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* CLR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4258_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_120019;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_prefetch (srca, 0);
+}}}}	m68k_incpci (2);
+l_120019: ;
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* CLR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4260_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_120020;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_prefetch (srca, 0);
+}}}}	m68k_incpci (2);
+l_120020: ;
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* CLR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4268_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_120021;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_prefetch (srca, 0);
+}}}}	m68k_incpci (4);
+l_120021: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4270_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_120022;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_prefetch (srca, 0);
+}}}}	m68k_incpci (4);
+l_120022: ;
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* CLR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4278_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_120023;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_prefetch (srca, 0);
+}}}}	m68k_incpci (4);
+l_120023: ;
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* CLR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4279_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_120024;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = get_word_prefetch_addr (srca);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_prefetch (srca, 0);
+}}}}	m68k_incpci (6);
+l_120024: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* CLR.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4280_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2 + count_cycles;
+} /* 6 (1/0) */
+
+/* CLR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4290_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_120026;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_word_prefetch (srca + 2, 0); put_word_prefetch (srca, 0 >> 16);
+}}}}	m68k_incpci (2);
+l_120026: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* CLR.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4298_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_120027;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_word_prefetch (srca + 2, 0); put_word_prefetch (srca, 0 >> 16);
+}}}}	m68k_incpci (2);
+l_120027: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (3/2) */
+
+/* CLR.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_120028;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	get_word_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_word_prefetch (srca + 2, 0); put_word_prefetch (srca, 0 >> 16);
+}}}}	m68k_incpci (2);
+l_120028: ;
+return 22 * CYCLE_UNIT / 2 + count_cycles;
+} /* 22 (3/2) */
+
+/* CLR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_120029;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_word_prefetch (srca + 2, 0); put_word_prefetch (srca, 0 >> 16);
+}}}}	m68k_incpci (4);
+l_120029: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_42b0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_120030;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_word_prefetch (srca + 2, 0); put_word_prefetch (srca, 0 >> 16);
+}}}}	m68k_incpci (4);
+l_120030: ;
+return 26 * CYCLE_UNIT / 2 + count_cycles;
+} /* 26 (4/2) */
+
+/* CLR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_42b8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_120031;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_word_prefetch (srca + 2, 0); put_word_prefetch (srca, 0 >> 16);
+}}}}	m68k_incpci (4);
+l_120031: ;
+return 24 * CYCLE_UNIT / 2 + count_cycles;
+} /* 24 (4/2) */
+
+/* CLR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_42b9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_120032;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = get_word_prefetch_addr (srca) << 16; src |= get_word_prefetch_addr (srca + 2);
+	regs.ir = regs.irc;
+	get_word_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_word_prefetch (srca + 2, 0); put_word_prefetch (srca, 0 >> 16);
+}}}}	m68k_incpci (6);
+l_120032: ;
+return 28 * CYCLE_UNIT / 2 + count_cycles;
+} /* 28 (5/2) */
+
+#endif
+
+#ifdef PART_4
+/* RTE.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e73_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 45;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_120033; }
+{{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+	if (sra & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, sra);
+		goto l_120033;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 sr = get_word_prefetch_addr (sra);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+	if (pca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, pca);
+		goto l_120033;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 pc = get_word_prefetch_addr (pca) << 16; pc |= get_word_prefetch_addr (pca + 2);
+	m68k_areg (regs, 7) += 4;
+	regs.sr = sr;
+	if (pc & 1) {
+		exception3i (0x4E73, pc);
+		goto l_120033;
+	}
+	m68k_setpci (pc);
+	MakeFromSR();
+	get_word_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_prefetch (2);
+}}}}}}}}l_120033: ;
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (5/0) */
+
+#endif
+
+#ifdef PART_5
+/* Scc.B Dn (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2 + count_cycles;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2 + count_cycles;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	get_word_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2 + count_cycles;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff0_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	BusCyclePenalty += 2;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2 + count_cycles;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff8_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (6);
+{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2 + count_cycles;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff9_12)(uae_u32 opcode)
+{
+	int count_cycles = 0;
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_prefetch (4) << 16;
+	srca |= get_word_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = get_byte_prefetch (srca);
+{	regs.ir = regs.irc;
+	get_word_prefetch (8);
+{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_prefetch (srca, val);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2 + count_cycles;
+} /* 20 (4/1) */
+
+#endif
+
+#ifdef PART_6
+#endif
+
+#ifdef PART_7
+#endif
+
+#ifdef PART_8
+#endif
+
diff --git a/src/cpu/cpuemu_13.c b/src/cpu/cpuemu_13.c
new file mode 100644
index 0000000..7906955
--- /dev/null
+++ b/src/cpu/cpuemu_13.c
@@ -0,0 +1,49116 @@
+#include "main.h"
+#include "sysdeps.h"
+#include "hatari-glue.h"
+#include "maccess.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "cputbl.h"
+#define CPUFUNC(x) x##_ff
+#define SET_CFLG_ALWAYS(x) SET_CFLG(x)
+#define SET_NFLG_ALWAYS(x) SET_NFLG(x)
+#ifdef NOFLAGS
+#include "noflags.h"
+#endif
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+/* OR.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0000_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* OR.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0010_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* OR.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0018_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* OR.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0020_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* OR.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0028_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* OR.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0030_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+} /* 22 (4/1) */
+
+/* OR.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0038_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* OR.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0039_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+} /* 24 (5/1) */
+
+/* ORSR.B #.W */
+void REGPARAM2 CPUFUNC(op_003c_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 20; 
+{	MakeSR ();
+{	uae_s16 src = get_word_ce000_prefetch (4);
+	src &= 0xFF;
+	do_cycles_ce000_internal (8);
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	regs.sr |= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+}}return;
+} /* 20 (3/0) */
+
+/* OR.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0040_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* OR.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0050_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130011;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_130011: ;
+return;
+} /* 16 (3/1) */
+
+/* OR.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0058_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130012;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_130012: ;
+return;
+} /* 16 (3/1) */
+
+/* OR.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0060_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130013;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_130013: ;
+return;
+} /* 18 (3/1) */
+
+/* OR.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0068_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130014;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (6);
+l_130014: ;
+return;
+} /* 20 (4/1) */
+
+/* OR.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0070_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130015;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (6);
+l_130015: ;
+return;
+} /* 22 (4/1) */
+
+/* OR.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0078_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130016;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (6);
+l_130016: ;
+return;
+} /* 20 (4/1) */
+
+/* OR.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0079_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130017;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (8);
+l_130017: ;
+return;
+} /* 24 (5/1) */
+
+/* ORSR.W #.W */
+void REGPARAM2 CPUFUNC(op_007c_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_130018; }
+{	MakeSR ();
+{	uae_s16 src = get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (8);
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	regs.sr |= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+}}}l_130018: ;
+return;
+} /* 20 (3/0) */
+
+/* OR.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0080_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+} /* 16 (3/0) */
+
+/* OR.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0090_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130020;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_130020: ;
+return;
+} /* 28 (5/2) */
+
+/* OR.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0098_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130021;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_130021: ;
+return;
+} /* 28 (5/2) */
+
+/* OR.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_00a0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130022;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_130022: ;
+return;
+} /* 30 (5/2) */
+
+/* OR.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_00a8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130023;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_130023: ;
+return;
+} /* 32 (6/2) */
+
+/* OR.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_00b0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 34; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130024;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_130024: ;
+return;
+} /* 34 (6/2) */
+
+/* OR.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_00b8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130025;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_130025: ;
+return;
+} /* 32 (6/2) */
+
+/* OR.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_00b9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (8) << 16;
+	dsta |= get_word_ce000_prefetch (10);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130026;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (12);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (10);
+l_130026: ;
+return;
+} /* 36 (7/2) */
+
+/* BTST.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_0100_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 31;
+	do_cycles_ce000_internal (2);
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* MVPMR.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_0108_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 16; 
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+{	uae_u16 val;
+	MovepByteNbr=1; val = ((x_get_byte (memp) & 0xff) << 8);
+	MovepByteNbr=2; val += (x_get_byte (memp + 2) & 0xff);
+	MovepByteNbr=0;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}	m68k_incpci (4);
+return;
+} /* 16 (4/0) */
+
+/* BTST.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_0110_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (2/0) */
+
+/* BTST.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_0118_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (2/0) */
+
+/* BTST.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_0120_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (2/0) */
+
+/* BTST.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0128_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* BTST.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0130_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* BTST.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0138_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* BTST.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0139_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (4/0) */
+
+/* BTST.B Dn,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_013a_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 2;
+	dsta += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* BTST.B Dn,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_013b_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* BTST.B Dn,#.B */
+void REGPARAM2 CPUFUNC(op_013c_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = (uae_u8)get_word_ce000_prefetch (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* BCHG.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_0140_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 31;
+	do_cycles_ce000_internal (2);
+	if (src > 15) do_cycles_ce000_internal (2);
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* MVPMR.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_0148_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 24; 
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+{	uae_u32 val;
+	MovepByteNbr=1; val = ((x_get_byte (memp) & 0xff) << 24);
+	MovepByteNbr=2; val += ((x_get_byte (memp + 2) & 0xff) << 16);
+	MovepByteNbr=3; val += ((x_get_byte (memp + 4) & 0xff) << 8);
+	MovepByteNbr=4; val += (x_get_byte (memp + 6) & 0xff);
+	MovepByteNbr=0;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (val);
+}}	m68k_incpci (4);
+return;
+} /* 24 (6/0) */
+
+/* BCHG.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_0150_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* BCHG.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_0158_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* BCHG.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_0160_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* BCHG.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0168_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* BCHG.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0170_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* BCHG.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0178_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* BCHG.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0179_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* BCLR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_0180_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 31;
+	do_cycles_ce000_internal (2);
+	if (src > 15) do_cycles_ce000_internal (2);
+	do_cycles_ce000_internal (2);
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* MVPRM.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0188_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	MovepByteNbr=1; 	x_put_byte (memp, src >> 8);
+	MovepByteNbr=2; 	x_put_byte (memp + 2, src);
+	MovepByteNbr=0;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+}}	m68k_incpci (4);
+return;
+} /* 16 (2/2) */
+
+/* BCLR.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_0190_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* BCLR.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_0198_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* BCLR.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_01a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* BCLR.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_01a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* BCLR.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_01b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* BCLR.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_01b8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* BCLR.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_01b9_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* BSET.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_01c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 31;
+	do_cycles_ce000_internal (2);
+	if (src > 15) do_cycles_ce000_internal (2);
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* MVPRM.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_01c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	MovepByteNbr=1; 	x_put_byte (memp, src >> 24);
+	MovepByteNbr=2; 	x_put_byte (memp + 2, src >> 16);
+	MovepByteNbr=3; 	x_put_byte (memp + 4, src >> 8);
+	MovepByteNbr=4; 	x_put_byte (memp + 6, src);
+	MovepByteNbr=0;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+}}	m68k_incpci (4);
+return;
+} /* 24 (2/4) */
+
+/* BSET.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_01d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* BSET.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_01d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* BSET.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_01e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* BSET.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_01e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* BSET.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_01f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* BSET.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_01f8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* BSET.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_01f9_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* AND.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0200_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* AND.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0210_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* AND.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0218_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* AND.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0220_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* AND.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0228_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* AND.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0230_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+} /* 22 (4/1) */
+
+/* AND.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0238_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* AND.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0239_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+} /* 24 (5/1) */
+
+/* ANDSR.B #.W */
+void REGPARAM2 CPUFUNC(op_023c_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 20; 
+{	MakeSR ();
+{	uae_s16 src = get_word_ce000_prefetch (4);
+	src |= 0xFF00;
+	do_cycles_ce000_internal (8);
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	regs.sr &= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+}}return;
+} /* 20 (3/0) */
+
+/* AND.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0240_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* AND.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0250_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130076;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_130076: ;
+return;
+} /* 16 (3/1) */
+
+/* AND.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0258_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130077;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_130077: ;
+return;
+} /* 16 (3/1) */
+
+/* AND.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0260_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130078;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_130078: ;
+return;
+} /* 18 (3/1) */
+
+/* AND.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0268_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130079;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (6);
+l_130079: ;
+return;
+} /* 20 (4/1) */
+
+/* AND.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0270_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130080;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (6);
+l_130080: ;
+return;
+} /* 22 (4/1) */
+
+/* AND.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0278_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130081;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (6);
+l_130081: ;
+return;
+} /* 20 (4/1) */
+
+/* AND.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0279_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130082;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (8);
+l_130082: ;
+return;
+} /* 24 (5/1) */
+
+/* ANDSR.W #.W */
+void REGPARAM2 CPUFUNC(op_027c_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_130083; }
+{	MakeSR ();
+{	uae_s16 src = get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (8);
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	regs.sr &= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+}}}l_130083: ;
+return;
+} /* 20 (3/0) */
+
+/* AND.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0280_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+} /* 16 (3/0) */
+
+/* AND.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0290_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130085;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_130085: ;
+return;
+} /* 28 (5/2) */
+
+/* AND.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0298_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130086;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_130086: ;
+return;
+} /* 28 (5/2) */
+
+/* AND.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_02a0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130087;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_130087: ;
+return;
+} /* 30 (5/2) */
+
+/* AND.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_02a8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130088;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_130088: ;
+return;
+} /* 32 (6/2) */
+
+/* AND.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_02b0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 34; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130089;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_130089: ;
+return;
+} /* 34 (6/2) */
+
+/* AND.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_02b8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130090;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_130090: ;
+return;
+} /* 32 (6/2) */
+
+/* AND.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_02b9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (8) << 16;
+	dsta |= get_word_ce000_prefetch (10);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130091;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (12);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (10);
+l_130091: ;
+return;
+} /* 36 (7/2) */
+
+/* SUB.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0400_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* SUB.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0410_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* SUB.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0418_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* SUB.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0420_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* SUB.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0428_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* SUB.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0430_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 22 (4/1) */
+
+/* SUB.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0438_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* SUB.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0439_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+} /* 24 (5/1) */
+
+/* SUB.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0440_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* SUB.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0450_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130101;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_130101: ;
+return;
+} /* 16 (3/1) */
+
+/* SUB.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0458_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130102;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_130102: ;
+return;
+} /* 16 (3/1) */
+
+/* SUB.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0460_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130103;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_130103: ;
+return;
+} /* 18 (3/1) */
+
+/* SUB.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0468_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130104;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_130104: ;
+return;
+} /* 20 (4/1) */
+
+/* SUB.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0470_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130105;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_130105: ;
+return;
+} /* 22 (4/1) */
+
+/* SUB.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0478_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130106;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_130106: ;
+return;
+} /* 20 (4/1) */
+
+/* SUB.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0479_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130107;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (8);
+l_130107: ;
+return;
+} /* 24 (5/1) */
+
+/* SUB.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0480_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/0) */
+
+/* SUB.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0490_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130109;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_130109: ;
+return;
+} /* 28 (5/2) */
+
+/* SUB.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0498_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130110;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_130110: ;
+return;
+} /* 28 (5/2) */
+
+/* SUB.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_04a0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130111;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_130111: ;
+return;
+} /* 30 (5/2) */
+
+/* SUB.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_04a8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130112;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (8);
+l_130112: ;
+return;
+} /* 32 (6/2) */
+
+/* SUB.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_04b0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 34; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130113;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (8);
+l_130113: ;
+return;
+} /* 34 (6/2) */
+
+/* SUB.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_04b8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130114;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (8);
+l_130114: ;
+return;
+} /* 32 (6/2) */
+
+/* SUB.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_04b9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (8) << 16;
+	dsta |= get_word_ce000_prefetch (10);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130115;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (12);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (10);
+l_130115: ;
+return;
+} /* 36 (7/2) */
+
+/* ADD.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0600_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* ADD.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0610_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* ADD.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0618_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* ADD.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0620_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* ADD.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0628_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* ADD.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0630_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 22 (4/1) */
+
+/* ADD.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0638_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* ADD.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0639_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+} /* 24 (5/1) */
+
+/* ADD.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0640_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* ADD.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0650_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130125;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_130125: ;
+return;
+} /* 16 (3/1) */
+
+/* ADD.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0658_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130126;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_130126: ;
+return;
+} /* 16 (3/1) */
+
+/* ADD.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0660_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130127;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_130127: ;
+return;
+} /* 18 (3/1) */
+
+/* ADD.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0668_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130128;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_130128: ;
+return;
+} /* 20 (4/1) */
+
+/* ADD.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0670_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130129;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_130129: ;
+return;
+} /* 22 (4/1) */
+
+/* ADD.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0678_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130130;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_130130: ;
+return;
+} /* 20 (4/1) */
+
+/* ADD.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0679_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130131;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (8);
+l_130131: ;
+return;
+} /* 24 (5/1) */
+
+/* ADD.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0680_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/0) */
+
+/* ADD.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0690_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130133;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_130133: ;
+return;
+} /* 28 (5/2) */
+
+/* ADD.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0698_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130134;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_130134: ;
+return;
+} /* 28 (5/2) */
+
+/* ADD.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_06a0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130135;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_130135: ;
+return;
+} /* 30 (5/2) */
+
+/* ADD.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_06a8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130136;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (8);
+l_130136: ;
+return;
+} /* 32 (6/2) */
+
+/* ADD.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_06b0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 34; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130137;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (8);
+l_130137: ;
+return;
+} /* 34 (6/2) */
+
+/* ADD.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_06b8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130138;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (8);
+l_130138: ;
+return;
+} /* 32 (6/2) */
+
+/* ADD.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_06b9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (8) << 16;
+	dsta |= get_word_ce000_prefetch (10);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130139;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (12);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (10);
+l_130139: ;
+return;
+} /* 36 (7/2) */
+
+/* BTST.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0800_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 31;
+	do_cycles_ce000_internal (2);
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (4);
+return;
+} /* 10 (2/0) */
+
+/* BTST.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0810_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* BTST.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0818_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* BTST.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0820_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* BTST.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0828_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (4/0) */
+
+/* BTST.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0830_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return;
+} /* 18 (4/0) */
+
+/* BTST.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0838_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (4/0) */
+
+/* BTST.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0839_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (8);
+return;
+} /* 20 (5/0) */
+
+/* BTST.B #.W,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_083a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (4/0) */
+
+/* BTST.B #.W,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_083b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	tmppc = m68k_getpci () + 4;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return;
+} /* 18 (4/0) */
+
+/* BCHG.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0840_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 31;
+	do_cycles_ce000_internal (2);
+	if (src > 15) do_cycles_ce000_internal (2);
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return;
+} /* 10+ (2/0) */
+
+/* BCHG.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0850_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* BCHG.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0858_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* BCHG.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0860_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* BCHG.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0868_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* BCHG.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0870_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+} /* 22 (4/1) */
+
+/* BCHG.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0878_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* BCHG.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0879_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return;
+} /* 24 (5/1) */
+
+/* BCLR.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0880_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 31;
+	do_cycles_ce000_internal (2);
+	if (src > 15) do_cycles_ce000_internal (2);
+	do_cycles_ce000_internal (2);
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return;
+} /* 12+ (2/0) */
+
+/* BCLR.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0890_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* BCLR.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0898_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* BCLR.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_08a0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* BCLR.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_08a8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* BCLR.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_08b0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+} /* 22 (4/1) */
+
+/* BCLR.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_08b8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* BCLR.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_08b9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return;
+} /* 24 (5/1) */
+
+/* BSET.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_08c0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 31;
+	do_cycles_ce000_internal (2);
+	if (src > 15) do_cycles_ce000_internal (2);
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return;
+} /* 10+ (2/0) */
+
+/* BSET.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_08d0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* BSET.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_08d8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* BSET.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_08e0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* BSET.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_08e8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* BSET.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_08f0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+} /* 22 (4/1) */
+
+/* BSET.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_08f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* BSET.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_08f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	ipl_fetch ();
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return;
+} /* 24 (5/1) */
+
+/* EOR.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0a00_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* EOR.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0a10_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* EOR.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0a18_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* EOR.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0a20_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* EOR.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0a28_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* EOR.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0a30_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+} /* 22 (4/1) */
+
+/* EOR.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0a38_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* EOR.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0a39_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+} /* 24 (5/1) */
+
+/* EORSR.B #.W */
+void REGPARAM2 CPUFUNC(op_0a3c_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 20; 
+{	MakeSR ();
+{	uae_s16 src = get_word_ce000_prefetch (4);
+	src &= 0xFF;
+	do_cycles_ce000_internal (8);
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	regs.sr ^= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+}}return;
+} /* 20 (3/0) */
+
+/* EOR.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0a40_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* EOR.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0a50_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130184;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_130184: ;
+return;
+} /* 16 (3/1) */
+
+/* EOR.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0a58_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130185;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_130185: ;
+return;
+} /* 16 (3/1) */
+
+/* EOR.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0a60_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130186;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_130186: ;
+return;
+} /* 18 (3/1) */
+
+/* EOR.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0a68_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130187;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (6);
+l_130187: ;
+return;
+} /* 20 (4/1) */
+
+/* EOR.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0a70_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130188;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (6);
+l_130188: ;
+return;
+} /* 22 (4/1) */
+
+/* EOR.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0a78_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130189;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (6);
+l_130189: ;
+return;
+} /* 20 (4/1) */
+
+/* EOR.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0a79_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130190;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (8);
+l_130190: ;
+return;
+} /* 24 (5/1) */
+
+/* EORSR.W #.W */
+void REGPARAM2 CPUFUNC(op_0a7c_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_130191; }
+{	MakeSR ();
+{	uae_s16 src = get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (8);
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	regs.sr ^= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+}}}l_130191: ;
+return;
+} /* 20 (3/0) */
+
+/* EOR.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0a80_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+} /* 16 (3/0) */
+
+/* EOR.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0a90_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130193;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_130193: ;
+return;
+} /* 28 (5/2) */
+
+/* EOR.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0a98_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130194;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_130194: ;
+return;
+} /* 28 (5/2) */
+
+/* EOR.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_0aa0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130195;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_130195: ;
+return;
+} /* 30 (5/2) */
+
+/* EOR.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0aa8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130196;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_130196: ;
+return;
+} /* 32 (6/2) */
+
+/* EOR.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0ab0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 34; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130197;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_130197: ;
+return;
+} /* 34 (6/2) */
+
+/* EOR.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0ab8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130198;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (8);
+l_130198: ;
+return;
+} /* 32 (6/2) */
+
+/* EOR.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0ab9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (8) << 16;
+	dsta |= get_word_ce000_prefetch (10);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130199;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (12);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (10);
+l_130199: ;
+return;
+} /* 36 (7/2) */
+
+#endif
+
+#ifdef PART_2
+/* CMP.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0c00_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* CMP.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0c10_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* CMP.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0c18_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* CMP.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0c20_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* CMP.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0c28_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 16 (4/0) */
+
+/* CMP.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0c30_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 18 (4/0) */
+
+/* CMP.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0c38_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 16 (4/0) */
+
+/* CMP.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0c39_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+} /* 20 (5/0) */
+
+/* CMP.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0c40_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* CMP.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0c50_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130209;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_130209: ;
+return;
+} /* 12 (3/0) */
+
+/* CMP.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0c58_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130210;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_130210: ;
+return;
+} /* 12 (3/0) */
+
+/* CMP.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0c60_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130211;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_130211: ;
+return;
+} /* 14 (3/0) */
+
+/* CMP.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0c68_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130212;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_130212: ;
+return;
+} /* 16 (4/0) */
+
+/* CMP.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0c70_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130213;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_130213: ;
+return;
+} /* 18 (4/0) */
+
+/* CMP.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0c78_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130214;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_130214: ;
+return;
+} /* 16 (4/0) */
+
+/* CMP.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0c79_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130215;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (8);
+l_130215: ;
+return;
+} /* 20 (5/0) */
+
+/* CMP.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0c80_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return;
+} /* 14 (3/0) */
+
+/* CMP.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0c90_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130217;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_130217: ;
+return;
+} /* 20 (5/0) */
+
+/* CMP.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0c98_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130218;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_130218: ;
+return;
+} /* 20 (5/0) */
+
+/* CMP.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_0ca0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130219;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_130219: ;
+return;
+} /* 22 (5/0) */
+
+/* CMP.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0ca8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130220;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (8);
+l_130220: ;
+return;
+} /* 24 (6/0) */
+
+/* CMP.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0cb0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 26; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130221;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (8);
+l_130221: ;
+return;
+} /* 26 (6/0) */
+
+/* CMP.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0cb8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130222;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (8);
+l_130222: ;
+return;
+} /* 24 (6/0) */
+
+/* CMP.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0cb9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (8) << 16;
+	dsta |= get_word_ce000_prefetch (10);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130223;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (12);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (10);
+l_130223: ;
+return;
+} /* 28 (7/0) */
+
+/* MOVE.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_1000_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 4 (1/0) */
+
+/* MOVE.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_1010_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 8 (2/0) */
+
+/* MOVE.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_1018_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 8 (2/0) */
+
+/* MOVE.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_1020_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 10 (2/0) */
+
+/* MOVE.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_1028_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 12 (3/0) */
+
+/* MOVE.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_1030_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 14 (3/0) */
+
+/* MOVE.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_1038_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 12 (3/0) */
+
+/* MOVE.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_1039_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 16 (4/0) */
+
+/* MOVE.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_103a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 12 (3/0) */
+
+/* MOVE.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_103b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 14 (3/0) */
+
+/* MOVE.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_103c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 8 (2/0) */
+
+/* MOVE.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_1080_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 8 (1/1) */
+
+/* MOVE.B (An),(An) */
+void REGPARAM2 CPUFUNC(op_1090_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 12 (2/1) */
+
+/* MOVE.B (An)+,(An) */
+void REGPARAM2 CPUFUNC(op_1098_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 12 (2/1) */
+
+/* MOVE.B -(An),(An) */
+void REGPARAM2 CPUFUNC(op_10a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 14 (2/1) */
+
+/* MOVE.B (d16,An),(An) */
+void REGPARAM2 CPUFUNC(op_10a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B (d8,An,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_10b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 18 (3/1) */
+
+/* MOVE.B (xxx).W,(An) */
+void REGPARAM2 CPUFUNC(op_10b8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B (xxx).L,(An) */
+void REGPARAM2 CPUFUNC(op_10b9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 20 (4/1) */
+
+/* MOVE.B (d16,PC),(An) */
+void REGPARAM2 CPUFUNC(op_10ba_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B (d8,PC,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_10bb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 18 (3/1) */
+
+/* MOVE.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_10bc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 12 (2/1) */
+
+/* MOVE.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_10c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 8 (1/1) */
+
+/* MOVE.B (An),(An)+ */
+void REGPARAM2 CPUFUNC(op_10d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 12 (2/1) */
+
+/* MOVE.B (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_10d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 12 (2/1) */
+
+/* MOVE.B -(An),(An)+ */
+void REGPARAM2 CPUFUNC(op_10e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 14 (2/1) */
+
+/* MOVE.B (d16,An),(An)+ */
+void REGPARAM2 CPUFUNC(op_10e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_10f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 18 (3/1) */
+
+/* MOVE.B (xxx).W,(An)+ */
+void REGPARAM2 CPUFUNC(op_10f8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B (xxx).L,(An)+ */
+void REGPARAM2 CPUFUNC(op_10f9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 20 (4/1) */
+
+/* MOVE.B (d16,PC),(An)+ */
+void REGPARAM2 CPUFUNC(op_10fa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_10fb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 18 (3/1) */
+
+/* MOVE.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_10fc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 12 (2/1) */
+
+/* MOVE.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_1100_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return;
+} /* 8 (1/1) */
+
+/* MOVE.B (An),-(An) */
+void REGPARAM2 CPUFUNC(op_1110_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+} /* 12 (2/1) */
+
+/* MOVE.B (An)+,-(An) */
+void REGPARAM2 CPUFUNC(op_1118_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+} /* 12 (2/1) */
+
+/* MOVE.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_1120_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+} /* 14 (2/1) */
+
+/* MOVE.B (d16,An),-(An) */
+void REGPARAM2 CPUFUNC(op_1128_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B (d8,An,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_1130_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+} /* 18 (3/1) */
+
+/* MOVE.B (xxx).W,-(An) */
+void REGPARAM2 CPUFUNC(op_1138_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B (xxx).L,-(An) */
+void REGPARAM2 CPUFUNC(op_1139_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+} /* 20 (4/1) */
+
+/* MOVE.B (d16,PC),-(An) */
+void REGPARAM2 CPUFUNC(op_113a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_113b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+} /* 18 (3/1) */
+
+/* MOVE.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_113c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+} /* 12 (2/1) */
+
+/* MOVE.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1140_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 12 (2/1) */
+
+/* MOVE.B (An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1150_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B (An)+,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1158_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B -(An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1160_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 18 (3/1) */
+
+/* MOVE.B (d16,An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1168_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 20 (4/1) */
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1170_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 22 (4/1) */
+
+/* MOVE.B (xxx).W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1178_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 20 (4/1) */
+
+/* MOVE.B (xxx).L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1179_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 24 (5/1) */
+
+/* MOVE.B (d16,PC),(d16,An) */
+void REGPARAM2 CPUFUNC(op_117a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 20 (4/1) */
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_117b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 22 (4/1) */
+
+/* MOVE.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_117c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_1180_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 14 (2/1) */
+
+/* MOVE.B (An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_1190_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 18 (3/1) */
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_1198_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 18 (3/1) */
+
+/* MOVE.B -(An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 20 (3/1) */
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 22 (4/1) */
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 24 (4/1) */
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11b8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 22 (4/1) */
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11b9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (8));
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 26 (5/1) */
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11ba_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 22 (4/1) */
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11bb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 24 (4/1) */
+
+/* MOVE.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11bc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 18 (3/1) */
+
+/* MOVE.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 12 (2/1) */
+
+/* MOVE.B (An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B (An)+,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B -(An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 18 (3/1) */
+
+/* MOVE.B (d16,An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 20 (4/1) */
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 22 (4/1) */
+
+/* MOVE.B (xxx).W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 20 (4/1) */
+
+/* MOVE.B (xxx).L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 24 (5/1) */
+
+/* MOVE.B (d16,PC),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11fa_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 20 (4/1) */
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11fb_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 22 (4/1) */
+
+/* MOVE.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11fc_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 16 (3/1) */
+
+/* MOVE.B (An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 20 (4/1) */
+
+/* MOVE.B (An)+,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 20 (4/1) */
+
+/* MOVE.B -(An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 22 (4/1) */
+
+/* MOVE.B (d16,An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 24 (5/1) */
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 26 (5/1) */
+
+/* MOVE.B (xxx).W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 24 (5/1) */
+
+/* MOVE.B (xxx).L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (8) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 10;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (10);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 28 (6/1) */
+
+/* MOVE.B (d16,PC),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13fa_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 24 (5/1) */
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13fb_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}return;
+} /* 26 (5/1) */
+
+/* MOVE.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13fc_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 20 (4/1) */
+
+/* MOVE.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_2000_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 4 (1/0) */
+
+/* MOVE.L An,Dn */
+void REGPARAM2 CPUFUNC(op_2008_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 4 (1/0) */
+
+/* MOVE.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_2010_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130314;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130314: ;
+return;
+} /* 12 (3/0) */
+
+/* MOVE.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_2018_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130315;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130315: ;
+return;
+} /* 12 (3/0) */
+
+/* MOVE.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_2020_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130316;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130316: ;
+return;
+} /* 14 (3/0) */
+
+/* MOVE.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_2028_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130317;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130317: ;
+return;
+} /* 16 (4/0) */
+
+/* MOVE.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_2030_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130318;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130318: ;
+return;
+} /* 18 (4/0) */
+
+/* MOVE.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_2038_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130319;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130319: ;
+return;
+} /* 16 (4/0) */
+
+/* MOVE.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_2039_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130320;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130320: ;
+return;
+} /* 20 (5/0) */
+
+/* MOVE.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_203a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130321;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130321: ;
+return;
+} /* 16 (4/0) */
+
+/* MOVE.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_203b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130322;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130322: ;
+return;
+} /* 18 (4/0) */
+
+/* MOVE.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_203c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 12 (3/0) */
+
+/* MOVEA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_2040_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 4 (1/0) */
+
+/* MOVEA.L An,An */
+void REGPARAM2 CPUFUNC(op_2048_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 4 (1/0) */
+
+/* MOVEA.L (An),An */
+void REGPARAM2 CPUFUNC(op_2050_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130326;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130326: ;
+return;
+} /* 12 (3/0) */
+
+/* MOVEA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_2058_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130327;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130327: ;
+return;
+} /* 12 (3/0) */
+
+/* MOVEA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_2060_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130328;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130328: ;
+return;
+} /* 14 (3/0) */
+
+/* MOVEA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_2068_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130329;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130329: ;
+return;
+} /* 16 (4/0) */
+
+/* MOVEA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_2070_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130330;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130330: ;
+return;
+} /* 18 (4/0) */
+
+/* MOVEA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_2078_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130331;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130331: ;
+return;
+} /* 16 (4/0) */
+
+/* MOVEA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_2079_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130332;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130332: ;
+return;
+} /* 20 (5/0) */
+
+/* MOVEA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_207a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130333;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130333: ;
+return;
+} /* 16 (4/0) */
+
+/* MOVEA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_207b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130334;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130334: ;
+return;
+} /* 18 (4/0) */
+
+/* MOVEA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_207c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 12 (3/0) */
+
+/* MOVE.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_2080_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130336;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130336: ;
+return;
+} /* 12 (1/2) */
+
+/* MOVE.L An,(An) */
+void REGPARAM2 CPUFUNC(op_2088_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130337;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130337: ;
+return;
+} /* 12 (1/2) */
+
+/* MOVE.L (An),(An) */
+void REGPARAM2 CPUFUNC(op_2090_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130338;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130338;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130338: ;
+return;
+} /* 20 (3/2) */
+
+/* MOVE.L (An)+,(An) */
+void REGPARAM2 CPUFUNC(op_2098_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130339;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130339;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130339: ;
+return;
+} /* 20 (3/2) */
+
+/* MOVE.L -(An),(An) */
+void REGPARAM2 CPUFUNC(op_20a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130340;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130340;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130340: ;
+return;
+} /* 22 (3/2) */
+
+/* MOVE.L (d16,An),(An) */
+void REGPARAM2 CPUFUNC(op_20a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130341;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130341;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130341: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L (d8,An,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_20b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130342;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130342;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130342: ;
+return;
+} /* 26 (4/2) */
+
+/* MOVE.L (xxx).W,(An) */
+void REGPARAM2 CPUFUNC(op_20b8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130343;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130343;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130343: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L (xxx).L,(An) */
+void REGPARAM2 CPUFUNC(op_20b9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130344;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130344;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130344: ;
+return;
+} /* 28 (5/2) */
+
+/* MOVE.L (d16,PC),(An) */
+void REGPARAM2 CPUFUNC(op_20ba_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130345;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130345;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130345: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L (d8,PC,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_20bb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130346;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130346;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130346: ;
+return;
+} /* 26 (4/2) */
+
+/* MOVE.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_20bc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130347;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130347: ;
+return;
+} /* 20 (3/2) */
+
+/* MOVE.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_20c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130348;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130348: ;
+return;
+} /* 12 (1/2) */
+
+/* MOVE.L An,(An)+ */
+void REGPARAM2 CPUFUNC(op_20c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130349;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130349: ;
+return;
+} /* 12 (1/2) */
+
+/* MOVE.L (An),(An)+ */
+void REGPARAM2 CPUFUNC(op_20d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130350;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130350;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130350: ;
+return;
+} /* 20 (3/2) */
+
+/* MOVE.L (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_20d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130351;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130351;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130351: ;
+return;
+} /* 20 (3/2) */
+
+/* MOVE.L -(An),(An)+ */
+void REGPARAM2 CPUFUNC(op_20e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130352;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130352;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130352: ;
+return;
+} /* 22 (3/2) */
+
+/* MOVE.L (d16,An),(An)+ */
+void REGPARAM2 CPUFUNC(op_20e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130353;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130353;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130353: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_20f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130354;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130354;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130354: ;
+return;
+} /* 26 (4/2) */
+
+/* MOVE.L (xxx).W,(An)+ */
+void REGPARAM2 CPUFUNC(op_20f8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130355;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130355;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130355: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L (xxx).L,(An)+ */
+void REGPARAM2 CPUFUNC(op_20f9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130356;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130356;
+	}
+{	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130356: ;
+return;
+} /* 28 (5/2) */
+
+/* MOVE.L (d16,PC),(An)+ */
+void REGPARAM2 CPUFUNC(op_20fa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130357;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130357;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130357: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_20fb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130358;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130358;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130358: ;
+return;
+} /* 26 (4/2) */
+
+/* MOVE.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_20fc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130359;
+	}
+{	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130359: ;
+return;
+} /* 20 (3/2) */
+
+/* MOVE.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_2100_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130360;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+}}}}l_130360: ;
+return;
+} /* 12 (1/2) */
+
+/* MOVE.L An,-(An) */
+void REGPARAM2 CPUFUNC(op_2108_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130361;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+}}}}l_130361: ;
+return;
+} /* 12 (1/2) */
+
+/* MOVE.L (An),-(An) */
+void REGPARAM2 CPUFUNC(op_2110_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130362;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130362;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+}}}}}}l_130362: ;
+return;
+} /* 20 (3/2) */
+
+/* MOVE.L (An)+,-(An) */
+void REGPARAM2 CPUFUNC(op_2118_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130363;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130363;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+}}}}}}l_130363: ;
+return;
+} /* 20 (3/2) */
+
+/* MOVE.L -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_2120_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130364;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130364;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, src);
+	m68k_incpci (2);
+}}}}}}l_130364: ;
+return;
+} /* 22 (3/2) */
+
+/* MOVE.L (d16,An),-(An) */
+void REGPARAM2 CPUFUNC(op_2128_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130365;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130365;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+}}}}}}l_130365: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L (d8,An,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_2130_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130366;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130366;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+}}}}}}l_130366: ;
+return;
+} /* 26 (4/2) */
+
+/* MOVE.L (xxx).W,-(An) */
+void REGPARAM2 CPUFUNC(op_2138_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130367;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130367;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+}}}}}}l_130367: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L (xxx).L,-(An) */
+void REGPARAM2 CPUFUNC(op_2139_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130368;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130368;
+	}
+{	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+}}}}}}l_130368: ;
+return;
+} /* 28 (5/2) */
+
+/* MOVE.L (d16,PC),-(An) */
+void REGPARAM2 CPUFUNC(op_213a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130369;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130369;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+}}}}}}l_130369: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_213b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130370;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130370;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+}}}}}}l_130370: ;
+return;
+} /* 26 (4/2) */
+
+/* MOVE.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_213c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130371;
+	}
+{	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+}}}}l_130371: ;
+return;
+} /* 20 (3/2) */
+
+/* MOVE.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2140_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130372;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130372: ;
+return;
+} /* 16 (2/2) */
+
+/* MOVE.L An,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2148_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130373;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130373: ;
+return;
+} /* 16 (2/2) */
+
+/* MOVE.L (An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2150_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130374;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130374;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130374: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L (An)+,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2158_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130375;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130375;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130375: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L -(An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2160_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130376;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130376;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130376: ;
+return;
+} /* 26 (4/2) */
+
+/* MOVE.L (d16,An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2168_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130377;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130377;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130377: ;
+return;
+} /* 28 (5/2) */
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2170_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130378;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130378;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130378: ;
+return;
+} /* 30 (5/2) */
+
+/* MOVE.L (xxx).W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2178_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130379;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130379;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130379: ;
+return;
+} /* 28 (5/2) */
+
+/* MOVE.L (xxx).L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2179_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130380;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130380;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130380: ;
+return;
+} /* 32 (6/2) */
+
+/* MOVE.L (d16,PC),(d16,An) */
+void REGPARAM2 CPUFUNC(op_217a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130381;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130381;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130381: ;
+return;
+} /* 28 (5/2) */
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_217b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130382;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130382;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130382: ;
+return;
+} /* 30 (5/2) */
+
+/* MOVE.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_217c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130383;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}}l_130383: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2180_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130384;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130384: ;
+return;
+} /* 18 (2/2) */
+
+/* MOVE.L An,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2188_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130385;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130385: ;
+return;
+} /* 18 (2/2) */
+
+/* MOVE.L (An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2190_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130386;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130386;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130386: ;
+return;
+} /* 26 (4/2) */
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2198_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130387;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130387;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130387: ;
+return;
+} /* 26 (4/2) */
+
+#endif
+
+#ifdef PART_3
+/* MOVE.L -(An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130388;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130388;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130388: ;
+return;
+} /* 28 (4/2) */
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130389;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130389;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130389: ;
+return;
+} /* 30 (5/2) */
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130390;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130390;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130390: ;
+return;
+} /* 32 (5/2) */
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21b8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130391;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130391;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130391: ;
+return;
+} /* 30 (5/2) */
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21b9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 34; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130392;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130392;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130392: ;
+return;
+} /* 34 (6/2) */
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21ba_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130393;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130393;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130393: ;
+return;
+} /* 30 (5/2) */
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21bb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130394;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130394;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130394: ;
+return;
+} /* 32 (5/2) */
+
+/* MOVE.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21bc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130395;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130395: ;
+return;
+} /* 26 (4/2) */
+
+/* MOVE.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130396;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130396: ;
+return;
+} /* 16 (2/2) */
+
+/* MOVE.L An,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130397;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130397: ;
+return;
+} /* 16 (2/2) */
+
+/* MOVE.L (An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130398;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130398;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130398: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L (An)+,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130399;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130399;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130399: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L -(An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130400;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130400;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130400: ;
+return;
+} /* 26 (4/2) */
+
+/* MOVE.L (d16,An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130401;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130401;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130401: ;
+return;
+} /* 28 (5/2) */
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130402;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130402;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130402: ;
+return;
+} /* 30 (5/2) */
+
+/* MOVE.L (xxx).W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130403;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130403;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130403: ;
+return;
+} /* 28 (5/2) */
+
+/* MOVE.L (xxx).L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130404;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130404;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130404: ;
+return;
+} /* 32 (6/2) */
+
+/* MOVE.L (d16,PC),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21fa_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130405;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130405;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130405: ;
+return;
+} /* 28 (5/2) */
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21fb_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130406;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130406;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130406: ;
+return;
+} /* 30 (5/2) */
+
+/* MOVE.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21fc_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130407;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130407: ;
+return;
+} /* 24 (4/2) */
+
+/* MOVE.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130408;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130408: ;
+return;
+} /* 20 (3/2) */
+
+/* MOVE.L An,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130409;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130409: ;
+return;
+} /* 20 (3/2) */
+
+/* MOVE.L (An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130410;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130410;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130410: ;
+return;
+} /* 28 (5/2) */
+
+/* MOVE.L (An)+,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130411;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130411;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130411: ;
+return;
+} /* 28 (5/2) */
+
+/* MOVE.L -(An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130412;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130412;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (6);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130412: ;
+return;
+} /* 30 (5/2) */
+
+/* MOVE.L (d16,An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130413;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130413;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130413: ;
+return;
+} /* 32 (6/2) */
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 34; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130414;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130414;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130414: ;
+return;
+} /* 34 (6/2) */
+
+/* MOVE.L (xxx).W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130415;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130415;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130415: ;
+return;
+} /* 32 (6/2) */
+
+/* MOVE.L (xxx).L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 36; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130416;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (8) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (10);
+		exception3_write(opcode, dsta);
+		goto l_130416;
+	}
+{	bus_error_offset = 10;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (10);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130416: ;
+return;
+} /* 36 (7/2) */
+
+/* MOVE.L (d16,PC),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23fa_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130417;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130417;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130417: ;
+return;
+} /* 32 (6/2) */
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23fb_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 34; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130418;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130418;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130418: ;
+return;
+} /* 34 (6/2) */
+
+/* MOVE.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23fc_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (8) << 16;
+	dsta |= get_word_ce000_prefetch (10);
+	if (dsta & 1) {
+	m68k_incpci (10);
+		exception3_write(opcode, dsta);
+		goto l_130419;
+	}
+{	bus_error_offset = 10;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_word (dsta, src >> 16);
+	x_put_word (dsta + 2, src);
+	m68k_incpci (10);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130419: ;
+return;
+} /* 28 (5/2) */
+
+/* MOVE.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_3000_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 4 (1/0) */
+
+/* MOVE.W An,Dn */
+void REGPARAM2 CPUFUNC(op_3008_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 4 (1/0) */
+
+/* MOVE.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_3010_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130422;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130422: ;
+return;
+} /* 8 (2/0) */
+
+/* MOVE.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_3018_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130423;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130423: ;
+return;
+} /* 8 (2/0) */
+
+/* MOVE.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_3020_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130424;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130424: ;
+return;
+} /* 10 (2/0) */
+
+/* MOVE.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_3028_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130425;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130425: ;
+return;
+} /* 12 (3/0) */
+
+/* MOVE.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_3030_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130426;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130426: ;
+return;
+} /* 14 (3/0) */
+
+/* MOVE.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_3038_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130427;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130427: ;
+return;
+} /* 12 (3/0) */
+
+/* MOVE.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_3039_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130428;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130428: ;
+return;
+} /* 16 (4/0) */
+
+/* MOVE.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_303a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130429;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130429: ;
+return;
+} /* 12 (3/0) */
+
+/* MOVE.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_303b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130430;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130430: ;
+return;
+} /* 14 (3/0) */
+
+/* MOVE.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_303c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 8 (2/0) */
+
+/* MOVEA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_3040_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 4 (1/0) */
+
+/* MOVEA.W An,An */
+void REGPARAM2 CPUFUNC(op_3048_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 4 (1/0) */
+
+/* MOVEA.W (An),An */
+void REGPARAM2 CPUFUNC(op_3050_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130434;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130434: ;
+return;
+} /* 8 (2/0) */
+
+/* MOVEA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_3058_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130435;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130435: ;
+return;
+} /* 8 (2/0) */
+
+/* MOVEA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_3060_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130436;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130436: ;
+return;
+} /* 10 (2/0) */
+
+/* MOVEA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_3068_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130437;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130437: ;
+return;
+} /* 12 (3/0) */
+
+/* MOVEA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_3070_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130438;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130438: ;
+return;
+} /* 14 (3/0) */
+
+/* MOVEA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_3078_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130439;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130439: ;
+return;
+} /* 12 (3/0) */
+
+/* MOVEA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_3079_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130440;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130440: ;
+return;
+} /* 16 (4/0) */
+
+/* MOVEA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_307a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130441;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130441: ;
+return;
+} /* 12 (3/0) */
+
+/* MOVEA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_307b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130442;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130442: ;
+return;
+} /* 14 (3/0) */
+
+/* MOVEA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_307c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 8 (2/0) */
+
+/* MOVE.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_3080_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130444;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130444: ;
+return;
+} /* 8 (1/1) */
+
+/* MOVE.W An,(An) */
+void REGPARAM2 CPUFUNC(op_3088_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130445;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130445: ;
+return;
+} /* 8 (1/1) */
+
+/* MOVE.W (An),(An) */
+void REGPARAM2 CPUFUNC(op_3090_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130446;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130446;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130446: ;
+return;
+} /* 12 (2/1) */
+
+/* MOVE.W (An)+,(An) */
+void REGPARAM2 CPUFUNC(op_3098_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130447;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130447;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130447: ;
+return;
+} /* 12 (2/1) */
+
+/* MOVE.W -(An),(An) */
+void REGPARAM2 CPUFUNC(op_30a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130448;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130448;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130448: ;
+return;
+} /* 14 (2/1) */
+
+/* MOVE.W (d16,An),(An) */
+void REGPARAM2 CPUFUNC(op_30a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130449;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130449;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130449: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W (d8,An,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_30b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130450;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130450;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130450: ;
+return;
+} /* 18 (3/1) */
+
+/* MOVE.W (xxx).W,(An) */
+void REGPARAM2 CPUFUNC(op_30b8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130451;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130451;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130451: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W (xxx).L,(An) */
+void REGPARAM2 CPUFUNC(op_30b9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130452;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130452;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130452: ;
+return;
+} /* 20 (4/1) */
+
+/* MOVE.W (d16,PC),(An) */
+void REGPARAM2 CPUFUNC(op_30ba_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130453;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130453;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130453: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W (d8,PC,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_30bb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130454;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130454;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130454: ;
+return;
+} /* 18 (3/1) */
+
+/* MOVE.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_30bc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130455;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130455: ;
+return;
+} /* 12 (2/1) */
+
+/* MOVE.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_30c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130456;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130456: ;
+return;
+} /* 8 (1/1) */
+
+/* MOVE.W An,(An)+ */
+void REGPARAM2 CPUFUNC(op_30c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130457;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130457: ;
+return;
+} /* 8 (1/1) */
+
+/* MOVE.W (An),(An)+ */
+void REGPARAM2 CPUFUNC(op_30d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130458;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130458;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130458: ;
+return;
+} /* 12 (2/1) */
+
+/* MOVE.W (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_30d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130459;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130459;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130459: ;
+return;
+} /* 12 (2/1) */
+
+/* MOVE.W -(An),(An)+ */
+void REGPARAM2 CPUFUNC(op_30e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130460;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130460;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130460: ;
+return;
+} /* 14 (2/1) */
+
+/* MOVE.W (d16,An),(An)+ */
+void REGPARAM2 CPUFUNC(op_30e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130461;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130461;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130461: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_30f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130462;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130462;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130462: ;
+return;
+} /* 18 (3/1) */
+
+/* MOVE.W (xxx).W,(An)+ */
+void REGPARAM2 CPUFUNC(op_30f8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130463;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130463;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130463: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W (xxx).L,(An)+ */
+void REGPARAM2 CPUFUNC(op_30f9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130464;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130464;
+	}
+{	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130464: ;
+return;
+} /* 20 (4/1) */
+
+/* MOVE.W (d16,PC),(An)+ */
+void REGPARAM2 CPUFUNC(op_30fa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130465;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130465;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130465: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_30fb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130466;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130466;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130466: ;
+return;
+} /* 18 (3/1) */
+
+/* MOVE.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_30fc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130467;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130467: ;
+return;
+} /* 12 (2/1) */
+
+/* MOVE.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_3100_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130468;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}l_130468: ;
+return;
+} /* 8 (1/1) */
+
+/* MOVE.W An,-(An) */
+void REGPARAM2 CPUFUNC(op_3108_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130469;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}l_130469: ;
+return;
+} /* 8 (1/1) */
+
+/* MOVE.W (An),-(An) */
+void REGPARAM2 CPUFUNC(op_3110_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130470;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130470;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}}l_130470: ;
+return;
+} /* 12 (2/1) */
+
+/* MOVE.W (An)+,-(An) */
+void REGPARAM2 CPUFUNC(op_3118_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130471;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130471;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}}l_130471: ;
+return;
+} /* 12 (2/1) */
+
+/* MOVE.W -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_3120_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130472;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130472;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}}l_130472: ;
+return;
+} /* 14 (2/1) */
+
+/* MOVE.W (d16,An),-(An) */
+void REGPARAM2 CPUFUNC(op_3128_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130473;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130473;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}}l_130473: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W (d8,An,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_3130_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130474;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130474;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}}l_130474: ;
+return;
+} /* 18 (3/1) */
+
+/* MOVE.W (xxx).W,-(An) */
+void REGPARAM2 CPUFUNC(op_3138_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130475;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130475;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}}l_130475: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W (xxx).L,-(An) */
+void REGPARAM2 CPUFUNC(op_3139_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130476;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130476;
+	}
+{	bus_error_offset = 8;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}}}l_130476: ;
+return;
+} /* 20 (4/1) */
+
+/* MOVE.W (d16,PC),-(An) */
+void REGPARAM2 CPUFUNC(op_313a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130477;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130477;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}}l_130477: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_313b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130478;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130478;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}}l_130478: ;
+return;
+} /* 18 (3/1) */
+
+/* MOVE.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_313c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130479;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}l_130479: ;
+return;
+} /* 12 (2/1) */
+
+/* MOVE.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3140_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130480;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130480: ;
+return;
+} /* 12 (2/1) */
+
+/* MOVE.W An,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3148_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130481;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130481: ;
+return;
+} /* 12 (2/1) */
+
+/* MOVE.W (An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3150_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130482;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130482;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130482: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W (An)+,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3158_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130483;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130483;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130483: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W -(An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3160_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130484;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130484;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130484: ;
+return;
+} /* 18 (3/1) */
+
+/* MOVE.W (d16,An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3168_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130485;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130485;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130485: ;
+return;
+} /* 20 (4/1) */
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3170_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130486;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130486;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130486: ;
+return;
+} /* 22 (4/1) */
+
+/* MOVE.W (xxx).W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3178_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130487;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130487;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130487: ;
+return;
+} /* 20 (4/1) */
+
+/* MOVE.W (xxx).L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3179_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130488;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130488;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130488: ;
+return;
+} /* 24 (5/1) */
+
+/* MOVE.W (d16,PC),(d16,An) */
+void REGPARAM2 CPUFUNC(op_317a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130489;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130489;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130489: ;
+return;
+} /* 20 (4/1) */
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_317b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130490;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130490;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130490: ;
+return;
+} /* 22 (4/1) */
+
+/* MOVE.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_317c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130491;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130491: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3180_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130492;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130492: ;
+return;
+} /* 14 (2/1) */
+
+/* MOVE.W An,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3188_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130493;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130493: ;
+return;
+} /* 14 (2/1) */
+
+/* MOVE.W (An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3190_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130494;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130494;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130494: ;
+return;
+} /* 18 (3/1) */
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3198_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130495;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130495;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130495: ;
+return;
+} /* 18 (3/1) */
+
+/* MOVE.W -(An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130496;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130496;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130496: ;
+return;
+} /* 20 (3/1) */
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130497;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130497;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130497: ;
+return;
+} /* 22 (4/1) */
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130498;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130498;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130498: ;
+return;
+} /* 24 (4/1) */
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31b8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130499;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130499;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130499: ;
+return;
+} /* 22 (4/1) */
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31b9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130500;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (8));
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130500;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130500: ;
+return;
+} /* 26 (5/1) */
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31ba_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130501;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130501;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130501: ;
+return;
+} /* 22 (4/1) */
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31bb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130502;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130502;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130502: ;
+return;
+} /* 24 (4/1) */
+
+/* MOVE.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31bc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130503;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130503: ;
+return;
+} /* 18 (3/1) */
+
+/* MOVE.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130504;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130504: ;
+return;
+} /* 12 (2/1) */
+
+/* MOVE.W An,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130505;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130505: ;
+return;
+} /* 12 (2/1) */
+
+/* MOVE.W (An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130506;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130506;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130506: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W (An)+,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130507;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130507;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130507: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W -(An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130508;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130508;
+	}
+{	bus_error_offset = 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130508: ;
+return;
+} /* 18 (3/1) */
+
+/* MOVE.W (d16,An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130509;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130509;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130509: ;
+return;
+} /* 20 (4/1) */
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130510;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130510;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130510: ;
+return;
+} /* 22 (4/1) */
+
+/* MOVE.W (xxx).W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130511;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130511;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130511: ;
+return;
+} /* 20 (4/1) */
+
+/* MOVE.W (xxx).L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130512;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130512;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130512: ;
+return;
+} /* 24 (5/1) */
+
+/* MOVE.W (d16,PC),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31fa_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130513;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130513;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130513: ;
+return;
+} /* 20 (4/1) */
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31fb_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130514;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130514;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130514: ;
+return;
+} /* 22 (4/1) */
+
+/* MOVE.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31fc_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130515;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130515: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130516;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130516: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W An,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130517;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130517: ;
+return;
+} /* 16 (3/1) */
+
+/* MOVE.W (An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130518;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130518;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130518: ;
+return;
+} /* 20 (4/1) */
+
+/* MOVE.W (An)+,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130519;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130519;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130519: ;
+return;
+} /* 20 (4/1) */
+
+/* MOVE.W -(An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130520;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130520;
+	}
+{	bus_error_offset = 6;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130520: ;
+return;
+} /* 22 (4/1) */
+
+/* MOVE.W (d16,An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130521;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130521;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130521: ;
+return;
+} /* 24 (5/1) */
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130522;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130522;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130522: ;
+return;
+} /* 26 (5/1) */
+
+/* MOVE.W (xxx).W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130523;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130523;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130523: ;
+return;
+} /* 24 (5/1) */
+
+/* MOVE.W (xxx).L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130524;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (8) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (10);
+		exception3_write(opcode, dsta);
+		goto l_130524;
+	}
+{	bus_error_offset = 10;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (10);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130524: ;
+return;
+} /* 28 (6/1) */
+
+/* MOVE.W (d16,PC),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33fa_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130525;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130525;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130525: ;
+return;
+} /* 24 (5/1) */
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33fb_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130526;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= regs.irc;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130526;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}l_130526: ;
+return;
+} /* 26 (5/1) */
+
+/* MOVE.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33fc_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (6) << 16;
+	dsta |= get_word_ce000_prefetch (8);
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130527;
+	}
+{	bus_error_offset = 8;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130527: ;
+return;
+} /* 20 (4/1) */
+
+/* NEGX.B Dn */
+void REGPARAM2 CPUFUNC(op_4000_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* NEGX.B (An) */
+void REGPARAM2 CPUFUNC(op_4010_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* NEGX.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4018_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* NEGX.B -(An) */
+void REGPARAM2 CPUFUNC(op_4020_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* NEGX.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4028_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* NEGX.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4030_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* NEGX.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4038_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* NEGX.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4039_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* NEGX.W Dn */
+void REGPARAM2 CPUFUNC(op_4040_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* NEGX.W (An) */
+void REGPARAM2 CPUFUNC(op_4050_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130537;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, newv);
+}}}}}}	m68k_incpci (2);
+l_130537: ;
+return;
+} /* 12 (2/1) */
+
+/* NEGX.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4058_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130538;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, newv);
+}}}}}}	m68k_incpci (2);
+l_130538: ;
+return;
+} /* 12 (2/1) */
+
+/* NEGX.W -(An) */
+void REGPARAM2 CPUFUNC(op_4060_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130539;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, newv);
+}}}}}}	m68k_incpci (2);
+l_130539: ;
+return;
+} /* 14 (2/1) */
+
+/* NEGX.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4068_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130540;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, newv);
+}}}}}}	m68k_incpci (4);
+l_130540: ;
+return;
+} /* 16 (3/1) */
+
+/* NEGX.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4070_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130541;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, newv);
+}}}}}}	m68k_incpci (4);
+l_130541: ;
+return;
+} /* 18 (3/1) */
+
+/* NEGX.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4078_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130542;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, newv);
+}}}}}}	m68k_incpci (4);
+l_130542: ;
+return;
+} /* 16 (3/1) */
+
+/* NEGX.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4079_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130543;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, newv);
+}}}}}}	m68k_incpci (6);
+l_130543: ;
+return;
+} /* 20 (4/1) */
+
+/* NEGX.L Dn */
+void REGPARAM2 CPUFUNC(op_4080_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* NEGX.L (An) */
+void REGPARAM2 CPUFUNC(op_4090_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130545;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_word (srca + 2, newv);
+	ipl_fetch ();
+x_put_word (srca, newv >> 16);
+}}}}}}	m68k_incpci (2);
+l_130545: ;
+return;
+} /* 20 (3/2) */
+
+/* NEGX.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4098_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130546;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_word (srca + 2, newv);
+	ipl_fetch ();
+x_put_word (srca, newv >> 16);
+}}}}}}	m68k_incpci (2);
+l_130546: ;
+return;
+} /* 20 (3/2) */
+
+/* NEGX.L -(An) */
+void REGPARAM2 CPUFUNC(op_40a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130547;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_word (srca + 2, newv);
+	ipl_fetch ();
+x_put_word (srca, newv >> 16);
+}}}}}}	m68k_incpci (2);
+l_130547: ;
+return;
+} /* 22 (3/2) */
+
+/* NEGX.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_40a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130548;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_word (srca + 2, newv);
+	ipl_fetch ();
+x_put_word (srca, newv >> 16);
+}}}}}}	m68k_incpci (4);
+l_130548: ;
+return;
+} /* 24 (4/2) */
+
+/* NEGX.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_40b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130549;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_word (srca + 2, newv);
+	ipl_fetch ();
+x_put_word (srca, newv >> 16);
+}}}}}}	m68k_incpci (4);
+l_130549: ;
+return;
+} /* 26 (4/2) */
+
+/* NEGX.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_40b8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130550;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_word (srca + 2, newv);
+	ipl_fetch ();
+x_put_word (srca, newv >> 16);
+}}}}}}	m68k_incpci (4);
+l_130550: ;
+return;
+} /* 24 (4/2) */
+
+/* NEGX.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_40b9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130551;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_word (srca + 2, newv);
+	ipl_fetch ();
+x_put_word (srca, newv >> 16);
+}}}}}}	m68k_incpci (6);
+l_130551: ;
+return;
+} /* 28 (5/2) */
+
+/* MVSR2.W Dn */
+void REGPARAM2 CPUFUNC(op_40c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{if (!regs.s) { Exception (8); goto l_130552; }
+{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}}	m68k_incpci (2);
+l_130552: ;
+return;
+} /* 6 (1/0) */
+
+/* MVSR2.W (An) */
+void REGPARAM2 CPUFUNC(op_40d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_130553; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130553;
+	}
+{	bus_error_offset = 4;
+	x_put_word (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr);
+}}}}	m68k_incpci (2);
+l_130553: ;
+return;
+} /* 12 (1/2) */
+
+/* MVSR2.W (An)+ */
+void REGPARAM2 CPUFUNC(op_40d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_130554; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130554;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += 2;
+	x_put_word (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr);
+}}}}	m68k_incpci (2);
+l_130554: ;
+return;
+} /* 12 (1/2) */
+
+/* MVSR2.W -(An) */
+void REGPARAM2 CPUFUNC(op_40e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 14; 
+{if (!regs.s) { Exception (8); goto l_130555; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130555;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+	x_put_word (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr);
+}}}}	m68k_incpci (2);
+l_130555: ;
+return;
+} /* 14 (1/2) */
+
+/* MVSR2.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_40e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_130556; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130556;
+	}
+{	bus_error_offset = 4;
+	x_put_word (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr);
+}}}}	m68k_incpci (4);
+l_130556: ;
+return;
+} /* 16 (2/2) */
+
+/* MVSR2.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_40f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 18; 
+{if (!regs.s) { Exception (8); goto l_130557; }
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130557;
+	}
+{	bus_error_offset = 4;
+	x_put_word (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr);
+}}}}	m68k_incpci (4);
+l_130557: ;
+return;
+} /* 18 (2/2) */
+
+/* MVSR2.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_40f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_130558; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130558;
+	}
+{	bus_error_offset = 4;
+	x_put_word (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr);
+}}}}	m68k_incpci (4);
+l_130558: ;
+return;
+} /* 16 (2/2) */
+
+/* MVSR2.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_40f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_130559; }
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130559;
+	}
+{	bus_error_offset = 6;
+	x_put_word (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr);
+}}}}	m68k_incpci (6);
+l_130559: ;
+return;
+} /* 20 (3/2) */
+
+/* CHK.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_4180_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	do_cycles_ce000_internal (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_130560;
+	}
+	do_cycles_ce000_internal (2);
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_130560;
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}l_130560: ;
+return;
+} /* 10 (1/0) */
+
+/* CHK.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_4190_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130561;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	do_cycles_ce000_internal (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_130561;
+	}
+	do_cycles_ce000_internal (2);
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_130561;
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130561: ;
+return;
+} /* 14 (2/0) */
+
+/* CHK.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_4198_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130562;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	do_cycles_ce000_internal (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_130562;
+	}
+	do_cycles_ce000_internal (2);
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_130562;
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130562: ;
+return;
+} /* 14 (2/0) */
+
+/* CHK.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_41a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130563;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	do_cycles_ce000_internal (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_130563;
+	}
+	do_cycles_ce000_internal (2);
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_130563;
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130563: ;
+return;
+} /* 16 (2/0) */
+
+/* CHK.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_41a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130564;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	do_cycles_ce000_internal (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_130564;
+	}
+	do_cycles_ce000_internal (2);
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_130564;
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130564: ;
+return;
+} /* 18 (3/0) */
+
+/* CHK.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_41b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130565;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	do_cycles_ce000_internal (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_130565;
+	}
+	do_cycles_ce000_internal (2);
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_130565;
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130565: ;
+return;
+} /* 20 (3/0) */
+
+/* CHK.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_41b8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130566;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	do_cycles_ce000_internal (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_130566;
+	}
+	do_cycles_ce000_internal (2);
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_130566;
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130566: ;
+return;
+} /* 18 (3/0) */
+
+/* CHK.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_41b9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130567;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	do_cycles_ce000_internal (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_130567;
+	}
+	do_cycles_ce000_internal (2);
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_130567;
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130567: ;
+return;
+} /* 22 (4/0) */
+
+/* CHK.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_41ba_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130568;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	do_cycles_ce000_internal (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_130568;
+	}
+	do_cycles_ce000_internal (2);
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_130568;
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130568: ;
+return;
+} /* 18 (3/0) */
+
+/* CHK.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_41bb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130569;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	do_cycles_ce000_internal (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_130569;
+	}
+	do_cycles_ce000_internal (2);
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_130569;
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130569: ;
+return;
+} /* 20 (3/0) */
+
+/* CHK.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_41bc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	do_cycles_ce000_internal (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_130570;
+	}
+	do_cycles_ce000_internal (2);
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_130570;
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}l_130570: ;
+return;
+} /* 14 (2/0) */
+
+/* LEA.L (An),An */
+void REGPARAM2 CPUFUNC(op_41d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* LEA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_41e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* LEA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_41f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 12; 
+{	do_cycles_ce000_internal (2);
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+{	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return;
+} /* 12 (2/0) */
+
+/* LEA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_41f8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* LEA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_41f9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (6);
+return;
+} /* 12 (3/0) */
+
+/* LEA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_41fa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* LEA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_41fb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 12; 
+{	do_cycles_ce000_internal (2);
+{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+{	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return;
+} /* 12 (2/0) */
+
+/* CLR.B Dn */
+void REGPARAM2 CPUFUNC(op_4200_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* CLR.B (An) */
+void REGPARAM2 CPUFUNC(op_4210_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* CLR.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4218_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* CLR.B -(An) */
+void REGPARAM2 CPUFUNC(op_4220_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* CLR.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4228_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, 0);
+}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* CLR.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4230_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, 0);
+}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* CLR.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4238_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, 0);
+}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* CLR.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4239_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, 0);
+}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* CLR.W Dn */
+void REGPARAM2 CPUFUNC(op_4240_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* CLR.W (An) */
+void REGPARAM2 CPUFUNC(op_4250_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130587;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, 0);
+}}}	m68k_incpci (2);
+l_130587: ;
+return;
+} /* 8 (1/1) */
+
+/* CLR.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4258_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130588;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, 0);
+}}}	m68k_incpci (2);
+l_130588: ;
+return;
+} /* 8 (1/1) */
+
+/* CLR.W -(An) */
+void REGPARAM2 CPUFUNC(op_4260_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130589;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, 0);
+}}}	m68k_incpci (2);
+l_130589: ;
+return;
+} /* 10 (1/1) */
+
+/* CLR.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4268_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130590;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, 0);
+}}}	m68k_incpci (4);
+l_130590: ;
+return;
+} /* 12 (2/1) */
+
+/* CLR.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4270_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130591;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, 0);
+}}}	m68k_incpci (4);
+l_130591: ;
+return;
+} /* 14 (2/1) */
+
+/* CLR.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4278_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130592;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, 0);
+}}}	m68k_incpci (4);
+l_130592: ;
+return;
+} /* 12 (2/1) */
+
+/* CLR.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4279_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130593;
+	}
+{	bus_error_offset = 6;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, 0);
+}}}	m68k_incpci (6);
+l_130593: ;
+return;
+} /* 16 (3/1) */
+
+/* CLR.L Dn */
+void REGPARAM2 CPUFUNC(op_4280_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* CLR.L (An) */
+void REGPARAM2 CPUFUNC(op_4290_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130595;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_word (srca + 2, 0);
+	ipl_fetch ();
+x_put_word (srca, 0 >> 16);
+}}}	m68k_incpci (2);
+l_130595: ;
+return;
+} /* 12 (1/2) */
+
+/* CLR.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4298_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130596;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_word (srca + 2, 0);
+	ipl_fetch ();
+x_put_word (srca, 0 >> 16);
+}}}	m68k_incpci (2);
+l_130596: ;
+return;
+} /* 12 (1/2) */
+
+/* CLR.L -(An) */
+void REGPARAM2 CPUFUNC(op_42a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130597;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_word (srca + 2, 0);
+	ipl_fetch ();
+x_put_word (srca, 0 >> 16);
+}}}	m68k_incpci (2);
+l_130597: ;
+return;
+} /* 14 (1/2) */
+
+/* CLR.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_42a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130598;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_word (srca + 2, 0);
+	ipl_fetch ();
+x_put_word (srca, 0 >> 16);
+}}}	m68k_incpci (4);
+l_130598: ;
+return;
+} /* 16 (2/2) */
+
+/* CLR.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_42b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130599;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_word (srca + 2, 0);
+	ipl_fetch ();
+x_put_word (srca, 0 >> 16);
+}}}	m68k_incpci (4);
+l_130599: ;
+return;
+} /* 18 (2/2) */
+
+/* CLR.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_42b8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130600;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_word (srca + 2, 0);
+	ipl_fetch ();
+x_put_word (srca, 0 >> 16);
+}}}	m68k_incpci (4);
+l_130600: ;
+return;
+} /* 16 (2/2) */
+
+/* CLR.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_42b9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130601;
+	}
+{	bus_error_offset = 6;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_word (srca + 2, 0);
+	ipl_fetch ();
+x_put_word (srca, 0 >> 16);
+}}}	m68k_incpci (6);
+l_130601: ;
+return;
+} /* 20 (3/2) */
+
+/* MVSR2.B Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
+}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+#endif
+/* MVSR2.B (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130603;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr & 0xff);
+}}}	m68k_incpci (2);
+l_130603: ;
+return;
+} /* 8 (1/1) */
+
+#endif
+/* MVSR2.B (An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130604;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr & 0xff);
+}}}	m68k_incpci (2);
+l_130604: ;
+return;
+} /* 8 (1/1) */
+
+#endif
+/* MVSR2.B -(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130605;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr & 0xff);
+}}}	m68k_incpci (2);
+l_130605: ;
+return;
+} /* 10 (1/1) */
+
+#endif
+/* MVSR2.B (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130606;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr & 0xff);
+}}}	m68k_incpci (4);
+l_130606: ;
+return;
+} /* 12 (2/1) */
+
+#endif
+/* MVSR2.B (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130607;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr & 0xff);
+}}}	m68k_incpci (4);
+l_130607: ;
+return;
+} /* 14 (2/1) */
+
+#endif
+/* MVSR2.B (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_130608;
+	}
+{	bus_error_offset = 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr & 0xff);
+}}}	m68k_incpci (4);
+l_130608: ;
+return;
+} /* 12 (2/1) */
+
+#endif
+/* MVSR2.B (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130609;
+	}
+{	bus_error_offset = 6;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr & 0xff);
+}}}	m68k_incpci (6);
+l_130609: ;
+return;
+} /* 16 (3/1) */
+
+#endif
+/* NEG.B Dn */
+void REGPARAM2 CPUFUNC(op_4400_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+#endif
+
+#ifdef PART_4
+/* NEG.B (An) */
+void REGPARAM2 CPUFUNC(op_4410_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* NEG.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4418_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* NEG.B -(An) */
+void REGPARAM2 CPUFUNC(op_4420_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* NEG.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4428_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* NEG.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4430_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* NEG.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4438_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* NEG.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4439_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* NEG.W Dn */
+void REGPARAM2 CPUFUNC(op_4440_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* NEG.W (An) */
+void REGPARAM2 CPUFUNC(op_4450_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130619;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (srca, dst);
+}}}}}}}	m68k_incpci (2);
+l_130619: ;
+return;
+} /* 12 (2/1) */
+
+/* NEG.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4458_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130620;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (srca, dst);
+}}}}}}}	m68k_incpci (2);
+l_130620: ;
+return;
+} /* 12 (2/1) */
+
+/* NEG.W -(An) */
+void REGPARAM2 CPUFUNC(op_4460_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130621;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (srca, dst);
+}}}}}}}	m68k_incpci (2);
+l_130621: ;
+return;
+} /* 14 (2/1) */
+
+/* NEG.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4468_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130622;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (srca, dst);
+}}}}}}}	m68k_incpci (4);
+l_130622: ;
+return;
+} /* 16 (3/1) */
+
+/* NEG.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4470_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130623;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (srca, dst);
+}}}}}}}	m68k_incpci (4);
+l_130623: ;
+return;
+} /* 18 (3/1) */
+
+/* NEG.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4478_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130624;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (srca, dst);
+}}}}}}}	m68k_incpci (4);
+l_130624: ;
+return;
+} /* 16 (3/1) */
+
+/* NEG.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4479_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130625;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (srca, dst);
+}}}}}}}	m68k_incpci (6);
+l_130625: ;
+return;
+} /* 20 (4/1) */
+
+/* NEG.L Dn */
+void REGPARAM2 CPUFUNC(op_4480_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* NEG.L (An) */
+void REGPARAM2 CPUFUNC(op_4490_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130627;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca + 2, dst);
+	ipl_fetch ();
+x_put_word (srca, dst >> 16);
+}}}}}}}	m68k_incpci (2);
+l_130627: ;
+return;
+} /* 20 (3/2) */
+
+/* NEG.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4498_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130628;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca + 2, dst);
+	ipl_fetch ();
+x_put_word (srca, dst >> 16);
+}}}}}}}	m68k_incpci (2);
+l_130628: ;
+return;
+} /* 20 (3/2) */
+
+/* NEG.L -(An) */
+void REGPARAM2 CPUFUNC(op_44a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130629;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca + 2, dst);
+	ipl_fetch ();
+x_put_word (srca, dst >> 16);
+}}}}}}}	m68k_incpci (2);
+l_130629: ;
+return;
+} /* 22 (3/2) */
+
+/* NEG.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_44a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130630;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca + 2, dst);
+	ipl_fetch ();
+x_put_word (srca, dst >> 16);
+}}}}}}}	m68k_incpci (4);
+l_130630: ;
+return;
+} /* 24 (4/2) */
+
+/* NEG.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_44b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130631;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca + 2, dst);
+	ipl_fetch ();
+x_put_word (srca, dst >> 16);
+}}}}}}}	m68k_incpci (4);
+l_130631: ;
+return;
+} /* 26 (4/2) */
+
+/* NEG.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_44b8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130632;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca + 2, dst);
+	ipl_fetch ();
+x_put_word (srca, dst >> 16);
+}}}}}}}	m68k_incpci (4);
+l_130632: ;
+return;
+} /* 24 (4/2) */
+
+/* NEG.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_44b9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130633;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca + 2, dst);
+	ipl_fetch ();
+x_put_word (srca, dst >> 16);
+}}}}}}}	m68k_incpci (6);
+l_130633: ;
+return;
+} /* 28 (5/2) */
+
+/* MV2SR.B Dn */
+void REGPARAM2 CPUFUNC(op_44c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	do_cycles_ce000_internal (4);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}return;
+} /* 12 (2/0) */
+
+/* MV2SR.B (An) */
+void REGPARAM2 CPUFUNC(op_44d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130635;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	do_cycles_ce000_internal (4);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130635: ;
+return;
+} /* 16 (3/0) */
+
+/* MV2SR.B (An)+ */
+void REGPARAM2 CPUFUNC(op_44d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130636;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	do_cycles_ce000_internal (4);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130636: ;
+return;
+} /* 16 (3/0) */
+
+/* MV2SR.B -(An) */
+void REGPARAM2 CPUFUNC(op_44e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130637;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	do_cycles_ce000_internal (4);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130637: ;
+return;
+} /* 18 (3/0) */
+
+/* MV2SR.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_44e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130638;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	do_cycles_ce000_internal (4);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130638: ;
+return;
+} /* 20 (4/0) */
+
+/* MV2SR.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_44f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130639;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	do_cycles_ce000_internal (4);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130639: ;
+return;
+} /* 22 (4/0) */
+
+/* MV2SR.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_44f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130640;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	do_cycles_ce000_internal (4);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130640: ;
+return;
+} /* 20 (4/0) */
+
+/* MV2SR.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_44f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130641;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+	do_cycles_ce000_internal (4);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (6);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130641: ;
+return;
+} /* 24 (5/0) */
+
+/* MV2SR.B (d16,PC) */
+void REGPARAM2 CPUFUNC(op_44fa_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130642;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	do_cycles_ce000_internal (4);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130642: ;
+return;
+} /* 20 (4/0) */
+
+/* MV2SR.B (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_44fb_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 22; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130643;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	do_cycles_ce000_internal (4);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}l_130643: ;
+return;
+} /* 22 (4/0) */
+
+/* MV2SR.B #.B */
+void REGPARAM2 CPUFUNC(op_44fc_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}return;
+} /* 16 (3/0) */
+
+/* NOT.B Dn */
+void REGPARAM2 CPUFUNC(op_4600_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* NOT.B (An) */
+void REGPARAM2 CPUFUNC(op_4610_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* NOT.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4618_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* NOT.B -(An) */
+void REGPARAM2 CPUFUNC(op_4620_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* NOT.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4628_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* NOT.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4630_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* NOT.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4638_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* NOT.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4639_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* NOT.W Dn */
+void REGPARAM2 CPUFUNC(op_4640_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* NOT.W (An) */
+void REGPARAM2 CPUFUNC(op_4650_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130654;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, dst);
+}}}}}	m68k_incpci (2);
+l_130654: ;
+return;
+} /* 12 (2/1) */
+
+/* NOT.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4658_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130655;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, dst);
+}}}}}	m68k_incpci (2);
+l_130655: ;
+return;
+} /* 12 (2/1) */
+
+/* NOT.W -(An) */
+void REGPARAM2 CPUFUNC(op_4660_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130656;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, dst);
+}}}}}	m68k_incpci (2);
+l_130656: ;
+return;
+} /* 14 (2/1) */
+
+/* NOT.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4668_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130657;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, dst);
+}}}}}	m68k_incpci (4);
+l_130657: ;
+return;
+} /* 16 (3/1) */
+
+/* NOT.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4670_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130658;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, dst);
+}}}}}	m68k_incpci (4);
+l_130658: ;
+return;
+} /* 18 (3/1) */
+
+/* NOT.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4678_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130659;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, dst);
+}}}}}	m68k_incpci (4);
+l_130659: ;
+return;
+} /* 16 (3/1) */
+
+/* NOT.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4679_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130660;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, dst);
+}}}}}	m68k_incpci (6);
+l_130660: ;
+return;
+} /* 20 (4/1) */
+
+/* NOT.L Dn */
+void REGPARAM2 CPUFUNC(op_4680_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* NOT.L (An) */
+void REGPARAM2 CPUFUNC(op_4690_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130662;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_word (srca + 2, dst);
+	ipl_fetch ();
+x_put_word (srca, dst >> 16);
+}}}}}	m68k_incpci (2);
+l_130662: ;
+return;
+} /* 20 (3/2) */
+
+/* NOT.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4698_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130663;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_word (srca + 2, dst);
+	ipl_fetch ();
+x_put_word (srca, dst >> 16);
+}}}}}	m68k_incpci (2);
+l_130663: ;
+return;
+} /* 20 (3/2) */
+
+/* NOT.L -(An) */
+void REGPARAM2 CPUFUNC(op_46a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130664;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_word (srca + 2, dst);
+	ipl_fetch ();
+x_put_word (srca, dst >> 16);
+}}}}}	m68k_incpci (2);
+l_130664: ;
+return;
+} /* 22 (3/2) */
+
+/* NOT.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_46a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130665;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_word (srca + 2, dst);
+	ipl_fetch ();
+x_put_word (srca, dst >> 16);
+}}}}}	m68k_incpci (4);
+l_130665: ;
+return;
+} /* 24 (4/2) */
+
+/* NOT.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_46b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130666;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_word (srca + 2, dst);
+	ipl_fetch ();
+x_put_word (srca, dst >> 16);
+}}}}}	m68k_incpci (4);
+l_130666: ;
+return;
+} /* 26 (4/2) */
+
+/* NOT.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_46b8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130667;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_word (srca + 2, dst);
+	ipl_fetch ();
+x_put_word (srca, dst >> 16);
+}}}}}	m68k_incpci (4);
+l_130667: ;
+return;
+} /* 24 (4/2) */
+
+/* NOT.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_46b9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130668;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_word (srca + 2, dst);
+	ipl_fetch ();
+x_put_word (srca, dst >> 16);
+}}}}}	m68k_incpci (6);
+l_130668: ;
+return;
+} /* 28 (5/2) */
+
+/* MV2SR.W Dn */
+void REGPARAM2 CPUFUNC(op_46c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_130669; }
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	do_cycles_ce000_internal (4);
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}l_130669: ;
+return;
+} /* 12 (2/0) */
+
+/* MV2SR.W (An) */
+void REGPARAM2 CPUFUNC(op_46d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_130670; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130670;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	do_cycles_ce000_internal (4);
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130670: ;
+return;
+} /* 16 (3/0) */
+
+/* MV2SR.W (An)+ */
+void REGPARAM2 CPUFUNC(op_46d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_130671; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130671;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	do_cycles_ce000_internal (4);
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130671: ;
+return;
+} /* 16 (3/0) */
+
+/* MV2SR.W -(An) */
+void REGPARAM2 CPUFUNC(op_46e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 18; 
+{if (!regs.s) { Exception (8); goto l_130672; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130672;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	do_cycles_ce000_internal (4);
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130672: ;
+return;
+} /* 18 (3/0) */
+
+/* MV2SR.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_46e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_130673; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130673;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	do_cycles_ce000_internal (4);
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130673: ;
+return;
+} /* 20 (4/0) */
+
+/* MV2SR.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_46f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 22; 
+{if (!regs.s) { Exception (8); goto l_130674; }
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130674;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	do_cycles_ce000_internal (4);
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130674: ;
+return;
+} /* 22 (4/0) */
+
+/* MV2SR.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_46f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_130675; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130675;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	do_cycles_ce000_internal (4);
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130675: ;
+return;
+} /* 20 (4/0) */
+
+/* MV2SR.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_46f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_130676; }
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130676;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+	do_cycles_ce000_internal (4);
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (6);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130676: ;
+return;
+} /* 24 (5/0) */
+
+/* MV2SR.W (d16,PC) */
+void REGPARAM2 CPUFUNC(op_46fa_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_130677; }
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130677;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	do_cycles_ce000_internal (4);
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130677: ;
+return;
+} /* 20 (4/0) */
+
+/* MV2SR.W (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_46fb_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 22; 
+{if (!regs.s) { Exception (8); goto l_130678; }
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130678;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	do_cycles_ce000_internal (4);
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130678: ;
+return;
+} /* 22 (4/0) */
+
+/* MV2SR.W #.W */
+void REGPARAM2 CPUFUNC(op_46fc_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_130679; }
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_incpci (4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}l_130679: ;
+return;
+} /* 16 (3/0) */
+
+/* NBCD.B Dn */
+void REGPARAM2 CPUFUNC(op_4800_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* NBCD.B (An) */
+void REGPARAM2 CPUFUNC(op_4810_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	ipl_fetch ();
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* NBCD.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4818_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	ipl_fetch ();
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* NBCD.B -(An) */
+void REGPARAM2 CPUFUNC(op_4820_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	ipl_fetch ();
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* NBCD.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4828_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	ipl_fetch ();
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* NBCD.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4830_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	ipl_fetch ();
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* NBCD.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4838_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	ipl_fetch ();
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* NBCD.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4839_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	ipl_fetch ();
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* SWAP.W Dn */
+void REGPARAM2 CPUFUNC(op_4840_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 34;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* PEA.L (An) */
+void REGPARAM2 CPUFUNC(op_4850_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, dsta);
+		goto l_130689;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	x_put_word (dsta, srca >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, srca);
+}}}}	m68k_incpci (2);
+l_130689: ;
+return;
+} /* 12 (1/2) */
+
+/* PEA.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4868_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130690;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, 7) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	x_put_word (dsta, srca >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, srca);
+}}}}	m68k_incpci (4);
+l_130690: ;
+return;
+} /* 16 (2/2) */
+
+/* PEA.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4870_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 20; 
+{	do_cycles_ce000_internal (2);
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130691;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, 7) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+	x_put_word (dsta, srca >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, srca);
+}}}}	m68k_incpci (4);
+l_130691: ;
+return;
+} /* 20 (2/2) */
+
+/* PEA.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4878_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130692;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, 7) = dsta;
+	x_put_word (dsta, srca >> 16);
+	x_put_word (dsta + 2, srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+}}}}	m68k_incpci (4);
+l_130692: ;
+return;
+} /* 16 (2/2) */
+
+/* PEA.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4879_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	if (dsta & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, dsta);
+		goto l_130693;
+	}
+{	bus_error_offset = 8;
+	m68k_areg (regs, 7) = dsta;
+	x_put_word (dsta, srca >> 16);
+	x_put_word (dsta + 2, srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130693: ;
+return;
+} /* 20 (3/2) */
+
+/* PEA.L (d16,PC) */
+void REGPARAM2 CPUFUNC(op_487a_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130694;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, 7) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	x_put_word (dsta, srca >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, srca);
+}}}}	m68k_incpci (4);
+l_130694: ;
+return;
+} /* 16 (2/2) */
+
+/* PEA.L (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_487b_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 20; 
+{	do_cycles_ce000_internal (2);
+{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, dsta);
+		goto l_130695;
+	}
+{	bus_error_offset = 6;
+	m68k_areg (regs, 7) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+	x_put_word (dsta, srca >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, srca);
+}}}}	m68k_incpci (4);
+l_130695: ;
+return;
+} /* 20 (2/2) */
+
+/* EXT.W Dn */
+void REGPARAM2 CPUFUNC(op_4880_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 dst = (uae_s16)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* MVMLE.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_4890_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130697;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		x_put_word (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		x_put_word (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+}}}}	m68k_incpci (4);
+l_130697: ;
+return;
+} /* 8+ (2/0) */
+
+/* MVMLE.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_48a0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130698;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	while (amask) {
+		srca -= 2;
+		x_put_word (srca, m68k_areg (regs, movem_index2[amask]));
+	amask = movem_next[amask];
+	}
+	while (dmask) {
+		srca -= 2;
+		x_put_word (srca, m68k_dreg (regs, movem_index2[dmask]));
+		dmask = movem_next[dmask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+}}}}	m68k_incpci (4);
+l_130698: ;
+return;
+} /* 8+ (2/0) */
+
+/* MVMLE.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_48a8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130699;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		x_put_word (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		x_put_word (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130699: ;
+return;
+} /* 12+ (3/0) */
+
+/* MVMLE.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_48b0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 14; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130700;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		x_put_word (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		x_put_word (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130700: ;
+return;
+} /* 14+ (3/0) */
+
+/* MVMLE.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_48b8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130701;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		x_put_word (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		x_put_word (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130701: ;
+return;
+} /* 12+ (3/0) */
+
+/* MVMLE.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_48b9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+{	uaecptr srca;
+	srca = get_word_ce000_prefetch (6) << 16;
+	srca |= get_word_ce000_prefetch (8);
+	if (srca & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, srca);
+		goto l_130702;
+	}
+{	bus_error_offset = 8;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		x_put_word (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		x_put_word (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+}}}}	m68k_incpci (8);
+l_130702: ;
+return;
+} /* 16+ (4/0) */
+
+/* EXT.L Dn */
+void REGPARAM2 CPUFUNC(op_48c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 dst = (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* MVMLE.L #.W,(An) */
+void REGPARAM2 CPUFUNC(op_48d0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130704;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		x_put_word (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16);
+		x_put_word (srca + 2, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		x_put_word (srca, m68k_areg (regs, movem_index1[amask]) >> 16);
+		x_put_word (srca + 2, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+}}}}	m68k_incpci (4);
+l_130704: ;
+return;
+} /* 8+ (2/0) */
+
+/* MVMLE.L #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_48e0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130705;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	while (amask) {
+		srca -= 4;
+		x_put_word (srca, m68k_areg (regs, movem_index2[amask]) >> 16);
+		x_put_word (srca + 2, m68k_areg (regs, movem_index2[amask]));
+		amask = movem_next[amask];
+	}
+	while (dmask) {
+		srca -= 4;
+		x_put_word (srca, m68k_dreg (regs, movem_index2[dmask]) >> 16);
+		x_put_word (srca + 2, m68k_dreg (regs, movem_index2[dmask]));
+		dmask = movem_next[dmask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+}}}}	m68k_incpci (4);
+l_130705: ;
+return;
+} /* 8+ (2/0) */
+
+/* MVMLE.L #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_48e8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130706;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		x_put_word (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16);
+		x_put_word (srca + 2, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		x_put_word (srca, m68k_areg (regs, movem_index1[amask]) >> 16);
+		x_put_word (srca + 2, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130706: ;
+return;
+} /* 12+ (3/0) */
+
+/* MVMLE.L #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_48f0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 14; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130707;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		x_put_word (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16);
+		x_put_word (srca + 2, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		x_put_word (srca, m68k_areg (regs, movem_index1[amask]) >> 16);
+		x_put_word (srca + 2, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130707: ;
+return;
+} /* 14+ (3/0) */
+
+/* MVMLE.L #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_48f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130708;
+	}
+{	bus_error_offset = 6;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		x_put_word (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16);
+		x_put_word (srca + 2, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		x_put_word (srca, m68k_areg (regs, movem_index1[amask]) >> 16);
+		x_put_word (srca + 2, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130708: ;
+return;
+} /* 12+ (3/0) */
+
+/* MVMLE.L #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_48f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+{	uaecptr srca;
+	srca = get_word_ce000_prefetch (6) << 16;
+	srca |= get_word_ce000_prefetch (8);
+	if (srca & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, srca);
+		goto l_130709;
+	}
+{	bus_error_offset = 8;
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		x_put_word (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16);
+		x_put_word (srca + 2, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		x_put_word (srca, m68k_areg (regs, movem_index1[amask]) >> 16);
+		x_put_word (srca + 2, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+}}}}	m68k_incpci (8);
+l_130709: ;
+return;
+} /* 16+ (4/0) */
+
+/* TST.B Dn */
+void REGPARAM2 CPUFUNC(op_4a00_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* TST.B (An) */
+void REGPARAM2 CPUFUNC(op_4a10_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+} /* 8 (2/0) */
+
+/* TST.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4a18_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+} /* 8 (2/0) */
+
+/* TST.B -(An) */
+void REGPARAM2 CPUFUNC(op_4a20_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+} /* 10 (2/0) */
+
+/* TST.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4a28_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* TST.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4a30_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* TST.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4a38_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* TST.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4a39_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (6);
+return;
+} /* 16 (4/0) */
+
+/* TST.W Dn */
+void REGPARAM2 CPUFUNC(op_4a40_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* TST.W (An) */
+void REGPARAM2 CPUFUNC(op_4a50_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130719;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}	m68k_incpci (2);
+l_130719: ;
+return;
+} /* 8 (2/0) */
+
+/* TST.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4a58_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130720;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}	m68k_incpci (2);
+l_130720: ;
+return;
+} /* 8 (2/0) */
+
+/* TST.W -(An) */
+void REGPARAM2 CPUFUNC(op_4a60_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130721;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}	m68k_incpci (2);
+l_130721: ;
+return;
+} /* 10 (2/0) */
+
+/* TST.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4a68_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130722;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}	m68k_incpci (4);
+l_130722: ;
+return;
+} /* 12 (3/0) */
+
+/* TST.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4a70_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130723;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}	m68k_incpci (4);
+l_130723: ;
+return;
+} /* 14 (3/0) */
+
+/* TST.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4a78_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130724;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}	m68k_incpci (4);
+l_130724: ;
+return;
+} /* 12 (3/0) */
+
+/* TST.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4a79_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130725;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}	m68k_incpci (6);
+l_130725: ;
+return;
+} /* 16 (4/0) */
+
+/* TST.L Dn */
+void REGPARAM2 CPUFUNC(op_4a80_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* TST.L (An) */
+void REGPARAM2 CPUFUNC(op_4a90_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130727;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}	m68k_incpci (2);
+l_130727: ;
+return;
+} /* 12 (3/0) */
+
+/* TST.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4a98_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130728;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}	m68k_incpci (2);
+l_130728: ;
+return;
+} /* 12 (3/0) */
+
+/* TST.L -(An) */
+void REGPARAM2 CPUFUNC(op_4aa0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130729;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}	m68k_incpci (2);
+l_130729: ;
+return;
+} /* 14 (3/0) */
+
+/* TST.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4aa8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130730;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}	m68k_incpci (4);
+l_130730: ;
+return;
+} /* 16 (4/0) */
+
+/* TST.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4ab0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_130731;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}	m68k_incpci (4);
+l_130731: ;
+return;
+} /* 18 (4/0) */
+
+/* TST.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4ab8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_130732;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}	m68k_incpci (4);
+l_130732: ;
+return;
+} /* 16 (4/0) */
+
+/* TST.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4ab9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_130733;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}	m68k_incpci (6);
+l_130733: ;
+return;
+} /* 20 (5/0) */
+
+/* TAS.B Dn */
+void REGPARAM2 CPUFUNC(op_4ac0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src |= 0x80;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((src) & 0xff);
+}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* TAS.B (An) */
+void REGPARAM2 CPUFUNC(op_4ad0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src |= 0x80;
+	if (!is_cycle_ce ()) {
+	ipl_fetch ();
+	x_put_byte (srca, src);
+	} else {
+		do_cycles_ce000_internal (4);
+	}
+}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* TAS.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4ad8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src |= 0x80;
+	if (!is_cycle_ce ()) {
+	ipl_fetch ();
+	x_put_byte (srca, src);
+	} else {
+		do_cycles_ce000_internal (4);
+	}
+}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* TAS.B -(An) */
+void REGPARAM2 CPUFUNC(op_4ae0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	src |= 0x80;
+	if (!is_cycle_ce ()) {
+	ipl_fetch ();
+	x_put_byte (srca, src);
+	} else {
+		do_cycles_ce000_internal (4);
+	}
+}}}	m68k_incpci (2);
+return;
+} /* 16 (2/1) */
+
+/* TAS.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4ae8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src |= 0x80;
+	if (!is_cycle_ce ()) {
+	ipl_fetch ();
+	x_put_byte (srca, src);
+	} else {
+		do_cycles_ce000_internal (4);
+	}
+}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* TAS.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4af0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src |= 0x80;
+	if (!is_cycle_ce ()) {
+	ipl_fetch ();
+	x_put_byte (srca, src);
+	} else {
+		do_cycles_ce000_internal (4);
+	}
+}}}	m68k_incpci (4);
+return;
+} /* 20 (3/1) */
+
+/* TAS.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4af8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	src |= 0x80;
+	if (!is_cycle_ce ()) {
+	ipl_fetch ();
+	x_put_byte (srca, src);
+	} else {
+		do_cycles_ce000_internal (4);
+	}
+}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* TAS.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4af9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	src |= 0x80;
+	if (!is_cycle_ce ()) {
+	ipl_fetch ();
+	x_put_byte (srca, src);
+	} else {
+		do_cycles_ce000_internal (4);
+	}
+}}}	m68k_incpci (6);
+return;
+} /* 22 (4/1) */
+
+/* MVMEL.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_4c90_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130742;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+}}}}	m68k_incpci (4);
+l_130742: ;
+return;
+} /* 12+ (3/0) */
+
+/* MVMEL.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_4c98_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130743;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	m68k_areg (regs, dstreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+}}}}	m68k_incpci (4);
+l_130743: ;
+return;
+} /* 12+ (3/0) */
+
+/* MVMEL.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_4ca8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130744;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130744: ;
+return;
+} /* 16+ (4/0) */
+
+/* MVMEL.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4cb0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 18; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+	do_cycles_ce000_internal (2);
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130745;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130745: ;
+return;
+} /* 18+ (4/0) */
+
+/* MVMEL.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_4cb8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130746;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130746: ;
+return;
+} /* 16+ (4/0) */
+
+/* MVMEL.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_4cb9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 20; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = get_word_ce000_prefetch (6) << 16;
+	srca |= get_word_ce000_prefetch (8);
+	if (srca & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, srca);
+		goto l_130747;
+	}
+{	bus_error_offset = 8;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+}}}}	m68k_incpci (8);
+l_130747: ;
+return;
+} /* 20+ (5/0) */
+
+/* MVMEL.W #.W,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_4cba_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130748;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130748: ;
+return;
+} /* 16+ (4/0) */
+
+/* MVMEL.W #.W,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4cbb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 18; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+	do_cycles_ce000_internal (2);
+{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 4;
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (6));
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130749;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130749: ;
+return;
+} /* 18+ (4/0) */
+
+/* MVMEL.L #.W,(An) */
+void REGPARAM2 CPUFUNC(op_4cd0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130750;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+}}}}	m68k_incpci (4);
+l_130750: ;
+return;
+} /* 12+ (3/0) */
+
+/* MVMEL.L #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_4cd8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130751;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	m68k_areg (regs, dstreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+}}}}	m68k_incpci (4);
+l_130751: ;
+return;
+} /* 12+ (3/0) */
+
+/* MVMEL.L #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_4ce8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130752;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130752: ;
+return;
+} /* 16+ (4/0) */
+
+/* MVMEL.L #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4cf0_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 18; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+	do_cycles_ce000_internal (2);
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (6));
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130753;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130753: ;
+return;
+} /* 18+ (4/0) */
+
+/* MVMEL.L #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_4cf8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130754;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130754: ;
+return;
+} /* 16+ (4/0) */
+
+/* MVMEL.L #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_4cf9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 20; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = get_word_ce000_prefetch (6) << 16;
+	srca |= get_word_ce000_prefetch (8);
+	if (srca & 1) {
+	m68k_incpci (8);
+		exception3_write(opcode, srca);
+		goto l_130755;
+	}
+{	bus_error_offset = 8;
+{	while (dmask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (10);
+}}}}	m68k_incpci (8);
+l_130755: ;
+return;
+} /* 20+ (5/0) */
+
+/* MVMEL.L #.W,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_4cfa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 16; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130756;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130756: ;
+return;
+} /* 16+ (4/0) */
+
+/* MVMEL.L #.W,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4cfb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 18; 
+{	uae_u16 mask = get_word_ce000_prefetch (4);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	uae_u32 v;
+	do_cycles_ce000_internal (2);
+{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 4;
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (6));
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_130757;
+	}
+{	bus_error_offset = 6;
+{	while (dmask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_dreg (regs, movem_index1[dmask]) = v;
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		v = x_get_word (srca) << 16;
+		v |= x_get_word (srca + 2);
+		m68k_areg (regs, movem_index1[amask]) = v;
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+}}}}	m68k_incpci (6);
+l_130757: ;
+return;
+} /* 18+ (4/0) */
+
+/* TRAPQ.L # */
+void REGPARAM2 CPUFUNC(op_4e40_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 15);
+	OpcodeFamily = 39;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+	m68k_incpci (2);
+	Exception (src + 32);
+}}return;
+} /* 4 (0/0) */
+
+/* LINK.W An,#.W */
+void REGPARAM2 CPUFUNC(op_4e50_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 16; 
+{{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	if (olda & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, olda);
+		goto l_130759;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s16 offs = get_word_ce000_prefetch (4);
+	x_put_word (olda, src >> 16);
+	x_put_word (olda + 2, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+}}}}}	m68k_incpci (4);
+l_130759: ;
+return;
+} /* 16 (2/2) */
+
+/* UNLK.L An */
+void REGPARAM2 CPUFUNC(op_4e58_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 48;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	m68k_areg (regs, 7) = src;
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7);
+	if (olda & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, olda);
+		goto l_130760;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 old = x_get_word (olda) << 16; old |= x_get_word (olda + 2);
+	m68k_areg (regs, 7) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_areg (regs, srcreg) = (old);
+}}}}}	m68k_incpci (2);
+l_130760: ;
+return;
+} /* 12 (3/0) */
+
+/* MVR2USP.L An */
+void REGPARAM2 CPUFUNC(op_4e60_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 40;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_130761; }
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	regs.usp = src;
+}}}	m68k_incpci (2);
+l_130761: ;
+return;
+} /* 4 (1/0) */
+
+/* MVUSP2R.L An */
+void REGPARAM2 CPUFUNC(op_4e68_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 41;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_130762; }
+{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_areg (regs, srcreg) = (regs.usp);
+}}}	m68k_incpci (2);
+l_130762: ;
+return;
+} /* 4 (1/0) */
+
+/* RESET.L  */
+void REGPARAM2 CPUFUNC(op_4e70_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 42;
+	CurrentInstrCycles = 132;
+{if (!regs.s) { Exception (8); goto l_130763; }
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	cpureset ();
+	m68k_incpci (2);
+	do_cycles_ce000_internal (128);
+	get_word_ce000_prefetch (2);
+}}l_130763: ;
+return;
+} /* 132 (1/0) */
+
+/* NOP.L  */
+void REGPARAM2 CPUFUNC(op_4e71_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 43;
+	CurrentInstrCycles = 4;  
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* STOP.L #.W */
+void REGPARAM2 CPUFUNC(op_4e72_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 44;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_130765; }
+{	regs.sr = regs.irc;
+	do_cycles_ce000_internal (4);
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_setstopped ();
+	m68k_incpci (4);
+}}l_130765: ;
+return;
+} /* 4 (0/0) */
+
+/* RTE.L  */
+void REGPARAM2 CPUFUNC(op_4e73_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 45;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_130766; }
+{	uae_u16 newsr; uae_u32 newpc;
+	for (;;) {
+		uaecptr a = m68k_areg (regs, 7);
+		uae_u16 sr = x_get_word (a);
+		uae_u32 pc = x_get_word (a + 2) << 16; pc |= x_get_word (a + 4);
+		uae_u16 format = x_get_word (a + 2 + 4);
+		int frame = format >> 12;
+		int offset = 8;
+		newsr = sr; newpc = pc;
+		if (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }
+		else if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }
+		else { m68k_areg (regs, 7) += offset; Exception (14); goto l_130766; }
+		regs.sr = newsr; MakeFromSR ();
+}
+	regs.sr = newsr;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	if (newpc & 1) {
+		exception3i (0x4E73, newpc);
+		goto l_130766;
+	}
+	m68k_setpci (newpc);
+	ipl_fetch ();
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_130766: ;
+return;
+} /* 24 (6/0) */
+
+/* RTD.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4e74_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 46;
+	CurrentInstrCycles = 20; 
+{{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+	if (pca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, pca);
+		goto l_130767;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 pc = x_get_word (pca) << 16; pc |= x_get_word (pca + 2);
+	m68k_areg (regs, 7) += 4;
+{	uae_s16 offs = get_word_ce000_prefetch (4);
+	m68k_areg (regs, 7) += offs;
+	if (pc & 1) {
+		exception3i (0x4E74, pc);
+		goto l_130767;
+	}
+	m68k_setpci (pc);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}l_130767: ;
+return;
+} /* 20 (5/0) */
+
+#endif
+/* RTS.L  */
+void REGPARAM2 CPUFUNC(op_4e75_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 49;
+	CurrentInstrCycles = 16; 
+{	uaecptr pc = m68k_getpci ();
+	m68k_do_rts_ce ();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (pc);
+		exception3i (0x4E75, faultpc);
+		goto l_130768;
+	}
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_130768: ;
+return;
+} /* 16 (4/0) */
+
+/* TRAPV.L  */
+void REGPARAM2 CPUFUNC(op_4e76_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 50;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	if (GET_VFLG ()) {
+		Exception (7);
+		goto l_130769;
+	}
+}l_130769: ;
+return;
+} /* 4 (1/0) */
+
+/* RTR.L  */
+void REGPARAM2 CPUFUNC(op_4e77_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 51;
+	CurrentInstrCycles = 20; 
+{	uaecptr oldpc = m68k_getpci ();
+	MakeSR ();
+{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+	if (sra & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, sra);
+		goto l_130770;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 sr = x_get_word (sra);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+	if (pca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, pca);
+		goto l_130770;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 pc = x_get_word (pca) << 16; pc |= x_get_word (pca + 2);
+	m68k_areg (regs, 7) += 4;
+	regs.sr &= 0xFF00; sr &= 0xFF;
+	regs.sr |= sr;
+	m68k_setpci (pc);
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (oldpc);
+		exception3i (0x4E77, faultpc);
+		goto l_130770;
+	}
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}}l_130770: ;
+return;
+} /* 20 (5/0) */
+
+/* MOVEC2.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4e7a_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 82;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_130771; }
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_movec2(src & 0xFFF, regp)) goto l_130771;
+}}}}	m68k_incpci (4);
+l_130771: ;
+return;
+} /* 8 (2/0) */
+
+#endif
+/* MOVE2C.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4e7b_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 83;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_130772; }
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_move2c(src & 0xFFF, regp)) goto l_130772;
+}}}}	m68k_incpci (4);
+l_130772: ;
+return;
+} /* 8 (2/0) */
+
+#endif
+/* JSR.L (An) */
+void REGPARAM2 CPUFUNC(op_4e90_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr oldpc = m68k_getpci () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_130773;
+	}
+	m68k_setpci (srca);
+	get_word_ce000_prefetch (0);
+	m68k_areg (regs, 7) -= 4;
+	x_put_word (m68k_areg (regs, 7), oldpc >> 16);
+	x_put_word (m68k_areg (regs, 7) + 2, oldpc);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}l_130773: ;
+return;
+} /* 16 (2/2) */
+
+/* JSR.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4ea8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)regs.irc;
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_130774;
+	}
+	do_cycles_ce000_internal (2);
+	m68k_setpci (srca);
+	get_word_ce000_prefetch (0);
+	m68k_areg (regs, 7) -= 4;
+	x_put_word (m68k_areg (regs, 7), oldpc >> 16);
+	x_put_word (m68k_areg (regs, 7) + 2, oldpc);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}l_130774: ;
+return;
+} /* 18 (2/2) */
+
+/* JSR.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4eb0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), regs.irc);
+{	uaecptr oldpc = m68k_getpci () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_130775;
+	}
+	do_cycles_ce000_internal (6);
+	oldpc += 2;
+	m68k_setpci (srca);
+	get_word_ce000_prefetch (0);
+	m68k_areg (regs, 7) -= 4;
+	x_put_word (m68k_areg (regs, 7), oldpc >> 16);
+	x_put_word (m68k_areg (regs, 7) + 2, oldpc);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}l_130775: ;
+return;
+} /* 22 (2/2) */
+
+/* JSR.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4eb8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)regs.irc;
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_130776;
+	}
+	do_cycles_ce000_internal (2);
+	m68k_setpci (srca);
+	get_word_ce000_prefetch (0);
+	m68k_areg (regs, 7) -= 4;
+	x_put_word (m68k_areg (regs, 7), oldpc >> 16);
+	x_put_word (m68k_areg (regs, 7) + 2, oldpc);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}l_130776: ;
+return;
+} /* 18 (2/2) */
+
+/* JSR.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4eb9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= regs.irc;
+{	uaecptr oldpc = m68k_getpci () + 6;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_130777;
+	}
+	m68k_setpci (srca);
+	get_word_ce000_prefetch (0);
+	m68k_areg (regs, 7) -= 4;
+	x_put_word (m68k_areg (regs, 7), oldpc >> 16);
+	x_put_word (m68k_areg (regs, 7) + 2, oldpc);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}l_130777: ;
+return;
+} /* 20 (3/2) */
+
+/* JSR.L (d16,PC) */
+void REGPARAM2 CPUFUNC(op_4eba_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)regs.irc;
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_130778;
+	}
+	do_cycles_ce000_internal (2);
+	m68k_setpci (srca);
+	get_word_ce000_prefetch (0);
+	m68k_areg (regs, 7) -= 4;
+	x_put_word (m68k_areg (regs, 7), oldpc >> 16);
+	x_put_word (m68k_areg (regs, 7) + 2, oldpc);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}l_130778: ;
+return;
+} /* 18 (2/2) */
+
+/* JSR.L (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4ebb_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 22; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	srca = get_disp_ea_000 (tmppc, regs.irc);
+{	uaecptr oldpc = m68k_getpci () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_130779;
+	}
+	do_cycles_ce000_internal (6);
+	oldpc += 2;
+	m68k_setpci (srca);
+	get_word_ce000_prefetch (0);
+	m68k_areg (regs, 7) -= 4;
+	x_put_word (m68k_areg (regs, 7), oldpc >> 16);
+	x_put_word (m68k_areg (regs, 7) + 2, oldpc);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}l_130779: ;
+return;
+} /* 22 (2/2) */
+
+/* JMP.L (An) */
+void REGPARAM2 CPUFUNC(op_4ed0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_130780;
+	}
+	m68k_setpci (srca);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}l_130780: ;
+return;
+} /* 8 (2/0) */
+
+/* JMP.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4ee8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)regs.irc;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_130781;
+	}
+	do_cycles_ce000_internal (2);
+	m68k_setpci (srca);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}l_130781: ;
+return;
+} /* 10 (2/0) */
+
+/* JMP.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4ef0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), regs.irc);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_130782;
+	}
+	do_cycles_ce000_internal (6);
+	m68k_setpci (srca);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}l_130782: ;
+return;
+} /* 14 (2/0) */
+
+/* JMP.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4ef8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)regs.irc;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_130783;
+	}
+	do_cycles_ce000_internal (2);
+	m68k_setpci (srca);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}l_130783: ;
+return;
+} /* 10 (2/0) */
+
+/* JMP.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4ef9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= regs.irc;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_130784;
+	}
+	m68k_setpci (srca);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}l_130784: ;
+return;
+} /* 12 (3/0) */
+
+/* JMP.L (d16,PC) */
+void REGPARAM2 CPUFUNC(op_4efa_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)regs.irc;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_130785;
+	}
+	do_cycles_ce000_internal (2);
+	m68k_setpci (srca);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}l_130785: ;
+return;
+} /* 10 (2/0) */
+
+/* JMP.L (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4efb_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	srca = get_disp_ea_000 (tmppc, regs.irc);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_130786;
+	}
+	do_cycles_ce000_internal (6);
+	m68k_setpci (srca);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}l_130786: ;
+return;
+} /* 14 (2/0) */
+
+/* ADDQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_5000_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* ADDQ.B #,(An) */
+void REGPARAM2 CPUFUNC(op_5010_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* ADDQ.B #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5018_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* ADDQ.B #,-(An) */
+void REGPARAM2 CPUFUNC(op_5020_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* ADDQ.B #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5028_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* ADDQ.B #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5030_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* ADDQ.B #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5038_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* ADDQ.B #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5039_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* ADDQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_5040_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* ADDAQ.W #,An */
+void REGPARAM2 CPUFUNC(op_5048_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* ADDQ.W #,(An) */
+void REGPARAM2 CPUFUNC(op_5050_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130797;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_130797: ;
+return;
+} /* 12 (2/1) */
+
+/* ADDQ.W #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5058_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130798;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_130798: ;
+return;
+} /* 12 (2/1) */
+
+/* ADDQ.W #,-(An) */
+void REGPARAM2 CPUFUNC(op_5060_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130799;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_130799: ;
+return;
+} /* 14 (2/1) */
+
+/* ADDQ.W #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5068_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130800;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_130800: ;
+return;
+} /* 16 (3/1) */
+
+/* ADDQ.W #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5070_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130801;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_130801: ;
+return;
+} /* 18 (3/1) */
+
+/* ADDQ.W #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5078_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130802;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_130802: ;
+return;
+} /* 16 (3/1) */
+
+/* ADDQ.W #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5079_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130803;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_130803: ;
+return;
+} /* 20 (4/1) */
+
+/* ADDQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_5080_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* ADDAQ.L #,An */
+void REGPARAM2 CPUFUNC(op_5088_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* ADDQ.L #,(An) */
+void REGPARAM2 CPUFUNC(op_5090_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130806;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_130806: ;
+return;
+} /* 20 (3/2) */
+
+/* ADDQ.L #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5098_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130807;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_130807: ;
+return;
+} /* 20 (3/2) */
+
+/* ADDQ.L #,-(An) */
+void REGPARAM2 CPUFUNC(op_50a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130808;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_130808: ;
+return;
+} /* 22 (3/2) */
+
+#endif
+
+#ifdef PART_5
+/* ADDQ.L #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_50a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130809;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_130809: ;
+return;
+} /* 24 (4/2) */
+
+/* ADDQ.L #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_50b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 26; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130810;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_130810: ;
+return;
+} /* 26 (4/2) */
+
+/* ADDQ.L #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_50b8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130811;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_130811: ;
+return;
+} /* 24 (4/2) */
+
+/* ADDQ.L #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_50b9_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130812;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_130812: ;
+return;
+} /* 28 (5/2) */
+
+/* Scc.B Dn (T) */
+void REGPARAM2 CPUFUNC(op_50c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (T) */
+void REGPARAM2 CPUFUNC(op_50c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (0)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130814;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130814: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (T) */
+void REGPARAM2 CPUFUNC(op_50d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (T) */
+void REGPARAM2 CPUFUNC(op_50d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (T) */
+void REGPARAM2 CPUFUNC(op_50e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (T) */
+void REGPARAM2 CPUFUNC(op_50e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (0) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (T) */
+void REGPARAM2 CPUFUNC(op_50f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (0) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (T) */
+void REGPARAM2 CPUFUNC(op_50f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (0) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (T) */
+void REGPARAM2 CPUFUNC(op_50f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (0) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* SUBQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_5100_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* SUBQ.B #,(An) */
+void REGPARAM2 CPUFUNC(op_5110_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* SUBQ.B #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5118_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* SUBQ.B #,-(An) */
+void REGPARAM2 CPUFUNC(op_5120_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* SUBQ.B #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5128_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* SUBQ.B #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5130_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* SUBQ.B #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5138_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* SUBQ.B #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5139_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* SUBQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_5140_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* SUBAQ.W #,An */
+void REGPARAM2 CPUFUNC(op_5148_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* SUBQ.W #,(An) */
+void REGPARAM2 CPUFUNC(op_5150_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130832;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_130832: ;
+return;
+} /* 12 (2/1) */
+
+/* SUBQ.W #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5158_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130833;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_130833: ;
+return;
+} /* 12 (2/1) */
+
+/* SUBQ.W #,-(An) */
+void REGPARAM2 CPUFUNC(op_5160_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130834;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_130834: ;
+return;
+} /* 14 (2/1) */
+
+/* SUBQ.W #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5168_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130835;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_130835: ;
+return;
+} /* 16 (3/1) */
+
+/* SUBQ.W #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5170_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130836;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_130836: ;
+return;
+} /* 18 (3/1) */
+
+/* SUBQ.W #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5178_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130837;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_130837: ;
+return;
+} /* 16 (3/1) */
+
+/* SUBQ.W #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5179_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130838;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_130838: ;
+return;
+} /* 20 (4/1) */
+
+/* SUBQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_5180_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* SUBAQ.L #,An */
+void REGPARAM2 CPUFUNC(op_5188_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* SUBQ.L #,(An) */
+void REGPARAM2 CPUFUNC(op_5190_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130841;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_130841: ;
+return;
+} /* 20 (3/2) */
+
+/* SUBQ.L #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5198_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130842;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_130842: ;
+return;
+} /* 20 (3/2) */
+
+/* SUBQ.L #,-(An) */
+void REGPARAM2 CPUFUNC(op_51a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130843;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_130843: ;
+return;
+} /* 22 (3/2) */
+
+/* SUBQ.L #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_51a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130844;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_130844: ;
+return;
+} /* 24 (4/2) */
+
+/* SUBQ.L #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_51b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 26; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_130845;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_130845: ;
+return;
+} /* 26 (4/2) */
+
+/* SUBQ.L #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_51b8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_130846;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_130846: ;
+return;
+} /* 24 (4/2) */
+
+/* SUBQ.L #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_51b9_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_130847;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_130847: ;
+return;
+} /* 28 (5/2) */
+
+/* Scc.B Dn (F) */
+void REGPARAM2 CPUFUNC(op_51c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (F) */
+void REGPARAM2 CPUFUNC(op_51c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (1)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130849;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130849: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (F) */
+void REGPARAM2 CPUFUNC(op_51d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (F) */
+void REGPARAM2 CPUFUNC(op_51d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (F) */
+void REGPARAM2 CPUFUNC(op_51e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (F) */
+void REGPARAM2 CPUFUNC(op_51e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (1) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (F) */
+void REGPARAM2 CPUFUNC(op_51f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (1) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (F) */
+void REGPARAM2 CPUFUNC(op_51f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (1) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (F) */
+void REGPARAM2 CPUFUNC(op_51f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (1) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (HI) */
+void REGPARAM2 CPUFUNC(op_52c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (HI) */
+void REGPARAM2 CPUFUNC(op_52c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (2)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130858;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130858: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (HI) */
+void REGPARAM2 CPUFUNC(op_52d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (HI) */
+void REGPARAM2 CPUFUNC(op_52d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (HI) */
+void REGPARAM2 CPUFUNC(op_52e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (HI) */
+void REGPARAM2 CPUFUNC(op_52e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (2) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (HI) */
+void REGPARAM2 CPUFUNC(op_52f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (2) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (HI) */
+void REGPARAM2 CPUFUNC(op_52f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (2) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (HI) */
+void REGPARAM2 CPUFUNC(op_52f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (2) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (LS) */
+void REGPARAM2 CPUFUNC(op_53c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (LS) */
+void REGPARAM2 CPUFUNC(op_53c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (3)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130867;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130867: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (LS) */
+void REGPARAM2 CPUFUNC(op_53d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (LS) */
+void REGPARAM2 CPUFUNC(op_53d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (LS) */
+void REGPARAM2 CPUFUNC(op_53e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (LS) */
+void REGPARAM2 CPUFUNC(op_53e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (3) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (LS) */
+void REGPARAM2 CPUFUNC(op_53f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (3) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (LS) */
+void REGPARAM2 CPUFUNC(op_53f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (3) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (LS) */
+void REGPARAM2 CPUFUNC(op_53f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (3) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (CC) */
+void REGPARAM2 CPUFUNC(op_54c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (CC) */
+void REGPARAM2 CPUFUNC(op_54c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (4)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130876;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130876: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (CC) */
+void REGPARAM2 CPUFUNC(op_54d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (CC) */
+void REGPARAM2 CPUFUNC(op_54d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (CC) */
+void REGPARAM2 CPUFUNC(op_54e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (CC) */
+void REGPARAM2 CPUFUNC(op_54e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (4) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (CC) */
+void REGPARAM2 CPUFUNC(op_54f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (4) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (CC) */
+void REGPARAM2 CPUFUNC(op_54f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (4) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (CC) */
+void REGPARAM2 CPUFUNC(op_54f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (4) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (CS) */
+void REGPARAM2 CPUFUNC(op_55c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (CS) */
+void REGPARAM2 CPUFUNC(op_55c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (5)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130885;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130885: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (CS) */
+void REGPARAM2 CPUFUNC(op_55d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (CS) */
+void REGPARAM2 CPUFUNC(op_55d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (CS) */
+void REGPARAM2 CPUFUNC(op_55e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (CS) */
+void REGPARAM2 CPUFUNC(op_55e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (5) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (CS) */
+void REGPARAM2 CPUFUNC(op_55f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (5) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (CS) */
+void REGPARAM2 CPUFUNC(op_55f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (5) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (CS) */
+void REGPARAM2 CPUFUNC(op_55f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (5) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (NE) */
+void REGPARAM2 CPUFUNC(op_56c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (NE) */
+void REGPARAM2 CPUFUNC(op_56c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (6)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130894;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130894: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (NE) */
+void REGPARAM2 CPUFUNC(op_56d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (NE) */
+void REGPARAM2 CPUFUNC(op_56d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (NE) */
+void REGPARAM2 CPUFUNC(op_56e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (NE) */
+void REGPARAM2 CPUFUNC(op_56e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (6) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (NE) */
+void REGPARAM2 CPUFUNC(op_56f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (6) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (NE) */
+void REGPARAM2 CPUFUNC(op_56f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (6) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (NE) */
+void REGPARAM2 CPUFUNC(op_56f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (6) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (EQ) */
+void REGPARAM2 CPUFUNC(op_57c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (EQ) */
+void REGPARAM2 CPUFUNC(op_57c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (7)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130903;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130903: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (EQ) */
+void REGPARAM2 CPUFUNC(op_57d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (7) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (EQ) */
+void REGPARAM2 CPUFUNC(op_57f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (7) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (EQ) */
+void REGPARAM2 CPUFUNC(op_57f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (7) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (EQ) */
+void REGPARAM2 CPUFUNC(op_57f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (7) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (VC) */
+void REGPARAM2 CPUFUNC(op_58c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (VC) */
+void REGPARAM2 CPUFUNC(op_58c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (8)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130912;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130912: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (VC) */
+void REGPARAM2 CPUFUNC(op_58d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (VC) */
+void REGPARAM2 CPUFUNC(op_58d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (VC) */
+void REGPARAM2 CPUFUNC(op_58e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (VC) */
+void REGPARAM2 CPUFUNC(op_58e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (8) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (VC) */
+void REGPARAM2 CPUFUNC(op_58f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (8) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (VC) */
+void REGPARAM2 CPUFUNC(op_58f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (8) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (VC) */
+void REGPARAM2 CPUFUNC(op_58f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (8) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (VS) */
+void REGPARAM2 CPUFUNC(op_59c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (VS) */
+void REGPARAM2 CPUFUNC(op_59c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (9)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130921;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130921: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (VS) */
+void REGPARAM2 CPUFUNC(op_59d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (VS) */
+void REGPARAM2 CPUFUNC(op_59d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (VS) */
+void REGPARAM2 CPUFUNC(op_59e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (VS) */
+void REGPARAM2 CPUFUNC(op_59e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (9) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (VS) */
+void REGPARAM2 CPUFUNC(op_59f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (9) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (VS) */
+void REGPARAM2 CPUFUNC(op_59f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (9) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (VS) */
+void REGPARAM2 CPUFUNC(op_59f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (9) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (PL) */
+void REGPARAM2 CPUFUNC(op_5ac0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (PL) */
+void REGPARAM2 CPUFUNC(op_5ac8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (10)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130930;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130930: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ad0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (PL) */
+void REGPARAM2 CPUFUNC(op_5ad8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ae0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ae8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (10) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (PL) */
+void REGPARAM2 CPUFUNC(op_5af0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (10) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (PL) */
+void REGPARAM2 CPUFUNC(op_5af8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (10) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (PL) */
+void REGPARAM2 CPUFUNC(op_5af9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (10) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (MI) */
+void REGPARAM2 CPUFUNC(op_5bc0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (MI) */
+void REGPARAM2 CPUFUNC(op_5bc8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (11)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130939;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130939: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (MI) */
+void REGPARAM2 CPUFUNC(op_5bd0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (MI) */
+void REGPARAM2 CPUFUNC(op_5bd8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (MI) */
+void REGPARAM2 CPUFUNC(op_5be0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (MI) */
+void REGPARAM2 CPUFUNC(op_5be8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (11) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (MI) */
+void REGPARAM2 CPUFUNC(op_5bf0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (11) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (MI) */
+void REGPARAM2 CPUFUNC(op_5bf8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (11) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (MI) */
+void REGPARAM2 CPUFUNC(op_5bf9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (11) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (GE) */
+void REGPARAM2 CPUFUNC(op_5cc0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (GE) */
+void REGPARAM2 CPUFUNC(op_5cc8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (12)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130948;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130948: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (GE) */
+void REGPARAM2 CPUFUNC(op_5cd0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (GE) */
+void REGPARAM2 CPUFUNC(op_5cd8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (GE) */
+void REGPARAM2 CPUFUNC(op_5ce0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (GE) */
+void REGPARAM2 CPUFUNC(op_5ce8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (12) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (GE) */
+void REGPARAM2 CPUFUNC(op_5cf0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (12) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (GE) */
+void REGPARAM2 CPUFUNC(op_5cf8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (12) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (GE) */
+void REGPARAM2 CPUFUNC(op_5cf9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (12) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (LT) */
+void REGPARAM2 CPUFUNC(op_5dc0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (LT) */
+void REGPARAM2 CPUFUNC(op_5dc8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (13)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130957;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130957: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (LT) */
+void REGPARAM2 CPUFUNC(op_5dd0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (LT) */
+void REGPARAM2 CPUFUNC(op_5dd8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (LT) */
+void REGPARAM2 CPUFUNC(op_5de0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (LT) */
+void REGPARAM2 CPUFUNC(op_5de8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (13) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (LT) */
+void REGPARAM2 CPUFUNC(op_5df0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (13) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (LT) */
+void REGPARAM2 CPUFUNC(op_5df8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (13) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (LT) */
+void REGPARAM2 CPUFUNC(op_5df9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (13) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (GT) */
+void REGPARAM2 CPUFUNC(op_5ec0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (GT) */
+void REGPARAM2 CPUFUNC(op_5ec8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (14)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130966;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130966: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ed0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (GT) */
+void REGPARAM2 CPUFUNC(op_5ed8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ee0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ee8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (14) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (GT) */
+void REGPARAM2 CPUFUNC(op_5ef0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (14) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (GT) */
+void REGPARAM2 CPUFUNC(op_5ef8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (14) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (GT) */
+void REGPARAM2 CPUFUNC(op_5ef9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (14) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B Dn (LE) */
+void REGPARAM2 CPUFUNC(op_5fc0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* DBcc.W Dn,#.W (LE) */
+void REGPARAM2 CPUFUNC(op_5fc8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = regs.irc;
+	uaecptr oldpc = m68k_getpci ();
+	do_cycles_ce000_internal (2);
+	if (!cctrue (15)) {
+	m68k_incpci ((uae_s32)offs + 2);
+		get_word_ce000_prefetch (0);
+		m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_130975;
+			}
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+			return;
+		}
+	} else {
+	do_cycles_ce000_internal (2);
+	}
+	m68k_setpci (oldpc + 4);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}}l_130975: ;
+return;
+} /* 10 (2/0) */
+
+/* Scc.B (An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fd0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B (An)+ (LE) */
+void REGPARAM2 CPUFUNC(op_5fd8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/1) */
+
+/* Scc.B -(An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fe0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (1/1) */
+
+/* Scc.B (d16,An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fe8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (15) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (d8,An,Xn) (LE) */
+void REGPARAM2 CPUFUNC(op_5ff0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (15) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (xxx).W (LE) */
+void REGPARAM2 CPUFUNC(op_5ff8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (15) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (xxx).L (LE) */
+void REGPARAM2 CPUFUNC(op_5ff9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (15) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/1) */
+
+/* Bcc.W #.W (T) */
+void REGPARAM2 CPUFUNC(op_6000_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_130983;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_130983: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (T) */
+void REGPARAM2 CPUFUNC(op_6001_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_130984;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_130984: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (T) */
+void REGPARAM2 CPUFUNC(op_60ff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (0)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_130985;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_130985: ;
+return;
+} /* 8 (1/0) */
+
+/* BSR.W #.W */
+void REGPARAM2 CPUFUNC(op_6100_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 18; 
+{	uae_s32 s;
+{	uae_s16 src = regs.irc;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_130986;
+	}
+	do_cycles_ce000_internal (2);
+	m68k_do_bsr_ce (m68k_getpci () + 4, s);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}l_130986: ;
+return;
+} /* 18 (2/2) */
+
+/* BSRQ.B # */
+void REGPARAM2 CPUFUNC(op_6101_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 18; 
+{	uae_s32 s;
+{	uae_u32 src = srcreg;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_130987;
+	}
+	do_cycles_ce000_internal (2);
+	m68k_do_bsr_ce (m68k_getpci () + 2, s);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}l_130987: ;
+return;
+} /* 18 (2/2) */
+
+/* BSR.L #.L */
+void REGPARAM2 CPUFUNC(op_61ff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 18; 
+{	uae_s32 s;
+	uae_u32 src = 0xffffffff;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_130988;
+	}
+	do_cycles_ce000_internal (2);
+	m68k_do_bsr_ce (m68k_getpci () + 2, s);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_130988: ;
+return;
+} /* 18 (2/2) */
+
+/* Bcc.W #.W (HI) */
+void REGPARAM2 CPUFUNC(op_6200_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_130989;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_130989: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (HI) */
+void REGPARAM2 CPUFUNC(op_6201_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_130990;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_130990: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (HI) */
+void REGPARAM2 CPUFUNC(op_62ff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (2)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_130991;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_130991: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (LS) */
+void REGPARAM2 CPUFUNC(op_6300_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_130992;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_130992: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (LS) */
+void REGPARAM2 CPUFUNC(op_6301_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_130993;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_130993: ;
+return;
+} /* 8 (1/0) */
+
+#endif
+
+#ifdef PART_6
+/* Bcc.L #.L (LS) */
+void REGPARAM2 CPUFUNC(op_63ff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (3)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_130994;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_130994: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (CC) */
+void REGPARAM2 CPUFUNC(op_6400_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_130995;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_130995: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (CC) */
+void REGPARAM2 CPUFUNC(op_6401_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_130996;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_130996: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (CC) */
+void REGPARAM2 CPUFUNC(op_64ff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (4)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_130997;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_130997: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (CS) */
+void REGPARAM2 CPUFUNC(op_6500_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_130998;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_130998: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (CS) */
+void REGPARAM2 CPUFUNC(op_6501_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_130999;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_130999: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (CS) */
+void REGPARAM2 CPUFUNC(op_65ff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (5)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_131000;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_131000: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (NE) */
+void REGPARAM2 CPUFUNC(op_6600_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131001;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131001: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (NE) */
+void REGPARAM2 CPUFUNC(op_6601_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131002;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131002: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (NE) */
+void REGPARAM2 CPUFUNC(op_66ff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (6)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_131003;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_131003: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (EQ) */
+void REGPARAM2 CPUFUNC(op_6700_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131004;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131004: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (EQ) */
+void REGPARAM2 CPUFUNC(op_6701_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131005;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131005: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (EQ) */
+void REGPARAM2 CPUFUNC(op_67ff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (7)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_131006;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_131006: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (VC) */
+void REGPARAM2 CPUFUNC(op_6800_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131007;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131007: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (VC) */
+void REGPARAM2 CPUFUNC(op_6801_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131008;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131008: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (VC) */
+void REGPARAM2 CPUFUNC(op_68ff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (8)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_131009;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_131009: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (VS) */
+void REGPARAM2 CPUFUNC(op_6900_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131010;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131010: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (VS) */
+void REGPARAM2 CPUFUNC(op_6901_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131011;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131011: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (VS) */
+void REGPARAM2 CPUFUNC(op_69ff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (9)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_131012;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_131012: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (PL) */
+void REGPARAM2 CPUFUNC(op_6a00_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131013;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131013: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (PL) */
+void REGPARAM2 CPUFUNC(op_6a01_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131014;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131014: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (PL) */
+void REGPARAM2 CPUFUNC(op_6aff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (10)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_131015;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_131015: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (MI) */
+void REGPARAM2 CPUFUNC(op_6b00_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131016;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131016: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (MI) */
+void REGPARAM2 CPUFUNC(op_6b01_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131017;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131017: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (MI) */
+void REGPARAM2 CPUFUNC(op_6bff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (11)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_131018;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_131018: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (GE) */
+void REGPARAM2 CPUFUNC(op_6c00_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131019;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131019: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (GE) */
+void REGPARAM2 CPUFUNC(op_6c01_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131020;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131020: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (GE) */
+void REGPARAM2 CPUFUNC(op_6cff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (12)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_131021;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_131021: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (LT) */
+void REGPARAM2 CPUFUNC(op_6d00_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131022;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131022: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (LT) */
+void REGPARAM2 CPUFUNC(op_6d01_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131023;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131023: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (LT) */
+void REGPARAM2 CPUFUNC(op_6dff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (13)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_131024;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_131024: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (GT) */
+void REGPARAM2 CPUFUNC(op_6e00_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131025;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131025: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (GT) */
+void REGPARAM2 CPUFUNC(op_6e01_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131026;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131026: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (GT) */
+void REGPARAM2 CPUFUNC(op_6eff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (14)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_131027;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_131027: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.W #.W (LE) */
+void REGPARAM2 CPUFUNC(op_6f00_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = regs.irc;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131028;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	do_cycles_ce000_internal (2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131028: ;
+return;
+} /* 12 (2/0) */
+
+/* BccQ.B # (LE) */
+void REGPARAM2 CPUFUNC(op_6f01_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	do_cycles_ce000_internal (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_131029;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	get_word_ce000_prefetch (2);
+}}l_131029: ;
+return;
+} /* 8 (1/0) */
+
+/* Bcc.L #.L (LE) */
+void REGPARAM2 CPUFUNC(op_6fff_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{	do_cycles_ce000_internal (2);
+	if (cctrue (15)) {
+		exception3i (opcode, m68k_getpci () + 1);
+		goto l_131030;
+	}
+	m68k_incpci (2);
+	do_cycles_ce000_internal (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}l_131030: ;
+return;
+} /* 8 (1/0) */
+
+/* MOVEQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_7000_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}return;
+} /* 4 (1/0) */
+
+/* OR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8000_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* OR.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_8010_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (2/0) */
+
+/* OR.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_8018_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (2/0) */
+
+/* OR.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_8020_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (2/0) */
+
+/* OR.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_8028_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* OR.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_8030_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* OR.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_8038_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* OR.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_8039_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (4/0) */
+
+/* OR.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_803a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* OR.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_803b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* OR.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_803c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* OR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8040_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* OR.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_8050_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131044;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (2);
+l_131044: ;
+return;
+} /* 8 (2/0) */
+
+/* OR.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_8058_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131045;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (2);
+l_131045: ;
+return;
+} /* 8 (2/0) */
+
+/* OR.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_8060_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131046;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (2);
+l_131046: ;
+return;
+} /* 10 (2/0) */
+
+/* OR.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_8068_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131047;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_131047: ;
+return;
+} /* 12 (3/0) */
+
+/* OR.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_8070_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131048;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_131048: ;
+return;
+} /* 14 (3/0) */
+
+/* OR.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_8078_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131049;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_131049: ;
+return;
+} /* 12 (3/0) */
+
+/* OR.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_8079_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131050;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (6);
+l_131050: ;
+return;
+} /* 16 (4/0) */
+
+/* OR.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_807a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131051;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_131051: ;
+return;
+} /* 12 (3/0) */
+
+/* OR.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_807b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131052;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_131052: ;
+return;
+} /* 14 (3/0) */
+
+/* OR.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_807c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* OR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8080_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* OR.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_8090_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131055;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (2);
+l_131055: ;
+return;
+} /* 14 (3/0) */
+
+/* OR.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_8098_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131056;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (2);
+l_131056: ;
+return;
+} /* 14 (3/0) */
+
+/* OR.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_80a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131057;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (2);
+l_131057: ;
+return;
+} /* 16 (3/0) */
+
+/* OR.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_80a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131058;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_131058: ;
+return;
+} /* 18 (4/0) */
+
+/* OR.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131059;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_131059: ;
+return;
+} /* 20 (4/0) */
+
+/* OR.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_80b8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131060;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_131060: ;
+return;
+} /* 18 (4/0) */
+
+/* OR.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_80b9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131061;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (6);
+l_131061: ;
+return;
+} /* 22 (5/0) */
+
+/* OR.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_80ba_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131062;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_131062: ;
+return;
+} /* 18 (4/0) */
+
+/* OR.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80bb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131063;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_131063: ;
+return;
+} /* 20 (4/0) */
+
+/* OR.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_80bc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+} /* 16 (3/0) */
+
+/* DIVU.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_80c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_131065;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+{		int cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}l_131065: ;
+return;
+} /* 4+ (1/0) */
+
+/* DIVU.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_80d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131066;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_131066;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+{		int cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}}}l_131066: ;
+return;
+} /* 8+ (2/0) */
+
+/* DIVU.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_80d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131067;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_131067;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+{		int cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}}}l_131067: ;
+return;
+} /* 8+ (2/0) */
+
+/* DIVU.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_80e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131068;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_131068;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+{		int cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}}}l_131068: ;
+return;
+} /* 10+ (2/0) */
+
+/* DIVU.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_80e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131069;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_131069;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+{		int cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}}}l_131069: ;
+return;
+} /* 12+ (3/0) */
+
+/* DIVU.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131070;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_131070;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+{		int cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}}}l_131070: ;
+return;
+} /* 14+ (3/0) */
+
+/* DIVU.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_80f8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131071;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_131071;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+{		int cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}}}l_131071: ;
+return;
+} /* 12+ (3/0) */
+
+/* DIVU.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_80f9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131072;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (6);
+		Exception (5);
+		goto l_131072;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+{		int cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (6);
+	}
+}}}}}}l_131072: ;
+return;
+} /* 16+ (4/0) */
+
+/* DIVU.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_80fa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131073;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_131073;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+{		int cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}}}l_131073: ;
+return;
+} /* 12+ (3/0) */
+
+/* DIVU.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80fb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131074;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_131074;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+{		int cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}}}l_131074: ;
+return;
+} /* 14+ (3/0) */
+
+/* DIVU.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_80fc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_131075;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+{		int cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}l_131075: ;
+return;
+} /* 8+ (2/0) */
+
+/* SBCD.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8100_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* SBCD.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_8108_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 18; 
+{	do_cycles_ce000_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 18 (3/1) */
+
+/* OR.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_8110_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* OR.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_8118_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* OR.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_8120_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* OR.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_8128_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* OR.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_8130_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* OR.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_8138_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* OR.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_8139_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* OR.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_8150_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131085;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (2);
+l_131085: ;
+return;
+} /* 12 (2/1) */
+
+/* OR.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_8158_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131086;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (2);
+l_131086: ;
+return;
+} /* 12 (2/1) */
+
+/* OR.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_8160_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131087;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (2);
+l_131087: ;
+return;
+} /* 14 (2/1) */
+
+/* OR.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_8168_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131088;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_131088: ;
+return;
+} /* 16 (3/1) */
+
+/* OR.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_8170_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131089;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_131089: ;
+return;
+} /* 18 (3/1) */
+
+/* OR.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_8178_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131090;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_131090: ;
+return;
+} /* 16 (3/1) */
+
+/* OR.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_8179_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_131091;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (6);
+l_131091: ;
+return;
+} /* 20 (4/1) */
+
+/* OR.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_8190_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131092;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_131092: ;
+return;
+} /* 20 (3/2) */
+
+/* OR.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_8198_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131093;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_131093: ;
+return;
+} /* 20 (3/2) */
+
+/* OR.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_81a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131094;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_131094: ;
+return;
+} /* 22 (3/2) */
+
+/* OR.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_81a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131095;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_131095: ;
+return;
+} /* 24 (4/2) */
+
+/* OR.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_81b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 26; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131096;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_131096: ;
+return;
+} /* 26 (4/2) */
+
+/* OR.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_81b8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131097;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_131097: ;
+return;
+} /* 24 (4/2) */
+
+/* OR.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_81b9_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_131098;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_131098: ;
+return;
+} /* 28 (5/2) */
+
+/* DIVS.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_81c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_131099;
+	}
+	CLEAR_CZNV ();
+{		int cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}l_131099: ;
+return;
+} /* 4+ (1/0) */
+
+/* DIVS.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_81d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131100;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_131100;
+	}
+	CLEAR_CZNV ();
+{		int cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}}}l_131100: ;
+return;
+} /* 8+ (2/0) */
+
+/* DIVS.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_81d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131101;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_131101;
+	}
+	CLEAR_CZNV ();
+{		int cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}}}l_131101: ;
+return;
+} /* 8+ (2/0) */
+
+/* DIVS.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_81e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131102;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (2);
+		Exception (5);
+		goto l_131102;
+	}
+	CLEAR_CZNV ();
+{		int cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}}}l_131102: ;
+return;
+} /* 10+ (2/0) */
+
+/* DIVS.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_81e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131103;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_131103;
+	}
+	CLEAR_CZNV ();
+{		int cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}}}l_131103: ;
+return;
+} /* 12+ (3/0) */
+
+/* DIVS.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_81f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131104;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_131104;
+	}
+	CLEAR_CZNV ();
+{		int cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}}}l_131104: ;
+return;
+} /* 14+ (3/0) */
+
+/* DIVS.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_81f8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131105;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_131105;
+	}
+	CLEAR_CZNV ();
+{		int cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}}}l_131105: ;
+return;
+} /* 12+ (3/0) */
+
+/* DIVS.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_81f9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131106;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (6);
+		Exception (5);
+		goto l_131106;
+	}
+	CLEAR_CZNV ();
+{		int cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (6);
+}}}}}}l_131106: ;
+return;
+} /* 16+ (4/0) */
+
+/* DIVS.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_81fa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131107;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_131107;
+	}
+	CLEAR_CZNV ();
+{		int cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}}}l_131107: ;
+return;
+} /* 12+ (3/0) */
+
+/* DIVS.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_81fb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131108;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_131108;
+	}
+	CLEAR_CZNV ();
+{		int cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}}}l_131108: ;
+return;
+} /* 14+ (3/0) */
+
+/* DIVS.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_81fc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpci (4);
+		Exception (5);
+		goto l_131109;
+	}
+	CLEAR_CZNV ();
+{		int cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}l_131109: ;
+return;
+} /* 8+ (2/0) */
+
+/* SUB.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9000_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* SUB.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_9010_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 8 (2/0) */
+
+/* SUB.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_9018_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 8 (2/0) */
+
+/* SUB.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_9020_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 10 (2/0) */
+
+/* SUB.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_9028_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* SUB.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_9030_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* SUB.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_9038_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* SUB.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_9039_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 16 (4/0) */
+
+/* SUB.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_903a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* SUB.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_903b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* SUB.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_903c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* SUB.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9040_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* SUB.W An,Dn */
+void REGPARAM2 CPUFUNC(op_9048_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* SUB.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_9050_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131123;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (2);
+l_131123: ;
+return;
+} /* 8 (2/0) */
+
+/* SUB.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_9058_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131124;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (2);
+l_131124: ;
+return;
+} /* 8 (2/0) */
+
+/* SUB.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_9060_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131125;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (2);
+l_131125: ;
+return;
+} /* 10 (2/0) */
+
+/* SUB.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_9068_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131126;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_131126: ;
+return;
+} /* 12 (3/0) */
+
+/* SUB.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_9070_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131127;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_131127: ;
+return;
+} /* 14 (3/0) */
+
+/* SUB.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_9078_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131128;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_131128: ;
+return;
+} /* 12 (3/0) */
+
+/* SUB.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_9079_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131129;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+l_131129: ;
+return;
+} /* 16 (4/0) */
+
+/* SUB.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_907a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131130;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_131130: ;
+return;
+} /* 12 (3/0) */
+
+/* SUB.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_907b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131131;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_131131: ;
+return;
+} /* 14 (3/0) */
+
+/* SUB.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_907c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* SUB.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9080_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* SUB.L An,Dn */
+void REGPARAM2 CPUFUNC(op_9088_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* SUB.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_9090_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131135;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (2);
+l_131135: ;
+return;
+} /* 14 (3/0) */
+
+/* SUB.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_9098_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131136;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (2);
+l_131136: ;
+return;
+} /* 14 (3/0) */
+
+/* SUB.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_90a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131137;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (2);
+l_131137: ;
+return;
+} /* 16 (3/0) */
+
+/* SUB.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_90a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131138;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_131138: ;
+return;
+} /* 18 (4/0) */
+
+/* SUB.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_90b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131139;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_131139: ;
+return;
+} /* 20 (4/0) */
+
+/* SUB.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_90b8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131140;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_131140: ;
+return;
+} /* 18 (4/0) */
+
+/* SUB.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_90b9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131141;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (6);
+l_131141: ;
+return;
+} /* 22 (5/0) */
+
+/* SUB.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_90ba_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131142;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_131142: ;
+return;
+} /* 18 (4/0) */
+
+/* SUB.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_90bb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131143;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_131143: ;
+return;
+} /* 20 (4/0) */
+
+/* SUB.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_90bc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/0) */
+
+/* SUBA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_90c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* SUBA.W An,An */
+void REGPARAM2 CPUFUNC(op_90c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* SUBA.W (An),An */
+void REGPARAM2 CPUFUNC(op_90d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131147;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131147: ;
+return;
+} /* 12 (2/0) */
+
+/* SUBA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_90d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131148;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131148: ;
+return;
+} /* 12 (2/0) */
+
+/* SUBA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_90e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131149;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131149: ;
+return;
+} /* 14 (2/0) */
+
+/* SUBA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_90e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131150;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131150: ;
+return;
+} /* 16 (3/0) */
+
+/* SUBA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_90f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131151;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131151: ;
+return;
+} /* 18 (3/0) */
+
+/* SUBA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_90f8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131152;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131152: ;
+return;
+} /* 16 (3/0) */
+
+/* SUBA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_90f9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131153;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+l_131153: ;
+return;
+} /* 20 (4/0) */
+
+/* SUBA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_90fa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131154;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131154: ;
+return;
+} /* 16 (3/0) */
+
+/* SUBA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_90fb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131155;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131155: ;
+return;
+} /* 18 (3/0) */
+
+/* SUBA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_90fc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/0) */
+
+/* SUBX.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9100_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* SUBX.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_9108_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 18; 
+{	do_cycles_ce000_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 18 (3/1) */
+
+/* SUB.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_9110_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* SUB.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_9118_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* SUB.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_9120_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* SUB.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_9128_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* SUB.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_9130_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* SUB.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_9138_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* SUB.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_9139_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* SUBX.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9140_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* SUBX.W -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_9148_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 18; 
+{	do_cycles_ce000_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131167;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131167;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}}	m68k_incpci (2);
+l_131167: ;
+return;
+} /* 18 (3/1) */
+
+/* SUB.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_9150_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131168;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_131168: ;
+return;
+} /* 12 (2/1) */
+
+/* SUB.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_9158_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131169;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_131169: ;
+return;
+} /* 12 (2/1) */
+
+/* SUB.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_9160_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131170;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_131170: ;
+return;
+} /* 14 (2/1) */
+
+/* SUB.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_9168_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131171;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_131171: ;
+return;
+} /* 16 (3/1) */
+
+/* SUB.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_9170_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131172;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_131172: ;
+return;
+} /* 18 (3/1) */
+
+/* SUB.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_9178_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131173;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_131173: ;
+return;
+} /* 16 (3/1) */
+
+/* SUB.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_9179_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_131174;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_131174: ;
+return;
+} /* 20 (4/1) */
+
+/* SUBX.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9180_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* SUBX.L -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_9188_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 30; 
+{	do_cycles_ce000_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131176;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131176;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_word (dsta, newv >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, newv);
+}}}}}}}}}	m68k_incpci (2);
+l_131176: ;
+return;
+} /* 30 (5/2) */
+
+/* SUB.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_9190_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131177;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_131177: ;
+return;
+} /* 20 (3/2) */
+
+/* SUB.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_9198_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131178;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_131178: ;
+return;
+} /* 20 (3/2) */
+
+/* SUB.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_91a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131179;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_131179: ;
+return;
+} /* 22 (3/2) */
+
+/* SUB.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_91a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131180;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_131180: ;
+return;
+} /* 24 (4/2) */
+
+/* SUB.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_91b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 26; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131181;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_131181: ;
+return;
+} /* 26 (4/2) */
+
+/* SUB.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_91b8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131182;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_131182: ;
+return;
+} /* 24 (4/2) */
+
+/* SUB.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_91b9_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_131183;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_131183: ;
+return;
+} /* 28 (5/2) */
+
+/* SUBA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_91c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* SUBA.L An,An */
+void REGPARAM2 CPUFUNC(op_91c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* SUBA.L (An),An */
+void REGPARAM2 CPUFUNC(op_91d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131186;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131186: ;
+return;
+} /* 14 (3/0) */
+
+/* SUBA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_91d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131187;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131187: ;
+return;
+} /* 14 (3/0) */
+
+/* SUBA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_91e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131188;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131188: ;
+return;
+} /* 16 (3/0) */
+
+/* SUBA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_91e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131189;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131189: ;
+return;
+} /* 18 (4/0) */
+
+/* SUBA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_91f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131190;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131190: ;
+return;
+} /* 20 (4/0) */
+
+/* SUBA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_91f8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131191;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131191: ;
+return;
+} /* 18 (4/0) */
+
+/* SUBA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_91f9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131192;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+l_131192: ;
+return;
+} /* 22 (5/0) */
+
+/* SUBA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_91fa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131193;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131193: ;
+return;
+} /* 18 (4/0) */
+
+/* SUBA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_91fb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131194;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131194: ;
+return;
+} /* 20 (4/0) */
+
+/* SUBA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_91fc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/0) */
+
+/* CMP.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b000_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* CMP.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_b010_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 8 (2/0) */
+
+/* CMP.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_b018_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 8 (2/0) */
+
+/* CMP.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_b020_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 10 (2/0) */
+
+/* CMP.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_b028_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* CMP.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b030_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* CMP.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_b038_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* CMP.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_b039_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 16 (4/0) */
+
+/* CMP.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_b03a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* CMP.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b03b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* CMP.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_b03c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* CMP.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b040_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* CMP.W An,Dn */
+void REGPARAM2 CPUFUNC(op_b048_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* CMP.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_b050_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131209;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_131209: ;
+return;
+} /* 8 (2/0) */
+
+/* CMP.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_b058_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131210;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_131210: ;
+return;
+} /* 8 (2/0) */
+
+/* CMP.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_b060_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131211;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_131211: ;
+return;
+} /* 10 (2/0) */
+
+/* CMP.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_b068_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131212;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131212: ;
+return;
+} /* 12 (3/0) */
+
+/* CMP.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b070_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131213;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131213: ;
+return;
+} /* 14 (3/0) */
+
+/* CMP.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_b078_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131214;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131214: ;
+return;
+} /* 12 (3/0) */
+
+/* CMP.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_b079_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131215;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_131215: ;
+return;
+} /* 16 (4/0) */
+
+/* CMP.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_b07a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131216;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131216: ;
+return;
+} /* 12 (3/0) */
+
+/* CMP.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b07b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131217;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131217: ;
+return;
+} /* 14 (3/0) */
+
+/* CMP.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_b07c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* CMP.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b080_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* CMP.L An,Dn */
+void REGPARAM2 CPUFUNC(op_b088_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* CMP.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_b090_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131221;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_131221: ;
+return;
+} /* 14 (3/0) */
+
+/* CMP.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_b098_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131222;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_131222: ;
+return;
+} /* 14 (3/0) */
+
+/* CMP.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_b0a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131223;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_131223: ;
+return;
+} /* 16 (3/0) */
+
+#endif
+
+#ifdef PART_7
+/* CMP.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_b0a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131224;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131224: ;
+return;
+} /* 18 (4/0) */
+
+/* CMP.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b0b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131225;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131225: ;
+return;
+} /* 20 (4/0) */
+
+/* CMP.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_b0b8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131226;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131226: ;
+return;
+} /* 18 (4/0) */
+
+/* CMP.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_b0b9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131227;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_131227: ;
+return;
+} /* 22 (5/0) */
+
+/* CMP.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_b0ba_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131228;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131228: ;
+return;
+} /* 18 (4/0) */
+
+/* CMP.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b0bb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131229;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131229: ;
+return;
+} /* 20 (4/0) */
+
+/* CMP.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_b0bc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return;
+} /* 14 (3/0) */
+
+/* CMPA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_b0c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* CMPA.W An,An */
+void REGPARAM2 CPUFUNC(op_b0c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* CMPA.W (An),An */
+void REGPARAM2 CPUFUNC(op_b0d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131233;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_131233: ;
+return;
+} /* 10 (2/0) */
+
+/* CMPA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_b0d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131234;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_131234: ;
+return;
+} /* 10 (2/0) */
+
+/* CMPA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_b0e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131235;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_131235: ;
+return;
+} /* 12 (2/0) */
+
+/* CMPA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_b0e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131236;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131236: ;
+return;
+} /* 14 (3/0) */
+
+/* CMPA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_b0f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131237;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131237: ;
+return;
+} /* 16 (3/0) */
+
+/* CMPA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_b0f8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131238;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131238: ;
+return;
+} /* 14 (3/0) */
+
+/* CMPA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_b0f9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131239;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_131239: ;
+return;
+} /* 18 (4/0) */
+
+/* CMPA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_b0fa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131240;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131240: ;
+return;
+} /* 14 (3/0) */
+
+/* CMPA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_b0fb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131241;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131241: ;
+return;
+} /* 16 (3/0) */
+
+/* CMPA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_b0fc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 10 (2/0) */
+
+/* EOR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b100_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* CMPM.B (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_b108_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+return;
+} /* 12 (3/0) */
+
+/* EOR.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_b110_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* EOR.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_b118_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* EOR.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_b120_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* EOR.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_b128_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* EOR.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_b130_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* EOR.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_b138_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* EOR.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_b139_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* EOR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b140_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* CMPM.W (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_b148_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131253;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131253;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}}}	m68k_incpci (2);
+l_131253: ;
+return;
+} /* 12 (3/0) */
+
+/* EOR.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_b150_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131254;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (2);
+l_131254: ;
+return;
+} /* 12 (2/1) */
+
+/* EOR.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_b158_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131255;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (2);
+l_131255: ;
+return;
+} /* 12 (2/1) */
+
+/* EOR.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_b160_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131256;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (2);
+l_131256: ;
+return;
+} /* 14 (2/1) */
+
+/* EOR.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_b168_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131257;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_131257: ;
+return;
+} /* 16 (3/1) */
+
+/* EOR.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_b170_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131258;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_131258: ;
+return;
+} /* 18 (3/1) */
+
+/* EOR.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_b178_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131259;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_131259: ;
+return;
+} /* 16 (3/1) */
+
+/* EOR.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_b179_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_131260;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (6);
+l_131260: ;
+return;
+} /* 20 (4/1) */
+
+/* EOR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b180_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* CMPM.L (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_b188_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131262;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131262;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}}}	m68k_incpci (2);
+l_131262: ;
+return;
+} /* 20 (5/0) */
+
+/* EOR.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_b190_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131263;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_131263: ;
+return;
+} /* 20 (3/2) */
+
+/* EOR.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_b198_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131264;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_131264: ;
+return;
+} /* 20 (3/2) */
+
+/* EOR.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_b1a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131265;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_131265: ;
+return;
+} /* 22 (3/2) */
+
+/* EOR.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_b1a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131266;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_131266: ;
+return;
+} /* 24 (4/2) */
+
+/* EOR.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_b1b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 26; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131267;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_131267: ;
+return;
+} /* 26 (4/2) */
+
+/* EOR.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_b1b8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131268;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_131268: ;
+return;
+} /* 24 (4/2) */
+
+/* EOR.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_b1b9_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_131269;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_131269: ;
+return;
+} /* 28 (5/2) */
+
+/* CMPA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_b1c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* CMPA.L An,An */
+void REGPARAM2 CPUFUNC(op_b1c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* CMPA.L (An),An */
+void REGPARAM2 CPUFUNC(op_b1d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131272;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_131272: ;
+return;
+} /* 14 (3/0) */
+
+/* CMPA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_b1d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131273;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_131273: ;
+return;
+} /* 14 (3/0) */
+
+/* CMPA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_b1e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131274;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+l_131274: ;
+return;
+} /* 16 (3/0) */
+
+/* CMPA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_b1e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131275;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131275: ;
+return;
+} /* 18 (4/0) */
+
+/* CMPA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_b1f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131276;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131276: ;
+return;
+} /* 20 (4/0) */
+
+/* CMPA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_b1f8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131277;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131277: ;
+return;
+} /* 18 (4/0) */
+
+/* CMPA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_b1f9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131278;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (6);
+l_131278: ;
+return;
+} /* 22 (5/0) */
+
+/* CMPA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_b1fa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131279;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131279: ;
+return;
+} /* 18 (4/0) */
+
+/* CMPA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_b1fb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131280;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (4);
+l_131280: ;
+return;
+} /* 20 (4/0) */
+
+/* CMPA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_b1fc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return;
+} /* 14 (3/0) */
+
+/* AND.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c000_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* AND.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_c010_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (2/0) */
+
+/* AND.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c018_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (2/0) */
+
+/* AND.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c020_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 10 (2/0) */
+
+/* AND.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c028_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* AND.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c030_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* AND.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c038_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* AND.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c039_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (4/0) */
+
+/* AND.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c03a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* AND.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c03b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* AND.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_c03c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* AND.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c040_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* AND.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_c050_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131294;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (2);
+l_131294: ;
+return;
+} /* 8 (2/0) */
+
+/* AND.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c058_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131295;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (2);
+l_131295: ;
+return;
+} /* 8 (2/0) */
+
+/* AND.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c060_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131296;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (2);
+l_131296: ;
+return;
+} /* 10 (2/0) */
+
+/* AND.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c068_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131297;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_131297: ;
+return;
+} /* 12 (3/0) */
+
+/* AND.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c070_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131298;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_131298: ;
+return;
+} /* 14 (3/0) */
+
+/* AND.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c078_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131299;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_131299: ;
+return;
+} /* 12 (3/0) */
+
+/* AND.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c079_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131300;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (6);
+l_131300: ;
+return;
+} /* 16 (4/0) */
+
+/* AND.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c07a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131301;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_131301: ;
+return;
+} /* 12 (3/0) */
+
+/* AND.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c07b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131302;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}	m68k_incpci (4);
+l_131302: ;
+return;
+} /* 14 (3/0) */
+
+/* AND.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_c07c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* AND.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c080_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* AND.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_c090_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131305;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (2);
+l_131305: ;
+return;
+} /* 14 (3/0) */
+
+/* AND.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c098_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131306;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (2);
+l_131306: ;
+return;
+} /* 14 (3/0) */
+
+/* AND.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c0a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131307;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (2);
+l_131307: ;
+return;
+} /* 16 (3/0) */
+
+/* AND.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c0a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131308;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_131308: ;
+return;
+} /* 18 (4/0) */
+
+/* AND.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131309;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_131309: ;
+return;
+} /* 20 (4/0) */
+
+/* AND.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c0b8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131310;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_131310: ;
+return;
+} /* 18 (4/0) */
+
+/* AND.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c0b9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131311;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (6);
+l_131311: ;
+return;
+} /* 22 (5/0) */
+
+/* AND.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c0ba_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131312;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_131312: ;
+return;
+} /* 18 (4/0) */
+
+/* AND.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0bb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131313;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}	m68k_incpci (4);
+l_131313: ;
+return;
+} /* 20 (4/0) */
+
+/* AND.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_c0bc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+} /* 16 (3/0) */
+
+/* MULU.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c0c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int cycles = 38 - 4, bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}return;
+} /* 38+ (1/0) */
+
+/* MULU.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_c0d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 42; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131316;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int cycles = 38 - 4, bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}}l_131316: ;
+return;
+} /* 42+ (2/0) */
+
+/* MULU.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c0d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 42; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131317;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int cycles = 38 - 4, bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}}l_131317: ;
+return;
+} /* 42+ (2/0) */
+
+/* MULU.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c0e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 44; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131318;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int cycles = 38 - 4, bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}}l_131318: ;
+return;
+} /* 44+ (2/0) */
+
+/* MULU.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c0e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 46; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131319;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int cycles = 38 - 4, bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}}l_131319: ;
+return;
+} /* 46+ (3/0) */
+
+/* MULU.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 48; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131320;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int cycles = 38 - 4, bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}}l_131320: ;
+return;
+} /* 48+ (3/0) */
+
+/* MULU.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c0f8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 46; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131321;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int cycles = 38 - 4, bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}}l_131321: ;
+return;
+} /* 46+ (3/0) */
+
+/* MULU.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c0f9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 50; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131322;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int cycles = 38 - 4, bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (6);
+}}}}}}l_131322: ;
+return;
+} /* 50+ (4/0) */
+
+/* MULU.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c0fa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 46; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131323;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int cycles = 38 - 4, bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}}l_131323: ;
+return;
+} /* 46+ (3/0) */
+
+/* MULU.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0fb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 48; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131324;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int cycles = 38 - 4, bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}}l_131324: ;
+return;
+} /* 48+ (3/0) */
+
+/* MULU.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_c0fc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 42; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	int cycles = 38 - 4, bits;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	for(bits = 0; bits < 16 && src; bits++, src >>= 1)
+		if (src & 1) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}return;
+} /* 42+ (2/0) */
+
+/* ABCD.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c100_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* ABCD.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_c108_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 18; 
+{	do_cycles_ce000_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 18 (3/1) */
+
+/* AND.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_c110_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* AND.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_c118_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* AND.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_c120_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* AND.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_c128_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* AND.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_c130_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* AND.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_c138_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* AND.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_c139_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* EXG.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c140_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* EXG.L An,An */
+void REGPARAM2 CPUFUNC(op_c148_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+	m68k_areg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* AND.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_c150_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131337;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (2);
+l_131337: ;
+return;
+} /* 12 (2/1) */
+
+/* AND.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_c158_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131338;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (2);
+l_131338: ;
+return;
+} /* 12 (2/1) */
+
+/* AND.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_c160_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131339;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (2);
+l_131339: ;
+return;
+} /* 14 (2/1) */
+
+/* AND.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_c168_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131340;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_131340: ;
+return;
+} /* 16 (3/1) */
+
+/* AND.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_c170_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131341;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_131341: ;
+return;
+} /* 18 (3/1) */
+
+/* AND.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_c178_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131342;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (4);
+l_131342: ;
+return;
+} /* 16 (3/1) */
+
+/* AND.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_c179_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_131343;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	ipl_fetch ();
+	x_put_word (dsta, src);
+}}}}}	m68k_incpci (6);
+l_131343: ;
+return;
+} /* 20 (4/1) */
+
+/* EXG.L Dn,An */
+void REGPARAM2 CPUFUNC(op_c188_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* AND.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_c190_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131345;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_131345: ;
+return;
+} /* 20 (3/2) */
+
+/* AND.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_c198_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131346;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_131346: ;
+return;
+} /* 20 (3/2) */
+
+/* AND.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_c1a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131347;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (2);
+l_131347: ;
+return;
+} /* 22 (3/2) */
+
+/* AND.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_c1a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131348;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_131348: ;
+return;
+} /* 24 (4/2) */
+
+/* AND.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_c1b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 26; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131349;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_131349: ;
+return;
+} /* 26 (4/2) */
+
+/* AND.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_c1b8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131350;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (4);
+l_131350: ;
+return;
+} /* 24 (4/2) */
+
+/* AND.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_c1b9_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_131351;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	x_put_word (dsta + 2, src);
+	ipl_fetch ();
+x_put_word (dsta, src >> 16);
+}}}}}	m68k_incpci (6);
+l_131351: ;
+return;
+} /* 28 (5/2) */
+
+/* MULS.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c1c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int cycles = 38 - 4, bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 38+ (1/0) */
+
+/* MULS.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_c1d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 42; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131353;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int cycles = 38 - 4, bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131353: ;
+return;
+} /* 42+ (2/0) */
+
+/* MULS.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c1d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 42; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131354;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int cycles = 38 - 4, bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131354: ;
+return;
+} /* 42+ (2/0) */
+
+/* MULS.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c1e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 44; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131355;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int cycles = 38 - 4, bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131355: ;
+return;
+} /* 44+ (2/0) */
+
+/* MULS.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c1e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 46; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131356;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int cycles = 38 - 4, bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131356: ;
+return;
+} /* 46+ (3/0) */
+
+/* MULS.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c1f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 48; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131357;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int cycles = 38 - 4, bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131357: ;
+return;
+} /* 48+ (3/0) */
+
+/* MULS.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c1f8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 46; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131358;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int cycles = 38 - 4, bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131358: ;
+return;
+} /* 46+ (3/0) */
+
+/* MULS.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c1f9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 50; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131359;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int cycles = 38 - 4, bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+l_131359: ;
+return;
+} /* 50+ (4/0) */
+
+/* MULS.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c1fa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 46; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131360;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int cycles = 38 - 4, bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131360: ;
+return;
+} /* 46+ (3/0) */
+
+/* MULS.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c1fb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 48; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131361;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int cycles = 38 - 4, bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131361: ;
+return;
+} /* 48+ (3/0) */
+
+/* MULS.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_c1fc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 42; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	int cycles = 38 - 4, bits;
+	uae_u32 usrc;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	usrc = ((uae_u32)src) << 1;
+	for(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)
+		if ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return;
+} /* 42+ (2/0) */
+
+/* ADD.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d000_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* ADD.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_d010_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 8 (2/0) */
+
+/* ADD.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_d018_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 8 (2/0) */
+
+/* ADD.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_d020_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 10 (2/0) */
+
+/* ADD.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_d028_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* ADD.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d030_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* ADD.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_d038_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* ADD.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_d039_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 16 (4/0) */
+
+/* ADD.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_d03a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 12 (3/0) */
+
+/* ADD.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d03b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 14 (3/0) */
+
+/* ADD.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_d03c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_ce000_prefetch (4);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* ADD.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d040_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* ADD.W An,Dn */
+void REGPARAM2 CPUFUNC(op_d048_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* ADD.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_d050_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131376;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (2);
+l_131376: ;
+return;
+} /* 8 (2/0) */
+
+/* ADD.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_d058_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131377;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (2);
+l_131377: ;
+return;
+} /* 8 (2/0) */
+
+/* ADD.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_d060_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131378;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (2);
+l_131378: ;
+return;
+} /* 10 (2/0) */
+
+/* ADD.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_d068_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131379;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_131379: ;
+return;
+} /* 12 (3/0) */
+
+/* ADD.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d070_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131380;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_131380: ;
+return;
+} /* 14 (3/0) */
+
+/* ADD.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_d078_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131381;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_131381: ;
+return;
+} /* 12 (3/0) */
+
+/* ADD.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_d079_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131382;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+l_131382: ;
+return;
+} /* 16 (4/0) */
+
+/* ADD.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_d07a_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131383;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_131383: ;
+return;
+} /* 12 (3/0) */
+
+/* ADD.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d07b_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131384;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_131384: ;
+return;
+} /* 14 (3/0) */
+
+/* ADD.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_d07c_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+} /* 8 (2/0) */
+
+/* ADD.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d080_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* ADD.L An,Dn */
+void REGPARAM2 CPUFUNC(op_d088_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* ADD.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_d090_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131388;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (2);
+l_131388: ;
+return;
+} /* 14 (3/0) */
+
+/* ADD.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_d098_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131389;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (2);
+l_131389: ;
+return;
+} /* 14 (3/0) */
+
+/* ADD.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_d0a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131390;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (2);
+l_131390: ;
+return;
+} /* 16 (3/0) */
+
+/* ADD.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_d0a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131391;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_131391: ;
+return;
+} /* 18 (4/0) */
+
+/* ADD.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d0b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131392;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_131392: ;
+return;
+} /* 20 (4/0) */
+
+/* ADD.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_d0b8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131393;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_131393: ;
+return;
+} /* 18 (4/0) */
+
+/* ADD.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_d0b9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131394;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (6);
+l_131394: ;
+return;
+} /* 22 (5/0) */
+
+/* ADD.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_d0ba_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131395;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_131395: ;
+return;
+} /* 18 (4/0) */
+
+/* ADD.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d0bb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131396;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}	m68k_incpci (4);
+l_131396: ;
+return;
+} /* 20 (4/0) */
+
+/* ADD.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_d0bc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/0) */
+
+/* ADDA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_d0c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* ADDA.W An,An */
+void REGPARAM2 CPUFUNC(op_d0c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* ADDA.W (An),An */
+void REGPARAM2 CPUFUNC(op_d0d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131400;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131400: ;
+return;
+} /* 12 (2/0) */
+
+/* ADDA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_d0d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131401;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131401: ;
+return;
+} /* 12 (2/0) */
+
+/* ADDA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_d0e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131402;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131402: ;
+return;
+} /* 14 (2/0) */
+
+/* ADDA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_d0e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131403;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131403: ;
+return;
+} /* 16 (3/0) */
+
+/* ADDA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_d0f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131404;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131404: ;
+return;
+} /* 18 (3/0) */
+
+/* ADDA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_d0f8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131405;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131405: ;
+return;
+} /* 16 (3/0) */
+
+/* ADDA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_d0f9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131406;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+l_131406: ;
+return;
+} /* 20 (4/0) */
+
+/* ADDA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_d0fa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131407;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131407: ;
+return;
+} /* 16 (3/0) */
+
+/* ADDA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_d0fb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131408;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131408: ;
+return;
+} /* 18 (3/0) */
+
+/* ADDA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_d0fc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_ce000_prefetch (4);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return;
+} /* 12 (2/0) */
+
+/* ADDX.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d100_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* ADDX.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_d108_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 18; 
+{	do_cycles_ce000_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 18 (3/1) */
+
+/* ADD.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_d110_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* ADD.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_d118_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* ADD.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_d120_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* ADD.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_d128_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* ADD.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_d130_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* ADD.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_d138_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* ADD.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_d139_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* ADDX.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d140_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* ADDX.W -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_d148_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 18; 
+{	do_cycles_ce000_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131420;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131420;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}}	m68k_incpci (2);
+l_131420: ;
+return;
+} /* 18 (3/1) */
+
+/* ADD.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_d150_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131421;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_131421: ;
+return;
+} /* 12 (2/1) */
+
+/* ADD.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_d158_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131422;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_131422: ;
+return;
+} /* 12 (2/1) */
+
+/* ADD.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_d160_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131423;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (2);
+l_131423: ;
+return;
+} /* 14 (2/1) */
+
+/* ADD.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_d168_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131424;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_131424: ;
+return;
+} /* 16 (3/1) */
+
+/* ADD.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_d170_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131425;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_131425: ;
+return;
+} /* 18 (3/1) */
+
+/* ADD.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_d178_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131426;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (4);
+l_131426: ;
+return;
+} /* 16 (3/1) */
+
+/* ADD.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_d179_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_131427;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 dst = x_get_word (dsta);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	ipl_fetch ();
+	x_put_word (dsta, newv);
+}}}}}}}}	m68k_incpci (6);
+l_131427: ;
+return;
+} /* 20 (4/1) */
+
+/* ADDX.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d180_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* ADDX.L -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_d188_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 30; 
+{	do_cycles_ce000_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131429;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131429;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_word (dsta, newv >> 16);
+	ipl_fetch ();
+	x_put_word (dsta + 2, newv);
+}}}}}}}}}	m68k_incpci (2);
+l_131429: ;
+return;
+} /* 30 (5/2) */
+
+/* ADD.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_d190_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131430;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_131430: ;
+return;
+} /* 20 (3/2) */
+
+/* ADD.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_d198_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131431;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_131431: ;
+return;
+} /* 20 (3/2) */
+
+/* ADD.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_d1a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131432;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (2);
+l_131432: ;
+return;
+} /* 22 (3/2) */
+
+/* ADD.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_d1a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131433;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_131433: ;
+return;
+} /* 24 (4/2) */
+
+/* ADD.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_d1b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 26; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	do_cycles_ce000_internal (2);
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_word_ce000_prefetch (4));
+	if (dsta & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dsta);
+		goto l_131434;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_131434: ;
+return;
+} /* 26 (4/2) */
+
+/* ADD.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_d1b8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dsta & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dsta);
+		goto l_131435;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (4);
+l_131435: ;
+return;
+} /* 24 (4/2) */
+
+/* ADD.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_d1b9_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_word_ce000_prefetch (4) << 16;
+	dsta |= get_word_ce000_prefetch (6);
+	if (dsta & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dsta);
+		goto l_131436;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 dst = x_get_word (dsta) << 16; dst |= x_get_word (dsta + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta + 2, newv);
+	ipl_fetch ();
+x_put_word (dsta, newv >> 16);
+}}}}}}}}	m68k_incpci (6);
+l_131436: ;
+return;
+} /* 28 (5/2) */
+
+/* ADDA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_d1c0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* ADDA.L An,An */
+void REGPARAM2 CPUFUNC(op_d1c8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+} /* 8 (1/0) */
+
+/* ADDA.L (An),An */
+void REGPARAM2 CPUFUNC(op_d1d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131439;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131439: ;
+return;
+} /* 14 (3/0) */
+
+/* ADDA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_d1d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131440;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131440: ;
+return;
+} /* 14 (3/0) */
+
+/* ADDA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_d1e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131441;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+l_131441: ;
+return;
+} /* 16 (3/0) */
+
+/* ADDA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_d1e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131442;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131442: ;
+return;
+} /* 18 (4/0) */
+
+/* ADDA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_d1f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131443;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131443: ;
+return;
+} /* 20 (4/0) */
+
+/* ADDA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_d1f8_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_131444;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131444: ;
+return;
+} /* 18 (4/0) */
+
+/* ADDA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_d1f9_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_131445;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+l_131445: ;
+return;
+} /* 22 (5/0) */
+
+/* ADDA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_d1fa_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131446;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131446: ;
+return;
+} /* 18 (4/0) */
+
+/* ADDA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_d1fb_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpci () + 2;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (tmppc, get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_131447;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	do_cycles_ce000_internal (2);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (4);
+l_131447: ;
+return;
+} /* 20 (4/0) */
+
+/* ADDA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_d1fc_13)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_word_ce000_prefetch (4) << 16;
+	src |= get_word_ce000_prefetch (6);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	do_cycles_ce000_internal (4);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return;
+} /* 16 (3/0) */
+
+/* ASRQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e000_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* LSRQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e008_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ROXRQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e010_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* RORQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e018_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ASR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e020_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* LSR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e028_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ROXR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e030_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ROR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e038_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ASRQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e040_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+#endif
+
+#ifdef PART_8
+/* LSRQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e048_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ROXRQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e050_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* RORQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e058_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ASR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e060_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* LSR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e068_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ROXR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e070_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ROR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e078_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ASRQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e080_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* LSRQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e088_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* ROXRQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e090_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* RORQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e098_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* ASR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* LSR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* ROXR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* ROR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0b8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* ASRW.W (An) */
+void REGPARAM2 CPUFUNC(op_e0d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131473;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131473: ;
+return;
+} /* 12 (2/1) */
+
+/* ASRW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e0d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131474;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131474: ;
+return;
+} /* 12 (2/1) */
+
+/* ASRW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e0e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131475;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131475: ;
+return;
+} /* 14 (2/1) */
+
+/* ASRW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e0e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131476;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131476: ;
+return;
+} /* 16 (3/1) */
+
+/* ASRW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e0f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	do_cycles_ce000_internal (2);
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131477;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131477: ;
+return;
+} /* 18 (3/1) */
+
+/* ASRW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e0f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131478;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131478: ;
+return;
+} /* 16 (3/1) */
+
+/* ASRW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e0f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_ce000_prefetch (4) << 16;
+	dataa |= get_word_ce000_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_131479;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (6);
+l_131479: ;
+return;
+} /* 20 (4/1) */
+
+/* ASLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e100_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* LSLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e108_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ROXLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e110_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ROLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e118_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ASL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e120_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* LSL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e128_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ROXL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e130_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ROL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e138_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ASLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e140_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* LSLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e148_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ROXLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e150_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ROLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e158_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 6;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ASL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e160_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* LSL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e168_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ROXL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e170_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ROL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e178_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	{
+		int cycles = 2;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+} /* 6+ (1/0) */
+
+/* ASLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e180_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* LSLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e188_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* ROXLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e190_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* ROLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e198_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* ASL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1a0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* LSL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1a8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* ROXL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1b0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* ROL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1b8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	{
+		int cycles = 4;
+		cycles += 2 * ccnt;
+		if (cycles > 0) do_cycles_ce000_internal (cycles);
+	}
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+} /* 8+ (1/0) */
+
+/* ASLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e1d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131504;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131504: ;
+return;
+} /* 12 (2/1) */
+
+/* ASLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e1d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131505;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131505: ;
+return;
+} /* 12 (2/1) */
+
+/* ASLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e1e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131506;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131506: ;
+return;
+} /* 14 (2/1) */
+
+/* ASLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e1e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131507;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131507: ;
+return;
+} /* 16 (3/1) */
+
+/* ASLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e1f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	do_cycles_ce000_internal (2);
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131508;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131508: ;
+return;
+} /* 18 (3/1) */
+
+/* ASLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e1f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131509;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131509: ;
+return;
+} /* 16 (3/1) */
+
+/* ASLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e1f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_ce000_prefetch (4) << 16;
+	dataa |= get_word_ce000_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_131510;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (6);
+l_131510: ;
+return;
+} /* 20 (4/1) */
+
+/* LSRW.W (An) */
+void REGPARAM2 CPUFUNC(op_e2d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131511;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131511: ;
+return;
+} /* 12 (2/1) */
+
+/* LSRW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e2d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131512;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131512: ;
+return;
+} /* 12 (2/1) */
+
+/* LSRW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e2e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131513;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131513: ;
+return;
+} /* 14 (2/1) */
+
+/* LSRW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e2e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131514;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131514: ;
+return;
+} /* 16 (3/1) */
+
+/* LSRW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e2f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	do_cycles_ce000_internal (2);
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131515;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131515: ;
+return;
+} /* 18 (3/1) */
+
+/* LSRW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e2f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131516;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131516: ;
+return;
+} /* 16 (3/1) */
+
+/* LSRW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e2f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_ce000_prefetch (4) << 16;
+	dataa |= get_word_ce000_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_131517;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (6);
+l_131517: ;
+return;
+} /* 20 (4/1) */
+
+/* LSLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e3d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131518;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131518: ;
+return;
+} /* 12 (2/1) */
+
+/* LSLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e3d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131519;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131519: ;
+return;
+} /* 12 (2/1) */
+
+/* LSLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e3e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131520;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131520: ;
+return;
+} /* 14 (2/1) */
+
+/* LSLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e3e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131521;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131521: ;
+return;
+} /* 16 (3/1) */
+
+/* LSLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e3f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	do_cycles_ce000_internal (2);
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131522;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131522: ;
+return;
+} /* 18 (3/1) */
+
+/* LSLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e3f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131523;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131523: ;
+return;
+} /* 16 (3/1) */
+
+/* LSLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e3f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_ce000_prefetch (4) << 16;
+	dataa |= get_word_ce000_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_131524;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (6);
+l_131524: ;
+return;
+} /* 20 (4/1) */
+
+/* ROXRW.W (An) */
+void REGPARAM2 CPUFUNC(op_e4d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131525;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131525: ;
+return;
+} /* 12 (2/1) */
+
+/* ROXRW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e4d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131526;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131526: ;
+return;
+} /* 12 (2/1) */
+
+/* ROXRW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e4e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131527;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131527: ;
+return;
+} /* 14 (2/1) */
+
+/* ROXRW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e4e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131528;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131528: ;
+return;
+} /* 16 (3/1) */
+
+/* ROXRW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e4f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	do_cycles_ce000_internal (2);
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131529;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131529: ;
+return;
+} /* 18 (3/1) */
+
+/* ROXRW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e4f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131530;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131530: ;
+return;
+} /* 16 (3/1) */
+
+/* ROXRW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e4f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_ce000_prefetch (4) << 16;
+	dataa |= get_word_ce000_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_131531;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (6);
+l_131531: ;
+return;
+} /* 20 (4/1) */
+
+/* ROXLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e5d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131532;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131532: ;
+return;
+} /* 12 (2/1) */
+
+/* ROXLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e5d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131533;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131533: ;
+return;
+} /* 12 (2/1) */
+
+/* ROXLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e5e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131534;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131534: ;
+return;
+} /* 14 (2/1) */
+
+/* ROXLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e5e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131535;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131535: ;
+return;
+} /* 16 (3/1) */
+
+/* ROXLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e5f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	do_cycles_ce000_internal (2);
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131536;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131536: ;
+return;
+} /* 18 (3/1) */
+
+/* ROXLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e5f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131537;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131537: ;
+return;
+} /* 16 (3/1) */
+
+/* ROXLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e5f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_ce000_prefetch (4) << 16;
+	dataa |= get_word_ce000_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_131538;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (6);
+l_131538: ;
+return;
+} /* 20 (4/1) */
+
+/* RORW.W (An) */
+void REGPARAM2 CPUFUNC(op_e6d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131539;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131539: ;
+return;
+} /* 12 (2/1) */
+
+/* RORW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e6d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131540;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131540: ;
+return;
+} /* 12 (2/1) */
+
+/* RORW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e6e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131541;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131541: ;
+return;
+} /* 14 (2/1) */
+
+/* RORW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e6e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131542;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131542: ;
+return;
+} /* 16 (3/1) */
+
+/* RORW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e6f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	do_cycles_ce000_internal (2);
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131543;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131543: ;
+return;
+} /* 18 (3/1) */
+
+/* RORW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e6f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131544;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131544: ;
+return;
+} /* 16 (3/1) */
+
+/* RORW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e6f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_ce000_prefetch (4) << 16;
+	dataa |= get_word_ce000_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_131545;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (6);
+l_131545: ;
+return;
+} /* 20 (4/1) */
+
+/* ROLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e7d0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131546;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131546: ;
+return;
+} /* 12 (2/1) */
+
+/* ROLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e7d8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131547;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131547: ;
+return;
+} /* 12 (2/1) */
+
+/* ROLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e7e0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131548;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (2);
+l_131548: ;
+return;
+} /* 14 (2/1) */
+
+/* ROLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e7e8_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131549;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131549: ;
+return;
+} /* 16 (3/1) */
+
+/* ROLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e7f0_13)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 18; 
+{{	uaecptr dataa;
+	do_cycles_ce000_internal (2);
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (dataa & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, dataa);
+		goto l_131550;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131550: ;
+return;
+} /* 18 (3/1) */
+
+/* ROLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e7f8_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (dataa & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, dataa);
+		goto l_131551;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (4);
+l_131551: ;
+return;
+} /* 16 (3/1) */
+
+/* ROLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e7f9_13)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_word_ce000_prefetch (4) << 16;
+	dataa |= get_word_ce000_prefetch (6);
+	if (dataa & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, dataa);
+		goto l_131552;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 data = x_get_word (dataa);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	ipl_fetch ();
+	x_put_word (dataa, val);
+}}}}}	m68k_incpci (6);
+l_131552: ;
+return;
+} /* 20 (4/1) */
+
+#endif
+
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+#endif
+
+#ifdef PART_2
+#endif
+
+#ifdef PART_3
+/* MVSR2.W Dn */
+void REGPARAM2 CPUFUNC(op_40c0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* MVSR2.W (An) */
+void REGPARAM2 CPUFUNC(op_40d0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_140002;
+	}
+{	bus_error_offset = 4;
+	x_put_word (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_140002: ;
+return;
+} /* 12 (1/2) */
+
+/* MVSR2.W (An)+ */
+void REGPARAM2 CPUFUNC(op_40d8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_140003;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) += 2;
+	x_put_word (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_140003: ;
+return;
+} /* 12 (1/2) */
+
+/* MVSR2.W -(An) */
+void REGPARAM2 CPUFUNC(op_40e0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_140004;
+	}
+{	bus_error_offset = 4;
+	m68k_areg (regs, srcreg) = srca;
+	x_put_word (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_140004: ;
+return;
+} /* 14 (1/2) */
+
+/* MVSR2.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_40e8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_140005;
+	}
+{	bus_error_offset = 4;
+	x_put_word (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_140005: ;
+return;
+} /* 16 (2/2) */
+
+/* MVSR2.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_40f0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_140006;
+	}
+{	bus_error_offset = 4;
+	x_put_word (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_140006: ;
+return;
+} /* 18 (2/2) */
+
+/* MVSR2.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_40f8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_write(opcode, srca);
+		goto l_140007;
+	}
+{	bus_error_offset = 4;
+	x_put_word (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_140007: ;
+return;
+} /* 16 (2/2) */
+
+/* MVSR2.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_40f9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_write(opcode, srca);
+		goto l_140008;
+	}
+{	bus_error_offset = 6;
+	x_put_word (srca, regs.sr | 0x0010);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	MakeSR ();
+	ipl_fetch ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (6);
+l_140008: ;
+return;
+} /* 20 (3/2) */
+
+/* CLR.B Dn */
+void REGPARAM2 CPUFUNC(op_4200_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* CLR.B (An) */
+void REGPARAM2 CPUFUNC(op_4210_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, 0);
+}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* CLR.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4218_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, 0);
+}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* CLR.B -(An) */
+void REGPARAM2 CPUFUNC(op_4220_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, 0);
+}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* CLR.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4228_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, 0);
+}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* CLR.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4230_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, 0);
+}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* CLR.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4238_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, 0);
+}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* CLR.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4239_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	ipl_fetch ();
+	x_put_byte (srca, 0);
+}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* CLR.W Dn */
+void REGPARAM2 CPUFUNC(op_4240_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpci (2);
+return;
+} /* 4 (1/0) */
+
+/* CLR.W (An) */
+void REGPARAM2 CPUFUNC(op_4250_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_140018;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, 0);
+}}}}	m68k_incpci (2);
+l_140018: ;
+return;
+} /* 12 (2/1) */
+
+/* CLR.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4258_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_140019;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, 0);
+}}}}	m68k_incpci (2);
+l_140019: ;
+return;
+} /* 12 (2/1) */
+
+/* CLR.W -(An) */
+void REGPARAM2 CPUFUNC(op_4260_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_140020;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, 0);
+}}}}	m68k_incpci (2);
+l_140020: ;
+return;
+} /* 14 (2/1) */
+
+/* CLR.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4268_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_140021;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, 0);
+}}}}	m68k_incpci (4);
+l_140021: ;
+return;
+} /* 16 (3/1) */
+
+/* CLR.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4270_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_140022;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, 0);
+}}}}	m68k_incpci (4);
+l_140022: ;
+return;
+} /* 18 (3/1) */
+
+/* CLR.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4278_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_140023;
+	}
+{	bus_error_offset = 4;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, 0);
+}}}}	m68k_incpci (4);
+l_140023: ;
+return;
+} /* 16 (3/1) */
+
+/* CLR.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4279_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_140024;
+	}
+{	bus_error_offset = 6;
+{	uae_s16 src = x_get_word (srca);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	ipl_fetch ();
+	x_put_word (srca, 0);
+}}}}	m68k_incpci (6);
+l_140024: ;
+return;
+} /* 20 (4/1) */
+
+/* CLR.L Dn */
+void REGPARAM2 CPUFUNC(op_4280_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	do_cycles_ce000_internal (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpci (2);
+return;
+} /* 6 (1/0) */
+
+/* CLR.L (An) */
+void REGPARAM2 CPUFUNC(op_4290_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_140026;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_word (srca + 2, 0);
+	ipl_fetch ();
+x_put_word (srca, 0 >> 16);
+}}}}	m68k_incpci (2);
+l_140026: ;
+return;
+} /* 20 (3/2) */
+
+/* CLR.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4298_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_140027;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) += 4;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_word (srca + 2, 0);
+	ipl_fetch ();
+x_put_word (srca, 0 >> 16);
+}}}}	m68k_incpci (2);
+l_140027: ;
+return;
+} /* 20 (3/2) */
+
+/* CLR.L -(An) */
+void REGPARAM2 CPUFUNC(op_42a0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	do_cycles_ce000_internal (2);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_140028;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	m68k_areg (regs, srcreg) = srca;
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_word (srca + 2, 0);
+	ipl_fetch ();
+x_put_word (srca, 0 >> 16);
+}}}}	m68k_incpci (2);
+l_140028: ;
+return;
+} /* 22 (3/2) */
+
+/* CLR.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_42a8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_140029;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_word (srca + 2, 0);
+	ipl_fetch ();
+x_put_word (srca, 0 >> 16);
+}}}}	m68k_incpci (4);
+l_140029: ;
+return;
+} /* 24 (4/2) */
+
+/* CLR.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_42b0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	if (srca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, srca);
+		goto l_140030;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_word (srca + 2, 0);
+	ipl_fetch ();
+x_put_word (srca, 0 >> 16);
+}}}}	m68k_incpci (4);
+l_140030: ;
+return;
+} /* 26 (4/2) */
+
+/* CLR.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_42b8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	if (srca & 1) {
+	m68k_incpci (4);
+		exception3_read(opcode, srca);
+		goto l_140031;
+	}
+{	bus_error_offset = 4;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_word (srca + 2, 0);
+	ipl_fetch ();
+x_put_word (srca, 0 >> 16);
+}}}}	m68k_incpci (4);
+l_140031: ;
+return;
+} /* 24 (4/2) */
+
+/* CLR.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_42b9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	if (srca & 1) {
+	m68k_incpci (6);
+		exception3_read(opcode, srca);
+		goto l_140032;
+	}
+{	bus_error_offset = 6;
+{	uae_s32 src = x_get_word (srca) << 16; src |= x_get_word (srca + 2);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_word (srca + 2, 0);
+	ipl_fetch ();
+x_put_word (srca, 0 >> 16);
+}}}}	m68k_incpci (6);
+l_140032: ;
+return;
+} /* 28 (5/2) */
+
+#endif
+
+#ifdef PART_4
+/* RTE.L  */
+void REGPARAM2 CPUFUNC(op_4e73_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 45;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_140033; }
+{{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+	if (sra & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, sra);
+		goto l_140033;
+	}
+{	bus_error_offset = 2;
+{	uae_s16 sr = x_get_word (sra);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+	if (pca & 1) {
+	m68k_incpci (2);
+		exception3_read(opcode, pca);
+		goto l_140033;
+	}
+{	bus_error_offset = 2;
+{	uae_s32 pc = x_get_word (pca) << 16; pc |= x_get_word (pca + 2);
+	m68k_areg (regs, 7) += 4;
+	regs.sr = sr;
+	if (pc & 1) {
+		exception3i (0x4E73, pc);
+		goto l_140033;
+	}
+	m68k_setpci (pc);
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	get_word_ce000_prefetch (0);
+	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (2);
+}}}}}}}}l_140033: ;
+return;
+} /* 20 (5/0) */
+
+#endif
+
+#ifdef PART_5
+/* Scc.B Dn (T) */
+void REGPARAM2 CPUFUNC(op_50c0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (T) */
+void REGPARAM2 CPUFUNC(op_50d0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (T) */
+void REGPARAM2 CPUFUNC(op_50d8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (T) */
+void REGPARAM2 CPUFUNC(op_50e0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (0) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (T) */
+void REGPARAM2 CPUFUNC(op_50e8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (0) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (T) */
+void REGPARAM2 CPUFUNC(op_50f0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (0) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (T) */
+void REGPARAM2 CPUFUNC(op_50f8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (0) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (T) */
+void REGPARAM2 CPUFUNC(op_50f9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (0) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (F) */
+void REGPARAM2 CPUFUNC(op_51c0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (F) */
+void REGPARAM2 CPUFUNC(op_51d0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (F) */
+void REGPARAM2 CPUFUNC(op_51d8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (F) */
+void REGPARAM2 CPUFUNC(op_51e0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (1) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (F) */
+void REGPARAM2 CPUFUNC(op_51e8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (1) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (F) */
+void REGPARAM2 CPUFUNC(op_51f0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (1) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (F) */
+void REGPARAM2 CPUFUNC(op_51f8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (1) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (F) */
+void REGPARAM2 CPUFUNC(op_51f9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (1) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (HI) */
+void REGPARAM2 CPUFUNC(op_52c0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (HI) */
+void REGPARAM2 CPUFUNC(op_52d0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (HI) */
+void REGPARAM2 CPUFUNC(op_52d8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (HI) */
+void REGPARAM2 CPUFUNC(op_52e0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (2) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (HI) */
+void REGPARAM2 CPUFUNC(op_52e8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (2) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (HI) */
+void REGPARAM2 CPUFUNC(op_52f0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (2) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (HI) */
+void REGPARAM2 CPUFUNC(op_52f8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (2) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (HI) */
+void REGPARAM2 CPUFUNC(op_52f9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (2) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (LS) */
+void REGPARAM2 CPUFUNC(op_53c0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (LS) */
+void REGPARAM2 CPUFUNC(op_53d0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (LS) */
+void REGPARAM2 CPUFUNC(op_53d8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (LS) */
+void REGPARAM2 CPUFUNC(op_53e0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (3) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (LS) */
+void REGPARAM2 CPUFUNC(op_53e8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (3) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (LS) */
+void REGPARAM2 CPUFUNC(op_53f0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (3) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (LS) */
+void REGPARAM2 CPUFUNC(op_53f8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (3) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (LS) */
+void REGPARAM2 CPUFUNC(op_53f9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (3) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (CC) */
+void REGPARAM2 CPUFUNC(op_54c0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (CC) */
+void REGPARAM2 CPUFUNC(op_54d0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (CC) */
+void REGPARAM2 CPUFUNC(op_54d8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (CC) */
+void REGPARAM2 CPUFUNC(op_54e0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (4) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (CC) */
+void REGPARAM2 CPUFUNC(op_54e8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (4) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (CC) */
+void REGPARAM2 CPUFUNC(op_54f0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (4) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (CC) */
+void REGPARAM2 CPUFUNC(op_54f8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (4) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (CC) */
+void REGPARAM2 CPUFUNC(op_54f9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (4) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (CS) */
+void REGPARAM2 CPUFUNC(op_55c0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (CS) */
+void REGPARAM2 CPUFUNC(op_55d0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (CS) */
+void REGPARAM2 CPUFUNC(op_55d8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (CS) */
+void REGPARAM2 CPUFUNC(op_55e0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (5) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (CS) */
+void REGPARAM2 CPUFUNC(op_55e8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (5) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (CS) */
+void REGPARAM2 CPUFUNC(op_55f0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (5) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (CS) */
+void REGPARAM2 CPUFUNC(op_55f8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (5) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (CS) */
+void REGPARAM2 CPUFUNC(op_55f9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (5) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (NE) */
+void REGPARAM2 CPUFUNC(op_56c0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (NE) */
+void REGPARAM2 CPUFUNC(op_56d0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (NE) */
+void REGPARAM2 CPUFUNC(op_56d8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (NE) */
+void REGPARAM2 CPUFUNC(op_56e0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (6) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (NE) */
+void REGPARAM2 CPUFUNC(op_56e8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (6) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (NE) */
+void REGPARAM2 CPUFUNC(op_56f0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (6) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (NE) */
+void REGPARAM2 CPUFUNC(op_56f8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (6) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (NE) */
+void REGPARAM2 CPUFUNC(op_56f9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (6) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (EQ) */
+void REGPARAM2 CPUFUNC(op_57c0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57d0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (EQ) */
+void REGPARAM2 CPUFUNC(op_57d8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57e0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (7) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57e8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (7) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (EQ) */
+void REGPARAM2 CPUFUNC(op_57f0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (7) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (EQ) */
+void REGPARAM2 CPUFUNC(op_57f8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (7) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (EQ) */
+void REGPARAM2 CPUFUNC(op_57f9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (7) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (VC) */
+void REGPARAM2 CPUFUNC(op_58c0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (VC) */
+void REGPARAM2 CPUFUNC(op_58d0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (VC) */
+void REGPARAM2 CPUFUNC(op_58d8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (VC) */
+void REGPARAM2 CPUFUNC(op_58e0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (8) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (VC) */
+void REGPARAM2 CPUFUNC(op_58e8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (8) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (VC) */
+void REGPARAM2 CPUFUNC(op_58f0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (8) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (VC) */
+void REGPARAM2 CPUFUNC(op_58f8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (8) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (VC) */
+void REGPARAM2 CPUFUNC(op_58f9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (8) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (VS) */
+void REGPARAM2 CPUFUNC(op_59c0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (VS) */
+void REGPARAM2 CPUFUNC(op_59d0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (VS) */
+void REGPARAM2 CPUFUNC(op_59d8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (VS) */
+void REGPARAM2 CPUFUNC(op_59e0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (9) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (VS) */
+void REGPARAM2 CPUFUNC(op_59e8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (9) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (VS) */
+void REGPARAM2 CPUFUNC(op_59f0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (9) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (VS) */
+void REGPARAM2 CPUFUNC(op_59f8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (9) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (VS) */
+void REGPARAM2 CPUFUNC(op_59f9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (9) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (PL) */
+void REGPARAM2 CPUFUNC(op_5ac0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ad0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (PL) */
+void REGPARAM2 CPUFUNC(op_5ad8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ae0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (10) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ae8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (10) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (PL) */
+void REGPARAM2 CPUFUNC(op_5af0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (10) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (PL) */
+void REGPARAM2 CPUFUNC(op_5af8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (10) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (PL) */
+void REGPARAM2 CPUFUNC(op_5af9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (10) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (MI) */
+void REGPARAM2 CPUFUNC(op_5bc0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (MI) */
+void REGPARAM2 CPUFUNC(op_5bd0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (MI) */
+void REGPARAM2 CPUFUNC(op_5bd8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (MI) */
+void REGPARAM2 CPUFUNC(op_5be0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (11) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (MI) */
+void REGPARAM2 CPUFUNC(op_5be8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (11) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (MI) */
+void REGPARAM2 CPUFUNC(op_5bf0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (11) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (MI) */
+void REGPARAM2 CPUFUNC(op_5bf8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (11) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (MI) */
+void REGPARAM2 CPUFUNC(op_5bf9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (11) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (GE) */
+void REGPARAM2 CPUFUNC(op_5cc0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (GE) */
+void REGPARAM2 CPUFUNC(op_5cd0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (GE) */
+void REGPARAM2 CPUFUNC(op_5cd8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (GE) */
+void REGPARAM2 CPUFUNC(op_5ce0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (12) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (GE) */
+void REGPARAM2 CPUFUNC(op_5ce8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (12) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (GE) */
+void REGPARAM2 CPUFUNC(op_5cf0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (12) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (GE) */
+void REGPARAM2 CPUFUNC(op_5cf8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (12) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (GE) */
+void REGPARAM2 CPUFUNC(op_5cf9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (12) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (LT) */
+void REGPARAM2 CPUFUNC(op_5dc0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (LT) */
+void REGPARAM2 CPUFUNC(op_5dd0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (LT) */
+void REGPARAM2 CPUFUNC(op_5dd8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (LT) */
+void REGPARAM2 CPUFUNC(op_5de0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (13) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (LT) */
+void REGPARAM2 CPUFUNC(op_5de8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (13) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (LT) */
+void REGPARAM2 CPUFUNC(op_5df0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (13) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (LT) */
+void REGPARAM2 CPUFUNC(op_5df8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (13) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (LT) */
+void REGPARAM2 CPUFUNC(op_5df9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (13) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (GT) */
+void REGPARAM2 CPUFUNC(op_5ec0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ed0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (GT) */
+void REGPARAM2 CPUFUNC(op_5ed8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ee0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (14) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ee8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (14) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (GT) */
+void REGPARAM2 CPUFUNC(op_5ef0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (14) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (GT) */
+void REGPARAM2 CPUFUNC(op_5ef8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (14) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (GT) */
+void REGPARAM2 CPUFUNC(op_5ef9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (14) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+/* Scc.B Dn (LE) */
+void REGPARAM2 CPUFUNC(op_5fc0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	int cycles = val ? 2 : 0;
+	if (cycles > 0) do_cycles_ce000_internal (cycles);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+} /* 4+ (1/0) */
+
+/* Scc.B (An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fd0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B (An)+ (LE) */
+void REGPARAM2 CPUFUNC(op_5fd8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 12 (2/1) */
+
+/* Scc.B -(An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fe0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	do_cycles_ce000_internal (2);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (4);
+{	int val = cctrue (15) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (2);
+return;
+} /* 14 (2/1) */
+
+/* Scc.B (d16,An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fe8_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (15) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (d8,An,Xn) (LE) */
+void REGPARAM2 CPUFUNC(op_5ff0_14)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	do_cycles_ce000_internal (2);
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_word_ce000_prefetch (4));
+	bus_error_offset = 2;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (15) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 18 (3/1) */
+
+/* Scc.B (xxx).W (LE) */
+void REGPARAM2 CPUFUNC(op_5ff8_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce000_prefetch (4);
+	bus_error_offset = 4;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (6);
+{	int val = cctrue (15) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (4);
+return;
+} /* 16 (3/1) */
+
+/* Scc.B (xxx).L (LE) */
+void REGPARAM2 CPUFUNC(op_5ff9_14)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_word_ce000_prefetch (4) << 16;
+	srca |= get_word_ce000_prefetch (6);
+	bus_error_offset = 6;
+{	uae_s8 src = x_get_byte (srca);
+{	regs.ir = regs.irc;
+	ipl_fetch ();
+	get_word_ce000_prefetch (8);
+{	int val = cctrue (15) ? 0xff : 0;
+	ipl_fetch ();
+	x_put_byte (srca, val);
+}}}}}	m68k_incpci (6);
+return;
+} /* 20 (4/1) */
+
+#endif
+
+#ifdef PART_6
+#endif
+
+#ifdef PART_7
+#endif
+
+#ifdef PART_8
+#endif
+
diff --git a/src/cpu/cpuemu_20.c b/src/cpu/cpuemu_20.c
new file mode 100644
index 0000000..f45cb48
--- /dev/null
+++ b/src/cpu/cpuemu_20.c
@@ -0,0 +1,39508 @@
+#include "main.h"
+#include "sysdeps.h"
+#include "hatari-glue.h"
+#include "maccess.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "cputbl.h"
+#define CPUFUNC(x) x##_ff
+#define SET_CFLG_ALWAYS(x) SET_CFLG(x)
+#define SET_NFLG_ALWAYS(x) SET_NFLG(x)
+#ifdef NOFLAGS
+#include "noflags.h"
+#endif
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0000_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0010_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0018_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0020_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0028_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0030_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0038_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0039_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_003c_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_word_020_prefetch (2);
+	src &= 0xFF;
+	regs.sr |= src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0040_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0050_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0058_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0060_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0068_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0070_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0078_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0079_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_007c_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200018; }
+{	MakeSR ();
+{	uae_s16 src = get_word_020_prefetch (2);
+	regs.sr |= src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200018: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0080_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0090_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0098_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_00b0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_00b8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_00b9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (10);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00d0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200027; }
+}
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200027: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00e8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200028; }
+}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200028: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200029; }
+}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200029: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200030; }
+}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200030: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200031; }
+}
+	regs.irc = get_word_020_prefetch (8);
+}}}	m68k_incpci (8);
+l_200031: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200032; }
+}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200032: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200033; }
+}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200033: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BTST.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0100_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPMR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0108_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 8;  
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_u16 val;
+	MovepByteNbr=1; val = ((x_get_byte (memp) & 0xff) << 8);
+	MovepByteNbr=2; val += (x_get_byte (memp + 2) & 0xff);
+	MovepByteNbr=0;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0110_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (2);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0118_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (2);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0120_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (2);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0128_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0130_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0138_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0139_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_013a_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 2;
+	dsta += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_013b_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,#.B */
+uae_u32 REGPARAM2 CPUFUNC(op_013c_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = (uae_u8)get_word_020_prefetch (2);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0140_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPMR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0148_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 16; 
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_u32 val;
+	MovepByteNbr=1; val = ((x_get_byte (memp) & 0xff) << 24);
+	MovepByteNbr=2; val += ((x_get_byte (memp + 2) & 0xff) << 16);
+	MovepByteNbr=3; val += ((x_get_byte (memp + 4) & 0xff) << 8);
+	MovepByteNbr=4; val += (x_get_byte (memp + 6) & 0xff);
+	MovepByteNbr=0;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0150_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0158_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0160_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0168_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0170_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0178_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0179_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0180_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPRM.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0188_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	MovepByteNbr=1; 	x_put_byte (memp, src >> 8);
+	MovepByteNbr=2; 	x_put_byte (memp + 2, src);
+	MovepByteNbr=0;
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0190_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0198_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01b8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01b9_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_01c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPRM.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	MovepByteNbr=1; 	x_put_byte (memp, src >> 24);
+	MovepByteNbr=2; 	x_put_byte (memp + 2, src >> 16);
+	MovepByteNbr=3; 	x_put_byte (memp + 4, src >> 8);
+	MovepByteNbr=4; 	x_put_byte (memp + 6, src);
+	MovepByteNbr=0;
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_01d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01f8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01f9_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0200_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0210_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0218_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0220_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0228_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0230_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0238_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0239_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ANDSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_023c_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_word_020_prefetch (2);
+	src |= 0xFF00;
+	regs.sr &= src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0240_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0250_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0258_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0260_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0268_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0270_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0278_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0279_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ANDSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_027c_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200090; }
+{	MakeSR ();
+{	uae_s16 src = get_word_020_prefetch (2);
+	regs.sr &= src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200090: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0280_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0290_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0298_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_02b0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_02b8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_02b9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (10);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02d0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200099; }
+}
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200099: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02e8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200100; }
+}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200100: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200101; }
+}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200101: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200102; }
+}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200102: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200103; }
+}
+	regs.irc = get_word_020_prefetch (8);
+}}}	m68k_incpci (8);
+l_200103: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200104; }
+}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200104: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200105; }
+}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200105: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0400_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0410_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0418_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0420_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0428_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0430_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0438_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0439_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0440_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0450_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0458_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0460_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0468_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0470_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0478_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0479_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0480_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0490_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0498_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_04b0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_04b8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_04b9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (10);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04d0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200130; }
+}
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200130: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04e8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200131; }
+}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200131: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200132; }
+}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200132: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200133; }
+}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200133: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200134; }
+}
+	regs.irc = get_word_020_prefetch (8);
+}}}	m68k_incpci (8);
+l_200134: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200135; }
+}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200135: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_200136; }
+}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200136: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0600_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0610_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0618_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0620_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0628_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0630_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0638_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0639_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0640_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0650_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0658_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0660_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0668_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0670_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0678_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0679_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0680_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0690_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0698_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_06b0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_06b8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_06b9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (10);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RTM.L Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_020_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* RTM.L An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_020_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_020_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_020_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_020_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_020_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_020_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_020_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_020_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BTST.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0800_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0810_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0818_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0820_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0828_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0830_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0838_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0839_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (8);
+}}}}	m68k_incpci (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_083a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_083b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0840_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0850_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0858_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0860_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0868_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0870_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0878_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0879_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0880_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0890_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0898_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08b0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08b8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08b9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_08c0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08d0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_08d8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08f0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a00_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a10_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a18_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a20_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a28_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a30_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a38_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a39_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a3c_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_word_020_prefetch (2);
+	src &= 0xFF;
+	regs.sr ^= src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a40_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a50_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a58_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a60_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a68_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a70_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a78_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a79_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a7c_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200221; }
+{	MakeSR ();
+{	uae_s16 src = get_word_020_prefetch (2);
+	regs.sr ^= src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200221: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a80_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a90_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a98_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (10);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CAS.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ad0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ad8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ae0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ae8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
+#ifdef PART_2
+/* CAS.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (0);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (8);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c00_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c10_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c18_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c20_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c28_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c30_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c38_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c39_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (8);
+}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c3a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.B #.B,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c3b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c40_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c50_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c58_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c60_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c68_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c70_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c78_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c79_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (8);
+}}}}}}}	m68k_incpci (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c7a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c7b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c80_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c90_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c98_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (8);
+}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (8);
+}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (10);
+}}}}}}}	m68k_incpci (10);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cba_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 6;
+	dsta += (uae_s32)(uae_s16)get_word_020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (8);
+}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.L #.L,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cbb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (6);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cd0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cd8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ce0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ce8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (0);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (8);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (8);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS2.W #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cfc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 extra;
+	extra = get_long_020_prefetch (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u16 dst1 = x_get_word (rn1), dst2 = x_get_word (rn2);
+{uae_u32 newv = ((uae_u16)(dst1)) - ((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s16)(dst1)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u16)(dst2)) - ((uae_u16)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s16)(dst2)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, extra & 7))) > ((uae_u16)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	x_put_word (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	x_put_word (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);
+	m68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);
+	}
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e10_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200275; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200275: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e18_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200276; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200276: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e20_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_200277; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200277: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e28_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200278; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200278: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e30_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200279; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	x_put_byte (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}	regs.irc = get_word_020_prefetch (0);
+}}}l_200279: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e38_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200280; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200280: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e39_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200281; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_long_020_prefetch (4);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_020_prefetch (8);
+}}}	m68k_incpci (8);
+l_200281: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e50_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200282; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200282: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e58_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200283; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, dstreg) += 2;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200283: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e60_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_200284; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200284: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e68_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200285; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200285: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e70_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200286; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	x_put_word (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}	regs.irc = get_word_020_prefetch (0);
+}}}l_200286: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e78_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200287; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200287: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e79_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200288; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_long_020_prefetch (4);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_020_prefetch (8);
+}}}	m68k_incpci (8);
+l_200288: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e90_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_200289; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200289: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e98_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_200290; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, dstreg) += 4;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200290: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ea0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_200291; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200291: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ea8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_200292; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200292: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_200293; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	x_put_long (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}	regs.irc = get_word_020_prefetch (0);
+}}}l_200293: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_200294; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+l_200294: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_200295; }
+{{	uae_s16 extra = get_word_020_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_long_020_prefetch (4);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_020_prefetch (8);
+}}}	m68k_incpci (8);
+l_200295: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ed0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (4);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ed8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (4);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ee0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (4);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ee8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (6);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (0);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (6);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_020_prefetch (8);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS2.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0efc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 extra;
+	extra = get_long_020_prefetch (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u32 dst1 = x_get_long (rn1), dst2 = x_get_long (rn2);
+{uae_u32 newv = ((uae_u32)(dst1)) - ((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s32)(dst1)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u32)(dst2)) - ((uae_u32)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s32)(dst2)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, extra & 7))) > ((uae_u32)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	x_put_long (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	x_put_long (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = dst2;
+	m68k_dreg (regs, (extra >> 22) & 7) = dst1;
+	}
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1000_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1010_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1018_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1020_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1028_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1030_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1038_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1039_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (6);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1080_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1090_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1098_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10ba_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1100_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1110_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1118_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1120_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1128_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1130_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1138_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1139_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1140_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1150_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1158_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1160_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1168_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1170_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1178_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1179_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1180_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1190_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1198_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11ba_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (10);
+	x_put_byte (dsta, src);
+	m68k_incpci (10);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2000_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2008_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2010_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2018_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2020_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2028_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2030_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2038_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2039_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2040_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2048_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2050_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2058_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2060_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2068_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2070_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_020_prefetch (0);
+	m68k_areg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2078_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2079_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_020_prefetch (6);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_020_prefetch (0);
+	m68k_areg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_207c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	regs.irc = get_word_020_prefetch (6);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2080_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2088_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2090_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2098_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20ba_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2100_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2108_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2110_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2118_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2120_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2128_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2130_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2138_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2139_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2140_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2148_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2150_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2158_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2160_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2168_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2170_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2178_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2179_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2180_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2188_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2190_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2198_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_3
+/* MOVE.L -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21ba_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (10);
+	x_put_long (dsta, src);
+	m68k_incpci (10);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (10);
+	x_put_long (dsta, src);
+	m68k_incpci (10);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3000_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3008_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3010_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3018_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3020_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3028_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3030_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3038_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3039_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (6);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3040_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3048_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3050_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3058_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3060_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3068_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3070_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_020_prefetch (0);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3078_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3079_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_020_prefetch (6);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (6);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_020_prefetch (0);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_307c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3080_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3088_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3090_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3098_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30ba_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3100_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3108_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3110_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3118_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3120_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3128_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3130_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3138_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3139_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3140_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3148_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3150_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3158_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3160_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3168_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3170_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3178_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3179_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3180_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3188_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3190_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3198_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31ba_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (10);
+	x_put_word (dsta, src);
+	m68k_incpci (10);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (8);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4000_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4010_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4018_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4020_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4028_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4030_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4038_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4039_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4040_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4050_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4058_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4060_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4068_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4070_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (srca, newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4078_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4079_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4080_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4090_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4098_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (srca, newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40b8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40b9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_40c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_200632; }
+{{	MakeSR ();
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}}	m68k_incpci (2);
+l_200632: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_200633; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_200633: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_40d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_200634; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_200634: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{if (!regs.s) { Exception (8); goto l_200635; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_200635: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_200636; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	MakeSR ();
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_200636: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_200637; }
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (srca, regs.sr);
+}}}}l_200637: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_200638; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	MakeSR ();
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_200638: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_200639; }
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+	MakeSR ();
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (6);
+l_200639: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CHK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4100_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200640;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200640;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}l_200640: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4110_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200641;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200641;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200641: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (An)+,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4118_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200642;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200642;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200642: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L -(An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4120_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200643;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200643;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200643: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d16,An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4128_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200644;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200644;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200644: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d8,An,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4130_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200645;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200645;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}}l_200645: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (xxx).W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4138_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200646;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200646;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200646: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (xxx).L,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4139_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200647;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200647;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200647: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d16,PC),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200648;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200648;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200648: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d8,PC,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200649;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200649;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}}l_200649: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L #.L,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200650;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200650;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}l_200650: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4180_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200651;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200651;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}l_200651: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4190_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200652;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200652;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200652: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4198_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200653;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200653;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200653: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200654;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200654;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200654: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200655;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200655;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200655: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200656;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200656;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}}l_200656: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200657;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200657;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200657: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200658;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200658;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200658: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41ba_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200659;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200659;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200659: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200660;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200660;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}}l_200660: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_200661;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_200661;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}l_200661: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	regs.irc = get_word_020_prefetch (0);
+	m68k_areg (regs, dstreg) = (srca);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	regs.irc = get_word_020_prefetch (6);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	regs.irc = get_word_020_prefetch (0);
+	m68k_areg (regs, dstreg) = (srca);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4200_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4210_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4218_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4220_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4228_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4230_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, 0);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4238_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4239_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4240_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4250_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4258_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4260_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4268_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (srca, 0);
+}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4270_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (srca, 0);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4278_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (srca, 0);
+}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4279_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (srca, 0);
+}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4280_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4290_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4298_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (srca, 0);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_42b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (srca, 0);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_42b8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (srca, 0);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_42b9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (srca, 0);
+}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	MakeSR ();
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	MakeSR ();
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (srca, regs.sr & 0xff);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	MakeSR ();
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+	MakeSR ();
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* NEG.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4400_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_4
+/* NEG.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4410_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4418_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4420_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4428_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4430_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, dst);
+}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4438_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4439_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4440_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4450_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4458_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4460_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4468_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4470_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (srca, dst);
+}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4478_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4479_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4480_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4490_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4498_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (srca, dst);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44b8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44b9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_44c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (2);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_44d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B #.B */
+uae_u32 REGPARAM2 CPUFUNC(op_44fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4600_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4610_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4618_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4620_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4628_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4630_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4638_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4639_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4640_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4650_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4658_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4660_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4668_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4670_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (srca, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4678_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4679_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4680_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4690_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4698_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (srca, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46b8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46b9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_46c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_200760; }
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+l_200760: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200761; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (2);
+}}}}	m68k_incpci (2);
+l_200761: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_46d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200762; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (2);
+}}}}	m68k_incpci (2);
+l_200762: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_200763; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (2);
+}}}}	m68k_incpci (2);
+l_200763: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200764; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+l_200764: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200765; }
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (0);
+}}}}}l_200765: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200766; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+l_200766: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200767; }
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+l_200767: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200768; }
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+l_200768: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200769; }
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (0);
+}}}}}l_200769: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_46fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200770; }
+{{	uae_s16 src = get_word_020_prefetch (2);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+l_200770: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4800_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LINK.L An,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4808_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 8;  
+{{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 offs;
+	offs = get_long_020_prefetch (2);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (olda, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* NBCD.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4810_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4818_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4820_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4828_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4830_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, newv);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4838_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4839_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SWAP.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4840_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 34;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BKPTQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4848_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 99;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_020_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PEA.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4850_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4868_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4870_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, srca);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4878_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4879_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_487a_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_487b_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, srca);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* EXT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4880_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u16 dst = (uae_s16)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4890_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 6;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	int type = get_cpu_model () >= 68020;
+	while (amask) {
+		srca -= 2;
+		if (!type || movem_index2[amask] != dstreg)
+			x_put_word (srca, m68k_areg (regs, movem_index2[amask]));
+		else
+			x_put_word (srca, m68k_areg (regs, movem_index2[amask]) - 2);
+		amask = movem_next[amask];
+	}
+	while (dmask) { srca -= 2; x_put_word (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48b0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_020_prefetch (0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48b8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48b9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+{	uaecptr srca;
+	srca = get_long_020_prefetch (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_020_prefetch (8);
+}}}	m68k_incpci (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EXT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_48c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48d0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 10; 
+{	uae_u16 mask = get_word_020_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	int type = get_cpu_model () >= 68020;
+	while (amask) {
+		srca -= 4;
+		if (!type || movem_index2[amask] != dstreg)
+			x_put_long (srca, m68k_areg (regs, movem_index2[amask]));
+		else
+			x_put_long (srca, m68k_areg (regs, movem_index2[amask]) - 4);
+		amask = movem_next[amask];
+	}
+	while (dmask) { srca -= 4; x_put_long (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48f0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_020_prefetch (0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+{	uaecptr srca;
+	srca = get_long_020_prefetch (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_020_prefetch (8);
+}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXT.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_49c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a00_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a10_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a18_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a20_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a28_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a30_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a38_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a39_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3a_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3b_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B #.B */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3c_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a40_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a48_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a50_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a58_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a60_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a68_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a70_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a78_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a79_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7a_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7b_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7c_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a80_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.L An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a88_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a90_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a98_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4aba_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4abb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4abc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TAS.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4ac0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((src) & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, src);
+}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4af0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, src);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4af8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, src);
+}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4af9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, src);
+}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MULL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c00_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_200847;
+	regs.irc = get_word_020_prefetch (0);
+}}}l_200847: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c10_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_200848;
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200848: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c18_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_200849;
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200849: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c20_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_200850;
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200850: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c28_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_200851;
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200851: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c30_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_200852;
+	regs.irc = get_word_020_prefetch (0);
+}}}}}l_200852: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c38_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_200853;
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200853: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c39_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_200854;
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200854: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_200855;
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200855: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_200856;
+	regs.irc = get_word_020_prefetch (0);
+}}}}}l_200856: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3c_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uae_s32 dst;
+	dst = get_long_020_prefetch (4);
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_200857;
+	regs.irc = get_word_020_prefetch (0);
+}}}l_200857: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c40_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_200858;
+	regs.irc = get_word_020_prefetch (0);
+}}}l_200858: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c50_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_200859;
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200859: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c58_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_200860;
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200860: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c60_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_200861;
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200861: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c68_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_200862;
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200862: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c70_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_200863;
+	regs.irc = get_word_020_prefetch (0);
+}}}}}l_200863: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c78_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_200864;
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200864: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c79_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_200865;
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200865: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_200866;
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_200866: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_200867;
+	regs.irc = get_word_020_prefetch (0);
+}}}}}l_200867: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7c_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uae_s32 dst;
+	dst = get_long_020_prefetch (4);
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_200868;
+	regs.irc = get_word_020_prefetch (0);
+}}}l_200868: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVMEL.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4c90_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4c98_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ca8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_long_020_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_020_prefetch (8);
+}}}	m68k_incpci (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cba_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cbb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_020_prefetch (4);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ce8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_long_020_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_020_prefetch (8);
+}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_020_prefetch (6);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* TRAPQ.L # */
+uae_u32 REGPARAM2 CPUFUNC(op_4e40_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 15);
+	OpcodeFamily = 39;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+	m68k_incpci (2);
+	Exception (src + 32);
+}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* LINK.W An,#.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e50_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 8;  
+{{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (olda, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* UNLK.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e58_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 48;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	m68k_areg (regs, 7) = src;
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7);
+{	uae_s32 old = x_get_long (olda);
+	m68k_areg (regs, 7) += 4;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, srcreg) = (old);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVR2USP.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e60_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 40;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_200888; }
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	regs.usp = src;
+	regs.irc = get_word_020_prefetch (2);
+}}}	m68k_incpci (2);
+l_200888: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVUSP2R.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e68_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 41;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_200889; }
+{{	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, srcreg) = (regs.usp);
+}}}	m68k_incpci (2);
+l_200889: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RESET.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e70_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 42;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_200890; }
+{	cpureset ();
+	m68k_incpci (2);
+	regs.irc = get_word_020_prefetch (0);
+}}l_200890: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOP.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e71_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 43;
+	CurrentInstrCycles = 4;  
+{	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* STOP.L #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e72_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 44;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200892; }
+{{	uae_s16 src = get_word_020_prefetch (2);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_setstopped ();
+	m68k_incpci (4);
+}}}l_200892: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RTE.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e73_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 45;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_200893; }
+{	uae_u16 newsr; uae_u32 newpc;
+	for (;;) {
+		uaecptr a = m68k_areg (regs, 7);
+		uae_u16 sr = x_get_word (a);
+		uae_u32 pc = x_get_long (a + 2);
+		uae_u16 format = x_get_word (a + 2 + 4);
+		int frame = format >> 12;
+		int offset = 8;
+		newsr = sr; newpc = pc;
+		if (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }
+		else if (frame == 0x1) { m68k_areg (regs, 7) += offset; }
+		else if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }
+		else if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }
+		else if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }
+		else if (frame == 0x7) { m68k_areg (regs, 7) += offset + 52; break; }
+		else if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }
+		else if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }
+		else if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }
+		else { m68k_areg (regs, 7) += offset; Exception (14); goto l_200893; }
+		regs.sr = newsr;
+	MakeFromSR();
+}
+	regs.sr = newsr;
+	MakeFromSR();
+	if (newpc & 1) {
+		exception3i (0x4E73, newpc);
+		goto l_200893;
+	}
+	m68k_setpci (newpc);
+	fill_prefetch_020 ();
+}}l_200893: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RTD.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e74_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 46;
+	CurrentInstrCycles = 8;  
+{{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = x_get_long (pca);
+	m68k_areg (regs, 7) += 4;
+{	uae_s16 offs = get_word_020_prefetch (2);
+	m68k_areg (regs, 7) += offs;
+	if (pc & 1) {
+		exception3i (0x4E74, pc);
+		goto l_200894;
+	}
+	m68k_setpci (pc);
+	fill_prefetch_020 ();
+}}}}l_200894: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* RTS.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e75_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 49;
+	CurrentInstrCycles = 8;  
+{	uaecptr pc = m68k_getpci ();
+	m68k_do_rtsi ();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (pc);
+		exception3i (0x4E75, faultpc);
+		goto l_200895;
+	}
+	fill_prefetch_020 ();
+}l_200895: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TRAPV.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e76_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 50;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	if (GET_VFLG ()) {
+		Exception (7);
+		goto l_200896;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}l_200896: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RTR.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e77_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 51;
+	CurrentInstrCycles = 12; 
+{	uaecptr oldpc = m68k_getpci ();
+	MakeSR ();
+{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+{	uae_s16 sr = x_get_word (sra);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = x_get_long (pca);
+	m68k_areg (regs, 7) += 4;
+	regs.sr &= 0xFF00; sr &= 0xFF;
+	regs.sr |= sr;
+	m68k_setpci (pc);
+	MakeFromSR();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (oldpc);
+		exception3i (0x4E77, faultpc);
+		goto l_200897;
+	}
+	fill_prefetch_020 ();
+}}}}}l_200897: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEC2.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7a_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 82;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200898; }
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_movec2(src & 0xFFF, regp)) goto l_200898;
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+l_200898: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE2C.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7b_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 83;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_200899; }
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_move2c(src & 0xFFF, regp)) goto l_200899;
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+l_200899: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* JSR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4e90_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr oldpc = m68k_getpci () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_200900;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_020 ();
+}}}l_200900: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ea8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_200901;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_020 ();
+}}}l_200901: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_200902;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_020 ();
+}}}}l_200902: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_200903;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_020 ();
+}}}l_200903: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uaecptr oldpc = m68k_getpci () + 6;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_200904;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_020 ();
+}}}l_200904: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eba_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_200905;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_020 ();
+}}}l_200905: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ebb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_200906;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_020 ();
+}}}}l_200906: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ed0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_200907;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_020 ();
+}}l_200907: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ee8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_200908;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_020 ();
+}}l_200908: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_200909;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_020 ();
+}}}l_200909: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_200910;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_020 ();
+}}l_200910: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_200911;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_020 ();
+}}l_200911: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_200912;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_020 ();
+}}l_200912: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_200913;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_020 ();
+}}}l_200913: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5000_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5010_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5018_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5020_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5028_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5030_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5038_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5039_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5040_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5048_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5050_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5058_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5060_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5068_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5070_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5078_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5079_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5080_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5088_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5090_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5098_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_5
+/* ADDQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_50b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_50b8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_50b9_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (0)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_200941;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_200941: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (0)) { Exception (7); goto l_200949; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_200949: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (0)) { Exception (7); goto l_200950; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_200950: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (0)) { Exception (7); goto l_200951; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_200951: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* SUBQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5100_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5110_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5118_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5120_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5128_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5130_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5138_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5139_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5140_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5148_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5150_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5158_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5160_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5168_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5170_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5178_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5179_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5180_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5188_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5190_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5198_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_51b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_51b8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_51b9_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (1)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_200979;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_200979: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (1)) { Exception (7); goto l_200987; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_200987: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (1)) { Exception (7); goto l_200988; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_200988: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (1)) { Exception (7); goto l_200989; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_200989: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (2)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_200991;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_200991: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (2)) { Exception (7); goto l_200999; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_200999: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (2)) { Exception (7); goto l_201000; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_201000: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (2)) { Exception (7); goto l_201001; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_201001: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (3)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_201003;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_201003: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (3)) { Exception (7); goto l_201011; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_201011: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (3)) { Exception (7); goto l_201012; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_201012: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (3)) { Exception (7); goto l_201013; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_201013: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (4)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_201015;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_201015: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (4)) { Exception (7); goto l_201023; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_201023: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (4)) { Exception (7); goto l_201024; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_201024: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (4)) { Exception (7); goto l_201025; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_201025: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (5)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_201027;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_201027: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (5)) { Exception (7); goto l_201035; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_201035: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (5)) { Exception (7); goto l_201036; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_201036: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (5)) { Exception (7); goto l_201037; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_201037: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (6)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_201039;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_201039: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (6)) { Exception (7); goto l_201047; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_201047: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (6)) { Exception (7); goto l_201048; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_201048: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (6)) { Exception (7); goto l_201049; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_201049: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (7)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_201051;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_201051: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (7)) { Exception (7); goto l_201059; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_201059: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (7)) { Exception (7); goto l_201060; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_201060: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (7)) { Exception (7); goto l_201061; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_201061: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (8)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_201063;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_201063: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (8)) { Exception (7); goto l_201071; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_201071: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (8)) { Exception (7); goto l_201072; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_201072: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (8)) { Exception (7); goto l_201073; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_201073: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (9)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_201075;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_201075: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (9)) { Exception (7); goto l_201083; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_201083: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (9)) { Exception (7); goto l_201084; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_201084: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (9)) { Exception (7); goto l_201085; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_201085: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (10)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_201087;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_201087: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (10)) { Exception (7); goto l_201095; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_201095: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (10)) { Exception (7); goto l_201096; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_201096: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (10)) { Exception (7); goto l_201097; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_201097: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (11)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_201099;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_201099: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (11)) { Exception (7); goto l_201107; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_201107: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (11)) { Exception (7); goto l_201108; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_201108: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (11)) { Exception (7); goto l_201109; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_201109: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (12)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_201111;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_201111: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (12)) { Exception (7); goto l_201119; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_201119: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (12)) { Exception (7); goto l_201120; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_201120: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (12)) { Exception (7); goto l_201121; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_201121: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (13)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_201123;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_201123: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (13)) { Exception (7); goto l_201131; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_201131: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (13)) { Exception (7); goto l_201132; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_201132: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (13)) { Exception (7); goto l_201133; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_201133: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (14)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_201135;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_201135: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (14)) { Exception (7); goto l_201143; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_201143: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (14)) { Exception (7); goto l_201144; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_201144: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (14)) { Exception (7); goto l_201145; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_201145: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_020_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (15)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_201147;
+			}
+	fill_prefetch_020 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_201147: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffa_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_020_prefetch (2);
+	if (cctrue (15)) { Exception (7); goto l_201155; }
+	regs.irc = get_word_020_prefetch (4);
+}}	m68k_incpci (4);
+l_201155: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffb_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (2);
+	if (cctrue (15)) { Exception (7); goto l_201156; }
+	regs.irc = get_word_020_prefetch (6);
+}}	m68k_incpci (6);
+l_201156: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffc_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (15)) { Exception (7); goto l_201157; }
+	regs.irc = get_word_020_prefetch (2);
+}	m68k_incpci (2);
+l_201157: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Bcc.W #.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6000_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201158;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201158: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6001_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201159;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201159: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_60ff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201160;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201160: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_6100_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_s16 src = get_word_020_prefetch (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_201161;
+	}
+	m68k_do_bsri (m68k_getpci () + 4, s);
+	fill_prefetch_020 ();
+}}l_201161: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSRQ.B # */
+uae_u32 REGPARAM2 CPUFUNC(op_6101_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_u32 src = srcreg;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_201162;
+	}
+	m68k_do_bsri (m68k_getpci () + 2, s);
+	fill_prefetch_020 ();
+}}l_201162: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSR.L #.L */
+uae_u32 REGPARAM2 CPUFUNC(op_61ff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_201163;
+	}
+	m68k_do_bsri (m68k_getpci () + 6, s);
+	fill_prefetch_020 ();
+}}l_201163: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6200_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201164;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201164: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6201_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201165;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201165: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_62ff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201166;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201166: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6300_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201167;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201167: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6301_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201168;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201168: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_6
+/* Bcc.L #.L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_63ff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201169;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201169: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6400_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201170;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201170: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6401_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201171;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201171: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_64ff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201172;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201172: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6500_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201173;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201173: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6501_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201174;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201174: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_65ff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201175;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201175: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6600_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201176;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201176: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6601_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201177;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201177: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_66ff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201178;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201178: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6700_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201179;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201179: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6701_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201180;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201180: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_67ff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201181;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201181: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6800_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201182;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201182: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6801_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201183;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201183: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_68ff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201184;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201184: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6900_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201185;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201185: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6901_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201186;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201186: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_69ff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201187;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201187: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a00_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201188;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201188: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a01_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201189;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201189: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6aff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201190;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201190: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b00_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201191;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201191: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b01_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201192;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201192: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6bff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201193;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201193: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c00_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201194;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201194: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c01_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201195;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201195: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6cff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201196;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201196: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d00_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201197;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201197: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d01_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201198;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201198: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6dff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201199;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201199: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e00_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201200;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201200: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e01_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201201;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201201: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6eff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201202;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201202: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f00_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201203;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_201203: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f01_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201204;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_201204: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6fff_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_201205;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_201205: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_7000_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8000_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8010_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8018_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8020_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8028_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8030_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8038_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8039_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8040_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8050_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8058_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8060_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8068_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8070_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8078_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8079_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8080_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8090_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8098_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80ba_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 110;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_201240;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}l_201240: ;
+return 110 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_201241;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_201241: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_201242;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_201242: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_201243;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_201243: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_201244;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_201244: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_201245;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}}l_201245: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_201246;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_201246: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_201247;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (6);
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_201247: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_201248;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_201248: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_201249;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}}l_201249: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 114;
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_201250;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}l_201250: ;
+return 114 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8100_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8108_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8110_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8118_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8120_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8128_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8130_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8138_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8139_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PACK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8140_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val = m68k_dreg (regs, srcreg) + get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);
+	regs.irc = get_word_020_prefetch (4);
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PACK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8148_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val;
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (val | ((uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff) << 8)) + get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) -= areg_byteinc[dstreg];
+	x_put_byte (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));
+	regs.irc = get_word_020_prefetch (4);
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* OR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8150_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8158_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8160_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8168_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8170_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8178_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8179_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* UNPK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8180_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val = m68k_dreg (regs, srcreg);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);
+	regs.irc = get_word_020_prefetch (4);
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* UNPK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8188_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val;
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];
+	x_put_byte (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);
+	x_put_byte (m68k_areg (regs, dstreg), val >> 8);
+	regs.irc = get_word_020_prefetch (4);
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* OR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8190_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8198_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_81b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_81b8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_81b9_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 142;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_201278;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	regs.irc = get_word_020_prefetch (0);
+}}}l_201278: ;
+return 142 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_201279;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_201279: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_201280;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_201280: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_201281;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_201281: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_201282;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_201282: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_201283;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}}l_201283: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_201284;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_201284: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_201285;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (6);
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_201285: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_201286;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	regs.irc = get_word_020_prefetch (0);
+}}}}l_201286: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_201287;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}}}}l_201287: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 146;
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_201288;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	regs.irc = get_word_020_prefetch (0);
+}}}l_201288: ;
+return 146 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9000_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9010_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9018_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9020_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9028_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9030_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9038_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9039_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9040_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9048_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9050_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9058_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9060_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9068_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9070_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9078_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9079_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9080_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9088_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9090_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9098_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90ba_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (6);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9100_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9108_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9110_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9118_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9120_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9128_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9130_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9138_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9139_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9140_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9148_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9150_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9158_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9160_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9168_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9170_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9178_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9179_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9180_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9188_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 26 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9190_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9198_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_91b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_91b8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_91b9_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (6);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_020_prefetch (6);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b000_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b010_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b018_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b020_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b028_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b030_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b038_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b039_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b040_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b048_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b050_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b058_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b060_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b068_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b070_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b078_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b079_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b080_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b088_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b090_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b098_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_7
+/* CMP.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0ba_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b100_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b108_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b110_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b118_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b120_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b128_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b130_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b138_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b139_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b140_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b148_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b150_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b158_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b160_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b168_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b170_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b178_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b179_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b180_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b188_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b190_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b198_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b9_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c000_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c010_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c018_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c020_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c028_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c030_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c038_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c039_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c040_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c050_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c058_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c060_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c068_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c070_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c078_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c079_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c080_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c090_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c098_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0ba_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 58; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}return 58 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 40; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return 40 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (6);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 62; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}return 62 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c100_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c108_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c110_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c118_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c120_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c128_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c130_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c138_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c139_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c140_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c148_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c150_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c158_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c160_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c168_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c170_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c178_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c179_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c188_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c190_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c198_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b9_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 58; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 58 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 40; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 40 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 62; 
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d000_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d010_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d018_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d020_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d028_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d030_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d038_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d039_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d040_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d048_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d050_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d058_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d060_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d068_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d070_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d078_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d079_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07c_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d080_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d088_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d090_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d098_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0ba_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (6);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_020_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d100_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d108_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d110_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d118_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d120_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d128_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d130_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d138_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d139_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d140_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d148_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d150_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d158_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d160_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d168_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d170_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d178_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d179_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d180_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d188_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 26 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d190_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d198_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b9_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f9_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (6);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fc_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_020_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_020_prefetch (6);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e000_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e008_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e010_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e018_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e020_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e028_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e030_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e038_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e040_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_8
+/* LSRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e048_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e050_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e058_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e060_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e068_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e070_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e078_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e080_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e088_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e090_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e098_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e100_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e108_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e110_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e118_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e120_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e128_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e130_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e138_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e140_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e148_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e150_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e158_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e160_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e168_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e170_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e178_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e180_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e188_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e190_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e198_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.irc = get_word_020_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e8_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.irc = get_word_020_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.irc = get_word_020_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.irc = get_word_020_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BFTST.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8c0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8d0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8e8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_020_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9c0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9d0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9e8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9fa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9fb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eac0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ead0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eae8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebc0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebd0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebe8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebfa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebfb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecc0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecd0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ece8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edc0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edd0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ede8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_020_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edfa_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edfb_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eec0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eed0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eee8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efc0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efd0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efe8_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff0_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff8_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff9_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_020_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_020_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f200_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_201788;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201788: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f208_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_201789;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201789: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f210_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_201790;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201790: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f218_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_201791;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201791: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f220_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_201792;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201792: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f228_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_201793;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201793: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f230_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_201794;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201794: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f238_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_201795;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201795: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f239_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_201796;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201796: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23a_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_201797;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201797: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23b_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_201798;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201798: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23c_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_201799;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201799: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f240_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_201800;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201800: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FDBcc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f248_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 105;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_dbcc (opcode, extra);
+	if (regs.fp_exception) goto l_201801;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_201801;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201801: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f250_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_201802;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201802: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f258_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_201803;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201803: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f260_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_201804;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201804: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f268_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_201805;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201805: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f270_20)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_201806;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201806: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f278_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_201807;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201807: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f279_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_201808;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201808: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27a_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 12; 
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_word_020_prefetch (2);
+{	uae_s16 dummy = get_word_020_prefetch (4);
+	m68k_incpci (6);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_201809;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201809: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27b_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 16; 
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_word_020_prefetch (2);
+{	uae_s32 dummy;
+	dummy = get_long_020_prefetch (4);
+	m68k_incpci (8);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_201810;
+	regs.irc = get_word_020_prefetch (0);
+}
+#endif
+}l_201810: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L  */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27c_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_word_020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_201811;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}l_201811: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FBccQ.L #,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f280_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s16 extra = get_word_020_prefetch (0);
+	m68k_incpci (2);
+	fpuop_bcc (opcode, pc,extra);
+	if (regs.fp_exception) goto l_201812;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_201812;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}
+#endif
+}l_201812: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FBccQ.L #,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f2c0_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+	CurrentInstrCycles = 12; 
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s32 extra;
+	extra = get_long_020_prefetch (0);
+	m68k_incpci (4);
+	fpuop_bcc (opcode, pc,extra);
+	if (regs.fp_exception) goto l_201813;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_201813;
+	}
+	regs.irc = get_word_020_prefetch (0);
+}}
+#endif
+}l_201813: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f310_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_201814; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_201814;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}}l_201814: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f320_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_201815; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_201815;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}}l_201815: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f328_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_201816; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_201816;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}}l_201816: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f330_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_201817; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_201817;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}}l_201817: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f338_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_201818; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_201818;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}}l_201818: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f339_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_201819; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_201819;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}}l_201819: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f350_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_201820; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_201820;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}}l_201820: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f358_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_201821; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_201821;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}}l_201821: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f368_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_201822; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_201822;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}}l_201822: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f370_20)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_201823; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_201823;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}}l_201823: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f378_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_201824; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_201824;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}}l_201824: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f379_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_201825; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_201825;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}}l_201825: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f37a_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_201826; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_201826;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}}l_201826: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f37b_20)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_201827; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_201827;
+	regs.irc = get_word_020_prefetch (0);
+
+#endif
+}}l_201827: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
diff --git a/src/cpu/cpuemu_21.c b/src/cpu/cpuemu_21.c
new file mode 100644
index 0000000..09f4898
--- /dev/null
+++ b/src/cpu/cpuemu_21.c
@@ -0,0 +1,46609 @@
+#include "main.h"
+#include "sysdeps.h"
+#include "hatari-glue.h"
+#include "maccess.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "cputbl.h"
+#define CPUFUNC(x) x##_ff
+#define SET_CFLG_ALWAYS(x) SET_CFLG(x)
+#define SET_NFLG_ALWAYS(x) SET_NFLG(x)
+#ifdef NOFLAGS
+#include "noflags.h"
+#endif
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+/* OR.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0000_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0010_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0018_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0020_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0028_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0030_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* OR.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0038_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0039_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* ORSR.B #.W */
+void REGPARAM2 CPUFUNC(op_003c_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+{	MakeSR ();
+{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	src &= 0xFF;
+	regs.sr |= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0040_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0050_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0058_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0060_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0068_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0070_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* OR.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0078_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0079_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* ORSR.W #.W */
+void REGPARAM2 CPUFUNC(op_007c_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+{if (!regs.s) { Exception (8); goto l_210018; }
+{	MakeSR ();
+{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	regs.sr |= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210018: ;
+return;
+}
+
+/* OR.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0080_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4+2=6,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0090_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0098_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_00a0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_00a8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* OR.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_00b0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:8,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* OR.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_00b8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* OR.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_00b9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{	/* ea H:5,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 5 * cpucycleunit)
+		regs.ce020memcycles = 5 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return;
+}
+
+/* CHK2.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00d0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210027; }
+}
+	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210027: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00e8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210028; }
+}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210028: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00f0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210029; }
+}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210029: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210030; }
+}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210030: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210031; }
+}
+	regs.irc = get_word_ce020_prefetch (8);
+}}}	m68k_incpci (8);
+l_210031: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210032; }
+}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210032: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce020 (tmppc, 0);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210033; }
+}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210033: ;
+return;
+}
+
+#endif
+/* BTST.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_0100_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVPMR.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_0108_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	/* OP zero */
+	uae_u16 val;
+	MovepByteNbr=1; val = ((x_get_byte (memp) & 0xff) << 8);
+	MovepByteNbr=2; val += (x_get_byte (memp + 2) & 0xff);
+	MovepByteNbr=0;
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_0110_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BTST.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_0118_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BTST.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_0120_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BTST.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0128_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0130_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}}return;
+}
+
+/* BTST.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0138_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0139_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BTST.B Dn,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_013a_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 2;
+	dsta += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B Dn,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_013b_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce020 (tmppc, 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}}return;
+}
+
+/* BTST.B Dn,#.B */
+void REGPARAM2 CPUFUNC(op_013c_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = (uae_u8)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_0140_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVPMR.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_0148_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	/* OP zero */
+	uae_u32 val;
+	MovepByteNbr=1; val = ((x_get_byte (memp) & 0xff) << 24);
+	MovepByteNbr=2; val += ((x_get_byte (memp + 2) & 0xff) << 16);
+	MovepByteNbr=3; val += ((x_get_byte (memp + 4) & 0xff) << 8);
+	MovepByteNbr=4; val += (x_get_byte (memp + 6) & 0xff);
+	MovepByteNbr=0;
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_0150_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCHG.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_0158_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCHG.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_0160_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCHG.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0168_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0170_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BCHG.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0178_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0179_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCLR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_0180_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVPRM.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0188_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* OP zero */
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	MovepByteNbr=1; 	x_put_byte (memp, src >> 8);
+	MovepByteNbr=2; 	x_put_byte (memp + 2, src);
+	MovepByteNbr=0;
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_0190_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCLR.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_0198_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCLR.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_01a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCLR.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_01a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_01b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BCLR.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_01b8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_01b9_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BSET.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_01c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVPRM.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_01c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* OP zero */
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	MovepByteNbr=1; 	x_put_byte (memp, src >> 24);
+	MovepByteNbr=2; 	x_put_byte (memp + 2, src >> 16);
+	MovepByteNbr=3; 	x_put_byte (memp + 4, src >> 8);
+	MovepByteNbr=4; 	x_put_byte (memp + 6, src);
+	MovepByteNbr=0;
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_01d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BSET.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_01d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BSET.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_01e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BSET.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_01e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_01f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BSET.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_01f8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_01f9_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0200_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0210_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0218_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0220_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0228_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0230_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* AND.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0238_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0239_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* ANDSR.B #.W */
+void REGPARAM2 CPUFUNC(op_023c_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+{	MakeSR ();
+{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	src |= 0xFF00;
+	regs.sr &= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0240_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0250_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0258_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0260_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0268_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0270_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* AND.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0278_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0279_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* ANDSR.W #.W */
+void REGPARAM2 CPUFUNC(op_027c_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+{if (!regs.s) { Exception (8); goto l_210090; }
+{	MakeSR ();
+{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	regs.sr &= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210090: ;
+return;
+}
+
+/* AND.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0280_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4+2=6,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0290_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0298_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_02a0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_02a8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* AND.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_02b0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:8,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* AND.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_02b8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* AND.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_02b9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{	/* ea H:5,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 5 * cpucycleunit)
+		regs.ce020memcycles = 5 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return;
+}
+
+/* CHK2.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02d0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210099; }
+}
+	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210099: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02e8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210100; }
+}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210100: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02f0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210101; }
+}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210101: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210102; }
+}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210102: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210103; }
+}
+	regs.irc = get_word_ce020_prefetch (8);
+}}}	m68k_incpci (8);
+l_210103: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210104; }
+}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210104: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce020 (tmppc, 0);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210105; }
+}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210105: ;
+return;
+}
+
+#endif
+/* SUB.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0400_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0410_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0418_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0420_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0428_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0430_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0438_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0439_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* SUB.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0440_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0450_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0458_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0460_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0468_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0470_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0478_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0479_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* SUB.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0480_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4+2=6,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0490_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0498_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_04a0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_04a8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* SUB.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_04b0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:8,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_04b8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* SUB.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_04b9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{	/* ea H:5,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 5 * cpucycleunit)
+		regs.ce020memcycles = 5 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (10);
+return;
+}
+
+/* CHK2.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04d0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210130; }
+}
+	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210130: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04e8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210131; }
+}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210131: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04f0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210132; }
+}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210132: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210133; }
+}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210133: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210134; }
+}
+	regs.irc = get_word_ce020_prefetch (8);
+}}}	m68k_incpci (8);
+l_210134: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210135; }
+}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210135: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce020 (tmppc, 0);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_210136; }
+}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210136: ;
+return;
+}
+
+#endif
+/* ADD.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0600_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0610_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0618_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0620_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0628_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0630_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0638_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0639_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* ADD.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0640_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0650_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0658_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0660_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0668_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0670_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0678_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0679_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* ADD.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0680_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4+2=6,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0690_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0698_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_06a0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_06a8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* ADD.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_06b0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:8,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_06b8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* ADD.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_06b9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{	/* ea H:5,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 5 * cpucycleunit)
+		regs.ce020memcycles = 5 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (10);
+return;
+}
+
+/* RTM.L Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce020_prefetch (0);
+}return;
+}
+
+#endif
+/* RTM.L An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce020_prefetch (0);
+}return;
+}
+
+#endif
+/* CALLM.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce020_prefetch (0);
+}return;
+}
+
+#endif
+/* CALLM.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce020_prefetch (0);
+}return;
+}
+
+#endif
+/* CALLM.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce020_prefetch (0);
+}return;
+}
+
+#endif
+/* CALLM.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce020_prefetch (0);
+}return;
+}
+
+#endif
+/* CALLM.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce020_prefetch (0);
+}return;
+}
+
+#endif
+/* CALLM.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce020_prefetch (0);
+}return;
+}
+
+#endif
+/* CALLM.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce020_prefetch (0);
+}return;
+}
+
+#endif
+/* BTST.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0800_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* No EA */
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0810_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0818_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0820_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0828_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BTST.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0830_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}}return;
+}
+
+/* BTST.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0838_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BTST.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0839_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* BTST.B #.W,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_083a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BTST.B #.W,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_083b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}}return;
+}
+
+/* BCHG.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0840_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* No EA */
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0850_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0858_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0860_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0868_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCHG.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0870_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BCHG.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0878_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCHG.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0879_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* BCLR.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0880_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* No EA */
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0890_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0898_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_08a0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_08a8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCLR.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_08b0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BCLR.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_08b8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCLR.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_08b9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* BSET.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_08c0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* No EA */
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_08d0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_08d8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_08e0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_08e8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BSET.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_08f0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BSET.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_08f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BSET.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_08f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EOR.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0a00_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0a10_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0a18_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0a20_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0a28_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0a30_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* EOR.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0a38_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0a39_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EORSR.B #.W */
+void REGPARAM2 CPUFUNC(op_0a3c_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+{	MakeSR ();
+{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	src &= 0xFF;
+	regs.sr ^= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0a40_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0a50_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0a58_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0a60_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0a68_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0a70_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* EOR.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0a78_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0a79_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EORSR.W #.W */
+void REGPARAM2 CPUFUNC(op_0a7c_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+{if (!regs.s) { Exception (8); goto l_210221; }
+{	MakeSR ();
+{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	regs.sr ^= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210221: ;
+return;
+}
+
+/* EOR.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0a80_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:4+2=6,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0a90_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:1,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0a98_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:4,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_0aa0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0aa8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:4,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EOR.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0ab0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:8,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* EOR.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0ab8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EOR.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0ab9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{	/* ea H:5,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 5 * cpucycleunit)
+		regs.ce020memcycles = 5 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return;
+}
+
+/* CAS.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ad0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (4);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ad8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (4);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ae0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (4);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ae8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (6);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+#endif
+
+#ifdef PART_2
+/* CAS.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0af0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (0);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (0);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}}return;
+}
+
+#endif
+/* CAS.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0af8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (6);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CAS.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0af9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (8);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (8);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* CMP.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0c00_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0c10_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0c18_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0c20_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0c28_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0c30_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0c38_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0c39_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* CMP.B #.B,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0c3a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CMP.B #.B,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0c3b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+#endif
+/* CMP.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0c40_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0c50_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0c58_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0c60_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0c68_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0c70_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0c78_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0c79_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* CMP.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0c7a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CMP.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0c7b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+#endif
+/* CMP.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0c80_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4+2=6,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0c90_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0c98_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_0ca0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0ca8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* CMP.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0cb0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:8,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0cb8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* CMP.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0cb9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{	/* ea H:5,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 5 * cpucycleunit)
+		regs.ce020memcycles = 5 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (10);
+return;
+}
+
+/* CMP.L #.L,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cba_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 6;
+	dsta += (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* CMP.L #.L,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cbb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+{	/* ea H:8,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (6);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+#endif
+/* CAS.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cd0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (4);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cd8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (4);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ce0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (4);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ce8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (6);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CAS.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cf0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (0);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (0);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}}return;
+}
+
+#endif
+/* CAS.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cf8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (6);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CAS.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cf9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (8);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (8);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* CAS2.W #.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cfc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+{{	uae_s32 extra;
+	extra = get_long_ce020_prefetch (2);
+	/* OP zero */
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u16 dst1 = x_get_word (rn1), dst2 = x_get_word (rn2);
+{uae_u32 newv = ((uae_u16)(dst1)) - ((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s16)(dst1)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u16)(dst2)) - ((uae_u16)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s16)(dst2)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, extra & 7))) > ((uae_u16)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	x_put_word (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	x_put_word (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);
+	m68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);
+	}
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* MOVES.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e10_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210275; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = x_get_byte (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210275: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e18_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210276; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	/* OP zero */
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210276: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e20_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210277; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	/* OP zero */
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, dstreg) = srca;
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210277: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e28_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210278; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 src = x_get_byte (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210278: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e30_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210279; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+	x_put_byte (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 1);
+{	uae_s8 src = x_get_byte (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}	regs.irc = get_word_ce020_prefetch (0);
+}}}l_210279: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e38_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210280; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s8 src = x_get_byte (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210280: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e39_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210281; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	/* OP zero */
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_long_ce020_prefetch (4);
+{	uae_s8 src = x_get_byte (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (8);
+}}}	m68k_incpci (8);
+l_210281: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e50_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210282; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210282: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e58_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210283; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	/* OP zero */
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, dstreg) += 2;
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210283: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e60_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210284; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	/* OP zero */
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, dstreg) = srca;
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210284: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e68_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210285; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210285: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e70_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210286; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+	x_put_word (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 1);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}	regs.irc = get_word_ce020_prefetch (0);
+}}}l_210286: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e78_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210287; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210287: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e79_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210288; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	/* OP zero */
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_long_ce020_prefetch (4);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (8);
+}}}	m68k_incpci (8);
+l_210288: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e90_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210289; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210289: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e98_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210290; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	/* OP zero */
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, dstreg) += 4;
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210290: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ea0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210291; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	/* OP zero */
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, dstreg) = srca;
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+l_210291: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ea8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210292; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210292: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0eb0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210293; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+	x_put_long (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 1);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}	regs.irc = get_word_ce020_prefetch (0);
+}}}l_210293: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0eb8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210294; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+l_210294: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0eb9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_210295; }
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	/* OP zero */
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_long_ce020_prefetch (4);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_ce020_prefetch (8);
+}}}	m68k_incpci (8);
+l_210295: ;
+return;
+}
+
+#endif
+/* CAS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ed0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (4);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (4);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ed8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (4);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (4);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ee0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (4);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (4);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ee8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (6);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (6);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CAS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ef0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (0);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (0);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}}return;
+}
+
+#endif
+/* CAS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ef8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (6);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (6);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CAS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ef9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce020_prefetch (8);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce020_prefetch (8);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* CAS2.L #.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0efc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+{{	uae_s32 extra;
+	extra = get_long_ce020_prefetch (2);
+	/* OP zero */
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u32 dst1 = x_get_long (rn1), dst2 = x_get_long (rn2);
+{uae_u32 newv = ((uae_u32)(dst1)) - ((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s32)(dst1)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u32)(dst2)) - ((uae_u32)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s32)(dst2)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, extra & 7))) > ((uae_u32)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	x_put_long (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	x_put_long (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = dst2;
+	m68k_dreg (regs, (extra >> 22) & 7) = dst1;
+	}
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* MOVE.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_1000_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_1010_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_1018_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_1020_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_1028_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_1030_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_1038_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_1039_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_103a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_103b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* MOVE.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_103c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_1080_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.B (An),(An) */
+void REGPARAM2 CPUFUNC(op_1090_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(An) */
+void REGPARAM2 CPUFUNC(op_1098_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B -(An),(An) */
+void REGPARAM2 CPUFUNC(op_10a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(An) */
+void REGPARAM2 CPUFUNC(op_10a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_10b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(An) */
+void REGPARAM2 CPUFUNC(op_10b8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(An) */
+void REGPARAM2 CPUFUNC(op_10b9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(An) */
+void REGPARAM2 CPUFUNC(op_10ba_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_10bb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_10bc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_10c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.B (An),(An)+ */
+void REGPARAM2 CPUFUNC(op_10d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_10d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B -(An),(An)+ */
+void REGPARAM2 CPUFUNC(op_10e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(An)+ */
+void REGPARAM2 CPUFUNC(op_10e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_10f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(An)+ */
+void REGPARAM2 CPUFUNC(op_10f8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(An)+ */
+void REGPARAM2 CPUFUNC(op_10f9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(An)+ */
+void REGPARAM2 CPUFUNC(op_10fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_10fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_10fc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_1100_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:0,T:2,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.B (An),-(An) */
+void REGPARAM2 CPUFUNC(op_1110_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (An)+,-(An) */
+void REGPARAM2 CPUFUNC(op_1118_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_1120_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),-(An) */
+void REGPARAM2 CPUFUNC(op_1128_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_1130_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,-(An) */
+void REGPARAM2 CPUFUNC(op_1138_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,-(An) */
+void REGPARAM2 CPUFUNC(op_1139_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),-(An) */
+void REGPARAM2 CPUFUNC(op_113a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_113b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_113c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1140_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B (An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1150_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1158_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B -(An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1160_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1168_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1170_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1178_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1179_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+	regs.irc = get_word_ce020_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(d16,An) */
+void REGPARAM2 CPUFUNC(op_117a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_117b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_117c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_1180_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}return;
+}
+
+/* MOVE.B (An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_1190_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_1198_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B -(An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 1);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11b8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11b9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11ba_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11bb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 1);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11bc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}return;
+}
+
+/* MOVE.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B (An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B -(An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+	regs.irc = get_word_ce020_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.B (An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B -(An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (6);
+	regs.irc = get_word_ce020_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (10);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}return;
+}
+
+/* MOVE.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_2000_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L An,Dn */
+void REGPARAM2 CPUFUNC(op_2008_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_2010_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_2018_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_2020_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_2028_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_2030_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_2038_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_2039_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_203a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_203b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* MOVE.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_203c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVEA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_2040_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVEA.L An,An */
+void REGPARAM2 CPUFUNC(op_2048_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVEA.L (An),An */
+void REGPARAM2 CPUFUNC(op_2050_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_2058_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_2060_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_2068_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_2070_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* MOVEA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_2078_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_2079_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVEA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_207a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_207b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* MOVEA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_207c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_2080_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L An,(An) */
+void REGPARAM2 CPUFUNC(op_2088_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L (An),(An) */
+void REGPARAM2 CPUFUNC(op_2090_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(An) */
+void REGPARAM2 CPUFUNC(op_2098_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L -(An),(An) */
+void REGPARAM2 CPUFUNC(op_20a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(An) */
+void REGPARAM2 CPUFUNC(op_20a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_20b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(An) */
+void REGPARAM2 CPUFUNC(op_20b8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(An) */
+void REGPARAM2 CPUFUNC(op_20b9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(An) */
+void REGPARAM2 CPUFUNC(op_20ba_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_20bb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_20bc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_20c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L An,(An)+ */
+void REGPARAM2 CPUFUNC(op_20c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L (An),(An)+ */
+void REGPARAM2 CPUFUNC(op_20d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_20d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L -(An),(An)+ */
+void REGPARAM2 CPUFUNC(op_20e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(An)+ */
+void REGPARAM2 CPUFUNC(op_20e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_20f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(An)+ */
+void REGPARAM2 CPUFUNC(op_20f8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(An)+ */
+void REGPARAM2 CPUFUNC(op_20f9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(An)+ */
+void REGPARAM2 CPUFUNC(op_20fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_20fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_20fc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_2100_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:0,T:2,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L An,-(An) */
+void REGPARAM2 CPUFUNC(op_2108_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:0,T:2,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L (An),-(An) */
+void REGPARAM2 CPUFUNC(op_2110_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (An)+,-(An) */
+void REGPARAM2 CPUFUNC(op_2118_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_2120_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),-(An) */
+void REGPARAM2 CPUFUNC(op_2128_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_2130_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,-(An) */
+void REGPARAM2 CPUFUNC(op_2138_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,-(An) */
+void REGPARAM2 CPUFUNC(op_2139_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),-(An) */
+void REGPARAM2 CPUFUNC(op_213a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_213b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_213c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2140_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.L An,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2148_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.L (An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2150_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2158_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L -(An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2160_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2168_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2170_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2178_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2179_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+	regs.irc = get_word_ce020_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(d16,An) */
+void REGPARAM2 CPUFUNC(op_217a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_217b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_217c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+	regs.irc = get_word_ce020_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}return;
+}
+
+/* MOVE.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2180_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}return;
+}
+
+/* MOVE.L An,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2188_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}return;
+}
+
+/* MOVE.L (An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2190_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2198_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+#endif
+
+#ifdef PART_3
+/* MOVE.L -(An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 1);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21b8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21b9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21ba_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21bb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 1);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21bc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}return;
+}
+
+/* MOVE.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.L An,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.L (An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L -(An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+	regs.irc = get_word_ce020_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+	regs.irc = get_word_ce020_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}return;
+}
+
+/* MOVE.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L An,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L (An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L -(An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (6);
+	regs.irc = get_word_ce020_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (10);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (6);
+	regs.irc = get_word_ce020_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (10);
+}}}return;
+}
+
+/* MOVE.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_3000_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W An,Dn */
+void REGPARAM2 CPUFUNC(op_3008_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_3010_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_3018_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_3020_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_3028_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_3030_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_3038_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_3039_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_303a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_303b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* MOVE.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_303c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVEA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_3040_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVEA.W An,An */
+void REGPARAM2 CPUFUNC(op_3048_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVEA.W (An),An */
+void REGPARAM2 CPUFUNC(op_3050_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_3058_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_3060_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_3068_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_3070_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return;
+}
+
+/* MOVEA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_3078_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_3079_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVEA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_307a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_307b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return;
+}
+
+/* MOVEA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_307c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_3080_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W An,(An) */
+void REGPARAM2 CPUFUNC(op_3088_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W (An),(An) */
+void REGPARAM2 CPUFUNC(op_3090_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(An) */
+void REGPARAM2 CPUFUNC(op_3098_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W -(An),(An) */
+void REGPARAM2 CPUFUNC(op_30a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(An) */
+void REGPARAM2 CPUFUNC(op_30a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_30b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(An) */
+void REGPARAM2 CPUFUNC(op_30b8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(An) */
+void REGPARAM2 CPUFUNC(op_30b9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(An) */
+void REGPARAM2 CPUFUNC(op_30ba_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_30bb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_30bc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_30c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W An,(An)+ */
+void REGPARAM2 CPUFUNC(op_30c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W (An),(An)+ */
+void REGPARAM2 CPUFUNC(op_30d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_30d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W -(An),(An)+ */
+void REGPARAM2 CPUFUNC(op_30e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(An)+ */
+void REGPARAM2 CPUFUNC(op_30e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_30f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(An)+ */
+void REGPARAM2 CPUFUNC(op_30f8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(An)+ */
+void REGPARAM2 CPUFUNC(op_30f9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(An)+ */
+void REGPARAM2 CPUFUNC(op_30fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_30fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_30fc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_3100_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:0,T:2,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W An,-(An) */
+void REGPARAM2 CPUFUNC(op_3108_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:0,T:2,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W (An),-(An) */
+void REGPARAM2 CPUFUNC(op_3110_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (An)+,-(An) */
+void REGPARAM2 CPUFUNC(op_3118_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_3120_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),-(An) */
+void REGPARAM2 CPUFUNC(op_3128_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_3130_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,-(An) */
+void REGPARAM2 CPUFUNC(op_3138_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,-(An) */
+void REGPARAM2 CPUFUNC(op_3139_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),-(An) */
+void REGPARAM2 CPUFUNC(op_313a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_313b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_313c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3140_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W An,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3148_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W (An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3150_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3158_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W -(An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3160_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3168_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3170_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3178_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3179_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+	regs.irc = get_word_ce020_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(d16,An) */
+void REGPARAM2 CPUFUNC(op_317a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_317b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_317c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3180_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}return;
+}
+
+/* MOVE.W An,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3188_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}return;
+}
+
+/* MOVE.W (An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3190_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3198_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W -(An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 1);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31b8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31b9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31ba_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31bb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 1);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31bc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}return;
+}
+
+/* MOVE.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W An,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W (An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W -(An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (6);
+	regs.irc = get_word_ce020_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.W An,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.W (An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W -(An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (6);
+	regs.irc = get_word_ce020_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (10);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (0);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	regs.irc = get_word_ce020_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}return;
+}
+
+/* NEGX.B Dn */
+void REGPARAM2 CPUFUNC(op_4000_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.B (An) */
+void REGPARAM2 CPUFUNC(op_4010_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4018_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.B -(An) */
+void REGPARAM2 CPUFUNC(op_4020_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4028_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4030_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, newv);
+}}}}}}return;
+}
+
+/* NEGX.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4038_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4039_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* NEGX.W Dn */
+void REGPARAM2 CPUFUNC(op_4040_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.W (An) */
+void REGPARAM2 CPUFUNC(op_4050_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4058_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.W -(An) */
+void REGPARAM2 CPUFUNC(op_4060_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4068_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4070_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, newv);
+}}}}}}return;
+}
+
+/* NEGX.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4078_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4079_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* NEGX.L Dn */
+void REGPARAM2 CPUFUNC(op_4080_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.L (An) */
+void REGPARAM2 CPUFUNC(op_4090_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4098_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.L -(An) */
+void REGPARAM2 CPUFUNC(op_40a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_40a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_40b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, newv);
+}}}}}}return;
+}
+
+/* NEGX.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_40b8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_40b9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* MVSR2.W Dn */
+void REGPARAM2 CPUFUNC(op_40c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_210632; }
+{{	/* op H:2,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}}	m68k_incpci (2);
+l_210632: ;
+return;
+}
+
+/* MVSR2.W (An) */
+void REGPARAM2 CPUFUNC(op_40d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_210633; }
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_210633: ;
+return;
+}
+
+/* MVSR2.W (An)+ */
+void REGPARAM2 CPUFUNC(op_40d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_210634; }
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	MakeSR ();
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_210634: ;
+return;
+}
+
+/* MVSR2.W -(An) */
+void REGPARAM2 CPUFUNC(op_40e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_210635; }
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_210635: ;
+return;
+}
+
+/* MVSR2.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_40e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_210636; }
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_210636: ;
+return;
+}
+
+/* MVSR2.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_40f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_210637; }
+{	/* ea H:4+2=6,T:0,C:0 cea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr);
+}}}}l_210637: ;
+return;
+}
+
+/* MVSR2.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_40f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_210638; }
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_210638: ;
+return;
+}
+
+/* MVSR2.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_40f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_210639; }
+{	/* ea H:4+2=6,T:0,C:0 cea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce020_prefetch (6);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (6);
+l_210639: ;
+return;
+}
+
+/* CHK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4100_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210640;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210640;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}l_210640: ;
+return;
+}
+
+#endif
+/* CHK.L (An),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4110_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210641;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210641;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210641: ;
+return;
+}
+
+#endif
+/* CHK.L (An)+,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4118_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210642;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210642;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210642: ;
+return;
+}
+
+#endif
+/* CHK.L -(An),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4120_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210643;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210643;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210643: ;
+return;
+}
+
+#endif
+/* CHK.L (d16,An),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4128_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210644;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210644;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210644: ;
+return;
+}
+
+#endif
+/* CHK.L (d8,An,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4130_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210645;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210645;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}l_210645: ;
+return;
+}
+
+#endif
+/* CHK.L (xxx).W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4138_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210646;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210646;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210646: ;
+return;
+}
+
+#endif
+/* CHK.L (xxx).L,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4139_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210647;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210647;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210647: ;
+return;
+}
+
+#endif
+/* CHK.L (d16,PC),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_413a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210648;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210648;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210648: ;
+return;
+}
+
+#endif
+/* CHK.L (d8,PC,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_413b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210649;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210649;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}l_210649: ;
+return;
+}
+
+#endif
+/* CHK.L #.L,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_413c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210650;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210650;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}l_210650: ;
+return;
+}
+
+#endif
+/* CHK.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_4180_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210651;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210651;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}l_210651: ;
+return;
+}
+
+/* CHK.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_4190_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210652;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210652;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210652: ;
+return;
+}
+
+/* CHK.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_4198_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210653;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210653;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210653: ;
+return;
+}
+
+/* CHK.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_41a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210654;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210654;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210654: ;
+return;
+}
+
+/* CHK.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_41a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210655;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210655;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210655: ;
+return;
+}
+
+/* CHK.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_41b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210656;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210656;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}l_210656: ;
+return;
+}
+
+/* CHK.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_41b8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210657;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210657;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210657: ;
+return;
+}
+
+/* CHK.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_41b9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210658;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210658;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210658: ;
+return;
+}
+
+/* CHK.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_41ba_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210659;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210659;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}l_210659: ;
+return;
+}
+
+/* CHK.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_41bb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210660;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210660;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}l_210660: ;
+return;
+}
+
+/* CHK.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_41bc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_210661;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_210661;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}l_210661: ;
+return;
+}
+
+/* LEA.L (An),An */
+void REGPARAM2 CPUFUNC(op_41d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	/* op H:2-,T:0,C:0 */
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* LEA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_41e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	/* op H:2-,T:0,C:0 */
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* LEA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_41f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{	/* ea H:4+2=6,T:0,C:0 cea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	/* op H:2-,T:0,C:0 */
+	regs.irc = get_word_ce020_prefetch (0);
+	m68k_areg (regs, dstreg) = (srca);
+}}}}return;
+}
+
+/* LEA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_41f8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	/* op H:2-,T:0,C:0 */
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* LEA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_41f9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{	/* ea H:4+2=6,T:0,C:0 cea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	/* op H:2-,T:0,C:0 */
+	regs.irc = get_word_ce020_prefetch (6);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* LEA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_41fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	/* op H:2-,T:0,C:0 */
+	regs.irc = get_word_ce020_prefetch (4);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* LEA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_41fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{	/* ea H:4+2=6,T:0,C:0 cea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	/* op H:2-,T:0,C:0 */
+	regs.irc = get_word_ce020_prefetch (0);
+	m68k_areg (regs, dstreg) = (srca);
+}}}}return;
+}
+
+/* CLR.B Dn */
+void REGPARAM2 CPUFUNC(op_4200_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.B (An) */
+void REGPARAM2 CPUFUNC(op_4210_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4218_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.B -(An) */
+void REGPARAM2 CPUFUNC(op_4220_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4228_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4230_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, 0);
+}}}return;
+}
+
+/* CLR.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4238_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4239_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (6);
+return;
+}
+
+/* CLR.W Dn */
+void REGPARAM2 CPUFUNC(op_4240_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.W (An) */
+void REGPARAM2 CPUFUNC(op_4250_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4258_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.W -(An) */
+void REGPARAM2 CPUFUNC(op_4260_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4268_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4270_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, 0);
+}}}return;
+}
+
+/* CLR.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4278_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4279_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, 0);
+}}	m68k_incpci (6);
+return;
+}
+
+/* CLR.L Dn */
+void REGPARAM2 CPUFUNC(op_4280_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.L (An) */
+void REGPARAM2 CPUFUNC(op_4290_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4298_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.L -(An) */
+void REGPARAM2 CPUFUNC(op_42a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_42a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_42b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, 0);
+}}}return;
+}
+
+/* CLR.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_42b8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_42b9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, 0);
+}}	m68k_incpci (6);
+return;
+}
+
+/* MVSR2.B Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{{	/* op H:2,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* MVSR2.B (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* MVSR2.B (An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	MakeSR ();
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* MVSR2.B -(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* MVSR2.B (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* MVSR2.B (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{	/* ea H:4+2=6,T:0,C:0 cea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}}return;
+}
+
+#endif
+/* MVSR2.B (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* MVSR2.B (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+{	/* ea H:4+2=6,T:0,C:0 cea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce020_prefetch (6);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* NEG.B Dn */
+void REGPARAM2 CPUFUNC(op_4400_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+
+#ifdef PART_4
+/* NEG.B (An) */
+void REGPARAM2 CPUFUNC(op_4410_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4418_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.B -(An) */
+void REGPARAM2 CPUFUNC(op_4420_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4428_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4430_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}}}return;
+}
+
+/* NEG.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4438_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4439_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* NEG.W Dn */
+void REGPARAM2 CPUFUNC(op_4440_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.W (An) */
+void REGPARAM2 CPUFUNC(op_4450_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4458_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.W -(An) */
+void REGPARAM2 CPUFUNC(op_4460_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4468_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4470_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}}}return;
+}
+
+/* NEG.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4478_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4479_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* NEG.L Dn */
+void REGPARAM2 CPUFUNC(op_4480_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.L (An) */
+void REGPARAM2 CPUFUNC(op_4490_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4498_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.L -(An) */
+void REGPARAM2 CPUFUNC(op_44a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_44a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_44b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}}}return;
+}
+
+/* NEG.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_44b8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_44b9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* MV2SR.B Dn */
+void REGPARAM2 CPUFUNC(op_44c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* op H:4,T:0,C:0 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+}}	m68k_incpci (2);
+return;
+}
+
+/* MV2SR.B (An) */
+void REGPARAM2 CPUFUNC(op_44d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MV2SR.B (An)+ */
+void REGPARAM2 CPUFUNC(op_44d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MV2SR.B -(An) */
+void REGPARAM2 CPUFUNC(op_44e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MV2SR.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_44e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MV2SR.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_44f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}}return;
+}
+
+/* MV2SR.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_44f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MV2SR.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_44f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MV2SR.B (d16,PC) */
+void REGPARAM2 CPUFUNC(op_44fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MV2SR.B (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_44fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}}return;
+}
+
+/* MV2SR.B #.B */
+void REGPARAM2 CPUFUNC(op_44fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.B Dn */
+void REGPARAM2 CPUFUNC(op_4600_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.B (An) */
+void REGPARAM2 CPUFUNC(op_4610_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4618_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.B -(An) */
+void REGPARAM2 CPUFUNC(op_4620_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4628_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4630_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}return;
+}
+
+/* NOT.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4638_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4639_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* NOT.W Dn */
+void REGPARAM2 CPUFUNC(op_4640_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.W (An) */
+void REGPARAM2 CPUFUNC(op_4650_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4658_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.W -(An) */
+void REGPARAM2 CPUFUNC(op_4660_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4668_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4670_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}return;
+}
+
+/* NOT.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4678_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4679_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* NOT.L Dn */
+void REGPARAM2 CPUFUNC(op_4680_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.L (An) */
+void REGPARAM2 CPUFUNC(op_4690_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4698_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.L -(An) */
+void REGPARAM2 CPUFUNC(op_46a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_46a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_46b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}return;
+}
+
+/* NOT.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_46b8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_46b9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* MV2SR.W Dn */
+void REGPARAM2 CPUFUNC(op_46c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_210760; }
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}	m68k_incpci (2);
+l_210760: ;
+return;
+}
+
+/* MV2SR.W (An) */
+void REGPARAM2 CPUFUNC(op_46d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_210761; }
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}	m68k_incpci (2);
+l_210761: ;
+return;
+}
+
+/* MV2SR.W (An)+ */
+void REGPARAM2 CPUFUNC(op_46d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_210762; }
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}	m68k_incpci (2);
+l_210762: ;
+return;
+}
+
+/* MV2SR.W -(An) */
+void REGPARAM2 CPUFUNC(op_46e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_210763; }
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}	m68k_incpci (2);
+l_210763: ;
+return;
+}
+
+/* MV2SR.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_46e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_210764; }
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}	m68k_incpci (4);
+l_210764: ;
+return;
+}
+
+/* MV2SR.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_46f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_210765; }
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}}l_210765: ;
+return;
+}
+
+/* MV2SR.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_46f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_210766; }
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}	m68k_incpci (4);
+l_210766: ;
+return;
+}
+
+/* MV2SR.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_46f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_210767; }
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}	m68k_incpci (6);
+l_210767: ;
+return;
+}
+
+/* MV2SR.W (d16,PC) */
+void REGPARAM2 CPUFUNC(op_46fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_210768; }
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}	m68k_incpci (4);
+l_210768: ;
+return;
+}
+
+/* MV2SR.W (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_46fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_210769; }
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}}l_210769: ;
+return;
+}
+
+/* MV2SR.W #.W */
+void REGPARAM2 CPUFUNC(op_46fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_210770; }
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}	m68k_incpci (4);
+l_210770: ;
+return;
+}
+
+/* NBCD.B Dn */
+void REGPARAM2 CPUFUNC(op_4800_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* LINK.L An,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4808_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+{	/* op H:2,T:0,C:4 */
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 offs;
+	offs = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	do_cycles_ce020_internal (4);
+	x_put_long (olda, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* NBCD.B (An) */
+void REGPARAM2 CPUFUNC(op_4810_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NBCD.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4818_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NBCD.B -(An) */
+void REGPARAM2 CPUFUNC(op_4820_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NBCD.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4828_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NBCD.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4830_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (srca, newv);
+}}}}}return;
+}
+
+/* NBCD.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4838_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NBCD.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4839_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce020_prefetch (6);
+	do_cycles_ce020_internal (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* SWAP.W Dn */
+void REGPARAM2 CPUFUNC(op_4840_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 34;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* BKPTQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4848_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 99;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce020_prefetch (0);
+}return;
+}
+
+#endif
+/* PEA.L (An) */
+void REGPARAM2 CPUFUNC(op_4850_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:2,C:2 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* PEA.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4868_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:2,C:2 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* PEA.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4870_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:2,C:2 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, srca);
+}}}}return;
+}
+
+/* PEA.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4878_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:2,C:2 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* PEA.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4879_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:2,C:2 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* PEA.L (d16,PC) */
+void REGPARAM2 CPUFUNC(op_487a_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:2,C:2 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* PEA.L (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_487b_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:2,C:2 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, srca);
+}}}}return;
+}
+
+/* EXT.W Dn */
+void REGPARAM2 CPUFUNC(op_4880_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u16 dst = (uae_s16)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVMLE.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_4890_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMLE.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_48a0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+	do_cycles_ce020_internal (2);
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	int type = get_cpu_model () >= 68020;
+	while (amask) {
+		srca -= 2;
+		if (!type || movem_index2[amask] != dstreg)
+			x_put_word (srca, m68k_areg (regs, movem_index2[amask]));
+		else
+			x_put_word (srca, m68k_areg (regs, movem_index2[amask]) - 2);
+		amask = movem_next[amask];
+	}
+	while (dmask) { srca -= 2; x_put_word (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMLE.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_48a8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMLE.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_48b0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}return;
+}
+
+/* MVMLE.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_48b8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMLE.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_48b9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (4);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_ce020_prefetch (8);
+}}}	m68k_incpci (8);
+return;
+}
+
+/* EXT.L Dn */
+void REGPARAM2 CPUFUNC(op_48c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 dst = (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVMLE.L #.W,(An) */
+void REGPARAM2 CPUFUNC(op_48d0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMLE.L #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_48e0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+	do_cycles_ce020_internal (2);
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	int type = get_cpu_model () >= 68020;
+	while (amask) {
+		srca -= 4;
+		if (!type || movem_index2[amask] != dstreg)
+			x_put_long (srca, m68k_areg (regs, movem_index2[amask]));
+		else
+			x_put_long (srca, m68k_areg (regs, movem_index2[amask]) - 4);
+		amask = movem_next[amask];
+	}
+	while (dmask) { srca -= 4; x_put_long (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMLE.L #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_48e8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMLE.L #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_48f0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}return;
+}
+
+/* MVMLE.L #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_48f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMLE.L #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_48f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (4);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_ce020_prefetch (8);
+}}}	m68k_incpci (8);
+return;
+}
+
+/* EXT.B Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_49c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 dst = (uae_s32)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* TST.B Dn */
+void REGPARAM2 CPUFUNC(op_4a00_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+}}	m68k_incpci (2);
+return;
+}
+
+/* TST.B (An) */
+void REGPARAM2 CPUFUNC(op_4a10_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4a18_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.B -(An) */
+void REGPARAM2 CPUFUNC(op_4a20_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4a28_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4a30_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return;
+}
+
+/* TST.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4a38_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4a39_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* TST.B (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a3a_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.B (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a3b_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return;
+}
+
+#endif
+/* TST.B #.B */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a3c_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.W Dn */
+void REGPARAM2 CPUFUNC(op_4a40_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+}}	m68k_incpci (2);
+return;
+}
+
+/* TST.W An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a48_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* TST.W (An) */
+void REGPARAM2 CPUFUNC(op_4a50_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4a58_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.W -(An) */
+void REGPARAM2 CPUFUNC(op_4a60_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4a68_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4a70_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return;
+}
+
+/* TST.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4a78_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4a79_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* TST.W (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a7a_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.W (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a7b_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return;
+}
+
+#endif
+/* TST.W #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a7c_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.L Dn */
+void REGPARAM2 CPUFUNC(op_4a80_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+}}	m68k_incpci (2);
+return;
+}
+
+/* TST.L An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a88_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* TST.L (An) */
+void REGPARAM2 CPUFUNC(op_4a90_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4a98_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.L -(An) */
+void REGPARAM2 CPUFUNC(op_4aa0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4aa8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4ab0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return;
+}
+
+/* TST.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4ab8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4ab9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* TST.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4aba_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4abb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return;
+}
+
+#endif
+/* TST.L #.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4abc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* TAS.B Dn */
+void REGPARAM2 CPUFUNC(op_4ac0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((src) & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+/* TAS.B (An) */
+void REGPARAM2 CPUFUNC(op_4ad0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TAS.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4ad8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TAS.B -(An) */
+void REGPARAM2 CPUFUNC(op_4ae0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TAS.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4ae8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TAS.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4af0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}}return;
+}
+
+/* TAS.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4af8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TAS.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4af9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MULL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c00_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_210847;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}l_210847: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c10_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_210848;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}l_210848: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c18_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_210849;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}l_210849: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c20_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_210850;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}l_210850: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c28_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_210851;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}l_210851: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c30_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:2,T:0,C:28 */
+	if (!m68k_mull(opcode, dst, extra)) goto l_210852;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}}l_210852: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c38_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_210853;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}l_210853: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c39_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_210854;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}l_210854: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c3a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_210855;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}l_210855: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c3b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:2,T:0,C:28 */
+	if (!m68k_mull(opcode, dst, extra)) goto l_210856;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}}l_210856: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c3c_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uae_s32 dst;
+	dst = get_long_ce020_prefetch (4);
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_210857;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}l_210857: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c40_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_210858;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}l_210858: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c50_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_210859;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}l_210859: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c58_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_210860;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}l_210860: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c60_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_210861;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}l_210861: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c68_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_210862;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}l_210862: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c70_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:0,T:0,C:50 */
+	if (!m68k_divl(opcode, dst, extra)) goto l_210863;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}}l_210863: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c78_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_210864;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}l_210864: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c79_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_210865;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}l_210865: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c7a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_210866;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}l_210866: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c7b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:0,T:0,C:50 */
+	if (!m68k_divl(opcode, dst, extra)) goto l_210867;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}}l_210867: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c7c_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uae_s32 dst;
+	dst = get_long_ce020_prefetch (4);
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_210868;
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}l_210868: ;
+return;
+}
+
+#endif
+/* MVMEL.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_4c90_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMEL.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_4c98_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMEL.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_4ca8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4cb0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}return;
+}
+
+/* MVMEL.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_4cb8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_4cb9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce020_prefetch (8);
+}}}	m68k_incpci (8);
+return;
+}
+
+/* MVMEL.W #.W,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_4cba_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.W #.W,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4cbb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}return;
+}
+
+/* MVMEL.L #.W,(An) */
+void REGPARAM2 CPUFUNC(op_4cd0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMEL.L #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_4cd8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_ce020_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMEL.L #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_4ce8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.L #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4cf0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}return;
+}
+
+/* MVMEL.L #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_4cf8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.L #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_4cf9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce020_prefetch (8);
+}}}	m68k_incpci (8);
+return;
+}
+
+/* MVMEL.L #.W,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_4cfa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce020_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.L #.W,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4cfb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce020_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}return;
+}
+
+/* TRAPQ.L # */
+void REGPARAM2 CPUFUNC(op_4e40_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 15);
+	OpcodeFamily = 39;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	m68k_incpci (2);
+	Exception (src + 32);
+}}return;
+}
+
+/* LINK.W An,#.W */
+void REGPARAM2 CPUFUNC(op_4e50_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+{	/* op H:0,T:0,C:4 */
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (2);
+	x_put_long (olda, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* UNLK.L An */
+void REGPARAM2 CPUFUNC(op_4e58_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 48;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	/* op H:0,T:0,C:5 */
+	m68k_areg (regs, 7) = src;
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7);
+{	uae_s32 old = x_get_long (olda);
+	m68k_areg (regs, 7) += 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (3);
+	m68k_areg (regs, srcreg) = (old);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* MVR2USP.L An */
+void REGPARAM2 CPUFUNC(op_4e60_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 40;
+{if (!regs.s) { Exception (8); goto l_210888; }
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	/* op H:4,T:0,C:0 */
+	regs.usp = src;
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (2);
+l_210888: ;
+return;
+}
+
+/* MVUSP2R.L An */
+void REGPARAM2 CPUFUNC(op_4e68_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 41;
+{if (!regs.s) { Exception (8); goto l_210889; }
+{{	/* op H:4,T:0,C:0 */
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, srcreg) = (regs.usp);
+}}}	m68k_incpci (2);
+l_210889: ;
+return;
+}
+
+/* RESET.L  */
+void REGPARAM2 CPUFUNC(op_4e70_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 42;
+{if (!regs.s) { Exception (8); goto l_210890; }
+{	cpureset ();
+	m68k_incpci (2);
+	regs.irc = get_word_ce020_prefetch (0);
+}}l_210890: ;
+return;
+}
+
+/* NOP.L  */
+void REGPARAM2 CPUFUNC(op_4e71_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 43;
+{	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+return;
+}
+
+/* STOP.L #.W */
+void REGPARAM2 CPUFUNC(op_4e72_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 44;
+{if (!regs.s) { Exception (8); goto l_210892; }
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_setstopped ();
+	m68k_incpci (4);
+	do_cycles_ce020_internal (6);
+}}}l_210892: ;
+return;
+}
+
+/* RTE.L  */
+void REGPARAM2 CPUFUNC(op_4e73_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 45;
+{if (!regs.s) { Exception (8); goto l_210893; }
+{	/* op H:1,T:9,C:8 */
+	uae_u16 newsr; uae_u32 newpc;
+	for (;;) {
+		uaecptr a = m68k_areg (regs, 7);
+		uae_u16 sr = x_get_word (a);
+		uae_u32 pc = x_get_long (a + 2);
+		uae_u16 format = x_get_word (a + 2 + 4);
+		int frame = format >> 12;
+		int offset = 8;
+		newsr = sr; newpc = pc;
+	do_cycles_ce020_internal (6);
+		if (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }
+		else if (frame == 0x1) { m68k_areg (regs, 7) += offset; }
+		else if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }
+		else if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }
+		else if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }
+		else if (frame == 0x7) { m68k_areg (regs, 7) += offset + 52; break; }
+		else if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }
+		else if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }
+		else if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }
+		else { m68k_areg (regs, 7) += offset; Exception (14); goto l_210893; }
+		regs.sr = newsr;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+}
+	regs.sr = newsr;
+	do_cycles_ce020_internal (4);
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	if (newpc & 1) {
+		exception3i (0x4E73, newpc);
+		goto l_210893;
+	}
+	m68k_setpci (newpc);
+	ipl_fetch ();
+	fill_prefetch_020 ();
+}}l_210893: ;
+return;
+}
+
+/* RTD.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4e74_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 46;
+{	/* op H:2,T:0,C:8 */
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = x_get_long (pca);
+	m68k_areg (regs, 7) += 4;
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* op H:2,T:0,C:8 */
+	m68k_areg (regs, 7) += offs;
+	if (pc & 1) {
+		exception3i (0x4E74, pc);
+		goto l_210894;
+	}
+	m68k_setpci (pc);
+	fill_prefetch_020 ();
+}}}}l_210894: ;
+return;
+}
+
+#endif
+/* RTS.L  */
+void REGPARAM2 CPUFUNC(op_4e75_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 49;
+{	/* op H:1,T:0,C:8 */
+	uaecptr pc = m68k_getpci ();
+	m68k_do_rts_ce020 ();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (pc);
+		exception3i (0x4E75, faultpc);
+		goto l_210895;
+	}
+	do_cycles_ce020_internal (3);
+	fill_prefetch_020 ();
+}l_210895: ;
+return;
+}
+
+/* TRAPV.L  */
+void REGPARAM2 CPUFUNC(op_4e76_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 50;
+{	m68k_incpci (2);
+	if (GET_VFLG ()) {
+		Exception (7);
+		goto l_210896;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}l_210896: ;
+return;
+}
+
+/* RTR.L  */
+void REGPARAM2 CPUFUNC(op_4e77_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 51;
+{	uaecptr oldpc = m68k_getpci ();
+	MakeSR ();
+{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+{	uae_s16 sr = x_get_word (sra);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = x_get_long (pca);
+	m68k_areg (regs, 7) += 4;
+	regs.sr &= 0xFF00; sr &= 0xFF;
+	regs.sr |= sr;
+	m68k_setpci (pc);
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (oldpc);
+		exception3i (0x4E77, faultpc);
+		goto l_210897;
+	}
+	fill_prefetch_020 ();
+}}}}}l_210897: ;
+return;
+}
+
+/* MOVEC2.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4e7a_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 82;
+{if (!regs.s) { Exception (8); goto l_210898; }
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* op H:6,T:0,C:0 */
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_movec2(src & 0xFFF, regp)) goto l_210898;
+	regs.irc = get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (4);
+}}}}	m68k_incpci (4);
+l_210898: ;
+return;
+}
+
+#endif
+/* MOVE2C.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4e7b_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 83;
+{if (!regs.s) { Exception (8); goto l_210899; }
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* op H:6,T:0,C:0 */
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_move2c(src & 0xFFF, regp)) goto l_210899;
+	regs.irc = get_word_ce020_prefetch (4);
+	do_cycles_ce020_internal (4);
+}}}}	m68k_incpci (4);
+l_210899: ;
+return;
+}
+
+#endif
+/* JSR.L (An) */
+void REGPARAM2 CPUFUNC(op_4e90_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+{	/* ea H:2,T:0,C:0 jea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uaecptr oldpc = m68k_getpci () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_210900;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_020 ();
+}}}l_210900: ;
+return;
+}
+
+/* JSR.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4ea8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+{	/* ea H:4,T:0,C:0 jea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_210901;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_020 ();
+}}}l_210901: ;
+return;
+}
+
+/* JSR.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4eb0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+{	/* ea H:0,T:0,C:0 jea */
+	regs.ce020memcycles = 0;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_210902;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_020 ();
+}}}}l_210902: ;
+return;
+}
+
+/* JSR.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4eb8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+{	/* ea H:2,T:0,C:0 jea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_210903;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_020 ();
+}}}l_210903: ;
+return;
+}
+
+/* JSR.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4eb9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+{	/* ea H:2,T:0,C:0 jea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uaecptr oldpc = m68k_getpci () + 6;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_210904;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_020 ();
+}}}l_210904: ;
+return;
+}
+
+/* JSR.L (d16,PC) */
+void REGPARAM2 CPUFUNC(op_4eba_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+{	/* ea H:4,T:0,C:0 jea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_210905;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_020 ();
+}}}l_210905: ;
+return;
+}
+
+/* JSR.L (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4ebb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+{	/* ea H:0,T:0,C:0 jea */
+	regs.ce020memcycles = 0;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_210906;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_020 ();
+}}}}l_210906: ;
+return;
+}
+
+/* JMP.L (An) */
+void REGPARAM2 CPUFUNC(op_4ed0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+{	/* ea H:2+4=6,T:0,C:0 jea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	/* op H:4-,T:0,C:0 */
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_210907;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_020 ();
+}}l_210907: ;
+return;
+}
+
+/* JMP.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4ee8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+{	/* ea H:4+4=8,T:0,C:0 jea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	/* op H:4-,T:0,C:0 */
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_210908;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_020 ();
+}}l_210908: ;
+return;
+}
+
+/* JMP.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4ef0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+{	/* ea H:0,T:0,C:0 jea */
+	regs.ce020memcycles = 0;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_210909;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_020 ();
+}}}l_210909: ;
+return;
+}
+
+/* JMP.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4ef8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+{	/* ea H:2+4=6,T:0,C:0 jea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	/* op H:4-,T:0,C:0 */
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_210910;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_020 ();
+}}l_210910: ;
+return;
+}
+
+/* JMP.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4ef9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+{	/* ea H:2+4=6,T:0,C:0 jea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	/* op H:4-,T:0,C:0 */
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_210911;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_020 ();
+}}l_210911: ;
+return;
+}
+
+/* JMP.L (d16,PC) */
+void REGPARAM2 CPUFUNC(op_4efa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+{	/* ea H:4+4=8,T:0,C:0 jea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	/* op H:4-,T:0,C:0 */
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_210912;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_020 ();
+}}l_210912: ;
+return;
+}
+
+/* JMP.L (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4efb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+{	/* ea H:0,T:0,C:0 jea */
+	regs.ce020memcycles = 0;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_210913;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_020 ();
+}}}l_210913: ;
+return;
+}
+
+/* ADDQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_5000_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.B #,(An) */
+void REGPARAM2 CPUFUNC(op_5010_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.B #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5018_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.B #,-(An) */
+void REGPARAM2 CPUFUNC(op_5020_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.B #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5028_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.B #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5030_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADDQ.B #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5038_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.B #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5039_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_5040_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDAQ.W #,An */
+void REGPARAM2 CPUFUNC(op_5048_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.W #,(An) */
+void REGPARAM2 CPUFUNC(op_5050_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.W #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5058_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.W #,-(An) */
+void REGPARAM2 CPUFUNC(op_5060_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.W #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5068_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.W #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5070_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADDQ.W #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5078_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.W #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5079_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_5080_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDAQ.L #,An */
+void REGPARAM2 CPUFUNC(op_5088_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.L #,(An) */
+void REGPARAM2 CPUFUNC(op_5090_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.L #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5098_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.L #,-(An) */
+void REGPARAM2 CPUFUNC(op_50a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+
+#ifdef PART_5
+/* ADDQ.L #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_50a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.L #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_50b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADDQ.L #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_50b8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.L #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_50b9_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* Scc.B Dn (T) */
+void REGPARAM2 CPUFUNC(op_50c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (T) */
+void REGPARAM2 CPUFUNC(op_50c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (0)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_210941;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_210941: ;
+return;
+}
+
+/* Scc.B (An) (T) */
+void REGPARAM2 CPUFUNC(op_50d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (T) */
+void REGPARAM2 CPUFUNC(op_50d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (T) */
+void REGPARAM2 CPUFUNC(op_50e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (T) */
+void REGPARAM2 CPUFUNC(op_50e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (T) */
+void REGPARAM2 CPUFUNC(op_50f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (T) */
+void REGPARAM2 CPUFUNC(op_50f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (T) */
+void REGPARAM2 CPUFUNC(op_50f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (T) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_50fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (0)) { Exception (7); goto l_210949; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_210949: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (T) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_50fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (0)) { Exception (7); goto l_210950; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_210950: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (T) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_50fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (0)) { Exception (7); goto l_210951; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_210951: ;
+return;
+}
+
+#endif
+/* SUBQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_5100_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.B #,(An) */
+void REGPARAM2 CPUFUNC(op_5110_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.B #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5118_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.B #,-(An) */
+void REGPARAM2 CPUFUNC(op_5120_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.B #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5128_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.B #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5130_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUBQ.B #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5138_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.B #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5139_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_5140_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBAQ.W #,An */
+void REGPARAM2 CPUFUNC(op_5148_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.W #,(An) */
+void REGPARAM2 CPUFUNC(op_5150_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.W #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5158_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.W #,-(An) */
+void REGPARAM2 CPUFUNC(op_5160_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.W #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5168_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.W #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5170_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUBQ.W #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5178_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.W #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5179_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_5180_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBAQ.L #,An */
+void REGPARAM2 CPUFUNC(op_5188_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.L #,(An) */
+void REGPARAM2 CPUFUNC(op_5190_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.L #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5198_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.L #,-(An) */
+void REGPARAM2 CPUFUNC(op_51a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.L #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_51a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.L #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_51b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUBQ.L #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_51b8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.L #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_51b9_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* Scc.B Dn (F) */
+void REGPARAM2 CPUFUNC(op_51c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (F) */
+void REGPARAM2 CPUFUNC(op_51c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (1)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_210979;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_210979: ;
+return;
+}
+
+/* Scc.B (An) (F) */
+void REGPARAM2 CPUFUNC(op_51d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (F) */
+void REGPARAM2 CPUFUNC(op_51d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (F) */
+void REGPARAM2 CPUFUNC(op_51e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (F) */
+void REGPARAM2 CPUFUNC(op_51e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (F) */
+void REGPARAM2 CPUFUNC(op_51f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (F) */
+void REGPARAM2 CPUFUNC(op_51f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (F) */
+void REGPARAM2 CPUFUNC(op_51f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (F) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_51fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (1)) { Exception (7); goto l_210987; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_210987: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (F) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_51fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (1)) { Exception (7); goto l_210988; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_210988: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (F) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_51fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (1)) { Exception (7); goto l_210989; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_210989: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (HI) */
+void REGPARAM2 CPUFUNC(op_52c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (HI) */
+void REGPARAM2 CPUFUNC(op_52c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (2)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_210991;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_210991: ;
+return;
+}
+
+/* Scc.B (An) (HI) */
+void REGPARAM2 CPUFUNC(op_52d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (HI) */
+void REGPARAM2 CPUFUNC(op_52d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (HI) */
+void REGPARAM2 CPUFUNC(op_52e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (HI) */
+void REGPARAM2 CPUFUNC(op_52e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (HI) */
+void REGPARAM2 CPUFUNC(op_52f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (HI) */
+void REGPARAM2 CPUFUNC(op_52f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (HI) */
+void REGPARAM2 CPUFUNC(op_52f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (HI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_52fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (2)) { Exception (7); goto l_210999; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_210999: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (HI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_52fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (2)) { Exception (7); goto l_211000; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_211000: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (HI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_52fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (2)) { Exception (7); goto l_211001; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_211001: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (LS) */
+void REGPARAM2 CPUFUNC(op_53c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (LS) */
+void REGPARAM2 CPUFUNC(op_53c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (3)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_211003;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_211003: ;
+return;
+}
+
+/* Scc.B (An) (LS) */
+void REGPARAM2 CPUFUNC(op_53d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (LS) */
+void REGPARAM2 CPUFUNC(op_53d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (LS) */
+void REGPARAM2 CPUFUNC(op_53e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (LS) */
+void REGPARAM2 CPUFUNC(op_53e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (LS) */
+void REGPARAM2 CPUFUNC(op_53f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (LS) */
+void REGPARAM2 CPUFUNC(op_53f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (LS) */
+void REGPARAM2 CPUFUNC(op_53f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (LS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_53fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (3)) { Exception (7); goto l_211011; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_211011: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (LS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_53fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (3)) { Exception (7); goto l_211012; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_211012: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (LS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_53fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (3)) { Exception (7); goto l_211013; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_211013: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (CC) */
+void REGPARAM2 CPUFUNC(op_54c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (CC) */
+void REGPARAM2 CPUFUNC(op_54c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (4)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_211015;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_211015: ;
+return;
+}
+
+/* Scc.B (An) (CC) */
+void REGPARAM2 CPUFUNC(op_54d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (CC) */
+void REGPARAM2 CPUFUNC(op_54d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (CC) */
+void REGPARAM2 CPUFUNC(op_54e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (CC) */
+void REGPARAM2 CPUFUNC(op_54e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (CC) */
+void REGPARAM2 CPUFUNC(op_54f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (CC) */
+void REGPARAM2 CPUFUNC(op_54f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (CC) */
+void REGPARAM2 CPUFUNC(op_54f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (CC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_54fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (4)) { Exception (7); goto l_211023; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_211023: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (CC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_54fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (4)) { Exception (7); goto l_211024; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_211024: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (CC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_54fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (4)) { Exception (7); goto l_211025; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_211025: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (CS) */
+void REGPARAM2 CPUFUNC(op_55c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (CS) */
+void REGPARAM2 CPUFUNC(op_55c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (5)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_211027;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_211027: ;
+return;
+}
+
+/* Scc.B (An) (CS) */
+void REGPARAM2 CPUFUNC(op_55d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (CS) */
+void REGPARAM2 CPUFUNC(op_55d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (CS) */
+void REGPARAM2 CPUFUNC(op_55e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (CS) */
+void REGPARAM2 CPUFUNC(op_55e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (CS) */
+void REGPARAM2 CPUFUNC(op_55f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (CS) */
+void REGPARAM2 CPUFUNC(op_55f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (CS) */
+void REGPARAM2 CPUFUNC(op_55f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (CS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_55fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (5)) { Exception (7); goto l_211035; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_211035: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (CS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_55fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (5)) { Exception (7); goto l_211036; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_211036: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (CS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_55fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (5)) { Exception (7); goto l_211037; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_211037: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (NE) */
+void REGPARAM2 CPUFUNC(op_56c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (NE) */
+void REGPARAM2 CPUFUNC(op_56c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (6)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_211039;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_211039: ;
+return;
+}
+
+/* Scc.B (An) (NE) */
+void REGPARAM2 CPUFUNC(op_56d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (NE) */
+void REGPARAM2 CPUFUNC(op_56d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (NE) */
+void REGPARAM2 CPUFUNC(op_56e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (NE) */
+void REGPARAM2 CPUFUNC(op_56e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (NE) */
+void REGPARAM2 CPUFUNC(op_56f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (NE) */
+void REGPARAM2 CPUFUNC(op_56f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (NE) */
+void REGPARAM2 CPUFUNC(op_56f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (NE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_56fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (6)) { Exception (7); goto l_211047; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_211047: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (NE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_56fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (6)) { Exception (7); goto l_211048; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_211048: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (NE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_56fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (6)) { Exception (7); goto l_211049; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_211049: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (EQ) */
+void REGPARAM2 CPUFUNC(op_57c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (EQ) */
+void REGPARAM2 CPUFUNC(op_57c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (7)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_211051;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_211051: ;
+return;
+}
+
+/* Scc.B (An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (EQ) */
+void REGPARAM2 CPUFUNC(op_57d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (EQ) */
+void REGPARAM2 CPUFUNC(op_57f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (EQ) */
+void REGPARAM2 CPUFUNC(op_57f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (EQ) */
+void REGPARAM2 CPUFUNC(op_57f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (EQ) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_57fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (7)) { Exception (7); goto l_211059; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_211059: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (EQ) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_57fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (7)) { Exception (7); goto l_211060; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_211060: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (EQ) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_57fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (7)) { Exception (7); goto l_211061; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_211061: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (VC) */
+void REGPARAM2 CPUFUNC(op_58c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (VC) */
+void REGPARAM2 CPUFUNC(op_58c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (8)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_211063;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_211063: ;
+return;
+}
+
+/* Scc.B (An) (VC) */
+void REGPARAM2 CPUFUNC(op_58d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (VC) */
+void REGPARAM2 CPUFUNC(op_58d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (VC) */
+void REGPARAM2 CPUFUNC(op_58e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (VC) */
+void REGPARAM2 CPUFUNC(op_58e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (VC) */
+void REGPARAM2 CPUFUNC(op_58f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (VC) */
+void REGPARAM2 CPUFUNC(op_58f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (VC) */
+void REGPARAM2 CPUFUNC(op_58f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (VC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_58fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (8)) { Exception (7); goto l_211071; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_211071: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (VC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_58fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (8)) { Exception (7); goto l_211072; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_211072: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (VC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_58fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (8)) { Exception (7); goto l_211073; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_211073: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (VS) */
+void REGPARAM2 CPUFUNC(op_59c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (VS) */
+void REGPARAM2 CPUFUNC(op_59c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (9)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_211075;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_211075: ;
+return;
+}
+
+/* Scc.B (An) (VS) */
+void REGPARAM2 CPUFUNC(op_59d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (VS) */
+void REGPARAM2 CPUFUNC(op_59d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (VS) */
+void REGPARAM2 CPUFUNC(op_59e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (VS) */
+void REGPARAM2 CPUFUNC(op_59e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (VS) */
+void REGPARAM2 CPUFUNC(op_59f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (VS) */
+void REGPARAM2 CPUFUNC(op_59f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (VS) */
+void REGPARAM2 CPUFUNC(op_59f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (VS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_59fa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (9)) { Exception (7); goto l_211083; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_211083: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (VS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_59fb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (9)) { Exception (7); goto l_211084; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_211084: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (VS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_59fc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (9)) { Exception (7); goto l_211085; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_211085: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (PL) */
+void REGPARAM2 CPUFUNC(op_5ac0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (PL) */
+void REGPARAM2 CPUFUNC(op_5ac8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (10)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_211087;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_211087: ;
+return;
+}
+
+/* Scc.B (An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ad0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (PL) */
+void REGPARAM2 CPUFUNC(op_5ad8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ae0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ae8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (PL) */
+void REGPARAM2 CPUFUNC(op_5af0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (PL) */
+void REGPARAM2 CPUFUNC(op_5af8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (PL) */
+void REGPARAM2 CPUFUNC(op_5af9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (PL) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5afa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (10)) { Exception (7); goto l_211095; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_211095: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (PL) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5afb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (10)) { Exception (7); goto l_211096; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_211096: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (PL) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5afc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (10)) { Exception (7); goto l_211097; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_211097: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (MI) */
+void REGPARAM2 CPUFUNC(op_5bc0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (MI) */
+void REGPARAM2 CPUFUNC(op_5bc8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (11)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_211099;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_211099: ;
+return;
+}
+
+/* Scc.B (An) (MI) */
+void REGPARAM2 CPUFUNC(op_5bd0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (MI) */
+void REGPARAM2 CPUFUNC(op_5bd8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (MI) */
+void REGPARAM2 CPUFUNC(op_5be0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (MI) */
+void REGPARAM2 CPUFUNC(op_5be8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (MI) */
+void REGPARAM2 CPUFUNC(op_5bf0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (MI) */
+void REGPARAM2 CPUFUNC(op_5bf8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (MI) */
+void REGPARAM2 CPUFUNC(op_5bf9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (MI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5bfa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (11)) { Exception (7); goto l_211107; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_211107: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (MI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5bfb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (11)) { Exception (7); goto l_211108; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_211108: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (MI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5bfc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (11)) { Exception (7); goto l_211109; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_211109: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (GE) */
+void REGPARAM2 CPUFUNC(op_5cc0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (GE) */
+void REGPARAM2 CPUFUNC(op_5cc8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (12)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_211111;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_211111: ;
+return;
+}
+
+/* Scc.B (An) (GE) */
+void REGPARAM2 CPUFUNC(op_5cd0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (GE) */
+void REGPARAM2 CPUFUNC(op_5cd8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (GE) */
+void REGPARAM2 CPUFUNC(op_5ce0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (GE) */
+void REGPARAM2 CPUFUNC(op_5ce8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (GE) */
+void REGPARAM2 CPUFUNC(op_5cf0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (GE) */
+void REGPARAM2 CPUFUNC(op_5cf8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (GE) */
+void REGPARAM2 CPUFUNC(op_5cf9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (GE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5cfa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (12)) { Exception (7); goto l_211119; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_211119: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (GE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5cfb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (12)) { Exception (7); goto l_211120; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_211120: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (GE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5cfc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (12)) { Exception (7); goto l_211121; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_211121: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (LT) */
+void REGPARAM2 CPUFUNC(op_5dc0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (LT) */
+void REGPARAM2 CPUFUNC(op_5dc8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (13)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_211123;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_211123: ;
+return;
+}
+
+/* Scc.B (An) (LT) */
+void REGPARAM2 CPUFUNC(op_5dd0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (LT) */
+void REGPARAM2 CPUFUNC(op_5dd8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (LT) */
+void REGPARAM2 CPUFUNC(op_5de0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (LT) */
+void REGPARAM2 CPUFUNC(op_5de8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (LT) */
+void REGPARAM2 CPUFUNC(op_5df0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (LT) */
+void REGPARAM2 CPUFUNC(op_5df8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (LT) */
+void REGPARAM2 CPUFUNC(op_5df9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (LT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5dfa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (13)) { Exception (7); goto l_211131; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_211131: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (LT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5dfb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (13)) { Exception (7); goto l_211132; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_211132: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (LT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5dfc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (13)) { Exception (7); goto l_211133; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_211133: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (GT) */
+void REGPARAM2 CPUFUNC(op_5ec0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (GT) */
+void REGPARAM2 CPUFUNC(op_5ec8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (14)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_211135;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_211135: ;
+return;
+}
+
+/* Scc.B (An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ed0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (GT) */
+void REGPARAM2 CPUFUNC(op_5ed8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ee0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ee8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (GT) */
+void REGPARAM2 CPUFUNC(op_5ef0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (GT) */
+void REGPARAM2 CPUFUNC(op_5ef8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (GT) */
+void REGPARAM2 CPUFUNC(op_5ef9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (GT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5efa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (14)) { Exception (7); goto l_211143; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_211143: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (GT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5efb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (14)) { Exception (7); goto l_211144; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_211144: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (GT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5efc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (14)) { Exception (7); goto l_211145; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_211145: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (LE) */
+void REGPARAM2 CPUFUNC(op_5fc0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (LE) */
+void REGPARAM2 CPUFUNC(op_5fc8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce020_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (15)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_211147;
+			}
+	fill_prefetch_020 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_211147: ;
+return;
+}
+
+/* Scc.B (An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fd0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (LE) */
+void REGPARAM2 CPUFUNC(op_5fd8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fe0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fe8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (LE) */
+void REGPARAM2 CPUFUNC(op_5ff0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (LE) */
+void REGPARAM2 CPUFUNC(op_5ff8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (LE) */
+void REGPARAM2 CPUFUNC(op_5ff9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (LE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5ffa_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (15)) { Exception (7); goto l_211155; }
+	regs.irc = get_word_ce020_prefetch (4);
+}}	m68k_incpci (4);
+l_211155: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (LE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5ffb_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (cctrue (15)) { Exception (7); goto l_211156; }
+	regs.irc = get_word_ce020_prefetch (6);
+}}	m68k_incpci (6);
+l_211156: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (LE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5ffc_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (15)) { Exception (7); goto l_211157; }
+	regs.irc = get_word_ce020_prefetch (2);
+}	m68k_incpci (2);
+l_211157: ;
+return;
+}
+
+#endif
+/* Bcc.W #.W (T) */
+void REGPARAM2 CPUFUNC(op_6000_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211158;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211158: ;
+return;
+}
+
+/* BccQ.B # (T) */
+void REGPARAM2 CPUFUNC(op_6001_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211159;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211159: ;
+return;
+}
+
+/* Bcc.L #.L (T) */
+void REGPARAM2 CPUFUNC(op_60ff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211160;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211160: ;
+return;
+}
+
+/* BSR.W #.W */
+void REGPARAM2 CPUFUNC(op_6100_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+{	uae_s32 s;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* op H:2,T:0,C:4 */
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_211161;
+	}
+	m68k_do_bsr_ce020 (m68k_getpci () + 4, s);
+	fill_prefetch_020 ();
+}}l_211161: ;
+return;
+}
+
+/* BSRQ.B # */
+void REGPARAM2 CPUFUNC(op_6101_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 54;
+{	uae_s32 s;
+{	uae_u32 src = srcreg;
+	/* op H:2,T:0,C:4 */
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_211162;
+	}
+	m68k_do_bsr_ce020 (m68k_getpci () + 2, s);
+	fill_prefetch_020 ();
+}}l_211162: ;
+return;
+}
+
+/* BSR.L #.L */
+void REGPARAM2 CPUFUNC(op_61ff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+{	uae_s32 s;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* op H:2,T:0,C:4 */
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_211163;
+	}
+	m68k_do_bsr_ce020 (m68k_getpci () + 6, s);
+	fill_prefetch_020 ();
+}}l_211163: ;
+return;
+}
+
+/* Bcc.W #.W (HI) */
+void REGPARAM2 CPUFUNC(op_6200_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211164;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211164: ;
+return;
+}
+
+/* BccQ.B # (HI) */
+void REGPARAM2 CPUFUNC(op_6201_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211165;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211165: ;
+return;
+}
+
+/* Bcc.L #.L (HI) */
+void REGPARAM2 CPUFUNC(op_62ff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211166;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211166: ;
+return;
+}
+
+/* Bcc.W #.W (LS) */
+void REGPARAM2 CPUFUNC(op_6300_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211167;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211167: ;
+return;
+}
+
+/* BccQ.B # (LS) */
+void REGPARAM2 CPUFUNC(op_6301_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211168;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211168: ;
+return;
+}
+
+#endif
+
+#ifdef PART_6
+/* Bcc.L #.L (LS) */
+void REGPARAM2 CPUFUNC(op_63ff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211169;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211169: ;
+return;
+}
+
+/* Bcc.W #.W (CC) */
+void REGPARAM2 CPUFUNC(op_6400_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211170;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211170: ;
+return;
+}
+
+/* BccQ.B # (CC) */
+void REGPARAM2 CPUFUNC(op_6401_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211171;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211171: ;
+return;
+}
+
+/* Bcc.L #.L (CC) */
+void REGPARAM2 CPUFUNC(op_64ff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211172;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211172: ;
+return;
+}
+
+/* Bcc.W #.W (CS) */
+void REGPARAM2 CPUFUNC(op_6500_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211173;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211173: ;
+return;
+}
+
+/* BccQ.B # (CS) */
+void REGPARAM2 CPUFUNC(op_6501_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211174;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211174: ;
+return;
+}
+
+/* Bcc.L #.L (CS) */
+void REGPARAM2 CPUFUNC(op_65ff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211175;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211175: ;
+return;
+}
+
+/* Bcc.W #.W (NE) */
+void REGPARAM2 CPUFUNC(op_6600_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211176;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211176: ;
+return;
+}
+
+/* BccQ.B # (NE) */
+void REGPARAM2 CPUFUNC(op_6601_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211177;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211177: ;
+return;
+}
+
+/* Bcc.L #.L (NE) */
+void REGPARAM2 CPUFUNC(op_66ff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211178;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211178: ;
+return;
+}
+
+/* Bcc.W #.W (EQ) */
+void REGPARAM2 CPUFUNC(op_6700_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211179;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211179: ;
+return;
+}
+
+/* BccQ.B # (EQ) */
+void REGPARAM2 CPUFUNC(op_6701_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211180;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211180: ;
+return;
+}
+
+/* Bcc.L #.L (EQ) */
+void REGPARAM2 CPUFUNC(op_67ff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211181;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211181: ;
+return;
+}
+
+/* Bcc.W #.W (VC) */
+void REGPARAM2 CPUFUNC(op_6800_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211182;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211182: ;
+return;
+}
+
+/* BccQ.B # (VC) */
+void REGPARAM2 CPUFUNC(op_6801_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211183;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211183: ;
+return;
+}
+
+/* Bcc.L #.L (VC) */
+void REGPARAM2 CPUFUNC(op_68ff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211184;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211184: ;
+return;
+}
+
+/* Bcc.W #.W (VS) */
+void REGPARAM2 CPUFUNC(op_6900_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211185;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211185: ;
+return;
+}
+
+/* BccQ.B # (VS) */
+void REGPARAM2 CPUFUNC(op_6901_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211186;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211186: ;
+return;
+}
+
+/* Bcc.L #.L (VS) */
+void REGPARAM2 CPUFUNC(op_69ff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211187;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211187: ;
+return;
+}
+
+/* Bcc.W #.W (PL) */
+void REGPARAM2 CPUFUNC(op_6a00_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211188;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211188: ;
+return;
+}
+
+/* BccQ.B # (PL) */
+void REGPARAM2 CPUFUNC(op_6a01_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211189;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211189: ;
+return;
+}
+
+/* Bcc.L #.L (PL) */
+void REGPARAM2 CPUFUNC(op_6aff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211190;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211190: ;
+return;
+}
+
+/* Bcc.W #.W (MI) */
+void REGPARAM2 CPUFUNC(op_6b00_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211191;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211191: ;
+return;
+}
+
+/* BccQ.B # (MI) */
+void REGPARAM2 CPUFUNC(op_6b01_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211192;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211192: ;
+return;
+}
+
+/* Bcc.L #.L (MI) */
+void REGPARAM2 CPUFUNC(op_6bff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211193;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211193: ;
+return;
+}
+
+/* Bcc.W #.W (GE) */
+void REGPARAM2 CPUFUNC(op_6c00_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211194;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211194: ;
+return;
+}
+
+/* BccQ.B # (GE) */
+void REGPARAM2 CPUFUNC(op_6c01_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211195;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211195: ;
+return;
+}
+
+/* Bcc.L #.L (GE) */
+void REGPARAM2 CPUFUNC(op_6cff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211196;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211196: ;
+return;
+}
+
+/* Bcc.W #.W (LT) */
+void REGPARAM2 CPUFUNC(op_6d00_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211197;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211197: ;
+return;
+}
+
+/* BccQ.B # (LT) */
+void REGPARAM2 CPUFUNC(op_6d01_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211198;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211198: ;
+return;
+}
+
+/* Bcc.L #.L (LT) */
+void REGPARAM2 CPUFUNC(op_6dff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211199;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211199: ;
+return;
+}
+
+/* Bcc.W #.W (GT) */
+void REGPARAM2 CPUFUNC(op_6e00_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211200;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211200: ;
+return;
+}
+
+/* BccQ.B # (GT) */
+void REGPARAM2 CPUFUNC(op_6e01_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211201;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211201: ;
+return;
+}
+
+/* Bcc.L #.L (GT) */
+void REGPARAM2 CPUFUNC(op_6eff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211202;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211202: ;
+return;
+}
+
+/* Bcc.W #.W (LE) */
+void REGPARAM2 CPUFUNC(op_6f00_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211203;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_211203: ;
+return;
+}
+
+/* BccQ.B # (LE) */
+void REGPARAM2 CPUFUNC(op_6f01_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211204;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_211204: ;
+return;
+}
+
+/* Bcc.L #.L (LE) */
+void REGPARAM2 CPUFUNC(op_6fff_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+	/* OP zero */
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_211205;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_020 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_211205: ;
+return;
+}
+
+/* MOVEQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_7000_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_u32 src = srcreg;
+{	/* op H:2,T:0,C:-2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* OR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8000_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* No EA */
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_8010_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_8018_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_8020_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_8028_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_8030_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* OR.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_8038_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_8039_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_803a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_803b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* OR.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_803c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8040_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_8050_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_8058_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_8060_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_8068_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_8070_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* OR.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_8078_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_8079_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_807a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_807b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* OR.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_807c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8080_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_8090_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_8098_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_80a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_80a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* OR.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_80b8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_80b9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_80ba_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80bb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* OR.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_80bc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* DIVU.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_80c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:52 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_211240;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (52);
+}}}l_211240: ;
+return;
+}
+
+/* DIVU.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_80d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_211241;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	do_cycles_ce020_internal (52);
+}}}}l_211241: ;
+return;
+}
+
+/* DIVU.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_80d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_211242;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	do_cycles_ce020_internal (52);
+}}}}l_211242: ;
+return;
+}
+
+/* DIVU.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_80e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_211243;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	do_cycles_ce020_internal (52);
+}}}}l_211243: ;
+return;
+}
+
+/* DIVU.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_80e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_211244;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	do_cycles_ce020_internal (52);
+}}}}l_211244: ;
+return;
+}
+
+/* DIVU.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_211245;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	do_cycles_ce020_internal (52);
+}}}}}l_211245: ;
+return;
+}
+
+/* DIVU.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_80f8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_211246;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	do_cycles_ce020_internal (52);
+}}}}l_211246: ;
+return;
+}
+
+/* DIVU.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_80f9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_211247;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (6);
+	}
+	do_cycles_ce020_internal (52);
+}}}}l_211247: ;
+return;
+}
+
+/* DIVU.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_80fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_211248;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	do_cycles_ce020_internal (52);
+}}}}l_211248: ;
+return;
+}
+
+/* DIVU.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_211249;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	do_cycles_ce020_internal (52);
+}}}}}l_211249: ;
+return;
+}
+
+/* DIVU.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_80fc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_211250;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	do_cycles_ce020_internal (52);
+}}}l_211250: ;
+return;
+}
+
+/* SBCD.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8100_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:0,T:0,C:4 */
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SBCD.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_8108_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:10 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:10 */
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (11);
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_8110_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_8118_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_8120_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_8128_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_8130_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* OR.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_8138_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_8139_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* PACK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_8140_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+{	uae_u16 val = m68k_dreg (regs, srcreg) + get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);
+	regs.irc = get_word_ce020_prefetch (4);
+}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* PACK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_8148_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+{	uae_u16 val;
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (val | ((uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff) << 8)) + get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) -= areg_byteinc[dstreg];
+	x_put_byte (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));
+	regs.irc = get_word_ce020_prefetch (4);
+}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* OR.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_8150_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_8158_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_8160_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_8168_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_8170_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* OR.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_8178_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_8179_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* UNPK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_8180_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+{	uae_u16 val = m68k_dreg (regs, srcreg);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);
+	regs.irc = get_word_ce020_prefetch (4);
+}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* UNPK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_8188_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+{	uae_u16 val;
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];
+	x_put_byte (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);
+	x_put_byte (m68k_areg (regs, dstreg), val >> 8);
+	regs.irc = get_word_ce020_prefetch (4);
+}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* OR.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_8190_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_8198_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_81a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_81a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_81b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* OR.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_81b8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_81b9_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* DIVS.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_81c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:52 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_211278;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	regs.irc = get_word_ce020_prefetch (0);
+	do_cycles_ce020_internal (52);
+}}}l_211278: ;
+return;
+}
+
+/* DIVS.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_81d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_211279;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	do_cycles_ce020_internal (52);
+}}}}l_211279: ;
+return;
+}
+
+/* DIVS.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_81d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_211280;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	do_cycles_ce020_internal (52);
+}}}}l_211280: ;
+return;
+}
+
+/* DIVS.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_81e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_211281;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	do_cycles_ce020_internal (52);
+}}}}l_211281: ;
+return;
+}
+
+/* DIVS.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_81e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_211282;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	do_cycles_ce020_internal (52);
+}}}}l_211282: ;
+return;
+}
+
+/* DIVS.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_81f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_211283;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	do_cycles_ce020_internal (52);
+}}}}}l_211283: ;
+return;
+}
+
+/* DIVS.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_81f8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_211284;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	do_cycles_ce020_internal (52);
+}}}}l_211284: ;
+return;
+}
+
+/* DIVS.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_81f9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_211285;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (6);
+	do_cycles_ce020_internal (52);
+}}}}l_211285: ;
+return;
+}
+
+/* DIVS.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_81fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_211286;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	do_cycles_ce020_internal (52);
+}}}}l_211286: ;
+return;
+}
+
+/* DIVS.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_81fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_211287;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	do_cycles_ce020_internal (52);
+}}}}}l_211287: ;
+return;
+}
+
+/* DIVS.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_81fc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_211288;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	do_cycles_ce020_internal (52);
+}}}l_211288: ;
+return;
+}
+
+/* SUB.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9000_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_9010_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_9018_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_9020_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_9028_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_9030_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return;
+}
+
+/* SUB.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_9038_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_9039_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_903a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_903b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return;
+}
+
+/* SUB.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_903c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9040_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W An,Dn */
+void REGPARAM2 CPUFUNC(op_9048_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_9050_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_9058_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_9060_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_9068_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_9070_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return;
+}
+
+/* SUB.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_9078_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_9079_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_907a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_907b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return;
+}
+
+/* SUB.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_907c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9080_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L An,Dn */
+void REGPARAM2 CPUFUNC(op_9088_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_9090_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_9098_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_90a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_90a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_90b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return;
+}
+
+/* SUB.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_90b8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_90b9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_90ba_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_90bb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return;
+}
+
+/* SUB.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_90bc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_90c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W An,An */
+void REGPARAM2 CPUFUNC(op_90c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* No EA */
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W (An),An */
+void REGPARAM2 CPUFUNC(op_90d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_90d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_90e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_90e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_90f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* SUBA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_90f8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_90f9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_90fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_90fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* SUBA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_90fc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBX.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9100_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBX.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_9108_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:6 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:6 */
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (7);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_9110_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_9118_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_9120_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_9128_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_9130_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_9138_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_9139_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBX.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9140_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBX.W -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_9148_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:6 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:6 */
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (7);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_9150_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_9158_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_9160_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_9168_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_9170_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_9178_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_9179_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBX.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9180_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBX.L -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_9188_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:6 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:6 */
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (7);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_9190_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_9198_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_91a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_91a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_91b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_91b8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_91b9_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_91c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L An,An */
+void REGPARAM2 CPUFUNC(op_91c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* No EA */
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L (An),An */
+void REGPARAM2 CPUFUNC(op_91d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_91d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_91e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_91e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_91f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* SUBA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_91f8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_91f9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_91fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_91fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* SUBA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_91fc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b000_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* No EA */
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_b010_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_b018_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_b020_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_b028_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b030_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_b038_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_b039_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_b03a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b03b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_b03c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b040_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W An,Dn */
+void REGPARAM2 CPUFUNC(op_b048_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* No EA */
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_b050_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_b058_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_b060_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_b068_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b070_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_b078_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_b079_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_b07a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b07b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_b07c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b080_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.L An,Dn */
+void REGPARAM2 CPUFUNC(op_b088_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* No EA */
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_b090_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_b098_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_b0a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+
+#ifdef PART_7
+/* CMP.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_b0a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b0b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_b0b8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_b0b9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_b0ba_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b0bb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_b0bc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMPA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_b0c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W An,An */
+void REGPARAM2 CPUFUNC(op_b0c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* No EA */
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W (An),An */
+void REGPARAM2 CPUFUNC(op_b0d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_b0d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_b0e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_b0e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_b0f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}}return;
+}
+
+/* CMPA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_b0f8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_b0f9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMPA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_b0fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_b0fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}}return;
+}
+
+/* CMPA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_b0fc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b100_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* No EA */
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPM.B (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_b108_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+{	/* No EA */
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	/* op H:0,T:0,C:8 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (6);
+}}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_b110_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_b118_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_b120_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_b128_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_b130_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* EOR.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_b138_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_b139_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b140_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPM.W (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_b148_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+{	/* No EA */
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	/* op H:0,T:0,C:8 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (6);
+}}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_b150_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_b158_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_b160_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_b168_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_b170_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* EOR.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_b178_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_b179_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b180_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPM.L (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_b188_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+{	/* No EA */
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	/* op H:0,T:0,C:8 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (6);
+}}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_b190_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_b198_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_b1a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_b1a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_b1b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* EOR.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_b1b8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_b1b9_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMPA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_b1c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L An,An */
+void REGPARAM2 CPUFUNC(op_b1c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* No EA */
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L (An),An */
+void REGPARAM2 CPUFUNC(op_b1d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_b1d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_b1e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_b1e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_b1f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}}return;
+}
+
+/* CMPA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_b1f8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_b1f9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMPA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_b1fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_b1fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}}return;
+}
+
+/* CMPA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_b1fc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c000_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:0 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_c010_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c018_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c020_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c028_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c030_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* AND.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c038_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c039_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c03a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c03b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* AND.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_c03c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c040_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:0 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_c050_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c058_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c060_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c068_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c070_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* AND.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c078_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c079_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c07a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c07b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* AND.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_c07c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c080_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:0 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_c090_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c098_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c0a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c0a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* AND.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c0b8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c0b9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c0ba_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0bb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* AND.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_c0bc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MULU.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c0c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MULU.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_c0d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MULU.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c0d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MULU.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c0e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MULU.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c0e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MULU.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* MULU.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c0f8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MULU.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c0f9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (6);
+}}}}}return;
+}
+
+/* MULU.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c0fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MULU.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* MULU.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_c0fc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* ABCD.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c100_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:0,T:0,C:4 */
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ABCD.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_c108_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:10 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:10 */
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (11);
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_c110_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_c118_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_c120_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_c128_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_c130_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* AND.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_c138_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_c139_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EXG.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c140_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* EXG.L An,An */
+void REGPARAM2 CPUFUNC(op_c148_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+{	/* No EA */
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_c150_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_c158_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_c160_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_c168_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_c170_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* AND.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_c178_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_c179_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EXG.L Dn,An */
+void REGPARAM2 CPUFUNC(op_c188_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_c190_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_c198_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_c1a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_c1a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_c1b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* AND.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_c1b8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_c1b9_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* MULS.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c1c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* MULS.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_c1d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* MULS.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c1d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* MULS.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c1e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* MULS.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c1e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* MULS.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c1f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* MULS.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c1f8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* MULS.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c1f9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* MULS.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c1fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* MULS.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c1fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* MULS.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_c1fc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d000_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_d010_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_d018_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_d020_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_d028_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d030_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return;
+}
+
+/* ADD.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_d038_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_d039_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_d03a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d03b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return;
+}
+
+/* ADD.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_d03c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = (uae_u8)get_word_ce020_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d040_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W An,Dn */
+void REGPARAM2 CPUFUNC(op_d048_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_d050_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_d058_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_d060_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_d068_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d070_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return;
+}
+
+/* ADD.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_d078_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_d079_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_d07a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d07b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return;
+}
+
+/* ADD.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_d07c_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d080_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L An,Dn */
+void REGPARAM2 CPUFUNC(op_d088_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_d090_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_d098_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_d0a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_d0a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d0b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return;
+}
+
+/* ADD.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_d0b8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_d0b9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_d0ba_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d0bb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return;
+}
+
+/* ADD.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_d0bc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_d0c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W An,An */
+void REGPARAM2 CPUFUNC(op_d0c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* No EA */
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W (An),An */
+void REGPARAM2 CPUFUNC(op_d0d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_d0d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_d0e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_d0e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_d0f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* ADDA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_d0f8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_d0f9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_d0fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_d0fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* ADDA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_d0fc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce020_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDX.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d100_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDX.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_d108_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:6 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:6 */
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (7);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_d110_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_d118_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_d120_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_d128_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_d130_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_d138_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_d139_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDX.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d140_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDX.W -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_d148_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:6 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:6 */
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (7);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_d150_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_d158_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_d160_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_d168_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_d170_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_d178_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_d179_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDX.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d180_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDX.L -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_d188_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:6 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:6 */
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (7);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_d190_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_d198_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_d1a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_d1a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_d1b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_d1b8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_d1b9_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (2);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_d1c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L An,An */
+void REGPARAM2 CPUFUNC(op_d1c8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* No EA */
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_ce020_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L (An),An */
+void REGPARAM2 CPUFUNC(op_d1d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_d1d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_d1e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_d1e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_d1f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* ADDA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_d1f8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_d1f9_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_d1fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_d1fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* ADDA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_d1fc_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce020_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ASRQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e000_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:4 */
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e008_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e010_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e018_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e020_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e028_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e030_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e038_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e040_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+
+#ifdef PART_8
+/* LSRQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e048_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e050_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e058_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e060_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e068_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e070_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e078_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e080_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:4 */
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e088_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e090_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e098_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0b8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (6);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRW.W (An) */
+void REGPARAM2 CPUFUNC(op_e0d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e0d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e0e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e0e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ASRW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e0f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ASRW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e0f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ASRW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e0f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ASLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e100_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:4 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e108_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e110_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e118_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e120_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e128_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e130_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e138_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e140_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e148_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e150_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e158_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e160_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e168_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e170_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e178_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e180_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:4 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e188_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e190_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e198_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1a0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1a8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1b0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1b8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce020_prefetch (2);
+	do_cycles_ce020_internal (6);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e1d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e1d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e1e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e1e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ASLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e1f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ASLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e1f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ASLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e1f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* LSRW.W (An) */
+void REGPARAM2 CPUFUNC(op_e2d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e2d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e2e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e2e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* LSRW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e2f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* LSRW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e2f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* LSRW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e2f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* LSLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e3d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e3d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e3e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e3e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* LSLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e3f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* LSLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e3f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* LSLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e3f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ROXRW.W (An) */
+void REGPARAM2 CPUFUNC(op_e4d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e4d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e4e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e4e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROXRW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e4f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ROXRW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e4f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROXRW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e4f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ROXLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e5d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e5d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e5e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e5e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROXLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e5f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ROXLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e5f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROXLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e5f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* RORW.W (An) */
+void REGPARAM2 CPUFUNC(op_e6d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e6d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e6e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e6e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* RORW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e6f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* RORW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e6f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* RORW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e6f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ROLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e7d0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e7d8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e7e0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce020_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e7e8_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e7f0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ROLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e7f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e7f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce020_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce020_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BFTST.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8c0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8d0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8e8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8f0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce020_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce020 (tmppc, 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFEXTU.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9c0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9d0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9e8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9f0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9f8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9f9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9fa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9fb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce020 (tmppc, 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFCHG.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eac0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFCHG.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ead0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFCHG.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eae8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFCHG.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eaf0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eaf8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eaf9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebc0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebd0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebe8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebf0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebf8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebf9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebfa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebfb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce020 (tmppc, 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFCLR.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecc0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFCLR.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecd0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFCLR.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ece8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFCLR.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecf0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecf8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecf9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edc0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edd0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ede8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edf0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edf8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edf9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce020_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edfa_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edfb_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce020 (tmppc, 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFSET.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eec0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFSET.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eed0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFSET.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eee8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFSET.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eef0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eef8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eef9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFINS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_efc0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFINS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_efd0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFINS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_efe8_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFINS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eff0_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce020 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eff8_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eff9_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce020_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce020_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* FPP.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f200_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_211788;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211788: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f208_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_211789;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211789: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f210_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_211790;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211790: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f218_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_211791;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211791: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f220_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_211792;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211792: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f228_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_211793;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211793: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f230_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_211794;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211794: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f238_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_211795;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211795: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f239_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_211796;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211796: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f23a_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_211797;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211797: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f23b_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_211798;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211798: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f23c_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_211799;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211799: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f240_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_211800;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211800: ;
+return;
+}
+
+#endif
+/* FDBcc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f248_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 105;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_dbcc (opcode, extra);
+	if (regs.fp_exception) goto l_211801;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_211801;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211801: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f250_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_211802;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211802: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f258_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_211803;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211803: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f260_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_211804;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211804: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f268_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_211805;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211805: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f270_21)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_211806;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211806: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f278_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_211807;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211807: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f279_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce020_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_211808;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211808: ;
+return;
+}
+
+#endif
+/* FTRAPcc.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f27a_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_word_ce020_prefetch (2);
+{	uae_s16 dummy = get_word_ce020_prefetch (4);
+	/* OP zero */
+	m68k_incpci (6);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_211809;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211809: ;
+return;
+}
+
+#endif
+/* FTRAPcc.L #.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f27b_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_word_ce020_prefetch (2);
+{	uae_s32 dummy;
+	dummy = get_long_ce020_prefetch (4);
+	/* OP zero */
+	m68k_incpci (8);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_211810;
+	regs.irc = get_word_ce020_prefetch (0);
+}
+#endif
+}l_211810: ;
+return;
+}
+
+#endif
+/* FTRAPcc.L  */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f27c_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_word_ce020_prefetch (2);
+	m68k_incpci (4);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_211811;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}l_211811: ;
+return;
+}
+
+#endif
+/* FBccQ.L #,#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f280_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s16 extra = get_word_ce020_prefetch (0);
+	/* OP zero */
+	m68k_incpci (2);
+	fpuop_bcc (opcode, pc,extra);
+	if (regs.fp_exception) goto l_211812;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_211812;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}
+#endif
+}l_211812: ;
+return;
+}
+
+#endif
+/* FBccQ.L #,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f2c0_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s32 extra;
+	extra = get_long_ce020_prefetch (0);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_bcc (opcode, pc,extra);
+	if (regs.fp_exception) goto l_211813;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_211813;
+	}
+	regs.irc = get_word_ce020_prefetch (0);
+}}
+#endif
+}l_211813: ;
+return;
+}
+
+#endif
+/* FSAVE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f310_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_211814; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_211814;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}}l_211814: ;
+return;
+}
+
+#endif
+/* FSAVE.L -(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f320_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_211815; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_211815;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}}l_211815: ;
+return;
+}
+
+#endif
+/* FSAVE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f328_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_211816; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_211816;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}}l_211816: ;
+return;
+}
+
+#endif
+/* FSAVE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f330_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_211817; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_211817;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}}l_211817: ;
+return;
+}
+
+#endif
+/* FSAVE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f338_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_211818; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_211818;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}}l_211818: ;
+return;
+}
+
+#endif
+/* FSAVE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f339_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_211819; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_211819;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}}l_211819: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f350_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_211820; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_211820;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}}l_211820: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f358_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_211821; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_211821;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}}l_211821: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f368_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_211822; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_211822;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}}l_211822: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f370_21)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_211823; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_211823;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}}l_211823: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f378_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_211824; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_211824;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}}l_211824: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f379_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_211825; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_211825;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}}l_211825: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f37a_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_211826; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_211826;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}}l_211826: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f37b_21)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_211827; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_211827;
+	regs.irc = get_word_ce020_prefetch (0);
+
+#endif
+}}l_211827: ;
+return;
+}
+
+#endif
+#endif
+
diff --git a/src/cpu/cpuemu_22.c b/src/cpu/cpuemu_22.c
new file mode 100644
index 0000000..d0f8473
--- /dev/null
+++ b/src/cpu/cpuemu_22.c
@@ -0,0 +1,39689 @@
+#include "main.h"
+#include "sysdeps.h"
+#include "hatari-glue.h"
+#include "maccess.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "cputbl.h"
+#define CPUFUNC(x) x##_ff
+#define SET_CFLG_ALWAYS(x) SET_CFLG(x)
+#define SET_NFLG_ALWAYS(x) SET_NFLG(x)
+#ifdef NOFLAGS
+#include "noflags.h"
+#endif
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0000_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0010_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0018_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0020_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0028_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0030_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0038_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0039_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_003c_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_word_030_prefetch (2);
+	src &= 0xFF;
+	regs.sr |= src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0040_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0050_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0058_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0060_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0068_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0070_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0078_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0079_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_007c_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220018; }
+{	MakeSR ();
+{	uae_s16 src = get_word_030_prefetch (2);
+	regs.sr |= src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220018: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0080_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0090_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0098_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_00b0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_00b8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_00b9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (10);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00d0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220027; }
+}
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220027: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00e8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220028; }
+}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220028: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220029; }
+}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220029: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220030; }
+}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220030: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220031; }
+}
+	regs.irc = get_word_030_prefetch (8);
+}}}	m68k_incpci (8);
+l_220031: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220032; }
+}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220032: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220033; }
+}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220033: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BTST.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0100_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPMR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0108_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 8;  
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_u16 val;
+	MovepByteNbr=1; val = ((x_get_byte (memp) & 0xff) << 8);
+	MovepByteNbr=2; val += (x_get_byte (memp + 2) & 0xff);
+	MovepByteNbr=0;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0110_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (2);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0118_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (2);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0120_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (2);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0128_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0130_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0138_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0139_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_013a_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 2;
+	dsta += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_013b_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,#.B */
+uae_u32 REGPARAM2 CPUFUNC(op_013c_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = (uae_u8)get_word_030_prefetch (2);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0140_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPMR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0148_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 16; 
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_u32 val;
+	MovepByteNbr=1; val = ((x_get_byte (memp) & 0xff) << 24);
+	MovepByteNbr=2; val += ((x_get_byte (memp + 2) & 0xff) << 16);
+	MovepByteNbr=3; val += ((x_get_byte (memp + 4) & 0xff) << 8);
+	MovepByteNbr=4; val += (x_get_byte (memp + 6) & 0xff);
+	MovepByteNbr=0;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0150_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0158_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0160_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0168_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0170_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0178_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0179_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0180_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPRM.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0188_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	MovepByteNbr=1; 	x_put_byte (memp, src >> 8);
+	MovepByteNbr=2; 	x_put_byte (memp + 2, src);
+	MovepByteNbr=0;
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0190_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0198_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01b8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01b9_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_01c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPRM.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	MovepByteNbr=1; 	x_put_byte (memp, src >> 24);
+	MovepByteNbr=2; 	x_put_byte (memp + 2, src >> 16);
+	MovepByteNbr=3; 	x_put_byte (memp + 4, src >> 8);
+	MovepByteNbr=4; 	x_put_byte (memp + 6, src);
+	MovepByteNbr=0;
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_01d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01f8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01f9_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0200_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0210_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0218_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0220_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0228_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0230_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0238_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0239_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ANDSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_023c_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_word_030_prefetch (2);
+	src |= 0xFF00;
+	regs.sr &= src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0240_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0250_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0258_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0260_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0268_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0270_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0278_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0279_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ANDSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_027c_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220090; }
+{	MakeSR ();
+{	uae_s16 src = get_word_030_prefetch (2);
+	regs.sr &= src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220090: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0280_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0290_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0298_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_02b0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_02b8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_02b9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (10);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02d0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220099; }
+}
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220099: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02e8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220100; }
+}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220100: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220101; }
+}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220101: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220102; }
+}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220102: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220103; }
+}
+	regs.irc = get_word_030_prefetch (8);
+}}}	m68k_incpci (8);
+l_220103: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220104; }
+}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220104: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220105; }
+}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220105: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0400_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0410_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0418_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0420_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0428_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0430_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0438_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0439_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0440_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0450_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0458_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0460_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0468_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0470_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0478_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0479_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0480_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0490_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0498_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_04b0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_04b8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_04b9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (10);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04d0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220130; }
+}
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220130: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04e8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220131; }
+}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220131: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220132; }
+}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220132: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220133; }
+}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220133: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220134; }
+}
+	regs.irc = get_word_030_prefetch (8);
+}}}	m68k_incpci (8);
+l_220134: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220135; }
+}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220135: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_220136; }
+}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220136: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0600_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0610_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0618_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0620_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0628_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0630_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0638_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0639_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0640_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0650_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0658_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0660_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0668_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0670_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0678_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0679_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0680_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0690_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0698_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_06b0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_06b8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_06b9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (10);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RTM.L Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_030_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* RTM.L An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_030_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_030_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_030_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_030_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_030_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_030_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_030_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_030_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BTST.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0800_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0810_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0818_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0820_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0828_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0830_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0838_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0839_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (8);
+}}}}	m68k_incpci (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_083a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_083b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0840_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0850_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0858_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0860_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0868_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0870_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0878_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0879_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0880_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0890_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0898_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08b0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08b8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08b9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_08c0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08d0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_08d8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08f0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a00_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a10_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a18_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a20_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a28_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a30_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a38_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a39_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a3c_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_word_030_prefetch (2);
+	src &= 0xFF;
+	regs.sr ^= src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a40_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a50_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a58_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a60_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a68_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a70_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a78_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a79_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a7c_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220221; }
+{	MakeSR ();
+{	uae_s16 src = get_word_030_prefetch (2);
+	regs.sr ^= src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220221: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a80_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a90_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a98_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (10);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CAS.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ad0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ad8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ae0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ae8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
+#ifdef PART_2
+/* CAS.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (0);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (8);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c00_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c10_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c18_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c20_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c28_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c30_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c38_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c39_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (8);
+}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c3a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.B #.B,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c3b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c40_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c50_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c58_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c60_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c68_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c70_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c78_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c79_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (8);
+}}}}}}}	m68k_incpci (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c7a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c7b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c80_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c90_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c98_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (8);
+}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (8);
+}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (10);
+}}}}}}}	m68k_incpci (10);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cba_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 6;
+	dsta += (uae_s32)(uae_s16)get_word_030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (8);
+}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.L #.L,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cbb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (6);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cd0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cd8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ce0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ce8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (0);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (8);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (8);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS2.W #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cfc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 extra;
+	extra = get_long_030_prefetch (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u16 dst1 = x_get_word (rn1), dst2 = x_get_word (rn2);
+{uae_u32 newv = ((uae_u16)(dst1)) - ((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s16)(dst1)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u16)(dst2)) - ((uae_u16)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s16)(dst2)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, extra & 7))) > ((uae_u16)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	x_put_word (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	x_put_word (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);
+	m68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);
+	}
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e10_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220275; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220275: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e18_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220276; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220276: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e20_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_220277; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220277: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e28_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220278; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220278: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e30_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220279; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	x_put_byte (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}	regs.irc = get_word_030_prefetch (0);
+}}}l_220279: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e38_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220280; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220280: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e39_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220281; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_long_030_prefetch (4);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_030_prefetch (8);
+}}}	m68k_incpci (8);
+l_220281: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e50_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220282; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220282: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e58_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220283; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, dstreg) += 2;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220283: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e60_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_220284; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220284: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e68_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220285; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220285: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e70_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220286; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	x_put_word (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}	regs.irc = get_word_030_prefetch (0);
+}}}l_220286: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e78_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220287; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220287: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e79_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220288; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_long_030_prefetch (4);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_030_prefetch (8);
+}}}	m68k_incpci (8);
+l_220288: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e90_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_220289; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220289: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e98_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_220290; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, dstreg) += 4;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220290: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ea0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_220291; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220291: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ea8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_220292; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220292: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_220293; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	x_put_long (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}	regs.irc = get_word_030_prefetch (0);
+}}}l_220293: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_220294; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+l_220294: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_220295; }
+{{	uae_s16 extra = get_word_030_prefetch (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_long_030_prefetch (4);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_030_prefetch (8);
+}}}	m68k_incpci (8);
+l_220295: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ed0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (4);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ed8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (4);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ee0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (4);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ee8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (6);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (0);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (6);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_030_prefetch (8);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS2.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0efc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 extra;
+	extra = get_long_030_prefetch (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u32 dst1 = x_get_long (rn1), dst2 = x_get_long (rn2);
+{uae_u32 newv = ((uae_u32)(dst1)) - ((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s32)(dst1)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u32)(dst2)) - ((uae_u32)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s32)(dst2)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, extra & 7))) > ((uae_u32)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	x_put_long (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	x_put_long (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = dst2;
+	m68k_dreg (regs, (extra >> 22) & 7) = dst1;
+	}
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1000_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1010_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1018_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1020_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1028_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1030_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1038_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1039_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (6);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1080_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1090_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1098_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10ba_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1100_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1110_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1118_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1120_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1128_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1130_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1138_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1139_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1140_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1150_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1158_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1160_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1168_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1170_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1178_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1179_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1180_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1190_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1198_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11ba_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (10);
+	x_put_byte (dsta, src);
+	m68k_incpci (10);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2000_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2008_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2010_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2018_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2020_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2028_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2030_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2038_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2039_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2040_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2048_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2050_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2058_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2060_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2068_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2070_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_030_prefetch (0);
+	m68k_areg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2078_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2079_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_030_prefetch (6);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_030_prefetch (0);
+	m68k_areg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_207c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	regs.irc = get_word_030_prefetch (6);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2080_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2088_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2090_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2098_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20ba_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2100_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2108_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2110_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2118_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2120_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2128_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2130_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2138_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2139_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2140_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2148_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2150_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2158_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2160_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2168_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2170_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2178_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2179_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2180_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2188_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2190_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2198_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_3
+/* MOVE.L -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21ba_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (10);
+	x_put_long (dsta, src);
+	m68k_incpci (10);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (10);
+	x_put_long (dsta, src);
+	m68k_incpci (10);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3000_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3008_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3010_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3018_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3020_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3028_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3030_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3038_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3039_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (6);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3040_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3048_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3050_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3058_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3060_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3068_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3070_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_030_prefetch (0);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3078_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3079_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_030_prefetch (6);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (6);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_030_prefetch (0);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_307c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3080_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3088_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3090_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3098_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30ba_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3100_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3108_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3110_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3118_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3120_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3128_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3130_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3138_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3139_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3140_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3148_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3150_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3158_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3160_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3168_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3170_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3178_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3179_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3180_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3188_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3190_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3198_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31ba_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (10);
+	x_put_word (dsta, src);
+	m68k_incpci (10);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (8);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4000_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4010_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4018_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4020_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4028_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4030_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4038_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4039_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4040_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4050_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4058_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4060_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4068_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4070_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (srca, newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4078_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4079_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4080_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4090_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4098_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (srca, newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40b8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40b9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_40c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_220632; }
+{{	MakeSR ();
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}}	m68k_incpci (2);
+l_220632: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_220633; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_220633: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_40d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_220634; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_220634: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{if (!regs.s) { Exception (8); goto l_220635; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_220635: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_220636; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	MakeSR ();
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_220636: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_220637; }
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (srca, regs.sr);
+}}}}l_220637: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_220638; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	MakeSR ();
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_220638: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_220639; }
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+	MakeSR ();
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (6);
+l_220639: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CHK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4100_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220640;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220640;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}l_220640: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4110_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220641;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220641;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220641: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (An)+,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4118_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220642;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220642;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220642: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L -(An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4120_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220643;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220643;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220643: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d16,An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4128_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220644;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220644;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220644: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d8,An,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4130_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220645;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220645;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}}l_220645: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (xxx).W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4138_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220646;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220646;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220646: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (xxx).L,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4139_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220647;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220647;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220647: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d16,PC),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220648;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220648;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220648: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d8,PC,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220649;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220649;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}}l_220649: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L #.L,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220650;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220650;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}l_220650: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4180_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220651;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220651;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}l_220651: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4190_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220652;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220652;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220652: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4198_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220653;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220653;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220653: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220654;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220654;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220654: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220655;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220655;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220655: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220656;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220656;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}}l_220656: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220657;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220657;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220657: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220658;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220658;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220658: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41ba_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220659;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220659;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220659: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220660;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220660;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}}l_220660: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_220661;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_220661;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}l_220661: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	regs.irc = get_word_030_prefetch (0);
+	m68k_areg (regs, dstreg) = (srca);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	regs.irc = get_word_030_prefetch (6);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	regs.irc = get_word_030_prefetch (0);
+	m68k_areg (regs, dstreg) = (srca);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4200_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4210_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4218_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4220_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4228_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4230_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, 0);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4238_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4239_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4240_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4250_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4258_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4260_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4268_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (srca, 0);
+}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4270_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (srca, 0);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4278_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (srca, 0);
+}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4279_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (srca, 0);
+}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4280_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4290_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4298_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (srca, 0);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_42b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (srca, 0);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_42b8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (srca, 0);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_42b9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (srca, 0);
+}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	MakeSR ();
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	MakeSR ();
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (srca, regs.sr & 0xff);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	MakeSR ();
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+	MakeSR ();
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* NEG.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4400_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_4
+/* NEG.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4410_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4418_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4420_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4428_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4430_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, dst);
+}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4438_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4439_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4440_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4450_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4458_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4460_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4468_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4470_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (srca, dst);
+}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4478_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4479_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4480_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4490_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4498_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (srca, dst);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44b8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44b9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_44c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (2);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_44d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B #.B */
+uae_u32 REGPARAM2 CPUFUNC(op_44fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4600_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4610_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4618_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4620_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4628_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4630_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4638_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4639_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4640_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4650_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4658_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4660_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4668_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4670_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (srca, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4678_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4679_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4680_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4690_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4698_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (srca, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46b8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46b9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_46c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_220760; }
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+l_220760: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220761; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (2);
+}}}}	m68k_incpci (2);
+l_220761: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_46d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220762; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (2);
+}}}}	m68k_incpci (2);
+l_220762: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_220763; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (2);
+}}}}	m68k_incpci (2);
+l_220763: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220764; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+l_220764: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220765; }
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (0);
+}}}}}l_220765: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220766; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+l_220766: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220767; }
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+l_220767: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220768; }
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+l_220768: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220769; }
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (0);
+}}}}}l_220769: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_46fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220770; }
+{{	uae_s16 src = get_word_030_prefetch (2);
+	regs.sr = src;
+	MakeFromSR();
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+l_220770: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4800_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LINK.L An,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4808_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 8;  
+{{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 offs;
+	offs = get_long_030_prefetch (2);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (olda, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* NBCD.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4810_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4818_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4820_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4828_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4830_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, newv);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4838_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4839_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SWAP.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4840_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 34;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BKPTQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4848_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 99;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_030_prefetch (0);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PEA.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4850_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4868_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4870_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, srca);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4878_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4879_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_487a_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_487b_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, srca);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* EXT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4880_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u16 dst = (uae_s16)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4890_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 6;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	int type = get_cpu_model () >= 68020;
+	while (amask) {
+		srca -= 2;
+		if (!type || movem_index2[amask] != dstreg)
+			x_put_word (srca, m68k_areg (regs, movem_index2[amask]));
+		else
+			x_put_word (srca, m68k_areg (regs, movem_index2[amask]) - 2);
+		amask = movem_next[amask];
+	}
+	while (dmask) { srca -= 2; x_put_word (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48b0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_030_prefetch (0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48b8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48b9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+{	uaecptr srca;
+	srca = get_long_030_prefetch (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_030_prefetch (8);
+}}}	m68k_incpci (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EXT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_48c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48d0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 10; 
+{	uae_u16 mask = get_word_030_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	int type = get_cpu_model () >= 68020;
+	while (amask) {
+		srca -= 4;
+		if (!type || movem_index2[amask] != dstreg)
+			x_put_long (srca, m68k_areg (regs, movem_index2[amask]));
+		else
+			x_put_long (srca, m68k_areg (regs, movem_index2[amask]) - 4);
+		amask = movem_next[amask];
+	}
+	while (dmask) { srca -= 4; x_put_long (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48f0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_030_prefetch (0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+{	uaecptr srca;
+	srca = get_long_030_prefetch (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_030_prefetch (8);
+}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXT.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_49c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a00_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a10_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a18_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a20_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a28_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a30_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a38_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a39_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3a_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3b_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B #.B */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3c_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a40_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a48_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a50_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a58_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a60_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a68_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a70_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a78_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a79_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7a_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7b_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7c_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a80_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.L An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a88_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a90_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a98_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4aba_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4abb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4abc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TAS.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4ac0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((src) & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, src);
+}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4af0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, src);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4af8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, src);
+}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4af9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, src);
+}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MULL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c00_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_220847;
+	regs.irc = get_word_030_prefetch (0);
+}}}l_220847: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c10_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_220848;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220848: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c18_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_220849;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220849: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c20_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_220850;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220850: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c28_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_220851;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220851: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c30_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_220852;
+	regs.irc = get_word_030_prefetch (0);
+}}}}}l_220852: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c38_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_220853;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220853: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c39_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_220854;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220854: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_220855;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220855: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_220856;
+	regs.irc = get_word_030_prefetch (0);
+}}}}}l_220856: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3c_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uae_s32 dst;
+	dst = get_long_030_prefetch (4);
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_220857;
+	regs.irc = get_word_030_prefetch (0);
+}}}l_220857: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c40_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_220858;
+	regs.irc = get_word_030_prefetch (0);
+}}}l_220858: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c50_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_220859;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220859: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c58_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_220860;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220860: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c60_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_220861;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220861: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c68_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_220862;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220862: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c70_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_220863;
+	regs.irc = get_word_030_prefetch (0);
+}}}}}l_220863: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c78_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_220864;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220864: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c79_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_220865;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220865: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_220866;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_220866: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_220867;
+	regs.irc = get_word_030_prefetch (0);
+}}}}}l_220867: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7c_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uae_s32 dst;
+	dst = get_long_030_prefetch (4);
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_220868;
+	regs.irc = get_word_030_prefetch (0);
+}}}l_220868: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVMEL.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4c90_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4c98_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ca8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_long_030_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_030_prefetch (8);
+}}}	m68k_incpci (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cba_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cbb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_030_prefetch (4);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ce8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_long_030_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_030_prefetch (8);
+}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_030_prefetch (6);
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_word_030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* TRAPQ.L # */
+uae_u32 REGPARAM2 CPUFUNC(op_4e40_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 15);
+	OpcodeFamily = 39;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+	m68k_incpci (2);
+	Exception (src + 32);
+}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* LINK.W An,#.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e50_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 8;  
+{{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (olda, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* UNLK.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e58_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 48;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	m68k_areg (regs, 7) = src;
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7);
+{	uae_s32 old = x_get_long (olda);
+	m68k_areg (regs, 7) += 4;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, srcreg) = (old);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVR2USP.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e60_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 40;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_220888; }
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	regs.usp = src;
+	regs.irc = get_word_030_prefetch (2);
+}}}	m68k_incpci (2);
+l_220888: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVUSP2R.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e68_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 41;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_220889; }
+{{	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, srcreg) = (regs.usp);
+}}}	m68k_incpci (2);
+l_220889: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RESET.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e70_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 42;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_220890; }
+{	cpureset ();
+	m68k_incpci (2);
+	regs.irc = get_word_030_prefetch (0);
+}}l_220890: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOP.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e71_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 43;
+	CurrentInstrCycles = 4;  
+{	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* STOP.L #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e72_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 44;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220892; }
+{{	uae_s16 src = get_word_030_prefetch (2);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_setstopped ();
+	m68k_incpci (4);
+}}}l_220892: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RTE.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e73_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 45;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_220893; }
+{	uae_u16 newsr; uae_u32 newpc;
+	for (;;) {
+		uaecptr a = m68k_areg (regs, 7);
+		uae_u16 sr = x_get_word (a);
+		uae_u32 pc = x_get_long (a + 2);
+		uae_u16 format = x_get_word (a + 2 + 4);
+		int frame = format >> 12;
+		int offset = 8;
+		newsr = sr; newpc = pc;
+		if (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }
+		else if (frame == 0x1) { m68k_areg (regs, 7) += offset; }
+		else if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }
+		else if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }
+		else if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }
+		else if (frame == 0x7) { m68k_areg (regs, 7) += offset + 52; break; }
+		else if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }
+		else if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }
+		else if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }
+		else { m68k_areg (regs, 7) += offset; Exception (14); goto l_220893; }
+		regs.sr = newsr;
+	MakeFromSR();
+}
+	regs.sr = newsr;
+	MakeFromSR();
+	if (newpc & 1) {
+		exception3i (0x4E73, newpc);
+		goto l_220893;
+	}
+	m68k_setpci (newpc);
+	fill_prefetch_030 ();
+}}l_220893: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RTD.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e74_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 46;
+	CurrentInstrCycles = 8;  
+{{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = x_get_long (pca);
+	m68k_areg (regs, 7) += 4;
+{	uae_s16 offs = get_word_030_prefetch (2);
+	m68k_areg (regs, 7) += offs;
+	if (pc & 1) {
+		exception3i (0x4E74, pc);
+		goto l_220894;
+	}
+	m68k_setpci (pc);
+	fill_prefetch_030 ();
+}}}}l_220894: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* RTS.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e75_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 49;
+	CurrentInstrCycles = 8;  
+{	uaecptr pc = m68k_getpci ();
+	m68k_do_rtsi ();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (pc);
+		exception3i (0x4E75, faultpc);
+		goto l_220895;
+	}
+	fill_prefetch_030 ();
+}l_220895: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TRAPV.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e76_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 50;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	if (GET_VFLG ()) {
+		Exception (7);
+		goto l_220896;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}l_220896: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RTR.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e77_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 51;
+	CurrentInstrCycles = 12; 
+{	uaecptr oldpc = m68k_getpci ();
+	MakeSR ();
+{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+{	uae_s16 sr = x_get_word (sra);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = x_get_long (pca);
+	m68k_areg (regs, 7) += 4;
+	regs.sr &= 0xFF00; sr &= 0xFF;
+	regs.sr |= sr;
+	m68k_setpci (pc);
+	MakeFromSR();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (oldpc);
+		exception3i (0x4E77, faultpc);
+		goto l_220897;
+	}
+	fill_prefetch_030 ();
+}}}}}l_220897: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEC2.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7a_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 82;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220898; }
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_movec2(src & 0xFFF, regp)) goto l_220898;
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+l_220898: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE2C.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7b_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 83;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_220899; }
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_move2c(src & 0xFFF, regp)) goto l_220899;
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+l_220899: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* JSR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4e90_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr oldpc = m68k_getpci () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_220900;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_030 ();
+}}}l_220900: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ea8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_220901;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_030 ();
+}}}l_220901: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_220902;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_030 ();
+}}}}l_220902: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_220903;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_030 ();
+}}}l_220903: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uaecptr oldpc = m68k_getpci () + 6;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_220904;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_030 ();
+}}}l_220904: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eba_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_220905;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_030 ();
+}}}l_220905: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ebb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_220906;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_030 ();
+}}}}l_220906: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ed0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_220907;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_030 ();
+}}l_220907: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ee8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_220908;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_030 ();
+}}l_220908: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_220909;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_030 ();
+}}}l_220909: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_220910;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_030 ();
+}}l_220910: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_220911;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_030 ();
+}}l_220911: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_220912;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_030 ();
+}}l_220912: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_220913;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_030 ();
+}}}l_220913: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5000_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5010_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5018_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5020_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5028_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5030_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5038_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5039_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5040_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5048_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5050_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5058_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5060_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5068_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5070_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5078_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5079_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5080_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5088_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5090_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5098_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_5
+/* ADDQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_50b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_50b8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_50b9_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (0)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_220941;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_220941: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (0)) { Exception (7); goto l_220949; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_220949: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (0)) { Exception (7); goto l_220950; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_220950: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (0)) { Exception (7); goto l_220951; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_220951: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* SUBQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5100_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5110_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5118_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5120_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5128_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5130_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5138_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5139_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5140_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5148_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5150_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5158_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5160_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5168_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5170_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5178_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5179_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5180_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5188_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5190_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5198_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_51b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_51b8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_51b9_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (1)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_220979;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_220979: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (1)) { Exception (7); goto l_220987; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_220987: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (1)) { Exception (7); goto l_220988; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_220988: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (1)) { Exception (7); goto l_220989; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_220989: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (2)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_220991;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_220991: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (2)) { Exception (7); goto l_220999; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_220999: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (2)) { Exception (7); goto l_221000; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_221000: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (2)) { Exception (7); goto l_221001; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_221001: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (3)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_221003;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_221003: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (3)) { Exception (7); goto l_221011; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_221011: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (3)) { Exception (7); goto l_221012; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_221012: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (3)) { Exception (7); goto l_221013; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_221013: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (4)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_221015;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_221015: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (4)) { Exception (7); goto l_221023; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_221023: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (4)) { Exception (7); goto l_221024; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_221024: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (4)) { Exception (7); goto l_221025; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_221025: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (5)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_221027;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_221027: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (5)) { Exception (7); goto l_221035; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_221035: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (5)) { Exception (7); goto l_221036; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_221036: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (5)) { Exception (7); goto l_221037; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_221037: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (6)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_221039;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_221039: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (6)) { Exception (7); goto l_221047; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_221047: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (6)) { Exception (7); goto l_221048; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_221048: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (6)) { Exception (7); goto l_221049; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_221049: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (7)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_221051;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_221051: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (7)) { Exception (7); goto l_221059; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_221059: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (7)) { Exception (7); goto l_221060; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_221060: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (7)) { Exception (7); goto l_221061; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_221061: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (8)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_221063;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_221063: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (8)) { Exception (7); goto l_221071; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_221071: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (8)) { Exception (7); goto l_221072; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_221072: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (8)) { Exception (7); goto l_221073; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_221073: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (9)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_221075;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_221075: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (9)) { Exception (7); goto l_221083; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_221083: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (9)) { Exception (7); goto l_221084; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_221084: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (9)) { Exception (7); goto l_221085; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_221085: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (10)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_221087;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_221087: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (10)) { Exception (7); goto l_221095; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_221095: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (10)) { Exception (7); goto l_221096; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_221096: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (10)) { Exception (7); goto l_221097; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_221097: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (11)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_221099;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_221099: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (11)) { Exception (7); goto l_221107; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_221107: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (11)) { Exception (7); goto l_221108; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_221108: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (11)) { Exception (7); goto l_221109; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_221109: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (12)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_221111;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_221111: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (12)) { Exception (7); goto l_221119; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_221119: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (12)) { Exception (7); goto l_221120; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_221120: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (12)) { Exception (7); goto l_221121; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_221121: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (13)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_221123;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_221123: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (13)) { Exception (7); goto l_221131; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_221131: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (13)) { Exception (7); goto l_221132; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_221132: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (13)) { Exception (7); goto l_221133; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_221133: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (14)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_221135;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_221135: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (14)) { Exception (7); goto l_221143; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_221143: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (14)) { Exception (7); goto l_221144; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_221144: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (14)) { Exception (7); goto l_221145; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_221145: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_030_prefetch (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (15)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_221147;
+			}
+	fill_prefetch_030 ();
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_020_prefetch();
+}}}l_221147: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffa_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_word_030_prefetch (2);
+	if (cctrue (15)) { Exception (7); goto l_221155; }
+	regs.irc = get_word_030_prefetch (4);
+}}	m68k_incpci (4);
+l_221155: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffb_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (2);
+	if (cctrue (15)) { Exception (7); goto l_221156; }
+	regs.irc = get_word_030_prefetch (6);
+}}	m68k_incpci (6);
+l_221156: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffc_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (15)) { Exception (7); goto l_221157; }
+	regs.irc = get_word_030_prefetch (2);
+}	m68k_incpci (2);
+l_221157: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Bcc.W #.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6000_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221158;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221158: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6001_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221159;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221159: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_60ff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221160;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221160: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_6100_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_s16 src = get_word_030_prefetch (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_221161;
+	}
+	m68k_do_bsri (m68k_getpci () + 4, s);
+	fill_prefetch_030 ();
+}}l_221161: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSRQ.B # */
+uae_u32 REGPARAM2 CPUFUNC(op_6101_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_u32 src = srcreg;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_221162;
+	}
+	m68k_do_bsri (m68k_getpci () + 2, s);
+	fill_prefetch_030 ();
+}}l_221162: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSR.L #.L */
+uae_u32 REGPARAM2 CPUFUNC(op_61ff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_221163;
+	}
+	m68k_do_bsri (m68k_getpci () + 6, s);
+	fill_prefetch_030 ();
+}}l_221163: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6200_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221164;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221164: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6201_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221165;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221165: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_62ff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221166;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221166: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6300_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221167;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221167: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6301_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221168;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221168: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_6
+/* Bcc.L #.L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_63ff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221169;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221169: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6400_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221170;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221170: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6401_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221171;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221171: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_64ff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221172;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221172: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6500_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221173;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221173: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6501_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221174;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221174: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_65ff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221175;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221175: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6600_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221176;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221176: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6601_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221177;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221177: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_66ff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221178;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221178: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6700_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221179;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221179: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6701_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221180;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221180: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_67ff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221181;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221181: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6800_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221182;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221182: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6801_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221183;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221183: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_68ff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221184;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221184: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6900_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221185;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221185: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6901_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221186;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221186: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_69ff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221187;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221187: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a00_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221188;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221188: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a01_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221189;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221189: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6aff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221190;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221190: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b00_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221191;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221191: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b01_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221192;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221192: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6bff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221193;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221193: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c00_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221194;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221194: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c01_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221195;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221195: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6cff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221196;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221196: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d00_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221197;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221197: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d01_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221198;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221198: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6dff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221199;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221199: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e00_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221200;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221200: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e01_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221201;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221201: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6eff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221202;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221202: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f00_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221203;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_020_prefetch();
+}}l_221203: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f01_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221204;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_020_prefetch();
+}}l_221204: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6fff_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_221205;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_020_prefetch();
+}}l_221205: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_7000_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8000_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8010_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8018_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8020_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8028_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8030_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8038_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8039_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8040_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8050_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8058_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8060_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8068_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8070_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8078_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8079_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8080_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8090_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8098_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80ba_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 110;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_221240;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}l_221240: ;
+return 110 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_221241;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221241: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_221242;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221242: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_221243;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221243: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_221244;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221244: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_221245;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}}l_221245: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_221246;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221246: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_221247;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (6);
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221247: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_221248;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221248: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_221249;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}}l_221249: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 114;
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_221250;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}l_221250: ;
+return 114 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8100_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8108_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8110_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8118_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8120_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8128_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8130_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8138_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8139_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PACK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8140_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val = m68k_dreg (regs, srcreg) + get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);
+	regs.irc = get_word_030_prefetch (4);
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PACK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8148_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val;
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (val | ((uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff) << 8)) + get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) -= areg_byteinc[dstreg];
+	x_put_byte (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));
+	regs.irc = get_word_030_prefetch (4);
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* OR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8150_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8158_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8160_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8168_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8170_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8178_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8179_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* UNPK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8180_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val = m68k_dreg (regs, srcreg);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);
+	regs.irc = get_word_030_prefetch (4);
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* UNPK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8188_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val;
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];
+	x_put_byte (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);
+	x_put_byte (m68k_areg (regs, dstreg), val >> 8);
+	regs.irc = get_word_030_prefetch (4);
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* OR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8190_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8198_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_81b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_81b8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_81b9_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 142;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_221278;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	regs.irc = get_word_030_prefetch (0);
+}}}l_221278: ;
+return 142 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_221279;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221279: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_221280;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221280: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_221281;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221281: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_221282;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221282: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_221283;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}}l_221283: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_221284;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221284: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_221285;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (6);
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221285: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_221286;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221286: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_221287;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}}}}l_221287: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 146;
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_221288;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	regs.irc = get_word_030_prefetch (0);
+}}}l_221288: ;
+return 146 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9000_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9010_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9018_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9020_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9028_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9030_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9038_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9039_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9040_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9048_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9050_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9058_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9060_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9068_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9070_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9078_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9079_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9080_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9088_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9090_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9098_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90ba_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (6);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9100_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9108_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9110_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9118_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9120_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9128_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9130_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9138_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9139_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9140_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9148_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9150_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9158_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9160_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9168_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9170_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9178_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9179_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9180_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9188_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 26 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9190_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9198_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_91b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_91b8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_91b9_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (6);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_030_prefetch (6);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b000_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b010_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b018_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b020_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b028_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b030_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b038_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b039_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b040_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b048_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b050_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b058_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b060_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b068_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b070_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b078_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b079_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b080_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b088_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b090_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b098_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_7
+/* CMP.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0ba_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b100_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b108_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b110_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b118_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b120_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b128_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b130_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b138_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b139_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b140_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b148_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b150_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b158_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b160_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b168_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b170_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b178_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b179_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b180_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b188_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b190_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b198_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b9_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c000_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c010_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c018_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c020_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c028_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c030_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c038_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c039_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c040_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c050_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c058_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c060_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c068_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c070_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c078_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c079_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c080_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c090_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c098_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0ba_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 58; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}return 58 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 40; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return 40 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (6);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 62; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}return 62 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c100_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c108_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c110_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c118_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c120_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c128_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c130_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c138_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c139_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c140_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c148_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c150_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c158_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c160_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c168_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c170_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c178_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c179_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c188_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c190_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c198_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b9_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 58; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 58 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 40; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 40 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 62; 
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d000_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d010_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d018_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d020_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d028_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d030_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d038_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d039_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = (uae_u8)get_word_030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d040_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d048_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d050_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d058_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d060_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d068_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d070_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d078_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d079_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07c_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d080_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d088_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d090_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d098_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0ba_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (6);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_word_030_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d100_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d108_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d110_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d118_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d120_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d128_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d130_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d138_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d139_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d140_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d148_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d150_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d158_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d160_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d168_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d170_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d178_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d179_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d180_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d188_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 26 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d190_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d198_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b9_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f9_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_long_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (6);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (4);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (0);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fc_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_long_030_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_030_prefetch (6);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e000_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e008_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e010_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e018_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e020_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e028_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e030_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e038_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e040_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_8
+/* LSRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e048_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e050_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e058_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e060_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e068_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e070_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e078_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e080_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e088_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e090_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e098_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e100_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e108_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e110_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e118_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e120_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e128_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e130_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e138_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e140_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e148_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e150_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e158_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e160_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e168_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e170_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e178_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e180_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e188_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e190_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e198_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.irc = get_word_030_prefetch (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e8_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.irc = get_word_030_prefetch (0);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.irc = get_word_030_prefetch (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_long_030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.irc = get_word_030_prefetch (6);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BFTST.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8c0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8d0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8e8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_030_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9c0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9d0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9e8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9fa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9fb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eac0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ead0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eae8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebc0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebd0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebe8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebfa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebfb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecc0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecd0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ece8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edc0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edd0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ede8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_030_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edfa_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edfb_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eec0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eed0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eee8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efc0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efd0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (4);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efe8_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff0_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff8_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (6);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff9_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_word_030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_030_prefetch (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_030_prefetch (8);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L Dn,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f000_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221788; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	uae_u16 extraa = 0;
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_221788;
+	regs.irc = get_word_030_prefetch (0);
+}}l_221788: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L An,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f008_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221789; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	uae_u16 extraa = 0;
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_221789;
+	regs.irc = get_word_030_prefetch (0);
+}}l_221789: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f010_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221790; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_221790;
+	regs.irc = get_word_030_prefetch (0);
+}}}l_221790: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (An)+,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f018_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221791; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_221791;
+	regs.irc = get_word_030_prefetch (0);
+}}}l_221791: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L -(An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f020_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 6;  
+{if (!regs.s) { Exception (8); goto l_221792; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) - 4;
+	m68k_areg (regs, srcreg) = extraa;
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_221792;
+	regs.irc = get_word_030_prefetch (0);
+}}}l_221792: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (d16,An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f028_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_221793; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_030_prefetch (0);
+	m68k_incpci (2);
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_221793;
+	regs.irc = get_word_030_prefetch (0);
+}}}l_221793: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (d8,An,Xn),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f030_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_221794; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+{	extraa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_221794;
+	regs.irc = get_word_030_prefetch (0);
+}}}}l_221794: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (xxx).W,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f038_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_221795; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = (uae_s32)(uae_s16)get_word_030_prefetch (0);
+	m68k_incpci (2);
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_221795;
+	regs.irc = get_word_030_prefetch (0);
+}}}l_221795: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (xxx).L,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f039_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_221796; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = get_long_030_prefetch (0);
+	m68k_incpci (4);
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_221796;
+	regs.irc = get_word_030_prefetch (0);
+}}}l_221796: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f200_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_221797;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221797: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f208_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_221798;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221798: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f210_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_221799;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221799: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f218_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_221800;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221800: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f220_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_221801;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221801: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f228_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_221802;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221802: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f230_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_221803;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221803: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f238_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_221804;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221804: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f239_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_221805;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221805: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23a_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_221806;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221806: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23b_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_221807;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221807: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23c_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_221808;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221808: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f240_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_221809;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221809: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FDBcc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f248_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 105;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_dbcc (opcode, extra);
+	if (regs.fp_exception) goto l_221810;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_221810;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221810: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f250_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_221811;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221811: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f258_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_221812;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221812: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f260_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_221813;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221813: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f268_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_221814;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221814: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f270_22)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_221815;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221815: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f278_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_221816;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221816: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f279_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_221817;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221817: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27a_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 12; 
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_word_030_prefetch (2);
+{	uae_s16 dummy = get_word_030_prefetch (4);
+	m68k_incpci (6);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_221818;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221818: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27b_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 16; 
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_word_030_prefetch (2);
+{	uae_s32 dummy;
+	dummy = get_long_030_prefetch (4);
+	m68k_incpci (8);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_221819;
+	regs.irc = get_word_030_prefetch (0);
+}
+#endif
+}l_221819: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L  */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27c_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_word_030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_221820;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}l_221820: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FBccQ.L #,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f280_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s16 extra = get_word_030_prefetch (0);
+	m68k_incpci (2);
+	fpuop_bcc (opcode, pc,extra);
+	if (regs.fp_exception) goto l_221821;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_221821;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}
+#endif
+}l_221821: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FBccQ.L #,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f2c0_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+	CurrentInstrCycles = 12; 
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s32 extra;
+	extra = get_long_030_prefetch (0);
+	m68k_incpci (4);
+	fpuop_bcc (opcode, pc,extra);
+	if (regs.fp_exception) goto l_221822;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_221822;
+	}
+	regs.irc = get_word_030_prefetch (0);
+}}
+#endif
+}l_221822: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f310_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221823; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_221823;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}}l_221823: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f320_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221824; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_221824;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}}l_221824: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f328_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221825; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_221825;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}}l_221825: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f330_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221826; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_221826;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}}l_221826: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f338_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221827; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_221827;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}}l_221827: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f339_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221828; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_221828;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}}l_221828: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f350_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221829; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_221829;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}}l_221829: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f358_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221830; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_221830;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}}l_221830: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f368_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221831; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_221831;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}}l_221831: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f370_22)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221832; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_221832;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}}l_221832: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f378_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221833; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_221833;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}}l_221833: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f379_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221834; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_221834;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}}l_221834: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f37a_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221835; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_221835;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}}l_221835: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f37b_22)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_221836; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_221836;
+	regs.irc = get_word_030_prefetch (0);
+
+#endif
+}}l_221836: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
diff --git a/src/cpu/cpuemu_23.c b/src/cpu/cpuemu_23.c
new file mode 100644
index 0000000..fecbb85
--- /dev/null
+++ b/src/cpu/cpuemu_23.c
@@ -0,0 +1,46788 @@
+#include "main.h"
+#include "sysdeps.h"
+#include "hatari-glue.h"
+#include "maccess.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "cputbl.h"
+#define CPUFUNC(x) x##_ff
+#define SET_CFLG_ALWAYS(x) SET_CFLG(x)
+#define SET_NFLG_ALWAYS(x) SET_NFLG(x)
+#ifdef NOFLAGS
+#include "noflags.h"
+#endif
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+/* OR.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0000_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0010_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0018_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0020_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0028_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0030_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* OR.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0038_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0039_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* ORSR.B #.W */
+void REGPARAM2 CPUFUNC(op_003c_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+{	MakeSR ();
+{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	src &= 0xFF;
+	regs.sr |= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0040_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0050_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0058_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0060_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0068_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0070_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* OR.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0078_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0079_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* ORSR.W #.W */
+void REGPARAM2 CPUFUNC(op_007c_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+{if (!regs.s) { Exception (8); goto l_230018; }
+{	MakeSR ();
+{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	regs.sr |= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230018: ;
+return;
+}
+
+/* OR.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0080_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4+2=6,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0090_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0098_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_00a0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_00a8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* OR.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_00b0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:8,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* OR.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_00b8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* OR.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_00b9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{	/* ea H:5,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 5 * cpucycleunit)
+		regs.ce020memcycles = 5 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return;
+}
+
+/* CHK2.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00d0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230027; }
+}
+	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230027: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00e8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230028; }
+}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230028: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00f0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230029; }
+}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230029: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230030; }
+}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230030: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230031; }
+}
+	regs.irc = get_word_ce030_prefetch (8);
+}}}	m68k_incpci (8);
+l_230031: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230032; }
+}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230032: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce030 (tmppc, 0);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230033; }
+}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230033: ;
+return;
+}
+
+#endif
+/* BTST.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_0100_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVPMR.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_0108_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	/* OP zero */
+	uae_u16 val;
+	MovepByteNbr=1; val = ((x_get_byte (memp) & 0xff) << 8);
+	MovepByteNbr=2; val += (x_get_byte (memp + 2) & 0xff);
+	MovepByteNbr=0;
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_0110_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BTST.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_0118_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BTST.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_0120_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BTST.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0128_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0130_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}}return;
+}
+
+/* BTST.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0138_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0139_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BTST.B Dn,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_013a_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 2;
+	dsta += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B Dn,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_013b_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce030 (tmppc, 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}}return;
+}
+
+/* BTST.B Dn,#.B */
+void REGPARAM2 CPUFUNC(op_013c_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = (uae_u8)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_0140_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVPMR.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_0148_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	/* OP zero */
+	uae_u32 val;
+	MovepByteNbr=1; val = ((x_get_byte (memp) & 0xff) << 24);
+	MovepByteNbr=2; val += ((x_get_byte (memp + 2) & 0xff) << 16);
+	MovepByteNbr=3; val += ((x_get_byte (memp + 4) & 0xff) << 8);
+	MovepByteNbr=4; val += (x_get_byte (memp + 6) & 0xff);
+	MovepByteNbr=0;
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_0150_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCHG.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_0158_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCHG.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_0160_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCHG.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0168_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0170_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BCHG.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0178_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0179_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCLR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_0180_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVPRM.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0188_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* OP zero */
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	MovepByteNbr=1; 	x_put_byte (memp, src >> 8);
+	MovepByteNbr=2; 	x_put_byte (memp + 2, src);
+	MovepByteNbr=0;
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_0190_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCLR.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_0198_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCLR.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_01a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCLR.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_01a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_01b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BCLR.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_01b8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_01b9_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BSET.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_01c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVPRM.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_01c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* OP zero */
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	MovepByteNbr=1; 	x_put_byte (memp, src >> 24);
+	MovepByteNbr=2; 	x_put_byte (memp + 2, src >> 16);
+	MovepByteNbr=3; 	x_put_byte (memp + 4, src >> 8);
+	MovepByteNbr=4; 	x_put_byte (memp + 6, src);
+	MovepByteNbr=0;
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_01d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BSET.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_01d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BSET.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_01e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BSET.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_01e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_01f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BSET.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_01f8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_01f9_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0200_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0210_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0218_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0220_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0228_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0230_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* AND.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0238_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0239_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* ANDSR.B #.W */
+void REGPARAM2 CPUFUNC(op_023c_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+{	MakeSR ();
+{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	src |= 0xFF00;
+	regs.sr &= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0240_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0250_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0258_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0260_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0268_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0270_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* AND.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0278_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0279_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* ANDSR.W #.W */
+void REGPARAM2 CPUFUNC(op_027c_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+{if (!regs.s) { Exception (8); goto l_230090; }
+{	MakeSR ();
+{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	regs.sr &= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230090: ;
+return;
+}
+
+/* AND.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0280_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4+2=6,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0290_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0298_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_02a0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_02a8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* AND.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_02b0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:8,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* AND.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_02b8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* AND.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_02b9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{	/* ea H:5,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 5 * cpucycleunit)
+		regs.ce020memcycles = 5 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return;
+}
+
+/* CHK2.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02d0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230099; }
+}
+	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230099: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02e8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230100; }
+}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230100: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02f0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230101; }
+}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230101: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230102; }
+}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230102: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230103; }
+}
+	regs.irc = get_word_ce030_prefetch (8);
+}}}	m68k_incpci (8);
+l_230103: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230104; }
+}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230104: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce030 (tmppc, 0);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230105; }
+}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230105: ;
+return;
+}
+
+#endif
+/* SUB.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0400_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0410_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0418_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0420_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0428_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0430_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0438_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0439_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* SUB.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0440_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0450_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0458_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0460_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0468_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0470_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0478_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0479_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* SUB.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0480_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4+2=6,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0490_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0498_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_04a0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_04a8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* SUB.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_04b0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:8,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_04b8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* SUB.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_04b9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{	/* ea H:5,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 5 * cpucycleunit)
+		regs.ce020memcycles = 5 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (10);
+return;
+}
+
+/* CHK2.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04d0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230130; }
+}
+	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230130: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04e8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230131; }
+}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230131: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04f0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230132; }
+}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230132: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230133; }
+}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230133: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230134; }
+}
+	regs.irc = get_word_ce030_prefetch (8);
+}}}	m68k_incpci (8);
+l_230134: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230135; }
+}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230135: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce030 (tmppc, 0);
+	/* OP zero */
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_230136; }
+}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230136: ;
+return;
+}
+
+#endif
+/* ADD.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0600_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0610_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0618_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0620_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0628_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0630_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0638_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0639_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* ADD.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0640_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0650_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0658_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0660_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0668_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0670_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0678_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0679_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* ADD.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0680_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4+2=6,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0690_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0698_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_06a0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_06a8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* ADD.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_06b0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:8,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_06b8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* ADD.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_06b9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{	/* ea H:5,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 5 * cpucycleunit)
+		regs.ce020memcycles = 5 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (10);
+return;
+}
+
+/* RTM.L Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce030_prefetch (0);
+}return;
+}
+
+#endif
+/* RTM.L An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce030_prefetch (0);
+}return;
+}
+
+#endif
+/* CALLM.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce030_prefetch (0);
+}return;
+}
+
+#endif
+/* CALLM.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce030_prefetch (0);
+}return;
+}
+
+#endif
+/* CALLM.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce030_prefetch (0);
+}return;
+}
+
+#endif
+/* CALLM.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce030_prefetch (0);
+}return;
+}
+
+#endif
+/* CALLM.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce030_prefetch (0);
+}return;
+}
+
+#endif
+/* CALLM.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce030_prefetch (0);
+}return;
+}
+
+#endif
+/* CALLM.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce030_prefetch (0);
+}return;
+}
+
+#endif
+/* BTST.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0800_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* No EA */
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	regs.irc = get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0810_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0818_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0820_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0828_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BTST.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0830_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}}return;
+}
+
+/* BTST.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0838_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BTST.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0839_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* BTST.B #.W,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_083a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BTST.B #.W,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_083b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	do_cycles_ce020_internal (2);
+}}}}}return;
+}
+
+/* BCHG.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0840_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* No EA */
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.irc = get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0850_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0858_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0860_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0868_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCHG.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0870_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BCHG.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0878_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCHG.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0879_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* BCLR.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0880_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* No EA */
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.irc = get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0890_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0898_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_08a0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_08a8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCLR.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_08b0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BCLR.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_08b8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCLR.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_08b9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* BSET.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_08c0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* No EA */
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.irc = get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_08d0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_08d8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_08e0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_08e8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BSET.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_08f0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BSET.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_08f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BSET.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_08f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EOR.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0a00_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0a10_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0a18_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0a20_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0a28_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0a30_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* EOR.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0a38_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0a39_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EORSR.B #.W */
+void REGPARAM2 CPUFUNC(op_0a3c_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+{	MakeSR ();
+{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	src &= 0xFF;
+	regs.sr ^= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0a40_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0a50_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0a58_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0a60_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0a68_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0a70_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* EOR.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0a78_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0a79_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EORSR.W #.W */
+void REGPARAM2 CPUFUNC(op_0a7c_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+{if (!regs.s) { Exception (8); goto l_230221; }
+{	MakeSR ();
+{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	regs.sr ^= src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230221: ;
+return;
+}
+
+/* EOR.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0a80_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:4+2=6,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (6);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0a90_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:1,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0a98_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:4,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_0aa0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0aa8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:4,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EOR.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0ab0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:8,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* EOR.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0ab8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EOR.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0ab9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{	/* ea H:5,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 5 * cpucycleunit)
+		regs.ce020memcycles = 5 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return;
+}
+
+/* CAS.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ad0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (4);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ad8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (4);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ae0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (4);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ae8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (6);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+#endif
+
+#ifdef PART_2
+/* CAS.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0af0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (0);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (0);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}}return;
+}
+
+#endif
+/* CAS.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0af8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (6);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CAS.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0af9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (8);
+	x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (8);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* CMP.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0c00_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0c10_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0c18_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0c20_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0c28_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0c30_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0c38_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0c39_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* CMP.B #.B,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0c3a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CMP.B #.B,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0c3b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+#endif
+/* CMP.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0c40_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2+2=4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0c50_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:1,C:1 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0c58_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0c60_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0c68_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0c70_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0c78_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0c79_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{	/* ea H:3,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 3 * cpucycleunit)
+		regs.ce020memcycles = 3 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* CMP.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0c7a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CMP.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0c7b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 dst = x_get_word (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+#endif
+/* CMP.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0c80_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4+2=6,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2-,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0c90_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0c98_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:1,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_0ca0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0ca8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* CMP.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0cb0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{	/* ea H:8,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0cb8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{	/* ea H:6,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* CMP.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0cb9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{	/* ea H:5,T:0,C:3 fiea */
+	if (regs.ce020memcycles > 5 * cpucycleunit)
+		regs.ce020memcycles = 5 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (10);
+return;
+}
+
+/* CMP.L #.L,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cba_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:0,C:2 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 6;
+	dsta += (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* CMP.L #.L,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cbb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+{	/* ea H:8,T:2,C:0 fiea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (6);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+#endif
+/* CAS.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cd0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (4);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cd8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (4);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ce0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (4);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (4);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ce8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (6);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CAS.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cf0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (0);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (0);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}}return;
+}
+
+#endif
+/* CAS.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cf8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (6);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (6);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CAS.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cf9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s16 dst = x_get_word (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (8);
+	x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (8);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* CAS2.W #.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cfc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+{{	uae_s32 extra;
+	extra = get_long_ce030_prefetch (2);
+	/* OP zero */
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u16 dst1 = x_get_word (rn1), dst2 = x_get_word (rn2);
+{uae_u32 newv = ((uae_u16)(dst1)) - ((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s16)(dst1)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u16)(dst2)) - ((uae_u16)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s16)(dst2)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, extra & 7))) > ((uae_u16)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	x_put_word (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	x_put_word (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);
+	m68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);
+	}
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* MOVES.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e10_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230275; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = x_get_byte (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230275: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e18_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230276; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	/* OP zero */
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230276: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e20_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230277; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	/* OP zero */
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, dstreg) = srca;
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230277: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e28_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230278; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 src = x_get_byte (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230278: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e30_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230279; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+	x_put_byte (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 1);
+{	uae_s8 src = x_get_byte (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}	regs.irc = get_word_ce030_prefetch (0);
+}}}l_230279: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e38_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230280; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s8 src = x_get_byte (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230280: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e39_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230281; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	/* OP zero */
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_long_ce030_prefetch (4);
+{	uae_s8 src = x_get_byte (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (8);
+}}}	m68k_incpci (8);
+l_230281: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e50_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230282; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230282: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e58_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230283; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	/* OP zero */
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, dstreg) += 2;
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230283: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e60_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230284; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	/* OP zero */
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, dstreg) = srca;
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230284: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e68_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230285; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230285: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e70_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230286; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+	x_put_word (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 1);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}	regs.irc = get_word_ce030_prefetch (0);
+}}}l_230286: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e78_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230287; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230287: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e79_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230288; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	/* OP zero */
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_long_ce030_prefetch (4);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (8);
+}}}	m68k_incpci (8);
+l_230288: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e90_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230289; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230289: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e98_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230290; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	/* OP zero */
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, dstreg) += 4;
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230290: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ea0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230291; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	/* OP zero */
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, dstreg) = srca;
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+l_230291: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ea8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230292; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230292: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0eb0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230293; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+	x_put_long (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 1);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}	regs.irc = get_word_ce030_prefetch (0);
+}}}l_230293: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0eb8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230294; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+l_230294: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0eb9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_230295; }
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	/* OP zero */
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_long_ce030_prefetch (4);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}	regs.irc = get_word_ce030_prefetch (8);
+}}}	m68k_incpci (8);
+l_230295: ;
+return;
+}
+
+#endif
+/* CAS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ed0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (4);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (4);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ed8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (4);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (4);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ee0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (4);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (4);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ee8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (6);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (6);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CAS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ef0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (0);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (0);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}}return;
+}
+
+#endif
+/* CAS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ef8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (6);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (6);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CAS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ef9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* OP zero */
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		regs.irc = get_word_ce030_prefetch (8);
+	x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+	regs.irc = get_word_ce030_prefetch (8);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* CAS2.L #.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0efc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+{{	uae_s32 extra;
+	extra = get_long_ce030_prefetch (2);
+	/* OP zero */
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u32 dst1 = x_get_long (rn1), dst2 = x_get_long (rn2);
+{uae_u32 newv = ((uae_u32)(dst1)) - ((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s32)(dst1)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u32)(dst2)) - ((uae_u32)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s32)(dst2)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, extra & 7))) > ((uae_u32)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	x_put_long (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	x_put_long (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = dst2;
+	m68k_dreg (regs, (extra >> 22) & 7) = dst1;
+	}
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* MOVE.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_1000_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_1010_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_1018_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_1020_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_1028_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_1030_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_1038_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_1039_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_103a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_103b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* MOVE.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_103c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_1080_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.B (An),(An) */
+void REGPARAM2 CPUFUNC(op_1090_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(An) */
+void REGPARAM2 CPUFUNC(op_1098_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B -(An),(An) */
+void REGPARAM2 CPUFUNC(op_10a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(An) */
+void REGPARAM2 CPUFUNC(op_10a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_10b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(An) */
+void REGPARAM2 CPUFUNC(op_10b8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(An) */
+void REGPARAM2 CPUFUNC(op_10b9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(An) */
+void REGPARAM2 CPUFUNC(op_10ba_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_10bb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_10bc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_10c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.B (An),(An)+ */
+void REGPARAM2 CPUFUNC(op_10d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_10d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B -(An),(An)+ */
+void REGPARAM2 CPUFUNC(op_10e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(An)+ */
+void REGPARAM2 CPUFUNC(op_10e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_10f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(An)+ */
+void REGPARAM2 CPUFUNC(op_10f8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(An)+ */
+void REGPARAM2 CPUFUNC(op_10f9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(An)+ */
+void REGPARAM2 CPUFUNC(op_10fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_10fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_10fc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_1100_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:0,T:2,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.B (An),-(An) */
+void REGPARAM2 CPUFUNC(op_1110_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (An)+,-(An) */
+void REGPARAM2 CPUFUNC(op_1118_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_1120_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),-(An) */
+void REGPARAM2 CPUFUNC(op_1128_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_1130_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,-(An) */
+void REGPARAM2 CPUFUNC(op_1138_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,-(An) */
+void REGPARAM2 CPUFUNC(op_1139_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),-(An) */
+void REGPARAM2 CPUFUNC(op_113a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_113b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_113c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1140_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B (An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1150_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1158_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B -(An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1160_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1168_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1170_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1178_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1179_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+	regs.irc = get_word_ce030_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(d16,An) */
+void REGPARAM2 CPUFUNC(op_117a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_117b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_117c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_1180_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}return;
+}
+
+/* MOVE.B (An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_1190_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_1198_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B -(An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 1);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11b8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11b9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11ba_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11bb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 1);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11bc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+}}}}return;
+}
+
+/* MOVE.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B (An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B -(An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+	regs.irc = get_word_ce030_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.B (An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B -(An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (6);
+	regs.irc = get_word_ce030_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (10);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}return;
+}
+
+/* MOVE.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_2000_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L An,Dn */
+void REGPARAM2 CPUFUNC(op_2008_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_2010_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_2018_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_2020_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_2028_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_2030_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_2038_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_2039_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_203a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_203b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* MOVE.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_203c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVEA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_2040_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVEA.L An,An */
+void REGPARAM2 CPUFUNC(op_2048_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVEA.L (An),An */
+void REGPARAM2 CPUFUNC(op_2050_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_2058_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_2060_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_2068_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_2070_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* MOVEA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_2078_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_2079_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVEA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_207a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_207b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* MOVEA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_207c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_2080_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L An,(An) */
+void REGPARAM2 CPUFUNC(op_2088_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L (An),(An) */
+void REGPARAM2 CPUFUNC(op_2090_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(An) */
+void REGPARAM2 CPUFUNC(op_2098_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L -(An),(An) */
+void REGPARAM2 CPUFUNC(op_20a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(An) */
+void REGPARAM2 CPUFUNC(op_20a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_20b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(An) */
+void REGPARAM2 CPUFUNC(op_20b8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(An) */
+void REGPARAM2 CPUFUNC(op_20b9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(An) */
+void REGPARAM2 CPUFUNC(op_20ba_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_20bb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_20bc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_20c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L An,(An)+ */
+void REGPARAM2 CPUFUNC(op_20c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L (An),(An)+ */
+void REGPARAM2 CPUFUNC(op_20d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_20d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L -(An),(An)+ */
+void REGPARAM2 CPUFUNC(op_20e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(An)+ */
+void REGPARAM2 CPUFUNC(op_20e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_20f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(An)+ */
+void REGPARAM2 CPUFUNC(op_20f8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(An)+ */
+void REGPARAM2 CPUFUNC(op_20f9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(An)+ */
+void REGPARAM2 CPUFUNC(op_20fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_20fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_20fc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_2100_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:0,T:2,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L An,-(An) */
+void REGPARAM2 CPUFUNC(op_2108_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:0,T:2,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L (An),-(An) */
+void REGPARAM2 CPUFUNC(op_2110_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (An)+,-(An) */
+void REGPARAM2 CPUFUNC(op_2118_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_2120_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),-(An) */
+void REGPARAM2 CPUFUNC(op_2128_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_2130_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,-(An) */
+void REGPARAM2 CPUFUNC(op_2138_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,-(An) */
+void REGPARAM2 CPUFUNC(op_2139_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),-(An) */
+void REGPARAM2 CPUFUNC(op_213a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_213b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_213c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2140_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.L An,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2148_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.L (An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2150_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2158_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L -(An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2160_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2168_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2170_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2178_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2179_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+	regs.irc = get_word_ce030_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(d16,An) */
+void REGPARAM2 CPUFUNC(op_217a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_217b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_217c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+	regs.irc = get_word_ce030_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}return;
+}
+
+/* MOVE.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2180_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}return;
+}
+
+/* MOVE.L An,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2188_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}return;
+}
+
+/* MOVE.L (An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2190_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2198_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+#endif
+
+#ifdef PART_3
+/* MOVE.L -(An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 1);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21b8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21b9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21ba_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21bb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 1);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21bc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+}}}}return;
+}
+
+/* MOVE.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.L An,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.L (An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L -(An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+	regs.irc = get_word_ce030_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+	regs.irc = get_word_ce030_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}return;
+}
+
+/* MOVE.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L An,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L (An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L -(An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (6);
+	regs.irc = get_word_ce030_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (10);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (6);
+	regs.irc = get_word_ce030_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_long (dsta, src);
+	m68k_incpci (10);
+}}}return;
+}
+
+/* MOVE.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_3000_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W An,Dn */
+void REGPARAM2 CPUFUNC(op_3008_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_3010_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_3018_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_3020_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_3028_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_3030_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_3038_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_3039_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_303a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_303b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* MOVE.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_303c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVEA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_3040_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVEA.W An,An */
+void REGPARAM2 CPUFUNC(op_3048_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	/* op H:2,T:0,C:0 */
+	src = (uae_s32)(uae_s16)src;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVEA.W (An),An */
+void REGPARAM2 CPUFUNC(op_3050_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_3058_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_3060_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_3068_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_3070_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return;
+}
+
+/* MOVEA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_3078_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_3079_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVEA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_307a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_307b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return;
+}
+
+/* MOVEA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_307c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_3080_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W An,(An) */
+void REGPARAM2 CPUFUNC(op_3088_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W (An),(An) */
+void REGPARAM2 CPUFUNC(op_3090_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(An) */
+void REGPARAM2 CPUFUNC(op_3098_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W -(An),(An) */
+void REGPARAM2 CPUFUNC(op_30a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(An) */
+void REGPARAM2 CPUFUNC(op_30a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_30b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(An) */
+void REGPARAM2 CPUFUNC(op_30b8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(An) */
+void REGPARAM2 CPUFUNC(op_30b9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(An) */
+void REGPARAM2 CPUFUNC(op_30ba_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_30bb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_30bc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_30c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W An,(An)+ */
+void REGPARAM2 CPUFUNC(op_30c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W (An),(An)+ */
+void REGPARAM2 CPUFUNC(op_30d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_30d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W -(An),(An)+ */
+void REGPARAM2 CPUFUNC(op_30e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(An)+ */
+void REGPARAM2 CPUFUNC(op_30e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_30f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(An)+ */
+void REGPARAM2 CPUFUNC(op_30f8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(An)+ */
+void REGPARAM2 CPUFUNC(op_30f9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(An)+ */
+void REGPARAM2 CPUFUNC(op_30fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_30fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_30fc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_3100_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:0,T:2,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W An,-(An) */
+void REGPARAM2 CPUFUNC(op_3108_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:0,T:2,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W (An),-(An) */
+void REGPARAM2 CPUFUNC(op_3110_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (An)+,-(An) */
+void REGPARAM2 CPUFUNC(op_3118_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_3120_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),-(An) */
+void REGPARAM2 CPUFUNC(op_3128_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_3130_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,-(An) */
+void REGPARAM2 CPUFUNC(op_3138_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,-(An) */
+void REGPARAM2 CPUFUNC(op_3139_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),-(An) */
+void REGPARAM2 CPUFUNC(op_313a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_313b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_313c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3140_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W An,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3148_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W (An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3150_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3158_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W -(An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3160_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3168_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3170_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3178_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3179_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+	regs.irc = get_word_ce030_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(d16,An) */
+void REGPARAM2 CPUFUNC(op_317a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_317b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_317c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3180_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}return;
+}
+
+/* MOVE.W An,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3188_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}return;
+}
+
+/* MOVE.W (An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3190_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3198_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W -(An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 1);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31b8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31b9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31ba_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31bb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 1);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31bc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+}}}}return;
+}
+
+/* MOVE.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W An,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W (An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W -(An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (6);
+	regs.irc = get_word_ce030_prefetch (8);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (2);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.W An,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.W (An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W -(An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (6);
+	regs.irc = get_word_ce030_prefetch (10);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (10);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (0);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{	/* ea H:2,T:0,C:0 fiea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	regs.irc = get_word_ce030_prefetch (8);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (4);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}return;
+}
+
+/* NEGX.B Dn */
+void REGPARAM2 CPUFUNC(op_4000_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.B (An) */
+void REGPARAM2 CPUFUNC(op_4010_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4018_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.B -(An) */
+void REGPARAM2 CPUFUNC(op_4020_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4028_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4030_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, newv);
+}}}}}}return;
+}
+
+/* NEGX.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4038_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4039_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* NEGX.W Dn */
+void REGPARAM2 CPUFUNC(op_4040_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.W (An) */
+void REGPARAM2 CPUFUNC(op_4050_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4058_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.W -(An) */
+void REGPARAM2 CPUFUNC(op_4060_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4068_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4070_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, newv);
+}}}}}}return;
+}
+
+/* NEGX.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4078_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4079_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* NEGX.L Dn */
+void REGPARAM2 CPUFUNC(op_4080_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.L (An) */
+void REGPARAM2 CPUFUNC(op_4090_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4098_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.L -(An) */
+void REGPARAM2 CPUFUNC(op_40a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_40a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_40b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, newv);
+}}}}}}return;
+}
+
+/* NEGX.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_40b8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_40b9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* MVSR2.W Dn */
+void REGPARAM2 CPUFUNC(op_40c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_230632; }
+{{	/* op H:2,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}}	m68k_incpci (2);
+l_230632: ;
+return;
+}
+
+/* MVSR2.W (An) */
+void REGPARAM2 CPUFUNC(op_40d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_230633; }
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_230633: ;
+return;
+}
+
+/* MVSR2.W (An)+ */
+void REGPARAM2 CPUFUNC(op_40d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_230634; }
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	MakeSR ();
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_230634: ;
+return;
+}
+
+/* MVSR2.W -(An) */
+void REGPARAM2 CPUFUNC(op_40e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_230635; }
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_230635: ;
+return;
+}
+
+/* MVSR2.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_40e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_230636; }
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_230636: ;
+return;
+}
+
+/* MVSR2.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_40f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_230637; }
+{	/* ea H:4+2=6,T:0,C:0 cea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr);
+}}}}l_230637: ;
+return;
+}
+
+/* MVSR2.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_40f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_230638; }
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_230638: ;
+return;
+}
+
+/* MVSR2.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_40f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_230639; }
+{	/* ea H:4+2=6,T:0,C:0 cea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce030_prefetch (6);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (6);
+l_230639: ;
+return;
+}
+
+/* CHK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4100_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230640;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230640;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}l_230640: ;
+return;
+}
+
+#endif
+/* CHK.L (An),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4110_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230641;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230641;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230641: ;
+return;
+}
+
+#endif
+/* CHK.L (An)+,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4118_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230642;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230642;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230642: ;
+return;
+}
+
+#endif
+/* CHK.L -(An),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4120_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230643;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230643;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230643: ;
+return;
+}
+
+#endif
+/* CHK.L (d16,An),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4128_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230644;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230644;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230644: ;
+return;
+}
+
+#endif
+/* CHK.L (d8,An,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4130_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230645;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230645;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}l_230645: ;
+return;
+}
+
+#endif
+/* CHK.L (xxx).W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4138_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230646;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230646;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230646: ;
+return;
+}
+
+#endif
+/* CHK.L (xxx).L,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4139_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230647;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230647;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230647: ;
+return;
+}
+
+#endif
+/* CHK.L (d16,PC),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_413a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230648;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230648;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230648: ;
+return;
+}
+
+#endif
+/* CHK.L (d8,PC,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_413b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230649;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230649;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}l_230649: ;
+return;
+}
+
+#endif
+/* CHK.L #.L,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_413c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230650;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230650;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}l_230650: ;
+return;
+}
+
+#endif
+/* CHK.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_4180_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230651;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230651;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}l_230651: ;
+return;
+}
+
+/* CHK.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_4190_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230652;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230652;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230652: ;
+return;
+}
+
+/* CHK.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_4198_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230653;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230653;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230653: ;
+return;
+}
+
+/* CHK.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_41a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230654;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230654;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230654: ;
+return;
+}
+
+/* CHK.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_41a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230655;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230655;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230655: ;
+return;
+}
+
+/* CHK.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_41b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230656;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230656;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}l_230656: ;
+return;
+}
+
+/* CHK.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_41b8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230657;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230657;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230657: ;
+return;
+}
+
+/* CHK.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_41b9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230658;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230658;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230658: ;
+return;
+}
+
+/* CHK.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_41ba_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230659;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230659;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_230659: ;
+return;
+}
+
+/* CHK.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_41bb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230660;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230660;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}l_230660: ;
+return;
+}
+
+/* CHK.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_41bc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* OP zero */
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_230661;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_230661;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}l_230661: ;
+return;
+}
+
+/* LEA.L (An),An */
+void REGPARAM2 CPUFUNC(op_41d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	/* op H:2-,T:0,C:0 */
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* LEA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_41e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	/* op H:2-,T:0,C:0 */
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* LEA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_41f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{	/* ea H:4+2=6,T:0,C:0 cea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	/* op H:2-,T:0,C:0 */
+	regs.irc = get_word_ce030_prefetch (0);
+	m68k_areg (regs, dstreg) = (srca);
+}}}}return;
+}
+
+/* LEA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_41f8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	/* op H:2-,T:0,C:0 */
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* LEA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_41f9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{	/* ea H:4+2=6,T:0,C:0 cea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	/* op H:2-,T:0,C:0 */
+	regs.irc = get_word_ce030_prefetch (6);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* LEA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_41fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	/* op H:2-,T:0,C:0 */
+	regs.irc = get_word_ce030_prefetch (4);
+	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* LEA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_41fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{	/* ea H:4+2=6,T:0,C:0 cea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	/* op H:2-,T:0,C:0 */
+	regs.irc = get_word_ce030_prefetch (0);
+	m68k_areg (regs, dstreg) = (srca);
+}}}}return;
+}
+
+/* CLR.B Dn */
+void REGPARAM2 CPUFUNC(op_4200_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.B (An) */
+void REGPARAM2 CPUFUNC(op_4210_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4218_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.B -(An) */
+void REGPARAM2 CPUFUNC(op_4220_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4228_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4230_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, 0);
+}}}return;
+}
+
+/* CLR.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4238_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4239_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (6);
+return;
+}
+
+/* CLR.W Dn */
+void REGPARAM2 CPUFUNC(op_4240_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.W (An) */
+void REGPARAM2 CPUFUNC(op_4250_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4258_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.W -(An) */
+void REGPARAM2 CPUFUNC(op_4260_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4268_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4270_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, 0);
+}}}return;
+}
+
+/* CLR.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4278_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4279_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, 0);
+}}	m68k_incpci (6);
+return;
+}
+
+/* CLR.L Dn */
+void REGPARAM2 CPUFUNC(op_4280_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	/* op H:2,T:0,C:0 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.L (An) */
+void REGPARAM2 CPUFUNC(op_4290_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4298_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.L -(An) */
+void REGPARAM2 CPUFUNC(op_42a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_42a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_42b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, 0);
+}}}return;
+}
+
+/* CLR.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_42b8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_42b9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, 0);
+}}	m68k_incpci (6);
+return;
+}
+
+/* MVSR2.B Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{{	/* op H:2,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* MVSR2.B (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* MVSR2.B (An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:2 */
+	MakeSR ();
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* MVSR2.B -(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* MVSR2.B (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* MVSR2.B (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{	/* ea H:4+2=6,T:0,C:0 cea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}}return;
+}
+
+#endif
+/* MVSR2.B (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+{	/* ea H:2+2=4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* MVSR2.B (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+{	/* ea H:4+2=6,T:0,C:0 cea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	/* op H:2-,T:0,C:2 */
+	MakeSR ();
+	regs.irc = get_word_ce030_prefetch (6);
+	do_cycles_ce020_internal (2);
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* NEG.B Dn */
+void REGPARAM2 CPUFUNC(op_4400_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+
+#ifdef PART_4
+/* NEG.B (An) */
+void REGPARAM2 CPUFUNC(op_4410_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4418_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.B -(An) */
+void REGPARAM2 CPUFUNC(op_4420_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4428_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4430_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}}}return;
+}
+
+/* NEG.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4438_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4439_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* NEG.W Dn */
+void REGPARAM2 CPUFUNC(op_4440_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.W (An) */
+void REGPARAM2 CPUFUNC(op_4450_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4458_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.W -(An) */
+void REGPARAM2 CPUFUNC(op_4460_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4468_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4470_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}}}return;
+}
+
+/* NEG.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4478_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4479_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* NEG.L Dn */
+void REGPARAM2 CPUFUNC(op_4480_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.L (An) */
+void REGPARAM2 CPUFUNC(op_4490_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4498_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.L -(An) */
+void REGPARAM2 CPUFUNC(op_44a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_44a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_44b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}}}return;
+}
+
+/* NEG.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_44b8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_44b9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* MV2SR.B Dn */
+void REGPARAM2 CPUFUNC(op_44c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* op H:4,T:0,C:0 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+}}	m68k_incpci (2);
+return;
+}
+
+/* MV2SR.B (An) */
+void REGPARAM2 CPUFUNC(op_44d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MV2SR.B (An)+ */
+void REGPARAM2 CPUFUNC(op_44d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MV2SR.B -(An) */
+void REGPARAM2 CPUFUNC(op_44e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MV2SR.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_44e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MV2SR.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_44f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}}return;
+}
+
+/* MV2SR.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_44f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MV2SR.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_44f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MV2SR.B (d16,PC) */
+void REGPARAM2 CPUFUNC(op_44fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MV2SR.B (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_44fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}}}return;
+}
+
+/* MV2SR.B #.B */
+void REGPARAM2 CPUFUNC(op_44fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (2);
+}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.B Dn */
+void REGPARAM2 CPUFUNC(op_4600_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.B (An) */
+void REGPARAM2 CPUFUNC(op_4610_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4618_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.B -(An) */
+void REGPARAM2 CPUFUNC(op_4620_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4628_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4630_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}}return;
+}
+
+/* NOT.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4638_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4639_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* NOT.W Dn */
+void REGPARAM2 CPUFUNC(op_4640_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.W (An) */
+void REGPARAM2 CPUFUNC(op_4650_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4658_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.W -(An) */
+void REGPARAM2 CPUFUNC(op_4660_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4668_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4670_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}}return;
+}
+
+/* NOT.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4678_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4679_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* NOT.L Dn */
+void REGPARAM2 CPUFUNC(op_4680_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.L (An) */
+void REGPARAM2 CPUFUNC(op_4690_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4698_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.L -(An) */
+void REGPARAM2 CPUFUNC(op_46a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_46a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_46b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}}return;
+}
+
+/* NOT.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_46b8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_46b9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* MV2SR.W Dn */
+void REGPARAM2 CPUFUNC(op_46c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_230760; }
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}	m68k_incpci (2);
+l_230760: ;
+return;
+}
+
+/* MV2SR.W (An) */
+void REGPARAM2 CPUFUNC(op_46d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_230761; }
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}	m68k_incpci (2);
+l_230761: ;
+return;
+}
+
+/* MV2SR.W (An)+ */
+void REGPARAM2 CPUFUNC(op_46d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_230762; }
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}	m68k_incpci (2);
+l_230762: ;
+return;
+}
+
+/* MV2SR.W -(An) */
+void REGPARAM2 CPUFUNC(op_46e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_230763; }
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}	m68k_incpci (2);
+l_230763: ;
+return;
+}
+
+/* MV2SR.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_46e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_230764; }
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}	m68k_incpci (4);
+l_230764: ;
+return;
+}
+
+/* MV2SR.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_46f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_230765; }
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}}l_230765: ;
+return;
+}
+
+/* MV2SR.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_46f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_230766; }
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}	m68k_incpci (4);
+l_230766: ;
+return;
+}
+
+/* MV2SR.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_46f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_230767; }
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}	m68k_incpci (6);
+l_230767: ;
+return;
+}
+
+/* MV2SR.W (d16,PC) */
+void REGPARAM2 CPUFUNC(op_46fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_230768; }
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}	m68k_incpci (4);
+l_230768: ;
+return;
+}
+
+/* MV2SR.W (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_46fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_230769; }
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}}}l_230769: ;
+return;
+}
+
+/* MV2SR.W #.W */
+void REGPARAM2 CPUFUNC(op_46fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_230770; }
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	do_cycles_ce020_internal (6);
+}}}	m68k_incpci (4);
+l_230770: ;
+return;
+}
+
+/* NBCD.B Dn */
+void REGPARAM2 CPUFUNC(op_4800_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* LINK.L An,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4808_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+{	/* op H:2,T:0,C:4 */
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 offs;
+	offs = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	do_cycles_ce020_internal (4);
+	x_put_long (olda, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* NBCD.B (An) */
+void REGPARAM2 CPUFUNC(op_4810_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NBCD.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4818_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NBCD.B -(An) */
+void REGPARAM2 CPUFUNC(op_4820_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NBCD.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4828_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NBCD.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4830_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (4);
+	x_put_byte (srca, newv);
+}}}}}return;
+}
+
+/* NBCD.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4838_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NBCD.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4839_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	/* op H:0,T:0,C:6 */
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce030_prefetch (6);
+	do_cycles_ce020_internal (4);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* SWAP.W Dn */
+void REGPARAM2 CPUFUNC(op_4840_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 34;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* BKPTQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4848_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 99;
+{	m68k_incpci (2);
+	op_illg (opcode);
+	regs.irc = get_word_ce030_prefetch (0);
+}return;
+}
+
+#endif
+/* PEA.L (An) */
+void REGPARAM2 CPUFUNC(op_4850_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:2,C:2 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* PEA.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4868_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:2,C:2 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* PEA.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4870_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:2,C:2 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, srca);
+}}}}return;
+}
+
+/* PEA.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4878_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:2,C:2 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* PEA.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4879_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:2,C:2 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* PEA.L (d16,PC) */
+void REGPARAM2 CPUFUNC(op_487a_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:2,C:2 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* PEA.L (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_487b_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:2,C:2 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	do_cycles_ce020_internal (2);
+	x_put_long (dsta, srca);
+}}}}return;
+}
+
+/* EXT.W Dn */
+void REGPARAM2 CPUFUNC(op_4880_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u16 dst = (uae_s16)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVMLE.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_4890_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMLE.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_48a0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+	do_cycles_ce020_internal (2);
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	int type = get_cpu_model () >= 68020;
+	while (amask) {
+		srca -= 2;
+		if (!type || movem_index2[amask] != dstreg)
+			x_put_word (srca, m68k_areg (regs, movem_index2[amask]));
+		else
+			x_put_word (srca, m68k_areg (regs, movem_index2[amask]) - 2);
+		amask = movem_next[amask];
+	}
+	while (dmask) { srca -= 2; x_put_word (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMLE.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_48a8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMLE.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_48b0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}return;
+}
+
+/* MVMLE.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_48b8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMLE.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_48b9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (4);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+	regs.irc = get_word_ce030_prefetch (8);
+}}}	m68k_incpci (8);
+return;
+}
+
+/* EXT.L Dn */
+void REGPARAM2 CPUFUNC(op_48c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 dst = (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVMLE.L #.W,(An) */
+void REGPARAM2 CPUFUNC(op_48d0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMLE.L #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_48e0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+	do_cycles_ce020_internal (2);
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	int type = get_cpu_model () >= 68020;
+	while (amask) {
+		srca -= 4;
+		if (!type || movem_index2[amask] != dstreg)
+			x_put_long (srca, m68k_areg (regs, movem_index2[amask]));
+		else
+			x_put_long (srca, m68k_areg (regs, movem_index2[amask]) - 4);
+		amask = movem_next[amask];
+	}
+	while (dmask) { srca -= 4; x_put_long (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMLE.L #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_48e8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMLE.L #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_48f0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}return;
+}
+
+/* MVMLE.L #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_48f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMLE.L #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_48f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (4);
+	do_cycles_ce020_internal (2);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+	regs.irc = get_word_ce030_prefetch (8);
+}}}	m68k_incpci (8);
+return;
+}
+
+/* EXT.B Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_49c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 dst = (uae_s32)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* TST.B Dn */
+void REGPARAM2 CPUFUNC(op_4a00_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+}}	m68k_incpci (2);
+return;
+}
+
+/* TST.B (An) */
+void REGPARAM2 CPUFUNC(op_4a10_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4a18_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.B -(An) */
+void REGPARAM2 CPUFUNC(op_4a20_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4a28_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4a30_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return;
+}
+
+/* TST.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4a38_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4a39_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* TST.B (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a3a_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.B (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a3b_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return;
+}
+
+#endif
+/* TST.B #.B */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a3c_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.W Dn */
+void REGPARAM2 CPUFUNC(op_4a40_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+}}	m68k_incpci (2);
+return;
+}
+
+/* TST.W An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a48_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* TST.W (An) */
+void REGPARAM2 CPUFUNC(op_4a50_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4a58_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.W -(An) */
+void REGPARAM2 CPUFUNC(op_4a60_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4a68_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4a70_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return;
+}
+
+/* TST.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4a78_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4a79_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* TST.W (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a7a_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.W (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a7b_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return;
+}
+
+#endif
+/* TST.W #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a7c_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.L Dn */
+void REGPARAM2 CPUFUNC(op_4a80_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+}}	m68k_incpci (2);
+return;
+}
+
+/* TST.L An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a88_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* TST.L (An) */
+void REGPARAM2 CPUFUNC(op_4a90_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4a98_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.L -(An) */
+void REGPARAM2 CPUFUNC(op_4aa0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4aa8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4ab0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return;
+}
+
+/* TST.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4ab8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4ab9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* TST.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4aba_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4abb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return;
+}
+
+#endif
+/* TST.L #.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4abc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* TAS.B Dn */
+void REGPARAM2 CPUFUNC(op_4ac0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((src) & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+/* TAS.B (An) */
+void REGPARAM2 CPUFUNC(op_4ad0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TAS.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4ad8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TAS.B -(An) */
+void REGPARAM2 CPUFUNC(op_4ae0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TAS.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4ae8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TAS.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4af0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}}return;
+}
+
+/* TAS.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4af8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TAS.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4af9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MULL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c00_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_230847;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}l_230847: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c10_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_230848;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}l_230848: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c18_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_230849;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}l_230849: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c20_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_230850;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}l_230850: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c28_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_230851;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}l_230851: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c30_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:2,T:0,C:28 */
+	if (!m68k_mull(opcode, dst, extra)) goto l_230852;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}}l_230852: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c38_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_230853;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}l_230853: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c39_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_230854;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}l_230854: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c3a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_230855;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}l_230855: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c3b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:2,T:0,C:28 */
+	if (!m68k_mull(opcode, dst, extra)) goto l_230856;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}}}l_230856: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c3c_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:2,T:0,C:28 */
+{	uae_s32 dst;
+	dst = get_long_ce030_prefetch (4);
+	/* op H:2,T:0,C:28 */
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_230857;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (28);
+}}}l_230857: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c40_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_230858;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}l_230858: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c50_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_230859;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}l_230859: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c58_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_230860;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}l_230860: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c60_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_230861;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}l_230861: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c68_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_230862;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}l_230862: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c70_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:0,T:0,C:50 */
+	if (!m68k_divl(opcode, dst, extra)) goto l_230863;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}}l_230863: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c78_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_230864;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}l_230864: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c79_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_230865;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}l_230865: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c7a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_230866;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}l_230866: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c7b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+	/* op H:0,T:0,C:50 */
+	if (!m68k_divl(opcode, dst, extra)) goto l_230867;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}}}l_230867: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c7c_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* op H:0,T:0,C:50 */
+{	uae_s32 dst;
+	dst = get_long_ce030_prefetch (4);
+	/* op H:0,T:0,C:50 */
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_230868;
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (48);
+}}}l_230868: ;
+return;
+}
+
+#endif
+/* MVMEL.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_4c90_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMEL.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_4c98_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMEL.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_4ca8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4cb0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}return;
+}
+
+/* MVMEL.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_4cb8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_4cb9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce030_prefetch (8);
+}}}	m68k_incpci (8);
+return;
+}
+
+/* MVMEL.W #.W,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_4cba_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.W #.W,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4cbb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}return;
+}
+
+/* MVMEL.L #.W,(An) */
+void REGPARAM2 CPUFUNC(op_4cd0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMEL.L #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_4cd8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	regs.irc = get_word_ce030_prefetch (4);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMEL.L #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_4ce8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.L #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4cf0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}return;
+}
+
+/* MVMEL.L #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_4cf8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.L #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_4cf9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce030_prefetch (8);
+}}}	m68k_incpci (8);
+return;
+}
+
+/* MVMEL.L #.W,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_4cfa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce030_prefetch (6);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.L #.W,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4cfb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_word_ce030_prefetch (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+	do_cycles_ce020_internal (6);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}return;
+}
+
+/* TRAPQ.L # */
+void REGPARAM2 CPUFUNC(op_4e40_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 15);
+	OpcodeFamily = 39;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	m68k_incpci (2);
+	Exception (src + 32);
+}}return;
+}
+
+/* LINK.W An,#.W */
+void REGPARAM2 CPUFUNC(op_4e50_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+{	/* op H:0,T:0,C:4 */
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (2);
+	x_put_long (olda, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* UNLK.L An */
+void REGPARAM2 CPUFUNC(op_4e58_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 48;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	/* op H:0,T:0,C:5 */
+	m68k_areg (regs, 7) = src;
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7);
+{	uae_s32 old = x_get_long (olda);
+	m68k_areg (regs, 7) += 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (3);
+	m68k_areg (regs, srcreg) = (old);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* MVR2USP.L An */
+void REGPARAM2 CPUFUNC(op_4e60_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 40;
+{if (!regs.s) { Exception (8); goto l_230888; }
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	/* op H:4,T:0,C:0 */
+	regs.usp = src;
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+}}}	m68k_incpci (2);
+l_230888: ;
+return;
+}
+
+/* MVUSP2R.L An */
+void REGPARAM2 CPUFUNC(op_4e68_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 41;
+{if (!regs.s) { Exception (8); goto l_230889; }
+{{	/* op H:4,T:0,C:0 */
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, srcreg) = (regs.usp);
+}}}	m68k_incpci (2);
+l_230889: ;
+return;
+}
+
+/* RESET.L  */
+void REGPARAM2 CPUFUNC(op_4e70_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 42;
+{if (!regs.s) { Exception (8); goto l_230890; }
+{	cpureset ();
+	m68k_incpci (2);
+	regs.irc = get_word_ce030_prefetch (0);
+}}l_230890: ;
+return;
+}
+
+/* NOP.L  */
+void REGPARAM2 CPUFUNC(op_4e71_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 43;
+{	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+return;
+}
+
+/* STOP.L #.W */
+void REGPARAM2 CPUFUNC(op_4e72_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 44;
+{if (!regs.s) { Exception (8); goto l_230892; }
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* op H:0,T:0,C:8 */
+	regs.sr = src;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	m68k_setstopped ();
+	m68k_incpci (4);
+	do_cycles_ce020_internal (6);
+}}}l_230892: ;
+return;
+}
+
+/* RTE.L  */
+void REGPARAM2 CPUFUNC(op_4e73_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 45;
+{if (!regs.s) { Exception (8); goto l_230893; }
+{	/* op H:1,T:9,C:8 */
+	uae_u16 newsr; uae_u32 newpc;
+	for (;;) {
+		uaecptr a = m68k_areg (regs, 7);
+		uae_u16 sr = x_get_word (a);
+		uae_u32 pc = x_get_long (a + 2);
+		uae_u16 format = x_get_word (a + 2 + 4);
+		int frame = format >> 12;
+		int offset = 8;
+		newsr = sr; newpc = pc;
+	do_cycles_ce020_internal (6);
+		if (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }
+		else if (frame == 0x1) { m68k_areg (regs, 7) += offset; }
+		else if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }
+		else if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }
+		else if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }
+		else if (frame == 0x7) { m68k_areg (regs, 7) += offset + 52; break; }
+		else if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }
+		else if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }
+		else if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }
+		else { m68k_areg (regs, 7) += offset; Exception (14); goto l_230893; }
+		regs.sr = newsr;
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+}
+	regs.sr = newsr;
+	do_cycles_ce020_internal (4);
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	if (newpc & 1) {
+		exception3i (0x4E73, newpc);
+		goto l_230893;
+	}
+	m68k_setpci (newpc);
+	ipl_fetch ();
+	fill_prefetch_030 ();
+}}l_230893: ;
+return;
+}
+
+/* RTD.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4e74_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 46;
+{	/* op H:2,T:0,C:8 */
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = x_get_long (pca);
+	m68k_areg (regs, 7) += 4;
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* op H:2,T:0,C:8 */
+	m68k_areg (regs, 7) += offs;
+	if (pc & 1) {
+		exception3i (0x4E74, pc);
+		goto l_230894;
+	}
+	m68k_setpci (pc);
+	fill_prefetch_030 ();
+}}}}l_230894: ;
+return;
+}
+
+#endif
+/* RTS.L  */
+void REGPARAM2 CPUFUNC(op_4e75_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 49;
+{	/* op H:1,T:0,C:8 */
+	uaecptr pc = m68k_getpci ();
+	m68k_do_rts_ce030 ();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (pc);
+		exception3i (0x4E75, faultpc);
+		goto l_230895;
+	}
+	do_cycles_ce020_internal (3);
+	fill_prefetch_030 ();
+}l_230895: ;
+return;
+}
+
+/* TRAPV.L  */
+void REGPARAM2 CPUFUNC(op_4e76_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 50;
+{	m68k_incpci (2);
+	if (GET_VFLG ()) {
+		Exception (7);
+		goto l_230896;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}l_230896: ;
+return;
+}
+
+/* RTR.L  */
+void REGPARAM2 CPUFUNC(op_4e77_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 51;
+{	uaecptr oldpc = m68k_getpci ();
+	MakeSR ();
+{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+{	uae_s16 sr = x_get_word (sra);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = x_get_long (pca);
+	m68k_areg (regs, 7) += 4;
+	regs.sr &= 0xFF00; sr &= 0xFF;
+	regs.sr |= sr;
+	m68k_setpci (pc);
+	MakeFromSR();
+	regs.ipl_pin = intlev ();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (oldpc);
+		exception3i (0x4E77, faultpc);
+		goto l_230897;
+	}
+	fill_prefetch_030 ();
+}}}}}l_230897: ;
+return;
+}
+
+/* MOVEC2.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4e7a_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 82;
+{if (!regs.s) { Exception (8); goto l_230898; }
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* op H:6,T:0,C:0 */
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_movec2(src & 0xFFF, regp)) goto l_230898;
+	regs.irc = get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (4);
+}}}}	m68k_incpci (4);
+l_230898: ;
+return;
+}
+
+#endif
+/* MOVE2C.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4e7b_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 83;
+{if (!regs.s) { Exception (8); goto l_230899; }
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* op H:6,T:0,C:0 */
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_move2c(src & 0xFFF, regp)) goto l_230899;
+	regs.irc = get_word_ce030_prefetch (4);
+	do_cycles_ce020_internal (4);
+}}}}	m68k_incpci (4);
+l_230899: ;
+return;
+}
+
+#endif
+/* JSR.L (An) */
+void REGPARAM2 CPUFUNC(op_4e90_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+{	/* ea H:2,T:0,C:0 jea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uaecptr oldpc = m68k_getpci () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_230900;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_030 ();
+}}}l_230900: ;
+return;
+}
+
+/* JSR.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4ea8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+{	/* ea H:4,T:0,C:0 jea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_230901;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_030 ();
+}}}l_230901: ;
+return;
+}
+
+/* JSR.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4eb0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+{	/* ea H:0,T:0,C:0 jea */
+	regs.ce020memcycles = 0;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_230902;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_030 ();
+}}}}l_230902: ;
+return;
+}
+
+/* JSR.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4eb8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+{	/* ea H:2,T:0,C:0 jea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_230903;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_030 ();
+}}}l_230903: ;
+return;
+}
+
+/* JSR.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4eb9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+{	/* ea H:2,T:0,C:0 jea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uaecptr oldpc = m68k_getpci () + 6;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_230904;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_030 ();
+}}}l_230904: ;
+return;
+}
+
+/* JSR.L (d16,PC) */
+void REGPARAM2 CPUFUNC(op_4eba_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+{	/* ea H:4,T:0,C:0 jea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_230905;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_030 ();
+}}}l_230905: ;
+return;
+}
+
+/* JSR.L (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4ebb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+{	/* ea H:0,T:0,C:0 jea */
+	regs.ce020memcycles = 0;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_230906;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+	fill_prefetch_030 ();
+}}}}l_230906: ;
+return;
+}
+
+/* JMP.L (An) */
+void REGPARAM2 CPUFUNC(op_4ed0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+{	/* ea H:2+4=6,T:0,C:0 jea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	/* op H:4-,T:0,C:0 */
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_230907;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_030 ();
+}}l_230907: ;
+return;
+}
+
+/* JMP.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4ee8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+{	/* ea H:4+4=8,T:0,C:0 jea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	/* op H:4-,T:0,C:0 */
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_230908;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_030 ();
+}}l_230908: ;
+return;
+}
+
+/* JMP.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4ef0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+{	/* ea H:0,T:0,C:0 jea */
+	regs.ce020memcycles = 0;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_230909;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_030 ();
+}}}l_230909: ;
+return;
+}
+
+/* JMP.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4ef8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+{	/* ea H:2+4=6,T:0,C:0 jea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	/* op H:4-,T:0,C:0 */
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_230910;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_030 ();
+}}l_230910: ;
+return;
+}
+
+/* JMP.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4ef9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+{	/* ea H:2+4=6,T:0,C:0 jea */
+	if (regs.ce020memcycles > 6 * cpucycleunit)
+		regs.ce020memcycles = 6 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	/* op H:4-,T:0,C:0 */
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_230911;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_030 ();
+}}l_230911: ;
+return;
+}
+
+/* JMP.L (d16,PC) */
+void REGPARAM2 CPUFUNC(op_4efa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+{	/* ea H:4+4=8,T:0,C:0 jea */
+	if (regs.ce020memcycles > 8 * cpucycleunit)
+		regs.ce020memcycles = 8 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	/* op H:4-,T:0,C:0 */
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_230912;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_030 ();
+}}l_230912: ;
+return;
+}
+
+/* JMP.L (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4efb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+{	/* ea H:0,T:0,C:0 jea */
+	regs.ce020memcycles = 0;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_230913;
+	}
+	m68k_setpci (srca);
+	fill_prefetch_030 ();
+}}}l_230913: ;
+return;
+}
+
+/* ADDQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_5000_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.B #,(An) */
+void REGPARAM2 CPUFUNC(op_5010_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.B #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5018_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.B #,-(An) */
+void REGPARAM2 CPUFUNC(op_5020_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.B #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5028_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.B #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5030_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADDQ.B #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5038_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.B #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5039_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_5040_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDAQ.W #,An */
+void REGPARAM2 CPUFUNC(op_5048_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.W #,(An) */
+void REGPARAM2 CPUFUNC(op_5050_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.W #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5058_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.W #,-(An) */
+void REGPARAM2 CPUFUNC(op_5060_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.W #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5068_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.W #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5070_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADDQ.W #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5078_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.W #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5079_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_5080_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDAQ.L #,An */
+void REGPARAM2 CPUFUNC(op_5088_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.L #,(An) */
+void REGPARAM2 CPUFUNC(op_5090_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.L #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5098_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.L #,-(An) */
+void REGPARAM2 CPUFUNC(op_50a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+
+#ifdef PART_5
+/* ADDQ.L #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_50a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.L #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_50b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADDQ.L #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_50b8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.L #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_50b9_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* Scc.B Dn (T) */
+void REGPARAM2 CPUFUNC(op_50c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (T) */
+void REGPARAM2 CPUFUNC(op_50c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (0)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_230941;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_230941: ;
+return;
+}
+
+/* Scc.B (An) (T) */
+void REGPARAM2 CPUFUNC(op_50d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (T) */
+void REGPARAM2 CPUFUNC(op_50d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (T) */
+void REGPARAM2 CPUFUNC(op_50e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (T) */
+void REGPARAM2 CPUFUNC(op_50e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (T) */
+void REGPARAM2 CPUFUNC(op_50f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (T) */
+void REGPARAM2 CPUFUNC(op_50f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (T) */
+void REGPARAM2 CPUFUNC(op_50f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (T) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_50fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (0)) { Exception (7); goto l_230949; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_230949: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (T) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_50fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (0)) { Exception (7); goto l_230950; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_230950: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (T) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_50fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (0)) { Exception (7); goto l_230951; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_230951: ;
+return;
+}
+
+#endif
+/* SUBQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_5100_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.B #,(An) */
+void REGPARAM2 CPUFUNC(op_5110_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.B #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5118_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.B #,-(An) */
+void REGPARAM2 CPUFUNC(op_5120_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.B #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5128_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.B #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5130_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUBQ.B #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5138_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.B #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5139_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_5140_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBAQ.W #,An */
+void REGPARAM2 CPUFUNC(op_5148_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.W #,(An) */
+void REGPARAM2 CPUFUNC(op_5150_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.W #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5158_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.W #,-(An) */
+void REGPARAM2 CPUFUNC(op_5160_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.W #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5168_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.W #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5170_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUBQ.W #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5178_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.W #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5179_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_5180_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBAQ.L #,An */
+void REGPARAM2 CPUFUNC(op_5188_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+{	/* No EA */
+{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.L #,(An) */
+void REGPARAM2 CPUFUNC(op_5190_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.L #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5198_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.L #,-(An) */
+void REGPARAM2 CPUFUNC(op_51a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.L #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_51a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.L #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_51b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUBQ.L #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_51b8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.L #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_51b9_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* Scc.B Dn (F) */
+void REGPARAM2 CPUFUNC(op_51c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (F) */
+void REGPARAM2 CPUFUNC(op_51c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (1)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_230979;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_230979: ;
+return;
+}
+
+/* Scc.B (An) (F) */
+void REGPARAM2 CPUFUNC(op_51d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (F) */
+void REGPARAM2 CPUFUNC(op_51d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (F) */
+void REGPARAM2 CPUFUNC(op_51e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (F) */
+void REGPARAM2 CPUFUNC(op_51e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (F) */
+void REGPARAM2 CPUFUNC(op_51f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (F) */
+void REGPARAM2 CPUFUNC(op_51f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (F) */
+void REGPARAM2 CPUFUNC(op_51f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (F) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_51fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (1)) { Exception (7); goto l_230987; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_230987: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (F) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_51fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (1)) { Exception (7); goto l_230988; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_230988: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (F) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_51fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (1)) { Exception (7); goto l_230989; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_230989: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (HI) */
+void REGPARAM2 CPUFUNC(op_52c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (HI) */
+void REGPARAM2 CPUFUNC(op_52c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (2)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_230991;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_230991: ;
+return;
+}
+
+/* Scc.B (An) (HI) */
+void REGPARAM2 CPUFUNC(op_52d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (HI) */
+void REGPARAM2 CPUFUNC(op_52d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (HI) */
+void REGPARAM2 CPUFUNC(op_52e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (HI) */
+void REGPARAM2 CPUFUNC(op_52e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (HI) */
+void REGPARAM2 CPUFUNC(op_52f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (HI) */
+void REGPARAM2 CPUFUNC(op_52f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (HI) */
+void REGPARAM2 CPUFUNC(op_52f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (HI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_52fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (2)) { Exception (7); goto l_230999; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_230999: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (HI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_52fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (2)) { Exception (7); goto l_231000; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_231000: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (HI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_52fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (2)) { Exception (7); goto l_231001; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_231001: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (LS) */
+void REGPARAM2 CPUFUNC(op_53c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (LS) */
+void REGPARAM2 CPUFUNC(op_53c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (3)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_231003;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_231003: ;
+return;
+}
+
+/* Scc.B (An) (LS) */
+void REGPARAM2 CPUFUNC(op_53d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (LS) */
+void REGPARAM2 CPUFUNC(op_53d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (LS) */
+void REGPARAM2 CPUFUNC(op_53e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (LS) */
+void REGPARAM2 CPUFUNC(op_53e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (LS) */
+void REGPARAM2 CPUFUNC(op_53f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (LS) */
+void REGPARAM2 CPUFUNC(op_53f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (LS) */
+void REGPARAM2 CPUFUNC(op_53f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (LS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_53fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (3)) { Exception (7); goto l_231011; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_231011: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (LS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_53fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (3)) { Exception (7); goto l_231012; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_231012: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (LS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_53fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (3)) { Exception (7); goto l_231013; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_231013: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (CC) */
+void REGPARAM2 CPUFUNC(op_54c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (CC) */
+void REGPARAM2 CPUFUNC(op_54c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (4)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_231015;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_231015: ;
+return;
+}
+
+/* Scc.B (An) (CC) */
+void REGPARAM2 CPUFUNC(op_54d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (CC) */
+void REGPARAM2 CPUFUNC(op_54d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (CC) */
+void REGPARAM2 CPUFUNC(op_54e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (CC) */
+void REGPARAM2 CPUFUNC(op_54e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (CC) */
+void REGPARAM2 CPUFUNC(op_54f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (CC) */
+void REGPARAM2 CPUFUNC(op_54f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (CC) */
+void REGPARAM2 CPUFUNC(op_54f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (CC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_54fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (4)) { Exception (7); goto l_231023; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_231023: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (CC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_54fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (4)) { Exception (7); goto l_231024; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_231024: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (CC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_54fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (4)) { Exception (7); goto l_231025; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_231025: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (CS) */
+void REGPARAM2 CPUFUNC(op_55c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (CS) */
+void REGPARAM2 CPUFUNC(op_55c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (5)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_231027;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_231027: ;
+return;
+}
+
+/* Scc.B (An) (CS) */
+void REGPARAM2 CPUFUNC(op_55d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (CS) */
+void REGPARAM2 CPUFUNC(op_55d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (CS) */
+void REGPARAM2 CPUFUNC(op_55e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (CS) */
+void REGPARAM2 CPUFUNC(op_55e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (CS) */
+void REGPARAM2 CPUFUNC(op_55f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (CS) */
+void REGPARAM2 CPUFUNC(op_55f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (CS) */
+void REGPARAM2 CPUFUNC(op_55f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (CS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_55fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (5)) { Exception (7); goto l_231035; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_231035: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (CS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_55fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (5)) { Exception (7); goto l_231036; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_231036: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (CS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_55fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (5)) { Exception (7); goto l_231037; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_231037: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (NE) */
+void REGPARAM2 CPUFUNC(op_56c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (NE) */
+void REGPARAM2 CPUFUNC(op_56c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (6)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_231039;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_231039: ;
+return;
+}
+
+/* Scc.B (An) (NE) */
+void REGPARAM2 CPUFUNC(op_56d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (NE) */
+void REGPARAM2 CPUFUNC(op_56d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (NE) */
+void REGPARAM2 CPUFUNC(op_56e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (NE) */
+void REGPARAM2 CPUFUNC(op_56e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (NE) */
+void REGPARAM2 CPUFUNC(op_56f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (NE) */
+void REGPARAM2 CPUFUNC(op_56f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (NE) */
+void REGPARAM2 CPUFUNC(op_56f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (NE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_56fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (6)) { Exception (7); goto l_231047; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_231047: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (NE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_56fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (6)) { Exception (7); goto l_231048; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_231048: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (NE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_56fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (6)) { Exception (7); goto l_231049; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_231049: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (EQ) */
+void REGPARAM2 CPUFUNC(op_57c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (EQ) */
+void REGPARAM2 CPUFUNC(op_57c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (7)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_231051;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_231051: ;
+return;
+}
+
+/* Scc.B (An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (EQ) */
+void REGPARAM2 CPUFUNC(op_57d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (EQ) */
+void REGPARAM2 CPUFUNC(op_57f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (EQ) */
+void REGPARAM2 CPUFUNC(op_57f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (EQ) */
+void REGPARAM2 CPUFUNC(op_57f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (EQ) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_57fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (7)) { Exception (7); goto l_231059; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_231059: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (EQ) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_57fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (7)) { Exception (7); goto l_231060; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_231060: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (EQ) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_57fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (7)) { Exception (7); goto l_231061; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_231061: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (VC) */
+void REGPARAM2 CPUFUNC(op_58c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (VC) */
+void REGPARAM2 CPUFUNC(op_58c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (8)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_231063;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_231063: ;
+return;
+}
+
+/* Scc.B (An) (VC) */
+void REGPARAM2 CPUFUNC(op_58d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (VC) */
+void REGPARAM2 CPUFUNC(op_58d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (VC) */
+void REGPARAM2 CPUFUNC(op_58e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (VC) */
+void REGPARAM2 CPUFUNC(op_58e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (VC) */
+void REGPARAM2 CPUFUNC(op_58f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (VC) */
+void REGPARAM2 CPUFUNC(op_58f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (VC) */
+void REGPARAM2 CPUFUNC(op_58f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (VC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_58fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (8)) { Exception (7); goto l_231071; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_231071: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (VC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_58fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (8)) { Exception (7); goto l_231072; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_231072: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (VC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_58fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (8)) { Exception (7); goto l_231073; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_231073: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (VS) */
+void REGPARAM2 CPUFUNC(op_59c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (VS) */
+void REGPARAM2 CPUFUNC(op_59c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (9)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_231075;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_231075: ;
+return;
+}
+
+/* Scc.B (An) (VS) */
+void REGPARAM2 CPUFUNC(op_59d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (VS) */
+void REGPARAM2 CPUFUNC(op_59d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (VS) */
+void REGPARAM2 CPUFUNC(op_59e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (VS) */
+void REGPARAM2 CPUFUNC(op_59e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (VS) */
+void REGPARAM2 CPUFUNC(op_59f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (VS) */
+void REGPARAM2 CPUFUNC(op_59f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (VS) */
+void REGPARAM2 CPUFUNC(op_59f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (VS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_59fa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (9)) { Exception (7); goto l_231083; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_231083: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (VS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_59fb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (9)) { Exception (7); goto l_231084; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_231084: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (VS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_59fc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (9)) { Exception (7); goto l_231085; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_231085: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (PL) */
+void REGPARAM2 CPUFUNC(op_5ac0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (PL) */
+void REGPARAM2 CPUFUNC(op_5ac8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (10)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_231087;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_231087: ;
+return;
+}
+
+/* Scc.B (An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ad0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (PL) */
+void REGPARAM2 CPUFUNC(op_5ad8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ae0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ae8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (PL) */
+void REGPARAM2 CPUFUNC(op_5af0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (PL) */
+void REGPARAM2 CPUFUNC(op_5af8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (PL) */
+void REGPARAM2 CPUFUNC(op_5af9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (PL) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5afa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (10)) { Exception (7); goto l_231095; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_231095: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (PL) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5afb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (10)) { Exception (7); goto l_231096; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_231096: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (PL) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5afc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (10)) { Exception (7); goto l_231097; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_231097: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (MI) */
+void REGPARAM2 CPUFUNC(op_5bc0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (MI) */
+void REGPARAM2 CPUFUNC(op_5bc8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (11)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_231099;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_231099: ;
+return;
+}
+
+/* Scc.B (An) (MI) */
+void REGPARAM2 CPUFUNC(op_5bd0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (MI) */
+void REGPARAM2 CPUFUNC(op_5bd8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (MI) */
+void REGPARAM2 CPUFUNC(op_5be0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (MI) */
+void REGPARAM2 CPUFUNC(op_5be8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (MI) */
+void REGPARAM2 CPUFUNC(op_5bf0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (MI) */
+void REGPARAM2 CPUFUNC(op_5bf8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (MI) */
+void REGPARAM2 CPUFUNC(op_5bf9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (MI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5bfa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (11)) { Exception (7); goto l_231107; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_231107: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (MI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5bfb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (11)) { Exception (7); goto l_231108; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_231108: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (MI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5bfc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (11)) { Exception (7); goto l_231109; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_231109: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (GE) */
+void REGPARAM2 CPUFUNC(op_5cc0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (GE) */
+void REGPARAM2 CPUFUNC(op_5cc8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (12)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_231111;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_231111: ;
+return;
+}
+
+/* Scc.B (An) (GE) */
+void REGPARAM2 CPUFUNC(op_5cd0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (GE) */
+void REGPARAM2 CPUFUNC(op_5cd8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (GE) */
+void REGPARAM2 CPUFUNC(op_5ce0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (GE) */
+void REGPARAM2 CPUFUNC(op_5ce8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (GE) */
+void REGPARAM2 CPUFUNC(op_5cf0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (GE) */
+void REGPARAM2 CPUFUNC(op_5cf8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (GE) */
+void REGPARAM2 CPUFUNC(op_5cf9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (GE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5cfa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (12)) { Exception (7); goto l_231119; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_231119: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (GE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5cfb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (12)) { Exception (7); goto l_231120; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_231120: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (GE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5cfc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (12)) { Exception (7); goto l_231121; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_231121: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (LT) */
+void REGPARAM2 CPUFUNC(op_5dc0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (LT) */
+void REGPARAM2 CPUFUNC(op_5dc8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (13)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_231123;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_231123: ;
+return;
+}
+
+/* Scc.B (An) (LT) */
+void REGPARAM2 CPUFUNC(op_5dd0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (LT) */
+void REGPARAM2 CPUFUNC(op_5dd8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (LT) */
+void REGPARAM2 CPUFUNC(op_5de0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (LT) */
+void REGPARAM2 CPUFUNC(op_5de8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (LT) */
+void REGPARAM2 CPUFUNC(op_5df0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (LT) */
+void REGPARAM2 CPUFUNC(op_5df8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (LT) */
+void REGPARAM2 CPUFUNC(op_5df9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (LT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5dfa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (13)) { Exception (7); goto l_231131; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_231131: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (LT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5dfb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (13)) { Exception (7); goto l_231132; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_231132: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (LT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5dfc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (13)) { Exception (7); goto l_231133; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_231133: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (GT) */
+void REGPARAM2 CPUFUNC(op_5ec0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (GT) */
+void REGPARAM2 CPUFUNC(op_5ec8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (14)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_231135;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_231135: ;
+return;
+}
+
+/* Scc.B (An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ed0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (GT) */
+void REGPARAM2 CPUFUNC(op_5ed8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ee0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ee8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (GT) */
+void REGPARAM2 CPUFUNC(op_5ef0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (GT) */
+void REGPARAM2 CPUFUNC(op_5ef8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (GT) */
+void REGPARAM2 CPUFUNC(op_5ef9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (GT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5efa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (14)) { Exception (7); goto l_231143; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_231143: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (GT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5efb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (14)) { Exception (7); goto l_231144; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_231144: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (GT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5efc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (14)) { Exception (7); goto l_231145; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_231145: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (LE) */
+void REGPARAM2 CPUFUNC(op_5fc0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (LE) */
+void REGPARAM2 CPUFUNC(op_5fc8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_word_ce030_prefetch (2);
+	/* OP zero */
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (15)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_231147;
+			}
+	fill_prefetch_030 ();
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+	continue_ce020_prefetch();
+}}}l_231147: ;
+return;
+}
+
+/* Scc.B (An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fd0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (LE) */
+void REGPARAM2 CPUFUNC(op_5fd8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:0,T:0,C:2 cea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fe0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fe8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (LE) */
+void REGPARAM2 CPUFUNC(op_5ff0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (LE) */
+void REGPARAM2 CPUFUNC(op_5ff8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:2,T:0,C:0 cea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (LE) */
+void REGPARAM2 CPUFUNC(op_5ff9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{	/* ea H:4,T:0,C:0 cea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (LE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5ffa_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (15)) { Exception (7); goto l_231155; }
+	regs.irc = get_word_ce030_prefetch (4);
+}}	m68k_incpci (4);
+l_231155: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (LE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5ffb_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (cctrue (15)) { Exception (7); goto l_231156; }
+	regs.irc = get_word_ce030_prefetch (6);
+}}	m68k_incpci (6);
+l_231156: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (LE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5ffc_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (15)) { Exception (7); goto l_231157; }
+	regs.irc = get_word_ce030_prefetch (2);
+}	m68k_incpci (2);
+l_231157: ;
+return;
+}
+
+#endif
+/* Bcc.W #.W (T) */
+void REGPARAM2 CPUFUNC(op_6000_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231158;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231158: ;
+return;
+}
+
+/* BccQ.B # (T) */
+void REGPARAM2 CPUFUNC(op_6001_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231159;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231159: ;
+return;
+}
+
+/* Bcc.L #.L (T) */
+void REGPARAM2 CPUFUNC(op_60ff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231160;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231160: ;
+return;
+}
+
+/* BSR.W #.W */
+void REGPARAM2 CPUFUNC(op_6100_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+{	uae_s32 s;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* op H:2,T:0,C:4 */
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_231161;
+	}
+	m68k_do_bsr_ce030 (m68k_getpci () + 4, s);
+	fill_prefetch_030 ();
+}}l_231161: ;
+return;
+}
+
+/* BSRQ.B # */
+void REGPARAM2 CPUFUNC(op_6101_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 54;
+{	uae_s32 s;
+{	uae_u32 src = srcreg;
+	/* op H:2,T:0,C:4 */
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_231162;
+	}
+	m68k_do_bsr_ce030 (m68k_getpci () + 2, s);
+	fill_prefetch_030 ();
+}}l_231162: ;
+return;
+}
+
+/* BSR.L #.L */
+void REGPARAM2 CPUFUNC(op_61ff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+{	uae_s32 s;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* op H:2,T:0,C:4 */
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_231163;
+	}
+	m68k_do_bsr_ce030 (m68k_getpci () + 6, s);
+	fill_prefetch_030 ();
+}}l_231163: ;
+return;
+}
+
+/* Bcc.W #.W (HI) */
+void REGPARAM2 CPUFUNC(op_6200_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231164;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231164: ;
+return;
+}
+
+/* BccQ.B # (HI) */
+void REGPARAM2 CPUFUNC(op_6201_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231165;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231165: ;
+return;
+}
+
+/* Bcc.L #.L (HI) */
+void REGPARAM2 CPUFUNC(op_62ff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231166;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231166: ;
+return;
+}
+
+/* Bcc.W #.W (LS) */
+void REGPARAM2 CPUFUNC(op_6300_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231167;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231167: ;
+return;
+}
+
+/* BccQ.B # (LS) */
+void REGPARAM2 CPUFUNC(op_6301_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231168;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231168: ;
+return;
+}
+
+#endif
+
+#ifdef PART_6
+/* Bcc.L #.L (LS) */
+void REGPARAM2 CPUFUNC(op_63ff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231169;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231169: ;
+return;
+}
+
+/* Bcc.W #.W (CC) */
+void REGPARAM2 CPUFUNC(op_6400_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231170;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231170: ;
+return;
+}
+
+/* BccQ.B # (CC) */
+void REGPARAM2 CPUFUNC(op_6401_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231171;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231171: ;
+return;
+}
+
+/* Bcc.L #.L (CC) */
+void REGPARAM2 CPUFUNC(op_64ff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231172;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231172: ;
+return;
+}
+
+/* Bcc.W #.W (CS) */
+void REGPARAM2 CPUFUNC(op_6500_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231173;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231173: ;
+return;
+}
+
+/* BccQ.B # (CS) */
+void REGPARAM2 CPUFUNC(op_6501_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231174;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231174: ;
+return;
+}
+
+/* Bcc.L #.L (CS) */
+void REGPARAM2 CPUFUNC(op_65ff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231175;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231175: ;
+return;
+}
+
+/* Bcc.W #.W (NE) */
+void REGPARAM2 CPUFUNC(op_6600_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231176;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231176: ;
+return;
+}
+
+/* BccQ.B # (NE) */
+void REGPARAM2 CPUFUNC(op_6601_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231177;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231177: ;
+return;
+}
+
+/* Bcc.L #.L (NE) */
+void REGPARAM2 CPUFUNC(op_66ff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231178;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231178: ;
+return;
+}
+
+/* Bcc.W #.W (EQ) */
+void REGPARAM2 CPUFUNC(op_6700_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231179;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231179: ;
+return;
+}
+
+/* BccQ.B # (EQ) */
+void REGPARAM2 CPUFUNC(op_6701_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231180;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231180: ;
+return;
+}
+
+/* Bcc.L #.L (EQ) */
+void REGPARAM2 CPUFUNC(op_67ff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231181;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231181: ;
+return;
+}
+
+/* Bcc.W #.W (VC) */
+void REGPARAM2 CPUFUNC(op_6800_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231182;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231182: ;
+return;
+}
+
+/* BccQ.B # (VC) */
+void REGPARAM2 CPUFUNC(op_6801_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231183;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231183: ;
+return;
+}
+
+/* Bcc.L #.L (VC) */
+void REGPARAM2 CPUFUNC(op_68ff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231184;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231184: ;
+return;
+}
+
+/* Bcc.W #.W (VS) */
+void REGPARAM2 CPUFUNC(op_6900_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231185;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231185: ;
+return;
+}
+
+/* BccQ.B # (VS) */
+void REGPARAM2 CPUFUNC(op_6901_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231186;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231186: ;
+return;
+}
+
+/* Bcc.L #.L (VS) */
+void REGPARAM2 CPUFUNC(op_69ff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231187;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231187: ;
+return;
+}
+
+/* Bcc.W #.W (PL) */
+void REGPARAM2 CPUFUNC(op_6a00_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231188;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231188: ;
+return;
+}
+
+/* BccQ.B # (PL) */
+void REGPARAM2 CPUFUNC(op_6a01_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231189;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231189: ;
+return;
+}
+
+/* Bcc.L #.L (PL) */
+void REGPARAM2 CPUFUNC(op_6aff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231190;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231190: ;
+return;
+}
+
+/* Bcc.W #.W (MI) */
+void REGPARAM2 CPUFUNC(op_6b00_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231191;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231191: ;
+return;
+}
+
+/* BccQ.B # (MI) */
+void REGPARAM2 CPUFUNC(op_6b01_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231192;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231192: ;
+return;
+}
+
+/* Bcc.L #.L (MI) */
+void REGPARAM2 CPUFUNC(op_6bff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231193;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231193: ;
+return;
+}
+
+/* Bcc.W #.W (GE) */
+void REGPARAM2 CPUFUNC(op_6c00_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231194;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231194: ;
+return;
+}
+
+/* BccQ.B # (GE) */
+void REGPARAM2 CPUFUNC(op_6c01_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231195;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231195: ;
+return;
+}
+
+/* Bcc.L #.L (GE) */
+void REGPARAM2 CPUFUNC(op_6cff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231196;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231196: ;
+return;
+}
+
+/* Bcc.W #.W (LT) */
+void REGPARAM2 CPUFUNC(op_6d00_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231197;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231197: ;
+return;
+}
+
+/* BccQ.B # (LT) */
+void REGPARAM2 CPUFUNC(op_6d01_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231198;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231198: ;
+return;
+}
+
+/* Bcc.L #.L (LT) */
+void REGPARAM2 CPUFUNC(op_6dff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231199;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231199: ;
+return;
+}
+
+/* Bcc.W #.W (GT) */
+void REGPARAM2 CPUFUNC(op_6e00_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231200;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231200: ;
+return;
+}
+
+/* BccQ.B # (GT) */
+void REGPARAM2 CPUFUNC(op_6e01_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231201;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231201: ;
+return;
+}
+
+/* Bcc.L #.L (GT) */
+void REGPARAM2 CPUFUNC(op_6eff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231202;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231202: ;
+return;
+}
+
+/* Bcc.W #.W (LE) */
+void REGPARAM2 CPUFUNC(op_6f00_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_word_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231203;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+	continue_ce020_prefetch();
+}}l_231203: ;
+return;
+}
+
+/* BccQ.B # (LE) */
+void REGPARAM2 CPUFUNC(op_6f01_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	/* OP zero */
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231204;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+	continue_ce020_prefetch();
+}}l_231204: ;
+return;
+}
+
+/* Bcc.L #.L (LE) */
+void REGPARAM2 CPUFUNC(op_6fff_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+	/* OP zero */
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_231205;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	fill_prefetch_030 ();
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+	continue_ce020_prefetch();
+}}l_231205: ;
+return;
+}
+
+/* MOVEQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_7000_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_u32 src = srcreg;
+{	/* op H:2,T:0,C:-2 */
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* OR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8000_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* No EA */
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_8010_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_8018_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_8020_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_8028_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_8030_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* OR.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_8038_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_8039_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_803a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_803b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* OR.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_803c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8040_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_8050_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_8058_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_8060_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_8068_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_8070_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* OR.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_8078_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_8079_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_807a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_807b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* OR.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_807c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8080_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_8090_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_8098_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_80a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_80a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* OR.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_80b8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_80b9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_80ba_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80bb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* OR.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_80bc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* DIVU.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_80c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:52 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_231240;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (52);
+}}}l_231240: ;
+return;
+}
+
+/* DIVU.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_80d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_231241;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	do_cycles_ce020_internal (52);
+}}}}l_231241: ;
+return;
+}
+
+/* DIVU.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_80d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_231242;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	do_cycles_ce020_internal (52);
+}}}}l_231242: ;
+return;
+}
+
+/* DIVU.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_80e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_231243;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+	do_cycles_ce020_internal (52);
+}}}}l_231243: ;
+return;
+}
+
+/* DIVU.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_80e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_231244;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	do_cycles_ce020_internal (52);
+}}}}l_231244: ;
+return;
+}
+
+/* DIVU.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_231245;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	do_cycles_ce020_internal (52);
+}}}}}l_231245: ;
+return;
+}
+
+/* DIVU.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_80f8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_231246;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	do_cycles_ce020_internal (52);
+}}}}l_231246: ;
+return;
+}
+
+/* DIVU.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_80f9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_231247;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (6);
+	}
+	do_cycles_ce020_internal (52);
+}}}}l_231247: ;
+return;
+}
+
+/* DIVU.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_80fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_231248;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	do_cycles_ce020_internal (52);
+}}}}l_231248: ;
+return;
+}
+
+/* DIVU.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_231249;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	do_cycles_ce020_internal (52);
+}}}}}l_231249: ;
+return;
+}
+
+/* DIVU.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_80fc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_231250;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+	do_cycles_ce020_internal (52);
+}}}l_231250: ;
+return;
+}
+
+/* SBCD.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8100_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:0,T:0,C:4 */
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SBCD.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_8108_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:10 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:10 */
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (11);
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_8110_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_8118_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_8120_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_8128_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_8130_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* OR.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_8138_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_8139_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* PACK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_8140_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+{	uae_u16 val = m68k_dreg (regs, srcreg) + get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);
+	regs.irc = get_word_ce030_prefetch (4);
+}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* PACK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_8148_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+{	uae_u16 val;
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (val | ((uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff) << 8)) + get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) -= areg_byteinc[dstreg];
+	x_put_byte (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));
+	regs.irc = get_word_ce030_prefetch (4);
+}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* OR.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_8150_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_8158_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_8160_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_8168_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_8170_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* OR.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_8178_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_8179_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* UNPK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_8180_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+{	uae_u16 val = m68k_dreg (regs, srcreg);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);
+	regs.irc = get_word_ce030_prefetch (4);
+}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* UNPK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_8188_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+{	uae_u16 val;
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];
+	x_put_byte (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);
+	x_put_byte (m68k_areg (regs, dstreg), val >> 8);
+	regs.irc = get_word_ce030_prefetch (4);
+}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* OR.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_8190_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_8198_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_81a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_81a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_81b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* OR.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_81b8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_81b9_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* DIVS.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_81c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:52 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_231278;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	regs.irc = get_word_ce030_prefetch (0);
+	do_cycles_ce020_internal (52);
+}}}l_231278: ;
+return;
+}
+
+/* DIVS.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_81d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_231279;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	do_cycles_ce020_internal (52);
+}}}}l_231279: ;
+return;
+}
+
+/* DIVS.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_81d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_231280;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	do_cycles_ce020_internal (52);
+}}}}l_231280: ;
+return;
+}
+
+/* DIVS.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_81e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_231281;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+	do_cycles_ce020_internal (52);
+}}}}l_231281: ;
+return;
+}
+
+/* DIVS.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_81e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_231282;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	do_cycles_ce020_internal (52);
+}}}}l_231282: ;
+return;
+}
+
+/* DIVS.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_81f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_231283;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	do_cycles_ce020_internal (52);
+}}}}}l_231283: ;
+return;
+}
+
+/* DIVS.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_81f8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_231284;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	do_cycles_ce020_internal (52);
+}}}}l_231284: ;
+return;
+}
+
+/* DIVS.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_81f9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_231285;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (6);
+	do_cycles_ce020_internal (52);
+}}}}l_231285: ;
+return;
+}
+
+/* DIVS.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_81fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_231286;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	do_cycles_ce020_internal (52);
+}}}}l_231286: ;
+return;
+}
+
+/* DIVS.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_81fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_231287;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	do_cycles_ce020_internal (52);
+}}}}}l_231287: ;
+return;
+}
+
+/* DIVS.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_81fc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:54 */
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_231288;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+	do_cycles_ce020_internal (52);
+}}}l_231288: ;
+return;
+}
+
+/* SUB.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9000_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_9010_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_9018_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_9020_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_9028_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_9030_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return;
+}
+
+/* SUB.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_9038_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_9039_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_903a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_903b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return;
+}
+
+/* SUB.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_903c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9040_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W An,Dn */
+void REGPARAM2 CPUFUNC(op_9048_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_9050_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_9058_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_9060_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_9068_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_9070_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return;
+}
+
+/* SUB.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_9078_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_9079_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_907a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_907b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return;
+}
+
+/* SUB.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_907c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9080_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L An,Dn */
+void REGPARAM2 CPUFUNC(op_9088_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* No EA */
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_9090_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_9098_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_90a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_90a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_90b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return;
+}
+
+/* SUB.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_90b8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_90b9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_90ba_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_90bb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return;
+}
+
+/* SUB.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_90bc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_90c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W An,An */
+void REGPARAM2 CPUFUNC(op_90c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* No EA */
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W (An),An */
+void REGPARAM2 CPUFUNC(op_90d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_90d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_90e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_90e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_90f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* SUBA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_90f8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_90f9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_90fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_90fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* SUBA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_90fc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst - src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBX.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9100_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBX.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_9108_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:6 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:6 */
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (7);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_9110_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_9118_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_9120_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_9128_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_9130_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_9138_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_9139_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBX.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9140_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBX.W -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_9148_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:6 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:6 */
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (7);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_9150_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_9158_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_9160_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_9168_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_9170_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_9178_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_9179_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBX.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9180_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBX.L -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_9188_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:6 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:6 */
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (7);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_9190_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_9198_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_91a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_91a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_91b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_91b8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_91b9_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_91c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L An,An */
+void REGPARAM2 CPUFUNC(op_91c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* No EA */
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst - src;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L (An),An */
+void REGPARAM2 CPUFUNC(op_91d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_91d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_91e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_91e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_91f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* SUBA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_91f8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_91f9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_91fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_91fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* SUBA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_91fc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b000_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* No EA */
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_b010_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_b018_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_b020_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_b028_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b030_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_b038_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_b039_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_b03a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b03b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_b03c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b040_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W An,Dn */
+void REGPARAM2 CPUFUNC(op_b048_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* No EA */
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_b050_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_b058_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_b060_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_b068_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b070_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_b078_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_b079_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_b07a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b07b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_b07c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b080_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.L An,Dn */
+void REGPARAM2 CPUFUNC(op_b088_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* No EA */
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_b090_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_b098_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_b0a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+
+#ifdef PART_7
+/* CMP.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_b0a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b0b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_b0b8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_b0b9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_b0ba_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b0bb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_b0bc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMPA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_b0c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W An,An */
+void REGPARAM2 CPUFUNC(op_b0c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* No EA */
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W (An),An */
+void REGPARAM2 CPUFUNC(op_b0d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_b0d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_b0e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_b0e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_b0f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}}return;
+}
+
+/* CMPA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_b0f8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_b0f9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMPA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_b0fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_b0fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}}return;
+}
+
+/* CMPA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_b0fc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b100_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* No EA */
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPM.B (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_b108_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+{	/* No EA */
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	/* op H:0,T:0,C:8 */
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (6);
+}}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_b110_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_b118_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_b120_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_b128_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_b130_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* EOR.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_b138_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_b139_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b140_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPM.W (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_b148_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+{	/* No EA */
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	/* op H:0,T:0,C:8 */
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (6);
+}}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_b150_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_b158_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_b160_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_b168_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_b170_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* EOR.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_b178_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_b179_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b180_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPM.L (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_b188_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+{	/* No EA */
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	/* op H:0,T:0,C:8 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (6);
+}}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_b190_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_b198_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_b1a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_b1a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_b1b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* EOR.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_b1b8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_b1b9_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMPA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_b1c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L An,An */
+void REGPARAM2 CPUFUNC(op_b1c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* No EA */
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L (An),An */
+void REGPARAM2 CPUFUNC(op_b1d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_b1d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_b1e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_b1e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_b1f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}}return;
+}
+
+/* CMPA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_b1f8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_b1f9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMPA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_b1fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_b1fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}}}return;
+}
+
+/* CMPA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_b1fc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (2);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c000_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:0 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_c010_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c018_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c020_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c028_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c030_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* AND.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c038_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c039_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c03a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c03b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* AND.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_c03c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c040_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:0 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_c050_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c058_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c060_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c068_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c070_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* AND.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c078_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c079_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c07a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c07b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* AND.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_c07c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c080_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:0 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_c090_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c098_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c0a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c0a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* AND.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c0b8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c0b9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c0ba_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0bb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* AND.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_c0bc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MULU.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c0c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MULU.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_c0d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MULU.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c0d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MULU.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c0e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MULU.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c0e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MULU.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* MULU.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c0f8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MULU.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c0f9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (6);
+}}}}}return;
+}
+
+/* MULU.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c0fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MULU.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* MULU.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_c0fc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* ABCD.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c100_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:0,T:0,C:4 */
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:0,T:0,C:4 */
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ABCD.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_c108_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:10 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:10 */
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (11);
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_c110_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_c118_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_c120_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_c128_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_c130_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* AND.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_c138_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_c139_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EXG.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c140_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* EXG.L An,An */
+void REGPARAM2 CPUFUNC(op_c148_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+{	/* No EA */
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_c150_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_c158_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_c160_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_c168_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_c170_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* AND.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_c178_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_c179_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EXG.L Dn,An */
+void REGPARAM2 CPUFUNC(op_c188_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_c190_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_c198_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_c1a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_c1a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_c1b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* AND.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_c1b8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_c1b9_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* MULS.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c1c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* MULS.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_c1d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* MULS.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c1d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* MULS.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c1e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* MULS.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c1e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* MULS.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c1f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* MULS.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c1f8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* MULS.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c1f9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* MULS.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c1fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* MULS.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c1fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* MULS.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_c1fc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+	/* op H:2,T:0,C:23 */
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	do_cycles_ce020_internal (23);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d000_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_d010_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_d018_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_d020_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_d028_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d030_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return;
+}
+
+/* ADD.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_d038_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_d039_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_d03a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d03b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return;
+}
+
+/* ADD.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_d03c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s8 src = (uae_u8)get_word_ce030_prefetch (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d040_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W An,Dn */
+void REGPARAM2 CPUFUNC(op_d048_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_d050_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_d058_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_d060_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_d068_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d070_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return;
+}
+
+/* ADD.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_d078_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_d079_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_d07a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d07b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return;
+}
+
+/* ADD.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_d07c_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d080_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L An,Dn */
+void REGPARAM2 CPUFUNC(op_d088_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* No EA */
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_d090_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_d098_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_d0a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_d0a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d0b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return;
+}
+
+/* ADD.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_d0b8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_d0b9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_d0ba_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d0bb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return;
+}
+
+/* ADD.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_d0bc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_d0c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* No EA */
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W An,An */
+void REGPARAM2 CPUFUNC(op_d0c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* No EA */
+{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:0,T:0,C:4 */
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W (An),An */
+void REGPARAM2 CPUFUNC(op_d0d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_d0d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_d0e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_d0e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_d0f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* ADDA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_d0f8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_d0f9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_d0fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_d0fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* ADDA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_d0fc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s16 src = get_word_ce030_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+	/* op H:4,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	do_cycles_ce020_internal (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDX.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d100_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDX.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_d108_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:6 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:6 */
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (7);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_d110_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_d118_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_d120_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_d128_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_d130_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_d138_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_d139_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDX.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d140_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDX.W -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_d148_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:6 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:6 */
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (7);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_d150_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_d158_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_d160_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_d168_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_d170_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_d178_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_d179_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDX.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d180_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	/* op H:2,T:0,C:0 */
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDX.L -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_d188_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	/* op H:2,T:1,C:6 */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	/* op H:2,T:1,C:6 */
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (7);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_d190_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_d198_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_d1a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_d1a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_d1b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_d1b8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_d1b9_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (2);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:1,C:2 */
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	do_cycles_ce020_internal (1);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_d1c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* No EA */
+{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L An,An */
+void REGPARAM2 CPUFUNC(op_d1c8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* No EA */
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	/* op H:2,T:0,C:0 */
+{	uae_u32 newv = dst + src;
+	regs.irc = get_word_ce030_prefetch (2);
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L (An),An */
+void REGPARAM2 CPUFUNC(op_d1d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_d1d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_d1e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_d1e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_d1f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* ADDA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_d1f8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_d1f9_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr srca;
+	srca = get_long_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_d1fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_d1fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_ce030 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* ADDA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_d1fc_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{	/* ea H:0,T:0,C:0 fea */
+	regs.ce020memcycles = 0;
+{	uae_s32 src;
+	src = get_long_ce030_prefetch (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:2 */
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ASRQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e000_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:4 */
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e008_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e010_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e018_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e020_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e028_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e030_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e038_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e040_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+
+#ifdef PART_8
+/* LSRQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e048_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e050_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e058_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e060_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e068_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e070_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e078_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e080_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:4 */
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e088_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e090_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e098_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0b8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (6);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRW.W (An) */
+void REGPARAM2 CPUFUNC(op_e0d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e0d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e0e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e0e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ASRW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e0f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ASRW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e0f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ASRW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e0f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ASLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e100_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:4 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e108_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e110_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e118_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e120_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e128_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e130_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e138_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{	/* No EA */
+{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:2 */
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e140_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e148_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e150_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e158_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e160_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e168_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e170_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e178_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{	/* No EA */
+{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:2 */
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (6);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e180_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:2,T:0,C:4 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e188_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:0 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (2);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e190_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e198_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{	/* No EA */
+{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1a0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:4,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1a8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:0 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (4);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1b0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:10,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (10);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1b8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{	/* No EA */
+{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+	/* op H:6,T:0,C:2 */
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	regs.irc = get_word_ce030_prefetch (2);
+	do_cycles_ce020_internal (6);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e1d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e1d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e1e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e1e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ASLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e1f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ASLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e1f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ASLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e1f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* LSRW.W (An) */
+void REGPARAM2 CPUFUNC(op_e2d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e2d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e2e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e2e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* LSRW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e2f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* LSRW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e2f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* LSRW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e2f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* LSLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e3d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e3d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e3e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e3e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* LSLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e3f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* LSLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e3f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* LSLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e3f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ROXRW.W (An) */
+void REGPARAM2 CPUFUNC(op_e4d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e4d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e4e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e4e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROXRW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e4f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ROXRW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e4f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROXRW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e4f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ROXLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e5d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e5d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e5e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e5e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROXLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e5f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ROXLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e5f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROXLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e5f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:4 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	do_cycles_ce020_internal (2);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* RORW.W (An) */
+void REGPARAM2 CPUFUNC(op_e6d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e6d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e6e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e6e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* RORW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e6f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* RORW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e6f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* RORW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e6f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ROLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e7d0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{	/* ea H:1,T:1,C:1 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (1);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e7d8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{	/* ea H:0,T:1,C:2 fea */
+	regs.ce020memcycles = 0;
+	do_cycles_ce020_internal (2);
+{	do_cycles_ce020_internal (1);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e7e0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	do_cycles_ce020_internal (2);
+	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+	regs.irc = get_word_ce030_prefetch (2);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e7e8_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e7f0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{	/* ea H:4,T:2,C:0 fea */
+	if (regs.ce020memcycles > 4 * cpucycleunit)
+		regs.ce020memcycles = 4 * cpucycleunit;
+{	do_cycles_ce020_internal (4);
+	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (0);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ROLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e7f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+{	/* ea H:2,T:2,C:0 fea */
+	if (regs.ce020memcycles > 2 * cpucycleunit)
+		regs.ce020memcycles = 2 * cpucycleunit;
+{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_word_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (4);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e7f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+{	/* ea H:1,T:0,C:3 fea */
+	if (regs.ce020memcycles > 1 * cpucycleunit)
+		regs.ce020memcycles = 1 * cpucycleunit;
+	do_cycles_ce020_internal (3);
+{	uaecptr dataa;
+	dataa = get_long_ce030_prefetch (2);
+{	uae_s16 data = x_get_word (dataa);
+	regs.irc = get_word_ce030_prefetch (6);
+	regs.ce020memcycles = 0;
+	/* op H:0,T:0,C:6 */
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	do_cycles_ce020_internal (4);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BFTST.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8c0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8d0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8e8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8f0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce030_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce030 (tmppc, 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFEXTU.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9c0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9d0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9e8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9f0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9f8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9f9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9fa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9fb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce030 (tmppc, 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFCHG.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eac0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFCHG.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ead0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFCHG.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eae8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFCHG.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eaf0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eaf8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eaf9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebc0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebd0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebe8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebf0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebf8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebf9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebfa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebfb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce030 (tmppc, 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFCLR.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecc0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFCLR.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecd0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFCLR.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ece8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFCLR.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecf0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecf8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecf9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edc0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edd0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ede8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edf0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edf8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edf9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce030_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edfa_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edfb_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_ce030 (tmppc, 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFSET.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eec0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFSET.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eed0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFSET.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eee8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFSET.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eef0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eef8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eef9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFINS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_efc0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFINS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_efd0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (4);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFINS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_efe8_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFINS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eff0_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_ce030 (m68k_areg (regs, dstreg), 0);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}}return;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eff8_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_word_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (6);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eff9_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+{	uaecptr dsta;
+	dsta = get_long_ce030_prefetch (4);
+	/* OP zero */
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+	regs.irc = get_word_ce030_prefetch (8);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* MMUOP030.L Dn,#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f000_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_231788; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_ce030_prefetch (2);
+	m68k_incpci (4);
+	uae_u16 extraa = 0;
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_231788;
+	regs.irc = get_word_ce030_prefetch (0);
+}}l_231788: ;
+return;
+}
+
+#endif
+/* MMUOP030.L An,#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f008_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_231789; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_ce030_prefetch (2);
+	m68k_incpci (4);
+	uae_u16 extraa = 0;
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_231789;
+	regs.irc = get_word_ce030_prefetch (0);
+}}l_231789: ;
+return;
+}
+
+#endif
+/* MMUOP030.L (An),#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f010_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_231790; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_ce030_prefetch (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	/* OP zero */
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_231790;
+	regs.irc = get_word_ce030_prefetch (0);
+}}}l_231790: ;
+return;
+}
+
+#endif
+/* MMUOP030.L (An)+,#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f018_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_231791; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_ce030_prefetch (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	/* OP zero */
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_231791;
+	regs.irc = get_word_ce030_prefetch (0);
+}}}l_231791: ;
+return;
+}
+
+#endif
+/* MMUOP030.L -(An),#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f020_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_231792; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_ce030_prefetch (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) - 4;
+	m68k_areg (regs, srcreg) = extraa;
+	/* OP zero */
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_231792;
+	regs.irc = get_word_ce030_prefetch (0);
+}}}l_231792: ;
+return;
+}
+
+#endif
+/* MMUOP030.L (d16,An),#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f028_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_231793; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_ce030_prefetch (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_word_ce030_prefetch (0);
+	/* OP zero */
+	m68k_incpci (2);
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_231793;
+	regs.irc = get_word_ce030_prefetch (0);
+}}}l_231793: ;
+return;
+}
+
+#endif
+/* MMUOP030.L (d8,An,Xn),#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f030_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_231794; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_ce030_prefetch (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+{	extraa = x_get_disp_ea_ce030 (m68k_areg (regs, srcreg), 0);
+	/* OP zero */
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_231794;
+	regs.irc = get_word_ce030_prefetch (0);
+}}}}l_231794: ;
+return;
+}
+
+#endif
+/* MMUOP030.L (xxx).W,#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f038_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_231795; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_ce030_prefetch (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = (uae_s32)(uae_s16)get_word_ce030_prefetch (0);
+	/* OP zero */
+	m68k_incpci (2);
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_231795;
+	regs.irc = get_word_ce030_prefetch (0);
+}}}l_231795: ;
+return;
+}
+
+#endif
+/* MMUOP030.L (xxx).L,#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f039_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_231796; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_word_ce030_prefetch (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = get_long_ce030_prefetch (0);
+	/* OP zero */
+	m68k_incpci (4);
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_231796;
+	regs.irc = get_word_ce030_prefetch (0);
+}}}l_231796: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f200_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_231797;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231797: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f208_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_231798;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231798: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f210_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_231799;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231799: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f218_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_231800;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231800: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f220_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_231801;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231801: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f228_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_231802;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231802: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f230_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_231803;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231803: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f238_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_231804;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231804: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f239_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_231805;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231805: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f23a_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_231806;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231806: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f23b_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_231807;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231807: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f23c_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_231808;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231808: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f240_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_231809;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231809: ;
+return;
+}
+
+#endif
+/* FDBcc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f248_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 105;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_dbcc (opcode, extra);
+	if (regs.fp_exception) goto l_231810;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_231810;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231810: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f250_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_231811;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231811: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f258_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_231812;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231812: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f260_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_231813;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231813: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f268_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_231814;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231814: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f270_23)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_231815;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231815: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f278_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_231816;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231816: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f279_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_word_ce030_prefetch (2);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_231817;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231817: ;
+return;
+}
+
+#endif
+/* FTRAPcc.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f27a_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_word_ce030_prefetch (2);
+{	uae_s16 dummy = get_word_ce030_prefetch (4);
+	/* OP zero */
+	m68k_incpci (6);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_231818;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231818: ;
+return;
+}
+
+#endif
+/* FTRAPcc.L #.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f27b_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_word_ce030_prefetch (2);
+{	uae_s32 dummy;
+	dummy = get_long_ce030_prefetch (4);
+	/* OP zero */
+	m68k_incpci (8);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_231819;
+	regs.irc = get_word_ce030_prefetch (0);
+}
+#endif
+}l_231819: ;
+return;
+}
+
+#endif
+/* FTRAPcc.L  */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f27c_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_word_ce030_prefetch (2);
+	m68k_incpci (4);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_231820;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}l_231820: ;
+return;
+}
+
+#endif
+/* FBccQ.L #,#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f280_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s16 extra = get_word_ce030_prefetch (0);
+	/* OP zero */
+	m68k_incpci (2);
+	fpuop_bcc (opcode, pc,extra);
+	if (regs.fp_exception) goto l_231821;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_231821;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}
+#endif
+}l_231821: ;
+return;
+}
+
+#endif
+/* FBccQ.L #,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f2c0_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s32 extra;
+	extra = get_long_ce030_prefetch (0);
+	/* OP zero */
+	m68k_incpci (4);
+	fpuop_bcc (opcode, pc,extra);
+	if (regs.fp_exception) goto l_231822;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_231822;
+	}
+	regs.irc = get_word_ce030_prefetch (0);
+}}
+#endif
+}l_231822: ;
+return;
+}
+
+#endif
+/* FSAVE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f310_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_231823; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_231823;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}}l_231823: ;
+return;
+}
+
+#endif
+/* FSAVE.L -(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f320_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_231824; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_231824;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}}l_231824: ;
+return;
+}
+
+#endif
+/* FSAVE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f328_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_231825; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_231825;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}}l_231825: ;
+return;
+}
+
+#endif
+/* FSAVE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f330_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_231826; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_231826;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}}l_231826: ;
+return;
+}
+
+#endif
+/* FSAVE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f338_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_231827; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_231827;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}}l_231827: ;
+return;
+}
+
+#endif
+/* FSAVE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f339_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_231828; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_231828;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}}l_231828: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f350_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_231829; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_231829;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}}l_231829: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f358_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_231830; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_231830;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}}l_231830: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f368_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_231831; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_231831;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}}l_231831: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f370_23)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_231832; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_231832;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}}l_231832: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f378_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_231833; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_231833;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}}l_231833: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f379_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_231834; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_231834;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}}l_231834: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f37a_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_231835; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_231835;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}}l_231835: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f37b_23)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_231836; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_231836;
+	regs.irc = get_word_ce030_prefetch (0);
+
+#endif
+}}l_231836: ;
+return;
+}
+
+#endif
+#endif
+
diff --git a/src/cpu/cpuemu_24.c b/src/cpu/cpuemu_24.c
new file mode 100644
index 0000000..bc0b1cc
--- /dev/null
+++ b/src/cpu/cpuemu_24.c
@@ -0,0 +1,36645 @@
+#include "main.h"
+#include "sysdeps.h"
+#include "hatari-glue.h"
+#include "maccess.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "cputbl.h"
+#define CPUFUNC(x) x##_ff
+#define SET_CFLG_ALWAYS(x) SET_CFLG(x)
+#define SET_NFLG_ALWAYS(x) SET_NFLG(x)
+#ifdef NOFLAGS
+#include "noflags.h"
+#endif
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+/* OR.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0000_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0010_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0018_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0020_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0028_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0030_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* OR.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0038_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0039_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* ORSR.B #.W */
+void REGPARAM2 CPUFUNC(op_003c_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+{	MakeSR ();
+{	uae_s16 src = get_iword_cache_040 (2);
+	src &= 0xFF;
+	regs.sr |= src;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0040_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0050_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0058_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0060_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0068_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0070_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* OR.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0078_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0079_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* ORSR.W #.W */
+void REGPARAM2 CPUFUNC(op_007c_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+{if (!regs.s) { Exception (8); goto l_240018; }
+{	MakeSR ();
+{	uae_s16 src = get_iword_cache_040 (2);
+	regs.sr |= src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_240018: ;
+return;
+}
+
+/* OR.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0080_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0090_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0098_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_00a0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_00a8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* OR.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_00b0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* OR.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_00b8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* OR.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_00b9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return;
+}
+
+/* CHK2.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00d0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240027; }
+}
+}}}	m68k_incpci (4);
+l_240027: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00e8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240028; }
+}
+}}}	m68k_incpci (6);
+l_240028: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00f0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240029; }
+}
+}}}}l_240029: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240030; }
+}
+}}}	m68k_incpci (6);
+l_240030: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240031; }
+}
+}}}	m68k_incpci (8);
+l_240031: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240032; }
+}
+}}}	m68k_incpci (6);
+l_240032: ;
+return;
+}
+
+#endif
+/* CHK2.B #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_00fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_040 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240033; }
+}
+}}}}l_240033: ;
+return;
+}
+
+#endif
+/* BTST.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_0100_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVPMR.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_0108_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_u16 val;
+	MovepByteNbr=1; val = ((x_get_byte (memp) & 0xff) << 8);
+	MovepByteNbr=2; val += (x_get_byte (memp + 2) & 0xff);
+	MovepByteNbr=0;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_0110_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BTST.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_0118_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BTST.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_0120_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BTST.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0128_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0130_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return;
+}
+
+/* BTST.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0138_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0139_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BTST.B Dn,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_013a_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 2;
+	dsta += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B Dn,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_013b_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return;
+}
+
+/* BTST.B Dn,#.B */
+void REGPARAM2 CPUFUNC(op_013c_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = (uae_u8)get_iword_cache_040 (2);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_0140_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVPMR.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_0148_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_u32 val;
+	MovepByteNbr=1; val = ((x_get_byte (memp) & 0xff) << 24);
+	MovepByteNbr=2; val += ((x_get_byte (memp + 2) & 0xff) << 16);
+	MovepByteNbr=3; val += ((x_get_byte (memp + 4) & 0xff) << 8);
+	MovepByteNbr=4; val += (x_get_byte (memp + 6) & 0xff);
+	MovepByteNbr=0;
+	m68k_dreg (regs, dstreg) = (val);
+}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_0150_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCHG.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_0158_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCHG.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_0160_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCHG.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0168_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0170_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BCHG.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0178_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0179_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCLR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_0180_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVPRM.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0188_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	MovepByteNbr=1; 	x_put_byte (memp, src >> 8);
+	MovepByteNbr=2; 	x_put_byte (memp + 2, src);
+	MovepByteNbr=0;
+}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_0190_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCLR.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_0198_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCLR.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_01a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BCLR.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_01a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_01b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BCLR.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_01b8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_01b9_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BSET.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_01c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVPRM.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_01c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	MovepByteNbr=1; 	x_put_byte (memp, src >> 24);
+	MovepByteNbr=2; 	x_put_byte (memp + 2, src >> 16);
+	MovepByteNbr=3; 	x_put_byte (memp + 4, src >> 8);
+	MovepByteNbr=4; 	x_put_byte (memp + 6, src);
+	MovepByteNbr=0;
+}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_01d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BSET.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_01d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BSET.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_01e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* BSET.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_01e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_01f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BSET.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_01f8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_01f9_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0200_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0210_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0218_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0220_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0228_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0230_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* AND.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0238_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0239_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* ANDSR.B #.W */
+void REGPARAM2 CPUFUNC(op_023c_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+{	MakeSR ();
+{	uae_s16 src = get_iword_cache_040 (2);
+	src |= 0xFF00;
+	regs.sr &= src;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0240_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0250_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0258_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0260_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0268_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0270_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* AND.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0278_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0279_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* ANDSR.W #.W */
+void REGPARAM2 CPUFUNC(op_027c_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+{if (!regs.s) { Exception (8); goto l_240090; }
+{	MakeSR ();
+{	uae_s16 src = get_iword_cache_040 (2);
+	regs.sr &= src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_240090: ;
+return;
+}
+
+/* AND.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0280_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0290_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0298_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_02a0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_02a8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* AND.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_02b0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* AND.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_02b8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* AND.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_02b9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return;
+}
+
+/* CHK2.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02d0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240099; }
+}
+}}}	m68k_incpci (4);
+l_240099: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02e8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240100; }
+}
+}}}	m68k_incpci (6);
+l_240100: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02f0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240101; }
+}
+}}}}l_240101: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240102; }
+}
+}}}	m68k_incpci (6);
+l_240102: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240103; }
+}
+}}}	m68k_incpci (8);
+l_240103: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240104; }
+}
+}}}	m68k_incpci (6);
+l_240104: ;
+return;
+}
+
+#endif
+/* CHK2.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_02fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_040 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240105; }
+}
+}}}}l_240105: ;
+return;
+}
+
+#endif
+/* SUB.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0400_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0410_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0418_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0420_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0428_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0430_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0438_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0439_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* SUB.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0440_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0450_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0458_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0460_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0468_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0470_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0478_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0479_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* SUB.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0480_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0490_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0498_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_04a0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_04a8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* SUB.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_04b0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_04b8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* SUB.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_04b9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (10);
+return;
+}
+
+/* CHK2.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04d0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240130; }
+}
+}}}	m68k_incpci (4);
+l_240130: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04e8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240131; }
+}
+}}}	m68k_incpci (6);
+l_240131: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04f0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240132; }
+}
+}}}}l_240132: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240133; }
+}
+}}}	m68k_incpci (6);
+l_240133: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240134; }
+}
+}}}	m68k_incpci (8);
+l_240134: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240135; }
+}
+}}}	m68k_incpci (6);
+l_240135: ;
+return;
+}
+
+#endif
+/* CHK2.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_04fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_040 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_240136; }
+}
+}}}}l_240136: ;
+return;
+}
+
+#endif
+/* ADD.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0600_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0610_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0618_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0620_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0628_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0630_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0638_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0639_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* ADD.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0640_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0650_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0658_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0660_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0668_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0670_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0678_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0679_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* ADD.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0680_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0690_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0698_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_06a0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_06a8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* ADD.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_06b0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_06b8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* ADD.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_06b9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (10);
+return;
+}
+
+/* RTM.L Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return;
+}
+
+#endif
+/* RTM.L An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return;
+}
+
+#endif
+/* CALLM.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return;
+}
+
+#endif
+/* CALLM.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return;
+}
+
+#endif
+/* CALLM.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return;
+}
+
+#endif
+/* CALLM.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return;
+}
+
+#endif
+/* CALLM.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return;
+}
+
+#endif
+/* CALLM.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return;
+}
+
+#endif
+/* CALLM.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_06fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return;
+}
+
+#endif
+/* BTST.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0800_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0810_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0818_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0820_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BTST.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0828_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BTST.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0830_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return;
+}
+
+/* BTST.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0838_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BTST.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0839_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* BTST.B #.W,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_083a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BTST.B #.W,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_083b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return;
+}
+
+/* BCHG.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0840_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0850_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0858_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0860_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCHG.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0868_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCHG.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0870_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BCHG.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0878_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCHG.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0879_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* BCLR.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0880_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0890_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0898_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_08a0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BCLR.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_08a8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCLR.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_08b0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BCLR.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_08b8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BCLR.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_08b9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* BSET.L #.W,Dn */
+void REGPARAM2 CPUFUNC(op_08c0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B #.W,(An) */
+void REGPARAM2 CPUFUNC(op_08d0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_08d8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_08e0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* BSET.B #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_08e8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BSET.B #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_08f0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}}return;
+}
+
+/* BSET.B #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_08f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BSET.B #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_08f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EOR.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0a00_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0a10_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0a18_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0a20_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0a28_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0a30_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* EOR.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0a38_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0a39_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EORSR.B #.W */
+void REGPARAM2 CPUFUNC(op_0a3c_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+{	MakeSR ();
+{	uae_s16 src = get_iword_cache_040 (2);
+	src &= 0xFF;
+	regs.sr ^= src;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0a40_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0a50_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0a58_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0a60_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0a68_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0a70_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* EOR.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0a78_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0a79_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EORSR.W #.W */
+void REGPARAM2 CPUFUNC(op_0a7c_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+{if (!regs.s) { Exception (8); goto l_240221; }
+{	MakeSR ();
+{	uae_s16 src = get_iword_cache_040 (2);
+	regs.sr ^= src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_240221: ;
+return;
+}
+
+/* EOR.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0a80_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0a90_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0a98_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_0aa0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0aa8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EOR.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0ab0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* EOR.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0ab8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (8);
+return;
+}
+
+/* EOR.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0ab9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (10);
+return;
+}
+
+/* CAS.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ad0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ad8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ae0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* CAS.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ae8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+#endif
+
+#ifdef PART_2
+/* CAS.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0af0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}}return;
+}
+
+#endif
+/* CAS.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0af8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CAS.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0af9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* CMP.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_0c00_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_0c10_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_0c18_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_0c20_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0c28_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0c30_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0c38_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0c39_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* CMP.B #.B,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0c3a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CMP.B #.B,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0c3b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+#endif
+/* CMP.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_0c40_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_0c50_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_0c58_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_0c60_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0c68_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0c70_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0c78_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0c79_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* CMP.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0c7a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* CMP.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0c7b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+#endif
+/* CMP.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_0c80_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_0c90_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_0c98_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_0ca0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_0ca8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* CMP.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_0cb0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_0cb8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+/* CMP.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_0cb9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (10);
+return;
+}
+
+/* CMP.L #.L,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cba_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 6;
+	dsta += (uae_s32)(uae_s16)get_iword_cache_040 (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* CMP.L #.L,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cbb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (6);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+#endif
+/* CAS.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cd0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (4);
+		op_unimpl (opcode);
+		goto l_240267;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_240267: ;
+return;
+}
+
+#endif
+/* CAS.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cd8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) -= 2;
+	m68k_incpci (4);
+		op_unimpl (opcode);
+		goto l_240268;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_240268: ;
+return;
+}
+
+#endif
+/* CAS.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ce0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) += 2;
+	m68k_incpci (4);
+		op_unimpl (opcode);
+		goto l_240269;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_240269: ;
+return;
+}
+
+#endif
+/* CAS.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ce8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (6);
+		op_unimpl (opcode);
+		goto l_240270;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+l_240270: ;
+return;
+}
+
+#endif
+/* CAS.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cf0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		op_unimpl (opcode);
+		goto l_240271;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}}l_240271: ;
+return;
+}
+
+#endif
+/* CAS.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cf8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (6);
+		op_unimpl (opcode);
+		goto l_240272;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+l_240272: ;
+return;
+}
+
+#endif
+/* CAS.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cf9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s16 dst = x_get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (8);
+		op_unimpl (opcode);
+		goto l_240273;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (8);
+l_240273: ;
+return;
+}
+
+#endif
+/* CAS2.W #.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0cfc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+{{	uae_s32 extra;
+	extra = get_ilong_cache_040 (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u16 dst1 = x_get_word (rn1), dst2 = x_get_word (rn2);
+{uae_u32 newv = ((uae_u16)(dst1)) - ((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s16)(dst1)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u16)(dst2)) - ((uae_u16)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s16)(dst2)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, extra & 7))) > ((uae_u16)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	x_put_word (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	x_put_word (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);
+	m68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);
+	}
+}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* MOVES.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e10_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240275; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (4);
+l_240275: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e18_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240276; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (4);
+l_240276: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e20_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240277; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (4);
+l_240277: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e28_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240278; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (6);
+l_240278: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e30_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240279; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	x_put_byte (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 1);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}}l_240279: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e38_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240280; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (6);
+l_240280: ;
+return;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e39_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240281; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_ilong_cache_040 (4);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (8);
+l_240281: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e50_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240282; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (4);
+l_240282: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e58_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240283; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, dstreg) += 2;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (4);
+l_240283: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e60_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240284; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (4);
+l_240284: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e68_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240285; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (6);
+l_240285: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e70_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240286; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	x_put_word (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 1);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}}l_240286: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e78_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240287; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (6);
+l_240287: ;
+return;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e79_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240288; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_ilong_cache_040 (4);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (8);
+l_240288: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e90_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240289; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (4);
+l_240289: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0e98_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240290; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, dstreg) += 4;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (4);
+l_240290: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ea0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240291; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (4);
+l_240291: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ea8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240292; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (6);
+l_240292: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0eb0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240293; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	x_put_long (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 1);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}}l_240293: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0eb8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240294; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (6);
+l_240294: ;
+return;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0eb9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+{if (!regs.s) { Exception (8); goto l_240295; }
+{{	uae_s16 extra = get_iword_cache_040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_ilong_cache_040 (4);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (8);
+l_240295: ;
+return;
+}
+
+#endif
+/* CAS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ed0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (4);
+		op_unimpl (opcode);
+		goto l_240296;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+l_240296: ;
+return;
+}
+
+#endif
+/* CAS.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ed8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) -= 4;
+	m68k_incpci (4);
+		op_unimpl (opcode);
+		goto l_240297;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+l_240297: ;
+return;
+}
+
+#endif
+/* CAS.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ee0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+		op_unimpl (opcode);
+		goto l_240298;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+l_240298: ;
+return;
+}
+
+#endif
+/* CAS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ee8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s32 dst = x_get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (6);
+		op_unimpl (opcode);
+		goto l_240299;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (6);
+l_240299: ;
+return;
+}
+
+#endif
+/* CAS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ef0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		op_unimpl (opcode);
+		goto l_240300;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}}l_240300: ;
+return;
+}
+
+#endif
+/* CAS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ef8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s32 dst = x_get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (6);
+		op_unimpl (opcode);
+		goto l_240301;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (6);
+l_240301: ;
+return;
+}
+
+#endif
+/* CAS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0ef9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s32 dst = x_get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (8);
+		op_unimpl (opcode);
+		goto l_240302;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (8);
+l_240302: ;
+return;
+}
+
+#endif
+/* CAS2.L #.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_0efc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+{{	uae_s32 extra;
+	extra = get_ilong_cache_040 (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u32 dst1 = x_get_long (rn1), dst2 = x_get_long (rn2);
+{uae_u32 newv = ((uae_u32)(dst1)) - ((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s32)(dst1)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u32)(dst2)) - ((uae_u32)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s32)(dst2)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, extra & 7))) > ((uae_u32)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	x_put_long (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	x_put_long (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = dst2;
+	m68k_dreg (regs, (extra >> 22) & 7) = dst1;
+	}
+}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* MOVE.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_1000_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_1010_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_1018_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_1020_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_1028_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_1030_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_1038_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_1039_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_103a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_103b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* MOVE.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_103c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_1080_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.B (An),(An) */
+void REGPARAM2 CPUFUNC(op_1090_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(An) */
+void REGPARAM2 CPUFUNC(op_1098_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B -(An),(An) */
+void REGPARAM2 CPUFUNC(op_10a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(An) */
+void REGPARAM2 CPUFUNC(op_10a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_10b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(An) */
+void REGPARAM2 CPUFUNC(op_10b8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(An) */
+void REGPARAM2 CPUFUNC(op_10b9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(An) */
+void REGPARAM2 CPUFUNC(op_10ba_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_10bb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(An) */
+void REGPARAM2 CPUFUNC(op_10bc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_10c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.B (An),(An)+ */
+void REGPARAM2 CPUFUNC(op_10d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_10d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B -(An),(An)+ */
+void REGPARAM2 CPUFUNC(op_10e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(An)+ */
+void REGPARAM2 CPUFUNC(op_10e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_10f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(An)+ */
+void REGPARAM2 CPUFUNC(op_10f8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(An)+ */
+void REGPARAM2 CPUFUNC(op_10f9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(An)+ */
+void REGPARAM2 CPUFUNC(op_10fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_10fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(An)+ */
+void REGPARAM2 CPUFUNC(op_10fc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_1100_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.B (An),-(An) */
+void REGPARAM2 CPUFUNC(op_1110_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (An)+,-(An) */
+void REGPARAM2 CPUFUNC(op_1118_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_1120_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),-(An) */
+void REGPARAM2 CPUFUNC(op_1128_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_1130_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,-(An) */
+void REGPARAM2 CPUFUNC(op_1138_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,-(An) */
+void REGPARAM2 CPUFUNC(op_1139_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),-(An) */
+void REGPARAM2 CPUFUNC(op_113a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_113b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B #.B,-(An) */
+void REGPARAM2 CPUFUNC(op_113c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1140_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B (An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1150_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1158_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B -(An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1160_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1168_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_1170_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1178_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_1179_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(d16,An) */
+void REGPARAM2 CPUFUNC(op_117a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_117b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(d16,An) */
+void REGPARAM2 CPUFUNC(op_117c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_1180_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}return;
+}
+
+/* MOVE.B (An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_1190_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_1198_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B -(An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11b8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11b9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11ba_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11bb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.B #.B,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_11bc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}return;
+}
+
+/* MOVE.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.B (An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B -(An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_11fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(xxx).W */
+void REGPARAM2 CPUFUNC(op_11fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.B (An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (An)+,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B -(An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.B (d16,An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.B (xxx).W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (xxx).L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (10);
+}}}}return;
+}
+
+/* MOVE.B (d16,PC),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_13fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.B #.B,(xxx).L */
+void REGPARAM2 CPUFUNC(op_13fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpci (8);
+}}}return;
+}
+
+/* MOVE.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_2000_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L An,Dn */
+void REGPARAM2 CPUFUNC(op_2008_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_2010_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_2018_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_2020_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_2028_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_2030_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_2038_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_2039_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_203a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_203b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* MOVE.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_203c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVEA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_2040_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVEA.L An,An */
+void REGPARAM2 CPUFUNC(op_2048_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVEA.L (An),An */
+void REGPARAM2 CPUFUNC(op_2050_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_2058_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_2060_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_2068_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_2070_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* MOVEA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_2078_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_2079_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVEA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_207a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_207b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* MOVEA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_207c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_2080_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L An,(An) */
+void REGPARAM2 CPUFUNC(op_2088_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L (An),(An) */
+void REGPARAM2 CPUFUNC(op_2090_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(An) */
+void REGPARAM2 CPUFUNC(op_2098_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L -(An),(An) */
+void REGPARAM2 CPUFUNC(op_20a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(An) */
+void REGPARAM2 CPUFUNC(op_20a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_20b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(An) */
+void REGPARAM2 CPUFUNC(op_20b8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(An) */
+void REGPARAM2 CPUFUNC(op_20b9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(An) */
+void REGPARAM2 CPUFUNC(op_20ba_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_20bb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(An) */
+void REGPARAM2 CPUFUNC(op_20bc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_20c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L An,(An)+ */
+void REGPARAM2 CPUFUNC(op_20c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L (An),(An)+ */
+void REGPARAM2 CPUFUNC(op_20d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_20d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L -(An),(An)+ */
+void REGPARAM2 CPUFUNC(op_20e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(An)+ */
+void REGPARAM2 CPUFUNC(op_20e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_20f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(An)+ */
+void REGPARAM2 CPUFUNC(op_20f8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(An)+ */
+void REGPARAM2 CPUFUNC(op_20f9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(An)+ */
+void REGPARAM2 CPUFUNC(op_20fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_20fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(An)+ */
+void REGPARAM2 CPUFUNC(op_20fc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_2100_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L An,-(An) */
+void REGPARAM2 CPUFUNC(op_2108_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.L (An),-(An) */
+void REGPARAM2 CPUFUNC(op_2110_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (An)+,-(An) */
+void REGPARAM2 CPUFUNC(op_2118_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_2120_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),-(An) */
+void REGPARAM2 CPUFUNC(op_2128_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_2130_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,-(An) */
+void REGPARAM2 CPUFUNC(op_2138_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,-(An) */
+void REGPARAM2 CPUFUNC(op_2139_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),-(An) */
+void REGPARAM2 CPUFUNC(op_213a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_213b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L #.L,-(An) */
+void REGPARAM2 CPUFUNC(op_213c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2140_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.L An,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2148_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.L (An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2150_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2158_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L -(An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2160_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2168_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_2170_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2178_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_2179_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(d16,An) */
+void REGPARAM2 CPUFUNC(op_217a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_217b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_217c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}return;
+}
+
+/* MOVE.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2180_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}return;
+}
+
+/* MOVE.L An,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2188_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}return;
+}
+
+/* MOVE.L (An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2190_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_2198_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+#endif
+
+#ifdef PART_3
+/* MOVE.L -(An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21b8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21b9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21ba_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21bb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.L #.L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_21bc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}return;
+}
+
+/* MOVE.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.L An,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.L (An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L -(An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_21fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_21fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}return;
+}
+
+/* MOVE.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L An,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.L (An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (An)+,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L -(An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.L (d16,An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.L (xxx).W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (xxx).L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (10);
+}}}}return;
+}
+
+/* MOVE.L (d16,PC),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_23fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.L #.L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_23fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpci (10);
+}}}return;
+}
+
+/* MOVE.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_3000_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W An,Dn */
+void REGPARAM2 CPUFUNC(op_3008_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_3010_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_3018_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_3020_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_3028_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_3030_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_3038_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_3039_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_303a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_303b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* MOVE.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_303c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVEA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_3040_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVEA.W An,An */
+void REGPARAM2 CPUFUNC(op_3048_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVEA.W (An),An */
+void REGPARAM2 CPUFUNC(op_3050_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_3058_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_3060_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVEA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_3068_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_3070_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return;
+}
+
+/* MOVEA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_3078_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_3079_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVEA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_307a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVEA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_307b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return;
+}
+
+/* MOVEA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_307c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_3080_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W An,(An) */
+void REGPARAM2 CPUFUNC(op_3088_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W (An),(An) */
+void REGPARAM2 CPUFUNC(op_3090_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(An) */
+void REGPARAM2 CPUFUNC(op_3098_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W -(An),(An) */
+void REGPARAM2 CPUFUNC(op_30a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(An) */
+void REGPARAM2 CPUFUNC(op_30a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_30b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(An) */
+void REGPARAM2 CPUFUNC(op_30b8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(An) */
+void REGPARAM2 CPUFUNC(op_30b9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(An) */
+void REGPARAM2 CPUFUNC(op_30ba_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(An) */
+void REGPARAM2 CPUFUNC(op_30bb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_30bc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_30c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W An,(An)+ */
+void REGPARAM2 CPUFUNC(op_30c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W (An),(An)+ */
+void REGPARAM2 CPUFUNC(op_30d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_30d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W -(An),(An)+ */
+void REGPARAM2 CPUFUNC(op_30e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(An)+ */
+void REGPARAM2 CPUFUNC(op_30e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_30f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(An)+ */
+void REGPARAM2 CPUFUNC(op_30f8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(An)+ */
+void REGPARAM2 CPUFUNC(op_30f9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(An)+ */
+void REGPARAM2 CPUFUNC(op_30fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+void REGPARAM2 CPUFUNC(op_30fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_30fc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_3100_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W An,-(An) */
+void REGPARAM2 CPUFUNC(op_3108_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* MOVE.W (An),-(An) */
+void REGPARAM2 CPUFUNC(op_3110_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (An)+,-(An) */
+void REGPARAM2 CPUFUNC(op_3118_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_3120_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),-(An) */
+void REGPARAM2 CPUFUNC(op_3128_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_3130_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,-(An) */
+void REGPARAM2 CPUFUNC(op_3138_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,-(An) */
+void REGPARAM2 CPUFUNC(op_3139_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),-(An) */
+void REGPARAM2 CPUFUNC(op_313a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+void REGPARAM2 CPUFUNC(op_313b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_313c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3140_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W An,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3148_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W (An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3150_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3158_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W -(An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3160_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3168_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_3170_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3178_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(d16,An) */
+void REGPARAM2 CPUFUNC(op_3179_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(d16,An) */
+void REGPARAM2 CPUFUNC(op_317a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+void REGPARAM2 CPUFUNC(op_317b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_317c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3180_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}return;
+}
+
+/* MOVE.W An,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3188_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}return;
+}
+
+/* MOVE.W (An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3190_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_3198_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W -(An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31b8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31b9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31ba_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31bb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}}return;
+}
+
+/* MOVE.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_31bc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}return;
+}
+
+/* MOVE.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W An,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}return;
+}
+
+/* MOVE.W (An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W -(An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+void REGPARAM2 CPUFUNC(op_31fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_31fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.W An,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}return;
+}
+
+/* MOVE.W (An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (An)+,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W -(An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (6);
+}}}}return;
+}
+
+/* MOVE.W (d16,An),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.W (xxx).W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (xxx).L,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (10);
+}}}}return;
+}
+
+/* MOVE.W (d16,PC),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}}return;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+void REGPARAM2 CPUFUNC(op_33fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MOVE.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_33fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpci (8);
+}}}return;
+}
+
+/* NEGX.B Dn */
+void REGPARAM2 CPUFUNC(op_4000_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.B (An) */
+void REGPARAM2 CPUFUNC(op_4010_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4018_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.B -(An) */
+void REGPARAM2 CPUFUNC(op_4020_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4028_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4030_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}}return;
+}
+
+/* NEGX.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4038_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4039_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* NEGX.W Dn */
+void REGPARAM2 CPUFUNC(op_4040_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.W (An) */
+void REGPARAM2 CPUFUNC(op_4050_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4058_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.W -(An) */
+void REGPARAM2 CPUFUNC(op_4060_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4068_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4070_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}}return;
+}
+
+/* NEGX.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4078_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4079_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* NEGX.L Dn */
+void REGPARAM2 CPUFUNC(op_4080_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.L (An) */
+void REGPARAM2 CPUFUNC(op_4090_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4098_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.L -(An) */
+void REGPARAM2 CPUFUNC(op_40a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEGX.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_40a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_40b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}}return;
+}
+
+/* NEGX.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_40b8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEGX.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_40b9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* MVSR2.W Dn */
+void REGPARAM2 CPUFUNC(op_40c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_240632; }
+{{	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}}	m68k_incpci (2);
+l_240632: ;
+return;
+}
+
+/* MVSR2.W (An) */
+void REGPARAM2 CPUFUNC(op_40d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_240633; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_240633: ;
+return;
+}
+
+/* MVSR2.W (An)+ */
+void REGPARAM2 CPUFUNC(op_40d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_240634; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_240634: ;
+return;
+}
+
+/* MVSR2.W -(An) */
+void REGPARAM2 CPUFUNC(op_40e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_240635; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_240635: ;
+return;
+}
+
+/* MVSR2.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_40e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_240636; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_240636: ;
+return;
+}
+
+/* MVSR2.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_40f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_240637; }
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}}l_240637: ;
+return;
+}
+
+/* MVSR2.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_40f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_240638; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_240638: ;
+return;
+}
+
+/* MVSR2.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_40f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+{if (!regs.s) { Exception (8); goto l_240639; }
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpci (6);
+l_240639: ;
+return;
+}
+
+/* CHK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4100_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240640;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240640;
+	}
+}}}l_240640: ;
+return;
+}
+
+#endif
+/* CHK.L (An),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4110_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240641;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240641;
+	}
+}}}}l_240641: ;
+return;
+}
+
+#endif
+/* CHK.L (An)+,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4118_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240642;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240642;
+	}
+}}}}l_240642: ;
+return;
+}
+
+#endif
+/* CHK.L -(An),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4120_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240643;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240643;
+	}
+}}}}l_240643: ;
+return;
+}
+
+#endif
+/* CHK.L (d16,An),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4128_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240644;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240644;
+	}
+}}}}l_240644: ;
+return;
+}
+
+#endif
+/* CHK.L (d8,An,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4130_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240645;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240645;
+	}
+}}}}}l_240645: ;
+return;
+}
+
+#endif
+/* CHK.L (xxx).W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4138_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240646;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240646;
+	}
+}}}}l_240646: ;
+return;
+}
+
+#endif
+/* CHK.L (xxx).L,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4139_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240647;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240647;
+	}
+}}}}l_240647: ;
+return;
+}
+
+#endif
+/* CHK.L (d16,PC),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_413a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240648;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240648;
+	}
+}}}}l_240648: ;
+return;
+}
+
+#endif
+/* CHK.L (d8,PC,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_413b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240649;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240649;
+	}
+}}}}}l_240649: ;
+return;
+}
+
+#endif
+/* CHK.L #.L,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_413c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240650;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240650;
+	}
+}}}l_240650: ;
+return;
+}
+
+#endif
+/* CHK.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_4180_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240651;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240651;
+	}
+}}}l_240651: ;
+return;
+}
+
+/* CHK.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_4190_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240652;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240652;
+	}
+}}}}l_240652: ;
+return;
+}
+
+/* CHK.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_4198_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240653;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240653;
+	}
+}}}}l_240653: ;
+return;
+}
+
+/* CHK.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_41a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240654;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240654;
+	}
+}}}}l_240654: ;
+return;
+}
+
+/* CHK.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_41a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240655;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240655;
+	}
+}}}}l_240655: ;
+return;
+}
+
+/* CHK.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_41b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240656;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240656;
+	}
+}}}}}l_240656: ;
+return;
+}
+
+/* CHK.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_41b8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240657;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240657;
+	}
+}}}}l_240657: ;
+return;
+}
+
+/* CHK.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_41b9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240658;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240658;
+	}
+}}}}l_240658: ;
+return;
+}
+
+/* CHK.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_41ba_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240659;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240659;
+	}
+}}}}l_240659: ;
+return;
+}
+
+/* CHK.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_41bb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240660;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240660;
+	}
+}}}}}l_240660: ;
+return;
+}
+
+/* CHK.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_41bc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_240661;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_240661;
+	}
+}}}l_240661: ;
+return;
+}
+
+/* LEA.L (An),An */
+void REGPARAM2 CPUFUNC(op_41d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* LEA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_41e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* LEA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_41f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}}return;
+}
+
+/* LEA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_41f8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* LEA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_41f9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* LEA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_41fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* LEA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_41fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}}return;
+}
+
+/* CLR.B Dn */
+void REGPARAM2 CPUFUNC(op_4200_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.B (An) */
+void REGPARAM2 CPUFUNC(op_4210_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4218_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.B -(An) */
+void REGPARAM2 CPUFUNC(op_4220_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4228_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4230_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}}return;
+}
+
+/* CLR.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4238_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4239_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}	m68k_incpci (6);
+return;
+}
+
+/* CLR.W Dn */
+void REGPARAM2 CPUFUNC(op_4240_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.W (An) */
+void REGPARAM2 CPUFUNC(op_4250_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4258_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.W -(An) */
+void REGPARAM2 CPUFUNC(op_4260_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4268_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4270_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}}return;
+}
+
+/* CLR.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4278_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4279_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}	m68k_incpci (6);
+return;
+}
+
+/* CLR.L Dn */
+void REGPARAM2 CPUFUNC(op_4280_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.L (An) */
+void REGPARAM2 CPUFUNC(op_4290_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4298_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.L -(An) */
+void REGPARAM2 CPUFUNC(op_42a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* CLR.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_42a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_42b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}}return;
+}
+
+/* CLR.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_42b8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}	m68k_incpci (4);
+return;
+}
+
+/* CLR.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_42b9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}	m68k_incpci (6);
+return;
+}
+
+/* MVSR2.B Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{{	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* MVSR2.B (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* MVSR2.B (An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* MVSR2.B -(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* MVSR2.B (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* MVSR2.B (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}}return;
+}
+
+#endif
+/* MVSR2.B (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* MVSR2.B (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_42f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* NEG.B Dn */
+void REGPARAM2 CPUFUNC(op_4400_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+
+#ifdef PART_4
+/* NEG.B (An) */
+void REGPARAM2 CPUFUNC(op_4410_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4418_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.B -(An) */
+void REGPARAM2 CPUFUNC(op_4420_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4428_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4430_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}}return;
+}
+
+/* NEG.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4438_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4439_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* NEG.W Dn */
+void REGPARAM2 CPUFUNC(op_4440_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.W (An) */
+void REGPARAM2 CPUFUNC(op_4450_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4458_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.W -(An) */
+void REGPARAM2 CPUFUNC(op_4460_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4468_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4470_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}}return;
+}
+
+/* NEG.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4478_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4479_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* NEG.L Dn */
+void REGPARAM2 CPUFUNC(op_4480_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.L (An) */
+void REGPARAM2 CPUFUNC(op_4490_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4498_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.L -(An) */
+void REGPARAM2 CPUFUNC(op_44a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* NEG.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_44a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_44b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}}return;
+}
+
+/* NEG.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_44b8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* NEG.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_44b9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* MV2SR.B Dn */
+void REGPARAM2 CPUFUNC(op_44c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}	m68k_incpci (2);
+return;
+}
+
+/* MV2SR.B (An) */
+void REGPARAM2 CPUFUNC(op_44d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MV2SR.B (An)+ */
+void REGPARAM2 CPUFUNC(op_44d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MV2SR.B -(An) */
+void REGPARAM2 CPUFUNC(op_44e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MV2SR.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_44e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MV2SR.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_44f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}}return;
+}
+
+/* MV2SR.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_44f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MV2SR.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_44f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MV2SR.B (d16,PC) */
+void REGPARAM2 CPUFUNC(op_44fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MV2SR.B (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_44fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}}return;
+}
+
+/* MV2SR.B #.B */
+void REGPARAM2 CPUFUNC(op_44fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.B Dn */
+void REGPARAM2 CPUFUNC(op_4600_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.B (An) */
+void REGPARAM2 CPUFUNC(op_4610_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4618_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.B -(An) */
+void REGPARAM2 CPUFUNC(op_4620_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4628_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4630_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}}return;
+}
+
+/* NOT.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4638_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4639_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* NOT.W Dn */
+void REGPARAM2 CPUFUNC(op_4640_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.W (An) */
+void REGPARAM2 CPUFUNC(op_4650_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4658_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.W -(An) */
+void REGPARAM2 CPUFUNC(op_4660_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4668_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4670_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}}return;
+}
+
+/* NOT.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4678_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4679_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* NOT.L Dn */
+void REGPARAM2 CPUFUNC(op_4680_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.L (An) */
+void REGPARAM2 CPUFUNC(op_4690_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4698_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.L -(An) */
+void REGPARAM2 CPUFUNC(op_46a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NOT.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_46a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_46b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}}return;
+}
+
+/* NOT.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_46b8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NOT.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_46b9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* MV2SR.W Dn */
+void REGPARAM2 CPUFUNC(op_46c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_240760; }
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.sr = src;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+l_240760: ;
+return;
+}
+
+/* MV2SR.W (An) */
+void REGPARAM2 CPUFUNC(op_46d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_240761; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (2);
+l_240761: ;
+return;
+}
+
+/* MV2SR.W (An)+ */
+void REGPARAM2 CPUFUNC(op_46d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_240762; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (2);
+l_240762: ;
+return;
+}
+
+/* MV2SR.W -(An) */
+void REGPARAM2 CPUFUNC(op_46e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_240763; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (2);
+l_240763: ;
+return;
+}
+
+/* MV2SR.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_46e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_240764; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (4);
+l_240764: ;
+return;
+}
+
+/* MV2SR.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_46f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_240765; }
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}}l_240765: ;
+return;
+}
+
+/* MV2SR.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_46f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_240766; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (4);
+l_240766: ;
+return;
+}
+
+/* MV2SR.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_46f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_240767; }
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (6);
+l_240767: ;
+return;
+}
+
+/* MV2SR.W (d16,PC) */
+void REGPARAM2 CPUFUNC(op_46fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_240768; }
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (4);
+l_240768: ;
+return;
+}
+
+/* MV2SR.W (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_46fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_240769; }
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}}l_240769: ;
+return;
+}
+
+/* MV2SR.W #.W */
+void REGPARAM2 CPUFUNC(op_46fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+{if (!regs.s) { Exception (8); goto l_240770; }
+{{	uae_s16 src = get_iword_cache_040 (2);
+	regs.sr = src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_240770: ;
+return;
+}
+
+/* NBCD.B Dn */
+void REGPARAM2 CPUFUNC(op_4800_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* LINK.L An,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4808_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+{{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 offs;
+	offs = get_ilong_cache_040 (2);
+	x_put_long (olda, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* NBCD.B (An) */
+void REGPARAM2 CPUFUNC(op_4810_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NBCD.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4818_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NBCD.B -(An) */
+void REGPARAM2 CPUFUNC(op_4820_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* NBCD.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4828_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NBCD.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4830_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (srca, newv);
+}}}}}return;
+}
+
+/* NBCD.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4838_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* NBCD.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4839_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (srca, newv);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* SWAP.W Dn */
+void REGPARAM2 CPUFUNC(op_4840_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 34;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* BKPTQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4848_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 99;
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return;
+}
+
+#endif
+/* PEA.L (An) */
+void REGPARAM2 CPUFUNC(op_4850_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* PEA.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4868_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* PEA.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4870_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}}return;
+}
+
+/* PEA.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4878_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* PEA.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4879_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* PEA.L (d16,PC) */
+void REGPARAM2 CPUFUNC(op_487a_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* PEA.L (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_487b_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}}return;
+}
+
+/* EXT.W Dn */
+void REGPARAM2 CPUFUNC(op_4880_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u16 dst = (uae_s16)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVMLE.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_4890_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_iword_cache_040 (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMLE.W #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_48a0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_iword_cache_040 (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	int type = get_cpu_model () >= 68020;
+	while (amask) {
+		srca -= 2;
+		if (!type || movem_index2[amask] != dstreg)
+			x_put_word (srca, m68k_areg (regs, movem_index2[amask]));
+		else
+			x_put_word (srca, m68k_areg (regs, movem_index2[amask]) - 2);
+		amask = movem_next[amask];
+	}
+	while (dmask) { srca -= 2; x_put_word (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMLE.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_48a8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_iword_cache_040 (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMLE.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_48b0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_iword_cache_040 (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}}return;
+}
+
+/* MVMLE.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_48b8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_iword_cache_040 (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMLE.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_48b9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_iword_cache_040 (2);
+{	uaecptr srca;
+	srca = get_ilong_cache_040 (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}	m68k_incpci (8);
+return;
+}
+
+/* EXT.L Dn */
+void REGPARAM2 CPUFUNC(op_48c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* MVMLE.L #.W,(An) */
+void REGPARAM2 CPUFUNC(op_48d0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_iword_cache_040 (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMLE.L #.W,-(An) */
+void REGPARAM2 CPUFUNC(op_48e0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_iword_cache_040 (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	int type = get_cpu_model () >= 68020;
+	while (amask) {
+		srca -= 4;
+		if (!type || movem_index2[amask] != dstreg)
+			x_put_long (srca, m68k_areg (regs, movem_index2[amask]));
+		else
+			x_put_long (srca, m68k_areg (regs, movem_index2[amask]) - 4);
+		amask = movem_next[amask];
+	}
+	while (dmask) { srca -= 4; x_put_long (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMLE.L #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_48e8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_iword_cache_040 (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMLE.L #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_48f0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_iword_cache_040 (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}}return;
+}
+
+/* MVMLE.L #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_48f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_iword_cache_040 (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMLE.L #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_48f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+{	uae_u16 mask = get_iword_cache_040 (2);
+{	uaecptr srca;
+	srca = get_ilong_cache_040 (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}	m68k_incpci (8);
+return;
+}
+
+/* EXT.B Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_49c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* TST.B Dn */
+void REGPARAM2 CPUFUNC(op_4a00_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* TST.B (An) */
+void REGPARAM2 CPUFUNC(op_4a10_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4a18_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.B -(An) */
+void REGPARAM2 CPUFUNC(op_4a20_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4a28_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4a30_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return;
+}
+
+/* TST.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4a38_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4a39_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* TST.B (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a3a_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.B (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a3b_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return;
+}
+
+#endif
+/* TST.B #.B */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a3c_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.W Dn */
+void REGPARAM2 CPUFUNC(op_4a40_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* TST.W An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a48_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* TST.W (An) */
+void REGPARAM2 CPUFUNC(op_4a50_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.W (An)+ */
+void REGPARAM2 CPUFUNC(op_4a58_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.W -(An) */
+void REGPARAM2 CPUFUNC(op_4a60_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_4a68_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4a70_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return;
+}
+
+/* TST.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_4a78_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_4a79_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* TST.W (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a7a_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.W (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a7b_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return;
+}
+
+#endif
+/* TST.W #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a7c_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.L Dn */
+void REGPARAM2 CPUFUNC(op_4a80_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (2);
+return;
+}
+
+/* TST.L An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4a88_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (2);
+return;
+}
+
+#endif
+/* TST.L (An) */
+void REGPARAM2 CPUFUNC(op_4a90_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.L (An)+ */
+void REGPARAM2 CPUFUNC(op_4a98_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.L -(An) */
+void REGPARAM2 CPUFUNC(op_4aa0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TST.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4aa8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4ab0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return;
+}
+
+/* TST.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4ab8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TST.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4ab9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* TST.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4aba_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* TST.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4abb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return;
+}
+
+#endif
+/* TST.L #.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4abc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* TAS.B Dn */
+void REGPARAM2 CPUFUNC(op_4ac0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((src) & 0xff);
+}}	m68k_incpci (2);
+return;
+}
+
+/* TAS.B (An) */
+void REGPARAM2 CPUFUNC(op_4ad0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TAS.B (An)+ */
+void REGPARAM2 CPUFUNC(op_4ad8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TAS.B -(An) */
+void REGPARAM2 CPUFUNC(op_4ae0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* TAS.B (d16,An) */
+void REGPARAM2 CPUFUNC(op_4ae8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TAS.B (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4af0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}}return;
+}
+
+/* TAS.B (xxx).W */
+void REGPARAM2 CPUFUNC(op_4af8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* TAS.B (xxx).L */
+void REGPARAM2 CPUFUNC(op_4af9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MULL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c00_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_240847;
+}}}l_240847: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c10_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_240848;
+}}}}l_240848: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c18_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_240849;
+}}}}l_240849: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c20_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_240850;
+}}}}l_240850: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c28_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_240851;
+}}}}l_240851: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c30_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_240852;
+}}}}}l_240852: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c38_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_240853;
+}}}}l_240853: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c39_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_240854;
+}}}}l_240854: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c3a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_240855;
+}}}}l_240855: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c3b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_240856;
+}}}}}l_240856: ;
+return;
+}
+
+#endif
+/* MULL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c3c_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uae_s32 dst;
+	dst = get_ilong_cache_040 (4);
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_240857;
+}}}l_240857: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c40_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_240858;
+}}}l_240858: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c50_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_240859;
+}}}}l_240859: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c58_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_240860;
+}}}}l_240860: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c60_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_240861;
+}}}}l_240861: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c68_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_240862;
+}}}}l_240862: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c70_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_240863;
+}}}}}l_240863: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c78_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_240864;
+}}}}l_240864: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c79_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_240865;
+}}}}l_240865: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c7a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_240866;
+}}}}l_240866: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c7b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_240867;
+}}}}}l_240867: ;
+return;
+}
+
+#endif
+/* DIVL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4c7c_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uae_s32 dst;
+	dst = get_ilong_cache_040 (4);
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_240868;
+}}}l_240868: ;
+return;
+}
+
+#endif
+/* MVMEL.W #.W,(An) */
+void REGPARAM2 CPUFUNC(op_4c90_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMEL.W #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_4c98_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMEL.W #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_4ca8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.W #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4cb0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}}return;
+}
+
+/* MVMEL.W #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_4cb8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.W #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_4cb9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_ilong_cache_040 (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpci (8);
+return;
+}
+
+/* MVMEL.W #.W,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_4cba_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.W #.W,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4cbb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}}return;
+}
+
+/* MVMEL.L #.W,(An) */
+void REGPARAM2 CPUFUNC(op_4cd0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMEL.L #.W,(An)+ */
+void REGPARAM2 CPUFUNC(op_4cd8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpci (4);
+return;
+}
+
+/* MVMEL.L #.W,(d16,An) */
+void REGPARAM2 CPUFUNC(op_4ce8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.L #.W,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4cf0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}}return;
+}
+
+/* MVMEL.L #.W,(xxx).W */
+void REGPARAM2 CPUFUNC(op_4cf8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.L #.W,(xxx).L */
+void REGPARAM2 CPUFUNC(op_4cf9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_ilong_cache_040 (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpci (8);
+return;
+}
+
+/* MVMEL.L #.W,(d16,PC) */
+void REGPARAM2 CPUFUNC(op_4cfa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MVMEL.L #.W,(d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4cfb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+{	uae_u16 mask = get_iword_cache_040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}}return;
+}
+
+/* TRAPQ.L # */
+void REGPARAM2 CPUFUNC(op_4e40_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 15);
+	OpcodeFamily = 39;
+{{	uae_u32 src = srcreg;
+	m68k_incpci (2);
+	Exception (src + 32);
+}}return;
+}
+
+/* LINK.W An,#.W */
+void REGPARAM2 CPUFUNC(op_4e50_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+{{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	x_put_long (olda, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* UNLK.L An */
+void REGPARAM2 CPUFUNC(op_4e58_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 48;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	m68k_areg (regs, 7) = src;
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7);
+{	uae_s32 old = x_get_long (olda);
+	m68k_areg (regs, 7) += 4;
+	m68k_areg (regs, srcreg) = (old);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* MVR2USP.L An */
+void REGPARAM2 CPUFUNC(op_4e60_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 40;
+{if (!regs.s) { Exception (8); goto l_240888; }
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	regs.usp = src;
+}}}	m68k_incpci (2);
+l_240888: ;
+return;
+}
+
+/* MVUSP2R.L An */
+void REGPARAM2 CPUFUNC(op_4e68_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 41;
+{if (!regs.s) { Exception (8); goto l_240889; }
+{{	m68k_areg (regs, srcreg) = (regs.usp);
+}}}	m68k_incpci (2);
+l_240889: ;
+return;
+}
+
+/* RESET.L  */
+void REGPARAM2 CPUFUNC(op_4e70_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 42;
+{if (!regs.s) { Exception (8); goto l_240890; }
+{	cpureset ();
+	m68k_incpci (2);
+}}l_240890: ;
+return;
+}
+
+/* NOP.L  */
+void REGPARAM2 CPUFUNC(op_4e71_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 43;
+{}	m68k_incpci (2);
+return;
+}
+
+/* STOP.L #.W */
+void REGPARAM2 CPUFUNC(op_4e72_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 44;
+{if (!regs.s) { Exception (8); goto l_240892; }
+{{	uae_s16 src = get_iword_cache_040 (2);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_setstopped ();
+	m68k_incpci (4);
+}}}l_240892: ;
+return;
+}
+
+/* RTE.L  */
+void REGPARAM2 CPUFUNC(op_4e73_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 45;
+{if (!regs.s) { Exception (8); goto l_240893; }
+{	uae_u16 newsr; uae_u32 newpc;
+	for (;;) {
+		uaecptr a = m68k_areg (regs, 7);
+		uae_u16 sr = x_get_word (a);
+		uae_u32 pc = x_get_long (a + 2);
+		uae_u16 format = x_get_word (a + 2 + 4);
+		int frame = format >> 12;
+		int offset = 8;
+		newsr = sr; newpc = pc;
+		if (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }
+		else if (frame == 0x1) { m68k_areg (regs, 7) += offset; }
+		else if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }
+		else if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }
+		else if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }
+		else if (frame == 0x7) { m68k_areg (regs, 7) += offset + 52; break; }
+		else if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }
+		else if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }
+		else if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }
+		else { m68k_areg (regs, 7) += offset; Exception (14); goto l_240893; }
+		regs.sr = newsr;
+	MakeFromSR();
+}
+	regs.sr = newsr;
+	MakeFromSR();
+	if (newpc & 1) {
+		exception3i (0x4E73, newpc);
+		goto l_240893;
+	}
+	m68k_setpci (newpc);
+}}l_240893: ;
+return;
+}
+
+/* RTD.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4e74_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 46;
+{{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = x_get_long (pca);
+	m68k_areg (regs, 7) += 4;
+{	uae_s16 offs = get_iword_cache_040 (2);
+	m68k_areg (regs, 7) += offs;
+	if (pc & 1) {
+		exception3i (0x4E74, pc);
+		goto l_240894;
+	}
+	m68k_setpci (pc);
+}}}}l_240894: ;
+return;
+}
+
+#endif
+/* RTS.L  */
+void REGPARAM2 CPUFUNC(op_4e75_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 49;
+{	uaecptr pc = m68k_getpci ();
+	m68k_do_rtsi ();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (pc);
+		exception3i (0x4E75, faultpc);
+		goto l_240895;
+	}
+}l_240895: ;
+return;
+}
+
+/* TRAPV.L  */
+void REGPARAM2 CPUFUNC(op_4e76_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 50;
+{	m68k_incpci (2);
+	if (GET_VFLG ()) {
+		Exception (7);
+		goto l_240896;
+	}
+}l_240896: ;
+return;
+}
+
+/* RTR.L  */
+void REGPARAM2 CPUFUNC(op_4e77_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 51;
+{	uaecptr oldpc = m68k_getpci ();
+	MakeSR ();
+{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+{	uae_s16 sr = x_get_word (sra);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = x_get_long (pca);
+	m68k_areg (regs, 7) += 4;
+	regs.sr &= 0xFF00; sr &= 0xFF;
+	regs.sr |= sr;
+	m68k_setpci (pc);
+	MakeFromSR();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (oldpc);
+		exception3i (0x4E77, faultpc);
+		goto l_240897;
+	}
+}}}}}l_240897: ;
+return;
+}
+
+/* MOVEC2.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4e7a_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 82;
+{if (!regs.s) { Exception (8); goto l_240898; }
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_movec2(src & 0xFFF, regp)) goto l_240898;
+}}}}	m68k_incpci (4);
+l_240898: ;
+return;
+}
+
+#endif
+/* MOVE2C.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_4e7b_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 83;
+{if (!regs.s) { Exception (8); goto l_240899; }
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_move2c(src & 0xFFF, regp)) goto l_240899;
+}}}}	m68k_incpci (4);
+l_240899: ;
+return;
+}
+
+#endif
+/* JSR.L (An) */
+void REGPARAM2 CPUFUNC(op_4e90_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr oldpc = m68k_getpci () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_240900;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}l_240900: ;
+return;
+}
+
+/* JSR.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4ea8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_240901;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}l_240901: ;
+return;
+}
+
+/* JSR.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4eb0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_240902;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}}l_240902: ;
+return;
+}
+
+/* JSR.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4eb8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_240903;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}l_240903: ;
+return;
+}
+
+/* JSR.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4eb9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uaecptr oldpc = m68k_getpci () + 6;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_240904;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}l_240904: ;
+return;
+}
+
+/* JSR.L (d16,PC) */
+void REGPARAM2 CPUFUNC(op_4eba_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_240905;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}l_240905: ;
+return;
+}
+
+/* JSR.L (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4ebb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_240906;
+	}
+	m68k_setpci (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}}l_240906: ;
+return;
+}
+
+/* JMP.L (An) */
+void REGPARAM2 CPUFUNC(op_4ed0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_240907;
+	}
+	m68k_setpci (srca);
+}}l_240907: ;
+return;
+}
+
+/* JMP.L (d16,An) */
+void REGPARAM2 CPUFUNC(op_4ee8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_240908;
+	}
+	m68k_setpci (srca);
+}}l_240908: ;
+return;
+}
+
+/* JMP.L (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_4ef0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_240909;
+	}
+	m68k_setpci (srca);
+}}}l_240909: ;
+return;
+}
+
+/* JMP.L (xxx).W */
+void REGPARAM2 CPUFUNC(op_4ef8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_240910;
+	}
+	m68k_setpci (srca);
+}}l_240910: ;
+return;
+}
+
+/* JMP.L (xxx).L */
+void REGPARAM2 CPUFUNC(op_4ef9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_240911;
+	}
+	m68k_setpci (srca);
+}}l_240911: ;
+return;
+}
+
+/* JMP.L (d16,PC) */
+void REGPARAM2 CPUFUNC(op_4efa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_240912;
+	}
+	m68k_setpci (srca);
+}}l_240912: ;
+return;
+}
+
+/* JMP.L (d8,PC,Xn) */
+void REGPARAM2 CPUFUNC(op_4efb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_240913;
+	}
+	m68k_setpci (srca);
+}}}l_240913: ;
+return;
+}
+
+/* ADDQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_5000_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.B #,(An) */
+void REGPARAM2 CPUFUNC(op_5010_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.B #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5018_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.B #,-(An) */
+void REGPARAM2 CPUFUNC(op_5020_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.B #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5028_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.B #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5030_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADDQ.B #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5038_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.B #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5039_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_5040_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDAQ.W #,An */
+void REGPARAM2 CPUFUNC(op_5048_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.W #,(An) */
+void REGPARAM2 CPUFUNC(op_5050_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.W #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5058_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.W #,-(An) */
+void REGPARAM2 CPUFUNC(op_5060_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.W #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5068_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.W #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5070_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADDQ.W #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5078_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.W #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5079_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_5080_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDAQ.L #,An */
+void REGPARAM2 CPUFUNC(op_5088_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.L #,(An) */
+void REGPARAM2 CPUFUNC(op_5090_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.L #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5098_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDQ.L #,-(An) */
+void REGPARAM2 CPUFUNC(op_50a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+
+#ifdef PART_5
+/* ADDQ.L #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_50a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.L #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_50b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADDQ.L #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_50b8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDQ.L #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_50b9_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* Scc.B Dn (T) */
+void REGPARAM2 CPUFUNC(op_50c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (0) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (T) */
+void REGPARAM2 CPUFUNC(op_50c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (0)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_240941;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_240941: ;
+return;
+}
+
+/* Scc.B (An) (T) */
+void REGPARAM2 CPUFUNC(op_50d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (T) */
+void REGPARAM2 CPUFUNC(op_50d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (T) */
+void REGPARAM2 CPUFUNC(op_50e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (T) */
+void REGPARAM2 CPUFUNC(op_50e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (T) */
+void REGPARAM2 CPUFUNC(op_50f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (T) */
+void REGPARAM2 CPUFUNC(op_50f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (T) */
+void REGPARAM2 CPUFUNC(op_50f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (T) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_50fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (0)) { Exception (7); goto l_240949; }
+}}	m68k_incpci (4);
+l_240949: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (T) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_50fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (0)) { Exception (7); goto l_240950; }
+}}	m68k_incpci (6);
+l_240950: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (T) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_50fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (0)) { Exception (7); goto l_240951; }
+}	m68k_incpci (2);
+l_240951: ;
+return;
+}
+
+#endif
+/* SUBQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_5100_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.B #,(An) */
+void REGPARAM2 CPUFUNC(op_5110_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.B #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5118_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.B #,-(An) */
+void REGPARAM2 CPUFUNC(op_5120_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.B #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5128_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.B #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5130_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUBQ.B #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5138_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.B #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5139_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_5140_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBAQ.W #,An */
+void REGPARAM2 CPUFUNC(op_5148_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.W #,(An) */
+void REGPARAM2 CPUFUNC(op_5150_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.W #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5158_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.W #,-(An) */
+void REGPARAM2 CPUFUNC(op_5160_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.W #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_5168_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.W #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_5170_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUBQ.W #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_5178_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.W #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_5179_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_5180_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBAQ.L #,An */
+void REGPARAM2 CPUFUNC(op_5188_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.L #,(An) */
+void REGPARAM2 CPUFUNC(op_5190_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.L #,(An)+ */
+void REGPARAM2 CPUFUNC(op_5198_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.L #,-(An) */
+void REGPARAM2 CPUFUNC(op_51a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBQ.L #,(d16,An) */
+void REGPARAM2 CPUFUNC(op_51a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.L #,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_51b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUBQ.L #,(xxx).W */
+void REGPARAM2 CPUFUNC(op_51b8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBQ.L #,(xxx).L */
+void REGPARAM2 CPUFUNC(op_51b9_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* Scc.B Dn (F) */
+void REGPARAM2 CPUFUNC(op_51c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (1) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (F) */
+void REGPARAM2 CPUFUNC(op_51c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (1)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_240979;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_240979: ;
+return;
+}
+
+/* Scc.B (An) (F) */
+void REGPARAM2 CPUFUNC(op_51d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (F) */
+void REGPARAM2 CPUFUNC(op_51d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (F) */
+void REGPARAM2 CPUFUNC(op_51e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (F) */
+void REGPARAM2 CPUFUNC(op_51e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (F) */
+void REGPARAM2 CPUFUNC(op_51f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (F) */
+void REGPARAM2 CPUFUNC(op_51f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (F) */
+void REGPARAM2 CPUFUNC(op_51f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (F) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_51fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (1)) { Exception (7); goto l_240987; }
+}}	m68k_incpci (4);
+l_240987: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (F) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_51fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (1)) { Exception (7); goto l_240988; }
+}}	m68k_incpci (6);
+l_240988: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (F) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_51fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (1)) { Exception (7); goto l_240989; }
+}	m68k_incpci (2);
+l_240989: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (HI) */
+void REGPARAM2 CPUFUNC(op_52c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (2) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (HI) */
+void REGPARAM2 CPUFUNC(op_52c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (2)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_240991;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_240991: ;
+return;
+}
+
+/* Scc.B (An) (HI) */
+void REGPARAM2 CPUFUNC(op_52d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (HI) */
+void REGPARAM2 CPUFUNC(op_52d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (HI) */
+void REGPARAM2 CPUFUNC(op_52e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (HI) */
+void REGPARAM2 CPUFUNC(op_52e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (HI) */
+void REGPARAM2 CPUFUNC(op_52f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (HI) */
+void REGPARAM2 CPUFUNC(op_52f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (HI) */
+void REGPARAM2 CPUFUNC(op_52f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (HI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_52fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (2)) { Exception (7); goto l_240999; }
+}}	m68k_incpci (4);
+l_240999: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (HI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_52fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (2)) { Exception (7); goto l_241000; }
+}}	m68k_incpci (6);
+l_241000: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (HI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_52fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (2)) { Exception (7); goto l_241001; }
+}	m68k_incpci (2);
+l_241001: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (LS) */
+void REGPARAM2 CPUFUNC(op_53c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (3) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (LS) */
+void REGPARAM2 CPUFUNC(op_53c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (3)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_241003;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_241003: ;
+return;
+}
+
+/* Scc.B (An) (LS) */
+void REGPARAM2 CPUFUNC(op_53d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (LS) */
+void REGPARAM2 CPUFUNC(op_53d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (LS) */
+void REGPARAM2 CPUFUNC(op_53e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (LS) */
+void REGPARAM2 CPUFUNC(op_53e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (LS) */
+void REGPARAM2 CPUFUNC(op_53f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (LS) */
+void REGPARAM2 CPUFUNC(op_53f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (LS) */
+void REGPARAM2 CPUFUNC(op_53f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (LS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_53fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (3)) { Exception (7); goto l_241011; }
+}}	m68k_incpci (4);
+l_241011: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (LS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_53fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (3)) { Exception (7); goto l_241012; }
+}}	m68k_incpci (6);
+l_241012: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (LS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_53fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (3)) { Exception (7); goto l_241013; }
+}	m68k_incpci (2);
+l_241013: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (CC) */
+void REGPARAM2 CPUFUNC(op_54c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (4) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (CC) */
+void REGPARAM2 CPUFUNC(op_54c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (4)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_241015;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_241015: ;
+return;
+}
+
+/* Scc.B (An) (CC) */
+void REGPARAM2 CPUFUNC(op_54d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (CC) */
+void REGPARAM2 CPUFUNC(op_54d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (CC) */
+void REGPARAM2 CPUFUNC(op_54e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (CC) */
+void REGPARAM2 CPUFUNC(op_54e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (CC) */
+void REGPARAM2 CPUFUNC(op_54f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (CC) */
+void REGPARAM2 CPUFUNC(op_54f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (CC) */
+void REGPARAM2 CPUFUNC(op_54f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (CC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_54fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (4)) { Exception (7); goto l_241023; }
+}}	m68k_incpci (4);
+l_241023: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (CC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_54fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (4)) { Exception (7); goto l_241024; }
+}}	m68k_incpci (6);
+l_241024: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (CC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_54fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (4)) { Exception (7); goto l_241025; }
+}	m68k_incpci (2);
+l_241025: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (CS) */
+void REGPARAM2 CPUFUNC(op_55c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (5) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (CS) */
+void REGPARAM2 CPUFUNC(op_55c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (5)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_241027;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_241027: ;
+return;
+}
+
+/* Scc.B (An) (CS) */
+void REGPARAM2 CPUFUNC(op_55d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (CS) */
+void REGPARAM2 CPUFUNC(op_55d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (CS) */
+void REGPARAM2 CPUFUNC(op_55e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (CS) */
+void REGPARAM2 CPUFUNC(op_55e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (CS) */
+void REGPARAM2 CPUFUNC(op_55f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (CS) */
+void REGPARAM2 CPUFUNC(op_55f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (CS) */
+void REGPARAM2 CPUFUNC(op_55f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (CS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_55fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (5)) { Exception (7); goto l_241035; }
+}}	m68k_incpci (4);
+l_241035: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (CS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_55fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (5)) { Exception (7); goto l_241036; }
+}}	m68k_incpci (6);
+l_241036: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (CS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_55fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (5)) { Exception (7); goto l_241037; }
+}	m68k_incpci (2);
+l_241037: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (NE) */
+void REGPARAM2 CPUFUNC(op_56c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (6) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (NE) */
+void REGPARAM2 CPUFUNC(op_56c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (6)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_241039;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_241039: ;
+return;
+}
+
+/* Scc.B (An) (NE) */
+void REGPARAM2 CPUFUNC(op_56d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (NE) */
+void REGPARAM2 CPUFUNC(op_56d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (NE) */
+void REGPARAM2 CPUFUNC(op_56e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (NE) */
+void REGPARAM2 CPUFUNC(op_56e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (NE) */
+void REGPARAM2 CPUFUNC(op_56f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (NE) */
+void REGPARAM2 CPUFUNC(op_56f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (NE) */
+void REGPARAM2 CPUFUNC(op_56f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (NE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_56fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (6)) { Exception (7); goto l_241047; }
+}}	m68k_incpci (4);
+l_241047: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (NE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_56fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (6)) { Exception (7); goto l_241048; }
+}}	m68k_incpci (6);
+l_241048: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (NE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_56fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (6)) { Exception (7); goto l_241049; }
+}	m68k_incpci (2);
+l_241049: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (EQ) */
+void REGPARAM2 CPUFUNC(op_57c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (7) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (EQ) */
+void REGPARAM2 CPUFUNC(op_57c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (7)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_241051;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_241051: ;
+return;
+}
+
+/* Scc.B (An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (EQ) */
+void REGPARAM2 CPUFUNC(op_57d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (EQ) */
+void REGPARAM2 CPUFUNC(op_57e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (EQ) */
+void REGPARAM2 CPUFUNC(op_57f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (EQ) */
+void REGPARAM2 CPUFUNC(op_57f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (EQ) */
+void REGPARAM2 CPUFUNC(op_57f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (EQ) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_57fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (7)) { Exception (7); goto l_241059; }
+}}	m68k_incpci (4);
+l_241059: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (EQ) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_57fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (7)) { Exception (7); goto l_241060; }
+}}	m68k_incpci (6);
+l_241060: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (EQ) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_57fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (7)) { Exception (7); goto l_241061; }
+}	m68k_incpci (2);
+l_241061: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (VC) */
+void REGPARAM2 CPUFUNC(op_58c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (8) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (VC) */
+void REGPARAM2 CPUFUNC(op_58c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (8)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_241063;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_241063: ;
+return;
+}
+
+/* Scc.B (An) (VC) */
+void REGPARAM2 CPUFUNC(op_58d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (VC) */
+void REGPARAM2 CPUFUNC(op_58d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (VC) */
+void REGPARAM2 CPUFUNC(op_58e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (VC) */
+void REGPARAM2 CPUFUNC(op_58e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (VC) */
+void REGPARAM2 CPUFUNC(op_58f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (VC) */
+void REGPARAM2 CPUFUNC(op_58f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (VC) */
+void REGPARAM2 CPUFUNC(op_58f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (VC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_58fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (8)) { Exception (7); goto l_241071; }
+}}	m68k_incpci (4);
+l_241071: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (VC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_58fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (8)) { Exception (7); goto l_241072; }
+}}	m68k_incpci (6);
+l_241072: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (VC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_58fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (8)) { Exception (7); goto l_241073; }
+}	m68k_incpci (2);
+l_241073: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (VS) */
+void REGPARAM2 CPUFUNC(op_59c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (9) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (VS) */
+void REGPARAM2 CPUFUNC(op_59c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (9)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_241075;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_241075: ;
+return;
+}
+
+/* Scc.B (An) (VS) */
+void REGPARAM2 CPUFUNC(op_59d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (VS) */
+void REGPARAM2 CPUFUNC(op_59d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (VS) */
+void REGPARAM2 CPUFUNC(op_59e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (VS) */
+void REGPARAM2 CPUFUNC(op_59e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (VS) */
+void REGPARAM2 CPUFUNC(op_59f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (VS) */
+void REGPARAM2 CPUFUNC(op_59f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (VS) */
+void REGPARAM2 CPUFUNC(op_59f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (VS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_59fa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (9)) { Exception (7); goto l_241083; }
+}}	m68k_incpci (4);
+l_241083: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (VS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_59fb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (9)) { Exception (7); goto l_241084; }
+}}	m68k_incpci (6);
+l_241084: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (VS) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_59fc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (9)) { Exception (7); goto l_241085; }
+}	m68k_incpci (2);
+l_241085: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (PL) */
+void REGPARAM2 CPUFUNC(op_5ac0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (10) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (PL) */
+void REGPARAM2 CPUFUNC(op_5ac8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (10)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_241087;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_241087: ;
+return;
+}
+
+/* Scc.B (An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ad0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (PL) */
+void REGPARAM2 CPUFUNC(op_5ad8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ae0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (PL) */
+void REGPARAM2 CPUFUNC(op_5ae8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (PL) */
+void REGPARAM2 CPUFUNC(op_5af0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (PL) */
+void REGPARAM2 CPUFUNC(op_5af8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (PL) */
+void REGPARAM2 CPUFUNC(op_5af9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (PL) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5afa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (10)) { Exception (7); goto l_241095; }
+}}	m68k_incpci (4);
+l_241095: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (PL) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5afb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (10)) { Exception (7); goto l_241096; }
+}}	m68k_incpci (6);
+l_241096: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (PL) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5afc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (10)) { Exception (7); goto l_241097; }
+}	m68k_incpci (2);
+l_241097: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (MI) */
+void REGPARAM2 CPUFUNC(op_5bc0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (11) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (MI) */
+void REGPARAM2 CPUFUNC(op_5bc8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (11)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_241099;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_241099: ;
+return;
+}
+
+/* Scc.B (An) (MI) */
+void REGPARAM2 CPUFUNC(op_5bd0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (MI) */
+void REGPARAM2 CPUFUNC(op_5bd8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (MI) */
+void REGPARAM2 CPUFUNC(op_5be0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (MI) */
+void REGPARAM2 CPUFUNC(op_5be8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (MI) */
+void REGPARAM2 CPUFUNC(op_5bf0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (MI) */
+void REGPARAM2 CPUFUNC(op_5bf8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (MI) */
+void REGPARAM2 CPUFUNC(op_5bf9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (MI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5bfa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (11)) { Exception (7); goto l_241107; }
+}}	m68k_incpci (4);
+l_241107: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (MI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5bfb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (11)) { Exception (7); goto l_241108; }
+}}	m68k_incpci (6);
+l_241108: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (MI) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5bfc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (11)) { Exception (7); goto l_241109; }
+}	m68k_incpci (2);
+l_241109: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (GE) */
+void REGPARAM2 CPUFUNC(op_5cc0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (12) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (GE) */
+void REGPARAM2 CPUFUNC(op_5cc8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (12)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_241111;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_241111: ;
+return;
+}
+
+/* Scc.B (An) (GE) */
+void REGPARAM2 CPUFUNC(op_5cd0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (GE) */
+void REGPARAM2 CPUFUNC(op_5cd8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (GE) */
+void REGPARAM2 CPUFUNC(op_5ce0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (GE) */
+void REGPARAM2 CPUFUNC(op_5ce8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (GE) */
+void REGPARAM2 CPUFUNC(op_5cf0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (GE) */
+void REGPARAM2 CPUFUNC(op_5cf8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (GE) */
+void REGPARAM2 CPUFUNC(op_5cf9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (GE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5cfa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (12)) { Exception (7); goto l_241119; }
+}}	m68k_incpci (4);
+l_241119: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (GE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5cfb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (12)) { Exception (7); goto l_241120; }
+}}	m68k_incpci (6);
+l_241120: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (GE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5cfc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (12)) { Exception (7); goto l_241121; }
+}	m68k_incpci (2);
+l_241121: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (LT) */
+void REGPARAM2 CPUFUNC(op_5dc0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (13) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (LT) */
+void REGPARAM2 CPUFUNC(op_5dc8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (13)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_241123;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_241123: ;
+return;
+}
+
+/* Scc.B (An) (LT) */
+void REGPARAM2 CPUFUNC(op_5dd0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (LT) */
+void REGPARAM2 CPUFUNC(op_5dd8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (LT) */
+void REGPARAM2 CPUFUNC(op_5de0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (LT) */
+void REGPARAM2 CPUFUNC(op_5de8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (LT) */
+void REGPARAM2 CPUFUNC(op_5df0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (LT) */
+void REGPARAM2 CPUFUNC(op_5df8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (LT) */
+void REGPARAM2 CPUFUNC(op_5df9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (LT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5dfa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (13)) { Exception (7); goto l_241131; }
+}}	m68k_incpci (4);
+l_241131: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (LT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5dfb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (13)) { Exception (7); goto l_241132; }
+}}	m68k_incpci (6);
+l_241132: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (LT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5dfc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (13)) { Exception (7); goto l_241133; }
+}	m68k_incpci (2);
+l_241133: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (GT) */
+void REGPARAM2 CPUFUNC(op_5ec0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (14) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (GT) */
+void REGPARAM2 CPUFUNC(op_5ec8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (14)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_241135;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_241135: ;
+return;
+}
+
+/* Scc.B (An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ed0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (GT) */
+void REGPARAM2 CPUFUNC(op_5ed8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ee0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (GT) */
+void REGPARAM2 CPUFUNC(op_5ee8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (GT) */
+void REGPARAM2 CPUFUNC(op_5ef0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (GT) */
+void REGPARAM2 CPUFUNC(op_5ef8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (GT) */
+void REGPARAM2 CPUFUNC(op_5ef9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (GT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5efa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (14)) { Exception (7); goto l_241143; }
+}}	m68k_incpci (4);
+l_241143: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (GT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5efb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (14)) { Exception (7); goto l_241144; }
+}}	m68k_incpci (6);
+l_241144: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (GT) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5efc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (14)) { Exception (7); goto l_241145; }
+}	m68k_incpci (2);
+l_241145: ;
+return;
+}
+
+#endif
+/* Scc.B Dn (LE) */
+void REGPARAM2 CPUFUNC(op_5fc0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{{{	int val = cctrue (15) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* DBcc.W Dn,#.W (LE) */
+void REGPARAM2 CPUFUNC(op_5fc8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_cache_040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (15)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_241147;
+			}
+			return;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_241147: ;
+return;
+}
+
+/* Scc.B (An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fd0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (An)+ (LE) */
+void REGPARAM2 CPUFUNC(op_5fd8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B -(An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fe0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* Scc.B (d16,An) (LE) */
+void REGPARAM2 CPUFUNC(op_5fe8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (d8,An,Xn) (LE) */
+void REGPARAM2 CPUFUNC(op_5ff0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return;
+}
+
+/* Scc.B (xxx).W (LE) */
+void REGPARAM2 CPUFUNC(op_5ff8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* Scc.B (xxx).L (LE) */
+void REGPARAM2 CPUFUNC(op_5ff9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* TRAPcc.L #.W (LE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5ffa_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s16 dummy = get_iword_cache_040 (2);
+	if (cctrue (15)) { Exception (7); goto l_241155; }
+}}	m68k_incpci (4);
+l_241155: ;
+return;
+}
+
+#endif
+/* TRAPcc.L #.L (LE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5ffb_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (2);
+	if (cctrue (15)) { Exception (7); goto l_241156; }
+}}	m68k_incpci (6);
+l_241156: ;
+return;
+}
+
+#endif
+/* TRAPcc.L  (LE) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_5ffc_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+{	if (cctrue (15)) { Exception (7); goto l_241157; }
+}	m68k_incpci (2);
+l_241157: ;
+return;
+}
+
+#endif
+/* Bcc.W #.W (T) */
+void REGPARAM2 CPUFUNC(op_6000_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241158;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241158: ;
+return;
+}
+
+/* BccQ.B # (T) */
+void REGPARAM2 CPUFUNC(op_6001_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241159;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241159: ;
+return;
+}
+
+/* Bcc.L #.L (T) */
+void REGPARAM2 CPUFUNC(op_60ff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241160;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241160: ;
+return;
+}
+
+/* BSR.W #.W */
+void REGPARAM2 CPUFUNC(op_6100_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+{	uae_s32 s;
+{	uae_s16 src = get_iword_cache_040 (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_241161;
+	}
+	m68k_do_bsri (m68k_getpci () + 4, s);
+}}l_241161: ;
+return;
+}
+
+/* BSRQ.B # */
+void REGPARAM2 CPUFUNC(op_6101_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 54;
+{	uae_s32 s;
+{	uae_u32 src = srcreg;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_241162;
+	}
+	m68k_do_bsri (m68k_getpci () + 2, s);
+}}l_241162: ;
+return;
+}
+
+/* BSR.L #.L */
+void REGPARAM2 CPUFUNC(op_61ff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+{	uae_s32 s;
+{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_241163;
+	}
+	m68k_do_bsri (m68k_getpci () + 6, s);
+}}l_241163: ;
+return;
+}
+
+/* Bcc.W #.W (HI) */
+void REGPARAM2 CPUFUNC(op_6200_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241164;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241164: ;
+return;
+}
+
+/* BccQ.B # (HI) */
+void REGPARAM2 CPUFUNC(op_6201_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241165;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241165: ;
+return;
+}
+
+/* Bcc.L #.L (HI) */
+void REGPARAM2 CPUFUNC(op_62ff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241166;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241166: ;
+return;
+}
+
+/* Bcc.W #.W (LS) */
+void REGPARAM2 CPUFUNC(op_6300_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241167;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241167: ;
+return;
+}
+
+/* BccQ.B # (LS) */
+void REGPARAM2 CPUFUNC(op_6301_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241168;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241168: ;
+return;
+}
+
+#endif
+
+#ifdef PART_6
+/* Bcc.L #.L (LS) */
+void REGPARAM2 CPUFUNC(op_63ff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241169;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241169: ;
+return;
+}
+
+/* Bcc.W #.W (CC) */
+void REGPARAM2 CPUFUNC(op_6400_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241170;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241170: ;
+return;
+}
+
+/* BccQ.B # (CC) */
+void REGPARAM2 CPUFUNC(op_6401_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241171;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241171: ;
+return;
+}
+
+/* Bcc.L #.L (CC) */
+void REGPARAM2 CPUFUNC(op_64ff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241172;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241172: ;
+return;
+}
+
+/* Bcc.W #.W (CS) */
+void REGPARAM2 CPUFUNC(op_6500_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241173;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241173: ;
+return;
+}
+
+/* BccQ.B # (CS) */
+void REGPARAM2 CPUFUNC(op_6501_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241174;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241174: ;
+return;
+}
+
+/* Bcc.L #.L (CS) */
+void REGPARAM2 CPUFUNC(op_65ff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241175;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241175: ;
+return;
+}
+
+/* Bcc.W #.W (NE) */
+void REGPARAM2 CPUFUNC(op_6600_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241176;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241176: ;
+return;
+}
+
+/* BccQ.B # (NE) */
+void REGPARAM2 CPUFUNC(op_6601_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241177;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241177: ;
+return;
+}
+
+/* Bcc.L #.L (NE) */
+void REGPARAM2 CPUFUNC(op_66ff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241178;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241178: ;
+return;
+}
+
+/* Bcc.W #.W (EQ) */
+void REGPARAM2 CPUFUNC(op_6700_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241179;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241179: ;
+return;
+}
+
+/* BccQ.B # (EQ) */
+void REGPARAM2 CPUFUNC(op_6701_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241180;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241180: ;
+return;
+}
+
+/* Bcc.L #.L (EQ) */
+void REGPARAM2 CPUFUNC(op_67ff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241181;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241181: ;
+return;
+}
+
+/* Bcc.W #.W (VC) */
+void REGPARAM2 CPUFUNC(op_6800_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241182;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241182: ;
+return;
+}
+
+/* BccQ.B # (VC) */
+void REGPARAM2 CPUFUNC(op_6801_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241183;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241183: ;
+return;
+}
+
+/* Bcc.L #.L (VC) */
+void REGPARAM2 CPUFUNC(op_68ff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241184;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241184: ;
+return;
+}
+
+/* Bcc.W #.W (VS) */
+void REGPARAM2 CPUFUNC(op_6900_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241185;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241185: ;
+return;
+}
+
+/* BccQ.B # (VS) */
+void REGPARAM2 CPUFUNC(op_6901_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241186;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241186: ;
+return;
+}
+
+/* Bcc.L #.L (VS) */
+void REGPARAM2 CPUFUNC(op_69ff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241187;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241187: ;
+return;
+}
+
+/* Bcc.W #.W (PL) */
+void REGPARAM2 CPUFUNC(op_6a00_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241188;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241188: ;
+return;
+}
+
+/* BccQ.B # (PL) */
+void REGPARAM2 CPUFUNC(op_6a01_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241189;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241189: ;
+return;
+}
+
+/* Bcc.L #.L (PL) */
+void REGPARAM2 CPUFUNC(op_6aff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241190;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241190: ;
+return;
+}
+
+/* Bcc.W #.W (MI) */
+void REGPARAM2 CPUFUNC(op_6b00_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241191;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241191: ;
+return;
+}
+
+/* BccQ.B # (MI) */
+void REGPARAM2 CPUFUNC(op_6b01_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241192;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241192: ;
+return;
+}
+
+/* Bcc.L #.L (MI) */
+void REGPARAM2 CPUFUNC(op_6bff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241193;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241193: ;
+return;
+}
+
+/* Bcc.W #.W (GE) */
+void REGPARAM2 CPUFUNC(op_6c00_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241194;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241194: ;
+return;
+}
+
+/* BccQ.B # (GE) */
+void REGPARAM2 CPUFUNC(op_6c01_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241195;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241195: ;
+return;
+}
+
+/* Bcc.L #.L (GE) */
+void REGPARAM2 CPUFUNC(op_6cff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241196;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241196: ;
+return;
+}
+
+/* Bcc.W #.W (LT) */
+void REGPARAM2 CPUFUNC(op_6d00_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241197;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241197: ;
+return;
+}
+
+/* BccQ.B # (LT) */
+void REGPARAM2 CPUFUNC(op_6d01_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241198;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241198: ;
+return;
+}
+
+/* Bcc.L #.L (LT) */
+void REGPARAM2 CPUFUNC(op_6dff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241199;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241199: ;
+return;
+}
+
+/* Bcc.W #.W (GT) */
+void REGPARAM2 CPUFUNC(op_6e00_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241200;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241200: ;
+return;
+}
+
+/* BccQ.B # (GT) */
+void REGPARAM2 CPUFUNC(op_6e01_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241201;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241201: ;
+return;
+}
+
+/* Bcc.L #.L (GT) */
+void REGPARAM2 CPUFUNC(op_6eff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241202;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241202: ;
+return;
+}
+
+/* Bcc.W #.W (LE) */
+void REGPARAM2 CPUFUNC(op_6f00_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s16 src = get_iword_cache_040 (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241203;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_241203: ;
+return;
+}
+
+/* BccQ.B # (LE) */
+void REGPARAM2 CPUFUNC(op_6f01_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+{{	uae_u32 src = srcreg;
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241204;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_241204: ;
+return;
+}
+
+/* Bcc.L #.L (LE) */
+void REGPARAM2 CPUFUNC(op_6fff_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_241205;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_241205: ;
+return;
+}
+
+/* MOVEQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_7000_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+{{	uae_u32 src = srcreg;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return;
+}
+
+/* OR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8000_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_8010_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_8018_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_8020_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_8028_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_8030_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* OR.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_8038_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_8039_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_803a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_803b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* OR.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_803c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8040_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_8050_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_8058_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_8060_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_8068_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_8070_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* OR.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_8078_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_8079_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_807a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_807b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* OR.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_807c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8080_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_8090_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_8098_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_80a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_80a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* OR.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_80b8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_80b9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* OR.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_80ba_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80bb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* OR.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_80bc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* DIVU.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_80c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_241240;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}l_241240: ;
+return;
+}
+
+/* DIVU.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_80d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_241241;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}l_241241: ;
+return;
+}
+
+/* DIVU.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_80d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_241242;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}l_241242: ;
+return;
+}
+
+/* DIVU.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_80e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_241243;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}l_241243: ;
+return;
+}
+
+/* DIVU.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_80e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_241244;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}l_241244: ;
+return;
+}
+
+/* DIVU.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_241245;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_241245: ;
+return;
+}
+
+/* DIVU.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_80f8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_241246;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}l_241246: ;
+return;
+}
+
+/* DIVU.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_80f9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_241247;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (6);
+	}
+}}}}l_241247: ;
+return;
+}
+
+/* DIVU.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_80fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_241248;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}l_241248: ;
+return;
+}
+
+/* DIVU.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_80fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_241249;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_241249: ;
+return;
+}
+
+/* DIVU.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_80fc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_241250;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}l_241250: ;
+return;
+}
+
+/* SBCD.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_8100_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SBCD.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_8108_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_8110_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_8118_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_8120_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_8128_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_8130_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* OR.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_8138_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_8139_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* PACK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_8140_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+{	uae_u16 val = m68k_dreg (regs, srcreg) + get_iword_cache_040 (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);
+}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* PACK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_8148_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+{	uae_u16 val;
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (val | ((uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff) << 8)) + get_iword_cache_040 (2);
+	m68k_areg (regs, dstreg) -= areg_byteinc[dstreg];
+	x_put_byte (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));
+}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* OR.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_8150_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_8158_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_8160_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_8168_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_8170_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* OR.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_8178_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_8179_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* UNPK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_8180_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+{	uae_u16 val = m68k_dreg (regs, srcreg);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_iword_cache_040 (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);
+}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* UNPK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_8188_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+{	uae_u16 val;
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_iword_cache_040 (2);
+	m68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];
+	x_put_byte (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);
+	x_put_byte (m68k_areg (regs, dstreg), val >> 8);
+}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* OR.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_8190_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_8198_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_81a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* OR.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_81a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_81b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* OR.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_81b8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* OR.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_81b9_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* DIVS.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_81c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_241278;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}l_241278: ;
+return;
+}
+
+/* DIVS.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_81d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_241279;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}l_241279: ;
+return;
+}
+
+/* DIVS.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_81d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_241280;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}l_241280: ;
+return;
+}
+
+/* DIVS.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_81e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_241281;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}l_241281: ;
+return;
+}
+
+/* DIVS.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_81e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_241282;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}l_241282: ;
+return;
+}
+
+/* DIVS.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_81f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_241283;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_241283: ;
+return;
+}
+
+/* DIVS.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_81f8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_241284;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}l_241284: ;
+return;
+}
+
+/* DIVS.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_81f9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_241285;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (6);
+}}}}l_241285: ;
+return;
+}
+
+/* DIVS.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_81fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_241286;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}l_241286: ;
+return;
+}
+
+/* DIVS.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_81fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_241287;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_241287: ;
+return;
+}
+
+/* DIVS.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_81fc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_241288;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}l_241288: ;
+return;
+}
+
+/* SUB.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9000_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_9010_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_9018_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_9020_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_9028_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_9030_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return;
+}
+
+/* SUB.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_9038_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_9039_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_903a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_903b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return;
+}
+
+/* SUB.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_903c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9040_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W An,Dn */
+void REGPARAM2 CPUFUNC(op_9048_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_9050_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_9058_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_9060_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_9068_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_9070_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return;
+}
+
+/* SUB.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_9078_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_9079_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_907a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_907b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return;
+}
+
+/* SUB.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_907c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9080_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L An,Dn */
+void REGPARAM2 CPUFUNC(op_9088_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_9090_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_9098_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_90a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_90a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_90b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return;
+}
+
+/* SUB.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_90b8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_90b9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUB.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_90ba_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_90bb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return;
+}
+
+/* SUB.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_90bc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_90c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W An,An */
+void REGPARAM2 CPUFUNC(op_90c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W (An),An */
+void REGPARAM2 CPUFUNC(op_90d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_90d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_90e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_90e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_90f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* SUBA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_90f8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_90f9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_90fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_90fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* SUBA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_90fc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBX.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9100_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBX.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_9108_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_9110_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_9118_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_9120_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_9128_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_9130_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_9138_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_9139_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBX.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9140_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBX.W -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_9148_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_9150_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_9158_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_9160_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_9168_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_9170_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_9178_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_9179_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBX.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_9180_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBX.L -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_9188_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_9190_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_9198_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_91a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUB.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_91a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_91b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* SUB.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_91b8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUB.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_91b9_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_91c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L An,An */
+void REGPARAM2 CPUFUNC(op_91c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L (An),An */
+void REGPARAM2 CPUFUNC(op_91d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_91d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_91e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* SUBA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_91e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_91f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* SUBA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_91f8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_91f9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* SUBA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_91fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* SUBA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_91fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* SUBA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_91fc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b000_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_b010_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_b018_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_b020_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_b028_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b030_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_b038_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_b039_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_b03a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b03b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_b03c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b040_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W An,Dn */
+void REGPARAM2 CPUFUNC(op_b048_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_b050_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_b058_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_b060_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_b068_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b070_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_b078_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_b079_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_b07a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b07b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_b07c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b080_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.L An,Dn */
+void REGPARAM2 CPUFUNC(op_b088_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_b090_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_b098_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMP.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_b0a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+
+#ifdef PART_7
+/* CMP.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_b0a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b0b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_b0b8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_b0b9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMP.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_b0ba_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMP.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_b0bb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMP.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_b0bc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMPA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_b0c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W An,An */
+void REGPARAM2 CPUFUNC(op_b0c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W (An),An */
+void REGPARAM2 CPUFUNC(op_b0d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_b0d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_b0e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_b0e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_b0f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMPA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_b0f8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_b0f9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMPA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_b0fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_b0fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMPA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_b0fc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b100_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPM.B (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_b108_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_b110_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_b118_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_b120_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_b128_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_b130_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* EOR.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_b138_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_b139_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b140_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPM.W (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_b148_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_b150_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_b158_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_b160_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_b168_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_b170_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* EOR.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_b178_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_b179_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EOR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_b180_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPM.L (An)+,(An)+ */
+void REGPARAM2 CPUFUNC(op_b188_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_b190_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_b198_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_b1a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* EOR.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_b1a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_b1b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* EOR.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_b1b8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* EOR.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_b1b9_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMPA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_b1c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L An,An */
+void REGPARAM2 CPUFUNC(op_b1c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L (An),An */
+void REGPARAM2 CPUFUNC(op_b1d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_b1d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_b1e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* CMPA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_b1e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_b1f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMPA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_b1f8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_b1f9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* CMPA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_b1fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* CMPA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_b1fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return;
+}
+
+/* CMPA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_b1fc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c000_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_c010_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c018_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c020_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c028_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c030_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* AND.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c038_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c039_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c03a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c03b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return;
+}
+
+/* AND.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_c03c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c040_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_c050_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c058_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c060_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c068_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c070_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* AND.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c078_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c079_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c07a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c07b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return;
+}
+
+/* AND.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_c07c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c080_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_c090_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c098_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c0a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c0a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* AND.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c0b8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c0b9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* AND.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c0ba_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0bb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return;
+}
+
+/* AND.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_c0bc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return;
+}
+
+/* MULU.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c0c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}return;
+}
+
+/* MULU.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_c0d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MULU.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c0d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MULU.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c0e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return;
+}
+
+/* MULU.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c0e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MULU.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* MULU.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c0f8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MULU.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c0f9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (6);
+}}}}}return;
+}
+
+/* MULU.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c0fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return;
+}
+
+/* MULU.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c0fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* MULU.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_c0fc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}return;
+}
+
+/* ABCD.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c100_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ABCD.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_c108_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_c110_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_c118_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_c120_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_c128_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_c130_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return;
+}
+
+/* AND.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_c138_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_c139_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EXG.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c140_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* EXG.L An,An */
+void REGPARAM2 CPUFUNC(op_c148_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	m68k_areg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_c150_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_c158_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_c160_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_c168_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_c170_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return;
+}
+
+/* AND.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_c178_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_c179_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* EXG.L Dn,An */
+void REGPARAM2 CPUFUNC(op_c188_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_c190_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_c198_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_c1a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* AND.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_c1a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_c1b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return;
+}
+
+/* AND.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_c1b8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* AND.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_c1b9_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* MULS.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_c1c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* MULS.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_c1d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* MULS.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_c1d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* MULS.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_c1e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* MULS.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_c1e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* MULS.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c1f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* MULS.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_c1f8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* MULS.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_c1f9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* MULS.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_c1fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* MULS.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_c1fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* MULS.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_c1fc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d000_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B (An),Dn */
+void REGPARAM2 CPUFUNC(op_d010_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_d018_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B -(An),Dn */
+void REGPARAM2 CPUFUNC(op_d020_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_d028_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d030_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return;
+}
+
+/* ADD.B (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_d038_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_d039_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.B (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_d03a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d03b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return;
+}
+
+/* ADD.B #.B,Dn */
+void REGPARAM2 CPUFUNC(op_d03c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uae_s8 src = (uae_u8)get_iword_cache_040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d040_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W An,Dn */
+void REGPARAM2 CPUFUNC(op_d048_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W (An),Dn */
+void REGPARAM2 CPUFUNC(op_d050_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_d058_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W -(An),Dn */
+void REGPARAM2 CPUFUNC(op_d060_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_d068_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d070_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return;
+}
+
+/* ADD.W (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_d078_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_d079_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.W (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_d07a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d07b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return;
+}
+
+/* ADD.W #.W,Dn */
+void REGPARAM2 CPUFUNC(op_d07c_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d080_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L An,Dn */
+void REGPARAM2 CPUFUNC(op_d088_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L (An),Dn */
+void REGPARAM2 CPUFUNC(op_d090_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L (An)+,Dn */
+void REGPARAM2 CPUFUNC(op_d098_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L -(An),Dn */
+void REGPARAM2 CPUFUNC(op_d0a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L (d16,An),Dn */
+void REGPARAM2 CPUFUNC(op_d0a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L (d8,An,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d0b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return;
+}
+
+/* ADD.L (xxx).W,Dn */
+void REGPARAM2 CPUFUNC(op_d0b8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L (xxx).L,Dn */
+void REGPARAM2 CPUFUNC(op_d0b9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADD.L (d16,PC),Dn */
+void REGPARAM2 CPUFUNC(op_d0ba_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L (d8,PC,Xn),Dn */
+void REGPARAM2 CPUFUNC(op_d0bb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return;
+}
+
+/* ADD.L #.L,Dn */
+void REGPARAM2 CPUFUNC(op_d0bc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDA.W Dn,An */
+void REGPARAM2 CPUFUNC(op_d0c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W An,An */
+void REGPARAM2 CPUFUNC(op_d0c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W (An),An */
+void REGPARAM2 CPUFUNC(op_d0d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W (An)+,An */
+void REGPARAM2 CPUFUNC(op_d0d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W -(An),An */
+void REGPARAM2 CPUFUNC(op_d0e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.W (d16,An),An */
+void REGPARAM2 CPUFUNC(op_d0e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.W (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_d0f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* ADDA.W (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_d0f8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.W (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_d0f9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDA.W (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_d0fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.W (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_d0fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* ADDA.W #.W,An */
+void REGPARAM2 CPUFUNC(op_d0fc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uae_s16 src = get_iword_cache_040 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDX.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d100_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDX.B -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_d108_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B Dn,(An) */
+void REGPARAM2 CPUFUNC(op_d110_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_d118_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_d120_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.B Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_d128_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_d130_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.B Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_d138_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.B Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_d139_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDX.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d140_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDX.W -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_d148_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W Dn,(An) */
+void REGPARAM2 CPUFUNC(op_d150_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_d158_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_d160_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.W Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_d168_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_d170_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.W Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_d178_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.W Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_d179_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDX.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_d180_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDX.L -(An),-(An) */
+void REGPARAM2 CPUFUNC(op_d188_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L Dn,(An) */
+void REGPARAM2 CPUFUNC(op_d190_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L Dn,(An)+ */
+void REGPARAM2 CPUFUNC(op_d198_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L Dn,-(An) */
+void REGPARAM2 CPUFUNC(op_d1a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADD.L Dn,(d16,An) */
+void REGPARAM2 CPUFUNC(op_d1a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L Dn,(d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_d1b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}}return;
+}
+
+/* ADD.L Dn,(xxx).W */
+void REGPARAM2 CPUFUNC(op_d1b8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADD.L Dn,(xxx).L */
+void REGPARAM2 CPUFUNC(op_d1b9_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDA.L Dn,An */
+void REGPARAM2 CPUFUNC(op_d1c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L An,An */
+void REGPARAM2 CPUFUNC(op_d1c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L (An),An */
+void REGPARAM2 CPUFUNC(op_d1d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L (An)+,An */
+void REGPARAM2 CPUFUNC(op_d1d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L -(An),An */
+void REGPARAM2 CPUFUNC(op_d1e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return;
+}
+
+/* ADDA.L (d16,An),An */
+void REGPARAM2 CPUFUNC(op_d1e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.L (d8,An,Xn),An */
+void REGPARAM2 CPUFUNC(op_d1f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* ADDA.L (xxx).W,An */
+void REGPARAM2 CPUFUNC(op_d1f8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.L (xxx).L,An */
+void REGPARAM2 CPUFUNC(op_d1f9_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	srca = get_ilong_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return;
+}
+
+/* ADDA.L (d16,PC),An */
+void REGPARAM2 CPUFUNC(op_d1fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return;
+}
+
+/* ADDA.L (d8,PC,Xn),An */
+void REGPARAM2 CPUFUNC(op_d1fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_040 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return;
+}
+
+/* ADDA.L #.L,An */
+void REGPARAM2 CPUFUNC(op_d1fc_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+{{	uae_s32 src;
+	src = get_ilong_cache_040 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ASRQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e000_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e008_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e010_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e018_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e020_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e028_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e030_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROR.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e038_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e040_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+#endif
+
+#ifdef PART_8
+/* LSRQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e048_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e050_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e058_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e060_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e068_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e070_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROR.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e078_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e080_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e088_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e090_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e098_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROR.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e0b8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRW.W (An) */
+void REGPARAM2 CPUFUNC(op_e0d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e0d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e0e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASRW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e0e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ASRW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e0f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ASRW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e0f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ASRW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e0f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+{{	uaecptr dataa;
+	dataa = get_ilong_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ASLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e100_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e108_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e110_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLQ.B #,Dn */
+void REGPARAM2 CPUFUNC(op_e118_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e120_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e128_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e130_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROL.B Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e138_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e140_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e148_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e150_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLQ.W #,Dn */
+void REGPARAM2 CPUFUNC(op_e158_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e160_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e168_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e170_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROL.W Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e178_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e180_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e188_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e190_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLQ.L #,Dn */
+void REGPARAM2 CPUFUNC(op_e198_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1a0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1a8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1b0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROL.L Dn,Dn */
+void REGPARAM2 CPUFUNC(op_e1b8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e1d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e1d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e1e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ASLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e1e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ASLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e1f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ASLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e1f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ASLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e1f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+{{	uaecptr dataa;
+	dataa = get_ilong_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* LSRW.W (An) */
+void REGPARAM2 CPUFUNC(op_e2d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e2d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e2e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSRW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e2e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* LSRW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e2f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* LSRW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e2f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* LSRW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e2f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+{{	uaecptr dataa;
+	dataa = get_ilong_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* LSLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e3d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e3d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e3e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* LSLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e3e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* LSLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e3f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* LSLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e3f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* LSLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e3f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+{{	uaecptr dataa;
+	dataa = get_ilong_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ROXRW.W (An) */
+void REGPARAM2 CPUFUNC(op_e4d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e4d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e4e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXRW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e4e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROXRW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e4f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ROXRW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e4f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROXRW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e4f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+{{	uaecptr dataa;
+	dataa = get_ilong_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ROXLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e5d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e5d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e5e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROXLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e5e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROXLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e5f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ROXLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e5f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROXLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e5f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+{{	uaecptr dataa;
+	dataa = get_ilong_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* RORW.W (An) */
+void REGPARAM2 CPUFUNC(op_e6d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e6d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e6e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* RORW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e6e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* RORW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e6f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* RORW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e6f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* RORW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e6f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+{{	uaecptr dataa;
+	dataa = get_ilong_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* ROLW.W (An) */
+void REGPARAM2 CPUFUNC(op_e7d0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLW.W (An)+ */
+void REGPARAM2 CPUFUNC(op_e7d8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLW.W -(An) */
+void REGPARAM2 CPUFUNC(op_e7e0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (2);
+return;
+}
+
+/* ROLW.W (d16,An) */
+void REGPARAM2 CPUFUNC(op_e7e8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROLW.W (d8,An,Xn) */
+void REGPARAM2 CPUFUNC(op_e7f0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}}return;
+}
+
+/* ROLW.W (xxx).W */
+void REGPARAM2 CPUFUNC(op_e7f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (4);
+return;
+}
+
+/* ROLW.W (xxx).L */
+void REGPARAM2 CPUFUNC(op_e7f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+{{	uaecptr dataa;
+	dataa = get_ilong_cache_040 (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}	m68k_incpci (6);
+return;
+}
+
+/* BFTST.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8c0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8d0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8e8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8f0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}}return;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFTST.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e8fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 88;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_040 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}}return;
+}
+
+#endif
+/* BFEXTU.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9c0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9d0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9e8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9f0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9f8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9f9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9fa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_e9fb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 89;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_040 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return;
+}
+
+#endif
+/* BFCHG.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eac0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFCHG.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ead0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFCHG.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eae8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFCHG.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eaf0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eaf8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eaf9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebc0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebd0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebe8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebf0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebf8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebf9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebfa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ebfb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 91;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_040 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return;
+}
+
+#endif
+/* BFCLR.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecc0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFCLR.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecd0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFCLR.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ece8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFCLR.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecf0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecf8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ecf9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edc0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edd0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_ede8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edf0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}}return;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edf8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edf9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edfa_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_edfb_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 93;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_040 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}}return;
+}
+
+#endif
+/* BFSET.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eec0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFSET.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eed0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFSET.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eee8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFSET.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eef0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eef8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eef9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* BFINS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_efc0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFINS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_efd0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* BFINS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_efe8_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFINS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eff0_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_040 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eff8_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_eff9_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+{{	uae_s16 extra = get_iword_cache_040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_cache_040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return;
+}
+
+#endif
+/* MMUOP030.L Dn,#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f000_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_241788; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	uae_u16 extraa = 0;
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_241788;
+}}l_241788: ;
+return;
+}
+
+#endif
+/* MMUOP030.L An,#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f008_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_241789; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	uae_u16 extraa = 0;
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_241789;
+}}l_241789: ;
+return;
+}
+
+#endif
+/* MMUOP030.L (An),#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f010_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_241790; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_241790;
+}}}l_241790: ;
+return;
+}
+
+#endif
+/* MMUOP030.L (An)+,#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f018_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_241791; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_241791;
+}}}l_241791: ;
+return;
+}
+
+#endif
+/* MMUOP030.L -(An),#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f020_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_241792; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) - 4;
+	m68k_areg (regs, srcreg) = extraa;
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_241792;
+}}}l_241792: ;
+return;
+}
+
+#endif
+/* MMUOP030.L (d16,An),#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f028_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_241793; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_cache_040 (0);
+	m68k_incpci (2);
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_241793;
+}}}l_241793: ;
+return;
+}
+
+#endif
+/* MMUOP030.L (d8,An,Xn),#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f030_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_241794; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+{	extraa = x_get_disp_ea_040 (m68k_areg (regs, srcreg), 0);
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_241794;
+}}}}l_241794: ;
+return;
+}
+
+#endif
+/* MMUOP030.L (xxx).W,#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f038_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_241795; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = (uae_s32)(uae_s16)get_iword_cache_040 (0);
+	m68k_incpci (2);
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_241795;
+}}}l_241795: ;
+return;
+}
+
+#endif
+/* MMUOP030.L (xxx).L,#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f039_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+{if (!regs.s) { Exception (8); goto l_241796; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = get_ilong_cache_040 (0);
+	m68k_incpci (4);
+	if (mmu_op30 (pc, opcode, extra, extraa)) goto l_241796;
+}}}l_241796: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f200_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_241797;
+}
+#endif
+}l_241797: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f208_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_241798;
+}
+#endif
+}l_241798: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f210_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_241799;
+}
+#endif
+}l_241799: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f218_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_241800;
+}
+#endif
+}l_241800: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f220_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_241801;
+}
+#endif
+}l_241801: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f228_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_241802;
+}
+#endif
+}l_241802: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f230_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_241803;
+}
+#endif
+}l_241803: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f238_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_241804;
+}
+#endif
+}l_241804: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f239_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_241805;
+}
+#endif
+}l_241805: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f23a_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_241806;
+}
+#endif
+}l_241806: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f23b_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_241807;
+}
+#endif
+}l_241807: ;
+return;
+}
+
+#endif
+/* FPP.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f23c_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+	if (regs.fp_exception) goto l_241808;
+}
+#endif
+}l_241808: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f240_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_241809;
+}
+#endif
+}l_241809: ;
+return;
+}
+
+#endif
+/* FDBcc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f248_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 105;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_dbcc (opcode, extra);
+	if (regs.fp_exception) goto l_241810;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_241810;
+	}
+}
+#endif
+}l_241810: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f250_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_241811;
+}
+#endif
+}l_241811: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f258_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_241812;
+}
+#endif
+}l_241812: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f260_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_241813;
+}
+#endif
+}l_241813: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f268_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_241814;
+}
+#endif
+}l_241814: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f270_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_241815;
+}
+#endif
+}l_241815: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f278_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_241816;
+}
+#endif
+}l_241816: ;
+return;
+}
+
+#endif
+/* FScc.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f279_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+	if (regs.fp_exception) goto l_241817;
+}
+#endif
+}l_241817: ;
+return;
+}
+
+#endif
+/* FTRAPcc.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f27a_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_iword_cache_040 (2);
+{	uae_s16 dummy = get_iword_cache_040 (4);
+	m68k_incpci (6);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_241818;
+}
+#endif
+}l_241818: ;
+return;
+}
+
+#endif
+/* FTRAPcc.L #.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f27b_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_iword_cache_040 (2);
+{	uae_s32 dummy;
+	dummy = get_ilong_cache_040 (4);
+	m68k_incpci (8);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_241819;
+}
+#endif
+}l_241819: ;
+return;
+}
+
+#endif
+/* FTRAPcc.L  */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f27c_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_iword_cache_040 (2);
+	m68k_incpci (4);
+	fpuop_trapcc (opcode, oldpc, extra);
+	if (regs.fp_exception) goto l_241820;
+
+#endif
+}l_241820: ;
+return;
+}
+
+#endif
+/* FBccQ.L #,#.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f280_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s16 extra = get_iword_cache_040 (0);
+	m68k_incpci (2);
+	fpuop_bcc (opcode, pc,extra);
+	if (regs.fp_exception) goto l_241821;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_241821;
+	}
+}}
+#endif
+}l_241821: ;
+return;
+}
+
+#endif
+/* FBccQ.L #,#.L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f2c0_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s32 extra;
+	extra = get_ilong_cache_040 (0);
+	m68k_incpci (4);
+	fpuop_bcc (opcode, pc,extra);
+	if (regs.fp_exception) goto l_241822;
+	if (regs.fp_branch) {
+		regs.fp_branch = false;
+		fill_prefetch();
+		goto l_241822;
+	}
+}}
+#endif
+}l_241822: ;
+return;
+}
+
+#endif
+/* FSAVE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f310_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_241823; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_241823;
+
+#endif
+}}l_241823: ;
+return;
+}
+
+#endif
+/* FSAVE.L -(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f320_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_241824; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_241824;
+
+#endif
+}}l_241824: ;
+return;
+}
+
+#endif
+/* FSAVE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f328_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_241825; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_241825;
+
+#endif
+}}l_241825: ;
+return;
+}
+
+#endif
+/* FSAVE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f330_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_241826; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_241826;
+
+#endif
+}}l_241826: ;
+return;
+}
+
+#endif
+/* FSAVE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f338_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_241827; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_241827;
+
+#endif
+}}l_241827: ;
+return;
+}
+
+#endif
+/* FSAVE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f339_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+{if (!regs.s) { Exception (8); goto l_241828; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+	if (regs.fp_exception) goto l_241828;
+
+#endif
+}}l_241828: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f350_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_241829; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_241829;
+
+#endif
+}}l_241829: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f358_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_241830; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_241830;
+
+#endif
+}}l_241830: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f368_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_241831; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_241831;
+
+#endif
+}}l_241831: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f370_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_241832; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_241832;
+
+#endif
+}}l_241832: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f378_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_241833; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_241833;
+
+#endif
+}}l_241833: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f379_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_241834; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_241834;
+
+#endif
+}}l_241834: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f37a_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_241835; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_241835;
+
+#endif
+}}l_241835: ;
+return;
+}
+
+#endif
+/* FRESTORE.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f37b_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+{if (!regs.s) { Exception (8); goto l_241836; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+	if (regs.fp_exception) goto l_241836;
+
+#endif
+}}l_241836: ;
+return;
+}
+
+#endif
+/* CINVLQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f408_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 111;
+{if (!regs.s) { Exception (8); goto l_241837; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241837: ;
+return;
+}
+
+#endif
+/* CINVPQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f410_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 112;
+{if (!regs.s) { Exception (8); goto l_241838; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241838: ;
+return;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f418_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+{if (!regs.s) { Exception (8); goto l_241839; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241839: ;
+return;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f419_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+{if (!regs.s) { Exception (8); goto l_241840; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241840: ;
+return;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f41a_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+{if (!regs.s) { Exception (8); goto l_241841; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241841: ;
+return;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f41b_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+{if (!regs.s) { Exception (8); goto l_241842; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241842: ;
+return;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f41c_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+{if (!regs.s) { Exception (8); goto l_241843; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241843: ;
+return;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f41d_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+{if (!regs.s) { Exception (8); goto l_241844; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241844: ;
+return;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f41e_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+{if (!regs.s) { Exception (8); goto l_241845; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241845: ;
+return;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f41f_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+{if (!regs.s) { Exception (8); goto l_241846; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241846: ;
+return;
+}
+
+#endif
+/* CPUSHLQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f428_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 114;
+{if (!regs.s) { Exception (8); goto l_241847; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241847: ;
+return;
+}
+
+#endif
+/* CPUSHPQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f430_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 115;
+{if (!regs.s) { Exception (8); goto l_241848; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241848: ;
+return;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f438_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+{if (!regs.s) { Exception (8); goto l_241849; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241849: ;
+return;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f439_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+{if (!regs.s) { Exception (8); goto l_241850; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241850: ;
+return;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f43a_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+{if (!regs.s) { Exception (8); goto l_241851; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241851: ;
+return;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f43b_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+{if (!regs.s) { Exception (8); goto l_241852; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241852: ;
+return;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f43c_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+{if (!regs.s) { Exception (8); goto l_241853; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241853: ;
+return;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f43d_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+{if (!regs.s) { Exception (8); goto l_241854; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241854: ;
+return;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f43e_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+{if (!regs.s) { Exception (8); goto l_241855; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241855: ;
+return;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f43f_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+{if (!regs.s) { Exception (8); goto l_241856; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_241856: ;
+return;
+}
+
+#endif
+/* PFLUSHN.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f500_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 119;
+{if (!regs.s) { Exception (8); goto l_241857; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_241857: ;
+return;
+}
+
+#endif
+/* PFLUSH.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f508_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 120;
+{if (!regs.s) { Exception (8); goto l_241858; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_241858: ;
+return;
+}
+
+#endif
+/* PFLUSHAN.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f510_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 121;
+{if (!regs.s) { Exception (8); goto l_241859; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_241859: ;
+return;
+}
+
+#endif
+/* PFLUSHA.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f518_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 122;
+{if (!regs.s) { Exception (8); goto l_241860; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_241860: ;
+return;
+}
+
+#endif
+/* PTESTW.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f548_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 126;
+{if (!regs.s) { Exception (8); goto l_241861; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_241861: ;
+return;
+}
+
+#endif
+/* PTESTR.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f568_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 125;
+{if (!regs.s) { Exception (8); goto l_241862; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_241862: ;
+return;
+}
+
+#endif
+/* PLPAW.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f588_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 124;
+{if (!regs.s) { Exception (8); goto l_241863; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_241863: ;
+return;
+}
+
+#endif
+/* PLPAR.L (An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f5c8_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 123;
+{if (!regs.s) { Exception (8); goto l_241864; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_241864: ;
+return;
+}
+
+#endif
+/* MOVE16.L (An)+,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f600_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 117;
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = m68k_areg (regs, srcreg);
+{	uaecptr memda;
+	memda = get_ilong_cache_040 (2);
+	memsa &= ~15;
+	memda &= ~15;
+	v[0] = x_get_long (memsa);
+	v[1] = x_get_long (memsa + 4);
+	v[2] = x_get_long (memsa + 8);
+	v[3] = x_get_long (memsa + 12);
+	x_put_long (memda , v[0]);
+	x_put_long (memda + 4, v[1]);
+	x_put_long (memda + 8, v[2]);
+	x_put_long (memda + 12, v[3]);
+	m68k_areg (regs, srcreg) += 16;
+}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* MOVE16.L (xxx).L,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f608_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 117;
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = get_ilong_cache_040 (2);
+{	uaecptr memda;
+	memda = m68k_areg (regs, dstreg);
+	memsa &= ~15;
+	memda &= ~15;
+	v[0] = x_get_long (memsa);
+	v[1] = x_get_long (memsa + 4);
+	v[2] = x_get_long (memsa + 8);
+	v[3] = x_get_long (memsa + 12);
+	x_put_long (memda , v[0]);
+	x_put_long (memda + 4, v[1]);
+	x_put_long (memda + 8, v[2]);
+	x_put_long (memda + 12, v[3]);
+	m68k_areg (regs, dstreg) += 16;
+}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* MOVE16.L (An),(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f610_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 117;
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = m68k_areg (regs, srcreg);
+{	uaecptr memda;
+	memda = get_ilong_cache_040 (2);
+	memsa &= ~15;
+	memda &= ~15;
+	v[0] = x_get_long (memsa);
+	v[1] = x_get_long (memsa + 4);
+	v[2] = x_get_long (memsa + 8);
+	v[3] = x_get_long (memsa + 12);
+	x_put_long (memda , v[0]);
+	x_put_long (memda + 4, v[1]);
+	x_put_long (memda + 8, v[2]);
+	x_put_long (memda + 12, v[3]);
+}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* MOVE16.L (xxx).L,(An) */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f618_24)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 117;
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = get_ilong_cache_040 (2);
+{	uaecptr memda;
+	memda = m68k_areg (regs, dstreg);
+	memsa &= ~15;
+	memda &= ~15;
+	v[0] = x_get_long (memsa);
+	v[1] = x_get_long (memsa + 4);
+	v[2] = x_get_long (memsa + 8);
+	v[3] = x_get_long (memsa + 12);
+	x_put_long (memda , v[0]);
+	x_put_long (memda + 4, v[1]);
+	x_put_long (memda + 8, v[2]);
+	x_put_long (memda + 12, v[3]);
+}}}	m68k_incpci (6);
+return;
+}
+
+#endif
+/* MOVE16.L (An)+,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f620_24)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = 0;
+	OpcodeFamily = 117;
+{	uae_u32 v[4];
+	uaecptr mems = m68k_areg (regs, srcreg) & ~15, memd;
+	dstreg = (get_iword_cache_040 (2) >> 12) & 7;
+	memd = m68k_areg (regs, dstreg) & ~15;
+	v[0] = x_get_long (mems);
+	v[1] = x_get_long (mems + 4);
+	v[2] = x_get_long (mems + 8);
+	v[3] = x_get_long (mems + 12);
+	x_put_long (memd , v[0]);
+	x_put_long (memd + 4, v[1]);
+	x_put_long (memd + 8, v[2]);
+	x_put_long (memd + 12, v[3]);
+	if (srcreg != dstreg)
+		m68k_areg (regs, srcreg) += 16;
+	m68k_areg (regs, dstreg) += 16;
+}	m68k_incpci (4);
+return;
+}
+
+#endif
+/* LPSTOP.L #.W */
+#ifndef CPUEMU_68000_ONLY
+void REGPARAM2 CPUFUNC(op_f800_24)(uae_u32 opcode)
+{
+	OpcodeFamily = 127;
+{if (!regs.s) { Exception (8); goto l_241870; }
+{	uae_u16 sw = x_get_iword (2);
+	uae_u16 sr;
+	if (sw != (0x100|0x80|0x40)) { Exception (4); goto l_241870; }
+	sr = x_get_iword (4);
+	if (!(sr & 0x8000)) { Exception (8); goto l_241870; }
+	regs.sr = sr;
+	MakeFromSR();
+	m68k_setstopped();
+	m68k_incpci (6);
+}}l_241870: ;
+return;
+}
+
+#endif
+#endif
+
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+#endif
+
+#ifdef PART_2
+#endif
+
+#ifdef PART_3
+#endif
+
+#ifdef PART_4
+#endif
+
+#ifdef PART_5
+#endif
+
+#ifdef PART_6
+#endif
+
+#ifdef PART_7
+#endif
+
+#ifdef PART_8
+#endif
+
diff --git a/src/cpu/cpuemu_31.c b/src/cpu/cpuemu_31.c
new file mode 100644
index 0000000..45bf3ed
--- /dev/null
+++ b/src/cpu/cpuemu_31.c
@@ -0,0 +1,41501 @@
+#include "main.h"
+#include "sysdeps.h"
+#include "hatari-glue.h"
+#include "maccess.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "cputbl.h"
+#include "cpummu.h"
+#define CPUFUNC(x) x##_ff
+#define SET_CFLG_ALWAYS(x) SET_CFLG(x)
+#define SET_NFLG_ALWAYS(x) SET_NFLG(x)
+#ifdef NOFLAGS
+#include "noflags.h"
+#endif
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0000_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0010_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0018_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0020_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0028_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0030_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0038_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0039_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* ORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_003c_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu040 (2);
+	src &= 0xFF;
+	regs.sr |= src;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0040_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0050_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0058_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0060_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0068_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0070_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0078_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0079_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_007c_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_310018; }
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu040 (2);
+	regs.sr |= src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_310018: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0080_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0090_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0098_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 30 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_00b0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_00b8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_00b9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (10);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 36 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00d0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu040 (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu040 (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310027; }
+}
+}}}	m68k_incpci (4);
+l_310027: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00e8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu040 (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu040 (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310028; }
+}
+}}}	m68k_incpci (6);
+l_310028: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu040 (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu040 (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310029; }
+}
+}}}}l_310029: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu040 (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu040 (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310030; }
+}
+}}}	m68k_incpci (6);
+l_310030: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu040 (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu040 (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310031; }
+}
+}}}	m68k_incpci (8);
+l_310031: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu040 (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu040 (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310032; }
+}
+}}}	m68k_incpci (6);
+l_310032: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu040 (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu040 (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310033; }
+}
+}}}}l_310033: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BTST.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0100_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPMR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0108_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 8;  
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_u16 val;
+	MovepByteNbr=1; val = ((get_byte_mmu040 (memp) & 0xff) << 8);
+	MovepByteNbr=2; val += (get_byte_mmu040 (memp + 2) & 0xff);
+	MovepByteNbr=0;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0110_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0118_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0120_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0128_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0130_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0138_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0139_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_013a_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 2;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_013b_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,#.B */
+uae_u32 REGPARAM2 CPUFUNC(op_013c_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = get_ibyte_mmu040 (2);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0140_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPMR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0148_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 16; 
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_u32 val;
+	MovepByteNbr=1; val = ((get_byte_mmu040 (memp) & 0xff) << 24);
+	MovepByteNbr=2; val += ((get_byte_mmu040 (memp + 2) & 0xff) << 16);
+	MovepByteNbr=3; val += ((get_byte_mmu040 (memp + 4) & 0xff) << 8);
+	MovepByteNbr=4; val += (get_byte_mmu040 (memp + 6) & 0xff);
+	MovepByteNbr=0;
+	m68k_dreg (regs, dstreg) = (val);
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0150_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0158_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0160_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0168_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0170_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0178_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0179_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0180_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPRM.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0188_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	MovepByteNbr=1; 	put_byte_mmu040 (memp, src >> 8);
+	MovepByteNbr=2; 	put_byte_mmu040 (memp + 2, src);
+	MovepByteNbr=0;
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0190_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0198_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01b8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01b9_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BSET.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_01c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPRM.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	MovepByteNbr=1; 	put_byte_mmu040 (memp, src >> 24);
+	MovepByteNbr=2; 	put_byte_mmu040 (memp + 2, src >> 16);
+	MovepByteNbr=3; 	put_byte_mmu040 (memp + 4, src >> 8);
+	MovepByteNbr=4; 	put_byte_mmu040 (memp + 6, src);
+	MovepByteNbr=0;
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_01d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01f8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01f9_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0200_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0210_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0218_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0220_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0228_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0230_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0238_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0239_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* ANDSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_023c_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu040 (2);
+	src |= 0xFF00;
+	regs.sr &= src;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0240_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0250_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0258_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0260_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0268_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0270_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0278_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0279_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ANDSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_027c_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_310090; }
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu040 (2);
+	regs.sr &= src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_310090: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0280_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0290_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0298_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 30 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_02b0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_02b8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_02b9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (10);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 36 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02d0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu040 (dsta); upper = (uae_s32)(uae_s16)get_word_mmu040 (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310099; }
+}
+}}}	m68k_incpci (4);
+l_310099: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02e8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu040 (dsta); upper = (uae_s32)(uae_s16)get_word_mmu040 (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310100; }
+}
+}}}	m68k_incpci (6);
+l_310100: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu040 (dsta); upper = (uae_s32)(uae_s16)get_word_mmu040 (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310101; }
+}
+}}}}l_310101: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu040 (dsta); upper = (uae_s32)(uae_s16)get_word_mmu040 (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310102; }
+}
+}}}	m68k_incpci (6);
+l_310102: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu040 (dsta); upper = (uae_s32)(uae_s16)get_word_mmu040 (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310103; }
+}
+}}}	m68k_incpci (8);
+l_310103: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu040 (dsta); upper = (uae_s32)(uae_s16)get_word_mmu040 (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310104; }
+}
+}}}	m68k_incpci (6);
+l_310104: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu040 (dsta); upper = (uae_s32)(uae_s16)get_word_mmu040 (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310105; }
+}
+}}}}l_310105: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0400_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0410_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0418_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0420_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0428_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0430_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0438_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0439_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0440_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0450_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0458_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0460_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0468_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0470_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0478_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0479_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0480_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0490_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0498_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 30 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_04b0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_04b8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_04b9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (10);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 36 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04d0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu040 (dsta); upper = get_long_mmu040 (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310130; }
+}
+}}}	m68k_incpci (4);
+l_310130: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04e8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu040 (dsta); upper = get_long_mmu040 (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310131; }
+}
+}}}	m68k_incpci (6);
+l_310131: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu040 (dsta); upper = get_long_mmu040 (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310132; }
+}
+}}}}l_310132: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu040 (dsta); upper = get_long_mmu040 (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310133; }
+}
+}}}	m68k_incpci (6);
+l_310133: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu040 (dsta); upper = get_long_mmu040 (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310134; }
+}
+}}}	m68k_incpci (8);
+l_310134: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu040 (dsta); upper = get_long_mmu040 (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310135; }
+}
+}}}	m68k_incpci (6);
+l_310135: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu040 (dsta); upper = get_long_mmu040 (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_310136; }
+}
+}}}}l_310136: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0600_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0610_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0618_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0620_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0628_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0630_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0638_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0639_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0640_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0650_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0658_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0660_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0668_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0670_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0678_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0679_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0680_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0690_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0698_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 30 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_06b0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_06b8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_06b9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (10);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 36 * CYCLE_UNIT / 2;
+}
+
+/* RTM.L Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* RTM.L An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BTST.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0800_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0810_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0818_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0820_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0828_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0830_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0838_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0839_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (8);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_083a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_083b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0840_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0850_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0858_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0860_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0868_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0870_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0878_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0879_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0880_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0890_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0898_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08b0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08b8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08b9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* BSET.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_08c0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08d0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_08d8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08f0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, dst);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a00_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a10_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a18_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a20_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a28_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a30_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a38_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a39_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* EORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a3c_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu040 (2);
+	src &= 0xFF;
+	regs.sr ^= src;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a40_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a50_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a58_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a60_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a68_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a70_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a78_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a79_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* EORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a7c_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_310221; }
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu040 (2);
+	regs.sr ^= src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_310221: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a80_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a90_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a98_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 30 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (10);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 36 * CYCLE_UNIT / 2;
+}
+
+/* CAS.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ad0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_lrmw_byte_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_byte_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ad8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_lrmw_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_byte_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ae0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_lrmw_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_byte_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ae8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_lrmw_byte_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_byte_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
+#ifdef PART_2
+/* CAS.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_lrmw_byte_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_byte_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_lrmw_byte_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_byte_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 28; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s8 dst = get_lrmw_byte_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_byte_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c00_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c10_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c18_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c20_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c28_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c30_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c38_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c39_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c3a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.B #.B,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c3b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c40_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c50_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c58_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c60_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c68_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c70_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c78_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c79_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c7a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c7b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c80_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c90_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c98_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (10);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cba_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 6;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu040 (6);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.L #.L,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cbb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (6);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cd0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_lrmw_word_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_word_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cd8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_lrmw_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_word_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ce0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_lrmw_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_word_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ce8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_lrmw_word_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_word_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_lrmw_word_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_word_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 dst = get_lrmw_word_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_word_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 28; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s16 dst = get_lrmw_word_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_word_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS2.W #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cfc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 extra;
+	extra = get_ilong_mmu040 (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u16 dst1 = get_lrmw_word_mmu040 (rn1), dst2 = get_lrmw_word_mmu040 (rn2);
+{uae_u32 newv = ((uae_u16)(dst1)) - ((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s16)(dst1)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u16)(dst2)) - ((uae_u16)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s16)(dst2)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, extra & 7))) > ((uae_u16)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	put_lrmw_word_mmu040 (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	put_lrmw_word_mmu040 (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);
+	m68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);
+	}
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e10_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_310275; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = sfc040_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+	m68k_incpci (4);
+}}}}}}l_310275: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e18_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_310276; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	dfc040_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = sfc040_get_byte (srca);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+	m68k_incpci (4);
+}}}}}}l_310276: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e20_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_310277; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	dfc040_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 src = sfc040_get_byte (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+	m68k_incpci (4);
+}}}}}}l_310277: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e28_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_310278; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 src = sfc040_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+	m68k_incpci (6);
+}}}}}}l_310278: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e30_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_310279; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_byte (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s8 src = sfc040_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}}l_310279: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e38_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_310280; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s8 src = sfc040_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+	m68k_incpci (6);
+}}}}}}l_310280: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e39_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_310281; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_ilong_mmu040 (4);
+{	uae_s8 src = sfc040_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+	m68k_incpci (8);
+}}}}}}l_310281: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e50_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_310282; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = sfc040_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+	m68k_incpci (4);
+}}}}}}l_310282: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e58_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_310283; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	dfc040_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = sfc040_get_word (srca);
+	m68k_areg (regs, dstreg) += 2;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+	m68k_incpci (4);
+}}}}}}l_310283: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e60_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_310284; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	dfc040_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 src = sfc040_get_word (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+	m68k_incpci (4);
+}}}}}}l_310284: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e68_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_310285; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 src = sfc040_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+	m68k_incpci (6);
+}}}}}}l_310285: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e70_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_310286; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_word (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s16 src = sfc040_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}}l_310286: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e78_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_310287; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s16 src = sfc040_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+	m68k_incpci (6);
+}}}}}}l_310287: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e79_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_310288; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_ilong_mmu040 (4);
+{	uae_s16 src = sfc040_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+	m68k_incpci (8);
+}}}}}}l_310288: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e90_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_310289; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = sfc040_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+	m68k_incpci (4);
+}}}}}}l_310289: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e98_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_310290; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	dfc040_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = sfc040_get_long (srca);
+	m68k_areg (regs, dstreg) += 4;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+	m68k_incpci (4);
+}}}}}}l_310290: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ea0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 28; 
+{if (!regs.s) { Exception (8); goto l_310291; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	dfc040_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 src = sfc040_get_long (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+	m68k_incpci (4);
+}}}}}}l_310291: ;
+return 28 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ea8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_310292; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s32 src = sfc040_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+	m68k_incpci (6);
+}}}}}}l_310292: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_310293; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_long (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s32 src = sfc040_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}}l_310293: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_310294; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s32 src = sfc040_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+	m68k_incpci (6);
+}}}}}}l_310294: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 40; 
+{if (!regs.s) { Exception (8); goto l_310295; }
+{{	uae_s16 extra = get_iword_mmu040 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	dfc040_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_ilong_mmu040 (4);
+{	uae_s32 src = sfc040_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+	m68k_incpci (8);
+}}}}}}l_310295: ;
+return 40 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ed0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 32; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_lrmw_long_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_long_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ed8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 32; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_lrmw_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_long_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ee0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 34; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_lrmw_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_long_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}return 34 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ee8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 36; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s32 dst = get_lrmw_long_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_long_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}return 36 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 36; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_lrmw_long_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_long_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}}return 36 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 36; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s32 dst = get_lrmw_long_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_long_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}return 36 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 40; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s32 dst = get_lrmw_long_mmu040 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu040 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_long_mmu040 (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}return 40 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS2.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0efc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 extra;
+	extra = get_ilong_mmu040 (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u32 dst1 = get_lrmw_long_mmu040 (rn1), dst2 = get_lrmw_long_mmu040 (rn2);
+{uae_u32 newv = ((uae_u32)(dst1)) - ((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s32)(dst1)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u32)(dst2)) - ((uae_u32)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s32)(dst2)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, extra & 7))) > ((uae_u32)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	put_lrmw_long_mmu040 (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	put_lrmw_long_mmu040 (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = dst2;
+	m68k_dreg (regs, (extra >> 22) & 7) = dst1;
+	}
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1000_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1010_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1018_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1020_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1028_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1030_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1038_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1039_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1080_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1090_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1098_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10ba_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1100_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1110_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1118_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1120_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1128_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1130_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1138_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1139_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1140_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1150_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1158_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1160_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1168_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1170_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1178_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1179_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1180_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1190_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1198_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11ba_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (10);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2000_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2008_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2010_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2018_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2020_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2028_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2030_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2038_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2039_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2040_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2048_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2050_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2058_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	mmufixup[0].reg = -1;
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2060_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	mmufixup[0].reg = -1;
+	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2068_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2070_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	m68k_areg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2078_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2079_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	m68k_areg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_207c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2080_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2088_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2090_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2098_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20ba_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2100_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2108_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2110_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2118_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2120_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2128_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2130_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2138_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2139_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2140_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2148_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2150_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2158_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2160_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 26 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2168_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2170_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2178_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2179_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2180_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2188_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2190_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2198_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_3
+/* MOVE.L -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 26 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21ba_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 26 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 30 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 36; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (10);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 36 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (10);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3000_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3008_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3010_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3018_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3020_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3028_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3030_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3038_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3039_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3040_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3048_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3050_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3058_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	mmufixup[0].reg = -1;
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3060_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	mmufixup[0].reg = -1;
+	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3068_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3070_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3078_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3079_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_307c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3080_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3088_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3090_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3098_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30ba_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3100_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3108_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3110_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3118_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3120_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3128_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3130_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3138_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3139_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3140_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3148_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3150_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3158_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3160_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3168_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3170_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3178_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3179_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3180_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3188_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3190_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3198_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31ba_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (10);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (8);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4000_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4010_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, newv);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4018_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, newv);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4020_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, newv);
+}}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4028_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, newv);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4030_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4038_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, newv);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4039_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, newv);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4040_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4050_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, newv);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4058_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (srca, newv);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4060_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (srca, newv);
+}}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4068_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, newv);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4070_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4078_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, newv);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4079_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, newv);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4080_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4090_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, newv);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4098_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (srca, newv);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (srca, newv);
+}}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, newv);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, newv);
+}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40b8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, newv);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40b9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, newv);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_40c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_310632; }
+{{	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}}	m68k_incpci (2);
+l_310632: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_310633; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, regs.sr);
+}}}l_310633: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_40d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_310634; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (srca, regs.sr);
+}}}l_310634: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_310635; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (srca, regs.sr);
+}}}l_310635: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_310636; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	MakeSR ();
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, regs.sr);
+}}}l_310636: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_310637; }
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, regs.sr);
+}}}}l_310637: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_310638; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	MakeSR ();
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, regs.sr);
+}}}l_310638: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_310639; }
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+	MakeSR ();
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, regs.sr);
+}}}l_310639: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4100_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310640;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310640;
+	}
+}}}l_310640: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4110_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310641;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310641;
+	}
+}}}}l_310641: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (An)+,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4118_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310642;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310642;
+	}
+}}}}l_310642: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L -(An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4120_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310643;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310643;
+	}
+}}}}l_310643: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d16,An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4128_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310644;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310644;
+	}
+}}}}l_310644: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d8,An,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4130_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310645;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310645;
+	}
+}}}}}l_310645: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (xxx).W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4138_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310646;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310646;
+	}
+}}}}l_310646: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (xxx).L,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4139_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310647;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310647;
+	}
+}}}}l_310647: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d16,PC),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310648;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310648;
+	}
+}}}}l_310648: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d8,PC,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310649;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310649;
+	}
+}}}}}l_310649: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L #.L,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310650;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310650;
+	}
+}}}l_310650: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4180_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310651;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310651;
+	}
+}}}l_310651: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4190_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310652;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310652;
+	}
+}}}}l_310652: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4198_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310653;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310653;
+	}
+}}}}l_310653: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310654;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310654;
+	}
+}}}}l_310654: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310655;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310655;
+	}
+}}}}l_310655: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310656;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310656;
+	}
+}}}}}l_310656: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310657;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310657;
+	}
+}}}}l_310657: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310658;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310658;
+	}
+}}}}l_310658: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41ba_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310659;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310659;
+	}
+}}}}l_310659: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310660;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310660;
+	}
+}}}}}l_310660: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_310661;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_310661;
+	}
+}}}l_310661: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4200_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4210_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, 0);
+}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4218_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, 0);
+}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4220_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, 0);
+}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4228_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, 0);
+}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4230_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, 0);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4238_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, 0);
+}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4239_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, 0);
+}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4240_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4250_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, 0);
+}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4258_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (srca, 0);
+}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4260_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (srca, 0);
+}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4268_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, 0);
+}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4270_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, 0);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4278_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, 0);
+}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4279_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, 0);
+}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4280_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4290_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, 0);
+}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4298_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (srca, 0);
+}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (srca, 0);
+}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, 0);
+}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_42b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, 0);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_42b8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, 0);
+}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_42b9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, 0);
+}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, regs.sr & 0xff);
+}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (srca, regs.sr & 0xff);
+}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (srca, regs.sr & 0xff);
+}}return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	MakeSR ();
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, regs.sr & 0xff);
+}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, regs.sr & 0xff);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	MakeSR ();
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, regs.sr & 0xff);
+}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+	MakeSR ();
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, regs.sr & 0xff);
+}}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* NEG.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4400_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_4
+/* NEG.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4410_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, dst);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4418_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, dst);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4420_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, dst);
+}}}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4428_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, dst);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4430_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, dst);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4438_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, dst);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4439_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, dst);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4440_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4450_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, dst);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4458_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (srca, dst);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4460_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (srca, dst);
+}}}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4468_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, dst);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4470_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, dst);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4478_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, dst);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4479_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, dst);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4480_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4490_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, dst);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4498_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (srca, dst);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (srca, dst);
+}}}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, dst);
+}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, dst);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44b8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, dst);
+}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44b9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, dst);
+}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_44c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_44d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B #.B */
+uae_u32 REGPARAM2 CPUFUNC(op_44fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4600_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4610_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, dst);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4618_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, dst);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4620_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, dst);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4628_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4630_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4638_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4639_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, dst);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4640_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4650_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, dst);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4658_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (srca, dst);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4660_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (srca, dst);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4668_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4670_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4678_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, dst);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4679_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (srca, dst);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4680_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4690_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, dst);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4698_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (srca, dst);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (srca, dst);
+}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, dst);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, dst);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46b8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, dst);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46b9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (srca, dst);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_46c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_310760; }
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.sr = src;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+l_310760: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_310761; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (2);
+l_310761: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_46d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_310762; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (2);
+l_310762: ;
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_310763; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (2);
+l_310763: ;
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_310764; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (4);
+l_310764: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_310765; }
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}}l_310765: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_310766; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (4);
+l_310766: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_310767; }
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (6);
+l_310767: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_310768; }
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (4);
+l_310768: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_310769; }
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}}l_310769: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_46fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_310770; }
+{{	uae_s16 src = get_iword_mmu040 (2);
+	regs.sr = src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_310770: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4800_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LINK.L An,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4808_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 22; 
+{	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+{	uae_s32 offs;
+	offs = get_ilong_mmu040 (2);
+	mmufixup[0].reg = -1;
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = (m68k_areg(regs, 7));
+	m68k_areg(regs, 7) += offs;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (olda, src);
+}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* NBCD.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4810_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, newv);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4818_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, newv);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4820_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, newv);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4828_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, newv);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4830_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, newv);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4838_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, newv);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4839_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, newv);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SWAP.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4840_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 34;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BKPTQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4848_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 99;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PEA.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4850_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, srca);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4868_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, srca);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4870_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, srca);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4878_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, srca);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4879_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, srca);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_487a_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, srca);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_487b_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, srca);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EXT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4880_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u16 dst = (uae_s16)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4890_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = m68k_areg (regs, dstreg);
+}{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		put_word_mmu040 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_word_mmu040 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 6;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = m68k_areg (regs, dstreg) - 0;
+}{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (amask) {
+		srca -= 2;
+		put_word_mmu040 (srca, m68k_areg (regs, movem_index2[amask]));
+		amask = movem_next[amask];
+	}
+	while (dmask) {
+		srca -= 2;
+		put_word_mmu040 (srca, m68k_dreg (regs, movem_index2[dmask]));
+		dmask = movem_next[dmask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	mmu040_movem = 0;
+}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+}{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		put_word_mmu040 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_word_mmu040 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48b0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+}{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		put_word_mmu040 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_word_mmu040 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48b8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+}{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		put_word_mmu040 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_word_mmu040 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48b9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = get_ilong_mmu040 (4);
+}{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		put_word_mmu040 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_word_mmu040 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EXT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_48c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48d0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = m68k_areg (regs, dstreg);
+}{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		put_long_mmu040 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_long_mmu040 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 10; 
+{	uae_u16 mask = get_iword_mmu040 (2);
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = m68k_areg (regs, dstreg) - 0;
+}{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (amask) {
+		srca -= 4;
+		put_long_mmu040 (srca, m68k_areg (regs, movem_index2[amask]));
+		amask = movem_next[amask];
+	}
+	while (dmask) {
+		srca -= 4;
+		put_long_mmu040 (srca, m68k_dreg (regs, movem_index2[dmask]));
+		dmask = movem_next[dmask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	mmu040_movem = 0;
+}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+}{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		put_long_mmu040 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_long_mmu040 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48f0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+}{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		put_long_mmu040 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_long_mmu040 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+}{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		put_long_mmu040 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_long_mmu040 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = get_ilong_mmu040 (4);
+}{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		put_long_mmu040 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_long_mmu040 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXT.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_49c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a00_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a10_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a18_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a20_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a28_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a30_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a38_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a39_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3a_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3b_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B #.B */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3c_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a40_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a48_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a50_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a58_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a60_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a68_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a70_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a78_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a79_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7a_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7b_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7c_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a80_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.L An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a88_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a90_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a98_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4aba_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4abb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4abc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TAS.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4ac0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((src) & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_lrmw_byte_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_lrmw_byte_mmu040 (srca, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_lrmw_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_lrmw_byte_mmu040 (srca, src);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_lrmw_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_lrmw_byte_mmu040 (srca, src);
+}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_lrmw_byte_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_lrmw_byte_mmu040 (srca, src);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4af0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_lrmw_byte_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_lrmw_byte_mmu040 (srca, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4af8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_lrmw_byte_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_lrmw_byte_mmu040 (srca, src);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4af9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_lrmw_byte_mmu040 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_lrmw_byte_mmu040 (srca, src);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MULL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c00_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_310847;
+}}}l_310847: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c10_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_310848;
+}}}}l_310848: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c18_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_310849;
+}}}}l_310849: ;
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c20_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_310850;
+}}}}l_310850: ;
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c28_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_310851;
+}}}}l_310851: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c30_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_310852;
+}}}}}l_310852: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c38_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_310853;
+}}}}l_310853: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c39_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_310854;
+}}}}l_310854: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_310855;
+}}}}l_310855: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_310856;
+}}}}}l_310856: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3c_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uae_s32 dst;
+	dst = get_ilong_mmu040 (4);
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_310857;
+}}}l_310857: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c40_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_310858;
+}}}l_310858: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c50_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_310859;
+}}}}l_310859: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c58_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_310860;
+}}}}l_310860: ;
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c60_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_310861;
+}}}}l_310861: ;
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c68_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_310862;
+}}}}l_310862: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c70_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_310863;
+}}}}}l_310863: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c78_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_310864;
+}}}}l_310864: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c79_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_310865;
+}}}}l_310865: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_310866;
+}}}}l_310866: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_310867;
+}}}}}l_310867: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7c_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uae_s32 dst;
+	dst = get_ilong_mmu040 (4);
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_310868;
+}}}l_310868: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVMEL.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4c90_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = m68k_areg (regs, dstreg);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4c98_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = m68k_areg (regs, dstreg);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	mmu040_movem = 0;
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ca8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = get_ilong_mmu040 (4);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cba_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (4);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cbb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = m68k_areg (regs, dstreg);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long_mmu040 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long_mmu040 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = m68k_areg (regs, dstreg);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long_mmu040 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long_mmu040 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	mmu040_movem = 0;
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ce8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long_mmu040 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long_mmu040 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long_mmu040 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long_mmu040 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long_mmu040 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long_mmu040 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = get_ilong_mmu040 (4);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long_mmu040 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long_mmu040 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (4);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long_mmu040 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long_mmu040 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu040 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+	if (mmu040_movem) {
+		srca = mmu040_movem_ea;
+	} else
+{{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+}{	mmu040_movem = 1;
+	mmu040_movem_ea = srca;
+	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = get_long_mmu040 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = get_long_mmu040 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	mmu040_movem = 0;
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* TRAPQ.L # */
+uae_u32 REGPARAM2 CPUFUNC(op_4e40_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 15);
+	OpcodeFamily = 39;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	Exception (src + 32);
+}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* LINK.W An,#.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e50_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 18; 
+{	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	mmufixup[0].reg = -1;
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = (m68k_areg(regs, 7));
+	m68k_areg(regs, 7) += offs;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (olda, src);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* UNLK.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e58_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 48;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	uae_s32 old = get_long_mmu040 (src);
+	m68k_areg (regs, 7) = src + 4;
+	m68k_areg (regs, srcreg) = old;
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVR2USP.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e60_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 40;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_310888; }
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	regs.usp = src;
+}}}	m68k_incpci (2);
+l_310888: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVUSP2R.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e68_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 41;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_310889; }
+{{	m68k_areg (regs, srcreg) = (regs.usp);
+}}}	m68k_incpci (2);
+l_310889: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RESET.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e70_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 42;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_310890; }
+{	cpureset ();
+	m68k_incpci (2);
+}}l_310890: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOP.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e71_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 43;
+	CurrentInstrCycles = 4;  
+{}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* STOP.L #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e72_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 44;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_310892; }
+{{	uae_s16 src = get_iword_mmu040 (2);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_setstopped ();
+	m68k_incpci (4);
+}}}l_310892: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RTE.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e73_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 45;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_310893; }
+{	uae_u16 newsr; uae_u32 newpc;
+	for (;;) {
+		uaecptr a = m68k_areg (regs, 7);
+		uae_u16 sr = get_word_mmu040 (a);
+		uae_u32 pc = get_long_mmu040 (a + 2);
+		uae_u16 format = get_word_mmu040 (a + 2 + 4);
+		int frame = format >> 12;
+		int offset = 8;
+		newsr = sr; newpc = pc;
+		if (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }
+		else if (frame == 0x1) { m68k_areg (regs, 7) += offset; }
+		else if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }
+		else if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }
+		else if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }
+		else if (frame == 0x7) { m68k_do_rte_mmu040 (a); m68k_areg (regs, 7) += offset + 52; break; }
+		else if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }
+		else if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }
+		else if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }
+		else { m68k_areg (regs, 7) += offset; Exception (14); goto l_310893; }
+		regs.sr = newsr;
+	MakeFromSR();
+}
+	regs.sr = newsr;
+	MakeFromSR();
+	if (newpc & 1) {
+		exception3i (0x4E73, newpc);
+		goto l_310893;
+	}
+	m68k_setpci (newpc);
+}}l_310893: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RTD.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e74_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 46;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 offs = get_iword_mmu040 (2);
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = get_long_mmu040 (pca);
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) += 4;
+	m68k_areg(regs, 7) += offs;
+	if (pc & 1) {
+		exception3i (0x4E74, pc);
+		goto l_310894;
+	}
+	m68k_setpci (pc);
+}}}}l_310894: ;
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* RTS.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e75_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 49;
+	CurrentInstrCycles = 8;  
+{	uaecptr pc = m68k_getpci ();
+	m68k_do_rts_mmu040 ();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (pc);
+		exception3i (0x4E75, faultpc);
+		goto l_310895;
+	}
+}l_310895: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TRAPV.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e76_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 50;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	if (GET_VFLG ()) {
+		Exception (7);
+		goto l_310896;
+	}
+}l_310896: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RTR.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e77_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 51;
+	CurrentInstrCycles = 16; 
+{	uaecptr oldpc = m68k_getpci ();
+	MakeSR ();
+{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+{	uae_s16 sr = get_word_mmu040 (sra);
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = get_long_mmu040 (pca);
+	m68k_areg (regs, 7) += 4;
+	mmufixup[0].reg = -1;
+	regs.sr &= 0xFF00; sr &= 0xFF;
+	regs.sr |= sr;
+	m68k_setpci (pc);
+	MakeFromSR();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (oldpc);
+		exception3i (0x4E77, faultpc);
+		goto l_310897;
+	}
+}}}}}l_310897: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEC2.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7a_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 82;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_310898; }
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_movec2(src & 0xFFF, regp)) goto l_310898;
+}}}}	m68k_incpci (4);
+l_310898: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE2C.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7b_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 83;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_310899; }
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_move2c(src & 0xFFF, regp)) goto l_310899;
+}}}}	m68k_incpci (4);
+l_310899: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* JSR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4e90_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr oldpc = m68k_getpci () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_310900;
+	}
+	put_long_mmu040 (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_310900: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ea8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_310901;
+	}
+	put_long_mmu040 (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_310901: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_310902;
+	}
+	put_long_mmu040 (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}}l_310902: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_310903;
+	}
+	put_long_mmu040 (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_310903: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uaecptr oldpc = m68k_getpci () + 6;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_310904;
+	}
+	put_long_mmu040 (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_310904: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eba_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_310905;
+	}
+	put_long_mmu040 (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_310905: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ebb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_310906;
+	}
+	put_long_mmu040 (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}}l_310906: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ed0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_310907;
+	}
+	m68k_setpci (srca);
+}}l_310907: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ee8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_310908;
+	}
+	m68k_setpci (srca);
+}}l_310908: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_310909;
+	}
+	m68k_setpci (srca);
+}}}l_310909: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_310910;
+	}
+	m68k_setpci (srca);
+}}l_310910: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_310911;
+	}
+	m68k_setpci (srca);
+}}l_310911: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_310912;
+	}
+	m68k_setpci (srca);
+}}l_310912: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_310913;
+	}
+	m68k_setpci (srca);
+}}}l_310913: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5000_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5010_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5018_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5020_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5028_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5030_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5038_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5039_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5040_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5048_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5050_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5058_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5060_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5068_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5070_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5078_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5079_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5080_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5088_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5090_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5098_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_5
+/* ADDQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_50b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_50b8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_50b9_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (0) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (0)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_310941;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_310941: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (0) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (0) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (0) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (0) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (0)) { Exception (7); goto l_310949; }
+}}	m68k_incpci (4);
+l_310949: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (0)) { Exception (7); goto l_310950; }
+}}	m68k_incpci (6);
+l_310950: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (0)) { Exception (7); goto l_310951; }
+}	m68k_incpci (2);
+l_310951: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* SUBQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5100_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5110_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5118_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5120_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5128_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5130_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5138_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5139_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5140_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5148_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5150_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5158_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5160_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5168_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5170_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5178_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5179_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5180_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5188_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5190_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5198_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_51b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_51b8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_51b9_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (1) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (1)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_310979;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_310979: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (1) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (1) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (1) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (1) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (1)) { Exception (7); goto l_310987; }
+}}	m68k_incpci (4);
+l_310987: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (1)) { Exception (7); goto l_310988; }
+}}	m68k_incpci (6);
+l_310988: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (1)) { Exception (7); goto l_310989; }
+}	m68k_incpci (2);
+l_310989: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (2) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (2)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_310991;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_310991: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (2) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (2) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (2) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (2) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (2)) { Exception (7); goto l_310999; }
+}}	m68k_incpci (4);
+l_310999: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (2)) { Exception (7); goto l_311000; }
+}}	m68k_incpci (6);
+l_311000: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (2)) { Exception (7); goto l_311001; }
+}	m68k_incpci (2);
+l_311001: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (3) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (3)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_311003;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_311003: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (3) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (3) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (3) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (3) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (3)) { Exception (7); goto l_311011; }
+}}	m68k_incpci (4);
+l_311011: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (3)) { Exception (7); goto l_311012; }
+}}	m68k_incpci (6);
+l_311012: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (3)) { Exception (7); goto l_311013; }
+}	m68k_incpci (2);
+l_311013: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (4) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (4)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_311015;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_311015: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (4) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (4) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (4) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (4) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (4)) { Exception (7); goto l_311023; }
+}}	m68k_incpci (4);
+l_311023: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (4)) { Exception (7); goto l_311024; }
+}}	m68k_incpci (6);
+l_311024: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (4)) { Exception (7); goto l_311025; }
+}	m68k_incpci (2);
+l_311025: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (5) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (5)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_311027;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_311027: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (5) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (5) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (5) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (5) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (5)) { Exception (7); goto l_311035; }
+}}	m68k_incpci (4);
+l_311035: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (5)) { Exception (7); goto l_311036; }
+}}	m68k_incpci (6);
+l_311036: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (5)) { Exception (7); goto l_311037; }
+}	m68k_incpci (2);
+l_311037: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (6) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (6)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_311039;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_311039: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (6) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (6) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (6) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (6) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (6)) { Exception (7); goto l_311047; }
+}}	m68k_incpci (4);
+l_311047: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (6)) { Exception (7); goto l_311048; }
+}}	m68k_incpci (6);
+l_311048: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (6)) { Exception (7); goto l_311049; }
+}	m68k_incpci (2);
+l_311049: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (7) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (7)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_311051;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_311051: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (7) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (7) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (7) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (7) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (7)) { Exception (7); goto l_311059; }
+}}	m68k_incpci (4);
+l_311059: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (7)) { Exception (7); goto l_311060; }
+}}	m68k_incpci (6);
+l_311060: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (7)) { Exception (7); goto l_311061; }
+}	m68k_incpci (2);
+l_311061: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (8) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (8)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_311063;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_311063: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (8) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (8) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (8) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (8) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (8)) { Exception (7); goto l_311071; }
+}}	m68k_incpci (4);
+l_311071: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (8)) { Exception (7); goto l_311072; }
+}}	m68k_incpci (6);
+l_311072: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (8)) { Exception (7); goto l_311073; }
+}	m68k_incpci (2);
+l_311073: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (9) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (9)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_311075;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_311075: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (9) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (9) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (9) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (9) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (9)) { Exception (7); goto l_311083; }
+}}	m68k_incpci (4);
+l_311083: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (9)) { Exception (7); goto l_311084; }
+}}	m68k_incpci (6);
+l_311084: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (9)) { Exception (7); goto l_311085; }
+}	m68k_incpci (2);
+l_311085: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (10) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (10)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_311087;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_311087: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (10) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (10) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (10) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (10) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (10)) { Exception (7); goto l_311095; }
+}}	m68k_incpci (4);
+l_311095: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (10)) { Exception (7); goto l_311096; }
+}}	m68k_incpci (6);
+l_311096: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (10)) { Exception (7); goto l_311097; }
+}	m68k_incpci (2);
+l_311097: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (11) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (11)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_311099;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_311099: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (11) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (11) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (11) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (11) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (11)) { Exception (7); goto l_311107; }
+}}	m68k_incpci (4);
+l_311107: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (11)) { Exception (7); goto l_311108; }
+}}	m68k_incpci (6);
+l_311108: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (11)) { Exception (7); goto l_311109; }
+}	m68k_incpci (2);
+l_311109: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (12) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (12)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_311111;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_311111: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (12) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (12) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (12) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (12) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (12)) { Exception (7); goto l_311119; }
+}}	m68k_incpci (4);
+l_311119: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (12)) { Exception (7); goto l_311120; }
+}}	m68k_incpci (6);
+l_311120: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (12)) { Exception (7); goto l_311121; }
+}	m68k_incpci (2);
+l_311121: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (13) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (13)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_311123;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_311123: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (13) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (13) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (13) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (13) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (13)) { Exception (7); goto l_311131; }
+}}	m68k_incpci (4);
+l_311131: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (13)) { Exception (7); goto l_311132; }
+}}	m68k_incpci (6);
+l_311132: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (13)) { Exception (7); goto l_311133; }
+}	m68k_incpci (2);
+l_311133: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (14) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (14)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_311135;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_311135: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (14) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (14) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (14) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (14) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (14)) { Exception (7); goto l_311143; }
+}}	m68k_incpci (4);
+l_311143: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (14)) { Exception (7); goto l_311144; }
+}}	m68k_incpci (6);
+l_311144: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (14)) { Exception (7); goto l_311145; }
+}	m68k_incpci (2);
+l_311145: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (15) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu040 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (15)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_311147;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_311147: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (15) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (15) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (15) ? 0xff : 0;
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (srca, val);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (15) ? 0xff : 0;
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (srca, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffa_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu040 (2);
+	if (cctrue (15)) { Exception (7); goto l_311155; }
+}}	m68k_incpci (4);
+l_311155: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffb_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (2);
+	if (cctrue (15)) { Exception (7); goto l_311156; }
+}}	m68k_incpci (6);
+l_311156: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffc_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (15)) { Exception (7); goto l_311157; }
+}	m68k_incpci (2);
+l_311157: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Bcc.W #.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6000_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311158;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311158: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6001_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311159;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311159: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_60ff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311160;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311160: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_6100_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_s16 src = get_iword_mmu040 (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_311161;
+	}
+	m68k_do_bsr_mmu040 (m68k_getpci () + 4, s);
+}}l_311161: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSRQ.B # */
+uae_u32 REGPARAM2 CPUFUNC(op_6101_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_u32 src = srcreg;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_311162;
+	}
+	m68k_do_bsr_mmu040 (m68k_getpci () + 2, s);
+}}l_311162: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSR.L #.L */
+uae_u32 REGPARAM2 CPUFUNC(op_61ff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_311163;
+	}
+	m68k_do_bsr_mmu040 (m68k_getpci () + 6, s);
+}}l_311163: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6200_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311164;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311164: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6201_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311165;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311165: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_62ff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311166;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311166: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6300_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311167;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311167: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6301_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311168;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311168: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_6
+/* Bcc.L #.L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_63ff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311169;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311169: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6400_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311170;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311170: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6401_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311171;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311171: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_64ff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311172;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311172: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6500_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311173;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311173: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6501_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311174;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311174: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_65ff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311175;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311175: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6600_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311176;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311176: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6601_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311177;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311177: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_66ff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311178;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311178: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6700_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311179;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311179: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6701_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311180;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311180: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_67ff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311181;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311181: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6800_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311182;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311182: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6801_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311183;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311183: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_68ff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311184;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311184: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6900_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311185;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311185: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6901_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311186;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311186: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_69ff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311187;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311187: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a00_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311188;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311188: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a01_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311189;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311189: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6aff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311190;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311190: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b00_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311191;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311191: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b01_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311192;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311192: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6bff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311193;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311193: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c00_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311194;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311194: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c01_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311195;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311195: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6cff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311196;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311196: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d00_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311197;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311197: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d01_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311198;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311198: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6dff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311199;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311199: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e00_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311200;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311200: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e01_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311201;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311201: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6eff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311202;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311202: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f00_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311203;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_311203: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f01_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311204;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_311204: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6fff_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_311205;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_311205: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_7000_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8000_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8010_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8018_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8020_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8028_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8030_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8038_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8039_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8040_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8050_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8058_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8060_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8068_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8070_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8078_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8079_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8080_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8090_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8098_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80ba_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 110;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_311240;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}l_311240: ;
+return 110 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 114;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_311241;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}l_311241: ;
+return 114 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 114;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_311242;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}l_311242: ;
+return 114 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 116;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_311243;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}l_311243: ;
+return 116 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_311244;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}l_311244: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_311245;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_311245: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_311246;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}l_311246: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 122;
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_311247;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (6);
+	}
+}}}}l_311247: ;
+return 122 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_311248;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}l_311248: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_311249;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_311249: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 114;
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_311250;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}l_311250: ;
+return 114 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8100_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8108_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	mmufixup[0].reg = -1;
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8110_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8118_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8120_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8128_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8130_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8138_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8139_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* PACK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8140_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val = m68k_dreg (regs, srcreg) + get_iword_mmu040 (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PACK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8148_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(get_byte_mmu040 (m68k_areg (regs, srcreg)) & 0xff);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (val | ((uae_u16)(get_byte_mmu040 (m68k_areg (regs, srcreg)) & 0xff) << 8)) + get_iword_mmu040 (2);
+	m68k_areg (regs, dstreg) -= areg_byteinc[dstreg];
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* OR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8150_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8158_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8160_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8168_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8170_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8178_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8179_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* UNPK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8180_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val = m68k_dreg (regs, srcreg);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_iword_mmu040 (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* UNPK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8188_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(get_byte_mmu040 (m68k_areg (regs, srcreg)) & 0xff);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_iword_mmu040 (2);
+	m68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];
+	put_byte_mmu040 (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);
+	put_byte_mmu040 (m68k_areg (regs, dstreg), val >> 8);
+}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* OR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8190_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8198_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_81b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_81b8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_81b9_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 142;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_311278;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}l_311278: ;
+return 142 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 146;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_311279;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}l_311279: ;
+return 146 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 146;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_311280;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}l_311280: ;
+return 146 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 148;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_311281;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}l_311281: ;
+return 148 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_311282;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}l_311282: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_311283;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_311283: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_311284;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}l_311284: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 154;
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_311285;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (6);
+}}}}l_311285: ;
+return 154 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_311286;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}l_311286: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_311287;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_311287: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 146;
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_311288;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}l_311288: ;
+return 146 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9000_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9010_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9018_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9020_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9028_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9030_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9038_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9039_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9040_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9048_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9050_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9058_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9060_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9068_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9070_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9078_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9079_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9080_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9088_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9090_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9098_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90ba_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9100_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9108_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9110_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9118_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9120_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9128_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9130_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9138_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9139_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9140_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9148_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9150_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9158_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9160_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9168_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9170_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9178_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9179_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9180_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9188_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9190_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9198_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_91b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_91b8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_91b9_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b000_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b010_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b018_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b020_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b028_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b030_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b038_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b039_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b040_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b048_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b050_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b058_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b060_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b068_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b070_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b078_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b079_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b080_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b088_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b090_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b098_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_7
+/* CMP.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0ba_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b100_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b108_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b110_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b118_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b120_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b128_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b130_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b138_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b139_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b140_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b148_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b150_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b158_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b160_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b168_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b170_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b178_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b179_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b180_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b188_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b190_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b198_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b9_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c000_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c010_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c018_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c020_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c028_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c030_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c038_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c039_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c040_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c050_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c058_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c060_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c068_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c070_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c078_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c079_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c080_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c090_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c098_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0ba_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 58; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}return 58 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 62; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return 62 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 62; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return 62 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 64; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return 64 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 70; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (6);
+}}}}}return 70 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 62; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}return 62 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c100_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c108_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	mmufixup[0].reg = -1;
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c110_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c118_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c120_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, src);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c128_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c130_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c138_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c139_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c140_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c148_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	m68k_areg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c150_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c158_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c160_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, src);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c168_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c170_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c178_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c179_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c188_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c190_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c198_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, src);
+}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b9_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, src);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 58; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 58 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 62; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 62; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 64; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 64 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 70; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 70 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 62; 
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d000_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d010_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d018_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d020_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d028_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d030_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d038_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d039_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu040 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu040 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d040_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d048_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d050_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d058_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d060_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d068_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d070_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d078_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d079_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07c_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d080_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d088_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d090_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d098_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0ba_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu040 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d100_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d108_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d110_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d118_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d120_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d128_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d130_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d138_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d139_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s8 dst = get_byte_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_byte_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d140_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d148_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d150_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d158_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d160_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d168_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d170_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d178_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d179_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s16 dst = get_word_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d180_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d188_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d190_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d198_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu040 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 22 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b9_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (2);
+{	uae_s32 dst = get_long_mmu040 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_long_mmu040 (dsta, newv);
+}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu040 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = -1;
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f9_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu040 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fc_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu040 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e000_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e008_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e010_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e018_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e020_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e028_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e030_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e038_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e040_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_8
+/* LSRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e048_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e050_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e058_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e060_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e068_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e070_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e078_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e080_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e088_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e090_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e098_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e100_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e108_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e110_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e118_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e120_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e128_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e130_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e138_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e140_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e148_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e150_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e158_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e160_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e168_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e170_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e178_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e180_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e188_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e190_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e198_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu040 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	m68k_incpci (2);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	mmufixup[0].reg = -1;
+	put_word_mmu040 (dataa, val);
+}}}}return 14 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e8_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	m68k_incpci (4);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu040 (2);
+{	uae_s16 data = get_word_mmu040 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	m68k_incpci (6);
+	regs.instruction_pc = m68k_getpci ();
+	mmu_restart = false;
+	put_word_mmu040 (dataa, val);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BFTST.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8c0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8d0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8e8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9c0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9d0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9e8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9fa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9fb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eac0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ead0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eae8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebc0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebd0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebe8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebfa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebfb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecc0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecd0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ece8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edc0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edd0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ede8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edfa_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edfb_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eec0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eed0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eee8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efc0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efd0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efe8_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff0_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff8_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff9_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu040 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu040 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L Dn,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f000_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311788; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	uae_u16 extraa = 0;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}l_311788: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L An,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f008_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311789; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	uae_u16 extraa = 0;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}l_311789: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f010_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311790; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_311790: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (An)+,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f018_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311791; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_311791: ;
+	mmufixup[0].reg = -1;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L -(An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f020_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 6;  
+{if (!regs.s) { Exception (8); goto l_311792; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) - 4;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = extraa;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_311792: ;
+	mmufixup[0].reg = -1;
+return 6 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (d16,An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f028_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_311793; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040 (0);
+	m68k_incpci (2);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_311793: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (d8,An,Xn),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f030_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_311794; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+{	extraa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}}l_311794: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (xxx).W,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f038_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_311795; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = (uae_s32)(uae_s16)get_iword_mmu040 (0);
+	m68k_incpci (2);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_311795: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (xxx).L,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f039_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_311796; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = get_ilong_mmu040 (0);
+	m68k_incpci (4);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_311796: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f200_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f208_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f210_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f218_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f220_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f228_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f230_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f238_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f239_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23a_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23b_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23c_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f240_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FDBcc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f248_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 105;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_dbcc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f250_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f258_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f260_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f268_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f270_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f278_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f279_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27a_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 12; 
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu040 (2);
+{	uae_s16 dummy = get_iword_mmu040 (4);
+	m68k_incpci (6);
+	fpuop_trapcc (opcode, oldpc, extra);
+}
+#endif
+}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27b_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 16; 
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu040 (2);
+{	uae_s32 dummy;
+	dummy = get_ilong_mmu040 (4);
+	m68k_incpci (8);
+	fpuop_trapcc (opcode, oldpc, extra);
+}
+#endif
+}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L  */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27c_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu040 (2);
+	m68k_incpci (4);
+	fpuop_trapcc (opcode, oldpc, extra);
+
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FBccQ.L #,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f280_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s16 extra = get_iword_mmu040 (0);
+	m68k_incpci (2);
+	fpuop_bcc (opcode, pc,extra);
+}}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FBccQ.L #,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f2c0_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+	CurrentInstrCycles = 12; 
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s32 extra;
+	extra = get_ilong_mmu040 (0);
+	m68k_incpci (4);
+	fpuop_bcc (opcode, pc,extra);
+}}
+#endif
+}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f310_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311823; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_311823: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f320_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311824; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_311824: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f328_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311825; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_311825: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f330_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311826; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_311826: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f338_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311827; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_311827: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f339_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311828; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_311828: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f350_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311829; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_311829: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f358_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311830; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_311830: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f368_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311831; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_311831: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f370_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311832; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_311832: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f378_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311833; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_311833: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f379_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311834; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_311834: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f37a_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311835; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_311835: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f37b_31)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311836; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_311836: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVLQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f408_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 111;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311837; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311837: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVPQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f410_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 112;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311838; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311838: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f418_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311839; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311839: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f419_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311840; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311840: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41a_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311841; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311841: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41b_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311842; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311842: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41c_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311843; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311843: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41d_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311844; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311844: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41e_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311845; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311845: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41f_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311846; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311846: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHLQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f428_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 114;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311847; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311847: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHPQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f430_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 115;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311848; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311848: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f438_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311849; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311849: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f439_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311850; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311850: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43a_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311851; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311851: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43b_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311852; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311852: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43c_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311853; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311853: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43d_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311854; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311854: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43e_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311855; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311855: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43f_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311856; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu040(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_311856: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSHN.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f500_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 119;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311857; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_311857: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSH.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f508_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 120;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311858; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_311858: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSHAN.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f510_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 121;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311859; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_311859: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSHA.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f518_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 122;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311860; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_311860: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PTESTW.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f548_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 126;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311861; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_311861: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PTESTR.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f568_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 125;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_311862; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_311862: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (An)+,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f600_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = m68k_areg (regs, srcreg);
+{	uaecptr memda;
+	memda = get_ilong_mmu040 (2);
+	get_move16_mmu (memsa, mmu040_move16);
+	put_move16_mmu (memda, mmu040_move16);
+	m68k_areg (regs, srcreg) += 16;
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (xxx).L,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f608_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = get_ilong_mmu040 (2);
+{	uaecptr memda;
+	memda = m68k_areg (regs, dstreg);
+	get_move16_mmu (memsa, mmu040_move16);
+	put_move16_mmu (memda, mmu040_move16);
+	m68k_areg (regs, dstreg) += 16;
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (An),(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f610_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = m68k_areg (regs, srcreg);
+{	uaecptr memda;
+	memda = get_ilong_mmu040 (2);
+	get_move16_mmu (memsa, mmu040_move16);
+	put_move16_mmu (memda, mmu040_move16);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (xxx).L,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f618_31)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = get_ilong_mmu040 (2);
+{	uaecptr memda;
+	memda = m68k_areg (regs, dstreg);
+	get_move16_mmu (memsa, mmu040_move16);
+	put_move16_mmu (memda, mmu040_move16);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (An)+,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f620_31)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = 0;
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 8;  
+{	uae_u32 v[4];
+	uaecptr mems = m68k_areg (regs, srcreg) & ~15, memd;
+	dstreg = (get_iword_mmu040 (2) >> 12) & 7;
+	memd = m68k_areg (regs, dstreg) & ~15;
+	get_move16_mmu (mems, v);
+	put_move16_mmu (memd, v);
+	if (srcreg != dstreg)
+		m68k_areg (regs, srcreg) += 16;
+	m68k_areg (regs, dstreg) += 16;
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
diff --git a/src/cpu/cpuemu_32.c b/src/cpu/cpuemu_32.c
new file mode 100644
index 0000000..c93de13
--- /dev/null
+++ b/src/cpu/cpuemu_32.c
@@ -0,0 +1,39754 @@
+#include "main.h"
+#include "sysdeps.h"
+#include "hatari-glue.h"
+#include "maccess.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "cputbl.h"
+#include "cpummu030.h"
+#define CPUFUNC(x) x##_ff
+#define SET_CFLG_ALWAYS(x) SET_CFLG(x)
+#define SET_NFLG_ALWAYS(x) SET_NFLG(x)
+#ifdef NOFLAGS
+#include "noflags.h"
+#endif
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0000_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0010_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0018_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0020_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0028_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0030_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0038_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0039_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (8);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* ORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_003c_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu030_state (2);
+	src &= 0xFF;
+	regs.sr |= src;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0040_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0050_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0058_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0060_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0068_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0070_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0078_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0079_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_007c_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_320018; }
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu030_state (2);
+	regs.sr |= src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_320018: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0080_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0090_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0098_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 30 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_00b0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_00b8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_00b9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (10);
+return 36 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00d0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu030_state (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu030_state (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320027; }
+}
+}}}	m68k_incpci (4);
+l_320027: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00e8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu030_state (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu030_state (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320028; }
+}
+}}}	m68k_incpci (6);
+l_320028: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu030_state (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu030_state (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320029; }
+}
+}}}}l_320029: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu030_state (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu030_state (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320030; }
+}
+}}}	m68k_incpci (6);
+l_320030: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu030_state (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu030_state (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320031; }
+}
+}}}	m68k_incpci (8);
+l_320031: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu030_state (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu030_state (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320032; }
+}
+}}}	m68k_incpci (6);
+l_320032: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = get_disp_ea_020_mmu030 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu030_state (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu030_state (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320033; }
+}
+}}}}l_320033: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BTST.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0100_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPMR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0108_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 8;  
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_u16 val;
+	MovepByteNbr=1; val = ((get_byte_mmu030_state (memp) & 0xff) << 8);
+	MovepByteNbr=2; val += (get_byte_mmu030_state (memp + 2) & 0xff);
+	MovepByteNbr=0;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0110_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0118_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0120_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0128_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0130_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0138_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0139_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_013a_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 2;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_013b_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	dsta = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,#.B */
+uae_u32 REGPARAM2 CPUFUNC(op_013c_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = get_ibyte_mmu030_state (2);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0140_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPMR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0148_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 16; 
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_u32 val;
+	MovepByteNbr=1; val = ((get_byte_mmu030_state (memp) & 0xff) << 24);
+	MovepByteNbr=2; val += ((get_byte_mmu030_state (memp + 2) & 0xff) << 16);
+	MovepByteNbr=3; val += ((get_byte_mmu030_state (memp + 4) & 0xff) << 8);
+	MovepByteNbr=4; val += (get_byte_mmu030_state (memp + 6) & 0xff);
+	MovepByteNbr=0;
+	m68k_dreg (regs, dstreg) = (val);
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0150_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0158_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0160_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0168_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0170_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0178_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0179_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0180_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPRM.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0188_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	MovepByteNbr=1; 	put_byte_mmu030_state (memp, src >> 8);
+	MovepByteNbr=2; 	put_byte_mmu030_state (memp + 2, src);
+	MovepByteNbr=0;
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0190_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0198_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01b8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01b9_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BSET.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_01c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPRM.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	MovepByteNbr=1; 	put_byte_mmu030_state (memp, src >> 24);
+	MovepByteNbr=2; 	put_byte_mmu030_state (memp + 2, src >> 16);
+	MovepByteNbr=3; 	put_byte_mmu030_state (memp + 4, src >> 8);
+	MovepByteNbr=4; 	put_byte_mmu030_state (memp + 6, src);
+	MovepByteNbr=0;
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_01d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01f8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01f9_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0200_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0210_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0218_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0220_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0228_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0230_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0238_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0239_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (8);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* ANDSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_023c_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu030_state (2);
+	src |= 0xFF00;
+	regs.sr &= src;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0240_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0250_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0258_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0260_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0268_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0270_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0278_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0279_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ANDSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_027c_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_320090; }
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu030_state (2);
+	regs.sr &= src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_320090: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0280_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0290_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0298_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 30 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_02b0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_02b8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_02b9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (10);
+return 36 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02d0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu030_state (dsta); upper = (uae_s32)(uae_s16)get_word_mmu030_state (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320099; }
+}
+}}}	m68k_incpci (4);
+l_320099: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02e8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu030_state (dsta); upper = (uae_s32)(uae_s16)get_word_mmu030_state (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320100; }
+}
+}}}	m68k_incpci (6);
+l_320100: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu030_state (dsta); upper = (uae_s32)(uae_s16)get_word_mmu030_state (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320101; }
+}
+}}}}l_320101: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu030_state (dsta); upper = (uae_s32)(uae_s16)get_word_mmu030_state (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320102; }
+}
+}}}	m68k_incpci (6);
+l_320102: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu030_state (dsta); upper = (uae_s32)(uae_s16)get_word_mmu030_state (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320103; }
+}
+}}}	m68k_incpci (8);
+l_320103: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu030_state (dsta); upper = (uae_s32)(uae_s16)get_word_mmu030_state (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320104; }
+}
+}}}	m68k_incpci (6);
+l_320104: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = get_disp_ea_020_mmu030 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu030_state (dsta); upper = (uae_s32)(uae_s16)get_word_mmu030_state (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320105; }
+}
+}}}}l_320105: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0400_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0410_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0418_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0420_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0428_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0430_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0438_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0439_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0440_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0450_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0458_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0460_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0468_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0470_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0478_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0479_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0480_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0490_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0498_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 30 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_04b0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_04b8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_04b9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (10);
+return 36 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04d0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu030_state (dsta); upper = get_long_mmu030_state (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320130; }
+}
+}}}	m68k_incpci (4);
+l_320130: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04e8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu030_state (dsta); upper = get_long_mmu030_state (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320131; }
+}
+}}}	m68k_incpci (6);
+l_320131: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu030_state (dsta); upper = get_long_mmu030_state (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320132; }
+}
+}}}}l_320132: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu030_state (dsta); upper = get_long_mmu030_state (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320133; }
+}
+}}}	m68k_incpci (6);
+l_320133: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu030_state (dsta); upper = get_long_mmu030_state (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320134; }
+}
+}}}	m68k_incpci (8);
+l_320134: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu030_state (dsta); upper = get_long_mmu030_state (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320135; }
+}
+}}}	m68k_incpci (6);
+l_320135: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = get_disp_ea_020_mmu030 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu030_state (dsta); upper = get_long_mmu030_state (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_320136; }
+}
+}}}}l_320136: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0600_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0610_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0618_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0620_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0628_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0630_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0638_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0639_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0640_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0650_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0658_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0660_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0668_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0670_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0678_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0679_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0680_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0690_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0698_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 30 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_06b0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_06b8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_06b9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (10);
+return 36 * CYCLE_UNIT / 2;
+}
+
+/* RTM.L Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* RTM.L An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BTST.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0800_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0810_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0818_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0820_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0828_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0830_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0838_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0839_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (8);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_083a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_083b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0840_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0850_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0858_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0860_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0868_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0870_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0878_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0879_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0880_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0890_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0898_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08b0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08b8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08b9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* BSET.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_08c0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08d0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_08d8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08f0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_byte_mmu030_state (dsta, dst);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a00_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a10_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a18_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a20_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a28_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a30_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a38_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a39_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (8);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* EORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a3c_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu030_state (2);
+	src &= 0xFF;
+	regs.sr ^= src;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a40_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a50_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a58_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a60_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a68_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a70_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a78_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a79_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* EORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a7c_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_320221; }
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu030_state (2);
+	regs.sr ^= src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_320221: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a80_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a90_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a98_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 30 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (10);
+return 36 * CYCLE_UNIT / 2;
+}
+
+/* CAS.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ad0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_lrmw_byte_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ad8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_lrmw_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ae0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_lrmw_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ae8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_lrmw_byte_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
+#ifdef PART_2
+/* CAS.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_lrmw_byte_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_lrmw_byte_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s8 dst = get_lrmw_byte_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c00_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c10_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c18_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c20_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c28_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c30_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c38_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c39_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c3a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.B #.B,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c3b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c40_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c50_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c58_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c60_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c68_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c70_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c78_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c79_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c7a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c7b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c80_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c90_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c98_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (10);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cba_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 6;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.L #.L,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cbb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (6);
+{	tmppc = m68k_getpci ();
+	dsta = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cd0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_lrmw_word_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cd8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_lrmw_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ce0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_lrmw_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ce8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_lrmw_word_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_lrmw_word_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 dst = get_lrmw_word_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s16 dst = get_lrmw_word_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS2.W #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cfc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 extra;
+	extra = get_ilong_mmu030_state (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u16 dst1 = get_lrmw_word_mmu030_state (rn1), dst2 = get_lrmw_word_mmu030_state (rn2);
+{uae_u32 newv = ((uae_u16)(dst1)) - ((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s16)(dst1)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u16)(dst2)) - ((uae_u16)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s16)(dst2)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, extra & 7))) > ((uae_u16)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	put_lrmw_word_mmu030_state (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	put_lrmw_word_mmu030_state (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);
+	m68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);
+	}
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e10_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_320275; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	dfc030_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = sfc030_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (4);
+l_320275: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e18_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_320276; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	dfc030_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = sfc030_get_byte (srca);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (4);
+l_320276: ;
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e20_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_320277; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	dfc030_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 src = sfc030_get_byte (srca);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (4);
+l_320277: ;
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e28_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_320278; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	dfc030_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 src = sfc030_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (6);
+l_320278: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e30_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_320279; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	dfc030_put_byte (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 1);
+{	uae_s8 src = sfc030_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}}l_320279: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e38_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_320280; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	dfc030_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s8 src = sfc030_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (6);
+l_320280: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e39_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_320281; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	dfc030_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (4);
+{	uae_s8 src = sfc030_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (8);
+l_320281: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e50_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_320282; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	dfc030_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = sfc030_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (4);
+l_320282: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e58_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_320283; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	dfc030_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = sfc030_get_word (srca);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (4);
+l_320283: ;
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e60_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_320284; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	dfc030_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 src = sfc030_get_word (srca);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (4);
+l_320284: ;
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e68_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_320285; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	dfc030_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 src = sfc030_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (6);
+l_320285: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e70_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_320286; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	dfc030_put_word (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 1);
+{	uae_s16 src = sfc030_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}}l_320286: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e78_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_320287; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	dfc030_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s16 src = sfc030_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (6);
+l_320287: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e79_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_320288; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	dfc030_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (4);
+{	uae_s16 src = sfc030_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (8);
+l_320288: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e90_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_320289; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	dfc030_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = sfc030_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (4);
+l_320289: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e98_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_320290; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	dfc030_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = sfc030_get_long (srca);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (4);
+l_320290: ;
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ea0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 28; 
+{if (!regs.s) { Exception (8); goto l_320291; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	dfc030_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 src = sfc030_get_long (srca);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (4);
+l_320291: ;
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ea8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_320292; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	dfc030_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s32 src = sfc030_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (6);
+l_320292: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_320293; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	dfc030_put_long (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 1);
+{	uae_s32 src = sfc030_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}}l_320293: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_320294; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	dfc030_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s32 src = sfc030_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (6);
+l_320294: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 40; 
+{if (!regs.s) { Exception (8); goto l_320295; }
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	dfc030_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (4);
+{	uae_s32 src = sfc030_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (8);
+l_320295: ;
+return 40 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ed0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_lrmw_long_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ed8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_lrmw_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ee0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 26; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_lrmw_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 26 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ee8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 28; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s32 dst = get_lrmw_long_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 28; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_lrmw_long_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 28; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s32 dst = get_lrmw_long_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 32; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s32 dst = get_lrmw_long_mmu030_state (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu030_state (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS2.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0efc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 extra;
+	extra = get_ilong_mmu030_state (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u32 dst1 = get_lrmw_long_mmu030_state (rn1), dst2 = get_lrmw_long_mmu030_state (rn2);
+{uae_u32 newv = ((uae_u32)(dst1)) - ((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s32)(dst1)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u32)(dst2)) - ((uae_u32)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s32)(dst2)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, extra & 7))) > ((uae_u32)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	put_lrmw_long_mmu030_state (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	put_lrmw_long_mmu030_state (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = dst2;
+	m68k_dreg (regs, (extra >> 22) & 7) = dst1;
+	}
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1000_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1010_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1018_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1020_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1028_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1030_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1038_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1039_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1080_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1090_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1098_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10ba_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1100_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1110_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1118_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1120_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1128_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1130_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1138_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1139_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1140_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1150_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1158_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1160_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1168_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1170_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1178_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1179_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1180_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1190_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1198_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11ba_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (10);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2000_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2008_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2010_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2018_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2020_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2028_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2030_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2038_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2039_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2040_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2048_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2050_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2058_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2060_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2068_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2070_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	m68k_areg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2078_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2079_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	m68k_areg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_207c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2080_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2088_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2090_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2098_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20ba_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2100_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2108_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2110_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2118_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2120_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2128_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2130_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2138_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2139_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2140_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2148_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2150_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2158_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2160_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 26 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2168_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2170_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2178_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2179_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2180_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2188_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2190_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2198_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_3
+/* MOVE.L -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 26 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21ba_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 26 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 30 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 36; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (10);
+}}}}return 36 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+	m68k_incpci (10);
+}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3000_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3008_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3010_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3018_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3020_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3028_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3030_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3038_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3039_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3040_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3048_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3050_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3058_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3060_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3068_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3070_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3078_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3079_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_307c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3080_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3088_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3090_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3098_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30ba_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3100_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3108_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3110_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3118_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3120_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3128_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3130_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3138_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3139_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3140_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3148_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3150_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3158_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3160_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3168_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3170_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3178_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3179_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3180_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3188_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3190_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3198_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31ba_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (10);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (4);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+	m68k_incpci (8);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4000_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4010_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4018_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4020_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4028_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4030_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_mmu030_state (srca, newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4038_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4039_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4040_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4050_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4058_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4060_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4068_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4070_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_mmu030_state (srca, newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4078_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4079_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4080_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4090_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4098_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long_mmu030_state (srca, newv);
+}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40b8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40b9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long_mmu030_state (srca, newv);
+}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_40c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_320632; }
+{{	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}}	m68k_incpci (2);
+l_320632: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_320633; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	put_word_mmu030_state (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_320633: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_40d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_320634; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	put_word_mmu030_state (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_320634: ;
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_320635; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	put_word_mmu030_state (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_320635: ;
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_320636; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	MakeSR ();
+	put_word_mmu030_state (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_320636: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_320637; }
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	put_word_mmu030_state (srca, regs.sr);
+}}}}l_320637: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_320638; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	MakeSR ();
+	put_word_mmu030_state (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_320638: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_320639; }
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+	MakeSR ();
+	put_word_mmu030_state (srca, regs.sr);
+}}}	m68k_incpci (6);
+l_320639: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4100_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320640;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320640;
+	}
+}}}l_320640: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4110_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320641;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320641;
+	}
+}}}}l_320641: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (An)+,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4118_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320642;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320642;
+	}
+}}}}l_320642: ;
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L -(An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4120_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320643;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320643;
+	}
+}}}}l_320643: ;
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d16,An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4128_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320644;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320644;
+	}
+}}}}l_320644: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d8,An,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4130_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320645;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320645;
+	}
+}}}}}l_320645: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (xxx).W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4138_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320646;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320646;
+	}
+}}}}l_320646: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (xxx).L,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4139_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320647;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320647;
+	}
+}}}}l_320647: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d16,PC),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320648;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320648;
+	}
+}}}}l_320648: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d8,PC,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320649;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320649;
+	}
+}}}}}l_320649: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L #.L,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320650;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320650;
+	}
+}}}l_320650: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4180_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320651;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320651;
+	}
+}}}l_320651: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4190_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320652;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320652;
+	}
+}}}}l_320652: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4198_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320653;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320653;
+	}
+}}}}l_320653: ;
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320654;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320654;
+	}
+}}}}l_320654: ;
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320655;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320655;
+	}
+}}}}l_320655: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320656;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320656;
+	}
+}}}}}l_320656: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320657;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320657;
+	}
+}}}}l_320657: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320658;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320658;
+	}
+}}}}l_320658: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41ba_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320659;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320659;
+	}
+}}}}l_320659: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320660;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320660;
+	}
+}}}}}l_320660: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_320661;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_320661;
+	}
+}}}l_320661: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4200_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4210_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_mmu030_state (srca, 0);
+}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4218_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_mmu030_state (srca, 0);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4220_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_mmu030_state (srca, 0);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4228_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_mmu030_state (srca, 0);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4230_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_mmu030_state (srca, 0);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4238_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_mmu030_state (srca, 0);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4239_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_mmu030_state (srca, 0);
+}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4240_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4250_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_mmu030_state (srca, 0);
+}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4258_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_mmu030_state (srca, 0);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4260_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_mmu030_state (srca, 0);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4268_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_mmu030_state (srca, 0);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4270_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_mmu030_state (srca, 0);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4278_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_mmu030_state (srca, 0);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4279_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_mmu030_state (srca, 0);
+}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4280_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4290_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long_mmu030_state (srca, 0);
+}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4298_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long_mmu030_state (srca, 0);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long_mmu030_state (srca, 0);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long_mmu030_state (srca, 0);
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_42b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long_mmu030_state (srca, 0);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_42b8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long_mmu030_state (srca, 0);
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_42b9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long_mmu030_state (srca, 0);
+}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	put_word_mmu030_state (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	put_word_mmu030_state (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	put_word_mmu030_state (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	MakeSR ();
+	put_word_mmu030_state (srca, regs.sr & 0xff);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	put_word_mmu030_state (srca, regs.sr & 0xff);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	MakeSR ();
+	put_word_mmu030_state (srca, regs.sr & 0xff);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+	MakeSR ();
+	put_word_mmu030_state (srca, regs.sr & 0xff);
+}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* NEG.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4400_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_4
+/* NEG.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4410_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4418_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4420_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4428_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4430_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (srca, dst);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4438_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4439_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4440_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4450_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4458_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4460_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4468_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4470_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (srca, dst);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4478_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4479_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4480_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4490_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4498_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (srca, dst);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44b8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44b9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (srca, dst);
+}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_44c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_44d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B #.B */
+uae_u32 REGPARAM2 CPUFUNC(op_44fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4600_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4610_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte_mmu030_state (srca, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4618_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte_mmu030_state (srca, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4620_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte_mmu030_state (srca, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4628_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte_mmu030_state (srca, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4630_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte_mmu030_state (srca, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4638_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte_mmu030_state (srca, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4639_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_byte_mmu030_state (srca, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4640_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4650_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word_mmu030_state (srca, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4658_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word_mmu030_state (srca, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4660_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word_mmu030_state (srca, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4668_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word_mmu030_state (srca, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4670_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word_mmu030_state (srca, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4678_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word_mmu030_state (srca, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4679_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_word_mmu030_state (srca, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4680_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4690_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long_mmu030_state (srca, dst);
+}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4698_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long_mmu030_state (srca, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long_mmu030_state (srca, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long_mmu030_state (srca, dst);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long_mmu030_state (srca, dst);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46b8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long_mmu030_state (srca, dst);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46b9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_long_mmu030_state (srca, dst);
+}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_46c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_320760; }
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.sr = src;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+l_320760: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_320761; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (2);
+l_320761: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_46d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_320762; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (2);
+l_320762: ;
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_320763; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (2);
+l_320763: ;
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_320764; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (4);
+l_320764: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_320765; }
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}}l_320765: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_320766; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (4);
+l_320766: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_320767; }
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (6);
+l_320767: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_320768; }
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (4);
+l_320768: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_320769; }
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}}l_320769: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_46fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_320770; }
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	regs.sr = src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_320770: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4800_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LINK.L An,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4808_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 22; 
+{	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+{	uae_s32 offs;
+	offs = get_ilong_mmu030_state (2);
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	mmufixup[1].reg = 7;
+	mmufixup[1].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = (m68k_areg(regs, 7));
+	m68k_areg(regs, 7) += offs;
+	put_long_mmu030_state (olda, src);
+}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* NBCD.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4810_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_mmu030_state (srca, newv);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4818_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_mmu030_state (srca, newv);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4820_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_mmu030_state (srca, newv);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4828_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_mmu030_state (srca, newv);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4830_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_mmu030_state (srca, newv);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4838_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_mmu030_state (srca, newv);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4839_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_mmu030_state (srca, newv);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SWAP.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4840_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 34;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BKPTQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4848_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 99;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PEA.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4850_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	put_long_mmu030_state (dsta, srca);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4868_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	put_long_mmu030_state (dsta, srca);
+}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4870_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	put_long_mmu030_state (dsta, srca);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4878_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	put_long_mmu030_state (dsta, srca);
+}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4879_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	put_long_mmu030_state (dsta, srca);
+}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_487a_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	put_long_mmu030_state (dsta, srca);
+}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_487b_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	put_long_mmu030_state (dsta, srca);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EXT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4880_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u16 dst = (uae_s16)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4890_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_word_mmu030 (srca, (mmu030_data_buffer = m68k_dreg (regs, movem_index1[dmask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_word_mmu030 (srca, (mmu030_data_buffer = m68k_areg (regs, movem_index1[amask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 6;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	while (amask) {
+		srca -= 2;
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_word_mmu030 (srca, (mmu030_data_buffer = m68k_areg (regs, movem_index2[amask])));
+			}
+			mmu030_state[0]++;
+		}
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+	while (dmask) {
+		srca -= 2;
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_word_mmu030 (srca, (mmu030_data_buffer = m68k_dreg (regs, movem_index2[dmask])));
+			}
+			mmu030_state[0]++;
+		}
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_word_mmu030 (srca, (mmu030_data_buffer = m68k_dreg (regs, movem_index1[dmask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_word_mmu030 (srca, (mmu030_data_buffer = m68k_areg (regs, movem_index1[amask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48b0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_word_mmu030 (srca, (mmu030_data_buffer = m68k_dreg (regs, movem_index1[dmask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_word_mmu030 (srca, (mmu030_data_buffer = m68k_areg (regs, movem_index1[amask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48b8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_word_mmu030 (srca, (mmu030_data_buffer = m68k_dreg (regs, movem_index1[dmask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_word_mmu030 (srca, (mmu030_data_buffer = m68k_areg (regs, movem_index1[amask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48b9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+{	uaecptr srca;
+	srca = get_ilong_mmu030_state (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_word_mmu030 (srca, (mmu030_data_buffer = m68k_dreg (regs, movem_index1[dmask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_word_mmu030 (srca, (mmu030_data_buffer = m68k_areg (regs, movem_index1[amask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EXT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_48c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48d0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_long_mmu030 (srca, (mmu030_data_buffer = m68k_dreg (regs, movem_index1[dmask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_long_mmu030 (srca, (mmu030_data_buffer = m68k_areg (regs, movem_index1[amask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 10; 
+{	uae_u16 mask = get_iword_mmu030_state (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	while (amask) {
+		srca -= 4;
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_long_mmu030 (srca, (mmu030_data_buffer = m68k_areg (regs, movem_index2[amask])));
+			}
+			mmu030_state[0]++;
+		}
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+	while (dmask) {
+		srca -= 4;
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_long_mmu030 (srca, (mmu030_data_buffer = m68k_dreg (regs, movem_index2[dmask])));
+			}
+			mmu030_state[0]++;
+		}
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_long_mmu030 (srca, (mmu030_data_buffer = m68k_dreg (regs, movem_index1[dmask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_long_mmu030 (srca, (mmu030_data_buffer = m68k_areg (regs, movem_index1[amask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48f0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_long_mmu030 (srca, (mmu030_data_buffer = m68k_dreg (regs, movem_index1[dmask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_long_mmu030 (srca, (mmu030_data_buffer = m68k_areg (regs, movem_index1[amask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_long_mmu030 (srca, (mmu030_data_buffer = m68k_dreg (regs, movem_index1[dmask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_long_mmu030 (srca, (mmu030_data_buffer = m68k_areg (regs, movem_index1[amask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+{	uaecptr srca;
+	srca = get_ilong_mmu030_state (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_long_mmu030 (srca, (mmu030_data_buffer = m68k_dreg (regs, movem_index1[dmask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				put_long_mmu030 (srca, (mmu030_data_buffer = m68k_areg (regs, movem_index1[amask])));
+			}
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXT.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_49c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a00_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a10_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a18_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a20_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a28_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a30_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a38_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a39_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3a_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3b_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B #.B */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3c_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a40_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a48_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a50_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a58_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a60_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a68_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a70_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a78_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a79_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7a_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7b_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7c_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a80_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.L An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a88_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a90_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a98_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4aba_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4abb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4abc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TAS.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4ac0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((src) & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_lrmw_byte_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_lrmw_byte_mmu030_state (srca, src);
+}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_lrmw_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_lrmw_byte_mmu030_state (srca, src);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_lrmw_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_lrmw_byte_mmu030_state (srca, src);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_lrmw_byte_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_lrmw_byte_mmu030_state (srca, src);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4af0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_lrmw_byte_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_lrmw_byte_mmu030_state (srca, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4af8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_lrmw_byte_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_lrmw_byte_mmu030_state (srca, src);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4af9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_lrmw_byte_mmu030_state (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_lrmw_byte_mmu030_state (srca, src);
+}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MULL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c00_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_320847;
+}}}l_320847: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c10_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_320848;
+}}}}l_320848: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c18_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_320849;
+}}}}l_320849: ;
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c20_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_320850;
+}}}}l_320850: ;
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c28_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_320851;
+}}}}l_320851: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c30_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_320852;
+}}}}}l_320852: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c38_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_320853;
+}}}}l_320853: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c39_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_320854;
+}}}}l_320854: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_320855;
+}}}}l_320855: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_320856;
+}}}}}l_320856: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3c_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uae_s32 dst;
+	dst = get_ilong_mmu030_state (4);
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_320857;
+}}}l_320857: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c40_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_320858;
+}}}l_320858: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c50_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_320859;
+}}}}l_320859: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c58_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_320860;
+}}}}l_320860: ;
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c60_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_320861;
+}}}}l_320861: ;
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c68_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_320862;
+}}}}l_320862: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c70_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_320863;
+}}}}}l_320863: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c78_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_320864;
+}}}}l_320864: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c79_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_320865;
+}}}}l_320865: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_320866;
+}}}}l_320866: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_320867;
+}}}}}l_320867: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7c_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uae_s32 dst;
+	dst = get_ilong_mmu030_state (4);
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_320868;
+}}}l_320868: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVMEL.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4c90_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4c98_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ca8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_ilong_mmu030_state (4);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cba_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cbb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = (uae_s32)(uae_s16)mmu030_data_buffer;
+			} else {
+				val = (uae_s32)(uae_s16)get_word_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 2;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ce8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_ilong_mmu030_state (4);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu030_state (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+	int movem_cnt = 0;
+	uae_u32 val;
+	if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+		srca = mmu030_ad[mmu030_idx].val;
+	else
+		mmu030_ad[mmu030_idx].val = srca;
+	while (dmask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_dreg (regs, movem_index1[dmask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		if (mmu030_state[0] == movem_cnt) {
+			if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+				mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+				val = mmu030_data_buffer;
+			} else {
+				val = get_long_mmu030 (srca);
+			}
+			m68k_areg (regs, movem_index1[amask]) = val;
+			mmu030_state[0]++;
+		}
+		srca += 4;
+		movem_cnt++;
+		amask = movem_next[amask];
+	}
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* TRAPQ.L # */
+uae_u32 REGPARAM2 CPUFUNC(op_4e40_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 15);
+	OpcodeFamily = 39;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+	m68k_incpci (2);
+	Exception (src + 32);
+}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* LINK.W An,#.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e50_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 18; 
+{	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	mmufixup[1].reg = 7;
+	mmufixup[1].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = (m68k_areg(regs, 7));
+	m68k_areg(regs, 7) += offs;
+	put_long_mmu030_state (olda, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* UNLK.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e58_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 48;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	uae_s32 old = get_long_mmu030_state (src);
+	m68k_areg (regs, 7) = src + 4;
+	m68k_areg (regs, srcreg) = old;
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVR2USP.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e60_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 40;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_320888; }
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	regs.usp = src;
+}}}	m68k_incpci (2);
+l_320888: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVUSP2R.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e68_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 41;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_320889; }
+{{	m68k_areg (regs, srcreg) = (regs.usp);
+}}}	m68k_incpci (2);
+l_320889: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RESET.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e70_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 42;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_320890; }
+{	cpureset ();
+	m68k_incpci (2);
+}}l_320890: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOP.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e71_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 43;
+	CurrentInstrCycles = 4;  
+{}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* STOP.L #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e72_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 44;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_320892; }
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_setstopped ();
+	m68k_incpci (4);
+}}}l_320892: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RTE.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e73_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 45;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_320893; }
+{	uae_u16 newsr; uae_u32 newpc;
+	for (;;) {
+		uaecptr a = m68k_areg (regs, 7);
+		uae_u16 sr = get_word_mmu030_state (a);
+		uae_u32 pc = get_long_mmu030_state (a + 2);
+		uae_u16 format = get_word_mmu030_state (a + 2 + 4);
+		int frame = format >> 12;
+		int offset = 8;
+		newsr = sr; newpc = pc;
+		if (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }
+		else if (frame == 0x1) { m68k_areg (regs, 7) += offset; }
+		else if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }
+		else if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }
+		else if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }
+		else if (frame == 0x7) { m68k_areg (regs, 7) += offset + 52; break; }
+		else if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }
+		else if (frame == 0xa) { m68k_do_rte_mmu030 (a); break; }
+		else if (frame == 0xb) { m68k_do_rte_mmu030 (a); break; }
+		else { m68k_areg (regs, 7) += offset; Exception (14); goto l_320893; }
+		regs.sr = newsr;
+	MakeFromSR();
+}
+	regs.sr = newsr;
+	MakeFromSR();
+	if (newpc & 1) {
+		exception3i (0x4E73, newpc);
+		goto l_320893;
+	}
+	m68k_setpci (newpc);
+}}l_320893: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RTD.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e74_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 46;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 offs = get_iword_mmu030_state (2);
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = get_long_mmu030_state (pca);
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) += 4;
+	m68k_areg(regs, 7) += offs;
+	if (pc & 1) {
+		exception3i (0x4E74, pc);
+		goto l_320894;
+	}
+	m68k_setpci (pc);
+}}}}l_320894: ;
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* RTS.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e75_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 49;
+	CurrentInstrCycles = 8;  
+{	uaecptr pc = m68k_getpci ();
+	m68k_do_rts_mmu030 ();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (pc);
+		exception3i (0x4E75, faultpc);
+		goto l_320895;
+	}
+}l_320895: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TRAPV.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e76_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 50;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	if (GET_VFLG ()) {
+		Exception (7);
+		goto l_320896;
+	}
+}l_320896: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RTR.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e77_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 51;
+	CurrentInstrCycles = 16; 
+{	uaecptr oldpc = m68k_getpci ();
+	MakeSR ();
+{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+{	uae_s16 sr = get_word_mmu030_state (sra);
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = get_long_mmu030_state (pca);
+	mmufixup[1].reg = 7;
+	mmufixup[1].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) += 4;
+	regs.sr &= 0xFF00; sr &= 0xFF;
+	regs.sr |= sr;
+	m68k_setpci (pc);
+	MakeFromSR();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (oldpc);
+		exception3i (0x4E77, faultpc);
+		goto l_320897;
+	}
+}}}}}l_320897: ;
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEC2.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7a_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 82;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_320898; }
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_movec2(src & 0xFFF, regp)) goto l_320898;
+}}}}	m68k_incpci (4);
+l_320898: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE2C.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7b_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 83;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_320899; }
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_move2c(src & 0xFFF, regp)) goto l_320899;
+}}}}	m68k_incpci (4);
+l_320899: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* JSR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4e90_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr oldpc = m68k_getpci () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_320900;
+	}
+	put_long_mmu030_state (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_320900: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ea8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_320901;
+	}
+	put_long_mmu030_state (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_320901: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_320902;
+	}
+	put_long_mmu030_state (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}}l_320902: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_320903;
+	}
+	put_long_mmu030_state (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_320903: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uaecptr oldpc = m68k_getpci () + 6;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_320904;
+	}
+	put_long_mmu030_state (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_320904: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eba_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_320905;
+	}
+	put_long_mmu030_state (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_320905: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ebb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_320906;
+	}
+	put_long_mmu030_state (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}}l_320906: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ed0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_320907;
+	}
+	m68k_setpci (srca);
+}}l_320907: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ee8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_320908;
+	}
+	m68k_setpci (srca);
+}}l_320908: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_320909;
+	}
+	m68k_setpci (srca);
+}}}l_320909: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_320910;
+	}
+	m68k_setpci (srca);
+}}l_320910: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_320911;
+	}
+	m68k_setpci (srca);
+}}l_320911: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_320912;
+	}
+	m68k_setpci (srca);
+}}l_320912: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_320913;
+	}
+	m68k_setpci (srca);
+}}}l_320913: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5000_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5010_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5018_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5020_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5028_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5030_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5038_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5039_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5040_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5048_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5050_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5058_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5060_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5068_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5070_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5078_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5079_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5080_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5088_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5090_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5098_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_5
+/* ADDQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_50b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_50b8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_50b9_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (0) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (0)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_320941;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_320941: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (0)) { Exception (7); goto l_320949; }
+}}	m68k_incpci (4);
+l_320949: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (0)) { Exception (7); goto l_320950; }
+}}	m68k_incpci (6);
+l_320950: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (0)) { Exception (7); goto l_320951; }
+}	m68k_incpci (2);
+l_320951: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* SUBQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5100_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5110_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5118_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5120_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5128_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5130_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5138_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5139_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5140_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5148_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5150_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5158_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5160_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5168_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5170_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5178_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5179_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5180_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5188_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5190_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5198_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_51b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_51b8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_51b9_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (1) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (1)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_320979;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_320979: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (1)) { Exception (7); goto l_320987; }
+}}	m68k_incpci (4);
+l_320987: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (1)) { Exception (7); goto l_320988; }
+}}	m68k_incpci (6);
+l_320988: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (1)) { Exception (7); goto l_320989; }
+}	m68k_incpci (2);
+l_320989: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (2) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (2)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_320991;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_320991: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (2)) { Exception (7); goto l_320999; }
+}}	m68k_incpci (4);
+l_320999: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (2)) { Exception (7); goto l_321000; }
+}}	m68k_incpci (6);
+l_321000: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (2)) { Exception (7); goto l_321001; }
+}	m68k_incpci (2);
+l_321001: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (3) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (3)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_321003;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_321003: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (3)) { Exception (7); goto l_321011; }
+}}	m68k_incpci (4);
+l_321011: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (3)) { Exception (7); goto l_321012; }
+}}	m68k_incpci (6);
+l_321012: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (3)) { Exception (7); goto l_321013; }
+}	m68k_incpci (2);
+l_321013: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (4) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (4)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_321015;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_321015: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (4)) { Exception (7); goto l_321023; }
+}}	m68k_incpci (4);
+l_321023: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (4)) { Exception (7); goto l_321024; }
+}}	m68k_incpci (6);
+l_321024: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (4)) { Exception (7); goto l_321025; }
+}	m68k_incpci (2);
+l_321025: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (5) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (5)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_321027;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_321027: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (5)) { Exception (7); goto l_321035; }
+}}	m68k_incpci (4);
+l_321035: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (5)) { Exception (7); goto l_321036; }
+}}	m68k_incpci (6);
+l_321036: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (5)) { Exception (7); goto l_321037; }
+}	m68k_incpci (2);
+l_321037: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (6) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (6)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_321039;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_321039: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (6)) { Exception (7); goto l_321047; }
+}}	m68k_incpci (4);
+l_321047: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (6)) { Exception (7); goto l_321048; }
+}}	m68k_incpci (6);
+l_321048: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (6)) { Exception (7); goto l_321049; }
+}	m68k_incpci (2);
+l_321049: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (7) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (7)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_321051;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_321051: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (7)) { Exception (7); goto l_321059; }
+}}	m68k_incpci (4);
+l_321059: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (7)) { Exception (7); goto l_321060; }
+}}	m68k_incpci (6);
+l_321060: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (7)) { Exception (7); goto l_321061; }
+}	m68k_incpci (2);
+l_321061: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (8) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (8)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_321063;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_321063: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (8)) { Exception (7); goto l_321071; }
+}}	m68k_incpci (4);
+l_321071: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (8)) { Exception (7); goto l_321072; }
+}}	m68k_incpci (6);
+l_321072: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (8)) { Exception (7); goto l_321073; }
+}	m68k_incpci (2);
+l_321073: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (9) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (9)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_321075;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_321075: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (9)) { Exception (7); goto l_321083; }
+}}	m68k_incpci (4);
+l_321083: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (9)) { Exception (7); goto l_321084; }
+}}	m68k_incpci (6);
+l_321084: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (9)) { Exception (7); goto l_321085; }
+}	m68k_incpci (2);
+l_321085: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (10) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (10)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_321087;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_321087: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (10)) { Exception (7); goto l_321095; }
+}}	m68k_incpci (4);
+l_321095: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (10)) { Exception (7); goto l_321096; }
+}}	m68k_incpci (6);
+l_321096: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (10)) { Exception (7); goto l_321097; }
+}	m68k_incpci (2);
+l_321097: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (11) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (11)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_321099;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_321099: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (11)) { Exception (7); goto l_321107; }
+}}	m68k_incpci (4);
+l_321107: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (11)) { Exception (7); goto l_321108; }
+}}	m68k_incpci (6);
+l_321108: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (11)) { Exception (7); goto l_321109; }
+}	m68k_incpci (2);
+l_321109: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (12) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (12)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_321111;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_321111: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (12)) { Exception (7); goto l_321119; }
+}}	m68k_incpci (4);
+l_321119: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (12)) { Exception (7); goto l_321120; }
+}}	m68k_incpci (6);
+l_321120: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (12)) { Exception (7); goto l_321121; }
+}	m68k_incpci (2);
+l_321121: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (13) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (13)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_321123;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_321123: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (13)) { Exception (7); goto l_321131; }
+}}	m68k_incpci (4);
+l_321131: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (13)) { Exception (7); goto l_321132; }
+}}	m68k_incpci (6);
+l_321132: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (13)) { Exception (7); goto l_321133; }
+}	m68k_incpci (2);
+l_321133: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (14) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (14)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_321135;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_321135: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (14)) { Exception (7); goto l_321143; }
+}}	m68k_incpci (4);
+l_321143: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (14)) { Exception (7); goto l_321144; }
+}}	m68k_incpci (6);
+l_321144: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (14)) { Exception (7); goto l_321145; }
+}	m68k_incpci (2);
+l_321145: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (15) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu030_state (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (15)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_321147;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_321147: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_mmu030_state (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffa_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu030_state (2);
+	if (cctrue (15)) { Exception (7); goto l_321155; }
+}}	m68k_incpci (4);
+l_321155: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffb_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (2);
+	if (cctrue (15)) { Exception (7); goto l_321156; }
+}}	m68k_incpci (6);
+l_321156: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffc_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (15)) { Exception (7); goto l_321157; }
+}	m68k_incpci (2);
+l_321157: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Bcc.W #.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6000_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321158;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321158: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6001_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321159;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321159: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_60ff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321160;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321160: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_6100_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_s16 src = get_iword_mmu030_state (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_321161;
+	}
+	m68k_do_bsr_mmu030 (m68k_getpci () + 4, s);
+}}l_321161: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSRQ.B # */
+uae_u32 REGPARAM2 CPUFUNC(op_6101_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_u32 src = srcreg;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_321162;
+	}
+	m68k_do_bsr_mmu030 (m68k_getpci () + 2, s);
+}}l_321162: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSR.L #.L */
+uae_u32 REGPARAM2 CPUFUNC(op_61ff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_321163;
+	}
+	m68k_do_bsr_mmu030 (m68k_getpci () + 6, s);
+}}l_321163: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6200_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321164;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321164: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6201_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321165;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321165: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_62ff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321166;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321166: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6300_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321167;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321167: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6301_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321168;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321168: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_6
+/* Bcc.L #.L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_63ff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321169;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321169: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6400_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321170;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321170: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6401_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321171;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321171: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_64ff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321172;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321172: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6500_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321173;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321173: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6501_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321174;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321174: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_65ff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321175;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321175: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6600_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321176;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321176: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6601_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321177;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321177: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_66ff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321178;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321178: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6700_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321179;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321179: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6701_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321180;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321180: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_67ff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321181;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321181: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6800_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321182;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321182: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6801_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321183;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321183: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_68ff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321184;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321184: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6900_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321185;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321185: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6901_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321186;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321186: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_69ff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321187;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321187: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a00_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321188;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321188: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a01_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321189;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321189: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6aff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321190;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321190: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b00_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321191;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321191: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b01_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321192;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321192: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6bff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321193;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321193: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c00_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321194;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321194: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c01_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321195;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321195: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6cff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321196;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321196: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d00_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321197;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321197: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d01_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321198;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321198: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6dff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321199;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321199: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e00_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321200;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321200: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e01_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321201;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321201: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6eff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321202;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321202: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f00_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321203;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_321203: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f01_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321204;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_321204: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6fff_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_321205;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_321205: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_7000_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8000_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8010_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8018_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8020_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8028_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8030_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8038_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8039_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8040_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8050_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8058_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8060_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8068_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8070_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8078_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8079_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8080_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8090_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8098_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80ba_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 110;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_321240;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}l_321240: ;
+return 110 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 114;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_321241;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}l_321241: ;
+return 114 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 114;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_321242;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}l_321242: ;
+	mmufixup[0].reg = -1;
+return 114 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 116;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_321243;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}l_321243: ;
+	mmufixup[0].reg = -1;
+return 116 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_321244;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}l_321244: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_321245;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_321245: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_321246;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}l_321246: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 122;
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_321247;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (6);
+	}
+}}}}l_321247: ;
+return 122 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_321248;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}l_321248: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_321249;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_321249: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 114;
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_321250;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}l_321250: ;
+return 114 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8100_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8108_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8110_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8118_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8120_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8128_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8130_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8138_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8139_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* PACK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8140_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val = m68k_dreg (regs, srcreg) + get_iword_mmu030_state (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PACK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8148_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(get_byte_mmu030_state (m68k_areg (regs, srcreg)) & 0xff);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (val | ((uae_u16)(get_byte_mmu030_state (m68k_areg (regs, srcreg)) & 0xff) << 8)) + get_iword_mmu030_state (2);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) -= areg_byteinc[dstreg];
+	put_byte_mmu030_state (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));
+}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* OR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8150_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8158_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8160_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8168_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8170_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8178_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8179_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* UNPK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8180_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val = m68k_dreg (regs, srcreg);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_iword_mmu030_state (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* UNPK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8188_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(get_byte_mmu030_state (m68k_areg (regs, srcreg)) & 0xff);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_iword_mmu030_state (2);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];
+	put_byte_mmu030_state (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);
+	put_byte_mmu030_state (m68k_areg (regs, dstreg), val >> 8);
+}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* OR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8190_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8198_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_81b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_81b8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_81b9_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 142;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_321278;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}l_321278: ;
+return 142 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 146;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_321279;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}l_321279: ;
+return 146 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 146;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_321280;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}l_321280: ;
+	mmufixup[0].reg = -1;
+return 146 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 148;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_321281;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}l_321281: ;
+	mmufixup[0].reg = -1;
+return 148 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_321282;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}l_321282: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_321283;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_321283: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_321284;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}l_321284: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 154;
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_321285;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (6);
+}}}}l_321285: ;
+return 154 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_321286;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}l_321286: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_321287;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_321287: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 146;
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_321288;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}l_321288: ;
+return 146 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9000_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9010_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9018_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9020_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9028_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9030_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9038_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9039_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9040_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9048_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9050_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9058_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9060_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9068_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9070_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9078_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9079_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9080_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9088_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9090_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9098_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90ba_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9100_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9108_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9110_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9118_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9120_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9128_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9130_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9138_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9139_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9140_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9148_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9150_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9158_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9160_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9168_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9170_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9178_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9179_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9180_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9188_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9190_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9198_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_91b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_91b8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_91b9_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b000_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b010_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b018_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b020_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b028_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b030_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b038_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b039_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b040_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b048_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b050_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b058_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b060_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b068_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b070_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b078_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b079_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b080_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b088_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b090_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b098_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_7
+/* CMP.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0ba_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b100_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b108_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b110_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b118_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b120_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b128_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b130_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b138_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b139_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b140_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b148_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b150_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b158_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b160_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b168_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b170_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b178_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b179_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b180_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b188_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b190_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b198_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b9_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c000_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c010_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c018_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c020_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c028_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c030_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c038_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c039_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c040_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c050_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c058_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c060_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c068_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c070_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c078_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c079_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c080_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c090_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c098_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0ba_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 58; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}return 58 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 62; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return 62 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 62; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}	mmufixup[0].reg = -1;
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 64; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}	mmufixup[0].reg = -1;
+return 64 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 70; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (6);
+}}}}}return 70 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 62; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}return 62 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c100_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c108_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c110_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c118_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c120_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c128_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c130_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c138_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c139_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c140_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c148_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	m68k_areg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c150_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c158_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c160_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c168_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c170_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c178_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c179_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c188_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c190_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c198_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b9_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu030_state (dsta, src);
+}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 58; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 58 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 62; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 62; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 64; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 64 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 70; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 70 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 62; 
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d000_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d010_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d018_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d020_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d028_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d030_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d038_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d039_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu030_state (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu030_state (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d040_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d048_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d050_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d058_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d060_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d068_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d070_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d078_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d079_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07c_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d080_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d088_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d090_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d098_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0ba_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s16 src = get_word_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu030_state (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d100_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d108_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d110_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d118_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d120_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d128_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d130_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d138_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d139_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s8 dst = get_byte_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_byte_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d140_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d148_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d150_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d158_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d160_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d168_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d170_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d178_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d179_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s16 dst = get_word_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_word_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d180_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d188_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d190_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d198_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b9_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (2);
+{	uae_s32 dst = get_long_mmu030_state (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_long_mmu030_state (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu030_state (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f9_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_s32 src = get_long_mmu030_state (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fc_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu030_state (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e000_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e008_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e010_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e018_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e020_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e028_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e030_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e038_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e040_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_8
+/* LSRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e048_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e050_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e058_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e060_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e068_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e070_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e078_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e080_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e088_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e090_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e098_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e100_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e108_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e110_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e118_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e120_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e128_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e130_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e138_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e140_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e148_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e150_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e158_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e160_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e168_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e170_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e178_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e180_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e188_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e190_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e198_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word_mmu030_state (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word_mmu030_state (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_word_mmu030_state (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e8_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word_mmu030_state (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu030_state (2);
+{	uae_s16 data = get_word_mmu030_state (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_word_mmu030_state (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BFTST.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8c0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8d0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8e8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9c0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9d0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9e8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9fa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9fb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eac0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ead0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eae8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebc0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebd0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebe8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebfa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebfb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecc0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecd0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ece8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edc0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edd0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ede8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edfa_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edfb_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = get_disp_ea_020_mmu030 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eec0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eed0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eee8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efc0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efd0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efe8_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff0_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = get_disp_ea_020_mmu030 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff8_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff9_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu030_state (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu030_state (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L Dn,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f000_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321788; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	uae_u16 extraa = 0;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}l_321788: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L An,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f008_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321789; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	uae_u16 extraa = 0;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}l_321789: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f010_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321790; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_321790: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (An)+,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f018_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321791; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_321791: ;
+	mmufixup[0].reg = -1;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L -(An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f020_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 6;  
+{if (!regs.s) { Exception (8); goto l_321792; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) - 4;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = extraa;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_321792: ;
+	mmufixup[0].reg = -1;
+return 6 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (d16,An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f028_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_321793; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu030_state (0);
+	m68k_incpci (2);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_321793: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (d8,An,Xn),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f030_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_321794; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+{	extraa = get_disp_ea_020_mmu030 (m68k_areg (regs, srcreg), 0);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}}l_321794: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (xxx).W,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f038_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_321795; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = (uae_s32)(uae_s16)get_iword_mmu030_state (0);
+	m68k_incpci (2);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_321795: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (xxx).L,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f039_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_321796; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = get_ilong_mmu030_state (0);
+	m68k_incpci (4);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_321796: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f200_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f208_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f210_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f218_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f220_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f228_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f230_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f238_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f239_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23a_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23b_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23c_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f240_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FDBcc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f248_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 105;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_dbcc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f250_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f258_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f260_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f268_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f270_32)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f278_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f279_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27a_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 12; 
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu030_state (2);
+{	uae_s16 dummy = get_iword_mmu030_state (4);
+	m68k_incpci (6);
+	fpuop_trapcc (opcode, oldpc, extra);
+}
+#endif
+}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27b_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 16; 
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu030_state (2);
+{	uae_s32 dummy;
+	dummy = get_ilong_mmu030_state (4);
+	m68k_incpci (8);
+	fpuop_trapcc (opcode, oldpc, extra);
+}
+#endif
+}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L  */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27c_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu030_state (2);
+	m68k_incpci (4);
+	fpuop_trapcc (opcode, oldpc, extra);
+
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FBccQ.L #,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f280_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s16 extra = get_iword_mmu030_state (0);
+	m68k_incpci (2);
+	fpuop_bcc (opcode, pc,extra);
+}}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FBccQ.L #,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f2c0_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+	CurrentInstrCycles = 12; 
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s32 extra;
+	extra = get_ilong_mmu030_state (0);
+	m68k_incpci (4);
+	fpuop_bcc (opcode, pc,extra);
+}}
+#endif
+}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f310_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321823; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_321823: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f320_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321824; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_321824: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f328_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321825; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_321825: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f330_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321826; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_321826: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f338_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321827; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_321827: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f339_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321828; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_321828: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f350_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321829; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_321829: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f358_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321830; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_321830: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f368_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321831; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_321831: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f370_32)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321832; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_321832: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f378_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321833; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_321833: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f379_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321834; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_321834: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f37a_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321835; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_321835: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f37b_32)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_321836; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_321836: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
diff --git a/src/cpu/cpuemu_33.c b/src/cpu/cpuemu_33.c
new file mode 100644
index 0000000..94cbc30
--- /dev/null
+++ b/src/cpu/cpuemu_33.c
@@ -0,0 +1,39922 @@
+#include "main.h"
+#include "sysdeps.h"
+#include "hatari-glue.h"
+#include "maccess.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "cputbl.h"
+#include "cpummu.h"
+#define CPUFUNC(x) x##_ff
+#define SET_CFLG_ALWAYS(x) SET_CFLG(x)
+#define SET_NFLG_ALWAYS(x) SET_NFLG(x)
+#ifdef NOFLAGS
+#include "noflags.h"
+#endif
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0000_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0010_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0018_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0020_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0028_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0030_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0038_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0039_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (8);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* ORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_003c_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu060 (2);
+	src &= 0xFF;
+	regs.sr |= src;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0040_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0050_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0058_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0060_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0068_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0070_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0078_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0079_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_007c_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_330018; }
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu060 (2);
+	regs.sr |= src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_330018: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0080_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0090_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0098_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 30 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_00b0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_00b8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_00b9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (10);
+return 36 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00d0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu060 (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu060 (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330027; }
+}
+}}}	m68k_incpci (4);
+l_330027: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00e8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu060 (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu060 (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330028; }
+}
+}}}	m68k_incpci (6);
+l_330028: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu060 (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu060 (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330029; }
+}
+}}}}l_330029: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu060 (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu060 (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330030; }
+}
+}}}	m68k_incpci (6);
+l_330030: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu060 (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu060 (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330031; }
+}
+}}}	m68k_incpci (8);
+l_330031: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu060 (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu060 (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330032; }
+}
+}}}	m68k_incpci (6);
+l_330032: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)get_byte_mmu060 (dsta); upper = (uae_s32)(uae_s8)get_byte_mmu060 (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330033; }
+}
+}}}}l_330033: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BTST.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0100_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPMR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0108_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 8;  
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_u16 val;
+	MovepByteNbr=1; val = ((get_byte_mmu060 (memp) & 0xff) << 8);
+	MovepByteNbr=2; val += (get_byte_mmu060 (memp + 2) & 0xff);
+	MovepByteNbr=0;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0110_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0118_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0120_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0128_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0130_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0138_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0139_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_013a_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 2;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_013b_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,#.B */
+uae_u32 REGPARAM2 CPUFUNC(op_013c_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = get_ibyte_mmu060 (2);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0140_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPMR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0148_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 16; 
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_u32 val;
+	MovepByteNbr=1; val = ((get_byte_mmu060 (memp) & 0xff) << 24);
+	MovepByteNbr=2; val += ((get_byte_mmu060 (memp + 2) & 0xff) << 16);
+	MovepByteNbr=3; val += ((get_byte_mmu060 (memp + 4) & 0xff) << 8);
+	MovepByteNbr=4; val += (get_byte_mmu060 (memp + 6) & 0xff);
+	MovepByteNbr=0;
+	m68k_dreg (regs, dstreg) = (val);
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0150_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0158_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0160_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0168_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0170_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0178_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0179_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0180_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPRM.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0188_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	MovepByteNbr=1; 	put_byte_mmu060 (memp, src >> 8);
+	MovepByteNbr=2; 	put_byte_mmu060 (memp + 2, src);
+	MovepByteNbr=0;
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0190_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0198_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01b8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01b9_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BSET.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_01c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPRM.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	MovepByteNbr=1; 	put_byte_mmu060 (memp, src >> 24);
+	MovepByteNbr=2; 	put_byte_mmu060 (memp + 2, src >> 16);
+	MovepByteNbr=3; 	put_byte_mmu060 (memp + 4, src >> 8);
+	MovepByteNbr=4; 	put_byte_mmu060 (memp + 6, src);
+	MovepByteNbr=0;
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_01d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01f8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01f9_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0200_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0210_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0218_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0220_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0228_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0230_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0238_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0239_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (8);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* ANDSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_023c_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu060 (2);
+	src |= 0xFF00;
+	regs.sr &= src;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0240_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0250_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0258_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0260_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0268_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0270_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0278_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0279_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ANDSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_027c_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_330090; }
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu060 (2);
+	regs.sr &= src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_330090: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0280_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0290_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0298_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 30 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_02b0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_02b8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_02b9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (10);
+return 36 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02d0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu060 (dsta); upper = (uae_s32)(uae_s16)get_word_mmu060 (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330099; }
+}
+}}}	m68k_incpci (4);
+l_330099: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02e8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu060 (dsta); upper = (uae_s32)(uae_s16)get_word_mmu060 (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330100; }
+}
+}}}	m68k_incpci (6);
+l_330100: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu060 (dsta); upper = (uae_s32)(uae_s16)get_word_mmu060 (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330101; }
+}
+}}}}l_330101: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu060 (dsta); upper = (uae_s32)(uae_s16)get_word_mmu060 (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330102; }
+}
+}}}	m68k_incpci (6);
+l_330102: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu060 (dsta); upper = (uae_s32)(uae_s16)get_word_mmu060 (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330103; }
+}
+}}}	m68k_incpci (8);
+l_330103: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu060 (dsta); upper = (uae_s32)(uae_s16)get_word_mmu060 (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330104; }
+}
+}}}	m68k_incpci (6);
+l_330104: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)get_word_mmu060 (dsta); upper = (uae_s32)(uae_s16)get_word_mmu060 (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330105; }
+}
+}}}}l_330105: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0400_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0410_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0418_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0420_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0428_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0430_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0438_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0439_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0440_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0450_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0458_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0460_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0468_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0470_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0478_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0479_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0480_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0490_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0498_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 30 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_04b0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_04b8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_04b9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (10);
+return 36 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04d0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu060 (dsta); upper = get_long_mmu060 (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330130; }
+}
+}}}	m68k_incpci (4);
+l_330130: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04e8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu060 (dsta); upper = get_long_mmu060 (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330131; }
+}
+}}}	m68k_incpci (6);
+l_330131: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu060 (dsta); upper = get_long_mmu060 (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330132; }
+}
+}}}}l_330132: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu060 (dsta); upper = get_long_mmu060 (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330133; }
+}
+}}}	m68k_incpci (6);
+l_330133: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu060 (dsta); upper = get_long_mmu060 (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330134; }
+}
+}}}	m68k_incpci (8);
+l_330134: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu060 (dsta); upper = get_long_mmu060 (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330135; }
+}
+}}}	m68k_incpci (6);
+l_330135: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = get_long_mmu060 (dsta); upper = get_long_mmu060 (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_330136; }
+}
+}}}}l_330136: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0600_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0610_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0618_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0620_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0628_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0630_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0638_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0639_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0640_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0650_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0658_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0660_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0668_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0670_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0678_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0679_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0680_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0690_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0698_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 30 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_06b0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_06b8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_06b9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (10);
+return 36 * CYCLE_UNIT / 2;
+}
+
+/* RTM.L Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* RTM.L An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BTST.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0800_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0810_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0818_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0820_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0828_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0830_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0838_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0839_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (8);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_083a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_083b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0840_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0850_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0858_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0860_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0868_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0870_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0878_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0879_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0880_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0890_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0898_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08b0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08b8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08b9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* BSET.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_08c0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08d0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_08d8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08f0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	put_rmw_byte_mmu060 (dsta, dst);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a00_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a10_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a18_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a20_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 22; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a28_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a30_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a38_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a39_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (8);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* EORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a3c_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu060 (2);
+	src &= 0xFF;
+	regs.sr ^= src;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a40_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a50_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a58_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a60_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a68_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a70_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a78_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a79_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* EORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a7c_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_330221; }
+{	MakeSR ();
+{	uae_s16 src = get_iword_mmu060 (2);
+	regs.sr ^= src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_330221: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a80_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a90_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a98_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 30; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 30 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 32; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (8);
+return 32 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 36; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (6);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (10);
+return 36 * CYCLE_UNIT / 2;
+}
+
+/* CAS.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ad0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_lrmw_byte_mmu060 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_byte_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ad8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_lrmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_byte_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ae0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_lrmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_byte_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ae8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_lrmw_byte_mmu060 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_byte_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
+#ifdef PART_2
+/* CAS.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_lrmw_byte_mmu060 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_byte_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_lrmw_byte_mmu060 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_byte_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (6);
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 28; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s8 dst = get_lrmw_byte_mmu060 (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_byte_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_byte_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpci (8);
+return 28 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c00_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c10_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c18_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c20_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 18; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c28_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c30_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c38_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c39_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c3a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.B #.B,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c3b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c40_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c50_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c58_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c60_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c68_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c70_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c78_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c79_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s16 dst = get_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c7a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c7b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 dst = get_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c80_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c90_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c98_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (6);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (6);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (6);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (10);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cba_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 6;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu060 (6);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (8);
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.L #.L,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cbb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (6);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cd0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_lrmw_word_mmu060 (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (4);
+		op_unimpl (opcode);
+		goto l_330267;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_word_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_330267: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cd8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_lrmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) -= 2;
+	m68k_incpci (4);
+		op_unimpl (opcode);
+		goto l_330268;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_word_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_330268: ;
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ce0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 22; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_lrmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) += 2;
+	m68k_incpci (4);
+		op_unimpl (opcode);
+		goto l_330269;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_word_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (4);
+l_330269: ;
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ce8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_lrmw_word_mmu060 (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (6);
+		op_unimpl (opcode);
+		goto l_330270;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_word_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+l_330270: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_lrmw_word_mmu060 (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		op_unimpl (opcode);
+		goto l_330271;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_word_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}}l_330271: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 dst = get_lrmw_word_mmu060 (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (6);
+		op_unimpl (opcode);
+		goto l_330272;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_word_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (6);
+l_330272: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 28; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s16 dst = get_lrmw_word_mmu060 (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (8);
+		op_unimpl (opcode);
+		goto l_330273;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_word_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_word_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpci (8);
+l_330273: ;
+return 28 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS2.W #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cfc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 extra;
+	extra = get_ilong_mmu060 (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u16 dst1 = get_lrmw_word_mmu060 (rn1), dst2 = get_lrmw_word_mmu060 (rn2);
+{uae_u32 newv = ((uae_u16)(dst1)) - ((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s16)(dst1)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u16)(dst2)) - ((uae_u16)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s16)(dst2)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, extra & 7))) > ((uae_u16)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	put_lrmw_word_mmu060 (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	put_lrmw_word_mmu060 (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);
+	m68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);
+	}
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e10_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_330275; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	dfc060_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = sfc060_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (4);
+l_330275: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e18_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_330276; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	dfc060_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = sfc060_get_byte (srca);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (4);
+l_330276: ;
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e20_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_330277; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	dfc060_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 src = sfc060_get_byte (srca);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (4);
+l_330277: ;
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e28_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_330278; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	dfc060_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 src = sfc060_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (6);
+l_330278: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e30_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_330279; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	dfc060_put_byte (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s8 src = sfc060_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}}l_330279: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e38_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_330280; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	dfc060_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s8 src = sfc060_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (6);
+l_330280: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e39_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_330281; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	dfc060_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_ilong_mmu060 (4);
+{	uae_s8 src = sfc060_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpci (8);
+l_330281: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e50_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_330282; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	dfc060_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = sfc060_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (4);
+l_330282: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e58_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_330283; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	dfc060_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = sfc060_get_word (srca);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (4);
+l_330283: ;
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e60_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_330284; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	dfc060_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 src = sfc060_get_word (srca);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (4);
+l_330284: ;
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e68_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_330285; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	dfc060_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 src = sfc060_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (6);
+l_330285: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e70_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_330286; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	dfc060_put_word (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s16 src = sfc060_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}}l_330286: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e78_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_330287; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	dfc060_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s16 src = sfc060_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (6);
+l_330287: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e79_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_330288; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	dfc060_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_ilong_mmu060 (4);
+{	uae_s16 src = sfc060_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpci (8);
+l_330288: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e90_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_330289; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	dfc060_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = sfc060_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (4);
+l_330289: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e98_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 24; 
+{if (!regs.s) { Exception (8); goto l_330290; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	dfc060_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = sfc060_get_long (srca);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (4);
+l_330290: ;
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ea0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 28; 
+{if (!regs.s) { Exception (8); goto l_330291; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	dfc060_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 src = sfc060_get_long (srca);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (4);
+l_330291: ;
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ea8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_330292; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	dfc060_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s32 src = sfc060_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (6);
+l_330292: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_330293; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	dfc060_put_long (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s32 src = sfc060_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}}l_330293: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 32; 
+{if (!regs.s) { Exception (8); goto l_330294; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	dfc060_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s32 src = sfc060_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (6);
+l_330294: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 40; 
+{if (!regs.s) { Exception (8); goto l_330295; }
+{{	uae_s16 extra = get_iword_mmu060 (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	dfc060_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_ilong_mmu060 (4);
+{	uae_s32 src = sfc060_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpci (8);
+l_330295: ;
+return 40 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ed0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 32; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_lrmw_long_mmu060 (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (4);
+		op_unimpl (opcode);
+		goto l_330296;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_long_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+l_330296: ;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ed8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 32; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_lrmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) -= 4;
+	m68k_incpci (4);
+		op_unimpl (opcode);
+		goto l_330297;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_long_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+l_330297: ;
+	mmufixup[0].reg = -1;
+return 32 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ee0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 34; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_lrmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+		op_unimpl (opcode);
+		goto l_330298;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_long_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (4);
+l_330298: ;
+	mmufixup[0].reg = -1;
+return 34 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ee8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 36; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s32 dst = get_lrmw_long_mmu060 (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (6);
+		op_unimpl (opcode);
+		goto l_330299;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_long_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (6);
+l_330299: ;
+return 36 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 36; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_lrmw_long_mmu060 (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		op_unimpl (opcode);
+		goto l_330300;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_long_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}}l_330300: ;
+return 36 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 36; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s32 dst = get_lrmw_long_mmu060 (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (6);
+		op_unimpl (opcode);
+		goto l_330301;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_long_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (6);
+l_330301: ;
+return 36 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 40; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s32 dst = get_lrmw_long_mmu060 (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpci (8);
+		op_unimpl (opcode);
+		goto l_330302;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		put_lrmw_long_mmu060 (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		put_lrmw_long_mmu060 (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpci (8);
+l_330302: ;
+return 40 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS2.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0efc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 extra;
+	extra = get_ilong_mmu060 (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u32 dst1 = get_lrmw_long_mmu060 (rn1), dst2 = get_lrmw_long_mmu060 (rn2);
+{uae_u32 newv = ((uae_u32)(dst1)) - ((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s32)(dst1)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u32)(dst2)) - ((uae_u32)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s32)(dst2)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, extra & 7))) > ((uae_u32)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	put_lrmw_long_mmu060 (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	put_lrmw_long_mmu060 (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = dst2;
+	m68k_dreg (regs, (extra >> 22) & 7) = dst1;
+	}
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1000_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1010_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1018_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1020_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1028_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1030_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1038_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1039_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1080_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1090_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1098_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10ba_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1100_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1110_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1118_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1120_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1128_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1130_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1138_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1139_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1140_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1150_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1158_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1160_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1168_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1170_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1178_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1179_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1180_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1190_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1198_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11ba_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (10);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_byte_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2000_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2008_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2010_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2018_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2020_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2028_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2030_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2038_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2039_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2040_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2048_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2050_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2058_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2060_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2068_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2070_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	m68k_areg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2078_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2079_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	m68k_areg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_207c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpci (6);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2080_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2088_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2090_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2098_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20ba_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2100_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2108_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2110_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2118_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2120_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2128_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2130_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2138_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2139_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2140_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2148_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2150_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2158_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2160_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 26 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2168_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2170_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2178_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2179_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2180_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2188_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2190_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2198_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_3
+/* MOVE.L -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 26 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21ba_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 26 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 30; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 30 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 36; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (10);
+}}}}return 36 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 32; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}}return 32 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_long_mmu060 (dsta, src);
+	m68k_incpci (10);
+}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3000_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3008_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3010_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3018_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3020_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3028_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3030_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3038_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3039_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3040_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3048_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3050_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3058_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3060_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3068_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3070_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3078_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3079_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_307c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpci (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3080_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3088_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3090_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3098_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30ba_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3100_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3108_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3110_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3118_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3120_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3128_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3130_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3138_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3139_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3140_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3148_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3150_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3158_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3160_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3168_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3170_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3178_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3179_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3180_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3188_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3190_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3198_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31ba_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (2);
+}}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (6);
+}}}}	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (10);
+}}}}return 28 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 24; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (4);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_word_mmu060 (dsta, src);
+	m68k_incpci (8);
+}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4000_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4010_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_rmw_byte_mmu060 (srca, newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4018_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_rmw_byte_mmu060 (srca, newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4020_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_rmw_byte_mmu060 (srca, newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4028_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_rmw_byte_mmu060 (srca, newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4030_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_rmw_byte_mmu060 (srca, newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4038_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_rmw_byte_mmu060 (srca, newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4039_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_rmw_byte_mmu060 (srca, newv);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4040_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4050_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_rmw_word_mmu060 (srca, newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4058_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_rmw_word_mmu060 (srca, newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4060_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_rmw_word_mmu060 (srca, newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4068_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_rmw_word_mmu060 (srca, newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4070_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_rmw_word_mmu060 (srca, newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4078_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_rmw_word_mmu060 (srca, newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4079_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_rmw_word_mmu060 (srca, newv);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4080_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4090_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_rmw_long_mmu060 (srca, newv);
+}}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4098_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_rmw_long_mmu060 (srca, newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_rmw_long_mmu060 (srca, newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_rmw_long_mmu060 (srca, newv);
+}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_rmw_long_mmu060 (srca, newv);
+}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40b8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_rmw_long_mmu060 (srca, newv);
+}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40b9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_rmw_long_mmu060 (srca, newv);
+}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_40c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_330632; }
+{{	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}}	m68k_incpci (2);
+l_330632: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_330633; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	put_word_mmu060 (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_330633: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_40d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_330634; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	put_word_mmu060 (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_330634: ;
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_330635; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	put_word_mmu060 (srca, regs.sr);
+}}}	m68k_incpci (2);
+l_330635: ;
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_330636; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	MakeSR ();
+	put_word_mmu060 (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_330636: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_330637; }
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	put_word_mmu060 (srca, regs.sr);
+}}}}l_330637: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_330638; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	MakeSR ();
+	put_word_mmu060 (srca, regs.sr);
+}}}	m68k_incpci (4);
+l_330638: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_330639; }
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+	MakeSR ();
+	put_word_mmu060 (srca, regs.sr);
+}}}	m68k_incpci (6);
+l_330639: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4100_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330640;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330640;
+	}
+}}}l_330640: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4110_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330641;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330641;
+	}
+}}}}l_330641: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (An)+,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4118_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330642;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330642;
+	}
+}}}}l_330642: ;
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L -(An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4120_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330643;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330643;
+	}
+}}}}l_330643: ;
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d16,An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4128_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330644;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330644;
+	}
+}}}}l_330644: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d8,An,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4130_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330645;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330645;
+	}
+}}}}}l_330645: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (xxx).W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4138_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330646;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330646;
+	}
+}}}}l_330646: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (xxx).L,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4139_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330647;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330647;
+	}
+}}}}l_330647: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d16,PC),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330648;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330648;
+	}
+}}}}l_330648: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d8,PC,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330649;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330649;
+	}
+}}}}}l_330649: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L #.L,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330650;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330650;
+	}
+}}}l_330650: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4180_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330651;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330651;
+	}
+}}}l_330651: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4190_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330652;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330652;
+	}
+}}}}l_330652: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4198_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330653;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330653;
+	}
+}}}}l_330653: ;
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330654;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330654;
+	}
+}}}}l_330654: ;
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330655;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330655;
+	}
+}}}}l_330655: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330656;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330656;
+	}
+}}}}}l_330656: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330657;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330657;
+	}
+}}}}l_330657: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330658;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330658;
+	}
+}}}}l_330658: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41ba_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330659;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330659;
+	}
+}}}}l_330659: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330660;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330660;
+	}
+}}}}}l_330660: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_330661;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_330661;
+	}
+}}}l_330661: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4200_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4210_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_mmu060 (srca, 0);
+}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4218_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_mmu060 (srca, 0);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4220_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_mmu060 (srca, 0);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4228_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_mmu060 (srca, 0);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4230_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_mmu060 (srca, 0);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4238_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_mmu060 (srca, 0);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4239_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	put_byte_mmu060 (srca, 0);
+}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4240_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4250_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_mmu060 (srca, 0);
+}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4258_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_mmu060 (srca, 0);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4260_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_mmu060 (srca, 0);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4268_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_mmu060 (srca, 0);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4270_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_mmu060 (srca, 0);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4278_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_mmu060 (srca, 0);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4279_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	put_word_mmu060 (srca, 0);
+}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4280_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4290_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long_mmu060 (srca, 0);
+}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4298_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long_mmu060 (srca, 0);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long_mmu060 (srca, 0);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long_mmu060 (srca, 0);
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_42b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long_mmu060 (srca, 0);
+}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_42b8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long_mmu060 (srca, 0);
+}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_42b9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	put_long_mmu060 (srca, 0);
+}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	put_word_mmu060 (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	put_word_mmu060 (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	put_word_mmu060 (srca, regs.sr & 0xff);
+}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	MakeSR ();
+	put_word_mmu060 (srca, regs.sr & 0xff);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	put_word_mmu060 (srca, regs.sr & 0xff);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	MakeSR ();
+	put_word_mmu060 (srca, regs.sr & 0xff);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+	MakeSR ();
+	put_word_mmu060 (srca, regs.sr & 0xff);
+}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* NEG.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4400_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_4
+/* NEG.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4410_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4418_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4420_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4428_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4430_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (srca, dst);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4438_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4439_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4440_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4450_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4458_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4460_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4468_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4470_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (srca, dst);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4478_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4479_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4480_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4490_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4498_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (srca, dst);
+}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44b8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44b9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (srca, dst);
+}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_44c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_44d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B #.B */
+uae_u32 REGPARAM2 CPUFUNC(op_44fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4600_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4610_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_rmw_byte_mmu060 (srca, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4618_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_rmw_byte_mmu060 (srca, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4620_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_rmw_byte_mmu060 (srca, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4628_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_rmw_byte_mmu060 (srca, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4630_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_rmw_byte_mmu060 (srca, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4638_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_rmw_byte_mmu060 (srca, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4639_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	put_rmw_byte_mmu060 (srca, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4640_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4650_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_rmw_word_mmu060 (srca, dst);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4658_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_rmw_word_mmu060 (srca, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4660_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_rmw_word_mmu060 (srca, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4668_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_rmw_word_mmu060 (srca, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4670_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_rmw_word_mmu060 (srca, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4678_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_rmw_word_mmu060 (srca, dst);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4679_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_rmw_word_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	put_rmw_word_mmu060 (srca, dst);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4680_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4690_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_rmw_long_mmu060 (srca, dst);
+}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4698_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_rmw_long_mmu060 (srca, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 22; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_rmw_long_mmu060 (srca, dst);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_rmw_long_mmu060 (srca, dst);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_rmw_long_mmu060 (srca, dst);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46b8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 24; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_rmw_long_mmu060 (srca, dst);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46b9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_rmw_long_mmu060 (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	put_rmw_long_mmu060 (srca, dst);
+}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_46c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_330760; }
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.sr = src;
+	MakeFromSR();
+}}}	m68k_incpci (2);
+l_330760: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_330761; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (2);
+l_330761: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_46d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_330762; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (2);
+l_330762: ;
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_330763; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (2);
+l_330763: ;
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_330764; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (4);
+l_330764: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_330765; }
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}}l_330765: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_330766; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (4);
+l_330766: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_330767; }
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (6);
+l_330767: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_330768; }
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpci (4);
+l_330768: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_330769; }
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}}l_330769: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_46fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_330770; }
+{{	uae_s16 src = get_iword_mmu060 (2);
+	regs.sr = src;
+	MakeFromSR();
+}}}	m68k_incpci (4);
+l_330770: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4800_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LINK.L An,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4808_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 22; 
+{	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+{	uae_s32 offs;
+	offs = get_ilong_mmu060 (2);
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	mmufixup[1].reg = 7;
+	mmufixup[1].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = (m68k_areg(regs, 7));
+	m68k_areg(regs, 7) += offs;
+	put_long_mmu060 (olda, src);
+}}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* NBCD.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4810_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_rmw_byte_mmu060 (srca, newv);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4818_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_rmw_byte_mmu060 (srca, newv);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4820_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_rmw_byte_mmu060 (srca, newv);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4828_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_rmw_byte_mmu060 (srca, newv);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4830_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_rmw_byte_mmu060 (srca, newv);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4838_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_rmw_byte_mmu060 (srca, newv);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4839_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_rmw_byte_mmu060 (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_rmw_byte_mmu060 (srca, newv);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SWAP.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4840_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 34;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BKPTQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4848_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 99;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PEA.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4850_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	put_long_mmu060 (dsta, srca);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4868_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	put_long_mmu060 (dsta, srca);
+}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4870_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	put_long_mmu060 (dsta, srca);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4878_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	put_long_mmu060 (dsta, srca);
+}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4879_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	put_long_mmu060 (dsta, srca);
+}}}	m68k_incpci (6);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_487a_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	put_long_mmu060 (dsta, srca);
+}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_487b_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = dsta;
+	put_long_mmu060 (dsta, srca);
+}}}}	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EXT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4880_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u16 dst = (uae_s16)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4890_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_mmu060 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_word_mmu060 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 6;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	while (amask) {
+		srca -= 2;
+		put_word_mmu060 (srca, m68k_areg (regs, movem_index2[amask]));
+		amask = movem_next[amask];
+	}
+	while (dmask) {
+		srca -= 2;
+		put_word_mmu060 (srca, m68k_dreg (regs, movem_index2[dmask]));
+		dmask = movem_next[dmask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpci (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_mmu060 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_word_mmu060 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48b0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_mmu060 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_word_mmu060 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48b8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_mmu060 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_word_mmu060 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48b9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+{	uaecptr srca;
+	srca = get_ilong_mmu060 (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_word_mmu060 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_word_mmu060 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 2;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EXT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_48c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48d0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_long_mmu060 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_long_mmu060 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 10; 
+{	uae_u16 mask = get_iword_mmu060 (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	while (amask) {
+		srca -= 4;
+		put_long_mmu060 (srca, m68k_areg (regs, movem_index2[amask]));
+		amask = movem_next[amask];
+	}
+	while (dmask) {
+		srca -= 4;
+		put_long_mmu060 (srca, m68k_dreg (regs, movem_index2[dmask]));
+		dmask = movem_next[dmask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpci (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_long_mmu060 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_long_mmu060 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48f0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_long_mmu060 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_long_mmu060 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_long_mmu060 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_long_mmu060 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+{	uaecptr srca;
+	srca = get_ilong_mmu060 (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) {
+		put_long_mmu060 (srca, m68k_dreg (regs, movem_index1[dmask]));
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		put_long_mmu060 (srca, m68k_areg (regs, movem_index1[amask]));
+		srca += 4;
+		amask = movem_next[amask];
+	}
+}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXT.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_49c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a00_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a10_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a18_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a20_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a28_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a30_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a38_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a39_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3a_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3b_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B #.B */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3c_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a40_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a48_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a50_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a58_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a60_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a68_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a70_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a78_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a79_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7a_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7b_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7c_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a80_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.L An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a88_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a90_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a98_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TST.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4aba_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4abb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4abc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TAS.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4ac0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((src) & 0xff);
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_lrmw_byte_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_lrmw_byte_mmu060 (srca, src);
+}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_lrmw_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_lrmw_byte_mmu060 (srca, src);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_lrmw_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_lrmw_byte_mmu060 (srca, src);
+}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_lrmw_byte_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_lrmw_byte_mmu060 (srca, src);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4af0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_lrmw_byte_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_lrmw_byte_mmu060 (srca, src);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4af8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_lrmw_byte_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_lrmw_byte_mmu060 (srca, src);
+}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4af9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_lrmw_byte_mmu060 (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	put_lrmw_byte_mmu060 (srca, src);
+}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* MULL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c00_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_330847;
+}}}l_330847: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c10_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_330848;
+}}}}l_330848: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c18_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_330849;
+}}}}l_330849: ;
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c20_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_330850;
+}}}}l_330850: ;
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c28_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_330851;
+}}}}l_330851: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c30_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_330852;
+}}}}}l_330852: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c38_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_330853;
+}}}}l_330853: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c39_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_330854;
+}}}}l_330854: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	m68k_incpci (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_330855;
+}}}}l_330855: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_330856;
+}}}}}l_330856: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3c_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uae_s32 dst;
+	dst = get_ilong_mmu060 (4);
+	m68k_incpci (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_330857;
+}}}l_330857: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c40_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_330858;
+}}}l_330858: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c50_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_330859;
+}}}}l_330859: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c58_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_330860;
+}}}}l_330860: ;
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c60_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 18; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpci (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_330861;
+}}}}l_330861: ;
+	mmufixup[0].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c68_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_330862;
+}}}}l_330862: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c70_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_330863;
+}}}}}l_330863: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c78_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_330864;
+}}}}l_330864: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c79_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_330865;
+}}}}l_330865: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	m68k_incpci (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_330866;
+}}}}l_330866: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_330867;
+}}}}}l_330867: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7c_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uae_s32 dst;
+	dst = get_ilong_mmu060 (4);
+	m68k_incpci (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_330868;
+}}}l_330868: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVMEL.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4c90_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4c98_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}	m68k_incpci (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ca8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_ilong_mmu060 (4);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}	m68k_incpci (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cba_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}	m68k_incpci (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cbb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = (uae_s32)(uae_s16)get_word_mmu060 (srca);
+		srca += 2;
+		amask = movem_next[amask];
+	}
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ce8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpci (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_ilong_mmu060 (4);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}	m68k_incpci (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpci () + 4;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}	m68k_incpci (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iword_mmu060 (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 tmp[16];
+	int tmpreg[16];
+	int idx = 0;
+	while (dmask) {
+		tmpreg[idx] = movem_index1[dmask] + 0;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		dmask = movem_next[dmask];
+	}
+	while (amask) {
+		tmpreg[idx] = movem_index1[amask] + 8;
+		tmp[idx++] = get_long_mmu060 (srca);
+		srca += 4;
+		amask = movem_next[amask];
+	}
+	while (--idx >= 0) {
+		regs.regs[tmpreg[idx]] = tmp[idx];
+	}
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* TRAPQ.L # */
+uae_u32 REGPARAM2 CPUFUNC(op_4e40_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 15);
+	OpcodeFamily = 39;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+	m68k_incpci (2);
+	Exception (src + 32);
+}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* LINK.W An,#.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e50_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 18; 
+{	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	mmufixup[1].reg = 7;
+	mmufixup[1].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = (m68k_areg(regs, 7));
+	m68k_areg(regs, 7) += offs;
+	put_long_mmu060 (olda, src);
+}}}}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* UNLK.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e58_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 48;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	uae_s32 old = get_long_mmu060 (src);
+	m68k_areg (regs, 7) = src + 4;
+	m68k_areg (regs, srcreg) = old;
+}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVR2USP.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e60_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 40;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_330888; }
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	regs.usp = src;
+}}}	m68k_incpci (2);
+l_330888: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVUSP2R.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e68_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 41;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_330889; }
+{{	m68k_areg (regs, srcreg) = (regs.usp);
+}}}	m68k_incpci (2);
+l_330889: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RESET.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e70_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 42;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_330890; }
+{	cpureset ();
+	m68k_incpci (2);
+}}l_330890: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOP.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e71_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 43;
+	CurrentInstrCycles = 4;  
+{}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* STOP.L #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e72_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 44;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_330892; }
+{{	uae_s16 src = get_iword_mmu060 (2);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_setstopped ();
+	m68k_incpci (4);
+}}}l_330892: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RTE.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e73_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 45;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_330893; }
+{	uae_u16 newsr; uae_u32 newpc;
+	for (;;) {
+		uaecptr a = m68k_areg (regs, 7);
+		uae_u16 sr = get_word_mmu060 (a);
+		uae_u32 pc = get_long_mmu060 (a + 2);
+		uae_u16 format = get_word_mmu060 (a + 2 + 4);
+		int frame = format >> 12;
+		int offset = 8;
+		newsr = sr; newpc = pc;
+		if (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }
+		else if (frame == 0x1) { m68k_areg (regs, 7) += offset; }
+		else if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }
+		else if (frame == 0x4) { m68k_do_rte_mmu060 (a); m68k_areg (regs, 7) += offset + 8; break; }
+		else if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }
+		else if (frame == 0x7) { m68k_areg (regs, 7) += offset + 52; break; }
+		else if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }
+		else if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }
+		else if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }
+		else { m68k_areg (regs, 7) += offset; Exception (14); goto l_330893; }
+		regs.sr = newsr;
+	MakeFromSR();
+}
+	regs.sr = newsr;
+	MakeFromSR();
+	if (newpc & 1) {
+		exception3i (0x4E73, newpc);
+		goto l_330893;
+	}
+	m68k_setpci (newpc);
+}}l_330893: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RTD.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e74_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 46;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 offs = get_iword_mmu060 (2);
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = get_long_mmu060 (pca);
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) += 4;
+	m68k_areg(regs, 7) += offs;
+	if (pc & 1) {
+		exception3i (0x4E74, pc);
+		goto l_330894;
+	}
+	m68k_setpci (pc);
+}}}}l_330894: ;
+	mmufixup[0].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* RTS.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e75_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 49;
+	CurrentInstrCycles = 8;  
+{	uaecptr pc = m68k_getpci ();
+	m68k_do_rts_mmu060 ();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (pc);
+		exception3i (0x4E75, faultpc);
+		goto l_330895;
+	}
+}l_330895: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TRAPV.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e76_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 50;
+	CurrentInstrCycles = 4;  
+{	m68k_incpci (2);
+	if (GET_VFLG ()) {
+		Exception (7);
+		goto l_330896;
+	}
+}l_330896: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RTR.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e77_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 51;
+	CurrentInstrCycles = 16; 
+{	uaecptr oldpc = m68k_getpci ();
+	MakeSR ();
+{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+{	uae_s16 sr = get_word_mmu060 (sra);
+	mmufixup[0].reg = 7;
+	mmufixup[0].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = get_long_mmu060 (pca);
+	mmufixup[1].reg = 7;
+	mmufixup[1].value = m68k_areg (regs, 7);
+	m68k_areg (regs, 7) += 4;
+	regs.sr &= 0xFF00; sr &= 0xFF;
+	regs.sr |= sr;
+	m68k_setpci (pc);
+	MakeFromSR();
+	if (m68k_getpci () & 1) {
+		uaecptr faultpc = m68k_getpci ();
+	m68k_setpci (oldpc);
+		exception3i (0x4E77, faultpc);
+		goto l_330897;
+	}
+}}}}}l_330897: ;
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVEC2.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7a_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 82;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_330898; }
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_movec2(src & 0xFFF, regp)) goto l_330898;
+}}}}	m68k_incpci (4);
+l_330898: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE2C.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7b_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 83;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_330899; }
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_move2c(src & 0xFFF, regp)) goto l_330899;
+}}}}	m68k_incpci (4);
+l_330899: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* JSR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4e90_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr oldpc = m68k_getpci () + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_330900;
+	}
+	put_long_mmu060 (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_330900: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ea8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_330901;
+	}
+	put_long_mmu060 (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_330901: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_330902;
+	}
+	put_long_mmu060 (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}}l_330902: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_330903;
+	}
+	put_long_mmu060 (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_330903: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uaecptr oldpc = m68k_getpci () + 6;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_330904;
+	}
+	put_long_mmu060 (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_330904: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eba_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uaecptr oldpc = m68k_getpci () + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_330905;
+	}
+	put_long_mmu060 (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}l_330905: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ebb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uaecptr oldpc = m68k_getpci () + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_330906;
+	}
+	put_long_mmu060 (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_setpci (srca);
+}}}}l_330906: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ed0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_330907;
+	}
+	m68k_setpci (srca);
+}}l_330907: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ee8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_330908;
+	}
+	m68k_setpci (srca);
+}}l_330908: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_330909;
+	}
+	m68k_setpci (srca);
+}}}l_330909: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_330910;
+	}
+	m68k_setpci (srca);
+}}l_330910: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_330911;
+	}
+	m68k_setpci (srca);
+}}l_330911: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_330912;
+	}
+	m68k_setpci (srca);
+}}l_330912: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_330913;
+	}
+	m68k_setpci (srca);
+}}}l_330913: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5000_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5010_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5018_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5020_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5028_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5030_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5038_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5039_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5040_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5048_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5050_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5058_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5060_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5068_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5070_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5078_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5079_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5080_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5088_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5090_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5098_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_5
+/* ADDQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_50b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_50b8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_50b9_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (0) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (0)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_330941;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_330941: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (0)) { Exception (7); goto l_330949; }
+}}	m68k_incpci (4);
+l_330949: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (0)) { Exception (7); goto l_330950; }
+}}	m68k_incpci (6);
+l_330950: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (0)) { Exception (7); goto l_330951; }
+}	m68k_incpci (2);
+l_330951: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* SUBQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5100_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5110_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5118_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5120_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5128_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5130_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5138_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5139_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5140_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5148_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5150_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5158_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5160_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5168_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5170_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5178_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5179_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5180_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5188_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5190_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5198_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_51b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_51b8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_51b9_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (1) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (1)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_330979;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_330979: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (1)) { Exception (7); goto l_330987; }
+}}	m68k_incpci (4);
+l_330987: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (1)) { Exception (7); goto l_330988; }
+}}	m68k_incpci (6);
+l_330988: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (1)) { Exception (7); goto l_330989; }
+}	m68k_incpci (2);
+l_330989: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (2) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (2)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_330991;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_330991: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (2)) { Exception (7); goto l_330999; }
+}}	m68k_incpci (4);
+l_330999: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (2)) { Exception (7); goto l_331000; }
+}}	m68k_incpci (6);
+l_331000: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (2)) { Exception (7); goto l_331001; }
+}	m68k_incpci (2);
+l_331001: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (3) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (3)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_331003;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_331003: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (3)) { Exception (7); goto l_331011; }
+}}	m68k_incpci (4);
+l_331011: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (3)) { Exception (7); goto l_331012; }
+}}	m68k_incpci (6);
+l_331012: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (3)) { Exception (7); goto l_331013; }
+}	m68k_incpci (2);
+l_331013: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (4) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (4)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_331015;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_331015: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (4)) { Exception (7); goto l_331023; }
+}}	m68k_incpci (4);
+l_331023: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (4)) { Exception (7); goto l_331024; }
+}}	m68k_incpci (6);
+l_331024: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (4)) { Exception (7); goto l_331025; }
+}	m68k_incpci (2);
+l_331025: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (5) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (5)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_331027;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_331027: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (5)) { Exception (7); goto l_331035; }
+}}	m68k_incpci (4);
+l_331035: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (5)) { Exception (7); goto l_331036; }
+}}	m68k_incpci (6);
+l_331036: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (5)) { Exception (7); goto l_331037; }
+}	m68k_incpci (2);
+l_331037: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (6) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (6)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_331039;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_331039: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (6)) { Exception (7); goto l_331047; }
+}}	m68k_incpci (4);
+l_331047: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (6)) { Exception (7); goto l_331048; }
+}}	m68k_incpci (6);
+l_331048: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (6)) { Exception (7); goto l_331049; }
+}	m68k_incpci (2);
+l_331049: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (7) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (7)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_331051;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_331051: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (7)) { Exception (7); goto l_331059; }
+}}	m68k_incpci (4);
+l_331059: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (7)) { Exception (7); goto l_331060; }
+}}	m68k_incpci (6);
+l_331060: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (7)) { Exception (7); goto l_331061; }
+}	m68k_incpci (2);
+l_331061: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (8) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (8)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_331063;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_331063: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (8)) { Exception (7); goto l_331071; }
+}}	m68k_incpci (4);
+l_331071: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (8)) { Exception (7); goto l_331072; }
+}}	m68k_incpci (6);
+l_331072: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (8)) { Exception (7); goto l_331073; }
+}	m68k_incpci (2);
+l_331073: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (9) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (9)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_331075;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_331075: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (9)) { Exception (7); goto l_331083; }
+}}	m68k_incpci (4);
+l_331083: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (9)) { Exception (7); goto l_331084; }
+}}	m68k_incpci (6);
+l_331084: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (9)) { Exception (7); goto l_331085; }
+}	m68k_incpci (2);
+l_331085: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (10) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (10)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_331087;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_331087: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (10)) { Exception (7); goto l_331095; }
+}}	m68k_incpci (4);
+l_331095: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (10)) { Exception (7); goto l_331096; }
+}}	m68k_incpci (6);
+l_331096: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (10)) { Exception (7); goto l_331097; }
+}	m68k_incpci (2);
+l_331097: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (11) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (11)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_331099;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_331099: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (11)) { Exception (7); goto l_331107; }
+}}	m68k_incpci (4);
+l_331107: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (11)) { Exception (7); goto l_331108; }
+}}	m68k_incpci (6);
+l_331108: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (11)) { Exception (7); goto l_331109; }
+}	m68k_incpci (2);
+l_331109: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (12) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (12)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_331111;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_331111: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (12)) { Exception (7); goto l_331119; }
+}}	m68k_incpci (4);
+l_331119: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (12)) { Exception (7); goto l_331120; }
+}}	m68k_incpci (6);
+l_331120: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (12)) { Exception (7); goto l_331121; }
+}	m68k_incpci (2);
+l_331121: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (13) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (13)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_331123;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_331123: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (13)) { Exception (7); goto l_331131; }
+}}	m68k_incpci (4);
+l_331131: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (13)) { Exception (7); goto l_331132; }
+}}	m68k_incpci (6);
+l_331132: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (13)) { Exception (7); goto l_331133; }
+}	m68k_incpci (2);
+l_331133: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (14) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (14)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_331135;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_331135: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (14)) { Exception (7); goto l_331143; }
+}}	m68k_incpci (4);
+l_331143: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (14)) { Exception (7); goto l_331144; }
+}}	m68k_incpci (6);
+l_331144: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (14)) { Exception (7); goto l_331145; }
+}	m68k_incpci (2);
+l_331145: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (15) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iword_mmu060 (2);
+	uaecptr oldpc = m68k_getpci ();
+	if (!cctrue (15)) {
+	m68k_incpci ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpci () + 2 + (uae_s32)offs + 2);
+				goto l_331147;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpci (oldpc + 4);
+}}}l_331147: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	put_byte_mmu060 (srca, val);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffa_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iword_mmu060 (2);
+	if (cctrue (15)) { Exception (7); goto l_331155; }
+}}	m68k_incpci (4);
+l_331155: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffb_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (2);
+	if (cctrue (15)) { Exception (7); goto l_331156; }
+}}	m68k_incpci (6);
+l_331156: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffc_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (15)) { Exception (7); goto l_331157; }
+}	m68k_incpci (2);
+l_331157: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Bcc.W #.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6000_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331158;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331158: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6001_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331159;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331159: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_60ff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331160;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331160: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_6100_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_s16 src = get_iword_mmu060 (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_331161;
+	}
+	m68k_do_bsr_mmu060 (m68k_getpci () + 4, s);
+}}l_331161: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSRQ.B # */
+uae_u32 REGPARAM2 CPUFUNC(op_6101_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_u32 src = srcreg;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_331162;
+	}
+	m68k_do_bsr_mmu060 (m68k_getpci () + 2, s);
+}}l_331162: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSR.L #.L */
+uae_u32 REGPARAM2 CPUFUNC(op_61ff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpci () + s, 0, 1, m68k_getpci () + s);
+		goto l_331163;
+	}
+	m68k_do_bsr_mmu060 (m68k_getpci () + 6, s);
+}}l_331163: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6200_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331164;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331164: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6201_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331165;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331165: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_62ff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331166;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331166: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6300_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331167;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331167: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6301_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331168;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331168: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_6
+/* Bcc.L #.L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_63ff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331169;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331169: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6400_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331170;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331170: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6401_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331171;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331171: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_64ff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331172;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331172: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6500_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331173;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331173: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6501_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331174;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331174: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_65ff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331175;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331175: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6600_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331176;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331176: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6601_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331177;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331177: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_66ff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331178;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331178: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6700_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331179;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331179: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6701_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331180;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331180: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_67ff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331181;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331181: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6800_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331182;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331182: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6801_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331183;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331183: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_68ff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331184;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331184: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6900_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331185;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331185: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6901_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331186;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331186: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_69ff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331187;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331187: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a00_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331188;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331188: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a01_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331189;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331189: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6aff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331190;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331190: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b00_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331191;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331191: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b01_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331192;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331192: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6bff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331193;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331193: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c00_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331194;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331194: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c01_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331195;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331195: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6cff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331196;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331196: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d00_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331197;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331197: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d01_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331198;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331198: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6dff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331199;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331199: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e00_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331200;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331200: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e01_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331201;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331201: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6eff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331202;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331202: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f00_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331203;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (4);
+}}l_331203: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f01_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331204;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (2);
+}}l_331204: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6fff_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpci () + 2 + (uae_s32)src);
+		goto l_331205;
+	}
+	m68k_incpci ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpci (6);
+}}l_331205: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_7000_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpci (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8000_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8010_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8018_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8020_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8028_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8030_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8038_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8039_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8040_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8050_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8058_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8060_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8068_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8070_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8078_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8079_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8080_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8090_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8098_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80ba_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 110;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_331240;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}l_331240: ;
+return 110 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 114;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_331241;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}l_331241: ;
+return 114 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 114;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_331242;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}l_331242: ;
+	mmufixup[0].reg = -1;
+return 114 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 116;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_331243;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (2);
+	}
+}}}}l_331243: ;
+	mmufixup[0].reg = -1;
+return 116 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_331244;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}l_331244: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_331245;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_331245: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_331246;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}l_331246: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 122;
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_331247;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (6);
+	}
+}}}}l_331247: ;
+return 122 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_331248;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}}l_331248: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 118;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_331249;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_331249: ;
+return 118 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 114;
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_331250;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpci (4);
+	}
+}}}l_331250: ;
+return 114 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8100_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8108_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8110_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8118_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8120_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8128_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8130_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8138_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8139_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* PACK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8140_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val = m68k_dreg (regs, srcreg) + get_iword_mmu060 (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PACK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8148_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(get_byte_mmu060 (m68k_areg (regs, srcreg)) & 0xff);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (val | ((uae_u16)(get_byte_mmu060 (m68k_areg (regs, srcreg)) & 0xff) << 8)) + get_iword_mmu060 (2);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) -= areg_byteinc[dstreg];
+	put_byte_mmu060 (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));
+}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* OR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8150_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8158_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8160_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8168_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8170_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8178_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8179_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* UNPK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8180_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val = m68k_dreg (regs, srcreg);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_iword_mmu060 (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* UNPK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8188_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(get_byte_mmu060 (m68k_areg (regs, srcreg)) & 0xff);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_iword_mmu060 (2);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];
+	put_byte_mmu060 (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);
+	put_byte_mmu060 (m68k_areg (regs, dstreg), val >> 8);
+}	m68k_incpci (4);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* OR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8190_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8198_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_81b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_81b8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_81b9_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 142;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_331278;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}l_331278: ;
+return 142 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 146;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_331279;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}l_331279: ;
+return 146 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 146;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_331280;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}l_331280: ;
+	mmufixup[0].reg = -1;
+return 146 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 148;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (2);
+		Exception (5);
+		goto l_331281;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (2);
+}}}}l_331281: ;
+	mmufixup[0].reg = -1;
+return 148 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_331282;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}l_331282: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_331283;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_331283: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_331284;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}l_331284: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 154;
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (6);
+		Exception (5);
+		goto l_331285;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (6);
+}}}}l_331285: ;
+return 154 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_331286;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}}l_331286: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 150;
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (0);
+		Exception (5);
+		goto l_331287;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_331287: ;
+return 150 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 146;
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpci (4);
+		Exception (5);
+		goto l_331288;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpci (4);
+}}}l_331288: ;
+return 146 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9000_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9010_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9018_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9020_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9028_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9030_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9038_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9039_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9040_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9048_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9050_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9058_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9060_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9068_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9070_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9078_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9079_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9080_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9088_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9090_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9098_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90ba_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9100_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9108_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9110_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9118_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9120_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9128_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9130_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9138_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9139_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9140_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9148_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9150_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9158_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9160_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9168_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9170_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9178_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9179_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9180_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9188_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9190_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9198_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_91b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_91b8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_91b9_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b000_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b010_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b018_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b020_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b028_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b030_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b038_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b039_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b040_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b048_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b050_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b058_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b060_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b068_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b070_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b078_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b079_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b080_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b088_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b090_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b098_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_7
+/* CMP.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0ba_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b100_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b108_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_byte_mmu060 (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b110_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b118_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b120_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b128_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b130_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b138_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b139_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b140_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b148_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_word_mmu060 (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b150_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b158_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b160_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b168_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b170_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b178_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b179_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b180_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b188_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_long_mmu060 (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b190_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b198_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b9_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c000_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c010_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c018_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c020_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c028_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c030_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c038_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c039_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c040_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c050_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c058_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c060_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c068_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c070_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c078_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c079_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c080_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c090_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c098_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0ba_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 58; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}return 58 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 62; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}return 62 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 62; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}	mmufixup[0].reg = -1;
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 64; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (2);
+}}}}}	mmufixup[0].reg = -1;
+return 64 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 70; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (6);
+}}}}}return 70 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 66; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 62; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpci (4);
+}}}}return 62 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c100_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c108_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c110_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c118_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c120_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c128_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c130_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c138_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c139_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	put_rmw_byte_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c140_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c148_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	m68k_areg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c150_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c158_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c160_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c168_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c170_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c178_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c179_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	put_rmw_word_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c188_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c190_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c198_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b9_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	put_rmw_long_mmu060 (dsta, src);
+}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 58; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 58 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 62; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 62; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 64; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 64 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 70; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 70 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 66; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 66 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 62; 
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d000_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d010_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d018_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d020_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d028_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d030_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d038_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d039_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = get_byte_mmu060 (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_ibyte_mmu060 (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d040_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d048_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d050_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d058_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d060_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d068_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d070_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d078_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d079_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07c_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d080_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d088_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d090_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d098_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0ba_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = get_word_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iword_mmu060 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d100_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d108_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = get_byte_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d110_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d118_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d120_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d128_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d130_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d138_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d139_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s8 dst = get_rmw_byte_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_byte_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d140_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d148_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = get_word_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d150_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d158_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d160_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d168_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d170_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d178_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d179_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s16 dst = get_rmw_word_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_word_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d180_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d188_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 28; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[1].reg = dstreg;
+	mmufixup[1].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d190_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d198_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 20; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 22; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+	mmufixup[0].reg = dstreg;
+	mmufixup[0].value = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 22 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpci (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}}return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 24; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (4);
+return 24 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b9_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 28; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (2);
+{	uae_s32 dst = get_rmw_long_mmu060 (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	put_rmw_long_mmu060 (dsta, newv);
+}}}}}}}	m68k_incpci (6);
+return 28 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = get_long_mmu060 (srca);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpci (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f9_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_ilong_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpci () + 2;
+	srca += (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpci (2);
+{	tmppc = m68k_getpci ();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = get_long_mmu060 (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fc_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_ilong_mmu060 (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e000_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e008_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e010_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e018_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e020_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e028_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e030_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e038_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e040_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_8
+/* LSRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e048_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e050_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e058_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e060_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e068_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e070_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e078_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e080_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e088_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e090_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e098_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e100_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e108_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e110_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e118_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e120_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e128_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e130_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e138_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e140_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e148_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e150_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e158_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e160_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e168_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e170_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e178_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e180_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e188_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e190_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e198_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpci (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_rmw_word_mmu060 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_rmw_word_mmu060 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 12; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 14; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (2);
+	mmufixup[0].reg = -1;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	m68k_incpci (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_rmw_word_mmu060 (dataa, val);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 16; 
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iword_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 20; 
+{{	uaecptr dataa;
+	dataa = get_ilong_mmu060 (2);
+{	uae_s16 data = get_rmw_word_mmu060 (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	put_rmw_word_mmu060 (dataa, val);
+}}}}	m68k_incpci (6);
+return 20 * CYCLE_UNIT / 2;
+}
+
+/* BFTST.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8c0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8d0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8e8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9c0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9d0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9e8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9fa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9fb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eac0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ead0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eae8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebc0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebd0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebe8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebfa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebfb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecc0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecd0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ece8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edc0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edd0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ede8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edfa_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_getpci () + 4;
+	dsta += (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edfb_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpci (4);
+{	tmppc = m68k_getpci ();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eec0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eed0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eee8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efc0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efd0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efe8_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff0_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	m68k_incpci (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff8_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iword_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff9_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iword_mmu060 (2);
+{	uaecptr dsta;
+	dsta = get_ilong_mmu060 (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = mmu060_get_rmw_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	mmu060_put_rmw_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpci (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L Dn,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f000_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331788; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	uae_u16 extraa = 0;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}l_331788: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L An,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f008_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331789; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	uae_u16 extraa = 0;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}l_331789: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f010_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331790; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_331790: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (An)+,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f018_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331791; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_331791: ;
+	mmufixup[0].reg = -1;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L -(An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f020_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 6;  
+{if (!regs.s) { Exception (8); goto l_331792; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) - 4;
+	mmufixup[0].reg = srcreg;
+	mmufixup[0].value = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) = extraa;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_331792: ;
+	mmufixup[0].reg = -1;
+return 6 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (d16,An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f028_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_331793; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu060 (0);
+	m68k_incpci (2);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_331793: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (d8,An,Xn),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f030_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_331794; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+{	extraa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}}l_331794: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (xxx).W,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f038_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_331795; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = (uae_s32)(uae_s16)get_iword_mmu060 (0);
+	m68k_incpci (2);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_331795: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (xxx).L,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f039_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_331796; }
+{	uaecptr pc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+{	uaecptr extraa;
+	extraa = get_ilong_mmu060 (0);
+	m68k_incpci (4);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_331796: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f200_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f208_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f210_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f218_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f220_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f228_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f230_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f238_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f239_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23a_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23b_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23c_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f240_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FDBcc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f248_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 105;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_dbcc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f250_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f258_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f260_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f268_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f270_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f278_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f279_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27a_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 12; 
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu060 (2);
+{	uae_s16 dummy = get_iword_mmu060 (4);
+	m68k_incpci (6);
+	fpuop_trapcc (opcode, oldpc, extra);
+}
+#endif
+}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27b_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 16; 
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu060 (2);
+{	uae_s32 dummy;
+	dummy = get_ilong_mmu060 (4);
+	m68k_incpci (8);
+	fpuop_trapcc (opcode, oldpc, extra);
+}
+#endif
+}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L  */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27c_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpci ();
+	uae_u16 extra = get_iword_mmu060 (2);
+	m68k_incpci (4);
+	fpuop_trapcc (opcode, oldpc, extra);
+
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FBccQ.L #,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f280_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s16 extra = get_iword_mmu060 (0);
+	m68k_incpci (2);
+	fpuop_bcc (opcode, pc,extra);
+}}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FBccQ.L #,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f2c0_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+	CurrentInstrCycles = 12; 
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+{	uaecptr pc = m68k_getpci ();
+{	uae_s32 extra;
+	extra = get_ilong_mmu060 (0);
+	m68k_incpci (4);
+	fpuop_bcc (opcode, pc,extra);
+}}
+#endif
+}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f310_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331823; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_331823: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f320_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331824; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_331824: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f328_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331825; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_331825: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f330_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331826; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_331826: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f338_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331827; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_331827: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f339_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331828; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_331828: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f350_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331829; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_331829: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f358_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331830; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_331830: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f368_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331831; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_331831: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f370_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331832; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_331832: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f378_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331833; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_331833: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f379_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331834; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_331834: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f37a_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331835; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_331835: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f37b_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331836; }
+{
+#ifdef FPUEMU
+	m68k_incpci (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_331836: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVLQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f408_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 111;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331837; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331837: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVPQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f410_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 112;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331838; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331838: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f418_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331839; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331839: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f419_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331840; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331840: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41a_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331841; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331841: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41b_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331842; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331842: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41c_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331843; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331843: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41d_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331844; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331844: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41e_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331845; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331845: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41f_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331846; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331846: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHLQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f428_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 114;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331847; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331847: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHPQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f430_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 115;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331848; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331848: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f438_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331849; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331849: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f439_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331850; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331850: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43a_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331851; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331851: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43b_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331852; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331852: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43c_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331853; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331853: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43d_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331854; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331854: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43e_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331855; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331855: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43f_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331856; }
+{	flush_cpu_caches_040(opcode);
+	flush_mmu060(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpci (2);
+l_331856: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSHN.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f500_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 119;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331857; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_331857: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSH.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f508_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 120;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331858; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_331858: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSHAN.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f510_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 121;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331859; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_331859: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSHA.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f518_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 122;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331860; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_331860: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PTESTW.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f548_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 126;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331861; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_331861: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PTESTR.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f568_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 125;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331862; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_331862: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PLPAW.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f588_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 124;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331863; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_331863: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PLPAR.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f5c8_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 123;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331864; }
+{	m68k_incpci (2);
+	mmu_op (opcode, 0);
+}}l_331864: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (An)+,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f600_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = m68k_areg (regs, srcreg);
+{	uaecptr memda;
+	memda = get_ilong_mmu060 (2);
+	get_move16_mmu (memsa, v);
+	put_move16_mmu (memda, v);
+	m68k_areg (regs, srcreg) += 16;
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (xxx).L,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f608_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = get_ilong_mmu060 (2);
+{	uaecptr memda;
+	memda = m68k_areg (regs, dstreg);
+	get_move16_mmu (memsa, v);
+	put_move16_mmu (memda, v);
+	m68k_areg (regs, dstreg) += 16;
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (An),(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f610_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = m68k_areg (regs, srcreg);
+{	uaecptr memda;
+	memda = get_ilong_mmu060 (2);
+	get_move16_mmu (memsa, v);
+	put_move16_mmu (memda, v);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (xxx).L,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f618_33)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = get_ilong_mmu060 (2);
+{	uaecptr memda;
+	memda = m68k_areg (regs, dstreg);
+	get_move16_mmu (memsa, v);
+	put_move16_mmu (memda, v);
+}}}	m68k_incpci (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (An)+,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f620_33)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = 0;
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 8;  
+{	uae_u32 v[4];
+	uaecptr mems = m68k_areg (regs, srcreg) & ~15, memd;
+	dstreg = (get_iword_mmu060 (2) >> 12) & 7;
+	memd = m68k_areg (regs, dstreg) & ~15;
+	get_move16_mmu (mems, v);
+	put_move16_mmu (memd, v);
+	if (srcreg != dstreg)
+		m68k_areg (regs, srcreg) += 16;
+	m68k_areg (regs, dstreg) += 16;
+}	m68k_incpci (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* LPSTOP.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f800_33)(uae_u32 opcode)
+{
+	OpcodeFamily = 127;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_331870; }
+{	uae_u16 sw = get_iword_mmu060 (2);
+	uae_u16 sr;
+	if (sw != (0x100|0x80|0x40)) { Exception (4); goto l_331870; }
+	sr = get_iword_mmu060 (4);
+	if (!(sr & 0x8000)) { Exception (8); goto l_331870; }
+	regs.sr = sr;
+	MakeFromSR();
+	m68k_setstopped();
+	m68k_incpci (6);
+}}l_331870: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
diff --git a/src/cpu/cpuemu_40.c b/src/cpu/cpuemu_40.c
new file mode 100644
index 0000000..3416bcf
--- /dev/null
+++ b/src/cpu/cpuemu_40.c
@@ -0,0 +1,46647 @@
+#include "main.h"
+#include "sysdeps.h"
+#include "hatari-glue.h"
+#include "maccess.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "cputbl.h"
+#define CPUFUNC(x) x##_ff
+#define SET_CFLG_ALWAYS(x) SET_CFLG(x)
+#define SET_NFLG_ALWAYS(x) SET_NFLG(x)
+#ifdef NOFLAGS
+#include "noflags.h"
+#endif
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0000_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0010_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0018_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0020_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0028_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0030_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0038_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0039_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_003c_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_iiword_jit (2);
+	src &= 0xFF;
+	regs.sr |= src;
+	MakeFromSR();
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0040_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0050_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0058_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0060_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0068_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0070_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0078_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0079_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_007c_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 4;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400018; }
+{	MakeSR ();
+{	uae_s16 src = get_iiword_jit (2);
+	regs.sr |= src;
+	MakeFromSR();
+}}}	m68k_incpc (4);
+l_400018: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0080_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0090_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0098_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_00a8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_00b0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_00b8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_00b9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00d0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400027; }
+}
+}}}	m68k_incpc (4);
+l_400027: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00e8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400028; }
+}
+}}}	m68k_incpc (6);
+l_400028: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400029; }
+}
+}}}}l_400029: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400030; }
+}
+}}}	m68k_incpc (6);
+l_400030: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400031; }
+}
+}}}	m68k_incpc (8);
+l_400031: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc() + 4;
+	dsta += (uae_s32)(uae_s16)get_iiword_jit (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400032; }
+}
+}}}	m68k_incpc (6);
+l_400032: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.B #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_00fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s8)x_get_byte (dsta); upper = (uae_s32)(uae_s8)x_get_byte (dsta + 1);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400033; }
+}
+}}}}l_400033: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BTST.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0100_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPMR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0108_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 8;  
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_u16 val;
+	MovepByteNbr=1; val = ((x_get_byte (memp) & 0xff) << 8);
+	MovepByteNbr=2; val += (x_get_byte (memp + 2) & 0xff);
+	MovepByteNbr=0;
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0110_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0118_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0120_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0128_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0130_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0138_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0139_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_013a_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_getpc() + 2;
+	dsta += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_013b_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,#.B */
+uae_u32 REGPARAM2 CPUFUNC(op_013c_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = get_iibyte_jit (2);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0140_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPMR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0148_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 29;
+	CurrentInstrCycles = 16; 
+{	uaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_u32 val;
+	MovepByteNbr=1; val = ((x_get_byte (memp) & 0xff) << 24);
+	MovepByteNbr=2; val += ((x_get_byte (memp + 2) & 0xff) << 16);
+	MovepByteNbr=3; val += ((x_get_byte (memp + 4) & 0xff) << 8);
+	MovepByteNbr=4; val += (x_get_byte (memp + 6) & 0xff);
+	MovepByteNbr=0;
+	m68k_dreg (regs, dstreg) = (val);
+}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0150_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0158_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0160_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0168_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0170_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0178_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0179_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0180_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPRM.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0188_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	MovepByteNbr=1; 	x_put_byte (memp, src >> 8);
+	MovepByteNbr=2; 	x_put_byte (memp + 2, src);
+	MovepByteNbr=0;
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0190_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0198_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01b8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01b9_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_01c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVPRM.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 28;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	uaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	MovepByteNbr=1; 	x_put_byte (memp, src >> 24);
+	MovepByteNbr=2; 	x_put_byte (memp + 2, src >> 16);
+	MovepByteNbr=3; 	x_put_byte (memp + 4, src >> 8);
+	MovepByteNbr=4; 	x_put_byte (memp + 6, src);
+	MovepByteNbr=0;
+}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_01d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_01e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_01f8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_01f9_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0200_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0210_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0218_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0220_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0228_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0230_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0238_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0239_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ANDSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_023c_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_iiword_jit (2);
+	src |= 0xFF00;
+	regs.sr &= src;
+	MakeFromSR();
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0240_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0250_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0258_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0260_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0268_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0270_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0278_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0279_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ANDSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_027c_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 5;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400090; }
+{	MakeSR ();
+{	uae_s16 src = get_iiword_jit (2);
+	regs.sr &= src;
+	MakeFromSR();
+}}}	m68k_incpc (4);
+l_400090: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0280_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0290_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0298_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_02a8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_02b0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_02b8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_02b9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02d0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400099; }
+}
+}}}	m68k_incpc (4);
+l_400099: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02e8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400100; }
+}
+}}}	m68k_incpc (6);
+l_400100: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400101; }
+}
+}}}}l_400101: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400102; }
+}
+}}}	m68k_incpc (6);
+l_400102: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400103; }
+}
+}}}	m68k_incpc (8);
+l_400103: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc() + 4;
+	dsta += (uae_s32)(uae_s16)get_iiword_jit (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400104; }
+}
+}}}	m68k_incpc (6);
+l_400104: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_02fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = (uae_s32)(uae_s16)x_get_word (dsta); upper = (uae_s32)(uae_s16)x_get_word (dsta + 2);
+	if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400105; }
+}
+}}}}l_400105: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0400_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0410_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0418_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0420_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0428_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0430_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0438_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0439_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0440_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0450_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0458_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0460_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0468_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0470_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0478_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0479_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0480_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0490_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0498_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_04a8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_04b0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_04b8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_04b9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CHK2.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04d0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400130; }
+}
+}}}	m68k_incpc (4);
+l_400130: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04e8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400131; }
+}
+}}}	m68k_incpc (6);
+l_400131: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400132; }
+}
+}}}}l_400132: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400133; }
+}
+}}}	m68k_incpc (6);
+l_400133: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400134; }
+}
+}}}	m68k_incpc (8);
+l_400134: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc() + 4;
+	dsta += (uae_s32)(uae_s16)get_iiword_jit (4);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400135; }
+}
+}}}	m68k_incpc (6);
+l_400135: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK2.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_04fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 81;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+	{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
+	lower = x_get_long (dsta); upper = x_get_long (dsta + 4);
+	SET_ZFLG (upper == reg || lower == reg);
+	SET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);
+	if ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto l_400136; }
+}
+}}}}l_400136: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0600_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0610_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0618_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0620_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0628_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0630_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0638_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0639_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0640_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0650_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0658_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0660_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0668_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0670_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0678_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0679_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0680_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0690_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0698_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_06a8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_06b0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_06b8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_06b9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RTM.L Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* RTM.L An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 101;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CALLM.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_06fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 100;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BTST.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0800_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0810_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0818_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0820_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0828_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0830_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0838_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0839_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_083a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc() + 4;
+	dsta += (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_083b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0840_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0850_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0858_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0860_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0868_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0870_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0878_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0879_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0880_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0890_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0898_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08a8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08b0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08b8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08b9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.L #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_08c0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= 31;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	m68k_dreg (regs, dstreg) = (dst);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08d0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_08d8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_08e8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08f0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_08f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_08f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a00_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a10_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a18_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a20_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a28_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a30_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a38_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a39_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EORSR.B #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a3c_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 8;  
+{	MakeSR ();
+{	uae_s16 src = get_iiword_jit (2);
+	src &= 0xFF;
+	regs.sr ^= src;
+	MakeFromSR();
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a40_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a50_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a58_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a60_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a68_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a70_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a78_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0a79_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EORSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_0a7c_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 6;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400221; }
+{	MakeSR ();
+{	uae_s16 src = get_iiword_jit (2);
+	regs.sr ^= src;
+	MakeFromSR();
+}}}	m68k_incpc (4);
+l_400221: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0a80_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a90_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0a98_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0aa8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (10);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CAS.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ad0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ad8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ae0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpc (4);
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ae8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
+#ifdef PART_2
+/* CAS.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0af9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s8)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(m68k_dreg (regs, rc))) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_byte (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_byte (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
+}}}}}}}}	m68k_incpc (8);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c00_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c10_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c18_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c20_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c28_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c30_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c38_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c39_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c3a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc() + 4;
+	dsta += (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.B #.B,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c3b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c40_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c50_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c58_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c60_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c68_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c70_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0c78_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0c79_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c7a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc() + 4;
+	dsta += (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.W #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0c7b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_0c80_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c90_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_0c98_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ca8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (10);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cba_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc() + 6;
+	dsta += (uae_s32)(uae_s16)get_iiword_jit (6);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CMP.L #.L,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cbb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (6);
+{	tmppc = m68k_getpc();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cd0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (4);
+		op_unimpl (opcode);
+		goto l_400267;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpc (4);
+l_400267: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cd8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) -= 2;
+	m68k_incpc (4);
+		op_unimpl (opcode);
+		goto l_400268;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpc (4);
+l_400268: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ce0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 14; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) += 2;
+	m68k_incpc (4);
+		op_unimpl (opcode);
+		goto l_400269;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpc (4);
+l_400269: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ce8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (6);
+		op_unimpl (opcode);
+		goto l_400270;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpc (6);
+l_400270: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		op_unimpl (opcode);
+		goto l_400271;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}}l_400271: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (6);
+		op_unimpl (opcode);
+		goto l_400272;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpc (6);
+l_400272: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cf9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s16 dst = x_get_word (dsta);
+	if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (8);
+		op_unimpl (opcode);
+		goto l_400273;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, rc))) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_word (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_word (dsta, dst);
+		m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
+}}}}}}}}	m68k_incpc (8);
+l_400273: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS2.W #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0cfc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 extra;
+	extra = get_iilong_jit (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u16 dst1 = x_get_word (rn1), dst2 = x_get_word (rn2);
+{uae_u32 newv = ((uae_u16)(dst1)) - ((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s16)(dst1)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u16)(dst2)) - ((uae_u16)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s16)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s16)(dst2)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(m68k_dreg (regs, extra & 7))) > ((uae_u16)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	x_put_word (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	x_put_word (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);
+	m68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);
+	}
+}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e10_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400275; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpc (4);
+l_400275: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e18_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400276; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpc (4);
+l_400276: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e20_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_400277; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpc (4);
+l_400277: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e28_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400278; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpc (6);
+l_400278: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e30_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400279; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	x_put_byte (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpc (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}}l_400279: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e38_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400280; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpc (6);
+l_400280: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.B #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e39_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400281; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	x_put_byte (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_iilong_jit (4);
+{	uae_s8 src = x_get_byte (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
+	}
+}}}}}}	m68k_incpc (8);
+l_400281: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e50_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400282; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpc (4);
+l_400282: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e58_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400283; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, dstreg) += 2;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpc (4);
+l_400283: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e60_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_400284; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpc (4);
+l_400284: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e68_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400285; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpc (6);
+l_400285: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e70_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400286; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	x_put_word (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpc (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}}l_400286: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e78_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400287; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpc (6);
+l_400287: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.W #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e79_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400288; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	x_put_word (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_iilong_jit (4);
+{	uae_s16 src = x_get_word (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (m68k_dreg (regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
+	}
+}}}}}}	m68k_incpc (8);
+l_400288: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e90_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_400289; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpc (4);
+l_400289: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0e98_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_400290; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, dstreg) += 4;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpc (4);
+l_400290: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ea0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 20; 
+{if (!regs.s) { Exception (8); goto l_400291; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, dstreg) = srca;
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpc (4);
+l_400291: ;
+return 20 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ea8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_400292; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpc (6);
+l_400292: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_400293; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	x_put_long (dsta, src);
+}}}else{{	uaecptr srca;
+	m68k_incpc (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}}l_400293: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_400294; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpc (6);
+l_400294: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVES.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0eb9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 103;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_400295; }
+{{	uae_s16 extra = get_iiword_jit (2);
+	if (extra & 0x800)
+{	uae_u32 src = regs.regs[(extra >> 12) & 15];
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	x_put_long (dsta, src);
+}}else{{	uaecptr srca;
+	srca = get_iilong_jit (4);
+{	uae_s32 src = x_get_long (srca);
+	if (extra & 0x8000) {
+	m68k_areg (regs, (extra >> 12) & 7) = src;
+	} else {
+	m68k_dreg (regs, (extra >> 12) & 7) = (src);
+	}
+}}}}}}	m68k_incpc (8);
+l_400295: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ed0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (4);
+		op_unimpl (opcode);
+		goto l_400296;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpc (4);
+l_400296: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ed8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) -= 4;
+	m68k_incpc (4);
+		op_unimpl (opcode);
+		goto l_400297;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpc (4);
+l_400297: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ee0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 26; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		m68k_areg (regs, dstreg) += 4;
+	m68k_incpc (4);
+		op_unimpl (opcode);
+		goto l_400298;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpc (4);
+l_400298: ;
+return 26 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ee8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s32 dst = x_get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (6);
+		op_unimpl (opcode);
+		goto l_400299;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpc (6);
+l_400299: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+		op_unimpl (opcode);
+		goto l_400300;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}}l_400300: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s32 dst = x_get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (6);
+		op_unimpl (opcode);
+		goto l_400301;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpc (6);
+l_400301: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0ef9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 84;
+	CurrentInstrCycles = 24; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s32 dst = x_get_long (dsta);
+	if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {
+	m68k_incpc (8);
+		op_unimpl (opcode);
+		goto l_400302;
+	}
+{	int ru = (src >> 6) & 7;
+	int rc = src & 7;
+{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg (regs, rc)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, rc))) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, rc))) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+		x_put_long (dsta, (m68k_dreg (regs, ru)));
+	}else{
+		x_put_long (dsta, dst);
+		m68k_dreg(regs, rc) = dst;
+}}}}}}}}	m68k_incpc (8);
+l_400302: ;
+return 24 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CAS2.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_0efc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 85;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 extra;
+	extra = get_iilong_jit (2);
+	uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
+	uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
+	uae_u32 dst1 = x_get_long (rn1), dst2 = x_get_long (rn2);
+{uae_u32 newv = ((uae_u32)(dst1)) - ((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, (extra >> 16) & 7))) < 0;
+	int flgo = ((uae_s32)(dst1)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+{uae_u32 newv = ((uae_u32)(dst2)) - ((uae_u32)(m68k_dreg (regs, extra & 7)));
+{	int flgs = ((uae_s32)(m68k_dreg (regs, extra & 7))) < 0;
+	int flgo = ((uae_s32)(dst2)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(m68k_dreg (regs, extra & 7))) > ((uae_u32)(dst2)));
+	SET_NFLG (flgn != 0);
+	if (GET_ZFLG ()) {
+	x_put_long (rn1, m68k_dreg (regs, (extra >> 22) & 7));
+	x_put_long (rn2, m68k_dreg (regs, (extra >> 6) & 7));
+	}}
+}}}}	if (! GET_ZFLG ()) {
+	m68k_dreg (regs, (extra >> 6) & 7) = dst2;
+	m68k_dreg (regs, (extra >> 22) & 7) = dst1;
+	}
+}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1000_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1010_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1018_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1020_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (2);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1028_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1030_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1038_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1039_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (6);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (4);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1080_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1090_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1098_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10ba_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1100_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1110_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1118_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1120_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1128_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1130_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1138_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1139_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1140_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1150_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1158_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1160_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1168_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1170_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1178_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1179_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1180_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1190_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1198_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11ba_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (10);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (8);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2000_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2008_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2010_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2018_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2020_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2028_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2030_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2038_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2039_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (6);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2040_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2048_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2050_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2058_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2060_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2068_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2070_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2078_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_2079_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_207c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (6);
+}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2080_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2088_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2090_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2098_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20ba_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2100_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2108_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2110_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2118_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2120_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2128_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2130_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2138_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2139_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2140_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2148_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2150_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2158_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2160_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2168_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2170_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2178_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2179_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (8);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2180_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2188_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2190_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2198_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_3
+/* MOVE.L -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21ba_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (2);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (8);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (10);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 16; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (10);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3000_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3008_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3010_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3018_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3020_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (2);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3028_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3030_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3038_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3039_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (6);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3040_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3048_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3050_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3058_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (2);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3060_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (2);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3068_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3070_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3078_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_3079_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (6);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (4);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_307c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (4);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3080_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3088_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3090_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3098_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30ba_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3100_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3108_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3110_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3118_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3120_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3128_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3130_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3138_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3139_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3140_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3148_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3150_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3158_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3160_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3168_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3170_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3178_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3179_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3180_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3188_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3190_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3198_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpc (6);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31ba_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 1);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (2);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (6);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (10);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (8);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4000_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4010_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4018_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4020_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4028_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4030_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4038_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4039_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4040_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4050_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4058_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4060_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4068_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4070_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4078_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4079_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4080_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, srcreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4090_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4098_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40b8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40b9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_40c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_400632; }
+{{	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}}	m68k_incpc (2);
+l_400632: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_400633; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpc (2);
+l_400633: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_40d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_400634; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpc (2);
+l_400634: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{if (!regs.s) { Exception (8); goto l_400635; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpc (2);
+l_400635: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_400636; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpc (4);
+l_400636: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_400637; }
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}}l_400637: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_400638; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpc (4);
+l_400638: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_400639; }
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpc (6);
+l_400639: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CHK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4100_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400640;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400640;
+	}
+}}}l_400640: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4110_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400641;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400641;
+	}
+}}}}l_400641: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (An)+,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4118_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400642;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400642;
+	}
+}}}}l_400642: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L -(An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4120_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400643;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400643;
+	}
+}}}}l_400643: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d16,An),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4128_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400644;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400644;
+	}
+}}}}l_400644: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d8,An,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4130_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400645;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400645;
+	}
+}}}}}l_400645: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (xxx).W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4138_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400646;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400646;
+	}
+}}}}l_400646: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (xxx).L,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4139_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400647;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400647;
+	}
+}}}}l_400647: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d16,PC),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400648;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400648;
+	}
+}}}}l_400648: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L (d8,PC,Xn),Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400649;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400649;
+	}
+}}}}}l_400649: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.L #.L,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_413c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400650;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400650;
+	}
+}}}l_400650: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CHK.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4180_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400651;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400651;
+	}
+}}}l_400651: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4190_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400652;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400652;
+	}
+}}}}l_400652: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4198_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400653;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400653;
+	}
+}}}}l_400653: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (2);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400654;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400654;
+	}
+}}}}l_400654: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400655;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400655;
+	}
+}}}}l_400655: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400656;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400656;
+	}
+}}}}}l_400656: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400657;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400657;
+	}
+}}}}l_400657: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (6);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400658;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400658;
+	}
+}}}}l_400658: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41ba_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400659;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400659;
+	}
+}}}}l_400659: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400660;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400660;
+	}
+}}}}}l_400660: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_400661;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_400661;
+	}
+}}}l_400661: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	m68k_areg (regs, dstreg) = (srca);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4200_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4210_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4218_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4220_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4228_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4230_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4238_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4239_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4240_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4250_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4258_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4260_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4268_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4270_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4278_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4279_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4280_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4290_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4298_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_42b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_42b8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_42b9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVSR2.B (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* NEG.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4400_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_4
+/* NEG.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4410_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4418_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4420_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4428_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4430_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4438_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4439_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4440_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4450_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4458_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4460_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4468_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4470_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4478_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4479_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4480_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4490_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4498_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44b8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44b9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_44c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_44d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_44e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_44f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_44f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B #.B */
+uae_u32 REGPARAM2 CPUFUNC(op_44fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4600_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((dst) & 0xff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4610_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4618_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4620_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4628_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4630_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4638_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4639_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4640_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4650_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4658_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4660_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4668_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4670_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4678_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4679_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4680_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4690_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4698_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46b8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46b9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_46c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_400760; }
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	regs.sr = src;
+	MakeFromSR();
+}}}	m68k_incpc (2);
+l_400760: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400761; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpc (2);
+l_400761: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_46d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400762; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpc (2);
+l_400762: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_400763; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpc (2);
+l_400763: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_46e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400764; }
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpc (4);
+l_400764: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400765; }
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}}l_400765: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_46f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400766; }
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpc (4);
+l_400766: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_46f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400767; }
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpc (6);
+l_400767: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400768; }
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}	m68k_incpc (4);
+l_400768: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400769; }
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+}}}}}l_400769: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_46fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400770; }
+{{	uae_s16 src = get_iiword_jit (2);
+	regs.sr = src;
+	MakeFromSR();
+}}}	m68k_incpc (4);
+l_400770: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4800_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LINK.L An,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4808_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 8;  
+{{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 offs;
+	offs = get_iilong_jit (2);
+	x_put_long (olda, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* NBCD.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4810_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (srca, newv);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4818_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (srca, newv);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4820_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (srca, newv);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4828_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (srca, newv);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4830_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (srca, newv);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4838_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (srca, newv);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4839_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (srca, newv);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SWAP.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4840_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 34;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BKPTQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4848_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 99;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	op_illg (opcode);
+}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PEA.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4850_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4868_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4870_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4878_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4879_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_487a_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_487b_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* EXT.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4880_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u16 dst = (uae_s16)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4890_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iiword_jit (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 6;  
+{	uae_u16 mask = get_iiword_jit (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	int type = get_cpu_model () >= 68020;
+	while (amask) {
+		srca -= 2;
+		if (!type || movem_index2[amask] != dstreg)
+			x_put_word (srca, m68k_areg (regs, movem_index2[amask]));
+		else
+			x_put_word (srca, m68k_areg (regs, movem_index2[amask]) - 2);
+		amask = movem_next[amask];
+	}
+	while (dmask) { srca -= 2; x_put_word (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48a8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iiword_jit (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48b0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iiword_jit (2);
+{	uaecptr srca;
+	m68k_incpc (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48b8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iiword_jit (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48b9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iiword_jit (2);
+{	uaecptr srca;
+	srca = get_iilong_jit (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}	m68k_incpc (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EXT.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_48c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48d0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iiword_jit (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 10; 
+{	uae_u16 mask = get_iiword_jit (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) - 0;
+{	uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
+	int type = get_cpu_model () >= 68020;
+	while (amask) {
+		srca -= 4;
+		if (!type || movem_index2[amask] != dstreg)
+			x_put_long (srca, m68k_areg (regs, movem_index2[amask]));
+		else
+			x_put_long (srca, m68k_areg (regs, movem_index2[amask]) - 4);
+		amask = movem_next[amask];
+	}
+	while (dmask) { srca -= 4; x_put_long (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_48e8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iiword_jit (2);
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48f0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iiword_jit (2);
+{	uaecptr srca;
+	m68k_incpc (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_48f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iiword_jit (2);
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_48f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iiword_jit (2);
+{	uaecptr srca;
+	srca = get_iilong_jit (4);
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXT.B Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_49c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 36;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_u32 dst = (uae_s32)(uae_s8)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	m68k_dreg (regs, srcreg) = (dst);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a00_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a10_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a18_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a20_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a28_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a30_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a38_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a39_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3a_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3b_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.B #.B */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a3c_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_iibyte_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a40_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a48_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a50_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a58_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a60_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a68_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a70_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4a78_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4a79_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7a_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7b_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.W #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a7c_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4a80_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TST.L An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4a88_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a90_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4a98_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4aa8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4aba_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4abb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TST.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4abc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TAS.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4ac0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((src) & 0xff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4af0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4af8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4af9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MULL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c00_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_400847;
+}}}l_400847: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c10_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpc (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_400848;
+}}}}l_400848: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c18_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpc (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_400849;
+}}}}l_400849: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c20_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpc (4);
+	if (!m68k_mull(opcode, dst, extra)) goto l_400850;
+}}}}l_400850: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c28_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpc (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_400851;
+}}}}l_400851: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c30_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_400852;
+}}}}}l_400852: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c38_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpc (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_400853;
+}}}}l_400853: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c39_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpc (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_400854;
+}}}}l_400854: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc() + 4;
+	dsta += (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpc (6);
+	if (!m68k_mull(opcode, dst, extra)) goto l_400855;
+}}}}l_400855: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_mull(opcode, dst, extra)) goto l_400856;
+}}}}}l_400856: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MULL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c3c_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 87;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uae_s32 dst;
+	dst = get_iilong_jit (4);
+	m68k_incpc (8);
+	if (!m68k_mull(opcode, dst, extra)) goto l_400857;
+}}}l_400857: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c40_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_400858;
+}}}l_400858: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c50_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpc (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_400859;
+}}}}l_400859: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c58_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	m68k_incpc (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_400860;
+}}}}l_400860: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c60_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	m68k_incpc (4);
+	if (!m68k_divl(opcode, dst, extra)) goto l_400861;
+}}}}l_400861: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c68_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpc (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_400862;
+}}}}l_400862: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c70_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_400863;
+}}}}}l_400863: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c78_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpc (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_400864;
+}}}}l_400864: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c79_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpc (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_400865;
+}}}}l_400865: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc() + 4;
+	dsta += (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_incpc (6);
+	if (!m68k_divl(opcode, dst, extra)) goto l_400866;
+}}}}l_400866: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 dst = x_get_long (dsta);
+	if (!m68k_divl(opcode, dst, extra)) goto l_400867;
+}}}}}l_400867: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* DIVL.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4c7c_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 86;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uae_s32 dst;
+	dst = get_iilong_jit (4);
+	m68k_incpc (8);
+	if (!m68k_divl(opcode, dst, extra)) goto l_400868;
+}}}l_400868: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MVMEL.W #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4c90_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4c98_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ca8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpc (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_iilong_jit (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (8);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cba_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpc() + 4;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cbb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 4;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4cd8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 12; 
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+	m68k_areg (regs, dstreg) = srca;
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ce8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	m68k_incpc (4);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_iilong_jit (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (8);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = m68k_getpc() + 4;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (4);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 8;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* TRAPQ.L # */
+uae_u32 REGPARAM2 CPUFUNC(op_4e40_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 15);
+	OpcodeFamily = 39;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+	m68k_incpc (2);
+	Exception (src + 32);
+}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* LINK.W An,#.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e50_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 47;
+	CurrentInstrCycles = 8;  
+{{	uaecptr olda;
+	olda = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = olda;
+{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	x_put_long (olda, src);
+	m68k_areg (regs, srcreg) = (m68k_areg (regs, 7));
+	m68k_areg (regs, 7) += offs;
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* UNLK.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e58_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 48;
+	CurrentInstrCycles = 8;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	m68k_areg (regs, 7) = src;
+{	uaecptr olda;
+	olda = m68k_areg (regs, 7);
+{	uae_s32 old = x_get_long (olda);
+	m68k_areg (regs, 7) += 4;
+	m68k_areg (regs, srcreg) = (old);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVR2USP.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e60_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 40;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_400888; }
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+	regs.usp = src;
+}}}	m68k_incpc (2);
+l_400888: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVUSP2R.L An */
+uae_u32 REGPARAM2 CPUFUNC(op_4e68_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 41;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_400889; }
+{{	m68k_areg (regs, srcreg) = (regs.usp);
+}}}	m68k_incpc (2);
+l_400889: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RESET.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e70_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 42;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_400890; }
+{	cpureset ();
+	m68k_incpc (2);
+}}l_400890: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NOP.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e71_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 43;
+	CurrentInstrCycles = 4;  
+{}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* STOP.L #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_4e72_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 44;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400892; }
+{{	uae_s16 src = get_iiword_jit (2);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_setstopped ();
+	m68k_incpc (4);
+}}}l_400892: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RTE.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e73_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 45;
+	CurrentInstrCycles = 16; 
+{if (!regs.s) { Exception (8); goto l_400893; }
+{	uae_u16 newsr; uae_u32 newpc;
+	for (;;) {
+		uaecptr a = m68k_areg (regs, 7);
+		uae_u16 sr = x_get_word (a);
+		uae_u32 pc = x_get_long (a + 2);
+		uae_u16 format = x_get_word (a + 2 + 4);
+		int frame = format >> 12;
+		int offset = 8;
+		newsr = sr; newpc = pc;
+		if (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }
+		else if (frame == 0x1) { m68k_areg (regs, 7) += offset; }
+		else if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }
+		else if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }
+		else if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }
+		else if (frame == 0x7) { m68k_areg (regs, 7) += offset + 52; break; }
+		else if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }
+		else if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }
+		else if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }
+		else { m68k_areg (regs, 7) += offset; Exception (14); goto l_400893; }
+		regs.sr = newsr;
+	MakeFromSR();
+}
+	regs.sr = newsr;
+	MakeFromSR();
+	if (newpc & 1) {
+		exception3i (0x4E73, newpc);
+		goto l_400893;
+	}
+	m68k_setpc (newpc);
+}}l_400893: ;
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* RTD.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e74_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 46;
+	CurrentInstrCycles = 8;  
+{{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = x_get_long (pca);
+	m68k_areg (regs, 7) += 4;
+{	uae_s16 offs = get_iiword_jit (2);
+	m68k_areg (regs, 7) += offs;
+	if (pc & 1) {
+		exception3i (0x4E74, pc);
+		goto l_400894;
+	}
+	m68k_setpc (pc);
+}}}}l_400894: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* RTS.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e75_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 49;
+	CurrentInstrCycles = 8;  
+{	uaecptr pc = m68k_getpc();
+	m68k_do_rtsi_jit ();
+	if (m68k_getpc() & 1) {
+		uaecptr faultpc = m68k_getpc();
+	m68k_setpc (pc);
+		exception3i (0x4E75, faultpc);
+		goto l_400895;
+	}
+}l_400895: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* TRAPV.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e76_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 50;
+	CurrentInstrCycles = 4;  
+{	m68k_incpc (2);
+	if (GET_VFLG ()) {
+		Exception (7);
+		goto l_400896;
+	}
+}l_400896: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RTR.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e77_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 51;
+	CurrentInstrCycles = 12; 
+{	uaecptr oldpc = m68k_getpc();
+	MakeSR ();
+{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+{	uae_s16 sr = x_get_word (sra);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = x_get_long (pca);
+	m68k_areg (regs, 7) += 4;
+	regs.sr &= 0xFF00; sr &= 0xFF;
+	regs.sr |= sr;
+	m68k_setpc (pc);
+	MakeFromSR();
+	if (m68k_getpc() & 1) {
+		uaecptr faultpc = m68k_getpc();
+	m68k_setpc (oldpc);
+		exception3i (0x4E77, faultpc);
+		goto l_400897;
+	}
+}}}}}l_400897: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEC2.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7a_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 82;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400898; }
+{{	uae_s16 src = get_iiword_jit (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_movec2(src & 0xFFF, regp)) goto l_400898;
+}}}}	m68k_incpc (4);
+l_400898: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE2C.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_4e7b_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 83;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_400899; }
+{{	uae_s16 src = get_iiword_jit (2);
+{	int regno = (src >> 12) & 15;
+	uae_u32 *regp = regs.regs + regno;
+	if (! m68k_move2c(src & 0xFFF, regp)) goto l_400899;
+}}}}	m68k_incpc (4);
+l_400899: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* JSR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4e90_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uaecptr oldpc = m68k_getpc() + 2;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_400900;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}l_400900: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ea8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uaecptr oldpc = m68k_getpc() + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_400901;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}l_400901: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uaecptr oldpc = m68k_getpc() + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_400902;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}}l_400902: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uaecptr oldpc = m68k_getpc() + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_400903;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}l_400903: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uaecptr oldpc = m68k_getpc() + 6;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_400904;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}l_400904: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eba_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uaecptr oldpc = m68k_getpc() + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_400905;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}l_400905: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ebb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uaecptr oldpc = m68k_getpc() + 0;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_400906;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}}l_400906: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ed0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_400907;
+	}
+	m68k_setpc (srca);
+}}l_400907: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ee8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_400908;
+	}
+	m68k_setpc (srca);
+}}l_400908: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_400909;
+	}
+	m68k_setpc (srca);
+}}}l_400909: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_400910;
+	}
+	m68k_setpc (srca);
+}}l_400910: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_400911;
+	}
+	m68k_setpc (srca);
+}}l_400911: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d16,PC) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_400912;
+	}
+	m68k_setpc (srca);
+}}l_400912: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_400913;
+	}
+	m68k_setpc (srca);
+}}}l_400913: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5000_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5010_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5018_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5020_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5028_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5030_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5038_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5039_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5040_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5048_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5050_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5058_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5060_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5068_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5070_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5078_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5079_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5080_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5088_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5090_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5098_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_5
+/* ADDQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_50a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_50b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_50b8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_50b9_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (0) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (0)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_400941;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_400941: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (0)) { Exception (7); goto l_400949; }
+}}	m68k_incpc (4);
+l_400949: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (0)) { Exception (7); goto l_400950; }
+}}	m68k_incpc (6);
+l_400950: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (T) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_50fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (0)) { Exception (7); goto l_400951; }
+}	m68k_incpc (2);
+l_400951: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* SUBQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5100_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5110_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5118_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5120_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5128_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5130_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5138_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5139_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5140_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBAQ.W #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5148_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5150_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5158_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5160_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5168_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5170_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_5178_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_5179_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_5180_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBAQ.L #,An */
+uae_u32 REGPARAM2 CPUFUNC(op_5188_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_5190_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_5198_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_51a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_51b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_51b8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_51b9_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (1) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (1)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_400979;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_400979: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (1)) { Exception (7); goto l_400987; }
+}}	m68k_incpc (4);
+l_400987: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (1)) { Exception (7); goto l_400988; }
+}}	m68k_incpc (6);
+l_400988: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (F) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_51fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (1)) { Exception (7); goto l_400989; }
+}	m68k_incpc (2);
+l_400989: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (2) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (2)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_400991;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_400991: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (2)) { Exception (7); goto l_400999; }
+}}	m68k_incpc (4);
+l_400999: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (2)) { Exception (7); goto l_401000; }
+}}	m68k_incpc (6);
+l_401000: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (HI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_52fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (2)) { Exception (7); goto l_401001; }
+}	m68k_incpc (2);
+l_401001: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (3) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (3)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_401003;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_401003: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (3)) { Exception (7); goto l_401011; }
+}}	m68k_incpc (4);
+l_401011: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (3)) { Exception (7); goto l_401012; }
+}}	m68k_incpc (6);
+l_401012: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_53fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (3)) { Exception (7); goto l_401013; }
+}	m68k_incpc (2);
+l_401013: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (4) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (4)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_401015;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_401015: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (4)) { Exception (7); goto l_401023; }
+}}	m68k_incpc (4);
+l_401023: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (4)) { Exception (7); goto l_401024; }
+}}	m68k_incpc (6);
+l_401024: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (CC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_54fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (4)) { Exception (7); goto l_401025; }
+}	m68k_incpc (2);
+l_401025: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (5) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (5)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_401027;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_401027: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (5)) { Exception (7); goto l_401035; }
+}}	m68k_incpc (4);
+l_401035: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (5)) { Exception (7); goto l_401036; }
+}}	m68k_incpc (6);
+l_401036: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (CS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_55fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (5)) { Exception (7); goto l_401037; }
+}	m68k_incpc (2);
+l_401037: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (6) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (6)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_401039;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_401039: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (6)) { Exception (7); goto l_401047; }
+}}	m68k_incpc (4);
+l_401047: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (6)) { Exception (7); goto l_401048; }
+}}	m68k_incpc (6);
+l_401048: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (NE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_56fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (6)) { Exception (7); goto l_401049; }
+}	m68k_incpc (2);
+l_401049: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (7) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (7)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_401051;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_401051: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (7)) { Exception (7); goto l_401059; }
+}}	m68k_incpc (4);
+l_401059: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (7)) { Exception (7); goto l_401060; }
+}}	m68k_incpc (6);
+l_401060: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (EQ) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_57fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (7)) { Exception (7); goto l_401061; }
+}	m68k_incpc (2);
+l_401061: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (8) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (8)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_401063;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_401063: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (8)) { Exception (7); goto l_401071; }
+}}	m68k_incpc (4);
+l_401071: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (8)) { Exception (7); goto l_401072; }
+}}	m68k_incpc (6);
+l_401072: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (VC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_58fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (8)) { Exception (7); goto l_401073; }
+}	m68k_incpc (2);
+l_401073: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (9) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (9)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_401075;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_401075: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (9)) { Exception (7); goto l_401083; }
+}}	m68k_incpc (4);
+l_401083: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (9)) { Exception (7); goto l_401084; }
+}}	m68k_incpc (6);
+l_401084: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (VS) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_59fc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (9)) { Exception (7); goto l_401085; }
+}	m68k_incpc (2);
+l_401085: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (10) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (10)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_401087;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_401087: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (10)) { Exception (7); goto l_401095; }
+}}	m68k_incpc (4);
+l_401095: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (10)) { Exception (7); goto l_401096; }
+}}	m68k_incpc (6);
+l_401096: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (PL) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5afc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (10)) { Exception (7); goto l_401097; }
+}	m68k_incpc (2);
+l_401097: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (11) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (11)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_401099;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_401099: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (11)) { Exception (7); goto l_401107; }
+}}	m68k_incpc (4);
+l_401107: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (11)) { Exception (7); goto l_401108; }
+}}	m68k_incpc (6);
+l_401108: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (MI) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5bfc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (11)) { Exception (7); goto l_401109; }
+}	m68k_incpc (2);
+l_401109: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (12) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (12)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_401111;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_401111: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (12)) { Exception (7); goto l_401119; }
+}}	m68k_incpc (4);
+l_401119: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (12)) { Exception (7); goto l_401120; }
+}}	m68k_incpc (6);
+l_401120: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (GE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5cfc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (12)) { Exception (7); goto l_401121; }
+}	m68k_incpc (2);
+l_401121: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (13) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (13)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_401123;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_401123: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (13)) { Exception (7); goto l_401131; }
+}}	m68k_incpc (4);
+l_401131: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (13)) { Exception (7); goto l_401132; }
+}}	m68k_incpc (6);
+l_401132: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5dfc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (13)) { Exception (7); goto l_401133; }
+}	m68k_incpc (2);
+l_401133: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (14) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (14)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_401135;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_401135: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (14)) { Exception (7); goto l_401143; }
+}}	m68k_incpc (4);
+l_401143: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (14)) { Exception (7); goto l_401144; }
+}}	m68k_incpc (6);
+l_401144: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (GT) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5efc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (14)) { Exception (7); goto l_401145; }
+}	m68k_incpc (2);
+l_401145: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Scc.B Dn (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{{{	int val = cctrue (15) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DBcc.W Dn,#.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 58;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 offs = get_iiword_jit (2);
+	uaecptr oldpc = m68k_getpc();
+	if (!cctrue (15)) {
+	m68k_incpc ((uae_s32)offs + 2);
+			m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
+		if (src) {
+			if (offs & 1) {
+				exception3i (opcode, m68k_getpc() + 2 + (uae_s32)offs + 2);
+				goto l_401147;
+			}
+			return 8 * CYCLE_UNIT / 2;
+		}
+	} else {
+	}
+	m68k_setpc (oldpc + 4);
+}}}l_401147: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TRAPcc.L #.W (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffa_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 dummy = get_iiword_jit (2);
+	if (cctrue (15)) { Exception (7); goto l_401155; }
+}}	m68k_incpc (4);
+l_401155: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L #.L (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffb_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 dummy;
+	dummy = get_iilong_jit (2);
+	if (cctrue (15)) { Exception (7); goto l_401156; }
+}}	m68k_incpc (6);
+l_401156: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* TRAPcc.L  (LE) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_5ffc_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 102;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (15)) { Exception (7); goto l_401157; }
+}	m68k_incpc (2);
+l_401157: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* Bcc.W #.W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6000_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401158;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401158: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_6001_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401159;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401159: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_60ff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (0)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401160;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401160: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BSR.W #.W */
+uae_u32 REGPARAM2 CPUFUNC(op_6100_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_s16 src = get_iiword_jit (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpc() + s, 0, 1, m68k_getpc() + s);
+		goto l_401161;
+	}
+	m68k_do_bsri_jit (m68k_getpc() + 4, s);
+}}l_401161: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSRQ.B # */
+uae_u32 REGPARAM2 CPUFUNC(op_6101_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_u32 src = srcreg;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpc() + s, 0, 1, m68k_getpc() + s);
+		goto l_401162;
+	}
+	m68k_do_bsri_jit (m68k_getpc() + 2, s);
+}}l_401162: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSR.L #.L */
+uae_u32 REGPARAM2 CPUFUNC(op_61ff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+{	uae_s32 src;
+	src = get_iilong_jit (2);
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpc() + s, 0, 1, m68k_getpc() + s);
+		goto l_401163;
+	}
+	m68k_do_bsri_jit (m68k_getpc() + 6, s);
+}}l_401163: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6200_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401164;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401164: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6201_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401165;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401165: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_62ff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (2)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401166;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401166: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6300_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401167;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401167: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6301_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401168;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401168: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_6
+/* Bcc.L #.L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_63ff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (3)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401169;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401169: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6400_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401170;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401170: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6401_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401171;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401171: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_64ff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (4)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401172;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401172: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6500_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401173;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401173: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6501_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401174;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401174: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_65ff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (5)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401175;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401175: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6600_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401176;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401176: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6601_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401177;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401177: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_66ff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (6)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401178;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401178: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6700_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401179;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401179: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_6701_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401180;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401180: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_67ff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (7)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401181;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401181: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6800_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401182;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401182: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_6801_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401183;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401183: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_68ff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (8)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401184;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401184: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6900_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401185;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401185: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_6901_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401186;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401186: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_69ff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (9)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401187;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401187: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a00_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401188;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401188: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6a01_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401189;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401189: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6aff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (10)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401190;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401190: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b00_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401191;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401191: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6b01_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401192;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401192: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6bff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (11)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401193;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401193: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c00_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401194;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401194: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6c01_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401195;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401195: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6cff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (12)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401196;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401196: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d00_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401197;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401197: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6d01_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401198;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401198: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6dff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (13)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401199;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401199: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e00_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401200;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401200: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6e01_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401201;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401201: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6eff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (14)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401202;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401202: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.W #.W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f00_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 src = get_iiword_jit (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401203;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (4);
+}}l_401203: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* BccQ.B # (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6f01_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 8;  
+{{	uae_u32 src = srcreg;
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401204;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (2);
+}}l_401204: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6fff_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+	if (!cctrue (15)) goto didnt_jump;
+	if (src & 1) {
+		exception3i (opcode, m68k_getpc() + 2 + (uae_s32)src);
+		goto l_401205;
+	}
+	m68k_incpc ((uae_s32)src + 2);
+	return 10 * CYCLE_UNIT / 2;
+didnt_jump:;
+	m68k_incpc (6);
+}}l_401205: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVEQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_7000_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (uae_s32)(uae_s8)(opcode & 255);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 src = srcreg;
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (2);
+}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8000_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8010_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8018_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8020_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8028_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8030_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8038_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8039_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8040_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8050_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8058_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8060_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8068_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8070_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8078_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8079_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8080_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8090_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8098_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80ba_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 110;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_401240;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (2);
+	}
+}}}l_401240: ;
+return 110 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_401241;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (2);
+	}
+}}}}l_401241: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_401242;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (2);
+	}
+}}}}l_401242: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_401243;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (2);
+	}
+}}}}l_401243: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_401244;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (4);
+	}
+}}}}l_401244: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (0);
+		Exception (5);
+		goto l_401245;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_401245: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_401246;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (4);
+	}
+}}}}l_401246: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (6);
+		Exception (5);
+		goto l_401247;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (6);
+	}
+}}}}l_401247: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_401248;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (4);
+	}
+}}}}l_401248: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (0);
+		Exception (5);
+		goto l_401249;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_401249: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 114;
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+		divbyzero_special (0, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_401250;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (4);
+	}
+}}}l_401250: ;
+return 114 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8100_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8108_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8110_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8118_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8120_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8128_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8130_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8138_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8139_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* PACK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8140_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val = m68k_dreg (regs, srcreg) + get_iiword_jit (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);
+}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PACK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8148_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 96;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val;
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff);
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (val | ((uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff) << 8)) + get_iiword_jit (2);
+	m68k_areg (regs, dstreg) -= areg_byteinc[dstreg];
+	x_put_byte (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));
+}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* OR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8150_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8158_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8160_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8168_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8170_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_8178_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_8179_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* UNPK.L Dn,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8180_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val = m68k_dreg (regs, srcreg);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_iiword_jit (2);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);
+}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* UNPK.L -(An),-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_8188_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 97;
+	CurrentInstrCycles = 8;  
+{	uae_u16 val;
+	m68k_areg (regs, srcreg) -= areg_byteinc[srcreg];
+	val = (uae_u16)(x_get_byte (m68k_areg (regs, srcreg)) & 0xff);
+	val = (((val << 4) & 0xf00) | (val & 0xf)) + get_iiword_jit (2);
+	m68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];
+	x_put_byte (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);
+	x_put_byte (m68k_areg (regs, dstreg), val >> 8);
+}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* OR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8190_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_8198_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_81a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_81b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_81b8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_81b9_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 142;
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_401278;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (2);
+}}}l_401278: ;
+return 142 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_401279;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (2);
+}}}}l_401279: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_401280;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (2);
+}}}}l_401280: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (2);
+		Exception (5);
+		goto l_401281;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (2);
+}}}}l_401281: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_401282;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (4);
+}}}}l_401282: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (0);
+		Exception (5);
+		goto l_401283;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_401283: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_401284;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (4);
+}}}}l_401284: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (6);
+		Exception (5);
+		goto l_401285;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (6);
+}}}}l_401285: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_401286;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (4);
+}}}}l_401286: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (0);
+		Exception (5);
+		goto l_401287;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+}}}}}l_401287: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 146;
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+		divbyzero_special (1, dst);
+	m68k_incpc (4);
+		Exception (5);
+		goto l_401288;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (4);
+}}}l_401288: ;
+return 146 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9000_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9010_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9018_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9020_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9028_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9030_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9038_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9039_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9040_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9048_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9050_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9058_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9060_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9068_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9070_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9078_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9079_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9080_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9088_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9090_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9098_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90ba_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9100_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9108_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9110_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9118_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9120_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9128_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9130_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9138_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9139_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9140_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9148_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9150_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9158_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9160_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9168_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9170_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_9178_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_9179_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9180_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9188_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 9;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 26 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_9190_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_9198_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_91a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_91b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_91b8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_91b9_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b000_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b010_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b018_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b020_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b028_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b030_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b038_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b039_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b040_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b048_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b050_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b058_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b060_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b068_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b070_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b078_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b079_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b080_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b088_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b090_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b098_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_7
+/* CMP.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0ba_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b100_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.B (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b108_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b110_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b118_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b120_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b128_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b130_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b138_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b139_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b140_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.W (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b148_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b150_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b158_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b160_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b168_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b170_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b178_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b179_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b180_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPM.L (An)+,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b188_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 26;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b190_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_b198_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b9_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c000_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c010_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c018_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c020_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c028_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c030_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c038_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c039_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c040_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c050_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c058_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c060_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c068_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c070_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c078_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c079_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c080_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c090_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c098_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0ba_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 58; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (2);
+}}}}return 58 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (2);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (2);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 40; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (2);
+}}}}}return 40 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (4);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (4);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (6);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (4);
+}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 38; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 62; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (4);
+}}}}return 62 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c100_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c108_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c110_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c118_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c120_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c128_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c130_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c138_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c139_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c140_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_dreg (regs, dstreg) = (src);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c148_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	m68k_areg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c150_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c158_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c160_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c168_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c170_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c178_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c179_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EXG.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_c188_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 35;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+	m68k_dreg (regs, srcreg) = (dst);
+	m68k_areg (regs, dstreg) = (src);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c190_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_c198_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b9_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 58; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 58 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 40; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 40 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (6);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 38; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}return 38 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 62; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (4);
+return 62 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d000_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d010_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d018_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d020_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d028_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d030_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d038_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d039_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d040_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d048_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d050_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d058_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d060_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (2);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d068_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d070_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d078_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d079_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (6);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}}return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07c_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d080_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L An,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d088_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d090_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (An)+,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d098_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L -(An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d16,An),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (xxx).W,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (xxx).L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d16,PC),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0ba_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W #.W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d100_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d108_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d110_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d118_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d120_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d128_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d130_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d138_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d139_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d140_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.W -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d148_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d150_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d158_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) += 2;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d160_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+{	uae_s16 dst = x_get_word (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d168_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d170_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d178_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d179_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d180_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDX.L -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d188_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 13;
+	CurrentInstrCycles = 26; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 26 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d190_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_d198_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) += 4;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+{	uae_s32 dst = x_get_long (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	m68k_incpc (2);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}}return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b9_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 16; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (2);
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L Dn,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L An,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (An)+,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L -(An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d16,An),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (xxx).W,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (xxx).L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f9_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d16,PC),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	m68k_incpc (2);
+{	tmppc = m68k_getpc();
+	srca = x_get_disp_ea_020 (tmppc, 0);
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L #.L,An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fc_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e000_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e008_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e010_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e018_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e020_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	uae_u32 sign = (0x80 & val) >> 7;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		val = 0xff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xff << (8 - cnt)) & (uae_u32)-sign;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e028_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG ((cnt == 8) & (val >> 7));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e030_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (7 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e038_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 7;
+	hival = val << (8 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xff;
+	SET_CFLG ((val & 0x80) >> 7);
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e040_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_8
+/* LSRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e048_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e050_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e058_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e060_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = (0x8000 & val) >> 15;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		val = 0xffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffff << (16 - cnt)) & (uae_u32)-sign;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e068_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG ((cnt == 16) & (val >> 15));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e070_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (15 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e078_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 15;
+	hival = val << (16 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffff;
+	SET_CFLG ((val & 0x8000) >> 15);
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e080_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e088_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXRQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e090_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* RORQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e098_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 64;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	uae_u32 sign = (0x80000000 & val) >> 31;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		val = 0xffffffff & (uae_u32)-sign;
+		SET_CFLG (sign);
+		COPY_CARRY ();
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+		val |= (0xffffffff << (32 - cnt)) & (uae_u32)-sign;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 66;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG ((cnt == 32) & (val >> 31));
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val >>= cnt - 1;
+		SET_CFLG (val & 1);
+		COPY_CARRY ();
+		val >>= 1;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 71;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 hival = (val << 1) | GET_XFLG ();
+	hival <<= (31 - cnt);
+	val >>= cnt;
+	carry = val & 1;
+	val >>= 1;
+	val |= hival;
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROR.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e0b8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 69;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {	uae_u32 hival;
+	cnt &= 31;
+	hival = val << (32 - cnt);
+	val >>= cnt;
+	val |= hival;
+	val &= 0xffffffff;
+	SET_CFLG ((val & 0x80000000) >> 31);
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e0d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_iilong_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e100_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e108_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e110_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.B #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e118_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e120_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e128_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 8) {
+		SET_CFLG (cnt == 8 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80) >> 7);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xff;
+	}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e130_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 36) cnt -= 36;
+	if (cnt >= 18) cnt -= 18;
+	if (cnt >= 9) cnt -= 9;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (7 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e138_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 cnt = m68k_dreg (regs, srcreg);
+{	uae_s8 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u8)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 7;
+	loval = val >> (8 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s8)(val)) == 0);
+	SET_NFLG (((uae_s8)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e140_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e148_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e150_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.W #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e158_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e160_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e168_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 16) {
+		SET_CFLG (cnt == 16 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x8000) >> 15);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffff;
+	}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e170_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 34) cnt -= 34;
+	if (cnt >= 17) cnt -= 17;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (15 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.W Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e178_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 cnt = m68k_dreg (regs, srcreg);
+{	uae_s16 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = (uae_u16)data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 15;
+	loval = val >> (16 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((val) & 0xffff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e180_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e188_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e190_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROLQ.L #,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e198_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_u32 cnt = srcreg;
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+{	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 65;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_VFLG (val != 0);
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
+		SET_VFLG ((val & mask) != mask && (val & mask) != 0);
+		val <<= cnt - 1;
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+		val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* LSL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1a8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 67;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 32) {
+		SET_CFLG (cnt == 32 ? val & 1 : 0);
+		COPY_CARRY ();
+		val = 0;
+	} else if (cnt > 0) {
+		val <<= (cnt - 1);
+		SET_CFLG ((val & 0x80000000) >> 31);
+		COPY_CARRY ();
+		val <<= 1;
+	val &= 0xffffffff;
+	}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROXL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 70;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt >= 33) cnt -= 33;
+	if (cnt > 0) {
+	cnt--;
+	{
+	uae_u32 carry;
+	uae_u32 loval = val >> (31 - cnt);
+	carry = loval & 1;
+	val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);
+	SET_XFLG (carry);
+	val &= 0xffffffff;
+	} }
+	SET_CFLG (GET_XFLG ());
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ROL.L Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_e1b8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 68;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 cnt = m68k_dreg (regs, srcreg);
+{	uae_s32 data = m68k_dreg (regs, dstreg);
+{	uae_u32 val = data;
+	int ccnt = cnt & 63;
+	cnt &= 63;
+	CLEAR_CZNV ();
+	if (cnt > 0) {
+	uae_u32 loval;
+	cnt &= 31;
+	loval = val >> (32 - cnt);
+	val <<= cnt;
+	val |= loval;
+	val &= 0xffffffff;
+	SET_CFLG (val & 1);
+}
+	SET_ZFLG (((uae_s32)(val)) == 0);
+	SET_NFLG (((uae_s32)(val)) < 0);
+	m68k_dreg (regs, dstreg) = (val);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e1d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_iilong_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e2d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_iilong_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e3d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_iilong_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e4d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_iilong_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e5d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_iilong_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e6d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_iilong_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_e7d8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg);
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) += 2;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 data = x_get_word (dataa);
+	m68k_areg (regs, srcreg) = dataa;
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7e8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	m68k_incpc (2);
+{	dataa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 8;  
+{{	uaecptr dataa;
+	dataa = get_iilong_jit (2);
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* BFTST.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8c0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8d0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8e8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc() + 4;
+	dsta += (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFTST.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e8fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 88;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9c0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9d0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9e8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9f9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9fa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc() + 4;
+	dsta += (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTU.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_e9fb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 89;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eac0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ead0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eae8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCHG.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eaf9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 90;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = tmp ^ (0xffffffffu >> (32 - width));
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebc0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebd0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebe8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebf9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebfa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc() + 4;
+	dsta += (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFEXTS.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ebfb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 91;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp = (uae_s32)tmp >> (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	m68k_dreg (regs, (extra >> 12) & 7) = tmp;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecc0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecd0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ece8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFCLR.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ecf9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 92;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0;
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edc0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edd0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_ede8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edf9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edfa_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_getpc() + 4;
+	dsta += (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFFFO.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_edfb_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 93;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	m68k_incpc (4);
+{	tmppc = m68k_getpc();
+	dsta = x_get_disp_ea_020 (tmppc, 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	{ uae_u32 mask = 1 << (width - 1);
+	while (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}
+	m68k_dreg (regs, (extra >> 12) & 7) = offset;
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eec0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eed0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eee8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFSET.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eef9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 94;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = 0xffffffffu >> (32 - width);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efc0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp = m68k_dreg(regs, dstreg);
+	offset &= 0x1f;
+	tmp = (tmp << offset) | (tmp >> (32 - offset));
+	bdata[0] = tmp & ((1 << (32 - width)) - 1);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	tmp = bdata[0] | (tmp << (32 - width));
+	m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efd0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 8;  
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_efe8_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff0_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	m68k_incpc (4);
+{	dsta = x_get_disp_ea_020 (m68k_areg (regs, dstreg), 0);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff8_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 12; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* BFINS.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_eff9_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 95;
+	CurrentInstrCycles = 16; 
+{{	uae_s16 extra = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+{	uae_u32 bdata[2];
+	uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
+	int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;
+	uae_u32 tmp;
+	dsta += offset >> 3;
+	tmp = x_get_bitfield (dsta, bdata, offset, width);
+	SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);
+	tmp >>= (32 - width);
+	SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);
+	tmp = m68k_dreg (regs, (extra >> 12) & 7);
+	tmp = tmp & (0xffffffffu >> (32 - width));
+	SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);
+	SET_ZFLG (tmp == 0);
+	x_put_bitfield(dsta, bdata, tmp, offset, width);
+}}}}	m68k_incpc (8);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L Dn,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f000_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401788; }
+{	uaecptr pc = m68k_getpc();
+	uae_u16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	uae_u16 extraa = 0;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}l_401788: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L An,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f008_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401789; }
+{	uaecptr pc = m68k_getpc();
+	uae_u16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	uae_u16 extraa = 0;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}l_401789: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f010_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401790; }
+{	uaecptr pc = m68k_getpc();
+	uae_u16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_401790: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (An)+,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f018_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401791; }
+{	uaecptr pc = m68k_getpc();
+	uae_u16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 4;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_401791: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L -(An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f020_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 6;  
+{if (!regs.s) { Exception (8); goto l_401792; }
+{	uaecptr pc = m68k_getpc();
+	uae_u16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) - 4;
+	m68k_areg (regs, srcreg) = extraa;
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_401792: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (d16,An),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f028_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_401793; }
+{	uaecptr pc = m68k_getpc();
+	uae_u16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+{	uaecptr extraa;
+	extraa = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (0);
+	m68k_incpc (2);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_401793: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (d8,An,Xn),#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f030_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_401794; }
+{	uaecptr pc = m68k_getpc();
+	uae_u16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+{	uaecptr extraa;
+{	extraa = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}}l_401794: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (xxx).W,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f038_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 8;  
+{if (!regs.s) { Exception (8); goto l_401795; }
+{	uaecptr pc = m68k_getpc();
+	uae_u16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+{	uaecptr extraa;
+	extraa = (uae_s32)(uae_s16)get_iiword_jit (0);
+	m68k_incpc (2);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_401795: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MMUOP030.L (xxx).L,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f039_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 118;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_401796; }
+{	uaecptr pc = m68k_getpc();
+	uae_u16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+{	uaecptr extraa;
+	extraa = get_iilong_jit (0);
+	m68k_incpc (4);
+	mmu_op30 (pc, opcode, extra, extraa);
+}}}l_401796: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f200_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f208_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f210_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f218_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f220_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f228_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f230_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f238_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f239_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23a_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 2;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,(d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23b_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FPP.L #.W,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f23c_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 104;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_arithmetic(opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f240_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FDBcc.L #.W,Dn */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f248_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 105;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_dbcc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f250_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f258_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,-(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f260_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f268_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f270_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f278_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FScc.L #.W,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f279_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 106;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+{	uae_s16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_scc (opcode, extra);
+}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27a_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 12; 
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpc();
+	uae_u16 extra = get_iiword_jit (2);
+{	uae_s16 dummy = get_iiword_jit (4);
+	m68k_incpc (6);
+	fpuop_trapcc (opcode, oldpc, extra);
+}
+#endif
+}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L #.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27b_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 16; 
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpc();
+	uae_u16 extra = get_iiword_jit (2);
+{	uae_s32 dummy;
+	dummy = get_iilong_jit (4);
+	m68k_incpc (8);
+	fpuop_trapcc (opcode, oldpc, extra);
+}
+#endif
+}return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FTRAPcc.L  */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f27c_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 107;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+	uaecptr oldpc = m68k_getpc();
+	uae_u16 extra = get_iiword_jit (2);
+	m68k_incpc (4);
+	fpuop_trapcc (opcode, oldpc, extra);
+
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FBccQ.L #,#.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f280_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+	CurrentInstrCycles = 8;  
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+{	uaecptr pc = m68k_getpc();
+{	uae_s16 extra = get_iiword_jit (0);
+	m68k_incpc (2);
+	fpuop_bcc (opcode, pc,extra);
+}}
+#endif
+}return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FBccQ.L #,#.L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f2c0_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 63);
+	OpcodeFamily = 108;
+	CurrentInstrCycles = 12; 
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+{	uaecptr pc = m68k_getpc();
+{	uae_s32 extra;
+	extra = get_iilong_jit (0);
+	m68k_incpc (4);
+	fpuop_bcc (opcode, pc,extra);
+}}
+#endif
+}return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f310_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401823; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_401823: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L -(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f320_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401824; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_401824: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f328_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401825; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_401825: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f330_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401826; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_401826: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f338_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401827; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_401827: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FSAVE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f339_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 109;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401828; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_save (opcode);
+
+#endif
+}}l_401828: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f350_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401829; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_401829: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f358_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401830; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_401830: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d16,An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f368_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401831; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_401831: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f370_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401832; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_401832: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (xxx).W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f378_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401833; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_401833: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f379_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401834; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_401834: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d16,PC) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f37a_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401835; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_401835: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* FRESTORE.L (d8,PC,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f37b_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 110;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401836; }
+{
+#ifdef FPUEMU
+	m68k_incpc (2);
+	fpuop_restore (opcode);
+
+#endif
+}}l_401836: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVLQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f408_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 111;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401837; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401837: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVPQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f410_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 112;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401838; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401838: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f418_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401839; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401839: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f419_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401840; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401840: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41a_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401841; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401841: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41b_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401842; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401842: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41c_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401843; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401843: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41d_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401844; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401844: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41e_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401845; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401845: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CINVAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f41f_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 113;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401846; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401846: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHLQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f428_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 114;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401847; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401847: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHPQ.L #,An */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f430_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 115;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401848; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401848: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f438_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401849; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401849: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f439_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401850; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401850: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43a_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401851; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401851: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43b_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401852; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401852: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43c_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401853; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401853: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43d_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401854; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401854: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43e_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401855; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401855: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* CPUSHAQ.L # */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f43f_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 6) & 3);
+	OpcodeFamily = 116;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401856; }
+{	flush_cpu_caches_040(opcode);
+	if (opcode & 0x80)
+		flush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);
+}}	m68k_incpc (2);
+l_401856: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSHN.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f500_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 119;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401857; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_401857: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSH.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f508_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 120;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401858; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_401858: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSHAN.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f510_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 121;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401859; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_401859: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PFLUSHA.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f518_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 122;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401860; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_401860: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PTESTW.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f548_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 126;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401861; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_401861: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PTESTR.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f568_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 125;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401862; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_401862: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PLPAW.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f588_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 124;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401863; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_401863: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* PLPAR.L (An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f5c8_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 123;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401864; }
+{	m68k_incpc (2);
+	mmu_op (opcode, 0);
+}}l_401864: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (An)+,(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f600_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = m68k_areg (regs, srcreg);
+{	uaecptr memda;
+	memda = get_iilong_jit (2);
+	memsa &= ~15;
+	memda &= ~15;
+	v[0] = x_get_long (memsa);
+	v[1] = x_get_long (memsa + 4);
+	v[2] = x_get_long (memsa + 8);
+	v[3] = x_get_long (memsa + 12);
+	x_put_long (memda , v[0]);
+	x_put_long (memda + 4, v[1]);
+	x_put_long (memda + 8, v[2]);
+	x_put_long (memda + 12, v[3]);
+	m68k_areg (regs, srcreg) += 16;
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (xxx).L,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f608_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = get_iilong_jit (2);
+{	uaecptr memda;
+	memda = m68k_areg (regs, dstreg);
+	memsa &= ~15;
+	memda &= ~15;
+	v[0] = x_get_long (memsa);
+	v[1] = x_get_long (memsa + 4);
+	v[2] = x_get_long (memsa + 8);
+	v[3] = x_get_long (memsa + 12);
+	x_put_long (memda , v[0]);
+	x_put_long (memda + 4, v[1]);
+	x_put_long (memda + 8, v[2]);
+	x_put_long (memda + 12, v[3]);
+	m68k_areg (regs, dstreg) += 16;
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (An),(xxx).L */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f610_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = m68k_areg (regs, srcreg);
+{	uaecptr memda;
+	memda = get_iilong_jit (2);
+	memsa &= ~15;
+	memda &= ~15;
+	v[0] = x_get_long (memsa);
+	v[1] = x_get_long (memsa + 4);
+	v[2] = x_get_long (memsa + 8);
+	v[3] = x_get_long (memsa + 12);
+	x_put_long (memda , v[0]);
+	x_put_long (memda + 4, v[1]);
+	x_put_long (memda + 8, v[2]);
+	x_put_long (memda + 12, v[3]);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (xxx).L,(An) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f618_40)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 12; 
+{	uae_u32 v[4];
+{	uaecptr memsa;
+	memsa = get_iilong_jit (2);
+{	uaecptr memda;
+	memda = m68k_areg (regs, dstreg);
+	memsa &= ~15;
+	memda &= ~15;
+	v[0] = x_get_long (memsa);
+	v[1] = x_get_long (memsa + 4);
+	v[2] = x_get_long (memsa + 8);
+	v[3] = x_get_long (memsa + 12);
+	x_put_long (memda , v[0]);
+	x_put_long (memda + 4, v[1]);
+	x_put_long (memda + 8, v[2]);
+	x_put_long (memda + 12, v[3]);
+}}}	m68k_incpc (6);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* MOVE16.L (An)+,(An)+ */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f620_40)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = 0;
+	OpcodeFamily = 117;
+	CurrentInstrCycles = 8;  
+{	uae_u32 v[4];
+	uaecptr mems = m68k_areg (regs, srcreg) & ~15, memd;
+	dstreg = (get_iiword_jit (2) >> 12) & 7;
+	memd = m68k_areg (regs, dstreg) & ~15;
+	v[0] = x_get_long (mems);
+	v[1] = x_get_long (mems + 4);
+	v[2] = x_get_long (mems + 8);
+	v[3] = x_get_long (mems + 12);
+	x_put_long (memd , v[0]);
+	x_put_long (memd + 4, v[1]);
+	x_put_long (memd + 8, v[2]);
+	x_put_long (memd + 12, v[3]);
+	if (srcreg != dstreg)
+		m68k_areg (regs, srcreg) += 16;
+	m68k_areg (regs, dstreg) += 16;
+}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+/* LPSTOP.L #.W */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_f800_40)(uae_u32 opcode)
+{
+	OpcodeFamily = 127;
+	CurrentInstrCycles = 4;  
+{if (!regs.s) { Exception (8); goto l_401870; }
+{	uae_u16 sw = get_iiword_jit (2);
+	uae_u16 sr;
+	if (sw != (0x100|0x80|0x40)) { Exception (4); goto l_401870; }
+	sr = get_iiword_jit (4);
+	if (!(sr & 0x8000)) { Exception (8); goto l_401870; }
+	regs.sr = sr;
+	MakeFromSR();
+	m68k_setstopped();
+	m68k_incpc (6);
+}}l_401870: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+#endif
+
+#ifdef PART_2
+#endif
+
+#ifdef PART_3
+#endif
+
+#ifdef PART_4
+#endif
+
+#ifdef PART_5
+#endif
+
+#ifdef PART_6
+#endif
+
+#ifdef PART_7
+#endif
+
+#ifdef PART_8
+#endif
+
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+#endif
+
+#ifdef PART_2
+#endif
+
+#ifdef PART_3
+#endif
+
+#ifdef PART_4
+/* NBCD.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4800_42)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((newv) & 0xff);
+}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4810_42)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4818_42)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4820_42)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4828_42)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4830_42)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	m68k_incpc (2);
+{	srca = x_get_disp_ea_020 (m68k_areg (regs, srcreg), 0);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	x_put_byte (srca, newv);
+}}}}}return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4838_42)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4839_42)(uae_u32 opcode)
+{
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_5
+#endif
+
+#ifdef PART_6
+/* SBCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8100_42)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* SBCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_8108_42)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 10;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int bcd = 0;
+	newv = tmp_newv = newv_hi + newv_lo;
+	if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
+	if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
+	SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_7
+/* ABCD.B Dn,Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c100_42)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* ABCD.B -(An),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_c108_42)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 14;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+{	uae_s8 dst = x_get_byte (dsta);
+	m68k_areg (regs, dstreg) = dsta;
+{	uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
+	uae_u16 newv, tmp_newv;
+	int cflg;
+	newv = tmp_newv = newv_hi + newv_lo;	if (newv_lo > 9) { newv += 6; }
+	cflg = (newv & 0x3F0) > 0x90;
+	if (cflg) newv += 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
+	x_put_byte (dsta, newv);
+}}}}}}	m68k_incpc (2);
+return 14 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_8
+#endif
+
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+#endif
+
+#ifdef PART_2
+#endif
+
+#ifdef PART_3
+#endif
+
+#ifdef PART_4
+#endif
+
+#ifdef PART_5
+#endif
+
+#ifdef PART_6
+#endif
+
+#ifdef PART_7
+#endif
+
+#ifdef PART_8
+#endif
+
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+/* OR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0030_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0070_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_00b0_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (6));
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0130_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B Dn,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_013b_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	tmppc = m68k_getpc() + 2;
+	dsta = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0170_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_01f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0230_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0270_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_02b0_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (6));
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0430_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0470_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_04b0_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (6));
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0630_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0670_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_06b0_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (6));
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (8);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0830_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BTST.B #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_083b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 21;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr tmppc;
+	uaecptr dsta;
+	tmppc = m68k_getpc() + 4;
+	dsta = get_disp_ea_000 (tmppc, get_iiword_jit (4));
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+}}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* BCHG.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0870_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 22;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	dst ^= (1 << src);
+	SET_ZFLG (((uae_u32)dst & (1 << src)) >> src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BCLR.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08b0_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 23;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst &= ~(1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* BSET.B #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_08f0_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 24;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= 7;
+	SET_ZFLG (1 ^ ((dst >> src) & 1));
+	dst |= (1 << src);
+	x_put_byte (dsta, dst);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a30_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0a70_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0ab0_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (6));
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (8);
+return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_2
+/* CMP.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c30_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0c70_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_0cb0_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 10; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (6));
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (8);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_1030_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (4);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_103b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+	m68k_incpc (4);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_10bb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_10fb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += areg_byteinc[dstreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1130_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_113b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - areg_byteinc[dstreg];
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_1170_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_117b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1180_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1190_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_1198_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11a8_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b8_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11b9_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (6));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11ba_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B #.B,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_11bc_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uae_s8 src = get_iibyte_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_11fb_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.B (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_13fb_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+	m68k_incpc (8);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_2030_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_203b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_2070_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_207b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	m68k_areg (regs, dstreg) = (src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_20bb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_20fb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2130_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_213b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 4;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_2170_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_217b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2180_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2188_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uae_s32 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2190_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_2198_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_3
+/* MOVE.L -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (4);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21a8_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b8_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21b9_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (6));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21ba_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 20; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 20 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L #.L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_21bc_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uae_s32 src;
+	src = get_iilong_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (6));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (8);
+}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_21fb_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (6);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.L (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_23fb_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 18; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+	m68k_incpc (8);
+}}}}return 18 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_3030_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (4);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_303b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+	m68k_incpc (4);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_3070_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (4);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVEA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_307b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 31;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	src = (uae_s32)(uae_s16)src;
+	m68k_areg (regs, dstreg) = (uae_s32)(uae_s16)(src);
+	m68k_incpc (4);
+}}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_30bb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_30fb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg);
+	m68k_areg (regs, dstreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3130_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),-(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_313b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) - 2;
+	m68k_areg (regs, dstreg) = dsta;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_3170_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_317b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3180_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W An,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3188_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = m68k_areg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3190_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (An)+,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_3198_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W -(An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (4);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,An),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31a8_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b8_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (xxx).L,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31b9_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (6));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d16,PC),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31ba_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_getpc() + 2;
+	srca += (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 12 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_31bc_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 6;  
+{{	uae_s16 src = get_iiword_jit (2);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}return 6 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_31fb_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = (uae_s32)(uae_s16)get_iiword_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (6);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,An,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MOVE.W (d8,PC,Xn),(xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_33fb_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 30;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uaecptr dsta;
+	dsta = get_iilong_jit (4);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+	m68k_incpc (8);
+}}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4030_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	x_put_byte (srca, newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4070_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s16)(newv)) == 0));
+	SET_NFLG (((uae_s16)(newv)) < 0);
+	x_put_word (srca, newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEGX.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 16;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));
+	SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s32)(newv)) == 0));
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	x_put_long (srca, newv);
+}}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_440113; }
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+	x_put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}}	m68k_incpc (4);
+l_440113: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_440114;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_440114;
+	}
+}}}}l_440114: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CHK.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_41bb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 80;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	m68k_incpc (4);
+	if (dst > src) {
+		SET_NFLG (0);
+		Exception (6);
+		goto l_440115;
+	}
+	if ((uae_s32)dst < 0) {
+		SET_NFLG (1);
+		Exception (6);
+		goto l_440115;
+	}
+}}}}l_440115: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* LEA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_41fb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 56;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	m68k_areg (regs, dstreg) = (srca);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4230_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4270_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_42b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.B (d8,An,Xn) */
+#ifndef CPUEMU_68000_ONLY
+uae_u32 REGPARAM2 CPUFUNC(op_42f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+	MakeSR ();
+	x_put_word (srca, regs.sr & 0xff);
+}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+#endif
+#endif
+
+#ifdef PART_4
+/* NEG.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4430_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(0)) < 0;
+	int flgn = ((uae_s8)(dst)) < 0;
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEG.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4470_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{{uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(0)) < 0;
+	int flgn = ((uae_s16)(dst)) < 0;
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NEG.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 15;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{{uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(0)) < 0;
+	int flgn = ((uae_s32)(dst)) < 0;
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(0)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (srca, dst);
+}}}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpc (4);
+}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.B (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_44fb_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+	MakeSR ();
+	regs.sr &= 0xFF00;
+	regs.sr |= src & 0xFF;
+	MakeFromSR();
+	m68k_incpc (4);
+}}}return 10 * CYCLE_UNIT / 2;
+}
+
+/* NOT.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4630_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(dst)) == 0);
+	SET_NFLG (((uae_s8)(dst)) < 0);
+	x_put_byte (srca, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NOT.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4670_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(dst)) == 0);
+	SET_NFLG (((uae_s16)(dst)) < 0);
+	x_put_word (srca, dst);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NOT.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 19;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_u32 dst = ~src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(dst)) == 0);
+	SET_NFLG (((uae_s32)(dst)) < 0);
+	x_put_long (srca, dst);
+}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_440130; }
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpc (4);
+}}}}l_440130: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MV2SR.W (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_46fb_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 33;
+	CurrentInstrCycles = 10; 
+{if (!regs.s) { Exception (8); goto l_440131; }
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+	regs.sr = src;
+	MakeFromSR();
+	m68k_incpc (4);
+}}}}l_440131: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* NBCD.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4830_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 17;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);
+	uae_u16 newv_hi = - (src & 0xF0);
+	uae_u16 newv;
+	int cflg, tmp_newv;
+	if (newv_lo > 9) { newv_lo -= 6; }
+	tmp_newv = newv = newv_hi + newv_lo;
+	cflg = (newv & 0x1F0) > 0x90;
+	if (cflg) newv -= 0x60;
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	SET_ZFLG (GET_ZFLG () & (((uae_s8)(newv)) == 0));
+	SET_NFLG (((uae_s8)(newv)) < 0);
+	SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
+	x_put_byte (srca, newv);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4870_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* PEA.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_487b_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 57;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uaecptr dsta;
+	dsta = m68k_areg (regs, 7) - 4;
+	m68k_areg (regs, 7) = dsta;
+	x_put_long (dsta, srca);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48b0_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 6;  
+{	uae_u16 mask = get_iiword_jit (2);
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_word (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; }
+	while (amask) { x_put_word (srca, m68k_areg (regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; }
+}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVMLE.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_48f0_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 38;
+	CurrentInstrCycles = 10; 
+{	uae_u16 mask = get_iiword_jit (2);
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+	while (dmask) { x_put_long (srca, m68k_dreg (regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; }
+	while (amask) { x_put_long (srca, m68k_areg (regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; }
+}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TST.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a30_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* TST.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4a70_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* TST.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ab0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 20;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4ac0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((src) & 0xff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4ad8_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpc (2);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ae8_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4af0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4af8_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* TAS.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4af9_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 98;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	src |= 0x80;
+	x_put_byte (srca, src);
+}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cb0_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 6;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.W #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cbb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 6;  
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 4;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (4));
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)x_get_word (srca); srca += 2; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cf0_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 10; 
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (4));
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVMEL.L #.W,(d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4cfb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = 3;
+	OpcodeFamily = 37;
+	CurrentInstrCycles = 10; 
+{	uae_u16 mask = get_iiword_jit (2);
+	uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
+{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 4;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (4));
+{	while (dmask) {
+		m68k_dreg (regs, movem_index1[dmask]) = x_get_long (srca); srca += 4; dmask = movem_next[dmask];
+	}
+	while (amask) {
+		m68k_areg (regs, movem_index1[amask]) = x_get_long (srca); srca += 4; amask = movem_next[amask];
+	}
+}}}	m68k_incpc (6);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4eb0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 14; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uaecptr oldpc = m68k_getpc() + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_440152;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}l_440152: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* JSR.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ebb_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 52;
+	CurrentInstrCycles = 14; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uaecptr oldpc = m68k_getpc() + 4;
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_440153;
+	}
+	m68k_setpc (srca);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), oldpc);
+}}}l_440153: ;
+return 14 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4ef0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_440154;
+	}
+	m68k_setpc (srca);
+}}l_440154: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* JMP.L (d8,PC,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4efb_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 53;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+	if (srca & 1) {
+		exception3i (opcode, srca);
+		goto l_440155;
+	}
+	m68k_setpc (srca);
+}}l_440155: ;
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5030_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5070_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_5
+/* ADDQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_50b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.B #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5130_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.W #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_5170_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBQ.L #,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_51b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = imm8_table[((opcode >> 9) & 7)];
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_u32 src = srcreg;
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_60ff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (0)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440178;
+	}
+	m68k_incpc (2);
+}l_440178: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* BSR.L #.L */
+uae_u32 REGPARAM2 CPUFUNC(op_61ff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 54;
+	CurrentInstrCycles = 10; 
+{	uae_s32 s;
+	uae_u32 src = 0xffffffff;
+	s = (uae_s32)src + 2;
+	if (src & 1) {
+		exception3b (opcode, m68k_getpc() + s, 0, 1, m68k_getpc() + s);
+		goto l_440179;
+	}
+	m68k_do_bsri_jit (m68k_getpc() + 2, s);
+}l_440179: ;
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_62ff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (2)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440180;
+	}
+	m68k_incpc (2);
+}l_440180: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_6
+/* Bcc.L #.L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_63ff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (3)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440181;
+	}
+	m68k_incpc (2);
+}l_440181: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_64ff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (4)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440182;
+	}
+	m68k_incpc (2);
+}l_440182: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_65ff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (5)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440183;
+	}
+	m68k_incpc (2);
+}l_440183: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_66ff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (6)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440184;
+	}
+	m68k_incpc (2);
+}l_440184: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_67ff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (7)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440185;
+	}
+	m68k_incpc (2);
+}l_440185: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_68ff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (8)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440186;
+	}
+	m68k_incpc (2);
+}l_440186: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_69ff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (9)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440187;
+	}
+	m68k_incpc (2);
+}l_440187: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_6aff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (10)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440188;
+	}
+	m68k_incpc (2);
+}l_440188: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_6bff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (11)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440189;
+	}
+	m68k_incpc (2);
+}l_440189: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6cff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (12)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440190;
+	}
+	m68k_incpc (2);
+}l_440190: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6dff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (13)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440191;
+	}
+	m68k_incpc (2);
+}l_440191: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_6eff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (14)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440192;
+	}
+	m68k_incpc (2);
+}l_440192: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Bcc.L #.L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_6fff_44)(uae_u32 opcode)
+{
+	OpcodeFamily = 55;
+	CurrentInstrCycles = 4;  
+{	if (cctrue (15)) {
+		exception3i (opcode, m68k_getpc() + 1);
+		goto l_440193;
+	}
+	m68k_incpc (2);
+}l_440193: ;
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8030_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_803b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_8070_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_807b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* OR.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80bb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpc (4);
+		Exception (5);
+		goto l_440200;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (4);
+	}
+}}}}l_440200: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* DIVU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_80fb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 60;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	CLEAR_CZNV ();
+	if (src == 0) {
+	m68k_incpc (4);
+		Exception (5);
+		goto l_440201;
+	} else {
+		uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
+		uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
+		if (newv > 0xffff) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	m68k_incpc (4);
+	}
+}}}}l_440201: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* OR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8130_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s8 dst = x_get_byte (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_8170_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s16 dst = x_get_word (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* OR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_81b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 1;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s32 dst = x_get_long (dsta);
+	src |= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpc (4);
+		Exception (5);
+		goto l_440205;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (4);
+}}}}l_440205: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* DIVS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_81fb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 61;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	if (src == 0) {
+	m68k_incpc (4);
+		Exception (5);
+		goto l_440206;
+	}
+	CLEAR_CZNV ();
+	if (dst == 0x80000000 && src == -1) {
+		SET_VFLG (1);
+		SET_NFLG (1);
+	} else {
+		uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
+		uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
+		if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+		} else {
+			if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_NFLG (((uae_s16)(newv)) < 0);
+			newv = (newv & 0xffff) | ((uae_u32)rem << 16);
+			m68k_dreg (regs, dstreg) = (newv);
+		}
+	}
+	m68k_incpc (4);
+}}}}l_440206: ;
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9030_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_903b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_9070_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_907b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_90bb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_90fb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9130_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_9170_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* SUB.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_91b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 7;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* SUBA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_91fb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 8;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst - src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b030_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b03b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u8)(src)) > ((uae_u8)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b070_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* CMP.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b07b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u16)(src)) > ((uae_u16)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_7
+/* CMP.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMP.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_b0bb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 25;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b0fb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 8;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* EOR.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b130_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s8 dst = x_get_byte (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b170_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s16 dst = x_get_word (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* EOR.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_b1b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 3;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s32 dst = x_get_long (dsta);
+	src ^= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* CMPA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_b1fb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 27;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs != flgo) && (flgn != flgo));
+	SET_CFLG (((uae_u32)(src)) > ((uae_u32)(dst)));
+	SET_NFLG (flgn != 0);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c030_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c03b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((src) & 0xff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c070_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c07b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((src) & 0xffff);
+}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* AND.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0bb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	m68k_dreg (regs, dstreg) = (src);
+}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 40; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (4);
+}}}}}return 40 * CYCLE_UNIT / 2;
+}
+
+/* MULU.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c0fb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 62;
+	CurrentInstrCycles = 40; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+	m68k_incpc (4);
+}}}}}return 40 * CYCLE_UNIT / 2;
+}
+
+/* AND.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c130_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s8 dst = x_get_byte (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(src)) == 0);
+	SET_NFLG (((uae_s8)(src)) < 0);
+	x_put_byte (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c170_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s16 dst = x_get_word (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(src)) == 0);
+	SET_NFLG (((uae_s16)(src)) < 0);
+	x_put_word (dsta, src);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* AND.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_c1b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 2;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s32 dst = x_get_long (dsta);
+	src &= dst;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(src)) == 0);
+	SET_NFLG (((uae_s32)(src)) < 0);
+	x_put_long (dsta, src);
+}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 40; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 40 * CYCLE_UNIT / 2;
+}
+
+/* MULS.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_c1fb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 63;
+	CurrentInstrCycles = 40; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{	uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_NFLG (((uae_s32)(newv)) < 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 40 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d030_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d03b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{	uae_s8 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xff) | ((newv) & 0xff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d070_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d07b_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 6;  
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s16 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
+}}}}}}}	m68k_incpc (4);
+return 6 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,An,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L (d8,PC,Xn),Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_d0bb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_dreg (regs, dstreg);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	m68k_dreg (regs, dstreg) = (newv);
+}}}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.W (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d0fb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 10; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.B Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d130_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s8 dst = x_get_byte (dsta);
+{{uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
+{	int flgs = ((uae_s8)(src)) < 0;
+	int flgo = ((uae_s8)(dst)) < 0;
+	int flgn = ((uae_s8)(newv)) < 0;
+	SET_ZFLG (((uae_s8)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u8)(~dst)) < ((uae_u8)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_byte (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.W Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d170_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 10; 
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s16 dst = x_get_word (dsta);
+{{uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
+{	int flgs = ((uae_s16)(src)) < 0;
+	int flgo = ((uae_s16)(dst)) < 0;
+	int flgn = ((uae_s16)(newv)) < 0;
+	SET_ZFLG (((uae_s16)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u16)(~dst)) < ((uae_u16)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_word (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ADD.L Dn,(d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_d1b0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = ((opcode >> 9) & 7);
+	uae_u32 dstreg = opcode & 7;
+	OpcodeFamily = 11;
+	CurrentInstrCycles = 18; 
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+{	uaecptr dsta;
+	dsta = get_disp_ea_000 (m68k_areg (regs, dstreg), get_iiword_jit (2));
+{	uae_s32 dst = x_get_long (dsta);
+{{uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
+{	int flgs = ((uae_s32)(src)) < 0;
+	int flgo = ((uae_s32)(dst)) < 0;
+	int flgn = ((uae_s32)(newv)) < 0;
+	SET_ZFLG (((uae_s32)(newv)) == 0);
+	SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));
+	SET_CFLG (((uae_u32)(~dst)) < ((uae_u32)(src)));
+	COPY_CARRY ();
+	SET_NFLG (flgn != 0);
+	x_put_long (dsta, newv);
+}}}}}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,An,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+/* ADDA.L (d8,PC,Xn),An */
+uae_u32 REGPARAM2 CPUFUNC(op_d1fb_44)(uae_u32 opcode)
+{
+	uae_u32 dstreg = (opcode >> 9) & 7;
+	OpcodeFamily = 12;
+	CurrentInstrCycles = 12; 
+{{	uaecptr tmppc;
+	uaecptr srca;
+	tmppc = m68k_getpc() + 2;
+	srca = get_disp_ea_000 (tmppc, get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+{	uae_s32 dst = m68k_areg (regs, dstreg);
+{	uae_u32 newv = dst + src;
+	m68k_areg (regs, dstreg) = (newv);
+}}}}}	m68k_incpc (4);
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_8
+/* ASRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e0f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 72;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 cflg = val & 1;
+	val = (val >> 1) | sign;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (cflg);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ASLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e1f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 73;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 sign = 0x8000 & val;
+	uae_u32 sign2;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	sign2 = 0x8000 & val;
+	SET_CFLG (sign != 0);
+	COPY_CARRY ();
+	SET_VFLG (GET_VFLG () | (sign2 != sign));
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* LSRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e2f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 74;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u32 val = (uae_u16)data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* LSLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e3f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 75;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROXRW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e4f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 79;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (GET_XFLG ()) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROXLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e5f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 78;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (GET_XFLG ()) val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	COPY_CARRY ();
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* RORW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e6f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 77;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 1;
+	val >>= 1;
+	if (carry) val |= 0x8000;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry);
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* ROLW.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_e7f0_44)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 76;
+	CurrentInstrCycles = 10; 
+{{	uaecptr dataa;
+	dataa = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 data = x_get_word (dataa);
+{	uae_u16 val = data;
+	uae_u32 carry = val & 0x8000;
+	val <<= 1;
+	if (carry)  val |= 1;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(val)) == 0);
+	SET_NFLG (((uae_s16)(val)) < 0);
+	SET_CFLG (carry >> 15);
+	x_put_word (dataa, val);
+}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+
+#if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8)
+#define PART_1 1
+#define PART_2 1
+#define PART_3 1
+#define PART_4 1
+#define PART_5 1
+#define PART_6 1
+#define PART_7 1
+#define PART_8 1
+#endif
+
+#ifdef PART_1
+#endif
+
+#ifdef PART_2
+#endif
+
+#ifdef PART_3
+/* MVSR2.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_40c0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 4;  
+{{	MakeSR ();
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40d0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	x_put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_40d8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+	m68k_areg (regs, srcreg) += 2;
+	x_put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+	m68k_areg (regs, srcreg) = srca;
+	x_put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_40e8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+	x_put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_40f0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+	x_put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_40f8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+	x_put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* MVSR2.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_40f9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 32;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+	x_put_word (srca, regs.sr | 0x0010);
+	MakeSR ();
+	x_put_word (srca, regs.sr);
+}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4200_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((0) & 0xff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4210_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4218_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4220_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4228_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4230_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4238_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.B (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4239_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s8)(0)) == 0);
+	SET_NFLG (((uae_s8)(0)) < 0);
+	x_put_byte (srca, 0);
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4240_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uae_s16 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xffff) | ((0) & 0xffff);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4250_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4258_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) += 2;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4260_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 2;
+{	uae_s16 src = x_get_word (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4268_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_4270_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_4278_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.W (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_4279_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s16 src = x_get_word (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s16)(0)) == 0);
+	SET_NFLG (((uae_s16)(0)) < 0);
+	x_put_word (srca, 0);
+}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L Dn */
+uae_u32 REGPARAM2 CPUFUNC(op_4280_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 4;  
+{{	uae_s32 src = m68k_dreg (regs, srcreg);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	m68k_dreg (regs, srcreg) = (0);
+}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An) */
+uae_u32 REGPARAM2 CPUFUNC(op_4290_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (An)+ */
+uae_u32 REGPARAM2 CPUFUNC(op_4298_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) += 4;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}}	m68k_incpc (2);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L -(An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - 4;
+{	uae_s32 src = x_get_long (srca);
+	m68k_areg (regs, srcreg) = srca;
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}}	m68k_incpc (2);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d16,An) */
+uae_u32 REGPARAM2 CPUFUNC(op_42a8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (d8,An,Xn) */
+uae_u32 REGPARAM2 CPUFUNC(op_42b0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 18; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}}	m68k_incpc (4);
+return 18 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).W */
+uae_u32 REGPARAM2 CPUFUNC(op_42b8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}}	m68k_incpc (4);
+return 16 * CYCLE_UNIT / 2;
+}
+
+/* CLR.L (xxx).L */
+uae_u32 REGPARAM2 CPUFUNC(op_42b9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 18;
+	CurrentInstrCycles = 16; 
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s32 src = x_get_long (srca);
+	CLEAR_CZNV ();
+	SET_ZFLG (((uae_s32)(0)) == 0);
+	SET_NFLG (((uae_s32)(0)) < 0);
+	x_put_long (srca, 0);
+}}}	m68k_incpc (6);
+return 16 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_4
+/* RTE.L  */
+uae_u32 REGPARAM2 CPUFUNC(op_4e73_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 45;
+	CurrentInstrCycles = 12; 
+{if (!regs.s) { Exception (8); goto l_450033; }
+{{	uaecptr sra;
+	sra = m68k_areg (regs, 7);
+{	uae_s16 sr = x_get_word (sra);
+	m68k_areg (regs, 7) += 2;
+{	uaecptr pca;
+	pca = m68k_areg (regs, 7);
+{	uae_s32 pc = x_get_long (pca);
+	m68k_areg (regs, 7) += 4;
+	regs.sr = sr;
+	if (pc & 1) {
+		exception3i (0x4E73, pc);
+		goto l_450033;
+	}
+	m68k_setpc (pc);
+	MakeFromSR();
+}}}}}}l_450033: ;
+return 12 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_5
+/* Scc.B Dn (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50c0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (0) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50d8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50e8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (T) */
+uae_u32 REGPARAM2 CPUFUNC(op_50f9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (0) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51c0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (1) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51d8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51e8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (F) */
+uae_u32 REGPARAM2 CPUFUNC(op_51f9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (1) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52c0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (2) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52d8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52e8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (HI) */
+uae_u32 REGPARAM2 CPUFUNC(op_52f9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (2) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53c0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (3) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53d8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53e8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LS) */
+uae_u32 REGPARAM2 CPUFUNC(op_53f9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (3) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54c0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (4) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54d8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54e8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CC) */
+uae_u32 REGPARAM2 CPUFUNC(op_54f9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (4) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55c0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (5) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55d8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55e8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (CS) */
+uae_u32 REGPARAM2 CPUFUNC(op_55f9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (5) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56c0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (6) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56d8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56e8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (NE) */
+uae_u32 REGPARAM2 CPUFUNC(op_56f9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (6) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57c0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (7) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57d8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57e8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (EQ) */
+uae_u32 REGPARAM2 CPUFUNC(op_57f9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (7) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58c0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (8) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58d8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58e8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VC) */
+uae_u32 REGPARAM2 CPUFUNC(op_58f9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (8) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59c0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (9) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59d8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59e8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (VS) */
+uae_u32 REGPARAM2 CPUFUNC(op_59f9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (9) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ac0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (10) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ad8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ae8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (PL) */
+uae_u32 REGPARAM2 CPUFUNC(op_5af9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (10) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bc0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (11) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bd8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5be8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (MI) */
+uae_u32 REGPARAM2 CPUFUNC(op_5bf9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (11) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cc0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (12) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cd8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ce8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5cf9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (12) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dc0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (13) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5dd8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5de8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5df9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (13) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ec0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (14) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ed8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ee8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (GT) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ef9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (14) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B Dn (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fc0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 4;  
+{{	uae_s8 src = m68k_dreg (regs, srcreg);
+{{	int val = cctrue (15) ? 0xff : 0;
+	m68k_dreg (regs, srcreg) = (m68k_dreg (regs, srcreg) & ~0xff) | ((val) & 0xff);
+}}}}	m68k_incpc (2);
+return 4 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (An)+ (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fd8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg);
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) += areg_byteinc[srcreg];
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B -(An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) - areg_byteinc[srcreg];
+{	uae_s8 src = x_get_byte (srca);
+	m68k_areg (regs, srcreg) = srca;
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (2);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d16,An) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5fe8_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (d8,An,Xn) (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff0_45)(uae_u32 opcode)
+{
+	uae_u32 srcreg = (opcode & 7);
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 10; 
+{{	uaecptr srca;
+	srca = get_disp_ea_000 (m68k_areg (regs, srcreg), get_iiword_jit (2));
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 10 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).W (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff8_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = (uae_s32)(uae_s16)get_iiword_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (4);
+return 8 * CYCLE_UNIT / 2;
+}
+
+/* Scc.B (xxx).L (LE) */
+uae_u32 REGPARAM2 CPUFUNC(op_5ff9_45)(uae_u32 opcode)
+{
+	OpcodeFamily = 59;
+	CurrentInstrCycles = 8;  
+{{	uaecptr srca;
+	srca = get_iilong_jit (2);
+{	uae_s8 src = x_get_byte (srca);
+{{	int val = cctrue (15) ? 0xff : 0;
+	x_put_byte (srca, val);
+}}}}}	m68k_incpc (6);
+return 8 * CYCLE_UNIT / 2;
+}
+
+#endif
+
+#ifdef PART_6
+#endif
+
+#ifdef PART_7
+#endif
+
+#ifdef PART_8
+#endif
+
diff --git a/src/cpu/cpummu.c b/src/cpu/cpummu.c
new file mode 100644
index 0000000..73e7741
--- /dev/null
+++ b/src/cpu/cpummu.c
@@ -0,0 +1,1536 @@
+/*
+ * cpummu.cpp -  MMU emulation
+ *
+ * Copyright (c) 2001-2004 Milan Jurik of ARAnyM dev team (see AUTHORS)
+ * 
+ * Inspired by UAE MMU patch
+ *
+ * This file is part of the ARAnyM project which builds a new and powerful
+ * TOS/FreeMiNT compatible virtual machine running on almost any hardware.
+ *
+ * ARAnyM is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * ARAnyM is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with ARAnyM; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+
+#include "main.h"
+#include "hatari-glue.h"
+
+
+#include "options_cpu.h"
+#include "memory.h"
+#include "newcpu.h"
+#include "cpummu.h"
+#include "debug.h"
+
+#define MMUDUMP 0
+
+#define DBG_MMU_VERBOSE	1
+#define DBG_MMU_SANITY	1
+#if 0
+#define write_log printf
+#endif
+
+#ifdef FULLMMU
+
+uae_u32 mmu_is_super;
+uae_u32 mmu_tagmask, mmu_pagemask, mmu_pagemaski;
+struct mmu_atc_line mmu_atc_array[ATC_TYPE][ATC_WAYS][ATC_SLOTS];
+bool mmu_pagesize_8k;
+
+int mmu060_state;
+uae_u16 mmu_opcode;
+bool mmu_restart;
+static bool locked_rmw_cycle;
+static bool ismoves;
+bool mmu_ttr_enabled;
+int mmu_atc_ways;
+
+int mmu040_movem;
+uaecptr mmu040_movem_ea;
+uae_u32 mmu040_move16[4];
+
+static void mmu_dump_ttr(const TCHAR * label, uae_u32 ttr)
+{
+#if MMUDEBUG > 0			// ifdef WINUAE_FOR_HATARI
+	DUNUSED(label);
+	uae_u32 from_addr, to_addr;
+
+	from_addr = ttr & MMU_TTR_LOGICAL_BASE;
+	to_addr = (ttr & MMU_TTR_LOGICAL_MASK) << 8;
+
+	write_log(_T("%s: [%08x] %08x - %08x enabled=%d supervisor=%d wp=%d cm=%02d\n"),
+			label, ttr,
+			from_addr, to_addr,
+			ttr & MMU_TTR_BIT_ENABLED ? 1 : 0,
+			(ttr & (MMU_TTR_BIT_SFIELD_ENABLED | MMU_TTR_BIT_SFIELD_SUPER)) >> MMU_TTR_SFIELD_SHIFT,
+			ttr & MMU_TTR_BIT_WRITE_PROTECT ? 1 : 0,
+			(ttr & MMU_TTR_CACHE_MASK) >> MMU_TTR_CACHE_SHIFT
+		  );
+#endif
+}
+
+void mmu_make_transparent_region(uaecptr baseaddr, uae_u32 size, int datamode)
+{
+	uae_u32 * ttr;
+	uae_u32 * ttr0 = datamode ? ®s.dtt0 : ®s.itt0;
+	uae_u32 * ttr1 = datamode ? ®s.dtt1 : ®s.itt1;
+
+	if ((*ttr1 & MMU_TTR_BIT_ENABLED) == 0)
+		ttr = ttr1;
+	else if ((*ttr0 & MMU_TTR_BIT_ENABLED) == 0)
+		ttr = ttr0;
+	else
+		return;
+
+	*ttr = baseaddr & MMU_TTR_LOGICAL_BASE;
+	*ttr |= ((baseaddr + size - 1) & MMU_TTR_LOGICAL_BASE) >> 8;
+	*ttr |= MMU_TTR_BIT_ENABLED;
+
+#if MMUDEBUG > 0
+	write_log(_T("MMU: map transparent mapping of %08x\n"), *ttr);
+#endif
+}
+
+void mmu_tt_modified (void)
+{
+	mmu_ttr_enabled = ((regs.dtt0 | regs.dtt1 | regs.itt0 | regs.itt1) & MMU_TTR_BIT_ENABLED) != 0;
+}
+
+
+#if MMUDUMP
+
+/* This dump output makes much more sense than old one */
+
+#define LEVELA_SIZE 7
+#define LEVELB_SIZE 7
+#define LEVELC_SIZE 6
+#define PAGE_SIZE 12 // = 1 << 12 = 4096
+
+#define LEVELA_VAL(x) ((((uae_u32)(x)) >> (32 - (LEVELA_SIZE                            ))) & ((1 << LEVELA_SIZE) - 1))
+#define LEVELB_VAL(x) ((((uae_u32)(x)) >> (32 - (LEVELA_SIZE + LEVELB_SIZE              ))) & ((1 << LEVELB_SIZE) - 1))
+#define LEVELC_VAL(x) ((((uae_u32)(x)) >> (32 - (LEVELA_SIZE + LEVELB_SIZE + LEVELC_SIZE))) & ((1 << LEVELC_SIZE) - 1))
+
+#define LEVELA(root, x) (get_long(root + LEVELA_VAL(x) * 4))
+#define LEVELB(a, x) (get_long((((uae_u32)a) & ~((1 << (LEVELB_SIZE + 2)) - 1)) + LEVELB_VAL(x) * 4))
+#define LEVELC(b, x) (get_long((((uae_u32)b) & ~((1 << (LEVELC_SIZE + 2)) - 1)) + LEVELC_VAL(x) * 4))
+
+#define ISINVALID(x) ((((ULONG)x) & 3) == 0)
+
+static uae_u32 getdesc(uae_u32 root, uae_u32 addr)
+{
+	ULONG desc;
+
+	desc = LEVELA(root, addr);
+	if (ISINVALID(desc))
+		return desc;
+	desc = LEVELB(desc, addr);
+	if (ISINVALID(desc))
+		return desc;
+	desc = LEVELC(desc, addr);
+	return desc;
+}
+static void mmu_dump_table(const char * label, uaecptr root_ptr)
+{
+	ULONG i;
+	ULONG startaddr;
+	ULONG odesc;
+	ULONG totalpages;
+	ULONG pagemask = (1 << PAGE_SIZE) - 1;
+
+	console_out_f(_T("MMU dump start. Root = %08x\n"), root_ptr);
+	totalpages = 1 << (32 - PAGE_SIZE);
+	startaddr = 0;
+	odesc = getdesc(root_ptr, startaddr);
+	for (i = 0; i <= totalpages; i++) {
+		ULONG addr = i << PAGE_SIZE;
+		ULONG desc = 0;
+		if (i < totalpages)
+			desc = getdesc(root_ptr, addr);
+		if ((desc & pagemask) != (odesc & pagemask) || i == totalpages) {
+			uae_u8 cm, sp;
+			cm = (odesc >> 5) & 3;
+			sp = (odesc >> 7) & 1;
+			console_out_f(_T("%08x - %08x: %08x WP=%d S=%d CM=%d (%08x)\n"),
+				startaddr, addr - 1, odesc & ~((1 << PAGE_SIZE) - 1),
+				(odesc & 4) ? 1 : 0, sp, cm, odesc);
+			startaddr = addr;
+			odesc = desc;
+		}
+	}
+	console_out_f(_T("MMU dump end\n"));
+}			
+
+#else
+/* {{{ mmu_dump_table */
+static void mmu_dump_table(const char * label, uaecptr root_ptr)
+{
+	DUNUSED(label);
+	const int ROOT_TABLE_SIZE = 128,
+		PTR_TABLE_SIZE = 128,
+		PAGE_TABLE_SIZE = 64,
+		ROOT_INDEX_SHIFT = 25,
+		PTR_INDEX_SHIFT = 18;
+	// const int PAGE_INDEX_SHIFT = 12;
+	int root_idx, ptr_idx, page_idx;
+	uae_u32 root_des, ptr_des, page_des;
+	uaecptr ptr_des_addr, page_addr,
+		root_log, ptr_log, page_log;
+
+	console_out_f(_T("%s: root=%x\n"), label, root_ptr);
+
+	for (root_idx = 0; root_idx < ROOT_TABLE_SIZE; root_idx++) {
+		root_des = phys_get_long(root_ptr + root_idx);
+
+		if ((root_des & 2) == 0)
+			continue;	/* invalid */
+
+		console_out_f(_T("ROOT: %03d U=%d W=%d UDT=%02d\n"), root_idx,
+				root_des & 8 ? 1 : 0,
+				root_des & 4 ? 1 : 0,
+				root_des & 3
+			  );
+
+		root_log = root_idx << ROOT_INDEX_SHIFT;
+
+		ptr_des_addr = root_des & MMU_ROOT_PTR_ADDR_MASK;
+
+		for (ptr_idx = 0; ptr_idx < PTR_TABLE_SIZE; ptr_idx++) {
+			struct {
+				uaecptr	log, phys;
+				int start_idx, n_pages;	/* number of pages covered by this entry */
+				uae_u32 match;
+			} page_info[PAGE_TABLE_SIZE];
+			int n_pages_used;
+
+			ptr_des = phys_get_long(ptr_des_addr + ptr_idx);
+			ptr_log = root_log | (ptr_idx << PTR_INDEX_SHIFT);
+
+			if ((ptr_des & 2) == 0)
+				continue; /* invalid */
+
+			page_addr = ptr_des & (mmu_pagesize_8k ? MMU_PTR_PAGE_ADDR_MASK_8 : MMU_PTR_PAGE_ADDR_MASK_4);
+
+			n_pages_used = -1;
+			for (page_idx = 0; page_idx < PAGE_TABLE_SIZE; page_idx++) {
+
+				page_des = phys_get_long(page_addr + page_idx);
+				page_log = ptr_log | (page_idx << 2);		// ??? PAGE_INDEX_SHIFT
+
+				switch (page_des & 3) {
+					case 0: /* invalid */
+						continue;
+					case 1: case 3: /* resident */
+					case 2: /* indirect */
+						if (n_pages_used == -1 || page_info[n_pages_used].match != page_des) {
+							/* use the next entry */
+							n_pages_used++;
+
+							page_info[n_pages_used].match = page_des;
+							page_info[n_pages_used].n_pages = 1;
+							page_info[n_pages_used].start_idx = page_idx;
+							page_info[n_pages_used].log = page_log;
+						} else {
+							page_info[n_pages_used].n_pages++;
+						}
+						break;
+				}
+			}
+
+			if (n_pages_used == -1)
+				continue;
+
+			console_out_f(_T(" PTR: %03d U=%d W=%d UDT=%02d\n"), ptr_idx,
+				ptr_des & 8 ? 1 : 0,
+				ptr_des & 4 ? 1 : 0,
+				ptr_des & 3
+			  );
+
+
+			for (page_idx = 0; page_idx <= n_pages_used; page_idx++) {
+				page_des = page_info[page_idx].match;
+
+				if ((page_des & MMU_PDT_MASK) == 2) {
+					console_out_f(_T("  PAGE: %03d-%03d log=%08x INDIRECT --> addr=%08x\n"),
+							page_info[page_idx].start_idx,
+							page_info[page_idx].start_idx + page_info[page_idx].n_pages - 1,
+							page_info[page_idx].log,
+							page_des & MMU_PAGE_INDIRECT_MASK
+						  );
+
+				} else {
+					console_out_f(_T("  PAGE: %03d-%03d log=%08x addr=%08x UR=%02d G=%d U1/0=%d S=%d CM=%d M=%d U=%d W=%d\n"),
+							page_info[page_idx].start_idx,
+							page_info[page_idx].start_idx + page_info[page_idx].n_pages - 1,
+							page_info[page_idx].log,
+							page_des & (mmu_pagesize_8k ? MMU_PAGE_ADDR_MASK_8 : MMU_PAGE_ADDR_MASK_4),
+							(page_des & (mmu_pagesize_8k ? MMU_PAGE_UR_MASK_8 : MMU_PAGE_UR_MASK_4)) >> MMU_PAGE_UR_SHIFT,
+							page_des & MMU_DES_GLOBAL ? 1 : 0,
+							(page_des & MMU_TTR_UX_MASK) >> MMU_TTR_UX_SHIFT,
+							page_des & MMU_DES_SUPER ? 1 : 0,
+							(page_des & MMU_TTR_CACHE_MASK) >> MMU_TTR_CACHE_SHIFT,
+							page_des & MMU_DES_MODIFIED ? 1 : 0,
+							page_des & MMU_DES_USED ? 1 : 0,
+							page_des & MMU_DES_WP ? 1 : 0
+						  );
+				}
+			}
+		}
+
+	}
+}
+/* }}} */
+#endif
+
+/* {{{ mmu_dump_atc */
+void mmu_dump_atc(void)
+{
+
+}
+/* }}} */
+
+/* {{{ mmu_dump_tables */
+void mmu_dump_tables(void)
+{
+	write_log(_T("URP: %08x   SRP: %08x  MMUSR: %x  TC: %x\n"), regs.urp, regs.srp, regs.mmusr, regs.tcr);
+	mmu_dump_ttr(_T("DTT0"), regs.dtt0);
+	mmu_dump_ttr(_T("DTT1"), regs.dtt1);
+	mmu_dump_ttr(_T("ITT0"), regs.itt0);
+	mmu_dump_ttr(_T("ITT1"), regs.itt1);
+	mmu_dump_atc();
+#if MMUDUMP
+	mmu_dump_table("SRP", regs.srp);
+#endif
+}
+/* }}} */
+
+static uaecptr REGPARAM2 mmu_lookup_pagetable(uaecptr addr, bool super, bool write, uae_u32 *status);
+
+static ALWAYS_INLINE int mmu_get_fc(bool super, bool data)
+{
+	return (super ? 4 : 0) | (data ? 1 : 2);
+}
+
+void mmu_bus_error(uaecptr addr, int fc, bool write, int size, bool rmw, uae_u32 status, bool nonmmu)
+{
+	if (currprefs.mmu_model == 68040) {
+		uae_u16 ssw = 0;
+
+		if (ismoves) {
+			// MOVES special behavior
+			int fc2 = write ? regs.dfc : regs.sfc;
+			if (fc2 == 0 || fc2 == 3 || fc2 == 4 || fc2 == 7)
+				ssw |= MMU_SSW_TT1;
+			if ((fc2 & 3) != 3)
+				fc2 &= ~2;
+#if MMUDEBUGMISC > 0
+			write_log (_T("040 MMU MOVES fc=%d -> %d\n"), fc, fc2);
+#endif
+			fc = fc2;
+		}
+
+		ssw |= fc & MMU_SSW_TM;				/* TM = FC */
+
+		switch (size) {
+		case sz_byte:
+			ssw |= MMU_SSW_SIZE_B;
+			break;
+		case sz_word:
+			ssw |= MMU_SSW_SIZE_W;
+			break;
+		case sz_long:
+			ssw |= MMU_SSW_SIZE_L;
+			break;
+		}
+
+		regs.wb3_status = write ? 0x80 | (ssw & 0x7f) : 0;
+		regs.wb2_status = 0;
+		if (!write)
+			ssw |= MMU_SSW_RW;
+
+		if (size == 16) { // MOVE16
+			ssw |= MMU_SSW_SIZE_CL;
+			ssw |= MMU_SSW_TT0;
+			regs.mmu_effective_addr &= ~15;
+			if (write) {
+				// clear normal writeback if MOVE16 write
+				regs.wb3_status &= ~0x80;
+				// wb2 = cacheline size writeback
+				regs.wb2_status = 0x80 | MMU_SSW_SIZE_CL | (ssw & 0x1f);
+				regs.wb2_address = regs.mmu_effective_addr;
+				write_log (_T("040 MMU MOVE16 WRITE FAULT!\n"));
+			}
+		}
+
+		if (mmu040_movem) {
+			ssw |= MMU_SSW_CM;
+			regs.mmu_effective_addr = mmu040_movem_ea;
+			mmu040_movem = 0;
+#if MMUDEBUGMISC > 0
+			write_log (_T("040 MMU_SSW_CM EA=%08X\n"), mmu040_movem_ea);
+#endif
+		}
+		if (locked_rmw_cycle) {
+			ssw |= MMU_SSW_LK;
+			ssw &= ~MMU_SSW_RW;
+			locked_rmw_cycle = false;
+#if MMUDEBUGMISC > 0
+			write_log (_T("040 MMU_SSW_LK!\n"));
+#endif
+		}
+
+		if (!nonmmu)
+			ssw |= MMU_SSW_ATC;
+		regs.mmu_ssw = ssw;
+
+#if MMUDEBUG > 0
+		write_log(_T("BF: fc=%d w=%d logical=%08x ssw=%04x PC=%08x INS=%04X\n"), fc, write, addr, ssw, m68k_getpc(), mmu_opcode);
+#endif
+	} else {
+		uae_u32 fslw = 0;
+
+		fslw |= write ? MMU_FSLW_W : MMU_FSLW_R;
+		fslw |= fc << 16; /* MMU_FSLW_TM */
+
+		switch (size) {
+		case sz_byte:
+			fslw |= MMU_FSLW_SIZE_B;
+			break;
+		case sz_word:
+			fslw |= MMU_FSLW_SIZE_W;
+			break;
+		case sz_long:
+			fslw |= MMU_FSLW_SIZE_L;
+			break;
+		case 16: // MOVE16
+			addr &= ~15;
+			fslw |= MMU_FSLW_SIZE_D;
+			fslw |= MMU_FSLW_TT_16;
+			break;
+		}
+		if ((fc & 3) == 2) {
+			// instruction faults always point to opcode address
+#if MMUDEBUGMISC > 0
+			write_log(_T("INS FAULT %08x %08x %d\n"), addr, regs.instruction_pc, mmu060_state);
+#endif
+			addr = regs.instruction_pc;
+			if (mmu060_state == 0) {
+				fslw |= MMU_FSLW_IO; // opword fetch
+			} else {
+				fslw |= MMU_FSLW_IO | MMU_FSLW_MA; // extension word
+			}
+		}
+		if (rmw) {
+			fslw |=  MMU_FSLW_W | MMU_FSLW_R;
+		}
+		if (locked_rmw_cycle) {
+			fslw |= MMU_FSLW_LK;
+			locked_rmw_cycle = false;
+			write_log (_T("060 MMU_FSLW_LK!\n"));
+		}
+		fslw |= status;
+		regs.mmu_fslw = fslw;
+
+#if MMUDEBUG > 0
+		write_log(_T("BF: fc=%d w=%d s=%d log=%08x ssw=%08x rmw=%d PC=%08x INS=%04X\n"), fc, write, 1 << size, addr, fslw, rmw, m68k_getpc(), mmu_opcode);
+#endif
+
+	}
+
+	regs.mmu_fault_addr = addr;
+
+#if 0
+	if (m68k_getpc () == 0x0004B0AC) {
+		write_log (_T("*"));
+#if 0
+		extern void activate_debugger(void);
+		activate_debugger ();
+#endif
+	}
+#endif
+	THROW(2);
+}
+
+void mmu_bus_error_ttr_write_fault(uaecptr addr, bool super, bool data, uae_u32 val, int size, bool rmw)
+{
+	uae_u32 status = 0;
+
+	if (currprefs.mmu_model == 68060) {
+		status |= MMU_FSLW_TTR;
+	}
+	regs.wb3_data = val;
+	mmu_bus_error(addr, mmu_get_fc (super, data), true, size, false, status, false);
+}
+
+
+/*
+ * Update the atc line for a given address by doing a mmu lookup.
+ */
+static uaecptr mmu_fill_atc(uaecptr addr, bool super, bool data, bool write, struct mmu_atc_line *l, uae_u32 *status)
+{
+	uae_u32 desc;
+
+	*status = 0;
+	SAVE_EXCEPTION;
+	TRY(prb) {
+		desc = mmu_lookup_pagetable(addr, super, write, status);
+#if MMUDEBUG > 2
+		write_log(_T("translate: %x,%u,%u,%u -> %x\n"), addr, super, write, data, desc);
+#endif
+		RESTORE_EXCEPTION;
+	}
+	CATCH(prb) {
+		RESTORE_EXCEPTION;
+		/* bus error during table search */
+		desc = 0;
+		*status = MMU_FSLW_TWE;
+		// goto fail;
+	} ENDTRY
+	if ((desc & 1) && (!super && desc & MMU_MMUSR_S)) {
+		*status |= MMU_FSLW_SP;
+#if MMUDEBUG > 1
+		write_log (_T("MMU: supervisor protected %x\n"), addr);
+#endif
+		l->valid = 0;
+		l->global = 0;
+	} else if ((desc & 1) == 0) {
+		l->valid = 0;
+		l->global = 0;
+	} else {
+		l->valid = 1;
+		l->phys = desc & mmu_pagemaski;
+		l->global = (desc & MMU_MMUSR_G) != 0;
+		l->modified = (desc & MMU_MMUSR_M) != 0;
+		l->write_protect = (desc & MMU_MMUSR_W) != 0;
+	}
+
+	return desc;
+}
+
+static ALWAYS_INLINE bool mmu_fill_atc_try(uaecptr addr, bool super, bool data, bool write, struct mmu_atc_line *l1, uae_u32 *status)
+{
+	mmu_fill_atc(addr,super,data,write,l1, status);
+	if (!(l1->valid)) {
+#if MMUDEBUG > 2
+		write_log(_T("MMU: non-resident page (%x,%x)!\n"), addr, regs.pc);
+#endif
+		goto fail;
+	}
+	if (write) {
+		if (l1->write_protect) {
+			*status |= MMU_FSLW_WP;
+#if MMUDEBUG > 0
+			write_log(_T("MMU: write protected %x by atc \n"), addr);
+#endif
+			mmu_dump_atc();
+			goto fail;
+		}
+
+	}
+	return true;
+
+fail:
+	return false;
+}
+
+uaecptr REGPARAM2 mmu_translate(uaecptr addr, bool super, bool data, bool write)
+{
+	struct mmu_atc_line *l;
+	uae_u32 status = 0;
+
+	// this should return a miss but choose a valid line
+	mmu_user_lookup(addr, super, data, write, &l);
+
+	mmu_fill_atc(addr, super, data, write, l, &status);
+	if (!l->valid || (write && l->write_protect)) {
+#if MMUDEBUG > 2
+		write_log(_T("[MMU] mmu_translate error"));
+#endif
+		mmu_bus_error(addr, mmu_get_fc(super, data), write, 0, false, status, false);
+		return 0;
+	}
+
+    return l->phys | (addr & mmu_pagemask);
+
+}
+
+/*
+ * Lookup the address by walking the page table and updating
+ * the page descriptors accordingly. Returns the found descriptor
+ * or produces a bus error.
+ */
+static uaecptr REGPARAM2 mmu_lookup_pagetable(uaecptr addr, bool super, bool write, uae_u32 *status)
+{
+	uae_u32 desc, desc_addr, wp;
+	int i;
+
+	wp = 0;
+	desc = super ? regs.srp : regs.urp;
+
+	/* fetch root table descriptor */
+	i = (addr >> 23) & 0x1fc;
+	desc_addr = (desc & MMU_ROOT_PTR_ADDR_MASK) | i;
+	desc = phys_get_long(desc_addr);
+	if ((desc & 2) == 0) {
+#if MMUDEBUG > 1
+		write_log(_T("MMU: invalid root descriptor %s for %x desc at %x desc=%x\n"), super ? _T("srp"):_T("urp"),
+				addr, desc_addr, desc);
+#endif
+		*status |= MMU_FSLW_PTA;
+		return 0;
+	}
+
+	wp |= desc;
+	if ((desc & MMU_DES_USED) == 0)
+		phys_put_long(desc_addr, desc | MMU_DES_USED);
+
+	/* fetch pointer table descriptor */
+	i = (addr >> 16) & 0x1fc;
+	desc_addr = (desc & MMU_ROOT_PTR_ADDR_MASK) | i;
+	desc = phys_get_long(desc_addr);
+	if ((desc & 2) == 0) {
+#if MMUDEBUG > 1
+		write_log(_T("MMU: invalid ptr descriptor %s for %x desc at %x desc=%x\n"), super ? _T("srp"):_T("urp"), 
+				addr, desc_addr, desc);
+#endif
+		*status |= MMU_FSLW_PTB;
+		return 0;
+	}
+	wp |= desc;
+	if ((desc & MMU_DES_USED) == 0)
+		phys_put_long(desc_addr, desc | MMU_DES_USED);
+
+	/* fetch page table descriptor */
+	if (mmu_pagesize_8k) {
+		i = (addr >> 11) & 0x7c;
+		desc_addr = (desc & MMU_PTR_PAGE_ADDR_MASK_8) + i;
+	} else {
+		i = (addr >> 10) & 0xfc;
+		desc_addr = (desc & MMU_PTR_PAGE_ADDR_MASK_4) + i;
+	}
+
+	desc = phys_get_long(desc_addr);
+	if ((desc & 3) == 2) {
+		/* indirect */
+		desc_addr = desc & MMU_PAGE_INDIRECT_MASK;
+		desc = phys_get_long(desc_addr);
+	}
+	if ((desc & 1) == 0) {
+#if MMUDEBUG > 2
+		write_log(_T("MMU: invalid page descriptor log=%0x desc=%08x @%08x\n"), addr, desc, desc_addr);
+#endif
+		if ((desc & 3) == 2) {
+			*status |= MMU_FSLW_IL;
+#if MMUDEBUG > 1
+			write_log(_T("MMU: double indirect descriptor log=%0x desc=%08x @%08x\n"), addr, desc, desc_addr);
+#endif	
+		} else {
+			*status |= MMU_FSLW_PF;
+		}
+		return desc;
+	}
+
+	desc |= wp & MMU_DES_WP;
+	if (write) {
+		if (desc & MMU_DES_WP) {
+			if ((desc & MMU_DES_USED) == 0) {
+				desc |= MMU_DES_USED;
+				phys_put_long(desc_addr, desc);
+			}
+		} else if ((desc & (MMU_DES_USED|MMU_DES_MODIFIED)) !=
+				   (MMU_DES_USED|MMU_DES_MODIFIED)) {
+			desc |= MMU_DES_USED|MMU_DES_MODIFIED;
+			phys_put_long(desc_addr, desc);
+		}
+	} else {
+		if ((desc & MMU_DES_USED) == 0) {
+			desc |= MMU_DES_USED;
+			phys_put_long(desc_addr, desc);
+		}
+	}
+	return desc;
+}
+
+static void misalignednotfirst(uaecptr addr)
+{
+#if MMUDEBUGMISC > 0
+	write_log (_T("misalignednotfirst %08x -> %08x %08X\n"), regs.mmu_fault_addr, addr, regs.instruction_pc);
+#endif
+	regs.mmu_fault_addr = addr;
+	regs.mmu_fslw |= MMU_FSLW_MA;
+	regs.mmu_ssw |= MMU_SSW_MA;
+}
+
+static void misalignednotfirstcheck(uaecptr addr)
+{
+	if (regs.mmu_fault_addr == addr)
+		return;
+	misalignednotfirst (addr);
+}
+
+uae_u16 REGPARAM2 mmu_get_word_unaligned(uaecptr addr, bool data, bool rmw)
+{
+	uae_u16 res;
+
+	res = (uae_u16)mmu_get_byte(addr, data, sz_word, rmw) << 8;
+	SAVE_EXCEPTION;
+	TRY(prb) {
+		res |= mmu_get_byte(addr + 1, data, sz_word, rmw);
+		RESTORE_EXCEPTION;
+	}
+	CATCH(prb) {
+		RESTORE_EXCEPTION;
+		misalignednotfirst(addr);
+		THROW_AGAIN(prb);
+	} ENDTRY
+	return res;
+}
+
+uae_u32 REGPARAM2 mmu_get_long_unaligned(uaecptr addr, bool data, bool rmw)
+{
+	uae_u32 res;
+
+	if (likely(!(addr & 1))) {
+		res = (uae_u32)mmu_get_word(addr, data, sz_long, rmw) << 16;
+		SAVE_EXCEPTION;
+		TRY(prb) {
+			res |= mmu_get_word(addr + 2, data, sz_long, rmw);
+			RESTORE_EXCEPTION;
+		}
+		CATCH(prb) {
+			RESTORE_EXCEPTION;
+			misalignednotfirst(addr);
+			THROW_AGAIN(prb);
+		} ENDTRY
+	} else {
+		res = (uae_u32)mmu_get_byte(addr, data, sz_long, rmw) << 8;
+		SAVE_EXCEPTION;
+		TRY(prb) {
+			res = (res | mmu_get_byte(addr + 1, data, sz_long, rmw)) << 8;
+			res = (res | mmu_get_byte(addr + 2, data, sz_long, rmw)) << 8;
+			res |= mmu_get_byte(addr + 3, data, sz_long, rmw);
+			RESTORE_EXCEPTION;
+		}
+		CATCH(prb) {
+			RESTORE_EXCEPTION;
+			misalignednotfirst(addr);
+			THROW_AGAIN(prb);
+		} ENDTRY
+	}
+	return res;
+}
+
+uae_u32 REGPARAM2 mmu_get_ilong_unaligned(uaecptr addr)
+{
+	uae_u32 res;
+
+	if (likely(!(addr & 1))) {
+		res = (uae_u32)mmu_get_iword(addr, sz_long) << 16;
+		SAVE_EXCEPTION;
+		TRY(prb) {
+			res |= mmu_get_iword(addr + 2, sz_long);
+			RESTORE_EXCEPTION;
+		}
+		CATCH(prb) {
+			RESTORE_EXCEPTION;
+			misalignednotfirst(addr);
+			THROW_AGAIN(prb);
+		} ENDTRY
+	}
+	return res;
+}
+
+uae_u16 REGPARAM2 mmu_get_lrmw_word_unaligned(uaecptr addr)
+{
+	uae_u16 res;
+
+	res = (uae_u16)mmu_get_user_byte(addr, regs.s != 0, true, true, sz_word) << 8;
+	SAVE_EXCEPTION;
+	TRY(prb) {
+		res |= mmu_get_user_byte(addr + 1, regs.s != 0, true, true, sz_word);
+		RESTORE_EXCEPTION;
+	}
+	CATCH(prb) {
+		RESTORE_EXCEPTION;
+		misalignednotfirst(addr);
+		THROW_AGAIN(prb);
+	} ENDTRY
+	return res;
+}
+
+uae_u32 REGPARAM2 mmu_get_lrmw_long_unaligned(uaecptr addr)
+{
+	uae_u32 res;
+
+	if (likely(!(addr & 1))) {
+		res = (uae_u32)mmu_get_user_word(addr, regs.s != 0, true, true, sz_long) << 16;
+		SAVE_EXCEPTION;
+		TRY(prb) {
+			res |= mmu_get_user_word(addr + 2, regs.s != 0, true, true, sz_long);
+			RESTORE_EXCEPTION;
+		}
+		CATCH(prb) {
+			RESTORE_EXCEPTION;
+			misalignednotfirst(addr);
+			THROW_AGAIN(prb);
+		} ENDTRY
+	} else {
+		res = (uae_u32)mmu_get_user_byte(addr, regs.s != 0, true, true, sz_long) << 8;
+		SAVE_EXCEPTION;
+		TRY(prb) {
+			res = (res | mmu_get_user_byte(addr + 1, regs.s != 0, true, true, sz_long)) << 8;
+			res = (res | mmu_get_user_byte(addr + 2, regs.s != 0, true, true, sz_long)) << 8;
+			res |= mmu_get_user_byte(addr + 3, regs.s != 0, true, true, sz_long);
+			RESTORE_EXCEPTION;
+		}
+		CATCH(prb) {
+			RESTORE_EXCEPTION;
+			misalignednotfirst(addr);
+			THROW_AGAIN(prb);
+		} ENDTRY
+	}
+	return res;
+}
+uae_u8 REGPARAM2 mmu_get_byte_slow(uaecptr addr, bool super, bool data,
+						 int size, bool rmw, struct mmu_atc_line *cl)
+{
+	uae_u32 status;
+	if (!mmu_fill_atc_try(addr, super, data, 0, cl, &status)) {
+		mmu_bus_error(addr, mmu_get_fc(super, data), 0, size, rmw, status, false);
+		return 0;
+	}
+	return x_phys_get_byte(mmu_get_real_address(addr, cl));
+}
+
+uae_u16 REGPARAM2 mmu_get_word_slow(uaecptr addr, bool super, bool data,
+						  int size, bool rmw, struct mmu_atc_line *cl)
+{
+	uae_u32 status;
+	if (!mmu_fill_atc_try(addr, super, data, 0, cl, &status)) {
+		mmu_bus_error(addr, mmu_get_fc(super, data), 0, size, rmw, status, false);
+		return 0;
+	}
+	return x_phys_get_word(mmu_get_real_address(addr, cl));
+}
+uae_u16 REGPARAM2 mmu_get_iword_slow(uaecptr addr, bool super,
+	int size, struct mmu_atc_line *cl)
+{
+	uae_u32 status;
+	if (!mmu_fill_atc_try(addr, super, false, 0, cl, &status)) {
+		mmu_bus_error(addr, mmu_get_fc(super, false), 0, size, false, status, false);
+		return 0;
+	}
+	return x_phys_get_iword(mmu_get_real_address(addr, cl));
+}
+
+uae_u32 REGPARAM2 mmu_get_long_slow(uaecptr addr, bool super, bool data,
+						  int size, bool rmw, struct mmu_atc_line *cl)
+{
+	uae_u32 status;
+	if (!mmu_fill_atc_try(addr, super, data, 0, cl, &status)) {
+		mmu_bus_error(addr, mmu_get_fc(super, data), 0, size, rmw, status, false);
+		return 0;
+	}
+	return x_phys_get_long(mmu_get_real_address(addr, cl));
+}
+uae_u32 REGPARAM2 mmu_get_ilong_slow(uaecptr addr, bool super,
+	int size, struct mmu_atc_line *cl)
+{
+	uae_u32 status;
+	if (!mmu_fill_atc_try(addr, super, false, 0, cl, &status)) {
+		mmu_bus_error(addr, mmu_get_fc(super, false), 0, size, false, status, false);
+		return 0;
+	}
+	return x_phys_get_ilong(mmu_get_real_address(addr, cl));
+}
+
+void REGPARAM2 mmu_put_long_unaligned(uaecptr addr, uae_u32 val, bool data, bool rmw)
+{
+	SAVE_EXCEPTION;
+	TRY(prb) {
+		if (likely(!(addr & 1))) {
+			mmu_put_word(addr, val >> 16, data, sz_long, rmw);
+			mmu_put_word(addr + 2, val, data, sz_long, rmw);
+		} else {
+			mmu_put_byte(addr, val >> 24, data, sz_long, rmw);
+			mmu_put_byte(addr + 1, val >> 16, data, sz_long, rmw);
+			mmu_put_byte(addr + 2, val >> 8, data, sz_long, rmw);
+			mmu_put_byte(addr + 3, val, data, sz_long, rmw);
+		}
+		RESTORE_EXCEPTION;
+	}
+	CATCH(prb) {
+		RESTORE_EXCEPTION;
+		regs.wb3_data = val;
+		misalignednotfirstcheck(addr);
+		THROW_AGAIN(prb);
+	} ENDTRY
+}
+
+void REGPARAM2 mmu_put_word_unaligned(uaecptr addr, uae_u16 val, bool data, bool rmw)
+{
+	SAVE_EXCEPTION;
+	TRY(prb) {
+		mmu_put_byte(addr, val >> 8, data, sz_word, rmw);
+		mmu_put_byte(addr + 1, val, data, sz_word, rmw);
+		RESTORE_EXCEPTION;
+	}
+	CATCH(prb) {
+		RESTORE_EXCEPTION;
+		regs.wb3_data = val;
+		misalignednotfirstcheck(addr);
+		THROW_AGAIN(prb);
+	} ENDTRY
+}
+
+void REGPARAM2 mmu_put_byte_slow(uaecptr addr, uae_u8 val, bool super, bool data,
+								 int size, bool rmw, struct mmu_atc_line *cl)
+{
+	uae_u32 status;
+	if (!mmu_fill_atc_try(addr, super, data, 1, cl, &status)) {
+		regs.wb3_data = val;
+		mmu_bus_error(addr, mmu_get_fc(super, data), 1, size, rmw, status, false);
+		return;
+	}
+	x_phys_put_byte(mmu_get_real_address(addr, cl), val);
+}
+
+void REGPARAM2 mmu_put_word_slow(uaecptr addr, uae_u16 val, bool super, bool data,
+								 int size, bool rmw, struct mmu_atc_line *cl)
+{
+	uae_u32 status;
+	if (!mmu_fill_atc_try(addr, super, data, 1, cl, &status)) {
+		regs.wb3_data = val;
+		mmu_bus_error(addr, mmu_get_fc(super, data), 1, size, rmw, status, false);
+		return;
+	}
+	x_phys_put_word(mmu_get_real_address(addr, cl), val);
+}
+
+void REGPARAM2 mmu_put_long_slow(uaecptr addr, uae_u32 val, bool super, bool data,
+								 int size, bool rmw, struct mmu_atc_line *cl)
+{
+	uae_u32 status;
+	if (!mmu_fill_atc_try(addr, super, data, 1, cl, &status)) {
+		regs.wb3_data = val;
+		mmu_bus_error(addr, mmu_get_fc(super, data), 1, size, rmw, status, false);
+		return;
+	}
+	x_phys_put_long(mmu_get_real_address(addr, cl), val);
+}
+
+uae_u32 REGPARAM2 sfc_get_long(uaecptr addr)
+{
+	bool super = (regs.sfc & 4) != 0;
+	bool data = true;
+	uae_u32 res;
+
+	ismoves = true;
+	if (likely(!is_unaligned(addr, 4))) {
+		res = mmu_get_user_long(addr, super, data, false, sz_long);
+	} else {
+		if (likely(!(addr & 1))) {
+			res = (uae_u32)mmu_get_user_word(addr, super, data, false, sz_long) << 16;
+			SAVE_EXCEPTION;
+			TRY(prb) {
+				res |= mmu_get_user_word(addr + 2, super, data, false, sz_long);
+				RESTORE_EXCEPTION;
+			}
+			CATCH(prb) {
+				RESTORE_EXCEPTION;
+				misalignednotfirst(addr);
+				THROW_AGAIN(prb);
+			} ENDTRY
+		} else {
+			res = (uae_u32)mmu_get_user_byte(addr, super, data, false, sz_long) << 8;
+			SAVE_EXCEPTION;
+			TRY(prb) {
+				res = (res | mmu_get_user_byte(addr + 1, super, data, false, sz_long)) << 8;
+				res = (res | mmu_get_user_byte(addr + 2, super, data, false, sz_long)) << 8;
+				res |= mmu_get_user_byte(addr + 3, super, data, false, sz_long);
+				RESTORE_EXCEPTION;
+			}
+			CATCH(prb) {
+				RESTORE_EXCEPTION;
+				misalignednotfirst(addr);
+				THROW_AGAIN(prb);
+			} ENDTRY
+		}
+	}
+
+	ismoves = false;
+	return res;
+}
+
+uae_u16 REGPARAM2 sfc_get_word(uaecptr addr)
+{
+	bool super = (regs.sfc & 4) != 0;
+	bool data = true;
+	uae_u16 res;
+
+	ismoves = true;
+	if (likely(!is_unaligned(addr, 2))) {
+		res = mmu_get_user_word(addr, super, data, false, sz_word);
+	} else {
+		res = (uae_u16)mmu_get_user_byte(addr, super, data, false, sz_word) << 8;
+		SAVE_EXCEPTION;
+		TRY(prb) {
+			res |= mmu_get_user_byte(addr + 1, super, data, false, sz_word);
+			RESTORE_EXCEPTION;
+		}
+		CATCH(prb) {
+			RESTORE_EXCEPTION;
+			misalignednotfirst(addr);
+			THROW_AGAIN(prb);
+		} ENDTRY
+	}
+	ismoves = false;
+	return res;
+}
+
+uae_u8 REGPARAM2 sfc_get_byte(uaecptr addr)
+{
+	bool super = (regs.sfc & 4) != 0;
+	bool data = true;
+	uae_u8 res;
+	
+	ismoves = true;
+	res = mmu_get_user_byte(addr, super, data, false, sz_byte);
+	ismoves = false;
+	return res;
+}
+
+void REGPARAM2 dfc_put_long(uaecptr addr, uae_u32 val)
+{
+	bool super = (regs.dfc & 4) != 0;
+	bool data = true;
+
+	ismoves = true;
+	SAVE_EXCEPTION;
+	TRY(prb) {
+		if (likely(!is_unaligned(addr, 4)))
+			mmu_put_user_long(addr, val, super, data, sz_long);
+		else if (likely(!(addr & 1))) {
+			mmu_put_user_word(addr, val >> 16, super, data, sz_long);
+			mmu_put_user_word(addr + 2, val, super, data, sz_long);
+		} else {
+			mmu_put_user_byte(addr, val >> 24, super, data, sz_long);
+			mmu_put_user_byte(addr + 1, val >> 16, super, data, sz_long);
+			mmu_put_user_byte(addr + 2, val >> 8, super, data, sz_long);
+			mmu_put_user_byte(addr + 3, val, super, data, sz_long);
+		}
+		RESTORE_EXCEPTION;
+	}
+	CATCH(prb) {
+		RESTORE_EXCEPTION;
+		regs.wb3_data = val;
+		misalignednotfirstcheck(addr);
+		THROW_AGAIN(prb);
+	} ENDTRY
+	ismoves = false;
+}
+
+void REGPARAM2 dfc_put_word(uaecptr addr, uae_u16 val)
+{
+	bool super = (regs.dfc & 4) != 0;
+	bool data = true;
+
+	ismoves = true;
+	SAVE_EXCEPTION;
+	TRY(prb) {
+		if (likely(!is_unaligned(addr, 2)))
+			mmu_put_user_word(addr, val, super, data, sz_word);
+		else {
+			mmu_put_user_byte(addr, val >> 8, super, data, sz_word);
+			mmu_put_user_byte(addr + 1, val, super, data, sz_word);
+		}
+		RESTORE_EXCEPTION;
+	}
+	CATCH(prb) {
+		RESTORE_EXCEPTION;
+		regs.wb3_data = val;
+		misalignednotfirstcheck(addr);
+		THROW_AGAIN(prb);
+	} ENDTRY
+	ismoves = false;
+}
+
+void REGPARAM2 dfc_put_byte(uaecptr addr, uae_u8 val)
+{
+	bool super = (regs.dfc & 4) != 0;
+	bool data = true;
+
+	ismoves = true;
+	SAVE_EXCEPTION;
+	TRY(prb) {
+		mmu_put_user_byte(addr, val, super, data, sz_byte);
+		RESTORE_EXCEPTION;
+	}
+	CATCH(prb) {
+		RESTORE_EXCEPTION;
+		regs.wb3_data = val;
+		THROW_AGAIN(prb);
+	} ENDTRY
+	ismoves = false;
+}
+
+void mmu_get_move16(uaecptr addr, uae_u32 *v, bool data, int size)
+{
+	struct mmu_atc_line *cl;
+	int i;
+	addr &= ~15;
+	for (i = 0; i < 4; i++) {
+		uaecptr addr2 = addr + i * 4;
+		//                                       addr,super,data
+		if ((!regs.mmu_enabled) || (mmu_match_ttr(addr2,regs.s != 0,data,false)!=TTR_NO_MATCH))
+			v[i] = x_phys_get_long(addr2);
+		else if (likely(mmu_lookup(addr2, data, false, &cl)))
+			v[i] = x_phys_get_long(mmu_get_real_address(addr2, cl));
+		else
+			v[i] = mmu_get_long_slow(addr2, regs.s != 0, data, size, false, cl);
+	}
+}
+
+void mmu_put_move16(uaecptr addr, uae_u32 *val, bool data, int size)
+{
+	struct mmu_atc_line *cl;
+	int i;
+	addr &= ~15;
+	for (i = 0; i < 4; i++) {
+		uaecptr addr2 = addr + i * 4;
+		//                                        addr,super,data
+		if ((!regs.mmu_enabled) || (mmu_match_ttr_write(addr2,regs.s != 0,data,val[i],size,false)==TTR_OK_MATCH))
+			x_phys_put_long(addr2,val[i]);
+		else if (likely(mmu_lookup(addr2, data, true, &cl)))
+			x_phys_put_long(mmu_get_real_address(addr2, cl), val[i]);
+		else
+			mmu_put_long_slow(addr2, val[i], regs.s != 0, data, size, false, cl);
+	}
+}
+
+
+void REGPARAM2 mmu_op_real(uae_u32 opcode, uae_u16 extra)
+{
+	bool super = (regs.dfc & 4) != 0;
+	DUNUSED(extra);
+	if ((opcode & 0xFE0) == 0x0500) { // PFLUSH
+		bool glob;
+		int regno;
+		//D(didflush = 0);
+		uae_u32 addr;
+		/* PFLUSH */
+		regno = opcode & 7;
+		glob = (opcode & 8) != 0;
+
+		if (opcode & 16) {
+#if MMUINSDEBUG > 1
+			write_log(_T("pflusha(%u,%u) PC=%08x\n"), glob, regs.dfc, m68k_getpc ());
+#endif
+			mmu_flush_atc_all(glob);
+		} else {
+			addr = m68k_areg(regs, regno);
+#if MMUINSDEBUG > 1
+			write_log(_T("pflush(%u,%u,%x) PC=%08x\n"), glob, regs.dfc, addr, m68k_getpc ());
+#endif
+			mmu_flush_atc(addr, super, glob);
+		}
+		flush_internals();
+#ifdef USE_JIT
+		flush_icache(0);
+#endif
+	} else if ((opcode & 0x0FD8) == 0x0548) { // PTEST (68040)
+		bool write;
+		int regno;
+		uae_u32 addr;
+
+		regno = opcode & 7;
+		write = (opcode & 32) == 0;
+		addr = m68k_areg(regs, regno);
+#if MMUINSDEBUG > 0
+		write_log(_T("PTEST%c (A%d) %08x DFC=%d\n"), write ? 'W' : 'R', regno, addr, regs.dfc);
+#endif
+		mmu_flush_atc(addr, super, true);
+		SAVE_EXCEPTION;
+		TRY(prb) {
+			struct mmu_atc_line *l;
+			uae_u32 desc;
+			bool data = (regs.dfc & 3) != 2;
+
+			if (mmu_match_ttr(addr,super,data, false)!=TTR_NO_MATCH) {
+				regs.mmusr = MMU_MMUSR_T | MMU_MMUSR_R;
+			} else {
+				uae_u32 status;
+				mmu_user_lookup(addr, super, data, write, &l);
+				desc = mmu_fill_atc(addr, super, data, write, l, &status);
+				if (!(l->valid)) {
+					regs.mmusr = MMU_MMUSR_B;
+				} else {
+					regs.mmusr = desc & (~0xfff|MMU_MMUSR_G|MMU_MMUSR_Ux|MMU_MMUSR_S|
+										 MMU_MMUSR_CM|MMU_MMUSR_M|MMU_MMUSR_W);
+					regs.mmusr |= MMU_MMUSR_R;
+				}
+			}
+		}
+		CATCH(prb) {
+			regs.mmusr = MMU_MMUSR_B;
+		} ENDTRY
+		RESTORE_EXCEPTION;
+#if MMUINSDEBUG > 0
+		write_log(_T("PTEST result: mmusr %08x\n"), regs.mmusr);
+#endif
+	} else if ((opcode & 0xFFB8) == 0xF588) { // PLPA (68060)
+		int write = (opcode & 0x40) == 0;
+		int regno = opcode & 7;
+		uae_u32 addr = m68k_areg (regs, regno);
+		bool data = (regs.dfc & 3) != 2;
+
+#if MMUINSDEBUG > 0
+		write_log(_T("PLPA%c param: %08x\n"), write ? 'W' : 'R', addr);
+#endif
+		if (mmu_match_ttr(addr,super,data,false)==TTR_NO_MATCH) {
+			m68k_areg (regs, regno) = mmu_translate (addr, super, data, write != 0);
+		}
+#if MMUINSDEBUG > 0
+		write_log(_T("PLPA%c result: %08x\n"), write ? 'W' : 'R', m68k_areg (regs, regno));
+#endif
+	} else {
+		op_illg (opcode);
+	}
+}
+
+// fixme : global parameter?
+void REGPARAM2 mmu_flush_atc(uaecptr addr, bool super, bool global)
+{
+	int way,type,index;
+
+	uaecptr tag = ((super ? 0x80000000 : 0) | (addr >> 1)) & mmu_tagmask;
+	if (mmu_pagesize_8k)
+		index=(addr & 0x0001E000)>>13;
+	else
+		index=(addr & 0x0000F000)>>12;
+	for (type=0;type 0
+		write_log (_T("MMU restarted MOVEM EA=%08X\n"), mmu040_movem_ea);
+#endif
+	}
+}
+
+void m68k_do_rte_mmu060 (uaecptr a7)
+{
+#if 0
+	mmu060_state = 2;
+#endif
+}
+
+void flush_mmu040 (uaecptr addr, int n)
+{
+}
+void m68k_do_rts_mmu040 (void)
+{
+	uaecptr stack = m68k_areg (regs, 7);
+	uaecptr newpc = get_long_mmu040 (stack);
+	m68k_areg (regs, 7) += 4;
+	m68k_setpc (newpc);
+}
+void m68k_do_bsr_mmu040 (uaecptr oldpc, uae_s32 offset)
+{
+	uaecptr newstack = m68k_areg (regs, 7) - 4;
+	put_long_mmu040 (newstack, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_incpci (offset);
+}
+
+void flush_mmu060 (uaecptr addr, int n)
+{
+}
+void m68k_do_rts_mmu060 (void)
+{
+	uaecptr stack = m68k_areg (regs, 7);
+	uaecptr newpc = get_long_mmu060 (stack);
+	m68k_areg (regs, 7) += 4;
+	m68k_setpc (newpc);
+}
+void m68k_do_bsr_mmu060 (uaecptr oldpc, uae_s32 offset)
+{
+	uaecptr newstack = m68k_areg (regs, 7) - 4;
+	put_long_mmu060 (newstack, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_incpci (offset);
+}
+
+void uae_mmu_put_lrmw (uaecptr addr, uae_u32 v, int size, int type)
+{
+	locked_rmw_cycle = true;
+	if (size == sz_byte) {
+		mmu_put_byte(addr, v, true, sz_byte, true);
+	} else if (size == sz_word) {
+		if (unlikely(is_unaligned(addr, 2))) {
+			mmu_put_word_unaligned(addr, v, true, true);
+		} else {
+			mmu_put_word(addr, v, true, sz_word, true);
+		}
+	} else {
+		if (unlikely(is_unaligned(addr, 4)))
+			mmu_put_long_unaligned(addr, v, true, true);
+		else
+			mmu_put_long(addr, v, true, sz_long, true);
+	}
+	locked_rmw_cycle = false;
+}
+uae_u32 uae_mmu_get_lrmw (uaecptr addr, int size, int type)
+{
+	uae_u32 v;
+	locked_rmw_cycle = true;
+	if (size == sz_byte) {
+		v = mmu_get_user_byte(addr, regs.s != 0, true, true, sz_byte);
+	} else if (size == sz_word) {
+		if (unlikely(is_unaligned(addr, 2))) {
+			v = mmu_get_lrmw_word_unaligned(addr);
+		} else {
+			v = mmu_get_user_word(addr, regs.s != 0, true, true, sz_word);
+		}
+	} else {
+		if (unlikely(is_unaligned(addr, 4)))
+			v = mmu_get_lrmw_long_unaligned(addr);
+		else
+			v = mmu_get_user_long(addr, regs.s != 0, true, true, sz_long);
+	}
+	locked_rmw_cycle = false;
+	return v;
+}
+
+uae_u32 REGPARAM2 mmu060_get_rmw_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width)
+{
+	uae_u32 tmp1, tmp2, res, mask;
+
+	offset &= 7;
+	mask = 0xffffffffu << (32 - width);
+	switch ((offset + width + 7) >> 3) {
+	case 1:
+		tmp1 = get_rmw_byte_mmu060 (src);
+		res = tmp1 << (24 + offset);
+		bdata[0] = tmp1 & ~(mask >> (24 + offset));
+		break;
+	case 2:
+		tmp1 = get_rmw_word_mmu060 (src);
+		res = tmp1 << (16 + offset);
+		bdata[0] = tmp1 & ~(mask >> (16 + offset));
+		break;
+	case 3:
+		tmp1 = get_rmw_word_mmu060 (src);
+		tmp2 = get_rmw_byte_mmu060 (src + 2);
+		res = tmp1 << (16 + offset);
+		bdata[0] = tmp1 & ~(mask >> (16 + offset));
+		res |= tmp2 << (8 + offset);
+		bdata[1] = tmp2 & ~(mask >> (8 + offset));
+		break;
+	case 4:
+		tmp1 = get_rmw_long_mmu060 (src);
+		res = tmp1 << offset;
+		bdata[0] = tmp1 & ~(mask >> offset);
+		break;
+	case 5:
+		tmp1 = get_rmw_long_mmu060 (src);
+		tmp2 = get_rmw_byte_mmu060 (src + 4);
+		res = tmp1 << offset;
+		bdata[0] = tmp1 & ~(mask >> offset);
+		res |= tmp2 >> (8 - offset);
+		bdata[1] = tmp2 & ~(mask << (8 - offset));
+		break;
+	default:
+		/* Panic? */
+		write_log (_T("x_get_bitfield() can't happen %d\n"), (offset + width + 7) >> 3);
+		res = 0;
+		break;
+	}
+	return res;
+}
+
+void REGPARAM2 mmu060_put_rmw_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width)
+{
+	offset = (offset & 7) + width;
+	switch ((offset + 7) >> 3) {
+	case 1:
+		put_rmw_byte_mmu060 (dst, bdata[0] | (val << (8 - offset)));
+		break;
+	case 2:
+		put_rmw_word_mmu060 (dst, bdata[0] | (val << (16 - offset)));
+		break;
+	case 3:
+		put_rmw_word_mmu060 (dst, bdata[0] | (val >> (offset - 16)));
+		put_rmw_byte_mmu060 (dst + 2, bdata[1] | (val << (24 - offset)));
+		break;
+	case 4:
+		put_rmw_long_mmu060 (dst, bdata[0] | (val << (32 - offset)));
+		break;
+	case 5:
+		put_rmw_long_mmu060 (dst, bdata[0] | (val >> (offset - 32)));
+		put_rmw_byte_mmu060 (dst + 4, bdata[1] | (val << (40 - offset)));
+		break;
+	default:
+		write_log (_T("x_put_bitfield() can't happen %d\n"), (offset + 7) >> 3);
+		break;
+	}
+}
+
+
+#ifndef __cplusplus
+jmp_buf __exbuf;
+int     __exvalue;
+#define MAX_TRY_STACK 256
+static int s_try_stack_size=0;
+static jmp_buf s_try_stack[MAX_TRY_STACK];
+jmp_buf* __poptry(void) {
+	if (s_try_stack_size>0) {
+        s_try_stack_size--;
+        if (s_try_stack_size == 0)
+            return NULL;
+        memcpy(&__exbuf,&s_try_stack[s_try_stack_size-1],sizeof(jmp_buf));
+        // fprintf(stderr,"pop %d jmpbuf=%08x\n",s_try_stack_size, s_try_stack[s_try_stack_size][0]);
+        return &s_try_stack[s_try_stack_size-1];
+    }
+	else {
+		fprintf(stderr,"try stack underflow...\n");
+	    // return (NULL);
+		abort();
+	}
+}
+void __pushtry(jmp_buf* j) {
+	if (s_try_stack_size0); }
+#endif
+
+#else
+
+void mmu_op(uae_u32 opcode, uae_u16 /*extra*/)
+{
+	if ((opcode & 0xFE0) == 0x0500) {
+		/* PFLUSH instruction */
+		flush_internals();
+	} else if ((opcode & 0x0FD8) == 0x548) {
+		/* PTEST instruction */
+	} else
+		op_illg(opcode);
+}
+
+#endif
+
+
+/*
+vim:ts=4:sw=4:
+*/
diff --git a/src/cpu/cpummu.h b/src/cpu/cpummu.h
new file mode 100644
index 0000000..e3a3ade
--- /dev/null
+++ b/src/cpu/cpummu.h
@@ -0,0 +1,927 @@
+/*
+ * cpummu.h - MMU emulation
+ *
+ * Copyright (c) 2001-2004 Milan Jurik of ARAnyM dev team (see AUTHORS)
+ * 
+ * Inspired by UAE MMU patch
+ *
+ * This file is part of the ARAnyM project which builds a new and powerful
+ * TOS/FreeMiNT compatible virtual machine running on almost any hardware.
+ *
+ * ARAnyM is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * ARAnyM is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with ARAnyM; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+
+#ifndef CPUMMU_H
+#define CPUMMU_H
+
+#include "mmu_common.h"
+
+#ifndef FULLMMU
+#define FULLMMU
+#endif
+
+#define DUNUSED(x)
+#define D
+#if DEBUG
+#define bug write_log
+#else
+#define bug
+#endif
+
+static __inline void flush_internals (void) { }
+
+extern int mmu060_state;
+
+extern int mmu040_movem;
+extern uaecptr mmu040_movem_ea;
+extern uae_u32 mmu040_move16[4];
+
+extern bool mmu_pagesize_8k;
+extern uae_u16 mmu_opcode;
+extern bool mmu_restart;
+extern bool mmu_ttr_enabled;
+
+//typedef uae_u8 flagtype;
+
+//static m68k_exception except;
+
+struct xttrx {
+    uae_u32 log_addr_base : 8;
+    uae_u32 log_addr_mask : 8;
+    uae_u32 enable : 1;
+    uae_u32 s_field : 2;
+    uae_u32 : 3;
+    uae_u32 usr1 : 1;
+    uae_u32 usr0 : 1;
+    uae_u32 : 1;
+    uae_u32 cmode : 2;
+    uae_u32 : 2;
+    uae_u32 write : 1;
+    uae_u32 : 2;
+};
+
+struct mmusr_t {
+   uae_u32 phys_addr : 20;
+   uae_u32 bus_err : 1;
+   uae_u32 global : 1;
+   uae_u32 usr1 : 1;
+   uae_u32 usr0 : 1;
+   uae_u32 super : 1;
+   uae_u32 cmode : 2;
+   uae_u32 modif : 1;
+   uae_u32 : 1;
+   uae_u32 write : 1;
+   uae_u32 ttrhit : 1;
+   uae_u32 resident : 1;
+};
+
+struct log_addr4 {
+   uae_u32 rif : 7;
+   uae_u32 pif : 7;
+   uae_u32 paif : 6;
+   uae_u32 poff : 12;
+};
+
+struct log_addr8 {
+  uae_u32 rif : 7;
+  uae_u32 pif : 7;
+  uae_u32 paif : 5;
+  uae_u32 poff : 13;
+};
+
+#define MMU_TEST_PTEST					1
+#define MMU_TEST_VERBOSE				2
+#define MMU_TEST_FORCE_TABLE_SEARCH		4
+#define MMU_TEST_NO_BUSERR				8
+
+extern void mmu_dump_atc(void);
+extern void mmu_dump_tables(void);
+
+#define MMU_TTR_LOGICAL_BASE				0xff000000
+#define MMU_TTR_LOGICAL_MASK				0x00ff0000
+#define MMU_TTR_BIT_ENABLED					(1 << 15)
+#define MMU_TTR_BIT_SFIELD_ENABLED			(1 << 14)
+#define MMU_TTR_BIT_SFIELD_SUPER			(1 << 13)
+#define MMU_TTR_SFIELD_SHIFT				13
+#define MMU_TTR_UX_MASK						((1 << 9) | (1 << 8))
+#define MMU_TTR_UX_SHIFT					8
+#define MMU_TTR_CACHE_MASK					((1 << 6) | (1 << 5))
+#define MMU_TTR_CACHE_SHIFT					5
+#define MMU_TTR_BIT_WRITE_PROTECT			(1 << 2)
+
+#define MMU_UDT_MASK	3
+#define MMU_PDT_MASK	3
+
+#define MMU_DES_WP			4
+#define MMU_DES_USED		8
+
+/* page descriptors only */
+#define MMU_DES_MODIFIED	16
+#define MMU_DES_SUPER		(1 << 7)
+#define MMU_DES_GLOBAL		(1 << 10)
+
+#define MMU_ROOT_PTR_ADDR_MASK			0xfffffe00
+#define MMU_PTR_PAGE_ADDR_MASK_8		0xffffff80
+#define MMU_PTR_PAGE_ADDR_MASK_4		0xffffff00
+
+#define MMU_PAGE_INDIRECT_MASK			0xfffffffc
+#define MMU_PAGE_ADDR_MASK_8			0xffffe000
+#define MMU_PAGE_ADDR_MASK_4			0xfffff000
+#define MMU_PAGE_UR_MASK_8				((1 << 12) | (1 << 11))
+#define MMU_PAGE_UR_MASK_4				(1 << 11)
+#define MMU_PAGE_UR_SHIFT				11
+
+#define MMU_MMUSR_ADDR_MASK				0xfffff000
+#define MMU_MMUSR_B						(1 << 11)
+#define MMU_MMUSR_G						(1 << 10)
+#define MMU_MMUSR_U1					(1 << 9)
+#define MMU_MMUSR_U0					(1 << 8)
+#define MMU_MMUSR_Ux					(MMU_MMUSR_U1 | MMU_MMUSR_U0)
+#define MMU_MMUSR_S						(1 << 7)
+#define MMU_MMUSR_CM					((1 << 6) | ( 1 << 5))
+#define MMU_MMUSR_M						(1 << 4)
+#define MMU_MMUSR_W						(1 << 2)
+#define MMU_MMUSR_T						(1 << 1)
+#define MMU_MMUSR_R						(1 << 0)
+
+#define TTR_I0	4
+#define TTR_I1	5
+#define TTR_D0	6
+#define TTR_D1	7
+
+#define TTR_NO_MATCH	0
+#define TTR_NO_WRITE	1
+#define TTR_OK_MATCH	2
+
+struct mmu_atc_line {
+	uaecptr tag; // tag is 16 or 17 bits S+logical
+	unsigned valid : 1;
+	unsigned global : 1;
+	unsigned modified : 1;
+	unsigned write_protect : 1;
+	uaecptr phys; // phys base address
+};
+
+/*
+ * 68040 ATC is a 4 way 16 slot associative address translation cache
+ * the 68040 has a DATA and an INSTRUCTION ATC.
+ * an ATC lookup may result in : a hit, a miss and a modified state.
+ * the 68060 can disable ATC allocation
+ * we must take care of 8k and 4k page size, index position is relative to page size
+ */
+
+#define ATC_WAYS 4
+#define ATC_SLOTS 16
+#define ATC_TYPE 2
+
+extern uae_u32 mmu_is_super;
+extern uae_u32 mmu_tagmask, mmu_pagemask;
+extern struct mmu_atc_line mmu_atc_array[ATC_TYPE][ATC_WAYS][ATC_SLOTS];
+
+/* Last matched ATC index, next lookup starts from this index as an optimization */
+extern int mmu_atc_ways;
+
+/*
+ * mmu access is a 4 step process:
+ * if mmu is not enabled just read physical
+ * check transparent region, if transparent, read physical
+ * check ATC (address translation cache), read immediatly if HIT
+ * read from mmu with the long path (and allocate ATC entry if needed)
+ */
+static ALWAYS_INLINE bool mmu_lookup(uaecptr addr, bool data, bool write,
+									  struct mmu_atc_line **cl)
+{
+	int way, i, index;
+	static int way_miss=0;
+
+	uae_u32 tag = (mmu_is_super | (addr >> 1)) & mmu_tagmask;
+	if (mmu_pagesize_8k)
+		index=(addr & 0x0001E000)>>13;
+	else
+		index=(addr & 0x0000F000)>>12;
+	for (i = 0; i < ATC_WAYS; i++) {
+		way = mmu_atc_ways;
+		// if we have this 
+		if ((tag == mmu_atc_array[data][way][index].tag) && (mmu_atc_array[data][way][index].valid)) {
+			*cl=&mmu_atc_array[data][way][index];
+			// if first write to this take slow path (but modify this slot)
+			if ((!mmu_atc_array[data][way][index].modified & write) || (mmu_atc_array[data][way][index].write_protect & write))
+				return false; 
+			return true;
+		}
+		mmu_atc_ways++;
+		mmu_atc_ways %= ATC_WAYS;
+	}
+	// we select a random way to void
+	*cl=&mmu_atc_array[data][way_miss%ATC_WAYS][index];
+	(*cl)->tag = tag;
+	way_miss++;
+	return false;
+}
+
+/*
+ */
+static ALWAYS_INLINE bool mmu_user_lookup(uaecptr addr, bool super, bool data,
+										   bool write, struct mmu_atc_line **cl)
+{
+	int way, i, index;
+	static int way_miss=0;
+
+	uae_u32 tag = ((super ? 0x80000000 : 0x00000000) | (addr >> 1)) & mmu_tagmask;
+	if (mmu_pagesize_8k)
+		index=(addr & 0x0001E000)>>13;
+	else
+		index=(addr & 0x0000F000)>>12;
+	for (i = 0; i < ATC_WAYS; i++) {
+		way = mmu_atc_ways;
+		// if we have this 
+		if ((tag == mmu_atc_array[data][way][index].tag) && (mmu_atc_array[data][way][index].valid)) {
+			*cl=&mmu_atc_array[data][way][index];
+			// if first write to this take slow path (but modify this slot)
+			if ((!mmu_atc_array[data][way][index].modified & write) || (mmu_atc_array[data][way][index].write_protect & write))
+				return false; 
+			return true;
+		}
+		mmu_atc_ways++;
+		mmu_atc_ways %= ATC_WAYS;
+	}
+	// we select a random way to void
+	*cl=&mmu_atc_array[data][way_miss%ATC_WAYS][index];
+	(*cl)->tag = tag;
+	way_miss++;
+	return false;
+}
+
+/* check if an address matches a ttr */
+STATIC_INLINE int mmu_do_match_ttr(uae_u32 ttr, uaecptr addr, bool super)
+{
+	if (ttr & MMU_TTR_BIT_ENABLED)	{	/* TTR enabled */
+		uae_u8 msb, mask;
+
+		msb = ((addr ^ ttr) & MMU_TTR_LOGICAL_BASE) >> 24;
+		mask = (ttr & MMU_TTR_LOGICAL_MASK) >> 16;
+
+		if (!(msb & ~mask)) {
+
+			if ((ttr & MMU_TTR_BIT_SFIELD_ENABLED) == 0) {
+				if (((ttr & MMU_TTR_BIT_SFIELD_SUPER) == 0) != (super == 0)) {
+					return TTR_NO_MATCH;
+				}
+			}
+
+			return (ttr & MMU_TTR_BIT_WRITE_PROTECT) ? TTR_NO_WRITE : TTR_OK_MATCH;
+		}
+	}
+	return TTR_NO_MATCH;
+}
+
+STATIC_INLINE int mmu_match_ttr(uaecptr addr, bool super, bool data, bool rmw)
+{
+	int res;
+
+	if (!mmu_ttr_enabled)
+		return TTR_NO_MATCH;
+	if (data) {
+		res = mmu_do_match_ttr(regs.dtt0, addr, super);
+		if (res == TTR_NO_MATCH)
+			res = mmu_do_match_ttr(regs.dtt1, addr, super);
+	} else {
+		res = mmu_do_match_ttr(regs.itt0, addr, super);
+		if (res == TTR_NO_MATCH)
+			res = mmu_do_match_ttr(regs.itt1, addr, super);
+	}
+	return res;
+}
+extern void mmu_bus_error_ttr_write_fault(uaecptr addr, bool super, bool data, uae_u32 val, int size, bool rmw);
+STATIC_INLINE int mmu_match_ttr_write(uaecptr addr, bool super, bool data,  uae_u32 val, int size, bool rmw)
+{
+	if (!mmu_ttr_enabled)
+		return TTR_NO_MATCH;
+	int res = mmu_match_ttr(addr, super, data, rmw);
+	if (res == TTR_NO_WRITE)
+		mmu_bus_error_ttr_write_fault(addr, super, data, val, size, rmw);
+	return res;
+}
+
+extern void mmu_tt_modified (void);
+
+extern uae_u32 REGPARAM3 mmu060_get_rmw_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM;
+extern void REGPARAM3 mmu060_put_rmw_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM;
+
+extern uae_u16 REGPARAM3 mmu_get_word_unaligned(uaecptr addr, bool data, bool rmw) REGPARAM;
+extern uae_u32 REGPARAM3 mmu_get_long_unaligned(uaecptr addr, bool data, bool rmw) REGPARAM;
+extern uae_u16 REGPARAM2 mmu_get_lrmw_word_unaligned(uaecptr addr) REGPARAM;
+extern uae_u32 REGPARAM2 mmu_get_lrmw_long_unaligned(uaecptr addr) REGPARAM;
+
+extern uae_u32 REGPARAM3 mmu_get_ilong_unaligned(uaecptr addr) REGPARAM;
+
+extern uae_u8 REGPARAM3 mmu_get_byte_slow(uaecptr addr, bool super, bool data,
+										  int size, bool rmw, struct mmu_atc_line *cl) REGPARAM;
+extern uae_u16 REGPARAM3 mmu_get_word_slow(uaecptr addr, bool super, bool data,
+										   int size, bool rmw, struct mmu_atc_line *cl) REGPARAM;
+extern uae_u32 REGPARAM3 mmu_get_long_slow(uaecptr addr, bool super, bool data,
+										   int size, bool rmw, struct mmu_atc_line *cl) REGPARAM;
+
+extern uae_u16 REGPARAM3 mmu_get_iword_slow(uaecptr addr, bool super,
+										   int size, struct mmu_atc_line *cl) REGPARAM;
+extern uae_u32 REGPARAM3 mmu_get_ilong_slow(uaecptr addr, bool super,
+										   int size, struct mmu_atc_line *cl) REGPARAM;
+
+extern void REGPARAM3 mmu_put_word_unaligned(uaecptr addr, uae_u16 val, bool data, bool rmw) REGPARAM;
+extern void REGPARAM3 mmu_put_long_unaligned(uaecptr addr, uae_u32 val, bool data, bool rmw) REGPARAM;
+
+extern void REGPARAM3 mmu_put_byte_slow(uaecptr addr, uae_u8 val, bool super, bool data,
+										int size, bool rmw, struct mmu_atc_line *cl) REGPARAM;
+extern void REGPARAM3 mmu_put_word_slow(uaecptr addr, uae_u16 val, bool super, bool data,
+										int size, bool rmw, struct mmu_atc_line *cl) REGPARAM;
+extern void REGPARAM3 mmu_put_long_slow(uaecptr addr, uae_u32 val, bool super, bool data,
+										int size, bool rmw, struct mmu_atc_line *cl) REGPARAM;
+
+extern void mmu_make_transparent_region(uaecptr baseaddr, uae_u32 size, int datamode);
+
+#define FC_DATA		(regs.s ? 5 : 1)
+#define FC_INST		(regs.s ? 6 : 2)
+
+extern uaecptr REGPARAM3 mmu_translate(uaecptr addr, bool super, bool data, bool write) REGPARAM;
+extern void mmu_bus_error(uaecptr addr, int fc, bool write, int size, bool rmw, uae_u32 status, bool nonmmu);
+
+extern uae_u32 REGPARAM3 sfc_get_long(uaecptr addr) REGPARAM;
+extern uae_u16 REGPARAM3 sfc_get_word(uaecptr addr) REGPARAM;
+extern uae_u8 REGPARAM3 sfc_get_byte(uaecptr addr) REGPARAM;
+extern void REGPARAM3 dfc_put_long(uaecptr addr, uae_u32 val) REGPARAM;
+extern void REGPARAM3 dfc_put_word(uaecptr addr, uae_u16 val) REGPARAM;
+extern void REGPARAM3 dfc_put_byte(uaecptr addr, uae_u8 val) REGPARAM;
+
+#define sfc040_get_long sfc_get_long
+#define sfc040_get_word sfc_get_word
+#define sfc040_get_byte sfc_get_byte
+#define dfc040_put_long dfc_put_long
+#define dfc040_put_word dfc_put_word
+#define dfc040_put_byte dfc_put_byte
+
+#define sfc060_get_long sfc_get_long
+#define sfc060_get_word sfc_get_word
+#define sfc060_get_byte sfc_get_byte
+#define dfc060_put_long dfc_put_long
+#define dfc060_put_word dfc_put_word
+#define dfc060_put_byte dfc_put_byte
+
+extern void uae_mmu_put_lrmw (uaecptr addr, uae_u32 v, int size, int type);
+extern uae_u32 uae_mmu_get_lrmw (uaecptr addr, int size, int type);
+
+extern void REGPARAM3 mmu_flush_atc(uaecptr addr, bool super, bool global) REGPARAM;
+extern void REGPARAM3 mmu_flush_atc_all(bool global) REGPARAM;
+extern void REGPARAM3 mmu_op_real(uae_u32 opcode, uae_u16 extra) REGPARAM;
+
+extern void REGPARAM3 mmu_reset(void) REGPARAM;
+extern void REGPARAM3 mmu_set_funcs(void) REGPARAM;
+extern void REGPARAM3 mmu_set_tc(uae_u16 tc) REGPARAM;
+extern void REGPARAM3 mmu_set_super(bool super) REGPARAM;
+
+static ALWAYS_INLINE uaecptr mmu_get_real_address(uaecptr addr, struct mmu_atc_line *cl)
+{
+    return cl->phys | (addr & mmu_pagemask);
+}
+
+extern void mmu_get_move16(uaecptr addr, uae_u32 *v, bool data, int size);
+extern void mmu_put_move16(uaecptr addr, uae_u32 *val, bool data, int size);
+
+static ALWAYS_INLINE uae_u32 mmu_get_long(uaecptr addr, bool data, int size, bool rmw)
+{
+	struct mmu_atc_line *cl;
+
+	//                                       addr,super,data
+	if ((!regs.mmu_enabled) || (mmu_match_ttr(addr,regs.s != 0,data,rmw)!=TTR_NO_MATCH))
+		return x_phys_get_long(addr);
+	if (likely(mmu_lookup(addr, data, false, &cl)))
+		return x_phys_get_long(mmu_get_real_address(addr, cl));
+	return mmu_get_long_slow(addr, regs.s != 0, data, size, rmw, cl);
+}
+
+static ALWAYS_INLINE uae_u32 mmu_get_ilong(uaecptr addr, int size)
+{
+	struct mmu_atc_line *cl;
+
+	//                                       addr,super,data
+	if ((!regs.mmu_enabled) || (mmu_match_ttr(addr, regs.s != 0, false, false) != TTR_NO_MATCH))
+		return x_phys_get_ilong(addr);
+	if (likely(mmu_lookup(addr, false, false, &cl)))
+		return x_phys_get_ilong(mmu_get_real_address(addr, cl));
+	return mmu_get_ilong_slow(addr, regs.s != 0, size, cl);
+}
+
+static ALWAYS_INLINE uae_u16 mmu_get_word(uaecptr addr, bool data, int size, bool rmw)
+{
+	struct mmu_atc_line *cl;
+
+	//                                       addr,super,data
+	if ((!regs.mmu_enabled) || (mmu_match_ttr(addr,regs.s != 0,data,rmw)!=TTR_NO_MATCH))
+		return x_phys_get_word(addr);
+	if (likely(mmu_lookup(addr, data, false, &cl)))
+		return x_phys_get_word(mmu_get_real_address(addr, cl));
+	return mmu_get_word_slow(addr, regs.s != 0, data, size, rmw, cl);
+}
+
+static ALWAYS_INLINE uae_u16 mmu_get_iword(uaecptr addr, int size)
+{
+	struct mmu_atc_line *cl;
+
+	//                                       addr,super,data
+	if ((!regs.mmu_enabled) || (mmu_match_ttr(addr, regs.s != 0, false, false) != TTR_NO_MATCH))
+		return x_phys_get_iword(addr);
+	if (likely(mmu_lookup(addr, false, false, &cl)))
+		return x_phys_get_iword(mmu_get_real_address(addr, cl));
+	return mmu_get_iword_slow(addr, regs.s != 0, size, cl);
+}
+
+static ALWAYS_INLINE uae_u8 mmu_get_byte(uaecptr addr, bool data, int size, bool rmw)
+{
+	struct mmu_atc_line *cl;
+
+	//                                       addr,super,data
+	if ((!regs.mmu_enabled) || (mmu_match_ttr(addr,regs.s != 0,data,rmw)!=TTR_NO_MATCH))
+		return x_phys_get_byte(addr);
+	if (likely(mmu_lookup(addr, data, false, &cl)))
+		return x_phys_get_byte(mmu_get_real_address(addr, cl));
+	return mmu_get_byte_slow(addr, regs.s != 0, data, size, rmw, cl);
+}
+
+static ALWAYS_INLINE void mmu_put_long(uaecptr addr, uae_u32 val, bool data, int size, bool rmw)
+{
+	struct mmu_atc_line *cl;
+
+	//                                        addr,super,data
+	if ((!regs.mmu_enabled) || mmu_match_ttr_write(addr,regs.s != 0,data,val,size,rmw)==TTR_OK_MATCH) {
+		x_phys_put_long(addr,val);
+		return;
+	}
+	if (likely(mmu_lookup(addr, data, true, &cl)))
+		x_phys_put_long(mmu_get_real_address(addr, cl), val);
+	else
+		mmu_put_long_slow(addr, val, regs.s != 0, data, size, rmw, cl);
+}
+
+static ALWAYS_INLINE void mmu_put_word(uaecptr addr, uae_u16 val, bool data, int size, bool rmw)
+{
+	struct mmu_atc_line *cl;
+
+	//                                        addr,super,data
+	if ((!regs.mmu_enabled) || (mmu_match_ttr_write(addr,regs.s != 0,data,val,size,rmw)==TTR_OK_MATCH)) {
+		x_phys_put_word(addr,val);
+		return;
+	}
+	if (likely(mmu_lookup(addr, data, true, &cl)))
+		x_phys_put_word(mmu_get_real_address(addr, cl), val);
+	else
+		mmu_put_word_slow(addr, val, regs.s != 0, data, size, rmw, cl);
+}
+
+static ALWAYS_INLINE void mmu_put_byte(uaecptr addr, uae_u8 val, bool data, int size, bool rmw)
+{
+	struct mmu_atc_line *cl;
+
+	//                                        addr,super,data
+	if ((!regs.mmu_enabled) || (mmu_match_ttr_write(addr,regs.s != 0,data,val,size,rmw)==TTR_OK_MATCH)) {
+		x_phys_put_byte(addr,val);
+		return;
+	}
+	if (likely(mmu_lookup(addr, data, true, &cl)))
+		x_phys_put_byte(mmu_get_real_address(addr, cl), val);
+	else
+		mmu_put_byte_slow(addr, val, regs.s != 0, data, size, rmw, cl);
+}
+
+static ALWAYS_INLINE uae_u32 mmu_get_user_long(uaecptr addr, bool super, bool data, bool write, int size)
+{
+	struct mmu_atc_line *cl;
+
+	//                                       addr,super,data
+	if ((!regs.mmu_enabled) || (mmu_match_ttr(addr,super,data,false)!=TTR_NO_MATCH))
+		return x_phys_get_long(addr);
+	if (likely(mmu_user_lookup(addr, super, data, write, &cl)))
+		return x_phys_get_long(mmu_get_real_address(addr, cl));
+	return mmu_get_long_slow(addr, super, data, size, false, cl);
+}
+
+static ALWAYS_INLINE uae_u16 mmu_get_user_word(uaecptr addr, bool super, bool data, bool write, int size)
+{
+	struct mmu_atc_line *cl;
+
+	//                                       addr,super,data
+	if ((!regs.mmu_enabled) || (mmu_match_ttr(addr,super,data,false)!=TTR_NO_MATCH))
+		return x_phys_get_word(addr);
+	if (likely(mmu_user_lookup(addr, super, data, write, &cl)))
+		return x_phys_get_word(mmu_get_real_address(addr, cl));
+	return mmu_get_word_slow(addr, super, data, size, false, cl);
+}
+
+static ALWAYS_INLINE uae_u8 mmu_get_user_byte(uaecptr addr, bool super, bool data, bool write, int size)
+{
+	struct mmu_atc_line *cl;
+
+	//                                       addr,super,data
+	if ((!regs.mmu_enabled) || (mmu_match_ttr(addr,super,data,false)!=TTR_NO_MATCH))
+		return x_phys_get_byte(addr);
+	if (likely(mmu_user_lookup(addr, super, data, write, &cl)))
+		return x_phys_get_byte(mmu_get_real_address(addr, cl));
+	return mmu_get_byte_slow(addr, super, data, size, false, cl);
+}
+
+static ALWAYS_INLINE void mmu_put_user_long(uaecptr addr, uae_u32 val, bool super, bool data, int size)
+{
+	struct mmu_atc_line *cl;
+
+	//                                        addr,super,data
+	if ((!regs.mmu_enabled) || (mmu_match_ttr(addr,super,data,false)==TTR_OK_MATCH)) {
+		x_phys_put_long(addr,val);
+		return;
+	}
+	if (likely(mmu_user_lookup(addr, super, data, true, &cl)))
+		x_phys_put_long(mmu_get_real_address(addr, cl), val);
+	else
+		mmu_put_long_slow(addr, val, super, data, size, false, cl);
+}
+
+static ALWAYS_INLINE void mmu_put_user_word(uaecptr addr, uae_u16 val, bool super, bool data, int size)
+{
+	struct mmu_atc_line *cl;
+
+	//                                        addr,super,data
+	if ((!regs.mmu_enabled) || (mmu_match_ttr(addr,super,data,false)==TTR_OK_MATCH)) {
+		x_phys_put_word(addr,val);
+		return;
+	}
+	if (likely(mmu_user_lookup(addr, super, data, true, &cl)))
+		x_phys_put_word(mmu_get_real_address(addr, cl), val);
+	else
+		mmu_put_word_slow(addr, val, super, data, size, false, cl);
+}
+
+static ALWAYS_INLINE void mmu_put_user_byte(uaecptr addr, uae_u8 val, bool super, bool data, int size)
+{
+	struct mmu_atc_line *cl;
+
+	//                                        addr,super,data
+	if ((!regs.mmu_enabled) || (mmu_match_ttr(addr,super,data,false)==TTR_OK_MATCH)) {
+		x_phys_put_byte(addr,val);
+		return;
+	}
+	if (likely(mmu_user_lookup(addr, super, data, true, &cl)))
+		x_phys_put_byte(mmu_get_real_address(addr, cl), val);
+	else
+		mmu_put_byte_slow(addr, val, super, data, size, false, cl);
+}
+
+
+static ALWAYS_INLINE void HWput_l(uaecptr addr, uae_u32 l)
+{
+    put_long (addr, l);
+}
+static ALWAYS_INLINE void HWput_w(uaecptr addr, uae_u32 w)
+{
+    put_word (addr, w);
+}
+static ALWAYS_INLINE void HWput_b(uaecptr addr, uae_u32 b)
+{
+    put_byte (addr, b);
+}
+static ALWAYS_INLINE uae_u32 HWget_l(uaecptr addr)
+{
+    return get_long (addr);
+}
+static ALWAYS_INLINE uae_u32 HWget_w(uaecptr addr)
+{
+    return get_word (addr);
+}
+static ALWAYS_INLINE uae_u32 HWget_b(uaecptr addr)
+{
+    return get_byte (addr);
+}
+
+static ALWAYS_INLINE uae_u32 uae_mmu040_get_ilong(uaecptr addr)
+{
+	if (unlikely(is_unaligned(addr, 4)))
+		return mmu_get_ilong_unaligned(addr);
+	return mmu_get_ilong(addr, sz_long);
+}
+static ALWAYS_INLINE uae_u16 uae_mmu040_get_iword(uaecptr addr)
+{
+	return mmu_get_iword(addr, sz_word);
+}
+static ALWAYS_INLINE uae_u16 uae_mmu040_get_ibyte(uaecptr addr)
+{
+	return mmu_get_byte(addr, false, sz_byte, false);
+}
+static ALWAYS_INLINE uae_u32 uae_mmu040_get_long(uaecptr addr)
+{
+	if (unlikely(is_unaligned(addr, 4)))
+		return mmu_get_long_unaligned(addr, true, false);
+	return mmu_get_long(addr, true, sz_long, false);
+}
+static ALWAYS_INLINE uae_u16 uae_mmu040_get_word(uaecptr addr)
+{
+	if (unlikely(is_unaligned(addr, 2)))
+		return mmu_get_word_unaligned(addr, true, false);
+	return mmu_get_word(addr, true, sz_word, false);
+}
+static ALWAYS_INLINE uae_u8 uae_mmu040_get_byte(uaecptr addr)
+{
+	return mmu_get_byte(addr, true, sz_byte, false);
+}
+
+static ALWAYS_INLINE void uae_mmu040_put_word(uaecptr addr, uae_u16 val)
+{
+	if (unlikely(is_unaligned(addr, 2)))
+		mmu_put_word_unaligned(addr, val, true, false);
+	else
+		mmu_put_word(addr, val, true, sz_word, false);
+}
+static ALWAYS_INLINE void uae_mmu040_put_byte(uaecptr addr, uae_u8 val)
+{
+	mmu_put_byte(addr, val, true, sz_byte, false);
+}
+static ALWAYS_INLINE void uae_mmu040_put_long(uaecptr addr, uae_u32 val)
+{
+	if (unlikely(is_unaligned(addr, 4)))
+		mmu_put_long_unaligned(addr, val, true, false);
+	else
+		mmu_put_long(addr, val, true, sz_long, false);
+}
+
+
+static ALWAYS_INLINE uae_u32 uae_mmu060_get_ilong(uaecptr addr)
+{
+	if (unlikely(is_unaligned(addr, 4)))
+		return mmu_get_ilong_unaligned(addr);
+	return mmu_get_ilong(addr, sz_long);
+}
+static ALWAYS_INLINE uae_u16 uae_mmu060_get_iword(uaecptr addr)
+{
+	return mmu_get_iword(addr, sz_word);
+}
+static ALWAYS_INLINE uae_u16 uae_mmu060_get_ibyte(uaecptr addr)
+{
+	return mmu_get_byte(addr, false, sz_byte, false);
+}
+static ALWAYS_INLINE uae_u32 uae_mmu060_get_long(uaecptr addr, bool rmw)
+{
+	if (unlikely(is_unaligned(addr, 4)))
+		return mmu_get_long_unaligned(addr, true, rmw);
+	return mmu_get_long(addr, true, sz_long, rmw);
+}
+static ALWAYS_INLINE uae_u16 uae_mmu060_get_word(uaecptr addr, bool rmw)
+{
+	if (unlikely(is_unaligned(addr, 2)))
+		return mmu_get_word_unaligned(addr, true, rmw);
+	return mmu_get_word(addr, true, sz_word, rmw);
+}
+static ALWAYS_INLINE uae_u8 uae_mmu060_get_byte(uaecptr addr, bool rmw)
+{
+	return mmu_get_byte(addr, true, sz_byte, rmw);
+}
+static ALWAYS_INLINE void uae_mmu_get_move16(uaecptr addr, uae_u32 *val)
+{
+	// move16 is always aligned
+	mmu_get_move16(addr, val, true, 16);
+}
+
+static ALWAYS_INLINE void uae_mmu060_put_long(uaecptr addr, uae_u32 val, bool rmw)
+{
+	if (unlikely(is_unaligned(addr, 4)))
+		mmu_put_long_unaligned(addr, val, true, rmw);
+	else
+		mmu_put_long(addr, val, true, sz_long, rmw);
+}
+static ALWAYS_INLINE void uae_mmu060_put_word(uaecptr addr, uae_u16 val, bool rmw)
+{
+	if (unlikely(is_unaligned(addr, 2)))
+		mmu_put_word_unaligned(addr, val, true, rmw);
+	else
+		mmu_put_word(addr, val, true, sz_word, rmw);
+}
+static ALWAYS_INLINE void uae_mmu060_put_byte(uaecptr addr, uae_u8 val, bool rmw)
+{
+	mmu_put_byte(addr, val, true, sz_byte, rmw);
+}
+static ALWAYS_INLINE void uae_mmu_put_move16(uaecptr addr, uae_u32 *val)
+{
+	// move16 is always aligned
+	mmu_put_move16(addr, val, true, 16);
+}
+
+// normal 040
+STATIC_INLINE void put_byte_mmu040 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu040_put_byte (addr, v);
+}
+STATIC_INLINE void put_word_mmu040 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu040_put_word (addr, v);
+}
+STATIC_INLINE void put_long_mmu040 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu040_put_long (addr, v);
+}
+STATIC_INLINE uae_u32 get_byte_mmu040 (uaecptr addr)
+{
+    return uae_mmu040_get_byte (addr);
+}
+STATIC_INLINE uae_u32 get_word_mmu040 (uaecptr addr)
+{
+    return uae_mmu040_get_word (addr);
+}
+STATIC_INLINE uae_u32 get_long_mmu040 (uaecptr addr)
+{
+    return uae_mmu040_get_long (addr);
+}
+// normal 060
+STATIC_INLINE void put_byte_mmu060 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu060_put_byte (addr, v, false);
+}
+STATIC_INLINE void put_word_mmu060 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu060_put_word (addr, v, false);
+}
+STATIC_INLINE void put_long_mmu060 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu060_put_long (addr, v, false);
+}
+STATIC_INLINE uae_u32 get_byte_mmu060 (uaecptr addr)
+{
+    return uae_mmu060_get_byte (addr, false);
+}
+STATIC_INLINE uae_u32 get_word_mmu060 (uaecptr addr)
+{
+    return uae_mmu060_get_word (addr, false);
+}
+STATIC_INLINE uae_u32 get_long_mmu060 (uaecptr addr)
+{
+    return uae_mmu060_get_long (addr, false);
+}
+
+STATIC_INLINE void get_move16_mmu (uaecptr addr, uae_u32 *v)
+{
+    uae_mmu_get_move16 (addr, v);
+}
+STATIC_INLINE void put_move16_mmu (uaecptr addr, uae_u32 *v)
+{
+    uae_mmu_put_move16 (addr, v);
+}
+
+// locked rmw 060
+STATIC_INLINE void put_lrmw_byte_mmu060 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu_put_lrmw (addr, v, sz_byte, 1);
+}
+STATIC_INLINE void put_lrmw_word_mmu060 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu_put_lrmw (addr, v, sz_word, 1);
+}
+STATIC_INLINE void put_lrmw_long_mmu060 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu_put_lrmw (addr, v, sz_long, 1);
+}
+STATIC_INLINE uae_u32 get_lrmw_byte_mmu060 (uaecptr addr)
+{
+    return uae_mmu_get_lrmw (addr, sz_byte, 1);
+}
+STATIC_INLINE uae_u32 get_lrmw_word_mmu060 (uaecptr addr)
+{
+    return uae_mmu_get_lrmw (addr, sz_word, 1);
+}
+STATIC_INLINE uae_u32 get_lrmw_long_mmu060 (uaecptr addr)
+{
+    return uae_mmu_get_lrmw (addr, sz_long, 1);
+}
+// normal rmw 060
+STATIC_INLINE void put_rmw_byte_mmu060 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu060_put_byte (addr, v, true);
+}
+STATIC_INLINE void put_rmw_word_mmu060 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu060_put_word (addr, v, true);
+}
+STATIC_INLINE void put_rmw_long_mmu060 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu060_put_long (addr, v, true);
+}
+STATIC_INLINE uae_u32 get_rmw_byte_mmu060 (uaecptr addr)
+{
+    return uae_mmu060_get_byte (addr, true);
+}
+STATIC_INLINE uae_u32 get_rmw_word_mmu060 (uaecptr addr)
+{
+    return uae_mmu060_get_word (addr, true);
+}
+STATIC_INLINE uae_u32 get_rmw_long_mmu060 (uaecptr addr)
+{
+    return uae_mmu060_get_long (addr, true);
+}
+// locked rmw 040
+STATIC_INLINE void put_lrmw_byte_mmu040 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu_put_lrmw (addr, v, sz_byte, 0);
+}
+STATIC_INLINE void put_lrmw_word_mmu040 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu_put_lrmw (addr, v, sz_word, 0);
+}
+STATIC_INLINE void put_lrmw_long_mmu040 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu_put_lrmw (addr, v, sz_long, 0);
+}
+STATIC_INLINE uae_u32 get_lrmw_byte_mmu040 (uaecptr addr)
+{
+    return uae_mmu_get_lrmw (addr, sz_byte, 0);
+}
+STATIC_INLINE uae_u32 get_lrmw_word_mmu040 (uaecptr addr)
+{
+    return uae_mmu_get_lrmw (addr, sz_word, 0);
+}
+STATIC_INLINE uae_u32 get_lrmw_long_mmu040 (uaecptr addr)
+{
+    return uae_mmu_get_lrmw (addr, sz_long, 0);
+}
+
+STATIC_INLINE uae_u32 get_ibyte_mmu040 (int o)
+{
+    uae_u32 pc = m68k_getpci () + o;
+    return uae_mmu040_get_iword (pc);
+}
+STATIC_INLINE uae_u32 get_iword_mmu040 (int o)
+{
+    uae_u32 pc = m68k_getpci () + o;
+    return uae_mmu040_get_iword (pc);
+}
+STATIC_INLINE uae_u32 get_ilong_mmu040 (int o)
+{
+    uae_u32 pc = m68k_getpci () + o;
+    return uae_mmu040_get_ilong (pc);
+}
+STATIC_INLINE uae_u32 next_iword_mmu040 (void)
+{
+    uae_u32 pc = m68k_getpci ();
+    m68k_incpci (2);
+    return uae_mmu040_get_iword (pc);
+}
+STATIC_INLINE uae_u32 next_ilong_mmu040 (void)
+{
+    uae_u32 pc = m68k_getpci ();
+    m68k_incpci (4);
+    return uae_mmu040_get_ilong (pc);
+}
+
+STATIC_INLINE uae_u32 get_ibyte_mmu060 (int o)
+{
+    uae_u32 pc = m68k_getpci () + o;
+    return uae_mmu060_get_iword (pc);
+}
+STATIC_INLINE uae_u32 get_iword_mmu060 (int o)
+{
+    uae_u32 pc = m68k_getpci () + o;
+    return uae_mmu060_get_iword (pc);
+}
+STATIC_INLINE uae_u32 get_ilong_mmu060 (int o)
+{
+    uae_u32 pc = m68k_getpci () + o;
+    return uae_mmu060_get_ilong (pc);
+}
+STATIC_INLINE uae_u32 next_iword_mmu060 (void)
+{
+    uae_u32 pc = m68k_getpci ();
+    m68k_incpci (2);
+    return uae_mmu060_get_iword (pc);
+}
+STATIC_INLINE uae_u32 next_ilong_mmu060 (void)
+{
+    uae_u32 pc = m68k_getpci ();
+    m68k_incpci (4);
+    return uae_mmu060_get_ilong (pc);
+}
+
+extern void flush_mmu040 (uaecptr, int);
+extern void m68k_do_rts_mmu040 (void);
+extern void m68k_do_rte_mmu040 (uaecptr a7);
+extern void m68k_do_bsr_mmu040 (uaecptr oldpc, uae_s32 offset);
+
+extern void flush_mmu060 (uaecptr, int);
+extern void m68k_do_rts_mmu060 (void);
+extern void m68k_do_rte_mmu060 (uaecptr a7);
+extern void m68k_do_bsr_mmu060 (uaecptr oldpc, uae_s32 offset);
+
+#endif /* CPUMMU_H */
diff --git a/src/cpu/cpummu030.c b/src/cpu/cpummu030.c
new file mode 100644
index 0000000..6f59c48
--- /dev/null
+++ b/src/cpu/cpummu030.c
@@ -0,0 +1,2520 @@
+/* Emulation of MC68030 MMU
+ * This code has been written for Previous - a NeXT Computer emulator
+ *
+ * This file is distributed under the GNU General Public License, version 2
+ * or at your option any later version. Read the file gpl.txt for details.
+ *
+ *
+ * Written by Andreas Grabher
+ *
+ * Many thanks go to Thomas Huth and the Hatari community for helping
+ * to test and debug this code!
+ *
+ *
+ * Release notes:
+ * 01-09-2012: First release
+ * 29-09-2012: Improved function code handling
+ * 16-11-2012: Improved exception handling
+ *
+ *
+ * - Check if read-modify-write operations are correctly detected for
+ *   handling transparent access (see TT matching functions)
+ * - If possible, test mmu030_table_search with all kinds of translations
+ *   (early termination, invalid descriptors, bus errors, indirect
+ *   descriptors, PTEST in different levels, etc).
+ * - Check which bits of an ATC entry or the status register should be set 
+ *   and which should be un-set, if an invalid translation occurs.
+ * - Handle cache inhibit bit when accessing ATC entries
+ */
+
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+
+#include "main.h"
+#include "hatari-glue.h"
+
+
+#include "options_cpu.h"
+#include "memory.h"
+#include "newcpu.h"
+#include "cpummu030.h"
+
+#define MMU030_OP_DBG_MSG 0
+#define MMU030_ATC_DBG_MSG 0
+#define MMU030_REG_DBG_MSG 0
+
+#define TT_FC_MASK      0x00000007
+#define TT_FC_BASE      0x00000070
+#define TT_RWM          0x00000100
+#define TT_RW           0x00000200
+#define TT_CI           0x00000400
+#define TT_ENABLE       0x00008000
+
+#define TT_ADDR_MASK    0x00FF0000
+#define TT_ADDR_BASE    0xFF000000
+
+static int bBusErrorReadWrite;
+static int atcindextable[32];
+static int tt_enabled;
+
+int mmu030_idx;
+
+uae_u32 mm030_stageb_address;
+bool mmu030_retry;
+int mmu030_opcode;
+int mmu030_opcode_stageb;
+
+int mmu030_fake_prefetch;
+uaecptr mmu030_fake_prefetch_addr;
+
+uae_u16 mmu030_state[3];
+uae_u32 mmu030_data_buffer;
+uae_u32 mmu030_disp_store[2];
+uae_u32 mmu030_fmovem_store[2];
+struct mmu030_access mmu030_ad[MAX_MMU030_ACCESS];
+
+/* for debugging messages */
+char table_letter[4] = {'A','B','C','D'};
+
+uae_u64 srp_030, crp_030;
+uae_u32 tt0_030, tt1_030, tc_030;
+uae_u16 mmusr_030;
+
+/* ATC struct */
+#define ATC030_NUM_ENTRIES  22
+
+typedef struct {
+    struct {
+        uaecptr addr;
+        bool modified;
+        bool write_protect;
+        bool cache_inhibit;
+        bool bus_error;
+    } physical;
+    
+    struct {
+        uaecptr addr;
+        uae_u32 fc;
+        bool valid;
+    } logical;
+    /* history bit */
+    int mru;
+} MMU030_ATC_LINE;
+
+
+/* MMU struct for 68030 */
+static struct {
+    
+    /* Translation tables */
+    struct {
+        struct {
+            uae_u32 mask;
+            uae_u8 shift;
+        } table[4];
+        
+        struct {
+            uae_u32 mask;
+			uae_u32 imask;
+            uae_u8 size;
+        } page;
+        
+        uae_u8 init_shift;
+        uae_u8 last_table;
+    } translation;
+    
+    /* Transparent translation */
+    struct {
+        TT_info tt0;
+        TT_info tt1;
+    } transparent;
+    
+    /* Address translation cache */
+    MMU030_ATC_LINE atc[ATC030_NUM_ENTRIES];
+    
+    /* Condition */
+    bool enabled;
+    uae_u16 status;
+} mmu030;
+
+
+
+/* MMU Status Register
+ *
+ * ---x ---x x-xx x---
+ * reserved (all 0)
+ *
+ * x--- ---- ---- ----
+ * bus error
+ *
+ * -x-- ---- ---- ----
+ * limit violation
+ *
+ * --x- ---- ---- ----
+ * supervisor only
+ *
+ * ---- x--- ---- ----
+ * write protected
+ *
+ * ---- -x-- ---- ----
+ * invalid
+ *
+ * ---- --x- ---- ----
+ * modified
+ *
+ * ---- ---- -x-- ----
+ * transparent access
+ *
+ * ---- ---- ---- -xxx
+ * number of levels (number of tables accessed during search)
+ *
+ */
+
+#define MMUSR_BUS_ERROR         0x8000
+#define MMUSR_LIMIT_VIOLATION   0x4000
+#define MMUSR_SUPER_VIOLATION   0x2000
+#define MMUSR_WRITE_PROTECTED   0x0800
+#define MMUSR_INVALID           0x0400
+#define MMUSR_MODIFIED          0x0200
+#define MMUSR_TRANSP_ACCESS     0x0040
+#define MMUSR_NUM_LEVELS_MASK   0x0007
+
+
+
+/* -- MMU instructions -- */
+
+bool mmu_op30_pmove (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
+{
+	int preg = (next >> 10) & 31;
+	int rw = (next >> 9) & 1;
+	int fd = (next >> 8) & 1;
+    
+#if MMU030_OP_DBG_MSG
+    switch (preg) {
+        case 0x10:
+            write_log(_T("PMOVE: %s TC %08X\n"), rw?"read":"write",
+                      rw?tc_030:x_get_long(extra));
+            break;
+        case 0x12:
+            write_log(_T("PMOVE: %s SRP %08X%08X\n"), rw?"read":"write",
+                      rw?(uae_u32)(srp_030>>32)&0xFFFFFFFF:x_get_long(extra),
+                      rw?(uae_u32)srp_030&0xFFFFFFFF:x_get_long(extra+4));
+            break;
+        case 0x13:
+            write_log(_T("PMOVE: %s CRP %08X%08X\n"), rw?"read":"write",
+                      rw?(uae_u32)(crp_030>>32)&0xFFFFFFFF:x_get_long(extra),
+                      rw?(uae_u32)crp_030&0xFFFFFFFF:x_get_long(extra+4));
+            break;
+        case 0x18:
+            write_log(_T("PMOVE: %s MMUSR %04X\n"), rw?"read":"write",
+                      rw?mmusr_030:x_get_word(extra));
+            break;
+        case 0x02:
+            write_log(_T("PMOVE: %s TT0 %08X\n"), rw?"read":"write",
+                      rw?tt0_030:x_get_long(extra));
+            break;
+        case 0x03:
+            write_log(_T("PMOVE: %s TT1 %08X\n"), rw?"read":"write",
+                      rw?tt1_030:x_get_long(extra));
+            break;
+        default:
+            break;
+    }
+    if (!fd && !rw && !(preg==0x18)) {
+        write_log(_T("PMOVE: flush ATC\n"));
+    }
+#endif
+    
+	switch (preg)
+	{
+        case 0x10: // TC
+            if (rw)
+                x_put_long (extra, tc_030);
+            else {
+                tc_030 = x_get_long (extra);
+                if (mmu030_decode_tc(tc_030))
+					return true;
+            }
+            break;
+        case 0x12: // SRP
+            if (rw) {
+                x_put_long (extra, srp_030 >> 32);
+                x_put_long (extra + 4, srp_030);
+            } else {
+                srp_030 = (uae_u64)x_get_long (extra) << 32;
+                srp_030 |= x_get_long (extra + 4);
+                if (mmu030_decode_rp(srp_030))
+					return true;
+            }
+            break;
+        case 0x13: // CRP
+            if (rw) {
+                x_put_long (extra, crp_030 >> 32);
+                x_put_long (extra + 4, crp_030);
+            } else {
+                crp_030 = (uae_u64)x_get_long (extra) << 32;
+                crp_030 |= x_get_long (extra + 4);
+                if (mmu030_decode_rp(crp_030))
+					return true;
+            }
+            break;
+        case 0x18: // MMUSR
+            if (rw)
+                x_put_word (extra, mmusr_030);
+            else
+                mmusr_030 = x_get_word (extra);
+            break;
+        case 0x02: // TT0
+            if (rw)
+                x_put_long (extra, tt0_030);
+            else {
+                tt0_030 = x_get_long (extra);
+                mmu030.transparent.tt0 = mmu030_decode_tt(tt0_030);
+            }
+            break;
+        case 0x03: // TT1
+            if (rw)
+                x_put_long (extra, tt1_030);
+            else {
+                tt1_030 = x_get_long (extra);
+                mmu030.transparent.tt1 = mmu030_decode_tt(tt1_030);
+            }
+            break;
+        default:
+            write_log (_T("Bad PMOVE at %08x\n"),m68k_getpc());
+            op_illg (opcode);
+            return true;
+	}
+    
+    if (!fd && !rw && !(preg==0x18)) {
+        mmu030_flush_atc_all();
+    }
+	tt_enabled = (tt0_030 & TT_ENABLE) || (tt1_030 & TT_ENABLE);
+	return false;
+}
+
+bool mmu_op30_ptest (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
+{
+    mmu030.status = mmusr_030 = 0;
+    
+    int level = (next&0x1C00)>>10;
+    int rw = (next >> 9) & 1;
+    int a = (next >> 8) & 1;
+    int areg = (next&0xE0)>>5;
+    uae_u32 fc = mmu_op30_helper_get_fc(next);
+        
+    bool write = rw ? false : true;
+
+    uae_u32 ret = 0;
+    
+    /* Check this - datasheet says:
+     * "When the instruction specifies an address translation cache search
+     *  with an address register operand, the MC68030 takes an F-line
+     *  unimplemented instruction exception."
+     */
+    if (!level && a) { /* correct ? */
+        write_log(_T("PTEST: Bad instruction causing F-line unimplemented instruction exception!\n"));
+        Exception(11); /* F-line unimplemented instruction exception */
+        return true;
+    }
+        
+#if MMU030_OP_DBG_MSG
+    write_log(_T("PTEST%c: addr = %08X, fc = %i, level = %i, "),
+              rw?'R':'W', extra, fc, level);
+    if (a) {
+        write_log(_T("return descriptor to register A%i\n"), areg);
+    } else {
+        write_log(_T("do not return descriptor\n"));
+    }
+#endif
+    
+    if (!level) {
+        mmu030_ptest_atc_search(extra, fc, write);
+    } else {
+        ret = mmu030_ptest_table_search(extra, fc, write, level);
+        if (a) {
+            m68k_areg (regs, areg) = ret;
+        }
+    }
+    mmusr_030 = mmu030.status;
+    
+#if MMU030_OP_DBG_MSG
+    write_log(_T("PTEST status: %04X, B = %i, L = %i, S = %i, W = %i, I = %i, M = %i, T = %i, N = %i\n"),
+              mmusr_030, (mmusr_030&MMUSR_BUS_ERROR)?1:0, (mmusr_030&MMUSR_LIMIT_VIOLATION)?1:0,
+              (mmusr_030&MMUSR_SUPER_VIOLATION)?1:0, (mmusr_030&MMUSR_WRITE_PROTECTED)?1:0,
+              (mmusr_030&MMUSR_INVALID)?1:0, (mmusr_030&MMUSR_MODIFIED)?1:0,
+              (mmusr_030&MMUSR_TRANSP_ACCESS)?1:0, mmusr_030&MMUSR_NUM_LEVELS_MASK);
+#endif
+	return false;
+}
+
+bool mmu_op30_pload (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
+{
+    int rw = (next >> 9) & 1;
+    uae_u32 fc = mmu_op30_helper_get_fc(next);
+    
+    bool write = rw ? false : true;
+
+#if 0
+    write_log (_T("PLOAD%c: Create ATC entry for %08X, FC = %i\n"), write?'W':'R', extra, fc);
+#endif
+
+    mmu030_flush_atc_page(extra);
+    mmu030_table_search(extra, fc, write, 0);
+	return false;
+}
+
+bool mmu_op30_pflush (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
+{
+    uae_u16 mode = (next&0x1C00)>>10;
+    uae_u32 fc_mask = (uae_u32)(next&0x00E0)>>5;
+    uae_u32 fc_base = mmu_op30_helper_get_fc(next);
+    
+#if 0
+    switch (mode) {
+        case 0x1:
+            write_log(_T("PFLUSH: Flush all entries\n"));
+            break;
+        case 0x4:
+            write_log(_T("PFLUSH: Flush by function code only\n"));
+            write_log(_T("PFLUSH: function code: base = %08X, mask = %08X\n"), fc_base, fc_mask);
+            break;
+        case 0x6:
+            write_log(_T("PFLUSH: Flush by function code and effective address\n"));
+            write_log(_T("PFLUSH: function code: base = %08X, mask = %08X\n"), fc_base, fc_mask);
+            write_log(_T("PFLUSH: effective address = %08X\n"), extra);
+            break;
+        default:
+            break;
+    }
+#endif
+    
+    switch (mode) {
+        case 0x1:
+            mmu030_flush_atc_all();
+            break;
+        case 0x4:
+            mmu030_flush_atc_fc(fc_base, fc_mask);
+            break;
+        case 0x6:
+            mmu030_flush_atc_page_fc(extra, fc_base, fc_mask);
+            break;
+            
+        default:
+            write_log(_T("PFLUSH ERROR: bad mode! (%i)\n"),mode);
+            break;
+    }
+	return false;
+}
+
+/* -- Helper function for MMU instructions -- */
+uae_u32 mmu_op30_helper_get_fc(uae_u16 next) {
+    switch (next&0x0018) {
+        case 0x0010:
+            return (next&0x7);
+        case 0x0008:
+            return (m68k_dreg(regs, next&0x7)&0x7);
+        case 0x0000:
+            if (next&1) {
+                return (regs.dfc);
+            } else {
+                return (regs.sfc);
+            }
+        default:
+            write_log(_T("MMU_OP30 ERROR: bad fc source! (%04X)\n"),next&0x0018);
+            return 0;
+    }
+}
+
+
+/* -- ATC flushing functions -- */
+
+/* This function flushes ATC entries depending on their function code */
+void mmu030_flush_atc_fc(uae_u32 fc_base, uae_u32 fc_mask) {
+    int i;
+    for (i=0; i>4;
+    ret.addr_base = TT & TT_ADDR_BASE;
+    ret.addr_mask = ~(((TT&TT_ADDR_MASK)<<8)|0x00FFFFFF);
+    
+#if 0
+    if ((TT&TT_ENABLE) && !(TT&TT_RWM)) {
+        write_log(_T("MMU Warning: Transparent translation of read-modify-write cycle is not correctly handled!\n"));
+    }
+#endif
+
+#if MMU030_REG_DBG_MSG /* enable or disable debugging messages */
+    write_log(_T("\n"));
+    write_log(_T("TRANSPARENT TRANSLATION: %08X\n"), TT);
+    write_log(_T("\n"));
+    
+    write_log(_T("TT: transparent translation "));
+    if (TT&TT_ENABLE) {
+        write_log(_T("enabled\n"));
+    } else {
+        write_log(_T("disabled\n"));
+        return ret;
+    }
+
+    write_log(_T("TT: caching %s\n"), (TT&TT_CI) ? _T("inhibited") : _T("enabled"));
+    write_log(_T("TT: read-modify-write "));
+    if (TT&TT_RWM) {
+        write_log(_T("enabled\n"));
+    } else {
+        write_log(_T("disabled (%s only)\n"), (TT&TT_RW) ? _T("read") : _T("write"));
+    }
+    write_log(_T("\n"));
+    write_log(_T("TT: function code base: %08X\n"), ret.fc_base);
+    write_log(_T("TT: function code mask: %08X\n"), ret.fc_mask);
+    write_log(_T("\n"));
+    write_log(_T("TT: address base: %08X\n"), ret.addr_base);
+    write_log(_T("TT: address mask: %08X\n"), ret.addr_mask);
+    write_log(_T("\n"));
+#endif
+    
+    return ret;
+}
+
+/* This function compares the address with both transparent
+ * translation registers and returns the result */
+int mmu030_match_ttr(uaecptr addr, uae_u32 fc, bool write)
+{
+    int tt0, tt1;
+
+    bool cache_inhibit = false; /* TODO: pass to memory access function */
+    
+    tt0 = mmu030_do_match_ttr(tt0_030, mmu030.transparent.tt0, addr, fc, write);
+    if (tt0&TT_OK_MATCH) {
+        cache_inhibit = (tt0_030&TT_CI) ? true : false;
+    }
+    tt1 = mmu030_do_match_ttr(tt1_030, mmu030.transparent.tt1, addr, fc, write);
+    if (tt1&TT_OK_MATCH) {
+        if (!cache_inhibit) {
+            cache_inhibit = (tt1_030&TT_CI) ? true : false;
+        }
+    }
+    
+    return (tt0|tt1);
+}
+int mmu030_match_ttr_access(uaecptr addr, uae_u32 fc, bool write)
+{
+    int tt0, tt1;
+	if (!tt_enabled)
+		return 0;
+    tt0 = mmu030_do_match_ttr(tt0_030, mmu030.transparent.tt0, addr, fc, write);
+    tt1 = mmu030_do_match_ttr(tt1_030, mmu030.transparent.tt1, addr, fc, write);
+    return (tt0|tt1) & TT_OK_MATCH;
+}
+
+/* Locked Read-Modify-Write */
+int mmu030_match_lrmw_ttr_access(uaecptr addr, uae_u32 fc)
+{
+    int tt0, tt1;
+
+ 	if (!tt_enabled)
+		return 0;
+    tt0 = mmu030_do_match_lrmw_ttr(tt0_030, mmu030.transparent.tt0, addr, fc);
+    tt1 = mmu030_do_match_lrmw_ttr(tt1_030, mmu030.transparent.tt1, addr, fc);
+    return (tt0|tt1) & TT_OK_MATCH;
+}
+
+/* This function checks if an address matches a transparent
+ * translation register */
+
+/* FIXME:
+ * If !(tt&TT_RMW) neither the read nor the write portion
+ * of a read-modify-write cycle is transparently translated! */
+
+int mmu030_do_match_ttr(uae_u32 tt, TT_info comp, uaecptr addr, uae_u32 fc, bool write)
+{
+	if (tt & TT_ENABLE)	{	/* transparent translation enabled */
+        
+        /* Compare actual function code with function code base using mask */
+        if ((comp.fc_base&comp.fc_mask)==(fc&comp.fc_mask)) {
+            
+            /* Compare actual address with address base using mask */
+            if ((comp.addr_base&comp.addr_mask)==(addr&comp.addr_mask)) {
+                
+                if (tt&TT_RWM) {  /* r/w field disabled */
+                    return TT_OK_MATCH;
+                } else {
+                    if (tt&TT_RW) { /* read access transparent */
+                        return write ? TT_NO_WRITE : TT_OK_MATCH;
+                    } else {        /* write access transparent */
+                        return write ? TT_OK_MATCH : TT_NO_READ; /* TODO: check this! */
+                    }
+                }
+            }
+		}
+	}
+	return TT_NO_MATCH;
+}
+
+int mmu030_do_match_lrmw_ttr(uae_u32 tt, TT_info comp, uaecptr addr, uae_u32 fc)
+{
+	if ((tt & TT_ENABLE) && (tt & TT_RWM))	{	/* transparent translation enabled */
+        
+        /* Compare actual function code with function code base using mask */
+        if ((comp.fc_base&comp.fc_mask)==(fc&comp.fc_mask)) {
+            
+            /* Compare actual address with address base using mask */
+            if ((comp.addr_base&comp.addr_mask)==(addr&comp.addr_mask)) {
+                
+				return TT_OK_MATCH;
+            }
+		}
+	}
+	return TT_NO_MATCH;
+}
+
+
+
+/* Translation Control Register:
+ *
+ * x--- ---- ---- ---- ---- ---- ---- ----
+ * translation: 1 = enable, 0 = disable
+ *
+ * ---- --x- ---- ---- ---- ---- ---- ----
+ * supervisor root: 1 = enable, 0 = disable
+ *
+ * ---- ---x ---- ---- ---- ---- ---- ----
+ * function code lookup: 1 = enable, 0 = disable
+ *
+ * ---- ---- xxxx ---- ---- ---- ---- ----
+ * page size:
+ * 1000 = 256 bytes
+ * 1001 = 512 bytes
+ * 1010 =  1 kB
+ * 1011 =  2 kB
+ * 1100 =  4 kB
+ * 1101 =  8 kB
+ * 1110 = 16 kB
+ * 1111 = 32 kB
+ *
+ * ---- ---- ---- xxxx ---- ---- ---- ----
+ * initial shift
+ *
+ * ---- ---- ---- ---- xxxx ---- ---- ----
+ * number of bits for table index A
+ *
+ * ---- ---- ---- ---- ---- xxxx ---- ----
+ * number of bits for table index B
+ *
+ * ---- ---- ---- ---- ---- ---- xxxx ----
+ * number of bits for table index C
+ *
+ * ---- ---- ---- ---- ---- ----- ---- xxxx
+ * number of bits for table index D
+ *
+ */
+
+
+#define TC_ENABLE_TRANSLATION   0x80000000
+#define TC_ENABLE_SUPERVISOR    0x02000000
+#define TC_ENABLE_FCL           0x01000000
+
+#define TC_PS_MASK              0x00F00000
+#define TC_IS_MASK              0x000F0000
+
+#define TC_TIA_MASK             0x0000F000
+#define TC_TIB_MASK             0x00000F00
+#define TC_TIC_MASK             0x000000F0
+#define TC_TID_MASK             0x0000000F
+
+static void mmu030_do_fake_prefetch(void)
+{
+	// fetch next opcode before MMU state switches.
+	// There are programs that do following:
+	// - enable MMU
+	// - JMP (An)
+	// "enable MMU" unmaps memory under us.
+	TRY (prb) {
+		uaecptr pc = m68k_getpci();
+		mmu030_fake_prefetch = -1;
+		mmu030_fake_prefetch_addr = mmu030_translate(pc, regs.s != 0, false, false);
+		mmu030_fake_prefetch = x_prefetch(0);
+		// A26x0 ROM code switches off rom
+		// NOP
+		// JMP (a0)
+		if (mmu030_fake_prefetch == 0x4e71)
+			mmu030_fake_prefetch = x_prefetch(2);
+	} CATCH (prb) {
+		// didn't work, oh well..
+		mmu030_fake_prefetch = -1;
+	} ENDTRY
+}
+
+bool mmu030_decode_tc(uae_u32 TC)
+{
+    /* Set MMU condition */    
+    if (TC & TC_ENABLE_TRANSLATION) {
+		if (!mmu030.enabled)
+			mmu030_do_fake_prefetch();
+        mmu030.enabled = true;
+    } else {
+		if (mmu030.enabled) {
+			mmu030_do_fake_prefetch();
+			write_log(_T("MMU disabled PC=%08x\n"), M68K_GETPC);
+		}
+        mmu030.enabled = false;
+        return false;
+    }
+    
+    /* Note: 0 = Table A, 1 = Table B, 2 = Table C, 3 = Table D */
+    int i, j;
+    uae_u8 TI_bits[4] = {0,0,0,0};
+
+    /* Reset variables before extracting new values from TC */
+    for (i = 0; i < 4; i++) {
+        mmu030.translation.table[i].mask = 0;
+        mmu030.translation.table[i].shift = 0;
+    }
+    
+    
+    /* Extract initial shift and page size values from TC register */
+    mmu030.translation.page.size = (TC & TC_PS_MASK) >> 20;
+    mmu030.translation.init_shift = (TC & TC_IS_MASK) >> 16;
+	regs.mmu_page_size = 1 << mmu030.translation.page.size;
+
+    
+	write_log(_T("68030 MMU enabled. Page size = %d PC=%08x\n"), regs.mmu_page_size, M68K_GETPC);
+
+	if (mmu030.translation.page.size<8) {
+        write_log(_T("MMU Configuration Exception: Bad value in TC register! (bad page size: %i byte)\n"),
+                  1<>shift */
+    
+    /* Get number of bits for each table index */
+    for (i = 0; i < 4; i++) {
+        j = (3-i)*4;
+        TI_bits[i] = (TC >> j) & 0xF;
+    }
+
+    /* Calculate masks and shifts for each table */
+    mmu030.translation.last_table = 0;
+    uae_u8 shift = 32 - mmu030.translation.init_shift;
+    for (i = 0; (i < 4) && TI_bits[i]; i++) {
+        /* Get the shift */
+        shift -= TI_bits[i];
+        mmu030.translation.table[i].shift = shift;
+        /* Build the mask */
+        for (j = 0; j < TI_bits[i]; j++) {
+            mmu030.translation.table[i].mask |= (1<<(mmu030.translation.table[i].shift + j));
+        }
+        /* Update until reaching the last table */
+        mmu030.translation.last_table = i;
+    }
+    
+#if MMU030_REG_DBG_MSG
+    /* At least one table has to be defined using at least
+     * 1 bit for the index. At least 2 bits are necessary 
+     * if there is no second table. If these conditions are
+     * not met, it will automatically lead to a sum <32
+     * and cause an exception (see below). */
+    if (!TI_bits[0]) {
+        write_log(_T("MMU Configuration Exception: Bad value in TC register! (no first table index defined)\n"));
+    } else if ((TI_bits[0]<2) && !TI_bits[1]) {
+        write_log(_T("MMU Configuration Exception: Bad value in TC register! (no second table index defined and)\n"));
+        write_log(_T("MMU Configuration Exception: Bad value in TC register! (only 1 bit for first table index)\n"));
+    }
+#endif
+    
+    /* TI fields are summed up until a zero field is reached (see above
+     * loop). The sum of all TI field values plus page size and initial
+     * shift has to be 32: IS + PS + TIA + TIB + TIC + TID = 32 */
+    if ((shift-mmu030.translation.page.size)!=0) {
+        write_log(_T("MMU Configuration Exception: Bad value in TC register! (bad sum)\n"));
+        Exception(56); /* MMU Configuration Exception */
+        return true;
+    }
+    
+#if MMU030_REG_DBG_MSG /* enable or disable debugging output */
+    write_log(_T("\n"));
+    write_log(_T("TRANSLATION CONTROL: %08X\n"), TC);
+    write_log(_T("\n"));
+    write_log(_T("TC: translation %s\n"), (TC&TC_ENABLE_TRANSLATION ? _T("enabled") : _T("disabled")));
+    write_log(_T("TC: supervisor root pointer %s\n"), (TC&TC_ENABLE_SUPERVISOR ? _T("enabled") : _T("disabled")));
+    write_log(_T("TC: function code lookup %s\n"), (TC&TC_ENABLE_FCL ? _T("enabled") : _T("disabled")));
+    write_log(_T("\n"));
+    
+    write_log(_T("TC: Initial Shift: %i\n"), mmu030.translation.init_shift);
+    write_log(_T("TC: Page Size: %i byte\n"), (1<> 32;
+    if (!descriptor_type) { /* If descriptor type is invalid */
+        write_log(_T("MMU Configuration Exception: Root Pointer is invalid!\n"));
+        Exception(56); /* MMU Configuration Exception */
+		return true;
+    }
+	return false;
+
+#if MMU030_REG_DBG_MSG /* enable or disable debugging output */
+    uae_u32 table_limit = (RP & RP_LIMIT_MASK) >> 48;
+    uae_u32 first_addr = (RP & RP_ADDR_MASK);
+    
+    write_log(_T("\n"));
+    write_log(_T("ROOT POINTER: %08X%08X\n"), (uae_u32)(RP>>32)&0xFFFFFFFF, (uae_u32)(RP&0xFFFFFFFF));
+    write_log(_T("\n"));
+    
+    write_log(_T("RP: descriptor type = %i "), descriptor_type);
+    switch (descriptor_type) {
+        case 0:
+            write_log(_T("(invalid descriptor)\n"));
+            break;
+        case 1:
+            write_log(_T("(early termination page descriptor)\n"));
+            break;
+        case 2:
+            write_log(_T("(valid 4 byte descriptor)\n"));
+            break;
+        case 3:
+            write_log(_T("(valid 8 byte descriptor)\n"));
+            break;
+    }
+    
+    write_log(_T("RP: %s limit = %i\n"), (RP&RP_LOWER_MASK) ? _T("lower") : _T("upper"), table_limit);
+    
+    write_log(_T("RP: first table address = %08X\n"), first_addr);
+    write_log(_T("\n"));
+#endif
+}
+
+
+
+/* Descriptors */
+
+#define DESCR_TYPE_MASK         0x00000003
+
+#define DESCR_TYPE_INVALID      0 /* all tables */
+
+#define DESCR_TYPE_EARLY_TERM   1 /* all but lowest level table */
+#define DESCR_TYPE_PAGE         1 /* only lowest level table */
+#define DESCR_TYPE_VALID4       2 /* all but lowest level table */
+#define DESCR_TYPE_INDIRECT4    2 /* only lowest level table */
+#define DESCR_TYPE_VALID8       3 /* all but lowest level table */
+#define DESCR_TYPE_INDIRECT8    3 /* only lowest level table */
+
+#define DESCR_TYPE_VALID_MASK       0x2 /* all but lowest level table */
+#define DESCR_TYPE_INDIRECT_MASK    0x2 /* only lowest level table */
+
+
+/* Short format (4 byte):
+ *
+ * ---- ---- ---- ---- ---- ---- ---- --xx
+ * descriptor type:
+ * 0 = invalid
+ * 1 = page descriptor (early termination)
+ * 2 = valid (4 byte)
+ * 3 = valid (8 byte)
+ *
+ *
+ * table descriptor:
+ * ---- ---- ---- ---- ---- ---- ---- -x--
+ * write protect
+ *
+ * ---- ---- ---- ---- ---- ---- ---- x---
+ * update
+ *
+ * xxxx xxxx xxxx xxxx xxxx xxxx xxxx ----
+ * table address
+ *
+ *
+ * (early termination) page descriptor:
+ * ---- ---- ---- ---- ---- ---- ---- -x--
+ * write protect
+ *
+ * ---- ---- ---- ---- ---- ---- ---- x---
+ * update
+ *
+ * ---- ---- ---- ---- ---- ---- ---x ----
+ * modified
+ *
+ * ---- ---- ---- ---- ---- ---- -x-- ----
+ * cache inhibit
+ *
+ * ---- ---- ---- ---- ---- ---- x-x- ----
+ * reserved (must be 0)
+ *
+ * xxxx xxxx xxxx xxxx xxxx xxxx ---- ----
+ * page address
+ *
+ *
+ * indirect descriptor:
+ * xxxx xxxx xxxx xxxx xxxx xxxx xxxx xx--
+ * descriptor address
+ *
+ */
+
+#define DESCR_WP       0x00000004
+#define DESCR_U        0x00000008
+#define DESCR_M        0x00000010 /* only last level table */
+#define DESCR_CI       0x00000040 /* only last level table */
+
+#define DESCR_TD_ADDR_MASK 0xFFFFFFF0
+#define DESCR_PD_ADDR_MASK 0xFFFFFF00
+#define DESCR_ID_ADDR_MASK 0xFFFFFFFC
+
+
+/* Long format (8 byte):
+ *
+ * ---- ---- ---- ---- ---- ---- ---- --xx | ---- ---- ---- ---- ---- ---- ---- ----
+ * descriptor type:
+ * 0 = invalid
+ * 1 = page descriptor (early termination)
+ * 2 = valid (4 byte)
+ * 3 = valid (8 byte)
+ *
+ *
+ * table desctriptor:
+ * ---- ---- ---- ---- ---- ---- ---- -x-- | ---- ---- ---- ---- ---- ---- ---- ----
+ * write protect
+ *
+ * ---- ---- ---- ---- ---- ---- ---- x--- | ---- ---- ---- ---- ---- ---- ---- ----
+ * update
+ *
+ * ---- ---- ---- ---- ---- ---- xxxx ---- | ---- ---- ---- ---- ---- ---- ---- ----
+ * reserved (must be 0)
+ *
+ * ---- ---- ---- ---- ---- ---x ---- ---- | ---- ---- ---- ---- ---- ---- ---- ----
+ * supervisor
+ *
+ * ---- ---- ---- ---- xxxx xxx- ---- ---- | ---- ---- ---- ---- ---- ---- ---- ----
+ * reserved (must be 1111 110)
+ *
+ * -xxx xxxx xxxx xxxx ---- ---- ---- ---- | ---- ---- ---- ---- ---- ---- ---- ----
+ * limit
+ *
+ * x--- ---- ---- ---- ---- ---- ---- ---- | ---- ---- ---- ---- ---- ---- ---- ----
+ * 0 = upper limit, 1 = lower limit
+ *
+ * ---- ---- ---- ---- ---- ---- ---- ---- | xxxx xxxx xxxx xxxx xxxx xxxx xxxx ----
+ * table address
+ *
+ *
+ * (early termination) page descriptor:
+ * ---- ---- ---- ---- ---- ---- ---- -x-- | ---- ---- ---- ---- ---- ---- ---- ----
+ * write protect
+ *
+ * ---- ---- ---- ---- ---- ---- ---- x--- | ---- ---- ---- ---- ---- ---- ---- ----
+ * update
+ *
+ * ---- ---- ---- ---- ---- ---- ---x ---- | ---- ---- ---- ---- ---- ---- ---- ----
+ * modified
+ *
+ * ---- ---- ---- ---- ---- ---- -x-- ---- | ---- ---- ---- ---- ---- ---- ---- ----
+ * cache inhibit
+ *
+ * ---- ---- ---- ---- ---- ---x ---- ---- | ---- ---- ---- ---- ---- ---- ---- ----
+ * supervisor
+ *
+ * ---- ---- ---- ---- ---- ---- x-x- ---- | ---- ---- ---- ---- ---- ---- ---- ----
+ * reserved (must be 0)
+ *
+ * ---- ---- ---- ---- xxxx xxx- ---- ---- | ---- ---- ---- ---- ---- ---- ---- ----
+ * reserved (must be 1111 110)
+ *
+ * -xxx xxxx xxxx xxxx ---- ---- ---- ---- | ---- ---- ---- ---- ---- ---- ---- ----
+ * limit (only used with early termination page descriptor)
+ *
+ * x--- ---- ---- ---- ---- ---- ---- ---- | ---- ---- ---- ---- ---- ---- ---- ----
+ * 0 = upper limit, 1 = lower limit (only used with early termination page descriptor)
+ *
+ * ---- ---- ---- ---- ---- ---- ---- ---- | xxxx xxxx xxxx xxxx xxxx xxxx ---- ----
+ * page address
+ *
+ *
+ * indirect descriptor:
+ * ---- ---- ---- ---- ---- ---- ---- ---- | xxxx xxxx xxxx xxxx xxxx xxxx xxxx xx--
+ * descriptor address
+ *
+ */
+
+/* only for long descriptors */
+#define DESCR_S        0x00000100
+
+#define DESCR_LIMIT_MASK   0x7FFF0000
+#define DESCR_LOWER_MASK   0x80000000
+
+
+
+/* This functions searches through the translation tables. It can be used 
+ * for PTEST (levels 1 to 7). Using level 0 creates an ATC entry. */
+
+uae_u32 mmu030_table_search(uaecptr addr, uae_u32 fc, bool write, int level) {
+        /* During table walk up to 7 different descriptors are used:
+         * root pointer, descriptors fetched from function code lookup table,
+         * tables A, B, C and D and one indirect descriptor */
+        uae_u32 descr[2];
+        uae_u32 descr_type;
+        uaecptr descr_addr[7];
+        uaecptr table_addr = 0;
+        uaecptr page_addr = 0;
+        uaecptr indirect_addr = 0;
+        uae_u32 table_index = 0;
+        uae_u32 limit = 0;
+        uae_u32 unused_fields_mask = 0;
+        bool super = (fc&4) ? true : false;
+        bool super_violation = false;
+        bool write_protected = false;
+        bool cache_inhibit = false;
+        bool descr_modified = false;
+        
+        mmu030.status = 0; /* Reset status */
+        
+        /* Initial values for condition variables.
+         * Note: Root pointer is long descriptor. */
+        int t = 0;
+        int addr_position = 1;
+        int next_size = 0;
+        int descr_size = 8;
+        int descr_num = 0;
+        bool early_termination = false;
+        
+        int i;
+#ifdef WINUAE_FOR_HATARI
+	/* NP TODO : phys_get_long / phys_put_long need supervisor bit to access */
+	/* the translation table at $700. Should it be automatically set by the MMU ? */
+	int old_regs_s;
+
+	old_regs_s = regs.s;
+	regs.s = 1;	/* needed for putlong / getlong */
+#endif
+    
+    TRY(prb) {
+        /* Use super user root pointer if enabled in TC register and access is in
+         * super user mode, else use cpu root pointer. */
+        if ((tc_030&TC_ENABLE_SUPERVISOR) && super) {
+            descr[0] = (srp_030>>32)&0xFFFFFFFF;
+            descr[1] = srp_030&0xFFFFFFFF;
+#if MMU030_REG_DBG_MSG
+            write_log(_T("Supervisor Root Pointer: %08X%08X\n"),descr[0],descr[1]);
+#endif // MMU030_REG_DBG_MSG
+        } else {
+            descr[0] = (crp_030>>32)&0xFFFFFFFF;
+            descr[1] = crp_030&0xFFFFFFFF;
+#if MMU030_REG_DBG_MSG
+            write_log(_T("CPU Root Pointer: %08X%08X\n"),descr[0],descr[1]);
+#endif
+		}
+                
+        if (descr[0]&RP_ZERO_BITS) {
+#if MMU030_REG_DBG_MSG
+			write_log(_T("MMU Warning: Root pointer reserved bits are non-zero! %08X\n"), descr[0]);
+#endif
+			descr[0] &= (~RP_ZERO_BITS);
+        }
+        
+        /* Check descriptor type of root pointer */
+        descr_type = descr[0]&DESCR_TYPE_MASK;
+        switch (descr_type) {
+            case DESCR_TYPE_INVALID:
+                write_log(_T("Fatal error: Root pointer is invalid descriptor!\n"));
+                mmu030.status |= MMUSR_INVALID;
+                goto stop_search;
+            case DESCR_TYPE_EARLY_TERM:
+                write_log(_T("Root pointer is early termination page descriptor.\n"));
+                early_termination = true;
+                goto handle_page_descriptor;
+            case DESCR_TYPE_VALID4:
+                next_size = 4;
+                break;
+            case DESCR_TYPE_VALID8:
+                next_size = 8;
+                break;
+        }
+        
+        /* If function code lookup is enabled in TC register use function code as
+         * index for top level table, limit check not required */
+        
+        if (tc_030&TC_ENABLE_FCL) {
+            write_log(_T("Function code lookup enabled, FC = %i\n"), fc);
+            
+            addr_position = (descr_size==4) ? 0 : 1;
+            table_addr = descr[addr_position]&DESCR_TD_ADDR_MASK;
+            table_index = fc; /* table index is function code */
+            write_log(_T("Table FCL at %08X: index = %i, "),table_addr,table_index);
+            
+            /* Fetch next descriptor */
+            descr_num++;
+            descr_addr[descr_num] = table_addr+(table_index*next_size);
+            
+            if (next_size==4) {
+                descr[0] = phys_get_long(descr_addr[descr_num]);
+#if MMU030_REG_DBG_MSG
+                write_log(_T("Next descriptor: %08X\n"),descr[0]);
+#endif
+            } else {
+                descr[0] = phys_get_long(descr_addr[descr_num]);
+                descr[1] = phys_get_long(descr_addr[descr_num]+4);
+#if MMU030_REG_DBG_MSG
+                write_log(_T("Next descriptor: %08X%08X\n"),descr[0],descr[1]);
+#endif
+            }
+            
+            descr_size = next_size;
+            
+            /* Check descriptor type */
+            descr_type = descr[0]&DESCR_TYPE_MASK;
+            switch (descr_type) {
+                case DESCR_TYPE_INVALID:
+                    write_log(_T("Invalid descriptor!\n"));
+                    /* stop table walk */
+                    mmu030.status |= MMUSR_INVALID;
+                    goto stop_search;
+                case DESCR_TYPE_EARLY_TERM:
+#if MMU030_REG_DBG_MSG
+                    write_log(_T("Early termination page descriptor!\n"));
+#endif
+					early_termination = true;
+                    goto handle_page_descriptor;
+                case DESCR_TYPE_VALID4:
+                    next_size = 4;
+                    break;
+                case DESCR_TYPE_VALID8:
+                    next_size = 8;
+                    break;
+            }
+        }
+        
+        
+        /* Upper level tables */
+        do {
+            if (descr_num) { /* if not root pointer */
+                /* Check protection */
+                if ((descr_size==8) && (descr[0]&DESCR_S) && !super) {
+                    super_violation = true;
+                }
+                if (descr[0]&DESCR_WP) {
+                    write_protected = true;
+                }
+                
+                /* Set the updated bit */
+                if (!level && !(descr[0]&DESCR_U) && !super_violation) {
+                    descr[0] |= DESCR_U;
+                    phys_put_long(descr_addr[descr_num], descr[0]);
+                }
+                
+                /* Update status bits */
+                mmu030.status |= super_violation ? MMUSR_SUPER_VIOLATION : 0;
+                mmu030.status |= write_protected ? MMUSR_WRITE_PROTECTED : 0;                
+
+                /* Check if ptest level is reached */
+                if (level && (level==descr_num)) {
+                    goto stop_search;
+                }
+            }
+            
+            addr_position = (descr_size==4) ? 0 : 1;
+            table_addr = descr[addr_position]&DESCR_TD_ADDR_MASK;
+            table_index = (addr&mmu030.translation.table[t].mask)>>mmu030.translation.table[t].shift;
+#if MMU030_REG_DBG_MSG
+            write_log(_T("Table %c at %08X: index = %i, "),table_letter[t],table_addr,table_index);
+#endif // MMU030_REG_DBG_MSG
+            t++; /* Proceed to the next table */
+            
+            /* Perform limit check */
+            if (descr_size==8) {
+                limit = (descr[0]&DESCR_LIMIT_MASK)>>16;
+                if ((descr[0]&DESCR_LOWER_MASK) && (table_indexlimit)) {
+                    mmu030.status |= (MMUSR_LIMIT_VIOLATION|MMUSR_INVALID);
+#if MMU030_REG_DBG_MSG
+                    write_log(_T("limit violation (upper limit %i)\n"),limit);
+#endif
+                    goto stop_search;
+                }
+            }
+            
+            /* Fetch next descriptor */
+            descr_num++;
+            descr_addr[descr_num] = table_addr+(table_index*next_size);
+            
+            if (next_size==4) {
+                descr[0] = phys_get_long(descr_addr[descr_num]);
+#if MMU030_REG_DBG_MSG
+                write_log(_T("Next descriptor: %08X\n"),descr[0]);
+#endif
+            } else {
+                descr[0] = phys_get_long(descr_addr[descr_num]);
+                descr[1] = phys_get_long(descr_addr[descr_num]+4);
+#if MMU030_REG_DBG_MSG
+                write_log(_T("Next descriptor: %08X%08X\n"),descr[0],descr[1]);
+#endif
+            }
+            
+            descr_size = next_size;
+            
+            /* Check descriptor type */
+            descr_type = descr[0]&DESCR_TYPE_MASK;
+            switch (descr_type) {
+                case DESCR_TYPE_INVALID:
+#if MMU030_REG_DBG_MSG
+                    write_log(_T("Invalid descriptor!\n"));
+#endif
+					/* stop table walk */
+                    mmu030.status |= MMUSR_INVALID;
+                    goto stop_search;
+                case DESCR_TYPE_EARLY_TERM:
+                    /* go to last level table handling code */
+                    if (t<=mmu030.translation.last_table) {
+#if MMU030_REG_DBG_MSG
+                        write_log(_T("Early termination page descriptor!\n"));
+#endif
+						early_termination = true;
+                    }
+                    goto handle_page_descriptor;
+                case DESCR_TYPE_VALID4:
+                    next_size = 4;
+                    break;
+                case DESCR_TYPE_VALID8:
+                    next_size = 8;
+                    break;
+            }
+        } while (t<=mmu030.translation.last_table);
+        
+        
+        /* Handle indirect descriptor */
+        
+        /* Check if ptest level is reached */
+        if (level && (level==descr_num)) {
+            goto stop_search;
+        }
+        
+        addr_position = (descr_size==4) ? 0 : 1;
+        indirect_addr = descr[addr_position]&DESCR_ID_ADDR_MASK;
+#if MMU030_REG_DBG_MSG
+        write_log(_T("Page indirect descriptor at %08X: "),indirect_addr);
+#endif
+
+        /* Fetch indirect descriptor */
+        descr_num++;
+        descr_addr[descr_num] = indirect_addr;
+        
+        if (next_size==4) {
+            descr[0] = phys_get_long(descr_addr[descr_num]);
+#if MMU030_REG_DBG_MSG
+            write_log(_T("descr = %08X\n"),descr[0]);
+#endif
+		} else {
+            descr[0] = phys_get_long(descr_addr[descr_num]);
+            descr[1] = phys_get_long(descr_addr[descr_num]+4);
+#if MMU030_REG_DBG_MSG
+            write_log(_T("descr = %08X%08X"),descr[0],descr[1]);
+#endif
+		}
+        
+        descr_size = next_size;
+        
+        /* Check descriptor type, only page descriptor is valid */
+        descr_type = descr[0]&DESCR_TYPE_MASK;
+        if (descr_type!=DESCR_TYPE_PAGE) {
+            mmu030.status |= MMUSR_INVALID;
+            goto stop_search;
+        }
+        
+    handle_page_descriptor:
+        
+        if (descr_num) { /* if not root pointer */
+            /* check protection */
+            if ((descr_size==8) && (descr[0]&DESCR_S) && !super) {
+                super_violation = true;
+            }
+            if (descr[0]&DESCR_WP) {
+                write_protected = true;
+            }
+
+            if (!level && !super_violation) {
+                /* set modified bit */
+                if (!(descr[0]&DESCR_M) && write && !write_protected) {
+                    descr[0] |= DESCR_M;
+                    descr_modified = true;
+                }
+                /* set updated bit */
+                if (!(descr[0]&DESCR_U)) {
+                    descr[0] |= DESCR_U;
+                    descr_modified = true;
+                }
+                /* write modified descriptor if neccessary */
+                if (descr_modified) {
+                    phys_put_long(descr_addr[descr_num], descr[0]);
+                }
+            }
+            
+            /* update status bits */
+            mmu030.status |= super_violation ? MMUSR_SUPER_VIOLATION : 0;
+            mmu030.status |= write_protected ? MMUSR_WRITE_PROTECTED : 0;
+
+            /* check if caching is inhibited */
+            cache_inhibit = descr[0]&DESCR_CI ? true : false;
+            
+            /* check for the modified bit and set it in the status register */
+            mmu030.status |= (descr[0]&DESCR_M) ? MMUSR_MODIFIED : 0;
+        }
+        
+        /* Check limit using next index field of logical address.
+         * Limit is only checked on early termination. If we are
+         * still at root pointer level, only check limit, if FCL
+         * is disabled. */
+        if (early_termination) {
+            if (descr_num || !(tc_030&TC_ENABLE_FCL)) {
+                if (descr_size==8) {
+                    table_index = (addr&mmu030.translation.table[t].mask)>>mmu030.translation.table[t].shift;
+                    limit = (descr[0]&DESCR_LIMIT_MASK)>>16;
+                    if ((descr[0]&DESCR_LOWER_MASK) && (table_indexlimit)) {
+                        mmu030.status |= (MMUSR_LIMIT_VIOLATION|MMUSR_INVALID);
+#if MMU030_REG_DBG_MSG
+                        write_log(_T("Limit violation (upper limit %i)\n"),limit);
+#endif
+                        goto stop_search;
+                    }
+                }
+            }
+            /* Get all unused bits of the logical address table index field.
+             * they are added to the page address */
+            /* TODO: They should be added via "unsigned addition". How to? */
+            do {
+                unused_fields_mask |= mmu030.translation.table[t].mask;
+                t++;
+            } while (t<=mmu030.translation.last_table);
+            page_addr = addr&unused_fields_mask;
+#if MMU030_REG_DBG_MSG
+            write_log(_T("Logical address unused bits: %08X (mask = %08X)\n"),
+                      page_addr,unused_fields_mask);
+#endif
+		}
+
+        /* Get page address */
+        addr_position = (descr_size==4) ? 0 : 1;
+        page_addr += (descr[addr_position]&DESCR_PD_ADDR_MASK);
+#if MMU030_REG_DBG_MSG
+        write_log(_T("Page at %08X\n"),page_addr);
+#endif // MMU030_REG_DBG_MSG
+        
+    stop_search:
+        ; /* Make compiler happy */
+    } CATCH(prb) {
+        /* We jump to this place, if a bus error occured during table search.
+         * bBusErrorReadWrite is set in m68000.c, M68000_BusError: read = 1 */
+        if (bBusErrorReadWrite) {
+            descr_num--;
+        }
+        mmu030.status |= (MMUSR_BUS_ERROR|MMUSR_INVALID);
+        write_log(_T("MMU: Bus error while %s descriptor!\n"),
+                  bBusErrorReadWrite?_T("reading"):_T("writing"));
+    } ENDTRY
+
+#ifdef WINUAE_FOR_HATARI
+    regs.s = old_regs_s;
+#endif
+
+    /* check if we have to handle ptest */
+    if (level) {
+        /* Note: wp, m and sv bits are undefined if the invalid bit is set */
+        mmu030.status = (mmu030.status&~MMUSR_NUM_LEVELS_MASK) | descr_num;
+
+        /* If root pointer is page descriptor (descr_num 0), return 0 */
+        return descr_num ? descr_addr[descr_num] : 0;
+    }
+    
+    /* Find an ATC entry to replace */
+    /* Search for invalid entry */
+    for (i=0; i= ATC030_NUM_ENTRIES) {
+		i = 0;
+		write_log (_T("ATC entry not found!!!\n"));
+	}
+
+    mmu030_atc_handle_history_bit(i);
+    
+    /* Create ATC entry */
+    mmu030.atc[i].logical.addr = addr & mmu030.translation.page.imask; /* delete page index bits */
+    mmu030.atc[i].logical.fc = fc;
+    mmu030.atc[i].logical.valid = true;
+    mmu030.atc[i].physical.addr = page_addr & mmu030.translation.page.imask; /* delete page index bits */
+    if ((mmu030.status&MMUSR_INVALID) || (mmu030.status&MMUSR_SUPER_VIOLATION)) {
+        mmu030.atc[i].physical.bus_error = true;
+    } else {
+        mmu030.atc[i].physical.bus_error = false;
+    }
+    mmu030.atc[i].physical.cache_inhibit = cache_inhibit;
+    mmu030.atc[i].physical.modified = (mmu030.status&MMUSR_MODIFIED) ? true : false;
+    mmu030.atc[i].physical.write_protect = (mmu030.status&MMUSR_WRITE_PROTECTED) ? true : false;
+
+#if MMU030_ATC_DBG_MSG    
+    write_log(_T("ATC create entry(%i): logical = %08X, physical = %08X, FC = %i\n"), i,
+              mmu030.atc[i].logical.addr, mmu030.atc[i].physical.addr,
+              mmu030.atc[i].logical.fc);
+    write_log(_T("ATC create entry(%i): B = %i, CI = %i, WP = %i, M = %i\n"), i,
+              mmu030.atc[i].physical.bus_error?1:0,
+              mmu030.atc[i].physical.cache_inhibit?1:0,
+              mmu030.atc[i].physical.write_protect?1:0,
+              mmu030.atc[i].physical.modified?1:0);
+#endif // MMU030_ATC_DBG_MSG
+    
+    return 0;
+}
+
+/* This function is used for PTEST level 0. */
+void mmu030_ptest_atc_search(uaecptr logical_addr, uae_u32 fc, bool write) {
+    int i;
+    mmu030.status = 0;
+        
+    if (mmu030_match_ttr(logical_addr, fc, write)&TT_OK_MATCH) {
+        mmu030.status |= MMUSR_TRANSP_ACCESS;
+        return;
+    }
+    
+    for (i = 0; i < ATC030_NUM_ENTRIES; i++) {
+        if ((mmu030.atc[i].logical.fc == fc) &&
+            (mmu030.atc[i].logical.addr == logical_addr) &&
+            mmu030.atc[i].logical.valid) {
+            break;
+        }
+    }
+    
+    if (i==ATC030_NUM_ENTRIES) {
+        mmu030.status |= MMUSR_INVALID;
+        return;
+    }
+    
+    mmu030.status |= mmu030.atc[i].physical.bus_error ? (MMUSR_BUS_ERROR|MMUSR_INVALID) : 0;
+    /* Note: write protect and modified bits are undefined if the invalid bit is set */
+    mmu030.status |= mmu030.atc[i].physical.write_protect ? MMUSR_WRITE_PROTECTED : 0;
+    mmu030.status |= mmu030.atc[i].physical.modified ? MMUSR_MODIFIED : 0;
+}
+
+/* This function is used for PTEST level 1 - 7. */
+uae_u32 mmu030_ptest_table_search(uaecptr logical_addr, uae_u32 fc, bool write, int level) {
+    if (mmu030_match_ttr(logical_addr, fc, write)&TT_OK_MATCH) {
+        return 0;
+    } else {
+        return mmu030_table_search(logical_addr, fc, write, level);
+    }
+}
+
+
+/* Address Translation Cache
+ *
+ * The ATC uses a pseudo-least-recently-used algorithm to keep track of
+ * least recently used entries. They are replaced if the cache is full.
+ * An internal history-bit (MRU-bit) is used to identify these entries.
+ * If an entry is accessed, its history-bit is set to 1. If after that
+ * there are no more entries with zero-bits, all other history-bits are
+ * set to 0. When no more invalid entries are in the ATC, the first entry
+ * with a zero-bit is replaced.
+ *
+ *
+ * Logical Portion (28 bit):
+ * oooo ---- xxxx xxxx xxxx xxxx xxxx xxxx
+ * logical address (most significant 24 bit)
+ *
+ * oooo -xxx ---- ---- ---- ---- ---- ----
+ * function code
+ *
+ * oooo x--- ---- ---- ---- ---- ---- ----
+ * valid
+ *
+ *
+ * Physical Portion (28 bit):
+ * oooo ---- xxxx xxxx xxxx xxxx xxxx xxxx
+ * physical address
+ *
+ * oooo ---x ---- ---- ---- ---- ---- ----
+ * modified
+ *
+ * oooo --x- ---- ---- ---- ---- ---- ----
+ * write protect
+ *
+ * oooo -x-- ---- ---- ---- ---- ---- ----
+ * cache inhibit
+ *
+ * oooo x--- ---- ---- ---- ---- ---- ----
+ * bus error
+ *
+ */
+
+#define ATC030_MASK         0x0FFFFFFF
+#define ATC030_ADDR_MASK    0x00FFFFFF /* after masking shift 8 (<< 8) */
+
+#define ATC030_LOG_FC   0x07000000
+#define ATC030_LOG_V    0x08000000
+
+#define ATC030_PHYS_M   0x01000000
+#define ATC030_PHYS_WP  0x02000000
+#define ATC030_PHYS_CI  0x04000000
+#define ATC030_PHYS_BE  0x08000000
+
+void mmu030_page_fault(uaecptr addr, bool read, int flags, uae_u32 fc) {
+	regs.mmu_fault_addr = addr;
+	regs.mmu_ssw = (fc & 1) ? MMU030_SSW_DF | (MMU030_SSW_DF << 1) : (MMU030_SSW_FB | MMU030_SSW_RB);
+	regs.mmu_ssw |= read ? MMU030_SSW_RW : 0;
+	regs.mmu_ssw |= flags;
+	regs.mmu_ssw |= fc;
+    bBusErrorReadWrite = read; 
+	mm030_stageb_address = addr;
+#if MMUDEBUG
+	write_log(_T("MMU: page fault (logical addr=%08X SSW=%04x read=%d size=%d fc=%d pc=%08x ob=%08x ins=%04X)\n"),
+		addr, regs.mmu_ssw, read, (flags & MMU030_SSW_SIZE_B) ? 1 : (flags & MMU030_SSW_SIZE_W) ? 2 : 4, fc,
+		regs.instruction_pc, (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM1) ? mmu030_data_buffer : mmu030_ad[mmu030_idx].val, mmu030_opcode & 0xffff);
+#endif
+	
+//	extern void activate_debugger(void);
+//	activate_debugger ();
+
+	THROW(2);
+}
+
+void mmu030_put_long_atc(uaecptr addr, uae_u32 val, int l, uae_u32 fc) {
+    uae_u32 page_index = addr & mmu030.translation.page.mask;
+    uae_u32 addr_mask = mmu030.translation.page.imask;
+    
+    uae_u32 physical_addr = mmu030.atc[l].physical.addr&addr_mask;
+#if MMU030_ATC_DBG_MSG
+    write_log(_T("ATC match(%i): page addr = %08X, index = %08X (lput %08X)\n"),
+              l, physical_addr, page_index, val);
+#endif
+    physical_addr += page_index;
+    
+    if (mmu030.atc[l].physical.bus_error || mmu030.atc[l].physical.write_protect) {
+        mmu030_page_fault(addr, false, MMU030_SSW_SIZE_L, fc);
+        return;
+    }
+
+    phys_put_long(physical_addr, val);
+}
+
+void mmu030_put_word_atc(uaecptr addr, uae_u16 val, int l, uae_u32 fc) {
+    uae_u32 page_index = addr & mmu030.translation.page.mask;
+    uae_u32 addr_mask = mmu030.translation.page.imask;
+    
+    uae_u32 physical_addr = mmu030.atc[l].physical.addr&addr_mask;
+#if MMU030_ATC_DBG_MSG
+    write_log(_T("ATC match(%i): page addr = %08X, index = %08X (wput %04X)\n"),
+              l, physical_addr, page_index, val);
+#endif
+    physical_addr += page_index;
+    
+    if (mmu030.atc[l].physical.bus_error || mmu030.atc[l].physical.write_protect) {
+        mmu030_page_fault(addr, false, MMU030_SSW_SIZE_W, fc);
+        return;
+    }
+
+    phys_put_word(physical_addr, val);
+}
+
+void mmu030_put_byte_atc(uaecptr addr, uae_u8 val, int l, uae_u32 fc) {
+    uae_u32 page_index = addr & mmu030.translation.page.mask;
+    uae_u32 addr_mask = mmu030.translation.page.imask;
+    
+    uae_u32 physical_addr = mmu030.atc[l].physical.addr&addr_mask;
+#if MMU030_ATC_DBG_MSG
+    write_log(_T("ATC match(%i): page addr = %08X, index = %08X (bput %02X)\n"),
+              l, physical_addr, page_index, val);
+#endif
+    physical_addr += page_index;
+    
+    if (mmu030.atc[l].physical.bus_error || mmu030.atc[l].physical.write_protect) {
+        mmu030_page_fault(addr, false, MMU030_SSW_SIZE_B, fc);
+        return;
+    }
+
+    phys_put_byte(physical_addr, val);
+}
+
+uae_u32 mmu030_get_long_atc(uaecptr addr, int l, uae_u32 fc) {
+    uae_u32 page_index = addr & mmu030.translation.page.mask;
+    uae_u32 addr_mask = mmu030.translation.page.imask;
+    
+    uae_u32 physical_addr = mmu030.atc[l].physical.addr&addr_mask;
+#if MMU030_ATC_DBG_MSG
+    write_log(_T("ATC match(%i): page addr = %08X, index = %08X (lget %08X)\n"), l,
+              physical_addr, page_index, phys_get_long(physical_addr+page_index));
+#endif
+    physical_addr += page_index;
+    
+    if (mmu030.atc[l].physical.bus_error) {
+        mmu030_page_fault(addr, true, MMU030_SSW_SIZE_L, fc);
+        return 0;
+    }
+
+    return phys_get_long(physical_addr);
+}
+uae_u32 mmu030_get_ilong_atc(uaecptr addr, int l, uae_u32 fc) {
+	uae_u32 page_index = addr & mmu030.translation.page.mask;
+	uae_u32 addr_mask = mmu030.translation.page.imask;
+
+	uae_u32 physical_addr = mmu030.atc[l].physical.addr&addr_mask;
+#if MMU030_ATC_DBG_MSG
+	write_log(_T("ATC match(%i): page addr = %08X, index = %08X (lget %08X)\n"), l,
+		physical_addr, page_index, phys_get_long(physical_addr + page_index));
+#endif
+	physical_addr += page_index;
+
+	if (mmu030.atc[l].physical.bus_error) {
+		mmu030_page_fault(addr, true, MMU030_SSW_SIZE_L, fc);
+		return 0;
+	}
+
+	return x_phys_get_ilong(physical_addr);
+}
+
+uae_u16 mmu030_get_word_atc(uaecptr addr, int l, uae_u32 fc) {
+    uae_u32 page_index = addr & mmu030.translation.page.mask;
+    uae_u32 addr_mask = mmu030.translation.page.imask;
+    
+    uae_u32 physical_addr = mmu030.atc[l].physical.addr&addr_mask;
+#if MMU030_ATC_DBG_MSG
+    write_log(_T("ATC match(%i): page addr = %08X, index = %08X (wget %04X)\n"), l,
+              physical_addr, page_index, phys_get_word(physical_addr+page_index));
+#endif
+    physical_addr += page_index;
+    
+    if (mmu030.atc[l].physical.bus_error) {
+        mmu030_page_fault(addr, true, MMU030_SSW_SIZE_W, fc);
+        return 0;
+    }
+    
+    return phys_get_word(physical_addr);
+}
+
+uae_u16 mmu030_get_iword_atc(uaecptr addr, int l, uae_u32 fc) {
+	uae_u32 page_index = addr & mmu030.translation.page.mask;
+	uae_u32 addr_mask = mmu030.translation.page.imask;
+
+	uae_u32 physical_addr = mmu030.atc[l].physical.addr&addr_mask;
+#if MMU030_ATC_DBG_MSG
+	write_log(_T("ATC match(%i): page addr = %08X, index = %08X (wget %04X)\n"), l,
+		physical_addr, page_index, phys_get_word(physical_addr + page_index));
+#endif
+	physical_addr += page_index;
+
+	if (mmu030.atc[l].physical.bus_error) {
+		mmu030_page_fault(addr, true, MMU030_SSW_SIZE_W, fc);
+		return 0;
+	}
+
+	return x_phys_get_iword(physical_addr);
+}
+
+uae_u8 mmu030_get_byte_atc(uaecptr addr, int l, uae_u32 fc) {
+    uae_u32 page_index = addr & mmu030.translation.page.mask;
+    uae_u32 addr_mask = mmu030.translation.page.imask;
+    
+    uae_u32 physical_addr = mmu030.atc[l].physical.addr&addr_mask;
+#if MMU030_ATC_DBG_MSG
+    write_log(_T("ATC match(%i): page addr = %08X, index = %08X (bget %02X)\n"), l,
+              physical_addr, page_index, phys_get_byte(physical_addr+page_index));
+#endif
+    physical_addr += page_index;
+    
+    if (mmu030.atc[l].physical.bus_error) {
+        mmu030_page_fault(addr, true, MMU030_SSW_SIZE_B, fc);
+        return 0;
+    }
+
+    return phys_get_byte(physical_addr);
+}
+
+/* Generic versions of above */
+void mmu030_put_atc_generic(uaecptr addr, uae_u32 val, int l, uae_u32 fc, int size, int flags) {
+    uae_u32 page_index = addr & mmu030.translation.page.mask;
+    uae_u32 addr_mask = mmu030.translation.page.imask;
+    
+    uae_u32 physical_addr = mmu030.atc[l].physical.addr & addr_mask;
+#if MMU030_ATC_DBG_MSG
+    write_log(_T("ATC match(%i): page addr = %08X, index = %08X (bput %02X)\n"),
+              l, physical_addr, page_index, val);
+#endif
+    physical_addr += page_index;
+    
+    if (mmu030.atc[l].physical.write_protect || mmu030.atc[l].physical.bus_error) {
+		mmu030_page_fault(addr, false, flags, fc);
+        return;
+    }
+	if (size == sz_byte)
+	    phys_put_byte(physical_addr, val);
+	else if (size == sz_word)
+	    phys_put_word(physical_addr, val);
+	else
+	    phys_put_long(physical_addr, val);
+
+}
+uae_u32 mmu030_get_atc_generic(uaecptr addr, int l, uae_u32 fc, int size, int flags, bool checkwrite) {
+    uae_u32 page_index = addr & mmu030.translation.page.mask;
+    uae_u32 addr_mask = mmu030.translation.page.imask;
+    
+    uae_u32 physical_addr = mmu030.atc[l].physical.addr & addr_mask;
+#if MMU030_ATC_DBG_MSG
+    write_log(_T("ATC match(%i): page addr = %08X, index = %08X (bget %02X)\n"), l,
+              physical_addr, page_index, phys_get_byte(physical_addr+page_index));
+#endif
+    physical_addr += page_index;
+    
+	if (mmu030.atc[l].physical.bus_error || (checkwrite && mmu030.atc[l].physical.write_protect)) {
+        mmu030_page_fault(addr, true, flags, fc);
+        return 0;
+    }
+	if (size == sz_byte)
+		return phys_get_byte(physical_addr);
+	else if (size == sz_word)
+		return phys_get_word(physical_addr);
+	return phys_get_long(physical_addr);
+}
+
+
+/* This function checks if a certain logical address is in the ATC 
+ * by comparing the logical address and function code to the values
+ * stored in the ATC entries. If a matching entry is found it sets
+ * the history bit and returns the cache index of the entry. */
+int mmu030_logical_is_in_atc(uaecptr addr, uae_u32 fc, bool write) {
+    uaecptr logical_addr = 0;
+    uae_u32 addr_mask = mmu030.translation.page.imask;
+	uae_u32 maddr = addr & addr_mask;
+    int offset = (maddr >> mmu030.translation.page.size) & 0x1f;
+
+    int i, index;
+	index = atcindextable[offset];
+    for (i=0; i= ATC030_NUM_ENTRIES)
+			index = 0;
+    }
+    return -1;
+}
+
+void mmu030_atc_handle_history_bit(int entry_num) {
+    int j;
+    mmu030.atc[entry_num].mru = 1;
+    for (j=0; j=0) {
+        mmu030_put_long_atc(addr, val, atc_line_num, fc);
+    } else {
+        mmu030_table_search(addr,fc,true,0);
+        mmu030_put_long_atc(addr, val, mmu030_logical_is_in_atc(addr,fc,true), fc);
+    }
+}
+
+void mmu030_put_word(uaecptr addr, uae_u16 val, uae_u32 fc) {
+    
+	//                                        addr,super,write
+	if ((!mmu030.enabled) || (mmu030_match_ttr_access(addr,fc,true)) || (fc==7)) {
+		phys_put_word(addr,val);
+		return;
+    }
+    
+    int atc_line_num = mmu030_logical_is_in_atc(addr, fc, true);
+    
+    if (atc_line_num>=0) {
+        mmu030_put_word_atc(addr, val, atc_line_num, fc);
+    } else {
+        mmu030_table_search(addr, fc, true, 0);
+        mmu030_put_word_atc(addr, val, mmu030_logical_is_in_atc(addr,fc,true), fc);
+    }
+}
+
+void mmu030_put_byte(uaecptr addr, uae_u8 val, uae_u32 fc) {
+    
+	//                                        addr,super,write
+	if ((!mmu030.enabled) || (mmu030_match_ttr_access(addr, fc, true)) || (fc==7)) {
+		phys_put_byte(addr,val);
+		return;
+    }
+    
+    int atc_line_num = mmu030_logical_is_in_atc(addr, fc, true);
+
+    if (atc_line_num>=0) {
+        mmu030_put_byte_atc(addr, val, atc_line_num, fc);
+    } else {
+        mmu030_table_search(addr, fc, true, 0);
+        mmu030_put_byte_atc(addr, val, mmu030_logical_is_in_atc(addr,fc,true), fc);
+    }
+}
+
+uae_u32 mmu030_get_ilong(uaecptr addr, uae_u32 fc) {
+
+	//                                        addr,super,write
+	if ((!mmu030.enabled) || (mmu030_match_ttr_access(addr, fc, false)) || (fc == 7)) {
+		return x_phys_get_ilong(addr);
+	}
+
+	int atc_line_num = mmu030_logical_is_in_atc(addr, fc, false);
+
+	if (atc_line_num >= 0) {
+		return mmu030_get_ilong_atc(addr, atc_line_num, fc);
+	}
+	else {
+		mmu030_table_search(addr, fc, false, 0);
+		return mmu030_get_ilong_atc(addr, mmu030_logical_is_in_atc(addr, fc, false), fc);
+	}
+}
+uae_u32 mmu030_get_long(uaecptr addr, uae_u32 fc) {
+    
+	//                                        addr,super,write
+	if ((!mmu030.enabled) || (mmu030_match_ttr_access(addr,fc,false)) || (fc==7)) {
+		return phys_get_long(addr);
+    }
+    
+    int atc_line_num = mmu030_logical_is_in_atc(addr, fc, false);
+
+    if (atc_line_num>=0) {
+        return mmu030_get_long_atc(addr, atc_line_num, fc);
+    } else {
+        mmu030_table_search(addr, fc, false, 0);
+        return mmu030_get_long_atc(addr, mmu030_logical_is_in_atc(addr,fc,false), fc);
+    }
+}
+
+uae_u16 mmu030_get_iword(uaecptr addr, uae_u32 fc) {
+
+	//                                        addr,super,write
+	if ((!mmu030.enabled) || (mmu030_match_ttr_access(addr, fc, false)) || (fc == 7)) {
+		return x_phys_get_iword(addr);
+	}
+
+	int atc_line_num = mmu030_logical_is_in_atc(addr, fc, false);
+
+	if (atc_line_num >= 0) {
+		return mmu030_get_iword_atc(addr, atc_line_num, fc);
+	} else {
+		mmu030_table_search(addr, fc, false, 0);
+		return mmu030_get_iword_atc(addr, mmu030_logical_is_in_atc(addr, fc, false), fc);
+	}
+}
+uae_u16 mmu030_get_word(uaecptr addr, uae_u32 fc) {
+    
+	//                                        addr,super,write
+	if ((!mmu030.enabled) || (mmu030_match_ttr_access(addr,fc,false)) || (fc==7)) {
+		return phys_get_word(addr);
+    }
+    
+    int atc_line_num = mmu030_logical_is_in_atc(addr, fc, false);
+
+    if (atc_line_num>=0) {
+        return mmu030_get_word_atc(addr, atc_line_num, fc);
+    } else {
+        mmu030_table_search(addr, fc, false, 0);
+        return mmu030_get_word_atc(addr, mmu030_logical_is_in_atc(addr,fc,false), fc);
+    }
+}
+
+uae_u8 mmu030_get_byte(uaecptr addr, uae_u32 fc) {
+    
+	//                                        addr,super,write
+	if ((!mmu030.enabled) || (mmu030_match_ttr_access(addr,fc,false)) || (fc==7)) {
+		return phys_get_byte(addr);
+    }
+    
+    int atc_line_num = mmu030_logical_is_in_atc(addr, fc, false);
+
+    if (atc_line_num>=0) {
+        return mmu030_get_byte_atc(addr, atc_line_num, fc);
+    } else {
+        mmu030_table_search(addr, fc, false, 0);
+        return mmu030_get_byte_atc(addr, mmu030_logical_is_in_atc(addr,fc,false), fc);
+    }
+}
+
+
+/* Not commonly used access function */
+void mmu030_put_generic(uaecptr addr, uae_u32 val, uae_u32 fc, int size, int accesssize, int flags) {
+    
+	//                                        addr,super,write
+	if ((!mmu030.enabled) || (mmu030_match_ttr_access(addr, fc, true)) || (fc==7)) {
+		if (size == sz_byte)
+			phys_put_byte(addr, val);
+		else if (size == sz_word)
+			phys_put_word(addr, val);
+		else
+			phys_put_long(addr, val);
+		return;
+    }
+    
+    int atc_line_num = mmu030_logical_is_in_atc(addr, fc, true);
+    if (atc_line_num>=0) {
+        mmu030_put_atc_generic(addr, val, atc_line_num, fc, size, flags);
+    } else {
+        mmu030_table_search(addr, fc, true, 0);
+		atc_line_num = mmu030_logical_is_in_atc(addr, fc, true);
+		if (accesssize == sz_byte)
+			flags |= MMU030_SSW_SIZE_B;
+		else if (accesssize == sz_word)
+			flags |= MMU030_SSW_SIZE_W;
+        mmu030_put_atc_generic(addr, val, atc_line_num, fc, size, flags);
+    }
+}
+static uae_u32 mmu030_get_generic_lrmw(uaecptr addr, uae_u32 fc, int size, int accesssize, int flags) {
+    
+	//                                        addr,super,write
+	if ((!mmu030.enabled) || (mmu030_match_lrmw_ttr_access(addr,fc)) || (fc==7)) {
+		if (size == sz_byte)
+			return phys_get_byte(addr);
+		else if (size == sz_word)
+			return phys_get_word(addr);
+		return phys_get_long(addr);
+    }
+    
+    int atc_line_num = mmu030_logical_is_in_atc(addr, fc, true);
+    if (atc_line_num>=0) {
+        return mmu030_get_atc_generic(addr, atc_line_num, fc, size, flags, true);
+    } else {
+        mmu030_table_search(addr, fc, true, 0);
+		atc_line_num = mmu030_logical_is_in_atc(addr, fc, true);
+		if (accesssize == sz_byte)
+			flags |= MMU030_SSW_SIZE_B;
+		else if (accesssize == sz_word)
+			flags |= MMU030_SSW_SIZE_W;
+        return mmu030_get_atc_generic(addr, atc_line_num, fc, size, flags, true);
+    }
+}
+uae_u32 mmu030_get_generic(uaecptr addr, uae_u32 fc, int size, int accesssize, int flags) {
+	if (flags & MMU030_SSW_RM) {
+		return mmu030_get_generic_lrmw(addr, fc, size, accesssize, flags);
+	}
+	//                                        addr,super,write
+	if ((!mmu030.enabled) || (mmu030_match_ttr_access(addr,fc,false)) || (fc==7)) {
+		if (size == sz_byte)
+			return phys_get_byte(addr);
+		else if (size == sz_word)
+			return phys_get_word(addr);
+		return phys_get_long(addr);
+    }
+    
+    int atc_line_num = mmu030_logical_is_in_atc(addr, fc, false);
+    if (atc_line_num>=0) {
+        return mmu030_get_atc_generic(addr, atc_line_num, fc, size, flags, false);
+    } else {
+        mmu030_table_search(addr, fc, false, 0);
+		atc_line_num = mmu030_logical_is_in_atc(addr, fc, false);
+		if (accesssize == sz_byte)
+			flags |= MMU030_SSW_SIZE_B;
+		else if (accesssize == sz_word)
+			flags |= MMU030_SSW_SIZE_W;
+        return mmu030_get_atc_generic(addr, atc_line_num, fc, size, flags, false);
+    }
+}
+
+
+/* Locked RMW is rarely used */
+uae_u32 uae_mmu030_get_lrmw(uaecptr addr, int size)
+{
+    uae_u32 fc = (regs.s ? 4 : 0) | 1;
+	if (size == sz_byte) {
+		return mmu030_get_generic(addr, fc, size, size, MMU030_SSW_RM);
+	} else if (size == sz_word) {
+		if (unlikely(is_unaligned(addr, 2)))
+			return mmu030_get_word_unaligned(addr, fc, MMU030_SSW_RM);
+		else
+			return mmu030_get_generic(addr, fc, size, size, MMU030_SSW_RM);
+	} else {
+		if (unlikely(is_unaligned(addr, 4)))
+			return mmu030_get_long_unaligned(addr, fc, MMU030_SSW_RM);
+		else
+			return mmu030_get_generic(addr, fc, size, size, MMU030_SSW_RM);
+	}
+}
+void uae_mmu030_put_lrmw(uaecptr addr, uae_u32 val, int size)
+{
+    uae_u32 fc = (regs.s ? 4 : 0) | 1;
+	if (size == sz_byte) {
+		mmu030_put_generic(addr, val, fc, size, size, MMU030_SSW_RM);
+	} else if (size == sz_word) {
+		if (unlikely(is_unaligned(addr, 2)))
+			mmu030_put_word_unaligned(addr, val, fc, MMU030_SSW_RM);
+		else
+			mmu030_put_generic(addr, val, fc, size, size, MMU030_SSW_RM);
+	} else {
+		if (unlikely(is_unaligned(addr, 4)))
+			mmu030_put_long_unaligned(addr, val, fc, MMU030_SSW_RM);
+		else
+			mmu030_put_generic(addr, val, fc, size, size, MMU030_SSW_RM);
+	}
+}
+uae_u16 REGPARAM2 mmu030_get_word_unaligned(uaecptr addr, uae_u32 fc, int flags)
+{
+	uae_u16 res;
+    
+	res = (uae_u16)mmu030_get_generic(addr, fc, sz_byte, sz_word, flags) << 8;
+	SAVE_EXCEPTION;
+	TRY(prb) {
+		res |= mmu030_get_generic(addr + 1, fc, sz_byte, sz_word, flags);
+		RESTORE_EXCEPTION;
+	}
+	CATCH(prb) {
+		RESTORE_EXCEPTION;
+		THROW_AGAIN(prb);
+	} ENDTRY
+	return res;
+}
+
+uae_u32 REGPARAM2 mmu030_get_ilong_unaligned(uaecptr addr, uae_u32 fc, int flags)
+{
+	uae_u32 res;
+
+	res = (uae_u32)mmu030_get_iword(addr, fc) << 16;
+	SAVE_EXCEPTION;
+	TRY(prb) {
+		res |= mmu030_get_iword(addr + 2, fc);
+		RESTORE_EXCEPTION;
+	}
+	CATCH(prb) {
+		RESTORE_EXCEPTION;
+		THROW_AGAIN(prb);
+	} ENDTRY
+	return res;
+}
+
+uae_u32 REGPARAM2 mmu030_get_long_unaligned(uaecptr addr, uae_u32 fc, int flags)
+{
+	uae_u32 res;
+    
+	if (likely(!(addr & 1))) {
+		res = (uae_u32)mmu030_get_generic(addr, fc, sz_word, sz_long, flags) << 16;
+		SAVE_EXCEPTION;
+		TRY(prb) {
+			res |= mmu030_get_generic(addr + 2, fc, sz_word, sz_long, flags);
+			RESTORE_EXCEPTION;
+		}
+		CATCH(prb) {
+			RESTORE_EXCEPTION;
+			THROW_AGAIN(prb);
+		} ENDTRY
+	} else {
+		res = (uae_u32)mmu030_get_generic(addr, fc, sz_byte, sz_long, flags) << 8;
+		SAVE_EXCEPTION;
+		TRY(prb) {
+			res = (res | mmu030_get_generic(addr + 1, fc, sz_byte, sz_long, flags)) << 8;
+			res = (res | mmu030_get_generic(addr + 2, fc, sz_byte, sz_long, flags)) << 8;
+			res |= mmu030_get_generic(addr + 3, fc, sz_byte, sz_long, flags);
+			RESTORE_EXCEPTION;
+		}
+		CATCH(prb) {
+			RESTORE_EXCEPTION;
+			THROW_AGAIN(prb);
+		} ENDTRY
+	}
+	return res;
+}
+
+
+void REGPARAM2 mmu030_put_long_unaligned(uaecptr addr, uae_u32 val, uae_u32 fc, int flags)
+{
+	SAVE_EXCEPTION;
+	TRY(prb) {
+		if (likely(!(addr & 1))) {
+			mmu030_put_generic(addr, val >> 16, fc, sz_word, sz_long, flags);
+			mmu030_put_generic(addr + 2, val, fc, sz_word, sz_long, flags);
+		} else {
+			mmu030_put_generic(addr, val >> 24, fc, sz_byte, sz_long, flags);
+			mmu030_put_generic(addr + 1, val >> 16, fc, sz_byte, sz_long, flags);
+			mmu030_put_generic(addr + 2, val >> 8, fc, sz_byte, sz_long, flags);
+			mmu030_put_generic(addr + 3, val, fc, sz_byte, sz_long, flags);
+		}
+		RESTORE_EXCEPTION;
+	}
+	CATCH(prb) {
+		RESTORE_EXCEPTION;
+		regs.wb3_data = val;
+		THROW_AGAIN(prb);
+	} ENDTRY
+}
+
+void REGPARAM2 mmu030_put_word_unaligned(uaecptr addr, uae_u16 val, uae_u32 fc, int flags)
+{
+	SAVE_EXCEPTION;
+	TRY(prb) {
+		mmu030_put_generic(addr, val >> 8, fc, sz_byte, sz_word, flags);
+		mmu030_put_generic(addr + 1, val, fc, sz_byte, sz_word, flags);
+		RESTORE_EXCEPTION;
+	}
+	CATCH(prb) {
+		RESTORE_EXCEPTION;
+		regs.wb3_data = val;
+		THROW_AGAIN(prb);
+	} ENDTRY
+}
+
+
+/* Used by debugger */
+static uaecptr mmu030_get_addr_atc(uaecptr addr, int l, uae_u32 fc, bool write) {
+    uae_u32 page_index = addr & mmu030.translation.page.mask;
+    uae_u32 addr_mask = mmu030.translation.page.imask;
+    
+    uae_u32 physical_addr = mmu030.atc[l].physical.addr&addr_mask;
+    physical_addr += page_index;
+    
+	if (mmu030.atc[l].physical.bus_error || (write && mmu030.atc[l].physical.write_protect)) {
+        mmu030_page_fault(addr, write == 0, MMU030_SSW_SIZE_B, fc);
+        return 0;
+    }
+
+    return physical_addr;
+}
+uaecptr mmu030_translate(uaecptr addr, bool super, bool data, bool write)
+{
+	int fc = (super ? 4 : 0) | (data ? 1 : 2);
+	if ((!mmu030.enabled) || (mmu030_match_ttr(addr,fc,write)&TT_OK_MATCH) || (fc==7)) {
+		return addr;
+    }
+    int atc_line_num = mmu030_logical_is_in_atc(addr, fc, write);
+
+    if (atc_line_num>=0) {
+        return mmu030_get_addr_atc(addr, atc_line_num, fc, write);
+    } else {
+        mmu030_table_search(addr, fc, false, 0);
+        return mmu030_get_addr_atc(addr, mmu030_logical_is_in_atc(addr,fc,write), fc, write);
+    }
+}
+
+#ifndef WINUAE_FOR_HATARI
+static uae_u32 get_dcache_byte(uaecptr addr)
+{
+	return read_dcache030(addr, 0);
+}
+static uae_u32 get_dcache_word(uaecptr addr)
+{
+	return read_dcache030(addr, 1);
+}
+static uae_u32 get_dcache_long(uaecptr addr)
+{
+	return read_dcache030(addr, 2);
+}
+static void put_dcache_byte(uaecptr addr, uae_u32 v)
+{
+	write_dcache030(addr, v, 0);
+}
+static void put_dcache_word(uaecptr addr, uae_u32 v)
+{
+	write_dcache030(addr, v, 1);
+}
+static void put_dcache_long(uaecptr addr, uae_u32 v)
+{
+	write_dcache030(addr, v, 2);
+}
+#endif
+
+/* MMU Reset */
+void mmu030_reset(int hardreset)
+{
+    /* A CPU reset causes the E-bits of TC and TT registers to be zeroed. */
+    mmu030.enabled = false;
+	regs.mmu_page_size = 0;
+	tc_030 &= ~TC_ENABLE_TRANSLATION;
+	tt0_030 &= ~TT_ENABLE;
+	tt1_030 &= ~TT_ENABLE;
+	if (hardreset) {
+		srp_030 = crp_030 = 0;
+		tt0_030 = tt1_030 = tc_030 = 0;
+        mmusr_030 = 0;
+        mmu030_flush_atc_all();
+	}
+	mmu030_set_funcs();
+}
+
+void mmu030_set_funcs(void)
+{
+	if (currprefs.mmu_model != 68030)
+		return;
+	if (currprefs.cpu_cycle_exact || currprefs.cpu_compatible) {
+		x_phys_get_iword = get_word_icache030;
+		x_phys_get_ilong = get_long_icache030;
+	} else {
+		x_phys_get_iword = phys_get_word;
+		x_phys_get_ilong = phys_get_long;
+	}
+}
+
+
+void m68k_do_rte_mmu030 (uaecptr a7)
+{
+	// Restore access error exception state
+
+	uae_u16 format = get_word_mmu030 (a7 + 6);
+	uae_u16 frame = format >> 12;
+	uae_u16 ssw = get_word_mmu030 (a7 + 10);
+
+	// Fetch last word, real CPU does it to allow OS bus handler to map
+	// the page if frame crosses pages and following page is not resident.
+	if (frame == 0xb)
+		get_word_mmu030(a7 + 92 - 2);
+	else
+		get_word_mmu030(a7 + 32 - 2);
+
+	// Internal register, our opcode storage area
+	mmu030_opcode = get_long_mmu030 (a7 + 0x14);
+	// Misc state data
+	mmu030_state[0] = get_word_mmu030 (a7 + 0x30);
+	mmu030_state[1] = get_word_mmu030 (a7 + 0x32);
+	mmu030_state[2] = get_word_mmu030 (a7 + 0x34);
+	mmu030_disp_store[0] = get_long_mmu030 (a7 + 0x1c);
+	mmu030_disp_store[1] = get_long_mmu030 (a7 + 0x1c + 4);
+	if (mmu030_state[1] & MMU030_STATEFLAG1_FMOVEM) {
+		mmu030_fmovem_store[0] = get_long_mmu030 (a7 + 0x5c - (7 + 1) * 4);
+		mmu030_fmovem_store[1] = get_long_mmu030 (a7 + 0x5c - (8 + 1) * 4);
+	}
+	// Rerun "mmu030_opcode" using restored state.
+	mmu030_retry = true;
+
+	if (frame == 0xb) {
+		uae_u16 idxsize = get_word_mmu030 (a7 + 0x36);
+		int i;
+		for (i = 0; i < idxsize + 1; i++) {
+			mmu030_ad[i].done = i < idxsize;
+			mmu030_ad[i].val = get_long_mmu030 (a7 + 0x5c - (i + 1) * 4);
+		}
+		mmu030_ad[idxsize + 1].done = false;
+		// did we have data fault but DF bit cleared?
+		if (ssw & (MMU030_SSW_DF << 1) && !(ssw & MMU030_SSW_DF)) {
+			// DF not set: mark access as done
+			if (ssw & MMU030_SSW_RM) {
+				// Read-Modify-Write: whole instruction is considered done
+				write_log (_T("Read-Modify-Write and DF bit cleared! PC=%08x\n"), regs.instruction_pc);
+				mmu030_retry = false;
+			} else if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM1) {
+				// if movem, skip next move
+				mmu030_data_buffer = get_long_mmu030 (a7 + 0x2c);
+				mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM2;
+			} else {
+				mmu030_ad[idxsize].done = true;
+				if (ssw & MMU030_SSW_RW) {
+					// Read and no DF: use value in data input buffer
+					mmu030_data_buffer = get_long_mmu030 (a7 + 0x2c);
+					mmu030_ad[idxsize].val = mmu030_data_buffer;
+				}
+			}
+		}
+		// did we have ins fault and RB bit cleared?
+		if ((ssw & MMU030_SSW_FB) && !(ssw & MMU030_SSW_RB)) {
+			uae_u16 stageb = get_word_mmu030 (a7 + 0x0e);
+			if (mmu030_opcode == -1) {
+				mmu030_opcode_stageb = stageb;
+				write_log (_T("Software fixed stage B! opcode = %04x\n"), stageb);
+			} else {
+				mmu030_ad[idxsize].done = true;
+				mmu030_ad[idxsize].val = stageb;
+				write_log (_T("Software fixed stage B! opcode = %04X, opword = %04x\n"), mmu030_opcode, stageb);
+			}
+		}
+		m68k_areg (regs, 7) += 92;
+	} else {
+		m68k_areg (regs, 7) += 32;
+	}
+}
+
+void flush_mmu030 (uaecptr addr, int n)
+{
+}
+
+void m68k_do_rts_mmu030 (void)
+{
+	m68k_setpc (get_long_mmu030_state (m68k_areg (regs, 7)));
+	m68k_areg (regs, 7) += 4;
+}
+
+void m68k_do_bsr_mmu030 (uaecptr oldpc, uae_s32 offset)
+{
+	put_long_mmu030_state (m68k_areg (regs, 7) - 4, oldpc);
+	m68k_areg (regs, 7) -= 4;
+	m68k_incpci (offset);
+}
+
+uae_u32 REGPARAM2 get_disp_ea_020_mmu030 (uae_u32 base, int idx)
+{
+	uae_u16 dp;
+	int reg;
+	uae_u32 v;
+	int oldidx;
+	int pcadd = 0;
+
+	// we need to do this hack here because in worst case we don't have enough
+	// stack frame space to store two very large 020 addressing mode access state
+	// + whatever the instruction itself does.
+
+	if (mmu030_state[1] & (1 << idx)) {
+		m68k_incpci (((mmu030_state[2] >> (idx * 4)) & 15) * 2);
+		return mmu030_disp_store[idx];
+	}
+
+	oldidx = mmu030_idx;
+	dp = next_iword_mmu030_state ();
+	pcadd += 1;
+	
+	reg = (dp >> 12) & 15;
+	uae_s32 regd = regs.regs[reg];
+	if ((dp & 0x800) == 0)
+		regd = (uae_s32)(uae_s16)regd;
+	regd <<= (dp >> 9) & 3;
+	if (dp & 0x100) {
+		uae_s32 outer = 0;
+		if (dp & 0x80)
+			base = 0;
+		if (dp & 0x40)
+			regd = 0;
+
+		if ((dp & 0x30) == 0x20) {
+			base += (uae_s32)(uae_s16) next_iword_mmu030_state ();
+			pcadd += 1;
+		}
+		if ((dp & 0x30) == 0x30) {
+			base += next_ilong_mmu030_state ();
+			pcadd += 2;
+		}
+
+		if ((dp & 0x3) == 0x2) {
+			outer = (uae_s32)(uae_s16) next_iword_mmu030_state ();
+			pcadd += 1;
+		}
+		if ((dp & 0x3) == 0x3) {
+			outer = next_ilong_mmu030_state ();
+			pcadd += 2;
+		}
+
+		if ((dp & 0x4) == 0) {
+			base += regd;
+		}
+		if (dp & 0x3) {
+			base = get_long_mmu030_state (base);
+		}
+		if (dp & 0x4) {
+			base += regd;
+		}
+		v = base + outer;
+	} else {
+		v = base + (uae_s32)((uae_s8)dp) + regd;
+	}
+
+	mmu030_state[1] |= 1 << idx;
+	mmu030_state[2] |= pcadd << (idx * 4);
+	mmu030_disp_store[idx] = v;
+	mmu030_idx = oldidx;
+	mmu030_ad[mmu030_idx].done = false;
+
+	return v;
+}
diff --git a/src/cpu/cpummu030.h b/src/cpu/cpummu030.h
new file mode 100644
index 0000000..0984a66
--- /dev/null
+++ b/src/cpu/cpummu030.h
@@ -0,0 +1,477 @@
+#ifndef CPUMMU030_H
+#define CPUMMU030_H
+
+#include "mmu_common.h"
+
+extern uae_u64 srp_030, crp_030;
+extern uae_u32 tt0_030, tt1_030, tc_030;
+extern uae_u16 mmusr_030;
+
+#define MAX_MMU030_ACCESS 10
+extern uae_u32 mm030_stageb_address;
+extern int mmu030_idx;
+extern bool mmu030_retry;
+extern int mmu030_opcode, mmu030_opcode_stageb;
+extern int mmu030_fake_prefetch;
+extern uaecptr mmu030_fake_prefetch_addr;
+extern uae_u16 mmu030_state[3];
+extern uae_u32 mmu030_data_buffer;
+extern uae_u32 mmu030_disp_store[2];
+extern uae_u32 mmu030_fmovem_store[2];
+
+#define MMU030_STATEFLAG1_FMOVEM 0x2000
+#define MMU030_STATEFLAG1_MOVEM1 0x4000
+#define MMU030_STATEFLAG1_MOVEM2 0x8000
+#define MMU030_STATEFLAG1_DISP0 0x0001
+#define MMU030_STATEFLAG1_DISP1 0x0002
+
+struct mmu030_access
+{
+	bool done;
+	uae_u32 val;
+};
+extern struct mmu030_access mmu030_ad[MAX_MMU030_ACCESS];
+
+uae_u32 REGPARAM3 get_disp_ea_020_mmu030 (uae_u32 base, int idx) REGPARAM;
+void mmu030_page_fault(uaecptr addr, bool read, int flags, uae_u32 fc);
+
+bool mmu_op30_pmove (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra);
+bool mmu_op30_ptest (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra);
+bool mmu_op30_pload (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra);
+bool mmu_op30_pflush (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra);
+
+uae_u32 mmu_op30_helper_get_fc(uae_u16 next);
+
+void mmu030_ptest_atc_search(uaecptr logical_addr, uae_u32 fc, bool write);
+uae_u32 mmu030_ptest_table_search(uaecptr extra, uae_u32 fc, bool write, int level);
+uae_u32 mmu030_table_search(uaecptr addr, uae_u32 fc, bool write, int level);
+
+
+typedef struct {
+    uae_u32 addr_base;
+    uae_u32 addr_mask;
+    uae_u32 fc_base;
+    uae_u32 fc_mask;
+} TT_info;
+
+TT_info mmu030_decode_tt(uae_u32 TT);
+bool mmu030_decode_tc(uae_u32 TC);
+bool mmu030_decode_rp(uae_u64 RP);
+
+int mmu030_logical_is_in_atc(uaecptr addr, uae_u32 fc, bool write);
+void mmu030_atc_handle_history_bit(int entry_num);
+
+void mmu030_put_long_atc(uaecptr addr, uae_u32 val, int l, uae_u32 fc);
+void mmu030_put_word_atc(uaecptr addr, uae_u16 val, int l, uae_u32 fc);
+void mmu030_put_byte_atc(uaecptr addr, uae_u8 val, int l, uae_u32 fc);
+uae_u32 mmu030_get_long_atc(uaecptr addr, int l, uae_u32 fc);
+uae_u16 mmu030_get_word_atc(uaecptr addr, int l, uae_u32 fc);
+uae_u8 mmu030_get_byte_atc(uaecptr addr, int l, uae_u32 fc);
+#ifdef WINUAE_FOR_HATARI
+uae_u32 mmu030_get_ilong_atc(uaecptr addr, int l, uae_u32 fc);
+uae_u16 mmu030_get_iword_atc(uaecptr addr, int l, uae_u32 fc);
+#endif
+
+void mmu030_put_atc_generic(uaecptr addr, uae_u32 val, int l, uae_u32 fc, int size, int flags);
+uae_u32 mmu030_get_atc_generic(uaecptr addr, int l, uae_u32 fc, int size, int flags, bool checkwrite);
+
+void mmu030_flush_atc_fc(uae_u32 fc_base, uae_u32 fc_mask);
+void mmu030_flush_atc_page(uaecptr logical_addr);
+void mmu030_flush_atc_page_fc(uaecptr logical_addr, uae_u32 fc_base, uae_u32 fc_mask);
+void mmu030_flush_atc_all(void);
+void mmu030_reset(int hardreset);
+void mmu030_set_funcs(void);
+uaecptr mmu030_translate(uaecptr addr, bool super, bool data, bool write);
+
+int mmu030_match_ttr(uaecptr addr, uae_u32 fc, bool write);
+int mmu030_match_ttr_access(uaecptr addr, uae_u32 fc, bool write);
+int mmu030_match_lrmw_ttr_access(uaecptr addr, uae_u32 fc);
+int mmu030_do_match_ttr(uae_u32 tt, TT_info masks, uaecptr addr, uae_u32 fc, bool write);
+int mmu030_do_match_lrmw_ttr(uae_u32 tt, TT_info masks, uaecptr addr, uae_u32 fc);
+
+void mmu030_put_long(uaecptr addr, uae_u32 val, uae_u32 fc);
+void mmu030_put_word(uaecptr addr, uae_u16 val, uae_u32 fc);
+void mmu030_put_byte(uaecptr addr, uae_u8  val, uae_u32 fc);
+uae_u32 mmu030_get_long(uaecptr addr, uae_u32 fc);
+uae_u16 mmu030_get_word(uaecptr addr, uae_u32 fc);
+uae_u8  mmu030_get_byte(uaecptr addr, uae_u32 fc);
+uae_u32 mmu030_get_ilong(uaecptr addr, uae_u32 fc);
+uae_u16 mmu030_get_iword(uaecptr addr, uae_u32 fc);
+
+uae_u32 uae_mmu030_get_lrmw(uaecptr addr, int size);
+void uae_mmu030_put_lrmw(uaecptr addr, uae_u32 val, int size);
+
+void mmu030_put_generic(uaecptr addr, uae_u32 val, uae_u32 fc, int size, int accesssize, int flags);
+uae_u32 mmu030_get_generic(uaecptr addr, uae_u32 fc, int size, int accesssize, int flags);
+
+extern uae_u16 REGPARAM3 mmu030_get_word_unaligned(uaecptr addr, uae_u32 fc, int flags) REGPARAM;
+extern uae_u32 REGPARAM3 mmu030_get_long_unaligned(uaecptr addr, uae_u32 fc, int flags) REGPARAM;
+extern uae_u32 REGPARAM3 mmu030_get_ilong_unaligned(uaecptr addr, uae_u32 fc, int flags) REGPARAM;
+extern uae_u16 REGPARAM3 mmu030_get_lrmw_word_unaligned(uaecptr addr, uae_u32 fc, int flags) REGPARAM;
+extern uae_u32 REGPARAM3 mmu030_get_lrmw_long_unaligned(uaecptr addr, uae_u32 fc, int flags) REGPARAM;
+extern void REGPARAM3 mmu030_put_word_unaligned(uaecptr addr, uae_u16 val, uae_u32 fc, int flags) REGPARAM;
+extern void REGPARAM3 mmu030_put_long_unaligned(uaecptr addr, uae_u32 val, uae_u32 fc, int flags) REGPARAM;
+
+static ALWAYS_INLINE uae_u32 uae_mmu030_get_ilong(uaecptr addr)
+{
+    uae_u32 fc = (regs.s ? 4 : 0) | 2;
+
+	if (unlikely(is_unaligned(addr, 4)))
+		return mmu030_get_ilong_unaligned(addr, fc, 0);
+	return mmu030_get_ilong(addr, fc);
+}
+static ALWAYS_INLINE uae_u16 uae_mmu030_get_iword(uaecptr addr)
+{
+    uae_u32 fc = (regs.s ? 4 : 0) | 2;
+	return mmu030_get_iword(addr, fc);
+}
+static ALWAYS_INLINE uae_u16 uae_mmu030_get_ibyte(uaecptr addr)
+{
+    uae_u32 fc = (regs.s ? 4 : 0) | 2;
+
+	return mmu030_get_byte(addr, fc);
+}
+static ALWAYS_INLINE uae_u32 uae_mmu030_get_long(uaecptr addr)
+{
+    uae_u32 fc = (regs.s ? 4 : 0) | 1;
+
+	if (unlikely(is_unaligned(addr, 4)))
+		return mmu030_get_long_unaligned(addr, fc, 0);
+	return mmu030_get_long(addr, fc);
+}
+static ALWAYS_INLINE uae_u16 uae_mmu030_get_word(uaecptr addr)
+{
+    uae_u32 fc = (regs.s ? 4 : 0) | 1;
+
+	if (unlikely(is_unaligned(addr, 2)))
+		return mmu030_get_word_unaligned(addr, fc, 0);
+	return mmu030_get_word(addr, fc);
+}
+static ALWAYS_INLINE uae_u8 uae_mmu030_get_byte(uaecptr addr)
+{
+    uae_u32 fc = (regs.s ? 4 : 0) | 1;
+
+	return mmu030_get_byte(addr, fc);
+}
+static ALWAYS_INLINE void uae_mmu030_put_long(uaecptr addr, uae_u32 val)
+{
+    uae_u32 fc = (regs.s ? 4 : 0) | 1;
+    
+	if (unlikely(is_unaligned(addr, 4)))
+		mmu030_put_long_unaligned(addr, val, fc, 0);
+	else
+		mmu030_put_long(addr, val, fc);
+}
+static ALWAYS_INLINE void uae_mmu030_put_word(uaecptr addr, uae_u16 val)
+{
+    uae_u32 fc = (regs.s ? 4 : 0) | 1;
+
+	if (unlikely(is_unaligned(addr, 2)))
+		mmu030_put_word_unaligned(addr, val, fc, 0);
+	else
+		mmu030_put_word(addr, val, fc);
+}
+static ALWAYS_INLINE void uae_mmu030_put_byte(uaecptr addr, uae_u8 val)
+{
+    uae_u32 fc = (regs.s ? 4 : 0) | 1;
+
+	mmu030_put_byte(addr, val, fc);
+}
+
+static ALWAYS_INLINE uae_u32 sfc030_get_long(uaecptr addr)
+{
+    uae_u32 fc = regs.sfc;
+#if MMUDEBUG > 2
+	write_log(_T("sfc030_get_long: FC = %i\n"),fc);
+#endif
+	if (unlikely(is_unaligned(addr, 4)))
+		return mmu030_get_long_unaligned(addr, fc, 0);
+	return mmu030_get_long(addr, fc);
+}
+
+static ALWAYS_INLINE uae_u16 sfc030_get_word(uaecptr addr)
+{
+    uae_u32 fc = regs.sfc;
+#if MMUDEBUG > 2
+	write_log(_T("sfc030_get_word: FC = %i\n"),fc);
+#endif
+    if (unlikely(is_unaligned(addr, 2)))
+		return mmu030_get_word_unaligned(addr, fc, 0);
+	return mmu030_get_word(addr, fc);
+}
+
+static ALWAYS_INLINE uae_u8 sfc030_get_byte(uaecptr addr)
+{
+    uae_u32 fc = regs.sfc;
+#if MMUDEBUG > 2
+	write_log(_T("sfc030_get_byte: FC = %i\n"),fc);
+#endif
+	return mmu030_get_byte(addr, fc);
+}
+
+static ALWAYS_INLINE void dfc030_put_long(uaecptr addr, uae_u32 val)
+{
+    uae_u32 fc = regs.dfc;
+#if MMUDEBUG > 2
+	write_log(_T("dfc030_put_long: %08X = %08X FC = %i\n"), addr, val, fc);
+#endif
+    if (unlikely(is_unaligned(addr, 4)))
+		mmu030_put_long_unaligned(addr, val, fc, 0);
+	else
+		mmu030_put_long(addr, val, fc);
+}
+
+static ALWAYS_INLINE void dfc030_put_word(uaecptr addr, uae_u16 val)
+{
+    uae_u32 fc = regs.dfc;
+#if MMUDEBUG > 2
+	write_log(_T("dfc030_put_word: %08X = %04X FC = %i\n"), addr, val, fc);
+#endif
+	if (unlikely(is_unaligned(addr, 2)))
+		mmu030_put_word_unaligned(addr, val, fc, 0);
+	else
+		mmu030_put_word(addr, val, fc);
+}
+
+static ALWAYS_INLINE void dfc030_put_byte(uaecptr addr, uae_u8 val)
+{
+    uae_u32 fc = regs.dfc;
+#if MMUDEBUG > 2
+	write_log(_T("dfc030_put_byte: %08X = %02X FC = %i\n"), addr, val, fc);
+#endif
+	mmu030_put_byte(addr, val, fc);
+}
+
+#define ACCESS_CHECK_PUT \
+	if (!mmu030_ad[mmu030_idx].done) { \
+		mmu030_ad[mmu030_idx].val = v; \
+	} else if (mmu030_ad[mmu030_idx].done) { \
+		mmu030_idx++; \
+		return; \
+	}
+
+#define ACCESS_CHECK_GET \
+	if (mmu030_ad[mmu030_idx].done) { \
+		v = mmu030_ad[mmu030_idx].val; \
+		mmu030_idx++; \
+		return v; \
+	}
+
+#define ACCESS_CHECK_GET_PC(pc) \
+	if (mmu030_ad[mmu030_idx].done) { \
+		v = mmu030_ad[mmu030_idx].val; \
+		mmu030_idx++; \
+		m68k_incpci (pc); \
+		return v; \
+	}
+
+#define ACCESS_EXIT_PUT \
+	mmu030_ad[mmu030_idx].done = true; \
+	mmu030_idx++; \
+	mmu030_ad[mmu030_idx].done = false;
+
+#define ACCESS_EXIT_GET \
+	mmu030_ad[mmu030_idx].val = v; \
+	mmu030_ad[mmu030_idx].done = true; \
+	mmu030_idx++; \
+	mmu030_ad[mmu030_idx].done = false;
+
+STATIC_INLINE void put_byte_mmu030_state (uaecptr addr, uae_u32 v)
+{
+	ACCESS_CHECK_PUT
+    uae_mmu030_put_byte (addr, v);
+	ACCESS_EXIT_PUT
+}
+STATIC_INLINE void put_lrmw_byte_mmu030_state (uaecptr addr, uae_u32 v)
+{
+	ACCESS_CHECK_PUT
+    uae_mmu030_put_lrmw (addr, v, sz_byte);
+	ACCESS_EXIT_PUT
+}
+STATIC_INLINE void put_word_mmu030_state (uaecptr addr, uae_u32 v)
+{
+	ACCESS_CHECK_PUT
+    uae_mmu030_put_word (addr, v);
+	ACCESS_EXIT_PUT
+}
+STATIC_INLINE void put_lrmw_word_mmu030_state (uaecptr addr, uae_u32 v)
+{
+	ACCESS_CHECK_PUT
+    uae_mmu030_put_lrmw (addr, v, sz_word);
+	ACCESS_EXIT_PUT
+}
+STATIC_INLINE void put_long_mmu030_state (uaecptr addr, uae_u32 v)
+{
+	ACCESS_CHECK_PUT
+    uae_mmu030_put_long (addr, v);
+	ACCESS_EXIT_PUT
+}
+STATIC_INLINE void put_lrmw_long_mmu030_state (uaecptr addr, uae_u32 v)
+{
+	ACCESS_CHECK_PUT
+    uae_mmu030_put_lrmw (addr, v, sz_long);
+	ACCESS_EXIT_PUT
+}
+
+STATIC_INLINE uae_u32 get_byte_mmu030_state (uaecptr addr)
+{
+	uae_u32 v;
+	ACCESS_CHECK_GET
+    v = uae_mmu030_get_byte (addr);
+	ACCESS_EXIT_GET
+	return v;
+}
+STATIC_INLINE uae_u32 get_lrmw_byte_mmu030_state (uaecptr addr)
+{
+	uae_u32 v;
+	ACCESS_CHECK_GET
+    v = uae_mmu030_get_lrmw (addr, sz_byte);
+	ACCESS_EXIT_GET
+	return v;
+}
+
+STATIC_INLINE uae_u32 get_word_mmu030_state (uaecptr addr)
+{
+ 	uae_u32 v;
+	ACCESS_CHECK_GET
+	v = uae_mmu030_get_word (addr);
+	ACCESS_EXIT_GET
+	return v;
+}
+STATIC_INLINE uae_u32 get_lrmw_word_mmu030_state (uaecptr addr)
+{
+ 	uae_u32 v;
+	ACCESS_CHECK_GET
+    v = uae_mmu030_get_lrmw (addr, sz_word);
+	ACCESS_EXIT_GET
+	return v;
+}
+STATIC_INLINE uae_u32 get_long_mmu030_state (uaecptr addr)
+{
+ 	uae_u32 v;
+	ACCESS_CHECK_GET
+	v = uae_mmu030_get_long (addr);
+	ACCESS_EXIT_GET
+	return v;
+}
+STATIC_INLINE uae_u32 get_lrmw_long_mmu030_state (uaecptr addr)
+{
+ 	uae_u32 v;
+	ACCESS_CHECK_GET
+    v = uae_mmu030_get_lrmw (addr, sz_long);
+	ACCESS_EXIT_GET
+	return v;
+}
+
+STATIC_INLINE uae_u32 get_ibyte_mmu030_state (int o)
+{
+ 	uae_u32 v;
+    uae_u32 addr = m68k_getpci () + o;
+	ACCESS_CHECK_GET
+    v = uae_mmu030_get_iword (addr);
+	ACCESS_EXIT_GET
+	return v;
+}
+STATIC_INLINE uae_u32 get_iword_mmu030_state (int o)
+{
+ 	uae_u32 v;
+    uae_u32 addr = m68k_getpci () + o;
+	ACCESS_CHECK_GET
+    v = uae_mmu030_get_iword (addr);
+	ACCESS_EXIT_GET
+	return v;
+}
+STATIC_INLINE uae_u32 get_ilong_mmu030_state (int o)
+{
+ 	uae_u32 v;
+    uae_u32 addr = m68k_getpci () + o;
+	ACCESS_CHECK_GET
+    v = uae_mmu030_get_ilong (addr);
+	ACCESS_EXIT_GET
+	return v;
+}
+STATIC_INLINE uae_u32 next_iword_mmu030_state (void)
+{
+ 	uae_u32 v;
+    uae_u32 addr = m68k_getpci ();
+	ACCESS_CHECK_GET_PC(2);
+    v = uae_mmu030_get_iword (addr);
+    m68k_incpci (2);
+	ACCESS_EXIT_GET
+	return v;
+}
+STATIC_INLINE uae_u32 next_ilong_mmu030_state (void)
+{
+ 	uae_u32 v;
+    uae_u32 addr = m68k_getpci ();
+	ACCESS_CHECK_GET_PC(4);
+    v = uae_mmu030_get_ilong (addr);
+    m68k_incpci (4);
+	ACCESS_EXIT_GET
+	return v;
+}
+
+STATIC_INLINE uae_u32 get_byte_mmu030 (uaecptr addr)
+{
+	return uae_mmu030_get_byte (addr);
+}
+STATIC_INLINE uae_u32 get_word_mmu030 (uaecptr addr)
+{
+	return uae_mmu030_get_word (addr);
+}
+STATIC_INLINE uae_u32 get_long_mmu030 (uaecptr addr)
+{
+	return uae_mmu030_get_long (addr);
+}
+STATIC_INLINE void put_byte_mmu030 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu030_put_byte (addr, v);
+}
+
+STATIC_INLINE void put_word_mmu030 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu030_put_word (addr, v);
+}
+STATIC_INLINE void put_long_mmu030 (uaecptr addr, uae_u32 v)
+{
+    uae_mmu030_put_long (addr, v);
+}
+
+STATIC_INLINE uae_u32 get_ibyte_mmu030 (int o)
+{
+    uae_u32 pc = m68k_getpci () + o;
+    return uae_mmu030_get_iword (pc);
+}
+STATIC_INLINE uae_u32 get_iword_mmu030 (int o)
+{
+    uae_u32 pc = m68k_getpci () + o;
+    return uae_mmu030_get_iword (pc);
+}
+STATIC_INLINE uae_u32 get_ilong_mmu030 (int o)
+{
+    uae_u32 pc = m68k_getpci () + o;
+    return uae_mmu030_get_ilong (pc);
+}
+STATIC_INLINE uae_u32 next_iword_mmu030 (void)
+{
+ 	uae_u32 v;
+    uae_u32 pc = m68k_getpci ();
+    v = uae_mmu030_get_iword (pc);
+    m68k_incpci (2);
+	return v;
+}
+STATIC_INLINE uae_u32 next_ilong_mmu030 (void)
+{
+ 	uae_u32 v;
+    uae_u32 pc = m68k_getpci ();
+    v = uae_mmu030_get_ilong (pc);
+    m68k_incpci (4);
+	return v;
+}
+
+extern void m68k_do_rts_mmu030 (void);
+extern void m68k_do_rte_mmu030 (uaecptr a7);
+extern void flush_mmu030 (uaecptr, int);
+extern void m68k_do_bsr_mmu030 (uaecptr oldpc, uae_s32 offset);
+
+#endif
diff --git a/src/cpu/cpustbl.c b/src/cpu/cpustbl.c
new file mode 100644
index 0000000..b905ed5
--- /dev/null
+++ b/src/cpu/cpustbl.c
@@ -0,0 +1,50181 @@
+#include "main.h"
+#include "sysdeps.h"
+#include "hatari-glue.h"
+#include "maccess.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "cputbl.h"
+#define CPUFUNC(x) x##_ff
+#define SET_CFLG_ALWAYS(x) SET_CFLG(x)
+#define SET_NFLG_ALWAYS(x) SET_NFLG(x)
+#ifdef NOFLAGS
+#include "noflags.h"
+#endif
+#ifdef CPUEMU_0
+const struct cputbl CPUFUNC(op_smalltbl_0)[] = {
+{ CPUFUNC(op_0000_0), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_0), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_0), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_0), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_0), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_0), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_0), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_0), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_0), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_0), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_0), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_0), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_0), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_0), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_0), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_0), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_0), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_0), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_0), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_0), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_0), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_0), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_0), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_0), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_0), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_0), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00d0_0), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00e8_0), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f0_0), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f8_0), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f9_0), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00fa_0), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00fb_0), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0100_0), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_0), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_0), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_0), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_0), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_0), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_0), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_0), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_0), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_0), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_0), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_0), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_0), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_0), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_0), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_0), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_0), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_0), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_0), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_0), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_0), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_0), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_0), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_0), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_0), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_0), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_0), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_0), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_0), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_0), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_0), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_0), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_0), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_0), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_0), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_0), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_0), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_0), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_0), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_0), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_0), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_0), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_0), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_0), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_0), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_0), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_0), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_0), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_0), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_0), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_0), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_0), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_0), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_0), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_0), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_0), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_0), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_0), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_0), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_0), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_0), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_0), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_0), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_0), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_0), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02d0_0), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02e8_0), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f0_0), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f8_0), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f9_0), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02fa_0), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02fb_0), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0400_0), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_0), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_0), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_0), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_0), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_0), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_0), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_0), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_0), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_0), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_0), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_0), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_0), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_0), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_0), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_0), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_0), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_0), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_0), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_0), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_0), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_0), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_0), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_0), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04d0_0), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04e8_0), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f0_0), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f8_0), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f9_0), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04fa_0), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04fb_0), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0600_0), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_0), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_0), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_0), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_0), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_0), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_0), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_0), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_0), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_0), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_0), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_0), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_0), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_0), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_0), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_0), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_0), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_0), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_0), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_0), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_0), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_0), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_0), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_0), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06c0_0), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06c8_0), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06d0_0), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06e8_0), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f0_0), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f8_0), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f9_0), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06fa_0), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06fb_0), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+{ CPUFUNC(op_0800_0), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_0), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_0), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_0), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_0), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_0), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_0), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_0), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_0), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_0), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_0), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_0), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_0), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_0), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_0), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_0), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_0), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_0), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_0), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_0), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_0), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_0), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_0), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_0), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_0), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_0), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_0), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_0), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_0), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_0), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_0), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_0), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_0), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_0), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_0), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_0), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_0), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_0), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_0), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_0), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_0), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_0), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_0), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_0), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_0), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_0), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_0), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_0), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_0), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_0), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_0), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_0), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_0), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_0), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_0), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_0), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_0), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_0), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_0), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_0), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ad0_0), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ad8_0), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ae0_0), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ae8_0), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af0_0), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af8_0), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af9_0), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+{ CPUFUNC(op_0c00_0), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_0), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_0), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_0), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_0), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_0), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_0), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_0), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c3a_0), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c3b_0), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ CPUFUNC(op_0c40_0), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_0), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_0), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_0), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_0), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_0), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_0), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_0), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c7a_0), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c7b_0), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ CPUFUNC(op_0c80_0), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_0), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_0), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_0), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_0), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_0), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_0), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_0), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cba_0), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cbb_0), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cd0_0), 0x0cd0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cd8_0), 0x0cd8, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ce0_0), 0x0ce0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ce8_0), 0x0ce8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf0_0), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf8_0), 0x0cf8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf9_0), 0x0cf9, 16, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cfc_0), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e10_0), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e18_0), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e20_0), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e28_0), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e30_0), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e38_0), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e39_0), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e50_0), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e58_0), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e60_0), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e68_0), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e70_0), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e78_0), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e79_0), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e90_0), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e98_0), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ea0_0), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ea8_0), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb0_0), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb8_0), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb9_0), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ed0_0), 0x0ed0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ed8_0), 0x0ed8, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ee0_0), 0x0ee0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ee8_0), 0x0ee8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef0_0), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef8_0), 0x0ef8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef9_0), 0x0ef9, 16, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0efc_0), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+{ CPUFUNC(op_1000_0), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_0), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_0), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_0), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_0), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_0), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_0), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_0), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_0), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_0), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_0), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_0), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_0), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_0), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_0), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_0), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_0), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_0), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_0), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_0), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_0), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_0), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_0), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_0), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_0), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_0), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_0), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_0), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_0), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_0), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_0), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_0), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_0), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_0), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_0), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_0), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_0), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_0), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_0), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_0), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_0), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_0), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_0), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_0), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_0), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_0), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_0), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_0), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_0), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_0), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_0), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_0), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_0), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_0), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_0), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_0), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_0), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_0), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_0), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_0), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_0), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_0), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_0), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_0), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_0), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_0), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_0), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_0), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_0), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_0), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_0), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_0), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_0), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_0), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_0), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_0), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_0), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_0), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_0), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_0), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_0), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_0), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_0), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_0), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_0), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_0), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_0), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_0), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_0), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_0), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_0), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_0), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_0), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_0), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_0), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_0), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_0), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_0), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_0), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_0), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_0), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_0), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_0), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_0), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_0), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_0), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_0), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_0), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_0), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_0), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_0), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_0), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_0), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_0), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_0), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_0), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_0), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_0), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_0), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_0), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_0), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_0), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_0), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_0), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_0), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_0), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_0), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_0), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_0), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_0), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_0), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_0), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_0), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_0), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_0), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_0), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_0), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_0), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_0), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_0), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_0), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_0), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_0), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_0), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_0), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_0), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_0), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_0), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_0), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_0), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_0), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_0), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_0), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_0), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_0), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_0), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_0), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_0), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_0), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_0), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_0), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_0), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_0), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_0), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_0), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_0), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_0), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_0), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_0), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_0), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_0), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_0), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_0), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_0), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_0), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_0), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_0), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_0), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_0), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_0), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_0), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_0), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_0), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_0), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_0), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_0), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_0), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_0), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_0), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_0), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_0), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_0), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_0), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_0), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_0), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_0), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_0), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_0), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_0), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_0), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_0), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_0), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_0), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_0), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_0), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_0), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_0), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_0), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_0), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_0), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_0), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_0), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_0), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_0), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_0), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_0), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_0), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_0), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_0), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_0), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_0), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_0), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_0), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_0), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_0), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_0), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_0), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_0), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_0), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_0), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_0), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_0), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_0), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_0), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_0), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_0), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_0), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_0), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_0), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_0), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_0), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_0), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_0), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_0), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_0), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_0), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_0), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_0), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_0), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_0), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_0), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_0), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_0), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_0), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_0), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_0), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_0), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_0), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_0), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_0), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_0), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_0), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_0), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_0), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_0), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_0), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_0), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_0), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_0), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_0), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_0), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_0), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_0), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_0), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_0), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_0), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_0), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_0), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_0), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_0), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_0), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_0), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_0), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_0), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_0), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_0), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_0), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_0), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_0), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_0), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_0), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_0), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_0), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_0), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_0), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_0), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_0), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_0), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_0), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_0), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_0), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_0), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_0), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_0), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_0), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_0), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_0), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_0), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_0), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_0), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_0), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_0), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_0), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_0), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_0), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_0), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_0), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_0), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_0), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_0), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_0), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_0), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_0), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_0), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_0), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_0), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_0), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_0), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_0), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_0), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_0), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_0), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_0), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_0), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_0), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_0), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4100_0), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4110_0), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4118_0), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4120_0), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4128_0), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4130_0), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4138_0), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4139_0), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413a_0), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413b_0), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413c_0), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+{ CPUFUNC(op_4180_0), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_0), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_0), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_0), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_0), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_0), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_0), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_0), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_0), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_0), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_0), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_0), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_0), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_0), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_0), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_0), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_0), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_0), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_0), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_0), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_0), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_0), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_0), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_0), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_0), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_0), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_0), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_0), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_0), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_0), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_0), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_0), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_0), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_0), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_0), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_0), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_0), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_0), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_0), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_0), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_0), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_0), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42c0_0), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d0_0), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d8_0), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e0_0), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e8_0), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f0_0), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f8_0), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f9_0), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+{ CPUFUNC(op_4400_0), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_0), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_0), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_0), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_0), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_0), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_0), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_0), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_0), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_0), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_0), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_0), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_0), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_0), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_0), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_0), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_0), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_0), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_0), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_0), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_0), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_0), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_0), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_0), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_0), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_0), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_0), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_0), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_0), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_0), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_0), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_0), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_0), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_0), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_0), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_0), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_0), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_0), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_0), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_0), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_0), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_0), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_0), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_0), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_0), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_0), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_0), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_0), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_0), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_0), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_0), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_0), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_0), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_0), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_0), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_0), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_0), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_0), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_0), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_0), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_0), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_0), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_0), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_0), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_0), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_0), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_0), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_0), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_0), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_0), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_0), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4808_0), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#endif
+{ CPUFUNC(op_4810_0), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_0), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_0), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_0), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_0), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_0), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_0), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_0), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4848_0), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+#endif
+{ CPUFUNC(op_4850_0), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_0), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_0), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_0), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_0), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_0), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_0), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_0), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_0), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_0), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_0), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_0), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_0), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_0), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_0), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_0), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_0), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_0), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_0), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_0), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_0), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_49c0_0), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+#endif
+{ CPUFUNC(op_4a00_0), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_0), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_0), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_0), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_0), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_0), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_0), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_0), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3a_0), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3b_0), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3c_0), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a40_0), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a48_0), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a50_0), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_0), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_0), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_0), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_0), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_0), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_0), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7a_0), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7b_0), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7c_0), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a80_0), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a88_0), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a90_0), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_0), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_0), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_0), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_0), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_0), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_0), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4aba_0), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4abb_0), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4abc_0), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4ac0_0), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_0), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_0), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_0), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_0), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_0), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_0), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_0), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c00_0), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c10_0), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c18_0), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c20_0), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c28_0), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c30_0), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c38_0), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c39_0), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3a_0), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3b_0), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3c_0), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c40_0), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c50_0), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c58_0), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c60_0), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c68_0), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c70_0), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c78_0), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c79_0), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7a_0), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7b_0), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7c_0), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+{ CPUFUNC(op_4c90_0), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_0), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_0), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_0), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_0), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_0), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_0), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_0), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_0), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_0), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_0), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_0), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_0), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_0), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_0), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_0), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_0), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_0), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_0), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_0), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_0), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_0), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_0), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_0), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_0), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e74_0), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+#endif
+{ CPUFUNC(op_4e75_0), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_0), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_0), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7a_0), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7b_0), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+#endif
+{ CPUFUNC(op_4e90_0), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_0), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_0), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_0), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_0), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_0), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_0), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_0), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_0), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_0), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_0), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_0), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_0), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_0), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_0), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_0), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_0), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_0), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_0), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_0), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_0), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_0), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_0), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_0), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_0), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_0), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_0), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_0), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_0), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_0), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_0), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_0), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_0), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_0), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_0), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_0), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_0), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_0), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_0), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_0), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_0), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_0), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_0), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_0), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_0), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_0), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_0), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_0), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_0), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fa_0), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fb_0), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fc_0), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5100_0), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_0), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_0), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_0), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_0), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_0), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_0), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_0), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_0), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_0), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_0), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_0), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_0), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_0), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_0), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_0), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_0), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_0), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_0), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_0), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_0), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_0), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_0), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_0), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_0), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_0), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_0), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_0), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_0), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_0), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_0), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_0), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_0), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_0), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_0), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fa_0), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fb_0), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fc_0), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_52c0_0), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_0), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_0), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_0), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_0), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_0), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_0), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_0), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_0), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fa_0), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fb_0), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fc_0), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_53c0_0), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_0), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_0), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_0), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_0), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_0), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_0), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_0), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_0), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fa_0), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fb_0), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fc_0), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_54c0_0), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_0), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_0), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_0), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_0), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_0), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_0), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_0), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_0), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fa_0), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fb_0), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fc_0), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_55c0_0), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_0), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_0), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_0), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_0), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_0), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_0), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_0), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_0), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fa_0), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fb_0), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fc_0), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_56c0_0), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_0), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_0), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_0), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_0), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_0), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_0), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_0), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_0), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fa_0), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fb_0), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fc_0), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_57c0_0), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_0), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_0), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_0), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_0), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_0), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_0), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_0), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_0), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fa_0), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fb_0), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fc_0), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_58c0_0), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_0), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_0), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_0), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_0), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_0), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_0), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_0), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_0), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fa_0), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fb_0), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fc_0), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_59c0_0), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_0), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_0), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_0), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_0), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_0), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_0), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_0), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_0), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fa_0), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fb_0), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fc_0), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5ac0_0), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_0), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_0), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_0), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_0), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_0), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_0), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_0), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_0), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afa_0), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afb_0), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afc_0), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5bc0_0), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_0), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_0), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_0), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_0), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_0), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_0), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_0), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_0), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfa_0), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfb_0), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfc_0), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5cc0_0), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_0), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_0), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_0), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_0), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_0), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_0), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_0), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_0), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfa_0), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfb_0), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfc_0), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5dc0_0), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_0), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_0), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_0), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_0), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_0), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_0), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_0), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_0), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfa_0), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfb_0), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfc_0), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5ec0_0), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_0), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_0), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_0), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_0), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_0), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_0), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_0), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_0), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efa_0), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efb_0), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efc_0), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5fc0_0), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_0), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_0), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_0), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_0), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_0), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_0), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_0), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_0), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffa_0), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffb_0), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffc_0), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_6000_0), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_0), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_0), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6100_0), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_0), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_0), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_0), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_0), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_0), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6300_0), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_0), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_0), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6400_0), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_0), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_0), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6500_0), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_0), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_0), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6600_0), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_0), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_0), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6700_0), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_0), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_0), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6800_0), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_0), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_0), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6900_0), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_0), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_0), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a00_0), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_0), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_0), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b00_0), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_0), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_0), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c00_0), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_0), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_0), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d00_0), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_0), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_0), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e00_0), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_0), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_0), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f00_0), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_0), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_0), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_7000_0), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_0), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_0), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_0), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_0), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_0), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_0), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_0), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_0), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_0), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_0), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_0), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_0), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_0), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_0), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_0), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_0), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_0), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_0), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_0), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_0), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_0), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_0), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_0), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_0), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_0), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_0), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_0), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_0), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_0), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_0), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_0), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_0), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_0), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_0), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_0), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_0), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_0), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_0), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_0), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_0), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_0), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_0), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_0), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_0), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_0), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_0), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_0), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_0), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_0), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_0), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_0), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_0), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_0), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8140_0), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8148_0), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+{ CPUFUNC(op_8150_0), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_0), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_0), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_0), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_0), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_0), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_0), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8180_0), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8188_0), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+{ CPUFUNC(op_8190_0), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_0), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_0), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_0), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_0), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_0), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_0), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_0), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_0), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_0), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_0), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_0), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_0), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_0), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_0), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_0), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_0), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_0), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_0), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_0), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_0), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_0), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_0), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_0), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_0), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_0), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_0), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_0), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_0), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_0), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_0), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_0), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_0), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_0), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_0), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_0), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_0), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_0), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_0), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_0), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_0), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_0), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_0), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_0), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_0), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_0), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_0), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_0), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_0), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_0), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_0), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_0), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_0), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_0), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_0), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_0), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_0), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_0), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_0), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_0), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_0), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_0), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_0), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_0), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_0), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_0), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_0), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_0), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_0), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_0), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_0), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_0), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_0), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_0), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_0), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_0), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_0), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_0), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_0), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_0), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_0), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_0), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_0), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_0), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_0), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_0), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_0), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_0), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_0), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_0), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_0), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_0), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_0), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_0), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_0), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_0), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_0), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_0), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_0), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_0), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_0), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_0), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_0), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_0), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_0), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_0), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_0), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_0), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_0), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_0), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_0), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_0), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_0), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_0), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_0), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_0), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_0), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_0), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_0), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_0), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_0), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_0), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_0), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_0), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_0), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_0), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_0), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_0), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_0), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_0), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_0), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_0), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_0), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_0), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_0), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_0), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_0), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_0), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_0), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_0), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_0), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_0), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_0), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_0), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_0), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_0), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_0), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_0), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_0), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_0), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_0), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_0), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_0), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_0), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_0), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_0), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_0), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_0), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_0), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_0), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_0), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_0), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_0), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_0), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_0), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_0), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_0), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_0), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_0), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_0), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_0), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_0), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_0), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_0), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_0), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_0), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_0), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_0), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_0), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_0), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_0), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_0), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_0), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_0), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_0), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_0), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_0), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_0), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_0), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_0), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_0), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_0), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_0), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_0), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_0), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_0), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_0), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_0), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_0), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_0), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_0), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_0), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_0), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_0), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_0), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_0), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_0), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_0), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_0), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_0), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_0), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_0), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_0), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_0), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_0), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_0), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_0), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_0), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_0), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_0), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_0), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_0), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_0), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_0), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_0), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_0), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_0), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_0), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_0), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_0), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_0), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_0), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_0), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_0), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_0), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_0), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_0), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_0), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_0), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_0), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_0), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_0), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_0), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_0), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_0), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_0), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_0), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_0), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_0), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_0), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_0), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_0), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_0), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_0), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_0), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_0), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_0), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_0), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_0), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_0), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_0), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_0), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_0), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_0), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_0), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_0), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_0), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_0), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_0), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_0), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_0), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_0), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_0), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_0), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_0), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_0), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_0), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_0), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_0), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_0), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_0), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_0), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_0), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_0), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_0), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_0), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_0), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_0), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_0), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_0), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_0), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_0), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_0), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_0), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_0), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_0), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_0), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_0), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_0), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_0), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_0), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_0), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_0), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_0), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_0), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_0), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_0), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_0), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_0), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_0), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_0), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_0), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_0), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_0), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_0), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_0), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_0), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_0), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_0), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_0), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_0), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_0), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_0), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_0), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_0), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_0), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_0), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_0), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_0), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_0), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_0), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_0), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_0), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_0), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_0), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_0), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_0), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_0), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_0), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_0), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_0), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_0), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_0), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_0), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_0), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_0), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_0), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_0), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_0), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_0), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_0), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_0), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_0), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_0), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_0), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_0), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_0), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_0), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_0), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_0), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_0), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_0), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_0), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_0), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_0), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_0), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_0), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_0), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_0), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_0), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_0), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_0), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_0), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_0), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_0), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_0), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_0), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_0), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_0), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_0), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_0), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_0), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_0), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_0), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_0), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_0), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_0), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_0), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_0), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_0), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_0), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_0), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_0), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_0), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_0), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_0), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_0), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_0), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_0), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_0), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_0), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_0), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_0), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_0), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_0), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_0), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_0), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_0), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_0), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_0), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_0), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_0), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_0), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_0), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_0), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_0), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_0), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_0), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_0), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_0), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_0), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_0), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_0), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_0), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_0), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_0), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_0), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_0), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_0), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_0), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_0), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_0), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_0), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_0), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_0), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_0), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_0), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_0), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_0), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_0), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_0), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_0), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_0), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_0), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_0), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_0), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_0), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_0), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_0), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_0), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_0), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_0), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_0), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_0), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_0), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_0), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_0), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_0), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_0), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_0), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_0), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8c0_0), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8d0_0), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8e8_0), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f0_0), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f8_0), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f9_0), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8fa_0), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8fb_0), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9c0_0), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9d0_0), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9e8_0), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f0_0), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f8_0), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f9_0), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9fa_0), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9fb_0), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eac0_0), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ead0_0), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eae8_0), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf0_0), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf8_0), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf9_0), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebc0_0), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebd0_0), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebe8_0), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf0_0), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf8_0), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf9_0), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebfa_0), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebfb_0), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecc0_0), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecd0_0), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ece8_0), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf0_0), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf8_0), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf9_0), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edc0_0), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edd0_0), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ede8_0), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf0_0), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf8_0), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf9_0), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edfa_0), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edfb_0), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eec0_0), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eed0_0), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eee8_0), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef0_0), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef8_0), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef9_0), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efc0_0), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efd0_0), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efe8_0), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff0_0), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff8_0), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff9_0), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f000_0), 0xf000, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f008_0), 0xf008, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f010_0), 0xf010, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f018_0), 0xf018, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f020_0), 0xf020, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f028_0), 0xf028, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f030_0), 0xf030, -1, { -3, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f038_0), 0xf038, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f039_0), 0xf039, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f200_0), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f208_0), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f210_0), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f218_0), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f220_0), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f228_0), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f230_0), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f238_0), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f239_0), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23a_0), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23b_0), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23c_0), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f240_0), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f248_0), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f250_0), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f258_0), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f260_0), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f268_0), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f270_0), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f278_0), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f279_0), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27a_0), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27b_0), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27c_0), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f280_0), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f2c0_0), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f310_0), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f320_0), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f328_0), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f330_0), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f338_0), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f339_0), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f350_0), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f358_0), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f368_0), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f370_0), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f378_0), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f379_0), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f37a_0), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f37b_0), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f408_0), 0xf408, -1, { 0, 0 }, 0 }, /* CINVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f410_0), 0xf410, -1, { 0, 0 }, 0 }, /* CINVP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f418_0), 0xf418, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f419_0), 0xf419, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41a_0), 0xf41a, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41b_0), 0xf41b, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41c_0), 0xf41c, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41d_0), 0xf41d, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41e_0), 0xf41e, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41f_0), 0xf41f, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f428_0), 0xf428, -1, { 0, 0 }, 0 }, /* CPUSHL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f430_0), 0xf430, -1, { 0, 0 }, 0 }, /* CPUSHP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f438_0), 0xf438, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f439_0), 0xf439, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43a_0), 0xf43a, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43b_0), 0xf43b, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43c_0), 0xf43c, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43d_0), 0xf43d, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43e_0), 0xf43e, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43f_0), 0xf43f, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f500_0), 0xf500, -1, { 0, 0 }, 0 }, /* PFLUSHN */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f508_0), 0xf508, -1, { 0, 0 }, 0 }, /* PFLUSH */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f510_0), 0xf510, -1, { 0, 0 }, 0 }, /* PFLUSHAN */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f518_0), 0xf518, -1, { 0, 0 }, 0 }, /* PFLUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f548_0), 0xf548, -1, { 0, 0 }, 0 }, /* PTESTW */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f568_0), 0xf568, -1, { 0, 0 }, 0 }, /* PTESTR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f588_0), 0xf588, -1, { 0, 0 }, 0 }, /* PLPAW */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f5c8_0), 0xf5c8, -1, { 0, 0 }, 0 }, /* PLPAR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f600_0), 0xf600, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f608_0), 0xf608, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f610_0), 0xf610, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f618_0), 0xf618, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f620_0), 0xf620, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f800_0), 0xf800, -1, { 0, 0 }, 0 }, /* LPSTOP */
+#endif
+{ 0, 0 }};
+#endif /* CPUEMU_0 */
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_1)[] = {
+{ CPUFUNC(op_0000_0), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_0), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_0), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_0), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_0), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_0), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_0), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_0), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_0), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_0), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_0), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_0), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_0), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_0), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_0), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_0), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_0), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_0), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_0), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_0), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_0), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_0), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_0), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_0), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_0), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_0), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00d0_0), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00e8_0), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f0_0), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f8_0), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f9_0), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00fa_0), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00fb_0), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0100_0), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_0), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_0), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_0), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_0), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_0), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_0), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_0), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_0), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_0), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_0), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_0), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_0), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_0), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_0), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_0), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_0), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_0), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_0), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_0), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_0), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_0), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_0), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_0), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_0), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_0), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_0), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_0), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_0), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_0), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_0), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_0), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_0), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_0), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_0), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_0), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_0), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_0), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_0), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_0), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_0), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_0), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_0), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_0), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_0), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_0), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_0), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_0), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_0), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_0), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_0), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_0), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_0), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_0), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_0), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_0), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_0), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_0), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_0), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_0), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_0), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_0), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_0), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_0), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_0), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02d0_0), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02e8_0), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f0_0), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f8_0), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f9_0), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02fa_0), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02fb_0), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0400_0), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_0), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_0), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_0), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_0), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_0), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_0), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_0), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_0), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_0), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_0), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_0), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_0), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_0), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_0), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_0), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_0), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_0), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_0), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_0), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_0), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_0), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_0), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_0), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04d0_0), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04e8_0), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f0_0), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f8_0), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f9_0), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04fa_0), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04fb_0), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0600_0), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_0), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_0), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_0), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_0), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_0), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_0), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_0), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_0), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_0), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_0), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_0), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_0), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_0), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_0), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_0), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_0), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_0), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_0), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_0), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_0), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_0), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_0), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_0), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06c0_0), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+{ CPUFUNC(op_06c8_0), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+{ CPUFUNC(op_06d0_0), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06e8_0), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f0_0), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f8_0), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f9_0), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06fa_0), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06fb_0), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_0800_0), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_0), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_0), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_0), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_0), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_0), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_0), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_0), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_0), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_0), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_0), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_0), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_0), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_0), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_0), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_0), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_0), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_0), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_0), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_0), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_0), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_0), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_0), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_0), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_0), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_0), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_0), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_0), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_0), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_0), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_0), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_0), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_0), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_0), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_0), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_0), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_0), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_0), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_0), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_0), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_0), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_0), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_0), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_0), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_0), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_0), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_0), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_0), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_0), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_0), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_0), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_0), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_0), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_0), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_0), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_0), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_0), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_0), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_0), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_0), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ad0_0), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ad8_0), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ae0_0), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ae8_0), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af0_0), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af8_0), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af9_0), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0c00_0), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_0), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_0), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_0), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_0), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_0), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_0), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_0), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c3a_0), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c3b_0), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c40_0), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_0), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_0), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_0), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_0), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_0), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_0), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_0), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c7a_0), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c7b_0), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c80_0), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_0), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_0), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_0), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_0), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_0), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_0), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_0), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cba_0), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cbb_0), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cd0_0), 0x0cd0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cd8_0), 0x0cd8, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ce0_0), 0x0ce0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ce8_0), 0x0ce8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf0_0), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf8_0), 0x0cf8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf9_0), 0x0cf9, 16, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cfc_0), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+{ CPUFUNC(op_0e10_0), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e18_0), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e20_0), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e28_0), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e30_0), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e38_0), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e39_0), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e50_0), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e58_0), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e60_0), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e68_0), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e70_0), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e78_0), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e79_0), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e90_0), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e98_0), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ea0_0), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ea8_0), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb0_0), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb8_0), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb9_0), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ed0_0), 0x0ed0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ed8_0), 0x0ed8, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ee0_0), 0x0ee0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ee8_0), 0x0ee8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef0_0), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef8_0), 0x0ef8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef9_0), 0x0ef9, 16, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0efc_0), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+{ CPUFUNC(op_1000_0), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_0), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_0), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_0), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_0), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_0), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_0), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_0), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_0), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_0), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_0), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_0), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_0), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_0), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_0), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_0), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_0), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_0), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_0), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_0), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_0), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_0), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_0), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_0), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_0), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_0), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_0), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_0), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_0), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_0), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_0), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_0), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_0), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_0), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_0), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_0), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_0), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_0), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_0), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_0), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_0), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_0), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_0), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_0), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_0), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_0), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_0), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_0), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_0), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_0), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_0), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_0), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_0), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_0), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_0), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_0), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_0), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_0), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_0), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_0), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_0), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_0), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_0), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_0), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_0), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_0), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_0), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_0), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_0), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_0), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_0), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_0), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_0), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_0), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_0), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_0), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_0), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_0), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_0), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_0), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_0), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_0), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_0), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_0), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_0), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_0), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_0), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_0), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_0), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_0), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_0), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_0), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_0), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_0), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_0), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_0), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_0), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_0), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_0), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_0), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_0), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_0), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_0), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_0), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_0), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_0), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_0), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_0), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_0), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_0), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_0), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_0), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_0), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_0), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_0), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_0), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_0), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_0), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_0), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_0), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_0), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_0), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_0), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_0), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_0), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_0), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_0), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_0), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_0), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_0), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_0), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_0), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_0), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_0), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_0), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_0), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_0), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_0), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_0), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_0), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_0), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_0), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_0), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_0), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_0), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_0), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_0), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_0), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_0), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_0), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_0), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_0), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_0), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_0), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_0), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_0), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_0), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_0), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_0), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_0), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_0), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_0), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_0), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_0), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_0), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_0), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_0), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_0), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_0), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_0), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_0), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_0), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_0), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_0), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_0), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_0), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_0), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_0), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_0), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_0), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_0), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_0), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_0), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_0), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_0), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_0), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_0), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_0), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_0), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_0), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_0), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_0), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_0), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_0), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_0), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_0), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_0), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_0), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_0), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_0), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_0), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_0), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_0), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_0), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_0), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_0), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_0), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_0), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_0), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_0), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_0), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_0), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_0), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_0), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_0), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_0), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_0), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_0), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_0), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_0), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_0), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_0), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_0), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_0), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_0), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_0), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_0), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_0), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_0), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_0), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_0), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_0), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_0), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_0), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_0), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_0), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_0), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_0), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_0), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_0), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_0), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_0), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_0), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_0), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_0), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_0), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_0), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_0), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_0), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_0), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_0), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_0), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_0), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_0), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_0), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_0), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_0), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_0), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_0), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_0), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_0), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_0), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_0), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_0), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_0), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_0), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_0), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_0), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_0), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_0), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_0), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_0), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_0), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_0), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_0), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_0), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_0), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_0), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_0), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_0), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_0), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_0), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_0), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_0), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_0), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_0), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_0), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_0), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_0), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_0), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_0), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_0), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_0), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_0), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_0), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_0), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_0), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_0), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_0), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_0), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_0), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_0), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_0), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_0), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_0), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_0), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_0), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_0), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_0), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_0), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_0), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_0), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_0), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_0), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_0), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_0), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_0), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_0), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_0), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_0), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_0), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_0), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_0), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_0), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_0), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_0), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_0), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_0), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_0), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_0), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_0), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_0), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_0), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_0), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_0), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_0), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4100_0), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4110_0), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4118_0), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4120_0), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4128_0), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4130_0), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4138_0), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4139_0), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413a_0), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413b_0), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413c_0), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4180_0), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_0), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_0), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_0), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_0), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_0), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_0), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_0), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_0), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_0), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_0), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_0), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_0), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_0), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_0), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_0), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_0), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_0), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_0), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_0), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_0), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_0), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_0), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_0), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_0), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_0), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_0), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_0), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_0), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_0), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_0), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_0), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_0), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_0), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_0), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_0), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_0), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_0), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_0), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_0), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_0), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_0), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42c0_0), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d0_0), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d8_0), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e0_0), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e8_0), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f0_0), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f8_0), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f9_0), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4400_0), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_0), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_0), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_0), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_0), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_0), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_0), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_0), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_0), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_0), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_0), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_0), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_0), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_0), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_0), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_0), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_0), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_0), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_0), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_0), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_0), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_0), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_0), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_0), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_0), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_0), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_0), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_0), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_0), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_0), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_0), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_0), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_0), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_0), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_0), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_0), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_0), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_0), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_0), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_0), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_0), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_0), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_0), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_0), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_0), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_0), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_0), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_0), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_0), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_0), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_0), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_0), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_0), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_0), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_0), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_0), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_0), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_0), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_0), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_0), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_0), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_0), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_0), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_0), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_0), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_0), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_0), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_0), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_0), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_0), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_0), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4808_0), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4810_0), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_0), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_0), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_0), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_0), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_0), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_0), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_0), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ CPUFUNC(op_4848_0), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+{ CPUFUNC(op_4850_0), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_0), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_0), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_0), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_0), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_0), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_0), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_0), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_0), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_0), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_0), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_0), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_0), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_0), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_0), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_0), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_0), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_0), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_0), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_0), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_0), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_49c0_0), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4a00_0), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_0), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_0), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_0), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_0), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_0), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_0), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_0), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3a_0), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3b_0), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3c_0), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a40_0), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a48_0), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a50_0), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_0), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_0), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_0), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_0), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_0), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_0), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7a_0), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7b_0), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7c_0), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a80_0), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a88_0), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a90_0), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_0), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_0), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_0), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_0), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_0), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_0), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aba_0), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4abb_0), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4abc_0), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ac0_0), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_0), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_0), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_0), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_0), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_0), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_0), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_0), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4c00_0), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c10_0), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c18_0), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c20_0), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c28_0), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c30_0), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c38_0), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c39_0), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3a_0), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3b_0), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3c_0), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c40_0), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c50_0), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c58_0), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c60_0), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c68_0), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c70_0), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c78_0), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c79_0), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7a_0), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7b_0), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7c_0), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c90_0), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_0), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_0), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_0), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_0), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_0), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_0), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_0), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_0), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_0), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_0), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_0), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_0), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_0), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_0), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_0), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_0), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_0), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_0), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_0), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_0), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_0), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_0), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_0), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_0), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+{ CPUFUNC(op_4e74_0), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+{ CPUFUNC(op_4e75_0), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_0), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_0), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+{ CPUFUNC(op_4e7a_0), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+{ CPUFUNC(op_4e7b_0), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+{ CPUFUNC(op_4e90_0), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_0), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_0), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_0), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_0), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_0), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_0), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_0), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_0), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_0), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_0), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_0), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_0), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_0), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_0), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_0), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_0), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_0), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_0), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_0), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_0), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_0), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_0), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_0), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_0), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_0), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_0), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_0), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_0), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_0), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_0), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_0), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_0), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_0), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_0), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_0), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_0), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_0), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_0), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_0), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_0), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_0), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_0), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_0), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_0), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_0), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_0), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_0), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_0), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50fa_0), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_50fb_0), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_50fc_0), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5100_0), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_0), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_0), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_0), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_0), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_0), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_0), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_0), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_0), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_0), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_0), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_0), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_0), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_0), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_0), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_0), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_0), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_0), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_0), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_0), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_0), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_0), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_0), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_0), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_0), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_0), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_0), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_0), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_0), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_0), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_0), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_0), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_0), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_0), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_0), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51fa_0), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_51fb_0), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_51fc_0), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52c0_0), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_0), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_0), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_0), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_0), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_0), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_0), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_0), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_0), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52fa_0), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52fb_0), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52fc_0), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53c0_0), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_0), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_0), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_0), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_0), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_0), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_0), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_0), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_0), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53fa_0), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53fb_0), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53fc_0), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54c0_0), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_0), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_0), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_0), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_0), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_0), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_0), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_0), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_0), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54fa_0), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54fb_0), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54fc_0), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55c0_0), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_0), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_0), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_0), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_0), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_0), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_0), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_0), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_0), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55fa_0), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55fb_0), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55fc_0), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56c0_0), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_0), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_0), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_0), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_0), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_0), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_0), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_0), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_0), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56fa_0), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56fb_0), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56fc_0), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57c0_0), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_0), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_0), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_0), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_0), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_0), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_0), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_0), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_0), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57fa_0), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57fb_0), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57fc_0), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58c0_0), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_0), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_0), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_0), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_0), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_0), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_0), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_0), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_0), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58fa_0), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58fb_0), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58fc_0), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59c0_0), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_0), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_0), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_0), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_0), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_0), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_0), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_0), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_0), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59fa_0), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59fb_0), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59fc_0), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ac0_0), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_0), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_0), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_0), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_0), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_0), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_0), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_0), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_0), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5afa_0), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5afb_0), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5afc_0), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bc0_0), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_0), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_0), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_0), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_0), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_0), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_0), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_0), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_0), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bfa_0), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bfb_0), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bfc_0), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cc0_0), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_0), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_0), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_0), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_0), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_0), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_0), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_0), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_0), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cfa_0), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cfb_0), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cfc_0), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dc0_0), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_0), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_0), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_0), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_0), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_0), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_0), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_0), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_0), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dfa_0), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dfb_0), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dfc_0), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ec0_0), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_0), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_0), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_0), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_0), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_0), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_0), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_0), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_0), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5efa_0), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5efb_0), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5efc_0), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5fc0_0), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_0), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_0), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_0), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_0), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_0), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_0), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_0), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_0), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ffa_0), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ffb_0), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ffc_0), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_6000_0), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_0), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_0), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6100_0), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_0), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_0), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_0), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_0), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_0), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6300_0), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_0), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_0), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6400_0), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_0), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_0), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6500_0), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_0), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_0), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6600_0), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_0), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_0), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6700_0), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_0), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_0), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6800_0), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_0), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_0), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6900_0), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_0), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_0), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a00_0), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_0), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_0), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b00_0), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_0), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_0), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c00_0), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_0), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_0), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d00_0), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_0), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_0), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e00_0), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_0), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_0), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f00_0), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_0), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_0), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_7000_0), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_0), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_0), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_0), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_0), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_0), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_0), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_0), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_0), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_0), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_0), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_0), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_0), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_0), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_0), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_0), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_0), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_0), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_0), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_0), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_0), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_0), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_0), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_0), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_0), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_0), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_0), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_0), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_0), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_0), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_0), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_0), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_0), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_0), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_0), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_0), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_0), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_0), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_0), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_0), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_0), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_0), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_0), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_0), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_0), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_0), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_0), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_0), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_0), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_0), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_0), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_0), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_0), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_0), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8140_0), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+{ CPUFUNC(op_8148_0), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+{ CPUFUNC(op_8150_0), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_0), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_0), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_0), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_0), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_0), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_0), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8180_0), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+{ CPUFUNC(op_8188_0), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+{ CPUFUNC(op_8190_0), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_0), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_0), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_0), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_0), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_0), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_0), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_0), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_0), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_0), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_0), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_0), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_0), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_0), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_0), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_0), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_0), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_0), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_0), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_0), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_0), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_0), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_0), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_0), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_0), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_0), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_0), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_0), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_0), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_0), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_0), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_0), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_0), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_0), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_0), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_0), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_0), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_0), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_0), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_0), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_0), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_0), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_0), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_0), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_0), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_0), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_0), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_0), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_0), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_0), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_0), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_0), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_0), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_0), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_0), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_0), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_0), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_0), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_0), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_0), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_0), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_0), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_0), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_0), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_0), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_0), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_0), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_0), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_0), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_0), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_0), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_0), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_0), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_0), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_0), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_0), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_0), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_0), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_0), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_0), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_0), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_0), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_0), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_0), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_0), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_0), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_0), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_0), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_0), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_0), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_0), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_0), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_0), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_0), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_0), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_0), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_0), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_0), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_0), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_0), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_0), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_0), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_0), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_0), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_0), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_0), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_0), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_0), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_0), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_0), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_0), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_0), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_0), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_0), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_0), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_0), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_0), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_0), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_0), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_0), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_0), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_0), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_0), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_0), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_0), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_0), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_0), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_0), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_0), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_0), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_0), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_0), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_0), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_0), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_0), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_0), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_0), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_0), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_0), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_0), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_0), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_0), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_0), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_0), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_0), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_0), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_0), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_0), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_0), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_0), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_0), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_0), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_0), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_0), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_0), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_0), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_0), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_0), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_0), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_0), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_0), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_0), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_0), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_0), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_0), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_0), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_0), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_0), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_0), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_0), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_0), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_0), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_0), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_0), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_0), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_0), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_0), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_0), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_0), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_0), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_0), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_0), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_0), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_0), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_0), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_0), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_0), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_0), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_0), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_0), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_0), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_0), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_0), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_0), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_0), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_0), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_0), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_0), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_0), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_0), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_0), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_0), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_0), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_0), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_0), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_0), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_0), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_0), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_0), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_0), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_0), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_0), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_0), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_0), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_0), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_0), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_0), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_0), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_0), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_0), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_0), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_0), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_0), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_0), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_0), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_0), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_0), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_0), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_0), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_0), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_0), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_0), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_0), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_0), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_0), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_0), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_0), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_0), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_0), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_0), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_0), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_0), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_0), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_0), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_0), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_0), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_0), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_0), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_0), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_0), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_0), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_0), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_0), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_0), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_0), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_0), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_0), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_0), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_0), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_0), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_0), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_0), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_0), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_0), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_0), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_0), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_0), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_0), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_0), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_0), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_0), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_0), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_0), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_0), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_0), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_0), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_0), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_0), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_0), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_0), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_0), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_0), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_0), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_0), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_0), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_0), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_0), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_0), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_0), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_0), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_0), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_0), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_0), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_0), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_0), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_0), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_0), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_0), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_0), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_0), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_0), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_0), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_0), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_0), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_0), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_0), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_0), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_0), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_0), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_0), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_0), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_0), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_0), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_0), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_0), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_0), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_0), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_0), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_0), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_0), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_0), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_0), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_0), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_0), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_0), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_0), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_0), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_0), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_0), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_0), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_0), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_0), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_0), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_0), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_0), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_0), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_0), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_0), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_0), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_0), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_0), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_0), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_0), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_0), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_0), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_0), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_0), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_0), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_0), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_0), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_0), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_0), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_0), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_0), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_0), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_0), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_0), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_0), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_0), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_0), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_0), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_0), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_0), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_0), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_0), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_0), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_0), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_0), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_0), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_0), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_0), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_0), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_0), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_0), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_0), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_0), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_0), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_0), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_0), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_0), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_0), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_0), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_0), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_0), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_0), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_0), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_0), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_0), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_0), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_0), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_0), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_0), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_0), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_0), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_0), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_0), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_0), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_0), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_0), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_0), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_0), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_0), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_0), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_0), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_0), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_0), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_0), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_0), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_0), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_0), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_0), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_0), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_0), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_0), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_0), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_0), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_0), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_0), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_0), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_0), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_0), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_0), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_0), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_0), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_0), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_0), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_0), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_0), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_0), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_0), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_0), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_0), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_0), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_0), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_0), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_0), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_0), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_0), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_0), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_0), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_0), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_0), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_0), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_0), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_0), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_0), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_0), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_0), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_0), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_0), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_0), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_0), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_0), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_0), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_0), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_0), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_0), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_0), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_0), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_0), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_0), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e8c0_0), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8d0_0), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8e8_0), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f0_0), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f8_0), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f9_0), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8fa_0), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8fb_0), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e9c0_0), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9d0_0), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9e8_0), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f0_0), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f8_0), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f9_0), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9fa_0), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9fb_0), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_eac0_0), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_ead0_0), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eae8_0), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf0_0), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf8_0), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf9_0), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_ebc0_0), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebd0_0), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebe8_0), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf0_0), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf8_0), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf9_0), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebfa_0), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebfb_0), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ecc0_0), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecd0_0), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ece8_0), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf0_0), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf8_0), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf9_0), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_edc0_0), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edd0_0), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_ede8_0), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf0_0), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf8_0), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf9_0), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edfa_0), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edfb_0), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_eec0_0), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eed0_0), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eee8_0), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef0_0), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef8_0), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef9_0), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_efc0_0), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_efd0_0), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_efe8_0), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff0_0), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff8_0), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff9_0), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_f000_0), 0xf000, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f008_0), 0xf008, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f010_0), 0xf010, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f018_0), 0xf018, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f020_0), 0xf020, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f028_0), 0xf028, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f030_0), 0xf030, -1, { -3, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f038_0), 0xf038, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f039_0), 0xf039, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f200_0), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f208_0), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f210_0), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f218_0), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f220_0), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f228_0), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f230_0), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f238_0), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f239_0), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23a_0), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23b_0), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23c_0), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f240_0), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f248_0), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+{ CPUFUNC(op_f250_0), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f258_0), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f260_0), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f268_0), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f270_0), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f278_0), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f279_0), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f27a_0), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f27b_0), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f27c_0), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f280_0), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+{ CPUFUNC(op_f2c0_0), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+{ CPUFUNC(op_f310_0), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f320_0), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f328_0), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f330_0), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f338_0), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f339_0), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f350_0), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f358_0), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f368_0), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f370_0), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f378_0), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f379_0), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f37a_0), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f37b_0), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f408_0), 0xf408, -1, { 0, 0 }, 0 }, /* CINVL */
+{ CPUFUNC(op_f410_0), 0xf410, -1, { 0, 0 }, 0 }, /* CINVP */
+{ CPUFUNC(op_f418_0), 0xf418, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f419_0), 0xf419, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f41a_0), 0xf41a, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f41b_0), 0xf41b, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f41c_0), 0xf41c, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f41d_0), 0xf41d, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f41e_0), 0xf41e, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f41f_0), 0xf41f, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f428_0), 0xf428, -1, { 0, 0 }, 0 }, /* CPUSHL */
+{ CPUFUNC(op_f430_0), 0xf430, -1, { 0, 0 }, 0 }, /* CPUSHP */
+{ CPUFUNC(op_f438_0), 0xf438, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f439_0), 0xf439, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f43a_0), 0xf43a, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f43b_0), 0xf43b, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f43c_0), 0xf43c, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f43d_0), 0xf43d, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f43e_0), 0xf43e, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f43f_0), 0xf43f, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f500_0), 0xf500, -1, { 0, 0 }, 0 }, /* PFLUSHN */
+{ CPUFUNC(op_f508_0), 0xf508, -1, { 0, 0 }, 0 }, /* PFLUSH */
+{ CPUFUNC(op_f510_0), 0xf510, -1, { 0, 0 }, 0 }, /* PFLUSHAN */
+{ CPUFUNC(op_f518_0), 0xf518, -1, { 0, 0 }, 0 }, /* PFLUSHA */
+{ CPUFUNC(op_f548_0), 0xf548, -1, { 0, 0 }, 0 }, /* PTESTW */
+{ CPUFUNC(op_f568_0), 0xf568, -1, { 0, 0 }, 0 }, /* PTESTR */
+{ CPUFUNC(op_f600_0), 0xf600, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ CPUFUNC(op_f608_0), 0xf608, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ CPUFUNC(op_f610_0), 0xf610, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ CPUFUNC(op_f618_0), 0xf618, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ CPUFUNC(op_f620_0), 0xf620, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_2)[] = {
+{ CPUFUNC(op_0000_0), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_0), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_0), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_0), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_0), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_0), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_0), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_0), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_0), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_0), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_0), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_0), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_0), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_0), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_0), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_0), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_0), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_0), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_0), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_0), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_0), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_0), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_0), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_0), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_0), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_0), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00d0_0), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00e8_0), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f0_0), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f8_0), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f9_0), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00fa_0), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00fb_0), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0100_0), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_0), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_0), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_0), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_0), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_0), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_0), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_0), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_0), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_0), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_0), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_0), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_0), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_0), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_0), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_0), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_0), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_0), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_0), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_0), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_0), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_0), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_0), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_0), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_0), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_0), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_0), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_0), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_0), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_0), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_0), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_0), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_0), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_0), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_0), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_0), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_0), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_0), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_0), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_0), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_0), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_0), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_0), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_0), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_0), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_0), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_0), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_0), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_0), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_0), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_0), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_0), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_0), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_0), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_0), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_0), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_0), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_0), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_0), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_0), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_0), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_0), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_0), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_0), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_0), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02d0_0), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02e8_0), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f0_0), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f8_0), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f9_0), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02fa_0), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02fb_0), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0400_0), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_0), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_0), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_0), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_0), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_0), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_0), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_0), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_0), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_0), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_0), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_0), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_0), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_0), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_0), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_0), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_0), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_0), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_0), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_0), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_0), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_0), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_0), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_0), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04d0_0), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04e8_0), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f0_0), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f8_0), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f9_0), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04fa_0), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04fb_0), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0600_0), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_0), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_0), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_0), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_0), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_0), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_0), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_0), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_0), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_0), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_0), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_0), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_0), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_0), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_0), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_0), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_0), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_0), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_0), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_0), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_0), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_0), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_0), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_0), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06c0_0), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+{ CPUFUNC(op_06c8_0), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+{ CPUFUNC(op_06d0_0), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06e8_0), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f0_0), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f8_0), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f9_0), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06fa_0), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06fb_0), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_0800_0), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_0), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_0), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_0), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_0), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_0), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_0), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_0), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_0), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_0), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_0), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_0), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_0), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_0), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_0), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_0), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_0), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_0), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_0), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_0), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_0), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_0), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_0), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_0), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_0), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_0), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_0), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_0), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_0), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_0), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_0), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_0), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_0), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_0), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_0), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_0), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_0), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_0), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_0), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_0), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_0), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_0), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_0), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_0), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_0), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_0), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_0), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_0), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_0), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_0), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_0), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_0), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_0), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_0), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_0), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_0), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_0), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_0), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_0), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_0), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ad0_0), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ad8_0), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ae0_0), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ae8_0), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af0_0), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af8_0), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af9_0), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0c00_0), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_0), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_0), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_0), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_0), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_0), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_0), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_0), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c3a_0), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c3b_0), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c40_0), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_0), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_0), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_0), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_0), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_0), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_0), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_0), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c7a_0), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c7b_0), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c80_0), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_0), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_0), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_0), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_0), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_0), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_0), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_0), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cba_0), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cbb_0), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cd0_0), 0x0cd0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cd8_0), 0x0cd8, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ce0_0), 0x0ce0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ce8_0), 0x0ce8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf0_0), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf8_0), 0x0cf8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf9_0), 0x0cf9, 16, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cfc_0), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+{ CPUFUNC(op_0e10_0), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e18_0), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e20_0), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e28_0), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e30_0), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e38_0), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e39_0), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e50_0), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e58_0), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e60_0), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e68_0), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e70_0), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e78_0), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e79_0), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e90_0), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e98_0), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ea0_0), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ea8_0), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb0_0), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb8_0), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb9_0), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ed0_0), 0x0ed0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ed8_0), 0x0ed8, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ee0_0), 0x0ee0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ee8_0), 0x0ee8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef0_0), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef8_0), 0x0ef8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef9_0), 0x0ef9, 16, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0efc_0), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+{ CPUFUNC(op_1000_0), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_0), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_0), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_0), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_0), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_0), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_0), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_0), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_0), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_0), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_0), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_0), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_0), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_0), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_0), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_0), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_0), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_0), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_0), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_0), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_0), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_0), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_0), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_0), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_0), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_0), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_0), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_0), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_0), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_0), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_0), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_0), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_0), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_0), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_0), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_0), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_0), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_0), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_0), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_0), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_0), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_0), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_0), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_0), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_0), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_0), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_0), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_0), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_0), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_0), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_0), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_0), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_0), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_0), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_0), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_0), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_0), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_0), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_0), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_0), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_0), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_0), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_0), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_0), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_0), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_0), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_0), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_0), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_0), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_0), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_0), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_0), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_0), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_0), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_0), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_0), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_0), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_0), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_0), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_0), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_0), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_0), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_0), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_0), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_0), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_0), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_0), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_0), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_0), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_0), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_0), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_0), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_0), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_0), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_0), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_0), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_0), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_0), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_0), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_0), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_0), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_0), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_0), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_0), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_0), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_0), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_0), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_0), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_0), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_0), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_0), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_0), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_0), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_0), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_0), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_0), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_0), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_0), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_0), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_0), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_0), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_0), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_0), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_0), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_0), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_0), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_0), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_0), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_0), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_0), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_0), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_0), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_0), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_0), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_0), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_0), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_0), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_0), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_0), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_0), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_0), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_0), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_0), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_0), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_0), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_0), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_0), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_0), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_0), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_0), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_0), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_0), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_0), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_0), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_0), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_0), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_0), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_0), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_0), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_0), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_0), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_0), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_0), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_0), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_0), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_0), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_0), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_0), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_0), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_0), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_0), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_0), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_0), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_0), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_0), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_0), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_0), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_0), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_0), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_0), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_0), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_0), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_0), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_0), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_0), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_0), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_0), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_0), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_0), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_0), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_0), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_0), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_0), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_0), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_0), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_0), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_0), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_0), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_0), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_0), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_0), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_0), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_0), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_0), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_0), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_0), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_0), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_0), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_0), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_0), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_0), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_0), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_0), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_0), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_0), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_0), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_0), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_0), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_0), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_0), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_0), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_0), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_0), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_0), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_0), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_0), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_0), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_0), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_0), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_0), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_0), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_0), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_0), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_0), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_0), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_0), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_0), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_0), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_0), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_0), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_0), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_0), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_0), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_0), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_0), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_0), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_0), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_0), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_0), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_0), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_0), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_0), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_0), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_0), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_0), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_0), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_0), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_0), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_0), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_0), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_0), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_0), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_0), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_0), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_0), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_0), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_0), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_0), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_0), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_0), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_0), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_0), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_0), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_0), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_0), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_0), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_0), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_0), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_0), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_0), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_0), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_0), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_0), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_0), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_0), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_0), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_0), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_0), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_0), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_0), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_0), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_0), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_0), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_0), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_0), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_0), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_0), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_0), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_0), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_0), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_0), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_0), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_0), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_0), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_0), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_0), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_0), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_0), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_0), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_0), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_0), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_0), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_0), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_0), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_0), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_0), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_0), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_0), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_0), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_0), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_0), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_0), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_0), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_0), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_0), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_0), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_0), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_0), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_0), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_0), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_0), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_0), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_0), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_0), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_0), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_0), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4100_0), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4110_0), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4118_0), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4120_0), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4128_0), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4130_0), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4138_0), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4139_0), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413a_0), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413b_0), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413c_0), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4180_0), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_0), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_0), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_0), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_0), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_0), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_0), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_0), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_0), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_0), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_0), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_0), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_0), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_0), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_0), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_0), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_0), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_0), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_0), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_0), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_0), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_0), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_0), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_0), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_0), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_0), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_0), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_0), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_0), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_0), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_0), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_0), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_0), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_0), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_0), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_0), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_0), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_0), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_0), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_0), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_0), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_0), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42c0_0), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d0_0), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d8_0), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e0_0), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e8_0), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f0_0), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f8_0), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f9_0), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4400_0), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_0), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_0), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_0), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_0), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_0), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_0), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_0), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_0), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_0), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_0), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_0), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_0), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_0), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_0), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_0), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_0), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_0), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_0), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_0), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_0), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_0), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_0), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_0), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_0), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_0), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_0), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_0), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_0), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_0), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_0), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_0), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_0), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_0), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_0), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_0), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_0), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_0), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_0), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_0), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_0), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_0), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_0), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_0), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_0), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_0), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_0), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_0), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_0), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_0), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_0), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_0), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_0), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_0), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_0), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_0), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_0), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_0), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_0), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_0), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_0), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_0), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_0), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_0), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_0), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_0), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_0), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_0), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_0), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_0), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_2), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4808_0), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4810_2), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_2), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_2), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_2), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_2), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_2), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_2), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_0), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ CPUFUNC(op_4848_0), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+{ CPUFUNC(op_4850_0), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_0), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_0), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_0), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_0), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_0), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_0), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_0), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_0), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_0), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_0), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_0), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_0), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_0), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_0), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_0), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_0), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_0), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_0), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_0), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_0), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_49c0_0), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4a00_0), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_0), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_0), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_0), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_0), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_0), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_0), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_0), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3a_0), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3b_0), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3c_0), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a40_0), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a48_0), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a50_0), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_0), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_0), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_0), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_0), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_0), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_0), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7a_0), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7b_0), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7c_0), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a80_0), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a88_0), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a90_0), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_0), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_0), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_0), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_0), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_0), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_0), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aba_0), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4abb_0), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4abc_0), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ac0_0), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_0), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_0), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_0), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_0), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_0), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_0), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_0), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4c00_0), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c10_0), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c18_0), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c20_0), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c28_0), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c30_0), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c38_0), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c39_0), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3a_0), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3b_0), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3c_0), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c40_0), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c50_0), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c58_0), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c60_0), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c68_0), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c70_0), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c78_0), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c79_0), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7a_0), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7b_0), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7c_0), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c90_0), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_0), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_0), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_0), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_0), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_0), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_0), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_0), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_0), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_0), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_0), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_0), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_0), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_0), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_0), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_0), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_0), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_0), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_0), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_0), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_0), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_0), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_0), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_0), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_0), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+{ CPUFUNC(op_4e74_0), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+{ CPUFUNC(op_4e75_0), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_0), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_0), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+{ CPUFUNC(op_4e7a_0), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+{ CPUFUNC(op_4e7b_0), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+{ CPUFUNC(op_4e90_0), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_0), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_0), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_0), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_0), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_0), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_0), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_0), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_0), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_0), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_0), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_0), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_0), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_0), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_0), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_0), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_0), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_0), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_0), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_0), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_0), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_0), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_0), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_0), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_0), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_0), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_0), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_0), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_0), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_0), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_0), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_0), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_0), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_0), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_0), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_0), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_0), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_0), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_0), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_0), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_0), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_0), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_0), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_0), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_0), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_0), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_0), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_0), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_0), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50fa_0), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_50fb_0), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_50fc_0), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5100_0), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_0), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_0), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_0), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_0), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_0), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_0), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_0), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_0), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_0), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_0), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_0), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_0), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_0), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_0), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_0), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_0), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_0), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_0), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_0), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_0), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_0), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_0), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_0), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_0), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_0), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_0), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_0), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_0), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_0), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_0), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_0), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_0), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_0), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_0), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51fa_0), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_51fb_0), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_51fc_0), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52c0_0), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_0), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_0), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_0), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_0), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_0), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_0), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_0), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_0), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52fa_0), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52fb_0), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52fc_0), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53c0_0), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_0), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_0), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_0), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_0), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_0), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_0), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_0), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_0), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53fa_0), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53fb_0), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53fc_0), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54c0_0), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_0), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_0), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_0), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_0), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_0), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_0), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_0), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_0), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54fa_0), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54fb_0), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54fc_0), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55c0_0), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_0), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_0), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_0), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_0), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_0), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_0), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_0), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_0), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55fa_0), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55fb_0), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55fc_0), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56c0_0), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_0), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_0), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_0), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_0), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_0), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_0), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_0), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_0), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56fa_0), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56fb_0), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56fc_0), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57c0_0), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_0), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_0), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_0), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_0), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_0), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_0), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_0), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_0), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57fa_0), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57fb_0), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57fc_0), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58c0_0), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_0), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_0), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_0), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_0), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_0), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_0), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_0), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_0), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58fa_0), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58fb_0), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58fc_0), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59c0_0), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_0), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_0), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_0), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_0), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_0), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_0), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_0), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_0), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59fa_0), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59fb_0), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59fc_0), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ac0_0), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_0), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_0), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_0), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_0), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_0), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_0), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_0), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_0), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5afa_0), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5afb_0), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5afc_0), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bc0_0), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_0), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_0), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_0), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_0), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_0), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_0), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_0), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_0), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bfa_0), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bfb_0), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bfc_0), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cc0_0), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_0), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_0), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_0), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_0), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_0), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_0), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_0), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_0), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cfa_0), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cfb_0), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cfc_0), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dc0_0), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_0), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_0), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_0), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_0), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_0), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_0), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_0), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_0), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dfa_0), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dfb_0), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dfc_0), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ec0_0), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_0), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_0), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_0), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_0), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_0), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_0), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_0), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_0), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5efa_0), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5efb_0), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5efc_0), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5fc0_0), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_0), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_0), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_0), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_0), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_0), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_0), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_0), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_0), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ffa_0), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ffb_0), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ffc_0), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_6000_0), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_0), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_0), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6100_0), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_0), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_0), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_0), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_0), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_0), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6300_0), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_0), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_0), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6400_0), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_0), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_0), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6500_0), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_0), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_0), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6600_0), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_0), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_0), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6700_0), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_0), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_0), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6800_0), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_0), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_0), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6900_0), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_0), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_0), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a00_0), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_0), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_0), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b00_0), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_0), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_0), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c00_0), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_0), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_0), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d00_0), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_0), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_0), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e00_0), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_0), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_0), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f00_0), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_0), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_0), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_7000_0), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_0), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_0), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_0), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_0), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_0), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_0), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_0), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_0), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_0), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_0), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_0), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_0), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_0), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_0), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_0), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_0), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_0), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_0), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_0), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_0), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_0), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_0), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_0), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_0), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_0), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_0), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_0), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_0), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_0), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_0), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_0), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_0), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_0), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_0), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_0), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_0), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_0), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_0), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_0), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_0), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_0), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_0), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_0), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_0), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_2), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_2), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_0), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_0), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_0), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_0), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_0), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_0), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_0), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8140_0), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+{ CPUFUNC(op_8148_0), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+{ CPUFUNC(op_8150_0), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_0), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_0), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_0), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_0), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_0), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_0), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8180_0), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+{ CPUFUNC(op_8188_0), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+{ CPUFUNC(op_8190_0), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_0), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_0), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_0), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_0), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_0), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_0), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_0), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_0), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_0), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_0), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_0), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_0), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_0), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_0), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_0), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_0), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_0), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_0), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_0), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_0), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_0), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_0), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_0), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_0), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_0), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_0), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_0), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_0), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_0), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_0), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_0), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_0), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_0), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_0), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_0), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_0), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_0), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_0), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_0), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_0), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_0), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_0), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_0), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_0), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_0), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_0), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_0), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_0), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_0), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_0), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_0), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_0), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_0), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_0), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_0), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_0), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_0), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_0), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_0), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_0), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_0), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_0), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_0), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_0), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_0), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_0), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_0), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_0), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_0), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_0), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_0), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_0), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_0), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_0), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_0), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_0), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_0), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_0), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_0), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_0), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_0), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_0), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_0), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_0), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_0), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_0), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_0), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_0), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_0), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_0), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_0), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_0), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_0), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_0), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_0), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_0), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_0), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_0), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_0), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_0), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_0), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_0), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_0), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_0), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_0), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_0), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_0), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_0), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_0), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_0), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_0), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_0), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_0), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_0), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_0), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_0), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_0), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_0), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_0), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_0), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_0), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_0), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_0), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_0), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_0), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_0), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_0), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_0), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_0), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_0), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_0), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_0), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_0), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_0), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_0), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_0), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_0), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_0), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_0), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_0), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_0), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_0), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_0), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_0), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_0), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_0), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_0), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_0), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_0), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_0), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_0), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_0), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_0), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_0), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_0), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_0), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_0), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_0), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_0), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_0), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_0), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_0), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_0), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_0), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_0), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_0), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_0), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_0), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_0), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_0), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_0), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_0), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_0), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_0), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_0), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_0), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_0), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_0), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_0), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_0), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_0), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_0), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_0), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_0), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_0), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_0), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_0), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_0), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_0), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_0), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_0), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_0), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_0), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_0), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_0), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_0), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_0), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_0), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_0), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_0), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_0), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_0), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_0), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_0), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_0), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_0), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_0), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_0), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_0), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_0), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_0), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_0), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_0), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_0), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_0), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_0), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_0), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_0), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_0), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_0), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_0), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_0), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_0), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_0), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_0), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_0), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_0), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_0), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_0), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_0), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_0), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_0), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_0), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_2), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_2), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_0), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_0), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_0), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_0), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_0), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_0), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_0), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_0), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_0), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_0), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_0), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_0), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_0), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_0), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_0), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_0), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_0), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_0), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_0), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_0), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_0), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_0), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_0), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_0), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_0), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_0), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_0), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_0), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_0), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_0), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_0), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_0), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_0), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_0), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_0), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_0), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_0), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_0), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_0), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_0), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_0), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_0), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_0), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_0), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_0), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_0), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_0), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_0), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_0), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_0), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_0), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_0), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_0), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_0), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_0), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_0), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_0), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_0), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_0), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_0), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_0), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_0), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_0), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_0), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_0), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_0), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_0), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_0), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_0), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_0), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_0), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_0), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_0), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_0), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_0), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_0), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_0), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_0), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_0), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_0), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_0), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_0), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_0), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_0), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_0), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_0), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_0), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_0), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_0), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_0), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_0), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_0), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_0), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_0), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_0), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_0), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_0), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_0), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_0), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_0), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_0), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_0), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_0), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_0), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_0), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_0), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_0), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_0), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_0), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_0), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_0), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_0), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_0), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_0), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_0), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_0), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_0), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_0), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_0), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_0), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_0), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_0), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_0), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_0), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_0), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_0), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_0), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_0), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_0), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_0), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_0), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_0), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_0), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_0), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_0), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_0), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_0), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_0), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_0), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_0), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_0), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_0), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_0), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_0), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_0), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_0), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_0), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_0), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_0), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_0), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_0), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_0), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_0), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_0), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_0), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_0), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_0), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_0), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_0), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_0), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_0), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_0), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_0), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_0), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_0), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_0), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_0), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_0), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_0), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_0), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_0), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_0), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_0), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_0), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_0), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_0), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_0), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_0), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_0), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_0), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_0), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_0), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_0), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_0), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_0), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_0), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_0), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_0), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_0), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_0), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_0), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_0), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_0), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_0), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_0), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_0), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_0), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_0), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_0), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_0), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_0), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_0), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_0), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_0), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_0), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_0), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_0), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_0), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_0), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_0), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_0), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_0), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_0), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_0), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_0), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_0), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_0), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_0), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_0), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_0), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_0), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_0), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_0), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_0), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_0), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e8c0_0), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8d0_0), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8e8_0), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f0_0), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f8_0), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f9_0), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8fa_0), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8fb_0), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e9c0_0), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9d0_0), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9e8_0), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f0_0), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f8_0), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f9_0), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9fa_0), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9fb_0), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_eac0_0), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_ead0_0), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eae8_0), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf0_0), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf8_0), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf9_0), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_ebc0_0), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebd0_0), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebe8_0), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf0_0), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf8_0), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf9_0), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebfa_0), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebfb_0), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ecc0_0), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecd0_0), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ece8_0), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf0_0), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf8_0), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf9_0), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_edc0_0), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edd0_0), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_ede8_0), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf0_0), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf8_0), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf9_0), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edfa_0), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edfb_0), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_eec0_0), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eed0_0), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eee8_0), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef0_0), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef8_0), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef9_0), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_efc0_0), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_efd0_0), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_efe8_0), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff0_0), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff8_0), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff9_0), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_f000_0), 0xf000, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f008_0), 0xf008, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f010_0), 0xf010, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f018_0), 0xf018, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f020_0), 0xf020, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f028_0), 0xf028, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f030_0), 0xf030, -1, { -3, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f038_0), 0xf038, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f039_0), 0xf039, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f200_0), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f208_0), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f210_0), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f218_0), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f220_0), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f228_0), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f230_0), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f238_0), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f239_0), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23a_0), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23b_0), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23c_0), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f240_0), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f248_0), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+{ CPUFUNC(op_f250_0), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f258_0), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f260_0), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f268_0), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f270_0), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f278_0), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f279_0), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f27a_0), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f27b_0), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f27c_0), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f280_0), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+{ CPUFUNC(op_f2c0_0), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+{ CPUFUNC(op_f310_0), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f320_0), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f328_0), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f330_0), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f338_0), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f339_0), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f350_0), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f358_0), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f368_0), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f370_0), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f378_0), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f379_0), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f37a_0), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f37b_0), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_3)[] = {
+{ CPUFUNC(op_0000_0), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_0), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_0), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_0), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_0), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_0), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_0), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_0), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_0), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_0), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_0), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_0), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_0), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_0), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_0), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_0), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_0), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_0), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_0), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_0), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_0), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_0), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_0), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_0), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_0), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_0), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00d0_0), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00e8_0), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f0_0), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f8_0), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f9_0), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00fa_0), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00fb_0), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0100_0), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_0), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_0), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_0), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_0), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_0), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_0), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_0), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_0), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_0), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_0), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_0), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_0), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_0), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_0), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_0), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_0), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_0), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_0), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_0), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_0), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_0), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_0), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_0), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_0), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_0), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_0), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_0), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_0), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_0), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_0), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_0), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_0), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_0), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_0), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_0), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_0), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_0), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_0), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_0), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_0), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_0), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_0), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_0), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_0), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_0), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_0), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_0), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_0), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_0), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_0), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_0), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_0), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_0), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_0), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_0), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_0), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_0), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_0), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_0), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_0), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_0), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_0), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_0), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_0), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02d0_0), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02e8_0), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f0_0), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f8_0), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f9_0), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02fa_0), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02fb_0), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0400_0), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_0), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_0), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_0), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_0), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_0), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_0), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_0), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_0), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_0), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_0), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_0), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_0), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_0), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_0), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_0), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_0), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_0), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_0), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_0), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_0), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_0), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_0), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_0), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04d0_0), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04e8_0), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f0_0), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f8_0), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f9_0), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04fa_0), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04fb_0), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0600_0), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_0), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_0), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_0), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_0), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_0), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_0), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_0), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_0), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_0), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_0), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_0), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_0), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_0), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_0), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_0), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_0), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_0), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_0), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_0), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_0), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_0), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_0), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_0), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06c0_0), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+{ CPUFUNC(op_06c8_0), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+{ CPUFUNC(op_06d0_0), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06e8_0), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f0_0), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f8_0), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f9_0), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06fa_0), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06fb_0), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_0800_0), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_0), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_0), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_0), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_0), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_0), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_0), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_0), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_0), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_0), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_0), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_0), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_0), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_0), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_0), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_0), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_0), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_0), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_0), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_0), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_0), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_0), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_0), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_0), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_0), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_0), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_0), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_0), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_0), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_0), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_0), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_0), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_0), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_0), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_0), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_0), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_0), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_0), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_0), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_0), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_0), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_0), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_0), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_0), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_0), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_0), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_0), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_0), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_0), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_0), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_0), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_0), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_0), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_0), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_0), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_0), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_0), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_0), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_0), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_0), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ad0_0), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ad8_0), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ae0_0), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ae8_0), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af0_0), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af8_0), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af9_0), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0c00_0), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_0), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_0), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_0), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_0), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_0), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_0), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_0), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c3a_0), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c3b_0), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c40_0), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_0), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_0), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_0), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_0), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_0), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_0), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_0), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c7a_0), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c7b_0), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c80_0), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_0), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_0), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_0), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_0), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_0), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_0), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_0), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cba_0), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cbb_0), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cd0_0), 0x0cd0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cd8_0), 0x0cd8, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ce0_0), 0x0ce0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ce8_0), 0x0ce8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf0_0), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf8_0), 0x0cf8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf9_0), 0x0cf9, 16, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cfc_0), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+{ CPUFUNC(op_0e10_0), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e18_0), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e20_0), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e28_0), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e30_0), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e38_0), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e39_0), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e50_0), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e58_0), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e60_0), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e68_0), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e70_0), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e78_0), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e79_0), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e90_0), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e98_0), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ea0_0), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ea8_0), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb0_0), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb8_0), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb9_0), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ed0_0), 0x0ed0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ed8_0), 0x0ed8, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ee0_0), 0x0ee0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ee8_0), 0x0ee8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef0_0), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef8_0), 0x0ef8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef9_0), 0x0ef9, 16, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0efc_0), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+{ CPUFUNC(op_1000_0), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_0), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_0), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_0), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_0), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_0), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_0), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_0), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_0), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_0), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_0), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_0), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_0), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_0), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_0), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_0), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_0), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_0), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_0), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_0), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_0), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_0), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_0), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_0), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_0), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_0), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_0), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_0), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_0), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_0), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_0), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_0), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_0), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_0), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_0), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_0), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_0), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_0), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_0), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_0), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_0), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_0), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_0), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_0), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_0), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_0), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_0), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_0), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_0), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_0), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_0), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_0), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_0), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_0), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_0), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_0), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_0), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_0), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_0), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_0), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_0), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_0), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_0), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_0), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_0), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_0), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_0), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_0), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_0), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_0), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_0), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_0), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_0), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_0), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_0), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_0), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_0), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_0), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_0), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_0), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_0), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_0), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_0), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_0), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_0), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_0), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_0), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_0), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_0), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_0), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_0), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_0), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_0), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_0), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_0), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_0), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_0), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_0), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_0), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_0), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_0), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_0), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_0), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_0), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_0), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_0), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_0), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_0), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_0), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_0), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_0), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_0), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_0), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_0), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_0), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_0), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_0), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_0), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_0), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_0), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_0), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_0), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_0), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_0), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_0), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_0), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_0), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_0), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_0), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_0), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_0), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_0), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_0), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_0), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_0), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_0), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_0), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_0), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_0), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_0), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_0), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_0), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_0), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_0), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_0), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_0), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_0), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_0), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_0), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_0), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_0), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_0), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_0), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_0), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_0), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_0), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_0), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_0), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_0), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_0), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_0), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_0), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_0), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_0), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_0), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_0), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_0), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_0), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_0), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_0), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_0), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_0), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_0), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_0), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_0), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_0), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_0), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_0), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_0), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_0), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_0), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_0), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_0), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_0), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_0), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_0), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_0), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_0), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_0), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_0), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_0), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_0), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_0), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_0), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_0), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_0), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_0), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_0), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_0), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_0), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_0), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_0), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_0), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_0), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_0), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_0), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_0), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_0), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_0), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_0), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_0), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_0), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_0), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_0), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_0), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_0), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_0), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_0), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_0), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_0), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_0), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_0), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_0), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_0), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_0), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_0), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_0), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_0), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_0), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_0), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_0), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_0), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_0), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_0), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_0), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_0), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_0), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_0), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_0), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_0), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_0), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_0), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_0), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_0), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_0), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_0), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_0), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_0), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_0), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_0), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_0), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_0), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_0), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_0), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_0), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_0), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_0), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_0), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_0), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_0), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_0), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_0), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_0), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_0), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_0), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_0), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_0), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_0), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_0), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_0), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_0), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_0), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_0), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_0), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_0), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_0), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_0), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_0), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_0), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_0), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_0), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_0), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_0), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_0), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_0), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_0), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_0), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_0), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_0), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_0), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_0), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_0), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_0), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_0), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_0), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_0), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_0), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_0), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_0), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_0), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_0), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_0), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_0), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_0), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_0), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_0), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_0), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_0), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_0), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_0), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_0), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_0), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_0), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_0), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_0), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_0), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_0), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_0), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_0), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_0), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_0), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_0), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_0), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_0), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_0), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_0), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_0), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_0), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_0), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_0), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_0), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_0), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_0), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_0), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_0), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_0), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4100_0), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4110_0), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4118_0), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4120_0), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4128_0), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4130_0), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4138_0), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4139_0), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413a_0), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413b_0), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413c_0), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4180_0), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_0), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_0), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_0), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_0), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_0), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_0), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_0), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_0), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_0), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_0), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_0), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_0), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_0), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_0), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_0), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_0), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_0), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_0), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_0), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_0), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_0), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_0), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_0), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_0), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_0), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_0), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_0), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_0), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_0), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_0), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_0), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_0), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_0), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_0), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_0), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_0), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_0), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_0), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_0), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_0), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_0), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42c0_0), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d0_0), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d8_0), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e0_0), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e8_0), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f0_0), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f8_0), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f9_0), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4400_0), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_0), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_0), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_0), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_0), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_0), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_0), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_0), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_0), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_0), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_0), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_0), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_0), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_0), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_0), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_0), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_0), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_0), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_0), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_0), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_0), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_0), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_0), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_0), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_0), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_0), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_0), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_0), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_0), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_0), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_0), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_0), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_0), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_0), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_0), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_0), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_0), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_0), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_0), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_0), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_0), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_0), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_0), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_0), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_0), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_0), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_0), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_0), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_0), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_0), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_0), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_0), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_0), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_0), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_0), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_0), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_0), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_0), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_0), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_0), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_0), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_0), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_0), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_0), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_0), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_0), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_0), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_0), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_0), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_0), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_2), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4808_0), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4810_2), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_2), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_2), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_2), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_2), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_2), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_2), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_0), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ CPUFUNC(op_4848_0), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+{ CPUFUNC(op_4850_0), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_0), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_0), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_0), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_0), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_0), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_0), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_0), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_0), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_0), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_0), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_0), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_0), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_0), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_0), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_0), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_0), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_0), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_0), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_0), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_0), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_49c0_0), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4a00_0), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_0), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_0), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_0), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_0), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_0), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_0), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_0), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3a_0), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3b_0), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3c_0), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a40_0), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a48_0), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a50_0), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_0), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_0), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_0), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_0), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_0), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_0), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7a_0), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7b_0), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7c_0), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a80_0), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a88_0), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a90_0), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_0), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_0), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_0), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_0), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_0), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_0), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aba_0), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4abb_0), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4abc_0), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ac0_0), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_0), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_0), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_0), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_0), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_0), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_0), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_0), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4c00_0), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c10_0), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c18_0), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c20_0), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c28_0), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c30_0), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c38_0), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c39_0), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3a_0), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3b_0), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3c_0), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c40_0), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c50_0), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c58_0), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c60_0), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c68_0), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c70_0), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c78_0), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c79_0), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7a_0), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7b_0), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7c_0), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c90_0), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_0), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_0), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_0), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_0), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_0), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_0), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_0), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_0), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_0), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_0), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_0), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_0), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_0), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_0), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_0), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_0), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_0), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_0), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_0), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_0), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_0), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_0), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_0), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_0), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+{ CPUFUNC(op_4e74_0), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+{ CPUFUNC(op_4e75_0), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_0), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_0), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+{ CPUFUNC(op_4e7a_0), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+{ CPUFUNC(op_4e7b_0), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+{ CPUFUNC(op_4e90_0), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_0), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_0), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_0), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_0), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_0), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_0), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_0), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_0), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_0), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_0), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_0), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_0), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_0), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_0), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_0), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_0), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_0), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_0), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_0), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_0), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_0), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_0), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_0), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_0), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_0), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_0), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_0), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_0), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_0), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_0), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_0), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_0), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_0), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_0), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_0), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_0), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_0), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_0), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_0), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_0), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_0), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_0), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_0), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_0), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_0), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_0), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_0), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_0), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50fa_0), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_50fb_0), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_50fc_0), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5100_0), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_0), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_0), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_0), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_0), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_0), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_0), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_0), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_0), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_0), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_0), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_0), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_0), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_0), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_0), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_0), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_0), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_0), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_0), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_0), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_0), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_0), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_0), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_0), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_0), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_0), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_0), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_0), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_0), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_0), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_0), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_0), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_0), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_0), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_0), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51fa_0), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_51fb_0), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_51fc_0), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52c0_0), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_0), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_0), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_0), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_0), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_0), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_0), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_0), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_0), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52fa_0), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52fb_0), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52fc_0), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53c0_0), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_0), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_0), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_0), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_0), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_0), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_0), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_0), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_0), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53fa_0), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53fb_0), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53fc_0), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54c0_0), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_0), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_0), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_0), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_0), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_0), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_0), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_0), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_0), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54fa_0), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54fb_0), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54fc_0), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55c0_0), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_0), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_0), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_0), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_0), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_0), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_0), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_0), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_0), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55fa_0), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55fb_0), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55fc_0), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56c0_0), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_0), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_0), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_0), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_0), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_0), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_0), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_0), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_0), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56fa_0), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56fb_0), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56fc_0), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57c0_0), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_0), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_0), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_0), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_0), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_0), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_0), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_0), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_0), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57fa_0), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57fb_0), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57fc_0), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58c0_0), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_0), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_0), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_0), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_0), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_0), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_0), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_0), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_0), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58fa_0), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58fb_0), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58fc_0), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59c0_0), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_0), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_0), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_0), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_0), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_0), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_0), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_0), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_0), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59fa_0), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59fb_0), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59fc_0), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ac0_0), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_0), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_0), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_0), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_0), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_0), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_0), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_0), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_0), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5afa_0), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5afb_0), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5afc_0), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bc0_0), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_0), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_0), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_0), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_0), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_0), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_0), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_0), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_0), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bfa_0), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bfb_0), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bfc_0), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cc0_0), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_0), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_0), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_0), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_0), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_0), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_0), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_0), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_0), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cfa_0), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cfb_0), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cfc_0), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dc0_0), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_0), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_0), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_0), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_0), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_0), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_0), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_0), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_0), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dfa_0), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dfb_0), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dfc_0), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ec0_0), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_0), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_0), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_0), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_0), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_0), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_0), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_0), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_0), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5efa_0), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5efb_0), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5efc_0), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5fc0_0), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_0), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_0), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_0), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_0), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_0), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_0), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_0), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_0), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ffa_0), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ffb_0), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ffc_0), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_6000_0), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_0), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_0), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6100_0), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_0), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_0), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_0), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_0), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_0), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6300_0), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_0), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_0), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6400_0), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_0), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_0), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6500_0), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_0), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_0), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6600_0), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_0), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_0), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6700_0), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_0), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_0), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6800_0), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_0), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_0), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6900_0), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_0), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_0), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a00_0), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_0), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_0), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b00_0), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_0), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_0), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c00_0), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_0), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_0), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d00_0), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_0), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_0), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e00_0), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_0), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_0), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f00_0), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_0), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_0), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_7000_0), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_0), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_0), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_0), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_0), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_0), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_0), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_0), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_0), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_0), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_0), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_0), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_0), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_0), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_0), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_0), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_0), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_0), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_0), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_0), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_0), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_0), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_0), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_0), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_0), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_0), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_0), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_0), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_0), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_0), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_0), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_0), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_0), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_0), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_0), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_0), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_0), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_0), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_0), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_0), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_0), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_0), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_0), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_0), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_0), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_2), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_2), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_0), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_0), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_0), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_0), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_0), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_0), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_0), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8140_0), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+{ CPUFUNC(op_8148_0), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+{ CPUFUNC(op_8150_0), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_0), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_0), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_0), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_0), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_0), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_0), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8180_0), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+{ CPUFUNC(op_8188_0), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+{ CPUFUNC(op_8190_0), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_0), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_0), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_0), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_0), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_0), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_0), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_0), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_0), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_0), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_0), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_0), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_0), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_0), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_0), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_0), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_0), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_0), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_0), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_0), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_0), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_0), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_0), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_0), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_0), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_0), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_0), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_0), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_0), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_0), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_0), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_0), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_0), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_0), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_0), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_0), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_0), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_0), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_0), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_0), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_0), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_0), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_0), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_0), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_0), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_0), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_0), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_0), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_0), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_0), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_0), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_0), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_0), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_0), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_0), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_0), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_0), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_0), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_0), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_0), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_0), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_0), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_0), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_0), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_0), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_0), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_0), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_0), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_0), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_0), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_0), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_0), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_0), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_0), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_0), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_0), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_0), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_0), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_0), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_0), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_0), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_0), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_0), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_0), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_0), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_0), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_0), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_0), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_0), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_0), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_0), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_0), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_0), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_0), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_0), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_0), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_0), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_0), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_0), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_0), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_0), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_0), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_0), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_0), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_0), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_0), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_0), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_0), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_0), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_0), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_0), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_0), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_0), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_0), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_0), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_0), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_0), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_0), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_0), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_0), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_0), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_0), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_0), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_0), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_0), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_0), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_0), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_0), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_0), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_0), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_0), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_0), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_0), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_0), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_0), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_0), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_0), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_0), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_0), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_0), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_0), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_0), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_0), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_0), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_0), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_0), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_0), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_0), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_0), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_0), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_0), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_0), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_0), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_0), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_0), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_0), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_0), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_0), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_0), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_0), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_0), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_0), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_0), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_0), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_0), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_0), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_0), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_0), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_0), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_0), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_0), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_0), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_0), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_0), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_0), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_0), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_0), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_0), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_0), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_0), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_0), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_0), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_0), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_0), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_0), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_0), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_0), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_0), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_0), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_0), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_0), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_0), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_0), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_0), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_0), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_0), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_0), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_0), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_0), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_0), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_0), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_0), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_0), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_0), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_0), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_0), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_0), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_0), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_0), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_0), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_0), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_0), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_0), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_0), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_0), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_0), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_0), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_0), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_0), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_0), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_0), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_0), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_0), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_0), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_0), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_0), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_0), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_0), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_0), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_0), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_0), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_0), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_0), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_0), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_2), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_2), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_0), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_0), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_0), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_0), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_0), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_0), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_0), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_0), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_0), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_0), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_0), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_0), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_0), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_0), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_0), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_0), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_0), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_0), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_0), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_0), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_0), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_0), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_0), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_0), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_0), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_0), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_0), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_0), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_0), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_0), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_0), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_0), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_0), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_0), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_0), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_0), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_0), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_0), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_0), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_0), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_0), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_0), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_0), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_0), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_0), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_0), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_0), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_0), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_0), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_0), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_0), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_0), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_0), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_0), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_0), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_0), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_0), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_0), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_0), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_0), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_0), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_0), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_0), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_0), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_0), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_0), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_0), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_0), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_0), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_0), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_0), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_0), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_0), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_0), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_0), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_0), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_0), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_0), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_0), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_0), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_0), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_0), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_0), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_0), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_0), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_0), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_0), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_0), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_0), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_0), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_0), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_0), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_0), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_0), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_0), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_0), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_0), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_0), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_0), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_0), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_0), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_0), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_0), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_0), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_0), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_0), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_0), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_0), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_0), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_0), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_0), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_0), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_0), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_0), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_0), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_0), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_0), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_0), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_0), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_0), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_0), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_0), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_0), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_0), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_0), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_0), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_0), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_0), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_0), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_0), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_0), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_0), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_0), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_0), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_0), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_0), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_0), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_0), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_0), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_0), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_0), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_0), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_0), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_0), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_0), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_0), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_0), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_0), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_0), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_0), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_0), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_0), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_0), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_0), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_0), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_0), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_0), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_0), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_0), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_0), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_0), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_0), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_0), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_0), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_0), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_0), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_0), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_0), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_0), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_0), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_0), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_0), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_0), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_0), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_0), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_0), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_0), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_0), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_0), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_0), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_0), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_0), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_0), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_0), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_0), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_0), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_0), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_0), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_0), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_0), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_0), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_0), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_0), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_0), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_0), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_0), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_0), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_0), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_0), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_0), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_0), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_0), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_0), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_0), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_0), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_0), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_0), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_0), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_0), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_0), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_0), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_0), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_0), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_0), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_0), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_0), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_0), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_0), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_0), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_0), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_0), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_0), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_0), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_0), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_0), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e8c0_0), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8d0_0), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8e8_0), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f0_0), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f8_0), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f9_0), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8fa_0), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8fb_0), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e9c0_0), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9d0_0), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9e8_0), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f0_0), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f8_0), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f9_0), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9fa_0), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9fb_0), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_eac0_0), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_ead0_0), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eae8_0), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf0_0), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf8_0), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf9_0), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_ebc0_0), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebd0_0), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebe8_0), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf0_0), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf8_0), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf9_0), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebfa_0), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebfb_0), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ecc0_0), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecd0_0), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ece8_0), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf0_0), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf8_0), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf9_0), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_edc0_0), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edd0_0), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_ede8_0), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf0_0), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf8_0), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf9_0), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edfa_0), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edfb_0), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_eec0_0), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eed0_0), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eee8_0), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef0_0), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef8_0), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef9_0), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_efc0_0), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_efd0_0), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_efe8_0), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff0_0), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff8_0), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff9_0), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_f200_0), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f208_0), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f210_0), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f218_0), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f220_0), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f228_0), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f230_0), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f238_0), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f239_0), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23a_0), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23b_0), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23c_0), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f240_0), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f248_0), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+{ CPUFUNC(op_f250_0), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f258_0), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f260_0), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f268_0), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f270_0), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f278_0), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f279_0), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f27a_0), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f27b_0), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f27c_0), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f280_0), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+{ CPUFUNC(op_f2c0_0), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+{ CPUFUNC(op_f310_0), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f320_0), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f328_0), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f330_0), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f338_0), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f339_0), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f350_0), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f358_0), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f368_0), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f370_0), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f378_0), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f379_0), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f37a_0), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f37b_0), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_4)[] = {
+{ CPUFUNC(op_0000_0), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_0), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_0), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_0), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_0), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_4), 0x0030, 6, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_0), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_0), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_0), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_0), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_0), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_0), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_0), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_0), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_4), 0x0070, 6, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_0), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_0), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_0), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_0), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_0), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_0), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_0), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_0), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_4), 0x00b0, 8, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_0), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_0), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0100_0), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_0), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_0), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_0), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_0), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_0), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_4), 0x0130, 4, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_0), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_0), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_0), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_4), 0x013b, 4, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_0), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_0), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_0), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_0), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_0), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_0), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_0), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_4), 0x0170, 4, { 4, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_0), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_0), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_0), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_0), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_0), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_0), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_0), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_0), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_4), 0x01b0, 4, { 4, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_0), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_0), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_0), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_0), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_0), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_0), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_0), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_0), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_4), 0x01f0, 4, { 4, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_0), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_0), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_0), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_0), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_0), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_0), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_0), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_4), 0x0230, 6, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_0), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_0), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_0), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_0), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_0), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_0), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_0), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_0), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_4), 0x0270, 6, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_0), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_0), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_0), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_0), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_0), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_0), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_0), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_0), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_4), 0x02b0, 8, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_0), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_0), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0400_0), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_0), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_0), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_0), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_0), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_4), 0x0430, 6, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_0), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_0), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_0), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_0), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_0), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_0), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_0), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_4), 0x0470, 6, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_0), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_0), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_0), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_0), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_0), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_0), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_0), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_4), 0x04b0, 8, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_0), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_0), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0600_0), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_0), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_0), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_0), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_0), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_4), 0x0630, 6, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_0), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_0), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_0), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_0), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_0), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_0), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_0), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_4), 0x0670, 6, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_0), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_0), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_0), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_0), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_0), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_0), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_0), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_4), 0x06b0, 8, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_0), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_0), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0800_0), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_0), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_0), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_0), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_0), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_4), 0x0830, 6, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_0), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_0), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_0), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_4), 0x083b, 6, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_0), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_0), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_0), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_0), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_0), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_4), 0x0870, 6, { 4, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_0), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_0), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_0), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_0), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_0), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_0), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_0), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_4), 0x08b0, 6, { 4, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_0), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_0), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_0), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_0), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_0), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_0), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_0), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_4), 0x08f0, 6, { 4, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_0), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_0), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_0), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_0), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_0), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_0), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_0), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_4), 0x0a30, 6, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_0), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_0), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_0), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_0), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_0), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_0), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_0), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_0), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_4), 0x0a70, 6, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_0), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_0), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_0), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_0), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_0), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_0), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_0), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_0), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_4), 0x0ab0, 8, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_0), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_0), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0c00_0), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_0), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_0), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_0), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_0), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_4), 0x0c30, 6, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_0), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_0), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c40_0), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_0), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_0), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_0), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_0), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_4), 0x0c70, 6, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_0), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_0), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c80_0), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_0), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_0), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_0), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_0), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_4), 0x0cb0, 8, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_0), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_0), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_1000_0), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_0), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_0), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_0), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_0), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_4), 0x1030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_0), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_0), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_0), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_4), 0x103b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_0), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_0), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_0), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_0), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_0), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_0), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_4), 0x10b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_0), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_0), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_0), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_4), 0x10bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_0), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_0), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_0), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_0), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_0), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_0), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_4), 0x10f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_0), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_0), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_0), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_4), 0x10fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_0), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_0), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_0), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_0), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_0), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_0), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_4), 0x1130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_0), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_0), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_0), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_4), 0x113b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_0), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_0), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_0), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_0), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_0), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_0), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_4), 0x1170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_0), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_0), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_0), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_4), 0x117b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_0), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_4), 0x1180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_4), 0x1190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_4), 0x1198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_4), 0x11a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_4), 0x11a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_4), 0x11b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_4), 0x11b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_4), 0x11b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_4), 0x11ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_4), 0x11bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_4), 0x11bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_0), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_0), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_0), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_0), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_0), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_4), 0x11f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_0), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_0), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_0), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_4), 0x11fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_0), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_0), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_0), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_0), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_0), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_0), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_4), 0x13f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_0), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_0), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_0), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_4), 0x13fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_0), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_0), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_0), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_0), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_0), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_0), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_0), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_4), 0x2030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_0), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_0), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_0), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_4), 0x203b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_0), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_0), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_0), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_0), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_0), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_0), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_0), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_4), 0x2070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_0), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_0), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_0), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_4), 0x207b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_0), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_0), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_0), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_0), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_0), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_0), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_0), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_4), 0x20b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_0), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_0), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_0), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_4), 0x20bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_0), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_0), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_0), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_0), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_0), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_0), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_0), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_4), 0x20f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_0), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_0), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_0), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_4), 0x20fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_0), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_0), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_0), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_0), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_0), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_0), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_0), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_4), 0x2130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_0), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_0), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_0), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_4), 0x213b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_0), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_0), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_0), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_0), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_0), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_0), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_0), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_4), 0x2170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_0), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_0), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_0), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_4), 0x217b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_0), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_4), 0x2180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_4), 0x2188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_4), 0x2190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_4), 0x2198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_4), 0x21a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_4), 0x21a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_4), 0x21b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_4), 0x21b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_4), 0x21b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_4), 0x21ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_4), 0x21bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_4), 0x21bc, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_0), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_0), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_0), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_0), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_0), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_0), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_4), 0x21f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_0), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_0), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_0), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_4), 0x21fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_0), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_0), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_0), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_0), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_0), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_0), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_0), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_4), 0x23f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_0), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_0), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_0), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_4), 0x23fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_0), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_0), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_0), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_0), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_0), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_0), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_0), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_4), 0x3030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_0), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_0), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_0), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_4), 0x303b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_0), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_0), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_0), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_0), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_0), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_0), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_0), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_4), 0x3070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_0), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_0), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_0), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_4), 0x307b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_0), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_0), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_0), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_0), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_0), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_0), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_0), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_4), 0x30b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_0), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_0), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_0), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_4), 0x30bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_0), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_0), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_0), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_0), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_0), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_0), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_0), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_4), 0x30f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_0), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_0), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_0), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_4), 0x30fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_0), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_0), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_0), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_0), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_0), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_0), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_0), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_4), 0x3130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_0), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_0), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_0), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_4), 0x313b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_0), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_0), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_0), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_0), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_0), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_0), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_0), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_4), 0x3170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_0), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_0), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_0), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_4), 0x317b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_0), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_4), 0x3180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_4), 0x3188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_4), 0x3190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_4), 0x3198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_4), 0x31a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_4), 0x31a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_4), 0x31b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_4), 0x31b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_4), 0x31b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_4), 0x31ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_4), 0x31bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_4), 0x31bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_0), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_0), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_0), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_0), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_0), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_0), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_4), 0x31f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_0), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_0), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_0), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_4), 0x31fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_0), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_0), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_0), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_0), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_0), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_0), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_0), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_4), 0x33f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_0), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_0), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_0), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_4), 0x33fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_0), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_0), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_0), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_0), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_0), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_0), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_4), 0x4030, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_0), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_0), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_0), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_0), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_0), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_0), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_0), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_4), 0x4070, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_0), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_0), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_0), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_0), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_0), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_0), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_0), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_4), 0x40b0, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_0), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_0), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_0), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_0), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_0), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_0), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_0), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_4), 0x40f0, 4, { 4, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_0), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_0), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4180_0), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_0), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_0), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_0), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_0), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_4), 0x41b0, 4, { 4, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_0), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_0), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_0), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_4), 0x41bb, 4, { 4, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_0), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_0), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_0), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_4), 0x41f0, 4, { 4, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_0), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_0), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_0), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_4), 0x41fb, 4, { 4, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_0), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_0), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_0), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_0), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_0), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_4), 0x4230, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_0), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_0), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_0), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_0), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_0), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_0), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_0), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_4), 0x4270, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_0), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_0), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_0), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_0), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_0), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_0), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_0), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_4), 0x42b0, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_0), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_0), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42c0_0), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d0_0), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d8_0), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e0_0), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e8_0), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f0_4), 0x42f0, 4, { 4, 0 }, 0 }, /* MVSR2 */
+#endif
+{ CPUFUNC(op_42f8_0), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f9_0), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4400_0), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_0), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_0), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_0), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_0), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_4), 0x4430, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_0), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_0), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_0), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_0), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_0), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_0), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_0), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_4), 0x4470, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_0), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_0), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_0), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_0), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_0), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_0), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_0), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_4), 0x44b0, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_0), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_0), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_0), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_0), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_0), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_0), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_0), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_4), 0x44f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_0), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_0), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_0), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_4), 0x44fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_0), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_0), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_0), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_0), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_0), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_0), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_4), 0x4630, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_0), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_0), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_0), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_0), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_0), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_0), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_0), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_4), 0x4670, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_0), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_0), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_0), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_0), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_0), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_0), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_0), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_4), 0x46b0, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_0), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_0), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_0), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_0), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_0), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_0), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_0), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_4), 0x46f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_0), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_0), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_0), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_4), 0x46fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_0), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_2), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4810_2), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_2), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_2), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_2), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_4), 0x4830, 4, { 4, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_2), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_2), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_0), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ CPUFUNC(op_4850_0), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_0), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_4), 0x4870, 4, { 4, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_0), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_0), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_0), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_4), 0x487b, 4, { 4, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_0), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_0), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_0), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_0), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_4), 0x48b0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_0), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_0), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_0), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_0), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_0), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_0), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_4), 0x48f0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_0), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_0), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_4a00_0), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_0), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_0), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_0), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_0), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_4), 0x4a30, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_0), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_0), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a40_0), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a50_0), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_0), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_0), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_0), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_4), 0x4a70, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_0), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_0), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a80_0), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a90_0), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_0), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_0), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_0), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_4), 0x4ab0, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_0), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_0), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ac0_4), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_4), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_4), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_4), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_4), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_4), 0x4af0, 4, { 4, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_4), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_4), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4c90_0), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_0), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_0), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_4), 0x4cb0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_0), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_0), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_0), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_4), 0x4cbb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_0), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_0), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_0), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_4), 0x4cf0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_0), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_0), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_0), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_4), 0x4cfb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_0), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_0), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_0), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_0), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_0), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_0), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_0), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_0), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_0), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+{ CPUFUNC(op_4e74_0), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+{ CPUFUNC(op_4e75_0), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_0), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_0), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+{ CPUFUNC(op_4e7a_0), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+{ CPUFUNC(op_4e7b_0), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+{ CPUFUNC(op_4e90_0), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_0), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_4), 0x4eb0, 4, { 4, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_0), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_0), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_0), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_4), 0x4ebb, 4, { 4, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_0), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_0), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_4), 0x4ef0, 4, { 4, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_0), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_0), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_0), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_4), 0x4efb, 4, { 4, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_0), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_0), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_0), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_0), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_0), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_4), 0x5030, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_0), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_0), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_0), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_0), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_0), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_0), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_0), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_0), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_4), 0x5070, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_0), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_0), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_0), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_0), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_0), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_0), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_0), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_0), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_4), 0x50b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_0), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_0), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_0), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_0), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_0), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_0), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_0), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_0), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_4), 0x50f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_0), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_0), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5100_0), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_0), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_0), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_0), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_0), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_4), 0x5130, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_0), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_0), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_0), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_0), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_0), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_0), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_0), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_0), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_4), 0x5170, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_0), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_0), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_0), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_0), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_0), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_0), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_0), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_0), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_4), 0x51b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_0), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_0), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_0), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_0), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_0), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_0), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_0), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_0), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_4), 0x51f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_0), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_0), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c0_0), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_0), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_0), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_0), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_0), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_0), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_4), 0x52f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_0), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_0), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c0_0), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_0), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_0), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_0), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_0), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_0), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_4), 0x53f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_0), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_0), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c0_0), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_0), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_0), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_0), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_0), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_0), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_4), 0x54f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_0), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_0), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c0_0), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_0), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_0), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_0), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_0), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_0), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_4), 0x55f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_0), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_0), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c0_0), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_0), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_0), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_0), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_0), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_0), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_4), 0x56f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_0), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_0), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c0_0), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_0), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_0), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_0), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_0), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_0), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_4), 0x57f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_0), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_0), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c0_0), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_0), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_0), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_0), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_0), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_0), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_4), 0x58f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_0), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_0), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c0_0), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_0), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_0), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_0), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_0), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_0), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_4), 0x59f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_0), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_0), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac0_0), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_0), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_0), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_0), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_0), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_0), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_4), 0x5af0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_0), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_0), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc0_0), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_0), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_0), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_0), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_0), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_0), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_4), 0x5bf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_0), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_0), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc0_0), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_0), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_0), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_0), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_0), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_0), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_4), 0x5cf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_0), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_0), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc0_0), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_0), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_0), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_0), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_0), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_0), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_4), 0x5df0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_0), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_0), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec0_0), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_0), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_0), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_0), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_0), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_0), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_4), 0x5ef0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_0), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_0), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc0_0), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_0), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_0), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_0), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_0), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_0), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_4), 0x5ff0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_0), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_0), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_6000_0), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_0), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_4), 0x60ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6100_0), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_0), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_4), 0x61ff, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_0), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_0), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_4), 0x62ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6300_0), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_0), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_4), 0x63ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6400_0), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_0), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_4), 0x64ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6500_0), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_0), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_4), 0x65ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6600_0), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_0), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_4), 0x66ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6700_0), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_0), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_4), 0x67ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6800_0), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_0), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_4), 0x68ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6900_0), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_0), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_4), 0x69ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6a00_0), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_0), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_4), 0x6aff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6b00_0), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_0), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_4), 0x6bff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6c00_0), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_0), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_4), 0x6cff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6d00_0), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_0), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_4), 0x6dff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6e00_0), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_0), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_4), 0x6eff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6f00_0), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_0), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_4), 0x6fff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_7000_0), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_0), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_0), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_0), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_0), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_0), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_4), 0x8030, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_0), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_0), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_0), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_4), 0x803b, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_0), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_0), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_0), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_0), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_0), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_0), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_4), 0x8070, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_0), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_0), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_0), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_4), 0x807b, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_0), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_0), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_0), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_0), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_0), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_0), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_4), 0x80b0, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_0), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_0), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_0), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_4), 0x80bb, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_0), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_0), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_0), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_0), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_0), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_0), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_4), 0x80f0, 4, { 4, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_0), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_0), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_0), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_4), 0x80fb, 4, { 4, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_0), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_2), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_2), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_0), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_0), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_0), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_0), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_4), 0x8130, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_0), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_0), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8150_0), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_0), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_0), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_0), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_4), 0x8170, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_0), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_0), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8190_0), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_0), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_0), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_0), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_4), 0x81b0, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_0), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_0), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_0), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_0), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_0), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_0), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_0), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_4), 0x81f0, 4, { 4, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_0), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_0), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_0), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_4), 0x81fb, 4, { 4, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_0), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_0), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_0), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_0), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_0), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_0), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_4), 0x9030, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_0), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_0), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_0), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_4), 0x903b, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_0), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_0), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_0), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_0), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_0), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_0), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_0), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_4), 0x9070, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_0), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_0), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_0), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_4), 0x907b, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_0), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_0), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_0), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_0), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_0), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_0), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_0), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_4), 0x90b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_0), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_0), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_0), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_4), 0x90bb, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_0), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_0), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_0), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_0), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_0), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_0), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_0), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_4), 0x90f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_0), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_0), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_0), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_4), 0x90fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_0), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_0), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_0), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_0), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_0), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_0), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_0), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_4), 0x9130, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_0), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_0), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_0), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_0), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_0), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_0), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_0), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_0), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_4), 0x9170, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_0), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_0), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_0), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_0), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_0), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_0), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_0), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_0), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_4), 0x91b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_0), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_0), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_0), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_0), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_0), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_0), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_0), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_0), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_4), 0x91f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_0), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_0), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_0), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_4), 0x91fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_0), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_0), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_0), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_0), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_0), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_0), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_4), 0xb030, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_0), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_0), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_0), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_4), 0xb03b, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_0), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_0), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_0), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_0), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_0), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_0), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_0), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_4), 0xb070, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_0), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_0), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_0), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_4), 0xb07b, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_0), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_0), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_0), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_0), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_0), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_0), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_0), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_4), 0xb0b0, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_0), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_0), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_0), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_4), 0xb0bb, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_0), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_0), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_0), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_0), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_0), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_0), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_0), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_4), 0xb0f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_0), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_0), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_0), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_4), 0xb0fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_0), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_0), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_0), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_0), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_0), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_0), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_0), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_4), 0xb130, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_0), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_0), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_0), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_0), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_0), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_0), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_0), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_0), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_4), 0xb170, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_0), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_0), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_0), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_0), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_0), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_0), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_0), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_0), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_4), 0xb1b0, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_0), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_0), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_0), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_0), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_0), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_0), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_0), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_0), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_4), 0xb1f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_0), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_0), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_0), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_4), 0xb1fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_0), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_0), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_0), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_0), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_0), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_0), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_4), 0xc030, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_0), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_0), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_0), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_4), 0xc03b, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_0), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_0), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_0), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_0), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_0), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_0), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_4), 0xc070, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_0), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_0), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_0), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_4), 0xc07b, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_0), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_0), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_0), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_0), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_0), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_0), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_4), 0xc0b0, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_0), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_0), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_0), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_4), 0xc0bb, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_0), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_0), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_0), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_0), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_0), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_0), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_4), 0xc0f0, 4, { 4, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_0), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_0), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_0), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_4), 0xc0fb, 4, { 4, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_0), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_2), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_2), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_0), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_0), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_0), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_0), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_4), 0xc130, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_0), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_0), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_0), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_0), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_0), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_0), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_0), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_0), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_4), 0xc170, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_0), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_0), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_0), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_0), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_0), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_0), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_0), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_4), 0xc1b0, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_0), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_0), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_0), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_0), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_0), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_0), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_0), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_4), 0xc1f0, 4, { 4, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_0), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_0), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_0), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_4), 0xc1fb, 4, { 4, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_0), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_0), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_0), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_0), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_0), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_0), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_4), 0xd030, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_0), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_0), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_0), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_4), 0xd03b, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_0), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_0), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_0), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_0), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_0), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_0), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_0), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_4), 0xd070, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_0), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_0), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_0), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_4), 0xd07b, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_0), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_0), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_0), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_0), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_0), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_0), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_0), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_4), 0xd0b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_0), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_0), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_0), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_4), 0xd0bb, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_0), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_0), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_0), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_0), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_0), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_0), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_0), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_4), 0xd0f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_0), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_0), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_0), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_4), 0xd0fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_0), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_0), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_0), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_0), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_0), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_0), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_0), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_4), 0xd130, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_0), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_0), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_0), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_0), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_0), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_0), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_0), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_0), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_4), 0xd170, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_0), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_0), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_0), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_0), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_0), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_0), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_0), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_0), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_4), 0xd1b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_0), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_0), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_0), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_0), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_0), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_0), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_0), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_0), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_4), 0xd1f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_0), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_0), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_0), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_4), 0xd1fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_0), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_0), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_0), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_0), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_0), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_0), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_0), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_0), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_0), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_0), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_0), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_0), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_0), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_0), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_0), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_0), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_0), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_0), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_0), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_0), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_0), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_0), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_0), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_0), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_0), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_0), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_0), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_0), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_0), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_4), 0xe0f0, 4, { 4, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_0), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_0), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_0), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_0), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_0), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_0), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_0), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_0), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_0), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_0), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_0), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_0), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_0), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_0), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_0), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_0), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_0), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_0), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_0), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_0), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_0), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_0), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_0), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_0), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_0), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_0), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_0), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_0), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_0), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_0), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_4), 0xe1f0, 4, { 4, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_0), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_0), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_0), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_0), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_0), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_0), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_4), 0xe2f0, 4, { 4, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_0), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_0), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_0), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_0), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_0), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_0), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_4), 0xe3f0, 4, { 4, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_0), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_0), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_0), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_0), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_0), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_0), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_4), 0xe4f0, 4, { 4, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_0), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_0), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_0), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_0), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_0), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_0), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_4), 0xe5f0, 4, { 4, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_0), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_0), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_0), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_0), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_0), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_0), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_4), 0xe6f0, 4, { 4, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_0), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_0), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_0), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_0), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_0), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_0), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_4), 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_0), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_0), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_5)[] = {
+{ CPUFUNC(op_0000_0), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_0), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_0), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_0), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_0), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_4), 0x0030, 6, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_0), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_0), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_0), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_0), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_0), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_0), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_0), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_0), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_4), 0x0070, 6, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_0), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_0), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_0), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_0), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_0), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_0), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_0), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_0), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_4), 0x00b0, 8, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_0), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_0), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0100_0), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_0), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_0), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_0), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_0), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_0), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_4), 0x0130, 4, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_0), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_0), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_0), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_4), 0x013b, 4, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_0), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_0), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_0), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_0), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_0), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_0), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_0), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_4), 0x0170, 4, { 4, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_0), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_0), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_0), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_0), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_0), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_0), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_0), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_0), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_4), 0x01b0, 4, { 4, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_0), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_0), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_0), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_0), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_0), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_0), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_0), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_0), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_4), 0x01f0, 4, { 4, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_0), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_0), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_0), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_0), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_0), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_0), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_0), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_4), 0x0230, 6, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_0), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_0), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_0), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_0), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_0), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_0), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_0), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_0), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_4), 0x0270, 6, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_0), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_0), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_0), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_0), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_0), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_0), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_0), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_0), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_4), 0x02b0, 8, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_0), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_0), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0400_0), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_0), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_0), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_0), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_0), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_4), 0x0430, 6, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_0), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_0), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_0), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_0), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_0), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_0), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_0), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_4), 0x0470, 6, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_0), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_0), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_0), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_0), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_0), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_0), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_0), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_4), 0x04b0, 8, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_0), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_0), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0600_0), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_0), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_0), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_0), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_0), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_4), 0x0630, 6, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_0), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_0), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_0), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_0), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_0), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_0), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_0), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_4), 0x0670, 6, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_0), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_0), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_0), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_0), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_0), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_0), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_0), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_4), 0x06b0, 8, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_0), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_0), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0800_0), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_0), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_0), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_0), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_0), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_4), 0x0830, 6, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_0), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_0), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_0), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_4), 0x083b, 6, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_0), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_0), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_0), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_0), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_0), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_4), 0x0870, 6, { 4, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_0), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_0), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_0), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_0), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_0), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_0), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_0), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_4), 0x08b0, 6, { 4, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_0), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_0), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_0), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_0), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_0), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_0), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_0), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_4), 0x08f0, 6, { 4, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_0), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_0), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_0), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_0), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_0), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_0), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_0), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_4), 0x0a30, 6, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_0), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_0), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_0), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_0), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_0), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_0), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_0), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_0), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_4), 0x0a70, 6, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_0), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_0), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_0), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_0), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_0), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_0), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_0), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_0), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_4), 0x0ab0, 8, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_0), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_0), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0c00_0), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_0), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_0), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_0), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_0), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_4), 0x0c30, 6, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_0), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_0), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c40_0), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_0), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_0), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_0), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_0), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_4), 0x0c70, 6, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_0), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_0), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c80_0), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_0), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_0), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_0), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_0), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_4), 0x0cb0, 8, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_0), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_0), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_1000_0), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_0), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_0), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_0), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_0), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_4), 0x1030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_0), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_0), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_0), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_4), 0x103b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_0), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_0), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_0), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_0), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_0), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_0), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_4), 0x10b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_0), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_0), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_0), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_4), 0x10bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_0), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_0), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_0), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_0), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_0), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_0), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_4), 0x10f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_0), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_0), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_0), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_4), 0x10fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_0), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_0), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_0), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_0), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_0), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_0), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_4), 0x1130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_0), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_0), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_0), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_4), 0x113b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_0), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_0), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_0), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_0), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_0), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_0), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_4), 0x1170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_0), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_0), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_0), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_4), 0x117b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_0), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_4), 0x1180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_4), 0x1190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_4), 0x1198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_4), 0x11a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_4), 0x11a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_4), 0x11b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_4), 0x11b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_4), 0x11b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_4), 0x11ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_4), 0x11bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_4), 0x11bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_0), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_0), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_0), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_0), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_0), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_4), 0x11f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_0), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_0), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_0), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_4), 0x11fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_0), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_0), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_0), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_0), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_0), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_0), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_4), 0x13f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_0), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_0), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_0), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_4), 0x13fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_0), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_0), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_0), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_0), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_0), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_0), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_0), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_4), 0x2030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_0), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_0), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_0), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_4), 0x203b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_0), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_0), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_0), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_0), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_0), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_0), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_0), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_4), 0x2070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_0), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_0), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_0), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_4), 0x207b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_0), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_0), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_0), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_0), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_0), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_0), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_0), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_4), 0x20b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_0), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_0), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_0), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_4), 0x20bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_0), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_0), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_0), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_0), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_0), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_0), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_0), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_4), 0x20f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_0), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_0), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_0), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_4), 0x20fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_0), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_0), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_0), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_0), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_0), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_0), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_0), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_4), 0x2130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_0), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_0), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_0), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_4), 0x213b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_0), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_0), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_0), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_0), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_0), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_0), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_0), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_4), 0x2170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_0), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_0), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_0), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_4), 0x217b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_0), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_4), 0x2180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_4), 0x2188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_4), 0x2190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_4), 0x2198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_4), 0x21a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_4), 0x21a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_4), 0x21b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_4), 0x21b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_4), 0x21b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_4), 0x21ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_4), 0x21bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_4), 0x21bc, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_0), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_0), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_0), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_0), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_0), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_0), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_4), 0x21f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_0), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_0), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_0), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_4), 0x21fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_0), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_0), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_0), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_0), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_0), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_0), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_0), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_4), 0x23f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_0), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_0), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_0), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_4), 0x23fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_0), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_0), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_0), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_0), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_0), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_0), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_0), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_4), 0x3030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_0), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_0), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_0), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_4), 0x303b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_0), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_0), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_0), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_0), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_0), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_0), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_0), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_4), 0x3070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_0), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_0), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_0), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_4), 0x307b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_0), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_0), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_0), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_0), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_0), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_0), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_0), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_4), 0x30b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_0), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_0), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_0), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_4), 0x30bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_0), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_0), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_0), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_0), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_0), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_0), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_0), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_4), 0x30f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_0), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_0), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_0), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_4), 0x30fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_0), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_0), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_0), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_0), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_0), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_0), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_0), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_4), 0x3130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_0), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_0), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_0), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_4), 0x313b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_0), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_0), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_0), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_0), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_0), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_0), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_0), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_4), 0x3170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_0), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_0), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_0), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_4), 0x317b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_0), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_4), 0x3180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_4), 0x3188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_4), 0x3190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_4), 0x3198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_4), 0x31a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_4), 0x31a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_4), 0x31b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_4), 0x31b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_4), 0x31b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_4), 0x31ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_4), 0x31bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_4), 0x31bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_0), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_0), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_0), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_0), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_0), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_0), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_4), 0x31f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_0), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_0), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_0), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_4), 0x31fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_0), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_0), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_0), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_0), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_0), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_0), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_0), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_4), 0x33f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_0), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_0), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_0), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_4), 0x33fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_0), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_0), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_0), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_0), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_0), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_0), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_4), 0x4030, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_0), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_0), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_0), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_0), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_0), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_0), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_0), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_4), 0x4070, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_0), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_0), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_0), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_0), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_0), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_0), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_0), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_4), 0x40b0, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_0), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_0), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_5), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_5), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_5), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_5), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_5), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_5), 0x40f0, 4, { 4, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_5), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_5), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4180_0), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_0), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_0), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_0), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_0), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_4), 0x41b0, 4, { 4, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_0), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_0), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_0), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_4), 0x41bb, 4, { 4, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_0), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_0), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_0), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_4), 0x41f0, 4, { 4, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_0), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_0), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_0), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_4), 0x41fb, 4, { 4, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_5), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_5), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_5), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_5), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_5), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_5), 0x4230, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_5), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_5), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_5), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_5), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_5), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_5), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_5), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_5), 0x4270, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_5), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_5), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_5), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_5), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_5), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_5), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_5), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_5), 0x42b0, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_5), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_5), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4400_0), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_0), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_0), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_0), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_0), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_4), 0x4430, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_0), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_0), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_0), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_0), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_0), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_0), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_0), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_4), 0x4470, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_0), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_0), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_0), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_0), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_0), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_0), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_0), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_4), 0x44b0, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_0), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_0), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_0), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_0), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_0), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_0), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_0), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_4), 0x44f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_0), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_0), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_0), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_4), 0x44fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_0), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_0), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_0), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_0), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_0), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_0), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_4), 0x4630, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_0), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_0), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_0), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_0), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_0), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_0), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_0), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_4), 0x4670, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_0), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_0), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_0), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_0), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_0), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_0), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_0), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_4), 0x46b0, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_0), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_0), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_0), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_0), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_0), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_0), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_0), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_4), 0x46f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_0), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_0), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_0), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_4), 0x46fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_0), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_2), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4810_2), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_2), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_2), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_2), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_4), 0x4830, 4, { 4, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_2), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_2), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_0), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ CPUFUNC(op_4850_0), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_0), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_4), 0x4870, 4, { 4, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_0), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_0), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_0), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_4), 0x487b, 4, { 4, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_0), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_0), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_0), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_0), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_4), 0x48b0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_0), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_0), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_0), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_0), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_0), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_0), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_4), 0x48f0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_0), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_0), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_4a00_0), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_0), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_0), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_0), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_0), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_4), 0x4a30, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_0), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_0), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a40_0), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a50_0), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_0), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_0), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_0), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_4), 0x4a70, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_0), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_0), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a80_0), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a90_0), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_0), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_0), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_0), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_4), 0x4ab0, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_0), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_0), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ac0_4), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_4), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_4), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_4), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_4), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_4), 0x4af0, 4, { 4, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_4), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_4), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4c90_0), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_0), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_0), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_4), 0x4cb0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_0), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_0), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_0), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_4), 0x4cbb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_0), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_0), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_0), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_4), 0x4cf0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_0), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_0), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_0), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_4), 0x4cfb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_0), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_0), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_0), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_0), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_0), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_0), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_0), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_0), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_5), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+{ CPUFUNC(op_4e75_0), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_0), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_0), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+{ CPUFUNC(op_4e90_0), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_0), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_4), 0x4eb0, 4, { 4, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_0), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_0), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_0), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_4), 0x4ebb, 4, { 4, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_0), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_0), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_4), 0x4ef0, 4, { 4, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_0), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_0), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_0), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_4), 0x4efb, 4, { 4, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_0), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_0), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_0), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_0), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_0), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_4), 0x5030, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_0), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_0), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_0), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_0), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_0), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_0), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_0), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_0), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_4), 0x5070, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_0), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_0), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_0), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_0), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_0), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_0), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_0), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_0), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_4), 0x50b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_0), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_0), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_5), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_0), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_5), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_5), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_5), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_5), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_5), 0x50f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_5), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_5), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5100_0), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_0), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_0), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_0), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_0), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_4), 0x5130, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_0), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_0), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_0), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_0), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_0), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_0), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_0), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_0), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_4), 0x5170, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_0), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_0), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_0), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_0), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_0), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_0), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_0), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_0), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_4), 0x51b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_0), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_0), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_5), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_0), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_5), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_5), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_5), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_5), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_5), 0x51f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_5), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_5), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c0_5), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_0), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_5), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_5), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_5), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_5), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_5), 0x52f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_5), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_5), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c0_5), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_0), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_5), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_5), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_5), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_5), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_5), 0x53f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_5), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_5), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c0_5), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_0), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_5), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_5), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_5), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_5), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_5), 0x54f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_5), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_5), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c0_5), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_0), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_5), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_5), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_5), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_5), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_5), 0x55f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_5), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_5), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c0_5), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_0), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_5), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_5), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_5), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_5), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_5), 0x56f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_5), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_5), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c0_5), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_0), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_5), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_5), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_5), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_5), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_5), 0x57f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_5), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_5), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c0_5), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_0), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_5), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_5), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_5), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_5), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_5), 0x58f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_5), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_5), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c0_5), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_0), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_5), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_5), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_5), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_5), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_5), 0x59f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_5), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_5), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac0_5), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_0), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_5), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_5), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_5), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_5), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_5), 0x5af0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_5), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_5), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc0_5), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_0), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_5), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_5), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_5), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_5), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_5), 0x5bf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_5), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_5), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc0_5), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_0), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_5), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_5), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_5), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_5), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_5), 0x5cf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_5), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_5), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc0_5), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_0), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_5), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_5), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_5), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_5), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_5), 0x5df0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_5), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_5), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec0_5), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_0), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_5), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_5), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_5), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_5), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_5), 0x5ef0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_5), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_5), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc0_5), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_0), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_5), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_5), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_5), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_5), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_5), 0x5ff0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_5), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_5), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_6000_0), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_0), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_4), 0x60ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6100_0), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_0), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_4), 0x61ff, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_0), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_0), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_4), 0x62ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6300_0), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_0), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_4), 0x63ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6400_0), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_0), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_4), 0x64ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6500_0), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_0), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_4), 0x65ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6600_0), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_0), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_4), 0x66ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6700_0), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_0), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_4), 0x67ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6800_0), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_0), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_4), 0x68ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6900_0), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_0), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_4), 0x69ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6a00_0), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_0), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_4), 0x6aff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6b00_0), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_0), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_4), 0x6bff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6c00_0), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_0), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_4), 0x6cff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6d00_0), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_0), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_4), 0x6dff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6e00_0), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_0), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_4), 0x6eff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6f00_0), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_0), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_4), 0x6fff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_7000_0), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_0), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_0), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_0), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_0), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_0), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_4), 0x8030, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_0), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_0), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_0), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_4), 0x803b, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_0), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_0), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_0), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_0), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_0), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_0), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_4), 0x8070, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_0), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_0), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_0), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_4), 0x807b, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_0), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_0), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_0), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_0), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_0), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_0), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_4), 0x80b0, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_0), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_0), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_0), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_4), 0x80bb, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_0), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_0), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_0), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_0), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_0), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_0), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_4), 0x80f0, 4, { 4, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_0), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_0), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_0), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_4), 0x80fb, 4, { 4, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_0), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_2), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_2), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_0), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_0), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_0), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_0), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_4), 0x8130, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_0), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_0), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8150_0), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_0), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_0), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_0), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_4), 0x8170, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_0), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_0), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8190_0), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_0), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_0), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_0), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_4), 0x81b0, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_0), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_0), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_0), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_0), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_0), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_0), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_0), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_4), 0x81f0, 4, { 4, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_0), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_0), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_0), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_4), 0x81fb, 4, { 4, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_0), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_0), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_0), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_0), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_0), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_0), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_4), 0x9030, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_0), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_0), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_0), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_4), 0x903b, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_0), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_0), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_0), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_0), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_0), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_0), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_0), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_4), 0x9070, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_0), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_0), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_0), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_4), 0x907b, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_0), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_0), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_0), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_0), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_0), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_0), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_0), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_4), 0x90b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_0), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_0), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_0), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_4), 0x90bb, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_0), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_0), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_0), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_0), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_0), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_0), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_0), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_4), 0x90f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_0), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_0), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_0), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_4), 0x90fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_0), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_0), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_0), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_0), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_0), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_0), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_0), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_4), 0x9130, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_0), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_0), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_0), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_0), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_0), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_0), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_0), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_0), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_4), 0x9170, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_0), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_0), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_0), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_0), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_0), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_0), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_0), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_0), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_4), 0x91b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_0), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_0), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_0), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_0), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_0), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_0), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_0), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_0), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_4), 0x91f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_0), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_0), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_0), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_4), 0x91fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_0), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_0), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_0), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_0), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_0), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_0), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_4), 0xb030, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_0), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_0), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_0), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_4), 0xb03b, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_0), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_0), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_0), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_0), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_0), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_0), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_0), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_4), 0xb070, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_0), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_0), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_0), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_4), 0xb07b, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_0), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_0), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_0), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_0), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_0), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_0), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_0), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_4), 0xb0b0, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_0), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_0), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_0), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_4), 0xb0bb, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_0), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_0), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_0), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_0), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_0), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_0), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_0), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_4), 0xb0f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_0), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_0), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_0), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_4), 0xb0fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_0), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_0), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_0), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_0), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_0), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_0), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_0), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_4), 0xb130, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_0), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_0), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_0), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_0), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_0), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_0), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_0), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_0), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_4), 0xb170, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_0), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_0), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_0), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_0), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_0), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_0), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_0), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_0), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_4), 0xb1b0, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_0), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_0), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_0), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_0), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_0), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_0), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_0), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_0), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_4), 0xb1f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_0), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_0), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_0), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_4), 0xb1fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_0), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_0), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_0), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_0), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_0), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_0), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_4), 0xc030, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_0), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_0), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_0), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_4), 0xc03b, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_0), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_0), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_0), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_0), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_0), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_0), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_4), 0xc070, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_0), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_0), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_0), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_4), 0xc07b, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_0), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_0), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_0), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_0), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_0), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_0), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_4), 0xc0b0, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_0), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_0), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_0), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_4), 0xc0bb, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_0), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_0), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_0), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_0), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_0), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_0), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_4), 0xc0f0, 4, { 4, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_0), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_0), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_0), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_4), 0xc0fb, 4, { 4, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_0), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_2), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_2), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_0), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_0), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_0), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_0), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_4), 0xc130, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_0), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_0), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_0), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_0), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_0), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_0), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_0), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_0), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_4), 0xc170, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_0), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_0), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_0), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_0), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_0), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_0), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_0), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_4), 0xc1b0, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_0), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_0), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_0), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_0), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_0), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_0), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_0), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_4), 0xc1f0, 4, { 4, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_0), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_0), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_0), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_4), 0xc1fb, 4, { 4, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_0), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_0), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_0), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_0), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_0), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_0), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_4), 0xd030, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_0), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_0), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_0), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_4), 0xd03b, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_0), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_0), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_0), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_0), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_0), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_0), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_0), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_4), 0xd070, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_0), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_0), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_0), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_4), 0xd07b, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_0), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_0), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_0), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_0), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_0), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_0), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_0), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_4), 0xd0b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_0), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_0), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_0), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_4), 0xd0bb, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_0), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_0), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_0), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_0), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_0), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_0), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_0), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_4), 0xd0f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_0), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_0), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_0), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_4), 0xd0fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_0), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_0), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_0), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_0), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_0), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_0), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_0), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_4), 0xd130, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_0), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_0), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_0), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_0), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_0), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_0), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_0), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_0), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_4), 0xd170, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_0), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_0), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_0), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_0), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_0), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_0), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_0), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_0), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_4), 0xd1b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_0), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_0), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_0), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_0), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_0), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_0), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_0), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_0), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_4), 0xd1f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_0), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_0), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_0), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_4), 0xd1fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_0), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_0), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_0), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_0), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_0), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_0), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_0), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_0), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_0), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_0), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_0), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_0), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_0), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_0), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_0), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_0), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_0), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_0), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_0), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_0), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_0), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_0), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_0), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_0), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_0), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_0), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_0), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_0), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_0), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_4), 0xe0f0, 4, { 4, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_0), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_0), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_0), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_0), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_0), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_0), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_0), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_0), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_0), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_0), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_0), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_0), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_0), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_0), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_0), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_0), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_0), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_0), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_0), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_0), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_0), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_0), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_0), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_0), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_0), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_0), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_0), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_0), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_0), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_0), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_4), 0xe1f0, 4, { 4, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_0), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_0), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_0), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_0), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_0), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_0), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_4), 0xe2f0, 4, { 4, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_0), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_0), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_0), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_0), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_0), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_0), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_4), 0xe3f0, 4, { 4, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_0), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_0), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_0), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_0), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_0), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_0), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_4), 0xe4f0, 4, { 4, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_0), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_0), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_0), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_0), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_0), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_0), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_4), 0xe5f0, 4, { 4, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_0), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_0), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_0), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_0), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_0), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_0), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_4), 0xe6f0, 4, { 4, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_0), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_0), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_0), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_0), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_0), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_0), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_4), 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_0), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_0), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#ifdef CPUEMU_11
+const struct cputbl CPUFUNC(op_smalltbl_11)[] = {
+{ CPUFUNC(op_0000_11), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_11), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_11), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_11), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_11), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_11), 0x0030, 6, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_11), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_11), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_11), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_11), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_11), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_11), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_11), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_11), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_11), 0x0070, 6, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_11), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_11), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_11), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_11), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_11), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_11), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_11), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_11), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_11), 0x00b0, 8, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_11), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_11), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0100_11), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_11), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_11), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_11), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_11), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_11), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_11), 0x0130, 4, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_11), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_11), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_11), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_11), 0x013b, 4, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_11), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_11), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_11), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_11), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_11), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_11), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_11), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_11), 0x0170, 4, { 4, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_11), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_11), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_11), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_11), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_11), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_11), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_11), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_11), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_11), 0x01b0, 4, { 4, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_11), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_11), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_11), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_11), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_11), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_11), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_11), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_11), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_11), 0x01f0, 4, { 4, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_11), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_11), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_11), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_11), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_11), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_11), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_11), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_11), 0x0230, 6, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_11), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_11), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_11), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_11), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_11), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_11), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_11), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_11), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_11), 0x0270, 6, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_11), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_11), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_11), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_11), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_11), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_11), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_11), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_11), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_11), 0x02b0, 8, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_11), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_11), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0400_11), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_11), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_11), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_11), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_11), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_11), 0x0430, 6, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_11), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_11), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_11), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_11), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_11), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_11), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_11), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_11), 0x0470, 6, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_11), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_11), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_11), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_11), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_11), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_11), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_11), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_11), 0x04b0, 8, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_11), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_11), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0600_11), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_11), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_11), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_11), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_11), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_11), 0x0630, 6, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_11), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_11), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_11), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_11), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_11), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_11), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_11), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_11), 0x0670, 6, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_11), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_11), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_11), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_11), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_11), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_11), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_11), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_11), 0x06b0, 8, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_11), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_11), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0800_11), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_11), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_11), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_11), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_11), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_11), 0x0830, 6, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_11), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_11), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_11), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_11), 0x083b, 6, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_11), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_11), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_11), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_11), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_11), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_11), 0x0870, 6, { 4, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_11), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_11), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_11), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_11), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_11), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_11), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_11), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_11), 0x08b0, 6, { 4, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_11), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_11), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_11), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_11), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_11), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_11), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_11), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_11), 0x08f0, 6, { 4, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_11), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_11), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_11), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_11), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_11), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_11), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_11), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_11), 0x0a30, 6, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_11), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_11), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_11), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_11), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_11), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_11), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_11), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_11), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_11), 0x0a70, 6, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_11), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_11), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_11), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_11), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_11), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_11), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_11), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_11), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_11), 0x0ab0, 8, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_11), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_11), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0c00_11), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_11), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_11), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_11), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_11), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_11), 0x0c30, 6, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_11), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_11), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c40_11), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_11), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_11), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_11), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_11), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_11), 0x0c70, 6, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_11), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_11), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c80_11), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_11), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_11), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_11), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_11), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_11), 0x0cb0, 8, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_11), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_11), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_1000_11), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_11), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_11), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_11), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_11), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_11), 0x1030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_11), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_11), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_11), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_11), 0x103b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_11), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_11), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_11), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_11), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_11), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_11), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_11), 0x10b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_11), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_11), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_11), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_11), 0x10bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_11), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_11), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_11), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_11), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_11), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_11), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_11), 0x10f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_11), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_11), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_11), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_11), 0x10fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_11), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_11), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_11), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_11), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_11), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_11), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_11), 0x1130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_11), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_11), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_11), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_11), 0x113b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_11), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_11), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_11), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_11), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_11), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_11), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_11), 0x1170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_11), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_11), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_11), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_11), 0x117b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_11), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_11), 0x1180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_11), 0x1190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_11), 0x1198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_11), 0x11a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_11), 0x11a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_11), 0x11b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_11), 0x11b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_11), 0x11b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_11), 0x11ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_11), 0x11bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_11), 0x11bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_11), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_11), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_11), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_11), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_11), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_11), 0x11f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_11), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_11), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_11), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_11), 0x11fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_11), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_11), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_11), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_11), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_11), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_11), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_11), 0x13f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_11), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_11), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_11), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_11), 0x13fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_11), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_11), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_11), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_11), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_11), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_11), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_11), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_11), 0x2030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_11), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_11), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_11), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_11), 0x203b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_11), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_11), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_11), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_11), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_11), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_11), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_11), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_11), 0x2070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_11), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_11), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_11), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_11), 0x207b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_11), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_11), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_11), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_11), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_11), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_11), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_11), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_11), 0x20b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_11), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_11), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_11), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_11), 0x20bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_11), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_11), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_11), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_11), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_11), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_11), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_11), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_11), 0x20f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_11), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_11), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_11), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_11), 0x20fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_11), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_11), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_11), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_11), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_11), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_11), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_11), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_11), 0x2130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_11), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_11), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_11), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_11), 0x213b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_11), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_11), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_11), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_11), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_11), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_11), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_11), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_11), 0x2170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_11), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_11), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_11), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_11), 0x217b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_11), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_11), 0x2180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_11), 0x2188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_11), 0x2190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_11), 0x2198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_11), 0x21a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_11), 0x21a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_11), 0x21b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_11), 0x21b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_11), 0x21b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_11), 0x21ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_11), 0x21bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_11), 0x21bc, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_11), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_11), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_11), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_11), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_11), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_11), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_11), 0x21f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_11), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_11), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_11), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_11), 0x21fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_11), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_11), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_11), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_11), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_11), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_11), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_11), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_11), 0x23f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_11), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_11), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_11), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_11), 0x23fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_11), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_11), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_11), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_11), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_11), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_11), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_11), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_11), 0x3030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_11), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_11), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_11), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_11), 0x303b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_11), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_11), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_11), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_11), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_11), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_11), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_11), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_11), 0x3070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_11), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_11), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_11), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_11), 0x307b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_11), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_11), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_11), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_11), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_11), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_11), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_11), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_11), 0x30b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_11), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_11), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_11), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_11), 0x30bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_11), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_11), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_11), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_11), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_11), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_11), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_11), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_11), 0x30f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_11), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_11), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_11), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_11), 0x30fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_11), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_11), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_11), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_11), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_11), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_11), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_11), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_11), 0x3130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_11), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_11), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_11), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_11), 0x313b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_11), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_11), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_11), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_11), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_11), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_11), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_11), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_11), 0x3170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_11), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_11), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_11), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_11), 0x317b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_11), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_11), 0x3180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_11), 0x3188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_11), 0x3190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_11), 0x3198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_11), 0x31a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_11), 0x31a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_11), 0x31b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_11), 0x31b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_11), 0x31b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_11), 0x31ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_11), 0x31bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_11), 0x31bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_11), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_11), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_11), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_11), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_11), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_11), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_11), 0x31f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_11), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_11), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_11), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_11), 0x31fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_11), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_11), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_11), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_11), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_11), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_11), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_11), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_11), 0x33f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_11), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_11), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_11), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_11), 0x33fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_11), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_11), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_11), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_11), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_11), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_11), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_11), 0x4030, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_11), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_11), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_11), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_11), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_11), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_11), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_11), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_11), 0x4070, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_11), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_11), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_11), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_11), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_11), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_11), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_11), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_11), 0x40b0, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_11), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_11), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_11), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_11), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_11), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_11), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_11), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_11), 0x40f0, 4, { 4, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_11), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_11), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4180_11), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_11), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_11), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_11), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_11), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_11), 0x41b0, 4, { 4, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_11), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_11), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_11), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_11), 0x41bb, 4, { 4, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_11), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_11), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_11), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_11), 0x41f0, 4, { 4, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_11), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_11), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_11), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_11), 0x41fb, 4, { 4, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_11), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_11), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_11), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_11), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_11), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_11), 0x4230, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_11), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_11), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_11), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_11), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_11), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_11), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_11), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_11), 0x4270, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_11), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_11), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_11), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_11), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_11), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_11), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_11), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_11), 0x42b0, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_11), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_11), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42c0_11), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d0_11), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d8_11), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e0_11), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e8_11), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f0_11), 0x42f0, 4, { 4, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f8_11), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f9_11), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+{ CPUFUNC(op_4400_11), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_11), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_11), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_11), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_11), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_11), 0x4430, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_11), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_11), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_11), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_11), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_11), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_11), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_11), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_11), 0x4470, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_11), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_11), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_11), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_11), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_11), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_11), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_11), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_11), 0x44b0, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_11), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_11), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_11), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_11), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_11), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_11), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_11), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_11), 0x44f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_11), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_11), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_11), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_11), 0x44fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_11), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_11), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_11), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_11), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_11), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_11), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_11), 0x4630, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_11), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_11), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_11), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_11), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_11), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_11), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_11), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_11), 0x4670, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_11), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_11), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_11), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_11), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_11), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_11), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_11), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_11), 0x46b0, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_11), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_11), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_11), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_11), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_11), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_11), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_11), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_11), 0x46f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_11), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_11), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_11), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_11), 0x46fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_11), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_11), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4810_11), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_11), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_11), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_11), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_11), 0x4830, 4, { 4, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_11), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_11), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_11), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ CPUFUNC(op_4850_11), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_11), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_11), 0x4870, 4, { 4, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_11), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_11), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_11), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_11), 0x487b, 4, { 4, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_11), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_11), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_11), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_11), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_11), 0x48b0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_11), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_11), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_11), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_11), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_11), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_11), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_11), 0x48f0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_11), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_11), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_4a00_11), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_11), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_11), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_11), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_11), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_11), 0x4a30, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_11), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_11), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a40_11), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a50_11), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_11), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_11), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_11), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_11), 0x4a70, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_11), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_11), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a80_11), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a90_11), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_11), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_11), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_11), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_11), 0x4ab0, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_11), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_11), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ac0_11), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_11), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_11), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_11), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_11), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_11), 0x4af0, 4, { 4, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_11), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_11), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4c90_11), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_11), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_11), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_11), 0x4cb0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_11), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_11), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_11), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_11), 0x4cbb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_11), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_11), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_11), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_11), 0x4cf0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_11), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_11), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_11), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_11), 0x4cfb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_11), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_11), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_11), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_11), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_11), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_11), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_11), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_11), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_11), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e74_11), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+#endif
+{ CPUFUNC(op_4e75_11), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_11), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_11), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7a_11), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7b_11), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+#endif
+{ CPUFUNC(op_4e90_11), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_11), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_11), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_11), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_11), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_11), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_11), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_11), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_11), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_11), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_11), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_11), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_11), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_11), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_11), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_11), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_11), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_11), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_11), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_11), 0x5030, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_11), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_11), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_11), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_11), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_11), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_11), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_11), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_11), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_11), 0x5070, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_11), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_11), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_11), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_11), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_11), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_11), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_11), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_11), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_11), 0x50b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_11), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_11), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_11), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_11), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_11), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_11), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_11), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_11), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_11), 0x50f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_11), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_11), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5100_11), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_11), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_11), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_11), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_11), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_11), 0x5130, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_11), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_11), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_11), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_11), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_11), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_11), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_11), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_11), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_11), 0x5170, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_11), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_11), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_11), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_11), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_11), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_11), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_11), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_11), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_11), 0x51b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_11), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_11), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_11), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_11), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_11), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_11), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_11), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_11), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_11), 0x51f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_11), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_11), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c0_11), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_11), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_11), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_11), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_11), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_11), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_11), 0x52f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_11), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_11), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c0_11), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_11), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_11), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_11), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_11), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_11), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_11), 0x53f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_11), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_11), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c0_11), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_11), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_11), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_11), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_11), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_11), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_11), 0x54f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_11), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_11), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c0_11), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_11), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_11), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_11), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_11), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_11), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_11), 0x55f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_11), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_11), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c0_11), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_11), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_11), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_11), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_11), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_11), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_11), 0x56f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_11), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_11), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c0_11), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_11), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_11), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_11), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_11), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_11), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_11), 0x57f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_11), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_11), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c0_11), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_11), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_11), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_11), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_11), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_11), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_11), 0x58f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_11), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_11), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c0_11), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_11), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_11), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_11), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_11), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_11), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_11), 0x59f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_11), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_11), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac0_11), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_11), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_11), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_11), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_11), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_11), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_11), 0x5af0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_11), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_11), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc0_11), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_11), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_11), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_11), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_11), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_11), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_11), 0x5bf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_11), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_11), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc0_11), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_11), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_11), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_11), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_11), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_11), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_11), 0x5cf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_11), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_11), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc0_11), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_11), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_11), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_11), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_11), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_11), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_11), 0x5df0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_11), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_11), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec0_11), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_11), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_11), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_11), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_11), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_11), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_11), 0x5ef0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_11), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_11), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc0_11), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_11), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_11), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_11), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_11), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_11), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_11), 0x5ff0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_11), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_11), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_6000_11), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_11), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_11), 0x60ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6100_11), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_11), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_11), 0x61ff, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_11), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_11), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_11), 0x62ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6300_11), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_11), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_11), 0x63ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6400_11), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_11), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_11), 0x64ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6500_11), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_11), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_11), 0x65ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6600_11), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_11), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_11), 0x66ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6700_11), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_11), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_11), 0x67ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6800_11), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_11), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_11), 0x68ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6900_11), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_11), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_11), 0x69ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6a00_11), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_11), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_11), 0x6aff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6b00_11), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_11), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_11), 0x6bff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6c00_11), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_11), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_11), 0x6cff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6d00_11), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_11), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_11), 0x6dff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6e00_11), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_11), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_11), 0x6eff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6f00_11), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_11), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_11), 0x6fff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_7000_11), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_11), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_11), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_11), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_11), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_11), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_11), 0x8030, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_11), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_11), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_11), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_11), 0x803b, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_11), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_11), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_11), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_11), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_11), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_11), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_11), 0x8070, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_11), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_11), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_11), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_11), 0x807b, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_11), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_11), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_11), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_11), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_11), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_11), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_11), 0x80b0, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_11), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_11), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_11), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_11), 0x80bb, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_11), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_11), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_11), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_11), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_11), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_11), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_11), 0x80f0, 4, { 4, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_11), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_11), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_11), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_11), 0x80fb, 4, { 4, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_11), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_11), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_11), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_11), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_11), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_11), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_11), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_11), 0x8130, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_11), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_11), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8150_11), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_11), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_11), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_11), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_11), 0x8170, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_11), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_11), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8190_11), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_11), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_11), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_11), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_11), 0x81b0, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_11), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_11), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_11), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_11), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_11), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_11), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_11), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_11), 0x81f0, 4, { 4, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_11), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_11), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_11), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_11), 0x81fb, 4, { 4, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_11), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_11), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_11), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_11), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_11), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_11), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_11), 0x9030, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_11), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_11), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_11), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_11), 0x903b, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_11), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_11), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_11), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_11), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_11), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_11), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_11), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_11), 0x9070, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_11), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_11), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_11), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_11), 0x907b, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_11), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_11), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_11), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_11), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_11), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_11), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_11), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_11), 0x90b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_11), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_11), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_11), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_11), 0x90bb, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_11), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_11), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_11), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_11), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_11), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_11), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_11), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_11), 0x90f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_11), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_11), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_11), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_11), 0x90fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_11), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_11), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_11), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_11), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_11), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_11), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_11), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_11), 0x9130, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_11), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_11), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_11), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_11), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_11), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_11), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_11), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_11), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_11), 0x9170, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_11), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_11), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_11), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_11), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_11), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_11), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_11), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_11), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_11), 0x91b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_11), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_11), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_11), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_11), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_11), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_11), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_11), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_11), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_11), 0x91f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_11), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_11), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_11), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_11), 0x91fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_11), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_11), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_11), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_11), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_11), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_11), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_11), 0xb030, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_11), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_11), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_11), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_11), 0xb03b, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_11), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_11), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_11), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_11), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_11), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_11), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_11), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_11), 0xb070, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_11), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_11), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_11), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_11), 0xb07b, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_11), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_11), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_11), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_11), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_11), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_11), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_11), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_11), 0xb0b0, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_11), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_11), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_11), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_11), 0xb0bb, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_11), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_11), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_11), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_11), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_11), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_11), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_11), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_11), 0xb0f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_11), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_11), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_11), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_11), 0xb0fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_11), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_11), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_11), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_11), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_11), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_11), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_11), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_11), 0xb130, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_11), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_11), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_11), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_11), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_11), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_11), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_11), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_11), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_11), 0xb170, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_11), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_11), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_11), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_11), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_11), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_11), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_11), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_11), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_11), 0xb1b0, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_11), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_11), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_11), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_11), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_11), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_11), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_11), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_11), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_11), 0xb1f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_11), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_11), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_11), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_11), 0xb1fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_11), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_11), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_11), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_11), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_11), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_11), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_11), 0xc030, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_11), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_11), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_11), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_11), 0xc03b, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_11), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_11), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_11), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_11), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_11), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_11), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_11), 0xc070, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_11), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_11), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_11), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_11), 0xc07b, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_11), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_11), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_11), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_11), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_11), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_11), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_11), 0xc0b0, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_11), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_11), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_11), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_11), 0xc0bb, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_11), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_11), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_11), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_11), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_11), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_11), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_11), 0xc0f0, 4, { 4, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_11), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_11), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_11), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_11), 0xc0fb, 4, { 4, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_11), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_11), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_11), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_11), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_11), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_11), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_11), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_11), 0xc130, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_11), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_11), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_11), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_11), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_11), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_11), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_11), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_11), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_11), 0xc170, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_11), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_11), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_11), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_11), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_11), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_11), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_11), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_11), 0xc1b0, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_11), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_11), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_11), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_11), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_11), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_11), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_11), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_11), 0xc1f0, 4, { 4, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_11), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_11), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_11), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_11), 0xc1fb, 4, { 4, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_11), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_11), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_11), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_11), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_11), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_11), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_11), 0xd030, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_11), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_11), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_11), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_11), 0xd03b, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_11), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_11), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_11), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_11), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_11), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_11), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_11), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_11), 0xd070, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_11), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_11), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_11), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_11), 0xd07b, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_11), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_11), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_11), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_11), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_11), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_11), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_11), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_11), 0xd0b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_11), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_11), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_11), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_11), 0xd0bb, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_11), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_11), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_11), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_11), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_11), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_11), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_11), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_11), 0xd0f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_11), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_11), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_11), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_11), 0xd0fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_11), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_11), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_11), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_11), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_11), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_11), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_11), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_11), 0xd130, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_11), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_11), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_11), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_11), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_11), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_11), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_11), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_11), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_11), 0xd170, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_11), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_11), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_11), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_11), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_11), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_11), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_11), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_11), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_11), 0xd1b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_11), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_11), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_11), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_11), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_11), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_11), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_11), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_11), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_11), 0xd1f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_11), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_11), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_11), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_11), 0xd1fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_11), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_11), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_11), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_11), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_11), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_11), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_11), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_11), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_11), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_11), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_11), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_11), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_11), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_11), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_11), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_11), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_11), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_11), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_11), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_11), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_11), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_11), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_11), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_11), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_11), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_11), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_11), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_11), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_11), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_11), 0xe0f0, 4, { 4, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_11), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_11), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_11), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_11), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_11), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_11), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_11), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_11), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_11), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_11), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_11), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_11), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_11), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_11), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_11), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_11), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_11), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_11), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_11), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_11), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_11), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_11), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_11), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_11), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_11), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_11), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_11), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_11), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_11), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_11), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_11), 0xe1f0, 4, { 4, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_11), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_11), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_11), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_11), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_11), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_11), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_11), 0xe2f0, 4, { 4, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_11), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_11), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_11), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_11), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_11), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_11), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_11), 0xe3f0, 4, { 4, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_11), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_11), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_11), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_11), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_11), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_11), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_11), 0xe4f0, 4, { 4, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_11), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_11), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_11), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_11), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_11), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_11), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_11), 0xe5f0, 4, { 4, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_11), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_11), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_11), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_11), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_11), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_11), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_11), 0xe6f0, 4, { 4, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_11), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_11), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_11), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_11), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_11), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_11), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_11), 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_11), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_11), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ 0, 0 }};
+#endif /* CPUEMU_11 */
+const struct cputbl CPUFUNC(op_smalltbl_12)[] = {
+{ CPUFUNC(op_0000_11), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_11), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_11), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_11), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_11), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_11), 0x0030, 6, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_11), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_11), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_11), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_11), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_11), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_11), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_11), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_11), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_11), 0x0070, 6, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_11), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_11), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_11), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_11), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_11), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_11), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_11), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_11), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_11), 0x00b0, 8, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_11), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_11), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0100_11), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_11), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_11), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_11), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_11), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_11), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_11), 0x0130, 4, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_11), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_11), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_11), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_11), 0x013b, 4, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_11), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_11), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_11), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_11), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_11), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_11), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_11), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_11), 0x0170, 4, { 4, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_11), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_11), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_11), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_11), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_11), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_11), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_11), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_11), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_11), 0x01b0, 4, { 4, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_11), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_11), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_11), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_11), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_11), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_11), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_11), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_11), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_11), 0x01f0, 4, { 4, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_11), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_11), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_11), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_11), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_11), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_11), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_11), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_11), 0x0230, 6, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_11), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_11), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_11), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_11), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_11), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_11), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_11), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_11), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_11), 0x0270, 6, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_11), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_11), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_11), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_11), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_11), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_11), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_11), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_11), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_11), 0x02b0, 8, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_11), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_11), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0400_11), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_11), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_11), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_11), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_11), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_11), 0x0430, 6, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_11), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_11), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_11), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_11), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_11), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_11), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_11), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_11), 0x0470, 6, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_11), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_11), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_11), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_11), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_11), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_11), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_11), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_11), 0x04b0, 8, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_11), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_11), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0600_11), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_11), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_11), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_11), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_11), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_11), 0x0630, 6, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_11), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_11), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_11), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_11), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_11), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_11), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_11), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_11), 0x0670, 6, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_11), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_11), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_11), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_11), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_11), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_11), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_11), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_11), 0x06b0, 8, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_11), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_11), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0800_11), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_11), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_11), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_11), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_11), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_11), 0x0830, 6, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_11), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_11), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_11), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_11), 0x083b, 6, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_11), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_11), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_11), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_11), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_11), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_11), 0x0870, 6, { 4, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_11), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_11), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_11), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_11), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_11), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_11), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_11), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_11), 0x08b0, 6, { 4, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_11), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_11), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_11), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_11), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_11), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_11), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_11), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_11), 0x08f0, 6, { 4, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_11), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_11), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_11), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_11), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_11), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_11), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_11), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_11), 0x0a30, 6, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_11), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_11), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_11), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_11), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_11), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_11), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_11), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_11), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_11), 0x0a70, 6, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_11), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_11), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_11), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_11), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_11), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_11), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_11), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_11), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_11), 0x0ab0, 8, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_11), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_11), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0c00_11), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_11), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_11), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_11), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_11), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_11), 0x0c30, 6, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_11), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_11), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c40_11), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_11), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_11), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_11), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_11), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_11), 0x0c70, 6, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_11), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_11), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c80_11), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_11), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_11), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_11), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_11), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_11), 0x0cb0, 8, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_11), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_11), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_1000_11), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_11), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_11), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_11), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_11), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_11), 0x1030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_11), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_11), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_11), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_11), 0x103b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_11), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_11), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_11), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_11), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_11), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_11), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_11), 0x10b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_11), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_11), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_11), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_11), 0x10bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_11), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_11), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_11), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_11), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_11), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_11), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_11), 0x10f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_11), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_11), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_11), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_11), 0x10fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_11), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_11), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_11), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_11), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_11), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_11), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_11), 0x1130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_11), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_11), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_11), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_11), 0x113b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_11), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_11), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_11), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_11), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_11), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_11), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_11), 0x1170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_11), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_11), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_11), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_11), 0x117b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_11), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_11), 0x1180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_11), 0x1190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_11), 0x1198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_11), 0x11a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_11), 0x11a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_11), 0x11b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_11), 0x11b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_11), 0x11b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_11), 0x11ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_11), 0x11bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_11), 0x11bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_11), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_11), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_11), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_11), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_11), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_11), 0x11f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_11), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_11), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_11), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_11), 0x11fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_11), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_11), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_11), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_11), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_11), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_11), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_11), 0x13f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_11), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_11), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_11), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_11), 0x13fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_11), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_11), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_11), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_11), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_11), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_11), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_11), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_11), 0x2030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_11), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_11), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_11), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_11), 0x203b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_11), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_11), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_11), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_11), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_11), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_11), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_11), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_11), 0x2070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_11), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_11), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_11), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_11), 0x207b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_11), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_11), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_11), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_11), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_11), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_11), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_11), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_11), 0x20b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_11), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_11), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_11), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_11), 0x20bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_11), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_11), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_11), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_11), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_11), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_11), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_11), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_11), 0x20f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_11), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_11), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_11), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_11), 0x20fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_11), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_11), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_11), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_11), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_11), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_11), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_11), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_11), 0x2130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_11), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_11), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_11), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_11), 0x213b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_11), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_11), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_11), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_11), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_11), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_11), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_11), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_11), 0x2170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_11), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_11), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_11), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_11), 0x217b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_11), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_11), 0x2180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_11), 0x2188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_11), 0x2190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_11), 0x2198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_11), 0x21a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_11), 0x21a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_11), 0x21b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_11), 0x21b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_11), 0x21b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_11), 0x21ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_11), 0x21bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_11), 0x21bc, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_11), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_11), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_11), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_11), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_11), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_11), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_11), 0x21f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_11), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_11), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_11), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_11), 0x21fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_11), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_11), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_11), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_11), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_11), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_11), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_11), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_11), 0x23f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_11), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_11), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_11), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_11), 0x23fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_11), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_11), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_11), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_11), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_11), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_11), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_11), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_11), 0x3030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_11), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_11), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_11), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_11), 0x303b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_11), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_11), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_11), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_11), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_11), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_11), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_11), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_11), 0x3070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_11), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_11), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_11), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_11), 0x307b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_11), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_11), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_11), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_11), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_11), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_11), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_11), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_11), 0x30b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_11), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_11), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_11), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_11), 0x30bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_11), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_11), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_11), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_11), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_11), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_11), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_11), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_11), 0x30f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_11), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_11), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_11), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_11), 0x30fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_11), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_11), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_11), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_11), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_11), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_11), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_11), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_11), 0x3130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_11), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_11), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_11), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_11), 0x313b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_11), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_11), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_11), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_11), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_11), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_11), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_11), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_11), 0x3170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_11), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_11), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_11), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_11), 0x317b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_11), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_11), 0x3180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_11), 0x3188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_11), 0x3190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_11), 0x3198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_11), 0x31a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_11), 0x31a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_11), 0x31b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_11), 0x31b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_11), 0x31b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_11), 0x31ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_11), 0x31bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_11), 0x31bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_11), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_11), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_11), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_11), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_11), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_11), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_11), 0x31f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_11), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_11), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_11), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_11), 0x31fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_11), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_11), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_11), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_11), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_11), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_11), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_11), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_11), 0x33f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_11), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_11), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_11), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_11), 0x33fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_11), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_11), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_11), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_11), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_11), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_11), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_11), 0x4030, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_11), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_11), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_11), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_11), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_11), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_11), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_11), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_11), 0x4070, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_11), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_11), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_11), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_11), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_11), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_11), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_11), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_11), 0x40b0, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_11), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_11), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_12), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_12), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_12), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_12), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_12), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_12), 0x40f0, 4, { 4, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_12), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_12), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4180_11), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_11), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_11), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_11), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_11), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_11), 0x41b0, 4, { 4, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_11), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_11), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_11), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_11), 0x41bb, 4, { 4, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_11), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_11), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_11), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_11), 0x41f0, 4, { 4, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_11), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_11), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_11), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_11), 0x41fb, 4, { 4, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_12), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_12), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_12), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_12), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_12), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_12), 0x4230, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_12), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_12), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_12), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_12), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_12), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_12), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_12), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_12), 0x4270, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_12), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_12), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_12), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_12), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_12), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_12), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_12), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_12), 0x42b0, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_12), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_12), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4400_11), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_11), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_11), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_11), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_11), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_11), 0x4430, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_11), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_11), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_11), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_11), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_11), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_11), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_11), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_11), 0x4470, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_11), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_11), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_11), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_11), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_11), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_11), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_11), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_11), 0x44b0, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_11), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_11), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_11), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_11), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_11), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_11), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_11), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_11), 0x44f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_11), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_11), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_11), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_11), 0x44fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_11), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_11), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_11), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_11), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_11), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_11), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_11), 0x4630, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_11), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_11), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_11), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_11), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_11), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_11), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_11), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_11), 0x4670, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_11), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_11), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_11), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_11), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_11), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_11), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_11), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_11), 0x46b0, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_11), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_11), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_11), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_11), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_11), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_11), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_11), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_11), 0x46f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_11), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_11), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_11), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_11), 0x46fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_11), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_11), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4810_11), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_11), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_11), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_11), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_11), 0x4830, 4, { 4, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_11), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_11), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_11), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ CPUFUNC(op_4850_11), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_11), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_11), 0x4870, 4, { 4, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_11), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_11), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_11), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_11), 0x487b, 4, { 4, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_11), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_11), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_11), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_11), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_11), 0x48b0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_11), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_11), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_11), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_11), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_11), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_11), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_11), 0x48f0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_11), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_11), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_4a00_11), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_11), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_11), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_11), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_11), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_11), 0x4a30, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_11), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_11), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a40_11), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a50_11), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_11), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_11), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_11), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_11), 0x4a70, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_11), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_11), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a80_11), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a90_11), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_11), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_11), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_11), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_11), 0x4ab0, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_11), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_11), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ac0_11), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_11), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_11), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_11), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_11), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_11), 0x4af0, 4, { 4, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_11), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_11), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4c90_11), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_11), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_11), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_11), 0x4cb0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_11), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_11), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_11), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_11), 0x4cbb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_11), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_11), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_11), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_11), 0x4cf0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_11), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_11), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_11), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_11), 0x4cfb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_11), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_11), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_11), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_11), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_11), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_11), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_11), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_11), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_12), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+{ CPUFUNC(op_4e75_11), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_11), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_11), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+{ CPUFUNC(op_4e90_11), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_11), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_11), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_11), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_11), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_11), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_11), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_11), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_11), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_11), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_11), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_11), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_11), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_11), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_11), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_11), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_11), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_11), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_11), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_11), 0x5030, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_11), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_11), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_11), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_11), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_11), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_11), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_11), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_11), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_11), 0x5070, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_11), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_11), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_11), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_11), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_11), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_11), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_11), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_11), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_11), 0x50b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_11), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_11), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_12), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_11), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_12), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_12), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_12), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_12), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_12), 0x50f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_12), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_12), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5100_11), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_11), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_11), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_11), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_11), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_11), 0x5130, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_11), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_11), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_11), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_11), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_11), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_11), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_11), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_11), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_11), 0x5170, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_11), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_11), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_11), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_11), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_11), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_11), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_11), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_11), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_11), 0x51b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_11), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_11), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_12), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_11), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_12), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_12), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_12), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_12), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_12), 0x51f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_12), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_12), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c0_12), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_11), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_12), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_12), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_12), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_12), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_12), 0x52f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_12), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_12), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c0_12), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_11), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_12), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_12), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_12), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_12), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_12), 0x53f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_12), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_12), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c0_12), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_11), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_12), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_12), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_12), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_12), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_12), 0x54f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_12), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_12), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c0_12), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_11), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_12), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_12), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_12), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_12), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_12), 0x55f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_12), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_12), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c0_12), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_11), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_12), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_12), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_12), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_12), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_12), 0x56f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_12), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_12), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c0_12), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_11), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_12), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_12), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_12), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_12), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_12), 0x57f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_12), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_12), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c0_12), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_11), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_12), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_12), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_12), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_12), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_12), 0x58f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_12), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_12), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c0_12), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_11), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_12), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_12), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_12), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_12), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_12), 0x59f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_12), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_12), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac0_12), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_11), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_12), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_12), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_12), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_12), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_12), 0x5af0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_12), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_12), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc0_12), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_11), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_12), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_12), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_12), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_12), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_12), 0x5bf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_12), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_12), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc0_12), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_11), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_12), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_12), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_12), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_12), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_12), 0x5cf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_12), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_12), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc0_12), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_11), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_12), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_12), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_12), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_12), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_12), 0x5df0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_12), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_12), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec0_12), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_11), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_12), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_12), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_12), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_12), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_12), 0x5ef0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_12), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_12), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc0_12), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_11), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_12), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_12), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_12), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_12), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_12), 0x5ff0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_12), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_12), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_6000_11), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_11), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_11), 0x60ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6100_11), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_11), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_11), 0x61ff, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_11), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_11), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_11), 0x62ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6300_11), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_11), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_11), 0x63ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6400_11), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_11), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_11), 0x64ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6500_11), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_11), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_11), 0x65ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6600_11), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_11), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_11), 0x66ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6700_11), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_11), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_11), 0x67ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6800_11), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_11), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_11), 0x68ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6900_11), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_11), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_11), 0x69ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6a00_11), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_11), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_11), 0x6aff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6b00_11), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_11), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_11), 0x6bff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6c00_11), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_11), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_11), 0x6cff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6d00_11), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_11), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_11), 0x6dff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6e00_11), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_11), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_11), 0x6eff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6f00_11), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_11), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_11), 0x6fff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_7000_11), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_11), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_11), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_11), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_11), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_11), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_11), 0x8030, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_11), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_11), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_11), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_11), 0x803b, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_11), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_11), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_11), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_11), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_11), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_11), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_11), 0x8070, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_11), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_11), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_11), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_11), 0x807b, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_11), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_11), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_11), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_11), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_11), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_11), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_11), 0x80b0, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_11), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_11), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_11), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_11), 0x80bb, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_11), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_11), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_11), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_11), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_11), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_11), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_11), 0x80f0, 4, { 4, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_11), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_11), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_11), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_11), 0x80fb, 4, { 4, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_11), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_11), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_11), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_11), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_11), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_11), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_11), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_11), 0x8130, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_11), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_11), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8150_11), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_11), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_11), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_11), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_11), 0x8170, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_11), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_11), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8190_11), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_11), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_11), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_11), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_11), 0x81b0, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_11), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_11), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_11), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_11), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_11), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_11), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_11), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_11), 0x81f0, 4, { 4, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_11), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_11), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_11), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_11), 0x81fb, 4, { 4, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_11), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_11), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_11), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_11), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_11), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_11), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_11), 0x9030, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_11), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_11), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_11), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_11), 0x903b, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_11), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_11), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_11), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_11), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_11), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_11), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_11), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_11), 0x9070, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_11), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_11), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_11), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_11), 0x907b, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_11), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_11), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_11), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_11), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_11), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_11), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_11), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_11), 0x90b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_11), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_11), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_11), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_11), 0x90bb, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_11), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_11), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_11), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_11), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_11), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_11), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_11), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_11), 0x90f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_11), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_11), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_11), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_11), 0x90fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_11), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_11), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_11), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_11), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_11), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_11), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_11), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_11), 0x9130, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_11), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_11), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_11), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_11), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_11), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_11), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_11), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_11), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_11), 0x9170, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_11), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_11), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_11), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_11), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_11), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_11), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_11), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_11), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_11), 0x91b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_11), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_11), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_11), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_11), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_11), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_11), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_11), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_11), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_11), 0x91f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_11), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_11), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_11), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_11), 0x91fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_11), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_11), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_11), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_11), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_11), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_11), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_11), 0xb030, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_11), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_11), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_11), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_11), 0xb03b, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_11), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_11), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_11), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_11), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_11), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_11), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_11), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_11), 0xb070, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_11), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_11), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_11), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_11), 0xb07b, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_11), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_11), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_11), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_11), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_11), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_11), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_11), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_11), 0xb0b0, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_11), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_11), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_11), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_11), 0xb0bb, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_11), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_11), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_11), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_11), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_11), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_11), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_11), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_11), 0xb0f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_11), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_11), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_11), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_11), 0xb0fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_11), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_11), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_11), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_11), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_11), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_11), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_11), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_11), 0xb130, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_11), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_11), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_11), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_11), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_11), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_11), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_11), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_11), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_11), 0xb170, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_11), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_11), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_11), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_11), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_11), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_11), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_11), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_11), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_11), 0xb1b0, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_11), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_11), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_11), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_11), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_11), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_11), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_11), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_11), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_11), 0xb1f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_11), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_11), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_11), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_11), 0xb1fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_11), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_11), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_11), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_11), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_11), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_11), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_11), 0xc030, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_11), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_11), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_11), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_11), 0xc03b, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_11), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_11), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_11), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_11), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_11), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_11), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_11), 0xc070, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_11), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_11), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_11), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_11), 0xc07b, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_11), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_11), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_11), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_11), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_11), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_11), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_11), 0xc0b0, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_11), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_11), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_11), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_11), 0xc0bb, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_11), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_11), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_11), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_11), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_11), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_11), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_11), 0xc0f0, 4, { 4, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_11), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_11), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_11), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_11), 0xc0fb, 4, { 4, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_11), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_11), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_11), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_11), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_11), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_11), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_11), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_11), 0xc130, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_11), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_11), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_11), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_11), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_11), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_11), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_11), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_11), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_11), 0xc170, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_11), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_11), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_11), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_11), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_11), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_11), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_11), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_11), 0xc1b0, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_11), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_11), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_11), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_11), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_11), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_11), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_11), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_11), 0xc1f0, 4, { 4, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_11), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_11), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_11), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_11), 0xc1fb, 4, { 4, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_11), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_11), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_11), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_11), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_11), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_11), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_11), 0xd030, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_11), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_11), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_11), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_11), 0xd03b, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_11), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_11), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_11), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_11), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_11), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_11), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_11), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_11), 0xd070, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_11), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_11), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_11), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_11), 0xd07b, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_11), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_11), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_11), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_11), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_11), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_11), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_11), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_11), 0xd0b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_11), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_11), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_11), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_11), 0xd0bb, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_11), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_11), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_11), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_11), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_11), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_11), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_11), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_11), 0xd0f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_11), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_11), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_11), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_11), 0xd0fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_11), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_11), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_11), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_11), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_11), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_11), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_11), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_11), 0xd130, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_11), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_11), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_11), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_11), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_11), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_11), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_11), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_11), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_11), 0xd170, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_11), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_11), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_11), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_11), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_11), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_11), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_11), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_11), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_11), 0xd1b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_11), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_11), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_11), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_11), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_11), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_11), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_11), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_11), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_11), 0xd1f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_11), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_11), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_11), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_11), 0xd1fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_11), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_11), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_11), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_11), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_11), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_11), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_11), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_11), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_11), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_11), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_11), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_11), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_11), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_11), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_11), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_11), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_11), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_11), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_11), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_11), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_11), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_11), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_11), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_11), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_11), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_11), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_11), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_11), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_11), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_11), 0xe0f0, 4, { 4, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_11), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_11), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_11), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_11), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_11), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_11), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_11), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_11), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_11), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_11), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_11), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_11), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_11), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_11), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_11), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_11), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_11), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_11), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_11), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_11), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_11), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_11), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_11), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_11), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_11), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_11), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_11), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_11), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_11), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_11), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_11), 0xe1f0, 4, { 4, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_11), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_11), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_11), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_11), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_11), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_11), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_11), 0xe2f0, 4, { 4, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_11), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_11), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_11), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_11), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_11), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_11), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_11), 0xe3f0, 4, { 4, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_11), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_11), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_11), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_11), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_11), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_11), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_11), 0xe4f0, 4, { 4, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_11), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_11), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_11), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_11), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_11), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_11), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_11), 0xe5f0, 4, { 4, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_11), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_11), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_11), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_11), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_11), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_11), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_11), 0xe6f0, 4, { 4, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_11), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_11), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_11), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_11), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_11), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_11), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_11), 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_11), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_11), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ 0, 0 }};
+#ifdef CPUEMU_13
+const struct cputbl CPUFUNC(op_smalltbl_13)[] = {
+{ (cpuop_func*)CPUFUNC(op_0000_13), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0010_13), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0018_13), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0020_13), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0028_13), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0030_13), 0x0030, 6, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0038_13), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0039_13), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_003c_13), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ (cpuop_func*)CPUFUNC(op_0040_13), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0050_13), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0058_13), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0060_13), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0068_13), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0070_13), 0x0070, 6, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0078_13), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0079_13), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_007c_13), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ (cpuop_func*)CPUFUNC(op_0080_13), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0090_13), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0098_13), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00a0_13), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00a8_13), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b0_13), 0x00b0, 8, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b8_13), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b9_13), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0100_13), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0108_13), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ (cpuop_func*)CPUFUNC(op_0110_13), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0118_13), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0120_13), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0128_13), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0130_13), 0x0130, 4, { 4, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0138_13), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0139_13), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013a_13), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013b_13), 0x013b, 4, { 4, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013c_13), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0140_13), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0148_13), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ (cpuop_func*)CPUFUNC(op_0150_13), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0158_13), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0160_13), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0168_13), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0170_13), 0x0170, 4, { 4, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0178_13), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0179_13), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0180_13), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0188_13), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ (cpuop_func*)CPUFUNC(op_0190_13), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0198_13), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01a0_13), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01a8_13), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b0_13), 0x01b0, 4, { 4, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b8_13), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b9_13), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01c0_13), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01c8_13), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ (cpuop_func*)CPUFUNC(op_01d0_13), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01d8_13), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01e0_13), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01e8_13), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f0_13), 0x01f0, 4, { 4, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f8_13), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f9_13), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_0200_13), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0210_13), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0218_13), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0220_13), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0228_13), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0230_13), 0x0230, 6, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0238_13), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0239_13), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_023c_13), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ (cpuop_func*)CPUFUNC(op_0240_13), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0250_13), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0258_13), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0260_13), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0268_13), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0270_13), 0x0270, 6, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0278_13), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0279_13), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_027c_13), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ (cpuop_func*)CPUFUNC(op_0280_13), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0290_13), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0298_13), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02a0_13), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02a8_13), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b0_13), 0x02b0, 8, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b8_13), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b9_13), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0400_13), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0410_13), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0418_13), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0420_13), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0428_13), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0430_13), 0x0430, 6, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0438_13), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0439_13), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0440_13), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0450_13), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0458_13), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0460_13), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0468_13), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0470_13), 0x0470, 6, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0478_13), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0479_13), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0480_13), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0490_13), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0498_13), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04a0_13), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04a8_13), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b0_13), 0x04b0, 8, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b8_13), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b9_13), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0600_13), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0610_13), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0618_13), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0620_13), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0628_13), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0630_13), 0x0630, 6, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0638_13), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0639_13), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0640_13), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0650_13), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0658_13), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0660_13), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0668_13), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0670_13), 0x0670, 6, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0678_13), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0679_13), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0680_13), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0690_13), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0698_13), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06a0_13), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06a8_13), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b0_13), 0x06b0, 8, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b8_13), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b9_13), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0800_13), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0810_13), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0818_13), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0820_13), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0828_13), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0830_13), 0x0830, 6, { 4, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0838_13), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0839_13), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_083a_13), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_083b_13), 0x083b, 6, { 4, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0840_13), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0850_13), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0858_13), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0860_13), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0868_13), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0870_13), 0x0870, 6, { 4, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0878_13), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0879_13), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0880_13), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0890_13), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0898_13), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08a0_13), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08a8_13), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b0_13), 0x08b0, 6, { 4, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b8_13), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b9_13), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08c0_13), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08d0_13), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08d8_13), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08e0_13), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08e8_13), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f0_13), 0x08f0, 6, { 4, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f8_13), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f9_13), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_0a00_13), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a10_13), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a18_13), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a20_13), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a28_13), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a30_13), 0x0a30, 6, { 4, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a38_13), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a39_13), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a3c_13), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ (cpuop_func*)CPUFUNC(op_0a40_13), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a50_13), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a58_13), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a60_13), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a68_13), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a70_13), 0x0a70, 6, { 4, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a78_13), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a79_13), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a7c_13), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ (cpuop_func*)CPUFUNC(op_0a80_13), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a90_13), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a98_13), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0aa0_13), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0aa8_13), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab0_13), 0x0ab0, 8, { 4, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab8_13), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab9_13), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0c00_13), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c10_13), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c18_13), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c20_13), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c28_13), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c30_13), 0x0c30, 6, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c38_13), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c39_13), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c40_13), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c50_13), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c58_13), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c60_13), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c68_13), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c70_13), 0x0c70, 6, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c78_13), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c79_13), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c80_13), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c90_13), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c98_13), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0ca0_13), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0ca8_13), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb0_13), 0x0cb0, 8, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb8_13), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb9_13), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_1000_13), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1010_13), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1018_13), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1020_13), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1028_13), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1030_13), 0x1030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1038_13), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1039_13), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103a_13), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103b_13), 0x103b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103c_13), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1080_13), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1090_13), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1098_13), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10a0_13), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10a8_13), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b0_13), 0x10b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b8_13), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b9_13), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10ba_13), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10bb_13), 0x10bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10bc_13), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10c0_13), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10d0_13), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10d8_13), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10e0_13), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10e8_13), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f0_13), 0x10f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f8_13), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f9_13), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fa_13), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fb_13), 0x10fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fc_13), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1100_13), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1110_13), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1118_13), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1120_13), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1128_13), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1130_13), 0x1130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1138_13), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1139_13), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113a_13), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113b_13), 0x113b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113c_13), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1140_13), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1150_13), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1158_13), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1160_13), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1168_13), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1170_13), 0x1170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1178_13), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1179_13), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117a_13), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117b_13), 0x117b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117c_13), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1180_13), 0x1180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1190_13), 0x1190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1198_13), 0x1198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11a0_13), 0x11a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11a8_13), 0x11a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b0_13), 0x11b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b8_13), 0x11b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b9_13), 0x11b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11ba_13), 0x11ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11bb_13), 0x11bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11bc_13), 0x11bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11c0_13), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11d0_13), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11d8_13), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11e0_13), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11e8_13), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f0_13), 0x11f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f8_13), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f9_13), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fa_13), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fb_13), 0x11fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fc_13), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13c0_13), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13d0_13), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13d8_13), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13e0_13), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13e8_13), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f0_13), 0x13f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f8_13), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f9_13), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fa_13), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fb_13), 0x13fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fc_13), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2000_13), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2008_13), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2010_13), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2018_13), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2020_13), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2028_13), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2030_13), 0x2030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2038_13), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2039_13), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203a_13), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203b_13), 0x203b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203c_13), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2040_13), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2048_13), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2050_13), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2058_13), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2060_13), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2068_13), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2070_13), 0x2070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2078_13), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2079_13), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207a_13), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207b_13), 0x207b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207c_13), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2080_13), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2088_13), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2090_13), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2098_13), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20a0_13), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20a8_13), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b0_13), 0x20b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b8_13), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b9_13), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20ba_13), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20bb_13), 0x20bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20bc_13), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20c0_13), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20c8_13), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20d0_13), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20d8_13), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20e0_13), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20e8_13), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f0_13), 0x20f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f8_13), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f9_13), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fa_13), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fb_13), 0x20fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fc_13), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2100_13), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2108_13), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2110_13), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2118_13), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2120_13), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2128_13), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2130_13), 0x2130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2138_13), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2139_13), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213a_13), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213b_13), 0x213b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213c_13), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2140_13), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2148_13), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2150_13), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2158_13), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2160_13), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2168_13), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2170_13), 0x2170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2178_13), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2179_13), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217a_13), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217b_13), 0x217b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217c_13), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2180_13), 0x2180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2188_13), 0x2188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2190_13), 0x2190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2198_13), 0x2198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21a0_13), 0x21a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21a8_13), 0x21a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b0_13), 0x21b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b8_13), 0x21b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b9_13), 0x21b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21ba_13), 0x21ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21bb_13), 0x21bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21bc_13), 0x21bc, 8, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21c0_13), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21c8_13), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21d0_13), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21d8_13), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21e0_13), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21e8_13), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f0_13), 0x21f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f8_13), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f9_13), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fa_13), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fb_13), 0x21fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fc_13), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23c0_13), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23c8_13), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23d0_13), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23d8_13), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23e0_13), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23e8_13), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f0_13), 0x23f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f8_13), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f9_13), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fa_13), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fb_13), 0x23fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fc_13), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3000_13), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3008_13), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3010_13), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3018_13), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3020_13), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3028_13), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3030_13), 0x3030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3038_13), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3039_13), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303a_13), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303b_13), 0x303b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303c_13), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3040_13), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3048_13), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3050_13), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3058_13), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3060_13), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3068_13), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3070_13), 0x3070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3078_13), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3079_13), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307a_13), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307b_13), 0x307b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307c_13), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3080_13), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3088_13), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3090_13), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3098_13), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30a0_13), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30a8_13), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b0_13), 0x30b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b8_13), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b9_13), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30ba_13), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30bb_13), 0x30bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30bc_13), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30c0_13), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30c8_13), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30d0_13), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30d8_13), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30e0_13), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30e8_13), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f0_13), 0x30f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f8_13), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f9_13), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fa_13), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fb_13), 0x30fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fc_13), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3100_13), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3108_13), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3110_13), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3118_13), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3120_13), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3128_13), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3130_13), 0x3130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3138_13), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3139_13), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313a_13), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313b_13), 0x313b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313c_13), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3140_13), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3148_13), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3150_13), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3158_13), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3160_13), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3168_13), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3170_13), 0x3170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3178_13), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3179_13), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317a_13), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317b_13), 0x317b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317c_13), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3180_13), 0x3180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3188_13), 0x3188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3190_13), 0x3190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3198_13), 0x3198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31a0_13), 0x31a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31a8_13), 0x31a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b0_13), 0x31b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b8_13), 0x31b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b9_13), 0x31b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31ba_13), 0x31ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31bb_13), 0x31bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31bc_13), 0x31bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31c0_13), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31c8_13), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31d0_13), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31d8_13), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31e0_13), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31e8_13), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f0_13), 0x31f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f8_13), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f9_13), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fa_13), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fb_13), 0x31fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fc_13), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33c0_13), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33c8_13), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33d0_13), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33d8_13), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33e0_13), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33e8_13), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f0_13), 0x33f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f8_13), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f9_13), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fa_13), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fb_13), 0x33fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fc_13), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_4000_13), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4010_13), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4018_13), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4020_13), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4028_13), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4030_13), 0x4030, 4, { 4, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4038_13), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4039_13), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4040_13), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4050_13), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4058_13), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4060_13), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4068_13), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4070_13), 0x4070, 4, { 4, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4078_13), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4079_13), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4080_13), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4090_13), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4098_13), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40a0_13), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40a8_13), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b0_13), 0x40b0, 4, { 4, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b8_13), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b9_13), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40c0_13), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40d0_13), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40d8_13), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40e0_13), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40e8_13), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f0_13), 0x40f0, 4, { 4, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f8_13), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f9_13), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_4180_13), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4190_13), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4198_13), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41a0_13), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41a8_13), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b0_13), 0x41b0, 4, { 4, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b8_13), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b9_13), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41ba_13), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41bb_13), 0x41bb, 4, { 4, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41bc_13), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41d0_13), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41e8_13), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f0_13), 0x41f0, 4, { 4, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f8_13), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f9_13), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41fa_13), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41fb_13), 0x41fb, 4, { 4, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_4200_13), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4210_13), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4218_13), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4220_13), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4228_13), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4230_13), 0x4230, 4, { 4, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4238_13), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4239_13), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4240_13), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4250_13), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4258_13), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4260_13), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4268_13), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4270_13), 0x4270, 4, { 4, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4278_13), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4279_13), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4280_13), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4290_13), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4298_13), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42a0_13), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42a8_13), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b0_13), 0x42b0, 4, { 4, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b8_13), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b9_13), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42c0_13), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42d0_13), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42d8_13), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42e0_13), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42e8_13), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42f0_13), 0x42f0, 4, { 4, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42f8_13), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42f9_13), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4400_13), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4410_13), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4418_13), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4420_13), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4428_13), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4430_13), 0x4430, 4, { 4, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4438_13), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4439_13), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4440_13), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4450_13), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4458_13), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4460_13), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4468_13), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4470_13), 0x4470, 4, { 4, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4478_13), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4479_13), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4480_13), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4490_13), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4498_13), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44a0_13), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44a8_13), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b0_13), 0x44b0, 4, { 4, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b8_13), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b9_13), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44c0_13), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44d0_13), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44d8_13), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44e0_13), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44e8_13), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f0_13), 0x44f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f8_13), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f9_13), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fa_13), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fb_13), 0x44fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fc_13), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_4600_13), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4610_13), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4618_13), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4620_13), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4628_13), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4630_13), 0x4630, 4, { 4, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4638_13), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4639_13), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4640_13), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4650_13), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4658_13), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4660_13), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4668_13), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4670_13), 0x4670, 4, { 4, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4678_13), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4679_13), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4680_13), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4690_13), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4698_13), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46a0_13), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46a8_13), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b0_13), 0x46b0, 4, { 4, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b8_13), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b9_13), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46c0_13), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46d0_13), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46d8_13), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46e0_13), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46e8_13), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f0_13), 0x46f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f8_13), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f9_13), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fa_13), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fb_13), 0x46fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fc_13), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_4800_13), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4810_13), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4818_13), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4820_13), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4828_13), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4830_13), 0x4830, 4, { 4, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4838_13), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4839_13), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4840_13), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ (cpuop_func*)CPUFUNC(op_4850_13), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4868_13), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4870_13), 0x4870, 4, { 4, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4878_13), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4879_13), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_487a_13), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_487b_13), 0x487b, 4, { 4, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4880_13), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ (cpuop_func*)CPUFUNC(op_4890_13), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48a0_13), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48a8_13), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b0_13), 0x48b0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b8_13), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b9_13), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48c0_13), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ (cpuop_func*)CPUFUNC(op_48d0_13), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48e0_13), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48e8_13), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f0_13), 0x48f0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f8_13), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f9_13), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_4a00_13), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a10_13), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a18_13), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a20_13), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a28_13), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a30_13), 0x4a30, 4, { 4, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a38_13), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a39_13), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a40_13), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a50_13), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a58_13), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a60_13), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a68_13), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a70_13), 0x4a70, 4, { 4, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a78_13), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a79_13), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a80_13), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a90_13), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a98_13), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4aa0_13), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4aa8_13), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab0_13), 0x4ab0, 4, { 4, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab8_13), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab9_13), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ac0_13), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ad0_13), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ad8_13), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ae0_13), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ae8_13), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af0_13), 0x4af0, 4, { 4, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af8_13), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af9_13), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4c90_13), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4c98_13), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4ca8_13), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb0_13), 0x4cb0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb8_13), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb9_13), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cba_13), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cbb_13), 0x4cbb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cd0_13), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cd8_13), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4ce8_13), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf0_13), 0x4cf0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf8_13), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf9_13), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cfa_13), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cfb_13), 0x4cfb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4e40_13), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ (cpuop_func*)CPUFUNC(op_4e50_13), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ (cpuop_func*)CPUFUNC(op_4e58_13), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ (cpuop_func*)CPUFUNC(op_4e60_13), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ (cpuop_func*)CPUFUNC(op_4e68_13), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ (cpuop_func*)CPUFUNC(op_4e70_13), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ (cpuop_func*)CPUFUNC(op_4e71_13), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ (cpuop_func*)CPUFUNC(op_4e72_13), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ (cpuop_func*)CPUFUNC(op_4e73_13), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4e74_13), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4e75_13), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ (cpuop_func*)CPUFUNC(op_4e76_13), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ (cpuop_func*)CPUFUNC(op_4e77_13), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4e7a_13), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4e7b_13), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4e90_13), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ea8_13), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb0_13), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb8_13), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb9_13), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eba_13), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ebb_13), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ed0_13), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ee8_13), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef0_13), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef8_13), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef9_13), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4efa_13), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4efb_13), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_5000_13), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5010_13), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5018_13), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5020_13), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5028_13), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5030_13), 0x5030, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5038_13), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5039_13), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5040_13), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5048_13), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_5050_13), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5058_13), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5060_13), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5068_13), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5070_13), 0x5070, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5078_13), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5079_13), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5080_13), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5088_13), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_5090_13), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5098_13), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50a0_13), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50a8_13), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b0_13), 0x50b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b8_13), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b9_13), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50c0_13), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50c8_13), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_50d0_13), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50d8_13), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50e0_13), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50e8_13), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f0_13), 0x50f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f8_13), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f9_13), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5100_13), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5110_13), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5118_13), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5120_13), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5128_13), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5130_13), 0x5130, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5138_13), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5139_13), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5140_13), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5148_13), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_5150_13), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5158_13), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5160_13), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5168_13), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5170_13), 0x5170, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5178_13), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5179_13), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5180_13), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5188_13), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_5190_13), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5198_13), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51a0_13), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51a8_13), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b0_13), 0x51b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b8_13), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b9_13), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51c0_13), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51c8_13), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_51d0_13), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51d8_13), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51e0_13), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51e8_13), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f0_13), 0x51f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f8_13), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f9_13), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52c0_13), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52c8_13), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_52d0_13), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52d8_13), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52e0_13), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52e8_13), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f0_13), 0x52f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f8_13), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f9_13), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53c0_13), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53c8_13), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_53d0_13), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53d8_13), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53e0_13), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53e8_13), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f0_13), 0x53f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f8_13), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f9_13), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54c0_13), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54c8_13), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_54d0_13), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54d8_13), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54e0_13), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54e8_13), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f0_13), 0x54f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f8_13), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f9_13), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55c0_13), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55c8_13), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_55d0_13), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55d8_13), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55e0_13), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55e8_13), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f0_13), 0x55f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f8_13), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f9_13), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56c0_13), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56c8_13), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_56d0_13), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56d8_13), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56e0_13), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56e8_13), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f0_13), 0x56f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f8_13), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f9_13), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57c0_13), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57c8_13), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_57d0_13), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57d8_13), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57e0_13), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57e8_13), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f0_13), 0x57f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f8_13), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f9_13), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58c0_13), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58c8_13), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_58d0_13), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58d8_13), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58e0_13), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58e8_13), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f0_13), 0x58f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f8_13), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f9_13), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59c0_13), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59c8_13), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_59d0_13), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59d8_13), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59e0_13), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59e8_13), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f0_13), 0x59f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f8_13), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f9_13), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ac0_13), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ac8_13), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5ad0_13), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ad8_13), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ae0_13), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ae8_13), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af0_13), 0x5af0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af8_13), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af9_13), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bc0_13), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bc8_13), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5bd0_13), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bd8_13), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5be0_13), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5be8_13), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf0_13), 0x5bf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf8_13), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf9_13), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cc0_13), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cc8_13), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5cd0_13), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cd8_13), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ce0_13), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ce8_13), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf0_13), 0x5cf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf8_13), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf9_13), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dc0_13), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dc8_13), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5dd0_13), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dd8_13), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5de0_13), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5de8_13), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df0_13), 0x5df0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df8_13), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df9_13), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ec0_13), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ec8_13), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5ed0_13), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ed8_13), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ee0_13), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ee8_13), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef0_13), 0x5ef0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef8_13), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef9_13), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fc0_13), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fc8_13), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5fd0_13), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fd8_13), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fe0_13), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fe8_13), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff0_13), 0x5ff0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff8_13), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff9_13), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_6000_13), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6001_13), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_60ff_13), 0x60ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6100_13), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_6101_13), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_61ff_13), 0x61ff, 2, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_6200_13), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6201_13), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_62ff_13), 0x62ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6300_13), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6301_13), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_63ff_13), 0x63ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6400_13), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6401_13), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_64ff_13), 0x64ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6500_13), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6501_13), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_65ff_13), 0x65ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6600_13), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6601_13), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_66ff_13), 0x66ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6700_13), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6701_13), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_67ff_13), 0x67ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6800_13), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6801_13), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_68ff_13), 0x68ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6900_13), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6901_13), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_69ff_13), 0x69ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6a00_13), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6a01_13), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6aff_13), 0x6aff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6b00_13), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6b01_13), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6bff_13), 0x6bff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6c00_13), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6c01_13), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6cff_13), 0x6cff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6d00_13), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6d01_13), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6dff_13), 0x6dff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6e00_13), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6e01_13), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6eff_13), 0x6eff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6f00_13), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6f01_13), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6fff_13), 0x6fff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_7000_13), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_8000_13), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8010_13), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8018_13), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8020_13), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8028_13), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8030_13), 0x8030, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8038_13), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8039_13), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803a_13), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803b_13), 0x803b, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803c_13), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8040_13), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8050_13), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8058_13), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8060_13), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8068_13), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8070_13), 0x8070, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8078_13), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8079_13), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807a_13), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807b_13), 0x807b, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807c_13), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8080_13), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8090_13), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8098_13), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80a0_13), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80a8_13), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b0_13), 0x80b0, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b8_13), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b9_13), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80ba_13), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80bb_13), 0x80bb, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80bc_13), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80c0_13), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80d0_13), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80d8_13), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80e0_13), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80e8_13), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f0_13), 0x80f0, 4, { 4, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f8_13), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f9_13), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fa_13), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fb_13), 0x80fb, 4, { 4, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fc_13), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_8100_13), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ (cpuop_func*)CPUFUNC(op_8108_13), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ (cpuop_func*)CPUFUNC(op_8110_13), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8118_13), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8120_13), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8128_13), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8130_13), 0x8130, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8138_13), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8139_13), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8150_13), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8158_13), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8160_13), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8168_13), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8170_13), 0x8170, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8178_13), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8179_13), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8190_13), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8198_13), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81a0_13), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81a8_13), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b0_13), 0x81b0, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b8_13), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b9_13), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81c0_13), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81d0_13), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81d8_13), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81e0_13), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81e8_13), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f0_13), 0x81f0, 4, { 4, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f8_13), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f9_13), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fa_13), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fb_13), 0x81fb, 4, { 4, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fc_13), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_9000_13), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9010_13), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9018_13), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9020_13), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9028_13), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9030_13), 0x9030, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9038_13), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9039_13), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903a_13), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903b_13), 0x903b, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903c_13), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9040_13), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9048_13), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9050_13), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9058_13), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9060_13), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9068_13), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9070_13), 0x9070, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9078_13), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9079_13), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907a_13), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907b_13), 0x907b, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907c_13), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9080_13), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9088_13), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9090_13), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9098_13), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90a0_13), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90a8_13), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b0_13), 0x90b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b8_13), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b9_13), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90ba_13), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90bb_13), 0x90bb, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90bc_13), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90c0_13), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90c8_13), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90d0_13), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90d8_13), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90e0_13), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90e8_13), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f0_13), 0x90f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f8_13), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f9_13), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fa_13), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fb_13), 0x90fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fc_13), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_9100_13), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9108_13), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9110_13), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9118_13), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9120_13), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9128_13), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9130_13), 0x9130, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9138_13), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9139_13), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9140_13), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9148_13), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9150_13), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9158_13), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9160_13), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9168_13), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9170_13), 0x9170, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9178_13), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9179_13), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9180_13), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9188_13), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9190_13), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9198_13), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91a0_13), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91a8_13), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b0_13), 0x91b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b8_13), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b9_13), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91c0_13), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91c8_13), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91d0_13), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91d8_13), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91e0_13), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91e8_13), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f0_13), 0x91f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f8_13), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f9_13), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fa_13), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fb_13), 0x91fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fc_13), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_b000_13), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b010_13), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b018_13), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b020_13), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b028_13), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b030_13), 0xb030, 4, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b038_13), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b039_13), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03a_13), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03b_13), 0xb03b, 4, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03c_13), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b040_13), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b048_13), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b050_13), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b058_13), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b060_13), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b068_13), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b070_13), 0xb070, 4, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b078_13), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b079_13), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07a_13), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07b_13), 0xb07b, 4, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07c_13), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b080_13), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b088_13), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b090_13), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b098_13), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0a0_13), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0a8_13), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b0_13), 0xb0b0, 4, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b8_13), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b9_13), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0ba_13), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0bb_13), 0xb0bb, 4, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0bc_13), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0c0_13), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0c8_13), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0d0_13), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0d8_13), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0e0_13), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0e8_13), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f0_13), 0xb0f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f8_13), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f9_13), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fa_13), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fb_13), 0xb0fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fc_13), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b100_13), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b108_13), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b110_13), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b118_13), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b120_13), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b128_13), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b130_13), 0xb130, 4, { 4, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b138_13), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b139_13), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b140_13), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b148_13), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b150_13), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b158_13), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b160_13), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b168_13), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b170_13), 0xb170, 4, { 4, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b178_13), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b179_13), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b180_13), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b188_13), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b190_13), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b198_13), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1a0_13), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1a8_13), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b0_13), 0xb1b0, 4, { 4, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b8_13), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b9_13), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1c0_13), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1c8_13), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1d0_13), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1d8_13), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1e0_13), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1e8_13), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f0_13), 0xb1f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f8_13), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f9_13), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fa_13), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fb_13), 0xb1fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fc_13), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_c000_13), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c010_13), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c018_13), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c020_13), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c028_13), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c030_13), 0xc030, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c038_13), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c039_13), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03a_13), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03b_13), 0xc03b, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03c_13), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c040_13), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c050_13), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c058_13), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c060_13), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c068_13), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c070_13), 0xc070, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c078_13), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c079_13), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07a_13), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07b_13), 0xc07b, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07c_13), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c080_13), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c090_13), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c098_13), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0a0_13), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0a8_13), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b0_13), 0xc0b0, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b8_13), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b9_13), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0ba_13), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0bb_13), 0xc0bb, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0bc_13), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0c0_13), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0d0_13), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0d8_13), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0e0_13), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0e8_13), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f0_13), 0xc0f0, 4, { 4, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f8_13), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f9_13), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fa_13), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fb_13), 0xc0fb, 4, { 4, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fc_13), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c100_13), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ (cpuop_func*)CPUFUNC(op_c108_13), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ (cpuop_func*)CPUFUNC(op_c110_13), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c118_13), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c120_13), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c128_13), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c130_13), 0xc130, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c138_13), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c139_13), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c140_13), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c148_13), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c150_13), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c158_13), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c160_13), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c168_13), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c170_13), 0xc170, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c178_13), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c179_13), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c188_13), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c190_13), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c198_13), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1a0_13), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1a8_13), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b0_13), 0xc1b0, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b8_13), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b9_13), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1c0_13), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1d0_13), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1d8_13), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1e0_13), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1e8_13), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f0_13), 0xc1f0, 4, { 4, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f8_13), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f9_13), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fa_13), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fb_13), 0xc1fb, 4, { 4, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fc_13), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_d000_13), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d010_13), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d018_13), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d020_13), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d028_13), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d030_13), 0xd030, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d038_13), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d039_13), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03a_13), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03b_13), 0xd03b, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03c_13), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d040_13), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d048_13), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d050_13), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d058_13), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d060_13), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d068_13), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d070_13), 0xd070, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d078_13), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d079_13), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07a_13), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07b_13), 0xd07b, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07c_13), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d080_13), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d088_13), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d090_13), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d098_13), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0a0_13), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0a8_13), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b0_13), 0xd0b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b8_13), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b9_13), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0ba_13), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0bb_13), 0xd0bb, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0bc_13), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0c0_13), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0c8_13), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0d0_13), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0d8_13), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0e0_13), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0e8_13), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f0_13), 0xd0f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f8_13), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f9_13), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fa_13), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fb_13), 0xd0fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fc_13), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d100_13), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d108_13), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d110_13), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d118_13), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d120_13), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d128_13), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d130_13), 0xd130, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d138_13), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d139_13), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d140_13), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d148_13), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d150_13), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d158_13), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d160_13), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d168_13), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d170_13), 0xd170, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d178_13), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d179_13), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d180_13), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d188_13), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d190_13), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d198_13), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1a0_13), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1a8_13), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b0_13), 0xd1b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b8_13), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b9_13), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1c0_13), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1c8_13), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1d0_13), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1d8_13), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1e0_13), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1e8_13), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f0_13), 0xd1f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f8_13), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f9_13), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fa_13), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fb_13), 0xd1fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fc_13), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_e000_13), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e008_13), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e010_13), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e018_13), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e020_13), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e028_13), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e030_13), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e038_13), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e040_13), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e048_13), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e050_13), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e058_13), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e060_13), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e068_13), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e070_13), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e078_13), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e080_13), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e088_13), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e090_13), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e098_13), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e0a0_13), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e0a8_13), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e0b0_13), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e0b8_13), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e0d0_13), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0d8_13), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0e0_13), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0e8_13), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f0_13), 0xe0f0, 4, { 4, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f8_13), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f9_13), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e100_13), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e108_13), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e110_13), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e118_13), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e120_13), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e128_13), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e130_13), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e138_13), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e140_13), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e148_13), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e150_13), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e158_13), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e160_13), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e168_13), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e170_13), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e178_13), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e180_13), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e188_13), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e190_13), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e198_13), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e1a0_13), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e1a8_13), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e1b0_13), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e1b8_13), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e1d0_13), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1d8_13), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1e0_13), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1e8_13), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f0_13), 0xe1f0, 4, { 4, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f8_13), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f9_13), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e2d0_13), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2d8_13), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2e0_13), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2e8_13), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f0_13), 0xe2f0, 4, { 4, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f8_13), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f9_13), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e3d0_13), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3d8_13), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3e0_13), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3e8_13), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f0_13), 0xe3f0, 4, { 4, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f8_13), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f9_13), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e4d0_13), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4d8_13), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4e0_13), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4e8_13), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f0_13), 0xe4f0, 4, { 4, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f8_13), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f9_13), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e5d0_13), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5d8_13), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5e0_13), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5e8_13), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f0_13), 0xe5f0, 4, { 4, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f8_13), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f9_13), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e6d0_13), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6d8_13), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6e0_13), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6e8_13), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f0_13), 0xe6f0, 4, { 4, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f8_13), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f9_13), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e7d0_13), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7d8_13), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7e0_13), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7e8_13), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f0_13), 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f8_13), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f9_13), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ 0, 0 }};
+#endif /* CPUEMU_13 */
+const struct cputbl CPUFUNC(op_smalltbl_14)[] = {
+{ (cpuop_func*)CPUFUNC(op_0000_13), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0010_13), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0018_13), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0020_13), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0028_13), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0030_13), 0x0030, 6, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0038_13), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0039_13), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_003c_13), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ (cpuop_func*)CPUFUNC(op_0040_13), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0050_13), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0058_13), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0060_13), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0068_13), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0070_13), 0x0070, 6, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0078_13), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0079_13), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_007c_13), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ (cpuop_func*)CPUFUNC(op_0080_13), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0090_13), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0098_13), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00a0_13), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00a8_13), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b0_13), 0x00b0, 8, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b8_13), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b9_13), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0100_13), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0108_13), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ (cpuop_func*)CPUFUNC(op_0110_13), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0118_13), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0120_13), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0128_13), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0130_13), 0x0130, 4, { 4, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0138_13), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0139_13), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013a_13), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013b_13), 0x013b, 4, { 4, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013c_13), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0140_13), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0148_13), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ (cpuop_func*)CPUFUNC(op_0150_13), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0158_13), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0160_13), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0168_13), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0170_13), 0x0170, 4, { 4, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0178_13), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0179_13), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0180_13), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0188_13), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ (cpuop_func*)CPUFUNC(op_0190_13), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0198_13), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01a0_13), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01a8_13), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b0_13), 0x01b0, 4, { 4, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b8_13), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b9_13), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01c0_13), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01c8_13), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ (cpuop_func*)CPUFUNC(op_01d0_13), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01d8_13), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01e0_13), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01e8_13), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f0_13), 0x01f0, 4, { 4, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f8_13), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f9_13), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_0200_13), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0210_13), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0218_13), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0220_13), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0228_13), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0230_13), 0x0230, 6, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0238_13), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0239_13), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_023c_13), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ (cpuop_func*)CPUFUNC(op_0240_13), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0250_13), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0258_13), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0260_13), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0268_13), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0270_13), 0x0270, 6, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0278_13), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0279_13), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_027c_13), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ (cpuop_func*)CPUFUNC(op_0280_13), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0290_13), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0298_13), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02a0_13), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02a8_13), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b0_13), 0x02b0, 8, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b8_13), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b9_13), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0400_13), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0410_13), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0418_13), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0420_13), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0428_13), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0430_13), 0x0430, 6, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0438_13), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0439_13), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0440_13), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0450_13), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0458_13), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0460_13), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0468_13), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0470_13), 0x0470, 6, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0478_13), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0479_13), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0480_13), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0490_13), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0498_13), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04a0_13), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04a8_13), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b0_13), 0x04b0, 8, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b8_13), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b9_13), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0600_13), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0610_13), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0618_13), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0620_13), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0628_13), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0630_13), 0x0630, 6, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0638_13), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0639_13), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0640_13), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0650_13), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0658_13), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0660_13), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0668_13), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0670_13), 0x0670, 6, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0678_13), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0679_13), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0680_13), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0690_13), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0698_13), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06a0_13), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06a8_13), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b0_13), 0x06b0, 8, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b8_13), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b9_13), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0800_13), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0810_13), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0818_13), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0820_13), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0828_13), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0830_13), 0x0830, 6, { 4, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0838_13), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0839_13), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_083a_13), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_083b_13), 0x083b, 6, { 4, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0840_13), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0850_13), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0858_13), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0860_13), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0868_13), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0870_13), 0x0870, 6, { 4, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0878_13), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0879_13), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0880_13), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0890_13), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0898_13), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08a0_13), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08a8_13), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b0_13), 0x08b0, 6, { 4, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b8_13), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b9_13), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08c0_13), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08d0_13), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08d8_13), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08e0_13), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08e8_13), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f0_13), 0x08f0, 6, { 4, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f8_13), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f9_13), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_0a00_13), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a10_13), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a18_13), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a20_13), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a28_13), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a30_13), 0x0a30, 6, { 4, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a38_13), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a39_13), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a3c_13), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ (cpuop_func*)CPUFUNC(op_0a40_13), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a50_13), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a58_13), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a60_13), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a68_13), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a70_13), 0x0a70, 6, { 4, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a78_13), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a79_13), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a7c_13), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ (cpuop_func*)CPUFUNC(op_0a80_13), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a90_13), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a98_13), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0aa0_13), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0aa8_13), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab0_13), 0x0ab0, 8, { 4, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab8_13), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab9_13), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0c00_13), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c10_13), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c18_13), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c20_13), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c28_13), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c30_13), 0x0c30, 6, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c38_13), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c39_13), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c40_13), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c50_13), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c58_13), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c60_13), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c68_13), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c70_13), 0x0c70, 6, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c78_13), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c79_13), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c80_13), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c90_13), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c98_13), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0ca0_13), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0ca8_13), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb0_13), 0x0cb0, 8, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb8_13), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb9_13), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_1000_13), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1010_13), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1018_13), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1020_13), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1028_13), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1030_13), 0x1030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1038_13), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1039_13), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103a_13), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103b_13), 0x103b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103c_13), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1080_13), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1090_13), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1098_13), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10a0_13), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10a8_13), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b0_13), 0x10b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b8_13), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b9_13), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10ba_13), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10bb_13), 0x10bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10bc_13), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10c0_13), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10d0_13), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10d8_13), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10e0_13), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10e8_13), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f0_13), 0x10f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f8_13), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f9_13), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fa_13), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fb_13), 0x10fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fc_13), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1100_13), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1110_13), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1118_13), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1120_13), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1128_13), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1130_13), 0x1130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1138_13), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1139_13), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113a_13), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113b_13), 0x113b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113c_13), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1140_13), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1150_13), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1158_13), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1160_13), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1168_13), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1170_13), 0x1170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1178_13), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1179_13), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117a_13), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117b_13), 0x117b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117c_13), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1180_13), 0x1180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1190_13), 0x1190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1198_13), 0x1198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11a0_13), 0x11a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11a8_13), 0x11a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b0_13), 0x11b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b8_13), 0x11b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b9_13), 0x11b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11ba_13), 0x11ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11bb_13), 0x11bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11bc_13), 0x11bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11c0_13), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11d0_13), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11d8_13), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11e0_13), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11e8_13), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f0_13), 0x11f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f8_13), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f9_13), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fa_13), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fb_13), 0x11fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fc_13), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13c0_13), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13d0_13), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13d8_13), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13e0_13), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13e8_13), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f0_13), 0x13f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f8_13), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f9_13), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fa_13), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fb_13), 0x13fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fc_13), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2000_13), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2008_13), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2010_13), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2018_13), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2020_13), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2028_13), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2030_13), 0x2030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2038_13), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2039_13), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203a_13), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203b_13), 0x203b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203c_13), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2040_13), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2048_13), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2050_13), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2058_13), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2060_13), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2068_13), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2070_13), 0x2070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2078_13), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2079_13), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207a_13), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207b_13), 0x207b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207c_13), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2080_13), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2088_13), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2090_13), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2098_13), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20a0_13), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20a8_13), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b0_13), 0x20b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b8_13), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b9_13), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20ba_13), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20bb_13), 0x20bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20bc_13), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20c0_13), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20c8_13), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20d0_13), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20d8_13), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20e0_13), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20e8_13), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f0_13), 0x20f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f8_13), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f9_13), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fa_13), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fb_13), 0x20fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fc_13), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2100_13), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2108_13), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2110_13), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2118_13), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2120_13), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2128_13), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2130_13), 0x2130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2138_13), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2139_13), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213a_13), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213b_13), 0x213b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213c_13), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2140_13), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2148_13), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2150_13), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2158_13), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2160_13), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2168_13), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2170_13), 0x2170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2178_13), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2179_13), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217a_13), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217b_13), 0x217b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217c_13), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2180_13), 0x2180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2188_13), 0x2188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2190_13), 0x2190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2198_13), 0x2198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21a0_13), 0x21a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21a8_13), 0x21a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b0_13), 0x21b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b8_13), 0x21b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b9_13), 0x21b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21ba_13), 0x21ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21bb_13), 0x21bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21bc_13), 0x21bc, 8, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21c0_13), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21c8_13), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21d0_13), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21d8_13), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21e0_13), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21e8_13), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f0_13), 0x21f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f8_13), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f9_13), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fa_13), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fb_13), 0x21fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fc_13), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23c0_13), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23c8_13), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23d0_13), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23d8_13), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23e0_13), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23e8_13), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f0_13), 0x23f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f8_13), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f9_13), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fa_13), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fb_13), 0x23fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fc_13), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3000_13), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3008_13), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3010_13), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3018_13), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3020_13), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3028_13), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3030_13), 0x3030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3038_13), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3039_13), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303a_13), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303b_13), 0x303b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303c_13), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3040_13), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3048_13), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3050_13), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3058_13), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3060_13), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3068_13), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3070_13), 0x3070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3078_13), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3079_13), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307a_13), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307b_13), 0x307b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307c_13), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3080_13), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3088_13), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3090_13), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3098_13), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30a0_13), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30a8_13), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b0_13), 0x30b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b8_13), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b9_13), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30ba_13), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30bb_13), 0x30bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30bc_13), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30c0_13), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30c8_13), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30d0_13), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30d8_13), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30e0_13), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30e8_13), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f0_13), 0x30f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f8_13), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f9_13), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fa_13), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fb_13), 0x30fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fc_13), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3100_13), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3108_13), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3110_13), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3118_13), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3120_13), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3128_13), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3130_13), 0x3130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3138_13), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3139_13), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313a_13), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313b_13), 0x313b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313c_13), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3140_13), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3148_13), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3150_13), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3158_13), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3160_13), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3168_13), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3170_13), 0x3170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3178_13), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3179_13), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317a_13), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317b_13), 0x317b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317c_13), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3180_13), 0x3180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3188_13), 0x3188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3190_13), 0x3190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3198_13), 0x3198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31a0_13), 0x31a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31a8_13), 0x31a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b0_13), 0x31b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b8_13), 0x31b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b9_13), 0x31b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31ba_13), 0x31ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31bb_13), 0x31bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31bc_13), 0x31bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31c0_13), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31c8_13), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31d0_13), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31d8_13), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31e0_13), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31e8_13), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f0_13), 0x31f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f8_13), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f9_13), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fa_13), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fb_13), 0x31fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fc_13), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33c0_13), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33c8_13), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33d0_13), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33d8_13), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33e0_13), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33e8_13), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f0_13), 0x33f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f8_13), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f9_13), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fa_13), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fb_13), 0x33fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fc_13), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_4000_13), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4010_13), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4018_13), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4020_13), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4028_13), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4030_13), 0x4030, 4, { 4, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4038_13), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4039_13), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4040_13), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4050_13), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4058_13), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4060_13), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4068_13), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4070_13), 0x4070, 4, { 4, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4078_13), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4079_13), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4080_13), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4090_13), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4098_13), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40a0_13), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40a8_13), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b0_13), 0x40b0, 4, { 4, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b8_13), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b9_13), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40c0_14), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40d0_14), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40d8_14), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40e0_14), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40e8_14), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f0_14), 0x40f0, 4, { 4, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f8_14), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f9_14), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_4180_13), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4190_13), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4198_13), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41a0_13), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41a8_13), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b0_13), 0x41b0, 4, { 4, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b8_13), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b9_13), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41ba_13), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41bb_13), 0x41bb, 4, { 4, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41bc_13), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41d0_13), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41e8_13), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f0_13), 0x41f0, 4, { 4, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f8_13), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f9_13), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41fa_13), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41fb_13), 0x41fb, 4, { 4, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_4200_14), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4210_14), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4218_14), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4220_14), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4228_14), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4230_14), 0x4230, 4, { 4, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4238_14), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4239_14), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4240_14), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4250_14), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4258_14), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4260_14), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4268_14), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4270_14), 0x4270, 4, { 4, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4278_14), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4279_14), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4280_14), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4290_14), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4298_14), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42a0_14), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42a8_14), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b0_14), 0x42b0, 4, { 4, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b8_14), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b9_14), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4400_13), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4410_13), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4418_13), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4420_13), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4428_13), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4430_13), 0x4430, 4, { 4, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4438_13), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4439_13), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4440_13), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4450_13), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4458_13), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4460_13), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4468_13), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4470_13), 0x4470, 4, { 4, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4478_13), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4479_13), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4480_13), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4490_13), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4498_13), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44a0_13), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44a8_13), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b0_13), 0x44b0, 4, { 4, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b8_13), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b9_13), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44c0_13), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44d0_13), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44d8_13), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44e0_13), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44e8_13), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f0_13), 0x44f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f8_13), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f9_13), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fa_13), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fb_13), 0x44fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fc_13), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_4600_13), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4610_13), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4618_13), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4620_13), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4628_13), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4630_13), 0x4630, 4, { 4, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4638_13), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4639_13), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4640_13), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4650_13), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4658_13), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4660_13), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4668_13), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4670_13), 0x4670, 4, { 4, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4678_13), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4679_13), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4680_13), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4690_13), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4698_13), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46a0_13), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46a8_13), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b0_13), 0x46b0, 4, { 4, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b8_13), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b9_13), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46c0_13), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46d0_13), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46d8_13), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46e0_13), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46e8_13), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f0_13), 0x46f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f8_13), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f9_13), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fa_13), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fb_13), 0x46fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fc_13), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_4800_13), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4810_13), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4818_13), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4820_13), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4828_13), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4830_13), 0x4830, 4, { 4, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4838_13), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4839_13), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4840_13), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ (cpuop_func*)CPUFUNC(op_4850_13), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4868_13), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4870_13), 0x4870, 4, { 4, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4878_13), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4879_13), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_487a_13), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_487b_13), 0x487b, 4, { 4, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4880_13), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ (cpuop_func*)CPUFUNC(op_4890_13), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48a0_13), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48a8_13), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b0_13), 0x48b0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b8_13), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b9_13), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48c0_13), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ (cpuop_func*)CPUFUNC(op_48d0_13), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48e0_13), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48e8_13), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f0_13), 0x48f0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f8_13), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f9_13), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_4a00_13), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a10_13), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a18_13), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a20_13), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a28_13), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a30_13), 0x4a30, 4, { 4, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a38_13), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a39_13), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a40_13), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a50_13), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a58_13), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a60_13), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a68_13), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a70_13), 0x4a70, 4, { 4, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a78_13), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a79_13), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a80_13), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a90_13), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a98_13), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4aa0_13), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4aa8_13), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab0_13), 0x4ab0, 4, { 4, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab8_13), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab9_13), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ac0_13), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ad0_13), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ad8_13), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ae0_13), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ae8_13), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af0_13), 0x4af0, 4, { 4, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af8_13), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af9_13), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4c90_13), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4c98_13), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4ca8_13), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb0_13), 0x4cb0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb8_13), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb9_13), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cba_13), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cbb_13), 0x4cbb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cd0_13), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cd8_13), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4ce8_13), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf0_13), 0x4cf0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf8_13), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf9_13), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cfa_13), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cfb_13), 0x4cfb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4e40_13), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ (cpuop_func*)CPUFUNC(op_4e50_13), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ (cpuop_func*)CPUFUNC(op_4e58_13), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ (cpuop_func*)CPUFUNC(op_4e60_13), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ (cpuop_func*)CPUFUNC(op_4e68_13), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ (cpuop_func*)CPUFUNC(op_4e70_13), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ (cpuop_func*)CPUFUNC(op_4e71_13), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ (cpuop_func*)CPUFUNC(op_4e72_13), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ (cpuop_func*)CPUFUNC(op_4e73_14), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+{ (cpuop_func*)CPUFUNC(op_4e75_13), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ (cpuop_func*)CPUFUNC(op_4e76_13), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ (cpuop_func*)CPUFUNC(op_4e77_13), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+{ (cpuop_func*)CPUFUNC(op_4e90_13), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ea8_13), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb0_13), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb8_13), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb9_13), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eba_13), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ebb_13), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ed0_13), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ee8_13), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef0_13), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef8_13), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef9_13), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4efa_13), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4efb_13), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_5000_13), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5010_13), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5018_13), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5020_13), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5028_13), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5030_13), 0x5030, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5038_13), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5039_13), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5040_13), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5048_13), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_5050_13), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5058_13), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5060_13), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5068_13), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5070_13), 0x5070, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5078_13), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5079_13), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5080_13), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5088_13), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_5090_13), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5098_13), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50a0_13), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50a8_13), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b0_13), 0x50b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b8_13), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b9_13), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50c0_14), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50c8_13), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_50d0_14), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50d8_14), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50e0_14), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50e8_14), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f0_14), 0x50f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f8_14), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f9_14), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5100_13), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5110_13), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5118_13), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5120_13), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5128_13), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5130_13), 0x5130, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5138_13), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5139_13), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5140_13), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5148_13), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_5150_13), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5158_13), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5160_13), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5168_13), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5170_13), 0x5170, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5178_13), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5179_13), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5180_13), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5188_13), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_5190_13), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5198_13), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51a0_13), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51a8_13), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b0_13), 0x51b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b8_13), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b9_13), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51c0_14), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51c8_13), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_51d0_14), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51d8_14), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51e0_14), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51e8_14), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f0_14), 0x51f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f8_14), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f9_14), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52c0_14), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52c8_13), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_52d0_14), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52d8_14), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52e0_14), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52e8_14), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f0_14), 0x52f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f8_14), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f9_14), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53c0_14), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53c8_13), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_53d0_14), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53d8_14), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53e0_14), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53e8_14), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f0_14), 0x53f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f8_14), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f9_14), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54c0_14), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54c8_13), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_54d0_14), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54d8_14), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54e0_14), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54e8_14), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f0_14), 0x54f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f8_14), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f9_14), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55c0_14), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55c8_13), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_55d0_14), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55d8_14), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55e0_14), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55e8_14), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f0_14), 0x55f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f8_14), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f9_14), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56c0_14), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56c8_13), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_56d0_14), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56d8_14), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56e0_14), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56e8_14), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f0_14), 0x56f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f8_14), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f9_14), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57c0_14), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57c8_13), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_57d0_14), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57d8_14), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57e0_14), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57e8_14), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f0_14), 0x57f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f8_14), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f9_14), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58c0_14), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58c8_13), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_58d0_14), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58d8_14), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58e0_14), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58e8_14), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f0_14), 0x58f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f8_14), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f9_14), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59c0_14), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59c8_13), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_59d0_14), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59d8_14), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59e0_14), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59e8_14), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f0_14), 0x59f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f8_14), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f9_14), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ac0_14), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ac8_13), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5ad0_14), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ad8_14), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ae0_14), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ae8_14), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af0_14), 0x5af0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af8_14), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af9_14), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bc0_14), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bc8_13), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5bd0_14), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bd8_14), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5be0_14), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5be8_14), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf0_14), 0x5bf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf8_14), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf9_14), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cc0_14), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cc8_13), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5cd0_14), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cd8_14), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ce0_14), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ce8_14), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf0_14), 0x5cf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf8_14), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf9_14), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dc0_14), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dc8_13), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5dd0_14), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dd8_14), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5de0_14), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5de8_14), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df0_14), 0x5df0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df8_14), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df9_14), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ec0_14), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ec8_13), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5ed0_14), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ed8_14), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ee0_14), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ee8_14), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef0_14), 0x5ef0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef8_14), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef9_14), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fc0_14), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fc8_13), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5fd0_14), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fd8_14), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fe0_14), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fe8_14), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff0_14), 0x5ff0, 4, { 4, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff8_14), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff9_14), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_6000_13), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6001_13), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_60ff_13), 0x60ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6100_13), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_6101_13), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_61ff_13), 0x61ff, 2, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_6200_13), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6201_13), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_62ff_13), 0x62ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6300_13), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6301_13), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_63ff_13), 0x63ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6400_13), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6401_13), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_64ff_13), 0x64ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6500_13), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6501_13), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_65ff_13), 0x65ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6600_13), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6601_13), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_66ff_13), 0x66ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6700_13), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6701_13), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_67ff_13), 0x67ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6800_13), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6801_13), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_68ff_13), 0x68ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6900_13), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6901_13), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_69ff_13), 0x69ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6a00_13), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6a01_13), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6aff_13), 0x6aff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6b00_13), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6b01_13), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6bff_13), 0x6bff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6c00_13), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6c01_13), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6cff_13), 0x6cff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6d00_13), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6d01_13), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6dff_13), 0x6dff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6e00_13), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6e01_13), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6eff_13), 0x6eff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6f00_13), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6f01_13), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6fff_13), 0x6fff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_7000_13), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_8000_13), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8010_13), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8018_13), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8020_13), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8028_13), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8030_13), 0x8030, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8038_13), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8039_13), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803a_13), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803b_13), 0x803b, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803c_13), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8040_13), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8050_13), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8058_13), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8060_13), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8068_13), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8070_13), 0x8070, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8078_13), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8079_13), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807a_13), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807b_13), 0x807b, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807c_13), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8080_13), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8090_13), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8098_13), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80a0_13), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80a8_13), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b0_13), 0x80b0, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b8_13), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b9_13), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80ba_13), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80bb_13), 0x80bb, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80bc_13), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80c0_13), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80d0_13), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80d8_13), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80e0_13), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80e8_13), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f0_13), 0x80f0, 4, { 4, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f8_13), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f9_13), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fa_13), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fb_13), 0x80fb, 4, { 4, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fc_13), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_8100_13), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ (cpuop_func*)CPUFUNC(op_8108_13), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ (cpuop_func*)CPUFUNC(op_8110_13), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8118_13), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8120_13), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8128_13), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8130_13), 0x8130, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8138_13), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8139_13), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8150_13), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8158_13), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8160_13), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8168_13), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8170_13), 0x8170, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8178_13), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8179_13), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8190_13), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8198_13), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81a0_13), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81a8_13), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b0_13), 0x81b0, 4, { 4, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b8_13), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b9_13), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81c0_13), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81d0_13), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81d8_13), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81e0_13), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81e8_13), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f0_13), 0x81f0, 4, { 4, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f8_13), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f9_13), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fa_13), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fb_13), 0x81fb, 4, { 4, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fc_13), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_9000_13), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9010_13), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9018_13), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9020_13), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9028_13), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9030_13), 0x9030, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9038_13), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9039_13), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903a_13), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903b_13), 0x903b, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903c_13), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9040_13), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9048_13), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9050_13), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9058_13), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9060_13), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9068_13), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9070_13), 0x9070, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9078_13), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9079_13), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907a_13), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907b_13), 0x907b, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907c_13), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9080_13), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9088_13), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9090_13), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9098_13), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90a0_13), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90a8_13), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b0_13), 0x90b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b8_13), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b9_13), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90ba_13), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90bb_13), 0x90bb, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90bc_13), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90c0_13), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90c8_13), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90d0_13), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90d8_13), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90e0_13), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90e8_13), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f0_13), 0x90f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f8_13), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f9_13), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fa_13), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fb_13), 0x90fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fc_13), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_9100_13), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9108_13), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9110_13), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9118_13), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9120_13), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9128_13), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9130_13), 0x9130, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9138_13), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9139_13), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9140_13), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9148_13), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9150_13), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9158_13), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9160_13), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9168_13), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9170_13), 0x9170, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9178_13), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9179_13), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9180_13), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9188_13), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9190_13), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9198_13), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91a0_13), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91a8_13), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b0_13), 0x91b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b8_13), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b9_13), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91c0_13), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91c8_13), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91d0_13), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91d8_13), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91e0_13), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91e8_13), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f0_13), 0x91f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f8_13), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f9_13), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fa_13), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fb_13), 0x91fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fc_13), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_b000_13), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b010_13), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b018_13), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b020_13), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b028_13), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b030_13), 0xb030, 4, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b038_13), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b039_13), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03a_13), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03b_13), 0xb03b, 4, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03c_13), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b040_13), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b048_13), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b050_13), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b058_13), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b060_13), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b068_13), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b070_13), 0xb070, 4, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b078_13), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b079_13), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07a_13), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07b_13), 0xb07b, 4, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07c_13), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b080_13), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b088_13), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b090_13), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b098_13), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0a0_13), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0a8_13), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b0_13), 0xb0b0, 4, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b8_13), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b9_13), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0ba_13), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0bb_13), 0xb0bb, 4, { 4, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0bc_13), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0c0_13), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0c8_13), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0d0_13), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0d8_13), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0e0_13), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0e8_13), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f0_13), 0xb0f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f8_13), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f9_13), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fa_13), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fb_13), 0xb0fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fc_13), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b100_13), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b108_13), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b110_13), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b118_13), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b120_13), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b128_13), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b130_13), 0xb130, 4, { 4, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b138_13), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b139_13), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b140_13), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b148_13), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b150_13), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b158_13), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b160_13), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b168_13), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b170_13), 0xb170, 4, { 4, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b178_13), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b179_13), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b180_13), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b188_13), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b190_13), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b198_13), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1a0_13), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1a8_13), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b0_13), 0xb1b0, 4, { 4, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b8_13), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b9_13), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1c0_13), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1c8_13), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1d0_13), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1d8_13), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1e0_13), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1e8_13), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f0_13), 0xb1f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f8_13), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f9_13), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fa_13), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fb_13), 0xb1fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fc_13), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_c000_13), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c010_13), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c018_13), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c020_13), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c028_13), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c030_13), 0xc030, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c038_13), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c039_13), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03a_13), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03b_13), 0xc03b, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03c_13), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c040_13), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c050_13), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c058_13), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c060_13), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c068_13), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c070_13), 0xc070, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c078_13), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c079_13), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07a_13), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07b_13), 0xc07b, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07c_13), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c080_13), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c090_13), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c098_13), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0a0_13), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0a8_13), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b0_13), 0xc0b0, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b8_13), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b9_13), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0ba_13), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0bb_13), 0xc0bb, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0bc_13), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0c0_13), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0d0_13), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0d8_13), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0e0_13), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0e8_13), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f0_13), 0xc0f0, 4, { 4, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f8_13), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f9_13), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fa_13), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fb_13), 0xc0fb, 4, { 4, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fc_13), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c100_13), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ (cpuop_func*)CPUFUNC(op_c108_13), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ (cpuop_func*)CPUFUNC(op_c110_13), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c118_13), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c120_13), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c128_13), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c130_13), 0xc130, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c138_13), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c139_13), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c140_13), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c148_13), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c150_13), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c158_13), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c160_13), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c168_13), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c170_13), 0xc170, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c178_13), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c179_13), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c188_13), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c190_13), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c198_13), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1a0_13), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1a8_13), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b0_13), 0xc1b0, 4, { 4, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b8_13), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b9_13), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1c0_13), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1d0_13), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1d8_13), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1e0_13), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1e8_13), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f0_13), 0xc1f0, 4, { 4, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f8_13), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f9_13), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fa_13), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fb_13), 0xc1fb, 4, { 4, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fc_13), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_d000_13), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d010_13), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d018_13), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d020_13), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d028_13), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d030_13), 0xd030, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d038_13), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d039_13), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03a_13), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03b_13), 0xd03b, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03c_13), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d040_13), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d048_13), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d050_13), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d058_13), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d060_13), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d068_13), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d070_13), 0xd070, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d078_13), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d079_13), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07a_13), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07b_13), 0xd07b, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07c_13), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d080_13), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d088_13), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d090_13), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d098_13), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0a0_13), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0a8_13), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b0_13), 0xd0b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b8_13), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b9_13), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0ba_13), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0bb_13), 0xd0bb, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0bc_13), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0c0_13), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0c8_13), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0d0_13), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0d8_13), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0e0_13), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0e8_13), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f0_13), 0xd0f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f8_13), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f9_13), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fa_13), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fb_13), 0xd0fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fc_13), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d100_13), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d108_13), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d110_13), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d118_13), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d120_13), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d128_13), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d130_13), 0xd130, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d138_13), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d139_13), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d140_13), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d148_13), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d150_13), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d158_13), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d160_13), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d168_13), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d170_13), 0xd170, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d178_13), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d179_13), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d180_13), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d188_13), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d190_13), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d198_13), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1a0_13), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1a8_13), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b0_13), 0xd1b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b8_13), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b9_13), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1c0_13), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1c8_13), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1d0_13), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1d8_13), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1e0_13), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1e8_13), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f0_13), 0xd1f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f8_13), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f9_13), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fa_13), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fb_13), 0xd1fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fc_13), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_e000_13), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e008_13), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e010_13), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e018_13), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e020_13), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e028_13), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e030_13), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e038_13), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e040_13), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e048_13), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e050_13), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e058_13), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e060_13), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e068_13), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e070_13), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e078_13), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e080_13), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e088_13), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e090_13), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e098_13), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e0a0_13), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e0a8_13), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e0b0_13), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e0b8_13), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e0d0_13), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0d8_13), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0e0_13), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0e8_13), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f0_13), 0xe0f0, 4, { 4, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f8_13), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f9_13), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e100_13), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e108_13), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e110_13), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e118_13), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e120_13), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e128_13), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e130_13), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e138_13), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e140_13), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e148_13), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e150_13), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e158_13), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e160_13), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e168_13), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e170_13), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e178_13), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e180_13), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e188_13), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e190_13), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e198_13), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e1a0_13), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e1a8_13), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e1b0_13), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e1b8_13), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e1d0_13), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1d8_13), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1e0_13), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1e8_13), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f0_13), 0xe1f0, 4, { 4, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f8_13), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f9_13), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e2d0_13), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2d8_13), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2e0_13), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2e8_13), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f0_13), 0xe2f0, 4, { 4, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f8_13), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f9_13), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e3d0_13), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3d8_13), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3e0_13), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3e8_13), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f0_13), 0xe3f0, 4, { 4, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f8_13), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f9_13), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e4d0_13), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4d8_13), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4e0_13), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4e8_13), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f0_13), 0xe4f0, 4, { 4, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f8_13), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f9_13), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e5d0_13), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5d8_13), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5e0_13), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5e8_13), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f0_13), 0xe5f0, 4, { 4, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f8_13), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f9_13), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e6d0_13), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6d8_13), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6e0_13), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6e8_13), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f0_13), 0xe6f0, 4, { 4, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f8_13), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f9_13), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e7d0_13), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7d8_13), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7e0_13), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7e8_13), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f0_13), 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f8_13), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f9_13), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ 0, 0 }};
+#ifdef CPUEMU_20
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_20)[] = {
+{ CPUFUNC(op_0000_20), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_20), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_20), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_20), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_20), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_20), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_20), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_20), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_20), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_20), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_20), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_20), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_20), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_20), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_20), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_20), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_20), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_20), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_20), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_20), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_20), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_20), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_20), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_20), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_20), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_20), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00d0_20), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00e8_20), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f0_20), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f8_20), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f9_20), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00fa_20), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00fb_20), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0100_20), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_20), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_20), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_20), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_20), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_20), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_20), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_20), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_20), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_20), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_20), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_20), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_20), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_20), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_20), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_20), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_20), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_20), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_20), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_20), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_20), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_20), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_20), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_20), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_20), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_20), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_20), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_20), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_20), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_20), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_20), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_20), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_20), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_20), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_20), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_20), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_20), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_20), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_20), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_20), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_20), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_20), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_20), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_20), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_20), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_20), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_20), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_20), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_20), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_20), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_20), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_20), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_20), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_20), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_20), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_20), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_20), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_20), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_20), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_20), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_20), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_20), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_20), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_20), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_20), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02d0_20), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02e8_20), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f0_20), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f8_20), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f9_20), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02fa_20), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02fb_20), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0400_20), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_20), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_20), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_20), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_20), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_20), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_20), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_20), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_20), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_20), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_20), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_20), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_20), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_20), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_20), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_20), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_20), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_20), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_20), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_20), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_20), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_20), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_20), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_20), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04d0_20), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04e8_20), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f0_20), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f8_20), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f9_20), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04fa_20), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04fb_20), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0600_20), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_20), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_20), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_20), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_20), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_20), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_20), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_20), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_20), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_20), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_20), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_20), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_20), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_20), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_20), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_20), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_20), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_20), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_20), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_20), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_20), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_20), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_20), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_20), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06c0_20), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06c8_20), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06d0_20), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06e8_20), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f0_20), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f8_20), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f9_20), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06fa_20), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06fb_20), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+{ CPUFUNC(op_0800_20), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_20), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_20), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_20), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_20), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_20), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_20), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_20), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_20), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_20), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_20), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_20), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_20), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_20), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_20), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_20), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_20), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_20), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_20), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_20), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_20), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_20), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_20), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_20), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_20), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_20), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_20), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_20), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_20), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_20), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_20), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_20), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_20), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_20), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_20), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_20), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_20), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_20), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_20), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_20), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_20), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_20), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_20), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_20), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_20), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_20), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_20), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_20), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_20), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_20), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_20), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_20), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_20), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_20), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_20), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_20), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_20), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_20), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_20), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_20), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ad0_20), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ad8_20), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ae0_20), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ae8_20), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af0_20), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af8_20), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af9_20), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+{ CPUFUNC(op_0c00_20), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_20), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_20), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_20), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_20), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_20), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_20), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_20), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c3a_20), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c3b_20), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ CPUFUNC(op_0c40_20), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_20), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_20), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_20), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_20), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_20), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_20), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_20), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c7a_20), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c7b_20), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ CPUFUNC(op_0c80_20), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_20), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_20), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_20), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_20), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_20), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_20), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_20), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cba_20), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cbb_20), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cd0_20), 0x0cd0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cd8_20), 0x0cd8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ce0_20), 0x0ce0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ce8_20), 0x0ce8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf0_20), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf8_20), 0x0cf8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf9_20), 0x0cf9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cfc_20), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e10_20), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e18_20), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e20_20), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e28_20), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e30_20), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e38_20), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e39_20), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e50_20), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e58_20), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e60_20), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e68_20), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e70_20), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e78_20), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e79_20), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e90_20), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e98_20), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ea0_20), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ea8_20), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb0_20), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb8_20), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb9_20), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ed0_20), 0x0ed0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ed8_20), 0x0ed8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ee0_20), 0x0ee0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ee8_20), 0x0ee8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef0_20), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef8_20), 0x0ef8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef9_20), 0x0ef9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0efc_20), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+{ CPUFUNC(op_1000_20), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_20), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_20), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_20), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_20), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_20), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_20), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_20), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_20), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_20), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_20), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_20), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_20), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_20), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_20), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_20), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_20), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_20), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_20), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_20), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_20), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_20), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_20), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_20), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_20), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_20), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_20), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_20), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_20), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_20), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_20), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_20), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_20), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_20), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_20), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_20), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_20), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_20), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_20), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_20), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_20), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_20), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_20), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_20), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_20), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_20), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_20), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_20), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_20), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_20), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_20), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_20), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_20), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_20), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_20), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_20), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_20), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_20), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_20), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_20), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_20), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_20), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_20), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_20), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_20), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_20), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_20), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_20), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_20), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_20), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_20), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_20), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_20), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_20), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_20), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_20), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_20), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_20), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_20), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_20), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_20), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_20), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_20), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_20), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_20), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_20), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_20), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_20), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_20), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_20), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_20), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_20), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_20), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_20), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_20), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_20), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_20), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_20), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_20), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_20), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_20), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_20), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_20), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_20), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_20), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_20), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_20), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_20), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_20), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_20), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_20), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_20), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_20), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_20), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_20), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_20), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_20), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_20), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_20), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_20), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_20), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_20), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_20), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_20), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_20), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_20), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_20), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_20), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_20), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_20), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_20), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_20), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_20), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_20), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_20), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_20), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_20), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_20), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_20), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_20), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_20), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_20), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_20), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_20), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_20), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_20), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_20), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_20), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_20), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_20), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_20), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_20), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_20), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_20), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_20), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_20), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_20), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_20), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_20), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_20), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_20), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_20), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_20), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_20), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_20), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_20), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_20), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_20), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_20), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_20), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_20), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_20), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_20), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_20), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_20), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_20), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_20), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_20), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_20), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_20), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_20), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_20), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_20), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_20), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_20), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_20), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_20), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_20), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_20), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_20), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_20), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_20), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_20), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_20), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_20), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_20), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_20), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_20), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_20), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_20), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_20), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_20), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_20), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_20), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_20), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_20), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_20), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_20), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_20), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_20), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_20), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_20), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_20), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_20), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_20), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_20), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_20), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_20), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_20), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_20), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_20), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_20), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_20), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_20), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_20), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_20), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_20), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_20), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_20), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_20), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_20), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_20), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_20), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_20), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_20), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_20), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_20), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_20), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_20), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_20), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_20), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_20), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_20), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_20), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_20), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_20), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_20), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_20), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_20), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_20), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_20), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_20), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_20), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_20), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_20), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_20), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_20), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_20), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_20), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_20), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_20), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_20), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_20), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_20), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_20), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_20), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_20), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_20), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_20), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_20), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_20), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_20), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_20), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_20), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_20), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_20), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_20), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_20), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_20), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_20), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_20), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_20), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_20), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_20), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_20), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_20), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_20), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_20), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_20), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_20), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_20), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_20), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_20), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_20), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_20), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_20), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_20), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_20), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_20), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_20), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_20), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_20), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_20), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_20), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_20), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_20), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_20), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_20), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_20), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_20), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_20), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_20), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_20), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_20), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_20), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_20), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_20), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_20), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_20), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_20), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_20), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_20), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_20), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_20), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_20), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_20), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_20), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_20), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_20), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_20), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_20), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_20), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_20), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_20), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_20), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_20), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4100_20), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4110_20), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4118_20), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4120_20), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4128_20), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4130_20), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4138_20), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4139_20), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413a_20), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413b_20), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413c_20), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+{ CPUFUNC(op_4180_20), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_20), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_20), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_20), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_20), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_20), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_20), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_20), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_20), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_20), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_20), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_20), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_20), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_20), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_20), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_20), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_20), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_20), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_20), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_20), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_20), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_20), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_20), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_20), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_20), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_20), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_20), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_20), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_20), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_20), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_20), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_20), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_20), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_20), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_20), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_20), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_20), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_20), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_20), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_20), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_20), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_20), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42c0_20), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d0_20), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d8_20), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e0_20), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e8_20), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f0_20), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f8_20), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f9_20), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+{ CPUFUNC(op_4400_20), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_20), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_20), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_20), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_20), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_20), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_20), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_20), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_20), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_20), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_20), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_20), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_20), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_20), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_20), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_20), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_20), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_20), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_20), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_20), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_20), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_20), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_20), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_20), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_20), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_20), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_20), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_20), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_20), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_20), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_20), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_20), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_20), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_20), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_20), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_20), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_20), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_20), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_20), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_20), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_20), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_20), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_20), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_20), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_20), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_20), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_20), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_20), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_20), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_20), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_20), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_20), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_20), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_20), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_20), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_20), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_20), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_20), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_20), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_20), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_20), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_20), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_20), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_20), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_20), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_20), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_20), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_20), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_20), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_20), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_20), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4808_20), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#endif
+{ CPUFUNC(op_4810_20), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_20), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_20), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_20), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_20), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_20), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_20), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_20), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4848_20), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+#endif
+{ CPUFUNC(op_4850_20), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_20), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_20), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_20), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_20), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_20), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_20), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_20), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_20), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_20), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_20), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_20), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_20), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_20), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_20), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_20), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_20), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_20), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_20), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_20), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_20), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_49c0_20), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+#endif
+{ CPUFUNC(op_4a00_20), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_20), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_20), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_20), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_20), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_20), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_20), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_20), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3a_20), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3b_20), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3c_20), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a40_20), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a48_20), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a50_20), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_20), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_20), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_20), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_20), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_20), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_20), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7a_20), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7b_20), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7c_20), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a80_20), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a88_20), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a90_20), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_20), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_20), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_20), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_20), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_20), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_20), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4aba_20), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4abb_20), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4abc_20), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4ac0_20), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_20), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_20), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_20), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_20), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_20), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_20), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_20), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c00_20), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c10_20), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c18_20), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c20_20), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c28_20), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c30_20), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c38_20), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c39_20), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3a_20), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3b_20), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3c_20), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c40_20), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c50_20), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c58_20), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c60_20), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c68_20), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c70_20), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c78_20), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c79_20), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7a_20), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7b_20), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7c_20), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+{ CPUFUNC(op_4c90_20), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_20), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_20), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_20), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_20), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_20), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_20), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_20), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_20), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_20), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_20), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_20), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_20), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_20), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_20), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_20), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_20), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_20), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_20), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_20), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_20), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_20), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_20), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_20), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_20), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e74_20), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+#endif
+{ CPUFUNC(op_4e75_20), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_20), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_20), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7a_20), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7b_20), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+#endif
+{ CPUFUNC(op_4e90_20), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_20), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_20), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_20), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_20), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_20), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_20), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_20), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_20), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_20), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_20), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_20), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_20), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_20), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_20), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_20), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_20), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_20), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_20), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_20), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_20), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_20), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_20), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_20), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_20), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_20), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_20), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_20), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_20), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_20), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_20), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_20), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_20), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_20), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_20), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_20), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_20), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_20), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_20), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_20), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_20), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_20), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_20), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_20), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_20), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_20), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_20), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_20), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_20), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fa_20), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fb_20), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fc_20), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5100_20), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_20), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_20), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_20), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_20), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_20), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_20), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_20), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_20), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_20), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_20), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_20), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_20), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_20), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_20), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_20), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_20), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_20), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_20), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_20), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_20), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_20), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_20), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_20), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_20), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_20), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_20), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_20), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_20), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_20), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_20), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_20), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_20), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_20), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_20), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fa_20), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fb_20), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fc_20), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_52c0_20), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_20), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_20), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_20), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_20), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_20), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_20), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_20), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_20), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fa_20), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fb_20), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fc_20), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_53c0_20), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_20), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_20), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_20), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_20), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_20), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_20), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_20), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_20), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fa_20), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fb_20), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fc_20), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_54c0_20), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_20), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_20), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_20), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_20), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_20), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_20), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_20), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_20), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fa_20), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fb_20), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fc_20), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_55c0_20), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_20), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_20), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_20), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_20), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_20), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_20), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_20), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_20), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fa_20), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fb_20), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fc_20), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_56c0_20), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_20), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_20), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_20), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_20), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_20), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_20), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_20), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_20), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fa_20), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fb_20), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fc_20), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_57c0_20), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_20), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_20), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_20), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_20), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_20), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_20), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_20), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_20), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fa_20), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fb_20), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fc_20), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_58c0_20), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_20), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_20), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_20), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_20), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_20), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_20), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_20), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_20), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fa_20), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fb_20), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fc_20), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_59c0_20), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_20), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_20), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_20), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_20), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_20), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_20), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_20), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_20), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fa_20), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fb_20), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fc_20), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5ac0_20), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_20), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_20), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_20), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_20), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_20), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_20), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_20), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_20), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afa_20), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afb_20), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afc_20), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5bc0_20), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_20), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_20), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_20), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_20), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_20), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_20), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_20), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_20), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfa_20), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfb_20), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfc_20), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5cc0_20), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_20), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_20), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_20), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_20), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_20), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_20), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_20), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_20), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfa_20), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfb_20), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfc_20), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5dc0_20), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_20), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_20), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_20), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_20), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_20), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_20), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_20), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_20), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfa_20), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfb_20), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfc_20), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5ec0_20), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_20), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_20), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_20), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_20), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_20), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_20), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_20), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_20), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efa_20), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efb_20), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efc_20), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5fc0_20), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_20), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_20), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_20), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_20), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_20), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_20), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_20), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_20), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffa_20), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffb_20), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffc_20), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_6000_20), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_20), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_20), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6100_20), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_20), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_20), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_20), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_20), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_20), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6300_20), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_20), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_20), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6400_20), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_20), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_20), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6500_20), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_20), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_20), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6600_20), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_20), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_20), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6700_20), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_20), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_20), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6800_20), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_20), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_20), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6900_20), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_20), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_20), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a00_20), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_20), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_20), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b00_20), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_20), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_20), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c00_20), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_20), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_20), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d00_20), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_20), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_20), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e00_20), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_20), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_20), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f00_20), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_20), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_20), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_7000_20), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_20), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_20), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_20), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_20), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_20), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_20), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_20), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_20), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_20), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_20), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_20), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_20), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_20), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_20), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_20), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_20), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_20), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_20), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_20), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_20), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_20), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_20), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_20), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_20), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_20), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_20), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_20), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_20), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_20), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_20), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_20), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_20), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_20), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_20), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_20), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_20), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_20), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_20), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_20), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_20), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_20), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_20), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_20), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_20), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_20), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_20), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_20), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_20), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_20), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_20), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_20), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_20), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_20), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8140_20), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8148_20), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+{ CPUFUNC(op_8150_20), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_20), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_20), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_20), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_20), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_20), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_20), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8180_20), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8188_20), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+{ CPUFUNC(op_8190_20), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_20), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_20), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_20), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_20), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_20), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_20), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_20), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_20), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_20), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_20), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_20), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_20), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_20), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_20), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_20), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_20), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_20), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_20), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_20), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_20), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_20), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_20), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_20), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_20), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_20), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_20), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_20), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_20), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_20), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_20), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_20), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_20), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_20), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_20), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_20), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_20), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_20), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_20), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_20), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_20), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_20), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_20), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_20), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_20), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_20), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_20), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_20), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_20), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_20), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_20), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_20), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_20), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_20), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_20), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_20), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_20), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_20), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_20), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_20), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_20), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_20), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_20), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_20), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_20), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_20), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_20), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_20), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_20), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_20), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_20), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_20), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_20), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_20), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_20), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_20), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_20), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_20), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_20), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_20), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_20), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_20), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_20), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_20), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_20), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_20), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_20), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_20), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_20), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_20), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_20), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_20), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_20), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_20), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_20), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_20), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_20), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_20), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_20), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_20), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_20), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_20), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_20), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_20), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_20), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_20), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_20), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_20), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_20), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_20), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_20), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_20), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_20), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_20), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_20), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_20), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_20), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_20), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_20), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_20), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_20), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_20), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_20), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_20), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_20), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_20), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_20), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_20), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_20), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_20), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_20), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_20), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_20), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_20), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_20), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_20), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_20), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_20), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_20), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_20), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_20), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_20), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_20), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_20), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_20), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_20), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_20), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_20), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_20), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_20), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_20), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_20), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_20), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_20), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_20), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_20), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_20), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_20), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_20), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_20), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_20), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_20), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_20), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_20), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_20), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_20), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_20), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_20), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_20), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_20), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_20), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_20), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_20), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_20), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_20), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_20), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_20), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_20), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_20), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_20), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_20), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_20), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_20), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_20), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_20), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_20), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_20), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_20), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_20), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_20), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_20), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_20), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_20), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_20), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_20), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_20), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_20), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_20), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_20), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_20), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_20), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_20), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_20), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_20), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_20), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_20), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_20), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_20), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_20), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_20), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_20), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_20), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_20), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_20), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_20), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_20), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_20), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_20), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_20), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_20), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_20), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_20), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_20), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_20), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_20), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_20), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_20), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_20), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_20), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_20), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_20), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_20), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_20), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_20), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_20), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_20), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_20), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_20), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_20), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_20), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_20), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_20), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_20), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_20), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_20), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_20), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_20), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_20), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_20), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_20), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_20), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_20), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_20), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_20), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_20), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_20), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_20), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_20), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_20), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_20), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_20), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_20), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_20), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_20), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_20), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_20), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_20), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_20), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_20), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_20), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_20), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_20), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_20), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_20), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_20), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_20), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_20), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_20), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_20), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_20), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_20), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_20), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_20), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_20), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_20), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_20), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_20), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_20), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_20), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_20), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_20), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_20), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_20), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_20), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_20), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_20), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_20), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_20), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_20), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_20), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_20), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_20), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_20), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_20), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_20), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_20), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_20), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_20), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_20), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_20), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_20), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_20), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_20), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_20), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_20), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_20), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_20), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_20), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_20), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_20), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_20), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_20), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_20), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_20), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_20), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_20), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_20), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_20), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_20), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_20), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_20), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_20), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_20), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_20), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_20), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_20), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_20), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_20), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_20), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_20), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_20), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_20), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_20), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_20), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_20), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_20), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_20), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_20), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_20), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_20), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_20), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_20), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_20), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_20), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_20), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_20), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_20), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_20), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_20), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_20), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_20), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_20), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_20), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_20), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_20), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_20), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_20), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_20), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_20), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_20), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_20), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_20), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_20), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_20), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_20), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_20), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_20), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_20), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_20), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_20), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_20), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_20), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_20), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_20), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_20), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_20), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_20), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_20), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_20), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_20), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_20), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_20), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_20), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_20), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_20), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_20), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_20), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_20), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_20), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_20), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_20), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_20), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_20), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_20), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_20), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_20), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_20), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_20), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_20), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_20), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_20), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_20), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_20), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_20), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_20), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_20), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_20), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_20), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_20), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_20), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_20), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_20), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_20), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_20), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_20), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_20), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_20), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_20), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_20), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_20), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_20), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_20), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_20), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_20), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_20), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_20), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_20), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_20), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_20), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_20), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_20), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_20), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_20), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_20), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_20), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_20), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_20), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_20), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_20), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_20), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_20), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_20), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_20), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_20), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_20), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_20), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_20), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_20), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_20), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_20), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_20), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8c0_20), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8d0_20), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8e8_20), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f0_20), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f8_20), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f9_20), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8fa_20), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8fb_20), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9c0_20), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9d0_20), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9e8_20), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f0_20), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f8_20), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f9_20), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9fa_20), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9fb_20), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eac0_20), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ead0_20), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eae8_20), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf0_20), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf8_20), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf9_20), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebc0_20), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebd0_20), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebe8_20), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf0_20), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf8_20), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf9_20), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebfa_20), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebfb_20), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecc0_20), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecd0_20), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ece8_20), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf0_20), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf8_20), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf9_20), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edc0_20), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edd0_20), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ede8_20), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf0_20), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf8_20), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf9_20), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edfa_20), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edfb_20), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eec0_20), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eed0_20), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eee8_20), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef0_20), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef8_20), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef9_20), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efc0_20), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efd0_20), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efe8_20), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff0_20), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff8_20), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff9_20), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f200_20), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f208_20), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f210_20), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f218_20), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f220_20), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f228_20), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f230_20), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f238_20), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f239_20), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23a_20), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23b_20), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23c_20), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f240_20), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f248_20), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f250_20), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f258_20), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f260_20), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f268_20), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f270_20), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f278_20), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f279_20), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27a_20), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27b_20), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27c_20), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f280_20), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f2c0_20), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f310_20), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f320_20), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f328_20), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f330_20), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f338_20), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f339_20), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f350_20), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f358_20), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f368_20), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f370_20), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f378_20), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f379_20), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f37a_20), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f37b_20), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#endif /* CPUEMU_20 */
+#ifdef CPUEMU_21
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_21)[] = {
+{ (cpuop_func*)CPUFUNC(op_0000_21), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0010_21), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0018_21), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0020_21), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0028_21), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0030_21), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0038_21), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0039_21), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_003c_21), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ (cpuop_func*)CPUFUNC(op_0040_21), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0050_21), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0058_21), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0060_21), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0068_21), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0070_21), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0078_21), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0079_21), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_007c_21), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ (cpuop_func*)CPUFUNC(op_0080_21), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0090_21), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0098_21), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00a0_21), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00a8_21), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b0_21), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b8_21), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b9_21), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00d0_21), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00e8_21), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00f0_21), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00f8_21), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00f9_21), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00fa_21), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00fb_21), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0100_21), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0108_21), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ (cpuop_func*)CPUFUNC(op_0110_21), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0118_21), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0120_21), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0128_21), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0130_21), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0138_21), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0139_21), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013a_21), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013b_21), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013c_21), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0140_21), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0148_21), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ (cpuop_func*)CPUFUNC(op_0150_21), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0158_21), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0160_21), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0168_21), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0170_21), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0178_21), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0179_21), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0180_21), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0188_21), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ (cpuop_func*)CPUFUNC(op_0190_21), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0198_21), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01a0_21), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01a8_21), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b0_21), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b8_21), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b9_21), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01c0_21), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01c8_21), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ (cpuop_func*)CPUFUNC(op_01d0_21), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01d8_21), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01e0_21), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01e8_21), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f0_21), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f8_21), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f9_21), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_0200_21), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0210_21), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0218_21), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0220_21), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0228_21), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0230_21), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0238_21), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0239_21), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_023c_21), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ (cpuop_func*)CPUFUNC(op_0240_21), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0250_21), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0258_21), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0260_21), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0268_21), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0270_21), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0278_21), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0279_21), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_027c_21), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ (cpuop_func*)CPUFUNC(op_0280_21), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0290_21), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0298_21), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02a0_21), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02a8_21), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b0_21), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b8_21), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b9_21), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02d0_21), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02e8_21), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02f0_21), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02f8_21), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02f9_21), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02fa_21), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02fb_21), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0400_21), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0410_21), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0418_21), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0420_21), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0428_21), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0430_21), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0438_21), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0439_21), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0440_21), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0450_21), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0458_21), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0460_21), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0468_21), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0470_21), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0478_21), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0479_21), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0480_21), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0490_21), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0498_21), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04a0_21), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04a8_21), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b0_21), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b8_21), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b9_21), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04d0_21), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04e8_21), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04f0_21), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04f8_21), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04f9_21), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04fa_21), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04fb_21), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0600_21), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0610_21), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0618_21), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0620_21), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0628_21), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0630_21), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0638_21), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0639_21), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0640_21), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0650_21), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0658_21), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0660_21), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0668_21), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0670_21), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0678_21), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0679_21), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0680_21), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0690_21), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0698_21), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06a0_21), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06a8_21), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b0_21), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b8_21), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b9_21), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06c0_21), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06c8_21), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06d0_21), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06e8_21), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06f0_21), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06f8_21), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06f9_21), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06fa_21), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06fb_21), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0800_21), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0810_21), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0818_21), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0820_21), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0828_21), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0830_21), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0838_21), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0839_21), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_083a_21), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_083b_21), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0840_21), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0850_21), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0858_21), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0860_21), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0868_21), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0870_21), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0878_21), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0879_21), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0880_21), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0890_21), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0898_21), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08a0_21), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08a8_21), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b0_21), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b8_21), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b9_21), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08c0_21), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08d0_21), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08d8_21), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08e0_21), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08e8_21), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f0_21), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f8_21), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f9_21), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_0a00_21), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a10_21), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a18_21), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a20_21), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a28_21), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a30_21), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a38_21), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a39_21), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a3c_21), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ (cpuop_func*)CPUFUNC(op_0a40_21), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a50_21), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a58_21), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a60_21), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a68_21), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a70_21), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a78_21), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a79_21), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a7c_21), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ (cpuop_func*)CPUFUNC(op_0a80_21), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a90_21), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a98_21), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0aa0_21), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0aa8_21), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab0_21), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab8_21), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab9_21), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ad0_21), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ad8_21), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ae0_21), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ae8_21), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0af0_21), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0af8_21), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0af9_21), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0c00_21), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c10_21), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c18_21), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c20_21), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c28_21), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c30_21), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c38_21), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c39_21), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0c3a_21), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0c3b_21), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0c40_21), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c50_21), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c58_21), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c60_21), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c68_21), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c70_21), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c78_21), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c79_21), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0c7a_21), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0c7b_21), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0c80_21), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c90_21), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c98_21), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0ca0_21), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0ca8_21), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb0_21), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb8_21), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb9_21), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cba_21), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cbb_21), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cd0_21), 0x0cd0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cd8_21), 0x0cd8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ce0_21), 0x0ce0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ce8_21), 0x0ce8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cf0_21), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cf8_21), 0x0cf8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cf9_21), 0x0cf9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cfc_21), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e10_21), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e18_21), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e20_21), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e28_21), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e30_21), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e38_21), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e39_21), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e50_21), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e58_21), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e60_21), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e68_21), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e70_21), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e78_21), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e79_21), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e90_21), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e98_21), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ea0_21), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ea8_21), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0eb0_21), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0eb8_21), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0eb9_21), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ed0_21), 0x0ed0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ed8_21), 0x0ed8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ee0_21), 0x0ee0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ee8_21), 0x0ee8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ef0_21), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ef8_21), 0x0ef8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ef9_21), 0x0ef9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0efc_21), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_1000_21), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1010_21), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1018_21), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1020_21), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1028_21), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1030_21), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1038_21), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1039_21), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103a_21), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103b_21), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103c_21), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1080_21), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1090_21), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1098_21), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10a0_21), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10a8_21), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b0_21), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b8_21), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b9_21), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10ba_21), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10bb_21), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10bc_21), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10c0_21), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10d0_21), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10d8_21), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10e0_21), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10e8_21), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f0_21), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f8_21), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f9_21), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fa_21), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fb_21), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fc_21), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1100_21), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1110_21), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1118_21), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1120_21), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1128_21), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1130_21), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1138_21), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1139_21), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113a_21), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113b_21), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113c_21), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1140_21), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1150_21), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1158_21), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1160_21), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1168_21), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1170_21), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1178_21), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1179_21), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117a_21), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117b_21), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117c_21), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1180_21), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1190_21), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1198_21), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11a0_21), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11a8_21), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b0_21), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b8_21), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b9_21), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11ba_21), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11bb_21), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11bc_21), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11c0_21), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11d0_21), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11d8_21), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11e0_21), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11e8_21), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f0_21), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f8_21), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f9_21), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fa_21), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fb_21), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fc_21), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13c0_21), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13d0_21), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13d8_21), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13e0_21), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13e8_21), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f0_21), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f8_21), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f9_21), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fa_21), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fb_21), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fc_21), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2000_21), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2008_21), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2010_21), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2018_21), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2020_21), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2028_21), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2030_21), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2038_21), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2039_21), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203a_21), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203b_21), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203c_21), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2040_21), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2048_21), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2050_21), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2058_21), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2060_21), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2068_21), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2070_21), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2078_21), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2079_21), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207a_21), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207b_21), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207c_21), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2080_21), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2088_21), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2090_21), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2098_21), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20a0_21), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20a8_21), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b0_21), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b8_21), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b9_21), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20ba_21), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20bb_21), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20bc_21), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20c0_21), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20c8_21), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20d0_21), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20d8_21), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20e0_21), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20e8_21), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f0_21), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f8_21), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f9_21), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fa_21), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fb_21), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fc_21), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2100_21), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2108_21), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2110_21), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2118_21), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2120_21), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2128_21), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2130_21), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2138_21), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2139_21), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213a_21), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213b_21), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213c_21), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2140_21), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2148_21), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2150_21), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2158_21), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2160_21), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2168_21), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2170_21), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2178_21), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2179_21), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217a_21), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217b_21), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217c_21), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2180_21), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2188_21), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2190_21), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2198_21), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21a0_21), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21a8_21), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b0_21), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b8_21), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b9_21), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21ba_21), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21bb_21), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21bc_21), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21c0_21), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21c8_21), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21d0_21), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21d8_21), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21e0_21), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21e8_21), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f0_21), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f8_21), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f9_21), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fa_21), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fb_21), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fc_21), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23c0_21), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23c8_21), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23d0_21), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23d8_21), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23e0_21), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23e8_21), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f0_21), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f8_21), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f9_21), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fa_21), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fb_21), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fc_21), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3000_21), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3008_21), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3010_21), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3018_21), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3020_21), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3028_21), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3030_21), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3038_21), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3039_21), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303a_21), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303b_21), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303c_21), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3040_21), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3048_21), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3050_21), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3058_21), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3060_21), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3068_21), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3070_21), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3078_21), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3079_21), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307a_21), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307b_21), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307c_21), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3080_21), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3088_21), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3090_21), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3098_21), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30a0_21), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30a8_21), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b0_21), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b8_21), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b9_21), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30ba_21), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30bb_21), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30bc_21), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30c0_21), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30c8_21), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30d0_21), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30d8_21), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30e0_21), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30e8_21), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f0_21), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f8_21), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f9_21), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fa_21), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fb_21), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fc_21), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3100_21), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3108_21), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3110_21), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3118_21), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3120_21), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3128_21), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3130_21), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3138_21), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3139_21), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313a_21), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313b_21), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313c_21), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3140_21), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3148_21), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3150_21), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3158_21), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3160_21), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3168_21), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3170_21), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3178_21), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3179_21), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317a_21), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317b_21), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317c_21), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3180_21), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3188_21), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3190_21), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3198_21), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31a0_21), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31a8_21), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b0_21), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b8_21), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b9_21), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31ba_21), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31bb_21), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31bc_21), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31c0_21), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31c8_21), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31d0_21), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31d8_21), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31e0_21), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31e8_21), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f0_21), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f8_21), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f9_21), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fa_21), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fb_21), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fc_21), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33c0_21), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33c8_21), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33d0_21), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33d8_21), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33e0_21), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33e8_21), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f0_21), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f8_21), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f9_21), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fa_21), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fb_21), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fc_21), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_4000_21), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4010_21), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4018_21), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4020_21), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4028_21), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4030_21), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4038_21), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4039_21), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4040_21), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4050_21), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4058_21), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4060_21), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4068_21), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4070_21), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4078_21), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4079_21), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4080_21), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4090_21), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4098_21), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40a0_21), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40a8_21), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b0_21), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b8_21), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b9_21), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40c0_21), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40d0_21), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40d8_21), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40e0_21), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40e8_21), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f0_21), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f8_21), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f9_21), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4100_21), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4110_21), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4118_21), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4120_21), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4128_21), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4130_21), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4138_21), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4139_21), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_413a_21), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_413b_21), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_413c_21), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4180_21), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4190_21), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4198_21), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41a0_21), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41a8_21), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b0_21), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b8_21), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b9_21), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41ba_21), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41bb_21), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41bc_21), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41d0_21), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41e8_21), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f0_21), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f8_21), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f9_21), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41fa_21), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41fb_21), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_4200_21), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4210_21), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4218_21), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4220_21), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4228_21), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4230_21), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4238_21), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4239_21), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4240_21), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4250_21), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4258_21), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4260_21), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4268_21), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4270_21), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4278_21), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4279_21), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4280_21), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4290_21), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4298_21), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42a0_21), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42a8_21), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b0_21), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b8_21), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b9_21), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42c0_21), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42d0_21), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42d8_21), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42e0_21), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42e8_21), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42f0_21), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42f8_21), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42f9_21), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4400_21), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4410_21), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4418_21), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4420_21), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4428_21), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4430_21), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4438_21), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4439_21), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4440_21), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4450_21), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4458_21), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4460_21), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4468_21), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4470_21), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4478_21), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4479_21), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4480_21), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4490_21), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4498_21), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44a0_21), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44a8_21), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b0_21), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b8_21), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b9_21), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44c0_21), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44d0_21), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44d8_21), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44e0_21), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44e8_21), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f0_21), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f8_21), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f9_21), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fa_21), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fb_21), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fc_21), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_4600_21), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4610_21), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4618_21), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4620_21), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4628_21), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4630_21), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4638_21), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4639_21), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4640_21), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4650_21), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4658_21), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4660_21), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4668_21), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4670_21), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4678_21), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4679_21), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4680_21), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4690_21), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4698_21), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46a0_21), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46a8_21), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b0_21), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b8_21), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b9_21), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46c0_21), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46d0_21), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46d8_21), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46e0_21), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46e8_21), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f0_21), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f8_21), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f9_21), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fa_21), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fb_21), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fc_21), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_4800_21), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4808_21), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4810_21), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4818_21), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4820_21), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4828_21), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4830_21), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4838_21), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4839_21), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4840_21), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4848_21), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4850_21), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4868_21), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4870_21), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4878_21), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4879_21), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_487a_21), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_487b_21), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4880_21), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ (cpuop_func*)CPUFUNC(op_4890_21), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48a0_21), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48a8_21), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b0_21), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b8_21), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b9_21), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48c0_21), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ (cpuop_func*)CPUFUNC(op_48d0_21), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48e0_21), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48e8_21), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f0_21), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f8_21), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f9_21), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_49c0_21), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a00_21), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a10_21), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a18_21), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a20_21), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a28_21), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a30_21), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a38_21), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a39_21), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a3a_21), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a3b_21), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a3c_21), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a40_21), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a48_21), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a50_21), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a58_21), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a60_21), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a68_21), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a70_21), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a78_21), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a79_21), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a7a_21), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a7b_21), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a7c_21), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a80_21), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a88_21), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a90_21), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a98_21), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4aa0_21), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4aa8_21), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab0_21), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab8_21), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab9_21), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4aba_21), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4abb_21), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4abc_21), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4ac0_21), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ad0_21), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ad8_21), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ae0_21), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ae8_21), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af0_21), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af8_21), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af9_21), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c00_21), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c10_21), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c18_21), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c20_21), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c28_21), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c30_21), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c38_21), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c39_21), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c3a_21), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c3b_21), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c3c_21), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c40_21), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c50_21), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c58_21), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c60_21), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c68_21), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c70_21), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c78_21), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c79_21), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c7a_21), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c7b_21), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c7c_21), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4c90_21), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4c98_21), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4ca8_21), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb0_21), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb8_21), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb9_21), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cba_21), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cbb_21), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cd0_21), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cd8_21), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4ce8_21), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf0_21), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf8_21), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf9_21), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cfa_21), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cfb_21), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4e40_21), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ (cpuop_func*)CPUFUNC(op_4e50_21), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ (cpuop_func*)CPUFUNC(op_4e58_21), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ (cpuop_func*)CPUFUNC(op_4e60_21), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ (cpuop_func*)CPUFUNC(op_4e68_21), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ (cpuop_func*)CPUFUNC(op_4e70_21), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ (cpuop_func*)CPUFUNC(op_4e71_21), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ (cpuop_func*)CPUFUNC(op_4e72_21), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ (cpuop_func*)CPUFUNC(op_4e73_21), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4e74_21), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4e75_21), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ (cpuop_func*)CPUFUNC(op_4e76_21), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ (cpuop_func*)CPUFUNC(op_4e77_21), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4e7a_21), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4e7b_21), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4e90_21), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ea8_21), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb0_21), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb8_21), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb9_21), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eba_21), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ebb_21), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ed0_21), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ee8_21), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef0_21), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef8_21), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef9_21), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4efa_21), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4efb_21), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_5000_21), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5010_21), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5018_21), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5020_21), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5028_21), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5030_21), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5038_21), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5039_21), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5040_21), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5048_21), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_5050_21), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5058_21), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5060_21), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5068_21), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5070_21), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5078_21), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5079_21), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5080_21), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5088_21), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_5090_21), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5098_21), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50a0_21), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50a8_21), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b0_21), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b8_21), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b9_21), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50c0_21), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50c8_21), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_50d0_21), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50d8_21), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50e0_21), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50e8_21), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f0_21), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f8_21), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f9_21), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_50fa_21), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_50fb_21), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_50fc_21), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5100_21), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5110_21), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5118_21), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5120_21), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5128_21), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5130_21), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5138_21), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5139_21), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5140_21), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5148_21), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_5150_21), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5158_21), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5160_21), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5168_21), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5170_21), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5178_21), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5179_21), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5180_21), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5188_21), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_5190_21), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5198_21), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51a0_21), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51a8_21), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b0_21), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b8_21), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b9_21), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51c0_21), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51c8_21), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_51d0_21), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51d8_21), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51e0_21), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51e8_21), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f0_21), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f8_21), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f9_21), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_51fa_21), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_51fb_21), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_51fc_21), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_52c0_21), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52c8_21), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_52d0_21), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52d8_21), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52e0_21), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52e8_21), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f0_21), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f8_21), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f9_21), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_52fa_21), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_52fb_21), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_52fc_21), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_53c0_21), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53c8_21), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_53d0_21), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53d8_21), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53e0_21), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53e8_21), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f0_21), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f8_21), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f9_21), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_53fa_21), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_53fb_21), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_53fc_21), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_54c0_21), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54c8_21), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_54d0_21), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54d8_21), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54e0_21), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54e8_21), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f0_21), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f8_21), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f9_21), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_54fa_21), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_54fb_21), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_54fc_21), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_55c0_21), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55c8_21), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_55d0_21), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55d8_21), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55e0_21), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55e8_21), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f0_21), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f8_21), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f9_21), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_55fa_21), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_55fb_21), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_55fc_21), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_56c0_21), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56c8_21), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_56d0_21), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56d8_21), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56e0_21), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56e8_21), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f0_21), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f8_21), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f9_21), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_56fa_21), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_56fb_21), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_56fc_21), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_57c0_21), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57c8_21), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_57d0_21), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57d8_21), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57e0_21), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57e8_21), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f0_21), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f8_21), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f9_21), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_57fa_21), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_57fb_21), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_57fc_21), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_58c0_21), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58c8_21), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_58d0_21), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58d8_21), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58e0_21), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58e8_21), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f0_21), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f8_21), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f9_21), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_58fa_21), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_58fb_21), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_58fc_21), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_59c0_21), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59c8_21), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_59d0_21), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59d8_21), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59e0_21), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59e8_21), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f0_21), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f8_21), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f9_21), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_59fa_21), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_59fb_21), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_59fc_21), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5ac0_21), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ac8_21), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5ad0_21), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ad8_21), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ae0_21), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ae8_21), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af0_21), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af8_21), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af9_21), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5afa_21), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5afb_21), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5afc_21), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5bc0_21), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bc8_21), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5bd0_21), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bd8_21), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5be0_21), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5be8_21), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf0_21), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf8_21), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf9_21), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5bfa_21), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5bfb_21), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5bfc_21), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5cc0_21), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cc8_21), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5cd0_21), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cd8_21), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ce0_21), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ce8_21), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf0_21), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf8_21), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf9_21), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5cfa_21), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5cfb_21), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5cfc_21), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5dc0_21), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dc8_21), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5dd0_21), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dd8_21), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5de0_21), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5de8_21), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df0_21), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df8_21), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df9_21), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5dfa_21), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5dfb_21), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5dfc_21), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5ec0_21), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ec8_21), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5ed0_21), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ed8_21), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ee0_21), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ee8_21), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef0_21), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef8_21), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef9_21), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5efa_21), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5efb_21), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5efc_21), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5fc0_21), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fc8_21), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5fd0_21), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fd8_21), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fe0_21), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fe8_21), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff0_21), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff8_21), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff9_21), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5ffa_21), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5ffb_21), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5ffc_21), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_6000_21), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6001_21), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_60ff_21), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6100_21), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_6101_21), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_61ff_21), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_6200_21), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6201_21), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_62ff_21), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6300_21), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6301_21), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_63ff_21), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6400_21), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6401_21), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_64ff_21), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6500_21), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6501_21), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_65ff_21), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6600_21), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6601_21), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_66ff_21), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6700_21), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6701_21), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_67ff_21), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6800_21), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6801_21), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_68ff_21), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6900_21), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6901_21), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_69ff_21), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6a00_21), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6a01_21), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6aff_21), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6b00_21), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6b01_21), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6bff_21), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6c00_21), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6c01_21), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6cff_21), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6d00_21), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6d01_21), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6dff_21), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6e00_21), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6e01_21), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6eff_21), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6f00_21), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6f01_21), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6fff_21), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_7000_21), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_8000_21), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8010_21), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8018_21), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8020_21), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8028_21), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8030_21), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8038_21), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8039_21), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803a_21), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803b_21), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803c_21), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8040_21), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8050_21), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8058_21), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8060_21), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8068_21), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8070_21), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8078_21), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8079_21), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807a_21), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807b_21), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807c_21), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8080_21), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8090_21), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8098_21), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80a0_21), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80a8_21), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b0_21), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b8_21), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b9_21), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80ba_21), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80bb_21), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80bc_21), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80c0_21), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80d0_21), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80d8_21), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80e0_21), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80e8_21), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f0_21), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f8_21), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f9_21), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fa_21), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fb_21), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fc_21), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_8100_21), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ (cpuop_func*)CPUFUNC(op_8108_21), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ (cpuop_func*)CPUFUNC(op_8110_21), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8118_21), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8120_21), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8128_21), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8130_21), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8138_21), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8139_21), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_8140_21), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_8148_21), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+{ (cpuop_func*)CPUFUNC(op_8150_21), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8158_21), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8160_21), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8168_21), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8170_21), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8178_21), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8179_21), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_8180_21), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_8188_21), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+{ (cpuop_func*)CPUFUNC(op_8190_21), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8198_21), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81a0_21), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81a8_21), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b0_21), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b8_21), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b9_21), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81c0_21), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81d0_21), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81d8_21), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81e0_21), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81e8_21), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f0_21), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f8_21), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f9_21), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fa_21), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fb_21), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fc_21), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_9000_21), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9010_21), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9018_21), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9020_21), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9028_21), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9030_21), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9038_21), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9039_21), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903a_21), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903b_21), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903c_21), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9040_21), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9048_21), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9050_21), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9058_21), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9060_21), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9068_21), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9070_21), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9078_21), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9079_21), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907a_21), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907b_21), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907c_21), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9080_21), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9088_21), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9090_21), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9098_21), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90a0_21), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90a8_21), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b0_21), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b8_21), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b9_21), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90ba_21), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90bb_21), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90bc_21), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90c0_21), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90c8_21), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90d0_21), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90d8_21), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90e0_21), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90e8_21), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f0_21), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f8_21), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f9_21), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fa_21), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fb_21), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fc_21), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_9100_21), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9108_21), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9110_21), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9118_21), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9120_21), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9128_21), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9130_21), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9138_21), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9139_21), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9140_21), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9148_21), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9150_21), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9158_21), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9160_21), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9168_21), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9170_21), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9178_21), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9179_21), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9180_21), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9188_21), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9190_21), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9198_21), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91a0_21), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91a8_21), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b0_21), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b8_21), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b9_21), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91c0_21), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91c8_21), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91d0_21), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91d8_21), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91e0_21), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91e8_21), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f0_21), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f8_21), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f9_21), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fa_21), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fb_21), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fc_21), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_b000_21), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b010_21), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b018_21), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b020_21), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b028_21), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b030_21), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b038_21), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b039_21), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03a_21), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03b_21), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03c_21), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b040_21), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b048_21), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b050_21), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b058_21), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b060_21), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b068_21), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b070_21), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b078_21), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b079_21), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07a_21), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07b_21), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07c_21), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b080_21), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b088_21), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b090_21), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b098_21), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0a0_21), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0a8_21), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b0_21), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b8_21), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b9_21), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0ba_21), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0bb_21), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0bc_21), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0c0_21), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0c8_21), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0d0_21), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0d8_21), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0e0_21), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0e8_21), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f0_21), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f8_21), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f9_21), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fa_21), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fb_21), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fc_21), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b100_21), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b108_21), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b110_21), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b118_21), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b120_21), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b128_21), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b130_21), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b138_21), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b139_21), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b140_21), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b148_21), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b150_21), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b158_21), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b160_21), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b168_21), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b170_21), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b178_21), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b179_21), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b180_21), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b188_21), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b190_21), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b198_21), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1a0_21), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1a8_21), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b0_21), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b8_21), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b9_21), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1c0_21), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1c8_21), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1d0_21), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1d8_21), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1e0_21), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1e8_21), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f0_21), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f8_21), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f9_21), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fa_21), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fb_21), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fc_21), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_c000_21), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c010_21), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c018_21), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c020_21), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c028_21), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c030_21), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c038_21), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c039_21), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03a_21), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03b_21), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03c_21), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c040_21), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c050_21), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c058_21), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c060_21), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c068_21), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c070_21), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c078_21), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c079_21), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07a_21), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07b_21), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07c_21), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c080_21), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c090_21), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c098_21), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0a0_21), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0a8_21), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b0_21), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b8_21), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b9_21), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0ba_21), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0bb_21), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0bc_21), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0c0_21), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0d0_21), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0d8_21), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0e0_21), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0e8_21), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f0_21), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f8_21), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f9_21), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fa_21), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fb_21), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fc_21), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c100_21), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ (cpuop_func*)CPUFUNC(op_c108_21), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ (cpuop_func*)CPUFUNC(op_c110_21), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c118_21), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c120_21), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c128_21), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c130_21), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c138_21), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c139_21), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c140_21), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c148_21), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c150_21), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c158_21), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c160_21), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c168_21), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c170_21), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c178_21), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c179_21), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c188_21), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c190_21), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c198_21), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1a0_21), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1a8_21), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b0_21), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b8_21), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b9_21), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1c0_21), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1d0_21), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1d8_21), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1e0_21), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1e8_21), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f0_21), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f8_21), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f9_21), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fa_21), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fb_21), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fc_21), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_d000_21), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d010_21), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d018_21), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d020_21), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d028_21), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d030_21), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d038_21), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d039_21), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03a_21), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03b_21), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03c_21), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d040_21), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d048_21), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d050_21), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d058_21), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d060_21), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d068_21), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d070_21), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d078_21), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d079_21), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07a_21), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07b_21), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07c_21), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d080_21), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d088_21), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d090_21), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d098_21), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0a0_21), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0a8_21), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b0_21), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b8_21), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b9_21), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0ba_21), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0bb_21), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0bc_21), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0c0_21), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0c8_21), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0d0_21), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0d8_21), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0e0_21), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0e8_21), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f0_21), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f8_21), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f9_21), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fa_21), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fb_21), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fc_21), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d100_21), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d108_21), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d110_21), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d118_21), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d120_21), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d128_21), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d130_21), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d138_21), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d139_21), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d140_21), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d148_21), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d150_21), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d158_21), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d160_21), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d168_21), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d170_21), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d178_21), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d179_21), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d180_21), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d188_21), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d190_21), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d198_21), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1a0_21), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1a8_21), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b0_21), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b8_21), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b9_21), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1c0_21), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1c8_21), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1d0_21), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1d8_21), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1e0_21), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1e8_21), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f0_21), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f8_21), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f9_21), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fa_21), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fb_21), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fc_21), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_e000_21), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e008_21), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e010_21), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e018_21), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e020_21), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e028_21), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e030_21), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e038_21), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e040_21), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e048_21), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e050_21), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e058_21), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e060_21), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e068_21), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e070_21), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e078_21), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e080_21), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e088_21), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e090_21), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e098_21), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e0a0_21), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e0a8_21), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e0b0_21), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e0b8_21), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e0d0_21), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0d8_21), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0e0_21), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0e8_21), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f0_21), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f8_21), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f9_21), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e100_21), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e108_21), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e110_21), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e118_21), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e120_21), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e128_21), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e130_21), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e138_21), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e140_21), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e148_21), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e150_21), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e158_21), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e160_21), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e168_21), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e170_21), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e178_21), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e180_21), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e188_21), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e190_21), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e198_21), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e1a0_21), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e1a8_21), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e1b0_21), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e1b8_21), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e1d0_21), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1d8_21), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1e0_21), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1e8_21), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f0_21), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f8_21), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f9_21), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e2d0_21), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2d8_21), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2e0_21), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2e8_21), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f0_21), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f8_21), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f9_21), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e3d0_21), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3d8_21), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3e0_21), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3e8_21), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f0_21), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f8_21), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f9_21), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e4d0_21), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4d8_21), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4e0_21), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4e8_21), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f0_21), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f8_21), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f9_21), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e5d0_21), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5d8_21), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5e0_21), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5e8_21), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f0_21), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f8_21), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f9_21), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e6d0_21), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6d8_21), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6e0_21), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6e8_21), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f0_21), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f8_21), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f9_21), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e7d0_21), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7d8_21), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7e0_21), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7e8_21), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f0_21), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f8_21), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f9_21), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8c0_21), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8d0_21), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8e8_21), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8f0_21), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8f8_21), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8f9_21), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8fa_21), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8fb_21), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9c0_21), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9d0_21), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9e8_21), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9f0_21), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9f8_21), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9f9_21), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9fa_21), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9fb_21), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eac0_21), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ead0_21), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eae8_21), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eaf0_21), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eaf8_21), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eaf9_21), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebc0_21), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebd0_21), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebe8_21), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebf0_21), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebf8_21), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebf9_21), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebfa_21), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebfb_21), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecc0_21), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecd0_21), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ece8_21), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecf0_21), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecf8_21), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecf9_21), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edc0_21), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edd0_21), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ede8_21), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edf0_21), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edf8_21), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edf9_21), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edfa_21), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edfb_21), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eec0_21), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eed0_21), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eee8_21), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eef0_21), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eef8_21), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eef9_21), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_efc0_21), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_efd0_21), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_efe8_21), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eff0_21), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eff8_21), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eff9_21), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f200_21), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f208_21), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f210_21), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f218_21), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f220_21), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f228_21), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f230_21), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f238_21), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f239_21), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f23a_21), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f23b_21), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f23c_21), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f240_21), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f248_21), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f250_21), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f258_21), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f260_21), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f268_21), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f270_21), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f278_21), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f279_21), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f27a_21), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f27b_21), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f27c_21), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f280_21), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f2c0_21), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f310_21), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f320_21), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f328_21), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f330_21), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f338_21), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f339_21), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f350_21), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f358_21), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f368_21), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f370_21), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f378_21), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f379_21), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f37a_21), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f37b_21), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#endif /* CPUEMU_21 */
+#ifdef CPUEMU_22
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_22)[] = {
+{ CPUFUNC(op_0000_22), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_22), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_22), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_22), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_22), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_22), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_22), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_22), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_22), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_22), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_22), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_22), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_22), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_22), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_22), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_22), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_22), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_22), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_22), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_22), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_22), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_22), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_22), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_22), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_22), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_22), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00d0_22), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00e8_22), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f0_22), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f8_22), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f9_22), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00fa_22), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00fb_22), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0100_22), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_22), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_22), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_22), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_22), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_22), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_22), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_22), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_22), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_22), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_22), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_22), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_22), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_22), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_22), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_22), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_22), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_22), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_22), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_22), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_22), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_22), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_22), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_22), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_22), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_22), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_22), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_22), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_22), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_22), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_22), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_22), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_22), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_22), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_22), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_22), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_22), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_22), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_22), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_22), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_22), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_22), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_22), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_22), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_22), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_22), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_22), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_22), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_22), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_22), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_22), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_22), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_22), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_22), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_22), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_22), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_22), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_22), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_22), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_22), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_22), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_22), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_22), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_22), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_22), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02d0_22), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02e8_22), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f0_22), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f8_22), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f9_22), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02fa_22), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02fb_22), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0400_22), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_22), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_22), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_22), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_22), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_22), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_22), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_22), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_22), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_22), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_22), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_22), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_22), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_22), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_22), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_22), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_22), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_22), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_22), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_22), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_22), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_22), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_22), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_22), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04d0_22), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04e8_22), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f0_22), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f8_22), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f9_22), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04fa_22), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04fb_22), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0600_22), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_22), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_22), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_22), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_22), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_22), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_22), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_22), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_22), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_22), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_22), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_22), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_22), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_22), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_22), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_22), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_22), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_22), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_22), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_22), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_22), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_22), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_22), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_22), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06c0_22), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06c8_22), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06d0_22), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06e8_22), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f0_22), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f8_22), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f9_22), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06fa_22), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06fb_22), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+{ CPUFUNC(op_0800_22), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_22), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_22), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_22), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_22), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_22), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_22), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_22), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_22), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_22), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_22), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_22), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_22), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_22), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_22), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_22), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_22), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_22), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_22), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_22), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_22), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_22), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_22), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_22), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_22), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_22), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_22), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_22), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_22), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_22), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_22), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_22), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_22), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_22), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_22), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_22), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_22), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_22), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_22), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_22), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_22), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_22), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_22), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_22), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_22), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_22), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_22), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_22), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_22), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_22), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_22), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_22), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_22), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_22), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_22), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_22), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_22), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_22), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_22), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_22), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ad0_22), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ad8_22), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ae0_22), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ae8_22), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af0_22), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af8_22), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af9_22), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+{ CPUFUNC(op_0c00_22), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_22), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_22), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_22), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_22), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_22), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_22), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_22), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c3a_22), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c3b_22), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ CPUFUNC(op_0c40_22), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_22), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_22), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_22), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_22), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_22), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_22), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_22), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c7a_22), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c7b_22), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ CPUFUNC(op_0c80_22), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_22), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_22), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_22), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_22), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_22), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_22), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_22), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cba_22), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cbb_22), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cd0_22), 0x0cd0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cd8_22), 0x0cd8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ce0_22), 0x0ce0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ce8_22), 0x0ce8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf0_22), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf8_22), 0x0cf8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf9_22), 0x0cf9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cfc_22), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e10_22), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e18_22), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e20_22), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e28_22), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e30_22), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e38_22), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e39_22), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e50_22), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e58_22), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e60_22), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e68_22), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e70_22), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e78_22), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e79_22), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e90_22), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e98_22), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ea0_22), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ea8_22), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb0_22), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb8_22), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb9_22), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ed0_22), 0x0ed0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ed8_22), 0x0ed8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ee0_22), 0x0ee0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ee8_22), 0x0ee8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef0_22), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef8_22), 0x0ef8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef9_22), 0x0ef9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0efc_22), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+{ CPUFUNC(op_1000_22), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_22), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_22), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_22), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_22), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_22), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_22), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_22), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_22), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_22), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_22), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_22), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_22), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_22), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_22), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_22), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_22), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_22), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_22), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_22), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_22), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_22), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_22), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_22), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_22), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_22), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_22), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_22), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_22), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_22), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_22), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_22), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_22), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_22), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_22), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_22), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_22), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_22), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_22), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_22), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_22), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_22), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_22), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_22), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_22), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_22), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_22), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_22), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_22), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_22), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_22), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_22), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_22), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_22), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_22), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_22), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_22), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_22), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_22), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_22), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_22), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_22), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_22), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_22), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_22), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_22), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_22), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_22), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_22), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_22), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_22), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_22), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_22), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_22), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_22), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_22), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_22), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_22), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_22), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_22), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_22), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_22), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_22), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_22), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_22), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_22), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_22), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_22), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_22), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_22), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_22), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_22), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_22), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_22), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_22), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_22), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_22), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_22), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_22), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_22), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_22), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_22), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_22), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_22), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_22), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_22), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_22), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_22), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_22), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_22), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_22), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_22), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_22), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_22), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_22), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_22), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_22), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_22), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_22), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_22), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_22), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_22), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_22), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_22), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_22), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_22), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_22), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_22), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_22), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_22), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_22), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_22), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_22), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_22), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_22), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_22), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_22), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_22), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_22), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_22), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_22), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_22), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_22), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_22), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_22), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_22), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_22), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_22), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_22), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_22), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_22), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_22), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_22), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_22), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_22), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_22), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_22), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_22), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_22), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_22), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_22), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_22), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_22), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_22), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_22), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_22), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_22), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_22), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_22), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_22), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_22), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_22), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_22), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_22), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_22), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_22), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_22), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_22), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_22), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_22), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_22), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_22), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_22), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_22), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_22), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_22), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_22), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_22), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_22), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_22), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_22), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_22), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_22), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_22), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_22), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_22), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_22), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_22), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_22), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_22), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_22), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_22), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_22), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_22), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_22), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_22), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_22), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_22), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_22), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_22), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_22), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_22), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_22), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_22), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_22), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_22), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_22), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_22), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_22), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_22), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_22), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_22), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_22), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_22), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_22), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_22), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_22), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_22), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_22), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_22), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_22), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_22), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_22), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_22), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_22), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_22), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_22), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_22), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_22), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_22), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_22), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_22), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_22), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_22), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_22), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_22), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_22), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_22), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_22), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_22), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_22), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_22), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_22), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_22), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_22), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_22), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_22), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_22), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_22), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_22), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_22), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_22), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_22), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_22), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_22), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_22), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_22), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_22), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_22), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_22), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_22), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_22), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_22), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_22), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_22), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_22), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_22), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_22), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_22), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_22), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_22), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_22), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_22), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_22), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_22), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_22), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_22), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_22), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_22), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_22), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_22), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_22), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_22), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_22), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_22), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_22), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_22), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_22), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_22), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_22), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_22), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_22), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_22), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_22), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_22), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_22), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_22), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_22), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_22), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_22), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_22), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_22), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_22), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_22), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_22), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_22), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_22), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_22), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_22), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_22), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_22), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_22), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_22), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_22), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_22), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_22), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_22), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_22), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_22), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_22), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_22), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_22), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_22), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_22), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_22), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_22), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4100_22), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4110_22), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4118_22), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4120_22), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4128_22), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4130_22), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4138_22), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4139_22), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413a_22), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413b_22), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413c_22), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+{ CPUFUNC(op_4180_22), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_22), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_22), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_22), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_22), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_22), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_22), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_22), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_22), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_22), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_22), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_22), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_22), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_22), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_22), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_22), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_22), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_22), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_22), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_22), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_22), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_22), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_22), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_22), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_22), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_22), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_22), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_22), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_22), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_22), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_22), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_22), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_22), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_22), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_22), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_22), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_22), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_22), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_22), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_22), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_22), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_22), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42c0_22), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d0_22), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d8_22), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e0_22), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e8_22), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f0_22), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f8_22), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f9_22), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+{ CPUFUNC(op_4400_22), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_22), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_22), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_22), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_22), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_22), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_22), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_22), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_22), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_22), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_22), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_22), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_22), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_22), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_22), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_22), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_22), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_22), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_22), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_22), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_22), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_22), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_22), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_22), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_22), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_22), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_22), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_22), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_22), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_22), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_22), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_22), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_22), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_22), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_22), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_22), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_22), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_22), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_22), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_22), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_22), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_22), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_22), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_22), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_22), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_22), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_22), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_22), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_22), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_22), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_22), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_22), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_22), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_22), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_22), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_22), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_22), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_22), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_22), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_22), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_22), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_22), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_22), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_22), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_22), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_22), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_22), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_22), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_22), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_22), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_22), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4808_22), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#endif
+{ CPUFUNC(op_4810_22), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_22), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_22), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_22), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_22), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_22), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_22), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_22), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4848_22), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+#endif
+{ CPUFUNC(op_4850_22), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_22), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_22), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_22), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_22), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_22), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_22), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_22), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_22), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_22), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_22), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_22), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_22), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_22), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_22), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_22), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_22), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_22), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_22), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_22), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_22), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_49c0_22), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+#endif
+{ CPUFUNC(op_4a00_22), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_22), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_22), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_22), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_22), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_22), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_22), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_22), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3a_22), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3b_22), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3c_22), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a40_22), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a48_22), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a50_22), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_22), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_22), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_22), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_22), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_22), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_22), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7a_22), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7b_22), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7c_22), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a80_22), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a88_22), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a90_22), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_22), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_22), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_22), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_22), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_22), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_22), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4aba_22), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4abb_22), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4abc_22), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4ac0_22), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_22), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_22), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_22), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_22), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_22), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_22), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_22), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c00_22), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c10_22), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c18_22), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c20_22), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c28_22), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c30_22), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c38_22), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c39_22), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3a_22), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3b_22), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3c_22), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c40_22), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c50_22), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c58_22), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c60_22), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c68_22), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c70_22), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c78_22), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c79_22), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7a_22), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7b_22), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7c_22), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+{ CPUFUNC(op_4c90_22), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_22), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_22), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_22), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_22), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_22), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_22), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_22), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_22), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_22), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_22), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_22), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_22), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_22), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_22), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_22), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_22), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_22), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_22), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_22), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_22), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_22), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_22), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_22), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_22), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e74_22), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+#endif
+{ CPUFUNC(op_4e75_22), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_22), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_22), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7a_22), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7b_22), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+#endif
+{ CPUFUNC(op_4e90_22), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_22), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_22), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_22), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_22), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_22), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_22), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_22), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_22), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_22), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_22), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_22), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_22), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_22), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_22), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_22), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_22), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_22), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_22), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_22), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_22), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_22), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_22), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_22), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_22), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_22), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_22), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_22), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_22), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_22), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_22), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_22), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_22), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_22), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_22), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_22), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_22), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_22), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_22), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_22), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_22), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_22), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_22), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_22), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_22), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_22), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_22), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_22), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_22), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fa_22), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fb_22), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fc_22), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5100_22), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_22), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_22), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_22), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_22), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_22), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_22), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_22), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_22), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_22), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_22), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_22), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_22), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_22), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_22), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_22), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_22), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_22), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_22), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_22), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_22), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_22), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_22), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_22), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_22), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_22), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_22), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_22), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_22), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_22), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_22), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_22), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_22), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_22), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_22), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fa_22), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fb_22), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fc_22), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_52c0_22), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_22), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_22), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_22), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_22), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_22), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_22), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_22), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_22), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fa_22), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fb_22), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fc_22), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_53c0_22), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_22), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_22), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_22), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_22), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_22), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_22), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_22), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_22), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fa_22), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fb_22), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fc_22), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_54c0_22), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_22), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_22), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_22), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_22), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_22), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_22), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_22), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_22), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fa_22), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fb_22), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fc_22), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_55c0_22), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_22), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_22), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_22), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_22), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_22), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_22), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_22), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_22), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fa_22), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fb_22), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fc_22), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_56c0_22), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_22), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_22), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_22), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_22), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_22), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_22), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_22), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_22), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fa_22), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fb_22), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fc_22), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_57c0_22), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_22), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_22), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_22), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_22), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_22), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_22), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_22), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_22), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fa_22), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fb_22), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fc_22), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_58c0_22), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_22), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_22), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_22), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_22), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_22), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_22), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_22), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_22), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fa_22), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fb_22), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fc_22), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_59c0_22), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_22), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_22), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_22), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_22), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_22), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_22), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_22), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_22), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fa_22), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fb_22), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fc_22), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5ac0_22), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_22), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_22), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_22), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_22), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_22), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_22), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_22), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_22), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afa_22), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afb_22), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afc_22), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5bc0_22), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_22), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_22), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_22), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_22), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_22), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_22), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_22), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_22), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfa_22), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfb_22), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfc_22), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5cc0_22), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_22), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_22), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_22), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_22), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_22), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_22), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_22), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_22), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfa_22), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfb_22), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfc_22), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5dc0_22), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_22), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_22), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_22), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_22), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_22), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_22), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_22), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_22), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfa_22), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfb_22), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfc_22), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5ec0_22), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_22), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_22), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_22), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_22), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_22), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_22), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_22), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_22), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efa_22), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efb_22), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efc_22), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5fc0_22), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_22), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_22), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_22), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_22), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_22), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_22), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_22), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_22), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffa_22), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffb_22), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffc_22), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_6000_22), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_22), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_22), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6100_22), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_22), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_22), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_22), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_22), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_22), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6300_22), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_22), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_22), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6400_22), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_22), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_22), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6500_22), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_22), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_22), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6600_22), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_22), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_22), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6700_22), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_22), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_22), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6800_22), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_22), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_22), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6900_22), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_22), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_22), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a00_22), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_22), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_22), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b00_22), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_22), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_22), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c00_22), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_22), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_22), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d00_22), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_22), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_22), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e00_22), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_22), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_22), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f00_22), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_22), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_22), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_7000_22), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_22), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_22), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_22), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_22), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_22), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_22), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_22), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_22), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_22), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_22), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_22), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_22), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_22), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_22), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_22), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_22), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_22), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_22), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_22), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_22), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_22), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_22), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_22), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_22), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_22), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_22), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_22), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_22), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_22), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_22), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_22), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_22), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_22), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_22), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_22), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_22), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_22), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_22), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_22), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_22), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_22), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_22), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_22), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_22), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_22), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_22), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_22), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_22), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_22), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_22), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_22), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_22), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_22), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8140_22), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8148_22), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+{ CPUFUNC(op_8150_22), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_22), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_22), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_22), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_22), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_22), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_22), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8180_22), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8188_22), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+{ CPUFUNC(op_8190_22), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_22), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_22), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_22), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_22), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_22), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_22), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_22), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_22), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_22), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_22), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_22), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_22), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_22), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_22), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_22), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_22), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_22), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_22), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_22), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_22), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_22), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_22), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_22), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_22), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_22), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_22), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_22), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_22), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_22), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_22), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_22), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_22), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_22), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_22), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_22), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_22), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_22), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_22), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_22), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_22), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_22), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_22), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_22), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_22), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_22), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_22), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_22), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_22), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_22), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_22), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_22), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_22), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_22), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_22), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_22), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_22), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_22), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_22), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_22), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_22), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_22), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_22), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_22), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_22), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_22), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_22), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_22), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_22), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_22), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_22), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_22), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_22), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_22), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_22), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_22), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_22), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_22), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_22), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_22), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_22), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_22), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_22), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_22), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_22), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_22), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_22), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_22), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_22), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_22), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_22), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_22), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_22), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_22), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_22), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_22), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_22), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_22), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_22), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_22), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_22), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_22), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_22), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_22), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_22), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_22), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_22), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_22), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_22), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_22), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_22), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_22), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_22), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_22), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_22), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_22), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_22), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_22), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_22), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_22), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_22), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_22), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_22), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_22), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_22), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_22), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_22), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_22), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_22), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_22), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_22), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_22), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_22), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_22), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_22), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_22), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_22), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_22), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_22), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_22), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_22), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_22), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_22), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_22), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_22), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_22), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_22), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_22), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_22), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_22), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_22), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_22), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_22), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_22), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_22), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_22), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_22), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_22), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_22), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_22), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_22), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_22), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_22), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_22), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_22), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_22), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_22), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_22), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_22), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_22), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_22), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_22), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_22), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_22), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_22), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_22), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_22), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_22), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_22), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_22), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_22), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_22), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_22), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_22), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_22), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_22), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_22), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_22), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_22), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_22), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_22), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_22), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_22), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_22), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_22), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_22), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_22), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_22), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_22), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_22), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_22), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_22), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_22), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_22), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_22), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_22), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_22), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_22), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_22), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_22), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_22), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_22), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_22), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_22), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_22), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_22), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_22), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_22), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_22), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_22), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_22), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_22), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_22), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_22), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_22), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_22), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_22), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_22), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_22), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_22), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_22), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_22), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_22), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_22), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_22), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_22), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_22), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_22), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_22), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_22), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_22), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_22), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_22), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_22), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_22), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_22), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_22), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_22), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_22), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_22), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_22), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_22), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_22), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_22), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_22), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_22), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_22), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_22), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_22), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_22), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_22), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_22), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_22), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_22), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_22), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_22), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_22), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_22), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_22), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_22), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_22), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_22), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_22), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_22), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_22), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_22), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_22), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_22), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_22), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_22), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_22), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_22), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_22), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_22), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_22), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_22), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_22), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_22), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_22), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_22), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_22), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_22), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_22), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_22), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_22), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_22), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_22), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_22), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_22), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_22), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_22), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_22), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_22), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_22), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_22), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_22), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_22), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_22), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_22), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_22), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_22), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_22), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_22), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_22), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_22), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_22), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_22), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_22), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_22), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_22), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_22), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_22), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_22), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_22), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_22), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_22), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_22), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_22), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_22), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_22), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_22), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_22), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_22), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_22), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_22), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_22), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_22), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_22), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_22), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_22), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_22), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_22), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_22), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_22), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_22), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_22), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_22), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_22), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_22), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_22), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_22), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_22), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_22), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_22), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_22), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_22), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_22), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_22), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_22), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_22), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_22), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_22), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_22), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_22), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_22), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_22), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_22), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_22), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_22), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_22), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_22), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_22), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_22), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_22), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_22), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_22), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_22), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_22), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_22), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_22), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_22), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_22), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_22), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_22), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_22), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_22), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_22), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_22), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_22), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_22), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_22), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_22), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_22), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_22), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_22), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_22), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_22), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_22), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_22), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_22), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_22), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_22), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_22), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_22), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_22), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_22), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_22), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_22), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_22), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_22), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_22), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_22), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_22), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_22), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_22), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_22), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_22), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_22), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_22), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_22), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_22), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_22), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_22), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_22), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_22), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_22), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_22), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_22), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_22), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_22), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_22), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_22), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_22), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_22), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_22), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_22), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_22), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_22), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_22), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_22), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_22), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_22), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_22), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_22), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_22), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_22), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_22), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_22), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_22), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_22), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_22), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_22), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_22), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_22), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_22), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_22), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_22), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_22), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_22), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_22), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_22), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8c0_22), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8d0_22), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8e8_22), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f0_22), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f8_22), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f9_22), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8fa_22), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8fb_22), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9c0_22), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9d0_22), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9e8_22), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f0_22), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f8_22), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f9_22), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9fa_22), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9fb_22), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eac0_22), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ead0_22), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eae8_22), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf0_22), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf8_22), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf9_22), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebc0_22), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebd0_22), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebe8_22), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf0_22), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf8_22), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf9_22), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebfa_22), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebfb_22), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecc0_22), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecd0_22), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ece8_22), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf0_22), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf8_22), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf9_22), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edc0_22), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edd0_22), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ede8_22), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf0_22), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf8_22), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf9_22), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edfa_22), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edfb_22), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eec0_22), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eed0_22), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eee8_22), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef0_22), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef8_22), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef9_22), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efc0_22), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efd0_22), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efe8_22), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff0_22), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff8_22), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff9_22), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f000_22), 0xf000, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f008_22), 0xf008, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f010_22), 0xf010, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f018_22), 0xf018, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f020_22), 0xf020, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f028_22), 0xf028, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f030_22), 0xf030, -1, { -3, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f038_22), 0xf038, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f039_22), 0xf039, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f200_22), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f208_22), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f210_22), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f218_22), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f220_22), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f228_22), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f230_22), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f238_22), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f239_22), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23a_22), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23b_22), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23c_22), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f240_22), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f248_22), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f250_22), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f258_22), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f260_22), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f268_22), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f270_22), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f278_22), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f279_22), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27a_22), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27b_22), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27c_22), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f280_22), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f2c0_22), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f310_22), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f320_22), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f328_22), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f330_22), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f338_22), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f339_22), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f350_22), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f358_22), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f368_22), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f370_22), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f378_22), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f379_22), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f37a_22), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f37b_22), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#endif /* CPUEMU_22 */
+#ifdef CPUEMU_23
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_23)[] = {
+{ (cpuop_func*)CPUFUNC(op_0000_23), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0010_23), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0018_23), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0020_23), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0028_23), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0030_23), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0038_23), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0039_23), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_003c_23), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ (cpuop_func*)CPUFUNC(op_0040_23), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0050_23), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0058_23), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0060_23), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0068_23), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0070_23), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0078_23), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0079_23), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_007c_23), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ (cpuop_func*)CPUFUNC(op_0080_23), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0090_23), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0098_23), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00a0_23), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00a8_23), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b0_23), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b8_23), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b9_23), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00d0_23), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00e8_23), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00f0_23), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00f8_23), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00f9_23), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00fa_23), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00fb_23), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0100_23), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0108_23), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ (cpuop_func*)CPUFUNC(op_0110_23), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0118_23), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0120_23), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0128_23), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0130_23), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0138_23), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0139_23), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013a_23), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013b_23), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013c_23), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0140_23), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0148_23), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ (cpuop_func*)CPUFUNC(op_0150_23), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0158_23), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0160_23), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0168_23), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0170_23), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0178_23), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0179_23), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0180_23), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0188_23), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ (cpuop_func*)CPUFUNC(op_0190_23), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0198_23), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01a0_23), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01a8_23), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b0_23), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b8_23), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b9_23), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01c0_23), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01c8_23), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ (cpuop_func*)CPUFUNC(op_01d0_23), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01d8_23), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01e0_23), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01e8_23), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f0_23), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f8_23), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f9_23), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_0200_23), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0210_23), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0218_23), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0220_23), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0228_23), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0230_23), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0238_23), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0239_23), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_023c_23), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ (cpuop_func*)CPUFUNC(op_0240_23), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0250_23), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0258_23), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0260_23), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0268_23), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0270_23), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0278_23), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0279_23), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_027c_23), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ (cpuop_func*)CPUFUNC(op_0280_23), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0290_23), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0298_23), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02a0_23), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02a8_23), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b0_23), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b8_23), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b9_23), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02d0_23), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02e8_23), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02f0_23), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02f8_23), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02f9_23), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02fa_23), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02fb_23), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0400_23), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0410_23), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0418_23), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0420_23), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0428_23), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0430_23), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0438_23), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0439_23), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0440_23), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0450_23), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0458_23), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0460_23), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0468_23), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0470_23), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0478_23), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0479_23), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0480_23), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0490_23), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0498_23), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04a0_23), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04a8_23), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b0_23), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b8_23), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b9_23), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04d0_23), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04e8_23), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04f0_23), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04f8_23), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04f9_23), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04fa_23), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04fb_23), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0600_23), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0610_23), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0618_23), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0620_23), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0628_23), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0630_23), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0638_23), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0639_23), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0640_23), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0650_23), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0658_23), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0660_23), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0668_23), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0670_23), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0678_23), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0679_23), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0680_23), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0690_23), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0698_23), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06a0_23), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06a8_23), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b0_23), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b8_23), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b9_23), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06c0_23), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06c8_23), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06d0_23), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06e8_23), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06f0_23), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06f8_23), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06f9_23), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06fa_23), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06fb_23), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0800_23), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0810_23), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0818_23), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0820_23), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0828_23), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0830_23), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0838_23), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0839_23), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_083a_23), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_083b_23), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0840_23), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0850_23), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0858_23), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0860_23), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0868_23), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0870_23), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0878_23), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0879_23), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0880_23), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0890_23), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0898_23), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08a0_23), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08a8_23), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b0_23), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b8_23), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b9_23), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08c0_23), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08d0_23), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08d8_23), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08e0_23), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08e8_23), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f0_23), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f8_23), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f9_23), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_0a00_23), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a10_23), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a18_23), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a20_23), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a28_23), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a30_23), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a38_23), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a39_23), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a3c_23), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ (cpuop_func*)CPUFUNC(op_0a40_23), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a50_23), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a58_23), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a60_23), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a68_23), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a70_23), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a78_23), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a79_23), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a7c_23), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ (cpuop_func*)CPUFUNC(op_0a80_23), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a90_23), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a98_23), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0aa0_23), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0aa8_23), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab0_23), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab8_23), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab9_23), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ad0_23), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ad8_23), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ae0_23), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ae8_23), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0af0_23), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0af8_23), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0af9_23), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0c00_23), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c10_23), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c18_23), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c20_23), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c28_23), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c30_23), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c38_23), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c39_23), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0c3a_23), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0c3b_23), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0c40_23), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c50_23), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c58_23), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c60_23), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c68_23), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c70_23), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c78_23), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c79_23), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0c7a_23), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0c7b_23), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0c80_23), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c90_23), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c98_23), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0ca0_23), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0ca8_23), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb0_23), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb8_23), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb9_23), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cba_23), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cbb_23), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cd0_23), 0x0cd0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cd8_23), 0x0cd8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ce0_23), 0x0ce0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ce8_23), 0x0ce8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cf0_23), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cf8_23), 0x0cf8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cf9_23), 0x0cf9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cfc_23), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e10_23), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e18_23), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e20_23), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e28_23), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e30_23), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e38_23), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e39_23), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e50_23), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e58_23), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e60_23), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e68_23), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e70_23), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e78_23), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e79_23), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e90_23), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e98_23), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ea0_23), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ea8_23), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0eb0_23), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0eb8_23), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0eb9_23), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ed0_23), 0x0ed0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ed8_23), 0x0ed8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ee0_23), 0x0ee0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ee8_23), 0x0ee8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ef0_23), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ef8_23), 0x0ef8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ef9_23), 0x0ef9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0efc_23), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_1000_23), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1010_23), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1018_23), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1020_23), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1028_23), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1030_23), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1038_23), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1039_23), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103a_23), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103b_23), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103c_23), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1080_23), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1090_23), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1098_23), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10a0_23), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10a8_23), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b0_23), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b8_23), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b9_23), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10ba_23), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10bb_23), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10bc_23), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10c0_23), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10d0_23), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10d8_23), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10e0_23), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10e8_23), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f0_23), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f8_23), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f9_23), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fa_23), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fb_23), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fc_23), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1100_23), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1110_23), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1118_23), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1120_23), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1128_23), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1130_23), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1138_23), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1139_23), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113a_23), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113b_23), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113c_23), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1140_23), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1150_23), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1158_23), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1160_23), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1168_23), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1170_23), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1178_23), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1179_23), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117a_23), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117b_23), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117c_23), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1180_23), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1190_23), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1198_23), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11a0_23), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11a8_23), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b0_23), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b8_23), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b9_23), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11ba_23), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11bb_23), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11bc_23), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11c0_23), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11d0_23), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11d8_23), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11e0_23), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11e8_23), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f0_23), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f8_23), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f9_23), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fa_23), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fb_23), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fc_23), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13c0_23), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13d0_23), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13d8_23), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13e0_23), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13e8_23), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f0_23), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f8_23), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f9_23), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fa_23), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fb_23), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fc_23), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2000_23), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2008_23), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2010_23), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2018_23), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2020_23), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2028_23), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2030_23), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2038_23), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2039_23), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203a_23), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203b_23), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203c_23), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2040_23), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2048_23), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2050_23), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2058_23), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2060_23), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2068_23), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2070_23), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2078_23), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2079_23), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207a_23), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207b_23), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207c_23), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2080_23), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2088_23), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2090_23), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2098_23), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20a0_23), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20a8_23), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b0_23), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b8_23), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b9_23), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20ba_23), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20bb_23), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20bc_23), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20c0_23), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20c8_23), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20d0_23), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20d8_23), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20e0_23), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20e8_23), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f0_23), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f8_23), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f9_23), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fa_23), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fb_23), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fc_23), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2100_23), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2108_23), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2110_23), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2118_23), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2120_23), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2128_23), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2130_23), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2138_23), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2139_23), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213a_23), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213b_23), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213c_23), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2140_23), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2148_23), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2150_23), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2158_23), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2160_23), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2168_23), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2170_23), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2178_23), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2179_23), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217a_23), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217b_23), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217c_23), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2180_23), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2188_23), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2190_23), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2198_23), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21a0_23), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21a8_23), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b0_23), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b8_23), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b9_23), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21ba_23), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21bb_23), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21bc_23), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21c0_23), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21c8_23), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21d0_23), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21d8_23), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21e0_23), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21e8_23), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f0_23), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f8_23), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f9_23), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fa_23), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fb_23), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fc_23), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23c0_23), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23c8_23), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23d0_23), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23d8_23), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23e0_23), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23e8_23), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f0_23), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f8_23), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f9_23), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fa_23), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fb_23), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fc_23), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3000_23), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3008_23), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3010_23), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3018_23), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3020_23), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3028_23), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3030_23), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3038_23), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3039_23), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303a_23), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303b_23), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303c_23), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3040_23), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3048_23), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3050_23), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3058_23), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3060_23), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3068_23), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3070_23), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3078_23), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3079_23), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307a_23), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307b_23), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307c_23), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3080_23), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3088_23), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3090_23), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3098_23), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30a0_23), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30a8_23), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b0_23), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b8_23), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b9_23), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30ba_23), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30bb_23), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30bc_23), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30c0_23), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30c8_23), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30d0_23), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30d8_23), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30e0_23), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30e8_23), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f0_23), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f8_23), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f9_23), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fa_23), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fb_23), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fc_23), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3100_23), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3108_23), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3110_23), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3118_23), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3120_23), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3128_23), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3130_23), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3138_23), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3139_23), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313a_23), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313b_23), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313c_23), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3140_23), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3148_23), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3150_23), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3158_23), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3160_23), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3168_23), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3170_23), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3178_23), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3179_23), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317a_23), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317b_23), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317c_23), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3180_23), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3188_23), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3190_23), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3198_23), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31a0_23), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31a8_23), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b0_23), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b8_23), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b9_23), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31ba_23), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31bb_23), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31bc_23), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31c0_23), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31c8_23), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31d0_23), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31d8_23), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31e0_23), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31e8_23), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f0_23), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f8_23), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f9_23), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fa_23), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fb_23), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fc_23), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33c0_23), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33c8_23), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33d0_23), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33d8_23), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33e0_23), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33e8_23), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f0_23), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f8_23), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f9_23), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fa_23), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fb_23), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fc_23), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_4000_23), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4010_23), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4018_23), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4020_23), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4028_23), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4030_23), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4038_23), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4039_23), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4040_23), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4050_23), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4058_23), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4060_23), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4068_23), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4070_23), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4078_23), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4079_23), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4080_23), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4090_23), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4098_23), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40a0_23), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40a8_23), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b0_23), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b8_23), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b9_23), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40c0_23), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40d0_23), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40d8_23), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40e0_23), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40e8_23), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f0_23), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f8_23), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f9_23), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4100_23), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4110_23), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4118_23), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4120_23), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4128_23), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4130_23), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4138_23), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4139_23), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_413a_23), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_413b_23), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_413c_23), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4180_23), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4190_23), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4198_23), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41a0_23), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41a8_23), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b0_23), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b8_23), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b9_23), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41ba_23), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41bb_23), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41bc_23), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41d0_23), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41e8_23), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f0_23), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f8_23), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f9_23), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41fa_23), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41fb_23), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_4200_23), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4210_23), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4218_23), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4220_23), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4228_23), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4230_23), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4238_23), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4239_23), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4240_23), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4250_23), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4258_23), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4260_23), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4268_23), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4270_23), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4278_23), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4279_23), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4280_23), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4290_23), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4298_23), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42a0_23), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42a8_23), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b0_23), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b8_23), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b9_23), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42c0_23), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42d0_23), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42d8_23), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42e0_23), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42e8_23), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42f0_23), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42f8_23), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42f9_23), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4400_23), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4410_23), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4418_23), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4420_23), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4428_23), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4430_23), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4438_23), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4439_23), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4440_23), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4450_23), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4458_23), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4460_23), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4468_23), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4470_23), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4478_23), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4479_23), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4480_23), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4490_23), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4498_23), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44a0_23), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44a8_23), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b0_23), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b8_23), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b9_23), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44c0_23), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44d0_23), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44d8_23), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44e0_23), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44e8_23), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f0_23), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f8_23), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f9_23), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fa_23), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fb_23), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fc_23), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_4600_23), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4610_23), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4618_23), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4620_23), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4628_23), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4630_23), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4638_23), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4639_23), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4640_23), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4650_23), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4658_23), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4660_23), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4668_23), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4670_23), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4678_23), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4679_23), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4680_23), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4690_23), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4698_23), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46a0_23), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46a8_23), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b0_23), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b8_23), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b9_23), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46c0_23), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46d0_23), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46d8_23), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46e0_23), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46e8_23), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f0_23), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f8_23), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f9_23), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fa_23), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fb_23), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fc_23), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_4800_23), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4808_23), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4810_23), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4818_23), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4820_23), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4828_23), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4830_23), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4838_23), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4839_23), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4840_23), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4848_23), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4850_23), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4868_23), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4870_23), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4878_23), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4879_23), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_487a_23), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_487b_23), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4880_23), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ (cpuop_func*)CPUFUNC(op_4890_23), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48a0_23), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48a8_23), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b0_23), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b8_23), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b9_23), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48c0_23), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ (cpuop_func*)CPUFUNC(op_48d0_23), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48e0_23), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48e8_23), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f0_23), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f8_23), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f9_23), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_49c0_23), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a00_23), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a10_23), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a18_23), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a20_23), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a28_23), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a30_23), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a38_23), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a39_23), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a3a_23), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a3b_23), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a3c_23), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a40_23), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a48_23), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a50_23), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a58_23), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a60_23), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a68_23), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a70_23), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a78_23), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a79_23), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a7a_23), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a7b_23), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a7c_23), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a80_23), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a88_23), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a90_23), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a98_23), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4aa0_23), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4aa8_23), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab0_23), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab8_23), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab9_23), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4aba_23), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4abb_23), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4abc_23), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4ac0_23), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ad0_23), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ad8_23), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ae0_23), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ae8_23), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af0_23), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af8_23), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af9_23), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c00_23), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c10_23), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c18_23), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c20_23), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c28_23), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c30_23), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c38_23), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c39_23), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c3a_23), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c3b_23), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c3c_23), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c40_23), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c50_23), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c58_23), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c60_23), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c68_23), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c70_23), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c78_23), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c79_23), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c7a_23), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c7b_23), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c7c_23), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4c90_23), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4c98_23), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4ca8_23), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb0_23), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb8_23), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb9_23), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cba_23), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cbb_23), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cd0_23), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cd8_23), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4ce8_23), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf0_23), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf8_23), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf9_23), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cfa_23), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cfb_23), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4e40_23), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ (cpuop_func*)CPUFUNC(op_4e50_23), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ (cpuop_func*)CPUFUNC(op_4e58_23), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ (cpuop_func*)CPUFUNC(op_4e60_23), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ (cpuop_func*)CPUFUNC(op_4e68_23), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ (cpuop_func*)CPUFUNC(op_4e70_23), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ (cpuop_func*)CPUFUNC(op_4e71_23), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ (cpuop_func*)CPUFUNC(op_4e72_23), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ (cpuop_func*)CPUFUNC(op_4e73_23), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4e74_23), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4e75_23), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ (cpuop_func*)CPUFUNC(op_4e76_23), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ (cpuop_func*)CPUFUNC(op_4e77_23), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4e7a_23), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4e7b_23), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4e90_23), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ea8_23), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb0_23), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb8_23), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb9_23), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eba_23), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ebb_23), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ed0_23), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ee8_23), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef0_23), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef8_23), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef9_23), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4efa_23), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4efb_23), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_5000_23), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5010_23), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5018_23), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5020_23), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5028_23), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5030_23), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5038_23), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5039_23), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5040_23), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5048_23), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_5050_23), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5058_23), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5060_23), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5068_23), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5070_23), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5078_23), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5079_23), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5080_23), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5088_23), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_5090_23), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5098_23), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50a0_23), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50a8_23), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b0_23), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b8_23), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b9_23), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50c0_23), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50c8_23), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_50d0_23), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50d8_23), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50e0_23), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50e8_23), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f0_23), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f8_23), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f9_23), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_50fa_23), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_50fb_23), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_50fc_23), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5100_23), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5110_23), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5118_23), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5120_23), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5128_23), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5130_23), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5138_23), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5139_23), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5140_23), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5148_23), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_5150_23), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5158_23), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5160_23), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5168_23), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5170_23), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5178_23), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5179_23), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5180_23), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5188_23), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_5190_23), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5198_23), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51a0_23), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51a8_23), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b0_23), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b8_23), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b9_23), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51c0_23), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51c8_23), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_51d0_23), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51d8_23), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51e0_23), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51e8_23), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f0_23), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f8_23), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f9_23), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_51fa_23), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_51fb_23), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_51fc_23), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_52c0_23), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52c8_23), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_52d0_23), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52d8_23), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52e0_23), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52e8_23), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f0_23), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f8_23), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f9_23), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_52fa_23), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_52fb_23), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_52fc_23), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_53c0_23), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53c8_23), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_53d0_23), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53d8_23), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53e0_23), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53e8_23), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f0_23), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f8_23), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f9_23), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_53fa_23), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_53fb_23), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_53fc_23), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_54c0_23), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54c8_23), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_54d0_23), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54d8_23), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54e0_23), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54e8_23), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f0_23), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f8_23), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f9_23), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_54fa_23), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_54fb_23), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_54fc_23), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_55c0_23), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55c8_23), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_55d0_23), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55d8_23), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55e0_23), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55e8_23), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f0_23), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f8_23), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f9_23), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_55fa_23), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_55fb_23), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_55fc_23), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_56c0_23), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56c8_23), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_56d0_23), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56d8_23), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56e0_23), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56e8_23), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f0_23), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f8_23), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f9_23), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_56fa_23), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_56fb_23), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_56fc_23), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_57c0_23), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57c8_23), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_57d0_23), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57d8_23), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57e0_23), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57e8_23), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f0_23), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f8_23), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f9_23), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_57fa_23), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_57fb_23), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_57fc_23), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_58c0_23), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58c8_23), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_58d0_23), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58d8_23), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58e0_23), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58e8_23), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f0_23), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f8_23), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f9_23), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_58fa_23), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_58fb_23), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_58fc_23), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_59c0_23), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59c8_23), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_59d0_23), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59d8_23), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59e0_23), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59e8_23), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f0_23), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f8_23), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f9_23), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_59fa_23), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_59fb_23), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_59fc_23), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5ac0_23), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ac8_23), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5ad0_23), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ad8_23), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ae0_23), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ae8_23), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af0_23), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af8_23), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af9_23), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5afa_23), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5afb_23), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5afc_23), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5bc0_23), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bc8_23), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5bd0_23), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bd8_23), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5be0_23), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5be8_23), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf0_23), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf8_23), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf9_23), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5bfa_23), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5bfb_23), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5bfc_23), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5cc0_23), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cc8_23), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5cd0_23), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cd8_23), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ce0_23), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ce8_23), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf0_23), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf8_23), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf9_23), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5cfa_23), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5cfb_23), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5cfc_23), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5dc0_23), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dc8_23), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5dd0_23), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dd8_23), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5de0_23), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5de8_23), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df0_23), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df8_23), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df9_23), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5dfa_23), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5dfb_23), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5dfc_23), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5ec0_23), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ec8_23), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5ed0_23), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ed8_23), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ee0_23), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ee8_23), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef0_23), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef8_23), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef9_23), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5efa_23), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5efb_23), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5efc_23), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5fc0_23), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fc8_23), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5fd0_23), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fd8_23), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fe0_23), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fe8_23), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff0_23), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff8_23), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff9_23), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5ffa_23), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5ffb_23), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5ffc_23), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_6000_23), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6001_23), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_60ff_23), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6100_23), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_6101_23), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_61ff_23), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_6200_23), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6201_23), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_62ff_23), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6300_23), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6301_23), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_63ff_23), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6400_23), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6401_23), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_64ff_23), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6500_23), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6501_23), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_65ff_23), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6600_23), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6601_23), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_66ff_23), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6700_23), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6701_23), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_67ff_23), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6800_23), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6801_23), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_68ff_23), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6900_23), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6901_23), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_69ff_23), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6a00_23), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6a01_23), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6aff_23), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6b00_23), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6b01_23), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6bff_23), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6c00_23), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6c01_23), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6cff_23), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6d00_23), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6d01_23), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6dff_23), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6e00_23), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6e01_23), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6eff_23), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6f00_23), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6f01_23), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6fff_23), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_7000_23), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_8000_23), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8010_23), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8018_23), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8020_23), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8028_23), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8030_23), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8038_23), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8039_23), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803a_23), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803b_23), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803c_23), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8040_23), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8050_23), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8058_23), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8060_23), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8068_23), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8070_23), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8078_23), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8079_23), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807a_23), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807b_23), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807c_23), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8080_23), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8090_23), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8098_23), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80a0_23), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80a8_23), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b0_23), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b8_23), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b9_23), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80ba_23), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80bb_23), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80bc_23), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80c0_23), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80d0_23), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80d8_23), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80e0_23), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80e8_23), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f0_23), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f8_23), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f9_23), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fa_23), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fb_23), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fc_23), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_8100_23), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ (cpuop_func*)CPUFUNC(op_8108_23), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ (cpuop_func*)CPUFUNC(op_8110_23), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8118_23), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8120_23), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8128_23), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8130_23), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8138_23), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8139_23), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_8140_23), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_8148_23), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+{ (cpuop_func*)CPUFUNC(op_8150_23), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8158_23), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8160_23), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8168_23), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8170_23), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8178_23), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8179_23), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_8180_23), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_8188_23), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+{ (cpuop_func*)CPUFUNC(op_8190_23), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8198_23), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81a0_23), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81a8_23), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b0_23), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b8_23), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b9_23), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81c0_23), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81d0_23), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81d8_23), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81e0_23), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81e8_23), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f0_23), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f8_23), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f9_23), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fa_23), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fb_23), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fc_23), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_9000_23), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9010_23), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9018_23), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9020_23), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9028_23), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9030_23), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9038_23), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9039_23), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903a_23), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903b_23), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903c_23), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9040_23), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9048_23), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9050_23), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9058_23), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9060_23), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9068_23), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9070_23), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9078_23), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9079_23), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907a_23), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907b_23), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907c_23), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9080_23), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9088_23), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9090_23), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9098_23), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90a0_23), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90a8_23), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b0_23), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b8_23), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b9_23), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90ba_23), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90bb_23), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90bc_23), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90c0_23), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90c8_23), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90d0_23), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90d8_23), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90e0_23), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90e8_23), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f0_23), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f8_23), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f9_23), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fa_23), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fb_23), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fc_23), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_9100_23), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9108_23), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9110_23), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9118_23), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9120_23), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9128_23), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9130_23), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9138_23), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9139_23), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9140_23), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9148_23), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9150_23), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9158_23), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9160_23), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9168_23), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9170_23), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9178_23), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9179_23), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9180_23), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9188_23), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9190_23), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9198_23), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91a0_23), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91a8_23), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b0_23), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b8_23), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b9_23), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91c0_23), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91c8_23), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91d0_23), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91d8_23), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91e0_23), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91e8_23), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f0_23), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f8_23), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f9_23), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fa_23), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fb_23), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fc_23), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_b000_23), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b010_23), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b018_23), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b020_23), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b028_23), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b030_23), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b038_23), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b039_23), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03a_23), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03b_23), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03c_23), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b040_23), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b048_23), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b050_23), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b058_23), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b060_23), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b068_23), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b070_23), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b078_23), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b079_23), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07a_23), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07b_23), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07c_23), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b080_23), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b088_23), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b090_23), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b098_23), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0a0_23), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0a8_23), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b0_23), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b8_23), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b9_23), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0ba_23), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0bb_23), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0bc_23), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0c0_23), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0c8_23), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0d0_23), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0d8_23), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0e0_23), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0e8_23), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f0_23), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f8_23), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f9_23), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fa_23), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fb_23), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fc_23), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b100_23), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b108_23), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b110_23), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b118_23), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b120_23), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b128_23), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b130_23), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b138_23), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b139_23), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b140_23), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b148_23), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b150_23), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b158_23), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b160_23), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b168_23), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b170_23), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b178_23), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b179_23), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b180_23), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b188_23), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b190_23), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b198_23), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1a0_23), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1a8_23), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b0_23), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b8_23), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b9_23), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1c0_23), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1c8_23), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1d0_23), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1d8_23), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1e0_23), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1e8_23), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f0_23), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f8_23), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f9_23), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fa_23), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fb_23), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fc_23), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_c000_23), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c010_23), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c018_23), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c020_23), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c028_23), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c030_23), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c038_23), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c039_23), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03a_23), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03b_23), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03c_23), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c040_23), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c050_23), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c058_23), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c060_23), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c068_23), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c070_23), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c078_23), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c079_23), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07a_23), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07b_23), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07c_23), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c080_23), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c090_23), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c098_23), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0a0_23), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0a8_23), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b0_23), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b8_23), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b9_23), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0ba_23), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0bb_23), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0bc_23), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0c0_23), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0d0_23), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0d8_23), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0e0_23), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0e8_23), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f0_23), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f8_23), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f9_23), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fa_23), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fb_23), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fc_23), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c100_23), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ (cpuop_func*)CPUFUNC(op_c108_23), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ (cpuop_func*)CPUFUNC(op_c110_23), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c118_23), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c120_23), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c128_23), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c130_23), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c138_23), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c139_23), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c140_23), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c148_23), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c150_23), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c158_23), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c160_23), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c168_23), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c170_23), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c178_23), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c179_23), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c188_23), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c190_23), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c198_23), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1a0_23), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1a8_23), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b0_23), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b8_23), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b9_23), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1c0_23), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1d0_23), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1d8_23), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1e0_23), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1e8_23), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f0_23), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f8_23), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f9_23), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fa_23), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fb_23), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fc_23), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_d000_23), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d010_23), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d018_23), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d020_23), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d028_23), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d030_23), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d038_23), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d039_23), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03a_23), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03b_23), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03c_23), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d040_23), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d048_23), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d050_23), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d058_23), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d060_23), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d068_23), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d070_23), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d078_23), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d079_23), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07a_23), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07b_23), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07c_23), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d080_23), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d088_23), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d090_23), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d098_23), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0a0_23), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0a8_23), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b0_23), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b8_23), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b9_23), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0ba_23), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0bb_23), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0bc_23), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0c0_23), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0c8_23), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0d0_23), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0d8_23), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0e0_23), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0e8_23), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f0_23), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f8_23), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f9_23), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fa_23), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fb_23), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fc_23), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d100_23), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d108_23), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d110_23), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d118_23), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d120_23), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d128_23), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d130_23), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d138_23), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d139_23), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d140_23), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d148_23), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d150_23), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d158_23), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d160_23), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d168_23), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d170_23), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d178_23), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d179_23), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d180_23), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d188_23), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d190_23), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d198_23), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1a0_23), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1a8_23), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b0_23), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b8_23), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b9_23), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1c0_23), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1c8_23), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1d0_23), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1d8_23), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1e0_23), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1e8_23), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f0_23), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f8_23), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f9_23), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fa_23), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fb_23), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fc_23), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_e000_23), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e008_23), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e010_23), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e018_23), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e020_23), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e028_23), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e030_23), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e038_23), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e040_23), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e048_23), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e050_23), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e058_23), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e060_23), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e068_23), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e070_23), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e078_23), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e080_23), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e088_23), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e090_23), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e098_23), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e0a0_23), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e0a8_23), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e0b0_23), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e0b8_23), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e0d0_23), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0d8_23), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0e0_23), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0e8_23), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f0_23), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f8_23), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f9_23), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e100_23), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e108_23), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e110_23), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e118_23), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e120_23), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e128_23), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e130_23), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e138_23), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e140_23), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e148_23), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e150_23), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e158_23), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e160_23), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e168_23), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e170_23), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e178_23), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e180_23), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e188_23), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e190_23), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e198_23), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e1a0_23), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e1a8_23), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e1b0_23), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e1b8_23), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e1d0_23), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1d8_23), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1e0_23), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1e8_23), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f0_23), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f8_23), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f9_23), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e2d0_23), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2d8_23), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2e0_23), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2e8_23), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f0_23), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f8_23), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f9_23), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e3d0_23), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3d8_23), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3e0_23), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3e8_23), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f0_23), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f8_23), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f9_23), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e4d0_23), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4d8_23), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4e0_23), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4e8_23), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f0_23), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f8_23), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f9_23), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e5d0_23), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5d8_23), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5e0_23), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5e8_23), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f0_23), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f8_23), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f9_23), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e6d0_23), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6d8_23), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6e0_23), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6e8_23), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f0_23), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f8_23), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f9_23), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e7d0_23), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7d8_23), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7e0_23), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7e8_23), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f0_23), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f8_23), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f9_23), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8c0_23), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8d0_23), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8e8_23), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8f0_23), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8f8_23), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8f9_23), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8fa_23), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8fb_23), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9c0_23), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9d0_23), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9e8_23), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9f0_23), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9f8_23), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9f9_23), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9fa_23), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9fb_23), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eac0_23), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ead0_23), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eae8_23), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eaf0_23), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eaf8_23), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eaf9_23), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebc0_23), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebd0_23), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebe8_23), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebf0_23), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebf8_23), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebf9_23), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebfa_23), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebfb_23), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecc0_23), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecd0_23), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ece8_23), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecf0_23), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecf8_23), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecf9_23), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edc0_23), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edd0_23), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ede8_23), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edf0_23), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edf8_23), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edf9_23), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edfa_23), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edfb_23), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eec0_23), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eed0_23), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eee8_23), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eef0_23), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eef8_23), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eef9_23), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_efc0_23), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_efd0_23), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_efe8_23), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eff0_23), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eff8_23), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eff9_23), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f000_23), 0xf000, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f008_23), 0xf008, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f010_23), 0xf010, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f018_23), 0xf018, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f020_23), 0xf020, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f028_23), 0xf028, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f030_23), 0xf030, -1, { -3, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f038_23), 0xf038, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f039_23), 0xf039, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f200_23), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f208_23), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f210_23), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f218_23), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f220_23), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f228_23), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f230_23), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f238_23), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f239_23), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f23a_23), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f23b_23), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f23c_23), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f240_23), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f248_23), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f250_23), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f258_23), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f260_23), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f268_23), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f270_23), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f278_23), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f279_23), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f27a_23), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f27b_23), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f27c_23), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f280_23), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f2c0_23), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f310_23), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f320_23), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f328_23), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f330_23), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f338_23), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f339_23), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f350_23), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f358_23), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f368_23), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f370_23), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f378_23), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f379_23), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f37a_23), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f37b_23), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#endif /* CPUEMU_23 */
+#ifdef CPUEMU_24
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_24)[] = {
+{ (cpuop_func*)CPUFUNC(op_0000_24), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0010_24), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0018_24), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0020_24), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0028_24), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0030_24), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0038_24), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0039_24), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_003c_24), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ (cpuop_func*)CPUFUNC(op_0040_24), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0050_24), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0058_24), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0060_24), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0068_24), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0070_24), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0078_24), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0079_24), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_007c_24), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ (cpuop_func*)CPUFUNC(op_0080_24), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0090_24), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0098_24), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00a0_24), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00a8_24), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b0_24), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b8_24), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b9_24), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00d0_24), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00e8_24), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00f0_24), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00f8_24), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00f9_24), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00fa_24), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_00fb_24), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0100_24), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0108_24), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ (cpuop_func*)CPUFUNC(op_0110_24), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0118_24), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0120_24), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0128_24), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0130_24), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0138_24), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0139_24), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013a_24), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013b_24), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013c_24), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0140_24), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0148_24), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ (cpuop_func*)CPUFUNC(op_0150_24), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0158_24), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0160_24), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0168_24), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0170_24), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0178_24), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0179_24), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0180_24), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0188_24), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ (cpuop_func*)CPUFUNC(op_0190_24), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0198_24), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01a0_24), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01a8_24), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b0_24), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b8_24), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b9_24), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01c0_24), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01c8_24), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ (cpuop_func*)CPUFUNC(op_01d0_24), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01d8_24), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01e0_24), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01e8_24), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f0_24), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f8_24), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f9_24), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_0200_24), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0210_24), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0218_24), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0220_24), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0228_24), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0230_24), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0238_24), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0239_24), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_023c_24), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ (cpuop_func*)CPUFUNC(op_0240_24), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0250_24), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0258_24), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0260_24), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0268_24), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0270_24), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0278_24), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0279_24), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_027c_24), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ (cpuop_func*)CPUFUNC(op_0280_24), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0290_24), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0298_24), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02a0_24), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02a8_24), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b0_24), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b8_24), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b9_24), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02d0_24), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02e8_24), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02f0_24), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02f8_24), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02f9_24), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02fa_24), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_02fb_24), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0400_24), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0410_24), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0418_24), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0420_24), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0428_24), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0430_24), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0438_24), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0439_24), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0440_24), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0450_24), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0458_24), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0460_24), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0468_24), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0470_24), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0478_24), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0479_24), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0480_24), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0490_24), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0498_24), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04a0_24), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04a8_24), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b0_24), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b8_24), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b9_24), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04d0_24), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04e8_24), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04f0_24), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04f8_24), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04f9_24), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04fa_24), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_04fb_24), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0600_24), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0610_24), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0618_24), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0620_24), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0628_24), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0630_24), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0638_24), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0639_24), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0640_24), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0650_24), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0658_24), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0660_24), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0668_24), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0670_24), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0678_24), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0679_24), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0680_24), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0690_24), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0698_24), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06a0_24), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06a8_24), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b0_24), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b8_24), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b9_24), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06c0_24), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06c8_24), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06d0_24), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06e8_24), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06f0_24), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06f8_24), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06f9_24), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06fa_24), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_06fb_24), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0800_24), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0810_24), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0818_24), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0820_24), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0828_24), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0830_24), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0838_24), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0839_24), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_083a_24), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_083b_24), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0840_24), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0850_24), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0858_24), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0860_24), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0868_24), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0870_24), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0878_24), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0879_24), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0880_24), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0890_24), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0898_24), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08a0_24), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08a8_24), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b0_24), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b8_24), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b9_24), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08c0_24), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08d0_24), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08d8_24), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08e0_24), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08e8_24), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f0_24), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f8_24), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f9_24), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_0a00_24), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a10_24), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a18_24), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a20_24), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a28_24), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a30_24), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a38_24), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a39_24), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a3c_24), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ (cpuop_func*)CPUFUNC(op_0a40_24), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a50_24), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a58_24), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a60_24), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a68_24), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a70_24), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a78_24), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a79_24), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a7c_24), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ (cpuop_func*)CPUFUNC(op_0a80_24), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a90_24), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a98_24), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0aa0_24), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0aa8_24), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab0_24), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab8_24), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab9_24), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ad0_24), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ad8_24), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ae0_24), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ae8_24), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0af0_24), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0af8_24), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0af9_24), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0c00_24), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c10_24), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c18_24), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c20_24), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c28_24), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c30_24), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c38_24), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c39_24), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0c3a_24), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0c3b_24), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0c40_24), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c50_24), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c58_24), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c60_24), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c68_24), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c70_24), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c78_24), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c79_24), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0c7a_24), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0c7b_24), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ (cpuop_func*)CPUFUNC(op_0c80_24), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c90_24), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c98_24), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0ca0_24), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0ca8_24), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb0_24), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb8_24), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb9_24), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cba_24), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cbb_24), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cd0_24), 0x0cd0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cd8_24), 0x0cd8, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ce0_24), 0x0ce0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ce8_24), 0x0ce8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cf0_24), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cf8_24), 0x0cf8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cf9_24), 0x0cf9, 16, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0cfc_24), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e10_24), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e18_24), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e20_24), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e28_24), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e30_24), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e38_24), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e39_24), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e50_24), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e58_24), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e60_24), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e68_24), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e70_24), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e78_24), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e79_24), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e90_24), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0e98_24), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ea0_24), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ea8_24), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0eb0_24), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0eb8_24), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0eb9_24), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ed0_24), 0x0ed0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ed8_24), 0x0ed8, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ee0_24), 0x0ee0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ee8_24), 0x0ee8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ef0_24), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ef8_24), 0x0ef8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0ef9_24), 0x0ef9, 16, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_0efc_24), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_1000_24), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1010_24), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1018_24), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1020_24), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1028_24), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1030_24), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1038_24), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1039_24), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103a_24), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103b_24), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103c_24), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1080_24), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1090_24), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1098_24), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10a0_24), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10a8_24), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b0_24), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b8_24), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b9_24), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10ba_24), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10bb_24), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10bc_24), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10c0_24), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10d0_24), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10d8_24), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10e0_24), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10e8_24), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f0_24), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f8_24), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f9_24), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fa_24), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fb_24), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fc_24), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1100_24), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1110_24), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1118_24), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1120_24), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1128_24), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1130_24), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1138_24), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1139_24), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113a_24), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113b_24), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113c_24), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1140_24), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1150_24), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1158_24), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1160_24), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1168_24), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1170_24), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1178_24), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1179_24), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117a_24), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117b_24), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117c_24), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1180_24), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1190_24), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1198_24), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11a0_24), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11a8_24), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b0_24), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b8_24), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b9_24), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11ba_24), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11bb_24), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11bc_24), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11c0_24), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11d0_24), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11d8_24), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11e0_24), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11e8_24), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f0_24), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f8_24), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f9_24), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fa_24), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fb_24), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fc_24), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13c0_24), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13d0_24), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13d8_24), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13e0_24), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13e8_24), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f0_24), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f8_24), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f9_24), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fa_24), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fb_24), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fc_24), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2000_24), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2008_24), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2010_24), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2018_24), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2020_24), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2028_24), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2030_24), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2038_24), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2039_24), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203a_24), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203b_24), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203c_24), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2040_24), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2048_24), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2050_24), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2058_24), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2060_24), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2068_24), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2070_24), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2078_24), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2079_24), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207a_24), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207b_24), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207c_24), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2080_24), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2088_24), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2090_24), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2098_24), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20a0_24), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20a8_24), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b0_24), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b8_24), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b9_24), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20ba_24), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20bb_24), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20bc_24), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20c0_24), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20c8_24), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20d0_24), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20d8_24), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20e0_24), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20e8_24), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f0_24), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f8_24), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f9_24), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fa_24), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fb_24), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fc_24), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2100_24), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2108_24), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2110_24), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2118_24), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2120_24), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2128_24), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2130_24), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2138_24), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2139_24), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213a_24), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213b_24), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213c_24), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2140_24), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2148_24), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2150_24), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2158_24), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2160_24), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2168_24), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2170_24), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2178_24), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2179_24), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217a_24), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217b_24), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217c_24), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2180_24), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2188_24), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2190_24), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2198_24), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21a0_24), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21a8_24), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b0_24), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b8_24), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b9_24), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21ba_24), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21bb_24), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21bc_24), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21c0_24), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21c8_24), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21d0_24), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21d8_24), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21e0_24), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21e8_24), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f0_24), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f8_24), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f9_24), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fa_24), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fb_24), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fc_24), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23c0_24), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23c8_24), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23d0_24), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23d8_24), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23e0_24), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23e8_24), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f0_24), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f8_24), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f9_24), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fa_24), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fb_24), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fc_24), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3000_24), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3008_24), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3010_24), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3018_24), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3020_24), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3028_24), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3030_24), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3038_24), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3039_24), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303a_24), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303b_24), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303c_24), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3040_24), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3048_24), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3050_24), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3058_24), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3060_24), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3068_24), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3070_24), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3078_24), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3079_24), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307a_24), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307b_24), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307c_24), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3080_24), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3088_24), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3090_24), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3098_24), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30a0_24), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30a8_24), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b0_24), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b8_24), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b9_24), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30ba_24), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30bb_24), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30bc_24), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30c0_24), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30c8_24), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30d0_24), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30d8_24), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30e0_24), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30e8_24), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f0_24), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f8_24), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f9_24), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fa_24), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fb_24), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fc_24), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3100_24), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3108_24), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3110_24), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3118_24), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3120_24), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3128_24), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3130_24), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3138_24), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3139_24), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313a_24), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313b_24), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313c_24), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3140_24), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3148_24), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3150_24), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3158_24), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3160_24), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3168_24), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3170_24), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3178_24), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3179_24), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317a_24), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317b_24), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317c_24), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3180_24), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3188_24), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3190_24), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3198_24), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31a0_24), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31a8_24), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b0_24), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b8_24), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b9_24), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31ba_24), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31bb_24), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31bc_24), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31c0_24), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31c8_24), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31d0_24), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31d8_24), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31e0_24), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31e8_24), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f0_24), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f8_24), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f9_24), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fa_24), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fb_24), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fc_24), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33c0_24), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33c8_24), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33d0_24), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33d8_24), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33e0_24), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33e8_24), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f0_24), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f8_24), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f9_24), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fa_24), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fb_24), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fc_24), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_4000_24), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4010_24), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4018_24), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4020_24), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4028_24), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4030_24), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4038_24), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4039_24), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4040_24), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4050_24), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4058_24), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4060_24), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4068_24), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4070_24), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4078_24), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4079_24), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4080_24), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4090_24), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4098_24), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40a0_24), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40a8_24), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b0_24), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b8_24), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b9_24), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40c0_24), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40d0_24), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40d8_24), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40e0_24), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40e8_24), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f0_24), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f8_24), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f9_24), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4100_24), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4110_24), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4118_24), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4120_24), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4128_24), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4130_24), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4138_24), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4139_24), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_413a_24), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_413b_24), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_413c_24), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4180_24), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4190_24), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4198_24), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41a0_24), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41a8_24), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b0_24), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b8_24), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b9_24), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41ba_24), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41bb_24), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41bc_24), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41d0_24), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41e8_24), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f0_24), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f8_24), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f9_24), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41fa_24), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41fb_24), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_4200_24), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4210_24), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4218_24), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4220_24), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4228_24), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4230_24), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4238_24), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4239_24), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4240_24), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4250_24), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4258_24), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4260_24), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4268_24), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4270_24), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4278_24), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4279_24), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4280_24), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4290_24), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4298_24), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42a0_24), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42a8_24), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b0_24), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b8_24), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b9_24), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42c0_24), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42d0_24), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42d8_24), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42e0_24), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42e8_24), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42f0_24), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42f8_24), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_42f9_24), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4400_24), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4410_24), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4418_24), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4420_24), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4428_24), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4430_24), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4438_24), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4439_24), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4440_24), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4450_24), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4458_24), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4460_24), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4468_24), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4470_24), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4478_24), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4479_24), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4480_24), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4490_24), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4498_24), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44a0_24), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44a8_24), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b0_24), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b8_24), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b9_24), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44c0_24), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44d0_24), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44d8_24), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44e0_24), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44e8_24), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f0_24), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f8_24), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f9_24), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fa_24), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fb_24), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fc_24), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_4600_24), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4610_24), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4618_24), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4620_24), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4628_24), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4630_24), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4638_24), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4639_24), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4640_24), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4650_24), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4658_24), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4660_24), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4668_24), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4670_24), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4678_24), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4679_24), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4680_24), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4690_24), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4698_24), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46a0_24), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46a8_24), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b0_24), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b8_24), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b9_24), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46c0_24), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46d0_24), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46d8_24), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46e0_24), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46e8_24), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f0_24), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f8_24), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f9_24), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fa_24), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fb_24), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fc_24), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_4800_24), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4808_24), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4810_24), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4818_24), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4820_24), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4828_24), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4830_24), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4838_24), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4839_24), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4840_24), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4848_24), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4850_24), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4868_24), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4870_24), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4878_24), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4879_24), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_487a_24), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_487b_24), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4880_24), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ (cpuop_func*)CPUFUNC(op_4890_24), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48a0_24), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48a8_24), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b0_24), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b8_24), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b9_24), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48c0_24), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ (cpuop_func*)CPUFUNC(op_48d0_24), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48e0_24), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48e8_24), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f0_24), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f8_24), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f9_24), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_49c0_24), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a00_24), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a10_24), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a18_24), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a20_24), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a28_24), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a30_24), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a38_24), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a39_24), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a3a_24), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a3b_24), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a3c_24), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a40_24), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a48_24), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a50_24), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a58_24), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a60_24), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a68_24), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a70_24), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a78_24), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a79_24), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a7a_24), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a7b_24), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a7c_24), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a80_24), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4a88_24), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4a90_24), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a98_24), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4aa0_24), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4aa8_24), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab0_24), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab8_24), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab9_24), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4aba_24), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4abb_24), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4abc_24), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4ac0_24), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ad0_24), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ad8_24), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ae0_24), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ae8_24), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af0_24), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af8_24), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af9_24), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c00_24), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c10_24), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c18_24), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c20_24), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c28_24), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c30_24), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c38_24), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c39_24), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c3a_24), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c3b_24), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c3c_24), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c40_24), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c50_24), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c58_24), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c60_24), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c68_24), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c70_24), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c78_24), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c79_24), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c7a_24), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c7b_24), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4c7c_24), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4c90_24), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4c98_24), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4ca8_24), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb0_24), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb8_24), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb9_24), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cba_24), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cbb_24), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cd0_24), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cd8_24), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4ce8_24), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf0_24), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf8_24), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf9_24), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cfa_24), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cfb_24), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4e40_24), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ (cpuop_func*)CPUFUNC(op_4e50_24), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ (cpuop_func*)CPUFUNC(op_4e58_24), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ (cpuop_func*)CPUFUNC(op_4e60_24), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ (cpuop_func*)CPUFUNC(op_4e68_24), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ (cpuop_func*)CPUFUNC(op_4e70_24), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ (cpuop_func*)CPUFUNC(op_4e71_24), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ (cpuop_func*)CPUFUNC(op_4e72_24), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ (cpuop_func*)CPUFUNC(op_4e73_24), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4e74_24), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4e75_24), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ (cpuop_func*)CPUFUNC(op_4e76_24), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ (cpuop_func*)CPUFUNC(op_4e77_24), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4e7a_24), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_4e7b_24), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+#endif
+{ (cpuop_func*)CPUFUNC(op_4e90_24), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ea8_24), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb0_24), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb8_24), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb9_24), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eba_24), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ebb_24), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ed0_24), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ee8_24), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef0_24), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef8_24), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef9_24), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4efa_24), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4efb_24), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_5000_24), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5010_24), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5018_24), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5020_24), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5028_24), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5030_24), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5038_24), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5039_24), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5040_24), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5048_24), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_5050_24), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5058_24), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5060_24), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5068_24), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5070_24), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5078_24), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5079_24), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5080_24), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5088_24), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_5090_24), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5098_24), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50a0_24), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50a8_24), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b0_24), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b8_24), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b9_24), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50c0_24), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50c8_24), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_50d0_24), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50d8_24), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50e0_24), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50e8_24), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f0_24), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f8_24), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f9_24), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_50fa_24), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_50fb_24), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_50fc_24), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5100_24), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5110_24), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5118_24), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5120_24), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5128_24), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5130_24), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5138_24), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5139_24), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5140_24), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5148_24), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_5150_24), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5158_24), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5160_24), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5168_24), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5170_24), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5178_24), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5179_24), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5180_24), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5188_24), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_5190_24), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5198_24), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51a0_24), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51a8_24), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b0_24), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b8_24), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b9_24), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51c0_24), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51c8_24), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_51d0_24), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51d8_24), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51e0_24), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51e8_24), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f0_24), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f8_24), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f9_24), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_51fa_24), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_51fb_24), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_51fc_24), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_52c0_24), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52c8_24), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_52d0_24), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52d8_24), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52e0_24), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52e8_24), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f0_24), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f8_24), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f9_24), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_52fa_24), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_52fb_24), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_52fc_24), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_53c0_24), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53c8_24), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_53d0_24), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53d8_24), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53e0_24), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53e8_24), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f0_24), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f8_24), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f9_24), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_53fa_24), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_53fb_24), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_53fc_24), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_54c0_24), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54c8_24), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_54d0_24), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54d8_24), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54e0_24), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54e8_24), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f0_24), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f8_24), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f9_24), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_54fa_24), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_54fb_24), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_54fc_24), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_55c0_24), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55c8_24), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_55d0_24), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55d8_24), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55e0_24), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55e8_24), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f0_24), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f8_24), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f9_24), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_55fa_24), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_55fb_24), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_55fc_24), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_56c0_24), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56c8_24), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_56d0_24), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56d8_24), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56e0_24), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56e8_24), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f0_24), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f8_24), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f9_24), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_56fa_24), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_56fb_24), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_56fc_24), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_57c0_24), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57c8_24), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_57d0_24), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57d8_24), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57e0_24), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57e8_24), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f0_24), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f8_24), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f9_24), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_57fa_24), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_57fb_24), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_57fc_24), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_58c0_24), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58c8_24), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_58d0_24), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58d8_24), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58e0_24), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58e8_24), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f0_24), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f8_24), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f9_24), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_58fa_24), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_58fb_24), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_58fc_24), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_59c0_24), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59c8_24), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_59d0_24), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59d8_24), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59e0_24), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59e8_24), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f0_24), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f8_24), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f9_24), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_59fa_24), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_59fb_24), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_59fc_24), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5ac0_24), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ac8_24), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5ad0_24), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ad8_24), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ae0_24), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ae8_24), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af0_24), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af8_24), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af9_24), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5afa_24), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5afb_24), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5afc_24), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5bc0_24), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bc8_24), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5bd0_24), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bd8_24), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5be0_24), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5be8_24), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf0_24), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf8_24), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf9_24), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5bfa_24), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5bfb_24), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5bfc_24), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5cc0_24), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cc8_24), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5cd0_24), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cd8_24), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ce0_24), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ce8_24), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf0_24), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf8_24), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf9_24), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5cfa_24), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5cfb_24), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5cfc_24), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5dc0_24), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dc8_24), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5dd0_24), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dd8_24), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5de0_24), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5de8_24), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df0_24), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df8_24), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df9_24), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5dfa_24), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5dfb_24), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5dfc_24), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5ec0_24), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ec8_24), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5ed0_24), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ed8_24), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ee0_24), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ee8_24), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef0_24), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef8_24), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef9_24), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5efa_24), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5efb_24), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5efc_24), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_5fc0_24), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fc8_24), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5fd0_24), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fd8_24), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fe0_24), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fe8_24), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff0_24), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff8_24), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff9_24), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5ffa_24), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5ffb_24), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_5ffc_24), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ (cpuop_func*)CPUFUNC(op_6000_24), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6001_24), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_60ff_24), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6100_24), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_6101_24), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_61ff_24), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_6200_24), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6201_24), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_62ff_24), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6300_24), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6301_24), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_63ff_24), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6400_24), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6401_24), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_64ff_24), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6500_24), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6501_24), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_65ff_24), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6600_24), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6601_24), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_66ff_24), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6700_24), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6701_24), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_67ff_24), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6800_24), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6801_24), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_68ff_24), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6900_24), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6901_24), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_69ff_24), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6a00_24), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6a01_24), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6aff_24), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6b00_24), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6b01_24), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6bff_24), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6c00_24), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6c01_24), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6cff_24), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6d00_24), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6d01_24), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6dff_24), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6e00_24), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6e01_24), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6eff_24), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6f00_24), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6f01_24), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6fff_24), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_7000_24), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_8000_24), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8010_24), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8018_24), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8020_24), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8028_24), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8030_24), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8038_24), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8039_24), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803a_24), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803b_24), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803c_24), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8040_24), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8050_24), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8058_24), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8060_24), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8068_24), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8070_24), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8078_24), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8079_24), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807a_24), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807b_24), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807c_24), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8080_24), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8090_24), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8098_24), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80a0_24), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80a8_24), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b0_24), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b8_24), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b9_24), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80ba_24), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80bb_24), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80bc_24), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80c0_24), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80d0_24), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80d8_24), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80e0_24), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80e8_24), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f0_24), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f8_24), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f9_24), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fa_24), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fb_24), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fc_24), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_8100_24), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ (cpuop_func*)CPUFUNC(op_8108_24), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ (cpuop_func*)CPUFUNC(op_8110_24), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8118_24), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8120_24), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8128_24), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8130_24), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8138_24), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8139_24), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_8140_24), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_8148_24), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+{ (cpuop_func*)CPUFUNC(op_8150_24), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8158_24), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8160_24), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8168_24), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8170_24), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8178_24), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8179_24), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_8180_24), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_8188_24), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+{ (cpuop_func*)CPUFUNC(op_8190_24), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8198_24), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81a0_24), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81a8_24), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b0_24), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b8_24), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b9_24), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81c0_24), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81d0_24), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81d8_24), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81e0_24), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81e8_24), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f0_24), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f8_24), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f9_24), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fa_24), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fb_24), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fc_24), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_9000_24), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9010_24), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9018_24), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9020_24), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9028_24), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9030_24), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9038_24), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9039_24), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903a_24), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903b_24), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903c_24), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9040_24), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9048_24), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9050_24), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9058_24), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9060_24), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9068_24), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9070_24), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9078_24), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9079_24), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907a_24), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907b_24), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907c_24), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9080_24), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9088_24), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9090_24), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9098_24), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90a0_24), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90a8_24), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b0_24), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b8_24), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b9_24), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90ba_24), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90bb_24), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90bc_24), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90c0_24), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90c8_24), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90d0_24), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90d8_24), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90e0_24), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90e8_24), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f0_24), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f8_24), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f9_24), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fa_24), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fb_24), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fc_24), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_9100_24), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9108_24), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9110_24), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9118_24), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9120_24), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9128_24), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9130_24), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9138_24), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9139_24), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9140_24), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9148_24), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9150_24), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9158_24), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9160_24), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9168_24), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9170_24), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9178_24), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9179_24), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9180_24), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9188_24), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9190_24), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9198_24), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91a0_24), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91a8_24), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b0_24), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b8_24), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b9_24), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91c0_24), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91c8_24), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91d0_24), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91d8_24), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91e0_24), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91e8_24), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f0_24), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f8_24), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f9_24), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fa_24), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fb_24), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fc_24), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_b000_24), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b010_24), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b018_24), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b020_24), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b028_24), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b030_24), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b038_24), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b039_24), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03a_24), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03b_24), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03c_24), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b040_24), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b048_24), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b050_24), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b058_24), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b060_24), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b068_24), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b070_24), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b078_24), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b079_24), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07a_24), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07b_24), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07c_24), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b080_24), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b088_24), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b090_24), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b098_24), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0a0_24), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0a8_24), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b0_24), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b8_24), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b9_24), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0ba_24), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0bb_24), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0bc_24), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0c0_24), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0c8_24), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0d0_24), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0d8_24), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0e0_24), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0e8_24), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f0_24), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f8_24), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f9_24), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fa_24), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fb_24), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fc_24), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b100_24), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b108_24), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b110_24), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b118_24), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b120_24), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b128_24), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b130_24), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b138_24), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b139_24), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b140_24), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b148_24), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b150_24), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b158_24), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b160_24), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b168_24), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b170_24), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b178_24), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b179_24), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b180_24), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b188_24), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b190_24), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b198_24), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1a0_24), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1a8_24), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b0_24), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b8_24), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b9_24), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1c0_24), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1c8_24), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1d0_24), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1d8_24), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1e0_24), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1e8_24), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f0_24), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f8_24), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f9_24), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fa_24), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fb_24), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fc_24), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_c000_24), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c010_24), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c018_24), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c020_24), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c028_24), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c030_24), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c038_24), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c039_24), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03a_24), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03b_24), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03c_24), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c040_24), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c050_24), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c058_24), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c060_24), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c068_24), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c070_24), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c078_24), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c079_24), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07a_24), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07b_24), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07c_24), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c080_24), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c090_24), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c098_24), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0a0_24), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0a8_24), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b0_24), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b8_24), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b9_24), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0ba_24), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0bb_24), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0bc_24), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0c0_24), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0d0_24), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0d8_24), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0e0_24), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0e8_24), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f0_24), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f8_24), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f9_24), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fa_24), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fb_24), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fc_24), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c100_24), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ (cpuop_func*)CPUFUNC(op_c108_24), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ (cpuop_func*)CPUFUNC(op_c110_24), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c118_24), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c120_24), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c128_24), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c130_24), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c138_24), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c139_24), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c140_24), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c148_24), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c150_24), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c158_24), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c160_24), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c168_24), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c170_24), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c178_24), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c179_24), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c188_24), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c190_24), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c198_24), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1a0_24), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1a8_24), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b0_24), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b8_24), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b9_24), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1c0_24), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1d0_24), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1d8_24), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1e0_24), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1e8_24), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f0_24), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f8_24), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f9_24), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fa_24), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fb_24), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fc_24), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_d000_24), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d010_24), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d018_24), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d020_24), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d028_24), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d030_24), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d038_24), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d039_24), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03a_24), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03b_24), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03c_24), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d040_24), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d048_24), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d050_24), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d058_24), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d060_24), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d068_24), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d070_24), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d078_24), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d079_24), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07a_24), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07b_24), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07c_24), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d080_24), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d088_24), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d090_24), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d098_24), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0a0_24), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0a8_24), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b0_24), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b8_24), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b9_24), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0ba_24), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0bb_24), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0bc_24), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0c0_24), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0c8_24), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0d0_24), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0d8_24), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0e0_24), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0e8_24), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f0_24), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f8_24), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f9_24), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fa_24), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fb_24), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fc_24), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d100_24), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d108_24), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d110_24), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d118_24), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d120_24), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d128_24), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d130_24), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d138_24), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d139_24), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d140_24), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d148_24), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d150_24), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d158_24), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d160_24), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d168_24), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d170_24), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d178_24), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d179_24), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d180_24), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d188_24), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d190_24), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d198_24), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1a0_24), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1a8_24), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b0_24), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b8_24), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b9_24), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1c0_24), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1c8_24), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1d0_24), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1d8_24), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1e0_24), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1e8_24), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f0_24), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f8_24), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f9_24), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fa_24), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fb_24), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fc_24), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_e000_24), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e008_24), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e010_24), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e018_24), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e020_24), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e028_24), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e030_24), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e038_24), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e040_24), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e048_24), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e050_24), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e058_24), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e060_24), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e068_24), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e070_24), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e078_24), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e080_24), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e088_24), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e090_24), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e098_24), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e0a0_24), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e0a8_24), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e0b0_24), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e0b8_24), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e0d0_24), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0d8_24), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0e0_24), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0e8_24), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f0_24), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f8_24), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f9_24), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e100_24), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e108_24), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e110_24), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e118_24), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e120_24), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e128_24), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e130_24), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e138_24), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e140_24), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e148_24), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e150_24), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e158_24), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e160_24), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e168_24), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e170_24), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e178_24), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e180_24), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e188_24), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e190_24), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e198_24), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e1a0_24), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e1a8_24), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e1b0_24), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e1b8_24), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e1d0_24), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1d8_24), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1e0_24), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1e8_24), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f0_24), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f8_24), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f9_24), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e2d0_24), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2d8_24), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2e0_24), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2e8_24), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f0_24), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f8_24), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f9_24), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e3d0_24), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3d8_24), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3e0_24), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3e8_24), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f0_24), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f8_24), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f9_24), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e4d0_24), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4d8_24), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4e0_24), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4e8_24), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f0_24), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f8_24), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f9_24), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e5d0_24), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5d8_24), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5e0_24), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5e8_24), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f0_24), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f8_24), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f9_24), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e6d0_24), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6d8_24), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6e0_24), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6e8_24), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f0_24), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f8_24), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f9_24), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e7d0_24), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7d8_24), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7e0_24), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7e8_24), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f0_24), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f8_24), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f9_24), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8c0_24), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8d0_24), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8e8_24), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8f0_24), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8f8_24), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8f9_24), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8fa_24), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e8fb_24), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9c0_24), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9d0_24), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9e8_24), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9f0_24), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9f8_24), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9f9_24), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9fa_24), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_e9fb_24), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eac0_24), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ead0_24), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eae8_24), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eaf0_24), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eaf8_24), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eaf9_24), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebc0_24), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebd0_24), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebe8_24), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebf0_24), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebf8_24), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebf9_24), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebfa_24), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ebfb_24), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecc0_24), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecd0_24), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ece8_24), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecf0_24), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecf8_24), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ecf9_24), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edc0_24), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edd0_24), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_ede8_24), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edf0_24), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edf8_24), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edf9_24), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edfa_24), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_edfb_24), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eec0_24), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eed0_24), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eee8_24), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eef0_24), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eef8_24), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eef9_24), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_efc0_24), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_efd0_24), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_efe8_24), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eff0_24), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eff8_24), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_eff9_24), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f000_24), 0xf000, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f008_24), 0xf008, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f010_24), 0xf010, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f018_24), 0xf018, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f020_24), 0xf020, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f028_24), 0xf028, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f030_24), 0xf030, -1, { -3, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f038_24), 0xf038, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f039_24), 0xf039, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f200_24), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f208_24), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f210_24), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f218_24), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f220_24), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f228_24), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f230_24), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f238_24), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f239_24), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f23a_24), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f23b_24), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f23c_24), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f240_24), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f248_24), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f250_24), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f258_24), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f260_24), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f268_24), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f270_24), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f278_24), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f279_24), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f27a_24), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f27b_24), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f27c_24), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f280_24), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f2c0_24), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f310_24), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f320_24), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f328_24), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f330_24), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f338_24), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f339_24), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f350_24), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f358_24), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f368_24), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f370_24), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f378_24), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f379_24), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f37a_24), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f37b_24), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f408_24), 0xf408, -1, { 0, 0 }, 0 }, /* CINVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f410_24), 0xf410, -1, { 0, 0 }, 0 }, /* CINVP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f418_24), 0xf418, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f419_24), 0xf419, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f41a_24), 0xf41a, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f41b_24), 0xf41b, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f41c_24), 0xf41c, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f41d_24), 0xf41d, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f41e_24), 0xf41e, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f41f_24), 0xf41f, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f428_24), 0xf428, -1, { 0, 0 }, 0 }, /* CPUSHL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f430_24), 0xf430, -1, { 0, 0 }, 0 }, /* CPUSHP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f438_24), 0xf438, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f439_24), 0xf439, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f43a_24), 0xf43a, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f43b_24), 0xf43b, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f43c_24), 0xf43c, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f43d_24), 0xf43d, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f43e_24), 0xf43e, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f43f_24), 0xf43f, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f500_24), 0xf500, -1, { 0, 0 }, 0 }, /* PFLUSHN */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f508_24), 0xf508, -1, { 0, 0 }, 0 }, /* PFLUSH */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f510_24), 0xf510, -1, { 0, 0 }, 0 }, /* PFLUSHAN */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f518_24), 0xf518, -1, { 0, 0 }, 0 }, /* PFLUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f548_24), 0xf548, -1, { 0, 0 }, 0 }, /* PTESTW */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f568_24), 0xf568, -1, { 0, 0 }, 0 }, /* PTESTR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f588_24), 0xf588, -1, { 0, 0 }, 0 }, /* PLPAW */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f5c8_24), 0xf5c8, -1, { 0, 0 }, 0 }, /* PLPAR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f600_24), 0xf600, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f608_24), 0xf608, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f610_24), 0xf610, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f618_24), 0xf618, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f620_24), 0xf620, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ (cpuop_func*)CPUFUNC(op_f800_24), 0xf800, -1, { 0, 0 }, 0 }, /* LPSTOP */
+#endif
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#endif /* CPUEMU_24 */
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_25)[] = {
+{ (cpuop_func*)CPUFUNC(op_0000_24), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0010_24), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0018_24), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0020_24), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0028_24), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0030_24), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0038_24), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0039_24), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_003c_24), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ (cpuop_func*)CPUFUNC(op_0040_24), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0050_24), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0058_24), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0060_24), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0068_24), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0070_24), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0078_24), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0079_24), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_007c_24), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ (cpuop_func*)CPUFUNC(op_0080_24), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0090_24), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_0098_24), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00a0_24), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00a8_24), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b0_24), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b8_24), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00b9_24), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_00d0_24), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_00e8_24), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_00f0_24), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_00f8_24), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_00f9_24), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_00fa_24), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_00fb_24), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_0100_24), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0108_24), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ (cpuop_func*)CPUFUNC(op_0110_24), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0118_24), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0120_24), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0128_24), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0130_24), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0138_24), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0139_24), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013a_24), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013b_24), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_013c_24), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0140_24), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0148_24), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ (cpuop_func*)CPUFUNC(op_0150_24), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0158_24), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0160_24), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0168_24), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0170_24), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0178_24), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0179_24), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0180_24), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0188_24), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ (cpuop_func*)CPUFUNC(op_0190_24), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0198_24), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01a0_24), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01a8_24), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b0_24), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b8_24), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01b9_24), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_01c0_24), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01c8_24), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ (cpuop_func*)CPUFUNC(op_01d0_24), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01d8_24), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01e0_24), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01e8_24), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f0_24), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f8_24), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_01f9_24), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_0200_24), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0210_24), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0218_24), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0220_24), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0228_24), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0230_24), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0238_24), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0239_24), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_023c_24), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ (cpuop_func*)CPUFUNC(op_0240_24), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0250_24), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0258_24), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0260_24), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0268_24), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0270_24), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0278_24), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0279_24), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_027c_24), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ (cpuop_func*)CPUFUNC(op_0280_24), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0290_24), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_0298_24), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02a0_24), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02a8_24), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b0_24), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b8_24), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02b9_24), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_02d0_24), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_02e8_24), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_02f0_24), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_02f8_24), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_02f9_24), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_02fa_24), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_02fb_24), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_0400_24), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0410_24), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0418_24), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0420_24), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0428_24), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0430_24), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0438_24), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0439_24), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0440_24), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0450_24), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0458_24), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0460_24), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0468_24), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0470_24), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0478_24), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0479_24), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0480_24), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0490_24), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_0498_24), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04a0_24), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04a8_24), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b0_24), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b8_24), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04b9_24), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_04d0_24), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_04e8_24), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_04f0_24), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_04f8_24), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_04f9_24), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_04fa_24), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_04fb_24), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ (cpuop_func*)CPUFUNC(op_0600_24), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0610_24), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0618_24), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0620_24), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0628_24), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0630_24), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0638_24), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0639_24), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0640_24), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0650_24), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0658_24), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0660_24), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0668_24), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0670_24), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0678_24), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0679_24), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0680_24), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0690_24), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_0698_24), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06a0_24), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06a8_24), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b0_24), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b8_24), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06b9_24), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_06c0_24), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+{ (cpuop_func*)CPUFUNC(op_06c8_24), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+{ (cpuop_func*)CPUFUNC(op_06d0_24), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+{ (cpuop_func*)CPUFUNC(op_06e8_24), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+{ (cpuop_func*)CPUFUNC(op_06f0_24), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+{ (cpuop_func*)CPUFUNC(op_06f8_24), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+{ (cpuop_func*)CPUFUNC(op_06f9_24), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+{ (cpuop_func*)CPUFUNC(op_06fa_24), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+{ (cpuop_func*)CPUFUNC(op_06fb_24), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+{ (cpuop_func*)CPUFUNC(op_0800_24), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0810_24), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0818_24), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0820_24), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0828_24), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0830_24), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0838_24), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0839_24), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_083a_24), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_083b_24), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ (cpuop_func*)CPUFUNC(op_0840_24), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0850_24), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0858_24), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0860_24), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0868_24), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0870_24), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0878_24), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0879_24), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ (cpuop_func*)CPUFUNC(op_0880_24), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0890_24), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_0898_24), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08a0_24), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08a8_24), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b0_24), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b8_24), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08b9_24), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ (cpuop_func*)CPUFUNC(op_08c0_24), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08d0_24), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08d8_24), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08e0_24), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08e8_24), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f0_24), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f8_24), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_08f9_24), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ (cpuop_func*)CPUFUNC(op_0a00_24), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a10_24), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a18_24), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a20_24), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a28_24), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a30_24), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a38_24), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a39_24), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a3c_24), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ (cpuop_func*)CPUFUNC(op_0a40_24), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a50_24), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a58_24), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a60_24), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a68_24), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a70_24), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a78_24), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a79_24), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a7c_24), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ (cpuop_func*)CPUFUNC(op_0a80_24), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a90_24), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0a98_24), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0aa0_24), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0aa8_24), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab0_24), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab8_24), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ab9_24), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_0ad0_24), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0ad8_24), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0ae0_24), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0ae8_24), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0af0_24), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0af8_24), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0af9_24), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0c00_24), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c10_24), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c18_24), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c20_24), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c28_24), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c30_24), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c38_24), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c39_24), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c3a_24), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c3b_24), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c40_24), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c50_24), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c58_24), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c60_24), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c68_24), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c70_24), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c78_24), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c79_24), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c7a_24), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c7b_24), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c80_24), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c90_24), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0c98_24), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0ca0_24), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0ca8_24), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb0_24), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb8_24), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cb9_24), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cba_24), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cbb_24), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_0cd0_24), 0x0cd0, 8, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0cd8_24), 0x0cd8, 8, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0ce0_24), 0x0ce0, 8, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0ce8_24), 0x0ce8, 12, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0cf0_24), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0cf8_24), 0x0cf8, 12, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0cf9_24), 0x0cf9, 16, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0cfc_24), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+{ (cpuop_func*)CPUFUNC(op_0e10_24), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e18_24), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e20_24), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e28_24), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e30_24), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e38_24), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e39_24), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e50_24), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e58_24), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e60_24), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e68_24), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e70_24), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e78_24), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e79_24), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e90_24), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0e98_24), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0ea0_24), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0ea8_24), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0eb0_24), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0eb8_24), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0eb9_24), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+{ (cpuop_func*)CPUFUNC(op_0ed0_24), 0x0ed0, 8, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0ed8_24), 0x0ed8, 8, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0ee0_24), 0x0ee0, 8, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0ee8_24), 0x0ee8, 12, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0ef0_24), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0ef8_24), 0x0ef8, 12, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0ef9_24), 0x0ef9, 16, { 0, 0 }, 0 }, /* CAS */
+{ (cpuop_func*)CPUFUNC(op_0efc_24), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+{ (cpuop_func*)CPUFUNC(op_1000_24), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1010_24), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1018_24), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1020_24), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1028_24), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1030_24), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1038_24), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1039_24), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103a_24), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103b_24), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_103c_24), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1080_24), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1090_24), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1098_24), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10a0_24), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10a8_24), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b0_24), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b8_24), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10b9_24), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10ba_24), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10bb_24), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10bc_24), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10c0_24), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10d0_24), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10d8_24), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10e0_24), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10e8_24), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f0_24), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f8_24), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10f9_24), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fa_24), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fb_24), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_10fc_24), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1100_24), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1110_24), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1118_24), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1120_24), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1128_24), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1130_24), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1138_24), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1139_24), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113a_24), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113b_24), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_113c_24), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1140_24), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1150_24), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1158_24), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1160_24), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1168_24), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1170_24), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1178_24), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1179_24), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117a_24), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117b_24), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_117c_24), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1180_24), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1190_24), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_1198_24), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11a0_24), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11a8_24), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b0_24), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b8_24), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11b9_24), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11ba_24), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11bb_24), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11bc_24), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11c0_24), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11d0_24), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11d8_24), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11e0_24), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11e8_24), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f0_24), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f8_24), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11f9_24), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fa_24), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fb_24), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_11fc_24), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13c0_24), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13d0_24), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13d8_24), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13e0_24), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13e8_24), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f0_24), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f8_24), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13f9_24), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fa_24), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fb_24), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_13fc_24), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2000_24), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2008_24), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2010_24), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2018_24), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2020_24), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2028_24), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2030_24), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2038_24), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2039_24), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203a_24), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203b_24), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_203c_24), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2040_24), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2048_24), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2050_24), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2058_24), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2060_24), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2068_24), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2070_24), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2078_24), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2079_24), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207a_24), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207b_24), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_207c_24), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_2080_24), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2088_24), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2090_24), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2098_24), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20a0_24), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20a8_24), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b0_24), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b8_24), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20b9_24), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20ba_24), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20bb_24), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20bc_24), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20c0_24), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20c8_24), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20d0_24), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20d8_24), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20e0_24), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20e8_24), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f0_24), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f8_24), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20f9_24), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fa_24), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fb_24), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_20fc_24), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2100_24), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2108_24), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2110_24), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2118_24), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2120_24), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2128_24), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2130_24), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2138_24), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2139_24), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213a_24), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213b_24), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_213c_24), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2140_24), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2148_24), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2150_24), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2158_24), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2160_24), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2168_24), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2170_24), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2178_24), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2179_24), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217a_24), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217b_24), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_217c_24), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2180_24), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2188_24), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2190_24), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_2198_24), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21a0_24), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21a8_24), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b0_24), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b8_24), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21b9_24), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21ba_24), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21bb_24), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21bc_24), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21c0_24), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21c8_24), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21d0_24), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21d8_24), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21e0_24), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21e8_24), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f0_24), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f8_24), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21f9_24), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fa_24), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fb_24), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_21fc_24), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23c0_24), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23c8_24), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23d0_24), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23d8_24), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23e0_24), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23e8_24), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f0_24), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f8_24), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23f9_24), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fa_24), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fb_24), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_23fc_24), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3000_24), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3008_24), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3010_24), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3018_24), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3020_24), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3028_24), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3030_24), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3038_24), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3039_24), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303a_24), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303b_24), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_303c_24), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3040_24), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3048_24), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3050_24), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3058_24), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3060_24), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3068_24), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3070_24), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3078_24), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3079_24), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307a_24), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307b_24), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_307c_24), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ (cpuop_func*)CPUFUNC(op_3080_24), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3088_24), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3090_24), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3098_24), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30a0_24), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30a8_24), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b0_24), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b8_24), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30b9_24), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30ba_24), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30bb_24), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30bc_24), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30c0_24), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30c8_24), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30d0_24), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30d8_24), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30e0_24), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30e8_24), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f0_24), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f8_24), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30f9_24), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fa_24), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fb_24), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_30fc_24), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3100_24), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3108_24), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3110_24), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3118_24), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3120_24), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3128_24), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3130_24), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3138_24), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3139_24), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313a_24), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313b_24), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_313c_24), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3140_24), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3148_24), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3150_24), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3158_24), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3160_24), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3168_24), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3170_24), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3178_24), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3179_24), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317a_24), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317b_24), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_317c_24), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3180_24), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3188_24), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3190_24), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_3198_24), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31a0_24), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31a8_24), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b0_24), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b8_24), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31b9_24), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31ba_24), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31bb_24), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31bc_24), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31c0_24), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31c8_24), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31d0_24), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31d8_24), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31e0_24), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31e8_24), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f0_24), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f8_24), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31f9_24), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fa_24), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fb_24), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_31fc_24), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33c0_24), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33c8_24), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33d0_24), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33d8_24), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33e0_24), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33e8_24), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f0_24), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f8_24), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33f9_24), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fa_24), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fb_24), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_33fc_24), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_4000_24), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4010_24), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4018_24), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4020_24), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4028_24), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4030_24), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4038_24), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4039_24), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4040_24), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4050_24), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4058_24), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4060_24), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4068_24), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4070_24), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4078_24), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4079_24), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4080_24), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4090_24), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_4098_24), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40a0_24), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40a8_24), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b0_24), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b8_24), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40b9_24), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ (cpuop_func*)CPUFUNC(op_40c0_24), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40d0_24), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40d8_24), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40e0_24), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40e8_24), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f0_24), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f8_24), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_40f9_24), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_4100_24), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4110_24), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4118_24), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4120_24), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4128_24), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4130_24), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4138_24), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4139_24), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_413a_24), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_413b_24), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_413c_24), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4180_24), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4190_24), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_4198_24), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41a0_24), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41a8_24), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b0_24), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b8_24), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41b9_24), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41ba_24), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41bb_24), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41bc_24), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ (cpuop_func*)CPUFUNC(op_41d0_24), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41e8_24), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f0_24), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f8_24), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41f9_24), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41fa_24), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_41fb_24), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ (cpuop_func*)CPUFUNC(op_4200_24), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4210_24), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4218_24), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4220_24), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4228_24), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4230_24), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4238_24), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4239_24), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4240_24), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4250_24), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4258_24), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4260_24), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4268_24), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4270_24), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4278_24), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4279_24), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4280_24), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4290_24), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_4298_24), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42a0_24), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42a8_24), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b0_24), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b8_24), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42b9_24), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+{ (cpuop_func*)CPUFUNC(op_42c0_24), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_42d0_24), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_42d8_24), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_42e0_24), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_42e8_24), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_42f0_24), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_42f8_24), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_42f9_24), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ (cpuop_func*)CPUFUNC(op_4400_24), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4410_24), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4418_24), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4420_24), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4428_24), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4430_24), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4438_24), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4439_24), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4440_24), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4450_24), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4458_24), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4460_24), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4468_24), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4470_24), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4478_24), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4479_24), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4480_24), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4490_24), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_4498_24), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44a0_24), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44a8_24), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b0_24), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b8_24), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44b9_24), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ (cpuop_func*)CPUFUNC(op_44c0_24), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44d0_24), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44d8_24), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44e0_24), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44e8_24), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f0_24), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f8_24), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44f9_24), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fa_24), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fb_24), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_44fc_24), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_4600_24), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4610_24), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4618_24), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4620_24), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4628_24), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4630_24), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4638_24), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4639_24), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4640_24), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4650_24), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4658_24), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4660_24), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4668_24), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4670_24), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4678_24), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4679_24), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4680_24), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4690_24), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_4698_24), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46a0_24), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46a8_24), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b0_24), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b8_24), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46b9_24), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ (cpuop_func*)CPUFUNC(op_46c0_24), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46d0_24), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46d8_24), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46e0_24), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46e8_24), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f0_24), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f8_24), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46f9_24), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fa_24), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fb_24), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_46fc_24), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ (cpuop_func*)CPUFUNC(op_4800_24), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4808_24), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+{ (cpuop_func*)CPUFUNC(op_4810_24), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4818_24), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4820_24), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4828_24), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4830_24), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4838_24), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4839_24), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ (cpuop_func*)CPUFUNC(op_4840_24), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ (cpuop_func*)CPUFUNC(op_4848_24), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+{ (cpuop_func*)CPUFUNC(op_4850_24), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4868_24), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4870_24), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4878_24), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4879_24), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_487a_24), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_487b_24), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ (cpuop_func*)CPUFUNC(op_4880_24), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ (cpuop_func*)CPUFUNC(op_4890_24), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48a0_24), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48a8_24), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b0_24), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b8_24), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48b9_24), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48c0_24), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ (cpuop_func*)CPUFUNC(op_48d0_24), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48e0_24), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48e8_24), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f0_24), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f8_24), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_48f9_24), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ (cpuop_func*)CPUFUNC(op_49c0_24), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ (cpuop_func*)CPUFUNC(op_4a00_24), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a10_24), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a18_24), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a20_24), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a28_24), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a30_24), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a38_24), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a39_24), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a3a_24), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a3b_24), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a3c_24), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a40_24), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a48_24), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a50_24), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a58_24), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a60_24), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a68_24), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a70_24), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a78_24), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a79_24), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a7a_24), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a7b_24), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a7c_24), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a80_24), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a88_24), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a90_24), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4a98_24), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4aa0_24), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4aa8_24), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab0_24), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab8_24), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ab9_24), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4aba_24), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4abb_24), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4abc_24), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+{ (cpuop_func*)CPUFUNC(op_4ac0_24), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ad0_24), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ad8_24), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ae0_24), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4ae8_24), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af0_24), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af8_24), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4af9_24), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ (cpuop_func*)CPUFUNC(op_4c00_24), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+{ (cpuop_func*)CPUFUNC(op_4c10_24), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+{ (cpuop_func*)CPUFUNC(op_4c18_24), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+{ (cpuop_func*)CPUFUNC(op_4c20_24), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+{ (cpuop_func*)CPUFUNC(op_4c28_24), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+{ (cpuop_func*)CPUFUNC(op_4c30_24), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+{ (cpuop_func*)CPUFUNC(op_4c38_24), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+{ (cpuop_func*)CPUFUNC(op_4c39_24), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+{ (cpuop_func*)CPUFUNC(op_4c3a_24), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+{ (cpuop_func*)CPUFUNC(op_4c3b_24), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+{ (cpuop_func*)CPUFUNC(op_4c3c_24), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+{ (cpuop_func*)CPUFUNC(op_4c40_24), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+{ (cpuop_func*)CPUFUNC(op_4c50_24), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+{ (cpuop_func*)CPUFUNC(op_4c58_24), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+{ (cpuop_func*)CPUFUNC(op_4c60_24), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+{ (cpuop_func*)CPUFUNC(op_4c68_24), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+{ (cpuop_func*)CPUFUNC(op_4c70_24), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+{ (cpuop_func*)CPUFUNC(op_4c78_24), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+{ (cpuop_func*)CPUFUNC(op_4c79_24), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+{ (cpuop_func*)CPUFUNC(op_4c7a_24), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+{ (cpuop_func*)CPUFUNC(op_4c7b_24), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+{ (cpuop_func*)CPUFUNC(op_4c7c_24), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+{ (cpuop_func*)CPUFUNC(op_4c90_24), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4c98_24), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4ca8_24), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb0_24), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb8_24), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cb9_24), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cba_24), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cbb_24), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cd0_24), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cd8_24), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4ce8_24), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf0_24), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf8_24), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cf9_24), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cfa_24), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4cfb_24), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ (cpuop_func*)CPUFUNC(op_4e40_24), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ (cpuop_func*)CPUFUNC(op_4e50_24), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ (cpuop_func*)CPUFUNC(op_4e58_24), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ (cpuop_func*)CPUFUNC(op_4e60_24), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ (cpuop_func*)CPUFUNC(op_4e68_24), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ (cpuop_func*)CPUFUNC(op_4e70_24), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ (cpuop_func*)CPUFUNC(op_4e71_24), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ (cpuop_func*)CPUFUNC(op_4e72_24), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ (cpuop_func*)CPUFUNC(op_4e73_24), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+{ (cpuop_func*)CPUFUNC(op_4e74_24), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+{ (cpuop_func*)CPUFUNC(op_4e75_24), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ (cpuop_func*)CPUFUNC(op_4e76_24), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ (cpuop_func*)CPUFUNC(op_4e77_24), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+{ (cpuop_func*)CPUFUNC(op_4e7a_24), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+{ (cpuop_func*)CPUFUNC(op_4e7b_24), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+{ (cpuop_func*)CPUFUNC(op_4e90_24), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ea8_24), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb0_24), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb8_24), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eb9_24), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4eba_24), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ebb_24), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ (cpuop_func*)CPUFUNC(op_4ed0_24), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ee8_24), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef0_24), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef8_24), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4ef9_24), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4efa_24), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_4efb_24), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ (cpuop_func*)CPUFUNC(op_5000_24), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5010_24), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5018_24), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5020_24), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5028_24), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5030_24), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5038_24), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5039_24), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5040_24), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5048_24), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_5050_24), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5058_24), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5060_24), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5068_24), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5070_24), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5078_24), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5079_24), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5080_24), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5088_24), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_5090_24), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_5098_24), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50a0_24), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50a8_24), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b0_24), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b8_24), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50b9_24), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_50c0_24), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50c8_24), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_50d0_24), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50d8_24), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50e0_24), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50e8_24), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f0_24), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f8_24), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50f9_24), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_50fa_24), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_50fb_24), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_50fc_24), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5100_24), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5110_24), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5118_24), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5120_24), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5128_24), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5130_24), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5138_24), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5139_24), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5140_24), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5148_24), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_5150_24), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5158_24), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5160_24), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5168_24), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5170_24), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5178_24), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5179_24), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5180_24), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5188_24), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_5190_24), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_5198_24), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51a0_24), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51a8_24), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b0_24), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b8_24), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51b9_24), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_51c0_24), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51c8_24), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_51d0_24), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51d8_24), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51e0_24), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51e8_24), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f0_24), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f8_24), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51f9_24), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_51fa_24), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_51fb_24), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_51fc_24), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_52c0_24), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52c8_24), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_52d0_24), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52d8_24), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52e0_24), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52e8_24), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f0_24), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f8_24), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52f9_24), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_52fa_24), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_52fb_24), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_52fc_24), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_53c0_24), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53c8_24), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_53d0_24), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53d8_24), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53e0_24), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53e8_24), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f0_24), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f8_24), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53f9_24), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_53fa_24), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_53fb_24), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_53fc_24), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_54c0_24), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54c8_24), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_54d0_24), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54d8_24), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54e0_24), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54e8_24), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f0_24), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f8_24), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54f9_24), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_54fa_24), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_54fb_24), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_54fc_24), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_55c0_24), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55c8_24), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_55d0_24), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55d8_24), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55e0_24), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55e8_24), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f0_24), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f8_24), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55f9_24), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_55fa_24), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_55fb_24), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_55fc_24), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_56c0_24), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56c8_24), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_56d0_24), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56d8_24), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56e0_24), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56e8_24), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f0_24), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f8_24), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56f9_24), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_56fa_24), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_56fb_24), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_56fc_24), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_57c0_24), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57c8_24), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_57d0_24), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57d8_24), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57e0_24), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57e8_24), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f0_24), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f8_24), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57f9_24), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_57fa_24), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_57fb_24), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_57fc_24), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_58c0_24), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58c8_24), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_58d0_24), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58d8_24), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58e0_24), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58e8_24), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f0_24), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f8_24), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58f9_24), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_58fa_24), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_58fb_24), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_58fc_24), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_59c0_24), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59c8_24), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_59d0_24), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59d8_24), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59e0_24), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59e8_24), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f0_24), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f8_24), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59f9_24), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_59fa_24), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_59fb_24), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_59fc_24), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5ac0_24), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ac8_24), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5ad0_24), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ad8_24), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ae0_24), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ae8_24), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af0_24), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af8_24), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5af9_24), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5afa_24), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5afb_24), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5afc_24), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5bc0_24), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bc8_24), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5bd0_24), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bd8_24), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5be0_24), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5be8_24), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf0_24), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf8_24), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bf9_24), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5bfa_24), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5bfb_24), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5bfc_24), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5cc0_24), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cc8_24), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5cd0_24), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cd8_24), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ce0_24), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ce8_24), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf0_24), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf8_24), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cf9_24), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5cfa_24), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5cfb_24), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5cfc_24), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5dc0_24), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dc8_24), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5dd0_24), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dd8_24), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5de0_24), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5de8_24), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df0_24), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df8_24), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5df9_24), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5dfa_24), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5dfb_24), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5dfc_24), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5ec0_24), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ec8_24), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5ed0_24), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ed8_24), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ee0_24), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ee8_24), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef0_24), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef8_24), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ef9_24), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5efa_24), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5efb_24), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5efc_24), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5fc0_24), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fc8_24), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ (cpuop_func*)CPUFUNC(op_5fd0_24), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fd8_24), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fe0_24), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5fe8_24), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff0_24), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff8_24), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ff9_24), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ (cpuop_func*)CPUFUNC(op_5ffa_24), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5ffb_24), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_5ffc_24), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ (cpuop_func*)CPUFUNC(op_6000_24), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6001_24), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_60ff_24), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6100_24), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_6101_24), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_61ff_24), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ (cpuop_func*)CPUFUNC(op_6200_24), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6201_24), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_62ff_24), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6300_24), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6301_24), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_63ff_24), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6400_24), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6401_24), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_64ff_24), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6500_24), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6501_24), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_65ff_24), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6600_24), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6601_24), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_66ff_24), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6700_24), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6701_24), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_67ff_24), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6800_24), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6801_24), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_68ff_24), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6900_24), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6901_24), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_69ff_24), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6a00_24), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6a01_24), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6aff_24), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6b00_24), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6b01_24), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6bff_24), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6c00_24), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6c01_24), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6cff_24), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6d00_24), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6d01_24), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6dff_24), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6e00_24), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6e01_24), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6eff_24), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6f00_24), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6f01_24), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_6fff_24), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ (cpuop_func*)CPUFUNC(op_7000_24), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ (cpuop_func*)CPUFUNC(op_8000_24), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8010_24), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8018_24), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8020_24), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8028_24), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8030_24), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8038_24), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8039_24), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803a_24), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803b_24), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_803c_24), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8040_24), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8050_24), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8058_24), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8060_24), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8068_24), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8070_24), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8078_24), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8079_24), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807a_24), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807b_24), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_807c_24), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8080_24), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8090_24), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8098_24), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80a0_24), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80a8_24), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b0_24), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b8_24), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80b9_24), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80ba_24), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80bb_24), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80bc_24), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_80c0_24), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80d0_24), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80d8_24), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80e0_24), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80e8_24), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f0_24), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f8_24), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80f9_24), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fa_24), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fb_24), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_80fc_24), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ (cpuop_func*)CPUFUNC(op_8100_24), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ (cpuop_func*)CPUFUNC(op_8108_24), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ (cpuop_func*)CPUFUNC(op_8110_24), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8118_24), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8120_24), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8128_24), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8130_24), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8138_24), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8139_24), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8140_24), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+{ (cpuop_func*)CPUFUNC(op_8148_24), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+{ (cpuop_func*)CPUFUNC(op_8150_24), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8158_24), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8160_24), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8168_24), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8170_24), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8178_24), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8179_24), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8180_24), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+{ (cpuop_func*)CPUFUNC(op_8188_24), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+{ (cpuop_func*)CPUFUNC(op_8190_24), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_8198_24), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81a0_24), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81a8_24), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b0_24), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b8_24), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81b9_24), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ (cpuop_func*)CPUFUNC(op_81c0_24), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81d0_24), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81d8_24), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81e0_24), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81e8_24), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f0_24), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f8_24), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81f9_24), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fa_24), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fb_24), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_81fc_24), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ (cpuop_func*)CPUFUNC(op_9000_24), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9010_24), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9018_24), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9020_24), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9028_24), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9030_24), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9038_24), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9039_24), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903a_24), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903b_24), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_903c_24), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9040_24), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9048_24), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9050_24), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9058_24), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9060_24), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9068_24), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9070_24), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9078_24), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9079_24), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907a_24), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907b_24), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_907c_24), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9080_24), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9088_24), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9090_24), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9098_24), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90a0_24), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90a8_24), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b0_24), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b8_24), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90b9_24), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90ba_24), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90bb_24), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90bc_24), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_90c0_24), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90c8_24), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90d0_24), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90d8_24), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90e0_24), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90e8_24), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f0_24), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f8_24), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90f9_24), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fa_24), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fb_24), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_90fc_24), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_9100_24), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9108_24), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9110_24), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9118_24), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9120_24), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9128_24), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9130_24), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9138_24), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9139_24), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9140_24), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9148_24), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9150_24), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9158_24), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9160_24), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9168_24), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9170_24), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9178_24), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9179_24), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9180_24), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9188_24), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ (cpuop_func*)CPUFUNC(op_9190_24), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_9198_24), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91a0_24), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91a8_24), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b0_24), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b8_24), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91b9_24), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ (cpuop_func*)CPUFUNC(op_91c0_24), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91c8_24), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91d0_24), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91d8_24), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91e0_24), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91e8_24), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f0_24), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f8_24), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91f9_24), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fa_24), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fb_24), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_91fc_24), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ (cpuop_func*)CPUFUNC(op_b000_24), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b010_24), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b018_24), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b020_24), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b028_24), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b030_24), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b038_24), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b039_24), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03a_24), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03b_24), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b03c_24), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b040_24), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b048_24), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b050_24), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b058_24), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b060_24), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b068_24), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b070_24), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b078_24), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b079_24), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07a_24), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07b_24), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b07c_24), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b080_24), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b088_24), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b090_24), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b098_24), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0a0_24), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0a8_24), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b0_24), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b8_24), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0b9_24), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0ba_24), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0bb_24), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0bc_24), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ (cpuop_func*)CPUFUNC(op_b0c0_24), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0c8_24), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0d0_24), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0d8_24), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0e0_24), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0e8_24), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f0_24), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f8_24), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0f9_24), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fa_24), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fb_24), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b0fc_24), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b100_24), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b108_24), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b110_24), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b118_24), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b120_24), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b128_24), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b130_24), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b138_24), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b139_24), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b140_24), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b148_24), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b150_24), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b158_24), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b160_24), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b168_24), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b170_24), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b178_24), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b179_24), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b180_24), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b188_24), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ (cpuop_func*)CPUFUNC(op_b190_24), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b198_24), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1a0_24), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1a8_24), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b0_24), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b8_24), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1b9_24), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ (cpuop_func*)CPUFUNC(op_b1c0_24), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1c8_24), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1d0_24), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1d8_24), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1e0_24), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1e8_24), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f0_24), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f8_24), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1f9_24), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fa_24), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fb_24), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_b1fc_24), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ (cpuop_func*)CPUFUNC(op_c000_24), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c010_24), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c018_24), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c020_24), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c028_24), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c030_24), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c038_24), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c039_24), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03a_24), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03b_24), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c03c_24), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c040_24), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c050_24), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c058_24), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c060_24), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c068_24), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c070_24), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c078_24), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c079_24), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07a_24), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07b_24), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c07c_24), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c080_24), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c090_24), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c098_24), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0a0_24), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0a8_24), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b0_24), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b8_24), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0b9_24), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0ba_24), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0bb_24), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0bc_24), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c0c0_24), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0d0_24), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0d8_24), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0e0_24), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0e8_24), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f0_24), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f8_24), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0f9_24), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fa_24), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fb_24), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c0fc_24), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ (cpuop_func*)CPUFUNC(op_c100_24), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ (cpuop_func*)CPUFUNC(op_c108_24), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ (cpuop_func*)CPUFUNC(op_c110_24), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c118_24), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c120_24), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c128_24), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c130_24), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c138_24), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c139_24), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c140_24), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c148_24), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c150_24), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c158_24), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c160_24), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c168_24), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c170_24), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c178_24), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c179_24), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c188_24), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ (cpuop_func*)CPUFUNC(op_c190_24), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c198_24), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1a0_24), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1a8_24), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b0_24), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b8_24), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1b9_24), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ (cpuop_func*)CPUFUNC(op_c1c0_24), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1d0_24), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1d8_24), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1e0_24), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1e8_24), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f0_24), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f8_24), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1f9_24), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fa_24), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fb_24), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_c1fc_24), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ (cpuop_func*)CPUFUNC(op_d000_24), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d010_24), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d018_24), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d020_24), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d028_24), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d030_24), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d038_24), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d039_24), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03a_24), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03b_24), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d03c_24), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d040_24), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d048_24), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d050_24), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d058_24), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d060_24), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d068_24), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d070_24), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d078_24), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d079_24), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07a_24), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07b_24), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d07c_24), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d080_24), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d088_24), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d090_24), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d098_24), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0a0_24), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0a8_24), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b0_24), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b8_24), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0b9_24), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0ba_24), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0bb_24), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0bc_24), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d0c0_24), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0c8_24), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0d0_24), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0d8_24), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0e0_24), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0e8_24), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f0_24), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f8_24), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0f9_24), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fa_24), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fb_24), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d0fc_24), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d100_24), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d108_24), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d110_24), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d118_24), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d120_24), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d128_24), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d130_24), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d138_24), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d139_24), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d140_24), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d148_24), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d150_24), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d158_24), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d160_24), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d168_24), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d170_24), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d178_24), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d179_24), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d180_24), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d188_24), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ (cpuop_func*)CPUFUNC(op_d190_24), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d198_24), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1a0_24), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1a8_24), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b0_24), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b8_24), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1b9_24), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ (cpuop_func*)CPUFUNC(op_d1c0_24), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1c8_24), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1d0_24), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1d8_24), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1e0_24), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1e8_24), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f0_24), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f8_24), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1f9_24), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fa_24), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fb_24), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_d1fc_24), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ (cpuop_func*)CPUFUNC(op_e000_24), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e008_24), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e010_24), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e018_24), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e020_24), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e028_24), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e030_24), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e038_24), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e040_24), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e048_24), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e050_24), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e058_24), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e060_24), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e068_24), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e070_24), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e078_24), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e080_24), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e088_24), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e090_24), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e098_24), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e0a0_24), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ (cpuop_func*)CPUFUNC(op_e0a8_24), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ (cpuop_func*)CPUFUNC(op_e0b0_24), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ (cpuop_func*)CPUFUNC(op_e0b8_24), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ (cpuop_func*)CPUFUNC(op_e0d0_24), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0d8_24), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0e0_24), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0e8_24), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f0_24), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f8_24), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e0f9_24), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ (cpuop_func*)CPUFUNC(op_e100_24), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e108_24), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e110_24), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e118_24), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e120_24), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e128_24), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e130_24), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e138_24), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e140_24), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e148_24), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e150_24), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e158_24), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e160_24), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e168_24), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e170_24), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e178_24), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e180_24), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e188_24), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e190_24), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e198_24), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e1a0_24), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ (cpuop_func*)CPUFUNC(op_e1a8_24), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ (cpuop_func*)CPUFUNC(op_e1b0_24), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ (cpuop_func*)CPUFUNC(op_e1b8_24), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ (cpuop_func*)CPUFUNC(op_e1d0_24), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1d8_24), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1e0_24), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1e8_24), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f0_24), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f8_24), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e1f9_24), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ (cpuop_func*)CPUFUNC(op_e2d0_24), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2d8_24), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2e0_24), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2e8_24), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f0_24), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f8_24), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e2f9_24), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ (cpuop_func*)CPUFUNC(op_e3d0_24), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3d8_24), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3e0_24), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3e8_24), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f0_24), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f8_24), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e3f9_24), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ (cpuop_func*)CPUFUNC(op_e4d0_24), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4d8_24), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4e0_24), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4e8_24), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f0_24), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f8_24), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e4f9_24), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ (cpuop_func*)CPUFUNC(op_e5d0_24), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5d8_24), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5e0_24), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5e8_24), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f0_24), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f8_24), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e5f9_24), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ (cpuop_func*)CPUFUNC(op_e6d0_24), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6d8_24), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6e0_24), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6e8_24), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f0_24), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f8_24), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e6f9_24), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ (cpuop_func*)CPUFUNC(op_e7d0_24), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7d8_24), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7e0_24), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7e8_24), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f0_24), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f8_24), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e7f9_24), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ (cpuop_func*)CPUFUNC(op_e8c0_24), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+{ (cpuop_func*)CPUFUNC(op_e8d0_24), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+{ (cpuop_func*)CPUFUNC(op_e8e8_24), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+{ (cpuop_func*)CPUFUNC(op_e8f0_24), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+{ (cpuop_func*)CPUFUNC(op_e8f8_24), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+{ (cpuop_func*)CPUFUNC(op_e8f9_24), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+{ (cpuop_func*)CPUFUNC(op_e8fa_24), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+{ (cpuop_func*)CPUFUNC(op_e8fb_24), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+{ (cpuop_func*)CPUFUNC(op_e9c0_24), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+{ (cpuop_func*)CPUFUNC(op_e9d0_24), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+{ (cpuop_func*)CPUFUNC(op_e9e8_24), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ (cpuop_func*)CPUFUNC(op_e9f0_24), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+{ (cpuop_func*)CPUFUNC(op_e9f8_24), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ (cpuop_func*)CPUFUNC(op_e9f9_24), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+{ (cpuop_func*)CPUFUNC(op_e9fa_24), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ (cpuop_func*)CPUFUNC(op_e9fb_24), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+{ (cpuop_func*)CPUFUNC(op_eac0_24), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+{ (cpuop_func*)CPUFUNC(op_ead0_24), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+{ (cpuop_func*)CPUFUNC(op_eae8_24), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+{ (cpuop_func*)CPUFUNC(op_eaf0_24), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+{ (cpuop_func*)CPUFUNC(op_eaf8_24), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+{ (cpuop_func*)CPUFUNC(op_eaf9_24), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+{ (cpuop_func*)CPUFUNC(op_ebc0_24), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+{ (cpuop_func*)CPUFUNC(op_ebd0_24), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+{ (cpuop_func*)CPUFUNC(op_ebe8_24), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ (cpuop_func*)CPUFUNC(op_ebf0_24), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+{ (cpuop_func*)CPUFUNC(op_ebf8_24), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ (cpuop_func*)CPUFUNC(op_ebf9_24), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+{ (cpuop_func*)CPUFUNC(op_ebfa_24), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ (cpuop_func*)CPUFUNC(op_ebfb_24), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+{ (cpuop_func*)CPUFUNC(op_ecc0_24), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+{ (cpuop_func*)CPUFUNC(op_ecd0_24), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+{ (cpuop_func*)CPUFUNC(op_ece8_24), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+{ (cpuop_func*)CPUFUNC(op_ecf0_24), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+{ (cpuop_func*)CPUFUNC(op_ecf8_24), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+{ (cpuop_func*)CPUFUNC(op_ecf9_24), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+{ (cpuop_func*)CPUFUNC(op_edc0_24), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+{ (cpuop_func*)CPUFUNC(op_edd0_24), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+{ (cpuop_func*)CPUFUNC(op_ede8_24), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ (cpuop_func*)CPUFUNC(op_edf0_24), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+{ (cpuop_func*)CPUFUNC(op_edf8_24), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ (cpuop_func*)CPUFUNC(op_edf9_24), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+{ (cpuop_func*)CPUFUNC(op_edfa_24), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ (cpuop_func*)CPUFUNC(op_edfb_24), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+{ (cpuop_func*)CPUFUNC(op_eec0_24), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+{ (cpuop_func*)CPUFUNC(op_eed0_24), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+{ (cpuop_func*)CPUFUNC(op_eee8_24), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+{ (cpuop_func*)CPUFUNC(op_eef0_24), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+{ (cpuop_func*)CPUFUNC(op_eef8_24), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+{ (cpuop_func*)CPUFUNC(op_eef9_24), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+{ (cpuop_func*)CPUFUNC(op_efc0_24), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+{ (cpuop_func*)CPUFUNC(op_efd0_24), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+{ (cpuop_func*)CPUFUNC(op_efe8_24), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+{ (cpuop_func*)CPUFUNC(op_eff0_24), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+{ (cpuop_func*)CPUFUNC(op_eff8_24), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+{ (cpuop_func*)CPUFUNC(op_eff9_24), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+{ (cpuop_func*)CPUFUNC(op_f000_24), 0xf000, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ (cpuop_func*)CPUFUNC(op_f008_24), 0xf008, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ (cpuop_func*)CPUFUNC(op_f010_24), 0xf010, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ (cpuop_func*)CPUFUNC(op_f018_24), 0xf018, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ (cpuop_func*)CPUFUNC(op_f020_24), 0xf020, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ (cpuop_func*)CPUFUNC(op_f028_24), 0xf028, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ (cpuop_func*)CPUFUNC(op_f030_24), 0xf030, -1, { -3, 0 }, 0 }, /* MMUOP030 */
+{ (cpuop_func*)CPUFUNC(op_f038_24), 0xf038, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ (cpuop_func*)CPUFUNC(op_f039_24), 0xf039, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ (cpuop_func*)CPUFUNC(op_f200_24), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+{ (cpuop_func*)CPUFUNC(op_f208_24), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+{ (cpuop_func*)CPUFUNC(op_f210_24), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+{ (cpuop_func*)CPUFUNC(op_f218_24), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+{ (cpuop_func*)CPUFUNC(op_f220_24), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+{ (cpuop_func*)CPUFUNC(op_f228_24), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+{ (cpuop_func*)CPUFUNC(op_f230_24), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+{ (cpuop_func*)CPUFUNC(op_f238_24), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+{ (cpuop_func*)CPUFUNC(op_f239_24), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+{ (cpuop_func*)CPUFUNC(op_f23a_24), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+{ (cpuop_func*)CPUFUNC(op_f23b_24), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+{ (cpuop_func*)CPUFUNC(op_f23c_24), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+{ (cpuop_func*)CPUFUNC(op_f240_24), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+{ (cpuop_func*)CPUFUNC(op_f248_24), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+{ (cpuop_func*)CPUFUNC(op_f250_24), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+{ (cpuop_func*)CPUFUNC(op_f258_24), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+{ (cpuop_func*)CPUFUNC(op_f260_24), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+{ (cpuop_func*)CPUFUNC(op_f268_24), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+{ (cpuop_func*)CPUFUNC(op_f270_24), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+{ (cpuop_func*)CPUFUNC(op_f278_24), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+{ (cpuop_func*)CPUFUNC(op_f279_24), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+{ (cpuop_func*)CPUFUNC(op_f27a_24), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ (cpuop_func*)CPUFUNC(op_f27b_24), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ (cpuop_func*)CPUFUNC(op_f27c_24), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ (cpuop_func*)CPUFUNC(op_f280_24), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+{ (cpuop_func*)CPUFUNC(op_f2c0_24), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+{ (cpuop_func*)CPUFUNC(op_f310_24), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ (cpuop_func*)CPUFUNC(op_f320_24), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ (cpuop_func*)CPUFUNC(op_f328_24), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ (cpuop_func*)CPUFUNC(op_f330_24), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ (cpuop_func*)CPUFUNC(op_f338_24), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ (cpuop_func*)CPUFUNC(op_f339_24), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ (cpuop_func*)CPUFUNC(op_f350_24), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ (cpuop_func*)CPUFUNC(op_f358_24), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ (cpuop_func*)CPUFUNC(op_f368_24), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ (cpuop_func*)CPUFUNC(op_f370_24), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ (cpuop_func*)CPUFUNC(op_f378_24), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ (cpuop_func*)CPUFUNC(op_f379_24), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ (cpuop_func*)CPUFUNC(op_f37a_24), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ (cpuop_func*)CPUFUNC(op_f37b_24), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ (cpuop_func*)CPUFUNC(op_f408_24), 0xf408, -1, { 0, 0 }, 0 }, /* CINVL */
+{ (cpuop_func*)CPUFUNC(op_f410_24), 0xf410, -1, { 0, 0 }, 0 }, /* CINVP */
+{ (cpuop_func*)CPUFUNC(op_f418_24), 0xf418, -1, { 0, 0 }, 0 }, /* CINVA */
+{ (cpuop_func*)CPUFUNC(op_f419_24), 0xf419, -1, { 0, 0 }, 0 }, /* CINVA */
+{ (cpuop_func*)CPUFUNC(op_f41a_24), 0xf41a, -1, { 0, 0 }, 0 }, /* CINVA */
+{ (cpuop_func*)CPUFUNC(op_f41b_24), 0xf41b, -1, { 0, 0 }, 0 }, /* CINVA */
+{ (cpuop_func*)CPUFUNC(op_f41c_24), 0xf41c, -1, { 0, 0 }, 0 }, /* CINVA */
+{ (cpuop_func*)CPUFUNC(op_f41d_24), 0xf41d, -1, { 0, 0 }, 0 }, /* CINVA */
+{ (cpuop_func*)CPUFUNC(op_f41e_24), 0xf41e, -1, { 0, 0 }, 0 }, /* CINVA */
+{ (cpuop_func*)CPUFUNC(op_f41f_24), 0xf41f, -1, { 0, 0 }, 0 }, /* CINVA */
+{ (cpuop_func*)CPUFUNC(op_f428_24), 0xf428, -1, { 0, 0 }, 0 }, /* CPUSHL */
+{ (cpuop_func*)CPUFUNC(op_f430_24), 0xf430, -1, { 0, 0 }, 0 }, /* CPUSHP */
+{ (cpuop_func*)CPUFUNC(op_f438_24), 0xf438, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ (cpuop_func*)CPUFUNC(op_f439_24), 0xf439, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ (cpuop_func*)CPUFUNC(op_f43a_24), 0xf43a, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ (cpuop_func*)CPUFUNC(op_f43b_24), 0xf43b, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ (cpuop_func*)CPUFUNC(op_f43c_24), 0xf43c, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ (cpuop_func*)CPUFUNC(op_f43d_24), 0xf43d, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ (cpuop_func*)CPUFUNC(op_f43e_24), 0xf43e, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ (cpuop_func*)CPUFUNC(op_f43f_24), 0xf43f, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ (cpuop_func*)CPUFUNC(op_f500_24), 0xf500, -1, { 0, 0 }, 0 }, /* PFLUSHN */
+{ (cpuop_func*)CPUFUNC(op_f508_24), 0xf508, -1, { 0, 0 }, 0 }, /* PFLUSH */
+{ (cpuop_func*)CPUFUNC(op_f510_24), 0xf510, -1, { 0, 0 }, 0 }, /* PFLUSHAN */
+{ (cpuop_func*)CPUFUNC(op_f518_24), 0xf518, -1, { 0, 0 }, 0 }, /* PFLUSHA */
+{ (cpuop_func*)CPUFUNC(op_f548_24), 0xf548, -1, { 0, 0 }, 0 }, /* PTESTW */
+{ (cpuop_func*)CPUFUNC(op_f568_24), 0xf568, -1, { 0, 0 }, 0 }, /* PTESTR */
+{ (cpuop_func*)CPUFUNC(op_f600_24), 0xf600, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ (cpuop_func*)CPUFUNC(op_f608_24), 0xf608, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ (cpuop_func*)CPUFUNC(op_f610_24), 0xf610, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ (cpuop_func*)CPUFUNC(op_f618_24), 0xf618, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ (cpuop_func*)CPUFUNC(op_f620_24), 0xf620, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#ifdef CPUEMU_31
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_31)[] = {
+{ CPUFUNC(op_0000_31), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_31), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_31), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_31), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_31), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_31), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_31), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_31), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_31), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_31), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_31), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_31), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_31), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_31), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_31), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_31), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_31), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_31), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_31), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_31), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_31), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_31), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_31), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_31), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_31), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_31), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00d0_31), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00e8_31), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f0_31), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f8_31), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f9_31), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00fa_31), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00fb_31), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0100_31), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_31), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_31), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_31), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_31), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_31), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_31), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_31), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_31), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_31), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_31), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_31), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_31), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_31), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_31), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_31), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_31), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_31), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_31), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_31), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_31), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_31), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_31), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_31), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_31), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_31), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_31), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_31), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_31), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_31), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_31), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_31), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_31), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_31), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_31), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_31), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_31), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_31), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_31), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_31), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_31), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_31), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_31), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_31), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_31), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_31), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_31), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_31), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_31), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_31), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_31), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_31), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_31), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_31), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_31), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_31), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_31), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_31), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_31), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_31), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_31), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_31), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_31), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_31), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_31), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02d0_31), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02e8_31), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f0_31), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f8_31), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f9_31), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02fa_31), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02fb_31), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0400_31), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_31), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_31), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_31), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_31), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_31), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_31), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_31), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_31), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_31), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_31), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_31), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_31), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_31), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_31), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_31), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_31), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_31), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_31), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_31), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_31), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_31), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_31), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_31), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04d0_31), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04e8_31), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f0_31), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f8_31), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f9_31), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04fa_31), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04fb_31), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0600_31), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_31), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_31), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_31), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_31), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_31), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_31), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_31), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_31), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_31), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_31), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_31), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_31), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_31), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_31), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_31), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_31), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_31), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_31), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_31), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_31), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_31), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_31), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_31), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06c0_31), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06c8_31), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06d0_31), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06e8_31), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f0_31), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f8_31), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f9_31), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06fa_31), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06fb_31), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+{ CPUFUNC(op_0800_31), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_31), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_31), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_31), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_31), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_31), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_31), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_31), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_31), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_31), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_31), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_31), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_31), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_31), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_31), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_31), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_31), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_31), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_31), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_31), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_31), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_31), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_31), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_31), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_31), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_31), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_31), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_31), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_31), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_31), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_31), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_31), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_31), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_31), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_31), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_31), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_31), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_31), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_31), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_31), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_31), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_31), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_31), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_31), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_31), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_31), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_31), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_31), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_31), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_31), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_31), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_31), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_31), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_31), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_31), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_31), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_31), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_31), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_31), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_31), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ad0_31), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ad8_31), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ae0_31), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ae8_31), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af0_31), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af8_31), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af9_31), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+{ CPUFUNC(op_0c00_31), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_31), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_31), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_31), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_31), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_31), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_31), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_31), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c3a_31), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c3b_31), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ CPUFUNC(op_0c40_31), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_31), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_31), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_31), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_31), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_31), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_31), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_31), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c7a_31), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c7b_31), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ CPUFUNC(op_0c80_31), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_31), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_31), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_31), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_31), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_31), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_31), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_31), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cba_31), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cbb_31), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cd0_31), 0x0cd0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cd8_31), 0x0cd8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ce0_31), 0x0ce0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ce8_31), 0x0ce8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf0_31), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf8_31), 0x0cf8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf9_31), 0x0cf9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cfc_31), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e10_31), 0x0e10, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e18_31), 0x0e18, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e20_31), 0x0e20, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e28_31), 0x0e28, 12, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e30_31), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e38_31), 0x0e38, 12, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e39_31), 0x0e39, 16, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e50_31), 0x0e50, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e58_31), 0x0e58, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e60_31), 0x0e60, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e68_31), 0x0e68, 12, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e70_31), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e78_31), 0x0e78, 12, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e79_31), 0x0e79, 16, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e90_31), 0x0e90, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e98_31), 0x0e98, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ea0_31), 0x0ea0, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ea8_31), 0x0ea8, 12, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb0_31), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb8_31), 0x0eb8, 12, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb9_31), 0x0eb9, 16, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ed0_31), 0x0ed0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ed8_31), 0x0ed8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ee0_31), 0x0ee0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ee8_31), 0x0ee8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef0_31), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef8_31), 0x0ef8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef9_31), 0x0ef9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0efc_31), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+{ CPUFUNC(op_1000_31), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_31), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_31), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_31), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_31), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_31), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_31), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_31), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_31), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_31), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_31), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_31), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_31), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_31), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_31), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_31), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_31), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_31), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_31), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_31), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_31), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_31), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_31), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_31), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_31), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_31), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_31), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_31), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_31), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_31), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_31), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_31), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_31), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_31), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_31), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_31), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_31), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_31), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_31), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_31), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_31), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_31), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_31), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_31), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_31), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_31), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_31), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_31), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_31), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_31), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_31), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_31), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_31), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_31), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_31), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_31), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_31), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_31), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_31), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_31), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_31), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_31), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_31), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_31), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_31), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_31), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_31), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_31), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_31), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_31), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_31), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_31), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_31), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_31), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_31), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_31), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_31), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_31), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_31), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_31), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_31), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_31), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_31), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_31), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_31), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_31), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_31), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_31), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_31), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_31), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_31), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_31), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_31), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_31), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_31), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_31), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_31), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_31), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_31), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_31), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_31), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_31), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_31), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_31), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_31), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_31), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_31), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_31), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_31), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_31), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_31), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_31), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_31), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_31), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_31), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_31), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_31), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_31), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_31), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_31), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_31), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_31), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_31), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_31), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_31), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_31), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_31), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_31), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_31), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_31), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_31), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_31), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_31), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_31), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_31), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_31), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_31), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_31), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_31), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_31), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_31), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_31), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_31), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_31), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_31), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_31), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_31), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_31), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_31), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_31), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_31), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_31), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_31), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_31), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_31), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_31), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_31), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_31), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_31), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_31), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_31), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_31), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_31), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_31), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_31), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_31), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_31), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_31), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_31), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_31), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_31), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_31), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_31), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_31), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_31), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_31), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_31), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_31), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_31), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_31), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_31), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_31), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_31), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_31), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_31), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_31), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_31), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_31), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_31), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_31), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_31), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_31), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_31), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_31), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_31), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_31), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_31), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_31), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_31), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_31), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_31), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_31), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_31), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_31), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_31), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_31), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_31), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_31), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_31), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_31), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_31), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_31), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_31), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_31), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_31), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_31), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_31), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_31), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_31), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_31), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_31), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_31), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_31), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_31), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_31), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_31), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_31), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_31), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_31), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_31), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_31), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_31), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_31), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_31), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_31), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_31), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_31), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_31), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_31), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_31), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_31), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_31), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_31), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_31), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_31), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_31), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_31), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_31), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_31), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_31), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_31), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_31), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_31), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_31), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_31), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_31), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_31), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_31), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_31), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_31), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_31), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_31), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_31), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_31), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_31), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_31), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_31), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_31), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_31), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_31), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_31), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_31), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_31), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_31), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_31), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_31), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_31), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_31), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_31), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_31), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_31), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_31), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_31), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_31), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_31), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_31), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_31), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_31), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_31), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_31), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_31), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_31), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_31), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_31), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_31), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_31), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_31), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_31), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_31), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_31), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_31), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_31), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_31), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_31), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_31), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_31), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_31), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_31), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_31), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_31), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_31), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_31), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_31), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_31), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_31), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_31), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_31), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_31), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_31), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_31), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_31), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_31), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_31), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_31), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_31), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_31), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_31), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_31), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_31), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_31), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_31), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_31), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_31), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_31), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_31), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_31), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4100_31), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4110_31), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4118_31), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4120_31), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4128_31), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4130_31), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4138_31), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4139_31), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413a_31), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413b_31), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413c_31), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+{ CPUFUNC(op_4180_31), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_31), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_31), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_31), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_31), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_31), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_31), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_31), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_31), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_31), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_31), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_31), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_31), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_31), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_31), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_31), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_31), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_31), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_31), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_31), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_31), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_31), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_31), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_31), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_31), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_31), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_31), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_31), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_31), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_31), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_31), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_31), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_31), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_31), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_31), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_31), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_31), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_31), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_31), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_31), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_31), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_31), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42c0_31), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d0_31), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d8_31), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e0_31), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e8_31), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f0_31), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f8_31), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f9_31), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+{ CPUFUNC(op_4400_31), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_31), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_31), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_31), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_31), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_31), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_31), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_31), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_31), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_31), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_31), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_31), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_31), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_31), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_31), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_31), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_31), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_31), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_31), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_31), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_31), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_31), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_31), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_31), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_31), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_31), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_31), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_31), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_31), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_31), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_31), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_31), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_31), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_31), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_31), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_31), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_31), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_31), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_31), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_31), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_31), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_31), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_31), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_31), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_31), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_31), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_31), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_31), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_31), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_31), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_31), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_31), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_31), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_31), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_31), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_31), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_31), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_31), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_31), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_31), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_31), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_31), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_31), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_31), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_31), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_31), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_31), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_31), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_31), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_31), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_31), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4808_31), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#endif
+{ CPUFUNC(op_4810_31), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_31), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_31), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_31), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_31), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_31), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_31), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_31), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4848_31), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+#endif
+{ CPUFUNC(op_4850_31), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_31), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_31), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_31), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_31), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_31), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_31), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_31), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_31), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_31), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_31), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_31), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_31), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_31), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_31), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_31), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_31), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_31), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_31), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_31), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_31), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_49c0_31), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+#endif
+{ CPUFUNC(op_4a00_31), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_31), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_31), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_31), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_31), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_31), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_31), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_31), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3a_31), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3b_31), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3c_31), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a40_31), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a48_31), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a50_31), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_31), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_31), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_31), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_31), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_31), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_31), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7a_31), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7b_31), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7c_31), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a80_31), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a88_31), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a90_31), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_31), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_31), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_31), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_31), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_31), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_31), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4aba_31), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4abb_31), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4abc_31), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4ac0_31), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_31), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_31), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_31), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_31), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_31), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_31), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_31), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c00_31), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c10_31), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c18_31), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c20_31), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c28_31), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c30_31), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c38_31), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c39_31), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3a_31), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3b_31), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3c_31), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c40_31), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c50_31), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c58_31), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c60_31), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c68_31), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c70_31), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c78_31), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c79_31), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7a_31), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7b_31), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7c_31), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+{ CPUFUNC(op_4c90_31), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_31), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_31), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_31), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_31), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_31), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_31), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_31), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_31), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_31), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_31), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_31), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_31), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_31), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_31), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_31), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_31), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_31), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_31), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_31), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_31), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_31), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_31), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_31), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_31), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e74_31), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+#endif
+{ CPUFUNC(op_4e75_31), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_31), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_31), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7a_31), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7b_31), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+#endif
+{ CPUFUNC(op_4e90_31), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_31), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_31), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_31), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_31), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_31), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_31), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_31), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_31), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_31), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_31), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_31), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_31), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_31), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_31), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_31), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_31), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_31), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_31), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_31), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_31), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_31), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_31), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_31), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_31), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_31), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_31), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_31), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_31), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_31), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_31), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_31), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_31), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_31), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_31), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_31), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_31), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_31), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_31), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_31), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_31), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_31), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_31), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_31), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_31), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_31), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_31), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_31), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_31), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fa_31), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fb_31), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fc_31), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5100_31), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_31), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_31), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_31), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_31), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_31), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_31), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_31), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_31), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_31), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_31), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_31), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_31), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_31), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_31), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_31), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_31), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_31), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_31), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_31), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_31), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_31), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_31), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_31), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_31), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_31), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_31), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_31), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_31), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_31), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_31), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_31), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_31), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_31), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_31), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fa_31), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fb_31), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fc_31), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_52c0_31), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_31), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_31), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_31), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_31), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_31), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_31), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_31), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_31), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fa_31), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fb_31), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fc_31), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_53c0_31), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_31), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_31), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_31), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_31), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_31), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_31), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_31), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_31), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fa_31), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fb_31), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fc_31), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_54c0_31), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_31), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_31), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_31), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_31), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_31), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_31), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_31), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_31), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fa_31), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fb_31), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fc_31), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_55c0_31), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_31), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_31), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_31), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_31), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_31), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_31), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_31), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_31), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fa_31), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fb_31), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fc_31), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_56c0_31), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_31), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_31), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_31), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_31), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_31), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_31), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_31), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_31), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fa_31), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fb_31), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fc_31), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_57c0_31), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_31), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_31), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_31), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_31), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_31), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_31), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_31), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_31), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fa_31), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fb_31), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fc_31), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_58c0_31), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_31), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_31), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_31), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_31), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_31), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_31), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_31), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_31), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fa_31), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fb_31), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fc_31), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_59c0_31), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_31), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_31), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_31), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_31), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_31), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_31), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_31), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_31), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fa_31), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fb_31), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fc_31), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5ac0_31), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_31), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_31), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_31), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_31), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_31), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_31), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_31), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_31), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afa_31), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afb_31), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afc_31), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5bc0_31), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_31), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_31), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_31), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_31), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_31), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_31), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_31), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_31), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfa_31), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfb_31), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfc_31), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5cc0_31), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_31), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_31), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_31), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_31), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_31), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_31), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_31), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_31), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfa_31), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfb_31), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfc_31), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5dc0_31), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_31), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_31), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_31), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_31), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_31), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_31), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_31), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_31), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfa_31), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfb_31), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfc_31), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5ec0_31), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_31), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_31), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_31), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_31), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_31), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_31), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_31), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_31), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efa_31), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efb_31), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efc_31), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5fc0_31), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_31), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_31), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_31), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_31), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_31), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_31), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_31), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_31), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffa_31), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffb_31), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffc_31), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_6000_31), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_31), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_31), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6100_31), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_31), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_31), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_31), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_31), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_31), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6300_31), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_31), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_31), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6400_31), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_31), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_31), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6500_31), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_31), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_31), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6600_31), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_31), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_31), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6700_31), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_31), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_31), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6800_31), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_31), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_31), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6900_31), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_31), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_31), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a00_31), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_31), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_31), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b00_31), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_31), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_31), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c00_31), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_31), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_31), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d00_31), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_31), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_31), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e00_31), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_31), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_31), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f00_31), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_31), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_31), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_7000_31), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_31), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_31), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_31), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_31), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_31), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_31), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_31), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_31), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_31), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_31), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_31), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_31), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_31), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_31), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_31), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_31), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_31), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_31), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_31), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_31), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_31), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_31), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_31), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_31), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_31), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_31), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_31), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_31), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_31), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_31), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_31), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_31), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_31), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_31), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_31), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_31), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_31), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_31), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_31), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_31), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_31), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_31), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_31), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_31), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_31), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_31), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_31), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_31), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_31), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_31), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_31), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_31), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_31), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8140_31), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8148_31), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+{ CPUFUNC(op_8150_31), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_31), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_31), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_31), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_31), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_31), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_31), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8180_31), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8188_31), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+{ CPUFUNC(op_8190_31), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_31), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_31), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_31), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_31), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_31), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_31), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_31), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_31), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_31), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_31), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_31), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_31), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_31), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_31), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_31), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_31), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_31), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_31), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_31), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_31), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_31), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_31), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_31), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_31), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_31), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_31), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_31), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_31), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_31), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_31), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_31), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_31), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_31), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_31), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_31), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_31), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_31), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_31), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_31), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_31), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_31), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_31), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_31), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_31), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_31), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_31), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_31), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_31), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_31), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_31), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_31), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_31), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_31), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_31), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_31), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_31), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_31), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_31), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_31), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_31), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_31), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_31), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_31), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_31), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_31), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_31), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_31), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_31), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_31), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_31), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_31), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_31), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_31), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_31), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_31), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_31), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_31), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_31), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_31), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_31), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_31), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_31), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_31), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_31), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_31), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_31), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_31), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_31), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_31), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_31), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_31), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_31), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_31), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_31), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_31), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_31), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_31), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_31), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_31), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_31), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_31), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_31), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_31), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_31), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_31), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_31), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_31), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_31), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_31), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_31), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_31), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_31), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_31), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_31), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_31), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_31), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_31), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_31), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_31), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_31), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_31), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_31), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_31), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_31), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_31), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_31), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_31), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_31), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_31), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_31), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_31), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_31), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_31), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_31), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_31), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_31), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_31), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_31), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_31), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_31), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_31), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_31), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_31), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_31), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_31), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_31), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_31), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_31), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_31), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_31), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_31), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_31), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_31), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_31), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_31), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_31), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_31), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_31), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_31), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_31), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_31), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_31), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_31), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_31), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_31), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_31), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_31), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_31), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_31), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_31), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_31), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_31), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_31), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_31), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_31), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_31), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_31), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_31), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_31), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_31), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_31), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_31), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_31), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_31), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_31), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_31), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_31), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_31), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_31), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_31), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_31), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_31), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_31), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_31), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_31), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_31), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_31), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_31), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_31), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_31), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_31), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_31), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_31), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_31), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_31), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_31), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_31), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_31), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_31), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_31), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_31), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_31), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_31), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_31), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_31), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_31), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_31), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_31), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_31), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_31), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_31), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_31), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_31), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_31), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_31), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_31), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_31), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_31), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_31), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_31), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_31), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_31), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_31), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_31), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_31), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_31), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_31), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_31), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_31), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_31), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_31), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_31), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_31), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_31), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_31), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_31), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_31), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_31), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_31), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_31), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_31), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_31), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_31), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_31), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_31), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_31), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_31), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_31), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_31), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_31), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_31), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_31), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_31), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_31), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_31), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_31), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_31), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_31), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_31), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_31), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_31), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_31), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_31), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_31), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_31), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_31), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_31), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_31), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_31), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_31), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_31), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_31), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_31), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_31), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_31), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_31), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_31), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_31), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_31), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_31), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_31), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_31), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_31), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_31), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_31), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_31), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_31), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_31), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_31), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_31), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_31), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_31), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_31), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_31), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_31), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_31), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_31), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_31), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_31), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_31), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_31), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_31), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_31), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_31), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_31), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_31), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_31), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_31), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_31), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_31), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_31), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_31), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_31), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_31), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_31), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_31), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_31), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_31), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_31), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_31), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_31), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_31), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_31), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_31), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_31), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_31), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_31), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_31), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_31), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_31), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_31), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_31), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_31), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_31), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_31), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_31), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_31), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_31), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_31), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_31), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_31), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_31), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_31), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_31), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_31), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_31), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_31), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_31), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_31), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_31), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_31), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_31), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_31), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_31), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_31), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_31), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_31), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_31), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_31), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_31), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_31), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_31), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_31), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_31), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_31), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_31), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_31), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_31), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_31), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_31), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_31), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_31), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_31), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_31), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_31), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_31), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_31), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_31), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_31), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_31), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_31), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_31), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_31), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_31), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_31), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_31), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_31), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_31), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_31), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_31), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_31), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_31), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_31), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_31), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_31), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_31), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_31), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_31), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_31), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_31), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_31), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_31), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_31), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_31), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_31), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_31), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_31), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_31), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_31), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_31), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_31), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_31), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_31), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_31), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_31), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_31), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_31), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_31), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_31), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_31), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_31), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_31), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_31), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_31), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_31), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_31), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_31), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_31), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_31), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_31), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_31), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_31), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_31), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_31), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_31), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_31), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_31), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_31), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_31), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_31), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_31), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_31), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_31), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_31), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_31), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_31), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_31), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_31), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_31), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_31), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8c0_31), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8d0_31), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8e8_31), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f0_31), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f8_31), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f9_31), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8fa_31), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8fb_31), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9c0_31), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9d0_31), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9e8_31), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f0_31), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f8_31), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f9_31), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9fa_31), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9fb_31), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eac0_31), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ead0_31), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eae8_31), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf0_31), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf8_31), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf9_31), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebc0_31), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebd0_31), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebe8_31), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf0_31), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf8_31), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf9_31), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebfa_31), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebfb_31), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecc0_31), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecd0_31), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ece8_31), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf0_31), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf8_31), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf9_31), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edc0_31), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edd0_31), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ede8_31), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf0_31), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf8_31), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf9_31), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edfa_31), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edfb_31), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eec0_31), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eed0_31), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eee8_31), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef0_31), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef8_31), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef9_31), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efc0_31), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efd0_31), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efe8_31), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff0_31), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff8_31), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff9_31), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f000_31), 0xf000, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f008_31), 0xf008, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f010_31), 0xf010, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f018_31), 0xf018, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f020_31), 0xf020, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f028_31), 0xf028, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f030_31), 0xf030, -1, { -3, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f038_31), 0xf038, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f039_31), 0xf039, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f200_31), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f208_31), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f210_31), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f218_31), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f220_31), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f228_31), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f230_31), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f238_31), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f239_31), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23a_31), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23b_31), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23c_31), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f240_31), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f248_31), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f250_31), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f258_31), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f260_31), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f268_31), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f270_31), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f278_31), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f279_31), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27a_31), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27b_31), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27c_31), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f280_31), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f2c0_31), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f310_31), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f320_31), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f328_31), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f330_31), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f338_31), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f339_31), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f350_31), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f358_31), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f368_31), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f370_31), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f378_31), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f379_31), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f37a_31), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f37b_31), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f408_31), 0xf408, -1, { 0, 0 }, 0 }, /* CINVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f410_31), 0xf410, -1, { 0, 0 }, 0 }, /* CINVP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f418_31), 0xf418, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f419_31), 0xf419, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41a_31), 0xf41a, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41b_31), 0xf41b, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41c_31), 0xf41c, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41d_31), 0xf41d, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41e_31), 0xf41e, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41f_31), 0xf41f, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f428_31), 0xf428, -1, { 0, 0 }, 0 }, /* CPUSHL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f430_31), 0xf430, -1, { 0, 0 }, 0 }, /* CPUSHP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f438_31), 0xf438, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f439_31), 0xf439, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43a_31), 0xf43a, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43b_31), 0xf43b, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43c_31), 0xf43c, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43d_31), 0xf43d, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43e_31), 0xf43e, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43f_31), 0xf43f, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f500_31), 0xf500, -1, { 0, 0 }, 0 }, /* PFLUSHN */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f508_31), 0xf508, -1, { 0, 0 }, 0 }, /* PFLUSH */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f510_31), 0xf510, -1, { 0, 0 }, 0 }, /* PFLUSHAN */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f518_31), 0xf518, -1, { 0, 0 }, 0 }, /* PFLUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f548_31), 0xf548, -1, { 0, 0 }, 0 }, /* PTESTW */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f568_31), 0xf568, -1, { 0, 0 }, 0 }, /* PTESTR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f600_31), 0xf600, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f608_31), 0xf608, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f610_31), 0xf610, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f618_31), 0xf618, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f620_31), 0xf620, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#endif /* CPUEMU_31 */
+#ifdef CPUEMU_32
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_32)[] = {
+{ CPUFUNC(op_0000_32), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_32), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_32), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_32), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_32), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_32), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_32), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_32), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_32), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_32), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_32), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_32), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_32), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_32), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_32), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_32), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_32), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_32), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_32), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_32), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_32), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_32), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_32), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_32), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_32), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_32), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00d0_32), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00e8_32), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f0_32), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f8_32), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f9_32), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00fa_32), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00fb_32), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0100_32), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_32), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_32), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_32), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_32), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_32), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_32), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_32), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_32), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_32), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_32), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_32), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_32), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_32), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_32), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_32), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_32), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_32), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_32), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_32), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_32), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_32), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_32), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_32), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_32), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_32), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_32), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_32), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_32), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_32), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_32), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_32), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_32), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_32), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_32), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_32), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_32), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_32), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_32), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_32), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_32), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_32), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_32), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_32), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_32), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_32), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_32), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_32), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_32), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_32), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_32), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_32), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_32), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_32), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_32), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_32), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_32), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_32), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_32), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_32), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_32), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_32), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_32), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_32), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_32), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02d0_32), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02e8_32), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f0_32), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f8_32), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f9_32), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02fa_32), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02fb_32), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0400_32), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_32), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_32), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_32), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_32), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_32), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_32), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_32), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_32), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_32), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_32), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_32), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_32), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_32), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_32), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_32), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_32), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_32), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_32), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_32), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_32), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_32), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_32), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_32), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04d0_32), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04e8_32), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f0_32), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f8_32), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f9_32), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04fa_32), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04fb_32), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0600_32), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_32), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_32), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_32), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_32), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_32), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_32), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_32), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_32), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_32), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_32), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_32), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_32), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_32), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_32), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_32), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_32), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_32), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_32), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_32), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_32), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_32), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_32), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_32), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06c0_32), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06c8_32), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06d0_32), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06e8_32), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f0_32), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f8_32), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f9_32), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06fa_32), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06fb_32), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+{ CPUFUNC(op_0800_32), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_32), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_32), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_32), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_32), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_32), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_32), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_32), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_32), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_32), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_32), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_32), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_32), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_32), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_32), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_32), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_32), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_32), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_32), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_32), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_32), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_32), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_32), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_32), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_32), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_32), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_32), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_32), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_32), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_32), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_32), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_32), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_32), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_32), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_32), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_32), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_32), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_32), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_32), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_32), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_32), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_32), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_32), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_32), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_32), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_32), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_32), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_32), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_32), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_32), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_32), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_32), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_32), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_32), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_32), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_32), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_32), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_32), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_32), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_32), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ad0_32), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ad8_32), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ae0_32), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ae8_32), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af0_32), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af8_32), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af9_32), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+{ CPUFUNC(op_0c00_32), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_32), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_32), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_32), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_32), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_32), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_32), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_32), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c3a_32), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c3b_32), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ CPUFUNC(op_0c40_32), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_32), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_32), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_32), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_32), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_32), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_32), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_32), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c7a_32), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c7b_32), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ CPUFUNC(op_0c80_32), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_32), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_32), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_32), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_32), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_32), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_32), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_32), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cba_32), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cbb_32), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cd0_32), 0x0cd0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cd8_32), 0x0cd8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ce0_32), 0x0ce0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ce8_32), 0x0ce8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf0_32), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf8_32), 0x0cf8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf9_32), 0x0cf9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cfc_32), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e10_32), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e18_32), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e20_32), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e28_32), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e30_32), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e38_32), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e39_32), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e50_32), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e58_32), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e60_32), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e68_32), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e70_32), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e78_32), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e79_32), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e90_32), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e98_32), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ea0_32), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ea8_32), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb0_32), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb8_32), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb9_32), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ed0_32), 0x0ed0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ed8_32), 0x0ed8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ee0_32), 0x0ee0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ee8_32), 0x0ee8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef0_32), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef8_32), 0x0ef8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef9_32), 0x0ef9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0efc_32), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+{ CPUFUNC(op_1000_32), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_32), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_32), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_32), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_32), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_32), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_32), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_32), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_32), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_32), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_32), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_32), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_32), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_32), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_32), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_32), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_32), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_32), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_32), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_32), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_32), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_32), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_32), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_32), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_32), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_32), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_32), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_32), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_32), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_32), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_32), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_32), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_32), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_32), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_32), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_32), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_32), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_32), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_32), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_32), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_32), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_32), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_32), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_32), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_32), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_32), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_32), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_32), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_32), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_32), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_32), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_32), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_32), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_32), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_32), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_32), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_32), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_32), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_32), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_32), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_32), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_32), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_32), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_32), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_32), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_32), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_32), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_32), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_32), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_32), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_32), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_32), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_32), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_32), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_32), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_32), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_32), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_32), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_32), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_32), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_32), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_32), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_32), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_32), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_32), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_32), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_32), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_32), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_32), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_32), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_32), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_32), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_32), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_32), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_32), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_32), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_32), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_32), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_32), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_32), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_32), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_32), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_32), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_32), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_32), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_32), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_32), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_32), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_32), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_32), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_32), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_32), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_32), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_32), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_32), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_32), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_32), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_32), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_32), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_32), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_32), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_32), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_32), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_32), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_32), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_32), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_32), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_32), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_32), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_32), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_32), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_32), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_32), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_32), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_32), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_32), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_32), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_32), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_32), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_32), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_32), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_32), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_32), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_32), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_32), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_32), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_32), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_32), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_32), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_32), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_32), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_32), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_32), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_32), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_32), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_32), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_32), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_32), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_32), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_32), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_32), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_32), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_32), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_32), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_32), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_32), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_32), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_32), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_32), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_32), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_32), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_32), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_32), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_32), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_32), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_32), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_32), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_32), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_32), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_32), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_32), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_32), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_32), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_32), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_32), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_32), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_32), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_32), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_32), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_32), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_32), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_32), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_32), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_32), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_32), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_32), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_32), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_32), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_32), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_32), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_32), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_32), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_32), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_32), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_32), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_32), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_32), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_32), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_32), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_32), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_32), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_32), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_32), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_32), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_32), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_32), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_32), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_32), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_32), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_32), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_32), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_32), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_32), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_32), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_32), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_32), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_32), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_32), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_32), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_32), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_32), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_32), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_32), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_32), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_32), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_32), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_32), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_32), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_32), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_32), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_32), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_32), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_32), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_32), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_32), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_32), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_32), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_32), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_32), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_32), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_32), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_32), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_32), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_32), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_32), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_32), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_32), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_32), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_32), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_32), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_32), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_32), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_32), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_32), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_32), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_32), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_32), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_32), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_32), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_32), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_32), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_32), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_32), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_32), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_32), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_32), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_32), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_32), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_32), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_32), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_32), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_32), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_32), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_32), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_32), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_32), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_32), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_32), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_32), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_32), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_32), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_32), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_32), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_32), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_32), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_32), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_32), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_32), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_32), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_32), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_32), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_32), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_32), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_32), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_32), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_32), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_32), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_32), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_32), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_32), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_32), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_32), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_32), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_32), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_32), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_32), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_32), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_32), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_32), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_32), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_32), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_32), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_32), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_32), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_32), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_32), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_32), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_32), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_32), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_32), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_32), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_32), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_32), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_32), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_32), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_32), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4100_32), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4110_32), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4118_32), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4120_32), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4128_32), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4130_32), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4138_32), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4139_32), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413a_32), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413b_32), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413c_32), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+{ CPUFUNC(op_4180_32), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_32), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_32), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_32), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_32), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_32), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_32), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_32), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_32), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_32), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_32), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_32), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_32), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_32), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_32), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_32), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_32), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_32), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_32), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_32), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_32), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_32), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_32), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_32), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_32), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_32), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_32), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_32), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_32), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_32), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_32), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_32), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_32), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_32), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_32), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_32), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_32), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_32), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_32), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_32), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_32), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_32), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42c0_32), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d0_32), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d8_32), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e0_32), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e8_32), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f0_32), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f8_32), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f9_32), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+{ CPUFUNC(op_4400_32), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_32), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_32), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_32), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_32), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_32), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_32), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_32), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_32), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_32), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_32), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_32), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_32), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_32), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_32), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_32), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_32), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_32), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_32), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_32), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_32), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_32), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_32), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_32), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_32), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_32), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_32), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_32), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_32), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_32), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_32), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_32), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_32), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_32), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_32), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_32), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_32), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_32), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_32), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_32), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_32), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_32), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_32), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_32), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_32), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_32), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_32), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_32), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_32), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_32), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_32), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_32), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_32), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_32), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_32), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_32), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_32), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_32), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_32), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_32), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_32), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_32), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_32), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_32), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_32), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_32), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_32), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_32), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_32), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_32), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_32), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4808_32), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#endif
+{ CPUFUNC(op_4810_32), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_32), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_32), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_32), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_32), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_32), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_32), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_32), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4848_32), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+#endif
+{ CPUFUNC(op_4850_32), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_32), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_32), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_32), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_32), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_32), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_32), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_32), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_32), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_32), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_32), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_32), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_32), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_32), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_32), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_32), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_32), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_32), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_32), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_32), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_32), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_49c0_32), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+#endif
+{ CPUFUNC(op_4a00_32), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_32), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_32), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_32), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_32), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_32), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_32), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_32), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3a_32), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3b_32), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3c_32), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a40_32), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a48_32), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a50_32), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_32), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_32), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_32), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_32), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_32), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_32), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7a_32), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7b_32), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7c_32), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a80_32), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a88_32), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a90_32), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_32), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_32), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_32), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_32), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_32), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_32), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4aba_32), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4abb_32), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4abc_32), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4ac0_32), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_32), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_32), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_32), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_32), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_32), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_32), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_32), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c00_32), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c10_32), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c18_32), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c20_32), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c28_32), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c30_32), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c38_32), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c39_32), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3a_32), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3b_32), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3c_32), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c40_32), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c50_32), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c58_32), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c60_32), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c68_32), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c70_32), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c78_32), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c79_32), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7a_32), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7b_32), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7c_32), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+{ CPUFUNC(op_4c90_32), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_32), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_32), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_32), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_32), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_32), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_32), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_32), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_32), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_32), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_32), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_32), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_32), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_32), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_32), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_32), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_32), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_32), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_32), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_32), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_32), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_32), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_32), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_32), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_32), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e74_32), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+#endif
+{ CPUFUNC(op_4e75_32), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_32), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_32), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7a_32), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7b_32), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+#endif
+{ CPUFUNC(op_4e90_32), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_32), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_32), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_32), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_32), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_32), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_32), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_32), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_32), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_32), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_32), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_32), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_32), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_32), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_32), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_32), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_32), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_32), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_32), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_32), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_32), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_32), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_32), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_32), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_32), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_32), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_32), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_32), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_32), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_32), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_32), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_32), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_32), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_32), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_32), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_32), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_32), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_32), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_32), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_32), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_32), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_32), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_32), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_32), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_32), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_32), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_32), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_32), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_32), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fa_32), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fb_32), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fc_32), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5100_32), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_32), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_32), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_32), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_32), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_32), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_32), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_32), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_32), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_32), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_32), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_32), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_32), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_32), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_32), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_32), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_32), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_32), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_32), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_32), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_32), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_32), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_32), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_32), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_32), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_32), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_32), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_32), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_32), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_32), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_32), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_32), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_32), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_32), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_32), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fa_32), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fb_32), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fc_32), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_52c0_32), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_32), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_32), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_32), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_32), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_32), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_32), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_32), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_32), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fa_32), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fb_32), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fc_32), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_53c0_32), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_32), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_32), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_32), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_32), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_32), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_32), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_32), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_32), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fa_32), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fb_32), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fc_32), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_54c0_32), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_32), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_32), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_32), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_32), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_32), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_32), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_32), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_32), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fa_32), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fb_32), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fc_32), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_55c0_32), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_32), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_32), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_32), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_32), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_32), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_32), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_32), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_32), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fa_32), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fb_32), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fc_32), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_56c0_32), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_32), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_32), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_32), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_32), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_32), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_32), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_32), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_32), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fa_32), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fb_32), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fc_32), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_57c0_32), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_32), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_32), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_32), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_32), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_32), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_32), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_32), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_32), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fa_32), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fb_32), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fc_32), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_58c0_32), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_32), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_32), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_32), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_32), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_32), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_32), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_32), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_32), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fa_32), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fb_32), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fc_32), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_59c0_32), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_32), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_32), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_32), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_32), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_32), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_32), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_32), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_32), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fa_32), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fb_32), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fc_32), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5ac0_32), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_32), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_32), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_32), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_32), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_32), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_32), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_32), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_32), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afa_32), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afb_32), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afc_32), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5bc0_32), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_32), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_32), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_32), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_32), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_32), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_32), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_32), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_32), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfa_32), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfb_32), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfc_32), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5cc0_32), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_32), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_32), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_32), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_32), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_32), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_32), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_32), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_32), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfa_32), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfb_32), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfc_32), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5dc0_32), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_32), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_32), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_32), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_32), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_32), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_32), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_32), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_32), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfa_32), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfb_32), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfc_32), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5ec0_32), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_32), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_32), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_32), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_32), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_32), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_32), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_32), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_32), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efa_32), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efb_32), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efc_32), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5fc0_32), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_32), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_32), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_32), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_32), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_32), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_32), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_32), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_32), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffa_32), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffb_32), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffc_32), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_6000_32), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_32), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_32), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6100_32), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_32), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_32), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_32), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_32), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_32), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6300_32), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_32), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_32), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6400_32), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_32), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_32), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6500_32), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_32), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_32), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6600_32), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_32), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_32), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6700_32), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_32), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_32), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6800_32), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_32), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_32), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6900_32), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_32), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_32), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a00_32), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_32), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_32), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b00_32), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_32), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_32), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c00_32), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_32), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_32), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d00_32), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_32), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_32), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e00_32), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_32), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_32), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f00_32), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_32), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_32), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_7000_32), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_32), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_32), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_32), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_32), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_32), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_32), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_32), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_32), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_32), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_32), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_32), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_32), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_32), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_32), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_32), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_32), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_32), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_32), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_32), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_32), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_32), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_32), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_32), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_32), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_32), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_32), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_32), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_32), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_32), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_32), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_32), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_32), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_32), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_32), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_32), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_32), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_32), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_32), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_32), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_32), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_32), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_32), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_32), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_32), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_32), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_32), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_32), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_32), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_32), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_32), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_32), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_32), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_32), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8140_32), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8148_32), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+{ CPUFUNC(op_8150_32), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_32), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_32), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_32), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_32), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_32), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_32), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8180_32), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8188_32), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+{ CPUFUNC(op_8190_32), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_32), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_32), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_32), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_32), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_32), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_32), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_32), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_32), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_32), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_32), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_32), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_32), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_32), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_32), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_32), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_32), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_32), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_32), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_32), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_32), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_32), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_32), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_32), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_32), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_32), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_32), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_32), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_32), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_32), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_32), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_32), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_32), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_32), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_32), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_32), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_32), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_32), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_32), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_32), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_32), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_32), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_32), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_32), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_32), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_32), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_32), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_32), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_32), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_32), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_32), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_32), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_32), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_32), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_32), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_32), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_32), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_32), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_32), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_32), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_32), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_32), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_32), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_32), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_32), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_32), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_32), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_32), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_32), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_32), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_32), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_32), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_32), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_32), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_32), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_32), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_32), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_32), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_32), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_32), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_32), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_32), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_32), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_32), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_32), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_32), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_32), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_32), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_32), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_32), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_32), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_32), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_32), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_32), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_32), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_32), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_32), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_32), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_32), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_32), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_32), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_32), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_32), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_32), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_32), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_32), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_32), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_32), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_32), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_32), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_32), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_32), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_32), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_32), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_32), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_32), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_32), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_32), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_32), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_32), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_32), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_32), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_32), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_32), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_32), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_32), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_32), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_32), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_32), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_32), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_32), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_32), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_32), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_32), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_32), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_32), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_32), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_32), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_32), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_32), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_32), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_32), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_32), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_32), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_32), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_32), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_32), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_32), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_32), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_32), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_32), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_32), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_32), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_32), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_32), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_32), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_32), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_32), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_32), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_32), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_32), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_32), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_32), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_32), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_32), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_32), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_32), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_32), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_32), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_32), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_32), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_32), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_32), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_32), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_32), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_32), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_32), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_32), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_32), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_32), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_32), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_32), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_32), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_32), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_32), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_32), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_32), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_32), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_32), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_32), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_32), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_32), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_32), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_32), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_32), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_32), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_32), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_32), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_32), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_32), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_32), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_32), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_32), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_32), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_32), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_32), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_32), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_32), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_32), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_32), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_32), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_32), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_32), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_32), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_32), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_32), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_32), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_32), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_32), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_32), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_32), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_32), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_32), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_32), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_32), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_32), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_32), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_32), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_32), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_32), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_32), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_32), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_32), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_32), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_32), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_32), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_32), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_32), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_32), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_32), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_32), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_32), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_32), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_32), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_32), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_32), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_32), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_32), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_32), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_32), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_32), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_32), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_32), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_32), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_32), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_32), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_32), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_32), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_32), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_32), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_32), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_32), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_32), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_32), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_32), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_32), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_32), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_32), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_32), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_32), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_32), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_32), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_32), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_32), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_32), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_32), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_32), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_32), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_32), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_32), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_32), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_32), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_32), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_32), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_32), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_32), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_32), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_32), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_32), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_32), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_32), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_32), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_32), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_32), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_32), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_32), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_32), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_32), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_32), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_32), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_32), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_32), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_32), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_32), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_32), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_32), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_32), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_32), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_32), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_32), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_32), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_32), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_32), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_32), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_32), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_32), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_32), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_32), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_32), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_32), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_32), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_32), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_32), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_32), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_32), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_32), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_32), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_32), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_32), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_32), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_32), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_32), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_32), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_32), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_32), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_32), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_32), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_32), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_32), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_32), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_32), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_32), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_32), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_32), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_32), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_32), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_32), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_32), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_32), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_32), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_32), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_32), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_32), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_32), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_32), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_32), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_32), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_32), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_32), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_32), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_32), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_32), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_32), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_32), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_32), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_32), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_32), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_32), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_32), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_32), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_32), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_32), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_32), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_32), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_32), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_32), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_32), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_32), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_32), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_32), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_32), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_32), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_32), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_32), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_32), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_32), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_32), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_32), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_32), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_32), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_32), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_32), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_32), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_32), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_32), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_32), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_32), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_32), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_32), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_32), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_32), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_32), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_32), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_32), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_32), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_32), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_32), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_32), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_32), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_32), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_32), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_32), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_32), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_32), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_32), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_32), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_32), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_32), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_32), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_32), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_32), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_32), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_32), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_32), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_32), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_32), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_32), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_32), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_32), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_32), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_32), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_32), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_32), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_32), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_32), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_32), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_32), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_32), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_32), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_32), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_32), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_32), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_32), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_32), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_32), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_32), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_32), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_32), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_32), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_32), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_32), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_32), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_32), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_32), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_32), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_32), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_32), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_32), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_32), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_32), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_32), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8c0_32), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8d0_32), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8e8_32), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f0_32), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f8_32), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f9_32), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8fa_32), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8fb_32), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9c0_32), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9d0_32), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9e8_32), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f0_32), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f8_32), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f9_32), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9fa_32), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9fb_32), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eac0_32), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ead0_32), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eae8_32), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf0_32), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf8_32), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf9_32), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebc0_32), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebd0_32), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebe8_32), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf0_32), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf8_32), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf9_32), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebfa_32), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebfb_32), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecc0_32), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecd0_32), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ece8_32), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf0_32), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf8_32), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf9_32), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edc0_32), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edd0_32), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ede8_32), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf0_32), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf8_32), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf9_32), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edfa_32), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edfb_32), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eec0_32), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eed0_32), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eee8_32), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef0_32), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef8_32), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef9_32), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efc0_32), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efd0_32), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efe8_32), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff0_32), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff8_32), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff9_32), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f000_32), 0xf000, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f008_32), 0xf008, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f010_32), 0xf010, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f018_32), 0xf018, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f020_32), 0xf020, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f028_32), 0xf028, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f030_32), 0xf030, -1, { -3, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f038_32), 0xf038, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f039_32), 0xf039, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f200_32), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f208_32), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f210_32), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f218_32), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f220_32), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f228_32), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f230_32), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f238_32), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f239_32), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23a_32), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23b_32), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23c_32), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f240_32), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f248_32), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f250_32), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f258_32), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f260_32), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f268_32), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f270_32), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f278_32), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f279_32), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27a_32), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27b_32), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27c_32), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f280_32), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f2c0_32), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f310_32), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f320_32), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f328_32), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f330_32), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f338_32), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f339_32), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f350_32), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f358_32), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f368_32), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f370_32), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f378_32), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f379_32), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f37a_32), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f37b_32), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#endif /* CPUEMU_32 */
+#ifdef CPUEMU_33
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_33)[] = {
+{ CPUFUNC(op_0000_33), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_33), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_33), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_33), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_33), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_33), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_33), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_33), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_33), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_33), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_33), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_33), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_33), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_33), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_33), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_33), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_33), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_33), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_33), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_33), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_33), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_33), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_33), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_33), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_33), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_33), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00d0_33), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00e8_33), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f0_33), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f8_33), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f9_33), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00fa_33), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00fb_33), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0100_33), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_33), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_33), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_33), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_33), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_33), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_33), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_33), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_33), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_33), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_33), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_33), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_33), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_33), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_33), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_33), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_33), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_33), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_33), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_33), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_33), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_33), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_33), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_33), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_33), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_33), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_33), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_33), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_33), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_33), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_33), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_33), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_33), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_33), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_33), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_33), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_33), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_33), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_33), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_33), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_33), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_33), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_33), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_33), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_33), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_33), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_33), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_33), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_33), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_33), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_33), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_33), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_33), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_33), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_33), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_33), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_33), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_33), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_33), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_33), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_33), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_33), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_33), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_33), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_33), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02d0_33), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02e8_33), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f0_33), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f8_33), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f9_33), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02fa_33), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02fb_33), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0400_33), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_33), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_33), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_33), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_33), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_33), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_33), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_33), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_33), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_33), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_33), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_33), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_33), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_33), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_33), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_33), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_33), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_33), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_33), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_33), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_33), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_33), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_33), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_33), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04d0_33), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04e8_33), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f0_33), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f8_33), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f9_33), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04fa_33), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04fb_33), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0600_33), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_33), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_33), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_33), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_33), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_33), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_33), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_33), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_33), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_33), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_33), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_33), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_33), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_33), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_33), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_33), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_33), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_33), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_33), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_33), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_33), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_33), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_33), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_33), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06c0_33), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06c8_33), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06d0_33), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06e8_33), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f0_33), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f8_33), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f9_33), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06fa_33), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06fb_33), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+{ CPUFUNC(op_0800_33), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_33), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_33), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_33), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_33), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_33), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_33), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_33), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_33), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_33), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_33), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_33), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_33), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_33), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_33), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_33), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_33), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_33), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_33), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_33), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_33), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_33), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_33), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_33), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_33), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_33), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_33), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_33), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_33), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_33), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_33), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_33), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_33), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_33), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_33), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_33), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_33), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_33), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_33), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_33), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_33), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_33), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_33), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_33), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_33), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_33), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_33), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_33), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_33), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_33), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_33), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_33), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_33), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_33), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_33), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_33), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_33), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_33), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_33), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_33), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ad0_33), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ad8_33), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ae0_33), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ae8_33), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af0_33), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af8_33), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af9_33), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+{ CPUFUNC(op_0c00_33), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_33), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_33), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_33), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_33), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_33), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_33), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_33), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c3a_33), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c3b_33), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ CPUFUNC(op_0c40_33), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_33), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_33), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_33), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_33), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_33), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_33), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_33), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c7a_33), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c7b_33), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ CPUFUNC(op_0c80_33), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_33), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_33), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_33), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_33), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_33), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_33), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_33), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cba_33), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cbb_33), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cd0_33), 0x0cd0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cd8_33), 0x0cd8, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ce0_33), 0x0ce0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ce8_33), 0x0ce8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf0_33), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf8_33), 0x0cf8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf9_33), 0x0cf9, 16, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cfc_33), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e10_33), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e18_33), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e20_33), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e28_33), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e30_33), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e38_33), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e39_33), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e50_33), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e58_33), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e60_33), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e68_33), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e70_33), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e78_33), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e79_33), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e90_33), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e98_33), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ea0_33), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ea8_33), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb0_33), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb8_33), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb9_33), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ed0_33), 0x0ed0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ed8_33), 0x0ed8, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ee0_33), 0x0ee0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ee8_33), 0x0ee8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef0_33), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef8_33), 0x0ef8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef9_33), 0x0ef9, 16, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0efc_33), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+{ CPUFUNC(op_1000_33), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_33), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_33), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_33), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_33), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_33), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_33), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_33), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_33), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_33), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_33), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_33), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_33), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_33), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_33), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_33), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_33), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_33), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_33), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_33), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_33), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_33), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_33), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_33), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_33), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_33), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_33), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_33), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_33), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_33), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_33), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_33), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_33), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_33), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_33), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_33), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_33), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_33), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_33), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_33), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_33), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_33), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_33), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_33), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_33), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_33), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_33), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_33), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_33), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_33), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_33), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_33), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_33), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_33), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_33), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_33), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_33), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_33), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_33), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_33), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_33), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_33), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_33), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_33), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_33), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_33), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_33), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_33), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_33), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_33), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_33), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_33), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_33), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_33), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_33), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_33), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_33), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_33), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_33), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_33), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_33), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_33), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_33), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_33), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_33), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_33), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_33), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_33), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_33), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_33), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_33), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_33), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_33), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_33), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_33), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_33), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_33), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_33), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_33), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_33), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_33), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_33), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_33), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_33), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_33), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_33), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_33), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_33), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_33), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_33), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_33), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_33), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_33), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_33), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_33), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_33), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_33), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_33), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_33), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_33), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_33), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_33), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_33), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_33), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_33), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_33), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_33), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_33), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_33), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_33), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_33), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_33), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_33), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_33), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_33), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_33), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_33), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_33), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_33), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_33), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_33), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_33), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_33), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_33), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_33), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_33), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_33), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_33), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_33), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_33), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_33), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_33), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_33), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_33), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_33), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_33), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_33), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_33), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_33), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_33), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_33), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_33), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_33), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_33), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_33), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_33), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_33), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_33), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_33), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_33), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_33), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_33), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_33), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_33), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_33), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_33), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_33), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_33), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_33), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_33), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_33), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_33), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_33), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_33), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_33), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_33), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_33), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_33), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_33), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_33), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_33), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_33), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_33), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_33), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_33), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_33), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_33), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_33), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_33), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_33), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_33), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_33), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_33), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_33), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_33), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_33), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_33), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_33), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_33), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_33), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_33), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_33), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_33), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_33), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_33), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_33), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_33), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_33), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_33), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_33), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_33), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_33), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_33), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_33), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_33), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_33), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_33), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_33), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_33), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_33), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_33), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_33), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_33), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_33), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_33), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_33), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_33), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_33), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_33), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_33), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_33), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_33), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_33), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_33), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_33), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_33), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_33), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_33), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_33), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_33), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_33), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_33), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_33), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_33), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_33), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_33), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_33), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_33), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_33), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_33), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_33), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_33), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_33), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_33), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_33), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_33), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_33), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_33), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_33), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_33), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_33), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_33), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_33), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_33), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_33), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_33), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_33), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_33), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_33), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_33), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_33), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_33), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_33), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_33), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_33), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_33), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_33), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_33), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_33), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_33), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_33), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_33), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_33), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_33), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_33), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_33), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_33), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_33), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_33), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_33), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_33), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_33), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_33), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_33), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_33), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_33), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_33), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_33), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_33), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_33), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_33), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_33), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_33), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_33), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_33), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_33), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_33), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_33), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_33), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_33), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_33), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_33), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_33), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_33), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_33), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_33), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_33), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_33), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_33), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_33), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_33), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_33), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_33), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_33), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_33), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_33), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4100_33), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4110_33), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4118_33), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4120_33), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4128_33), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4130_33), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4138_33), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4139_33), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413a_33), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413b_33), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413c_33), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+{ CPUFUNC(op_4180_33), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_33), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_33), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_33), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_33), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_33), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_33), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_33), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_33), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_33), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_33), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_33), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_33), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_33), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_33), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_33), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_33), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_33), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_33), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_33), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_33), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_33), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_33), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_33), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_33), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_33), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_33), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_33), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_33), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_33), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_33), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_33), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_33), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_33), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_33), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_33), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_33), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_33), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_33), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_33), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_33), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_33), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42c0_33), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d0_33), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d8_33), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e0_33), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e8_33), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f0_33), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f8_33), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f9_33), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+{ CPUFUNC(op_4400_33), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_33), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_33), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_33), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_33), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_33), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_33), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_33), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_33), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_33), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_33), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_33), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_33), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_33), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_33), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_33), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_33), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_33), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_33), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_33), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_33), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_33), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_33), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_33), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_33), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_33), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_33), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_33), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_33), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_33), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_33), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_33), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_33), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_33), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_33), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_33), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_33), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_33), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_33), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_33), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_33), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_33), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_33), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_33), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_33), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_33), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_33), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_33), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_33), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_33), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_33), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_33), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_33), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_33), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_33), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_33), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_33), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_33), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_33), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_33), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_33), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_33), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_33), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_33), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_33), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_33), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_33), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_33), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_33), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_33), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_33), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4808_33), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#endif
+{ CPUFUNC(op_4810_33), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_33), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_33), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_33), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_33), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_33), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_33), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_33), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4848_33), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+#endif
+{ CPUFUNC(op_4850_33), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_33), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_33), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_33), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_33), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_33), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_33), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_33), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_33), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_33), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_33), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_33), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_33), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_33), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_33), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_33), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_33), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_33), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_33), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_33), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_33), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_49c0_33), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+#endif
+{ CPUFUNC(op_4a00_33), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_33), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_33), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_33), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_33), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_33), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_33), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_33), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3a_33), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3b_33), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3c_33), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a40_33), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a48_33), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a50_33), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_33), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_33), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_33), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_33), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_33), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_33), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7a_33), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7b_33), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7c_33), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a80_33), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a88_33), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a90_33), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_33), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_33), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_33), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_33), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_33), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_33), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4aba_33), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4abb_33), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4abc_33), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4ac0_33), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_33), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_33), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_33), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_33), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_33), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_33), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_33), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c00_33), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c10_33), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c18_33), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c20_33), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c28_33), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c30_33), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c38_33), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c39_33), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3a_33), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3b_33), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3c_33), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c40_33), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c50_33), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c58_33), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c60_33), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c68_33), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c70_33), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c78_33), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c79_33), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7a_33), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7b_33), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7c_33), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+{ CPUFUNC(op_4c90_33), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_33), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_33), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_33), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_33), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_33), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_33), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_33), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_33), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_33), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_33), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_33), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_33), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_33), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_33), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_33), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_33), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_33), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_33), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_33), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_33), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_33), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_33), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_33), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_33), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e74_33), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+#endif
+{ CPUFUNC(op_4e75_33), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_33), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_33), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7a_33), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7b_33), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+#endif
+{ CPUFUNC(op_4e90_33), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_33), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_33), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_33), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_33), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_33), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_33), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_33), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_33), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_33), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_33), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_33), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_33), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_33), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_33), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_33), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_33), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_33), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_33), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_33), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_33), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_33), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_33), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_33), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_33), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_33), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_33), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_33), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_33), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_33), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_33), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_33), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_33), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_33), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_33), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_33), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_33), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_33), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_33), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_33), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_33), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_33), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_33), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_33), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_33), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_33), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_33), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_33), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_33), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fa_33), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fb_33), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fc_33), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5100_33), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_33), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_33), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_33), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_33), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_33), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_33), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_33), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_33), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_33), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_33), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_33), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_33), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_33), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_33), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_33), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_33), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_33), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_33), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_33), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_33), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_33), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_33), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_33), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_33), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_33), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_33), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_33), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_33), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_33), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_33), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_33), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_33), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_33), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_33), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fa_33), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fb_33), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fc_33), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_52c0_33), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_33), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_33), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_33), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_33), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_33), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_33), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_33), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_33), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fa_33), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fb_33), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fc_33), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_53c0_33), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_33), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_33), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_33), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_33), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_33), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_33), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_33), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_33), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fa_33), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fb_33), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fc_33), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_54c0_33), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_33), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_33), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_33), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_33), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_33), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_33), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_33), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_33), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fa_33), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fb_33), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fc_33), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_55c0_33), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_33), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_33), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_33), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_33), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_33), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_33), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_33), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_33), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fa_33), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fb_33), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fc_33), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_56c0_33), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_33), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_33), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_33), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_33), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_33), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_33), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_33), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_33), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fa_33), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fb_33), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fc_33), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_57c0_33), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_33), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_33), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_33), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_33), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_33), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_33), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_33), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_33), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fa_33), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fb_33), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fc_33), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_58c0_33), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_33), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_33), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_33), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_33), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_33), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_33), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_33), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_33), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fa_33), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fb_33), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fc_33), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_59c0_33), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_33), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_33), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_33), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_33), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_33), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_33), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_33), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_33), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fa_33), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fb_33), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fc_33), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5ac0_33), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_33), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_33), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_33), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_33), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_33), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_33), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_33), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_33), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afa_33), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afb_33), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afc_33), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5bc0_33), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_33), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_33), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_33), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_33), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_33), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_33), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_33), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_33), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfa_33), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfb_33), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfc_33), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5cc0_33), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_33), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_33), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_33), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_33), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_33), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_33), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_33), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_33), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfa_33), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfb_33), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfc_33), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5dc0_33), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_33), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_33), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_33), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_33), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_33), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_33), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_33), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_33), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfa_33), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfb_33), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfc_33), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5ec0_33), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_33), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_33), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_33), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_33), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_33), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_33), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_33), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_33), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efa_33), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efb_33), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efc_33), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5fc0_33), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_33), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_33), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_33), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_33), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_33), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_33), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_33), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_33), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffa_33), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffb_33), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffc_33), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_6000_33), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_33), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_33), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6100_33), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_33), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_33), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_33), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_33), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_33), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6300_33), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_33), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_33), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6400_33), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_33), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_33), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6500_33), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_33), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_33), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6600_33), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_33), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_33), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6700_33), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_33), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_33), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6800_33), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_33), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_33), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6900_33), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_33), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_33), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a00_33), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_33), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_33), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b00_33), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_33), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_33), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c00_33), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_33), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_33), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d00_33), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_33), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_33), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e00_33), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_33), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_33), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f00_33), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_33), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_33), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_7000_33), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_33), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_33), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_33), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_33), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_33), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_33), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_33), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_33), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_33), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_33), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_33), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_33), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_33), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_33), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_33), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_33), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_33), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_33), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_33), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_33), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_33), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_33), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_33), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_33), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_33), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_33), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_33), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_33), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_33), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_33), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_33), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_33), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_33), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_33), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_33), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_33), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_33), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_33), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_33), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_33), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_33), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_33), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_33), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_33), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_33), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_33), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_33), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_33), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_33), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_33), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_33), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_33), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_33), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8140_33), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8148_33), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+{ CPUFUNC(op_8150_33), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_33), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_33), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_33), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_33), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_33), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_33), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8180_33), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8188_33), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+{ CPUFUNC(op_8190_33), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_33), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_33), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_33), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_33), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_33), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_33), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_33), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_33), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_33), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_33), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_33), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_33), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_33), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_33), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_33), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_33), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_33), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_33), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_33), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_33), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_33), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_33), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_33), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_33), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_33), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_33), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_33), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_33), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_33), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_33), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_33), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_33), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_33), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_33), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_33), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_33), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_33), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_33), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_33), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_33), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_33), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_33), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_33), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_33), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_33), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_33), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_33), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_33), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_33), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_33), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_33), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_33), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_33), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_33), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_33), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_33), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_33), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_33), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_33), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_33), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_33), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_33), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_33), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_33), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_33), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_33), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_33), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_33), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_33), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_33), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_33), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_33), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_33), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_33), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_33), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_33), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_33), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_33), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_33), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_33), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_33), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_33), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_33), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_33), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_33), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_33), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_33), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_33), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_33), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_33), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_33), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_33), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_33), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_33), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_33), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_33), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_33), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_33), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_33), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_33), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_33), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_33), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_33), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_33), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_33), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_33), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_33), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_33), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_33), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_33), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_33), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_33), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_33), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_33), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_33), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_33), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_33), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_33), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_33), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_33), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_33), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_33), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_33), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_33), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_33), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_33), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_33), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_33), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_33), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_33), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_33), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_33), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_33), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_33), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_33), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_33), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_33), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_33), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_33), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_33), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_33), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_33), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_33), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_33), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_33), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_33), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_33), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_33), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_33), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_33), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_33), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_33), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_33), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_33), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_33), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_33), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_33), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_33), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_33), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_33), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_33), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_33), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_33), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_33), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_33), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_33), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_33), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_33), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_33), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_33), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_33), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_33), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_33), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_33), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_33), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_33), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_33), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_33), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_33), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_33), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_33), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_33), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_33), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_33), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_33), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_33), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_33), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_33), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_33), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_33), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_33), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_33), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_33), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_33), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_33), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_33), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_33), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_33), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_33), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_33), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_33), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_33), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_33), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_33), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_33), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_33), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_33), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_33), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_33), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_33), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_33), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_33), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_33), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_33), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_33), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_33), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_33), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_33), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_33), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_33), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_33), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_33), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_33), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_33), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_33), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_33), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_33), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_33), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_33), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_33), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_33), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_33), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_33), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_33), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_33), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_33), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_33), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_33), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_33), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_33), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_33), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_33), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_33), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_33), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_33), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_33), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_33), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_33), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_33), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_33), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_33), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_33), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_33), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_33), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_33), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_33), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_33), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_33), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_33), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_33), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_33), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_33), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_33), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_33), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_33), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_33), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_33), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_33), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_33), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_33), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_33), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_33), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_33), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_33), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_33), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_33), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_33), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_33), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_33), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_33), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_33), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_33), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_33), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_33), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_33), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_33), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_33), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_33), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_33), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_33), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_33), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_33), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_33), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_33), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_33), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_33), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_33), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_33), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_33), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_33), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_33), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_33), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_33), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_33), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_33), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_33), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_33), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_33), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_33), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_33), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_33), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_33), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_33), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_33), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_33), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_33), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_33), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_33), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_33), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_33), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_33), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_33), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_33), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_33), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_33), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_33), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_33), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_33), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_33), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_33), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_33), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_33), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_33), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_33), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_33), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_33), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_33), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_33), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_33), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_33), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_33), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_33), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_33), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_33), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_33), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_33), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_33), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_33), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_33), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_33), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_33), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_33), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_33), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_33), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_33), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_33), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_33), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_33), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_33), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_33), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_33), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_33), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_33), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_33), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_33), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_33), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_33), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_33), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_33), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_33), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_33), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_33), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_33), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_33), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_33), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_33), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_33), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_33), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_33), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_33), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_33), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_33), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_33), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_33), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_33), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_33), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_33), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_33), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_33), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_33), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_33), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_33), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_33), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_33), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_33), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_33), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_33), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_33), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_33), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_33), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_33), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_33), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_33), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_33), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_33), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_33), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_33), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_33), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_33), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_33), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_33), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_33), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_33), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_33), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_33), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_33), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_33), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_33), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_33), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_33), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_33), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_33), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_33), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_33), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_33), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_33), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_33), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_33), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_33), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_33), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_33), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_33), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_33), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_33), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_33), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_33), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_33), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_33), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_33), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_33), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_33), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_33), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_33), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_33), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_33), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_33), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_33), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_33), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_33), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_33), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_33), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_33), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_33), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_33), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_33), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_33), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_33), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_33), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_33), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_33), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8c0_33), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8d0_33), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8e8_33), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f0_33), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f8_33), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f9_33), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8fa_33), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8fb_33), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9c0_33), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9d0_33), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9e8_33), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f0_33), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f8_33), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f9_33), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9fa_33), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9fb_33), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eac0_33), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ead0_33), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eae8_33), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf0_33), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf8_33), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf9_33), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebc0_33), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebd0_33), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebe8_33), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf0_33), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf8_33), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf9_33), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebfa_33), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebfb_33), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecc0_33), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecd0_33), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ece8_33), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf0_33), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf8_33), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf9_33), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edc0_33), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edd0_33), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ede8_33), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf0_33), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf8_33), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf9_33), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edfa_33), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edfb_33), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eec0_33), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eed0_33), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eee8_33), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef0_33), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef8_33), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef9_33), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efc0_33), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efd0_33), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efe8_33), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff0_33), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff8_33), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff9_33), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f000_33), 0xf000, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f008_33), 0xf008, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f010_33), 0xf010, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f018_33), 0xf018, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f020_33), 0xf020, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f028_33), 0xf028, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f030_33), 0xf030, -1, { -3, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f038_33), 0xf038, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f039_33), 0xf039, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f200_33), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f208_33), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f210_33), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f218_33), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f220_33), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f228_33), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f230_33), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f238_33), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f239_33), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23a_33), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23b_33), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23c_33), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f240_33), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f248_33), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f250_33), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f258_33), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f260_33), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f268_33), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f270_33), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f278_33), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f279_33), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27a_33), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27b_33), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27c_33), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f280_33), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f2c0_33), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f310_33), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f320_33), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f328_33), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f330_33), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f338_33), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f339_33), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f350_33), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f358_33), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f368_33), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f370_33), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f378_33), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f379_33), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f37a_33), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f37b_33), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f408_33), 0xf408, -1, { 0, 0 }, 0 }, /* CINVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f410_33), 0xf410, -1, { 0, 0 }, 0 }, /* CINVP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f418_33), 0xf418, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f419_33), 0xf419, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41a_33), 0xf41a, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41b_33), 0xf41b, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41c_33), 0xf41c, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41d_33), 0xf41d, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41e_33), 0xf41e, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41f_33), 0xf41f, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f428_33), 0xf428, -1, { 0, 0 }, 0 }, /* CPUSHL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f430_33), 0xf430, -1, { 0, 0 }, 0 }, /* CPUSHP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f438_33), 0xf438, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f439_33), 0xf439, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43a_33), 0xf43a, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43b_33), 0xf43b, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43c_33), 0xf43c, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43d_33), 0xf43d, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43e_33), 0xf43e, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43f_33), 0xf43f, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f500_33), 0xf500, -1, { 0, 0 }, 0 }, /* PFLUSHN */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f508_33), 0xf508, -1, { 0, 0 }, 0 }, /* PFLUSH */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f510_33), 0xf510, -1, { 0, 0 }, 0 }, /* PFLUSHAN */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f518_33), 0xf518, -1, { 0, 0 }, 0 }, /* PFLUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f548_33), 0xf548, -1, { 0, 0 }, 0 }, /* PTESTW */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f568_33), 0xf568, -1, { 0, 0 }, 0 }, /* PTESTR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f588_33), 0xf588, -1, { 0, 0 }, 0 }, /* PLPAW */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f5c8_33), 0xf5c8, -1, { 0, 0 }, 0 }, /* PLPAR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f600_33), 0xf600, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f608_33), 0xf608, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f610_33), 0xf610, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f618_33), 0xf618, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f620_33), 0xf620, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f800_33), 0xf800, -1, { 0, 0 }, 0 }, /* LPSTOP */
+#endif
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#endif /* CPUEMU_33 */
+#ifdef CPUEMU_40
+const struct cputbl CPUFUNC(op_smalltbl_40)[] = {
+{ CPUFUNC(op_0000_40), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_40), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_40), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_40), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_40), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_40), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_40), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_40), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_40), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_40), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_40), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_40), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_40), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_40), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_40), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_40), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_40), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_40), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_40), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_40), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_40), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_40), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_40), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_40), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_40), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_40), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00d0_40), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00e8_40), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f0_40), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f8_40), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00f9_40), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00fa_40), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_00fb_40), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0100_40), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_40), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_40), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_40), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_40), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_40), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_40), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_40), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_40), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_40), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_40), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_40), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_40), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_40), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_40), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_40), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_40), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_40), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_40), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_40), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_40), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_40), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_40), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_40), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_40), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_40), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_40), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_40), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_40), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_40), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_40), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_40), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_40), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_40), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_40), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_40), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_40), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_40), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_40), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_40), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_40), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_40), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_40), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_40), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_40), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_40), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_40), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_40), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_40), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_40), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_40), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_40), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_40), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_40), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_40), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_40), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_40), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_40), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_40), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_40), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_40), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_40), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_40), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_40), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_40), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02d0_40), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02e8_40), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f0_40), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f8_40), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02f9_40), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02fa_40), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_02fb_40), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0400_40), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_40), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_40), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_40), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_40), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_40), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_40), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_40), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_40), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_40), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_40), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_40), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_40), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_40), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_40), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_40), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_40), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_40), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_40), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_40), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_40), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_40), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_40), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_40), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04d0_40), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04e8_40), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f0_40), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f8_40), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04f9_40), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04fa_40), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_04fb_40), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+#endif
+{ CPUFUNC(op_0600_40), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_40), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_40), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_40), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_40), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_40), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_40), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_40), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_40), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_40), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_40), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_40), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_40), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_40), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_40), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_40), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_40), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_40), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_40), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_40), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_40), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_40), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_40), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_40), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06c0_40), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06c8_40), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06d0_40), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06e8_40), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f0_40), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f8_40), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06f9_40), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06fa_40), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_06fb_40), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+#endif
+{ CPUFUNC(op_0800_40), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_40), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_40), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_40), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_40), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_40), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_40), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_40), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_40), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_40), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_40), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_40), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_40), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_40), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_40), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_40), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_40), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_40), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_40), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_40), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_40), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_40), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_40), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_40), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_40), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_40), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_40), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_40), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_40), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_40), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_40), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_40), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_40), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_40), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_40), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_40), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_40), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_40), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_40), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_40), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_40), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_40), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_40), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_40), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_40), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_40), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_40), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_40), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_40), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_40), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_40), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_40), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_40), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_40), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_40), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_40), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_40), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_40), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_40), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_40), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ad0_40), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ad8_40), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ae0_40), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ae8_40), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af0_40), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af8_40), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0af9_40), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+{ CPUFUNC(op_0c00_40), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_40), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_40), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_40), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_40), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_40), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_40), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_40), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c3a_40), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c3b_40), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ CPUFUNC(op_0c40_40), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_40), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_40), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_40), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_40), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_40), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_40), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_40), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c7a_40), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0c7b_40), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+#endif
+{ CPUFUNC(op_0c80_40), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_40), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_40), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_40), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_40), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_40), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_40), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_40), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cba_40), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cbb_40), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cd0_40), 0x0cd0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cd8_40), 0x0cd8, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ce0_40), 0x0ce0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ce8_40), 0x0ce8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf0_40), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf8_40), 0x0cf8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cf9_40), 0x0cf9, 16, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0cfc_40), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e10_40), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e18_40), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e20_40), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e28_40), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e30_40), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e38_40), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e39_40), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e50_40), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e58_40), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e60_40), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e68_40), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e70_40), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e78_40), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e79_40), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e90_40), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0e98_40), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ea0_40), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ea8_40), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb0_40), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb8_40), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0eb9_40), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ed0_40), 0x0ed0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ed8_40), 0x0ed8, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ee0_40), 0x0ee0, 8, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ee8_40), 0x0ee8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef0_40), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef8_40), 0x0ef8, 12, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0ef9_40), 0x0ef9, 16, { 0, 0 }, 0 }, /* CAS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_0efc_40), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+#endif
+{ CPUFUNC(op_1000_40), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_40), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_40), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_40), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_40), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_40), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_40), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_40), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_40), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_40), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_40), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_40), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_40), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_40), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_40), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_40), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_40), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_40), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_40), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_40), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_40), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_40), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_40), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_40), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_40), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_40), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_40), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_40), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_40), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_40), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_40), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_40), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_40), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_40), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_40), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_40), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_40), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_40), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_40), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_40), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_40), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_40), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_40), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_40), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_40), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_40), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_40), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_40), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_40), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_40), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_40), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_40), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_40), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_40), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_40), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_40), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_40), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_40), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_40), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_40), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_40), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_40), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_40), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_40), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_40), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_40), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_40), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_40), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_40), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_40), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_40), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_40), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_40), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_40), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_40), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_40), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_40), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_40), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_40), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_40), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_40), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_40), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_40), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_40), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_40), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_40), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_40), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_40), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_40), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_40), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_40), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_40), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_40), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_40), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_40), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_40), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_40), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_40), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_40), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_40), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_40), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_40), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_40), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_40), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_40), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_40), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_40), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_40), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_40), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_40), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_40), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_40), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_40), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_40), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_40), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_40), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_40), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_40), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_40), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_40), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_40), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_40), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_40), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_40), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_40), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_40), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_40), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_40), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_40), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_40), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_40), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_40), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_40), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_40), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_40), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_40), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_40), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_40), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_40), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_40), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_40), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_40), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_40), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_40), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_40), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_40), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_40), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_40), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_40), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_40), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_40), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_40), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_40), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_40), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_40), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_40), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_40), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_40), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_40), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_40), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_40), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_40), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_40), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_40), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_40), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_40), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_40), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_40), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_40), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_40), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_40), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_40), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_40), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_40), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_40), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_40), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_40), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_40), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_40), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_40), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_40), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_40), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_40), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_40), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_40), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_40), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_40), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_40), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_40), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_40), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_40), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_40), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_40), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_40), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_40), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_40), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_40), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_40), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_40), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_40), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_40), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_40), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_40), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_40), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_40), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_40), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_40), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_40), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_40), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_40), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_40), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_40), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_40), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_40), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_40), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_40), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_40), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_40), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_40), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_40), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_40), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_40), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_40), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_40), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_40), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_40), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_40), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_40), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_40), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_40), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_40), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_40), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_40), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_40), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_40), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_40), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_40), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_40), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_40), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_40), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_40), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_40), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_40), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_40), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_40), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_40), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_40), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_40), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_40), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_40), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_40), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_40), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_40), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_40), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_40), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_40), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_40), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_40), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_40), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_40), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_40), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_40), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_40), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_40), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_40), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_40), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_40), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_40), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_40), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_40), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_40), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_40), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_40), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_40), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_40), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_40), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_40), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_40), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_40), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_40), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_40), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_40), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_40), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_40), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_40), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_40), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_40), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_40), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_40), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_40), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_40), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_40), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_40), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_40), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_40), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_40), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_40), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_40), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_40), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_40), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_40), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_40), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_40), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_40), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_40), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_40), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_40), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_40), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_40), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_40), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_40), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_40), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_40), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_40), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_40), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_40), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_40), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_40), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_40), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_40), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_40), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_40), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_40), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_40), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_40), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_40), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_40), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_40), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_40), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_40), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_40), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_40), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_40), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_40), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_40), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_40), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4100_40), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4110_40), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4118_40), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4120_40), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4128_40), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4130_40), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4138_40), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4139_40), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413a_40), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413b_40), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_413c_40), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+#endif
+{ CPUFUNC(op_4180_40), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_40), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_40), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_40), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_40), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_40), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_40), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_40), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_40), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_40), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_40), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_40), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_40), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_40), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_40), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_40), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_40), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_40), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_40), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_40), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_40), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_40), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_40), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_40), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_40), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_40), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_40), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_40), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_40), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_40), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_40), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_40), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_40), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_40), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_40), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_40), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_40), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_40), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_40), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_40), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_40), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_40), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42c0_40), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d0_40), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42d8_40), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e0_40), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42e8_40), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f0_40), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f8_40), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f9_40), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+#endif
+{ CPUFUNC(op_4400_40), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_40), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_40), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_40), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_40), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_40), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_40), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_40), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_40), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_40), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_40), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_40), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_40), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_40), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_40), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_40), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_40), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_40), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_40), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_40), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_40), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_40), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_40), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_40), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_40), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_40), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_40), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_40), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_40), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_40), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_40), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_40), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_40), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_40), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_40), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_40), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_40), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_40), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_40), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_40), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_40), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_40), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_40), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_40), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_40), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_40), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_40), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_40), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_40), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_40), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_40), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_40), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_40), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_40), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_40), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_40), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_40), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_40), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_40), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_40), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_40), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_40), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_40), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_40), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_40), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_40), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_40), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_40), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_40), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_40), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_40), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4808_40), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+#endif
+{ CPUFUNC(op_4810_40), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_40), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_40), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_40), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_40), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_40), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_40), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_40), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4848_40), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+#endif
+{ CPUFUNC(op_4850_40), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_40), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_40), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_40), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_40), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_40), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_40), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_40), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_40), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_40), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_40), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_40), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_40), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_40), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_40), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_40), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_40), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_40), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_40), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_40), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_40), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_49c0_40), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+#endif
+{ CPUFUNC(op_4a00_40), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_40), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_40), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_40), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_40), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_40), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_40), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_40), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3a_40), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3b_40), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a3c_40), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a40_40), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a48_40), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a50_40), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_40), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_40), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_40), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_40), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_40), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_40), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7a_40), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7b_40), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a7c_40), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a80_40), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4a88_40), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4a90_40), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_40), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_40), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_40), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_40), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_40), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_40), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4aba_40), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4abb_40), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4abc_40), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+#endif
+{ CPUFUNC(op_4ac0_40), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_40), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_40), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_40), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_40), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_40), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_40), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_40), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c00_40), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c10_40), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c18_40), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c20_40), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c28_40), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c30_40), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c38_40), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c39_40), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3a_40), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3b_40), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c3c_40), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c40_40), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c50_40), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c58_40), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c60_40), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c68_40), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c70_40), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c78_40), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c79_40), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7a_40), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7b_40), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4c7c_40), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+#endif
+{ CPUFUNC(op_4c90_40), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_40), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_40), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_40), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_40), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_40), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_40), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_40), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_40), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_40), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_40), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_40), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_40), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_40), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_40), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_40), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_40), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_40), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_40), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_40), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_40), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_40), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_40), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_40), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_40), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e74_40), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+#endif
+{ CPUFUNC(op_4e75_40), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_40), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_40), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7a_40), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_4e7b_40), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+#endif
+{ CPUFUNC(op_4e90_40), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_40), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_40), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_40), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_40), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_40), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_40), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_40), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_40), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_40), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_40), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_40), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_40), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_40), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_40), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_40), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_40), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_40), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_40), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_40), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_40), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_40), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_40), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_40), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_40), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_40), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_40), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_40), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_40), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_40), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_40), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_40), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_40), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_40), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_40), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_40), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_40), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_40), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_40), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_40), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_40), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_40), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_40), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_40), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_40), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_40), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_40), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_40), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_40), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fa_40), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fb_40), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_50fc_40), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5100_40), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_40), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_40), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_40), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_40), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_40), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_40), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_40), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_40), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_40), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_40), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_40), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_40), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_40), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_40), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_40), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_40), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_40), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_40), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_40), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_40), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_40), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_40), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_40), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_40), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_40), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_40), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_40), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_40), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_40), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_40), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_40), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_40), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_40), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_40), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fa_40), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fb_40), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_51fc_40), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_52c0_40), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_40), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_40), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_40), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_40), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_40), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_40), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_40), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_40), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fa_40), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fb_40), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_52fc_40), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_53c0_40), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_40), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_40), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_40), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_40), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_40), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_40), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_40), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_40), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fa_40), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fb_40), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_53fc_40), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_54c0_40), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_40), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_40), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_40), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_40), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_40), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_40), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_40), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_40), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fa_40), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fb_40), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_54fc_40), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_55c0_40), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_40), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_40), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_40), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_40), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_40), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_40), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_40), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_40), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fa_40), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fb_40), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_55fc_40), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_56c0_40), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_40), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_40), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_40), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_40), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_40), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_40), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_40), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_40), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fa_40), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fb_40), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_56fc_40), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_57c0_40), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_40), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_40), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_40), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_40), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_40), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_40), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_40), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_40), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fa_40), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fb_40), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_57fc_40), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_58c0_40), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_40), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_40), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_40), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_40), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_40), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_40), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_40), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_40), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fa_40), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fb_40), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_58fc_40), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_59c0_40), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_40), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_40), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_40), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_40), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_40), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_40), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_40), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_40), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fa_40), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fb_40), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_59fc_40), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5ac0_40), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_40), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_40), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_40), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_40), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_40), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_40), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_40), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_40), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afa_40), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afb_40), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5afc_40), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5bc0_40), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_40), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_40), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_40), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_40), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_40), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_40), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_40), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_40), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfa_40), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfb_40), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5bfc_40), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5cc0_40), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_40), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_40), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_40), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_40), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_40), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_40), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_40), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_40), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfa_40), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfb_40), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5cfc_40), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5dc0_40), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_40), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_40), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_40), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_40), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_40), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_40), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_40), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_40), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfa_40), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfb_40), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5dfc_40), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5ec0_40), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_40), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_40), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_40), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_40), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_40), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_40), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_40), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_40), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efa_40), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efb_40), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5efc_40), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_5fc0_40), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_40), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_40), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_40), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_40), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_40), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_40), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_40), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_40), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffa_40), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffb_40), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_5ffc_40), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+#endif
+{ CPUFUNC(op_6000_40), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_40), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_40), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6100_40), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_40), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_40), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_40), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_40), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_40), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6300_40), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_40), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_40), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6400_40), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_40), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_40), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6500_40), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_40), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_40), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6600_40), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_40), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_40), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6700_40), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_40), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_40), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6800_40), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_40), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_40), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6900_40), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_40), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_40), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a00_40), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_40), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_40), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b00_40), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_40), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_40), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c00_40), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_40), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_40), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d00_40), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_40), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_40), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e00_40), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_40), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_40), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f00_40), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_40), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_40), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_7000_40), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_40), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_40), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_40), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_40), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_40), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_40), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_40), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_40), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_40), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_40), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_40), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_40), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_40), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_40), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_40), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_40), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_40), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_40), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_40), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_40), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_40), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_40), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_40), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_40), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_40), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_40), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_40), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_40), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_40), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_40), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_40), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_40), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_40), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_40), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_40), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_40), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_40), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_40), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_40), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_40), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_40), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_40), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_40), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_40), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_40), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_40), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_40), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_40), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_40), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_40), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_40), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_40), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_40), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8140_40), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8148_40), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+#endif
+{ CPUFUNC(op_8150_40), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_40), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_40), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_40), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_40), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_40), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_40), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8180_40), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_8188_40), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+#endif
+{ CPUFUNC(op_8190_40), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_40), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_40), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_40), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_40), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_40), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_40), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_40), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_40), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_40), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_40), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_40), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_40), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_40), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_40), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_40), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_40), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_40), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_40), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_40), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_40), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_40), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_40), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_40), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_40), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_40), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_40), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_40), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_40), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_40), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_40), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_40), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_40), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_40), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_40), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_40), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_40), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_40), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_40), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_40), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_40), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_40), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_40), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_40), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_40), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_40), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_40), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_40), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_40), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_40), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_40), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_40), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_40), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_40), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_40), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_40), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_40), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_40), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_40), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_40), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_40), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_40), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_40), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_40), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_40), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_40), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_40), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_40), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_40), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_40), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_40), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_40), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_40), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_40), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_40), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_40), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_40), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_40), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_40), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_40), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_40), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_40), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_40), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_40), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_40), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_40), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_40), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_40), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_40), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_40), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_40), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_40), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_40), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_40), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_40), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_40), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_40), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_40), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_40), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_40), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_40), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_40), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_40), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_40), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_40), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_40), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_40), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_40), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_40), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_40), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_40), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_40), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_40), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_40), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_40), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_40), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_40), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_40), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_40), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_40), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_40), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_40), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_40), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_40), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_40), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_40), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_40), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_40), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_40), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_40), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_40), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_40), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_40), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_40), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_40), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_40), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_40), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_40), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_40), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_40), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_40), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_40), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_40), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_40), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_40), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_40), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_40), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_40), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_40), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_40), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_40), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_40), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_40), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_40), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_40), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_40), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_40), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_40), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_40), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_40), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_40), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_40), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_40), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_40), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_40), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_40), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_40), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_40), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_40), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_40), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_40), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_40), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_40), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_40), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_40), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_40), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_40), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_40), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_40), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_40), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_40), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_40), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_40), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_40), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_40), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_40), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_40), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_40), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_40), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_40), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_40), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_40), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_40), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_40), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_40), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_40), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_40), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_40), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_40), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_40), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_40), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_40), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_40), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_40), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_40), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_40), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_40), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_40), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_40), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_40), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_40), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_40), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_40), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_40), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_40), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_40), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_40), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_40), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_40), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_40), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_40), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_40), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_40), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_40), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_40), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_40), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_40), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_40), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_40), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_40), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_40), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_40), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_40), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_40), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_40), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_40), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_40), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_40), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_40), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_40), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_40), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_40), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_40), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_40), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_40), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_40), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_40), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_40), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_40), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_40), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_40), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_40), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_40), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_40), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_40), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_40), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_40), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_40), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_40), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_40), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_40), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_40), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_40), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_40), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_40), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_40), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_40), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_40), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_40), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_40), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_40), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_40), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_40), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_40), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_40), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_40), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_40), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_40), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_40), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_40), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_40), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_40), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_40), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_40), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_40), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_40), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_40), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_40), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_40), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_40), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_40), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_40), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_40), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_40), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_40), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_40), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_40), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_40), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_40), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_40), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_40), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_40), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_40), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_40), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_40), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_40), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_40), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_40), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_40), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_40), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_40), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_40), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_40), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_40), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_40), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_40), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_40), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_40), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_40), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_40), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_40), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_40), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_40), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_40), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_40), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_40), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_40), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_40), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_40), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_40), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_40), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_40), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_40), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_40), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_40), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_40), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_40), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_40), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_40), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_40), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_40), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_40), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_40), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_40), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_40), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_40), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_40), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_40), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_40), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_40), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_40), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_40), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_40), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_40), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_40), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_40), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_40), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_40), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_40), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_40), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_40), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_40), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_40), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_40), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_40), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_40), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_40), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_40), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_40), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_40), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_40), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_40), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_40), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_40), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_40), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_40), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_40), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_40), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_40), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_40), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_40), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_40), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_40), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_40), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_40), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_40), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_40), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_40), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_40), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_40), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_40), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_40), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_40), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_40), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_40), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_40), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_40), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_40), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_40), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_40), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_40), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_40), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_40), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_40), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_40), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_40), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_40), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_40), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_40), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_40), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_40), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_40), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_40), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_40), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_40), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_40), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_40), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_40), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_40), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_40), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_40), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_40), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_40), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_40), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_40), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_40), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_40), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_40), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_40), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_40), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_40), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_40), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_40), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_40), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_40), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_40), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_40), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_40), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_40), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_40), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_40), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_40), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_40), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_40), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_40), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_40), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_40), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_40), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_40), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_40), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_40), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_40), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_40), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_40), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_40), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_40), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_40), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_40), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_40), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_40), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_40), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8c0_40), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8d0_40), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8e8_40), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f0_40), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f8_40), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8f9_40), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8fa_40), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e8fb_40), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9c0_40), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9d0_40), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9e8_40), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f0_40), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f8_40), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9f9_40), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9fa_40), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_e9fb_40), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eac0_40), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ead0_40), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eae8_40), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf0_40), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf8_40), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eaf9_40), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebc0_40), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebd0_40), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebe8_40), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf0_40), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf8_40), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebf9_40), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebfa_40), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ebfb_40), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecc0_40), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecd0_40), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ece8_40), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf0_40), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf8_40), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ecf9_40), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edc0_40), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edd0_40), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_ede8_40), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf0_40), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf8_40), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edf9_40), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edfa_40), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_edfb_40), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eec0_40), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eed0_40), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eee8_40), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef0_40), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef8_40), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eef9_40), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efc0_40), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efd0_40), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_efe8_40), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff0_40), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff8_40), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_eff9_40), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f000_40), 0xf000, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f008_40), 0xf008, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f010_40), 0xf010, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f018_40), 0xf018, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f020_40), 0xf020, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f028_40), 0xf028, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f030_40), 0xf030, -1, { -3, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f038_40), 0xf038, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f039_40), 0xf039, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f200_40), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f208_40), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f210_40), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f218_40), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f220_40), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f228_40), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f230_40), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f238_40), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f239_40), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23a_40), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23b_40), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f23c_40), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f240_40), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f248_40), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f250_40), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f258_40), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f260_40), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f268_40), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f270_40), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f278_40), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f279_40), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27a_40), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27b_40), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f27c_40), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f280_40), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f2c0_40), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f310_40), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f320_40), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f328_40), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f330_40), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f338_40), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f339_40), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f350_40), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f358_40), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f368_40), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f370_40), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f378_40), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f379_40), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f37a_40), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f37b_40), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f408_40), 0xf408, -1, { 0, 0 }, 0 }, /* CINVL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f410_40), 0xf410, -1, { 0, 0 }, 0 }, /* CINVP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f418_40), 0xf418, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f419_40), 0xf419, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41a_40), 0xf41a, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41b_40), 0xf41b, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41c_40), 0xf41c, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41d_40), 0xf41d, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41e_40), 0xf41e, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f41f_40), 0xf41f, -1, { 0, 0 }, 0 }, /* CINVA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f428_40), 0xf428, -1, { 0, 0 }, 0 }, /* CPUSHL */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f430_40), 0xf430, -1, { 0, 0 }, 0 }, /* CPUSHP */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f438_40), 0xf438, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f439_40), 0xf439, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43a_40), 0xf43a, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43b_40), 0xf43b, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43c_40), 0xf43c, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43d_40), 0xf43d, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43e_40), 0xf43e, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f43f_40), 0xf43f, -1, { 0, 0 }, 0 }, /* CPUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f500_40), 0xf500, -1, { 0, 0 }, 0 }, /* PFLUSHN */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f508_40), 0xf508, -1, { 0, 0 }, 0 }, /* PFLUSH */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f510_40), 0xf510, -1, { 0, 0 }, 0 }, /* PFLUSHAN */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f518_40), 0xf518, -1, { 0, 0 }, 0 }, /* PFLUSHA */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f548_40), 0xf548, -1, { 0, 0 }, 0 }, /* PTESTW */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f568_40), 0xf568, -1, { 0, 0 }, 0 }, /* PTESTR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f588_40), 0xf588, -1, { 0, 0 }, 0 }, /* PLPAW */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f5c8_40), 0xf5c8, -1, { 0, 0 }, 0 }, /* PLPAR */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f600_40), 0xf600, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f608_40), 0xf608, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f610_40), 0xf610, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f618_40), 0xf618, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f620_40), 0xf620, -1, { 0, 0 }, 0 }, /* MOVE16 */
+#endif
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_f800_40), 0xf800, -1, { 0, 0 }, 0 }, /* LPSTOP */
+#endif
+{ 0, 0 }};
+#endif /* CPUEMU_40 */
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_41)[] = {
+{ CPUFUNC(op_0000_40), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_40), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_40), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_40), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_40), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_40), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_40), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_40), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_40), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_40), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_40), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_40), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_40), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_40), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_40), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_40), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_40), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_40), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_40), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_40), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_40), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_40), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_40), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_40), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_40), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_40), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00d0_40), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00e8_40), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f0_40), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f8_40), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f9_40), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00fa_40), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00fb_40), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0100_40), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_40), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_40), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_40), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_40), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_40), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_40), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_40), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_40), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_40), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_40), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_40), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_40), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_40), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_40), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_40), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_40), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_40), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_40), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_40), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_40), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_40), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_40), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_40), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_40), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_40), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_40), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_40), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_40), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_40), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_40), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_40), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_40), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_40), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_40), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_40), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_40), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_40), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_40), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_40), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_40), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_40), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_40), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_40), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_40), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_40), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_40), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_40), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_40), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_40), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_40), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_40), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_40), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_40), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_40), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_40), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_40), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_40), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_40), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_40), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_40), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_40), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_40), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_40), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_40), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02d0_40), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02e8_40), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f0_40), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f8_40), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f9_40), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02fa_40), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02fb_40), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0400_40), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_40), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_40), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_40), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_40), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_40), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_40), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_40), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_40), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_40), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_40), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_40), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_40), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_40), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_40), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_40), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_40), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_40), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_40), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_40), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_40), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_40), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_40), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_40), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04d0_40), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04e8_40), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f0_40), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f8_40), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f9_40), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04fa_40), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04fb_40), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0600_40), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_40), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_40), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_40), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_40), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_40), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_40), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_40), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_40), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_40), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_40), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_40), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_40), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_40), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_40), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_40), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_40), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_40), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_40), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_40), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_40), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_40), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_40), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_40), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06c0_40), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+{ CPUFUNC(op_06c8_40), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+{ CPUFUNC(op_06d0_40), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06e8_40), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f0_40), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f8_40), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f9_40), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06fa_40), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06fb_40), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_0800_40), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_40), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_40), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_40), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_40), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_40), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_40), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_40), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_40), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_40), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_40), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_40), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_40), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_40), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_40), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_40), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_40), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_40), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_40), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_40), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_40), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_40), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_40), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_40), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_40), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_40), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_40), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_40), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_40), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_40), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_40), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_40), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_40), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_40), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_40), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_40), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_40), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_40), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_40), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_40), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_40), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_40), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_40), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_40), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_40), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_40), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_40), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_40), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_40), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_40), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_40), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_40), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_40), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_40), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_40), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_40), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_40), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_40), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_40), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_40), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ad0_40), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ad8_40), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ae0_40), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ae8_40), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af0_40), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af8_40), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af9_40), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0c00_40), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_40), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_40), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_40), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_40), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_40), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_40), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_40), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c3a_40), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c3b_40), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c40_40), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_40), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_40), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_40), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_40), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_40), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_40), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_40), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c7a_40), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c7b_40), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c80_40), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_40), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_40), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_40), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_40), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_40), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_40), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_40), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cba_40), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cbb_40), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cd0_40), 0x0cd0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cd8_40), 0x0cd8, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ce0_40), 0x0ce0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ce8_40), 0x0ce8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf0_40), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf8_40), 0x0cf8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf9_40), 0x0cf9, 16, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cfc_40), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+{ CPUFUNC(op_0e10_40), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e18_40), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e20_40), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e28_40), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e30_40), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e38_40), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e39_40), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e50_40), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e58_40), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e60_40), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e68_40), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e70_40), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e78_40), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e79_40), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e90_40), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e98_40), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ea0_40), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ea8_40), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb0_40), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb8_40), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb9_40), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ed0_40), 0x0ed0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ed8_40), 0x0ed8, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ee0_40), 0x0ee0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ee8_40), 0x0ee8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef0_40), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef8_40), 0x0ef8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef9_40), 0x0ef9, 16, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0efc_40), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+{ CPUFUNC(op_1000_40), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_40), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_40), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_40), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_40), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_40), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_40), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_40), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_40), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_40), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_40), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_40), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_40), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_40), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_40), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_40), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_40), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_40), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_40), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_40), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_40), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_40), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_40), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_40), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_40), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_40), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_40), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_40), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_40), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_40), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_40), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_40), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_40), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_40), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_40), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_40), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_40), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_40), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_40), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_40), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_40), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_40), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_40), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_40), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_40), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_40), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_40), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_40), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_40), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_40), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_40), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_40), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_40), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_40), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_40), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_40), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_40), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_40), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_40), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_40), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_40), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_40), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_40), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_40), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_40), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_40), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_40), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_40), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_40), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_40), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_40), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_40), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_40), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_40), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_40), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_40), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_40), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_40), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_40), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_40), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_40), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_40), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_40), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_40), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_40), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_40), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_40), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_40), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_40), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_40), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_40), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_40), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_40), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_40), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_40), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_40), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_40), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_40), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_40), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_40), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_40), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_40), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_40), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_40), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_40), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_40), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_40), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_40), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_40), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_40), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_40), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_40), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_40), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_40), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_40), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_40), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_40), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_40), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_40), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_40), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_40), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_40), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_40), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_40), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_40), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_40), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_40), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_40), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_40), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_40), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_40), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_40), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_40), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_40), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_40), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_40), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_40), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_40), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_40), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_40), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_40), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_40), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_40), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_40), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_40), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_40), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_40), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_40), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_40), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_40), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_40), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_40), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_40), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_40), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_40), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_40), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_40), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_40), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_40), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_40), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_40), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_40), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_40), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_40), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_40), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_40), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_40), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_40), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_40), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_40), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_40), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_40), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_40), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_40), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_40), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_40), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_40), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_40), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_40), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_40), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_40), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_40), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_40), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_40), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_40), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_40), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_40), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_40), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_40), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_40), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_40), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_40), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_40), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_40), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_40), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_40), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_40), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_40), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_40), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_40), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_40), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_40), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_40), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_40), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_40), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_40), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_40), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_40), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_40), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_40), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_40), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_40), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_40), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_40), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_40), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_40), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_40), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_40), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_40), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_40), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_40), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_40), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_40), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_40), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_40), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_40), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_40), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_40), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_40), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_40), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_40), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_40), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_40), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_40), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_40), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_40), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_40), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_40), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_40), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_40), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_40), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_40), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_40), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_40), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_40), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_40), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_40), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_40), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_40), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_40), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_40), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_40), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_40), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_40), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_40), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_40), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_40), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_40), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_40), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_40), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_40), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_40), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_40), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_40), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_40), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_40), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_40), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_40), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_40), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_40), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_40), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_40), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_40), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_40), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_40), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_40), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_40), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_40), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_40), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_40), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_40), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_40), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_40), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_40), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_40), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_40), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_40), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_40), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_40), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_40), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_40), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_40), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_40), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_40), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_40), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_40), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_40), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_40), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_40), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_40), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_40), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_40), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_40), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_40), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_40), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_40), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_40), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_40), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_40), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_40), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_40), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_40), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_40), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_40), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_40), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_40), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_40), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_40), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_40), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_40), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_40), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_40), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_40), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_40), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_40), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_40), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_40), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_40), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_40), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_40), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_40), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_40), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_40), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_40), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_40), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_40), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4100_40), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4110_40), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4118_40), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4120_40), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4128_40), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4130_40), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4138_40), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4139_40), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413a_40), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413b_40), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413c_40), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4180_40), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_40), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_40), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_40), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_40), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_40), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_40), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_40), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_40), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_40), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_40), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_40), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_40), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_40), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_40), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_40), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_40), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_40), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_40), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_40), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_40), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_40), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_40), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_40), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_40), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_40), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_40), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_40), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_40), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_40), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_40), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_40), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_40), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_40), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_40), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_40), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_40), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_40), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_40), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_40), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_40), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_40), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42c0_40), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d0_40), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d8_40), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e0_40), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e8_40), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f0_40), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f8_40), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f9_40), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4400_40), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_40), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_40), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_40), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_40), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_40), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_40), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_40), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_40), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_40), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_40), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_40), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_40), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_40), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_40), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_40), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_40), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_40), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_40), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_40), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_40), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_40), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_40), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_40), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_40), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_40), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_40), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_40), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_40), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_40), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_40), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_40), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_40), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_40), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_40), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_40), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_40), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_40), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_40), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_40), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_40), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_40), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_40), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_40), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_40), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_40), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_40), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_40), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_40), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_40), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_40), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_40), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_40), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_40), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_40), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_40), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_40), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_40), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_40), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_40), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_40), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_40), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_40), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_40), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_40), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_40), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_40), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_40), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_40), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_40), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_40), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4808_40), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4810_40), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_40), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_40), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_40), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_40), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_40), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_40), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_40), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ CPUFUNC(op_4848_40), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+{ CPUFUNC(op_4850_40), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_40), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_40), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_40), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_40), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_40), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_40), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_40), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_40), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_40), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_40), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_40), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_40), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_40), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_40), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_40), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_40), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_40), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_40), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_40), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_40), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_49c0_40), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4a00_40), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_40), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_40), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_40), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_40), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_40), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_40), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_40), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3a_40), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3b_40), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3c_40), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a40_40), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a48_40), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a50_40), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_40), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_40), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_40), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_40), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_40), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_40), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7a_40), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7b_40), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7c_40), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a80_40), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a88_40), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a90_40), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_40), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_40), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_40), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_40), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_40), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_40), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aba_40), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4abb_40), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4abc_40), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ac0_40), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_40), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_40), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_40), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_40), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_40), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_40), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_40), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4c00_40), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c10_40), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c18_40), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c20_40), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c28_40), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c30_40), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c38_40), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c39_40), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3a_40), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3b_40), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3c_40), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c40_40), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c50_40), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c58_40), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c60_40), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c68_40), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c70_40), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c78_40), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c79_40), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7a_40), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7b_40), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7c_40), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c90_40), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_40), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_40), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_40), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_40), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_40), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_40), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_40), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_40), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_40), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_40), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_40), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_40), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_40), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_40), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_40), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_40), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_40), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_40), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_40), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_40), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_40), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_40), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_40), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_40), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+{ CPUFUNC(op_4e74_40), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+{ CPUFUNC(op_4e75_40), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_40), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_40), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+{ CPUFUNC(op_4e7a_40), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+{ CPUFUNC(op_4e7b_40), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+{ CPUFUNC(op_4e90_40), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_40), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_40), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_40), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_40), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_40), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_40), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_40), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_40), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_40), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_40), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_40), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_40), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_40), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_40), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_40), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_40), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_40), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_40), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_40), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_40), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_40), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_40), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_40), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_40), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_40), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_40), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_40), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_40), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_40), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_40), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_40), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_40), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_40), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_40), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_40), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_40), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_40), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_40), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_40), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_40), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_40), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_40), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_40), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_40), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_40), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_40), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_40), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_40), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50fa_40), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_50fb_40), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_50fc_40), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5100_40), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_40), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_40), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_40), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_40), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_40), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_40), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_40), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_40), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_40), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_40), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_40), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_40), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_40), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_40), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_40), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_40), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_40), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_40), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_40), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_40), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_40), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_40), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_40), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_40), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_40), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_40), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_40), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_40), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_40), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_40), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_40), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_40), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_40), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_40), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51fa_40), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_51fb_40), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_51fc_40), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52c0_40), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_40), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_40), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_40), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_40), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_40), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_40), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_40), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_40), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52fa_40), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52fb_40), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52fc_40), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53c0_40), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_40), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_40), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_40), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_40), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_40), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_40), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_40), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_40), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53fa_40), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53fb_40), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53fc_40), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54c0_40), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_40), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_40), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_40), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_40), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_40), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_40), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_40), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_40), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54fa_40), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54fb_40), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54fc_40), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55c0_40), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_40), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_40), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_40), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_40), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_40), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_40), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_40), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_40), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55fa_40), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55fb_40), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55fc_40), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56c0_40), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_40), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_40), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_40), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_40), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_40), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_40), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_40), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_40), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56fa_40), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56fb_40), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56fc_40), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57c0_40), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_40), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_40), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_40), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_40), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_40), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_40), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_40), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_40), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57fa_40), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57fb_40), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57fc_40), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58c0_40), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_40), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_40), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_40), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_40), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_40), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_40), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_40), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_40), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58fa_40), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58fb_40), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58fc_40), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59c0_40), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_40), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_40), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_40), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_40), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_40), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_40), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_40), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_40), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59fa_40), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59fb_40), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59fc_40), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ac0_40), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_40), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_40), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_40), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_40), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_40), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_40), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_40), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_40), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5afa_40), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5afb_40), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5afc_40), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bc0_40), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_40), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_40), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_40), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_40), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_40), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_40), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_40), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_40), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bfa_40), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bfb_40), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bfc_40), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cc0_40), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_40), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_40), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_40), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_40), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_40), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_40), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_40), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_40), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cfa_40), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cfb_40), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cfc_40), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dc0_40), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_40), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_40), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_40), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_40), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_40), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_40), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_40), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_40), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dfa_40), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dfb_40), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dfc_40), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ec0_40), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_40), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_40), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_40), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_40), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_40), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_40), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_40), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_40), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5efa_40), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5efb_40), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5efc_40), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5fc0_40), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_40), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_40), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_40), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_40), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_40), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_40), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_40), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_40), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ffa_40), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ffb_40), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ffc_40), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_6000_40), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_40), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_40), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6100_40), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_40), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_40), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_40), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_40), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_40), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6300_40), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_40), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_40), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6400_40), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_40), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_40), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6500_40), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_40), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_40), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6600_40), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_40), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_40), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6700_40), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_40), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_40), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6800_40), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_40), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_40), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6900_40), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_40), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_40), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a00_40), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_40), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_40), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b00_40), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_40), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_40), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c00_40), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_40), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_40), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d00_40), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_40), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_40), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e00_40), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_40), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_40), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f00_40), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_40), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_40), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_7000_40), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_40), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_40), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_40), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_40), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_40), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_40), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_40), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_40), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_40), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_40), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_40), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_40), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_40), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_40), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_40), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_40), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_40), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_40), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_40), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_40), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_40), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_40), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_40), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_40), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_40), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_40), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_40), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_40), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_40), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_40), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_40), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_40), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_40), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_40), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_40), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_40), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_40), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_40), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_40), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_40), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_40), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_40), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_40), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_40), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_40), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_40), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_40), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_40), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_40), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_40), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_40), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_40), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_40), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8140_40), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+{ CPUFUNC(op_8148_40), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+{ CPUFUNC(op_8150_40), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_40), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_40), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_40), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_40), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_40), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_40), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8180_40), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+{ CPUFUNC(op_8188_40), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+{ CPUFUNC(op_8190_40), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_40), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_40), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_40), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_40), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_40), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_40), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_40), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_40), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_40), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_40), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_40), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_40), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_40), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_40), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_40), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_40), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_40), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_40), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_40), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_40), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_40), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_40), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_40), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_40), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_40), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_40), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_40), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_40), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_40), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_40), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_40), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_40), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_40), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_40), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_40), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_40), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_40), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_40), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_40), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_40), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_40), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_40), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_40), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_40), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_40), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_40), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_40), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_40), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_40), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_40), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_40), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_40), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_40), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_40), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_40), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_40), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_40), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_40), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_40), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_40), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_40), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_40), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_40), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_40), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_40), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_40), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_40), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_40), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_40), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_40), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_40), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_40), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_40), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_40), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_40), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_40), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_40), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_40), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_40), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_40), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_40), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_40), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_40), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_40), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_40), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_40), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_40), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_40), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_40), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_40), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_40), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_40), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_40), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_40), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_40), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_40), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_40), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_40), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_40), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_40), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_40), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_40), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_40), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_40), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_40), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_40), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_40), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_40), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_40), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_40), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_40), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_40), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_40), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_40), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_40), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_40), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_40), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_40), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_40), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_40), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_40), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_40), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_40), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_40), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_40), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_40), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_40), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_40), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_40), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_40), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_40), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_40), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_40), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_40), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_40), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_40), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_40), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_40), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_40), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_40), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_40), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_40), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_40), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_40), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_40), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_40), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_40), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_40), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_40), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_40), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_40), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_40), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_40), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_40), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_40), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_40), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_40), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_40), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_40), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_40), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_40), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_40), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_40), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_40), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_40), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_40), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_40), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_40), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_40), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_40), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_40), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_40), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_40), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_40), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_40), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_40), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_40), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_40), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_40), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_40), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_40), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_40), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_40), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_40), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_40), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_40), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_40), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_40), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_40), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_40), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_40), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_40), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_40), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_40), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_40), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_40), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_40), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_40), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_40), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_40), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_40), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_40), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_40), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_40), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_40), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_40), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_40), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_40), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_40), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_40), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_40), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_40), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_40), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_40), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_40), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_40), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_40), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_40), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_40), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_40), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_40), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_40), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_40), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_40), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_40), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_40), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_40), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_40), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_40), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_40), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_40), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_40), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_40), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_40), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_40), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_40), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_40), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_40), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_40), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_40), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_40), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_40), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_40), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_40), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_40), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_40), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_40), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_40), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_40), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_40), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_40), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_40), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_40), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_40), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_40), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_40), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_40), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_40), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_40), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_40), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_40), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_40), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_40), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_40), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_40), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_40), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_40), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_40), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_40), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_40), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_40), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_40), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_40), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_40), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_40), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_40), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_40), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_40), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_40), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_40), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_40), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_40), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_40), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_40), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_40), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_40), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_40), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_40), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_40), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_40), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_40), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_40), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_40), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_40), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_40), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_40), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_40), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_40), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_40), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_40), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_40), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_40), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_40), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_40), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_40), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_40), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_40), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_40), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_40), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_40), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_40), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_40), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_40), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_40), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_40), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_40), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_40), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_40), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_40), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_40), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_40), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_40), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_40), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_40), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_40), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_40), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_40), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_40), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_40), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_40), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_40), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_40), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_40), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_40), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_40), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_40), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_40), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_40), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_40), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_40), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_40), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_40), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_40), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_40), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_40), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_40), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_40), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_40), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_40), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_40), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_40), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_40), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_40), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_40), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_40), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_40), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_40), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_40), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_40), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_40), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_40), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_40), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_40), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_40), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_40), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_40), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_40), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_40), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_40), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_40), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_40), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_40), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_40), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_40), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_40), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_40), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_40), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_40), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_40), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_40), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_40), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_40), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_40), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_40), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_40), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_40), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_40), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_40), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_40), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_40), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_40), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_40), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_40), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_40), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_40), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_40), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_40), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_40), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_40), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_40), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_40), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_40), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_40), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_40), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_40), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_40), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_40), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_40), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_40), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_40), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_40), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_40), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_40), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_40), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_40), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_40), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_40), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_40), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_40), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_40), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_40), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_40), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_40), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_40), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_40), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_40), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_40), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_40), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_40), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_40), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_40), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_40), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_40), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_40), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_40), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_40), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_40), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_40), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_40), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_40), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_40), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_40), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_40), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_40), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_40), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_40), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_40), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_40), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_40), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_40), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_40), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_40), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_40), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_40), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_40), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_40), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_40), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_40), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_40), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_40), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e8c0_40), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8d0_40), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8e8_40), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f0_40), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f8_40), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f9_40), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8fa_40), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8fb_40), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e9c0_40), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9d0_40), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9e8_40), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f0_40), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f8_40), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f9_40), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9fa_40), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9fb_40), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_eac0_40), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_ead0_40), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eae8_40), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf0_40), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf8_40), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf9_40), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_ebc0_40), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebd0_40), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebe8_40), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf0_40), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf8_40), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf9_40), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebfa_40), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebfb_40), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ecc0_40), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecd0_40), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ece8_40), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf0_40), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf8_40), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf9_40), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_edc0_40), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edd0_40), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_ede8_40), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf0_40), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf8_40), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf9_40), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edfa_40), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edfb_40), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_eec0_40), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eed0_40), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eee8_40), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef0_40), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef8_40), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef9_40), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_efc0_40), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_efd0_40), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_efe8_40), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff0_40), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff8_40), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff9_40), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_f000_40), 0xf000, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f008_40), 0xf008, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f010_40), 0xf010, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f018_40), 0xf018, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f020_40), 0xf020, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f028_40), 0xf028, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f030_40), 0xf030, -1, { -3, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f038_40), 0xf038, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f039_40), 0xf039, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f200_40), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f208_40), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f210_40), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f218_40), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f220_40), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f228_40), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f230_40), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f238_40), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f239_40), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23a_40), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23b_40), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23c_40), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f240_40), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f248_40), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+{ CPUFUNC(op_f250_40), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f258_40), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f260_40), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f268_40), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f270_40), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f278_40), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f279_40), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f27a_40), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f27b_40), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f27c_40), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f280_40), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+{ CPUFUNC(op_f2c0_40), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+{ CPUFUNC(op_f310_40), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f320_40), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f328_40), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f330_40), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f338_40), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f339_40), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f350_40), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f358_40), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f368_40), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f370_40), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f378_40), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f379_40), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f37a_40), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f37b_40), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f408_40), 0xf408, -1, { 0, 0 }, 0 }, /* CINVL */
+{ CPUFUNC(op_f410_40), 0xf410, -1, { 0, 0 }, 0 }, /* CINVP */
+{ CPUFUNC(op_f418_40), 0xf418, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f419_40), 0xf419, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f41a_40), 0xf41a, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f41b_40), 0xf41b, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f41c_40), 0xf41c, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f41d_40), 0xf41d, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f41e_40), 0xf41e, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f41f_40), 0xf41f, -1, { 0, 0 }, 0 }, /* CINVA */
+{ CPUFUNC(op_f428_40), 0xf428, -1, { 0, 0 }, 0 }, /* CPUSHL */
+{ CPUFUNC(op_f430_40), 0xf430, -1, { 0, 0 }, 0 }, /* CPUSHP */
+{ CPUFUNC(op_f438_40), 0xf438, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f439_40), 0xf439, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f43a_40), 0xf43a, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f43b_40), 0xf43b, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f43c_40), 0xf43c, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f43d_40), 0xf43d, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f43e_40), 0xf43e, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f43f_40), 0xf43f, -1, { 0, 0 }, 0 }, /* CPUSHA */
+{ CPUFUNC(op_f500_40), 0xf500, -1, { 0, 0 }, 0 }, /* PFLUSHN */
+{ CPUFUNC(op_f508_40), 0xf508, -1, { 0, 0 }, 0 }, /* PFLUSH */
+{ CPUFUNC(op_f510_40), 0xf510, -1, { 0, 0 }, 0 }, /* PFLUSHAN */
+{ CPUFUNC(op_f518_40), 0xf518, -1, { 0, 0 }, 0 }, /* PFLUSHA */
+{ CPUFUNC(op_f548_40), 0xf548, -1, { 0, 0 }, 0 }, /* PTESTW */
+{ CPUFUNC(op_f568_40), 0xf568, -1, { 0, 0 }, 0 }, /* PTESTR */
+{ CPUFUNC(op_f600_40), 0xf600, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ CPUFUNC(op_f608_40), 0xf608, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ CPUFUNC(op_f610_40), 0xf610, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ CPUFUNC(op_f618_40), 0xf618, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ CPUFUNC(op_f620_40), 0xf620, -1, { 0, 0 }, 0 }, /* MOVE16 */
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_42)[] = {
+{ CPUFUNC(op_0000_40), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_40), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_40), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_40), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_40), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_40), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_40), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_40), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_40), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_40), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_40), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_40), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_40), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_40), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_40), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_40), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_40), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_40), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_40), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_40), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_40), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_40), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_40), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_40), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_40), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_40), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00d0_40), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00e8_40), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f0_40), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f8_40), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f9_40), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00fa_40), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00fb_40), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0100_40), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_40), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_40), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_40), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_40), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_40), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_40), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_40), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_40), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_40), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_40), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_40), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_40), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_40), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_40), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_40), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_40), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_40), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_40), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_40), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_40), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_40), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_40), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_40), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_40), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_40), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_40), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_40), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_40), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_40), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_40), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_40), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_40), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_40), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_40), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_40), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_40), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_40), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_40), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_40), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_40), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_40), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_40), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_40), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_40), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_40), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_40), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_40), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_40), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_40), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_40), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_40), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_40), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_40), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_40), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_40), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_40), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_40), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_40), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_40), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_40), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_40), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_40), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_40), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_40), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02d0_40), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02e8_40), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f0_40), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f8_40), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f9_40), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02fa_40), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02fb_40), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0400_40), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_40), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_40), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_40), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_40), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_40), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_40), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_40), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_40), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_40), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_40), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_40), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_40), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_40), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_40), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_40), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_40), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_40), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_40), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_40), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_40), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_40), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_40), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_40), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04d0_40), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04e8_40), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f0_40), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f8_40), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f9_40), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04fa_40), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04fb_40), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0600_40), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_40), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_40), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_40), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_40), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_40), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_40), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_40), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_40), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_40), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_40), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_40), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_40), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_40), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_40), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_40), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_40), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_40), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_40), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_40), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_40), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_40), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_40), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_40), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06c0_40), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+{ CPUFUNC(op_06c8_40), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+{ CPUFUNC(op_06d0_40), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06e8_40), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f0_40), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f8_40), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f9_40), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06fa_40), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06fb_40), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_0800_40), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_40), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_40), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_40), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_40), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_40), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_40), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_40), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_40), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_40), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_40), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_40), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_40), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_40), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_40), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_40), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_40), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_40), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_40), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_40), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_40), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_40), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_40), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_40), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_40), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_40), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_40), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_40), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_40), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_40), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_40), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_40), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_40), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_40), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_40), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_40), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_40), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_40), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_40), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_40), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_40), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_40), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_40), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_40), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_40), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_40), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_40), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_40), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_40), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_40), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_40), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_40), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_40), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_40), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_40), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_40), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_40), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_40), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_40), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_40), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ad0_40), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ad8_40), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ae0_40), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ae8_40), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af0_40), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af8_40), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af9_40), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0c00_40), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_40), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_40), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_40), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_40), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_40), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_40), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_40), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c3a_40), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c3b_40), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c40_40), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_40), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_40), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_40), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_40), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_40), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_40), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_40), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c7a_40), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c7b_40), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c80_40), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_40), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_40), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_40), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_40), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_40), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_40), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_40), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cba_40), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cbb_40), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cd0_40), 0x0cd0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cd8_40), 0x0cd8, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ce0_40), 0x0ce0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ce8_40), 0x0ce8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf0_40), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf8_40), 0x0cf8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf9_40), 0x0cf9, 16, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cfc_40), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+{ CPUFUNC(op_0e10_40), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e18_40), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e20_40), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e28_40), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e30_40), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e38_40), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e39_40), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e50_40), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e58_40), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e60_40), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e68_40), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e70_40), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e78_40), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e79_40), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e90_40), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e98_40), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ea0_40), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ea8_40), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb0_40), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb8_40), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb9_40), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ed0_40), 0x0ed0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ed8_40), 0x0ed8, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ee0_40), 0x0ee0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ee8_40), 0x0ee8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef0_40), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef8_40), 0x0ef8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef9_40), 0x0ef9, 16, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0efc_40), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+{ CPUFUNC(op_1000_40), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_40), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_40), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_40), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_40), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_40), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_40), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_40), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_40), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_40), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_40), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_40), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_40), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_40), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_40), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_40), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_40), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_40), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_40), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_40), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_40), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_40), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_40), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_40), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_40), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_40), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_40), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_40), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_40), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_40), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_40), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_40), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_40), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_40), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_40), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_40), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_40), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_40), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_40), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_40), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_40), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_40), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_40), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_40), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_40), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_40), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_40), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_40), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_40), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_40), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_40), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_40), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_40), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_40), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_40), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_40), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_40), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_40), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_40), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_40), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_40), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_40), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_40), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_40), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_40), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_40), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_40), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_40), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_40), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_40), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_40), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_40), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_40), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_40), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_40), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_40), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_40), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_40), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_40), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_40), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_40), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_40), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_40), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_40), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_40), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_40), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_40), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_40), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_40), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_40), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_40), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_40), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_40), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_40), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_40), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_40), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_40), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_40), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_40), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_40), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_40), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_40), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_40), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_40), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_40), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_40), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_40), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_40), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_40), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_40), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_40), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_40), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_40), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_40), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_40), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_40), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_40), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_40), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_40), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_40), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_40), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_40), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_40), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_40), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_40), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_40), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_40), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_40), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_40), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_40), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_40), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_40), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_40), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_40), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_40), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_40), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_40), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_40), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_40), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_40), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_40), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_40), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_40), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_40), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_40), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_40), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_40), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_40), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_40), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_40), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_40), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_40), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_40), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_40), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_40), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_40), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_40), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_40), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_40), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_40), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_40), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_40), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_40), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_40), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_40), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_40), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_40), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_40), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_40), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_40), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_40), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_40), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_40), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_40), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_40), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_40), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_40), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_40), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_40), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_40), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_40), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_40), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_40), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_40), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_40), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_40), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_40), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_40), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_40), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_40), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_40), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_40), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_40), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_40), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_40), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_40), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_40), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_40), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_40), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_40), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_40), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_40), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_40), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_40), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_40), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_40), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_40), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_40), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_40), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_40), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_40), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_40), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_40), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_40), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_40), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_40), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_40), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_40), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_40), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_40), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_40), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_40), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_40), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_40), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_40), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_40), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_40), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_40), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_40), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_40), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_40), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_40), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_40), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_40), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_40), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_40), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_40), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_40), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_40), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_40), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_40), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_40), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_40), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_40), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_40), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_40), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_40), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_40), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_40), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_40), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_40), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_40), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_40), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_40), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_40), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_40), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_40), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_40), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_40), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_40), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_40), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_40), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_40), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_40), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_40), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_40), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_40), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_40), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_40), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_40), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_40), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_40), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_40), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_40), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_40), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_40), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_40), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_40), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_40), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_40), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_40), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_40), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_40), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_40), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_40), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_40), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_40), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_40), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_40), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_40), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_40), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_40), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_40), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_40), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_40), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_40), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_40), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_40), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_40), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_40), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_40), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_40), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_40), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_40), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_40), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_40), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_40), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_40), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_40), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_40), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_40), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_40), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_40), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_40), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_40), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_40), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_40), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_40), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_40), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_40), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_40), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_40), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_40), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_40), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_40), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_40), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_40), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_40), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_40), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_40), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_40), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_40), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_40), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_40), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_40), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_40), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4100_40), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4110_40), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4118_40), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4120_40), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4128_40), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4130_40), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4138_40), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4139_40), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413a_40), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413b_40), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413c_40), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4180_40), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_40), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_40), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_40), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_40), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_40), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_40), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_40), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_40), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_40), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_40), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_40), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_40), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_40), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_40), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_40), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_40), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_40), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_40), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_40), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_40), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_40), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_40), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_40), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_40), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_40), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_40), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_40), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_40), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_40), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_40), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_40), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_40), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_40), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_40), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_40), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_40), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_40), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_40), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_40), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_40), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_40), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42c0_40), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d0_40), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d8_40), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e0_40), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e8_40), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f0_40), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f8_40), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f9_40), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4400_40), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_40), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_40), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_40), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_40), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_40), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_40), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_40), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_40), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_40), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_40), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_40), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_40), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_40), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_40), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_40), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_40), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_40), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_40), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_40), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_40), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_40), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_40), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_40), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_40), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_40), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_40), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_40), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_40), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_40), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_40), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_40), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_40), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_40), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_40), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_40), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_40), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_40), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_40), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_40), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_40), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_40), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_40), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_40), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_40), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_40), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_40), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_40), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_40), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_40), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_40), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_40), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_40), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_40), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_40), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_40), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_40), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_40), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_40), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_40), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_40), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_40), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_40), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_40), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_40), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_40), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_40), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_40), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_40), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_40), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_42), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4808_40), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4810_42), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_42), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_42), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_42), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_42), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_42), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_42), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_40), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ CPUFUNC(op_4848_40), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+{ CPUFUNC(op_4850_40), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_40), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_40), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_40), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_40), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_40), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_40), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_40), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_40), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_40), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_40), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_40), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_40), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_40), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_40), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_40), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_40), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_40), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_40), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_40), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_40), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_49c0_40), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4a00_40), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_40), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_40), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_40), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_40), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_40), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_40), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_40), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3a_40), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3b_40), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3c_40), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a40_40), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a48_40), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a50_40), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_40), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_40), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_40), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_40), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_40), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_40), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7a_40), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7b_40), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7c_40), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a80_40), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a88_40), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a90_40), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_40), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_40), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_40), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_40), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_40), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_40), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aba_40), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4abb_40), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4abc_40), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ac0_40), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_40), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_40), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_40), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_40), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_40), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_40), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_40), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4c00_40), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c10_40), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c18_40), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c20_40), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c28_40), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c30_40), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c38_40), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c39_40), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3a_40), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3b_40), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3c_40), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c40_40), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c50_40), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c58_40), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c60_40), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c68_40), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c70_40), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c78_40), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c79_40), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7a_40), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7b_40), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7c_40), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c90_40), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_40), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_40), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_40), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_40), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_40), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_40), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_40), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_40), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_40), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_40), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_40), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_40), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_40), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_40), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_40), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_40), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_40), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_40), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_40), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_40), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_40), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_40), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_40), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_40), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+{ CPUFUNC(op_4e74_40), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+{ CPUFUNC(op_4e75_40), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_40), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_40), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+{ CPUFUNC(op_4e7a_40), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+{ CPUFUNC(op_4e7b_40), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+{ CPUFUNC(op_4e90_40), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_40), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_40), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_40), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_40), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_40), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_40), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_40), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_40), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_40), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_40), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_40), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_40), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_40), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_40), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_40), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_40), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_40), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_40), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_40), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_40), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_40), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_40), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_40), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_40), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_40), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_40), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_40), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_40), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_40), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_40), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_40), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_40), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_40), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_40), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_40), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_40), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_40), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_40), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_40), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_40), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_40), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_40), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_40), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_40), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_40), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_40), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_40), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_40), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50fa_40), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_50fb_40), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_50fc_40), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5100_40), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_40), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_40), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_40), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_40), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_40), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_40), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_40), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_40), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_40), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_40), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_40), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_40), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_40), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_40), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_40), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_40), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_40), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_40), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_40), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_40), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_40), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_40), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_40), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_40), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_40), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_40), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_40), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_40), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_40), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_40), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_40), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_40), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_40), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_40), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51fa_40), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_51fb_40), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_51fc_40), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52c0_40), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_40), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_40), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_40), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_40), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_40), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_40), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_40), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_40), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52fa_40), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52fb_40), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52fc_40), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53c0_40), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_40), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_40), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_40), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_40), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_40), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_40), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_40), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_40), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53fa_40), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53fb_40), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53fc_40), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54c0_40), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_40), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_40), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_40), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_40), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_40), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_40), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_40), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_40), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54fa_40), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54fb_40), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54fc_40), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55c0_40), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_40), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_40), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_40), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_40), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_40), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_40), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_40), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_40), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55fa_40), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55fb_40), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55fc_40), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56c0_40), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_40), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_40), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_40), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_40), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_40), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_40), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_40), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_40), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56fa_40), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56fb_40), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56fc_40), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57c0_40), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_40), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_40), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_40), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_40), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_40), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_40), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_40), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_40), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57fa_40), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57fb_40), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57fc_40), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58c0_40), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_40), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_40), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_40), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_40), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_40), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_40), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_40), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_40), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58fa_40), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58fb_40), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58fc_40), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59c0_40), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_40), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_40), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_40), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_40), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_40), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_40), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_40), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_40), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59fa_40), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59fb_40), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59fc_40), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ac0_40), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_40), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_40), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_40), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_40), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_40), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_40), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_40), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_40), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5afa_40), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5afb_40), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5afc_40), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bc0_40), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_40), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_40), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_40), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_40), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_40), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_40), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_40), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_40), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bfa_40), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bfb_40), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bfc_40), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cc0_40), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_40), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_40), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_40), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_40), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_40), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_40), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_40), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_40), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cfa_40), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cfb_40), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cfc_40), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dc0_40), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_40), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_40), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_40), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_40), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_40), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_40), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_40), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_40), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dfa_40), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dfb_40), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dfc_40), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ec0_40), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_40), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_40), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_40), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_40), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_40), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_40), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_40), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_40), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5efa_40), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5efb_40), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5efc_40), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5fc0_40), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_40), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_40), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_40), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_40), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_40), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_40), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_40), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_40), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ffa_40), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ffb_40), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ffc_40), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_6000_40), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_40), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_40), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6100_40), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_40), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_40), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_40), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_40), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_40), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6300_40), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_40), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_40), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6400_40), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_40), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_40), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6500_40), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_40), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_40), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6600_40), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_40), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_40), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6700_40), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_40), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_40), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6800_40), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_40), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_40), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6900_40), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_40), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_40), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a00_40), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_40), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_40), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b00_40), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_40), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_40), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c00_40), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_40), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_40), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d00_40), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_40), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_40), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e00_40), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_40), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_40), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f00_40), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_40), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_40), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_7000_40), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_40), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_40), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_40), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_40), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_40), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_40), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_40), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_40), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_40), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_40), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_40), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_40), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_40), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_40), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_40), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_40), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_40), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_40), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_40), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_40), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_40), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_40), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_40), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_40), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_40), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_40), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_40), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_40), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_40), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_40), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_40), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_40), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_40), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_40), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_40), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_40), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_40), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_40), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_40), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_40), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_40), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_40), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_40), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_40), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_42), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_42), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_40), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_40), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_40), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_40), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_40), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_40), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_40), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8140_40), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+{ CPUFUNC(op_8148_40), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+{ CPUFUNC(op_8150_40), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_40), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_40), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_40), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_40), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_40), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_40), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8180_40), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+{ CPUFUNC(op_8188_40), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+{ CPUFUNC(op_8190_40), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_40), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_40), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_40), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_40), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_40), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_40), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_40), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_40), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_40), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_40), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_40), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_40), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_40), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_40), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_40), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_40), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_40), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_40), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_40), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_40), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_40), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_40), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_40), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_40), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_40), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_40), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_40), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_40), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_40), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_40), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_40), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_40), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_40), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_40), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_40), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_40), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_40), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_40), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_40), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_40), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_40), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_40), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_40), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_40), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_40), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_40), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_40), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_40), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_40), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_40), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_40), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_40), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_40), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_40), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_40), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_40), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_40), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_40), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_40), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_40), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_40), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_40), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_40), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_40), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_40), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_40), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_40), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_40), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_40), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_40), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_40), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_40), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_40), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_40), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_40), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_40), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_40), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_40), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_40), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_40), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_40), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_40), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_40), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_40), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_40), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_40), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_40), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_40), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_40), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_40), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_40), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_40), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_40), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_40), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_40), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_40), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_40), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_40), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_40), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_40), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_40), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_40), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_40), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_40), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_40), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_40), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_40), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_40), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_40), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_40), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_40), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_40), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_40), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_40), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_40), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_40), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_40), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_40), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_40), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_40), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_40), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_40), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_40), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_40), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_40), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_40), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_40), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_40), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_40), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_40), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_40), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_40), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_40), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_40), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_40), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_40), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_40), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_40), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_40), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_40), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_40), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_40), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_40), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_40), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_40), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_40), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_40), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_40), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_40), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_40), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_40), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_40), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_40), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_40), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_40), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_40), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_40), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_40), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_40), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_40), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_40), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_40), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_40), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_40), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_40), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_40), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_40), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_40), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_40), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_40), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_40), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_40), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_40), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_40), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_40), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_40), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_40), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_40), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_40), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_40), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_40), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_40), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_40), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_40), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_40), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_40), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_40), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_40), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_40), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_40), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_40), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_40), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_40), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_40), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_40), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_40), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_40), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_40), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_40), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_40), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_40), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_40), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_40), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_40), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_40), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_40), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_40), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_40), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_40), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_40), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_40), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_40), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_40), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_40), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_40), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_40), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_40), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_40), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_40), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_40), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_40), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_40), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_40), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_40), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_40), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_40), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_40), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_40), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_40), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_40), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_40), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_40), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_40), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_42), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_42), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_40), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_40), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_40), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_40), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_40), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_40), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_40), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_40), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_40), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_40), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_40), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_40), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_40), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_40), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_40), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_40), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_40), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_40), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_40), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_40), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_40), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_40), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_40), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_40), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_40), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_40), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_40), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_40), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_40), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_40), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_40), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_40), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_40), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_40), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_40), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_40), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_40), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_40), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_40), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_40), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_40), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_40), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_40), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_40), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_40), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_40), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_40), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_40), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_40), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_40), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_40), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_40), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_40), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_40), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_40), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_40), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_40), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_40), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_40), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_40), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_40), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_40), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_40), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_40), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_40), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_40), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_40), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_40), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_40), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_40), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_40), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_40), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_40), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_40), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_40), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_40), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_40), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_40), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_40), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_40), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_40), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_40), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_40), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_40), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_40), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_40), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_40), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_40), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_40), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_40), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_40), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_40), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_40), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_40), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_40), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_40), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_40), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_40), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_40), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_40), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_40), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_40), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_40), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_40), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_40), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_40), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_40), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_40), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_40), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_40), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_40), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_40), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_40), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_40), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_40), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_40), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_40), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_40), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_40), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_40), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_40), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_40), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_40), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_40), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_40), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_40), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_40), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_40), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_40), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_40), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_40), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_40), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_40), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_40), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_40), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_40), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_40), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_40), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_40), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_40), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_40), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_40), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_40), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_40), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_40), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_40), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_40), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_40), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_40), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_40), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_40), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_40), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_40), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_40), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_40), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_40), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_40), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_40), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_40), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_40), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_40), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_40), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_40), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_40), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_40), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_40), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_40), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_40), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_40), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_40), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_40), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_40), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_40), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_40), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_40), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_40), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_40), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_40), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_40), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_40), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_40), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_40), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_40), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_40), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_40), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_40), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_40), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_40), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_40), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_40), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_40), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_40), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_40), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_40), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_40), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_40), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_40), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_40), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_40), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_40), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_40), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_40), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_40), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_40), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_40), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_40), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_40), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_40), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_40), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_40), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_40), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_40), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_40), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_40), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_40), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_40), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_40), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_40), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_40), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_40), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_40), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_40), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_40), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_40), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_40), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e8c0_40), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8d0_40), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8e8_40), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f0_40), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f8_40), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f9_40), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8fa_40), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8fb_40), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e9c0_40), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9d0_40), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9e8_40), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f0_40), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f8_40), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f9_40), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9fa_40), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9fb_40), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_eac0_40), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_ead0_40), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eae8_40), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf0_40), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf8_40), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf9_40), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_ebc0_40), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebd0_40), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebe8_40), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf0_40), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf8_40), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf9_40), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebfa_40), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebfb_40), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ecc0_40), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecd0_40), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ece8_40), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf0_40), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf8_40), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf9_40), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_edc0_40), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edd0_40), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_ede8_40), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf0_40), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf8_40), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf9_40), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edfa_40), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edfb_40), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_eec0_40), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eed0_40), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eee8_40), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef0_40), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef8_40), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef9_40), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_efc0_40), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_efd0_40), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_efe8_40), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff0_40), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff8_40), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff9_40), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_f000_40), 0xf000, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f008_40), 0xf008, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f010_40), 0xf010, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f018_40), 0xf018, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f020_40), 0xf020, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f028_40), 0xf028, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f030_40), 0xf030, -1, { -3, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f038_40), 0xf038, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f039_40), 0xf039, -1, { 0, 0 }, 0 }, /* MMUOP030 */
+{ CPUFUNC(op_f200_40), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f208_40), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f210_40), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f218_40), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f220_40), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f228_40), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f230_40), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f238_40), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f239_40), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23a_40), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23b_40), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23c_40), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f240_40), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f248_40), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+{ CPUFUNC(op_f250_40), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f258_40), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f260_40), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f268_40), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f270_40), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f278_40), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f279_40), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f27a_40), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f27b_40), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f27c_40), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f280_40), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+{ CPUFUNC(op_f2c0_40), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+{ CPUFUNC(op_f310_40), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f320_40), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f328_40), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f330_40), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f338_40), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f339_40), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f350_40), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f358_40), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f368_40), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f370_40), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f378_40), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f379_40), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f37a_40), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f37b_40), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_43)[] = {
+{ CPUFUNC(op_0000_40), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_40), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_40), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_40), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_40), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_40), 0x0030, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_40), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_40), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_40), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_40), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_40), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_40), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_40), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_40), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_40), 0x0070, 4, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_40), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_40), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_40), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_40), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_40), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_40), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_40), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_40), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_40), 0x00b0, 6, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_40), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_40), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00d0_40), 0x00d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00e8_40), 0x00e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f0_40), 0x00f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f8_40), 0x00f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00f9_40), 0x00f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00fa_40), 0x00fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_00fb_40), 0x00fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0100_40), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_40), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_40), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_40), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_40), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_40), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_40), 0x0130, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_40), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_40), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_40), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_40), 0x013b, 2, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_40), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_40), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_40), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_40), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_40), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_40), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_40), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_40), 0x0170, 2, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_40), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_40), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_40), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_40), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_40), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_40), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_40), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_40), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_40), 0x01b0, 2, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_40), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_40), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_40), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_40), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_40), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_40), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_40), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_40), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_40), 0x01f0, 2, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_40), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_40), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_40), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_40), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_40), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_40), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_40), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_40), 0x0230, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_40), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_40), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_40), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_40), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_40), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_40), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_40), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_40), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_40), 0x0270, 4, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_40), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_40), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_40), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_40), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_40), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_40), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_40), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_40), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_40), 0x02b0, 6, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_40), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_40), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02d0_40), 0x02d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02e8_40), 0x02e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f0_40), 0x02f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f8_40), 0x02f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02f9_40), 0x02f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02fa_40), 0x02fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_02fb_40), 0x02fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0400_40), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_40), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_40), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_40), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_40), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_40), 0x0430, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_40), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_40), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_40), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_40), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_40), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_40), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_40), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_40), 0x0470, 4, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_40), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_40), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_40), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_40), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_40), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_40), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_40), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_40), 0x04b0, 6, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_40), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_40), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04d0_40), 0x04d0, 4, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04e8_40), 0x04e8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f0_40), 0x04f0, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f8_40), 0x04f8, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04f9_40), 0x04f9, 8, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04fa_40), 0x04fa, 6, { 0, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_04fb_40), 0x04fb, 4, { 2, 0 }, 0 }, /* CHK2 */
+{ CPUFUNC(op_0600_40), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_40), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_40), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_40), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_40), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_40), 0x0630, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_40), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_40), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_40), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_40), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_40), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_40), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_40), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_40), 0x0670, 4, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_40), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_40), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_40), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_40), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_40), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_40), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_40), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_40), 0x06b0, 6, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_40), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_40), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06c0_40), 0x06c0, 2, { 0, 0 }, 0 }, /* RTM */
+{ CPUFUNC(op_06c8_40), 0x06c8, 2, { 0, 0 }, 0 }, /* RTM */
+{ CPUFUNC(op_06d0_40), 0x06d0, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06e8_40), 0x06e8, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f0_40), 0x06f0, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f8_40), 0x06f8, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06f9_40), 0x06f9, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06fa_40), 0x06fa, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_06fb_40), 0x06fb, 2, { 0, 0 }, 0 }, /* CALLM */
+{ CPUFUNC(op_0800_40), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_40), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_40), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_40), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_40), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_40), 0x0830, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_40), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_40), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_40), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_40), 0x083b, 4, { 2, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_40), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_40), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_40), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_40), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_40), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_40), 0x0870, 4, { 2, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_40), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_40), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_40), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_40), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_40), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_40), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_40), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_40), 0x08b0, 4, { 2, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_40), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_40), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_40), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_40), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_40), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_40), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_40), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_40), 0x08f0, 4, { 2, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_40), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_40), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_40), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_40), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_40), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_40), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_40), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_40), 0x0a30, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_40), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_40), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_40), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_40), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_40), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_40), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_40), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_40), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_40), 0x0a70, 4, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_40), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_40), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_40), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_40), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_40), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_40), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_40), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_40), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_40), 0x0ab0, 6, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_40), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_40), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ad0_40), 0x0ad0, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ad8_40), 0x0ad8, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ae0_40), 0x0ae0, 4, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ae8_40), 0x0ae8, 6, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af0_40), 0x0af0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af8_40), 0x0af8, 6, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0af9_40), 0x0af9, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0c00_40), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_40), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_40), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_40), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_40), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_40), 0x0c30, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_40), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_40), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c3a_40), 0x0c3a, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c3b_40), 0x0c3b, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c40_40), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_40), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_40), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_40), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_40), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_40), 0x0c70, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_40), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_40), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c7a_40), 0x0c7a, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c7b_40), 0x0c7b, 4, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c80_40), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_40), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_40), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_40), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_40), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_40), 0x0cb0, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_40), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_40), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cba_40), 0x0cba, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cbb_40), 0x0cbb, 6, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cd0_40), 0x0cd0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cd8_40), 0x0cd8, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ce0_40), 0x0ce0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ce8_40), 0x0ce8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf0_40), 0x0cf0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf8_40), 0x0cf8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cf9_40), 0x0cf9, 16, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0cfc_40), 0x0cfc, 6, { 0, 0 }, 0 }, /* CAS2 */
+{ CPUFUNC(op_0e10_40), 0x0e10, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e18_40), 0x0e18, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e20_40), 0x0e20, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e28_40), 0x0e28, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e30_40), 0x0e30, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e38_40), 0x0e38, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e39_40), 0x0e39, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e50_40), 0x0e50, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e58_40), 0x0e58, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e60_40), 0x0e60, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e68_40), 0x0e68, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e70_40), 0x0e70, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e78_40), 0x0e78, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e79_40), 0x0e79, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e90_40), 0x0e90, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0e98_40), 0x0e98, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ea0_40), 0x0ea0, 4, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ea8_40), 0x0ea8, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb0_40), 0x0eb0, 8, { 6, 2 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb8_40), 0x0eb8, 6, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0eb9_40), 0x0eb9, 8, { 0, 0 }, 0 }, /* MOVES */
+{ CPUFUNC(op_0ed0_40), 0x0ed0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ed8_40), 0x0ed8, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ee0_40), 0x0ee0, 8, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ee8_40), 0x0ee8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef0_40), 0x0ef0, 4, { 2, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef8_40), 0x0ef8, 12, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0ef9_40), 0x0ef9, 16, { 0, 0 }, 0 }, /* CAS */
+{ CPUFUNC(op_0efc_40), 0x0efc, 6, { 0, 0 }, 0 }, /* CAS2 */
+{ CPUFUNC(op_1000_40), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_40), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_40), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_40), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_40), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_40), 0x1030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_40), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_40), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_40), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_40), 0x103b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_40), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_40), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_40), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_40), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_40), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_40), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_40), 0x10b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_40), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_40), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_40), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_40), 0x10bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_40), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_40), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_40), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_40), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_40), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_40), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_40), 0x10f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_40), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_40), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_40), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_40), 0x10fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_40), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_40), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_40), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_40), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_40), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_40), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_40), 0x1130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_40), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_40), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_40), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_40), 0x113b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_40), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_40), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_40), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_40), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_40), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_40), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_40), 0x1170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_40), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_40), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_40), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_40), 0x117b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_40), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_40), 0x1180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_40), 0x1190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_40), 0x1198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_40), 0x11a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_40), 0x11a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_40), 0x11b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_40), 0x11b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_40), 0x11b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_40), 0x11ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_40), 0x11bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_40), 0x11bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_40), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_40), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_40), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_40), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_40), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_40), 0x11f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_40), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_40), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_40), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_40), 0x11fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_40), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_40), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_40), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_40), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_40), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_40), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_40), 0x13f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_40), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_40), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_40), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_40), 0x13fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_40), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_40), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_40), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_40), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_40), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_40), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_40), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_40), 0x2030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_40), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_40), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_40), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_40), 0x203b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_40), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_40), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_40), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_40), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_40), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_40), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_40), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_40), 0x2070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_40), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_40), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_40), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_40), 0x207b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_40), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_40), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_40), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_40), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_40), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_40), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_40), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_40), 0x20b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_40), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_40), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_40), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_40), 0x20bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_40), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_40), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_40), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_40), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_40), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_40), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_40), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_40), 0x20f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_40), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_40), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_40), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_40), 0x20fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_40), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_40), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_40), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_40), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_40), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_40), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_40), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_40), 0x2130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_40), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_40), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_40), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_40), 0x213b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_40), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_40), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_40), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_40), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_40), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_40), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_40), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_40), 0x2170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_40), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_40), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_40), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_40), 0x217b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_40), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_40), 0x2180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_40), 0x2188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_40), 0x2190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_40), 0x2198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_40), 0x21a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_40), 0x21a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_40), 0x21b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_40), 0x21b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_40), 0x21b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_40), 0x21ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_40), 0x21bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_40), 0x21bc, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_40), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_40), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_40), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_40), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_40), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_40), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_40), 0x21f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_40), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_40), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_40), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_40), 0x21fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_40), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_40), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_40), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_40), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_40), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_40), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_40), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_40), 0x23f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_40), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_40), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_40), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_40), 0x23fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_40), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_40), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_40), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_40), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_40), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_40), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_40), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_40), 0x3030, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_40), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_40), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_40), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_40), 0x303b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_40), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_40), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_40), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_40), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_40), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_40), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_40), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_40), 0x3070, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_40), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_40), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_40), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_40), 0x307b, 2, { 2, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_40), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_40), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_40), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_40), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_40), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_40), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_40), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_40), 0x30b0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_40), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_40), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_40), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_40), 0x30bb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_40), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_40), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_40), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_40), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_40), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_40), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_40), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_40), 0x30f0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_40), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_40), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_40), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_40), 0x30fb, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_40), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_40), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_40), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_40), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_40), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_40), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_40), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_40), 0x3130, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_40), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_40), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_40), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_40), 0x313b, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_40), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_40), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_40), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_40), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_40), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_40), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_40), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_40), 0x3170, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_40), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_40), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_40), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_40), 0x317b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_40), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_40), 0x3180, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_40), 0x3188, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_40), 0x3190, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_40), 0x3198, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_40), 0x31a0, 2, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_40), 0x31a8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_40), 0x31b0, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_40), 0x31b8, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_40), 0x31b9, 6, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_40), 0x31ba, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_40), 0x31bb, 2, { 2, 2 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_40), 0x31bc, 4, { 2, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_40), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_40), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_40), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_40), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_40), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_40), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_40), 0x31f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_40), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_40), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_40), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_40), 0x31fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_40), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_40), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_40), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_40), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_40), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_40), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_40), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_40), 0x33f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_40), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_40), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_40), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_40), 0x33fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_40), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_40), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_40), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_40), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_40), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_40), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_40), 0x4030, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_40), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_40), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_40), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_40), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_40), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_40), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_40), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_40), 0x4070, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_40), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_40), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_40), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_40), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_40), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_40), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_40), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_40), 0x40b0, 2, { 2, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_40), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_40), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_40), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_40), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_40), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_40), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_40), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_40), 0x40f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_40), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_40), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4100_40), 0x4100, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4110_40), 0x4110, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4118_40), 0x4118, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4120_40), 0x4120, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4128_40), 0x4128, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4130_40), 0x4130, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4138_40), 0x4138, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4139_40), 0x4139, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413a_40), 0x413a, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413b_40), 0x413b, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_413c_40), 0x413c, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4180_40), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_40), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_40), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_40), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_40), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_40), 0x41b0, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_40), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_40), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_40), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_40), 0x41bb, 2, { 2, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_40), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_40), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_40), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_40), 0x41f0, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_40), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_40), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_40), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_40), 0x41fb, 2, { 2, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_40), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_40), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_40), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_40), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_40), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_40), 0x4230, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_40), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_40), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_40), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_40), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_40), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_40), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_40), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_40), 0x4270, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_40), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_40), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_40), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_40), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_40), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_40), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_40), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_40), 0x42b0, 2, { 2, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_40), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_40), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42c0_40), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d0_40), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d8_40), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e0_40), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e8_40), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f0_40), 0x42f0, 2, { 2, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f8_40), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f9_40), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4400_40), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_40), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_40), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_40), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_40), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_40), 0x4430, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_40), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_40), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_40), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_40), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_40), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_40), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_40), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_40), 0x4470, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_40), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_40), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_40), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_40), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_40), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_40), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_40), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_40), 0x44b0, 2, { 2, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_40), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_40), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_40), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_40), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_40), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_40), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_40), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_40), 0x44f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_40), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_40), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_40), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_40), 0x44fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_40), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_40), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_40), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_40), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_40), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_40), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_40), 0x4630, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_40), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_40), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_40), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_40), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_40), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_40), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_40), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_40), 0x4670, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_40), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_40), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_40), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_40), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_40), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_40), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_40), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_40), 0x46b0, 2, { 2, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_40), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_40), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_40), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_40), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_40), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_40), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_40), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_40), 0x46f0, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_40), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_40), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_40), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_40), 0x46fb, 2, { 2, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_40), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_42), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4808_40), 0x4808, 6, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4810_42), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_42), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_42), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_42), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_42), 0x4830, 2, { 2, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_42), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_42), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_40), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ CPUFUNC(op_4848_40), 0x4848, 2, { 0, 0 }, 0 }, /* BKPT */
+{ CPUFUNC(op_4850_40), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_40), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_40), 0x4870, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_40), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_40), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_40), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_40), 0x487b, 2, { 2, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_40), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_40), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_40), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_40), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_40), 0x48b0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_40), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_40), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_40), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_40), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_40), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_40), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_40), 0x48f0, 4, { 2, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_40), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_40), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_49c0_40), 0x49c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4a00_40), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_40), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_40), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_40), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_40), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_40), 0x4a30, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_40), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_40), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3a_40), 0x4a3a, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3b_40), 0x4a3b, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a3c_40), 0x4a3c, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a40_40), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a48_40), 0x4a48, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a50_40), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_40), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_40), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_40), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_40), 0x4a70, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_40), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_40), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7a_40), 0x4a7a, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7b_40), 0x4a7b, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a7c_40), 0x4a7c, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a80_40), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a88_40), 0x4a88, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a90_40), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_40), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_40), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_40), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_40), 0x4ab0, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_40), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_40), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aba_40), 0x4aba, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4abb_40), 0x4abb, 2, { 2, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4abc_40), 0x4abc, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ac0_40), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_40), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_40), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_40), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_40), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_40), 0x4af0, 2, { 2, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_40), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_40), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4c00_40), 0x4c00, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c10_40), 0x4c10, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c18_40), 0x4c18, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c20_40), 0x4c20, 4, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c28_40), 0x4c28, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c30_40), 0x4c30, 4, { 2, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c38_40), 0x4c38, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c39_40), 0x4c39, 8, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3a_40), 0x4c3a, 6, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3b_40), 0x4c3b, 4, { 2, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c3c_40), 0x4c3c, 8, { 0, 0 }, 0 }, /* MULL */
+{ CPUFUNC(op_4c40_40), 0x4c40, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c50_40), 0x4c50, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c58_40), 0x4c58, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c60_40), 0x4c60, 4, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c68_40), 0x4c68, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c70_40), 0x4c70, 4, { 2, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c78_40), 0x4c78, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c79_40), 0x4c79, 8, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7a_40), 0x4c7a, 6, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7b_40), 0x4c7b, 4, { 2, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c7c_40), 0x4c7c, 8, { 0, 0 }, 0 }, /* DIVL */
+{ CPUFUNC(op_4c90_40), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_40), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_40), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_40), 0x4cb0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_40), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_40), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_40), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_40), 0x4cbb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_40), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_40), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_40), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_40), 0x4cf0, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_40), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_40), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_40), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_40), 0x4cfb, 4, { 2, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_40), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_40), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_40), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_40), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_40), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_40), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_40), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_40), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_40), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+{ CPUFUNC(op_4e74_40), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+{ CPUFUNC(op_4e75_40), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_40), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_40), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+{ CPUFUNC(op_4e7a_40), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+{ CPUFUNC(op_4e7b_40), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+{ CPUFUNC(op_4e90_40), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_40), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_40), 0x4eb0, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_40), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_40), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_40), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_40), 0x4ebb, 2, { 2, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_40), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_40), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_40), 0x4ef0, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_40), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_40), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_40), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_40), 0x4efb, 2, { 2, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_40), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_40), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_40), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_40), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_40), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_40), 0x5030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_40), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_40), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_40), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_40), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_40), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_40), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_40), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_40), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_40), 0x5070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_40), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_40), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_40), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_40), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_40), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_40), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_40), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_40), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_40), 0x50b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_40), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_40), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_40), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_40), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_40), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_40), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_40), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_40), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_40), 0x50f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_40), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_40), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50fa_40), 0x50fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_50fb_40), 0x50fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_50fc_40), 0x50fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5100_40), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_40), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_40), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_40), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_40), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_40), 0x5130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_40), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_40), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_40), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_40), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_40), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_40), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_40), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_40), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_40), 0x5170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_40), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_40), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_40), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_40), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_40), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_40), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_40), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_40), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_40), 0x51b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_40), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_40), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_40), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_40), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_40), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_40), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_40), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_40), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_40), 0x51f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_40), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_40), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51fa_40), 0x51fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_51fb_40), 0x51fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_51fc_40), 0x51fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52c0_40), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_40), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_40), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_40), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_40), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_40), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_40), 0x52f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_40), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_40), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52fa_40), 0x52fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52fb_40), 0x52fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_52fc_40), 0x52fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53c0_40), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_40), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_40), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_40), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_40), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_40), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_40), 0x53f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_40), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_40), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53fa_40), 0x53fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53fb_40), 0x53fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_53fc_40), 0x53fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54c0_40), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_40), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_40), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_40), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_40), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_40), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_40), 0x54f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_40), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_40), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54fa_40), 0x54fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54fb_40), 0x54fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_54fc_40), 0x54fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55c0_40), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_40), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_40), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_40), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_40), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_40), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_40), 0x55f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_40), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_40), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55fa_40), 0x55fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55fb_40), 0x55fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_55fc_40), 0x55fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56c0_40), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_40), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_40), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_40), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_40), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_40), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_40), 0x56f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_40), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_40), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56fa_40), 0x56fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56fb_40), 0x56fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_56fc_40), 0x56fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57c0_40), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_40), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_40), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_40), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_40), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_40), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_40), 0x57f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_40), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_40), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57fa_40), 0x57fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57fb_40), 0x57fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_57fc_40), 0x57fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58c0_40), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_40), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_40), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_40), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_40), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_40), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_40), 0x58f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_40), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_40), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58fa_40), 0x58fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58fb_40), 0x58fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_58fc_40), 0x58fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59c0_40), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_40), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_40), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_40), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_40), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_40), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_40), 0x59f0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_40), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_40), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59fa_40), 0x59fa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59fb_40), 0x59fb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_59fc_40), 0x59fc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ac0_40), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_40), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_40), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_40), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_40), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_40), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_40), 0x5af0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_40), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_40), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5afa_40), 0x5afa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5afb_40), 0x5afb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5afc_40), 0x5afc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bc0_40), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_40), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_40), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_40), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_40), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_40), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_40), 0x5bf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_40), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_40), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bfa_40), 0x5bfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bfb_40), 0x5bfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5bfc_40), 0x5bfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cc0_40), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_40), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_40), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_40), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_40), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_40), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_40), 0x5cf0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_40), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_40), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cfa_40), 0x5cfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cfb_40), 0x5cfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5cfc_40), 0x5cfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dc0_40), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_40), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_40), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_40), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_40), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_40), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_40), 0x5df0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_40), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_40), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dfa_40), 0x5dfa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dfb_40), 0x5dfb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5dfc_40), 0x5dfc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ec0_40), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_40), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_40), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_40), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_40), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_40), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_40), 0x5ef0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_40), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_40), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5efa_40), 0x5efa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5efb_40), 0x5efb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5efc_40), 0x5efc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5fc0_40), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_40), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_40), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_40), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_40), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_40), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_40), 0x5ff0, 2, { 2, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_40), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_40), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ffa_40), 0x5ffa, 4, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ffb_40), 0x5ffb, 6, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_5ffc_40), 0x5ffc, 2, { 0, 0 }, 0 }, /* TRAPcc */
+{ CPUFUNC(op_6000_40), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_40), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_40), 0x60ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6100_40), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_40), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_40), 0x61ff, 6, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_40), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_40), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_40), 0x62ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6300_40), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_40), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_40), 0x63ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6400_40), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_40), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_40), 0x64ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6500_40), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_40), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_40), 0x65ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6600_40), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_40), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_40), 0x66ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6700_40), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_40), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_40), 0x67ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6800_40), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_40), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_40), 0x68ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6900_40), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_40), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_40), 0x69ff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a00_40), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_40), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_40), 0x6aff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b00_40), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_40), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_40), 0x6bff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c00_40), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_40), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_40), 0x6cff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d00_40), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_40), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_40), 0x6dff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e00_40), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_40), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_40), 0x6eff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f00_40), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_40), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_40), 0x6fff, 6, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_7000_40), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_40), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_40), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_40), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_40), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_40), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_40), 0x8030, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_40), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_40), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_40), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_40), 0x803b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_40), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_40), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_40), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_40), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_40), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_40), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_40), 0x8070, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_40), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_40), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_40), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_40), 0x807b, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_40), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_40), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_40), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_40), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_40), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_40), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_40), 0x80b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_40), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_40), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_40), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_40), 0x80bb, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_40), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_40), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_40), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_40), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_40), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_40), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_40), 0x80f0, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_40), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_40), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_40), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_40), 0x80fb, 2, { 2, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_40), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_42), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_42), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_40), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_40), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_40), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_40), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_40), 0x8130, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_40), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_40), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8140_40), 0x8140, 4, { 0, 0 }, 0 }, /* PACK */
+{ CPUFUNC(op_8148_40), 0x8148, 4, { 0, 0 }, 0 }, /* PACK */
+{ CPUFUNC(op_8150_40), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_40), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_40), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_40), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_40), 0x8170, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_40), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_40), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8180_40), 0x8180, 4, { 0, 0 }, 0 }, /* UNPK */
+{ CPUFUNC(op_8188_40), 0x8188, 4, { 0, 0 }, 0 }, /* UNPK */
+{ CPUFUNC(op_8190_40), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_40), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_40), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_40), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_40), 0x81b0, 2, { 2, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_40), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_40), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_40), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_40), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_40), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_40), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_40), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_40), 0x81f0, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_40), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_40), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_40), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_40), 0x81fb, 2, { 2, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_40), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_40), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_40), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_40), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_40), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_40), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_40), 0x9030, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_40), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_40), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_40), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_40), 0x903b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_40), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_40), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_40), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_40), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_40), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_40), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_40), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_40), 0x9070, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_40), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_40), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_40), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_40), 0x907b, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_40), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_40), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_40), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_40), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_40), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_40), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_40), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_40), 0x90b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_40), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_40), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_40), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_40), 0x90bb, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_40), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_40), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_40), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_40), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_40), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_40), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_40), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_40), 0x90f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_40), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_40), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_40), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_40), 0x90fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_40), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_40), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_40), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_40), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_40), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_40), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_40), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_40), 0x9130, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_40), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_40), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_40), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_40), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_40), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_40), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_40), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_40), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_40), 0x9170, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_40), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_40), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_40), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_40), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_40), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_40), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_40), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_40), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_40), 0x91b0, 2, { 2, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_40), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_40), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_40), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_40), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_40), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_40), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_40), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_40), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_40), 0x91f0, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_40), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_40), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_40), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_40), 0x91fb, 2, { 2, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_40), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_40), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_40), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_40), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_40), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_40), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_40), 0xb030, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_40), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_40), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_40), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_40), 0xb03b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_40), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_40), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_40), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_40), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_40), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_40), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_40), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_40), 0xb070, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_40), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_40), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_40), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_40), 0xb07b, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_40), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_40), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_40), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_40), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_40), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_40), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_40), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_40), 0xb0b0, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_40), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_40), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_40), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_40), 0xb0bb, 2, { 2, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_40), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_40), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_40), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_40), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_40), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_40), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_40), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_40), 0xb0f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_40), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_40), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_40), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_40), 0xb0fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_40), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_40), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_40), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_40), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_40), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_40), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_40), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_40), 0xb130, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_40), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_40), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_40), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_40), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_40), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_40), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_40), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_40), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_40), 0xb170, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_40), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_40), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_40), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_40), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_40), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_40), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_40), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_40), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_40), 0xb1b0, 2, { 2, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_40), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_40), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_40), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_40), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_40), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_40), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_40), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_40), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_40), 0xb1f0, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_40), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_40), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_40), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_40), 0xb1fb, 2, { 2, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_40), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_40), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_40), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_40), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_40), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_40), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_40), 0xc030, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_40), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_40), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_40), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_40), 0xc03b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_40), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_40), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_40), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_40), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_40), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_40), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_40), 0xc070, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_40), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_40), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_40), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_40), 0xc07b, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_40), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_40), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_40), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_40), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_40), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_40), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_40), 0xc0b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_40), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_40), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_40), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_40), 0xc0bb, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_40), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_40), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_40), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_40), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_40), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_40), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_40), 0xc0f0, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_40), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_40), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_40), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_40), 0xc0fb, 2, { 2, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_40), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_42), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_42), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_40), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_40), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_40), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_40), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_40), 0xc130, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_40), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_40), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_40), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_40), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_40), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_40), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_40), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_40), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_40), 0xc170, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_40), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_40), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_40), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_40), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_40), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_40), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_40), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_40), 0xc1b0, 2, { 2, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_40), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_40), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_40), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_40), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_40), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_40), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_40), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_40), 0xc1f0, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_40), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_40), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_40), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_40), 0xc1fb, 2, { 2, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_40), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_40), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_40), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_40), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_40), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_40), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_40), 0xd030, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_40), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_40), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_40), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_40), 0xd03b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_40), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_40), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_40), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_40), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_40), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_40), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_40), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_40), 0xd070, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_40), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_40), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_40), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_40), 0xd07b, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_40), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_40), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_40), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_40), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_40), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_40), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_40), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_40), 0xd0b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_40), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_40), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_40), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_40), 0xd0bb, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_40), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_40), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_40), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_40), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_40), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_40), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_40), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_40), 0xd0f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_40), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_40), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_40), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_40), 0xd0fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_40), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_40), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_40), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_40), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_40), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_40), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_40), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_40), 0xd130, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_40), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_40), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_40), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_40), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_40), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_40), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_40), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_40), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_40), 0xd170, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_40), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_40), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_40), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_40), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_40), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_40), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_40), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_40), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_40), 0xd1b0, 2, { 2, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_40), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_40), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_40), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_40), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_40), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_40), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_40), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_40), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_40), 0xd1f0, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_40), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_40), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_40), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_40), 0xd1fb, 2, { 2, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_40), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_40), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_40), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_40), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_40), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_40), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_40), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_40), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_40), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_40), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_40), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_40), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_40), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_40), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_40), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_40), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_40), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_40), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_40), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_40), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_40), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_40), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_40), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_40), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_40), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_40), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_40), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_40), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_40), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_40), 0xe0f0, 2, { 2, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_40), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_40), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_40), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_40), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_40), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_40), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_40), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_40), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_40), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_40), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_40), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_40), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_40), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_40), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_40), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_40), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_40), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_40), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_40), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_40), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_40), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_40), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_40), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_40), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_40), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_40), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_40), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_40), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_40), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_40), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_40), 0xe1f0, 2, { 2, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_40), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_40), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_40), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_40), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_40), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_40), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_40), 0xe2f0, 2, { 2, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_40), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_40), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_40), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_40), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_40), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_40), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_40), 0xe3f0, 2, { 2, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_40), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_40), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_40), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_40), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_40), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_40), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_40), 0xe4f0, 2, { 2, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_40), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_40), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_40), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_40), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_40), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_40), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_40), 0xe5f0, 2, { 2, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_40), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_40), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_40), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_40), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_40), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_40), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_40), 0xe6f0, 2, { 2, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_40), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_40), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_40), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_40), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_40), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_40), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_40), 0xe7f0, 2, { 2, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_40), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_40), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e8c0_40), 0xe8c0, 4, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8d0_40), 0xe8d0, 4, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8e8_40), 0xe8e8, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f0_40), 0xe8f0, 4, { 2, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f8_40), 0xe8f8, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8f9_40), 0xe8f9, 8, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8fa_40), 0xe8fa, 6, { 0, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e8fb_40), 0xe8fb, 4, { 2, 0 }, 0 }, /* BFTST */
+{ CPUFUNC(op_e9c0_40), 0xe9c0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9d0_40), 0xe9d0, 4, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9e8_40), 0xe9e8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f0_40), 0xe9f0, 4, { 2, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f8_40), 0xe9f8, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9f9_40), 0xe9f9, 8, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9fa_40), 0xe9fa, 6, { 0, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_e9fb_40), 0xe9fb, 4, { 2, 0 }, 0 }, /* BFEXTU */
+{ CPUFUNC(op_eac0_40), 0xeac0, 4, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_ead0_40), 0xead0, 4, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eae8_40), 0xeae8, 6, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf0_40), 0xeaf0, 4, { 2, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf8_40), 0xeaf8, 6, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_eaf9_40), 0xeaf9, 8, { 0, 0 }, 0 }, /* BFCHG */
+{ CPUFUNC(op_ebc0_40), 0xebc0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebd0_40), 0xebd0, 4, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebe8_40), 0xebe8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf0_40), 0xebf0, 4, { 2, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf8_40), 0xebf8, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebf9_40), 0xebf9, 8, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebfa_40), 0xebfa, 6, { 0, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ebfb_40), 0xebfb, 4, { 2, 0 }, 0 }, /* BFEXTS */
+{ CPUFUNC(op_ecc0_40), 0xecc0, 4, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecd0_40), 0xecd0, 4, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ece8_40), 0xece8, 6, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf0_40), 0xecf0, 4, { 2, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf8_40), 0xecf8, 6, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_ecf9_40), 0xecf9, 8, { 0, 0 }, 0 }, /* BFCLR */
+{ CPUFUNC(op_edc0_40), 0xedc0, 4, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edd0_40), 0xedd0, 4, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_ede8_40), 0xede8, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf0_40), 0xedf0, 4, { 2, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf8_40), 0xedf8, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edf9_40), 0xedf9, 8, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edfa_40), 0xedfa, 6, { 0, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_edfb_40), 0xedfb, 4, { 2, 0 }, 0 }, /* BFFFO */
+{ CPUFUNC(op_eec0_40), 0xeec0, 4, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eed0_40), 0xeed0, 4, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eee8_40), 0xeee8, 6, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef0_40), 0xeef0, 4, { 2, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef8_40), 0xeef8, 6, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_eef9_40), 0xeef9, 8, { 0, 0 }, 0 }, /* BFSET */
+{ CPUFUNC(op_efc0_40), 0xefc0, 4, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_efd0_40), 0xefd0, 4, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_efe8_40), 0xefe8, 6, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff0_40), 0xeff0, 4, { 2, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff8_40), 0xeff8, 6, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_eff9_40), 0xeff9, 8, { 0, 0 }, 0 }, /* BFINS */
+{ CPUFUNC(op_f200_40), 0xf200, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f208_40), 0xf208, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f210_40), 0xf210, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f218_40), 0xf218, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f220_40), 0xf220, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f228_40), 0xf228, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f230_40), 0xf230, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f238_40), 0xf238, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f239_40), 0xf239, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23a_40), 0xf23a, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23b_40), 0xf23b, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f23c_40), 0xf23c, -1, { 0, 0 }, 0 }, /* FPP */
+{ CPUFUNC(op_f240_40), 0xf240, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f248_40), 0xf248, -1, { 0, 0 }, 0 }, /* FDBcc */
+{ CPUFUNC(op_f250_40), 0xf250, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f258_40), 0xf258, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f260_40), 0xf260, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f268_40), 0xf268, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f270_40), 0xf270, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f278_40), 0xf278, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f279_40), 0xf279, -1, { 0, 0 }, 0 }, /* FScc */
+{ CPUFUNC(op_f27a_40), 0xf27a, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f27b_40), 0xf27b, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f27c_40), 0xf27c, -1, { 0, 0 }, 0 }, /* FTRAPcc */
+{ CPUFUNC(op_f280_40), 0xf280, -1, { 0, 0 }, 0 }, /* FBcc */
+{ CPUFUNC(op_f2c0_40), 0xf2c0, -1, { 0, 0 }, 0 }, /* FBcc */
+{ CPUFUNC(op_f310_40), 0xf310, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f320_40), 0xf320, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f328_40), 0xf328, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f330_40), 0xf330, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f338_40), 0xf338, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f339_40), 0xf339, -1, { 0, 0 }, 0 }, /* FSAVE */
+{ CPUFUNC(op_f350_40), 0xf350, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f358_40), 0xf358, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f368_40), 0xf368, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f370_40), 0xf370, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f378_40), 0xf378, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f379_40), 0xf379, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f37a_40), 0xf37a, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ CPUFUNC(op_f37b_40), 0xf37b, -1, { 0, 0 }, 0 }, /* FRESTORE */
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_44)[] = {
+{ CPUFUNC(op_0000_40), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_40), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_40), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_40), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_40), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_44), 0x0030, 6, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_40), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_40), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_40), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_40), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_40), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_40), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_40), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_40), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_44), 0x0070, 6, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_40), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_40), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_40), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_40), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_40), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_40), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_40), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_40), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_44), 0x00b0, 8, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_40), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_40), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0100_40), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_40), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_40), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_40), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_40), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_40), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_44), 0x0130, 4, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_40), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_40), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_40), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_44), 0x013b, 4, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_40), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_40), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_40), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_40), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_40), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_40), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_40), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_44), 0x0170, 4, { 4, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_40), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_40), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_40), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_40), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_40), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_40), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_40), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_40), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_44), 0x01b0, 4, { 4, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_40), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_40), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_40), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_40), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_40), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_40), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_40), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_40), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_44), 0x01f0, 4, { 4, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_40), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_40), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_40), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_40), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_40), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_40), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_40), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_44), 0x0230, 6, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_40), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_40), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_40), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_40), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_40), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_40), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_40), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_40), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_44), 0x0270, 6, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_40), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_40), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_40), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_40), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_40), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_40), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_40), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_40), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_44), 0x02b0, 8, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_40), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_40), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0400_40), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_40), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_40), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_40), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_40), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_44), 0x0430, 6, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_40), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_40), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_40), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_40), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_40), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_40), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_40), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_44), 0x0470, 6, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_40), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_40), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_40), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_40), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_40), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_40), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_40), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_44), 0x04b0, 8, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_40), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_40), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0600_40), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_40), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_40), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_40), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_40), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_44), 0x0630, 6, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_40), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_40), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_40), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_40), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_40), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_40), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_40), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_44), 0x0670, 6, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_40), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_40), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_40), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_40), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_40), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_40), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_40), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_44), 0x06b0, 8, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_40), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_40), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0800_40), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_40), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_40), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_40), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_40), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_44), 0x0830, 6, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_40), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_40), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_40), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_44), 0x083b, 6, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_40), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_40), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_40), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_40), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_40), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_44), 0x0870, 6, { 4, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_40), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_40), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_40), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_40), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_40), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_40), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_40), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_44), 0x08b0, 6, { 4, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_40), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_40), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_40), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_40), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_40), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_40), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_40), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_44), 0x08f0, 6, { 4, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_40), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_40), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_40), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_40), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_40), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_40), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_40), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_44), 0x0a30, 6, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_40), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_40), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_40), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_40), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_40), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_40), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_40), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_40), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_44), 0x0a70, 6, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_40), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_40), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_40), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_40), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_40), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_40), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_40), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_40), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_44), 0x0ab0, 8, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_40), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_40), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0c00_40), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_40), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_40), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_40), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_40), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_44), 0x0c30, 6, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_40), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_40), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c40_40), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_40), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_40), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_40), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_40), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_44), 0x0c70, 6, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_40), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_40), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c80_40), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_40), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_40), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_40), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_40), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_44), 0x0cb0, 8, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_40), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_40), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_1000_40), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_40), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_40), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_40), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_40), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_44), 0x1030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_40), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_40), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_40), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_44), 0x103b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_40), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_40), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_40), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_40), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_40), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_40), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_44), 0x10b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_40), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_40), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_40), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_44), 0x10bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_40), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_40), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_40), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_40), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_40), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_40), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_44), 0x10f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_40), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_40), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_40), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_44), 0x10fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_40), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_40), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_40), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_40), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_40), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_40), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_44), 0x1130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_40), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_40), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_40), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_44), 0x113b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_40), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_40), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_40), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_40), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_40), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_40), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_44), 0x1170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_40), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_40), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_40), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_44), 0x117b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_40), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_44), 0x1180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_44), 0x1190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_44), 0x1198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_44), 0x11a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_44), 0x11a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_44), 0x11b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_44), 0x11b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_44), 0x11b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_44), 0x11ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_44), 0x11bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_44), 0x11bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_40), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_40), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_40), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_40), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_40), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_44), 0x11f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_40), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_40), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_40), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_44), 0x11fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_40), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_40), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_40), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_40), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_40), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_40), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_44), 0x13f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_40), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_40), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_40), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_44), 0x13fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_40), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_40), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_40), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_40), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_40), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_40), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_40), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_44), 0x2030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_40), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_40), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_40), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_44), 0x203b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_40), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_40), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_40), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_40), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_40), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_40), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_40), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_44), 0x2070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_40), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_40), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_40), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_44), 0x207b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_40), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_40), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_40), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_40), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_40), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_40), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_40), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_44), 0x20b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_40), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_40), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_40), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_44), 0x20bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_40), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_40), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_40), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_40), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_40), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_40), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_40), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_44), 0x20f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_40), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_40), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_40), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_44), 0x20fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_40), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_40), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_40), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_40), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_40), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_40), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_40), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_44), 0x2130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_40), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_40), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_40), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_44), 0x213b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_40), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_40), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_40), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_40), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_40), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_40), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_40), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_44), 0x2170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_40), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_40), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_40), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_44), 0x217b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_40), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_44), 0x2180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_44), 0x2188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_44), 0x2190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_44), 0x2198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_44), 0x21a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_44), 0x21a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_44), 0x21b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_44), 0x21b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_44), 0x21b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_44), 0x21ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_44), 0x21bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_44), 0x21bc, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_40), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_40), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_40), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_40), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_40), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_40), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_44), 0x21f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_40), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_40), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_40), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_44), 0x21fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_40), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_40), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_40), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_40), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_40), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_40), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_40), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_44), 0x23f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_40), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_40), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_40), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_44), 0x23fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_40), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_40), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_40), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_40), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_40), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_40), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_40), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_44), 0x3030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_40), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_40), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_40), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_44), 0x303b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_40), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_40), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_40), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_40), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_40), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_40), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_40), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_44), 0x3070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_40), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_40), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_40), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_44), 0x307b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_40), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_40), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_40), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_40), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_40), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_40), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_40), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_44), 0x30b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_40), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_40), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_40), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_44), 0x30bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_40), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_40), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_40), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_40), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_40), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_40), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_40), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_44), 0x30f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_40), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_40), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_40), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_44), 0x30fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_40), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_40), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_40), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_40), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_40), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_40), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_40), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_44), 0x3130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_40), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_40), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_40), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_44), 0x313b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_40), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_40), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_40), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_40), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_40), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_40), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_40), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_44), 0x3170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_40), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_40), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_40), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_44), 0x317b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_40), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_44), 0x3180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_44), 0x3188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_44), 0x3190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_44), 0x3198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_44), 0x31a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_44), 0x31a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_44), 0x31b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_44), 0x31b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_44), 0x31b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_44), 0x31ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_44), 0x31bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_44), 0x31bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_40), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_40), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_40), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_40), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_40), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_40), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_44), 0x31f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_40), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_40), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_40), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_44), 0x31fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_40), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_40), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_40), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_40), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_40), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_40), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_40), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_44), 0x33f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_40), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_40), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_40), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_44), 0x33fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_40), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_40), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_40), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_40), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_40), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_40), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_44), 0x4030, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_40), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_40), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_40), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_40), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_40), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_40), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_40), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_44), 0x4070, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_40), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_40), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_40), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_40), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_40), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_40), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_40), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_44), 0x40b0, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_40), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_40), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_40), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_40), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_40), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_40), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_40), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_44), 0x40f0, 4, { 4, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_40), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_40), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4180_40), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_40), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_40), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_40), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_40), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_44), 0x41b0, 4, { 4, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_40), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_40), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_40), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_44), 0x41bb, 4, { 4, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_40), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_40), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_40), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_44), 0x41f0, 4, { 4, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_40), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_40), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_40), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_44), 0x41fb, 4, { 4, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_40), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_40), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_40), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_40), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_40), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_44), 0x4230, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_40), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_40), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_40), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_40), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_40), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_40), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_40), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_44), 0x4270, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_40), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_40), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_40), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_40), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_40), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_40), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_40), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_44), 0x42b0, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_40), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_40), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42c0_40), 0x42c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d0_40), 0x42d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42d8_40), 0x42d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e0_40), 0x42e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42e8_40), 0x42e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+#ifndef CPUEMU_68000_ONLY
+{ CPUFUNC(op_42f0_44), 0x42f0, 4, { 4, 0 }, 0 }, /* MVSR2 */
+#endif
+{ CPUFUNC(op_42f8_40), 0x42f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_42f9_40), 0x42f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4400_40), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_40), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_40), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_40), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_40), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_44), 0x4430, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_40), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_40), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_40), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_40), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_40), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_40), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_40), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_44), 0x4470, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_40), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_40), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_40), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_40), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_40), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_40), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_40), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_44), 0x44b0, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_40), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_40), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_40), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_40), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_40), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_40), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_40), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_44), 0x44f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_40), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_40), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_40), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_44), 0x44fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_40), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_40), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_40), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_40), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_40), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_40), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_44), 0x4630, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_40), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_40), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_40), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_40), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_40), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_40), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_40), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_44), 0x4670, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_40), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_40), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_40), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_40), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_40), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_40), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_40), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_44), 0x46b0, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_40), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_40), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_40), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_40), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_40), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_40), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_40), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_44), 0x46f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_40), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_40), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_40), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_44), 0x46fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_40), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_42), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4810_42), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_42), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_42), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_42), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_44), 0x4830, 4, { 4, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_42), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_42), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_40), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ CPUFUNC(op_4850_40), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_40), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_44), 0x4870, 4, { 4, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_40), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_40), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_40), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_44), 0x487b, 4, { 4, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_40), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_40), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_40), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_40), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_44), 0x48b0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_40), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_40), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_40), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_40), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_40), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_40), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_44), 0x48f0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_40), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_40), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_4a00_40), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_40), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_40), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_40), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_40), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_44), 0x4a30, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_40), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_40), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a40_40), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a50_40), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_40), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_40), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_40), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_44), 0x4a70, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_40), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_40), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a80_40), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a90_40), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_40), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_40), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_40), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_44), 0x4ab0, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_40), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_40), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ac0_44), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_44), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_44), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_44), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_44), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_44), 0x4af0, 4, { 4, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_44), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_44), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4c90_40), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_40), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_40), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_44), 0x4cb0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_40), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_40), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_40), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_44), 0x4cbb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_40), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_40), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_40), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_44), 0x4cf0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_40), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_40), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_40), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_44), 0x4cfb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_40), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_40), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_40), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_40), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_40), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_40), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_40), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_40), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_40), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+{ CPUFUNC(op_4e74_40), 0x4e74, 4, { 0, 0 }, 1 }, /* RTD */
+{ CPUFUNC(op_4e75_40), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_40), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_40), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+{ CPUFUNC(op_4e7a_40), 0x4e7a, 4, { 0, 0 }, 0 }, /* MOVEC2 */
+{ CPUFUNC(op_4e7b_40), 0x4e7b, 4, { 0, 0 }, 0 }, /* MOVE2C */
+{ CPUFUNC(op_4e90_40), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_40), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_44), 0x4eb0, 4, { 4, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_40), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_40), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_40), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_44), 0x4ebb, 4, { 4, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_40), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_40), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_44), 0x4ef0, 4, { 4, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_40), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_40), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_40), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_44), 0x4efb, 4, { 4, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_40), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_40), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_40), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_40), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_40), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_44), 0x5030, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_40), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_40), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_40), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_40), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_40), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_40), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_40), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_40), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_44), 0x5070, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_40), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_40), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_40), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_40), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_40), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_40), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_40), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_40), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_44), 0x50b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_40), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_40), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_40), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_40), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_40), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_40), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_40), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_40), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_44), 0x50f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_40), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_40), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5100_40), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_40), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_40), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_40), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_40), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_44), 0x5130, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_40), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_40), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_40), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_40), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_40), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_40), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_40), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_40), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_44), 0x5170, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_40), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_40), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_40), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_40), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_40), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_40), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_40), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_40), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_44), 0x51b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_40), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_40), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_40), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_40), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_40), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_40), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_40), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_40), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_44), 0x51f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_40), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_40), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c0_40), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_40), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_40), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_40), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_40), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_40), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_44), 0x52f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_40), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_40), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c0_40), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_40), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_40), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_40), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_40), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_40), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_44), 0x53f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_40), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_40), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c0_40), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_40), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_40), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_40), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_40), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_40), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_44), 0x54f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_40), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_40), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c0_40), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_40), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_40), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_40), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_40), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_40), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_44), 0x55f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_40), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_40), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c0_40), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_40), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_40), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_40), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_40), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_40), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_44), 0x56f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_40), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_40), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c0_40), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_40), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_40), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_40), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_40), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_40), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_44), 0x57f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_40), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_40), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c0_40), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_40), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_40), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_40), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_40), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_40), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_44), 0x58f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_40), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_40), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c0_40), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_40), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_40), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_40), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_40), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_40), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_44), 0x59f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_40), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_40), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac0_40), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_40), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_40), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_40), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_40), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_40), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_44), 0x5af0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_40), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_40), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc0_40), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_40), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_40), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_40), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_40), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_40), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_44), 0x5bf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_40), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_40), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc0_40), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_40), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_40), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_40), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_40), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_40), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_44), 0x5cf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_40), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_40), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc0_40), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_40), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_40), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_40), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_40), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_40), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_44), 0x5df0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_40), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_40), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec0_40), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_40), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_40), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_40), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_40), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_40), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_44), 0x5ef0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_40), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_40), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc0_40), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_40), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_40), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_40), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_40), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_40), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_44), 0x5ff0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_40), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_40), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_6000_40), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_40), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_44), 0x60ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6100_40), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_40), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_44), 0x61ff, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_40), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_40), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_44), 0x62ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6300_40), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_40), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_44), 0x63ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6400_40), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_40), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_44), 0x64ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6500_40), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_40), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_44), 0x65ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6600_40), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_40), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_44), 0x66ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6700_40), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_40), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_44), 0x67ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6800_40), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_40), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_44), 0x68ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6900_40), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_40), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_44), 0x69ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6a00_40), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_40), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_44), 0x6aff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6b00_40), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_40), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_44), 0x6bff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6c00_40), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_40), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_44), 0x6cff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6d00_40), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_40), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_44), 0x6dff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6e00_40), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_40), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_44), 0x6eff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6f00_40), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_40), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_44), 0x6fff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_7000_40), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_40), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_40), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_40), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_40), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_40), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_44), 0x8030, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_40), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_40), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_40), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_44), 0x803b, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_40), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_40), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_40), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_40), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_40), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_40), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_44), 0x8070, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_40), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_40), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_40), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_44), 0x807b, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_40), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_40), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_40), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_40), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_40), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_40), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_44), 0x80b0, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_40), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_40), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_40), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_44), 0x80bb, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_40), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_40), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_40), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_40), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_40), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_40), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_44), 0x80f0, 4, { 4, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_40), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_40), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_40), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_44), 0x80fb, 4, { 4, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_40), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_42), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_42), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_40), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_40), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_40), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_40), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_44), 0x8130, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_40), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_40), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8150_40), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_40), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_40), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_40), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_44), 0x8170, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_40), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_40), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8190_40), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_40), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_40), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_40), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_44), 0x81b0, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_40), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_40), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_40), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_40), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_40), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_40), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_40), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_44), 0x81f0, 4, { 4, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_40), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_40), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_40), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_44), 0x81fb, 4, { 4, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_40), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_40), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_40), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_40), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_40), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_40), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_44), 0x9030, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_40), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_40), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_40), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_44), 0x903b, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_40), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_40), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_40), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_40), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_40), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_40), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_40), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_44), 0x9070, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_40), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_40), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_40), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_44), 0x907b, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_40), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_40), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_40), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_40), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_40), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_40), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_40), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_44), 0x90b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_40), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_40), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_40), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_44), 0x90bb, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_40), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_40), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_40), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_40), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_40), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_40), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_40), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_44), 0x90f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_40), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_40), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_40), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_44), 0x90fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_40), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_40), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_40), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_40), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_40), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_40), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_40), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_44), 0x9130, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_40), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_40), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_40), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_40), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_40), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_40), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_40), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_40), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_44), 0x9170, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_40), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_40), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_40), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_40), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_40), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_40), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_40), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_40), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_44), 0x91b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_40), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_40), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_40), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_40), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_40), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_40), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_40), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_40), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_44), 0x91f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_40), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_40), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_40), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_44), 0x91fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_40), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_40), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_40), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_40), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_40), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_40), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_44), 0xb030, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_40), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_40), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_40), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_44), 0xb03b, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_40), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_40), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_40), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_40), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_40), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_40), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_40), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_44), 0xb070, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_40), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_40), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_40), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_44), 0xb07b, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_40), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_40), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_40), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_40), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_40), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_40), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_40), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_44), 0xb0b0, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_40), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_40), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_40), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_44), 0xb0bb, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_40), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_40), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_40), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_40), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_40), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_40), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_40), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_44), 0xb0f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_40), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_40), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_40), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_44), 0xb0fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_40), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_40), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_40), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_40), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_40), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_40), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_40), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_44), 0xb130, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_40), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_40), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_40), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_40), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_40), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_40), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_40), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_40), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_44), 0xb170, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_40), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_40), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_40), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_40), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_40), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_40), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_40), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_40), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_44), 0xb1b0, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_40), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_40), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_40), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_40), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_40), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_40), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_40), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_40), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_44), 0xb1f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_40), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_40), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_40), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_44), 0xb1fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_40), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_40), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_40), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_40), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_40), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_40), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_44), 0xc030, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_40), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_40), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_40), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_44), 0xc03b, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_40), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_40), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_40), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_40), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_40), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_40), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_44), 0xc070, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_40), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_40), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_40), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_44), 0xc07b, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_40), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_40), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_40), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_40), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_40), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_40), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_44), 0xc0b0, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_40), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_40), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_40), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_44), 0xc0bb, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_40), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_40), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_40), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_40), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_40), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_40), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_44), 0xc0f0, 4, { 4, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_40), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_40), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_40), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_44), 0xc0fb, 4, { 4, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_40), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_42), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_42), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_40), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_40), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_40), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_40), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_44), 0xc130, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_40), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_40), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_40), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_40), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_40), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_40), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_40), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_40), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_44), 0xc170, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_40), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_40), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_40), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_40), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_40), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_40), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_40), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_44), 0xc1b0, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_40), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_40), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_40), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_40), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_40), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_40), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_40), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_44), 0xc1f0, 4, { 4, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_40), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_40), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_40), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_44), 0xc1fb, 4, { 4, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_40), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_40), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_40), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_40), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_40), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_40), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_44), 0xd030, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_40), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_40), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_40), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_44), 0xd03b, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_40), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_40), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_40), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_40), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_40), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_40), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_40), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_44), 0xd070, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_40), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_40), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_40), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_44), 0xd07b, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_40), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_40), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_40), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_40), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_40), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_40), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_40), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_44), 0xd0b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_40), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_40), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_40), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_44), 0xd0bb, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_40), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_40), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_40), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_40), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_40), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_40), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_40), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_44), 0xd0f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_40), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_40), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_40), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_44), 0xd0fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_40), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_40), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_40), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_40), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_40), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_40), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_40), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_44), 0xd130, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_40), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_40), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_40), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_40), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_40), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_40), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_40), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_40), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_44), 0xd170, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_40), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_40), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_40), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_40), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_40), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_40), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_40), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_40), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_44), 0xd1b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_40), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_40), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_40), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_40), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_40), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_40), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_40), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_40), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_44), 0xd1f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_40), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_40), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_40), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_44), 0xd1fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_40), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_40), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_40), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_40), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_40), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_40), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_40), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_40), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_40), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_40), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_40), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_40), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_40), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_40), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_40), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_40), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_40), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_40), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_40), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_40), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_40), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_40), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_40), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_40), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_40), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_40), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_40), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_40), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_40), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_44), 0xe0f0, 4, { 4, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_40), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_40), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_40), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_40), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_40), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_40), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_40), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_40), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_40), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_40), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_40), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_40), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_40), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_40), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_40), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_40), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_40), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_40), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_40), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_40), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_40), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_40), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_40), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_40), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_40), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_40), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_40), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_40), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_40), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_40), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_44), 0xe1f0, 4, { 4, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_40), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_40), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_40), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_40), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_40), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_40), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_44), 0xe2f0, 4, { 4, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_40), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_40), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_40), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_40), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_40), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_40), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_44), 0xe3f0, 4, { 4, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_40), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_40), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_40), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_40), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_40), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_40), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_44), 0xe4f0, 4, { 4, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_40), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_40), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_40), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_40), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_40), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_40), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_44), 0xe5f0, 4, { 4, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_40), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_40), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_40), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_40), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_40), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_40), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_44), 0xe6f0, 4, { 4, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_40), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_40), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_40), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_40), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_40), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_40), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_44), 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_40), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_40), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
+#ifndef CPUEMU_68000_ONLY
+const struct cputbl CPUFUNC(op_smalltbl_45)[] = {
+{ CPUFUNC(op_0000_40), 0x0000, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0010_40), 0x0010, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0018_40), 0x0018, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0020_40), 0x0020, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0028_40), 0x0028, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0030_44), 0x0030, 6, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0038_40), 0x0038, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0039_40), 0x0039, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_003c_40), 0x003c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0040_40), 0x0040, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0050_40), 0x0050, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0058_40), 0x0058, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0060_40), 0x0060, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0068_40), 0x0068, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0070_44), 0x0070, 6, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0078_40), 0x0078, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0079_40), 0x0079, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_007c_40), 0x007c, 4, { 0, 0 }, 0 }, /* ORSR */
+{ CPUFUNC(op_0080_40), 0x0080, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0090_40), 0x0090, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0098_40), 0x0098, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a0_40), 0x00a0, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00a8_40), 0x00a8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b0_44), 0x00b0, 8, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b8_40), 0x00b8, 8, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_00b9_40), 0x00b9, 10, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_0100_40), 0x0100, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0108_40), 0x0108, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0110_40), 0x0110, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0118_40), 0x0118, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0120_40), 0x0120, 2, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0128_40), 0x0128, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0130_44), 0x0130, 4, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0138_40), 0x0138, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0139_40), 0x0139, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013a_40), 0x013a, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013b_44), 0x013b, 4, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_013c_40), 0x013c, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0140_40), 0x0140, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0148_40), 0x0148, 4, { 0, 0 }, 0 }, /* MVPMR */
+{ CPUFUNC(op_0150_40), 0x0150, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0158_40), 0x0158, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0160_40), 0x0160, 2, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0168_40), 0x0168, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0170_44), 0x0170, 4, { 4, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0178_40), 0x0178, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0179_40), 0x0179, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0180_40), 0x0180, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0188_40), 0x0188, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_0190_40), 0x0190, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0198_40), 0x0198, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a0_40), 0x01a0, 2, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01a8_40), 0x01a8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b0_44), 0x01b0, 4, { 4, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b8_40), 0x01b8, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01b9_40), 0x01b9, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_01c0_40), 0x01c0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01c8_40), 0x01c8, 4, { 0, 0 }, 0 }, /* MVPRM */
+{ CPUFUNC(op_01d0_40), 0x01d0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01d8_40), 0x01d8, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e0_40), 0x01e0, 2, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01e8_40), 0x01e8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f0_44), 0x01f0, 4, { 4, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f8_40), 0x01f8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_01f9_40), 0x01f9, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0200_40), 0x0200, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0210_40), 0x0210, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0218_40), 0x0218, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0220_40), 0x0220, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0228_40), 0x0228, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0230_44), 0x0230, 6, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0238_40), 0x0238, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0239_40), 0x0239, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_023c_40), 0x023c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0240_40), 0x0240, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0250_40), 0x0250, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0258_40), 0x0258, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0260_40), 0x0260, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0268_40), 0x0268, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0270_44), 0x0270, 6, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0278_40), 0x0278, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0279_40), 0x0279, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_027c_40), 0x027c, 4, { 0, 0 }, 0 }, /* ANDSR */
+{ CPUFUNC(op_0280_40), 0x0280, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0290_40), 0x0290, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0298_40), 0x0298, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a0_40), 0x02a0, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02a8_40), 0x02a8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b0_44), 0x02b0, 8, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b8_40), 0x02b8, 8, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_02b9_40), 0x02b9, 10, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_0400_40), 0x0400, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0410_40), 0x0410, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0418_40), 0x0418, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0420_40), 0x0420, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0428_40), 0x0428, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0430_44), 0x0430, 6, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0438_40), 0x0438, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0439_40), 0x0439, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0440_40), 0x0440, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0450_40), 0x0450, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0458_40), 0x0458, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0460_40), 0x0460, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0468_40), 0x0468, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0470_44), 0x0470, 6, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0478_40), 0x0478, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0479_40), 0x0479, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0480_40), 0x0480, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0490_40), 0x0490, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0498_40), 0x0498, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a0_40), 0x04a0, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04a8_40), 0x04a8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b0_44), 0x04b0, 8, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b8_40), 0x04b8, 8, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_04b9_40), 0x04b9, 10, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_0600_40), 0x0600, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0610_40), 0x0610, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0618_40), 0x0618, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0620_40), 0x0620, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0628_40), 0x0628, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0630_44), 0x0630, 6, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0638_40), 0x0638, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0639_40), 0x0639, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0640_40), 0x0640, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0650_40), 0x0650, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0658_40), 0x0658, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0660_40), 0x0660, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0668_40), 0x0668, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0670_44), 0x0670, 6, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0678_40), 0x0678, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0679_40), 0x0679, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0680_40), 0x0680, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0690_40), 0x0690, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0698_40), 0x0698, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a0_40), 0x06a0, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06a8_40), 0x06a8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b0_44), 0x06b0, 8, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b8_40), 0x06b8, 8, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_06b9_40), 0x06b9, 10, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_0800_40), 0x0800, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0810_40), 0x0810, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0818_40), 0x0818, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0820_40), 0x0820, 4, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0828_40), 0x0828, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0830_44), 0x0830, 6, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0838_40), 0x0838, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0839_40), 0x0839, 8, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083a_40), 0x083a, 6, { 0, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_083b_44), 0x083b, 6, { 4, 0 }, 0 }, /* BTST */
+{ CPUFUNC(op_0840_40), 0x0840, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0850_40), 0x0850, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0858_40), 0x0858, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0860_40), 0x0860, 4, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0868_40), 0x0868, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0870_44), 0x0870, 6, { 4, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0878_40), 0x0878, 6, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0879_40), 0x0879, 8, { 0, 0 }, 0 }, /* BCHG */
+{ CPUFUNC(op_0880_40), 0x0880, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0890_40), 0x0890, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_0898_40), 0x0898, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a0_40), 0x08a0, 4, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08a8_40), 0x08a8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b0_44), 0x08b0, 6, { 4, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b8_40), 0x08b8, 6, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08b9_40), 0x08b9, 8, { 0, 0 }, 0 }, /* BCLR */
+{ CPUFUNC(op_08c0_40), 0x08c0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d0_40), 0x08d0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08d8_40), 0x08d8, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e0_40), 0x08e0, 4, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08e8_40), 0x08e8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f0_44), 0x08f0, 6, { 4, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f8_40), 0x08f8, 6, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_08f9_40), 0x08f9, 8, { 0, 0 }, 0 }, /* BSET */
+{ CPUFUNC(op_0a00_40), 0x0a00, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a10_40), 0x0a10, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a18_40), 0x0a18, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a20_40), 0x0a20, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a28_40), 0x0a28, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a30_44), 0x0a30, 6, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a38_40), 0x0a38, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a39_40), 0x0a39, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a3c_40), 0x0a3c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a40_40), 0x0a40, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a50_40), 0x0a50, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a58_40), 0x0a58, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a60_40), 0x0a60, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a68_40), 0x0a68, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a70_44), 0x0a70, 6, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a78_40), 0x0a78, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a79_40), 0x0a79, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a7c_40), 0x0a7c, 4, { 0, 0 }, 0 }, /* EORSR */
+{ CPUFUNC(op_0a80_40), 0x0a80, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a90_40), 0x0a90, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0a98_40), 0x0a98, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa0_40), 0x0aa0, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0aa8_40), 0x0aa8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab0_44), 0x0ab0, 8, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab8_40), 0x0ab8, 8, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0ab9_40), 0x0ab9, 10, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_0c00_40), 0x0c00, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c10_40), 0x0c10, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c18_40), 0x0c18, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c20_40), 0x0c20, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c28_40), 0x0c28, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c30_44), 0x0c30, 6, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c38_40), 0x0c38, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c39_40), 0x0c39, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c40_40), 0x0c40, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c50_40), 0x0c50, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c58_40), 0x0c58, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c60_40), 0x0c60, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c68_40), 0x0c68, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c70_44), 0x0c70, 6, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c78_40), 0x0c78, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c79_40), 0x0c79, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c80_40), 0x0c80, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c90_40), 0x0c90, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0c98_40), 0x0c98, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca0_40), 0x0ca0, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0ca8_40), 0x0ca8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb0_44), 0x0cb0, 8, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb8_40), 0x0cb8, 8, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_0cb9_40), 0x0cb9, 10, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_1000_40), 0x1000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1010_40), 0x1010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1018_40), 0x1018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1020_40), 0x1020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1028_40), 0x1028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1030_44), 0x1030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1038_40), 0x1038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1039_40), 0x1039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103a_40), 0x103a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103b_44), 0x103b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_103c_40), 0x103c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1080_40), 0x1080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1090_40), 0x1090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1098_40), 0x1098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a0_40), 0x10a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10a8_40), 0x10a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b0_44), 0x10b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b8_40), 0x10b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10b9_40), 0x10b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10ba_40), 0x10ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bb_44), 0x10bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10bc_40), 0x10bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10c0_40), 0x10c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d0_40), 0x10d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10d8_40), 0x10d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e0_40), 0x10e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10e8_40), 0x10e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f0_44), 0x10f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f8_40), 0x10f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10f9_40), 0x10f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fa_40), 0x10fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fb_44), 0x10fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_10fc_40), 0x10fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1100_40), 0x1100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1110_40), 0x1110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1118_40), 0x1118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1120_40), 0x1120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1128_40), 0x1128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1130_44), 0x1130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1138_40), 0x1138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1139_40), 0x1139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113a_40), 0x113a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113b_44), 0x113b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_113c_40), 0x113c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1140_40), 0x1140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1150_40), 0x1150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1158_40), 0x1158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1160_40), 0x1160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1168_40), 0x1168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1170_44), 0x1170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1178_40), 0x1178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1179_40), 0x1179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117a_40), 0x117a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117b_44), 0x117b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_117c_40), 0x117c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1180_44), 0x1180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1190_44), 0x1190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_1198_44), 0x1198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a0_44), 0x11a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11a8_44), 0x11a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b0_44), 0x11b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b8_44), 0x11b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11b9_44), 0x11b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11ba_44), 0x11ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bb_44), 0x11bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11bc_44), 0x11bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11c0_40), 0x11c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d0_40), 0x11d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11d8_40), 0x11d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e0_40), 0x11e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11e8_40), 0x11e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f0_44), 0x11f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f8_40), 0x11f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11f9_40), 0x11f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fa_40), 0x11fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fb_44), 0x11fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_11fc_40), 0x11fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13c0_40), 0x13c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d0_40), 0x13d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13d8_40), 0x13d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e0_40), 0x13e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13e8_40), 0x13e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f0_44), 0x13f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f8_40), 0x13f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13f9_40), 0x13f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fa_40), 0x13fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fb_44), 0x13fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_13fc_40), 0x13fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2000_40), 0x2000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2008_40), 0x2008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2010_40), 0x2010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2018_40), 0x2018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2020_40), 0x2020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2028_40), 0x2028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2030_44), 0x2030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2038_40), 0x2038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2039_40), 0x2039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203a_40), 0x203a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203b_44), 0x203b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_203c_40), 0x203c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2040_40), 0x2040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2048_40), 0x2048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2050_40), 0x2050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2058_40), 0x2058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2060_40), 0x2060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2068_40), 0x2068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2070_44), 0x2070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2078_40), 0x2078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2079_40), 0x2079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207a_40), 0x207a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207b_44), 0x207b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_207c_40), 0x207c, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_2080_40), 0x2080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2088_40), 0x2088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2090_40), 0x2090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2098_40), 0x2098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a0_40), 0x20a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20a8_40), 0x20a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b0_44), 0x20b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b8_40), 0x20b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20b9_40), 0x20b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20ba_40), 0x20ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bb_44), 0x20bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20bc_40), 0x20bc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c0_40), 0x20c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20c8_40), 0x20c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d0_40), 0x20d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20d8_40), 0x20d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e0_40), 0x20e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20e8_40), 0x20e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f0_44), 0x20f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f8_40), 0x20f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20f9_40), 0x20f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fa_40), 0x20fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fb_44), 0x20fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_20fc_40), 0x20fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2100_40), 0x2100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2108_40), 0x2108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2110_40), 0x2110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2118_40), 0x2118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2120_40), 0x2120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2128_40), 0x2128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2130_44), 0x2130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2138_40), 0x2138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2139_40), 0x2139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213a_40), 0x213a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213b_44), 0x213b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_213c_40), 0x213c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2140_40), 0x2140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2148_40), 0x2148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2150_40), 0x2150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2158_40), 0x2158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2160_40), 0x2160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2168_40), 0x2168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2170_44), 0x2170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2178_40), 0x2178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2179_40), 0x2179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217a_40), 0x217a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217b_44), 0x217b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_217c_40), 0x217c, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2180_44), 0x2180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2188_44), 0x2188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2190_44), 0x2190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_2198_44), 0x2198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a0_44), 0x21a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21a8_44), 0x21a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b0_44), 0x21b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b8_44), 0x21b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21b9_44), 0x21b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21ba_44), 0x21ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bb_44), 0x21bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21bc_44), 0x21bc, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c0_40), 0x21c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21c8_40), 0x21c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d0_40), 0x21d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21d8_40), 0x21d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e0_40), 0x21e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21e8_40), 0x21e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f0_44), 0x21f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f8_40), 0x21f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21f9_40), 0x21f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fa_40), 0x21fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fb_44), 0x21fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_21fc_40), 0x21fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c0_40), 0x23c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23c8_40), 0x23c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d0_40), 0x23d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23d8_40), 0x23d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e0_40), 0x23e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23e8_40), 0x23e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f0_44), 0x23f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f8_40), 0x23f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23f9_40), 0x23f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fa_40), 0x23fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fb_44), 0x23fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_23fc_40), 0x23fc, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3000_40), 0x3000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3008_40), 0x3008, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3010_40), 0x3010, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3018_40), 0x3018, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3020_40), 0x3020, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3028_40), 0x3028, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3030_44), 0x3030, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3038_40), 0x3038, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3039_40), 0x3039, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303a_40), 0x303a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303b_44), 0x303b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_303c_40), 0x303c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3040_40), 0x3040, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3048_40), 0x3048, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3050_40), 0x3050, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3058_40), 0x3058, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3060_40), 0x3060, 2, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3068_40), 0x3068, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3070_44), 0x3070, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3078_40), 0x3078, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3079_40), 0x3079, 6, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307a_40), 0x307a, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307b_44), 0x307b, 4, { 4, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_307c_40), 0x307c, 4, { 0, 0 }, 0 }, /* MOVEA */
+{ CPUFUNC(op_3080_40), 0x3080, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3088_40), 0x3088, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3090_40), 0x3090, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3098_40), 0x3098, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a0_40), 0x30a0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30a8_40), 0x30a8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b0_44), 0x30b0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b8_40), 0x30b8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30b9_40), 0x30b9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30ba_40), 0x30ba, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bb_44), 0x30bb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30bc_40), 0x30bc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c0_40), 0x30c0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30c8_40), 0x30c8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d0_40), 0x30d0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30d8_40), 0x30d8, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e0_40), 0x30e0, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30e8_40), 0x30e8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f0_44), 0x30f0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f8_40), 0x30f8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30f9_40), 0x30f9, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fa_40), 0x30fa, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fb_44), 0x30fb, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_30fc_40), 0x30fc, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3100_40), 0x3100, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3108_40), 0x3108, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3110_40), 0x3110, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3118_40), 0x3118, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3120_40), 0x3120, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3128_40), 0x3128, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3130_44), 0x3130, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3138_40), 0x3138, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3139_40), 0x3139, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313a_40), 0x313a, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313b_44), 0x313b, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_313c_40), 0x313c, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3140_40), 0x3140, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3148_40), 0x3148, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3150_40), 0x3150, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3158_40), 0x3158, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3160_40), 0x3160, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3168_40), 0x3168, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3170_44), 0x3170, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3178_40), 0x3178, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3179_40), 0x3179, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317a_40), 0x317a, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317b_44), 0x317b, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_317c_40), 0x317c, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3180_44), 0x3180, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3188_44), 0x3188, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3190_44), 0x3190, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_3198_44), 0x3198, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a0_44), 0x31a0, 4, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31a8_44), 0x31a8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b0_44), 0x31b0, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b8_44), 0x31b8, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31b9_44), 0x31b9, 8, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31ba_44), 0x31ba, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bb_44), 0x31bb, 6, { 6, 4 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31bc_44), 0x31bc, 6, { 4, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c0_40), 0x31c0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31c8_40), 0x31c8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d0_40), 0x31d0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31d8_40), 0x31d8, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e0_40), 0x31e0, 4, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31e8_40), 0x31e8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f0_44), 0x31f0, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f8_40), 0x31f8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31f9_40), 0x31f9, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fa_40), 0x31fa, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fb_44), 0x31fb, 6, { 6, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_31fc_40), 0x31fc, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c0_40), 0x33c0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33c8_40), 0x33c8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d0_40), 0x33d0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33d8_40), 0x33d8, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e0_40), 0x33e0, 6, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33e8_40), 0x33e8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f0_44), 0x33f0, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f8_40), 0x33f8, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33f9_40), 0x33f9, 10, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fa_40), 0x33fa, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fb_44), 0x33fb, 8, { 8, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_33fc_40), 0x33fc, 8, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_4000_40), 0x4000, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4010_40), 0x4010, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4018_40), 0x4018, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4020_40), 0x4020, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4028_40), 0x4028, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4030_44), 0x4030, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4038_40), 0x4038, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4039_40), 0x4039, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4040_40), 0x4040, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4050_40), 0x4050, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4058_40), 0x4058, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4060_40), 0x4060, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4068_40), 0x4068, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4070_44), 0x4070, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4078_40), 0x4078, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4079_40), 0x4079, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4080_40), 0x4080, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4090_40), 0x4090, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_4098_40), 0x4098, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a0_40), 0x40a0, 2, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40a8_40), 0x40a8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b0_44), 0x40b0, 4, { 4, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b8_40), 0x40b8, 4, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40b9_40), 0x40b9, 6, { 0, 0 }, 0 }, /* NEGX */
+{ CPUFUNC(op_40c0_45), 0x40c0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d0_45), 0x40d0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40d8_45), 0x40d8, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e0_45), 0x40e0, 2, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40e8_45), 0x40e8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f0_45), 0x40f0, 4, { 4, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f8_45), 0x40f8, 4, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_40f9_45), 0x40f9, 6, { 0, 0 }, 0 }, /* MVSR2 */
+{ CPUFUNC(op_4180_40), 0x4180, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4190_40), 0x4190, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_4198_40), 0x4198, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a0_40), 0x41a0, 2, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41a8_40), 0x41a8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b0_44), 0x41b0, 4, { 4, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b8_40), 0x41b8, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41b9_40), 0x41b9, 6, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41ba_40), 0x41ba, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bb_44), 0x41bb, 4, { 4, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41bc_40), 0x41bc, 4, { 0, 0 }, 0 }, /* CHK */
+{ CPUFUNC(op_41d0_40), 0x41d0, 2, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41e8_40), 0x41e8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f0_44), 0x41f0, 4, { 4, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f8_40), 0x41f8, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41f9_40), 0x41f9, 6, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fa_40), 0x41fa, 4, { 0, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_41fb_44), 0x41fb, 4, { 4, 0 }, 0 }, /* LEA */
+{ CPUFUNC(op_4200_45), 0x4200, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4210_45), 0x4210, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4218_45), 0x4218, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4220_45), 0x4220, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4228_45), 0x4228, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4230_45), 0x4230, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4238_45), 0x4238, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4239_45), 0x4239, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4240_45), 0x4240, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4250_45), 0x4250, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4258_45), 0x4258, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4260_45), 0x4260, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4268_45), 0x4268, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4270_45), 0x4270, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4278_45), 0x4278, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4279_45), 0x4279, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4280_45), 0x4280, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4290_45), 0x4290, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4298_45), 0x4298, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a0_45), 0x42a0, 2, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42a8_45), 0x42a8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b0_45), 0x42b0, 4, { 4, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b8_45), 0x42b8, 4, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_42b9_45), 0x42b9, 6, { 0, 0 }, 0 }, /* CLR */
+{ CPUFUNC(op_4400_40), 0x4400, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4410_40), 0x4410, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4418_40), 0x4418, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4420_40), 0x4420, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4428_40), 0x4428, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4430_44), 0x4430, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4438_40), 0x4438, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4439_40), 0x4439, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4440_40), 0x4440, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4450_40), 0x4450, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4458_40), 0x4458, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4460_40), 0x4460, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4468_40), 0x4468, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4470_44), 0x4470, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4478_40), 0x4478, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4479_40), 0x4479, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4480_40), 0x4480, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4490_40), 0x4490, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_4498_40), 0x4498, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a0_40), 0x44a0, 2, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44a8_40), 0x44a8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b0_44), 0x44b0, 4, { 4, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b8_40), 0x44b8, 4, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44b9_40), 0x44b9, 6, { 0, 0 }, 0 }, /* NEG */
+{ CPUFUNC(op_44c0_40), 0x44c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d0_40), 0x44d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44d8_40), 0x44d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e0_40), 0x44e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44e8_40), 0x44e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f0_44), 0x44f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f8_40), 0x44f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44f9_40), 0x44f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fa_40), 0x44fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fb_44), 0x44fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_44fc_40), 0x44fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4600_40), 0x4600, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4610_40), 0x4610, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4618_40), 0x4618, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4620_40), 0x4620, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4628_40), 0x4628, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4630_44), 0x4630, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4638_40), 0x4638, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4639_40), 0x4639, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4640_40), 0x4640, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4650_40), 0x4650, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4658_40), 0x4658, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4660_40), 0x4660, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4668_40), 0x4668, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4670_44), 0x4670, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4678_40), 0x4678, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4679_40), 0x4679, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4680_40), 0x4680, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4690_40), 0x4690, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_4698_40), 0x4698, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a0_40), 0x46a0, 2, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46a8_40), 0x46a8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b0_44), 0x46b0, 4, { 4, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b8_40), 0x46b8, 4, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46b9_40), 0x46b9, 6, { 0, 0 }, 0 }, /* NOT */
+{ CPUFUNC(op_46c0_40), 0x46c0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d0_40), 0x46d0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46d8_40), 0x46d8, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e0_40), 0x46e0, 2, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46e8_40), 0x46e8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f0_44), 0x46f0, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f8_40), 0x46f8, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46f9_40), 0x46f9, 6, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fa_40), 0x46fa, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fb_44), 0x46fb, 4, { 4, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_46fc_40), 0x46fc, 4, { 0, 0 }, 0 }, /* MV2SR */
+{ CPUFUNC(op_4800_42), 0x4800, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4810_42), 0x4810, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4818_42), 0x4818, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4820_42), 0x4820, 2, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4828_42), 0x4828, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4830_44), 0x4830, 4, { 4, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4838_42), 0x4838, 4, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4839_42), 0x4839, 6, { 0, 0 }, 0 }, /* NBCD */
+{ CPUFUNC(op_4840_40), 0x4840, 2, { 0, 0 }, 0 }, /* SWAP */
+{ CPUFUNC(op_4850_40), 0x4850, 2, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4868_40), 0x4868, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4870_44), 0x4870, 4, { 4, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4878_40), 0x4878, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4879_40), 0x4879, 6, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487a_40), 0x487a, 4, { 0, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_487b_44), 0x487b, 4, { 4, 0 }, 0 }, /* PEA */
+{ CPUFUNC(op_4880_40), 0x4880, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_4890_40), 0x4890, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a0_40), 0x48a0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48a8_40), 0x48a8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b0_44), 0x48b0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b8_40), 0x48b8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48b9_40), 0x48b9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48c0_40), 0x48c0, 2, { 0, 0 }, 0 }, /* EXT */
+{ CPUFUNC(op_48d0_40), 0x48d0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e0_40), 0x48e0, 4, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48e8_40), 0x48e8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f0_44), 0x48f0, 6, { 4, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f8_40), 0x48f8, 6, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_48f9_40), 0x48f9, 8, { 0, 0 }, 0 }, /* MVMLE */
+{ CPUFUNC(op_4a00_40), 0x4a00, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a10_40), 0x4a10, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a18_40), 0x4a18, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a20_40), 0x4a20, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a28_40), 0x4a28, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a30_44), 0x4a30, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a38_40), 0x4a38, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a39_40), 0x4a39, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a40_40), 0x4a40, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a50_40), 0x4a50, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a58_40), 0x4a58, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a60_40), 0x4a60, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a68_40), 0x4a68, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a70_44), 0x4a70, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a78_40), 0x4a78, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a79_40), 0x4a79, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a80_40), 0x4a80, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a90_40), 0x4a90, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4a98_40), 0x4a98, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa0_40), 0x4aa0, 2, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4aa8_40), 0x4aa8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab0_44), 0x4ab0, 4, { 4, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab8_40), 0x4ab8, 4, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ab9_40), 0x4ab9, 6, { 0, 0 }, 0 }, /* TST */
+{ CPUFUNC(op_4ac0_44), 0x4ac0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad0_44), 0x4ad0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ad8_44), 0x4ad8, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae0_44), 0x4ae0, 2, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4ae8_44), 0x4ae8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af0_44), 0x4af0, 4, { 4, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af8_44), 0x4af8, 4, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4af9_44), 0x4af9, 6, { 0, 0 }, 0 }, /* TAS */
+{ CPUFUNC(op_4c90_40), 0x4c90, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4c98_40), 0x4c98, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ca8_40), 0x4ca8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb0_44), 0x4cb0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb8_40), 0x4cb8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cb9_40), 0x4cb9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cba_40), 0x4cba, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cbb_44), 0x4cbb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd0_40), 0x4cd0, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cd8_40), 0x4cd8, 4, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4ce8_40), 0x4ce8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf0_44), 0x4cf0, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf8_40), 0x4cf8, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cf9_40), 0x4cf9, 8, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfa_40), 0x4cfa, 6, { 0, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4cfb_44), 0x4cfb, 6, { 4, 0 }, 0 }, /* MVMEL */
+{ CPUFUNC(op_4e40_40), 0x4e40, 2, { 0, 0 }, 2 }, /* TRAP */
+{ CPUFUNC(op_4e50_40), 0x4e50, 4, { 0, 0 }, 0 }, /* LINK */
+{ CPUFUNC(op_4e58_40), 0x4e58, 2, { 0, 0 }, 0 }, /* UNLK */
+{ CPUFUNC(op_4e60_40), 0x4e60, 2, { 0, 0 }, 0 }, /* MVR2USP */
+{ CPUFUNC(op_4e68_40), 0x4e68, 2, { 0, 0 }, 0 }, /* MVUSP2R */
+{ CPUFUNC(op_4e70_40), 0x4e70, 2, { 0, 0 }, 0 }, /* RESET */
+{ CPUFUNC(op_4e71_40), 0x4e71, 2, { 0, 0 }, 0 }, /* NOP */
+{ CPUFUNC(op_4e72_40), 0x4e72, 4, { 0, 0 }, 0 }, /* STOP */
+{ CPUFUNC(op_4e73_45), 0x4e73, 2, { 0, 0 }, 1 }, /* RTE */
+{ CPUFUNC(op_4e75_40), 0x4e75, 2, { 0, 0 }, 1 }, /* RTS */
+{ CPUFUNC(op_4e76_40), 0x4e76, 2, { 0, 0 }, 0 }, /* TRAPV */
+{ CPUFUNC(op_4e77_40), 0x4e77, 2, { 0, 0 }, 1 }, /* RTR */
+{ CPUFUNC(op_4e90_40), 0x4e90, 2, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ea8_40), 0x4ea8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb0_44), 0x4eb0, 4, { 4, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb8_40), 0x4eb8, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eb9_40), 0x4eb9, 6, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4eba_40), 0x4eba, 4, { 0, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ebb_44), 0x4ebb, 4, { 4, 0 }, 1 }, /* JSR */
+{ CPUFUNC(op_4ed0_40), 0x4ed0, 2, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ee8_40), 0x4ee8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef0_44), 0x4ef0, 4, { 4, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef8_40), 0x4ef8, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4ef9_40), 0x4ef9, 6, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efa_40), 0x4efa, 4, { 0, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_4efb_44), 0x4efb, 4, { 4, 0 }, 1 }, /* JMP */
+{ CPUFUNC(op_5000_40), 0x5000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5010_40), 0x5010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5018_40), 0x5018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5020_40), 0x5020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5028_40), 0x5028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5030_44), 0x5030, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5038_40), 0x5038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5039_40), 0x5039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5040_40), 0x5040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5048_40), 0x5048, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5050_40), 0x5050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5058_40), 0x5058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5060_40), 0x5060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5068_40), 0x5068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5070_44), 0x5070, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5078_40), 0x5078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5079_40), 0x5079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5080_40), 0x5080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5088_40), 0x5088, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_5090_40), 0x5090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_5098_40), 0x5098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a0_40), 0x50a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50a8_40), 0x50a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b0_44), 0x50b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b8_40), 0x50b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50b9_40), 0x50b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_50c0_45), 0x50c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50c8_40), 0x50c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_50d0_45), 0x50d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50d8_45), 0x50d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e0_45), 0x50e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50e8_45), 0x50e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f0_45), 0x50f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f8_45), 0x50f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_50f9_45), 0x50f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5100_40), 0x5100, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5110_40), 0x5110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5118_40), 0x5118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5120_40), 0x5120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5128_40), 0x5128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5130_44), 0x5130, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5138_40), 0x5138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5139_40), 0x5139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5140_40), 0x5140, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5148_40), 0x5148, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5150_40), 0x5150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5158_40), 0x5158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5160_40), 0x5160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5168_40), 0x5168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5170_44), 0x5170, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5178_40), 0x5178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5179_40), 0x5179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5180_40), 0x5180, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5188_40), 0x5188, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_5190_40), 0x5190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_5198_40), 0x5198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a0_40), 0x51a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51a8_40), 0x51a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b0_44), 0x51b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b8_40), 0x51b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51b9_40), 0x51b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_51c0_45), 0x51c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51c8_40), 0x51c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_51d0_45), 0x51d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51d8_45), 0x51d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e0_45), 0x51e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51e8_45), 0x51e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f0_45), 0x51f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f8_45), 0x51f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_51f9_45), 0x51f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c0_45), 0x52c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52c8_40), 0x52c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_52d0_45), 0x52d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52d8_45), 0x52d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e0_45), 0x52e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52e8_45), 0x52e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f0_45), 0x52f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f8_45), 0x52f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_52f9_45), 0x52f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c0_45), 0x53c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53c8_40), 0x53c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_53d0_45), 0x53d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53d8_45), 0x53d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e0_45), 0x53e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53e8_45), 0x53e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f0_45), 0x53f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f8_45), 0x53f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_53f9_45), 0x53f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c0_45), 0x54c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54c8_40), 0x54c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_54d0_45), 0x54d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54d8_45), 0x54d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e0_45), 0x54e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54e8_45), 0x54e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f0_45), 0x54f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f8_45), 0x54f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_54f9_45), 0x54f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c0_45), 0x55c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55c8_40), 0x55c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_55d0_45), 0x55d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55d8_45), 0x55d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e0_45), 0x55e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55e8_45), 0x55e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f0_45), 0x55f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f8_45), 0x55f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_55f9_45), 0x55f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c0_45), 0x56c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56c8_40), 0x56c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_56d0_45), 0x56d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56d8_45), 0x56d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e0_45), 0x56e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56e8_45), 0x56e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f0_45), 0x56f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f8_45), 0x56f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_56f9_45), 0x56f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c0_45), 0x57c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57c8_40), 0x57c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_57d0_45), 0x57d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57d8_45), 0x57d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e0_45), 0x57e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57e8_45), 0x57e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f0_45), 0x57f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f8_45), 0x57f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_57f9_45), 0x57f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c0_45), 0x58c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58c8_40), 0x58c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_58d0_45), 0x58d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58d8_45), 0x58d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e0_45), 0x58e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58e8_45), 0x58e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f0_45), 0x58f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f8_45), 0x58f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_58f9_45), 0x58f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c0_45), 0x59c0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59c8_40), 0x59c8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_59d0_45), 0x59d0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59d8_45), 0x59d8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e0_45), 0x59e0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59e8_45), 0x59e8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f0_45), 0x59f0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f8_45), 0x59f8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_59f9_45), 0x59f9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac0_45), 0x5ac0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ac8_40), 0x5ac8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ad0_45), 0x5ad0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ad8_45), 0x5ad8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae0_45), 0x5ae0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ae8_45), 0x5ae8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af0_45), 0x5af0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af8_45), 0x5af8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5af9_45), 0x5af9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc0_45), 0x5bc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bc8_40), 0x5bc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5bd0_45), 0x5bd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bd8_45), 0x5bd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be0_45), 0x5be0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5be8_45), 0x5be8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf0_45), 0x5bf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf8_45), 0x5bf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5bf9_45), 0x5bf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc0_45), 0x5cc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cc8_40), 0x5cc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5cd0_45), 0x5cd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cd8_45), 0x5cd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce0_45), 0x5ce0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ce8_45), 0x5ce8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf0_45), 0x5cf0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf8_45), 0x5cf8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5cf9_45), 0x5cf9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc0_45), 0x5dc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dc8_40), 0x5dc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5dd0_45), 0x5dd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5dd8_45), 0x5dd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de0_45), 0x5de0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5de8_45), 0x5de8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df0_45), 0x5df0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df8_45), 0x5df8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5df9_45), 0x5df9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec0_45), 0x5ec0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ec8_40), 0x5ec8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5ed0_45), 0x5ed0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ed8_45), 0x5ed8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee0_45), 0x5ee0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ee8_45), 0x5ee8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef0_45), 0x5ef0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef8_45), 0x5ef8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ef9_45), 0x5ef9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc0_45), 0x5fc0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fc8_40), 0x5fc8, 4, { 0, 0 }, 1 }, /* DBcc */
+{ CPUFUNC(op_5fd0_45), 0x5fd0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fd8_45), 0x5fd8, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe0_45), 0x5fe0, 2, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5fe8_45), 0x5fe8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff0_45), 0x5ff0, 4, { 4, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff8_45), 0x5ff8, 4, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_5ff9_45), 0x5ff9, 6, { 0, 0 }, 0 }, /* Scc */
+{ CPUFUNC(op_6000_40), 0x6000, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6001_40), 0x6001, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_60ff_44), 0x60ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6100_40), 0x6100, 4, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6101_40), 0x6101, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_61ff_44), 0x61ff, 2, { 0, 0 }, 1 }, /* BSR */
+{ CPUFUNC(op_6200_40), 0x6200, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6201_40), 0x6201, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_62ff_44), 0x62ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6300_40), 0x6300, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6301_40), 0x6301, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_63ff_44), 0x63ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6400_40), 0x6400, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6401_40), 0x6401, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_64ff_44), 0x64ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6500_40), 0x6500, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6501_40), 0x6501, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_65ff_44), 0x65ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6600_40), 0x6600, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6601_40), 0x6601, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_66ff_44), 0x66ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6700_40), 0x6700, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6701_40), 0x6701, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_67ff_44), 0x67ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6800_40), 0x6800, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6801_40), 0x6801, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_68ff_44), 0x68ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6900_40), 0x6900, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6901_40), 0x6901, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_69ff_44), 0x69ff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6a00_40), 0x6a00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6a01_40), 0x6a01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6aff_44), 0x6aff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6b00_40), 0x6b00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6b01_40), 0x6b01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6bff_44), 0x6bff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6c00_40), 0x6c00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6c01_40), 0x6c01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6cff_44), 0x6cff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6d00_40), 0x6d00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6d01_40), 0x6d01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6dff_44), 0x6dff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6e00_40), 0x6e00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6e01_40), 0x6e01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6eff_44), 0x6eff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_6f00_40), 0x6f00, 4, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6f01_40), 0x6f01, 2, { 0, 0 }, 1 }, /* Bcc */
+{ CPUFUNC(op_6fff_44), 0x6fff, 2, { 0, 0 }, 0 }, /* Bcc */
+{ CPUFUNC(op_7000_40), 0x7000, 2, { 0, 0 }, 0 }, /* MOVE */
+{ CPUFUNC(op_8000_40), 0x8000, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8010_40), 0x8010, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8018_40), 0x8018, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8020_40), 0x8020, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8028_40), 0x8028, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8030_44), 0x8030, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8038_40), 0x8038, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8039_40), 0x8039, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803a_40), 0x803a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803b_44), 0x803b, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_803c_40), 0x803c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8040_40), 0x8040, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8050_40), 0x8050, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8058_40), 0x8058, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8060_40), 0x8060, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8068_40), 0x8068, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8070_44), 0x8070, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8078_40), 0x8078, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8079_40), 0x8079, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807a_40), 0x807a, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807b_44), 0x807b, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_807c_40), 0x807c, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8080_40), 0x8080, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8090_40), 0x8090, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8098_40), 0x8098, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a0_40), 0x80a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80a8_40), 0x80a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b0_44), 0x80b0, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b8_40), 0x80b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80b9_40), 0x80b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80ba_40), 0x80ba, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bb_44), 0x80bb, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80bc_40), 0x80bc, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_80c0_40), 0x80c0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d0_40), 0x80d0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80d8_40), 0x80d8, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e0_40), 0x80e0, 2, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80e8_40), 0x80e8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f0_44), 0x80f0, 4, { 4, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f8_40), 0x80f8, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80f9_40), 0x80f9, 6, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fa_40), 0x80fa, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fb_44), 0x80fb, 4, { 4, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_80fc_40), 0x80fc, 4, { 0, 0 }, 0 }, /* DIVU */
+{ CPUFUNC(op_8100_42), 0x8100, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8108_42), 0x8108, 2, { 0, 0 }, 0 }, /* SBCD */
+{ CPUFUNC(op_8110_40), 0x8110, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8118_40), 0x8118, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8120_40), 0x8120, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8128_40), 0x8128, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8130_44), 0x8130, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8138_40), 0x8138, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8139_40), 0x8139, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8150_40), 0x8150, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8158_40), 0x8158, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8160_40), 0x8160, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8168_40), 0x8168, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8170_44), 0x8170, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8178_40), 0x8178, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8179_40), 0x8179, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8190_40), 0x8190, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_8198_40), 0x8198, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a0_40), 0x81a0, 2, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81a8_40), 0x81a8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b0_44), 0x81b0, 4, { 4, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b8_40), 0x81b8, 4, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81b9_40), 0x81b9, 6, { 0, 0 }, 0 }, /* OR */
+{ CPUFUNC(op_81c0_40), 0x81c0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d0_40), 0x81d0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81d8_40), 0x81d8, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e0_40), 0x81e0, 2, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81e8_40), 0x81e8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f0_44), 0x81f0, 4, { 4, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f8_40), 0x81f8, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81f9_40), 0x81f9, 6, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fa_40), 0x81fa, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fb_44), 0x81fb, 4, { 4, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_81fc_40), 0x81fc, 4, { 0, 0 }, 0 }, /* DIVS */
+{ CPUFUNC(op_9000_40), 0x9000, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9010_40), 0x9010, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9018_40), 0x9018, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9020_40), 0x9020, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9028_40), 0x9028, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9030_44), 0x9030, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9038_40), 0x9038, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9039_40), 0x9039, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903a_40), 0x903a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903b_44), 0x903b, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_903c_40), 0x903c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9040_40), 0x9040, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9048_40), 0x9048, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9050_40), 0x9050, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9058_40), 0x9058, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9060_40), 0x9060, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9068_40), 0x9068, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9070_44), 0x9070, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9078_40), 0x9078, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9079_40), 0x9079, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907a_40), 0x907a, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907b_44), 0x907b, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_907c_40), 0x907c, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9080_40), 0x9080, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9088_40), 0x9088, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9090_40), 0x9090, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9098_40), 0x9098, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a0_40), 0x90a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90a8_40), 0x90a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b0_44), 0x90b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b8_40), 0x90b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90b9_40), 0x90b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90ba_40), 0x90ba, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bb_44), 0x90bb, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90bc_40), 0x90bc, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_90c0_40), 0x90c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90c8_40), 0x90c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d0_40), 0x90d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90d8_40), 0x90d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e0_40), 0x90e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90e8_40), 0x90e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f0_44), 0x90f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f8_40), 0x90f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90f9_40), 0x90f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fa_40), 0x90fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fb_44), 0x90fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_90fc_40), 0x90fc, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_9100_40), 0x9100, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9108_40), 0x9108, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9110_40), 0x9110, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9118_40), 0x9118, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9120_40), 0x9120, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9128_40), 0x9128, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9130_44), 0x9130, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9138_40), 0x9138, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9139_40), 0x9139, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9140_40), 0x9140, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9148_40), 0x9148, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9150_40), 0x9150, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9158_40), 0x9158, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9160_40), 0x9160, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9168_40), 0x9168, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9170_44), 0x9170, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9178_40), 0x9178, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9179_40), 0x9179, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9180_40), 0x9180, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9188_40), 0x9188, 2, { 0, 0 }, 0 }, /* SUBX */
+{ CPUFUNC(op_9190_40), 0x9190, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_9198_40), 0x9198, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a0_40), 0x91a0, 2, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91a8_40), 0x91a8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b0_44), 0x91b0, 4, { 4, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b8_40), 0x91b8, 4, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91b9_40), 0x91b9, 6, { 0, 0 }, 0 }, /* SUB */
+{ CPUFUNC(op_91c0_40), 0x91c0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91c8_40), 0x91c8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d0_40), 0x91d0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91d8_40), 0x91d8, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e0_40), 0x91e0, 2, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91e8_40), 0x91e8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f0_44), 0x91f0, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f8_40), 0x91f8, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91f9_40), 0x91f9, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fa_40), 0x91fa, 4, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fb_44), 0x91fb, 4, { 4, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_91fc_40), 0x91fc, 6, { 0, 0 }, 0 }, /* SUBA */
+{ CPUFUNC(op_b000_40), 0xb000, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b010_40), 0xb010, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b018_40), 0xb018, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b020_40), 0xb020, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b028_40), 0xb028, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b030_44), 0xb030, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b038_40), 0xb038, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b039_40), 0xb039, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03a_40), 0xb03a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03b_44), 0xb03b, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b03c_40), 0xb03c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b040_40), 0xb040, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b048_40), 0xb048, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b050_40), 0xb050, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b058_40), 0xb058, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b060_40), 0xb060, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b068_40), 0xb068, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b070_44), 0xb070, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b078_40), 0xb078, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b079_40), 0xb079, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07a_40), 0xb07a, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07b_44), 0xb07b, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b07c_40), 0xb07c, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b080_40), 0xb080, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b088_40), 0xb088, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b090_40), 0xb090, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b098_40), 0xb098, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a0_40), 0xb0a0, 2, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0a8_40), 0xb0a8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b0_44), 0xb0b0, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b8_40), 0xb0b8, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0b9_40), 0xb0b9, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0ba_40), 0xb0ba, 4, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bb_44), 0xb0bb, 4, { 4, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0bc_40), 0xb0bc, 6, { 0, 0 }, 0 }, /* CMP */
+{ CPUFUNC(op_b0c0_40), 0xb0c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0c8_40), 0xb0c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d0_40), 0xb0d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0d8_40), 0xb0d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e0_40), 0xb0e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0e8_40), 0xb0e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f0_44), 0xb0f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f8_40), 0xb0f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0f9_40), 0xb0f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fa_40), 0xb0fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fb_44), 0xb0fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b0fc_40), 0xb0fc, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b100_40), 0xb100, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b108_40), 0xb108, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b110_40), 0xb110, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b118_40), 0xb118, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b120_40), 0xb120, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b128_40), 0xb128, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b130_44), 0xb130, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b138_40), 0xb138, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b139_40), 0xb139, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b140_40), 0xb140, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b148_40), 0xb148, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b150_40), 0xb150, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b158_40), 0xb158, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b160_40), 0xb160, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b168_40), 0xb168, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b170_44), 0xb170, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b178_40), 0xb178, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b179_40), 0xb179, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b180_40), 0xb180, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b188_40), 0xb188, 2, { 0, 0 }, 0 }, /* CMPM */
+{ CPUFUNC(op_b190_40), 0xb190, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b198_40), 0xb198, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a0_40), 0xb1a0, 2, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1a8_40), 0xb1a8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b0_44), 0xb1b0, 4, { 4, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b8_40), 0xb1b8, 4, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1b9_40), 0xb1b9, 6, { 0, 0 }, 0 }, /* EOR */
+{ CPUFUNC(op_b1c0_40), 0xb1c0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1c8_40), 0xb1c8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d0_40), 0xb1d0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1d8_40), 0xb1d8, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e0_40), 0xb1e0, 2, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1e8_40), 0xb1e8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f0_44), 0xb1f0, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f8_40), 0xb1f8, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1f9_40), 0xb1f9, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fa_40), 0xb1fa, 4, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fb_44), 0xb1fb, 4, { 4, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_b1fc_40), 0xb1fc, 6, { 0, 0 }, 0 }, /* CMPA */
+{ CPUFUNC(op_c000_40), 0xc000, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c010_40), 0xc010, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c018_40), 0xc018, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c020_40), 0xc020, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c028_40), 0xc028, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c030_44), 0xc030, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c038_40), 0xc038, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c039_40), 0xc039, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03a_40), 0xc03a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03b_44), 0xc03b, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c03c_40), 0xc03c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c040_40), 0xc040, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c050_40), 0xc050, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c058_40), 0xc058, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c060_40), 0xc060, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c068_40), 0xc068, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c070_44), 0xc070, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c078_40), 0xc078, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c079_40), 0xc079, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07a_40), 0xc07a, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07b_44), 0xc07b, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c07c_40), 0xc07c, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c080_40), 0xc080, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c090_40), 0xc090, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c098_40), 0xc098, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a0_40), 0xc0a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0a8_40), 0xc0a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b0_44), 0xc0b0, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b8_40), 0xc0b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0b9_40), 0xc0b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0ba_40), 0xc0ba, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bb_44), 0xc0bb, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0bc_40), 0xc0bc, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c0c0_40), 0xc0c0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d0_40), 0xc0d0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0d8_40), 0xc0d8, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e0_40), 0xc0e0, 2, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0e8_40), 0xc0e8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f0_44), 0xc0f0, 4, { 4, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f8_40), 0xc0f8, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0f9_40), 0xc0f9, 6, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fa_40), 0xc0fa, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fb_44), 0xc0fb, 4, { 4, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c0fc_40), 0xc0fc, 4, { 0, 0 }, 0 }, /* MULU */
+{ CPUFUNC(op_c100_42), 0xc100, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c108_42), 0xc108, 2, { 0, 0 }, 0 }, /* ABCD */
+{ CPUFUNC(op_c110_40), 0xc110, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c118_40), 0xc118, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c120_40), 0xc120, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c128_40), 0xc128, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c130_44), 0xc130, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c138_40), 0xc138, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c139_40), 0xc139, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c140_40), 0xc140, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c148_40), 0xc148, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c150_40), 0xc150, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c158_40), 0xc158, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c160_40), 0xc160, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c168_40), 0xc168, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c170_44), 0xc170, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c178_40), 0xc178, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c179_40), 0xc179, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c188_40), 0xc188, 2, { 0, 0 }, 0 }, /* EXG */
+{ CPUFUNC(op_c190_40), 0xc190, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c198_40), 0xc198, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a0_40), 0xc1a0, 2, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1a8_40), 0xc1a8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b0_44), 0xc1b0, 4, { 4, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b8_40), 0xc1b8, 4, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1b9_40), 0xc1b9, 6, { 0, 0 }, 0 }, /* AND */
+{ CPUFUNC(op_c1c0_40), 0xc1c0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d0_40), 0xc1d0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1d8_40), 0xc1d8, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e0_40), 0xc1e0, 2, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1e8_40), 0xc1e8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f0_44), 0xc1f0, 4, { 4, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f8_40), 0xc1f8, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1f9_40), 0xc1f9, 6, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fa_40), 0xc1fa, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fb_44), 0xc1fb, 4, { 4, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_c1fc_40), 0xc1fc, 4, { 0, 0 }, 0 }, /* MULS */
+{ CPUFUNC(op_d000_40), 0xd000, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d010_40), 0xd010, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d018_40), 0xd018, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d020_40), 0xd020, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d028_40), 0xd028, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d030_44), 0xd030, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d038_40), 0xd038, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d039_40), 0xd039, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03a_40), 0xd03a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03b_44), 0xd03b, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d03c_40), 0xd03c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d040_40), 0xd040, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d048_40), 0xd048, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d050_40), 0xd050, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d058_40), 0xd058, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d060_40), 0xd060, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d068_40), 0xd068, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d070_44), 0xd070, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d078_40), 0xd078, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d079_40), 0xd079, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07a_40), 0xd07a, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07b_44), 0xd07b, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d07c_40), 0xd07c, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d080_40), 0xd080, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d088_40), 0xd088, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d090_40), 0xd090, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d098_40), 0xd098, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a0_40), 0xd0a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0a8_40), 0xd0a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b0_44), 0xd0b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b8_40), 0xd0b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0b9_40), 0xd0b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0ba_40), 0xd0ba, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bb_44), 0xd0bb, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0bc_40), 0xd0bc, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d0c0_40), 0xd0c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0c8_40), 0xd0c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d0_40), 0xd0d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0d8_40), 0xd0d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e0_40), 0xd0e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0e8_40), 0xd0e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f0_44), 0xd0f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f8_40), 0xd0f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0f9_40), 0xd0f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fa_40), 0xd0fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fb_44), 0xd0fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d0fc_40), 0xd0fc, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d100_40), 0xd100, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d108_40), 0xd108, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d110_40), 0xd110, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d118_40), 0xd118, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d120_40), 0xd120, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d128_40), 0xd128, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d130_44), 0xd130, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d138_40), 0xd138, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d139_40), 0xd139, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d140_40), 0xd140, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d148_40), 0xd148, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d150_40), 0xd150, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d158_40), 0xd158, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d160_40), 0xd160, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d168_40), 0xd168, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d170_44), 0xd170, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d178_40), 0xd178, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d179_40), 0xd179, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d180_40), 0xd180, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d188_40), 0xd188, 2, { 0, 0 }, 0 }, /* ADDX */
+{ CPUFUNC(op_d190_40), 0xd190, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d198_40), 0xd198, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a0_40), 0xd1a0, 2, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1a8_40), 0xd1a8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b0_44), 0xd1b0, 4, { 4, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b8_40), 0xd1b8, 4, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1b9_40), 0xd1b9, 6, { 0, 0 }, 0 }, /* ADD */
+{ CPUFUNC(op_d1c0_40), 0xd1c0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1c8_40), 0xd1c8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d0_40), 0xd1d0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1d8_40), 0xd1d8, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e0_40), 0xd1e0, 2, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1e8_40), 0xd1e8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f0_44), 0xd1f0, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f8_40), 0xd1f8, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1f9_40), 0xd1f9, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fa_40), 0xd1fa, 4, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fb_44), 0xd1fb, 4, { 4, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_d1fc_40), 0xd1fc, 6, { 0, 0 }, 0 }, /* ADDA */
+{ CPUFUNC(op_e000_40), 0xe000, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e008_40), 0xe008, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e010_40), 0xe010, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e018_40), 0xe018, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e020_40), 0xe020, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e028_40), 0xe028, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e030_40), 0xe030, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e038_40), 0xe038, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e040_40), 0xe040, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e048_40), 0xe048, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e050_40), 0xe050, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e058_40), 0xe058, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e060_40), 0xe060, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e068_40), 0xe068, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e070_40), 0xe070, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e078_40), 0xe078, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e080_40), 0xe080, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e088_40), 0xe088, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e090_40), 0xe090, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e098_40), 0xe098, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0a0_40), 0xe0a0, 2, { 0, 0 }, 0 }, /* ASR */
+{ CPUFUNC(op_e0a8_40), 0xe0a8, 2, { 0, 0 }, 0 }, /* LSR */
+{ CPUFUNC(op_e0b0_40), 0xe0b0, 2, { 0, 0 }, 0 }, /* ROXR */
+{ CPUFUNC(op_e0b8_40), 0xe0b8, 2, { 0, 0 }, 0 }, /* ROR */
+{ CPUFUNC(op_e0d0_40), 0xe0d0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0d8_40), 0xe0d8, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e0_40), 0xe0e0, 2, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0e8_40), 0xe0e8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f0_44), 0xe0f0, 4, { 4, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f8_40), 0xe0f8, 4, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e0f9_40), 0xe0f9, 6, { 0, 0 }, 0 }, /* ASRW */
+{ CPUFUNC(op_e100_40), 0xe100, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e108_40), 0xe108, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e110_40), 0xe110, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e118_40), 0xe118, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e120_40), 0xe120, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e128_40), 0xe128, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e130_40), 0xe130, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e138_40), 0xe138, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e140_40), 0xe140, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e148_40), 0xe148, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e150_40), 0xe150, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e158_40), 0xe158, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e160_40), 0xe160, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e168_40), 0xe168, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e170_40), 0xe170, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e178_40), 0xe178, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e180_40), 0xe180, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e188_40), 0xe188, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e190_40), 0xe190, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e198_40), 0xe198, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1a0_40), 0xe1a0, 2, { 0, 0 }, 0 }, /* ASL */
+{ CPUFUNC(op_e1a8_40), 0xe1a8, 2, { 0, 0 }, 0 }, /* LSL */
+{ CPUFUNC(op_e1b0_40), 0xe1b0, 2, { 0, 0 }, 0 }, /* ROXL */
+{ CPUFUNC(op_e1b8_40), 0xe1b8, 2, { 0, 0 }, 0 }, /* ROL */
+{ CPUFUNC(op_e1d0_40), 0xe1d0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1d8_40), 0xe1d8, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e0_40), 0xe1e0, 2, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1e8_40), 0xe1e8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f0_44), 0xe1f0, 4, { 4, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f8_40), 0xe1f8, 4, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e1f9_40), 0xe1f9, 6, { 0, 0 }, 0 }, /* ASLW */
+{ CPUFUNC(op_e2d0_40), 0xe2d0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2d8_40), 0xe2d8, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e0_40), 0xe2e0, 2, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2e8_40), 0xe2e8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f0_44), 0xe2f0, 4, { 4, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f8_40), 0xe2f8, 4, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e2f9_40), 0xe2f9, 6, { 0, 0 }, 0 }, /* LSRW */
+{ CPUFUNC(op_e3d0_40), 0xe3d0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3d8_40), 0xe3d8, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e0_40), 0xe3e0, 2, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3e8_40), 0xe3e8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f0_44), 0xe3f0, 4, { 4, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f8_40), 0xe3f8, 4, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e3f9_40), 0xe3f9, 6, { 0, 0 }, 0 }, /* LSLW */
+{ CPUFUNC(op_e4d0_40), 0xe4d0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4d8_40), 0xe4d8, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e0_40), 0xe4e0, 2, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4e8_40), 0xe4e8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f0_44), 0xe4f0, 4, { 4, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f8_40), 0xe4f8, 4, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e4f9_40), 0xe4f9, 6, { 0, 0 }, 0 }, /* ROXRW */
+{ CPUFUNC(op_e5d0_40), 0xe5d0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5d8_40), 0xe5d8, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e0_40), 0xe5e0, 2, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5e8_40), 0xe5e8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f0_44), 0xe5f0, 4, { 4, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f8_40), 0xe5f8, 4, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e5f9_40), 0xe5f9, 6, { 0, 0 }, 0 }, /* ROXLW */
+{ CPUFUNC(op_e6d0_40), 0xe6d0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6d8_40), 0xe6d8, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e0_40), 0xe6e0, 2, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6e8_40), 0xe6e8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f0_44), 0xe6f0, 4, { 4, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f8_40), 0xe6f8, 4, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e6f9_40), 0xe6f9, 6, { 0, 0 }, 0 }, /* RORW */
+{ CPUFUNC(op_e7d0_40), 0xe7d0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7d8_40), 0xe7d8, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e0_40), 0xe7e0, 2, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7e8_40), 0xe7e8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f0_44), 0xe7f0, 4, { 4, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f8_40), 0xe7f8, 4, { 0, 0 }, 0 }, /* ROLW */
+{ CPUFUNC(op_e7f9_40), 0xe7f9, 6, { 0, 0 }, 0 }, /* ROLW */
+{ 0, 0 }};
+#endif /* CPUEMU_68000_ONLY */
diff --git a/src/cpu/cputbl.h b/src/cpu/cputbl.h
new file mode 100644
index 0000000..91e65f2
--- /dev/null
+++ b/src/cpu/cputbl.h
@@ -0,0 +1,45626 @@
+extern cpuop_func op_0000_0_nf;
+extern cpuop_func op_0000_0_ff;
+extern cpuop_func op_0010_0_nf;
+extern cpuop_func op_0010_0_ff;
+extern cpuop_func op_0018_0_nf;
+extern cpuop_func op_0018_0_ff;
+extern cpuop_func op_0020_0_nf;
+extern cpuop_func op_0020_0_ff;
+extern cpuop_func op_0028_0_nf;
+extern cpuop_func op_0028_0_ff;
+extern cpuop_func op_0030_0_nf;
+extern cpuop_func op_0030_0_ff;
+extern cpuop_func op_0038_0_nf;
+extern cpuop_func op_0038_0_ff;
+extern cpuop_func op_0039_0_nf;
+extern cpuop_func op_0039_0_ff;
+extern cpuop_func op_003c_0_nf;
+extern cpuop_func op_003c_0_ff;
+extern cpuop_func op_0040_0_nf;
+extern cpuop_func op_0040_0_ff;
+extern cpuop_func op_0050_0_nf;
+extern cpuop_func op_0050_0_ff;
+extern cpuop_func op_0058_0_nf;
+extern cpuop_func op_0058_0_ff;
+extern cpuop_func op_0060_0_nf;
+extern cpuop_func op_0060_0_ff;
+extern cpuop_func op_0068_0_nf;
+extern cpuop_func op_0068_0_ff;
+extern cpuop_func op_0070_0_nf;
+extern cpuop_func op_0070_0_ff;
+extern cpuop_func op_0078_0_nf;
+extern cpuop_func op_0078_0_ff;
+extern cpuop_func op_0079_0_nf;
+extern cpuop_func op_0079_0_ff;
+extern cpuop_func op_007c_0_nf;
+extern cpuop_func op_007c_0_ff;
+extern cpuop_func op_0080_0_nf;
+extern cpuop_func op_0080_0_ff;
+extern cpuop_func op_0090_0_nf;
+extern cpuop_func op_0090_0_ff;
+extern cpuop_func op_0098_0_nf;
+extern cpuop_func op_0098_0_ff;
+extern cpuop_func op_00a0_0_nf;
+extern cpuop_func op_00a0_0_ff;
+extern cpuop_func op_00a8_0_nf;
+extern cpuop_func op_00a8_0_ff;
+extern cpuop_func op_00b0_0_nf;
+extern cpuop_func op_00b0_0_ff;
+extern cpuop_func op_00b8_0_nf;
+extern cpuop_func op_00b8_0_ff;
+extern cpuop_func op_00b9_0_nf;
+extern cpuop_func op_00b9_0_ff;
+extern cpuop_func op_00d0_0_nf;
+extern cpuop_func op_00d0_0_ff;
+extern cpuop_func op_00e8_0_nf;
+extern cpuop_func op_00e8_0_ff;
+extern cpuop_func op_00f0_0_nf;
+extern cpuop_func op_00f0_0_ff;
+extern cpuop_func op_00f8_0_nf;
+extern cpuop_func op_00f8_0_ff;
+extern cpuop_func op_00f9_0_nf;
+extern cpuop_func op_00f9_0_ff;
+extern cpuop_func op_00fa_0_nf;
+extern cpuop_func op_00fa_0_ff;
+extern cpuop_func op_00fb_0_nf;
+extern cpuop_func op_00fb_0_ff;
+extern cpuop_func op_0100_0_nf;
+extern cpuop_func op_0100_0_ff;
+extern cpuop_func op_0108_0_nf;
+extern cpuop_func op_0108_0_ff;
+extern cpuop_func op_0110_0_nf;
+extern cpuop_func op_0110_0_ff;
+extern cpuop_func op_0118_0_nf;
+extern cpuop_func op_0118_0_ff;
+extern cpuop_func op_0120_0_nf;
+extern cpuop_func op_0120_0_ff;
+extern cpuop_func op_0128_0_nf;
+extern cpuop_func op_0128_0_ff;
+extern cpuop_func op_0130_0_nf;
+extern cpuop_func op_0130_0_ff;
+extern cpuop_func op_0138_0_nf;
+extern cpuop_func op_0138_0_ff;
+extern cpuop_func op_0139_0_nf;
+extern cpuop_func op_0139_0_ff;
+extern cpuop_func op_013a_0_nf;
+extern cpuop_func op_013a_0_ff;
+extern cpuop_func op_013b_0_nf;
+extern cpuop_func op_013b_0_ff;
+extern cpuop_func op_013c_0_nf;
+extern cpuop_func op_013c_0_ff;
+extern cpuop_func op_0140_0_nf;
+extern cpuop_func op_0140_0_ff;
+extern cpuop_func op_0148_0_nf;
+extern cpuop_func op_0148_0_ff;
+extern cpuop_func op_0150_0_nf;
+extern cpuop_func op_0150_0_ff;
+extern cpuop_func op_0158_0_nf;
+extern cpuop_func op_0158_0_ff;
+extern cpuop_func op_0160_0_nf;
+extern cpuop_func op_0160_0_ff;
+extern cpuop_func op_0168_0_nf;
+extern cpuop_func op_0168_0_ff;
+extern cpuop_func op_0170_0_nf;
+extern cpuop_func op_0170_0_ff;
+extern cpuop_func op_0178_0_nf;
+extern cpuop_func op_0178_0_ff;
+extern cpuop_func op_0179_0_nf;
+extern cpuop_func op_0179_0_ff;
+extern cpuop_func op_0180_0_nf;
+extern cpuop_func op_0180_0_ff;
+extern cpuop_func op_0188_0_nf;
+extern cpuop_func op_0188_0_ff;
+extern cpuop_func op_0190_0_nf;
+extern cpuop_func op_0190_0_ff;
+extern cpuop_func op_0198_0_nf;
+extern cpuop_func op_0198_0_ff;
+extern cpuop_func op_01a0_0_nf;
+extern cpuop_func op_01a0_0_ff;
+extern cpuop_func op_01a8_0_nf;
+extern cpuop_func op_01a8_0_ff;
+extern cpuop_func op_01b0_0_nf;
+extern cpuop_func op_01b0_0_ff;
+extern cpuop_func op_01b8_0_nf;
+extern cpuop_func op_01b8_0_ff;
+extern cpuop_func op_01b9_0_nf;
+extern cpuop_func op_01b9_0_ff;
+extern cpuop_func op_01c0_0_nf;
+extern cpuop_func op_01c0_0_ff;
+extern cpuop_func op_01c8_0_nf;
+extern cpuop_func op_01c8_0_ff;
+extern cpuop_func op_01d0_0_nf;
+extern cpuop_func op_01d0_0_ff;
+extern cpuop_func op_01d8_0_nf;
+extern cpuop_func op_01d8_0_ff;
+extern cpuop_func op_01e0_0_nf;
+extern cpuop_func op_01e0_0_ff;
+extern cpuop_func op_01e8_0_nf;
+extern cpuop_func op_01e8_0_ff;
+extern cpuop_func op_01f0_0_nf;
+extern cpuop_func op_01f0_0_ff;
+extern cpuop_func op_01f8_0_nf;
+extern cpuop_func op_01f8_0_ff;
+extern cpuop_func op_01f9_0_nf;
+extern cpuop_func op_01f9_0_ff;
+extern cpuop_func op_0200_0_nf;
+extern cpuop_func op_0200_0_ff;
+extern cpuop_func op_0210_0_nf;
+extern cpuop_func op_0210_0_ff;
+extern cpuop_func op_0218_0_nf;
+extern cpuop_func op_0218_0_ff;
+extern cpuop_func op_0220_0_nf;
+extern cpuop_func op_0220_0_ff;
+extern cpuop_func op_0228_0_nf;
+extern cpuop_func op_0228_0_ff;
+extern cpuop_func op_0230_0_nf;
+extern cpuop_func op_0230_0_ff;
+extern cpuop_func op_0238_0_nf;
+extern cpuop_func op_0238_0_ff;
+extern cpuop_func op_0239_0_nf;
+extern cpuop_func op_0239_0_ff;
+extern cpuop_func op_023c_0_nf;
+extern cpuop_func op_023c_0_ff;
+extern cpuop_func op_0240_0_nf;
+extern cpuop_func op_0240_0_ff;
+extern cpuop_func op_0250_0_nf;
+extern cpuop_func op_0250_0_ff;
+extern cpuop_func op_0258_0_nf;
+extern cpuop_func op_0258_0_ff;
+extern cpuop_func op_0260_0_nf;
+extern cpuop_func op_0260_0_ff;
+extern cpuop_func op_0268_0_nf;
+extern cpuop_func op_0268_0_ff;
+extern cpuop_func op_0270_0_nf;
+extern cpuop_func op_0270_0_ff;
+extern cpuop_func op_0278_0_nf;
+extern cpuop_func op_0278_0_ff;
+extern cpuop_func op_0279_0_nf;
+extern cpuop_func op_0279_0_ff;
+extern cpuop_func op_027c_0_nf;
+extern cpuop_func op_027c_0_ff;
+extern cpuop_func op_0280_0_nf;
+extern cpuop_func op_0280_0_ff;
+extern cpuop_func op_0290_0_nf;
+extern cpuop_func op_0290_0_ff;
+extern cpuop_func op_0298_0_nf;
+extern cpuop_func op_0298_0_ff;
+extern cpuop_func op_02a0_0_nf;
+extern cpuop_func op_02a0_0_ff;
+extern cpuop_func op_02a8_0_nf;
+extern cpuop_func op_02a8_0_ff;
+extern cpuop_func op_02b0_0_nf;
+extern cpuop_func op_02b0_0_ff;
+extern cpuop_func op_02b8_0_nf;
+extern cpuop_func op_02b8_0_ff;
+extern cpuop_func op_02b9_0_nf;
+extern cpuop_func op_02b9_0_ff;
+extern cpuop_func op_02d0_0_nf;
+extern cpuop_func op_02d0_0_ff;
+extern cpuop_func op_02e8_0_nf;
+extern cpuop_func op_02e8_0_ff;
+extern cpuop_func op_02f0_0_nf;
+extern cpuop_func op_02f0_0_ff;
+extern cpuop_func op_02f8_0_nf;
+extern cpuop_func op_02f8_0_ff;
+extern cpuop_func op_02f9_0_nf;
+extern cpuop_func op_02f9_0_ff;
+extern cpuop_func op_02fa_0_nf;
+extern cpuop_func op_02fa_0_ff;
+extern cpuop_func op_02fb_0_nf;
+extern cpuop_func op_02fb_0_ff;
+extern cpuop_func op_0400_0_nf;
+extern cpuop_func op_0400_0_ff;
+extern cpuop_func op_0410_0_nf;
+extern cpuop_func op_0410_0_ff;
+extern cpuop_func op_0418_0_nf;
+extern cpuop_func op_0418_0_ff;
+extern cpuop_func op_0420_0_nf;
+extern cpuop_func op_0420_0_ff;
+extern cpuop_func op_0428_0_nf;
+extern cpuop_func op_0428_0_ff;
+extern cpuop_func op_0430_0_nf;
+extern cpuop_func op_0430_0_ff;
+extern cpuop_func op_0438_0_nf;
+extern cpuop_func op_0438_0_ff;
+extern cpuop_func op_0439_0_nf;
+extern cpuop_func op_0439_0_ff;
+extern cpuop_func op_0440_0_nf;
+extern cpuop_func op_0440_0_ff;
+extern cpuop_func op_0450_0_nf;
+extern cpuop_func op_0450_0_ff;
+extern cpuop_func op_0458_0_nf;
+extern cpuop_func op_0458_0_ff;
+extern cpuop_func op_0460_0_nf;
+extern cpuop_func op_0460_0_ff;
+extern cpuop_func op_0468_0_nf;
+extern cpuop_func op_0468_0_ff;
+extern cpuop_func op_0470_0_nf;
+extern cpuop_func op_0470_0_ff;
+extern cpuop_func op_0478_0_nf;
+extern cpuop_func op_0478_0_ff;
+extern cpuop_func op_0479_0_nf;
+extern cpuop_func op_0479_0_ff;
+extern cpuop_func op_0480_0_nf;
+extern cpuop_func op_0480_0_ff;
+extern cpuop_func op_0490_0_nf;
+extern cpuop_func op_0490_0_ff;
+extern cpuop_func op_0498_0_nf;
+extern cpuop_func op_0498_0_ff;
+extern cpuop_func op_04a0_0_nf;
+extern cpuop_func op_04a0_0_ff;
+extern cpuop_func op_04a8_0_nf;
+extern cpuop_func op_04a8_0_ff;
+extern cpuop_func op_04b0_0_nf;
+extern cpuop_func op_04b0_0_ff;
+extern cpuop_func op_04b8_0_nf;
+extern cpuop_func op_04b8_0_ff;
+extern cpuop_func op_04b9_0_nf;
+extern cpuop_func op_04b9_0_ff;
+extern cpuop_func op_04d0_0_nf;
+extern cpuop_func op_04d0_0_ff;
+extern cpuop_func op_04e8_0_nf;
+extern cpuop_func op_04e8_0_ff;
+extern cpuop_func op_04f0_0_nf;
+extern cpuop_func op_04f0_0_ff;
+extern cpuop_func op_04f8_0_nf;
+extern cpuop_func op_04f8_0_ff;
+extern cpuop_func op_04f9_0_nf;
+extern cpuop_func op_04f9_0_ff;
+extern cpuop_func op_04fa_0_nf;
+extern cpuop_func op_04fa_0_ff;
+extern cpuop_func op_04fb_0_nf;
+extern cpuop_func op_04fb_0_ff;
+extern cpuop_func op_0600_0_nf;
+extern cpuop_func op_0600_0_ff;
+extern cpuop_func op_0610_0_nf;
+extern cpuop_func op_0610_0_ff;
+extern cpuop_func op_0618_0_nf;
+extern cpuop_func op_0618_0_ff;
+extern cpuop_func op_0620_0_nf;
+extern cpuop_func op_0620_0_ff;
+extern cpuop_func op_0628_0_nf;
+extern cpuop_func op_0628_0_ff;
+extern cpuop_func op_0630_0_nf;
+extern cpuop_func op_0630_0_ff;
+extern cpuop_func op_0638_0_nf;
+extern cpuop_func op_0638_0_ff;
+extern cpuop_func op_0639_0_nf;
+extern cpuop_func op_0639_0_ff;
+extern cpuop_func op_0640_0_nf;
+extern cpuop_func op_0640_0_ff;
+extern cpuop_func op_0650_0_nf;
+extern cpuop_func op_0650_0_ff;
+extern cpuop_func op_0658_0_nf;
+extern cpuop_func op_0658_0_ff;
+extern cpuop_func op_0660_0_nf;
+extern cpuop_func op_0660_0_ff;
+extern cpuop_func op_0668_0_nf;
+extern cpuop_func op_0668_0_ff;
+extern cpuop_func op_0670_0_nf;
+extern cpuop_func op_0670_0_ff;
+extern cpuop_func op_0678_0_nf;
+extern cpuop_func op_0678_0_ff;
+extern cpuop_func op_0679_0_nf;
+extern cpuop_func op_0679_0_ff;
+extern cpuop_func op_0680_0_nf;
+extern cpuop_func op_0680_0_ff;
+extern cpuop_func op_0690_0_nf;
+extern cpuop_func op_0690_0_ff;
+extern cpuop_func op_0698_0_nf;
+extern cpuop_func op_0698_0_ff;
+extern cpuop_func op_06a0_0_nf;
+extern cpuop_func op_06a0_0_ff;
+extern cpuop_func op_06a8_0_nf;
+extern cpuop_func op_06a8_0_ff;
+extern cpuop_func op_06b0_0_nf;
+extern cpuop_func op_06b0_0_ff;
+extern cpuop_func op_06b8_0_nf;
+extern cpuop_func op_06b8_0_ff;
+extern cpuop_func op_06b9_0_nf;
+extern cpuop_func op_06b9_0_ff;
+extern cpuop_func op_06c0_0_nf;
+extern cpuop_func op_06c0_0_ff;
+extern cpuop_func op_06c8_0_nf;
+extern cpuop_func op_06c8_0_ff;
+extern cpuop_func op_06d0_0_nf;
+extern cpuop_func op_06d0_0_ff;
+extern cpuop_func op_06e8_0_nf;
+extern cpuop_func op_06e8_0_ff;
+extern cpuop_func op_06f0_0_nf;
+extern cpuop_func op_06f0_0_ff;
+extern cpuop_func op_06f8_0_nf;
+extern cpuop_func op_06f8_0_ff;
+extern cpuop_func op_06f9_0_nf;
+extern cpuop_func op_06f9_0_ff;
+extern cpuop_func op_06fa_0_nf;
+extern cpuop_func op_06fa_0_ff;
+extern cpuop_func op_06fb_0_nf;
+extern cpuop_func op_06fb_0_ff;
+extern cpuop_func op_0800_0_nf;
+extern cpuop_func op_0800_0_ff;
+extern cpuop_func op_0810_0_nf;
+extern cpuop_func op_0810_0_ff;
+extern cpuop_func op_0818_0_nf;
+extern cpuop_func op_0818_0_ff;
+extern cpuop_func op_0820_0_nf;
+extern cpuop_func op_0820_0_ff;
+extern cpuop_func op_0828_0_nf;
+extern cpuop_func op_0828_0_ff;
+extern cpuop_func op_0830_0_nf;
+extern cpuop_func op_0830_0_ff;
+extern cpuop_func op_0838_0_nf;
+extern cpuop_func op_0838_0_ff;
+extern cpuop_func op_0839_0_nf;
+extern cpuop_func op_0839_0_ff;
+extern cpuop_func op_083a_0_nf;
+extern cpuop_func op_083a_0_ff;
+extern cpuop_func op_083b_0_nf;
+extern cpuop_func op_083b_0_ff;
+extern cpuop_func op_0840_0_nf;
+extern cpuop_func op_0840_0_ff;
+extern cpuop_func op_0850_0_nf;
+extern cpuop_func op_0850_0_ff;
+extern cpuop_func op_0858_0_nf;
+extern cpuop_func op_0858_0_ff;
+extern cpuop_func op_0860_0_nf;
+extern cpuop_func op_0860_0_ff;
+extern cpuop_func op_0868_0_nf;
+extern cpuop_func op_0868_0_ff;
+extern cpuop_func op_0870_0_nf;
+extern cpuop_func op_0870_0_ff;
+extern cpuop_func op_0878_0_nf;
+extern cpuop_func op_0878_0_ff;
+extern cpuop_func op_0879_0_nf;
+extern cpuop_func op_0879_0_ff;
+extern cpuop_func op_0880_0_nf;
+extern cpuop_func op_0880_0_ff;
+extern cpuop_func op_0890_0_nf;
+extern cpuop_func op_0890_0_ff;
+extern cpuop_func op_0898_0_nf;
+extern cpuop_func op_0898_0_ff;
+extern cpuop_func op_08a0_0_nf;
+extern cpuop_func op_08a0_0_ff;
+extern cpuop_func op_08a8_0_nf;
+extern cpuop_func op_08a8_0_ff;
+extern cpuop_func op_08b0_0_nf;
+extern cpuop_func op_08b0_0_ff;
+extern cpuop_func op_08b8_0_nf;
+extern cpuop_func op_08b8_0_ff;
+extern cpuop_func op_08b9_0_nf;
+extern cpuop_func op_08b9_0_ff;
+extern cpuop_func op_08c0_0_nf;
+extern cpuop_func op_08c0_0_ff;
+extern cpuop_func op_08d0_0_nf;
+extern cpuop_func op_08d0_0_ff;
+extern cpuop_func op_08d8_0_nf;
+extern cpuop_func op_08d8_0_ff;
+extern cpuop_func op_08e0_0_nf;
+extern cpuop_func op_08e0_0_ff;
+extern cpuop_func op_08e8_0_nf;
+extern cpuop_func op_08e8_0_ff;
+extern cpuop_func op_08f0_0_nf;
+extern cpuop_func op_08f0_0_ff;
+extern cpuop_func op_08f8_0_nf;
+extern cpuop_func op_08f8_0_ff;
+extern cpuop_func op_08f9_0_nf;
+extern cpuop_func op_08f9_0_ff;
+extern cpuop_func op_0a00_0_nf;
+extern cpuop_func op_0a00_0_ff;
+extern cpuop_func op_0a10_0_nf;
+extern cpuop_func op_0a10_0_ff;
+extern cpuop_func op_0a18_0_nf;
+extern cpuop_func op_0a18_0_ff;
+extern cpuop_func op_0a20_0_nf;
+extern cpuop_func op_0a20_0_ff;
+extern cpuop_func op_0a28_0_nf;
+extern cpuop_func op_0a28_0_ff;
+extern cpuop_func op_0a30_0_nf;
+extern cpuop_func op_0a30_0_ff;
+extern cpuop_func op_0a38_0_nf;
+extern cpuop_func op_0a38_0_ff;
+extern cpuop_func op_0a39_0_nf;
+extern cpuop_func op_0a39_0_ff;
+extern cpuop_func op_0a3c_0_nf;
+extern cpuop_func op_0a3c_0_ff;
+extern cpuop_func op_0a40_0_nf;
+extern cpuop_func op_0a40_0_ff;
+extern cpuop_func op_0a50_0_nf;
+extern cpuop_func op_0a50_0_ff;
+extern cpuop_func op_0a58_0_nf;
+extern cpuop_func op_0a58_0_ff;
+extern cpuop_func op_0a60_0_nf;
+extern cpuop_func op_0a60_0_ff;
+extern cpuop_func op_0a68_0_nf;
+extern cpuop_func op_0a68_0_ff;
+extern cpuop_func op_0a70_0_nf;
+extern cpuop_func op_0a70_0_ff;
+extern cpuop_func op_0a78_0_nf;
+extern cpuop_func op_0a78_0_ff;
+extern cpuop_func op_0a79_0_nf;
+extern cpuop_func op_0a79_0_ff;
+extern cpuop_func op_0a7c_0_nf;
+extern cpuop_func op_0a7c_0_ff;
+extern cpuop_func op_0a80_0_nf;
+extern cpuop_func op_0a80_0_ff;
+extern cpuop_func op_0a90_0_nf;
+extern cpuop_func op_0a90_0_ff;
+extern cpuop_func op_0a98_0_nf;
+extern cpuop_func op_0a98_0_ff;
+extern cpuop_func op_0aa0_0_nf;
+extern cpuop_func op_0aa0_0_ff;
+extern cpuop_func op_0aa8_0_nf;
+extern cpuop_func op_0aa8_0_ff;
+extern cpuop_func op_0ab0_0_nf;
+extern cpuop_func op_0ab0_0_ff;
+extern cpuop_func op_0ab8_0_nf;
+extern cpuop_func op_0ab8_0_ff;
+extern cpuop_func op_0ab9_0_nf;
+extern cpuop_func op_0ab9_0_ff;
+extern cpuop_func op_0ad0_0_nf;
+extern cpuop_func op_0ad0_0_ff;
+extern cpuop_func op_0ad8_0_nf;
+extern cpuop_func op_0ad8_0_ff;
+extern cpuop_func op_0ae0_0_nf;
+extern cpuop_func op_0ae0_0_ff;
+extern cpuop_func op_0ae8_0_nf;
+extern cpuop_func op_0ae8_0_ff;
+extern cpuop_func op_0af0_0_nf;
+extern cpuop_func op_0af0_0_ff;
+extern cpuop_func op_0af8_0_nf;
+extern cpuop_func op_0af8_0_ff;
+extern cpuop_func op_0af9_0_nf;
+extern cpuop_func op_0af9_0_ff;
+extern cpuop_func op_0c00_0_nf;
+extern cpuop_func op_0c00_0_ff;
+extern cpuop_func op_0c10_0_nf;
+extern cpuop_func op_0c10_0_ff;
+extern cpuop_func op_0c18_0_nf;
+extern cpuop_func op_0c18_0_ff;
+extern cpuop_func op_0c20_0_nf;
+extern cpuop_func op_0c20_0_ff;
+extern cpuop_func op_0c28_0_nf;
+extern cpuop_func op_0c28_0_ff;
+extern cpuop_func op_0c30_0_nf;
+extern cpuop_func op_0c30_0_ff;
+extern cpuop_func op_0c38_0_nf;
+extern cpuop_func op_0c38_0_ff;
+extern cpuop_func op_0c39_0_nf;
+extern cpuop_func op_0c39_0_ff;
+extern cpuop_func op_0c3a_0_nf;
+extern cpuop_func op_0c3a_0_ff;
+extern cpuop_func op_0c3b_0_nf;
+extern cpuop_func op_0c3b_0_ff;
+extern cpuop_func op_0c40_0_nf;
+extern cpuop_func op_0c40_0_ff;
+extern cpuop_func op_0c50_0_nf;
+extern cpuop_func op_0c50_0_ff;
+extern cpuop_func op_0c58_0_nf;
+extern cpuop_func op_0c58_0_ff;
+extern cpuop_func op_0c60_0_nf;
+extern cpuop_func op_0c60_0_ff;
+extern cpuop_func op_0c68_0_nf;
+extern cpuop_func op_0c68_0_ff;
+extern cpuop_func op_0c70_0_nf;
+extern cpuop_func op_0c70_0_ff;
+extern cpuop_func op_0c78_0_nf;
+extern cpuop_func op_0c78_0_ff;
+extern cpuop_func op_0c79_0_nf;
+extern cpuop_func op_0c79_0_ff;
+extern cpuop_func op_0c7a_0_nf;
+extern cpuop_func op_0c7a_0_ff;
+extern cpuop_func op_0c7b_0_nf;
+extern cpuop_func op_0c7b_0_ff;
+extern cpuop_func op_0c80_0_nf;
+extern cpuop_func op_0c80_0_ff;
+extern cpuop_func op_0c90_0_nf;
+extern cpuop_func op_0c90_0_ff;
+extern cpuop_func op_0c98_0_nf;
+extern cpuop_func op_0c98_0_ff;
+extern cpuop_func op_0ca0_0_nf;
+extern cpuop_func op_0ca0_0_ff;
+extern cpuop_func op_0ca8_0_nf;
+extern cpuop_func op_0ca8_0_ff;
+extern cpuop_func op_0cb0_0_nf;
+extern cpuop_func op_0cb0_0_ff;
+extern cpuop_func op_0cb8_0_nf;
+extern cpuop_func op_0cb8_0_ff;
+extern cpuop_func op_0cb9_0_nf;
+extern cpuop_func op_0cb9_0_ff;
+extern cpuop_func op_0cba_0_nf;
+extern cpuop_func op_0cba_0_ff;
+extern cpuop_func op_0cbb_0_nf;
+extern cpuop_func op_0cbb_0_ff;
+extern cpuop_func op_0cd0_0_nf;
+extern cpuop_func op_0cd0_0_ff;
+extern cpuop_func op_0cd8_0_nf;
+extern cpuop_func op_0cd8_0_ff;
+extern cpuop_func op_0ce0_0_nf;
+extern cpuop_func op_0ce0_0_ff;
+extern cpuop_func op_0ce8_0_nf;
+extern cpuop_func op_0ce8_0_ff;
+extern cpuop_func op_0cf0_0_nf;
+extern cpuop_func op_0cf0_0_ff;
+extern cpuop_func op_0cf8_0_nf;
+extern cpuop_func op_0cf8_0_ff;
+extern cpuop_func op_0cf9_0_nf;
+extern cpuop_func op_0cf9_0_ff;
+extern cpuop_func op_0cfc_0_nf;
+extern cpuop_func op_0cfc_0_ff;
+extern cpuop_func op_0e10_0_nf;
+extern cpuop_func op_0e10_0_ff;
+extern cpuop_func op_0e18_0_nf;
+extern cpuop_func op_0e18_0_ff;
+extern cpuop_func op_0e20_0_nf;
+extern cpuop_func op_0e20_0_ff;
+extern cpuop_func op_0e28_0_nf;
+extern cpuop_func op_0e28_0_ff;
+extern cpuop_func op_0e30_0_nf;
+extern cpuop_func op_0e30_0_ff;
+extern cpuop_func op_0e38_0_nf;
+extern cpuop_func op_0e38_0_ff;
+extern cpuop_func op_0e39_0_nf;
+extern cpuop_func op_0e39_0_ff;
+extern cpuop_func op_0e50_0_nf;
+extern cpuop_func op_0e50_0_ff;
+extern cpuop_func op_0e58_0_nf;
+extern cpuop_func op_0e58_0_ff;
+extern cpuop_func op_0e60_0_nf;
+extern cpuop_func op_0e60_0_ff;
+extern cpuop_func op_0e68_0_nf;
+extern cpuop_func op_0e68_0_ff;
+extern cpuop_func op_0e70_0_nf;
+extern cpuop_func op_0e70_0_ff;
+extern cpuop_func op_0e78_0_nf;
+extern cpuop_func op_0e78_0_ff;
+extern cpuop_func op_0e79_0_nf;
+extern cpuop_func op_0e79_0_ff;
+extern cpuop_func op_0e90_0_nf;
+extern cpuop_func op_0e90_0_ff;
+extern cpuop_func op_0e98_0_nf;
+extern cpuop_func op_0e98_0_ff;
+extern cpuop_func op_0ea0_0_nf;
+extern cpuop_func op_0ea0_0_ff;
+extern cpuop_func op_0ea8_0_nf;
+extern cpuop_func op_0ea8_0_ff;
+extern cpuop_func op_0eb0_0_nf;
+extern cpuop_func op_0eb0_0_ff;
+extern cpuop_func op_0eb8_0_nf;
+extern cpuop_func op_0eb8_0_ff;
+extern cpuop_func op_0eb9_0_nf;
+extern cpuop_func op_0eb9_0_ff;
+extern cpuop_func op_0ed0_0_nf;
+extern cpuop_func op_0ed0_0_ff;
+extern cpuop_func op_0ed8_0_nf;
+extern cpuop_func op_0ed8_0_ff;
+extern cpuop_func op_0ee0_0_nf;
+extern cpuop_func op_0ee0_0_ff;
+extern cpuop_func op_0ee8_0_nf;
+extern cpuop_func op_0ee8_0_ff;
+extern cpuop_func op_0ef0_0_nf;
+extern cpuop_func op_0ef0_0_ff;
+extern cpuop_func op_0ef8_0_nf;
+extern cpuop_func op_0ef8_0_ff;
+extern cpuop_func op_0ef9_0_nf;
+extern cpuop_func op_0ef9_0_ff;
+extern cpuop_func op_0efc_0_nf;
+extern cpuop_func op_0efc_0_ff;
+extern cpuop_func op_1000_0_nf;
+extern cpuop_func op_1000_0_ff;
+extern cpuop_func op_1010_0_nf;
+extern cpuop_func op_1010_0_ff;
+extern cpuop_func op_1018_0_nf;
+extern cpuop_func op_1018_0_ff;
+extern cpuop_func op_1020_0_nf;
+extern cpuop_func op_1020_0_ff;
+extern cpuop_func op_1028_0_nf;
+extern cpuop_func op_1028_0_ff;
+extern cpuop_func op_1030_0_nf;
+extern cpuop_func op_1030_0_ff;
+extern cpuop_func op_1038_0_nf;
+extern cpuop_func op_1038_0_ff;
+extern cpuop_func op_1039_0_nf;
+extern cpuop_func op_1039_0_ff;
+extern cpuop_func op_103a_0_nf;
+extern cpuop_func op_103a_0_ff;
+extern cpuop_func op_103b_0_nf;
+extern cpuop_func op_103b_0_ff;
+extern cpuop_func op_103c_0_nf;
+extern cpuop_func op_103c_0_ff;
+extern cpuop_func op_1080_0_nf;
+extern cpuop_func op_1080_0_ff;
+extern cpuop_func op_1090_0_nf;
+extern cpuop_func op_1090_0_ff;
+extern cpuop_func op_1098_0_nf;
+extern cpuop_func op_1098_0_ff;
+extern cpuop_func op_10a0_0_nf;
+extern cpuop_func op_10a0_0_ff;
+extern cpuop_func op_10a8_0_nf;
+extern cpuop_func op_10a8_0_ff;
+extern cpuop_func op_10b0_0_nf;
+extern cpuop_func op_10b0_0_ff;
+extern cpuop_func op_10b8_0_nf;
+extern cpuop_func op_10b8_0_ff;
+extern cpuop_func op_10b9_0_nf;
+extern cpuop_func op_10b9_0_ff;
+extern cpuop_func op_10ba_0_nf;
+extern cpuop_func op_10ba_0_ff;
+extern cpuop_func op_10bb_0_nf;
+extern cpuop_func op_10bb_0_ff;
+extern cpuop_func op_10bc_0_nf;
+extern cpuop_func op_10bc_0_ff;
+extern cpuop_func op_10c0_0_nf;
+extern cpuop_func op_10c0_0_ff;
+extern cpuop_func op_10d0_0_nf;
+extern cpuop_func op_10d0_0_ff;
+extern cpuop_func op_10d8_0_nf;
+extern cpuop_func op_10d8_0_ff;
+extern cpuop_func op_10e0_0_nf;
+extern cpuop_func op_10e0_0_ff;
+extern cpuop_func op_10e8_0_nf;
+extern cpuop_func op_10e8_0_ff;
+extern cpuop_func op_10f0_0_nf;
+extern cpuop_func op_10f0_0_ff;
+extern cpuop_func op_10f8_0_nf;
+extern cpuop_func op_10f8_0_ff;
+extern cpuop_func op_10f9_0_nf;
+extern cpuop_func op_10f9_0_ff;
+extern cpuop_func op_10fa_0_nf;
+extern cpuop_func op_10fa_0_ff;
+extern cpuop_func op_10fb_0_nf;
+extern cpuop_func op_10fb_0_ff;
+extern cpuop_func op_10fc_0_nf;
+extern cpuop_func op_10fc_0_ff;
+extern cpuop_func op_1100_0_nf;
+extern cpuop_func op_1100_0_ff;
+extern cpuop_func op_1110_0_nf;
+extern cpuop_func op_1110_0_ff;
+extern cpuop_func op_1118_0_nf;
+extern cpuop_func op_1118_0_ff;
+extern cpuop_func op_1120_0_nf;
+extern cpuop_func op_1120_0_ff;
+extern cpuop_func op_1128_0_nf;
+extern cpuop_func op_1128_0_ff;
+extern cpuop_func op_1130_0_nf;
+extern cpuop_func op_1130_0_ff;
+extern cpuop_func op_1138_0_nf;
+extern cpuop_func op_1138_0_ff;
+extern cpuop_func op_1139_0_nf;
+extern cpuop_func op_1139_0_ff;
+extern cpuop_func op_113a_0_nf;
+extern cpuop_func op_113a_0_ff;
+extern cpuop_func op_113b_0_nf;
+extern cpuop_func op_113b_0_ff;
+extern cpuop_func op_113c_0_nf;
+extern cpuop_func op_113c_0_ff;
+extern cpuop_func op_1140_0_nf;
+extern cpuop_func op_1140_0_ff;
+extern cpuop_func op_1150_0_nf;
+extern cpuop_func op_1150_0_ff;
+extern cpuop_func op_1158_0_nf;
+extern cpuop_func op_1158_0_ff;
+extern cpuop_func op_1160_0_nf;
+extern cpuop_func op_1160_0_ff;
+extern cpuop_func op_1168_0_nf;
+extern cpuop_func op_1168_0_ff;
+extern cpuop_func op_1170_0_nf;
+extern cpuop_func op_1170_0_ff;
+extern cpuop_func op_1178_0_nf;
+extern cpuop_func op_1178_0_ff;
+extern cpuop_func op_1179_0_nf;
+extern cpuop_func op_1179_0_ff;
+extern cpuop_func op_117a_0_nf;
+extern cpuop_func op_117a_0_ff;
+extern cpuop_func op_117b_0_nf;
+extern cpuop_func op_117b_0_ff;
+extern cpuop_func op_117c_0_nf;
+extern cpuop_func op_117c_0_ff;
+extern cpuop_func op_1180_0_nf;
+extern cpuop_func op_1180_0_ff;
+extern cpuop_func op_1190_0_nf;
+extern cpuop_func op_1190_0_ff;
+extern cpuop_func op_1198_0_nf;
+extern cpuop_func op_1198_0_ff;
+extern cpuop_func op_11a0_0_nf;
+extern cpuop_func op_11a0_0_ff;
+extern cpuop_func op_11a8_0_nf;
+extern cpuop_func op_11a8_0_ff;
+extern cpuop_func op_11b0_0_nf;
+extern cpuop_func op_11b0_0_ff;
+extern cpuop_func op_11b8_0_nf;
+extern cpuop_func op_11b8_0_ff;
+extern cpuop_func op_11b9_0_nf;
+extern cpuop_func op_11b9_0_ff;
+extern cpuop_func op_11ba_0_nf;
+extern cpuop_func op_11ba_0_ff;
+extern cpuop_func op_11bb_0_nf;
+extern cpuop_func op_11bb_0_ff;
+extern cpuop_func op_11bc_0_nf;
+extern cpuop_func op_11bc_0_ff;
+extern cpuop_func op_11c0_0_nf;
+extern cpuop_func op_11c0_0_ff;
+extern cpuop_func op_11d0_0_nf;
+extern cpuop_func op_11d0_0_ff;
+extern cpuop_func op_11d8_0_nf;
+extern cpuop_func op_11d8_0_ff;
+extern cpuop_func op_11e0_0_nf;
+extern cpuop_func op_11e0_0_ff;
+extern cpuop_func op_11e8_0_nf;
+extern cpuop_func op_11e8_0_ff;
+extern cpuop_func op_11f0_0_nf;
+extern cpuop_func op_11f0_0_ff;
+extern cpuop_func op_11f8_0_nf;
+extern cpuop_func op_11f8_0_ff;
+extern cpuop_func op_11f9_0_nf;
+extern cpuop_func op_11f9_0_ff;
+extern cpuop_func op_11fa_0_nf;
+extern cpuop_func op_11fa_0_ff;
+extern cpuop_func op_11fb_0_nf;
+extern cpuop_func op_11fb_0_ff;
+extern cpuop_func op_11fc_0_nf;
+extern cpuop_func op_11fc_0_ff;
+extern cpuop_func op_13c0_0_nf;
+extern cpuop_func op_13c0_0_ff;
+extern cpuop_func op_13d0_0_nf;
+extern cpuop_func op_13d0_0_ff;
+extern cpuop_func op_13d8_0_nf;
+extern cpuop_func op_13d8_0_ff;
+extern cpuop_func op_13e0_0_nf;
+extern cpuop_func op_13e0_0_ff;
+extern cpuop_func op_13e8_0_nf;
+extern cpuop_func op_13e8_0_ff;
+extern cpuop_func op_13f0_0_nf;
+extern cpuop_func op_13f0_0_ff;
+extern cpuop_func op_13f8_0_nf;
+extern cpuop_func op_13f8_0_ff;
+extern cpuop_func op_13f9_0_nf;
+extern cpuop_func op_13f9_0_ff;
+extern cpuop_func op_13fa_0_nf;
+extern cpuop_func op_13fa_0_ff;
+extern cpuop_func op_13fb_0_nf;
+extern cpuop_func op_13fb_0_ff;
+extern cpuop_func op_13fc_0_nf;
+extern cpuop_func op_13fc_0_ff;
+extern cpuop_func op_2000_0_nf;
+extern cpuop_func op_2000_0_ff;
+extern cpuop_func op_2008_0_nf;
+extern cpuop_func op_2008_0_ff;
+extern cpuop_func op_2010_0_nf;
+extern cpuop_func op_2010_0_ff;
+extern cpuop_func op_2018_0_nf;
+extern cpuop_func op_2018_0_ff;
+extern cpuop_func op_2020_0_nf;
+extern cpuop_func op_2020_0_ff;
+extern cpuop_func op_2028_0_nf;
+extern cpuop_func op_2028_0_ff;
+extern cpuop_func op_2030_0_nf;
+extern cpuop_func op_2030_0_ff;
+extern cpuop_func op_2038_0_nf;
+extern cpuop_func op_2038_0_ff;
+extern cpuop_func op_2039_0_nf;
+extern cpuop_func op_2039_0_ff;
+extern cpuop_func op_203a_0_nf;
+extern cpuop_func op_203a_0_ff;
+extern cpuop_func op_203b_0_nf;
+extern cpuop_func op_203b_0_ff;
+extern cpuop_func op_203c_0_nf;
+extern cpuop_func op_203c_0_ff;
+extern cpuop_func op_2040_0_nf;
+extern cpuop_func op_2040_0_ff;
+extern cpuop_func op_2048_0_nf;
+extern cpuop_func op_2048_0_ff;
+extern cpuop_func op_2050_0_nf;
+extern cpuop_func op_2050_0_ff;
+extern cpuop_func op_2058_0_nf;
+extern cpuop_func op_2058_0_ff;
+extern cpuop_func op_2060_0_nf;
+extern cpuop_func op_2060_0_ff;
+extern cpuop_func op_2068_0_nf;
+extern cpuop_func op_2068_0_ff;
+extern cpuop_func op_2070_0_nf;
+extern cpuop_func op_2070_0_ff;
+extern cpuop_func op_2078_0_nf;
+extern cpuop_func op_2078_0_ff;
+extern cpuop_func op_2079_0_nf;
+extern cpuop_func op_2079_0_ff;
+extern cpuop_func op_207a_0_nf;
+extern cpuop_func op_207a_0_ff;
+extern cpuop_func op_207b_0_nf;
+extern cpuop_func op_207b_0_ff;
+extern cpuop_func op_207c_0_nf;
+extern cpuop_func op_207c_0_ff;
+extern cpuop_func op_2080_0_nf;
+extern cpuop_func op_2080_0_ff;
+extern cpuop_func op_2088_0_nf;
+extern cpuop_func op_2088_0_ff;
+extern cpuop_func op_2090_0_nf;
+extern cpuop_func op_2090_0_ff;
+extern cpuop_func op_2098_0_nf;
+extern cpuop_func op_2098_0_ff;
+extern cpuop_func op_20a0_0_nf;
+extern cpuop_func op_20a0_0_ff;
+extern cpuop_func op_20a8_0_nf;
+extern cpuop_func op_20a8_0_ff;
+extern cpuop_func op_20b0_0_nf;
+extern cpuop_func op_20b0_0_ff;
+extern cpuop_func op_20b8_0_nf;
+extern cpuop_func op_20b8_0_ff;
+extern cpuop_func op_20b9_0_nf;
+extern cpuop_func op_20b9_0_ff;
+extern cpuop_func op_20ba_0_nf;
+extern cpuop_func op_20ba_0_ff;
+extern cpuop_func op_20bb_0_nf;
+extern cpuop_func op_20bb_0_ff;
+extern cpuop_func op_20bc_0_nf;
+extern cpuop_func op_20bc_0_ff;
+extern cpuop_func op_20c0_0_nf;
+extern cpuop_func op_20c0_0_ff;
+extern cpuop_func op_20c8_0_nf;
+extern cpuop_func op_20c8_0_ff;
+extern cpuop_func op_20d0_0_nf;
+extern cpuop_func op_20d0_0_ff;
+extern cpuop_func op_20d8_0_nf;
+extern cpuop_func op_20d8_0_ff;
+extern cpuop_func op_20e0_0_nf;
+extern cpuop_func op_20e0_0_ff;
+extern cpuop_func op_20e8_0_nf;
+extern cpuop_func op_20e8_0_ff;
+extern cpuop_func op_20f0_0_nf;
+extern cpuop_func op_20f0_0_ff;
+extern cpuop_func op_20f8_0_nf;
+extern cpuop_func op_20f8_0_ff;
+extern cpuop_func op_20f9_0_nf;
+extern cpuop_func op_20f9_0_ff;
+extern cpuop_func op_20fa_0_nf;
+extern cpuop_func op_20fa_0_ff;
+extern cpuop_func op_20fb_0_nf;
+extern cpuop_func op_20fb_0_ff;
+extern cpuop_func op_20fc_0_nf;
+extern cpuop_func op_20fc_0_ff;
+extern cpuop_func op_2100_0_nf;
+extern cpuop_func op_2100_0_ff;
+extern cpuop_func op_2108_0_nf;
+extern cpuop_func op_2108_0_ff;
+extern cpuop_func op_2110_0_nf;
+extern cpuop_func op_2110_0_ff;
+extern cpuop_func op_2118_0_nf;
+extern cpuop_func op_2118_0_ff;
+extern cpuop_func op_2120_0_nf;
+extern cpuop_func op_2120_0_ff;
+extern cpuop_func op_2128_0_nf;
+extern cpuop_func op_2128_0_ff;
+extern cpuop_func op_2130_0_nf;
+extern cpuop_func op_2130_0_ff;
+extern cpuop_func op_2138_0_nf;
+extern cpuop_func op_2138_0_ff;
+extern cpuop_func op_2139_0_nf;
+extern cpuop_func op_2139_0_ff;
+extern cpuop_func op_213a_0_nf;
+extern cpuop_func op_213a_0_ff;
+extern cpuop_func op_213b_0_nf;
+extern cpuop_func op_213b_0_ff;
+extern cpuop_func op_213c_0_nf;
+extern cpuop_func op_213c_0_ff;
+extern cpuop_func op_2140_0_nf;
+extern cpuop_func op_2140_0_ff;
+extern cpuop_func op_2148_0_nf;
+extern cpuop_func op_2148_0_ff;
+extern cpuop_func op_2150_0_nf;
+extern cpuop_func op_2150_0_ff;
+extern cpuop_func op_2158_0_nf;
+extern cpuop_func op_2158_0_ff;
+extern cpuop_func op_2160_0_nf;
+extern cpuop_func op_2160_0_ff;
+extern cpuop_func op_2168_0_nf;
+extern cpuop_func op_2168_0_ff;
+extern cpuop_func op_2170_0_nf;
+extern cpuop_func op_2170_0_ff;
+extern cpuop_func op_2178_0_nf;
+extern cpuop_func op_2178_0_ff;
+extern cpuop_func op_2179_0_nf;
+extern cpuop_func op_2179_0_ff;
+extern cpuop_func op_217a_0_nf;
+extern cpuop_func op_217a_0_ff;
+extern cpuop_func op_217b_0_nf;
+extern cpuop_func op_217b_0_ff;
+extern cpuop_func op_217c_0_nf;
+extern cpuop_func op_217c_0_ff;
+extern cpuop_func op_2180_0_nf;
+extern cpuop_func op_2180_0_ff;
+extern cpuop_func op_2188_0_nf;
+extern cpuop_func op_2188_0_ff;
+extern cpuop_func op_2190_0_nf;
+extern cpuop_func op_2190_0_ff;
+extern cpuop_func op_2198_0_nf;
+extern cpuop_func op_2198_0_ff;
+extern cpuop_func op_21a0_0_nf;
+extern cpuop_func op_21a0_0_ff;
+extern cpuop_func op_21a8_0_nf;
+extern cpuop_func op_21a8_0_ff;
+extern cpuop_func op_21b0_0_nf;
+extern cpuop_func op_21b0_0_ff;
+extern cpuop_func op_21b8_0_nf;
+extern cpuop_func op_21b8_0_ff;
+extern cpuop_func op_21b9_0_nf;
+extern cpuop_func op_21b9_0_ff;
+extern cpuop_func op_21ba_0_nf;
+extern cpuop_func op_21ba_0_ff;
+extern cpuop_func op_21bb_0_nf;
+extern cpuop_func op_21bb_0_ff;
+extern cpuop_func op_21bc_0_nf;
+extern cpuop_func op_21bc_0_ff;
+extern cpuop_func op_21c0_0_nf;
+extern cpuop_func op_21c0_0_ff;
+extern cpuop_func op_21c8_0_nf;
+extern cpuop_func op_21c8_0_ff;
+extern cpuop_func op_21d0_0_nf;
+extern cpuop_func op_21d0_0_ff;
+extern cpuop_func op_21d8_0_nf;
+extern cpuop_func op_21d8_0_ff;
+extern cpuop_func op_21e0_0_nf;
+extern cpuop_func op_21e0_0_ff;
+extern cpuop_func op_21e8_0_nf;
+extern cpuop_func op_21e8_0_ff;
+extern cpuop_func op_21f0_0_nf;
+extern cpuop_func op_21f0_0_ff;
+extern cpuop_func op_21f8_0_nf;
+extern cpuop_func op_21f8_0_ff;
+extern cpuop_func op_21f9_0_nf;
+extern cpuop_func op_21f9_0_ff;
+extern cpuop_func op_21fa_0_nf;
+extern cpuop_func op_21fa_0_ff;
+extern cpuop_func op_21fb_0_nf;
+extern cpuop_func op_21fb_0_ff;
+extern cpuop_func op_21fc_0_nf;
+extern cpuop_func op_21fc_0_ff;
+extern cpuop_func op_23c0_0_nf;
+extern cpuop_func op_23c0_0_ff;
+extern cpuop_func op_23c8_0_nf;
+extern cpuop_func op_23c8_0_ff;
+extern cpuop_func op_23d0_0_nf;
+extern cpuop_func op_23d0_0_ff;
+extern cpuop_func op_23d8_0_nf;
+extern cpuop_func op_23d8_0_ff;
+extern cpuop_func op_23e0_0_nf;
+extern cpuop_func op_23e0_0_ff;
+extern cpuop_func op_23e8_0_nf;
+extern cpuop_func op_23e8_0_ff;
+extern cpuop_func op_23f0_0_nf;
+extern cpuop_func op_23f0_0_ff;
+extern cpuop_func op_23f8_0_nf;
+extern cpuop_func op_23f8_0_ff;
+extern cpuop_func op_23f9_0_nf;
+extern cpuop_func op_23f9_0_ff;
+extern cpuop_func op_23fa_0_nf;
+extern cpuop_func op_23fa_0_ff;
+extern cpuop_func op_23fb_0_nf;
+extern cpuop_func op_23fb_0_ff;
+extern cpuop_func op_23fc_0_nf;
+extern cpuop_func op_23fc_0_ff;
+extern cpuop_func op_3000_0_nf;
+extern cpuop_func op_3000_0_ff;
+extern cpuop_func op_3008_0_nf;
+extern cpuop_func op_3008_0_ff;
+extern cpuop_func op_3010_0_nf;
+extern cpuop_func op_3010_0_ff;
+extern cpuop_func op_3018_0_nf;
+extern cpuop_func op_3018_0_ff;
+extern cpuop_func op_3020_0_nf;
+extern cpuop_func op_3020_0_ff;
+extern cpuop_func op_3028_0_nf;
+extern cpuop_func op_3028_0_ff;
+extern cpuop_func op_3030_0_nf;
+extern cpuop_func op_3030_0_ff;
+extern cpuop_func op_3038_0_nf;
+extern cpuop_func op_3038_0_ff;
+extern cpuop_func op_3039_0_nf;
+extern cpuop_func op_3039_0_ff;
+extern cpuop_func op_303a_0_nf;
+extern cpuop_func op_303a_0_ff;
+extern cpuop_func op_303b_0_nf;
+extern cpuop_func op_303b_0_ff;
+extern cpuop_func op_303c_0_nf;
+extern cpuop_func op_303c_0_ff;
+extern cpuop_func op_3040_0_nf;
+extern cpuop_func op_3040_0_ff;
+extern cpuop_func op_3048_0_nf;
+extern cpuop_func op_3048_0_ff;
+extern cpuop_func op_3050_0_nf;
+extern cpuop_func op_3050_0_ff;
+extern cpuop_func op_3058_0_nf;
+extern cpuop_func op_3058_0_ff;
+extern cpuop_func op_3060_0_nf;
+extern cpuop_func op_3060_0_ff;
+extern cpuop_func op_3068_0_nf;
+extern cpuop_func op_3068_0_ff;
+extern cpuop_func op_3070_0_nf;
+extern cpuop_func op_3070_0_ff;
+extern cpuop_func op_3078_0_nf;
+extern cpuop_func op_3078_0_ff;
+extern cpuop_func op_3079_0_nf;
+extern cpuop_func op_3079_0_ff;
+extern cpuop_func op_307a_0_nf;
+extern cpuop_func op_307a_0_ff;
+extern cpuop_func op_307b_0_nf;
+extern cpuop_func op_307b_0_ff;
+extern cpuop_func op_307c_0_nf;
+extern cpuop_func op_307c_0_ff;
+extern cpuop_func op_3080_0_nf;
+extern cpuop_func op_3080_0_ff;
+extern cpuop_func op_3088_0_nf;
+extern cpuop_func op_3088_0_ff;
+extern cpuop_func op_3090_0_nf;
+extern cpuop_func op_3090_0_ff;
+extern cpuop_func op_3098_0_nf;
+extern cpuop_func op_3098_0_ff;
+extern cpuop_func op_30a0_0_nf;
+extern cpuop_func op_30a0_0_ff;
+extern cpuop_func op_30a8_0_nf;
+extern cpuop_func op_30a8_0_ff;
+extern cpuop_func op_30b0_0_nf;
+extern cpuop_func op_30b0_0_ff;
+extern cpuop_func op_30b8_0_nf;
+extern cpuop_func op_30b8_0_ff;
+extern cpuop_func op_30b9_0_nf;
+extern cpuop_func op_30b9_0_ff;
+extern cpuop_func op_30ba_0_nf;
+extern cpuop_func op_30ba_0_ff;
+extern cpuop_func op_30bb_0_nf;
+extern cpuop_func op_30bb_0_ff;
+extern cpuop_func op_30bc_0_nf;
+extern cpuop_func op_30bc_0_ff;
+extern cpuop_func op_30c0_0_nf;
+extern cpuop_func op_30c0_0_ff;
+extern cpuop_func op_30c8_0_nf;
+extern cpuop_func op_30c8_0_ff;
+extern cpuop_func op_30d0_0_nf;
+extern cpuop_func op_30d0_0_ff;
+extern cpuop_func op_30d8_0_nf;
+extern cpuop_func op_30d8_0_ff;
+extern cpuop_func op_30e0_0_nf;
+extern cpuop_func op_30e0_0_ff;
+extern cpuop_func op_30e8_0_nf;
+extern cpuop_func op_30e8_0_ff;
+extern cpuop_func op_30f0_0_nf;
+extern cpuop_func op_30f0_0_ff;
+extern cpuop_func op_30f8_0_nf;
+extern cpuop_func op_30f8_0_ff;
+extern cpuop_func op_30f9_0_nf;
+extern cpuop_func op_30f9_0_ff;
+extern cpuop_func op_30fa_0_nf;
+extern cpuop_func op_30fa_0_ff;
+extern cpuop_func op_30fb_0_nf;
+extern cpuop_func op_30fb_0_ff;
+extern cpuop_func op_30fc_0_nf;
+extern cpuop_func op_30fc_0_ff;
+extern cpuop_func op_3100_0_nf;
+extern cpuop_func op_3100_0_ff;
+extern cpuop_func op_3108_0_nf;
+extern cpuop_func op_3108_0_ff;
+extern cpuop_func op_3110_0_nf;
+extern cpuop_func op_3110_0_ff;
+extern cpuop_func op_3118_0_nf;
+extern cpuop_func op_3118_0_ff;
+extern cpuop_func op_3120_0_nf;
+extern cpuop_func op_3120_0_ff;
+extern cpuop_func op_3128_0_nf;
+extern cpuop_func op_3128_0_ff;
+extern cpuop_func op_3130_0_nf;
+extern cpuop_func op_3130_0_ff;
+extern cpuop_func op_3138_0_nf;
+extern cpuop_func op_3138_0_ff;
+extern cpuop_func op_3139_0_nf;
+extern cpuop_func op_3139_0_ff;
+extern cpuop_func op_313a_0_nf;
+extern cpuop_func op_313a_0_ff;
+extern cpuop_func op_313b_0_nf;
+extern cpuop_func op_313b_0_ff;
+extern cpuop_func op_313c_0_nf;
+extern cpuop_func op_313c_0_ff;
+extern cpuop_func op_3140_0_nf;
+extern cpuop_func op_3140_0_ff;
+extern cpuop_func op_3148_0_nf;
+extern cpuop_func op_3148_0_ff;
+extern cpuop_func op_3150_0_nf;
+extern cpuop_func op_3150_0_ff;
+extern cpuop_func op_3158_0_nf;
+extern cpuop_func op_3158_0_ff;
+extern cpuop_func op_3160_0_nf;
+extern cpuop_func op_3160_0_ff;
+extern cpuop_func op_3168_0_nf;
+extern cpuop_func op_3168_0_ff;
+extern cpuop_func op_3170_0_nf;
+extern cpuop_func op_3170_0_ff;
+extern cpuop_func op_3178_0_nf;
+extern cpuop_func op_3178_0_ff;
+extern cpuop_func op_3179_0_nf;
+extern cpuop_func op_3179_0_ff;
+extern cpuop_func op_317a_0_nf;
+extern cpuop_func op_317a_0_ff;
+extern cpuop_func op_317b_0_nf;
+extern cpuop_func op_317b_0_ff;
+extern cpuop_func op_317c_0_nf;
+extern cpuop_func op_317c_0_ff;
+extern cpuop_func op_3180_0_nf;
+extern cpuop_func op_3180_0_ff;
+extern cpuop_func op_3188_0_nf;
+extern cpuop_func op_3188_0_ff;
+extern cpuop_func op_3190_0_nf;
+extern cpuop_func op_3190_0_ff;
+extern cpuop_func op_3198_0_nf;
+extern cpuop_func op_3198_0_ff;
+extern cpuop_func op_31a0_0_nf;
+extern cpuop_func op_31a0_0_ff;
+extern cpuop_func op_31a8_0_nf;
+extern cpuop_func op_31a8_0_ff;
+extern cpuop_func op_31b0_0_nf;
+extern cpuop_func op_31b0_0_ff;
+extern cpuop_func op_31b8_0_nf;
+extern cpuop_func op_31b8_0_ff;
+extern cpuop_func op_31b9_0_nf;
+extern cpuop_func op_31b9_0_ff;
+extern cpuop_func op_31ba_0_nf;
+extern cpuop_func op_31ba_0_ff;
+extern cpuop_func op_31bb_0_nf;
+extern cpuop_func op_31bb_0_ff;
+extern cpuop_func op_31bc_0_nf;
+extern cpuop_func op_31bc_0_ff;
+extern cpuop_func op_31c0_0_nf;
+extern cpuop_func op_31c0_0_ff;
+extern cpuop_func op_31c8_0_nf;
+extern cpuop_func op_31c8_0_ff;
+extern cpuop_func op_31d0_0_nf;
+extern cpuop_func op_31d0_0_ff;
+extern cpuop_func op_31d8_0_nf;
+extern cpuop_func op_31d8_0_ff;
+extern cpuop_func op_31e0_0_nf;
+extern cpuop_func op_31e0_0_ff;
+extern cpuop_func op_31e8_0_nf;
+extern cpuop_func op_31e8_0_ff;
+extern cpuop_func op_31f0_0_nf;
+extern cpuop_func op_31f0_0_ff;
+extern cpuop_func op_31f8_0_nf;
+extern cpuop_func op_31f8_0_ff;
+extern cpuop_func op_31f9_0_nf;
+extern cpuop_func op_31f9_0_ff;
+extern cpuop_func op_31fa_0_nf;
+extern cpuop_func op_31fa_0_ff;
+extern cpuop_func op_31fb_0_nf;
+extern cpuop_func op_31fb_0_ff;
+extern cpuop_func op_31fc_0_nf;
+extern cpuop_func op_31fc_0_ff;
+extern cpuop_func op_33c0_0_nf;
+extern cpuop_func op_33c0_0_ff;
+extern cpuop_func op_33c8_0_nf;
+extern cpuop_func op_33c8_0_ff;
+extern cpuop_func op_33d0_0_nf;
+extern cpuop_func op_33d0_0_ff;
+extern cpuop_func op_33d8_0_nf;
+extern cpuop_func op_33d8_0_ff;
+extern cpuop_func op_33e0_0_nf;
+extern cpuop_func op_33e0_0_ff;
+extern cpuop_func op_33e8_0_nf;
+extern cpuop_func op_33e8_0_ff;
+extern cpuop_func op_33f0_0_nf;
+extern cpuop_func op_33f0_0_ff;
+extern cpuop_func op_33f8_0_nf;
+extern cpuop_func op_33f8_0_ff;
+extern cpuop_func op_33f9_0_nf;
+extern cpuop_func op_33f9_0_ff;
+extern cpuop_func op_33fa_0_nf;
+extern cpuop_func op_33fa_0_ff;
+extern cpuop_func op_33fb_0_nf;
+extern cpuop_func op_33fb_0_ff;
+extern cpuop_func op_33fc_0_nf;
+extern cpuop_func op_33fc_0_ff;
+extern cpuop_func op_4000_0_nf;
+extern cpuop_func op_4000_0_ff;
+extern cpuop_func op_4010_0_nf;
+extern cpuop_func op_4010_0_ff;
+extern cpuop_func op_4018_0_nf;
+extern cpuop_func op_4018_0_ff;
+extern cpuop_func op_4020_0_nf;
+extern cpuop_func op_4020_0_ff;
+extern cpuop_func op_4028_0_nf;
+extern cpuop_func op_4028_0_ff;
+extern cpuop_func op_4030_0_nf;
+extern cpuop_func op_4030_0_ff;
+extern cpuop_func op_4038_0_nf;
+extern cpuop_func op_4038_0_ff;
+extern cpuop_func op_4039_0_nf;
+extern cpuop_func op_4039_0_ff;
+extern cpuop_func op_4040_0_nf;
+extern cpuop_func op_4040_0_ff;
+extern cpuop_func op_4050_0_nf;
+extern cpuop_func op_4050_0_ff;
+extern cpuop_func op_4058_0_nf;
+extern cpuop_func op_4058_0_ff;
+extern cpuop_func op_4060_0_nf;
+extern cpuop_func op_4060_0_ff;
+extern cpuop_func op_4068_0_nf;
+extern cpuop_func op_4068_0_ff;
+extern cpuop_func op_4070_0_nf;
+extern cpuop_func op_4070_0_ff;
+extern cpuop_func op_4078_0_nf;
+extern cpuop_func op_4078_0_ff;
+extern cpuop_func op_4079_0_nf;
+extern cpuop_func op_4079_0_ff;
+extern cpuop_func op_4080_0_nf;
+extern cpuop_func op_4080_0_ff;
+extern cpuop_func op_4090_0_nf;
+extern cpuop_func op_4090_0_ff;
+extern cpuop_func op_4098_0_nf;
+extern cpuop_func op_4098_0_ff;
+extern cpuop_func op_40a0_0_nf;
+extern cpuop_func op_40a0_0_ff;
+extern cpuop_func op_40a8_0_nf;
+extern cpuop_func op_40a8_0_ff;
+extern cpuop_func op_40b0_0_nf;
+extern cpuop_func op_40b0_0_ff;
+extern cpuop_func op_40b8_0_nf;
+extern cpuop_func op_40b8_0_ff;
+extern cpuop_func op_40b9_0_nf;
+extern cpuop_func op_40b9_0_ff;
+extern cpuop_func op_40c0_0_nf;
+extern cpuop_func op_40c0_0_ff;
+extern cpuop_func op_40d0_0_nf;
+extern cpuop_func op_40d0_0_ff;
+extern cpuop_func op_40d8_0_nf;
+extern cpuop_func op_40d8_0_ff;
+extern cpuop_func op_40e0_0_nf;
+extern cpuop_func op_40e0_0_ff;
+extern cpuop_func op_40e8_0_nf;
+extern cpuop_func op_40e8_0_ff;
+extern cpuop_func op_40f0_0_nf;
+extern cpuop_func op_40f0_0_ff;
+extern cpuop_func op_40f8_0_nf;
+extern cpuop_func op_40f8_0_ff;
+extern cpuop_func op_40f9_0_nf;
+extern cpuop_func op_40f9_0_ff;
+extern cpuop_func op_4100_0_nf;
+extern cpuop_func op_4100_0_ff;
+extern cpuop_func op_4110_0_nf;
+extern cpuop_func op_4110_0_ff;
+extern cpuop_func op_4118_0_nf;
+extern cpuop_func op_4118_0_ff;
+extern cpuop_func op_4120_0_nf;
+extern cpuop_func op_4120_0_ff;
+extern cpuop_func op_4128_0_nf;
+extern cpuop_func op_4128_0_ff;
+extern cpuop_func op_4130_0_nf;
+extern cpuop_func op_4130_0_ff;
+extern cpuop_func op_4138_0_nf;
+extern cpuop_func op_4138_0_ff;
+extern cpuop_func op_4139_0_nf;
+extern cpuop_func op_4139_0_ff;
+extern cpuop_func op_413a_0_nf;
+extern cpuop_func op_413a_0_ff;
+extern cpuop_func op_413b_0_nf;
+extern cpuop_func op_413b_0_ff;
+extern cpuop_func op_413c_0_nf;
+extern cpuop_func op_413c_0_ff;
+extern cpuop_func op_4180_0_nf;
+extern cpuop_func op_4180_0_ff;
+extern cpuop_func op_4190_0_nf;
+extern cpuop_func op_4190_0_ff;
+extern cpuop_func op_4198_0_nf;
+extern cpuop_func op_4198_0_ff;
+extern cpuop_func op_41a0_0_nf;
+extern cpuop_func op_41a0_0_ff;
+extern cpuop_func op_41a8_0_nf;
+extern cpuop_func op_41a8_0_ff;
+extern cpuop_func op_41b0_0_nf;
+extern cpuop_func op_41b0_0_ff;
+extern cpuop_func op_41b8_0_nf;
+extern cpuop_func op_41b8_0_ff;
+extern cpuop_func op_41b9_0_nf;
+extern cpuop_func op_41b9_0_ff;
+extern cpuop_func op_41ba_0_nf;
+extern cpuop_func op_41ba_0_ff;
+extern cpuop_func op_41bb_0_nf;
+extern cpuop_func op_41bb_0_ff;
+extern cpuop_func op_41bc_0_nf;
+extern cpuop_func op_41bc_0_ff;
+extern cpuop_func op_41d0_0_nf;
+extern cpuop_func op_41d0_0_ff;
+extern cpuop_func op_41e8_0_nf;
+extern cpuop_func op_41e8_0_ff;
+extern cpuop_func op_41f0_0_nf;
+extern cpuop_func op_41f0_0_ff;
+extern cpuop_func op_41f8_0_nf;
+extern cpuop_func op_41f8_0_ff;
+extern cpuop_func op_41f9_0_nf;
+extern cpuop_func op_41f9_0_ff;
+extern cpuop_func op_41fa_0_nf;
+extern cpuop_func op_41fa_0_ff;
+extern cpuop_func op_41fb_0_nf;
+extern cpuop_func op_41fb_0_ff;
+extern cpuop_func op_4200_0_nf;
+extern cpuop_func op_4200_0_ff;
+extern cpuop_func op_4210_0_nf;
+extern cpuop_func op_4210_0_ff;
+extern cpuop_func op_4218_0_nf;
+extern cpuop_func op_4218_0_ff;
+extern cpuop_func op_4220_0_nf;
+extern cpuop_func op_4220_0_ff;
+extern cpuop_func op_4228_0_nf;
+extern cpuop_func op_4228_0_ff;
+extern cpuop_func op_4230_0_nf;
+extern cpuop_func op_4230_0_ff;
+extern cpuop_func op_4238_0_nf;
+extern cpuop_func op_4238_0_ff;
+extern cpuop_func op_4239_0_nf;
+extern cpuop_func op_4239_0_ff;
+extern cpuop_func op_4240_0_nf;
+extern cpuop_func op_4240_0_ff;
+extern cpuop_func op_4250_0_nf;
+extern cpuop_func op_4250_0_ff;
+extern cpuop_func op_4258_0_nf;
+extern cpuop_func op_4258_0_ff;
+extern cpuop_func op_4260_0_nf;
+extern cpuop_func op_4260_0_ff;
+extern cpuop_func op_4268_0_nf;
+extern cpuop_func op_4268_0_ff;
+extern cpuop_func op_4270_0_nf;
+extern cpuop_func op_4270_0_ff;
+extern cpuop_func op_4278_0_nf;
+extern cpuop_func op_4278_0_ff;
+extern cpuop_func op_4279_0_nf;
+extern cpuop_func op_4279_0_ff;
+extern cpuop_func op_4280_0_nf;
+extern cpuop_func op_4280_0_ff;
+extern cpuop_func op_4290_0_nf;
+extern cpuop_func op_4290_0_ff;
+extern cpuop_func op_4298_0_nf;
+extern cpuop_func op_4298_0_ff;
+extern cpuop_func op_42a0_0_nf;
+extern cpuop_func op_42a0_0_ff;
+extern cpuop_func op_42a8_0_nf;
+extern cpuop_func op_42a8_0_ff;
+extern cpuop_func op_42b0_0_nf;
+extern cpuop_func op_42b0_0_ff;
+extern cpuop_func op_42b8_0_nf;
+extern cpuop_func op_42b8_0_ff;
+extern cpuop_func op_42b9_0_nf;
+extern cpuop_func op_42b9_0_ff;
+extern cpuop_func op_42c0_0_nf;
+extern cpuop_func op_42c0_0_ff;
+extern cpuop_func op_42d0_0_nf;
+extern cpuop_func op_42d0_0_ff;
+extern cpuop_func op_42d8_0_nf;
+extern cpuop_func op_42d8_0_ff;
+extern cpuop_func op_42e0_0_nf;
+extern cpuop_func op_42e0_0_ff;
+extern cpuop_func op_42e8_0_nf;
+extern cpuop_func op_42e8_0_ff;
+extern cpuop_func op_42f0_0_nf;
+extern cpuop_func op_42f0_0_ff;
+extern cpuop_func op_42f8_0_nf;
+extern cpuop_func op_42f8_0_ff;
+extern cpuop_func op_42f9_0_nf;
+extern cpuop_func op_42f9_0_ff;
+extern cpuop_func op_4400_0_nf;
+extern cpuop_func op_4400_0_ff;
+extern cpuop_func op_4410_0_nf;
+extern cpuop_func op_4410_0_ff;
+extern cpuop_func op_4418_0_nf;
+extern cpuop_func op_4418_0_ff;
+extern cpuop_func op_4420_0_nf;
+extern cpuop_func op_4420_0_ff;
+extern cpuop_func op_4428_0_nf;
+extern cpuop_func op_4428_0_ff;
+extern cpuop_func op_4430_0_nf;
+extern cpuop_func op_4430_0_ff;
+extern cpuop_func op_4438_0_nf;
+extern cpuop_func op_4438_0_ff;
+extern cpuop_func op_4439_0_nf;
+extern cpuop_func op_4439_0_ff;
+extern cpuop_func op_4440_0_nf;
+extern cpuop_func op_4440_0_ff;
+extern cpuop_func op_4450_0_nf;
+extern cpuop_func op_4450_0_ff;
+extern cpuop_func op_4458_0_nf;
+extern cpuop_func op_4458_0_ff;
+extern cpuop_func op_4460_0_nf;
+extern cpuop_func op_4460_0_ff;
+extern cpuop_func op_4468_0_nf;
+extern cpuop_func op_4468_0_ff;
+extern cpuop_func op_4470_0_nf;
+extern cpuop_func op_4470_0_ff;
+extern cpuop_func op_4478_0_nf;
+extern cpuop_func op_4478_0_ff;
+extern cpuop_func op_4479_0_nf;
+extern cpuop_func op_4479_0_ff;
+extern cpuop_func op_4480_0_nf;
+extern cpuop_func op_4480_0_ff;
+extern cpuop_func op_4490_0_nf;
+extern cpuop_func op_4490_0_ff;
+extern cpuop_func op_4498_0_nf;
+extern cpuop_func op_4498_0_ff;
+extern cpuop_func op_44a0_0_nf;
+extern cpuop_func op_44a0_0_ff;
+extern cpuop_func op_44a8_0_nf;
+extern cpuop_func op_44a8_0_ff;
+extern cpuop_func op_44b0_0_nf;
+extern cpuop_func op_44b0_0_ff;
+extern cpuop_func op_44b8_0_nf;
+extern cpuop_func op_44b8_0_ff;
+extern cpuop_func op_44b9_0_nf;
+extern cpuop_func op_44b9_0_ff;
+extern cpuop_func op_44c0_0_nf;
+extern cpuop_func op_44c0_0_ff;
+extern cpuop_func op_44d0_0_nf;
+extern cpuop_func op_44d0_0_ff;
+extern cpuop_func op_44d8_0_nf;
+extern cpuop_func op_44d8_0_ff;
+extern cpuop_func op_44e0_0_nf;
+extern cpuop_func op_44e0_0_ff;
+extern cpuop_func op_44e8_0_nf;
+extern cpuop_func op_44e8_0_ff;
+extern cpuop_func op_44f0_0_nf;
+extern cpuop_func op_44f0_0_ff;
+extern cpuop_func op_44f8_0_nf;
+extern cpuop_func op_44f8_0_ff;
+extern cpuop_func op_44f9_0_nf;
+extern cpuop_func op_44f9_0_ff;
+extern cpuop_func op_44fa_0_nf;
+extern cpuop_func op_44fa_0_ff;
+extern cpuop_func op_44fb_0_nf;
+extern cpuop_func op_44fb_0_ff;
+extern cpuop_func op_44fc_0_nf;
+extern cpuop_func op_44fc_0_ff;
+extern cpuop_func op_4600_0_nf;
+extern cpuop_func op_4600_0_ff;
+extern cpuop_func op_4610_0_nf;
+extern cpuop_func op_4610_0_ff;
+extern cpuop_func op_4618_0_nf;
+extern cpuop_func op_4618_0_ff;
+extern cpuop_func op_4620_0_nf;
+extern cpuop_func op_4620_0_ff;
+extern cpuop_func op_4628_0_nf;
+extern cpuop_func op_4628_0_ff;
+extern cpuop_func op_4630_0_nf;
+extern cpuop_func op_4630_0_ff;
+extern cpuop_func op_4638_0_nf;
+extern cpuop_func op_4638_0_ff;
+extern cpuop_func op_4639_0_nf;
+extern cpuop_func op_4639_0_ff;
+extern cpuop_func op_4640_0_nf;
+extern cpuop_func op_4640_0_ff;
+extern cpuop_func op_4650_0_nf;
+extern cpuop_func op_4650_0_ff;
+extern cpuop_func op_4658_0_nf;
+extern cpuop_func op_4658_0_ff;
+extern cpuop_func op_4660_0_nf;
+extern cpuop_func op_4660_0_ff;
+extern cpuop_func op_4668_0_nf;
+extern cpuop_func op_4668_0_ff;
+extern cpuop_func op_4670_0_nf;
+extern cpuop_func op_4670_0_ff;
+extern cpuop_func op_4678_0_nf;
+extern cpuop_func op_4678_0_ff;
+extern cpuop_func op_4679_0_nf;
+extern cpuop_func op_4679_0_ff;
+extern cpuop_func op_4680_0_nf;
+extern cpuop_func op_4680_0_ff;
+extern cpuop_func op_4690_0_nf;
+extern cpuop_func op_4690_0_ff;
+extern cpuop_func op_4698_0_nf;
+extern cpuop_func op_4698_0_ff;
+extern cpuop_func op_46a0_0_nf;
+extern cpuop_func op_46a0_0_ff;
+extern cpuop_func op_46a8_0_nf;
+extern cpuop_func op_46a8_0_ff;
+extern cpuop_func op_46b0_0_nf;
+extern cpuop_func op_46b0_0_ff;
+extern cpuop_func op_46b8_0_nf;
+extern cpuop_func op_46b8_0_ff;
+extern cpuop_func op_46b9_0_nf;
+extern cpuop_func op_46b9_0_ff;
+extern cpuop_func op_46c0_0_nf;
+extern cpuop_func op_46c0_0_ff;
+extern cpuop_func op_46d0_0_nf;
+extern cpuop_func op_46d0_0_ff;
+extern cpuop_func op_46d8_0_nf;
+extern cpuop_func op_46d8_0_ff;
+extern cpuop_func op_46e0_0_nf;
+extern cpuop_func op_46e0_0_ff;
+extern cpuop_func op_46e8_0_nf;
+extern cpuop_func op_46e8_0_ff;
+extern cpuop_func op_46f0_0_nf;
+extern cpuop_func op_46f0_0_ff;
+extern cpuop_func op_46f8_0_nf;
+extern cpuop_func op_46f8_0_ff;
+extern cpuop_func op_46f9_0_nf;
+extern cpuop_func op_46f9_0_ff;
+extern cpuop_func op_46fa_0_nf;
+extern cpuop_func op_46fa_0_ff;
+extern cpuop_func op_46fb_0_nf;
+extern cpuop_func op_46fb_0_ff;
+extern cpuop_func op_46fc_0_nf;
+extern cpuop_func op_46fc_0_ff;
+extern cpuop_func op_4800_0_nf;
+extern cpuop_func op_4800_0_ff;
+extern cpuop_func op_4808_0_nf;
+extern cpuop_func op_4808_0_ff;
+extern cpuop_func op_4810_0_nf;
+extern cpuop_func op_4810_0_ff;
+extern cpuop_func op_4818_0_nf;
+extern cpuop_func op_4818_0_ff;
+extern cpuop_func op_4820_0_nf;
+extern cpuop_func op_4820_0_ff;
+extern cpuop_func op_4828_0_nf;
+extern cpuop_func op_4828_0_ff;
+extern cpuop_func op_4830_0_nf;
+extern cpuop_func op_4830_0_ff;
+extern cpuop_func op_4838_0_nf;
+extern cpuop_func op_4838_0_ff;
+extern cpuop_func op_4839_0_nf;
+extern cpuop_func op_4839_0_ff;
+extern cpuop_func op_4840_0_nf;
+extern cpuop_func op_4840_0_ff;
+extern cpuop_func op_4848_0_nf;
+extern cpuop_func op_4848_0_ff;
+extern cpuop_func op_4850_0_nf;
+extern cpuop_func op_4850_0_ff;
+extern cpuop_func op_4868_0_nf;
+extern cpuop_func op_4868_0_ff;
+extern cpuop_func op_4870_0_nf;
+extern cpuop_func op_4870_0_ff;
+extern cpuop_func op_4878_0_nf;
+extern cpuop_func op_4878_0_ff;
+extern cpuop_func op_4879_0_nf;
+extern cpuop_func op_4879_0_ff;
+extern cpuop_func op_487a_0_nf;
+extern cpuop_func op_487a_0_ff;
+extern cpuop_func op_487b_0_nf;
+extern cpuop_func op_487b_0_ff;
+extern cpuop_func op_4880_0_nf;
+extern cpuop_func op_4880_0_ff;
+extern cpuop_func op_4890_0_nf;
+extern cpuop_func op_4890_0_ff;
+extern cpuop_func op_48a0_0_nf;
+extern cpuop_func op_48a0_0_ff;
+extern cpuop_func op_48a8_0_nf;
+extern cpuop_func op_48a8_0_ff;
+extern cpuop_func op_48b0_0_nf;
+extern cpuop_func op_48b0_0_ff;
+extern cpuop_func op_48b8_0_nf;
+extern cpuop_func op_48b8_0_ff;
+extern cpuop_func op_48b9_0_nf;
+extern cpuop_func op_48b9_0_ff;
+extern cpuop_func op_48c0_0_nf;
+extern cpuop_func op_48c0_0_ff;
+extern cpuop_func op_48d0_0_nf;
+extern cpuop_func op_48d0_0_ff;
+extern cpuop_func op_48e0_0_nf;
+extern cpuop_func op_48e0_0_ff;
+extern cpuop_func op_48e8_0_nf;
+extern cpuop_func op_48e8_0_ff;
+extern cpuop_func op_48f0_0_nf;
+extern cpuop_func op_48f0_0_ff;
+extern cpuop_func op_48f8_0_nf;
+extern cpuop_func op_48f8_0_ff;
+extern cpuop_func op_48f9_0_nf;
+extern cpuop_func op_48f9_0_ff;
+extern cpuop_func op_49c0_0_nf;
+extern cpuop_func op_49c0_0_ff;
+extern cpuop_func op_4a00_0_nf;
+extern cpuop_func op_4a00_0_ff;
+extern cpuop_func op_4a10_0_nf;
+extern cpuop_func op_4a10_0_ff;
+extern cpuop_func op_4a18_0_nf;
+extern cpuop_func op_4a18_0_ff;
+extern cpuop_func op_4a20_0_nf;
+extern cpuop_func op_4a20_0_ff;
+extern cpuop_func op_4a28_0_nf;
+extern cpuop_func op_4a28_0_ff;
+extern cpuop_func op_4a30_0_nf;
+extern cpuop_func op_4a30_0_ff;
+extern cpuop_func op_4a38_0_nf;
+extern cpuop_func op_4a38_0_ff;
+extern cpuop_func op_4a39_0_nf;
+extern cpuop_func op_4a39_0_ff;
+extern cpuop_func op_4a3a_0_nf;
+extern cpuop_func op_4a3a_0_ff;
+extern cpuop_func op_4a3b_0_nf;
+extern cpuop_func op_4a3b_0_ff;
+extern cpuop_func op_4a3c_0_nf;
+extern cpuop_func op_4a3c_0_ff;
+extern cpuop_func op_4a40_0_nf;
+extern cpuop_func op_4a40_0_ff;
+extern cpuop_func op_4a48_0_nf;
+extern cpuop_func op_4a48_0_ff;
+extern cpuop_func op_4a50_0_nf;
+extern cpuop_func op_4a50_0_ff;
+extern cpuop_func op_4a58_0_nf;
+extern cpuop_func op_4a58_0_ff;
+extern cpuop_func op_4a60_0_nf;
+extern cpuop_func op_4a60_0_ff;
+extern cpuop_func op_4a68_0_nf;
+extern cpuop_func op_4a68_0_ff;
+extern cpuop_func op_4a70_0_nf;
+extern cpuop_func op_4a70_0_ff;
+extern cpuop_func op_4a78_0_nf;
+extern cpuop_func op_4a78_0_ff;
+extern cpuop_func op_4a79_0_nf;
+extern cpuop_func op_4a79_0_ff;
+extern cpuop_func op_4a7a_0_nf;
+extern cpuop_func op_4a7a_0_ff;
+extern cpuop_func op_4a7b_0_nf;
+extern cpuop_func op_4a7b_0_ff;
+extern cpuop_func op_4a7c_0_nf;
+extern cpuop_func op_4a7c_0_ff;
+extern cpuop_func op_4a80_0_nf;
+extern cpuop_func op_4a80_0_ff;
+extern cpuop_func op_4a88_0_nf;
+extern cpuop_func op_4a88_0_ff;
+extern cpuop_func op_4a90_0_nf;
+extern cpuop_func op_4a90_0_ff;
+extern cpuop_func op_4a98_0_nf;
+extern cpuop_func op_4a98_0_ff;
+extern cpuop_func op_4aa0_0_nf;
+extern cpuop_func op_4aa0_0_ff;
+extern cpuop_func op_4aa8_0_nf;
+extern cpuop_func op_4aa8_0_ff;
+extern cpuop_func op_4ab0_0_nf;
+extern cpuop_func op_4ab0_0_ff;
+extern cpuop_func op_4ab8_0_nf;
+extern cpuop_func op_4ab8_0_ff;
+extern cpuop_func op_4ab9_0_nf;
+extern cpuop_func op_4ab9_0_ff;
+extern cpuop_func op_4aba_0_nf;
+extern cpuop_func op_4aba_0_ff;
+extern cpuop_func op_4abb_0_nf;
+extern cpuop_func op_4abb_0_ff;
+extern cpuop_func op_4abc_0_nf;
+extern cpuop_func op_4abc_0_ff;
+extern cpuop_func op_4ac0_0_nf;
+extern cpuop_func op_4ac0_0_ff;
+extern cpuop_func op_4ad0_0_nf;
+extern cpuop_func op_4ad0_0_ff;
+extern cpuop_func op_4ad8_0_nf;
+extern cpuop_func op_4ad8_0_ff;
+extern cpuop_func op_4ae0_0_nf;
+extern cpuop_func op_4ae0_0_ff;
+extern cpuop_func op_4ae8_0_nf;
+extern cpuop_func op_4ae8_0_ff;
+extern cpuop_func op_4af0_0_nf;
+extern cpuop_func op_4af0_0_ff;
+extern cpuop_func op_4af8_0_nf;
+extern cpuop_func op_4af8_0_ff;
+extern cpuop_func op_4af9_0_nf;
+extern cpuop_func op_4af9_0_ff;
+extern cpuop_func op_4c00_0_nf;
+extern cpuop_func op_4c00_0_ff;
+extern cpuop_func op_4c10_0_nf;
+extern cpuop_func op_4c10_0_ff;
+extern cpuop_func op_4c18_0_nf;
+extern cpuop_func op_4c18_0_ff;
+extern cpuop_func op_4c20_0_nf;
+extern cpuop_func op_4c20_0_ff;
+extern cpuop_func op_4c28_0_nf;
+extern cpuop_func op_4c28_0_ff;
+extern cpuop_func op_4c30_0_nf;
+extern cpuop_func op_4c30_0_ff;
+extern cpuop_func op_4c38_0_nf;
+extern cpuop_func op_4c38_0_ff;
+extern cpuop_func op_4c39_0_nf;
+extern cpuop_func op_4c39_0_ff;
+extern cpuop_func op_4c3a_0_nf;
+extern cpuop_func op_4c3a_0_ff;
+extern cpuop_func op_4c3b_0_nf;
+extern cpuop_func op_4c3b_0_ff;
+extern cpuop_func op_4c3c_0_nf;
+extern cpuop_func op_4c3c_0_ff;
+extern cpuop_func op_4c40_0_nf;
+extern cpuop_func op_4c40_0_ff;
+extern cpuop_func op_4c50_0_nf;
+extern cpuop_func op_4c50_0_ff;
+extern cpuop_func op_4c58_0_nf;
+extern cpuop_func op_4c58_0_ff;
+extern cpuop_func op_4c60_0_nf;
+extern cpuop_func op_4c60_0_ff;
+extern cpuop_func op_4c68_0_nf;
+extern cpuop_func op_4c68_0_ff;
+extern cpuop_func op_4c70_0_nf;
+extern cpuop_func op_4c70_0_ff;
+extern cpuop_func op_4c78_0_nf;
+extern cpuop_func op_4c78_0_ff;
+extern cpuop_func op_4c79_0_nf;
+extern cpuop_func op_4c79_0_ff;
+extern cpuop_func op_4c7a_0_nf;
+extern cpuop_func op_4c7a_0_ff;
+extern cpuop_func op_4c7b_0_nf;
+extern cpuop_func op_4c7b_0_ff;
+extern cpuop_func op_4c7c_0_nf;
+extern cpuop_func op_4c7c_0_ff;
+extern cpuop_func op_4c90_0_nf;
+extern cpuop_func op_4c90_0_ff;
+extern cpuop_func op_4c98_0_nf;
+extern cpuop_func op_4c98_0_ff;
+extern cpuop_func op_4ca8_0_nf;
+extern cpuop_func op_4ca8_0_ff;
+extern cpuop_func op_4cb0_0_nf;
+extern cpuop_func op_4cb0_0_ff;
+extern cpuop_func op_4cb8_0_nf;
+extern cpuop_func op_4cb8_0_ff;
+extern cpuop_func op_4cb9_0_nf;
+extern cpuop_func op_4cb9_0_ff;
+extern cpuop_func op_4cba_0_nf;
+extern cpuop_func op_4cba_0_ff;
+extern cpuop_func op_4cbb_0_nf;
+extern cpuop_func op_4cbb_0_ff;
+extern cpuop_func op_4cd0_0_nf;
+extern cpuop_func op_4cd0_0_ff;
+extern cpuop_func op_4cd8_0_nf;
+extern cpuop_func op_4cd8_0_ff;
+extern cpuop_func op_4ce8_0_nf;
+extern cpuop_func op_4ce8_0_ff;
+extern cpuop_func op_4cf0_0_nf;
+extern cpuop_func op_4cf0_0_ff;
+extern cpuop_func op_4cf8_0_nf;
+extern cpuop_func op_4cf8_0_ff;
+extern cpuop_func op_4cf9_0_nf;
+extern cpuop_func op_4cf9_0_ff;
+extern cpuop_func op_4cfa_0_nf;
+extern cpuop_func op_4cfa_0_ff;
+extern cpuop_func op_4cfb_0_nf;
+extern cpuop_func op_4cfb_0_ff;
+extern cpuop_func op_4e40_0_nf;
+extern cpuop_func op_4e40_0_ff;
+extern cpuop_func op_4e50_0_nf;
+extern cpuop_func op_4e50_0_ff;
+extern cpuop_func op_4e58_0_nf;
+extern cpuop_func op_4e58_0_ff;
+extern cpuop_func op_4e60_0_nf;
+extern cpuop_func op_4e60_0_ff;
+extern cpuop_func op_4e68_0_nf;
+extern cpuop_func op_4e68_0_ff;
+extern cpuop_func op_4e70_0_nf;
+extern cpuop_func op_4e70_0_ff;
+extern cpuop_func op_4e71_0_nf;
+extern cpuop_func op_4e71_0_ff;
+extern cpuop_func op_4e72_0_nf;
+extern cpuop_func op_4e72_0_ff;
+extern cpuop_func op_4e73_0_nf;
+extern cpuop_func op_4e73_0_ff;
+extern cpuop_func op_4e74_0_nf;
+extern cpuop_func op_4e74_0_ff;
+extern cpuop_func op_4e75_0_nf;
+extern cpuop_func op_4e75_0_ff;
+extern cpuop_func op_4e76_0_nf;
+extern cpuop_func op_4e76_0_ff;
+extern cpuop_func op_4e77_0_nf;
+extern cpuop_func op_4e77_0_ff;
+extern cpuop_func op_4e7a_0_nf;
+extern cpuop_func op_4e7a_0_ff;
+extern cpuop_func op_4e7b_0_nf;
+extern cpuop_func op_4e7b_0_ff;
+extern cpuop_func op_4e90_0_nf;
+extern cpuop_func op_4e90_0_ff;
+extern cpuop_func op_4ea8_0_nf;
+extern cpuop_func op_4ea8_0_ff;
+extern cpuop_func op_4eb0_0_nf;
+extern cpuop_func op_4eb0_0_ff;
+extern cpuop_func op_4eb8_0_nf;
+extern cpuop_func op_4eb8_0_ff;
+extern cpuop_func op_4eb9_0_nf;
+extern cpuop_func op_4eb9_0_ff;
+extern cpuop_func op_4eba_0_nf;
+extern cpuop_func op_4eba_0_ff;
+extern cpuop_func op_4ebb_0_nf;
+extern cpuop_func op_4ebb_0_ff;
+extern cpuop_func op_4ed0_0_nf;
+extern cpuop_func op_4ed0_0_ff;
+extern cpuop_func op_4ee8_0_nf;
+extern cpuop_func op_4ee8_0_ff;
+extern cpuop_func op_4ef0_0_nf;
+extern cpuop_func op_4ef0_0_ff;
+extern cpuop_func op_4ef8_0_nf;
+extern cpuop_func op_4ef8_0_ff;
+extern cpuop_func op_4ef9_0_nf;
+extern cpuop_func op_4ef9_0_ff;
+extern cpuop_func op_4efa_0_nf;
+extern cpuop_func op_4efa_0_ff;
+extern cpuop_func op_4efb_0_nf;
+extern cpuop_func op_4efb_0_ff;
+extern cpuop_func op_5000_0_nf;
+extern cpuop_func op_5000_0_ff;
+extern cpuop_func op_5010_0_nf;
+extern cpuop_func op_5010_0_ff;
+extern cpuop_func op_5018_0_nf;
+extern cpuop_func op_5018_0_ff;
+extern cpuop_func op_5020_0_nf;
+extern cpuop_func op_5020_0_ff;
+extern cpuop_func op_5028_0_nf;
+extern cpuop_func op_5028_0_ff;
+extern cpuop_func op_5030_0_nf;
+extern cpuop_func op_5030_0_ff;
+extern cpuop_func op_5038_0_nf;
+extern cpuop_func op_5038_0_ff;
+extern cpuop_func op_5039_0_nf;
+extern cpuop_func op_5039_0_ff;
+extern cpuop_func op_5040_0_nf;
+extern cpuop_func op_5040_0_ff;
+extern cpuop_func op_5048_0_nf;
+extern cpuop_func op_5048_0_ff;
+extern cpuop_func op_5050_0_nf;
+extern cpuop_func op_5050_0_ff;
+extern cpuop_func op_5058_0_nf;
+extern cpuop_func op_5058_0_ff;
+extern cpuop_func op_5060_0_nf;
+extern cpuop_func op_5060_0_ff;
+extern cpuop_func op_5068_0_nf;
+extern cpuop_func op_5068_0_ff;
+extern cpuop_func op_5070_0_nf;
+extern cpuop_func op_5070_0_ff;
+extern cpuop_func op_5078_0_nf;
+extern cpuop_func op_5078_0_ff;
+extern cpuop_func op_5079_0_nf;
+extern cpuop_func op_5079_0_ff;
+extern cpuop_func op_5080_0_nf;
+extern cpuop_func op_5080_0_ff;
+extern cpuop_func op_5088_0_nf;
+extern cpuop_func op_5088_0_ff;
+extern cpuop_func op_5090_0_nf;
+extern cpuop_func op_5090_0_ff;
+extern cpuop_func op_5098_0_nf;
+extern cpuop_func op_5098_0_ff;
+extern cpuop_func op_50a0_0_nf;
+extern cpuop_func op_50a0_0_ff;
+extern cpuop_func op_50a8_0_nf;
+extern cpuop_func op_50a8_0_ff;
+extern cpuop_func op_50b0_0_nf;
+extern cpuop_func op_50b0_0_ff;
+extern cpuop_func op_50b8_0_nf;
+extern cpuop_func op_50b8_0_ff;
+extern cpuop_func op_50b9_0_nf;
+extern cpuop_func op_50b9_0_ff;
+extern cpuop_func op_50c0_0_nf;
+extern cpuop_func op_50c0_0_ff;
+extern cpuop_func op_50c8_0_nf;
+extern cpuop_func op_50c8_0_ff;
+extern cpuop_func op_50d0_0_nf;
+extern cpuop_func op_50d0_0_ff;
+extern cpuop_func op_50d8_0_nf;
+extern cpuop_func op_50d8_0_ff;
+extern cpuop_func op_50e0_0_nf;
+extern cpuop_func op_50e0_0_ff;
+extern cpuop_func op_50e8_0_nf;
+extern cpuop_func op_50e8_0_ff;
+extern cpuop_func op_50f0_0_nf;
+extern cpuop_func op_50f0_0_ff;
+extern cpuop_func op_50f8_0_nf;
+extern cpuop_func op_50f8_0_ff;
+extern cpuop_func op_50f9_0_nf;
+extern cpuop_func op_50f9_0_ff;
+extern cpuop_func op_50fa_0_nf;
+extern cpuop_func op_50fa_0_ff;
+extern cpuop_func op_50fb_0_nf;
+extern cpuop_func op_50fb_0_ff;
+extern cpuop_func op_50fc_0_nf;
+extern cpuop_func op_50fc_0_ff;
+extern cpuop_func op_5100_0_nf;
+extern cpuop_func op_5100_0_ff;
+extern cpuop_func op_5110_0_nf;
+extern cpuop_func op_5110_0_ff;
+extern cpuop_func op_5118_0_nf;
+extern cpuop_func op_5118_0_ff;
+extern cpuop_func op_5120_0_nf;
+extern cpuop_func op_5120_0_ff;
+extern cpuop_func op_5128_0_nf;
+extern cpuop_func op_5128_0_ff;
+extern cpuop_func op_5130_0_nf;
+extern cpuop_func op_5130_0_ff;
+extern cpuop_func op_5138_0_nf;
+extern cpuop_func op_5138_0_ff;
+extern cpuop_func op_5139_0_nf;
+extern cpuop_func op_5139_0_ff;
+extern cpuop_func op_5140_0_nf;
+extern cpuop_func op_5140_0_ff;
+extern cpuop_func op_5148_0_nf;
+extern cpuop_func op_5148_0_ff;
+extern cpuop_func op_5150_0_nf;
+extern cpuop_func op_5150_0_ff;
+extern cpuop_func op_5158_0_nf;
+extern cpuop_func op_5158_0_ff;
+extern cpuop_func op_5160_0_nf;
+extern cpuop_func op_5160_0_ff;
+extern cpuop_func op_5168_0_nf;
+extern cpuop_func op_5168_0_ff;
+extern cpuop_func op_5170_0_nf;
+extern cpuop_func op_5170_0_ff;
+extern cpuop_func op_5178_0_nf;
+extern cpuop_func op_5178_0_ff;
+extern cpuop_func op_5179_0_nf;
+extern cpuop_func op_5179_0_ff;
+extern cpuop_func op_5180_0_nf;
+extern cpuop_func op_5180_0_ff;
+extern cpuop_func op_5188_0_nf;
+extern cpuop_func op_5188_0_ff;
+extern cpuop_func op_5190_0_nf;
+extern cpuop_func op_5190_0_ff;
+extern cpuop_func op_5198_0_nf;
+extern cpuop_func op_5198_0_ff;
+extern cpuop_func op_51a0_0_nf;
+extern cpuop_func op_51a0_0_ff;
+extern cpuop_func op_51a8_0_nf;
+extern cpuop_func op_51a8_0_ff;
+extern cpuop_func op_51b0_0_nf;
+extern cpuop_func op_51b0_0_ff;
+extern cpuop_func op_51b8_0_nf;
+extern cpuop_func op_51b8_0_ff;
+extern cpuop_func op_51b9_0_nf;
+extern cpuop_func op_51b9_0_ff;
+extern cpuop_func op_51c0_0_nf;
+extern cpuop_func op_51c0_0_ff;
+extern cpuop_func op_51c8_0_nf;
+extern cpuop_func op_51c8_0_ff;
+extern cpuop_func op_51d0_0_nf;
+extern cpuop_func op_51d0_0_ff;
+extern cpuop_func op_51d8_0_nf;
+extern cpuop_func op_51d8_0_ff;
+extern cpuop_func op_51e0_0_nf;
+extern cpuop_func op_51e0_0_ff;
+extern cpuop_func op_51e8_0_nf;
+extern cpuop_func op_51e8_0_ff;
+extern cpuop_func op_51f0_0_nf;
+extern cpuop_func op_51f0_0_ff;
+extern cpuop_func op_51f8_0_nf;
+extern cpuop_func op_51f8_0_ff;
+extern cpuop_func op_51f9_0_nf;
+extern cpuop_func op_51f9_0_ff;
+extern cpuop_func op_51fa_0_nf;
+extern cpuop_func op_51fa_0_ff;
+extern cpuop_func op_51fb_0_nf;
+extern cpuop_func op_51fb_0_ff;
+extern cpuop_func op_51fc_0_nf;
+extern cpuop_func op_51fc_0_ff;
+extern cpuop_func op_52c0_0_nf;
+extern cpuop_func op_52c0_0_ff;
+extern cpuop_func op_52c8_0_nf;
+extern cpuop_func op_52c8_0_ff;
+extern cpuop_func op_52d0_0_nf;
+extern cpuop_func op_52d0_0_ff;
+extern cpuop_func op_52d8_0_nf;
+extern cpuop_func op_52d8_0_ff;
+extern cpuop_func op_52e0_0_nf;
+extern cpuop_func op_52e0_0_ff;
+extern cpuop_func op_52e8_0_nf;
+extern cpuop_func op_52e8_0_ff;
+extern cpuop_func op_52f0_0_nf;
+extern cpuop_func op_52f0_0_ff;
+extern cpuop_func op_52f8_0_nf;
+extern cpuop_func op_52f8_0_ff;
+extern cpuop_func op_52f9_0_nf;
+extern cpuop_func op_52f9_0_ff;
+extern cpuop_func op_52fa_0_nf;
+extern cpuop_func op_52fa_0_ff;
+extern cpuop_func op_52fb_0_nf;
+extern cpuop_func op_52fb_0_ff;
+extern cpuop_func op_52fc_0_nf;
+extern cpuop_func op_52fc_0_ff;
+extern cpuop_func op_53c0_0_nf;
+extern cpuop_func op_53c0_0_ff;
+extern cpuop_func op_53c8_0_nf;
+extern cpuop_func op_53c8_0_ff;
+extern cpuop_func op_53d0_0_nf;
+extern cpuop_func op_53d0_0_ff;
+extern cpuop_func op_53d8_0_nf;
+extern cpuop_func op_53d8_0_ff;
+extern cpuop_func op_53e0_0_nf;
+extern cpuop_func op_53e0_0_ff;
+extern cpuop_func op_53e8_0_nf;
+extern cpuop_func op_53e8_0_ff;
+extern cpuop_func op_53f0_0_nf;
+extern cpuop_func op_53f0_0_ff;
+extern cpuop_func op_53f8_0_nf;
+extern cpuop_func op_53f8_0_ff;
+extern cpuop_func op_53f9_0_nf;
+extern cpuop_func op_53f9_0_ff;
+extern cpuop_func op_53fa_0_nf;
+extern cpuop_func op_53fa_0_ff;
+extern cpuop_func op_53fb_0_nf;
+extern cpuop_func op_53fb_0_ff;
+extern cpuop_func op_53fc_0_nf;
+extern cpuop_func op_53fc_0_ff;
+extern cpuop_func op_54c0_0_nf;
+extern cpuop_func op_54c0_0_ff;
+extern cpuop_func op_54c8_0_nf;
+extern cpuop_func op_54c8_0_ff;
+extern cpuop_func op_54d0_0_nf;
+extern cpuop_func op_54d0_0_ff;
+extern cpuop_func op_54d8_0_nf;
+extern cpuop_func op_54d8_0_ff;
+extern cpuop_func op_54e0_0_nf;
+extern cpuop_func op_54e0_0_ff;
+extern cpuop_func op_54e8_0_nf;
+extern cpuop_func op_54e8_0_ff;
+extern cpuop_func op_54f0_0_nf;
+extern cpuop_func op_54f0_0_ff;
+extern cpuop_func op_54f8_0_nf;
+extern cpuop_func op_54f8_0_ff;
+extern cpuop_func op_54f9_0_nf;
+extern cpuop_func op_54f9_0_ff;
+extern cpuop_func op_54fa_0_nf;
+extern cpuop_func op_54fa_0_ff;
+extern cpuop_func op_54fb_0_nf;
+extern cpuop_func op_54fb_0_ff;
+extern cpuop_func op_54fc_0_nf;
+extern cpuop_func op_54fc_0_ff;
+extern cpuop_func op_55c0_0_nf;
+extern cpuop_func op_55c0_0_ff;
+extern cpuop_func op_55c8_0_nf;
+extern cpuop_func op_55c8_0_ff;
+extern cpuop_func op_55d0_0_nf;
+extern cpuop_func op_55d0_0_ff;
+extern cpuop_func op_55d8_0_nf;
+extern cpuop_func op_55d8_0_ff;
+extern cpuop_func op_55e0_0_nf;
+extern cpuop_func op_55e0_0_ff;
+extern cpuop_func op_55e8_0_nf;
+extern cpuop_func op_55e8_0_ff;
+extern cpuop_func op_55f0_0_nf;
+extern cpuop_func op_55f0_0_ff;
+extern cpuop_func op_55f8_0_nf;
+extern cpuop_func op_55f8_0_ff;
+extern cpuop_func op_55f9_0_nf;
+extern cpuop_func op_55f9_0_ff;
+extern cpuop_func op_55fa_0_nf;
+extern cpuop_func op_55fa_0_ff;
+extern cpuop_func op_55fb_0_nf;
+extern cpuop_func op_55fb_0_ff;
+extern cpuop_func op_55fc_0_nf;
+extern cpuop_func op_55fc_0_ff;
+extern cpuop_func op_56c0_0_nf;
+extern cpuop_func op_56c0_0_ff;
+extern cpuop_func op_56c8_0_nf;
+extern cpuop_func op_56c8_0_ff;
+extern cpuop_func op_56d0_0_nf;
+extern cpuop_func op_56d0_0_ff;
+extern cpuop_func op_56d8_0_nf;
+extern cpuop_func op_56d8_0_ff;
+extern cpuop_func op_56e0_0_nf;
+extern cpuop_func op_56e0_0_ff;
+extern cpuop_func op_56e8_0_nf;
+extern cpuop_func op_56e8_0_ff;
+extern cpuop_func op_56f0_0_nf;
+extern cpuop_func op_56f0_0_ff;
+extern cpuop_func op_56f8_0_nf;
+extern cpuop_func op_56f8_0_ff;
+extern cpuop_func op_56f9_0_nf;
+extern cpuop_func op_56f9_0_ff;
+extern cpuop_func op_56fa_0_nf;
+extern cpuop_func op_56fa_0_ff;
+extern cpuop_func op_56fb_0_nf;
+extern cpuop_func op_56fb_0_ff;
+extern cpuop_func op_56fc_0_nf;
+extern cpuop_func op_56fc_0_ff;
+extern cpuop_func op_57c0_0_nf;
+extern cpuop_func op_57c0_0_ff;
+extern cpuop_func op_57c8_0_nf;
+extern cpuop_func op_57c8_0_ff;
+extern cpuop_func op_57d0_0_nf;
+extern cpuop_func op_57d0_0_ff;
+extern cpuop_func op_57d8_0_nf;
+extern cpuop_func op_57d8_0_ff;
+extern cpuop_func op_57e0_0_nf;
+extern cpuop_func op_57e0_0_ff;
+extern cpuop_func op_57e8_0_nf;
+extern cpuop_func op_57e8_0_ff;
+extern cpuop_func op_57f0_0_nf;
+extern cpuop_func op_57f0_0_ff;
+extern cpuop_func op_57f8_0_nf;
+extern cpuop_func op_57f8_0_ff;
+extern cpuop_func op_57f9_0_nf;
+extern cpuop_func op_57f9_0_ff;
+extern cpuop_func op_57fa_0_nf;
+extern cpuop_func op_57fa_0_ff;
+extern cpuop_func op_57fb_0_nf;
+extern cpuop_func op_57fb_0_ff;
+extern cpuop_func op_57fc_0_nf;
+extern cpuop_func op_57fc_0_ff;
+extern cpuop_func op_58c0_0_nf;
+extern cpuop_func op_58c0_0_ff;
+extern cpuop_func op_58c8_0_nf;
+extern cpuop_func op_58c8_0_ff;
+extern cpuop_func op_58d0_0_nf;
+extern cpuop_func op_58d0_0_ff;
+extern cpuop_func op_58d8_0_nf;
+extern cpuop_func op_58d8_0_ff;
+extern cpuop_func op_58e0_0_nf;
+extern cpuop_func op_58e0_0_ff;
+extern cpuop_func op_58e8_0_nf;
+extern cpuop_func op_58e8_0_ff;
+extern cpuop_func op_58f0_0_nf;
+extern cpuop_func op_58f0_0_ff;
+extern cpuop_func op_58f8_0_nf;
+extern cpuop_func op_58f8_0_ff;
+extern cpuop_func op_58f9_0_nf;
+extern cpuop_func op_58f9_0_ff;
+extern cpuop_func op_58fa_0_nf;
+extern cpuop_func op_58fa_0_ff;
+extern cpuop_func op_58fb_0_nf;
+extern cpuop_func op_58fb_0_ff;
+extern cpuop_func op_58fc_0_nf;
+extern cpuop_func op_58fc_0_ff;
+extern cpuop_func op_59c0_0_nf;
+extern cpuop_func op_59c0_0_ff;
+extern cpuop_func op_59c8_0_nf;
+extern cpuop_func op_59c8_0_ff;
+extern cpuop_func op_59d0_0_nf;
+extern cpuop_func op_59d0_0_ff;
+extern cpuop_func op_59d8_0_nf;
+extern cpuop_func op_59d8_0_ff;
+extern cpuop_func op_59e0_0_nf;
+extern cpuop_func op_59e0_0_ff;
+extern cpuop_func op_59e8_0_nf;
+extern cpuop_func op_59e8_0_ff;
+extern cpuop_func op_59f0_0_nf;
+extern cpuop_func op_59f0_0_ff;
+extern cpuop_func op_59f8_0_nf;
+extern cpuop_func op_59f8_0_ff;
+extern cpuop_func op_59f9_0_nf;
+extern cpuop_func op_59f9_0_ff;
+extern cpuop_func op_59fa_0_nf;
+extern cpuop_func op_59fa_0_ff;
+extern cpuop_func op_59fb_0_nf;
+extern cpuop_func op_59fb_0_ff;
+extern cpuop_func op_59fc_0_nf;
+extern cpuop_func op_59fc_0_ff;
+extern cpuop_func op_5ac0_0_nf;
+extern cpuop_func op_5ac0_0_ff;
+extern cpuop_func op_5ac8_0_nf;
+extern cpuop_func op_5ac8_0_ff;
+extern cpuop_func op_5ad0_0_nf;
+extern cpuop_func op_5ad0_0_ff;
+extern cpuop_func op_5ad8_0_nf;
+extern cpuop_func op_5ad8_0_ff;
+extern cpuop_func op_5ae0_0_nf;
+extern cpuop_func op_5ae0_0_ff;
+extern cpuop_func op_5ae8_0_nf;
+extern cpuop_func op_5ae8_0_ff;
+extern cpuop_func op_5af0_0_nf;
+extern cpuop_func op_5af0_0_ff;
+extern cpuop_func op_5af8_0_nf;
+extern cpuop_func op_5af8_0_ff;
+extern cpuop_func op_5af9_0_nf;
+extern cpuop_func op_5af9_0_ff;
+extern cpuop_func op_5afa_0_nf;
+extern cpuop_func op_5afa_0_ff;
+extern cpuop_func op_5afb_0_nf;
+extern cpuop_func op_5afb_0_ff;
+extern cpuop_func op_5afc_0_nf;
+extern cpuop_func op_5afc_0_ff;
+extern cpuop_func op_5bc0_0_nf;
+extern cpuop_func op_5bc0_0_ff;
+extern cpuop_func op_5bc8_0_nf;
+extern cpuop_func op_5bc8_0_ff;
+extern cpuop_func op_5bd0_0_nf;
+extern cpuop_func op_5bd0_0_ff;
+extern cpuop_func op_5bd8_0_nf;
+extern cpuop_func op_5bd8_0_ff;
+extern cpuop_func op_5be0_0_nf;
+extern cpuop_func op_5be0_0_ff;
+extern cpuop_func op_5be8_0_nf;
+extern cpuop_func op_5be8_0_ff;
+extern cpuop_func op_5bf0_0_nf;
+extern cpuop_func op_5bf0_0_ff;
+extern cpuop_func op_5bf8_0_nf;
+extern cpuop_func op_5bf8_0_ff;
+extern cpuop_func op_5bf9_0_nf;
+extern cpuop_func op_5bf9_0_ff;
+extern cpuop_func op_5bfa_0_nf;
+extern cpuop_func op_5bfa_0_ff;
+extern cpuop_func op_5bfb_0_nf;
+extern cpuop_func op_5bfb_0_ff;
+extern cpuop_func op_5bfc_0_nf;
+extern cpuop_func op_5bfc_0_ff;
+extern cpuop_func op_5cc0_0_nf;
+extern cpuop_func op_5cc0_0_ff;
+extern cpuop_func op_5cc8_0_nf;
+extern cpuop_func op_5cc8_0_ff;
+extern cpuop_func op_5cd0_0_nf;
+extern cpuop_func op_5cd0_0_ff;
+extern cpuop_func op_5cd8_0_nf;
+extern cpuop_func op_5cd8_0_ff;
+extern cpuop_func op_5ce0_0_nf;
+extern cpuop_func op_5ce0_0_ff;
+extern cpuop_func op_5ce8_0_nf;
+extern cpuop_func op_5ce8_0_ff;
+extern cpuop_func op_5cf0_0_nf;
+extern cpuop_func op_5cf0_0_ff;
+extern cpuop_func op_5cf8_0_nf;
+extern cpuop_func op_5cf8_0_ff;
+extern cpuop_func op_5cf9_0_nf;
+extern cpuop_func op_5cf9_0_ff;
+extern cpuop_func op_5cfa_0_nf;
+extern cpuop_func op_5cfa_0_ff;
+extern cpuop_func op_5cfb_0_nf;
+extern cpuop_func op_5cfb_0_ff;
+extern cpuop_func op_5cfc_0_nf;
+extern cpuop_func op_5cfc_0_ff;
+extern cpuop_func op_5dc0_0_nf;
+extern cpuop_func op_5dc0_0_ff;
+extern cpuop_func op_5dc8_0_nf;
+extern cpuop_func op_5dc8_0_ff;
+extern cpuop_func op_5dd0_0_nf;
+extern cpuop_func op_5dd0_0_ff;
+extern cpuop_func op_5dd8_0_nf;
+extern cpuop_func op_5dd8_0_ff;
+extern cpuop_func op_5de0_0_nf;
+extern cpuop_func op_5de0_0_ff;
+extern cpuop_func op_5de8_0_nf;
+extern cpuop_func op_5de8_0_ff;
+extern cpuop_func op_5df0_0_nf;
+extern cpuop_func op_5df0_0_ff;
+extern cpuop_func op_5df8_0_nf;
+extern cpuop_func op_5df8_0_ff;
+extern cpuop_func op_5df9_0_nf;
+extern cpuop_func op_5df9_0_ff;
+extern cpuop_func op_5dfa_0_nf;
+extern cpuop_func op_5dfa_0_ff;
+extern cpuop_func op_5dfb_0_nf;
+extern cpuop_func op_5dfb_0_ff;
+extern cpuop_func op_5dfc_0_nf;
+extern cpuop_func op_5dfc_0_ff;
+extern cpuop_func op_5ec0_0_nf;
+extern cpuop_func op_5ec0_0_ff;
+extern cpuop_func op_5ec8_0_nf;
+extern cpuop_func op_5ec8_0_ff;
+extern cpuop_func op_5ed0_0_nf;
+extern cpuop_func op_5ed0_0_ff;
+extern cpuop_func op_5ed8_0_nf;
+extern cpuop_func op_5ed8_0_ff;
+extern cpuop_func op_5ee0_0_nf;
+extern cpuop_func op_5ee0_0_ff;
+extern cpuop_func op_5ee8_0_nf;
+extern cpuop_func op_5ee8_0_ff;
+extern cpuop_func op_5ef0_0_nf;
+extern cpuop_func op_5ef0_0_ff;
+extern cpuop_func op_5ef8_0_nf;
+extern cpuop_func op_5ef8_0_ff;
+extern cpuop_func op_5ef9_0_nf;
+extern cpuop_func op_5ef9_0_ff;
+extern cpuop_func op_5efa_0_nf;
+extern cpuop_func op_5efa_0_ff;
+extern cpuop_func op_5efb_0_nf;
+extern cpuop_func op_5efb_0_ff;
+extern cpuop_func op_5efc_0_nf;
+extern cpuop_func op_5efc_0_ff;
+extern cpuop_func op_5fc0_0_nf;
+extern cpuop_func op_5fc0_0_ff;
+extern cpuop_func op_5fc8_0_nf;
+extern cpuop_func op_5fc8_0_ff;
+extern cpuop_func op_5fd0_0_nf;
+extern cpuop_func op_5fd0_0_ff;
+extern cpuop_func op_5fd8_0_nf;
+extern cpuop_func op_5fd8_0_ff;
+extern cpuop_func op_5fe0_0_nf;
+extern cpuop_func op_5fe0_0_ff;
+extern cpuop_func op_5fe8_0_nf;
+extern cpuop_func op_5fe8_0_ff;
+extern cpuop_func op_5ff0_0_nf;
+extern cpuop_func op_5ff0_0_ff;
+extern cpuop_func op_5ff8_0_nf;
+extern cpuop_func op_5ff8_0_ff;
+extern cpuop_func op_5ff9_0_nf;
+extern cpuop_func op_5ff9_0_ff;
+extern cpuop_func op_5ffa_0_nf;
+extern cpuop_func op_5ffa_0_ff;
+extern cpuop_func op_5ffb_0_nf;
+extern cpuop_func op_5ffb_0_ff;
+extern cpuop_func op_5ffc_0_nf;
+extern cpuop_func op_5ffc_0_ff;
+extern cpuop_func op_6000_0_nf;
+extern cpuop_func op_6000_0_ff;
+extern cpuop_func op_6001_0_nf;
+extern cpuop_func op_6001_0_ff;
+extern cpuop_func op_60ff_0_nf;
+extern cpuop_func op_60ff_0_ff;
+extern cpuop_func op_6100_0_nf;
+extern cpuop_func op_6100_0_ff;
+extern cpuop_func op_6101_0_nf;
+extern cpuop_func op_6101_0_ff;
+extern cpuop_func op_61ff_0_nf;
+extern cpuop_func op_61ff_0_ff;
+extern cpuop_func op_6200_0_nf;
+extern cpuop_func op_6200_0_ff;
+extern cpuop_func op_6201_0_nf;
+extern cpuop_func op_6201_0_ff;
+extern cpuop_func op_62ff_0_nf;
+extern cpuop_func op_62ff_0_ff;
+extern cpuop_func op_6300_0_nf;
+extern cpuop_func op_6300_0_ff;
+extern cpuop_func op_6301_0_nf;
+extern cpuop_func op_6301_0_ff;
+extern cpuop_func op_63ff_0_nf;
+extern cpuop_func op_63ff_0_ff;
+extern cpuop_func op_6400_0_nf;
+extern cpuop_func op_6400_0_ff;
+extern cpuop_func op_6401_0_nf;
+extern cpuop_func op_6401_0_ff;
+extern cpuop_func op_64ff_0_nf;
+extern cpuop_func op_64ff_0_ff;
+extern cpuop_func op_6500_0_nf;
+extern cpuop_func op_6500_0_ff;
+extern cpuop_func op_6501_0_nf;
+extern cpuop_func op_6501_0_ff;
+extern cpuop_func op_65ff_0_nf;
+extern cpuop_func op_65ff_0_ff;
+extern cpuop_func op_6600_0_nf;
+extern cpuop_func op_6600_0_ff;
+extern cpuop_func op_6601_0_nf;
+extern cpuop_func op_6601_0_ff;
+extern cpuop_func op_66ff_0_nf;
+extern cpuop_func op_66ff_0_ff;
+extern cpuop_func op_6700_0_nf;
+extern cpuop_func op_6700_0_ff;
+extern cpuop_func op_6701_0_nf;
+extern cpuop_func op_6701_0_ff;
+extern cpuop_func op_67ff_0_nf;
+extern cpuop_func op_67ff_0_ff;
+extern cpuop_func op_6800_0_nf;
+extern cpuop_func op_6800_0_ff;
+extern cpuop_func op_6801_0_nf;
+extern cpuop_func op_6801_0_ff;
+extern cpuop_func op_68ff_0_nf;
+extern cpuop_func op_68ff_0_ff;
+extern cpuop_func op_6900_0_nf;
+extern cpuop_func op_6900_0_ff;
+extern cpuop_func op_6901_0_nf;
+extern cpuop_func op_6901_0_ff;
+extern cpuop_func op_69ff_0_nf;
+extern cpuop_func op_69ff_0_ff;
+extern cpuop_func op_6a00_0_nf;
+extern cpuop_func op_6a00_0_ff;
+extern cpuop_func op_6a01_0_nf;
+extern cpuop_func op_6a01_0_ff;
+extern cpuop_func op_6aff_0_nf;
+extern cpuop_func op_6aff_0_ff;
+extern cpuop_func op_6b00_0_nf;
+extern cpuop_func op_6b00_0_ff;
+extern cpuop_func op_6b01_0_nf;
+extern cpuop_func op_6b01_0_ff;
+extern cpuop_func op_6bff_0_nf;
+extern cpuop_func op_6bff_0_ff;
+extern cpuop_func op_6c00_0_nf;
+extern cpuop_func op_6c00_0_ff;
+extern cpuop_func op_6c01_0_nf;
+extern cpuop_func op_6c01_0_ff;
+extern cpuop_func op_6cff_0_nf;
+extern cpuop_func op_6cff_0_ff;
+extern cpuop_func op_6d00_0_nf;
+extern cpuop_func op_6d00_0_ff;
+extern cpuop_func op_6d01_0_nf;
+extern cpuop_func op_6d01_0_ff;
+extern cpuop_func op_6dff_0_nf;
+extern cpuop_func op_6dff_0_ff;
+extern cpuop_func op_6e00_0_nf;
+extern cpuop_func op_6e00_0_ff;
+extern cpuop_func op_6e01_0_nf;
+extern cpuop_func op_6e01_0_ff;
+extern cpuop_func op_6eff_0_nf;
+extern cpuop_func op_6eff_0_ff;
+extern cpuop_func op_6f00_0_nf;
+extern cpuop_func op_6f00_0_ff;
+extern cpuop_func op_6f01_0_nf;
+extern cpuop_func op_6f01_0_ff;
+extern cpuop_func op_6fff_0_nf;
+extern cpuop_func op_6fff_0_ff;
+extern cpuop_func op_7000_0_nf;
+extern cpuop_func op_7000_0_ff;
+extern cpuop_func op_8000_0_nf;
+extern cpuop_func op_8000_0_ff;
+extern cpuop_func op_8010_0_nf;
+extern cpuop_func op_8010_0_ff;
+extern cpuop_func op_8018_0_nf;
+extern cpuop_func op_8018_0_ff;
+extern cpuop_func op_8020_0_nf;
+extern cpuop_func op_8020_0_ff;
+extern cpuop_func op_8028_0_nf;
+extern cpuop_func op_8028_0_ff;
+extern cpuop_func op_8030_0_nf;
+extern cpuop_func op_8030_0_ff;
+extern cpuop_func op_8038_0_nf;
+extern cpuop_func op_8038_0_ff;
+extern cpuop_func op_8039_0_nf;
+extern cpuop_func op_8039_0_ff;
+extern cpuop_func op_803a_0_nf;
+extern cpuop_func op_803a_0_ff;
+extern cpuop_func op_803b_0_nf;
+extern cpuop_func op_803b_0_ff;
+extern cpuop_func op_803c_0_nf;
+extern cpuop_func op_803c_0_ff;
+extern cpuop_func op_8040_0_nf;
+extern cpuop_func op_8040_0_ff;
+extern cpuop_func op_8050_0_nf;
+extern cpuop_func op_8050_0_ff;
+extern cpuop_func op_8058_0_nf;
+extern cpuop_func op_8058_0_ff;
+extern cpuop_func op_8060_0_nf;
+extern cpuop_func op_8060_0_ff;
+extern cpuop_func op_8068_0_nf;
+extern cpuop_func op_8068_0_ff;
+extern cpuop_func op_8070_0_nf;
+extern cpuop_func op_8070_0_ff;
+extern cpuop_func op_8078_0_nf;
+extern cpuop_func op_8078_0_ff;
+extern cpuop_func op_8079_0_nf;
+extern cpuop_func op_8079_0_ff;
+extern cpuop_func op_807a_0_nf;
+extern cpuop_func op_807a_0_ff;
+extern cpuop_func op_807b_0_nf;
+extern cpuop_func op_807b_0_ff;
+extern cpuop_func op_807c_0_nf;
+extern cpuop_func op_807c_0_ff;
+extern cpuop_func op_8080_0_nf;
+extern cpuop_func op_8080_0_ff;
+extern cpuop_func op_8090_0_nf;
+extern cpuop_func op_8090_0_ff;
+extern cpuop_func op_8098_0_nf;
+extern cpuop_func op_8098_0_ff;
+extern cpuop_func op_80a0_0_nf;
+extern cpuop_func op_80a0_0_ff;
+extern cpuop_func op_80a8_0_nf;
+extern cpuop_func op_80a8_0_ff;
+extern cpuop_func op_80b0_0_nf;
+extern cpuop_func op_80b0_0_ff;
+extern cpuop_func op_80b8_0_nf;
+extern cpuop_func op_80b8_0_ff;
+extern cpuop_func op_80b9_0_nf;
+extern cpuop_func op_80b9_0_ff;
+extern cpuop_func op_80ba_0_nf;
+extern cpuop_func op_80ba_0_ff;
+extern cpuop_func op_80bb_0_nf;
+extern cpuop_func op_80bb_0_ff;
+extern cpuop_func op_80bc_0_nf;
+extern cpuop_func op_80bc_0_ff;
+extern cpuop_func op_80c0_0_nf;
+extern cpuop_func op_80c0_0_ff;
+extern cpuop_func op_80d0_0_nf;
+extern cpuop_func op_80d0_0_ff;
+extern cpuop_func op_80d8_0_nf;
+extern cpuop_func op_80d8_0_ff;
+extern cpuop_func op_80e0_0_nf;
+extern cpuop_func op_80e0_0_ff;
+extern cpuop_func op_80e8_0_nf;
+extern cpuop_func op_80e8_0_ff;
+extern cpuop_func op_80f0_0_nf;
+extern cpuop_func op_80f0_0_ff;
+extern cpuop_func op_80f8_0_nf;
+extern cpuop_func op_80f8_0_ff;
+extern cpuop_func op_80f9_0_nf;
+extern cpuop_func op_80f9_0_ff;
+extern cpuop_func op_80fa_0_nf;
+extern cpuop_func op_80fa_0_ff;
+extern cpuop_func op_80fb_0_nf;
+extern cpuop_func op_80fb_0_ff;
+extern cpuop_func op_80fc_0_nf;
+extern cpuop_func op_80fc_0_ff;
+extern cpuop_func op_8100_0_nf;
+extern cpuop_func op_8100_0_ff;
+extern cpuop_func op_8108_0_nf;
+extern cpuop_func op_8108_0_ff;
+extern cpuop_func op_8110_0_nf;
+extern cpuop_func op_8110_0_ff;
+extern cpuop_func op_8118_0_nf;
+extern cpuop_func op_8118_0_ff;
+extern cpuop_func op_8120_0_nf;
+extern cpuop_func op_8120_0_ff;
+extern cpuop_func op_8128_0_nf;
+extern cpuop_func op_8128_0_ff;
+extern cpuop_func op_8130_0_nf;
+extern cpuop_func op_8130_0_ff;
+extern cpuop_func op_8138_0_nf;
+extern cpuop_func op_8138_0_ff;
+extern cpuop_func op_8139_0_nf;
+extern cpuop_func op_8139_0_ff;
+extern cpuop_func op_8140_0_nf;
+extern cpuop_func op_8140_0_ff;
+extern cpuop_func op_8148_0_nf;
+extern cpuop_func op_8148_0_ff;
+extern cpuop_func op_8150_0_nf;
+extern cpuop_func op_8150_0_ff;
+extern cpuop_func op_8158_0_nf;
+extern cpuop_func op_8158_0_ff;
+extern cpuop_func op_8160_0_nf;
+extern cpuop_func op_8160_0_ff;
+extern cpuop_func op_8168_0_nf;
+extern cpuop_func op_8168_0_ff;
+extern cpuop_func op_8170_0_nf;
+extern cpuop_func op_8170_0_ff;
+extern cpuop_func op_8178_0_nf;
+extern cpuop_func op_8178_0_ff;
+extern cpuop_func op_8179_0_nf;
+extern cpuop_func op_8179_0_ff;
+extern cpuop_func op_8180_0_nf;
+extern cpuop_func op_8180_0_ff;
+extern cpuop_func op_8188_0_nf;
+extern cpuop_func op_8188_0_ff;
+extern cpuop_func op_8190_0_nf;
+extern cpuop_func op_8190_0_ff;
+extern cpuop_func op_8198_0_nf;
+extern cpuop_func op_8198_0_ff;
+extern cpuop_func op_81a0_0_nf;
+extern cpuop_func op_81a0_0_ff;
+extern cpuop_func op_81a8_0_nf;
+extern cpuop_func op_81a8_0_ff;
+extern cpuop_func op_81b0_0_nf;
+extern cpuop_func op_81b0_0_ff;
+extern cpuop_func op_81b8_0_nf;
+extern cpuop_func op_81b8_0_ff;
+extern cpuop_func op_81b9_0_nf;
+extern cpuop_func op_81b9_0_ff;
+extern cpuop_func op_81c0_0_nf;
+extern cpuop_func op_81c0_0_ff;
+extern cpuop_func op_81d0_0_nf;
+extern cpuop_func op_81d0_0_ff;
+extern cpuop_func op_81d8_0_nf;
+extern cpuop_func op_81d8_0_ff;
+extern cpuop_func op_81e0_0_nf;
+extern cpuop_func op_81e0_0_ff;
+extern cpuop_func op_81e8_0_nf;
+extern cpuop_func op_81e8_0_ff;
+extern cpuop_func op_81f0_0_nf;
+extern cpuop_func op_81f0_0_ff;
+extern cpuop_func op_81f8_0_nf;
+extern cpuop_func op_81f8_0_ff;
+extern cpuop_func op_81f9_0_nf;
+extern cpuop_func op_81f9_0_ff;
+extern cpuop_func op_81fa_0_nf;
+extern cpuop_func op_81fa_0_ff;
+extern cpuop_func op_81fb_0_nf;
+extern cpuop_func op_81fb_0_ff;
+extern cpuop_func op_81fc_0_nf;
+extern cpuop_func op_81fc_0_ff;
+extern cpuop_func op_9000_0_nf;
+extern cpuop_func op_9000_0_ff;
+extern cpuop_func op_9010_0_nf;
+extern cpuop_func op_9010_0_ff;
+extern cpuop_func op_9018_0_nf;
+extern cpuop_func op_9018_0_ff;
+extern cpuop_func op_9020_0_nf;
+extern cpuop_func op_9020_0_ff;
+extern cpuop_func op_9028_0_nf;
+extern cpuop_func op_9028_0_ff;
+extern cpuop_func op_9030_0_nf;
+extern cpuop_func op_9030_0_ff;
+extern cpuop_func op_9038_0_nf;
+extern cpuop_func op_9038_0_ff;
+extern cpuop_func op_9039_0_nf;
+extern cpuop_func op_9039_0_ff;
+extern cpuop_func op_903a_0_nf;
+extern cpuop_func op_903a_0_ff;
+extern cpuop_func op_903b_0_nf;
+extern cpuop_func op_903b_0_ff;
+extern cpuop_func op_903c_0_nf;
+extern cpuop_func op_903c_0_ff;
+extern cpuop_func op_9040_0_nf;
+extern cpuop_func op_9040_0_ff;
+extern cpuop_func op_9048_0_nf;
+extern cpuop_func op_9048_0_ff;
+extern cpuop_func op_9050_0_nf;
+extern cpuop_func op_9050_0_ff;
+extern cpuop_func op_9058_0_nf;
+extern cpuop_func op_9058_0_ff;
+extern cpuop_func op_9060_0_nf;
+extern cpuop_func op_9060_0_ff;
+extern cpuop_func op_9068_0_nf;
+extern cpuop_func op_9068_0_ff;
+extern cpuop_func op_9070_0_nf;
+extern cpuop_func op_9070_0_ff;
+extern cpuop_func op_9078_0_nf;
+extern cpuop_func op_9078_0_ff;
+extern cpuop_func op_9079_0_nf;
+extern cpuop_func op_9079_0_ff;
+extern cpuop_func op_907a_0_nf;
+extern cpuop_func op_907a_0_ff;
+extern cpuop_func op_907b_0_nf;
+extern cpuop_func op_907b_0_ff;
+extern cpuop_func op_907c_0_nf;
+extern cpuop_func op_907c_0_ff;
+extern cpuop_func op_9080_0_nf;
+extern cpuop_func op_9080_0_ff;
+extern cpuop_func op_9088_0_nf;
+extern cpuop_func op_9088_0_ff;
+extern cpuop_func op_9090_0_nf;
+extern cpuop_func op_9090_0_ff;
+extern cpuop_func op_9098_0_nf;
+extern cpuop_func op_9098_0_ff;
+extern cpuop_func op_90a0_0_nf;
+extern cpuop_func op_90a0_0_ff;
+extern cpuop_func op_90a8_0_nf;
+extern cpuop_func op_90a8_0_ff;
+extern cpuop_func op_90b0_0_nf;
+extern cpuop_func op_90b0_0_ff;
+extern cpuop_func op_90b8_0_nf;
+extern cpuop_func op_90b8_0_ff;
+extern cpuop_func op_90b9_0_nf;
+extern cpuop_func op_90b9_0_ff;
+extern cpuop_func op_90ba_0_nf;
+extern cpuop_func op_90ba_0_ff;
+extern cpuop_func op_90bb_0_nf;
+extern cpuop_func op_90bb_0_ff;
+extern cpuop_func op_90bc_0_nf;
+extern cpuop_func op_90bc_0_ff;
+extern cpuop_func op_90c0_0_nf;
+extern cpuop_func op_90c0_0_ff;
+extern cpuop_func op_90c8_0_nf;
+extern cpuop_func op_90c8_0_ff;
+extern cpuop_func op_90d0_0_nf;
+extern cpuop_func op_90d0_0_ff;
+extern cpuop_func op_90d8_0_nf;
+extern cpuop_func op_90d8_0_ff;
+extern cpuop_func op_90e0_0_nf;
+extern cpuop_func op_90e0_0_ff;
+extern cpuop_func op_90e8_0_nf;
+extern cpuop_func op_90e8_0_ff;
+extern cpuop_func op_90f0_0_nf;
+extern cpuop_func op_90f0_0_ff;
+extern cpuop_func op_90f8_0_nf;
+extern cpuop_func op_90f8_0_ff;
+extern cpuop_func op_90f9_0_nf;
+extern cpuop_func op_90f9_0_ff;
+extern cpuop_func op_90fa_0_nf;
+extern cpuop_func op_90fa_0_ff;
+extern cpuop_func op_90fb_0_nf;
+extern cpuop_func op_90fb_0_ff;
+extern cpuop_func op_90fc_0_nf;
+extern cpuop_func op_90fc_0_ff;
+extern cpuop_func op_9100_0_nf;
+extern cpuop_func op_9100_0_ff;
+extern cpuop_func op_9108_0_nf;
+extern cpuop_func op_9108_0_ff;
+extern cpuop_func op_9110_0_nf;
+extern cpuop_func op_9110_0_ff;
+extern cpuop_func op_9118_0_nf;
+extern cpuop_func op_9118_0_ff;
+extern cpuop_func op_9120_0_nf;
+extern cpuop_func op_9120_0_ff;
+extern cpuop_func op_9128_0_nf;
+extern cpuop_func op_9128_0_ff;
+extern cpuop_func op_9130_0_nf;
+extern cpuop_func op_9130_0_ff;
+extern cpuop_func op_9138_0_nf;
+extern cpuop_func op_9138_0_ff;
+extern cpuop_func op_9139_0_nf;
+extern cpuop_func op_9139_0_ff;
+extern cpuop_func op_9140_0_nf;
+extern cpuop_func op_9140_0_ff;
+extern cpuop_func op_9148_0_nf;
+extern cpuop_func op_9148_0_ff;
+extern cpuop_func op_9150_0_nf;
+extern cpuop_func op_9150_0_ff;
+extern cpuop_func op_9158_0_nf;
+extern cpuop_func op_9158_0_ff;
+extern cpuop_func op_9160_0_nf;
+extern cpuop_func op_9160_0_ff;
+extern cpuop_func op_9168_0_nf;
+extern cpuop_func op_9168_0_ff;
+extern cpuop_func op_9170_0_nf;
+extern cpuop_func op_9170_0_ff;
+extern cpuop_func op_9178_0_nf;
+extern cpuop_func op_9178_0_ff;
+extern cpuop_func op_9179_0_nf;
+extern cpuop_func op_9179_0_ff;
+extern cpuop_func op_9180_0_nf;
+extern cpuop_func op_9180_0_ff;
+extern cpuop_func op_9188_0_nf;
+extern cpuop_func op_9188_0_ff;
+extern cpuop_func op_9190_0_nf;
+extern cpuop_func op_9190_0_ff;
+extern cpuop_func op_9198_0_nf;
+extern cpuop_func op_9198_0_ff;
+extern cpuop_func op_91a0_0_nf;
+extern cpuop_func op_91a0_0_ff;
+extern cpuop_func op_91a8_0_nf;
+extern cpuop_func op_91a8_0_ff;
+extern cpuop_func op_91b0_0_nf;
+extern cpuop_func op_91b0_0_ff;
+extern cpuop_func op_91b8_0_nf;
+extern cpuop_func op_91b8_0_ff;
+extern cpuop_func op_91b9_0_nf;
+extern cpuop_func op_91b9_0_ff;
+extern cpuop_func op_91c0_0_nf;
+extern cpuop_func op_91c0_0_ff;
+extern cpuop_func op_91c8_0_nf;
+extern cpuop_func op_91c8_0_ff;
+extern cpuop_func op_91d0_0_nf;
+extern cpuop_func op_91d0_0_ff;
+extern cpuop_func op_91d8_0_nf;
+extern cpuop_func op_91d8_0_ff;
+extern cpuop_func op_91e0_0_nf;
+extern cpuop_func op_91e0_0_ff;
+extern cpuop_func op_91e8_0_nf;
+extern cpuop_func op_91e8_0_ff;
+extern cpuop_func op_91f0_0_nf;
+extern cpuop_func op_91f0_0_ff;
+extern cpuop_func op_91f8_0_nf;
+extern cpuop_func op_91f8_0_ff;
+extern cpuop_func op_91f9_0_nf;
+extern cpuop_func op_91f9_0_ff;
+extern cpuop_func op_91fa_0_nf;
+extern cpuop_func op_91fa_0_ff;
+extern cpuop_func op_91fb_0_nf;
+extern cpuop_func op_91fb_0_ff;
+extern cpuop_func op_91fc_0_nf;
+extern cpuop_func op_91fc_0_ff;
+extern cpuop_func op_b000_0_nf;
+extern cpuop_func op_b000_0_ff;
+extern cpuop_func op_b010_0_nf;
+extern cpuop_func op_b010_0_ff;
+extern cpuop_func op_b018_0_nf;
+extern cpuop_func op_b018_0_ff;
+extern cpuop_func op_b020_0_nf;
+extern cpuop_func op_b020_0_ff;
+extern cpuop_func op_b028_0_nf;
+extern cpuop_func op_b028_0_ff;
+extern cpuop_func op_b030_0_nf;
+extern cpuop_func op_b030_0_ff;
+extern cpuop_func op_b038_0_nf;
+extern cpuop_func op_b038_0_ff;
+extern cpuop_func op_b039_0_nf;
+extern cpuop_func op_b039_0_ff;
+extern cpuop_func op_b03a_0_nf;
+extern cpuop_func op_b03a_0_ff;
+extern cpuop_func op_b03b_0_nf;
+extern cpuop_func op_b03b_0_ff;
+extern cpuop_func op_b03c_0_nf;
+extern cpuop_func op_b03c_0_ff;
+extern cpuop_func op_b040_0_nf;
+extern cpuop_func op_b040_0_ff;
+extern cpuop_func op_b048_0_nf;
+extern cpuop_func op_b048_0_ff;
+extern cpuop_func op_b050_0_nf;
+extern cpuop_func op_b050_0_ff;
+extern cpuop_func op_b058_0_nf;
+extern cpuop_func op_b058_0_ff;
+extern cpuop_func op_b060_0_nf;
+extern cpuop_func op_b060_0_ff;
+extern cpuop_func op_b068_0_nf;
+extern cpuop_func op_b068_0_ff;
+extern cpuop_func op_b070_0_nf;
+extern cpuop_func op_b070_0_ff;
+extern cpuop_func op_b078_0_nf;
+extern cpuop_func op_b078_0_ff;
+extern cpuop_func op_b079_0_nf;
+extern cpuop_func op_b079_0_ff;
+extern cpuop_func op_b07a_0_nf;
+extern cpuop_func op_b07a_0_ff;
+extern cpuop_func op_b07b_0_nf;
+extern cpuop_func op_b07b_0_ff;
+extern cpuop_func op_b07c_0_nf;
+extern cpuop_func op_b07c_0_ff;
+extern cpuop_func op_b080_0_nf;
+extern cpuop_func op_b080_0_ff;
+extern cpuop_func op_b088_0_nf;
+extern cpuop_func op_b088_0_ff;
+extern cpuop_func op_b090_0_nf;
+extern cpuop_func op_b090_0_ff;
+extern cpuop_func op_b098_0_nf;
+extern cpuop_func op_b098_0_ff;
+extern cpuop_func op_b0a0_0_nf;
+extern cpuop_func op_b0a0_0_ff;
+extern cpuop_func op_b0a8_0_nf;
+extern cpuop_func op_b0a8_0_ff;
+extern cpuop_func op_b0b0_0_nf;
+extern cpuop_func op_b0b0_0_ff;
+extern cpuop_func op_b0b8_0_nf;
+extern cpuop_func op_b0b8_0_ff;
+extern cpuop_func op_b0b9_0_nf;
+extern cpuop_func op_b0b9_0_ff;
+extern cpuop_func op_b0ba_0_nf;
+extern cpuop_func op_b0ba_0_ff;
+extern cpuop_func op_b0bb_0_nf;
+extern cpuop_func op_b0bb_0_ff;
+extern cpuop_func op_b0bc_0_nf;
+extern cpuop_func op_b0bc_0_ff;
+extern cpuop_func op_b0c0_0_nf;
+extern cpuop_func op_b0c0_0_ff;
+extern cpuop_func op_b0c8_0_nf;
+extern cpuop_func op_b0c8_0_ff;
+extern cpuop_func op_b0d0_0_nf;
+extern cpuop_func op_b0d0_0_ff;
+extern cpuop_func op_b0d8_0_nf;
+extern cpuop_func op_b0d8_0_ff;
+extern cpuop_func op_b0e0_0_nf;
+extern cpuop_func op_b0e0_0_ff;
+extern cpuop_func op_b0e8_0_nf;
+extern cpuop_func op_b0e8_0_ff;
+extern cpuop_func op_b0f0_0_nf;
+extern cpuop_func op_b0f0_0_ff;
+extern cpuop_func op_b0f8_0_nf;
+extern cpuop_func op_b0f8_0_ff;
+extern cpuop_func op_b0f9_0_nf;
+extern cpuop_func op_b0f9_0_ff;
+extern cpuop_func op_b0fa_0_nf;
+extern cpuop_func op_b0fa_0_ff;
+extern cpuop_func op_b0fb_0_nf;
+extern cpuop_func op_b0fb_0_ff;
+extern cpuop_func op_b0fc_0_nf;
+extern cpuop_func op_b0fc_0_ff;
+extern cpuop_func op_b100_0_nf;
+extern cpuop_func op_b100_0_ff;
+extern cpuop_func op_b108_0_nf;
+extern cpuop_func op_b108_0_ff;
+extern cpuop_func op_b110_0_nf;
+extern cpuop_func op_b110_0_ff;
+extern cpuop_func op_b118_0_nf;
+extern cpuop_func op_b118_0_ff;
+extern cpuop_func op_b120_0_nf;
+extern cpuop_func op_b120_0_ff;
+extern cpuop_func op_b128_0_nf;
+extern cpuop_func op_b128_0_ff;
+extern cpuop_func op_b130_0_nf;
+extern cpuop_func op_b130_0_ff;
+extern cpuop_func op_b138_0_nf;
+extern cpuop_func op_b138_0_ff;
+extern cpuop_func op_b139_0_nf;
+extern cpuop_func op_b139_0_ff;
+extern cpuop_func op_b140_0_nf;
+extern cpuop_func op_b140_0_ff;
+extern cpuop_func op_b148_0_nf;
+extern cpuop_func op_b148_0_ff;
+extern cpuop_func op_b150_0_nf;
+extern cpuop_func op_b150_0_ff;
+extern cpuop_func op_b158_0_nf;
+extern cpuop_func op_b158_0_ff;
+extern cpuop_func op_b160_0_nf;
+extern cpuop_func op_b160_0_ff;
+extern cpuop_func op_b168_0_nf;
+extern cpuop_func op_b168_0_ff;
+extern cpuop_func op_b170_0_nf;
+extern cpuop_func op_b170_0_ff;
+extern cpuop_func op_b178_0_nf;
+extern cpuop_func op_b178_0_ff;
+extern cpuop_func op_b179_0_nf;
+extern cpuop_func op_b179_0_ff;
+extern cpuop_func op_b180_0_nf;
+extern cpuop_func op_b180_0_ff;
+extern cpuop_func op_b188_0_nf;
+extern cpuop_func op_b188_0_ff;
+extern cpuop_func op_b190_0_nf;
+extern cpuop_func op_b190_0_ff;
+extern cpuop_func op_b198_0_nf;
+extern cpuop_func op_b198_0_ff;
+extern cpuop_func op_b1a0_0_nf;
+extern cpuop_func op_b1a0_0_ff;
+extern cpuop_func op_b1a8_0_nf;
+extern cpuop_func op_b1a8_0_ff;
+extern cpuop_func op_b1b0_0_nf;
+extern cpuop_func op_b1b0_0_ff;
+extern cpuop_func op_b1b8_0_nf;
+extern cpuop_func op_b1b8_0_ff;
+extern cpuop_func op_b1b9_0_nf;
+extern cpuop_func op_b1b9_0_ff;
+extern cpuop_func op_b1c0_0_nf;
+extern cpuop_func op_b1c0_0_ff;
+extern cpuop_func op_b1c8_0_nf;
+extern cpuop_func op_b1c8_0_ff;
+extern cpuop_func op_b1d0_0_nf;
+extern cpuop_func op_b1d0_0_ff;
+extern cpuop_func op_b1d8_0_nf;
+extern cpuop_func op_b1d8_0_ff;
+extern cpuop_func op_b1e0_0_nf;
+extern cpuop_func op_b1e0_0_ff;
+extern cpuop_func op_b1e8_0_nf;
+extern cpuop_func op_b1e8_0_ff;
+extern cpuop_func op_b1f0_0_nf;
+extern cpuop_func op_b1f0_0_ff;
+extern cpuop_func op_b1f8_0_nf;
+extern cpuop_func op_b1f8_0_ff;
+extern cpuop_func op_b1f9_0_nf;
+extern cpuop_func op_b1f9_0_ff;
+extern cpuop_func op_b1fa_0_nf;
+extern cpuop_func op_b1fa_0_ff;
+extern cpuop_func op_b1fb_0_nf;
+extern cpuop_func op_b1fb_0_ff;
+extern cpuop_func op_b1fc_0_nf;
+extern cpuop_func op_b1fc_0_ff;
+extern cpuop_func op_c000_0_nf;
+extern cpuop_func op_c000_0_ff;
+extern cpuop_func op_c010_0_nf;
+extern cpuop_func op_c010_0_ff;
+extern cpuop_func op_c018_0_nf;
+extern cpuop_func op_c018_0_ff;
+extern cpuop_func op_c020_0_nf;
+extern cpuop_func op_c020_0_ff;
+extern cpuop_func op_c028_0_nf;
+extern cpuop_func op_c028_0_ff;
+extern cpuop_func op_c030_0_nf;
+extern cpuop_func op_c030_0_ff;
+extern cpuop_func op_c038_0_nf;
+extern cpuop_func op_c038_0_ff;
+extern cpuop_func op_c039_0_nf;
+extern cpuop_func op_c039_0_ff;
+extern cpuop_func op_c03a_0_nf;
+extern cpuop_func op_c03a_0_ff;
+extern cpuop_func op_c03b_0_nf;
+extern cpuop_func op_c03b_0_ff;
+extern cpuop_func op_c03c_0_nf;
+extern cpuop_func op_c03c_0_ff;
+extern cpuop_func op_c040_0_nf;
+extern cpuop_func op_c040_0_ff;
+extern cpuop_func op_c050_0_nf;
+extern cpuop_func op_c050_0_ff;
+extern cpuop_func op_c058_0_nf;
+extern cpuop_func op_c058_0_ff;
+extern cpuop_func op_c060_0_nf;
+extern cpuop_func op_c060_0_ff;
+extern cpuop_func op_c068_0_nf;
+extern cpuop_func op_c068_0_ff;
+extern cpuop_func op_c070_0_nf;
+extern cpuop_func op_c070_0_ff;
+extern cpuop_func op_c078_0_nf;
+extern cpuop_func op_c078_0_ff;
+extern cpuop_func op_c079_0_nf;
+extern cpuop_func op_c079_0_ff;
+extern cpuop_func op_c07a_0_nf;
+extern cpuop_func op_c07a_0_ff;
+extern cpuop_func op_c07b_0_nf;
+extern cpuop_func op_c07b_0_ff;
+extern cpuop_func op_c07c_0_nf;
+extern cpuop_func op_c07c_0_ff;
+extern cpuop_func op_c080_0_nf;
+extern cpuop_func op_c080_0_ff;
+extern cpuop_func op_c090_0_nf;
+extern cpuop_func op_c090_0_ff;
+extern cpuop_func op_c098_0_nf;
+extern cpuop_func op_c098_0_ff;
+extern cpuop_func op_c0a0_0_nf;
+extern cpuop_func op_c0a0_0_ff;
+extern cpuop_func op_c0a8_0_nf;
+extern cpuop_func op_c0a8_0_ff;
+extern cpuop_func op_c0b0_0_nf;
+extern cpuop_func op_c0b0_0_ff;
+extern cpuop_func op_c0b8_0_nf;
+extern cpuop_func op_c0b8_0_ff;
+extern cpuop_func op_c0b9_0_nf;
+extern cpuop_func op_c0b9_0_ff;
+extern cpuop_func op_c0ba_0_nf;
+extern cpuop_func op_c0ba_0_ff;
+extern cpuop_func op_c0bb_0_nf;
+extern cpuop_func op_c0bb_0_ff;
+extern cpuop_func op_c0bc_0_nf;
+extern cpuop_func op_c0bc_0_ff;
+extern cpuop_func op_c0c0_0_nf;
+extern cpuop_func op_c0c0_0_ff;
+extern cpuop_func op_c0d0_0_nf;
+extern cpuop_func op_c0d0_0_ff;
+extern cpuop_func op_c0d8_0_nf;
+extern cpuop_func op_c0d8_0_ff;
+extern cpuop_func op_c0e0_0_nf;
+extern cpuop_func op_c0e0_0_ff;
+extern cpuop_func op_c0e8_0_nf;
+extern cpuop_func op_c0e8_0_ff;
+extern cpuop_func op_c0f0_0_nf;
+extern cpuop_func op_c0f0_0_ff;
+extern cpuop_func op_c0f8_0_nf;
+extern cpuop_func op_c0f8_0_ff;
+extern cpuop_func op_c0f9_0_nf;
+extern cpuop_func op_c0f9_0_ff;
+extern cpuop_func op_c0fa_0_nf;
+extern cpuop_func op_c0fa_0_ff;
+extern cpuop_func op_c0fb_0_nf;
+extern cpuop_func op_c0fb_0_ff;
+extern cpuop_func op_c0fc_0_nf;
+extern cpuop_func op_c0fc_0_ff;
+extern cpuop_func op_c100_0_nf;
+extern cpuop_func op_c100_0_ff;
+extern cpuop_func op_c108_0_nf;
+extern cpuop_func op_c108_0_ff;
+extern cpuop_func op_c110_0_nf;
+extern cpuop_func op_c110_0_ff;
+extern cpuop_func op_c118_0_nf;
+extern cpuop_func op_c118_0_ff;
+extern cpuop_func op_c120_0_nf;
+extern cpuop_func op_c120_0_ff;
+extern cpuop_func op_c128_0_nf;
+extern cpuop_func op_c128_0_ff;
+extern cpuop_func op_c130_0_nf;
+extern cpuop_func op_c130_0_ff;
+extern cpuop_func op_c138_0_nf;
+extern cpuop_func op_c138_0_ff;
+extern cpuop_func op_c139_0_nf;
+extern cpuop_func op_c139_0_ff;
+extern cpuop_func op_c140_0_nf;
+extern cpuop_func op_c140_0_ff;
+extern cpuop_func op_c148_0_nf;
+extern cpuop_func op_c148_0_ff;
+extern cpuop_func op_c150_0_nf;
+extern cpuop_func op_c150_0_ff;
+extern cpuop_func op_c158_0_nf;
+extern cpuop_func op_c158_0_ff;
+extern cpuop_func op_c160_0_nf;
+extern cpuop_func op_c160_0_ff;
+extern cpuop_func op_c168_0_nf;
+extern cpuop_func op_c168_0_ff;
+extern cpuop_func op_c170_0_nf;
+extern cpuop_func op_c170_0_ff;
+extern cpuop_func op_c178_0_nf;
+extern cpuop_func op_c178_0_ff;
+extern cpuop_func op_c179_0_nf;
+extern cpuop_func op_c179_0_ff;
+extern cpuop_func op_c188_0_nf;
+extern cpuop_func op_c188_0_ff;
+extern cpuop_func op_c190_0_nf;
+extern cpuop_func op_c190_0_ff;
+extern cpuop_func op_c198_0_nf;
+extern cpuop_func op_c198_0_ff;
+extern cpuop_func op_c1a0_0_nf;
+extern cpuop_func op_c1a0_0_ff;
+extern cpuop_func op_c1a8_0_nf;
+extern cpuop_func op_c1a8_0_ff;
+extern cpuop_func op_c1b0_0_nf;
+extern cpuop_func op_c1b0_0_ff;
+extern cpuop_func op_c1b8_0_nf;
+extern cpuop_func op_c1b8_0_ff;
+extern cpuop_func op_c1b9_0_nf;
+extern cpuop_func op_c1b9_0_ff;
+extern cpuop_func op_c1c0_0_nf;
+extern cpuop_func op_c1c0_0_ff;
+extern cpuop_func op_c1d0_0_nf;
+extern cpuop_func op_c1d0_0_ff;
+extern cpuop_func op_c1d8_0_nf;
+extern cpuop_func op_c1d8_0_ff;
+extern cpuop_func op_c1e0_0_nf;
+extern cpuop_func op_c1e0_0_ff;
+extern cpuop_func op_c1e8_0_nf;
+extern cpuop_func op_c1e8_0_ff;
+extern cpuop_func op_c1f0_0_nf;
+extern cpuop_func op_c1f0_0_ff;
+extern cpuop_func op_c1f8_0_nf;
+extern cpuop_func op_c1f8_0_ff;
+extern cpuop_func op_c1f9_0_nf;
+extern cpuop_func op_c1f9_0_ff;
+extern cpuop_func op_c1fa_0_nf;
+extern cpuop_func op_c1fa_0_ff;
+extern cpuop_func op_c1fb_0_nf;
+extern cpuop_func op_c1fb_0_ff;
+extern cpuop_func op_c1fc_0_nf;
+extern cpuop_func op_c1fc_0_ff;
+extern cpuop_func op_d000_0_nf;
+extern cpuop_func op_d000_0_ff;
+extern cpuop_func op_d010_0_nf;
+extern cpuop_func op_d010_0_ff;
+extern cpuop_func op_d018_0_nf;
+extern cpuop_func op_d018_0_ff;
+extern cpuop_func op_d020_0_nf;
+extern cpuop_func op_d020_0_ff;
+extern cpuop_func op_d028_0_nf;
+extern cpuop_func op_d028_0_ff;
+extern cpuop_func op_d030_0_nf;
+extern cpuop_func op_d030_0_ff;
+extern cpuop_func op_d038_0_nf;
+extern cpuop_func op_d038_0_ff;
+extern cpuop_func op_d039_0_nf;
+extern cpuop_func op_d039_0_ff;
+extern cpuop_func op_d03a_0_nf;
+extern cpuop_func op_d03a_0_ff;
+extern cpuop_func op_d03b_0_nf;
+extern cpuop_func op_d03b_0_ff;
+extern cpuop_func op_d03c_0_nf;
+extern cpuop_func op_d03c_0_ff;
+extern cpuop_func op_d040_0_nf;
+extern cpuop_func op_d040_0_ff;
+extern cpuop_func op_d048_0_nf;
+extern cpuop_func op_d048_0_ff;
+extern cpuop_func op_d050_0_nf;
+extern cpuop_func op_d050_0_ff;
+extern cpuop_func op_d058_0_nf;
+extern cpuop_func op_d058_0_ff;
+extern cpuop_func op_d060_0_nf;
+extern cpuop_func op_d060_0_ff;
+extern cpuop_func op_d068_0_nf;
+extern cpuop_func op_d068_0_ff;
+extern cpuop_func op_d070_0_nf;
+extern cpuop_func op_d070_0_ff;
+extern cpuop_func op_d078_0_nf;
+extern cpuop_func op_d078_0_ff;
+extern cpuop_func op_d079_0_nf;
+extern cpuop_func op_d079_0_ff;
+extern cpuop_func op_d07a_0_nf;
+extern cpuop_func op_d07a_0_ff;
+extern cpuop_func op_d07b_0_nf;
+extern cpuop_func op_d07b_0_ff;
+extern cpuop_func op_d07c_0_nf;
+extern cpuop_func op_d07c_0_ff;
+extern cpuop_func op_d080_0_nf;
+extern cpuop_func op_d080_0_ff;
+extern cpuop_func op_d088_0_nf;
+extern cpuop_func op_d088_0_ff;
+extern cpuop_func op_d090_0_nf;
+extern cpuop_func op_d090_0_ff;
+extern cpuop_func op_d098_0_nf;
+extern cpuop_func op_d098_0_ff;
+extern cpuop_func op_d0a0_0_nf;
+extern cpuop_func op_d0a0_0_ff;
+extern cpuop_func op_d0a8_0_nf;
+extern cpuop_func op_d0a8_0_ff;
+extern cpuop_func op_d0b0_0_nf;
+extern cpuop_func op_d0b0_0_ff;
+extern cpuop_func op_d0b8_0_nf;
+extern cpuop_func op_d0b8_0_ff;
+extern cpuop_func op_d0b9_0_nf;
+extern cpuop_func op_d0b9_0_ff;
+extern cpuop_func op_d0ba_0_nf;
+extern cpuop_func op_d0ba_0_ff;
+extern cpuop_func op_d0bb_0_nf;
+extern cpuop_func op_d0bb_0_ff;
+extern cpuop_func op_d0bc_0_nf;
+extern cpuop_func op_d0bc_0_ff;
+extern cpuop_func op_d0c0_0_nf;
+extern cpuop_func op_d0c0_0_ff;
+extern cpuop_func op_d0c8_0_nf;
+extern cpuop_func op_d0c8_0_ff;
+extern cpuop_func op_d0d0_0_nf;
+extern cpuop_func op_d0d0_0_ff;
+extern cpuop_func op_d0d8_0_nf;
+extern cpuop_func op_d0d8_0_ff;
+extern cpuop_func op_d0e0_0_nf;
+extern cpuop_func op_d0e0_0_ff;
+extern cpuop_func op_d0e8_0_nf;
+extern cpuop_func op_d0e8_0_ff;
+extern cpuop_func op_d0f0_0_nf;
+extern cpuop_func op_d0f0_0_ff;
+extern cpuop_func op_d0f8_0_nf;
+extern cpuop_func op_d0f8_0_ff;
+extern cpuop_func op_d0f9_0_nf;
+extern cpuop_func op_d0f9_0_ff;
+extern cpuop_func op_d0fa_0_nf;
+extern cpuop_func op_d0fa_0_ff;
+extern cpuop_func op_d0fb_0_nf;
+extern cpuop_func op_d0fb_0_ff;
+extern cpuop_func op_d0fc_0_nf;
+extern cpuop_func op_d0fc_0_ff;
+extern cpuop_func op_d100_0_nf;
+extern cpuop_func op_d100_0_ff;
+extern cpuop_func op_d108_0_nf;
+extern cpuop_func op_d108_0_ff;
+extern cpuop_func op_d110_0_nf;
+extern cpuop_func op_d110_0_ff;
+extern cpuop_func op_d118_0_nf;
+extern cpuop_func op_d118_0_ff;
+extern cpuop_func op_d120_0_nf;
+extern cpuop_func op_d120_0_ff;
+extern cpuop_func op_d128_0_nf;
+extern cpuop_func op_d128_0_ff;
+extern cpuop_func op_d130_0_nf;
+extern cpuop_func op_d130_0_ff;
+extern cpuop_func op_d138_0_nf;
+extern cpuop_func op_d138_0_ff;
+extern cpuop_func op_d139_0_nf;
+extern cpuop_func op_d139_0_ff;
+extern cpuop_func op_d140_0_nf;
+extern cpuop_func op_d140_0_ff;
+extern cpuop_func op_d148_0_nf;
+extern cpuop_func op_d148_0_ff;
+extern cpuop_func op_d150_0_nf;
+extern cpuop_func op_d150_0_ff;
+extern cpuop_func op_d158_0_nf;
+extern cpuop_func op_d158_0_ff;
+extern cpuop_func op_d160_0_nf;
+extern cpuop_func op_d160_0_ff;
+extern cpuop_func op_d168_0_nf;
+extern cpuop_func op_d168_0_ff;
+extern cpuop_func op_d170_0_nf;
+extern cpuop_func op_d170_0_ff;
+extern cpuop_func op_d178_0_nf;
+extern cpuop_func op_d178_0_ff;
+extern cpuop_func op_d179_0_nf;
+extern cpuop_func op_d179_0_ff;
+extern cpuop_func op_d180_0_nf;
+extern cpuop_func op_d180_0_ff;
+extern cpuop_func op_d188_0_nf;
+extern cpuop_func op_d188_0_ff;
+extern cpuop_func op_d190_0_nf;
+extern cpuop_func op_d190_0_ff;
+extern cpuop_func op_d198_0_nf;
+extern cpuop_func op_d198_0_ff;
+extern cpuop_func op_d1a0_0_nf;
+extern cpuop_func op_d1a0_0_ff;
+extern cpuop_func op_d1a8_0_nf;
+extern cpuop_func op_d1a8_0_ff;
+extern cpuop_func op_d1b0_0_nf;
+extern cpuop_func op_d1b0_0_ff;
+extern cpuop_func op_d1b8_0_nf;
+extern cpuop_func op_d1b8_0_ff;
+extern cpuop_func op_d1b9_0_nf;
+extern cpuop_func op_d1b9_0_ff;
+extern cpuop_func op_d1c0_0_nf;
+extern cpuop_func op_d1c0_0_ff;
+extern cpuop_func op_d1c8_0_nf;
+extern cpuop_func op_d1c8_0_ff;
+extern cpuop_func op_d1d0_0_nf;
+extern cpuop_func op_d1d0_0_ff;
+extern cpuop_func op_d1d8_0_nf;
+extern cpuop_func op_d1d8_0_ff;
+extern cpuop_func op_d1e0_0_nf;
+extern cpuop_func op_d1e0_0_ff;
+extern cpuop_func op_d1e8_0_nf;
+extern cpuop_func op_d1e8_0_ff;
+extern cpuop_func op_d1f0_0_nf;
+extern cpuop_func op_d1f0_0_ff;
+extern cpuop_func op_d1f8_0_nf;
+extern cpuop_func op_d1f8_0_ff;
+extern cpuop_func op_d1f9_0_nf;
+extern cpuop_func op_d1f9_0_ff;
+extern cpuop_func op_d1fa_0_nf;
+extern cpuop_func op_d1fa_0_ff;
+extern cpuop_func op_d1fb_0_nf;
+extern cpuop_func op_d1fb_0_ff;
+extern cpuop_func op_d1fc_0_nf;
+extern cpuop_func op_d1fc_0_ff;
+extern cpuop_func op_e000_0_nf;
+extern cpuop_func op_e000_0_ff;
+extern cpuop_func op_e008_0_nf;
+extern cpuop_func op_e008_0_ff;
+extern cpuop_func op_e010_0_nf;
+extern cpuop_func op_e010_0_ff;
+extern cpuop_func op_e018_0_nf;
+extern cpuop_func op_e018_0_ff;
+extern cpuop_func op_e020_0_nf;
+extern cpuop_func op_e020_0_ff;
+extern cpuop_func op_e028_0_nf;
+extern cpuop_func op_e028_0_ff;
+extern cpuop_func op_e030_0_nf;
+extern cpuop_func op_e030_0_ff;
+extern cpuop_func op_e038_0_nf;
+extern cpuop_func op_e038_0_ff;
+extern cpuop_func op_e040_0_nf;
+extern cpuop_func op_e040_0_ff;
+extern cpuop_func op_e048_0_nf;
+extern cpuop_func op_e048_0_ff;
+extern cpuop_func op_e050_0_nf;
+extern cpuop_func op_e050_0_ff;
+extern cpuop_func op_e058_0_nf;
+extern cpuop_func op_e058_0_ff;
+extern cpuop_func op_e060_0_nf;
+extern cpuop_func op_e060_0_ff;
+extern cpuop_func op_e068_0_nf;
+extern cpuop_func op_e068_0_ff;
+extern cpuop_func op_e070_0_nf;
+extern cpuop_func op_e070_0_ff;
+extern cpuop_func op_e078_0_nf;
+extern cpuop_func op_e078_0_ff;
+extern cpuop_func op_e080_0_nf;
+extern cpuop_func op_e080_0_ff;
+extern cpuop_func op_e088_0_nf;
+extern cpuop_func op_e088_0_ff;
+extern cpuop_func op_e090_0_nf;
+extern cpuop_func op_e090_0_ff;
+extern cpuop_func op_e098_0_nf;
+extern cpuop_func op_e098_0_ff;
+extern cpuop_func op_e0a0_0_nf;
+extern cpuop_func op_e0a0_0_ff;
+extern cpuop_func op_e0a8_0_nf;
+extern cpuop_func op_e0a8_0_ff;
+extern cpuop_func op_e0b0_0_nf;
+extern cpuop_func op_e0b0_0_ff;
+extern cpuop_func op_e0b8_0_nf;
+extern cpuop_func op_e0b8_0_ff;
+extern cpuop_func op_e0d0_0_nf;
+extern cpuop_func op_e0d0_0_ff;
+extern cpuop_func op_e0d8_0_nf;
+extern cpuop_func op_e0d8_0_ff;
+extern cpuop_func op_e0e0_0_nf;
+extern cpuop_func op_e0e0_0_ff;
+extern cpuop_func op_e0e8_0_nf;
+extern cpuop_func op_e0e8_0_ff;
+extern cpuop_func op_e0f0_0_nf;
+extern cpuop_func op_e0f0_0_ff;
+extern cpuop_func op_e0f8_0_nf;
+extern cpuop_func op_e0f8_0_ff;
+extern cpuop_func op_e0f9_0_nf;
+extern cpuop_func op_e0f9_0_ff;
+extern cpuop_func op_e100_0_nf;
+extern cpuop_func op_e100_0_ff;
+extern cpuop_func op_e108_0_nf;
+extern cpuop_func op_e108_0_ff;
+extern cpuop_func op_e110_0_nf;
+extern cpuop_func op_e110_0_ff;
+extern cpuop_func op_e118_0_nf;
+extern cpuop_func op_e118_0_ff;
+extern cpuop_func op_e120_0_nf;
+extern cpuop_func op_e120_0_ff;
+extern cpuop_func op_e128_0_nf;
+extern cpuop_func op_e128_0_ff;
+extern cpuop_func op_e130_0_nf;
+extern cpuop_func op_e130_0_ff;
+extern cpuop_func op_e138_0_nf;
+extern cpuop_func op_e138_0_ff;
+extern cpuop_func op_e140_0_nf;
+extern cpuop_func op_e140_0_ff;
+extern cpuop_func op_e148_0_nf;
+extern cpuop_func op_e148_0_ff;
+extern cpuop_func op_e150_0_nf;
+extern cpuop_func op_e150_0_ff;
+extern cpuop_func op_e158_0_nf;
+extern cpuop_func op_e158_0_ff;
+extern cpuop_func op_e160_0_nf;
+extern cpuop_func op_e160_0_ff;
+extern cpuop_func op_e168_0_nf;
+extern cpuop_func op_e168_0_ff;
+extern cpuop_func op_e170_0_nf;
+extern cpuop_func op_e170_0_ff;
+extern cpuop_func op_e178_0_nf;
+extern cpuop_func op_e178_0_ff;
+extern cpuop_func op_e180_0_nf;
+extern cpuop_func op_e180_0_ff;
+extern cpuop_func op_e188_0_nf;
+extern cpuop_func op_e188_0_ff;
+extern cpuop_func op_e190_0_nf;
+extern cpuop_func op_e190_0_ff;
+extern cpuop_func op_e198_0_nf;
+extern cpuop_func op_e198_0_ff;
+extern cpuop_func op_e1a0_0_nf;
+extern cpuop_func op_e1a0_0_ff;
+extern cpuop_func op_e1a8_0_nf;
+extern cpuop_func op_e1a8_0_ff;
+extern cpuop_func op_e1b0_0_nf;
+extern cpuop_func op_e1b0_0_ff;
+extern cpuop_func op_e1b8_0_nf;
+extern cpuop_func op_e1b8_0_ff;
+extern cpuop_func op_e1d0_0_nf;
+extern cpuop_func op_e1d0_0_ff;
+extern cpuop_func op_e1d8_0_nf;
+extern cpuop_func op_e1d8_0_ff;
+extern cpuop_func op_e1e0_0_nf;
+extern cpuop_func op_e1e0_0_ff;
+extern cpuop_func op_e1e8_0_nf;
+extern cpuop_func op_e1e8_0_ff;
+extern cpuop_func op_e1f0_0_nf;
+extern cpuop_func op_e1f0_0_ff;
+extern cpuop_func op_e1f8_0_nf;
+extern cpuop_func op_e1f8_0_ff;
+extern cpuop_func op_e1f9_0_nf;
+extern cpuop_func op_e1f9_0_ff;
+extern cpuop_func op_e2d0_0_nf;
+extern cpuop_func op_e2d0_0_ff;
+extern cpuop_func op_e2d8_0_nf;
+extern cpuop_func op_e2d8_0_ff;
+extern cpuop_func op_e2e0_0_nf;
+extern cpuop_func op_e2e0_0_ff;
+extern cpuop_func op_e2e8_0_nf;
+extern cpuop_func op_e2e8_0_ff;
+extern cpuop_func op_e2f0_0_nf;
+extern cpuop_func op_e2f0_0_ff;
+extern cpuop_func op_e2f8_0_nf;
+extern cpuop_func op_e2f8_0_ff;
+extern cpuop_func op_e2f9_0_nf;
+extern cpuop_func op_e2f9_0_ff;
+extern cpuop_func op_e3d0_0_nf;
+extern cpuop_func op_e3d0_0_ff;
+extern cpuop_func op_e3d8_0_nf;
+extern cpuop_func op_e3d8_0_ff;
+extern cpuop_func op_e3e0_0_nf;
+extern cpuop_func op_e3e0_0_ff;
+extern cpuop_func op_e3e8_0_nf;
+extern cpuop_func op_e3e8_0_ff;
+extern cpuop_func op_e3f0_0_nf;
+extern cpuop_func op_e3f0_0_ff;
+extern cpuop_func op_e3f8_0_nf;
+extern cpuop_func op_e3f8_0_ff;
+extern cpuop_func op_e3f9_0_nf;
+extern cpuop_func op_e3f9_0_ff;
+extern cpuop_func op_e4d0_0_nf;
+extern cpuop_func op_e4d0_0_ff;
+extern cpuop_func op_e4d8_0_nf;
+extern cpuop_func op_e4d8_0_ff;
+extern cpuop_func op_e4e0_0_nf;
+extern cpuop_func op_e4e0_0_ff;
+extern cpuop_func op_e4e8_0_nf;
+extern cpuop_func op_e4e8_0_ff;
+extern cpuop_func op_e4f0_0_nf;
+extern cpuop_func op_e4f0_0_ff;
+extern cpuop_func op_e4f8_0_nf;
+extern cpuop_func op_e4f8_0_ff;
+extern cpuop_func op_e4f9_0_nf;
+extern cpuop_func op_e4f9_0_ff;
+extern cpuop_func op_e5d0_0_nf;
+extern cpuop_func op_e5d0_0_ff;
+extern cpuop_func op_e5d8_0_nf;
+extern cpuop_func op_e5d8_0_ff;
+extern cpuop_func op_e5e0_0_nf;
+extern cpuop_func op_e5e0_0_ff;
+extern cpuop_func op_e5e8_0_nf;
+extern cpuop_func op_e5e8_0_ff;
+extern cpuop_func op_e5f0_0_nf;
+extern cpuop_func op_e5f0_0_ff;
+extern cpuop_func op_e5f8_0_nf;
+extern cpuop_func op_e5f8_0_ff;
+extern cpuop_func op_e5f9_0_nf;
+extern cpuop_func op_e5f9_0_ff;
+extern cpuop_func op_e6d0_0_nf;
+extern cpuop_func op_e6d0_0_ff;
+extern cpuop_func op_e6d8_0_nf;
+extern cpuop_func op_e6d8_0_ff;
+extern cpuop_func op_e6e0_0_nf;
+extern cpuop_func op_e6e0_0_ff;
+extern cpuop_func op_e6e8_0_nf;
+extern cpuop_func op_e6e8_0_ff;
+extern cpuop_func op_e6f0_0_nf;
+extern cpuop_func op_e6f0_0_ff;
+extern cpuop_func op_e6f8_0_nf;
+extern cpuop_func op_e6f8_0_ff;
+extern cpuop_func op_e6f9_0_nf;
+extern cpuop_func op_e6f9_0_ff;
+extern cpuop_func op_e7d0_0_nf;
+extern cpuop_func op_e7d0_0_ff;
+extern cpuop_func op_e7d8_0_nf;
+extern cpuop_func op_e7d8_0_ff;
+extern cpuop_func op_e7e0_0_nf;
+extern cpuop_func op_e7e0_0_ff;
+extern cpuop_func op_e7e8_0_nf;
+extern cpuop_func op_e7e8_0_ff;
+extern cpuop_func op_e7f0_0_nf;
+extern cpuop_func op_e7f0_0_ff;
+extern cpuop_func op_e7f8_0_nf;
+extern cpuop_func op_e7f8_0_ff;
+extern cpuop_func op_e7f9_0_nf;
+extern cpuop_func op_e7f9_0_ff;
+extern cpuop_func op_e8c0_0_nf;
+extern cpuop_func op_e8c0_0_ff;
+extern cpuop_func op_e8d0_0_nf;
+extern cpuop_func op_e8d0_0_ff;
+extern cpuop_func op_e8e8_0_nf;
+extern cpuop_func op_e8e8_0_ff;
+extern cpuop_func op_e8f0_0_nf;
+extern cpuop_func op_e8f0_0_ff;
+extern cpuop_func op_e8f8_0_nf;
+extern cpuop_func op_e8f8_0_ff;
+extern cpuop_func op_e8f9_0_nf;
+extern cpuop_func op_e8f9_0_ff;
+extern cpuop_func op_e8fa_0_nf;
+extern cpuop_func op_e8fa_0_ff;
+extern cpuop_func op_e8fb_0_nf;
+extern cpuop_func op_e8fb_0_ff;
+extern cpuop_func op_e9c0_0_nf;
+extern cpuop_func op_e9c0_0_ff;
+extern cpuop_func op_e9d0_0_nf;
+extern cpuop_func op_e9d0_0_ff;
+extern cpuop_func op_e9e8_0_nf;
+extern cpuop_func op_e9e8_0_ff;
+extern cpuop_func op_e9f0_0_nf;
+extern cpuop_func op_e9f0_0_ff;
+extern cpuop_func op_e9f8_0_nf;
+extern cpuop_func op_e9f8_0_ff;
+extern cpuop_func op_e9f9_0_nf;
+extern cpuop_func op_e9f9_0_ff;
+extern cpuop_func op_e9fa_0_nf;
+extern cpuop_func op_e9fa_0_ff;
+extern cpuop_func op_e9fb_0_nf;
+extern cpuop_func op_e9fb_0_ff;
+extern cpuop_func op_eac0_0_nf;
+extern cpuop_func op_eac0_0_ff;
+extern cpuop_func op_ead0_0_nf;
+extern cpuop_func op_ead0_0_ff;
+extern cpuop_func op_eae8_0_nf;
+extern cpuop_func op_eae8_0_ff;
+extern cpuop_func op_eaf0_0_nf;
+extern cpuop_func op_eaf0_0_ff;
+extern cpuop_func op_eaf8_0_nf;
+extern cpuop_func op_eaf8_0_ff;
+extern cpuop_func op_eaf9_0_nf;
+extern cpuop_func op_eaf9_0_ff;
+extern cpuop_func op_ebc0_0_nf;
+extern cpuop_func op_ebc0_0_ff;
+extern cpuop_func op_ebd0_0_nf;
+extern cpuop_func op_ebd0_0_ff;
+extern cpuop_func op_ebe8_0_nf;
+extern cpuop_func op_ebe8_0_ff;
+extern cpuop_func op_ebf0_0_nf;
+extern cpuop_func op_ebf0_0_ff;
+extern cpuop_func op_ebf8_0_nf;
+extern cpuop_func op_ebf8_0_ff;
+extern cpuop_func op_ebf9_0_nf;
+extern cpuop_func op_ebf9_0_ff;
+extern cpuop_func op_ebfa_0_nf;
+extern cpuop_func op_ebfa_0_ff;
+extern cpuop_func op_ebfb_0_nf;
+extern cpuop_func op_ebfb_0_ff;
+extern cpuop_func op_ecc0_0_nf;
+extern cpuop_func op_ecc0_0_ff;
+extern cpuop_func op_ecd0_0_nf;
+extern cpuop_func op_ecd0_0_ff;
+extern cpuop_func op_ece8_0_nf;
+extern cpuop_func op_ece8_0_ff;
+extern cpuop_func op_ecf0_0_nf;
+extern cpuop_func op_ecf0_0_ff;
+extern cpuop_func op_ecf8_0_nf;
+extern cpuop_func op_ecf8_0_ff;
+extern cpuop_func op_ecf9_0_nf;
+extern cpuop_func op_ecf9_0_ff;
+extern cpuop_func op_edc0_0_nf;
+extern cpuop_func op_edc0_0_ff;
+extern cpuop_func op_edd0_0_nf;
+extern cpuop_func op_edd0_0_ff;
+extern cpuop_func op_ede8_0_nf;
+extern cpuop_func op_ede8_0_ff;
+extern cpuop_func op_edf0_0_nf;
+extern cpuop_func op_edf0_0_ff;
+extern cpuop_func op_edf8_0_nf;
+extern cpuop_func op_edf8_0_ff;
+extern cpuop_func op_edf9_0_nf;
+extern cpuop_func op_edf9_0_ff;
+extern cpuop_func op_edfa_0_nf;
+extern cpuop_func op_edfa_0_ff;
+extern cpuop_func op_edfb_0_nf;
+extern cpuop_func op_edfb_0_ff;
+extern cpuop_func op_eec0_0_nf;
+extern cpuop_func op_eec0_0_ff;
+extern cpuop_func op_eed0_0_nf;
+extern cpuop_func op_eed0_0_ff;
+extern cpuop_func op_eee8_0_nf;
+extern cpuop_func op_eee8_0_ff;
+extern cpuop_func op_eef0_0_nf;
+extern cpuop_func op_eef0_0_ff;
+extern cpuop_func op_eef8_0_nf;
+extern cpuop_func op_eef8_0_ff;
+extern cpuop_func op_eef9_0_nf;
+extern cpuop_func op_eef9_0_ff;
+extern cpuop_func op_efc0_0_nf;
+extern cpuop_func op_efc0_0_ff;
+extern cpuop_func op_efd0_0_nf;
+extern cpuop_func op_efd0_0_ff;
+extern cpuop_func op_efe8_0_nf;
+extern cpuop_func op_efe8_0_ff;
+extern cpuop_func op_eff0_0_nf;
+extern cpuop_func op_eff0_0_ff;
+extern cpuop_func op_eff8_0_nf;
+extern cpuop_func op_eff8_0_ff;
+extern cpuop_func op_eff9_0_nf;
+extern cpuop_func op_eff9_0_ff;
+extern cpuop_func op_f000_0_nf;
+extern cpuop_func op_f000_0_ff;
+extern cpuop_func op_f008_0_nf;
+extern cpuop_func op_f008_0_ff;
+extern cpuop_func op_f010_0_nf;
+extern cpuop_func op_f010_0_ff;
+extern cpuop_func op_f018_0_nf;
+extern cpuop_func op_f018_0_ff;
+extern cpuop_func op_f020_0_nf;
+extern cpuop_func op_f020_0_ff;
+extern cpuop_func op_f028_0_nf;
+extern cpuop_func op_f028_0_ff;
+extern cpuop_func op_f030_0_nf;
+extern cpuop_func op_f030_0_ff;
+extern cpuop_func op_f038_0_nf;
+extern cpuop_func op_f038_0_ff;
+extern cpuop_func op_f039_0_nf;
+extern cpuop_func op_f039_0_ff;
+extern cpuop_func op_f200_0_nf;
+extern cpuop_func op_f200_0_ff;
+extern cpuop_func op_f208_0_nf;
+extern cpuop_func op_f208_0_ff;
+extern cpuop_func op_f210_0_nf;
+extern cpuop_func op_f210_0_ff;
+extern cpuop_func op_f218_0_nf;
+extern cpuop_func op_f218_0_ff;
+extern cpuop_func op_f220_0_nf;
+extern cpuop_func op_f220_0_ff;
+extern cpuop_func op_f228_0_nf;
+extern cpuop_func op_f228_0_ff;
+extern cpuop_func op_f230_0_nf;
+extern cpuop_func op_f230_0_ff;
+extern cpuop_func op_f238_0_nf;
+extern cpuop_func op_f238_0_ff;
+extern cpuop_func op_f239_0_nf;
+extern cpuop_func op_f239_0_ff;
+extern cpuop_func op_f23a_0_nf;
+extern cpuop_func op_f23a_0_ff;
+extern cpuop_func op_f23b_0_nf;
+extern cpuop_func op_f23b_0_ff;
+extern cpuop_func op_f23c_0_nf;
+extern cpuop_func op_f23c_0_ff;
+extern cpuop_func op_f240_0_nf;
+extern cpuop_func op_f240_0_ff;
+extern cpuop_func op_f248_0_nf;
+extern cpuop_func op_f248_0_ff;
+extern cpuop_func op_f250_0_nf;
+extern cpuop_func op_f250_0_ff;
+extern cpuop_func op_f258_0_nf;
+extern cpuop_func op_f258_0_ff;
+extern cpuop_func op_f260_0_nf;
+extern cpuop_func op_f260_0_ff;
+extern cpuop_func op_f268_0_nf;
+extern cpuop_func op_f268_0_ff;
+extern cpuop_func op_f270_0_nf;
+extern cpuop_func op_f270_0_ff;
+extern cpuop_func op_f278_0_nf;
+extern cpuop_func op_f278_0_ff;
+extern cpuop_func op_f279_0_nf;
+extern cpuop_func op_f279_0_ff;
+extern cpuop_func op_f27a_0_nf;
+extern cpuop_func op_f27a_0_ff;
+extern cpuop_func op_f27b_0_nf;
+extern cpuop_func op_f27b_0_ff;
+extern cpuop_func op_f27c_0_nf;
+extern cpuop_func op_f27c_0_ff;
+extern cpuop_func op_f280_0_nf;
+extern cpuop_func op_f280_0_ff;
+extern cpuop_func op_f2c0_0_nf;
+extern cpuop_func op_f2c0_0_ff;
+extern cpuop_func op_f310_0_nf;
+extern cpuop_func op_f310_0_ff;
+extern cpuop_func op_f320_0_nf;
+extern cpuop_func op_f320_0_ff;
+extern cpuop_func op_f328_0_nf;
+extern cpuop_func op_f328_0_ff;
+extern cpuop_func op_f330_0_nf;
+extern cpuop_func op_f330_0_ff;
+extern cpuop_func op_f338_0_nf;
+extern cpuop_func op_f338_0_ff;
+extern cpuop_func op_f339_0_nf;
+extern cpuop_func op_f339_0_ff;
+extern cpuop_func op_f350_0_nf;
+extern cpuop_func op_f350_0_ff;
+extern cpuop_func op_f358_0_nf;
+extern cpuop_func op_f358_0_ff;
+extern cpuop_func op_f368_0_nf;
+extern cpuop_func op_f368_0_ff;
+extern cpuop_func op_f370_0_nf;
+extern cpuop_func op_f370_0_ff;
+extern cpuop_func op_f378_0_nf;
+extern cpuop_func op_f378_0_ff;
+extern cpuop_func op_f379_0_nf;
+extern cpuop_func op_f379_0_ff;
+extern cpuop_func op_f37a_0_nf;
+extern cpuop_func op_f37a_0_ff;
+extern cpuop_func op_f37b_0_nf;
+extern cpuop_func op_f37b_0_ff;
+extern cpuop_func op_f408_0_nf;
+extern cpuop_func op_f408_0_ff;
+extern cpuop_func op_f410_0_nf;
+extern cpuop_func op_f410_0_ff;
+extern cpuop_func op_f418_0_nf;
+extern cpuop_func op_f418_0_ff;
+extern cpuop_func op_f419_0_nf;
+extern cpuop_func op_f419_0_ff;
+extern cpuop_func op_f41a_0_nf;
+extern cpuop_func op_f41a_0_ff;
+extern cpuop_func op_f41b_0_nf;
+extern cpuop_func op_f41b_0_ff;
+extern cpuop_func op_f41c_0_nf;
+extern cpuop_func op_f41c_0_ff;
+extern cpuop_func op_f41d_0_nf;
+extern cpuop_func op_f41d_0_ff;
+extern cpuop_func op_f41e_0_nf;
+extern cpuop_func op_f41e_0_ff;
+extern cpuop_func op_f41f_0_nf;
+extern cpuop_func op_f41f_0_ff;
+extern cpuop_func op_f428_0_nf;
+extern cpuop_func op_f428_0_ff;
+extern cpuop_func op_f430_0_nf;
+extern cpuop_func op_f430_0_ff;
+extern cpuop_func op_f438_0_nf;
+extern cpuop_func op_f438_0_ff;
+extern cpuop_func op_f439_0_nf;
+extern cpuop_func op_f439_0_ff;
+extern cpuop_func op_f43a_0_nf;
+extern cpuop_func op_f43a_0_ff;
+extern cpuop_func op_f43b_0_nf;
+extern cpuop_func op_f43b_0_ff;
+extern cpuop_func op_f43c_0_nf;
+extern cpuop_func op_f43c_0_ff;
+extern cpuop_func op_f43d_0_nf;
+extern cpuop_func op_f43d_0_ff;
+extern cpuop_func op_f43e_0_nf;
+extern cpuop_func op_f43e_0_ff;
+extern cpuop_func op_f43f_0_nf;
+extern cpuop_func op_f43f_0_ff;
+extern cpuop_func op_f500_0_nf;
+extern cpuop_func op_f500_0_ff;
+extern cpuop_func op_f508_0_nf;
+extern cpuop_func op_f508_0_ff;
+extern cpuop_func op_f510_0_nf;
+extern cpuop_func op_f510_0_ff;
+extern cpuop_func op_f518_0_nf;
+extern cpuop_func op_f518_0_ff;
+extern cpuop_func op_f548_0_nf;
+extern cpuop_func op_f548_0_ff;
+extern cpuop_func op_f568_0_nf;
+extern cpuop_func op_f568_0_ff;
+extern cpuop_func op_f588_0_nf;
+extern cpuop_func op_f588_0_ff;
+extern cpuop_func op_f5c8_0_nf;
+extern cpuop_func op_f5c8_0_ff;
+extern cpuop_func op_f600_0_nf;
+extern cpuop_func op_f600_0_ff;
+extern cpuop_func op_f608_0_nf;
+extern cpuop_func op_f608_0_ff;
+extern cpuop_func op_f610_0_nf;
+extern cpuop_func op_f610_0_ff;
+extern cpuop_func op_f618_0_nf;
+extern cpuop_func op_f618_0_ff;
+extern cpuop_func op_f620_0_nf;
+extern cpuop_func op_f620_0_ff;
+extern cpuop_func op_f800_0_nf;
+extern cpuop_func op_f800_0_ff;
+extern cpuop_func op_4800_2_nf;
+extern cpuop_func op_4800_2_ff;
+extern cpuop_func op_4810_2_nf;
+extern cpuop_func op_4810_2_ff;
+extern cpuop_func op_4818_2_nf;
+extern cpuop_func op_4818_2_ff;
+extern cpuop_func op_4820_2_nf;
+extern cpuop_func op_4820_2_ff;
+extern cpuop_func op_4828_2_nf;
+extern cpuop_func op_4828_2_ff;
+extern cpuop_func op_4830_2_nf;
+extern cpuop_func op_4830_2_ff;
+extern cpuop_func op_4838_2_nf;
+extern cpuop_func op_4838_2_ff;
+extern cpuop_func op_4839_2_nf;
+extern cpuop_func op_4839_2_ff;
+extern cpuop_func op_8100_2_nf;
+extern cpuop_func op_8100_2_ff;
+extern cpuop_func op_8108_2_nf;
+extern cpuop_func op_8108_2_ff;
+extern cpuop_func op_c100_2_nf;
+extern cpuop_func op_c100_2_ff;
+extern cpuop_func op_c108_2_nf;
+extern cpuop_func op_c108_2_ff;
+extern cpuop_func op_0030_4_nf;
+extern cpuop_func op_0030_4_ff;
+extern cpuop_func op_0070_4_nf;
+extern cpuop_func op_0070_4_ff;
+extern cpuop_func op_00b0_4_nf;
+extern cpuop_func op_00b0_4_ff;
+extern cpuop_func op_0130_4_nf;
+extern cpuop_func op_0130_4_ff;
+extern cpuop_func op_013b_4_nf;
+extern cpuop_func op_013b_4_ff;
+extern cpuop_func op_0170_4_nf;
+extern cpuop_func op_0170_4_ff;
+extern cpuop_func op_01b0_4_nf;
+extern cpuop_func op_01b0_4_ff;
+extern cpuop_func op_01f0_4_nf;
+extern cpuop_func op_01f0_4_ff;
+extern cpuop_func op_0230_4_nf;
+extern cpuop_func op_0230_4_ff;
+extern cpuop_func op_0270_4_nf;
+extern cpuop_func op_0270_4_ff;
+extern cpuop_func op_02b0_4_nf;
+extern cpuop_func op_02b0_4_ff;
+extern cpuop_func op_0430_4_nf;
+extern cpuop_func op_0430_4_ff;
+extern cpuop_func op_0470_4_nf;
+extern cpuop_func op_0470_4_ff;
+extern cpuop_func op_04b0_4_nf;
+extern cpuop_func op_04b0_4_ff;
+extern cpuop_func op_0630_4_nf;
+extern cpuop_func op_0630_4_ff;
+extern cpuop_func op_0670_4_nf;
+extern cpuop_func op_0670_4_ff;
+extern cpuop_func op_06b0_4_nf;
+extern cpuop_func op_06b0_4_ff;
+extern cpuop_func op_0830_4_nf;
+extern cpuop_func op_0830_4_ff;
+extern cpuop_func op_083b_4_nf;
+extern cpuop_func op_083b_4_ff;
+extern cpuop_func op_0870_4_nf;
+extern cpuop_func op_0870_4_ff;
+extern cpuop_func op_08b0_4_nf;
+extern cpuop_func op_08b0_4_ff;
+extern cpuop_func op_08f0_4_nf;
+extern cpuop_func op_08f0_4_ff;
+extern cpuop_func op_0a30_4_nf;
+extern cpuop_func op_0a30_4_ff;
+extern cpuop_func op_0a70_4_nf;
+extern cpuop_func op_0a70_4_ff;
+extern cpuop_func op_0ab0_4_nf;
+extern cpuop_func op_0ab0_4_ff;
+extern cpuop_func op_0c30_4_nf;
+extern cpuop_func op_0c30_4_ff;
+extern cpuop_func op_0c70_4_nf;
+extern cpuop_func op_0c70_4_ff;
+extern cpuop_func op_0cb0_4_nf;
+extern cpuop_func op_0cb0_4_ff;
+extern cpuop_func op_1030_4_nf;
+extern cpuop_func op_1030_4_ff;
+extern cpuop_func op_103b_4_nf;
+extern cpuop_func op_103b_4_ff;
+extern cpuop_func op_10b0_4_nf;
+extern cpuop_func op_10b0_4_ff;
+extern cpuop_func op_10bb_4_nf;
+extern cpuop_func op_10bb_4_ff;
+extern cpuop_func op_10f0_4_nf;
+extern cpuop_func op_10f0_4_ff;
+extern cpuop_func op_10fb_4_nf;
+extern cpuop_func op_10fb_4_ff;
+extern cpuop_func op_1130_4_nf;
+extern cpuop_func op_1130_4_ff;
+extern cpuop_func op_113b_4_nf;
+extern cpuop_func op_113b_4_ff;
+extern cpuop_func op_1170_4_nf;
+extern cpuop_func op_1170_4_ff;
+extern cpuop_func op_117b_4_nf;
+extern cpuop_func op_117b_4_ff;
+extern cpuop_func op_1180_4_nf;
+extern cpuop_func op_1180_4_ff;
+extern cpuop_func op_1190_4_nf;
+extern cpuop_func op_1190_4_ff;
+extern cpuop_func op_1198_4_nf;
+extern cpuop_func op_1198_4_ff;
+extern cpuop_func op_11a0_4_nf;
+extern cpuop_func op_11a0_4_ff;
+extern cpuop_func op_11a8_4_nf;
+extern cpuop_func op_11a8_4_ff;
+extern cpuop_func op_11b0_4_nf;
+extern cpuop_func op_11b0_4_ff;
+extern cpuop_func op_11b8_4_nf;
+extern cpuop_func op_11b8_4_ff;
+extern cpuop_func op_11b9_4_nf;
+extern cpuop_func op_11b9_4_ff;
+extern cpuop_func op_11ba_4_nf;
+extern cpuop_func op_11ba_4_ff;
+extern cpuop_func op_11bb_4_nf;
+extern cpuop_func op_11bb_4_ff;
+extern cpuop_func op_11bc_4_nf;
+extern cpuop_func op_11bc_4_ff;
+extern cpuop_func op_11f0_4_nf;
+extern cpuop_func op_11f0_4_ff;
+extern cpuop_func op_11fb_4_nf;
+extern cpuop_func op_11fb_4_ff;
+extern cpuop_func op_13f0_4_nf;
+extern cpuop_func op_13f0_4_ff;
+extern cpuop_func op_13fb_4_nf;
+extern cpuop_func op_13fb_4_ff;
+extern cpuop_func op_2030_4_nf;
+extern cpuop_func op_2030_4_ff;
+extern cpuop_func op_203b_4_nf;
+extern cpuop_func op_203b_4_ff;
+extern cpuop_func op_2070_4_nf;
+extern cpuop_func op_2070_4_ff;
+extern cpuop_func op_207b_4_nf;
+extern cpuop_func op_207b_4_ff;
+extern cpuop_func op_20b0_4_nf;
+extern cpuop_func op_20b0_4_ff;
+extern cpuop_func op_20bb_4_nf;
+extern cpuop_func op_20bb_4_ff;
+extern cpuop_func op_20f0_4_nf;
+extern cpuop_func op_20f0_4_ff;
+extern cpuop_func op_20fb_4_nf;
+extern cpuop_func op_20fb_4_ff;
+extern cpuop_func op_2130_4_nf;
+extern cpuop_func op_2130_4_ff;
+extern cpuop_func op_213b_4_nf;
+extern cpuop_func op_213b_4_ff;
+extern cpuop_func op_2170_4_nf;
+extern cpuop_func op_2170_4_ff;
+extern cpuop_func op_217b_4_nf;
+extern cpuop_func op_217b_4_ff;
+extern cpuop_func op_2180_4_nf;
+extern cpuop_func op_2180_4_ff;
+extern cpuop_func op_2188_4_nf;
+extern cpuop_func op_2188_4_ff;
+extern cpuop_func op_2190_4_nf;
+extern cpuop_func op_2190_4_ff;
+extern cpuop_func op_2198_4_nf;
+extern cpuop_func op_2198_4_ff;
+extern cpuop_func op_21a0_4_nf;
+extern cpuop_func op_21a0_4_ff;
+extern cpuop_func op_21a8_4_nf;
+extern cpuop_func op_21a8_4_ff;
+extern cpuop_func op_21b0_4_nf;
+extern cpuop_func op_21b0_4_ff;
+extern cpuop_func op_21b8_4_nf;
+extern cpuop_func op_21b8_4_ff;
+extern cpuop_func op_21b9_4_nf;
+extern cpuop_func op_21b9_4_ff;
+extern cpuop_func op_21ba_4_nf;
+extern cpuop_func op_21ba_4_ff;
+extern cpuop_func op_21bb_4_nf;
+extern cpuop_func op_21bb_4_ff;
+extern cpuop_func op_21bc_4_nf;
+extern cpuop_func op_21bc_4_ff;
+extern cpuop_func op_21f0_4_nf;
+extern cpuop_func op_21f0_4_ff;
+extern cpuop_func op_21fb_4_nf;
+extern cpuop_func op_21fb_4_ff;
+extern cpuop_func op_23f0_4_nf;
+extern cpuop_func op_23f0_4_ff;
+extern cpuop_func op_23fb_4_nf;
+extern cpuop_func op_23fb_4_ff;
+extern cpuop_func op_3030_4_nf;
+extern cpuop_func op_3030_4_ff;
+extern cpuop_func op_303b_4_nf;
+extern cpuop_func op_303b_4_ff;
+extern cpuop_func op_3070_4_nf;
+extern cpuop_func op_3070_4_ff;
+extern cpuop_func op_307b_4_nf;
+extern cpuop_func op_307b_4_ff;
+extern cpuop_func op_30b0_4_nf;
+extern cpuop_func op_30b0_4_ff;
+extern cpuop_func op_30bb_4_nf;
+extern cpuop_func op_30bb_4_ff;
+extern cpuop_func op_30f0_4_nf;
+extern cpuop_func op_30f0_4_ff;
+extern cpuop_func op_30fb_4_nf;
+extern cpuop_func op_30fb_4_ff;
+extern cpuop_func op_3130_4_nf;
+extern cpuop_func op_3130_4_ff;
+extern cpuop_func op_313b_4_nf;
+extern cpuop_func op_313b_4_ff;
+extern cpuop_func op_3170_4_nf;
+extern cpuop_func op_3170_4_ff;
+extern cpuop_func op_317b_4_nf;
+extern cpuop_func op_317b_4_ff;
+extern cpuop_func op_3180_4_nf;
+extern cpuop_func op_3180_4_ff;
+extern cpuop_func op_3188_4_nf;
+extern cpuop_func op_3188_4_ff;
+extern cpuop_func op_3190_4_nf;
+extern cpuop_func op_3190_4_ff;
+extern cpuop_func op_3198_4_nf;
+extern cpuop_func op_3198_4_ff;
+extern cpuop_func op_31a0_4_nf;
+extern cpuop_func op_31a0_4_ff;
+extern cpuop_func op_31a8_4_nf;
+extern cpuop_func op_31a8_4_ff;
+extern cpuop_func op_31b0_4_nf;
+extern cpuop_func op_31b0_4_ff;
+extern cpuop_func op_31b8_4_nf;
+extern cpuop_func op_31b8_4_ff;
+extern cpuop_func op_31b9_4_nf;
+extern cpuop_func op_31b9_4_ff;
+extern cpuop_func op_31ba_4_nf;
+extern cpuop_func op_31ba_4_ff;
+extern cpuop_func op_31bb_4_nf;
+extern cpuop_func op_31bb_4_ff;
+extern cpuop_func op_31bc_4_nf;
+extern cpuop_func op_31bc_4_ff;
+extern cpuop_func op_31f0_4_nf;
+extern cpuop_func op_31f0_4_ff;
+extern cpuop_func op_31fb_4_nf;
+extern cpuop_func op_31fb_4_ff;
+extern cpuop_func op_33f0_4_nf;
+extern cpuop_func op_33f0_4_ff;
+extern cpuop_func op_33fb_4_nf;
+extern cpuop_func op_33fb_4_ff;
+extern cpuop_func op_4030_4_nf;
+extern cpuop_func op_4030_4_ff;
+extern cpuop_func op_4070_4_nf;
+extern cpuop_func op_4070_4_ff;
+extern cpuop_func op_40b0_4_nf;
+extern cpuop_func op_40b0_4_ff;
+extern cpuop_func op_40f0_4_nf;
+extern cpuop_func op_40f0_4_ff;
+extern cpuop_func op_41b0_4_nf;
+extern cpuop_func op_41b0_4_ff;
+extern cpuop_func op_41bb_4_nf;
+extern cpuop_func op_41bb_4_ff;
+extern cpuop_func op_41f0_4_nf;
+extern cpuop_func op_41f0_4_ff;
+extern cpuop_func op_41fb_4_nf;
+extern cpuop_func op_41fb_4_ff;
+extern cpuop_func op_4230_4_nf;
+extern cpuop_func op_4230_4_ff;
+extern cpuop_func op_4270_4_nf;
+extern cpuop_func op_4270_4_ff;
+extern cpuop_func op_42b0_4_nf;
+extern cpuop_func op_42b0_4_ff;
+extern cpuop_func op_42f0_4_nf;
+extern cpuop_func op_42f0_4_ff;
+extern cpuop_func op_4430_4_nf;
+extern cpuop_func op_4430_4_ff;
+extern cpuop_func op_4470_4_nf;
+extern cpuop_func op_4470_4_ff;
+extern cpuop_func op_44b0_4_nf;
+extern cpuop_func op_44b0_4_ff;
+extern cpuop_func op_44f0_4_nf;
+extern cpuop_func op_44f0_4_ff;
+extern cpuop_func op_44fb_4_nf;
+extern cpuop_func op_44fb_4_ff;
+extern cpuop_func op_4630_4_nf;
+extern cpuop_func op_4630_4_ff;
+extern cpuop_func op_4670_4_nf;
+extern cpuop_func op_4670_4_ff;
+extern cpuop_func op_46b0_4_nf;
+extern cpuop_func op_46b0_4_ff;
+extern cpuop_func op_46f0_4_nf;
+extern cpuop_func op_46f0_4_ff;
+extern cpuop_func op_46fb_4_nf;
+extern cpuop_func op_46fb_4_ff;
+extern cpuop_func op_4830_4_nf;
+extern cpuop_func op_4830_4_ff;
+extern cpuop_func op_4870_4_nf;
+extern cpuop_func op_4870_4_ff;
+extern cpuop_func op_487b_4_nf;
+extern cpuop_func op_487b_4_ff;
+extern cpuop_func op_48b0_4_nf;
+extern cpuop_func op_48b0_4_ff;
+extern cpuop_func op_48f0_4_nf;
+extern cpuop_func op_48f0_4_ff;
+extern cpuop_func op_4a30_4_nf;
+extern cpuop_func op_4a30_4_ff;
+extern cpuop_func op_4a70_4_nf;
+extern cpuop_func op_4a70_4_ff;
+extern cpuop_func op_4ab0_4_nf;
+extern cpuop_func op_4ab0_4_ff;
+extern cpuop_func op_4ac0_4_nf;
+extern cpuop_func op_4ac0_4_ff;
+extern cpuop_func op_4ad0_4_nf;
+extern cpuop_func op_4ad0_4_ff;
+extern cpuop_func op_4ad8_4_nf;
+extern cpuop_func op_4ad8_4_ff;
+extern cpuop_func op_4ae0_4_nf;
+extern cpuop_func op_4ae0_4_ff;
+extern cpuop_func op_4ae8_4_nf;
+extern cpuop_func op_4ae8_4_ff;
+extern cpuop_func op_4af0_4_nf;
+extern cpuop_func op_4af0_4_ff;
+extern cpuop_func op_4af8_4_nf;
+extern cpuop_func op_4af8_4_ff;
+extern cpuop_func op_4af9_4_nf;
+extern cpuop_func op_4af9_4_ff;
+extern cpuop_func op_4cb0_4_nf;
+extern cpuop_func op_4cb0_4_ff;
+extern cpuop_func op_4cbb_4_nf;
+extern cpuop_func op_4cbb_4_ff;
+extern cpuop_func op_4cf0_4_nf;
+extern cpuop_func op_4cf0_4_ff;
+extern cpuop_func op_4cfb_4_nf;
+extern cpuop_func op_4cfb_4_ff;
+extern cpuop_func op_4eb0_4_nf;
+extern cpuop_func op_4eb0_4_ff;
+extern cpuop_func op_4ebb_4_nf;
+extern cpuop_func op_4ebb_4_ff;
+extern cpuop_func op_4ef0_4_nf;
+extern cpuop_func op_4ef0_4_ff;
+extern cpuop_func op_4efb_4_nf;
+extern cpuop_func op_4efb_4_ff;
+extern cpuop_func op_5030_4_nf;
+extern cpuop_func op_5030_4_ff;
+extern cpuop_func op_5070_4_nf;
+extern cpuop_func op_5070_4_ff;
+extern cpuop_func op_50b0_4_nf;
+extern cpuop_func op_50b0_4_ff;
+extern cpuop_func op_50f0_4_nf;
+extern cpuop_func op_50f0_4_ff;
+extern cpuop_func op_5130_4_nf;
+extern cpuop_func op_5130_4_ff;
+extern cpuop_func op_5170_4_nf;
+extern cpuop_func op_5170_4_ff;
+extern cpuop_func op_51b0_4_nf;
+extern cpuop_func op_51b0_4_ff;
+extern cpuop_func op_51f0_4_nf;
+extern cpuop_func op_51f0_4_ff;
+extern cpuop_func op_52f0_4_nf;
+extern cpuop_func op_52f0_4_ff;
+extern cpuop_func op_53f0_4_nf;
+extern cpuop_func op_53f0_4_ff;
+extern cpuop_func op_54f0_4_nf;
+extern cpuop_func op_54f0_4_ff;
+extern cpuop_func op_55f0_4_nf;
+extern cpuop_func op_55f0_4_ff;
+extern cpuop_func op_56f0_4_nf;
+extern cpuop_func op_56f0_4_ff;
+extern cpuop_func op_57f0_4_nf;
+extern cpuop_func op_57f0_4_ff;
+extern cpuop_func op_58f0_4_nf;
+extern cpuop_func op_58f0_4_ff;
+extern cpuop_func op_59f0_4_nf;
+extern cpuop_func op_59f0_4_ff;
+extern cpuop_func op_5af0_4_nf;
+extern cpuop_func op_5af0_4_ff;
+extern cpuop_func op_5bf0_4_nf;
+extern cpuop_func op_5bf0_4_ff;
+extern cpuop_func op_5cf0_4_nf;
+extern cpuop_func op_5cf0_4_ff;
+extern cpuop_func op_5df0_4_nf;
+extern cpuop_func op_5df0_4_ff;
+extern cpuop_func op_5ef0_4_nf;
+extern cpuop_func op_5ef0_4_ff;
+extern cpuop_func op_5ff0_4_nf;
+extern cpuop_func op_5ff0_4_ff;
+extern cpuop_func op_60ff_4_nf;
+extern cpuop_func op_60ff_4_ff;
+extern cpuop_func op_61ff_4_nf;
+extern cpuop_func op_61ff_4_ff;
+extern cpuop_func op_62ff_4_nf;
+extern cpuop_func op_62ff_4_ff;
+extern cpuop_func op_63ff_4_nf;
+extern cpuop_func op_63ff_4_ff;
+extern cpuop_func op_64ff_4_nf;
+extern cpuop_func op_64ff_4_ff;
+extern cpuop_func op_65ff_4_nf;
+extern cpuop_func op_65ff_4_ff;
+extern cpuop_func op_66ff_4_nf;
+extern cpuop_func op_66ff_4_ff;
+extern cpuop_func op_67ff_4_nf;
+extern cpuop_func op_67ff_4_ff;
+extern cpuop_func op_68ff_4_nf;
+extern cpuop_func op_68ff_4_ff;
+extern cpuop_func op_69ff_4_nf;
+extern cpuop_func op_69ff_4_ff;
+extern cpuop_func op_6aff_4_nf;
+extern cpuop_func op_6aff_4_ff;
+extern cpuop_func op_6bff_4_nf;
+extern cpuop_func op_6bff_4_ff;
+extern cpuop_func op_6cff_4_nf;
+extern cpuop_func op_6cff_4_ff;
+extern cpuop_func op_6dff_4_nf;
+extern cpuop_func op_6dff_4_ff;
+extern cpuop_func op_6eff_4_nf;
+extern cpuop_func op_6eff_4_ff;
+extern cpuop_func op_6fff_4_nf;
+extern cpuop_func op_6fff_4_ff;
+extern cpuop_func op_8030_4_nf;
+extern cpuop_func op_8030_4_ff;
+extern cpuop_func op_803b_4_nf;
+extern cpuop_func op_803b_4_ff;
+extern cpuop_func op_8070_4_nf;
+extern cpuop_func op_8070_4_ff;
+extern cpuop_func op_807b_4_nf;
+extern cpuop_func op_807b_4_ff;
+extern cpuop_func op_80b0_4_nf;
+extern cpuop_func op_80b0_4_ff;
+extern cpuop_func op_80bb_4_nf;
+extern cpuop_func op_80bb_4_ff;
+extern cpuop_func op_80f0_4_nf;
+extern cpuop_func op_80f0_4_ff;
+extern cpuop_func op_80fb_4_nf;
+extern cpuop_func op_80fb_4_ff;
+extern cpuop_func op_8130_4_nf;
+extern cpuop_func op_8130_4_ff;
+extern cpuop_func op_8170_4_nf;
+extern cpuop_func op_8170_4_ff;
+extern cpuop_func op_81b0_4_nf;
+extern cpuop_func op_81b0_4_ff;
+extern cpuop_func op_81f0_4_nf;
+extern cpuop_func op_81f0_4_ff;
+extern cpuop_func op_81fb_4_nf;
+extern cpuop_func op_81fb_4_ff;
+extern cpuop_func op_9030_4_nf;
+extern cpuop_func op_9030_4_ff;
+extern cpuop_func op_903b_4_nf;
+extern cpuop_func op_903b_4_ff;
+extern cpuop_func op_9070_4_nf;
+extern cpuop_func op_9070_4_ff;
+extern cpuop_func op_907b_4_nf;
+extern cpuop_func op_907b_4_ff;
+extern cpuop_func op_90b0_4_nf;
+extern cpuop_func op_90b0_4_ff;
+extern cpuop_func op_90bb_4_nf;
+extern cpuop_func op_90bb_4_ff;
+extern cpuop_func op_90f0_4_nf;
+extern cpuop_func op_90f0_4_ff;
+extern cpuop_func op_90fb_4_nf;
+extern cpuop_func op_90fb_4_ff;
+extern cpuop_func op_9130_4_nf;
+extern cpuop_func op_9130_4_ff;
+extern cpuop_func op_9170_4_nf;
+extern cpuop_func op_9170_4_ff;
+extern cpuop_func op_91b0_4_nf;
+extern cpuop_func op_91b0_4_ff;
+extern cpuop_func op_91f0_4_nf;
+extern cpuop_func op_91f0_4_ff;
+extern cpuop_func op_91fb_4_nf;
+extern cpuop_func op_91fb_4_ff;
+extern cpuop_func op_b030_4_nf;
+extern cpuop_func op_b030_4_ff;
+extern cpuop_func op_b03b_4_nf;
+extern cpuop_func op_b03b_4_ff;
+extern cpuop_func op_b070_4_nf;
+extern cpuop_func op_b070_4_ff;
+extern cpuop_func op_b07b_4_nf;
+extern cpuop_func op_b07b_4_ff;
+extern cpuop_func op_b0b0_4_nf;
+extern cpuop_func op_b0b0_4_ff;
+extern cpuop_func op_b0bb_4_nf;
+extern cpuop_func op_b0bb_4_ff;
+extern cpuop_func op_b0f0_4_nf;
+extern cpuop_func op_b0f0_4_ff;
+extern cpuop_func op_b0fb_4_nf;
+extern cpuop_func op_b0fb_4_ff;
+extern cpuop_func op_b130_4_nf;
+extern cpuop_func op_b130_4_ff;
+extern cpuop_func op_b170_4_nf;
+extern cpuop_func op_b170_4_ff;
+extern cpuop_func op_b1b0_4_nf;
+extern cpuop_func op_b1b0_4_ff;
+extern cpuop_func op_b1f0_4_nf;
+extern cpuop_func op_b1f0_4_ff;
+extern cpuop_func op_b1fb_4_nf;
+extern cpuop_func op_b1fb_4_ff;
+extern cpuop_func op_c030_4_nf;
+extern cpuop_func op_c030_4_ff;
+extern cpuop_func op_c03b_4_nf;
+extern cpuop_func op_c03b_4_ff;
+extern cpuop_func op_c070_4_nf;
+extern cpuop_func op_c070_4_ff;
+extern cpuop_func op_c07b_4_nf;
+extern cpuop_func op_c07b_4_ff;
+extern cpuop_func op_c0b0_4_nf;
+extern cpuop_func op_c0b0_4_ff;
+extern cpuop_func op_c0bb_4_nf;
+extern cpuop_func op_c0bb_4_ff;
+extern cpuop_func op_c0f0_4_nf;
+extern cpuop_func op_c0f0_4_ff;
+extern cpuop_func op_c0fb_4_nf;
+extern cpuop_func op_c0fb_4_ff;
+extern cpuop_func op_c130_4_nf;
+extern cpuop_func op_c130_4_ff;
+extern cpuop_func op_c170_4_nf;
+extern cpuop_func op_c170_4_ff;
+extern cpuop_func op_c1b0_4_nf;
+extern cpuop_func op_c1b0_4_ff;
+extern cpuop_func op_c1f0_4_nf;
+extern cpuop_func op_c1f0_4_ff;
+extern cpuop_func op_c1fb_4_nf;
+extern cpuop_func op_c1fb_4_ff;
+extern cpuop_func op_d030_4_nf;
+extern cpuop_func op_d030_4_ff;
+extern cpuop_func op_d03b_4_nf;
+extern cpuop_func op_d03b_4_ff;
+extern cpuop_func op_d070_4_nf;
+extern cpuop_func op_d070_4_ff;
+extern cpuop_func op_d07b_4_nf;
+extern cpuop_func op_d07b_4_ff;
+extern cpuop_func op_d0b0_4_nf;
+extern cpuop_func op_d0b0_4_ff;
+extern cpuop_func op_d0bb_4_nf;
+extern cpuop_func op_d0bb_4_ff;
+extern cpuop_func op_d0f0_4_nf;
+extern cpuop_func op_d0f0_4_ff;
+extern cpuop_func op_d0fb_4_nf;
+extern cpuop_func op_d0fb_4_ff;
+extern cpuop_func op_d130_4_nf;
+extern cpuop_func op_d130_4_ff;
+extern cpuop_func op_d170_4_nf;
+extern cpuop_func op_d170_4_ff;
+extern cpuop_func op_d1b0_4_nf;
+extern cpuop_func op_d1b0_4_ff;
+extern cpuop_func op_d1f0_4_nf;
+extern cpuop_func op_d1f0_4_ff;
+extern cpuop_func op_d1fb_4_nf;
+extern cpuop_func op_d1fb_4_ff;
+extern cpuop_func op_e0f0_4_nf;
+extern cpuop_func op_e0f0_4_ff;
+extern cpuop_func op_e1f0_4_nf;
+extern cpuop_func op_e1f0_4_ff;
+extern cpuop_func op_e2f0_4_nf;
+extern cpuop_func op_e2f0_4_ff;
+extern cpuop_func op_e3f0_4_nf;
+extern cpuop_func op_e3f0_4_ff;
+extern cpuop_func op_e4f0_4_nf;
+extern cpuop_func op_e4f0_4_ff;
+extern cpuop_func op_e5f0_4_nf;
+extern cpuop_func op_e5f0_4_ff;
+extern cpuop_func op_e6f0_4_nf;
+extern cpuop_func op_e6f0_4_ff;
+extern cpuop_func op_e7f0_4_nf;
+extern cpuop_func op_e7f0_4_ff;
+extern cpuop_func op_40c0_5_nf;
+extern cpuop_func op_40c0_5_ff;
+extern cpuop_func op_40d0_5_nf;
+extern cpuop_func op_40d0_5_ff;
+extern cpuop_func op_40d8_5_nf;
+extern cpuop_func op_40d8_5_ff;
+extern cpuop_func op_40e0_5_nf;
+extern cpuop_func op_40e0_5_ff;
+extern cpuop_func op_40e8_5_nf;
+extern cpuop_func op_40e8_5_ff;
+extern cpuop_func op_40f0_5_nf;
+extern cpuop_func op_40f0_5_ff;
+extern cpuop_func op_40f8_5_nf;
+extern cpuop_func op_40f8_5_ff;
+extern cpuop_func op_40f9_5_nf;
+extern cpuop_func op_40f9_5_ff;
+extern cpuop_func op_4200_5_nf;
+extern cpuop_func op_4200_5_ff;
+extern cpuop_func op_4210_5_nf;
+extern cpuop_func op_4210_5_ff;
+extern cpuop_func op_4218_5_nf;
+extern cpuop_func op_4218_5_ff;
+extern cpuop_func op_4220_5_nf;
+extern cpuop_func op_4220_5_ff;
+extern cpuop_func op_4228_5_nf;
+extern cpuop_func op_4228_5_ff;
+extern cpuop_func op_4230_5_nf;
+extern cpuop_func op_4230_5_ff;
+extern cpuop_func op_4238_5_nf;
+extern cpuop_func op_4238_5_ff;
+extern cpuop_func op_4239_5_nf;
+extern cpuop_func op_4239_5_ff;
+extern cpuop_func op_4240_5_nf;
+extern cpuop_func op_4240_5_ff;
+extern cpuop_func op_4250_5_nf;
+extern cpuop_func op_4250_5_ff;
+extern cpuop_func op_4258_5_nf;
+extern cpuop_func op_4258_5_ff;
+extern cpuop_func op_4260_5_nf;
+extern cpuop_func op_4260_5_ff;
+extern cpuop_func op_4268_5_nf;
+extern cpuop_func op_4268_5_ff;
+extern cpuop_func op_4270_5_nf;
+extern cpuop_func op_4270_5_ff;
+extern cpuop_func op_4278_5_nf;
+extern cpuop_func op_4278_5_ff;
+extern cpuop_func op_4279_5_nf;
+extern cpuop_func op_4279_5_ff;
+extern cpuop_func op_4280_5_nf;
+extern cpuop_func op_4280_5_ff;
+extern cpuop_func op_4290_5_nf;
+extern cpuop_func op_4290_5_ff;
+extern cpuop_func op_4298_5_nf;
+extern cpuop_func op_4298_5_ff;
+extern cpuop_func op_42a0_5_nf;
+extern cpuop_func op_42a0_5_ff;
+extern cpuop_func op_42a8_5_nf;
+extern cpuop_func op_42a8_5_ff;
+extern cpuop_func op_42b0_5_nf;
+extern cpuop_func op_42b0_5_ff;
+extern cpuop_func op_42b8_5_nf;
+extern cpuop_func op_42b8_5_ff;
+extern cpuop_func op_42b9_5_nf;
+extern cpuop_func op_42b9_5_ff;
+extern cpuop_func op_4e73_5_nf;
+extern cpuop_func op_4e73_5_ff;
+extern cpuop_func op_50c0_5_nf;
+extern cpuop_func op_50c0_5_ff;
+extern cpuop_func op_50d0_5_nf;
+extern cpuop_func op_50d0_5_ff;
+extern cpuop_func op_50d8_5_nf;
+extern cpuop_func op_50d8_5_ff;
+extern cpuop_func op_50e0_5_nf;
+extern cpuop_func op_50e0_5_ff;
+extern cpuop_func op_50e8_5_nf;
+extern cpuop_func op_50e8_5_ff;
+extern cpuop_func op_50f0_5_nf;
+extern cpuop_func op_50f0_5_ff;
+extern cpuop_func op_50f8_5_nf;
+extern cpuop_func op_50f8_5_ff;
+extern cpuop_func op_50f9_5_nf;
+extern cpuop_func op_50f9_5_ff;
+extern cpuop_func op_51c0_5_nf;
+extern cpuop_func op_51c0_5_ff;
+extern cpuop_func op_51d0_5_nf;
+extern cpuop_func op_51d0_5_ff;
+extern cpuop_func op_51d8_5_nf;
+extern cpuop_func op_51d8_5_ff;
+extern cpuop_func op_51e0_5_nf;
+extern cpuop_func op_51e0_5_ff;
+extern cpuop_func op_51e8_5_nf;
+extern cpuop_func op_51e8_5_ff;
+extern cpuop_func op_51f0_5_nf;
+extern cpuop_func op_51f0_5_ff;
+extern cpuop_func op_51f8_5_nf;
+extern cpuop_func op_51f8_5_ff;
+extern cpuop_func op_51f9_5_nf;
+extern cpuop_func op_51f9_5_ff;
+extern cpuop_func op_52c0_5_nf;
+extern cpuop_func op_52c0_5_ff;
+extern cpuop_func op_52d0_5_nf;
+extern cpuop_func op_52d0_5_ff;
+extern cpuop_func op_52d8_5_nf;
+extern cpuop_func op_52d8_5_ff;
+extern cpuop_func op_52e0_5_nf;
+extern cpuop_func op_52e0_5_ff;
+extern cpuop_func op_52e8_5_nf;
+extern cpuop_func op_52e8_5_ff;
+extern cpuop_func op_52f0_5_nf;
+extern cpuop_func op_52f0_5_ff;
+extern cpuop_func op_52f8_5_nf;
+extern cpuop_func op_52f8_5_ff;
+extern cpuop_func op_52f9_5_nf;
+extern cpuop_func op_52f9_5_ff;
+extern cpuop_func op_53c0_5_nf;
+extern cpuop_func op_53c0_5_ff;
+extern cpuop_func op_53d0_5_nf;
+extern cpuop_func op_53d0_5_ff;
+extern cpuop_func op_53d8_5_nf;
+extern cpuop_func op_53d8_5_ff;
+extern cpuop_func op_53e0_5_nf;
+extern cpuop_func op_53e0_5_ff;
+extern cpuop_func op_53e8_5_nf;
+extern cpuop_func op_53e8_5_ff;
+extern cpuop_func op_53f0_5_nf;
+extern cpuop_func op_53f0_5_ff;
+extern cpuop_func op_53f8_5_nf;
+extern cpuop_func op_53f8_5_ff;
+extern cpuop_func op_53f9_5_nf;
+extern cpuop_func op_53f9_5_ff;
+extern cpuop_func op_54c0_5_nf;
+extern cpuop_func op_54c0_5_ff;
+extern cpuop_func op_54d0_5_nf;
+extern cpuop_func op_54d0_5_ff;
+extern cpuop_func op_54d8_5_nf;
+extern cpuop_func op_54d8_5_ff;
+extern cpuop_func op_54e0_5_nf;
+extern cpuop_func op_54e0_5_ff;
+extern cpuop_func op_54e8_5_nf;
+extern cpuop_func op_54e8_5_ff;
+extern cpuop_func op_54f0_5_nf;
+extern cpuop_func op_54f0_5_ff;
+extern cpuop_func op_54f8_5_nf;
+extern cpuop_func op_54f8_5_ff;
+extern cpuop_func op_54f9_5_nf;
+extern cpuop_func op_54f9_5_ff;
+extern cpuop_func op_55c0_5_nf;
+extern cpuop_func op_55c0_5_ff;
+extern cpuop_func op_55d0_5_nf;
+extern cpuop_func op_55d0_5_ff;
+extern cpuop_func op_55d8_5_nf;
+extern cpuop_func op_55d8_5_ff;
+extern cpuop_func op_55e0_5_nf;
+extern cpuop_func op_55e0_5_ff;
+extern cpuop_func op_55e8_5_nf;
+extern cpuop_func op_55e8_5_ff;
+extern cpuop_func op_55f0_5_nf;
+extern cpuop_func op_55f0_5_ff;
+extern cpuop_func op_55f8_5_nf;
+extern cpuop_func op_55f8_5_ff;
+extern cpuop_func op_55f9_5_nf;
+extern cpuop_func op_55f9_5_ff;
+extern cpuop_func op_56c0_5_nf;
+extern cpuop_func op_56c0_5_ff;
+extern cpuop_func op_56d0_5_nf;
+extern cpuop_func op_56d0_5_ff;
+extern cpuop_func op_56d8_5_nf;
+extern cpuop_func op_56d8_5_ff;
+extern cpuop_func op_56e0_5_nf;
+extern cpuop_func op_56e0_5_ff;
+extern cpuop_func op_56e8_5_nf;
+extern cpuop_func op_56e8_5_ff;
+extern cpuop_func op_56f0_5_nf;
+extern cpuop_func op_56f0_5_ff;
+extern cpuop_func op_56f8_5_nf;
+extern cpuop_func op_56f8_5_ff;
+extern cpuop_func op_56f9_5_nf;
+extern cpuop_func op_56f9_5_ff;
+extern cpuop_func op_57c0_5_nf;
+extern cpuop_func op_57c0_5_ff;
+extern cpuop_func op_57d0_5_nf;
+extern cpuop_func op_57d0_5_ff;
+extern cpuop_func op_57d8_5_nf;
+extern cpuop_func op_57d8_5_ff;
+extern cpuop_func op_57e0_5_nf;
+extern cpuop_func op_57e0_5_ff;
+extern cpuop_func op_57e8_5_nf;
+extern cpuop_func op_57e8_5_ff;
+extern cpuop_func op_57f0_5_nf;
+extern cpuop_func op_57f0_5_ff;
+extern cpuop_func op_57f8_5_nf;
+extern cpuop_func op_57f8_5_ff;
+extern cpuop_func op_57f9_5_nf;
+extern cpuop_func op_57f9_5_ff;
+extern cpuop_func op_58c0_5_nf;
+extern cpuop_func op_58c0_5_ff;
+extern cpuop_func op_58d0_5_nf;
+extern cpuop_func op_58d0_5_ff;
+extern cpuop_func op_58d8_5_nf;
+extern cpuop_func op_58d8_5_ff;
+extern cpuop_func op_58e0_5_nf;
+extern cpuop_func op_58e0_5_ff;
+extern cpuop_func op_58e8_5_nf;
+extern cpuop_func op_58e8_5_ff;
+extern cpuop_func op_58f0_5_nf;
+extern cpuop_func op_58f0_5_ff;
+extern cpuop_func op_58f8_5_nf;
+extern cpuop_func op_58f8_5_ff;
+extern cpuop_func op_58f9_5_nf;
+extern cpuop_func op_58f9_5_ff;
+extern cpuop_func op_59c0_5_nf;
+extern cpuop_func op_59c0_5_ff;
+extern cpuop_func op_59d0_5_nf;
+extern cpuop_func op_59d0_5_ff;
+extern cpuop_func op_59d8_5_nf;
+extern cpuop_func op_59d8_5_ff;
+extern cpuop_func op_59e0_5_nf;
+extern cpuop_func op_59e0_5_ff;
+extern cpuop_func op_59e8_5_nf;
+extern cpuop_func op_59e8_5_ff;
+extern cpuop_func op_59f0_5_nf;
+extern cpuop_func op_59f0_5_ff;
+extern cpuop_func op_59f8_5_nf;
+extern cpuop_func op_59f8_5_ff;
+extern cpuop_func op_59f9_5_nf;
+extern cpuop_func op_59f9_5_ff;
+extern cpuop_func op_5ac0_5_nf;
+extern cpuop_func op_5ac0_5_ff;
+extern cpuop_func op_5ad0_5_nf;
+extern cpuop_func op_5ad0_5_ff;
+extern cpuop_func op_5ad8_5_nf;
+extern cpuop_func op_5ad8_5_ff;
+extern cpuop_func op_5ae0_5_nf;
+extern cpuop_func op_5ae0_5_ff;
+extern cpuop_func op_5ae8_5_nf;
+extern cpuop_func op_5ae8_5_ff;
+extern cpuop_func op_5af0_5_nf;
+extern cpuop_func op_5af0_5_ff;
+extern cpuop_func op_5af8_5_nf;
+extern cpuop_func op_5af8_5_ff;
+extern cpuop_func op_5af9_5_nf;
+extern cpuop_func op_5af9_5_ff;
+extern cpuop_func op_5bc0_5_nf;
+extern cpuop_func op_5bc0_5_ff;
+extern cpuop_func op_5bd0_5_nf;
+extern cpuop_func op_5bd0_5_ff;
+extern cpuop_func op_5bd8_5_nf;
+extern cpuop_func op_5bd8_5_ff;
+extern cpuop_func op_5be0_5_nf;
+extern cpuop_func op_5be0_5_ff;
+extern cpuop_func op_5be8_5_nf;
+extern cpuop_func op_5be8_5_ff;
+extern cpuop_func op_5bf0_5_nf;
+extern cpuop_func op_5bf0_5_ff;
+extern cpuop_func op_5bf8_5_nf;
+extern cpuop_func op_5bf8_5_ff;
+extern cpuop_func op_5bf9_5_nf;
+extern cpuop_func op_5bf9_5_ff;
+extern cpuop_func op_5cc0_5_nf;
+extern cpuop_func op_5cc0_5_ff;
+extern cpuop_func op_5cd0_5_nf;
+extern cpuop_func op_5cd0_5_ff;
+extern cpuop_func op_5cd8_5_nf;
+extern cpuop_func op_5cd8_5_ff;
+extern cpuop_func op_5ce0_5_nf;
+extern cpuop_func op_5ce0_5_ff;
+extern cpuop_func op_5ce8_5_nf;
+extern cpuop_func op_5ce8_5_ff;
+extern cpuop_func op_5cf0_5_nf;
+extern cpuop_func op_5cf0_5_ff;
+extern cpuop_func op_5cf8_5_nf;
+extern cpuop_func op_5cf8_5_ff;
+extern cpuop_func op_5cf9_5_nf;
+extern cpuop_func op_5cf9_5_ff;
+extern cpuop_func op_5dc0_5_nf;
+extern cpuop_func op_5dc0_5_ff;
+extern cpuop_func op_5dd0_5_nf;
+extern cpuop_func op_5dd0_5_ff;
+extern cpuop_func op_5dd8_5_nf;
+extern cpuop_func op_5dd8_5_ff;
+extern cpuop_func op_5de0_5_nf;
+extern cpuop_func op_5de0_5_ff;
+extern cpuop_func op_5de8_5_nf;
+extern cpuop_func op_5de8_5_ff;
+extern cpuop_func op_5df0_5_nf;
+extern cpuop_func op_5df0_5_ff;
+extern cpuop_func op_5df8_5_nf;
+extern cpuop_func op_5df8_5_ff;
+extern cpuop_func op_5df9_5_nf;
+extern cpuop_func op_5df9_5_ff;
+extern cpuop_func op_5ec0_5_nf;
+extern cpuop_func op_5ec0_5_ff;
+extern cpuop_func op_5ed0_5_nf;
+extern cpuop_func op_5ed0_5_ff;
+extern cpuop_func op_5ed8_5_nf;
+extern cpuop_func op_5ed8_5_ff;
+extern cpuop_func op_5ee0_5_nf;
+extern cpuop_func op_5ee0_5_ff;
+extern cpuop_func op_5ee8_5_nf;
+extern cpuop_func op_5ee8_5_ff;
+extern cpuop_func op_5ef0_5_nf;
+extern cpuop_func op_5ef0_5_ff;
+extern cpuop_func op_5ef8_5_nf;
+extern cpuop_func op_5ef8_5_ff;
+extern cpuop_func op_5ef9_5_nf;
+extern cpuop_func op_5ef9_5_ff;
+extern cpuop_func op_5fc0_5_nf;
+extern cpuop_func op_5fc0_5_ff;
+extern cpuop_func op_5fd0_5_nf;
+extern cpuop_func op_5fd0_5_ff;
+extern cpuop_func op_5fd8_5_nf;
+extern cpuop_func op_5fd8_5_ff;
+extern cpuop_func op_5fe0_5_nf;
+extern cpuop_func op_5fe0_5_ff;
+extern cpuop_func op_5fe8_5_nf;
+extern cpuop_func op_5fe8_5_ff;
+extern cpuop_func op_5ff0_5_nf;
+extern cpuop_func op_5ff0_5_ff;
+extern cpuop_func op_5ff8_5_nf;
+extern cpuop_func op_5ff8_5_ff;
+extern cpuop_func op_5ff9_5_nf;
+extern cpuop_func op_5ff9_5_ff;
+extern cpuop_func op_0000_11_nf;
+extern cpuop_func op_0000_11_ff;
+extern cpuop_func op_0010_11_nf;
+extern cpuop_func op_0010_11_ff;
+extern cpuop_func op_0018_11_nf;
+extern cpuop_func op_0018_11_ff;
+extern cpuop_func op_0020_11_nf;
+extern cpuop_func op_0020_11_ff;
+extern cpuop_func op_0028_11_nf;
+extern cpuop_func op_0028_11_ff;
+extern cpuop_func op_0030_11_nf;
+extern cpuop_func op_0030_11_ff;
+extern cpuop_func op_0038_11_nf;
+extern cpuop_func op_0038_11_ff;
+extern cpuop_func op_0039_11_nf;
+extern cpuop_func op_0039_11_ff;
+extern cpuop_func op_003c_11_nf;
+extern cpuop_func op_003c_11_ff;
+extern cpuop_func op_0040_11_nf;
+extern cpuop_func op_0040_11_ff;
+extern cpuop_func op_0050_11_nf;
+extern cpuop_func op_0050_11_ff;
+extern cpuop_func op_0058_11_nf;
+extern cpuop_func op_0058_11_ff;
+extern cpuop_func op_0060_11_nf;
+extern cpuop_func op_0060_11_ff;
+extern cpuop_func op_0068_11_nf;
+extern cpuop_func op_0068_11_ff;
+extern cpuop_func op_0070_11_nf;
+extern cpuop_func op_0070_11_ff;
+extern cpuop_func op_0078_11_nf;
+extern cpuop_func op_0078_11_ff;
+extern cpuop_func op_0079_11_nf;
+extern cpuop_func op_0079_11_ff;
+extern cpuop_func op_007c_11_nf;
+extern cpuop_func op_007c_11_ff;
+extern cpuop_func op_0080_11_nf;
+extern cpuop_func op_0080_11_ff;
+extern cpuop_func op_0090_11_nf;
+extern cpuop_func op_0090_11_ff;
+extern cpuop_func op_0098_11_nf;
+extern cpuop_func op_0098_11_ff;
+extern cpuop_func op_00a0_11_nf;
+extern cpuop_func op_00a0_11_ff;
+extern cpuop_func op_00a8_11_nf;
+extern cpuop_func op_00a8_11_ff;
+extern cpuop_func op_00b0_11_nf;
+extern cpuop_func op_00b0_11_ff;
+extern cpuop_func op_00b8_11_nf;
+extern cpuop_func op_00b8_11_ff;
+extern cpuop_func op_00b9_11_nf;
+extern cpuop_func op_00b9_11_ff;
+extern cpuop_func op_0100_11_nf;
+extern cpuop_func op_0100_11_ff;
+extern cpuop_func op_0108_11_nf;
+extern cpuop_func op_0108_11_ff;
+extern cpuop_func op_0110_11_nf;
+extern cpuop_func op_0110_11_ff;
+extern cpuop_func op_0118_11_nf;
+extern cpuop_func op_0118_11_ff;
+extern cpuop_func op_0120_11_nf;
+extern cpuop_func op_0120_11_ff;
+extern cpuop_func op_0128_11_nf;
+extern cpuop_func op_0128_11_ff;
+extern cpuop_func op_0130_11_nf;
+extern cpuop_func op_0130_11_ff;
+extern cpuop_func op_0138_11_nf;
+extern cpuop_func op_0138_11_ff;
+extern cpuop_func op_0139_11_nf;
+extern cpuop_func op_0139_11_ff;
+extern cpuop_func op_013a_11_nf;
+extern cpuop_func op_013a_11_ff;
+extern cpuop_func op_013b_11_nf;
+extern cpuop_func op_013b_11_ff;
+extern cpuop_func op_013c_11_nf;
+extern cpuop_func op_013c_11_ff;
+extern cpuop_func op_0140_11_nf;
+extern cpuop_func op_0140_11_ff;
+extern cpuop_func op_0148_11_nf;
+extern cpuop_func op_0148_11_ff;
+extern cpuop_func op_0150_11_nf;
+extern cpuop_func op_0150_11_ff;
+extern cpuop_func op_0158_11_nf;
+extern cpuop_func op_0158_11_ff;
+extern cpuop_func op_0160_11_nf;
+extern cpuop_func op_0160_11_ff;
+extern cpuop_func op_0168_11_nf;
+extern cpuop_func op_0168_11_ff;
+extern cpuop_func op_0170_11_nf;
+extern cpuop_func op_0170_11_ff;
+extern cpuop_func op_0178_11_nf;
+extern cpuop_func op_0178_11_ff;
+extern cpuop_func op_0179_11_nf;
+extern cpuop_func op_0179_11_ff;
+extern cpuop_func op_0180_11_nf;
+extern cpuop_func op_0180_11_ff;
+extern cpuop_func op_0188_11_nf;
+extern cpuop_func op_0188_11_ff;
+extern cpuop_func op_0190_11_nf;
+extern cpuop_func op_0190_11_ff;
+extern cpuop_func op_0198_11_nf;
+extern cpuop_func op_0198_11_ff;
+extern cpuop_func op_01a0_11_nf;
+extern cpuop_func op_01a0_11_ff;
+extern cpuop_func op_01a8_11_nf;
+extern cpuop_func op_01a8_11_ff;
+extern cpuop_func op_01b0_11_nf;
+extern cpuop_func op_01b0_11_ff;
+extern cpuop_func op_01b8_11_nf;
+extern cpuop_func op_01b8_11_ff;
+extern cpuop_func op_01b9_11_nf;
+extern cpuop_func op_01b9_11_ff;
+extern cpuop_func op_01c0_11_nf;
+extern cpuop_func op_01c0_11_ff;
+extern cpuop_func op_01c8_11_nf;
+extern cpuop_func op_01c8_11_ff;
+extern cpuop_func op_01d0_11_nf;
+extern cpuop_func op_01d0_11_ff;
+extern cpuop_func op_01d8_11_nf;
+extern cpuop_func op_01d8_11_ff;
+extern cpuop_func op_01e0_11_nf;
+extern cpuop_func op_01e0_11_ff;
+extern cpuop_func op_01e8_11_nf;
+extern cpuop_func op_01e8_11_ff;
+extern cpuop_func op_01f0_11_nf;
+extern cpuop_func op_01f0_11_ff;
+extern cpuop_func op_01f8_11_nf;
+extern cpuop_func op_01f8_11_ff;
+extern cpuop_func op_01f9_11_nf;
+extern cpuop_func op_01f9_11_ff;
+extern cpuop_func op_0200_11_nf;
+extern cpuop_func op_0200_11_ff;
+extern cpuop_func op_0210_11_nf;
+extern cpuop_func op_0210_11_ff;
+extern cpuop_func op_0218_11_nf;
+extern cpuop_func op_0218_11_ff;
+extern cpuop_func op_0220_11_nf;
+extern cpuop_func op_0220_11_ff;
+extern cpuop_func op_0228_11_nf;
+extern cpuop_func op_0228_11_ff;
+extern cpuop_func op_0230_11_nf;
+extern cpuop_func op_0230_11_ff;
+extern cpuop_func op_0238_11_nf;
+extern cpuop_func op_0238_11_ff;
+extern cpuop_func op_0239_11_nf;
+extern cpuop_func op_0239_11_ff;
+extern cpuop_func op_023c_11_nf;
+extern cpuop_func op_023c_11_ff;
+extern cpuop_func op_0240_11_nf;
+extern cpuop_func op_0240_11_ff;
+extern cpuop_func op_0250_11_nf;
+extern cpuop_func op_0250_11_ff;
+extern cpuop_func op_0258_11_nf;
+extern cpuop_func op_0258_11_ff;
+extern cpuop_func op_0260_11_nf;
+extern cpuop_func op_0260_11_ff;
+extern cpuop_func op_0268_11_nf;
+extern cpuop_func op_0268_11_ff;
+extern cpuop_func op_0270_11_nf;
+extern cpuop_func op_0270_11_ff;
+extern cpuop_func op_0278_11_nf;
+extern cpuop_func op_0278_11_ff;
+extern cpuop_func op_0279_11_nf;
+extern cpuop_func op_0279_11_ff;
+extern cpuop_func op_027c_11_nf;
+extern cpuop_func op_027c_11_ff;
+extern cpuop_func op_0280_11_nf;
+extern cpuop_func op_0280_11_ff;
+extern cpuop_func op_0290_11_nf;
+extern cpuop_func op_0290_11_ff;
+extern cpuop_func op_0298_11_nf;
+extern cpuop_func op_0298_11_ff;
+extern cpuop_func op_02a0_11_nf;
+extern cpuop_func op_02a0_11_ff;
+extern cpuop_func op_02a8_11_nf;
+extern cpuop_func op_02a8_11_ff;
+extern cpuop_func op_02b0_11_nf;
+extern cpuop_func op_02b0_11_ff;
+extern cpuop_func op_02b8_11_nf;
+extern cpuop_func op_02b8_11_ff;
+extern cpuop_func op_02b9_11_nf;
+extern cpuop_func op_02b9_11_ff;
+extern cpuop_func op_0400_11_nf;
+extern cpuop_func op_0400_11_ff;
+extern cpuop_func op_0410_11_nf;
+extern cpuop_func op_0410_11_ff;
+extern cpuop_func op_0418_11_nf;
+extern cpuop_func op_0418_11_ff;
+extern cpuop_func op_0420_11_nf;
+extern cpuop_func op_0420_11_ff;
+extern cpuop_func op_0428_11_nf;
+extern cpuop_func op_0428_11_ff;
+extern cpuop_func op_0430_11_nf;
+extern cpuop_func op_0430_11_ff;
+extern cpuop_func op_0438_11_nf;
+extern cpuop_func op_0438_11_ff;
+extern cpuop_func op_0439_11_nf;
+extern cpuop_func op_0439_11_ff;
+extern cpuop_func op_0440_11_nf;
+extern cpuop_func op_0440_11_ff;
+extern cpuop_func op_0450_11_nf;
+extern cpuop_func op_0450_11_ff;
+extern cpuop_func op_0458_11_nf;
+extern cpuop_func op_0458_11_ff;
+extern cpuop_func op_0460_11_nf;
+extern cpuop_func op_0460_11_ff;
+extern cpuop_func op_0468_11_nf;
+extern cpuop_func op_0468_11_ff;
+extern cpuop_func op_0470_11_nf;
+extern cpuop_func op_0470_11_ff;
+extern cpuop_func op_0478_11_nf;
+extern cpuop_func op_0478_11_ff;
+extern cpuop_func op_0479_11_nf;
+extern cpuop_func op_0479_11_ff;
+extern cpuop_func op_0480_11_nf;
+extern cpuop_func op_0480_11_ff;
+extern cpuop_func op_0490_11_nf;
+extern cpuop_func op_0490_11_ff;
+extern cpuop_func op_0498_11_nf;
+extern cpuop_func op_0498_11_ff;
+extern cpuop_func op_04a0_11_nf;
+extern cpuop_func op_04a0_11_ff;
+extern cpuop_func op_04a8_11_nf;
+extern cpuop_func op_04a8_11_ff;
+extern cpuop_func op_04b0_11_nf;
+extern cpuop_func op_04b0_11_ff;
+extern cpuop_func op_04b8_11_nf;
+extern cpuop_func op_04b8_11_ff;
+extern cpuop_func op_04b9_11_nf;
+extern cpuop_func op_04b9_11_ff;
+extern cpuop_func op_0600_11_nf;
+extern cpuop_func op_0600_11_ff;
+extern cpuop_func op_0610_11_nf;
+extern cpuop_func op_0610_11_ff;
+extern cpuop_func op_0618_11_nf;
+extern cpuop_func op_0618_11_ff;
+extern cpuop_func op_0620_11_nf;
+extern cpuop_func op_0620_11_ff;
+extern cpuop_func op_0628_11_nf;
+extern cpuop_func op_0628_11_ff;
+extern cpuop_func op_0630_11_nf;
+extern cpuop_func op_0630_11_ff;
+extern cpuop_func op_0638_11_nf;
+extern cpuop_func op_0638_11_ff;
+extern cpuop_func op_0639_11_nf;
+extern cpuop_func op_0639_11_ff;
+extern cpuop_func op_0640_11_nf;
+extern cpuop_func op_0640_11_ff;
+extern cpuop_func op_0650_11_nf;
+extern cpuop_func op_0650_11_ff;
+extern cpuop_func op_0658_11_nf;
+extern cpuop_func op_0658_11_ff;
+extern cpuop_func op_0660_11_nf;
+extern cpuop_func op_0660_11_ff;
+extern cpuop_func op_0668_11_nf;
+extern cpuop_func op_0668_11_ff;
+extern cpuop_func op_0670_11_nf;
+extern cpuop_func op_0670_11_ff;
+extern cpuop_func op_0678_11_nf;
+extern cpuop_func op_0678_11_ff;
+extern cpuop_func op_0679_11_nf;
+extern cpuop_func op_0679_11_ff;
+extern cpuop_func op_0680_11_nf;
+extern cpuop_func op_0680_11_ff;
+extern cpuop_func op_0690_11_nf;
+extern cpuop_func op_0690_11_ff;
+extern cpuop_func op_0698_11_nf;
+extern cpuop_func op_0698_11_ff;
+extern cpuop_func op_06a0_11_nf;
+extern cpuop_func op_06a0_11_ff;
+extern cpuop_func op_06a8_11_nf;
+extern cpuop_func op_06a8_11_ff;
+extern cpuop_func op_06b0_11_nf;
+extern cpuop_func op_06b0_11_ff;
+extern cpuop_func op_06b8_11_nf;
+extern cpuop_func op_06b8_11_ff;
+extern cpuop_func op_06b9_11_nf;
+extern cpuop_func op_06b9_11_ff;
+extern cpuop_func op_0800_11_nf;
+extern cpuop_func op_0800_11_ff;
+extern cpuop_func op_0810_11_nf;
+extern cpuop_func op_0810_11_ff;
+extern cpuop_func op_0818_11_nf;
+extern cpuop_func op_0818_11_ff;
+extern cpuop_func op_0820_11_nf;
+extern cpuop_func op_0820_11_ff;
+extern cpuop_func op_0828_11_nf;
+extern cpuop_func op_0828_11_ff;
+extern cpuop_func op_0830_11_nf;
+extern cpuop_func op_0830_11_ff;
+extern cpuop_func op_0838_11_nf;
+extern cpuop_func op_0838_11_ff;
+extern cpuop_func op_0839_11_nf;
+extern cpuop_func op_0839_11_ff;
+extern cpuop_func op_083a_11_nf;
+extern cpuop_func op_083a_11_ff;
+extern cpuop_func op_083b_11_nf;
+extern cpuop_func op_083b_11_ff;
+extern cpuop_func op_0840_11_nf;
+extern cpuop_func op_0840_11_ff;
+extern cpuop_func op_0850_11_nf;
+extern cpuop_func op_0850_11_ff;
+extern cpuop_func op_0858_11_nf;
+extern cpuop_func op_0858_11_ff;
+extern cpuop_func op_0860_11_nf;
+extern cpuop_func op_0860_11_ff;
+extern cpuop_func op_0868_11_nf;
+extern cpuop_func op_0868_11_ff;
+extern cpuop_func op_0870_11_nf;
+extern cpuop_func op_0870_11_ff;
+extern cpuop_func op_0878_11_nf;
+extern cpuop_func op_0878_11_ff;
+extern cpuop_func op_0879_11_nf;
+extern cpuop_func op_0879_11_ff;
+extern cpuop_func op_0880_11_nf;
+extern cpuop_func op_0880_11_ff;
+extern cpuop_func op_0890_11_nf;
+extern cpuop_func op_0890_11_ff;
+extern cpuop_func op_0898_11_nf;
+extern cpuop_func op_0898_11_ff;
+extern cpuop_func op_08a0_11_nf;
+extern cpuop_func op_08a0_11_ff;
+extern cpuop_func op_08a8_11_nf;
+extern cpuop_func op_08a8_11_ff;
+extern cpuop_func op_08b0_11_nf;
+extern cpuop_func op_08b0_11_ff;
+extern cpuop_func op_08b8_11_nf;
+extern cpuop_func op_08b8_11_ff;
+extern cpuop_func op_08b9_11_nf;
+extern cpuop_func op_08b9_11_ff;
+extern cpuop_func op_08c0_11_nf;
+extern cpuop_func op_08c0_11_ff;
+extern cpuop_func op_08d0_11_nf;
+extern cpuop_func op_08d0_11_ff;
+extern cpuop_func op_08d8_11_nf;
+extern cpuop_func op_08d8_11_ff;
+extern cpuop_func op_08e0_11_nf;
+extern cpuop_func op_08e0_11_ff;
+extern cpuop_func op_08e8_11_nf;
+extern cpuop_func op_08e8_11_ff;
+extern cpuop_func op_08f0_11_nf;
+extern cpuop_func op_08f0_11_ff;
+extern cpuop_func op_08f8_11_nf;
+extern cpuop_func op_08f8_11_ff;
+extern cpuop_func op_08f9_11_nf;
+extern cpuop_func op_08f9_11_ff;
+extern cpuop_func op_0a00_11_nf;
+extern cpuop_func op_0a00_11_ff;
+extern cpuop_func op_0a10_11_nf;
+extern cpuop_func op_0a10_11_ff;
+extern cpuop_func op_0a18_11_nf;
+extern cpuop_func op_0a18_11_ff;
+extern cpuop_func op_0a20_11_nf;
+extern cpuop_func op_0a20_11_ff;
+extern cpuop_func op_0a28_11_nf;
+extern cpuop_func op_0a28_11_ff;
+extern cpuop_func op_0a30_11_nf;
+extern cpuop_func op_0a30_11_ff;
+extern cpuop_func op_0a38_11_nf;
+extern cpuop_func op_0a38_11_ff;
+extern cpuop_func op_0a39_11_nf;
+extern cpuop_func op_0a39_11_ff;
+extern cpuop_func op_0a3c_11_nf;
+extern cpuop_func op_0a3c_11_ff;
+extern cpuop_func op_0a40_11_nf;
+extern cpuop_func op_0a40_11_ff;
+extern cpuop_func op_0a50_11_nf;
+extern cpuop_func op_0a50_11_ff;
+extern cpuop_func op_0a58_11_nf;
+extern cpuop_func op_0a58_11_ff;
+extern cpuop_func op_0a60_11_nf;
+extern cpuop_func op_0a60_11_ff;
+extern cpuop_func op_0a68_11_nf;
+extern cpuop_func op_0a68_11_ff;
+extern cpuop_func op_0a70_11_nf;
+extern cpuop_func op_0a70_11_ff;
+extern cpuop_func op_0a78_11_nf;
+extern cpuop_func op_0a78_11_ff;
+extern cpuop_func op_0a79_11_nf;
+extern cpuop_func op_0a79_11_ff;
+extern cpuop_func op_0a7c_11_nf;
+extern cpuop_func op_0a7c_11_ff;
+extern cpuop_func op_0a80_11_nf;
+extern cpuop_func op_0a80_11_ff;
+extern cpuop_func op_0a90_11_nf;
+extern cpuop_func op_0a90_11_ff;
+extern cpuop_func op_0a98_11_nf;
+extern cpuop_func op_0a98_11_ff;
+extern cpuop_func op_0aa0_11_nf;
+extern cpuop_func op_0aa0_11_ff;
+extern cpuop_func op_0aa8_11_nf;
+extern cpuop_func op_0aa8_11_ff;
+extern cpuop_func op_0ab0_11_nf;
+extern cpuop_func op_0ab0_11_ff;
+extern cpuop_func op_0ab8_11_nf;
+extern cpuop_func op_0ab8_11_ff;
+extern cpuop_func op_0ab9_11_nf;
+extern cpuop_func op_0ab9_11_ff;
+extern cpuop_func op_0c00_11_nf;
+extern cpuop_func op_0c00_11_ff;
+extern cpuop_func op_0c10_11_nf;
+extern cpuop_func op_0c10_11_ff;
+extern cpuop_func op_0c18_11_nf;
+extern cpuop_func op_0c18_11_ff;
+extern cpuop_func op_0c20_11_nf;
+extern cpuop_func op_0c20_11_ff;
+extern cpuop_func op_0c28_11_nf;
+extern cpuop_func op_0c28_11_ff;
+extern cpuop_func op_0c30_11_nf;
+extern cpuop_func op_0c30_11_ff;
+extern cpuop_func op_0c38_11_nf;
+extern cpuop_func op_0c38_11_ff;
+extern cpuop_func op_0c39_11_nf;
+extern cpuop_func op_0c39_11_ff;
+extern cpuop_func op_0c40_11_nf;
+extern cpuop_func op_0c40_11_ff;
+extern cpuop_func op_0c50_11_nf;
+extern cpuop_func op_0c50_11_ff;
+extern cpuop_func op_0c58_11_nf;
+extern cpuop_func op_0c58_11_ff;
+extern cpuop_func op_0c60_11_nf;
+extern cpuop_func op_0c60_11_ff;
+extern cpuop_func op_0c68_11_nf;
+extern cpuop_func op_0c68_11_ff;
+extern cpuop_func op_0c70_11_nf;
+extern cpuop_func op_0c70_11_ff;
+extern cpuop_func op_0c78_11_nf;
+extern cpuop_func op_0c78_11_ff;
+extern cpuop_func op_0c79_11_nf;
+extern cpuop_func op_0c79_11_ff;
+extern cpuop_func op_0c80_11_nf;
+extern cpuop_func op_0c80_11_ff;
+extern cpuop_func op_0c90_11_nf;
+extern cpuop_func op_0c90_11_ff;
+extern cpuop_func op_0c98_11_nf;
+extern cpuop_func op_0c98_11_ff;
+extern cpuop_func op_0ca0_11_nf;
+extern cpuop_func op_0ca0_11_ff;
+extern cpuop_func op_0ca8_11_nf;
+extern cpuop_func op_0ca8_11_ff;
+extern cpuop_func op_0cb0_11_nf;
+extern cpuop_func op_0cb0_11_ff;
+extern cpuop_func op_0cb8_11_nf;
+extern cpuop_func op_0cb8_11_ff;
+extern cpuop_func op_0cb9_11_nf;
+extern cpuop_func op_0cb9_11_ff;
+extern cpuop_func op_1000_11_nf;
+extern cpuop_func op_1000_11_ff;
+extern cpuop_func op_1010_11_nf;
+extern cpuop_func op_1010_11_ff;
+extern cpuop_func op_1018_11_nf;
+extern cpuop_func op_1018_11_ff;
+extern cpuop_func op_1020_11_nf;
+extern cpuop_func op_1020_11_ff;
+extern cpuop_func op_1028_11_nf;
+extern cpuop_func op_1028_11_ff;
+extern cpuop_func op_1030_11_nf;
+extern cpuop_func op_1030_11_ff;
+extern cpuop_func op_1038_11_nf;
+extern cpuop_func op_1038_11_ff;
+extern cpuop_func op_1039_11_nf;
+extern cpuop_func op_1039_11_ff;
+extern cpuop_func op_103a_11_nf;
+extern cpuop_func op_103a_11_ff;
+extern cpuop_func op_103b_11_nf;
+extern cpuop_func op_103b_11_ff;
+extern cpuop_func op_103c_11_nf;
+extern cpuop_func op_103c_11_ff;
+extern cpuop_func op_1080_11_nf;
+extern cpuop_func op_1080_11_ff;
+extern cpuop_func op_1090_11_nf;
+extern cpuop_func op_1090_11_ff;
+extern cpuop_func op_1098_11_nf;
+extern cpuop_func op_1098_11_ff;
+extern cpuop_func op_10a0_11_nf;
+extern cpuop_func op_10a0_11_ff;
+extern cpuop_func op_10a8_11_nf;
+extern cpuop_func op_10a8_11_ff;
+extern cpuop_func op_10b0_11_nf;
+extern cpuop_func op_10b0_11_ff;
+extern cpuop_func op_10b8_11_nf;
+extern cpuop_func op_10b8_11_ff;
+extern cpuop_func op_10b9_11_nf;
+extern cpuop_func op_10b9_11_ff;
+extern cpuop_func op_10ba_11_nf;
+extern cpuop_func op_10ba_11_ff;
+extern cpuop_func op_10bb_11_nf;
+extern cpuop_func op_10bb_11_ff;
+extern cpuop_func op_10bc_11_nf;
+extern cpuop_func op_10bc_11_ff;
+extern cpuop_func op_10c0_11_nf;
+extern cpuop_func op_10c0_11_ff;
+extern cpuop_func op_10d0_11_nf;
+extern cpuop_func op_10d0_11_ff;
+extern cpuop_func op_10d8_11_nf;
+extern cpuop_func op_10d8_11_ff;
+extern cpuop_func op_10e0_11_nf;
+extern cpuop_func op_10e0_11_ff;
+extern cpuop_func op_10e8_11_nf;
+extern cpuop_func op_10e8_11_ff;
+extern cpuop_func op_10f0_11_nf;
+extern cpuop_func op_10f0_11_ff;
+extern cpuop_func op_10f8_11_nf;
+extern cpuop_func op_10f8_11_ff;
+extern cpuop_func op_10f9_11_nf;
+extern cpuop_func op_10f9_11_ff;
+extern cpuop_func op_10fa_11_nf;
+extern cpuop_func op_10fa_11_ff;
+extern cpuop_func op_10fb_11_nf;
+extern cpuop_func op_10fb_11_ff;
+extern cpuop_func op_10fc_11_nf;
+extern cpuop_func op_10fc_11_ff;
+extern cpuop_func op_1100_11_nf;
+extern cpuop_func op_1100_11_ff;
+extern cpuop_func op_1110_11_nf;
+extern cpuop_func op_1110_11_ff;
+extern cpuop_func op_1118_11_nf;
+extern cpuop_func op_1118_11_ff;
+extern cpuop_func op_1120_11_nf;
+extern cpuop_func op_1120_11_ff;
+extern cpuop_func op_1128_11_nf;
+extern cpuop_func op_1128_11_ff;
+extern cpuop_func op_1130_11_nf;
+extern cpuop_func op_1130_11_ff;
+extern cpuop_func op_1138_11_nf;
+extern cpuop_func op_1138_11_ff;
+extern cpuop_func op_1139_11_nf;
+extern cpuop_func op_1139_11_ff;
+extern cpuop_func op_113a_11_nf;
+extern cpuop_func op_113a_11_ff;
+extern cpuop_func op_113b_11_nf;
+extern cpuop_func op_113b_11_ff;
+extern cpuop_func op_113c_11_nf;
+extern cpuop_func op_113c_11_ff;
+extern cpuop_func op_1140_11_nf;
+extern cpuop_func op_1140_11_ff;
+extern cpuop_func op_1150_11_nf;
+extern cpuop_func op_1150_11_ff;
+extern cpuop_func op_1158_11_nf;
+extern cpuop_func op_1158_11_ff;
+extern cpuop_func op_1160_11_nf;
+extern cpuop_func op_1160_11_ff;
+extern cpuop_func op_1168_11_nf;
+extern cpuop_func op_1168_11_ff;
+extern cpuop_func op_1170_11_nf;
+extern cpuop_func op_1170_11_ff;
+extern cpuop_func op_1178_11_nf;
+extern cpuop_func op_1178_11_ff;
+extern cpuop_func op_1179_11_nf;
+extern cpuop_func op_1179_11_ff;
+extern cpuop_func op_117a_11_nf;
+extern cpuop_func op_117a_11_ff;
+extern cpuop_func op_117b_11_nf;
+extern cpuop_func op_117b_11_ff;
+extern cpuop_func op_117c_11_nf;
+extern cpuop_func op_117c_11_ff;
+extern cpuop_func op_1180_11_nf;
+extern cpuop_func op_1180_11_ff;
+extern cpuop_func op_1190_11_nf;
+extern cpuop_func op_1190_11_ff;
+extern cpuop_func op_1198_11_nf;
+extern cpuop_func op_1198_11_ff;
+extern cpuop_func op_11a0_11_nf;
+extern cpuop_func op_11a0_11_ff;
+extern cpuop_func op_11a8_11_nf;
+extern cpuop_func op_11a8_11_ff;
+extern cpuop_func op_11b0_11_nf;
+extern cpuop_func op_11b0_11_ff;
+extern cpuop_func op_11b8_11_nf;
+extern cpuop_func op_11b8_11_ff;
+extern cpuop_func op_11b9_11_nf;
+extern cpuop_func op_11b9_11_ff;
+extern cpuop_func op_11ba_11_nf;
+extern cpuop_func op_11ba_11_ff;
+extern cpuop_func op_11bb_11_nf;
+extern cpuop_func op_11bb_11_ff;
+extern cpuop_func op_11bc_11_nf;
+extern cpuop_func op_11bc_11_ff;
+extern cpuop_func op_11c0_11_nf;
+extern cpuop_func op_11c0_11_ff;
+extern cpuop_func op_11d0_11_nf;
+extern cpuop_func op_11d0_11_ff;
+extern cpuop_func op_11d8_11_nf;
+extern cpuop_func op_11d8_11_ff;
+extern cpuop_func op_11e0_11_nf;
+extern cpuop_func op_11e0_11_ff;
+extern cpuop_func op_11e8_11_nf;
+extern cpuop_func op_11e8_11_ff;
+extern cpuop_func op_11f0_11_nf;
+extern cpuop_func op_11f0_11_ff;
+extern cpuop_func op_11f8_11_nf;
+extern cpuop_func op_11f8_11_ff;
+extern cpuop_func op_11f9_11_nf;
+extern cpuop_func op_11f9_11_ff;
+extern cpuop_func op_11fa_11_nf;
+extern cpuop_func op_11fa_11_ff;
+extern cpuop_func op_11fb_11_nf;
+extern cpuop_func op_11fb_11_ff;
+extern cpuop_func op_11fc_11_nf;
+extern cpuop_func op_11fc_11_ff;
+extern cpuop_func op_13c0_11_nf;
+extern cpuop_func op_13c0_11_ff;
+extern cpuop_func op_13d0_11_nf;
+extern cpuop_func op_13d0_11_ff;
+extern cpuop_func op_13d8_11_nf;
+extern cpuop_func op_13d8_11_ff;
+extern cpuop_func op_13e0_11_nf;
+extern cpuop_func op_13e0_11_ff;
+extern cpuop_func op_13e8_11_nf;
+extern cpuop_func op_13e8_11_ff;
+extern cpuop_func op_13f0_11_nf;
+extern cpuop_func op_13f0_11_ff;
+extern cpuop_func op_13f8_11_nf;
+extern cpuop_func op_13f8_11_ff;
+extern cpuop_func op_13f9_11_nf;
+extern cpuop_func op_13f9_11_ff;
+extern cpuop_func op_13fa_11_nf;
+extern cpuop_func op_13fa_11_ff;
+extern cpuop_func op_13fb_11_nf;
+extern cpuop_func op_13fb_11_ff;
+extern cpuop_func op_13fc_11_nf;
+extern cpuop_func op_13fc_11_ff;
+extern cpuop_func op_2000_11_nf;
+extern cpuop_func op_2000_11_ff;
+extern cpuop_func op_2008_11_nf;
+extern cpuop_func op_2008_11_ff;
+extern cpuop_func op_2010_11_nf;
+extern cpuop_func op_2010_11_ff;
+extern cpuop_func op_2018_11_nf;
+extern cpuop_func op_2018_11_ff;
+extern cpuop_func op_2020_11_nf;
+extern cpuop_func op_2020_11_ff;
+extern cpuop_func op_2028_11_nf;
+extern cpuop_func op_2028_11_ff;
+extern cpuop_func op_2030_11_nf;
+extern cpuop_func op_2030_11_ff;
+extern cpuop_func op_2038_11_nf;
+extern cpuop_func op_2038_11_ff;
+extern cpuop_func op_2039_11_nf;
+extern cpuop_func op_2039_11_ff;
+extern cpuop_func op_203a_11_nf;
+extern cpuop_func op_203a_11_ff;
+extern cpuop_func op_203b_11_nf;
+extern cpuop_func op_203b_11_ff;
+extern cpuop_func op_203c_11_nf;
+extern cpuop_func op_203c_11_ff;
+extern cpuop_func op_2040_11_nf;
+extern cpuop_func op_2040_11_ff;
+extern cpuop_func op_2048_11_nf;
+extern cpuop_func op_2048_11_ff;
+extern cpuop_func op_2050_11_nf;
+extern cpuop_func op_2050_11_ff;
+extern cpuop_func op_2058_11_nf;
+extern cpuop_func op_2058_11_ff;
+extern cpuop_func op_2060_11_nf;
+extern cpuop_func op_2060_11_ff;
+extern cpuop_func op_2068_11_nf;
+extern cpuop_func op_2068_11_ff;
+extern cpuop_func op_2070_11_nf;
+extern cpuop_func op_2070_11_ff;
+extern cpuop_func op_2078_11_nf;
+extern cpuop_func op_2078_11_ff;
+extern cpuop_func op_2079_11_nf;
+extern cpuop_func op_2079_11_ff;
+extern cpuop_func op_207a_11_nf;
+extern cpuop_func op_207a_11_ff;
+extern cpuop_func op_207b_11_nf;
+extern cpuop_func op_207b_11_ff;
+extern cpuop_func op_207c_11_nf;
+extern cpuop_func op_207c_11_ff;
+extern cpuop_func op_2080_11_nf;
+extern cpuop_func op_2080_11_ff;
+extern cpuop_func op_2088_11_nf;
+extern cpuop_func op_2088_11_ff;
+extern cpuop_func op_2090_11_nf;
+extern cpuop_func op_2090_11_ff;
+extern cpuop_func op_2098_11_nf;
+extern cpuop_func op_2098_11_ff;
+extern cpuop_func op_20a0_11_nf;
+extern cpuop_func op_20a0_11_ff;
+extern cpuop_func op_20a8_11_nf;
+extern cpuop_func op_20a8_11_ff;
+extern cpuop_func op_20b0_11_nf;
+extern cpuop_func op_20b0_11_ff;
+extern cpuop_func op_20b8_11_nf;
+extern cpuop_func op_20b8_11_ff;
+extern cpuop_func op_20b9_11_nf;
+extern cpuop_func op_20b9_11_ff;
+extern cpuop_func op_20ba_11_nf;
+extern cpuop_func op_20ba_11_ff;
+extern cpuop_func op_20bb_11_nf;
+extern cpuop_func op_20bb_11_ff;
+extern cpuop_func op_20bc_11_nf;
+extern cpuop_func op_20bc_11_ff;
+extern cpuop_func op_20c0_11_nf;
+extern cpuop_func op_20c0_11_ff;
+extern cpuop_func op_20c8_11_nf;
+extern cpuop_func op_20c8_11_ff;
+extern cpuop_func op_20d0_11_nf;
+extern cpuop_func op_20d0_11_ff;
+extern cpuop_func op_20d8_11_nf;
+extern cpuop_func op_20d8_11_ff;
+extern cpuop_func op_20e0_11_nf;
+extern cpuop_func op_20e0_11_ff;
+extern cpuop_func op_20e8_11_nf;
+extern cpuop_func op_20e8_11_ff;
+extern cpuop_func op_20f0_11_nf;
+extern cpuop_func op_20f0_11_ff;
+extern cpuop_func op_20f8_11_nf;
+extern cpuop_func op_20f8_11_ff;
+extern cpuop_func op_20f9_11_nf;
+extern cpuop_func op_20f9_11_ff;
+extern cpuop_func op_20fa_11_nf;
+extern cpuop_func op_20fa_11_ff;
+extern cpuop_func op_20fb_11_nf;
+extern cpuop_func op_20fb_11_ff;
+extern cpuop_func op_20fc_11_nf;
+extern cpuop_func op_20fc_11_ff;
+extern cpuop_func op_2100_11_nf;
+extern cpuop_func op_2100_11_ff;
+extern cpuop_func op_2108_11_nf;
+extern cpuop_func op_2108_11_ff;
+extern cpuop_func op_2110_11_nf;
+extern cpuop_func op_2110_11_ff;
+extern cpuop_func op_2118_11_nf;
+extern cpuop_func op_2118_11_ff;
+extern cpuop_func op_2120_11_nf;
+extern cpuop_func op_2120_11_ff;
+extern cpuop_func op_2128_11_nf;
+extern cpuop_func op_2128_11_ff;
+extern cpuop_func op_2130_11_nf;
+extern cpuop_func op_2130_11_ff;
+extern cpuop_func op_2138_11_nf;
+extern cpuop_func op_2138_11_ff;
+extern cpuop_func op_2139_11_nf;
+extern cpuop_func op_2139_11_ff;
+extern cpuop_func op_213a_11_nf;
+extern cpuop_func op_213a_11_ff;
+extern cpuop_func op_213b_11_nf;
+extern cpuop_func op_213b_11_ff;
+extern cpuop_func op_213c_11_nf;
+extern cpuop_func op_213c_11_ff;
+extern cpuop_func op_2140_11_nf;
+extern cpuop_func op_2140_11_ff;
+extern cpuop_func op_2148_11_nf;
+extern cpuop_func op_2148_11_ff;
+extern cpuop_func op_2150_11_nf;
+extern cpuop_func op_2150_11_ff;
+extern cpuop_func op_2158_11_nf;
+extern cpuop_func op_2158_11_ff;
+extern cpuop_func op_2160_11_nf;
+extern cpuop_func op_2160_11_ff;
+extern cpuop_func op_2168_11_nf;
+extern cpuop_func op_2168_11_ff;
+extern cpuop_func op_2170_11_nf;
+extern cpuop_func op_2170_11_ff;
+extern cpuop_func op_2178_11_nf;
+extern cpuop_func op_2178_11_ff;
+extern cpuop_func op_2179_11_nf;
+extern cpuop_func op_2179_11_ff;
+extern cpuop_func op_217a_11_nf;
+extern cpuop_func op_217a_11_ff;
+extern cpuop_func op_217b_11_nf;
+extern cpuop_func op_217b_11_ff;
+extern cpuop_func op_217c_11_nf;
+extern cpuop_func op_217c_11_ff;
+extern cpuop_func op_2180_11_nf;
+extern cpuop_func op_2180_11_ff;
+extern cpuop_func op_2188_11_nf;
+extern cpuop_func op_2188_11_ff;
+extern cpuop_func op_2190_11_nf;
+extern cpuop_func op_2190_11_ff;
+extern cpuop_func op_2198_11_nf;
+extern cpuop_func op_2198_11_ff;
+extern cpuop_func op_21a0_11_nf;
+extern cpuop_func op_21a0_11_ff;
+extern cpuop_func op_21a8_11_nf;
+extern cpuop_func op_21a8_11_ff;
+extern cpuop_func op_21b0_11_nf;
+extern cpuop_func op_21b0_11_ff;
+extern cpuop_func op_21b8_11_nf;
+extern cpuop_func op_21b8_11_ff;
+extern cpuop_func op_21b9_11_nf;
+extern cpuop_func op_21b9_11_ff;
+extern cpuop_func op_21ba_11_nf;
+extern cpuop_func op_21ba_11_ff;
+extern cpuop_func op_21bb_11_nf;
+extern cpuop_func op_21bb_11_ff;
+extern cpuop_func op_21bc_11_nf;
+extern cpuop_func op_21bc_11_ff;
+extern cpuop_func op_21c0_11_nf;
+extern cpuop_func op_21c0_11_ff;
+extern cpuop_func op_21c8_11_nf;
+extern cpuop_func op_21c8_11_ff;
+extern cpuop_func op_21d0_11_nf;
+extern cpuop_func op_21d0_11_ff;
+extern cpuop_func op_21d8_11_nf;
+extern cpuop_func op_21d8_11_ff;
+extern cpuop_func op_21e0_11_nf;
+extern cpuop_func op_21e0_11_ff;
+extern cpuop_func op_21e8_11_nf;
+extern cpuop_func op_21e8_11_ff;
+extern cpuop_func op_21f0_11_nf;
+extern cpuop_func op_21f0_11_ff;
+extern cpuop_func op_21f8_11_nf;
+extern cpuop_func op_21f8_11_ff;
+extern cpuop_func op_21f9_11_nf;
+extern cpuop_func op_21f9_11_ff;
+extern cpuop_func op_21fa_11_nf;
+extern cpuop_func op_21fa_11_ff;
+extern cpuop_func op_21fb_11_nf;
+extern cpuop_func op_21fb_11_ff;
+extern cpuop_func op_21fc_11_nf;
+extern cpuop_func op_21fc_11_ff;
+extern cpuop_func op_23c0_11_nf;
+extern cpuop_func op_23c0_11_ff;
+extern cpuop_func op_23c8_11_nf;
+extern cpuop_func op_23c8_11_ff;
+extern cpuop_func op_23d0_11_nf;
+extern cpuop_func op_23d0_11_ff;
+extern cpuop_func op_23d8_11_nf;
+extern cpuop_func op_23d8_11_ff;
+extern cpuop_func op_23e0_11_nf;
+extern cpuop_func op_23e0_11_ff;
+extern cpuop_func op_23e8_11_nf;
+extern cpuop_func op_23e8_11_ff;
+extern cpuop_func op_23f0_11_nf;
+extern cpuop_func op_23f0_11_ff;
+extern cpuop_func op_23f8_11_nf;
+extern cpuop_func op_23f8_11_ff;
+extern cpuop_func op_23f9_11_nf;
+extern cpuop_func op_23f9_11_ff;
+extern cpuop_func op_23fa_11_nf;
+extern cpuop_func op_23fa_11_ff;
+extern cpuop_func op_23fb_11_nf;
+extern cpuop_func op_23fb_11_ff;
+extern cpuop_func op_23fc_11_nf;
+extern cpuop_func op_23fc_11_ff;
+extern cpuop_func op_3000_11_nf;
+extern cpuop_func op_3000_11_ff;
+extern cpuop_func op_3008_11_nf;
+extern cpuop_func op_3008_11_ff;
+extern cpuop_func op_3010_11_nf;
+extern cpuop_func op_3010_11_ff;
+extern cpuop_func op_3018_11_nf;
+extern cpuop_func op_3018_11_ff;
+extern cpuop_func op_3020_11_nf;
+extern cpuop_func op_3020_11_ff;
+extern cpuop_func op_3028_11_nf;
+extern cpuop_func op_3028_11_ff;
+extern cpuop_func op_3030_11_nf;
+extern cpuop_func op_3030_11_ff;
+extern cpuop_func op_3038_11_nf;
+extern cpuop_func op_3038_11_ff;
+extern cpuop_func op_3039_11_nf;
+extern cpuop_func op_3039_11_ff;
+extern cpuop_func op_303a_11_nf;
+extern cpuop_func op_303a_11_ff;
+extern cpuop_func op_303b_11_nf;
+extern cpuop_func op_303b_11_ff;
+extern cpuop_func op_303c_11_nf;
+extern cpuop_func op_303c_11_ff;
+extern cpuop_func op_3040_11_nf;
+extern cpuop_func op_3040_11_ff;
+extern cpuop_func op_3048_11_nf;
+extern cpuop_func op_3048_11_ff;
+extern cpuop_func op_3050_11_nf;
+extern cpuop_func op_3050_11_ff;
+extern cpuop_func op_3058_11_nf;
+extern cpuop_func op_3058_11_ff;
+extern cpuop_func op_3060_11_nf;
+extern cpuop_func op_3060_11_ff;
+extern cpuop_func op_3068_11_nf;
+extern cpuop_func op_3068_11_ff;
+extern cpuop_func op_3070_11_nf;
+extern cpuop_func op_3070_11_ff;
+extern cpuop_func op_3078_11_nf;
+extern cpuop_func op_3078_11_ff;
+extern cpuop_func op_3079_11_nf;
+extern cpuop_func op_3079_11_ff;
+extern cpuop_func op_307a_11_nf;
+extern cpuop_func op_307a_11_ff;
+extern cpuop_func op_307b_11_nf;
+extern cpuop_func op_307b_11_ff;
+extern cpuop_func op_307c_11_nf;
+extern cpuop_func op_307c_11_ff;
+extern cpuop_func op_3080_11_nf;
+extern cpuop_func op_3080_11_ff;
+extern cpuop_func op_3088_11_nf;
+extern cpuop_func op_3088_11_ff;
+extern cpuop_func op_3090_11_nf;
+extern cpuop_func op_3090_11_ff;
+extern cpuop_func op_3098_11_nf;
+extern cpuop_func op_3098_11_ff;
+extern cpuop_func op_30a0_11_nf;
+extern cpuop_func op_30a0_11_ff;
+extern cpuop_func op_30a8_11_nf;
+extern cpuop_func op_30a8_11_ff;
+extern cpuop_func op_30b0_11_nf;
+extern cpuop_func op_30b0_11_ff;
+extern cpuop_func op_30b8_11_nf;
+extern cpuop_func op_30b8_11_ff;
+extern cpuop_func op_30b9_11_nf;
+extern cpuop_func op_30b9_11_ff;
+extern cpuop_func op_30ba_11_nf;
+extern cpuop_func op_30ba_11_ff;
+extern cpuop_func op_30bb_11_nf;
+extern cpuop_func op_30bb_11_ff;
+extern cpuop_func op_30bc_11_nf;
+extern cpuop_func op_30bc_11_ff;
+extern cpuop_func op_30c0_11_nf;
+extern cpuop_func op_30c0_11_ff;
+extern cpuop_func op_30c8_11_nf;
+extern cpuop_func op_30c8_11_ff;
+extern cpuop_func op_30d0_11_nf;
+extern cpuop_func op_30d0_11_ff;
+extern cpuop_func op_30d8_11_nf;
+extern cpuop_func op_30d8_11_ff;
+extern cpuop_func op_30e0_11_nf;
+extern cpuop_func op_30e0_11_ff;
+extern cpuop_func op_30e8_11_nf;
+extern cpuop_func op_30e8_11_ff;
+extern cpuop_func op_30f0_11_nf;
+extern cpuop_func op_30f0_11_ff;
+extern cpuop_func op_30f8_11_nf;
+extern cpuop_func op_30f8_11_ff;
+extern cpuop_func op_30f9_11_nf;
+extern cpuop_func op_30f9_11_ff;
+extern cpuop_func op_30fa_11_nf;
+extern cpuop_func op_30fa_11_ff;
+extern cpuop_func op_30fb_11_nf;
+extern cpuop_func op_30fb_11_ff;
+extern cpuop_func op_30fc_11_nf;
+extern cpuop_func op_30fc_11_ff;
+extern cpuop_func op_3100_11_nf;
+extern cpuop_func op_3100_11_ff;
+extern cpuop_func op_3108_11_nf;
+extern cpuop_func op_3108_11_ff;
+extern cpuop_func op_3110_11_nf;
+extern cpuop_func op_3110_11_ff;
+extern cpuop_func op_3118_11_nf;
+extern cpuop_func op_3118_11_ff;
+extern cpuop_func op_3120_11_nf;
+extern cpuop_func op_3120_11_ff;
+extern cpuop_func op_3128_11_nf;
+extern cpuop_func op_3128_11_ff;
+extern cpuop_func op_3130_11_nf;
+extern cpuop_func op_3130_11_ff;
+extern cpuop_func op_3138_11_nf;
+extern cpuop_func op_3138_11_ff;
+extern cpuop_func op_3139_11_nf;
+extern cpuop_func op_3139_11_ff;
+extern cpuop_func op_313a_11_nf;
+extern cpuop_func op_313a_11_ff;
+extern cpuop_func op_313b_11_nf;
+extern cpuop_func op_313b_11_ff;
+extern cpuop_func op_313c_11_nf;
+extern cpuop_func op_313c_11_ff;
+extern cpuop_func op_3140_11_nf;
+extern cpuop_func op_3140_11_ff;
+extern cpuop_func op_3148_11_nf;
+extern cpuop_func op_3148_11_ff;
+extern cpuop_func op_3150_11_nf;
+extern cpuop_func op_3150_11_ff;
+extern cpuop_func op_3158_11_nf;
+extern cpuop_func op_3158_11_ff;
+extern cpuop_func op_3160_11_nf;
+extern cpuop_func op_3160_11_ff;
+extern cpuop_func op_3168_11_nf;
+extern cpuop_func op_3168_11_ff;
+extern cpuop_func op_3170_11_nf;
+extern cpuop_func op_3170_11_ff;
+extern cpuop_func op_3178_11_nf;
+extern cpuop_func op_3178_11_ff;
+extern cpuop_func op_3179_11_nf;
+extern cpuop_func op_3179_11_ff;
+extern cpuop_func op_317a_11_nf;
+extern cpuop_func op_317a_11_ff;
+extern cpuop_func op_317b_11_nf;
+extern cpuop_func op_317b_11_ff;
+extern cpuop_func op_317c_11_nf;
+extern cpuop_func op_317c_11_ff;
+extern cpuop_func op_3180_11_nf;
+extern cpuop_func op_3180_11_ff;
+extern cpuop_func op_3188_11_nf;
+extern cpuop_func op_3188_11_ff;
+extern cpuop_func op_3190_11_nf;
+extern cpuop_func op_3190_11_ff;
+extern cpuop_func op_3198_11_nf;
+extern cpuop_func op_3198_11_ff;
+extern cpuop_func op_31a0_11_nf;
+extern cpuop_func op_31a0_11_ff;
+extern cpuop_func op_31a8_11_nf;
+extern cpuop_func op_31a8_11_ff;
+extern cpuop_func op_31b0_11_nf;
+extern cpuop_func op_31b0_11_ff;
+extern cpuop_func op_31b8_11_nf;
+extern cpuop_func op_31b8_11_ff;
+extern cpuop_func op_31b9_11_nf;
+extern cpuop_func op_31b9_11_ff;
+extern cpuop_func op_31ba_11_nf;
+extern cpuop_func op_31ba_11_ff;
+extern cpuop_func op_31bb_11_nf;
+extern cpuop_func op_31bb_11_ff;
+extern cpuop_func op_31bc_11_nf;
+extern cpuop_func op_31bc_11_ff;
+extern cpuop_func op_31c0_11_nf;
+extern cpuop_func op_31c0_11_ff;
+extern cpuop_func op_31c8_11_nf;
+extern cpuop_func op_31c8_11_ff;
+extern cpuop_func op_31d0_11_nf;
+extern cpuop_func op_31d0_11_ff;
+extern cpuop_func op_31d8_11_nf;
+extern cpuop_func op_31d8_11_ff;
+extern cpuop_func op_31e0_11_nf;
+extern cpuop_func op_31e0_11_ff;
+extern cpuop_func op_31e8_11_nf;
+extern cpuop_func op_31e8_11_ff;
+extern cpuop_func op_31f0_11_nf;
+extern cpuop_func op_31f0_11_ff;
+extern cpuop_func op_31f8_11_nf;
+extern cpuop_func op_31f8_11_ff;
+extern cpuop_func op_31f9_11_nf;
+extern cpuop_func op_31f9_11_ff;
+extern cpuop_func op_31fa_11_nf;
+extern cpuop_func op_31fa_11_ff;
+extern cpuop_func op_31fb_11_nf;
+extern cpuop_func op_31fb_11_ff;
+extern cpuop_func op_31fc_11_nf;
+extern cpuop_func op_31fc_11_ff;
+extern cpuop_func op_33c0_11_nf;
+extern cpuop_func op_33c0_11_ff;
+extern cpuop_func op_33c8_11_nf;
+extern cpuop_func op_33c8_11_ff;
+extern cpuop_func op_33d0_11_nf;
+extern cpuop_func op_33d0_11_ff;
+extern cpuop_func op_33d8_11_nf;
+extern cpuop_func op_33d8_11_ff;
+extern cpuop_func op_33e0_11_nf;
+extern cpuop_func op_33e0_11_ff;
+extern cpuop_func op_33e8_11_nf;
+extern cpuop_func op_33e8_11_ff;
+extern cpuop_func op_33f0_11_nf;
+extern cpuop_func op_33f0_11_ff;
+extern cpuop_func op_33f8_11_nf;
+extern cpuop_func op_33f8_11_ff;
+extern cpuop_func op_33f9_11_nf;
+extern cpuop_func op_33f9_11_ff;
+extern cpuop_func op_33fa_11_nf;
+extern cpuop_func op_33fa_11_ff;
+extern cpuop_func op_33fb_11_nf;
+extern cpuop_func op_33fb_11_ff;
+extern cpuop_func op_33fc_11_nf;
+extern cpuop_func op_33fc_11_ff;
+extern cpuop_func op_4000_11_nf;
+extern cpuop_func op_4000_11_ff;
+extern cpuop_func op_4010_11_nf;
+extern cpuop_func op_4010_11_ff;
+extern cpuop_func op_4018_11_nf;
+extern cpuop_func op_4018_11_ff;
+extern cpuop_func op_4020_11_nf;
+extern cpuop_func op_4020_11_ff;
+extern cpuop_func op_4028_11_nf;
+extern cpuop_func op_4028_11_ff;
+extern cpuop_func op_4030_11_nf;
+extern cpuop_func op_4030_11_ff;
+extern cpuop_func op_4038_11_nf;
+extern cpuop_func op_4038_11_ff;
+extern cpuop_func op_4039_11_nf;
+extern cpuop_func op_4039_11_ff;
+extern cpuop_func op_4040_11_nf;
+extern cpuop_func op_4040_11_ff;
+extern cpuop_func op_4050_11_nf;
+extern cpuop_func op_4050_11_ff;
+extern cpuop_func op_4058_11_nf;
+extern cpuop_func op_4058_11_ff;
+extern cpuop_func op_4060_11_nf;
+extern cpuop_func op_4060_11_ff;
+extern cpuop_func op_4068_11_nf;
+extern cpuop_func op_4068_11_ff;
+extern cpuop_func op_4070_11_nf;
+extern cpuop_func op_4070_11_ff;
+extern cpuop_func op_4078_11_nf;
+extern cpuop_func op_4078_11_ff;
+extern cpuop_func op_4079_11_nf;
+extern cpuop_func op_4079_11_ff;
+extern cpuop_func op_4080_11_nf;
+extern cpuop_func op_4080_11_ff;
+extern cpuop_func op_4090_11_nf;
+extern cpuop_func op_4090_11_ff;
+extern cpuop_func op_4098_11_nf;
+extern cpuop_func op_4098_11_ff;
+extern cpuop_func op_40a0_11_nf;
+extern cpuop_func op_40a0_11_ff;
+extern cpuop_func op_40a8_11_nf;
+extern cpuop_func op_40a8_11_ff;
+extern cpuop_func op_40b0_11_nf;
+extern cpuop_func op_40b0_11_ff;
+extern cpuop_func op_40b8_11_nf;
+extern cpuop_func op_40b8_11_ff;
+extern cpuop_func op_40b9_11_nf;
+extern cpuop_func op_40b9_11_ff;
+extern cpuop_func op_40c0_11_nf;
+extern cpuop_func op_40c0_11_ff;
+extern cpuop_func op_40d0_11_nf;
+extern cpuop_func op_40d0_11_ff;
+extern cpuop_func op_40d8_11_nf;
+extern cpuop_func op_40d8_11_ff;
+extern cpuop_func op_40e0_11_nf;
+extern cpuop_func op_40e0_11_ff;
+extern cpuop_func op_40e8_11_nf;
+extern cpuop_func op_40e8_11_ff;
+extern cpuop_func op_40f0_11_nf;
+extern cpuop_func op_40f0_11_ff;
+extern cpuop_func op_40f8_11_nf;
+extern cpuop_func op_40f8_11_ff;
+extern cpuop_func op_40f9_11_nf;
+extern cpuop_func op_40f9_11_ff;
+extern cpuop_func op_4180_11_nf;
+extern cpuop_func op_4180_11_ff;
+extern cpuop_func op_4190_11_nf;
+extern cpuop_func op_4190_11_ff;
+extern cpuop_func op_4198_11_nf;
+extern cpuop_func op_4198_11_ff;
+extern cpuop_func op_41a0_11_nf;
+extern cpuop_func op_41a0_11_ff;
+extern cpuop_func op_41a8_11_nf;
+extern cpuop_func op_41a8_11_ff;
+extern cpuop_func op_41b0_11_nf;
+extern cpuop_func op_41b0_11_ff;
+extern cpuop_func op_41b8_11_nf;
+extern cpuop_func op_41b8_11_ff;
+extern cpuop_func op_41b9_11_nf;
+extern cpuop_func op_41b9_11_ff;
+extern cpuop_func op_41ba_11_nf;
+extern cpuop_func op_41ba_11_ff;
+extern cpuop_func op_41bb_11_nf;
+extern cpuop_func op_41bb_11_ff;
+extern cpuop_func op_41bc_11_nf;
+extern cpuop_func op_41bc_11_ff;
+extern cpuop_func op_41d0_11_nf;
+extern cpuop_func op_41d0_11_ff;
+extern cpuop_func op_41e8_11_nf;
+extern cpuop_func op_41e8_11_ff;
+extern cpuop_func op_41f0_11_nf;
+extern cpuop_func op_41f0_11_ff;
+extern cpuop_func op_41f8_11_nf;
+extern cpuop_func op_41f8_11_ff;
+extern cpuop_func op_41f9_11_nf;
+extern cpuop_func op_41f9_11_ff;
+extern cpuop_func op_41fa_11_nf;
+extern cpuop_func op_41fa_11_ff;
+extern cpuop_func op_41fb_11_nf;
+extern cpuop_func op_41fb_11_ff;
+extern cpuop_func op_4200_11_nf;
+extern cpuop_func op_4200_11_ff;
+extern cpuop_func op_4210_11_nf;
+extern cpuop_func op_4210_11_ff;
+extern cpuop_func op_4218_11_nf;
+extern cpuop_func op_4218_11_ff;
+extern cpuop_func op_4220_11_nf;
+extern cpuop_func op_4220_11_ff;
+extern cpuop_func op_4228_11_nf;
+extern cpuop_func op_4228_11_ff;
+extern cpuop_func op_4230_11_nf;
+extern cpuop_func op_4230_11_ff;
+extern cpuop_func op_4238_11_nf;
+extern cpuop_func op_4238_11_ff;
+extern cpuop_func op_4239_11_nf;
+extern cpuop_func op_4239_11_ff;
+extern cpuop_func op_4240_11_nf;
+extern cpuop_func op_4240_11_ff;
+extern cpuop_func op_4250_11_nf;
+extern cpuop_func op_4250_11_ff;
+extern cpuop_func op_4258_11_nf;
+extern cpuop_func op_4258_11_ff;
+extern cpuop_func op_4260_11_nf;
+extern cpuop_func op_4260_11_ff;
+extern cpuop_func op_4268_11_nf;
+extern cpuop_func op_4268_11_ff;
+extern cpuop_func op_4270_11_nf;
+extern cpuop_func op_4270_11_ff;
+extern cpuop_func op_4278_11_nf;
+extern cpuop_func op_4278_11_ff;
+extern cpuop_func op_4279_11_nf;
+extern cpuop_func op_4279_11_ff;
+extern cpuop_func op_4280_11_nf;
+extern cpuop_func op_4280_11_ff;
+extern cpuop_func op_4290_11_nf;
+extern cpuop_func op_4290_11_ff;
+extern cpuop_func op_4298_11_nf;
+extern cpuop_func op_4298_11_ff;
+extern cpuop_func op_42a0_11_nf;
+extern cpuop_func op_42a0_11_ff;
+extern cpuop_func op_42a8_11_nf;
+extern cpuop_func op_42a8_11_ff;
+extern cpuop_func op_42b0_11_nf;
+extern cpuop_func op_42b0_11_ff;
+extern cpuop_func op_42b8_11_nf;
+extern cpuop_func op_42b8_11_ff;
+extern cpuop_func op_42b9_11_nf;
+extern cpuop_func op_42b9_11_ff;
+extern cpuop_func op_42c0_11_nf;
+extern cpuop_func op_42c0_11_ff;
+extern cpuop_func op_42d0_11_nf;
+extern cpuop_func op_42d0_11_ff;
+extern cpuop_func op_42d8_11_nf;
+extern cpuop_func op_42d8_11_ff;
+extern cpuop_func op_42e0_11_nf;
+extern cpuop_func op_42e0_11_ff;
+extern cpuop_func op_42e8_11_nf;
+extern cpuop_func op_42e8_11_ff;
+extern cpuop_func op_42f0_11_nf;
+extern cpuop_func op_42f0_11_ff;
+extern cpuop_func op_42f8_11_nf;
+extern cpuop_func op_42f8_11_ff;
+extern cpuop_func op_42f9_11_nf;
+extern cpuop_func op_42f9_11_ff;
+extern cpuop_func op_4400_11_nf;
+extern cpuop_func op_4400_11_ff;
+extern cpuop_func op_4410_11_nf;
+extern cpuop_func op_4410_11_ff;
+extern cpuop_func op_4418_11_nf;
+extern cpuop_func op_4418_11_ff;
+extern cpuop_func op_4420_11_nf;
+extern cpuop_func op_4420_11_ff;
+extern cpuop_func op_4428_11_nf;
+extern cpuop_func op_4428_11_ff;
+extern cpuop_func op_4430_11_nf;
+extern cpuop_func op_4430_11_ff;
+extern cpuop_func op_4438_11_nf;
+extern cpuop_func op_4438_11_ff;
+extern cpuop_func op_4439_11_nf;
+extern cpuop_func op_4439_11_ff;
+extern cpuop_func op_4440_11_nf;
+extern cpuop_func op_4440_11_ff;
+extern cpuop_func op_4450_11_nf;
+extern cpuop_func op_4450_11_ff;
+extern cpuop_func op_4458_11_nf;
+extern cpuop_func op_4458_11_ff;
+extern cpuop_func op_4460_11_nf;
+extern cpuop_func op_4460_11_ff;
+extern cpuop_func op_4468_11_nf;
+extern cpuop_func op_4468_11_ff;
+extern cpuop_func op_4470_11_nf;
+extern cpuop_func op_4470_11_ff;
+extern cpuop_func op_4478_11_nf;
+extern cpuop_func op_4478_11_ff;
+extern cpuop_func op_4479_11_nf;
+extern cpuop_func op_4479_11_ff;
+extern cpuop_func op_4480_11_nf;
+extern cpuop_func op_4480_11_ff;
+extern cpuop_func op_4490_11_nf;
+extern cpuop_func op_4490_11_ff;
+extern cpuop_func op_4498_11_nf;
+extern cpuop_func op_4498_11_ff;
+extern cpuop_func op_44a0_11_nf;
+extern cpuop_func op_44a0_11_ff;
+extern cpuop_func op_44a8_11_nf;
+extern cpuop_func op_44a8_11_ff;
+extern cpuop_func op_44b0_11_nf;
+extern cpuop_func op_44b0_11_ff;
+extern cpuop_func op_44b8_11_nf;
+extern cpuop_func op_44b8_11_ff;
+extern cpuop_func op_44b9_11_nf;
+extern cpuop_func op_44b9_11_ff;
+extern cpuop_func op_44c0_11_nf;
+extern cpuop_func op_44c0_11_ff;
+extern cpuop_func op_44d0_11_nf;
+extern cpuop_func op_44d0_11_ff;
+extern cpuop_func op_44d8_11_nf;
+extern cpuop_func op_44d8_11_ff;
+extern cpuop_func op_44e0_11_nf;
+extern cpuop_func op_44e0_11_ff;
+extern cpuop_func op_44e8_11_nf;
+extern cpuop_func op_44e8_11_ff;
+extern cpuop_func op_44f0_11_nf;
+extern cpuop_func op_44f0_11_ff;
+extern cpuop_func op_44f8_11_nf;
+extern cpuop_func op_44f8_11_ff;
+extern cpuop_func op_44f9_11_nf;
+extern cpuop_func op_44f9_11_ff;
+extern cpuop_func op_44fa_11_nf;
+extern cpuop_func op_44fa_11_ff;
+extern cpuop_func op_44fb_11_nf;
+extern cpuop_func op_44fb_11_ff;
+extern cpuop_func op_44fc_11_nf;
+extern cpuop_func op_44fc_11_ff;
+extern cpuop_func op_4600_11_nf;
+extern cpuop_func op_4600_11_ff;
+extern cpuop_func op_4610_11_nf;
+extern cpuop_func op_4610_11_ff;
+extern cpuop_func op_4618_11_nf;
+extern cpuop_func op_4618_11_ff;
+extern cpuop_func op_4620_11_nf;
+extern cpuop_func op_4620_11_ff;
+extern cpuop_func op_4628_11_nf;
+extern cpuop_func op_4628_11_ff;
+extern cpuop_func op_4630_11_nf;
+extern cpuop_func op_4630_11_ff;
+extern cpuop_func op_4638_11_nf;
+extern cpuop_func op_4638_11_ff;
+extern cpuop_func op_4639_11_nf;
+extern cpuop_func op_4639_11_ff;
+extern cpuop_func op_4640_11_nf;
+extern cpuop_func op_4640_11_ff;
+extern cpuop_func op_4650_11_nf;
+extern cpuop_func op_4650_11_ff;
+extern cpuop_func op_4658_11_nf;
+extern cpuop_func op_4658_11_ff;
+extern cpuop_func op_4660_11_nf;
+extern cpuop_func op_4660_11_ff;
+extern cpuop_func op_4668_11_nf;
+extern cpuop_func op_4668_11_ff;
+extern cpuop_func op_4670_11_nf;
+extern cpuop_func op_4670_11_ff;
+extern cpuop_func op_4678_11_nf;
+extern cpuop_func op_4678_11_ff;
+extern cpuop_func op_4679_11_nf;
+extern cpuop_func op_4679_11_ff;
+extern cpuop_func op_4680_11_nf;
+extern cpuop_func op_4680_11_ff;
+extern cpuop_func op_4690_11_nf;
+extern cpuop_func op_4690_11_ff;
+extern cpuop_func op_4698_11_nf;
+extern cpuop_func op_4698_11_ff;
+extern cpuop_func op_46a0_11_nf;
+extern cpuop_func op_46a0_11_ff;
+extern cpuop_func op_46a8_11_nf;
+extern cpuop_func op_46a8_11_ff;
+extern cpuop_func op_46b0_11_nf;
+extern cpuop_func op_46b0_11_ff;
+extern cpuop_func op_46b8_11_nf;
+extern cpuop_func op_46b8_11_ff;
+extern cpuop_func op_46b9_11_nf;
+extern cpuop_func op_46b9_11_ff;
+extern cpuop_func op_46c0_11_nf;
+extern cpuop_func op_46c0_11_ff;
+extern cpuop_func op_46d0_11_nf;
+extern cpuop_func op_46d0_11_ff;
+extern cpuop_func op_46d8_11_nf;
+extern cpuop_func op_46d8_11_ff;
+extern cpuop_func op_46e0_11_nf;
+extern cpuop_func op_46e0_11_ff;
+extern cpuop_func op_46e8_11_nf;
+extern cpuop_func op_46e8_11_ff;
+extern cpuop_func op_46f0_11_nf;
+extern cpuop_func op_46f0_11_ff;
+extern cpuop_func op_46f8_11_nf;
+extern cpuop_func op_46f8_11_ff;
+extern cpuop_func op_46f9_11_nf;
+extern cpuop_func op_46f9_11_ff;
+extern cpuop_func op_46fa_11_nf;
+extern cpuop_func op_46fa_11_ff;
+extern cpuop_func op_46fb_11_nf;
+extern cpuop_func op_46fb_11_ff;
+extern cpuop_func op_46fc_11_nf;
+extern cpuop_func op_46fc_11_ff;
+extern cpuop_func op_4800_11_nf;
+extern cpuop_func op_4800_11_ff;
+extern cpuop_func op_4810_11_nf;
+extern cpuop_func op_4810_11_ff;
+extern cpuop_func op_4818_11_nf;
+extern cpuop_func op_4818_11_ff;
+extern cpuop_func op_4820_11_nf;
+extern cpuop_func op_4820_11_ff;
+extern cpuop_func op_4828_11_nf;
+extern cpuop_func op_4828_11_ff;
+extern cpuop_func op_4830_11_nf;
+extern cpuop_func op_4830_11_ff;
+extern cpuop_func op_4838_11_nf;
+extern cpuop_func op_4838_11_ff;
+extern cpuop_func op_4839_11_nf;
+extern cpuop_func op_4839_11_ff;
+extern cpuop_func op_4840_11_nf;
+extern cpuop_func op_4840_11_ff;
+extern cpuop_func op_4850_11_nf;
+extern cpuop_func op_4850_11_ff;
+extern cpuop_func op_4868_11_nf;
+extern cpuop_func op_4868_11_ff;
+extern cpuop_func op_4870_11_nf;
+extern cpuop_func op_4870_11_ff;
+extern cpuop_func op_4878_11_nf;
+extern cpuop_func op_4878_11_ff;
+extern cpuop_func op_4879_11_nf;
+extern cpuop_func op_4879_11_ff;
+extern cpuop_func op_487a_11_nf;
+extern cpuop_func op_487a_11_ff;
+extern cpuop_func op_487b_11_nf;
+extern cpuop_func op_487b_11_ff;
+extern cpuop_func op_4880_11_nf;
+extern cpuop_func op_4880_11_ff;
+extern cpuop_func op_4890_11_nf;
+extern cpuop_func op_4890_11_ff;
+extern cpuop_func op_48a0_11_nf;
+extern cpuop_func op_48a0_11_ff;
+extern cpuop_func op_48a8_11_nf;
+extern cpuop_func op_48a8_11_ff;
+extern cpuop_func op_48b0_11_nf;
+extern cpuop_func op_48b0_11_ff;
+extern cpuop_func op_48b8_11_nf;
+extern cpuop_func op_48b8_11_ff;
+extern cpuop_func op_48b9_11_nf;
+extern cpuop_func op_48b9_11_ff;
+extern cpuop_func op_48c0_11_nf;
+extern cpuop_func op_48c0_11_ff;
+extern cpuop_func op_48d0_11_nf;
+extern cpuop_func op_48d0_11_ff;
+extern cpuop_func op_48e0_11_nf;
+extern cpuop_func op_48e0_11_ff;
+extern cpuop_func op_48e8_11_nf;
+extern cpuop_func op_48e8_11_ff;
+extern cpuop_func op_48f0_11_nf;
+extern cpuop_func op_48f0_11_ff;
+extern cpuop_func op_48f8_11_nf;
+extern cpuop_func op_48f8_11_ff;
+extern cpuop_func op_48f9_11_nf;
+extern cpuop_func op_48f9_11_ff;
+extern cpuop_func op_4a00_11_nf;
+extern cpuop_func op_4a00_11_ff;
+extern cpuop_func op_4a10_11_nf;
+extern cpuop_func op_4a10_11_ff;
+extern cpuop_func op_4a18_11_nf;
+extern cpuop_func op_4a18_11_ff;
+extern cpuop_func op_4a20_11_nf;
+extern cpuop_func op_4a20_11_ff;
+extern cpuop_func op_4a28_11_nf;
+extern cpuop_func op_4a28_11_ff;
+extern cpuop_func op_4a30_11_nf;
+extern cpuop_func op_4a30_11_ff;
+extern cpuop_func op_4a38_11_nf;
+extern cpuop_func op_4a38_11_ff;
+extern cpuop_func op_4a39_11_nf;
+extern cpuop_func op_4a39_11_ff;
+extern cpuop_func op_4a40_11_nf;
+extern cpuop_func op_4a40_11_ff;
+extern cpuop_func op_4a50_11_nf;
+extern cpuop_func op_4a50_11_ff;
+extern cpuop_func op_4a58_11_nf;
+extern cpuop_func op_4a58_11_ff;
+extern cpuop_func op_4a60_11_nf;
+extern cpuop_func op_4a60_11_ff;
+extern cpuop_func op_4a68_11_nf;
+extern cpuop_func op_4a68_11_ff;
+extern cpuop_func op_4a70_11_nf;
+extern cpuop_func op_4a70_11_ff;
+extern cpuop_func op_4a78_11_nf;
+extern cpuop_func op_4a78_11_ff;
+extern cpuop_func op_4a79_11_nf;
+extern cpuop_func op_4a79_11_ff;
+extern cpuop_func op_4a80_11_nf;
+extern cpuop_func op_4a80_11_ff;
+extern cpuop_func op_4a90_11_nf;
+extern cpuop_func op_4a90_11_ff;
+extern cpuop_func op_4a98_11_nf;
+extern cpuop_func op_4a98_11_ff;
+extern cpuop_func op_4aa0_11_nf;
+extern cpuop_func op_4aa0_11_ff;
+extern cpuop_func op_4aa8_11_nf;
+extern cpuop_func op_4aa8_11_ff;
+extern cpuop_func op_4ab0_11_nf;
+extern cpuop_func op_4ab0_11_ff;
+extern cpuop_func op_4ab8_11_nf;
+extern cpuop_func op_4ab8_11_ff;
+extern cpuop_func op_4ab9_11_nf;
+extern cpuop_func op_4ab9_11_ff;
+extern cpuop_func op_4ac0_11_nf;
+extern cpuop_func op_4ac0_11_ff;
+extern cpuop_func op_4ad0_11_nf;
+extern cpuop_func op_4ad0_11_ff;
+extern cpuop_func op_4ad8_11_nf;
+extern cpuop_func op_4ad8_11_ff;
+extern cpuop_func op_4ae0_11_nf;
+extern cpuop_func op_4ae0_11_ff;
+extern cpuop_func op_4ae8_11_nf;
+extern cpuop_func op_4ae8_11_ff;
+extern cpuop_func op_4af0_11_nf;
+extern cpuop_func op_4af0_11_ff;
+extern cpuop_func op_4af8_11_nf;
+extern cpuop_func op_4af8_11_ff;
+extern cpuop_func op_4af9_11_nf;
+extern cpuop_func op_4af9_11_ff;
+extern cpuop_func op_4c90_11_nf;
+extern cpuop_func op_4c90_11_ff;
+extern cpuop_func op_4c98_11_nf;
+extern cpuop_func op_4c98_11_ff;
+extern cpuop_func op_4ca8_11_nf;
+extern cpuop_func op_4ca8_11_ff;
+extern cpuop_func op_4cb0_11_nf;
+extern cpuop_func op_4cb0_11_ff;
+extern cpuop_func op_4cb8_11_nf;
+extern cpuop_func op_4cb8_11_ff;
+extern cpuop_func op_4cb9_11_nf;
+extern cpuop_func op_4cb9_11_ff;
+extern cpuop_func op_4cba_11_nf;
+extern cpuop_func op_4cba_11_ff;
+extern cpuop_func op_4cbb_11_nf;
+extern cpuop_func op_4cbb_11_ff;
+extern cpuop_func op_4cd0_11_nf;
+extern cpuop_func op_4cd0_11_ff;
+extern cpuop_func op_4cd8_11_nf;
+extern cpuop_func op_4cd8_11_ff;
+extern cpuop_func op_4ce8_11_nf;
+extern cpuop_func op_4ce8_11_ff;
+extern cpuop_func op_4cf0_11_nf;
+extern cpuop_func op_4cf0_11_ff;
+extern cpuop_func op_4cf8_11_nf;
+extern cpuop_func op_4cf8_11_ff;
+extern cpuop_func op_4cf9_11_nf;
+extern cpuop_func op_4cf9_11_ff;
+extern cpuop_func op_4cfa_11_nf;
+extern cpuop_func op_4cfa_11_ff;
+extern cpuop_func op_4cfb_11_nf;
+extern cpuop_func op_4cfb_11_ff;
+extern cpuop_func op_4e40_11_nf;
+extern cpuop_func op_4e40_11_ff;
+extern cpuop_func op_4e50_11_nf;
+extern cpuop_func op_4e50_11_ff;
+extern cpuop_func op_4e58_11_nf;
+extern cpuop_func op_4e58_11_ff;
+extern cpuop_func op_4e60_11_nf;
+extern cpuop_func op_4e60_11_ff;
+extern cpuop_func op_4e68_11_nf;
+extern cpuop_func op_4e68_11_ff;
+extern cpuop_func op_4e70_11_nf;
+extern cpuop_func op_4e70_11_ff;
+extern cpuop_func op_4e71_11_nf;
+extern cpuop_func op_4e71_11_ff;
+extern cpuop_func op_4e72_11_nf;
+extern cpuop_func op_4e72_11_ff;
+extern cpuop_func op_4e73_11_nf;
+extern cpuop_func op_4e73_11_ff;
+extern cpuop_func op_4e74_11_nf;
+extern cpuop_func op_4e74_11_ff;
+extern cpuop_func op_4e75_11_nf;
+extern cpuop_func op_4e75_11_ff;
+extern cpuop_func op_4e76_11_nf;
+extern cpuop_func op_4e76_11_ff;
+extern cpuop_func op_4e77_11_nf;
+extern cpuop_func op_4e77_11_ff;
+extern cpuop_func op_4e7a_11_nf;
+extern cpuop_func op_4e7a_11_ff;
+extern cpuop_func op_4e7b_11_nf;
+extern cpuop_func op_4e7b_11_ff;
+extern cpuop_func op_4e90_11_nf;
+extern cpuop_func op_4e90_11_ff;
+extern cpuop_func op_4ea8_11_nf;
+extern cpuop_func op_4ea8_11_ff;
+extern cpuop_func op_4eb0_11_nf;
+extern cpuop_func op_4eb0_11_ff;
+extern cpuop_func op_4eb8_11_nf;
+extern cpuop_func op_4eb8_11_ff;
+extern cpuop_func op_4eb9_11_nf;
+extern cpuop_func op_4eb9_11_ff;
+extern cpuop_func op_4eba_11_nf;
+extern cpuop_func op_4eba_11_ff;
+extern cpuop_func op_4ebb_11_nf;
+extern cpuop_func op_4ebb_11_ff;
+extern cpuop_func op_4ed0_11_nf;
+extern cpuop_func op_4ed0_11_ff;
+extern cpuop_func op_4ee8_11_nf;
+extern cpuop_func op_4ee8_11_ff;
+extern cpuop_func op_4ef0_11_nf;
+extern cpuop_func op_4ef0_11_ff;
+extern cpuop_func op_4ef8_11_nf;
+extern cpuop_func op_4ef8_11_ff;
+extern cpuop_func op_4ef9_11_nf;
+extern cpuop_func op_4ef9_11_ff;
+extern cpuop_func op_4efa_11_nf;
+extern cpuop_func op_4efa_11_ff;
+extern cpuop_func op_4efb_11_nf;
+extern cpuop_func op_4efb_11_ff;
+extern cpuop_func op_5000_11_nf;
+extern cpuop_func op_5000_11_ff;
+extern cpuop_func op_5010_11_nf;
+extern cpuop_func op_5010_11_ff;
+extern cpuop_func op_5018_11_nf;
+extern cpuop_func op_5018_11_ff;
+extern cpuop_func op_5020_11_nf;
+extern cpuop_func op_5020_11_ff;
+extern cpuop_func op_5028_11_nf;
+extern cpuop_func op_5028_11_ff;
+extern cpuop_func op_5030_11_nf;
+extern cpuop_func op_5030_11_ff;
+extern cpuop_func op_5038_11_nf;
+extern cpuop_func op_5038_11_ff;
+extern cpuop_func op_5039_11_nf;
+extern cpuop_func op_5039_11_ff;
+extern cpuop_func op_5040_11_nf;
+extern cpuop_func op_5040_11_ff;
+extern cpuop_func op_5048_11_nf;
+extern cpuop_func op_5048_11_ff;
+extern cpuop_func op_5050_11_nf;
+extern cpuop_func op_5050_11_ff;
+extern cpuop_func op_5058_11_nf;
+extern cpuop_func op_5058_11_ff;
+extern cpuop_func op_5060_11_nf;
+extern cpuop_func op_5060_11_ff;
+extern cpuop_func op_5068_11_nf;
+extern cpuop_func op_5068_11_ff;
+extern cpuop_func op_5070_11_nf;
+extern cpuop_func op_5070_11_ff;
+extern cpuop_func op_5078_11_nf;
+extern cpuop_func op_5078_11_ff;
+extern cpuop_func op_5079_11_nf;
+extern cpuop_func op_5079_11_ff;
+extern cpuop_func op_5080_11_nf;
+extern cpuop_func op_5080_11_ff;
+extern cpuop_func op_5088_11_nf;
+extern cpuop_func op_5088_11_ff;
+extern cpuop_func op_5090_11_nf;
+extern cpuop_func op_5090_11_ff;
+extern cpuop_func op_5098_11_nf;
+extern cpuop_func op_5098_11_ff;
+extern cpuop_func op_50a0_11_nf;
+extern cpuop_func op_50a0_11_ff;
+extern cpuop_func op_50a8_11_nf;
+extern cpuop_func op_50a8_11_ff;
+extern cpuop_func op_50b0_11_nf;
+extern cpuop_func op_50b0_11_ff;
+extern cpuop_func op_50b8_11_nf;
+extern cpuop_func op_50b8_11_ff;
+extern cpuop_func op_50b9_11_nf;
+extern cpuop_func op_50b9_11_ff;
+extern cpuop_func op_50c0_11_nf;
+extern cpuop_func op_50c0_11_ff;
+extern cpuop_func op_50c8_11_nf;
+extern cpuop_func op_50c8_11_ff;
+extern cpuop_func op_50d0_11_nf;
+extern cpuop_func op_50d0_11_ff;
+extern cpuop_func op_50d8_11_nf;
+extern cpuop_func op_50d8_11_ff;
+extern cpuop_func op_50e0_11_nf;
+extern cpuop_func op_50e0_11_ff;
+extern cpuop_func op_50e8_11_nf;
+extern cpuop_func op_50e8_11_ff;
+extern cpuop_func op_50f0_11_nf;
+extern cpuop_func op_50f0_11_ff;
+extern cpuop_func op_50f8_11_nf;
+extern cpuop_func op_50f8_11_ff;
+extern cpuop_func op_50f9_11_nf;
+extern cpuop_func op_50f9_11_ff;
+extern cpuop_func op_5100_11_nf;
+extern cpuop_func op_5100_11_ff;
+extern cpuop_func op_5110_11_nf;
+extern cpuop_func op_5110_11_ff;
+extern cpuop_func op_5118_11_nf;
+extern cpuop_func op_5118_11_ff;
+extern cpuop_func op_5120_11_nf;
+extern cpuop_func op_5120_11_ff;
+extern cpuop_func op_5128_11_nf;
+extern cpuop_func op_5128_11_ff;
+extern cpuop_func op_5130_11_nf;
+extern cpuop_func op_5130_11_ff;
+extern cpuop_func op_5138_11_nf;
+extern cpuop_func op_5138_11_ff;
+extern cpuop_func op_5139_11_nf;
+extern cpuop_func op_5139_11_ff;
+extern cpuop_func op_5140_11_nf;
+extern cpuop_func op_5140_11_ff;
+extern cpuop_func op_5148_11_nf;
+extern cpuop_func op_5148_11_ff;
+extern cpuop_func op_5150_11_nf;
+extern cpuop_func op_5150_11_ff;
+extern cpuop_func op_5158_11_nf;
+extern cpuop_func op_5158_11_ff;
+extern cpuop_func op_5160_11_nf;
+extern cpuop_func op_5160_11_ff;
+extern cpuop_func op_5168_11_nf;
+extern cpuop_func op_5168_11_ff;
+extern cpuop_func op_5170_11_nf;
+extern cpuop_func op_5170_11_ff;
+extern cpuop_func op_5178_11_nf;
+extern cpuop_func op_5178_11_ff;
+extern cpuop_func op_5179_11_nf;
+extern cpuop_func op_5179_11_ff;
+extern cpuop_func op_5180_11_nf;
+extern cpuop_func op_5180_11_ff;
+extern cpuop_func op_5188_11_nf;
+extern cpuop_func op_5188_11_ff;
+extern cpuop_func op_5190_11_nf;
+extern cpuop_func op_5190_11_ff;
+extern cpuop_func op_5198_11_nf;
+extern cpuop_func op_5198_11_ff;
+extern cpuop_func op_51a0_11_nf;
+extern cpuop_func op_51a0_11_ff;
+extern cpuop_func op_51a8_11_nf;
+extern cpuop_func op_51a8_11_ff;
+extern cpuop_func op_51b0_11_nf;
+extern cpuop_func op_51b0_11_ff;
+extern cpuop_func op_51b8_11_nf;
+extern cpuop_func op_51b8_11_ff;
+extern cpuop_func op_51b9_11_nf;
+extern cpuop_func op_51b9_11_ff;
+extern cpuop_func op_51c0_11_nf;
+extern cpuop_func op_51c0_11_ff;
+extern cpuop_func op_51c8_11_nf;
+extern cpuop_func op_51c8_11_ff;
+extern cpuop_func op_51d0_11_nf;
+extern cpuop_func op_51d0_11_ff;
+extern cpuop_func op_51d8_11_nf;
+extern cpuop_func op_51d8_11_ff;
+extern cpuop_func op_51e0_11_nf;
+extern cpuop_func op_51e0_11_ff;
+extern cpuop_func op_51e8_11_nf;
+extern cpuop_func op_51e8_11_ff;
+extern cpuop_func op_51f0_11_nf;
+extern cpuop_func op_51f0_11_ff;
+extern cpuop_func op_51f8_11_nf;
+extern cpuop_func op_51f8_11_ff;
+extern cpuop_func op_51f9_11_nf;
+extern cpuop_func op_51f9_11_ff;
+extern cpuop_func op_52c0_11_nf;
+extern cpuop_func op_52c0_11_ff;
+extern cpuop_func op_52c8_11_nf;
+extern cpuop_func op_52c8_11_ff;
+extern cpuop_func op_52d0_11_nf;
+extern cpuop_func op_52d0_11_ff;
+extern cpuop_func op_52d8_11_nf;
+extern cpuop_func op_52d8_11_ff;
+extern cpuop_func op_52e0_11_nf;
+extern cpuop_func op_52e0_11_ff;
+extern cpuop_func op_52e8_11_nf;
+extern cpuop_func op_52e8_11_ff;
+extern cpuop_func op_52f0_11_nf;
+extern cpuop_func op_52f0_11_ff;
+extern cpuop_func op_52f8_11_nf;
+extern cpuop_func op_52f8_11_ff;
+extern cpuop_func op_52f9_11_nf;
+extern cpuop_func op_52f9_11_ff;
+extern cpuop_func op_53c0_11_nf;
+extern cpuop_func op_53c0_11_ff;
+extern cpuop_func op_53c8_11_nf;
+extern cpuop_func op_53c8_11_ff;
+extern cpuop_func op_53d0_11_nf;
+extern cpuop_func op_53d0_11_ff;
+extern cpuop_func op_53d8_11_nf;
+extern cpuop_func op_53d8_11_ff;
+extern cpuop_func op_53e0_11_nf;
+extern cpuop_func op_53e0_11_ff;
+extern cpuop_func op_53e8_11_nf;
+extern cpuop_func op_53e8_11_ff;
+extern cpuop_func op_53f0_11_nf;
+extern cpuop_func op_53f0_11_ff;
+extern cpuop_func op_53f8_11_nf;
+extern cpuop_func op_53f8_11_ff;
+extern cpuop_func op_53f9_11_nf;
+extern cpuop_func op_53f9_11_ff;
+extern cpuop_func op_54c0_11_nf;
+extern cpuop_func op_54c0_11_ff;
+extern cpuop_func op_54c8_11_nf;
+extern cpuop_func op_54c8_11_ff;
+extern cpuop_func op_54d0_11_nf;
+extern cpuop_func op_54d0_11_ff;
+extern cpuop_func op_54d8_11_nf;
+extern cpuop_func op_54d8_11_ff;
+extern cpuop_func op_54e0_11_nf;
+extern cpuop_func op_54e0_11_ff;
+extern cpuop_func op_54e8_11_nf;
+extern cpuop_func op_54e8_11_ff;
+extern cpuop_func op_54f0_11_nf;
+extern cpuop_func op_54f0_11_ff;
+extern cpuop_func op_54f8_11_nf;
+extern cpuop_func op_54f8_11_ff;
+extern cpuop_func op_54f9_11_nf;
+extern cpuop_func op_54f9_11_ff;
+extern cpuop_func op_55c0_11_nf;
+extern cpuop_func op_55c0_11_ff;
+extern cpuop_func op_55c8_11_nf;
+extern cpuop_func op_55c8_11_ff;
+extern cpuop_func op_55d0_11_nf;
+extern cpuop_func op_55d0_11_ff;
+extern cpuop_func op_55d8_11_nf;
+extern cpuop_func op_55d8_11_ff;
+extern cpuop_func op_55e0_11_nf;
+extern cpuop_func op_55e0_11_ff;
+extern cpuop_func op_55e8_11_nf;
+extern cpuop_func op_55e8_11_ff;
+extern cpuop_func op_55f0_11_nf;
+extern cpuop_func op_55f0_11_ff;
+extern cpuop_func op_55f8_11_nf;
+extern cpuop_func op_55f8_11_ff;
+extern cpuop_func op_55f9_11_nf;
+extern cpuop_func op_55f9_11_ff;
+extern cpuop_func op_56c0_11_nf;
+extern cpuop_func op_56c0_11_ff;
+extern cpuop_func op_56c8_11_nf;
+extern cpuop_func op_56c8_11_ff;
+extern cpuop_func op_56d0_11_nf;
+extern cpuop_func op_56d0_11_ff;
+extern cpuop_func op_56d8_11_nf;
+extern cpuop_func op_56d8_11_ff;
+extern cpuop_func op_56e0_11_nf;
+extern cpuop_func op_56e0_11_ff;
+extern cpuop_func op_56e8_11_nf;
+extern cpuop_func op_56e8_11_ff;
+extern cpuop_func op_56f0_11_nf;
+extern cpuop_func op_56f0_11_ff;
+extern cpuop_func op_56f8_11_nf;
+extern cpuop_func op_56f8_11_ff;
+extern cpuop_func op_56f9_11_nf;
+extern cpuop_func op_56f9_11_ff;
+extern cpuop_func op_57c0_11_nf;
+extern cpuop_func op_57c0_11_ff;
+extern cpuop_func op_57c8_11_nf;
+extern cpuop_func op_57c8_11_ff;
+extern cpuop_func op_57d0_11_nf;
+extern cpuop_func op_57d0_11_ff;
+extern cpuop_func op_57d8_11_nf;
+extern cpuop_func op_57d8_11_ff;
+extern cpuop_func op_57e0_11_nf;
+extern cpuop_func op_57e0_11_ff;
+extern cpuop_func op_57e8_11_nf;
+extern cpuop_func op_57e8_11_ff;
+extern cpuop_func op_57f0_11_nf;
+extern cpuop_func op_57f0_11_ff;
+extern cpuop_func op_57f8_11_nf;
+extern cpuop_func op_57f8_11_ff;
+extern cpuop_func op_57f9_11_nf;
+extern cpuop_func op_57f9_11_ff;
+extern cpuop_func op_58c0_11_nf;
+extern cpuop_func op_58c0_11_ff;
+extern cpuop_func op_58c8_11_nf;
+extern cpuop_func op_58c8_11_ff;
+extern cpuop_func op_58d0_11_nf;
+extern cpuop_func op_58d0_11_ff;
+extern cpuop_func op_58d8_11_nf;
+extern cpuop_func op_58d8_11_ff;
+extern cpuop_func op_58e0_11_nf;
+extern cpuop_func op_58e0_11_ff;
+extern cpuop_func op_58e8_11_nf;
+extern cpuop_func op_58e8_11_ff;
+extern cpuop_func op_58f0_11_nf;
+extern cpuop_func op_58f0_11_ff;
+extern cpuop_func op_58f8_11_nf;
+extern cpuop_func op_58f8_11_ff;
+extern cpuop_func op_58f9_11_nf;
+extern cpuop_func op_58f9_11_ff;
+extern cpuop_func op_59c0_11_nf;
+extern cpuop_func op_59c0_11_ff;
+extern cpuop_func op_59c8_11_nf;
+extern cpuop_func op_59c8_11_ff;
+extern cpuop_func op_59d0_11_nf;
+extern cpuop_func op_59d0_11_ff;
+extern cpuop_func op_59d8_11_nf;
+extern cpuop_func op_59d8_11_ff;
+extern cpuop_func op_59e0_11_nf;
+extern cpuop_func op_59e0_11_ff;
+extern cpuop_func op_59e8_11_nf;
+extern cpuop_func op_59e8_11_ff;
+extern cpuop_func op_59f0_11_nf;
+extern cpuop_func op_59f0_11_ff;
+extern cpuop_func op_59f8_11_nf;
+extern cpuop_func op_59f8_11_ff;
+extern cpuop_func op_59f9_11_nf;
+extern cpuop_func op_59f9_11_ff;
+extern cpuop_func op_5ac0_11_nf;
+extern cpuop_func op_5ac0_11_ff;
+extern cpuop_func op_5ac8_11_nf;
+extern cpuop_func op_5ac8_11_ff;
+extern cpuop_func op_5ad0_11_nf;
+extern cpuop_func op_5ad0_11_ff;
+extern cpuop_func op_5ad8_11_nf;
+extern cpuop_func op_5ad8_11_ff;
+extern cpuop_func op_5ae0_11_nf;
+extern cpuop_func op_5ae0_11_ff;
+extern cpuop_func op_5ae8_11_nf;
+extern cpuop_func op_5ae8_11_ff;
+extern cpuop_func op_5af0_11_nf;
+extern cpuop_func op_5af0_11_ff;
+extern cpuop_func op_5af8_11_nf;
+extern cpuop_func op_5af8_11_ff;
+extern cpuop_func op_5af9_11_nf;
+extern cpuop_func op_5af9_11_ff;
+extern cpuop_func op_5bc0_11_nf;
+extern cpuop_func op_5bc0_11_ff;
+extern cpuop_func op_5bc8_11_nf;
+extern cpuop_func op_5bc8_11_ff;
+extern cpuop_func op_5bd0_11_nf;
+extern cpuop_func op_5bd0_11_ff;
+extern cpuop_func op_5bd8_11_nf;
+extern cpuop_func op_5bd8_11_ff;
+extern cpuop_func op_5be0_11_nf;
+extern cpuop_func op_5be0_11_ff;
+extern cpuop_func op_5be8_11_nf;
+extern cpuop_func op_5be8_11_ff;
+extern cpuop_func op_5bf0_11_nf;
+extern cpuop_func op_5bf0_11_ff;
+extern cpuop_func op_5bf8_11_nf;
+extern cpuop_func op_5bf8_11_ff;
+extern cpuop_func op_5bf9_11_nf;
+extern cpuop_func op_5bf9_11_ff;
+extern cpuop_func op_5cc0_11_nf;
+extern cpuop_func op_5cc0_11_ff;
+extern cpuop_func op_5cc8_11_nf;
+extern cpuop_func op_5cc8_11_ff;
+extern cpuop_func op_5cd0_11_nf;
+extern cpuop_func op_5cd0_11_ff;
+extern cpuop_func op_5cd8_11_nf;
+extern cpuop_func op_5cd8_11_ff;
+extern cpuop_func op_5ce0_11_nf;
+extern cpuop_func op_5ce0_11_ff;
+extern cpuop_func op_5ce8_11_nf;
+extern cpuop_func op_5ce8_11_ff;
+extern cpuop_func op_5cf0_11_nf;
+extern cpuop_func op_5cf0_11_ff;
+extern cpuop_func op_5cf8_11_nf;
+extern cpuop_func op_5cf8_11_ff;
+extern cpuop_func op_5cf9_11_nf;
+extern cpuop_func op_5cf9_11_ff;
+extern cpuop_func op_5dc0_11_nf;
+extern cpuop_func op_5dc0_11_ff;
+extern cpuop_func op_5dc8_11_nf;
+extern cpuop_func op_5dc8_11_ff;
+extern cpuop_func op_5dd0_11_nf;
+extern cpuop_func op_5dd0_11_ff;
+extern cpuop_func op_5dd8_11_nf;
+extern cpuop_func op_5dd8_11_ff;
+extern cpuop_func op_5de0_11_nf;
+extern cpuop_func op_5de0_11_ff;
+extern cpuop_func op_5de8_11_nf;
+extern cpuop_func op_5de8_11_ff;
+extern cpuop_func op_5df0_11_nf;
+extern cpuop_func op_5df0_11_ff;
+extern cpuop_func op_5df8_11_nf;
+extern cpuop_func op_5df8_11_ff;
+extern cpuop_func op_5df9_11_nf;
+extern cpuop_func op_5df9_11_ff;
+extern cpuop_func op_5ec0_11_nf;
+extern cpuop_func op_5ec0_11_ff;
+extern cpuop_func op_5ec8_11_nf;
+extern cpuop_func op_5ec8_11_ff;
+extern cpuop_func op_5ed0_11_nf;
+extern cpuop_func op_5ed0_11_ff;
+extern cpuop_func op_5ed8_11_nf;
+extern cpuop_func op_5ed8_11_ff;
+extern cpuop_func op_5ee0_11_nf;
+extern cpuop_func op_5ee0_11_ff;
+extern cpuop_func op_5ee8_11_nf;
+extern cpuop_func op_5ee8_11_ff;
+extern cpuop_func op_5ef0_11_nf;
+extern cpuop_func op_5ef0_11_ff;
+extern cpuop_func op_5ef8_11_nf;
+extern cpuop_func op_5ef8_11_ff;
+extern cpuop_func op_5ef9_11_nf;
+extern cpuop_func op_5ef9_11_ff;
+extern cpuop_func op_5fc0_11_nf;
+extern cpuop_func op_5fc0_11_ff;
+extern cpuop_func op_5fc8_11_nf;
+extern cpuop_func op_5fc8_11_ff;
+extern cpuop_func op_5fd0_11_nf;
+extern cpuop_func op_5fd0_11_ff;
+extern cpuop_func op_5fd8_11_nf;
+extern cpuop_func op_5fd8_11_ff;
+extern cpuop_func op_5fe0_11_nf;
+extern cpuop_func op_5fe0_11_ff;
+extern cpuop_func op_5fe8_11_nf;
+extern cpuop_func op_5fe8_11_ff;
+extern cpuop_func op_5ff0_11_nf;
+extern cpuop_func op_5ff0_11_ff;
+extern cpuop_func op_5ff8_11_nf;
+extern cpuop_func op_5ff8_11_ff;
+extern cpuop_func op_5ff9_11_nf;
+extern cpuop_func op_5ff9_11_ff;
+extern cpuop_func op_6000_11_nf;
+extern cpuop_func op_6000_11_ff;
+extern cpuop_func op_6001_11_nf;
+extern cpuop_func op_6001_11_ff;
+extern cpuop_func op_60ff_11_nf;
+extern cpuop_func op_60ff_11_ff;
+extern cpuop_func op_6100_11_nf;
+extern cpuop_func op_6100_11_ff;
+extern cpuop_func op_6101_11_nf;
+extern cpuop_func op_6101_11_ff;
+extern cpuop_func op_61ff_11_nf;
+extern cpuop_func op_61ff_11_ff;
+extern cpuop_func op_6200_11_nf;
+extern cpuop_func op_6200_11_ff;
+extern cpuop_func op_6201_11_nf;
+extern cpuop_func op_6201_11_ff;
+extern cpuop_func op_62ff_11_nf;
+extern cpuop_func op_62ff_11_ff;
+extern cpuop_func op_6300_11_nf;
+extern cpuop_func op_6300_11_ff;
+extern cpuop_func op_6301_11_nf;
+extern cpuop_func op_6301_11_ff;
+extern cpuop_func op_63ff_11_nf;
+extern cpuop_func op_63ff_11_ff;
+extern cpuop_func op_6400_11_nf;
+extern cpuop_func op_6400_11_ff;
+extern cpuop_func op_6401_11_nf;
+extern cpuop_func op_6401_11_ff;
+extern cpuop_func op_64ff_11_nf;
+extern cpuop_func op_64ff_11_ff;
+extern cpuop_func op_6500_11_nf;
+extern cpuop_func op_6500_11_ff;
+extern cpuop_func op_6501_11_nf;
+extern cpuop_func op_6501_11_ff;
+extern cpuop_func op_65ff_11_nf;
+extern cpuop_func op_65ff_11_ff;
+extern cpuop_func op_6600_11_nf;
+extern cpuop_func op_6600_11_ff;
+extern cpuop_func op_6601_11_nf;
+extern cpuop_func op_6601_11_ff;
+extern cpuop_func op_66ff_11_nf;
+extern cpuop_func op_66ff_11_ff;
+extern cpuop_func op_6700_11_nf;
+extern cpuop_func op_6700_11_ff;
+extern cpuop_func op_6701_11_nf;
+extern cpuop_func op_6701_11_ff;
+extern cpuop_func op_67ff_11_nf;
+extern cpuop_func op_67ff_11_ff;
+extern cpuop_func op_6800_11_nf;
+extern cpuop_func op_6800_11_ff;
+extern cpuop_func op_6801_11_nf;
+extern cpuop_func op_6801_11_ff;
+extern cpuop_func op_68ff_11_nf;
+extern cpuop_func op_68ff_11_ff;
+extern cpuop_func op_6900_11_nf;
+extern cpuop_func op_6900_11_ff;
+extern cpuop_func op_6901_11_nf;
+extern cpuop_func op_6901_11_ff;
+extern cpuop_func op_69ff_11_nf;
+extern cpuop_func op_69ff_11_ff;
+extern cpuop_func op_6a00_11_nf;
+extern cpuop_func op_6a00_11_ff;
+extern cpuop_func op_6a01_11_nf;
+extern cpuop_func op_6a01_11_ff;
+extern cpuop_func op_6aff_11_nf;
+extern cpuop_func op_6aff_11_ff;
+extern cpuop_func op_6b00_11_nf;
+extern cpuop_func op_6b00_11_ff;
+extern cpuop_func op_6b01_11_nf;
+extern cpuop_func op_6b01_11_ff;
+extern cpuop_func op_6bff_11_nf;
+extern cpuop_func op_6bff_11_ff;
+extern cpuop_func op_6c00_11_nf;
+extern cpuop_func op_6c00_11_ff;
+extern cpuop_func op_6c01_11_nf;
+extern cpuop_func op_6c01_11_ff;
+extern cpuop_func op_6cff_11_nf;
+extern cpuop_func op_6cff_11_ff;
+extern cpuop_func op_6d00_11_nf;
+extern cpuop_func op_6d00_11_ff;
+extern cpuop_func op_6d01_11_nf;
+extern cpuop_func op_6d01_11_ff;
+extern cpuop_func op_6dff_11_nf;
+extern cpuop_func op_6dff_11_ff;
+extern cpuop_func op_6e00_11_nf;
+extern cpuop_func op_6e00_11_ff;
+extern cpuop_func op_6e01_11_nf;
+extern cpuop_func op_6e01_11_ff;
+extern cpuop_func op_6eff_11_nf;
+extern cpuop_func op_6eff_11_ff;
+extern cpuop_func op_6f00_11_nf;
+extern cpuop_func op_6f00_11_ff;
+extern cpuop_func op_6f01_11_nf;
+extern cpuop_func op_6f01_11_ff;
+extern cpuop_func op_6fff_11_nf;
+extern cpuop_func op_6fff_11_ff;
+extern cpuop_func op_7000_11_nf;
+extern cpuop_func op_7000_11_ff;
+extern cpuop_func op_8000_11_nf;
+extern cpuop_func op_8000_11_ff;
+extern cpuop_func op_8010_11_nf;
+extern cpuop_func op_8010_11_ff;
+extern cpuop_func op_8018_11_nf;
+extern cpuop_func op_8018_11_ff;
+extern cpuop_func op_8020_11_nf;
+extern cpuop_func op_8020_11_ff;
+extern cpuop_func op_8028_11_nf;
+extern cpuop_func op_8028_11_ff;
+extern cpuop_func op_8030_11_nf;
+extern cpuop_func op_8030_11_ff;
+extern cpuop_func op_8038_11_nf;
+extern cpuop_func op_8038_11_ff;
+extern cpuop_func op_8039_11_nf;
+extern cpuop_func op_8039_11_ff;
+extern cpuop_func op_803a_11_nf;
+extern cpuop_func op_803a_11_ff;
+extern cpuop_func op_803b_11_nf;
+extern cpuop_func op_803b_11_ff;
+extern cpuop_func op_803c_11_nf;
+extern cpuop_func op_803c_11_ff;
+extern cpuop_func op_8040_11_nf;
+extern cpuop_func op_8040_11_ff;
+extern cpuop_func op_8050_11_nf;
+extern cpuop_func op_8050_11_ff;
+extern cpuop_func op_8058_11_nf;
+extern cpuop_func op_8058_11_ff;
+extern cpuop_func op_8060_11_nf;
+extern cpuop_func op_8060_11_ff;
+extern cpuop_func op_8068_11_nf;
+extern cpuop_func op_8068_11_ff;
+extern cpuop_func op_8070_11_nf;
+extern cpuop_func op_8070_11_ff;
+extern cpuop_func op_8078_11_nf;
+extern cpuop_func op_8078_11_ff;
+extern cpuop_func op_8079_11_nf;
+extern cpuop_func op_8079_11_ff;
+extern cpuop_func op_807a_11_nf;
+extern cpuop_func op_807a_11_ff;
+extern cpuop_func op_807b_11_nf;
+extern cpuop_func op_807b_11_ff;
+extern cpuop_func op_807c_11_nf;
+extern cpuop_func op_807c_11_ff;
+extern cpuop_func op_8080_11_nf;
+extern cpuop_func op_8080_11_ff;
+extern cpuop_func op_8090_11_nf;
+extern cpuop_func op_8090_11_ff;
+extern cpuop_func op_8098_11_nf;
+extern cpuop_func op_8098_11_ff;
+extern cpuop_func op_80a0_11_nf;
+extern cpuop_func op_80a0_11_ff;
+extern cpuop_func op_80a8_11_nf;
+extern cpuop_func op_80a8_11_ff;
+extern cpuop_func op_80b0_11_nf;
+extern cpuop_func op_80b0_11_ff;
+extern cpuop_func op_80b8_11_nf;
+extern cpuop_func op_80b8_11_ff;
+extern cpuop_func op_80b9_11_nf;
+extern cpuop_func op_80b9_11_ff;
+extern cpuop_func op_80ba_11_nf;
+extern cpuop_func op_80ba_11_ff;
+extern cpuop_func op_80bb_11_nf;
+extern cpuop_func op_80bb_11_ff;
+extern cpuop_func op_80bc_11_nf;
+extern cpuop_func op_80bc_11_ff;
+extern cpuop_func op_80c0_11_nf;
+extern cpuop_func op_80c0_11_ff;
+extern cpuop_func op_80d0_11_nf;
+extern cpuop_func op_80d0_11_ff;
+extern cpuop_func op_80d8_11_nf;
+extern cpuop_func op_80d8_11_ff;
+extern cpuop_func op_80e0_11_nf;
+extern cpuop_func op_80e0_11_ff;
+extern cpuop_func op_80e8_11_nf;
+extern cpuop_func op_80e8_11_ff;
+extern cpuop_func op_80f0_11_nf;
+extern cpuop_func op_80f0_11_ff;
+extern cpuop_func op_80f8_11_nf;
+extern cpuop_func op_80f8_11_ff;
+extern cpuop_func op_80f9_11_nf;
+extern cpuop_func op_80f9_11_ff;
+extern cpuop_func op_80fa_11_nf;
+extern cpuop_func op_80fa_11_ff;
+extern cpuop_func op_80fb_11_nf;
+extern cpuop_func op_80fb_11_ff;
+extern cpuop_func op_80fc_11_nf;
+extern cpuop_func op_80fc_11_ff;
+extern cpuop_func op_8100_11_nf;
+extern cpuop_func op_8100_11_ff;
+extern cpuop_func op_8108_11_nf;
+extern cpuop_func op_8108_11_ff;
+extern cpuop_func op_8110_11_nf;
+extern cpuop_func op_8110_11_ff;
+extern cpuop_func op_8118_11_nf;
+extern cpuop_func op_8118_11_ff;
+extern cpuop_func op_8120_11_nf;
+extern cpuop_func op_8120_11_ff;
+extern cpuop_func op_8128_11_nf;
+extern cpuop_func op_8128_11_ff;
+extern cpuop_func op_8130_11_nf;
+extern cpuop_func op_8130_11_ff;
+extern cpuop_func op_8138_11_nf;
+extern cpuop_func op_8138_11_ff;
+extern cpuop_func op_8139_11_nf;
+extern cpuop_func op_8139_11_ff;
+extern cpuop_func op_8150_11_nf;
+extern cpuop_func op_8150_11_ff;
+extern cpuop_func op_8158_11_nf;
+extern cpuop_func op_8158_11_ff;
+extern cpuop_func op_8160_11_nf;
+extern cpuop_func op_8160_11_ff;
+extern cpuop_func op_8168_11_nf;
+extern cpuop_func op_8168_11_ff;
+extern cpuop_func op_8170_11_nf;
+extern cpuop_func op_8170_11_ff;
+extern cpuop_func op_8178_11_nf;
+extern cpuop_func op_8178_11_ff;
+extern cpuop_func op_8179_11_nf;
+extern cpuop_func op_8179_11_ff;
+extern cpuop_func op_8190_11_nf;
+extern cpuop_func op_8190_11_ff;
+extern cpuop_func op_8198_11_nf;
+extern cpuop_func op_8198_11_ff;
+extern cpuop_func op_81a0_11_nf;
+extern cpuop_func op_81a0_11_ff;
+extern cpuop_func op_81a8_11_nf;
+extern cpuop_func op_81a8_11_ff;
+extern cpuop_func op_81b0_11_nf;
+extern cpuop_func op_81b0_11_ff;
+extern cpuop_func op_81b8_11_nf;
+extern cpuop_func op_81b8_11_ff;
+extern cpuop_func op_81b9_11_nf;
+extern cpuop_func op_81b9_11_ff;
+extern cpuop_func op_81c0_11_nf;
+extern cpuop_func op_81c0_11_ff;
+extern cpuop_func op_81d0_11_nf;
+extern cpuop_func op_81d0_11_ff;
+extern cpuop_func op_81d8_11_nf;
+extern cpuop_func op_81d8_11_ff;
+extern cpuop_func op_81e0_11_nf;
+extern cpuop_func op_81e0_11_ff;
+extern cpuop_func op_81e8_11_nf;
+extern cpuop_func op_81e8_11_ff;
+extern cpuop_func op_81f0_11_nf;
+extern cpuop_func op_81f0_11_ff;
+extern cpuop_func op_81f8_11_nf;
+extern cpuop_func op_81f8_11_ff;
+extern cpuop_func op_81f9_11_nf;
+extern cpuop_func op_81f9_11_ff;
+extern cpuop_func op_81fa_11_nf;
+extern cpuop_func op_81fa_11_ff;
+extern cpuop_func op_81fb_11_nf;
+extern cpuop_func op_81fb_11_ff;
+extern cpuop_func op_81fc_11_nf;
+extern cpuop_func op_81fc_11_ff;
+extern cpuop_func op_9000_11_nf;
+extern cpuop_func op_9000_11_ff;
+extern cpuop_func op_9010_11_nf;
+extern cpuop_func op_9010_11_ff;
+extern cpuop_func op_9018_11_nf;
+extern cpuop_func op_9018_11_ff;
+extern cpuop_func op_9020_11_nf;
+extern cpuop_func op_9020_11_ff;
+extern cpuop_func op_9028_11_nf;
+extern cpuop_func op_9028_11_ff;
+extern cpuop_func op_9030_11_nf;
+extern cpuop_func op_9030_11_ff;
+extern cpuop_func op_9038_11_nf;
+extern cpuop_func op_9038_11_ff;
+extern cpuop_func op_9039_11_nf;
+extern cpuop_func op_9039_11_ff;
+extern cpuop_func op_903a_11_nf;
+extern cpuop_func op_903a_11_ff;
+extern cpuop_func op_903b_11_nf;
+extern cpuop_func op_903b_11_ff;
+extern cpuop_func op_903c_11_nf;
+extern cpuop_func op_903c_11_ff;
+extern cpuop_func op_9040_11_nf;
+extern cpuop_func op_9040_11_ff;
+extern cpuop_func op_9048_11_nf;
+extern cpuop_func op_9048_11_ff;
+extern cpuop_func op_9050_11_nf;
+extern cpuop_func op_9050_11_ff;
+extern cpuop_func op_9058_11_nf;
+extern cpuop_func op_9058_11_ff;
+extern cpuop_func op_9060_11_nf;
+extern cpuop_func op_9060_11_ff;
+extern cpuop_func op_9068_11_nf;
+extern cpuop_func op_9068_11_ff;
+extern cpuop_func op_9070_11_nf;
+extern cpuop_func op_9070_11_ff;
+extern cpuop_func op_9078_11_nf;
+extern cpuop_func op_9078_11_ff;
+extern cpuop_func op_9079_11_nf;
+extern cpuop_func op_9079_11_ff;
+extern cpuop_func op_907a_11_nf;
+extern cpuop_func op_907a_11_ff;
+extern cpuop_func op_907b_11_nf;
+extern cpuop_func op_907b_11_ff;
+extern cpuop_func op_907c_11_nf;
+extern cpuop_func op_907c_11_ff;
+extern cpuop_func op_9080_11_nf;
+extern cpuop_func op_9080_11_ff;
+extern cpuop_func op_9088_11_nf;
+extern cpuop_func op_9088_11_ff;
+extern cpuop_func op_9090_11_nf;
+extern cpuop_func op_9090_11_ff;
+extern cpuop_func op_9098_11_nf;
+extern cpuop_func op_9098_11_ff;
+extern cpuop_func op_90a0_11_nf;
+extern cpuop_func op_90a0_11_ff;
+extern cpuop_func op_90a8_11_nf;
+extern cpuop_func op_90a8_11_ff;
+extern cpuop_func op_90b0_11_nf;
+extern cpuop_func op_90b0_11_ff;
+extern cpuop_func op_90b8_11_nf;
+extern cpuop_func op_90b8_11_ff;
+extern cpuop_func op_90b9_11_nf;
+extern cpuop_func op_90b9_11_ff;
+extern cpuop_func op_90ba_11_nf;
+extern cpuop_func op_90ba_11_ff;
+extern cpuop_func op_90bb_11_nf;
+extern cpuop_func op_90bb_11_ff;
+extern cpuop_func op_90bc_11_nf;
+extern cpuop_func op_90bc_11_ff;
+extern cpuop_func op_90c0_11_nf;
+extern cpuop_func op_90c0_11_ff;
+extern cpuop_func op_90c8_11_nf;
+extern cpuop_func op_90c8_11_ff;
+extern cpuop_func op_90d0_11_nf;
+extern cpuop_func op_90d0_11_ff;
+extern cpuop_func op_90d8_11_nf;
+extern cpuop_func op_90d8_11_ff;
+extern cpuop_func op_90e0_11_nf;
+extern cpuop_func op_90e0_11_ff;
+extern cpuop_func op_90e8_11_nf;
+extern cpuop_func op_90e8_11_ff;
+extern cpuop_func op_90f0_11_nf;
+extern cpuop_func op_90f0_11_ff;
+extern cpuop_func op_90f8_11_nf;
+extern cpuop_func op_90f8_11_ff;
+extern cpuop_func op_90f9_11_nf;
+extern cpuop_func op_90f9_11_ff;
+extern cpuop_func op_90fa_11_nf;
+extern cpuop_func op_90fa_11_ff;
+extern cpuop_func op_90fb_11_nf;
+extern cpuop_func op_90fb_11_ff;
+extern cpuop_func op_90fc_11_nf;
+extern cpuop_func op_90fc_11_ff;
+extern cpuop_func op_9100_11_nf;
+extern cpuop_func op_9100_11_ff;
+extern cpuop_func op_9108_11_nf;
+extern cpuop_func op_9108_11_ff;
+extern cpuop_func op_9110_11_nf;
+extern cpuop_func op_9110_11_ff;
+extern cpuop_func op_9118_11_nf;
+extern cpuop_func op_9118_11_ff;
+extern cpuop_func op_9120_11_nf;
+extern cpuop_func op_9120_11_ff;
+extern cpuop_func op_9128_11_nf;
+extern cpuop_func op_9128_11_ff;
+extern cpuop_func op_9130_11_nf;
+extern cpuop_func op_9130_11_ff;
+extern cpuop_func op_9138_11_nf;
+extern cpuop_func op_9138_11_ff;
+extern cpuop_func op_9139_11_nf;
+extern cpuop_func op_9139_11_ff;
+extern cpuop_func op_9140_11_nf;
+extern cpuop_func op_9140_11_ff;
+extern cpuop_func op_9148_11_nf;
+extern cpuop_func op_9148_11_ff;
+extern cpuop_func op_9150_11_nf;
+extern cpuop_func op_9150_11_ff;
+extern cpuop_func op_9158_11_nf;
+extern cpuop_func op_9158_11_ff;
+extern cpuop_func op_9160_11_nf;
+extern cpuop_func op_9160_11_ff;
+extern cpuop_func op_9168_11_nf;
+extern cpuop_func op_9168_11_ff;
+extern cpuop_func op_9170_11_nf;
+extern cpuop_func op_9170_11_ff;
+extern cpuop_func op_9178_11_nf;
+extern cpuop_func op_9178_11_ff;
+extern cpuop_func op_9179_11_nf;
+extern cpuop_func op_9179_11_ff;
+extern cpuop_func op_9180_11_nf;
+extern cpuop_func op_9180_11_ff;
+extern cpuop_func op_9188_11_nf;
+extern cpuop_func op_9188_11_ff;
+extern cpuop_func op_9190_11_nf;
+extern cpuop_func op_9190_11_ff;
+extern cpuop_func op_9198_11_nf;
+extern cpuop_func op_9198_11_ff;
+extern cpuop_func op_91a0_11_nf;
+extern cpuop_func op_91a0_11_ff;
+extern cpuop_func op_91a8_11_nf;
+extern cpuop_func op_91a8_11_ff;
+extern cpuop_func op_91b0_11_nf;
+extern cpuop_func op_91b0_11_ff;
+extern cpuop_func op_91b8_11_nf;
+extern cpuop_func op_91b8_11_ff;
+extern cpuop_func op_91b9_11_nf;
+extern cpuop_func op_91b9_11_ff;
+extern cpuop_func op_91c0_11_nf;
+extern cpuop_func op_91c0_11_ff;
+extern cpuop_func op_91c8_11_nf;
+extern cpuop_func op_91c8_11_ff;
+extern cpuop_func op_91d0_11_nf;
+extern cpuop_func op_91d0_11_ff;
+extern cpuop_func op_91d8_11_nf;
+extern cpuop_func op_91d8_11_ff;
+extern cpuop_func op_91e0_11_nf;
+extern cpuop_func op_91e0_11_ff;
+extern cpuop_func op_91e8_11_nf;
+extern cpuop_func op_91e8_11_ff;
+extern cpuop_func op_91f0_11_nf;
+extern cpuop_func op_91f0_11_ff;
+extern cpuop_func op_91f8_11_nf;
+extern cpuop_func op_91f8_11_ff;
+extern cpuop_func op_91f9_11_nf;
+extern cpuop_func op_91f9_11_ff;
+extern cpuop_func op_91fa_11_nf;
+extern cpuop_func op_91fa_11_ff;
+extern cpuop_func op_91fb_11_nf;
+extern cpuop_func op_91fb_11_ff;
+extern cpuop_func op_91fc_11_nf;
+extern cpuop_func op_91fc_11_ff;
+extern cpuop_func op_b000_11_nf;
+extern cpuop_func op_b000_11_ff;
+extern cpuop_func op_b010_11_nf;
+extern cpuop_func op_b010_11_ff;
+extern cpuop_func op_b018_11_nf;
+extern cpuop_func op_b018_11_ff;
+extern cpuop_func op_b020_11_nf;
+extern cpuop_func op_b020_11_ff;
+extern cpuop_func op_b028_11_nf;
+extern cpuop_func op_b028_11_ff;
+extern cpuop_func op_b030_11_nf;
+extern cpuop_func op_b030_11_ff;
+extern cpuop_func op_b038_11_nf;
+extern cpuop_func op_b038_11_ff;
+extern cpuop_func op_b039_11_nf;
+extern cpuop_func op_b039_11_ff;
+extern cpuop_func op_b03a_11_nf;
+extern cpuop_func op_b03a_11_ff;
+extern cpuop_func op_b03b_11_nf;
+extern cpuop_func op_b03b_11_ff;
+extern cpuop_func op_b03c_11_nf;
+extern cpuop_func op_b03c_11_ff;
+extern cpuop_func op_b040_11_nf;
+extern cpuop_func op_b040_11_ff;
+extern cpuop_func op_b048_11_nf;
+extern cpuop_func op_b048_11_ff;
+extern cpuop_func op_b050_11_nf;
+extern cpuop_func op_b050_11_ff;
+extern cpuop_func op_b058_11_nf;
+extern cpuop_func op_b058_11_ff;
+extern cpuop_func op_b060_11_nf;
+extern cpuop_func op_b060_11_ff;
+extern cpuop_func op_b068_11_nf;
+extern cpuop_func op_b068_11_ff;
+extern cpuop_func op_b070_11_nf;
+extern cpuop_func op_b070_11_ff;
+extern cpuop_func op_b078_11_nf;
+extern cpuop_func op_b078_11_ff;
+extern cpuop_func op_b079_11_nf;
+extern cpuop_func op_b079_11_ff;
+extern cpuop_func op_b07a_11_nf;
+extern cpuop_func op_b07a_11_ff;
+extern cpuop_func op_b07b_11_nf;
+extern cpuop_func op_b07b_11_ff;
+extern cpuop_func op_b07c_11_nf;
+extern cpuop_func op_b07c_11_ff;
+extern cpuop_func op_b080_11_nf;
+extern cpuop_func op_b080_11_ff;
+extern cpuop_func op_b088_11_nf;
+extern cpuop_func op_b088_11_ff;
+extern cpuop_func op_b090_11_nf;
+extern cpuop_func op_b090_11_ff;
+extern cpuop_func op_b098_11_nf;
+extern cpuop_func op_b098_11_ff;
+extern cpuop_func op_b0a0_11_nf;
+extern cpuop_func op_b0a0_11_ff;
+extern cpuop_func op_b0a8_11_nf;
+extern cpuop_func op_b0a8_11_ff;
+extern cpuop_func op_b0b0_11_nf;
+extern cpuop_func op_b0b0_11_ff;
+extern cpuop_func op_b0b8_11_nf;
+extern cpuop_func op_b0b8_11_ff;
+extern cpuop_func op_b0b9_11_nf;
+extern cpuop_func op_b0b9_11_ff;
+extern cpuop_func op_b0ba_11_nf;
+extern cpuop_func op_b0ba_11_ff;
+extern cpuop_func op_b0bb_11_nf;
+extern cpuop_func op_b0bb_11_ff;
+extern cpuop_func op_b0bc_11_nf;
+extern cpuop_func op_b0bc_11_ff;
+extern cpuop_func op_b0c0_11_nf;
+extern cpuop_func op_b0c0_11_ff;
+extern cpuop_func op_b0c8_11_nf;
+extern cpuop_func op_b0c8_11_ff;
+extern cpuop_func op_b0d0_11_nf;
+extern cpuop_func op_b0d0_11_ff;
+extern cpuop_func op_b0d8_11_nf;
+extern cpuop_func op_b0d8_11_ff;
+extern cpuop_func op_b0e0_11_nf;
+extern cpuop_func op_b0e0_11_ff;
+extern cpuop_func op_b0e8_11_nf;
+extern cpuop_func op_b0e8_11_ff;
+extern cpuop_func op_b0f0_11_nf;
+extern cpuop_func op_b0f0_11_ff;
+extern cpuop_func op_b0f8_11_nf;
+extern cpuop_func op_b0f8_11_ff;
+extern cpuop_func op_b0f9_11_nf;
+extern cpuop_func op_b0f9_11_ff;
+extern cpuop_func op_b0fa_11_nf;
+extern cpuop_func op_b0fa_11_ff;
+extern cpuop_func op_b0fb_11_nf;
+extern cpuop_func op_b0fb_11_ff;
+extern cpuop_func op_b0fc_11_nf;
+extern cpuop_func op_b0fc_11_ff;
+extern cpuop_func op_b100_11_nf;
+extern cpuop_func op_b100_11_ff;
+extern cpuop_func op_b108_11_nf;
+extern cpuop_func op_b108_11_ff;
+extern cpuop_func op_b110_11_nf;
+extern cpuop_func op_b110_11_ff;
+extern cpuop_func op_b118_11_nf;
+extern cpuop_func op_b118_11_ff;
+extern cpuop_func op_b120_11_nf;
+extern cpuop_func op_b120_11_ff;
+extern cpuop_func op_b128_11_nf;
+extern cpuop_func op_b128_11_ff;
+extern cpuop_func op_b130_11_nf;
+extern cpuop_func op_b130_11_ff;
+extern cpuop_func op_b138_11_nf;
+extern cpuop_func op_b138_11_ff;
+extern cpuop_func op_b139_11_nf;
+extern cpuop_func op_b139_11_ff;
+extern cpuop_func op_b140_11_nf;
+extern cpuop_func op_b140_11_ff;
+extern cpuop_func op_b148_11_nf;
+extern cpuop_func op_b148_11_ff;
+extern cpuop_func op_b150_11_nf;
+extern cpuop_func op_b150_11_ff;
+extern cpuop_func op_b158_11_nf;
+extern cpuop_func op_b158_11_ff;
+extern cpuop_func op_b160_11_nf;
+extern cpuop_func op_b160_11_ff;
+extern cpuop_func op_b168_11_nf;
+extern cpuop_func op_b168_11_ff;
+extern cpuop_func op_b170_11_nf;
+extern cpuop_func op_b170_11_ff;
+extern cpuop_func op_b178_11_nf;
+extern cpuop_func op_b178_11_ff;
+extern cpuop_func op_b179_11_nf;
+extern cpuop_func op_b179_11_ff;
+extern cpuop_func op_b180_11_nf;
+extern cpuop_func op_b180_11_ff;
+extern cpuop_func op_b188_11_nf;
+extern cpuop_func op_b188_11_ff;
+extern cpuop_func op_b190_11_nf;
+extern cpuop_func op_b190_11_ff;
+extern cpuop_func op_b198_11_nf;
+extern cpuop_func op_b198_11_ff;
+extern cpuop_func op_b1a0_11_nf;
+extern cpuop_func op_b1a0_11_ff;
+extern cpuop_func op_b1a8_11_nf;
+extern cpuop_func op_b1a8_11_ff;
+extern cpuop_func op_b1b0_11_nf;
+extern cpuop_func op_b1b0_11_ff;
+extern cpuop_func op_b1b8_11_nf;
+extern cpuop_func op_b1b8_11_ff;
+extern cpuop_func op_b1b9_11_nf;
+extern cpuop_func op_b1b9_11_ff;
+extern cpuop_func op_b1c0_11_nf;
+extern cpuop_func op_b1c0_11_ff;
+extern cpuop_func op_b1c8_11_nf;
+extern cpuop_func op_b1c8_11_ff;
+extern cpuop_func op_b1d0_11_nf;
+extern cpuop_func op_b1d0_11_ff;
+extern cpuop_func op_b1d8_11_nf;
+extern cpuop_func op_b1d8_11_ff;
+extern cpuop_func op_b1e0_11_nf;
+extern cpuop_func op_b1e0_11_ff;
+extern cpuop_func op_b1e8_11_nf;
+extern cpuop_func op_b1e8_11_ff;
+extern cpuop_func op_b1f0_11_nf;
+extern cpuop_func op_b1f0_11_ff;
+extern cpuop_func op_b1f8_11_nf;
+extern cpuop_func op_b1f8_11_ff;
+extern cpuop_func op_b1f9_11_nf;
+extern cpuop_func op_b1f9_11_ff;
+extern cpuop_func op_b1fa_11_nf;
+extern cpuop_func op_b1fa_11_ff;
+extern cpuop_func op_b1fb_11_nf;
+extern cpuop_func op_b1fb_11_ff;
+extern cpuop_func op_b1fc_11_nf;
+extern cpuop_func op_b1fc_11_ff;
+extern cpuop_func op_c000_11_nf;
+extern cpuop_func op_c000_11_ff;
+extern cpuop_func op_c010_11_nf;
+extern cpuop_func op_c010_11_ff;
+extern cpuop_func op_c018_11_nf;
+extern cpuop_func op_c018_11_ff;
+extern cpuop_func op_c020_11_nf;
+extern cpuop_func op_c020_11_ff;
+extern cpuop_func op_c028_11_nf;
+extern cpuop_func op_c028_11_ff;
+extern cpuop_func op_c030_11_nf;
+extern cpuop_func op_c030_11_ff;
+extern cpuop_func op_c038_11_nf;
+extern cpuop_func op_c038_11_ff;
+extern cpuop_func op_c039_11_nf;
+extern cpuop_func op_c039_11_ff;
+extern cpuop_func op_c03a_11_nf;
+extern cpuop_func op_c03a_11_ff;
+extern cpuop_func op_c03b_11_nf;
+extern cpuop_func op_c03b_11_ff;
+extern cpuop_func op_c03c_11_nf;
+extern cpuop_func op_c03c_11_ff;
+extern cpuop_func op_c040_11_nf;
+extern cpuop_func op_c040_11_ff;
+extern cpuop_func op_c050_11_nf;
+extern cpuop_func op_c050_11_ff;
+extern cpuop_func op_c058_11_nf;
+extern cpuop_func op_c058_11_ff;
+extern cpuop_func op_c060_11_nf;
+extern cpuop_func op_c060_11_ff;
+extern cpuop_func op_c068_11_nf;
+extern cpuop_func op_c068_11_ff;
+extern cpuop_func op_c070_11_nf;
+extern cpuop_func op_c070_11_ff;
+extern cpuop_func op_c078_11_nf;
+extern cpuop_func op_c078_11_ff;
+extern cpuop_func op_c079_11_nf;
+extern cpuop_func op_c079_11_ff;
+extern cpuop_func op_c07a_11_nf;
+extern cpuop_func op_c07a_11_ff;
+extern cpuop_func op_c07b_11_nf;
+extern cpuop_func op_c07b_11_ff;
+extern cpuop_func op_c07c_11_nf;
+extern cpuop_func op_c07c_11_ff;
+extern cpuop_func op_c080_11_nf;
+extern cpuop_func op_c080_11_ff;
+extern cpuop_func op_c090_11_nf;
+extern cpuop_func op_c090_11_ff;
+extern cpuop_func op_c098_11_nf;
+extern cpuop_func op_c098_11_ff;
+extern cpuop_func op_c0a0_11_nf;
+extern cpuop_func op_c0a0_11_ff;
+extern cpuop_func op_c0a8_11_nf;
+extern cpuop_func op_c0a8_11_ff;
+extern cpuop_func op_c0b0_11_nf;
+extern cpuop_func op_c0b0_11_ff;
+extern cpuop_func op_c0b8_11_nf;
+extern cpuop_func op_c0b8_11_ff;
+extern cpuop_func op_c0b9_11_nf;
+extern cpuop_func op_c0b9_11_ff;
+extern cpuop_func op_c0ba_11_nf;
+extern cpuop_func op_c0ba_11_ff;
+extern cpuop_func op_c0bb_11_nf;
+extern cpuop_func op_c0bb_11_ff;
+extern cpuop_func op_c0bc_11_nf;
+extern cpuop_func op_c0bc_11_ff;
+extern cpuop_func op_c0c0_11_nf;
+extern cpuop_func op_c0c0_11_ff;
+extern cpuop_func op_c0d0_11_nf;
+extern cpuop_func op_c0d0_11_ff;
+extern cpuop_func op_c0d8_11_nf;
+extern cpuop_func op_c0d8_11_ff;
+extern cpuop_func op_c0e0_11_nf;
+extern cpuop_func op_c0e0_11_ff;
+extern cpuop_func op_c0e8_11_nf;
+extern cpuop_func op_c0e8_11_ff;
+extern cpuop_func op_c0f0_11_nf;
+extern cpuop_func op_c0f0_11_ff;
+extern cpuop_func op_c0f8_11_nf;
+extern cpuop_func op_c0f8_11_ff;
+extern cpuop_func op_c0f9_11_nf;
+extern cpuop_func op_c0f9_11_ff;
+extern cpuop_func op_c0fa_11_nf;
+extern cpuop_func op_c0fa_11_ff;
+extern cpuop_func op_c0fb_11_nf;
+extern cpuop_func op_c0fb_11_ff;
+extern cpuop_func op_c0fc_11_nf;
+extern cpuop_func op_c0fc_11_ff;
+extern cpuop_func op_c100_11_nf;
+extern cpuop_func op_c100_11_ff;
+extern cpuop_func op_c108_11_nf;
+extern cpuop_func op_c108_11_ff;
+extern cpuop_func op_c110_11_nf;
+extern cpuop_func op_c110_11_ff;
+extern cpuop_func op_c118_11_nf;
+extern cpuop_func op_c118_11_ff;
+extern cpuop_func op_c120_11_nf;
+extern cpuop_func op_c120_11_ff;
+extern cpuop_func op_c128_11_nf;
+extern cpuop_func op_c128_11_ff;
+extern cpuop_func op_c130_11_nf;
+extern cpuop_func op_c130_11_ff;
+extern cpuop_func op_c138_11_nf;
+extern cpuop_func op_c138_11_ff;
+extern cpuop_func op_c139_11_nf;
+extern cpuop_func op_c139_11_ff;
+extern cpuop_func op_c140_11_nf;
+extern cpuop_func op_c140_11_ff;
+extern cpuop_func op_c148_11_nf;
+extern cpuop_func op_c148_11_ff;
+extern cpuop_func op_c150_11_nf;
+extern cpuop_func op_c150_11_ff;
+extern cpuop_func op_c158_11_nf;
+extern cpuop_func op_c158_11_ff;
+extern cpuop_func op_c160_11_nf;
+extern cpuop_func op_c160_11_ff;
+extern cpuop_func op_c168_11_nf;
+extern cpuop_func op_c168_11_ff;
+extern cpuop_func op_c170_11_nf;
+extern cpuop_func op_c170_11_ff;
+extern cpuop_func op_c178_11_nf;
+extern cpuop_func op_c178_11_ff;
+extern cpuop_func op_c179_11_nf;
+extern cpuop_func op_c179_11_ff;
+extern cpuop_func op_c188_11_nf;
+extern cpuop_func op_c188_11_ff;
+extern cpuop_func op_c190_11_nf;
+extern cpuop_func op_c190_11_ff;
+extern cpuop_func op_c198_11_nf;
+extern cpuop_func op_c198_11_ff;
+extern cpuop_func op_c1a0_11_nf;
+extern cpuop_func op_c1a0_11_ff;
+extern cpuop_func op_c1a8_11_nf;
+extern cpuop_func op_c1a8_11_ff;
+extern cpuop_func op_c1b0_11_nf;
+extern cpuop_func op_c1b0_11_ff;
+extern cpuop_func op_c1b8_11_nf;
+extern cpuop_func op_c1b8_11_ff;
+extern cpuop_func op_c1b9_11_nf;
+extern cpuop_func op_c1b9_11_ff;
+extern cpuop_func op_c1c0_11_nf;
+extern cpuop_func op_c1c0_11_ff;
+extern cpuop_func op_c1d0_11_nf;
+extern cpuop_func op_c1d0_11_ff;
+extern cpuop_func op_c1d8_11_nf;
+extern cpuop_func op_c1d8_11_ff;
+extern cpuop_func op_c1e0_11_nf;
+extern cpuop_func op_c1e0_11_ff;
+extern cpuop_func op_c1e8_11_nf;
+extern cpuop_func op_c1e8_11_ff;
+extern cpuop_func op_c1f0_11_nf;
+extern cpuop_func op_c1f0_11_ff;
+extern cpuop_func op_c1f8_11_nf;
+extern cpuop_func op_c1f8_11_ff;
+extern cpuop_func op_c1f9_11_nf;
+extern cpuop_func op_c1f9_11_ff;
+extern cpuop_func op_c1fa_11_nf;
+extern cpuop_func op_c1fa_11_ff;
+extern cpuop_func op_c1fb_11_nf;
+extern cpuop_func op_c1fb_11_ff;
+extern cpuop_func op_c1fc_11_nf;
+extern cpuop_func op_c1fc_11_ff;
+extern cpuop_func op_d000_11_nf;
+extern cpuop_func op_d000_11_ff;
+extern cpuop_func op_d010_11_nf;
+extern cpuop_func op_d010_11_ff;
+extern cpuop_func op_d018_11_nf;
+extern cpuop_func op_d018_11_ff;
+extern cpuop_func op_d020_11_nf;
+extern cpuop_func op_d020_11_ff;
+extern cpuop_func op_d028_11_nf;
+extern cpuop_func op_d028_11_ff;
+extern cpuop_func op_d030_11_nf;
+extern cpuop_func op_d030_11_ff;
+extern cpuop_func op_d038_11_nf;
+extern cpuop_func op_d038_11_ff;
+extern cpuop_func op_d039_11_nf;
+extern cpuop_func op_d039_11_ff;
+extern cpuop_func op_d03a_11_nf;
+extern cpuop_func op_d03a_11_ff;
+extern cpuop_func op_d03b_11_nf;
+extern cpuop_func op_d03b_11_ff;
+extern cpuop_func op_d03c_11_nf;
+extern cpuop_func op_d03c_11_ff;
+extern cpuop_func op_d040_11_nf;
+extern cpuop_func op_d040_11_ff;
+extern cpuop_func op_d048_11_nf;
+extern cpuop_func op_d048_11_ff;
+extern cpuop_func op_d050_11_nf;
+extern cpuop_func op_d050_11_ff;
+extern cpuop_func op_d058_11_nf;
+extern cpuop_func op_d058_11_ff;
+extern cpuop_func op_d060_11_nf;
+extern cpuop_func op_d060_11_ff;
+extern cpuop_func op_d068_11_nf;
+extern cpuop_func op_d068_11_ff;
+extern cpuop_func op_d070_11_nf;
+extern cpuop_func op_d070_11_ff;
+extern cpuop_func op_d078_11_nf;
+extern cpuop_func op_d078_11_ff;
+extern cpuop_func op_d079_11_nf;
+extern cpuop_func op_d079_11_ff;
+extern cpuop_func op_d07a_11_nf;
+extern cpuop_func op_d07a_11_ff;
+extern cpuop_func op_d07b_11_nf;
+extern cpuop_func op_d07b_11_ff;
+extern cpuop_func op_d07c_11_nf;
+extern cpuop_func op_d07c_11_ff;
+extern cpuop_func op_d080_11_nf;
+extern cpuop_func op_d080_11_ff;
+extern cpuop_func op_d088_11_nf;
+extern cpuop_func op_d088_11_ff;
+extern cpuop_func op_d090_11_nf;
+extern cpuop_func op_d090_11_ff;
+extern cpuop_func op_d098_11_nf;
+extern cpuop_func op_d098_11_ff;
+extern cpuop_func op_d0a0_11_nf;
+extern cpuop_func op_d0a0_11_ff;
+extern cpuop_func op_d0a8_11_nf;
+extern cpuop_func op_d0a8_11_ff;
+extern cpuop_func op_d0b0_11_nf;
+extern cpuop_func op_d0b0_11_ff;
+extern cpuop_func op_d0b8_11_nf;
+extern cpuop_func op_d0b8_11_ff;
+extern cpuop_func op_d0b9_11_nf;
+extern cpuop_func op_d0b9_11_ff;
+extern cpuop_func op_d0ba_11_nf;
+extern cpuop_func op_d0ba_11_ff;
+extern cpuop_func op_d0bb_11_nf;
+extern cpuop_func op_d0bb_11_ff;
+extern cpuop_func op_d0bc_11_nf;
+extern cpuop_func op_d0bc_11_ff;
+extern cpuop_func op_d0c0_11_nf;
+extern cpuop_func op_d0c0_11_ff;
+extern cpuop_func op_d0c8_11_nf;
+extern cpuop_func op_d0c8_11_ff;
+extern cpuop_func op_d0d0_11_nf;
+extern cpuop_func op_d0d0_11_ff;
+extern cpuop_func op_d0d8_11_nf;
+extern cpuop_func op_d0d8_11_ff;
+extern cpuop_func op_d0e0_11_nf;
+extern cpuop_func op_d0e0_11_ff;
+extern cpuop_func op_d0e8_11_nf;
+extern cpuop_func op_d0e8_11_ff;
+extern cpuop_func op_d0f0_11_nf;
+extern cpuop_func op_d0f0_11_ff;
+extern cpuop_func op_d0f8_11_nf;
+extern cpuop_func op_d0f8_11_ff;
+extern cpuop_func op_d0f9_11_nf;
+extern cpuop_func op_d0f9_11_ff;
+extern cpuop_func op_d0fa_11_nf;
+extern cpuop_func op_d0fa_11_ff;
+extern cpuop_func op_d0fb_11_nf;
+extern cpuop_func op_d0fb_11_ff;
+extern cpuop_func op_d0fc_11_nf;
+extern cpuop_func op_d0fc_11_ff;
+extern cpuop_func op_d100_11_nf;
+extern cpuop_func op_d100_11_ff;
+extern cpuop_func op_d108_11_nf;
+extern cpuop_func op_d108_11_ff;
+extern cpuop_func op_d110_11_nf;
+extern cpuop_func op_d110_11_ff;
+extern cpuop_func op_d118_11_nf;
+extern cpuop_func op_d118_11_ff;
+extern cpuop_func op_d120_11_nf;
+extern cpuop_func op_d120_11_ff;
+extern cpuop_func op_d128_11_nf;
+extern cpuop_func op_d128_11_ff;
+extern cpuop_func op_d130_11_nf;
+extern cpuop_func op_d130_11_ff;
+extern cpuop_func op_d138_11_nf;
+extern cpuop_func op_d138_11_ff;
+extern cpuop_func op_d139_11_nf;
+extern cpuop_func op_d139_11_ff;
+extern cpuop_func op_d140_11_nf;
+extern cpuop_func op_d140_11_ff;
+extern cpuop_func op_d148_11_nf;
+extern cpuop_func op_d148_11_ff;
+extern cpuop_func op_d150_11_nf;
+extern cpuop_func op_d150_11_ff;
+extern cpuop_func op_d158_11_nf;
+extern cpuop_func op_d158_11_ff;
+extern cpuop_func op_d160_11_nf;
+extern cpuop_func op_d160_11_ff;
+extern cpuop_func op_d168_11_nf;
+extern cpuop_func op_d168_11_ff;
+extern cpuop_func op_d170_11_nf;
+extern cpuop_func op_d170_11_ff;
+extern cpuop_func op_d178_11_nf;
+extern cpuop_func op_d178_11_ff;
+extern cpuop_func op_d179_11_nf;
+extern cpuop_func op_d179_11_ff;
+extern cpuop_func op_d180_11_nf;
+extern cpuop_func op_d180_11_ff;
+extern cpuop_func op_d188_11_nf;
+extern cpuop_func op_d188_11_ff;
+extern cpuop_func op_d190_11_nf;
+extern cpuop_func op_d190_11_ff;
+extern cpuop_func op_d198_11_nf;
+extern cpuop_func op_d198_11_ff;
+extern cpuop_func op_d1a0_11_nf;
+extern cpuop_func op_d1a0_11_ff;
+extern cpuop_func op_d1a8_11_nf;
+extern cpuop_func op_d1a8_11_ff;
+extern cpuop_func op_d1b0_11_nf;
+extern cpuop_func op_d1b0_11_ff;
+extern cpuop_func op_d1b8_11_nf;
+extern cpuop_func op_d1b8_11_ff;
+extern cpuop_func op_d1b9_11_nf;
+extern cpuop_func op_d1b9_11_ff;
+extern cpuop_func op_d1c0_11_nf;
+extern cpuop_func op_d1c0_11_ff;
+extern cpuop_func op_d1c8_11_nf;
+extern cpuop_func op_d1c8_11_ff;
+extern cpuop_func op_d1d0_11_nf;
+extern cpuop_func op_d1d0_11_ff;
+extern cpuop_func op_d1d8_11_nf;
+extern cpuop_func op_d1d8_11_ff;
+extern cpuop_func op_d1e0_11_nf;
+extern cpuop_func op_d1e0_11_ff;
+extern cpuop_func op_d1e8_11_nf;
+extern cpuop_func op_d1e8_11_ff;
+extern cpuop_func op_d1f0_11_nf;
+extern cpuop_func op_d1f0_11_ff;
+extern cpuop_func op_d1f8_11_nf;
+extern cpuop_func op_d1f8_11_ff;
+extern cpuop_func op_d1f9_11_nf;
+extern cpuop_func op_d1f9_11_ff;
+extern cpuop_func op_d1fa_11_nf;
+extern cpuop_func op_d1fa_11_ff;
+extern cpuop_func op_d1fb_11_nf;
+extern cpuop_func op_d1fb_11_ff;
+extern cpuop_func op_d1fc_11_nf;
+extern cpuop_func op_d1fc_11_ff;
+extern cpuop_func op_e000_11_nf;
+extern cpuop_func op_e000_11_ff;
+extern cpuop_func op_e008_11_nf;
+extern cpuop_func op_e008_11_ff;
+extern cpuop_func op_e010_11_nf;
+extern cpuop_func op_e010_11_ff;
+extern cpuop_func op_e018_11_nf;
+extern cpuop_func op_e018_11_ff;
+extern cpuop_func op_e020_11_nf;
+extern cpuop_func op_e020_11_ff;
+extern cpuop_func op_e028_11_nf;
+extern cpuop_func op_e028_11_ff;
+extern cpuop_func op_e030_11_nf;
+extern cpuop_func op_e030_11_ff;
+extern cpuop_func op_e038_11_nf;
+extern cpuop_func op_e038_11_ff;
+extern cpuop_func op_e040_11_nf;
+extern cpuop_func op_e040_11_ff;
+extern cpuop_func op_e048_11_nf;
+extern cpuop_func op_e048_11_ff;
+extern cpuop_func op_e050_11_nf;
+extern cpuop_func op_e050_11_ff;
+extern cpuop_func op_e058_11_nf;
+extern cpuop_func op_e058_11_ff;
+extern cpuop_func op_e060_11_nf;
+extern cpuop_func op_e060_11_ff;
+extern cpuop_func op_e068_11_nf;
+extern cpuop_func op_e068_11_ff;
+extern cpuop_func op_e070_11_nf;
+extern cpuop_func op_e070_11_ff;
+extern cpuop_func op_e078_11_nf;
+extern cpuop_func op_e078_11_ff;
+extern cpuop_func op_e080_11_nf;
+extern cpuop_func op_e080_11_ff;
+extern cpuop_func op_e088_11_nf;
+extern cpuop_func op_e088_11_ff;
+extern cpuop_func op_e090_11_nf;
+extern cpuop_func op_e090_11_ff;
+extern cpuop_func op_e098_11_nf;
+extern cpuop_func op_e098_11_ff;
+extern cpuop_func op_e0a0_11_nf;
+extern cpuop_func op_e0a0_11_ff;
+extern cpuop_func op_e0a8_11_nf;
+extern cpuop_func op_e0a8_11_ff;
+extern cpuop_func op_e0b0_11_nf;
+extern cpuop_func op_e0b0_11_ff;
+extern cpuop_func op_e0b8_11_nf;
+extern cpuop_func op_e0b8_11_ff;
+extern cpuop_func op_e0d0_11_nf;
+extern cpuop_func op_e0d0_11_ff;
+extern cpuop_func op_e0d8_11_nf;
+extern cpuop_func op_e0d8_11_ff;
+extern cpuop_func op_e0e0_11_nf;
+extern cpuop_func op_e0e0_11_ff;
+extern cpuop_func op_e0e8_11_nf;
+extern cpuop_func op_e0e8_11_ff;
+extern cpuop_func op_e0f0_11_nf;
+extern cpuop_func op_e0f0_11_ff;
+extern cpuop_func op_e0f8_11_nf;
+extern cpuop_func op_e0f8_11_ff;
+extern cpuop_func op_e0f9_11_nf;
+extern cpuop_func op_e0f9_11_ff;
+extern cpuop_func op_e100_11_nf;
+extern cpuop_func op_e100_11_ff;
+extern cpuop_func op_e108_11_nf;
+extern cpuop_func op_e108_11_ff;
+extern cpuop_func op_e110_11_nf;
+extern cpuop_func op_e110_11_ff;
+extern cpuop_func op_e118_11_nf;
+extern cpuop_func op_e118_11_ff;
+extern cpuop_func op_e120_11_nf;
+extern cpuop_func op_e120_11_ff;
+extern cpuop_func op_e128_11_nf;
+extern cpuop_func op_e128_11_ff;
+extern cpuop_func op_e130_11_nf;
+extern cpuop_func op_e130_11_ff;
+extern cpuop_func op_e138_11_nf;
+extern cpuop_func op_e138_11_ff;
+extern cpuop_func op_e140_11_nf;
+extern cpuop_func op_e140_11_ff;
+extern cpuop_func op_e148_11_nf;
+extern cpuop_func op_e148_11_ff;
+extern cpuop_func op_e150_11_nf;
+extern cpuop_func op_e150_11_ff;
+extern cpuop_func op_e158_11_nf;
+extern cpuop_func op_e158_11_ff;
+extern cpuop_func op_e160_11_nf;
+extern cpuop_func op_e160_11_ff;
+extern cpuop_func op_e168_11_nf;
+extern cpuop_func op_e168_11_ff;
+extern cpuop_func op_e170_11_nf;
+extern cpuop_func op_e170_11_ff;
+extern cpuop_func op_e178_11_nf;
+extern cpuop_func op_e178_11_ff;
+extern cpuop_func op_e180_11_nf;
+extern cpuop_func op_e180_11_ff;
+extern cpuop_func op_e188_11_nf;
+extern cpuop_func op_e188_11_ff;
+extern cpuop_func op_e190_11_nf;
+extern cpuop_func op_e190_11_ff;
+extern cpuop_func op_e198_11_nf;
+extern cpuop_func op_e198_11_ff;
+extern cpuop_func op_e1a0_11_nf;
+extern cpuop_func op_e1a0_11_ff;
+extern cpuop_func op_e1a8_11_nf;
+extern cpuop_func op_e1a8_11_ff;
+extern cpuop_func op_e1b0_11_nf;
+extern cpuop_func op_e1b0_11_ff;
+extern cpuop_func op_e1b8_11_nf;
+extern cpuop_func op_e1b8_11_ff;
+extern cpuop_func op_e1d0_11_nf;
+extern cpuop_func op_e1d0_11_ff;
+extern cpuop_func op_e1d8_11_nf;
+extern cpuop_func op_e1d8_11_ff;
+extern cpuop_func op_e1e0_11_nf;
+extern cpuop_func op_e1e0_11_ff;
+extern cpuop_func op_e1e8_11_nf;
+extern cpuop_func op_e1e8_11_ff;
+extern cpuop_func op_e1f0_11_nf;
+extern cpuop_func op_e1f0_11_ff;
+extern cpuop_func op_e1f8_11_nf;
+extern cpuop_func op_e1f8_11_ff;
+extern cpuop_func op_e1f9_11_nf;
+extern cpuop_func op_e1f9_11_ff;
+extern cpuop_func op_e2d0_11_nf;
+extern cpuop_func op_e2d0_11_ff;
+extern cpuop_func op_e2d8_11_nf;
+extern cpuop_func op_e2d8_11_ff;
+extern cpuop_func op_e2e0_11_nf;
+extern cpuop_func op_e2e0_11_ff;
+extern cpuop_func op_e2e8_11_nf;
+extern cpuop_func op_e2e8_11_ff;
+extern cpuop_func op_e2f0_11_nf;
+extern cpuop_func op_e2f0_11_ff;
+extern cpuop_func op_e2f8_11_nf;
+extern cpuop_func op_e2f8_11_ff;
+extern cpuop_func op_e2f9_11_nf;
+extern cpuop_func op_e2f9_11_ff;
+extern cpuop_func op_e3d0_11_nf;
+extern cpuop_func op_e3d0_11_ff;
+extern cpuop_func op_e3d8_11_nf;
+extern cpuop_func op_e3d8_11_ff;
+extern cpuop_func op_e3e0_11_nf;
+extern cpuop_func op_e3e0_11_ff;
+extern cpuop_func op_e3e8_11_nf;
+extern cpuop_func op_e3e8_11_ff;
+extern cpuop_func op_e3f0_11_nf;
+extern cpuop_func op_e3f0_11_ff;
+extern cpuop_func op_e3f8_11_nf;
+extern cpuop_func op_e3f8_11_ff;
+extern cpuop_func op_e3f9_11_nf;
+extern cpuop_func op_e3f9_11_ff;
+extern cpuop_func op_e4d0_11_nf;
+extern cpuop_func op_e4d0_11_ff;
+extern cpuop_func op_e4d8_11_nf;
+extern cpuop_func op_e4d8_11_ff;
+extern cpuop_func op_e4e0_11_nf;
+extern cpuop_func op_e4e0_11_ff;
+extern cpuop_func op_e4e8_11_nf;
+extern cpuop_func op_e4e8_11_ff;
+extern cpuop_func op_e4f0_11_nf;
+extern cpuop_func op_e4f0_11_ff;
+extern cpuop_func op_e4f8_11_nf;
+extern cpuop_func op_e4f8_11_ff;
+extern cpuop_func op_e4f9_11_nf;
+extern cpuop_func op_e4f9_11_ff;
+extern cpuop_func op_e5d0_11_nf;
+extern cpuop_func op_e5d0_11_ff;
+extern cpuop_func op_e5d8_11_nf;
+extern cpuop_func op_e5d8_11_ff;
+extern cpuop_func op_e5e0_11_nf;
+extern cpuop_func op_e5e0_11_ff;
+extern cpuop_func op_e5e8_11_nf;
+extern cpuop_func op_e5e8_11_ff;
+extern cpuop_func op_e5f0_11_nf;
+extern cpuop_func op_e5f0_11_ff;
+extern cpuop_func op_e5f8_11_nf;
+extern cpuop_func op_e5f8_11_ff;
+extern cpuop_func op_e5f9_11_nf;
+extern cpuop_func op_e5f9_11_ff;
+extern cpuop_func op_e6d0_11_nf;
+extern cpuop_func op_e6d0_11_ff;
+extern cpuop_func op_e6d8_11_nf;
+extern cpuop_func op_e6d8_11_ff;
+extern cpuop_func op_e6e0_11_nf;
+extern cpuop_func op_e6e0_11_ff;
+extern cpuop_func op_e6e8_11_nf;
+extern cpuop_func op_e6e8_11_ff;
+extern cpuop_func op_e6f0_11_nf;
+extern cpuop_func op_e6f0_11_ff;
+extern cpuop_func op_e6f8_11_nf;
+extern cpuop_func op_e6f8_11_ff;
+extern cpuop_func op_e6f9_11_nf;
+extern cpuop_func op_e6f9_11_ff;
+extern cpuop_func op_e7d0_11_nf;
+extern cpuop_func op_e7d0_11_ff;
+extern cpuop_func op_e7d8_11_nf;
+extern cpuop_func op_e7d8_11_ff;
+extern cpuop_func op_e7e0_11_nf;
+extern cpuop_func op_e7e0_11_ff;
+extern cpuop_func op_e7e8_11_nf;
+extern cpuop_func op_e7e8_11_ff;
+extern cpuop_func op_e7f0_11_nf;
+extern cpuop_func op_e7f0_11_ff;
+extern cpuop_func op_e7f8_11_nf;
+extern cpuop_func op_e7f8_11_ff;
+extern cpuop_func op_e7f9_11_nf;
+extern cpuop_func op_e7f9_11_ff;
+extern cpuop_func op_40c0_12_nf;
+extern cpuop_func op_40c0_12_ff;
+extern cpuop_func op_40d0_12_nf;
+extern cpuop_func op_40d0_12_ff;
+extern cpuop_func op_40d8_12_nf;
+extern cpuop_func op_40d8_12_ff;
+extern cpuop_func op_40e0_12_nf;
+extern cpuop_func op_40e0_12_ff;
+extern cpuop_func op_40e8_12_nf;
+extern cpuop_func op_40e8_12_ff;
+extern cpuop_func op_40f0_12_nf;
+extern cpuop_func op_40f0_12_ff;
+extern cpuop_func op_40f8_12_nf;
+extern cpuop_func op_40f8_12_ff;
+extern cpuop_func op_40f9_12_nf;
+extern cpuop_func op_40f9_12_ff;
+extern cpuop_func op_4200_12_nf;
+extern cpuop_func op_4200_12_ff;
+extern cpuop_func op_4210_12_nf;
+extern cpuop_func op_4210_12_ff;
+extern cpuop_func op_4218_12_nf;
+extern cpuop_func op_4218_12_ff;
+extern cpuop_func op_4220_12_nf;
+extern cpuop_func op_4220_12_ff;
+extern cpuop_func op_4228_12_nf;
+extern cpuop_func op_4228_12_ff;
+extern cpuop_func op_4230_12_nf;
+extern cpuop_func op_4230_12_ff;
+extern cpuop_func op_4238_12_nf;
+extern cpuop_func op_4238_12_ff;
+extern cpuop_func op_4239_12_nf;
+extern cpuop_func op_4239_12_ff;
+extern cpuop_func op_4240_12_nf;
+extern cpuop_func op_4240_12_ff;
+extern cpuop_func op_4250_12_nf;
+extern cpuop_func op_4250_12_ff;
+extern cpuop_func op_4258_12_nf;
+extern cpuop_func op_4258_12_ff;
+extern cpuop_func op_4260_12_nf;
+extern cpuop_func op_4260_12_ff;
+extern cpuop_func op_4268_12_nf;
+extern cpuop_func op_4268_12_ff;
+extern cpuop_func op_4270_12_nf;
+extern cpuop_func op_4270_12_ff;
+extern cpuop_func op_4278_12_nf;
+extern cpuop_func op_4278_12_ff;
+extern cpuop_func op_4279_12_nf;
+extern cpuop_func op_4279_12_ff;
+extern cpuop_func op_4280_12_nf;
+extern cpuop_func op_4280_12_ff;
+extern cpuop_func op_4290_12_nf;
+extern cpuop_func op_4290_12_ff;
+extern cpuop_func op_4298_12_nf;
+extern cpuop_func op_4298_12_ff;
+extern cpuop_func op_42a0_12_nf;
+extern cpuop_func op_42a0_12_ff;
+extern cpuop_func op_42a8_12_nf;
+extern cpuop_func op_42a8_12_ff;
+extern cpuop_func op_42b0_12_nf;
+extern cpuop_func op_42b0_12_ff;
+extern cpuop_func op_42b8_12_nf;
+extern cpuop_func op_42b8_12_ff;
+extern cpuop_func op_42b9_12_nf;
+extern cpuop_func op_42b9_12_ff;
+extern cpuop_func op_4e73_12_nf;
+extern cpuop_func op_4e73_12_ff;
+extern cpuop_func op_50c0_12_nf;
+extern cpuop_func op_50c0_12_ff;
+extern cpuop_func op_50d0_12_nf;
+extern cpuop_func op_50d0_12_ff;
+extern cpuop_func op_50d8_12_nf;
+extern cpuop_func op_50d8_12_ff;
+extern cpuop_func op_50e0_12_nf;
+extern cpuop_func op_50e0_12_ff;
+extern cpuop_func op_50e8_12_nf;
+extern cpuop_func op_50e8_12_ff;
+extern cpuop_func op_50f0_12_nf;
+extern cpuop_func op_50f0_12_ff;
+extern cpuop_func op_50f8_12_nf;
+extern cpuop_func op_50f8_12_ff;
+extern cpuop_func op_50f9_12_nf;
+extern cpuop_func op_50f9_12_ff;
+extern cpuop_func op_51c0_12_nf;
+extern cpuop_func op_51c0_12_ff;
+extern cpuop_func op_51d0_12_nf;
+extern cpuop_func op_51d0_12_ff;
+extern cpuop_func op_51d8_12_nf;
+extern cpuop_func op_51d8_12_ff;
+extern cpuop_func op_51e0_12_nf;
+extern cpuop_func op_51e0_12_ff;
+extern cpuop_func op_51e8_12_nf;
+extern cpuop_func op_51e8_12_ff;
+extern cpuop_func op_51f0_12_nf;
+extern cpuop_func op_51f0_12_ff;
+extern cpuop_func op_51f8_12_nf;
+extern cpuop_func op_51f8_12_ff;
+extern cpuop_func op_51f9_12_nf;
+extern cpuop_func op_51f9_12_ff;
+extern cpuop_func op_52c0_12_nf;
+extern cpuop_func op_52c0_12_ff;
+extern cpuop_func op_52d0_12_nf;
+extern cpuop_func op_52d0_12_ff;
+extern cpuop_func op_52d8_12_nf;
+extern cpuop_func op_52d8_12_ff;
+extern cpuop_func op_52e0_12_nf;
+extern cpuop_func op_52e0_12_ff;
+extern cpuop_func op_52e8_12_nf;
+extern cpuop_func op_52e8_12_ff;
+extern cpuop_func op_52f0_12_nf;
+extern cpuop_func op_52f0_12_ff;
+extern cpuop_func op_52f8_12_nf;
+extern cpuop_func op_52f8_12_ff;
+extern cpuop_func op_52f9_12_nf;
+extern cpuop_func op_52f9_12_ff;
+extern cpuop_func op_53c0_12_nf;
+extern cpuop_func op_53c0_12_ff;
+extern cpuop_func op_53d0_12_nf;
+extern cpuop_func op_53d0_12_ff;
+extern cpuop_func op_53d8_12_nf;
+extern cpuop_func op_53d8_12_ff;
+extern cpuop_func op_53e0_12_nf;
+extern cpuop_func op_53e0_12_ff;
+extern cpuop_func op_53e8_12_nf;
+extern cpuop_func op_53e8_12_ff;
+extern cpuop_func op_53f0_12_nf;
+extern cpuop_func op_53f0_12_ff;
+extern cpuop_func op_53f8_12_nf;
+extern cpuop_func op_53f8_12_ff;
+extern cpuop_func op_53f9_12_nf;
+extern cpuop_func op_53f9_12_ff;
+extern cpuop_func op_54c0_12_nf;
+extern cpuop_func op_54c0_12_ff;
+extern cpuop_func op_54d0_12_nf;
+extern cpuop_func op_54d0_12_ff;
+extern cpuop_func op_54d8_12_nf;
+extern cpuop_func op_54d8_12_ff;
+extern cpuop_func op_54e0_12_nf;
+extern cpuop_func op_54e0_12_ff;
+extern cpuop_func op_54e8_12_nf;
+extern cpuop_func op_54e8_12_ff;
+extern cpuop_func op_54f0_12_nf;
+extern cpuop_func op_54f0_12_ff;
+extern cpuop_func op_54f8_12_nf;
+extern cpuop_func op_54f8_12_ff;
+extern cpuop_func op_54f9_12_nf;
+extern cpuop_func op_54f9_12_ff;
+extern cpuop_func op_55c0_12_nf;
+extern cpuop_func op_55c0_12_ff;
+extern cpuop_func op_55d0_12_nf;
+extern cpuop_func op_55d0_12_ff;
+extern cpuop_func op_55d8_12_nf;
+extern cpuop_func op_55d8_12_ff;
+extern cpuop_func op_55e0_12_nf;
+extern cpuop_func op_55e0_12_ff;
+extern cpuop_func op_55e8_12_nf;
+extern cpuop_func op_55e8_12_ff;
+extern cpuop_func op_55f0_12_nf;
+extern cpuop_func op_55f0_12_ff;
+extern cpuop_func op_55f8_12_nf;
+extern cpuop_func op_55f8_12_ff;
+extern cpuop_func op_55f9_12_nf;
+extern cpuop_func op_55f9_12_ff;
+extern cpuop_func op_56c0_12_nf;
+extern cpuop_func op_56c0_12_ff;
+extern cpuop_func op_56d0_12_nf;
+extern cpuop_func op_56d0_12_ff;
+extern cpuop_func op_56d8_12_nf;
+extern cpuop_func op_56d8_12_ff;
+extern cpuop_func op_56e0_12_nf;
+extern cpuop_func op_56e0_12_ff;
+extern cpuop_func op_56e8_12_nf;
+extern cpuop_func op_56e8_12_ff;
+extern cpuop_func op_56f0_12_nf;
+extern cpuop_func op_56f0_12_ff;
+extern cpuop_func op_56f8_12_nf;
+extern cpuop_func op_56f8_12_ff;
+extern cpuop_func op_56f9_12_nf;
+extern cpuop_func op_56f9_12_ff;
+extern cpuop_func op_57c0_12_nf;
+extern cpuop_func op_57c0_12_ff;
+extern cpuop_func op_57d0_12_nf;
+extern cpuop_func op_57d0_12_ff;
+extern cpuop_func op_57d8_12_nf;
+extern cpuop_func op_57d8_12_ff;
+extern cpuop_func op_57e0_12_nf;
+extern cpuop_func op_57e0_12_ff;
+extern cpuop_func op_57e8_12_nf;
+extern cpuop_func op_57e8_12_ff;
+extern cpuop_func op_57f0_12_nf;
+extern cpuop_func op_57f0_12_ff;
+extern cpuop_func op_57f8_12_nf;
+extern cpuop_func op_57f8_12_ff;
+extern cpuop_func op_57f9_12_nf;
+extern cpuop_func op_57f9_12_ff;
+extern cpuop_func op_58c0_12_nf;
+extern cpuop_func op_58c0_12_ff;
+extern cpuop_func op_58d0_12_nf;
+extern cpuop_func op_58d0_12_ff;
+extern cpuop_func op_58d8_12_nf;
+extern cpuop_func op_58d8_12_ff;
+extern cpuop_func op_58e0_12_nf;
+extern cpuop_func op_58e0_12_ff;
+extern cpuop_func op_58e8_12_nf;
+extern cpuop_func op_58e8_12_ff;
+extern cpuop_func op_58f0_12_nf;
+extern cpuop_func op_58f0_12_ff;
+extern cpuop_func op_58f8_12_nf;
+extern cpuop_func op_58f8_12_ff;
+extern cpuop_func op_58f9_12_nf;
+extern cpuop_func op_58f9_12_ff;
+extern cpuop_func op_59c0_12_nf;
+extern cpuop_func op_59c0_12_ff;
+extern cpuop_func op_59d0_12_nf;
+extern cpuop_func op_59d0_12_ff;
+extern cpuop_func op_59d8_12_nf;
+extern cpuop_func op_59d8_12_ff;
+extern cpuop_func op_59e0_12_nf;
+extern cpuop_func op_59e0_12_ff;
+extern cpuop_func op_59e8_12_nf;
+extern cpuop_func op_59e8_12_ff;
+extern cpuop_func op_59f0_12_nf;
+extern cpuop_func op_59f0_12_ff;
+extern cpuop_func op_59f8_12_nf;
+extern cpuop_func op_59f8_12_ff;
+extern cpuop_func op_59f9_12_nf;
+extern cpuop_func op_59f9_12_ff;
+extern cpuop_func op_5ac0_12_nf;
+extern cpuop_func op_5ac0_12_ff;
+extern cpuop_func op_5ad0_12_nf;
+extern cpuop_func op_5ad0_12_ff;
+extern cpuop_func op_5ad8_12_nf;
+extern cpuop_func op_5ad8_12_ff;
+extern cpuop_func op_5ae0_12_nf;
+extern cpuop_func op_5ae0_12_ff;
+extern cpuop_func op_5ae8_12_nf;
+extern cpuop_func op_5ae8_12_ff;
+extern cpuop_func op_5af0_12_nf;
+extern cpuop_func op_5af0_12_ff;
+extern cpuop_func op_5af8_12_nf;
+extern cpuop_func op_5af8_12_ff;
+extern cpuop_func op_5af9_12_nf;
+extern cpuop_func op_5af9_12_ff;
+extern cpuop_func op_5bc0_12_nf;
+extern cpuop_func op_5bc0_12_ff;
+extern cpuop_func op_5bd0_12_nf;
+extern cpuop_func op_5bd0_12_ff;
+extern cpuop_func op_5bd8_12_nf;
+extern cpuop_func op_5bd8_12_ff;
+extern cpuop_func op_5be0_12_nf;
+extern cpuop_func op_5be0_12_ff;
+extern cpuop_func op_5be8_12_nf;
+extern cpuop_func op_5be8_12_ff;
+extern cpuop_func op_5bf0_12_nf;
+extern cpuop_func op_5bf0_12_ff;
+extern cpuop_func op_5bf8_12_nf;
+extern cpuop_func op_5bf8_12_ff;
+extern cpuop_func op_5bf9_12_nf;
+extern cpuop_func op_5bf9_12_ff;
+extern cpuop_func op_5cc0_12_nf;
+extern cpuop_func op_5cc0_12_ff;
+extern cpuop_func op_5cd0_12_nf;
+extern cpuop_func op_5cd0_12_ff;
+extern cpuop_func op_5cd8_12_nf;
+extern cpuop_func op_5cd8_12_ff;
+extern cpuop_func op_5ce0_12_nf;
+extern cpuop_func op_5ce0_12_ff;
+extern cpuop_func op_5ce8_12_nf;
+extern cpuop_func op_5ce8_12_ff;
+extern cpuop_func op_5cf0_12_nf;
+extern cpuop_func op_5cf0_12_ff;
+extern cpuop_func op_5cf8_12_nf;
+extern cpuop_func op_5cf8_12_ff;
+extern cpuop_func op_5cf9_12_nf;
+extern cpuop_func op_5cf9_12_ff;
+extern cpuop_func op_5dc0_12_nf;
+extern cpuop_func op_5dc0_12_ff;
+extern cpuop_func op_5dd0_12_nf;
+extern cpuop_func op_5dd0_12_ff;
+extern cpuop_func op_5dd8_12_nf;
+extern cpuop_func op_5dd8_12_ff;
+extern cpuop_func op_5de0_12_nf;
+extern cpuop_func op_5de0_12_ff;
+extern cpuop_func op_5de8_12_nf;
+extern cpuop_func op_5de8_12_ff;
+extern cpuop_func op_5df0_12_nf;
+extern cpuop_func op_5df0_12_ff;
+extern cpuop_func op_5df8_12_nf;
+extern cpuop_func op_5df8_12_ff;
+extern cpuop_func op_5df9_12_nf;
+extern cpuop_func op_5df9_12_ff;
+extern cpuop_func op_5ec0_12_nf;
+extern cpuop_func op_5ec0_12_ff;
+extern cpuop_func op_5ed0_12_nf;
+extern cpuop_func op_5ed0_12_ff;
+extern cpuop_func op_5ed8_12_nf;
+extern cpuop_func op_5ed8_12_ff;
+extern cpuop_func op_5ee0_12_nf;
+extern cpuop_func op_5ee0_12_ff;
+extern cpuop_func op_5ee8_12_nf;
+extern cpuop_func op_5ee8_12_ff;
+extern cpuop_func op_5ef0_12_nf;
+extern cpuop_func op_5ef0_12_ff;
+extern cpuop_func op_5ef8_12_nf;
+extern cpuop_func op_5ef8_12_ff;
+extern cpuop_func op_5ef9_12_nf;
+extern cpuop_func op_5ef9_12_ff;
+extern cpuop_func op_5fc0_12_nf;
+extern cpuop_func op_5fc0_12_ff;
+extern cpuop_func op_5fd0_12_nf;
+extern cpuop_func op_5fd0_12_ff;
+extern cpuop_func op_5fd8_12_nf;
+extern cpuop_func op_5fd8_12_ff;
+extern cpuop_func op_5fe0_12_nf;
+extern cpuop_func op_5fe0_12_ff;
+extern cpuop_func op_5fe8_12_nf;
+extern cpuop_func op_5fe8_12_ff;
+extern cpuop_func op_5ff0_12_nf;
+extern cpuop_func op_5ff0_12_ff;
+extern cpuop_func op_5ff8_12_nf;
+extern cpuop_func op_5ff8_12_ff;
+extern cpuop_func op_5ff9_12_nf;
+extern cpuop_func op_5ff9_12_ff;
+extern cpuop_func_ce op_0000_13_nf;
+extern cpuop_func_ce op_0000_13_ff;
+extern cpuop_func_ce op_0010_13_nf;
+extern cpuop_func_ce op_0010_13_ff;
+extern cpuop_func_ce op_0018_13_nf;
+extern cpuop_func_ce op_0018_13_ff;
+extern cpuop_func_ce op_0020_13_nf;
+extern cpuop_func_ce op_0020_13_ff;
+extern cpuop_func_ce op_0028_13_nf;
+extern cpuop_func_ce op_0028_13_ff;
+extern cpuop_func_ce op_0030_13_nf;
+extern cpuop_func_ce op_0030_13_ff;
+extern cpuop_func_ce op_0038_13_nf;
+extern cpuop_func_ce op_0038_13_ff;
+extern cpuop_func_ce op_0039_13_nf;
+extern cpuop_func_ce op_0039_13_ff;
+extern cpuop_func_ce op_003c_13_nf;
+extern cpuop_func_ce op_003c_13_ff;
+extern cpuop_func_ce op_0040_13_nf;
+extern cpuop_func_ce op_0040_13_ff;
+extern cpuop_func_ce op_0050_13_nf;
+extern cpuop_func_ce op_0050_13_ff;
+extern cpuop_func_ce op_0058_13_nf;
+extern cpuop_func_ce op_0058_13_ff;
+extern cpuop_func_ce op_0060_13_nf;
+extern cpuop_func_ce op_0060_13_ff;
+extern cpuop_func_ce op_0068_13_nf;
+extern cpuop_func_ce op_0068_13_ff;
+extern cpuop_func_ce op_0070_13_nf;
+extern cpuop_func_ce op_0070_13_ff;
+extern cpuop_func_ce op_0078_13_nf;
+extern cpuop_func_ce op_0078_13_ff;
+extern cpuop_func_ce op_0079_13_nf;
+extern cpuop_func_ce op_0079_13_ff;
+extern cpuop_func_ce op_007c_13_nf;
+extern cpuop_func_ce op_007c_13_ff;
+extern cpuop_func_ce op_0080_13_nf;
+extern cpuop_func_ce op_0080_13_ff;
+extern cpuop_func_ce op_0090_13_nf;
+extern cpuop_func_ce op_0090_13_ff;
+extern cpuop_func_ce op_0098_13_nf;
+extern cpuop_func_ce op_0098_13_ff;
+extern cpuop_func_ce op_00a0_13_nf;
+extern cpuop_func_ce op_00a0_13_ff;
+extern cpuop_func_ce op_00a8_13_nf;
+extern cpuop_func_ce op_00a8_13_ff;
+extern cpuop_func_ce op_00b0_13_nf;
+extern cpuop_func_ce op_00b0_13_ff;
+extern cpuop_func_ce op_00b8_13_nf;
+extern cpuop_func_ce op_00b8_13_ff;
+extern cpuop_func_ce op_00b9_13_nf;
+extern cpuop_func_ce op_00b9_13_ff;
+extern cpuop_func_ce op_0100_13_nf;
+extern cpuop_func_ce op_0100_13_ff;
+extern cpuop_func_ce op_0108_13_nf;
+extern cpuop_func_ce op_0108_13_ff;
+extern cpuop_func_ce op_0110_13_nf;
+extern cpuop_func_ce op_0110_13_ff;
+extern cpuop_func_ce op_0118_13_nf;
+extern cpuop_func_ce op_0118_13_ff;
+extern cpuop_func_ce op_0120_13_nf;
+extern cpuop_func_ce op_0120_13_ff;
+extern cpuop_func_ce op_0128_13_nf;
+extern cpuop_func_ce op_0128_13_ff;
+extern cpuop_func_ce op_0130_13_nf;
+extern cpuop_func_ce op_0130_13_ff;
+extern cpuop_func_ce op_0138_13_nf;
+extern cpuop_func_ce op_0138_13_ff;
+extern cpuop_func_ce op_0139_13_nf;
+extern cpuop_func_ce op_0139_13_ff;
+extern cpuop_func_ce op_013a_13_nf;
+extern cpuop_func_ce op_013a_13_ff;
+extern cpuop_func_ce op_013b_13_nf;
+extern cpuop_func_ce op_013b_13_ff;
+extern cpuop_func_ce op_013c_13_nf;
+extern cpuop_func_ce op_013c_13_ff;
+extern cpuop_func_ce op_0140_13_nf;
+extern cpuop_func_ce op_0140_13_ff;
+extern cpuop_func_ce op_0148_13_nf;
+extern cpuop_func_ce op_0148_13_ff;
+extern cpuop_func_ce op_0150_13_nf;
+extern cpuop_func_ce op_0150_13_ff;
+extern cpuop_func_ce op_0158_13_nf;
+extern cpuop_func_ce op_0158_13_ff;
+extern cpuop_func_ce op_0160_13_nf;
+extern cpuop_func_ce op_0160_13_ff;
+extern cpuop_func_ce op_0168_13_nf;
+extern cpuop_func_ce op_0168_13_ff;
+extern cpuop_func_ce op_0170_13_nf;
+extern cpuop_func_ce op_0170_13_ff;
+extern cpuop_func_ce op_0178_13_nf;
+extern cpuop_func_ce op_0178_13_ff;
+extern cpuop_func_ce op_0179_13_nf;
+extern cpuop_func_ce op_0179_13_ff;
+extern cpuop_func_ce op_0180_13_nf;
+extern cpuop_func_ce op_0180_13_ff;
+extern cpuop_func_ce op_0188_13_nf;
+extern cpuop_func_ce op_0188_13_ff;
+extern cpuop_func_ce op_0190_13_nf;
+extern cpuop_func_ce op_0190_13_ff;
+extern cpuop_func_ce op_0198_13_nf;
+extern cpuop_func_ce op_0198_13_ff;
+extern cpuop_func_ce op_01a0_13_nf;
+extern cpuop_func_ce op_01a0_13_ff;
+extern cpuop_func_ce op_01a8_13_nf;
+extern cpuop_func_ce op_01a8_13_ff;
+extern cpuop_func_ce op_01b0_13_nf;
+extern cpuop_func_ce op_01b0_13_ff;
+extern cpuop_func_ce op_01b8_13_nf;
+extern cpuop_func_ce op_01b8_13_ff;
+extern cpuop_func_ce op_01b9_13_nf;
+extern cpuop_func_ce op_01b9_13_ff;
+extern cpuop_func_ce op_01c0_13_nf;
+extern cpuop_func_ce op_01c0_13_ff;
+extern cpuop_func_ce op_01c8_13_nf;
+extern cpuop_func_ce op_01c8_13_ff;
+extern cpuop_func_ce op_01d0_13_nf;
+extern cpuop_func_ce op_01d0_13_ff;
+extern cpuop_func_ce op_01d8_13_nf;
+extern cpuop_func_ce op_01d8_13_ff;
+extern cpuop_func_ce op_01e0_13_nf;
+extern cpuop_func_ce op_01e0_13_ff;
+extern cpuop_func_ce op_01e8_13_nf;
+extern cpuop_func_ce op_01e8_13_ff;
+extern cpuop_func_ce op_01f0_13_nf;
+extern cpuop_func_ce op_01f0_13_ff;
+extern cpuop_func_ce op_01f8_13_nf;
+extern cpuop_func_ce op_01f8_13_ff;
+extern cpuop_func_ce op_01f9_13_nf;
+extern cpuop_func_ce op_01f9_13_ff;
+extern cpuop_func_ce op_0200_13_nf;
+extern cpuop_func_ce op_0200_13_ff;
+extern cpuop_func_ce op_0210_13_nf;
+extern cpuop_func_ce op_0210_13_ff;
+extern cpuop_func_ce op_0218_13_nf;
+extern cpuop_func_ce op_0218_13_ff;
+extern cpuop_func_ce op_0220_13_nf;
+extern cpuop_func_ce op_0220_13_ff;
+extern cpuop_func_ce op_0228_13_nf;
+extern cpuop_func_ce op_0228_13_ff;
+extern cpuop_func_ce op_0230_13_nf;
+extern cpuop_func_ce op_0230_13_ff;
+extern cpuop_func_ce op_0238_13_nf;
+extern cpuop_func_ce op_0238_13_ff;
+extern cpuop_func_ce op_0239_13_nf;
+extern cpuop_func_ce op_0239_13_ff;
+extern cpuop_func_ce op_023c_13_nf;
+extern cpuop_func_ce op_023c_13_ff;
+extern cpuop_func_ce op_0240_13_nf;
+extern cpuop_func_ce op_0240_13_ff;
+extern cpuop_func_ce op_0250_13_nf;
+extern cpuop_func_ce op_0250_13_ff;
+extern cpuop_func_ce op_0258_13_nf;
+extern cpuop_func_ce op_0258_13_ff;
+extern cpuop_func_ce op_0260_13_nf;
+extern cpuop_func_ce op_0260_13_ff;
+extern cpuop_func_ce op_0268_13_nf;
+extern cpuop_func_ce op_0268_13_ff;
+extern cpuop_func_ce op_0270_13_nf;
+extern cpuop_func_ce op_0270_13_ff;
+extern cpuop_func_ce op_0278_13_nf;
+extern cpuop_func_ce op_0278_13_ff;
+extern cpuop_func_ce op_0279_13_nf;
+extern cpuop_func_ce op_0279_13_ff;
+extern cpuop_func_ce op_027c_13_nf;
+extern cpuop_func_ce op_027c_13_ff;
+extern cpuop_func_ce op_0280_13_nf;
+extern cpuop_func_ce op_0280_13_ff;
+extern cpuop_func_ce op_0290_13_nf;
+extern cpuop_func_ce op_0290_13_ff;
+extern cpuop_func_ce op_0298_13_nf;
+extern cpuop_func_ce op_0298_13_ff;
+extern cpuop_func_ce op_02a0_13_nf;
+extern cpuop_func_ce op_02a0_13_ff;
+extern cpuop_func_ce op_02a8_13_nf;
+extern cpuop_func_ce op_02a8_13_ff;
+extern cpuop_func_ce op_02b0_13_nf;
+extern cpuop_func_ce op_02b0_13_ff;
+extern cpuop_func_ce op_02b8_13_nf;
+extern cpuop_func_ce op_02b8_13_ff;
+extern cpuop_func_ce op_02b9_13_nf;
+extern cpuop_func_ce op_02b9_13_ff;
+extern cpuop_func_ce op_0400_13_nf;
+extern cpuop_func_ce op_0400_13_ff;
+extern cpuop_func_ce op_0410_13_nf;
+extern cpuop_func_ce op_0410_13_ff;
+extern cpuop_func_ce op_0418_13_nf;
+extern cpuop_func_ce op_0418_13_ff;
+extern cpuop_func_ce op_0420_13_nf;
+extern cpuop_func_ce op_0420_13_ff;
+extern cpuop_func_ce op_0428_13_nf;
+extern cpuop_func_ce op_0428_13_ff;
+extern cpuop_func_ce op_0430_13_nf;
+extern cpuop_func_ce op_0430_13_ff;
+extern cpuop_func_ce op_0438_13_nf;
+extern cpuop_func_ce op_0438_13_ff;
+extern cpuop_func_ce op_0439_13_nf;
+extern cpuop_func_ce op_0439_13_ff;
+extern cpuop_func_ce op_0440_13_nf;
+extern cpuop_func_ce op_0440_13_ff;
+extern cpuop_func_ce op_0450_13_nf;
+extern cpuop_func_ce op_0450_13_ff;
+extern cpuop_func_ce op_0458_13_nf;
+extern cpuop_func_ce op_0458_13_ff;
+extern cpuop_func_ce op_0460_13_nf;
+extern cpuop_func_ce op_0460_13_ff;
+extern cpuop_func_ce op_0468_13_nf;
+extern cpuop_func_ce op_0468_13_ff;
+extern cpuop_func_ce op_0470_13_nf;
+extern cpuop_func_ce op_0470_13_ff;
+extern cpuop_func_ce op_0478_13_nf;
+extern cpuop_func_ce op_0478_13_ff;
+extern cpuop_func_ce op_0479_13_nf;
+extern cpuop_func_ce op_0479_13_ff;
+extern cpuop_func_ce op_0480_13_nf;
+extern cpuop_func_ce op_0480_13_ff;
+extern cpuop_func_ce op_0490_13_nf;
+extern cpuop_func_ce op_0490_13_ff;
+extern cpuop_func_ce op_0498_13_nf;
+extern cpuop_func_ce op_0498_13_ff;
+extern cpuop_func_ce op_04a0_13_nf;
+extern cpuop_func_ce op_04a0_13_ff;
+extern cpuop_func_ce op_04a8_13_nf;
+extern cpuop_func_ce op_04a8_13_ff;
+extern cpuop_func_ce op_04b0_13_nf;
+extern cpuop_func_ce op_04b0_13_ff;
+extern cpuop_func_ce op_04b8_13_nf;
+extern cpuop_func_ce op_04b8_13_ff;
+extern cpuop_func_ce op_04b9_13_nf;
+extern cpuop_func_ce op_04b9_13_ff;
+extern cpuop_func_ce op_0600_13_nf;
+extern cpuop_func_ce op_0600_13_ff;
+extern cpuop_func_ce op_0610_13_nf;
+extern cpuop_func_ce op_0610_13_ff;
+extern cpuop_func_ce op_0618_13_nf;
+extern cpuop_func_ce op_0618_13_ff;
+extern cpuop_func_ce op_0620_13_nf;
+extern cpuop_func_ce op_0620_13_ff;
+extern cpuop_func_ce op_0628_13_nf;
+extern cpuop_func_ce op_0628_13_ff;
+extern cpuop_func_ce op_0630_13_nf;
+extern cpuop_func_ce op_0630_13_ff;
+extern cpuop_func_ce op_0638_13_nf;
+extern cpuop_func_ce op_0638_13_ff;
+extern cpuop_func_ce op_0639_13_nf;
+extern cpuop_func_ce op_0639_13_ff;
+extern cpuop_func_ce op_0640_13_nf;
+extern cpuop_func_ce op_0640_13_ff;
+extern cpuop_func_ce op_0650_13_nf;
+extern cpuop_func_ce op_0650_13_ff;
+extern cpuop_func_ce op_0658_13_nf;
+extern cpuop_func_ce op_0658_13_ff;
+extern cpuop_func_ce op_0660_13_nf;
+extern cpuop_func_ce op_0660_13_ff;
+extern cpuop_func_ce op_0668_13_nf;
+extern cpuop_func_ce op_0668_13_ff;
+extern cpuop_func_ce op_0670_13_nf;
+extern cpuop_func_ce op_0670_13_ff;
+extern cpuop_func_ce op_0678_13_nf;
+extern cpuop_func_ce op_0678_13_ff;
+extern cpuop_func_ce op_0679_13_nf;
+extern cpuop_func_ce op_0679_13_ff;
+extern cpuop_func_ce op_0680_13_nf;
+extern cpuop_func_ce op_0680_13_ff;
+extern cpuop_func_ce op_0690_13_nf;
+extern cpuop_func_ce op_0690_13_ff;
+extern cpuop_func_ce op_0698_13_nf;
+extern cpuop_func_ce op_0698_13_ff;
+extern cpuop_func_ce op_06a0_13_nf;
+extern cpuop_func_ce op_06a0_13_ff;
+extern cpuop_func_ce op_06a8_13_nf;
+extern cpuop_func_ce op_06a8_13_ff;
+extern cpuop_func_ce op_06b0_13_nf;
+extern cpuop_func_ce op_06b0_13_ff;
+extern cpuop_func_ce op_06b8_13_nf;
+extern cpuop_func_ce op_06b8_13_ff;
+extern cpuop_func_ce op_06b9_13_nf;
+extern cpuop_func_ce op_06b9_13_ff;
+extern cpuop_func_ce op_0800_13_nf;
+extern cpuop_func_ce op_0800_13_ff;
+extern cpuop_func_ce op_0810_13_nf;
+extern cpuop_func_ce op_0810_13_ff;
+extern cpuop_func_ce op_0818_13_nf;
+extern cpuop_func_ce op_0818_13_ff;
+extern cpuop_func_ce op_0820_13_nf;
+extern cpuop_func_ce op_0820_13_ff;
+extern cpuop_func_ce op_0828_13_nf;
+extern cpuop_func_ce op_0828_13_ff;
+extern cpuop_func_ce op_0830_13_nf;
+extern cpuop_func_ce op_0830_13_ff;
+extern cpuop_func_ce op_0838_13_nf;
+extern cpuop_func_ce op_0838_13_ff;
+extern cpuop_func_ce op_0839_13_nf;
+extern cpuop_func_ce op_0839_13_ff;
+extern cpuop_func_ce op_083a_13_nf;
+extern cpuop_func_ce op_083a_13_ff;
+extern cpuop_func_ce op_083b_13_nf;
+extern cpuop_func_ce op_083b_13_ff;
+extern cpuop_func_ce op_0840_13_nf;
+extern cpuop_func_ce op_0840_13_ff;
+extern cpuop_func_ce op_0850_13_nf;
+extern cpuop_func_ce op_0850_13_ff;
+extern cpuop_func_ce op_0858_13_nf;
+extern cpuop_func_ce op_0858_13_ff;
+extern cpuop_func_ce op_0860_13_nf;
+extern cpuop_func_ce op_0860_13_ff;
+extern cpuop_func_ce op_0868_13_nf;
+extern cpuop_func_ce op_0868_13_ff;
+extern cpuop_func_ce op_0870_13_nf;
+extern cpuop_func_ce op_0870_13_ff;
+extern cpuop_func_ce op_0878_13_nf;
+extern cpuop_func_ce op_0878_13_ff;
+extern cpuop_func_ce op_0879_13_nf;
+extern cpuop_func_ce op_0879_13_ff;
+extern cpuop_func_ce op_0880_13_nf;
+extern cpuop_func_ce op_0880_13_ff;
+extern cpuop_func_ce op_0890_13_nf;
+extern cpuop_func_ce op_0890_13_ff;
+extern cpuop_func_ce op_0898_13_nf;
+extern cpuop_func_ce op_0898_13_ff;
+extern cpuop_func_ce op_08a0_13_nf;
+extern cpuop_func_ce op_08a0_13_ff;
+extern cpuop_func_ce op_08a8_13_nf;
+extern cpuop_func_ce op_08a8_13_ff;
+extern cpuop_func_ce op_08b0_13_nf;
+extern cpuop_func_ce op_08b0_13_ff;
+extern cpuop_func_ce op_08b8_13_nf;
+extern cpuop_func_ce op_08b8_13_ff;
+extern cpuop_func_ce op_08b9_13_nf;
+extern cpuop_func_ce op_08b9_13_ff;
+extern cpuop_func_ce op_08c0_13_nf;
+extern cpuop_func_ce op_08c0_13_ff;
+extern cpuop_func_ce op_08d0_13_nf;
+extern cpuop_func_ce op_08d0_13_ff;
+extern cpuop_func_ce op_08d8_13_nf;
+extern cpuop_func_ce op_08d8_13_ff;
+extern cpuop_func_ce op_08e0_13_nf;
+extern cpuop_func_ce op_08e0_13_ff;
+extern cpuop_func_ce op_08e8_13_nf;
+extern cpuop_func_ce op_08e8_13_ff;
+extern cpuop_func_ce op_08f0_13_nf;
+extern cpuop_func_ce op_08f0_13_ff;
+extern cpuop_func_ce op_08f8_13_nf;
+extern cpuop_func_ce op_08f8_13_ff;
+extern cpuop_func_ce op_08f9_13_nf;
+extern cpuop_func_ce op_08f9_13_ff;
+extern cpuop_func_ce op_0a00_13_nf;
+extern cpuop_func_ce op_0a00_13_ff;
+extern cpuop_func_ce op_0a10_13_nf;
+extern cpuop_func_ce op_0a10_13_ff;
+extern cpuop_func_ce op_0a18_13_nf;
+extern cpuop_func_ce op_0a18_13_ff;
+extern cpuop_func_ce op_0a20_13_nf;
+extern cpuop_func_ce op_0a20_13_ff;
+extern cpuop_func_ce op_0a28_13_nf;
+extern cpuop_func_ce op_0a28_13_ff;
+extern cpuop_func_ce op_0a30_13_nf;
+extern cpuop_func_ce op_0a30_13_ff;
+extern cpuop_func_ce op_0a38_13_nf;
+extern cpuop_func_ce op_0a38_13_ff;
+extern cpuop_func_ce op_0a39_13_nf;
+extern cpuop_func_ce op_0a39_13_ff;
+extern cpuop_func_ce op_0a3c_13_nf;
+extern cpuop_func_ce op_0a3c_13_ff;
+extern cpuop_func_ce op_0a40_13_nf;
+extern cpuop_func_ce op_0a40_13_ff;
+extern cpuop_func_ce op_0a50_13_nf;
+extern cpuop_func_ce op_0a50_13_ff;
+extern cpuop_func_ce op_0a58_13_nf;
+extern cpuop_func_ce op_0a58_13_ff;
+extern cpuop_func_ce op_0a60_13_nf;
+extern cpuop_func_ce op_0a60_13_ff;
+extern cpuop_func_ce op_0a68_13_nf;
+extern cpuop_func_ce op_0a68_13_ff;
+extern cpuop_func_ce op_0a70_13_nf;
+extern cpuop_func_ce op_0a70_13_ff;
+extern cpuop_func_ce op_0a78_13_nf;
+extern cpuop_func_ce op_0a78_13_ff;
+extern cpuop_func_ce op_0a79_13_nf;
+extern cpuop_func_ce op_0a79_13_ff;
+extern cpuop_func_ce op_0a7c_13_nf;
+extern cpuop_func_ce op_0a7c_13_ff;
+extern cpuop_func_ce op_0a80_13_nf;
+extern cpuop_func_ce op_0a80_13_ff;
+extern cpuop_func_ce op_0a90_13_nf;
+extern cpuop_func_ce op_0a90_13_ff;
+extern cpuop_func_ce op_0a98_13_nf;
+extern cpuop_func_ce op_0a98_13_ff;
+extern cpuop_func_ce op_0aa0_13_nf;
+extern cpuop_func_ce op_0aa0_13_ff;
+extern cpuop_func_ce op_0aa8_13_nf;
+extern cpuop_func_ce op_0aa8_13_ff;
+extern cpuop_func_ce op_0ab0_13_nf;
+extern cpuop_func_ce op_0ab0_13_ff;
+extern cpuop_func_ce op_0ab8_13_nf;
+extern cpuop_func_ce op_0ab8_13_ff;
+extern cpuop_func_ce op_0ab9_13_nf;
+extern cpuop_func_ce op_0ab9_13_ff;
+extern cpuop_func_ce op_0c00_13_nf;
+extern cpuop_func_ce op_0c00_13_ff;
+extern cpuop_func_ce op_0c10_13_nf;
+extern cpuop_func_ce op_0c10_13_ff;
+extern cpuop_func_ce op_0c18_13_nf;
+extern cpuop_func_ce op_0c18_13_ff;
+extern cpuop_func_ce op_0c20_13_nf;
+extern cpuop_func_ce op_0c20_13_ff;
+extern cpuop_func_ce op_0c28_13_nf;
+extern cpuop_func_ce op_0c28_13_ff;
+extern cpuop_func_ce op_0c30_13_nf;
+extern cpuop_func_ce op_0c30_13_ff;
+extern cpuop_func_ce op_0c38_13_nf;
+extern cpuop_func_ce op_0c38_13_ff;
+extern cpuop_func_ce op_0c39_13_nf;
+extern cpuop_func_ce op_0c39_13_ff;
+extern cpuop_func_ce op_0c40_13_nf;
+extern cpuop_func_ce op_0c40_13_ff;
+extern cpuop_func_ce op_0c50_13_nf;
+extern cpuop_func_ce op_0c50_13_ff;
+extern cpuop_func_ce op_0c58_13_nf;
+extern cpuop_func_ce op_0c58_13_ff;
+extern cpuop_func_ce op_0c60_13_nf;
+extern cpuop_func_ce op_0c60_13_ff;
+extern cpuop_func_ce op_0c68_13_nf;
+extern cpuop_func_ce op_0c68_13_ff;
+extern cpuop_func_ce op_0c70_13_nf;
+extern cpuop_func_ce op_0c70_13_ff;
+extern cpuop_func_ce op_0c78_13_nf;
+extern cpuop_func_ce op_0c78_13_ff;
+extern cpuop_func_ce op_0c79_13_nf;
+extern cpuop_func_ce op_0c79_13_ff;
+extern cpuop_func_ce op_0c80_13_nf;
+extern cpuop_func_ce op_0c80_13_ff;
+extern cpuop_func_ce op_0c90_13_nf;
+extern cpuop_func_ce op_0c90_13_ff;
+extern cpuop_func_ce op_0c98_13_nf;
+extern cpuop_func_ce op_0c98_13_ff;
+extern cpuop_func_ce op_0ca0_13_nf;
+extern cpuop_func_ce op_0ca0_13_ff;
+extern cpuop_func_ce op_0ca8_13_nf;
+extern cpuop_func_ce op_0ca8_13_ff;
+extern cpuop_func_ce op_0cb0_13_nf;
+extern cpuop_func_ce op_0cb0_13_ff;
+extern cpuop_func_ce op_0cb8_13_nf;
+extern cpuop_func_ce op_0cb8_13_ff;
+extern cpuop_func_ce op_0cb9_13_nf;
+extern cpuop_func_ce op_0cb9_13_ff;
+extern cpuop_func_ce op_1000_13_nf;
+extern cpuop_func_ce op_1000_13_ff;
+extern cpuop_func_ce op_1010_13_nf;
+extern cpuop_func_ce op_1010_13_ff;
+extern cpuop_func_ce op_1018_13_nf;
+extern cpuop_func_ce op_1018_13_ff;
+extern cpuop_func_ce op_1020_13_nf;
+extern cpuop_func_ce op_1020_13_ff;
+extern cpuop_func_ce op_1028_13_nf;
+extern cpuop_func_ce op_1028_13_ff;
+extern cpuop_func_ce op_1030_13_nf;
+extern cpuop_func_ce op_1030_13_ff;
+extern cpuop_func_ce op_1038_13_nf;
+extern cpuop_func_ce op_1038_13_ff;
+extern cpuop_func_ce op_1039_13_nf;
+extern cpuop_func_ce op_1039_13_ff;
+extern cpuop_func_ce op_103a_13_nf;
+extern cpuop_func_ce op_103a_13_ff;
+extern cpuop_func_ce op_103b_13_nf;
+extern cpuop_func_ce op_103b_13_ff;
+extern cpuop_func_ce op_103c_13_nf;
+extern cpuop_func_ce op_103c_13_ff;
+extern cpuop_func_ce op_1080_13_nf;
+extern cpuop_func_ce op_1080_13_ff;
+extern cpuop_func_ce op_1090_13_nf;
+extern cpuop_func_ce op_1090_13_ff;
+extern cpuop_func_ce op_1098_13_nf;
+extern cpuop_func_ce op_1098_13_ff;
+extern cpuop_func_ce op_10a0_13_nf;
+extern cpuop_func_ce op_10a0_13_ff;
+extern cpuop_func_ce op_10a8_13_nf;
+extern cpuop_func_ce op_10a8_13_ff;
+extern cpuop_func_ce op_10b0_13_nf;
+extern cpuop_func_ce op_10b0_13_ff;
+extern cpuop_func_ce op_10b8_13_nf;
+extern cpuop_func_ce op_10b8_13_ff;
+extern cpuop_func_ce op_10b9_13_nf;
+extern cpuop_func_ce op_10b9_13_ff;
+extern cpuop_func_ce op_10ba_13_nf;
+extern cpuop_func_ce op_10ba_13_ff;
+extern cpuop_func_ce op_10bb_13_nf;
+extern cpuop_func_ce op_10bb_13_ff;
+extern cpuop_func_ce op_10bc_13_nf;
+extern cpuop_func_ce op_10bc_13_ff;
+extern cpuop_func_ce op_10c0_13_nf;
+extern cpuop_func_ce op_10c0_13_ff;
+extern cpuop_func_ce op_10d0_13_nf;
+extern cpuop_func_ce op_10d0_13_ff;
+extern cpuop_func_ce op_10d8_13_nf;
+extern cpuop_func_ce op_10d8_13_ff;
+extern cpuop_func_ce op_10e0_13_nf;
+extern cpuop_func_ce op_10e0_13_ff;
+extern cpuop_func_ce op_10e8_13_nf;
+extern cpuop_func_ce op_10e8_13_ff;
+extern cpuop_func_ce op_10f0_13_nf;
+extern cpuop_func_ce op_10f0_13_ff;
+extern cpuop_func_ce op_10f8_13_nf;
+extern cpuop_func_ce op_10f8_13_ff;
+extern cpuop_func_ce op_10f9_13_nf;
+extern cpuop_func_ce op_10f9_13_ff;
+extern cpuop_func_ce op_10fa_13_nf;
+extern cpuop_func_ce op_10fa_13_ff;
+extern cpuop_func_ce op_10fb_13_nf;
+extern cpuop_func_ce op_10fb_13_ff;
+extern cpuop_func_ce op_10fc_13_nf;
+extern cpuop_func_ce op_10fc_13_ff;
+extern cpuop_func_ce op_1100_13_nf;
+extern cpuop_func_ce op_1100_13_ff;
+extern cpuop_func_ce op_1110_13_nf;
+extern cpuop_func_ce op_1110_13_ff;
+extern cpuop_func_ce op_1118_13_nf;
+extern cpuop_func_ce op_1118_13_ff;
+extern cpuop_func_ce op_1120_13_nf;
+extern cpuop_func_ce op_1120_13_ff;
+extern cpuop_func_ce op_1128_13_nf;
+extern cpuop_func_ce op_1128_13_ff;
+extern cpuop_func_ce op_1130_13_nf;
+extern cpuop_func_ce op_1130_13_ff;
+extern cpuop_func_ce op_1138_13_nf;
+extern cpuop_func_ce op_1138_13_ff;
+extern cpuop_func_ce op_1139_13_nf;
+extern cpuop_func_ce op_1139_13_ff;
+extern cpuop_func_ce op_113a_13_nf;
+extern cpuop_func_ce op_113a_13_ff;
+extern cpuop_func_ce op_113b_13_nf;
+extern cpuop_func_ce op_113b_13_ff;
+extern cpuop_func_ce op_113c_13_nf;
+extern cpuop_func_ce op_113c_13_ff;
+extern cpuop_func_ce op_1140_13_nf;
+extern cpuop_func_ce op_1140_13_ff;
+extern cpuop_func_ce op_1150_13_nf;
+extern cpuop_func_ce op_1150_13_ff;
+extern cpuop_func_ce op_1158_13_nf;
+extern cpuop_func_ce op_1158_13_ff;
+extern cpuop_func_ce op_1160_13_nf;
+extern cpuop_func_ce op_1160_13_ff;
+extern cpuop_func_ce op_1168_13_nf;
+extern cpuop_func_ce op_1168_13_ff;
+extern cpuop_func_ce op_1170_13_nf;
+extern cpuop_func_ce op_1170_13_ff;
+extern cpuop_func_ce op_1178_13_nf;
+extern cpuop_func_ce op_1178_13_ff;
+extern cpuop_func_ce op_1179_13_nf;
+extern cpuop_func_ce op_1179_13_ff;
+extern cpuop_func_ce op_117a_13_nf;
+extern cpuop_func_ce op_117a_13_ff;
+extern cpuop_func_ce op_117b_13_nf;
+extern cpuop_func_ce op_117b_13_ff;
+extern cpuop_func_ce op_117c_13_nf;
+extern cpuop_func_ce op_117c_13_ff;
+extern cpuop_func_ce op_1180_13_nf;
+extern cpuop_func_ce op_1180_13_ff;
+extern cpuop_func_ce op_1190_13_nf;
+extern cpuop_func_ce op_1190_13_ff;
+extern cpuop_func_ce op_1198_13_nf;
+extern cpuop_func_ce op_1198_13_ff;
+extern cpuop_func_ce op_11a0_13_nf;
+extern cpuop_func_ce op_11a0_13_ff;
+extern cpuop_func_ce op_11a8_13_nf;
+extern cpuop_func_ce op_11a8_13_ff;
+extern cpuop_func_ce op_11b0_13_nf;
+extern cpuop_func_ce op_11b0_13_ff;
+extern cpuop_func_ce op_11b8_13_nf;
+extern cpuop_func_ce op_11b8_13_ff;
+extern cpuop_func_ce op_11b9_13_nf;
+extern cpuop_func_ce op_11b9_13_ff;
+extern cpuop_func_ce op_11ba_13_nf;
+extern cpuop_func_ce op_11ba_13_ff;
+extern cpuop_func_ce op_11bb_13_nf;
+extern cpuop_func_ce op_11bb_13_ff;
+extern cpuop_func_ce op_11bc_13_nf;
+extern cpuop_func_ce op_11bc_13_ff;
+extern cpuop_func_ce op_11c0_13_nf;
+extern cpuop_func_ce op_11c0_13_ff;
+extern cpuop_func_ce op_11d0_13_nf;
+extern cpuop_func_ce op_11d0_13_ff;
+extern cpuop_func_ce op_11d8_13_nf;
+extern cpuop_func_ce op_11d8_13_ff;
+extern cpuop_func_ce op_11e0_13_nf;
+extern cpuop_func_ce op_11e0_13_ff;
+extern cpuop_func_ce op_11e8_13_nf;
+extern cpuop_func_ce op_11e8_13_ff;
+extern cpuop_func_ce op_11f0_13_nf;
+extern cpuop_func_ce op_11f0_13_ff;
+extern cpuop_func_ce op_11f8_13_nf;
+extern cpuop_func_ce op_11f8_13_ff;
+extern cpuop_func_ce op_11f9_13_nf;
+extern cpuop_func_ce op_11f9_13_ff;
+extern cpuop_func_ce op_11fa_13_nf;
+extern cpuop_func_ce op_11fa_13_ff;
+extern cpuop_func_ce op_11fb_13_nf;
+extern cpuop_func_ce op_11fb_13_ff;
+extern cpuop_func_ce op_11fc_13_nf;
+extern cpuop_func_ce op_11fc_13_ff;
+extern cpuop_func_ce op_13c0_13_nf;
+extern cpuop_func_ce op_13c0_13_ff;
+extern cpuop_func_ce op_13d0_13_nf;
+extern cpuop_func_ce op_13d0_13_ff;
+extern cpuop_func_ce op_13d8_13_nf;
+extern cpuop_func_ce op_13d8_13_ff;
+extern cpuop_func_ce op_13e0_13_nf;
+extern cpuop_func_ce op_13e0_13_ff;
+extern cpuop_func_ce op_13e8_13_nf;
+extern cpuop_func_ce op_13e8_13_ff;
+extern cpuop_func_ce op_13f0_13_nf;
+extern cpuop_func_ce op_13f0_13_ff;
+extern cpuop_func_ce op_13f8_13_nf;
+extern cpuop_func_ce op_13f8_13_ff;
+extern cpuop_func_ce op_13f9_13_nf;
+extern cpuop_func_ce op_13f9_13_ff;
+extern cpuop_func_ce op_13fa_13_nf;
+extern cpuop_func_ce op_13fa_13_ff;
+extern cpuop_func_ce op_13fb_13_nf;
+extern cpuop_func_ce op_13fb_13_ff;
+extern cpuop_func_ce op_13fc_13_nf;
+extern cpuop_func_ce op_13fc_13_ff;
+extern cpuop_func_ce op_2000_13_nf;
+extern cpuop_func_ce op_2000_13_ff;
+extern cpuop_func_ce op_2008_13_nf;
+extern cpuop_func_ce op_2008_13_ff;
+extern cpuop_func_ce op_2010_13_nf;
+extern cpuop_func_ce op_2010_13_ff;
+extern cpuop_func_ce op_2018_13_nf;
+extern cpuop_func_ce op_2018_13_ff;
+extern cpuop_func_ce op_2020_13_nf;
+extern cpuop_func_ce op_2020_13_ff;
+extern cpuop_func_ce op_2028_13_nf;
+extern cpuop_func_ce op_2028_13_ff;
+extern cpuop_func_ce op_2030_13_nf;
+extern cpuop_func_ce op_2030_13_ff;
+extern cpuop_func_ce op_2038_13_nf;
+extern cpuop_func_ce op_2038_13_ff;
+extern cpuop_func_ce op_2039_13_nf;
+extern cpuop_func_ce op_2039_13_ff;
+extern cpuop_func_ce op_203a_13_nf;
+extern cpuop_func_ce op_203a_13_ff;
+extern cpuop_func_ce op_203b_13_nf;
+extern cpuop_func_ce op_203b_13_ff;
+extern cpuop_func_ce op_203c_13_nf;
+extern cpuop_func_ce op_203c_13_ff;
+extern cpuop_func_ce op_2040_13_nf;
+extern cpuop_func_ce op_2040_13_ff;
+extern cpuop_func_ce op_2048_13_nf;
+extern cpuop_func_ce op_2048_13_ff;
+extern cpuop_func_ce op_2050_13_nf;
+extern cpuop_func_ce op_2050_13_ff;
+extern cpuop_func_ce op_2058_13_nf;
+extern cpuop_func_ce op_2058_13_ff;
+extern cpuop_func_ce op_2060_13_nf;
+extern cpuop_func_ce op_2060_13_ff;
+extern cpuop_func_ce op_2068_13_nf;
+extern cpuop_func_ce op_2068_13_ff;
+extern cpuop_func_ce op_2070_13_nf;
+extern cpuop_func_ce op_2070_13_ff;
+extern cpuop_func_ce op_2078_13_nf;
+extern cpuop_func_ce op_2078_13_ff;
+extern cpuop_func_ce op_2079_13_nf;
+extern cpuop_func_ce op_2079_13_ff;
+extern cpuop_func_ce op_207a_13_nf;
+extern cpuop_func_ce op_207a_13_ff;
+extern cpuop_func_ce op_207b_13_nf;
+extern cpuop_func_ce op_207b_13_ff;
+extern cpuop_func_ce op_207c_13_nf;
+extern cpuop_func_ce op_207c_13_ff;
+extern cpuop_func_ce op_2080_13_nf;
+extern cpuop_func_ce op_2080_13_ff;
+extern cpuop_func_ce op_2088_13_nf;
+extern cpuop_func_ce op_2088_13_ff;
+extern cpuop_func_ce op_2090_13_nf;
+extern cpuop_func_ce op_2090_13_ff;
+extern cpuop_func_ce op_2098_13_nf;
+extern cpuop_func_ce op_2098_13_ff;
+extern cpuop_func_ce op_20a0_13_nf;
+extern cpuop_func_ce op_20a0_13_ff;
+extern cpuop_func_ce op_20a8_13_nf;
+extern cpuop_func_ce op_20a8_13_ff;
+extern cpuop_func_ce op_20b0_13_nf;
+extern cpuop_func_ce op_20b0_13_ff;
+extern cpuop_func_ce op_20b8_13_nf;
+extern cpuop_func_ce op_20b8_13_ff;
+extern cpuop_func_ce op_20b9_13_nf;
+extern cpuop_func_ce op_20b9_13_ff;
+extern cpuop_func_ce op_20ba_13_nf;
+extern cpuop_func_ce op_20ba_13_ff;
+extern cpuop_func_ce op_20bb_13_nf;
+extern cpuop_func_ce op_20bb_13_ff;
+extern cpuop_func_ce op_20bc_13_nf;
+extern cpuop_func_ce op_20bc_13_ff;
+extern cpuop_func_ce op_20c0_13_nf;
+extern cpuop_func_ce op_20c0_13_ff;
+extern cpuop_func_ce op_20c8_13_nf;
+extern cpuop_func_ce op_20c8_13_ff;
+extern cpuop_func_ce op_20d0_13_nf;
+extern cpuop_func_ce op_20d0_13_ff;
+extern cpuop_func_ce op_20d8_13_nf;
+extern cpuop_func_ce op_20d8_13_ff;
+extern cpuop_func_ce op_20e0_13_nf;
+extern cpuop_func_ce op_20e0_13_ff;
+extern cpuop_func_ce op_20e8_13_nf;
+extern cpuop_func_ce op_20e8_13_ff;
+extern cpuop_func_ce op_20f0_13_nf;
+extern cpuop_func_ce op_20f0_13_ff;
+extern cpuop_func_ce op_20f8_13_nf;
+extern cpuop_func_ce op_20f8_13_ff;
+extern cpuop_func_ce op_20f9_13_nf;
+extern cpuop_func_ce op_20f9_13_ff;
+extern cpuop_func_ce op_20fa_13_nf;
+extern cpuop_func_ce op_20fa_13_ff;
+extern cpuop_func_ce op_20fb_13_nf;
+extern cpuop_func_ce op_20fb_13_ff;
+extern cpuop_func_ce op_20fc_13_nf;
+extern cpuop_func_ce op_20fc_13_ff;
+extern cpuop_func_ce op_2100_13_nf;
+extern cpuop_func_ce op_2100_13_ff;
+extern cpuop_func_ce op_2108_13_nf;
+extern cpuop_func_ce op_2108_13_ff;
+extern cpuop_func_ce op_2110_13_nf;
+extern cpuop_func_ce op_2110_13_ff;
+extern cpuop_func_ce op_2118_13_nf;
+extern cpuop_func_ce op_2118_13_ff;
+extern cpuop_func_ce op_2120_13_nf;
+extern cpuop_func_ce op_2120_13_ff;
+extern cpuop_func_ce op_2128_13_nf;
+extern cpuop_func_ce op_2128_13_ff;
+extern cpuop_func_ce op_2130_13_nf;
+extern cpuop_func_ce op_2130_13_ff;
+extern cpuop_func_ce op_2138_13_nf;
+extern cpuop_func_ce op_2138_13_ff;
+extern cpuop_func_ce op_2139_13_nf;
+extern cpuop_func_ce op_2139_13_ff;
+extern cpuop_func_ce op_213a_13_nf;
+extern cpuop_func_ce op_213a_13_ff;
+extern cpuop_func_ce op_213b_13_nf;
+extern cpuop_func_ce op_213b_13_ff;
+extern cpuop_func_ce op_213c_13_nf;
+extern cpuop_func_ce op_213c_13_ff;
+extern cpuop_func_ce op_2140_13_nf;
+extern cpuop_func_ce op_2140_13_ff;
+extern cpuop_func_ce op_2148_13_nf;
+extern cpuop_func_ce op_2148_13_ff;
+extern cpuop_func_ce op_2150_13_nf;
+extern cpuop_func_ce op_2150_13_ff;
+extern cpuop_func_ce op_2158_13_nf;
+extern cpuop_func_ce op_2158_13_ff;
+extern cpuop_func_ce op_2160_13_nf;
+extern cpuop_func_ce op_2160_13_ff;
+extern cpuop_func_ce op_2168_13_nf;
+extern cpuop_func_ce op_2168_13_ff;
+extern cpuop_func_ce op_2170_13_nf;
+extern cpuop_func_ce op_2170_13_ff;
+extern cpuop_func_ce op_2178_13_nf;
+extern cpuop_func_ce op_2178_13_ff;
+extern cpuop_func_ce op_2179_13_nf;
+extern cpuop_func_ce op_2179_13_ff;
+extern cpuop_func_ce op_217a_13_nf;
+extern cpuop_func_ce op_217a_13_ff;
+extern cpuop_func_ce op_217b_13_nf;
+extern cpuop_func_ce op_217b_13_ff;
+extern cpuop_func_ce op_217c_13_nf;
+extern cpuop_func_ce op_217c_13_ff;
+extern cpuop_func_ce op_2180_13_nf;
+extern cpuop_func_ce op_2180_13_ff;
+extern cpuop_func_ce op_2188_13_nf;
+extern cpuop_func_ce op_2188_13_ff;
+extern cpuop_func_ce op_2190_13_nf;
+extern cpuop_func_ce op_2190_13_ff;
+extern cpuop_func_ce op_2198_13_nf;
+extern cpuop_func_ce op_2198_13_ff;
+extern cpuop_func_ce op_21a0_13_nf;
+extern cpuop_func_ce op_21a0_13_ff;
+extern cpuop_func_ce op_21a8_13_nf;
+extern cpuop_func_ce op_21a8_13_ff;
+extern cpuop_func_ce op_21b0_13_nf;
+extern cpuop_func_ce op_21b0_13_ff;
+extern cpuop_func_ce op_21b8_13_nf;
+extern cpuop_func_ce op_21b8_13_ff;
+extern cpuop_func_ce op_21b9_13_nf;
+extern cpuop_func_ce op_21b9_13_ff;
+extern cpuop_func_ce op_21ba_13_nf;
+extern cpuop_func_ce op_21ba_13_ff;
+extern cpuop_func_ce op_21bb_13_nf;
+extern cpuop_func_ce op_21bb_13_ff;
+extern cpuop_func_ce op_21bc_13_nf;
+extern cpuop_func_ce op_21bc_13_ff;
+extern cpuop_func_ce op_21c0_13_nf;
+extern cpuop_func_ce op_21c0_13_ff;
+extern cpuop_func_ce op_21c8_13_nf;
+extern cpuop_func_ce op_21c8_13_ff;
+extern cpuop_func_ce op_21d0_13_nf;
+extern cpuop_func_ce op_21d0_13_ff;
+extern cpuop_func_ce op_21d8_13_nf;
+extern cpuop_func_ce op_21d8_13_ff;
+extern cpuop_func_ce op_21e0_13_nf;
+extern cpuop_func_ce op_21e0_13_ff;
+extern cpuop_func_ce op_21e8_13_nf;
+extern cpuop_func_ce op_21e8_13_ff;
+extern cpuop_func_ce op_21f0_13_nf;
+extern cpuop_func_ce op_21f0_13_ff;
+extern cpuop_func_ce op_21f8_13_nf;
+extern cpuop_func_ce op_21f8_13_ff;
+extern cpuop_func_ce op_21f9_13_nf;
+extern cpuop_func_ce op_21f9_13_ff;
+extern cpuop_func_ce op_21fa_13_nf;
+extern cpuop_func_ce op_21fa_13_ff;
+extern cpuop_func_ce op_21fb_13_nf;
+extern cpuop_func_ce op_21fb_13_ff;
+extern cpuop_func_ce op_21fc_13_nf;
+extern cpuop_func_ce op_21fc_13_ff;
+extern cpuop_func_ce op_23c0_13_nf;
+extern cpuop_func_ce op_23c0_13_ff;
+extern cpuop_func_ce op_23c8_13_nf;
+extern cpuop_func_ce op_23c8_13_ff;
+extern cpuop_func_ce op_23d0_13_nf;
+extern cpuop_func_ce op_23d0_13_ff;
+extern cpuop_func_ce op_23d8_13_nf;
+extern cpuop_func_ce op_23d8_13_ff;
+extern cpuop_func_ce op_23e0_13_nf;
+extern cpuop_func_ce op_23e0_13_ff;
+extern cpuop_func_ce op_23e8_13_nf;
+extern cpuop_func_ce op_23e8_13_ff;
+extern cpuop_func_ce op_23f0_13_nf;
+extern cpuop_func_ce op_23f0_13_ff;
+extern cpuop_func_ce op_23f8_13_nf;
+extern cpuop_func_ce op_23f8_13_ff;
+extern cpuop_func_ce op_23f9_13_nf;
+extern cpuop_func_ce op_23f9_13_ff;
+extern cpuop_func_ce op_23fa_13_nf;
+extern cpuop_func_ce op_23fa_13_ff;
+extern cpuop_func_ce op_23fb_13_nf;
+extern cpuop_func_ce op_23fb_13_ff;
+extern cpuop_func_ce op_23fc_13_nf;
+extern cpuop_func_ce op_23fc_13_ff;
+extern cpuop_func_ce op_3000_13_nf;
+extern cpuop_func_ce op_3000_13_ff;
+extern cpuop_func_ce op_3008_13_nf;
+extern cpuop_func_ce op_3008_13_ff;
+extern cpuop_func_ce op_3010_13_nf;
+extern cpuop_func_ce op_3010_13_ff;
+extern cpuop_func_ce op_3018_13_nf;
+extern cpuop_func_ce op_3018_13_ff;
+extern cpuop_func_ce op_3020_13_nf;
+extern cpuop_func_ce op_3020_13_ff;
+extern cpuop_func_ce op_3028_13_nf;
+extern cpuop_func_ce op_3028_13_ff;
+extern cpuop_func_ce op_3030_13_nf;
+extern cpuop_func_ce op_3030_13_ff;
+extern cpuop_func_ce op_3038_13_nf;
+extern cpuop_func_ce op_3038_13_ff;
+extern cpuop_func_ce op_3039_13_nf;
+extern cpuop_func_ce op_3039_13_ff;
+extern cpuop_func_ce op_303a_13_nf;
+extern cpuop_func_ce op_303a_13_ff;
+extern cpuop_func_ce op_303b_13_nf;
+extern cpuop_func_ce op_303b_13_ff;
+extern cpuop_func_ce op_303c_13_nf;
+extern cpuop_func_ce op_303c_13_ff;
+extern cpuop_func_ce op_3040_13_nf;
+extern cpuop_func_ce op_3040_13_ff;
+extern cpuop_func_ce op_3048_13_nf;
+extern cpuop_func_ce op_3048_13_ff;
+extern cpuop_func_ce op_3050_13_nf;
+extern cpuop_func_ce op_3050_13_ff;
+extern cpuop_func_ce op_3058_13_nf;
+extern cpuop_func_ce op_3058_13_ff;
+extern cpuop_func_ce op_3060_13_nf;
+extern cpuop_func_ce op_3060_13_ff;
+extern cpuop_func_ce op_3068_13_nf;
+extern cpuop_func_ce op_3068_13_ff;
+extern cpuop_func_ce op_3070_13_nf;
+extern cpuop_func_ce op_3070_13_ff;
+extern cpuop_func_ce op_3078_13_nf;
+extern cpuop_func_ce op_3078_13_ff;
+extern cpuop_func_ce op_3079_13_nf;
+extern cpuop_func_ce op_3079_13_ff;
+extern cpuop_func_ce op_307a_13_nf;
+extern cpuop_func_ce op_307a_13_ff;
+extern cpuop_func_ce op_307b_13_nf;
+extern cpuop_func_ce op_307b_13_ff;
+extern cpuop_func_ce op_307c_13_nf;
+extern cpuop_func_ce op_307c_13_ff;
+extern cpuop_func_ce op_3080_13_nf;
+extern cpuop_func_ce op_3080_13_ff;
+extern cpuop_func_ce op_3088_13_nf;
+extern cpuop_func_ce op_3088_13_ff;
+extern cpuop_func_ce op_3090_13_nf;
+extern cpuop_func_ce op_3090_13_ff;
+extern cpuop_func_ce op_3098_13_nf;
+extern cpuop_func_ce op_3098_13_ff;
+extern cpuop_func_ce op_30a0_13_nf;
+extern cpuop_func_ce op_30a0_13_ff;
+extern cpuop_func_ce op_30a8_13_nf;
+extern cpuop_func_ce op_30a8_13_ff;
+extern cpuop_func_ce op_30b0_13_nf;
+extern cpuop_func_ce op_30b0_13_ff;
+extern cpuop_func_ce op_30b8_13_nf;
+extern cpuop_func_ce op_30b8_13_ff;
+extern cpuop_func_ce op_30b9_13_nf;
+extern cpuop_func_ce op_30b9_13_ff;
+extern cpuop_func_ce op_30ba_13_nf;
+extern cpuop_func_ce op_30ba_13_ff;
+extern cpuop_func_ce op_30bb_13_nf;
+extern cpuop_func_ce op_30bb_13_ff;
+extern cpuop_func_ce op_30bc_13_nf;
+extern cpuop_func_ce op_30bc_13_ff;
+extern cpuop_func_ce op_30c0_13_nf;
+extern cpuop_func_ce op_30c0_13_ff;
+extern cpuop_func_ce op_30c8_13_nf;
+extern cpuop_func_ce op_30c8_13_ff;
+extern cpuop_func_ce op_30d0_13_nf;
+extern cpuop_func_ce op_30d0_13_ff;
+extern cpuop_func_ce op_30d8_13_nf;
+extern cpuop_func_ce op_30d8_13_ff;
+extern cpuop_func_ce op_30e0_13_nf;
+extern cpuop_func_ce op_30e0_13_ff;
+extern cpuop_func_ce op_30e8_13_nf;
+extern cpuop_func_ce op_30e8_13_ff;
+extern cpuop_func_ce op_30f0_13_nf;
+extern cpuop_func_ce op_30f0_13_ff;
+extern cpuop_func_ce op_30f8_13_nf;
+extern cpuop_func_ce op_30f8_13_ff;
+extern cpuop_func_ce op_30f9_13_nf;
+extern cpuop_func_ce op_30f9_13_ff;
+extern cpuop_func_ce op_30fa_13_nf;
+extern cpuop_func_ce op_30fa_13_ff;
+extern cpuop_func_ce op_30fb_13_nf;
+extern cpuop_func_ce op_30fb_13_ff;
+extern cpuop_func_ce op_30fc_13_nf;
+extern cpuop_func_ce op_30fc_13_ff;
+extern cpuop_func_ce op_3100_13_nf;
+extern cpuop_func_ce op_3100_13_ff;
+extern cpuop_func_ce op_3108_13_nf;
+extern cpuop_func_ce op_3108_13_ff;
+extern cpuop_func_ce op_3110_13_nf;
+extern cpuop_func_ce op_3110_13_ff;
+extern cpuop_func_ce op_3118_13_nf;
+extern cpuop_func_ce op_3118_13_ff;
+extern cpuop_func_ce op_3120_13_nf;
+extern cpuop_func_ce op_3120_13_ff;
+extern cpuop_func_ce op_3128_13_nf;
+extern cpuop_func_ce op_3128_13_ff;
+extern cpuop_func_ce op_3130_13_nf;
+extern cpuop_func_ce op_3130_13_ff;
+extern cpuop_func_ce op_3138_13_nf;
+extern cpuop_func_ce op_3138_13_ff;
+extern cpuop_func_ce op_3139_13_nf;
+extern cpuop_func_ce op_3139_13_ff;
+extern cpuop_func_ce op_313a_13_nf;
+extern cpuop_func_ce op_313a_13_ff;
+extern cpuop_func_ce op_313b_13_nf;
+extern cpuop_func_ce op_313b_13_ff;
+extern cpuop_func_ce op_313c_13_nf;
+extern cpuop_func_ce op_313c_13_ff;
+extern cpuop_func_ce op_3140_13_nf;
+extern cpuop_func_ce op_3140_13_ff;
+extern cpuop_func_ce op_3148_13_nf;
+extern cpuop_func_ce op_3148_13_ff;
+extern cpuop_func_ce op_3150_13_nf;
+extern cpuop_func_ce op_3150_13_ff;
+extern cpuop_func_ce op_3158_13_nf;
+extern cpuop_func_ce op_3158_13_ff;
+extern cpuop_func_ce op_3160_13_nf;
+extern cpuop_func_ce op_3160_13_ff;
+extern cpuop_func_ce op_3168_13_nf;
+extern cpuop_func_ce op_3168_13_ff;
+extern cpuop_func_ce op_3170_13_nf;
+extern cpuop_func_ce op_3170_13_ff;
+extern cpuop_func_ce op_3178_13_nf;
+extern cpuop_func_ce op_3178_13_ff;
+extern cpuop_func_ce op_3179_13_nf;
+extern cpuop_func_ce op_3179_13_ff;
+extern cpuop_func_ce op_317a_13_nf;
+extern cpuop_func_ce op_317a_13_ff;
+extern cpuop_func_ce op_317b_13_nf;
+extern cpuop_func_ce op_317b_13_ff;
+extern cpuop_func_ce op_317c_13_nf;
+extern cpuop_func_ce op_317c_13_ff;
+extern cpuop_func_ce op_3180_13_nf;
+extern cpuop_func_ce op_3180_13_ff;
+extern cpuop_func_ce op_3188_13_nf;
+extern cpuop_func_ce op_3188_13_ff;
+extern cpuop_func_ce op_3190_13_nf;
+extern cpuop_func_ce op_3190_13_ff;
+extern cpuop_func_ce op_3198_13_nf;
+extern cpuop_func_ce op_3198_13_ff;
+extern cpuop_func_ce op_31a0_13_nf;
+extern cpuop_func_ce op_31a0_13_ff;
+extern cpuop_func_ce op_31a8_13_nf;
+extern cpuop_func_ce op_31a8_13_ff;
+extern cpuop_func_ce op_31b0_13_nf;
+extern cpuop_func_ce op_31b0_13_ff;
+extern cpuop_func_ce op_31b8_13_nf;
+extern cpuop_func_ce op_31b8_13_ff;
+extern cpuop_func_ce op_31b9_13_nf;
+extern cpuop_func_ce op_31b9_13_ff;
+extern cpuop_func_ce op_31ba_13_nf;
+extern cpuop_func_ce op_31ba_13_ff;
+extern cpuop_func_ce op_31bb_13_nf;
+extern cpuop_func_ce op_31bb_13_ff;
+extern cpuop_func_ce op_31bc_13_nf;
+extern cpuop_func_ce op_31bc_13_ff;
+extern cpuop_func_ce op_31c0_13_nf;
+extern cpuop_func_ce op_31c0_13_ff;
+extern cpuop_func_ce op_31c8_13_nf;
+extern cpuop_func_ce op_31c8_13_ff;
+extern cpuop_func_ce op_31d0_13_nf;
+extern cpuop_func_ce op_31d0_13_ff;
+extern cpuop_func_ce op_31d8_13_nf;
+extern cpuop_func_ce op_31d8_13_ff;
+extern cpuop_func_ce op_31e0_13_nf;
+extern cpuop_func_ce op_31e0_13_ff;
+extern cpuop_func_ce op_31e8_13_nf;
+extern cpuop_func_ce op_31e8_13_ff;
+extern cpuop_func_ce op_31f0_13_nf;
+extern cpuop_func_ce op_31f0_13_ff;
+extern cpuop_func_ce op_31f8_13_nf;
+extern cpuop_func_ce op_31f8_13_ff;
+extern cpuop_func_ce op_31f9_13_nf;
+extern cpuop_func_ce op_31f9_13_ff;
+extern cpuop_func_ce op_31fa_13_nf;
+extern cpuop_func_ce op_31fa_13_ff;
+extern cpuop_func_ce op_31fb_13_nf;
+extern cpuop_func_ce op_31fb_13_ff;
+extern cpuop_func_ce op_31fc_13_nf;
+extern cpuop_func_ce op_31fc_13_ff;
+extern cpuop_func_ce op_33c0_13_nf;
+extern cpuop_func_ce op_33c0_13_ff;
+extern cpuop_func_ce op_33c8_13_nf;
+extern cpuop_func_ce op_33c8_13_ff;
+extern cpuop_func_ce op_33d0_13_nf;
+extern cpuop_func_ce op_33d0_13_ff;
+extern cpuop_func_ce op_33d8_13_nf;
+extern cpuop_func_ce op_33d8_13_ff;
+extern cpuop_func_ce op_33e0_13_nf;
+extern cpuop_func_ce op_33e0_13_ff;
+extern cpuop_func_ce op_33e8_13_nf;
+extern cpuop_func_ce op_33e8_13_ff;
+extern cpuop_func_ce op_33f0_13_nf;
+extern cpuop_func_ce op_33f0_13_ff;
+extern cpuop_func_ce op_33f8_13_nf;
+extern cpuop_func_ce op_33f8_13_ff;
+extern cpuop_func_ce op_33f9_13_nf;
+extern cpuop_func_ce op_33f9_13_ff;
+extern cpuop_func_ce op_33fa_13_nf;
+extern cpuop_func_ce op_33fa_13_ff;
+extern cpuop_func_ce op_33fb_13_nf;
+extern cpuop_func_ce op_33fb_13_ff;
+extern cpuop_func_ce op_33fc_13_nf;
+extern cpuop_func_ce op_33fc_13_ff;
+extern cpuop_func_ce op_4000_13_nf;
+extern cpuop_func_ce op_4000_13_ff;
+extern cpuop_func_ce op_4010_13_nf;
+extern cpuop_func_ce op_4010_13_ff;
+extern cpuop_func_ce op_4018_13_nf;
+extern cpuop_func_ce op_4018_13_ff;
+extern cpuop_func_ce op_4020_13_nf;
+extern cpuop_func_ce op_4020_13_ff;
+extern cpuop_func_ce op_4028_13_nf;
+extern cpuop_func_ce op_4028_13_ff;
+extern cpuop_func_ce op_4030_13_nf;
+extern cpuop_func_ce op_4030_13_ff;
+extern cpuop_func_ce op_4038_13_nf;
+extern cpuop_func_ce op_4038_13_ff;
+extern cpuop_func_ce op_4039_13_nf;
+extern cpuop_func_ce op_4039_13_ff;
+extern cpuop_func_ce op_4040_13_nf;
+extern cpuop_func_ce op_4040_13_ff;
+extern cpuop_func_ce op_4050_13_nf;
+extern cpuop_func_ce op_4050_13_ff;
+extern cpuop_func_ce op_4058_13_nf;
+extern cpuop_func_ce op_4058_13_ff;
+extern cpuop_func_ce op_4060_13_nf;
+extern cpuop_func_ce op_4060_13_ff;
+extern cpuop_func_ce op_4068_13_nf;
+extern cpuop_func_ce op_4068_13_ff;
+extern cpuop_func_ce op_4070_13_nf;
+extern cpuop_func_ce op_4070_13_ff;
+extern cpuop_func_ce op_4078_13_nf;
+extern cpuop_func_ce op_4078_13_ff;
+extern cpuop_func_ce op_4079_13_nf;
+extern cpuop_func_ce op_4079_13_ff;
+extern cpuop_func_ce op_4080_13_nf;
+extern cpuop_func_ce op_4080_13_ff;
+extern cpuop_func_ce op_4090_13_nf;
+extern cpuop_func_ce op_4090_13_ff;
+extern cpuop_func_ce op_4098_13_nf;
+extern cpuop_func_ce op_4098_13_ff;
+extern cpuop_func_ce op_40a0_13_nf;
+extern cpuop_func_ce op_40a0_13_ff;
+extern cpuop_func_ce op_40a8_13_nf;
+extern cpuop_func_ce op_40a8_13_ff;
+extern cpuop_func_ce op_40b0_13_nf;
+extern cpuop_func_ce op_40b0_13_ff;
+extern cpuop_func_ce op_40b8_13_nf;
+extern cpuop_func_ce op_40b8_13_ff;
+extern cpuop_func_ce op_40b9_13_nf;
+extern cpuop_func_ce op_40b9_13_ff;
+extern cpuop_func_ce op_40c0_13_nf;
+extern cpuop_func_ce op_40c0_13_ff;
+extern cpuop_func_ce op_40d0_13_nf;
+extern cpuop_func_ce op_40d0_13_ff;
+extern cpuop_func_ce op_40d8_13_nf;
+extern cpuop_func_ce op_40d8_13_ff;
+extern cpuop_func_ce op_40e0_13_nf;
+extern cpuop_func_ce op_40e0_13_ff;
+extern cpuop_func_ce op_40e8_13_nf;
+extern cpuop_func_ce op_40e8_13_ff;
+extern cpuop_func_ce op_40f0_13_nf;
+extern cpuop_func_ce op_40f0_13_ff;
+extern cpuop_func_ce op_40f8_13_nf;
+extern cpuop_func_ce op_40f8_13_ff;
+extern cpuop_func_ce op_40f9_13_nf;
+extern cpuop_func_ce op_40f9_13_ff;
+extern cpuop_func_ce op_4180_13_nf;
+extern cpuop_func_ce op_4180_13_ff;
+extern cpuop_func_ce op_4190_13_nf;
+extern cpuop_func_ce op_4190_13_ff;
+extern cpuop_func_ce op_4198_13_nf;
+extern cpuop_func_ce op_4198_13_ff;
+extern cpuop_func_ce op_41a0_13_nf;
+extern cpuop_func_ce op_41a0_13_ff;
+extern cpuop_func_ce op_41a8_13_nf;
+extern cpuop_func_ce op_41a8_13_ff;
+extern cpuop_func_ce op_41b0_13_nf;
+extern cpuop_func_ce op_41b0_13_ff;
+extern cpuop_func_ce op_41b8_13_nf;
+extern cpuop_func_ce op_41b8_13_ff;
+extern cpuop_func_ce op_41b9_13_nf;
+extern cpuop_func_ce op_41b9_13_ff;
+extern cpuop_func_ce op_41ba_13_nf;
+extern cpuop_func_ce op_41ba_13_ff;
+extern cpuop_func_ce op_41bb_13_nf;
+extern cpuop_func_ce op_41bb_13_ff;
+extern cpuop_func_ce op_41bc_13_nf;
+extern cpuop_func_ce op_41bc_13_ff;
+extern cpuop_func_ce op_41d0_13_nf;
+extern cpuop_func_ce op_41d0_13_ff;
+extern cpuop_func_ce op_41e8_13_nf;
+extern cpuop_func_ce op_41e8_13_ff;
+extern cpuop_func_ce op_41f0_13_nf;
+extern cpuop_func_ce op_41f0_13_ff;
+extern cpuop_func_ce op_41f8_13_nf;
+extern cpuop_func_ce op_41f8_13_ff;
+extern cpuop_func_ce op_41f9_13_nf;
+extern cpuop_func_ce op_41f9_13_ff;
+extern cpuop_func_ce op_41fa_13_nf;
+extern cpuop_func_ce op_41fa_13_ff;
+extern cpuop_func_ce op_41fb_13_nf;
+extern cpuop_func_ce op_41fb_13_ff;
+extern cpuop_func_ce op_4200_13_nf;
+extern cpuop_func_ce op_4200_13_ff;
+extern cpuop_func_ce op_4210_13_nf;
+extern cpuop_func_ce op_4210_13_ff;
+extern cpuop_func_ce op_4218_13_nf;
+extern cpuop_func_ce op_4218_13_ff;
+extern cpuop_func_ce op_4220_13_nf;
+extern cpuop_func_ce op_4220_13_ff;
+extern cpuop_func_ce op_4228_13_nf;
+extern cpuop_func_ce op_4228_13_ff;
+extern cpuop_func_ce op_4230_13_nf;
+extern cpuop_func_ce op_4230_13_ff;
+extern cpuop_func_ce op_4238_13_nf;
+extern cpuop_func_ce op_4238_13_ff;
+extern cpuop_func_ce op_4239_13_nf;
+extern cpuop_func_ce op_4239_13_ff;
+extern cpuop_func_ce op_4240_13_nf;
+extern cpuop_func_ce op_4240_13_ff;
+extern cpuop_func_ce op_4250_13_nf;
+extern cpuop_func_ce op_4250_13_ff;
+extern cpuop_func_ce op_4258_13_nf;
+extern cpuop_func_ce op_4258_13_ff;
+extern cpuop_func_ce op_4260_13_nf;
+extern cpuop_func_ce op_4260_13_ff;
+extern cpuop_func_ce op_4268_13_nf;
+extern cpuop_func_ce op_4268_13_ff;
+extern cpuop_func_ce op_4270_13_nf;
+extern cpuop_func_ce op_4270_13_ff;
+extern cpuop_func_ce op_4278_13_nf;
+extern cpuop_func_ce op_4278_13_ff;
+extern cpuop_func_ce op_4279_13_nf;
+extern cpuop_func_ce op_4279_13_ff;
+extern cpuop_func_ce op_4280_13_nf;
+extern cpuop_func_ce op_4280_13_ff;
+extern cpuop_func_ce op_4290_13_nf;
+extern cpuop_func_ce op_4290_13_ff;
+extern cpuop_func_ce op_4298_13_nf;
+extern cpuop_func_ce op_4298_13_ff;
+extern cpuop_func_ce op_42a0_13_nf;
+extern cpuop_func_ce op_42a0_13_ff;
+extern cpuop_func_ce op_42a8_13_nf;
+extern cpuop_func_ce op_42a8_13_ff;
+extern cpuop_func_ce op_42b0_13_nf;
+extern cpuop_func_ce op_42b0_13_ff;
+extern cpuop_func_ce op_42b8_13_nf;
+extern cpuop_func_ce op_42b8_13_ff;
+extern cpuop_func_ce op_42b9_13_nf;
+extern cpuop_func_ce op_42b9_13_ff;
+extern cpuop_func_ce op_42c0_13_nf;
+extern cpuop_func_ce op_42c0_13_ff;
+extern cpuop_func_ce op_42d0_13_nf;
+extern cpuop_func_ce op_42d0_13_ff;
+extern cpuop_func_ce op_42d8_13_nf;
+extern cpuop_func_ce op_42d8_13_ff;
+extern cpuop_func_ce op_42e0_13_nf;
+extern cpuop_func_ce op_42e0_13_ff;
+extern cpuop_func_ce op_42e8_13_nf;
+extern cpuop_func_ce op_42e8_13_ff;
+extern cpuop_func_ce op_42f0_13_nf;
+extern cpuop_func_ce op_42f0_13_ff;
+extern cpuop_func_ce op_42f8_13_nf;
+extern cpuop_func_ce op_42f8_13_ff;
+extern cpuop_func_ce op_42f9_13_nf;
+extern cpuop_func_ce op_42f9_13_ff;
+extern cpuop_func_ce op_4400_13_nf;
+extern cpuop_func_ce op_4400_13_ff;
+extern cpuop_func_ce op_4410_13_nf;
+extern cpuop_func_ce op_4410_13_ff;
+extern cpuop_func_ce op_4418_13_nf;
+extern cpuop_func_ce op_4418_13_ff;
+extern cpuop_func_ce op_4420_13_nf;
+extern cpuop_func_ce op_4420_13_ff;
+extern cpuop_func_ce op_4428_13_nf;
+extern cpuop_func_ce op_4428_13_ff;
+extern cpuop_func_ce op_4430_13_nf;
+extern cpuop_func_ce op_4430_13_ff;
+extern cpuop_func_ce op_4438_13_nf;
+extern cpuop_func_ce op_4438_13_ff;
+extern cpuop_func_ce op_4439_13_nf;
+extern cpuop_func_ce op_4439_13_ff;
+extern cpuop_func_ce op_4440_13_nf;
+extern cpuop_func_ce op_4440_13_ff;
+extern cpuop_func_ce op_4450_13_nf;
+extern cpuop_func_ce op_4450_13_ff;
+extern cpuop_func_ce op_4458_13_nf;
+extern cpuop_func_ce op_4458_13_ff;
+extern cpuop_func_ce op_4460_13_nf;
+extern cpuop_func_ce op_4460_13_ff;
+extern cpuop_func_ce op_4468_13_nf;
+extern cpuop_func_ce op_4468_13_ff;
+extern cpuop_func_ce op_4470_13_nf;
+extern cpuop_func_ce op_4470_13_ff;
+extern cpuop_func_ce op_4478_13_nf;
+extern cpuop_func_ce op_4478_13_ff;
+extern cpuop_func_ce op_4479_13_nf;
+extern cpuop_func_ce op_4479_13_ff;
+extern cpuop_func_ce op_4480_13_nf;
+extern cpuop_func_ce op_4480_13_ff;
+extern cpuop_func_ce op_4490_13_nf;
+extern cpuop_func_ce op_4490_13_ff;
+extern cpuop_func_ce op_4498_13_nf;
+extern cpuop_func_ce op_4498_13_ff;
+extern cpuop_func_ce op_44a0_13_nf;
+extern cpuop_func_ce op_44a0_13_ff;
+extern cpuop_func_ce op_44a8_13_nf;
+extern cpuop_func_ce op_44a8_13_ff;
+extern cpuop_func_ce op_44b0_13_nf;
+extern cpuop_func_ce op_44b0_13_ff;
+extern cpuop_func_ce op_44b8_13_nf;
+extern cpuop_func_ce op_44b8_13_ff;
+extern cpuop_func_ce op_44b9_13_nf;
+extern cpuop_func_ce op_44b9_13_ff;
+extern cpuop_func_ce op_44c0_13_nf;
+extern cpuop_func_ce op_44c0_13_ff;
+extern cpuop_func_ce op_44d0_13_nf;
+extern cpuop_func_ce op_44d0_13_ff;
+extern cpuop_func_ce op_44d8_13_nf;
+extern cpuop_func_ce op_44d8_13_ff;
+extern cpuop_func_ce op_44e0_13_nf;
+extern cpuop_func_ce op_44e0_13_ff;
+extern cpuop_func_ce op_44e8_13_nf;
+extern cpuop_func_ce op_44e8_13_ff;
+extern cpuop_func_ce op_44f0_13_nf;
+extern cpuop_func_ce op_44f0_13_ff;
+extern cpuop_func_ce op_44f8_13_nf;
+extern cpuop_func_ce op_44f8_13_ff;
+extern cpuop_func_ce op_44f9_13_nf;
+extern cpuop_func_ce op_44f9_13_ff;
+extern cpuop_func_ce op_44fa_13_nf;
+extern cpuop_func_ce op_44fa_13_ff;
+extern cpuop_func_ce op_44fb_13_nf;
+extern cpuop_func_ce op_44fb_13_ff;
+extern cpuop_func_ce op_44fc_13_nf;
+extern cpuop_func_ce op_44fc_13_ff;
+extern cpuop_func_ce op_4600_13_nf;
+extern cpuop_func_ce op_4600_13_ff;
+extern cpuop_func_ce op_4610_13_nf;
+extern cpuop_func_ce op_4610_13_ff;
+extern cpuop_func_ce op_4618_13_nf;
+extern cpuop_func_ce op_4618_13_ff;
+extern cpuop_func_ce op_4620_13_nf;
+extern cpuop_func_ce op_4620_13_ff;
+extern cpuop_func_ce op_4628_13_nf;
+extern cpuop_func_ce op_4628_13_ff;
+extern cpuop_func_ce op_4630_13_nf;
+extern cpuop_func_ce op_4630_13_ff;
+extern cpuop_func_ce op_4638_13_nf;
+extern cpuop_func_ce op_4638_13_ff;
+extern cpuop_func_ce op_4639_13_nf;
+extern cpuop_func_ce op_4639_13_ff;
+extern cpuop_func_ce op_4640_13_nf;
+extern cpuop_func_ce op_4640_13_ff;
+extern cpuop_func_ce op_4650_13_nf;
+extern cpuop_func_ce op_4650_13_ff;
+extern cpuop_func_ce op_4658_13_nf;
+extern cpuop_func_ce op_4658_13_ff;
+extern cpuop_func_ce op_4660_13_nf;
+extern cpuop_func_ce op_4660_13_ff;
+extern cpuop_func_ce op_4668_13_nf;
+extern cpuop_func_ce op_4668_13_ff;
+extern cpuop_func_ce op_4670_13_nf;
+extern cpuop_func_ce op_4670_13_ff;
+extern cpuop_func_ce op_4678_13_nf;
+extern cpuop_func_ce op_4678_13_ff;
+extern cpuop_func_ce op_4679_13_nf;
+extern cpuop_func_ce op_4679_13_ff;
+extern cpuop_func_ce op_4680_13_nf;
+extern cpuop_func_ce op_4680_13_ff;
+extern cpuop_func_ce op_4690_13_nf;
+extern cpuop_func_ce op_4690_13_ff;
+extern cpuop_func_ce op_4698_13_nf;
+extern cpuop_func_ce op_4698_13_ff;
+extern cpuop_func_ce op_46a0_13_nf;
+extern cpuop_func_ce op_46a0_13_ff;
+extern cpuop_func_ce op_46a8_13_nf;
+extern cpuop_func_ce op_46a8_13_ff;
+extern cpuop_func_ce op_46b0_13_nf;
+extern cpuop_func_ce op_46b0_13_ff;
+extern cpuop_func_ce op_46b8_13_nf;
+extern cpuop_func_ce op_46b8_13_ff;
+extern cpuop_func_ce op_46b9_13_nf;
+extern cpuop_func_ce op_46b9_13_ff;
+extern cpuop_func_ce op_46c0_13_nf;
+extern cpuop_func_ce op_46c0_13_ff;
+extern cpuop_func_ce op_46d0_13_nf;
+extern cpuop_func_ce op_46d0_13_ff;
+extern cpuop_func_ce op_46d8_13_nf;
+extern cpuop_func_ce op_46d8_13_ff;
+extern cpuop_func_ce op_46e0_13_nf;
+extern cpuop_func_ce op_46e0_13_ff;
+extern cpuop_func_ce op_46e8_13_nf;
+extern cpuop_func_ce op_46e8_13_ff;
+extern cpuop_func_ce op_46f0_13_nf;
+extern cpuop_func_ce op_46f0_13_ff;
+extern cpuop_func_ce op_46f8_13_nf;
+extern cpuop_func_ce op_46f8_13_ff;
+extern cpuop_func_ce op_46f9_13_nf;
+extern cpuop_func_ce op_46f9_13_ff;
+extern cpuop_func_ce op_46fa_13_nf;
+extern cpuop_func_ce op_46fa_13_ff;
+extern cpuop_func_ce op_46fb_13_nf;
+extern cpuop_func_ce op_46fb_13_ff;
+extern cpuop_func_ce op_46fc_13_nf;
+extern cpuop_func_ce op_46fc_13_ff;
+extern cpuop_func_ce op_4800_13_nf;
+extern cpuop_func_ce op_4800_13_ff;
+extern cpuop_func_ce op_4810_13_nf;
+extern cpuop_func_ce op_4810_13_ff;
+extern cpuop_func_ce op_4818_13_nf;
+extern cpuop_func_ce op_4818_13_ff;
+extern cpuop_func_ce op_4820_13_nf;
+extern cpuop_func_ce op_4820_13_ff;
+extern cpuop_func_ce op_4828_13_nf;
+extern cpuop_func_ce op_4828_13_ff;
+extern cpuop_func_ce op_4830_13_nf;
+extern cpuop_func_ce op_4830_13_ff;
+extern cpuop_func_ce op_4838_13_nf;
+extern cpuop_func_ce op_4838_13_ff;
+extern cpuop_func_ce op_4839_13_nf;
+extern cpuop_func_ce op_4839_13_ff;
+extern cpuop_func_ce op_4840_13_nf;
+extern cpuop_func_ce op_4840_13_ff;
+extern cpuop_func_ce op_4850_13_nf;
+extern cpuop_func_ce op_4850_13_ff;
+extern cpuop_func_ce op_4868_13_nf;
+extern cpuop_func_ce op_4868_13_ff;
+extern cpuop_func_ce op_4870_13_nf;
+extern cpuop_func_ce op_4870_13_ff;
+extern cpuop_func_ce op_4878_13_nf;
+extern cpuop_func_ce op_4878_13_ff;
+extern cpuop_func_ce op_4879_13_nf;
+extern cpuop_func_ce op_4879_13_ff;
+extern cpuop_func_ce op_487a_13_nf;
+extern cpuop_func_ce op_487a_13_ff;
+extern cpuop_func_ce op_487b_13_nf;
+extern cpuop_func_ce op_487b_13_ff;
+extern cpuop_func_ce op_4880_13_nf;
+extern cpuop_func_ce op_4880_13_ff;
+extern cpuop_func_ce op_4890_13_nf;
+extern cpuop_func_ce op_4890_13_ff;
+extern cpuop_func_ce op_48a0_13_nf;
+extern cpuop_func_ce op_48a0_13_ff;
+extern cpuop_func_ce op_48a8_13_nf;
+extern cpuop_func_ce op_48a8_13_ff;
+extern cpuop_func_ce op_48b0_13_nf;
+extern cpuop_func_ce op_48b0_13_ff;
+extern cpuop_func_ce op_48b8_13_nf;
+extern cpuop_func_ce op_48b8_13_ff;
+extern cpuop_func_ce op_48b9_13_nf;
+extern cpuop_func_ce op_48b9_13_ff;
+extern cpuop_func_ce op_48c0_13_nf;
+extern cpuop_func_ce op_48c0_13_ff;
+extern cpuop_func_ce op_48d0_13_nf;
+extern cpuop_func_ce op_48d0_13_ff;
+extern cpuop_func_ce op_48e0_13_nf;
+extern cpuop_func_ce op_48e0_13_ff;
+extern cpuop_func_ce op_48e8_13_nf;
+extern cpuop_func_ce op_48e8_13_ff;
+extern cpuop_func_ce op_48f0_13_nf;
+extern cpuop_func_ce op_48f0_13_ff;
+extern cpuop_func_ce op_48f8_13_nf;
+extern cpuop_func_ce op_48f8_13_ff;
+extern cpuop_func_ce op_48f9_13_nf;
+extern cpuop_func_ce op_48f9_13_ff;
+extern cpuop_func_ce op_4a00_13_nf;
+extern cpuop_func_ce op_4a00_13_ff;
+extern cpuop_func_ce op_4a10_13_nf;
+extern cpuop_func_ce op_4a10_13_ff;
+extern cpuop_func_ce op_4a18_13_nf;
+extern cpuop_func_ce op_4a18_13_ff;
+extern cpuop_func_ce op_4a20_13_nf;
+extern cpuop_func_ce op_4a20_13_ff;
+extern cpuop_func_ce op_4a28_13_nf;
+extern cpuop_func_ce op_4a28_13_ff;
+extern cpuop_func_ce op_4a30_13_nf;
+extern cpuop_func_ce op_4a30_13_ff;
+extern cpuop_func_ce op_4a38_13_nf;
+extern cpuop_func_ce op_4a38_13_ff;
+extern cpuop_func_ce op_4a39_13_nf;
+extern cpuop_func_ce op_4a39_13_ff;
+extern cpuop_func_ce op_4a40_13_nf;
+extern cpuop_func_ce op_4a40_13_ff;
+extern cpuop_func_ce op_4a50_13_nf;
+extern cpuop_func_ce op_4a50_13_ff;
+extern cpuop_func_ce op_4a58_13_nf;
+extern cpuop_func_ce op_4a58_13_ff;
+extern cpuop_func_ce op_4a60_13_nf;
+extern cpuop_func_ce op_4a60_13_ff;
+extern cpuop_func_ce op_4a68_13_nf;
+extern cpuop_func_ce op_4a68_13_ff;
+extern cpuop_func_ce op_4a70_13_nf;
+extern cpuop_func_ce op_4a70_13_ff;
+extern cpuop_func_ce op_4a78_13_nf;
+extern cpuop_func_ce op_4a78_13_ff;
+extern cpuop_func_ce op_4a79_13_nf;
+extern cpuop_func_ce op_4a79_13_ff;
+extern cpuop_func_ce op_4a80_13_nf;
+extern cpuop_func_ce op_4a80_13_ff;
+extern cpuop_func_ce op_4a90_13_nf;
+extern cpuop_func_ce op_4a90_13_ff;
+extern cpuop_func_ce op_4a98_13_nf;
+extern cpuop_func_ce op_4a98_13_ff;
+extern cpuop_func_ce op_4aa0_13_nf;
+extern cpuop_func_ce op_4aa0_13_ff;
+extern cpuop_func_ce op_4aa8_13_nf;
+extern cpuop_func_ce op_4aa8_13_ff;
+extern cpuop_func_ce op_4ab0_13_nf;
+extern cpuop_func_ce op_4ab0_13_ff;
+extern cpuop_func_ce op_4ab8_13_nf;
+extern cpuop_func_ce op_4ab8_13_ff;
+extern cpuop_func_ce op_4ab9_13_nf;
+extern cpuop_func_ce op_4ab9_13_ff;
+extern cpuop_func_ce op_4ac0_13_nf;
+extern cpuop_func_ce op_4ac0_13_ff;
+extern cpuop_func_ce op_4ad0_13_nf;
+extern cpuop_func_ce op_4ad0_13_ff;
+extern cpuop_func_ce op_4ad8_13_nf;
+extern cpuop_func_ce op_4ad8_13_ff;
+extern cpuop_func_ce op_4ae0_13_nf;
+extern cpuop_func_ce op_4ae0_13_ff;
+extern cpuop_func_ce op_4ae8_13_nf;
+extern cpuop_func_ce op_4ae8_13_ff;
+extern cpuop_func_ce op_4af0_13_nf;
+extern cpuop_func_ce op_4af0_13_ff;
+extern cpuop_func_ce op_4af8_13_nf;
+extern cpuop_func_ce op_4af8_13_ff;
+extern cpuop_func_ce op_4af9_13_nf;
+extern cpuop_func_ce op_4af9_13_ff;
+extern cpuop_func_ce op_4c90_13_nf;
+extern cpuop_func_ce op_4c90_13_ff;
+extern cpuop_func_ce op_4c98_13_nf;
+extern cpuop_func_ce op_4c98_13_ff;
+extern cpuop_func_ce op_4ca8_13_nf;
+extern cpuop_func_ce op_4ca8_13_ff;
+extern cpuop_func_ce op_4cb0_13_nf;
+extern cpuop_func_ce op_4cb0_13_ff;
+extern cpuop_func_ce op_4cb8_13_nf;
+extern cpuop_func_ce op_4cb8_13_ff;
+extern cpuop_func_ce op_4cb9_13_nf;
+extern cpuop_func_ce op_4cb9_13_ff;
+extern cpuop_func_ce op_4cba_13_nf;
+extern cpuop_func_ce op_4cba_13_ff;
+extern cpuop_func_ce op_4cbb_13_nf;
+extern cpuop_func_ce op_4cbb_13_ff;
+extern cpuop_func_ce op_4cd0_13_nf;
+extern cpuop_func_ce op_4cd0_13_ff;
+extern cpuop_func_ce op_4cd8_13_nf;
+extern cpuop_func_ce op_4cd8_13_ff;
+extern cpuop_func_ce op_4ce8_13_nf;
+extern cpuop_func_ce op_4ce8_13_ff;
+extern cpuop_func_ce op_4cf0_13_nf;
+extern cpuop_func_ce op_4cf0_13_ff;
+extern cpuop_func_ce op_4cf8_13_nf;
+extern cpuop_func_ce op_4cf8_13_ff;
+extern cpuop_func_ce op_4cf9_13_nf;
+extern cpuop_func_ce op_4cf9_13_ff;
+extern cpuop_func_ce op_4cfa_13_nf;
+extern cpuop_func_ce op_4cfa_13_ff;
+extern cpuop_func_ce op_4cfb_13_nf;
+extern cpuop_func_ce op_4cfb_13_ff;
+extern cpuop_func_ce op_4e40_13_nf;
+extern cpuop_func_ce op_4e40_13_ff;
+extern cpuop_func_ce op_4e50_13_nf;
+extern cpuop_func_ce op_4e50_13_ff;
+extern cpuop_func_ce op_4e58_13_nf;
+extern cpuop_func_ce op_4e58_13_ff;
+extern cpuop_func_ce op_4e60_13_nf;
+extern cpuop_func_ce op_4e60_13_ff;
+extern cpuop_func_ce op_4e68_13_nf;
+extern cpuop_func_ce op_4e68_13_ff;
+extern cpuop_func_ce op_4e70_13_nf;
+extern cpuop_func_ce op_4e70_13_ff;
+extern cpuop_func_ce op_4e71_13_nf;
+extern cpuop_func_ce op_4e71_13_ff;
+extern cpuop_func_ce op_4e72_13_nf;
+extern cpuop_func_ce op_4e72_13_ff;
+extern cpuop_func_ce op_4e73_13_nf;
+extern cpuop_func_ce op_4e73_13_ff;
+extern cpuop_func_ce op_4e74_13_nf;
+extern cpuop_func_ce op_4e74_13_ff;
+extern cpuop_func_ce op_4e75_13_nf;
+extern cpuop_func_ce op_4e75_13_ff;
+extern cpuop_func_ce op_4e76_13_nf;
+extern cpuop_func_ce op_4e76_13_ff;
+extern cpuop_func_ce op_4e77_13_nf;
+extern cpuop_func_ce op_4e77_13_ff;
+extern cpuop_func_ce op_4e7a_13_nf;
+extern cpuop_func_ce op_4e7a_13_ff;
+extern cpuop_func_ce op_4e7b_13_nf;
+extern cpuop_func_ce op_4e7b_13_ff;
+extern cpuop_func_ce op_4e90_13_nf;
+extern cpuop_func_ce op_4e90_13_ff;
+extern cpuop_func_ce op_4ea8_13_nf;
+extern cpuop_func_ce op_4ea8_13_ff;
+extern cpuop_func_ce op_4eb0_13_nf;
+extern cpuop_func_ce op_4eb0_13_ff;
+extern cpuop_func_ce op_4eb8_13_nf;
+extern cpuop_func_ce op_4eb8_13_ff;
+extern cpuop_func_ce op_4eb9_13_nf;
+extern cpuop_func_ce op_4eb9_13_ff;
+extern cpuop_func_ce op_4eba_13_nf;
+extern cpuop_func_ce op_4eba_13_ff;
+extern cpuop_func_ce op_4ebb_13_nf;
+extern cpuop_func_ce op_4ebb_13_ff;
+extern cpuop_func_ce op_4ed0_13_nf;
+extern cpuop_func_ce op_4ed0_13_ff;
+extern cpuop_func_ce op_4ee8_13_nf;
+extern cpuop_func_ce op_4ee8_13_ff;
+extern cpuop_func_ce op_4ef0_13_nf;
+extern cpuop_func_ce op_4ef0_13_ff;
+extern cpuop_func_ce op_4ef8_13_nf;
+extern cpuop_func_ce op_4ef8_13_ff;
+extern cpuop_func_ce op_4ef9_13_nf;
+extern cpuop_func_ce op_4ef9_13_ff;
+extern cpuop_func_ce op_4efa_13_nf;
+extern cpuop_func_ce op_4efa_13_ff;
+extern cpuop_func_ce op_4efb_13_nf;
+extern cpuop_func_ce op_4efb_13_ff;
+extern cpuop_func_ce op_5000_13_nf;
+extern cpuop_func_ce op_5000_13_ff;
+extern cpuop_func_ce op_5010_13_nf;
+extern cpuop_func_ce op_5010_13_ff;
+extern cpuop_func_ce op_5018_13_nf;
+extern cpuop_func_ce op_5018_13_ff;
+extern cpuop_func_ce op_5020_13_nf;
+extern cpuop_func_ce op_5020_13_ff;
+extern cpuop_func_ce op_5028_13_nf;
+extern cpuop_func_ce op_5028_13_ff;
+extern cpuop_func_ce op_5030_13_nf;
+extern cpuop_func_ce op_5030_13_ff;
+extern cpuop_func_ce op_5038_13_nf;
+extern cpuop_func_ce op_5038_13_ff;
+extern cpuop_func_ce op_5039_13_nf;
+extern cpuop_func_ce op_5039_13_ff;
+extern cpuop_func_ce op_5040_13_nf;
+extern cpuop_func_ce op_5040_13_ff;
+extern cpuop_func_ce op_5048_13_nf;
+extern cpuop_func_ce op_5048_13_ff;
+extern cpuop_func_ce op_5050_13_nf;
+extern cpuop_func_ce op_5050_13_ff;
+extern cpuop_func_ce op_5058_13_nf;
+extern cpuop_func_ce op_5058_13_ff;
+extern cpuop_func_ce op_5060_13_nf;
+extern cpuop_func_ce op_5060_13_ff;
+extern cpuop_func_ce op_5068_13_nf;
+extern cpuop_func_ce op_5068_13_ff;
+extern cpuop_func_ce op_5070_13_nf;
+extern cpuop_func_ce op_5070_13_ff;
+extern cpuop_func_ce op_5078_13_nf;
+extern cpuop_func_ce op_5078_13_ff;
+extern cpuop_func_ce op_5079_13_nf;
+extern cpuop_func_ce op_5079_13_ff;
+extern cpuop_func_ce op_5080_13_nf;
+extern cpuop_func_ce op_5080_13_ff;
+extern cpuop_func_ce op_5088_13_nf;
+extern cpuop_func_ce op_5088_13_ff;
+extern cpuop_func_ce op_5090_13_nf;
+extern cpuop_func_ce op_5090_13_ff;
+extern cpuop_func_ce op_5098_13_nf;
+extern cpuop_func_ce op_5098_13_ff;
+extern cpuop_func_ce op_50a0_13_nf;
+extern cpuop_func_ce op_50a0_13_ff;
+extern cpuop_func_ce op_50a8_13_nf;
+extern cpuop_func_ce op_50a8_13_ff;
+extern cpuop_func_ce op_50b0_13_nf;
+extern cpuop_func_ce op_50b0_13_ff;
+extern cpuop_func_ce op_50b8_13_nf;
+extern cpuop_func_ce op_50b8_13_ff;
+extern cpuop_func_ce op_50b9_13_nf;
+extern cpuop_func_ce op_50b9_13_ff;
+extern cpuop_func_ce op_50c0_13_nf;
+extern cpuop_func_ce op_50c0_13_ff;
+extern cpuop_func_ce op_50c8_13_nf;
+extern cpuop_func_ce op_50c8_13_ff;
+extern cpuop_func_ce op_50d0_13_nf;
+extern cpuop_func_ce op_50d0_13_ff;
+extern cpuop_func_ce op_50d8_13_nf;
+extern cpuop_func_ce op_50d8_13_ff;
+extern cpuop_func_ce op_50e0_13_nf;
+extern cpuop_func_ce op_50e0_13_ff;
+extern cpuop_func_ce op_50e8_13_nf;
+extern cpuop_func_ce op_50e8_13_ff;
+extern cpuop_func_ce op_50f0_13_nf;
+extern cpuop_func_ce op_50f0_13_ff;
+extern cpuop_func_ce op_50f8_13_nf;
+extern cpuop_func_ce op_50f8_13_ff;
+extern cpuop_func_ce op_50f9_13_nf;
+extern cpuop_func_ce op_50f9_13_ff;
+extern cpuop_func_ce op_5100_13_nf;
+extern cpuop_func_ce op_5100_13_ff;
+extern cpuop_func_ce op_5110_13_nf;
+extern cpuop_func_ce op_5110_13_ff;
+extern cpuop_func_ce op_5118_13_nf;
+extern cpuop_func_ce op_5118_13_ff;
+extern cpuop_func_ce op_5120_13_nf;
+extern cpuop_func_ce op_5120_13_ff;
+extern cpuop_func_ce op_5128_13_nf;
+extern cpuop_func_ce op_5128_13_ff;
+extern cpuop_func_ce op_5130_13_nf;
+extern cpuop_func_ce op_5130_13_ff;
+extern cpuop_func_ce op_5138_13_nf;
+extern cpuop_func_ce op_5138_13_ff;
+extern cpuop_func_ce op_5139_13_nf;
+extern cpuop_func_ce op_5139_13_ff;
+extern cpuop_func_ce op_5140_13_nf;
+extern cpuop_func_ce op_5140_13_ff;
+extern cpuop_func_ce op_5148_13_nf;
+extern cpuop_func_ce op_5148_13_ff;
+extern cpuop_func_ce op_5150_13_nf;
+extern cpuop_func_ce op_5150_13_ff;
+extern cpuop_func_ce op_5158_13_nf;
+extern cpuop_func_ce op_5158_13_ff;
+extern cpuop_func_ce op_5160_13_nf;
+extern cpuop_func_ce op_5160_13_ff;
+extern cpuop_func_ce op_5168_13_nf;
+extern cpuop_func_ce op_5168_13_ff;
+extern cpuop_func_ce op_5170_13_nf;
+extern cpuop_func_ce op_5170_13_ff;
+extern cpuop_func_ce op_5178_13_nf;
+extern cpuop_func_ce op_5178_13_ff;
+extern cpuop_func_ce op_5179_13_nf;
+extern cpuop_func_ce op_5179_13_ff;
+extern cpuop_func_ce op_5180_13_nf;
+extern cpuop_func_ce op_5180_13_ff;
+extern cpuop_func_ce op_5188_13_nf;
+extern cpuop_func_ce op_5188_13_ff;
+extern cpuop_func_ce op_5190_13_nf;
+extern cpuop_func_ce op_5190_13_ff;
+extern cpuop_func_ce op_5198_13_nf;
+extern cpuop_func_ce op_5198_13_ff;
+extern cpuop_func_ce op_51a0_13_nf;
+extern cpuop_func_ce op_51a0_13_ff;
+extern cpuop_func_ce op_51a8_13_nf;
+extern cpuop_func_ce op_51a8_13_ff;
+extern cpuop_func_ce op_51b0_13_nf;
+extern cpuop_func_ce op_51b0_13_ff;
+extern cpuop_func_ce op_51b8_13_nf;
+extern cpuop_func_ce op_51b8_13_ff;
+extern cpuop_func_ce op_51b9_13_nf;
+extern cpuop_func_ce op_51b9_13_ff;
+extern cpuop_func_ce op_51c0_13_nf;
+extern cpuop_func_ce op_51c0_13_ff;
+extern cpuop_func_ce op_51c8_13_nf;
+extern cpuop_func_ce op_51c8_13_ff;
+extern cpuop_func_ce op_51d0_13_nf;
+extern cpuop_func_ce op_51d0_13_ff;
+extern cpuop_func_ce op_51d8_13_nf;
+extern cpuop_func_ce op_51d8_13_ff;
+extern cpuop_func_ce op_51e0_13_nf;
+extern cpuop_func_ce op_51e0_13_ff;
+extern cpuop_func_ce op_51e8_13_nf;
+extern cpuop_func_ce op_51e8_13_ff;
+extern cpuop_func_ce op_51f0_13_nf;
+extern cpuop_func_ce op_51f0_13_ff;
+extern cpuop_func_ce op_51f8_13_nf;
+extern cpuop_func_ce op_51f8_13_ff;
+extern cpuop_func_ce op_51f9_13_nf;
+extern cpuop_func_ce op_51f9_13_ff;
+extern cpuop_func_ce op_52c0_13_nf;
+extern cpuop_func_ce op_52c0_13_ff;
+extern cpuop_func_ce op_52c8_13_nf;
+extern cpuop_func_ce op_52c8_13_ff;
+extern cpuop_func_ce op_52d0_13_nf;
+extern cpuop_func_ce op_52d0_13_ff;
+extern cpuop_func_ce op_52d8_13_nf;
+extern cpuop_func_ce op_52d8_13_ff;
+extern cpuop_func_ce op_52e0_13_nf;
+extern cpuop_func_ce op_52e0_13_ff;
+extern cpuop_func_ce op_52e8_13_nf;
+extern cpuop_func_ce op_52e8_13_ff;
+extern cpuop_func_ce op_52f0_13_nf;
+extern cpuop_func_ce op_52f0_13_ff;
+extern cpuop_func_ce op_52f8_13_nf;
+extern cpuop_func_ce op_52f8_13_ff;
+extern cpuop_func_ce op_52f9_13_nf;
+extern cpuop_func_ce op_52f9_13_ff;
+extern cpuop_func_ce op_53c0_13_nf;
+extern cpuop_func_ce op_53c0_13_ff;
+extern cpuop_func_ce op_53c8_13_nf;
+extern cpuop_func_ce op_53c8_13_ff;
+extern cpuop_func_ce op_53d0_13_nf;
+extern cpuop_func_ce op_53d0_13_ff;
+extern cpuop_func_ce op_53d8_13_nf;
+extern cpuop_func_ce op_53d8_13_ff;
+extern cpuop_func_ce op_53e0_13_nf;
+extern cpuop_func_ce op_53e0_13_ff;
+extern cpuop_func_ce op_53e8_13_nf;
+extern cpuop_func_ce op_53e8_13_ff;
+extern cpuop_func_ce op_53f0_13_nf;
+extern cpuop_func_ce op_53f0_13_ff;
+extern cpuop_func_ce op_53f8_13_nf;
+extern cpuop_func_ce op_53f8_13_ff;
+extern cpuop_func_ce op_53f9_13_nf;
+extern cpuop_func_ce op_53f9_13_ff;
+extern cpuop_func_ce op_54c0_13_nf;
+extern cpuop_func_ce op_54c0_13_ff;
+extern cpuop_func_ce op_54c8_13_nf;
+extern cpuop_func_ce op_54c8_13_ff;
+extern cpuop_func_ce op_54d0_13_nf;
+extern cpuop_func_ce op_54d0_13_ff;
+extern cpuop_func_ce op_54d8_13_nf;
+extern cpuop_func_ce op_54d8_13_ff;
+extern cpuop_func_ce op_54e0_13_nf;
+extern cpuop_func_ce op_54e0_13_ff;
+extern cpuop_func_ce op_54e8_13_nf;
+extern cpuop_func_ce op_54e8_13_ff;
+extern cpuop_func_ce op_54f0_13_nf;
+extern cpuop_func_ce op_54f0_13_ff;
+extern cpuop_func_ce op_54f8_13_nf;
+extern cpuop_func_ce op_54f8_13_ff;
+extern cpuop_func_ce op_54f9_13_nf;
+extern cpuop_func_ce op_54f9_13_ff;
+extern cpuop_func_ce op_55c0_13_nf;
+extern cpuop_func_ce op_55c0_13_ff;
+extern cpuop_func_ce op_55c8_13_nf;
+extern cpuop_func_ce op_55c8_13_ff;
+extern cpuop_func_ce op_55d0_13_nf;
+extern cpuop_func_ce op_55d0_13_ff;
+extern cpuop_func_ce op_55d8_13_nf;
+extern cpuop_func_ce op_55d8_13_ff;
+extern cpuop_func_ce op_55e0_13_nf;
+extern cpuop_func_ce op_55e0_13_ff;
+extern cpuop_func_ce op_55e8_13_nf;
+extern cpuop_func_ce op_55e8_13_ff;
+extern cpuop_func_ce op_55f0_13_nf;
+extern cpuop_func_ce op_55f0_13_ff;
+extern cpuop_func_ce op_55f8_13_nf;
+extern cpuop_func_ce op_55f8_13_ff;
+extern cpuop_func_ce op_55f9_13_nf;
+extern cpuop_func_ce op_55f9_13_ff;
+extern cpuop_func_ce op_56c0_13_nf;
+extern cpuop_func_ce op_56c0_13_ff;
+extern cpuop_func_ce op_56c8_13_nf;
+extern cpuop_func_ce op_56c8_13_ff;
+extern cpuop_func_ce op_56d0_13_nf;
+extern cpuop_func_ce op_56d0_13_ff;
+extern cpuop_func_ce op_56d8_13_nf;
+extern cpuop_func_ce op_56d8_13_ff;
+extern cpuop_func_ce op_56e0_13_nf;
+extern cpuop_func_ce op_56e0_13_ff;
+extern cpuop_func_ce op_56e8_13_nf;
+extern cpuop_func_ce op_56e8_13_ff;
+extern cpuop_func_ce op_56f0_13_nf;
+extern cpuop_func_ce op_56f0_13_ff;
+extern cpuop_func_ce op_56f8_13_nf;
+extern cpuop_func_ce op_56f8_13_ff;
+extern cpuop_func_ce op_56f9_13_nf;
+extern cpuop_func_ce op_56f9_13_ff;
+extern cpuop_func_ce op_57c0_13_nf;
+extern cpuop_func_ce op_57c0_13_ff;
+extern cpuop_func_ce op_57c8_13_nf;
+extern cpuop_func_ce op_57c8_13_ff;
+extern cpuop_func_ce op_57d0_13_nf;
+extern cpuop_func_ce op_57d0_13_ff;
+extern cpuop_func_ce op_57d8_13_nf;
+extern cpuop_func_ce op_57d8_13_ff;
+extern cpuop_func_ce op_57e0_13_nf;
+extern cpuop_func_ce op_57e0_13_ff;
+extern cpuop_func_ce op_57e8_13_nf;
+extern cpuop_func_ce op_57e8_13_ff;
+extern cpuop_func_ce op_57f0_13_nf;
+extern cpuop_func_ce op_57f0_13_ff;
+extern cpuop_func_ce op_57f8_13_nf;
+extern cpuop_func_ce op_57f8_13_ff;
+extern cpuop_func_ce op_57f9_13_nf;
+extern cpuop_func_ce op_57f9_13_ff;
+extern cpuop_func_ce op_58c0_13_nf;
+extern cpuop_func_ce op_58c0_13_ff;
+extern cpuop_func_ce op_58c8_13_nf;
+extern cpuop_func_ce op_58c8_13_ff;
+extern cpuop_func_ce op_58d0_13_nf;
+extern cpuop_func_ce op_58d0_13_ff;
+extern cpuop_func_ce op_58d8_13_nf;
+extern cpuop_func_ce op_58d8_13_ff;
+extern cpuop_func_ce op_58e0_13_nf;
+extern cpuop_func_ce op_58e0_13_ff;
+extern cpuop_func_ce op_58e8_13_nf;
+extern cpuop_func_ce op_58e8_13_ff;
+extern cpuop_func_ce op_58f0_13_nf;
+extern cpuop_func_ce op_58f0_13_ff;
+extern cpuop_func_ce op_58f8_13_nf;
+extern cpuop_func_ce op_58f8_13_ff;
+extern cpuop_func_ce op_58f9_13_nf;
+extern cpuop_func_ce op_58f9_13_ff;
+extern cpuop_func_ce op_59c0_13_nf;
+extern cpuop_func_ce op_59c0_13_ff;
+extern cpuop_func_ce op_59c8_13_nf;
+extern cpuop_func_ce op_59c8_13_ff;
+extern cpuop_func_ce op_59d0_13_nf;
+extern cpuop_func_ce op_59d0_13_ff;
+extern cpuop_func_ce op_59d8_13_nf;
+extern cpuop_func_ce op_59d8_13_ff;
+extern cpuop_func_ce op_59e0_13_nf;
+extern cpuop_func_ce op_59e0_13_ff;
+extern cpuop_func_ce op_59e8_13_nf;
+extern cpuop_func_ce op_59e8_13_ff;
+extern cpuop_func_ce op_59f0_13_nf;
+extern cpuop_func_ce op_59f0_13_ff;
+extern cpuop_func_ce op_59f8_13_nf;
+extern cpuop_func_ce op_59f8_13_ff;
+extern cpuop_func_ce op_59f9_13_nf;
+extern cpuop_func_ce op_59f9_13_ff;
+extern cpuop_func_ce op_5ac0_13_nf;
+extern cpuop_func_ce op_5ac0_13_ff;
+extern cpuop_func_ce op_5ac8_13_nf;
+extern cpuop_func_ce op_5ac8_13_ff;
+extern cpuop_func_ce op_5ad0_13_nf;
+extern cpuop_func_ce op_5ad0_13_ff;
+extern cpuop_func_ce op_5ad8_13_nf;
+extern cpuop_func_ce op_5ad8_13_ff;
+extern cpuop_func_ce op_5ae0_13_nf;
+extern cpuop_func_ce op_5ae0_13_ff;
+extern cpuop_func_ce op_5ae8_13_nf;
+extern cpuop_func_ce op_5ae8_13_ff;
+extern cpuop_func_ce op_5af0_13_nf;
+extern cpuop_func_ce op_5af0_13_ff;
+extern cpuop_func_ce op_5af8_13_nf;
+extern cpuop_func_ce op_5af8_13_ff;
+extern cpuop_func_ce op_5af9_13_nf;
+extern cpuop_func_ce op_5af9_13_ff;
+extern cpuop_func_ce op_5bc0_13_nf;
+extern cpuop_func_ce op_5bc0_13_ff;
+extern cpuop_func_ce op_5bc8_13_nf;
+extern cpuop_func_ce op_5bc8_13_ff;
+extern cpuop_func_ce op_5bd0_13_nf;
+extern cpuop_func_ce op_5bd0_13_ff;
+extern cpuop_func_ce op_5bd8_13_nf;
+extern cpuop_func_ce op_5bd8_13_ff;
+extern cpuop_func_ce op_5be0_13_nf;
+extern cpuop_func_ce op_5be0_13_ff;
+extern cpuop_func_ce op_5be8_13_nf;
+extern cpuop_func_ce op_5be8_13_ff;
+extern cpuop_func_ce op_5bf0_13_nf;
+extern cpuop_func_ce op_5bf0_13_ff;
+extern cpuop_func_ce op_5bf8_13_nf;
+extern cpuop_func_ce op_5bf8_13_ff;
+extern cpuop_func_ce op_5bf9_13_nf;
+extern cpuop_func_ce op_5bf9_13_ff;
+extern cpuop_func_ce op_5cc0_13_nf;
+extern cpuop_func_ce op_5cc0_13_ff;
+extern cpuop_func_ce op_5cc8_13_nf;
+extern cpuop_func_ce op_5cc8_13_ff;
+extern cpuop_func_ce op_5cd0_13_nf;
+extern cpuop_func_ce op_5cd0_13_ff;
+extern cpuop_func_ce op_5cd8_13_nf;
+extern cpuop_func_ce op_5cd8_13_ff;
+extern cpuop_func_ce op_5ce0_13_nf;
+extern cpuop_func_ce op_5ce0_13_ff;
+extern cpuop_func_ce op_5ce8_13_nf;
+extern cpuop_func_ce op_5ce8_13_ff;
+extern cpuop_func_ce op_5cf0_13_nf;
+extern cpuop_func_ce op_5cf0_13_ff;
+extern cpuop_func_ce op_5cf8_13_nf;
+extern cpuop_func_ce op_5cf8_13_ff;
+extern cpuop_func_ce op_5cf9_13_nf;
+extern cpuop_func_ce op_5cf9_13_ff;
+extern cpuop_func_ce op_5dc0_13_nf;
+extern cpuop_func_ce op_5dc0_13_ff;
+extern cpuop_func_ce op_5dc8_13_nf;
+extern cpuop_func_ce op_5dc8_13_ff;
+extern cpuop_func_ce op_5dd0_13_nf;
+extern cpuop_func_ce op_5dd0_13_ff;
+extern cpuop_func_ce op_5dd8_13_nf;
+extern cpuop_func_ce op_5dd8_13_ff;
+extern cpuop_func_ce op_5de0_13_nf;
+extern cpuop_func_ce op_5de0_13_ff;
+extern cpuop_func_ce op_5de8_13_nf;
+extern cpuop_func_ce op_5de8_13_ff;
+extern cpuop_func_ce op_5df0_13_nf;
+extern cpuop_func_ce op_5df0_13_ff;
+extern cpuop_func_ce op_5df8_13_nf;
+extern cpuop_func_ce op_5df8_13_ff;
+extern cpuop_func_ce op_5df9_13_nf;
+extern cpuop_func_ce op_5df9_13_ff;
+extern cpuop_func_ce op_5ec0_13_nf;
+extern cpuop_func_ce op_5ec0_13_ff;
+extern cpuop_func_ce op_5ec8_13_nf;
+extern cpuop_func_ce op_5ec8_13_ff;
+extern cpuop_func_ce op_5ed0_13_nf;
+extern cpuop_func_ce op_5ed0_13_ff;
+extern cpuop_func_ce op_5ed8_13_nf;
+extern cpuop_func_ce op_5ed8_13_ff;
+extern cpuop_func_ce op_5ee0_13_nf;
+extern cpuop_func_ce op_5ee0_13_ff;
+extern cpuop_func_ce op_5ee8_13_nf;
+extern cpuop_func_ce op_5ee8_13_ff;
+extern cpuop_func_ce op_5ef0_13_nf;
+extern cpuop_func_ce op_5ef0_13_ff;
+extern cpuop_func_ce op_5ef8_13_nf;
+extern cpuop_func_ce op_5ef8_13_ff;
+extern cpuop_func_ce op_5ef9_13_nf;
+extern cpuop_func_ce op_5ef9_13_ff;
+extern cpuop_func_ce op_5fc0_13_nf;
+extern cpuop_func_ce op_5fc0_13_ff;
+extern cpuop_func_ce op_5fc8_13_nf;
+extern cpuop_func_ce op_5fc8_13_ff;
+extern cpuop_func_ce op_5fd0_13_nf;
+extern cpuop_func_ce op_5fd0_13_ff;
+extern cpuop_func_ce op_5fd8_13_nf;
+extern cpuop_func_ce op_5fd8_13_ff;
+extern cpuop_func_ce op_5fe0_13_nf;
+extern cpuop_func_ce op_5fe0_13_ff;
+extern cpuop_func_ce op_5fe8_13_nf;
+extern cpuop_func_ce op_5fe8_13_ff;
+extern cpuop_func_ce op_5ff0_13_nf;
+extern cpuop_func_ce op_5ff0_13_ff;
+extern cpuop_func_ce op_5ff8_13_nf;
+extern cpuop_func_ce op_5ff8_13_ff;
+extern cpuop_func_ce op_5ff9_13_nf;
+extern cpuop_func_ce op_5ff9_13_ff;
+extern cpuop_func_ce op_6000_13_nf;
+extern cpuop_func_ce op_6000_13_ff;
+extern cpuop_func_ce op_6001_13_nf;
+extern cpuop_func_ce op_6001_13_ff;
+extern cpuop_func_ce op_60ff_13_nf;
+extern cpuop_func_ce op_60ff_13_ff;
+extern cpuop_func_ce op_6100_13_nf;
+extern cpuop_func_ce op_6100_13_ff;
+extern cpuop_func_ce op_6101_13_nf;
+extern cpuop_func_ce op_6101_13_ff;
+extern cpuop_func_ce op_61ff_13_nf;
+extern cpuop_func_ce op_61ff_13_ff;
+extern cpuop_func_ce op_6200_13_nf;
+extern cpuop_func_ce op_6200_13_ff;
+extern cpuop_func_ce op_6201_13_nf;
+extern cpuop_func_ce op_6201_13_ff;
+extern cpuop_func_ce op_62ff_13_nf;
+extern cpuop_func_ce op_62ff_13_ff;
+extern cpuop_func_ce op_6300_13_nf;
+extern cpuop_func_ce op_6300_13_ff;
+extern cpuop_func_ce op_6301_13_nf;
+extern cpuop_func_ce op_6301_13_ff;
+extern cpuop_func_ce op_63ff_13_nf;
+extern cpuop_func_ce op_63ff_13_ff;
+extern cpuop_func_ce op_6400_13_nf;
+extern cpuop_func_ce op_6400_13_ff;
+extern cpuop_func_ce op_6401_13_nf;
+extern cpuop_func_ce op_6401_13_ff;
+extern cpuop_func_ce op_64ff_13_nf;
+extern cpuop_func_ce op_64ff_13_ff;
+extern cpuop_func_ce op_6500_13_nf;
+extern cpuop_func_ce op_6500_13_ff;
+extern cpuop_func_ce op_6501_13_nf;
+extern cpuop_func_ce op_6501_13_ff;
+extern cpuop_func_ce op_65ff_13_nf;
+extern cpuop_func_ce op_65ff_13_ff;
+extern cpuop_func_ce op_6600_13_nf;
+extern cpuop_func_ce op_6600_13_ff;
+extern cpuop_func_ce op_6601_13_nf;
+extern cpuop_func_ce op_6601_13_ff;
+extern cpuop_func_ce op_66ff_13_nf;
+extern cpuop_func_ce op_66ff_13_ff;
+extern cpuop_func_ce op_6700_13_nf;
+extern cpuop_func_ce op_6700_13_ff;
+extern cpuop_func_ce op_6701_13_nf;
+extern cpuop_func_ce op_6701_13_ff;
+extern cpuop_func_ce op_67ff_13_nf;
+extern cpuop_func_ce op_67ff_13_ff;
+extern cpuop_func_ce op_6800_13_nf;
+extern cpuop_func_ce op_6800_13_ff;
+extern cpuop_func_ce op_6801_13_nf;
+extern cpuop_func_ce op_6801_13_ff;
+extern cpuop_func_ce op_68ff_13_nf;
+extern cpuop_func_ce op_68ff_13_ff;
+extern cpuop_func_ce op_6900_13_nf;
+extern cpuop_func_ce op_6900_13_ff;
+extern cpuop_func_ce op_6901_13_nf;
+extern cpuop_func_ce op_6901_13_ff;
+extern cpuop_func_ce op_69ff_13_nf;
+extern cpuop_func_ce op_69ff_13_ff;
+extern cpuop_func_ce op_6a00_13_nf;
+extern cpuop_func_ce op_6a00_13_ff;
+extern cpuop_func_ce op_6a01_13_nf;
+extern cpuop_func_ce op_6a01_13_ff;
+extern cpuop_func_ce op_6aff_13_nf;
+extern cpuop_func_ce op_6aff_13_ff;
+extern cpuop_func_ce op_6b00_13_nf;
+extern cpuop_func_ce op_6b00_13_ff;
+extern cpuop_func_ce op_6b01_13_nf;
+extern cpuop_func_ce op_6b01_13_ff;
+extern cpuop_func_ce op_6bff_13_nf;
+extern cpuop_func_ce op_6bff_13_ff;
+extern cpuop_func_ce op_6c00_13_nf;
+extern cpuop_func_ce op_6c00_13_ff;
+extern cpuop_func_ce op_6c01_13_nf;
+extern cpuop_func_ce op_6c01_13_ff;
+extern cpuop_func_ce op_6cff_13_nf;
+extern cpuop_func_ce op_6cff_13_ff;
+extern cpuop_func_ce op_6d00_13_nf;
+extern cpuop_func_ce op_6d00_13_ff;
+extern cpuop_func_ce op_6d01_13_nf;
+extern cpuop_func_ce op_6d01_13_ff;
+extern cpuop_func_ce op_6dff_13_nf;
+extern cpuop_func_ce op_6dff_13_ff;
+extern cpuop_func_ce op_6e00_13_nf;
+extern cpuop_func_ce op_6e00_13_ff;
+extern cpuop_func_ce op_6e01_13_nf;
+extern cpuop_func_ce op_6e01_13_ff;
+extern cpuop_func_ce op_6eff_13_nf;
+extern cpuop_func_ce op_6eff_13_ff;
+extern cpuop_func_ce op_6f00_13_nf;
+extern cpuop_func_ce op_6f00_13_ff;
+extern cpuop_func_ce op_6f01_13_nf;
+extern cpuop_func_ce op_6f01_13_ff;
+extern cpuop_func_ce op_6fff_13_nf;
+extern cpuop_func_ce op_6fff_13_ff;
+extern cpuop_func_ce op_7000_13_nf;
+extern cpuop_func_ce op_7000_13_ff;
+extern cpuop_func_ce op_8000_13_nf;
+extern cpuop_func_ce op_8000_13_ff;
+extern cpuop_func_ce op_8010_13_nf;
+extern cpuop_func_ce op_8010_13_ff;
+extern cpuop_func_ce op_8018_13_nf;
+extern cpuop_func_ce op_8018_13_ff;
+extern cpuop_func_ce op_8020_13_nf;
+extern cpuop_func_ce op_8020_13_ff;
+extern cpuop_func_ce op_8028_13_nf;
+extern cpuop_func_ce op_8028_13_ff;
+extern cpuop_func_ce op_8030_13_nf;
+extern cpuop_func_ce op_8030_13_ff;
+extern cpuop_func_ce op_8038_13_nf;
+extern cpuop_func_ce op_8038_13_ff;
+extern cpuop_func_ce op_8039_13_nf;
+extern cpuop_func_ce op_8039_13_ff;
+extern cpuop_func_ce op_803a_13_nf;
+extern cpuop_func_ce op_803a_13_ff;
+extern cpuop_func_ce op_803b_13_nf;
+extern cpuop_func_ce op_803b_13_ff;
+extern cpuop_func_ce op_803c_13_nf;
+extern cpuop_func_ce op_803c_13_ff;
+extern cpuop_func_ce op_8040_13_nf;
+extern cpuop_func_ce op_8040_13_ff;
+extern cpuop_func_ce op_8050_13_nf;
+extern cpuop_func_ce op_8050_13_ff;
+extern cpuop_func_ce op_8058_13_nf;
+extern cpuop_func_ce op_8058_13_ff;
+extern cpuop_func_ce op_8060_13_nf;
+extern cpuop_func_ce op_8060_13_ff;
+extern cpuop_func_ce op_8068_13_nf;
+extern cpuop_func_ce op_8068_13_ff;
+extern cpuop_func_ce op_8070_13_nf;
+extern cpuop_func_ce op_8070_13_ff;
+extern cpuop_func_ce op_8078_13_nf;
+extern cpuop_func_ce op_8078_13_ff;
+extern cpuop_func_ce op_8079_13_nf;
+extern cpuop_func_ce op_8079_13_ff;
+extern cpuop_func_ce op_807a_13_nf;
+extern cpuop_func_ce op_807a_13_ff;
+extern cpuop_func_ce op_807b_13_nf;
+extern cpuop_func_ce op_807b_13_ff;
+extern cpuop_func_ce op_807c_13_nf;
+extern cpuop_func_ce op_807c_13_ff;
+extern cpuop_func_ce op_8080_13_nf;
+extern cpuop_func_ce op_8080_13_ff;
+extern cpuop_func_ce op_8090_13_nf;
+extern cpuop_func_ce op_8090_13_ff;
+extern cpuop_func_ce op_8098_13_nf;
+extern cpuop_func_ce op_8098_13_ff;
+extern cpuop_func_ce op_80a0_13_nf;
+extern cpuop_func_ce op_80a0_13_ff;
+extern cpuop_func_ce op_80a8_13_nf;
+extern cpuop_func_ce op_80a8_13_ff;
+extern cpuop_func_ce op_80b0_13_nf;
+extern cpuop_func_ce op_80b0_13_ff;
+extern cpuop_func_ce op_80b8_13_nf;
+extern cpuop_func_ce op_80b8_13_ff;
+extern cpuop_func_ce op_80b9_13_nf;
+extern cpuop_func_ce op_80b9_13_ff;
+extern cpuop_func_ce op_80ba_13_nf;
+extern cpuop_func_ce op_80ba_13_ff;
+extern cpuop_func_ce op_80bb_13_nf;
+extern cpuop_func_ce op_80bb_13_ff;
+extern cpuop_func_ce op_80bc_13_nf;
+extern cpuop_func_ce op_80bc_13_ff;
+extern cpuop_func_ce op_80c0_13_nf;
+extern cpuop_func_ce op_80c0_13_ff;
+extern cpuop_func_ce op_80d0_13_nf;
+extern cpuop_func_ce op_80d0_13_ff;
+extern cpuop_func_ce op_80d8_13_nf;
+extern cpuop_func_ce op_80d8_13_ff;
+extern cpuop_func_ce op_80e0_13_nf;
+extern cpuop_func_ce op_80e0_13_ff;
+extern cpuop_func_ce op_80e8_13_nf;
+extern cpuop_func_ce op_80e8_13_ff;
+extern cpuop_func_ce op_80f0_13_nf;
+extern cpuop_func_ce op_80f0_13_ff;
+extern cpuop_func_ce op_80f8_13_nf;
+extern cpuop_func_ce op_80f8_13_ff;
+extern cpuop_func_ce op_80f9_13_nf;
+extern cpuop_func_ce op_80f9_13_ff;
+extern cpuop_func_ce op_80fa_13_nf;
+extern cpuop_func_ce op_80fa_13_ff;
+extern cpuop_func_ce op_80fb_13_nf;
+extern cpuop_func_ce op_80fb_13_ff;
+extern cpuop_func_ce op_80fc_13_nf;
+extern cpuop_func_ce op_80fc_13_ff;
+extern cpuop_func_ce op_8100_13_nf;
+extern cpuop_func_ce op_8100_13_ff;
+extern cpuop_func_ce op_8108_13_nf;
+extern cpuop_func_ce op_8108_13_ff;
+extern cpuop_func_ce op_8110_13_nf;
+extern cpuop_func_ce op_8110_13_ff;
+extern cpuop_func_ce op_8118_13_nf;
+extern cpuop_func_ce op_8118_13_ff;
+extern cpuop_func_ce op_8120_13_nf;
+extern cpuop_func_ce op_8120_13_ff;
+extern cpuop_func_ce op_8128_13_nf;
+extern cpuop_func_ce op_8128_13_ff;
+extern cpuop_func_ce op_8130_13_nf;
+extern cpuop_func_ce op_8130_13_ff;
+extern cpuop_func_ce op_8138_13_nf;
+extern cpuop_func_ce op_8138_13_ff;
+extern cpuop_func_ce op_8139_13_nf;
+extern cpuop_func_ce op_8139_13_ff;
+extern cpuop_func_ce op_8150_13_nf;
+extern cpuop_func_ce op_8150_13_ff;
+extern cpuop_func_ce op_8158_13_nf;
+extern cpuop_func_ce op_8158_13_ff;
+extern cpuop_func_ce op_8160_13_nf;
+extern cpuop_func_ce op_8160_13_ff;
+extern cpuop_func_ce op_8168_13_nf;
+extern cpuop_func_ce op_8168_13_ff;
+extern cpuop_func_ce op_8170_13_nf;
+extern cpuop_func_ce op_8170_13_ff;
+extern cpuop_func_ce op_8178_13_nf;
+extern cpuop_func_ce op_8178_13_ff;
+extern cpuop_func_ce op_8179_13_nf;
+extern cpuop_func_ce op_8179_13_ff;
+extern cpuop_func_ce op_8190_13_nf;
+extern cpuop_func_ce op_8190_13_ff;
+extern cpuop_func_ce op_8198_13_nf;
+extern cpuop_func_ce op_8198_13_ff;
+extern cpuop_func_ce op_81a0_13_nf;
+extern cpuop_func_ce op_81a0_13_ff;
+extern cpuop_func_ce op_81a8_13_nf;
+extern cpuop_func_ce op_81a8_13_ff;
+extern cpuop_func_ce op_81b0_13_nf;
+extern cpuop_func_ce op_81b0_13_ff;
+extern cpuop_func_ce op_81b8_13_nf;
+extern cpuop_func_ce op_81b8_13_ff;
+extern cpuop_func_ce op_81b9_13_nf;
+extern cpuop_func_ce op_81b9_13_ff;
+extern cpuop_func_ce op_81c0_13_nf;
+extern cpuop_func_ce op_81c0_13_ff;
+extern cpuop_func_ce op_81d0_13_nf;
+extern cpuop_func_ce op_81d0_13_ff;
+extern cpuop_func_ce op_81d8_13_nf;
+extern cpuop_func_ce op_81d8_13_ff;
+extern cpuop_func_ce op_81e0_13_nf;
+extern cpuop_func_ce op_81e0_13_ff;
+extern cpuop_func_ce op_81e8_13_nf;
+extern cpuop_func_ce op_81e8_13_ff;
+extern cpuop_func_ce op_81f0_13_nf;
+extern cpuop_func_ce op_81f0_13_ff;
+extern cpuop_func_ce op_81f8_13_nf;
+extern cpuop_func_ce op_81f8_13_ff;
+extern cpuop_func_ce op_81f9_13_nf;
+extern cpuop_func_ce op_81f9_13_ff;
+extern cpuop_func_ce op_81fa_13_nf;
+extern cpuop_func_ce op_81fa_13_ff;
+extern cpuop_func_ce op_81fb_13_nf;
+extern cpuop_func_ce op_81fb_13_ff;
+extern cpuop_func_ce op_81fc_13_nf;
+extern cpuop_func_ce op_81fc_13_ff;
+extern cpuop_func_ce op_9000_13_nf;
+extern cpuop_func_ce op_9000_13_ff;
+extern cpuop_func_ce op_9010_13_nf;
+extern cpuop_func_ce op_9010_13_ff;
+extern cpuop_func_ce op_9018_13_nf;
+extern cpuop_func_ce op_9018_13_ff;
+extern cpuop_func_ce op_9020_13_nf;
+extern cpuop_func_ce op_9020_13_ff;
+extern cpuop_func_ce op_9028_13_nf;
+extern cpuop_func_ce op_9028_13_ff;
+extern cpuop_func_ce op_9030_13_nf;
+extern cpuop_func_ce op_9030_13_ff;
+extern cpuop_func_ce op_9038_13_nf;
+extern cpuop_func_ce op_9038_13_ff;
+extern cpuop_func_ce op_9039_13_nf;
+extern cpuop_func_ce op_9039_13_ff;
+extern cpuop_func_ce op_903a_13_nf;
+extern cpuop_func_ce op_903a_13_ff;
+extern cpuop_func_ce op_903b_13_nf;
+extern cpuop_func_ce op_903b_13_ff;
+extern cpuop_func_ce op_903c_13_nf;
+extern cpuop_func_ce op_903c_13_ff;
+extern cpuop_func_ce op_9040_13_nf;
+extern cpuop_func_ce op_9040_13_ff;
+extern cpuop_func_ce op_9048_13_nf;
+extern cpuop_func_ce op_9048_13_ff;
+extern cpuop_func_ce op_9050_13_nf;
+extern cpuop_func_ce op_9050_13_ff;
+extern cpuop_func_ce op_9058_13_nf;
+extern cpuop_func_ce op_9058_13_ff;
+extern cpuop_func_ce op_9060_13_nf;
+extern cpuop_func_ce op_9060_13_ff;
+extern cpuop_func_ce op_9068_13_nf;
+extern cpuop_func_ce op_9068_13_ff;
+extern cpuop_func_ce op_9070_13_nf;
+extern cpuop_func_ce op_9070_13_ff;
+extern cpuop_func_ce op_9078_13_nf;
+extern cpuop_func_ce op_9078_13_ff;
+extern cpuop_func_ce op_9079_13_nf;
+extern cpuop_func_ce op_9079_13_ff;
+extern cpuop_func_ce op_907a_13_nf;
+extern cpuop_func_ce op_907a_13_ff;
+extern cpuop_func_ce op_907b_13_nf;
+extern cpuop_func_ce op_907b_13_ff;
+extern cpuop_func_ce op_907c_13_nf;
+extern cpuop_func_ce op_907c_13_ff;
+extern cpuop_func_ce op_9080_13_nf;
+extern cpuop_func_ce op_9080_13_ff;
+extern cpuop_func_ce op_9088_13_nf;
+extern cpuop_func_ce op_9088_13_ff;
+extern cpuop_func_ce op_9090_13_nf;
+extern cpuop_func_ce op_9090_13_ff;
+extern cpuop_func_ce op_9098_13_nf;
+extern cpuop_func_ce op_9098_13_ff;
+extern cpuop_func_ce op_90a0_13_nf;
+extern cpuop_func_ce op_90a0_13_ff;
+extern cpuop_func_ce op_90a8_13_nf;
+extern cpuop_func_ce op_90a8_13_ff;
+extern cpuop_func_ce op_90b0_13_nf;
+extern cpuop_func_ce op_90b0_13_ff;
+extern cpuop_func_ce op_90b8_13_nf;
+extern cpuop_func_ce op_90b8_13_ff;
+extern cpuop_func_ce op_90b9_13_nf;
+extern cpuop_func_ce op_90b9_13_ff;
+extern cpuop_func_ce op_90ba_13_nf;
+extern cpuop_func_ce op_90ba_13_ff;
+extern cpuop_func_ce op_90bb_13_nf;
+extern cpuop_func_ce op_90bb_13_ff;
+extern cpuop_func_ce op_90bc_13_nf;
+extern cpuop_func_ce op_90bc_13_ff;
+extern cpuop_func_ce op_90c0_13_nf;
+extern cpuop_func_ce op_90c0_13_ff;
+extern cpuop_func_ce op_90c8_13_nf;
+extern cpuop_func_ce op_90c8_13_ff;
+extern cpuop_func_ce op_90d0_13_nf;
+extern cpuop_func_ce op_90d0_13_ff;
+extern cpuop_func_ce op_90d8_13_nf;
+extern cpuop_func_ce op_90d8_13_ff;
+extern cpuop_func_ce op_90e0_13_nf;
+extern cpuop_func_ce op_90e0_13_ff;
+extern cpuop_func_ce op_90e8_13_nf;
+extern cpuop_func_ce op_90e8_13_ff;
+extern cpuop_func_ce op_90f0_13_nf;
+extern cpuop_func_ce op_90f0_13_ff;
+extern cpuop_func_ce op_90f8_13_nf;
+extern cpuop_func_ce op_90f8_13_ff;
+extern cpuop_func_ce op_90f9_13_nf;
+extern cpuop_func_ce op_90f9_13_ff;
+extern cpuop_func_ce op_90fa_13_nf;
+extern cpuop_func_ce op_90fa_13_ff;
+extern cpuop_func_ce op_90fb_13_nf;
+extern cpuop_func_ce op_90fb_13_ff;
+extern cpuop_func_ce op_90fc_13_nf;
+extern cpuop_func_ce op_90fc_13_ff;
+extern cpuop_func_ce op_9100_13_nf;
+extern cpuop_func_ce op_9100_13_ff;
+extern cpuop_func_ce op_9108_13_nf;
+extern cpuop_func_ce op_9108_13_ff;
+extern cpuop_func_ce op_9110_13_nf;
+extern cpuop_func_ce op_9110_13_ff;
+extern cpuop_func_ce op_9118_13_nf;
+extern cpuop_func_ce op_9118_13_ff;
+extern cpuop_func_ce op_9120_13_nf;
+extern cpuop_func_ce op_9120_13_ff;
+extern cpuop_func_ce op_9128_13_nf;
+extern cpuop_func_ce op_9128_13_ff;
+extern cpuop_func_ce op_9130_13_nf;
+extern cpuop_func_ce op_9130_13_ff;
+extern cpuop_func_ce op_9138_13_nf;
+extern cpuop_func_ce op_9138_13_ff;
+extern cpuop_func_ce op_9139_13_nf;
+extern cpuop_func_ce op_9139_13_ff;
+extern cpuop_func_ce op_9140_13_nf;
+extern cpuop_func_ce op_9140_13_ff;
+extern cpuop_func_ce op_9148_13_nf;
+extern cpuop_func_ce op_9148_13_ff;
+extern cpuop_func_ce op_9150_13_nf;
+extern cpuop_func_ce op_9150_13_ff;
+extern cpuop_func_ce op_9158_13_nf;
+extern cpuop_func_ce op_9158_13_ff;
+extern cpuop_func_ce op_9160_13_nf;
+extern cpuop_func_ce op_9160_13_ff;
+extern cpuop_func_ce op_9168_13_nf;
+extern cpuop_func_ce op_9168_13_ff;
+extern cpuop_func_ce op_9170_13_nf;
+extern cpuop_func_ce op_9170_13_ff;
+extern cpuop_func_ce op_9178_13_nf;
+extern cpuop_func_ce op_9178_13_ff;
+extern cpuop_func_ce op_9179_13_nf;
+extern cpuop_func_ce op_9179_13_ff;
+extern cpuop_func_ce op_9180_13_nf;
+extern cpuop_func_ce op_9180_13_ff;
+extern cpuop_func_ce op_9188_13_nf;
+extern cpuop_func_ce op_9188_13_ff;
+extern cpuop_func_ce op_9190_13_nf;
+extern cpuop_func_ce op_9190_13_ff;
+extern cpuop_func_ce op_9198_13_nf;
+extern cpuop_func_ce op_9198_13_ff;
+extern cpuop_func_ce op_91a0_13_nf;
+extern cpuop_func_ce op_91a0_13_ff;
+extern cpuop_func_ce op_91a8_13_nf;
+extern cpuop_func_ce op_91a8_13_ff;
+extern cpuop_func_ce op_91b0_13_nf;
+extern cpuop_func_ce op_91b0_13_ff;
+extern cpuop_func_ce op_91b8_13_nf;
+extern cpuop_func_ce op_91b8_13_ff;
+extern cpuop_func_ce op_91b9_13_nf;
+extern cpuop_func_ce op_91b9_13_ff;
+extern cpuop_func_ce op_91c0_13_nf;
+extern cpuop_func_ce op_91c0_13_ff;
+extern cpuop_func_ce op_91c8_13_nf;
+extern cpuop_func_ce op_91c8_13_ff;
+extern cpuop_func_ce op_91d0_13_nf;
+extern cpuop_func_ce op_91d0_13_ff;
+extern cpuop_func_ce op_91d8_13_nf;
+extern cpuop_func_ce op_91d8_13_ff;
+extern cpuop_func_ce op_91e0_13_nf;
+extern cpuop_func_ce op_91e0_13_ff;
+extern cpuop_func_ce op_91e8_13_nf;
+extern cpuop_func_ce op_91e8_13_ff;
+extern cpuop_func_ce op_91f0_13_nf;
+extern cpuop_func_ce op_91f0_13_ff;
+extern cpuop_func_ce op_91f8_13_nf;
+extern cpuop_func_ce op_91f8_13_ff;
+extern cpuop_func_ce op_91f9_13_nf;
+extern cpuop_func_ce op_91f9_13_ff;
+extern cpuop_func_ce op_91fa_13_nf;
+extern cpuop_func_ce op_91fa_13_ff;
+extern cpuop_func_ce op_91fb_13_nf;
+extern cpuop_func_ce op_91fb_13_ff;
+extern cpuop_func_ce op_91fc_13_nf;
+extern cpuop_func_ce op_91fc_13_ff;
+extern cpuop_func_ce op_b000_13_nf;
+extern cpuop_func_ce op_b000_13_ff;
+extern cpuop_func_ce op_b010_13_nf;
+extern cpuop_func_ce op_b010_13_ff;
+extern cpuop_func_ce op_b018_13_nf;
+extern cpuop_func_ce op_b018_13_ff;
+extern cpuop_func_ce op_b020_13_nf;
+extern cpuop_func_ce op_b020_13_ff;
+extern cpuop_func_ce op_b028_13_nf;
+extern cpuop_func_ce op_b028_13_ff;
+extern cpuop_func_ce op_b030_13_nf;
+extern cpuop_func_ce op_b030_13_ff;
+extern cpuop_func_ce op_b038_13_nf;
+extern cpuop_func_ce op_b038_13_ff;
+extern cpuop_func_ce op_b039_13_nf;
+extern cpuop_func_ce op_b039_13_ff;
+extern cpuop_func_ce op_b03a_13_nf;
+extern cpuop_func_ce op_b03a_13_ff;
+extern cpuop_func_ce op_b03b_13_nf;
+extern cpuop_func_ce op_b03b_13_ff;
+extern cpuop_func_ce op_b03c_13_nf;
+extern cpuop_func_ce op_b03c_13_ff;
+extern cpuop_func_ce op_b040_13_nf;
+extern cpuop_func_ce op_b040_13_ff;
+extern cpuop_func_ce op_b048_13_nf;
+extern cpuop_func_ce op_b048_13_ff;
+extern cpuop_func_ce op_b050_13_nf;
+extern cpuop_func_ce op_b050_13_ff;
+extern cpuop_func_ce op_b058_13_nf;
+extern cpuop_func_ce op_b058_13_ff;
+extern cpuop_func_ce op_b060_13_nf;
+extern cpuop_func_ce op_b060_13_ff;
+extern cpuop_func_ce op_b068_13_nf;
+extern cpuop_func_ce op_b068_13_ff;
+extern cpuop_func_ce op_b070_13_nf;
+extern cpuop_func_ce op_b070_13_ff;
+extern cpuop_func_ce op_b078_13_nf;
+extern cpuop_func_ce op_b078_13_ff;
+extern cpuop_func_ce op_b079_13_nf;
+extern cpuop_func_ce op_b079_13_ff;
+extern cpuop_func_ce op_b07a_13_nf;
+extern cpuop_func_ce op_b07a_13_ff;
+extern cpuop_func_ce op_b07b_13_nf;
+extern cpuop_func_ce op_b07b_13_ff;
+extern cpuop_func_ce op_b07c_13_nf;
+extern cpuop_func_ce op_b07c_13_ff;
+extern cpuop_func_ce op_b080_13_nf;
+extern cpuop_func_ce op_b080_13_ff;
+extern cpuop_func_ce op_b088_13_nf;
+extern cpuop_func_ce op_b088_13_ff;
+extern cpuop_func_ce op_b090_13_nf;
+extern cpuop_func_ce op_b090_13_ff;
+extern cpuop_func_ce op_b098_13_nf;
+extern cpuop_func_ce op_b098_13_ff;
+extern cpuop_func_ce op_b0a0_13_nf;
+extern cpuop_func_ce op_b0a0_13_ff;
+extern cpuop_func_ce op_b0a8_13_nf;
+extern cpuop_func_ce op_b0a8_13_ff;
+extern cpuop_func_ce op_b0b0_13_nf;
+extern cpuop_func_ce op_b0b0_13_ff;
+extern cpuop_func_ce op_b0b8_13_nf;
+extern cpuop_func_ce op_b0b8_13_ff;
+extern cpuop_func_ce op_b0b9_13_nf;
+extern cpuop_func_ce op_b0b9_13_ff;
+extern cpuop_func_ce op_b0ba_13_nf;
+extern cpuop_func_ce op_b0ba_13_ff;
+extern cpuop_func_ce op_b0bb_13_nf;
+extern cpuop_func_ce op_b0bb_13_ff;
+extern cpuop_func_ce op_b0bc_13_nf;
+extern cpuop_func_ce op_b0bc_13_ff;
+extern cpuop_func_ce op_b0c0_13_nf;
+extern cpuop_func_ce op_b0c0_13_ff;
+extern cpuop_func_ce op_b0c8_13_nf;
+extern cpuop_func_ce op_b0c8_13_ff;
+extern cpuop_func_ce op_b0d0_13_nf;
+extern cpuop_func_ce op_b0d0_13_ff;
+extern cpuop_func_ce op_b0d8_13_nf;
+extern cpuop_func_ce op_b0d8_13_ff;
+extern cpuop_func_ce op_b0e0_13_nf;
+extern cpuop_func_ce op_b0e0_13_ff;
+extern cpuop_func_ce op_b0e8_13_nf;
+extern cpuop_func_ce op_b0e8_13_ff;
+extern cpuop_func_ce op_b0f0_13_nf;
+extern cpuop_func_ce op_b0f0_13_ff;
+extern cpuop_func_ce op_b0f8_13_nf;
+extern cpuop_func_ce op_b0f8_13_ff;
+extern cpuop_func_ce op_b0f9_13_nf;
+extern cpuop_func_ce op_b0f9_13_ff;
+extern cpuop_func_ce op_b0fa_13_nf;
+extern cpuop_func_ce op_b0fa_13_ff;
+extern cpuop_func_ce op_b0fb_13_nf;
+extern cpuop_func_ce op_b0fb_13_ff;
+extern cpuop_func_ce op_b0fc_13_nf;
+extern cpuop_func_ce op_b0fc_13_ff;
+extern cpuop_func_ce op_b100_13_nf;
+extern cpuop_func_ce op_b100_13_ff;
+extern cpuop_func_ce op_b108_13_nf;
+extern cpuop_func_ce op_b108_13_ff;
+extern cpuop_func_ce op_b110_13_nf;
+extern cpuop_func_ce op_b110_13_ff;
+extern cpuop_func_ce op_b118_13_nf;
+extern cpuop_func_ce op_b118_13_ff;
+extern cpuop_func_ce op_b120_13_nf;
+extern cpuop_func_ce op_b120_13_ff;
+extern cpuop_func_ce op_b128_13_nf;
+extern cpuop_func_ce op_b128_13_ff;
+extern cpuop_func_ce op_b130_13_nf;
+extern cpuop_func_ce op_b130_13_ff;
+extern cpuop_func_ce op_b138_13_nf;
+extern cpuop_func_ce op_b138_13_ff;
+extern cpuop_func_ce op_b139_13_nf;
+extern cpuop_func_ce op_b139_13_ff;
+extern cpuop_func_ce op_b140_13_nf;
+extern cpuop_func_ce op_b140_13_ff;
+extern cpuop_func_ce op_b148_13_nf;
+extern cpuop_func_ce op_b148_13_ff;
+extern cpuop_func_ce op_b150_13_nf;
+extern cpuop_func_ce op_b150_13_ff;
+extern cpuop_func_ce op_b158_13_nf;
+extern cpuop_func_ce op_b158_13_ff;
+extern cpuop_func_ce op_b160_13_nf;
+extern cpuop_func_ce op_b160_13_ff;
+extern cpuop_func_ce op_b168_13_nf;
+extern cpuop_func_ce op_b168_13_ff;
+extern cpuop_func_ce op_b170_13_nf;
+extern cpuop_func_ce op_b170_13_ff;
+extern cpuop_func_ce op_b178_13_nf;
+extern cpuop_func_ce op_b178_13_ff;
+extern cpuop_func_ce op_b179_13_nf;
+extern cpuop_func_ce op_b179_13_ff;
+extern cpuop_func_ce op_b180_13_nf;
+extern cpuop_func_ce op_b180_13_ff;
+extern cpuop_func_ce op_b188_13_nf;
+extern cpuop_func_ce op_b188_13_ff;
+extern cpuop_func_ce op_b190_13_nf;
+extern cpuop_func_ce op_b190_13_ff;
+extern cpuop_func_ce op_b198_13_nf;
+extern cpuop_func_ce op_b198_13_ff;
+extern cpuop_func_ce op_b1a0_13_nf;
+extern cpuop_func_ce op_b1a0_13_ff;
+extern cpuop_func_ce op_b1a8_13_nf;
+extern cpuop_func_ce op_b1a8_13_ff;
+extern cpuop_func_ce op_b1b0_13_nf;
+extern cpuop_func_ce op_b1b0_13_ff;
+extern cpuop_func_ce op_b1b8_13_nf;
+extern cpuop_func_ce op_b1b8_13_ff;
+extern cpuop_func_ce op_b1b9_13_nf;
+extern cpuop_func_ce op_b1b9_13_ff;
+extern cpuop_func_ce op_b1c0_13_nf;
+extern cpuop_func_ce op_b1c0_13_ff;
+extern cpuop_func_ce op_b1c8_13_nf;
+extern cpuop_func_ce op_b1c8_13_ff;
+extern cpuop_func_ce op_b1d0_13_nf;
+extern cpuop_func_ce op_b1d0_13_ff;
+extern cpuop_func_ce op_b1d8_13_nf;
+extern cpuop_func_ce op_b1d8_13_ff;
+extern cpuop_func_ce op_b1e0_13_nf;
+extern cpuop_func_ce op_b1e0_13_ff;
+extern cpuop_func_ce op_b1e8_13_nf;
+extern cpuop_func_ce op_b1e8_13_ff;
+extern cpuop_func_ce op_b1f0_13_nf;
+extern cpuop_func_ce op_b1f0_13_ff;
+extern cpuop_func_ce op_b1f8_13_nf;
+extern cpuop_func_ce op_b1f8_13_ff;
+extern cpuop_func_ce op_b1f9_13_nf;
+extern cpuop_func_ce op_b1f9_13_ff;
+extern cpuop_func_ce op_b1fa_13_nf;
+extern cpuop_func_ce op_b1fa_13_ff;
+extern cpuop_func_ce op_b1fb_13_nf;
+extern cpuop_func_ce op_b1fb_13_ff;
+extern cpuop_func_ce op_b1fc_13_nf;
+extern cpuop_func_ce op_b1fc_13_ff;
+extern cpuop_func_ce op_c000_13_nf;
+extern cpuop_func_ce op_c000_13_ff;
+extern cpuop_func_ce op_c010_13_nf;
+extern cpuop_func_ce op_c010_13_ff;
+extern cpuop_func_ce op_c018_13_nf;
+extern cpuop_func_ce op_c018_13_ff;
+extern cpuop_func_ce op_c020_13_nf;
+extern cpuop_func_ce op_c020_13_ff;
+extern cpuop_func_ce op_c028_13_nf;
+extern cpuop_func_ce op_c028_13_ff;
+extern cpuop_func_ce op_c030_13_nf;
+extern cpuop_func_ce op_c030_13_ff;
+extern cpuop_func_ce op_c038_13_nf;
+extern cpuop_func_ce op_c038_13_ff;
+extern cpuop_func_ce op_c039_13_nf;
+extern cpuop_func_ce op_c039_13_ff;
+extern cpuop_func_ce op_c03a_13_nf;
+extern cpuop_func_ce op_c03a_13_ff;
+extern cpuop_func_ce op_c03b_13_nf;
+extern cpuop_func_ce op_c03b_13_ff;
+extern cpuop_func_ce op_c03c_13_nf;
+extern cpuop_func_ce op_c03c_13_ff;
+extern cpuop_func_ce op_c040_13_nf;
+extern cpuop_func_ce op_c040_13_ff;
+extern cpuop_func_ce op_c050_13_nf;
+extern cpuop_func_ce op_c050_13_ff;
+extern cpuop_func_ce op_c058_13_nf;
+extern cpuop_func_ce op_c058_13_ff;
+extern cpuop_func_ce op_c060_13_nf;
+extern cpuop_func_ce op_c060_13_ff;
+extern cpuop_func_ce op_c068_13_nf;
+extern cpuop_func_ce op_c068_13_ff;
+extern cpuop_func_ce op_c070_13_nf;
+extern cpuop_func_ce op_c070_13_ff;
+extern cpuop_func_ce op_c078_13_nf;
+extern cpuop_func_ce op_c078_13_ff;
+extern cpuop_func_ce op_c079_13_nf;
+extern cpuop_func_ce op_c079_13_ff;
+extern cpuop_func_ce op_c07a_13_nf;
+extern cpuop_func_ce op_c07a_13_ff;
+extern cpuop_func_ce op_c07b_13_nf;
+extern cpuop_func_ce op_c07b_13_ff;
+extern cpuop_func_ce op_c07c_13_nf;
+extern cpuop_func_ce op_c07c_13_ff;
+extern cpuop_func_ce op_c080_13_nf;
+extern cpuop_func_ce op_c080_13_ff;
+extern cpuop_func_ce op_c090_13_nf;
+extern cpuop_func_ce op_c090_13_ff;
+extern cpuop_func_ce op_c098_13_nf;
+extern cpuop_func_ce op_c098_13_ff;
+extern cpuop_func_ce op_c0a0_13_nf;
+extern cpuop_func_ce op_c0a0_13_ff;
+extern cpuop_func_ce op_c0a8_13_nf;
+extern cpuop_func_ce op_c0a8_13_ff;
+extern cpuop_func_ce op_c0b0_13_nf;
+extern cpuop_func_ce op_c0b0_13_ff;
+extern cpuop_func_ce op_c0b8_13_nf;
+extern cpuop_func_ce op_c0b8_13_ff;
+extern cpuop_func_ce op_c0b9_13_nf;
+extern cpuop_func_ce op_c0b9_13_ff;
+extern cpuop_func_ce op_c0ba_13_nf;
+extern cpuop_func_ce op_c0ba_13_ff;
+extern cpuop_func_ce op_c0bb_13_nf;
+extern cpuop_func_ce op_c0bb_13_ff;
+extern cpuop_func_ce op_c0bc_13_nf;
+extern cpuop_func_ce op_c0bc_13_ff;
+extern cpuop_func_ce op_c0c0_13_nf;
+extern cpuop_func_ce op_c0c0_13_ff;
+extern cpuop_func_ce op_c0d0_13_nf;
+extern cpuop_func_ce op_c0d0_13_ff;
+extern cpuop_func_ce op_c0d8_13_nf;
+extern cpuop_func_ce op_c0d8_13_ff;
+extern cpuop_func_ce op_c0e0_13_nf;
+extern cpuop_func_ce op_c0e0_13_ff;
+extern cpuop_func_ce op_c0e8_13_nf;
+extern cpuop_func_ce op_c0e8_13_ff;
+extern cpuop_func_ce op_c0f0_13_nf;
+extern cpuop_func_ce op_c0f0_13_ff;
+extern cpuop_func_ce op_c0f8_13_nf;
+extern cpuop_func_ce op_c0f8_13_ff;
+extern cpuop_func_ce op_c0f9_13_nf;
+extern cpuop_func_ce op_c0f9_13_ff;
+extern cpuop_func_ce op_c0fa_13_nf;
+extern cpuop_func_ce op_c0fa_13_ff;
+extern cpuop_func_ce op_c0fb_13_nf;
+extern cpuop_func_ce op_c0fb_13_ff;
+extern cpuop_func_ce op_c0fc_13_nf;
+extern cpuop_func_ce op_c0fc_13_ff;
+extern cpuop_func_ce op_c100_13_nf;
+extern cpuop_func_ce op_c100_13_ff;
+extern cpuop_func_ce op_c108_13_nf;
+extern cpuop_func_ce op_c108_13_ff;
+extern cpuop_func_ce op_c110_13_nf;
+extern cpuop_func_ce op_c110_13_ff;
+extern cpuop_func_ce op_c118_13_nf;
+extern cpuop_func_ce op_c118_13_ff;
+extern cpuop_func_ce op_c120_13_nf;
+extern cpuop_func_ce op_c120_13_ff;
+extern cpuop_func_ce op_c128_13_nf;
+extern cpuop_func_ce op_c128_13_ff;
+extern cpuop_func_ce op_c130_13_nf;
+extern cpuop_func_ce op_c130_13_ff;
+extern cpuop_func_ce op_c138_13_nf;
+extern cpuop_func_ce op_c138_13_ff;
+extern cpuop_func_ce op_c139_13_nf;
+extern cpuop_func_ce op_c139_13_ff;
+extern cpuop_func_ce op_c140_13_nf;
+extern cpuop_func_ce op_c140_13_ff;
+extern cpuop_func_ce op_c148_13_nf;
+extern cpuop_func_ce op_c148_13_ff;
+extern cpuop_func_ce op_c150_13_nf;
+extern cpuop_func_ce op_c150_13_ff;
+extern cpuop_func_ce op_c158_13_nf;
+extern cpuop_func_ce op_c158_13_ff;
+extern cpuop_func_ce op_c160_13_nf;
+extern cpuop_func_ce op_c160_13_ff;
+extern cpuop_func_ce op_c168_13_nf;
+extern cpuop_func_ce op_c168_13_ff;
+extern cpuop_func_ce op_c170_13_nf;
+extern cpuop_func_ce op_c170_13_ff;
+extern cpuop_func_ce op_c178_13_nf;
+extern cpuop_func_ce op_c178_13_ff;
+extern cpuop_func_ce op_c179_13_nf;
+extern cpuop_func_ce op_c179_13_ff;
+extern cpuop_func_ce op_c188_13_nf;
+extern cpuop_func_ce op_c188_13_ff;
+extern cpuop_func_ce op_c190_13_nf;
+extern cpuop_func_ce op_c190_13_ff;
+extern cpuop_func_ce op_c198_13_nf;
+extern cpuop_func_ce op_c198_13_ff;
+extern cpuop_func_ce op_c1a0_13_nf;
+extern cpuop_func_ce op_c1a0_13_ff;
+extern cpuop_func_ce op_c1a8_13_nf;
+extern cpuop_func_ce op_c1a8_13_ff;
+extern cpuop_func_ce op_c1b0_13_nf;
+extern cpuop_func_ce op_c1b0_13_ff;
+extern cpuop_func_ce op_c1b8_13_nf;
+extern cpuop_func_ce op_c1b8_13_ff;
+extern cpuop_func_ce op_c1b9_13_nf;
+extern cpuop_func_ce op_c1b9_13_ff;
+extern cpuop_func_ce op_c1c0_13_nf;
+extern cpuop_func_ce op_c1c0_13_ff;
+extern cpuop_func_ce op_c1d0_13_nf;
+extern cpuop_func_ce op_c1d0_13_ff;
+extern cpuop_func_ce op_c1d8_13_nf;
+extern cpuop_func_ce op_c1d8_13_ff;
+extern cpuop_func_ce op_c1e0_13_nf;
+extern cpuop_func_ce op_c1e0_13_ff;
+extern cpuop_func_ce op_c1e8_13_nf;
+extern cpuop_func_ce op_c1e8_13_ff;
+extern cpuop_func_ce op_c1f0_13_nf;
+extern cpuop_func_ce op_c1f0_13_ff;
+extern cpuop_func_ce op_c1f8_13_nf;
+extern cpuop_func_ce op_c1f8_13_ff;
+extern cpuop_func_ce op_c1f9_13_nf;
+extern cpuop_func_ce op_c1f9_13_ff;
+extern cpuop_func_ce op_c1fa_13_nf;
+extern cpuop_func_ce op_c1fa_13_ff;
+extern cpuop_func_ce op_c1fb_13_nf;
+extern cpuop_func_ce op_c1fb_13_ff;
+extern cpuop_func_ce op_c1fc_13_nf;
+extern cpuop_func_ce op_c1fc_13_ff;
+extern cpuop_func_ce op_d000_13_nf;
+extern cpuop_func_ce op_d000_13_ff;
+extern cpuop_func_ce op_d010_13_nf;
+extern cpuop_func_ce op_d010_13_ff;
+extern cpuop_func_ce op_d018_13_nf;
+extern cpuop_func_ce op_d018_13_ff;
+extern cpuop_func_ce op_d020_13_nf;
+extern cpuop_func_ce op_d020_13_ff;
+extern cpuop_func_ce op_d028_13_nf;
+extern cpuop_func_ce op_d028_13_ff;
+extern cpuop_func_ce op_d030_13_nf;
+extern cpuop_func_ce op_d030_13_ff;
+extern cpuop_func_ce op_d038_13_nf;
+extern cpuop_func_ce op_d038_13_ff;
+extern cpuop_func_ce op_d039_13_nf;
+extern cpuop_func_ce op_d039_13_ff;
+extern cpuop_func_ce op_d03a_13_nf;
+extern cpuop_func_ce op_d03a_13_ff;
+extern cpuop_func_ce op_d03b_13_nf;
+extern cpuop_func_ce op_d03b_13_ff;
+extern cpuop_func_ce op_d03c_13_nf;
+extern cpuop_func_ce op_d03c_13_ff;
+extern cpuop_func_ce op_d040_13_nf;
+extern cpuop_func_ce op_d040_13_ff;
+extern cpuop_func_ce op_d048_13_nf;
+extern cpuop_func_ce op_d048_13_ff;
+extern cpuop_func_ce op_d050_13_nf;
+extern cpuop_func_ce op_d050_13_ff;
+extern cpuop_func_ce op_d058_13_nf;
+extern cpuop_func_ce op_d058_13_ff;
+extern cpuop_func_ce op_d060_13_nf;
+extern cpuop_func_ce op_d060_13_ff;
+extern cpuop_func_ce op_d068_13_nf;
+extern cpuop_func_ce op_d068_13_ff;
+extern cpuop_func_ce op_d070_13_nf;
+extern cpuop_func_ce op_d070_13_ff;
+extern cpuop_func_ce op_d078_13_nf;
+extern cpuop_func_ce op_d078_13_ff;
+extern cpuop_func_ce op_d079_13_nf;
+extern cpuop_func_ce op_d079_13_ff;
+extern cpuop_func_ce op_d07a_13_nf;
+extern cpuop_func_ce op_d07a_13_ff;
+extern cpuop_func_ce op_d07b_13_nf;
+extern cpuop_func_ce op_d07b_13_ff;
+extern cpuop_func_ce op_d07c_13_nf;
+extern cpuop_func_ce op_d07c_13_ff;
+extern cpuop_func_ce op_d080_13_nf;
+extern cpuop_func_ce op_d080_13_ff;
+extern cpuop_func_ce op_d088_13_nf;
+extern cpuop_func_ce op_d088_13_ff;
+extern cpuop_func_ce op_d090_13_nf;
+extern cpuop_func_ce op_d090_13_ff;
+extern cpuop_func_ce op_d098_13_nf;
+extern cpuop_func_ce op_d098_13_ff;
+extern cpuop_func_ce op_d0a0_13_nf;
+extern cpuop_func_ce op_d0a0_13_ff;
+extern cpuop_func_ce op_d0a8_13_nf;
+extern cpuop_func_ce op_d0a8_13_ff;
+extern cpuop_func_ce op_d0b0_13_nf;
+extern cpuop_func_ce op_d0b0_13_ff;
+extern cpuop_func_ce op_d0b8_13_nf;
+extern cpuop_func_ce op_d0b8_13_ff;
+extern cpuop_func_ce op_d0b9_13_nf;
+extern cpuop_func_ce op_d0b9_13_ff;
+extern cpuop_func_ce op_d0ba_13_nf;
+extern cpuop_func_ce op_d0ba_13_ff;
+extern cpuop_func_ce op_d0bb_13_nf;
+extern cpuop_func_ce op_d0bb_13_ff;
+extern cpuop_func_ce op_d0bc_13_nf;
+extern cpuop_func_ce op_d0bc_13_ff;
+extern cpuop_func_ce op_d0c0_13_nf;
+extern cpuop_func_ce op_d0c0_13_ff;
+extern cpuop_func_ce op_d0c8_13_nf;
+extern cpuop_func_ce op_d0c8_13_ff;
+extern cpuop_func_ce op_d0d0_13_nf;
+extern cpuop_func_ce op_d0d0_13_ff;
+extern cpuop_func_ce op_d0d8_13_nf;
+extern cpuop_func_ce op_d0d8_13_ff;
+extern cpuop_func_ce op_d0e0_13_nf;
+extern cpuop_func_ce op_d0e0_13_ff;
+extern cpuop_func_ce op_d0e8_13_nf;
+extern cpuop_func_ce op_d0e8_13_ff;
+extern cpuop_func_ce op_d0f0_13_nf;
+extern cpuop_func_ce op_d0f0_13_ff;
+extern cpuop_func_ce op_d0f8_13_nf;
+extern cpuop_func_ce op_d0f8_13_ff;
+extern cpuop_func_ce op_d0f9_13_nf;
+extern cpuop_func_ce op_d0f9_13_ff;
+extern cpuop_func_ce op_d0fa_13_nf;
+extern cpuop_func_ce op_d0fa_13_ff;
+extern cpuop_func_ce op_d0fb_13_nf;
+extern cpuop_func_ce op_d0fb_13_ff;
+extern cpuop_func_ce op_d0fc_13_nf;
+extern cpuop_func_ce op_d0fc_13_ff;
+extern cpuop_func_ce op_d100_13_nf;
+extern cpuop_func_ce op_d100_13_ff;
+extern cpuop_func_ce op_d108_13_nf;
+extern cpuop_func_ce op_d108_13_ff;
+extern cpuop_func_ce op_d110_13_nf;
+extern cpuop_func_ce op_d110_13_ff;
+extern cpuop_func_ce op_d118_13_nf;
+extern cpuop_func_ce op_d118_13_ff;
+extern cpuop_func_ce op_d120_13_nf;
+extern cpuop_func_ce op_d120_13_ff;
+extern cpuop_func_ce op_d128_13_nf;
+extern cpuop_func_ce op_d128_13_ff;
+extern cpuop_func_ce op_d130_13_nf;
+extern cpuop_func_ce op_d130_13_ff;
+extern cpuop_func_ce op_d138_13_nf;
+extern cpuop_func_ce op_d138_13_ff;
+extern cpuop_func_ce op_d139_13_nf;
+extern cpuop_func_ce op_d139_13_ff;
+extern cpuop_func_ce op_d140_13_nf;
+extern cpuop_func_ce op_d140_13_ff;
+extern cpuop_func_ce op_d148_13_nf;
+extern cpuop_func_ce op_d148_13_ff;
+extern cpuop_func_ce op_d150_13_nf;
+extern cpuop_func_ce op_d150_13_ff;
+extern cpuop_func_ce op_d158_13_nf;
+extern cpuop_func_ce op_d158_13_ff;
+extern cpuop_func_ce op_d160_13_nf;
+extern cpuop_func_ce op_d160_13_ff;
+extern cpuop_func_ce op_d168_13_nf;
+extern cpuop_func_ce op_d168_13_ff;
+extern cpuop_func_ce op_d170_13_nf;
+extern cpuop_func_ce op_d170_13_ff;
+extern cpuop_func_ce op_d178_13_nf;
+extern cpuop_func_ce op_d178_13_ff;
+extern cpuop_func_ce op_d179_13_nf;
+extern cpuop_func_ce op_d179_13_ff;
+extern cpuop_func_ce op_d180_13_nf;
+extern cpuop_func_ce op_d180_13_ff;
+extern cpuop_func_ce op_d188_13_nf;
+extern cpuop_func_ce op_d188_13_ff;
+extern cpuop_func_ce op_d190_13_nf;
+extern cpuop_func_ce op_d190_13_ff;
+extern cpuop_func_ce op_d198_13_nf;
+extern cpuop_func_ce op_d198_13_ff;
+extern cpuop_func_ce op_d1a0_13_nf;
+extern cpuop_func_ce op_d1a0_13_ff;
+extern cpuop_func_ce op_d1a8_13_nf;
+extern cpuop_func_ce op_d1a8_13_ff;
+extern cpuop_func_ce op_d1b0_13_nf;
+extern cpuop_func_ce op_d1b0_13_ff;
+extern cpuop_func_ce op_d1b8_13_nf;
+extern cpuop_func_ce op_d1b8_13_ff;
+extern cpuop_func_ce op_d1b9_13_nf;
+extern cpuop_func_ce op_d1b9_13_ff;
+extern cpuop_func_ce op_d1c0_13_nf;
+extern cpuop_func_ce op_d1c0_13_ff;
+extern cpuop_func_ce op_d1c8_13_nf;
+extern cpuop_func_ce op_d1c8_13_ff;
+extern cpuop_func_ce op_d1d0_13_nf;
+extern cpuop_func_ce op_d1d0_13_ff;
+extern cpuop_func_ce op_d1d8_13_nf;
+extern cpuop_func_ce op_d1d8_13_ff;
+extern cpuop_func_ce op_d1e0_13_nf;
+extern cpuop_func_ce op_d1e0_13_ff;
+extern cpuop_func_ce op_d1e8_13_nf;
+extern cpuop_func_ce op_d1e8_13_ff;
+extern cpuop_func_ce op_d1f0_13_nf;
+extern cpuop_func_ce op_d1f0_13_ff;
+extern cpuop_func_ce op_d1f8_13_nf;
+extern cpuop_func_ce op_d1f8_13_ff;
+extern cpuop_func_ce op_d1f9_13_nf;
+extern cpuop_func_ce op_d1f9_13_ff;
+extern cpuop_func_ce op_d1fa_13_nf;
+extern cpuop_func_ce op_d1fa_13_ff;
+extern cpuop_func_ce op_d1fb_13_nf;
+extern cpuop_func_ce op_d1fb_13_ff;
+extern cpuop_func_ce op_d1fc_13_nf;
+extern cpuop_func_ce op_d1fc_13_ff;
+extern cpuop_func_ce op_e000_13_nf;
+extern cpuop_func_ce op_e000_13_ff;
+extern cpuop_func_ce op_e008_13_nf;
+extern cpuop_func_ce op_e008_13_ff;
+extern cpuop_func_ce op_e010_13_nf;
+extern cpuop_func_ce op_e010_13_ff;
+extern cpuop_func_ce op_e018_13_nf;
+extern cpuop_func_ce op_e018_13_ff;
+extern cpuop_func_ce op_e020_13_nf;
+extern cpuop_func_ce op_e020_13_ff;
+extern cpuop_func_ce op_e028_13_nf;
+extern cpuop_func_ce op_e028_13_ff;
+extern cpuop_func_ce op_e030_13_nf;
+extern cpuop_func_ce op_e030_13_ff;
+extern cpuop_func_ce op_e038_13_nf;
+extern cpuop_func_ce op_e038_13_ff;
+extern cpuop_func_ce op_e040_13_nf;
+extern cpuop_func_ce op_e040_13_ff;
+extern cpuop_func_ce op_e048_13_nf;
+extern cpuop_func_ce op_e048_13_ff;
+extern cpuop_func_ce op_e050_13_nf;
+extern cpuop_func_ce op_e050_13_ff;
+extern cpuop_func_ce op_e058_13_nf;
+extern cpuop_func_ce op_e058_13_ff;
+extern cpuop_func_ce op_e060_13_nf;
+extern cpuop_func_ce op_e060_13_ff;
+extern cpuop_func_ce op_e068_13_nf;
+extern cpuop_func_ce op_e068_13_ff;
+extern cpuop_func_ce op_e070_13_nf;
+extern cpuop_func_ce op_e070_13_ff;
+extern cpuop_func_ce op_e078_13_nf;
+extern cpuop_func_ce op_e078_13_ff;
+extern cpuop_func_ce op_e080_13_nf;
+extern cpuop_func_ce op_e080_13_ff;
+extern cpuop_func_ce op_e088_13_nf;
+extern cpuop_func_ce op_e088_13_ff;
+extern cpuop_func_ce op_e090_13_nf;
+extern cpuop_func_ce op_e090_13_ff;
+extern cpuop_func_ce op_e098_13_nf;
+extern cpuop_func_ce op_e098_13_ff;
+extern cpuop_func_ce op_e0a0_13_nf;
+extern cpuop_func_ce op_e0a0_13_ff;
+extern cpuop_func_ce op_e0a8_13_nf;
+extern cpuop_func_ce op_e0a8_13_ff;
+extern cpuop_func_ce op_e0b0_13_nf;
+extern cpuop_func_ce op_e0b0_13_ff;
+extern cpuop_func_ce op_e0b8_13_nf;
+extern cpuop_func_ce op_e0b8_13_ff;
+extern cpuop_func_ce op_e0d0_13_nf;
+extern cpuop_func_ce op_e0d0_13_ff;
+extern cpuop_func_ce op_e0d8_13_nf;
+extern cpuop_func_ce op_e0d8_13_ff;
+extern cpuop_func_ce op_e0e0_13_nf;
+extern cpuop_func_ce op_e0e0_13_ff;
+extern cpuop_func_ce op_e0e8_13_nf;
+extern cpuop_func_ce op_e0e8_13_ff;
+extern cpuop_func_ce op_e0f0_13_nf;
+extern cpuop_func_ce op_e0f0_13_ff;
+extern cpuop_func_ce op_e0f8_13_nf;
+extern cpuop_func_ce op_e0f8_13_ff;
+extern cpuop_func_ce op_e0f9_13_nf;
+extern cpuop_func_ce op_e0f9_13_ff;
+extern cpuop_func_ce op_e100_13_nf;
+extern cpuop_func_ce op_e100_13_ff;
+extern cpuop_func_ce op_e108_13_nf;
+extern cpuop_func_ce op_e108_13_ff;
+extern cpuop_func_ce op_e110_13_nf;
+extern cpuop_func_ce op_e110_13_ff;
+extern cpuop_func_ce op_e118_13_nf;
+extern cpuop_func_ce op_e118_13_ff;
+extern cpuop_func_ce op_e120_13_nf;
+extern cpuop_func_ce op_e120_13_ff;
+extern cpuop_func_ce op_e128_13_nf;
+extern cpuop_func_ce op_e128_13_ff;
+extern cpuop_func_ce op_e130_13_nf;
+extern cpuop_func_ce op_e130_13_ff;
+extern cpuop_func_ce op_e138_13_nf;
+extern cpuop_func_ce op_e138_13_ff;
+extern cpuop_func_ce op_e140_13_nf;
+extern cpuop_func_ce op_e140_13_ff;
+extern cpuop_func_ce op_e148_13_nf;
+extern cpuop_func_ce op_e148_13_ff;
+extern cpuop_func_ce op_e150_13_nf;
+extern cpuop_func_ce op_e150_13_ff;
+extern cpuop_func_ce op_e158_13_nf;
+extern cpuop_func_ce op_e158_13_ff;
+extern cpuop_func_ce op_e160_13_nf;
+extern cpuop_func_ce op_e160_13_ff;
+extern cpuop_func_ce op_e168_13_nf;
+extern cpuop_func_ce op_e168_13_ff;
+extern cpuop_func_ce op_e170_13_nf;
+extern cpuop_func_ce op_e170_13_ff;
+extern cpuop_func_ce op_e178_13_nf;
+extern cpuop_func_ce op_e178_13_ff;
+extern cpuop_func_ce op_e180_13_nf;
+extern cpuop_func_ce op_e180_13_ff;
+extern cpuop_func_ce op_e188_13_nf;
+extern cpuop_func_ce op_e188_13_ff;
+extern cpuop_func_ce op_e190_13_nf;
+extern cpuop_func_ce op_e190_13_ff;
+extern cpuop_func_ce op_e198_13_nf;
+extern cpuop_func_ce op_e198_13_ff;
+extern cpuop_func_ce op_e1a0_13_nf;
+extern cpuop_func_ce op_e1a0_13_ff;
+extern cpuop_func_ce op_e1a8_13_nf;
+extern cpuop_func_ce op_e1a8_13_ff;
+extern cpuop_func_ce op_e1b0_13_nf;
+extern cpuop_func_ce op_e1b0_13_ff;
+extern cpuop_func_ce op_e1b8_13_nf;
+extern cpuop_func_ce op_e1b8_13_ff;
+extern cpuop_func_ce op_e1d0_13_nf;
+extern cpuop_func_ce op_e1d0_13_ff;
+extern cpuop_func_ce op_e1d8_13_nf;
+extern cpuop_func_ce op_e1d8_13_ff;
+extern cpuop_func_ce op_e1e0_13_nf;
+extern cpuop_func_ce op_e1e0_13_ff;
+extern cpuop_func_ce op_e1e8_13_nf;
+extern cpuop_func_ce op_e1e8_13_ff;
+extern cpuop_func_ce op_e1f0_13_nf;
+extern cpuop_func_ce op_e1f0_13_ff;
+extern cpuop_func_ce op_e1f8_13_nf;
+extern cpuop_func_ce op_e1f8_13_ff;
+extern cpuop_func_ce op_e1f9_13_nf;
+extern cpuop_func_ce op_e1f9_13_ff;
+extern cpuop_func_ce op_e2d0_13_nf;
+extern cpuop_func_ce op_e2d0_13_ff;
+extern cpuop_func_ce op_e2d8_13_nf;
+extern cpuop_func_ce op_e2d8_13_ff;
+extern cpuop_func_ce op_e2e0_13_nf;
+extern cpuop_func_ce op_e2e0_13_ff;
+extern cpuop_func_ce op_e2e8_13_nf;
+extern cpuop_func_ce op_e2e8_13_ff;
+extern cpuop_func_ce op_e2f0_13_nf;
+extern cpuop_func_ce op_e2f0_13_ff;
+extern cpuop_func_ce op_e2f8_13_nf;
+extern cpuop_func_ce op_e2f8_13_ff;
+extern cpuop_func_ce op_e2f9_13_nf;
+extern cpuop_func_ce op_e2f9_13_ff;
+extern cpuop_func_ce op_e3d0_13_nf;
+extern cpuop_func_ce op_e3d0_13_ff;
+extern cpuop_func_ce op_e3d8_13_nf;
+extern cpuop_func_ce op_e3d8_13_ff;
+extern cpuop_func_ce op_e3e0_13_nf;
+extern cpuop_func_ce op_e3e0_13_ff;
+extern cpuop_func_ce op_e3e8_13_nf;
+extern cpuop_func_ce op_e3e8_13_ff;
+extern cpuop_func_ce op_e3f0_13_nf;
+extern cpuop_func_ce op_e3f0_13_ff;
+extern cpuop_func_ce op_e3f8_13_nf;
+extern cpuop_func_ce op_e3f8_13_ff;
+extern cpuop_func_ce op_e3f9_13_nf;
+extern cpuop_func_ce op_e3f9_13_ff;
+extern cpuop_func_ce op_e4d0_13_nf;
+extern cpuop_func_ce op_e4d0_13_ff;
+extern cpuop_func_ce op_e4d8_13_nf;
+extern cpuop_func_ce op_e4d8_13_ff;
+extern cpuop_func_ce op_e4e0_13_nf;
+extern cpuop_func_ce op_e4e0_13_ff;
+extern cpuop_func_ce op_e4e8_13_nf;
+extern cpuop_func_ce op_e4e8_13_ff;
+extern cpuop_func_ce op_e4f0_13_nf;
+extern cpuop_func_ce op_e4f0_13_ff;
+extern cpuop_func_ce op_e4f8_13_nf;
+extern cpuop_func_ce op_e4f8_13_ff;
+extern cpuop_func_ce op_e4f9_13_nf;
+extern cpuop_func_ce op_e4f9_13_ff;
+extern cpuop_func_ce op_e5d0_13_nf;
+extern cpuop_func_ce op_e5d0_13_ff;
+extern cpuop_func_ce op_e5d8_13_nf;
+extern cpuop_func_ce op_e5d8_13_ff;
+extern cpuop_func_ce op_e5e0_13_nf;
+extern cpuop_func_ce op_e5e0_13_ff;
+extern cpuop_func_ce op_e5e8_13_nf;
+extern cpuop_func_ce op_e5e8_13_ff;
+extern cpuop_func_ce op_e5f0_13_nf;
+extern cpuop_func_ce op_e5f0_13_ff;
+extern cpuop_func_ce op_e5f8_13_nf;
+extern cpuop_func_ce op_e5f8_13_ff;
+extern cpuop_func_ce op_e5f9_13_nf;
+extern cpuop_func_ce op_e5f9_13_ff;
+extern cpuop_func_ce op_e6d0_13_nf;
+extern cpuop_func_ce op_e6d0_13_ff;
+extern cpuop_func_ce op_e6d8_13_nf;
+extern cpuop_func_ce op_e6d8_13_ff;
+extern cpuop_func_ce op_e6e0_13_nf;
+extern cpuop_func_ce op_e6e0_13_ff;
+extern cpuop_func_ce op_e6e8_13_nf;
+extern cpuop_func_ce op_e6e8_13_ff;
+extern cpuop_func_ce op_e6f0_13_nf;
+extern cpuop_func_ce op_e6f0_13_ff;
+extern cpuop_func_ce op_e6f8_13_nf;
+extern cpuop_func_ce op_e6f8_13_ff;
+extern cpuop_func_ce op_e6f9_13_nf;
+extern cpuop_func_ce op_e6f9_13_ff;
+extern cpuop_func_ce op_e7d0_13_nf;
+extern cpuop_func_ce op_e7d0_13_ff;
+extern cpuop_func_ce op_e7d8_13_nf;
+extern cpuop_func_ce op_e7d8_13_ff;
+extern cpuop_func_ce op_e7e0_13_nf;
+extern cpuop_func_ce op_e7e0_13_ff;
+extern cpuop_func_ce op_e7e8_13_nf;
+extern cpuop_func_ce op_e7e8_13_ff;
+extern cpuop_func_ce op_e7f0_13_nf;
+extern cpuop_func_ce op_e7f0_13_ff;
+extern cpuop_func_ce op_e7f8_13_nf;
+extern cpuop_func_ce op_e7f8_13_ff;
+extern cpuop_func_ce op_e7f9_13_nf;
+extern cpuop_func_ce op_e7f9_13_ff;
+extern cpuop_func_ce op_40c0_14_nf;
+extern cpuop_func_ce op_40c0_14_ff;
+extern cpuop_func_ce op_40d0_14_nf;
+extern cpuop_func_ce op_40d0_14_ff;
+extern cpuop_func_ce op_40d8_14_nf;
+extern cpuop_func_ce op_40d8_14_ff;
+extern cpuop_func_ce op_40e0_14_nf;
+extern cpuop_func_ce op_40e0_14_ff;
+extern cpuop_func_ce op_40e8_14_nf;
+extern cpuop_func_ce op_40e8_14_ff;
+extern cpuop_func_ce op_40f0_14_nf;
+extern cpuop_func_ce op_40f0_14_ff;
+extern cpuop_func_ce op_40f8_14_nf;
+extern cpuop_func_ce op_40f8_14_ff;
+extern cpuop_func_ce op_40f9_14_nf;
+extern cpuop_func_ce op_40f9_14_ff;
+extern cpuop_func_ce op_4200_14_nf;
+extern cpuop_func_ce op_4200_14_ff;
+extern cpuop_func_ce op_4210_14_nf;
+extern cpuop_func_ce op_4210_14_ff;
+extern cpuop_func_ce op_4218_14_nf;
+extern cpuop_func_ce op_4218_14_ff;
+extern cpuop_func_ce op_4220_14_nf;
+extern cpuop_func_ce op_4220_14_ff;
+extern cpuop_func_ce op_4228_14_nf;
+extern cpuop_func_ce op_4228_14_ff;
+extern cpuop_func_ce op_4230_14_nf;
+extern cpuop_func_ce op_4230_14_ff;
+extern cpuop_func_ce op_4238_14_nf;
+extern cpuop_func_ce op_4238_14_ff;
+extern cpuop_func_ce op_4239_14_nf;
+extern cpuop_func_ce op_4239_14_ff;
+extern cpuop_func_ce op_4240_14_nf;
+extern cpuop_func_ce op_4240_14_ff;
+extern cpuop_func_ce op_4250_14_nf;
+extern cpuop_func_ce op_4250_14_ff;
+extern cpuop_func_ce op_4258_14_nf;
+extern cpuop_func_ce op_4258_14_ff;
+extern cpuop_func_ce op_4260_14_nf;
+extern cpuop_func_ce op_4260_14_ff;
+extern cpuop_func_ce op_4268_14_nf;
+extern cpuop_func_ce op_4268_14_ff;
+extern cpuop_func_ce op_4270_14_nf;
+extern cpuop_func_ce op_4270_14_ff;
+extern cpuop_func_ce op_4278_14_nf;
+extern cpuop_func_ce op_4278_14_ff;
+extern cpuop_func_ce op_4279_14_nf;
+extern cpuop_func_ce op_4279_14_ff;
+extern cpuop_func_ce op_4280_14_nf;
+extern cpuop_func_ce op_4280_14_ff;
+extern cpuop_func_ce op_4290_14_nf;
+extern cpuop_func_ce op_4290_14_ff;
+extern cpuop_func_ce op_4298_14_nf;
+extern cpuop_func_ce op_4298_14_ff;
+extern cpuop_func_ce op_42a0_14_nf;
+extern cpuop_func_ce op_42a0_14_ff;
+extern cpuop_func_ce op_42a8_14_nf;
+extern cpuop_func_ce op_42a8_14_ff;
+extern cpuop_func_ce op_42b0_14_nf;
+extern cpuop_func_ce op_42b0_14_ff;
+extern cpuop_func_ce op_42b8_14_nf;
+extern cpuop_func_ce op_42b8_14_ff;
+extern cpuop_func_ce op_42b9_14_nf;
+extern cpuop_func_ce op_42b9_14_ff;
+extern cpuop_func_ce op_4e73_14_nf;
+extern cpuop_func_ce op_4e73_14_ff;
+extern cpuop_func_ce op_50c0_14_nf;
+extern cpuop_func_ce op_50c0_14_ff;
+extern cpuop_func_ce op_50d0_14_nf;
+extern cpuop_func_ce op_50d0_14_ff;
+extern cpuop_func_ce op_50d8_14_nf;
+extern cpuop_func_ce op_50d8_14_ff;
+extern cpuop_func_ce op_50e0_14_nf;
+extern cpuop_func_ce op_50e0_14_ff;
+extern cpuop_func_ce op_50e8_14_nf;
+extern cpuop_func_ce op_50e8_14_ff;
+extern cpuop_func_ce op_50f0_14_nf;
+extern cpuop_func_ce op_50f0_14_ff;
+extern cpuop_func_ce op_50f8_14_nf;
+extern cpuop_func_ce op_50f8_14_ff;
+extern cpuop_func_ce op_50f9_14_nf;
+extern cpuop_func_ce op_50f9_14_ff;
+extern cpuop_func_ce op_51c0_14_nf;
+extern cpuop_func_ce op_51c0_14_ff;
+extern cpuop_func_ce op_51d0_14_nf;
+extern cpuop_func_ce op_51d0_14_ff;
+extern cpuop_func_ce op_51d8_14_nf;
+extern cpuop_func_ce op_51d8_14_ff;
+extern cpuop_func_ce op_51e0_14_nf;
+extern cpuop_func_ce op_51e0_14_ff;
+extern cpuop_func_ce op_51e8_14_nf;
+extern cpuop_func_ce op_51e8_14_ff;
+extern cpuop_func_ce op_51f0_14_nf;
+extern cpuop_func_ce op_51f0_14_ff;
+extern cpuop_func_ce op_51f8_14_nf;
+extern cpuop_func_ce op_51f8_14_ff;
+extern cpuop_func_ce op_51f9_14_nf;
+extern cpuop_func_ce op_51f9_14_ff;
+extern cpuop_func_ce op_52c0_14_nf;
+extern cpuop_func_ce op_52c0_14_ff;
+extern cpuop_func_ce op_52d0_14_nf;
+extern cpuop_func_ce op_52d0_14_ff;
+extern cpuop_func_ce op_52d8_14_nf;
+extern cpuop_func_ce op_52d8_14_ff;
+extern cpuop_func_ce op_52e0_14_nf;
+extern cpuop_func_ce op_52e0_14_ff;
+extern cpuop_func_ce op_52e8_14_nf;
+extern cpuop_func_ce op_52e8_14_ff;
+extern cpuop_func_ce op_52f0_14_nf;
+extern cpuop_func_ce op_52f0_14_ff;
+extern cpuop_func_ce op_52f8_14_nf;
+extern cpuop_func_ce op_52f8_14_ff;
+extern cpuop_func_ce op_52f9_14_nf;
+extern cpuop_func_ce op_52f9_14_ff;
+extern cpuop_func_ce op_53c0_14_nf;
+extern cpuop_func_ce op_53c0_14_ff;
+extern cpuop_func_ce op_53d0_14_nf;
+extern cpuop_func_ce op_53d0_14_ff;
+extern cpuop_func_ce op_53d8_14_nf;
+extern cpuop_func_ce op_53d8_14_ff;
+extern cpuop_func_ce op_53e0_14_nf;
+extern cpuop_func_ce op_53e0_14_ff;
+extern cpuop_func_ce op_53e8_14_nf;
+extern cpuop_func_ce op_53e8_14_ff;
+extern cpuop_func_ce op_53f0_14_nf;
+extern cpuop_func_ce op_53f0_14_ff;
+extern cpuop_func_ce op_53f8_14_nf;
+extern cpuop_func_ce op_53f8_14_ff;
+extern cpuop_func_ce op_53f9_14_nf;
+extern cpuop_func_ce op_53f9_14_ff;
+extern cpuop_func_ce op_54c0_14_nf;
+extern cpuop_func_ce op_54c0_14_ff;
+extern cpuop_func_ce op_54d0_14_nf;
+extern cpuop_func_ce op_54d0_14_ff;
+extern cpuop_func_ce op_54d8_14_nf;
+extern cpuop_func_ce op_54d8_14_ff;
+extern cpuop_func_ce op_54e0_14_nf;
+extern cpuop_func_ce op_54e0_14_ff;
+extern cpuop_func_ce op_54e8_14_nf;
+extern cpuop_func_ce op_54e8_14_ff;
+extern cpuop_func_ce op_54f0_14_nf;
+extern cpuop_func_ce op_54f0_14_ff;
+extern cpuop_func_ce op_54f8_14_nf;
+extern cpuop_func_ce op_54f8_14_ff;
+extern cpuop_func_ce op_54f9_14_nf;
+extern cpuop_func_ce op_54f9_14_ff;
+extern cpuop_func_ce op_55c0_14_nf;
+extern cpuop_func_ce op_55c0_14_ff;
+extern cpuop_func_ce op_55d0_14_nf;
+extern cpuop_func_ce op_55d0_14_ff;
+extern cpuop_func_ce op_55d8_14_nf;
+extern cpuop_func_ce op_55d8_14_ff;
+extern cpuop_func_ce op_55e0_14_nf;
+extern cpuop_func_ce op_55e0_14_ff;
+extern cpuop_func_ce op_55e8_14_nf;
+extern cpuop_func_ce op_55e8_14_ff;
+extern cpuop_func_ce op_55f0_14_nf;
+extern cpuop_func_ce op_55f0_14_ff;
+extern cpuop_func_ce op_55f8_14_nf;
+extern cpuop_func_ce op_55f8_14_ff;
+extern cpuop_func_ce op_55f9_14_nf;
+extern cpuop_func_ce op_55f9_14_ff;
+extern cpuop_func_ce op_56c0_14_nf;
+extern cpuop_func_ce op_56c0_14_ff;
+extern cpuop_func_ce op_56d0_14_nf;
+extern cpuop_func_ce op_56d0_14_ff;
+extern cpuop_func_ce op_56d8_14_nf;
+extern cpuop_func_ce op_56d8_14_ff;
+extern cpuop_func_ce op_56e0_14_nf;
+extern cpuop_func_ce op_56e0_14_ff;
+extern cpuop_func_ce op_56e8_14_nf;
+extern cpuop_func_ce op_56e8_14_ff;
+extern cpuop_func_ce op_56f0_14_nf;
+extern cpuop_func_ce op_56f0_14_ff;
+extern cpuop_func_ce op_56f8_14_nf;
+extern cpuop_func_ce op_56f8_14_ff;
+extern cpuop_func_ce op_56f9_14_nf;
+extern cpuop_func_ce op_56f9_14_ff;
+extern cpuop_func_ce op_57c0_14_nf;
+extern cpuop_func_ce op_57c0_14_ff;
+extern cpuop_func_ce op_57d0_14_nf;
+extern cpuop_func_ce op_57d0_14_ff;
+extern cpuop_func_ce op_57d8_14_nf;
+extern cpuop_func_ce op_57d8_14_ff;
+extern cpuop_func_ce op_57e0_14_nf;
+extern cpuop_func_ce op_57e0_14_ff;
+extern cpuop_func_ce op_57e8_14_nf;
+extern cpuop_func_ce op_57e8_14_ff;
+extern cpuop_func_ce op_57f0_14_nf;
+extern cpuop_func_ce op_57f0_14_ff;
+extern cpuop_func_ce op_57f8_14_nf;
+extern cpuop_func_ce op_57f8_14_ff;
+extern cpuop_func_ce op_57f9_14_nf;
+extern cpuop_func_ce op_57f9_14_ff;
+extern cpuop_func_ce op_58c0_14_nf;
+extern cpuop_func_ce op_58c0_14_ff;
+extern cpuop_func_ce op_58d0_14_nf;
+extern cpuop_func_ce op_58d0_14_ff;
+extern cpuop_func_ce op_58d8_14_nf;
+extern cpuop_func_ce op_58d8_14_ff;
+extern cpuop_func_ce op_58e0_14_nf;
+extern cpuop_func_ce op_58e0_14_ff;
+extern cpuop_func_ce op_58e8_14_nf;
+extern cpuop_func_ce op_58e8_14_ff;
+extern cpuop_func_ce op_58f0_14_nf;
+extern cpuop_func_ce op_58f0_14_ff;
+extern cpuop_func_ce op_58f8_14_nf;
+extern cpuop_func_ce op_58f8_14_ff;
+extern cpuop_func_ce op_58f9_14_nf;
+extern cpuop_func_ce op_58f9_14_ff;
+extern cpuop_func_ce op_59c0_14_nf;
+extern cpuop_func_ce op_59c0_14_ff;
+extern cpuop_func_ce op_59d0_14_nf;
+extern cpuop_func_ce op_59d0_14_ff;
+extern cpuop_func_ce op_59d8_14_nf;
+extern cpuop_func_ce op_59d8_14_ff;
+extern cpuop_func_ce op_59e0_14_nf;
+extern cpuop_func_ce op_59e0_14_ff;
+extern cpuop_func_ce op_59e8_14_nf;
+extern cpuop_func_ce op_59e8_14_ff;
+extern cpuop_func_ce op_59f0_14_nf;
+extern cpuop_func_ce op_59f0_14_ff;
+extern cpuop_func_ce op_59f8_14_nf;
+extern cpuop_func_ce op_59f8_14_ff;
+extern cpuop_func_ce op_59f9_14_nf;
+extern cpuop_func_ce op_59f9_14_ff;
+extern cpuop_func_ce op_5ac0_14_nf;
+extern cpuop_func_ce op_5ac0_14_ff;
+extern cpuop_func_ce op_5ad0_14_nf;
+extern cpuop_func_ce op_5ad0_14_ff;
+extern cpuop_func_ce op_5ad8_14_nf;
+extern cpuop_func_ce op_5ad8_14_ff;
+extern cpuop_func_ce op_5ae0_14_nf;
+extern cpuop_func_ce op_5ae0_14_ff;
+extern cpuop_func_ce op_5ae8_14_nf;
+extern cpuop_func_ce op_5ae8_14_ff;
+extern cpuop_func_ce op_5af0_14_nf;
+extern cpuop_func_ce op_5af0_14_ff;
+extern cpuop_func_ce op_5af8_14_nf;
+extern cpuop_func_ce op_5af8_14_ff;
+extern cpuop_func_ce op_5af9_14_nf;
+extern cpuop_func_ce op_5af9_14_ff;
+extern cpuop_func_ce op_5bc0_14_nf;
+extern cpuop_func_ce op_5bc0_14_ff;
+extern cpuop_func_ce op_5bd0_14_nf;
+extern cpuop_func_ce op_5bd0_14_ff;
+extern cpuop_func_ce op_5bd8_14_nf;
+extern cpuop_func_ce op_5bd8_14_ff;
+extern cpuop_func_ce op_5be0_14_nf;
+extern cpuop_func_ce op_5be0_14_ff;
+extern cpuop_func_ce op_5be8_14_nf;
+extern cpuop_func_ce op_5be8_14_ff;
+extern cpuop_func_ce op_5bf0_14_nf;
+extern cpuop_func_ce op_5bf0_14_ff;
+extern cpuop_func_ce op_5bf8_14_nf;
+extern cpuop_func_ce op_5bf8_14_ff;
+extern cpuop_func_ce op_5bf9_14_nf;
+extern cpuop_func_ce op_5bf9_14_ff;
+extern cpuop_func_ce op_5cc0_14_nf;
+extern cpuop_func_ce op_5cc0_14_ff;
+extern cpuop_func_ce op_5cd0_14_nf;
+extern cpuop_func_ce op_5cd0_14_ff;
+extern cpuop_func_ce op_5cd8_14_nf;
+extern cpuop_func_ce op_5cd8_14_ff;
+extern cpuop_func_ce op_5ce0_14_nf;
+extern cpuop_func_ce op_5ce0_14_ff;
+extern cpuop_func_ce op_5ce8_14_nf;
+extern cpuop_func_ce op_5ce8_14_ff;
+extern cpuop_func_ce op_5cf0_14_nf;
+extern cpuop_func_ce op_5cf0_14_ff;
+extern cpuop_func_ce op_5cf8_14_nf;
+extern cpuop_func_ce op_5cf8_14_ff;
+extern cpuop_func_ce op_5cf9_14_nf;
+extern cpuop_func_ce op_5cf9_14_ff;
+extern cpuop_func_ce op_5dc0_14_nf;
+extern cpuop_func_ce op_5dc0_14_ff;
+extern cpuop_func_ce op_5dd0_14_nf;
+extern cpuop_func_ce op_5dd0_14_ff;
+extern cpuop_func_ce op_5dd8_14_nf;
+extern cpuop_func_ce op_5dd8_14_ff;
+extern cpuop_func_ce op_5de0_14_nf;
+extern cpuop_func_ce op_5de0_14_ff;
+extern cpuop_func_ce op_5de8_14_nf;
+extern cpuop_func_ce op_5de8_14_ff;
+extern cpuop_func_ce op_5df0_14_nf;
+extern cpuop_func_ce op_5df0_14_ff;
+extern cpuop_func_ce op_5df8_14_nf;
+extern cpuop_func_ce op_5df8_14_ff;
+extern cpuop_func_ce op_5df9_14_nf;
+extern cpuop_func_ce op_5df9_14_ff;
+extern cpuop_func_ce op_5ec0_14_nf;
+extern cpuop_func_ce op_5ec0_14_ff;
+extern cpuop_func_ce op_5ed0_14_nf;
+extern cpuop_func_ce op_5ed0_14_ff;
+extern cpuop_func_ce op_5ed8_14_nf;
+extern cpuop_func_ce op_5ed8_14_ff;
+extern cpuop_func_ce op_5ee0_14_nf;
+extern cpuop_func_ce op_5ee0_14_ff;
+extern cpuop_func_ce op_5ee8_14_nf;
+extern cpuop_func_ce op_5ee8_14_ff;
+extern cpuop_func_ce op_5ef0_14_nf;
+extern cpuop_func_ce op_5ef0_14_ff;
+extern cpuop_func_ce op_5ef8_14_nf;
+extern cpuop_func_ce op_5ef8_14_ff;
+extern cpuop_func_ce op_5ef9_14_nf;
+extern cpuop_func_ce op_5ef9_14_ff;
+extern cpuop_func_ce op_5fc0_14_nf;
+extern cpuop_func_ce op_5fc0_14_ff;
+extern cpuop_func_ce op_5fd0_14_nf;
+extern cpuop_func_ce op_5fd0_14_ff;
+extern cpuop_func_ce op_5fd8_14_nf;
+extern cpuop_func_ce op_5fd8_14_ff;
+extern cpuop_func_ce op_5fe0_14_nf;
+extern cpuop_func_ce op_5fe0_14_ff;
+extern cpuop_func_ce op_5fe8_14_nf;
+extern cpuop_func_ce op_5fe8_14_ff;
+extern cpuop_func_ce op_5ff0_14_nf;
+extern cpuop_func_ce op_5ff0_14_ff;
+extern cpuop_func_ce op_5ff8_14_nf;
+extern cpuop_func_ce op_5ff8_14_ff;
+extern cpuop_func_ce op_5ff9_14_nf;
+extern cpuop_func_ce op_5ff9_14_ff;
+extern cpuop_func op_0000_20_nf;
+extern cpuop_func op_0000_20_ff;
+extern cpuop_func op_0010_20_nf;
+extern cpuop_func op_0010_20_ff;
+extern cpuop_func op_0018_20_nf;
+extern cpuop_func op_0018_20_ff;
+extern cpuop_func op_0020_20_nf;
+extern cpuop_func op_0020_20_ff;
+extern cpuop_func op_0028_20_nf;
+extern cpuop_func op_0028_20_ff;
+extern cpuop_func op_0030_20_nf;
+extern cpuop_func op_0030_20_ff;
+extern cpuop_func op_0038_20_nf;
+extern cpuop_func op_0038_20_ff;
+extern cpuop_func op_0039_20_nf;
+extern cpuop_func op_0039_20_ff;
+extern cpuop_func op_003c_20_nf;
+extern cpuop_func op_003c_20_ff;
+extern cpuop_func op_0040_20_nf;
+extern cpuop_func op_0040_20_ff;
+extern cpuop_func op_0050_20_nf;
+extern cpuop_func op_0050_20_ff;
+extern cpuop_func op_0058_20_nf;
+extern cpuop_func op_0058_20_ff;
+extern cpuop_func op_0060_20_nf;
+extern cpuop_func op_0060_20_ff;
+extern cpuop_func op_0068_20_nf;
+extern cpuop_func op_0068_20_ff;
+extern cpuop_func op_0070_20_nf;
+extern cpuop_func op_0070_20_ff;
+extern cpuop_func op_0078_20_nf;
+extern cpuop_func op_0078_20_ff;
+extern cpuop_func op_0079_20_nf;
+extern cpuop_func op_0079_20_ff;
+extern cpuop_func op_007c_20_nf;
+extern cpuop_func op_007c_20_ff;
+extern cpuop_func op_0080_20_nf;
+extern cpuop_func op_0080_20_ff;
+extern cpuop_func op_0090_20_nf;
+extern cpuop_func op_0090_20_ff;
+extern cpuop_func op_0098_20_nf;
+extern cpuop_func op_0098_20_ff;
+extern cpuop_func op_00a0_20_nf;
+extern cpuop_func op_00a0_20_ff;
+extern cpuop_func op_00a8_20_nf;
+extern cpuop_func op_00a8_20_ff;
+extern cpuop_func op_00b0_20_nf;
+extern cpuop_func op_00b0_20_ff;
+extern cpuop_func op_00b8_20_nf;
+extern cpuop_func op_00b8_20_ff;
+extern cpuop_func op_00b9_20_nf;
+extern cpuop_func op_00b9_20_ff;
+extern cpuop_func op_00d0_20_nf;
+extern cpuop_func op_00d0_20_ff;
+extern cpuop_func op_00e8_20_nf;
+extern cpuop_func op_00e8_20_ff;
+extern cpuop_func op_00f0_20_nf;
+extern cpuop_func op_00f0_20_ff;
+extern cpuop_func op_00f8_20_nf;
+extern cpuop_func op_00f8_20_ff;
+extern cpuop_func op_00f9_20_nf;
+extern cpuop_func op_00f9_20_ff;
+extern cpuop_func op_00fa_20_nf;
+extern cpuop_func op_00fa_20_ff;
+extern cpuop_func op_00fb_20_nf;
+extern cpuop_func op_00fb_20_ff;
+extern cpuop_func op_0100_20_nf;
+extern cpuop_func op_0100_20_ff;
+extern cpuop_func op_0108_20_nf;
+extern cpuop_func op_0108_20_ff;
+extern cpuop_func op_0110_20_nf;
+extern cpuop_func op_0110_20_ff;
+extern cpuop_func op_0118_20_nf;
+extern cpuop_func op_0118_20_ff;
+extern cpuop_func op_0120_20_nf;
+extern cpuop_func op_0120_20_ff;
+extern cpuop_func op_0128_20_nf;
+extern cpuop_func op_0128_20_ff;
+extern cpuop_func op_0130_20_nf;
+extern cpuop_func op_0130_20_ff;
+extern cpuop_func op_0138_20_nf;
+extern cpuop_func op_0138_20_ff;
+extern cpuop_func op_0139_20_nf;
+extern cpuop_func op_0139_20_ff;
+extern cpuop_func op_013a_20_nf;
+extern cpuop_func op_013a_20_ff;
+extern cpuop_func op_013b_20_nf;
+extern cpuop_func op_013b_20_ff;
+extern cpuop_func op_013c_20_nf;
+extern cpuop_func op_013c_20_ff;
+extern cpuop_func op_0140_20_nf;
+extern cpuop_func op_0140_20_ff;
+extern cpuop_func op_0148_20_nf;
+extern cpuop_func op_0148_20_ff;
+extern cpuop_func op_0150_20_nf;
+extern cpuop_func op_0150_20_ff;
+extern cpuop_func op_0158_20_nf;
+extern cpuop_func op_0158_20_ff;
+extern cpuop_func op_0160_20_nf;
+extern cpuop_func op_0160_20_ff;
+extern cpuop_func op_0168_20_nf;
+extern cpuop_func op_0168_20_ff;
+extern cpuop_func op_0170_20_nf;
+extern cpuop_func op_0170_20_ff;
+extern cpuop_func op_0178_20_nf;
+extern cpuop_func op_0178_20_ff;
+extern cpuop_func op_0179_20_nf;
+extern cpuop_func op_0179_20_ff;
+extern cpuop_func op_0180_20_nf;
+extern cpuop_func op_0180_20_ff;
+extern cpuop_func op_0188_20_nf;
+extern cpuop_func op_0188_20_ff;
+extern cpuop_func op_0190_20_nf;
+extern cpuop_func op_0190_20_ff;
+extern cpuop_func op_0198_20_nf;
+extern cpuop_func op_0198_20_ff;
+extern cpuop_func op_01a0_20_nf;
+extern cpuop_func op_01a0_20_ff;
+extern cpuop_func op_01a8_20_nf;
+extern cpuop_func op_01a8_20_ff;
+extern cpuop_func op_01b0_20_nf;
+extern cpuop_func op_01b0_20_ff;
+extern cpuop_func op_01b8_20_nf;
+extern cpuop_func op_01b8_20_ff;
+extern cpuop_func op_01b9_20_nf;
+extern cpuop_func op_01b9_20_ff;
+extern cpuop_func op_01c0_20_nf;
+extern cpuop_func op_01c0_20_ff;
+extern cpuop_func op_01c8_20_nf;
+extern cpuop_func op_01c8_20_ff;
+extern cpuop_func op_01d0_20_nf;
+extern cpuop_func op_01d0_20_ff;
+extern cpuop_func op_01d8_20_nf;
+extern cpuop_func op_01d8_20_ff;
+extern cpuop_func op_01e0_20_nf;
+extern cpuop_func op_01e0_20_ff;
+extern cpuop_func op_01e8_20_nf;
+extern cpuop_func op_01e8_20_ff;
+extern cpuop_func op_01f0_20_nf;
+extern cpuop_func op_01f0_20_ff;
+extern cpuop_func op_01f8_20_nf;
+extern cpuop_func op_01f8_20_ff;
+extern cpuop_func op_01f9_20_nf;
+extern cpuop_func op_01f9_20_ff;
+extern cpuop_func op_0200_20_nf;
+extern cpuop_func op_0200_20_ff;
+extern cpuop_func op_0210_20_nf;
+extern cpuop_func op_0210_20_ff;
+extern cpuop_func op_0218_20_nf;
+extern cpuop_func op_0218_20_ff;
+extern cpuop_func op_0220_20_nf;
+extern cpuop_func op_0220_20_ff;
+extern cpuop_func op_0228_20_nf;
+extern cpuop_func op_0228_20_ff;
+extern cpuop_func op_0230_20_nf;
+extern cpuop_func op_0230_20_ff;
+extern cpuop_func op_0238_20_nf;
+extern cpuop_func op_0238_20_ff;
+extern cpuop_func op_0239_20_nf;
+extern cpuop_func op_0239_20_ff;
+extern cpuop_func op_023c_20_nf;
+extern cpuop_func op_023c_20_ff;
+extern cpuop_func op_0240_20_nf;
+extern cpuop_func op_0240_20_ff;
+extern cpuop_func op_0250_20_nf;
+extern cpuop_func op_0250_20_ff;
+extern cpuop_func op_0258_20_nf;
+extern cpuop_func op_0258_20_ff;
+extern cpuop_func op_0260_20_nf;
+extern cpuop_func op_0260_20_ff;
+extern cpuop_func op_0268_20_nf;
+extern cpuop_func op_0268_20_ff;
+extern cpuop_func op_0270_20_nf;
+extern cpuop_func op_0270_20_ff;
+extern cpuop_func op_0278_20_nf;
+extern cpuop_func op_0278_20_ff;
+extern cpuop_func op_0279_20_nf;
+extern cpuop_func op_0279_20_ff;
+extern cpuop_func op_027c_20_nf;
+extern cpuop_func op_027c_20_ff;
+extern cpuop_func op_0280_20_nf;
+extern cpuop_func op_0280_20_ff;
+extern cpuop_func op_0290_20_nf;
+extern cpuop_func op_0290_20_ff;
+extern cpuop_func op_0298_20_nf;
+extern cpuop_func op_0298_20_ff;
+extern cpuop_func op_02a0_20_nf;
+extern cpuop_func op_02a0_20_ff;
+extern cpuop_func op_02a8_20_nf;
+extern cpuop_func op_02a8_20_ff;
+extern cpuop_func op_02b0_20_nf;
+extern cpuop_func op_02b0_20_ff;
+extern cpuop_func op_02b8_20_nf;
+extern cpuop_func op_02b8_20_ff;
+extern cpuop_func op_02b9_20_nf;
+extern cpuop_func op_02b9_20_ff;
+extern cpuop_func op_02d0_20_nf;
+extern cpuop_func op_02d0_20_ff;
+extern cpuop_func op_02e8_20_nf;
+extern cpuop_func op_02e8_20_ff;
+extern cpuop_func op_02f0_20_nf;
+extern cpuop_func op_02f0_20_ff;
+extern cpuop_func op_02f8_20_nf;
+extern cpuop_func op_02f8_20_ff;
+extern cpuop_func op_02f9_20_nf;
+extern cpuop_func op_02f9_20_ff;
+extern cpuop_func op_02fa_20_nf;
+extern cpuop_func op_02fa_20_ff;
+extern cpuop_func op_02fb_20_nf;
+extern cpuop_func op_02fb_20_ff;
+extern cpuop_func op_0400_20_nf;
+extern cpuop_func op_0400_20_ff;
+extern cpuop_func op_0410_20_nf;
+extern cpuop_func op_0410_20_ff;
+extern cpuop_func op_0418_20_nf;
+extern cpuop_func op_0418_20_ff;
+extern cpuop_func op_0420_20_nf;
+extern cpuop_func op_0420_20_ff;
+extern cpuop_func op_0428_20_nf;
+extern cpuop_func op_0428_20_ff;
+extern cpuop_func op_0430_20_nf;
+extern cpuop_func op_0430_20_ff;
+extern cpuop_func op_0438_20_nf;
+extern cpuop_func op_0438_20_ff;
+extern cpuop_func op_0439_20_nf;
+extern cpuop_func op_0439_20_ff;
+extern cpuop_func op_0440_20_nf;
+extern cpuop_func op_0440_20_ff;
+extern cpuop_func op_0450_20_nf;
+extern cpuop_func op_0450_20_ff;
+extern cpuop_func op_0458_20_nf;
+extern cpuop_func op_0458_20_ff;
+extern cpuop_func op_0460_20_nf;
+extern cpuop_func op_0460_20_ff;
+extern cpuop_func op_0468_20_nf;
+extern cpuop_func op_0468_20_ff;
+extern cpuop_func op_0470_20_nf;
+extern cpuop_func op_0470_20_ff;
+extern cpuop_func op_0478_20_nf;
+extern cpuop_func op_0478_20_ff;
+extern cpuop_func op_0479_20_nf;
+extern cpuop_func op_0479_20_ff;
+extern cpuop_func op_0480_20_nf;
+extern cpuop_func op_0480_20_ff;
+extern cpuop_func op_0490_20_nf;
+extern cpuop_func op_0490_20_ff;
+extern cpuop_func op_0498_20_nf;
+extern cpuop_func op_0498_20_ff;
+extern cpuop_func op_04a0_20_nf;
+extern cpuop_func op_04a0_20_ff;
+extern cpuop_func op_04a8_20_nf;
+extern cpuop_func op_04a8_20_ff;
+extern cpuop_func op_04b0_20_nf;
+extern cpuop_func op_04b0_20_ff;
+extern cpuop_func op_04b8_20_nf;
+extern cpuop_func op_04b8_20_ff;
+extern cpuop_func op_04b9_20_nf;
+extern cpuop_func op_04b9_20_ff;
+extern cpuop_func op_04d0_20_nf;
+extern cpuop_func op_04d0_20_ff;
+extern cpuop_func op_04e8_20_nf;
+extern cpuop_func op_04e8_20_ff;
+extern cpuop_func op_04f0_20_nf;
+extern cpuop_func op_04f0_20_ff;
+extern cpuop_func op_04f8_20_nf;
+extern cpuop_func op_04f8_20_ff;
+extern cpuop_func op_04f9_20_nf;
+extern cpuop_func op_04f9_20_ff;
+extern cpuop_func op_04fa_20_nf;
+extern cpuop_func op_04fa_20_ff;
+extern cpuop_func op_04fb_20_nf;
+extern cpuop_func op_04fb_20_ff;
+extern cpuop_func op_0600_20_nf;
+extern cpuop_func op_0600_20_ff;
+extern cpuop_func op_0610_20_nf;
+extern cpuop_func op_0610_20_ff;
+extern cpuop_func op_0618_20_nf;
+extern cpuop_func op_0618_20_ff;
+extern cpuop_func op_0620_20_nf;
+extern cpuop_func op_0620_20_ff;
+extern cpuop_func op_0628_20_nf;
+extern cpuop_func op_0628_20_ff;
+extern cpuop_func op_0630_20_nf;
+extern cpuop_func op_0630_20_ff;
+extern cpuop_func op_0638_20_nf;
+extern cpuop_func op_0638_20_ff;
+extern cpuop_func op_0639_20_nf;
+extern cpuop_func op_0639_20_ff;
+extern cpuop_func op_0640_20_nf;
+extern cpuop_func op_0640_20_ff;
+extern cpuop_func op_0650_20_nf;
+extern cpuop_func op_0650_20_ff;
+extern cpuop_func op_0658_20_nf;
+extern cpuop_func op_0658_20_ff;
+extern cpuop_func op_0660_20_nf;
+extern cpuop_func op_0660_20_ff;
+extern cpuop_func op_0668_20_nf;
+extern cpuop_func op_0668_20_ff;
+extern cpuop_func op_0670_20_nf;
+extern cpuop_func op_0670_20_ff;
+extern cpuop_func op_0678_20_nf;
+extern cpuop_func op_0678_20_ff;
+extern cpuop_func op_0679_20_nf;
+extern cpuop_func op_0679_20_ff;
+extern cpuop_func op_0680_20_nf;
+extern cpuop_func op_0680_20_ff;
+extern cpuop_func op_0690_20_nf;
+extern cpuop_func op_0690_20_ff;
+extern cpuop_func op_0698_20_nf;
+extern cpuop_func op_0698_20_ff;
+extern cpuop_func op_06a0_20_nf;
+extern cpuop_func op_06a0_20_ff;
+extern cpuop_func op_06a8_20_nf;
+extern cpuop_func op_06a8_20_ff;
+extern cpuop_func op_06b0_20_nf;
+extern cpuop_func op_06b0_20_ff;
+extern cpuop_func op_06b8_20_nf;
+extern cpuop_func op_06b8_20_ff;
+extern cpuop_func op_06b9_20_nf;
+extern cpuop_func op_06b9_20_ff;
+extern cpuop_func op_06c0_20_nf;
+extern cpuop_func op_06c0_20_ff;
+extern cpuop_func op_06c8_20_nf;
+extern cpuop_func op_06c8_20_ff;
+extern cpuop_func op_06d0_20_nf;
+extern cpuop_func op_06d0_20_ff;
+extern cpuop_func op_06e8_20_nf;
+extern cpuop_func op_06e8_20_ff;
+extern cpuop_func op_06f0_20_nf;
+extern cpuop_func op_06f0_20_ff;
+extern cpuop_func op_06f8_20_nf;
+extern cpuop_func op_06f8_20_ff;
+extern cpuop_func op_06f9_20_nf;
+extern cpuop_func op_06f9_20_ff;
+extern cpuop_func op_06fa_20_nf;
+extern cpuop_func op_06fa_20_ff;
+extern cpuop_func op_06fb_20_nf;
+extern cpuop_func op_06fb_20_ff;
+extern cpuop_func op_0800_20_nf;
+extern cpuop_func op_0800_20_ff;
+extern cpuop_func op_0810_20_nf;
+extern cpuop_func op_0810_20_ff;
+extern cpuop_func op_0818_20_nf;
+extern cpuop_func op_0818_20_ff;
+extern cpuop_func op_0820_20_nf;
+extern cpuop_func op_0820_20_ff;
+extern cpuop_func op_0828_20_nf;
+extern cpuop_func op_0828_20_ff;
+extern cpuop_func op_0830_20_nf;
+extern cpuop_func op_0830_20_ff;
+extern cpuop_func op_0838_20_nf;
+extern cpuop_func op_0838_20_ff;
+extern cpuop_func op_0839_20_nf;
+extern cpuop_func op_0839_20_ff;
+extern cpuop_func op_083a_20_nf;
+extern cpuop_func op_083a_20_ff;
+extern cpuop_func op_083b_20_nf;
+extern cpuop_func op_083b_20_ff;
+extern cpuop_func op_0840_20_nf;
+extern cpuop_func op_0840_20_ff;
+extern cpuop_func op_0850_20_nf;
+extern cpuop_func op_0850_20_ff;
+extern cpuop_func op_0858_20_nf;
+extern cpuop_func op_0858_20_ff;
+extern cpuop_func op_0860_20_nf;
+extern cpuop_func op_0860_20_ff;
+extern cpuop_func op_0868_20_nf;
+extern cpuop_func op_0868_20_ff;
+extern cpuop_func op_0870_20_nf;
+extern cpuop_func op_0870_20_ff;
+extern cpuop_func op_0878_20_nf;
+extern cpuop_func op_0878_20_ff;
+extern cpuop_func op_0879_20_nf;
+extern cpuop_func op_0879_20_ff;
+extern cpuop_func op_0880_20_nf;
+extern cpuop_func op_0880_20_ff;
+extern cpuop_func op_0890_20_nf;
+extern cpuop_func op_0890_20_ff;
+extern cpuop_func op_0898_20_nf;
+extern cpuop_func op_0898_20_ff;
+extern cpuop_func op_08a0_20_nf;
+extern cpuop_func op_08a0_20_ff;
+extern cpuop_func op_08a8_20_nf;
+extern cpuop_func op_08a8_20_ff;
+extern cpuop_func op_08b0_20_nf;
+extern cpuop_func op_08b0_20_ff;
+extern cpuop_func op_08b8_20_nf;
+extern cpuop_func op_08b8_20_ff;
+extern cpuop_func op_08b9_20_nf;
+extern cpuop_func op_08b9_20_ff;
+extern cpuop_func op_08c0_20_nf;
+extern cpuop_func op_08c0_20_ff;
+extern cpuop_func op_08d0_20_nf;
+extern cpuop_func op_08d0_20_ff;
+extern cpuop_func op_08d8_20_nf;
+extern cpuop_func op_08d8_20_ff;
+extern cpuop_func op_08e0_20_nf;
+extern cpuop_func op_08e0_20_ff;
+extern cpuop_func op_08e8_20_nf;
+extern cpuop_func op_08e8_20_ff;
+extern cpuop_func op_08f0_20_nf;
+extern cpuop_func op_08f0_20_ff;
+extern cpuop_func op_08f8_20_nf;
+extern cpuop_func op_08f8_20_ff;
+extern cpuop_func op_08f9_20_nf;
+extern cpuop_func op_08f9_20_ff;
+extern cpuop_func op_0a00_20_nf;
+extern cpuop_func op_0a00_20_ff;
+extern cpuop_func op_0a10_20_nf;
+extern cpuop_func op_0a10_20_ff;
+extern cpuop_func op_0a18_20_nf;
+extern cpuop_func op_0a18_20_ff;
+extern cpuop_func op_0a20_20_nf;
+extern cpuop_func op_0a20_20_ff;
+extern cpuop_func op_0a28_20_nf;
+extern cpuop_func op_0a28_20_ff;
+extern cpuop_func op_0a30_20_nf;
+extern cpuop_func op_0a30_20_ff;
+extern cpuop_func op_0a38_20_nf;
+extern cpuop_func op_0a38_20_ff;
+extern cpuop_func op_0a39_20_nf;
+extern cpuop_func op_0a39_20_ff;
+extern cpuop_func op_0a3c_20_nf;
+extern cpuop_func op_0a3c_20_ff;
+extern cpuop_func op_0a40_20_nf;
+extern cpuop_func op_0a40_20_ff;
+extern cpuop_func op_0a50_20_nf;
+extern cpuop_func op_0a50_20_ff;
+extern cpuop_func op_0a58_20_nf;
+extern cpuop_func op_0a58_20_ff;
+extern cpuop_func op_0a60_20_nf;
+extern cpuop_func op_0a60_20_ff;
+extern cpuop_func op_0a68_20_nf;
+extern cpuop_func op_0a68_20_ff;
+extern cpuop_func op_0a70_20_nf;
+extern cpuop_func op_0a70_20_ff;
+extern cpuop_func op_0a78_20_nf;
+extern cpuop_func op_0a78_20_ff;
+extern cpuop_func op_0a79_20_nf;
+extern cpuop_func op_0a79_20_ff;
+extern cpuop_func op_0a7c_20_nf;
+extern cpuop_func op_0a7c_20_ff;
+extern cpuop_func op_0a80_20_nf;
+extern cpuop_func op_0a80_20_ff;
+extern cpuop_func op_0a90_20_nf;
+extern cpuop_func op_0a90_20_ff;
+extern cpuop_func op_0a98_20_nf;
+extern cpuop_func op_0a98_20_ff;
+extern cpuop_func op_0aa0_20_nf;
+extern cpuop_func op_0aa0_20_ff;
+extern cpuop_func op_0aa8_20_nf;
+extern cpuop_func op_0aa8_20_ff;
+extern cpuop_func op_0ab0_20_nf;
+extern cpuop_func op_0ab0_20_ff;
+extern cpuop_func op_0ab8_20_nf;
+extern cpuop_func op_0ab8_20_ff;
+extern cpuop_func op_0ab9_20_nf;
+extern cpuop_func op_0ab9_20_ff;
+extern cpuop_func op_0ad0_20_nf;
+extern cpuop_func op_0ad0_20_ff;
+extern cpuop_func op_0ad8_20_nf;
+extern cpuop_func op_0ad8_20_ff;
+extern cpuop_func op_0ae0_20_nf;
+extern cpuop_func op_0ae0_20_ff;
+extern cpuop_func op_0ae8_20_nf;
+extern cpuop_func op_0ae8_20_ff;
+extern cpuop_func op_0af0_20_nf;
+extern cpuop_func op_0af0_20_ff;
+extern cpuop_func op_0af8_20_nf;
+extern cpuop_func op_0af8_20_ff;
+extern cpuop_func op_0af9_20_nf;
+extern cpuop_func op_0af9_20_ff;
+extern cpuop_func op_0c00_20_nf;
+extern cpuop_func op_0c00_20_ff;
+extern cpuop_func op_0c10_20_nf;
+extern cpuop_func op_0c10_20_ff;
+extern cpuop_func op_0c18_20_nf;
+extern cpuop_func op_0c18_20_ff;
+extern cpuop_func op_0c20_20_nf;
+extern cpuop_func op_0c20_20_ff;
+extern cpuop_func op_0c28_20_nf;
+extern cpuop_func op_0c28_20_ff;
+extern cpuop_func op_0c30_20_nf;
+extern cpuop_func op_0c30_20_ff;
+extern cpuop_func op_0c38_20_nf;
+extern cpuop_func op_0c38_20_ff;
+extern cpuop_func op_0c39_20_nf;
+extern cpuop_func op_0c39_20_ff;
+extern cpuop_func op_0c3a_20_nf;
+extern cpuop_func op_0c3a_20_ff;
+extern cpuop_func op_0c3b_20_nf;
+extern cpuop_func op_0c3b_20_ff;
+extern cpuop_func op_0c40_20_nf;
+extern cpuop_func op_0c40_20_ff;
+extern cpuop_func op_0c50_20_nf;
+extern cpuop_func op_0c50_20_ff;
+extern cpuop_func op_0c58_20_nf;
+extern cpuop_func op_0c58_20_ff;
+extern cpuop_func op_0c60_20_nf;
+extern cpuop_func op_0c60_20_ff;
+extern cpuop_func op_0c68_20_nf;
+extern cpuop_func op_0c68_20_ff;
+extern cpuop_func op_0c70_20_nf;
+extern cpuop_func op_0c70_20_ff;
+extern cpuop_func op_0c78_20_nf;
+extern cpuop_func op_0c78_20_ff;
+extern cpuop_func op_0c79_20_nf;
+extern cpuop_func op_0c79_20_ff;
+extern cpuop_func op_0c7a_20_nf;
+extern cpuop_func op_0c7a_20_ff;
+extern cpuop_func op_0c7b_20_nf;
+extern cpuop_func op_0c7b_20_ff;
+extern cpuop_func op_0c80_20_nf;
+extern cpuop_func op_0c80_20_ff;
+extern cpuop_func op_0c90_20_nf;
+extern cpuop_func op_0c90_20_ff;
+extern cpuop_func op_0c98_20_nf;
+extern cpuop_func op_0c98_20_ff;
+extern cpuop_func op_0ca0_20_nf;
+extern cpuop_func op_0ca0_20_ff;
+extern cpuop_func op_0ca8_20_nf;
+extern cpuop_func op_0ca8_20_ff;
+extern cpuop_func op_0cb0_20_nf;
+extern cpuop_func op_0cb0_20_ff;
+extern cpuop_func op_0cb8_20_nf;
+extern cpuop_func op_0cb8_20_ff;
+extern cpuop_func op_0cb9_20_nf;
+extern cpuop_func op_0cb9_20_ff;
+extern cpuop_func op_0cba_20_nf;
+extern cpuop_func op_0cba_20_ff;
+extern cpuop_func op_0cbb_20_nf;
+extern cpuop_func op_0cbb_20_ff;
+extern cpuop_func op_0cd0_20_nf;
+extern cpuop_func op_0cd0_20_ff;
+extern cpuop_func op_0cd8_20_nf;
+extern cpuop_func op_0cd8_20_ff;
+extern cpuop_func op_0ce0_20_nf;
+extern cpuop_func op_0ce0_20_ff;
+extern cpuop_func op_0ce8_20_nf;
+extern cpuop_func op_0ce8_20_ff;
+extern cpuop_func op_0cf0_20_nf;
+extern cpuop_func op_0cf0_20_ff;
+extern cpuop_func op_0cf8_20_nf;
+extern cpuop_func op_0cf8_20_ff;
+extern cpuop_func op_0cf9_20_nf;
+extern cpuop_func op_0cf9_20_ff;
+extern cpuop_func op_0cfc_20_nf;
+extern cpuop_func op_0cfc_20_ff;
+extern cpuop_func op_0e10_20_nf;
+extern cpuop_func op_0e10_20_ff;
+extern cpuop_func op_0e18_20_nf;
+extern cpuop_func op_0e18_20_ff;
+extern cpuop_func op_0e20_20_nf;
+extern cpuop_func op_0e20_20_ff;
+extern cpuop_func op_0e28_20_nf;
+extern cpuop_func op_0e28_20_ff;
+extern cpuop_func op_0e30_20_nf;
+extern cpuop_func op_0e30_20_ff;
+extern cpuop_func op_0e38_20_nf;
+extern cpuop_func op_0e38_20_ff;
+extern cpuop_func op_0e39_20_nf;
+extern cpuop_func op_0e39_20_ff;
+extern cpuop_func op_0e50_20_nf;
+extern cpuop_func op_0e50_20_ff;
+extern cpuop_func op_0e58_20_nf;
+extern cpuop_func op_0e58_20_ff;
+extern cpuop_func op_0e60_20_nf;
+extern cpuop_func op_0e60_20_ff;
+extern cpuop_func op_0e68_20_nf;
+extern cpuop_func op_0e68_20_ff;
+extern cpuop_func op_0e70_20_nf;
+extern cpuop_func op_0e70_20_ff;
+extern cpuop_func op_0e78_20_nf;
+extern cpuop_func op_0e78_20_ff;
+extern cpuop_func op_0e79_20_nf;
+extern cpuop_func op_0e79_20_ff;
+extern cpuop_func op_0e90_20_nf;
+extern cpuop_func op_0e90_20_ff;
+extern cpuop_func op_0e98_20_nf;
+extern cpuop_func op_0e98_20_ff;
+extern cpuop_func op_0ea0_20_nf;
+extern cpuop_func op_0ea0_20_ff;
+extern cpuop_func op_0ea8_20_nf;
+extern cpuop_func op_0ea8_20_ff;
+extern cpuop_func op_0eb0_20_nf;
+extern cpuop_func op_0eb0_20_ff;
+extern cpuop_func op_0eb8_20_nf;
+extern cpuop_func op_0eb8_20_ff;
+extern cpuop_func op_0eb9_20_nf;
+extern cpuop_func op_0eb9_20_ff;
+extern cpuop_func op_0ed0_20_nf;
+extern cpuop_func op_0ed0_20_ff;
+extern cpuop_func op_0ed8_20_nf;
+extern cpuop_func op_0ed8_20_ff;
+extern cpuop_func op_0ee0_20_nf;
+extern cpuop_func op_0ee0_20_ff;
+extern cpuop_func op_0ee8_20_nf;
+extern cpuop_func op_0ee8_20_ff;
+extern cpuop_func op_0ef0_20_nf;
+extern cpuop_func op_0ef0_20_ff;
+extern cpuop_func op_0ef8_20_nf;
+extern cpuop_func op_0ef8_20_ff;
+extern cpuop_func op_0ef9_20_nf;
+extern cpuop_func op_0ef9_20_ff;
+extern cpuop_func op_0efc_20_nf;
+extern cpuop_func op_0efc_20_ff;
+extern cpuop_func op_1000_20_nf;
+extern cpuop_func op_1000_20_ff;
+extern cpuop_func op_1010_20_nf;
+extern cpuop_func op_1010_20_ff;
+extern cpuop_func op_1018_20_nf;
+extern cpuop_func op_1018_20_ff;
+extern cpuop_func op_1020_20_nf;
+extern cpuop_func op_1020_20_ff;
+extern cpuop_func op_1028_20_nf;
+extern cpuop_func op_1028_20_ff;
+extern cpuop_func op_1030_20_nf;
+extern cpuop_func op_1030_20_ff;
+extern cpuop_func op_1038_20_nf;
+extern cpuop_func op_1038_20_ff;
+extern cpuop_func op_1039_20_nf;
+extern cpuop_func op_1039_20_ff;
+extern cpuop_func op_103a_20_nf;
+extern cpuop_func op_103a_20_ff;
+extern cpuop_func op_103b_20_nf;
+extern cpuop_func op_103b_20_ff;
+extern cpuop_func op_103c_20_nf;
+extern cpuop_func op_103c_20_ff;
+extern cpuop_func op_1080_20_nf;
+extern cpuop_func op_1080_20_ff;
+extern cpuop_func op_1090_20_nf;
+extern cpuop_func op_1090_20_ff;
+extern cpuop_func op_1098_20_nf;
+extern cpuop_func op_1098_20_ff;
+extern cpuop_func op_10a0_20_nf;
+extern cpuop_func op_10a0_20_ff;
+extern cpuop_func op_10a8_20_nf;
+extern cpuop_func op_10a8_20_ff;
+extern cpuop_func op_10b0_20_nf;
+extern cpuop_func op_10b0_20_ff;
+extern cpuop_func op_10b8_20_nf;
+extern cpuop_func op_10b8_20_ff;
+extern cpuop_func op_10b9_20_nf;
+extern cpuop_func op_10b9_20_ff;
+extern cpuop_func op_10ba_20_nf;
+extern cpuop_func op_10ba_20_ff;
+extern cpuop_func op_10bb_20_nf;
+extern cpuop_func op_10bb_20_ff;
+extern cpuop_func op_10bc_20_nf;
+extern cpuop_func op_10bc_20_ff;
+extern cpuop_func op_10c0_20_nf;
+extern cpuop_func op_10c0_20_ff;
+extern cpuop_func op_10d0_20_nf;
+extern cpuop_func op_10d0_20_ff;
+extern cpuop_func op_10d8_20_nf;
+extern cpuop_func op_10d8_20_ff;
+extern cpuop_func op_10e0_20_nf;
+extern cpuop_func op_10e0_20_ff;
+extern cpuop_func op_10e8_20_nf;
+extern cpuop_func op_10e8_20_ff;
+extern cpuop_func op_10f0_20_nf;
+extern cpuop_func op_10f0_20_ff;
+extern cpuop_func op_10f8_20_nf;
+extern cpuop_func op_10f8_20_ff;
+extern cpuop_func op_10f9_20_nf;
+extern cpuop_func op_10f9_20_ff;
+extern cpuop_func op_10fa_20_nf;
+extern cpuop_func op_10fa_20_ff;
+extern cpuop_func op_10fb_20_nf;
+extern cpuop_func op_10fb_20_ff;
+extern cpuop_func op_10fc_20_nf;
+extern cpuop_func op_10fc_20_ff;
+extern cpuop_func op_1100_20_nf;
+extern cpuop_func op_1100_20_ff;
+extern cpuop_func op_1110_20_nf;
+extern cpuop_func op_1110_20_ff;
+extern cpuop_func op_1118_20_nf;
+extern cpuop_func op_1118_20_ff;
+extern cpuop_func op_1120_20_nf;
+extern cpuop_func op_1120_20_ff;
+extern cpuop_func op_1128_20_nf;
+extern cpuop_func op_1128_20_ff;
+extern cpuop_func op_1130_20_nf;
+extern cpuop_func op_1130_20_ff;
+extern cpuop_func op_1138_20_nf;
+extern cpuop_func op_1138_20_ff;
+extern cpuop_func op_1139_20_nf;
+extern cpuop_func op_1139_20_ff;
+extern cpuop_func op_113a_20_nf;
+extern cpuop_func op_113a_20_ff;
+extern cpuop_func op_113b_20_nf;
+extern cpuop_func op_113b_20_ff;
+extern cpuop_func op_113c_20_nf;
+extern cpuop_func op_113c_20_ff;
+extern cpuop_func op_1140_20_nf;
+extern cpuop_func op_1140_20_ff;
+extern cpuop_func op_1150_20_nf;
+extern cpuop_func op_1150_20_ff;
+extern cpuop_func op_1158_20_nf;
+extern cpuop_func op_1158_20_ff;
+extern cpuop_func op_1160_20_nf;
+extern cpuop_func op_1160_20_ff;
+extern cpuop_func op_1168_20_nf;
+extern cpuop_func op_1168_20_ff;
+extern cpuop_func op_1170_20_nf;
+extern cpuop_func op_1170_20_ff;
+extern cpuop_func op_1178_20_nf;
+extern cpuop_func op_1178_20_ff;
+extern cpuop_func op_1179_20_nf;
+extern cpuop_func op_1179_20_ff;
+extern cpuop_func op_117a_20_nf;
+extern cpuop_func op_117a_20_ff;
+extern cpuop_func op_117b_20_nf;
+extern cpuop_func op_117b_20_ff;
+extern cpuop_func op_117c_20_nf;
+extern cpuop_func op_117c_20_ff;
+extern cpuop_func op_1180_20_nf;
+extern cpuop_func op_1180_20_ff;
+extern cpuop_func op_1190_20_nf;
+extern cpuop_func op_1190_20_ff;
+extern cpuop_func op_1198_20_nf;
+extern cpuop_func op_1198_20_ff;
+extern cpuop_func op_11a0_20_nf;
+extern cpuop_func op_11a0_20_ff;
+extern cpuop_func op_11a8_20_nf;
+extern cpuop_func op_11a8_20_ff;
+extern cpuop_func op_11b0_20_nf;
+extern cpuop_func op_11b0_20_ff;
+extern cpuop_func op_11b8_20_nf;
+extern cpuop_func op_11b8_20_ff;
+extern cpuop_func op_11b9_20_nf;
+extern cpuop_func op_11b9_20_ff;
+extern cpuop_func op_11ba_20_nf;
+extern cpuop_func op_11ba_20_ff;
+extern cpuop_func op_11bb_20_nf;
+extern cpuop_func op_11bb_20_ff;
+extern cpuop_func op_11bc_20_nf;
+extern cpuop_func op_11bc_20_ff;
+extern cpuop_func op_11c0_20_nf;
+extern cpuop_func op_11c0_20_ff;
+extern cpuop_func op_11d0_20_nf;
+extern cpuop_func op_11d0_20_ff;
+extern cpuop_func op_11d8_20_nf;
+extern cpuop_func op_11d8_20_ff;
+extern cpuop_func op_11e0_20_nf;
+extern cpuop_func op_11e0_20_ff;
+extern cpuop_func op_11e8_20_nf;
+extern cpuop_func op_11e8_20_ff;
+extern cpuop_func op_11f0_20_nf;
+extern cpuop_func op_11f0_20_ff;
+extern cpuop_func op_11f8_20_nf;
+extern cpuop_func op_11f8_20_ff;
+extern cpuop_func op_11f9_20_nf;
+extern cpuop_func op_11f9_20_ff;
+extern cpuop_func op_11fa_20_nf;
+extern cpuop_func op_11fa_20_ff;
+extern cpuop_func op_11fb_20_nf;
+extern cpuop_func op_11fb_20_ff;
+extern cpuop_func op_11fc_20_nf;
+extern cpuop_func op_11fc_20_ff;
+extern cpuop_func op_13c0_20_nf;
+extern cpuop_func op_13c0_20_ff;
+extern cpuop_func op_13d0_20_nf;
+extern cpuop_func op_13d0_20_ff;
+extern cpuop_func op_13d8_20_nf;
+extern cpuop_func op_13d8_20_ff;
+extern cpuop_func op_13e0_20_nf;
+extern cpuop_func op_13e0_20_ff;
+extern cpuop_func op_13e8_20_nf;
+extern cpuop_func op_13e8_20_ff;
+extern cpuop_func op_13f0_20_nf;
+extern cpuop_func op_13f0_20_ff;
+extern cpuop_func op_13f8_20_nf;
+extern cpuop_func op_13f8_20_ff;
+extern cpuop_func op_13f9_20_nf;
+extern cpuop_func op_13f9_20_ff;
+extern cpuop_func op_13fa_20_nf;
+extern cpuop_func op_13fa_20_ff;
+extern cpuop_func op_13fb_20_nf;
+extern cpuop_func op_13fb_20_ff;
+extern cpuop_func op_13fc_20_nf;
+extern cpuop_func op_13fc_20_ff;
+extern cpuop_func op_2000_20_nf;
+extern cpuop_func op_2000_20_ff;
+extern cpuop_func op_2008_20_nf;
+extern cpuop_func op_2008_20_ff;
+extern cpuop_func op_2010_20_nf;
+extern cpuop_func op_2010_20_ff;
+extern cpuop_func op_2018_20_nf;
+extern cpuop_func op_2018_20_ff;
+extern cpuop_func op_2020_20_nf;
+extern cpuop_func op_2020_20_ff;
+extern cpuop_func op_2028_20_nf;
+extern cpuop_func op_2028_20_ff;
+extern cpuop_func op_2030_20_nf;
+extern cpuop_func op_2030_20_ff;
+extern cpuop_func op_2038_20_nf;
+extern cpuop_func op_2038_20_ff;
+extern cpuop_func op_2039_20_nf;
+extern cpuop_func op_2039_20_ff;
+extern cpuop_func op_203a_20_nf;
+extern cpuop_func op_203a_20_ff;
+extern cpuop_func op_203b_20_nf;
+extern cpuop_func op_203b_20_ff;
+extern cpuop_func op_203c_20_nf;
+extern cpuop_func op_203c_20_ff;
+extern cpuop_func op_2040_20_nf;
+extern cpuop_func op_2040_20_ff;
+extern cpuop_func op_2048_20_nf;
+extern cpuop_func op_2048_20_ff;
+extern cpuop_func op_2050_20_nf;
+extern cpuop_func op_2050_20_ff;
+extern cpuop_func op_2058_20_nf;
+extern cpuop_func op_2058_20_ff;
+extern cpuop_func op_2060_20_nf;
+extern cpuop_func op_2060_20_ff;
+extern cpuop_func op_2068_20_nf;
+extern cpuop_func op_2068_20_ff;
+extern cpuop_func op_2070_20_nf;
+extern cpuop_func op_2070_20_ff;
+extern cpuop_func op_2078_20_nf;
+extern cpuop_func op_2078_20_ff;
+extern cpuop_func op_2079_20_nf;
+extern cpuop_func op_2079_20_ff;
+extern cpuop_func op_207a_20_nf;
+extern cpuop_func op_207a_20_ff;
+extern cpuop_func op_207b_20_nf;
+extern cpuop_func op_207b_20_ff;
+extern cpuop_func op_207c_20_nf;
+extern cpuop_func op_207c_20_ff;
+extern cpuop_func op_2080_20_nf;
+extern cpuop_func op_2080_20_ff;
+extern cpuop_func op_2088_20_nf;
+extern cpuop_func op_2088_20_ff;
+extern cpuop_func op_2090_20_nf;
+extern cpuop_func op_2090_20_ff;
+extern cpuop_func op_2098_20_nf;
+extern cpuop_func op_2098_20_ff;
+extern cpuop_func op_20a0_20_nf;
+extern cpuop_func op_20a0_20_ff;
+extern cpuop_func op_20a8_20_nf;
+extern cpuop_func op_20a8_20_ff;
+extern cpuop_func op_20b0_20_nf;
+extern cpuop_func op_20b0_20_ff;
+extern cpuop_func op_20b8_20_nf;
+extern cpuop_func op_20b8_20_ff;
+extern cpuop_func op_20b9_20_nf;
+extern cpuop_func op_20b9_20_ff;
+extern cpuop_func op_20ba_20_nf;
+extern cpuop_func op_20ba_20_ff;
+extern cpuop_func op_20bb_20_nf;
+extern cpuop_func op_20bb_20_ff;
+extern cpuop_func op_20bc_20_nf;
+extern cpuop_func op_20bc_20_ff;
+extern cpuop_func op_20c0_20_nf;
+extern cpuop_func op_20c0_20_ff;
+extern cpuop_func op_20c8_20_nf;
+extern cpuop_func op_20c8_20_ff;
+extern cpuop_func op_20d0_20_nf;
+extern cpuop_func op_20d0_20_ff;
+extern cpuop_func op_20d8_20_nf;
+extern cpuop_func op_20d8_20_ff;
+extern cpuop_func op_20e0_20_nf;
+extern cpuop_func op_20e0_20_ff;
+extern cpuop_func op_20e8_20_nf;
+extern cpuop_func op_20e8_20_ff;
+extern cpuop_func op_20f0_20_nf;
+extern cpuop_func op_20f0_20_ff;
+extern cpuop_func op_20f8_20_nf;
+extern cpuop_func op_20f8_20_ff;
+extern cpuop_func op_20f9_20_nf;
+extern cpuop_func op_20f9_20_ff;
+extern cpuop_func op_20fa_20_nf;
+extern cpuop_func op_20fa_20_ff;
+extern cpuop_func op_20fb_20_nf;
+extern cpuop_func op_20fb_20_ff;
+extern cpuop_func op_20fc_20_nf;
+extern cpuop_func op_20fc_20_ff;
+extern cpuop_func op_2100_20_nf;
+extern cpuop_func op_2100_20_ff;
+extern cpuop_func op_2108_20_nf;
+extern cpuop_func op_2108_20_ff;
+extern cpuop_func op_2110_20_nf;
+extern cpuop_func op_2110_20_ff;
+extern cpuop_func op_2118_20_nf;
+extern cpuop_func op_2118_20_ff;
+extern cpuop_func op_2120_20_nf;
+extern cpuop_func op_2120_20_ff;
+extern cpuop_func op_2128_20_nf;
+extern cpuop_func op_2128_20_ff;
+extern cpuop_func op_2130_20_nf;
+extern cpuop_func op_2130_20_ff;
+extern cpuop_func op_2138_20_nf;
+extern cpuop_func op_2138_20_ff;
+extern cpuop_func op_2139_20_nf;
+extern cpuop_func op_2139_20_ff;
+extern cpuop_func op_213a_20_nf;
+extern cpuop_func op_213a_20_ff;
+extern cpuop_func op_213b_20_nf;
+extern cpuop_func op_213b_20_ff;
+extern cpuop_func op_213c_20_nf;
+extern cpuop_func op_213c_20_ff;
+extern cpuop_func op_2140_20_nf;
+extern cpuop_func op_2140_20_ff;
+extern cpuop_func op_2148_20_nf;
+extern cpuop_func op_2148_20_ff;
+extern cpuop_func op_2150_20_nf;
+extern cpuop_func op_2150_20_ff;
+extern cpuop_func op_2158_20_nf;
+extern cpuop_func op_2158_20_ff;
+extern cpuop_func op_2160_20_nf;
+extern cpuop_func op_2160_20_ff;
+extern cpuop_func op_2168_20_nf;
+extern cpuop_func op_2168_20_ff;
+extern cpuop_func op_2170_20_nf;
+extern cpuop_func op_2170_20_ff;
+extern cpuop_func op_2178_20_nf;
+extern cpuop_func op_2178_20_ff;
+extern cpuop_func op_2179_20_nf;
+extern cpuop_func op_2179_20_ff;
+extern cpuop_func op_217a_20_nf;
+extern cpuop_func op_217a_20_ff;
+extern cpuop_func op_217b_20_nf;
+extern cpuop_func op_217b_20_ff;
+extern cpuop_func op_217c_20_nf;
+extern cpuop_func op_217c_20_ff;
+extern cpuop_func op_2180_20_nf;
+extern cpuop_func op_2180_20_ff;
+extern cpuop_func op_2188_20_nf;
+extern cpuop_func op_2188_20_ff;
+extern cpuop_func op_2190_20_nf;
+extern cpuop_func op_2190_20_ff;
+extern cpuop_func op_2198_20_nf;
+extern cpuop_func op_2198_20_ff;
+extern cpuop_func op_21a0_20_nf;
+extern cpuop_func op_21a0_20_ff;
+extern cpuop_func op_21a8_20_nf;
+extern cpuop_func op_21a8_20_ff;
+extern cpuop_func op_21b0_20_nf;
+extern cpuop_func op_21b0_20_ff;
+extern cpuop_func op_21b8_20_nf;
+extern cpuop_func op_21b8_20_ff;
+extern cpuop_func op_21b9_20_nf;
+extern cpuop_func op_21b9_20_ff;
+extern cpuop_func op_21ba_20_nf;
+extern cpuop_func op_21ba_20_ff;
+extern cpuop_func op_21bb_20_nf;
+extern cpuop_func op_21bb_20_ff;
+extern cpuop_func op_21bc_20_nf;
+extern cpuop_func op_21bc_20_ff;
+extern cpuop_func op_21c0_20_nf;
+extern cpuop_func op_21c0_20_ff;
+extern cpuop_func op_21c8_20_nf;
+extern cpuop_func op_21c8_20_ff;
+extern cpuop_func op_21d0_20_nf;
+extern cpuop_func op_21d0_20_ff;
+extern cpuop_func op_21d8_20_nf;
+extern cpuop_func op_21d8_20_ff;
+extern cpuop_func op_21e0_20_nf;
+extern cpuop_func op_21e0_20_ff;
+extern cpuop_func op_21e8_20_nf;
+extern cpuop_func op_21e8_20_ff;
+extern cpuop_func op_21f0_20_nf;
+extern cpuop_func op_21f0_20_ff;
+extern cpuop_func op_21f8_20_nf;
+extern cpuop_func op_21f8_20_ff;
+extern cpuop_func op_21f9_20_nf;
+extern cpuop_func op_21f9_20_ff;
+extern cpuop_func op_21fa_20_nf;
+extern cpuop_func op_21fa_20_ff;
+extern cpuop_func op_21fb_20_nf;
+extern cpuop_func op_21fb_20_ff;
+extern cpuop_func op_21fc_20_nf;
+extern cpuop_func op_21fc_20_ff;
+extern cpuop_func op_23c0_20_nf;
+extern cpuop_func op_23c0_20_ff;
+extern cpuop_func op_23c8_20_nf;
+extern cpuop_func op_23c8_20_ff;
+extern cpuop_func op_23d0_20_nf;
+extern cpuop_func op_23d0_20_ff;
+extern cpuop_func op_23d8_20_nf;
+extern cpuop_func op_23d8_20_ff;
+extern cpuop_func op_23e0_20_nf;
+extern cpuop_func op_23e0_20_ff;
+extern cpuop_func op_23e8_20_nf;
+extern cpuop_func op_23e8_20_ff;
+extern cpuop_func op_23f0_20_nf;
+extern cpuop_func op_23f0_20_ff;
+extern cpuop_func op_23f8_20_nf;
+extern cpuop_func op_23f8_20_ff;
+extern cpuop_func op_23f9_20_nf;
+extern cpuop_func op_23f9_20_ff;
+extern cpuop_func op_23fa_20_nf;
+extern cpuop_func op_23fa_20_ff;
+extern cpuop_func op_23fb_20_nf;
+extern cpuop_func op_23fb_20_ff;
+extern cpuop_func op_23fc_20_nf;
+extern cpuop_func op_23fc_20_ff;
+extern cpuop_func op_3000_20_nf;
+extern cpuop_func op_3000_20_ff;
+extern cpuop_func op_3008_20_nf;
+extern cpuop_func op_3008_20_ff;
+extern cpuop_func op_3010_20_nf;
+extern cpuop_func op_3010_20_ff;
+extern cpuop_func op_3018_20_nf;
+extern cpuop_func op_3018_20_ff;
+extern cpuop_func op_3020_20_nf;
+extern cpuop_func op_3020_20_ff;
+extern cpuop_func op_3028_20_nf;
+extern cpuop_func op_3028_20_ff;
+extern cpuop_func op_3030_20_nf;
+extern cpuop_func op_3030_20_ff;
+extern cpuop_func op_3038_20_nf;
+extern cpuop_func op_3038_20_ff;
+extern cpuop_func op_3039_20_nf;
+extern cpuop_func op_3039_20_ff;
+extern cpuop_func op_303a_20_nf;
+extern cpuop_func op_303a_20_ff;
+extern cpuop_func op_303b_20_nf;
+extern cpuop_func op_303b_20_ff;
+extern cpuop_func op_303c_20_nf;
+extern cpuop_func op_303c_20_ff;
+extern cpuop_func op_3040_20_nf;
+extern cpuop_func op_3040_20_ff;
+extern cpuop_func op_3048_20_nf;
+extern cpuop_func op_3048_20_ff;
+extern cpuop_func op_3050_20_nf;
+extern cpuop_func op_3050_20_ff;
+extern cpuop_func op_3058_20_nf;
+extern cpuop_func op_3058_20_ff;
+extern cpuop_func op_3060_20_nf;
+extern cpuop_func op_3060_20_ff;
+extern cpuop_func op_3068_20_nf;
+extern cpuop_func op_3068_20_ff;
+extern cpuop_func op_3070_20_nf;
+extern cpuop_func op_3070_20_ff;
+extern cpuop_func op_3078_20_nf;
+extern cpuop_func op_3078_20_ff;
+extern cpuop_func op_3079_20_nf;
+extern cpuop_func op_3079_20_ff;
+extern cpuop_func op_307a_20_nf;
+extern cpuop_func op_307a_20_ff;
+extern cpuop_func op_307b_20_nf;
+extern cpuop_func op_307b_20_ff;
+extern cpuop_func op_307c_20_nf;
+extern cpuop_func op_307c_20_ff;
+extern cpuop_func op_3080_20_nf;
+extern cpuop_func op_3080_20_ff;
+extern cpuop_func op_3088_20_nf;
+extern cpuop_func op_3088_20_ff;
+extern cpuop_func op_3090_20_nf;
+extern cpuop_func op_3090_20_ff;
+extern cpuop_func op_3098_20_nf;
+extern cpuop_func op_3098_20_ff;
+extern cpuop_func op_30a0_20_nf;
+extern cpuop_func op_30a0_20_ff;
+extern cpuop_func op_30a8_20_nf;
+extern cpuop_func op_30a8_20_ff;
+extern cpuop_func op_30b0_20_nf;
+extern cpuop_func op_30b0_20_ff;
+extern cpuop_func op_30b8_20_nf;
+extern cpuop_func op_30b8_20_ff;
+extern cpuop_func op_30b9_20_nf;
+extern cpuop_func op_30b9_20_ff;
+extern cpuop_func op_30ba_20_nf;
+extern cpuop_func op_30ba_20_ff;
+extern cpuop_func op_30bb_20_nf;
+extern cpuop_func op_30bb_20_ff;
+extern cpuop_func op_30bc_20_nf;
+extern cpuop_func op_30bc_20_ff;
+extern cpuop_func op_30c0_20_nf;
+extern cpuop_func op_30c0_20_ff;
+extern cpuop_func op_30c8_20_nf;
+extern cpuop_func op_30c8_20_ff;
+extern cpuop_func op_30d0_20_nf;
+extern cpuop_func op_30d0_20_ff;
+extern cpuop_func op_30d8_20_nf;
+extern cpuop_func op_30d8_20_ff;
+extern cpuop_func op_30e0_20_nf;
+extern cpuop_func op_30e0_20_ff;
+extern cpuop_func op_30e8_20_nf;
+extern cpuop_func op_30e8_20_ff;
+extern cpuop_func op_30f0_20_nf;
+extern cpuop_func op_30f0_20_ff;
+extern cpuop_func op_30f8_20_nf;
+extern cpuop_func op_30f8_20_ff;
+extern cpuop_func op_30f9_20_nf;
+extern cpuop_func op_30f9_20_ff;
+extern cpuop_func op_30fa_20_nf;
+extern cpuop_func op_30fa_20_ff;
+extern cpuop_func op_30fb_20_nf;
+extern cpuop_func op_30fb_20_ff;
+extern cpuop_func op_30fc_20_nf;
+extern cpuop_func op_30fc_20_ff;
+extern cpuop_func op_3100_20_nf;
+extern cpuop_func op_3100_20_ff;
+extern cpuop_func op_3108_20_nf;
+extern cpuop_func op_3108_20_ff;
+extern cpuop_func op_3110_20_nf;
+extern cpuop_func op_3110_20_ff;
+extern cpuop_func op_3118_20_nf;
+extern cpuop_func op_3118_20_ff;
+extern cpuop_func op_3120_20_nf;
+extern cpuop_func op_3120_20_ff;
+extern cpuop_func op_3128_20_nf;
+extern cpuop_func op_3128_20_ff;
+extern cpuop_func op_3130_20_nf;
+extern cpuop_func op_3130_20_ff;
+extern cpuop_func op_3138_20_nf;
+extern cpuop_func op_3138_20_ff;
+extern cpuop_func op_3139_20_nf;
+extern cpuop_func op_3139_20_ff;
+extern cpuop_func op_313a_20_nf;
+extern cpuop_func op_313a_20_ff;
+extern cpuop_func op_313b_20_nf;
+extern cpuop_func op_313b_20_ff;
+extern cpuop_func op_313c_20_nf;
+extern cpuop_func op_313c_20_ff;
+extern cpuop_func op_3140_20_nf;
+extern cpuop_func op_3140_20_ff;
+extern cpuop_func op_3148_20_nf;
+extern cpuop_func op_3148_20_ff;
+extern cpuop_func op_3150_20_nf;
+extern cpuop_func op_3150_20_ff;
+extern cpuop_func op_3158_20_nf;
+extern cpuop_func op_3158_20_ff;
+extern cpuop_func op_3160_20_nf;
+extern cpuop_func op_3160_20_ff;
+extern cpuop_func op_3168_20_nf;
+extern cpuop_func op_3168_20_ff;
+extern cpuop_func op_3170_20_nf;
+extern cpuop_func op_3170_20_ff;
+extern cpuop_func op_3178_20_nf;
+extern cpuop_func op_3178_20_ff;
+extern cpuop_func op_3179_20_nf;
+extern cpuop_func op_3179_20_ff;
+extern cpuop_func op_317a_20_nf;
+extern cpuop_func op_317a_20_ff;
+extern cpuop_func op_317b_20_nf;
+extern cpuop_func op_317b_20_ff;
+extern cpuop_func op_317c_20_nf;
+extern cpuop_func op_317c_20_ff;
+extern cpuop_func op_3180_20_nf;
+extern cpuop_func op_3180_20_ff;
+extern cpuop_func op_3188_20_nf;
+extern cpuop_func op_3188_20_ff;
+extern cpuop_func op_3190_20_nf;
+extern cpuop_func op_3190_20_ff;
+extern cpuop_func op_3198_20_nf;
+extern cpuop_func op_3198_20_ff;
+extern cpuop_func op_31a0_20_nf;
+extern cpuop_func op_31a0_20_ff;
+extern cpuop_func op_31a8_20_nf;
+extern cpuop_func op_31a8_20_ff;
+extern cpuop_func op_31b0_20_nf;
+extern cpuop_func op_31b0_20_ff;
+extern cpuop_func op_31b8_20_nf;
+extern cpuop_func op_31b8_20_ff;
+extern cpuop_func op_31b9_20_nf;
+extern cpuop_func op_31b9_20_ff;
+extern cpuop_func op_31ba_20_nf;
+extern cpuop_func op_31ba_20_ff;
+extern cpuop_func op_31bb_20_nf;
+extern cpuop_func op_31bb_20_ff;
+extern cpuop_func op_31bc_20_nf;
+extern cpuop_func op_31bc_20_ff;
+extern cpuop_func op_31c0_20_nf;
+extern cpuop_func op_31c0_20_ff;
+extern cpuop_func op_31c8_20_nf;
+extern cpuop_func op_31c8_20_ff;
+extern cpuop_func op_31d0_20_nf;
+extern cpuop_func op_31d0_20_ff;
+extern cpuop_func op_31d8_20_nf;
+extern cpuop_func op_31d8_20_ff;
+extern cpuop_func op_31e0_20_nf;
+extern cpuop_func op_31e0_20_ff;
+extern cpuop_func op_31e8_20_nf;
+extern cpuop_func op_31e8_20_ff;
+extern cpuop_func op_31f0_20_nf;
+extern cpuop_func op_31f0_20_ff;
+extern cpuop_func op_31f8_20_nf;
+extern cpuop_func op_31f8_20_ff;
+extern cpuop_func op_31f9_20_nf;
+extern cpuop_func op_31f9_20_ff;
+extern cpuop_func op_31fa_20_nf;
+extern cpuop_func op_31fa_20_ff;
+extern cpuop_func op_31fb_20_nf;
+extern cpuop_func op_31fb_20_ff;
+extern cpuop_func op_31fc_20_nf;
+extern cpuop_func op_31fc_20_ff;
+extern cpuop_func op_33c0_20_nf;
+extern cpuop_func op_33c0_20_ff;
+extern cpuop_func op_33c8_20_nf;
+extern cpuop_func op_33c8_20_ff;
+extern cpuop_func op_33d0_20_nf;
+extern cpuop_func op_33d0_20_ff;
+extern cpuop_func op_33d8_20_nf;
+extern cpuop_func op_33d8_20_ff;
+extern cpuop_func op_33e0_20_nf;
+extern cpuop_func op_33e0_20_ff;
+extern cpuop_func op_33e8_20_nf;
+extern cpuop_func op_33e8_20_ff;
+extern cpuop_func op_33f0_20_nf;
+extern cpuop_func op_33f0_20_ff;
+extern cpuop_func op_33f8_20_nf;
+extern cpuop_func op_33f8_20_ff;
+extern cpuop_func op_33f9_20_nf;
+extern cpuop_func op_33f9_20_ff;
+extern cpuop_func op_33fa_20_nf;
+extern cpuop_func op_33fa_20_ff;
+extern cpuop_func op_33fb_20_nf;
+extern cpuop_func op_33fb_20_ff;
+extern cpuop_func op_33fc_20_nf;
+extern cpuop_func op_33fc_20_ff;
+extern cpuop_func op_4000_20_nf;
+extern cpuop_func op_4000_20_ff;
+extern cpuop_func op_4010_20_nf;
+extern cpuop_func op_4010_20_ff;
+extern cpuop_func op_4018_20_nf;
+extern cpuop_func op_4018_20_ff;
+extern cpuop_func op_4020_20_nf;
+extern cpuop_func op_4020_20_ff;
+extern cpuop_func op_4028_20_nf;
+extern cpuop_func op_4028_20_ff;
+extern cpuop_func op_4030_20_nf;
+extern cpuop_func op_4030_20_ff;
+extern cpuop_func op_4038_20_nf;
+extern cpuop_func op_4038_20_ff;
+extern cpuop_func op_4039_20_nf;
+extern cpuop_func op_4039_20_ff;
+extern cpuop_func op_4040_20_nf;
+extern cpuop_func op_4040_20_ff;
+extern cpuop_func op_4050_20_nf;
+extern cpuop_func op_4050_20_ff;
+extern cpuop_func op_4058_20_nf;
+extern cpuop_func op_4058_20_ff;
+extern cpuop_func op_4060_20_nf;
+extern cpuop_func op_4060_20_ff;
+extern cpuop_func op_4068_20_nf;
+extern cpuop_func op_4068_20_ff;
+extern cpuop_func op_4070_20_nf;
+extern cpuop_func op_4070_20_ff;
+extern cpuop_func op_4078_20_nf;
+extern cpuop_func op_4078_20_ff;
+extern cpuop_func op_4079_20_nf;
+extern cpuop_func op_4079_20_ff;
+extern cpuop_func op_4080_20_nf;
+extern cpuop_func op_4080_20_ff;
+extern cpuop_func op_4090_20_nf;
+extern cpuop_func op_4090_20_ff;
+extern cpuop_func op_4098_20_nf;
+extern cpuop_func op_4098_20_ff;
+extern cpuop_func op_40a0_20_nf;
+extern cpuop_func op_40a0_20_ff;
+extern cpuop_func op_40a8_20_nf;
+extern cpuop_func op_40a8_20_ff;
+extern cpuop_func op_40b0_20_nf;
+extern cpuop_func op_40b0_20_ff;
+extern cpuop_func op_40b8_20_nf;
+extern cpuop_func op_40b8_20_ff;
+extern cpuop_func op_40b9_20_nf;
+extern cpuop_func op_40b9_20_ff;
+extern cpuop_func op_40c0_20_nf;
+extern cpuop_func op_40c0_20_ff;
+extern cpuop_func op_40d0_20_nf;
+extern cpuop_func op_40d0_20_ff;
+extern cpuop_func op_40d8_20_nf;
+extern cpuop_func op_40d8_20_ff;
+extern cpuop_func op_40e0_20_nf;
+extern cpuop_func op_40e0_20_ff;
+extern cpuop_func op_40e8_20_nf;
+extern cpuop_func op_40e8_20_ff;
+extern cpuop_func op_40f0_20_nf;
+extern cpuop_func op_40f0_20_ff;
+extern cpuop_func op_40f8_20_nf;
+extern cpuop_func op_40f8_20_ff;
+extern cpuop_func op_40f9_20_nf;
+extern cpuop_func op_40f9_20_ff;
+extern cpuop_func op_4100_20_nf;
+extern cpuop_func op_4100_20_ff;
+extern cpuop_func op_4110_20_nf;
+extern cpuop_func op_4110_20_ff;
+extern cpuop_func op_4118_20_nf;
+extern cpuop_func op_4118_20_ff;
+extern cpuop_func op_4120_20_nf;
+extern cpuop_func op_4120_20_ff;
+extern cpuop_func op_4128_20_nf;
+extern cpuop_func op_4128_20_ff;
+extern cpuop_func op_4130_20_nf;
+extern cpuop_func op_4130_20_ff;
+extern cpuop_func op_4138_20_nf;
+extern cpuop_func op_4138_20_ff;
+extern cpuop_func op_4139_20_nf;
+extern cpuop_func op_4139_20_ff;
+extern cpuop_func op_413a_20_nf;
+extern cpuop_func op_413a_20_ff;
+extern cpuop_func op_413b_20_nf;
+extern cpuop_func op_413b_20_ff;
+extern cpuop_func op_413c_20_nf;
+extern cpuop_func op_413c_20_ff;
+extern cpuop_func op_4180_20_nf;
+extern cpuop_func op_4180_20_ff;
+extern cpuop_func op_4190_20_nf;
+extern cpuop_func op_4190_20_ff;
+extern cpuop_func op_4198_20_nf;
+extern cpuop_func op_4198_20_ff;
+extern cpuop_func op_41a0_20_nf;
+extern cpuop_func op_41a0_20_ff;
+extern cpuop_func op_41a8_20_nf;
+extern cpuop_func op_41a8_20_ff;
+extern cpuop_func op_41b0_20_nf;
+extern cpuop_func op_41b0_20_ff;
+extern cpuop_func op_41b8_20_nf;
+extern cpuop_func op_41b8_20_ff;
+extern cpuop_func op_41b9_20_nf;
+extern cpuop_func op_41b9_20_ff;
+extern cpuop_func op_41ba_20_nf;
+extern cpuop_func op_41ba_20_ff;
+extern cpuop_func op_41bb_20_nf;
+extern cpuop_func op_41bb_20_ff;
+extern cpuop_func op_41bc_20_nf;
+extern cpuop_func op_41bc_20_ff;
+extern cpuop_func op_41d0_20_nf;
+extern cpuop_func op_41d0_20_ff;
+extern cpuop_func op_41e8_20_nf;
+extern cpuop_func op_41e8_20_ff;
+extern cpuop_func op_41f0_20_nf;
+extern cpuop_func op_41f0_20_ff;
+extern cpuop_func op_41f8_20_nf;
+extern cpuop_func op_41f8_20_ff;
+extern cpuop_func op_41f9_20_nf;
+extern cpuop_func op_41f9_20_ff;
+extern cpuop_func op_41fa_20_nf;
+extern cpuop_func op_41fa_20_ff;
+extern cpuop_func op_41fb_20_nf;
+extern cpuop_func op_41fb_20_ff;
+extern cpuop_func op_4200_20_nf;
+extern cpuop_func op_4200_20_ff;
+extern cpuop_func op_4210_20_nf;
+extern cpuop_func op_4210_20_ff;
+extern cpuop_func op_4218_20_nf;
+extern cpuop_func op_4218_20_ff;
+extern cpuop_func op_4220_20_nf;
+extern cpuop_func op_4220_20_ff;
+extern cpuop_func op_4228_20_nf;
+extern cpuop_func op_4228_20_ff;
+extern cpuop_func op_4230_20_nf;
+extern cpuop_func op_4230_20_ff;
+extern cpuop_func op_4238_20_nf;
+extern cpuop_func op_4238_20_ff;
+extern cpuop_func op_4239_20_nf;
+extern cpuop_func op_4239_20_ff;
+extern cpuop_func op_4240_20_nf;
+extern cpuop_func op_4240_20_ff;
+extern cpuop_func op_4250_20_nf;
+extern cpuop_func op_4250_20_ff;
+extern cpuop_func op_4258_20_nf;
+extern cpuop_func op_4258_20_ff;
+extern cpuop_func op_4260_20_nf;
+extern cpuop_func op_4260_20_ff;
+extern cpuop_func op_4268_20_nf;
+extern cpuop_func op_4268_20_ff;
+extern cpuop_func op_4270_20_nf;
+extern cpuop_func op_4270_20_ff;
+extern cpuop_func op_4278_20_nf;
+extern cpuop_func op_4278_20_ff;
+extern cpuop_func op_4279_20_nf;
+extern cpuop_func op_4279_20_ff;
+extern cpuop_func op_4280_20_nf;
+extern cpuop_func op_4280_20_ff;
+extern cpuop_func op_4290_20_nf;
+extern cpuop_func op_4290_20_ff;
+extern cpuop_func op_4298_20_nf;
+extern cpuop_func op_4298_20_ff;
+extern cpuop_func op_42a0_20_nf;
+extern cpuop_func op_42a0_20_ff;
+extern cpuop_func op_42a8_20_nf;
+extern cpuop_func op_42a8_20_ff;
+extern cpuop_func op_42b0_20_nf;
+extern cpuop_func op_42b0_20_ff;
+extern cpuop_func op_42b8_20_nf;
+extern cpuop_func op_42b8_20_ff;
+extern cpuop_func op_42b9_20_nf;
+extern cpuop_func op_42b9_20_ff;
+extern cpuop_func op_42c0_20_nf;
+extern cpuop_func op_42c0_20_ff;
+extern cpuop_func op_42d0_20_nf;
+extern cpuop_func op_42d0_20_ff;
+extern cpuop_func op_42d8_20_nf;
+extern cpuop_func op_42d8_20_ff;
+extern cpuop_func op_42e0_20_nf;
+extern cpuop_func op_42e0_20_ff;
+extern cpuop_func op_42e8_20_nf;
+extern cpuop_func op_42e8_20_ff;
+extern cpuop_func op_42f0_20_nf;
+extern cpuop_func op_42f0_20_ff;
+extern cpuop_func op_42f8_20_nf;
+extern cpuop_func op_42f8_20_ff;
+extern cpuop_func op_42f9_20_nf;
+extern cpuop_func op_42f9_20_ff;
+extern cpuop_func op_4400_20_nf;
+extern cpuop_func op_4400_20_ff;
+extern cpuop_func op_4410_20_nf;
+extern cpuop_func op_4410_20_ff;
+extern cpuop_func op_4418_20_nf;
+extern cpuop_func op_4418_20_ff;
+extern cpuop_func op_4420_20_nf;
+extern cpuop_func op_4420_20_ff;
+extern cpuop_func op_4428_20_nf;
+extern cpuop_func op_4428_20_ff;
+extern cpuop_func op_4430_20_nf;
+extern cpuop_func op_4430_20_ff;
+extern cpuop_func op_4438_20_nf;
+extern cpuop_func op_4438_20_ff;
+extern cpuop_func op_4439_20_nf;
+extern cpuop_func op_4439_20_ff;
+extern cpuop_func op_4440_20_nf;
+extern cpuop_func op_4440_20_ff;
+extern cpuop_func op_4450_20_nf;
+extern cpuop_func op_4450_20_ff;
+extern cpuop_func op_4458_20_nf;
+extern cpuop_func op_4458_20_ff;
+extern cpuop_func op_4460_20_nf;
+extern cpuop_func op_4460_20_ff;
+extern cpuop_func op_4468_20_nf;
+extern cpuop_func op_4468_20_ff;
+extern cpuop_func op_4470_20_nf;
+extern cpuop_func op_4470_20_ff;
+extern cpuop_func op_4478_20_nf;
+extern cpuop_func op_4478_20_ff;
+extern cpuop_func op_4479_20_nf;
+extern cpuop_func op_4479_20_ff;
+extern cpuop_func op_4480_20_nf;
+extern cpuop_func op_4480_20_ff;
+extern cpuop_func op_4490_20_nf;
+extern cpuop_func op_4490_20_ff;
+extern cpuop_func op_4498_20_nf;
+extern cpuop_func op_4498_20_ff;
+extern cpuop_func op_44a0_20_nf;
+extern cpuop_func op_44a0_20_ff;
+extern cpuop_func op_44a8_20_nf;
+extern cpuop_func op_44a8_20_ff;
+extern cpuop_func op_44b0_20_nf;
+extern cpuop_func op_44b0_20_ff;
+extern cpuop_func op_44b8_20_nf;
+extern cpuop_func op_44b8_20_ff;
+extern cpuop_func op_44b9_20_nf;
+extern cpuop_func op_44b9_20_ff;
+extern cpuop_func op_44c0_20_nf;
+extern cpuop_func op_44c0_20_ff;
+extern cpuop_func op_44d0_20_nf;
+extern cpuop_func op_44d0_20_ff;
+extern cpuop_func op_44d8_20_nf;
+extern cpuop_func op_44d8_20_ff;
+extern cpuop_func op_44e0_20_nf;
+extern cpuop_func op_44e0_20_ff;
+extern cpuop_func op_44e8_20_nf;
+extern cpuop_func op_44e8_20_ff;
+extern cpuop_func op_44f0_20_nf;
+extern cpuop_func op_44f0_20_ff;
+extern cpuop_func op_44f8_20_nf;
+extern cpuop_func op_44f8_20_ff;
+extern cpuop_func op_44f9_20_nf;
+extern cpuop_func op_44f9_20_ff;
+extern cpuop_func op_44fa_20_nf;
+extern cpuop_func op_44fa_20_ff;
+extern cpuop_func op_44fb_20_nf;
+extern cpuop_func op_44fb_20_ff;
+extern cpuop_func op_44fc_20_nf;
+extern cpuop_func op_44fc_20_ff;
+extern cpuop_func op_4600_20_nf;
+extern cpuop_func op_4600_20_ff;
+extern cpuop_func op_4610_20_nf;
+extern cpuop_func op_4610_20_ff;
+extern cpuop_func op_4618_20_nf;
+extern cpuop_func op_4618_20_ff;
+extern cpuop_func op_4620_20_nf;
+extern cpuop_func op_4620_20_ff;
+extern cpuop_func op_4628_20_nf;
+extern cpuop_func op_4628_20_ff;
+extern cpuop_func op_4630_20_nf;
+extern cpuop_func op_4630_20_ff;
+extern cpuop_func op_4638_20_nf;
+extern cpuop_func op_4638_20_ff;
+extern cpuop_func op_4639_20_nf;
+extern cpuop_func op_4639_20_ff;
+extern cpuop_func op_4640_20_nf;
+extern cpuop_func op_4640_20_ff;
+extern cpuop_func op_4650_20_nf;
+extern cpuop_func op_4650_20_ff;
+extern cpuop_func op_4658_20_nf;
+extern cpuop_func op_4658_20_ff;
+extern cpuop_func op_4660_20_nf;
+extern cpuop_func op_4660_20_ff;
+extern cpuop_func op_4668_20_nf;
+extern cpuop_func op_4668_20_ff;
+extern cpuop_func op_4670_20_nf;
+extern cpuop_func op_4670_20_ff;
+extern cpuop_func op_4678_20_nf;
+extern cpuop_func op_4678_20_ff;
+extern cpuop_func op_4679_20_nf;
+extern cpuop_func op_4679_20_ff;
+extern cpuop_func op_4680_20_nf;
+extern cpuop_func op_4680_20_ff;
+extern cpuop_func op_4690_20_nf;
+extern cpuop_func op_4690_20_ff;
+extern cpuop_func op_4698_20_nf;
+extern cpuop_func op_4698_20_ff;
+extern cpuop_func op_46a0_20_nf;
+extern cpuop_func op_46a0_20_ff;
+extern cpuop_func op_46a8_20_nf;
+extern cpuop_func op_46a8_20_ff;
+extern cpuop_func op_46b0_20_nf;
+extern cpuop_func op_46b0_20_ff;
+extern cpuop_func op_46b8_20_nf;
+extern cpuop_func op_46b8_20_ff;
+extern cpuop_func op_46b9_20_nf;
+extern cpuop_func op_46b9_20_ff;
+extern cpuop_func op_46c0_20_nf;
+extern cpuop_func op_46c0_20_ff;
+extern cpuop_func op_46d0_20_nf;
+extern cpuop_func op_46d0_20_ff;
+extern cpuop_func op_46d8_20_nf;
+extern cpuop_func op_46d8_20_ff;
+extern cpuop_func op_46e0_20_nf;
+extern cpuop_func op_46e0_20_ff;
+extern cpuop_func op_46e8_20_nf;
+extern cpuop_func op_46e8_20_ff;
+extern cpuop_func op_46f0_20_nf;
+extern cpuop_func op_46f0_20_ff;
+extern cpuop_func op_46f8_20_nf;
+extern cpuop_func op_46f8_20_ff;
+extern cpuop_func op_46f9_20_nf;
+extern cpuop_func op_46f9_20_ff;
+extern cpuop_func op_46fa_20_nf;
+extern cpuop_func op_46fa_20_ff;
+extern cpuop_func op_46fb_20_nf;
+extern cpuop_func op_46fb_20_ff;
+extern cpuop_func op_46fc_20_nf;
+extern cpuop_func op_46fc_20_ff;
+extern cpuop_func op_4800_20_nf;
+extern cpuop_func op_4800_20_ff;
+extern cpuop_func op_4808_20_nf;
+extern cpuop_func op_4808_20_ff;
+extern cpuop_func op_4810_20_nf;
+extern cpuop_func op_4810_20_ff;
+extern cpuop_func op_4818_20_nf;
+extern cpuop_func op_4818_20_ff;
+extern cpuop_func op_4820_20_nf;
+extern cpuop_func op_4820_20_ff;
+extern cpuop_func op_4828_20_nf;
+extern cpuop_func op_4828_20_ff;
+extern cpuop_func op_4830_20_nf;
+extern cpuop_func op_4830_20_ff;
+extern cpuop_func op_4838_20_nf;
+extern cpuop_func op_4838_20_ff;
+extern cpuop_func op_4839_20_nf;
+extern cpuop_func op_4839_20_ff;
+extern cpuop_func op_4840_20_nf;
+extern cpuop_func op_4840_20_ff;
+extern cpuop_func op_4848_20_nf;
+extern cpuop_func op_4848_20_ff;
+extern cpuop_func op_4850_20_nf;
+extern cpuop_func op_4850_20_ff;
+extern cpuop_func op_4868_20_nf;
+extern cpuop_func op_4868_20_ff;
+extern cpuop_func op_4870_20_nf;
+extern cpuop_func op_4870_20_ff;
+extern cpuop_func op_4878_20_nf;
+extern cpuop_func op_4878_20_ff;
+extern cpuop_func op_4879_20_nf;
+extern cpuop_func op_4879_20_ff;
+extern cpuop_func op_487a_20_nf;
+extern cpuop_func op_487a_20_ff;
+extern cpuop_func op_487b_20_nf;
+extern cpuop_func op_487b_20_ff;
+extern cpuop_func op_4880_20_nf;
+extern cpuop_func op_4880_20_ff;
+extern cpuop_func op_4890_20_nf;
+extern cpuop_func op_4890_20_ff;
+extern cpuop_func op_48a0_20_nf;
+extern cpuop_func op_48a0_20_ff;
+extern cpuop_func op_48a8_20_nf;
+extern cpuop_func op_48a8_20_ff;
+extern cpuop_func op_48b0_20_nf;
+extern cpuop_func op_48b0_20_ff;
+extern cpuop_func op_48b8_20_nf;
+extern cpuop_func op_48b8_20_ff;
+extern cpuop_func op_48b9_20_nf;
+extern cpuop_func op_48b9_20_ff;
+extern cpuop_func op_48c0_20_nf;
+extern cpuop_func op_48c0_20_ff;
+extern cpuop_func op_48d0_20_nf;
+extern cpuop_func op_48d0_20_ff;
+extern cpuop_func op_48e0_20_nf;
+extern cpuop_func op_48e0_20_ff;
+extern cpuop_func op_48e8_20_nf;
+extern cpuop_func op_48e8_20_ff;
+extern cpuop_func op_48f0_20_nf;
+extern cpuop_func op_48f0_20_ff;
+extern cpuop_func op_48f8_20_nf;
+extern cpuop_func op_48f8_20_ff;
+extern cpuop_func op_48f9_20_nf;
+extern cpuop_func op_48f9_20_ff;
+extern cpuop_func op_49c0_20_nf;
+extern cpuop_func op_49c0_20_ff;
+extern cpuop_func op_4a00_20_nf;
+extern cpuop_func op_4a00_20_ff;
+extern cpuop_func op_4a10_20_nf;
+extern cpuop_func op_4a10_20_ff;
+extern cpuop_func op_4a18_20_nf;
+extern cpuop_func op_4a18_20_ff;
+extern cpuop_func op_4a20_20_nf;
+extern cpuop_func op_4a20_20_ff;
+extern cpuop_func op_4a28_20_nf;
+extern cpuop_func op_4a28_20_ff;
+extern cpuop_func op_4a30_20_nf;
+extern cpuop_func op_4a30_20_ff;
+extern cpuop_func op_4a38_20_nf;
+extern cpuop_func op_4a38_20_ff;
+extern cpuop_func op_4a39_20_nf;
+extern cpuop_func op_4a39_20_ff;
+extern cpuop_func op_4a3a_20_nf;
+extern cpuop_func op_4a3a_20_ff;
+extern cpuop_func op_4a3b_20_nf;
+extern cpuop_func op_4a3b_20_ff;
+extern cpuop_func op_4a3c_20_nf;
+extern cpuop_func op_4a3c_20_ff;
+extern cpuop_func op_4a40_20_nf;
+extern cpuop_func op_4a40_20_ff;
+extern cpuop_func op_4a48_20_nf;
+extern cpuop_func op_4a48_20_ff;
+extern cpuop_func op_4a50_20_nf;
+extern cpuop_func op_4a50_20_ff;
+extern cpuop_func op_4a58_20_nf;
+extern cpuop_func op_4a58_20_ff;
+extern cpuop_func op_4a60_20_nf;
+extern cpuop_func op_4a60_20_ff;
+extern cpuop_func op_4a68_20_nf;
+extern cpuop_func op_4a68_20_ff;
+extern cpuop_func op_4a70_20_nf;
+extern cpuop_func op_4a70_20_ff;
+extern cpuop_func op_4a78_20_nf;
+extern cpuop_func op_4a78_20_ff;
+extern cpuop_func op_4a79_20_nf;
+extern cpuop_func op_4a79_20_ff;
+extern cpuop_func op_4a7a_20_nf;
+extern cpuop_func op_4a7a_20_ff;
+extern cpuop_func op_4a7b_20_nf;
+extern cpuop_func op_4a7b_20_ff;
+extern cpuop_func op_4a7c_20_nf;
+extern cpuop_func op_4a7c_20_ff;
+extern cpuop_func op_4a80_20_nf;
+extern cpuop_func op_4a80_20_ff;
+extern cpuop_func op_4a88_20_nf;
+extern cpuop_func op_4a88_20_ff;
+extern cpuop_func op_4a90_20_nf;
+extern cpuop_func op_4a90_20_ff;
+extern cpuop_func op_4a98_20_nf;
+extern cpuop_func op_4a98_20_ff;
+extern cpuop_func op_4aa0_20_nf;
+extern cpuop_func op_4aa0_20_ff;
+extern cpuop_func op_4aa8_20_nf;
+extern cpuop_func op_4aa8_20_ff;
+extern cpuop_func op_4ab0_20_nf;
+extern cpuop_func op_4ab0_20_ff;
+extern cpuop_func op_4ab8_20_nf;
+extern cpuop_func op_4ab8_20_ff;
+extern cpuop_func op_4ab9_20_nf;
+extern cpuop_func op_4ab9_20_ff;
+extern cpuop_func op_4aba_20_nf;
+extern cpuop_func op_4aba_20_ff;
+extern cpuop_func op_4abb_20_nf;
+extern cpuop_func op_4abb_20_ff;
+extern cpuop_func op_4abc_20_nf;
+extern cpuop_func op_4abc_20_ff;
+extern cpuop_func op_4ac0_20_nf;
+extern cpuop_func op_4ac0_20_ff;
+extern cpuop_func op_4ad0_20_nf;
+extern cpuop_func op_4ad0_20_ff;
+extern cpuop_func op_4ad8_20_nf;
+extern cpuop_func op_4ad8_20_ff;
+extern cpuop_func op_4ae0_20_nf;
+extern cpuop_func op_4ae0_20_ff;
+extern cpuop_func op_4ae8_20_nf;
+extern cpuop_func op_4ae8_20_ff;
+extern cpuop_func op_4af0_20_nf;
+extern cpuop_func op_4af0_20_ff;
+extern cpuop_func op_4af8_20_nf;
+extern cpuop_func op_4af8_20_ff;
+extern cpuop_func op_4af9_20_nf;
+extern cpuop_func op_4af9_20_ff;
+extern cpuop_func op_4c00_20_nf;
+extern cpuop_func op_4c00_20_ff;
+extern cpuop_func op_4c10_20_nf;
+extern cpuop_func op_4c10_20_ff;
+extern cpuop_func op_4c18_20_nf;
+extern cpuop_func op_4c18_20_ff;
+extern cpuop_func op_4c20_20_nf;
+extern cpuop_func op_4c20_20_ff;
+extern cpuop_func op_4c28_20_nf;
+extern cpuop_func op_4c28_20_ff;
+extern cpuop_func op_4c30_20_nf;
+extern cpuop_func op_4c30_20_ff;
+extern cpuop_func op_4c38_20_nf;
+extern cpuop_func op_4c38_20_ff;
+extern cpuop_func op_4c39_20_nf;
+extern cpuop_func op_4c39_20_ff;
+extern cpuop_func op_4c3a_20_nf;
+extern cpuop_func op_4c3a_20_ff;
+extern cpuop_func op_4c3b_20_nf;
+extern cpuop_func op_4c3b_20_ff;
+extern cpuop_func op_4c3c_20_nf;
+extern cpuop_func op_4c3c_20_ff;
+extern cpuop_func op_4c40_20_nf;
+extern cpuop_func op_4c40_20_ff;
+extern cpuop_func op_4c50_20_nf;
+extern cpuop_func op_4c50_20_ff;
+extern cpuop_func op_4c58_20_nf;
+extern cpuop_func op_4c58_20_ff;
+extern cpuop_func op_4c60_20_nf;
+extern cpuop_func op_4c60_20_ff;
+extern cpuop_func op_4c68_20_nf;
+extern cpuop_func op_4c68_20_ff;
+extern cpuop_func op_4c70_20_nf;
+extern cpuop_func op_4c70_20_ff;
+extern cpuop_func op_4c78_20_nf;
+extern cpuop_func op_4c78_20_ff;
+extern cpuop_func op_4c79_20_nf;
+extern cpuop_func op_4c79_20_ff;
+extern cpuop_func op_4c7a_20_nf;
+extern cpuop_func op_4c7a_20_ff;
+extern cpuop_func op_4c7b_20_nf;
+extern cpuop_func op_4c7b_20_ff;
+extern cpuop_func op_4c7c_20_nf;
+extern cpuop_func op_4c7c_20_ff;
+extern cpuop_func op_4c90_20_nf;
+extern cpuop_func op_4c90_20_ff;
+extern cpuop_func op_4c98_20_nf;
+extern cpuop_func op_4c98_20_ff;
+extern cpuop_func op_4ca8_20_nf;
+extern cpuop_func op_4ca8_20_ff;
+extern cpuop_func op_4cb0_20_nf;
+extern cpuop_func op_4cb0_20_ff;
+extern cpuop_func op_4cb8_20_nf;
+extern cpuop_func op_4cb8_20_ff;
+extern cpuop_func op_4cb9_20_nf;
+extern cpuop_func op_4cb9_20_ff;
+extern cpuop_func op_4cba_20_nf;
+extern cpuop_func op_4cba_20_ff;
+extern cpuop_func op_4cbb_20_nf;
+extern cpuop_func op_4cbb_20_ff;
+extern cpuop_func op_4cd0_20_nf;
+extern cpuop_func op_4cd0_20_ff;
+extern cpuop_func op_4cd8_20_nf;
+extern cpuop_func op_4cd8_20_ff;
+extern cpuop_func op_4ce8_20_nf;
+extern cpuop_func op_4ce8_20_ff;
+extern cpuop_func op_4cf0_20_nf;
+extern cpuop_func op_4cf0_20_ff;
+extern cpuop_func op_4cf8_20_nf;
+extern cpuop_func op_4cf8_20_ff;
+extern cpuop_func op_4cf9_20_nf;
+extern cpuop_func op_4cf9_20_ff;
+extern cpuop_func op_4cfa_20_nf;
+extern cpuop_func op_4cfa_20_ff;
+extern cpuop_func op_4cfb_20_nf;
+extern cpuop_func op_4cfb_20_ff;
+extern cpuop_func op_4e40_20_nf;
+extern cpuop_func op_4e40_20_ff;
+extern cpuop_func op_4e50_20_nf;
+extern cpuop_func op_4e50_20_ff;
+extern cpuop_func op_4e58_20_nf;
+extern cpuop_func op_4e58_20_ff;
+extern cpuop_func op_4e60_20_nf;
+extern cpuop_func op_4e60_20_ff;
+extern cpuop_func op_4e68_20_nf;
+extern cpuop_func op_4e68_20_ff;
+extern cpuop_func op_4e70_20_nf;
+extern cpuop_func op_4e70_20_ff;
+extern cpuop_func op_4e71_20_nf;
+extern cpuop_func op_4e71_20_ff;
+extern cpuop_func op_4e72_20_nf;
+extern cpuop_func op_4e72_20_ff;
+extern cpuop_func op_4e73_20_nf;
+extern cpuop_func op_4e73_20_ff;
+extern cpuop_func op_4e74_20_nf;
+extern cpuop_func op_4e74_20_ff;
+extern cpuop_func op_4e75_20_nf;
+extern cpuop_func op_4e75_20_ff;
+extern cpuop_func op_4e76_20_nf;
+extern cpuop_func op_4e76_20_ff;
+extern cpuop_func op_4e77_20_nf;
+extern cpuop_func op_4e77_20_ff;
+extern cpuop_func op_4e7a_20_nf;
+extern cpuop_func op_4e7a_20_ff;
+extern cpuop_func op_4e7b_20_nf;
+extern cpuop_func op_4e7b_20_ff;
+extern cpuop_func op_4e90_20_nf;
+extern cpuop_func op_4e90_20_ff;
+extern cpuop_func op_4ea8_20_nf;
+extern cpuop_func op_4ea8_20_ff;
+extern cpuop_func op_4eb0_20_nf;
+extern cpuop_func op_4eb0_20_ff;
+extern cpuop_func op_4eb8_20_nf;
+extern cpuop_func op_4eb8_20_ff;
+extern cpuop_func op_4eb9_20_nf;
+extern cpuop_func op_4eb9_20_ff;
+extern cpuop_func op_4eba_20_nf;
+extern cpuop_func op_4eba_20_ff;
+extern cpuop_func op_4ebb_20_nf;
+extern cpuop_func op_4ebb_20_ff;
+extern cpuop_func op_4ed0_20_nf;
+extern cpuop_func op_4ed0_20_ff;
+extern cpuop_func op_4ee8_20_nf;
+extern cpuop_func op_4ee8_20_ff;
+extern cpuop_func op_4ef0_20_nf;
+extern cpuop_func op_4ef0_20_ff;
+extern cpuop_func op_4ef8_20_nf;
+extern cpuop_func op_4ef8_20_ff;
+extern cpuop_func op_4ef9_20_nf;
+extern cpuop_func op_4ef9_20_ff;
+extern cpuop_func op_4efa_20_nf;
+extern cpuop_func op_4efa_20_ff;
+extern cpuop_func op_4efb_20_nf;
+extern cpuop_func op_4efb_20_ff;
+extern cpuop_func op_5000_20_nf;
+extern cpuop_func op_5000_20_ff;
+extern cpuop_func op_5010_20_nf;
+extern cpuop_func op_5010_20_ff;
+extern cpuop_func op_5018_20_nf;
+extern cpuop_func op_5018_20_ff;
+extern cpuop_func op_5020_20_nf;
+extern cpuop_func op_5020_20_ff;
+extern cpuop_func op_5028_20_nf;
+extern cpuop_func op_5028_20_ff;
+extern cpuop_func op_5030_20_nf;
+extern cpuop_func op_5030_20_ff;
+extern cpuop_func op_5038_20_nf;
+extern cpuop_func op_5038_20_ff;
+extern cpuop_func op_5039_20_nf;
+extern cpuop_func op_5039_20_ff;
+extern cpuop_func op_5040_20_nf;
+extern cpuop_func op_5040_20_ff;
+extern cpuop_func op_5048_20_nf;
+extern cpuop_func op_5048_20_ff;
+extern cpuop_func op_5050_20_nf;
+extern cpuop_func op_5050_20_ff;
+extern cpuop_func op_5058_20_nf;
+extern cpuop_func op_5058_20_ff;
+extern cpuop_func op_5060_20_nf;
+extern cpuop_func op_5060_20_ff;
+extern cpuop_func op_5068_20_nf;
+extern cpuop_func op_5068_20_ff;
+extern cpuop_func op_5070_20_nf;
+extern cpuop_func op_5070_20_ff;
+extern cpuop_func op_5078_20_nf;
+extern cpuop_func op_5078_20_ff;
+extern cpuop_func op_5079_20_nf;
+extern cpuop_func op_5079_20_ff;
+extern cpuop_func op_5080_20_nf;
+extern cpuop_func op_5080_20_ff;
+extern cpuop_func op_5088_20_nf;
+extern cpuop_func op_5088_20_ff;
+extern cpuop_func op_5090_20_nf;
+extern cpuop_func op_5090_20_ff;
+extern cpuop_func op_5098_20_nf;
+extern cpuop_func op_5098_20_ff;
+extern cpuop_func op_50a0_20_nf;
+extern cpuop_func op_50a0_20_ff;
+extern cpuop_func op_50a8_20_nf;
+extern cpuop_func op_50a8_20_ff;
+extern cpuop_func op_50b0_20_nf;
+extern cpuop_func op_50b0_20_ff;
+extern cpuop_func op_50b8_20_nf;
+extern cpuop_func op_50b8_20_ff;
+extern cpuop_func op_50b9_20_nf;
+extern cpuop_func op_50b9_20_ff;
+extern cpuop_func op_50c0_20_nf;
+extern cpuop_func op_50c0_20_ff;
+extern cpuop_func op_50c8_20_nf;
+extern cpuop_func op_50c8_20_ff;
+extern cpuop_func op_50d0_20_nf;
+extern cpuop_func op_50d0_20_ff;
+extern cpuop_func op_50d8_20_nf;
+extern cpuop_func op_50d8_20_ff;
+extern cpuop_func op_50e0_20_nf;
+extern cpuop_func op_50e0_20_ff;
+extern cpuop_func op_50e8_20_nf;
+extern cpuop_func op_50e8_20_ff;
+extern cpuop_func op_50f0_20_nf;
+extern cpuop_func op_50f0_20_ff;
+extern cpuop_func op_50f8_20_nf;
+extern cpuop_func op_50f8_20_ff;
+extern cpuop_func op_50f9_20_nf;
+extern cpuop_func op_50f9_20_ff;
+extern cpuop_func op_50fa_20_nf;
+extern cpuop_func op_50fa_20_ff;
+extern cpuop_func op_50fb_20_nf;
+extern cpuop_func op_50fb_20_ff;
+extern cpuop_func op_50fc_20_nf;
+extern cpuop_func op_50fc_20_ff;
+extern cpuop_func op_5100_20_nf;
+extern cpuop_func op_5100_20_ff;
+extern cpuop_func op_5110_20_nf;
+extern cpuop_func op_5110_20_ff;
+extern cpuop_func op_5118_20_nf;
+extern cpuop_func op_5118_20_ff;
+extern cpuop_func op_5120_20_nf;
+extern cpuop_func op_5120_20_ff;
+extern cpuop_func op_5128_20_nf;
+extern cpuop_func op_5128_20_ff;
+extern cpuop_func op_5130_20_nf;
+extern cpuop_func op_5130_20_ff;
+extern cpuop_func op_5138_20_nf;
+extern cpuop_func op_5138_20_ff;
+extern cpuop_func op_5139_20_nf;
+extern cpuop_func op_5139_20_ff;
+extern cpuop_func op_5140_20_nf;
+extern cpuop_func op_5140_20_ff;
+extern cpuop_func op_5148_20_nf;
+extern cpuop_func op_5148_20_ff;
+extern cpuop_func op_5150_20_nf;
+extern cpuop_func op_5150_20_ff;
+extern cpuop_func op_5158_20_nf;
+extern cpuop_func op_5158_20_ff;
+extern cpuop_func op_5160_20_nf;
+extern cpuop_func op_5160_20_ff;
+extern cpuop_func op_5168_20_nf;
+extern cpuop_func op_5168_20_ff;
+extern cpuop_func op_5170_20_nf;
+extern cpuop_func op_5170_20_ff;
+extern cpuop_func op_5178_20_nf;
+extern cpuop_func op_5178_20_ff;
+extern cpuop_func op_5179_20_nf;
+extern cpuop_func op_5179_20_ff;
+extern cpuop_func op_5180_20_nf;
+extern cpuop_func op_5180_20_ff;
+extern cpuop_func op_5188_20_nf;
+extern cpuop_func op_5188_20_ff;
+extern cpuop_func op_5190_20_nf;
+extern cpuop_func op_5190_20_ff;
+extern cpuop_func op_5198_20_nf;
+extern cpuop_func op_5198_20_ff;
+extern cpuop_func op_51a0_20_nf;
+extern cpuop_func op_51a0_20_ff;
+extern cpuop_func op_51a8_20_nf;
+extern cpuop_func op_51a8_20_ff;
+extern cpuop_func op_51b0_20_nf;
+extern cpuop_func op_51b0_20_ff;
+extern cpuop_func op_51b8_20_nf;
+extern cpuop_func op_51b8_20_ff;
+extern cpuop_func op_51b9_20_nf;
+extern cpuop_func op_51b9_20_ff;
+extern cpuop_func op_51c0_20_nf;
+extern cpuop_func op_51c0_20_ff;
+extern cpuop_func op_51c8_20_nf;
+extern cpuop_func op_51c8_20_ff;
+extern cpuop_func op_51d0_20_nf;
+extern cpuop_func op_51d0_20_ff;
+extern cpuop_func op_51d8_20_nf;
+extern cpuop_func op_51d8_20_ff;
+extern cpuop_func op_51e0_20_nf;
+extern cpuop_func op_51e0_20_ff;
+extern cpuop_func op_51e8_20_nf;
+extern cpuop_func op_51e8_20_ff;
+extern cpuop_func op_51f0_20_nf;
+extern cpuop_func op_51f0_20_ff;
+extern cpuop_func op_51f8_20_nf;
+extern cpuop_func op_51f8_20_ff;
+extern cpuop_func op_51f9_20_nf;
+extern cpuop_func op_51f9_20_ff;
+extern cpuop_func op_51fa_20_nf;
+extern cpuop_func op_51fa_20_ff;
+extern cpuop_func op_51fb_20_nf;
+extern cpuop_func op_51fb_20_ff;
+extern cpuop_func op_51fc_20_nf;
+extern cpuop_func op_51fc_20_ff;
+extern cpuop_func op_52c0_20_nf;
+extern cpuop_func op_52c0_20_ff;
+extern cpuop_func op_52c8_20_nf;
+extern cpuop_func op_52c8_20_ff;
+extern cpuop_func op_52d0_20_nf;
+extern cpuop_func op_52d0_20_ff;
+extern cpuop_func op_52d8_20_nf;
+extern cpuop_func op_52d8_20_ff;
+extern cpuop_func op_52e0_20_nf;
+extern cpuop_func op_52e0_20_ff;
+extern cpuop_func op_52e8_20_nf;
+extern cpuop_func op_52e8_20_ff;
+extern cpuop_func op_52f0_20_nf;
+extern cpuop_func op_52f0_20_ff;
+extern cpuop_func op_52f8_20_nf;
+extern cpuop_func op_52f8_20_ff;
+extern cpuop_func op_52f9_20_nf;
+extern cpuop_func op_52f9_20_ff;
+extern cpuop_func op_52fa_20_nf;
+extern cpuop_func op_52fa_20_ff;
+extern cpuop_func op_52fb_20_nf;
+extern cpuop_func op_52fb_20_ff;
+extern cpuop_func op_52fc_20_nf;
+extern cpuop_func op_52fc_20_ff;
+extern cpuop_func op_53c0_20_nf;
+extern cpuop_func op_53c0_20_ff;
+extern cpuop_func op_53c8_20_nf;
+extern cpuop_func op_53c8_20_ff;
+extern cpuop_func op_53d0_20_nf;
+extern cpuop_func op_53d0_20_ff;
+extern cpuop_func op_53d8_20_nf;
+extern cpuop_func op_53d8_20_ff;
+extern cpuop_func op_53e0_20_nf;
+extern cpuop_func op_53e0_20_ff;
+extern cpuop_func op_53e8_20_nf;
+extern cpuop_func op_53e8_20_ff;
+extern cpuop_func op_53f0_20_nf;
+extern cpuop_func op_53f0_20_ff;
+extern cpuop_func op_53f8_20_nf;
+extern cpuop_func op_53f8_20_ff;
+extern cpuop_func op_53f9_20_nf;
+extern cpuop_func op_53f9_20_ff;
+extern cpuop_func op_53fa_20_nf;
+extern cpuop_func op_53fa_20_ff;
+extern cpuop_func op_53fb_20_nf;
+extern cpuop_func op_53fb_20_ff;
+extern cpuop_func op_53fc_20_nf;
+extern cpuop_func op_53fc_20_ff;
+extern cpuop_func op_54c0_20_nf;
+extern cpuop_func op_54c0_20_ff;
+extern cpuop_func op_54c8_20_nf;
+extern cpuop_func op_54c8_20_ff;
+extern cpuop_func op_54d0_20_nf;
+extern cpuop_func op_54d0_20_ff;
+extern cpuop_func op_54d8_20_nf;
+extern cpuop_func op_54d8_20_ff;
+extern cpuop_func op_54e0_20_nf;
+extern cpuop_func op_54e0_20_ff;
+extern cpuop_func op_54e8_20_nf;
+extern cpuop_func op_54e8_20_ff;
+extern cpuop_func op_54f0_20_nf;
+extern cpuop_func op_54f0_20_ff;
+extern cpuop_func op_54f8_20_nf;
+extern cpuop_func op_54f8_20_ff;
+extern cpuop_func op_54f9_20_nf;
+extern cpuop_func op_54f9_20_ff;
+extern cpuop_func op_54fa_20_nf;
+extern cpuop_func op_54fa_20_ff;
+extern cpuop_func op_54fb_20_nf;
+extern cpuop_func op_54fb_20_ff;
+extern cpuop_func op_54fc_20_nf;
+extern cpuop_func op_54fc_20_ff;
+extern cpuop_func op_55c0_20_nf;
+extern cpuop_func op_55c0_20_ff;
+extern cpuop_func op_55c8_20_nf;
+extern cpuop_func op_55c8_20_ff;
+extern cpuop_func op_55d0_20_nf;
+extern cpuop_func op_55d0_20_ff;
+extern cpuop_func op_55d8_20_nf;
+extern cpuop_func op_55d8_20_ff;
+extern cpuop_func op_55e0_20_nf;
+extern cpuop_func op_55e0_20_ff;
+extern cpuop_func op_55e8_20_nf;
+extern cpuop_func op_55e8_20_ff;
+extern cpuop_func op_55f0_20_nf;
+extern cpuop_func op_55f0_20_ff;
+extern cpuop_func op_55f8_20_nf;
+extern cpuop_func op_55f8_20_ff;
+extern cpuop_func op_55f9_20_nf;
+extern cpuop_func op_55f9_20_ff;
+extern cpuop_func op_55fa_20_nf;
+extern cpuop_func op_55fa_20_ff;
+extern cpuop_func op_55fb_20_nf;
+extern cpuop_func op_55fb_20_ff;
+extern cpuop_func op_55fc_20_nf;
+extern cpuop_func op_55fc_20_ff;
+extern cpuop_func op_56c0_20_nf;
+extern cpuop_func op_56c0_20_ff;
+extern cpuop_func op_56c8_20_nf;
+extern cpuop_func op_56c8_20_ff;
+extern cpuop_func op_56d0_20_nf;
+extern cpuop_func op_56d0_20_ff;
+extern cpuop_func op_56d8_20_nf;
+extern cpuop_func op_56d8_20_ff;
+extern cpuop_func op_56e0_20_nf;
+extern cpuop_func op_56e0_20_ff;
+extern cpuop_func op_56e8_20_nf;
+extern cpuop_func op_56e8_20_ff;
+extern cpuop_func op_56f0_20_nf;
+extern cpuop_func op_56f0_20_ff;
+extern cpuop_func op_56f8_20_nf;
+extern cpuop_func op_56f8_20_ff;
+extern cpuop_func op_56f9_20_nf;
+extern cpuop_func op_56f9_20_ff;
+extern cpuop_func op_56fa_20_nf;
+extern cpuop_func op_56fa_20_ff;
+extern cpuop_func op_56fb_20_nf;
+extern cpuop_func op_56fb_20_ff;
+extern cpuop_func op_56fc_20_nf;
+extern cpuop_func op_56fc_20_ff;
+extern cpuop_func op_57c0_20_nf;
+extern cpuop_func op_57c0_20_ff;
+extern cpuop_func op_57c8_20_nf;
+extern cpuop_func op_57c8_20_ff;
+extern cpuop_func op_57d0_20_nf;
+extern cpuop_func op_57d0_20_ff;
+extern cpuop_func op_57d8_20_nf;
+extern cpuop_func op_57d8_20_ff;
+extern cpuop_func op_57e0_20_nf;
+extern cpuop_func op_57e0_20_ff;
+extern cpuop_func op_57e8_20_nf;
+extern cpuop_func op_57e8_20_ff;
+extern cpuop_func op_57f0_20_nf;
+extern cpuop_func op_57f0_20_ff;
+extern cpuop_func op_57f8_20_nf;
+extern cpuop_func op_57f8_20_ff;
+extern cpuop_func op_57f9_20_nf;
+extern cpuop_func op_57f9_20_ff;
+extern cpuop_func op_57fa_20_nf;
+extern cpuop_func op_57fa_20_ff;
+extern cpuop_func op_57fb_20_nf;
+extern cpuop_func op_57fb_20_ff;
+extern cpuop_func op_57fc_20_nf;
+extern cpuop_func op_57fc_20_ff;
+extern cpuop_func op_58c0_20_nf;
+extern cpuop_func op_58c0_20_ff;
+extern cpuop_func op_58c8_20_nf;
+extern cpuop_func op_58c8_20_ff;
+extern cpuop_func op_58d0_20_nf;
+extern cpuop_func op_58d0_20_ff;
+extern cpuop_func op_58d8_20_nf;
+extern cpuop_func op_58d8_20_ff;
+extern cpuop_func op_58e0_20_nf;
+extern cpuop_func op_58e0_20_ff;
+extern cpuop_func op_58e8_20_nf;
+extern cpuop_func op_58e8_20_ff;
+extern cpuop_func op_58f0_20_nf;
+extern cpuop_func op_58f0_20_ff;
+extern cpuop_func op_58f8_20_nf;
+extern cpuop_func op_58f8_20_ff;
+extern cpuop_func op_58f9_20_nf;
+extern cpuop_func op_58f9_20_ff;
+extern cpuop_func op_58fa_20_nf;
+extern cpuop_func op_58fa_20_ff;
+extern cpuop_func op_58fb_20_nf;
+extern cpuop_func op_58fb_20_ff;
+extern cpuop_func op_58fc_20_nf;
+extern cpuop_func op_58fc_20_ff;
+extern cpuop_func op_59c0_20_nf;
+extern cpuop_func op_59c0_20_ff;
+extern cpuop_func op_59c8_20_nf;
+extern cpuop_func op_59c8_20_ff;
+extern cpuop_func op_59d0_20_nf;
+extern cpuop_func op_59d0_20_ff;
+extern cpuop_func op_59d8_20_nf;
+extern cpuop_func op_59d8_20_ff;
+extern cpuop_func op_59e0_20_nf;
+extern cpuop_func op_59e0_20_ff;
+extern cpuop_func op_59e8_20_nf;
+extern cpuop_func op_59e8_20_ff;
+extern cpuop_func op_59f0_20_nf;
+extern cpuop_func op_59f0_20_ff;
+extern cpuop_func op_59f8_20_nf;
+extern cpuop_func op_59f8_20_ff;
+extern cpuop_func op_59f9_20_nf;
+extern cpuop_func op_59f9_20_ff;
+extern cpuop_func op_59fa_20_nf;
+extern cpuop_func op_59fa_20_ff;
+extern cpuop_func op_59fb_20_nf;
+extern cpuop_func op_59fb_20_ff;
+extern cpuop_func op_59fc_20_nf;
+extern cpuop_func op_59fc_20_ff;
+extern cpuop_func op_5ac0_20_nf;
+extern cpuop_func op_5ac0_20_ff;
+extern cpuop_func op_5ac8_20_nf;
+extern cpuop_func op_5ac8_20_ff;
+extern cpuop_func op_5ad0_20_nf;
+extern cpuop_func op_5ad0_20_ff;
+extern cpuop_func op_5ad8_20_nf;
+extern cpuop_func op_5ad8_20_ff;
+extern cpuop_func op_5ae0_20_nf;
+extern cpuop_func op_5ae0_20_ff;
+extern cpuop_func op_5ae8_20_nf;
+extern cpuop_func op_5ae8_20_ff;
+extern cpuop_func op_5af0_20_nf;
+extern cpuop_func op_5af0_20_ff;
+extern cpuop_func op_5af8_20_nf;
+extern cpuop_func op_5af8_20_ff;
+extern cpuop_func op_5af9_20_nf;
+extern cpuop_func op_5af9_20_ff;
+extern cpuop_func op_5afa_20_nf;
+extern cpuop_func op_5afa_20_ff;
+extern cpuop_func op_5afb_20_nf;
+extern cpuop_func op_5afb_20_ff;
+extern cpuop_func op_5afc_20_nf;
+extern cpuop_func op_5afc_20_ff;
+extern cpuop_func op_5bc0_20_nf;
+extern cpuop_func op_5bc0_20_ff;
+extern cpuop_func op_5bc8_20_nf;
+extern cpuop_func op_5bc8_20_ff;
+extern cpuop_func op_5bd0_20_nf;
+extern cpuop_func op_5bd0_20_ff;
+extern cpuop_func op_5bd8_20_nf;
+extern cpuop_func op_5bd8_20_ff;
+extern cpuop_func op_5be0_20_nf;
+extern cpuop_func op_5be0_20_ff;
+extern cpuop_func op_5be8_20_nf;
+extern cpuop_func op_5be8_20_ff;
+extern cpuop_func op_5bf0_20_nf;
+extern cpuop_func op_5bf0_20_ff;
+extern cpuop_func op_5bf8_20_nf;
+extern cpuop_func op_5bf8_20_ff;
+extern cpuop_func op_5bf9_20_nf;
+extern cpuop_func op_5bf9_20_ff;
+extern cpuop_func op_5bfa_20_nf;
+extern cpuop_func op_5bfa_20_ff;
+extern cpuop_func op_5bfb_20_nf;
+extern cpuop_func op_5bfb_20_ff;
+extern cpuop_func op_5bfc_20_nf;
+extern cpuop_func op_5bfc_20_ff;
+extern cpuop_func op_5cc0_20_nf;
+extern cpuop_func op_5cc0_20_ff;
+extern cpuop_func op_5cc8_20_nf;
+extern cpuop_func op_5cc8_20_ff;
+extern cpuop_func op_5cd0_20_nf;
+extern cpuop_func op_5cd0_20_ff;
+extern cpuop_func op_5cd8_20_nf;
+extern cpuop_func op_5cd8_20_ff;
+extern cpuop_func op_5ce0_20_nf;
+extern cpuop_func op_5ce0_20_ff;
+extern cpuop_func op_5ce8_20_nf;
+extern cpuop_func op_5ce8_20_ff;
+extern cpuop_func op_5cf0_20_nf;
+extern cpuop_func op_5cf0_20_ff;
+extern cpuop_func op_5cf8_20_nf;
+extern cpuop_func op_5cf8_20_ff;
+extern cpuop_func op_5cf9_20_nf;
+extern cpuop_func op_5cf9_20_ff;
+extern cpuop_func op_5cfa_20_nf;
+extern cpuop_func op_5cfa_20_ff;
+extern cpuop_func op_5cfb_20_nf;
+extern cpuop_func op_5cfb_20_ff;
+extern cpuop_func op_5cfc_20_nf;
+extern cpuop_func op_5cfc_20_ff;
+extern cpuop_func op_5dc0_20_nf;
+extern cpuop_func op_5dc0_20_ff;
+extern cpuop_func op_5dc8_20_nf;
+extern cpuop_func op_5dc8_20_ff;
+extern cpuop_func op_5dd0_20_nf;
+extern cpuop_func op_5dd0_20_ff;
+extern cpuop_func op_5dd8_20_nf;
+extern cpuop_func op_5dd8_20_ff;
+extern cpuop_func op_5de0_20_nf;
+extern cpuop_func op_5de0_20_ff;
+extern cpuop_func op_5de8_20_nf;
+extern cpuop_func op_5de8_20_ff;
+extern cpuop_func op_5df0_20_nf;
+extern cpuop_func op_5df0_20_ff;
+extern cpuop_func op_5df8_20_nf;
+extern cpuop_func op_5df8_20_ff;
+extern cpuop_func op_5df9_20_nf;
+extern cpuop_func op_5df9_20_ff;
+extern cpuop_func op_5dfa_20_nf;
+extern cpuop_func op_5dfa_20_ff;
+extern cpuop_func op_5dfb_20_nf;
+extern cpuop_func op_5dfb_20_ff;
+extern cpuop_func op_5dfc_20_nf;
+extern cpuop_func op_5dfc_20_ff;
+extern cpuop_func op_5ec0_20_nf;
+extern cpuop_func op_5ec0_20_ff;
+extern cpuop_func op_5ec8_20_nf;
+extern cpuop_func op_5ec8_20_ff;
+extern cpuop_func op_5ed0_20_nf;
+extern cpuop_func op_5ed0_20_ff;
+extern cpuop_func op_5ed8_20_nf;
+extern cpuop_func op_5ed8_20_ff;
+extern cpuop_func op_5ee0_20_nf;
+extern cpuop_func op_5ee0_20_ff;
+extern cpuop_func op_5ee8_20_nf;
+extern cpuop_func op_5ee8_20_ff;
+extern cpuop_func op_5ef0_20_nf;
+extern cpuop_func op_5ef0_20_ff;
+extern cpuop_func op_5ef8_20_nf;
+extern cpuop_func op_5ef8_20_ff;
+extern cpuop_func op_5ef9_20_nf;
+extern cpuop_func op_5ef9_20_ff;
+extern cpuop_func op_5efa_20_nf;
+extern cpuop_func op_5efa_20_ff;
+extern cpuop_func op_5efb_20_nf;
+extern cpuop_func op_5efb_20_ff;
+extern cpuop_func op_5efc_20_nf;
+extern cpuop_func op_5efc_20_ff;
+extern cpuop_func op_5fc0_20_nf;
+extern cpuop_func op_5fc0_20_ff;
+extern cpuop_func op_5fc8_20_nf;
+extern cpuop_func op_5fc8_20_ff;
+extern cpuop_func op_5fd0_20_nf;
+extern cpuop_func op_5fd0_20_ff;
+extern cpuop_func op_5fd8_20_nf;
+extern cpuop_func op_5fd8_20_ff;
+extern cpuop_func op_5fe0_20_nf;
+extern cpuop_func op_5fe0_20_ff;
+extern cpuop_func op_5fe8_20_nf;
+extern cpuop_func op_5fe8_20_ff;
+extern cpuop_func op_5ff0_20_nf;
+extern cpuop_func op_5ff0_20_ff;
+extern cpuop_func op_5ff8_20_nf;
+extern cpuop_func op_5ff8_20_ff;
+extern cpuop_func op_5ff9_20_nf;
+extern cpuop_func op_5ff9_20_ff;
+extern cpuop_func op_5ffa_20_nf;
+extern cpuop_func op_5ffa_20_ff;
+extern cpuop_func op_5ffb_20_nf;
+extern cpuop_func op_5ffb_20_ff;
+extern cpuop_func op_5ffc_20_nf;
+extern cpuop_func op_5ffc_20_ff;
+extern cpuop_func op_6000_20_nf;
+extern cpuop_func op_6000_20_ff;
+extern cpuop_func op_6001_20_nf;
+extern cpuop_func op_6001_20_ff;
+extern cpuop_func op_60ff_20_nf;
+extern cpuop_func op_60ff_20_ff;
+extern cpuop_func op_6100_20_nf;
+extern cpuop_func op_6100_20_ff;
+extern cpuop_func op_6101_20_nf;
+extern cpuop_func op_6101_20_ff;
+extern cpuop_func op_61ff_20_nf;
+extern cpuop_func op_61ff_20_ff;
+extern cpuop_func op_6200_20_nf;
+extern cpuop_func op_6200_20_ff;
+extern cpuop_func op_6201_20_nf;
+extern cpuop_func op_6201_20_ff;
+extern cpuop_func op_62ff_20_nf;
+extern cpuop_func op_62ff_20_ff;
+extern cpuop_func op_6300_20_nf;
+extern cpuop_func op_6300_20_ff;
+extern cpuop_func op_6301_20_nf;
+extern cpuop_func op_6301_20_ff;
+extern cpuop_func op_63ff_20_nf;
+extern cpuop_func op_63ff_20_ff;
+extern cpuop_func op_6400_20_nf;
+extern cpuop_func op_6400_20_ff;
+extern cpuop_func op_6401_20_nf;
+extern cpuop_func op_6401_20_ff;
+extern cpuop_func op_64ff_20_nf;
+extern cpuop_func op_64ff_20_ff;
+extern cpuop_func op_6500_20_nf;
+extern cpuop_func op_6500_20_ff;
+extern cpuop_func op_6501_20_nf;
+extern cpuop_func op_6501_20_ff;
+extern cpuop_func op_65ff_20_nf;
+extern cpuop_func op_65ff_20_ff;
+extern cpuop_func op_6600_20_nf;
+extern cpuop_func op_6600_20_ff;
+extern cpuop_func op_6601_20_nf;
+extern cpuop_func op_6601_20_ff;
+extern cpuop_func op_66ff_20_nf;
+extern cpuop_func op_66ff_20_ff;
+extern cpuop_func op_6700_20_nf;
+extern cpuop_func op_6700_20_ff;
+extern cpuop_func op_6701_20_nf;
+extern cpuop_func op_6701_20_ff;
+extern cpuop_func op_67ff_20_nf;
+extern cpuop_func op_67ff_20_ff;
+extern cpuop_func op_6800_20_nf;
+extern cpuop_func op_6800_20_ff;
+extern cpuop_func op_6801_20_nf;
+extern cpuop_func op_6801_20_ff;
+extern cpuop_func op_68ff_20_nf;
+extern cpuop_func op_68ff_20_ff;
+extern cpuop_func op_6900_20_nf;
+extern cpuop_func op_6900_20_ff;
+extern cpuop_func op_6901_20_nf;
+extern cpuop_func op_6901_20_ff;
+extern cpuop_func op_69ff_20_nf;
+extern cpuop_func op_69ff_20_ff;
+extern cpuop_func op_6a00_20_nf;
+extern cpuop_func op_6a00_20_ff;
+extern cpuop_func op_6a01_20_nf;
+extern cpuop_func op_6a01_20_ff;
+extern cpuop_func op_6aff_20_nf;
+extern cpuop_func op_6aff_20_ff;
+extern cpuop_func op_6b00_20_nf;
+extern cpuop_func op_6b00_20_ff;
+extern cpuop_func op_6b01_20_nf;
+extern cpuop_func op_6b01_20_ff;
+extern cpuop_func op_6bff_20_nf;
+extern cpuop_func op_6bff_20_ff;
+extern cpuop_func op_6c00_20_nf;
+extern cpuop_func op_6c00_20_ff;
+extern cpuop_func op_6c01_20_nf;
+extern cpuop_func op_6c01_20_ff;
+extern cpuop_func op_6cff_20_nf;
+extern cpuop_func op_6cff_20_ff;
+extern cpuop_func op_6d00_20_nf;
+extern cpuop_func op_6d00_20_ff;
+extern cpuop_func op_6d01_20_nf;
+extern cpuop_func op_6d01_20_ff;
+extern cpuop_func op_6dff_20_nf;
+extern cpuop_func op_6dff_20_ff;
+extern cpuop_func op_6e00_20_nf;
+extern cpuop_func op_6e00_20_ff;
+extern cpuop_func op_6e01_20_nf;
+extern cpuop_func op_6e01_20_ff;
+extern cpuop_func op_6eff_20_nf;
+extern cpuop_func op_6eff_20_ff;
+extern cpuop_func op_6f00_20_nf;
+extern cpuop_func op_6f00_20_ff;
+extern cpuop_func op_6f01_20_nf;
+extern cpuop_func op_6f01_20_ff;
+extern cpuop_func op_6fff_20_nf;
+extern cpuop_func op_6fff_20_ff;
+extern cpuop_func op_7000_20_nf;
+extern cpuop_func op_7000_20_ff;
+extern cpuop_func op_8000_20_nf;
+extern cpuop_func op_8000_20_ff;
+extern cpuop_func op_8010_20_nf;
+extern cpuop_func op_8010_20_ff;
+extern cpuop_func op_8018_20_nf;
+extern cpuop_func op_8018_20_ff;
+extern cpuop_func op_8020_20_nf;
+extern cpuop_func op_8020_20_ff;
+extern cpuop_func op_8028_20_nf;
+extern cpuop_func op_8028_20_ff;
+extern cpuop_func op_8030_20_nf;
+extern cpuop_func op_8030_20_ff;
+extern cpuop_func op_8038_20_nf;
+extern cpuop_func op_8038_20_ff;
+extern cpuop_func op_8039_20_nf;
+extern cpuop_func op_8039_20_ff;
+extern cpuop_func op_803a_20_nf;
+extern cpuop_func op_803a_20_ff;
+extern cpuop_func op_803b_20_nf;
+extern cpuop_func op_803b_20_ff;
+extern cpuop_func op_803c_20_nf;
+extern cpuop_func op_803c_20_ff;
+extern cpuop_func op_8040_20_nf;
+extern cpuop_func op_8040_20_ff;
+extern cpuop_func op_8050_20_nf;
+extern cpuop_func op_8050_20_ff;
+extern cpuop_func op_8058_20_nf;
+extern cpuop_func op_8058_20_ff;
+extern cpuop_func op_8060_20_nf;
+extern cpuop_func op_8060_20_ff;
+extern cpuop_func op_8068_20_nf;
+extern cpuop_func op_8068_20_ff;
+extern cpuop_func op_8070_20_nf;
+extern cpuop_func op_8070_20_ff;
+extern cpuop_func op_8078_20_nf;
+extern cpuop_func op_8078_20_ff;
+extern cpuop_func op_8079_20_nf;
+extern cpuop_func op_8079_20_ff;
+extern cpuop_func op_807a_20_nf;
+extern cpuop_func op_807a_20_ff;
+extern cpuop_func op_807b_20_nf;
+extern cpuop_func op_807b_20_ff;
+extern cpuop_func op_807c_20_nf;
+extern cpuop_func op_807c_20_ff;
+extern cpuop_func op_8080_20_nf;
+extern cpuop_func op_8080_20_ff;
+extern cpuop_func op_8090_20_nf;
+extern cpuop_func op_8090_20_ff;
+extern cpuop_func op_8098_20_nf;
+extern cpuop_func op_8098_20_ff;
+extern cpuop_func op_80a0_20_nf;
+extern cpuop_func op_80a0_20_ff;
+extern cpuop_func op_80a8_20_nf;
+extern cpuop_func op_80a8_20_ff;
+extern cpuop_func op_80b0_20_nf;
+extern cpuop_func op_80b0_20_ff;
+extern cpuop_func op_80b8_20_nf;
+extern cpuop_func op_80b8_20_ff;
+extern cpuop_func op_80b9_20_nf;
+extern cpuop_func op_80b9_20_ff;
+extern cpuop_func op_80ba_20_nf;
+extern cpuop_func op_80ba_20_ff;
+extern cpuop_func op_80bb_20_nf;
+extern cpuop_func op_80bb_20_ff;
+extern cpuop_func op_80bc_20_nf;
+extern cpuop_func op_80bc_20_ff;
+extern cpuop_func op_80c0_20_nf;
+extern cpuop_func op_80c0_20_ff;
+extern cpuop_func op_80d0_20_nf;
+extern cpuop_func op_80d0_20_ff;
+extern cpuop_func op_80d8_20_nf;
+extern cpuop_func op_80d8_20_ff;
+extern cpuop_func op_80e0_20_nf;
+extern cpuop_func op_80e0_20_ff;
+extern cpuop_func op_80e8_20_nf;
+extern cpuop_func op_80e8_20_ff;
+extern cpuop_func op_80f0_20_nf;
+extern cpuop_func op_80f0_20_ff;
+extern cpuop_func op_80f8_20_nf;
+extern cpuop_func op_80f8_20_ff;
+extern cpuop_func op_80f9_20_nf;
+extern cpuop_func op_80f9_20_ff;
+extern cpuop_func op_80fa_20_nf;
+extern cpuop_func op_80fa_20_ff;
+extern cpuop_func op_80fb_20_nf;
+extern cpuop_func op_80fb_20_ff;
+extern cpuop_func op_80fc_20_nf;
+extern cpuop_func op_80fc_20_ff;
+extern cpuop_func op_8100_20_nf;
+extern cpuop_func op_8100_20_ff;
+extern cpuop_func op_8108_20_nf;
+extern cpuop_func op_8108_20_ff;
+extern cpuop_func op_8110_20_nf;
+extern cpuop_func op_8110_20_ff;
+extern cpuop_func op_8118_20_nf;
+extern cpuop_func op_8118_20_ff;
+extern cpuop_func op_8120_20_nf;
+extern cpuop_func op_8120_20_ff;
+extern cpuop_func op_8128_20_nf;
+extern cpuop_func op_8128_20_ff;
+extern cpuop_func op_8130_20_nf;
+extern cpuop_func op_8130_20_ff;
+extern cpuop_func op_8138_20_nf;
+extern cpuop_func op_8138_20_ff;
+extern cpuop_func op_8139_20_nf;
+extern cpuop_func op_8139_20_ff;
+extern cpuop_func op_8140_20_nf;
+extern cpuop_func op_8140_20_ff;
+extern cpuop_func op_8148_20_nf;
+extern cpuop_func op_8148_20_ff;
+extern cpuop_func op_8150_20_nf;
+extern cpuop_func op_8150_20_ff;
+extern cpuop_func op_8158_20_nf;
+extern cpuop_func op_8158_20_ff;
+extern cpuop_func op_8160_20_nf;
+extern cpuop_func op_8160_20_ff;
+extern cpuop_func op_8168_20_nf;
+extern cpuop_func op_8168_20_ff;
+extern cpuop_func op_8170_20_nf;
+extern cpuop_func op_8170_20_ff;
+extern cpuop_func op_8178_20_nf;
+extern cpuop_func op_8178_20_ff;
+extern cpuop_func op_8179_20_nf;
+extern cpuop_func op_8179_20_ff;
+extern cpuop_func op_8180_20_nf;
+extern cpuop_func op_8180_20_ff;
+extern cpuop_func op_8188_20_nf;
+extern cpuop_func op_8188_20_ff;
+extern cpuop_func op_8190_20_nf;
+extern cpuop_func op_8190_20_ff;
+extern cpuop_func op_8198_20_nf;
+extern cpuop_func op_8198_20_ff;
+extern cpuop_func op_81a0_20_nf;
+extern cpuop_func op_81a0_20_ff;
+extern cpuop_func op_81a8_20_nf;
+extern cpuop_func op_81a8_20_ff;
+extern cpuop_func op_81b0_20_nf;
+extern cpuop_func op_81b0_20_ff;
+extern cpuop_func op_81b8_20_nf;
+extern cpuop_func op_81b8_20_ff;
+extern cpuop_func op_81b9_20_nf;
+extern cpuop_func op_81b9_20_ff;
+extern cpuop_func op_81c0_20_nf;
+extern cpuop_func op_81c0_20_ff;
+extern cpuop_func op_81d0_20_nf;
+extern cpuop_func op_81d0_20_ff;
+extern cpuop_func op_81d8_20_nf;
+extern cpuop_func op_81d8_20_ff;
+extern cpuop_func op_81e0_20_nf;
+extern cpuop_func op_81e0_20_ff;
+extern cpuop_func op_81e8_20_nf;
+extern cpuop_func op_81e8_20_ff;
+extern cpuop_func op_81f0_20_nf;
+extern cpuop_func op_81f0_20_ff;
+extern cpuop_func op_81f8_20_nf;
+extern cpuop_func op_81f8_20_ff;
+extern cpuop_func op_81f9_20_nf;
+extern cpuop_func op_81f9_20_ff;
+extern cpuop_func op_81fa_20_nf;
+extern cpuop_func op_81fa_20_ff;
+extern cpuop_func op_81fb_20_nf;
+extern cpuop_func op_81fb_20_ff;
+extern cpuop_func op_81fc_20_nf;
+extern cpuop_func op_81fc_20_ff;
+extern cpuop_func op_9000_20_nf;
+extern cpuop_func op_9000_20_ff;
+extern cpuop_func op_9010_20_nf;
+extern cpuop_func op_9010_20_ff;
+extern cpuop_func op_9018_20_nf;
+extern cpuop_func op_9018_20_ff;
+extern cpuop_func op_9020_20_nf;
+extern cpuop_func op_9020_20_ff;
+extern cpuop_func op_9028_20_nf;
+extern cpuop_func op_9028_20_ff;
+extern cpuop_func op_9030_20_nf;
+extern cpuop_func op_9030_20_ff;
+extern cpuop_func op_9038_20_nf;
+extern cpuop_func op_9038_20_ff;
+extern cpuop_func op_9039_20_nf;
+extern cpuop_func op_9039_20_ff;
+extern cpuop_func op_903a_20_nf;
+extern cpuop_func op_903a_20_ff;
+extern cpuop_func op_903b_20_nf;
+extern cpuop_func op_903b_20_ff;
+extern cpuop_func op_903c_20_nf;
+extern cpuop_func op_903c_20_ff;
+extern cpuop_func op_9040_20_nf;
+extern cpuop_func op_9040_20_ff;
+extern cpuop_func op_9048_20_nf;
+extern cpuop_func op_9048_20_ff;
+extern cpuop_func op_9050_20_nf;
+extern cpuop_func op_9050_20_ff;
+extern cpuop_func op_9058_20_nf;
+extern cpuop_func op_9058_20_ff;
+extern cpuop_func op_9060_20_nf;
+extern cpuop_func op_9060_20_ff;
+extern cpuop_func op_9068_20_nf;
+extern cpuop_func op_9068_20_ff;
+extern cpuop_func op_9070_20_nf;
+extern cpuop_func op_9070_20_ff;
+extern cpuop_func op_9078_20_nf;
+extern cpuop_func op_9078_20_ff;
+extern cpuop_func op_9079_20_nf;
+extern cpuop_func op_9079_20_ff;
+extern cpuop_func op_907a_20_nf;
+extern cpuop_func op_907a_20_ff;
+extern cpuop_func op_907b_20_nf;
+extern cpuop_func op_907b_20_ff;
+extern cpuop_func op_907c_20_nf;
+extern cpuop_func op_907c_20_ff;
+extern cpuop_func op_9080_20_nf;
+extern cpuop_func op_9080_20_ff;
+extern cpuop_func op_9088_20_nf;
+extern cpuop_func op_9088_20_ff;
+extern cpuop_func op_9090_20_nf;
+extern cpuop_func op_9090_20_ff;
+extern cpuop_func op_9098_20_nf;
+extern cpuop_func op_9098_20_ff;
+extern cpuop_func op_90a0_20_nf;
+extern cpuop_func op_90a0_20_ff;
+extern cpuop_func op_90a8_20_nf;
+extern cpuop_func op_90a8_20_ff;
+extern cpuop_func op_90b0_20_nf;
+extern cpuop_func op_90b0_20_ff;
+extern cpuop_func op_90b8_20_nf;
+extern cpuop_func op_90b8_20_ff;
+extern cpuop_func op_90b9_20_nf;
+extern cpuop_func op_90b9_20_ff;
+extern cpuop_func op_90ba_20_nf;
+extern cpuop_func op_90ba_20_ff;
+extern cpuop_func op_90bb_20_nf;
+extern cpuop_func op_90bb_20_ff;
+extern cpuop_func op_90bc_20_nf;
+extern cpuop_func op_90bc_20_ff;
+extern cpuop_func op_90c0_20_nf;
+extern cpuop_func op_90c0_20_ff;
+extern cpuop_func op_90c8_20_nf;
+extern cpuop_func op_90c8_20_ff;
+extern cpuop_func op_90d0_20_nf;
+extern cpuop_func op_90d0_20_ff;
+extern cpuop_func op_90d8_20_nf;
+extern cpuop_func op_90d8_20_ff;
+extern cpuop_func op_90e0_20_nf;
+extern cpuop_func op_90e0_20_ff;
+extern cpuop_func op_90e8_20_nf;
+extern cpuop_func op_90e8_20_ff;
+extern cpuop_func op_90f0_20_nf;
+extern cpuop_func op_90f0_20_ff;
+extern cpuop_func op_90f8_20_nf;
+extern cpuop_func op_90f8_20_ff;
+extern cpuop_func op_90f9_20_nf;
+extern cpuop_func op_90f9_20_ff;
+extern cpuop_func op_90fa_20_nf;
+extern cpuop_func op_90fa_20_ff;
+extern cpuop_func op_90fb_20_nf;
+extern cpuop_func op_90fb_20_ff;
+extern cpuop_func op_90fc_20_nf;
+extern cpuop_func op_90fc_20_ff;
+extern cpuop_func op_9100_20_nf;
+extern cpuop_func op_9100_20_ff;
+extern cpuop_func op_9108_20_nf;
+extern cpuop_func op_9108_20_ff;
+extern cpuop_func op_9110_20_nf;
+extern cpuop_func op_9110_20_ff;
+extern cpuop_func op_9118_20_nf;
+extern cpuop_func op_9118_20_ff;
+extern cpuop_func op_9120_20_nf;
+extern cpuop_func op_9120_20_ff;
+extern cpuop_func op_9128_20_nf;
+extern cpuop_func op_9128_20_ff;
+extern cpuop_func op_9130_20_nf;
+extern cpuop_func op_9130_20_ff;
+extern cpuop_func op_9138_20_nf;
+extern cpuop_func op_9138_20_ff;
+extern cpuop_func op_9139_20_nf;
+extern cpuop_func op_9139_20_ff;
+extern cpuop_func op_9140_20_nf;
+extern cpuop_func op_9140_20_ff;
+extern cpuop_func op_9148_20_nf;
+extern cpuop_func op_9148_20_ff;
+extern cpuop_func op_9150_20_nf;
+extern cpuop_func op_9150_20_ff;
+extern cpuop_func op_9158_20_nf;
+extern cpuop_func op_9158_20_ff;
+extern cpuop_func op_9160_20_nf;
+extern cpuop_func op_9160_20_ff;
+extern cpuop_func op_9168_20_nf;
+extern cpuop_func op_9168_20_ff;
+extern cpuop_func op_9170_20_nf;
+extern cpuop_func op_9170_20_ff;
+extern cpuop_func op_9178_20_nf;
+extern cpuop_func op_9178_20_ff;
+extern cpuop_func op_9179_20_nf;
+extern cpuop_func op_9179_20_ff;
+extern cpuop_func op_9180_20_nf;
+extern cpuop_func op_9180_20_ff;
+extern cpuop_func op_9188_20_nf;
+extern cpuop_func op_9188_20_ff;
+extern cpuop_func op_9190_20_nf;
+extern cpuop_func op_9190_20_ff;
+extern cpuop_func op_9198_20_nf;
+extern cpuop_func op_9198_20_ff;
+extern cpuop_func op_91a0_20_nf;
+extern cpuop_func op_91a0_20_ff;
+extern cpuop_func op_91a8_20_nf;
+extern cpuop_func op_91a8_20_ff;
+extern cpuop_func op_91b0_20_nf;
+extern cpuop_func op_91b0_20_ff;
+extern cpuop_func op_91b8_20_nf;
+extern cpuop_func op_91b8_20_ff;
+extern cpuop_func op_91b9_20_nf;
+extern cpuop_func op_91b9_20_ff;
+extern cpuop_func op_91c0_20_nf;
+extern cpuop_func op_91c0_20_ff;
+extern cpuop_func op_91c8_20_nf;
+extern cpuop_func op_91c8_20_ff;
+extern cpuop_func op_91d0_20_nf;
+extern cpuop_func op_91d0_20_ff;
+extern cpuop_func op_91d8_20_nf;
+extern cpuop_func op_91d8_20_ff;
+extern cpuop_func op_91e0_20_nf;
+extern cpuop_func op_91e0_20_ff;
+extern cpuop_func op_91e8_20_nf;
+extern cpuop_func op_91e8_20_ff;
+extern cpuop_func op_91f0_20_nf;
+extern cpuop_func op_91f0_20_ff;
+extern cpuop_func op_91f8_20_nf;
+extern cpuop_func op_91f8_20_ff;
+extern cpuop_func op_91f9_20_nf;
+extern cpuop_func op_91f9_20_ff;
+extern cpuop_func op_91fa_20_nf;
+extern cpuop_func op_91fa_20_ff;
+extern cpuop_func op_91fb_20_nf;
+extern cpuop_func op_91fb_20_ff;
+extern cpuop_func op_91fc_20_nf;
+extern cpuop_func op_91fc_20_ff;
+extern cpuop_func op_b000_20_nf;
+extern cpuop_func op_b000_20_ff;
+extern cpuop_func op_b010_20_nf;
+extern cpuop_func op_b010_20_ff;
+extern cpuop_func op_b018_20_nf;
+extern cpuop_func op_b018_20_ff;
+extern cpuop_func op_b020_20_nf;
+extern cpuop_func op_b020_20_ff;
+extern cpuop_func op_b028_20_nf;
+extern cpuop_func op_b028_20_ff;
+extern cpuop_func op_b030_20_nf;
+extern cpuop_func op_b030_20_ff;
+extern cpuop_func op_b038_20_nf;
+extern cpuop_func op_b038_20_ff;
+extern cpuop_func op_b039_20_nf;
+extern cpuop_func op_b039_20_ff;
+extern cpuop_func op_b03a_20_nf;
+extern cpuop_func op_b03a_20_ff;
+extern cpuop_func op_b03b_20_nf;
+extern cpuop_func op_b03b_20_ff;
+extern cpuop_func op_b03c_20_nf;
+extern cpuop_func op_b03c_20_ff;
+extern cpuop_func op_b040_20_nf;
+extern cpuop_func op_b040_20_ff;
+extern cpuop_func op_b048_20_nf;
+extern cpuop_func op_b048_20_ff;
+extern cpuop_func op_b050_20_nf;
+extern cpuop_func op_b050_20_ff;
+extern cpuop_func op_b058_20_nf;
+extern cpuop_func op_b058_20_ff;
+extern cpuop_func op_b060_20_nf;
+extern cpuop_func op_b060_20_ff;
+extern cpuop_func op_b068_20_nf;
+extern cpuop_func op_b068_20_ff;
+extern cpuop_func op_b070_20_nf;
+extern cpuop_func op_b070_20_ff;
+extern cpuop_func op_b078_20_nf;
+extern cpuop_func op_b078_20_ff;
+extern cpuop_func op_b079_20_nf;
+extern cpuop_func op_b079_20_ff;
+extern cpuop_func op_b07a_20_nf;
+extern cpuop_func op_b07a_20_ff;
+extern cpuop_func op_b07b_20_nf;
+extern cpuop_func op_b07b_20_ff;
+extern cpuop_func op_b07c_20_nf;
+extern cpuop_func op_b07c_20_ff;
+extern cpuop_func op_b080_20_nf;
+extern cpuop_func op_b080_20_ff;
+extern cpuop_func op_b088_20_nf;
+extern cpuop_func op_b088_20_ff;
+extern cpuop_func op_b090_20_nf;
+extern cpuop_func op_b090_20_ff;
+extern cpuop_func op_b098_20_nf;
+extern cpuop_func op_b098_20_ff;
+extern cpuop_func op_b0a0_20_nf;
+extern cpuop_func op_b0a0_20_ff;
+extern cpuop_func op_b0a8_20_nf;
+extern cpuop_func op_b0a8_20_ff;
+extern cpuop_func op_b0b0_20_nf;
+extern cpuop_func op_b0b0_20_ff;
+extern cpuop_func op_b0b8_20_nf;
+extern cpuop_func op_b0b8_20_ff;
+extern cpuop_func op_b0b9_20_nf;
+extern cpuop_func op_b0b9_20_ff;
+extern cpuop_func op_b0ba_20_nf;
+extern cpuop_func op_b0ba_20_ff;
+extern cpuop_func op_b0bb_20_nf;
+extern cpuop_func op_b0bb_20_ff;
+extern cpuop_func op_b0bc_20_nf;
+extern cpuop_func op_b0bc_20_ff;
+extern cpuop_func op_b0c0_20_nf;
+extern cpuop_func op_b0c0_20_ff;
+extern cpuop_func op_b0c8_20_nf;
+extern cpuop_func op_b0c8_20_ff;
+extern cpuop_func op_b0d0_20_nf;
+extern cpuop_func op_b0d0_20_ff;
+extern cpuop_func op_b0d8_20_nf;
+extern cpuop_func op_b0d8_20_ff;
+extern cpuop_func op_b0e0_20_nf;
+extern cpuop_func op_b0e0_20_ff;
+extern cpuop_func op_b0e8_20_nf;
+extern cpuop_func op_b0e8_20_ff;
+extern cpuop_func op_b0f0_20_nf;
+extern cpuop_func op_b0f0_20_ff;
+extern cpuop_func op_b0f8_20_nf;
+extern cpuop_func op_b0f8_20_ff;
+extern cpuop_func op_b0f9_20_nf;
+extern cpuop_func op_b0f9_20_ff;
+extern cpuop_func op_b0fa_20_nf;
+extern cpuop_func op_b0fa_20_ff;
+extern cpuop_func op_b0fb_20_nf;
+extern cpuop_func op_b0fb_20_ff;
+extern cpuop_func op_b0fc_20_nf;
+extern cpuop_func op_b0fc_20_ff;
+extern cpuop_func op_b100_20_nf;
+extern cpuop_func op_b100_20_ff;
+extern cpuop_func op_b108_20_nf;
+extern cpuop_func op_b108_20_ff;
+extern cpuop_func op_b110_20_nf;
+extern cpuop_func op_b110_20_ff;
+extern cpuop_func op_b118_20_nf;
+extern cpuop_func op_b118_20_ff;
+extern cpuop_func op_b120_20_nf;
+extern cpuop_func op_b120_20_ff;
+extern cpuop_func op_b128_20_nf;
+extern cpuop_func op_b128_20_ff;
+extern cpuop_func op_b130_20_nf;
+extern cpuop_func op_b130_20_ff;
+extern cpuop_func op_b138_20_nf;
+extern cpuop_func op_b138_20_ff;
+extern cpuop_func op_b139_20_nf;
+extern cpuop_func op_b139_20_ff;
+extern cpuop_func op_b140_20_nf;
+extern cpuop_func op_b140_20_ff;
+extern cpuop_func op_b148_20_nf;
+extern cpuop_func op_b148_20_ff;
+extern cpuop_func op_b150_20_nf;
+extern cpuop_func op_b150_20_ff;
+extern cpuop_func op_b158_20_nf;
+extern cpuop_func op_b158_20_ff;
+extern cpuop_func op_b160_20_nf;
+extern cpuop_func op_b160_20_ff;
+extern cpuop_func op_b168_20_nf;
+extern cpuop_func op_b168_20_ff;
+extern cpuop_func op_b170_20_nf;
+extern cpuop_func op_b170_20_ff;
+extern cpuop_func op_b178_20_nf;
+extern cpuop_func op_b178_20_ff;
+extern cpuop_func op_b179_20_nf;
+extern cpuop_func op_b179_20_ff;
+extern cpuop_func op_b180_20_nf;
+extern cpuop_func op_b180_20_ff;
+extern cpuop_func op_b188_20_nf;
+extern cpuop_func op_b188_20_ff;
+extern cpuop_func op_b190_20_nf;
+extern cpuop_func op_b190_20_ff;
+extern cpuop_func op_b198_20_nf;
+extern cpuop_func op_b198_20_ff;
+extern cpuop_func op_b1a0_20_nf;
+extern cpuop_func op_b1a0_20_ff;
+extern cpuop_func op_b1a8_20_nf;
+extern cpuop_func op_b1a8_20_ff;
+extern cpuop_func op_b1b0_20_nf;
+extern cpuop_func op_b1b0_20_ff;
+extern cpuop_func op_b1b8_20_nf;
+extern cpuop_func op_b1b8_20_ff;
+extern cpuop_func op_b1b9_20_nf;
+extern cpuop_func op_b1b9_20_ff;
+extern cpuop_func op_b1c0_20_nf;
+extern cpuop_func op_b1c0_20_ff;
+extern cpuop_func op_b1c8_20_nf;
+extern cpuop_func op_b1c8_20_ff;
+extern cpuop_func op_b1d0_20_nf;
+extern cpuop_func op_b1d0_20_ff;
+extern cpuop_func op_b1d8_20_nf;
+extern cpuop_func op_b1d8_20_ff;
+extern cpuop_func op_b1e0_20_nf;
+extern cpuop_func op_b1e0_20_ff;
+extern cpuop_func op_b1e8_20_nf;
+extern cpuop_func op_b1e8_20_ff;
+extern cpuop_func op_b1f0_20_nf;
+extern cpuop_func op_b1f0_20_ff;
+extern cpuop_func op_b1f8_20_nf;
+extern cpuop_func op_b1f8_20_ff;
+extern cpuop_func op_b1f9_20_nf;
+extern cpuop_func op_b1f9_20_ff;
+extern cpuop_func op_b1fa_20_nf;
+extern cpuop_func op_b1fa_20_ff;
+extern cpuop_func op_b1fb_20_nf;
+extern cpuop_func op_b1fb_20_ff;
+extern cpuop_func op_b1fc_20_nf;
+extern cpuop_func op_b1fc_20_ff;
+extern cpuop_func op_c000_20_nf;
+extern cpuop_func op_c000_20_ff;
+extern cpuop_func op_c010_20_nf;
+extern cpuop_func op_c010_20_ff;
+extern cpuop_func op_c018_20_nf;
+extern cpuop_func op_c018_20_ff;
+extern cpuop_func op_c020_20_nf;
+extern cpuop_func op_c020_20_ff;
+extern cpuop_func op_c028_20_nf;
+extern cpuop_func op_c028_20_ff;
+extern cpuop_func op_c030_20_nf;
+extern cpuop_func op_c030_20_ff;
+extern cpuop_func op_c038_20_nf;
+extern cpuop_func op_c038_20_ff;
+extern cpuop_func op_c039_20_nf;
+extern cpuop_func op_c039_20_ff;
+extern cpuop_func op_c03a_20_nf;
+extern cpuop_func op_c03a_20_ff;
+extern cpuop_func op_c03b_20_nf;
+extern cpuop_func op_c03b_20_ff;
+extern cpuop_func op_c03c_20_nf;
+extern cpuop_func op_c03c_20_ff;
+extern cpuop_func op_c040_20_nf;
+extern cpuop_func op_c040_20_ff;
+extern cpuop_func op_c050_20_nf;
+extern cpuop_func op_c050_20_ff;
+extern cpuop_func op_c058_20_nf;
+extern cpuop_func op_c058_20_ff;
+extern cpuop_func op_c060_20_nf;
+extern cpuop_func op_c060_20_ff;
+extern cpuop_func op_c068_20_nf;
+extern cpuop_func op_c068_20_ff;
+extern cpuop_func op_c070_20_nf;
+extern cpuop_func op_c070_20_ff;
+extern cpuop_func op_c078_20_nf;
+extern cpuop_func op_c078_20_ff;
+extern cpuop_func op_c079_20_nf;
+extern cpuop_func op_c079_20_ff;
+extern cpuop_func op_c07a_20_nf;
+extern cpuop_func op_c07a_20_ff;
+extern cpuop_func op_c07b_20_nf;
+extern cpuop_func op_c07b_20_ff;
+extern cpuop_func op_c07c_20_nf;
+extern cpuop_func op_c07c_20_ff;
+extern cpuop_func op_c080_20_nf;
+extern cpuop_func op_c080_20_ff;
+extern cpuop_func op_c090_20_nf;
+extern cpuop_func op_c090_20_ff;
+extern cpuop_func op_c098_20_nf;
+extern cpuop_func op_c098_20_ff;
+extern cpuop_func op_c0a0_20_nf;
+extern cpuop_func op_c0a0_20_ff;
+extern cpuop_func op_c0a8_20_nf;
+extern cpuop_func op_c0a8_20_ff;
+extern cpuop_func op_c0b0_20_nf;
+extern cpuop_func op_c0b0_20_ff;
+extern cpuop_func op_c0b8_20_nf;
+extern cpuop_func op_c0b8_20_ff;
+extern cpuop_func op_c0b9_20_nf;
+extern cpuop_func op_c0b9_20_ff;
+extern cpuop_func op_c0ba_20_nf;
+extern cpuop_func op_c0ba_20_ff;
+extern cpuop_func op_c0bb_20_nf;
+extern cpuop_func op_c0bb_20_ff;
+extern cpuop_func op_c0bc_20_nf;
+extern cpuop_func op_c0bc_20_ff;
+extern cpuop_func op_c0c0_20_nf;
+extern cpuop_func op_c0c0_20_ff;
+extern cpuop_func op_c0d0_20_nf;
+extern cpuop_func op_c0d0_20_ff;
+extern cpuop_func op_c0d8_20_nf;
+extern cpuop_func op_c0d8_20_ff;
+extern cpuop_func op_c0e0_20_nf;
+extern cpuop_func op_c0e0_20_ff;
+extern cpuop_func op_c0e8_20_nf;
+extern cpuop_func op_c0e8_20_ff;
+extern cpuop_func op_c0f0_20_nf;
+extern cpuop_func op_c0f0_20_ff;
+extern cpuop_func op_c0f8_20_nf;
+extern cpuop_func op_c0f8_20_ff;
+extern cpuop_func op_c0f9_20_nf;
+extern cpuop_func op_c0f9_20_ff;
+extern cpuop_func op_c0fa_20_nf;
+extern cpuop_func op_c0fa_20_ff;
+extern cpuop_func op_c0fb_20_nf;
+extern cpuop_func op_c0fb_20_ff;
+extern cpuop_func op_c0fc_20_nf;
+extern cpuop_func op_c0fc_20_ff;
+extern cpuop_func op_c100_20_nf;
+extern cpuop_func op_c100_20_ff;
+extern cpuop_func op_c108_20_nf;
+extern cpuop_func op_c108_20_ff;
+extern cpuop_func op_c110_20_nf;
+extern cpuop_func op_c110_20_ff;
+extern cpuop_func op_c118_20_nf;
+extern cpuop_func op_c118_20_ff;
+extern cpuop_func op_c120_20_nf;
+extern cpuop_func op_c120_20_ff;
+extern cpuop_func op_c128_20_nf;
+extern cpuop_func op_c128_20_ff;
+extern cpuop_func op_c130_20_nf;
+extern cpuop_func op_c130_20_ff;
+extern cpuop_func op_c138_20_nf;
+extern cpuop_func op_c138_20_ff;
+extern cpuop_func op_c139_20_nf;
+extern cpuop_func op_c139_20_ff;
+extern cpuop_func op_c140_20_nf;
+extern cpuop_func op_c140_20_ff;
+extern cpuop_func op_c148_20_nf;
+extern cpuop_func op_c148_20_ff;
+extern cpuop_func op_c150_20_nf;
+extern cpuop_func op_c150_20_ff;
+extern cpuop_func op_c158_20_nf;
+extern cpuop_func op_c158_20_ff;
+extern cpuop_func op_c160_20_nf;
+extern cpuop_func op_c160_20_ff;
+extern cpuop_func op_c168_20_nf;
+extern cpuop_func op_c168_20_ff;
+extern cpuop_func op_c170_20_nf;
+extern cpuop_func op_c170_20_ff;
+extern cpuop_func op_c178_20_nf;
+extern cpuop_func op_c178_20_ff;
+extern cpuop_func op_c179_20_nf;
+extern cpuop_func op_c179_20_ff;
+extern cpuop_func op_c188_20_nf;
+extern cpuop_func op_c188_20_ff;
+extern cpuop_func op_c190_20_nf;
+extern cpuop_func op_c190_20_ff;
+extern cpuop_func op_c198_20_nf;
+extern cpuop_func op_c198_20_ff;
+extern cpuop_func op_c1a0_20_nf;
+extern cpuop_func op_c1a0_20_ff;
+extern cpuop_func op_c1a8_20_nf;
+extern cpuop_func op_c1a8_20_ff;
+extern cpuop_func op_c1b0_20_nf;
+extern cpuop_func op_c1b0_20_ff;
+extern cpuop_func op_c1b8_20_nf;
+extern cpuop_func op_c1b8_20_ff;
+extern cpuop_func op_c1b9_20_nf;
+extern cpuop_func op_c1b9_20_ff;
+extern cpuop_func op_c1c0_20_nf;
+extern cpuop_func op_c1c0_20_ff;
+extern cpuop_func op_c1d0_20_nf;
+extern cpuop_func op_c1d0_20_ff;
+extern cpuop_func op_c1d8_20_nf;
+extern cpuop_func op_c1d8_20_ff;
+extern cpuop_func op_c1e0_20_nf;
+extern cpuop_func op_c1e0_20_ff;
+extern cpuop_func op_c1e8_20_nf;
+extern cpuop_func op_c1e8_20_ff;
+extern cpuop_func op_c1f0_20_nf;
+extern cpuop_func op_c1f0_20_ff;
+extern cpuop_func op_c1f8_20_nf;
+extern cpuop_func op_c1f8_20_ff;
+extern cpuop_func op_c1f9_20_nf;
+extern cpuop_func op_c1f9_20_ff;
+extern cpuop_func op_c1fa_20_nf;
+extern cpuop_func op_c1fa_20_ff;
+extern cpuop_func op_c1fb_20_nf;
+extern cpuop_func op_c1fb_20_ff;
+extern cpuop_func op_c1fc_20_nf;
+extern cpuop_func op_c1fc_20_ff;
+extern cpuop_func op_d000_20_nf;
+extern cpuop_func op_d000_20_ff;
+extern cpuop_func op_d010_20_nf;
+extern cpuop_func op_d010_20_ff;
+extern cpuop_func op_d018_20_nf;
+extern cpuop_func op_d018_20_ff;
+extern cpuop_func op_d020_20_nf;
+extern cpuop_func op_d020_20_ff;
+extern cpuop_func op_d028_20_nf;
+extern cpuop_func op_d028_20_ff;
+extern cpuop_func op_d030_20_nf;
+extern cpuop_func op_d030_20_ff;
+extern cpuop_func op_d038_20_nf;
+extern cpuop_func op_d038_20_ff;
+extern cpuop_func op_d039_20_nf;
+extern cpuop_func op_d039_20_ff;
+extern cpuop_func op_d03a_20_nf;
+extern cpuop_func op_d03a_20_ff;
+extern cpuop_func op_d03b_20_nf;
+extern cpuop_func op_d03b_20_ff;
+extern cpuop_func op_d03c_20_nf;
+extern cpuop_func op_d03c_20_ff;
+extern cpuop_func op_d040_20_nf;
+extern cpuop_func op_d040_20_ff;
+extern cpuop_func op_d048_20_nf;
+extern cpuop_func op_d048_20_ff;
+extern cpuop_func op_d050_20_nf;
+extern cpuop_func op_d050_20_ff;
+extern cpuop_func op_d058_20_nf;
+extern cpuop_func op_d058_20_ff;
+extern cpuop_func op_d060_20_nf;
+extern cpuop_func op_d060_20_ff;
+extern cpuop_func op_d068_20_nf;
+extern cpuop_func op_d068_20_ff;
+extern cpuop_func op_d070_20_nf;
+extern cpuop_func op_d070_20_ff;
+extern cpuop_func op_d078_20_nf;
+extern cpuop_func op_d078_20_ff;
+extern cpuop_func op_d079_20_nf;
+extern cpuop_func op_d079_20_ff;
+extern cpuop_func op_d07a_20_nf;
+extern cpuop_func op_d07a_20_ff;
+extern cpuop_func op_d07b_20_nf;
+extern cpuop_func op_d07b_20_ff;
+extern cpuop_func op_d07c_20_nf;
+extern cpuop_func op_d07c_20_ff;
+extern cpuop_func op_d080_20_nf;
+extern cpuop_func op_d080_20_ff;
+extern cpuop_func op_d088_20_nf;
+extern cpuop_func op_d088_20_ff;
+extern cpuop_func op_d090_20_nf;
+extern cpuop_func op_d090_20_ff;
+extern cpuop_func op_d098_20_nf;
+extern cpuop_func op_d098_20_ff;
+extern cpuop_func op_d0a0_20_nf;
+extern cpuop_func op_d0a0_20_ff;
+extern cpuop_func op_d0a8_20_nf;
+extern cpuop_func op_d0a8_20_ff;
+extern cpuop_func op_d0b0_20_nf;
+extern cpuop_func op_d0b0_20_ff;
+extern cpuop_func op_d0b8_20_nf;
+extern cpuop_func op_d0b8_20_ff;
+extern cpuop_func op_d0b9_20_nf;
+extern cpuop_func op_d0b9_20_ff;
+extern cpuop_func op_d0ba_20_nf;
+extern cpuop_func op_d0ba_20_ff;
+extern cpuop_func op_d0bb_20_nf;
+extern cpuop_func op_d0bb_20_ff;
+extern cpuop_func op_d0bc_20_nf;
+extern cpuop_func op_d0bc_20_ff;
+extern cpuop_func op_d0c0_20_nf;
+extern cpuop_func op_d0c0_20_ff;
+extern cpuop_func op_d0c8_20_nf;
+extern cpuop_func op_d0c8_20_ff;
+extern cpuop_func op_d0d0_20_nf;
+extern cpuop_func op_d0d0_20_ff;
+extern cpuop_func op_d0d8_20_nf;
+extern cpuop_func op_d0d8_20_ff;
+extern cpuop_func op_d0e0_20_nf;
+extern cpuop_func op_d0e0_20_ff;
+extern cpuop_func op_d0e8_20_nf;
+extern cpuop_func op_d0e8_20_ff;
+extern cpuop_func op_d0f0_20_nf;
+extern cpuop_func op_d0f0_20_ff;
+extern cpuop_func op_d0f8_20_nf;
+extern cpuop_func op_d0f8_20_ff;
+extern cpuop_func op_d0f9_20_nf;
+extern cpuop_func op_d0f9_20_ff;
+extern cpuop_func op_d0fa_20_nf;
+extern cpuop_func op_d0fa_20_ff;
+extern cpuop_func op_d0fb_20_nf;
+extern cpuop_func op_d0fb_20_ff;
+extern cpuop_func op_d0fc_20_nf;
+extern cpuop_func op_d0fc_20_ff;
+extern cpuop_func op_d100_20_nf;
+extern cpuop_func op_d100_20_ff;
+extern cpuop_func op_d108_20_nf;
+extern cpuop_func op_d108_20_ff;
+extern cpuop_func op_d110_20_nf;
+extern cpuop_func op_d110_20_ff;
+extern cpuop_func op_d118_20_nf;
+extern cpuop_func op_d118_20_ff;
+extern cpuop_func op_d120_20_nf;
+extern cpuop_func op_d120_20_ff;
+extern cpuop_func op_d128_20_nf;
+extern cpuop_func op_d128_20_ff;
+extern cpuop_func op_d130_20_nf;
+extern cpuop_func op_d130_20_ff;
+extern cpuop_func op_d138_20_nf;
+extern cpuop_func op_d138_20_ff;
+extern cpuop_func op_d139_20_nf;
+extern cpuop_func op_d139_20_ff;
+extern cpuop_func op_d140_20_nf;
+extern cpuop_func op_d140_20_ff;
+extern cpuop_func op_d148_20_nf;
+extern cpuop_func op_d148_20_ff;
+extern cpuop_func op_d150_20_nf;
+extern cpuop_func op_d150_20_ff;
+extern cpuop_func op_d158_20_nf;
+extern cpuop_func op_d158_20_ff;
+extern cpuop_func op_d160_20_nf;
+extern cpuop_func op_d160_20_ff;
+extern cpuop_func op_d168_20_nf;
+extern cpuop_func op_d168_20_ff;
+extern cpuop_func op_d170_20_nf;
+extern cpuop_func op_d170_20_ff;
+extern cpuop_func op_d178_20_nf;
+extern cpuop_func op_d178_20_ff;
+extern cpuop_func op_d179_20_nf;
+extern cpuop_func op_d179_20_ff;
+extern cpuop_func op_d180_20_nf;
+extern cpuop_func op_d180_20_ff;
+extern cpuop_func op_d188_20_nf;
+extern cpuop_func op_d188_20_ff;
+extern cpuop_func op_d190_20_nf;
+extern cpuop_func op_d190_20_ff;
+extern cpuop_func op_d198_20_nf;
+extern cpuop_func op_d198_20_ff;
+extern cpuop_func op_d1a0_20_nf;
+extern cpuop_func op_d1a0_20_ff;
+extern cpuop_func op_d1a8_20_nf;
+extern cpuop_func op_d1a8_20_ff;
+extern cpuop_func op_d1b0_20_nf;
+extern cpuop_func op_d1b0_20_ff;
+extern cpuop_func op_d1b8_20_nf;
+extern cpuop_func op_d1b8_20_ff;
+extern cpuop_func op_d1b9_20_nf;
+extern cpuop_func op_d1b9_20_ff;
+extern cpuop_func op_d1c0_20_nf;
+extern cpuop_func op_d1c0_20_ff;
+extern cpuop_func op_d1c8_20_nf;
+extern cpuop_func op_d1c8_20_ff;
+extern cpuop_func op_d1d0_20_nf;
+extern cpuop_func op_d1d0_20_ff;
+extern cpuop_func op_d1d8_20_nf;
+extern cpuop_func op_d1d8_20_ff;
+extern cpuop_func op_d1e0_20_nf;
+extern cpuop_func op_d1e0_20_ff;
+extern cpuop_func op_d1e8_20_nf;
+extern cpuop_func op_d1e8_20_ff;
+extern cpuop_func op_d1f0_20_nf;
+extern cpuop_func op_d1f0_20_ff;
+extern cpuop_func op_d1f8_20_nf;
+extern cpuop_func op_d1f8_20_ff;
+extern cpuop_func op_d1f9_20_nf;
+extern cpuop_func op_d1f9_20_ff;
+extern cpuop_func op_d1fa_20_nf;
+extern cpuop_func op_d1fa_20_ff;
+extern cpuop_func op_d1fb_20_nf;
+extern cpuop_func op_d1fb_20_ff;
+extern cpuop_func op_d1fc_20_nf;
+extern cpuop_func op_d1fc_20_ff;
+extern cpuop_func op_e000_20_nf;
+extern cpuop_func op_e000_20_ff;
+extern cpuop_func op_e008_20_nf;
+extern cpuop_func op_e008_20_ff;
+extern cpuop_func op_e010_20_nf;
+extern cpuop_func op_e010_20_ff;
+extern cpuop_func op_e018_20_nf;
+extern cpuop_func op_e018_20_ff;
+extern cpuop_func op_e020_20_nf;
+extern cpuop_func op_e020_20_ff;
+extern cpuop_func op_e028_20_nf;
+extern cpuop_func op_e028_20_ff;
+extern cpuop_func op_e030_20_nf;
+extern cpuop_func op_e030_20_ff;
+extern cpuop_func op_e038_20_nf;
+extern cpuop_func op_e038_20_ff;
+extern cpuop_func op_e040_20_nf;
+extern cpuop_func op_e040_20_ff;
+extern cpuop_func op_e048_20_nf;
+extern cpuop_func op_e048_20_ff;
+extern cpuop_func op_e050_20_nf;
+extern cpuop_func op_e050_20_ff;
+extern cpuop_func op_e058_20_nf;
+extern cpuop_func op_e058_20_ff;
+extern cpuop_func op_e060_20_nf;
+extern cpuop_func op_e060_20_ff;
+extern cpuop_func op_e068_20_nf;
+extern cpuop_func op_e068_20_ff;
+extern cpuop_func op_e070_20_nf;
+extern cpuop_func op_e070_20_ff;
+extern cpuop_func op_e078_20_nf;
+extern cpuop_func op_e078_20_ff;
+extern cpuop_func op_e080_20_nf;
+extern cpuop_func op_e080_20_ff;
+extern cpuop_func op_e088_20_nf;
+extern cpuop_func op_e088_20_ff;
+extern cpuop_func op_e090_20_nf;
+extern cpuop_func op_e090_20_ff;
+extern cpuop_func op_e098_20_nf;
+extern cpuop_func op_e098_20_ff;
+extern cpuop_func op_e0a0_20_nf;
+extern cpuop_func op_e0a0_20_ff;
+extern cpuop_func op_e0a8_20_nf;
+extern cpuop_func op_e0a8_20_ff;
+extern cpuop_func op_e0b0_20_nf;
+extern cpuop_func op_e0b0_20_ff;
+extern cpuop_func op_e0b8_20_nf;
+extern cpuop_func op_e0b8_20_ff;
+extern cpuop_func op_e0d0_20_nf;
+extern cpuop_func op_e0d0_20_ff;
+extern cpuop_func op_e0d8_20_nf;
+extern cpuop_func op_e0d8_20_ff;
+extern cpuop_func op_e0e0_20_nf;
+extern cpuop_func op_e0e0_20_ff;
+extern cpuop_func op_e0e8_20_nf;
+extern cpuop_func op_e0e8_20_ff;
+extern cpuop_func op_e0f0_20_nf;
+extern cpuop_func op_e0f0_20_ff;
+extern cpuop_func op_e0f8_20_nf;
+extern cpuop_func op_e0f8_20_ff;
+extern cpuop_func op_e0f9_20_nf;
+extern cpuop_func op_e0f9_20_ff;
+extern cpuop_func op_e100_20_nf;
+extern cpuop_func op_e100_20_ff;
+extern cpuop_func op_e108_20_nf;
+extern cpuop_func op_e108_20_ff;
+extern cpuop_func op_e110_20_nf;
+extern cpuop_func op_e110_20_ff;
+extern cpuop_func op_e118_20_nf;
+extern cpuop_func op_e118_20_ff;
+extern cpuop_func op_e120_20_nf;
+extern cpuop_func op_e120_20_ff;
+extern cpuop_func op_e128_20_nf;
+extern cpuop_func op_e128_20_ff;
+extern cpuop_func op_e130_20_nf;
+extern cpuop_func op_e130_20_ff;
+extern cpuop_func op_e138_20_nf;
+extern cpuop_func op_e138_20_ff;
+extern cpuop_func op_e140_20_nf;
+extern cpuop_func op_e140_20_ff;
+extern cpuop_func op_e148_20_nf;
+extern cpuop_func op_e148_20_ff;
+extern cpuop_func op_e150_20_nf;
+extern cpuop_func op_e150_20_ff;
+extern cpuop_func op_e158_20_nf;
+extern cpuop_func op_e158_20_ff;
+extern cpuop_func op_e160_20_nf;
+extern cpuop_func op_e160_20_ff;
+extern cpuop_func op_e168_20_nf;
+extern cpuop_func op_e168_20_ff;
+extern cpuop_func op_e170_20_nf;
+extern cpuop_func op_e170_20_ff;
+extern cpuop_func op_e178_20_nf;
+extern cpuop_func op_e178_20_ff;
+extern cpuop_func op_e180_20_nf;
+extern cpuop_func op_e180_20_ff;
+extern cpuop_func op_e188_20_nf;
+extern cpuop_func op_e188_20_ff;
+extern cpuop_func op_e190_20_nf;
+extern cpuop_func op_e190_20_ff;
+extern cpuop_func op_e198_20_nf;
+extern cpuop_func op_e198_20_ff;
+extern cpuop_func op_e1a0_20_nf;
+extern cpuop_func op_e1a0_20_ff;
+extern cpuop_func op_e1a8_20_nf;
+extern cpuop_func op_e1a8_20_ff;
+extern cpuop_func op_e1b0_20_nf;
+extern cpuop_func op_e1b0_20_ff;
+extern cpuop_func op_e1b8_20_nf;
+extern cpuop_func op_e1b8_20_ff;
+extern cpuop_func op_e1d0_20_nf;
+extern cpuop_func op_e1d0_20_ff;
+extern cpuop_func op_e1d8_20_nf;
+extern cpuop_func op_e1d8_20_ff;
+extern cpuop_func op_e1e0_20_nf;
+extern cpuop_func op_e1e0_20_ff;
+extern cpuop_func op_e1e8_20_nf;
+extern cpuop_func op_e1e8_20_ff;
+extern cpuop_func op_e1f0_20_nf;
+extern cpuop_func op_e1f0_20_ff;
+extern cpuop_func op_e1f8_20_nf;
+extern cpuop_func op_e1f8_20_ff;
+extern cpuop_func op_e1f9_20_nf;
+extern cpuop_func op_e1f9_20_ff;
+extern cpuop_func op_e2d0_20_nf;
+extern cpuop_func op_e2d0_20_ff;
+extern cpuop_func op_e2d8_20_nf;
+extern cpuop_func op_e2d8_20_ff;
+extern cpuop_func op_e2e0_20_nf;
+extern cpuop_func op_e2e0_20_ff;
+extern cpuop_func op_e2e8_20_nf;
+extern cpuop_func op_e2e8_20_ff;
+extern cpuop_func op_e2f0_20_nf;
+extern cpuop_func op_e2f0_20_ff;
+extern cpuop_func op_e2f8_20_nf;
+extern cpuop_func op_e2f8_20_ff;
+extern cpuop_func op_e2f9_20_nf;
+extern cpuop_func op_e2f9_20_ff;
+extern cpuop_func op_e3d0_20_nf;
+extern cpuop_func op_e3d0_20_ff;
+extern cpuop_func op_e3d8_20_nf;
+extern cpuop_func op_e3d8_20_ff;
+extern cpuop_func op_e3e0_20_nf;
+extern cpuop_func op_e3e0_20_ff;
+extern cpuop_func op_e3e8_20_nf;
+extern cpuop_func op_e3e8_20_ff;
+extern cpuop_func op_e3f0_20_nf;
+extern cpuop_func op_e3f0_20_ff;
+extern cpuop_func op_e3f8_20_nf;
+extern cpuop_func op_e3f8_20_ff;
+extern cpuop_func op_e3f9_20_nf;
+extern cpuop_func op_e3f9_20_ff;
+extern cpuop_func op_e4d0_20_nf;
+extern cpuop_func op_e4d0_20_ff;
+extern cpuop_func op_e4d8_20_nf;
+extern cpuop_func op_e4d8_20_ff;
+extern cpuop_func op_e4e0_20_nf;
+extern cpuop_func op_e4e0_20_ff;
+extern cpuop_func op_e4e8_20_nf;
+extern cpuop_func op_e4e8_20_ff;
+extern cpuop_func op_e4f0_20_nf;
+extern cpuop_func op_e4f0_20_ff;
+extern cpuop_func op_e4f8_20_nf;
+extern cpuop_func op_e4f8_20_ff;
+extern cpuop_func op_e4f9_20_nf;
+extern cpuop_func op_e4f9_20_ff;
+extern cpuop_func op_e5d0_20_nf;
+extern cpuop_func op_e5d0_20_ff;
+extern cpuop_func op_e5d8_20_nf;
+extern cpuop_func op_e5d8_20_ff;
+extern cpuop_func op_e5e0_20_nf;
+extern cpuop_func op_e5e0_20_ff;
+extern cpuop_func op_e5e8_20_nf;
+extern cpuop_func op_e5e8_20_ff;
+extern cpuop_func op_e5f0_20_nf;
+extern cpuop_func op_e5f0_20_ff;
+extern cpuop_func op_e5f8_20_nf;
+extern cpuop_func op_e5f8_20_ff;
+extern cpuop_func op_e5f9_20_nf;
+extern cpuop_func op_e5f9_20_ff;
+extern cpuop_func op_e6d0_20_nf;
+extern cpuop_func op_e6d0_20_ff;
+extern cpuop_func op_e6d8_20_nf;
+extern cpuop_func op_e6d8_20_ff;
+extern cpuop_func op_e6e0_20_nf;
+extern cpuop_func op_e6e0_20_ff;
+extern cpuop_func op_e6e8_20_nf;
+extern cpuop_func op_e6e8_20_ff;
+extern cpuop_func op_e6f0_20_nf;
+extern cpuop_func op_e6f0_20_ff;
+extern cpuop_func op_e6f8_20_nf;
+extern cpuop_func op_e6f8_20_ff;
+extern cpuop_func op_e6f9_20_nf;
+extern cpuop_func op_e6f9_20_ff;
+extern cpuop_func op_e7d0_20_nf;
+extern cpuop_func op_e7d0_20_ff;
+extern cpuop_func op_e7d8_20_nf;
+extern cpuop_func op_e7d8_20_ff;
+extern cpuop_func op_e7e0_20_nf;
+extern cpuop_func op_e7e0_20_ff;
+extern cpuop_func op_e7e8_20_nf;
+extern cpuop_func op_e7e8_20_ff;
+extern cpuop_func op_e7f0_20_nf;
+extern cpuop_func op_e7f0_20_ff;
+extern cpuop_func op_e7f8_20_nf;
+extern cpuop_func op_e7f8_20_ff;
+extern cpuop_func op_e7f9_20_nf;
+extern cpuop_func op_e7f9_20_ff;
+extern cpuop_func op_e8c0_20_nf;
+extern cpuop_func op_e8c0_20_ff;
+extern cpuop_func op_e8d0_20_nf;
+extern cpuop_func op_e8d0_20_ff;
+extern cpuop_func op_e8e8_20_nf;
+extern cpuop_func op_e8e8_20_ff;
+extern cpuop_func op_e8f0_20_nf;
+extern cpuop_func op_e8f0_20_ff;
+extern cpuop_func op_e8f8_20_nf;
+extern cpuop_func op_e8f8_20_ff;
+extern cpuop_func op_e8f9_20_nf;
+extern cpuop_func op_e8f9_20_ff;
+extern cpuop_func op_e8fa_20_nf;
+extern cpuop_func op_e8fa_20_ff;
+extern cpuop_func op_e8fb_20_nf;
+extern cpuop_func op_e8fb_20_ff;
+extern cpuop_func op_e9c0_20_nf;
+extern cpuop_func op_e9c0_20_ff;
+extern cpuop_func op_e9d0_20_nf;
+extern cpuop_func op_e9d0_20_ff;
+extern cpuop_func op_e9e8_20_nf;
+extern cpuop_func op_e9e8_20_ff;
+extern cpuop_func op_e9f0_20_nf;
+extern cpuop_func op_e9f0_20_ff;
+extern cpuop_func op_e9f8_20_nf;
+extern cpuop_func op_e9f8_20_ff;
+extern cpuop_func op_e9f9_20_nf;
+extern cpuop_func op_e9f9_20_ff;
+extern cpuop_func op_e9fa_20_nf;
+extern cpuop_func op_e9fa_20_ff;
+extern cpuop_func op_e9fb_20_nf;
+extern cpuop_func op_e9fb_20_ff;
+extern cpuop_func op_eac0_20_nf;
+extern cpuop_func op_eac0_20_ff;
+extern cpuop_func op_ead0_20_nf;
+extern cpuop_func op_ead0_20_ff;
+extern cpuop_func op_eae8_20_nf;
+extern cpuop_func op_eae8_20_ff;
+extern cpuop_func op_eaf0_20_nf;
+extern cpuop_func op_eaf0_20_ff;
+extern cpuop_func op_eaf8_20_nf;
+extern cpuop_func op_eaf8_20_ff;
+extern cpuop_func op_eaf9_20_nf;
+extern cpuop_func op_eaf9_20_ff;
+extern cpuop_func op_ebc0_20_nf;
+extern cpuop_func op_ebc0_20_ff;
+extern cpuop_func op_ebd0_20_nf;
+extern cpuop_func op_ebd0_20_ff;
+extern cpuop_func op_ebe8_20_nf;
+extern cpuop_func op_ebe8_20_ff;
+extern cpuop_func op_ebf0_20_nf;
+extern cpuop_func op_ebf0_20_ff;
+extern cpuop_func op_ebf8_20_nf;
+extern cpuop_func op_ebf8_20_ff;
+extern cpuop_func op_ebf9_20_nf;
+extern cpuop_func op_ebf9_20_ff;
+extern cpuop_func op_ebfa_20_nf;
+extern cpuop_func op_ebfa_20_ff;
+extern cpuop_func op_ebfb_20_nf;
+extern cpuop_func op_ebfb_20_ff;
+extern cpuop_func op_ecc0_20_nf;
+extern cpuop_func op_ecc0_20_ff;
+extern cpuop_func op_ecd0_20_nf;
+extern cpuop_func op_ecd0_20_ff;
+extern cpuop_func op_ece8_20_nf;
+extern cpuop_func op_ece8_20_ff;
+extern cpuop_func op_ecf0_20_nf;
+extern cpuop_func op_ecf0_20_ff;
+extern cpuop_func op_ecf8_20_nf;
+extern cpuop_func op_ecf8_20_ff;
+extern cpuop_func op_ecf9_20_nf;
+extern cpuop_func op_ecf9_20_ff;
+extern cpuop_func op_edc0_20_nf;
+extern cpuop_func op_edc0_20_ff;
+extern cpuop_func op_edd0_20_nf;
+extern cpuop_func op_edd0_20_ff;
+extern cpuop_func op_ede8_20_nf;
+extern cpuop_func op_ede8_20_ff;
+extern cpuop_func op_edf0_20_nf;
+extern cpuop_func op_edf0_20_ff;
+extern cpuop_func op_edf8_20_nf;
+extern cpuop_func op_edf8_20_ff;
+extern cpuop_func op_edf9_20_nf;
+extern cpuop_func op_edf9_20_ff;
+extern cpuop_func op_edfa_20_nf;
+extern cpuop_func op_edfa_20_ff;
+extern cpuop_func op_edfb_20_nf;
+extern cpuop_func op_edfb_20_ff;
+extern cpuop_func op_eec0_20_nf;
+extern cpuop_func op_eec0_20_ff;
+extern cpuop_func op_eed0_20_nf;
+extern cpuop_func op_eed0_20_ff;
+extern cpuop_func op_eee8_20_nf;
+extern cpuop_func op_eee8_20_ff;
+extern cpuop_func op_eef0_20_nf;
+extern cpuop_func op_eef0_20_ff;
+extern cpuop_func op_eef8_20_nf;
+extern cpuop_func op_eef8_20_ff;
+extern cpuop_func op_eef9_20_nf;
+extern cpuop_func op_eef9_20_ff;
+extern cpuop_func op_efc0_20_nf;
+extern cpuop_func op_efc0_20_ff;
+extern cpuop_func op_efd0_20_nf;
+extern cpuop_func op_efd0_20_ff;
+extern cpuop_func op_efe8_20_nf;
+extern cpuop_func op_efe8_20_ff;
+extern cpuop_func op_eff0_20_nf;
+extern cpuop_func op_eff0_20_ff;
+extern cpuop_func op_eff8_20_nf;
+extern cpuop_func op_eff8_20_ff;
+extern cpuop_func op_eff9_20_nf;
+extern cpuop_func op_eff9_20_ff;
+extern cpuop_func op_f200_20_nf;
+extern cpuop_func op_f200_20_ff;
+extern cpuop_func op_f208_20_nf;
+extern cpuop_func op_f208_20_ff;
+extern cpuop_func op_f210_20_nf;
+extern cpuop_func op_f210_20_ff;
+extern cpuop_func op_f218_20_nf;
+extern cpuop_func op_f218_20_ff;
+extern cpuop_func op_f220_20_nf;
+extern cpuop_func op_f220_20_ff;
+extern cpuop_func op_f228_20_nf;
+extern cpuop_func op_f228_20_ff;
+extern cpuop_func op_f230_20_nf;
+extern cpuop_func op_f230_20_ff;
+extern cpuop_func op_f238_20_nf;
+extern cpuop_func op_f238_20_ff;
+extern cpuop_func op_f239_20_nf;
+extern cpuop_func op_f239_20_ff;
+extern cpuop_func op_f23a_20_nf;
+extern cpuop_func op_f23a_20_ff;
+extern cpuop_func op_f23b_20_nf;
+extern cpuop_func op_f23b_20_ff;
+extern cpuop_func op_f23c_20_nf;
+extern cpuop_func op_f23c_20_ff;
+extern cpuop_func op_f240_20_nf;
+extern cpuop_func op_f240_20_ff;
+extern cpuop_func op_f248_20_nf;
+extern cpuop_func op_f248_20_ff;
+extern cpuop_func op_f250_20_nf;
+extern cpuop_func op_f250_20_ff;
+extern cpuop_func op_f258_20_nf;
+extern cpuop_func op_f258_20_ff;
+extern cpuop_func op_f260_20_nf;
+extern cpuop_func op_f260_20_ff;
+extern cpuop_func op_f268_20_nf;
+extern cpuop_func op_f268_20_ff;
+extern cpuop_func op_f270_20_nf;
+extern cpuop_func op_f270_20_ff;
+extern cpuop_func op_f278_20_nf;
+extern cpuop_func op_f278_20_ff;
+extern cpuop_func op_f279_20_nf;
+extern cpuop_func op_f279_20_ff;
+extern cpuop_func op_f27a_20_nf;
+extern cpuop_func op_f27a_20_ff;
+extern cpuop_func op_f27b_20_nf;
+extern cpuop_func op_f27b_20_ff;
+extern cpuop_func op_f27c_20_nf;
+extern cpuop_func op_f27c_20_ff;
+extern cpuop_func op_f280_20_nf;
+extern cpuop_func op_f280_20_ff;
+extern cpuop_func op_f2c0_20_nf;
+extern cpuop_func op_f2c0_20_ff;
+extern cpuop_func op_f310_20_nf;
+extern cpuop_func op_f310_20_ff;
+extern cpuop_func op_f320_20_nf;
+extern cpuop_func op_f320_20_ff;
+extern cpuop_func op_f328_20_nf;
+extern cpuop_func op_f328_20_ff;
+extern cpuop_func op_f330_20_nf;
+extern cpuop_func op_f330_20_ff;
+extern cpuop_func op_f338_20_nf;
+extern cpuop_func op_f338_20_ff;
+extern cpuop_func op_f339_20_nf;
+extern cpuop_func op_f339_20_ff;
+extern cpuop_func op_f350_20_nf;
+extern cpuop_func op_f350_20_ff;
+extern cpuop_func op_f358_20_nf;
+extern cpuop_func op_f358_20_ff;
+extern cpuop_func op_f368_20_nf;
+extern cpuop_func op_f368_20_ff;
+extern cpuop_func op_f370_20_nf;
+extern cpuop_func op_f370_20_ff;
+extern cpuop_func op_f378_20_nf;
+extern cpuop_func op_f378_20_ff;
+extern cpuop_func op_f379_20_nf;
+extern cpuop_func op_f379_20_ff;
+extern cpuop_func op_f37a_20_nf;
+extern cpuop_func op_f37a_20_ff;
+extern cpuop_func op_f37b_20_nf;
+extern cpuop_func op_f37b_20_ff;
+extern cpuop_func_ce op_0000_21_nf;
+extern cpuop_func_ce op_0000_21_ff;
+extern cpuop_func_ce op_0010_21_nf;
+extern cpuop_func_ce op_0010_21_ff;
+extern cpuop_func_ce op_0018_21_nf;
+extern cpuop_func_ce op_0018_21_ff;
+extern cpuop_func_ce op_0020_21_nf;
+extern cpuop_func_ce op_0020_21_ff;
+extern cpuop_func_ce op_0028_21_nf;
+extern cpuop_func_ce op_0028_21_ff;
+extern cpuop_func_ce op_0030_21_nf;
+extern cpuop_func_ce op_0030_21_ff;
+extern cpuop_func_ce op_0038_21_nf;
+extern cpuop_func_ce op_0038_21_ff;
+extern cpuop_func_ce op_0039_21_nf;
+extern cpuop_func_ce op_0039_21_ff;
+extern cpuop_func_ce op_003c_21_nf;
+extern cpuop_func_ce op_003c_21_ff;
+extern cpuop_func_ce op_0040_21_nf;
+extern cpuop_func_ce op_0040_21_ff;
+extern cpuop_func_ce op_0050_21_nf;
+extern cpuop_func_ce op_0050_21_ff;
+extern cpuop_func_ce op_0058_21_nf;
+extern cpuop_func_ce op_0058_21_ff;
+extern cpuop_func_ce op_0060_21_nf;
+extern cpuop_func_ce op_0060_21_ff;
+extern cpuop_func_ce op_0068_21_nf;
+extern cpuop_func_ce op_0068_21_ff;
+extern cpuop_func_ce op_0070_21_nf;
+extern cpuop_func_ce op_0070_21_ff;
+extern cpuop_func_ce op_0078_21_nf;
+extern cpuop_func_ce op_0078_21_ff;
+extern cpuop_func_ce op_0079_21_nf;
+extern cpuop_func_ce op_0079_21_ff;
+extern cpuop_func_ce op_007c_21_nf;
+extern cpuop_func_ce op_007c_21_ff;
+extern cpuop_func_ce op_0080_21_nf;
+extern cpuop_func_ce op_0080_21_ff;
+extern cpuop_func_ce op_0090_21_nf;
+extern cpuop_func_ce op_0090_21_ff;
+extern cpuop_func_ce op_0098_21_nf;
+extern cpuop_func_ce op_0098_21_ff;
+extern cpuop_func_ce op_00a0_21_nf;
+extern cpuop_func_ce op_00a0_21_ff;
+extern cpuop_func_ce op_00a8_21_nf;
+extern cpuop_func_ce op_00a8_21_ff;
+extern cpuop_func_ce op_00b0_21_nf;
+extern cpuop_func_ce op_00b0_21_ff;
+extern cpuop_func_ce op_00b8_21_nf;
+extern cpuop_func_ce op_00b8_21_ff;
+extern cpuop_func_ce op_00b9_21_nf;
+extern cpuop_func_ce op_00b9_21_ff;
+extern cpuop_func_ce op_00d0_21_nf;
+extern cpuop_func_ce op_00d0_21_ff;
+extern cpuop_func_ce op_00e8_21_nf;
+extern cpuop_func_ce op_00e8_21_ff;
+extern cpuop_func_ce op_00f0_21_nf;
+extern cpuop_func_ce op_00f0_21_ff;
+extern cpuop_func_ce op_00f8_21_nf;
+extern cpuop_func_ce op_00f8_21_ff;
+extern cpuop_func_ce op_00f9_21_nf;
+extern cpuop_func_ce op_00f9_21_ff;
+extern cpuop_func_ce op_00fa_21_nf;
+extern cpuop_func_ce op_00fa_21_ff;
+extern cpuop_func_ce op_00fb_21_nf;
+extern cpuop_func_ce op_00fb_21_ff;
+extern cpuop_func_ce op_0100_21_nf;
+extern cpuop_func_ce op_0100_21_ff;
+extern cpuop_func_ce op_0108_21_nf;
+extern cpuop_func_ce op_0108_21_ff;
+extern cpuop_func_ce op_0110_21_nf;
+extern cpuop_func_ce op_0110_21_ff;
+extern cpuop_func_ce op_0118_21_nf;
+extern cpuop_func_ce op_0118_21_ff;
+extern cpuop_func_ce op_0120_21_nf;
+extern cpuop_func_ce op_0120_21_ff;
+extern cpuop_func_ce op_0128_21_nf;
+extern cpuop_func_ce op_0128_21_ff;
+extern cpuop_func_ce op_0130_21_nf;
+extern cpuop_func_ce op_0130_21_ff;
+extern cpuop_func_ce op_0138_21_nf;
+extern cpuop_func_ce op_0138_21_ff;
+extern cpuop_func_ce op_0139_21_nf;
+extern cpuop_func_ce op_0139_21_ff;
+extern cpuop_func_ce op_013a_21_nf;
+extern cpuop_func_ce op_013a_21_ff;
+extern cpuop_func_ce op_013b_21_nf;
+extern cpuop_func_ce op_013b_21_ff;
+extern cpuop_func_ce op_013c_21_nf;
+extern cpuop_func_ce op_013c_21_ff;
+extern cpuop_func_ce op_0140_21_nf;
+extern cpuop_func_ce op_0140_21_ff;
+extern cpuop_func_ce op_0148_21_nf;
+extern cpuop_func_ce op_0148_21_ff;
+extern cpuop_func_ce op_0150_21_nf;
+extern cpuop_func_ce op_0150_21_ff;
+extern cpuop_func_ce op_0158_21_nf;
+extern cpuop_func_ce op_0158_21_ff;
+extern cpuop_func_ce op_0160_21_nf;
+extern cpuop_func_ce op_0160_21_ff;
+extern cpuop_func_ce op_0168_21_nf;
+extern cpuop_func_ce op_0168_21_ff;
+extern cpuop_func_ce op_0170_21_nf;
+extern cpuop_func_ce op_0170_21_ff;
+extern cpuop_func_ce op_0178_21_nf;
+extern cpuop_func_ce op_0178_21_ff;
+extern cpuop_func_ce op_0179_21_nf;
+extern cpuop_func_ce op_0179_21_ff;
+extern cpuop_func_ce op_0180_21_nf;
+extern cpuop_func_ce op_0180_21_ff;
+extern cpuop_func_ce op_0188_21_nf;
+extern cpuop_func_ce op_0188_21_ff;
+extern cpuop_func_ce op_0190_21_nf;
+extern cpuop_func_ce op_0190_21_ff;
+extern cpuop_func_ce op_0198_21_nf;
+extern cpuop_func_ce op_0198_21_ff;
+extern cpuop_func_ce op_01a0_21_nf;
+extern cpuop_func_ce op_01a0_21_ff;
+extern cpuop_func_ce op_01a8_21_nf;
+extern cpuop_func_ce op_01a8_21_ff;
+extern cpuop_func_ce op_01b0_21_nf;
+extern cpuop_func_ce op_01b0_21_ff;
+extern cpuop_func_ce op_01b8_21_nf;
+extern cpuop_func_ce op_01b8_21_ff;
+extern cpuop_func_ce op_01b9_21_nf;
+extern cpuop_func_ce op_01b9_21_ff;
+extern cpuop_func_ce op_01c0_21_nf;
+extern cpuop_func_ce op_01c0_21_ff;
+extern cpuop_func_ce op_01c8_21_nf;
+extern cpuop_func_ce op_01c8_21_ff;
+extern cpuop_func_ce op_01d0_21_nf;
+extern cpuop_func_ce op_01d0_21_ff;
+extern cpuop_func_ce op_01d8_21_nf;
+extern cpuop_func_ce op_01d8_21_ff;
+extern cpuop_func_ce op_01e0_21_nf;
+extern cpuop_func_ce op_01e0_21_ff;
+extern cpuop_func_ce op_01e8_21_nf;
+extern cpuop_func_ce op_01e8_21_ff;
+extern cpuop_func_ce op_01f0_21_nf;
+extern cpuop_func_ce op_01f0_21_ff;
+extern cpuop_func_ce op_01f8_21_nf;
+extern cpuop_func_ce op_01f8_21_ff;
+extern cpuop_func_ce op_01f9_21_nf;
+extern cpuop_func_ce op_01f9_21_ff;
+extern cpuop_func_ce op_0200_21_nf;
+extern cpuop_func_ce op_0200_21_ff;
+extern cpuop_func_ce op_0210_21_nf;
+extern cpuop_func_ce op_0210_21_ff;
+extern cpuop_func_ce op_0218_21_nf;
+extern cpuop_func_ce op_0218_21_ff;
+extern cpuop_func_ce op_0220_21_nf;
+extern cpuop_func_ce op_0220_21_ff;
+extern cpuop_func_ce op_0228_21_nf;
+extern cpuop_func_ce op_0228_21_ff;
+extern cpuop_func_ce op_0230_21_nf;
+extern cpuop_func_ce op_0230_21_ff;
+extern cpuop_func_ce op_0238_21_nf;
+extern cpuop_func_ce op_0238_21_ff;
+extern cpuop_func_ce op_0239_21_nf;
+extern cpuop_func_ce op_0239_21_ff;
+extern cpuop_func_ce op_023c_21_nf;
+extern cpuop_func_ce op_023c_21_ff;
+extern cpuop_func_ce op_0240_21_nf;
+extern cpuop_func_ce op_0240_21_ff;
+extern cpuop_func_ce op_0250_21_nf;
+extern cpuop_func_ce op_0250_21_ff;
+extern cpuop_func_ce op_0258_21_nf;
+extern cpuop_func_ce op_0258_21_ff;
+extern cpuop_func_ce op_0260_21_nf;
+extern cpuop_func_ce op_0260_21_ff;
+extern cpuop_func_ce op_0268_21_nf;
+extern cpuop_func_ce op_0268_21_ff;
+extern cpuop_func_ce op_0270_21_nf;
+extern cpuop_func_ce op_0270_21_ff;
+extern cpuop_func_ce op_0278_21_nf;
+extern cpuop_func_ce op_0278_21_ff;
+extern cpuop_func_ce op_0279_21_nf;
+extern cpuop_func_ce op_0279_21_ff;
+extern cpuop_func_ce op_027c_21_nf;
+extern cpuop_func_ce op_027c_21_ff;
+extern cpuop_func_ce op_0280_21_nf;
+extern cpuop_func_ce op_0280_21_ff;
+extern cpuop_func_ce op_0290_21_nf;
+extern cpuop_func_ce op_0290_21_ff;
+extern cpuop_func_ce op_0298_21_nf;
+extern cpuop_func_ce op_0298_21_ff;
+extern cpuop_func_ce op_02a0_21_nf;
+extern cpuop_func_ce op_02a0_21_ff;
+extern cpuop_func_ce op_02a8_21_nf;
+extern cpuop_func_ce op_02a8_21_ff;
+extern cpuop_func_ce op_02b0_21_nf;
+extern cpuop_func_ce op_02b0_21_ff;
+extern cpuop_func_ce op_02b8_21_nf;
+extern cpuop_func_ce op_02b8_21_ff;
+extern cpuop_func_ce op_02b9_21_nf;
+extern cpuop_func_ce op_02b9_21_ff;
+extern cpuop_func_ce op_02d0_21_nf;
+extern cpuop_func_ce op_02d0_21_ff;
+extern cpuop_func_ce op_02e8_21_nf;
+extern cpuop_func_ce op_02e8_21_ff;
+extern cpuop_func_ce op_02f0_21_nf;
+extern cpuop_func_ce op_02f0_21_ff;
+extern cpuop_func_ce op_02f8_21_nf;
+extern cpuop_func_ce op_02f8_21_ff;
+extern cpuop_func_ce op_02f9_21_nf;
+extern cpuop_func_ce op_02f9_21_ff;
+extern cpuop_func_ce op_02fa_21_nf;
+extern cpuop_func_ce op_02fa_21_ff;
+extern cpuop_func_ce op_02fb_21_nf;
+extern cpuop_func_ce op_02fb_21_ff;
+extern cpuop_func_ce op_0400_21_nf;
+extern cpuop_func_ce op_0400_21_ff;
+extern cpuop_func_ce op_0410_21_nf;
+extern cpuop_func_ce op_0410_21_ff;
+extern cpuop_func_ce op_0418_21_nf;
+extern cpuop_func_ce op_0418_21_ff;
+extern cpuop_func_ce op_0420_21_nf;
+extern cpuop_func_ce op_0420_21_ff;
+extern cpuop_func_ce op_0428_21_nf;
+extern cpuop_func_ce op_0428_21_ff;
+extern cpuop_func_ce op_0430_21_nf;
+extern cpuop_func_ce op_0430_21_ff;
+extern cpuop_func_ce op_0438_21_nf;
+extern cpuop_func_ce op_0438_21_ff;
+extern cpuop_func_ce op_0439_21_nf;
+extern cpuop_func_ce op_0439_21_ff;
+extern cpuop_func_ce op_0440_21_nf;
+extern cpuop_func_ce op_0440_21_ff;
+extern cpuop_func_ce op_0450_21_nf;
+extern cpuop_func_ce op_0450_21_ff;
+extern cpuop_func_ce op_0458_21_nf;
+extern cpuop_func_ce op_0458_21_ff;
+extern cpuop_func_ce op_0460_21_nf;
+extern cpuop_func_ce op_0460_21_ff;
+extern cpuop_func_ce op_0468_21_nf;
+extern cpuop_func_ce op_0468_21_ff;
+extern cpuop_func_ce op_0470_21_nf;
+extern cpuop_func_ce op_0470_21_ff;
+extern cpuop_func_ce op_0478_21_nf;
+extern cpuop_func_ce op_0478_21_ff;
+extern cpuop_func_ce op_0479_21_nf;
+extern cpuop_func_ce op_0479_21_ff;
+extern cpuop_func_ce op_0480_21_nf;
+extern cpuop_func_ce op_0480_21_ff;
+extern cpuop_func_ce op_0490_21_nf;
+extern cpuop_func_ce op_0490_21_ff;
+extern cpuop_func_ce op_0498_21_nf;
+extern cpuop_func_ce op_0498_21_ff;
+extern cpuop_func_ce op_04a0_21_nf;
+extern cpuop_func_ce op_04a0_21_ff;
+extern cpuop_func_ce op_04a8_21_nf;
+extern cpuop_func_ce op_04a8_21_ff;
+extern cpuop_func_ce op_04b0_21_nf;
+extern cpuop_func_ce op_04b0_21_ff;
+extern cpuop_func_ce op_04b8_21_nf;
+extern cpuop_func_ce op_04b8_21_ff;
+extern cpuop_func_ce op_04b9_21_nf;
+extern cpuop_func_ce op_04b9_21_ff;
+extern cpuop_func_ce op_04d0_21_nf;
+extern cpuop_func_ce op_04d0_21_ff;
+extern cpuop_func_ce op_04e8_21_nf;
+extern cpuop_func_ce op_04e8_21_ff;
+extern cpuop_func_ce op_04f0_21_nf;
+extern cpuop_func_ce op_04f0_21_ff;
+extern cpuop_func_ce op_04f8_21_nf;
+extern cpuop_func_ce op_04f8_21_ff;
+extern cpuop_func_ce op_04f9_21_nf;
+extern cpuop_func_ce op_04f9_21_ff;
+extern cpuop_func_ce op_04fa_21_nf;
+extern cpuop_func_ce op_04fa_21_ff;
+extern cpuop_func_ce op_04fb_21_nf;
+extern cpuop_func_ce op_04fb_21_ff;
+extern cpuop_func_ce op_0600_21_nf;
+extern cpuop_func_ce op_0600_21_ff;
+extern cpuop_func_ce op_0610_21_nf;
+extern cpuop_func_ce op_0610_21_ff;
+extern cpuop_func_ce op_0618_21_nf;
+extern cpuop_func_ce op_0618_21_ff;
+extern cpuop_func_ce op_0620_21_nf;
+extern cpuop_func_ce op_0620_21_ff;
+extern cpuop_func_ce op_0628_21_nf;
+extern cpuop_func_ce op_0628_21_ff;
+extern cpuop_func_ce op_0630_21_nf;
+extern cpuop_func_ce op_0630_21_ff;
+extern cpuop_func_ce op_0638_21_nf;
+extern cpuop_func_ce op_0638_21_ff;
+extern cpuop_func_ce op_0639_21_nf;
+extern cpuop_func_ce op_0639_21_ff;
+extern cpuop_func_ce op_0640_21_nf;
+extern cpuop_func_ce op_0640_21_ff;
+extern cpuop_func_ce op_0650_21_nf;
+extern cpuop_func_ce op_0650_21_ff;
+extern cpuop_func_ce op_0658_21_nf;
+extern cpuop_func_ce op_0658_21_ff;
+extern cpuop_func_ce op_0660_21_nf;
+extern cpuop_func_ce op_0660_21_ff;
+extern cpuop_func_ce op_0668_21_nf;
+extern cpuop_func_ce op_0668_21_ff;
+extern cpuop_func_ce op_0670_21_nf;
+extern cpuop_func_ce op_0670_21_ff;
+extern cpuop_func_ce op_0678_21_nf;
+extern cpuop_func_ce op_0678_21_ff;
+extern cpuop_func_ce op_0679_21_nf;
+extern cpuop_func_ce op_0679_21_ff;
+extern cpuop_func_ce op_0680_21_nf;
+extern cpuop_func_ce op_0680_21_ff;
+extern cpuop_func_ce op_0690_21_nf;
+extern cpuop_func_ce op_0690_21_ff;
+extern cpuop_func_ce op_0698_21_nf;
+extern cpuop_func_ce op_0698_21_ff;
+extern cpuop_func_ce op_06a0_21_nf;
+extern cpuop_func_ce op_06a0_21_ff;
+extern cpuop_func_ce op_06a8_21_nf;
+extern cpuop_func_ce op_06a8_21_ff;
+extern cpuop_func_ce op_06b0_21_nf;
+extern cpuop_func_ce op_06b0_21_ff;
+extern cpuop_func_ce op_06b8_21_nf;
+extern cpuop_func_ce op_06b8_21_ff;
+extern cpuop_func_ce op_06b9_21_nf;
+extern cpuop_func_ce op_06b9_21_ff;
+extern cpuop_func_ce op_06c0_21_nf;
+extern cpuop_func_ce op_06c0_21_ff;
+extern cpuop_func_ce op_06c8_21_nf;
+extern cpuop_func_ce op_06c8_21_ff;
+extern cpuop_func_ce op_06d0_21_nf;
+extern cpuop_func_ce op_06d0_21_ff;
+extern cpuop_func_ce op_06e8_21_nf;
+extern cpuop_func_ce op_06e8_21_ff;
+extern cpuop_func_ce op_06f0_21_nf;
+extern cpuop_func_ce op_06f0_21_ff;
+extern cpuop_func_ce op_06f8_21_nf;
+extern cpuop_func_ce op_06f8_21_ff;
+extern cpuop_func_ce op_06f9_21_nf;
+extern cpuop_func_ce op_06f9_21_ff;
+extern cpuop_func_ce op_06fa_21_nf;
+extern cpuop_func_ce op_06fa_21_ff;
+extern cpuop_func_ce op_06fb_21_nf;
+extern cpuop_func_ce op_06fb_21_ff;
+extern cpuop_func_ce op_0800_21_nf;
+extern cpuop_func_ce op_0800_21_ff;
+extern cpuop_func_ce op_0810_21_nf;
+extern cpuop_func_ce op_0810_21_ff;
+extern cpuop_func_ce op_0818_21_nf;
+extern cpuop_func_ce op_0818_21_ff;
+extern cpuop_func_ce op_0820_21_nf;
+extern cpuop_func_ce op_0820_21_ff;
+extern cpuop_func_ce op_0828_21_nf;
+extern cpuop_func_ce op_0828_21_ff;
+extern cpuop_func_ce op_0830_21_nf;
+extern cpuop_func_ce op_0830_21_ff;
+extern cpuop_func_ce op_0838_21_nf;
+extern cpuop_func_ce op_0838_21_ff;
+extern cpuop_func_ce op_0839_21_nf;
+extern cpuop_func_ce op_0839_21_ff;
+extern cpuop_func_ce op_083a_21_nf;
+extern cpuop_func_ce op_083a_21_ff;
+extern cpuop_func_ce op_083b_21_nf;
+extern cpuop_func_ce op_083b_21_ff;
+extern cpuop_func_ce op_0840_21_nf;
+extern cpuop_func_ce op_0840_21_ff;
+extern cpuop_func_ce op_0850_21_nf;
+extern cpuop_func_ce op_0850_21_ff;
+extern cpuop_func_ce op_0858_21_nf;
+extern cpuop_func_ce op_0858_21_ff;
+extern cpuop_func_ce op_0860_21_nf;
+extern cpuop_func_ce op_0860_21_ff;
+extern cpuop_func_ce op_0868_21_nf;
+extern cpuop_func_ce op_0868_21_ff;
+extern cpuop_func_ce op_0870_21_nf;
+extern cpuop_func_ce op_0870_21_ff;
+extern cpuop_func_ce op_0878_21_nf;
+extern cpuop_func_ce op_0878_21_ff;
+extern cpuop_func_ce op_0879_21_nf;
+extern cpuop_func_ce op_0879_21_ff;
+extern cpuop_func_ce op_0880_21_nf;
+extern cpuop_func_ce op_0880_21_ff;
+extern cpuop_func_ce op_0890_21_nf;
+extern cpuop_func_ce op_0890_21_ff;
+extern cpuop_func_ce op_0898_21_nf;
+extern cpuop_func_ce op_0898_21_ff;
+extern cpuop_func_ce op_08a0_21_nf;
+extern cpuop_func_ce op_08a0_21_ff;
+extern cpuop_func_ce op_08a8_21_nf;
+extern cpuop_func_ce op_08a8_21_ff;
+extern cpuop_func_ce op_08b0_21_nf;
+extern cpuop_func_ce op_08b0_21_ff;
+extern cpuop_func_ce op_08b8_21_nf;
+extern cpuop_func_ce op_08b8_21_ff;
+extern cpuop_func_ce op_08b9_21_nf;
+extern cpuop_func_ce op_08b9_21_ff;
+extern cpuop_func_ce op_08c0_21_nf;
+extern cpuop_func_ce op_08c0_21_ff;
+extern cpuop_func_ce op_08d0_21_nf;
+extern cpuop_func_ce op_08d0_21_ff;
+extern cpuop_func_ce op_08d8_21_nf;
+extern cpuop_func_ce op_08d8_21_ff;
+extern cpuop_func_ce op_08e0_21_nf;
+extern cpuop_func_ce op_08e0_21_ff;
+extern cpuop_func_ce op_08e8_21_nf;
+extern cpuop_func_ce op_08e8_21_ff;
+extern cpuop_func_ce op_08f0_21_nf;
+extern cpuop_func_ce op_08f0_21_ff;
+extern cpuop_func_ce op_08f8_21_nf;
+extern cpuop_func_ce op_08f8_21_ff;
+extern cpuop_func_ce op_08f9_21_nf;
+extern cpuop_func_ce op_08f9_21_ff;
+extern cpuop_func_ce op_0a00_21_nf;
+extern cpuop_func_ce op_0a00_21_ff;
+extern cpuop_func_ce op_0a10_21_nf;
+extern cpuop_func_ce op_0a10_21_ff;
+extern cpuop_func_ce op_0a18_21_nf;
+extern cpuop_func_ce op_0a18_21_ff;
+extern cpuop_func_ce op_0a20_21_nf;
+extern cpuop_func_ce op_0a20_21_ff;
+extern cpuop_func_ce op_0a28_21_nf;
+extern cpuop_func_ce op_0a28_21_ff;
+extern cpuop_func_ce op_0a30_21_nf;
+extern cpuop_func_ce op_0a30_21_ff;
+extern cpuop_func_ce op_0a38_21_nf;
+extern cpuop_func_ce op_0a38_21_ff;
+extern cpuop_func_ce op_0a39_21_nf;
+extern cpuop_func_ce op_0a39_21_ff;
+extern cpuop_func_ce op_0a3c_21_nf;
+extern cpuop_func_ce op_0a3c_21_ff;
+extern cpuop_func_ce op_0a40_21_nf;
+extern cpuop_func_ce op_0a40_21_ff;
+extern cpuop_func_ce op_0a50_21_nf;
+extern cpuop_func_ce op_0a50_21_ff;
+extern cpuop_func_ce op_0a58_21_nf;
+extern cpuop_func_ce op_0a58_21_ff;
+extern cpuop_func_ce op_0a60_21_nf;
+extern cpuop_func_ce op_0a60_21_ff;
+extern cpuop_func_ce op_0a68_21_nf;
+extern cpuop_func_ce op_0a68_21_ff;
+extern cpuop_func_ce op_0a70_21_nf;
+extern cpuop_func_ce op_0a70_21_ff;
+extern cpuop_func_ce op_0a78_21_nf;
+extern cpuop_func_ce op_0a78_21_ff;
+extern cpuop_func_ce op_0a79_21_nf;
+extern cpuop_func_ce op_0a79_21_ff;
+extern cpuop_func_ce op_0a7c_21_nf;
+extern cpuop_func_ce op_0a7c_21_ff;
+extern cpuop_func_ce op_0a80_21_nf;
+extern cpuop_func_ce op_0a80_21_ff;
+extern cpuop_func_ce op_0a90_21_nf;
+extern cpuop_func_ce op_0a90_21_ff;
+extern cpuop_func_ce op_0a98_21_nf;
+extern cpuop_func_ce op_0a98_21_ff;
+extern cpuop_func_ce op_0aa0_21_nf;
+extern cpuop_func_ce op_0aa0_21_ff;
+extern cpuop_func_ce op_0aa8_21_nf;
+extern cpuop_func_ce op_0aa8_21_ff;
+extern cpuop_func_ce op_0ab0_21_nf;
+extern cpuop_func_ce op_0ab0_21_ff;
+extern cpuop_func_ce op_0ab8_21_nf;
+extern cpuop_func_ce op_0ab8_21_ff;
+extern cpuop_func_ce op_0ab9_21_nf;
+extern cpuop_func_ce op_0ab9_21_ff;
+extern cpuop_func_ce op_0ad0_21_nf;
+extern cpuop_func_ce op_0ad0_21_ff;
+extern cpuop_func_ce op_0ad8_21_nf;
+extern cpuop_func_ce op_0ad8_21_ff;
+extern cpuop_func_ce op_0ae0_21_nf;
+extern cpuop_func_ce op_0ae0_21_ff;
+extern cpuop_func_ce op_0ae8_21_nf;
+extern cpuop_func_ce op_0ae8_21_ff;
+extern cpuop_func_ce op_0af0_21_nf;
+extern cpuop_func_ce op_0af0_21_ff;
+extern cpuop_func_ce op_0af8_21_nf;
+extern cpuop_func_ce op_0af8_21_ff;
+extern cpuop_func_ce op_0af9_21_nf;
+extern cpuop_func_ce op_0af9_21_ff;
+extern cpuop_func_ce op_0c00_21_nf;
+extern cpuop_func_ce op_0c00_21_ff;
+extern cpuop_func_ce op_0c10_21_nf;
+extern cpuop_func_ce op_0c10_21_ff;
+extern cpuop_func_ce op_0c18_21_nf;
+extern cpuop_func_ce op_0c18_21_ff;
+extern cpuop_func_ce op_0c20_21_nf;
+extern cpuop_func_ce op_0c20_21_ff;
+extern cpuop_func_ce op_0c28_21_nf;
+extern cpuop_func_ce op_0c28_21_ff;
+extern cpuop_func_ce op_0c30_21_nf;
+extern cpuop_func_ce op_0c30_21_ff;
+extern cpuop_func_ce op_0c38_21_nf;
+extern cpuop_func_ce op_0c38_21_ff;
+extern cpuop_func_ce op_0c39_21_nf;
+extern cpuop_func_ce op_0c39_21_ff;
+extern cpuop_func_ce op_0c3a_21_nf;
+extern cpuop_func_ce op_0c3a_21_ff;
+extern cpuop_func_ce op_0c3b_21_nf;
+extern cpuop_func_ce op_0c3b_21_ff;
+extern cpuop_func_ce op_0c40_21_nf;
+extern cpuop_func_ce op_0c40_21_ff;
+extern cpuop_func_ce op_0c50_21_nf;
+extern cpuop_func_ce op_0c50_21_ff;
+extern cpuop_func_ce op_0c58_21_nf;
+extern cpuop_func_ce op_0c58_21_ff;
+extern cpuop_func_ce op_0c60_21_nf;
+extern cpuop_func_ce op_0c60_21_ff;
+extern cpuop_func_ce op_0c68_21_nf;
+extern cpuop_func_ce op_0c68_21_ff;
+extern cpuop_func_ce op_0c70_21_nf;
+extern cpuop_func_ce op_0c70_21_ff;
+extern cpuop_func_ce op_0c78_21_nf;
+extern cpuop_func_ce op_0c78_21_ff;
+extern cpuop_func_ce op_0c79_21_nf;
+extern cpuop_func_ce op_0c79_21_ff;
+extern cpuop_func_ce op_0c7a_21_nf;
+extern cpuop_func_ce op_0c7a_21_ff;
+extern cpuop_func_ce op_0c7b_21_nf;
+extern cpuop_func_ce op_0c7b_21_ff;
+extern cpuop_func_ce op_0c80_21_nf;
+extern cpuop_func_ce op_0c80_21_ff;
+extern cpuop_func_ce op_0c90_21_nf;
+extern cpuop_func_ce op_0c90_21_ff;
+extern cpuop_func_ce op_0c98_21_nf;
+extern cpuop_func_ce op_0c98_21_ff;
+extern cpuop_func_ce op_0ca0_21_nf;
+extern cpuop_func_ce op_0ca0_21_ff;
+extern cpuop_func_ce op_0ca8_21_nf;
+extern cpuop_func_ce op_0ca8_21_ff;
+extern cpuop_func_ce op_0cb0_21_nf;
+extern cpuop_func_ce op_0cb0_21_ff;
+extern cpuop_func_ce op_0cb8_21_nf;
+extern cpuop_func_ce op_0cb8_21_ff;
+extern cpuop_func_ce op_0cb9_21_nf;
+extern cpuop_func_ce op_0cb9_21_ff;
+extern cpuop_func_ce op_0cba_21_nf;
+extern cpuop_func_ce op_0cba_21_ff;
+extern cpuop_func_ce op_0cbb_21_nf;
+extern cpuop_func_ce op_0cbb_21_ff;
+extern cpuop_func_ce op_0cd0_21_nf;
+extern cpuop_func_ce op_0cd0_21_ff;
+extern cpuop_func_ce op_0cd8_21_nf;
+extern cpuop_func_ce op_0cd8_21_ff;
+extern cpuop_func_ce op_0ce0_21_nf;
+extern cpuop_func_ce op_0ce0_21_ff;
+extern cpuop_func_ce op_0ce8_21_nf;
+extern cpuop_func_ce op_0ce8_21_ff;
+extern cpuop_func_ce op_0cf0_21_nf;
+extern cpuop_func_ce op_0cf0_21_ff;
+extern cpuop_func_ce op_0cf8_21_nf;
+extern cpuop_func_ce op_0cf8_21_ff;
+extern cpuop_func_ce op_0cf9_21_nf;
+extern cpuop_func_ce op_0cf9_21_ff;
+extern cpuop_func_ce op_0cfc_21_nf;
+extern cpuop_func_ce op_0cfc_21_ff;
+extern cpuop_func_ce op_0e10_21_nf;
+extern cpuop_func_ce op_0e10_21_ff;
+extern cpuop_func_ce op_0e18_21_nf;
+extern cpuop_func_ce op_0e18_21_ff;
+extern cpuop_func_ce op_0e20_21_nf;
+extern cpuop_func_ce op_0e20_21_ff;
+extern cpuop_func_ce op_0e28_21_nf;
+extern cpuop_func_ce op_0e28_21_ff;
+extern cpuop_func_ce op_0e30_21_nf;
+extern cpuop_func_ce op_0e30_21_ff;
+extern cpuop_func_ce op_0e38_21_nf;
+extern cpuop_func_ce op_0e38_21_ff;
+extern cpuop_func_ce op_0e39_21_nf;
+extern cpuop_func_ce op_0e39_21_ff;
+extern cpuop_func_ce op_0e50_21_nf;
+extern cpuop_func_ce op_0e50_21_ff;
+extern cpuop_func_ce op_0e58_21_nf;
+extern cpuop_func_ce op_0e58_21_ff;
+extern cpuop_func_ce op_0e60_21_nf;
+extern cpuop_func_ce op_0e60_21_ff;
+extern cpuop_func_ce op_0e68_21_nf;
+extern cpuop_func_ce op_0e68_21_ff;
+extern cpuop_func_ce op_0e70_21_nf;
+extern cpuop_func_ce op_0e70_21_ff;
+extern cpuop_func_ce op_0e78_21_nf;
+extern cpuop_func_ce op_0e78_21_ff;
+extern cpuop_func_ce op_0e79_21_nf;
+extern cpuop_func_ce op_0e79_21_ff;
+extern cpuop_func_ce op_0e90_21_nf;
+extern cpuop_func_ce op_0e90_21_ff;
+extern cpuop_func_ce op_0e98_21_nf;
+extern cpuop_func_ce op_0e98_21_ff;
+extern cpuop_func_ce op_0ea0_21_nf;
+extern cpuop_func_ce op_0ea0_21_ff;
+extern cpuop_func_ce op_0ea8_21_nf;
+extern cpuop_func_ce op_0ea8_21_ff;
+extern cpuop_func_ce op_0eb0_21_nf;
+extern cpuop_func_ce op_0eb0_21_ff;
+extern cpuop_func_ce op_0eb8_21_nf;
+extern cpuop_func_ce op_0eb8_21_ff;
+extern cpuop_func_ce op_0eb9_21_nf;
+extern cpuop_func_ce op_0eb9_21_ff;
+extern cpuop_func_ce op_0ed0_21_nf;
+extern cpuop_func_ce op_0ed0_21_ff;
+extern cpuop_func_ce op_0ed8_21_nf;
+extern cpuop_func_ce op_0ed8_21_ff;
+extern cpuop_func_ce op_0ee0_21_nf;
+extern cpuop_func_ce op_0ee0_21_ff;
+extern cpuop_func_ce op_0ee8_21_nf;
+extern cpuop_func_ce op_0ee8_21_ff;
+extern cpuop_func_ce op_0ef0_21_nf;
+extern cpuop_func_ce op_0ef0_21_ff;
+extern cpuop_func_ce op_0ef8_21_nf;
+extern cpuop_func_ce op_0ef8_21_ff;
+extern cpuop_func_ce op_0ef9_21_nf;
+extern cpuop_func_ce op_0ef9_21_ff;
+extern cpuop_func_ce op_0efc_21_nf;
+extern cpuop_func_ce op_0efc_21_ff;
+extern cpuop_func_ce op_1000_21_nf;
+extern cpuop_func_ce op_1000_21_ff;
+extern cpuop_func_ce op_1010_21_nf;
+extern cpuop_func_ce op_1010_21_ff;
+extern cpuop_func_ce op_1018_21_nf;
+extern cpuop_func_ce op_1018_21_ff;
+extern cpuop_func_ce op_1020_21_nf;
+extern cpuop_func_ce op_1020_21_ff;
+extern cpuop_func_ce op_1028_21_nf;
+extern cpuop_func_ce op_1028_21_ff;
+extern cpuop_func_ce op_1030_21_nf;
+extern cpuop_func_ce op_1030_21_ff;
+extern cpuop_func_ce op_1038_21_nf;
+extern cpuop_func_ce op_1038_21_ff;
+extern cpuop_func_ce op_1039_21_nf;
+extern cpuop_func_ce op_1039_21_ff;
+extern cpuop_func_ce op_103a_21_nf;
+extern cpuop_func_ce op_103a_21_ff;
+extern cpuop_func_ce op_103b_21_nf;
+extern cpuop_func_ce op_103b_21_ff;
+extern cpuop_func_ce op_103c_21_nf;
+extern cpuop_func_ce op_103c_21_ff;
+extern cpuop_func_ce op_1080_21_nf;
+extern cpuop_func_ce op_1080_21_ff;
+extern cpuop_func_ce op_1090_21_nf;
+extern cpuop_func_ce op_1090_21_ff;
+extern cpuop_func_ce op_1098_21_nf;
+extern cpuop_func_ce op_1098_21_ff;
+extern cpuop_func_ce op_10a0_21_nf;
+extern cpuop_func_ce op_10a0_21_ff;
+extern cpuop_func_ce op_10a8_21_nf;
+extern cpuop_func_ce op_10a8_21_ff;
+extern cpuop_func_ce op_10b0_21_nf;
+extern cpuop_func_ce op_10b0_21_ff;
+extern cpuop_func_ce op_10b8_21_nf;
+extern cpuop_func_ce op_10b8_21_ff;
+extern cpuop_func_ce op_10b9_21_nf;
+extern cpuop_func_ce op_10b9_21_ff;
+extern cpuop_func_ce op_10ba_21_nf;
+extern cpuop_func_ce op_10ba_21_ff;
+extern cpuop_func_ce op_10bb_21_nf;
+extern cpuop_func_ce op_10bb_21_ff;
+extern cpuop_func_ce op_10bc_21_nf;
+extern cpuop_func_ce op_10bc_21_ff;
+extern cpuop_func_ce op_10c0_21_nf;
+extern cpuop_func_ce op_10c0_21_ff;
+extern cpuop_func_ce op_10d0_21_nf;
+extern cpuop_func_ce op_10d0_21_ff;
+extern cpuop_func_ce op_10d8_21_nf;
+extern cpuop_func_ce op_10d8_21_ff;
+extern cpuop_func_ce op_10e0_21_nf;
+extern cpuop_func_ce op_10e0_21_ff;
+extern cpuop_func_ce op_10e8_21_nf;
+extern cpuop_func_ce op_10e8_21_ff;
+extern cpuop_func_ce op_10f0_21_nf;
+extern cpuop_func_ce op_10f0_21_ff;
+extern cpuop_func_ce op_10f8_21_nf;
+extern cpuop_func_ce op_10f8_21_ff;
+extern cpuop_func_ce op_10f9_21_nf;
+extern cpuop_func_ce op_10f9_21_ff;
+extern cpuop_func_ce op_10fa_21_nf;
+extern cpuop_func_ce op_10fa_21_ff;
+extern cpuop_func_ce op_10fb_21_nf;
+extern cpuop_func_ce op_10fb_21_ff;
+extern cpuop_func_ce op_10fc_21_nf;
+extern cpuop_func_ce op_10fc_21_ff;
+extern cpuop_func_ce op_1100_21_nf;
+extern cpuop_func_ce op_1100_21_ff;
+extern cpuop_func_ce op_1110_21_nf;
+extern cpuop_func_ce op_1110_21_ff;
+extern cpuop_func_ce op_1118_21_nf;
+extern cpuop_func_ce op_1118_21_ff;
+extern cpuop_func_ce op_1120_21_nf;
+extern cpuop_func_ce op_1120_21_ff;
+extern cpuop_func_ce op_1128_21_nf;
+extern cpuop_func_ce op_1128_21_ff;
+extern cpuop_func_ce op_1130_21_nf;
+extern cpuop_func_ce op_1130_21_ff;
+extern cpuop_func_ce op_1138_21_nf;
+extern cpuop_func_ce op_1138_21_ff;
+extern cpuop_func_ce op_1139_21_nf;
+extern cpuop_func_ce op_1139_21_ff;
+extern cpuop_func_ce op_113a_21_nf;
+extern cpuop_func_ce op_113a_21_ff;
+extern cpuop_func_ce op_113b_21_nf;
+extern cpuop_func_ce op_113b_21_ff;
+extern cpuop_func_ce op_113c_21_nf;
+extern cpuop_func_ce op_113c_21_ff;
+extern cpuop_func_ce op_1140_21_nf;
+extern cpuop_func_ce op_1140_21_ff;
+extern cpuop_func_ce op_1150_21_nf;
+extern cpuop_func_ce op_1150_21_ff;
+extern cpuop_func_ce op_1158_21_nf;
+extern cpuop_func_ce op_1158_21_ff;
+extern cpuop_func_ce op_1160_21_nf;
+extern cpuop_func_ce op_1160_21_ff;
+extern cpuop_func_ce op_1168_21_nf;
+extern cpuop_func_ce op_1168_21_ff;
+extern cpuop_func_ce op_1170_21_nf;
+extern cpuop_func_ce op_1170_21_ff;
+extern cpuop_func_ce op_1178_21_nf;
+extern cpuop_func_ce op_1178_21_ff;
+extern cpuop_func_ce op_1179_21_nf;
+extern cpuop_func_ce op_1179_21_ff;
+extern cpuop_func_ce op_117a_21_nf;
+extern cpuop_func_ce op_117a_21_ff;
+extern cpuop_func_ce op_117b_21_nf;
+extern cpuop_func_ce op_117b_21_ff;
+extern cpuop_func_ce op_117c_21_nf;
+extern cpuop_func_ce op_117c_21_ff;
+extern cpuop_func_ce op_1180_21_nf;
+extern cpuop_func_ce op_1180_21_ff;
+extern cpuop_func_ce op_1190_21_nf;
+extern cpuop_func_ce op_1190_21_ff;
+extern cpuop_func_ce op_1198_21_nf;
+extern cpuop_func_ce op_1198_21_ff;
+extern cpuop_func_ce op_11a0_21_nf;
+extern cpuop_func_ce op_11a0_21_ff;
+extern cpuop_func_ce op_11a8_21_nf;
+extern cpuop_func_ce op_11a8_21_ff;
+extern cpuop_func_ce op_11b0_21_nf;
+extern cpuop_func_ce op_11b0_21_ff;
+extern cpuop_func_ce op_11b8_21_nf;
+extern cpuop_func_ce op_11b8_21_ff;
+extern cpuop_func_ce op_11b9_21_nf;
+extern cpuop_func_ce op_11b9_21_ff;
+extern cpuop_func_ce op_11ba_21_nf;
+extern cpuop_func_ce op_11ba_21_ff;
+extern cpuop_func_ce op_11bb_21_nf;
+extern cpuop_func_ce op_11bb_21_ff;
+extern cpuop_func_ce op_11bc_21_nf;
+extern cpuop_func_ce op_11bc_21_ff;
+extern cpuop_func_ce op_11c0_21_nf;
+extern cpuop_func_ce op_11c0_21_ff;
+extern cpuop_func_ce op_11d0_21_nf;
+extern cpuop_func_ce op_11d0_21_ff;
+extern cpuop_func_ce op_11d8_21_nf;
+extern cpuop_func_ce op_11d8_21_ff;
+extern cpuop_func_ce op_11e0_21_nf;
+extern cpuop_func_ce op_11e0_21_ff;
+extern cpuop_func_ce op_11e8_21_nf;
+extern cpuop_func_ce op_11e8_21_ff;
+extern cpuop_func_ce op_11f0_21_nf;
+extern cpuop_func_ce op_11f0_21_ff;
+extern cpuop_func_ce op_11f8_21_nf;
+extern cpuop_func_ce op_11f8_21_ff;
+extern cpuop_func_ce op_11f9_21_nf;
+extern cpuop_func_ce op_11f9_21_ff;
+extern cpuop_func_ce op_11fa_21_nf;
+extern cpuop_func_ce op_11fa_21_ff;
+extern cpuop_func_ce op_11fb_21_nf;
+extern cpuop_func_ce op_11fb_21_ff;
+extern cpuop_func_ce op_11fc_21_nf;
+extern cpuop_func_ce op_11fc_21_ff;
+extern cpuop_func_ce op_13c0_21_nf;
+extern cpuop_func_ce op_13c0_21_ff;
+extern cpuop_func_ce op_13d0_21_nf;
+extern cpuop_func_ce op_13d0_21_ff;
+extern cpuop_func_ce op_13d8_21_nf;
+extern cpuop_func_ce op_13d8_21_ff;
+extern cpuop_func_ce op_13e0_21_nf;
+extern cpuop_func_ce op_13e0_21_ff;
+extern cpuop_func_ce op_13e8_21_nf;
+extern cpuop_func_ce op_13e8_21_ff;
+extern cpuop_func_ce op_13f0_21_nf;
+extern cpuop_func_ce op_13f0_21_ff;
+extern cpuop_func_ce op_13f8_21_nf;
+extern cpuop_func_ce op_13f8_21_ff;
+extern cpuop_func_ce op_13f9_21_nf;
+extern cpuop_func_ce op_13f9_21_ff;
+extern cpuop_func_ce op_13fa_21_nf;
+extern cpuop_func_ce op_13fa_21_ff;
+extern cpuop_func_ce op_13fb_21_nf;
+extern cpuop_func_ce op_13fb_21_ff;
+extern cpuop_func_ce op_13fc_21_nf;
+extern cpuop_func_ce op_13fc_21_ff;
+extern cpuop_func_ce op_2000_21_nf;
+extern cpuop_func_ce op_2000_21_ff;
+extern cpuop_func_ce op_2008_21_nf;
+extern cpuop_func_ce op_2008_21_ff;
+extern cpuop_func_ce op_2010_21_nf;
+extern cpuop_func_ce op_2010_21_ff;
+extern cpuop_func_ce op_2018_21_nf;
+extern cpuop_func_ce op_2018_21_ff;
+extern cpuop_func_ce op_2020_21_nf;
+extern cpuop_func_ce op_2020_21_ff;
+extern cpuop_func_ce op_2028_21_nf;
+extern cpuop_func_ce op_2028_21_ff;
+extern cpuop_func_ce op_2030_21_nf;
+extern cpuop_func_ce op_2030_21_ff;
+extern cpuop_func_ce op_2038_21_nf;
+extern cpuop_func_ce op_2038_21_ff;
+extern cpuop_func_ce op_2039_21_nf;
+extern cpuop_func_ce op_2039_21_ff;
+extern cpuop_func_ce op_203a_21_nf;
+extern cpuop_func_ce op_203a_21_ff;
+extern cpuop_func_ce op_203b_21_nf;
+extern cpuop_func_ce op_203b_21_ff;
+extern cpuop_func_ce op_203c_21_nf;
+extern cpuop_func_ce op_203c_21_ff;
+extern cpuop_func_ce op_2040_21_nf;
+extern cpuop_func_ce op_2040_21_ff;
+extern cpuop_func_ce op_2048_21_nf;
+extern cpuop_func_ce op_2048_21_ff;
+extern cpuop_func_ce op_2050_21_nf;
+extern cpuop_func_ce op_2050_21_ff;
+extern cpuop_func_ce op_2058_21_nf;
+extern cpuop_func_ce op_2058_21_ff;
+extern cpuop_func_ce op_2060_21_nf;
+extern cpuop_func_ce op_2060_21_ff;
+extern cpuop_func_ce op_2068_21_nf;
+extern cpuop_func_ce op_2068_21_ff;
+extern cpuop_func_ce op_2070_21_nf;
+extern cpuop_func_ce op_2070_21_ff;
+extern cpuop_func_ce op_2078_21_nf;
+extern cpuop_func_ce op_2078_21_ff;
+extern cpuop_func_ce op_2079_21_nf;
+extern cpuop_func_ce op_2079_21_ff;
+extern cpuop_func_ce op_207a_21_nf;
+extern cpuop_func_ce op_207a_21_ff;
+extern cpuop_func_ce op_207b_21_nf;
+extern cpuop_func_ce op_207b_21_ff;
+extern cpuop_func_ce op_207c_21_nf;
+extern cpuop_func_ce op_207c_21_ff;
+extern cpuop_func_ce op_2080_21_nf;
+extern cpuop_func_ce op_2080_21_ff;
+extern cpuop_func_ce op_2088_21_nf;
+extern cpuop_func_ce op_2088_21_ff;
+extern cpuop_func_ce op_2090_21_nf;
+extern cpuop_func_ce op_2090_21_ff;
+extern cpuop_func_ce op_2098_21_nf;
+extern cpuop_func_ce op_2098_21_ff;
+extern cpuop_func_ce op_20a0_21_nf;
+extern cpuop_func_ce op_20a0_21_ff;
+extern cpuop_func_ce op_20a8_21_nf;
+extern cpuop_func_ce op_20a8_21_ff;
+extern cpuop_func_ce op_20b0_21_nf;
+extern cpuop_func_ce op_20b0_21_ff;
+extern cpuop_func_ce op_20b8_21_nf;
+extern cpuop_func_ce op_20b8_21_ff;
+extern cpuop_func_ce op_20b9_21_nf;
+extern cpuop_func_ce op_20b9_21_ff;
+extern cpuop_func_ce op_20ba_21_nf;
+extern cpuop_func_ce op_20ba_21_ff;
+extern cpuop_func_ce op_20bb_21_nf;
+extern cpuop_func_ce op_20bb_21_ff;
+extern cpuop_func_ce op_20bc_21_nf;
+extern cpuop_func_ce op_20bc_21_ff;
+extern cpuop_func_ce op_20c0_21_nf;
+extern cpuop_func_ce op_20c0_21_ff;
+extern cpuop_func_ce op_20c8_21_nf;
+extern cpuop_func_ce op_20c8_21_ff;
+extern cpuop_func_ce op_20d0_21_nf;
+extern cpuop_func_ce op_20d0_21_ff;
+extern cpuop_func_ce op_20d8_21_nf;
+extern cpuop_func_ce op_20d8_21_ff;
+extern cpuop_func_ce op_20e0_21_nf;
+extern cpuop_func_ce op_20e0_21_ff;
+extern cpuop_func_ce op_20e8_21_nf;
+extern cpuop_func_ce op_20e8_21_ff;
+extern cpuop_func_ce op_20f0_21_nf;
+extern cpuop_func_ce op_20f0_21_ff;
+extern cpuop_func_ce op_20f8_21_nf;
+extern cpuop_func_ce op_20f8_21_ff;
+extern cpuop_func_ce op_20f9_21_nf;
+extern cpuop_func_ce op_20f9_21_ff;
+extern cpuop_func_ce op_20fa_21_nf;
+extern cpuop_func_ce op_20fa_21_ff;
+extern cpuop_func_ce op_20fb_21_nf;
+extern cpuop_func_ce op_20fb_21_ff;
+extern cpuop_func_ce op_20fc_21_nf;
+extern cpuop_func_ce op_20fc_21_ff;
+extern cpuop_func_ce op_2100_21_nf;
+extern cpuop_func_ce op_2100_21_ff;
+extern cpuop_func_ce op_2108_21_nf;
+extern cpuop_func_ce op_2108_21_ff;
+extern cpuop_func_ce op_2110_21_nf;
+extern cpuop_func_ce op_2110_21_ff;
+extern cpuop_func_ce op_2118_21_nf;
+extern cpuop_func_ce op_2118_21_ff;
+extern cpuop_func_ce op_2120_21_nf;
+extern cpuop_func_ce op_2120_21_ff;
+extern cpuop_func_ce op_2128_21_nf;
+extern cpuop_func_ce op_2128_21_ff;
+extern cpuop_func_ce op_2130_21_nf;
+extern cpuop_func_ce op_2130_21_ff;
+extern cpuop_func_ce op_2138_21_nf;
+extern cpuop_func_ce op_2138_21_ff;
+extern cpuop_func_ce op_2139_21_nf;
+extern cpuop_func_ce op_2139_21_ff;
+extern cpuop_func_ce op_213a_21_nf;
+extern cpuop_func_ce op_213a_21_ff;
+extern cpuop_func_ce op_213b_21_nf;
+extern cpuop_func_ce op_213b_21_ff;
+extern cpuop_func_ce op_213c_21_nf;
+extern cpuop_func_ce op_213c_21_ff;
+extern cpuop_func_ce op_2140_21_nf;
+extern cpuop_func_ce op_2140_21_ff;
+extern cpuop_func_ce op_2148_21_nf;
+extern cpuop_func_ce op_2148_21_ff;
+extern cpuop_func_ce op_2150_21_nf;
+extern cpuop_func_ce op_2150_21_ff;
+extern cpuop_func_ce op_2158_21_nf;
+extern cpuop_func_ce op_2158_21_ff;
+extern cpuop_func_ce op_2160_21_nf;
+extern cpuop_func_ce op_2160_21_ff;
+extern cpuop_func_ce op_2168_21_nf;
+extern cpuop_func_ce op_2168_21_ff;
+extern cpuop_func_ce op_2170_21_nf;
+extern cpuop_func_ce op_2170_21_ff;
+extern cpuop_func_ce op_2178_21_nf;
+extern cpuop_func_ce op_2178_21_ff;
+extern cpuop_func_ce op_2179_21_nf;
+extern cpuop_func_ce op_2179_21_ff;
+extern cpuop_func_ce op_217a_21_nf;
+extern cpuop_func_ce op_217a_21_ff;
+extern cpuop_func_ce op_217b_21_nf;
+extern cpuop_func_ce op_217b_21_ff;
+extern cpuop_func_ce op_217c_21_nf;
+extern cpuop_func_ce op_217c_21_ff;
+extern cpuop_func_ce op_2180_21_nf;
+extern cpuop_func_ce op_2180_21_ff;
+extern cpuop_func_ce op_2188_21_nf;
+extern cpuop_func_ce op_2188_21_ff;
+extern cpuop_func_ce op_2190_21_nf;
+extern cpuop_func_ce op_2190_21_ff;
+extern cpuop_func_ce op_2198_21_nf;
+extern cpuop_func_ce op_2198_21_ff;
+extern cpuop_func_ce op_21a0_21_nf;
+extern cpuop_func_ce op_21a0_21_ff;
+extern cpuop_func_ce op_21a8_21_nf;
+extern cpuop_func_ce op_21a8_21_ff;
+extern cpuop_func_ce op_21b0_21_nf;
+extern cpuop_func_ce op_21b0_21_ff;
+extern cpuop_func_ce op_21b8_21_nf;
+extern cpuop_func_ce op_21b8_21_ff;
+extern cpuop_func_ce op_21b9_21_nf;
+extern cpuop_func_ce op_21b9_21_ff;
+extern cpuop_func_ce op_21ba_21_nf;
+extern cpuop_func_ce op_21ba_21_ff;
+extern cpuop_func_ce op_21bb_21_nf;
+extern cpuop_func_ce op_21bb_21_ff;
+extern cpuop_func_ce op_21bc_21_nf;
+extern cpuop_func_ce op_21bc_21_ff;
+extern cpuop_func_ce op_21c0_21_nf;
+extern cpuop_func_ce op_21c0_21_ff;
+extern cpuop_func_ce op_21c8_21_nf;
+extern cpuop_func_ce op_21c8_21_ff;
+extern cpuop_func_ce op_21d0_21_nf;
+extern cpuop_func_ce op_21d0_21_ff;
+extern cpuop_func_ce op_21d8_21_nf;
+extern cpuop_func_ce op_21d8_21_ff;
+extern cpuop_func_ce op_21e0_21_nf;
+extern cpuop_func_ce op_21e0_21_ff;
+extern cpuop_func_ce op_21e8_21_nf;
+extern cpuop_func_ce op_21e8_21_ff;
+extern cpuop_func_ce op_21f0_21_nf;
+extern cpuop_func_ce op_21f0_21_ff;
+extern cpuop_func_ce op_21f8_21_nf;
+extern cpuop_func_ce op_21f8_21_ff;
+extern cpuop_func_ce op_21f9_21_nf;
+extern cpuop_func_ce op_21f9_21_ff;
+extern cpuop_func_ce op_21fa_21_nf;
+extern cpuop_func_ce op_21fa_21_ff;
+extern cpuop_func_ce op_21fb_21_nf;
+extern cpuop_func_ce op_21fb_21_ff;
+extern cpuop_func_ce op_21fc_21_nf;
+extern cpuop_func_ce op_21fc_21_ff;
+extern cpuop_func_ce op_23c0_21_nf;
+extern cpuop_func_ce op_23c0_21_ff;
+extern cpuop_func_ce op_23c8_21_nf;
+extern cpuop_func_ce op_23c8_21_ff;
+extern cpuop_func_ce op_23d0_21_nf;
+extern cpuop_func_ce op_23d0_21_ff;
+extern cpuop_func_ce op_23d8_21_nf;
+extern cpuop_func_ce op_23d8_21_ff;
+extern cpuop_func_ce op_23e0_21_nf;
+extern cpuop_func_ce op_23e0_21_ff;
+extern cpuop_func_ce op_23e8_21_nf;
+extern cpuop_func_ce op_23e8_21_ff;
+extern cpuop_func_ce op_23f0_21_nf;
+extern cpuop_func_ce op_23f0_21_ff;
+extern cpuop_func_ce op_23f8_21_nf;
+extern cpuop_func_ce op_23f8_21_ff;
+extern cpuop_func_ce op_23f9_21_nf;
+extern cpuop_func_ce op_23f9_21_ff;
+extern cpuop_func_ce op_23fa_21_nf;
+extern cpuop_func_ce op_23fa_21_ff;
+extern cpuop_func_ce op_23fb_21_nf;
+extern cpuop_func_ce op_23fb_21_ff;
+extern cpuop_func_ce op_23fc_21_nf;
+extern cpuop_func_ce op_23fc_21_ff;
+extern cpuop_func_ce op_3000_21_nf;
+extern cpuop_func_ce op_3000_21_ff;
+extern cpuop_func_ce op_3008_21_nf;
+extern cpuop_func_ce op_3008_21_ff;
+extern cpuop_func_ce op_3010_21_nf;
+extern cpuop_func_ce op_3010_21_ff;
+extern cpuop_func_ce op_3018_21_nf;
+extern cpuop_func_ce op_3018_21_ff;
+extern cpuop_func_ce op_3020_21_nf;
+extern cpuop_func_ce op_3020_21_ff;
+extern cpuop_func_ce op_3028_21_nf;
+extern cpuop_func_ce op_3028_21_ff;
+extern cpuop_func_ce op_3030_21_nf;
+extern cpuop_func_ce op_3030_21_ff;
+extern cpuop_func_ce op_3038_21_nf;
+extern cpuop_func_ce op_3038_21_ff;
+extern cpuop_func_ce op_3039_21_nf;
+extern cpuop_func_ce op_3039_21_ff;
+extern cpuop_func_ce op_303a_21_nf;
+extern cpuop_func_ce op_303a_21_ff;
+extern cpuop_func_ce op_303b_21_nf;
+extern cpuop_func_ce op_303b_21_ff;
+extern cpuop_func_ce op_303c_21_nf;
+extern cpuop_func_ce op_303c_21_ff;
+extern cpuop_func_ce op_3040_21_nf;
+extern cpuop_func_ce op_3040_21_ff;
+extern cpuop_func_ce op_3048_21_nf;
+extern cpuop_func_ce op_3048_21_ff;
+extern cpuop_func_ce op_3050_21_nf;
+extern cpuop_func_ce op_3050_21_ff;
+extern cpuop_func_ce op_3058_21_nf;
+extern cpuop_func_ce op_3058_21_ff;
+extern cpuop_func_ce op_3060_21_nf;
+extern cpuop_func_ce op_3060_21_ff;
+extern cpuop_func_ce op_3068_21_nf;
+extern cpuop_func_ce op_3068_21_ff;
+extern cpuop_func_ce op_3070_21_nf;
+extern cpuop_func_ce op_3070_21_ff;
+extern cpuop_func_ce op_3078_21_nf;
+extern cpuop_func_ce op_3078_21_ff;
+extern cpuop_func_ce op_3079_21_nf;
+extern cpuop_func_ce op_3079_21_ff;
+extern cpuop_func_ce op_307a_21_nf;
+extern cpuop_func_ce op_307a_21_ff;
+extern cpuop_func_ce op_307b_21_nf;
+extern cpuop_func_ce op_307b_21_ff;
+extern cpuop_func_ce op_307c_21_nf;
+extern cpuop_func_ce op_307c_21_ff;
+extern cpuop_func_ce op_3080_21_nf;
+extern cpuop_func_ce op_3080_21_ff;
+extern cpuop_func_ce op_3088_21_nf;
+extern cpuop_func_ce op_3088_21_ff;
+extern cpuop_func_ce op_3090_21_nf;
+extern cpuop_func_ce op_3090_21_ff;
+extern cpuop_func_ce op_3098_21_nf;
+extern cpuop_func_ce op_3098_21_ff;
+extern cpuop_func_ce op_30a0_21_nf;
+extern cpuop_func_ce op_30a0_21_ff;
+extern cpuop_func_ce op_30a8_21_nf;
+extern cpuop_func_ce op_30a8_21_ff;
+extern cpuop_func_ce op_30b0_21_nf;
+extern cpuop_func_ce op_30b0_21_ff;
+extern cpuop_func_ce op_30b8_21_nf;
+extern cpuop_func_ce op_30b8_21_ff;
+extern cpuop_func_ce op_30b9_21_nf;
+extern cpuop_func_ce op_30b9_21_ff;
+extern cpuop_func_ce op_30ba_21_nf;
+extern cpuop_func_ce op_30ba_21_ff;
+extern cpuop_func_ce op_30bb_21_nf;
+extern cpuop_func_ce op_30bb_21_ff;
+extern cpuop_func_ce op_30bc_21_nf;
+extern cpuop_func_ce op_30bc_21_ff;
+extern cpuop_func_ce op_30c0_21_nf;
+extern cpuop_func_ce op_30c0_21_ff;
+extern cpuop_func_ce op_30c8_21_nf;
+extern cpuop_func_ce op_30c8_21_ff;
+extern cpuop_func_ce op_30d0_21_nf;
+extern cpuop_func_ce op_30d0_21_ff;
+extern cpuop_func_ce op_30d8_21_nf;
+extern cpuop_func_ce op_30d8_21_ff;
+extern cpuop_func_ce op_30e0_21_nf;
+extern cpuop_func_ce op_30e0_21_ff;
+extern cpuop_func_ce op_30e8_21_nf;
+extern cpuop_func_ce op_30e8_21_ff;
+extern cpuop_func_ce op_30f0_21_nf;
+extern cpuop_func_ce op_30f0_21_ff;
+extern cpuop_func_ce op_30f8_21_nf;
+extern cpuop_func_ce op_30f8_21_ff;
+extern cpuop_func_ce op_30f9_21_nf;
+extern cpuop_func_ce op_30f9_21_ff;
+extern cpuop_func_ce op_30fa_21_nf;
+extern cpuop_func_ce op_30fa_21_ff;
+extern cpuop_func_ce op_30fb_21_nf;
+extern cpuop_func_ce op_30fb_21_ff;
+extern cpuop_func_ce op_30fc_21_nf;
+extern cpuop_func_ce op_30fc_21_ff;
+extern cpuop_func_ce op_3100_21_nf;
+extern cpuop_func_ce op_3100_21_ff;
+extern cpuop_func_ce op_3108_21_nf;
+extern cpuop_func_ce op_3108_21_ff;
+extern cpuop_func_ce op_3110_21_nf;
+extern cpuop_func_ce op_3110_21_ff;
+extern cpuop_func_ce op_3118_21_nf;
+extern cpuop_func_ce op_3118_21_ff;
+extern cpuop_func_ce op_3120_21_nf;
+extern cpuop_func_ce op_3120_21_ff;
+extern cpuop_func_ce op_3128_21_nf;
+extern cpuop_func_ce op_3128_21_ff;
+extern cpuop_func_ce op_3130_21_nf;
+extern cpuop_func_ce op_3130_21_ff;
+extern cpuop_func_ce op_3138_21_nf;
+extern cpuop_func_ce op_3138_21_ff;
+extern cpuop_func_ce op_3139_21_nf;
+extern cpuop_func_ce op_3139_21_ff;
+extern cpuop_func_ce op_313a_21_nf;
+extern cpuop_func_ce op_313a_21_ff;
+extern cpuop_func_ce op_313b_21_nf;
+extern cpuop_func_ce op_313b_21_ff;
+extern cpuop_func_ce op_313c_21_nf;
+extern cpuop_func_ce op_313c_21_ff;
+extern cpuop_func_ce op_3140_21_nf;
+extern cpuop_func_ce op_3140_21_ff;
+extern cpuop_func_ce op_3148_21_nf;
+extern cpuop_func_ce op_3148_21_ff;
+extern cpuop_func_ce op_3150_21_nf;
+extern cpuop_func_ce op_3150_21_ff;
+extern cpuop_func_ce op_3158_21_nf;
+extern cpuop_func_ce op_3158_21_ff;
+extern cpuop_func_ce op_3160_21_nf;
+extern cpuop_func_ce op_3160_21_ff;
+extern cpuop_func_ce op_3168_21_nf;
+extern cpuop_func_ce op_3168_21_ff;
+extern cpuop_func_ce op_3170_21_nf;
+extern cpuop_func_ce op_3170_21_ff;
+extern cpuop_func_ce op_3178_21_nf;
+extern cpuop_func_ce op_3178_21_ff;
+extern cpuop_func_ce op_3179_21_nf;
+extern cpuop_func_ce op_3179_21_ff;
+extern cpuop_func_ce op_317a_21_nf;
+extern cpuop_func_ce op_317a_21_ff;
+extern cpuop_func_ce op_317b_21_nf;
+extern cpuop_func_ce op_317b_21_ff;
+extern cpuop_func_ce op_317c_21_nf;
+extern cpuop_func_ce op_317c_21_ff;
+extern cpuop_func_ce op_3180_21_nf;
+extern cpuop_func_ce op_3180_21_ff;
+extern cpuop_func_ce op_3188_21_nf;
+extern cpuop_func_ce op_3188_21_ff;
+extern cpuop_func_ce op_3190_21_nf;
+extern cpuop_func_ce op_3190_21_ff;
+extern cpuop_func_ce op_3198_21_nf;
+extern cpuop_func_ce op_3198_21_ff;
+extern cpuop_func_ce op_31a0_21_nf;
+extern cpuop_func_ce op_31a0_21_ff;
+extern cpuop_func_ce op_31a8_21_nf;
+extern cpuop_func_ce op_31a8_21_ff;
+extern cpuop_func_ce op_31b0_21_nf;
+extern cpuop_func_ce op_31b0_21_ff;
+extern cpuop_func_ce op_31b8_21_nf;
+extern cpuop_func_ce op_31b8_21_ff;
+extern cpuop_func_ce op_31b9_21_nf;
+extern cpuop_func_ce op_31b9_21_ff;
+extern cpuop_func_ce op_31ba_21_nf;
+extern cpuop_func_ce op_31ba_21_ff;
+extern cpuop_func_ce op_31bb_21_nf;
+extern cpuop_func_ce op_31bb_21_ff;
+extern cpuop_func_ce op_31bc_21_nf;
+extern cpuop_func_ce op_31bc_21_ff;
+extern cpuop_func_ce op_31c0_21_nf;
+extern cpuop_func_ce op_31c0_21_ff;
+extern cpuop_func_ce op_31c8_21_nf;
+extern cpuop_func_ce op_31c8_21_ff;
+extern cpuop_func_ce op_31d0_21_nf;
+extern cpuop_func_ce op_31d0_21_ff;
+extern cpuop_func_ce op_31d8_21_nf;
+extern cpuop_func_ce op_31d8_21_ff;
+extern cpuop_func_ce op_31e0_21_nf;
+extern cpuop_func_ce op_31e0_21_ff;
+extern cpuop_func_ce op_31e8_21_nf;
+extern cpuop_func_ce op_31e8_21_ff;
+extern cpuop_func_ce op_31f0_21_nf;
+extern cpuop_func_ce op_31f0_21_ff;
+extern cpuop_func_ce op_31f8_21_nf;
+extern cpuop_func_ce op_31f8_21_ff;
+extern cpuop_func_ce op_31f9_21_nf;
+extern cpuop_func_ce op_31f9_21_ff;
+extern cpuop_func_ce op_31fa_21_nf;
+extern cpuop_func_ce op_31fa_21_ff;
+extern cpuop_func_ce op_31fb_21_nf;
+extern cpuop_func_ce op_31fb_21_ff;
+extern cpuop_func_ce op_31fc_21_nf;
+extern cpuop_func_ce op_31fc_21_ff;
+extern cpuop_func_ce op_33c0_21_nf;
+extern cpuop_func_ce op_33c0_21_ff;
+extern cpuop_func_ce op_33c8_21_nf;
+extern cpuop_func_ce op_33c8_21_ff;
+extern cpuop_func_ce op_33d0_21_nf;
+extern cpuop_func_ce op_33d0_21_ff;
+extern cpuop_func_ce op_33d8_21_nf;
+extern cpuop_func_ce op_33d8_21_ff;
+extern cpuop_func_ce op_33e0_21_nf;
+extern cpuop_func_ce op_33e0_21_ff;
+extern cpuop_func_ce op_33e8_21_nf;
+extern cpuop_func_ce op_33e8_21_ff;
+extern cpuop_func_ce op_33f0_21_nf;
+extern cpuop_func_ce op_33f0_21_ff;
+extern cpuop_func_ce op_33f8_21_nf;
+extern cpuop_func_ce op_33f8_21_ff;
+extern cpuop_func_ce op_33f9_21_nf;
+extern cpuop_func_ce op_33f9_21_ff;
+extern cpuop_func_ce op_33fa_21_nf;
+extern cpuop_func_ce op_33fa_21_ff;
+extern cpuop_func_ce op_33fb_21_nf;
+extern cpuop_func_ce op_33fb_21_ff;
+extern cpuop_func_ce op_33fc_21_nf;
+extern cpuop_func_ce op_33fc_21_ff;
+extern cpuop_func_ce op_4000_21_nf;
+extern cpuop_func_ce op_4000_21_ff;
+extern cpuop_func_ce op_4010_21_nf;
+extern cpuop_func_ce op_4010_21_ff;
+extern cpuop_func_ce op_4018_21_nf;
+extern cpuop_func_ce op_4018_21_ff;
+extern cpuop_func_ce op_4020_21_nf;
+extern cpuop_func_ce op_4020_21_ff;
+extern cpuop_func_ce op_4028_21_nf;
+extern cpuop_func_ce op_4028_21_ff;
+extern cpuop_func_ce op_4030_21_nf;
+extern cpuop_func_ce op_4030_21_ff;
+extern cpuop_func_ce op_4038_21_nf;
+extern cpuop_func_ce op_4038_21_ff;
+extern cpuop_func_ce op_4039_21_nf;
+extern cpuop_func_ce op_4039_21_ff;
+extern cpuop_func_ce op_4040_21_nf;
+extern cpuop_func_ce op_4040_21_ff;
+extern cpuop_func_ce op_4050_21_nf;
+extern cpuop_func_ce op_4050_21_ff;
+extern cpuop_func_ce op_4058_21_nf;
+extern cpuop_func_ce op_4058_21_ff;
+extern cpuop_func_ce op_4060_21_nf;
+extern cpuop_func_ce op_4060_21_ff;
+extern cpuop_func_ce op_4068_21_nf;
+extern cpuop_func_ce op_4068_21_ff;
+extern cpuop_func_ce op_4070_21_nf;
+extern cpuop_func_ce op_4070_21_ff;
+extern cpuop_func_ce op_4078_21_nf;
+extern cpuop_func_ce op_4078_21_ff;
+extern cpuop_func_ce op_4079_21_nf;
+extern cpuop_func_ce op_4079_21_ff;
+extern cpuop_func_ce op_4080_21_nf;
+extern cpuop_func_ce op_4080_21_ff;
+extern cpuop_func_ce op_4090_21_nf;
+extern cpuop_func_ce op_4090_21_ff;
+extern cpuop_func_ce op_4098_21_nf;
+extern cpuop_func_ce op_4098_21_ff;
+extern cpuop_func_ce op_40a0_21_nf;
+extern cpuop_func_ce op_40a0_21_ff;
+extern cpuop_func_ce op_40a8_21_nf;
+extern cpuop_func_ce op_40a8_21_ff;
+extern cpuop_func_ce op_40b0_21_nf;
+extern cpuop_func_ce op_40b0_21_ff;
+extern cpuop_func_ce op_40b8_21_nf;
+extern cpuop_func_ce op_40b8_21_ff;
+extern cpuop_func_ce op_40b9_21_nf;
+extern cpuop_func_ce op_40b9_21_ff;
+extern cpuop_func_ce op_40c0_21_nf;
+extern cpuop_func_ce op_40c0_21_ff;
+extern cpuop_func_ce op_40d0_21_nf;
+extern cpuop_func_ce op_40d0_21_ff;
+extern cpuop_func_ce op_40d8_21_nf;
+extern cpuop_func_ce op_40d8_21_ff;
+extern cpuop_func_ce op_40e0_21_nf;
+extern cpuop_func_ce op_40e0_21_ff;
+extern cpuop_func_ce op_40e8_21_nf;
+extern cpuop_func_ce op_40e8_21_ff;
+extern cpuop_func_ce op_40f0_21_nf;
+extern cpuop_func_ce op_40f0_21_ff;
+extern cpuop_func_ce op_40f8_21_nf;
+extern cpuop_func_ce op_40f8_21_ff;
+extern cpuop_func_ce op_40f9_21_nf;
+extern cpuop_func_ce op_40f9_21_ff;
+extern cpuop_func_ce op_4100_21_nf;
+extern cpuop_func_ce op_4100_21_ff;
+extern cpuop_func_ce op_4110_21_nf;
+extern cpuop_func_ce op_4110_21_ff;
+extern cpuop_func_ce op_4118_21_nf;
+extern cpuop_func_ce op_4118_21_ff;
+extern cpuop_func_ce op_4120_21_nf;
+extern cpuop_func_ce op_4120_21_ff;
+extern cpuop_func_ce op_4128_21_nf;
+extern cpuop_func_ce op_4128_21_ff;
+extern cpuop_func_ce op_4130_21_nf;
+extern cpuop_func_ce op_4130_21_ff;
+extern cpuop_func_ce op_4138_21_nf;
+extern cpuop_func_ce op_4138_21_ff;
+extern cpuop_func_ce op_4139_21_nf;
+extern cpuop_func_ce op_4139_21_ff;
+extern cpuop_func_ce op_413a_21_nf;
+extern cpuop_func_ce op_413a_21_ff;
+extern cpuop_func_ce op_413b_21_nf;
+extern cpuop_func_ce op_413b_21_ff;
+extern cpuop_func_ce op_413c_21_nf;
+extern cpuop_func_ce op_413c_21_ff;
+extern cpuop_func_ce op_4180_21_nf;
+extern cpuop_func_ce op_4180_21_ff;
+extern cpuop_func_ce op_4190_21_nf;
+extern cpuop_func_ce op_4190_21_ff;
+extern cpuop_func_ce op_4198_21_nf;
+extern cpuop_func_ce op_4198_21_ff;
+extern cpuop_func_ce op_41a0_21_nf;
+extern cpuop_func_ce op_41a0_21_ff;
+extern cpuop_func_ce op_41a8_21_nf;
+extern cpuop_func_ce op_41a8_21_ff;
+extern cpuop_func_ce op_41b0_21_nf;
+extern cpuop_func_ce op_41b0_21_ff;
+extern cpuop_func_ce op_41b8_21_nf;
+extern cpuop_func_ce op_41b8_21_ff;
+extern cpuop_func_ce op_41b9_21_nf;
+extern cpuop_func_ce op_41b9_21_ff;
+extern cpuop_func_ce op_41ba_21_nf;
+extern cpuop_func_ce op_41ba_21_ff;
+extern cpuop_func_ce op_41bb_21_nf;
+extern cpuop_func_ce op_41bb_21_ff;
+extern cpuop_func_ce op_41bc_21_nf;
+extern cpuop_func_ce op_41bc_21_ff;
+extern cpuop_func_ce op_41d0_21_nf;
+extern cpuop_func_ce op_41d0_21_ff;
+extern cpuop_func_ce op_41e8_21_nf;
+extern cpuop_func_ce op_41e8_21_ff;
+extern cpuop_func_ce op_41f0_21_nf;
+extern cpuop_func_ce op_41f0_21_ff;
+extern cpuop_func_ce op_41f8_21_nf;
+extern cpuop_func_ce op_41f8_21_ff;
+extern cpuop_func_ce op_41f9_21_nf;
+extern cpuop_func_ce op_41f9_21_ff;
+extern cpuop_func_ce op_41fa_21_nf;
+extern cpuop_func_ce op_41fa_21_ff;
+extern cpuop_func_ce op_41fb_21_nf;
+extern cpuop_func_ce op_41fb_21_ff;
+extern cpuop_func_ce op_4200_21_nf;
+extern cpuop_func_ce op_4200_21_ff;
+extern cpuop_func_ce op_4210_21_nf;
+extern cpuop_func_ce op_4210_21_ff;
+extern cpuop_func_ce op_4218_21_nf;
+extern cpuop_func_ce op_4218_21_ff;
+extern cpuop_func_ce op_4220_21_nf;
+extern cpuop_func_ce op_4220_21_ff;
+extern cpuop_func_ce op_4228_21_nf;
+extern cpuop_func_ce op_4228_21_ff;
+extern cpuop_func_ce op_4230_21_nf;
+extern cpuop_func_ce op_4230_21_ff;
+extern cpuop_func_ce op_4238_21_nf;
+extern cpuop_func_ce op_4238_21_ff;
+extern cpuop_func_ce op_4239_21_nf;
+extern cpuop_func_ce op_4239_21_ff;
+extern cpuop_func_ce op_4240_21_nf;
+extern cpuop_func_ce op_4240_21_ff;
+extern cpuop_func_ce op_4250_21_nf;
+extern cpuop_func_ce op_4250_21_ff;
+extern cpuop_func_ce op_4258_21_nf;
+extern cpuop_func_ce op_4258_21_ff;
+extern cpuop_func_ce op_4260_21_nf;
+extern cpuop_func_ce op_4260_21_ff;
+extern cpuop_func_ce op_4268_21_nf;
+extern cpuop_func_ce op_4268_21_ff;
+extern cpuop_func_ce op_4270_21_nf;
+extern cpuop_func_ce op_4270_21_ff;
+extern cpuop_func_ce op_4278_21_nf;
+extern cpuop_func_ce op_4278_21_ff;
+extern cpuop_func_ce op_4279_21_nf;
+extern cpuop_func_ce op_4279_21_ff;
+extern cpuop_func_ce op_4280_21_nf;
+extern cpuop_func_ce op_4280_21_ff;
+extern cpuop_func_ce op_4290_21_nf;
+extern cpuop_func_ce op_4290_21_ff;
+extern cpuop_func_ce op_4298_21_nf;
+extern cpuop_func_ce op_4298_21_ff;
+extern cpuop_func_ce op_42a0_21_nf;
+extern cpuop_func_ce op_42a0_21_ff;
+extern cpuop_func_ce op_42a8_21_nf;
+extern cpuop_func_ce op_42a8_21_ff;
+extern cpuop_func_ce op_42b0_21_nf;
+extern cpuop_func_ce op_42b0_21_ff;
+extern cpuop_func_ce op_42b8_21_nf;
+extern cpuop_func_ce op_42b8_21_ff;
+extern cpuop_func_ce op_42b9_21_nf;
+extern cpuop_func_ce op_42b9_21_ff;
+extern cpuop_func_ce op_42c0_21_nf;
+extern cpuop_func_ce op_42c0_21_ff;
+extern cpuop_func_ce op_42d0_21_nf;
+extern cpuop_func_ce op_42d0_21_ff;
+extern cpuop_func_ce op_42d8_21_nf;
+extern cpuop_func_ce op_42d8_21_ff;
+extern cpuop_func_ce op_42e0_21_nf;
+extern cpuop_func_ce op_42e0_21_ff;
+extern cpuop_func_ce op_42e8_21_nf;
+extern cpuop_func_ce op_42e8_21_ff;
+extern cpuop_func_ce op_42f0_21_nf;
+extern cpuop_func_ce op_42f0_21_ff;
+extern cpuop_func_ce op_42f8_21_nf;
+extern cpuop_func_ce op_42f8_21_ff;
+extern cpuop_func_ce op_42f9_21_nf;
+extern cpuop_func_ce op_42f9_21_ff;
+extern cpuop_func_ce op_4400_21_nf;
+extern cpuop_func_ce op_4400_21_ff;
+extern cpuop_func_ce op_4410_21_nf;
+extern cpuop_func_ce op_4410_21_ff;
+extern cpuop_func_ce op_4418_21_nf;
+extern cpuop_func_ce op_4418_21_ff;
+extern cpuop_func_ce op_4420_21_nf;
+extern cpuop_func_ce op_4420_21_ff;
+extern cpuop_func_ce op_4428_21_nf;
+extern cpuop_func_ce op_4428_21_ff;
+extern cpuop_func_ce op_4430_21_nf;
+extern cpuop_func_ce op_4430_21_ff;
+extern cpuop_func_ce op_4438_21_nf;
+extern cpuop_func_ce op_4438_21_ff;
+extern cpuop_func_ce op_4439_21_nf;
+extern cpuop_func_ce op_4439_21_ff;
+extern cpuop_func_ce op_4440_21_nf;
+extern cpuop_func_ce op_4440_21_ff;
+extern cpuop_func_ce op_4450_21_nf;
+extern cpuop_func_ce op_4450_21_ff;
+extern cpuop_func_ce op_4458_21_nf;
+extern cpuop_func_ce op_4458_21_ff;
+extern cpuop_func_ce op_4460_21_nf;
+extern cpuop_func_ce op_4460_21_ff;
+extern cpuop_func_ce op_4468_21_nf;
+extern cpuop_func_ce op_4468_21_ff;
+extern cpuop_func_ce op_4470_21_nf;
+extern cpuop_func_ce op_4470_21_ff;
+extern cpuop_func_ce op_4478_21_nf;
+extern cpuop_func_ce op_4478_21_ff;
+extern cpuop_func_ce op_4479_21_nf;
+extern cpuop_func_ce op_4479_21_ff;
+extern cpuop_func_ce op_4480_21_nf;
+extern cpuop_func_ce op_4480_21_ff;
+extern cpuop_func_ce op_4490_21_nf;
+extern cpuop_func_ce op_4490_21_ff;
+extern cpuop_func_ce op_4498_21_nf;
+extern cpuop_func_ce op_4498_21_ff;
+extern cpuop_func_ce op_44a0_21_nf;
+extern cpuop_func_ce op_44a0_21_ff;
+extern cpuop_func_ce op_44a8_21_nf;
+extern cpuop_func_ce op_44a8_21_ff;
+extern cpuop_func_ce op_44b0_21_nf;
+extern cpuop_func_ce op_44b0_21_ff;
+extern cpuop_func_ce op_44b8_21_nf;
+extern cpuop_func_ce op_44b8_21_ff;
+extern cpuop_func_ce op_44b9_21_nf;
+extern cpuop_func_ce op_44b9_21_ff;
+extern cpuop_func_ce op_44c0_21_nf;
+extern cpuop_func_ce op_44c0_21_ff;
+extern cpuop_func_ce op_44d0_21_nf;
+extern cpuop_func_ce op_44d0_21_ff;
+extern cpuop_func_ce op_44d8_21_nf;
+extern cpuop_func_ce op_44d8_21_ff;
+extern cpuop_func_ce op_44e0_21_nf;
+extern cpuop_func_ce op_44e0_21_ff;
+extern cpuop_func_ce op_44e8_21_nf;
+extern cpuop_func_ce op_44e8_21_ff;
+extern cpuop_func_ce op_44f0_21_nf;
+extern cpuop_func_ce op_44f0_21_ff;
+extern cpuop_func_ce op_44f8_21_nf;
+extern cpuop_func_ce op_44f8_21_ff;
+extern cpuop_func_ce op_44f9_21_nf;
+extern cpuop_func_ce op_44f9_21_ff;
+extern cpuop_func_ce op_44fa_21_nf;
+extern cpuop_func_ce op_44fa_21_ff;
+extern cpuop_func_ce op_44fb_21_nf;
+extern cpuop_func_ce op_44fb_21_ff;
+extern cpuop_func_ce op_44fc_21_nf;
+extern cpuop_func_ce op_44fc_21_ff;
+extern cpuop_func_ce op_4600_21_nf;
+extern cpuop_func_ce op_4600_21_ff;
+extern cpuop_func_ce op_4610_21_nf;
+extern cpuop_func_ce op_4610_21_ff;
+extern cpuop_func_ce op_4618_21_nf;
+extern cpuop_func_ce op_4618_21_ff;
+extern cpuop_func_ce op_4620_21_nf;
+extern cpuop_func_ce op_4620_21_ff;
+extern cpuop_func_ce op_4628_21_nf;
+extern cpuop_func_ce op_4628_21_ff;
+extern cpuop_func_ce op_4630_21_nf;
+extern cpuop_func_ce op_4630_21_ff;
+extern cpuop_func_ce op_4638_21_nf;
+extern cpuop_func_ce op_4638_21_ff;
+extern cpuop_func_ce op_4639_21_nf;
+extern cpuop_func_ce op_4639_21_ff;
+extern cpuop_func_ce op_4640_21_nf;
+extern cpuop_func_ce op_4640_21_ff;
+extern cpuop_func_ce op_4650_21_nf;
+extern cpuop_func_ce op_4650_21_ff;
+extern cpuop_func_ce op_4658_21_nf;
+extern cpuop_func_ce op_4658_21_ff;
+extern cpuop_func_ce op_4660_21_nf;
+extern cpuop_func_ce op_4660_21_ff;
+extern cpuop_func_ce op_4668_21_nf;
+extern cpuop_func_ce op_4668_21_ff;
+extern cpuop_func_ce op_4670_21_nf;
+extern cpuop_func_ce op_4670_21_ff;
+extern cpuop_func_ce op_4678_21_nf;
+extern cpuop_func_ce op_4678_21_ff;
+extern cpuop_func_ce op_4679_21_nf;
+extern cpuop_func_ce op_4679_21_ff;
+extern cpuop_func_ce op_4680_21_nf;
+extern cpuop_func_ce op_4680_21_ff;
+extern cpuop_func_ce op_4690_21_nf;
+extern cpuop_func_ce op_4690_21_ff;
+extern cpuop_func_ce op_4698_21_nf;
+extern cpuop_func_ce op_4698_21_ff;
+extern cpuop_func_ce op_46a0_21_nf;
+extern cpuop_func_ce op_46a0_21_ff;
+extern cpuop_func_ce op_46a8_21_nf;
+extern cpuop_func_ce op_46a8_21_ff;
+extern cpuop_func_ce op_46b0_21_nf;
+extern cpuop_func_ce op_46b0_21_ff;
+extern cpuop_func_ce op_46b8_21_nf;
+extern cpuop_func_ce op_46b8_21_ff;
+extern cpuop_func_ce op_46b9_21_nf;
+extern cpuop_func_ce op_46b9_21_ff;
+extern cpuop_func_ce op_46c0_21_nf;
+extern cpuop_func_ce op_46c0_21_ff;
+extern cpuop_func_ce op_46d0_21_nf;
+extern cpuop_func_ce op_46d0_21_ff;
+extern cpuop_func_ce op_46d8_21_nf;
+extern cpuop_func_ce op_46d8_21_ff;
+extern cpuop_func_ce op_46e0_21_nf;
+extern cpuop_func_ce op_46e0_21_ff;
+extern cpuop_func_ce op_46e8_21_nf;
+extern cpuop_func_ce op_46e8_21_ff;
+extern cpuop_func_ce op_46f0_21_nf;
+extern cpuop_func_ce op_46f0_21_ff;
+extern cpuop_func_ce op_46f8_21_nf;
+extern cpuop_func_ce op_46f8_21_ff;
+extern cpuop_func_ce op_46f9_21_nf;
+extern cpuop_func_ce op_46f9_21_ff;
+extern cpuop_func_ce op_46fa_21_nf;
+extern cpuop_func_ce op_46fa_21_ff;
+extern cpuop_func_ce op_46fb_21_nf;
+extern cpuop_func_ce op_46fb_21_ff;
+extern cpuop_func_ce op_46fc_21_nf;
+extern cpuop_func_ce op_46fc_21_ff;
+extern cpuop_func_ce op_4800_21_nf;
+extern cpuop_func_ce op_4800_21_ff;
+extern cpuop_func_ce op_4808_21_nf;
+extern cpuop_func_ce op_4808_21_ff;
+extern cpuop_func_ce op_4810_21_nf;
+extern cpuop_func_ce op_4810_21_ff;
+extern cpuop_func_ce op_4818_21_nf;
+extern cpuop_func_ce op_4818_21_ff;
+extern cpuop_func_ce op_4820_21_nf;
+extern cpuop_func_ce op_4820_21_ff;
+extern cpuop_func_ce op_4828_21_nf;
+extern cpuop_func_ce op_4828_21_ff;
+extern cpuop_func_ce op_4830_21_nf;
+extern cpuop_func_ce op_4830_21_ff;
+extern cpuop_func_ce op_4838_21_nf;
+extern cpuop_func_ce op_4838_21_ff;
+extern cpuop_func_ce op_4839_21_nf;
+extern cpuop_func_ce op_4839_21_ff;
+extern cpuop_func_ce op_4840_21_nf;
+extern cpuop_func_ce op_4840_21_ff;
+extern cpuop_func_ce op_4848_21_nf;
+extern cpuop_func_ce op_4848_21_ff;
+extern cpuop_func_ce op_4850_21_nf;
+extern cpuop_func_ce op_4850_21_ff;
+extern cpuop_func_ce op_4868_21_nf;
+extern cpuop_func_ce op_4868_21_ff;
+extern cpuop_func_ce op_4870_21_nf;
+extern cpuop_func_ce op_4870_21_ff;
+extern cpuop_func_ce op_4878_21_nf;
+extern cpuop_func_ce op_4878_21_ff;
+extern cpuop_func_ce op_4879_21_nf;
+extern cpuop_func_ce op_4879_21_ff;
+extern cpuop_func_ce op_487a_21_nf;
+extern cpuop_func_ce op_487a_21_ff;
+extern cpuop_func_ce op_487b_21_nf;
+extern cpuop_func_ce op_487b_21_ff;
+extern cpuop_func_ce op_4880_21_nf;
+extern cpuop_func_ce op_4880_21_ff;
+extern cpuop_func_ce op_4890_21_nf;
+extern cpuop_func_ce op_4890_21_ff;
+extern cpuop_func_ce op_48a0_21_nf;
+extern cpuop_func_ce op_48a0_21_ff;
+extern cpuop_func_ce op_48a8_21_nf;
+extern cpuop_func_ce op_48a8_21_ff;
+extern cpuop_func_ce op_48b0_21_nf;
+extern cpuop_func_ce op_48b0_21_ff;
+extern cpuop_func_ce op_48b8_21_nf;
+extern cpuop_func_ce op_48b8_21_ff;
+extern cpuop_func_ce op_48b9_21_nf;
+extern cpuop_func_ce op_48b9_21_ff;
+extern cpuop_func_ce op_48c0_21_nf;
+extern cpuop_func_ce op_48c0_21_ff;
+extern cpuop_func_ce op_48d0_21_nf;
+extern cpuop_func_ce op_48d0_21_ff;
+extern cpuop_func_ce op_48e0_21_nf;
+extern cpuop_func_ce op_48e0_21_ff;
+extern cpuop_func_ce op_48e8_21_nf;
+extern cpuop_func_ce op_48e8_21_ff;
+extern cpuop_func_ce op_48f0_21_nf;
+extern cpuop_func_ce op_48f0_21_ff;
+extern cpuop_func_ce op_48f8_21_nf;
+extern cpuop_func_ce op_48f8_21_ff;
+extern cpuop_func_ce op_48f9_21_nf;
+extern cpuop_func_ce op_48f9_21_ff;
+extern cpuop_func_ce op_49c0_21_nf;
+extern cpuop_func_ce op_49c0_21_ff;
+extern cpuop_func_ce op_4a00_21_nf;
+extern cpuop_func_ce op_4a00_21_ff;
+extern cpuop_func_ce op_4a10_21_nf;
+extern cpuop_func_ce op_4a10_21_ff;
+extern cpuop_func_ce op_4a18_21_nf;
+extern cpuop_func_ce op_4a18_21_ff;
+extern cpuop_func_ce op_4a20_21_nf;
+extern cpuop_func_ce op_4a20_21_ff;
+extern cpuop_func_ce op_4a28_21_nf;
+extern cpuop_func_ce op_4a28_21_ff;
+extern cpuop_func_ce op_4a30_21_nf;
+extern cpuop_func_ce op_4a30_21_ff;
+extern cpuop_func_ce op_4a38_21_nf;
+extern cpuop_func_ce op_4a38_21_ff;
+extern cpuop_func_ce op_4a39_21_nf;
+extern cpuop_func_ce op_4a39_21_ff;
+extern cpuop_func_ce op_4a3a_21_nf;
+extern cpuop_func_ce op_4a3a_21_ff;
+extern cpuop_func_ce op_4a3b_21_nf;
+extern cpuop_func_ce op_4a3b_21_ff;
+extern cpuop_func_ce op_4a3c_21_nf;
+extern cpuop_func_ce op_4a3c_21_ff;
+extern cpuop_func_ce op_4a40_21_nf;
+extern cpuop_func_ce op_4a40_21_ff;
+extern cpuop_func_ce op_4a48_21_nf;
+extern cpuop_func_ce op_4a48_21_ff;
+extern cpuop_func_ce op_4a50_21_nf;
+extern cpuop_func_ce op_4a50_21_ff;
+extern cpuop_func_ce op_4a58_21_nf;
+extern cpuop_func_ce op_4a58_21_ff;
+extern cpuop_func_ce op_4a60_21_nf;
+extern cpuop_func_ce op_4a60_21_ff;
+extern cpuop_func_ce op_4a68_21_nf;
+extern cpuop_func_ce op_4a68_21_ff;
+extern cpuop_func_ce op_4a70_21_nf;
+extern cpuop_func_ce op_4a70_21_ff;
+extern cpuop_func_ce op_4a78_21_nf;
+extern cpuop_func_ce op_4a78_21_ff;
+extern cpuop_func_ce op_4a79_21_nf;
+extern cpuop_func_ce op_4a79_21_ff;
+extern cpuop_func_ce op_4a7a_21_nf;
+extern cpuop_func_ce op_4a7a_21_ff;
+extern cpuop_func_ce op_4a7b_21_nf;
+extern cpuop_func_ce op_4a7b_21_ff;
+extern cpuop_func_ce op_4a7c_21_nf;
+extern cpuop_func_ce op_4a7c_21_ff;
+extern cpuop_func_ce op_4a80_21_nf;
+extern cpuop_func_ce op_4a80_21_ff;
+extern cpuop_func_ce op_4a88_21_nf;
+extern cpuop_func_ce op_4a88_21_ff;
+extern cpuop_func_ce op_4a90_21_nf;
+extern cpuop_func_ce op_4a90_21_ff;
+extern cpuop_func_ce op_4a98_21_nf;
+extern cpuop_func_ce op_4a98_21_ff;
+extern cpuop_func_ce op_4aa0_21_nf;
+extern cpuop_func_ce op_4aa0_21_ff;
+extern cpuop_func_ce op_4aa8_21_nf;
+extern cpuop_func_ce op_4aa8_21_ff;
+extern cpuop_func_ce op_4ab0_21_nf;
+extern cpuop_func_ce op_4ab0_21_ff;
+extern cpuop_func_ce op_4ab8_21_nf;
+extern cpuop_func_ce op_4ab8_21_ff;
+extern cpuop_func_ce op_4ab9_21_nf;
+extern cpuop_func_ce op_4ab9_21_ff;
+extern cpuop_func_ce op_4aba_21_nf;
+extern cpuop_func_ce op_4aba_21_ff;
+extern cpuop_func_ce op_4abb_21_nf;
+extern cpuop_func_ce op_4abb_21_ff;
+extern cpuop_func_ce op_4abc_21_nf;
+extern cpuop_func_ce op_4abc_21_ff;
+extern cpuop_func_ce op_4ac0_21_nf;
+extern cpuop_func_ce op_4ac0_21_ff;
+extern cpuop_func_ce op_4ad0_21_nf;
+extern cpuop_func_ce op_4ad0_21_ff;
+extern cpuop_func_ce op_4ad8_21_nf;
+extern cpuop_func_ce op_4ad8_21_ff;
+extern cpuop_func_ce op_4ae0_21_nf;
+extern cpuop_func_ce op_4ae0_21_ff;
+extern cpuop_func_ce op_4ae8_21_nf;
+extern cpuop_func_ce op_4ae8_21_ff;
+extern cpuop_func_ce op_4af0_21_nf;
+extern cpuop_func_ce op_4af0_21_ff;
+extern cpuop_func_ce op_4af8_21_nf;
+extern cpuop_func_ce op_4af8_21_ff;
+extern cpuop_func_ce op_4af9_21_nf;
+extern cpuop_func_ce op_4af9_21_ff;
+extern cpuop_func_ce op_4c00_21_nf;
+extern cpuop_func_ce op_4c00_21_ff;
+extern cpuop_func_ce op_4c10_21_nf;
+extern cpuop_func_ce op_4c10_21_ff;
+extern cpuop_func_ce op_4c18_21_nf;
+extern cpuop_func_ce op_4c18_21_ff;
+extern cpuop_func_ce op_4c20_21_nf;
+extern cpuop_func_ce op_4c20_21_ff;
+extern cpuop_func_ce op_4c28_21_nf;
+extern cpuop_func_ce op_4c28_21_ff;
+extern cpuop_func_ce op_4c30_21_nf;
+extern cpuop_func_ce op_4c30_21_ff;
+extern cpuop_func_ce op_4c38_21_nf;
+extern cpuop_func_ce op_4c38_21_ff;
+extern cpuop_func_ce op_4c39_21_nf;
+extern cpuop_func_ce op_4c39_21_ff;
+extern cpuop_func_ce op_4c3a_21_nf;
+extern cpuop_func_ce op_4c3a_21_ff;
+extern cpuop_func_ce op_4c3b_21_nf;
+extern cpuop_func_ce op_4c3b_21_ff;
+extern cpuop_func_ce op_4c3c_21_nf;
+extern cpuop_func_ce op_4c3c_21_ff;
+extern cpuop_func_ce op_4c40_21_nf;
+extern cpuop_func_ce op_4c40_21_ff;
+extern cpuop_func_ce op_4c50_21_nf;
+extern cpuop_func_ce op_4c50_21_ff;
+extern cpuop_func_ce op_4c58_21_nf;
+extern cpuop_func_ce op_4c58_21_ff;
+extern cpuop_func_ce op_4c60_21_nf;
+extern cpuop_func_ce op_4c60_21_ff;
+extern cpuop_func_ce op_4c68_21_nf;
+extern cpuop_func_ce op_4c68_21_ff;
+extern cpuop_func_ce op_4c70_21_nf;
+extern cpuop_func_ce op_4c70_21_ff;
+extern cpuop_func_ce op_4c78_21_nf;
+extern cpuop_func_ce op_4c78_21_ff;
+extern cpuop_func_ce op_4c79_21_nf;
+extern cpuop_func_ce op_4c79_21_ff;
+extern cpuop_func_ce op_4c7a_21_nf;
+extern cpuop_func_ce op_4c7a_21_ff;
+extern cpuop_func_ce op_4c7b_21_nf;
+extern cpuop_func_ce op_4c7b_21_ff;
+extern cpuop_func_ce op_4c7c_21_nf;
+extern cpuop_func_ce op_4c7c_21_ff;
+extern cpuop_func_ce op_4c90_21_nf;
+extern cpuop_func_ce op_4c90_21_ff;
+extern cpuop_func_ce op_4c98_21_nf;
+extern cpuop_func_ce op_4c98_21_ff;
+extern cpuop_func_ce op_4ca8_21_nf;
+extern cpuop_func_ce op_4ca8_21_ff;
+extern cpuop_func_ce op_4cb0_21_nf;
+extern cpuop_func_ce op_4cb0_21_ff;
+extern cpuop_func_ce op_4cb8_21_nf;
+extern cpuop_func_ce op_4cb8_21_ff;
+extern cpuop_func_ce op_4cb9_21_nf;
+extern cpuop_func_ce op_4cb9_21_ff;
+extern cpuop_func_ce op_4cba_21_nf;
+extern cpuop_func_ce op_4cba_21_ff;
+extern cpuop_func_ce op_4cbb_21_nf;
+extern cpuop_func_ce op_4cbb_21_ff;
+extern cpuop_func_ce op_4cd0_21_nf;
+extern cpuop_func_ce op_4cd0_21_ff;
+extern cpuop_func_ce op_4cd8_21_nf;
+extern cpuop_func_ce op_4cd8_21_ff;
+extern cpuop_func_ce op_4ce8_21_nf;
+extern cpuop_func_ce op_4ce8_21_ff;
+extern cpuop_func_ce op_4cf0_21_nf;
+extern cpuop_func_ce op_4cf0_21_ff;
+extern cpuop_func_ce op_4cf8_21_nf;
+extern cpuop_func_ce op_4cf8_21_ff;
+extern cpuop_func_ce op_4cf9_21_nf;
+extern cpuop_func_ce op_4cf9_21_ff;
+extern cpuop_func_ce op_4cfa_21_nf;
+extern cpuop_func_ce op_4cfa_21_ff;
+extern cpuop_func_ce op_4cfb_21_nf;
+extern cpuop_func_ce op_4cfb_21_ff;
+extern cpuop_func_ce op_4e40_21_nf;
+extern cpuop_func_ce op_4e40_21_ff;
+extern cpuop_func_ce op_4e50_21_nf;
+extern cpuop_func_ce op_4e50_21_ff;
+extern cpuop_func_ce op_4e58_21_nf;
+extern cpuop_func_ce op_4e58_21_ff;
+extern cpuop_func_ce op_4e60_21_nf;
+extern cpuop_func_ce op_4e60_21_ff;
+extern cpuop_func_ce op_4e68_21_nf;
+extern cpuop_func_ce op_4e68_21_ff;
+extern cpuop_func_ce op_4e70_21_nf;
+extern cpuop_func_ce op_4e70_21_ff;
+extern cpuop_func_ce op_4e71_21_nf;
+extern cpuop_func_ce op_4e71_21_ff;
+extern cpuop_func_ce op_4e72_21_nf;
+extern cpuop_func_ce op_4e72_21_ff;
+extern cpuop_func_ce op_4e73_21_nf;
+extern cpuop_func_ce op_4e73_21_ff;
+extern cpuop_func_ce op_4e74_21_nf;
+extern cpuop_func_ce op_4e74_21_ff;
+extern cpuop_func_ce op_4e75_21_nf;
+extern cpuop_func_ce op_4e75_21_ff;
+extern cpuop_func_ce op_4e76_21_nf;
+extern cpuop_func_ce op_4e76_21_ff;
+extern cpuop_func_ce op_4e77_21_nf;
+extern cpuop_func_ce op_4e77_21_ff;
+extern cpuop_func_ce op_4e7a_21_nf;
+extern cpuop_func_ce op_4e7a_21_ff;
+extern cpuop_func_ce op_4e7b_21_nf;
+extern cpuop_func_ce op_4e7b_21_ff;
+extern cpuop_func_ce op_4e90_21_nf;
+extern cpuop_func_ce op_4e90_21_ff;
+extern cpuop_func_ce op_4ea8_21_nf;
+extern cpuop_func_ce op_4ea8_21_ff;
+extern cpuop_func_ce op_4eb0_21_nf;
+extern cpuop_func_ce op_4eb0_21_ff;
+extern cpuop_func_ce op_4eb8_21_nf;
+extern cpuop_func_ce op_4eb8_21_ff;
+extern cpuop_func_ce op_4eb9_21_nf;
+extern cpuop_func_ce op_4eb9_21_ff;
+extern cpuop_func_ce op_4eba_21_nf;
+extern cpuop_func_ce op_4eba_21_ff;
+extern cpuop_func_ce op_4ebb_21_nf;
+extern cpuop_func_ce op_4ebb_21_ff;
+extern cpuop_func_ce op_4ed0_21_nf;
+extern cpuop_func_ce op_4ed0_21_ff;
+extern cpuop_func_ce op_4ee8_21_nf;
+extern cpuop_func_ce op_4ee8_21_ff;
+extern cpuop_func_ce op_4ef0_21_nf;
+extern cpuop_func_ce op_4ef0_21_ff;
+extern cpuop_func_ce op_4ef8_21_nf;
+extern cpuop_func_ce op_4ef8_21_ff;
+extern cpuop_func_ce op_4ef9_21_nf;
+extern cpuop_func_ce op_4ef9_21_ff;
+extern cpuop_func_ce op_4efa_21_nf;
+extern cpuop_func_ce op_4efa_21_ff;
+extern cpuop_func_ce op_4efb_21_nf;
+extern cpuop_func_ce op_4efb_21_ff;
+extern cpuop_func_ce op_5000_21_nf;
+extern cpuop_func_ce op_5000_21_ff;
+extern cpuop_func_ce op_5010_21_nf;
+extern cpuop_func_ce op_5010_21_ff;
+extern cpuop_func_ce op_5018_21_nf;
+extern cpuop_func_ce op_5018_21_ff;
+extern cpuop_func_ce op_5020_21_nf;
+extern cpuop_func_ce op_5020_21_ff;
+extern cpuop_func_ce op_5028_21_nf;
+extern cpuop_func_ce op_5028_21_ff;
+extern cpuop_func_ce op_5030_21_nf;
+extern cpuop_func_ce op_5030_21_ff;
+extern cpuop_func_ce op_5038_21_nf;
+extern cpuop_func_ce op_5038_21_ff;
+extern cpuop_func_ce op_5039_21_nf;
+extern cpuop_func_ce op_5039_21_ff;
+extern cpuop_func_ce op_5040_21_nf;
+extern cpuop_func_ce op_5040_21_ff;
+extern cpuop_func_ce op_5048_21_nf;
+extern cpuop_func_ce op_5048_21_ff;
+extern cpuop_func_ce op_5050_21_nf;
+extern cpuop_func_ce op_5050_21_ff;
+extern cpuop_func_ce op_5058_21_nf;
+extern cpuop_func_ce op_5058_21_ff;
+extern cpuop_func_ce op_5060_21_nf;
+extern cpuop_func_ce op_5060_21_ff;
+extern cpuop_func_ce op_5068_21_nf;
+extern cpuop_func_ce op_5068_21_ff;
+extern cpuop_func_ce op_5070_21_nf;
+extern cpuop_func_ce op_5070_21_ff;
+extern cpuop_func_ce op_5078_21_nf;
+extern cpuop_func_ce op_5078_21_ff;
+extern cpuop_func_ce op_5079_21_nf;
+extern cpuop_func_ce op_5079_21_ff;
+extern cpuop_func_ce op_5080_21_nf;
+extern cpuop_func_ce op_5080_21_ff;
+extern cpuop_func_ce op_5088_21_nf;
+extern cpuop_func_ce op_5088_21_ff;
+extern cpuop_func_ce op_5090_21_nf;
+extern cpuop_func_ce op_5090_21_ff;
+extern cpuop_func_ce op_5098_21_nf;
+extern cpuop_func_ce op_5098_21_ff;
+extern cpuop_func_ce op_50a0_21_nf;
+extern cpuop_func_ce op_50a0_21_ff;
+extern cpuop_func_ce op_50a8_21_nf;
+extern cpuop_func_ce op_50a8_21_ff;
+extern cpuop_func_ce op_50b0_21_nf;
+extern cpuop_func_ce op_50b0_21_ff;
+extern cpuop_func_ce op_50b8_21_nf;
+extern cpuop_func_ce op_50b8_21_ff;
+extern cpuop_func_ce op_50b9_21_nf;
+extern cpuop_func_ce op_50b9_21_ff;
+extern cpuop_func_ce op_50c0_21_nf;
+extern cpuop_func_ce op_50c0_21_ff;
+extern cpuop_func_ce op_50c8_21_nf;
+extern cpuop_func_ce op_50c8_21_ff;
+extern cpuop_func_ce op_50d0_21_nf;
+extern cpuop_func_ce op_50d0_21_ff;
+extern cpuop_func_ce op_50d8_21_nf;
+extern cpuop_func_ce op_50d8_21_ff;
+extern cpuop_func_ce op_50e0_21_nf;
+extern cpuop_func_ce op_50e0_21_ff;
+extern cpuop_func_ce op_50e8_21_nf;
+extern cpuop_func_ce op_50e8_21_ff;
+extern cpuop_func_ce op_50f0_21_nf;
+extern cpuop_func_ce op_50f0_21_ff;
+extern cpuop_func_ce op_50f8_21_nf;
+extern cpuop_func_ce op_50f8_21_ff;
+extern cpuop_func_ce op_50f9_21_nf;
+extern cpuop_func_ce op_50f9_21_ff;
+extern cpuop_func_ce op_50fa_21_nf;
+extern cpuop_func_ce op_50fa_21_ff;
+extern cpuop_func_ce op_50fb_21_nf;
+extern cpuop_func_ce op_50fb_21_ff;
+extern cpuop_func_ce op_50fc_21_nf;
+extern cpuop_func_ce op_50fc_21_ff;
+extern cpuop_func_ce op_5100_21_nf;
+extern cpuop_func_ce op_5100_21_ff;
+extern cpuop_func_ce op_5110_21_nf;
+extern cpuop_func_ce op_5110_21_ff;
+extern cpuop_func_ce op_5118_21_nf;
+extern cpuop_func_ce op_5118_21_ff;
+extern cpuop_func_ce op_5120_21_nf;
+extern cpuop_func_ce op_5120_21_ff;
+extern cpuop_func_ce op_5128_21_nf;
+extern cpuop_func_ce op_5128_21_ff;
+extern cpuop_func_ce op_5130_21_nf;
+extern cpuop_func_ce op_5130_21_ff;
+extern cpuop_func_ce op_5138_21_nf;
+extern cpuop_func_ce op_5138_21_ff;
+extern cpuop_func_ce op_5139_21_nf;
+extern cpuop_func_ce op_5139_21_ff;
+extern cpuop_func_ce op_5140_21_nf;
+extern cpuop_func_ce op_5140_21_ff;
+extern cpuop_func_ce op_5148_21_nf;
+extern cpuop_func_ce op_5148_21_ff;
+extern cpuop_func_ce op_5150_21_nf;
+extern cpuop_func_ce op_5150_21_ff;
+extern cpuop_func_ce op_5158_21_nf;
+extern cpuop_func_ce op_5158_21_ff;
+extern cpuop_func_ce op_5160_21_nf;
+extern cpuop_func_ce op_5160_21_ff;
+extern cpuop_func_ce op_5168_21_nf;
+extern cpuop_func_ce op_5168_21_ff;
+extern cpuop_func_ce op_5170_21_nf;
+extern cpuop_func_ce op_5170_21_ff;
+extern cpuop_func_ce op_5178_21_nf;
+extern cpuop_func_ce op_5178_21_ff;
+extern cpuop_func_ce op_5179_21_nf;
+extern cpuop_func_ce op_5179_21_ff;
+extern cpuop_func_ce op_5180_21_nf;
+extern cpuop_func_ce op_5180_21_ff;
+extern cpuop_func_ce op_5188_21_nf;
+extern cpuop_func_ce op_5188_21_ff;
+extern cpuop_func_ce op_5190_21_nf;
+extern cpuop_func_ce op_5190_21_ff;
+extern cpuop_func_ce op_5198_21_nf;
+extern cpuop_func_ce op_5198_21_ff;
+extern cpuop_func_ce op_51a0_21_nf;
+extern cpuop_func_ce op_51a0_21_ff;
+extern cpuop_func_ce op_51a8_21_nf;
+extern cpuop_func_ce op_51a8_21_ff;
+extern cpuop_func_ce op_51b0_21_nf;
+extern cpuop_func_ce op_51b0_21_ff;
+extern cpuop_func_ce op_51b8_21_nf;
+extern cpuop_func_ce op_51b8_21_ff;
+extern cpuop_func_ce op_51b9_21_nf;
+extern cpuop_func_ce op_51b9_21_ff;
+extern cpuop_func_ce op_51c0_21_nf;
+extern cpuop_func_ce op_51c0_21_ff;
+extern cpuop_func_ce op_51c8_21_nf;
+extern cpuop_func_ce op_51c8_21_ff;
+extern cpuop_func_ce op_51d0_21_nf;
+extern cpuop_func_ce op_51d0_21_ff;
+extern cpuop_func_ce op_51d8_21_nf;
+extern cpuop_func_ce op_51d8_21_ff;
+extern cpuop_func_ce op_51e0_21_nf;
+extern cpuop_func_ce op_51e0_21_ff;
+extern cpuop_func_ce op_51e8_21_nf;
+extern cpuop_func_ce op_51e8_21_ff;
+extern cpuop_func_ce op_51f0_21_nf;
+extern cpuop_func_ce op_51f0_21_ff;
+extern cpuop_func_ce op_51f8_21_nf;
+extern cpuop_func_ce op_51f8_21_ff;
+extern cpuop_func_ce op_51f9_21_nf;
+extern cpuop_func_ce op_51f9_21_ff;
+extern cpuop_func_ce op_51fa_21_nf;
+extern cpuop_func_ce op_51fa_21_ff;
+extern cpuop_func_ce op_51fb_21_nf;
+extern cpuop_func_ce op_51fb_21_ff;
+extern cpuop_func_ce op_51fc_21_nf;
+extern cpuop_func_ce op_51fc_21_ff;
+extern cpuop_func_ce op_52c0_21_nf;
+extern cpuop_func_ce op_52c0_21_ff;
+extern cpuop_func_ce op_52c8_21_nf;
+extern cpuop_func_ce op_52c8_21_ff;
+extern cpuop_func_ce op_52d0_21_nf;
+extern cpuop_func_ce op_52d0_21_ff;
+extern cpuop_func_ce op_52d8_21_nf;
+extern cpuop_func_ce op_52d8_21_ff;
+extern cpuop_func_ce op_52e0_21_nf;
+extern cpuop_func_ce op_52e0_21_ff;
+extern cpuop_func_ce op_52e8_21_nf;
+extern cpuop_func_ce op_52e8_21_ff;
+extern cpuop_func_ce op_52f0_21_nf;
+extern cpuop_func_ce op_52f0_21_ff;
+extern cpuop_func_ce op_52f8_21_nf;
+extern cpuop_func_ce op_52f8_21_ff;
+extern cpuop_func_ce op_52f9_21_nf;
+extern cpuop_func_ce op_52f9_21_ff;
+extern cpuop_func_ce op_52fa_21_nf;
+extern cpuop_func_ce op_52fa_21_ff;
+extern cpuop_func_ce op_52fb_21_nf;
+extern cpuop_func_ce op_52fb_21_ff;
+extern cpuop_func_ce op_52fc_21_nf;
+extern cpuop_func_ce op_52fc_21_ff;
+extern cpuop_func_ce op_53c0_21_nf;
+extern cpuop_func_ce op_53c0_21_ff;
+extern cpuop_func_ce op_53c8_21_nf;
+extern cpuop_func_ce op_53c8_21_ff;
+extern cpuop_func_ce op_53d0_21_nf;
+extern cpuop_func_ce op_53d0_21_ff;
+extern cpuop_func_ce op_53d8_21_nf;
+extern cpuop_func_ce op_53d8_21_ff;
+extern cpuop_func_ce op_53e0_21_nf;
+extern cpuop_func_ce op_53e0_21_ff;
+extern cpuop_func_ce op_53e8_21_nf;
+extern cpuop_func_ce op_53e8_21_ff;
+extern cpuop_func_ce op_53f0_21_nf;
+extern cpuop_func_ce op_53f0_21_ff;
+extern cpuop_func_ce op_53f8_21_nf;
+extern cpuop_func_ce op_53f8_21_ff;
+extern cpuop_func_ce op_53f9_21_nf;
+extern cpuop_func_ce op_53f9_21_ff;
+extern cpuop_func_ce op_53fa_21_nf;
+extern cpuop_func_ce op_53fa_21_ff;
+extern cpuop_func_ce op_53fb_21_nf;
+extern cpuop_func_ce op_53fb_21_ff;
+extern cpuop_func_ce op_53fc_21_nf;
+extern cpuop_func_ce op_53fc_21_ff;
+extern cpuop_func_ce op_54c0_21_nf;
+extern cpuop_func_ce op_54c0_21_ff;
+extern cpuop_func_ce op_54c8_21_nf;
+extern cpuop_func_ce op_54c8_21_ff;
+extern cpuop_func_ce op_54d0_21_nf;
+extern cpuop_func_ce op_54d0_21_ff;
+extern cpuop_func_ce op_54d8_21_nf;
+extern cpuop_func_ce op_54d8_21_ff;
+extern cpuop_func_ce op_54e0_21_nf;
+extern cpuop_func_ce op_54e0_21_ff;
+extern cpuop_func_ce op_54e8_21_nf;
+extern cpuop_func_ce op_54e8_21_ff;
+extern cpuop_func_ce op_54f0_21_nf;
+extern cpuop_func_ce op_54f0_21_ff;
+extern cpuop_func_ce op_54f8_21_nf;
+extern cpuop_func_ce op_54f8_21_ff;
+extern cpuop_func_ce op_54f9_21_nf;
+extern cpuop_func_ce op_54f9_21_ff;
+extern cpuop_func_ce op_54fa_21_nf;
+extern cpuop_func_ce op_54fa_21_ff;
+extern cpuop_func_ce op_54fb_21_nf;
+extern cpuop_func_ce op_54fb_21_ff;
+extern cpuop_func_ce op_54fc_21_nf;
+extern cpuop_func_ce op_54fc_21_ff;
+extern cpuop_func_ce op_55c0_21_nf;
+extern cpuop_func_ce op_55c0_21_ff;
+extern cpuop_func_ce op_55c8_21_nf;
+extern cpuop_func_ce op_55c8_21_ff;
+extern cpuop_func_ce op_55d0_21_nf;
+extern cpuop_func_ce op_55d0_21_ff;
+extern cpuop_func_ce op_55d8_21_nf;
+extern cpuop_func_ce op_55d8_21_ff;
+extern cpuop_func_ce op_55e0_21_nf;
+extern cpuop_func_ce op_55e0_21_ff;
+extern cpuop_func_ce op_55e8_21_nf;
+extern cpuop_func_ce op_55e8_21_ff;
+extern cpuop_func_ce op_55f0_21_nf;
+extern cpuop_func_ce op_55f0_21_ff;
+extern cpuop_func_ce op_55f8_21_nf;
+extern cpuop_func_ce op_55f8_21_ff;
+extern cpuop_func_ce op_55f9_21_nf;
+extern cpuop_func_ce op_55f9_21_ff;
+extern cpuop_func_ce op_55fa_21_nf;
+extern cpuop_func_ce op_55fa_21_ff;
+extern cpuop_func_ce op_55fb_21_nf;
+extern cpuop_func_ce op_55fb_21_ff;
+extern cpuop_func_ce op_55fc_21_nf;
+extern cpuop_func_ce op_55fc_21_ff;
+extern cpuop_func_ce op_56c0_21_nf;
+extern cpuop_func_ce op_56c0_21_ff;
+extern cpuop_func_ce op_56c8_21_nf;
+extern cpuop_func_ce op_56c8_21_ff;
+extern cpuop_func_ce op_56d0_21_nf;
+extern cpuop_func_ce op_56d0_21_ff;
+extern cpuop_func_ce op_56d8_21_nf;
+extern cpuop_func_ce op_56d8_21_ff;
+extern cpuop_func_ce op_56e0_21_nf;
+extern cpuop_func_ce op_56e0_21_ff;
+extern cpuop_func_ce op_56e8_21_nf;
+extern cpuop_func_ce op_56e8_21_ff;
+extern cpuop_func_ce op_56f0_21_nf;
+extern cpuop_func_ce op_56f0_21_ff;
+extern cpuop_func_ce op_56f8_21_nf;
+extern cpuop_func_ce op_56f8_21_ff;
+extern cpuop_func_ce op_56f9_21_nf;
+extern cpuop_func_ce op_56f9_21_ff;
+extern cpuop_func_ce op_56fa_21_nf;
+extern cpuop_func_ce op_56fa_21_ff;
+extern cpuop_func_ce op_56fb_21_nf;
+extern cpuop_func_ce op_56fb_21_ff;
+extern cpuop_func_ce op_56fc_21_nf;
+extern cpuop_func_ce op_56fc_21_ff;
+extern cpuop_func_ce op_57c0_21_nf;
+extern cpuop_func_ce op_57c0_21_ff;
+extern cpuop_func_ce op_57c8_21_nf;
+extern cpuop_func_ce op_57c8_21_ff;
+extern cpuop_func_ce op_57d0_21_nf;
+extern cpuop_func_ce op_57d0_21_ff;
+extern cpuop_func_ce op_57d8_21_nf;
+extern cpuop_func_ce op_57d8_21_ff;
+extern cpuop_func_ce op_57e0_21_nf;
+extern cpuop_func_ce op_57e0_21_ff;
+extern cpuop_func_ce op_57e8_21_nf;
+extern cpuop_func_ce op_57e8_21_ff;
+extern cpuop_func_ce op_57f0_21_nf;
+extern cpuop_func_ce op_57f0_21_ff;
+extern cpuop_func_ce op_57f8_21_nf;
+extern cpuop_func_ce op_57f8_21_ff;
+extern cpuop_func_ce op_57f9_21_nf;
+extern cpuop_func_ce op_57f9_21_ff;
+extern cpuop_func_ce op_57fa_21_nf;
+extern cpuop_func_ce op_57fa_21_ff;
+extern cpuop_func_ce op_57fb_21_nf;
+extern cpuop_func_ce op_57fb_21_ff;
+extern cpuop_func_ce op_57fc_21_nf;
+extern cpuop_func_ce op_57fc_21_ff;
+extern cpuop_func_ce op_58c0_21_nf;
+extern cpuop_func_ce op_58c0_21_ff;
+extern cpuop_func_ce op_58c8_21_nf;
+extern cpuop_func_ce op_58c8_21_ff;
+extern cpuop_func_ce op_58d0_21_nf;
+extern cpuop_func_ce op_58d0_21_ff;
+extern cpuop_func_ce op_58d8_21_nf;
+extern cpuop_func_ce op_58d8_21_ff;
+extern cpuop_func_ce op_58e0_21_nf;
+extern cpuop_func_ce op_58e0_21_ff;
+extern cpuop_func_ce op_58e8_21_nf;
+extern cpuop_func_ce op_58e8_21_ff;
+extern cpuop_func_ce op_58f0_21_nf;
+extern cpuop_func_ce op_58f0_21_ff;
+extern cpuop_func_ce op_58f8_21_nf;
+extern cpuop_func_ce op_58f8_21_ff;
+extern cpuop_func_ce op_58f9_21_nf;
+extern cpuop_func_ce op_58f9_21_ff;
+extern cpuop_func_ce op_58fa_21_nf;
+extern cpuop_func_ce op_58fa_21_ff;
+extern cpuop_func_ce op_58fb_21_nf;
+extern cpuop_func_ce op_58fb_21_ff;
+extern cpuop_func_ce op_58fc_21_nf;
+extern cpuop_func_ce op_58fc_21_ff;
+extern cpuop_func_ce op_59c0_21_nf;
+extern cpuop_func_ce op_59c0_21_ff;
+extern cpuop_func_ce op_59c8_21_nf;
+extern cpuop_func_ce op_59c8_21_ff;
+extern cpuop_func_ce op_59d0_21_nf;
+extern cpuop_func_ce op_59d0_21_ff;
+extern cpuop_func_ce op_59d8_21_nf;
+extern cpuop_func_ce op_59d8_21_ff;
+extern cpuop_func_ce op_59e0_21_nf;
+extern cpuop_func_ce op_59e0_21_ff;
+extern cpuop_func_ce op_59e8_21_nf;
+extern cpuop_func_ce op_59e8_21_ff;
+extern cpuop_func_ce op_59f0_21_nf;
+extern cpuop_func_ce op_59f0_21_ff;
+extern cpuop_func_ce op_59f8_21_nf;
+extern cpuop_func_ce op_59f8_21_ff;
+extern cpuop_func_ce op_59f9_21_nf;
+extern cpuop_func_ce op_59f9_21_ff;
+extern cpuop_func_ce op_59fa_21_nf;
+extern cpuop_func_ce op_59fa_21_ff;
+extern cpuop_func_ce op_59fb_21_nf;
+extern cpuop_func_ce op_59fb_21_ff;
+extern cpuop_func_ce op_59fc_21_nf;
+extern cpuop_func_ce op_59fc_21_ff;
+extern cpuop_func_ce op_5ac0_21_nf;
+extern cpuop_func_ce op_5ac0_21_ff;
+extern cpuop_func_ce op_5ac8_21_nf;
+extern cpuop_func_ce op_5ac8_21_ff;
+extern cpuop_func_ce op_5ad0_21_nf;
+extern cpuop_func_ce op_5ad0_21_ff;
+extern cpuop_func_ce op_5ad8_21_nf;
+extern cpuop_func_ce op_5ad8_21_ff;
+extern cpuop_func_ce op_5ae0_21_nf;
+extern cpuop_func_ce op_5ae0_21_ff;
+extern cpuop_func_ce op_5ae8_21_nf;
+extern cpuop_func_ce op_5ae8_21_ff;
+extern cpuop_func_ce op_5af0_21_nf;
+extern cpuop_func_ce op_5af0_21_ff;
+extern cpuop_func_ce op_5af8_21_nf;
+extern cpuop_func_ce op_5af8_21_ff;
+extern cpuop_func_ce op_5af9_21_nf;
+extern cpuop_func_ce op_5af9_21_ff;
+extern cpuop_func_ce op_5afa_21_nf;
+extern cpuop_func_ce op_5afa_21_ff;
+extern cpuop_func_ce op_5afb_21_nf;
+extern cpuop_func_ce op_5afb_21_ff;
+extern cpuop_func_ce op_5afc_21_nf;
+extern cpuop_func_ce op_5afc_21_ff;
+extern cpuop_func_ce op_5bc0_21_nf;
+extern cpuop_func_ce op_5bc0_21_ff;
+extern cpuop_func_ce op_5bc8_21_nf;
+extern cpuop_func_ce op_5bc8_21_ff;
+extern cpuop_func_ce op_5bd0_21_nf;
+extern cpuop_func_ce op_5bd0_21_ff;
+extern cpuop_func_ce op_5bd8_21_nf;
+extern cpuop_func_ce op_5bd8_21_ff;
+extern cpuop_func_ce op_5be0_21_nf;
+extern cpuop_func_ce op_5be0_21_ff;
+extern cpuop_func_ce op_5be8_21_nf;
+extern cpuop_func_ce op_5be8_21_ff;
+extern cpuop_func_ce op_5bf0_21_nf;
+extern cpuop_func_ce op_5bf0_21_ff;
+extern cpuop_func_ce op_5bf8_21_nf;
+extern cpuop_func_ce op_5bf8_21_ff;
+extern cpuop_func_ce op_5bf9_21_nf;
+extern cpuop_func_ce op_5bf9_21_ff;
+extern cpuop_func_ce op_5bfa_21_nf;
+extern cpuop_func_ce op_5bfa_21_ff;
+extern cpuop_func_ce op_5bfb_21_nf;
+extern cpuop_func_ce op_5bfb_21_ff;
+extern cpuop_func_ce op_5bfc_21_nf;
+extern cpuop_func_ce op_5bfc_21_ff;
+extern cpuop_func_ce op_5cc0_21_nf;
+extern cpuop_func_ce op_5cc0_21_ff;
+extern cpuop_func_ce op_5cc8_21_nf;
+extern cpuop_func_ce op_5cc8_21_ff;
+extern cpuop_func_ce op_5cd0_21_nf;
+extern cpuop_func_ce op_5cd0_21_ff;
+extern cpuop_func_ce op_5cd8_21_nf;
+extern cpuop_func_ce op_5cd8_21_ff;
+extern cpuop_func_ce op_5ce0_21_nf;
+extern cpuop_func_ce op_5ce0_21_ff;
+extern cpuop_func_ce op_5ce8_21_nf;
+extern cpuop_func_ce op_5ce8_21_ff;
+extern cpuop_func_ce op_5cf0_21_nf;
+extern cpuop_func_ce op_5cf0_21_ff;
+extern cpuop_func_ce op_5cf8_21_nf;
+extern cpuop_func_ce op_5cf8_21_ff;
+extern cpuop_func_ce op_5cf9_21_nf;
+extern cpuop_func_ce op_5cf9_21_ff;
+extern cpuop_func_ce op_5cfa_21_nf;
+extern cpuop_func_ce op_5cfa_21_ff;
+extern cpuop_func_ce op_5cfb_21_nf;
+extern cpuop_func_ce op_5cfb_21_ff;
+extern cpuop_func_ce op_5cfc_21_nf;
+extern cpuop_func_ce op_5cfc_21_ff;
+extern cpuop_func_ce op_5dc0_21_nf;
+extern cpuop_func_ce op_5dc0_21_ff;
+extern cpuop_func_ce op_5dc8_21_nf;
+extern cpuop_func_ce op_5dc8_21_ff;
+extern cpuop_func_ce op_5dd0_21_nf;
+extern cpuop_func_ce op_5dd0_21_ff;
+extern cpuop_func_ce op_5dd8_21_nf;
+extern cpuop_func_ce op_5dd8_21_ff;
+extern cpuop_func_ce op_5de0_21_nf;
+extern cpuop_func_ce op_5de0_21_ff;
+extern cpuop_func_ce op_5de8_21_nf;
+extern cpuop_func_ce op_5de8_21_ff;
+extern cpuop_func_ce op_5df0_21_nf;
+extern cpuop_func_ce op_5df0_21_ff;
+extern cpuop_func_ce op_5df8_21_nf;
+extern cpuop_func_ce op_5df8_21_ff;
+extern cpuop_func_ce op_5df9_21_nf;
+extern cpuop_func_ce op_5df9_21_ff;
+extern cpuop_func_ce op_5dfa_21_nf;
+extern cpuop_func_ce op_5dfa_21_ff;
+extern cpuop_func_ce op_5dfb_21_nf;
+extern cpuop_func_ce op_5dfb_21_ff;
+extern cpuop_func_ce op_5dfc_21_nf;
+extern cpuop_func_ce op_5dfc_21_ff;
+extern cpuop_func_ce op_5ec0_21_nf;
+extern cpuop_func_ce op_5ec0_21_ff;
+extern cpuop_func_ce op_5ec8_21_nf;
+extern cpuop_func_ce op_5ec8_21_ff;
+extern cpuop_func_ce op_5ed0_21_nf;
+extern cpuop_func_ce op_5ed0_21_ff;
+extern cpuop_func_ce op_5ed8_21_nf;
+extern cpuop_func_ce op_5ed8_21_ff;
+extern cpuop_func_ce op_5ee0_21_nf;
+extern cpuop_func_ce op_5ee0_21_ff;
+extern cpuop_func_ce op_5ee8_21_nf;
+extern cpuop_func_ce op_5ee8_21_ff;
+extern cpuop_func_ce op_5ef0_21_nf;
+extern cpuop_func_ce op_5ef0_21_ff;
+extern cpuop_func_ce op_5ef8_21_nf;
+extern cpuop_func_ce op_5ef8_21_ff;
+extern cpuop_func_ce op_5ef9_21_nf;
+extern cpuop_func_ce op_5ef9_21_ff;
+extern cpuop_func_ce op_5efa_21_nf;
+extern cpuop_func_ce op_5efa_21_ff;
+extern cpuop_func_ce op_5efb_21_nf;
+extern cpuop_func_ce op_5efb_21_ff;
+extern cpuop_func_ce op_5efc_21_nf;
+extern cpuop_func_ce op_5efc_21_ff;
+extern cpuop_func_ce op_5fc0_21_nf;
+extern cpuop_func_ce op_5fc0_21_ff;
+extern cpuop_func_ce op_5fc8_21_nf;
+extern cpuop_func_ce op_5fc8_21_ff;
+extern cpuop_func_ce op_5fd0_21_nf;
+extern cpuop_func_ce op_5fd0_21_ff;
+extern cpuop_func_ce op_5fd8_21_nf;
+extern cpuop_func_ce op_5fd8_21_ff;
+extern cpuop_func_ce op_5fe0_21_nf;
+extern cpuop_func_ce op_5fe0_21_ff;
+extern cpuop_func_ce op_5fe8_21_nf;
+extern cpuop_func_ce op_5fe8_21_ff;
+extern cpuop_func_ce op_5ff0_21_nf;
+extern cpuop_func_ce op_5ff0_21_ff;
+extern cpuop_func_ce op_5ff8_21_nf;
+extern cpuop_func_ce op_5ff8_21_ff;
+extern cpuop_func_ce op_5ff9_21_nf;
+extern cpuop_func_ce op_5ff9_21_ff;
+extern cpuop_func_ce op_5ffa_21_nf;
+extern cpuop_func_ce op_5ffa_21_ff;
+extern cpuop_func_ce op_5ffb_21_nf;
+extern cpuop_func_ce op_5ffb_21_ff;
+extern cpuop_func_ce op_5ffc_21_nf;
+extern cpuop_func_ce op_5ffc_21_ff;
+extern cpuop_func_ce op_6000_21_nf;
+extern cpuop_func_ce op_6000_21_ff;
+extern cpuop_func_ce op_6001_21_nf;
+extern cpuop_func_ce op_6001_21_ff;
+extern cpuop_func_ce op_60ff_21_nf;
+extern cpuop_func_ce op_60ff_21_ff;
+extern cpuop_func_ce op_6100_21_nf;
+extern cpuop_func_ce op_6100_21_ff;
+extern cpuop_func_ce op_6101_21_nf;
+extern cpuop_func_ce op_6101_21_ff;
+extern cpuop_func_ce op_61ff_21_nf;
+extern cpuop_func_ce op_61ff_21_ff;
+extern cpuop_func_ce op_6200_21_nf;
+extern cpuop_func_ce op_6200_21_ff;
+extern cpuop_func_ce op_6201_21_nf;
+extern cpuop_func_ce op_6201_21_ff;
+extern cpuop_func_ce op_62ff_21_nf;
+extern cpuop_func_ce op_62ff_21_ff;
+extern cpuop_func_ce op_6300_21_nf;
+extern cpuop_func_ce op_6300_21_ff;
+extern cpuop_func_ce op_6301_21_nf;
+extern cpuop_func_ce op_6301_21_ff;
+extern cpuop_func_ce op_63ff_21_nf;
+extern cpuop_func_ce op_63ff_21_ff;
+extern cpuop_func_ce op_6400_21_nf;
+extern cpuop_func_ce op_6400_21_ff;
+extern cpuop_func_ce op_6401_21_nf;
+extern cpuop_func_ce op_6401_21_ff;
+extern cpuop_func_ce op_64ff_21_nf;
+extern cpuop_func_ce op_64ff_21_ff;
+extern cpuop_func_ce op_6500_21_nf;
+extern cpuop_func_ce op_6500_21_ff;
+extern cpuop_func_ce op_6501_21_nf;
+extern cpuop_func_ce op_6501_21_ff;
+extern cpuop_func_ce op_65ff_21_nf;
+extern cpuop_func_ce op_65ff_21_ff;
+extern cpuop_func_ce op_6600_21_nf;
+extern cpuop_func_ce op_6600_21_ff;
+extern cpuop_func_ce op_6601_21_nf;
+extern cpuop_func_ce op_6601_21_ff;
+extern cpuop_func_ce op_66ff_21_nf;
+extern cpuop_func_ce op_66ff_21_ff;
+extern cpuop_func_ce op_6700_21_nf;
+extern cpuop_func_ce op_6700_21_ff;
+extern cpuop_func_ce op_6701_21_nf;
+extern cpuop_func_ce op_6701_21_ff;
+extern cpuop_func_ce op_67ff_21_nf;
+extern cpuop_func_ce op_67ff_21_ff;
+extern cpuop_func_ce op_6800_21_nf;
+extern cpuop_func_ce op_6800_21_ff;
+extern cpuop_func_ce op_6801_21_nf;
+extern cpuop_func_ce op_6801_21_ff;
+extern cpuop_func_ce op_68ff_21_nf;
+extern cpuop_func_ce op_68ff_21_ff;
+extern cpuop_func_ce op_6900_21_nf;
+extern cpuop_func_ce op_6900_21_ff;
+extern cpuop_func_ce op_6901_21_nf;
+extern cpuop_func_ce op_6901_21_ff;
+extern cpuop_func_ce op_69ff_21_nf;
+extern cpuop_func_ce op_69ff_21_ff;
+extern cpuop_func_ce op_6a00_21_nf;
+extern cpuop_func_ce op_6a00_21_ff;
+extern cpuop_func_ce op_6a01_21_nf;
+extern cpuop_func_ce op_6a01_21_ff;
+extern cpuop_func_ce op_6aff_21_nf;
+extern cpuop_func_ce op_6aff_21_ff;
+extern cpuop_func_ce op_6b00_21_nf;
+extern cpuop_func_ce op_6b00_21_ff;
+extern cpuop_func_ce op_6b01_21_nf;
+extern cpuop_func_ce op_6b01_21_ff;
+extern cpuop_func_ce op_6bff_21_nf;
+extern cpuop_func_ce op_6bff_21_ff;
+extern cpuop_func_ce op_6c00_21_nf;
+extern cpuop_func_ce op_6c00_21_ff;
+extern cpuop_func_ce op_6c01_21_nf;
+extern cpuop_func_ce op_6c01_21_ff;
+extern cpuop_func_ce op_6cff_21_nf;
+extern cpuop_func_ce op_6cff_21_ff;
+extern cpuop_func_ce op_6d00_21_nf;
+extern cpuop_func_ce op_6d00_21_ff;
+extern cpuop_func_ce op_6d01_21_nf;
+extern cpuop_func_ce op_6d01_21_ff;
+extern cpuop_func_ce op_6dff_21_nf;
+extern cpuop_func_ce op_6dff_21_ff;
+extern cpuop_func_ce op_6e00_21_nf;
+extern cpuop_func_ce op_6e00_21_ff;
+extern cpuop_func_ce op_6e01_21_nf;
+extern cpuop_func_ce op_6e01_21_ff;
+extern cpuop_func_ce op_6eff_21_nf;
+extern cpuop_func_ce op_6eff_21_ff;
+extern cpuop_func_ce op_6f00_21_nf;
+extern cpuop_func_ce op_6f00_21_ff;
+extern cpuop_func_ce op_6f01_21_nf;
+extern cpuop_func_ce op_6f01_21_ff;
+extern cpuop_func_ce op_6fff_21_nf;
+extern cpuop_func_ce op_6fff_21_ff;
+extern cpuop_func_ce op_7000_21_nf;
+extern cpuop_func_ce op_7000_21_ff;
+extern cpuop_func_ce op_8000_21_nf;
+extern cpuop_func_ce op_8000_21_ff;
+extern cpuop_func_ce op_8010_21_nf;
+extern cpuop_func_ce op_8010_21_ff;
+extern cpuop_func_ce op_8018_21_nf;
+extern cpuop_func_ce op_8018_21_ff;
+extern cpuop_func_ce op_8020_21_nf;
+extern cpuop_func_ce op_8020_21_ff;
+extern cpuop_func_ce op_8028_21_nf;
+extern cpuop_func_ce op_8028_21_ff;
+extern cpuop_func_ce op_8030_21_nf;
+extern cpuop_func_ce op_8030_21_ff;
+extern cpuop_func_ce op_8038_21_nf;
+extern cpuop_func_ce op_8038_21_ff;
+extern cpuop_func_ce op_8039_21_nf;
+extern cpuop_func_ce op_8039_21_ff;
+extern cpuop_func_ce op_803a_21_nf;
+extern cpuop_func_ce op_803a_21_ff;
+extern cpuop_func_ce op_803b_21_nf;
+extern cpuop_func_ce op_803b_21_ff;
+extern cpuop_func_ce op_803c_21_nf;
+extern cpuop_func_ce op_803c_21_ff;
+extern cpuop_func_ce op_8040_21_nf;
+extern cpuop_func_ce op_8040_21_ff;
+extern cpuop_func_ce op_8050_21_nf;
+extern cpuop_func_ce op_8050_21_ff;
+extern cpuop_func_ce op_8058_21_nf;
+extern cpuop_func_ce op_8058_21_ff;
+extern cpuop_func_ce op_8060_21_nf;
+extern cpuop_func_ce op_8060_21_ff;
+extern cpuop_func_ce op_8068_21_nf;
+extern cpuop_func_ce op_8068_21_ff;
+extern cpuop_func_ce op_8070_21_nf;
+extern cpuop_func_ce op_8070_21_ff;
+extern cpuop_func_ce op_8078_21_nf;
+extern cpuop_func_ce op_8078_21_ff;
+extern cpuop_func_ce op_8079_21_nf;
+extern cpuop_func_ce op_8079_21_ff;
+extern cpuop_func_ce op_807a_21_nf;
+extern cpuop_func_ce op_807a_21_ff;
+extern cpuop_func_ce op_807b_21_nf;
+extern cpuop_func_ce op_807b_21_ff;
+extern cpuop_func_ce op_807c_21_nf;
+extern cpuop_func_ce op_807c_21_ff;
+extern cpuop_func_ce op_8080_21_nf;
+extern cpuop_func_ce op_8080_21_ff;
+extern cpuop_func_ce op_8090_21_nf;
+extern cpuop_func_ce op_8090_21_ff;
+extern cpuop_func_ce op_8098_21_nf;
+extern cpuop_func_ce op_8098_21_ff;
+extern cpuop_func_ce op_80a0_21_nf;
+extern cpuop_func_ce op_80a0_21_ff;
+extern cpuop_func_ce op_80a8_21_nf;
+extern cpuop_func_ce op_80a8_21_ff;
+extern cpuop_func_ce op_80b0_21_nf;
+extern cpuop_func_ce op_80b0_21_ff;
+extern cpuop_func_ce op_80b8_21_nf;
+extern cpuop_func_ce op_80b8_21_ff;
+extern cpuop_func_ce op_80b9_21_nf;
+extern cpuop_func_ce op_80b9_21_ff;
+extern cpuop_func_ce op_80ba_21_nf;
+extern cpuop_func_ce op_80ba_21_ff;
+extern cpuop_func_ce op_80bb_21_nf;
+extern cpuop_func_ce op_80bb_21_ff;
+extern cpuop_func_ce op_80bc_21_nf;
+extern cpuop_func_ce op_80bc_21_ff;
+extern cpuop_func_ce op_80c0_21_nf;
+extern cpuop_func_ce op_80c0_21_ff;
+extern cpuop_func_ce op_80d0_21_nf;
+extern cpuop_func_ce op_80d0_21_ff;
+extern cpuop_func_ce op_80d8_21_nf;
+extern cpuop_func_ce op_80d8_21_ff;
+extern cpuop_func_ce op_80e0_21_nf;
+extern cpuop_func_ce op_80e0_21_ff;
+extern cpuop_func_ce op_80e8_21_nf;
+extern cpuop_func_ce op_80e8_21_ff;
+extern cpuop_func_ce op_80f0_21_nf;
+extern cpuop_func_ce op_80f0_21_ff;
+extern cpuop_func_ce op_80f8_21_nf;
+extern cpuop_func_ce op_80f8_21_ff;
+extern cpuop_func_ce op_80f9_21_nf;
+extern cpuop_func_ce op_80f9_21_ff;
+extern cpuop_func_ce op_80fa_21_nf;
+extern cpuop_func_ce op_80fa_21_ff;
+extern cpuop_func_ce op_80fb_21_nf;
+extern cpuop_func_ce op_80fb_21_ff;
+extern cpuop_func_ce op_80fc_21_nf;
+extern cpuop_func_ce op_80fc_21_ff;
+extern cpuop_func_ce op_8100_21_nf;
+extern cpuop_func_ce op_8100_21_ff;
+extern cpuop_func_ce op_8108_21_nf;
+extern cpuop_func_ce op_8108_21_ff;
+extern cpuop_func_ce op_8110_21_nf;
+extern cpuop_func_ce op_8110_21_ff;
+extern cpuop_func_ce op_8118_21_nf;
+extern cpuop_func_ce op_8118_21_ff;
+extern cpuop_func_ce op_8120_21_nf;
+extern cpuop_func_ce op_8120_21_ff;
+extern cpuop_func_ce op_8128_21_nf;
+extern cpuop_func_ce op_8128_21_ff;
+extern cpuop_func_ce op_8130_21_nf;
+extern cpuop_func_ce op_8130_21_ff;
+extern cpuop_func_ce op_8138_21_nf;
+extern cpuop_func_ce op_8138_21_ff;
+extern cpuop_func_ce op_8139_21_nf;
+extern cpuop_func_ce op_8139_21_ff;
+extern cpuop_func_ce op_8140_21_nf;
+extern cpuop_func_ce op_8140_21_ff;
+extern cpuop_func_ce op_8148_21_nf;
+extern cpuop_func_ce op_8148_21_ff;
+extern cpuop_func_ce op_8150_21_nf;
+extern cpuop_func_ce op_8150_21_ff;
+extern cpuop_func_ce op_8158_21_nf;
+extern cpuop_func_ce op_8158_21_ff;
+extern cpuop_func_ce op_8160_21_nf;
+extern cpuop_func_ce op_8160_21_ff;
+extern cpuop_func_ce op_8168_21_nf;
+extern cpuop_func_ce op_8168_21_ff;
+extern cpuop_func_ce op_8170_21_nf;
+extern cpuop_func_ce op_8170_21_ff;
+extern cpuop_func_ce op_8178_21_nf;
+extern cpuop_func_ce op_8178_21_ff;
+extern cpuop_func_ce op_8179_21_nf;
+extern cpuop_func_ce op_8179_21_ff;
+extern cpuop_func_ce op_8180_21_nf;
+extern cpuop_func_ce op_8180_21_ff;
+extern cpuop_func_ce op_8188_21_nf;
+extern cpuop_func_ce op_8188_21_ff;
+extern cpuop_func_ce op_8190_21_nf;
+extern cpuop_func_ce op_8190_21_ff;
+extern cpuop_func_ce op_8198_21_nf;
+extern cpuop_func_ce op_8198_21_ff;
+extern cpuop_func_ce op_81a0_21_nf;
+extern cpuop_func_ce op_81a0_21_ff;
+extern cpuop_func_ce op_81a8_21_nf;
+extern cpuop_func_ce op_81a8_21_ff;
+extern cpuop_func_ce op_81b0_21_nf;
+extern cpuop_func_ce op_81b0_21_ff;
+extern cpuop_func_ce op_81b8_21_nf;
+extern cpuop_func_ce op_81b8_21_ff;
+extern cpuop_func_ce op_81b9_21_nf;
+extern cpuop_func_ce op_81b9_21_ff;
+extern cpuop_func_ce op_81c0_21_nf;
+extern cpuop_func_ce op_81c0_21_ff;
+extern cpuop_func_ce op_81d0_21_nf;
+extern cpuop_func_ce op_81d0_21_ff;
+extern cpuop_func_ce op_81d8_21_nf;
+extern cpuop_func_ce op_81d8_21_ff;
+extern cpuop_func_ce op_81e0_21_nf;
+extern cpuop_func_ce op_81e0_21_ff;
+extern cpuop_func_ce op_81e8_21_nf;
+extern cpuop_func_ce op_81e8_21_ff;
+extern cpuop_func_ce op_81f0_21_nf;
+extern cpuop_func_ce op_81f0_21_ff;
+extern cpuop_func_ce op_81f8_21_nf;
+extern cpuop_func_ce op_81f8_21_ff;
+extern cpuop_func_ce op_81f9_21_nf;
+extern cpuop_func_ce op_81f9_21_ff;
+extern cpuop_func_ce op_81fa_21_nf;
+extern cpuop_func_ce op_81fa_21_ff;
+extern cpuop_func_ce op_81fb_21_nf;
+extern cpuop_func_ce op_81fb_21_ff;
+extern cpuop_func_ce op_81fc_21_nf;
+extern cpuop_func_ce op_81fc_21_ff;
+extern cpuop_func_ce op_9000_21_nf;
+extern cpuop_func_ce op_9000_21_ff;
+extern cpuop_func_ce op_9010_21_nf;
+extern cpuop_func_ce op_9010_21_ff;
+extern cpuop_func_ce op_9018_21_nf;
+extern cpuop_func_ce op_9018_21_ff;
+extern cpuop_func_ce op_9020_21_nf;
+extern cpuop_func_ce op_9020_21_ff;
+extern cpuop_func_ce op_9028_21_nf;
+extern cpuop_func_ce op_9028_21_ff;
+extern cpuop_func_ce op_9030_21_nf;
+extern cpuop_func_ce op_9030_21_ff;
+extern cpuop_func_ce op_9038_21_nf;
+extern cpuop_func_ce op_9038_21_ff;
+extern cpuop_func_ce op_9039_21_nf;
+extern cpuop_func_ce op_9039_21_ff;
+extern cpuop_func_ce op_903a_21_nf;
+extern cpuop_func_ce op_903a_21_ff;
+extern cpuop_func_ce op_903b_21_nf;
+extern cpuop_func_ce op_903b_21_ff;
+extern cpuop_func_ce op_903c_21_nf;
+extern cpuop_func_ce op_903c_21_ff;
+extern cpuop_func_ce op_9040_21_nf;
+extern cpuop_func_ce op_9040_21_ff;
+extern cpuop_func_ce op_9048_21_nf;
+extern cpuop_func_ce op_9048_21_ff;
+extern cpuop_func_ce op_9050_21_nf;
+extern cpuop_func_ce op_9050_21_ff;
+extern cpuop_func_ce op_9058_21_nf;
+extern cpuop_func_ce op_9058_21_ff;
+extern cpuop_func_ce op_9060_21_nf;
+extern cpuop_func_ce op_9060_21_ff;
+extern cpuop_func_ce op_9068_21_nf;
+extern cpuop_func_ce op_9068_21_ff;
+extern cpuop_func_ce op_9070_21_nf;
+extern cpuop_func_ce op_9070_21_ff;
+extern cpuop_func_ce op_9078_21_nf;
+extern cpuop_func_ce op_9078_21_ff;
+extern cpuop_func_ce op_9079_21_nf;
+extern cpuop_func_ce op_9079_21_ff;
+extern cpuop_func_ce op_907a_21_nf;
+extern cpuop_func_ce op_907a_21_ff;
+extern cpuop_func_ce op_907b_21_nf;
+extern cpuop_func_ce op_907b_21_ff;
+extern cpuop_func_ce op_907c_21_nf;
+extern cpuop_func_ce op_907c_21_ff;
+extern cpuop_func_ce op_9080_21_nf;
+extern cpuop_func_ce op_9080_21_ff;
+extern cpuop_func_ce op_9088_21_nf;
+extern cpuop_func_ce op_9088_21_ff;
+extern cpuop_func_ce op_9090_21_nf;
+extern cpuop_func_ce op_9090_21_ff;
+extern cpuop_func_ce op_9098_21_nf;
+extern cpuop_func_ce op_9098_21_ff;
+extern cpuop_func_ce op_90a0_21_nf;
+extern cpuop_func_ce op_90a0_21_ff;
+extern cpuop_func_ce op_90a8_21_nf;
+extern cpuop_func_ce op_90a8_21_ff;
+extern cpuop_func_ce op_90b0_21_nf;
+extern cpuop_func_ce op_90b0_21_ff;
+extern cpuop_func_ce op_90b8_21_nf;
+extern cpuop_func_ce op_90b8_21_ff;
+extern cpuop_func_ce op_90b9_21_nf;
+extern cpuop_func_ce op_90b9_21_ff;
+extern cpuop_func_ce op_90ba_21_nf;
+extern cpuop_func_ce op_90ba_21_ff;
+extern cpuop_func_ce op_90bb_21_nf;
+extern cpuop_func_ce op_90bb_21_ff;
+extern cpuop_func_ce op_90bc_21_nf;
+extern cpuop_func_ce op_90bc_21_ff;
+extern cpuop_func_ce op_90c0_21_nf;
+extern cpuop_func_ce op_90c0_21_ff;
+extern cpuop_func_ce op_90c8_21_nf;
+extern cpuop_func_ce op_90c8_21_ff;
+extern cpuop_func_ce op_90d0_21_nf;
+extern cpuop_func_ce op_90d0_21_ff;
+extern cpuop_func_ce op_90d8_21_nf;
+extern cpuop_func_ce op_90d8_21_ff;
+extern cpuop_func_ce op_90e0_21_nf;
+extern cpuop_func_ce op_90e0_21_ff;
+extern cpuop_func_ce op_90e8_21_nf;
+extern cpuop_func_ce op_90e8_21_ff;
+extern cpuop_func_ce op_90f0_21_nf;
+extern cpuop_func_ce op_90f0_21_ff;
+extern cpuop_func_ce op_90f8_21_nf;
+extern cpuop_func_ce op_90f8_21_ff;
+extern cpuop_func_ce op_90f9_21_nf;
+extern cpuop_func_ce op_90f9_21_ff;
+extern cpuop_func_ce op_90fa_21_nf;
+extern cpuop_func_ce op_90fa_21_ff;
+extern cpuop_func_ce op_90fb_21_nf;
+extern cpuop_func_ce op_90fb_21_ff;
+extern cpuop_func_ce op_90fc_21_nf;
+extern cpuop_func_ce op_90fc_21_ff;
+extern cpuop_func_ce op_9100_21_nf;
+extern cpuop_func_ce op_9100_21_ff;
+extern cpuop_func_ce op_9108_21_nf;
+extern cpuop_func_ce op_9108_21_ff;
+extern cpuop_func_ce op_9110_21_nf;
+extern cpuop_func_ce op_9110_21_ff;
+extern cpuop_func_ce op_9118_21_nf;
+extern cpuop_func_ce op_9118_21_ff;
+extern cpuop_func_ce op_9120_21_nf;
+extern cpuop_func_ce op_9120_21_ff;
+extern cpuop_func_ce op_9128_21_nf;
+extern cpuop_func_ce op_9128_21_ff;
+extern cpuop_func_ce op_9130_21_nf;
+extern cpuop_func_ce op_9130_21_ff;
+extern cpuop_func_ce op_9138_21_nf;
+extern cpuop_func_ce op_9138_21_ff;
+extern cpuop_func_ce op_9139_21_nf;
+extern cpuop_func_ce op_9139_21_ff;
+extern cpuop_func_ce op_9140_21_nf;
+extern cpuop_func_ce op_9140_21_ff;
+extern cpuop_func_ce op_9148_21_nf;
+extern cpuop_func_ce op_9148_21_ff;
+extern cpuop_func_ce op_9150_21_nf;
+extern cpuop_func_ce op_9150_21_ff;
+extern cpuop_func_ce op_9158_21_nf;
+extern cpuop_func_ce op_9158_21_ff;
+extern cpuop_func_ce op_9160_21_nf;
+extern cpuop_func_ce op_9160_21_ff;
+extern cpuop_func_ce op_9168_21_nf;
+extern cpuop_func_ce op_9168_21_ff;
+extern cpuop_func_ce op_9170_21_nf;
+extern cpuop_func_ce op_9170_21_ff;
+extern cpuop_func_ce op_9178_21_nf;
+extern cpuop_func_ce op_9178_21_ff;
+extern cpuop_func_ce op_9179_21_nf;
+extern cpuop_func_ce op_9179_21_ff;
+extern cpuop_func_ce op_9180_21_nf;
+extern cpuop_func_ce op_9180_21_ff;
+extern cpuop_func_ce op_9188_21_nf;
+extern cpuop_func_ce op_9188_21_ff;
+extern cpuop_func_ce op_9190_21_nf;
+extern cpuop_func_ce op_9190_21_ff;
+extern cpuop_func_ce op_9198_21_nf;
+extern cpuop_func_ce op_9198_21_ff;
+extern cpuop_func_ce op_91a0_21_nf;
+extern cpuop_func_ce op_91a0_21_ff;
+extern cpuop_func_ce op_91a8_21_nf;
+extern cpuop_func_ce op_91a8_21_ff;
+extern cpuop_func_ce op_91b0_21_nf;
+extern cpuop_func_ce op_91b0_21_ff;
+extern cpuop_func_ce op_91b8_21_nf;
+extern cpuop_func_ce op_91b8_21_ff;
+extern cpuop_func_ce op_91b9_21_nf;
+extern cpuop_func_ce op_91b9_21_ff;
+extern cpuop_func_ce op_91c0_21_nf;
+extern cpuop_func_ce op_91c0_21_ff;
+extern cpuop_func_ce op_91c8_21_nf;
+extern cpuop_func_ce op_91c8_21_ff;
+extern cpuop_func_ce op_91d0_21_nf;
+extern cpuop_func_ce op_91d0_21_ff;
+extern cpuop_func_ce op_91d8_21_nf;
+extern cpuop_func_ce op_91d8_21_ff;
+extern cpuop_func_ce op_91e0_21_nf;
+extern cpuop_func_ce op_91e0_21_ff;
+extern cpuop_func_ce op_91e8_21_nf;
+extern cpuop_func_ce op_91e8_21_ff;
+extern cpuop_func_ce op_91f0_21_nf;
+extern cpuop_func_ce op_91f0_21_ff;
+extern cpuop_func_ce op_91f8_21_nf;
+extern cpuop_func_ce op_91f8_21_ff;
+extern cpuop_func_ce op_91f9_21_nf;
+extern cpuop_func_ce op_91f9_21_ff;
+extern cpuop_func_ce op_91fa_21_nf;
+extern cpuop_func_ce op_91fa_21_ff;
+extern cpuop_func_ce op_91fb_21_nf;
+extern cpuop_func_ce op_91fb_21_ff;
+extern cpuop_func_ce op_91fc_21_nf;
+extern cpuop_func_ce op_91fc_21_ff;
+extern cpuop_func_ce op_b000_21_nf;
+extern cpuop_func_ce op_b000_21_ff;
+extern cpuop_func_ce op_b010_21_nf;
+extern cpuop_func_ce op_b010_21_ff;
+extern cpuop_func_ce op_b018_21_nf;
+extern cpuop_func_ce op_b018_21_ff;
+extern cpuop_func_ce op_b020_21_nf;
+extern cpuop_func_ce op_b020_21_ff;
+extern cpuop_func_ce op_b028_21_nf;
+extern cpuop_func_ce op_b028_21_ff;
+extern cpuop_func_ce op_b030_21_nf;
+extern cpuop_func_ce op_b030_21_ff;
+extern cpuop_func_ce op_b038_21_nf;
+extern cpuop_func_ce op_b038_21_ff;
+extern cpuop_func_ce op_b039_21_nf;
+extern cpuop_func_ce op_b039_21_ff;
+extern cpuop_func_ce op_b03a_21_nf;
+extern cpuop_func_ce op_b03a_21_ff;
+extern cpuop_func_ce op_b03b_21_nf;
+extern cpuop_func_ce op_b03b_21_ff;
+extern cpuop_func_ce op_b03c_21_nf;
+extern cpuop_func_ce op_b03c_21_ff;
+extern cpuop_func_ce op_b040_21_nf;
+extern cpuop_func_ce op_b040_21_ff;
+extern cpuop_func_ce op_b048_21_nf;
+extern cpuop_func_ce op_b048_21_ff;
+extern cpuop_func_ce op_b050_21_nf;
+extern cpuop_func_ce op_b050_21_ff;
+extern cpuop_func_ce op_b058_21_nf;
+extern cpuop_func_ce op_b058_21_ff;
+extern cpuop_func_ce op_b060_21_nf;
+extern cpuop_func_ce op_b060_21_ff;
+extern cpuop_func_ce op_b068_21_nf;
+extern cpuop_func_ce op_b068_21_ff;
+extern cpuop_func_ce op_b070_21_nf;
+extern cpuop_func_ce op_b070_21_ff;
+extern cpuop_func_ce op_b078_21_nf;
+extern cpuop_func_ce op_b078_21_ff;
+extern cpuop_func_ce op_b079_21_nf;
+extern cpuop_func_ce op_b079_21_ff;
+extern cpuop_func_ce op_b07a_21_nf;
+extern cpuop_func_ce op_b07a_21_ff;
+extern cpuop_func_ce op_b07b_21_nf;
+extern cpuop_func_ce op_b07b_21_ff;
+extern cpuop_func_ce op_b07c_21_nf;
+extern cpuop_func_ce op_b07c_21_ff;
+extern cpuop_func_ce op_b080_21_nf;
+extern cpuop_func_ce op_b080_21_ff;
+extern cpuop_func_ce op_b088_21_nf;
+extern cpuop_func_ce op_b088_21_ff;
+extern cpuop_func_ce op_b090_21_nf;
+extern cpuop_func_ce op_b090_21_ff;
+extern cpuop_func_ce op_b098_21_nf;
+extern cpuop_func_ce op_b098_21_ff;
+extern cpuop_func_ce op_b0a0_21_nf;
+extern cpuop_func_ce op_b0a0_21_ff;
+extern cpuop_func_ce op_b0a8_21_nf;
+extern cpuop_func_ce op_b0a8_21_ff;
+extern cpuop_func_ce op_b0b0_21_nf;
+extern cpuop_func_ce op_b0b0_21_ff;
+extern cpuop_func_ce op_b0b8_21_nf;
+extern cpuop_func_ce op_b0b8_21_ff;
+extern cpuop_func_ce op_b0b9_21_nf;
+extern cpuop_func_ce op_b0b9_21_ff;
+extern cpuop_func_ce op_b0ba_21_nf;
+extern cpuop_func_ce op_b0ba_21_ff;
+extern cpuop_func_ce op_b0bb_21_nf;
+extern cpuop_func_ce op_b0bb_21_ff;
+extern cpuop_func_ce op_b0bc_21_nf;
+extern cpuop_func_ce op_b0bc_21_ff;
+extern cpuop_func_ce op_b0c0_21_nf;
+extern cpuop_func_ce op_b0c0_21_ff;
+extern cpuop_func_ce op_b0c8_21_nf;
+extern cpuop_func_ce op_b0c8_21_ff;
+extern cpuop_func_ce op_b0d0_21_nf;
+extern cpuop_func_ce op_b0d0_21_ff;
+extern cpuop_func_ce op_b0d8_21_nf;
+extern cpuop_func_ce op_b0d8_21_ff;
+extern cpuop_func_ce op_b0e0_21_nf;
+extern cpuop_func_ce op_b0e0_21_ff;
+extern cpuop_func_ce op_b0e8_21_nf;
+extern cpuop_func_ce op_b0e8_21_ff;
+extern cpuop_func_ce op_b0f0_21_nf;
+extern cpuop_func_ce op_b0f0_21_ff;
+extern cpuop_func_ce op_b0f8_21_nf;
+extern cpuop_func_ce op_b0f8_21_ff;
+extern cpuop_func_ce op_b0f9_21_nf;
+extern cpuop_func_ce op_b0f9_21_ff;
+extern cpuop_func_ce op_b0fa_21_nf;
+extern cpuop_func_ce op_b0fa_21_ff;
+extern cpuop_func_ce op_b0fb_21_nf;
+extern cpuop_func_ce op_b0fb_21_ff;
+extern cpuop_func_ce op_b0fc_21_nf;
+extern cpuop_func_ce op_b0fc_21_ff;
+extern cpuop_func_ce op_b100_21_nf;
+extern cpuop_func_ce op_b100_21_ff;
+extern cpuop_func_ce op_b108_21_nf;
+extern cpuop_func_ce op_b108_21_ff;
+extern cpuop_func_ce op_b110_21_nf;
+extern cpuop_func_ce op_b110_21_ff;
+extern cpuop_func_ce op_b118_21_nf;
+extern cpuop_func_ce op_b118_21_ff;
+extern cpuop_func_ce op_b120_21_nf;
+extern cpuop_func_ce op_b120_21_ff;
+extern cpuop_func_ce op_b128_21_nf;
+extern cpuop_func_ce op_b128_21_ff;
+extern cpuop_func_ce op_b130_21_nf;
+extern cpuop_func_ce op_b130_21_ff;
+extern cpuop_func_ce op_b138_21_nf;
+extern cpuop_func_ce op_b138_21_ff;
+extern cpuop_func_ce op_b139_21_nf;
+extern cpuop_func_ce op_b139_21_ff;
+extern cpuop_func_ce op_b140_21_nf;
+extern cpuop_func_ce op_b140_21_ff;
+extern cpuop_func_ce op_b148_21_nf;
+extern cpuop_func_ce op_b148_21_ff;
+extern cpuop_func_ce op_b150_21_nf;
+extern cpuop_func_ce op_b150_21_ff;
+extern cpuop_func_ce op_b158_21_nf;
+extern cpuop_func_ce op_b158_21_ff;
+extern cpuop_func_ce op_b160_21_nf;
+extern cpuop_func_ce op_b160_21_ff;
+extern cpuop_func_ce op_b168_21_nf;
+extern cpuop_func_ce op_b168_21_ff;
+extern cpuop_func_ce op_b170_21_nf;
+extern cpuop_func_ce op_b170_21_ff;
+extern cpuop_func_ce op_b178_21_nf;
+extern cpuop_func_ce op_b178_21_ff;
+extern cpuop_func_ce op_b179_21_nf;
+extern cpuop_func_ce op_b179_21_ff;
+extern cpuop_func_ce op_b180_21_nf;
+extern cpuop_func_ce op_b180_21_ff;
+extern cpuop_func_ce op_b188_21_nf;
+extern cpuop_func_ce op_b188_21_ff;
+extern cpuop_func_ce op_b190_21_nf;
+extern cpuop_func_ce op_b190_21_ff;
+extern cpuop_func_ce op_b198_21_nf;
+extern cpuop_func_ce op_b198_21_ff;
+extern cpuop_func_ce op_b1a0_21_nf;
+extern cpuop_func_ce op_b1a0_21_ff;
+extern cpuop_func_ce op_b1a8_21_nf;
+extern cpuop_func_ce op_b1a8_21_ff;
+extern cpuop_func_ce op_b1b0_21_nf;
+extern cpuop_func_ce op_b1b0_21_ff;
+extern cpuop_func_ce op_b1b8_21_nf;
+extern cpuop_func_ce op_b1b8_21_ff;
+extern cpuop_func_ce op_b1b9_21_nf;
+extern cpuop_func_ce op_b1b9_21_ff;
+extern cpuop_func_ce op_b1c0_21_nf;
+extern cpuop_func_ce op_b1c0_21_ff;
+extern cpuop_func_ce op_b1c8_21_nf;
+extern cpuop_func_ce op_b1c8_21_ff;
+extern cpuop_func_ce op_b1d0_21_nf;
+extern cpuop_func_ce op_b1d0_21_ff;
+extern cpuop_func_ce op_b1d8_21_nf;
+extern cpuop_func_ce op_b1d8_21_ff;
+extern cpuop_func_ce op_b1e0_21_nf;
+extern cpuop_func_ce op_b1e0_21_ff;
+extern cpuop_func_ce op_b1e8_21_nf;
+extern cpuop_func_ce op_b1e8_21_ff;
+extern cpuop_func_ce op_b1f0_21_nf;
+extern cpuop_func_ce op_b1f0_21_ff;
+extern cpuop_func_ce op_b1f8_21_nf;
+extern cpuop_func_ce op_b1f8_21_ff;
+extern cpuop_func_ce op_b1f9_21_nf;
+extern cpuop_func_ce op_b1f9_21_ff;
+extern cpuop_func_ce op_b1fa_21_nf;
+extern cpuop_func_ce op_b1fa_21_ff;
+extern cpuop_func_ce op_b1fb_21_nf;
+extern cpuop_func_ce op_b1fb_21_ff;
+extern cpuop_func_ce op_b1fc_21_nf;
+extern cpuop_func_ce op_b1fc_21_ff;
+extern cpuop_func_ce op_c000_21_nf;
+extern cpuop_func_ce op_c000_21_ff;
+extern cpuop_func_ce op_c010_21_nf;
+extern cpuop_func_ce op_c010_21_ff;
+extern cpuop_func_ce op_c018_21_nf;
+extern cpuop_func_ce op_c018_21_ff;
+extern cpuop_func_ce op_c020_21_nf;
+extern cpuop_func_ce op_c020_21_ff;
+extern cpuop_func_ce op_c028_21_nf;
+extern cpuop_func_ce op_c028_21_ff;
+extern cpuop_func_ce op_c030_21_nf;
+extern cpuop_func_ce op_c030_21_ff;
+extern cpuop_func_ce op_c038_21_nf;
+extern cpuop_func_ce op_c038_21_ff;
+extern cpuop_func_ce op_c039_21_nf;
+extern cpuop_func_ce op_c039_21_ff;
+extern cpuop_func_ce op_c03a_21_nf;
+extern cpuop_func_ce op_c03a_21_ff;
+extern cpuop_func_ce op_c03b_21_nf;
+extern cpuop_func_ce op_c03b_21_ff;
+extern cpuop_func_ce op_c03c_21_nf;
+extern cpuop_func_ce op_c03c_21_ff;
+extern cpuop_func_ce op_c040_21_nf;
+extern cpuop_func_ce op_c040_21_ff;
+extern cpuop_func_ce op_c050_21_nf;
+extern cpuop_func_ce op_c050_21_ff;
+extern cpuop_func_ce op_c058_21_nf;
+extern cpuop_func_ce op_c058_21_ff;
+extern cpuop_func_ce op_c060_21_nf;
+extern cpuop_func_ce op_c060_21_ff;
+extern cpuop_func_ce op_c068_21_nf;
+extern cpuop_func_ce op_c068_21_ff;
+extern cpuop_func_ce op_c070_21_nf;
+extern cpuop_func_ce op_c070_21_ff;
+extern cpuop_func_ce op_c078_21_nf;
+extern cpuop_func_ce op_c078_21_ff;
+extern cpuop_func_ce op_c079_21_nf;
+extern cpuop_func_ce op_c079_21_ff;
+extern cpuop_func_ce op_c07a_21_nf;
+extern cpuop_func_ce op_c07a_21_ff;
+extern cpuop_func_ce op_c07b_21_nf;
+extern cpuop_func_ce op_c07b_21_ff;
+extern cpuop_func_ce op_c07c_21_nf;
+extern cpuop_func_ce op_c07c_21_ff;
+extern cpuop_func_ce op_c080_21_nf;
+extern cpuop_func_ce op_c080_21_ff;
+extern cpuop_func_ce op_c090_21_nf;
+extern cpuop_func_ce op_c090_21_ff;
+extern cpuop_func_ce op_c098_21_nf;
+extern cpuop_func_ce op_c098_21_ff;
+extern cpuop_func_ce op_c0a0_21_nf;
+extern cpuop_func_ce op_c0a0_21_ff;
+extern cpuop_func_ce op_c0a8_21_nf;
+extern cpuop_func_ce op_c0a8_21_ff;
+extern cpuop_func_ce op_c0b0_21_nf;
+extern cpuop_func_ce op_c0b0_21_ff;
+extern cpuop_func_ce op_c0b8_21_nf;
+extern cpuop_func_ce op_c0b8_21_ff;
+extern cpuop_func_ce op_c0b9_21_nf;
+extern cpuop_func_ce op_c0b9_21_ff;
+extern cpuop_func_ce op_c0ba_21_nf;
+extern cpuop_func_ce op_c0ba_21_ff;
+extern cpuop_func_ce op_c0bb_21_nf;
+extern cpuop_func_ce op_c0bb_21_ff;
+extern cpuop_func_ce op_c0bc_21_nf;
+extern cpuop_func_ce op_c0bc_21_ff;
+extern cpuop_func_ce op_c0c0_21_nf;
+extern cpuop_func_ce op_c0c0_21_ff;
+extern cpuop_func_ce op_c0d0_21_nf;
+extern cpuop_func_ce op_c0d0_21_ff;
+extern cpuop_func_ce op_c0d8_21_nf;
+extern cpuop_func_ce op_c0d8_21_ff;
+extern cpuop_func_ce op_c0e0_21_nf;
+extern cpuop_func_ce op_c0e0_21_ff;
+extern cpuop_func_ce op_c0e8_21_nf;
+extern cpuop_func_ce op_c0e8_21_ff;
+extern cpuop_func_ce op_c0f0_21_nf;
+extern cpuop_func_ce op_c0f0_21_ff;
+extern cpuop_func_ce op_c0f8_21_nf;
+extern cpuop_func_ce op_c0f8_21_ff;
+extern cpuop_func_ce op_c0f9_21_nf;
+extern cpuop_func_ce op_c0f9_21_ff;
+extern cpuop_func_ce op_c0fa_21_nf;
+extern cpuop_func_ce op_c0fa_21_ff;
+extern cpuop_func_ce op_c0fb_21_nf;
+extern cpuop_func_ce op_c0fb_21_ff;
+extern cpuop_func_ce op_c0fc_21_nf;
+extern cpuop_func_ce op_c0fc_21_ff;
+extern cpuop_func_ce op_c100_21_nf;
+extern cpuop_func_ce op_c100_21_ff;
+extern cpuop_func_ce op_c108_21_nf;
+extern cpuop_func_ce op_c108_21_ff;
+extern cpuop_func_ce op_c110_21_nf;
+extern cpuop_func_ce op_c110_21_ff;
+extern cpuop_func_ce op_c118_21_nf;
+extern cpuop_func_ce op_c118_21_ff;
+extern cpuop_func_ce op_c120_21_nf;
+extern cpuop_func_ce op_c120_21_ff;
+extern cpuop_func_ce op_c128_21_nf;
+extern cpuop_func_ce op_c128_21_ff;
+extern cpuop_func_ce op_c130_21_nf;
+extern cpuop_func_ce op_c130_21_ff;
+extern cpuop_func_ce op_c138_21_nf;
+extern cpuop_func_ce op_c138_21_ff;
+extern cpuop_func_ce op_c139_21_nf;
+extern cpuop_func_ce op_c139_21_ff;
+extern cpuop_func_ce op_c140_21_nf;
+extern cpuop_func_ce op_c140_21_ff;
+extern cpuop_func_ce op_c148_21_nf;
+extern cpuop_func_ce op_c148_21_ff;
+extern cpuop_func_ce op_c150_21_nf;
+extern cpuop_func_ce op_c150_21_ff;
+extern cpuop_func_ce op_c158_21_nf;
+extern cpuop_func_ce op_c158_21_ff;
+extern cpuop_func_ce op_c160_21_nf;
+extern cpuop_func_ce op_c160_21_ff;
+extern cpuop_func_ce op_c168_21_nf;
+extern cpuop_func_ce op_c168_21_ff;
+extern cpuop_func_ce op_c170_21_nf;
+extern cpuop_func_ce op_c170_21_ff;
+extern cpuop_func_ce op_c178_21_nf;
+extern cpuop_func_ce op_c178_21_ff;
+extern cpuop_func_ce op_c179_21_nf;
+extern cpuop_func_ce op_c179_21_ff;
+extern cpuop_func_ce op_c188_21_nf;
+extern cpuop_func_ce op_c188_21_ff;
+extern cpuop_func_ce op_c190_21_nf;
+extern cpuop_func_ce op_c190_21_ff;
+extern cpuop_func_ce op_c198_21_nf;
+extern cpuop_func_ce op_c198_21_ff;
+extern cpuop_func_ce op_c1a0_21_nf;
+extern cpuop_func_ce op_c1a0_21_ff;
+extern cpuop_func_ce op_c1a8_21_nf;
+extern cpuop_func_ce op_c1a8_21_ff;
+extern cpuop_func_ce op_c1b0_21_nf;
+extern cpuop_func_ce op_c1b0_21_ff;
+extern cpuop_func_ce op_c1b8_21_nf;
+extern cpuop_func_ce op_c1b8_21_ff;
+extern cpuop_func_ce op_c1b9_21_nf;
+extern cpuop_func_ce op_c1b9_21_ff;
+extern cpuop_func_ce op_c1c0_21_nf;
+extern cpuop_func_ce op_c1c0_21_ff;
+extern cpuop_func_ce op_c1d0_21_nf;
+extern cpuop_func_ce op_c1d0_21_ff;
+extern cpuop_func_ce op_c1d8_21_nf;
+extern cpuop_func_ce op_c1d8_21_ff;
+extern cpuop_func_ce op_c1e0_21_nf;
+extern cpuop_func_ce op_c1e0_21_ff;
+extern cpuop_func_ce op_c1e8_21_nf;
+extern cpuop_func_ce op_c1e8_21_ff;
+extern cpuop_func_ce op_c1f0_21_nf;
+extern cpuop_func_ce op_c1f0_21_ff;
+extern cpuop_func_ce op_c1f8_21_nf;
+extern cpuop_func_ce op_c1f8_21_ff;
+extern cpuop_func_ce op_c1f9_21_nf;
+extern cpuop_func_ce op_c1f9_21_ff;
+extern cpuop_func_ce op_c1fa_21_nf;
+extern cpuop_func_ce op_c1fa_21_ff;
+extern cpuop_func_ce op_c1fb_21_nf;
+extern cpuop_func_ce op_c1fb_21_ff;
+extern cpuop_func_ce op_c1fc_21_nf;
+extern cpuop_func_ce op_c1fc_21_ff;
+extern cpuop_func_ce op_d000_21_nf;
+extern cpuop_func_ce op_d000_21_ff;
+extern cpuop_func_ce op_d010_21_nf;
+extern cpuop_func_ce op_d010_21_ff;
+extern cpuop_func_ce op_d018_21_nf;
+extern cpuop_func_ce op_d018_21_ff;
+extern cpuop_func_ce op_d020_21_nf;
+extern cpuop_func_ce op_d020_21_ff;
+extern cpuop_func_ce op_d028_21_nf;
+extern cpuop_func_ce op_d028_21_ff;
+extern cpuop_func_ce op_d030_21_nf;
+extern cpuop_func_ce op_d030_21_ff;
+extern cpuop_func_ce op_d038_21_nf;
+extern cpuop_func_ce op_d038_21_ff;
+extern cpuop_func_ce op_d039_21_nf;
+extern cpuop_func_ce op_d039_21_ff;
+extern cpuop_func_ce op_d03a_21_nf;
+extern cpuop_func_ce op_d03a_21_ff;
+extern cpuop_func_ce op_d03b_21_nf;
+extern cpuop_func_ce op_d03b_21_ff;
+extern cpuop_func_ce op_d03c_21_nf;
+extern cpuop_func_ce op_d03c_21_ff;
+extern cpuop_func_ce op_d040_21_nf;
+extern cpuop_func_ce op_d040_21_ff;
+extern cpuop_func_ce op_d048_21_nf;
+extern cpuop_func_ce op_d048_21_ff;
+extern cpuop_func_ce op_d050_21_nf;
+extern cpuop_func_ce op_d050_21_ff;
+extern cpuop_func_ce op_d058_21_nf;
+extern cpuop_func_ce op_d058_21_ff;
+extern cpuop_func_ce op_d060_21_nf;
+extern cpuop_func_ce op_d060_21_ff;
+extern cpuop_func_ce op_d068_21_nf;
+extern cpuop_func_ce op_d068_21_ff;
+extern cpuop_func_ce op_d070_21_nf;
+extern cpuop_func_ce op_d070_21_ff;
+extern cpuop_func_ce op_d078_21_nf;
+extern cpuop_func_ce op_d078_21_ff;
+extern cpuop_func_ce op_d079_21_nf;
+extern cpuop_func_ce op_d079_21_ff;
+extern cpuop_func_ce op_d07a_21_nf;
+extern cpuop_func_ce op_d07a_21_ff;
+extern cpuop_func_ce op_d07b_21_nf;
+extern cpuop_func_ce op_d07b_21_ff;
+extern cpuop_func_ce op_d07c_21_nf;
+extern cpuop_func_ce op_d07c_21_ff;
+extern cpuop_func_ce op_d080_21_nf;
+extern cpuop_func_ce op_d080_21_ff;
+extern cpuop_func_ce op_d088_21_nf;
+extern cpuop_func_ce op_d088_21_ff;
+extern cpuop_func_ce op_d090_21_nf;
+extern cpuop_func_ce op_d090_21_ff;
+extern cpuop_func_ce op_d098_21_nf;
+extern cpuop_func_ce op_d098_21_ff;
+extern cpuop_func_ce op_d0a0_21_nf;
+extern cpuop_func_ce op_d0a0_21_ff;
+extern cpuop_func_ce op_d0a8_21_nf;
+extern cpuop_func_ce op_d0a8_21_ff;
+extern cpuop_func_ce op_d0b0_21_nf;
+extern cpuop_func_ce op_d0b0_21_ff;
+extern cpuop_func_ce op_d0b8_21_nf;
+extern cpuop_func_ce op_d0b8_21_ff;
+extern cpuop_func_ce op_d0b9_21_nf;
+extern cpuop_func_ce op_d0b9_21_ff;
+extern cpuop_func_ce op_d0ba_21_nf;
+extern cpuop_func_ce op_d0ba_21_ff;
+extern cpuop_func_ce op_d0bb_21_nf;
+extern cpuop_func_ce op_d0bb_21_ff;
+extern cpuop_func_ce op_d0bc_21_nf;
+extern cpuop_func_ce op_d0bc_21_ff;
+extern cpuop_func_ce op_d0c0_21_nf;
+extern cpuop_func_ce op_d0c0_21_ff;
+extern cpuop_func_ce op_d0c8_21_nf;
+extern cpuop_func_ce op_d0c8_21_ff;
+extern cpuop_func_ce op_d0d0_21_nf;
+extern cpuop_func_ce op_d0d0_21_ff;
+extern cpuop_func_ce op_d0d8_21_nf;
+extern cpuop_func_ce op_d0d8_21_ff;
+extern cpuop_func_ce op_d0e0_21_nf;
+extern cpuop_func_ce op_d0e0_21_ff;
+extern cpuop_func_ce op_d0e8_21_nf;
+extern cpuop_func_ce op_d0e8_21_ff;
+extern cpuop_func_ce op_d0f0_21_nf;
+extern cpuop_func_ce op_d0f0_21_ff;
+extern cpuop_func_ce op_d0f8_21_nf;
+extern cpuop_func_ce op_d0f8_21_ff;
+extern cpuop_func_ce op_d0f9_21_nf;
+extern cpuop_func_ce op_d0f9_21_ff;
+extern cpuop_func_ce op_d0fa_21_nf;
+extern cpuop_func_ce op_d0fa_21_ff;
+extern cpuop_func_ce op_d0fb_21_nf;
+extern cpuop_func_ce op_d0fb_21_ff;
+extern cpuop_func_ce op_d0fc_21_nf;
+extern cpuop_func_ce op_d0fc_21_ff;
+extern cpuop_func_ce op_d100_21_nf;
+extern cpuop_func_ce op_d100_21_ff;
+extern cpuop_func_ce op_d108_21_nf;
+extern cpuop_func_ce op_d108_21_ff;
+extern cpuop_func_ce op_d110_21_nf;
+extern cpuop_func_ce op_d110_21_ff;
+extern cpuop_func_ce op_d118_21_nf;
+extern cpuop_func_ce op_d118_21_ff;
+extern cpuop_func_ce op_d120_21_nf;
+extern cpuop_func_ce op_d120_21_ff;
+extern cpuop_func_ce op_d128_21_nf;
+extern cpuop_func_ce op_d128_21_ff;
+extern cpuop_func_ce op_d130_21_nf;
+extern cpuop_func_ce op_d130_21_ff;
+extern cpuop_func_ce op_d138_21_nf;
+extern cpuop_func_ce op_d138_21_ff;
+extern cpuop_func_ce op_d139_21_nf;
+extern cpuop_func_ce op_d139_21_ff;
+extern cpuop_func_ce op_d140_21_nf;
+extern cpuop_func_ce op_d140_21_ff;
+extern cpuop_func_ce op_d148_21_nf;
+extern cpuop_func_ce op_d148_21_ff;
+extern cpuop_func_ce op_d150_21_nf;
+extern cpuop_func_ce op_d150_21_ff;
+extern cpuop_func_ce op_d158_21_nf;
+extern cpuop_func_ce op_d158_21_ff;
+extern cpuop_func_ce op_d160_21_nf;
+extern cpuop_func_ce op_d160_21_ff;
+extern cpuop_func_ce op_d168_21_nf;
+extern cpuop_func_ce op_d168_21_ff;
+extern cpuop_func_ce op_d170_21_nf;
+extern cpuop_func_ce op_d170_21_ff;
+extern cpuop_func_ce op_d178_21_nf;
+extern cpuop_func_ce op_d178_21_ff;
+extern cpuop_func_ce op_d179_21_nf;
+extern cpuop_func_ce op_d179_21_ff;
+extern cpuop_func_ce op_d180_21_nf;
+extern cpuop_func_ce op_d180_21_ff;
+extern cpuop_func_ce op_d188_21_nf;
+extern cpuop_func_ce op_d188_21_ff;
+extern cpuop_func_ce op_d190_21_nf;
+extern cpuop_func_ce op_d190_21_ff;
+extern cpuop_func_ce op_d198_21_nf;
+extern cpuop_func_ce op_d198_21_ff;
+extern cpuop_func_ce op_d1a0_21_nf;
+extern cpuop_func_ce op_d1a0_21_ff;
+extern cpuop_func_ce op_d1a8_21_nf;
+extern cpuop_func_ce op_d1a8_21_ff;
+extern cpuop_func_ce op_d1b0_21_nf;
+extern cpuop_func_ce op_d1b0_21_ff;
+extern cpuop_func_ce op_d1b8_21_nf;
+extern cpuop_func_ce op_d1b8_21_ff;
+extern cpuop_func_ce op_d1b9_21_nf;
+extern cpuop_func_ce op_d1b9_21_ff;
+extern cpuop_func_ce op_d1c0_21_nf;
+extern cpuop_func_ce op_d1c0_21_ff;
+extern cpuop_func_ce op_d1c8_21_nf;
+extern cpuop_func_ce op_d1c8_21_ff;
+extern cpuop_func_ce op_d1d0_21_nf;
+extern cpuop_func_ce op_d1d0_21_ff;
+extern cpuop_func_ce op_d1d8_21_nf;
+extern cpuop_func_ce op_d1d8_21_ff;
+extern cpuop_func_ce op_d1e0_21_nf;
+extern cpuop_func_ce op_d1e0_21_ff;
+extern cpuop_func_ce op_d1e8_21_nf;
+extern cpuop_func_ce op_d1e8_21_ff;
+extern cpuop_func_ce op_d1f0_21_nf;
+extern cpuop_func_ce op_d1f0_21_ff;
+extern cpuop_func_ce op_d1f8_21_nf;
+extern cpuop_func_ce op_d1f8_21_ff;
+extern cpuop_func_ce op_d1f9_21_nf;
+extern cpuop_func_ce op_d1f9_21_ff;
+extern cpuop_func_ce op_d1fa_21_nf;
+extern cpuop_func_ce op_d1fa_21_ff;
+extern cpuop_func_ce op_d1fb_21_nf;
+extern cpuop_func_ce op_d1fb_21_ff;
+extern cpuop_func_ce op_d1fc_21_nf;
+extern cpuop_func_ce op_d1fc_21_ff;
+extern cpuop_func_ce op_e000_21_nf;
+extern cpuop_func_ce op_e000_21_ff;
+extern cpuop_func_ce op_e008_21_nf;
+extern cpuop_func_ce op_e008_21_ff;
+extern cpuop_func_ce op_e010_21_nf;
+extern cpuop_func_ce op_e010_21_ff;
+extern cpuop_func_ce op_e018_21_nf;
+extern cpuop_func_ce op_e018_21_ff;
+extern cpuop_func_ce op_e020_21_nf;
+extern cpuop_func_ce op_e020_21_ff;
+extern cpuop_func_ce op_e028_21_nf;
+extern cpuop_func_ce op_e028_21_ff;
+extern cpuop_func_ce op_e030_21_nf;
+extern cpuop_func_ce op_e030_21_ff;
+extern cpuop_func_ce op_e038_21_nf;
+extern cpuop_func_ce op_e038_21_ff;
+extern cpuop_func_ce op_e040_21_nf;
+extern cpuop_func_ce op_e040_21_ff;
+extern cpuop_func_ce op_e048_21_nf;
+extern cpuop_func_ce op_e048_21_ff;
+extern cpuop_func_ce op_e050_21_nf;
+extern cpuop_func_ce op_e050_21_ff;
+extern cpuop_func_ce op_e058_21_nf;
+extern cpuop_func_ce op_e058_21_ff;
+extern cpuop_func_ce op_e060_21_nf;
+extern cpuop_func_ce op_e060_21_ff;
+extern cpuop_func_ce op_e068_21_nf;
+extern cpuop_func_ce op_e068_21_ff;
+extern cpuop_func_ce op_e070_21_nf;
+extern cpuop_func_ce op_e070_21_ff;
+extern cpuop_func_ce op_e078_21_nf;
+extern cpuop_func_ce op_e078_21_ff;
+extern cpuop_func_ce op_e080_21_nf;
+extern cpuop_func_ce op_e080_21_ff;
+extern cpuop_func_ce op_e088_21_nf;
+extern cpuop_func_ce op_e088_21_ff;
+extern cpuop_func_ce op_e090_21_nf;
+extern cpuop_func_ce op_e090_21_ff;
+extern cpuop_func_ce op_e098_21_nf;
+extern cpuop_func_ce op_e098_21_ff;
+extern cpuop_func_ce op_e0a0_21_nf;
+extern cpuop_func_ce op_e0a0_21_ff;
+extern cpuop_func_ce op_e0a8_21_nf;
+extern cpuop_func_ce op_e0a8_21_ff;
+extern cpuop_func_ce op_e0b0_21_nf;
+extern cpuop_func_ce op_e0b0_21_ff;
+extern cpuop_func_ce op_e0b8_21_nf;
+extern cpuop_func_ce op_e0b8_21_ff;
+extern cpuop_func_ce op_e0d0_21_nf;
+extern cpuop_func_ce op_e0d0_21_ff;
+extern cpuop_func_ce op_e0d8_21_nf;
+extern cpuop_func_ce op_e0d8_21_ff;
+extern cpuop_func_ce op_e0e0_21_nf;
+extern cpuop_func_ce op_e0e0_21_ff;
+extern cpuop_func_ce op_e0e8_21_nf;
+extern cpuop_func_ce op_e0e8_21_ff;
+extern cpuop_func_ce op_e0f0_21_nf;
+extern cpuop_func_ce op_e0f0_21_ff;
+extern cpuop_func_ce op_e0f8_21_nf;
+extern cpuop_func_ce op_e0f8_21_ff;
+extern cpuop_func_ce op_e0f9_21_nf;
+extern cpuop_func_ce op_e0f9_21_ff;
+extern cpuop_func_ce op_e100_21_nf;
+extern cpuop_func_ce op_e100_21_ff;
+extern cpuop_func_ce op_e108_21_nf;
+extern cpuop_func_ce op_e108_21_ff;
+extern cpuop_func_ce op_e110_21_nf;
+extern cpuop_func_ce op_e110_21_ff;
+extern cpuop_func_ce op_e118_21_nf;
+extern cpuop_func_ce op_e118_21_ff;
+extern cpuop_func_ce op_e120_21_nf;
+extern cpuop_func_ce op_e120_21_ff;
+extern cpuop_func_ce op_e128_21_nf;
+extern cpuop_func_ce op_e128_21_ff;
+extern cpuop_func_ce op_e130_21_nf;
+extern cpuop_func_ce op_e130_21_ff;
+extern cpuop_func_ce op_e138_21_nf;
+extern cpuop_func_ce op_e138_21_ff;
+extern cpuop_func_ce op_e140_21_nf;
+extern cpuop_func_ce op_e140_21_ff;
+extern cpuop_func_ce op_e148_21_nf;
+extern cpuop_func_ce op_e148_21_ff;
+extern cpuop_func_ce op_e150_21_nf;
+extern cpuop_func_ce op_e150_21_ff;
+extern cpuop_func_ce op_e158_21_nf;
+extern cpuop_func_ce op_e158_21_ff;
+extern cpuop_func_ce op_e160_21_nf;
+extern cpuop_func_ce op_e160_21_ff;
+extern cpuop_func_ce op_e168_21_nf;
+extern cpuop_func_ce op_e168_21_ff;
+extern cpuop_func_ce op_e170_21_nf;
+extern cpuop_func_ce op_e170_21_ff;
+extern cpuop_func_ce op_e178_21_nf;
+extern cpuop_func_ce op_e178_21_ff;
+extern cpuop_func_ce op_e180_21_nf;
+extern cpuop_func_ce op_e180_21_ff;
+extern cpuop_func_ce op_e188_21_nf;
+extern cpuop_func_ce op_e188_21_ff;
+extern cpuop_func_ce op_e190_21_nf;
+extern cpuop_func_ce op_e190_21_ff;
+extern cpuop_func_ce op_e198_21_nf;
+extern cpuop_func_ce op_e198_21_ff;
+extern cpuop_func_ce op_e1a0_21_nf;
+extern cpuop_func_ce op_e1a0_21_ff;
+extern cpuop_func_ce op_e1a8_21_nf;
+extern cpuop_func_ce op_e1a8_21_ff;
+extern cpuop_func_ce op_e1b0_21_nf;
+extern cpuop_func_ce op_e1b0_21_ff;
+extern cpuop_func_ce op_e1b8_21_nf;
+extern cpuop_func_ce op_e1b8_21_ff;
+extern cpuop_func_ce op_e1d0_21_nf;
+extern cpuop_func_ce op_e1d0_21_ff;
+extern cpuop_func_ce op_e1d8_21_nf;
+extern cpuop_func_ce op_e1d8_21_ff;
+extern cpuop_func_ce op_e1e0_21_nf;
+extern cpuop_func_ce op_e1e0_21_ff;
+extern cpuop_func_ce op_e1e8_21_nf;
+extern cpuop_func_ce op_e1e8_21_ff;
+extern cpuop_func_ce op_e1f0_21_nf;
+extern cpuop_func_ce op_e1f0_21_ff;
+extern cpuop_func_ce op_e1f8_21_nf;
+extern cpuop_func_ce op_e1f8_21_ff;
+extern cpuop_func_ce op_e1f9_21_nf;
+extern cpuop_func_ce op_e1f9_21_ff;
+extern cpuop_func_ce op_e2d0_21_nf;
+extern cpuop_func_ce op_e2d0_21_ff;
+extern cpuop_func_ce op_e2d8_21_nf;
+extern cpuop_func_ce op_e2d8_21_ff;
+extern cpuop_func_ce op_e2e0_21_nf;
+extern cpuop_func_ce op_e2e0_21_ff;
+extern cpuop_func_ce op_e2e8_21_nf;
+extern cpuop_func_ce op_e2e8_21_ff;
+extern cpuop_func_ce op_e2f0_21_nf;
+extern cpuop_func_ce op_e2f0_21_ff;
+extern cpuop_func_ce op_e2f8_21_nf;
+extern cpuop_func_ce op_e2f8_21_ff;
+extern cpuop_func_ce op_e2f9_21_nf;
+extern cpuop_func_ce op_e2f9_21_ff;
+extern cpuop_func_ce op_e3d0_21_nf;
+extern cpuop_func_ce op_e3d0_21_ff;
+extern cpuop_func_ce op_e3d8_21_nf;
+extern cpuop_func_ce op_e3d8_21_ff;
+extern cpuop_func_ce op_e3e0_21_nf;
+extern cpuop_func_ce op_e3e0_21_ff;
+extern cpuop_func_ce op_e3e8_21_nf;
+extern cpuop_func_ce op_e3e8_21_ff;
+extern cpuop_func_ce op_e3f0_21_nf;
+extern cpuop_func_ce op_e3f0_21_ff;
+extern cpuop_func_ce op_e3f8_21_nf;
+extern cpuop_func_ce op_e3f8_21_ff;
+extern cpuop_func_ce op_e3f9_21_nf;
+extern cpuop_func_ce op_e3f9_21_ff;
+extern cpuop_func_ce op_e4d0_21_nf;
+extern cpuop_func_ce op_e4d0_21_ff;
+extern cpuop_func_ce op_e4d8_21_nf;
+extern cpuop_func_ce op_e4d8_21_ff;
+extern cpuop_func_ce op_e4e0_21_nf;
+extern cpuop_func_ce op_e4e0_21_ff;
+extern cpuop_func_ce op_e4e8_21_nf;
+extern cpuop_func_ce op_e4e8_21_ff;
+extern cpuop_func_ce op_e4f0_21_nf;
+extern cpuop_func_ce op_e4f0_21_ff;
+extern cpuop_func_ce op_e4f8_21_nf;
+extern cpuop_func_ce op_e4f8_21_ff;
+extern cpuop_func_ce op_e4f9_21_nf;
+extern cpuop_func_ce op_e4f9_21_ff;
+extern cpuop_func_ce op_e5d0_21_nf;
+extern cpuop_func_ce op_e5d0_21_ff;
+extern cpuop_func_ce op_e5d8_21_nf;
+extern cpuop_func_ce op_e5d8_21_ff;
+extern cpuop_func_ce op_e5e0_21_nf;
+extern cpuop_func_ce op_e5e0_21_ff;
+extern cpuop_func_ce op_e5e8_21_nf;
+extern cpuop_func_ce op_e5e8_21_ff;
+extern cpuop_func_ce op_e5f0_21_nf;
+extern cpuop_func_ce op_e5f0_21_ff;
+extern cpuop_func_ce op_e5f8_21_nf;
+extern cpuop_func_ce op_e5f8_21_ff;
+extern cpuop_func_ce op_e5f9_21_nf;
+extern cpuop_func_ce op_e5f9_21_ff;
+extern cpuop_func_ce op_e6d0_21_nf;
+extern cpuop_func_ce op_e6d0_21_ff;
+extern cpuop_func_ce op_e6d8_21_nf;
+extern cpuop_func_ce op_e6d8_21_ff;
+extern cpuop_func_ce op_e6e0_21_nf;
+extern cpuop_func_ce op_e6e0_21_ff;
+extern cpuop_func_ce op_e6e8_21_nf;
+extern cpuop_func_ce op_e6e8_21_ff;
+extern cpuop_func_ce op_e6f0_21_nf;
+extern cpuop_func_ce op_e6f0_21_ff;
+extern cpuop_func_ce op_e6f8_21_nf;
+extern cpuop_func_ce op_e6f8_21_ff;
+extern cpuop_func_ce op_e6f9_21_nf;
+extern cpuop_func_ce op_e6f9_21_ff;
+extern cpuop_func_ce op_e7d0_21_nf;
+extern cpuop_func_ce op_e7d0_21_ff;
+extern cpuop_func_ce op_e7d8_21_nf;
+extern cpuop_func_ce op_e7d8_21_ff;
+extern cpuop_func_ce op_e7e0_21_nf;
+extern cpuop_func_ce op_e7e0_21_ff;
+extern cpuop_func_ce op_e7e8_21_nf;
+extern cpuop_func_ce op_e7e8_21_ff;
+extern cpuop_func_ce op_e7f0_21_nf;
+extern cpuop_func_ce op_e7f0_21_ff;
+extern cpuop_func_ce op_e7f8_21_nf;
+extern cpuop_func_ce op_e7f8_21_ff;
+extern cpuop_func_ce op_e7f9_21_nf;
+extern cpuop_func_ce op_e7f9_21_ff;
+extern cpuop_func_ce op_e8c0_21_nf;
+extern cpuop_func_ce op_e8c0_21_ff;
+extern cpuop_func_ce op_e8d0_21_nf;
+extern cpuop_func_ce op_e8d0_21_ff;
+extern cpuop_func_ce op_e8e8_21_nf;
+extern cpuop_func_ce op_e8e8_21_ff;
+extern cpuop_func_ce op_e8f0_21_nf;
+extern cpuop_func_ce op_e8f0_21_ff;
+extern cpuop_func_ce op_e8f8_21_nf;
+extern cpuop_func_ce op_e8f8_21_ff;
+extern cpuop_func_ce op_e8f9_21_nf;
+extern cpuop_func_ce op_e8f9_21_ff;
+extern cpuop_func_ce op_e8fa_21_nf;
+extern cpuop_func_ce op_e8fa_21_ff;
+extern cpuop_func_ce op_e8fb_21_nf;
+extern cpuop_func_ce op_e8fb_21_ff;
+extern cpuop_func_ce op_e9c0_21_nf;
+extern cpuop_func_ce op_e9c0_21_ff;
+extern cpuop_func_ce op_e9d0_21_nf;
+extern cpuop_func_ce op_e9d0_21_ff;
+extern cpuop_func_ce op_e9e8_21_nf;
+extern cpuop_func_ce op_e9e8_21_ff;
+extern cpuop_func_ce op_e9f0_21_nf;
+extern cpuop_func_ce op_e9f0_21_ff;
+extern cpuop_func_ce op_e9f8_21_nf;
+extern cpuop_func_ce op_e9f8_21_ff;
+extern cpuop_func_ce op_e9f9_21_nf;
+extern cpuop_func_ce op_e9f9_21_ff;
+extern cpuop_func_ce op_e9fa_21_nf;
+extern cpuop_func_ce op_e9fa_21_ff;
+extern cpuop_func_ce op_e9fb_21_nf;
+extern cpuop_func_ce op_e9fb_21_ff;
+extern cpuop_func_ce op_eac0_21_nf;
+extern cpuop_func_ce op_eac0_21_ff;
+extern cpuop_func_ce op_ead0_21_nf;
+extern cpuop_func_ce op_ead0_21_ff;
+extern cpuop_func_ce op_eae8_21_nf;
+extern cpuop_func_ce op_eae8_21_ff;
+extern cpuop_func_ce op_eaf0_21_nf;
+extern cpuop_func_ce op_eaf0_21_ff;
+extern cpuop_func_ce op_eaf8_21_nf;
+extern cpuop_func_ce op_eaf8_21_ff;
+extern cpuop_func_ce op_eaf9_21_nf;
+extern cpuop_func_ce op_eaf9_21_ff;
+extern cpuop_func_ce op_ebc0_21_nf;
+extern cpuop_func_ce op_ebc0_21_ff;
+extern cpuop_func_ce op_ebd0_21_nf;
+extern cpuop_func_ce op_ebd0_21_ff;
+extern cpuop_func_ce op_ebe8_21_nf;
+extern cpuop_func_ce op_ebe8_21_ff;
+extern cpuop_func_ce op_ebf0_21_nf;
+extern cpuop_func_ce op_ebf0_21_ff;
+extern cpuop_func_ce op_ebf8_21_nf;
+extern cpuop_func_ce op_ebf8_21_ff;
+extern cpuop_func_ce op_ebf9_21_nf;
+extern cpuop_func_ce op_ebf9_21_ff;
+extern cpuop_func_ce op_ebfa_21_nf;
+extern cpuop_func_ce op_ebfa_21_ff;
+extern cpuop_func_ce op_ebfb_21_nf;
+extern cpuop_func_ce op_ebfb_21_ff;
+extern cpuop_func_ce op_ecc0_21_nf;
+extern cpuop_func_ce op_ecc0_21_ff;
+extern cpuop_func_ce op_ecd0_21_nf;
+extern cpuop_func_ce op_ecd0_21_ff;
+extern cpuop_func_ce op_ece8_21_nf;
+extern cpuop_func_ce op_ece8_21_ff;
+extern cpuop_func_ce op_ecf0_21_nf;
+extern cpuop_func_ce op_ecf0_21_ff;
+extern cpuop_func_ce op_ecf8_21_nf;
+extern cpuop_func_ce op_ecf8_21_ff;
+extern cpuop_func_ce op_ecf9_21_nf;
+extern cpuop_func_ce op_ecf9_21_ff;
+extern cpuop_func_ce op_edc0_21_nf;
+extern cpuop_func_ce op_edc0_21_ff;
+extern cpuop_func_ce op_edd0_21_nf;
+extern cpuop_func_ce op_edd0_21_ff;
+extern cpuop_func_ce op_ede8_21_nf;
+extern cpuop_func_ce op_ede8_21_ff;
+extern cpuop_func_ce op_edf0_21_nf;
+extern cpuop_func_ce op_edf0_21_ff;
+extern cpuop_func_ce op_edf8_21_nf;
+extern cpuop_func_ce op_edf8_21_ff;
+extern cpuop_func_ce op_edf9_21_nf;
+extern cpuop_func_ce op_edf9_21_ff;
+extern cpuop_func_ce op_edfa_21_nf;
+extern cpuop_func_ce op_edfa_21_ff;
+extern cpuop_func_ce op_edfb_21_nf;
+extern cpuop_func_ce op_edfb_21_ff;
+extern cpuop_func_ce op_eec0_21_nf;
+extern cpuop_func_ce op_eec0_21_ff;
+extern cpuop_func_ce op_eed0_21_nf;
+extern cpuop_func_ce op_eed0_21_ff;
+extern cpuop_func_ce op_eee8_21_nf;
+extern cpuop_func_ce op_eee8_21_ff;
+extern cpuop_func_ce op_eef0_21_nf;
+extern cpuop_func_ce op_eef0_21_ff;
+extern cpuop_func_ce op_eef8_21_nf;
+extern cpuop_func_ce op_eef8_21_ff;
+extern cpuop_func_ce op_eef9_21_nf;
+extern cpuop_func_ce op_eef9_21_ff;
+extern cpuop_func_ce op_efc0_21_nf;
+extern cpuop_func_ce op_efc0_21_ff;
+extern cpuop_func_ce op_efd0_21_nf;
+extern cpuop_func_ce op_efd0_21_ff;
+extern cpuop_func_ce op_efe8_21_nf;
+extern cpuop_func_ce op_efe8_21_ff;
+extern cpuop_func_ce op_eff0_21_nf;
+extern cpuop_func_ce op_eff0_21_ff;
+extern cpuop_func_ce op_eff8_21_nf;
+extern cpuop_func_ce op_eff8_21_ff;
+extern cpuop_func_ce op_eff9_21_nf;
+extern cpuop_func_ce op_eff9_21_ff;
+extern cpuop_func_ce op_f200_21_nf;
+extern cpuop_func_ce op_f200_21_ff;
+extern cpuop_func_ce op_f208_21_nf;
+extern cpuop_func_ce op_f208_21_ff;
+extern cpuop_func_ce op_f210_21_nf;
+extern cpuop_func_ce op_f210_21_ff;
+extern cpuop_func_ce op_f218_21_nf;
+extern cpuop_func_ce op_f218_21_ff;
+extern cpuop_func_ce op_f220_21_nf;
+extern cpuop_func_ce op_f220_21_ff;
+extern cpuop_func_ce op_f228_21_nf;
+extern cpuop_func_ce op_f228_21_ff;
+extern cpuop_func_ce op_f230_21_nf;
+extern cpuop_func_ce op_f230_21_ff;
+extern cpuop_func_ce op_f238_21_nf;
+extern cpuop_func_ce op_f238_21_ff;
+extern cpuop_func_ce op_f239_21_nf;
+extern cpuop_func_ce op_f239_21_ff;
+extern cpuop_func_ce op_f23a_21_nf;
+extern cpuop_func_ce op_f23a_21_ff;
+extern cpuop_func_ce op_f23b_21_nf;
+extern cpuop_func_ce op_f23b_21_ff;
+extern cpuop_func_ce op_f23c_21_nf;
+extern cpuop_func_ce op_f23c_21_ff;
+extern cpuop_func_ce op_f240_21_nf;
+extern cpuop_func_ce op_f240_21_ff;
+extern cpuop_func_ce op_f248_21_nf;
+extern cpuop_func_ce op_f248_21_ff;
+extern cpuop_func_ce op_f250_21_nf;
+extern cpuop_func_ce op_f250_21_ff;
+extern cpuop_func_ce op_f258_21_nf;
+extern cpuop_func_ce op_f258_21_ff;
+extern cpuop_func_ce op_f260_21_nf;
+extern cpuop_func_ce op_f260_21_ff;
+extern cpuop_func_ce op_f268_21_nf;
+extern cpuop_func_ce op_f268_21_ff;
+extern cpuop_func_ce op_f270_21_nf;
+extern cpuop_func_ce op_f270_21_ff;
+extern cpuop_func_ce op_f278_21_nf;
+extern cpuop_func_ce op_f278_21_ff;
+extern cpuop_func_ce op_f279_21_nf;
+extern cpuop_func_ce op_f279_21_ff;
+extern cpuop_func_ce op_f27a_21_nf;
+extern cpuop_func_ce op_f27a_21_ff;
+extern cpuop_func_ce op_f27b_21_nf;
+extern cpuop_func_ce op_f27b_21_ff;
+extern cpuop_func_ce op_f27c_21_nf;
+extern cpuop_func_ce op_f27c_21_ff;
+extern cpuop_func_ce op_f280_21_nf;
+extern cpuop_func_ce op_f280_21_ff;
+extern cpuop_func_ce op_f2c0_21_nf;
+extern cpuop_func_ce op_f2c0_21_ff;
+extern cpuop_func_ce op_f310_21_nf;
+extern cpuop_func_ce op_f310_21_ff;
+extern cpuop_func_ce op_f320_21_nf;
+extern cpuop_func_ce op_f320_21_ff;
+extern cpuop_func_ce op_f328_21_nf;
+extern cpuop_func_ce op_f328_21_ff;
+extern cpuop_func_ce op_f330_21_nf;
+extern cpuop_func_ce op_f330_21_ff;
+extern cpuop_func_ce op_f338_21_nf;
+extern cpuop_func_ce op_f338_21_ff;
+extern cpuop_func_ce op_f339_21_nf;
+extern cpuop_func_ce op_f339_21_ff;
+extern cpuop_func_ce op_f350_21_nf;
+extern cpuop_func_ce op_f350_21_ff;
+extern cpuop_func_ce op_f358_21_nf;
+extern cpuop_func_ce op_f358_21_ff;
+extern cpuop_func_ce op_f368_21_nf;
+extern cpuop_func_ce op_f368_21_ff;
+extern cpuop_func_ce op_f370_21_nf;
+extern cpuop_func_ce op_f370_21_ff;
+extern cpuop_func_ce op_f378_21_nf;
+extern cpuop_func_ce op_f378_21_ff;
+extern cpuop_func_ce op_f379_21_nf;
+extern cpuop_func_ce op_f379_21_ff;
+extern cpuop_func_ce op_f37a_21_nf;
+extern cpuop_func_ce op_f37a_21_ff;
+extern cpuop_func_ce op_f37b_21_nf;
+extern cpuop_func_ce op_f37b_21_ff;
+extern cpuop_func op_0000_22_nf;
+extern cpuop_func op_0000_22_ff;
+extern cpuop_func op_0010_22_nf;
+extern cpuop_func op_0010_22_ff;
+extern cpuop_func op_0018_22_nf;
+extern cpuop_func op_0018_22_ff;
+extern cpuop_func op_0020_22_nf;
+extern cpuop_func op_0020_22_ff;
+extern cpuop_func op_0028_22_nf;
+extern cpuop_func op_0028_22_ff;
+extern cpuop_func op_0030_22_nf;
+extern cpuop_func op_0030_22_ff;
+extern cpuop_func op_0038_22_nf;
+extern cpuop_func op_0038_22_ff;
+extern cpuop_func op_0039_22_nf;
+extern cpuop_func op_0039_22_ff;
+extern cpuop_func op_003c_22_nf;
+extern cpuop_func op_003c_22_ff;
+extern cpuop_func op_0040_22_nf;
+extern cpuop_func op_0040_22_ff;
+extern cpuop_func op_0050_22_nf;
+extern cpuop_func op_0050_22_ff;
+extern cpuop_func op_0058_22_nf;
+extern cpuop_func op_0058_22_ff;
+extern cpuop_func op_0060_22_nf;
+extern cpuop_func op_0060_22_ff;
+extern cpuop_func op_0068_22_nf;
+extern cpuop_func op_0068_22_ff;
+extern cpuop_func op_0070_22_nf;
+extern cpuop_func op_0070_22_ff;
+extern cpuop_func op_0078_22_nf;
+extern cpuop_func op_0078_22_ff;
+extern cpuop_func op_0079_22_nf;
+extern cpuop_func op_0079_22_ff;
+extern cpuop_func op_007c_22_nf;
+extern cpuop_func op_007c_22_ff;
+extern cpuop_func op_0080_22_nf;
+extern cpuop_func op_0080_22_ff;
+extern cpuop_func op_0090_22_nf;
+extern cpuop_func op_0090_22_ff;
+extern cpuop_func op_0098_22_nf;
+extern cpuop_func op_0098_22_ff;
+extern cpuop_func op_00a0_22_nf;
+extern cpuop_func op_00a0_22_ff;
+extern cpuop_func op_00a8_22_nf;
+extern cpuop_func op_00a8_22_ff;
+extern cpuop_func op_00b0_22_nf;
+extern cpuop_func op_00b0_22_ff;
+extern cpuop_func op_00b8_22_nf;
+extern cpuop_func op_00b8_22_ff;
+extern cpuop_func op_00b9_22_nf;
+extern cpuop_func op_00b9_22_ff;
+extern cpuop_func op_00d0_22_nf;
+extern cpuop_func op_00d0_22_ff;
+extern cpuop_func op_00e8_22_nf;
+extern cpuop_func op_00e8_22_ff;
+extern cpuop_func op_00f0_22_nf;
+extern cpuop_func op_00f0_22_ff;
+extern cpuop_func op_00f8_22_nf;
+extern cpuop_func op_00f8_22_ff;
+extern cpuop_func op_00f9_22_nf;
+extern cpuop_func op_00f9_22_ff;
+extern cpuop_func op_00fa_22_nf;
+extern cpuop_func op_00fa_22_ff;
+extern cpuop_func op_00fb_22_nf;
+extern cpuop_func op_00fb_22_ff;
+extern cpuop_func op_0100_22_nf;
+extern cpuop_func op_0100_22_ff;
+extern cpuop_func op_0108_22_nf;
+extern cpuop_func op_0108_22_ff;
+extern cpuop_func op_0110_22_nf;
+extern cpuop_func op_0110_22_ff;
+extern cpuop_func op_0118_22_nf;
+extern cpuop_func op_0118_22_ff;
+extern cpuop_func op_0120_22_nf;
+extern cpuop_func op_0120_22_ff;
+extern cpuop_func op_0128_22_nf;
+extern cpuop_func op_0128_22_ff;
+extern cpuop_func op_0130_22_nf;
+extern cpuop_func op_0130_22_ff;
+extern cpuop_func op_0138_22_nf;
+extern cpuop_func op_0138_22_ff;
+extern cpuop_func op_0139_22_nf;
+extern cpuop_func op_0139_22_ff;
+extern cpuop_func op_013a_22_nf;
+extern cpuop_func op_013a_22_ff;
+extern cpuop_func op_013b_22_nf;
+extern cpuop_func op_013b_22_ff;
+extern cpuop_func op_013c_22_nf;
+extern cpuop_func op_013c_22_ff;
+extern cpuop_func op_0140_22_nf;
+extern cpuop_func op_0140_22_ff;
+extern cpuop_func op_0148_22_nf;
+extern cpuop_func op_0148_22_ff;
+extern cpuop_func op_0150_22_nf;
+extern cpuop_func op_0150_22_ff;
+extern cpuop_func op_0158_22_nf;
+extern cpuop_func op_0158_22_ff;
+extern cpuop_func op_0160_22_nf;
+extern cpuop_func op_0160_22_ff;
+extern cpuop_func op_0168_22_nf;
+extern cpuop_func op_0168_22_ff;
+extern cpuop_func op_0170_22_nf;
+extern cpuop_func op_0170_22_ff;
+extern cpuop_func op_0178_22_nf;
+extern cpuop_func op_0178_22_ff;
+extern cpuop_func op_0179_22_nf;
+extern cpuop_func op_0179_22_ff;
+extern cpuop_func op_0180_22_nf;
+extern cpuop_func op_0180_22_ff;
+extern cpuop_func op_0188_22_nf;
+extern cpuop_func op_0188_22_ff;
+extern cpuop_func op_0190_22_nf;
+extern cpuop_func op_0190_22_ff;
+extern cpuop_func op_0198_22_nf;
+extern cpuop_func op_0198_22_ff;
+extern cpuop_func op_01a0_22_nf;
+extern cpuop_func op_01a0_22_ff;
+extern cpuop_func op_01a8_22_nf;
+extern cpuop_func op_01a8_22_ff;
+extern cpuop_func op_01b0_22_nf;
+extern cpuop_func op_01b0_22_ff;
+extern cpuop_func op_01b8_22_nf;
+extern cpuop_func op_01b8_22_ff;
+extern cpuop_func op_01b9_22_nf;
+extern cpuop_func op_01b9_22_ff;
+extern cpuop_func op_01c0_22_nf;
+extern cpuop_func op_01c0_22_ff;
+extern cpuop_func op_01c8_22_nf;
+extern cpuop_func op_01c8_22_ff;
+extern cpuop_func op_01d0_22_nf;
+extern cpuop_func op_01d0_22_ff;
+extern cpuop_func op_01d8_22_nf;
+extern cpuop_func op_01d8_22_ff;
+extern cpuop_func op_01e0_22_nf;
+extern cpuop_func op_01e0_22_ff;
+extern cpuop_func op_01e8_22_nf;
+extern cpuop_func op_01e8_22_ff;
+extern cpuop_func op_01f0_22_nf;
+extern cpuop_func op_01f0_22_ff;
+extern cpuop_func op_01f8_22_nf;
+extern cpuop_func op_01f8_22_ff;
+extern cpuop_func op_01f9_22_nf;
+extern cpuop_func op_01f9_22_ff;
+extern cpuop_func op_0200_22_nf;
+extern cpuop_func op_0200_22_ff;
+extern cpuop_func op_0210_22_nf;
+extern cpuop_func op_0210_22_ff;
+extern cpuop_func op_0218_22_nf;
+extern cpuop_func op_0218_22_ff;
+extern cpuop_func op_0220_22_nf;
+extern cpuop_func op_0220_22_ff;
+extern cpuop_func op_0228_22_nf;
+extern cpuop_func op_0228_22_ff;
+extern cpuop_func op_0230_22_nf;
+extern cpuop_func op_0230_22_ff;
+extern cpuop_func op_0238_22_nf;
+extern cpuop_func op_0238_22_ff;
+extern cpuop_func op_0239_22_nf;
+extern cpuop_func op_0239_22_ff;
+extern cpuop_func op_023c_22_nf;
+extern cpuop_func op_023c_22_ff;
+extern cpuop_func op_0240_22_nf;
+extern cpuop_func op_0240_22_ff;
+extern cpuop_func op_0250_22_nf;
+extern cpuop_func op_0250_22_ff;
+extern cpuop_func op_0258_22_nf;
+extern cpuop_func op_0258_22_ff;
+extern cpuop_func op_0260_22_nf;
+extern cpuop_func op_0260_22_ff;
+extern cpuop_func op_0268_22_nf;
+extern cpuop_func op_0268_22_ff;
+extern cpuop_func op_0270_22_nf;
+extern cpuop_func op_0270_22_ff;
+extern cpuop_func op_0278_22_nf;
+extern cpuop_func op_0278_22_ff;
+extern cpuop_func op_0279_22_nf;
+extern cpuop_func op_0279_22_ff;
+extern cpuop_func op_027c_22_nf;
+extern cpuop_func op_027c_22_ff;
+extern cpuop_func op_0280_22_nf;
+extern cpuop_func op_0280_22_ff;
+extern cpuop_func op_0290_22_nf;
+extern cpuop_func op_0290_22_ff;
+extern cpuop_func op_0298_22_nf;
+extern cpuop_func op_0298_22_ff;
+extern cpuop_func op_02a0_22_nf;
+extern cpuop_func op_02a0_22_ff;
+extern cpuop_func op_02a8_22_nf;
+extern cpuop_func op_02a8_22_ff;
+extern cpuop_func op_02b0_22_nf;
+extern cpuop_func op_02b0_22_ff;
+extern cpuop_func op_02b8_22_nf;
+extern cpuop_func op_02b8_22_ff;
+extern cpuop_func op_02b9_22_nf;
+extern cpuop_func op_02b9_22_ff;
+extern cpuop_func op_02d0_22_nf;
+extern cpuop_func op_02d0_22_ff;
+extern cpuop_func op_02e8_22_nf;
+extern cpuop_func op_02e8_22_ff;
+extern cpuop_func op_02f0_22_nf;
+extern cpuop_func op_02f0_22_ff;
+extern cpuop_func op_02f8_22_nf;
+extern cpuop_func op_02f8_22_ff;
+extern cpuop_func op_02f9_22_nf;
+extern cpuop_func op_02f9_22_ff;
+extern cpuop_func op_02fa_22_nf;
+extern cpuop_func op_02fa_22_ff;
+extern cpuop_func op_02fb_22_nf;
+extern cpuop_func op_02fb_22_ff;
+extern cpuop_func op_0400_22_nf;
+extern cpuop_func op_0400_22_ff;
+extern cpuop_func op_0410_22_nf;
+extern cpuop_func op_0410_22_ff;
+extern cpuop_func op_0418_22_nf;
+extern cpuop_func op_0418_22_ff;
+extern cpuop_func op_0420_22_nf;
+extern cpuop_func op_0420_22_ff;
+extern cpuop_func op_0428_22_nf;
+extern cpuop_func op_0428_22_ff;
+extern cpuop_func op_0430_22_nf;
+extern cpuop_func op_0430_22_ff;
+extern cpuop_func op_0438_22_nf;
+extern cpuop_func op_0438_22_ff;
+extern cpuop_func op_0439_22_nf;
+extern cpuop_func op_0439_22_ff;
+extern cpuop_func op_0440_22_nf;
+extern cpuop_func op_0440_22_ff;
+extern cpuop_func op_0450_22_nf;
+extern cpuop_func op_0450_22_ff;
+extern cpuop_func op_0458_22_nf;
+extern cpuop_func op_0458_22_ff;
+extern cpuop_func op_0460_22_nf;
+extern cpuop_func op_0460_22_ff;
+extern cpuop_func op_0468_22_nf;
+extern cpuop_func op_0468_22_ff;
+extern cpuop_func op_0470_22_nf;
+extern cpuop_func op_0470_22_ff;
+extern cpuop_func op_0478_22_nf;
+extern cpuop_func op_0478_22_ff;
+extern cpuop_func op_0479_22_nf;
+extern cpuop_func op_0479_22_ff;
+extern cpuop_func op_0480_22_nf;
+extern cpuop_func op_0480_22_ff;
+extern cpuop_func op_0490_22_nf;
+extern cpuop_func op_0490_22_ff;
+extern cpuop_func op_0498_22_nf;
+extern cpuop_func op_0498_22_ff;
+extern cpuop_func op_04a0_22_nf;
+extern cpuop_func op_04a0_22_ff;
+extern cpuop_func op_04a8_22_nf;
+extern cpuop_func op_04a8_22_ff;
+extern cpuop_func op_04b0_22_nf;
+extern cpuop_func op_04b0_22_ff;
+extern cpuop_func op_04b8_22_nf;
+extern cpuop_func op_04b8_22_ff;
+extern cpuop_func op_04b9_22_nf;
+extern cpuop_func op_04b9_22_ff;
+extern cpuop_func op_04d0_22_nf;
+extern cpuop_func op_04d0_22_ff;
+extern cpuop_func op_04e8_22_nf;
+extern cpuop_func op_04e8_22_ff;
+extern cpuop_func op_04f0_22_nf;
+extern cpuop_func op_04f0_22_ff;
+extern cpuop_func op_04f8_22_nf;
+extern cpuop_func op_04f8_22_ff;
+extern cpuop_func op_04f9_22_nf;
+extern cpuop_func op_04f9_22_ff;
+extern cpuop_func op_04fa_22_nf;
+extern cpuop_func op_04fa_22_ff;
+extern cpuop_func op_04fb_22_nf;
+extern cpuop_func op_04fb_22_ff;
+extern cpuop_func op_0600_22_nf;
+extern cpuop_func op_0600_22_ff;
+extern cpuop_func op_0610_22_nf;
+extern cpuop_func op_0610_22_ff;
+extern cpuop_func op_0618_22_nf;
+extern cpuop_func op_0618_22_ff;
+extern cpuop_func op_0620_22_nf;
+extern cpuop_func op_0620_22_ff;
+extern cpuop_func op_0628_22_nf;
+extern cpuop_func op_0628_22_ff;
+extern cpuop_func op_0630_22_nf;
+extern cpuop_func op_0630_22_ff;
+extern cpuop_func op_0638_22_nf;
+extern cpuop_func op_0638_22_ff;
+extern cpuop_func op_0639_22_nf;
+extern cpuop_func op_0639_22_ff;
+extern cpuop_func op_0640_22_nf;
+extern cpuop_func op_0640_22_ff;
+extern cpuop_func op_0650_22_nf;
+extern cpuop_func op_0650_22_ff;
+extern cpuop_func op_0658_22_nf;
+extern cpuop_func op_0658_22_ff;
+extern cpuop_func op_0660_22_nf;
+extern cpuop_func op_0660_22_ff;
+extern cpuop_func op_0668_22_nf;
+extern cpuop_func op_0668_22_ff;
+extern cpuop_func op_0670_22_nf;
+extern cpuop_func op_0670_22_ff;
+extern cpuop_func op_0678_22_nf;
+extern cpuop_func op_0678_22_ff;
+extern cpuop_func op_0679_22_nf;
+extern cpuop_func op_0679_22_ff;
+extern cpuop_func op_0680_22_nf;
+extern cpuop_func op_0680_22_ff;
+extern cpuop_func op_0690_22_nf;
+extern cpuop_func op_0690_22_ff;
+extern cpuop_func op_0698_22_nf;
+extern cpuop_func op_0698_22_ff;
+extern cpuop_func op_06a0_22_nf;
+extern cpuop_func op_06a0_22_ff;
+extern cpuop_func op_06a8_22_nf;
+extern cpuop_func op_06a8_22_ff;
+extern cpuop_func op_06b0_22_nf;
+extern cpuop_func op_06b0_22_ff;
+extern cpuop_func op_06b8_22_nf;
+extern cpuop_func op_06b8_22_ff;
+extern cpuop_func op_06b9_22_nf;
+extern cpuop_func op_06b9_22_ff;
+extern cpuop_func op_06c0_22_nf;
+extern cpuop_func op_06c0_22_ff;
+extern cpuop_func op_06c8_22_nf;
+extern cpuop_func op_06c8_22_ff;
+extern cpuop_func op_06d0_22_nf;
+extern cpuop_func op_06d0_22_ff;
+extern cpuop_func op_06e8_22_nf;
+extern cpuop_func op_06e8_22_ff;
+extern cpuop_func op_06f0_22_nf;
+extern cpuop_func op_06f0_22_ff;
+extern cpuop_func op_06f8_22_nf;
+extern cpuop_func op_06f8_22_ff;
+extern cpuop_func op_06f9_22_nf;
+extern cpuop_func op_06f9_22_ff;
+extern cpuop_func op_06fa_22_nf;
+extern cpuop_func op_06fa_22_ff;
+extern cpuop_func op_06fb_22_nf;
+extern cpuop_func op_06fb_22_ff;
+extern cpuop_func op_0800_22_nf;
+extern cpuop_func op_0800_22_ff;
+extern cpuop_func op_0810_22_nf;
+extern cpuop_func op_0810_22_ff;
+extern cpuop_func op_0818_22_nf;
+extern cpuop_func op_0818_22_ff;
+extern cpuop_func op_0820_22_nf;
+extern cpuop_func op_0820_22_ff;
+extern cpuop_func op_0828_22_nf;
+extern cpuop_func op_0828_22_ff;
+extern cpuop_func op_0830_22_nf;
+extern cpuop_func op_0830_22_ff;
+extern cpuop_func op_0838_22_nf;
+extern cpuop_func op_0838_22_ff;
+extern cpuop_func op_0839_22_nf;
+extern cpuop_func op_0839_22_ff;
+extern cpuop_func op_083a_22_nf;
+extern cpuop_func op_083a_22_ff;
+extern cpuop_func op_083b_22_nf;
+extern cpuop_func op_083b_22_ff;
+extern cpuop_func op_0840_22_nf;
+extern cpuop_func op_0840_22_ff;
+extern cpuop_func op_0850_22_nf;
+extern cpuop_func op_0850_22_ff;
+extern cpuop_func op_0858_22_nf;
+extern cpuop_func op_0858_22_ff;
+extern cpuop_func op_0860_22_nf;
+extern cpuop_func op_0860_22_ff;
+extern cpuop_func op_0868_22_nf;
+extern cpuop_func op_0868_22_ff;
+extern cpuop_func op_0870_22_nf;
+extern cpuop_func op_0870_22_ff;
+extern cpuop_func op_0878_22_nf;
+extern cpuop_func op_0878_22_ff;
+extern cpuop_func op_0879_22_nf;
+extern cpuop_func op_0879_22_ff;
+extern cpuop_func op_0880_22_nf;
+extern cpuop_func op_0880_22_ff;
+extern cpuop_func op_0890_22_nf;
+extern cpuop_func op_0890_22_ff;
+extern cpuop_func op_0898_22_nf;
+extern cpuop_func op_0898_22_ff;
+extern cpuop_func op_08a0_22_nf;
+extern cpuop_func op_08a0_22_ff;
+extern cpuop_func op_08a8_22_nf;
+extern cpuop_func op_08a8_22_ff;
+extern cpuop_func op_08b0_22_nf;
+extern cpuop_func op_08b0_22_ff;
+extern cpuop_func op_08b8_22_nf;
+extern cpuop_func op_08b8_22_ff;
+extern cpuop_func op_08b9_22_nf;
+extern cpuop_func op_08b9_22_ff;
+extern cpuop_func op_08c0_22_nf;
+extern cpuop_func op_08c0_22_ff;
+extern cpuop_func op_08d0_22_nf;
+extern cpuop_func op_08d0_22_ff;
+extern cpuop_func op_08d8_22_nf;
+extern cpuop_func op_08d8_22_ff;
+extern cpuop_func op_08e0_22_nf;
+extern cpuop_func op_08e0_22_ff;
+extern cpuop_func op_08e8_22_nf;
+extern cpuop_func op_08e8_22_ff;
+extern cpuop_func op_08f0_22_nf;
+extern cpuop_func op_08f0_22_ff;
+extern cpuop_func op_08f8_22_nf;
+extern cpuop_func op_08f8_22_ff;
+extern cpuop_func op_08f9_22_nf;
+extern cpuop_func op_08f9_22_ff;
+extern cpuop_func op_0a00_22_nf;
+extern cpuop_func op_0a00_22_ff;
+extern cpuop_func op_0a10_22_nf;
+extern cpuop_func op_0a10_22_ff;
+extern cpuop_func op_0a18_22_nf;
+extern cpuop_func op_0a18_22_ff;
+extern cpuop_func op_0a20_22_nf;
+extern cpuop_func op_0a20_22_ff;
+extern cpuop_func op_0a28_22_nf;
+extern cpuop_func op_0a28_22_ff;
+extern cpuop_func op_0a30_22_nf;
+extern cpuop_func op_0a30_22_ff;
+extern cpuop_func op_0a38_22_nf;
+extern cpuop_func op_0a38_22_ff;
+extern cpuop_func op_0a39_22_nf;
+extern cpuop_func op_0a39_22_ff;
+extern cpuop_func op_0a3c_22_nf;
+extern cpuop_func op_0a3c_22_ff;
+extern cpuop_func op_0a40_22_nf;
+extern cpuop_func op_0a40_22_ff;
+extern cpuop_func op_0a50_22_nf;
+extern cpuop_func op_0a50_22_ff;
+extern cpuop_func op_0a58_22_nf;
+extern cpuop_func op_0a58_22_ff;
+extern cpuop_func op_0a60_22_nf;
+extern cpuop_func op_0a60_22_ff;
+extern cpuop_func op_0a68_22_nf;
+extern cpuop_func op_0a68_22_ff;
+extern cpuop_func op_0a70_22_nf;
+extern cpuop_func op_0a70_22_ff;
+extern cpuop_func op_0a78_22_nf;
+extern cpuop_func op_0a78_22_ff;
+extern cpuop_func op_0a79_22_nf;
+extern cpuop_func op_0a79_22_ff;
+extern cpuop_func op_0a7c_22_nf;
+extern cpuop_func op_0a7c_22_ff;
+extern cpuop_func op_0a80_22_nf;
+extern cpuop_func op_0a80_22_ff;
+extern cpuop_func op_0a90_22_nf;
+extern cpuop_func op_0a90_22_ff;
+extern cpuop_func op_0a98_22_nf;
+extern cpuop_func op_0a98_22_ff;
+extern cpuop_func op_0aa0_22_nf;
+extern cpuop_func op_0aa0_22_ff;
+extern cpuop_func op_0aa8_22_nf;
+extern cpuop_func op_0aa8_22_ff;
+extern cpuop_func op_0ab0_22_nf;
+extern cpuop_func op_0ab0_22_ff;
+extern cpuop_func op_0ab8_22_nf;
+extern cpuop_func op_0ab8_22_ff;
+extern cpuop_func op_0ab9_22_nf;
+extern cpuop_func op_0ab9_22_ff;
+extern cpuop_func op_0ad0_22_nf;
+extern cpuop_func op_0ad0_22_ff;
+extern cpuop_func op_0ad8_22_nf;
+extern cpuop_func op_0ad8_22_ff;
+extern cpuop_func op_0ae0_22_nf;
+extern cpuop_func op_0ae0_22_ff;
+extern cpuop_func op_0ae8_22_nf;
+extern cpuop_func op_0ae8_22_ff;
+extern cpuop_func op_0af0_22_nf;
+extern cpuop_func op_0af0_22_ff;
+extern cpuop_func op_0af8_22_nf;
+extern cpuop_func op_0af8_22_ff;
+extern cpuop_func op_0af9_22_nf;
+extern cpuop_func op_0af9_22_ff;
+extern cpuop_func op_0c00_22_nf;
+extern cpuop_func op_0c00_22_ff;
+extern cpuop_func op_0c10_22_nf;
+extern cpuop_func op_0c10_22_ff;
+extern cpuop_func op_0c18_22_nf;
+extern cpuop_func op_0c18_22_ff;
+extern cpuop_func op_0c20_22_nf;
+extern cpuop_func op_0c20_22_ff;
+extern cpuop_func op_0c28_22_nf;
+extern cpuop_func op_0c28_22_ff;
+extern cpuop_func op_0c30_22_nf;
+extern cpuop_func op_0c30_22_ff;
+extern cpuop_func op_0c38_22_nf;
+extern cpuop_func op_0c38_22_ff;
+extern cpuop_func op_0c39_22_nf;
+extern cpuop_func op_0c39_22_ff;
+extern cpuop_func op_0c3a_22_nf;
+extern cpuop_func op_0c3a_22_ff;
+extern cpuop_func op_0c3b_22_nf;
+extern cpuop_func op_0c3b_22_ff;
+extern cpuop_func op_0c40_22_nf;
+extern cpuop_func op_0c40_22_ff;
+extern cpuop_func op_0c50_22_nf;
+extern cpuop_func op_0c50_22_ff;
+extern cpuop_func op_0c58_22_nf;
+extern cpuop_func op_0c58_22_ff;
+extern cpuop_func op_0c60_22_nf;
+extern cpuop_func op_0c60_22_ff;
+extern cpuop_func op_0c68_22_nf;
+extern cpuop_func op_0c68_22_ff;
+extern cpuop_func op_0c70_22_nf;
+extern cpuop_func op_0c70_22_ff;
+extern cpuop_func op_0c78_22_nf;
+extern cpuop_func op_0c78_22_ff;
+extern cpuop_func op_0c79_22_nf;
+extern cpuop_func op_0c79_22_ff;
+extern cpuop_func op_0c7a_22_nf;
+extern cpuop_func op_0c7a_22_ff;
+extern cpuop_func op_0c7b_22_nf;
+extern cpuop_func op_0c7b_22_ff;
+extern cpuop_func op_0c80_22_nf;
+extern cpuop_func op_0c80_22_ff;
+extern cpuop_func op_0c90_22_nf;
+extern cpuop_func op_0c90_22_ff;
+extern cpuop_func op_0c98_22_nf;
+extern cpuop_func op_0c98_22_ff;
+extern cpuop_func op_0ca0_22_nf;
+extern cpuop_func op_0ca0_22_ff;
+extern cpuop_func op_0ca8_22_nf;
+extern cpuop_func op_0ca8_22_ff;
+extern cpuop_func op_0cb0_22_nf;
+extern cpuop_func op_0cb0_22_ff;
+extern cpuop_func op_0cb8_22_nf;
+extern cpuop_func op_0cb8_22_ff;
+extern cpuop_func op_0cb9_22_nf;
+extern cpuop_func op_0cb9_22_ff;
+extern cpuop_func op_0cba_22_nf;
+extern cpuop_func op_0cba_22_ff;
+extern cpuop_func op_0cbb_22_nf;
+extern cpuop_func op_0cbb_22_ff;
+extern cpuop_func op_0cd0_22_nf;
+extern cpuop_func op_0cd0_22_ff;
+extern cpuop_func op_0cd8_22_nf;
+extern cpuop_func op_0cd8_22_ff;
+extern cpuop_func op_0ce0_22_nf;
+extern cpuop_func op_0ce0_22_ff;
+extern cpuop_func op_0ce8_22_nf;
+extern cpuop_func op_0ce8_22_ff;
+extern cpuop_func op_0cf0_22_nf;
+extern cpuop_func op_0cf0_22_ff;
+extern cpuop_func op_0cf8_22_nf;
+extern cpuop_func op_0cf8_22_ff;
+extern cpuop_func op_0cf9_22_nf;
+extern cpuop_func op_0cf9_22_ff;
+extern cpuop_func op_0cfc_22_nf;
+extern cpuop_func op_0cfc_22_ff;
+extern cpuop_func op_0e10_22_nf;
+extern cpuop_func op_0e10_22_ff;
+extern cpuop_func op_0e18_22_nf;
+extern cpuop_func op_0e18_22_ff;
+extern cpuop_func op_0e20_22_nf;
+extern cpuop_func op_0e20_22_ff;
+extern cpuop_func op_0e28_22_nf;
+extern cpuop_func op_0e28_22_ff;
+extern cpuop_func op_0e30_22_nf;
+extern cpuop_func op_0e30_22_ff;
+extern cpuop_func op_0e38_22_nf;
+extern cpuop_func op_0e38_22_ff;
+extern cpuop_func op_0e39_22_nf;
+extern cpuop_func op_0e39_22_ff;
+extern cpuop_func op_0e50_22_nf;
+extern cpuop_func op_0e50_22_ff;
+extern cpuop_func op_0e58_22_nf;
+extern cpuop_func op_0e58_22_ff;
+extern cpuop_func op_0e60_22_nf;
+extern cpuop_func op_0e60_22_ff;
+extern cpuop_func op_0e68_22_nf;
+extern cpuop_func op_0e68_22_ff;
+extern cpuop_func op_0e70_22_nf;
+extern cpuop_func op_0e70_22_ff;
+extern cpuop_func op_0e78_22_nf;
+extern cpuop_func op_0e78_22_ff;
+extern cpuop_func op_0e79_22_nf;
+extern cpuop_func op_0e79_22_ff;
+extern cpuop_func op_0e90_22_nf;
+extern cpuop_func op_0e90_22_ff;
+extern cpuop_func op_0e98_22_nf;
+extern cpuop_func op_0e98_22_ff;
+extern cpuop_func op_0ea0_22_nf;
+extern cpuop_func op_0ea0_22_ff;
+extern cpuop_func op_0ea8_22_nf;
+extern cpuop_func op_0ea8_22_ff;
+extern cpuop_func op_0eb0_22_nf;
+extern cpuop_func op_0eb0_22_ff;
+extern cpuop_func op_0eb8_22_nf;
+extern cpuop_func op_0eb8_22_ff;
+extern cpuop_func op_0eb9_22_nf;
+extern cpuop_func op_0eb9_22_ff;
+extern cpuop_func op_0ed0_22_nf;
+extern cpuop_func op_0ed0_22_ff;
+extern cpuop_func op_0ed8_22_nf;
+extern cpuop_func op_0ed8_22_ff;
+extern cpuop_func op_0ee0_22_nf;
+extern cpuop_func op_0ee0_22_ff;
+extern cpuop_func op_0ee8_22_nf;
+extern cpuop_func op_0ee8_22_ff;
+extern cpuop_func op_0ef0_22_nf;
+extern cpuop_func op_0ef0_22_ff;
+extern cpuop_func op_0ef8_22_nf;
+extern cpuop_func op_0ef8_22_ff;
+extern cpuop_func op_0ef9_22_nf;
+extern cpuop_func op_0ef9_22_ff;
+extern cpuop_func op_0efc_22_nf;
+extern cpuop_func op_0efc_22_ff;
+extern cpuop_func op_1000_22_nf;
+extern cpuop_func op_1000_22_ff;
+extern cpuop_func op_1010_22_nf;
+extern cpuop_func op_1010_22_ff;
+extern cpuop_func op_1018_22_nf;
+extern cpuop_func op_1018_22_ff;
+extern cpuop_func op_1020_22_nf;
+extern cpuop_func op_1020_22_ff;
+extern cpuop_func op_1028_22_nf;
+extern cpuop_func op_1028_22_ff;
+extern cpuop_func op_1030_22_nf;
+extern cpuop_func op_1030_22_ff;
+extern cpuop_func op_1038_22_nf;
+extern cpuop_func op_1038_22_ff;
+extern cpuop_func op_1039_22_nf;
+extern cpuop_func op_1039_22_ff;
+extern cpuop_func op_103a_22_nf;
+extern cpuop_func op_103a_22_ff;
+extern cpuop_func op_103b_22_nf;
+extern cpuop_func op_103b_22_ff;
+extern cpuop_func op_103c_22_nf;
+extern cpuop_func op_103c_22_ff;
+extern cpuop_func op_1080_22_nf;
+extern cpuop_func op_1080_22_ff;
+extern cpuop_func op_1090_22_nf;
+extern cpuop_func op_1090_22_ff;
+extern cpuop_func op_1098_22_nf;
+extern cpuop_func op_1098_22_ff;
+extern cpuop_func op_10a0_22_nf;
+extern cpuop_func op_10a0_22_ff;
+extern cpuop_func op_10a8_22_nf;
+extern cpuop_func op_10a8_22_ff;
+extern cpuop_func op_10b0_22_nf;
+extern cpuop_func op_10b0_22_ff;
+extern cpuop_func op_10b8_22_nf;
+extern cpuop_func op_10b8_22_ff;
+extern cpuop_func op_10b9_22_nf;
+extern cpuop_func op_10b9_22_ff;
+extern cpuop_func op_10ba_22_nf;
+extern cpuop_func op_10ba_22_ff;
+extern cpuop_func op_10bb_22_nf;
+extern cpuop_func op_10bb_22_ff;
+extern cpuop_func op_10bc_22_nf;
+extern cpuop_func op_10bc_22_ff;
+extern cpuop_func op_10c0_22_nf;
+extern cpuop_func op_10c0_22_ff;
+extern cpuop_func op_10d0_22_nf;
+extern cpuop_func op_10d0_22_ff;
+extern cpuop_func op_10d8_22_nf;
+extern cpuop_func op_10d8_22_ff;
+extern cpuop_func op_10e0_22_nf;
+extern cpuop_func op_10e0_22_ff;
+extern cpuop_func op_10e8_22_nf;
+extern cpuop_func op_10e8_22_ff;
+extern cpuop_func op_10f0_22_nf;
+extern cpuop_func op_10f0_22_ff;
+extern cpuop_func op_10f8_22_nf;
+extern cpuop_func op_10f8_22_ff;
+extern cpuop_func op_10f9_22_nf;
+extern cpuop_func op_10f9_22_ff;
+extern cpuop_func op_10fa_22_nf;
+extern cpuop_func op_10fa_22_ff;
+extern cpuop_func op_10fb_22_nf;
+extern cpuop_func op_10fb_22_ff;
+extern cpuop_func op_10fc_22_nf;
+extern cpuop_func op_10fc_22_ff;
+extern cpuop_func op_1100_22_nf;
+extern cpuop_func op_1100_22_ff;
+extern cpuop_func op_1110_22_nf;
+extern cpuop_func op_1110_22_ff;
+extern cpuop_func op_1118_22_nf;
+extern cpuop_func op_1118_22_ff;
+extern cpuop_func op_1120_22_nf;
+extern cpuop_func op_1120_22_ff;
+extern cpuop_func op_1128_22_nf;
+extern cpuop_func op_1128_22_ff;
+extern cpuop_func op_1130_22_nf;
+extern cpuop_func op_1130_22_ff;
+extern cpuop_func op_1138_22_nf;
+extern cpuop_func op_1138_22_ff;
+extern cpuop_func op_1139_22_nf;
+extern cpuop_func op_1139_22_ff;
+extern cpuop_func op_113a_22_nf;
+extern cpuop_func op_113a_22_ff;
+extern cpuop_func op_113b_22_nf;
+extern cpuop_func op_113b_22_ff;
+extern cpuop_func op_113c_22_nf;
+extern cpuop_func op_113c_22_ff;
+extern cpuop_func op_1140_22_nf;
+extern cpuop_func op_1140_22_ff;
+extern cpuop_func op_1150_22_nf;
+extern cpuop_func op_1150_22_ff;
+extern cpuop_func op_1158_22_nf;
+extern cpuop_func op_1158_22_ff;
+extern cpuop_func op_1160_22_nf;
+extern cpuop_func op_1160_22_ff;
+extern cpuop_func op_1168_22_nf;
+extern cpuop_func op_1168_22_ff;
+extern cpuop_func op_1170_22_nf;
+extern cpuop_func op_1170_22_ff;
+extern cpuop_func op_1178_22_nf;
+extern cpuop_func op_1178_22_ff;
+extern cpuop_func op_1179_22_nf;
+extern cpuop_func op_1179_22_ff;
+extern cpuop_func op_117a_22_nf;
+extern cpuop_func op_117a_22_ff;
+extern cpuop_func op_117b_22_nf;
+extern cpuop_func op_117b_22_ff;
+extern cpuop_func op_117c_22_nf;
+extern cpuop_func op_117c_22_ff;
+extern cpuop_func op_1180_22_nf;
+extern cpuop_func op_1180_22_ff;
+extern cpuop_func op_1190_22_nf;
+extern cpuop_func op_1190_22_ff;
+extern cpuop_func op_1198_22_nf;
+extern cpuop_func op_1198_22_ff;
+extern cpuop_func op_11a0_22_nf;
+extern cpuop_func op_11a0_22_ff;
+extern cpuop_func op_11a8_22_nf;
+extern cpuop_func op_11a8_22_ff;
+extern cpuop_func op_11b0_22_nf;
+extern cpuop_func op_11b0_22_ff;
+extern cpuop_func op_11b8_22_nf;
+extern cpuop_func op_11b8_22_ff;
+extern cpuop_func op_11b9_22_nf;
+extern cpuop_func op_11b9_22_ff;
+extern cpuop_func op_11ba_22_nf;
+extern cpuop_func op_11ba_22_ff;
+extern cpuop_func op_11bb_22_nf;
+extern cpuop_func op_11bb_22_ff;
+extern cpuop_func op_11bc_22_nf;
+extern cpuop_func op_11bc_22_ff;
+extern cpuop_func op_11c0_22_nf;
+extern cpuop_func op_11c0_22_ff;
+extern cpuop_func op_11d0_22_nf;
+extern cpuop_func op_11d0_22_ff;
+extern cpuop_func op_11d8_22_nf;
+extern cpuop_func op_11d8_22_ff;
+extern cpuop_func op_11e0_22_nf;
+extern cpuop_func op_11e0_22_ff;
+extern cpuop_func op_11e8_22_nf;
+extern cpuop_func op_11e8_22_ff;
+extern cpuop_func op_11f0_22_nf;
+extern cpuop_func op_11f0_22_ff;
+extern cpuop_func op_11f8_22_nf;
+extern cpuop_func op_11f8_22_ff;
+extern cpuop_func op_11f9_22_nf;
+extern cpuop_func op_11f9_22_ff;
+extern cpuop_func op_11fa_22_nf;
+extern cpuop_func op_11fa_22_ff;
+extern cpuop_func op_11fb_22_nf;
+extern cpuop_func op_11fb_22_ff;
+extern cpuop_func op_11fc_22_nf;
+extern cpuop_func op_11fc_22_ff;
+extern cpuop_func op_13c0_22_nf;
+extern cpuop_func op_13c0_22_ff;
+extern cpuop_func op_13d0_22_nf;
+extern cpuop_func op_13d0_22_ff;
+extern cpuop_func op_13d8_22_nf;
+extern cpuop_func op_13d8_22_ff;
+extern cpuop_func op_13e0_22_nf;
+extern cpuop_func op_13e0_22_ff;
+extern cpuop_func op_13e8_22_nf;
+extern cpuop_func op_13e8_22_ff;
+extern cpuop_func op_13f0_22_nf;
+extern cpuop_func op_13f0_22_ff;
+extern cpuop_func op_13f8_22_nf;
+extern cpuop_func op_13f8_22_ff;
+extern cpuop_func op_13f9_22_nf;
+extern cpuop_func op_13f9_22_ff;
+extern cpuop_func op_13fa_22_nf;
+extern cpuop_func op_13fa_22_ff;
+extern cpuop_func op_13fb_22_nf;
+extern cpuop_func op_13fb_22_ff;
+extern cpuop_func op_13fc_22_nf;
+extern cpuop_func op_13fc_22_ff;
+extern cpuop_func op_2000_22_nf;
+extern cpuop_func op_2000_22_ff;
+extern cpuop_func op_2008_22_nf;
+extern cpuop_func op_2008_22_ff;
+extern cpuop_func op_2010_22_nf;
+extern cpuop_func op_2010_22_ff;
+extern cpuop_func op_2018_22_nf;
+extern cpuop_func op_2018_22_ff;
+extern cpuop_func op_2020_22_nf;
+extern cpuop_func op_2020_22_ff;
+extern cpuop_func op_2028_22_nf;
+extern cpuop_func op_2028_22_ff;
+extern cpuop_func op_2030_22_nf;
+extern cpuop_func op_2030_22_ff;
+extern cpuop_func op_2038_22_nf;
+extern cpuop_func op_2038_22_ff;
+extern cpuop_func op_2039_22_nf;
+extern cpuop_func op_2039_22_ff;
+extern cpuop_func op_203a_22_nf;
+extern cpuop_func op_203a_22_ff;
+extern cpuop_func op_203b_22_nf;
+extern cpuop_func op_203b_22_ff;
+extern cpuop_func op_203c_22_nf;
+extern cpuop_func op_203c_22_ff;
+extern cpuop_func op_2040_22_nf;
+extern cpuop_func op_2040_22_ff;
+extern cpuop_func op_2048_22_nf;
+extern cpuop_func op_2048_22_ff;
+extern cpuop_func op_2050_22_nf;
+extern cpuop_func op_2050_22_ff;
+extern cpuop_func op_2058_22_nf;
+extern cpuop_func op_2058_22_ff;
+extern cpuop_func op_2060_22_nf;
+extern cpuop_func op_2060_22_ff;
+extern cpuop_func op_2068_22_nf;
+extern cpuop_func op_2068_22_ff;
+extern cpuop_func op_2070_22_nf;
+extern cpuop_func op_2070_22_ff;
+extern cpuop_func op_2078_22_nf;
+extern cpuop_func op_2078_22_ff;
+extern cpuop_func op_2079_22_nf;
+extern cpuop_func op_2079_22_ff;
+extern cpuop_func op_207a_22_nf;
+extern cpuop_func op_207a_22_ff;
+extern cpuop_func op_207b_22_nf;
+extern cpuop_func op_207b_22_ff;
+extern cpuop_func op_207c_22_nf;
+extern cpuop_func op_207c_22_ff;
+extern cpuop_func op_2080_22_nf;
+extern cpuop_func op_2080_22_ff;
+extern cpuop_func op_2088_22_nf;
+extern cpuop_func op_2088_22_ff;
+extern cpuop_func op_2090_22_nf;
+extern cpuop_func op_2090_22_ff;
+extern cpuop_func op_2098_22_nf;
+extern cpuop_func op_2098_22_ff;
+extern cpuop_func op_20a0_22_nf;
+extern cpuop_func op_20a0_22_ff;
+extern cpuop_func op_20a8_22_nf;
+extern cpuop_func op_20a8_22_ff;
+extern cpuop_func op_20b0_22_nf;
+extern cpuop_func op_20b0_22_ff;
+extern cpuop_func op_20b8_22_nf;
+extern cpuop_func op_20b8_22_ff;
+extern cpuop_func op_20b9_22_nf;
+extern cpuop_func op_20b9_22_ff;
+extern cpuop_func op_20ba_22_nf;
+extern cpuop_func op_20ba_22_ff;
+extern cpuop_func op_20bb_22_nf;
+extern cpuop_func op_20bb_22_ff;
+extern cpuop_func op_20bc_22_nf;
+extern cpuop_func op_20bc_22_ff;
+extern cpuop_func op_20c0_22_nf;
+extern cpuop_func op_20c0_22_ff;
+extern cpuop_func op_20c8_22_nf;
+extern cpuop_func op_20c8_22_ff;
+extern cpuop_func op_20d0_22_nf;
+extern cpuop_func op_20d0_22_ff;
+extern cpuop_func op_20d8_22_nf;
+extern cpuop_func op_20d8_22_ff;
+extern cpuop_func op_20e0_22_nf;
+extern cpuop_func op_20e0_22_ff;
+extern cpuop_func op_20e8_22_nf;
+extern cpuop_func op_20e8_22_ff;
+extern cpuop_func op_20f0_22_nf;
+extern cpuop_func op_20f0_22_ff;
+extern cpuop_func op_20f8_22_nf;
+extern cpuop_func op_20f8_22_ff;
+extern cpuop_func op_20f9_22_nf;
+extern cpuop_func op_20f9_22_ff;
+extern cpuop_func op_20fa_22_nf;
+extern cpuop_func op_20fa_22_ff;
+extern cpuop_func op_20fb_22_nf;
+extern cpuop_func op_20fb_22_ff;
+extern cpuop_func op_20fc_22_nf;
+extern cpuop_func op_20fc_22_ff;
+extern cpuop_func op_2100_22_nf;
+extern cpuop_func op_2100_22_ff;
+extern cpuop_func op_2108_22_nf;
+extern cpuop_func op_2108_22_ff;
+extern cpuop_func op_2110_22_nf;
+extern cpuop_func op_2110_22_ff;
+extern cpuop_func op_2118_22_nf;
+extern cpuop_func op_2118_22_ff;
+extern cpuop_func op_2120_22_nf;
+extern cpuop_func op_2120_22_ff;
+extern cpuop_func op_2128_22_nf;
+extern cpuop_func op_2128_22_ff;
+extern cpuop_func op_2130_22_nf;
+extern cpuop_func op_2130_22_ff;
+extern cpuop_func op_2138_22_nf;
+extern cpuop_func op_2138_22_ff;
+extern cpuop_func op_2139_22_nf;
+extern cpuop_func op_2139_22_ff;
+extern cpuop_func op_213a_22_nf;
+extern cpuop_func op_213a_22_ff;
+extern cpuop_func op_213b_22_nf;
+extern cpuop_func op_213b_22_ff;
+extern cpuop_func op_213c_22_nf;
+extern cpuop_func op_213c_22_ff;
+extern cpuop_func op_2140_22_nf;
+extern cpuop_func op_2140_22_ff;
+extern cpuop_func op_2148_22_nf;
+extern cpuop_func op_2148_22_ff;
+extern cpuop_func op_2150_22_nf;
+extern cpuop_func op_2150_22_ff;
+extern cpuop_func op_2158_22_nf;
+extern cpuop_func op_2158_22_ff;
+extern cpuop_func op_2160_22_nf;
+extern cpuop_func op_2160_22_ff;
+extern cpuop_func op_2168_22_nf;
+extern cpuop_func op_2168_22_ff;
+extern cpuop_func op_2170_22_nf;
+extern cpuop_func op_2170_22_ff;
+extern cpuop_func op_2178_22_nf;
+extern cpuop_func op_2178_22_ff;
+extern cpuop_func op_2179_22_nf;
+extern cpuop_func op_2179_22_ff;
+extern cpuop_func op_217a_22_nf;
+extern cpuop_func op_217a_22_ff;
+extern cpuop_func op_217b_22_nf;
+extern cpuop_func op_217b_22_ff;
+extern cpuop_func op_217c_22_nf;
+extern cpuop_func op_217c_22_ff;
+extern cpuop_func op_2180_22_nf;
+extern cpuop_func op_2180_22_ff;
+extern cpuop_func op_2188_22_nf;
+extern cpuop_func op_2188_22_ff;
+extern cpuop_func op_2190_22_nf;
+extern cpuop_func op_2190_22_ff;
+extern cpuop_func op_2198_22_nf;
+extern cpuop_func op_2198_22_ff;
+extern cpuop_func op_21a0_22_nf;
+extern cpuop_func op_21a0_22_ff;
+extern cpuop_func op_21a8_22_nf;
+extern cpuop_func op_21a8_22_ff;
+extern cpuop_func op_21b0_22_nf;
+extern cpuop_func op_21b0_22_ff;
+extern cpuop_func op_21b8_22_nf;
+extern cpuop_func op_21b8_22_ff;
+extern cpuop_func op_21b9_22_nf;
+extern cpuop_func op_21b9_22_ff;
+extern cpuop_func op_21ba_22_nf;
+extern cpuop_func op_21ba_22_ff;
+extern cpuop_func op_21bb_22_nf;
+extern cpuop_func op_21bb_22_ff;
+extern cpuop_func op_21bc_22_nf;
+extern cpuop_func op_21bc_22_ff;
+extern cpuop_func op_21c0_22_nf;
+extern cpuop_func op_21c0_22_ff;
+extern cpuop_func op_21c8_22_nf;
+extern cpuop_func op_21c8_22_ff;
+extern cpuop_func op_21d0_22_nf;
+extern cpuop_func op_21d0_22_ff;
+extern cpuop_func op_21d8_22_nf;
+extern cpuop_func op_21d8_22_ff;
+extern cpuop_func op_21e0_22_nf;
+extern cpuop_func op_21e0_22_ff;
+extern cpuop_func op_21e8_22_nf;
+extern cpuop_func op_21e8_22_ff;
+extern cpuop_func op_21f0_22_nf;
+extern cpuop_func op_21f0_22_ff;
+extern cpuop_func op_21f8_22_nf;
+extern cpuop_func op_21f8_22_ff;
+extern cpuop_func op_21f9_22_nf;
+extern cpuop_func op_21f9_22_ff;
+extern cpuop_func op_21fa_22_nf;
+extern cpuop_func op_21fa_22_ff;
+extern cpuop_func op_21fb_22_nf;
+extern cpuop_func op_21fb_22_ff;
+extern cpuop_func op_21fc_22_nf;
+extern cpuop_func op_21fc_22_ff;
+extern cpuop_func op_23c0_22_nf;
+extern cpuop_func op_23c0_22_ff;
+extern cpuop_func op_23c8_22_nf;
+extern cpuop_func op_23c8_22_ff;
+extern cpuop_func op_23d0_22_nf;
+extern cpuop_func op_23d0_22_ff;
+extern cpuop_func op_23d8_22_nf;
+extern cpuop_func op_23d8_22_ff;
+extern cpuop_func op_23e0_22_nf;
+extern cpuop_func op_23e0_22_ff;
+extern cpuop_func op_23e8_22_nf;
+extern cpuop_func op_23e8_22_ff;
+extern cpuop_func op_23f0_22_nf;
+extern cpuop_func op_23f0_22_ff;
+extern cpuop_func op_23f8_22_nf;
+extern cpuop_func op_23f8_22_ff;
+extern cpuop_func op_23f9_22_nf;
+extern cpuop_func op_23f9_22_ff;
+extern cpuop_func op_23fa_22_nf;
+extern cpuop_func op_23fa_22_ff;
+extern cpuop_func op_23fb_22_nf;
+extern cpuop_func op_23fb_22_ff;
+extern cpuop_func op_23fc_22_nf;
+extern cpuop_func op_23fc_22_ff;
+extern cpuop_func op_3000_22_nf;
+extern cpuop_func op_3000_22_ff;
+extern cpuop_func op_3008_22_nf;
+extern cpuop_func op_3008_22_ff;
+extern cpuop_func op_3010_22_nf;
+extern cpuop_func op_3010_22_ff;
+extern cpuop_func op_3018_22_nf;
+extern cpuop_func op_3018_22_ff;
+extern cpuop_func op_3020_22_nf;
+extern cpuop_func op_3020_22_ff;
+extern cpuop_func op_3028_22_nf;
+extern cpuop_func op_3028_22_ff;
+extern cpuop_func op_3030_22_nf;
+extern cpuop_func op_3030_22_ff;
+extern cpuop_func op_3038_22_nf;
+extern cpuop_func op_3038_22_ff;
+extern cpuop_func op_3039_22_nf;
+extern cpuop_func op_3039_22_ff;
+extern cpuop_func op_303a_22_nf;
+extern cpuop_func op_303a_22_ff;
+extern cpuop_func op_303b_22_nf;
+extern cpuop_func op_303b_22_ff;
+extern cpuop_func op_303c_22_nf;
+extern cpuop_func op_303c_22_ff;
+extern cpuop_func op_3040_22_nf;
+extern cpuop_func op_3040_22_ff;
+extern cpuop_func op_3048_22_nf;
+extern cpuop_func op_3048_22_ff;
+extern cpuop_func op_3050_22_nf;
+extern cpuop_func op_3050_22_ff;
+extern cpuop_func op_3058_22_nf;
+extern cpuop_func op_3058_22_ff;
+extern cpuop_func op_3060_22_nf;
+extern cpuop_func op_3060_22_ff;
+extern cpuop_func op_3068_22_nf;
+extern cpuop_func op_3068_22_ff;
+extern cpuop_func op_3070_22_nf;
+extern cpuop_func op_3070_22_ff;
+extern cpuop_func op_3078_22_nf;
+extern cpuop_func op_3078_22_ff;
+extern cpuop_func op_3079_22_nf;
+extern cpuop_func op_3079_22_ff;
+extern cpuop_func op_307a_22_nf;
+extern cpuop_func op_307a_22_ff;
+extern cpuop_func op_307b_22_nf;
+extern cpuop_func op_307b_22_ff;
+extern cpuop_func op_307c_22_nf;
+extern cpuop_func op_307c_22_ff;
+extern cpuop_func op_3080_22_nf;
+extern cpuop_func op_3080_22_ff;
+extern cpuop_func op_3088_22_nf;
+extern cpuop_func op_3088_22_ff;
+extern cpuop_func op_3090_22_nf;
+extern cpuop_func op_3090_22_ff;
+extern cpuop_func op_3098_22_nf;
+extern cpuop_func op_3098_22_ff;
+extern cpuop_func op_30a0_22_nf;
+extern cpuop_func op_30a0_22_ff;
+extern cpuop_func op_30a8_22_nf;
+extern cpuop_func op_30a8_22_ff;
+extern cpuop_func op_30b0_22_nf;
+extern cpuop_func op_30b0_22_ff;
+extern cpuop_func op_30b8_22_nf;
+extern cpuop_func op_30b8_22_ff;
+extern cpuop_func op_30b9_22_nf;
+extern cpuop_func op_30b9_22_ff;
+extern cpuop_func op_30ba_22_nf;
+extern cpuop_func op_30ba_22_ff;
+extern cpuop_func op_30bb_22_nf;
+extern cpuop_func op_30bb_22_ff;
+extern cpuop_func op_30bc_22_nf;
+extern cpuop_func op_30bc_22_ff;
+extern cpuop_func op_30c0_22_nf;
+extern cpuop_func op_30c0_22_ff;
+extern cpuop_func op_30c8_22_nf;
+extern cpuop_func op_30c8_22_ff;
+extern cpuop_func op_30d0_22_nf;
+extern cpuop_func op_30d0_22_ff;
+extern cpuop_func op_30d8_22_nf;
+extern cpuop_func op_30d8_22_ff;
+extern cpuop_func op_30e0_22_nf;
+extern cpuop_func op_30e0_22_ff;
+extern cpuop_func op_30e8_22_nf;
+extern cpuop_func op_30e8_22_ff;
+extern cpuop_func op_30f0_22_nf;
+extern cpuop_func op_30f0_22_ff;
+extern cpuop_func op_30f8_22_nf;
+extern cpuop_func op_30f8_22_ff;
+extern cpuop_func op_30f9_22_nf;
+extern cpuop_func op_30f9_22_ff;
+extern cpuop_func op_30fa_22_nf;
+extern cpuop_func op_30fa_22_ff;
+extern cpuop_func op_30fb_22_nf;
+extern cpuop_func op_30fb_22_ff;
+extern cpuop_func op_30fc_22_nf;
+extern cpuop_func op_30fc_22_ff;
+extern cpuop_func op_3100_22_nf;
+extern cpuop_func op_3100_22_ff;
+extern cpuop_func op_3108_22_nf;
+extern cpuop_func op_3108_22_ff;
+extern cpuop_func op_3110_22_nf;
+extern cpuop_func op_3110_22_ff;
+extern cpuop_func op_3118_22_nf;
+extern cpuop_func op_3118_22_ff;
+extern cpuop_func op_3120_22_nf;
+extern cpuop_func op_3120_22_ff;
+extern cpuop_func op_3128_22_nf;
+extern cpuop_func op_3128_22_ff;
+extern cpuop_func op_3130_22_nf;
+extern cpuop_func op_3130_22_ff;
+extern cpuop_func op_3138_22_nf;
+extern cpuop_func op_3138_22_ff;
+extern cpuop_func op_3139_22_nf;
+extern cpuop_func op_3139_22_ff;
+extern cpuop_func op_313a_22_nf;
+extern cpuop_func op_313a_22_ff;
+extern cpuop_func op_313b_22_nf;
+extern cpuop_func op_313b_22_ff;
+extern cpuop_func op_313c_22_nf;
+extern cpuop_func op_313c_22_ff;
+extern cpuop_func op_3140_22_nf;
+extern cpuop_func op_3140_22_ff;
+extern cpuop_func op_3148_22_nf;
+extern cpuop_func op_3148_22_ff;
+extern cpuop_func op_3150_22_nf;
+extern cpuop_func op_3150_22_ff;
+extern cpuop_func op_3158_22_nf;
+extern cpuop_func op_3158_22_ff;
+extern cpuop_func op_3160_22_nf;
+extern cpuop_func op_3160_22_ff;
+extern cpuop_func op_3168_22_nf;
+extern cpuop_func op_3168_22_ff;
+extern cpuop_func op_3170_22_nf;
+extern cpuop_func op_3170_22_ff;
+extern cpuop_func op_3178_22_nf;
+extern cpuop_func op_3178_22_ff;
+extern cpuop_func op_3179_22_nf;
+extern cpuop_func op_3179_22_ff;
+extern cpuop_func op_317a_22_nf;
+extern cpuop_func op_317a_22_ff;
+extern cpuop_func op_317b_22_nf;
+extern cpuop_func op_317b_22_ff;
+extern cpuop_func op_317c_22_nf;
+extern cpuop_func op_317c_22_ff;
+extern cpuop_func op_3180_22_nf;
+extern cpuop_func op_3180_22_ff;
+extern cpuop_func op_3188_22_nf;
+extern cpuop_func op_3188_22_ff;
+extern cpuop_func op_3190_22_nf;
+extern cpuop_func op_3190_22_ff;
+extern cpuop_func op_3198_22_nf;
+extern cpuop_func op_3198_22_ff;
+extern cpuop_func op_31a0_22_nf;
+extern cpuop_func op_31a0_22_ff;
+extern cpuop_func op_31a8_22_nf;
+extern cpuop_func op_31a8_22_ff;
+extern cpuop_func op_31b0_22_nf;
+extern cpuop_func op_31b0_22_ff;
+extern cpuop_func op_31b8_22_nf;
+extern cpuop_func op_31b8_22_ff;
+extern cpuop_func op_31b9_22_nf;
+extern cpuop_func op_31b9_22_ff;
+extern cpuop_func op_31ba_22_nf;
+extern cpuop_func op_31ba_22_ff;
+extern cpuop_func op_31bb_22_nf;
+extern cpuop_func op_31bb_22_ff;
+extern cpuop_func op_31bc_22_nf;
+extern cpuop_func op_31bc_22_ff;
+extern cpuop_func op_31c0_22_nf;
+extern cpuop_func op_31c0_22_ff;
+extern cpuop_func op_31c8_22_nf;
+extern cpuop_func op_31c8_22_ff;
+extern cpuop_func op_31d0_22_nf;
+extern cpuop_func op_31d0_22_ff;
+extern cpuop_func op_31d8_22_nf;
+extern cpuop_func op_31d8_22_ff;
+extern cpuop_func op_31e0_22_nf;
+extern cpuop_func op_31e0_22_ff;
+extern cpuop_func op_31e8_22_nf;
+extern cpuop_func op_31e8_22_ff;
+extern cpuop_func op_31f0_22_nf;
+extern cpuop_func op_31f0_22_ff;
+extern cpuop_func op_31f8_22_nf;
+extern cpuop_func op_31f8_22_ff;
+extern cpuop_func op_31f9_22_nf;
+extern cpuop_func op_31f9_22_ff;
+extern cpuop_func op_31fa_22_nf;
+extern cpuop_func op_31fa_22_ff;
+extern cpuop_func op_31fb_22_nf;
+extern cpuop_func op_31fb_22_ff;
+extern cpuop_func op_31fc_22_nf;
+extern cpuop_func op_31fc_22_ff;
+extern cpuop_func op_33c0_22_nf;
+extern cpuop_func op_33c0_22_ff;
+extern cpuop_func op_33c8_22_nf;
+extern cpuop_func op_33c8_22_ff;
+extern cpuop_func op_33d0_22_nf;
+extern cpuop_func op_33d0_22_ff;
+extern cpuop_func op_33d8_22_nf;
+extern cpuop_func op_33d8_22_ff;
+extern cpuop_func op_33e0_22_nf;
+extern cpuop_func op_33e0_22_ff;
+extern cpuop_func op_33e8_22_nf;
+extern cpuop_func op_33e8_22_ff;
+extern cpuop_func op_33f0_22_nf;
+extern cpuop_func op_33f0_22_ff;
+extern cpuop_func op_33f8_22_nf;
+extern cpuop_func op_33f8_22_ff;
+extern cpuop_func op_33f9_22_nf;
+extern cpuop_func op_33f9_22_ff;
+extern cpuop_func op_33fa_22_nf;
+extern cpuop_func op_33fa_22_ff;
+extern cpuop_func op_33fb_22_nf;
+extern cpuop_func op_33fb_22_ff;
+extern cpuop_func op_33fc_22_nf;
+extern cpuop_func op_33fc_22_ff;
+extern cpuop_func op_4000_22_nf;
+extern cpuop_func op_4000_22_ff;
+extern cpuop_func op_4010_22_nf;
+extern cpuop_func op_4010_22_ff;
+extern cpuop_func op_4018_22_nf;
+extern cpuop_func op_4018_22_ff;
+extern cpuop_func op_4020_22_nf;
+extern cpuop_func op_4020_22_ff;
+extern cpuop_func op_4028_22_nf;
+extern cpuop_func op_4028_22_ff;
+extern cpuop_func op_4030_22_nf;
+extern cpuop_func op_4030_22_ff;
+extern cpuop_func op_4038_22_nf;
+extern cpuop_func op_4038_22_ff;
+extern cpuop_func op_4039_22_nf;
+extern cpuop_func op_4039_22_ff;
+extern cpuop_func op_4040_22_nf;
+extern cpuop_func op_4040_22_ff;
+extern cpuop_func op_4050_22_nf;
+extern cpuop_func op_4050_22_ff;
+extern cpuop_func op_4058_22_nf;
+extern cpuop_func op_4058_22_ff;
+extern cpuop_func op_4060_22_nf;
+extern cpuop_func op_4060_22_ff;
+extern cpuop_func op_4068_22_nf;
+extern cpuop_func op_4068_22_ff;
+extern cpuop_func op_4070_22_nf;
+extern cpuop_func op_4070_22_ff;
+extern cpuop_func op_4078_22_nf;
+extern cpuop_func op_4078_22_ff;
+extern cpuop_func op_4079_22_nf;
+extern cpuop_func op_4079_22_ff;
+extern cpuop_func op_4080_22_nf;
+extern cpuop_func op_4080_22_ff;
+extern cpuop_func op_4090_22_nf;
+extern cpuop_func op_4090_22_ff;
+extern cpuop_func op_4098_22_nf;
+extern cpuop_func op_4098_22_ff;
+extern cpuop_func op_40a0_22_nf;
+extern cpuop_func op_40a0_22_ff;
+extern cpuop_func op_40a8_22_nf;
+extern cpuop_func op_40a8_22_ff;
+extern cpuop_func op_40b0_22_nf;
+extern cpuop_func op_40b0_22_ff;
+extern cpuop_func op_40b8_22_nf;
+extern cpuop_func op_40b8_22_ff;
+extern cpuop_func op_40b9_22_nf;
+extern cpuop_func op_40b9_22_ff;
+extern cpuop_func op_40c0_22_nf;
+extern cpuop_func op_40c0_22_ff;
+extern cpuop_func op_40d0_22_nf;
+extern cpuop_func op_40d0_22_ff;
+extern cpuop_func op_40d8_22_nf;
+extern cpuop_func op_40d8_22_ff;
+extern cpuop_func op_40e0_22_nf;
+extern cpuop_func op_40e0_22_ff;
+extern cpuop_func op_40e8_22_nf;
+extern cpuop_func op_40e8_22_ff;
+extern cpuop_func op_40f0_22_nf;
+extern cpuop_func op_40f0_22_ff;
+extern cpuop_func op_40f8_22_nf;
+extern cpuop_func op_40f8_22_ff;
+extern cpuop_func op_40f9_22_nf;
+extern cpuop_func op_40f9_22_ff;
+extern cpuop_func op_4100_22_nf;
+extern cpuop_func op_4100_22_ff;
+extern cpuop_func op_4110_22_nf;
+extern cpuop_func op_4110_22_ff;
+extern cpuop_func op_4118_22_nf;
+extern cpuop_func op_4118_22_ff;
+extern cpuop_func op_4120_22_nf;
+extern cpuop_func op_4120_22_ff;
+extern cpuop_func op_4128_22_nf;
+extern cpuop_func op_4128_22_ff;
+extern cpuop_func op_4130_22_nf;
+extern cpuop_func op_4130_22_ff;
+extern cpuop_func op_4138_22_nf;
+extern cpuop_func op_4138_22_ff;
+extern cpuop_func op_4139_22_nf;
+extern cpuop_func op_4139_22_ff;
+extern cpuop_func op_413a_22_nf;
+extern cpuop_func op_413a_22_ff;
+extern cpuop_func op_413b_22_nf;
+extern cpuop_func op_413b_22_ff;
+extern cpuop_func op_413c_22_nf;
+extern cpuop_func op_413c_22_ff;
+extern cpuop_func op_4180_22_nf;
+extern cpuop_func op_4180_22_ff;
+extern cpuop_func op_4190_22_nf;
+extern cpuop_func op_4190_22_ff;
+extern cpuop_func op_4198_22_nf;
+extern cpuop_func op_4198_22_ff;
+extern cpuop_func op_41a0_22_nf;
+extern cpuop_func op_41a0_22_ff;
+extern cpuop_func op_41a8_22_nf;
+extern cpuop_func op_41a8_22_ff;
+extern cpuop_func op_41b0_22_nf;
+extern cpuop_func op_41b0_22_ff;
+extern cpuop_func op_41b8_22_nf;
+extern cpuop_func op_41b8_22_ff;
+extern cpuop_func op_41b9_22_nf;
+extern cpuop_func op_41b9_22_ff;
+extern cpuop_func op_41ba_22_nf;
+extern cpuop_func op_41ba_22_ff;
+extern cpuop_func op_41bb_22_nf;
+extern cpuop_func op_41bb_22_ff;
+extern cpuop_func op_41bc_22_nf;
+extern cpuop_func op_41bc_22_ff;
+extern cpuop_func op_41d0_22_nf;
+extern cpuop_func op_41d0_22_ff;
+extern cpuop_func op_41e8_22_nf;
+extern cpuop_func op_41e8_22_ff;
+extern cpuop_func op_41f0_22_nf;
+extern cpuop_func op_41f0_22_ff;
+extern cpuop_func op_41f8_22_nf;
+extern cpuop_func op_41f8_22_ff;
+extern cpuop_func op_41f9_22_nf;
+extern cpuop_func op_41f9_22_ff;
+extern cpuop_func op_41fa_22_nf;
+extern cpuop_func op_41fa_22_ff;
+extern cpuop_func op_41fb_22_nf;
+extern cpuop_func op_41fb_22_ff;
+extern cpuop_func op_4200_22_nf;
+extern cpuop_func op_4200_22_ff;
+extern cpuop_func op_4210_22_nf;
+extern cpuop_func op_4210_22_ff;
+extern cpuop_func op_4218_22_nf;
+extern cpuop_func op_4218_22_ff;
+extern cpuop_func op_4220_22_nf;
+extern cpuop_func op_4220_22_ff;
+extern cpuop_func op_4228_22_nf;
+extern cpuop_func op_4228_22_ff;
+extern cpuop_func op_4230_22_nf;
+extern cpuop_func op_4230_22_ff;
+extern cpuop_func op_4238_22_nf;
+extern cpuop_func op_4238_22_ff;
+extern cpuop_func op_4239_22_nf;
+extern cpuop_func op_4239_22_ff;
+extern cpuop_func op_4240_22_nf;
+extern cpuop_func op_4240_22_ff;
+extern cpuop_func op_4250_22_nf;
+extern cpuop_func op_4250_22_ff;
+extern cpuop_func op_4258_22_nf;
+extern cpuop_func op_4258_22_ff;
+extern cpuop_func op_4260_22_nf;
+extern cpuop_func op_4260_22_ff;
+extern cpuop_func op_4268_22_nf;
+extern cpuop_func op_4268_22_ff;
+extern cpuop_func op_4270_22_nf;
+extern cpuop_func op_4270_22_ff;
+extern cpuop_func op_4278_22_nf;
+extern cpuop_func op_4278_22_ff;
+extern cpuop_func op_4279_22_nf;
+extern cpuop_func op_4279_22_ff;
+extern cpuop_func op_4280_22_nf;
+extern cpuop_func op_4280_22_ff;
+extern cpuop_func op_4290_22_nf;
+extern cpuop_func op_4290_22_ff;
+extern cpuop_func op_4298_22_nf;
+extern cpuop_func op_4298_22_ff;
+extern cpuop_func op_42a0_22_nf;
+extern cpuop_func op_42a0_22_ff;
+extern cpuop_func op_42a8_22_nf;
+extern cpuop_func op_42a8_22_ff;
+extern cpuop_func op_42b0_22_nf;
+extern cpuop_func op_42b0_22_ff;
+extern cpuop_func op_42b8_22_nf;
+extern cpuop_func op_42b8_22_ff;
+extern cpuop_func op_42b9_22_nf;
+extern cpuop_func op_42b9_22_ff;
+extern cpuop_func op_42c0_22_nf;
+extern cpuop_func op_42c0_22_ff;
+extern cpuop_func op_42d0_22_nf;
+extern cpuop_func op_42d0_22_ff;
+extern cpuop_func op_42d8_22_nf;
+extern cpuop_func op_42d8_22_ff;
+extern cpuop_func op_42e0_22_nf;
+extern cpuop_func op_42e0_22_ff;
+extern cpuop_func op_42e8_22_nf;
+extern cpuop_func op_42e8_22_ff;
+extern cpuop_func op_42f0_22_nf;
+extern cpuop_func op_42f0_22_ff;
+extern cpuop_func op_42f8_22_nf;
+extern cpuop_func op_42f8_22_ff;
+extern cpuop_func op_42f9_22_nf;
+extern cpuop_func op_42f9_22_ff;
+extern cpuop_func op_4400_22_nf;
+extern cpuop_func op_4400_22_ff;
+extern cpuop_func op_4410_22_nf;
+extern cpuop_func op_4410_22_ff;
+extern cpuop_func op_4418_22_nf;
+extern cpuop_func op_4418_22_ff;
+extern cpuop_func op_4420_22_nf;
+extern cpuop_func op_4420_22_ff;
+extern cpuop_func op_4428_22_nf;
+extern cpuop_func op_4428_22_ff;
+extern cpuop_func op_4430_22_nf;
+extern cpuop_func op_4430_22_ff;
+extern cpuop_func op_4438_22_nf;
+extern cpuop_func op_4438_22_ff;
+extern cpuop_func op_4439_22_nf;
+extern cpuop_func op_4439_22_ff;
+extern cpuop_func op_4440_22_nf;
+extern cpuop_func op_4440_22_ff;
+extern cpuop_func op_4450_22_nf;
+extern cpuop_func op_4450_22_ff;
+extern cpuop_func op_4458_22_nf;
+extern cpuop_func op_4458_22_ff;
+extern cpuop_func op_4460_22_nf;
+extern cpuop_func op_4460_22_ff;
+extern cpuop_func op_4468_22_nf;
+extern cpuop_func op_4468_22_ff;
+extern cpuop_func op_4470_22_nf;
+extern cpuop_func op_4470_22_ff;
+extern cpuop_func op_4478_22_nf;
+extern cpuop_func op_4478_22_ff;
+extern cpuop_func op_4479_22_nf;
+extern cpuop_func op_4479_22_ff;
+extern cpuop_func op_4480_22_nf;
+extern cpuop_func op_4480_22_ff;
+extern cpuop_func op_4490_22_nf;
+extern cpuop_func op_4490_22_ff;
+extern cpuop_func op_4498_22_nf;
+extern cpuop_func op_4498_22_ff;
+extern cpuop_func op_44a0_22_nf;
+extern cpuop_func op_44a0_22_ff;
+extern cpuop_func op_44a8_22_nf;
+extern cpuop_func op_44a8_22_ff;
+extern cpuop_func op_44b0_22_nf;
+extern cpuop_func op_44b0_22_ff;
+extern cpuop_func op_44b8_22_nf;
+extern cpuop_func op_44b8_22_ff;
+extern cpuop_func op_44b9_22_nf;
+extern cpuop_func op_44b9_22_ff;
+extern cpuop_func op_44c0_22_nf;
+extern cpuop_func op_44c0_22_ff;
+extern cpuop_func op_44d0_22_nf;
+extern cpuop_func op_44d0_22_ff;
+extern cpuop_func op_44d8_22_nf;
+extern cpuop_func op_44d8_22_ff;
+extern cpuop_func op_44e0_22_nf;
+extern cpuop_func op_44e0_22_ff;
+extern cpuop_func op_44e8_22_nf;
+extern cpuop_func op_44e8_22_ff;
+extern cpuop_func op_44f0_22_nf;
+extern cpuop_func op_44f0_22_ff;
+extern cpuop_func op_44f8_22_nf;
+extern cpuop_func op_44f8_22_ff;
+extern cpuop_func op_44f9_22_nf;
+extern cpuop_func op_44f9_22_ff;
+extern cpuop_func op_44fa_22_nf;
+extern cpuop_func op_44fa_22_ff;
+extern cpuop_func op_44fb_22_nf;
+extern cpuop_func op_44fb_22_ff;
+extern cpuop_func op_44fc_22_nf;
+extern cpuop_func op_44fc_22_ff;
+extern cpuop_func op_4600_22_nf;
+extern cpuop_func op_4600_22_ff;
+extern cpuop_func op_4610_22_nf;
+extern cpuop_func op_4610_22_ff;
+extern cpuop_func op_4618_22_nf;
+extern cpuop_func op_4618_22_ff;
+extern cpuop_func op_4620_22_nf;
+extern cpuop_func op_4620_22_ff;
+extern cpuop_func op_4628_22_nf;
+extern cpuop_func op_4628_22_ff;
+extern cpuop_func op_4630_22_nf;
+extern cpuop_func op_4630_22_ff;
+extern cpuop_func op_4638_22_nf;
+extern cpuop_func op_4638_22_ff;
+extern cpuop_func op_4639_22_nf;
+extern cpuop_func op_4639_22_ff;
+extern cpuop_func op_4640_22_nf;
+extern cpuop_func op_4640_22_ff;
+extern cpuop_func op_4650_22_nf;
+extern cpuop_func op_4650_22_ff;
+extern cpuop_func op_4658_22_nf;
+extern cpuop_func op_4658_22_ff;
+extern cpuop_func op_4660_22_nf;
+extern cpuop_func op_4660_22_ff;
+extern cpuop_func op_4668_22_nf;
+extern cpuop_func op_4668_22_ff;
+extern cpuop_func op_4670_22_nf;
+extern cpuop_func op_4670_22_ff;
+extern cpuop_func op_4678_22_nf;
+extern cpuop_func op_4678_22_ff;
+extern cpuop_func op_4679_22_nf;
+extern cpuop_func op_4679_22_ff;
+extern cpuop_func op_4680_22_nf;
+extern cpuop_func op_4680_22_ff;
+extern cpuop_func op_4690_22_nf;
+extern cpuop_func op_4690_22_ff;
+extern cpuop_func op_4698_22_nf;
+extern cpuop_func op_4698_22_ff;
+extern cpuop_func op_46a0_22_nf;
+extern cpuop_func op_46a0_22_ff;
+extern cpuop_func op_46a8_22_nf;
+extern cpuop_func op_46a8_22_ff;
+extern cpuop_func op_46b0_22_nf;
+extern cpuop_func op_46b0_22_ff;
+extern cpuop_func op_46b8_22_nf;
+extern cpuop_func op_46b8_22_ff;
+extern cpuop_func op_46b9_22_nf;
+extern cpuop_func op_46b9_22_ff;
+extern cpuop_func op_46c0_22_nf;
+extern cpuop_func op_46c0_22_ff;
+extern cpuop_func op_46d0_22_nf;
+extern cpuop_func op_46d0_22_ff;
+extern cpuop_func op_46d8_22_nf;
+extern cpuop_func op_46d8_22_ff;
+extern cpuop_func op_46e0_22_nf;
+extern cpuop_func op_46e0_22_ff;
+extern cpuop_func op_46e8_22_nf;
+extern cpuop_func op_46e8_22_ff;
+extern cpuop_func op_46f0_22_nf;
+extern cpuop_func op_46f0_22_ff;
+extern cpuop_func op_46f8_22_nf;
+extern cpuop_func op_46f8_22_ff;
+extern cpuop_func op_46f9_22_nf;
+extern cpuop_func op_46f9_22_ff;
+extern cpuop_func op_46fa_22_nf;
+extern cpuop_func op_46fa_22_ff;
+extern cpuop_func op_46fb_22_nf;
+extern cpuop_func op_46fb_22_ff;
+extern cpuop_func op_46fc_22_nf;
+extern cpuop_func op_46fc_22_ff;
+extern cpuop_func op_4800_22_nf;
+extern cpuop_func op_4800_22_ff;
+extern cpuop_func op_4808_22_nf;
+extern cpuop_func op_4808_22_ff;
+extern cpuop_func op_4810_22_nf;
+extern cpuop_func op_4810_22_ff;
+extern cpuop_func op_4818_22_nf;
+extern cpuop_func op_4818_22_ff;
+extern cpuop_func op_4820_22_nf;
+extern cpuop_func op_4820_22_ff;
+extern cpuop_func op_4828_22_nf;
+extern cpuop_func op_4828_22_ff;
+extern cpuop_func op_4830_22_nf;
+extern cpuop_func op_4830_22_ff;
+extern cpuop_func op_4838_22_nf;
+extern cpuop_func op_4838_22_ff;
+extern cpuop_func op_4839_22_nf;
+extern cpuop_func op_4839_22_ff;
+extern cpuop_func op_4840_22_nf;
+extern cpuop_func op_4840_22_ff;
+extern cpuop_func op_4848_22_nf;
+extern cpuop_func op_4848_22_ff;
+extern cpuop_func op_4850_22_nf;
+extern cpuop_func op_4850_22_ff;
+extern cpuop_func op_4868_22_nf;
+extern cpuop_func op_4868_22_ff;
+extern cpuop_func op_4870_22_nf;
+extern cpuop_func op_4870_22_ff;
+extern cpuop_func op_4878_22_nf;
+extern cpuop_func op_4878_22_ff;
+extern cpuop_func op_4879_22_nf;
+extern cpuop_func op_4879_22_ff;
+extern cpuop_func op_487a_22_nf;
+extern cpuop_func op_487a_22_ff;
+extern cpuop_func op_487b_22_nf;
+extern cpuop_func op_487b_22_ff;
+extern cpuop_func op_4880_22_nf;
+extern cpuop_func op_4880_22_ff;
+extern cpuop_func op_4890_22_nf;
+extern cpuop_func op_4890_22_ff;
+extern cpuop_func op_48a0_22_nf;
+extern cpuop_func op_48a0_22_ff;
+extern cpuop_func op_48a8_22_nf;
+extern cpuop_func op_48a8_22_ff;
+extern cpuop_func op_48b0_22_nf;
+extern cpuop_func op_48b0_22_ff;
+extern cpuop_func op_48b8_22_nf;
+extern cpuop_func op_48b8_22_ff;
+extern cpuop_func op_48b9_22_nf;
+extern cpuop_func op_48b9_22_ff;
+extern cpuop_func op_48c0_22_nf;
+extern cpuop_func op_48c0_22_ff;
+extern cpuop_func op_48d0_22_nf;
+extern cpuop_func op_48d0_22_ff;
+extern cpuop_func op_48e0_22_nf;
+extern cpuop_func op_48e0_22_ff;
+extern cpuop_func op_48e8_22_nf;
+extern cpuop_func op_48e8_22_ff;
+extern cpuop_func op_48f0_22_nf;
+extern cpuop_func op_48f0_22_ff;
+extern cpuop_func op_48f8_22_nf;
+extern cpuop_func op_48f8_22_ff;
+extern cpuop_func op_48f9_22_nf;
+extern cpuop_func op_48f9_22_ff;
+extern cpuop_func op_49c0_22_nf;
+extern cpuop_func op_49c0_22_ff;
+extern cpuop_func op_4a00_22_nf;
+extern cpuop_func op_4a00_22_ff;
+extern cpuop_func op_4a10_22_nf;
+extern cpuop_func op_4a10_22_ff;
+extern cpuop_func op_4a18_22_nf;
+extern cpuop_func op_4a18_22_ff;
+extern cpuop_func op_4a20_22_nf;
+extern cpuop_func op_4a20_22_ff;
+extern cpuop_func op_4a28_22_nf;
+extern cpuop_func op_4a28_22_ff;
+extern cpuop_func op_4a30_22_nf;
+extern cpuop_func op_4a30_22_ff;
+extern cpuop_func op_4a38_22_nf;
+extern cpuop_func op_4a38_22_ff;
+extern cpuop_func op_4a39_22_nf;
+extern cpuop_func op_4a39_22_ff;
+extern cpuop_func op_4a3a_22_nf;
+extern cpuop_func op_4a3a_22_ff;
+extern cpuop_func op_4a3b_22_nf;
+extern cpuop_func op_4a3b_22_ff;
+extern cpuop_func op_4a3c_22_nf;
+extern cpuop_func op_4a3c_22_ff;
+extern cpuop_func op_4a40_22_nf;
+extern cpuop_func op_4a40_22_ff;
+extern cpuop_func op_4a48_22_nf;
+extern cpuop_func op_4a48_22_ff;
+extern cpuop_func op_4a50_22_nf;
+extern cpuop_func op_4a50_22_ff;
+extern cpuop_func op_4a58_22_nf;
+extern cpuop_func op_4a58_22_ff;
+extern cpuop_func op_4a60_22_nf;
+extern cpuop_func op_4a60_22_ff;
+extern cpuop_func op_4a68_22_nf;
+extern cpuop_func op_4a68_22_ff;
+extern cpuop_func op_4a70_22_nf;
+extern cpuop_func op_4a70_22_ff;
+extern cpuop_func op_4a78_22_nf;
+extern cpuop_func op_4a78_22_ff;
+extern cpuop_func op_4a79_22_nf;
+extern cpuop_func op_4a79_22_ff;
+extern cpuop_func op_4a7a_22_nf;
+extern cpuop_func op_4a7a_22_ff;
+extern cpuop_func op_4a7b_22_nf;
+extern cpuop_func op_4a7b_22_ff;
+extern cpuop_func op_4a7c_22_nf;
+extern cpuop_func op_4a7c_22_ff;
+extern cpuop_func op_4a80_22_nf;
+extern cpuop_func op_4a80_22_ff;
+extern cpuop_func op_4a88_22_nf;
+extern cpuop_func op_4a88_22_ff;
+extern cpuop_func op_4a90_22_nf;
+extern cpuop_func op_4a90_22_ff;
+extern cpuop_func op_4a98_22_nf;
+extern cpuop_func op_4a98_22_ff;
+extern cpuop_func op_4aa0_22_nf;
+extern cpuop_func op_4aa0_22_ff;
+extern cpuop_func op_4aa8_22_nf;
+extern cpuop_func op_4aa8_22_ff;
+extern cpuop_func op_4ab0_22_nf;
+extern cpuop_func op_4ab0_22_ff;
+extern cpuop_func op_4ab8_22_nf;
+extern cpuop_func op_4ab8_22_ff;
+extern cpuop_func op_4ab9_22_nf;
+extern cpuop_func op_4ab9_22_ff;
+extern cpuop_func op_4aba_22_nf;
+extern cpuop_func op_4aba_22_ff;
+extern cpuop_func op_4abb_22_nf;
+extern cpuop_func op_4abb_22_ff;
+extern cpuop_func op_4abc_22_nf;
+extern cpuop_func op_4abc_22_ff;
+extern cpuop_func op_4ac0_22_nf;
+extern cpuop_func op_4ac0_22_ff;
+extern cpuop_func op_4ad0_22_nf;
+extern cpuop_func op_4ad0_22_ff;
+extern cpuop_func op_4ad8_22_nf;
+extern cpuop_func op_4ad8_22_ff;
+extern cpuop_func op_4ae0_22_nf;
+extern cpuop_func op_4ae0_22_ff;
+extern cpuop_func op_4ae8_22_nf;
+extern cpuop_func op_4ae8_22_ff;
+extern cpuop_func op_4af0_22_nf;
+extern cpuop_func op_4af0_22_ff;
+extern cpuop_func op_4af8_22_nf;
+extern cpuop_func op_4af8_22_ff;
+extern cpuop_func op_4af9_22_nf;
+extern cpuop_func op_4af9_22_ff;
+extern cpuop_func op_4c00_22_nf;
+extern cpuop_func op_4c00_22_ff;
+extern cpuop_func op_4c10_22_nf;
+extern cpuop_func op_4c10_22_ff;
+extern cpuop_func op_4c18_22_nf;
+extern cpuop_func op_4c18_22_ff;
+extern cpuop_func op_4c20_22_nf;
+extern cpuop_func op_4c20_22_ff;
+extern cpuop_func op_4c28_22_nf;
+extern cpuop_func op_4c28_22_ff;
+extern cpuop_func op_4c30_22_nf;
+extern cpuop_func op_4c30_22_ff;
+extern cpuop_func op_4c38_22_nf;
+extern cpuop_func op_4c38_22_ff;
+extern cpuop_func op_4c39_22_nf;
+extern cpuop_func op_4c39_22_ff;
+extern cpuop_func op_4c3a_22_nf;
+extern cpuop_func op_4c3a_22_ff;
+extern cpuop_func op_4c3b_22_nf;
+extern cpuop_func op_4c3b_22_ff;
+extern cpuop_func op_4c3c_22_nf;
+extern cpuop_func op_4c3c_22_ff;
+extern cpuop_func op_4c40_22_nf;
+extern cpuop_func op_4c40_22_ff;
+extern cpuop_func op_4c50_22_nf;
+extern cpuop_func op_4c50_22_ff;
+extern cpuop_func op_4c58_22_nf;
+extern cpuop_func op_4c58_22_ff;
+extern cpuop_func op_4c60_22_nf;
+extern cpuop_func op_4c60_22_ff;
+extern cpuop_func op_4c68_22_nf;
+extern cpuop_func op_4c68_22_ff;
+extern cpuop_func op_4c70_22_nf;
+extern cpuop_func op_4c70_22_ff;
+extern cpuop_func op_4c78_22_nf;
+extern cpuop_func op_4c78_22_ff;
+extern cpuop_func op_4c79_22_nf;
+extern cpuop_func op_4c79_22_ff;
+extern cpuop_func op_4c7a_22_nf;
+extern cpuop_func op_4c7a_22_ff;
+extern cpuop_func op_4c7b_22_nf;
+extern cpuop_func op_4c7b_22_ff;
+extern cpuop_func op_4c7c_22_nf;
+extern cpuop_func op_4c7c_22_ff;
+extern cpuop_func op_4c90_22_nf;
+extern cpuop_func op_4c90_22_ff;
+extern cpuop_func op_4c98_22_nf;
+extern cpuop_func op_4c98_22_ff;
+extern cpuop_func op_4ca8_22_nf;
+extern cpuop_func op_4ca8_22_ff;
+extern cpuop_func op_4cb0_22_nf;
+extern cpuop_func op_4cb0_22_ff;
+extern cpuop_func op_4cb8_22_nf;
+extern cpuop_func op_4cb8_22_ff;
+extern cpuop_func op_4cb9_22_nf;
+extern cpuop_func op_4cb9_22_ff;
+extern cpuop_func op_4cba_22_nf;
+extern cpuop_func op_4cba_22_ff;
+extern cpuop_func op_4cbb_22_nf;
+extern cpuop_func op_4cbb_22_ff;
+extern cpuop_func op_4cd0_22_nf;
+extern cpuop_func op_4cd0_22_ff;
+extern cpuop_func op_4cd8_22_nf;
+extern cpuop_func op_4cd8_22_ff;
+extern cpuop_func op_4ce8_22_nf;
+extern cpuop_func op_4ce8_22_ff;
+extern cpuop_func op_4cf0_22_nf;
+extern cpuop_func op_4cf0_22_ff;
+extern cpuop_func op_4cf8_22_nf;
+extern cpuop_func op_4cf8_22_ff;
+extern cpuop_func op_4cf9_22_nf;
+extern cpuop_func op_4cf9_22_ff;
+extern cpuop_func op_4cfa_22_nf;
+extern cpuop_func op_4cfa_22_ff;
+extern cpuop_func op_4cfb_22_nf;
+extern cpuop_func op_4cfb_22_ff;
+extern cpuop_func op_4e40_22_nf;
+extern cpuop_func op_4e40_22_ff;
+extern cpuop_func op_4e50_22_nf;
+extern cpuop_func op_4e50_22_ff;
+extern cpuop_func op_4e58_22_nf;
+extern cpuop_func op_4e58_22_ff;
+extern cpuop_func op_4e60_22_nf;
+extern cpuop_func op_4e60_22_ff;
+extern cpuop_func op_4e68_22_nf;
+extern cpuop_func op_4e68_22_ff;
+extern cpuop_func op_4e70_22_nf;
+extern cpuop_func op_4e70_22_ff;
+extern cpuop_func op_4e71_22_nf;
+extern cpuop_func op_4e71_22_ff;
+extern cpuop_func op_4e72_22_nf;
+extern cpuop_func op_4e72_22_ff;
+extern cpuop_func op_4e73_22_nf;
+extern cpuop_func op_4e73_22_ff;
+extern cpuop_func op_4e74_22_nf;
+extern cpuop_func op_4e74_22_ff;
+extern cpuop_func op_4e75_22_nf;
+extern cpuop_func op_4e75_22_ff;
+extern cpuop_func op_4e76_22_nf;
+extern cpuop_func op_4e76_22_ff;
+extern cpuop_func op_4e77_22_nf;
+extern cpuop_func op_4e77_22_ff;
+extern cpuop_func op_4e7a_22_nf;
+extern cpuop_func op_4e7a_22_ff;
+extern cpuop_func op_4e7b_22_nf;
+extern cpuop_func op_4e7b_22_ff;
+extern cpuop_func op_4e90_22_nf;
+extern cpuop_func op_4e90_22_ff;
+extern cpuop_func op_4ea8_22_nf;
+extern cpuop_func op_4ea8_22_ff;
+extern cpuop_func op_4eb0_22_nf;
+extern cpuop_func op_4eb0_22_ff;
+extern cpuop_func op_4eb8_22_nf;
+extern cpuop_func op_4eb8_22_ff;
+extern cpuop_func op_4eb9_22_nf;
+extern cpuop_func op_4eb9_22_ff;
+extern cpuop_func op_4eba_22_nf;
+extern cpuop_func op_4eba_22_ff;
+extern cpuop_func op_4ebb_22_nf;
+extern cpuop_func op_4ebb_22_ff;
+extern cpuop_func op_4ed0_22_nf;
+extern cpuop_func op_4ed0_22_ff;
+extern cpuop_func op_4ee8_22_nf;
+extern cpuop_func op_4ee8_22_ff;
+extern cpuop_func op_4ef0_22_nf;
+extern cpuop_func op_4ef0_22_ff;
+extern cpuop_func op_4ef8_22_nf;
+extern cpuop_func op_4ef8_22_ff;
+extern cpuop_func op_4ef9_22_nf;
+extern cpuop_func op_4ef9_22_ff;
+extern cpuop_func op_4efa_22_nf;
+extern cpuop_func op_4efa_22_ff;
+extern cpuop_func op_4efb_22_nf;
+extern cpuop_func op_4efb_22_ff;
+extern cpuop_func op_5000_22_nf;
+extern cpuop_func op_5000_22_ff;
+extern cpuop_func op_5010_22_nf;
+extern cpuop_func op_5010_22_ff;
+extern cpuop_func op_5018_22_nf;
+extern cpuop_func op_5018_22_ff;
+extern cpuop_func op_5020_22_nf;
+extern cpuop_func op_5020_22_ff;
+extern cpuop_func op_5028_22_nf;
+extern cpuop_func op_5028_22_ff;
+extern cpuop_func op_5030_22_nf;
+extern cpuop_func op_5030_22_ff;
+extern cpuop_func op_5038_22_nf;
+extern cpuop_func op_5038_22_ff;
+extern cpuop_func op_5039_22_nf;
+extern cpuop_func op_5039_22_ff;
+extern cpuop_func op_5040_22_nf;
+extern cpuop_func op_5040_22_ff;
+extern cpuop_func op_5048_22_nf;
+extern cpuop_func op_5048_22_ff;
+extern cpuop_func op_5050_22_nf;
+extern cpuop_func op_5050_22_ff;
+extern cpuop_func op_5058_22_nf;
+extern cpuop_func op_5058_22_ff;
+extern cpuop_func op_5060_22_nf;
+extern cpuop_func op_5060_22_ff;
+extern cpuop_func op_5068_22_nf;
+extern cpuop_func op_5068_22_ff;
+extern cpuop_func op_5070_22_nf;
+extern cpuop_func op_5070_22_ff;
+extern cpuop_func op_5078_22_nf;
+extern cpuop_func op_5078_22_ff;
+extern cpuop_func op_5079_22_nf;
+extern cpuop_func op_5079_22_ff;
+extern cpuop_func op_5080_22_nf;
+extern cpuop_func op_5080_22_ff;
+extern cpuop_func op_5088_22_nf;
+extern cpuop_func op_5088_22_ff;
+extern cpuop_func op_5090_22_nf;
+extern cpuop_func op_5090_22_ff;
+extern cpuop_func op_5098_22_nf;
+extern cpuop_func op_5098_22_ff;
+extern cpuop_func op_50a0_22_nf;
+extern cpuop_func op_50a0_22_ff;
+extern cpuop_func op_50a8_22_nf;
+extern cpuop_func op_50a8_22_ff;
+extern cpuop_func op_50b0_22_nf;
+extern cpuop_func op_50b0_22_ff;
+extern cpuop_func op_50b8_22_nf;
+extern cpuop_func op_50b8_22_ff;
+extern cpuop_func op_50b9_22_nf;
+extern cpuop_func op_50b9_22_ff;
+extern cpuop_func op_50c0_22_nf;
+extern cpuop_func op_50c0_22_ff;
+extern cpuop_func op_50c8_22_nf;
+extern cpuop_func op_50c8_22_ff;
+extern cpuop_func op_50d0_22_nf;
+extern cpuop_func op_50d0_22_ff;
+extern cpuop_func op_50d8_22_nf;
+extern cpuop_func op_50d8_22_ff;
+extern cpuop_func op_50e0_22_nf;
+extern cpuop_func op_50e0_22_ff;
+extern cpuop_func op_50e8_22_nf;
+extern cpuop_func op_50e8_22_ff;
+extern cpuop_func op_50f0_22_nf;
+extern cpuop_func op_50f0_22_ff;
+extern cpuop_func op_50f8_22_nf;
+extern cpuop_func op_50f8_22_ff;
+extern cpuop_func op_50f9_22_nf;
+extern cpuop_func op_50f9_22_ff;
+extern cpuop_func op_50fa_22_nf;
+extern cpuop_func op_50fa_22_ff;
+extern cpuop_func op_50fb_22_nf;
+extern cpuop_func op_50fb_22_ff;
+extern cpuop_func op_50fc_22_nf;
+extern cpuop_func op_50fc_22_ff;
+extern cpuop_func op_5100_22_nf;
+extern cpuop_func op_5100_22_ff;
+extern cpuop_func op_5110_22_nf;
+extern cpuop_func op_5110_22_ff;
+extern cpuop_func op_5118_22_nf;
+extern cpuop_func op_5118_22_ff;
+extern cpuop_func op_5120_22_nf;
+extern cpuop_func op_5120_22_ff;
+extern cpuop_func op_5128_22_nf;
+extern cpuop_func op_5128_22_ff;
+extern cpuop_func op_5130_22_nf;
+extern cpuop_func op_5130_22_ff;
+extern cpuop_func op_5138_22_nf;
+extern cpuop_func op_5138_22_ff;
+extern cpuop_func op_5139_22_nf;
+extern cpuop_func op_5139_22_ff;
+extern cpuop_func op_5140_22_nf;
+extern cpuop_func op_5140_22_ff;
+extern cpuop_func op_5148_22_nf;
+extern cpuop_func op_5148_22_ff;
+extern cpuop_func op_5150_22_nf;
+extern cpuop_func op_5150_22_ff;
+extern cpuop_func op_5158_22_nf;
+extern cpuop_func op_5158_22_ff;
+extern cpuop_func op_5160_22_nf;
+extern cpuop_func op_5160_22_ff;
+extern cpuop_func op_5168_22_nf;
+extern cpuop_func op_5168_22_ff;
+extern cpuop_func op_5170_22_nf;
+extern cpuop_func op_5170_22_ff;
+extern cpuop_func op_5178_22_nf;
+extern cpuop_func op_5178_22_ff;
+extern cpuop_func op_5179_22_nf;
+extern cpuop_func op_5179_22_ff;
+extern cpuop_func op_5180_22_nf;
+extern cpuop_func op_5180_22_ff;
+extern cpuop_func op_5188_22_nf;
+extern cpuop_func op_5188_22_ff;
+extern cpuop_func op_5190_22_nf;
+extern cpuop_func op_5190_22_ff;
+extern cpuop_func op_5198_22_nf;
+extern cpuop_func op_5198_22_ff;
+extern cpuop_func op_51a0_22_nf;
+extern cpuop_func op_51a0_22_ff;
+extern cpuop_func op_51a8_22_nf;
+extern cpuop_func op_51a8_22_ff;
+extern cpuop_func op_51b0_22_nf;
+extern cpuop_func op_51b0_22_ff;
+extern cpuop_func op_51b8_22_nf;
+extern cpuop_func op_51b8_22_ff;
+extern cpuop_func op_51b9_22_nf;
+extern cpuop_func op_51b9_22_ff;
+extern cpuop_func op_51c0_22_nf;
+extern cpuop_func op_51c0_22_ff;
+extern cpuop_func op_51c8_22_nf;
+extern cpuop_func op_51c8_22_ff;
+extern cpuop_func op_51d0_22_nf;
+extern cpuop_func op_51d0_22_ff;
+extern cpuop_func op_51d8_22_nf;
+extern cpuop_func op_51d8_22_ff;
+extern cpuop_func op_51e0_22_nf;
+extern cpuop_func op_51e0_22_ff;
+extern cpuop_func op_51e8_22_nf;
+extern cpuop_func op_51e8_22_ff;
+extern cpuop_func op_51f0_22_nf;
+extern cpuop_func op_51f0_22_ff;
+extern cpuop_func op_51f8_22_nf;
+extern cpuop_func op_51f8_22_ff;
+extern cpuop_func op_51f9_22_nf;
+extern cpuop_func op_51f9_22_ff;
+extern cpuop_func op_51fa_22_nf;
+extern cpuop_func op_51fa_22_ff;
+extern cpuop_func op_51fb_22_nf;
+extern cpuop_func op_51fb_22_ff;
+extern cpuop_func op_51fc_22_nf;
+extern cpuop_func op_51fc_22_ff;
+extern cpuop_func op_52c0_22_nf;
+extern cpuop_func op_52c0_22_ff;
+extern cpuop_func op_52c8_22_nf;
+extern cpuop_func op_52c8_22_ff;
+extern cpuop_func op_52d0_22_nf;
+extern cpuop_func op_52d0_22_ff;
+extern cpuop_func op_52d8_22_nf;
+extern cpuop_func op_52d8_22_ff;
+extern cpuop_func op_52e0_22_nf;
+extern cpuop_func op_52e0_22_ff;
+extern cpuop_func op_52e8_22_nf;
+extern cpuop_func op_52e8_22_ff;
+extern cpuop_func op_52f0_22_nf;
+extern cpuop_func op_52f0_22_ff;
+extern cpuop_func op_52f8_22_nf;
+extern cpuop_func op_52f8_22_ff;
+extern cpuop_func op_52f9_22_nf;
+extern cpuop_func op_52f9_22_ff;
+extern cpuop_func op_52fa_22_nf;
+extern cpuop_func op_52fa_22_ff;
+extern cpuop_func op_52fb_22_nf;
+extern cpuop_func op_52fb_22_ff;
+extern cpuop_func op_52fc_22_nf;
+extern cpuop_func op_52fc_22_ff;
+extern cpuop_func op_53c0_22_nf;
+extern cpuop_func op_53c0_22_ff;
+extern cpuop_func op_53c8_22_nf;
+extern cpuop_func op_53c8_22_ff;
+extern cpuop_func op_53d0_22_nf;
+extern cpuop_func op_53d0_22_ff;
+extern cpuop_func op_53d8_22_nf;
+extern cpuop_func op_53d8_22_ff;
+extern cpuop_func op_53e0_22_nf;
+extern cpuop_func op_53e0_22_ff;
+extern cpuop_func op_53e8_22_nf;
+extern cpuop_func op_53e8_22_ff;
+extern cpuop_func op_53f0_22_nf;
+extern cpuop_func op_53f0_22_ff;
+extern cpuop_func op_53f8_22_nf;
+extern cpuop_func op_53f8_22_ff;
+extern cpuop_func op_53f9_22_nf;
+extern cpuop_func op_53f9_22_ff;
+extern cpuop_func op_53fa_22_nf;
+extern cpuop_func op_53fa_22_ff;
+extern cpuop_func op_53fb_22_nf;
+extern cpuop_func op_53fb_22_ff;
+extern cpuop_func op_53fc_22_nf;
+extern cpuop_func op_53fc_22_ff;
+extern cpuop_func op_54c0_22_nf;
+extern cpuop_func op_54c0_22_ff;
+extern cpuop_func op_54c8_22_nf;
+extern cpuop_func op_54c8_22_ff;
+extern cpuop_func op_54d0_22_nf;
+extern cpuop_func op_54d0_22_ff;
+extern cpuop_func op_54d8_22_nf;
+extern cpuop_func op_54d8_22_ff;
+extern cpuop_func op_54e0_22_nf;
+extern cpuop_func op_54e0_22_ff;
+extern cpuop_func op_54e8_22_nf;
+extern cpuop_func op_54e8_22_ff;
+extern cpuop_func op_54f0_22_nf;
+extern cpuop_func op_54f0_22_ff;
+extern cpuop_func op_54f8_22_nf;
+extern cpuop_func op_54f8_22_ff;
+extern cpuop_func op_54f9_22_nf;
+extern cpuop_func op_54f9_22_ff;
+extern cpuop_func op_54fa_22_nf;
+extern cpuop_func op_54fa_22_ff;
+extern cpuop_func op_54fb_22_nf;
+extern cpuop_func op_54fb_22_ff;
+extern cpuop_func op_54fc_22_nf;
+extern cpuop_func op_54fc_22_ff;
+extern cpuop_func op_55c0_22_nf;
+extern cpuop_func op_55c0_22_ff;
+extern cpuop_func op_55c8_22_nf;
+extern cpuop_func op_55c8_22_ff;
+extern cpuop_func op_55d0_22_nf;
+extern cpuop_func op_55d0_22_ff;
+extern cpuop_func op_55d8_22_nf;
+extern cpuop_func op_55d8_22_ff;
+extern cpuop_func op_55e0_22_nf;
+extern cpuop_func op_55e0_22_ff;
+extern cpuop_func op_55e8_22_nf;
+extern cpuop_func op_55e8_22_ff;
+extern cpuop_func op_55f0_22_nf;
+extern cpuop_func op_55f0_22_ff;
+extern cpuop_func op_55f8_22_nf;
+extern cpuop_func op_55f8_22_ff;
+extern cpuop_func op_55f9_22_nf;
+extern cpuop_func op_55f9_22_ff;
+extern cpuop_func op_55fa_22_nf;
+extern cpuop_func op_55fa_22_ff;
+extern cpuop_func op_55fb_22_nf;
+extern cpuop_func op_55fb_22_ff;
+extern cpuop_func op_55fc_22_nf;
+extern cpuop_func op_55fc_22_ff;
+extern cpuop_func op_56c0_22_nf;
+extern cpuop_func op_56c0_22_ff;
+extern cpuop_func op_56c8_22_nf;
+extern cpuop_func op_56c8_22_ff;
+extern cpuop_func op_56d0_22_nf;
+extern cpuop_func op_56d0_22_ff;
+extern cpuop_func op_56d8_22_nf;
+extern cpuop_func op_56d8_22_ff;
+extern cpuop_func op_56e0_22_nf;
+extern cpuop_func op_56e0_22_ff;
+extern cpuop_func op_56e8_22_nf;
+extern cpuop_func op_56e8_22_ff;
+extern cpuop_func op_56f0_22_nf;
+extern cpuop_func op_56f0_22_ff;
+extern cpuop_func op_56f8_22_nf;
+extern cpuop_func op_56f8_22_ff;
+extern cpuop_func op_56f9_22_nf;
+extern cpuop_func op_56f9_22_ff;
+extern cpuop_func op_56fa_22_nf;
+extern cpuop_func op_56fa_22_ff;
+extern cpuop_func op_56fb_22_nf;
+extern cpuop_func op_56fb_22_ff;
+extern cpuop_func op_56fc_22_nf;
+extern cpuop_func op_56fc_22_ff;
+extern cpuop_func op_57c0_22_nf;
+extern cpuop_func op_57c0_22_ff;
+extern cpuop_func op_57c8_22_nf;
+extern cpuop_func op_57c8_22_ff;
+extern cpuop_func op_57d0_22_nf;
+extern cpuop_func op_57d0_22_ff;
+extern cpuop_func op_57d8_22_nf;
+extern cpuop_func op_57d8_22_ff;
+extern cpuop_func op_57e0_22_nf;
+extern cpuop_func op_57e0_22_ff;
+extern cpuop_func op_57e8_22_nf;
+extern cpuop_func op_57e8_22_ff;
+extern cpuop_func op_57f0_22_nf;
+extern cpuop_func op_57f0_22_ff;
+extern cpuop_func op_57f8_22_nf;
+extern cpuop_func op_57f8_22_ff;
+extern cpuop_func op_57f9_22_nf;
+extern cpuop_func op_57f9_22_ff;
+extern cpuop_func op_57fa_22_nf;
+extern cpuop_func op_57fa_22_ff;
+extern cpuop_func op_57fb_22_nf;
+extern cpuop_func op_57fb_22_ff;
+extern cpuop_func op_57fc_22_nf;
+extern cpuop_func op_57fc_22_ff;
+extern cpuop_func op_58c0_22_nf;
+extern cpuop_func op_58c0_22_ff;
+extern cpuop_func op_58c8_22_nf;
+extern cpuop_func op_58c8_22_ff;
+extern cpuop_func op_58d0_22_nf;
+extern cpuop_func op_58d0_22_ff;
+extern cpuop_func op_58d8_22_nf;
+extern cpuop_func op_58d8_22_ff;
+extern cpuop_func op_58e0_22_nf;
+extern cpuop_func op_58e0_22_ff;
+extern cpuop_func op_58e8_22_nf;
+extern cpuop_func op_58e8_22_ff;
+extern cpuop_func op_58f0_22_nf;
+extern cpuop_func op_58f0_22_ff;
+extern cpuop_func op_58f8_22_nf;
+extern cpuop_func op_58f8_22_ff;
+extern cpuop_func op_58f9_22_nf;
+extern cpuop_func op_58f9_22_ff;
+extern cpuop_func op_58fa_22_nf;
+extern cpuop_func op_58fa_22_ff;
+extern cpuop_func op_58fb_22_nf;
+extern cpuop_func op_58fb_22_ff;
+extern cpuop_func op_58fc_22_nf;
+extern cpuop_func op_58fc_22_ff;
+extern cpuop_func op_59c0_22_nf;
+extern cpuop_func op_59c0_22_ff;
+extern cpuop_func op_59c8_22_nf;
+extern cpuop_func op_59c8_22_ff;
+extern cpuop_func op_59d0_22_nf;
+extern cpuop_func op_59d0_22_ff;
+extern cpuop_func op_59d8_22_nf;
+extern cpuop_func op_59d8_22_ff;
+extern cpuop_func op_59e0_22_nf;
+extern cpuop_func op_59e0_22_ff;
+extern cpuop_func op_59e8_22_nf;
+extern cpuop_func op_59e8_22_ff;
+extern cpuop_func op_59f0_22_nf;
+extern cpuop_func op_59f0_22_ff;
+extern cpuop_func op_59f8_22_nf;
+extern cpuop_func op_59f8_22_ff;
+extern cpuop_func op_59f9_22_nf;
+extern cpuop_func op_59f9_22_ff;
+extern cpuop_func op_59fa_22_nf;
+extern cpuop_func op_59fa_22_ff;
+extern cpuop_func op_59fb_22_nf;
+extern cpuop_func op_59fb_22_ff;
+extern cpuop_func op_59fc_22_nf;
+extern cpuop_func op_59fc_22_ff;
+extern cpuop_func op_5ac0_22_nf;
+extern cpuop_func op_5ac0_22_ff;
+extern cpuop_func op_5ac8_22_nf;
+extern cpuop_func op_5ac8_22_ff;
+extern cpuop_func op_5ad0_22_nf;
+extern cpuop_func op_5ad0_22_ff;
+extern cpuop_func op_5ad8_22_nf;
+extern cpuop_func op_5ad8_22_ff;
+extern cpuop_func op_5ae0_22_nf;
+extern cpuop_func op_5ae0_22_ff;
+extern cpuop_func op_5ae8_22_nf;
+extern cpuop_func op_5ae8_22_ff;
+extern cpuop_func op_5af0_22_nf;
+extern cpuop_func op_5af0_22_ff;
+extern cpuop_func op_5af8_22_nf;
+extern cpuop_func op_5af8_22_ff;
+extern cpuop_func op_5af9_22_nf;
+extern cpuop_func op_5af9_22_ff;
+extern cpuop_func op_5afa_22_nf;
+extern cpuop_func op_5afa_22_ff;
+extern cpuop_func op_5afb_22_nf;
+extern cpuop_func op_5afb_22_ff;
+extern cpuop_func op_5afc_22_nf;
+extern cpuop_func op_5afc_22_ff;
+extern cpuop_func op_5bc0_22_nf;
+extern cpuop_func op_5bc0_22_ff;
+extern cpuop_func op_5bc8_22_nf;
+extern cpuop_func op_5bc8_22_ff;
+extern cpuop_func op_5bd0_22_nf;
+extern cpuop_func op_5bd0_22_ff;
+extern cpuop_func op_5bd8_22_nf;
+extern cpuop_func op_5bd8_22_ff;
+extern cpuop_func op_5be0_22_nf;
+extern cpuop_func op_5be0_22_ff;
+extern cpuop_func op_5be8_22_nf;
+extern cpuop_func op_5be8_22_ff;
+extern cpuop_func op_5bf0_22_nf;
+extern cpuop_func op_5bf0_22_ff;
+extern cpuop_func op_5bf8_22_nf;
+extern cpuop_func op_5bf8_22_ff;
+extern cpuop_func op_5bf9_22_nf;
+extern cpuop_func op_5bf9_22_ff;
+extern cpuop_func op_5bfa_22_nf;
+extern cpuop_func op_5bfa_22_ff;
+extern cpuop_func op_5bfb_22_nf;
+extern cpuop_func op_5bfb_22_ff;
+extern cpuop_func op_5bfc_22_nf;
+extern cpuop_func op_5bfc_22_ff;
+extern cpuop_func op_5cc0_22_nf;
+extern cpuop_func op_5cc0_22_ff;
+extern cpuop_func op_5cc8_22_nf;
+extern cpuop_func op_5cc8_22_ff;
+extern cpuop_func op_5cd0_22_nf;
+extern cpuop_func op_5cd0_22_ff;
+extern cpuop_func op_5cd8_22_nf;
+extern cpuop_func op_5cd8_22_ff;
+extern cpuop_func op_5ce0_22_nf;
+extern cpuop_func op_5ce0_22_ff;
+extern cpuop_func op_5ce8_22_nf;
+extern cpuop_func op_5ce8_22_ff;
+extern cpuop_func op_5cf0_22_nf;
+extern cpuop_func op_5cf0_22_ff;
+extern cpuop_func op_5cf8_22_nf;
+extern cpuop_func op_5cf8_22_ff;
+extern cpuop_func op_5cf9_22_nf;
+extern cpuop_func op_5cf9_22_ff;
+extern cpuop_func op_5cfa_22_nf;
+extern cpuop_func op_5cfa_22_ff;
+extern cpuop_func op_5cfb_22_nf;
+extern cpuop_func op_5cfb_22_ff;
+extern cpuop_func op_5cfc_22_nf;
+extern cpuop_func op_5cfc_22_ff;
+extern cpuop_func op_5dc0_22_nf;
+extern cpuop_func op_5dc0_22_ff;
+extern cpuop_func op_5dc8_22_nf;
+extern cpuop_func op_5dc8_22_ff;
+extern cpuop_func op_5dd0_22_nf;
+extern cpuop_func op_5dd0_22_ff;
+extern cpuop_func op_5dd8_22_nf;
+extern cpuop_func op_5dd8_22_ff;
+extern cpuop_func op_5de0_22_nf;
+extern cpuop_func op_5de0_22_ff;
+extern cpuop_func op_5de8_22_nf;
+extern cpuop_func op_5de8_22_ff;
+extern cpuop_func op_5df0_22_nf;
+extern cpuop_func op_5df0_22_ff;
+extern cpuop_func op_5df8_22_nf;
+extern cpuop_func op_5df8_22_ff;
+extern cpuop_func op_5df9_22_nf;
+extern cpuop_func op_5df9_22_ff;
+extern cpuop_func op_5dfa_22_nf;
+extern cpuop_func op_5dfa_22_ff;
+extern cpuop_func op_5dfb_22_nf;
+extern cpuop_func op_5dfb_22_ff;
+extern cpuop_func op_5dfc_22_nf;
+extern cpuop_func op_5dfc_22_ff;
+extern cpuop_func op_5ec0_22_nf;
+extern cpuop_func op_5ec0_22_ff;
+extern cpuop_func op_5ec8_22_nf;
+extern cpuop_func op_5ec8_22_ff;
+extern cpuop_func op_5ed0_22_nf;
+extern cpuop_func op_5ed0_22_ff;
+extern cpuop_func op_5ed8_22_nf;
+extern cpuop_func op_5ed8_22_ff;
+extern cpuop_func op_5ee0_22_nf;
+extern cpuop_func op_5ee0_22_ff;
+extern cpuop_func op_5ee8_22_nf;
+extern cpuop_func op_5ee8_22_ff;
+extern cpuop_func op_5ef0_22_nf;
+extern cpuop_func op_5ef0_22_ff;
+extern cpuop_func op_5ef8_22_nf;
+extern cpuop_func op_5ef8_22_ff;
+extern cpuop_func op_5ef9_22_nf;
+extern cpuop_func op_5ef9_22_ff;
+extern cpuop_func op_5efa_22_nf;
+extern cpuop_func op_5efa_22_ff;
+extern cpuop_func op_5efb_22_nf;
+extern cpuop_func op_5efb_22_ff;
+extern cpuop_func op_5efc_22_nf;
+extern cpuop_func op_5efc_22_ff;
+extern cpuop_func op_5fc0_22_nf;
+extern cpuop_func op_5fc0_22_ff;
+extern cpuop_func op_5fc8_22_nf;
+extern cpuop_func op_5fc8_22_ff;
+extern cpuop_func op_5fd0_22_nf;
+extern cpuop_func op_5fd0_22_ff;
+extern cpuop_func op_5fd8_22_nf;
+extern cpuop_func op_5fd8_22_ff;
+extern cpuop_func op_5fe0_22_nf;
+extern cpuop_func op_5fe0_22_ff;
+extern cpuop_func op_5fe8_22_nf;
+extern cpuop_func op_5fe8_22_ff;
+extern cpuop_func op_5ff0_22_nf;
+extern cpuop_func op_5ff0_22_ff;
+extern cpuop_func op_5ff8_22_nf;
+extern cpuop_func op_5ff8_22_ff;
+extern cpuop_func op_5ff9_22_nf;
+extern cpuop_func op_5ff9_22_ff;
+extern cpuop_func op_5ffa_22_nf;
+extern cpuop_func op_5ffa_22_ff;
+extern cpuop_func op_5ffb_22_nf;
+extern cpuop_func op_5ffb_22_ff;
+extern cpuop_func op_5ffc_22_nf;
+extern cpuop_func op_5ffc_22_ff;
+extern cpuop_func op_6000_22_nf;
+extern cpuop_func op_6000_22_ff;
+extern cpuop_func op_6001_22_nf;
+extern cpuop_func op_6001_22_ff;
+extern cpuop_func op_60ff_22_nf;
+extern cpuop_func op_60ff_22_ff;
+extern cpuop_func op_6100_22_nf;
+extern cpuop_func op_6100_22_ff;
+extern cpuop_func op_6101_22_nf;
+extern cpuop_func op_6101_22_ff;
+extern cpuop_func op_61ff_22_nf;
+extern cpuop_func op_61ff_22_ff;
+extern cpuop_func op_6200_22_nf;
+extern cpuop_func op_6200_22_ff;
+extern cpuop_func op_6201_22_nf;
+extern cpuop_func op_6201_22_ff;
+extern cpuop_func op_62ff_22_nf;
+extern cpuop_func op_62ff_22_ff;
+extern cpuop_func op_6300_22_nf;
+extern cpuop_func op_6300_22_ff;
+extern cpuop_func op_6301_22_nf;
+extern cpuop_func op_6301_22_ff;
+extern cpuop_func op_63ff_22_nf;
+extern cpuop_func op_63ff_22_ff;
+extern cpuop_func op_6400_22_nf;
+extern cpuop_func op_6400_22_ff;
+extern cpuop_func op_6401_22_nf;
+extern cpuop_func op_6401_22_ff;
+extern cpuop_func op_64ff_22_nf;
+extern cpuop_func op_64ff_22_ff;
+extern cpuop_func op_6500_22_nf;
+extern cpuop_func op_6500_22_ff;
+extern cpuop_func op_6501_22_nf;
+extern cpuop_func op_6501_22_ff;
+extern cpuop_func op_65ff_22_nf;
+extern cpuop_func op_65ff_22_ff;
+extern cpuop_func op_6600_22_nf;
+extern cpuop_func op_6600_22_ff;
+extern cpuop_func op_6601_22_nf;
+extern cpuop_func op_6601_22_ff;
+extern cpuop_func op_66ff_22_nf;
+extern cpuop_func op_66ff_22_ff;
+extern cpuop_func op_6700_22_nf;
+extern cpuop_func op_6700_22_ff;
+extern cpuop_func op_6701_22_nf;
+extern cpuop_func op_6701_22_ff;
+extern cpuop_func op_67ff_22_nf;
+extern cpuop_func op_67ff_22_ff;
+extern cpuop_func op_6800_22_nf;
+extern cpuop_func op_6800_22_ff;
+extern cpuop_func op_6801_22_nf;
+extern cpuop_func op_6801_22_ff;
+extern cpuop_func op_68ff_22_nf;
+extern cpuop_func op_68ff_22_ff;
+extern cpuop_func op_6900_22_nf;
+extern cpuop_func op_6900_22_ff;
+extern cpuop_func op_6901_22_nf;
+extern cpuop_func op_6901_22_ff;
+extern cpuop_func op_69ff_22_nf;
+extern cpuop_func op_69ff_22_ff;
+extern cpuop_func op_6a00_22_nf;
+extern cpuop_func op_6a00_22_ff;
+extern cpuop_func op_6a01_22_nf;
+extern cpuop_func op_6a01_22_ff;
+extern cpuop_func op_6aff_22_nf;
+extern cpuop_func op_6aff_22_ff;
+extern cpuop_func op_6b00_22_nf;
+extern cpuop_func op_6b00_22_ff;
+extern cpuop_func op_6b01_22_nf;
+extern cpuop_func op_6b01_22_ff;
+extern cpuop_func op_6bff_22_nf;
+extern cpuop_func op_6bff_22_ff;
+extern cpuop_func op_6c00_22_nf;
+extern cpuop_func op_6c00_22_ff;
+extern cpuop_func op_6c01_22_nf;
+extern cpuop_func op_6c01_22_ff;
+extern cpuop_func op_6cff_22_nf;
+extern cpuop_func op_6cff_22_ff;
+extern cpuop_func op_6d00_22_nf;
+extern cpuop_func op_6d00_22_ff;
+extern cpuop_func op_6d01_22_nf;
+extern cpuop_func op_6d01_22_ff;
+extern cpuop_func op_6dff_22_nf;
+extern cpuop_func op_6dff_22_ff;
+extern cpuop_func op_6e00_22_nf;
+extern cpuop_func op_6e00_22_ff;
+extern cpuop_func op_6e01_22_nf;
+extern cpuop_func op_6e01_22_ff;
+extern cpuop_func op_6eff_22_nf;
+extern cpuop_func op_6eff_22_ff;
+extern cpuop_func op_6f00_22_nf;
+extern cpuop_func op_6f00_22_ff;
+extern cpuop_func op_6f01_22_nf;
+extern cpuop_func op_6f01_22_ff;
+extern cpuop_func op_6fff_22_nf;
+extern cpuop_func op_6fff_22_ff;
+extern cpuop_func op_7000_22_nf;
+extern cpuop_func op_7000_22_ff;
+extern cpuop_func op_8000_22_nf;
+extern cpuop_func op_8000_22_ff;
+extern cpuop_func op_8010_22_nf;
+extern cpuop_func op_8010_22_ff;
+extern cpuop_func op_8018_22_nf;
+extern cpuop_func op_8018_22_ff;
+extern cpuop_func op_8020_22_nf;
+extern cpuop_func op_8020_22_ff;
+extern cpuop_func op_8028_22_nf;
+extern cpuop_func op_8028_22_ff;
+extern cpuop_func op_8030_22_nf;
+extern cpuop_func op_8030_22_ff;
+extern cpuop_func op_8038_22_nf;
+extern cpuop_func op_8038_22_ff;
+extern cpuop_func op_8039_22_nf;
+extern cpuop_func op_8039_22_ff;
+extern cpuop_func op_803a_22_nf;
+extern cpuop_func op_803a_22_ff;
+extern cpuop_func op_803b_22_nf;
+extern cpuop_func op_803b_22_ff;
+extern cpuop_func op_803c_22_nf;
+extern cpuop_func op_803c_22_ff;
+extern cpuop_func op_8040_22_nf;
+extern cpuop_func op_8040_22_ff;
+extern cpuop_func op_8050_22_nf;
+extern cpuop_func op_8050_22_ff;
+extern cpuop_func op_8058_22_nf;
+extern cpuop_func op_8058_22_ff;
+extern cpuop_func op_8060_22_nf;
+extern cpuop_func op_8060_22_ff;
+extern cpuop_func op_8068_22_nf;
+extern cpuop_func op_8068_22_ff;
+extern cpuop_func op_8070_22_nf;
+extern cpuop_func op_8070_22_ff;
+extern cpuop_func op_8078_22_nf;
+extern cpuop_func op_8078_22_ff;
+extern cpuop_func op_8079_22_nf;
+extern cpuop_func op_8079_22_ff;
+extern cpuop_func op_807a_22_nf;
+extern cpuop_func op_807a_22_ff;
+extern cpuop_func op_807b_22_nf;
+extern cpuop_func op_807b_22_ff;
+extern cpuop_func op_807c_22_nf;
+extern cpuop_func op_807c_22_ff;
+extern cpuop_func op_8080_22_nf;
+extern cpuop_func op_8080_22_ff;
+extern cpuop_func op_8090_22_nf;
+extern cpuop_func op_8090_22_ff;
+extern cpuop_func op_8098_22_nf;
+extern cpuop_func op_8098_22_ff;
+extern cpuop_func op_80a0_22_nf;
+extern cpuop_func op_80a0_22_ff;
+extern cpuop_func op_80a8_22_nf;
+extern cpuop_func op_80a8_22_ff;
+extern cpuop_func op_80b0_22_nf;
+extern cpuop_func op_80b0_22_ff;
+extern cpuop_func op_80b8_22_nf;
+extern cpuop_func op_80b8_22_ff;
+extern cpuop_func op_80b9_22_nf;
+extern cpuop_func op_80b9_22_ff;
+extern cpuop_func op_80ba_22_nf;
+extern cpuop_func op_80ba_22_ff;
+extern cpuop_func op_80bb_22_nf;
+extern cpuop_func op_80bb_22_ff;
+extern cpuop_func op_80bc_22_nf;
+extern cpuop_func op_80bc_22_ff;
+extern cpuop_func op_80c0_22_nf;
+extern cpuop_func op_80c0_22_ff;
+extern cpuop_func op_80d0_22_nf;
+extern cpuop_func op_80d0_22_ff;
+extern cpuop_func op_80d8_22_nf;
+extern cpuop_func op_80d8_22_ff;
+extern cpuop_func op_80e0_22_nf;
+extern cpuop_func op_80e0_22_ff;
+extern cpuop_func op_80e8_22_nf;
+extern cpuop_func op_80e8_22_ff;
+extern cpuop_func op_80f0_22_nf;
+extern cpuop_func op_80f0_22_ff;
+extern cpuop_func op_80f8_22_nf;
+extern cpuop_func op_80f8_22_ff;
+extern cpuop_func op_80f9_22_nf;
+extern cpuop_func op_80f9_22_ff;
+extern cpuop_func op_80fa_22_nf;
+extern cpuop_func op_80fa_22_ff;
+extern cpuop_func op_80fb_22_nf;
+extern cpuop_func op_80fb_22_ff;
+extern cpuop_func op_80fc_22_nf;
+extern cpuop_func op_80fc_22_ff;
+extern cpuop_func op_8100_22_nf;
+extern cpuop_func op_8100_22_ff;
+extern cpuop_func op_8108_22_nf;
+extern cpuop_func op_8108_22_ff;
+extern cpuop_func op_8110_22_nf;
+extern cpuop_func op_8110_22_ff;
+extern cpuop_func op_8118_22_nf;
+extern cpuop_func op_8118_22_ff;
+extern cpuop_func op_8120_22_nf;
+extern cpuop_func op_8120_22_ff;
+extern cpuop_func op_8128_22_nf;
+extern cpuop_func op_8128_22_ff;
+extern cpuop_func op_8130_22_nf;
+extern cpuop_func op_8130_22_ff;
+extern cpuop_func op_8138_22_nf;
+extern cpuop_func op_8138_22_ff;
+extern cpuop_func op_8139_22_nf;
+extern cpuop_func op_8139_22_ff;
+extern cpuop_func op_8140_22_nf;
+extern cpuop_func op_8140_22_ff;
+extern cpuop_func op_8148_22_nf;
+extern cpuop_func op_8148_22_ff;
+extern cpuop_func op_8150_22_nf;
+extern cpuop_func op_8150_22_ff;
+extern cpuop_func op_8158_22_nf;
+extern cpuop_func op_8158_22_ff;
+extern cpuop_func op_8160_22_nf;
+extern cpuop_func op_8160_22_ff;
+extern cpuop_func op_8168_22_nf;
+extern cpuop_func op_8168_22_ff;
+extern cpuop_func op_8170_22_nf;
+extern cpuop_func op_8170_22_ff;
+extern cpuop_func op_8178_22_nf;
+extern cpuop_func op_8178_22_ff;
+extern cpuop_func op_8179_22_nf;
+extern cpuop_func op_8179_22_ff;
+extern cpuop_func op_8180_22_nf;
+extern cpuop_func op_8180_22_ff;
+extern cpuop_func op_8188_22_nf;
+extern cpuop_func op_8188_22_ff;
+extern cpuop_func op_8190_22_nf;
+extern cpuop_func op_8190_22_ff;
+extern cpuop_func op_8198_22_nf;
+extern cpuop_func op_8198_22_ff;
+extern cpuop_func op_81a0_22_nf;
+extern cpuop_func op_81a0_22_ff;
+extern cpuop_func op_81a8_22_nf;
+extern cpuop_func op_81a8_22_ff;
+extern cpuop_func op_81b0_22_nf;
+extern cpuop_func op_81b0_22_ff;
+extern cpuop_func op_81b8_22_nf;
+extern cpuop_func op_81b8_22_ff;
+extern cpuop_func op_81b9_22_nf;
+extern cpuop_func op_81b9_22_ff;
+extern cpuop_func op_81c0_22_nf;
+extern cpuop_func op_81c0_22_ff;
+extern cpuop_func op_81d0_22_nf;
+extern cpuop_func op_81d0_22_ff;
+extern cpuop_func op_81d8_22_nf;
+extern cpuop_func op_81d8_22_ff;
+extern cpuop_func op_81e0_22_nf;
+extern cpuop_func op_81e0_22_ff;
+extern cpuop_func op_81e8_22_nf;
+extern cpuop_func op_81e8_22_ff;
+extern cpuop_func op_81f0_22_nf;
+extern cpuop_func op_81f0_22_ff;
+extern cpuop_func op_81f8_22_nf;
+extern cpuop_func op_81f8_22_ff;
+extern cpuop_func op_81f9_22_nf;
+extern cpuop_func op_81f9_22_ff;
+extern cpuop_func op_81fa_22_nf;
+extern cpuop_func op_81fa_22_ff;
+extern cpuop_func op_81fb_22_nf;
+extern cpuop_func op_81fb_22_ff;
+extern cpuop_func op_81fc_22_nf;
+extern cpuop_func op_81fc_22_ff;
+extern cpuop_func op_9000_22_nf;
+extern cpuop_func op_9000_22_ff;
+extern cpuop_func op_9010_22_nf;
+extern cpuop_func op_9010_22_ff;
+extern cpuop_func op_9018_22_nf;
+extern cpuop_func op_9018_22_ff;
+extern cpuop_func op_9020_22_nf;
+extern cpuop_func op_9020_22_ff;
+extern cpuop_func op_9028_22_nf;
+extern cpuop_func op_9028_22_ff;
+extern cpuop_func op_9030_22_nf;
+extern cpuop_func op_9030_22_ff;
+extern cpuop_func op_9038_22_nf;
+extern cpuop_func op_9038_22_ff;
+extern cpuop_func op_9039_22_nf;
+extern cpuop_func op_9039_22_ff;
+extern cpuop_func op_903a_22_nf;
+extern cpuop_func op_903a_22_ff;
+extern cpuop_func op_903b_22_nf;
+extern cpuop_func op_903b_22_ff;
+extern cpuop_func op_903c_22_nf;
+extern cpuop_func op_903c_22_ff;
+extern cpuop_func op_9040_22_nf;
+extern cpuop_func op_9040_22_ff;
+extern cpuop_func op_9048_22_nf;
+extern cpuop_func op_9048_22_ff;
+extern cpuop_func op_9050_22_nf;
+extern cpuop_func op_9050_22_ff;
+extern cpuop_func op_9058_22_nf;
+extern cpuop_func op_9058_22_ff;
+extern cpuop_func op_9060_22_nf;
+extern cpuop_func op_9060_22_ff;
+extern cpuop_func op_9068_22_nf;
+extern cpuop_func op_9068_22_ff;
+extern cpuop_func op_9070_22_nf;
+extern cpuop_func op_9070_22_ff;
+extern cpuop_func op_9078_22_nf;
+extern cpuop_func op_9078_22_ff;
+extern cpuop_func op_9079_22_nf;
+extern cpuop_func op_9079_22_ff;
+extern cpuop_func op_907a_22_nf;
+extern cpuop_func op_907a_22_ff;
+extern cpuop_func op_907b_22_nf;
+extern cpuop_func op_907b_22_ff;
+extern cpuop_func op_907c_22_nf;
+extern cpuop_func op_907c_22_ff;
+extern cpuop_func op_9080_22_nf;
+extern cpuop_func op_9080_22_ff;
+extern cpuop_func op_9088_22_nf;
+extern cpuop_func op_9088_22_ff;
+extern cpuop_func op_9090_22_nf;
+extern cpuop_func op_9090_22_ff;
+extern cpuop_func op_9098_22_nf;
+extern cpuop_func op_9098_22_ff;
+extern cpuop_func op_90a0_22_nf;
+extern cpuop_func op_90a0_22_ff;
+extern cpuop_func op_90a8_22_nf;
+extern cpuop_func op_90a8_22_ff;
+extern cpuop_func op_90b0_22_nf;
+extern cpuop_func op_90b0_22_ff;
+extern cpuop_func op_90b8_22_nf;
+extern cpuop_func op_90b8_22_ff;
+extern cpuop_func op_90b9_22_nf;
+extern cpuop_func op_90b9_22_ff;
+extern cpuop_func op_90ba_22_nf;
+extern cpuop_func op_90ba_22_ff;
+extern cpuop_func op_90bb_22_nf;
+extern cpuop_func op_90bb_22_ff;
+extern cpuop_func op_90bc_22_nf;
+extern cpuop_func op_90bc_22_ff;
+extern cpuop_func op_90c0_22_nf;
+extern cpuop_func op_90c0_22_ff;
+extern cpuop_func op_90c8_22_nf;
+extern cpuop_func op_90c8_22_ff;
+extern cpuop_func op_90d0_22_nf;
+extern cpuop_func op_90d0_22_ff;
+extern cpuop_func op_90d8_22_nf;
+extern cpuop_func op_90d8_22_ff;
+extern cpuop_func op_90e0_22_nf;
+extern cpuop_func op_90e0_22_ff;
+extern cpuop_func op_90e8_22_nf;
+extern cpuop_func op_90e8_22_ff;
+extern cpuop_func op_90f0_22_nf;
+extern cpuop_func op_90f0_22_ff;
+extern cpuop_func op_90f8_22_nf;
+extern cpuop_func op_90f8_22_ff;
+extern cpuop_func op_90f9_22_nf;
+extern cpuop_func op_90f9_22_ff;
+extern cpuop_func op_90fa_22_nf;
+extern cpuop_func op_90fa_22_ff;
+extern cpuop_func op_90fb_22_nf;
+extern cpuop_func op_90fb_22_ff;
+extern cpuop_func op_90fc_22_nf;
+extern cpuop_func op_90fc_22_ff;
+extern cpuop_func op_9100_22_nf;
+extern cpuop_func op_9100_22_ff;
+extern cpuop_func op_9108_22_nf;
+extern cpuop_func op_9108_22_ff;
+extern cpuop_func op_9110_22_nf;
+extern cpuop_func op_9110_22_ff;
+extern cpuop_func op_9118_22_nf;
+extern cpuop_func op_9118_22_ff;
+extern cpuop_func op_9120_22_nf;
+extern cpuop_func op_9120_22_ff;
+extern cpuop_func op_9128_22_nf;
+extern cpuop_func op_9128_22_ff;
+extern cpuop_func op_9130_22_nf;
+extern cpuop_func op_9130_22_ff;
+extern cpuop_func op_9138_22_nf;
+extern cpuop_func op_9138_22_ff;
+extern cpuop_func op_9139_22_nf;
+extern cpuop_func op_9139_22_ff;
+extern cpuop_func op_9140_22_nf;
+extern cpuop_func op_9140_22_ff;
+extern cpuop_func op_9148_22_nf;
+extern cpuop_func op_9148_22_ff;
+extern cpuop_func op_9150_22_nf;
+extern cpuop_func op_9150_22_ff;
+extern cpuop_func op_9158_22_nf;
+extern cpuop_func op_9158_22_ff;
+extern cpuop_func op_9160_22_nf;
+extern cpuop_func op_9160_22_ff;
+extern cpuop_func op_9168_22_nf;
+extern cpuop_func op_9168_22_ff;
+extern cpuop_func op_9170_22_nf;
+extern cpuop_func op_9170_22_ff;
+extern cpuop_func op_9178_22_nf;
+extern cpuop_func op_9178_22_ff;
+extern cpuop_func op_9179_22_nf;
+extern cpuop_func op_9179_22_ff;
+extern cpuop_func op_9180_22_nf;
+extern cpuop_func op_9180_22_ff;
+extern cpuop_func op_9188_22_nf;
+extern cpuop_func op_9188_22_ff;
+extern cpuop_func op_9190_22_nf;
+extern cpuop_func op_9190_22_ff;
+extern cpuop_func op_9198_22_nf;
+extern cpuop_func op_9198_22_ff;
+extern cpuop_func op_91a0_22_nf;
+extern cpuop_func op_91a0_22_ff;
+extern cpuop_func op_91a8_22_nf;
+extern cpuop_func op_91a8_22_ff;
+extern cpuop_func op_91b0_22_nf;
+extern cpuop_func op_91b0_22_ff;
+extern cpuop_func op_91b8_22_nf;
+extern cpuop_func op_91b8_22_ff;
+extern cpuop_func op_91b9_22_nf;
+extern cpuop_func op_91b9_22_ff;
+extern cpuop_func op_91c0_22_nf;
+extern cpuop_func op_91c0_22_ff;
+extern cpuop_func op_91c8_22_nf;
+extern cpuop_func op_91c8_22_ff;
+extern cpuop_func op_91d0_22_nf;
+extern cpuop_func op_91d0_22_ff;
+extern cpuop_func op_91d8_22_nf;
+extern cpuop_func op_91d8_22_ff;
+extern cpuop_func op_91e0_22_nf;
+extern cpuop_func op_91e0_22_ff;
+extern cpuop_func op_91e8_22_nf;
+extern cpuop_func op_91e8_22_ff;
+extern cpuop_func op_91f0_22_nf;
+extern cpuop_func op_91f0_22_ff;
+extern cpuop_func op_91f8_22_nf;
+extern cpuop_func op_91f8_22_ff;
+extern cpuop_func op_91f9_22_nf;
+extern cpuop_func op_91f9_22_ff;
+extern cpuop_func op_91fa_22_nf;
+extern cpuop_func op_91fa_22_ff;
+extern cpuop_func op_91fb_22_nf;
+extern cpuop_func op_91fb_22_ff;
+extern cpuop_func op_91fc_22_nf;
+extern cpuop_func op_91fc_22_ff;
+extern cpuop_func op_b000_22_nf;
+extern cpuop_func op_b000_22_ff;
+extern cpuop_func op_b010_22_nf;
+extern cpuop_func op_b010_22_ff;
+extern cpuop_func op_b018_22_nf;
+extern cpuop_func op_b018_22_ff;
+extern cpuop_func op_b020_22_nf;
+extern cpuop_func op_b020_22_ff;
+extern cpuop_func op_b028_22_nf;
+extern cpuop_func op_b028_22_ff;
+extern cpuop_func op_b030_22_nf;
+extern cpuop_func op_b030_22_ff;
+extern cpuop_func op_b038_22_nf;
+extern cpuop_func op_b038_22_ff;
+extern cpuop_func op_b039_22_nf;
+extern cpuop_func op_b039_22_ff;
+extern cpuop_func op_b03a_22_nf;
+extern cpuop_func op_b03a_22_ff;
+extern cpuop_func op_b03b_22_nf;
+extern cpuop_func op_b03b_22_ff;
+extern cpuop_func op_b03c_22_nf;
+extern cpuop_func op_b03c_22_ff;
+extern cpuop_func op_b040_22_nf;
+extern cpuop_func op_b040_22_ff;
+extern cpuop_func op_b048_22_nf;
+extern cpuop_func op_b048_22_ff;
+extern cpuop_func op_b050_22_nf;
+extern cpuop_func op_b050_22_ff;
+extern cpuop_func op_b058_22_nf;
+extern cpuop_func op_b058_22_ff;
+extern cpuop_func op_b060_22_nf;
+extern cpuop_func op_b060_22_ff;
+extern cpuop_func op_b068_22_nf;
+extern cpuop_func op_b068_22_ff;
+extern cpuop_func op_b070_22_nf;
+extern cpuop_func op_b070_22_ff;
+extern cpuop_func op_b078_22_nf;
+extern cpuop_func op_b078_22_ff;
+extern cpuop_func op_b079_22_nf;
+extern cpuop_func op_b079_22_ff;
+extern cpuop_func op_b07a_22_nf;
+extern cpuop_func op_b07a_22_ff;
+extern cpuop_func op_b07b_22_nf;
+extern cpuop_func op_b07b_22_ff;
+extern cpuop_func op_b07c_22_nf;
+extern cpuop_func op_b07c_22_ff;
+extern cpuop_func op_b080_22_nf;
+extern cpuop_func op_b080_22_ff;
+extern cpuop_func op_b088_22_nf;
+extern cpuop_func op_b088_22_ff;
+extern cpuop_func op_b090_22_nf;
+extern cpuop_func op_b090_22_ff;
+extern cpuop_func op_b098_22_nf;
+extern cpuop_func op_b098_22_ff;
+extern cpuop_func op_b0a0_22_nf;
+extern cpuop_func op_b0a0_22_ff;
+extern cpuop_func op_b0a8_22_nf;
+extern cpuop_func op_b0a8_22_ff;
+extern cpuop_func op_b0b0_22_nf;
+extern cpuop_func op_b0b0_22_ff;
+extern cpuop_func op_b0b8_22_nf;
+extern cpuop_func op_b0b8_22_ff;
+extern cpuop_func op_b0b9_22_nf;
+extern cpuop_func op_b0b9_22_ff;
+extern cpuop_func op_b0ba_22_nf;
+extern cpuop_func op_b0ba_22_ff;
+extern cpuop_func op_b0bb_22_nf;
+extern cpuop_func op_b0bb_22_ff;
+extern cpuop_func op_b0bc_22_nf;
+extern cpuop_func op_b0bc_22_ff;
+extern cpuop_func op_b0c0_22_nf;
+extern cpuop_func op_b0c0_22_ff;
+extern cpuop_func op_b0c8_22_nf;
+extern cpuop_func op_b0c8_22_ff;
+extern cpuop_func op_b0d0_22_nf;
+extern cpuop_func op_b0d0_22_ff;
+extern cpuop_func op_b0d8_22_nf;
+extern cpuop_func op_b0d8_22_ff;
+extern cpuop_func op_b0e0_22_nf;
+extern cpuop_func op_b0e0_22_ff;
+extern cpuop_func op_b0e8_22_nf;
+extern cpuop_func op_b0e8_22_ff;
+extern cpuop_func op_b0f0_22_nf;
+extern cpuop_func op_b0f0_22_ff;
+extern cpuop_func op_b0f8_22_nf;
+extern cpuop_func op_b0f8_22_ff;
+extern cpuop_func op_b0f9_22_nf;
+extern cpuop_func op_b0f9_22_ff;
+extern cpuop_func op_b0fa_22_nf;
+extern cpuop_func op_b0fa_22_ff;
+extern cpuop_func op_b0fb_22_nf;
+extern cpuop_func op_b0fb_22_ff;
+extern cpuop_func op_b0fc_22_nf;
+extern cpuop_func op_b0fc_22_ff;
+extern cpuop_func op_b100_22_nf;
+extern cpuop_func op_b100_22_ff;
+extern cpuop_func op_b108_22_nf;
+extern cpuop_func op_b108_22_ff;
+extern cpuop_func op_b110_22_nf;
+extern cpuop_func op_b110_22_ff;
+extern cpuop_func op_b118_22_nf;
+extern cpuop_func op_b118_22_ff;
+extern cpuop_func op_b120_22_nf;
+extern cpuop_func op_b120_22_ff;
+extern cpuop_func op_b128_22_nf;
+extern cpuop_func op_b128_22_ff;
+extern cpuop_func op_b130_22_nf;
+extern cpuop_func op_b130_22_ff;
+extern cpuop_func op_b138_22_nf;
+extern cpuop_func op_b138_22_ff;
+extern cpuop_func op_b139_22_nf;
+extern cpuop_func op_b139_22_ff;
+extern cpuop_func op_b140_22_nf;
+extern cpuop_func op_b140_22_ff;
+extern cpuop_func op_b148_22_nf;
+extern cpuop_func op_b148_22_ff;
+extern cpuop_func op_b150_22_nf;
+extern cpuop_func op_b150_22_ff;
+extern cpuop_func op_b158_22_nf;
+extern cpuop_func op_b158_22_ff;
+extern cpuop_func op_b160_22_nf;
+extern cpuop_func op_b160_22_ff;
+extern cpuop_func op_b168_22_nf;
+extern cpuop_func op_b168_22_ff;
+extern cpuop_func op_b170_22_nf;
+extern cpuop_func op_b170_22_ff;
+extern cpuop_func op_b178_22_nf;
+extern cpuop_func op_b178_22_ff;
+extern cpuop_func op_b179_22_nf;
+extern cpuop_func op_b179_22_ff;
+extern cpuop_func op_b180_22_nf;
+extern cpuop_func op_b180_22_ff;
+extern cpuop_func op_b188_22_nf;
+extern cpuop_func op_b188_22_ff;
+extern cpuop_func op_b190_22_nf;
+extern cpuop_func op_b190_22_ff;
+extern cpuop_func op_b198_22_nf;
+extern cpuop_func op_b198_22_ff;
+extern cpuop_func op_b1a0_22_nf;
+extern cpuop_func op_b1a0_22_ff;
+extern cpuop_func op_b1a8_22_nf;
+extern cpuop_func op_b1a8_22_ff;
+extern cpuop_func op_b1b0_22_nf;
+extern cpuop_func op_b1b0_22_ff;
+extern cpuop_func op_b1b8_22_nf;
+extern cpuop_func op_b1b8_22_ff;
+extern cpuop_func op_b1b9_22_nf;
+extern cpuop_func op_b1b9_22_ff;
+extern cpuop_func op_b1c0_22_nf;
+extern cpuop_func op_b1c0_22_ff;
+extern cpuop_func op_b1c8_22_nf;
+extern cpuop_func op_b1c8_22_ff;
+extern cpuop_func op_b1d0_22_nf;
+extern cpuop_func op_b1d0_22_ff;
+extern cpuop_func op_b1d8_22_nf;
+extern cpuop_func op_b1d8_22_ff;
+extern cpuop_func op_b1e0_22_nf;
+extern cpuop_func op_b1e0_22_ff;
+extern cpuop_func op_b1e8_22_nf;
+extern cpuop_func op_b1e8_22_ff;
+extern cpuop_func op_b1f0_22_nf;
+extern cpuop_func op_b1f0_22_ff;
+extern cpuop_func op_b1f8_22_nf;
+extern cpuop_func op_b1f8_22_ff;
+extern cpuop_func op_b1f9_22_nf;
+extern cpuop_func op_b1f9_22_ff;
+extern cpuop_func op_b1fa_22_nf;
+extern cpuop_func op_b1fa_22_ff;
+extern cpuop_func op_b1fb_22_nf;
+extern cpuop_func op_b1fb_22_ff;
+extern cpuop_func op_b1fc_22_nf;
+extern cpuop_func op_b1fc_22_ff;
+extern cpuop_func op_c000_22_nf;
+extern cpuop_func op_c000_22_ff;
+extern cpuop_func op_c010_22_nf;
+extern cpuop_func op_c010_22_ff;
+extern cpuop_func op_c018_22_nf;
+extern cpuop_func op_c018_22_ff;
+extern cpuop_func op_c020_22_nf;
+extern cpuop_func op_c020_22_ff;
+extern cpuop_func op_c028_22_nf;
+extern cpuop_func op_c028_22_ff;
+extern cpuop_func op_c030_22_nf;
+extern cpuop_func op_c030_22_ff;
+extern cpuop_func op_c038_22_nf;
+extern cpuop_func op_c038_22_ff;
+extern cpuop_func op_c039_22_nf;
+extern cpuop_func op_c039_22_ff;
+extern cpuop_func op_c03a_22_nf;
+extern cpuop_func op_c03a_22_ff;
+extern cpuop_func op_c03b_22_nf;
+extern cpuop_func op_c03b_22_ff;
+extern cpuop_func op_c03c_22_nf;
+extern cpuop_func op_c03c_22_ff;
+extern cpuop_func op_c040_22_nf;
+extern cpuop_func op_c040_22_ff;
+extern cpuop_func op_c050_22_nf;
+extern cpuop_func op_c050_22_ff;
+extern cpuop_func op_c058_22_nf;
+extern cpuop_func op_c058_22_ff;
+extern cpuop_func op_c060_22_nf;
+extern cpuop_func op_c060_22_ff;
+extern cpuop_func op_c068_22_nf;
+extern cpuop_func op_c068_22_ff;
+extern cpuop_func op_c070_22_nf;
+extern cpuop_func op_c070_22_ff;
+extern cpuop_func op_c078_22_nf;
+extern cpuop_func op_c078_22_ff;
+extern cpuop_func op_c079_22_nf;
+extern cpuop_func op_c079_22_ff;
+extern cpuop_func op_c07a_22_nf;
+extern cpuop_func op_c07a_22_ff;
+extern cpuop_func op_c07b_22_nf;
+extern cpuop_func op_c07b_22_ff;
+extern cpuop_func op_c07c_22_nf;
+extern cpuop_func op_c07c_22_ff;
+extern cpuop_func op_c080_22_nf;
+extern cpuop_func op_c080_22_ff;
+extern cpuop_func op_c090_22_nf;
+extern cpuop_func op_c090_22_ff;
+extern cpuop_func op_c098_22_nf;
+extern cpuop_func op_c098_22_ff;
+extern cpuop_func op_c0a0_22_nf;
+extern cpuop_func op_c0a0_22_ff;
+extern cpuop_func op_c0a8_22_nf;
+extern cpuop_func op_c0a8_22_ff;
+extern cpuop_func op_c0b0_22_nf;
+extern cpuop_func op_c0b0_22_ff;
+extern cpuop_func op_c0b8_22_nf;
+extern cpuop_func op_c0b8_22_ff;
+extern cpuop_func op_c0b9_22_nf;
+extern cpuop_func op_c0b9_22_ff;
+extern cpuop_func op_c0ba_22_nf;
+extern cpuop_func op_c0ba_22_ff;
+extern cpuop_func op_c0bb_22_nf;
+extern cpuop_func op_c0bb_22_ff;
+extern cpuop_func op_c0bc_22_nf;
+extern cpuop_func op_c0bc_22_ff;
+extern cpuop_func op_c0c0_22_nf;
+extern cpuop_func op_c0c0_22_ff;
+extern cpuop_func op_c0d0_22_nf;
+extern cpuop_func op_c0d0_22_ff;
+extern cpuop_func op_c0d8_22_nf;
+extern cpuop_func op_c0d8_22_ff;
+extern cpuop_func op_c0e0_22_nf;
+extern cpuop_func op_c0e0_22_ff;
+extern cpuop_func op_c0e8_22_nf;
+extern cpuop_func op_c0e8_22_ff;
+extern cpuop_func op_c0f0_22_nf;
+extern cpuop_func op_c0f0_22_ff;
+extern cpuop_func op_c0f8_22_nf;
+extern cpuop_func op_c0f8_22_ff;
+extern cpuop_func op_c0f9_22_nf;
+extern cpuop_func op_c0f9_22_ff;
+extern cpuop_func op_c0fa_22_nf;
+extern cpuop_func op_c0fa_22_ff;
+extern cpuop_func op_c0fb_22_nf;
+extern cpuop_func op_c0fb_22_ff;
+extern cpuop_func op_c0fc_22_nf;
+extern cpuop_func op_c0fc_22_ff;
+extern cpuop_func op_c100_22_nf;
+extern cpuop_func op_c100_22_ff;
+extern cpuop_func op_c108_22_nf;
+extern cpuop_func op_c108_22_ff;
+extern cpuop_func op_c110_22_nf;
+extern cpuop_func op_c110_22_ff;
+extern cpuop_func op_c118_22_nf;
+extern cpuop_func op_c118_22_ff;
+extern cpuop_func op_c120_22_nf;
+extern cpuop_func op_c120_22_ff;
+extern cpuop_func op_c128_22_nf;
+extern cpuop_func op_c128_22_ff;
+extern cpuop_func op_c130_22_nf;
+extern cpuop_func op_c130_22_ff;
+extern cpuop_func op_c138_22_nf;
+extern cpuop_func op_c138_22_ff;
+extern cpuop_func op_c139_22_nf;
+extern cpuop_func op_c139_22_ff;
+extern cpuop_func op_c140_22_nf;
+extern cpuop_func op_c140_22_ff;
+extern cpuop_func op_c148_22_nf;
+extern cpuop_func op_c148_22_ff;
+extern cpuop_func op_c150_22_nf;
+extern cpuop_func op_c150_22_ff;
+extern cpuop_func op_c158_22_nf;
+extern cpuop_func op_c158_22_ff;
+extern cpuop_func op_c160_22_nf;
+extern cpuop_func op_c160_22_ff;
+extern cpuop_func op_c168_22_nf;
+extern cpuop_func op_c168_22_ff;
+extern cpuop_func op_c170_22_nf;
+extern cpuop_func op_c170_22_ff;
+extern cpuop_func op_c178_22_nf;
+extern cpuop_func op_c178_22_ff;
+extern cpuop_func op_c179_22_nf;
+extern cpuop_func op_c179_22_ff;
+extern cpuop_func op_c188_22_nf;
+extern cpuop_func op_c188_22_ff;
+extern cpuop_func op_c190_22_nf;
+extern cpuop_func op_c190_22_ff;
+extern cpuop_func op_c198_22_nf;
+extern cpuop_func op_c198_22_ff;
+extern cpuop_func op_c1a0_22_nf;
+extern cpuop_func op_c1a0_22_ff;
+extern cpuop_func op_c1a8_22_nf;
+extern cpuop_func op_c1a8_22_ff;
+extern cpuop_func op_c1b0_22_nf;
+extern cpuop_func op_c1b0_22_ff;
+extern cpuop_func op_c1b8_22_nf;
+extern cpuop_func op_c1b8_22_ff;
+extern cpuop_func op_c1b9_22_nf;
+extern cpuop_func op_c1b9_22_ff;
+extern cpuop_func op_c1c0_22_nf;
+extern cpuop_func op_c1c0_22_ff;
+extern cpuop_func op_c1d0_22_nf;
+extern cpuop_func op_c1d0_22_ff;
+extern cpuop_func op_c1d8_22_nf;
+extern cpuop_func op_c1d8_22_ff;
+extern cpuop_func op_c1e0_22_nf;
+extern cpuop_func op_c1e0_22_ff;
+extern cpuop_func op_c1e8_22_nf;
+extern cpuop_func op_c1e8_22_ff;
+extern cpuop_func op_c1f0_22_nf;
+extern cpuop_func op_c1f0_22_ff;
+extern cpuop_func op_c1f8_22_nf;
+extern cpuop_func op_c1f8_22_ff;
+extern cpuop_func op_c1f9_22_nf;
+extern cpuop_func op_c1f9_22_ff;
+extern cpuop_func op_c1fa_22_nf;
+extern cpuop_func op_c1fa_22_ff;
+extern cpuop_func op_c1fb_22_nf;
+extern cpuop_func op_c1fb_22_ff;
+extern cpuop_func op_c1fc_22_nf;
+extern cpuop_func op_c1fc_22_ff;
+extern cpuop_func op_d000_22_nf;
+extern cpuop_func op_d000_22_ff;
+extern cpuop_func op_d010_22_nf;
+extern cpuop_func op_d010_22_ff;
+extern cpuop_func op_d018_22_nf;
+extern cpuop_func op_d018_22_ff;
+extern cpuop_func op_d020_22_nf;
+extern cpuop_func op_d020_22_ff;
+extern cpuop_func op_d028_22_nf;
+extern cpuop_func op_d028_22_ff;
+extern cpuop_func op_d030_22_nf;
+extern cpuop_func op_d030_22_ff;
+extern cpuop_func op_d038_22_nf;
+extern cpuop_func op_d038_22_ff;
+extern cpuop_func op_d039_22_nf;
+extern cpuop_func op_d039_22_ff;
+extern cpuop_func op_d03a_22_nf;
+extern cpuop_func op_d03a_22_ff;
+extern cpuop_func op_d03b_22_nf;
+extern cpuop_func op_d03b_22_ff;
+extern cpuop_func op_d03c_22_nf;
+extern cpuop_func op_d03c_22_ff;
+extern cpuop_func op_d040_22_nf;
+extern cpuop_func op_d040_22_ff;
+extern cpuop_func op_d048_22_nf;
+extern cpuop_func op_d048_22_ff;
+extern cpuop_func op_d050_22_nf;
+extern cpuop_func op_d050_22_ff;
+extern cpuop_func op_d058_22_nf;
+extern cpuop_func op_d058_22_ff;
+extern cpuop_func op_d060_22_nf;
+extern cpuop_func op_d060_22_ff;
+extern cpuop_func op_d068_22_nf;
+extern cpuop_func op_d068_22_ff;
+extern cpuop_func op_d070_22_nf;
+extern cpuop_func op_d070_22_ff;
+extern cpuop_func op_d078_22_nf;
+extern cpuop_func op_d078_22_ff;
+extern cpuop_func op_d079_22_nf;
+extern cpuop_func op_d079_22_ff;
+extern cpuop_func op_d07a_22_nf;
+extern cpuop_func op_d07a_22_ff;
+extern cpuop_func op_d07b_22_nf;
+extern cpuop_func op_d07b_22_ff;
+extern cpuop_func op_d07c_22_nf;
+extern cpuop_func op_d07c_22_ff;
+extern cpuop_func op_d080_22_nf;
+extern cpuop_func op_d080_22_ff;
+extern cpuop_func op_d088_22_nf;
+extern cpuop_func op_d088_22_ff;
+extern cpuop_func op_d090_22_nf;
+extern cpuop_func op_d090_22_ff;
+extern cpuop_func op_d098_22_nf;
+extern cpuop_func op_d098_22_ff;
+extern cpuop_func op_d0a0_22_nf;
+extern cpuop_func op_d0a0_22_ff;
+extern cpuop_func op_d0a8_22_nf;
+extern cpuop_func op_d0a8_22_ff;
+extern cpuop_func op_d0b0_22_nf;
+extern cpuop_func op_d0b0_22_ff;
+extern cpuop_func op_d0b8_22_nf;
+extern cpuop_func op_d0b8_22_ff;
+extern cpuop_func op_d0b9_22_nf;
+extern cpuop_func op_d0b9_22_ff;
+extern cpuop_func op_d0ba_22_nf;
+extern cpuop_func op_d0ba_22_ff;
+extern cpuop_func op_d0bb_22_nf;
+extern cpuop_func op_d0bb_22_ff;
+extern cpuop_func op_d0bc_22_nf;
+extern cpuop_func op_d0bc_22_ff;
+extern cpuop_func op_d0c0_22_nf;
+extern cpuop_func op_d0c0_22_ff;
+extern cpuop_func op_d0c8_22_nf;
+extern cpuop_func op_d0c8_22_ff;
+extern cpuop_func op_d0d0_22_nf;
+extern cpuop_func op_d0d0_22_ff;
+extern cpuop_func op_d0d8_22_nf;
+extern cpuop_func op_d0d8_22_ff;
+extern cpuop_func op_d0e0_22_nf;
+extern cpuop_func op_d0e0_22_ff;
+extern cpuop_func op_d0e8_22_nf;
+extern cpuop_func op_d0e8_22_ff;
+extern cpuop_func op_d0f0_22_nf;
+extern cpuop_func op_d0f0_22_ff;
+extern cpuop_func op_d0f8_22_nf;
+extern cpuop_func op_d0f8_22_ff;
+extern cpuop_func op_d0f9_22_nf;
+extern cpuop_func op_d0f9_22_ff;
+extern cpuop_func op_d0fa_22_nf;
+extern cpuop_func op_d0fa_22_ff;
+extern cpuop_func op_d0fb_22_nf;
+extern cpuop_func op_d0fb_22_ff;
+extern cpuop_func op_d0fc_22_nf;
+extern cpuop_func op_d0fc_22_ff;
+extern cpuop_func op_d100_22_nf;
+extern cpuop_func op_d100_22_ff;
+extern cpuop_func op_d108_22_nf;
+extern cpuop_func op_d108_22_ff;
+extern cpuop_func op_d110_22_nf;
+extern cpuop_func op_d110_22_ff;
+extern cpuop_func op_d118_22_nf;
+extern cpuop_func op_d118_22_ff;
+extern cpuop_func op_d120_22_nf;
+extern cpuop_func op_d120_22_ff;
+extern cpuop_func op_d128_22_nf;
+extern cpuop_func op_d128_22_ff;
+extern cpuop_func op_d130_22_nf;
+extern cpuop_func op_d130_22_ff;
+extern cpuop_func op_d138_22_nf;
+extern cpuop_func op_d138_22_ff;
+extern cpuop_func op_d139_22_nf;
+extern cpuop_func op_d139_22_ff;
+extern cpuop_func op_d140_22_nf;
+extern cpuop_func op_d140_22_ff;
+extern cpuop_func op_d148_22_nf;
+extern cpuop_func op_d148_22_ff;
+extern cpuop_func op_d150_22_nf;
+extern cpuop_func op_d150_22_ff;
+extern cpuop_func op_d158_22_nf;
+extern cpuop_func op_d158_22_ff;
+extern cpuop_func op_d160_22_nf;
+extern cpuop_func op_d160_22_ff;
+extern cpuop_func op_d168_22_nf;
+extern cpuop_func op_d168_22_ff;
+extern cpuop_func op_d170_22_nf;
+extern cpuop_func op_d170_22_ff;
+extern cpuop_func op_d178_22_nf;
+extern cpuop_func op_d178_22_ff;
+extern cpuop_func op_d179_22_nf;
+extern cpuop_func op_d179_22_ff;
+extern cpuop_func op_d180_22_nf;
+extern cpuop_func op_d180_22_ff;
+extern cpuop_func op_d188_22_nf;
+extern cpuop_func op_d188_22_ff;
+extern cpuop_func op_d190_22_nf;
+extern cpuop_func op_d190_22_ff;
+extern cpuop_func op_d198_22_nf;
+extern cpuop_func op_d198_22_ff;
+extern cpuop_func op_d1a0_22_nf;
+extern cpuop_func op_d1a0_22_ff;
+extern cpuop_func op_d1a8_22_nf;
+extern cpuop_func op_d1a8_22_ff;
+extern cpuop_func op_d1b0_22_nf;
+extern cpuop_func op_d1b0_22_ff;
+extern cpuop_func op_d1b8_22_nf;
+extern cpuop_func op_d1b8_22_ff;
+extern cpuop_func op_d1b9_22_nf;
+extern cpuop_func op_d1b9_22_ff;
+extern cpuop_func op_d1c0_22_nf;
+extern cpuop_func op_d1c0_22_ff;
+extern cpuop_func op_d1c8_22_nf;
+extern cpuop_func op_d1c8_22_ff;
+extern cpuop_func op_d1d0_22_nf;
+extern cpuop_func op_d1d0_22_ff;
+extern cpuop_func op_d1d8_22_nf;
+extern cpuop_func op_d1d8_22_ff;
+extern cpuop_func op_d1e0_22_nf;
+extern cpuop_func op_d1e0_22_ff;
+extern cpuop_func op_d1e8_22_nf;
+extern cpuop_func op_d1e8_22_ff;
+extern cpuop_func op_d1f0_22_nf;
+extern cpuop_func op_d1f0_22_ff;
+extern cpuop_func op_d1f8_22_nf;
+extern cpuop_func op_d1f8_22_ff;
+extern cpuop_func op_d1f9_22_nf;
+extern cpuop_func op_d1f9_22_ff;
+extern cpuop_func op_d1fa_22_nf;
+extern cpuop_func op_d1fa_22_ff;
+extern cpuop_func op_d1fb_22_nf;
+extern cpuop_func op_d1fb_22_ff;
+extern cpuop_func op_d1fc_22_nf;
+extern cpuop_func op_d1fc_22_ff;
+extern cpuop_func op_e000_22_nf;
+extern cpuop_func op_e000_22_ff;
+extern cpuop_func op_e008_22_nf;
+extern cpuop_func op_e008_22_ff;
+extern cpuop_func op_e010_22_nf;
+extern cpuop_func op_e010_22_ff;
+extern cpuop_func op_e018_22_nf;
+extern cpuop_func op_e018_22_ff;
+extern cpuop_func op_e020_22_nf;
+extern cpuop_func op_e020_22_ff;
+extern cpuop_func op_e028_22_nf;
+extern cpuop_func op_e028_22_ff;
+extern cpuop_func op_e030_22_nf;
+extern cpuop_func op_e030_22_ff;
+extern cpuop_func op_e038_22_nf;
+extern cpuop_func op_e038_22_ff;
+extern cpuop_func op_e040_22_nf;
+extern cpuop_func op_e040_22_ff;
+extern cpuop_func op_e048_22_nf;
+extern cpuop_func op_e048_22_ff;
+extern cpuop_func op_e050_22_nf;
+extern cpuop_func op_e050_22_ff;
+extern cpuop_func op_e058_22_nf;
+extern cpuop_func op_e058_22_ff;
+extern cpuop_func op_e060_22_nf;
+extern cpuop_func op_e060_22_ff;
+extern cpuop_func op_e068_22_nf;
+extern cpuop_func op_e068_22_ff;
+extern cpuop_func op_e070_22_nf;
+extern cpuop_func op_e070_22_ff;
+extern cpuop_func op_e078_22_nf;
+extern cpuop_func op_e078_22_ff;
+extern cpuop_func op_e080_22_nf;
+extern cpuop_func op_e080_22_ff;
+extern cpuop_func op_e088_22_nf;
+extern cpuop_func op_e088_22_ff;
+extern cpuop_func op_e090_22_nf;
+extern cpuop_func op_e090_22_ff;
+extern cpuop_func op_e098_22_nf;
+extern cpuop_func op_e098_22_ff;
+extern cpuop_func op_e0a0_22_nf;
+extern cpuop_func op_e0a0_22_ff;
+extern cpuop_func op_e0a8_22_nf;
+extern cpuop_func op_e0a8_22_ff;
+extern cpuop_func op_e0b0_22_nf;
+extern cpuop_func op_e0b0_22_ff;
+extern cpuop_func op_e0b8_22_nf;
+extern cpuop_func op_e0b8_22_ff;
+extern cpuop_func op_e0d0_22_nf;
+extern cpuop_func op_e0d0_22_ff;
+extern cpuop_func op_e0d8_22_nf;
+extern cpuop_func op_e0d8_22_ff;
+extern cpuop_func op_e0e0_22_nf;
+extern cpuop_func op_e0e0_22_ff;
+extern cpuop_func op_e0e8_22_nf;
+extern cpuop_func op_e0e8_22_ff;
+extern cpuop_func op_e0f0_22_nf;
+extern cpuop_func op_e0f0_22_ff;
+extern cpuop_func op_e0f8_22_nf;
+extern cpuop_func op_e0f8_22_ff;
+extern cpuop_func op_e0f9_22_nf;
+extern cpuop_func op_e0f9_22_ff;
+extern cpuop_func op_e100_22_nf;
+extern cpuop_func op_e100_22_ff;
+extern cpuop_func op_e108_22_nf;
+extern cpuop_func op_e108_22_ff;
+extern cpuop_func op_e110_22_nf;
+extern cpuop_func op_e110_22_ff;
+extern cpuop_func op_e118_22_nf;
+extern cpuop_func op_e118_22_ff;
+extern cpuop_func op_e120_22_nf;
+extern cpuop_func op_e120_22_ff;
+extern cpuop_func op_e128_22_nf;
+extern cpuop_func op_e128_22_ff;
+extern cpuop_func op_e130_22_nf;
+extern cpuop_func op_e130_22_ff;
+extern cpuop_func op_e138_22_nf;
+extern cpuop_func op_e138_22_ff;
+extern cpuop_func op_e140_22_nf;
+extern cpuop_func op_e140_22_ff;
+extern cpuop_func op_e148_22_nf;
+extern cpuop_func op_e148_22_ff;
+extern cpuop_func op_e150_22_nf;
+extern cpuop_func op_e150_22_ff;
+extern cpuop_func op_e158_22_nf;
+extern cpuop_func op_e158_22_ff;
+extern cpuop_func op_e160_22_nf;
+extern cpuop_func op_e160_22_ff;
+extern cpuop_func op_e168_22_nf;
+extern cpuop_func op_e168_22_ff;
+extern cpuop_func op_e170_22_nf;
+extern cpuop_func op_e170_22_ff;
+extern cpuop_func op_e178_22_nf;
+extern cpuop_func op_e178_22_ff;
+extern cpuop_func op_e180_22_nf;
+extern cpuop_func op_e180_22_ff;
+extern cpuop_func op_e188_22_nf;
+extern cpuop_func op_e188_22_ff;
+extern cpuop_func op_e190_22_nf;
+extern cpuop_func op_e190_22_ff;
+extern cpuop_func op_e198_22_nf;
+extern cpuop_func op_e198_22_ff;
+extern cpuop_func op_e1a0_22_nf;
+extern cpuop_func op_e1a0_22_ff;
+extern cpuop_func op_e1a8_22_nf;
+extern cpuop_func op_e1a8_22_ff;
+extern cpuop_func op_e1b0_22_nf;
+extern cpuop_func op_e1b0_22_ff;
+extern cpuop_func op_e1b8_22_nf;
+extern cpuop_func op_e1b8_22_ff;
+extern cpuop_func op_e1d0_22_nf;
+extern cpuop_func op_e1d0_22_ff;
+extern cpuop_func op_e1d8_22_nf;
+extern cpuop_func op_e1d8_22_ff;
+extern cpuop_func op_e1e0_22_nf;
+extern cpuop_func op_e1e0_22_ff;
+extern cpuop_func op_e1e8_22_nf;
+extern cpuop_func op_e1e8_22_ff;
+extern cpuop_func op_e1f0_22_nf;
+extern cpuop_func op_e1f0_22_ff;
+extern cpuop_func op_e1f8_22_nf;
+extern cpuop_func op_e1f8_22_ff;
+extern cpuop_func op_e1f9_22_nf;
+extern cpuop_func op_e1f9_22_ff;
+extern cpuop_func op_e2d0_22_nf;
+extern cpuop_func op_e2d0_22_ff;
+extern cpuop_func op_e2d8_22_nf;
+extern cpuop_func op_e2d8_22_ff;
+extern cpuop_func op_e2e0_22_nf;
+extern cpuop_func op_e2e0_22_ff;
+extern cpuop_func op_e2e8_22_nf;
+extern cpuop_func op_e2e8_22_ff;
+extern cpuop_func op_e2f0_22_nf;
+extern cpuop_func op_e2f0_22_ff;
+extern cpuop_func op_e2f8_22_nf;
+extern cpuop_func op_e2f8_22_ff;
+extern cpuop_func op_e2f9_22_nf;
+extern cpuop_func op_e2f9_22_ff;
+extern cpuop_func op_e3d0_22_nf;
+extern cpuop_func op_e3d0_22_ff;
+extern cpuop_func op_e3d8_22_nf;
+extern cpuop_func op_e3d8_22_ff;
+extern cpuop_func op_e3e0_22_nf;
+extern cpuop_func op_e3e0_22_ff;
+extern cpuop_func op_e3e8_22_nf;
+extern cpuop_func op_e3e8_22_ff;
+extern cpuop_func op_e3f0_22_nf;
+extern cpuop_func op_e3f0_22_ff;
+extern cpuop_func op_e3f8_22_nf;
+extern cpuop_func op_e3f8_22_ff;
+extern cpuop_func op_e3f9_22_nf;
+extern cpuop_func op_e3f9_22_ff;
+extern cpuop_func op_e4d0_22_nf;
+extern cpuop_func op_e4d0_22_ff;
+extern cpuop_func op_e4d8_22_nf;
+extern cpuop_func op_e4d8_22_ff;
+extern cpuop_func op_e4e0_22_nf;
+extern cpuop_func op_e4e0_22_ff;
+extern cpuop_func op_e4e8_22_nf;
+extern cpuop_func op_e4e8_22_ff;
+extern cpuop_func op_e4f0_22_nf;
+extern cpuop_func op_e4f0_22_ff;
+extern cpuop_func op_e4f8_22_nf;
+extern cpuop_func op_e4f8_22_ff;
+extern cpuop_func op_e4f9_22_nf;
+extern cpuop_func op_e4f9_22_ff;
+extern cpuop_func op_e5d0_22_nf;
+extern cpuop_func op_e5d0_22_ff;
+extern cpuop_func op_e5d8_22_nf;
+extern cpuop_func op_e5d8_22_ff;
+extern cpuop_func op_e5e0_22_nf;
+extern cpuop_func op_e5e0_22_ff;
+extern cpuop_func op_e5e8_22_nf;
+extern cpuop_func op_e5e8_22_ff;
+extern cpuop_func op_e5f0_22_nf;
+extern cpuop_func op_e5f0_22_ff;
+extern cpuop_func op_e5f8_22_nf;
+extern cpuop_func op_e5f8_22_ff;
+extern cpuop_func op_e5f9_22_nf;
+extern cpuop_func op_e5f9_22_ff;
+extern cpuop_func op_e6d0_22_nf;
+extern cpuop_func op_e6d0_22_ff;
+extern cpuop_func op_e6d8_22_nf;
+extern cpuop_func op_e6d8_22_ff;
+extern cpuop_func op_e6e0_22_nf;
+extern cpuop_func op_e6e0_22_ff;
+extern cpuop_func op_e6e8_22_nf;
+extern cpuop_func op_e6e8_22_ff;
+extern cpuop_func op_e6f0_22_nf;
+extern cpuop_func op_e6f0_22_ff;
+extern cpuop_func op_e6f8_22_nf;
+extern cpuop_func op_e6f8_22_ff;
+extern cpuop_func op_e6f9_22_nf;
+extern cpuop_func op_e6f9_22_ff;
+extern cpuop_func op_e7d0_22_nf;
+extern cpuop_func op_e7d0_22_ff;
+extern cpuop_func op_e7d8_22_nf;
+extern cpuop_func op_e7d8_22_ff;
+extern cpuop_func op_e7e0_22_nf;
+extern cpuop_func op_e7e0_22_ff;
+extern cpuop_func op_e7e8_22_nf;
+extern cpuop_func op_e7e8_22_ff;
+extern cpuop_func op_e7f0_22_nf;
+extern cpuop_func op_e7f0_22_ff;
+extern cpuop_func op_e7f8_22_nf;
+extern cpuop_func op_e7f8_22_ff;
+extern cpuop_func op_e7f9_22_nf;
+extern cpuop_func op_e7f9_22_ff;
+extern cpuop_func op_e8c0_22_nf;
+extern cpuop_func op_e8c0_22_ff;
+extern cpuop_func op_e8d0_22_nf;
+extern cpuop_func op_e8d0_22_ff;
+extern cpuop_func op_e8e8_22_nf;
+extern cpuop_func op_e8e8_22_ff;
+extern cpuop_func op_e8f0_22_nf;
+extern cpuop_func op_e8f0_22_ff;
+extern cpuop_func op_e8f8_22_nf;
+extern cpuop_func op_e8f8_22_ff;
+extern cpuop_func op_e8f9_22_nf;
+extern cpuop_func op_e8f9_22_ff;
+extern cpuop_func op_e8fa_22_nf;
+extern cpuop_func op_e8fa_22_ff;
+extern cpuop_func op_e8fb_22_nf;
+extern cpuop_func op_e8fb_22_ff;
+extern cpuop_func op_e9c0_22_nf;
+extern cpuop_func op_e9c0_22_ff;
+extern cpuop_func op_e9d0_22_nf;
+extern cpuop_func op_e9d0_22_ff;
+extern cpuop_func op_e9e8_22_nf;
+extern cpuop_func op_e9e8_22_ff;
+extern cpuop_func op_e9f0_22_nf;
+extern cpuop_func op_e9f0_22_ff;
+extern cpuop_func op_e9f8_22_nf;
+extern cpuop_func op_e9f8_22_ff;
+extern cpuop_func op_e9f9_22_nf;
+extern cpuop_func op_e9f9_22_ff;
+extern cpuop_func op_e9fa_22_nf;
+extern cpuop_func op_e9fa_22_ff;
+extern cpuop_func op_e9fb_22_nf;
+extern cpuop_func op_e9fb_22_ff;
+extern cpuop_func op_eac0_22_nf;
+extern cpuop_func op_eac0_22_ff;
+extern cpuop_func op_ead0_22_nf;
+extern cpuop_func op_ead0_22_ff;
+extern cpuop_func op_eae8_22_nf;
+extern cpuop_func op_eae8_22_ff;
+extern cpuop_func op_eaf0_22_nf;
+extern cpuop_func op_eaf0_22_ff;
+extern cpuop_func op_eaf8_22_nf;
+extern cpuop_func op_eaf8_22_ff;
+extern cpuop_func op_eaf9_22_nf;
+extern cpuop_func op_eaf9_22_ff;
+extern cpuop_func op_ebc0_22_nf;
+extern cpuop_func op_ebc0_22_ff;
+extern cpuop_func op_ebd0_22_nf;
+extern cpuop_func op_ebd0_22_ff;
+extern cpuop_func op_ebe8_22_nf;
+extern cpuop_func op_ebe8_22_ff;
+extern cpuop_func op_ebf0_22_nf;
+extern cpuop_func op_ebf0_22_ff;
+extern cpuop_func op_ebf8_22_nf;
+extern cpuop_func op_ebf8_22_ff;
+extern cpuop_func op_ebf9_22_nf;
+extern cpuop_func op_ebf9_22_ff;
+extern cpuop_func op_ebfa_22_nf;
+extern cpuop_func op_ebfa_22_ff;
+extern cpuop_func op_ebfb_22_nf;
+extern cpuop_func op_ebfb_22_ff;
+extern cpuop_func op_ecc0_22_nf;
+extern cpuop_func op_ecc0_22_ff;
+extern cpuop_func op_ecd0_22_nf;
+extern cpuop_func op_ecd0_22_ff;
+extern cpuop_func op_ece8_22_nf;
+extern cpuop_func op_ece8_22_ff;
+extern cpuop_func op_ecf0_22_nf;
+extern cpuop_func op_ecf0_22_ff;
+extern cpuop_func op_ecf8_22_nf;
+extern cpuop_func op_ecf8_22_ff;
+extern cpuop_func op_ecf9_22_nf;
+extern cpuop_func op_ecf9_22_ff;
+extern cpuop_func op_edc0_22_nf;
+extern cpuop_func op_edc0_22_ff;
+extern cpuop_func op_edd0_22_nf;
+extern cpuop_func op_edd0_22_ff;
+extern cpuop_func op_ede8_22_nf;
+extern cpuop_func op_ede8_22_ff;
+extern cpuop_func op_edf0_22_nf;
+extern cpuop_func op_edf0_22_ff;
+extern cpuop_func op_edf8_22_nf;
+extern cpuop_func op_edf8_22_ff;
+extern cpuop_func op_edf9_22_nf;
+extern cpuop_func op_edf9_22_ff;
+extern cpuop_func op_edfa_22_nf;
+extern cpuop_func op_edfa_22_ff;
+extern cpuop_func op_edfb_22_nf;
+extern cpuop_func op_edfb_22_ff;
+extern cpuop_func op_eec0_22_nf;
+extern cpuop_func op_eec0_22_ff;
+extern cpuop_func op_eed0_22_nf;
+extern cpuop_func op_eed0_22_ff;
+extern cpuop_func op_eee8_22_nf;
+extern cpuop_func op_eee8_22_ff;
+extern cpuop_func op_eef0_22_nf;
+extern cpuop_func op_eef0_22_ff;
+extern cpuop_func op_eef8_22_nf;
+extern cpuop_func op_eef8_22_ff;
+extern cpuop_func op_eef9_22_nf;
+extern cpuop_func op_eef9_22_ff;
+extern cpuop_func op_efc0_22_nf;
+extern cpuop_func op_efc0_22_ff;
+extern cpuop_func op_efd0_22_nf;
+extern cpuop_func op_efd0_22_ff;
+extern cpuop_func op_efe8_22_nf;
+extern cpuop_func op_efe8_22_ff;
+extern cpuop_func op_eff0_22_nf;
+extern cpuop_func op_eff0_22_ff;
+extern cpuop_func op_eff8_22_nf;
+extern cpuop_func op_eff8_22_ff;
+extern cpuop_func op_eff9_22_nf;
+extern cpuop_func op_eff9_22_ff;
+extern cpuop_func op_f000_22_nf;
+extern cpuop_func op_f000_22_ff;
+extern cpuop_func op_f008_22_nf;
+extern cpuop_func op_f008_22_ff;
+extern cpuop_func op_f010_22_nf;
+extern cpuop_func op_f010_22_ff;
+extern cpuop_func op_f018_22_nf;
+extern cpuop_func op_f018_22_ff;
+extern cpuop_func op_f020_22_nf;
+extern cpuop_func op_f020_22_ff;
+extern cpuop_func op_f028_22_nf;
+extern cpuop_func op_f028_22_ff;
+extern cpuop_func op_f030_22_nf;
+extern cpuop_func op_f030_22_ff;
+extern cpuop_func op_f038_22_nf;
+extern cpuop_func op_f038_22_ff;
+extern cpuop_func op_f039_22_nf;
+extern cpuop_func op_f039_22_ff;
+extern cpuop_func op_f200_22_nf;
+extern cpuop_func op_f200_22_ff;
+extern cpuop_func op_f208_22_nf;
+extern cpuop_func op_f208_22_ff;
+extern cpuop_func op_f210_22_nf;
+extern cpuop_func op_f210_22_ff;
+extern cpuop_func op_f218_22_nf;
+extern cpuop_func op_f218_22_ff;
+extern cpuop_func op_f220_22_nf;
+extern cpuop_func op_f220_22_ff;
+extern cpuop_func op_f228_22_nf;
+extern cpuop_func op_f228_22_ff;
+extern cpuop_func op_f230_22_nf;
+extern cpuop_func op_f230_22_ff;
+extern cpuop_func op_f238_22_nf;
+extern cpuop_func op_f238_22_ff;
+extern cpuop_func op_f239_22_nf;
+extern cpuop_func op_f239_22_ff;
+extern cpuop_func op_f23a_22_nf;
+extern cpuop_func op_f23a_22_ff;
+extern cpuop_func op_f23b_22_nf;
+extern cpuop_func op_f23b_22_ff;
+extern cpuop_func op_f23c_22_nf;
+extern cpuop_func op_f23c_22_ff;
+extern cpuop_func op_f240_22_nf;
+extern cpuop_func op_f240_22_ff;
+extern cpuop_func op_f248_22_nf;
+extern cpuop_func op_f248_22_ff;
+extern cpuop_func op_f250_22_nf;
+extern cpuop_func op_f250_22_ff;
+extern cpuop_func op_f258_22_nf;
+extern cpuop_func op_f258_22_ff;
+extern cpuop_func op_f260_22_nf;
+extern cpuop_func op_f260_22_ff;
+extern cpuop_func op_f268_22_nf;
+extern cpuop_func op_f268_22_ff;
+extern cpuop_func op_f270_22_nf;
+extern cpuop_func op_f270_22_ff;
+extern cpuop_func op_f278_22_nf;
+extern cpuop_func op_f278_22_ff;
+extern cpuop_func op_f279_22_nf;
+extern cpuop_func op_f279_22_ff;
+extern cpuop_func op_f27a_22_nf;
+extern cpuop_func op_f27a_22_ff;
+extern cpuop_func op_f27b_22_nf;
+extern cpuop_func op_f27b_22_ff;
+extern cpuop_func op_f27c_22_nf;
+extern cpuop_func op_f27c_22_ff;
+extern cpuop_func op_f280_22_nf;
+extern cpuop_func op_f280_22_ff;
+extern cpuop_func op_f2c0_22_nf;
+extern cpuop_func op_f2c0_22_ff;
+extern cpuop_func op_f310_22_nf;
+extern cpuop_func op_f310_22_ff;
+extern cpuop_func op_f320_22_nf;
+extern cpuop_func op_f320_22_ff;
+extern cpuop_func op_f328_22_nf;
+extern cpuop_func op_f328_22_ff;
+extern cpuop_func op_f330_22_nf;
+extern cpuop_func op_f330_22_ff;
+extern cpuop_func op_f338_22_nf;
+extern cpuop_func op_f338_22_ff;
+extern cpuop_func op_f339_22_nf;
+extern cpuop_func op_f339_22_ff;
+extern cpuop_func op_f350_22_nf;
+extern cpuop_func op_f350_22_ff;
+extern cpuop_func op_f358_22_nf;
+extern cpuop_func op_f358_22_ff;
+extern cpuop_func op_f368_22_nf;
+extern cpuop_func op_f368_22_ff;
+extern cpuop_func op_f370_22_nf;
+extern cpuop_func op_f370_22_ff;
+extern cpuop_func op_f378_22_nf;
+extern cpuop_func op_f378_22_ff;
+extern cpuop_func op_f379_22_nf;
+extern cpuop_func op_f379_22_ff;
+extern cpuop_func op_f37a_22_nf;
+extern cpuop_func op_f37a_22_ff;
+extern cpuop_func op_f37b_22_nf;
+extern cpuop_func op_f37b_22_ff;
+extern cpuop_func_ce op_0000_23_nf;
+extern cpuop_func_ce op_0000_23_ff;
+extern cpuop_func_ce op_0010_23_nf;
+extern cpuop_func_ce op_0010_23_ff;
+extern cpuop_func_ce op_0018_23_nf;
+extern cpuop_func_ce op_0018_23_ff;
+extern cpuop_func_ce op_0020_23_nf;
+extern cpuop_func_ce op_0020_23_ff;
+extern cpuop_func_ce op_0028_23_nf;
+extern cpuop_func_ce op_0028_23_ff;
+extern cpuop_func_ce op_0030_23_nf;
+extern cpuop_func_ce op_0030_23_ff;
+extern cpuop_func_ce op_0038_23_nf;
+extern cpuop_func_ce op_0038_23_ff;
+extern cpuop_func_ce op_0039_23_nf;
+extern cpuop_func_ce op_0039_23_ff;
+extern cpuop_func_ce op_003c_23_nf;
+extern cpuop_func_ce op_003c_23_ff;
+extern cpuop_func_ce op_0040_23_nf;
+extern cpuop_func_ce op_0040_23_ff;
+extern cpuop_func_ce op_0050_23_nf;
+extern cpuop_func_ce op_0050_23_ff;
+extern cpuop_func_ce op_0058_23_nf;
+extern cpuop_func_ce op_0058_23_ff;
+extern cpuop_func_ce op_0060_23_nf;
+extern cpuop_func_ce op_0060_23_ff;
+extern cpuop_func_ce op_0068_23_nf;
+extern cpuop_func_ce op_0068_23_ff;
+extern cpuop_func_ce op_0070_23_nf;
+extern cpuop_func_ce op_0070_23_ff;
+extern cpuop_func_ce op_0078_23_nf;
+extern cpuop_func_ce op_0078_23_ff;
+extern cpuop_func_ce op_0079_23_nf;
+extern cpuop_func_ce op_0079_23_ff;
+extern cpuop_func_ce op_007c_23_nf;
+extern cpuop_func_ce op_007c_23_ff;
+extern cpuop_func_ce op_0080_23_nf;
+extern cpuop_func_ce op_0080_23_ff;
+extern cpuop_func_ce op_0090_23_nf;
+extern cpuop_func_ce op_0090_23_ff;
+extern cpuop_func_ce op_0098_23_nf;
+extern cpuop_func_ce op_0098_23_ff;
+extern cpuop_func_ce op_00a0_23_nf;
+extern cpuop_func_ce op_00a0_23_ff;
+extern cpuop_func_ce op_00a8_23_nf;
+extern cpuop_func_ce op_00a8_23_ff;
+extern cpuop_func_ce op_00b0_23_nf;
+extern cpuop_func_ce op_00b0_23_ff;
+extern cpuop_func_ce op_00b8_23_nf;
+extern cpuop_func_ce op_00b8_23_ff;
+extern cpuop_func_ce op_00b9_23_nf;
+extern cpuop_func_ce op_00b9_23_ff;
+extern cpuop_func_ce op_00d0_23_nf;
+extern cpuop_func_ce op_00d0_23_ff;
+extern cpuop_func_ce op_00e8_23_nf;
+extern cpuop_func_ce op_00e8_23_ff;
+extern cpuop_func_ce op_00f0_23_nf;
+extern cpuop_func_ce op_00f0_23_ff;
+extern cpuop_func_ce op_00f8_23_nf;
+extern cpuop_func_ce op_00f8_23_ff;
+extern cpuop_func_ce op_00f9_23_nf;
+extern cpuop_func_ce op_00f9_23_ff;
+extern cpuop_func_ce op_00fa_23_nf;
+extern cpuop_func_ce op_00fa_23_ff;
+extern cpuop_func_ce op_00fb_23_nf;
+extern cpuop_func_ce op_00fb_23_ff;
+extern cpuop_func_ce op_0100_23_nf;
+extern cpuop_func_ce op_0100_23_ff;
+extern cpuop_func_ce op_0108_23_nf;
+extern cpuop_func_ce op_0108_23_ff;
+extern cpuop_func_ce op_0110_23_nf;
+extern cpuop_func_ce op_0110_23_ff;
+extern cpuop_func_ce op_0118_23_nf;
+extern cpuop_func_ce op_0118_23_ff;
+extern cpuop_func_ce op_0120_23_nf;
+extern cpuop_func_ce op_0120_23_ff;
+extern cpuop_func_ce op_0128_23_nf;
+extern cpuop_func_ce op_0128_23_ff;
+extern cpuop_func_ce op_0130_23_nf;
+extern cpuop_func_ce op_0130_23_ff;
+extern cpuop_func_ce op_0138_23_nf;
+extern cpuop_func_ce op_0138_23_ff;
+extern cpuop_func_ce op_0139_23_nf;
+extern cpuop_func_ce op_0139_23_ff;
+extern cpuop_func_ce op_013a_23_nf;
+extern cpuop_func_ce op_013a_23_ff;
+extern cpuop_func_ce op_013b_23_nf;
+extern cpuop_func_ce op_013b_23_ff;
+extern cpuop_func_ce op_013c_23_nf;
+extern cpuop_func_ce op_013c_23_ff;
+extern cpuop_func_ce op_0140_23_nf;
+extern cpuop_func_ce op_0140_23_ff;
+extern cpuop_func_ce op_0148_23_nf;
+extern cpuop_func_ce op_0148_23_ff;
+extern cpuop_func_ce op_0150_23_nf;
+extern cpuop_func_ce op_0150_23_ff;
+extern cpuop_func_ce op_0158_23_nf;
+extern cpuop_func_ce op_0158_23_ff;
+extern cpuop_func_ce op_0160_23_nf;
+extern cpuop_func_ce op_0160_23_ff;
+extern cpuop_func_ce op_0168_23_nf;
+extern cpuop_func_ce op_0168_23_ff;
+extern cpuop_func_ce op_0170_23_nf;
+extern cpuop_func_ce op_0170_23_ff;
+extern cpuop_func_ce op_0178_23_nf;
+extern cpuop_func_ce op_0178_23_ff;
+extern cpuop_func_ce op_0179_23_nf;
+extern cpuop_func_ce op_0179_23_ff;
+extern cpuop_func_ce op_0180_23_nf;
+extern cpuop_func_ce op_0180_23_ff;
+extern cpuop_func_ce op_0188_23_nf;
+extern cpuop_func_ce op_0188_23_ff;
+extern cpuop_func_ce op_0190_23_nf;
+extern cpuop_func_ce op_0190_23_ff;
+extern cpuop_func_ce op_0198_23_nf;
+extern cpuop_func_ce op_0198_23_ff;
+extern cpuop_func_ce op_01a0_23_nf;
+extern cpuop_func_ce op_01a0_23_ff;
+extern cpuop_func_ce op_01a8_23_nf;
+extern cpuop_func_ce op_01a8_23_ff;
+extern cpuop_func_ce op_01b0_23_nf;
+extern cpuop_func_ce op_01b0_23_ff;
+extern cpuop_func_ce op_01b8_23_nf;
+extern cpuop_func_ce op_01b8_23_ff;
+extern cpuop_func_ce op_01b9_23_nf;
+extern cpuop_func_ce op_01b9_23_ff;
+extern cpuop_func_ce op_01c0_23_nf;
+extern cpuop_func_ce op_01c0_23_ff;
+extern cpuop_func_ce op_01c8_23_nf;
+extern cpuop_func_ce op_01c8_23_ff;
+extern cpuop_func_ce op_01d0_23_nf;
+extern cpuop_func_ce op_01d0_23_ff;
+extern cpuop_func_ce op_01d8_23_nf;
+extern cpuop_func_ce op_01d8_23_ff;
+extern cpuop_func_ce op_01e0_23_nf;
+extern cpuop_func_ce op_01e0_23_ff;
+extern cpuop_func_ce op_01e8_23_nf;
+extern cpuop_func_ce op_01e8_23_ff;
+extern cpuop_func_ce op_01f0_23_nf;
+extern cpuop_func_ce op_01f0_23_ff;
+extern cpuop_func_ce op_01f8_23_nf;
+extern cpuop_func_ce op_01f8_23_ff;
+extern cpuop_func_ce op_01f9_23_nf;
+extern cpuop_func_ce op_01f9_23_ff;
+extern cpuop_func_ce op_0200_23_nf;
+extern cpuop_func_ce op_0200_23_ff;
+extern cpuop_func_ce op_0210_23_nf;
+extern cpuop_func_ce op_0210_23_ff;
+extern cpuop_func_ce op_0218_23_nf;
+extern cpuop_func_ce op_0218_23_ff;
+extern cpuop_func_ce op_0220_23_nf;
+extern cpuop_func_ce op_0220_23_ff;
+extern cpuop_func_ce op_0228_23_nf;
+extern cpuop_func_ce op_0228_23_ff;
+extern cpuop_func_ce op_0230_23_nf;
+extern cpuop_func_ce op_0230_23_ff;
+extern cpuop_func_ce op_0238_23_nf;
+extern cpuop_func_ce op_0238_23_ff;
+extern cpuop_func_ce op_0239_23_nf;
+extern cpuop_func_ce op_0239_23_ff;
+extern cpuop_func_ce op_023c_23_nf;
+extern cpuop_func_ce op_023c_23_ff;
+extern cpuop_func_ce op_0240_23_nf;
+extern cpuop_func_ce op_0240_23_ff;
+extern cpuop_func_ce op_0250_23_nf;
+extern cpuop_func_ce op_0250_23_ff;
+extern cpuop_func_ce op_0258_23_nf;
+extern cpuop_func_ce op_0258_23_ff;
+extern cpuop_func_ce op_0260_23_nf;
+extern cpuop_func_ce op_0260_23_ff;
+extern cpuop_func_ce op_0268_23_nf;
+extern cpuop_func_ce op_0268_23_ff;
+extern cpuop_func_ce op_0270_23_nf;
+extern cpuop_func_ce op_0270_23_ff;
+extern cpuop_func_ce op_0278_23_nf;
+extern cpuop_func_ce op_0278_23_ff;
+extern cpuop_func_ce op_0279_23_nf;
+extern cpuop_func_ce op_0279_23_ff;
+extern cpuop_func_ce op_027c_23_nf;
+extern cpuop_func_ce op_027c_23_ff;
+extern cpuop_func_ce op_0280_23_nf;
+extern cpuop_func_ce op_0280_23_ff;
+extern cpuop_func_ce op_0290_23_nf;
+extern cpuop_func_ce op_0290_23_ff;
+extern cpuop_func_ce op_0298_23_nf;
+extern cpuop_func_ce op_0298_23_ff;
+extern cpuop_func_ce op_02a0_23_nf;
+extern cpuop_func_ce op_02a0_23_ff;
+extern cpuop_func_ce op_02a8_23_nf;
+extern cpuop_func_ce op_02a8_23_ff;
+extern cpuop_func_ce op_02b0_23_nf;
+extern cpuop_func_ce op_02b0_23_ff;
+extern cpuop_func_ce op_02b8_23_nf;
+extern cpuop_func_ce op_02b8_23_ff;
+extern cpuop_func_ce op_02b9_23_nf;
+extern cpuop_func_ce op_02b9_23_ff;
+extern cpuop_func_ce op_02d0_23_nf;
+extern cpuop_func_ce op_02d0_23_ff;
+extern cpuop_func_ce op_02e8_23_nf;
+extern cpuop_func_ce op_02e8_23_ff;
+extern cpuop_func_ce op_02f0_23_nf;
+extern cpuop_func_ce op_02f0_23_ff;
+extern cpuop_func_ce op_02f8_23_nf;
+extern cpuop_func_ce op_02f8_23_ff;
+extern cpuop_func_ce op_02f9_23_nf;
+extern cpuop_func_ce op_02f9_23_ff;
+extern cpuop_func_ce op_02fa_23_nf;
+extern cpuop_func_ce op_02fa_23_ff;
+extern cpuop_func_ce op_02fb_23_nf;
+extern cpuop_func_ce op_02fb_23_ff;
+extern cpuop_func_ce op_0400_23_nf;
+extern cpuop_func_ce op_0400_23_ff;
+extern cpuop_func_ce op_0410_23_nf;
+extern cpuop_func_ce op_0410_23_ff;
+extern cpuop_func_ce op_0418_23_nf;
+extern cpuop_func_ce op_0418_23_ff;
+extern cpuop_func_ce op_0420_23_nf;
+extern cpuop_func_ce op_0420_23_ff;
+extern cpuop_func_ce op_0428_23_nf;
+extern cpuop_func_ce op_0428_23_ff;
+extern cpuop_func_ce op_0430_23_nf;
+extern cpuop_func_ce op_0430_23_ff;
+extern cpuop_func_ce op_0438_23_nf;
+extern cpuop_func_ce op_0438_23_ff;
+extern cpuop_func_ce op_0439_23_nf;
+extern cpuop_func_ce op_0439_23_ff;
+extern cpuop_func_ce op_0440_23_nf;
+extern cpuop_func_ce op_0440_23_ff;
+extern cpuop_func_ce op_0450_23_nf;
+extern cpuop_func_ce op_0450_23_ff;
+extern cpuop_func_ce op_0458_23_nf;
+extern cpuop_func_ce op_0458_23_ff;
+extern cpuop_func_ce op_0460_23_nf;
+extern cpuop_func_ce op_0460_23_ff;
+extern cpuop_func_ce op_0468_23_nf;
+extern cpuop_func_ce op_0468_23_ff;
+extern cpuop_func_ce op_0470_23_nf;
+extern cpuop_func_ce op_0470_23_ff;
+extern cpuop_func_ce op_0478_23_nf;
+extern cpuop_func_ce op_0478_23_ff;
+extern cpuop_func_ce op_0479_23_nf;
+extern cpuop_func_ce op_0479_23_ff;
+extern cpuop_func_ce op_0480_23_nf;
+extern cpuop_func_ce op_0480_23_ff;
+extern cpuop_func_ce op_0490_23_nf;
+extern cpuop_func_ce op_0490_23_ff;
+extern cpuop_func_ce op_0498_23_nf;
+extern cpuop_func_ce op_0498_23_ff;
+extern cpuop_func_ce op_04a0_23_nf;
+extern cpuop_func_ce op_04a0_23_ff;
+extern cpuop_func_ce op_04a8_23_nf;
+extern cpuop_func_ce op_04a8_23_ff;
+extern cpuop_func_ce op_04b0_23_nf;
+extern cpuop_func_ce op_04b0_23_ff;
+extern cpuop_func_ce op_04b8_23_nf;
+extern cpuop_func_ce op_04b8_23_ff;
+extern cpuop_func_ce op_04b9_23_nf;
+extern cpuop_func_ce op_04b9_23_ff;
+extern cpuop_func_ce op_04d0_23_nf;
+extern cpuop_func_ce op_04d0_23_ff;
+extern cpuop_func_ce op_04e8_23_nf;
+extern cpuop_func_ce op_04e8_23_ff;
+extern cpuop_func_ce op_04f0_23_nf;
+extern cpuop_func_ce op_04f0_23_ff;
+extern cpuop_func_ce op_04f8_23_nf;
+extern cpuop_func_ce op_04f8_23_ff;
+extern cpuop_func_ce op_04f9_23_nf;
+extern cpuop_func_ce op_04f9_23_ff;
+extern cpuop_func_ce op_04fa_23_nf;
+extern cpuop_func_ce op_04fa_23_ff;
+extern cpuop_func_ce op_04fb_23_nf;
+extern cpuop_func_ce op_04fb_23_ff;
+extern cpuop_func_ce op_0600_23_nf;
+extern cpuop_func_ce op_0600_23_ff;
+extern cpuop_func_ce op_0610_23_nf;
+extern cpuop_func_ce op_0610_23_ff;
+extern cpuop_func_ce op_0618_23_nf;
+extern cpuop_func_ce op_0618_23_ff;
+extern cpuop_func_ce op_0620_23_nf;
+extern cpuop_func_ce op_0620_23_ff;
+extern cpuop_func_ce op_0628_23_nf;
+extern cpuop_func_ce op_0628_23_ff;
+extern cpuop_func_ce op_0630_23_nf;
+extern cpuop_func_ce op_0630_23_ff;
+extern cpuop_func_ce op_0638_23_nf;
+extern cpuop_func_ce op_0638_23_ff;
+extern cpuop_func_ce op_0639_23_nf;
+extern cpuop_func_ce op_0639_23_ff;
+extern cpuop_func_ce op_0640_23_nf;
+extern cpuop_func_ce op_0640_23_ff;
+extern cpuop_func_ce op_0650_23_nf;
+extern cpuop_func_ce op_0650_23_ff;
+extern cpuop_func_ce op_0658_23_nf;
+extern cpuop_func_ce op_0658_23_ff;
+extern cpuop_func_ce op_0660_23_nf;
+extern cpuop_func_ce op_0660_23_ff;
+extern cpuop_func_ce op_0668_23_nf;
+extern cpuop_func_ce op_0668_23_ff;
+extern cpuop_func_ce op_0670_23_nf;
+extern cpuop_func_ce op_0670_23_ff;
+extern cpuop_func_ce op_0678_23_nf;
+extern cpuop_func_ce op_0678_23_ff;
+extern cpuop_func_ce op_0679_23_nf;
+extern cpuop_func_ce op_0679_23_ff;
+extern cpuop_func_ce op_0680_23_nf;
+extern cpuop_func_ce op_0680_23_ff;
+extern cpuop_func_ce op_0690_23_nf;
+extern cpuop_func_ce op_0690_23_ff;
+extern cpuop_func_ce op_0698_23_nf;
+extern cpuop_func_ce op_0698_23_ff;
+extern cpuop_func_ce op_06a0_23_nf;
+extern cpuop_func_ce op_06a0_23_ff;
+extern cpuop_func_ce op_06a8_23_nf;
+extern cpuop_func_ce op_06a8_23_ff;
+extern cpuop_func_ce op_06b0_23_nf;
+extern cpuop_func_ce op_06b0_23_ff;
+extern cpuop_func_ce op_06b8_23_nf;
+extern cpuop_func_ce op_06b8_23_ff;
+extern cpuop_func_ce op_06b9_23_nf;
+extern cpuop_func_ce op_06b9_23_ff;
+extern cpuop_func_ce op_06c0_23_nf;
+extern cpuop_func_ce op_06c0_23_ff;
+extern cpuop_func_ce op_06c8_23_nf;
+extern cpuop_func_ce op_06c8_23_ff;
+extern cpuop_func_ce op_06d0_23_nf;
+extern cpuop_func_ce op_06d0_23_ff;
+extern cpuop_func_ce op_06e8_23_nf;
+extern cpuop_func_ce op_06e8_23_ff;
+extern cpuop_func_ce op_06f0_23_nf;
+extern cpuop_func_ce op_06f0_23_ff;
+extern cpuop_func_ce op_06f8_23_nf;
+extern cpuop_func_ce op_06f8_23_ff;
+extern cpuop_func_ce op_06f9_23_nf;
+extern cpuop_func_ce op_06f9_23_ff;
+extern cpuop_func_ce op_06fa_23_nf;
+extern cpuop_func_ce op_06fa_23_ff;
+extern cpuop_func_ce op_06fb_23_nf;
+extern cpuop_func_ce op_06fb_23_ff;
+extern cpuop_func_ce op_0800_23_nf;
+extern cpuop_func_ce op_0800_23_ff;
+extern cpuop_func_ce op_0810_23_nf;
+extern cpuop_func_ce op_0810_23_ff;
+extern cpuop_func_ce op_0818_23_nf;
+extern cpuop_func_ce op_0818_23_ff;
+extern cpuop_func_ce op_0820_23_nf;
+extern cpuop_func_ce op_0820_23_ff;
+extern cpuop_func_ce op_0828_23_nf;
+extern cpuop_func_ce op_0828_23_ff;
+extern cpuop_func_ce op_0830_23_nf;
+extern cpuop_func_ce op_0830_23_ff;
+extern cpuop_func_ce op_0838_23_nf;
+extern cpuop_func_ce op_0838_23_ff;
+extern cpuop_func_ce op_0839_23_nf;
+extern cpuop_func_ce op_0839_23_ff;
+extern cpuop_func_ce op_083a_23_nf;
+extern cpuop_func_ce op_083a_23_ff;
+extern cpuop_func_ce op_083b_23_nf;
+extern cpuop_func_ce op_083b_23_ff;
+extern cpuop_func_ce op_0840_23_nf;
+extern cpuop_func_ce op_0840_23_ff;
+extern cpuop_func_ce op_0850_23_nf;
+extern cpuop_func_ce op_0850_23_ff;
+extern cpuop_func_ce op_0858_23_nf;
+extern cpuop_func_ce op_0858_23_ff;
+extern cpuop_func_ce op_0860_23_nf;
+extern cpuop_func_ce op_0860_23_ff;
+extern cpuop_func_ce op_0868_23_nf;
+extern cpuop_func_ce op_0868_23_ff;
+extern cpuop_func_ce op_0870_23_nf;
+extern cpuop_func_ce op_0870_23_ff;
+extern cpuop_func_ce op_0878_23_nf;
+extern cpuop_func_ce op_0878_23_ff;
+extern cpuop_func_ce op_0879_23_nf;
+extern cpuop_func_ce op_0879_23_ff;
+extern cpuop_func_ce op_0880_23_nf;
+extern cpuop_func_ce op_0880_23_ff;
+extern cpuop_func_ce op_0890_23_nf;
+extern cpuop_func_ce op_0890_23_ff;
+extern cpuop_func_ce op_0898_23_nf;
+extern cpuop_func_ce op_0898_23_ff;
+extern cpuop_func_ce op_08a0_23_nf;
+extern cpuop_func_ce op_08a0_23_ff;
+extern cpuop_func_ce op_08a8_23_nf;
+extern cpuop_func_ce op_08a8_23_ff;
+extern cpuop_func_ce op_08b0_23_nf;
+extern cpuop_func_ce op_08b0_23_ff;
+extern cpuop_func_ce op_08b8_23_nf;
+extern cpuop_func_ce op_08b8_23_ff;
+extern cpuop_func_ce op_08b9_23_nf;
+extern cpuop_func_ce op_08b9_23_ff;
+extern cpuop_func_ce op_08c0_23_nf;
+extern cpuop_func_ce op_08c0_23_ff;
+extern cpuop_func_ce op_08d0_23_nf;
+extern cpuop_func_ce op_08d0_23_ff;
+extern cpuop_func_ce op_08d8_23_nf;
+extern cpuop_func_ce op_08d8_23_ff;
+extern cpuop_func_ce op_08e0_23_nf;
+extern cpuop_func_ce op_08e0_23_ff;
+extern cpuop_func_ce op_08e8_23_nf;
+extern cpuop_func_ce op_08e8_23_ff;
+extern cpuop_func_ce op_08f0_23_nf;
+extern cpuop_func_ce op_08f0_23_ff;
+extern cpuop_func_ce op_08f8_23_nf;
+extern cpuop_func_ce op_08f8_23_ff;
+extern cpuop_func_ce op_08f9_23_nf;
+extern cpuop_func_ce op_08f9_23_ff;
+extern cpuop_func_ce op_0a00_23_nf;
+extern cpuop_func_ce op_0a00_23_ff;
+extern cpuop_func_ce op_0a10_23_nf;
+extern cpuop_func_ce op_0a10_23_ff;
+extern cpuop_func_ce op_0a18_23_nf;
+extern cpuop_func_ce op_0a18_23_ff;
+extern cpuop_func_ce op_0a20_23_nf;
+extern cpuop_func_ce op_0a20_23_ff;
+extern cpuop_func_ce op_0a28_23_nf;
+extern cpuop_func_ce op_0a28_23_ff;
+extern cpuop_func_ce op_0a30_23_nf;
+extern cpuop_func_ce op_0a30_23_ff;
+extern cpuop_func_ce op_0a38_23_nf;
+extern cpuop_func_ce op_0a38_23_ff;
+extern cpuop_func_ce op_0a39_23_nf;
+extern cpuop_func_ce op_0a39_23_ff;
+extern cpuop_func_ce op_0a3c_23_nf;
+extern cpuop_func_ce op_0a3c_23_ff;
+extern cpuop_func_ce op_0a40_23_nf;
+extern cpuop_func_ce op_0a40_23_ff;
+extern cpuop_func_ce op_0a50_23_nf;
+extern cpuop_func_ce op_0a50_23_ff;
+extern cpuop_func_ce op_0a58_23_nf;
+extern cpuop_func_ce op_0a58_23_ff;
+extern cpuop_func_ce op_0a60_23_nf;
+extern cpuop_func_ce op_0a60_23_ff;
+extern cpuop_func_ce op_0a68_23_nf;
+extern cpuop_func_ce op_0a68_23_ff;
+extern cpuop_func_ce op_0a70_23_nf;
+extern cpuop_func_ce op_0a70_23_ff;
+extern cpuop_func_ce op_0a78_23_nf;
+extern cpuop_func_ce op_0a78_23_ff;
+extern cpuop_func_ce op_0a79_23_nf;
+extern cpuop_func_ce op_0a79_23_ff;
+extern cpuop_func_ce op_0a7c_23_nf;
+extern cpuop_func_ce op_0a7c_23_ff;
+extern cpuop_func_ce op_0a80_23_nf;
+extern cpuop_func_ce op_0a80_23_ff;
+extern cpuop_func_ce op_0a90_23_nf;
+extern cpuop_func_ce op_0a90_23_ff;
+extern cpuop_func_ce op_0a98_23_nf;
+extern cpuop_func_ce op_0a98_23_ff;
+extern cpuop_func_ce op_0aa0_23_nf;
+extern cpuop_func_ce op_0aa0_23_ff;
+extern cpuop_func_ce op_0aa8_23_nf;
+extern cpuop_func_ce op_0aa8_23_ff;
+extern cpuop_func_ce op_0ab0_23_nf;
+extern cpuop_func_ce op_0ab0_23_ff;
+extern cpuop_func_ce op_0ab8_23_nf;
+extern cpuop_func_ce op_0ab8_23_ff;
+extern cpuop_func_ce op_0ab9_23_nf;
+extern cpuop_func_ce op_0ab9_23_ff;
+extern cpuop_func_ce op_0ad0_23_nf;
+extern cpuop_func_ce op_0ad0_23_ff;
+extern cpuop_func_ce op_0ad8_23_nf;
+extern cpuop_func_ce op_0ad8_23_ff;
+extern cpuop_func_ce op_0ae0_23_nf;
+extern cpuop_func_ce op_0ae0_23_ff;
+extern cpuop_func_ce op_0ae8_23_nf;
+extern cpuop_func_ce op_0ae8_23_ff;
+extern cpuop_func_ce op_0af0_23_nf;
+extern cpuop_func_ce op_0af0_23_ff;
+extern cpuop_func_ce op_0af8_23_nf;
+extern cpuop_func_ce op_0af8_23_ff;
+extern cpuop_func_ce op_0af9_23_nf;
+extern cpuop_func_ce op_0af9_23_ff;
+extern cpuop_func_ce op_0c00_23_nf;
+extern cpuop_func_ce op_0c00_23_ff;
+extern cpuop_func_ce op_0c10_23_nf;
+extern cpuop_func_ce op_0c10_23_ff;
+extern cpuop_func_ce op_0c18_23_nf;
+extern cpuop_func_ce op_0c18_23_ff;
+extern cpuop_func_ce op_0c20_23_nf;
+extern cpuop_func_ce op_0c20_23_ff;
+extern cpuop_func_ce op_0c28_23_nf;
+extern cpuop_func_ce op_0c28_23_ff;
+extern cpuop_func_ce op_0c30_23_nf;
+extern cpuop_func_ce op_0c30_23_ff;
+extern cpuop_func_ce op_0c38_23_nf;
+extern cpuop_func_ce op_0c38_23_ff;
+extern cpuop_func_ce op_0c39_23_nf;
+extern cpuop_func_ce op_0c39_23_ff;
+extern cpuop_func_ce op_0c3a_23_nf;
+extern cpuop_func_ce op_0c3a_23_ff;
+extern cpuop_func_ce op_0c3b_23_nf;
+extern cpuop_func_ce op_0c3b_23_ff;
+extern cpuop_func_ce op_0c40_23_nf;
+extern cpuop_func_ce op_0c40_23_ff;
+extern cpuop_func_ce op_0c50_23_nf;
+extern cpuop_func_ce op_0c50_23_ff;
+extern cpuop_func_ce op_0c58_23_nf;
+extern cpuop_func_ce op_0c58_23_ff;
+extern cpuop_func_ce op_0c60_23_nf;
+extern cpuop_func_ce op_0c60_23_ff;
+extern cpuop_func_ce op_0c68_23_nf;
+extern cpuop_func_ce op_0c68_23_ff;
+extern cpuop_func_ce op_0c70_23_nf;
+extern cpuop_func_ce op_0c70_23_ff;
+extern cpuop_func_ce op_0c78_23_nf;
+extern cpuop_func_ce op_0c78_23_ff;
+extern cpuop_func_ce op_0c79_23_nf;
+extern cpuop_func_ce op_0c79_23_ff;
+extern cpuop_func_ce op_0c7a_23_nf;
+extern cpuop_func_ce op_0c7a_23_ff;
+extern cpuop_func_ce op_0c7b_23_nf;
+extern cpuop_func_ce op_0c7b_23_ff;
+extern cpuop_func_ce op_0c80_23_nf;
+extern cpuop_func_ce op_0c80_23_ff;
+extern cpuop_func_ce op_0c90_23_nf;
+extern cpuop_func_ce op_0c90_23_ff;
+extern cpuop_func_ce op_0c98_23_nf;
+extern cpuop_func_ce op_0c98_23_ff;
+extern cpuop_func_ce op_0ca0_23_nf;
+extern cpuop_func_ce op_0ca0_23_ff;
+extern cpuop_func_ce op_0ca8_23_nf;
+extern cpuop_func_ce op_0ca8_23_ff;
+extern cpuop_func_ce op_0cb0_23_nf;
+extern cpuop_func_ce op_0cb0_23_ff;
+extern cpuop_func_ce op_0cb8_23_nf;
+extern cpuop_func_ce op_0cb8_23_ff;
+extern cpuop_func_ce op_0cb9_23_nf;
+extern cpuop_func_ce op_0cb9_23_ff;
+extern cpuop_func_ce op_0cba_23_nf;
+extern cpuop_func_ce op_0cba_23_ff;
+extern cpuop_func_ce op_0cbb_23_nf;
+extern cpuop_func_ce op_0cbb_23_ff;
+extern cpuop_func_ce op_0cd0_23_nf;
+extern cpuop_func_ce op_0cd0_23_ff;
+extern cpuop_func_ce op_0cd8_23_nf;
+extern cpuop_func_ce op_0cd8_23_ff;
+extern cpuop_func_ce op_0ce0_23_nf;
+extern cpuop_func_ce op_0ce0_23_ff;
+extern cpuop_func_ce op_0ce8_23_nf;
+extern cpuop_func_ce op_0ce8_23_ff;
+extern cpuop_func_ce op_0cf0_23_nf;
+extern cpuop_func_ce op_0cf0_23_ff;
+extern cpuop_func_ce op_0cf8_23_nf;
+extern cpuop_func_ce op_0cf8_23_ff;
+extern cpuop_func_ce op_0cf9_23_nf;
+extern cpuop_func_ce op_0cf9_23_ff;
+extern cpuop_func_ce op_0cfc_23_nf;
+extern cpuop_func_ce op_0cfc_23_ff;
+extern cpuop_func_ce op_0e10_23_nf;
+extern cpuop_func_ce op_0e10_23_ff;
+extern cpuop_func_ce op_0e18_23_nf;
+extern cpuop_func_ce op_0e18_23_ff;
+extern cpuop_func_ce op_0e20_23_nf;
+extern cpuop_func_ce op_0e20_23_ff;
+extern cpuop_func_ce op_0e28_23_nf;
+extern cpuop_func_ce op_0e28_23_ff;
+extern cpuop_func_ce op_0e30_23_nf;
+extern cpuop_func_ce op_0e30_23_ff;
+extern cpuop_func_ce op_0e38_23_nf;
+extern cpuop_func_ce op_0e38_23_ff;
+extern cpuop_func_ce op_0e39_23_nf;
+extern cpuop_func_ce op_0e39_23_ff;
+extern cpuop_func_ce op_0e50_23_nf;
+extern cpuop_func_ce op_0e50_23_ff;
+extern cpuop_func_ce op_0e58_23_nf;
+extern cpuop_func_ce op_0e58_23_ff;
+extern cpuop_func_ce op_0e60_23_nf;
+extern cpuop_func_ce op_0e60_23_ff;
+extern cpuop_func_ce op_0e68_23_nf;
+extern cpuop_func_ce op_0e68_23_ff;
+extern cpuop_func_ce op_0e70_23_nf;
+extern cpuop_func_ce op_0e70_23_ff;
+extern cpuop_func_ce op_0e78_23_nf;
+extern cpuop_func_ce op_0e78_23_ff;
+extern cpuop_func_ce op_0e79_23_nf;
+extern cpuop_func_ce op_0e79_23_ff;
+extern cpuop_func_ce op_0e90_23_nf;
+extern cpuop_func_ce op_0e90_23_ff;
+extern cpuop_func_ce op_0e98_23_nf;
+extern cpuop_func_ce op_0e98_23_ff;
+extern cpuop_func_ce op_0ea0_23_nf;
+extern cpuop_func_ce op_0ea0_23_ff;
+extern cpuop_func_ce op_0ea8_23_nf;
+extern cpuop_func_ce op_0ea8_23_ff;
+extern cpuop_func_ce op_0eb0_23_nf;
+extern cpuop_func_ce op_0eb0_23_ff;
+extern cpuop_func_ce op_0eb8_23_nf;
+extern cpuop_func_ce op_0eb8_23_ff;
+extern cpuop_func_ce op_0eb9_23_nf;
+extern cpuop_func_ce op_0eb9_23_ff;
+extern cpuop_func_ce op_0ed0_23_nf;
+extern cpuop_func_ce op_0ed0_23_ff;
+extern cpuop_func_ce op_0ed8_23_nf;
+extern cpuop_func_ce op_0ed8_23_ff;
+extern cpuop_func_ce op_0ee0_23_nf;
+extern cpuop_func_ce op_0ee0_23_ff;
+extern cpuop_func_ce op_0ee8_23_nf;
+extern cpuop_func_ce op_0ee8_23_ff;
+extern cpuop_func_ce op_0ef0_23_nf;
+extern cpuop_func_ce op_0ef0_23_ff;
+extern cpuop_func_ce op_0ef8_23_nf;
+extern cpuop_func_ce op_0ef8_23_ff;
+extern cpuop_func_ce op_0ef9_23_nf;
+extern cpuop_func_ce op_0ef9_23_ff;
+extern cpuop_func_ce op_0efc_23_nf;
+extern cpuop_func_ce op_0efc_23_ff;
+extern cpuop_func_ce op_1000_23_nf;
+extern cpuop_func_ce op_1000_23_ff;
+extern cpuop_func_ce op_1010_23_nf;
+extern cpuop_func_ce op_1010_23_ff;
+extern cpuop_func_ce op_1018_23_nf;
+extern cpuop_func_ce op_1018_23_ff;
+extern cpuop_func_ce op_1020_23_nf;
+extern cpuop_func_ce op_1020_23_ff;
+extern cpuop_func_ce op_1028_23_nf;
+extern cpuop_func_ce op_1028_23_ff;
+extern cpuop_func_ce op_1030_23_nf;
+extern cpuop_func_ce op_1030_23_ff;
+extern cpuop_func_ce op_1038_23_nf;
+extern cpuop_func_ce op_1038_23_ff;
+extern cpuop_func_ce op_1039_23_nf;
+extern cpuop_func_ce op_1039_23_ff;
+extern cpuop_func_ce op_103a_23_nf;
+extern cpuop_func_ce op_103a_23_ff;
+extern cpuop_func_ce op_103b_23_nf;
+extern cpuop_func_ce op_103b_23_ff;
+extern cpuop_func_ce op_103c_23_nf;
+extern cpuop_func_ce op_103c_23_ff;
+extern cpuop_func_ce op_1080_23_nf;
+extern cpuop_func_ce op_1080_23_ff;
+extern cpuop_func_ce op_1090_23_nf;
+extern cpuop_func_ce op_1090_23_ff;
+extern cpuop_func_ce op_1098_23_nf;
+extern cpuop_func_ce op_1098_23_ff;
+extern cpuop_func_ce op_10a0_23_nf;
+extern cpuop_func_ce op_10a0_23_ff;
+extern cpuop_func_ce op_10a8_23_nf;
+extern cpuop_func_ce op_10a8_23_ff;
+extern cpuop_func_ce op_10b0_23_nf;
+extern cpuop_func_ce op_10b0_23_ff;
+extern cpuop_func_ce op_10b8_23_nf;
+extern cpuop_func_ce op_10b8_23_ff;
+extern cpuop_func_ce op_10b9_23_nf;
+extern cpuop_func_ce op_10b9_23_ff;
+extern cpuop_func_ce op_10ba_23_nf;
+extern cpuop_func_ce op_10ba_23_ff;
+extern cpuop_func_ce op_10bb_23_nf;
+extern cpuop_func_ce op_10bb_23_ff;
+extern cpuop_func_ce op_10bc_23_nf;
+extern cpuop_func_ce op_10bc_23_ff;
+extern cpuop_func_ce op_10c0_23_nf;
+extern cpuop_func_ce op_10c0_23_ff;
+extern cpuop_func_ce op_10d0_23_nf;
+extern cpuop_func_ce op_10d0_23_ff;
+extern cpuop_func_ce op_10d8_23_nf;
+extern cpuop_func_ce op_10d8_23_ff;
+extern cpuop_func_ce op_10e0_23_nf;
+extern cpuop_func_ce op_10e0_23_ff;
+extern cpuop_func_ce op_10e8_23_nf;
+extern cpuop_func_ce op_10e8_23_ff;
+extern cpuop_func_ce op_10f0_23_nf;
+extern cpuop_func_ce op_10f0_23_ff;
+extern cpuop_func_ce op_10f8_23_nf;
+extern cpuop_func_ce op_10f8_23_ff;
+extern cpuop_func_ce op_10f9_23_nf;
+extern cpuop_func_ce op_10f9_23_ff;
+extern cpuop_func_ce op_10fa_23_nf;
+extern cpuop_func_ce op_10fa_23_ff;
+extern cpuop_func_ce op_10fb_23_nf;
+extern cpuop_func_ce op_10fb_23_ff;
+extern cpuop_func_ce op_10fc_23_nf;
+extern cpuop_func_ce op_10fc_23_ff;
+extern cpuop_func_ce op_1100_23_nf;
+extern cpuop_func_ce op_1100_23_ff;
+extern cpuop_func_ce op_1110_23_nf;
+extern cpuop_func_ce op_1110_23_ff;
+extern cpuop_func_ce op_1118_23_nf;
+extern cpuop_func_ce op_1118_23_ff;
+extern cpuop_func_ce op_1120_23_nf;
+extern cpuop_func_ce op_1120_23_ff;
+extern cpuop_func_ce op_1128_23_nf;
+extern cpuop_func_ce op_1128_23_ff;
+extern cpuop_func_ce op_1130_23_nf;
+extern cpuop_func_ce op_1130_23_ff;
+extern cpuop_func_ce op_1138_23_nf;
+extern cpuop_func_ce op_1138_23_ff;
+extern cpuop_func_ce op_1139_23_nf;
+extern cpuop_func_ce op_1139_23_ff;
+extern cpuop_func_ce op_113a_23_nf;
+extern cpuop_func_ce op_113a_23_ff;
+extern cpuop_func_ce op_113b_23_nf;
+extern cpuop_func_ce op_113b_23_ff;
+extern cpuop_func_ce op_113c_23_nf;
+extern cpuop_func_ce op_113c_23_ff;
+extern cpuop_func_ce op_1140_23_nf;
+extern cpuop_func_ce op_1140_23_ff;
+extern cpuop_func_ce op_1150_23_nf;
+extern cpuop_func_ce op_1150_23_ff;
+extern cpuop_func_ce op_1158_23_nf;
+extern cpuop_func_ce op_1158_23_ff;
+extern cpuop_func_ce op_1160_23_nf;
+extern cpuop_func_ce op_1160_23_ff;
+extern cpuop_func_ce op_1168_23_nf;
+extern cpuop_func_ce op_1168_23_ff;
+extern cpuop_func_ce op_1170_23_nf;
+extern cpuop_func_ce op_1170_23_ff;
+extern cpuop_func_ce op_1178_23_nf;
+extern cpuop_func_ce op_1178_23_ff;
+extern cpuop_func_ce op_1179_23_nf;
+extern cpuop_func_ce op_1179_23_ff;
+extern cpuop_func_ce op_117a_23_nf;
+extern cpuop_func_ce op_117a_23_ff;
+extern cpuop_func_ce op_117b_23_nf;
+extern cpuop_func_ce op_117b_23_ff;
+extern cpuop_func_ce op_117c_23_nf;
+extern cpuop_func_ce op_117c_23_ff;
+extern cpuop_func_ce op_1180_23_nf;
+extern cpuop_func_ce op_1180_23_ff;
+extern cpuop_func_ce op_1190_23_nf;
+extern cpuop_func_ce op_1190_23_ff;
+extern cpuop_func_ce op_1198_23_nf;
+extern cpuop_func_ce op_1198_23_ff;
+extern cpuop_func_ce op_11a0_23_nf;
+extern cpuop_func_ce op_11a0_23_ff;
+extern cpuop_func_ce op_11a8_23_nf;
+extern cpuop_func_ce op_11a8_23_ff;
+extern cpuop_func_ce op_11b0_23_nf;
+extern cpuop_func_ce op_11b0_23_ff;
+extern cpuop_func_ce op_11b8_23_nf;
+extern cpuop_func_ce op_11b8_23_ff;
+extern cpuop_func_ce op_11b9_23_nf;
+extern cpuop_func_ce op_11b9_23_ff;
+extern cpuop_func_ce op_11ba_23_nf;
+extern cpuop_func_ce op_11ba_23_ff;
+extern cpuop_func_ce op_11bb_23_nf;
+extern cpuop_func_ce op_11bb_23_ff;
+extern cpuop_func_ce op_11bc_23_nf;
+extern cpuop_func_ce op_11bc_23_ff;
+extern cpuop_func_ce op_11c0_23_nf;
+extern cpuop_func_ce op_11c0_23_ff;
+extern cpuop_func_ce op_11d0_23_nf;
+extern cpuop_func_ce op_11d0_23_ff;
+extern cpuop_func_ce op_11d8_23_nf;
+extern cpuop_func_ce op_11d8_23_ff;
+extern cpuop_func_ce op_11e0_23_nf;
+extern cpuop_func_ce op_11e0_23_ff;
+extern cpuop_func_ce op_11e8_23_nf;
+extern cpuop_func_ce op_11e8_23_ff;
+extern cpuop_func_ce op_11f0_23_nf;
+extern cpuop_func_ce op_11f0_23_ff;
+extern cpuop_func_ce op_11f8_23_nf;
+extern cpuop_func_ce op_11f8_23_ff;
+extern cpuop_func_ce op_11f9_23_nf;
+extern cpuop_func_ce op_11f9_23_ff;
+extern cpuop_func_ce op_11fa_23_nf;
+extern cpuop_func_ce op_11fa_23_ff;
+extern cpuop_func_ce op_11fb_23_nf;
+extern cpuop_func_ce op_11fb_23_ff;
+extern cpuop_func_ce op_11fc_23_nf;
+extern cpuop_func_ce op_11fc_23_ff;
+extern cpuop_func_ce op_13c0_23_nf;
+extern cpuop_func_ce op_13c0_23_ff;
+extern cpuop_func_ce op_13d0_23_nf;
+extern cpuop_func_ce op_13d0_23_ff;
+extern cpuop_func_ce op_13d8_23_nf;
+extern cpuop_func_ce op_13d8_23_ff;
+extern cpuop_func_ce op_13e0_23_nf;
+extern cpuop_func_ce op_13e0_23_ff;
+extern cpuop_func_ce op_13e8_23_nf;
+extern cpuop_func_ce op_13e8_23_ff;
+extern cpuop_func_ce op_13f0_23_nf;
+extern cpuop_func_ce op_13f0_23_ff;
+extern cpuop_func_ce op_13f8_23_nf;
+extern cpuop_func_ce op_13f8_23_ff;
+extern cpuop_func_ce op_13f9_23_nf;
+extern cpuop_func_ce op_13f9_23_ff;
+extern cpuop_func_ce op_13fa_23_nf;
+extern cpuop_func_ce op_13fa_23_ff;
+extern cpuop_func_ce op_13fb_23_nf;
+extern cpuop_func_ce op_13fb_23_ff;
+extern cpuop_func_ce op_13fc_23_nf;
+extern cpuop_func_ce op_13fc_23_ff;
+extern cpuop_func_ce op_2000_23_nf;
+extern cpuop_func_ce op_2000_23_ff;
+extern cpuop_func_ce op_2008_23_nf;
+extern cpuop_func_ce op_2008_23_ff;
+extern cpuop_func_ce op_2010_23_nf;
+extern cpuop_func_ce op_2010_23_ff;
+extern cpuop_func_ce op_2018_23_nf;
+extern cpuop_func_ce op_2018_23_ff;
+extern cpuop_func_ce op_2020_23_nf;
+extern cpuop_func_ce op_2020_23_ff;
+extern cpuop_func_ce op_2028_23_nf;
+extern cpuop_func_ce op_2028_23_ff;
+extern cpuop_func_ce op_2030_23_nf;
+extern cpuop_func_ce op_2030_23_ff;
+extern cpuop_func_ce op_2038_23_nf;
+extern cpuop_func_ce op_2038_23_ff;
+extern cpuop_func_ce op_2039_23_nf;
+extern cpuop_func_ce op_2039_23_ff;
+extern cpuop_func_ce op_203a_23_nf;
+extern cpuop_func_ce op_203a_23_ff;
+extern cpuop_func_ce op_203b_23_nf;
+extern cpuop_func_ce op_203b_23_ff;
+extern cpuop_func_ce op_203c_23_nf;
+extern cpuop_func_ce op_203c_23_ff;
+extern cpuop_func_ce op_2040_23_nf;
+extern cpuop_func_ce op_2040_23_ff;
+extern cpuop_func_ce op_2048_23_nf;
+extern cpuop_func_ce op_2048_23_ff;
+extern cpuop_func_ce op_2050_23_nf;
+extern cpuop_func_ce op_2050_23_ff;
+extern cpuop_func_ce op_2058_23_nf;
+extern cpuop_func_ce op_2058_23_ff;
+extern cpuop_func_ce op_2060_23_nf;
+extern cpuop_func_ce op_2060_23_ff;
+extern cpuop_func_ce op_2068_23_nf;
+extern cpuop_func_ce op_2068_23_ff;
+extern cpuop_func_ce op_2070_23_nf;
+extern cpuop_func_ce op_2070_23_ff;
+extern cpuop_func_ce op_2078_23_nf;
+extern cpuop_func_ce op_2078_23_ff;
+extern cpuop_func_ce op_2079_23_nf;
+extern cpuop_func_ce op_2079_23_ff;
+extern cpuop_func_ce op_207a_23_nf;
+extern cpuop_func_ce op_207a_23_ff;
+extern cpuop_func_ce op_207b_23_nf;
+extern cpuop_func_ce op_207b_23_ff;
+extern cpuop_func_ce op_207c_23_nf;
+extern cpuop_func_ce op_207c_23_ff;
+extern cpuop_func_ce op_2080_23_nf;
+extern cpuop_func_ce op_2080_23_ff;
+extern cpuop_func_ce op_2088_23_nf;
+extern cpuop_func_ce op_2088_23_ff;
+extern cpuop_func_ce op_2090_23_nf;
+extern cpuop_func_ce op_2090_23_ff;
+extern cpuop_func_ce op_2098_23_nf;
+extern cpuop_func_ce op_2098_23_ff;
+extern cpuop_func_ce op_20a0_23_nf;
+extern cpuop_func_ce op_20a0_23_ff;
+extern cpuop_func_ce op_20a8_23_nf;
+extern cpuop_func_ce op_20a8_23_ff;
+extern cpuop_func_ce op_20b0_23_nf;
+extern cpuop_func_ce op_20b0_23_ff;
+extern cpuop_func_ce op_20b8_23_nf;
+extern cpuop_func_ce op_20b8_23_ff;
+extern cpuop_func_ce op_20b9_23_nf;
+extern cpuop_func_ce op_20b9_23_ff;
+extern cpuop_func_ce op_20ba_23_nf;
+extern cpuop_func_ce op_20ba_23_ff;
+extern cpuop_func_ce op_20bb_23_nf;
+extern cpuop_func_ce op_20bb_23_ff;
+extern cpuop_func_ce op_20bc_23_nf;
+extern cpuop_func_ce op_20bc_23_ff;
+extern cpuop_func_ce op_20c0_23_nf;
+extern cpuop_func_ce op_20c0_23_ff;
+extern cpuop_func_ce op_20c8_23_nf;
+extern cpuop_func_ce op_20c8_23_ff;
+extern cpuop_func_ce op_20d0_23_nf;
+extern cpuop_func_ce op_20d0_23_ff;
+extern cpuop_func_ce op_20d8_23_nf;
+extern cpuop_func_ce op_20d8_23_ff;
+extern cpuop_func_ce op_20e0_23_nf;
+extern cpuop_func_ce op_20e0_23_ff;
+extern cpuop_func_ce op_20e8_23_nf;
+extern cpuop_func_ce op_20e8_23_ff;
+extern cpuop_func_ce op_20f0_23_nf;
+extern cpuop_func_ce op_20f0_23_ff;
+extern cpuop_func_ce op_20f8_23_nf;
+extern cpuop_func_ce op_20f8_23_ff;
+extern cpuop_func_ce op_20f9_23_nf;
+extern cpuop_func_ce op_20f9_23_ff;
+extern cpuop_func_ce op_20fa_23_nf;
+extern cpuop_func_ce op_20fa_23_ff;
+extern cpuop_func_ce op_20fb_23_nf;
+extern cpuop_func_ce op_20fb_23_ff;
+extern cpuop_func_ce op_20fc_23_nf;
+extern cpuop_func_ce op_20fc_23_ff;
+extern cpuop_func_ce op_2100_23_nf;
+extern cpuop_func_ce op_2100_23_ff;
+extern cpuop_func_ce op_2108_23_nf;
+extern cpuop_func_ce op_2108_23_ff;
+extern cpuop_func_ce op_2110_23_nf;
+extern cpuop_func_ce op_2110_23_ff;
+extern cpuop_func_ce op_2118_23_nf;
+extern cpuop_func_ce op_2118_23_ff;
+extern cpuop_func_ce op_2120_23_nf;
+extern cpuop_func_ce op_2120_23_ff;
+extern cpuop_func_ce op_2128_23_nf;
+extern cpuop_func_ce op_2128_23_ff;
+extern cpuop_func_ce op_2130_23_nf;
+extern cpuop_func_ce op_2130_23_ff;
+extern cpuop_func_ce op_2138_23_nf;
+extern cpuop_func_ce op_2138_23_ff;
+extern cpuop_func_ce op_2139_23_nf;
+extern cpuop_func_ce op_2139_23_ff;
+extern cpuop_func_ce op_213a_23_nf;
+extern cpuop_func_ce op_213a_23_ff;
+extern cpuop_func_ce op_213b_23_nf;
+extern cpuop_func_ce op_213b_23_ff;
+extern cpuop_func_ce op_213c_23_nf;
+extern cpuop_func_ce op_213c_23_ff;
+extern cpuop_func_ce op_2140_23_nf;
+extern cpuop_func_ce op_2140_23_ff;
+extern cpuop_func_ce op_2148_23_nf;
+extern cpuop_func_ce op_2148_23_ff;
+extern cpuop_func_ce op_2150_23_nf;
+extern cpuop_func_ce op_2150_23_ff;
+extern cpuop_func_ce op_2158_23_nf;
+extern cpuop_func_ce op_2158_23_ff;
+extern cpuop_func_ce op_2160_23_nf;
+extern cpuop_func_ce op_2160_23_ff;
+extern cpuop_func_ce op_2168_23_nf;
+extern cpuop_func_ce op_2168_23_ff;
+extern cpuop_func_ce op_2170_23_nf;
+extern cpuop_func_ce op_2170_23_ff;
+extern cpuop_func_ce op_2178_23_nf;
+extern cpuop_func_ce op_2178_23_ff;
+extern cpuop_func_ce op_2179_23_nf;
+extern cpuop_func_ce op_2179_23_ff;
+extern cpuop_func_ce op_217a_23_nf;
+extern cpuop_func_ce op_217a_23_ff;
+extern cpuop_func_ce op_217b_23_nf;
+extern cpuop_func_ce op_217b_23_ff;
+extern cpuop_func_ce op_217c_23_nf;
+extern cpuop_func_ce op_217c_23_ff;
+extern cpuop_func_ce op_2180_23_nf;
+extern cpuop_func_ce op_2180_23_ff;
+extern cpuop_func_ce op_2188_23_nf;
+extern cpuop_func_ce op_2188_23_ff;
+extern cpuop_func_ce op_2190_23_nf;
+extern cpuop_func_ce op_2190_23_ff;
+extern cpuop_func_ce op_2198_23_nf;
+extern cpuop_func_ce op_2198_23_ff;
+extern cpuop_func_ce op_21a0_23_nf;
+extern cpuop_func_ce op_21a0_23_ff;
+extern cpuop_func_ce op_21a8_23_nf;
+extern cpuop_func_ce op_21a8_23_ff;
+extern cpuop_func_ce op_21b0_23_nf;
+extern cpuop_func_ce op_21b0_23_ff;
+extern cpuop_func_ce op_21b8_23_nf;
+extern cpuop_func_ce op_21b8_23_ff;
+extern cpuop_func_ce op_21b9_23_nf;
+extern cpuop_func_ce op_21b9_23_ff;
+extern cpuop_func_ce op_21ba_23_nf;
+extern cpuop_func_ce op_21ba_23_ff;
+extern cpuop_func_ce op_21bb_23_nf;
+extern cpuop_func_ce op_21bb_23_ff;
+extern cpuop_func_ce op_21bc_23_nf;
+extern cpuop_func_ce op_21bc_23_ff;
+extern cpuop_func_ce op_21c0_23_nf;
+extern cpuop_func_ce op_21c0_23_ff;
+extern cpuop_func_ce op_21c8_23_nf;
+extern cpuop_func_ce op_21c8_23_ff;
+extern cpuop_func_ce op_21d0_23_nf;
+extern cpuop_func_ce op_21d0_23_ff;
+extern cpuop_func_ce op_21d8_23_nf;
+extern cpuop_func_ce op_21d8_23_ff;
+extern cpuop_func_ce op_21e0_23_nf;
+extern cpuop_func_ce op_21e0_23_ff;
+extern cpuop_func_ce op_21e8_23_nf;
+extern cpuop_func_ce op_21e8_23_ff;
+extern cpuop_func_ce op_21f0_23_nf;
+extern cpuop_func_ce op_21f0_23_ff;
+extern cpuop_func_ce op_21f8_23_nf;
+extern cpuop_func_ce op_21f8_23_ff;
+extern cpuop_func_ce op_21f9_23_nf;
+extern cpuop_func_ce op_21f9_23_ff;
+extern cpuop_func_ce op_21fa_23_nf;
+extern cpuop_func_ce op_21fa_23_ff;
+extern cpuop_func_ce op_21fb_23_nf;
+extern cpuop_func_ce op_21fb_23_ff;
+extern cpuop_func_ce op_21fc_23_nf;
+extern cpuop_func_ce op_21fc_23_ff;
+extern cpuop_func_ce op_23c0_23_nf;
+extern cpuop_func_ce op_23c0_23_ff;
+extern cpuop_func_ce op_23c8_23_nf;
+extern cpuop_func_ce op_23c8_23_ff;
+extern cpuop_func_ce op_23d0_23_nf;
+extern cpuop_func_ce op_23d0_23_ff;
+extern cpuop_func_ce op_23d8_23_nf;
+extern cpuop_func_ce op_23d8_23_ff;
+extern cpuop_func_ce op_23e0_23_nf;
+extern cpuop_func_ce op_23e0_23_ff;
+extern cpuop_func_ce op_23e8_23_nf;
+extern cpuop_func_ce op_23e8_23_ff;
+extern cpuop_func_ce op_23f0_23_nf;
+extern cpuop_func_ce op_23f0_23_ff;
+extern cpuop_func_ce op_23f8_23_nf;
+extern cpuop_func_ce op_23f8_23_ff;
+extern cpuop_func_ce op_23f9_23_nf;
+extern cpuop_func_ce op_23f9_23_ff;
+extern cpuop_func_ce op_23fa_23_nf;
+extern cpuop_func_ce op_23fa_23_ff;
+extern cpuop_func_ce op_23fb_23_nf;
+extern cpuop_func_ce op_23fb_23_ff;
+extern cpuop_func_ce op_23fc_23_nf;
+extern cpuop_func_ce op_23fc_23_ff;
+extern cpuop_func_ce op_3000_23_nf;
+extern cpuop_func_ce op_3000_23_ff;
+extern cpuop_func_ce op_3008_23_nf;
+extern cpuop_func_ce op_3008_23_ff;
+extern cpuop_func_ce op_3010_23_nf;
+extern cpuop_func_ce op_3010_23_ff;
+extern cpuop_func_ce op_3018_23_nf;
+extern cpuop_func_ce op_3018_23_ff;
+extern cpuop_func_ce op_3020_23_nf;
+extern cpuop_func_ce op_3020_23_ff;
+extern cpuop_func_ce op_3028_23_nf;
+extern cpuop_func_ce op_3028_23_ff;
+extern cpuop_func_ce op_3030_23_nf;
+extern cpuop_func_ce op_3030_23_ff;
+extern cpuop_func_ce op_3038_23_nf;
+extern cpuop_func_ce op_3038_23_ff;
+extern cpuop_func_ce op_3039_23_nf;
+extern cpuop_func_ce op_3039_23_ff;
+extern cpuop_func_ce op_303a_23_nf;
+extern cpuop_func_ce op_303a_23_ff;
+extern cpuop_func_ce op_303b_23_nf;
+extern cpuop_func_ce op_303b_23_ff;
+extern cpuop_func_ce op_303c_23_nf;
+extern cpuop_func_ce op_303c_23_ff;
+extern cpuop_func_ce op_3040_23_nf;
+extern cpuop_func_ce op_3040_23_ff;
+extern cpuop_func_ce op_3048_23_nf;
+extern cpuop_func_ce op_3048_23_ff;
+extern cpuop_func_ce op_3050_23_nf;
+extern cpuop_func_ce op_3050_23_ff;
+extern cpuop_func_ce op_3058_23_nf;
+extern cpuop_func_ce op_3058_23_ff;
+extern cpuop_func_ce op_3060_23_nf;
+extern cpuop_func_ce op_3060_23_ff;
+extern cpuop_func_ce op_3068_23_nf;
+extern cpuop_func_ce op_3068_23_ff;
+extern cpuop_func_ce op_3070_23_nf;
+extern cpuop_func_ce op_3070_23_ff;
+extern cpuop_func_ce op_3078_23_nf;
+extern cpuop_func_ce op_3078_23_ff;
+extern cpuop_func_ce op_3079_23_nf;
+extern cpuop_func_ce op_3079_23_ff;
+extern cpuop_func_ce op_307a_23_nf;
+extern cpuop_func_ce op_307a_23_ff;
+extern cpuop_func_ce op_307b_23_nf;
+extern cpuop_func_ce op_307b_23_ff;
+extern cpuop_func_ce op_307c_23_nf;
+extern cpuop_func_ce op_307c_23_ff;
+extern cpuop_func_ce op_3080_23_nf;
+extern cpuop_func_ce op_3080_23_ff;
+extern cpuop_func_ce op_3088_23_nf;
+extern cpuop_func_ce op_3088_23_ff;
+extern cpuop_func_ce op_3090_23_nf;
+extern cpuop_func_ce op_3090_23_ff;
+extern cpuop_func_ce op_3098_23_nf;
+extern cpuop_func_ce op_3098_23_ff;
+extern cpuop_func_ce op_30a0_23_nf;
+extern cpuop_func_ce op_30a0_23_ff;
+extern cpuop_func_ce op_30a8_23_nf;
+extern cpuop_func_ce op_30a8_23_ff;
+extern cpuop_func_ce op_30b0_23_nf;
+extern cpuop_func_ce op_30b0_23_ff;
+extern cpuop_func_ce op_30b8_23_nf;
+extern cpuop_func_ce op_30b8_23_ff;
+extern cpuop_func_ce op_30b9_23_nf;
+extern cpuop_func_ce op_30b9_23_ff;
+extern cpuop_func_ce op_30ba_23_nf;
+extern cpuop_func_ce op_30ba_23_ff;
+extern cpuop_func_ce op_30bb_23_nf;
+extern cpuop_func_ce op_30bb_23_ff;
+extern cpuop_func_ce op_30bc_23_nf;
+extern cpuop_func_ce op_30bc_23_ff;
+extern cpuop_func_ce op_30c0_23_nf;
+extern cpuop_func_ce op_30c0_23_ff;
+extern cpuop_func_ce op_30c8_23_nf;
+extern cpuop_func_ce op_30c8_23_ff;
+extern cpuop_func_ce op_30d0_23_nf;
+extern cpuop_func_ce op_30d0_23_ff;
+extern cpuop_func_ce op_30d8_23_nf;
+extern cpuop_func_ce op_30d8_23_ff;
+extern cpuop_func_ce op_30e0_23_nf;
+extern cpuop_func_ce op_30e0_23_ff;
+extern cpuop_func_ce op_30e8_23_nf;
+extern cpuop_func_ce op_30e8_23_ff;
+extern cpuop_func_ce op_30f0_23_nf;
+extern cpuop_func_ce op_30f0_23_ff;
+extern cpuop_func_ce op_30f8_23_nf;
+extern cpuop_func_ce op_30f8_23_ff;
+extern cpuop_func_ce op_30f9_23_nf;
+extern cpuop_func_ce op_30f9_23_ff;
+extern cpuop_func_ce op_30fa_23_nf;
+extern cpuop_func_ce op_30fa_23_ff;
+extern cpuop_func_ce op_30fb_23_nf;
+extern cpuop_func_ce op_30fb_23_ff;
+extern cpuop_func_ce op_30fc_23_nf;
+extern cpuop_func_ce op_30fc_23_ff;
+extern cpuop_func_ce op_3100_23_nf;
+extern cpuop_func_ce op_3100_23_ff;
+extern cpuop_func_ce op_3108_23_nf;
+extern cpuop_func_ce op_3108_23_ff;
+extern cpuop_func_ce op_3110_23_nf;
+extern cpuop_func_ce op_3110_23_ff;
+extern cpuop_func_ce op_3118_23_nf;
+extern cpuop_func_ce op_3118_23_ff;
+extern cpuop_func_ce op_3120_23_nf;
+extern cpuop_func_ce op_3120_23_ff;
+extern cpuop_func_ce op_3128_23_nf;
+extern cpuop_func_ce op_3128_23_ff;
+extern cpuop_func_ce op_3130_23_nf;
+extern cpuop_func_ce op_3130_23_ff;
+extern cpuop_func_ce op_3138_23_nf;
+extern cpuop_func_ce op_3138_23_ff;
+extern cpuop_func_ce op_3139_23_nf;
+extern cpuop_func_ce op_3139_23_ff;
+extern cpuop_func_ce op_313a_23_nf;
+extern cpuop_func_ce op_313a_23_ff;
+extern cpuop_func_ce op_313b_23_nf;
+extern cpuop_func_ce op_313b_23_ff;
+extern cpuop_func_ce op_313c_23_nf;
+extern cpuop_func_ce op_313c_23_ff;
+extern cpuop_func_ce op_3140_23_nf;
+extern cpuop_func_ce op_3140_23_ff;
+extern cpuop_func_ce op_3148_23_nf;
+extern cpuop_func_ce op_3148_23_ff;
+extern cpuop_func_ce op_3150_23_nf;
+extern cpuop_func_ce op_3150_23_ff;
+extern cpuop_func_ce op_3158_23_nf;
+extern cpuop_func_ce op_3158_23_ff;
+extern cpuop_func_ce op_3160_23_nf;
+extern cpuop_func_ce op_3160_23_ff;
+extern cpuop_func_ce op_3168_23_nf;
+extern cpuop_func_ce op_3168_23_ff;
+extern cpuop_func_ce op_3170_23_nf;
+extern cpuop_func_ce op_3170_23_ff;
+extern cpuop_func_ce op_3178_23_nf;
+extern cpuop_func_ce op_3178_23_ff;
+extern cpuop_func_ce op_3179_23_nf;
+extern cpuop_func_ce op_3179_23_ff;
+extern cpuop_func_ce op_317a_23_nf;
+extern cpuop_func_ce op_317a_23_ff;
+extern cpuop_func_ce op_317b_23_nf;
+extern cpuop_func_ce op_317b_23_ff;
+extern cpuop_func_ce op_317c_23_nf;
+extern cpuop_func_ce op_317c_23_ff;
+extern cpuop_func_ce op_3180_23_nf;
+extern cpuop_func_ce op_3180_23_ff;
+extern cpuop_func_ce op_3188_23_nf;
+extern cpuop_func_ce op_3188_23_ff;
+extern cpuop_func_ce op_3190_23_nf;
+extern cpuop_func_ce op_3190_23_ff;
+extern cpuop_func_ce op_3198_23_nf;
+extern cpuop_func_ce op_3198_23_ff;
+extern cpuop_func_ce op_31a0_23_nf;
+extern cpuop_func_ce op_31a0_23_ff;
+extern cpuop_func_ce op_31a8_23_nf;
+extern cpuop_func_ce op_31a8_23_ff;
+extern cpuop_func_ce op_31b0_23_nf;
+extern cpuop_func_ce op_31b0_23_ff;
+extern cpuop_func_ce op_31b8_23_nf;
+extern cpuop_func_ce op_31b8_23_ff;
+extern cpuop_func_ce op_31b9_23_nf;
+extern cpuop_func_ce op_31b9_23_ff;
+extern cpuop_func_ce op_31ba_23_nf;
+extern cpuop_func_ce op_31ba_23_ff;
+extern cpuop_func_ce op_31bb_23_nf;
+extern cpuop_func_ce op_31bb_23_ff;
+extern cpuop_func_ce op_31bc_23_nf;
+extern cpuop_func_ce op_31bc_23_ff;
+extern cpuop_func_ce op_31c0_23_nf;
+extern cpuop_func_ce op_31c0_23_ff;
+extern cpuop_func_ce op_31c8_23_nf;
+extern cpuop_func_ce op_31c8_23_ff;
+extern cpuop_func_ce op_31d0_23_nf;
+extern cpuop_func_ce op_31d0_23_ff;
+extern cpuop_func_ce op_31d8_23_nf;
+extern cpuop_func_ce op_31d8_23_ff;
+extern cpuop_func_ce op_31e0_23_nf;
+extern cpuop_func_ce op_31e0_23_ff;
+extern cpuop_func_ce op_31e8_23_nf;
+extern cpuop_func_ce op_31e8_23_ff;
+extern cpuop_func_ce op_31f0_23_nf;
+extern cpuop_func_ce op_31f0_23_ff;
+extern cpuop_func_ce op_31f8_23_nf;
+extern cpuop_func_ce op_31f8_23_ff;
+extern cpuop_func_ce op_31f9_23_nf;
+extern cpuop_func_ce op_31f9_23_ff;
+extern cpuop_func_ce op_31fa_23_nf;
+extern cpuop_func_ce op_31fa_23_ff;
+extern cpuop_func_ce op_31fb_23_nf;
+extern cpuop_func_ce op_31fb_23_ff;
+extern cpuop_func_ce op_31fc_23_nf;
+extern cpuop_func_ce op_31fc_23_ff;
+extern cpuop_func_ce op_33c0_23_nf;
+extern cpuop_func_ce op_33c0_23_ff;
+extern cpuop_func_ce op_33c8_23_nf;
+extern cpuop_func_ce op_33c8_23_ff;
+extern cpuop_func_ce op_33d0_23_nf;
+extern cpuop_func_ce op_33d0_23_ff;
+extern cpuop_func_ce op_33d8_23_nf;
+extern cpuop_func_ce op_33d8_23_ff;
+extern cpuop_func_ce op_33e0_23_nf;
+extern cpuop_func_ce op_33e0_23_ff;
+extern cpuop_func_ce op_33e8_23_nf;
+extern cpuop_func_ce op_33e8_23_ff;
+extern cpuop_func_ce op_33f0_23_nf;
+extern cpuop_func_ce op_33f0_23_ff;
+extern cpuop_func_ce op_33f8_23_nf;
+extern cpuop_func_ce op_33f8_23_ff;
+extern cpuop_func_ce op_33f9_23_nf;
+extern cpuop_func_ce op_33f9_23_ff;
+extern cpuop_func_ce op_33fa_23_nf;
+extern cpuop_func_ce op_33fa_23_ff;
+extern cpuop_func_ce op_33fb_23_nf;
+extern cpuop_func_ce op_33fb_23_ff;
+extern cpuop_func_ce op_33fc_23_nf;
+extern cpuop_func_ce op_33fc_23_ff;
+extern cpuop_func_ce op_4000_23_nf;
+extern cpuop_func_ce op_4000_23_ff;
+extern cpuop_func_ce op_4010_23_nf;
+extern cpuop_func_ce op_4010_23_ff;
+extern cpuop_func_ce op_4018_23_nf;
+extern cpuop_func_ce op_4018_23_ff;
+extern cpuop_func_ce op_4020_23_nf;
+extern cpuop_func_ce op_4020_23_ff;
+extern cpuop_func_ce op_4028_23_nf;
+extern cpuop_func_ce op_4028_23_ff;
+extern cpuop_func_ce op_4030_23_nf;
+extern cpuop_func_ce op_4030_23_ff;
+extern cpuop_func_ce op_4038_23_nf;
+extern cpuop_func_ce op_4038_23_ff;
+extern cpuop_func_ce op_4039_23_nf;
+extern cpuop_func_ce op_4039_23_ff;
+extern cpuop_func_ce op_4040_23_nf;
+extern cpuop_func_ce op_4040_23_ff;
+extern cpuop_func_ce op_4050_23_nf;
+extern cpuop_func_ce op_4050_23_ff;
+extern cpuop_func_ce op_4058_23_nf;
+extern cpuop_func_ce op_4058_23_ff;
+extern cpuop_func_ce op_4060_23_nf;
+extern cpuop_func_ce op_4060_23_ff;
+extern cpuop_func_ce op_4068_23_nf;
+extern cpuop_func_ce op_4068_23_ff;
+extern cpuop_func_ce op_4070_23_nf;
+extern cpuop_func_ce op_4070_23_ff;
+extern cpuop_func_ce op_4078_23_nf;
+extern cpuop_func_ce op_4078_23_ff;
+extern cpuop_func_ce op_4079_23_nf;
+extern cpuop_func_ce op_4079_23_ff;
+extern cpuop_func_ce op_4080_23_nf;
+extern cpuop_func_ce op_4080_23_ff;
+extern cpuop_func_ce op_4090_23_nf;
+extern cpuop_func_ce op_4090_23_ff;
+extern cpuop_func_ce op_4098_23_nf;
+extern cpuop_func_ce op_4098_23_ff;
+extern cpuop_func_ce op_40a0_23_nf;
+extern cpuop_func_ce op_40a0_23_ff;
+extern cpuop_func_ce op_40a8_23_nf;
+extern cpuop_func_ce op_40a8_23_ff;
+extern cpuop_func_ce op_40b0_23_nf;
+extern cpuop_func_ce op_40b0_23_ff;
+extern cpuop_func_ce op_40b8_23_nf;
+extern cpuop_func_ce op_40b8_23_ff;
+extern cpuop_func_ce op_40b9_23_nf;
+extern cpuop_func_ce op_40b9_23_ff;
+extern cpuop_func_ce op_40c0_23_nf;
+extern cpuop_func_ce op_40c0_23_ff;
+extern cpuop_func_ce op_40d0_23_nf;
+extern cpuop_func_ce op_40d0_23_ff;
+extern cpuop_func_ce op_40d8_23_nf;
+extern cpuop_func_ce op_40d8_23_ff;
+extern cpuop_func_ce op_40e0_23_nf;
+extern cpuop_func_ce op_40e0_23_ff;
+extern cpuop_func_ce op_40e8_23_nf;
+extern cpuop_func_ce op_40e8_23_ff;
+extern cpuop_func_ce op_40f0_23_nf;
+extern cpuop_func_ce op_40f0_23_ff;
+extern cpuop_func_ce op_40f8_23_nf;
+extern cpuop_func_ce op_40f8_23_ff;
+extern cpuop_func_ce op_40f9_23_nf;
+extern cpuop_func_ce op_40f9_23_ff;
+extern cpuop_func_ce op_4100_23_nf;
+extern cpuop_func_ce op_4100_23_ff;
+extern cpuop_func_ce op_4110_23_nf;
+extern cpuop_func_ce op_4110_23_ff;
+extern cpuop_func_ce op_4118_23_nf;
+extern cpuop_func_ce op_4118_23_ff;
+extern cpuop_func_ce op_4120_23_nf;
+extern cpuop_func_ce op_4120_23_ff;
+extern cpuop_func_ce op_4128_23_nf;
+extern cpuop_func_ce op_4128_23_ff;
+extern cpuop_func_ce op_4130_23_nf;
+extern cpuop_func_ce op_4130_23_ff;
+extern cpuop_func_ce op_4138_23_nf;
+extern cpuop_func_ce op_4138_23_ff;
+extern cpuop_func_ce op_4139_23_nf;
+extern cpuop_func_ce op_4139_23_ff;
+extern cpuop_func_ce op_413a_23_nf;
+extern cpuop_func_ce op_413a_23_ff;
+extern cpuop_func_ce op_413b_23_nf;
+extern cpuop_func_ce op_413b_23_ff;
+extern cpuop_func_ce op_413c_23_nf;
+extern cpuop_func_ce op_413c_23_ff;
+extern cpuop_func_ce op_4180_23_nf;
+extern cpuop_func_ce op_4180_23_ff;
+extern cpuop_func_ce op_4190_23_nf;
+extern cpuop_func_ce op_4190_23_ff;
+extern cpuop_func_ce op_4198_23_nf;
+extern cpuop_func_ce op_4198_23_ff;
+extern cpuop_func_ce op_41a0_23_nf;
+extern cpuop_func_ce op_41a0_23_ff;
+extern cpuop_func_ce op_41a8_23_nf;
+extern cpuop_func_ce op_41a8_23_ff;
+extern cpuop_func_ce op_41b0_23_nf;
+extern cpuop_func_ce op_41b0_23_ff;
+extern cpuop_func_ce op_41b8_23_nf;
+extern cpuop_func_ce op_41b8_23_ff;
+extern cpuop_func_ce op_41b9_23_nf;
+extern cpuop_func_ce op_41b9_23_ff;
+extern cpuop_func_ce op_41ba_23_nf;
+extern cpuop_func_ce op_41ba_23_ff;
+extern cpuop_func_ce op_41bb_23_nf;
+extern cpuop_func_ce op_41bb_23_ff;
+extern cpuop_func_ce op_41bc_23_nf;
+extern cpuop_func_ce op_41bc_23_ff;
+extern cpuop_func_ce op_41d0_23_nf;
+extern cpuop_func_ce op_41d0_23_ff;
+extern cpuop_func_ce op_41e8_23_nf;
+extern cpuop_func_ce op_41e8_23_ff;
+extern cpuop_func_ce op_41f0_23_nf;
+extern cpuop_func_ce op_41f0_23_ff;
+extern cpuop_func_ce op_41f8_23_nf;
+extern cpuop_func_ce op_41f8_23_ff;
+extern cpuop_func_ce op_41f9_23_nf;
+extern cpuop_func_ce op_41f9_23_ff;
+extern cpuop_func_ce op_41fa_23_nf;
+extern cpuop_func_ce op_41fa_23_ff;
+extern cpuop_func_ce op_41fb_23_nf;
+extern cpuop_func_ce op_41fb_23_ff;
+extern cpuop_func_ce op_4200_23_nf;
+extern cpuop_func_ce op_4200_23_ff;
+extern cpuop_func_ce op_4210_23_nf;
+extern cpuop_func_ce op_4210_23_ff;
+extern cpuop_func_ce op_4218_23_nf;
+extern cpuop_func_ce op_4218_23_ff;
+extern cpuop_func_ce op_4220_23_nf;
+extern cpuop_func_ce op_4220_23_ff;
+extern cpuop_func_ce op_4228_23_nf;
+extern cpuop_func_ce op_4228_23_ff;
+extern cpuop_func_ce op_4230_23_nf;
+extern cpuop_func_ce op_4230_23_ff;
+extern cpuop_func_ce op_4238_23_nf;
+extern cpuop_func_ce op_4238_23_ff;
+extern cpuop_func_ce op_4239_23_nf;
+extern cpuop_func_ce op_4239_23_ff;
+extern cpuop_func_ce op_4240_23_nf;
+extern cpuop_func_ce op_4240_23_ff;
+extern cpuop_func_ce op_4250_23_nf;
+extern cpuop_func_ce op_4250_23_ff;
+extern cpuop_func_ce op_4258_23_nf;
+extern cpuop_func_ce op_4258_23_ff;
+extern cpuop_func_ce op_4260_23_nf;
+extern cpuop_func_ce op_4260_23_ff;
+extern cpuop_func_ce op_4268_23_nf;
+extern cpuop_func_ce op_4268_23_ff;
+extern cpuop_func_ce op_4270_23_nf;
+extern cpuop_func_ce op_4270_23_ff;
+extern cpuop_func_ce op_4278_23_nf;
+extern cpuop_func_ce op_4278_23_ff;
+extern cpuop_func_ce op_4279_23_nf;
+extern cpuop_func_ce op_4279_23_ff;
+extern cpuop_func_ce op_4280_23_nf;
+extern cpuop_func_ce op_4280_23_ff;
+extern cpuop_func_ce op_4290_23_nf;
+extern cpuop_func_ce op_4290_23_ff;
+extern cpuop_func_ce op_4298_23_nf;
+extern cpuop_func_ce op_4298_23_ff;
+extern cpuop_func_ce op_42a0_23_nf;
+extern cpuop_func_ce op_42a0_23_ff;
+extern cpuop_func_ce op_42a8_23_nf;
+extern cpuop_func_ce op_42a8_23_ff;
+extern cpuop_func_ce op_42b0_23_nf;
+extern cpuop_func_ce op_42b0_23_ff;
+extern cpuop_func_ce op_42b8_23_nf;
+extern cpuop_func_ce op_42b8_23_ff;
+extern cpuop_func_ce op_42b9_23_nf;
+extern cpuop_func_ce op_42b9_23_ff;
+extern cpuop_func_ce op_42c0_23_nf;
+extern cpuop_func_ce op_42c0_23_ff;
+extern cpuop_func_ce op_42d0_23_nf;
+extern cpuop_func_ce op_42d0_23_ff;
+extern cpuop_func_ce op_42d8_23_nf;
+extern cpuop_func_ce op_42d8_23_ff;
+extern cpuop_func_ce op_42e0_23_nf;
+extern cpuop_func_ce op_42e0_23_ff;
+extern cpuop_func_ce op_42e8_23_nf;
+extern cpuop_func_ce op_42e8_23_ff;
+extern cpuop_func_ce op_42f0_23_nf;
+extern cpuop_func_ce op_42f0_23_ff;
+extern cpuop_func_ce op_42f8_23_nf;
+extern cpuop_func_ce op_42f8_23_ff;
+extern cpuop_func_ce op_42f9_23_nf;
+extern cpuop_func_ce op_42f9_23_ff;
+extern cpuop_func_ce op_4400_23_nf;
+extern cpuop_func_ce op_4400_23_ff;
+extern cpuop_func_ce op_4410_23_nf;
+extern cpuop_func_ce op_4410_23_ff;
+extern cpuop_func_ce op_4418_23_nf;
+extern cpuop_func_ce op_4418_23_ff;
+extern cpuop_func_ce op_4420_23_nf;
+extern cpuop_func_ce op_4420_23_ff;
+extern cpuop_func_ce op_4428_23_nf;
+extern cpuop_func_ce op_4428_23_ff;
+extern cpuop_func_ce op_4430_23_nf;
+extern cpuop_func_ce op_4430_23_ff;
+extern cpuop_func_ce op_4438_23_nf;
+extern cpuop_func_ce op_4438_23_ff;
+extern cpuop_func_ce op_4439_23_nf;
+extern cpuop_func_ce op_4439_23_ff;
+extern cpuop_func_ce op_4440_23_nf;
+extern cpuop_func_ce op_4440_23_ff;
+extern cpuop_func_ce op_4450_23_nf;
+extern cpuop_func_ce op_4450_23_ff;
+extern cpuop_func_ce op_4458_23_nf;
+extern cpuop_func_ce op_4458_23_ff;
+extern cpuop_func_ce op_4460_23_nf;
+extern cpuop_func_ce op_4460_23_ff;
+extern cpuop_func_ce op_4468_23_nf;
+extern cpuop_func_ce op_4468_23_ff;
+extern cpuop_func_ce op_4470_23_nf;
+extern cpuop_func_ce op_4470_23_ff;
+extern cpuop_func_ce op_4478_23_nf;
+extern cpuop_func_ce op_4478_23_ff;
+extern cpuop_func_ce op_4479_23_nf;
+extern cpuop_func_ce op_4479_23_ff;
+extern cpuop_func_ce op_4480_23_nf;
+extern cpuop_func_ce op_4480_23_ff;
+extern cpuop_func_ce op_4490_23_nf;
+extern cpuop_func_ce op_4490_23_ff;
+extern cpuop_func_ce op_4498_23_nf;
+extern cpuop_func_ce op_4498_23_ff;
+extern cpuop_func_ce op_44a0_23_nf;
+extern cpuop_func_ce op_44a0_23_ff;
+extern cpuop_func_ce op_44a8_23_nf;
+extern cpuop_func_ce op_44a8_23_ff;
+extern cpuop_func_ce op_44b0_23_nf;
+extern cpuop_func_ce op_44b0_23_ff;
+extern cpuop_func_ce op_44b8_23_nf;
+extern cpuop_func_ce op_44b8_23_ff;
+extern cpuop_func_ce op_44b9_23_nf;
+extern cpuop_func_ce op_44b9_23_ff;
+extern cpuop_func_ce op_44c0_23_nf;
+extern cpuop_func_ce op_44c0_23_ff;
+extern cpuop_func_ce op_44d0_23_nf;
+extern cpuop_func_ce op_44d0_23_ff;
+extern cpuop_func_ce op_44d8_23_nf;
+extern cpuop_func_ce op_44d8_23_ff;
+extern cpuop_func_ce op_44e0_23_nf;
+extern cpuop_func_ce op_44e0_23_ff;
+extern cpuop_func_ce op_44e8_23_nf;
+extern cpuop_func_ce op_44e8_23_ff;
+extern cpuop_func_ce op_44f0_23_nf;
+extern cpuop_func_ce op_44f0_23_ff;
+extern cpuop_func_ce op_44f8_23_nf;
+extern cpuop_func_ce op_44f8_23_ff;
+extern cpuop_func_ce op_44f9_23_nf;
+extern cpuop_func_ce op_44f9_23_ff;
+extern cpuop_func_ce op_44fa_23_nf;
+extern cpuop_func_ce op_44fa_23_ff;
+extern cpuop_func_ce op_44fb_23_nf;
+extern cpuop_func_ce op_44fb_23_ff;
+extern cpuop_func_ce op_44fc_23_nf;
+extern cpuop_func_ce op_44fc_23_ff;
+extern cpuop_func_ce op_4600_23_nf;
+extern cpuop_func_ce op_4600_23_ff;
+extern cpuop_func_ce op_4610_23_nf;
+extern cpuop_func_ce op_4610_23_ff;
+extern cpuop_func_ce op_4618_23_nf;
+extern cpuop_func_ce op_4618_23_ff;
+extern cpuop_func_ce op_4620_23_nf;
+extern cpuop_func_ce op_4620_23_ff;
+extern cpuop_func_ce op_4628_23_nf;
+extern cpuop_func_ce op_4628_23_ff;
+extern cpuop_func_ce op_4630_23_nf;
+extern cpuop_func_ce op_4630_23_ff;
+extern cpuop_func_ce op_4638_23_nf;
+extern cpuop_func_ce op_4638_23_ff;
+extern cpuop_func_ce op_4639_23_nf;
+extern cpuop_func_ce op_4639_23_ff;
+extern cpuop_func_ce op_4640_23_nf;
+extern cpuop_func_ce op_4640_23_ff;
+extern cpuop_func_ce op_4650_23_nf;
+extern cpuop_func_ce op_4650_23_ff;
+extern cpuop_func_ce op_4658_23_nf;
+extern cpuop_func_ce op_4658_23_ff;
+extern cpuop_func_ce op_4660_23_nf;
+extern cpuop_func_ce op_4660_23_ff;
+extern cpuop_func_ce op_4668_23_nf;
+extern cpuop_func_ce op_4668_23_ff;
+extern cpuop_func_ce op_4670_23_nf;
+extern cpuop_func_ce op_4670_23_ff;
+extern cpuop_func_ce op_4678_23_nf;
+extern cpuop_func_ce op_4678_23_ff;
+extern cpuop_func_ce op_4679_23_nf;
+extern cpuop_func_ce op_4679_23_ff;
+extern cpuop_func_ce op_4680_23_nf;
+extern cpuop_func_ce op_4680_23_ff;
+extern cpuop_func_ce op_4690_23_nf;
+extern cpuop_func_ce op_4690_23_ff;
+extern cpuop_func_ce op_4698_23_nf;
+extern cpuop_func_ce op_4698_23_ff;
+extern cpuop_func_ce op_46a0_23_nf;
+extern cpuop_func_ce op_46a0_23_ff;
+extern cpuop_func_ce op_46a8_23_nf;
+extern cpuop_func_ce op_46a8_23_ff;
+extern cpuop_func_ce op_46b0_23_nf;
+extern cpuop_func_ce op_46b0_23_ff;
+extern cpuop_func_ce op_46b8_23_nf;
+extern cpuop_func_ce op_46b8_23_ff;
+extern cpuop_func_ce op_46b9_23_nf;
+extern cpuop_func_ce op_46b9_23_ff;
+extern cpuop_func_ce op_46c0_23_nf;
+extern cpuop_func_ce op_46c0_23_ff;
+extern cpuop_func_ce op_46d0_23_nf;
+extern cpuop_func_ce op_46d0_23_ff;
+extern cpuop_func_ce op_46d8_23_nf;
+extern cpuop_func_ce op_46d8_23_ff;
+extern cpuop_func_ce op_46e0_23_nf;
+extern cpuop_func_ce op_46e0_23_ff;
+extern cpuop_func_ce op_46e8_23_nf;
+extern cpuop_func_ce op_46e8_23_ff;
+extern cpuop_func_ce op_46f0_23_nf;
+extern cpuop_func_ce op_46f0_23_ff;
+extern cpuop_func_ce op_46f8_23_nf;
+extern cpuop_func_ce op_46f8_23_ff;
+extern cpuop_func_ce op_46f9_23_nf;
+extern cpuop_func_ce op_46f9_23_ff;
+extern cpuop_func_ce op_46fa_23_nf;
+extern cpuop_func_ce op_46fa_23_ff;
+extern cpuop_func_ce op_46fb_23_nf;
+extern cpuop_func_ce op_46fb_23_ff;
+extern cpuop_func_ce op_46fc_23_nf;
+extern cpuop_func_ce op_46fc_23_ff;
+extern cpuop_func_ce op_4800_23_nf;
+extern cpuop_func_ce op_4800_23_ff;
+extern cpuop_func_ce op_4808_23_nf;
+extern cpuop_func_ce op_4808_23_ff;
+extern cpuop_func_ce op_4810_23_nf;
+extern cpuop_func_ce op_4810_23_ff;
+extern cpuop_func_ce op_4818_23_nf;
+extern cpuop_func_ce op_4818_23_ff;
+extern cpuop_func_ce op_4820_23_nf;
+extern cpuop_func_ce op_4820_23_ff;
+extern cpuop_func_ce op_4828_23_nf;
+extern cpuop_func_ce op_4828_23_ff;
+extern cpuop_func_ce op_4830_23_nf;
+extern cpuop_func_ce op_4830_23_ff;
+extern cpuop_func_ce op_4838_23_nf;
+extern cpuop_func_ce op_4838_23_ff;
+extern cpuop_func_ce op_4839_23_nf;
+extern cpuop_func_ce op_4839_23_ff;
+extern cpuop_func_ce op_4840_23_nf;
+extern cpuop_func_ce op_4840_23_ff;
+extern cpuop_func_ce op_4848_23_nf;
+extern cpuop_func_ce op_4848_23_ff;
+extern cpuop_func_ce op_4850_23_nf;
+extern cpuop_func_ce op_4850_23_ff;
+extern cpuop_func_ce op_4868_23_nf;
+extern cpuop_func_ce op_4868_23_ff;
+extern cpuop_func_ce op_4870_23_nf;
+extern cpuop_func_ce op_4870_23_ff;
+extern cpuop_func_ce op_4878_23_nf;
+extern cpuop_func_ce op_4878_23_ff;
+extern cpuop_func_ce op_4879_23_nf;
+extern cpuop_func_ce op_4879_23_ff;
+extern cpuop_func_ce op_487a_23_nf;
+extern cpuop_func_ce op_487a_23_ff;
+extern cpuop_func_ce op_487b_23_nf;
+extern cpuop_func_ce op_487b_23_ff;
+extern cpuop_func_ce op_4880_23_nf;
+extern cpuop_func_ce op_4880_23_ff;
+extern cpuop_func_ce op_4890_23_nf;
+extern cpuop_func_ce op_4890_23_ff;
+extern cpuop_func_ce op_48a0_23_nf;
+extern cpuop_func_ce op_48a0_23_ff;
+extern cpuop_func_ce op_48a8_23_nf;
+extern cpuop_func_ce op_48a8_23_ff;
+extern cpuop_func_ce op_48b0_23_nf;
+extern cpuop_func_ce op_48b0_23_ff;
+extern cpuop_func_ce op_48b8_23_nf;
+extern cpuop_func_ce op_48b8_23_ff;
+extern cpuop_func_ce op_48b9_23_nf;
+extern cpuop_func_ce op_48b9_23_ff;
+extern cpuop_func_ce op_48c0_23_nf;
+extern cpuop_func_ce op_48c0_23_ff;
+extern cpuop_func_ce op_48d0_23_nf;
+extern cpuop_func_ce op_48d0_23_ff;
+extern cpuop_func_ce op_48e0_23_nf;
+extern cpuop_func_ce op_48e0_23_ff;
+extern cpuop_func_ce op_48e8_23_nf;
+extern cpuop_func_ce op_48e8_23_ff;
+extern cpuop_func_ce op_48f0_23_nf;
+extern cpuop_func_ce op_48f0_23_ff;
+extern cpuop_func_ce op_48f8_23_nf;
+extern cpuop_func_ce op_48f8_23_ff;
+extern cpuop_func_ce op_48f9_23_nf;
+extern cpuop_func_ce op_48f9_23_ff;
+extern cpuop_func_ce op_49c0_23_nf;
+extern cpuop_func_ce op_49c0_23_ff;
+extern cpuop_func_ce op_4a00_23_nf;
+extern cpuop_func_ce op_4a00_23_ff;
+extern cpuop_func_ce op_4a10_23_nf;
+extern cpuop_func_ce op_4a10_23_ff;
+extern cpuop_func_ce op_4a18_23_nf;
+extern cpuop_func_ce op_4a18_23_ff;
+extern cpuop_func_ce op_4a20_23_nf;
+extern cpuop_func_ce op_4a20_23_ff;
+extern cpuop_func_ce op_4a28_23_nf;
+extern cpuop_func_ce op_4a28_23_ff;
+extern cpuop_func_ce op_4a30_23_nf;
+extern cpuop_func_ce op_4a30_23_ff;
+extern cpuop_func_ce op_4a38_23_nf;
+extern cpuop_func_ce op_4a38_23_ff;
+extern cpuop_func_ce op_4a39_23_nf;
+extern cpuop_func_ce op_4a39_23_ff;
+extern cpuop_func_ce op_4a3a_23_nf;
+extern cpuop_func_ce op_4a3a_23_ff;
+extern cpuop_func_ce op_4a3b_23_nf;
+extern cpuop_func_ce op_4a3b_23_ff;
+extern cpuop_func_ce op_4a3c_23_nf;
+extern cpuop_func_ce op_4a3c_23_ff;
+extern cpuop_func_ce op_4a40_23_nf;
+extern cpuop_func_ce op_4a40_23_ff;
+extern cpuop_func_ce op_4a48_23_nf;
+extern cpuop_func_ce op_4a48_23_ff;
+extern cpuop_func_ce op_4a50_23_nf;
+extern cpuop_func_ce op_4a50_23_ff;
+extern cpuop_func_ce op_4a58_23_nf;
+extern cpuop_func_ce op_4a58_23_ff;
+extern cpuop_func_ce op_4a60_23_nf;
+extern cpuop_func_ce op_4a60_23_ff;
+extern cpuop_func_ce op_4a68_23_nf;
+extern cpuop_func_ce op_4a68_23_ff;
+extern cpuop_func_ce op_4a70_23_nf;
+extern cpuop_func_ce op_4a70_23_ff;
+extern cpuop_func_ce op_4a78_23_nf;
+extern cpuop_func_ce op_4a78_23_ff;
+extern cpuop_func_ce op_4a79_23_nf;
+extern cpuop_func_ce op_4a79_23_ff;
+extern cpuop_func_ce op_4a7a_23_nf;
+extern cpuop_func_ce op_4a7a_23_ff;
+extern cpuop_func_ce op_4a7b_23_nf;
+extern cpuop_func_ce op_4a7b_23_ff;
+extern cpuop_func_ce op_4a7c_23_nf;
+extern cpuop_func_ce op_4a7c_23_ff;
+extern cpuop_func_ce op_4a80_23_nf;
+extern cpuop_func_ce op_4a80_23_ff;
+extern cpuop_func_ce op_4a88_23_nf;
+extern cpuop_func_ce op_4a88_23_ff;
+extern cpuop_func_ce op_4a90_23_nf;
+extern cpuop_func_ce op_4a90_23_ff;
+extern cpuop_func_ce op_4a98_23_nf;
+extern cpuop_func_ce op_4a98_23_ff;
+extern cpuop_func_ce op_4aa0_23_nf;
+extern cpuop_func_ce op_4aa0_23_ff;
+extern cpuop_func_ce op_4aa8_23_nf;
+extern cpuop_func_ce op_4aa8_23_ff;
+extern cpuop_func_ce op_4ab0_23_nf;
+extern cpuop_func_ce op_4ab0_23_ff;
+extern cpuop_func_ce op_4ab8_23_nf;
+extern cpuop_func_ce op_4ab8_23_ff;
+extern cpuop_func_ce op_4ab9_23_nf;
+extern cpuop_func_ce op_4ab9_23_ff;
+extern cpuop_func_ce op_4aba_23_nf;
+extern cpuop_func_ce op_4aba_23_ff;
+extern cpuop_func_ce op_4abb_23_nf;
+extern cpuop_func_ce op_4abb_23_ff;
+extern cpuop_func_ce op_4abc_23_nf;
+extern cpuop_func_ce op_4abc_23_ff;
+extern cpuop_func_ce op_4ac0_23_nf;
+extern cpuop_func_ce op_4ac0_23_ff;
+extern cpuop_func_ce op_4ad0_23_nf;
+extern cpuop_func_ce op_4ad0_23_ff;
+extern cpuop_func_ce op_4ad8_23_nf;
+extern cpuop_func_ce op_4ad8_23_ff;
+extern cpuop_func_ce op_4ae0_23_nf;
+extern cpuop_func_ce op_4ae0_23_ff;
+extern cpuop_func_ce op_4ae8_23_nf;
+extern cpuop_func_ce op_4ae8_23_ff;
+extern cpuop_func_ce op_4af0_23_nf;
+extern cpuop_func_ce op_4af0_23_ff;
+extern cpuop_func_ce op_4af8_23_nf;
+extern cpuop_func_ce op_4af8_23_ff;
+extern cpuop_func_ce op_4af9_23_nf;
+extern cpuop_func_ce op_4af9_23_ff;
+extern cpuop_func_ce op_4c00_23_nf;
+extern cpuop_func_ce op_4c00_23_ff;
+extern cpuop_func_ce op_4c10_23_nf;
+extern cpuop_func_ce op_4c10_23_ff;
+extern cpuop_func_ce op_4c18_23_nf;
+extern cpuop_func_ce op_4c18_23_ff;
+extern cpuop_func_ce op_4c20_23_nf;
+extern cpuop_func_ce op_4c20_23_ff;
+extern cpuop_func_ce op_4c28_23_nf;
+extern cpuop_func_ce op_4c28_23_ff;
+extern cpuop_func_ce op_4c30_23_nf;
+extern cpuop_func_ce op_4c30_23_ff;
+extern cpuop_func_ce op_4c38_23_nf;
+extern cpuop_func_ce op_4c38_23_ff;
+extern cpuop_func_ce op_4c39_23_nf;
+extern cpuop_func_ce op_4c39_23_ff;
+extern cpuop_func_ce op_4c3a_23_nf;
+extern cpuop_func_ce op_4c3a_23_ff;
+extern cpuop_func_ce op_4c3b_23_nf;
+extern cpuop_func_ce op_4c3b_23_ff;
+extern cpuop_func_ce op_4c3c_23_nf;
+extern cpuop_func_ce op_4c3c_23_ff;
+extern cpuop_func_ce op_4c40_23_nf;
+extern cpuop_func_ce op_4c40_23_ff;
+extern cpuop_func_ce op_4c50_23_nf;
+extern cpuop_func_ce op_4c50_23_ff;
+extern cpuop_func_ce op_4c58_23_nf;
+extern cpuop_func_ce op_4c58_23_ff;
+extern cpuop_func_ce op_4c60_23_nf;
+extern cpuop_func_ce op_4c60_23_ff;
+extern cpuop_func_ce op_4c68_23_nf;
+extern cpuop_func_ce op_4c68_23_ff;
+extern cpuop_func_ce op_4c70_23_nf;
+extern cpuop_func_ce op_4c70_23_ff;
+extern cpuop_func_ce op_4c78_23_nf;
+extern cpuop_func_ce op_4c78_23_ff;
+extern cpuop_func_ce op_4c79_23_nf;
+extern cpuop_func_ce op_4c79_23_ff;
+extern cpuop_func_ce op_4c7a_23_nf;
+extern cpuop_func_ce op_4c7a_23_ff;
+extern cpuop_func_ce op_4c7b_23_nf;
+extern cpuop_func_ce op_4c7b_23_ff;
+extern cpuop_func_ce op_4c7c_23_nf;
+extern cpuop_func_ce op_4c7c_23_ff;
+extern cpuop_func_ce op_4c90_23_nf;
+extern cpuop_func_ce op_4c90_23_ff;
+extern cpuop_func_ce op_4c98_23_nf;
+extern cpuop_func_ce op_4c98_23_ff;
+extern cpuop_func_ce op_4ca8_23_nf;
+extern cpuop_func_ce op_4ca8_23_ff;
+extern cpuop_func_ce op_4cb0_23_nf;
+extern cpuop_func_ce op_4cb0_23_ff;
+extern cpuop_func_ce op_4cb8_23_nf;
+extern cpuop_func_ce op_4cb8_23_ff;
+extern cpuop_func_ce op_4cb9_23_nf;
+extern cpuop_func_ce op_4cb9_23_ff;
+extern cpuop_func_ce op_4cba_23_nf;
+extern cpuop_func_ce op_4cba_23_ff;
+extern cpuop_func_ce op_4cbb_23_nf;
+extern cpuop_func_ce op_4cbb_23_ff;
+extern cpuop_func_ce op_4cd0_23_nf;
+extern cpuop_func_ce op_4cd0_23_ff;
+extern cpuop_func_ce op_4cd8_23_nf;
+extern cpuop_func_ce op_4cd8_23_ff;
+extern cpuop_func_ce op_4ce8_23_nf;
+extern cpuop_func_ce op_4ce8_23_ff;
+extern cpuop_func_ce op_4cf0_23_nf;
+extern cpuop_func_ce op_4cf0_23_ff;
+extern cpuop_func_ce op_4cf8_23_nf;
+extern cpuop_func_ce op_4cf8_23_ff;
+extern cpuop_func_ce op_4cf9_23_nf;
+extern cpuop_func_ce op_4cf9_23_ff;
+extern cpuop_func_ce op_4cfa_23_nf;
+extern cpuop_func_ce op_4cfa_23_ff;
+extern cpuop_func_ce op_4cfb_23_nf;
+extern cpuop_func_ce op_4cfb_23_ff;
+extern cpuop_func_ce op_4e40_23_nf;
+extern cpuop_func_ce op_4e40_23_ff;
+extern cpuop_func_ce op_4e50_23_nf;
+extern cpuop_func_ce op_4e50_23_ff;
+extern cpuop_func_ce op_4e58_23_nf;
+extern cpuop_func_ce op_4e58_23_ff;
+extern cpuop_func_ce op_4e60_23_nf;
+extern cpuop_func_ce op_4e60_23_ff;
+extern cpuop_func_ce op_4e68_23_nf;
+extern cpuop_func_ce op_4e68_23_ff;
+extern cpuop_func_ce op_4e70_23_nf;
+extern cpuop_func_ce op_4e70_23_ff;
+extern cpuop_func_ce op_4e71_23_nf;
+extern cpuop_func_ce op_4e71_23_ff;
+extern cpuop_func_ce op_4e72_23_nf;
+extern cpuop_func_ce op_4e72_23_ff;
+extern cpuop_func_ce op_4e73_23_nf;
+extern cpuop_func_ce op_4e73_23_ff;
+extern cpuop_func_ce op_4e74_23_nf;
+extern cpuop_func_ce op_4e74_23_ff;
+extern cpuop_func_ce op_4e75_23_nf;
+extern cpuop_func_ce op_4e75_23_ff;
+extern cpuop_func_ce op_4e76_23_nf;
+extern cpuop_func_ce op_4e76_23_ff;
+extern cpuop_func_ce op_4e77_23_nf;
+extern cpuop_func_ce op_4e77_23_ff;
+extern cpuop_func_ce op_4e7a_23_nf;
+extern cpuop_func_ce op_4e7a_23_ff;
+extern cpuop_func_ce op_4e7b_23_nf;
+extern cpuop_func_ce op_4e7b_23_ff;
+extern cpuop_func_ce op_4e90_23_nf;
+extern cpuop_func_ce op_4e90_23_ff;
+extern cpuop_func_ce op_4ea8_23_nf;
+extern cpuop_func_ce op_4ea8_23_ff;
+extern cpuop_func_ce op_4eb0_23_nf;
+extern cpuop_func_ce op_4eb0_23_ff;
+extern cpuop_func_ce op_4eb8_23_nf;
+extern cpuop_func_ce op_4eb8_23_ff;
+extern cpuop_func_ce op_4eb9_23_nf;
+extern cpuop_func_ce op_4eb9_23_ff;
+extern cpuop_func_ce op_4eba_23_nf;
+extern cpuop_func_ce op_4eba_23_ff;
+extern cpuop_func_ce op_4ebb_23_nf;
+extern cpuop_func_ce op_4ebb_23_ff;
+extern cpuop_func_ce op_4ed0_23_nf;
+extern cpuop_func_ce op_4ed0_23_ff;
+extern cpuop_func_ce op_4ee8_23_nf;
+extern cpuop_func_ce op_4ee8_23_ff;
+extern cpuop_func_ce op_4ef0_23_nf;
+extern cpuop_func_ce op_4ef0_23_ff;
+extern cpuop_func_ce op_4ef8_23_nf;
+extern cpuop_func_ce op_4ef8_23_ff;
+extern cpuop_func_ce op_4ef9_23_nf;
+extern cpuop_func_ce op_4ef9_23_ff;
+extern cpuop_func_ce op_4efa_23_nf;
+extern cpuop_func_ce op_4efa_23_ff;
+extern cpuop_func_ce op_4efb_23_nf;
+extern cpuop_func_ce op_4efb_23_ff;
+extern cpuop_func_ce op_5000_23_nf;
+extern cpuop_func_ce op_5000_23_ff;
+extern cpuop_func_ce op_5010_23_nf;
+extern cpuop_func_ce op_5010_23_ff;
+extern cpuop_func_ce op_5018_23_nf;
+extern cpuop_func_ce op_5018_23_ff;
+extern cpuop_func_ce op_5020_23_nf;
+extern cpuop_func_ce op_5020_23_ff;
+extern cpuop_func_ce op_5028_23_nf;
+extern cpuop_func_ce op_5028_23_ff;
+extern cpuop_func_ce op_5030_23_nf;
+extern cpuop_func_ce op_5030_23_ff;
+extern cpuop_func_ce op_5038_23_nf;
+extern cpuop_func_ce op_5038_23_ff;
+extern cpuop_func_ce op_5039_23_nf;
+extern cpuop_func_ce op_5039_23_ff;
+extern cpuop_func_ce op_5040_23_nf;
+extern cpuop_func_ce op_5040_23_ff;
+extern cpuop_func_ce op_5048_23_nf;
+extern cpuop_func_ce op_5048_23_ff;
+extern cpuop_func_ce op_5050_23_nf;
+extern cpuop_func_ce op_5050_23_ff;
+extern cpuop_func_ce op_5058_23_nf;
+extern cpuop_func_ce op_5058_23_ff;
+extern cpuop_func_ce op_5060_23_nf;
+extern cpuop_func_ce op_5060_23_ff;
+extern cpuop_func_ce op_5068_23_nf;
+extern cpuop_func_ce op_5068_23_ff;
+extern cpuop_func_ce op_5070_23_nf;
+extern cpuop_func_ce op_5070_23_ff;
+extern cpuop_func_ce op_5078_23_nf;
+extern cpuop_func_ce op_5078_23_ff;
+extern cpuop_func_ce op_5079_23_nf;
+extern cpuop_func_ce op_5079_23_ff;
+extern cpuop_func_ce op_5080_23_nf;
+extern cpuop_func_ce op_5080_23_ff;
+extern cpuop_func_ce op_5088_23_nf;
+extern cpuop_func_ce op_5088_23_ff;
+extern cpuop_func_ce op_5090_23_nf;
+extern cpuop_func_ce op_5090_23_ff;
+extern cpuop_func_ce op_5098_23_nf;
+extern cpuop_func_ce op_5098_23_ff;
+extern cpuop_func_ce op_50a0_23_nf;
+extern cpuop_func_ce op_50a0_23_ff;
+extern cpuop_func_ce op_50a8_23_nf;
+extern cpuop_func_ce op_50a8_23_ff;
+extern cpuop_func_ce op_50b0_23_nf;
+extern cpuop_func_ce op_50b0_23_ff;
+extern cpuop_func_ce op_50b8_23_nf;
+extern cpuop_func_ce op_50b8_23_ff;
+extern cpuop_func_ce op_50b9_23_nf;
+extern cpuop_func_ce op_50b9_23_ff;
+extern cpuop_func_ce op_50c0_23_nf;
+extern cpuop_func_ce op_50c0_23_ff;
+extern cpuop_func_ce op_50c8_23_nf;
+extern cpuop_func_ce op_50c8_23_ff;
+extern cpuop_func_ce op_50d0_23_nf;
+extern cpuop_func_ce op_50d0_23_ff;
+extern cpuop_func_ce op_50d8_23_nf;
+extern cpuop_func_ce op_50d8_23_ff;
+extern cpuop_func_ce op_50e0_23_nf;
+extern cpuop_func_ce op_50e0_23_ff;
+extern cpuop_func_ce op_50e8_23_nf;
+extern cpuop_func_ce op_50e8_23_ff;
+extern cpuop_func_ce op_50f0_23_nf;
+extern cpuop_func_ce op_50f0_23_ff;
+extern cpuop_func_ce op_50f8_23_nf;
+extern cpuop_func_ce op_50f8_23_ff;
+extern cpuop_func_ce op_50f9_23_nf;
+extern cpuop_func_ce op_50f9_23_ff;
+extern cpuop_func_ce op_50fa_23_nf;
+extern cpuop_func_ce op_50fa_23_ff;
+extern cpuop_func_ce op_50fb_23_nf;
+extern cpuop_func_ce op_50fb_23_ff;
+extern cpuop_func_ce op_50fc_23_nf;
+extern cpuop_func_ce op_50fc_23_ff;
+extern cpuop_func_ce op_5100_23_nf;
+extern cpuop_func_ce op_5100_23_ff;
+extern cpuop_func_ce op_5110_23_nf;
+extern cpuop_func_ce op_5110_23_ff;
+extern cpuop_func_ce op_5118_23_nf;
+extern cpuop_func_ce op_5118_23_ff;
+extern cpuop_func_ce op_5120_23_nf;
+extern cpuop_func_ce op_5120_23_ff;
+extern cpuop_func_ce op_5128_23_nf;
+extern cpuop_func_ce op_5128_23_ff;
+extern cpuop_func_ce op_5130_23_nf;
+extern cpuop_func_ce op_5130_23_ff;
+extern cpuop_func_ce op_5138_23_nf;
+extern cpuop_func_ce op_5138_23_ff;
+extern cpuop_func_ce op_5139_23_nf;
+extern cpuop_func_ce op_5139_23_ff;
+extern cpuop_func_ce op_5140_23_nf;
+extern cpuop_func_ce op_5140_23_ff;
+extern cpuop_func_ce op_5148_23_nf;
+extern cpuop_func_ce op_5148_23_ff;
+extern cpuop_func_ce op_5150_23_nf;
+extern cpuop_func_ce op_5150_23_ff;
+extern cpuop_func_ce op_5158_23_nf;
+extern cpuop_func_ce op_5158_23_ff;
+extern cpuop_func_ce op_5160_23_nf;
+extern cpuop_func_ce op_5160_23_ff;
+extern cpuop_func_ce op_5168_23_nf;
+extern cpuop_func_ce op_5168_23_ff;
+extern cpuop_func_ce op_5170_23_nf;
+extern cpuop_func_ce op_5170_23_ff;
+extern cpuop_func_ce op_5178_23_nf;
+extern cpuop_func_ce op_5178_23_ff;
+extern cpuop_func_ce op_5179_23_nf;
+extern cpuop_func_ce op_5179_23_ff;
+extern cpuop_func_ce op_5180_23_nf;
+extern cpuop_func_ce op_5180_23_ff;
+extern cpuop_func_ce op_5188_23_nf;
+extern cpuop_func_ce op_5188_23_ff;
+extern cpuop_func_ce op_5190_23_nf;
+extern cpuop_func_ce op_5190_23_ff;
+extern cpuop_func_ce op_5198_23_nf;
+extern cpuop_func_ce op_5198_23_ff;
+extern cpuop_func_ce op_51a0_23_nf;
+extern cpuop_func_ce op_51a0_23_ff;
+extern cpuop_func_ce op_51a8_23_nf;
+extern cpuop_func_ce op_51a8_23_ff;
+extern cpuop_func_ce op_51b0_23_nf;
+extern cpuop_func_ce op_51b0_23_ff;
+extern cpuop_func_ce op_51b8_23_nf;
+extern cpuop_func_ce op_51b8_23_ff;
+extern cpuop_func_ce op_51b9_23_nf;
+extern cpuop_func_ce op_51b9_23_ff;
+extern cpuop_func_ce op_51c0_23_nf;
+extern cpuop_func_ce op_51c0_23_ff;
+extern cpuop_func_ce op_51c8_23_nf;
+extern cpuop_func_ce op_51c8_23_ff;
+extern cpuop_func_ce op_51d0_23_nf;
+extern cpuop_func_ce op_51d0_23_ff;
+extern cpuop_func_ce op_51d8_23_nf;
+extern cpuop_func_ce op_51d8_23_ff;
+extern cpuop_func_ce op_51e0_23_nf;
+extern cpuop_func_ce op_51e0_23_ff;
+extern cpuop_func_ce op_51e8_23_nf;
+extern cpuop_func_ce op_51e8_23_ff;
+extern cpuop_func_ce op_51f0_23_nf;
+extern cpuop_func_ce op_51f0_23_ff;
+extern cpuop_func_ce op_51f8_23_nf;
+extern cpuop_func_ce op_51f8_23_ff;
+extern cpuop_func_ce op_51f9_23_nf;
+extern cpuop_func_ce op_51f9_23_ff;
+extern cpuop_func_ce op_51fa_23_nf;
+extern cpuop_func_ce op_51fa_23_ff;
+extern cpuop_func_ce op_51fb_23_nf;
+extern cpuop_func_ce op_51fb_23_ff;
+extern cpuop_func_ce op_51fc_23_nf;
+extern cpuop_func_ce op_51fc_23_ff;
+extern cpuop_func_ce op_52c0_23_nf;
+extern cpuop_func_ce op_52c0_23_ff;
+extern cpuop_func_ce op_52c8_23_nf;
+extern cpuop_func_ce op_52c8_23_ff;
+extern cpuop_func_ce op_52d0_23_nf;
+extern cpuop_func_ce op_52d0_23_ff;
+extern cpuop_func_ce op_52d8_23_nf;
+extern cpuop_func_ce op_52d8_23_ff;
+extern cpuop_func_ce op_52e0_23_nf;
+extern cpuop_func_ce op_52e0_23_ff;
+extern cpuop_func_ce op_52e8_23_nf;
+extern cpuop_func_ce op_52e8_23_ff;
+extern cpuop_func_ce op_52f0_23_nf;
+extern cpuop_func_ce op_52f0_23_ff;
+extern cpuop_func_ce op_52f8_23_nf;
+extern cpuop_func_ce op_52f8_23_ff;
+extern cpuop_func_ce op_52f9_23_nf;
+extern cpuop_func_ce op_52f9_23_ff;
+extern cpuop_func_ce op_52fa_23_nf;
+extern cpuop_func_ce op_52fa_23_ff;
+extern cpuop_func_ce op_52fb_23_nf;
+extern cpuop_func_ce op_52fb_23_ff;
+extern cpuop_func_ce op_52fc_23_nf;
+extern cpuop_func_ce op_52fc_23_ff;
+extern cpuop_func_ce op_53c0_23_nf;
+extern cpuop_func_ce op_53c0_23_ff;
+extern cpuop_func_ce op_53c8_23_nf;
+extern cpuop_func_ce op_53c8_23_ff;
+extern cpuop_func_ce op_53d0_23_nf;
+extern cpuop_func_ce op_53d0_23_ff;
+extern cpuop_func_ce op_53d8_23_nf;
+extern cpuop_func_ce op_53d8_23_ff;
+extern cpuop_func_ce op_53e0_23_nf;
+extern cpuop_func_ce op_53e0_23_ff;
+extern cpuop_func_ce op_53e8_23_nf;
+extern cpuop_func_ce op_53e8_23_ff;
+extern cpuop_func_ce op_53f0_23_nf;
+extern cpuop_func_ce op_53f0_23_ff;
+extern cpuop_func_ce op_53f8_23_nf;
+extern cpuop_func_ce op_53f8_23_ff;
+extern cpuop_func_ce op_53f9_23_nf;
+extern cpuop_func_ce op_53f9_23_ff;
+extern cpuop_func_ce op_53fa_23_nf;
+extern cpuop_func_ce op_53fa_23_ff;
+extern cpuop_func_ce op_53fb_23_nf;
+extern cpuop_func_ce op_53fb_23_ff;
+extern cpuop_func_ce op_53fc_23_nf;
+extern cpuop_func_ce op_53fc_23_ff;
+extern cpuop_func_ce op_54c0_23_nf;
+extern cpuop_func_ce op_54c0_23_ff;
+extern cpuop_func_ce op_54c8_23_nf;
+extern cpuop_func_ce op_54c8_23_ff;
+extern cpuop_func_ce op_54d0_23_nf;
+extern cpuop_func_ce op_54d0_23_ff;
+extern cpuop_func_ce op_54d8_23_nf;
+extern cpuop_func_ce op_54d8_23_ff;
+extern cpuop_func_ce op_54e0_23_nf;
+extern cpuop_func_ce op_54e0_23_ff;
+extern cpuop_func_ce op_54e8_23_nf;
+extern cpuop_func_ce op_54e8_23_ff;
+extern cpuop_func_ce op_54f0_23_nf;
+extern cpuop_func_ce op_54f0_23_ff;
+extern cpuop_func_ce op_54f8_23_nf;
+extern cpuop_func_ce op_54f8_23_ff;
+extern cpuop_func_ce op_54f9_23_nf;
+extern cpuop_func_ce op_54f9_23_ff;
+extern cpuop_func_ce op_54fa_23_nf;
+extern cpuop_func_ce op_54fa_23_ff;
+extern cpuop_func_ce op_54fb_23_nf;
+extern cpuop_func_ce op_54fb_23_ff;
+extern cpuop_func_ce op_54fc_23_nf;
+extern cpuop_func_ce op_54fc_23_ff;
+extern cpuop_func_ce op_55c0_23_nf;
+extern cpuop_func_ce op_55c0_23_ff;
+extern cpuop_func_ce op_55c8_23_nf;
+extern cpuop_func_ce op_55c8_23_ff;
+extern cpuop_func_ce op_55d0_23_nf;
+extern cpuop_func_ce op_55d0_23_ff;
+extern cpuop_func_ce op_55d8_23_nf;
+extern cpuop_func_ce op_55d8_23_ff;
+extern cpuop_func_ce op_55e0_23_nf;
+extern cpuop_func_ce op_55e0_23_ff;
+extern cpuop_func_ce op_55e8_23_nf;
+extern cpuop_func_ce op_55e8_23_ff;
+extern cpuop_func_ce op_55f0_23_nf;
+extern cpuop_func_ce op_55f0_23_ff;
+extern cpuop_func_ce op_55f8_23_nf;
+extern cpuop_func_ce op_55f8_23_ff;
+extern cpuop_func_ce op_55f9_23_nf;
+extern cpuop_func_ce op_55f9_23_ff;
+extern cpuop_func_ce op_55fa_23_nf;
+extern cpuop_func_ce op_55fa_23_ff;
+extern cpuop_func_ce op_55fb_23_nf;
+extern cpuop_func_ce op_55fb_23_ff;
+extern cpuop_func_ce op_55fc_23_nf;
+extern cpuop_func_ce op_55fc_23_ff;
+extern cpuop_func_ce op_56c0_23_nf;
+extern cpuop_func_ce op_56c0_23_ff;
+extern cpuop_func_ce op_56c8_23_nf;
+extern cpuop_func_ce op_56c8_23_ff;
+extern cpuop_func_ce op_56d0_23_nf;
+extern cpuop_func_ce op_56d0_23_ff;
+extern cpuop_func_ce op_56d8_23_nf;
+extern cpuop_func_ce op_56d8_23_ff;
+extern cpuop_func_ce op_56e0_23_nf;
+extern cpuop_func_ce op_56e0_23_ff;
+extern cpuop_func_ce op_56e8_23_nf;
+extern cpuop_func_ce op_56e8_23_ff;
+extern cpuop_func_ce op_56f0_23_nf;
+extern cpuop_func_ce op_56f0_23_ff;
+extern cpuop_func_ce op_56f8_23_nf;
+extern cpuop_func_ce op_56f8_23_ff;
+extern cpuop_func_ce op_56f9_23_nf;
+extern cpuop_func_ce op_56f9_23_ff;
+extern cpuop_func_ce op_56fa_23_nf;
+extern cpuop_func_ce op_56fa_23_ff;
+extern cpuop_func_ce op_56fb_23_nf;
+extern cpuop_func_ce op_56fb_23_ff;
+extern cpuop_func_ce op_56fc_23_nf;
+extern cpuop_func_ce op_56fc_23_ff;
+extern cpuop_func_ce op_57c0_23_nf;
+extern cpuop_func_ce op_57c0_23_ff;
+extern cpuop_func_ce op_57c8_23_nf;
+extern cpuop_func_ce op_57c8_23_ff;
+extern cpuop_func_ce op_57d0_23_nf;
+extern cpuop_func_ce op_57d0_23_ff;
+extern cpuop_func_ce op_57d8_23_nf;
+extern cpuop_func_ce op_57d8_23_ff;
+extern cpuop_func_ce op_57e0_23_nf;
+extern cpuop_func_ce op_57e0_23_ff;
+extern cpuop_func_ce op_57e8_23_nf;
+extern cpuop_func_ce op_57e8_23_ff;
+extern cpuop_func_ce op_57f0_23_nf;
+extern cpuop_func_ce op_57f0_23_ff;
+extern cpuop_func_ce op_57f8_23_nf;
+extern cpuop_func_ce op_57f8_23_ff;
+extern cpuop_func_ce op_57f9_23_nf;
+extern cpuop_func_ce op_57f9_23_ff;
+extern cpuop_func_ce op_57fa_23_nf;
+extern cpuop_func_ce op_57fa_23_ff;
+extern cpuop_func_ce op_57fb_23_nf;
+extern cpuop_func_ce op_57fb_23_ff;
+extern cpuop_func_ce op_57fc_23_nf;
+extern cpuop_func_ce op_57fc_23_ff;
+extern cpuop_func_ce op_58c0_23_nf;
+extern cpuop_func_ce op_58c0_23_ff;
+extern cpuop_func_ce op_58c8_23_nf;
+extern cpuop_func_ce op_58c8_23_ff;
+extern cpuop_func_ce op_58d0_23_nf;
+extern cpuop_func_ce op_58d0_23_ff;
+extern cpuop_func_ce op_58d8_23_nf;
+extern cpuop_func_ce op_58d8_23_ff;
+extern cpuop_func_ce op_58e0_23_nf;
+extern cpuop_func_ce op_58e0_23_ff;
+extern cpuop_func_ce op_58e8_23_nf;
+extern cpuop_func_ce op_58e8_23_ff;
+extern cpuop_func_ce op_58f0_23_nf;
+extern cpuop_func_ce op_58f0_23_ff;
+extern cpuop_func_ce op_58f8_23_nf;
+extern cpuop_func_ce op_58f8_23_ff;
+extern cpuop_func_ce op_58f9_23_nf;
+extern cpuop_func_ce op_58f9_23_ff;
+extern cpuop_func_ce op_58fa_23_nf;
+extern cpuop_func_ce op_58fa_23_ff;
+extern cpuop_func_ce op_58fb_23_nf;
+extern cpuop_func_ce op_58fb_23_ff;
+extern cpuop_func_ce op_58fc_23_nf;
+extern cpuop_func_ce op_58fc_23_ff;
+extern cpuop_func_ce op_59c0_23_nf;
+extern cpuop_func_ce op_59c0_23_ff;
+extern cpuop_func_ce op_59c8_23_nf;
+extern cpuop_func_ce op_59c8_23_ff;
+extern cpuop_func_ce op_59d0_23_nf;
+extern cpuop_func_ce op_59d0_23_ff;
+extern cpuop_func_ce op_59d8_23_nf;
+extern cpuop_func_ce op_59d8_23_ff;
+extern cpuop_func_ce op_59e0_23_nf;
+extern cpuop_func_ce op_59e0_23_ff;
+extern cpuop_func_ce op_59e8_23_nf;
+extern cpuop_func_ce op_59e8_23_ff;
+extern cpuop_func_ce op_59f0_23_nf;
+extern cpuop_func_ce op_59f0_23_ff;
+extern cpuop_func_ce op_59f8_23_nf;
+extern cpuop_func_ce op_59f8_23_ff;
+extern cpuop_func_ce op_59f9_23_nf;
+extern cpuop_func_ce op_59f9_23_ff;
+extern cpuop_func_ce op_59fa_23_nf;
+extern cpuop_func_ce op_59fa_23_ff;
+extern cpuop_func_ce op_59fb_23_nf;
+extern cpuop_func_ce op_59fb_23_ff;
+extern cpuop_func_ce op_59fc_23_nf;
+extern cpuop_func_ce op_59fc_23_ff;
+extern cpuop_func_ce op_5ac0_23_nf;
+extern cpuop_func_ce op_5ac0_23_ff;
+extern cpuop_func_ce op_5ac8_23_nf;
+extern cpuop_func_ce op_5ac8_23_ff;
+extern cpuop_func_ce op_5ad0_23_nf;
+extern cpuop_func_ce op_5ad0_23_ff;
+extern cpuop_func_ce op_5ad8_23_nf;
+extern cpuop_func_ce op_5ad8_23_ff;
+extern cpuop_func_ce op_5ae0_23_nf;
+extern cpuop_func_ce op_5ae0_23_ff;
+extern cpuop_func_ce op_5ae8_23_nf;
+extern cpuop_func_ce op_5ae8_23_ff;
+extern cpuop_func_ce op_5af0_23_nf;
+extern cpuop_func_ce op_5af0_23_ff;
+extern cpuop_func_ce op_5af8_23_nf;
+extern cpuop_func_ce op_5af8_23_ff;
+extern cpuop_func_ce op_5af9_23_nf;
+extern cpuop_func_ce op_5af9_23_ff;
+extern cpuop_func_ce op_5afa_23_nf;
+extern cpuop_func_ce op_5afa_23_ff;
+extern cpuop_func_ce op_5afb_23_nf;
+extern cpuop_func_ce op_5afb_23_ff;
+extern cpuop_func_ce op_5afc_23_nf;
+extern cpuop_func_ce op_5afc_23_ff;
+extern cpuop_func_ce op_5bc0_23_nf;
+extern cpuop_func_ce op_5bc0_23_ff;
+extern cpuop_func_ce op_5bc8_23_nf;
+extern cpuop_func_ce op_5bc8_23_ff;
+extern cpuop_func_ce op_5bd0_23_nf;
+extern cpuop_func_ce op_5bd0_23_ff;
+extern cpuop_func_ce op_5bd8_23_nf;
+extern cpuop_func_ce op_5bd8_23_ff;
+extern cpuop_func_ce op_5be0_23_nf;
+extern cpuop_func_ce op_5be0_23_ff;
+extern cpuop_func_ce op_5be8_23_nf;
+extern cpuop_func_ce op_5be8_23_ff;
+extern cpuop_func_ce op_5bf0_23_nf;
+extern cpuop_func_ce op_5bf0_23_ff;
+extern cpuop_func_ce op_5bf8_23_nf;
+extern cpuop_func_ce op_5bf8_23_ff;
+extern cpuop_func_ce op_5bf9_23_nf;
+extern cpuop_func_ce op_5bf9_23_ff;
+extern cpuop_func_ce op_5bfa_23_nf;
+extern cpuop_func_ce op_5bfa_23_ff;
+extern cpuop_func_ce op_5bfb_23_nf;
+extern cpuop_func_ce op_5bfb_23_ff;
+extern cpuop_func_ce op_5bfc_23_nf;
+extern cpuop_func_ce op_5bfc_23_ff;
+extern cpuop_func_ce op_5cc0_23_nf;
+extern cpuop_func_ce op_5cc0_23_ff;
+extern cpuop_func_ce op_5cc8_23_nf;
+extern cpuop_func_ce op_5cc8_23_ff;
+extern cpuop_func_ce op_5cd0_23_nf;
+extern cpuop_func_ce op_5cd0_23_ff;
+extern cpuop_func_ce op_5cd8_23_nf;
+extern cpuop_func_ce op_5cd8_23_ff;
+extern cpuop_func_ce op_5ce0_23_nf;
+extern cpuop_func_ce op_5ce0_23_ff;
+extern cpuop_func_ce op_5ce8_23_nf;
+extern cpuop_func_ce op_5ce8_23_ff;
+extern cpuop_func_ce op_5cf0_23_nf;
+extern cpuop_func_ce op_5cf0_23_ff;
+extern cpuop_func_ce op_5cf8_23_nf;
+extern cpuop_func_ce op_5cf8_23_ff;
+extern cpuop_func_ce op_5cf9_23_nf;
+extern cpuop_func_ce op_5cf9_23_ff;
+extern cpuop_func_ce op_5cfa_23_nf;
+extern cpuop_func_ce op_5cfa_23_ff;
+extern cpuop_func_ce op_5cfb_23_nf;
+extern cpuop_func_ce op_5cfb_23_ff;
+extern cpuop_func_ce op_5cfc_23_nf;
+extern cpuop_func_ce op_5cfc_23_ff;
+extern cpuop_func_ce op_5dc0_23_nf;
+extern cpuop_func_ce op_5dc0_23_ff;
+extern cpuop_func_ce op_5dc8_23_nf;
+extern cpuop_func_ce op_5dc8_23_ff;
+extern cpuop_func_ce op_5dd0_23_nf;
+extern cpuop_func_ce op_5dd0_23_ff;
+extern cpuop_func_ce op_5dd8_23_nf;
+extern cpuop_func_ce op_5dd8_23_ff;
+extern cpuop_func_ce op_5de0_23_nf;
+extern cpuop_func_ce op_5de0_23_ff;
+extern cpuop_func_ce op_5de8_23_nf;
+extern cpuop_func_ce op_5de8_23_ff;
+extern cpuop_func_ce op_5df0_23_nf;
+extern cpuop_func_ce op_5df0_23_ff;
+extern cpuop_func_ce op_5df8_23_nf;
+extern cpuop_func_ce op_5df8_23_ff;
+extern cpuop_func_ce op_5df9_23_nf;
+extern cpuop_func_ce op_5df9_23_ff;
+extern cpuop_func_ce op_5dfa_23_nf;
+extern cpuop_func_ce op_5dfa_23_ff;
+extern cpuop_func_ce op_5dfb_23_nf;
+extern cpuop_func_ce op_5dfb_23_ff;
+extern cpuop_func_ce op_5dfc_23_nf;
+extern cpuop_func_ce op_5dfc_23_ff;
+extern cpuop_func_ce op_5ec0_23_nf;
+extern cpuop_func_ce op_5ec0_23_ff;
+extern cpuop_func_ce op_5ec8_23_nf;
+extern cpuop_func_ce op_5ec8_23_ff;
+extern cpuop_func_ce op_5ed0_23_nf;
+extern cpuop_func_ce op_5ed0_23_ff;
+extern cpuop_func_ce op_5ed8_23_nf;
+extern cpuop_func_ce op_5ed8_23_ff;
+extern cpuop_func_ce op_5ee0_23_nf;
+extern cpuop_func_ce op_5ee0_23_ff;
+extern cpuop_func_ce op_5ee8_23_nf;
+extern cpuop_func_ce op_5ee8_23_ff;
+extern cpuop_func_ce op_5ef0_23_nf;
+extern cpuop_func_ce op_5ef0_23_ff;
+extern cpuop_func_ce op_5ef8_23_nf;
+extern cpuop_func_ce op_5ef8_23_ff;
+extern cpuop_func_ce op_5ef9_23_nf;
+extern cpuop_func_ce op_5ef9_23_ff;
+extern cpuop_func_ce op_5efa_23_nf;
+extern cpuop_func_ce op_5efa_23_ff;
+extern cpuop_func_ce op_5efb_23_nf;
+extern cpuop_func_ce op_5efb_23_ff;
+extern cpuop_func_ce op_5efc_23_nf;
+extern cpuop_func_ce op_5efc_23_ff;
+extern cpuop_func_ce op_5fc0_23_nf;
+extern cpuop_func_ce op_5fc0_23_ff;
+extern cpuop_func_ce op_5fc8_23_nf;
+extern cpuop_func_ce op_5fc8_23_ff;
+extern cpuop_func_ce op_5fd0_23_nf;
+extern cpuop_func_ce op_5fd0_23_ff;
+extern cpuop_func_ce op_5fd8_23_nf;
+extern cpuop_func_ce op_5fd8_23_ff;
+extern cpuop_func_ce op_5fe0_23_nf;
+extern cpuop_func_ce op_5fe0_23_ff;
+extern cpuop_func_ce op_5fe8_23_nf;
+extern cpuop_func_ce op_5fe8_23_ff;
+extern cpuop_func_ce op_5ff0_23_nf;
+extern cpuop_func_ce op_5ff0_23_ff;
+extern cpuop_func_ce op_5ff8_23_nf;
+extern cpuop_func_ce op_5ff8_23_ff;
+extern cpuop_func_ce op_5ff9_23_nf;
+extern cpuop_func_ce op_5ff9_23_ff;
+extern cpuop_func_ce op_5ffa_23_nf;
+extern cpuop_func_ce op_5ffa_23_ff;
+extern cpuop_func_ce op_5ffb_23_nf;
+extern cpuop_func_ce op_5ffb_23_ff;
+extern cpuop_func_ce op_5ffc_23_nf;
+extern cpuop_func_ce op_5ffc_23_ff;
+extern cpuop_func_ce op_6000_23_nf;
+extern cpuop_func_ce op_6000_23_ff;
+extern cpuop_func_ce op_6001_23_nf;
+extern cpuop_func_ce op_6001_23_ff;
+extern cpuop_func_ce op_60ff_23_nf;
+extern cpuop_func_ce op_60ff_23_ff;
+extern cpuop_func_ce op_6100_23_nf;
+extern cpuop_func_ce op_6100_23_ff;
+extern cpuop_func_ce op_6101_23_nf;
+extern cpuop_func_ce op_6101_23_ff;
+extern cpuop_func_ce op_61ff_23_nf;
+extern cpuop_func_ce op_61ff_23_ff;
+extern cpuop_func_ce op_6200_23_nf;
+extern cpuop_func_ce op_6200_23_ff;
+extern cpuop_func_ce op_6201_23_nf;
+extern cpuop_func_ce op_6201_23_ff;
+extern cpuop_func_ce op_62ff_23_nf;
+extern cpuop_func_ce op_62ff_23_ff;
+extern cpuop_func_ce op_6300_23_nf;
+extern cpuop_func_ce op_6300_23_ff;
+extern cpuop_func_ce op_6301_23_nf;
+extern cpuop_func_ce op_6301_23_ff;
+extern cpuop_func_ce op_63ff_23_nf;
+extern cpuop_func_ce op_63ff_23_ff;
+extern cpuop_func_ce op_6400_23_nf;
+extern cpuop_func_ce op_6400_23_ff;
+extern cpuop_func_ce op_6401_23_nf;
+extern cpuop_func_ce op_6401_23_ff;
+extern cpuop_func_ce op_64ff_23_nf;
+extern cpuop_func_ce op_64ff_23_ff;
+extern cpuop_func_ce op_6500_23_nf;
+extern cpuop_func_ce op_6500_23_ff;
+extern cpuop_func_ce op_6501_23_nf;
+extern cpuop_func_ce op_6501_23_ff;
+extern cpuop_func_ce op_65ff_23_nf;
+extern cpuop_func_ce op_65ff_23_ff;
+extern cpuop_func_ce op_6600_23_nf;
+extern cpuop_func_ce op_6600_23_ff;
+extern cpuop_func_ce op_6601_23_nf;
+extern cpuop_func_ce op_6601_23_ff;
+extern cpuop_func_ce op_66ff_23_nf;
+extern cpuop_func_ce op_66ff_23_ff;
+extern cpuop_func_ce op_6700_23_nf;
+extern cpuop_func_ce op_6700_23_ff;
+extern cpuop_func_ce op_6701_23_nf;
+extern cpuop_func_ce op_6701_23_ff;
+extern cpuop_func_ce op_67ff_23_nf;
+extern cpuop_func_ce op_67ff_23_ff;
+extern cpuop_func_ce op_6800_23_nf;
+extern cpuop_func_ce op_6800_23_ff;
+extern cpuop_func_ce op_6801_23_nf;
+extern cpuop_func_ce op_6801_23_ff;
+extern cpuop_func_ce op_68ff_23_nf;
+extern cpuop_func_ce op_68ff_23_ff;
+extern cpuop_func_ce op_6900_23_nf;
+extern cpuop_func_ce op_6900_23_ff;
+extern cpuop_func_ce op_6901_23_nf;
+extern cpuop_func_ce op_6901_23_ff;
+extern cpuop_func_ce op_69ff_23_nf;
+extern cpuop_func_ce op_69ff_23_ff;
+extern cpuop_func_ce op_6a00_23_nf;
+extern cpuop_func_ce op_6a00_23_ff;
+extern cpuop_func_ce op_6a01_23_nf;
+extern cpuop_func_ce op_6a01_23_ff;
+extern cpuop_func_ce op_6aff_23_nf;
+extern cpuop_func_ce op_6aff_23_ff;
+extern cpuop_func_ce op_6b00_23_nf;
+extern cpuop_func_ce op_6b00_23_ff;
+extern cpuop_func_ce op_6b01_23_nf;
+extern cpuop_func_ce op_6b01_23_ff;
+extern cpuop_func_ce op_6bff_23_nf;
+extern cpuop_func_ce op_6bff_23_ff;
+extern cpuop_func_ce op_6c00_23_nf;
+extern cpuop_func_ce op_6c00_23_ff;
+extern cpuop_func_ce op_6c01_23_nf;
+extern cpuop_func_ce op_6c01_23_ff;
+extern cpuop_func_ce op_6cff_23_nf;
+extern cpuop_func_ce op_6cff_23_ff;
+extern cpuop_func_ce op_6d00_23_nf;
+extern cpuop_func_ce op_6d00_23_ff;
+extern cpuop_func_ce op_6d01_23_nf;
+extern cpuop_func_ce op_6d01_23_ff;
+extern cpuop_func_ce op_6dff_23_nf;
+extern cpuop_func_ce op_6dff_23_ff;
+extern cpuop_func_ce op_6e00_23_nf;
+extern cpuop_func_ce op_6e00_23_ff;
+extern cpuop_func_ce op_6e01_23_nf;
+extern cpuop_func_ce op_6e01_23_ff;
+extern cpuop_func_ce op_6eff_23_nf;
+extern cpuop_func_ce op_6eff_23_ff;
+extern cpuop_func_ce op_6f00_23_nf;
+extern cpuop_func_ce op_6f00_23_ff;
+extern cpuop_func_ce op_6f01_23_nf;
+extern cpuop_func_ce op_6f01_23_ff;
+extern cpuop_func_ce op_6fff_23_nf;
+extern cpuop_func_ce op_6fff_23_ff;
+extern cpuop_func_ce op_7000_23_nf;
+extern cpuop_func_ce op_7000_23_ff;
+extern cpuop_func_ce op_8000_23_nf;
+extern cpuop_func_ce op_8000_23_ff;
+extern cpuop_func_ce op_8010_23_nf;
+extern cpuop_func_ce op_8010_23_ff;
+extern cpuop_func_ce op_8018_23_nf;
+extern cpuop_func_ce op_8018_23_ff;
+extern cpuop_func_ce op_8020_23_nf;
+extern cpuop_func_ce op_8020_23_ff;
+extern cpuop_func_ce op_8028_23_nf;
+extern cpuop_func_ce op_8028_23_ff;
+extern cpuop_func_ce op_8030_23_nf;
+extern cpuop_func_ce op_8030_23_ff;
+extern cpuop_func_ce op_8038_23_nf;
+extern cpuop_func_ce op_8038_23_ff;
+extern cpuop_func_ce op_8039_23_nf;
+extern cpuop_func_ce op_8039_23_ff;
+extern cpuop_func_ce op_803a_23_nf;
+extern cpuop_func_ce op_803a_23_ff;
+extern cpuop_func_ce op_803b_23_nf;
+extern cpuop_func_ce op_803b_23_ff;
+extern cpuop_func_ce op_803c_23_nf;
+extern cpuop_func_ce op_803c_23_ff;
+extern cpuop_func_ce op_8040_23_nf;
+extern cpuop_func_ce op_8040_23_ff;
+extern cpuop_func_ce op_8050_23_nf;
+extern cpuop_func_ce op_8050_23_ff;
+extern cpuop_func_ce op_8058_23_nf;
+extern cpuop_func_ce op_8058_23_ff;
+extern cpuop_func_ce op_8060_23_nf;
+extern cpuop_func_ce op_8060_23_ff;
+extern cpuop_func_ce op_8068_23_nf;
+extern cpuop_func_ce op_8068_23_ff;
+extern cpuop_func_ce op_8070_23_nf;
+extern cpuop_func_ce op_8070_23_ff;
+extern cpuop_func_ce op_8078_23_nf;
+extern cpuop_func_ce op_8078_23_ff;
+extern cpuop_func_ce op_8079_23_nf;
+extern cpuop_func_ce op_8079_23_ff;
+extern cpuop_func_ce op_807a_23_nf;
+extern cpuop_func_ce op_807a_23_ff;
+extern cpuop_func_ce op_807b_23_nf;
+extern cpuop_func_ce op_807b_23_ff;
+extern cpuop_func_ce op_807c_23_nf;
+extern cpuop_func_ce op_807c_23_ff;
+extern cpuop_func_ce op_8080_23_nf;
+extern cpuop_func_ce op_8080_23_ff;
+extern cpuop_func_ce op_8090_23_nf;
+extern cpuop_func_ce op_8090_23_ff;
+extern cpuop_func_ce op_8098_23_nf;
+extern cpuop_func_ce op_8098_23_ff;
+extern cpuop_func_ce op_80a0_23_nf;
+extern cpuop_func_ce op_80a0_23_ff;
+extern cpuop_func_ce op_80a8_23_nf;
+extern cpuop_func_ce op_80a8_23_ff;
+extern cpuop_func_ce op_80b0_23_nf;
+extern cpuop_func_ce op_80b0_23_ff;
+extern cpuop_func_ce op_80b8_23_nf;
+extern cpuop_func_ce op_80b8_23_ff;
+extern cpuop_func_ce op_80b9_23_nf;
+extern cpuop_func_ce op_80b9_23_ff;
+extern cpuop_func_ce op_80ba_23_nf;
+extern cpuop_func_ce op_80ba_23_ff;
+extern cpuop_func_ce op_80bb_23_nf;
+extern cpuop_func_ce op_80bb_23_ff;
+extern cpuop_func_ce op_80bc_23_nf;
+extern cpuop_func_ce op_80bc_23_ff;
+extern cpuop_func_ce op_80c0_23_nf;
+extern cpuop_func_ce op_80c0_23_ff;
+extern cpuop_func_ce op_80d0_23_nf;
+extern cpuop_func_ce op_80d0_23_ff;
+extern cpuop_func_ce op_80d8_23_nf;
+extern cpuop_func_ce op_80d8_23_ff;
+extern cpuop_func_ce op_80e0_23_nf;
+extern cpuop_func_ce op_80e0_23_ff;
+extern cpuop_func_ce op_80e8_23_nf;
+extern cpuop_func_ce op_80e8_23_ff;
+extern cpuop_func_ce op_80f0_23_nf;
+extern cpuop_func_ce op_80f0_23_ff;
+extern cpuop_func_ce op_80f8_23_nf;
+extern cpuop_func_ce op_80f8_23_ff;
+extern cpuop_func_ce op_80f9_23_nf;
+extern cpuop_func_ce op_80f9_23_ff;
+extern cpuop_func_ce op_80fa_23_nf;
+extern cpuop_func_ce op_80fa_23_ff;
+extern cpuop_func_ce op_80fb_23_nf;
+extern cpuop_func_ce op_80fb_23_ff;
+extern cpuop_func_ce op_80fc_23_nf;
+extern cpuop_func_ce op_80fc_23_ff;
+extern cpuop_func_ce op_8100_23_nf;
+extern cpuop_func_ce op_8100_23_ff;
+extern cpuop_func_ce op_8108_23_nf;
+extern cpuop_func_ce op_8108_23_ff;
+extern cpuop_func_ce op_8110_23_nf;
+extern cpuop_func_ce op_8110_23_ff;
+extern cpuop_func_ce op_8118_23_nf;
+extern cpuop_func_ce op_8118_23_ff;
+extern cpuop_func_ce op_8120_23_nf;
+extern cpuop_func_ce op_8120_23_ff;
+extern cpuop_func_ce op_8128_23_nf;
+extern cpuop_func_ce op_8128_23_ff;
+extern cpuop_func_ce op_8130_23_nf;
+extern cpuop_func_ce op_8130_23_ff;
+extern cpuop_func_ce op_8138_23_nf;
+extern cpuop_func_ce op_8138_23_ff;
+extern cpuop_func_ce op_8139_23_nf;
+extern cpuop_func_ce op_8139_23_ff;
+extern cpuop_func_ce op_8140_23_nf;
+extern cpuop_func_ce op_8140_23_ff;
+extern cpuop_func_ce op_8148_23_nf;
+extern cpuop_func_ce op_8148_23_ff;
+extern cpuop_func_ce op_8150_23_nf;
+extern cpuop_func_ce op_8150_23_ff;
+extern cpuop_func_ce op_8158_23_nf;
+extern cpuop_func_ce op_8158_23_ff;
+extern cpuop_func_ce op_8160_23_nf;
+extern cpuop_func_ce op_8160_23_ff;
+extern cpuop_func_ce op_8168_23_nf;
+extern cpuop_func_ce op_8168_23_ff;
+extern cpuop_func_ce op_8170_23_nf;
+extern cpuop_func_ce op_8170_23_ff;
+extern cpuop_func_ce op_8178_23_nf;
+extern cpuop_func_ce op_8178_23_ff;
+extern cpuop_func_ce op_8179_23_nf;
+extern cpuop_func_ce op_8179_23_ff;
+extern cpuop_func_ce op_8180_23_nf;
+extern cpuop_func_ce op_8180_23_ff;
+extern cpuop_func_ce op_8188_23_nf;
+extern cpuop_func_ce op_8188_23_ff;
+extern cpuop_func_ce op_8190_23_nf;
+extern cpuop_func_ce op_8190_23_ff;
+extern cpuop_func_ce op_8198_23_nf;
+extern cpuop_func_ce op_8198_23_ff;
+extern cpuop_func_ce op_81a0_23_nf;
+extern cpuop_func_ce op_81a0_23_ff;
+extern cpuop_func_ce op_81a8_23_nf;
+extern cpuop_func_ce op_81a8_23_ff;
+extern cpuop_func_ce op_81b0_23_nf;
+extern cpuop_func_ce op_81b0_23_ff;
+extern cpuop_func_ce op_81b8_23_nf;
+extern cpuop_func_ce op_81b8_23_ff;
+extern cpuop_func_ce op_81b9_23_nf;
+extern cpuop_func_ce op_81b9_23_ff;
+extern cpuop_func_ce op_81c0_23_nf;
+extern cpuop_func_ce op_81c0_23_ff;
+extern cpuop_func_ce op_81d0_23_nf;
+extern cpuop_func_ce op_81d0_23_ff;
+extern cpuop_func_ce op_81d8_23_nf;
+extern cpuop_func_ce op_81d8_23_ff;
+extern cpuop_func_ce op_81e0_23_nf;
+extern cpuop_func_ce op_81e0_23_ff;
+extern cpuop_func_ce op_81e8_23_nf;
+extern cpuop_func_ce op_81e8_23_ff;
+extern cpuop_func_ce op_81f0_23_nf;
+extern cpuop_func_ce op_81f0_23_ff;
+extern cpuop_func_ce op_81f8_23_nf;
+extern cpuop_func_ce op_81f8_23_ff;
+extern cpuop_func_ce op_81f9_23_nf;
+extern cpuop_func_ce op_81f9_23_ff;
+extern cpuop_func_ce op_81fa_23_nf;
+extern cpuop_func_ce op_81fa_23_ff;
+extern cpuop_func_ce op_81fb_23_nf;
+extern cpuop_func_ce op_81fb_23_ff;
+extern cpuop_func_ce op_81fc_23_nf;
+extern cpuop_func_ce op_81fc_23_ff;
+extern cpuop_func_ce op_9000_23_nf;
+extern cpuop_func_ce op_9000_23_ff;
+extern cpuop_func_ce op_9010_23_nf;
+extern cpuop_func_ce op_9010_23_ff;
+extern cpuop_func_ce op_9018_23_nf;
+extern cpuop_func_ce op_9018_23_ff;
+extern cpuop_func_ce op_9020_23_nf;
+extern cpuop_func_ce op_9020_23_ff;
+extern cpuop_func_ce op_9028_23_nf;
+extern cpuop_func_ce op_9028_23_ff;
+extern cpuop_func_ce op_9030_23_nf;
+extern cpuop_func_ce op_9030_23_ff;
+extern cpuop_func_ce op_9038_23_nf;
+extern cpuop_func_ce op_9038_23_ff;
+extern cpuop_func_ce op_9039_23_nf;
+extern cpuop_func_ce op_9039_23_ff;
+extern cpuop_func_ce op_903a_23_nf;
+extern cpuop_func_ce op_903a_23_ff;
+extern cpuop_func_ce op_903b_23_nf;
+extern cpuop_func_ce op_903b_23_ff;
+extern cpuop_func_ce op_903c_23_nf;
+extern cpuop_func_ce op_903c_23_ff;
+extern cpuop_func_ce op_9040_23_nf;
+extern cpuop_func_ce op_9040_23_ff;
+extern cpuop_func_ce op_9048_23_nf;
+extern cpuop_func_ce op_9048_23_ff;
+extern cpuop_func_ce op_9050_23_nf;
+extern cpuop_func_ce op_9050_23_ff;
+extern cpuop_func_ce op_9058_23_nf;
+extern cpuop_func_ce op_9058_23_ff;
+extern cpuop_func_ce op_9060_23_nf;
+extern cpuop_func_ce op_9060_23_ff;
+extern cpuop_func_ce op_9068_23_nf;
+extern cpuop_func_ce op_9068_23_ff;
+extern cpuop_func_ce op_9070_23_nf;
+extern cpuop_func_ce op_9070_23_ff;
+extern cpuop_func_ce op_9078_23_nf;
+extern cpuop_func_ce op_9078_23_ff;
+extern cpuop_func_ce op_9079_23_nf;
+extern cpuop_func_ce op_9079_23_ff;
+extern cpuop_func_ce op_907a_23_nf;
+extern cpuop_func_ce op_907a_23_ff;
+extern cpuop_func_ce op_907b_23_nf;
+extern cpuop_func_ce op_907b_23_ff;
+extern cpuop_func_ce op_907c_23_nf;
+extern cpuop_func_ce op_907c_23_ff;
+extern cpuop_func_ce op_9080_23_nf;
+extern cpuop_func_ce op_9080_23_ff;
+extern cpuop_func_ce op_9088_23_nf;
+extern cpuop_func_ce op_9088_23_ff;
+extern cpuop_func_ce op_9090_23_nf;
+extern cpuop_func_ce op_9090_23_ff;
+extern cpuop_func_ce op_9098_23_nf;
+extern cpuop_func_ce op_9098_23_ff;
+extern cpuop_func_ce op_90a0_23_nf;
+extern cpuop_func_ce op_90a0_23_ff;
+extern cpuop_func_ce op_90a8_23_nf;
+extern cpuop_func_ce op_90a8_23_ff;
+extern cpuop_func_ce op_90b0_23_nf;
+extern cpuop_func_ce op_90b0_23_ff;
+extern cpuop_func_ce op_90b8_23_nf;
+extern cpuop_func_ce op_90b8_23_ff;
+extern cpuop_func_ce op_90b9_23_nf;
+extern cpuop_func_ce op_90b9_23_ff;
+extern cpuop_func_ce op_90ba_23_nf;
+extern cpuop_func_ce op_90ba_23_ff;
+extern cpuop_func_ce op_90bb_23_nf;
+extern cpuop_func_ce op_90bb_23_ff;
+extern cpuop_func_ce op_90bc_23_nf;
+extern cpuop_func_ce op_90bc_23_ff;
+extern cpuop_func_ce op_90c0_23_nf;
+extern cpuop_func_ce op_90c0_23_ff;
+extern cpuop_func_ce op_90c8_23_nf;
+extern cpuop_func_ce op_90c8_23_ff;
+extern cpuop_func_ce op_90d0_23_nf;
+extern cpuop_func_ce op_90d0_23_ff;
+extern cpuop_func_ce op_90d8_23_nf;
+extern cpuop_func_ce op_90d8_23_ff;
+extern cpuop_func_ce op_90e0_23_nf;
+extern cpuop_func_ce op_90e0_23_ff;
+extern cpuop_func_ce op_90e8_23_nf;
+extern cpuop_func_ce op_90e8_23_ff;
+extern cpuop_func_ce op_90f0_23_nf;
+extern cpuop_func_ce op_90f0_23_ff;
+extern cpuop_func_ce op_90f8_23_nf;
+extern cpuop_func_ce op_90f8_23_ff;
+extern cpuop_func_ce op_90f9_23_nf;
+extern cpuop_func_ce op_90f9_23_ff;
+extern cpuop_func_ce op_90fa_23_nf;
+extern cpuop_func_ce op_90fa_23_ff;
+extern cpuop_func_ce op_90fb_23_nf;
+extern cpuop_func_ce op_90fb_23_ff;
+extern cpuop_func_ce op_90fc_23_nf;
+extern cpuop_func_ce op_90fc_23_ff;
+extern cpuop_func_ce op_9100_23_nf;
+extern cpuop_func_ce op_9100_23_ff;
+extern cpuop_func_ce op_9108_23_nf;
+extern cpuop_func_ce op_9108_23_ff;
+extern cpuop_func_ce op_9110_23_nf;
+extern cpuop_func_ce op_9110_23_ff;
+extern cpuop_func_ce op_9118_23_nf;
+extern cpuop_func_ce op_9118_23_ff;
+extern cpuop_func_ce op_9120_23_nf;
+extern cpuop_func_ce op_9120_23_ff;
+extern cpuop_func_ce op_9128_23_nf;
+extern cpuop_func_ce op_9128_23_ff;
+extern cpuop_func_ce op_9130_23_nf;
+extern cpuop_func_ce op_9130_23_ff;
+extern cpuop_func_ce op_9138_23_nf;
+extern cpuop_func_ce op_9138_23_ff;
+extern cpuop_func_ce op_9139_23_nf;
+extern cpuop_func_ce op_9139_23_ff;
+extern cpuop_func_ce op_9140_23_nf;
+extern cpuop_func_ce op_9140_23_ff;
+extern cpuop_func_ce op_9148_23_nf;
+extern cpuop_func_ce op_9148_23_ff;
+extern cpuop_func_ce op_9150_23_nf;
+extern cpuop_func_ce op_9150_23_ff;
+extern cpuop_func_ce op_9158_23_nf;
+extern cpuop_func_ce op_9158_23_ff;
+extern cpuop_func_ce op_9160_23_nf;
+extern cpuop_func_ce op_9160_23_ff;
+extern cpuop_func_ce op_9168_23_nf;
+extern cpuop_func_ce op_9168_23_ff;
+extern cpuop_func_ce op_9170_23_nf;
+extern cpuop_func_ce op_9170_23_ff;
+extern cpuop_func_ce op_9178_23_nf;
+extern cpuop_func_ce op_9178_23_ff;
+extern cpuop_func_ce op_9179_23_nf;
+extern cpuop_func_ce op_9179_23_ff;
+extern cpuop_func_ce op_9180_23_nf;
+extern cpuop_func_ce op_9180_23_ff;
+extern cpuop_func_ce op_9188_23_nf;
+extern cpuop_func_ce op_9188_23_ff;
+extern cpuop_func_ce op_9190_23_nf;
+extern cpuop_func_ce op_9190_23_ff;
+extern cpuop_func_ce op_9198_23_nf;
+extern cpuop_func_ce op_9198_23_ff;
+extern cpuop_func_ce op_91a0_23_nf;
+extern cpuop_func_ce op_91a0_23_ff;
+extern cpuop_func_ce op_91a8_23_nf;
+extern cpuop_func_ce op_91a8_23_ff;
+extern cpuop_func_ce op_91b0_23_nf;
+extern cpuop_func_ce op_91b0_23_ff;
+extern cpuop_func_ce op_91b8_23_nf;
+extern cpuop_func_ce op_91b8_23_ff;
+extern cpuop_func_ce op_91b9_23_nf;
+extern cpuop_func_ce op_91b9_23_ff;
+extern cpuop_func_ce op_91c0_23_nf;
+extern cpuop_func_ce op_91c0_23_ff;
+extern cpuop_func_ce op_91c8_23_nf;
+extern cpuop_func_ce op_91c8_23_ff;
+extern cpuop_func_ce op_91d0_23_nf;
+extern cpuop_func_ce op_91d0_23_ff;
+extern cpuop_func_ce op_91d8_23_nf;
+extern cpuop_func_ce op_91d8_23_ff;
+extern cpuop_func_ce op_91e0_23_nf;
+extern cpuop_func_ce op_91e0_23_ff;
+extern cpuop_func_ce op_91e8_23_nf;
+extern cpuop_func_ce op_91e8_23_ff;
+extern cpuop_func_ce op_91f0_23_nf;
+extern cpuop_func_ce op_91f0_23_ff;
+extern cpuop_func_ce op_91f8_23_nf;
+extern cpuop_func_ce op_91f8_23_ff;
+extern cpuop_func_ce op_91f9_23_nf;
+extern cpuop_func_ce op_91f9_23_ff;
+extern cpuop_func_ce op_91fa_23_nf;
+extern cpuop_func_ce op_91fa_23_ff;
+extern cpuop_func_ce op_91fb_23_nf;
+extern cpuop_func_ce op_91fb_23_ff;
+extern cpuop_func_ce op_91fc_23_nf;
+extern cpuop_func_ce op_91fc_23_ff;
+extern cpuop_func_ce op_b000_23_nf;
+extern cpuop_func_ce op_b000_23_ff;
+extern cpuop_func_ce op_b010_23_nf;
+extern cpuop_func_ce op_b010_23_ff;
+extern cpuop_func_ce op_b018_23_nf;
+extern cpuop_func_ce op_b018_23_ff;
+extern cpuop_func_ce op_b020_23_nf;
+extern cpuop_func_ce op_b020_23_ff;
+extern cpuop_func_ce op_b028_23_nf;
+extern cpuop_func_ce op_b028_23_ff;
+extern cpuop_func_ce op_b030_23_nf;
+extern cpuop_func_ce op_b030_23_ff;
+extern cpuop_func_ce op_b038_23_nf;
+extern cpuop_func_ce op_b038_23_ff;
+extern cpuop_func_ce op_b039_23_nf;
+extern cpuop_func_ce op_b039_23_ff;
+extern cpuop_func_ce op_b03a_23_nf;
+extern cpuop_func_ce op_b03a_23_ff;
+extern cpuop_func_ce op_b03b_23_nf;
+extern cpuop_func_ce op_b03b_23_ff;
+extern cpuop_func_ce op_b03c_23_nf;
+extern cpuop_func_ce op_b03c_23_ff;
+extern cpuop_func_ce op_b040_23_nf;
+extern cpuop_func_ce op_b040_23_ff;
+extern cpuop_func_ce op_b048_23_nf;
+extern cpuop_func_ce op_b048_23_ff;
+extern cpuop_func_ce op_b050_23_nf;
+extern cpuop_func_ce op_b050_23_ff;
+extern cpuop_func_ce op_b058_23_nf;
+extern cpuop_func_ce op_b058_23_ff;
+extern cpuop_func_ce op_b060_23_nf;
+extern cpuop_func_ce op_b060_23_ff;
+extern cpuop_func_ce op_b068_23_nf;
+extern cpuop_func_ce op_b068_23_ff;
+extern cpuop_func_ce op_b070_23_nf;
+extern cpuop_func_ce op_b070_23_ff;
+extern cpuop_func_ce op_b078_23_nf;
+extern cpuop_func_ce op_b078_23_ff;
+extern cpuop_func_ce op_b079_23_nf;
+extern cpuop_func_ce op_b079_23_ff;
+extern cpuop_func_ce op_b07a_23_nf;
+extern cpuop_func_ce op_b07a_23_ff;
+extern cpuop_func_ce op_b07b_23_nf;
+extern cpuop_func_ce op_b07b_23_ff;
+extern cpuop_func_ce op_b07c_23_nf;
+extern cpuop_func_ce op_b07c_23_ff;
+extern cpuop_func_ce op_b080_23_nf;
+extern cpuop_func_ce op_b080_23_ff;
+extern cpuop_func_ce op_b088_23_nf;
+extern cpuop_func_ce op_b088_23_ff;
+extern cpuop_func_ce op_b090_23_nf;
+extern cpuop_func_ce op_b090_23_ff;
+extern cpuop_func_ce op_b098_23_nf;
+extern cpuop_func_ce op_b098_23_ff;
+extern cpuop_func_ce op_b0a0_23_nf;
+extern cpuop_func_ce op_b0a0_23_ff;
+extern cpuop_func_ce op_b0a8_23_nf;
+extern cpuop_func_ce op_b0a8_23_ff;
+extern cpuop_func_ce op_b0b0_23_nf;
+extern cpuop_func_ce op_b0b0_23_ff;
+extern cpuop_func_ce op_b0b8_23_nf;
+extern cpuop_func_ce op_b0b8_23_ff;
+extern cpuop_func_ce op_b0b9_23_nf;
+extern cpuop_func_ce op_b0b9_23_ff;
+extern cpuop_func_ce op_b0ba_23_nf;
+extern cpuop_func_ce op_b0ba_23_ff;
+extern cpuop_func_ce op_b0bb_23_nf;
+extern cpuop_func_ce op_b0bb_23_ff;
+extern cpuop_func_ce op_b0bc_23_nf;
+extern cpuop_func_ce op_b0bc_23_ff;
+extern cpuop_func_ce op_b0c0_23_nf;
+extern cpuop_func_ce op_b0c0_23_ff;
+extern cpuop_func_ce op_b0c8_23_nf;
+extern cpuop_func_ce op_b0c8_23_ff;
+extern cpuop_func_ce op_b0d0_23_nf;
+extern cpuop_func_ce op_b0d0_23_ff;
+extern cpuop_func_ce op_b0d8_23_nf;
+extern cpuop_func_ce op_b0d8_23_ff;
+extern cpuop_func_ce op_b0e0_23_nf;
+extern cpuop_func_ce op_b0e0_23_ff;
+extern cpuop_func_ce op_b0e8_23_nf;
+extern cpuop_func_ce op_b0e8_23_ff;
+extern cpuop_func_ce op_b0f0_23_nf;
+extern cpuop_func_ce op_b0f0_23_ff;
+extern cpuop_func_ce op_b0f8_23_nf;
+extern cpuop_func_ce op_b0f8_23_ff;
+extern cpuop_func_ce op_b0f9_23_nf;
+extern cpuop_func_ce op_b0f9_23_ff;
+extern cpuop_func_ce op_b0fa_23_nf;
+extern cpuop_func_ce op_b0fa_23_ff;
+extern cpuop_func_ce op_b0fb_23_nf;
+extern cpuop_func_ce op_b0fb_23_ff;
+extern cpuop_func_ce op_b0fc_23_nf;
+extern cpuop_func_ce op_b0fc_23_ff;
+extern cpuop_func_ce op_b100_23_nf;
+extern cpuop_func_ce op_b100_23_ff;
+extern cpuop_func_ce op_b108_23_nf;
+extern cpuop_func_ce op_b108_23_ff;
+extern cpuop_func_ce op_b110_23_nf;
+extern cpuop_func_ce op_b110_23_ff;
+extern cpuop_func_ce op_b118_23_nf;
+extern cpuop_func_ce op_b118_23_ff;
+extern cpuop_func_ce op_b120_23_nf;
+extern cpuop_func_ce op_b120_23_ff;
+extern cpuop_func_ce op_b128_23_nf;
+extern cpuop_func_ce op_b128_23_ff;
+extern cpuop_func_ce op_b130_23_nf;
+extern cpuop_func_ce op_b130_23_ff;
+extern cpuop_func_ce op_b138_23_nf;
+extern cpuop_func_ce op_b138_23_ff;
+extern cpuop_func_ce op_b139_23_nf;
+extern cpuop_func_ce op_b139_23_ff;
+extern cpuop_func_ce op_b140_23_nf;
+extern cpuop_func_ce op_b140_23_ff;
+extern cpuop_func_ce op_b148_23_nf;
+extern cpuop_func_ce op_b148_23_ff;
+extern cpuop_func_ce op_b150_23_nf;
+extern cpuop_func_ce op_b150_23_ff;
+extern cpuop_func_ce op_b158_23_nf;
+extern cpuop_func_ce op_b158_23_ff;
+extern cpuop_func_ce op_b160_23_nf;
+extern cpuop_func_ce op_b160_23_ff;
+extern cpuop_func_ce op_b168_23_nf;
+extern cpuop_func_ce op_b168_23_ff;
+extern cpuop_func_ce op_b170_23_nf;
+extern cpuop_func_ce op_b170_23_ff;
+extern cpuop_func_ce op_b178_23_nf;
+extern cpuop_func_ce op_b178_23_ff;
+extern cpuop_func_ce op_b179_23_nf;
+extern cpuop_func_ce op_b179_23_ff;
+extern cpuop_func_ce op_b180_23_nf;
+extern cpuop_func_ce op_b180_23_ff;
+extern cpuop_func_ce op_b188_23_nf;
+extern cpuop_func_ce op_b188_23_ff;
+extern cpuop_func_ce op_b190_23_nf;
+extern cpuop_func_ce op_b190_23_ff;
+extern cpuop_func_ce op_b198_23_nf;
+extern cpuop_func_ce op_b198_23_ff;
+extern cpuop_func_ce op_b1a0_23_nf;
+extern cpuop_func_ce op_b1a0_23_ff;
+extern cpuop_func_ce op_b1a8_23_nf;
+extern cpuop_func_ce op_b1a8_23_ff;
+extern cpuop_func_ce op_b1b0_23_nf;
+extern cpuop_func_ce op_b1b0_23_ff;
+extern cpuop_func_ce op_b1b8_23_nf;
+extern cpuop_func_ce op_b1b8_23_ff;
+extern cpuop_func_ce op_b1b9_23_nf;
+extern cpuop_func_ce op_b1b9_23_ff;
+extern cpuop_func_ce op_b1c0_23_nf;
+extern cpuop_func_ce op_b1c0_23_ff;
+extern cpuop_func_ce op_b1c8_23_nf;
+extern cpuop_func_ce op_b1c8_23_ff;
+extern cpuop_func_ce op_b1d0_23_nf;
+extern cpuop_func_ce op_b1d0_23_ff;
+extern cpuop_func_ce op_b1d8_23_nf;
+extern cpuop_func_ce op_b1d8_23_ff;
+extern cpuop_func_ce op_b1e0_23_nf;
+extern cpuop_func_ce op_b1e0_23_ff;
+extern cpuop_func_ce op_b1e8_23_nf;
+extern cpuop_func_ce op_b1e8_23_ff;
+extern cpuop_func_ce op_b1f0_23_nf;
+extern cpuop_func_ce op_b1f0_23_ff;
+extern cpuop_func_ce op_b1f8_23_nf;
+extern cpuop_func_ce op_b1f8_23_ff;
+extern cpuop_func_ce op_b1f9_23_nf;
+extern cpuop_func_ce op_b1f9_23_ff;
+extern cpuop_func_ce op_b1fa_23_nf;
+extern cpuop_func_ce op_b1fa_23_ff;
+extern cpuop_func_ce op_b1fb_23_nf;
+extern cpuop_func_ce op_b1fb_23_ff;
+extern cpuop_func_ce op_b1fc_23_nf;
+extern cpuop_func_ce op_b1fc_23_ff;
+extern cpuop_func_ce op_c000_23_nf;
+extern cpuop_func_ce op_c000_23_ff;
+extern cpuop_func_ce op_c010_23_nf;
+extern cpuop_func_ce op_c010_23_ff;
+extern cpuop_func_ce op_c018_23_nf;
+extern cpuop_func_ce op_c018_23_ff;
+extern cpuop_func_ce op_c020_23_nf;
+extern cpuop_func_ce op_c020_23_ff;
+extern cpuop_func_ce op_c028_23_nf;
+extern cpuop_func_ce op_c028_23_ff;
+extern cpuop_func_ce op_c030_23_nf;
+extern cpuop_func_ce op_c030_23_ff;
+extern cpuop_func_ce op_c038_23_nf;
+extern cpuop_func_ce op_c038_23_ff;
+extern cpuop_func_ce op_c039_23_nf;
+extern cpuop_func_ce op_c039_23_ff;
+extern cpuop_func_ce op_c03a_23_nf;
+extern cpuop_func_ce op_c03a_23_ff;
+extern cpuop_func_ce op_c03b_23_nf;
+extern cpuop_func_ce op_c03b_23_ff;
+extern cpuop_func_ce op_c03c_23_nf;
+extern cpuop_func_ce op_c03c_23_ff;
+extern cpuop_func_ce op_c040_23_nf;
+extern cpuop_func_ce op_c040_23_ff;
+extern cpuop_func_ce op_c050_23_nf;
+extern cpuop_func_ce op_c050_23_ff;
+extern cpuop_func_ce op_c058_23_nf;
+extern cpuop_func_ce op_c058_23_ff;
+extern cpuop_func_ce op_c060_23_nf;
+extern cpuop_func_ce op_c060_23_ff;
+extern cpuop_func_ce op_c068_23_nf;
+extern cpuop_func_ce op_c068_23_ff;
+extern cpuop_func_ce op_c070_23_nf;
+extern cpuop_func_ce op_c070_23_ff;
+extern cpuop_func_ce op_c078_23_nf;
+extern cpuop_func_ce op_c078_23_ff;
+extern cpuop_func_ce op_c079_23_nf;
+extern cpuop_func_ce op_c079_23_ff;
+extern cpuop_func_ce op_c07a_23_nf;
+extern cpuop_func_ce op_c07a_23_ff;
+extern cpuop_func_ce op_c07b_23_nf;
+extern cpuop_func_ce op_c07b_23_ff;
+extern cpuop_func_ce op_c07c_23_nf;
+extern cpuop_func_ce op_c07c_23_ff;
+extern cpuop_func_ce op_c080_23_nf;
+extern cpuop_func_ce op_c080_23_ff;
+extern cpuop_func_ce op_c090_23_nf;
+extern cpuop_func_ce op_c090_23_ff;
+extern cpuop_func_ce op_c098_23_nf;
+extern cpuop_func_ce op_c098_23_ff;
+extern cpuop_func_ce op_c0a0_23_nf;
+extern cpuop_func_ce op_c0a0_23_ff;
+extern cpuop_func_ce op_c0a8_23_nf;
+extern cpuop_func_ce op_c0a8_23_ff;
+extern cpuop_func_ce op_c0b0_23_nf;
+extern cpuop_func_ce op_c0b0_23_ff;
+extern cpuop_func_ce op_c0b8_23_nf;
+extern cpuop_func_ce op_c0b8_23_ff;
+extern cpuop_func_ce op_c0b9_23_nf;
+extern cpuop_func_ce op_c0b9_23_ff;
+extern cpuop_func_ce op_c0ba_23_nf;
+extern cpuop_func_ce op_c0ba_23_ff;
+extern cpuop_func_ce op_c0bb_23_nf;
+extern cpuop_func_ce op_c0bb_23_ff;
+extern cpuop_func_ce op_c0bc_23_nf;
+extern cpuop_func_ce op_c0bc_23_ff;
+extern cpuop_func_ce op_c0c0_23_nf;
+extern cpuop_func_ce op_c0c0_23_ff;
+extern cpuop_func_ce op_c0d0_23_nf;
+extern cpuop_func_ce op_c0d0_23_ff;
+extern cpuop_func_ce op_c0d8_23_nf;
+extern cpuop_func_ce op_c0d8_23_ff;
+extern cpuop_func_ce op_c0e0_23_nf;
+extern cpuop_func_ce op_c0e0_23_ff;
+extern cpuop_func_ce op_c0e8_23_nf;
+extern cpuop_func_ce op_c0e8_23_ff;
+extern cpuop_func_ce op_c0f0_23_nf;
+extern cpuop_func_ce op_c0f0_23_ff;
+extern cpuop_func_ce op_c0f8_23_nf;
+extern cpuop_func_ce op_c0f8_23_ff;
+extern cpuop_func_ce op_c0f9_23_nf;
+extern cpuop_func_ce op_c0f9_23_ff;
+extern cpuop_func_ce op_c0fa_23_nf;
+extern cpuop_func_ce op_c0fa_23_ff;
+extern cpuop_func_ce op_c0fb_23_nf;
+extern cpuop_func_ce op_c0fb_23_ff;
+extern cpuop_func_ce op_c0fc_23_nf;
+extern cpuop_func_ce op_c0fc_23_ff;
+extern cpuop_func_ce op_c100_23_nf;
+extern cpuop_func_ce op_c100_23_ff;
+extern cpuop_func_ce op_c108_23_nf;
+extern cpuop_func_ce op_c108_23_ff;
+extern cpuop_func_ce op_c110_23_nf;
+extern cpuop_func_ce op_c110_23_ff;
+extern cpuop_func_ce op_c118_23_nf;
+extern cpuop_func_ce op_c118_23_ff;
+extern cpuop_func_ce op_c120_23_nf;
+extern cpuop_func_ce op_c120_23_ff;
+extern cpuop_func_ce op_c128_23_nf;
+extern cpuop_func_ce op_c128_23_ff;
+extern cpuop_func_ce op_c130_23_nf;
+extern cpuop_func_ce op_c130_23_ff;
+extern cpuop_func_ce op_c138_23_nf;
+extern cpuop_func_ce op_c138_23_ff;
+extern cpuop_func_ce op_c139_23_nf;
+extern cpuop_func_ce op_c139_23_ff;
+extern cpuop_func_ce op_c140_23_nf;
+extern cpuop_func_ce op_c140_23_ff;
+extern cpuop_func_ce op_c148_23_nf;
+extern cpuop_func_ce op_c148_23_ff;
+extern cpuop_func_ce op_c150_23_nf;
+extern cpuop_func_ce op_c150_23_ff;
+extern cpuop_func_ce op_c158_23_nf;
+extern cpuop_func_ce op_c158_23_ff;
+extern cpuop_func_ce op_c160_23_nf;
+extern cpuop_func_ce op_c160_23_ff;
+extern cpuop_func_ce op_c168_23_nf;
+extern cpuop_func_ce op_c168_23_ff;
+extern cpuop_func_ce op_c170_23_nf;
+extern cpuop_func_ce op_c170_23_ff;
+extern cpuop_func_ce op_c178_23_nf;
+extern cpuop_func_ce op_c178_23_ff;
+extern cpuop_func_ce op_c179_23_nf;
+extern cpuop_func_ce op_c179_23_ff;
+extern cpuop_func_ce op_c188_23_nf;
+extern cpuop_func_ce op_c188_23_ff;
+extern cpuop_func_ce op_c190_23_nf;
+extern cpuop_func_ce op_c190_23_ff;
+extern cpuop_func_ce op_c198_23_nf;
+extern cpuop_func_ce op_c198_23_ff;
+extern cpuop_func_ce op_c1a0_23_nf;
+extern cpuop_func_ce op_c1a0_23_ff;
+extern cpuop_func_ce op_c1a8_23_nf;
+extern cpuop_func_ce op_c1a8_23_ff;
+extern cpuop_func_ce op_c1b0_23_nf;
+extern cpuop_func_ce op_c1b0_23_ff;
+extern cpuop_func_ce op_c1b8_23_nf;
+extern cpuop_func_ce op_c1b8_23_ff;
+extern cpuop_func_ce op_c1b9_23_nf;
+extern cpuop_func_ce op_c1b9_23_ff;
+extern cpuop_func_ce op_c1c0_23_nf;
+extern cpuop_func_ce op_c1c0_23_ff;
+extern cpuop_func_ce op_c1d0_23_nf;
+extern cpuop_func_ce op_c1d0_23_ff;
+extern cpuop_func_ce op_c1d8_23_nf;
+extern cpuop_func_ce op_c1d8_23_ff;
+extern cpuop_func_ce op_c1e0_23_nf;
+extern cpuop_func_ce op_c1e0_23_ff;
+extern cpuop_func_ce op_c1e8_23_nf;
+extern cpuop_func_ce op_c1e8_23_ff;
+extern cpuop_func_ce op_c1f0_23_nf;
+extern cpuop_func_ce op_c1f0_23_ff;
+extern cpuop_func_ce op_c1f8_23_nf;
+extern cpuop_func_ce op_c1f8_23_ff;
+extern cpuop_func_ce op_c1f9_23_nf;
+extern cpuop_func_ce op_c1f9_23_ff;
+extern cpuop_func_ce op_c1fa_23_nf;
+extern cpuop_func_ce op_c1fa_23_ff;
+extern cpuop_func_ce op_c1fb_23_nf;
+extern cpuop_func_ce op_c1fb_23_ff;
+extern cpuop_func_ce op_c1fc_23_nf;
+extern cpuop_func_ce op_c1fc_23_ff;
+extern cpuop_func_ce op_d000_23_nf;
+extern cpuop_func_ce op_d000_23_ff;
+extern cpuop_func_ce op_d010_23_nf;
+extern cpuop_func_ce op_d010_23_ff;
+extern cpuop_func_ce op_d018_23_nf;
+extern cpuop_func_ce op_d018_23_ff;
+extern cpuop_func_ce op_d020_23_nf;
+extern cpuop_func_ce op_d020_23_ff;
+extern cpuop_func_ce op_d028_23_nf;
+extern cpuop_func_ce op_d028_23_ff;
+extern cpuop_func_ce op_d030_23_nf;
+extern cpuop_func_ce op_d030_23_ff;
+extern cpuop_func_ce op_d038_23_nf;
+extern cpuop_func_ce op_d038_23_ff;
+extern cpuop_func_ce op_d039_23_nf;
+extern cpuop_func_ce op_d039_23_ff;
+extern cpuop_func_ce op_d03a_23_nf;
+extern cpuop_func_ce op_d03a_23_ff;
+extern cpuop_func_ce op_d03b_23_nf;
+extern cpuop_func_ce op_d03b_23_ff;
+extern cpuop_func_ce op_d03c_23_nf;
+extern cpuop_func_ce op_d03c_23_ff;
+extern cpuop_func_ce op_d040_23_nf;
+extern cpuop_func_ce op_d040_23_ff;
+extern cpuop_func_ce op_d048_23_nf;
+extern cpuop_func_ce op_d048_23_ff;
+extern cpuop_func_ce op_d050_23_nf;
+extern cpuop_func_ce op_d050_23_ff;
+extern cpuop_func_ce op_d058_23_nf;
+extern cpuop_func_ce op_d058_23_ff;
+extern cpuop_func_ce op_d060_23_nf;
+extern cpuop_func_ce op_d060_23_ff;
+extern cpuop_func_ce op_d068_23_nf;
+extern cpuop_func_ce op_d068_23_ff;
+extern cpuop_func_ce op_d070_23_nf;
+extern cpuop_func_ce op_d070_23_ff;
+extern cpuop_func_ce op_d078_23_nf;
+extern cpuop_func_ce op_d078_23_ff;
+extern cpuop_func_ce op_d079_23_nf;
+extern cpuop_func_ce op_d079_23_ff;
+extern cpuop_func_ce op_d07a_23_nf;
+extern cpuop_func_ce op_d07a_23_ff;
+extern cpuop_func_ce op_d07b_23_nf;
+extern cpuop_func_ce op_d07b_23_ff;
+extern cpuop_func_ce op_d07c_23_nf;
+extern cpuop_func_ce op_d07c_23_ff;
+extern cpuop_func_ce op_d080_23_nf;
+extern cpuop_func_ce op_d080_23_ff;
+extern cpuop_func_ce op_d088_23_nf;
+extern cpuop_func_ce op_d088_23_ff;
+extern cpuop_func_ce op_d090_23_nf;
+extern cpuop_func_ce op_d090_23_ff;
+extern cpuop_func_ce op_d098_23_nf;
+extern cpuop_func_ce op_d098_23_ff;
+extern cpuop_func_ce op_d0a0_23_nf;
+extern cpuop_func_ce op_d0a0_23_ff;
+extern cpuop_func_ce op_d0a8_23_nf;
+extern cpuop_func_ce op_d0a8_23_ff;
+extern cpuop_func_ce op_d0b0_23_nf;
+extern cpuop_func_ce op_d0b0_23_ff;
+extern cpuop_func_ce op_d0b8_23_nf;
+extern cpuop_func_ce op_d0b8_23_ff;
+extern cpuop_func_ce op_d0b9_23_nf;
+extern cpuop_func_ce op_d0b9_23_ff;
+extern cpuop_func_ce op_d0ba_23_nf;
+extern cpuop_func_ce op_d0ba_23_ff;
+extern cpuop_func_ce op_d0bb_23_nf;
+extern cpuop_func_ce op_d0bb_23_ff;
+extern cpuop_func_ce op_d0bc_23_nf;
+extern cpuop_func_ce op_d0bc_23_ff;
+extern cpuop_func_ce op_d0c0_23_nf;
+extern cpuop_func_ce op_d0c0_23_ff;
+extern cpuop_func_ce op_d0c8_23_nf;
+extern cpuop_func_ce op_d0c8_23_ff;
+extern cpuop_func_ce op_d0d0_23_nf;
+extern cpuop_func_ce op_d0d0_23_ff;
+extern cpuop_func_ce op_d0d8_23_nf;
+extern cpuop_func_ce op_d0d8_23_ff;
+extern cpuop_func_ce op_d0e0_23_nf;
+extern cpuop_func_ce op_d0e0_23_ff;
+extern cpuop_func_ce op_d0e8_23_nf;
+extern cpuop_func_ce op_d0e8_23_ff;
+extern cpuop_func_ce op_d0f0_23_nf;
+extern cpuop_func_ce op_d0f0_23_ff;
+extern cpuop_func_ce op_d0f8_23_nf;
+extern cpuop_func_ce op_d0f8_23_ff;
+extern cpuop_func_ce op_d0f9_23_nf;
+extern cpuop_func_ce op_d0f9_23_ff;
+extern cpuop_func_ce op_d0fa_23_nf;
+extern cpuop_func_ce op_d0fa_23_ff;
+extern cpuop_func_ce op_d0fb_23_nf;
+extern cpuop_func_ce op_d0fb_23_ff;
+extern cpuop_func_ce op_d0fc_23_nf;
+extern cpuop_func_ce op_d0fc_23_ff;
+extern cpuop_func_ce op_d100_23_nf;
+extern cpuop_func_ce op_d100_23_ff;
+extern cpuop_func_ce op_d108_23_nf;
+extern cpuop_func_ce op_d108_23_ff;
+extern cpuop_func_ce op_d110_23_nf;
+extern cpuop_func_ce op_d110_23_ff;
+extern cpuop_func_ce op_d118_23_nf;
+extern cpuop_func_ce op_d118_23_ff;
+extern cpuop_func_ce op_d120_23_nf;
+extern cpuop_func_ce op_d120_23_ff;
+extern cpuop_func_ce op_d128_23_nf;
+extern cpuop_func_ce op_d128_23_ff;
+extern cpuop_func_ce op_d130_23_nf;
+extern cpuop_func_ce op_d130_23_ff;
+extern cpuop_func_ce op_d138_23_nf;
+extern cpuop_func_ce op_d138_23_ff;
+extern cpuop_func_ce op_d139_23_nf;
+extern cpuop_func_ce op_d139_23_ff;
+extern cpuop_func_ce op_d140_23_nf;
+extern cpuop_func_ce op_d140_23_ff;
+extern cpuop_func_ce op_d148_23_nf;
+extern cpuop_func_ce op_d148_23_ff;
+extern cpuop_func_ce op_d150_23_nf;
+extern cpuop_func_ce op_d150_23_ff;
+extern cpuop_func_ce op_d158_23_nf;
+extern cpuop_func_ce op_d158_23_ff;
+extern cpuop_func_ce op_d160_23_nf;
+extern cpuop_func_ce op_d160_23_ff;
+extern cpuop_func_ce op_d168_23_nf;
+extern cpuop_func_ce op_d168_23_ff;
+extern cpuop_func_ce op_d170_23_nf;
+extern cpuop_func_ce op_d170_23_ff;
+extern cpuop_func_ce op_d178_23_nf;
+extern cpuop_func_ce op_d178_23_ff;
+extern cpuop_func_ce op_d179_23_nf;
+extern cpuop_func_ce op_d179_23_ff;
+extern cpuop_func_ce op_d180_23_nf;
+extern cpuop_func_ce op_d180_23_ff;
+extern cpuop_func_ce op_d188_23_nf;
+extern cpuop_func_ce op_d188_23_ff;
+extern cpuop_func_ce op_d190_23_nf;
+extern cpuop_func_ce op_d190_23_ff;
+extern cpuop_func_ce op_d198_23_nf;
+extern cpuop_func_ce op_d198_23_ff;
+extern cpuop_func_ce op_d1a0_23_nf;
+extern cpuop_func_ce op_d1a0_23_ff;
+extern cpuop_func_ce op_d1a8_23_nf;
+extern cpuop_func_ce op_d1a8_23_ff;
+extern cpuop_func_ce op_d1b0_23_nf;
+extern cpuop_func_ce op_d1b0_23_ff;
+extern cpuop_func_ce op_d1b8_23_nf;
+extern cpuop_func_ce op_d1b8_23_ff;
+extern cpuop_func_ce op_d1b9_23_nf;
+extern cpuop_func_ce op_d1b9_23_ff;
+extern cpuop_func_ce op_d1c0_23_nf;
+extern cpuop_func_ce op_d1c0_23_ff;
+extern cpuop_func_ce op_d1c8_23_nf;
+extern cpuop_func_ce op_d1c8_23_ff;
+extern cpuop_func_ce op_d1d0_23_nf;
+extern cpuop_func_ce op_d1d0_23_ff;
+extern cpuop_func_ce op_d1d8_23_nf;
+extern cpuop_func_ce op_d1d8_23_ff;
+extern cpuop_func_ce op_d1e0_23_nf;
+extern cpuop_func_ce op_d1e0_23_ff;
+extern cpuop_func_ce op_d1e8_23_nf;
+extern cpuop_func_ce op_d1e8_23_ff;
+extern cpuop_func_ce op_d1f0_23_nf;
+extern cpuop_func_ce op_d1f0_23_ff;
+extern cpuop_func_ce op_d1f8_23_nf;
+extern cpuop_func_ce op_d1f8_23_ff;
+extern cpuop_func_ce op_d1f9_23_nf;
+extern cpuop_func_ce op_d1f9_23_ff;
+extern cpuop_func_ce op_d1fa_23_nf;
+extern cpuop_func_ce op_d1fa_23_ff;
+extern cpuop_func_ce op_d1fb_23_nf;
+extern cpuop_func_ce op_d1fb_23_ff;
+extern cpuop_func_ce op_d1fc_23_nf;
+extern cpuop_func_ce op_d1fc_23_ff;
+extern cpuop_func_ce op_e000_23_nf;
+extern cpuop_func_ce op_e000_23_ff;
+extern cpuop_func_ce op_e008_23_nf;
+extern cpuop_func_ce op_e008_23_ff;
+extern cpuop_func_ce op_e010_23_nf;
+extern cpuop_func_ce op_e010_23_ff;
+extern cpuop_func_ce op_e018_23_nf;
+extern cpuop_func_ce op_e018_23_ff;
+extern cpuop_func_ce op_e020_23_nf;
+extern cpuop_func_ce op_e020_23_ff;
+extern cpuop_func_ce op_e028_23_nf;
+extern cpuop_func_ce op_e028_23_ff;
+extern cpuop_func_ce op_e030_23_nf;
+extern cpuop_func_ce op_e030_23_ff;
+extern cpuop_func_ce op_e038_23_nf;
+extern cpuop_func_ce op_e038_23_ff;
+extern cpuop_func_ce op_e040_23_nf;
+extern cpuop_func_ce op_e040_23_ff;
+extern cpuop_func_ce op_e048_23_nf;
+extern cpuop_func_ce op_e048_23_ff;
+extern cpuop_func_ce op_e050_23_nf;
+extern cpuop_func_ce op_e050_23_ff;
+extern cpuop_func_ce op_e058_23_nf;
+extern cpuop_func_ce op_e058_23_ff;
+extern cpuop_func_ce op_e060_23_nf;
+extern cpuop_func_ce op_e060_23_ff;
+extern cpuop_func_ce op_e068_23_nf;
+extern cpuop_func_ce op_e068_23_ff;
+extern cpuop_func_ce op_e070_23_nf;
+extern cpuop_func_ce op_e070_23_ff;
+extern cpuop_func_ce op_e078_23_nf;
+extern cpuop_func_ce op_e078_23_ff;
+extern cpuop_func_ce op_e080_23_nf;
+extern cpuop_func_ce op_e080_23_ff;
+extern cpuop_func_ce op_e088_23_nf;
+extern cpuop_func_ce op_e088_23_ff;
+extern cpuop_func_ce op_e090_23_nf;
+extern cpuop_func_ce op_e090_23_ff;
+extern cpuop_func_ce op_e098_23_nf;
+extern cpuop_func_ce op_e098_23_ff;
+extern cpuop_func_ce op_e0a0_23_nf;
+extern cpuop_func_ce op_e0a0_23_ff;
+extern cpuop_func_ce op_e0a8_23_nf;
+extern cpuop_func_ce op_e0a8_23_ff;
+extern cpuop_func_ce op_e0b0_23_nf;
+extern cpuop_func_ce op_e0b0_23_ff;
+extern cpuop_func_ce op_e0b8_23_nf;
+extern cpuop_func_ce op_e0b8_23_ff;
+extern cpuop_func_ce op_e0d0_23_nf;
+extern cpuop_func_ce op_e0d0_23_ff;
+extern cpuop_func_ce op_e0d8_23_nf;
+extern cpuop_func_ce op_e0d8_23_ff;
+extern cpuop_func_ce op_e0e0_23_nf;
+extern cpuop_func_ce op_e0e0_23_ff;
+extern cpuop_func_ce op_e0e8_23_nf;
+extern cpuop_func_ce op_e0e8_23_ff;
+extern cpuop_func_ce op_e0f0_23_nf;
+extern cpuop_func_ce op_e0f0_23_ff;
+extern cpuop_func_ce op_e0f8_23_nf;
+extern cpuop_func_ce op_e0f8_23_ff;
+extern cpuop_func_ce op_e0f9_23_nf;
+extern cpuop_func_ce op_e0f9_23_ff;
+extern cpuop_func_ce op_e100_23_nf;
+extern cpuop_func_ce op_e100_23_ff;
+extern cpuop_func_ce op_e108_23_nf;
+extern cpuop_func_ce op_e108_23_ff;
+extern cpuop_func_ce op_e110_23_nf;
+extern cpuop_func_ce op_e110_23_ff;
+extern cpuop_func_ce op_e118_23_nf;
+extern cpuop_func_ce op_e118_23_ff;
+extern cpuop_func_ce op_e120_23_nf;
+extern cpuop_func_ce op_e120_23_ff;
+extern cpuop_func_ce op_e128_23_nf;
+extern cpuop_func_ce op_e128_23_ff;
+extern cpuop_func_ce op_e130_23_nf;
+extern cpuop_func_ce op_e130_23_ff;
+extern cpuop_func_ce op_e138_23_nf;
+extern cpuop_func_ce op_e138_23_ff;
+extern cpuop_func_ce op_e140_23_nf;
+extern cpuop_func_ce op_e140_23_ff;
+extern cpuop_func_ce op_e148_23_nf;
+extern cpuop_func_ce op_e148_23_ff;
+extern cpuop_func_ce op_e150_23_nf;
+extern cpuop_func_ce op_e150_23_ff;
+extern cpuop_func_ce op_e158_23_nf;
+extern cpuop_func_ce op_e158_23_ff;
+extern cpuop_func_ce op_e160_23_nf;
+extern cpuop_func_ce op_e160_23_ff;
+extern cpuop_func_ce op_e168_23_nf;
+extern cpuop_func_ce op_e168_23_ff;
+extern cpuop_func_ce op_e170_23_nf;
+extern cpuop_func_ce op_e170_23_ff;
+extern cpuop_func_ce op_e178_23_nf;
+extern cpuop_func_ce op_e178_23_ff;
+extern cpuop_func_ce op_e180_23_nf;
+extern cpuop_func_ce op_e180_23_ff;
+extern cpuop_func_ce op_e188_23_nf;
+extern cpuop_func_ce op_e188_23_ff;
+extern cpuop_func_ce op_e190_23_nf;
+extern cpuop_func_ce op_e190_23_ff;
+extern cpuop_func_ce op_e198_23_nf;
+extern cpuop_func_ce op_e198_23_ff;
+extern cpuop_func_ce op_e1a0_23_nf;
+extern cpuop_func_ce op_e1a0_23_ff;
+extern cpuop_func_ce op_e1a8_23_nf;
+extern cpuop_func_ce op_e1a8_23_ff;
+extern cpuop_func_ce op_e1b0_23_nf;
+extern cpuop_func_ce op_e1b0_23_ff;
+extern cpuop_func_ce op_e1b8_23_nf;
+extern cpuop_func_ce op_e1b8_23_ff;
+extern cpuop_func_ce op_e1d0_23_nf;
+extern cpuop_func_ce op_e1d0_23_ff;
+extern cpuop_func_ce op_e1d8_23_nf;
+extern cpuop_func_ce op_e1d8_23_ff;
+extern cpuop_func_ce op_e1e0_23_nf;
+extern cpuop_func_ce op_e1e0_23_ff;
+extern cpuop_func_ce op_e1e8_23_nf;
+extern cpuop_func_ce op_e1e8_23_ff;
+extern cpuop_func_ce op_e1f0_23_nf;
+extern cpuop_func_ce op_e1f0_23_ff;
+extern cpuop_func_ce op_e1f8_23_nf;
+extern cpuop_func_ce op_e1f8_23_ff;
+extern cpuop_func_ce op_e1f9_23_nf;
+extern cpuop_func_ce op_e1f9_23_ff;
+extern cpuop_func_ce op_e2d0_23_nf;
+extern cpuop_func_ce op_e2d0_23_ff;
+extern cpuop_func_ce op_e2d8_23_nf;
+extern cpuop_func_ce op_e2d8_23_ff;
+extern cpuop_func_ce op_e2e0_23_nf;
+extern cpuop_func_ce op_e2e0_23_ff;
+extern cpuop_func_ce op_e2e8_23_nf;
+extern cpuop_func_ce op_e2e8_23_ff;
+extern cpuop_func_ce op_e2f0_23_nf;
+extern cpuop_func_ce op_e2f0_23_ff;
+extern cpuop_func_ce op_e2f8_23_nf;
+extern cpuop_func_ce op_e2f8_23_ff;
+extern cpuop_func_ce op_e2f9_23_nf;
+extern cpuop_func_ce op_e2f9_23_ff;
+extern cpuop_func_ce op_e3d0_23_nf;
+extern cpuop_func_ce op_e3d0_23_ff;
+extern cpuop_func_ce op_e3d8_23_nf;
+extern cpuop_func_ce op_e3d8_23_ff;
+extern cpuop_func_ce op_e3e0_23_nf;
+extern cpuop_func_ce op_e3e0_23_ff;
+extern cpuop_func_ce op_e3e8_23_nf;
+extern cpuop_func_ce op_e3e8_23_ff;
+extern cpuop_func_ce op_e3f0_23_nf;
+extern cpuop_func_ce op_e3f0_23_ff;
+extern cpuop_func_ce op_e3f8_23_nf;
+extern cpuop_func_ce op_e3f8_23_ff;
+extern cpuop_func_ce op_e3f9_23_nf;
+extern cpuop_func_ce op_e3f9_23_ff;
+extern cpuop_func_ce op_e4d0_23_nf;
+extern cpuop_func_ce op_e4d0_23_ff;
+extern cpuop_func_ce op_e4d8_23_nf;
+extern cpuop_func_ce op_e4d8_23_ff;
+extern cpuop_func_ce op_e4e0_23_nf;
+extern cpuop_func_ce op_e4e0_23_ff;
+extern cpuop_func_ce op_e4e8_23_nf;
+extern cpuop_func_ce op_e4e8_23_ff;
+extern cpuop_func_ce op_e4f0_23_nf;
+extern cpuop_func_ce op_e4f0_23_ff;
+extern cpuop_func_ce op_e4f8_23_nf;
+extern cpuop_func_ce op_e4f8_23_ff;
+extern cpuop_func_ce op_e4f9_23_nf;
+extern cpuop_func_ce op_e4f9_23_ff;
+extern cpuop_func_ce op_e5d0_23_nf;
+extern cpuop_func_ce op_e5d0_23_ff;
+extern cpuop_func_ce op_e5d8_23_nf;
+extern cpuop_func_ce op_e5d8_23_ff;
+extern cpuop_func_ce op_e5e0_23_nf;
+extern cpuop_func_ce op_e5e0_23_ff;
+extern cpuop_func_ce op_e5e8_23_nf;
+extern cpuop_func_ce op_e5e8_23_ff;
+extern cpuop_func_ce op_e5f0_23_nf;
+extern cpuop_func_ce op_e5f0_23_ff;
+extern cpuop_func_ce op_e5f8_23_nf;
+extern cpuop_func_ce op_e5f8_23_ff;
+extern cpuop_func_ce op_e5f9_23_nf;
+extern cpuop_func_ce op_e5f9_23_ff;
+extern cpuop_func_ce op_e6d0_23_nf;
+extern cpuop_func_ce op_e6d0_23_ff;
+extern cpuop_func_ce op_e6d8_23_nf;
+extern cpuop_func_ce op_e6d8_23_ff;
+extern cpuop_func_ce op_e6e0_23_nf;
+extern cpuop_func_ce op_e6e0_23_ff;
+extern cpuop_func_ce op_e6e8_23_nf;
+extern cpuop_func_ce op_e6e8_23_ff;
+extern cpuop_func_ce op_e6f0_23_nf;
+extern cpuop_func_ce op_e6f0_23_ff;
+extern cpuop_func_ce op_e6f8_23_nf;
+extern cpuop_func_ce op_e6f8_23_ff;
+extern cpuop_func_ce op_e6f9_23_nf;
+extern cpuop_func_ce op_e6f9_23_ff;
+extern cpuop_func_ce op_e7d0_23_nf;
+extern cpuop_func_ce op_e7d0_23_ff;
+extern cpuop_func_ce op_e7d8_23_nf;
+extern cpuop_func_ce op_e7d8_23_ff;
+extern cpuop_func_ce op_e7e0_23_nf;
+extern cpuop_func_ce op_e7e0_23_ff;
+extern cpuop_func_ce op_e7e8_23_nf;
+extern cpuop_func_ce op_e7e8_23_ff;
+extern cpuop_func_ce op_e7f0_23_nf;
+extern cpuop_func_ce op_e7f0_23_ff;
+extern cpuop_func_ce op_e7f8_23_nf;
+extern cpuop_func_ce op_e7f8_23_ff;
+extern cpuop_func_ce op_e7f9_23_nf;
+extern cpuop_func_ce op_e7f9_23_ff;
+extern cpuop_func_ce op_e8c0_23_nf;
+extern cpuop_func_ce op_e8c0_23_ff;
+extern cpuop_func_ce op_e8d0_23_nf;
+extern cpuop_func_ce op_e8d0_23_ff;
+extern cpuop_func_ce op_e8e8_23_nf;
+extern cpuop_func_ce op_e8e8_23_ff;
+extern cpuop_func_ce op_e8f0_23_nf;
+extern cpuop_func_ce op_e8f0_23_ff;
+extern cpuop_func_ce op_e8f8_23_nf;
+extern cpuop_func_ce op_e8f8_23_ff;
+extern cpuop_func_ce op_e8f9_23_nf;
+extern cpuop_func_ce op_e8f9_23_ff;
+extern cpuop_func_ce op_e8fa_23_nf;
+extern cpuop_func_ce op_e8fa_23_ff;
+extern cpuop_func_ce op_e8fb_23_nf;
+extern cpuop_func_ce op_e8fb_23_ff;
+extern cpuop_func_ce op_e9c0_23_nf;
+extern cpuop_func_ce op_e9c0_23_ff;
+extern cpuop_func_ce op_e9d0_23_nf;
+extern cpuop_func_ce op_e9d0_23_ff;
+extern cpuop_func_ce op_e9e8_23_nf;
+extern cpuop_func_ce op_e9e8_23_ff;
+extern cpuop_func_ce op_e9f0_23_nf;
+extern cpuop_func_ce op_e9f0_23_ff;
+extern cpuop_func_ce op_e9f8_23_nf;
+extern cpuop_func_ce op_e9f8_23_ff;
+extern cpuop_func_ce op_e9f9_23_nf;
+extern cpuop_func_ce op_e9f9_23_ff;
+extern cpuop_func_ce op_e9fa_23_nf;
+extern cpuop_func_ce op_e9fa_23_ff;
+extern cpuop_func_ce op_e9fb_23_nf;
+extern cpuop_func_ce op_e9fb_23_ff;
+extern cpuop_func_ce op_eac0_23_nf;
+extern cpuop_func_ce op_eac0_23_ff;
+extern cpuop_func_ce op_ead0_23_nf;
+extern cpuop_func_ce op_ead0_23_ff;
+extern cpuop_func_ce op_eae8_23_nf;
+extern cpuop_func_ce op_eae8_23_ff;
+extern cpuop_func_ce op_eaf0_23_nf;
+extern cpuop_func_ce op_eaf0_23_ff;
+extern cpuop_func_ce op_eaf8_23_nf;
+extern cpuop_func_ce op_eaf8_23_ff;
+extern cpuop_func_ce op_eaf9_23_nf;
+extern cpuop_func_ce op_eaf9_23_ff;
+extern cpuop_func_ce op_ebc0_23_nf;
+extern cpuop_func_ce op_ebc0_23_ff;
+extern cpuop_func_ce op_ebd0_23_nf;
+extern cpuop_func_ce op_ebd0_23_ff;
+extern cpuop_func_ce op_ebe8_23_nf;
+extern cpuop_func_ce op_ebe8_23_ff;
+extern cpuop_func_ce op_ebf0_23_nf;
+extern cpuop_func_ce op_ebf0_23_ff;
+extern cpuop_func_ce op_ebf8_23_nf;
+extern cpuop_func_ce op_ebf8_23_ff;
+extern cpuop_func_ce op_ebf9_23_nf;
+extern cpuop_func_ce op_ebf9_23_ff;
+extern cpuop_func_ce op_ebfa_23_nf;
+extern cpuop_func_ce op_ebfa_23_ff;
+extern cpuop_func_ce op_ebfb_23_nf;
+extern cpuop_func_ce op_ebfb_23_ff;
+extern cpuop_func_ce op_ecc0_23_nf;
+extern cpuop_func_ce op_ecc0_23_ff;
+extern cpuop_func_ce op_ecd0_23_nf;
+extern cpuop_func_ce op_ecd0_23_ff;
+extern cpuop_func_ce op_ece8_23_nf;
+extern cpuop_func_ce op_ece8_23_ff;
+extern cpuop_func_ce op_ecf0_23_nf;
+extern cpuop_func_ce op_ecf0_23_ff;
+extern cpuop_func_ce op_ecf8_23_nf;
+extern cpuop_func_ce op_ecf8_23_ff;
+extern cpuop_func_ce op_ecf9_23_nf;
+extern cpuop_func_ce op_ecf9_23_ff;
+extern cpuop_func_ce op_edc0_23_nf;
+extern cpuop_func_ce op_edc0_23_ff;
+extern cpuop_func_ce op_edd0_23_nf;
+extern cpuop_func_ce op_edd0_23_ff;
+extern cpuop_func_ce op_ede8_23_nf;
+extern cpuop_func_ce op_ede8_23_ff;
+extern cpuop_func_ce op_edf0_23_nf;
+extern cpuop_func_ce op_edf0_23_ff;
+extern cpuop_func_ce op_edf8_23_nf;
+extern cpuop_func_ce op_edf8_23_ff;
+extern cpuop_func_ce op_edf9_23_nf;
+extern cpuop_func_ce op_edf9_23_ff;
+extern cpuop_func_ce op_edfa_23_nf;
+extern cpuop_func_ce op_edfa_23_ff;
+extern cpuop_func_ce op_edfb_23_nf;
+extern cpuop_func_ce op_edfb_23_ff;
+extern cpuop_func_ce op_eec0_23_nf;
+extern cpuop_func_ce op_eec0_23_ff;
+extern cpuop_func_ce op_eed0_23_nf;
+extern cpuop_func_ce op_eed0_23_ff;
+extern cpuop_func_ce op_eee8_23_nf;
+extern cpuop_func_ce op_eee8_23_ff;
+extern cpuop_func_ce op_eef0_23_nf;
+extern cpuop_func_ce op_eef0_23_ff;
+extern cpuop_func_ce op_eef8_23_nf;
+extern cpuop_func_ce op_eef8_23_ff;
+extern cpuop_func_ce op_eef9_23_nf;
+extern cpuop_func_ce op_eef9_23_ff;
+extern cpuop_func_ce op_efc0_23_nf;
+extern cpuop_func_ce op_efc0_23_ff;
+extern cpuop_func_ce op_efd0_23_nf;
+extern cpuop_func_ce op_efd0_23_ff;
+extern cpuop_func_ce op_efe8_23_nf;
+extern cpuop_func_ce op_efe8_23_ff;
+extern cpuop_func_ce op_eff0_23_nf;
+extern cpuop_func_ce op_eff0_23_ff;
+extern cpuop_func_ce op_eff8_23_nf;
+extern cpuop_func_ce op_eff8_23_ff;
+extern cpuop_func_ce op_eff9_23_nf;
+extern cpuop_func_ce op_eff9_23_ff;
+extern cpuop_func_ce op_f000_23_nf;
+extern cpuop_func_ce op_f000_23_ff;
+extern cpuop_func_ce op_f008_23_nf;
+extern cpuop_func_ce op_f008_23_ff;
+extern cpuop_func_ce op_f010_23_nf;
+extern cpuop_func_ce op_f010_23_ff;
+extern cpuop_func_ce op_f018_23_nf;
+extern cpuop_func_ce op_f018_23_ff;
+extern cpuop_func_ce op_f020_23_nf;
+extern cpuop_func_ce op_f020_23_ff;
+extern cpuop_func_ce op_f028_23_nf;
+extern cpuop_func_ce op_f028_23_ff;
+extern cpuop_func_ce op_f030_23_nf;
+extern cpuop_func_ce op_f030_23_ff;
+extern cpuop_func_ce op_f038_23_nf;
+extern cpuop_func_ce op_f038_23_ff;
+extern cpuop_func_ce op_f039_23_nf;
+extern cpuop_func_ce op_f039_23_ff;
+extern cpuop_func_ce op_f200_23_nf;
+extern cpuop_func_ce op_f200_23_ff;
+extern cpuop_func_ce op_f208_23_nf;
+extern cpuop_func_ce op_f208_23_ff;
+extern cpuop_func_ce op_f210_23_nf;
+extern cpuop_func_ce op_f210_23_ff;
+extern cpuop_func_ce op_f218_23_nf;
+extern cpuop_func_ce op_f218_23_ff;
+extern cpuop_func_ce op_f220_23_nf;
+extern cpuop_func_ce op_f220_23_ff;
+extern cpuop_func_ce op_f228_23_nf;
+extern cpuop_func_ce op_f228_23_ff;
+extern cpuop_func_ce op_f230_23_nf;
+extern cpuop_func_ce op_f230_23_ff;
+extern cpuop_func_ce op_f238_23_nf;
+extern cpuop_func_ce op_f238_23_ff;
+extern cpuop_func_ce op_f239_23_nf;
+extern cpuop_func_ce op_f239_23_ff;
+extern cpuop_func_ce op_f23a_23_nf;
+extern cpuop_func_ce op_f23a_23_ff;
+extern cpuop_func_ce op_f23b_23_nf;
+extern cpuop_func_ce op_f23b_23_ff;
+extern cpuop_func_ce op_f23c_23_nf;
+extern cpuop_func_ce op_f23c_23_ff;
+extern cpuop_func_ce op_f240_23_nf;
+extern cpuop_func_ce op_f240_23_ff;
+extern cpuop_func_ce op_f248_23_nf;
+extern cpuop_func_ce op_f248_23_ff;
+extern cpuop_func_ce op_f250_23_nf;
+extern cpuop_func_ce op_f250_23_ff;
+extern cpuop_func_ce op_f258_23_nf;
+extern cpuop_func_ce op_f258_23_ff;
+extern cpuop_func_ce op_f260_23_nf;
+extern cpuop_func_ce op_f260_23_ff;
+extern cpuop_func_ce op_f268_23_nf;
+extern cpuop_func_ce op_f268_23_ff;
+extern cpuop_func_ce op_f270_23_nf;
+extern cpuop_func_ce op_f270_23_ff;
+extern cpuop_func_ce op_f278_23_nf;
+extern cpuop_func_ce op_f278_23_ff;
+extern cpuop_func_ce op_f279_23_nf;
+extern cpuop_func_ce op_f279_23_ff;
+extern cpuop_func_ce op_f27a_23_nf;
+extern cpuop_func_ce op_f27a_23_ff;
+extern cpuop_func_ce op_f27b_23_nf;
+extern cpuop_func_ce op_f27b_23_ff;
+extern cpuop_func_ce op_f27c_23_nf;
+extern cpuop_func_ce op_f27c_23_ff;
+extern cpuop_func_ce op_f280_23_nf;
+extern cpuop_func_ce op_f280_23_ff;
+extern cpuop_func_ce op_f2c0_23_nf;
+extern cpuop_func_ce op_f2c0_23_ff;
+extern cpuop_func_ce op_f310_23_nf;
+extern cpuop_func_ce op_f310_23_ff;
+extern cpuop_func_ce op_f320_23_nf;
+extern cpuop_func_ce op_f320_23_ff;
+extern cpuop_func_ce op_f328_23_nf;
+extern cpuop_func_ce op_f328_23_ff;
+extern cpuop_func_ce op_f330_23_nf;
+extern cpuop_func_ce op_f330_23_ff;
+extern cpuop_func_ce op_f338_23_nf;
+extern cpuop_func_ce op_f338_23_ff;
+extern cpuop_func_ce op_f339_23_nf;
+extern cpuop_func_ce op_f339_23_ff;
+extern cpuop_func_ce op_f350_23_nf;
+extern cpuop_func_ce op_f350_23_ff;
+extern cpuop_func_ce op_f358_23_nf;
+extern cpuop_func_ce op_f358_23_ff;
+extern cpuop_func_ce op_f368_23_nf;
+extern cpuop_func_ce op_f368_23_ff;
+extern cpuop_func_ce op_f370_23_nf;
+extern cpuop_func_ce op_f370_23_ff;
+extern cpuop_func_ce op_f378_23_nf;
+extern cpuop_func_ce op_f378_23_ff;
+extern cpuop_func_ce op_f379_23_nf;
+extern cpuop_func_ce op_f379_23_ff;
+extern cpuop_func_ce op_f37a_23_nf;
+extern cpuop_func_ce op_f37a_23_ff;
+extern cpuop_func_ce op_f37b_23_nf;
+extern cpuop_func_ce op_f37b_23_ff;
+extern cpuop_func_ce op_0000_24_nf;
+extern cpuop_func_ce op_0000_24_ff;
+extern cpuop_func_ce op_0010_24_nf;
+extern cpuop_func_ce op_0010_24_ff;
+extern cpuop_func_ce op_0018_24_nf;
+extern cpuop_func_ce op_0018_24_ff;
+extern cpuop_func_ce op_0020_24_nf;
+extern cpuop_func_ce op_0020_24_ff;
+extern cpuop_func_ce op_0028_24_nf;
+extern cpuop_func_ce op_0028_24_ff;
+extern cpuop_func_ce op_0030_24_nf;
+extern cpuop_func_ce op_0030_24_ff;
+extern cpuop_func_ce op_0038_24_nf;
+extern cpuop_func_ce op_0038_24_ff;
+extern cpuop_func_ce op_0039_24_nf;
+extern cpuop_func_ce op_0039_24_ff;
+extern cpuop_func_ce op_003c_24_nf;
+extern cpuop_func_ce op_003c_24_ff;
+extern cpuop_func_ce op_0040_24_nf;
+extern cpuop_func_ce op_0040_24_ff;
+extern cpuop_func_ce op_0050_24_nf;
+extern cpuop_func_ce op_0050_24_ff;
+extern cpuop_func_ce op_0058_24_nf;
+extern cpuop_func_ce op_0058_24_ff;
+extern cpuop_func_ce op_0060_24_nf;
+extern cpuop_func_ce op_0060_24_ff;
+extern cpuop_func_ce op_0068_24_nf;
+extern cpuop_func_ce op_0068_24_ff;
+extern cpuop_func_ce op_0070_24_nf;
+extern cpuop_func_ce op_0070_24_ff;
+extern cpuop_func_ce op_0078_24_nf;
+extern cpuop_func_ce op_0078_24_ff;
+extern cpuop_func_ce op_0079_24_nf;
+extern cpuop_func_ce op_0079_24_ff;
+extern cpuop_func_ce op_007c_24_nf;
+extern cpuop_func_ce op_007c_24_ff;
+extern cpuop_func_ce op_0080_24_nf;
+extern cpuop_func_ce op_0080_24_ff;
+extern cpuop_func_ce op_0090_24_nf;
+extern cpuop_func_ce op_0090_24_ff;
+extern cpuop_func_ce op_0098_24_nf;
+extern cpuop_func_ce op_0098_24_ff;
+extern cpuop_func_ce op_00a0_24_nf;
+extern cpuop_func_ce op_00a0_24_ff;
+extern cpuop_func_ce op_00a8_24_nf;
+extern cpuop_func_ce op_00a8_24_ff;
+extern cpuop_func_ce op_00b0_24_nf;
+extern cpuop_func_ce op_00b0_24_ff;
+extern cpuop_func_ce op_00b8_24_nf;
+extern cpuop_func_ce op_00b8_24_ff;
+extern cpuop_func_ce op_00b9_24_nf;
+extern cpuop_func_ce op_00b9_24_ff;
+extern cpuop_func_ce op_00d0_24_nf;
+extern cpuop_func_ce op_00d0_24_ff;
+extern cpuop_func_ce op_00e8_24_nf;
+extern cpuop_func_ce op_00e8_24_ff;
+extern cpuop_func_ce op_00f0_24_nf;
+extern cpuop_func_ce op_00f0_24_ff;
+extern cpuop_func_ce op_00f8_24_nf;
+extern cpuop_func_ce op_00f8_24_ff;
+extern cpuop_func_ce op_00f9_24_nf;
+extern cpuop_func_ce op_00f9_24_ff;
+extern cpuop_func_ce op_00fa_24_nf;
+extern cpuop_func_ce op_00fa_24_ff;
+extern cpuop_func_ce op_00fb_24_nf;
+extern cpuop_func_ce op_00fb_24_ff;
+extern cpuop_func_ce op_0100_24_nf;
+extern cpuop_func_ce op_0100_24_ff;
+extern cpuop_func_ce op_0108_24_nf;
+extern cpuop_func_ce op_0108_24_ff;
+extern cpuop_func_ce op_0110_24_nf;
+extern cpuop_func_ce op_0110_24_ff;
+extern cpuop_func_ce op_0118_24_nf;
+extern cpuop_func_ce op_0118_24_ff;
+extern cpuop_func_ce op_0120_24_nf;
+extern cpuop_func_ce op_0120_24_ff;
+extern cpuop_func_ce op_0128_24_nf;
+extern cpuop_func_ce op_0128_24_ff;
+extern cpuop_func_ce op_0130_24_nf;
+extern cpuop_func_ce op_0130_24_ff;
+extern cpuop_func_ce op_0138_24_nf;
+extern cpuop_func_ce op_0138_24_ff;
+extern cpuop_func_ce op_0139_24_nf;
+extern cpuop_func_ce op_0139_24_ff;
+extern cpuop_func_ce op_013a_24_nf;
+extern cpuop_func_ce op_013a_24_ff;
+extern cpuop_func_ce op_013b_24_nf;
+extern cpuop_func_ce op_013b_24_ff;
+extern cpuop_func_ce op_013c_24_nf;
+extern cpuop_func_ce op_013c_24_ff;
+extern cpuop_func_ce op_0140_24_nf;
+extern cpuop_func_ce op_0140_24_ff;
+extern cpuop_func_ce op_0148_24_nf;
+extern cpuop_func_ce op_0148_24_ff;
+extern cpuop_func_ce op_0150_24_nf;
+extern cpuop_func_ce op_0150_24_ff;
+extern cpuop_func_ce op_0158_24_nf;
+extern cpuop_func_ce op_0158_24_ff;
+extern cpuop_func_ce op_0160_24_nf;
+extern cpuop_func_ce op_0160_24_ff;
+extern cpuop_func_ce op_0168_24_nf;
+extern cpuop_func_ce op_0168_24_ff;
+extern cpuop_func_ce op_0170_24_nf;
+extern cpuop_func_ce op_0170_24_ff;
+extern cpuop_func_ce op_0178_24_nf;
+extern cpuop_func_ce op_0178_24_ff;
+extern cpuop_func_ce op_0179_24_nf;
+extern cpuop_func_ce op_0179_24_ff;
+extern cpuop_func_ce op_0180_24_nf;
+extern cpuop_func_ce op_0180_24_ff;
+extern cpuop_func_ce op_0188_24_nf;
+extern cpuop_func_ce op_0188_24_ff;
+extern cpuop_func_ce op_0190_24_nf;
+extern cpuop_func_ce op_0190_24_ff;
+extern cpuop_func_ce op_0198_24_nf;
+extern cpuop_func_ce op_0198_24_ff;
+extern cpuop_func_ce op_01a0_24_nf;
+extern cpuop_func_ce op_01a0_24_ff;
+extern cpuop_func_ce op_01a8_24_nf;
+extern cpuop_func_ce op_01a8_24_ff;
+extern cpuop_func_ce op_01b0_24_nf;
+extern cpuop_func_ce op_01b0_24_ff;
+extern cpuop_func_ce op_01b8_24_nf;
+extern cpuop_func_ce op_01b8_24_ff;
+extern cpuop_func_ce op_01b9_24_nf;
+extern cpuop_func_ce op_01b9_24_ff;
+extern cpuop_func_ce op_01c0_24_nf;
+extern cpuop_func_ce op_01c0_24_ff;
+extern cpuop_func_ce op_01c8_24_nf;
+extern cpuop_func_ce op_01c8_24_ff;
+extern cpuop_func_ce op_01d0_24_nf;
+extern cpuop_func_ce op_01d0_24_ff;
+extern cpuop_func_ce op_01d8_24_nf;
+extern cpuop_func_ce op_01d8_24_ff;
+extern cpuop_func_ce op_01e0_24_nf;
+extern cpuop_func_ce op_01e0_24_ff;
+extern cpuop_func_ce op_01e8_24_nf;
+extern cpuop_func_ce op_01e8_24_ff;
+extern cpuop_func_ce op_01f0_24_nf;
+extern cpuop_func_ce op_01f0_24_ff;
+extern cpuop_func_ce op_01f8_24_nf;
+extern cpuop_func_ce op_01f8_24_ff;
+extern cpuop_func_ce op_01f9_24_nf;
+extern cpuop_func_ce op_01f9_24_ff;
+extern cpuop_func_ce op_0200_24_nf;
+extern cpuop_func_ce op_0200_24_ff;
+extern cpuop_func_ce op_0210_24_nf;
+extern cpuop_func_ce op_0210_24_ff;
+extern cpuop_func_ce op_0218_24_nf;
+extern cpuop_func_ce op_0218_24_ff;
+extern cpuop_func_ce op_0220_24_nf;
+extern cpuop_func_ce op_0220_24_ff;
+extern cpuop_func_ce op_0228_24_nf;
+extern cpuop_func_ce op_0228_24_ff;
+extern cpuop_func_ce op_0230_24_nf;
+extern cpuop_func_ce op_0230_24_ff;
+extern cpuop_func_ce op_0238_24_nf;
+extern cpuop_func_ce op_0238_24_ff;
+extern cpuop_func_ce op_0239_24_nf;
+extern cpuop_func_ce op_0239_24_ff;
+extern cpuop_func_ce op_023c_24_nf;
+extern cpuop_func_ce op_023c_24_ff;
+extern cpuop_func_ce op_0240_24_nf;
+extern cpuop_func_ce op_0240_24_ff;
+extern cpuop_func_ce op_0250_24_nf;
+extern cpuop_func_ce op_0250_24_ff;
+extern cpuop_func_ce op_0258_24_nf;
+extern cpuop_func_ce op_0258_24_ff;
+extern cpuop_func_ce op_0260_24_nf;
+extern cpuop_func_ce op_0260_24_ff;
+extern cpuop_func_ce op_0268_24_nf;
+extern cpuop_func_ce op_0268_24_ff;
+extern cpuop_func_ce op_0270_24_nf;
+extern cpuop_func_ce op_0270_24_ff;
+extern cpuop_func_ce op_0278_24_nf;
+extern cpuop_func_ce op_0278_24_ff;
+extern cpuop_func_ce op_0279_24_nf;
+extern cpuop_func_ce op_0279_24_ff;
+extern cpuop_func_ce op_027c_24_nf;
+extern cpuop_func_ce op_027c_24_ff;
+extern cpuop_func_ce op_0280_24_nf;
+extern cpuop_func_ce op_0280_24_ff;
+extern cpuop_func_ce op_0290_24_nf;
+extern cpuop_func_ce op_0290_24_ff;
+extern cpuop_func_ce op_0298_24_nf;
+extern cpuop_func_ce op_0298_24_ff;
+extern cpuop_func_ce op_02a0_24_nf;
+extern cpuop_func_ce op_02a0_24_ff;
+extern cpuop_func_ce op_02a8_24_nf;
+extern cpuop_func_ce op_02a8_24_ff;
+extern cpuop_func_ce op_02b0_24_nf;
+extern cpuop_func_ce op_02b0_24_ff;
+extern cpuop_func_ce op_02b8_24_nf;
+extern cpuop_func_ce op_02b8_24_ff;
+extern cpuop_func_ce op_02b9_24_nf;
+extern cpuop_func_ce op_02b9_24_ff;
+extern cpuop_func_ce op_02d0_24_nf;
+extern cpuop_func_ce op_02d0_24_ff;
+extern cpuop_func_ce op_02e8_24_nf;
+extern cpuop_func_ce op_02e8_24_ff;
+extern cpuop_func_ce op_02f0_24_nf;
+extern cpuop_func_ce op_02f0_24_ff;
+extern cpuop_func_ce op_02f8_24_nf;
+extern cpuop_func_ce op_02f8_24_ff;
+extern cpuop_func_ce op_02f9_24_nf;
+extern cpuop_func_ce op_02f9_24_ff;
+extern cpuop_func_ce op_02fa_24_nf;
+extern cpuop_func_ce op_02fa_24_ff;
+extern cpuop_func_ce op_02fb_24_nf;
+extern cpuop_func_ce op_02fb_24_ff;
+extern cpuop_func_ce op_0400_24_nf;
+extern cpuop_func_ce op_0400_24_ff;
+extern cpuop_func_ce op_0410_24_nf;
+extern cpuop_func_ce op_0410_24_ff;
+extern cpuop_func_ce op_0418_24_nf;
+extern cpuop_func_ce op_0418_24_ff;
+extern cpuop_func_ce op_0420_24_nf;
+extern cpuop_func_ce op_0420_24_ff;
+extern cpuop_func_ce op_0428_24_nf;
+extern cpuop_func_ce op_0428_24_ff;
+extern cpuop_func_ce op_0430_24_nf;
+extern cpuop_func_ce op_0430_24_ff;
+extern cpuop_func_ce op_0438_24_nf;
+extern cpuop_func_ce op_0438_24_ff;
+extern cpuop_func_ce op_0439_24_nf;
+extern cpuop_func_ce op_0439_24_ff;
+extern cpuop_func_ce op_0440_24_nf;
+extern cpuop_func_ce op_0440_24_ff;
+extern cpuop_func_ce op_0450_24_nf;
+extern cpuop_func_ce op_0450_24_ff;
+extern cpuop_func_ce op_0458_24_nf;
+extern cpuop_func_ce op_0458_24_ff;
+extern cpuop_func_ce op_0460_24_nf;
+extern cpuop_func_ce op_0460_24_ff;
+extern cpuop_func_ce op_0468_24_nf;
+extern cpuop_func_ce op_0468_24_ff;
+extern cpuop_func_ce op_0470_24_nf;
+extern cpuop_func_ce op_0470_24_ff;
+extern cpuop_func_ce op_0478_24_nf;
+extern cpuop_func_ce op_0478_24_ff;
+extern cpuop_func_ce op_0479_24_nf;
+extern cpuop_func_ce op_0479_24_ff;
+extern cpuop_func_ce op_0480_24_nf;
+extern cpuop_func_ce op_0480_24_ff;
+extern cpuop_func_ce op_0490_24_nf;
+extern cpuop_func_ce op_0490_24_ff;
+extern cpuop_func_ce op_0498_24_nf;
+extern cpuop_func_ce op_0498_24_ff;
+extern cpuop_func_ce op_04a0_24_nf;
+extern cpuop_func_ce op_04a0_24_ff;
+extern cpuop_func_ce op_04a8_24_nf;
+extern cpuop_func_ce op_04a8_24_ff;
+extern cpuop_func_ce op_04b0_24_nf;
+extern cpuop_func_ce op_04b0_24_ff;
+extern cpuop_func_ce op_04b8_24_nf;
+extern cpuop_func_ce op_04b8_24_ff;
+extern cpuop_func_ce op_04b9_24_nf;
+extern cpuop_func_ce op_04b9_24_ff;
+extern cpuop_func_ce op_04d0_24_nf;
+extern cpuop_func_ce op_04d0_24_ff;
+extern cpuop_func_ce op_04e8_24_nf;
+extern cpuop_func_ce op_04e8_24_ff;
+extern cpuop_func_ce op_04f0_24_nf;
+extern cpuop_func_ce op_04f0_24_ff;
+extern cpuop_func_ce op_04f8_24_nf;
+extern cpuop_func_ce op_04f8_24_ff;
+extern cpuop_func_ce op_04f9_24_nf;
+extern cpuop_func_ce op_04f9_24_ff;
+extern cpuop_func_ce op_04fa_24_nf;
+extern cpuop_func_ce op_04fa_24_ff;
+extern cpuop_func_ce op_04fb_24_nf;
+extern cpuop_func_ce op_04fb_24_ff;
+extern cpuop_func_ce op_0600_24_nf;
+extern cpuop_func_ce op_0600_24_ff;
+extern cpuop_func_ce op_0610_24_nf;
+extern cpuop_func_ce op_0610_24_ff;
+extern cpuop_func_ce op_0618_24_nf;
+extern cpuop_func_ce op_0618_24_ff;
+extern cpuop_func_ce op_0620_24_nf;
+extern cpuop_func_ce op_0620_24_ff;
+extern cpuop_func_ce op_0628_24_nf;
+extern cpuop_func_ce op_0628_24_ff;
+extern cpuop_func_ce op_0630_24_nf;
+extern cpuop_func_ce op_0630_24_ff;
+extern cpuop_func_ce op_0638_24_nf;
+extern cpuop_func_ce op_0638_24_ff;
+extern cpuop_func_ce op_0639_24_nf;
+extern cpuop_func_ce op_0639_24_ff;
+extern cpuop_func_ce op_0640_24_nf;
+extern cpuop_func_ce op_0640_24_ff;
+extern cpuop_func_ce op_0650_24_nf;
+extern cpuop_func_ce op_0650_24_ff;
+extern cpuop_func_ce op_0658_24_nf;
+extern cpuop_func_ce op_0658_24_ff;
+extern cpuop_func_ce op_0660_24_nf;
+extern cpuop_func_ce op_0660_24_ff;
+extern cpuop_func_ce op_0668_24_nf;
+extern cpuop_func_ce op_0668_24_ff;
+extern cpuop_func_ce op_0670_24_nf;
+extern cpuop_func_ce op_0670_24_ff;
+extern cpuop_func_ce op_0678_24_nf;
+extern cpuop_func_ce op_0678_24_ff;
+extern cpuop_func_ce op_0679_24_nf;
+extern cpuop_func_ce op_0679_24_ff;
+extern cpuop_func_ce op_0680_24_nf;
+extern cpuop_func_ce op_0680_24_ff;
+extern cpuop_func_ce op_0690_24_nf;
+extern cpuop_func_ce op_0690_24_ff;
+extern cpuop_func_ce op_0698_24_nf;
+extern cpuop_func_ce op_0698_24_ff;
+extern cpuop_func_ce op_06a0_24_nf;
+extern cpuop_func_ce op_06a0_24_ff;
+extern cpuop_func_ce op_06a8_24_nf;
+extern cpuop_func_ce op_06a8_24_ff;
+extern cpuop_func_ce op_06b0_24_nf;
+extern cpuop_func_ce op_06b0_24_ff;
+extern cpuop_func_ce op_06b8_24_nf;
+extern cpuop_func_ce op_06b8_24_ff;
+extern cpuop_func_ce op_06b9_24_nf;
+extern cpuop_func_ce op_06b9_24_ff;
+extern cpuop_func_ce op_06c0_24_nf;
+extern cpuop_func_ce op_06c0_24_ff;
+extern cpuop_func_ce op_06c8_24_nf;
+extern cpuop_func_ce op_06c8_24_ff;
+extern cpuop_func_ce op_06d0_24_nf;
+extern cpuop_func_ce op_06d0_24_ff;
+extern cpuop_func_ce op_06e8_24_nf;
+extern cpuop_func_ce op_06e8_24_ff;
+extern cpuop_func_ce op_06f0_24_nf;
+extern cpuop_func_ce op_06f0_24_ff;
+extern cpuop_func_ce op_06f8_24_nf;
+extern cpuop_func_ce op_06f8_24_ff;
+extern cpuop_func_ce op_06f9_24_nf;
+extern cpuop_func_ce op_06f9_24_ff;
+extern cpuop_func_ce op_06fa_24_nf;
+extern cpuop_func_ce op_06fa_24_ff;
+extern cpuop_func_ce op_06fb_24_nf;
+extern cpuop_func_ce op_06fb_24_ff;
+extern cpuop_func_ce op_0800_24_nf;
+extern cpuop_func_ce op_0800_24_ff;
+extern cpuop_func_ce op_0810_24_nf;
+extern cpuop_func_ce op_0810_24_ff;
+extern cpuop_func_ce op_0818_24_nf;
+extern cpuop_func_ce op_0818_24_ff;
+extern cpuop_func_ce op_0820_24_nf;
+extern cpuop_func_ce op_0820_24_ff;
+extern cpuop_func_ce op_0828_24_nf;
+extern cpuop_func_ce op_0828_24_ff;
+extern cpuop_func_ce op_0830_24_nf;
+extern cpuop_func_ce op_0830_24_ff;
+extern cpuop_func_ce op_0838_24_nf;
+extern cpuop_func_ce op_0838_24_ff;
+extern cpuop_func_ce op_0839_24_nf;
+extern cpuop_func_ce op_0839_24_ff;
+extern cpuop_func_ce op_083a_24_nf;
+extern cpuop_func_ce op_083a_24_ff;
+extern cpuop_func_ce op_083b_24_nf;
+extern cpuop_func_ce op_083b_24_ff;
+extern cpuop_func_ce op_0840_24_nf;
+extern cpuop_func_ce op_0840_24_ff;
+extern cpuop_func_ce op_0850_24_nf;
+extern cpuop_func_ce op_0850_24_ff;
+extern cpuop_func_ce op_0858_24_nf;
+extern cpuop_func_ce op_0858_24_ff;
+extern cpuop_func_ce op_0860_24_nf;
+extern cpuop_func_ce op_0860_24_ff;
+extern cpuop_func_ce op_0868_24_nf;
+extern cpuop_func_ce op_0868_24_ff;
+extern cpuop_func_ce op_0870_24_nf;
+extern cpuop_func_ce op_0870_24_ff;
+extern cpuop_func_ce op_0878_24_nf;
+extern cpuop_func_ce op_0878_24_ff;
+extern cpuop_func_ce op_0879_24_nf;
+extern cpuop_func_ce op_0879_24_ff;
+extern cpuop_func_ce op_0880_24_nf;
+extern cpuop_func_ce op_0880_24_ff;
+extern cpuop_func_ce op_0890_24_nf;
+extern cpuop_func_ce op_0890_24_ff;
+extern cpuop_func_ce op_0898_24_nf;
+extern cpuop_func_ce op_0898_24_ff;
+extern cpuop_func_ce op_08a0_24_nf;
+extern cpuop_func_ce op_08a0_24_ff;
+extern cpuop_func_ce op_08a8_24_nf;
+extern cpuop_func_ce op_08a8_24_ff;
+extern cpuop_func_ce op_08b0_24_nf;
+extern cpuop_func_ce op_08b0_24_ff;
+extern cpuop_func_ce op_08b8_24_nf;
+extern cpuop_func_ce op_08b8_24_ff;
+extern cpuop_func_ce op_08b9_24_nf;
+extern cpuop_func_ce op_08b9_24_ff;
+extern cpuop_func_ce op_08c0_24_nf;
+extern cpuop_func_ce op_08c0_24_ff;
+extern cpuop_func_ce op_08d0_24_nf;
+extern cpuop_func_ce op_08d0_24_ff;
+extern cpuop_func_ce op_08d8_24_nf;
+extern cpuop_func_ce op_08d8_24_ff;
+extern cpuop_func_ce op_08e0_24_nf;
+extern cpuop_func_ce op_08e0_24_ff;
+extern cpuop_func_ce op_08e8_24_nf;
+extern cpuop_func_ce op_08e8_24_ff;
+extern cpuop_func_ce op_08f0_24_nf;
+extern cpuop_func_ce op_08f0_24_ff;
+extern cpuop_func_ce op_08f8_24_nf;
+extern cpuop_func_ce op_08f8_24_ff;
+extern cpuop_func_ce op_08f9_24_nf;
+extern cpuop_func_ce op_08f9_24_ff;
+extern cpuop_func_ce op_0a00_24_nf;
+extern cpuop_func_ce op_0a00_24_ff;
+extern cpuop_func_ce op_0a10_24_nf;
+extern cpuop_func_ce op_0a10_24_ff;
+extern cpuop_func_ce op_0a18_24_nf;
+extern cpuop_func_ce op_0a18_24_ff;
+extern cpuop_func_ce op_0a20_24_nf;
+extern cpuop_func_ce op_0a20_24_ff;
+extern cpuop_func_ce op_0a28_24_nf;
+extern cpuop_func_ce op_0a28_24_ff;
+extern cpuop_func_ce op_0a30_24_nf;
+extern cpuop_func_ce op_0a30_24_ff;
+extern cpuop_func_ce op_0a38_24_nf;
+extern cpuop_func_ce op_0a38_24_ff;
+extern cpuop_func_ce op_0a39_24_nf;
+extern cpuop_func_ce op_0a39_24_ff;
+extern cpuop_func_ce op_0a3c_24_nf;
+extern cpuop_func_ce op_0a3c_24_ff;
+extern cpuop_func_ce op_0a40_24_nf;
+extern cpuop_func_ce op_0a40_24_ff;
+extern cpuop_func_ce op_0a50_24_nf;
+extern cpuop_func_ce op_0a50_24_ff;
+extern cpuop_func_ce op_0a58_24_nf;
+extern cpuop_func_ce op_0a58_24_ff;
+extern cpuop_func_ce op_0a60_24_nf;
+extern cpuop_func_ce op_0a60_24_ff;
+extern cpuop_func_ce op_0a68_24_nf;
+extern cpuop_func_ce op_0a68_24_ff;
+extern cpuop_func_ce op_0a70_24_nf;
+extern cpuop_func_ce op_0a70_24_ff;
+extern cpuop_func_ce op_0a78_24_nf;
+extern cpuop_func_ce op_0a78_24_ff;
+extern cpuop_func_ce op_0a79_24_nf;
+extern cpuop_func_ce op_0a79_24_ff;
+extern cpuop_func_ce op_0a7c_24_nf;
+extern cpuop_func_ce op_0a7c_24_ff;
+extern cpuop_func_ce op_0a80_24_nf;
+extern cpuop_func_ce op_0a80_24_ff;
+extern cpuop_func_ce op_0a90_24_nf;
+extern cpuop_func_ce op_0a90_24_ff;
+extern cpuop_func_ce op_0a98_24_nf;
+extern cpuop_func_ce op_0a98_24_ff;
+extern cpuop_func_ce op_0aa0_24_nf;
+extern cpuop_func_ce op_0aa0_24_ff;
+extern cpuop_func_ce op_0aa8_24_nf;
+extern cpuop_func_ce op_0aa8_24_ff;
+extern cpuop_func_ce op_0ab0_24_nf;
+extern cpuop_func_ce op_0ab0_24_ff;
+extern cpuop_func_ce op_0ab8_24_nf;
+extern cpuop_func_ce op_0ab8_24_ff;
+extern cpuop_func_ce op_0ab9_24_nf;
+extern cpuop_func_ce op_0ab9_24_ff;
+extern cpuop_func_ce op_0ad0_24_nf;
+extern cpuop_func_ce op_0ad0_24_ff;
+extern cpuop_func_ce op_0ad8_24_nf;
+extern cpuop_func_ce op_0ad8_24_ff;
+extern cpuop_func_ce op_0ae0_24_nf;
+extern cpuop_func_ce op_0ae0_24_ff;
+extern cpuop_func_ce op_0ae8_24_nf;
+extern cpuop_func_ce op_0ae8_24_ff;
+extern cpuop_func_ce op_0af0_24_nf;
+extern cpuop_func_ce op_0af0_24_ff;
+extern cpuop_func_ce op_0af8_24_nf;
+extern cpuop_func_ce op_0af8_24_ff;
+extern cpuop_func_ce op_0af9_24_nf;
+extern cpuop_func_ce op_0af9_24_ff;
+extern cpuop_func_ce op_0c00_24_nf;
+extern cpuop_func_ce op_0c00_24_ff;
+extern cpuop_func_ce op_0c10_24_nf;
+extern cpuop_func_ce op_0c10_24_ff;
+extern cpuop_func_ce op_0c18_24_nf;
+extern cpuop_func_ce op_0c18_24_ff;
+extern cpuop_func_ce op_0c20_24_nf;
+extern cpuop_func_ce op_0c20_24_ff;
+extern cpuop_func_ce op_0c28_24_nf;
+extern cpuop_func_ce op_0c28_24_ff;
+extern cpuop_func_ce op_0c30_24_nf;
+extern cpuop_func_ce op_0c30_24_ff;
+extern cpuop_func_ce op_0c38_24_nf;
+extern cpuop_func_ce op_0c38_24_ff;
+extern cpuop_func_ce op_0c39_24_nf;
+extern cpuop_func_ce op_0c39_24_ff;
+extern cpuop_func_ce op_0c3a_24_nf;
+extern cpuop_func_ce op_0c3a_24_ff;
+extern cpuop_func_ce op_0c3b_24_nf;
+extern cpuop_func_ce op_0c3b_24_ff;
+extern cpuop_func_ce op_0c40_24_nf;
+extern cpuop_func_ce op_0c40_24_ff;
+extern cpuop_func_ce op_0c50_24_nf;
+extern cpuop_func_ce op_0c50_24_ff;
+extern cpuop_func_ce op_0c58_24_nf;
+extern cpuop_func_ce op_0c58_24_ff;
+extern cpuop_func_ce op_0c60_24_nf;
+extern cpuop_func_ce op_0c60_24_ff;
+extern cpuop_func_ce op_0c68_24_nf;
+extern cpuop_func_ce op_0c68_24_ff;
+extern cpuop_func_ce op_0c70_24_nf;
+extern cpuop_func_ce op_0c70_24_ff;
+extern cpuop_func_ce op_0c78_24_nf;
+extern cpuop_func_ce op_0c78_24_ff;
+extern cpuop_func_ce op_0c79_24_nf;
+extern cpuop_func_ce op_0c79_24_ff;
+extern cpuop_func_ce op_0c7a_24_nf;
+extern cpuop_func_ce op_0c7a_24_ff;
+extern cpuop_func_ce op_0c7b_24_nf;
+extern cpuop_func_ce op_0c7b_24_ff;
+extern cpuop_func_ce op_0c80_24_nf;
+extern cpuop_func_ce op_0c80_24_ff;
+extern cpuop_func_ce op_0c90_24_nf;
+extern cpuop_func_ce op_0c90_24_ff;
+extern cpuop_func_ce op_0c98_24_nf;
+extern cpuop_func_ce op_0c98_24_ff;
+extern cpuop_func_ce op_0ca0_24_nf;
+extern cpuop_func_ce op_0ca0_24_ff;
+extern cpuop_func_ce op_0ca8_24_nf;
+extern cpuop_func_ce op_0ca8_24_ff;
+extern cpuop_func_ce op_0cb0_24_nf;
+extern cpuop_func_ce op_0cb0_24_ff;
+extern cpuop_func_ce op_0cb8_24_nf;
+extern cpuop_func_ce op_0cb8_24_ff;
+extern cpuop_func_ce op_0cb9_24_nf;
+extern cpuop_func_ce op_0cb9_24_ff;
+extern cpuop_func_ce op_0cba_24_nf;
+extern cpuop_func_ce op_0cba_24_ff;
+extern cpuop_func_ce op_0cbb_24_nf;
+extern cpuop_func_ce op_0cbb_24_ff;
+extern cpuop_func_ce op_0cd0_24_nf;
+extern cpuop_func_ce op_0cd0_24_ff;
+extern cpuop_func_ce op_0cd8_24_nf;
+extern cpuop_func_ce op_0cd8_24_ff;
+extern cpuop_func_ce op_0ce0_24_nf;
+extern cpuop_func_ce op_0ce0_24_ff;
+extern cpuop_func_ce op_0ce8_24_nf;
+extern cpuop_func_ce op_0ce8_24_ff;
+extern cpuop_func_ce op_0cf0_24_nf;
+extern cpuop_func_ce op_0cf0_24_ff;
+extern cpuop_func_ce op_0cf8_24_nf;
+extern cpuop_func_ce op_0cf8_24_ff;
+extern cpuop_func_ce op_0cf9_24_nf;
+extern cpuop_func_ce op_0cf9_24_ff;
+extern cpuop_func_ce op_0cfc_24_nf;
+extern cpuop_func_ce op_0cfc_24_ff;
+extern cpuop_func_ce op_0e10_24_nf;
+extern cpuop_func_ce op_0e10_24_ff;
+extern cpuop_func_ce op_0e18_24_nf;
+extern cpuop_func_ce op_0e18_24_ff;
+extern cpuop_func_ce op_0e20_24_nf;
+extern cpuop_func_ce op_0e20_24_ff;
+extern cpuop_func_ce op_0e28_24_nf;
+extern cpuop_func_ce op_0e28_24_ff;
+extern cpuop_func_ce op_0e30_24_nf;
+extern cpuop_func_ce op_0e30_24_ff;
+extern cpuop_func_ce op_0e38_24_nf;
+extern cpuop_func_ce op_0e38_24_ff;
+extern cpuop_func_ce op_0e39_24_nf;
+extern cpuop_func_ce op_0e39_24_ff;
+extern cpuop_func_ce op_0e50_24_nf;
+extern cpuop_func_ce op_0e50_24_ff;
+extern cpuop_func_ce op_0e58_24_nf;
+extern cpuop_func_ce op_0e58_24_ff;
+extern cpuop_func_ce op_0e60_24_nf;
+extern cpuop_func_ce op_0e60_24_ff;
+extern cpuop_func_ce op_0e68_24_nf;
+extern cpuop_func_ce op_0e68_24_ff;
+extern cpuop_func_ce op_0e70_24_nf;
+extern cpuop_func_ce op_0e70_24_ff;
+extern cpuop_func_ce op_0e78_24_nf;
+extern cpuop_func_ce op_0e78_24_ff;
+extern cpuop_func_ce op_0e79_24_nf;
+extern cpuop_func_ce op_0e79_24_ff;
+extern cpuop_func_ce op_0e90_24_nf;
+extern cpuop_func_ce op_0e90_24_ff;
+extern cpuop_func_ce op_0e98_24_nf;
+extern cpuop_func_ce op_0e98_24_ff;
+extern cpuop_func_ce op_0ea0_24_nf;
+extern cpuop_func_ce op_0ea0_24_ff;
+extern cpuop_func_ce op_0ea8_24_nf;
+extern cpuop_func_ce op_0ea8_24_ff;
+extern cpuop_func_ce op_0eb0_24_nf;
+extern cpuop_func_ce op_0eb0_24_ff;
+extern cpuop_func_ce op_0eb8_24_nf;
+extern cpuop_func_ce op_0eb8_24_ff;
+extern cpuop_func_ce op_0eb9_24_nf;
+extern cpuop_func_ce op_0eb9_24_ff;
+extern cpuop_func_ce op_0ed0_24_nf;
+extern cpuop_func_ce op_0ed0_24_ff;
+extern cpuop_func_ce op_0ed8_24_nf;
+extern cpuop_func_ce op_0ed8_24_ff;
+extern cpuop_func_ce op_0ee0_24_nf;
+extern cpuop_func_ce op_0ee0_24_ff;
+extern cpuop_func_ce op_0ee8_24_nf;
+extern cpuop_func_ce op_0ee8_24_ff;
+extern cpuop_func_ce op_0ef0_24_nf;
+extern cpuop_func_ce op_0ef0_24_ff;
+extern cpuop_func_ce op_0ef8_24_nf;
+extern cpuop_func_ce op_0ef8_24_ff;
+extern cpuop_func_ce op_0ef9_24_nf;
+extern cpuop_func_ce op_0ef9_24_ff;
+extern cpuop_func_ce op_0efc_24_nf;
+extern cpuop_func_ce op_0efc_24_ff;
+extern cpuop_func_ce op_1000_24_nf;
+extern cpuop_func_ce op_1000_24_ff;
+extern cpuop_func_ce op_1010_24_nf;
+extern cpuop_func_ce op_1010_24_ff;
+extern cpuop_func_ce op_1018_24_nf;
+extern cpuop_func_ce op_1018_24_ff;
+extern cpuop_func_ce op_1020_24_nf;
+extern cpuop_func_ce op_1020_24_ff;
+extern cpuop_func_ce op_1028_24_nf;
+extern cpuop_func_ce op_1028_24_ff;
+extern cpuop_func_ce op_1030_24_nf;
+extern cpuop_func_ce op_1030_24_ff;
+extern cpuop_func_ce op_1038_24_nf;
+extern cpuop_func_ce op_1038_24_ff;
+extern cpuop_func_ce op_1039_24_nf;
+extern cpuop_func_ce op_1039_24_ff;
+extern cpuop_func_ce op_103a_24_nf;
+extern cpuop_func_ce op_103a_24_ff;
+extern cpuop_func_ce op_103b_24_nf;
+extern cpuop_func_ce op_103b_24_ff;
+extern cpuop_func_ce op_103c_24_nf;
+extern cpuop_func_ce op_103c_24_ff;
+extern cpuop_func_ce op_1080_24_nf;
+extern cpuop_func_ce op_1080_24_ff;
+extern cpuop_func_ce op_1090_24_nf;
+extern cpuop_func_ce op_1090_24_ff;
+extern cpuop_func_ce op_1098_24_nf;
+extern cpuop_func_ce op_1098_24_ff;
+extern cpuop_func_ce op_10a0_24_nf;
+extern cpuop_func_ce op_10a0_24_ff;
+extern cpuop_func_ce op_10a8_24_nf;
+extern cpuop_func_ce op_10a8_24_ff;
+extern cpuop_func_ce op_10b0_24_nf;
+extern cpuop_func_ce op_10b0_24_ff;
+extern cpuop_func_ce op_10b8_24_nf;
+extern cpuop_func_ce op_10b8_24_ff;
+extern cpuop_func_ce op_10b9_24_nf;
+extern cpuop_func_ce op_10b9_24_ff;
+extern cpuop_func_ce op_10ba_24_nf;
+extern cpuop_func_ce op_10ba_24_ff;
+extern cpuop_func_ce op_10bb_24_nf;
+extern cpuop_func_ce op_10bb_24_ff;
+extern cpuop_func_ce op_10bc_24_nf;
+extern cpuop_func_ce op_10bc_24_ff;
+extern cpuop_func_ce op_10c0_24_nf;
+extern cpuop_func_ce op_10c0_24_ff;
+extern cpuop_func_ce op_10d0_24_nf;
+extern cpuop_func_ce op_10d0_24_ff;
+extern cpuop_func_ce op_10d8_24_nf;
+extern cpuop_func_ce op_10d8_24_ff;
+extern cpuop_func_ce op_10e0_24_nf;
+extern cpuop_func_ce op_10e0_24_ff;
+extern cpuop_func_ce op_10e8_24_nf;
+extern cpuop_func_ce op_10e8_24_ff;
+extern cpuop_func_ce op_10f0_24_nf;
+extern cpuop_func_ce op_10f0_24_ff;
+extern cpuop_func_ce op_10f8_24_nf;
+extern cpuop_func_ce op_10f8_24_ff;
+extern cpuop_func_ce op_10f9_24_nf;
+extern cpuop_func_ce op_10f9_24_ff;
+extern cpuop_func_ce op_10fa_24_nf;
+extern cpuop_func_ce op_10fa_24_ff;
+extern cpuop_func_ce op_10fb_24_nf;
+extern cpuop_func_ce op_10fb_24_ff;
+extern cpuop_func_ce op_10fc_24_nf;
+extern cpuop_func_ce op_10fc_24_ff;
+extern cpuop_func_ce op_1100_24_nf;
+extern cpuop_func_ce op_1100_24_ff;
+extern cpuop_func_ce op_1110_24_nf;
+extern cpuop_func_ce op_1110_24_ff;
+extern cpuop_func_ce op_1118_24_nf;
+extern cpuop_func_ce op_1118_24_ff;
+extern cpuop_func_ce op_1120_24_nf;
+extern cpuop_func_ce op_1120_24_ff;
+extern cpuop_func_ce op_1128_24_nf;
+extern cpuop_func_ce op_1128_24_ff;
+extern cpuop_func_ce op_1130_24_nf;
+extern cpuop_func_ce op_1130_24_ff;
+extern cpuop_func_ce op_1138_24_nf;
+extern cpuop_func_ce op_1138_24_ff;
+extern cpuop_func_ce op_1139_24_nf;
+extern cpuop_func_ce op_1139_24_ff;
+extern cpuop_func_ce op_113a_24_nf;
+extern cpuop_func_ce op_113a_24_ff;
+extern cpuop_func_ce op_113b_24_nf;
+extern cpuop_func_ce op_113b_24_ff;
+extern cpuop_func_ce op_113c_24_nf;
+extern cpuop_func_ce op_113c_24_ff;
+extern cpuop_func_ce op_1140_24_nf;
+extern cpuop_func_ce op_1140_24_ff;
+extern cpuop_func_ce op_1150_24_nf;
+extern cpuop_func_ce op_1150_24_ff;
+extern cpuop_func_ce op_1158_24_nf;
+extern cpuop_func_ce op_1158_24_ff;
+extern cpuop_func_ce op_1160_24_nf;
+extern cpuop_func_ce op_1160_24_ff;
+extern cpuop_func_ce op_1168_24_nf;
+extern cpuop_func_ce op_1168_24_ff;
+extern cpuop_func_ce op_1170_24_nf;
+extern cpuop_func_ce op_1170_24_ff;
+extern cpuop_func_ce op_1178_24_nf;
+extern cpuop_func_ce op_1178_24_ff;
+extern cpuop_func_ce op_1179_24_nf;
+extern cpuop_func_ce op_1179_24_ff;
+extern cpuop_func_ce op_117a_24_nf;
+extern cpuop_func_ce op_117a_24_ff;
+extern cpuop_func_ce op_117b_24_nf;
+extern cpuop_func_ce op_117b_24_ff;
+extern cpuop_func_ce op_117c_24_nf;
+extern cpuop_func_ce op_117c_24_ff;
+extern cpuop_func_ce op_1180_24_nf;
+extern cpuop_func_ce op_1180_24_ff;
+extern cpuop_func_ce op_1190_24_nf;
+extern cpuop_func_ce op_1190_24_ff;
+extern cpuop_func_ce op_1198_24_nf;
+extern cpuop_func_ce op_1198_24_ff;
+extern cpuop_func_ce op_11a0_24_nf;
+extern cpuop_func_ce op_11a0_24_ff;
+extern cpuop_func_ce op_11a8_24_nf;
+extern cpuop_func_ce op_11a8_24_ff;
+extern cpuop_func_ce op_11b0_24_nf;
+extern cpuop_func_ce op_11b0_24_ff;
+extern cpuop_func_ce op_11b8_24_nf;
+extern cpuop_func_ce op_11b8_24_ff;
+extern cpuop_func_ce op_11b9_24_nf;
+extern cpuop_func_ce op_11b9_24_ff;
+extern cpuop_func_ce op_11ba_24_nf;
+extern cpuop_func_ce op_11ba_24_ff;
+extern cpuop_func_ce op_11bb_24_nf;
+extern cpuop_func_ce op_11bb_24_ff;
+extern cpuop_func_ce op_11bc_24_nf;
+extern cpuop_func_ce op_11bc_24_ff;
+extern cpuop_func_ce op_11c0_24_nf;
+extern cpuop_func_ce op_11c0_24_ff;
+extern cpuop_func_ce op_11d0_24_nf;
+extern cpuop_func_ce op_11d0_24_ff;
+extern cpuop_func_ce op_11d8_24_nf;
+extern cpuop_func_ce op_11d8_24_ff;
+extern cpuop_func_ce op_11e0_24_nf;
+extern cpuop_func_ce op_11e0_24_ff;
+extern cpuop_func_ce op_11e8_24_nf;
+extern cpuop_func_ce op_11e8_24_ff;
+extern cpuop_func_ce op_11f0_24_nf;
+extern cpuop_func_ce op_11f0_24_ff;
+extern cpuop_func_ce op_11f8_24_nf;
+extern cpuop_func_ce op_11f8_24_ff;
+extern cpuop_func_ce op_11f9_24_nf;
+extern cpuop_func_ce op_11f9_24_ff;
+extern cpuop_func_ce op_11fa_24_nf;
+extern cpuop_func_ce op_11fa_24_ff;
+extern cpuop_func_ce op_11fb_24_nf;
+extern cpuop_func_ce op_11fb_24_ff;
+extern cpuop_func_ce op_11fc_24_nf;
+extern cpuop_func_ce op_11fc_24_ff;
+extern cpuop_func_ce op_13c0_24_nf;
+extern cpuop_func_ce op_13c0_24_ff;
+extern cpuop_func_ce op_13d0_24_nf;
+extern cpuop_func_ce op_13d0_24_ff;
+extern cpuop_func_ce op_13d8_24_nf;
+extern cpuop_func_ce op_13d8_24_ff;
+extern cpuop_func_ce op_13e0_24_nf;
+extern cpuop_func_ce op_13e0_24_ff;
+extern cpuop_func_ce op_13e8_24_nf;
+extern cpuop_func_ce op_13e8_24_ff;
+extern cpuop_func_ce op_13f0_24_nf;
+extern cpuop_func_ce op_13f0_24_ff;
+extern cpuop_func_ce op_13f8_24_nf;
+extern cpuop_func_ce op_13f8_24_ff;
+extern cpuop_func_ce op_13f9_24_nf;
+extern cpuop_func_ce op_13f9_24_ff;
+extern cpuop_func_ce op_13fa_24_nf;
+extern cpuop_func_ce op_13fa_24_ff;
+extern cpuop_func_ce op_13fb_24_nf;
+extern cpuop_func_ce op_13fb_24_ff;
+extern cpuop_func_ce op_13fc_24_nf;
+extern cpuop_func_ce op_13fc_24_ff;
+extern cpuop_func_ce op_2000_24_nf;
+extern cpuop_func_ce op_2000_24_ff;
+extern cpuop_func_ce op_2008_24_nf;
+extern cpuop_func_ce op_2008_24_ff;
+extern cpuop_func_ce op_2010_24_nf;
+extern cpuop_func_ce op_2010_24_ff;
+extern cpuop_func_ce op_2018_24_nf;
+extern cpuop_func_ce op_2018_24_ff;
+extern cpuop_func_ce op_2020_24_nf;
+extern cpuop_func_ce op_2020_24_ff;
+extern cpuop_func_ce op_2028_24_nf;
+extern cpuop_func_ce op_2028_24_ff;
+extern cpuop_func_ce op_2030_24_nf;
+extern cpuop_func_ce op_2030_24_ff;
+extern cpuop_func_ce op_2038_24_nf;
+extern cpuop_func_ce op_2038_24_ff;
+extern cpuop_func_ce op_2039_24_nf;
+extern cpuop_func_ce op_2039_24_ff;
+extern cpuop_func_ce op_203a_24_nf;
+extern cpuop_func_ce op_203a_24_ff;
+extern cpuop_func_ce op_203b_24_nf;
+extern cpuop_func_ce op_203b_24_ff;
+extern cpuop_func_ce op_203c_24_nf;
+extern cpuop_func_ce op_203c_24_ff;
+extern cpuop_func_ce op_2040_24_nf;
+extern cpuop_func_ce op_2040_24_ff;
+extern cpuop_func_ce op_2048_24_nf;
+extern cpuop_func_ce op_2048_24_ff;
+extern cpuop_func_ce op_2050_24_nf;
+extern cpuop_func_ce op_2050_24_ff;
+extern cpuop_func_ce op_2058_24_nf;
+extern cpuop_func_ce op_2058_24_ff;
+extern cpuop_func_ce op_2060_24_nf;
+extern cpuop_func_ce op_2060_24_ff;
+extern cpuop_func_ce op_2068_24_nf;
+extern cpuop_func_ce op_2068_24_ff;
+extern cpuop_func_ce op_2070_24_nf;
+extern cpuop_func_ce op_2070_24_ff;
+extern cpuop_func_ce op_2078_24_nf;
+extern cpuop_func_ce op_2078_24_ff;
+extern cpuop_func_ce op_2079_24_nf;
+extern cpuop_func_ce op_2079_24_ff;
+extern cpuop_func_ce op_207a_24_nf;
+extern cpuop_func_ce op_207a_24_ff;
+extern cpuop_func_ce op_207b_24_nf;
+extern cpuop_func_ce op_207b_24_ff;
+extern cpuop_func_ce op_207c_24_nf;
+extern cpuop_func_ce op_207c_24_ff;
+extern cpuop_func_ce op_2080_24_nf;
+extern cpuop_func_ce op_2080_24_ff;
+extern cpuop_func_ce op_2088_24_nf;
+extern cpuop_func_ce op_2088_24_ff;
+extern cpuop_func_ce op_2090_24_nf;
+extern cpuop_func_ce op_2090_24_ff;
+extern cpuop_func_ce op_2098_24_nf;
+extern cpuop_func_ce op_2098_24_ff;
+extern cpuop_func_ce op_20a0_24_nf;
+extern cpuop_func_ce op_20a0_24_ff;
+extern cpuop_func_ce op_20a8_24_nf;
+extern cpuop_func_ce op_20a8_24_ff;
+extern cpuop_func_ce op_20b0_24_nf;
+extern cpuop_func_ce op_20b0_24_ff;
+extern cpuop_func_ce op_20b8_24_nf;
+extern cpuop_func_ce op_20b8_24_ff;
+extern cpuop_func_ce op_20b9_24_nf;
+extern cpuop_func_ce op_20b9_24_ff;
+extern cpuop_func_ce op_20ba_24_nf;
+extern cpuop_func_ce op_20ba_24_ff;
+extern cpuop_func_ce op_20bb_24_nf;
+extern cpuop_func_ce op_20bb_24_ff;
+extern cpuop_func_ce op_20bc_24_nf;
+extern cpuop_func_ce op_20bc_24_ff;
+extern cpuop_func_ce op_20c0_24_nf;
+extern cpuop_func_ce op_20c0_24_ff;
+extern cpuop_func_ce op_20c8_24_nf;
+extern cpuop_func_ce op_20c8_24_ff;
+extern cpuop_func_ce op_20d0_24_nf;
+extern cpuop_func_ce op_20d0_24_ff;
+extern cpuop_func_ce op_20d8_24_nf;
+extern cpuop_func_ce op_20d8_24_ff;
+extern cpuop_func_ce op_20e0_24_nf;
+extern cpuop_func_ce op_20e0_24_ff;
+extern cpuop_func_ce op_20e8_24_nf;
+extern cpuop_func_ce op_20e8_24_ff;
+extern cpuop_func_ce op_20f0_24_nf;
+extern cpuop_func_ce op_20f0_24_ff;
+extern cpuop_func_ce op_20f8_24_nf;
+extern cpuop_func_ce op_20f8_24_ff;
+extern cpuop_func_ce op_20f9_24_nf;
+extern cpuop_func_ce op_20f9_24_ff;
+extern cpuop_func_ce op_20fa_24_nf;
+extern cpuop_func_ce op_20fa_24_ff;
+extern cpuop_func_ce op_20fb_24_nf;
+extern cpuop_func_ce op_20fb_24_ff;
+extern cpuop_func_ce op_20fc_24_nf;
+extern cpuop_func_ce op_20fc_24_ff;
+extern cpuop_func_ce op_2100_24_nf;
+extern cpuop_func_ce op_2100_24_ff;
+extern cpuop_func_ce op_2108_24_nf;
+extern cpuop_func_ce op_2108_24_ff;
+extern cpuop_func_ce op_2110_24_nf;
+extern cpuop_func_ce op_2110_24_ff;
+extern cpuop_func_ce op_2118_24_nf;
+extern cpuop_func_ce op_2118_24_ff;
+extern cpuop_func_ce op_2120_24_nf;
+extern cpuop_func_ce op_2120_24_ff;
+extern cpuop_func_ce op_2128_24_nf;
+extern cpuop_func_ce op_2128_24_ff;
+extern cpuop_func_ce op_2130_24_nf;
+extern cpuop_func_ce op_2130_24_ff;
+extern cpuop_func_ce op_2138_24_nf;
+extern cpuop_func_ce op_2138_24_ff;
+extern cpuop_func_ce op_2139_24_nf;
+extern cpuop_func_ce op_2139_24_ff;
+extern cpuop_func_ce op_213a_24_nf;
+extern cpuop_func_ce op_213a_24_ff;
+extern cpuop_func_ce op_213b_24_nf;
+extern cpuop_func_ce op_213b_24_ff;
+extern cpuop_func_ce op_213c_24_nf;
+extern cpuop_func_ce op_213c_24_ff;
+extern cpuop_func_ce op_2140_24_nf;
+extern cpuop_func_ce op_2140_24_ff;
+extern cpuop_func_ce op_2148_24_nf;
+extern cpuop_func_ce op_2148_24_ff;
+extern cpuop_func_ce op_2150_24_nf;
+extern cpuop_func_ce op_2150_24_ff;
+extern cpuop_func_ce op_2158_24_nf;
+extern cpuop_func_ce op_2158_24_ff;
+extern cpuop_func_ce op_2160_24_nf;
+extern cpuop_func_ce op_2160_24_ff;
+extern cpuop_func_ce op_2168_24_nf;
+extern cpuop_func_ce op_2168_24_ff;
+extern cpuop_func_ce op_2170_24_nf;
+extern cpuop_func_ce op_2170_24_ff;
+extern cpuop_func_ce op_2178_24_nf;
+extern cpuop_func_ce op_2178_24_ff;
+extern cpuop_func_ce op_2179_24_nf;
+extern cpuop_func_ce op_2179_24_ff;
+extern cpuop_func_ce op_217a_24_nf;
+extern cpuop_func_ce op_217a_24_ff;
+extern cpuop_func_ce op_217b_24_nf;
+extern cpuop_func_ce op_217b_24_ff;
+extern cpuop_func_ce op_217c_24_nf;
+extern cpuop_func_ce op_217c_24_ff;
+extern cpuop_func_ce op_2180_24_nf;
+extern cpuop_func_ce op_2180_24_ff;
+extern cpuop_func_ce op_2188_24_nf;
+extern cpuop_func_ce op_2188_24_ff;
+extern cpuop_func_ce op_2190_24_nf;
+extern cpuop_func_ce op_2190_24_ff;
+extern cpuop_func_ce op_2198_24_nf;
+extern cpuop_func_ce op_2198_24_ff;
+extern cpuop_func_ce op_21a0_24_nf;
+extern cpuop_func_ce op_21a0_24_ff;
+extern cpuop_func_ce op_21a8_24_nf;
+extern cpuop_func_ce op_21a8_24_ff;
+extern cpuop_func_ce op_21b0_24_nf;
+extern cpuop_func_ce op_21b0_24_ff;
+extern cpuop_func_ce op_21b8_24_nf;
+extern cpuop_func_ce op_21b8_24_ff;
+extern cpuop_func_ce op_21b9_24_nf;
+extern cpuop_func_ce op_21b9_24_ff;
+extern cpuop_func_ce op_21ba_24_nf;
+extern cpuop_func_ce op_21ba_24_ff;
+extern cpuop_func_ce op_21bb_24_nf;
+extern cpuop_func_ce op_21bb_24_ff;
+extern cpuop_func_ce op_21bc_24_nf;
+extern cpuop_func_ce op_21bc_24_ff;
+extern cpuop_func_ce op_21c0_24_nf;
+extern cpuop_func_ce op_21c0_24_ff;
+extern cpuop_func_ce op_21c8_24_nf;
+extern cpuop_func_ce op_21c8_24_ff;
+extern cpuop_func_ce op_21d0_24_nf;
+extern cpuop_func_ce op_21d0_24_ff;
+extern cpuop_func_ce op_21d8_24_nf;
+extern cpuop_func_ce op_21d8_24_ff;
+extern cpuop_func_ce op_21e0_24_nf;
+extern cpuop_func_ce op_21e0_24_ff;
+extern cpuop_func_ce op_21e8_24_nf;
+extern cpuop_func_ce op_21e8_24_ff;
+extern cpuop_func_ce op_21f0_24_nf;
+extern cpuop_func_ce op_21f0_24_ff;
+extern cpuop_func_ce op_21f8_24_nf;
+extern cpuop_func_ce op_21f8_24_ff;
+extern cpuop_func_ce op_21f9_24_nf;
+extern cpuop_func_ce op_21f9_24_ff;
+extern cpuop_func_ce op_21fa_24_nf;
+extern cpuop_func_ce op_21fa_24_ff;
+extern cpuop_func_ce op_21fb_24_nf;
+extern cpuop_func_ce op_21fb_24_ff;
+extern cpuop_func_ce op_21fc_24_nf;
+extern cpuop_func_ce op_21fc_24_ff;
+extern cpuop_func_ce op_23c0_24_nf;
+extern cpuop_func_ce op_23c0_24_ff;
+extern cpuop_func_ce op_23c8_24_nf;
+extern cpuop_func_ce op_23c8_24_ff;
+extern cpuop_func_ce op_23d0_24_nf;
+extern cpuop_func_ce op_23d0_24_ff;
+extern cpuop_func_ce op_23d8_24_nf;
+extern cpuop_func_ce op_23d8_24_ff;
+extern cpuop_func_ce op_23e0_24_nf;
+extern cpuop_func_ce op_23e0_24_ff;
+extern cpuop_func_ce op_23e8_24_nf;
+extern cpuop_func_ce op_23e8_24_ff;
+extern cpuop_func_ce op_23f0_24_nf;
+extern cpuop_func_ce op_23f0_24_ff;
+extern cpuop_func_ce op_23f8_24_nf;
+extern cpuop_func_ce op_23f8_24_ff;
+extern cpuop_func_ce op_23f9_24_nf;
+extern cpuop_func_ce op_23f9_24_ff;
+extern cpuop_func_ce op_23fa_24_nf;
+extern cpuop_func_ce op_23fa_24_ff;
+extern cpuop_func_ce op_23fb_24_nf;
+extern cpuop_func_ce op_23fb_24_ff;
+extern cpuop_func_ce op_23fc_24_nf;
+extern cpuop_func_ce op_23fc_24_ff;
+extern cpuop_func_ce op_3000_24_nf;
+extern cpuop_func_ce op_3000_24_ff;
+extern cpuop_func_ce op_3008_24_nf;
+extern cpuop_func_ce op_3008_24_ff;
+extern cpuop_func_ce op_3010_24_nf;
+extern cpuop_func_ce op_3010_24_ff;
+extern cpuop_func_ce op_3018_24_nf;
+extern cpuop_func_ce op_3018_24_ff;
+extern cpuop_func_ce op_3020_24_nf;
+extern cpuop_func_ce op_3020_24_ff;
+extern cpuop_func_ce op_3028_24_nf;
+extern cpuop_func_ce op_3028_24_ff;
+extern cpuop_func_ce op_3030_24_nf;
+extern cpuop_func_ce op_3030_24_ff;
+extern cpuop_func_ce op_3038_24_nf;
+extern cpuop_func_ce op_3038_24_ff;
+extern cpuop_func_ce op_3039_24_nf;
+extern cpuop_func_ce op_3039_24_ff;
+extern cpuop_func_ce op_303a_24_nf;
+extern cpuop_func_ce op_303a_24_ff;
+extern cpuop_func_ce op_303b_24_nf;
+extern cpuop_func_ce op_303b_24_ff;
+extern cpuop_func_ce op_303c_24_nf;
+extern cpuop_func_ce op_303c_24_ff;
+extern cpuop_func_ce op_3040_24_nf;
+extern cpuop_func_ce op_3040_24_ff;
+extern cpuop_func_ce op_3048_24_nf;
+extern cpuop_func_ce op_3048_24_ff;
+extern cpuop_func_ce op_3050_24_nf;
+extern cpuop_func_ce op_3050_24_ff;
+extern cpuop_func_ce op_3058_24_nf;
+extern cpuop_func_ce op_3058_24_ff;
+extern cpuop_func_ce op_3060_24_nf;
+extern cpuop_func_ce op_3060_24_ff;
+extern cpuop_func_ce op_3068_24_nf;
+extern cpuop_func_ce op_3068_24_ff;
+extern cpuop_func_ce op_3070_24_nf;
+extern cpuop_func_ce op_3070_24_ff;
+extern cpuop_func_ce op_3078_24_nf;
+extern cpuop_func_ce op_3078_24_ff;
+extern cpuop_func_ce op_3079_24_nf;
+extern cpuop_func_ce op_3079_24_ff;
+extern cpuop_func_ce op_307a_24_nf;
+extern cpuop_func_ce op_307a_24_ff;
+extern cpuop_func_ce op_307b_24_nf;
+extern cpuop_func_ce op_307b_24_ff;
+extern cpuop_func_ce op_307c_24_nf;
+extern cpuop_func_ce op_307c_24_ff;
+extern cpuop_func_ce op_3080_24_nf;
+extern cpuop_func_ce op_3080_24_ff;
+extern cpuop_func_ce op_3088_24_nf;
+extern cpuop_func_ce op_3088_24_ff;
+extern cpuop_func_ce op_3090_24_nf;
+extern cpuop_func_ce op_3090_24_ff;
+extern cpuop_func_ce op_3098_24_nf;
+extern cpuop_func_ce op_3098_24_ff;
+extern cpuop_func_ce op_30a0_24_nf;
+extern cpuop_func_ce op_30a0_24_ff;
+extern cpuop_func_ce op_30a8_24_nf;
+extern cpuop_func_ce op_30a8_24_ff;
+extern cpuop_func_ce op_30b0_24_nf;
+extern cpuop_func_ce op_30b0_24_ff;
+extern cpuop_func_ce op_30b8_24_nf;
+extern cpuop_func_ce op_30b8_24_ff;
+extern cpuop_func_ce op_30b9_24_nf;
+extern cpuop_func_ce op_30b9_24_ff;
+extern cpuop_func_ce op_30ba_24_nf;
+extern cpuop_func_ce op_30ba_24_ff;
+extern cpuop_func_ce op_30bb_24_nf;
+extern cpuop_func_ce op_30bb_24_ff;
+extern cpuop_func_ce op_30bc_24_nf;
+extern cpuop_func_ce op_30bc_24_ff;
+extern cpuop_func_ce op_30c0_24_nf;
+extern cpuop_func_ce op_30c0_24_ff;
+extern cpuop_func_ce op_30c8_24_nf;
+extern cpuop_func_ce op_30c8_24_ff;
+extern cpuop_func_ce op_30d0_24_nf;
+extern cpuop_func_ce op_30d0_24_ff;
+extern cpuop_func_ce op_30d8_24_nf;
+extern cpuop_func_ce op_30d8_24_ff;
+extern cpuop_func_ce op_30e0_24_nf;
+extern cpuop_func_ce op_30e0_24_ff;
+extern cpuop_func_ce op_30e8_24_nf;
+extern cpuop_func_ce op_30e8_24_ff;
+extern cpuop_func_ce op_30f0_24_nf;
+extern cpuop_func_ce op_30f0_24_ff;
+extern cpuop_func_ce op_30f8_24_nf;
+extern cpuop_func_ce op_30f8_24_ff;
+extern cpuop_func_ce op_30f9_24_nf;
+extern cpuop_func_ce op_30f9_24_ff;
+extern cpuop_func_ce op_30fa_24_nf;
+extern cpuop_func_ce op_30fa_24_ff;
+extern cpuop_func_ce op_30fb_24_nf;
+extern cpuop_func_ce op_30fb_24_ff;
+extern cpuop_func_ce op_30fc_24_nf;
+extern cpuop_func_ce op_30fc_24_ff;
+extern cpuop_func_ce op_3100_24_nf;
+extern cpuop_func_ce op_3100_24_ff;
+extern cpuop_func_ce op_3108_24_nf;
+extern cpuop_func_ce op_3108_24_ff;
+extern cpuop_func_ce op_3110_24_nf;
+extern cpuop_func_ce op_3110_24_ff;
+extern cpuop_func_ce op_3118_24_nf;
+extern cpuop_func_ce op_3118_24_ff;
+extern cpuop_func_ce op_3120_24_nf;
+extern cpuop_func_ce op_3120_24_ff;
+extern cpuop_func_ce op_3128_24_nf;
+extern cpuop_func_ce op_3128_24_ff;
+extern cpuop_func_ce op_3130_24_nf;
+extern cpuop_func_ce op_3130_24_ff;
+extern cpuop_func_ce op_3138_24_nf;
+extern cpuop_func_ce op_3138_24_ff;
+extern cpuop_func_ce op_3139_24_nf;
+extern cpuop_func_ce op_3139_24_ff;
+extern cpuop_func_ce op_313a_24_nf;
+extern cpuop_func_ce op_313a_24_ff;
+extern cpuop_func_ce op_313b_24_nf;
+extern cpuop_func_ce op_313b_24_ff;
+extern cpuop_func_ce op_313c_24_nf;
+extern cpuop_func_ce op_313c_24_ff;
+extern cpuop_func_ce op_3140_24_nf;
+extern cpuop_func_ce op_3140_24_ff;
+extern cpuop_func_ce op_3148_24_nf;
+extern cpuop_func_ce op_3148_24_ff;
+extern cpuop_func_ce op_3150_24_nf;
+extern cpuop_func_ce op_3150_24_ff;
+extern cpuop_func_ce op_3158_24_nf;
+extern cpuop_func_ce op_3158_24_ff;
+extern cpuop_func_ce op_3160_24_nf;
+extern cpuop_func_ce op_3160_24_ff;
+extern cpuop_func_ce op_3168_24_nf;
+extern cpuop_func_ce op_3168_24_ff;
+extern cpuop_func_ce op_3170_24_nf;
+extern cpuop_func_ce op_3170_24_ff;
+extern cpuop_func_ce op_3178_24_nf;
+extern cpuop_func_ce op_3178_24_ff;
+extern cpuop_func_ce op_3179_24_nf;
+extern cpuop_func_ce op_3179_24_ff;
+extern cpuop_func_ce op_317a_24_nf;
+extern cpuop_func_ce op_317a_24_ff;
+extern cpuop_func_ce op_317b_24_nf;
+extern cpuop_func_ce op_317b_24_ff;
+extern cpuop_func_ce op_317c_24_nf;
+extern cpuop_func_ce op_317c_24_ff;
+extern cpuop_func_ce op_3180_24_nf;
+extern cpuop_func_ce op_3180_24_ff;
+extern cpuop_func_ce op_3188_24_nf;
+extern cpuop_func_ce op_3188_24_ff;
+extern cpuop_func_ce op_3190_24_nf;
+extern cpuop_func_ce op_3190_24_ff;
+extern cpuop_func_ce op_3198_24_nf;
+extern cpuop_func_ce op_3198_24_ff;
+extern cpuop_func_ce op_31a0_24_nf;
+extern cpuop_func_ce op_31a0_24_ff;
+extern cpuop_func_ce op_31a8_24_nf;
+extern cpuop_func_ce op_31a8_24_ff;
+extern cpuop_func_ce op_31b0_24_nf;
+extern cpuop_func_ce op_31b0_24_ff;
+extern cpuop_func_ce op_31b8_24_nf;
+extern cpuop_func_ce op_31b8_24_ff;
+extern cpuop_func_ce op_31b9_24_nf;
+extern cpuop_func_ce op_31b9_24_ff;
+extern cpuop_func_ce op_31ba_24_nf;
+extern cpuop_func_ce op_31ba_24_ff;
+extern cpuop_func_ce op_31bb_24_nf;
+extern cpuop_func_ce op_31bb_24_ff;
+extern cpuop_func_ce op_31bc_24_nf;
+extern cpuop_func_ce op_31bc_24_ff;
+extern cpuop_func_ce op_31c0_24_nf;
+extern cpuop_func_ce op_31c0_24_ff;
+extern cpuop_func_ce op_31c8_24_nf;
+extern cpuop_func_ce op_31c8_24_ff;
+extern cpuop_func_ce op_31d0_24_nf;
+extern cpuop_func_ce op_31d0_24_ff;
+extern cpuop_func_ce op_31d8_24_nf;
+extern cpuop_func_ce op_31d8_24_ff;
+extern cpuop_func_ce op_31e0_24_nf;
+extern cpuop_func_ce op_31e0_24_ff;
+extern cpuop_func_ce op_31e8_24_nf;
+extern cpuop_func_ce op_31e8_24_ff;
+extern cpuop_func_ce op_31f0_24_nf;
+extern cpuop_func_ce op_31f0_24_ff;
+extern cpuop_func_ce op_31f8_24_nf;
+extern cpuop_func_ce op_31f8_24_ff;
+extern cpuop_func_ce op_31f9_24_nf;
+extern cpuop_func_ce op_31f9_24_ff;
+extern cpuop_func_ce op_31fa_24_nf;
+extern cpuop_func_ce op_31fa_24_ff;
+extern cpuop_func_ce op_31fb_24_nf;
+extern cpuop_func_ce op_31fb_24_ff;
+extern cpuop_func_ce op_31fc_24_nf;
+extern cpuop_func_ce op_31fc_24_ff;
+extern cpuop_func_ce op_33c0_24_nf;
+extern cpuop_func_ce op_33c0_24_ff;
+extern cpuop_func_ce op_33c8_24_nf;
+extern cpuop_func_ce op_33c8_24_ff;
+extern cpuop_func_ce op_33d0_24_nf;
+extern cpuop_func_ce op_33d0_24_ff;
+extern cpuop_func_ce op_33d8_24_nf;
+extern cpuop_func_ce op_33d8_24_ff;
+extern cpuop_func_ce op_33e0_24_nf;
+extern cpuop_func_ce op_33e0_24_ff;
+extern cpuop_func_ce op_33e8_24_nf;
+extern cpuop_func_ce op_33e8_24_ff;
+extern cpuop_func_ce op_33f0_24_nf;
+extern cpuop_func_ce op_33f0_24_ff;
+extern cpuop_func_ce op_33f8_24_nf;
+extern cpuop_func_ce op_33f8_24_ff;
+extern cpuop_func_ce op_33f9_24_nf;
+extern cpuop_func_ce op_33f9_24_ff;
+extern cpuop_func_ce op_33fa_24_nf;
+extern cpuop_func_ce op_33fa_24_ff;
+extern cpuop_func_ce op_33fb_24_nf;
+extern cpuop_func_ce op_33fb_24_ff;
+extern cpuop_func_ce op_33fc_24_nf;
+extern cpuop_func_ce op_33fc_24_ff;
+extern cpuop_func_ce op_4000_24_nf;
+extern cpuop_func_ce op_4000_24_ff;
+extern cpuop_func_ce op_4010_24_nf;
+extern cpuop_func_ce op_4010_24_ff;
+extern cpuop_func_ce op_4018_24_nf;
+extern cpuop_func_ce op_4018_24_ff;
+extern cpuop_func_ce op_4020_24_nf;
+extern cpuop_func_ce op_4020_24_ff;
+extern cpuop_func_ce op_4028_24_nf;
+extern cpuop_func_ce op_4028_24_ff;
+extern cpuop_func_ce op_4030_24_nf;
+extern cpuop_func_ce op_4030_24_ff;
+extern cpuop_func_ce op_4038_24_nf;
+extern cpuop_func_ce op_4038_24_ff;
+extern cpuop_func_ce op_4039_24_nf;
+extern cpuop_func_ce op_4039_24_ff;
+extern cpuop_func_ce op_4040_24_nf;
+extern cpuop_func_ce op_4040_24_ff;
+extern cpuop_func_ce op_4050_24_nf;
+extern cpuop_func_ce op_4050_24_ff;
+extern cpuop_func_ce op_4058_24_nf;
+extern cpuop_func_ce op_4058_24_ff;
+extern cpuop_func_ce op_4060_24_nf;
+extern cpuop_func_ce op_4060_24_ff;
+extern cpuop_func_ce op_4068_24_nf;
+extern cpuop_func_ce op_4068_24_ff;
+extern cpuop_func_ce op_4070_24_nf;
+extern cpuop_func_ce op_4070_24_ff;
+extern cpuop_func_ce op_4078_24_nf;
+extern cpuop_func_ce op_4078_24_ff;
+extern cpuop_func_ce op_4079_24_nf;
+extern cpuop_func_ce op_4079_24_ff;
+extern cpuop_func_ce op_4080_24_nf;
+extern cpuop_func_ce op_4080_24_ff;
+extern cpuop_func_ce op_4090_24_nf;
+extern cpuop_func_ce op_4090_24_ff;
+extern cpuop_func_ce op_4098_24_nf;
+extern cpuop_func_ce op_4098_24_ff;
+extern cpuop_func_ce op_40a0_24_nf;
+extern cpuop_func_ce op_40a0_24_ff;
+extern cpuop_func_ce op_40a8_24_nf;
+extern cpuop_func_ce op_40a8_24_ff;
+extern cpuop_func_ce op_40b0_24_nf;
+extern cpuop_func_ce op_40b0_24_ff;
+extern cpuop_func_ce op_40b8_24_nf;
+extern cpuop_func_ce op_40b8_24_ff;
+extern cpuop_func_ce op_40b9_24_nf;
+extern cpuop_func_ce op_40b9_24_ff;
+extern cpuop_func_ce op_40c0_24_nf;
+extern cpuop_func_ce op_40c0_24_ff;
+extern cpuop_func_ce op_40d0_24_nf;
+extern cpuop_func_ce op_40d0_24_ff;
+extern cpuop_func_ce op_40d8_24_nf;
+extern cpuop_func_ce op_40d8_24_ff;
+extern cpuop_func_ce op_40e0_24_nf;
+extern cpuop_func_ce op_40e0_24_ff;
+extern cpuop_func_ce op_40e8_24_nf;
+extern cpuop_func_ce op_40e8_24_ff;
+extern cpuop_func_ce op_40f0_24_nf;
+extern cpuop_func_ce op_40f0_24_ff;
+extern cpuop_func_ce op_40f8_24_nf;
+extern cpuop_func_ce op_40f8_24_ff;
+extern cpuop_func_ce op_40f9_24_nf;
+extern cpuop_func_ce op_40f9_24_ff;
+extern cpuop_func_ce op_4100_24_nf;
+extern cpuop_func_ce op_4100_24_ff;
+extern cpuop_func_ce op_4110_24_nf;
+extern cpuop_func_ce op_4110_24_ff;
+extern cpuop_func_ce op_4118_24_nf;
+extern cpuop_func_ce op_4118_24_ff;
+extern cpuop_func_ce op_4120_24_nf;
+extern cpuop_func_ce op_4120_24_ff;
+extern cpuop_func_ce op_4128_24_nf;
+extern cpuop_func_ce op_4128_24_ff;
+extern cpuop_func_ce op_4130_24_nf;
+extern cpuop_func_ce op_4130_24_ff;
+extern cpuop_func_ce op_4138_24_nf;
+extern cpuop_func_ce op_4138_24_ff;
+extern cpuop_func_ce op_4139_24_nf;
+extern cpuop_func_ce op_4139_24_ff;
+extern cpuop_func_ce op_413a_24_nf;
+extern cpuop_func_ce op_413a_24_ff;
+extern cpuop_func_ce op_413b_24_nf;
+extern cpuop_func_ce op_413b_24_ff;
+extern cpuop_func_ce op_413c_24_nf;
+extern cpuop_func_ce op_413c_24_ff;
+extern cpuop_func_ce op_4180_24_nf;
+extern cpuop_func_ce op_4180_24_ff;
+extern cpuop_func_ce op_4190_24_nf;
+extern cpuop_func_ce op_4190_24_ff;
+extern cpuop_func_ce op_4198_24_nf;
+extern cpuop_func_ce op_4198_24_ff;
+extern cpuop_func_ce op_41a0_24_nf;
+extern cpuop_func_ce op_41a0_24_ff;
+extern cpuop_func_ce op_41a8_24_nf;
+extern cpuop_func_ce op_41a8_24_ff;
+extern cpuop_func_ce op_41b0_24_nf;
+extern cpuop_func_ce op_41b0_24_ff;
+extern cpuop_func_ce op_41b8_24_nf;
+extern cpuop_func_ce op_41b8_24_ff;
+extern cpuop_func_ce op_41b9_24_nf;
+extern cpuop_func_ce op_41b9_24_ff;
+extern cpuop_func_ce op_41ba_24_nf;
+extern cpuop_func_ce op_41ba_24_ff;
+extern cpuop_func_ce op_41bb_24_nf;
+extern cpuop_func_ce op_41bb_24_ff;
+extern cpuop_func_ce op_41bc_24_nf;
+extern cpuop_func_ce op_41bc_24_ff;
+extern cpuop_func_ce op_41d0_24_nf;
+extern cpuop_func_ce op_41d0_24_ff;
+extern cpuop_func_ce op_41e8_24_nf;
+extern cpuop_func_ce op_41e8_24_ff;
+extern cpuop_func_ce op_41f0_24_nf;
+extern cpuop_func_ce op_41f0_24_ff;
+extern cpuop_func_ce op_41f8_24_nf;
+extern cpuop_func_ce op_41f8_24_ff;
+extern cpuop_func_ce op_41f9_24_nf;
+extern cpuop_func_ce op_41f9_24_ff;
+extern cpuop_func_ce op_41fa_24_nf;
+extern cpuop_func_ce op_41fa_24_ff;
+extern cpuop_func_ce op_41fb_24_nf;
+extern cpuop_func_ce op_41fb_24_ff;
+extern cpuop_func_ce op_4200_24_nf;
+extern cpuop_func_ce op_4200_24_ff;
+extern cpuop_func_ce op_4210_24_nf;
+extern cpuop_func_ce op_4210_24_ff;
+extern cpuop_func_ce op_4218_24_nf;
+extern cpuop_func_ce op_4218_24_ff;
+extern cpuop_func_ce op_4220_24_nf;
+extern cpuop_func_ce op_4220_24_ff;
+extern cpuop_func_ce op_4228_24_nf;
+extern cpuop_func_ce op_4228_24_ff;
+extern cpuop_func_ce op_4230_24_nf;
+extern cpuop_func_ce op_4230_24_ff;
+extern cpuop_func_ce op_4238_24_nf;
+extern cpuop_func_ce op_4238_24_ff;
+extern cpuop_func_ce op_4239_24_nf;
+extern cpuop_func_ce op_4239_24_ff;
+extern cpuop_func_ce op_4240_24_nf;
+extern cpuop_func_ce op_4240_24_ff;
+extern cpuop_func_ce op_4250_24_nf;
+extern cpuop_func_ce op_4250_24_ff;
+extern cpuop_func_ce op_4258_24_nf;
+extern cpuop_func_ce op_4258_24_ff;
+extern cpuop_func_ce op_4260_24_nf;
+extern cpuop_func_ce op_4260_24_ff;
+extern cpuop_func_ce op_4268_24_nf;
+extern cpuop_func_ce op_4268_24_ff;
+extern cpuop_func_ce op_4270_24_nf;
+extern cpuop_func_ce op_4270_24_ff;
+extern cpuop_func_ce op_4278_24_nf;
+extern cpuop_func_ce op_4278_24_ff;
+extern cpuop_func_ce op_4279_24_nf;
+extern cpuop_func_ce op_4279_24_ff;
+extern cpuop_func_ce op_4280_24_nf;
+extern cpuop_func_ce op_4280_24_ff;
+extern cpuop_func_ce op_4290_24_nf;
+extern cpuop_func_ce op_4290_24_ff;
+extern cpuop_func_ce op_4298_24_nf;
+extern cpuop_func_ce op_4298_24_ff;
+extern cpuop_func_ce op_42a0_24_nf;
+extern cpuop_func_ce op_42a0_24_ff;
+extern cpuop_func_ce op_42a8_24_nf;
+extern cpuop_func_ce op_42a8_24_ff;
+extern cpuop_func_ce op_42b0_24_nf;
+extern cpuop_func_ce op_42b0_24_ff;
+extern cpuop_func_ce op_42b8_24_nf;
+extern cpuop_func_ce op_42b8_24_ff;
+extern cpuop_func_ce op_42b9_24_nf;
+extern cpuop_func_ce op_42b9_24_ff;
+extern cpuop_func_ce op_42c0_24_nf;
+extern cpuop_func_ce op_42c0_24_ff;
+extern cpuop_func_ce op_42d0_24_nf;
+extern cpuop_func_ce op_42d0_24_ff;
+extern cpuop_func_ce op_42d8_24_nf;
+extern cpuop_func_ce op_42d8_24_ff;
+extern cpuop_func_ce op_42e0_24_nf;
+extern cpuop_func_ce op_42e0_24_ff;
+extern cpuop_func_ce op_42e8_24_nf;
+extern cpuop_func_ce op_42e8_24_ff;
+extern cpuop_func_ce op_42f0_24_nf;
+extern cpuop_func_ce op_42f0_24_ff;
+extern cpuop_func_ce op_42f8_24_nf;
+extern cpuop_func_ce op_42f8_24_ff;
+extern cpuop_func_ce op_42f9_24_nf;
+extern cpuop_func_ce op_42f9_24_ff;
+extern cpuop_func_ce op_4400_24_nf;
+extern cpuop_func_ce op_4400_24_ff;
+extern cpuop_func_ce op_4410_24_nf;
+extern cpuop_func_ce op_4410_24_ff;
+extern cpuop_func_ce op_4418_24_nf;
+extern cpuop_func_ce op_4418_24_ff;
+extern cpuop_func_ce op_4420_24_nf;
+extern cpuop_func_ce op_4420_24_ff;
+extern cpuop_func_ce op_4428_24_nf;
+extern cpuop_func_ce op_4428_24_ff;
+extern cpuop_func_ce op_4430_24_nf;
+extern cpuop_func_ce op_4430_24_ff;
+extern cpuop_func_ce op_4438_24_nf;
+extern cpuop_func_ce op_4438_24_ff;
+extern cpuop_func_ce op_4439_24_nf;
+extern cpuop_func_ce op_4439_24_ff;
+extern cpuop_func_ce op_4440_24_nf;
+extern cpuop_func_ce op_4440_24_ff;
+extern cpuop_func_ce op_4450_24_nf;
+extern cpuop_func_ce op_4450_24_ff;
+extern cpuop_func_ce op_4458_24_nf;
+extern cpuop_func_ce op_4458_24_ff;
+extern cpuop_func_ce op_4460_24_nf;
+extern cpuop_func_ce op_4460_24_ff;
+extern cpuop_func_ce op_4468_24_nf;
+extern cpuop_func_ce op_4468_24_ff;
+extern cpuop_func_ce op_4470_24_nf;
+extern cpuop_func_ce op_4470_24_ff;
+extern cpuop_func_ce op_4478_24_nf;
+extern cpuop_func_ce op_4478_24_ff;
+extern cpuop_func_ce op_4479_24_nf;
+extern cpuop_func_ce op_4479_24_ff;
+extern cpuop_func_ce op_4480_24_nf;
+extern cpuop_func_ce op_4480_24_ff;
+extern cpuop_func_ce op_4490_24_nf;
+extern cpuop_func_ce op_4490_24_ff;
+extern cpuop_func_ce op_4498_24_nf;
+extern cpuop_func_ce op_4498_24_ff;
+extern cpuop_func_ce op_44a0_24_nf;
+extern cpuop_func_ce op_44a0_24_ff;
+extern cpuop_func_ce op_44a8_24_nf;
+extern cpuop_func_ce op_44a8_24_ff;
+extern cpuop_func_ce op_44b0_24_nf;
+extern cpuop_func_ce op_44b0_24_ff;
+extern cpuop_func_ce op_44b8_24_nf;
+extern cpuop_func_ce op_44b8_24_ff;
+extern cpuop_func_ce op_44b9_24_nf;
+extern cpuop_func_ce op_44b9_24_ff;
+extern cpuop_func_ce op_44c0_24_nf;
+extern cpuop_func_ce op_44c0_24_ff;
+extern cpuop_func_ce op_44d0_24_nf;
+extern cpuop_func_ce op_44d0_24_ff;
+extern cpuop_func_ce op_44d8_24_nf;
+extern cpuop_func_ce op_44d8_24_ff;
+extern cpuop_func_ce op_44e0_24_nf;
+extern cpuop_func_ce op_44e0_24_ff;
+extern cpuop_func_ce op_44e8_24_nf;
+extern cpuop_func_ce op_44e8_24_ff;
+extern cpuop_func_ce op_44f0_24_nf;
+extern cpuop_func_ce op_44f0_24_ff;
+extern cpuop_func_ce op_44f8_24_nf;
+extern cpuop_func_ce op_44f8_24_ff;
+extern cpuop_func_ce op_44f9_24_nf;
+extern cpuop_func_ce op_44f9_24_ff;
+extern cpuop_func_ce op_44fa_24_nf;
+extern cpuop_func_ce op_44fa_24_ff;
+extern cpuop_func_ce op_44fb_24_nf;
+extern cpuop_func_ce op_44fb_24_ff;
+extern cpuop_func_ce op_44fc_24_nf;
+extern cpuop_func_ce op_44fc_24_ff;
+extern cpuop_func_ce op_4600_24_nf;
+extern cpuop_func_ce op_4600_24_ff;
+extern cpuop_func_ce op_4610_24_nf;
+extern cpuop_func_ce op_4610_24_ff;
+extern cpuop_func_ce op_4618_24_nf;
+extern cpuop_func_ce op_4618_24_ff;
+extern cpuop_func_ce op_4620_24_nf;
+extern cpuop_func_ce op_4620_24_ff;
+extern cpuop_func_ce op_4628_24_nf;
+extern cpuop_func_ce op_4628_24_ff;
+extern cpuop_func_ce op_4630_24_nf;
+extern cpuop_func_ce op_4630_24_ff;
+extern cpuop_func_ce op_4638_24_nf;
+extern cpuop_func_ce op_4638_24_ff;
+extern cpuop_func_ce op_4639_24_nf;
+extern cpuop_func_ce op_4639_24_ff;
+extern cpuop_func_ce op_4640_24_nf;
+extern cpuop_func_ce op_4640_24_ff;
+extern cpuop_func_ce op_4650_24_nf;
+extern cpuop_func_ce op_4650_24_ff;
+extern cpuop_func_ce op_4658_24_nf;
+extern cpuop_func_ce op_4658_24_ff;
+extern cpuop_func_ce op_4660_24_nf;
+extern cpuop_func_ce op_4660_24_ff;
+extern cpuop_func_ce op_4668_24_nf;
+extern cpuop_func_ce op_4668_24_ff;
+extern cpuop_func_ce op_4670_24_nf;
+extern cpuop_func_ce op_4670_24_ff;
+extern cpuop_func_ce op_4678_24_nf;
+extern cpuop_func_ce op_4678_24_ff;
+extern cpuop_func_ce op_4679_24_nf;
+extern cpuop_func_ce op_4679_24_ff;
+extern cpuop_func_ce op_4680_24_nf;
+extern cpuop_func_ce op_4680_24_ff;
+extern cpuop_func_ce op_4690_24_nf;
+extern cpuop_func_ce op_4690_24_ff;
+extern cpuop_func_ce op_4698_24_nf;
+extern cpuop_func_ce op_4698_24_ff;
+extern cpuop_func_ce op_46a0_24_nf;
+extern cpuop_func_ce op_46a0_24_ff;
+extern cpuop_func_ce op_46a8_24_nf;
+extern cpuop_func_ce op_46a8_24_ff;
+extern cpuop_func_ce op_46b0_24_nf;
+extern cpuop_func_ce op_46b0_24_ff;
+extern cpuop_func_ce op_46b8_24_nf;
+extern cpuop_func_ce op_46b8_24_ff;
+extern cpuop_func_ce op_46b9_24_nf;
+extern cpuop_func_ce op_46b9_24_ff;
+extern cpuop_func_ce op_46c0_24_nf;
+extern cpuop_func_ce op_46c0_24_ff;
+extern cpuop_func_ce op_46d0_24_nf;
+extern cpuop_func_ce op_46d0_24_ff;
+extern cpuop_func_ce op_46d8_24_nf;
+extern cpuop_func_ce op_46d8_24_ff;
+extern cpuop_func_ce op_46e0_24_nf;
+extern cpuop_func_ce op_46e0_24_ff;
+extern cpuop_func_ce op_46e8_24_nf;
+extern cpuop_func_ce op_46e8_24_ff;
+extern cpuop_func_ce op_46f0_24_nf;
+extern cpuop_func_ce op_46f0_24_ff;
+extern cpuop_func_ce op_46f8_24_nf;
+extern cpuop_func_ce op_46f8_24_ff;
+extern cpuop_func_ce op_46f9_24_nf;
+extern cpuop_func_ce op_46f9_24_ff;
+extern cpuop_func_ce op_46fa_24_nf;
+extern cpuop_func_ce op_46fa_24_ff;
+extern cpuop_func_ce op_46fb_24_nf;
+extern cpuop_func_ce op_46fb_24_ff;
+extern cpuop_func_ce op_46fc_24_nf;
+extern cpuop_func_ce op_46fc_24_ff;
+extern cpuop_func_ce op_4800_24_nf;
+extern cpuop_func_ce op_4800_24_ff;
+extern cpuop_func_ce op_4808_24_nf;
+extern cpuop_func_ce op_4808_24_ff;
+extern cpuop_func_ce op_4810_24_nf;
+extern cpuop_func_ce op_4810_24_ff;
+extern cpuop_func_ce op_4818_24_nf;
+extern cpuop_func_ce op_4818_24_ff;
+extern cpuop_func_ce op_4820_24_nf;
+extern cpuop_func_ce op_4820_24_ff;
+extern cpuop_func_ce op_4828_24_nf;
+extern cpuop_func_ce op_4828_24_ff;
+extern cpuop_func_ce op_4830_24_nf;
+extern cpuop_func_ce op_4830_24_ff;
+extern cpuop_func_ce op_4838_24_nf;
+extern cpuop_func_ce op_4838_24_ff;
+extern cpuop_func_ce op_4839_24_nf;
+extern cpuop_func_ce op_4839_24_ff;
+extern cpuop_func_ce op_4840_24_nf;
+extern cpuop_func_ce op_4840_24_ff;
+extern cpuop_func_ce op_4848_24_nf;
+extern cpuop_func_ce op_4848_24_ff;
+extern cpuop_func_ce op_4850_24_nf;
+extern cpuop_func_ce op_4850_24_ff;
+extern cpuop_func_ce op_4868_24_nf;
+extern cpuop_func_ce op_4868_24_ff;
+extern cpuop_func_ce op_4870_24_nf;
+extern cpuop_func_ce op_4870_24_ff;
+extern cpuop_func_ce op_4878_24_nf;
+extern cpuop_func_ce op_4878_24_ff;
+extern cpuop_func_ce op_4879_24_nf;
+extern cpuop_func_ce op_4879_24_ff;
+extern cpuop_func_ce op_487a_24_nf;
+extern cpuop_func_ce op_487a_24_ff;
+extern cpuop_func_ce op_487b_24_nf;
+extern cpuop_func_ce op_487b_24_ff;
+extern cpuop_func_ce op_4880_24_nf;
+extern cpuop_func_ce op_4880_24_ff;
+extern cpuop_func_ce op_4890_24_nf;
+extern cpuop_func_ce op_4890_24_ff;
+extern cpuop_func_ce op_48a0_24_nf;
+extern cpuop_func_ce op_48a0_24_ff;
+extern cpuop_func_ce op_48a8_24_nf;
+extern cpuop_func_ce op_48a8_24_ff;
+extern cpuop_func_ce op_48b0_24_nf;
+extern cpuop_func_ce op_48b0_24_ff;
+extern cpuop_func_ce op_48b8_24_nf;
+extern cpuop_func_ce op_48b8_24_ff;
+extern cpuop_func_ce op_48b9_24_nf;
+extern cpuop_func_ce op_48b9_24_ff;
+extern cpuop_func_ce op_48c0_24_nf;
+extern cpuop_func_ce op_48c0_24_ff;
+extern cpuop_func_ce op_48d0_24_nf;
+extern cpuop_func_ce op_48d0_24_ff;
+extern cpuop_func_ce op_48e0_24_nf;
+extern cpuop_func_ce op_48e0_24_ff;
+extern cpuop_func_ce op_48e8_24_nf;
+extern cpuop_func_ce op_48e8_24_ff;
+extern cpuop_func_ce op_48f0_24_nf;
+extern cpuop_func_ce op_48f0_24_ff;
+extern cpuop_func_ce op_48f8_24_nf;
+extern cpuop_func_ce op_48f8_24_ff;
+extern cpuop_func_ce op_48f9_24_nf;
+extern cpuop_func_ce op_48f9_24_ff;
+extern cpuop_func_ce op_49c0_24_nf;
+extern cpuop_func_ce op_49c0_24_ff;
+extern cpuop_func_ce op_4a00_24_nf;
+extern cpuop_func_ce op_4a00_24_ff;
+extern cpuop_func_ce op_4a10_24_nf;
+extern cpuop_func_ce op_4a10_24_ff;
+extern cpuop_func_ce op_4a18_24_nf;
+extern cpuop_func_ce op_4a18_24_ff;
+extern cpuop_func_ce op_4a20_24_nf;
+extern cpuop_func_ce op_4a20_24_ff;
+extern cpuop_func_ce op_4a28_24_nf;
+extern cpuop_func_ce op_4a28_24_ff;
+extern cpuop_func_ce op_4a30_24_nf;
+extern cpuop_func_ce op_4a30_24_ff;
+extern cpuop_func_ce op_4a38_24_nf;
+extern cpuop_func_ce op_4a38_24_ff;
+extern cpuop_func_ce op_4a39_24_nf;
+extern cpuop_func_ce op_4a39_24_ff;
+extern cpuop_func_ce op_4a3a_24_nf;
+extern cpuop_func_ce op_4a3a_24_ff;
+extern cpuop_func_ce op_4a3b_24_nf;
+extern cpuop_func_ce op_4a3b_24_ff;
+extern cpuop_func_ce op_4a3c_24_nf;
+extern cpuop_func_ce op_4a3c_24_ff;
+extern cpuop_func_ce op_4a40_24_nf;
+extern cpuop_func_ce op_4a40_24_ff;
+extern cpuop_func_ce op_4a48_24_nf;
+extern cpuop_func_ce op_4a48_24_ff;
+extern cpuop_func_ce op_4a50_24_nf;
+extern cpuop_func_ce op_4a50_24_ff;
+extern cpuop_func_ce op_4a58_24_nf;
+extern cpuop_func_ce op_4a58_24_ff;
+extern cpuop_func_ce op_4a60_24_nf;
+extern cpuop_func_ce op_4a60_24_ff;
+extern cpuop_func_ce op_4a68_24_nf;
+extern cpuop_func_ce op_4a68_24_ff;
+extern cpuop_func_ce op_4a70_24_nf;
+extern cpuop_func_ce op_4a70_24_ff;
+extern cpuop_func_ce op_4a78_24_nf;
+extern cpuop_func_ce op_4a78_24_ff;
+extern cpuop_func_ce op_4a79_24_nf;
+extern cpuop_func_ce op_4a79_24_ff;
+extern cpuop_func_ce op_4a7a_24_nf;
+extern cpuop_func_ce op_4a7a_24_ff;
+extern cpuop_func_ce op_4a7b_24_nf;
+extern cpuop_func_ce op_4a7b_24_ff;
+extern cpuop_func_ce op_4a7c_24_nf;
+extern cpuop_func_ce op_4a7c_24_ff;
+extern cpuop_func_ce op_4a80_24_nf;
+extern cpuop_func_ce op_4a80_24_ff;
+extern cpuop_func_ce op_4a88_24_nf;
+extern cpuop_func_ce op_4a88_24_ff;
+extern cpuop_func_ce op_4a90_24_nf;
+extern cpuop_func_ce op_4a90_24_ff;
+extern cpuop_func_ce op_4a98_24_nf;
+extern cpuop_func_ce op_4a98_24_ff;
+extern cpuop_func_ce op_4aa0_24_nf;
+extern cpuop_func_ce op_4aa0_24_ff;
+extern cpuop_func_ce op_4aa8_24_nf;
+extern cpuop_func_ce op_4aa8_24_ff;
+extern cpuop_func_ce op_4ab0_24_nf;
+extern cpuop_func_ce op_4ab0_24_ff;
+extern cpuop_func_ce op_4ab8_24_nf;
+extern cpuop_func_ce op_4ab8_24_ff;
+extern cpuop_func_ce op_4ab9_24_nf;
+extern cpuop_func_ce op_4ab9_24_ff;
+extern cpuop_func_ce op_4aba_24_nf;
+extern cpuop_func_ce op_4aba_24_ff;
+extern cpuop_func_ce op_4abb_24_nf;
+extern cpuop_func_ce op_4abb_24_ff;
+extern cpuop_func_ce op_4abc_24_nf;
+extern cpuop_func_ce op_4abc_24_ff;
+extern cpuop_func_ce op_4ac0_24_nf;
+extern cpuop_func_ce op_4ac0_24_ff;
+extern cpuop_func_ce op_4ad0_24_nf;
+extern cpuop_func_ce op_4ad0_24_ff;
+extern cpuop_func_ce op_4ad8_24_nf;
+extern cpuop_func_ce op_4ad8_24_ff;
+extern cpuop_func_ce op_4ae0_24_nf;
+extern cpuop_func_ce op_4ae0_24_ff;
+extern cpuop_func_ce op_4ae8_24_nf;
+extern cpuop_func_ce op_4ae8_24_ff;
+extern cpuop_func_ce op_4af0_24_nf;
+extern cpuop_func_ce op_4af0_24_ff;
+extern cpuop_func_ce op_4af8_24_nf;
+extern cpuop_func_ce op_4af8_24_ff;
+extern cpuop_func_ce op_4af9_24_nf;
+extern cpuop_func_ce op_4af9_24_ff;
+extern cpuop_func_ce op_4c00_24_nf;
+extern cpuop_func_ce op_4c00_24_ff;
+extern cpuop_func_ce op_4c10_24_nf;
+extern cpuop_func_ce op_4c10_24_ff;
+extern cpuop_func_ce op_4c18_24_nf;
+extern cpuop_func_ce op_4c18_24_ff;
+extern cpuop_func_ce op_4c20_24_nf;
+extern cpuop_func_ce op_4c20_24_ff;
+extern cpuop_func_ce op_4c28_24_nf;
+extern cpuop_func_ce op_4c28_24_ff;
+extern cpuop_func_ce op_4c30_24_nf;
+extern cpuop_func_ce op_4c30_24_ff;
+extern cpuop_func_ce op_4c38_24_nf;
+extern cpuop_func_ce op_4c38_24_ff;
+extern cpuop_func_ce op_4c39_24_nf;
+extern cpuop_func_ce op_4c39_24_ff;
+extern cpuop_func_ce op_4c3a_24_nf;
+extern cpuop_func_ce op_4c3a_24_ff;
+extern cpuop_func_ce op_4c3b_24_nf;
+extern cpuop_func_ce op_4c3b_24_ff;
+extern cpuop_func_ce op_4c3c_24_nf;
+extern cpuop_func_ce op_4c3c_24_ff;
+extern cpuop_func_ce op_4c40_24_nf;
+extern cpuop_func_ce op_4c40_24_ff;
+extern cpuop_func_ce op_4c50_24_nf;
+extern cpuop_func_ce op_4c50_24_ff;
+extern cpuop_func_ce op_4c58_24_nf;
+extern cpuop_func_ce op_4c58_24_ff;
+extern cpuop_func_ce op_4c60_24_nf;
+extern cpuop_func_ce op_4c60_24_ff;
+extern cpuop_func_ce op_4c68_24_nf;
+extern cpuop_func_ce op_4c68_24_ff;
+extern cpuop_func_ce op_4c70_24_nf;
+extern cpuop_func_ce op_4c70_24_ff;
+extern cpuop_func_ce op_4c78_24_nf;
+extern cpuop_func_ce op_4c78_24_ff;
+extern cpuop_func_ce op_4c79_24_nf;
+extern cpuop_func_ce op_4c79_24_ff;
+extern cpuop_func_ce op_4c7a_24_nf;
+extern cpuop_func_ce op_4c7a_24_ff;
+extern cpuop_func_ce op_4c7b_24_nf;
+extern cpuop_func_ce op_4c7b_24_ff;
+extern cpuop_func_ce op_4c7c_24_nf;
+extern cpuop_func_ce op_4c7c_24_ff;
+extern cpuop_func_ce op_4c90_24_nf;
+extern cpuop_func_ce op_4c90_24_ff;
+extern cpuop_func_ce op_4c98_24_nf;
+extern cpuop_func_ce op_4c98_24_ff;
+extern cpuop_func_ce op_4ca8_24_nf;
+extern cpuop_func_ce op_4ca8_24_ff;
+extern cpuop_func_ce op_4cb0_24_nf;
+extern cpuop_func_ce op_4cb0_24_ff;
+extern cpuop_func_ce op_4cb8_24_nf;
+extern cpuop_func_ce op_4cb8_24_ff;
+extern cpuop_func_ce op_4cb9_24_nf;
+extern cpuop_func_ce op_4cb9_24_ff;
+extern cpuop_func_ce op_4cba_24_nf;
+extern cpuop_func_ce op_4cba_24_ff;
+extern cpuop_func_ce op_4cbb_24_nf;
+extern cpuop_func_ce op_4cbb_24_ff;
+extern cpuop_func_ce op_4cd0_24_nf;
+extern cpuop_func_ce op_4cd0_24_ff;
+extern cpuop_func_ce op_4cd8_24_nf;
+extern cpuop_func_ce op_4cd8_24_ff;
+extern cpuop_func_ce op_4ce8_24_nf;
+extern cpuop_func_ce op_4ce8_24_ff;
+extern cpuop_func_ce op_4cf0_24_nf;
+extern cpuop_func_ce op_4cf0_24_ff;
+extern cpuop_func_ce op_4cf8_24_nf;
+extern cpuop_func_ce op_4cf8_24_ff;
+extern cpuop_func_ce op_4cf9_24_nf;
+extern cpuop_func_ce op_4cf9_24_ff;
+extern cpuop_func_ce op_4cfa_24_nf;
+extern cpuop_func_ce op_4cfa_24_ff;
+extern cpuop_func_ce op_4cfb_24_nf;
+extern cpuop_func_ce op_4cfb_24_ff;
+extern cpuop_func_ce op_4e40_24_nf;
+extern cpuop_func_ce op_4e40_24_ff;
+extern cpuop_func_ce op_4e50_24_nf;
+extern cpuop_func_ce op_4e50_24_ff;
+extern cpuop_func_ce op_4e58_24_nf;
+extern cpuop_func_ce op_4e58_24_ff;
+extern cpuop_func_ce op_4e60_24_nf;
+extern cpuop_func_ce op_4e60_24_ff;
+extern cpuop_func_ce op_4e68_24_nf;
+extern cpuop_func_ce op_4e68_24_ff;
+extern cpuop_func_ce op_4e70_24_nf;
+extern cpuop_func_ce op_4e70_24_ff;
+extern cpuop_func_ce op_4e71_24_nf;
+extern cpuop_func_ce op_4e71_24_ff;
+extern cpuop_func_ce op_4e72_24_nf;
+extern cpuop_func_ce op_4e72_24_ff;
+extern cpuop_func_ce op_4e73_24_nf;
+extern cpuop_func_ce op_4e73_24_ff;
+extern cpuop_func_ce op_4e74_24_nf;
+extern cpuop_func_ce op_4e74_24_ff;
+extern cpuop_func_ce op_4e75_24_nf;
+extern cpuop_func_ce op_4e75_24_ff;
+extern cpuop_func_ce op_4e76_24_nf;
+extern cpuop_func_ce op_4e76_24_ff;
+extern cpuop_func_ce op_4e77_24_nf;
+extern cpuop_func_ce op_4e77_24_ff;
+extern cpuop_func_ce op_4e7a_24_nf;
+extern cpuop_func_ce op_4e7a_24_ff;
+extern cpuop_func_ce op_4e7b_24_nf;
+extern cpuop_func_ce op_4e7b_24_ff;
+extern cpuop_func_ce op_4e90_24_nf;
+extern cpuop_func_ce op_4e90_24_ff;
+extern cpuop_func_ce op_4ea8_24_nf;
+extern cpuop_func_ce op_4ea8_24_ff;
+extern cpuop_func_ce op_4eb0_24_nf;
+extern cpuop_func_ce op_4eb0_24_ff;
+extern cpuop_func_ce op_4eb8_24_nf;
+extern cpuop_func_ce op_4eb8_24_ff;
+extern cpuop_func_ce op_4eb9_24_nf;
+extern cpuop_func_ce op_4eb9_24_ff;
+extern cpuop_func_ce op_4eba_24_nf;
+extern cpuop_func_ce op_4eba_24_ff;
+extern cpuop_func_ce op_4ebb_24_nf;
+extern cpuop_func_ce op_4ebb_24_ff;
+extern cpuop_func_ce op_4ed0_24_nf;
+extern cpuop_func_ce op_4ed0_24_ff;
+extern cpuop_func_ce op_4ee8_24_nf;
+extern cpuop_func_ce op_4ee8_24_ff;
+extern cpuop_func_ce op_4ef0_24_nf;
+extern cpuop_func_ce op_4ef0_24_ff;
+extern cpuop_func_ce op_4ef8_24_nf;
+extern cpuop_func_ce op_4ef8_24_ff;
+extern cpuop_func_ce op_4ef9_24_nf;
+extern cpuop_func_ce op_4ef9_24_ff;
+extern cpuop_func_ce op_4efa_24_nf;
+extern cpuop_func_ce op_4efa_24_ff;
+extern cpuop_func_ce op_4efb_24_nf;
+extern cpuop_func_ce op_4efb_24_ff;
+extern cpuop_func_ce op_5000_24_nf;
+extern cpuop_func_ce op_5000_24_ff;
+extern cpuop_func_ce op_5010_24_nf;
+extern cpuop_func_ce op_5010_24_ff;
+extern cpuop_func_ce op_5018_24_nf;
+extern cpuop_func_ce op_5018_24_ff;
+extern cpuop_func_ce op_5020_24_nf;
+extern cpuop_func_ce op_5020_24_ff;
+extern cpuop_func_ce op_5028_24_nf;
+extern cpuop_func_ce op_5028_24_ff;
+extern cpuop_func_ce op_5030_24_nf;
+extern cpuop_func_ce op_5030_24_ff;
+extern cpuop_func_ce op_5038_24_nf;
+extern cpuop_func_ce op_5038_24_ff;
+extern cpuop_func_ce op_5039_24_nf;
+extern cpuop_func_ce op_5039_24_ff;
+extern cpuop_func_ce op_5040_24_nf;
+extern cpuop_func_ce op_5040_24_ff;
+extern cpuop_func_ce op_5048_24_nf;
+extern cpuop_func_ce op_5048_24_ff;
+extern cpuop_func_ce op_5050_24_nf;
+extern cpuop_func_ce op_5050_24_ff;
+extern cpuop_func_ce op_5058_24_nf;
+extern cpuop_func_ce op_5058_24_ff;
+extern cpuop_func_ce op_5060_24_nf;
+extern cpuop_func_ce op_5060_24_ff;
+extern cpuop_func_ce op_5068_24_nf;
+extern cpuop_func_ce op_5068_24_ff;
+extern cpuop_func_ce op_5070_24_nf;
+extern cpuop_func_ce op_5070_24_ff;
+extern cpuop_func_ce op_5078_24_nf;
+extern cpuop_func_ce op_5078_24_ff;
+extern cpuop_func_ce op_5079_24_nf;
+extern cpuop_func_ce op_5079_24_ff;
+extern cpuop_func_ce op_5080_24_nf;
+extern cpuop_func_ce op_5080_24_ff;
+extern cpuop_func_ce op_5088_24_nf;
+extern cpuop_func_ce op_5088_24_ff;
+extern cpuop_func_ce op_5090_24_nf;
+extern cpuop_func_ce op_5090_24_ff;
+extern cpuop_func_ce op_5098_24_nf;
+extern cpuop_func_ce op_5098_24_ff;
+extern cpuop_func_ce op_50a0_24_nf;
+extern cpuop_func_ce op_50a0_24_ff;
+extern cpuop_func_ce op_50a8_24_nf;
+extern cpuop_func_ce op_50a8_24_ff;
+extern cpuop_func_ce op_50b0_24_nf;
+extern cpuop_func_ce op_50b0_24_ff;
+extern cpuop_func_ce op_50b8_24_nf;
+extern cpuop_func_ce op_50b8_24_ff;
+extern cpuop_func_ce op_50b9_24_nf;
+extern cpuop_func_ce op_50b9_24_ff;
+extern cpuop_func_ce op_50c0_24_nf;
+extern cpuop_func_ce op_50c0_24_ff;
+extern cpuop_func_ce op_50c8_24_nf;
+extern cpuop_func_ce op_50c8_24_ff;
+extern cpuop_func_ce op_50d0_24_nf;
+extern cpuop_func_ce op_50d0_24_ff;
+extern cpuop_func_ce op_50d8_24_nf;
+extern cpuop_func_ce op_50d8_24_ff;
+extern cpuop_func_ce op_50e0_24_nf;
+extern cpuop_func_ce op_50e0_24_ff;
+extern cpuop_func_ce op_50e8_24_nf;
+extern cpuop_func_ce op_50e8_24_ff;
+extern cpuop_func_ce op_50f0_24_nf;
+extern cpuop_func_ce op_50f0_24_ff;
+extern cpuop_func_ce op_50f8_24_nf;
+extern cpuop_func_ce op_50f8_24_ff;
+extern cpuop_func_ce op_50f9_24_nf;
+extern cpuop_func_ce op_50f9_24_ff;
+extern cpuop_func_ce op_50fa_24_nf;
+extern cpuop_func_ce op_50fa_24_ff;
+extern cpuop_func_ce op_50fb_24_nf;
+extern cpuop_func_ce op_50fb_24_ff;
+extern cpuop_func_ce op_50fc_24_nf;
+extern cpuop_func_ce op_50fc_24_ff;
+extern cpuop_func_ce op_5100_24_nf;
+extern cpuop_func_ce op_5100_24_ff;
+extern cpuop_func_ce op_5110_24_nf;
+extern cpuop_func_ce op_5110_24_ff;
+extern cpuop_func_ce op_5118_24_nf;
+extern cpuop_func_ce op_5118_24_ff;
+extern cpuop_func_ce op_5120_24_nf;
+extern cpuop_func_ce op_5120_24_ff;
+extern cpuop_func_ce op_5128_24_nf;
+extern cpuop_func_ce op_5128_24_ff;
+extern cpuop_func_ce op_5130_24_nf;
+extern cpuop_func_ce op_5130_24_ff;
+extern cpuop_func_ce op_5138_24_nf;
+extern cpuop_func_ce op_5138_24_ff;
+extern cpuop_func_ce op_5139_24_nf;
+extern cpuop_func_ce op_5139_24_ff;
+extern cpuop_func_ce op_5140_24_nf;
+extern cpuop_func_ce op_5140_24_ff;
+extern cpuop_func_ce op_5148_24_nf;
+extern cpuop_func_ce op_5148_24_ff;
+extern cpuop_func_ce op_5150_24_nf;
+extern cpuop_func_ce op_5150_24_ff;
+extern cpuop_func_ce op_5158_24_nf;
+extern cpuop_func_ce op_5158_24_ff;
+extern cpuop_func_ce op_5160_24_nf;
+extern cpuop_func_ce op_5160_24_ff;
+extern cpuop_func_ce op_5168_24_nf;
+extern cpuop_func_ce op_5168_24_ff;
+extern cpuop_func_ce op_5170_24_nf;
+extern cpuop_func_ce op_5170_24_ff;
+extern cpuop_func_ce op_5178_24_nf;
+extern cpuop_func_ce op_5178_24_ff;
+extern cpuop_func_ce op_5179_24_nf;
+extern cpuop_func_ce op_5179_24_ff;
+extern cpuop_func_ce op_5180_24_nf;
+extern cpuop_func_ce op_5180_24_ff;
+extern cpuop_func_ce op_5188_24_nf;
+extern cpuop_func_ce op_5188_24_ff;
+extern cpuop_func_ce op_5190_24_nf;
+extern cpuop_func_ce op_5190_24_ff;
+extern cpuop_func_ce op_5198_24_nf;
+extern cpuop_func_ce op_5198_24_ff;
+extern cpuop_func_ce op_51a0_24_nf;
+extern cpuop_func_ce op_51a0_24_ff;
+extern cpuop_func_ce op_51a8_24_nf;
+extern cpuop_func_ce op_51a8_24_ff;
+extern cpuop_func_ce op_51b0_24_nf;
+extern cpuop_func_ce op_51b0_24_ff;
+extern cpuop_func_ce op_51b8_24_nf;
+extern cpuop_func_ce op_51b8_24_ff;
+extern cpuop_func_ce op_51b9_24_nf;
+extern cpuop_func_ce op_51b9_24_ff;
+extern cpuop_func_ce op_51c0_24_nf;
+extern cpuop_func_ce op_51c0_24_ff;
+extern cpuop_func_ce op_51c8_24_nf;
+extern cpuop_func_ce op_51c8_24_ff;
+extern cpuop_func_ce op_51d0_24_nf;
+extern cpuop_func_ce op_51d0_24_ff;
+extern cpuop_func_ce op_51d8_24_nf;
+extern cpuop_func_ce op_51d8_24_ff;
+extern cpuop_func_ce op_51e0_24_nf;
+extern cpuop_func_ce op_51e0_24_ff;
+extern cpuop_func_ce op_51e8_24_nf;
+extern cpuop_func_ce op_51e8_24_ff;
+extern cpuop_func_ce op_51f0_24_nf;
+extern cpuop_func_ce op_51f0_24_ff;
+extern cpuop_func_ce op_51f8_24_nf;
+extern cpuop_func_ce op_51f8_24_ff;
+extern cpuop_func_ce op_51f9_24_nf;
+extern cpuop_func_ce op_51f9_24_ff;
+extern cpuop_func_ce op_51fa_24_nf;
+extern cpuop_func_ce op_51fa_24_ff;
+extern cpuop_func_ce op_51fb_24_nf;
+extern cpuop_func_ce op_51fb_24_ff;
+extern cpuop_func_ce op_51fc_24_nf;
+extern cpuop_func_ce op_51fc_24_ff;
+extern cpuop_func_ce op_52c0_24_nf;
+extern cpuop_func_ce op_52c0_24_ff;
+extern cpuop_func_ce op_52c8_24_nf;
+extern cpuop_func_ce op_52c8_24_ff;
+extern cpuop_func_ce op_52d0_24_nf;
+extern cpuop_func_ce op_52d0_24_ff;
+extern cpuop_func_ce op_52d8_24_nf;
+extern cpuop_func_ce op_52d8_24_ff;
+extern cpuop_func_ce op_52e0_24_nf;
+extern cpuop_func_ce op_52e0_24_ff;
+extern cpuop_func_ce op_52e8_24_nf;
+extern cpuop_func_ce op_52e8_24_ff;
+extern cpuop_func_ce op_52f0_24_nf;
+extern cpuop_func_ce op_52f0_24_ff;
+extern cpuop_func_ce op_52f8_24_nf;
+extern cpuop_func_ce op_52f8_24_ff;
+extern cpuop_func_ce op_52f9_24_nf;
+extern cpuop_func_ce op_52f9_24_ff;
+extern cpuop_func_ce op_52fa_24_nf;
+extern cpuop_func_ce op_52fa_24_ff;
+extern cpuop_func_ce op_52fb_24_nf;
+extern cpuop_func_ce op_52fb_24_ff;
+extern cpuop_func_ce op_52fc_24_nf;
+extern cpuop_func_ce op_52fc_24_ff;
+extern cpuop_func_ce op_53c0_24_nf;
+extern cpuop_func_ce op_53c0_24_ff;
+extern cpuop_func_ce op_53c8_24_nf;
+extern cpuop_func_ce op_53c8_24_ff;
+extern cpuop_func_ce op_53d0_24_nf;
+extern cpuop_func_ce op_53d0_24_ff;
+extern cpuop_func_ce op_53d8_24_nf;
+extern cpuop_func_ce op_53d8_24_ff;
+extern cpuop_func_ce op_53e0_24_nf;
+extern cpuop_func_ce op_53e0_24_ff;
+extern cpuop_func_ce op_53e8_24_nf;
+extern cpuop_func_ce op_53e8_24_ff;
+extern cpuop_func_ce op_53f0_24_nf;
+extern cpuop_func_ce op_53f0_24_ff;
+extern cpuop_func_ce op_53f8_24_nf;
+extern cpuop_func_ce op_53f8_24_ff;
+extern cpuop_func_ce op_53f9_24_nf;
+extern cpuop_func_ce op_53f9_24_ff;
+extern cpuop_func_ce op_53fa_24_nf;
+extern cpuop_func_ce op_53fa_24_ff;
+extern cpuop_func_ce op_53fb_24_nf;
+extern cpuop_func_ce op_53fb_24_ff;
+extern cpuop_func_ce op_53fc_24_nf;
+extern cpuop_func_ce op_53fc_24_ff;
+extern cpuop_func_ce op_54c0_24_nf;
+extern cpuop_func_ce op_54c0_24_ff;
+extern cpuop_func_ce op_54c8_24_nf;
+extern cpuop_func_ce op_54c8_24_ff;
+extern cpuop_func_ce op_54d0_24_nf;
+extern cpuop_func_ce op_54d0_24_ff;
+extern cpuop_func_ce op_54d8_24_nf;
+extern cpuop_func_ce op_54d8_24_ff;
+extern cpuop_func_ce op_54e0_24_nf;
+extern cpuop_func_ce op_54e0_24_ff;
+extern cpuop_func_ce op_54e8_24_nf;
+extern cpuop_func_ce op_54e8_24_ff;
+extern cpuop_func_ce op_54f0_24_nf;
+extern cpuop_func_ce op_54f0_24_ff;
+extern cpuop_func_ce op_54f8_24_nf;
+extern cpuop_func_ce op_54f8_24_ff;
+extern cpuop_func_ce op_54f9_24_nf;
+extern cpuop_func_ce op_54f9_24_ff;
+extern cpuop_func_ce op_54fa_24_nf;
+extern cpuop_func_ce op_54fa_24_ff;
+extern cpuop_func_ce op_54fb_24_nf;
+extern cpuop_func_ce op_54fb_24_ff;
+extern cpuop_func_ce op_54fc_24_nf;
+extern cpuop_func_ce op_54fc_24_ff;
+extern cpuop_func_ce op_55c0_24_nf;
+extern cpuop_func_ce op_55c0_24_ff;
+extern cpuop_func_ce op_55c8_24_nf;
+extern cpuop_func_ce op_55c8_24_ff;
+extern cpuop_func_ce op_55d0_24_nf;
+extern cpuop_func_ce op_55d0_24_ff;
+extern cpuop_func_ce op_55d8_24_nf;
+extern cpuop_func_ce op_55d8_24_ff;
+extern cpuop_func_ce op_55e0_24_nf;
+extern cpuop_func_ce op_55e0_24_ff;
+extern cpuop_func_ce op_55e8_24_nf;
+extern cpuop_func_ce op_55e8_24_ff;
+extern cpuop_func_ce op_55f0_24_nf;
+extern cpuop_func_ce op_55f0_24_ff;
+extern cpuop_func_ce op_55f8_24_nf;
+extern cpuop_func_ce op_55f8_24_ff;
+extern cpuop_func_ce op_55f9_24_nf;
+extern cpuop_func_ce op_55f9_24_ff;
+extern cpuop_func_ce op_55fa_24_nf;
+extern cpuop_func_ce op_55fa_24_ff;
+extern cpuop_func_ce op_55fb_24_nf;
+extern cpuop_func_ce op_55fb_24_ff;
+extern cpuop_func_ce op_55fc_24_nf;
+extern cpuop_func_ce op_55fc_24_ff;
+extern cpuop_func_ce op_56c0_24_nf;
+extern cpuop_func_ce op_56c0_24_ff;
+extern cpuop_func_ce op_56c8_24_nf;
+extern cpuop_func_ce op_56c8_24_ff;
+extern cpuop_func_ce op_56d0_24_nf;
+extern cpuop_func_ce op_56d0_24_ff;
+extern cpuop_func_ce op_56d8_24_nf;
+extern cpuop_func_ce op_56d8_24_ff;
+extern cpuop_func_ce op_56e0_24_nf;
+extern cpuop_func_ce op_56e0_24_ff;
+extern cpuop_func_ce op_56e8_24_nf;
+extern cpuop_func_ce op_56e8_24_ff;
+extern cpuop_func_ce op_56f0_24_nf;
+extern cpuop_func_ce op_56f0_24_ff;
+extern cpuop_func_ce op_56f8_24_nf;
+extern cpuop_func_ce op_56f8_24_ff;
+extern cpuop_func_ce op_56f9_24_nf;
+extern cpuop_func_ce op_56f9_24_ff;
+extern cpuop_func_ce op_56fa_24_nf;
+extern cpuop_func_ce op_56fa_24_ff;
+extern cpuop_func_ce op_56fb_24_nf;
+extern cpuop_func_ce op_56fb_24_ff;
+extern cpuop_func_ce op_56fc_24_nf;
+extern cpuop_func_ce op_56fc_24_ff;
+extern cpuop_func_ce op_57c0_24_nf;
+extern cpuop_func_ce op_57c0_24_ff;
+extern cpuop_func_ce op_57c8_24_nf;
+extern cpuop_func_ce op_57c8_24_ff;
+extern cpuop_func_ce op_57d0_24_nf;
+extern cpuop_func_ce op_57d0_24_ff;
+extern cpuop_func_ce op_57d8_24_nf;
+extern cpuop_func_ce op_57d8_24_ff;
+extern cpuop_func_ce op_57e0_24_nf;
+extern cpuop_func_ce op_57e0_24_ff;
+extern cpuop_func_ce op_57e8_24_nf;
+extern cpuop_func_ce op_57e8_24_ff;
+extern cpuop_func_ce op_57f0_24_nf;
+extern cpuop_func_ce op_57f0_24_ff;
+extern cpuop_func_ce op_57f8_24_nf;
+extern cpuop_func_ce op_57f8_24_ff;
+extern cpuop_func_ce op_57f9_24_nf;
+extern cpuop_func_ce op_57f9_24_ff;
+extern cpuop_func_ce op_57fa_24_nf;
+extern cpuop_func_ce op_57fa_24_ff;
+extern cpuop_func_ce op_57fb_24_nf;
+extern cpuop_func_ce op_57fb_24_ff;
+extern cpuop_func_ce op_57fc_24_nf;
+extern cpuop_func_ce op_57fc_24_ff;
+extern cpuop_func_ce op_58c0_24_nf;
+extern cpuop_func_ce op_58c0_24_ff;
+extern cpuop_func_ce op_58c8_24_nf;
+extern cpuop_func_ce op_58c8_24_ff;
+extern cpuop_func_ce op_58d0_24_nf;
+extern cpuop_func_ce op_58d0_24_ff;
+extern cpuop_func_ce op_58d8_24_nf;
+extern cpuop_func_ce op_58d8_24_ff;
+extern cpuop_func_ce op_58e0_24_nf;
+extern cpuop_func_ce op_58e0_24_ff;
+extern cpuop_func_ce op_58e8_24_nf;
+extern cpuop_func_ce op_58e8_24_ff;
+extern cpuop_func_ce op_58f0_24_nf;
+extern cpuop_func_ce op_58f0_24_ff;
+extern cpuop_func_ce op_58f8_24_nf;
+extern cpuop_func_ce op_58f8_24_ff;
+extern cpuop_func_ce op_58f9_24_nf;
+extern cpuop_func_ce op_58f9_24_ff;
+extern cpuop_func_ce op_58fa_24_nf;
+extern cpuop_func_ce op_58fa_24_ff;
+extern cpuop_func_ce op_58fb_24_nf;
+extern cpuop_func_ce op_58fb_24_ff;
+extern cpuop_func_ce op_58fc_24_nf;
+extern cpuop_func_ce op_58fc_24_ff;
+extern cpuop_func_ce op_59c0_24_nf;
+extern cpuop_func_ce op_59c0_24_ff;
+extern cpuop_func_ce op_59c8_24_nf;
+extern cpuop_func_ce op_59c8_24_ff;
+extern cpuop_func_ce op_59d0_24_nf;
+extern cpuop_func_ce op_59d0_24_ff;
+extern cpuop_func_ce op_59d8_24_nf;
+extern cpuop_func_ce op_59d8_24_ff;
+extern cpuop_func_ce op_59e0_24_nf;
+extern cpuop_func_ce op_59e0_24_ff;
+extern cpuop_func_ce op_59e8_24_nf;
+extern cpuop_func_ce op_59e8_24_ff;
+extern cpuop_func_ce op_59f0_24_nf;
+extern cpuop_func_ce op_59f0_24_ff;
+extern cpuop_func_ce op_59f8_24_nf;
+extern cpuop_func_ce op_59f8_24_ff;
+extern cpuop_func_ce op_59f9_24_nf;
+extern cpuop_func_ce op_59f9_24_ff;
+extern cpuop_func_ce op_59fa_24_nf;
+extern cpuop_func_ce op_59fa_24_ff;
+extern cpuop_func_ce op_59fb_24_nf;
+extern cpuop_func_ce op_59fb_24_ff;
+extern cpuop_func_ce op_59fc_24_nf;
+extern cpuop_func_ce op_59fc_24_ff;
+extern cpuop_func_ce op_5ac0_24_nf;
+extern cpuop_func_ce op_5ac0_24_ff;
+extern cpuop_func_ce op_5ac8_24_nf;
+extern cpuop_func_ce op_5ac8_24_ff;
+extern cpuop_func_ce op_5ad0_24_nf;
+extern cpuop_func_ce op_5ad0_24_ff;
+extern cpuop_func_ce op_5ad8_24_nf;
+extern cpuop_func_ce op_5ad8_24_ff;
+extern cpuop_func_ce op_5ae0_24_nf;
+extern cpuop_func_ce op_5ae0_24_ff;
+extern cpuop_func_ce op_5ae8_24_nf;
+extern cpuop_func_ce op_5ae8_24_ff;
+extern cpuop_func_ce op_5af0_24_nf;
+extern cpuop_func_ce op_5af0_24_ff;
+extern cpuop_func_ce op_5af8_24_nf;
+extern cpuop_func_ce op_5af8_24_ff;
+extern cpuop_func_ce op_5af9_24_nf;
+extern cpuop_func_ce op_5af9_24_ff;
+extern cpuop_func_ce op_5afa_24_nf;
+extern cpuop_func_ce op_5afa_24_ff;
+extern cpuop_func_ce op_5afb_24_nf;
+extern cpuop_func_ce op_5afb_24_ff;
+extern cpuop_func_ce op_5afc_24_nf;
+extern cpuop_func_ce op_5afc_24_ff;
+extern cpuop_func_ce op_5bc0_24_nf;
+extern cpuop_func_ce op_5bc0_24_ff;
+extern cpuop_func_ce op_5bc8_24_nf;
+extern cpuop_func_ce op_5bc8_24_ff;
+extern cpuop_func_ce op_5bd0_24_nf;
+extern cpuop_func_ce op_5bd0_24_ff;
+extern cpuop_func_ce op_5bd8_24_nf;
+extern cpuop_func_ce op_5bd8_24_ff;
+extern cpuop_func_ce op_5be0_24_nf;
+extern cpuop_func_ce op_5be0_24_ff;
+extern cpuop_func_ce op_5be8_24_nf;
+extern cpuop_func_ce op_5be8_24_ff;
+extern cpuop_func_ce op_5bf0_24_nf;
+extern cpuop_func_ce op_5bf0_24_ff;
+extern cpuop_func_ce op_5bf8_24_nf;
+extern cpuop_func_ce op_5bf8_24_ff;
+extern cpuop_func_ce op_5bf9_24_nf;
+extern cpuop_func_ce op_5bf9_24_ff;
+extern cpuop_func_ce op_5bfa_24_nf;
+extern cpuop_func_ce op_5bfa_24_ff;
+extern cpuop_func_ce op_5bfb_24_nf;
+extern cpuop_func_ce op_5bfb_24_ff;
+extern cpuop_func_ce op_5bfc_24_nf;
+extern cpuop_func_ce op_5bfc_24_ff;
+extern cpuop_func_ce op_5cc0_24_nf;
+extern cpuop_func_ce op_5cc0_24_ff;
+extern cpuop_func_ce op_5cc8_24_nf;
+extern cpuop_func_ce op_5cc8_24_ff;
+extern cpuop_func_ce op_5cd0_24_nf;
+extern cpuop_func_ce op_5cd0_24_ff;
+extern cpuop_func_ce op_5cd8_24_nf;
+extern cpuop_func_ce op_5cd8_24_ff;
+extern cpuop_func_ce op_5ce0_24_nf;
+extern cpuop_func_ce op_5ce0_24_ff;
+extern cpuop_func_ce op_5ce8_24_nf;
+extern cpuop_func_ce op_5ce8_24_ff;
+extern cpuop_func_ce op_5cf0_24_nf;
+extern cpuop_func_ce op_5cf0_24_ff;
+extern cpuop_func_ce op_5cf8_24_nf;
+extern cpuop_func_ce op_5cf8_24_ff;
+extern cpuop_func_ce op_5cf9_24_nf;
+extern cpuop_func_ce op_5cf9_24_ff;
+extern cpuop_func_ce op_5cfa_24_nf;
+extern cpuop_func_ce op_5cfa_24_ff;
+extern cpuop_func_ce op_5cfb_24_nf;
+extern cpuop_func_ce op_5cfb_24_ff;
+extern cpuop_func_ce op_5cfc_24_nf;
+extern cpuop_func_ce op_5cfc_24_ff;
+extern cpuop_func_ce op_5dc0_24_nf;
+extern cpuop_func_ce op_5dc0_24_ff;
+extern cpuop_func_ce op_5dc8_24_nf;
+extern cpuop_func_ce op_5dc8_24_ff;
+extern cpuop_func_ce op_5dd0_24_nf;
+extern cpuop_func_ce op_5dd0_24_ff;
+extern cpuop_func_ce op_5dd8_24_nf;
+extern cpuop_func_ce op_5dd8_24_ff;
+extern cpuop_func_ce op_5de0_24_nf;
+extern cpuop_func_ce op_5de0_24_ff;
+extern cpuop_func_ce op_5de8_24_nf;
+extern cpuop_func_ce op_5de8_24_ff;
+extern cpuop_func_ce op_5df0_24_nf;
+extern cpuop_func_ce op_5df0_24_ff;
+extern cpuop_func_ce op_5df8_24_nf;
+extern cpuop_func_ce op_5df8_24_ff;
+extern cpuop_func_ce op_5df9_24_nf;
+extern cpuop_func_ce op_5df9_24_ff;
+extern cpuop_func_ce op_5dfa_24_nf;
+extern cpuop_func_ce op_5dfa_24_ff;
+extern cpuop_func_ce op_5dfb_24_nf;
+extern cpuop_func_ce op_5dfb_24_ff;
+extern cpuop_func_ce op_5dfc_24_nf;
+extern cpuop_func_ce op_5dfc_24_ff;
+extern cpuop_func_ce op_5ec0_24_nf;
+extern cpuop_func_ce op_5ec0_24_ff;
+extern cpuop_func_ce op_5ec8_24_nf;
+extern cpuop_func_ce op_5ec8_24_ff;
+extern cpuop_func_ce op_5ed0_24_nf;
+extern cpuop_func_ce op_5ed0_24_ff;
+extern cpuop_func_ce op_5ed8_24_nf;
+extern cpuop_func_ce op_5ed8_24_ff;
+extern cpuop_func_ce op_5ee0_24_nf;
+extern cpuop_func_ce op_5ee0_24_ff;
+extern cpuop_func_ce op_5ee8_24_nf;
+extern cpuop_func_ce op_5ee8_24_ff;
+extern cpuop_func_ce op_5ef0_24_nf;
+extern cpuop_func_ce op_5ef0_24_ff;
+extern cpuop_func_ce op_5ef8_24_nf;
+extern cpuop_func_ce op_5ef8_24_ff;
+extern cpuop_func_ce op_5ef9_24_nf;
+extern cpuop_func_ce op_5ef9_24_ff;
+extern cpuop_func_ce op_5efa_24_nf;
+extern cpuop_func_ce op_5efa_24_ff;
+extern cpuop_func_ce op_5efb_24_nf;
+extern cpuop_func_ce op_5efb_24_ff;
+extern cpuop_func_ce op_5efc_24_nf;
+extern cpuop_func_ce op_5efc_24_ff;
+extern cpuop_func_ce op_5fc0_24_nf;
+extern cpuop_func_ce op_5fc0_24_ff;
+extern cpuop_func_ce op_5fc8_24_nf;
+extern cpuop_func_ce op_5fc8_24_ff;
+extern cpuop_func_ce op_5fd0_24_nf;
+extern cpuop_func_ce op_5fd0_24_ff;
+extern cpuop_func_ce op_5fd8_24_nf;
+extern cpuop_func_ce op_5fd8_24_ff;
+extern cpuop_func_ce op_5fe0_24_nf;
+extern cpuop_func_ce op_5fe0_24_ff;
+extern cpuop_func_ce op_5fe8_24_nf;
+extern cpuop_func_ce op_5fe8_24_ff;
+extern cpuop_func_ce op_5ff0_24_nf;
+extern cpuop_func_ce op_5ff0_24_ff;
+extern cpuop_func_ce op_5ff8_24_nf;
+extern cpuop_func_ce op_5ff8_24_ff;
+extern cpuop_func_ce op_5ff9_24_nf;
+extern cpuop_func_ce op_5ff9_24_ff;
+extern cpuop_func_ce op_5ffa_24_nf;
+extern cpuop_func_ce op_5ffa_24_ff;
+extern cpuop_func_ce op_5ffb_24_nf;
+extern cpuop_func_ce op_5ffb_24_ff;
+extern cpuop_func_ce op_5ffc_24_nf;
+extern cpuop_func_ce op_5ffc_24_ff;
+extern cpuop_func_ce op_6000_24_nf;
+extern cpuop_func_ce op_6000_24_ff;
+extern cpuop_func_ce op_6001_24_nf;
+extern cpuop_func_ce op_6001_24_ff;
+extern cpuop_func_ce op_60ff_24_nf;
+extern cpuop_func_ce op_60ff_24_ff;
+extern cpuop_func_ce op_6100_24_nf;
+extern cpuop_func_ce op_6100_24_ff;
+extern cpuop_func_ce op_6101_24_nf;
+extern cpuop_func_ce op_6101_24_ff;
+extern cpuop_func_ce op_61ff_24_nf;
+extern cpuop_func_ce op_61ff_24_ff;
+extern cpuop_func_ce op_6200_24_nf;
+extern cpuop_func_ce op_6200_24_ff;
+extern cpuop_func_ce op_6201_24_nf;
+extern cpuop_func_ce op_6201_24_ff;
+extern cpuop_func_ce op_62ff_24_nf;
+extern cpuop_func_ce op_62ff_24_ff;
+extern cpuop_func_ce op_6300_24_nf;
+extern cpuop_func_ce op_6300_24_ff;
+extern cpuop_func_ce op_6301_24_nf;
+extern cpuop_func_ce op_6301_24_ff;
+extern cpuop_func_ce op_63ff_24_nf;
+extern cpuop_func_ce op_63ff_24_ff;
+extern cpuop_func_ce op_6400_24_nf;
+extern cpuop_func_ce op_6400_24_ff;
+extern cpuop_func_ce op_6401_24_nf;
+extern cpuop_func_ce op_6401_24_ff;
+extern cpuop_func_ce op_64ff_24_nf;
+extern cpuop_func_ce op_64ff_24_ff;
+extern cpuop_func_ce op_6500_24_nf;
+extern cpuop_func_ce op_6500_24_ff;
+extern cpuop_func_ce op_6501_24_nf;
+extern cpuop_func_ce op_6501_24_ff;
+extern cpuop_func_ce op_65ff_24_nf;
+extern cpuop_func_ce op_65ff_24_ff;
+extern cpuop_func_ce op_6600_24_nf;
+extern cpuop_func_ce op_6600_24_ff;
+extern cpuop_func_ce op_6601_24_nf;
+extern cpuop_func_ce op_6601_24_ff;
+extern cpuop_func_ce op_66ff_24_nf;
+extern cpuop_func_ce op_66ff_24_ff;
+extern cpuop_func_ce op_6700_24_nf;
+extern cpuop_func_ce op_6700_24_ff;
+extern cpuop_func_ce op_6701_24_nf;
+extern cpuop_func_ce op_6701_24_ff;
+extern cpuop_func_ce op_67ff_24_nf;
+extern cpuop_func_ce op_67ff_24_ff;
+extern cpuop_func_ce op_6800_24_nf;
+extern cpuop_func_ce op_6800_24_ff;
+extern cpuop_func_ce op_6801_24_nf;
+extern cpuop_func_ce op_6801_24_ff;
+extern cpuop_func_ce op_68ff_24_nf;
+extern cpuop_func_ce op_68ff_24_ff;
+extern cpuop_func_ce op_6900_24_nf;
+extern cpuop_func_ce op_6900_24_ff;
+extern cpuop_func_ce op_6901_24_nf;
+extern cpuop_func_ce op_6901_24_ff;
+extern cpuop_func_ce op_69ff_24_nf;
+extern cpuop_func_ce op_69ff_24_ff;
+extern cpuop_func_ce op_6a00_24_nf;
+extern cpuop_func_ce op_6a00_24_ff;
+extern cpuop_func_ce op_6a01_24_nf;
+extern cpuop_func_ce op_6a01_24_ff;
+extern cpuop_func_ce op_6aff_24_nf;
+extern cpuop_func_ce op_6aff_24_ff;
+extern cpuop_func_ce op_6b00_24_nf;
+extern cpuop_func_ce op_6b00_24_ff;
+extern cpuop_func_ce op_6b01_24_nf;
+extern cpuop_func_ce op_6b01_24_ff;
+extern cpuop_func_ce op_6bff_24_nf;
+extern cpuop_func_ce op_6bff_24_ff;
+extern cpuop_func_ce op_6c00_24_nf;
+extern cpuop_func_ce op_6c00_24_ff;
+extern cpuop_func_ce op_6c01_24_nf;
+extern cpuop_func_ce op_6c01_24_ff;
+extern cpuop_func_ce op_6cff_24_nf;
+extern cpuop_func_ce op_6cff_24_ff;
+extern cpuop_func_ce op_6d00_24_nf;
+extern cpuop_func_ce op_6d00_24_ff;
+extern cpuop_func_ce op_6d01_24_nf;
+extern cpuop_func_ce op_6d01_24_ff;
+extern cpuop_func_ce op_6dff_24_nf;
+extern cpuop_func_ce op_6dff_24_ff;
+extern cpuop_func_ce op_6e00_24_nf;
+extern cpuop_func_ce op_6e00_24_ff;
+extern cpuop_func_ce op_6e01_24_nf;
+extern cpuop_func_ce op_6e01_24_ff;
+extern cpuop_func_ce op_6eff_24_nf;
+extern cpuop_func_ce op_6eff_24_ff;
+extern cpuop_func_ce op_6f00_24_nf;
+extern cpuop_func_ce op_6f00_24_ff;
+extern cpuop_func_ce op_6f01_24_nf;
+extern cpuop_func_ce op_6f01_24_ff;
+extern cpuop_func_ce op_6fff_24_nf;
+extern cpuop_func_ce op_6fff_24_ff;
+extern cpuop_func_ce op_7000_24_nf;
+extern cpuop_func_ce op_7000_24_ff;
+extern cpuop_func_ce op_8000_24_nf;
+extern cpuop_func_ce op_8000_24_ff;
+extern cpuop_func_ce op_8010_24_nf;
+extern cpuop_func_ce op_8010_24_ff;
+extern cpuop_func_ce op_8018_24_nf;
+extern cpuop_func_ce op_8018_24_ff;
+extern cpuop_func_ce op_8020_24_nf;
+extern cpuop_func_ce op_8020_24_ff;
+extern cpuop_func_ce op_8028_24_nf;
+extern cpuop_func_ce op_8028_24_ff;
+extern cpuop_func_ce op_8030_24_nf;
+extern cpuop_func_ce op_8030_24_ff;
+extern cpuop_func_ce op_8038_24_nf;
+extern cpuop_func_ce op_8038_24_ff;
+extern cpuop_func_ce op_8039_24_nf;
+extern cpuop_func_ce op_8039_24_ff;
+extern cpuop_func_ce op_803a_24_nf;
+extern cpuop_func_ce op_803a_24_ff;
+extern cpuop_func_ce op_803b_24_nf;
+extern cpuop_func_ce op_803b_24_ff;
+extern cpuop_func_ce op_803c_24_nf;
+extern cpuop_func_ce op_803c_24_ff;
+extern cpuop_func_ce op_8040_24_nf;
+extern cpuop_func_ce op_8040_24_ff;
+extern cpuop_func_ce op_8050_24_nf;
+extern cpuop_func_ce op_8050_24_ff;
+extern cpuop_func_ce op_8058_24_nf;
+extern cpuop_func_ce op_8058_24_ff;
+extern cpuop_func_ce op_8060_24_nf;
+extern cpuop_func_ce op_8060_24_ff;
+extern cpuop_func_ce op_8068_24_nf;
+extern cpuop_func_ce op_8068_24_ff;
+extern cpuop_func_ce op_8070_24_nf;
+extern cpuop_func_ce op_8070_24_ff;
+extern cpuop_func_ce op_8078_24_nf;
+extern cpuop_func_ce op_8078_24_ff;
+extern cpuop_func_ce op_8079_24_nf;
+extern cpuop_func_ce op_8079_24_ff;
+extern cpuop_func_ce op_807a_24_nf;
+extern cpuop_func_ce op_807a_24_ff;
+extern cpuop_func_ce op_807b_24_nf;
+extern cpuop_func_ce op_807b_24_ff;
+extern cpuop_func_ce op_807c_24_nf;
+extern cpuop_func_ce op_807c_24_ff;
+extern cpuop_func_ce op_8080_24_nf;
+extern cpuop_func_ce op_8080_24_ff;
+extern cpuop_func_ce op_8090_24_nf;
+extern cpuop_func_ce op_8090_24_ff;
+extern cpuop_func_ce op_8098_24_nf;
+extern cpuop_func_ce op_8098_24_ff;
+extern cpuop_func_ce op_80a0_24_nf;
+extern cpuop_func_ce op_80a0_24_ff;
+extern cpuop_func_ce op_80a8_24_nf;
+extern cpuop_func_ce op_80a8_24_ff;
+extern cpuop_func_ce op_80b0_24_nf;
+extern cpuop_func_ce op_80b0_24_ff;
+extern cpuop_func_ce op_80b8_24_nf;
+extern cpuop_func_ce op_80b8_24_ff;
+extern cpuop_func_ce op_80b9_24_nf;
+extern cpuop_func_ce op_80b9_24_ff;
+extern cpuop_func_ce op_80ba_24_nf;
+extern cpuop_func_ce op_80ba_24_ff;
+extern cpuop_func_ce op_80bb_24_nf;
+extern cpuop_func_ce op_80bb_24_ff;
+extern cpuop_func_ce op_80bc_24_nf;
+extern cpuop_func_ce op_80bc_24_ff;
+extern cpuop_func_ce op_80c0_24_nf;
+extern cpuop_func_ce op_80c0_24_ff;
+extern cpuop_func_ce op_80d0_24_nf;
+extern cpuop_func_ce op_80d0_24_ff;
+extern cpuop_func_ce op_80d8_24_nf;
+extern cpuop_func_ce op_80d8_24_ff;
+extern cpuop_func_ce op_80e0_24_nf;
+extern cpuop_func_ce op_80e0_24_ff;
+extern cpuop_func_ce op_80e8_24_nf;
+extern cpuop_func_ce op_80e8_24_ff;
+extern cpuop_func_ce op_80f0_24_nf;
+extern cpuop_func_ce op_80f0_24_ff;
+extern cpuop_func_ce op_80f8_24_nf;
+extern cpuop_func_ce op_80f8_24_ff;
+extern cpuop_func_ce op_80f9_24_nf;
+extern cpuop_func_ce op_80f9_24_ff;
+extern cpuop_func_ce op_80fa_24_nf;
+extern cpuop_func_ce op_80fa_24_ff;
+extern cpuop_func_ce op_80fb_24_nf;
+extern cpuop_func_ce op_80fb_24_ff;
+extern cpuop_func_ce op_80fc_24_nf;
+extern cpuop_func_ce op_80fc_24_ff;
+extern cpuop_func_ce op_8100_24_nf;
+extern cpuop_func_ce op_8100_24_ff;
+extern cpuop_func_ce op_8108_24_nf;
+extern cpuop_func_ce op_8108_24_ff;
+extern cpuop_func_ce op_8110_24_nf;
+extern cpuop_func_ce op_8110_24_ff;
+extern cpuop_func_ce op_8118_24_nf;
+extern cpuop_func_ce op_8118_24_ff;
+extern cpuop_func_ce op_8120_24_nf;
+extern cpuop_func_ce op_8120_24_ff;
+extern cpuop_func_ce op_8128_24_nf;
+extern cpuop_func_ce op_8128_24_ff;
+extern cpuop_func_ce op_8130_24_nf;
+extern cpuop_func_ce op_8130_24_ff;
+extern cpuop_func_ce op_8138_24_nf;
+extern cpuop_func_ce op_8138_24_ff;
+extern cpuop_func_ce op_8139_24_nf;
+extern cpuop_func_ce op_8139_24_ff;
+extern cpuop_func_ce op_8140_24_nf;
+extern cpuop_func_ce op_8140_24_ff;
+extern cpuop_func_ce op_8148_24_nf;
+extern cpuop_func_ce op_8148_24_ff;
+extern cpuop_func_ce op_8150_24_nf;
+extern cpuop_func_ce op_8150_24_ff;
+extern cpuop_func_ce op_8158_24_nf;
+extern cpuop_func_ce op_8158_24_ff;
+extern cpuop_func_ce op_8160_24_nf;
+extern cpuop_func_ce op_8160_24_ff;
+extern cpuop_func_ce op_8168_24_nf;
+extern cpuop_func_ce op_8168_24_ff;
+extern cpuop_func_ce op_8170_24_nf;
+extern cpuop_func_ce op_8170_24_ff;
+extern cpuop_func_ce op_8178_24_nf;
+extern cpuop_func_ce op_8178_24_ff;
+extern cpuop_func_ce op_8179_24_nf;
+extern cpuop_func_ce op_8179_24_ff;
+extern cpuop_func_ce op_8180_24_nf;
+extern cpuop_func_ce op_8180_24_ff;
+extern cpuop_func_ce op_8188_24_nf;
+extern cpuop_func_ce op_8188_24_ff;
+extern cpuop_func_ce op_8190_24_nf;
+extern cpuop_func_ce op_8190_24_ff;
+extern cpuop_func_ce op_8198_24_nf;
+extern cpuop_func_ce op_8198_24_ff;
+extern cpuop_func_ce op_81a0_24_nf;
+extern cpuop_func_ce op_81a0_24_ff;
+extern cpuop_func_ce op_81a8_24_nf;
+extern cpuop_func_ce op_81a8_24_ff;
+extern cpuop_func_ce op_81b0_24_nf;
+extern cpuop_func_ce op_81b0_24_ff;
+extern cpuop_func_ce op_81b8_24_nf;
+extern cpuop_func_ce op_81b8_24_ff;
+extern cpuop_func_ce op_81b9_24_nf;
+extern cpuop_func_ce op_81b9_24_ff;
+extern cpuop_func_ce op_81c0_24_nf;
+extern cpuop_func_ce op_81c0_24_ff;
+extern cpuop_func_ce op_81d0_24_nf;
+extern cpuop_func_ce op_81d0_24_ff;
+extern cpuop_func_ce op_81d8_24_nf;
+extern cpuop_func_ce op_81d8_24_ff;
+extern cpuop_func_ce op_81e0_24_nf;
+extern cpuop_func_ce op_81e0_24_ff;
+extern cpuop_func_ce op_81e8_24_nf;
+extern cpuop_func_ce op_81e8_24_ff;
+extern cpuop_func_ce op_81f0_24_nf;
+extern cpuop_func_ce op_81f0_24_ff;
+extern cpuop_func_ce op_81f8_24_nf;
+extern cpuop_func_ce op_81f8_24_ff;
+extern cpuop_func_ce op_81f9_24_nf;
+extern cpuop_func_ce op_81f9_24_ff;
+extern cpuop_func_ce op_81fa_24_nf;
+extern cpuop_func_ce op_81fa_24_ff;
+extern cpuop_func_ce op_81fb_24_nf;
+extern cpuop_func_ce op_81fb_24_ff;
+extern cpuop_func_ce op_81fc_24_nf;
+extern cpuop_func_ce op_81fc_24_ff;
+extern cpuop_func_ce op_9000_24_nf;
+extern cpuop_func_ce op_9000_24_ff;
+extern cpuop_func_ce op_9010_24_nf;
+extern cpuop_func_ce op_9010_24_ff;
+extern cpuop_func_ce op_9018_24_nf;
+extern cpuop_func_ce op_9018_24_ff;
+extern cpuop_func_ce op_9020_24_nf;
+extern cpuop_func_ce op_9020_24_ff;
+extern cpuop_func_ce op_9028_24_nf;
+extern cpuop_func_ce op_9028_24_ff;
+extern cpuop_func_ce op_9030_24_nf;
+extern cpuop_func_ce op_9030_24_ff;
+extern cpuop_func_ce op_9038_24_nf;
+extern cpuop_func_ce op_9038_24_ff;
+extern cpuop_func_ce op_9039_24_nf;
+extern cpuop_func_ce op_9039_24_ff;
+extern cpuop_func_ce op_903a_24_nf;
+extern cpuop_func_ce op_903a_24_ff;
+extern cpuop_func_ce op_903b_24_nf;
+extern cpuop_func_ce op_903b_24_ff;
+extern cpuop_func_ce op_903c_24_nf;
+extern cpuop_func_ce op_903c_24_ff;
+extern cpuop_func_ce op_9040_24_nf;
+extern cpuop_func_ce op_9040_24_ff;
+extern cpuop_func_ce op_9048_24_nf;
+extern cpuop_func_ce op_9048_24_ff;
+extern cpuop_func_ce op_9050_24_nf;
+extern cpuop_func_ce op_9050_24_ff;
+extern cpuop_func_ce op_9058_24_nf;
+extern cpuop_func_ce op_9058_24_ff;
+extern cpuop_func_ce op_9060_24_nf;
+extern cpuop_func_ce op_9060_24_ff;
+extern cpuop_func_ce op_9068_24_nf;
+extern cpuop_func_ce op_9068_24_ff;
+extern cpuop_func_ce op_9070_24_nf;
+extern cpuop_func_ce op_9070_24_ff;
+extern cpuop_func_ce op_9078_24_nf;
+extern cpuop_func_ce op_9078_24_ff;
+extern cpuop_func_ce op_9079_24_nf;
+extern cpuop_func_ce op_9079_24_ff;
+extern cpuop_func_ce op_907a_24_nf;
+extern cpuop_func_ce op_907a_24_ff;
+extern cpuop_func_ce op_907b_24_nf;
+extern cpuop_func_ce op_907b_24_ff;
+extern cpuop_func_ce op_907c_24_nf;
+extern cpuop_func_ce op_907c_24_ff;
+extern cpuop_func_ce op_9080_24_nf;
+extern cpuop_func_ce op_9080_24_ff;
+extern cpuop_func_ce op_9088_24_nf;
+extern cpuop_func_ce op_9088_24_ff;
+extern cpuop_func_ce op_9090_24_nf;
+extern cpuop_func_ce op_9090_24_ff;
+extern cpuop_func_ce op_9098_24_nf;
+extern cpuop_func_ce op_9098_24_ff;
+extern cpuop_func_ce op_90a0_24_nf;
+extern cpuop_func_ce op_90a0_24_ff;
+extern cpuop_func_ce op_90a8_24_nf;
+extern cpuop_func_ce op_90a8_24_ff;
+extern cpuop_func_ce op_90b0_24_nf;
+extern cpuop_func_ce op_90b0_24_ff;
+extern cpuop_func_ce op_90b8_24_nf;
+extern cpuop_func_ce op_90b8_24_ff;
+extern cpuop_func_ce op_90b9_24_nf;
+extern cpuop_func_ce op_90b9_24_ff;
+extern cpuop_func_ce op_90ba_24_nf;
+extern cpuop_func_ce op_90ba_24_ff;
+extern cpuop_func_ce op_90bb_24_nf;
+extern cpuop_func_ce op_90bb_24_ff;
+extern cpuop_func_ce op_90bc_24_nf;
+extern cpuop_func_ce op_90bc_24_ff;
+extern cpuop_func_ce op_90c0_24_nf;
+extern cpuop_func_ce op_90c0_24_ff;
+extern cpuop_func_ce op_90c8_24_nf;
+extern cpuop_func_ce op_90c8_24_ff;
+extern cpuop_func_ce op_90d0_24_nf;
+extern cpuop_func_ce op_90d0_24_ff;
+extern cpuop_func_ce op_90d8_24_nf;
+extern cpuop_func_ce op_90d8_24_ff;
+extern cpuop_func_ce op_90e0_24_nf;
+extern cpuop_func_ce op_90e0_24_ff;
+extern cpuop_func_ce op_90e8_24_nf;
+extern cpuop_func_ce op_90e8_24_ff;
+extern cpuop_func_ce op_90f0_24_nf;
+extern cpuop_func_ce op_90f0_24_ff;
+extern cpuop_func_ce op_90f8_24_nf;
+extern cpuop_func_ce op_90f8_24_ff;
+extern cpuop_func_ce op_90f9_24_nf;
+extern cpuop_func_ce op_90f9_24_ff;
+extern cpuop_func_ce op_90fa_24_nf;
+extern cpuop_func_ce op_90fa_24_ff;
+extern cpuop_func_ce op_90fb_24_nf;
+extern cpuop_func_ce op_90fb_24_ff;
+extern cpuop_func_ce op_90fc_24_nf;
+extern cpuop_func_ce op_90fc_24_ff;
+extern cpuop_func_ce op_9100_24_nf;
+extern cpuop_func_ce op_9100_24_ff;
+extern cpuop_func_ce op_9108_24_nf;
+extern cpuop_func_ce op_9108_24_ff;
+extern cpuop_func_ce op_9110_24_nf;
+extern cpuop_func_ce op_9110_24_ff;
+extern cpuop_func_ce op_9118_24_nf;
+extern cpuop_func_ce op_9118_24_ff;
+extern cpuop_func_ce op_9120_24_nf;
+extern cpuop_func_ce op_9120_24_ff;
+extern cpuop_func_ce op_9128_24_nf;
+extern cpuop_func_ce op_9128_24_ff;
+extern cpuop_func_ce op_9130_24_nf;
+extern cpuop_func_ce op_9130_24_ff;
+extern cpuop_func_ce op_9138_24_nf;
+extern cpuop_func_ce op_9138_24_ff;
+extern cpuop_func_ce op_9139_24_nf;
+extern cpuop_func_ce op_9139_24_ff;
+extern cpuop_func_ce op_9140_24_nf;
+extern cpuop_func_ce op_9140_24_ff;
+extern cpuop_func_ce op_9148_24_nf;
+extern cpuop_func_ce op_9148_24_ff;
+extern cpuop_func_ce op_9150_24_nf;
+extern cpuop_func_ce op_9150_24_ff;
+extern cpuop_func_ce op_9158_24_nf;
+extern cpuop_func_ce op_9158_24_ff;
+extern cpuop_func_ce op_9160_24_nf;
+extern cpuop_func_ce op_9160_24_ff;
+extern cpuop_func_ce op_9168_24_nf;
+extern cpuop_func_ce op_9168_24_ff;
+extern cpuop_func_ce op_9170_24_nf;
+extern cpuop_func_ce op_9170_24_ff;
+extern cpuop_func_ce op_9178_24_nf;
+extern cpuop_func_ce op_9178_24_ff;
+extern cpuop_func_ce op_9179_24_nf;
+extern cpuop_func_ce op_9179_24_ff;
+extern cpuop_func_ce op_9180_24_nf;
+extern cpuop_func_ce op_9180_24_ff;
+extern cpuop_func_ce op_9188_24_nf;
+extern cpuop_func_ce op_9188_24_ff;
+extern cpuop_func_ce op_9190_24_nf;
+extern cpuop_func_ce op_9190_24_ff;
+extern cpuop_func_ce op_9198_24_nf;
+extern cpuop_func_ce op_9198_24_ff;
+extern cpuop_func_ce op_91a0_24_nf;
+extern cpuop_func_ce op_91a0_24_ff;
+extern cpuop_func_ce op_91a8_24_nf;
+extern cpuop_func_ce op_91a8_24_ff;
+extern cpuop_func_ce op_91b0_24_nf;
+extern cpuop_func_ce op_91b0_24_ff;
+extern cpuop_func_ce op_91b8_24_nf;
+extern cpuop_func_ce op_91b8_24_ff;
+extern cpuop_func_ce op_91b9_24_nf;
+extern cpuop_func_ce op_91b9_24_ff;
+extern cpuop_func_ce op_91c0_24_nf;
+extern cpuop_func_ce op_91c0_24_ff;
+extern cpuop_func_ce op_91c8_24_nf;
+extern cpuop_func_ce op_91c8_24_ff;
+extern cpuop_func_ce op_91d0_24_nf;
+extern cpuop_func_ce op_91d0_24_ff;
+extern cpuop_func_ce op_91d8_24_nf;
+extern cpuop_func_ce op_91d8_24_ff;
+extern cpuop_func_ce op_91e0_24_nf;
+extern cpuop_func_ce op_91e0_24_ff;
+extern cpuop_func_ce op_91e8_24_nf;
+extern cpuop_func_ce op_91e8_24_ff;
+extern cpuop_func_ce op_91f0_24_nf;
+extern cpuop_func_ce op_91f0_24_ff;
+extern cpuop_func_ce op_91f8_24_nf;
+extern cpuop_func_ce op_91f8_24_ff;
+extern cpuop_func_ce op_91f9_24_nf;
+extern cpuop_func_ce op_91f9_24_ff;
+extern cpuop_func_ce op_91fa_24_nf;
+extern cpuop_func_ce op_91fa_24_ff;
+extern cpuop_func_ce op_91fb_24_nf;
+extern cpuop_func_ce op_91fb_24_ff;
+extern cpuop_func_ce op_91fc_24_nf;
+extern cpuop_func_ce op_91fc_24_ff;
+extern cpuop_func_ce op_b000_24_nf;
+extern cpuop_func_ce op_b000_24_ff;
+extern cpuop_func_ce op_b010_24_nf;
+extern cpuop_func_ce op_b010_24_ff;
+extern cpuop_func_ce op_b018_24_nf;
+extern cpuop_func_ce op_b018_24_ff;
+extern cpuop_func_ce op_b020_24_nf;
+extern cpuop_func_ce op_b020_24_ff;
+extern cpuop_func_ce op_b028_24_nf;
+extern cpuop_func_ce op_b028_24_ff;
+extern cpuop_func_ce op_b030_24_nf;
+extern cpuop_func_ce op_b030_24_ff;
+extern cpuop_func_ce op_b038_24_nf;
+extern cpuop_func_ce op_b038_24_ff;
+extern cpuop_func_ce op_b039_24_nf;
+extern cpuop_func_ce op_b039_24_ff;
+extern cpuop_func_ce op_b03a_24_nf;
+extern cpuop_func_ce op_b03a_24_ff;
+extern cpuop_func_ce op_b03b_24_nf;
+extern cpuop_func_ce op_b03b_24_ff;
+extern cpuop_func_ce op_b03c_24_nf;
+extern cpuop_func_ce op_b03c_24_ff;
+extern cpuop_func_ce op_b040_24_nf;
+extern cpuop_func_ce op_b040_24_ff;
+extern cpuop_func_ce op_b048_24_nf;
+extern cpuop_func_ce op_b048_24_ff;
+extern cpuop_func_ce op_b050_24_nf;
+extern cpuop_func_ce op_b050_24_ff;
+extern cpuop_func_ce op_b058_24_nf;
+extern cpuop_func_ce op_b058_24_ff;
+extern cpuop_func_ce op_b060_24_nf;
+extern cpuop_func_ce op_b060_24_ff;
+extern cpuop_func_ce op_b068_24_nf;
+extern cpuop_func_ce op_b068_24_ff;
+extern cpuop_func_ce op_b070_24_nf;
+extern cpuop_func_ce op_b070_24_ff;
+extern cpuop_func_ce op_b078_24_nf;
+extern cpuop_func_ce op_b078_24_ff;
+extern cpuop_func_ce op_b079_24_nf;
+extern cpuop_func_ce op_b079_24_ff;
+extern cpuop_func_ce op_b07a_24_nf;
+extern cpuop_func_ce op_b07a_24_ff;
+extern cpuop_func_ce op_b07b_24_nf;
+extern cpuop_func_ce op_b07b_24_ff;
+extern cpuop_func_ce op_b07c_24_nf;
+extern cpuop_func_ce op_b07c_24_ff;
+extern cpuop_func_ce op_b080_24_nf;
+extern cpuop_func_ce op_b080_24_ff;
+extern cpuop_func_ce op_b088_24_nf;
+extern cpuop_func_ce op_b088_24_ff;
+extern cpuop_func_ce op_b090_24_nf;
+extern cpuop_func_ce op_b090_24_ff;
+extern cpuop_func_ce op_b098_24_nf;
+extern cpuop_func_ce op_b098_24_ff;
+extern cpuop_func_ce op_b0a0_24_nf;
+extern cpuop_func_ce op_b0a0_24_ff;
+extern cpuop_func_ce op_b0a8_24_nf;
+extern cpuop_func_ce op_b0a8_24_ff;
+extern cpuop_func_ce op_b0b0_24_nf;
+extern cpuop_func_ce op_b0b0_24_ff;
+extern cpuop_func_ce op_b0b8_24_nf;
+extern cpuop_func_ce op_b0b8_24_ff;
+extern cpuop_func_ce op_b0b9_24_nf;
+extern cpuop_func_ce op_b0b9_24_ff;
+extern cpuop_func_ce op_b0ba_24_nf;
+extern cpuop_func_ce op_b0ba_24_ff;
+extern cpuop_func_ce op_b0bb_24_nf;
+extern cpuop_func_ce op_b0bb_24_ff;
+extern cpuop_func_ce op_b0bc_24_nf;
+extern cpuop_func_ce op_b0bc_24_ff;
+extern cpuop_func_ce op_b0c0_24_nf;
+extern cpuop_func_ce op_b0c0_24_ff;
+extern cpuop_func_ce op_b0c8_24_nf;
+extern cpuop_func_ce op_b0c8_24_ff;
+extern cpuop_func_ce op_b0d0_24_nf;
+extern cpuop_func_ce op_b0d0_24_ff;
+extern cpuop_func_ce op_b0d8_24_nf;
+extern cpuop_func_ce op_b0d8_24_ff;
+extern cpuop_func_ce op_b0e0_24_nf;
+extern cpuop_func_ce op_b0e0_24_ff;
+extern cpuop_func_ce op_b0e8_24_nf;
+extern cpuop_func_ce op_b0e8_24_ff;
+extern cpuop_func_ce op_b0f0_24_nf;
+extern cpuop_func_ce op_b0f0_24_ff;
+extern cpuop_func_ce op_b0f8_24_nf;
+extern cpuop_func_ce op_b0f8_24_ff;
+extern cpuop_func_ce op_b0f9_24_nf;
+extern cpuop_func_ce op_b0f9_24_ff;
+extern cpuop_func_ce op_b0fa_24_nf;
+extern cpuop_func_ce op_b0fa_24_ff;
+extern cpuop_func_ce op_b0fb_24_nf;
+extern cpuop_func_ce op_b0fb_24_ff;
+extern cpuop_func_ce op_b0fc_24_nf;
+extern cpuop_func_ce op_b0fc_24_ff;
+extern cpuop_func_ce op_b100_24_nf;
+extern cpuop_func_ce op_b100_24_ff;
+extern cpuop_func_ce op_b108_24_nf;
+extern cpuop_func_ce op_b108_24_ff;
+extern cpuop_func_ce op_b110_24_nf;
+extern cpuop_func_ce op_b110_24_ff;
+extern cpuop_func_ce op_b118_24_nf;
+extern cpuop_func_ce op_b118_24_ff;
+extern cpuop_func_ce op_b120_24_nf;
+extern cpuop_func_ce op_b120_24_ff;
+extern cpuop_func_ce op_b128_24_nf;
+extern cpuop_func_ce op_b128_24_ff;
+extern cpuop_func_ce op_b130_24_nf;
+extern cpuop_func_ce op_b130_24_ff;
+extern cpuop_func_ce op_b138_24_nf;
+extern cpuop_func_ce op_b138_24_ff;
+extern cpuop_func_ce op_b139_24_nf;
+extern cpuop_func_ce op_b139_24_ff;
+extern cpuop_func_ce op_b140_24_nf;
+extern cpuop_func_ce op_b140_24_ff;
+extern cpuop_func_ce op_b148_24_nf;
+extern cpuop_func_ce op_b148_24_ff;
+extern cpuop_func_ce op_b150_24_nf;
+extern cpuop_func_ce op_b150_24_ff;
+extern cpuop_func_ce op_b158_24_nf;
+extern cpuop_func_ce op_b158_24_ff;
+extern cpuop_func_ce op_b160_24_nf;
+extern cpuop_func_ce op_b160_24_ff;
+extern cpuop_func_ce op_b168_24_nf;
+extern cpuop_func_ce op_b168_24_ff;
+extern cpuop_func_ce op_b170_24_nf;
+extern cpuop_func_ce op_b170_24_ff;
+extern cpuop_func_ce op_b178_24_nf;
+extern cpuop_func_ce op_b178_24_ff;
+extern cpuop_func_ce op_b179_24_nf;
+extern cpuop_func_ce op_b179_24_ff;
+extern cpuop_func_ce op_b180_24_nf;
+extern cpuop_func_ce op_b180_24_ff;
+extern cpuop_func_ce op_b188_24_nf;
+extern cpuop_func_ce op_b188_24_ff;
+extern cpuop_func_ce op_b190_24_nf;
+extern cpuop_func_ce op_b190_24_ff;
+extern cpuop_func_ce op_b198_24_nf;
+extern cpuop_func_ce op_b198_24_ff;
+extern cpuop_func_ce op_b1a0_24_nf;
+extern cpuop_func_ce op_b1a0_24_ff;
+extern cpuop_func_ce op_b1a8_24_nf;
+extern cpuop_func_ce op_b1a8_24_ff;
+extern cpuop_func_ce op_b1b0_24_nf;
+extern cpuop_func_ce op_b1b0_24_ff;
+extern cpuop_func_ce op_b1b8_24_nf;
+extern cpuop_func_ce op_b1b8_24_ff;
+extern cpuop_func_ce op_b1b9_24_nf;
+extern cpuop_func_ce op_b1b9_24_ff;
+extern cpuop_func_ce op_b1c0_24_nf;
+extern cpuop_func_ce op_b1c0_24_ff;
+extern cpuop_func_ce op_b1c8_24_nf;
+extern cpuop_func_ce op_b1c8_24_ff;
+extern cpuop_func_ce op_b1d0_24_nf;
+extern cpuop_func_ce op_b1d0_24_ff;
+extern cpuop_func_ce op_b1d8_24_nf;
+extern cpuop_func_ce op_b1d8_24_ff;
+extern cpuop_func_ce op_b1e0_24_nf;
+extern cpuop_func_ce op_b1e0_24_ff;
+extern cpuop_func_ce op_b1e8_24_nf;
+extern cpuop_func_ce op_b1e8_24_ff;
+extern cpuop_func_ce op_b1f0_24_nf;
+extern cpuop_func_ce op_b1f0_24_ff;
+extern cpuop_func_ce op_b1f8_24_nf;
+extern cpuop_func_ce op_b1f8_24_ff;
+extern cpuop_func_ce op_b1f9_24_nf;
+extern cpuop_func_ce op_b1f9_24_ff;
+extern cpuop_func_ce op_b1fa_24_nf;
+extern cpuop_func_ce op_b1fa_24_ff;
+extern cpuop_func_ce op_b1fb_24_nf;
+extern cpuop_func_ce op_b1fb_24_ff;
+extern cpuop_func_ce op_b1fc_24_nf;
+extern cpuop_func_ce op_b1fc_24_ff;
+extern cpuop_func_ce op_c000_24_nf;
+extern cpuop_func_ce op_c000_24_ff;
+extern cpuop_func_ce op_c010_24_nf;
+extern cpuop_func_ce op_c010_24_ff;
+extern cpuop_func_ce op_c018_24_nf;
+extern cpuop_func_ce op_c018_24_ff;
+extern cpuop_func_ce op_c020_24_nf;
+extern cpuop_func_ce op_c020_24_ff;
+extern cpuop_func_ce op_c028_24_nf;
+extern cpuop_func_ce op_c028_24_ff;
+extern cpuop_func_ce op_c030_24_nf;
+extern cpuop_func_ce op_c030_24_ff;
+extern cpuop_func_ce op_c038_24_nf;
+extern cpuop_func_ce op_c038_24_ff;
+extern cpuop_func_ce op_c039_24_nf;
+extern cpuop_func_ce op_c039_24_ff;
+extern cpuop_func_ce op_c03a_24_nf;
+extern cpuop_func_ce op_c03a_24_ff;
+extern cpuop_func_ce op_c03b_24_nf;
+extern cpuop_func_ce op_c03b_24_ff;
+extern cpuop_func_ce op_c03c_24_nf;
+extern cpuop_func_ce op_c03c_24_ff;
+extern cpuop_func_ce op_c040_24_nf;
+extern cpuop_func_ce op_c040_24_ff;
+extern cpuop_func_ce op_c050_24_nf;
+extern cpuop_func_ce op_c050_24_ff;
+extern cpuop_func_ce op_c058_24_nf;
+extern cpuop_func_ce op_c058_24_ff;
+extern cpuop_func_ce op_c060_24_nf;
+extern cpuop_func_ce op_c060_24_ff;
+extern cpuop_func_ce op_c068_24_nf;
+extern cpuop_func_ce op_c068_24_ff;
+extern cpuop_func_ce op_c070_24_nf;
+extern cpuop_func_ce op_c070_24_ff;
+extern cpuop_func_ce op_c078_24_nf;
+extern cpuop_func_ce op_c078_24_ff;
+extern cpuop_func_ce op_c079_24_nf;
+extern cpuop_func_ce op_c079_24_ff;
+extern cpuop_func_ce op_c07a_24_nf;
+extern cpuop_func_ce op_c07a_24_ff;
+extern cpuop_func_ce op_c07b_24_nf;
+extern cpuop_func_ce op_c07b_24_ff;
+extern cpuop_func_ce op_c07c_24_nf;
+extern cpuop_func_ce op_c07c_24_ff;
+extern cpuop_func_ce op_c080_24_nf;
+extern cpuop_func_ce op_c080_24_ff;
+extern cpuop_func_ce op_c090_24_nf;
+extern cpuop_func_ce op_c090_24_ff;
+extern cpuop_func_ce op_c098_24_nf;
+extern cpuop_func_ce op_c098_24_ff;
+extern cpuop_func_ce op_c0a0_24_nf;
+extern cpuop_func_ce op_c0a0_24_ff;
+extern cpuop_func_ce op_c0a8_24_nf;
+extern cpuop_func_ce op_c0a8_24_ff;
+extern cpuop_func_ce op_c0b0_24_nf;
+extern cpuop_func_ce op_c0b0_24_ff;
+extern cpuop_func_ce op_c0b8_24_nf;
+extern cpuop_func_ce op_c0b8_24_ff;
+extern cpuop_func_ce op_c0b9_24_nf;
+extern cpuop_func_ce op_c0b9_24_ff;
+extern cpuop_func_ce op_c0ba_24_nf;
+extern cpuop_func_ce op_c0ba_24_ff;
+extern cpuop_func_ce op_c0bb_24_nf;
+extern cpuop_func_ce op_c0bb_24_ff;
+extern cpuop_func_ce op_c0bc_24_nf;
+extern cpuop_func_ce op_c0bc_24_ff;
+extern cpuop_func_ce op_c0c0_24_nf;
+extern cpuop_func_ce op_c0c0_24_ff;
+extern cpuop_func_ce op_c0d0_24_nf;
+extern cpuop_func_ce op_c0d0_24_ff;
+extern cpuop_func_ce op_c0d8_24_nf;
+extern cpuop_func_ce op_c0d8_24_ff;
+extern cpuop_func_ce op_c0e0_24_nf;
+extern cpuop_func_ce op_c0e0_24_ff;
+extern cpuop_func_ce op_c0e8_24_nf;
+extern cpuop_func_ce op_c0e8_24_ff;
+extern cpuop_func_ce op_c0f0_24_nf;
+extern cpuop_func_ce op_c0f0_24_ff;
+extern cpuop_func_ce op_c0f8_24_nf;
+extern cpuop_func_ce op_c0f8_24_ff;
+extern cpuop_func_ce op_c0f9_24_nf;
+extern cpuop_func_ce op_c0f9_24_ff;
+extern cpuop_func_ce op_c0fa_24_nf;
+extern cpuop_func_ce op_c0fa_24_ff;
+extern cpuop_func_ce op_c0fb_24_nf;
+extern cpuop_func_ce op_c0fb_24_ff;
+extern cpuop_func_ce op_c0fc_24_nf;
+extern cpuop_func_ce op_c0fc_24_ff;
+extern cpuop_func_ce op_c100_24_nf;
+extern cpuop_func_ce op_c100_24_ff;
+extern cpuop_func_ce op_c108_24_nf;
+extern cpuop_func_ce op_c108_24_ff;
+extern cpuop_func_ce op_c110_24_nf;
+extern cpuop_func_ce op_c110_24_ff;
+extern cpuop_func_ce op_c118_24_nf;
+extern cpuop_func_ce op_c118_24_ff;
+extern cpuop_func_ce op_c120_24_nf;
+extern cpuop_func_ce op_c120_24_ff;
+extern cpuop_func_ce op_c128_24_nf;
+extern cpuop_func_ce op_c128_24_ff;
+extern cpuop_func_ce op_c130_24_nf;
+extern cpuop_func_ce op_c130_24_ff;
+extern cpuop_func_ce op_c138_24_nf;
+extern cpuop_func_ce op_c138_24_ff;
+extern cpuop_func_ce op_c139_24_nf;
+extern cpuop_func_ce op_c139_24_ff;
+extern cpuop_func_ce op_c140_24_nf;
+extern cpuop_func_ce op_c140_24_ff;
+extern cpuop_func_ce op_c148_24_nf;
+extern cpuop_func_ce op_c148_24_ff;
+extern cpuop_func_ce op_c150_24_nf;
+extern cpuop_func_ce op_c150_24_ff;
+extern cpuop_func_ce op_c158_24_nf;
+extern cpuop_func_ce op_c158_24_ff;
+extern cpuop_func_ce op_c160_24_nf;
+extern cpuop_func_ce op_c160_24_ff;
+extern cpuop_func_ce op_c168_24_nf;
+extern cpuop_func_ce op_c168_24_ff;
+extern cpuop_func_ce op_c170_24_nf;
+extern cpuop_func_ce op_c170_24_ff;
+extern cpuop_func_ce op_c178_24_nf;
+extern cpuop_func_ce op_c178_24_ff;
+extern cpuop_func_ce op_c179_24_nf;
+extern cpuop_func_ce op_c179_24_ff;
+extern cpuop_func_ce op_c188_24_nf;
+extern cpuop_func_ce op_c188_24_ff;
+extern cpuop_func_ce op_c190_24_nf;
+extern cpuop_func_ce op_c190_24_ff;
+extern cpuop_func_ce op_c198_24_nf;
+extern cpuop_func_ce op_c198_24_ff;
+extern cpuop_func_ce op_c1a0_24_nf;
+extern cpuop_func_ce op_c1a0_24_ff;
+extern cpuop_func_ce op_c1a8_24_nf;
+extern cpuop_func_ce op_c1a8_24_ff;
+extern cpuop_func_ce op_c1b0_24_nf;
+extern cpuop_func_ce op_c1b0_24_ff;
+extern cpuop_func_ce op_c1b8_24_nf;
+extern cpuop_func_ce op_c1b8_24_ff;
+extern cpuop_func_ce op_c1b9_24_nf;
+extern cpuop_func_ce op_c1b9_24_ff;
+extern cpuop_func_ce op_c1c0_24_nf;
+extern cpuop_func_ce op_c1c0_24_ff;
+extern cpuop_func_ce op_c1d0_24_nf;
+extern cpuop_func_ce op_c1d0_24_ff;
+extern cpuop_func_ce op_c1d8_24_nf;
+extern cpuop_func_ce op_c1d8_24_ff;
+extern cpuop_func_ce op_c1e0_24_nf;
+extern cpuop_func_ce op_c1e0_24_ff;
+extern cpuop_func_ce op_c1e8_24_nf;
+extern cpuop_func_ce op_c1e8_24_ff;
+extern cpuop_func_ce op_c1f0_24_nf;
+extern cpuop_func_ce op_c1f0_24_ff;
+extern cpuop_func_ce op_c1f8_24_nf;
+extern cpuop_func_ce op_c1f8_24_ff;
+extern cpuop_func_ce op_c1f9_24_nf;
+extern cpuop_func_ce op_c1f9_24_ff;
+extern cpuop_func_ce op_c1fa_24_nf;
+extern cpuop_func_ce op_c1fa_24_ff;
+extern cpuop_func_ce op_c1fb_24_nf;
+extern cpuop_func_ce op_c1fb_24_ff;
+extern cpuop_func_ce op_c1fc_24_nf;
+extern cpuop_func_ce op_c1fc_24_ff;
+extern cpuop_func_ce op_d000_24_nf;
+extern cpuop_func_ce op_d000_24_ff;
+extern cpuop_func_ce op_d010_24_nf;
+extern cpuop_func_ce op_d010_24_ff;
+extern cpuop_func_ce op_d018_24_nf;
+extern cpuop_func_ce op_d018_24_ff;
+extern cpuop_func_ce op_d020_24_nf;
+extern cpuop_func_ce op_d020_24_ff;
+extern cpuop_func_ce op_d028_24_nf;
+extern cpuop_func_ce op_d028_24_ff;
+extern cpuop_func_ce op_d030_24_nf;
+extern cpuop_func_ce op_d030_24_ff;
+extern cpuop_func_ce op_d038_24_nf;
+extern cpuop_func_ce op_d038_24_ff;
+extern cpuop_func_ce op_d039_24_nf;
+extern cpuop_func_ce op_d039_24_ff;
+extern cpuop_func_ce op_d03a_24_nf;
+extern cpuop_func_ce op_d03a_24_ff;
+extern cpuop_func_ce op_d03b_24_nf;
+extern cpuop_func_ce op_d03b_24_ff;
+extern cpuop_func_ce op_d03c_24_nf;
+extern cpuop_func_ce op_d03c_24_ff;
+extern cpuop_func_ce op_d040_24_nf;
+extern cpuop_func_ce op_d040_24_ff;
+extern cpuop_func_ce op_d048_24_nf;
+extern cpuop_func_ce op_d048_24_ff;
+extern cpuop_func_ce op_d050_24_nf;
+extern cpuop_func_ce op_d050_24_ff;
+extern cpuop_func_ce op_d058_24_nf;
+extern cpuop_func_ce op_d058_24_ff;
+extern cpuop_func_ce op_d060_24_nf;
+extern cpuop_func_ce op_d060_24_ff;
+extern cpuop_func_ce op_d068_24_nf;
+extern cpuop_func_ce op_d068_24_ff;
+extern cpuop_func_ce op_d070_24_nf;
+extern cpuop_func_ce op_d070_24_ff;
+extern cpuop_func_ce op_d078_24_nf;
+extern cpuop_func_ce op_d078_24_ff;
+extern cpuop_func_ce op_d079_24_nf;
+extern cpuop_func_ce op_d079_24_ff;
+extern cpuop_func_ce op_d07a_24_nf;
+extern cpuop_func_ce op_d07a_24_ff;
+extern cpuop_func_ce op_d07b_24_nf;
+extern cpuop_func_ce op_d07b_24_ff;
+extern cpuop_func_ce op_d07c_24_nf;
+extern cpuop_func_ce op_d07c_24_ff;
+extern cpuop_func_ce op_d080_24_nf;
+extern cpuop_func_ce op_d080_24_ff;
+extern cpuop_func_ce op_d088_24_nf;
+extern cpuop_func_ce op_d088_24_ff;
+extern cpuop_func_ce op_d090_24_nf;
+extern cpuop_func_ce op_d090_24_ff;
+extern cpuop_func_ce op_d098_24_nf;
+extern cpuop_func_ce op_d098_24_ff;
+extern cpuop_func_ce op_d0a0_24_nf;
+extern cpuop_func_ce op_d0a0_24_ff;
+extern cpuop_func_ce op_d0a8_24_nf;
+extern cpuop_func_ce op_d0a8_24_ff;
+extern cpuop_func_ce op_d0b0_24_nf;
+extern cpuop_func_ce op_d0b0_24_ff;
+extern cpuop_func_ce op_d0b8_24_nf;
+extern cpuop_func_ce op_d0b8_24_ff;
+extern cpuop_func_ce op_d0b9_24_nf;
+extern cpuop_func_ce op_d0b9_24_ff;
+extern cpuop_func_ce op_d0ba_24_nf;
+extern cpuop_func_ce op_d0ba_24_ff;
+extern cpuop_func_ce op_d0bb_24_nf;
+extern cpuop_func_ce op_d0bb_24_ff;
+extern cpuop_func_ce op_d0bc_24_nf;
+extern cpuop_func_ce op_d0bc_24_ff;
+extern cpuop_func_ce op_d0c0_24_nf;
+extern cpuop_func_ce op_d0c0_24_ff;
+extern cpuop_func_ce op_d0c8_24_nf;
+extern cpuop_func_ce op_d0c8_24_ff;
+extern cpuop_func_ce op_d0d0_24_nf;
+extern cpuop_func_ce op_d0d0_24_ff;
+extern cpuop_func_ce op_d0d8_24_nf;
+extern cpuop_func_ce op_d0d8_24_ff;
+extern cpuop_func_ce op_d0e0_24_nf;
+extern cpuop_func_ce op_d0e0_24_ff;
+extern cpuop_func_ce op_d0e8_24_nf;
+extern cpuop_func_ce op_d0e8_24_ff;
+extern cpuop_func_ce op_d0f0_24_nf;
+extern cpuop_func_ce op_d0f0_24_ff;
+extern cpuop_func_ce op_d0f8_24_nf;
+extern cpuop_func_ce op_d0f8_24_ff;
+extern cpuop_func_ce op_d0f9_24_nf;
+extern cpuop_func_ce op_d0f9_24_ff;
+extern cpuop_func_ce op_d0fa_24_nf;
+extern cpuop_func_ce op_d0fa_24_ff;
+extern cpuop_func_ce op_d0fb_24_nf;
+extern cpuop_func_ce op_d0fb_24_ff;
+extern cpuop_func_ce op_d0fc_24_nf;
+extern cpuop_func_ce op_d0fc_24_ff;
+extern cpuop_func_ce op_d100_24_nf;
+extern cpuop_func_ce op_d100_24_ff;
+extern cpuop_func_ce op_d108_24_nf;
+extern cpuop_func_ce op_d108_24_ff;
+extern cpuop_func_ce op_d110_24_nf;
+extern cpuop_func_ce op_d110_24_ff;
+extern cpuop_func_ce op_d118_24_nf;
+extern cpuop_func_ce op_d118_24_ff;
+extern cpuop_func_ce op_d120_24_nf;
+extern cpuop_func_ce op_d120_24_ff;
+extern cpuop_func_ce op_d128_24_nf;
+extern cpuop_func_ce op_d128_24_ff;
+extern cpuop_func_ce op_d130_24_nf;
+extern cpuop_func_ce op_d130_24_ff;
+extern cpuop_func_ce op_d138_24_nf;
+extern cpuop_func_ce op_d138_24_ff;
+extern cpuop_func_ce op_d139_24_nf;
+extern cpuop_func_ce op_d139_24_ff;
+extern cpuop_func_ce op_d140_24_nf;
+extern cpuop_func_ce op_d140_24_ff;
+extern cpuop_func_ce op_d148_24_nf;
+extern cpuop_func_ce op_d148_24_ff;
+extern cpuop_func_ce op_d150_24_nf;
+extern cpuop_func_ce op_d150_24_ff;
+extern cpuop_func_ce op_d158_24_nf;
+extern cpuop_func_ce op_d158_24_ff;
+extern cpuop_func_ce op_d160_24_nf;
+extern cpuop_func_ce op_d160_24_ff;
+extern cpuop_func_ce op_d168_24_nf;
+extern cpuop_func_ce op_d168_24_ff;
+extern cpuop_func_ce op_d170_24_nf;
+extern cpuop_func_ce op_d170_24_ff;
+extern cpuop_func_ce op_d178_24_nf;
+extern cpuop_func_ce op_d178_24_ff;
+extern cpuop_func_ce op_d179_24_nf;
+extern cpuop_func_ce op_d179_24_ff;
+extern cpuop_func_ce op_d180_24_nf;
+extern cpuop_func_ce op_d180_24_ff;
+extern cpuop_func_ce op_d188_24_nf;
+extern cpuop_func_ce op_d188_24_ff;
+extern cpuop_func_ce op_d190_24_nf;
+extern cpuop_func_ce op_d190_24_ff;
+extern cpuop_func_ce op_d198_24_nf;
+extern cpuop_func_ce op_d198_24_ff;
+extern cpuop_func_ce op_d1a0_24_nf;
+extern cpuop_func_ce op_d1a0_24_ff;
+extern cpuop_func_ce op_d1a8_24_nf;
+extern cpuop_func_ce op_d1a8_24_ff;
+extern cpuop_func_ce op_d1b0_24_nf;
+extern cpuop_func_ce op_d1b0_24_ff;
+extern cpuop_func_ce op_d1b8_24_nf;
+extern cpuop_func_ce op_d1b8_24_ff;
+extern cpuop_func_ce op_d1b9_24_nf;
+extern cpuop_func_ce op_d1b9_24_ff;
+extern cpuop_func_ce op_d1c0_24_nf;
+extern cpuop_func_ce op_d1c0_24_ff;
+extern cpuop_func_ce op_d1c8_24_nf;
+extern cpuop_func_ce op_d1c8_24_ff;
+extern cpuop_func_ce op_d1d0_24_nf;
+extern cpuop_func_ce op_d1d0_24_ff;
+extern cpuop_func_ce op_d1d8_24_nf;
+extern cpuop_func_ce op_d1d8_24_ff;
+extern cpuop_func_ce op_d1e0_24_nf;
+extern cpuop_func_ce op_d1e0_24_ff;
+extern cpuop_func_ce op_d1e8_24_nf;
+extern cpuop_func_ce op_d1e8_24_ff;
+extern cpuop_func_ce op_d1f0_24_nf;
+extern cpuop_func_ce op_d1f0_24_ff;
+extern cpuop_func_ce op_d1f8_24_nf;
+extern cpuop_func_ce op_d1f8_24_ff;
+extern cpuop_func_ce op_d1f9_24_nf;
+extern cpuop_func_ce op_d1f9_24_ff;
+extern cpuop_func_ce op_d1fa_24_nf;
+extern cpuop_func_ce op_d1fa_24_ff;
+extern cpuop_func_ce op_d1fb_24_nf;
+extern cpuop_func_ce op_d1fb_24_ff;
+extern cpuop_func_ce op_d1fc_24_nf;
+extern cpuop_func_ce op_d1fc_24_ff;
+extern cpuop_func_ce op_e000_24_nf;
+extern cpuop_func_ce op_e000_24_ff;
+extern cpuop_func_ce op_e008_24_nf;
+extern cpuop_func_ce op_e008_24_ff;
+extern cpuop_func_ce op_e010_24_nf;
+extern cpuop_func_ce op_e010_24_ff;
+extern cpuop_func_ce op_e018_24_nf;
+extern cpuop_func_ce op_e018_24_ff;
+extern cpuop_func_ce op_e020_24_nf;
+extern cpuop_func_ce op_e020_24_ff;
+extern cpuop_func_ce op_e028_24_nf;
+extern cpuop_func_ce op_e028_24_ff;
+extern cpuop_func_ce op_e030_24_nf;
+extern cpuop_func_ce op_e030_24_ff;
+extern cpuop_func_ce op_e038_24_nf;
+extern cpuop_func_ce op_e038_24_ff;
+extern cpuop_func_ce op_e040_24_nf;
+extern cpuop_func_ce op_e040_24_ff;
+extern cpuop_func_ce op_e048_24_nf;
+extern cpuop_func_ce op_e048_24_ff;
+extern cpuop_func_ce op_e050_24_nf;
+extern cpuop_func_ce op_e050_24_ff;
+extern cpuop_func_ce op_e058_24_nf;
+extern cpuop_func_ce op_e058_24_ff;
+extern cpuop_func_ce op_e060_24_nf;
+extern cpuop_func_ce op_e060_24_ff;
+extern cpuop_func_ce op_e068_24_nf;
+extern cpuop_func_ce op_e068_24_ff;
+extern cpuop_func_ce op_e070_24_nf;
+extern cpuop_func_ce op_e070_24_ff;
+extern cpuop_func_ce op_e078_24_nf;
+extern cpuop_func_ce op_e078_24_ff;
+extern cpuop_func_ce op_e080_24_nf;
+extern cpuop_func_ce op_e080_24_ff;
+extern cpuop_func_ce op_e088_24_nf;
+extern cpuop_func_ce op_e088_24_ff;
+extern cpuop_func_ce op_e090_24_nf;
+extern cpuop_func_ce op_e090_24_ff;
+extern cpuop_func_ce op_e098_24_nf;
+extern cpuop_func_ce op_e098_24_ff;
+extern cpuop_func_ce op_e0a0_24_nf;
+extern cpuop_func_ce op_e0a0_24_ff;
+extern cpuop_func_ce op_e0a8_24_nf;
+extern cpuop_func_ce op_e0a8_24_ff;
+extern cpuop_func_ce op_e0b0_24_nf;
+extern cpuop_func_ce op_e0b0_24_ff;
+extern cpuop_func_ce op_e0b8_24_nf;
+extern cpuop_func_ce op_e0b8_24_ff;
+extern cpuop_func_ce op_e0d0_24_nf;
+extern cpuop_func_ce op_e0d0_24_ff;
+extern cpuop_func_ce op_e0d8_24_nf;
+extern cpuop_func_ce op_e0d8_24_ff;
+extern cpuop_func_ce op_e0e0_24_nf;
+extern cpuop_func_ce op_e0e0_24_ff;
+extern cpuop_func_ce op_e0e8_24_nf;
+extern cpuop_func_ce op_e0e8_24_ff;
+extern cpuop_func_ce op_e0f0_24_nf;
+extern cpuop_func_ce op_e0f0_24_ff;
+extern cpuop_func_ce op_e0f8_24_nf;
+extern cpuop_func_ce op_e0f8_24_ff;
+extern cpuop_func_ce op_e0f9_24_nf;
+extern cpuop_func_ce op_e0f9_24_ff;
+extern cpuop_func_ce op_e100_24_nf;
+extern cpuop_func_ce op_e100_24_ff;
+extern cpuop_func_ce op_e108_24_nf;
+extern cpuop_func_ce op_e108_24_ff;
+extern cpuop_func_ce op_e110_24_nf;
+extern cpuop_func_ce op_e110_24_ff;
+extern cpuop_func_ce op_e118_24_nf;
+extern cpuop_func_ce op_e118_24_ff;
+extern cpuop_func_ce op_e120_24_nf;
+extern cpuop_func_ce op_e120_24_ff;
+extern cpuop_func_ce op_e128_24_nf;
+extern cpuop_func_ce op_e128_24_ff;
+extern cpuop_func_ce op_e130_24_nf;
+extern cpuop_func_ce op_e130_24_ff;
+extern cpuop_func_ce op_e138_24_nf;
+extern cpuop_func_ce op_e138_24_ff;
+extern cpuop_func_ce op_e140_24_nf;
+extern cpuop_func_ce op_e140_24_ff;
+extern cpuop_func_ce op_e148_24_nf;
+extern cpuop_func_ce op_e148_24_ff;
+extern cpuop_func_ce op_e150_24_nf;
+extern cpuop_func_ce op_e150_24_ff;
+extern cpuop_func_ce op_e158_24_nf;
+extern cpuop_func_ce op_e158_24_ff;
+extern cpuop_func_ce op_e160_24_nf;
+extern cpuop_func_ce op_e160_24_ff;
+extern cpuop_func_ce op_e168_24_nf;
+extern cpuop_func_ce op_e168_24_ff;
+extern cpuop_func_ce op_e170_24_nf;
+extern cpuop_func_ce op_e170_24_ff;
+extern cpuop_func_ce op_e178_24_nf;
+extern cpuop_func_ce op_e178_24_ff;
+extern cpuop_func_ce op_e180_24_nf;
+extern cpuop_func_ce op_e180_24_ff;
+extern cpuop_func_ce op_e188_24_nf;
+extern cpuop_func_ce op_e188_24_ff;
+extern cpuop_func_ce op_e190_24_nf;
+extern cpuop_func_ce op_e190_24_ff;
+extern cpuop_func_ce op_e198_24_nf;
+extern cpuop_func_ce op_e198_24_ff;
+extern cpuop_func_ce op_e1a0_24_nf;
+extern cpuop_func_ce op_e1a0_24_ff;
+extern cpuop_func_ce op_e1a8_24_nf;
+extern cpuop_func_ce op_e1a8_24_ff;
+extern cpuop_func_ce op_e1b0_24_nf;
+extern cpuop_func_ce op_e1b0_24_ff;
+extern cpuop_func_ce op_e1b8_24_nf;
+extern cpuop_func_ce op_e1b8_24_ff;
+extern cpuop_func_ce op_e1d0_24_nf;
+extern cpuop_func_ce op_e1d0_24_ff;
+extern cpuop_func_ce op_e1d8_24_nf;
+extern cpuop_func_ce op_e1d8_24_ff;
+extern cpuop_func_ce op_e1e0_24_nf;
+extern cpuop_func_ce op_e1e0_24_ff;
+extern cpuop_func_ce op_e1e8_24_nf;
+extern cpuop_func_ce op_e1e8_24_ff;
+extern cpuop_func_ce op_e1f0_24_nf;
+extern cpuop_func_ce op_e1f0_24_ff;
+extern cpuop_func_ce op_e1f8_24_nf;
+extern cpuop_func_ce op_e1f8_24_ff;
+extern cpuop_func_ce op_e1f9_24_nf;
+extern cpuop_func_ce op_e1f9_24_ff;
+extern cpuop_func_ce op_e2d0_24_nf;
+extern cpuop_func_ce op_e2d0_24_ff;
+extern cpuop_func_ce op_e2d8_24_nf;
+extern cpuop_func_ce op_e2d8_24_ff;
+extern cpuop_func_ce op_e2e0_24_nf;
+extern cpuop_func_ce op_e2e0_24_ff;
+extern cpuop_func_ce op_e2e8_24_nf;
+extern cpuop_func_ce op_e2e8_24_ff;
+extern cpuop_func_ce op_e2f0_24_nf;
+extern cpuop_func_ce op_e2f0_24_ff;
+extern cpuop_func_ce op_e2f8_24_nf;
+extern cpuop_func_ce op_e2f8_24_ff;
+extern cpuop_func_ce op_e2f9_24_nf;
+extern cpuop_func_ce op_e2f9_24_ff;
+extern cpuop_func_ce op_e3d0_24_nf;
+extern cpuop_func_ce op_e3d0_24_ff;
+extern cpuop_func_ce op_e3d8_24_nf;
+extern cpuop_func_ce op_e3d8_24_ff;
+extern cpuop_func_ce op_e3e0_24_nf;
+extern cpuop_func_ce op_e3e0_24_ff;
+extern cpuop_func_ce op_e3e8_24_nf;
+extern cpuop_func_ce op_e3e8_24_ff;
+extern cpuop_func_ce op_e3f0_24_nf;
+extern cpuop_func_ce op_e3f0_24_ff;
+extern cpuop_func_ce op_e3f8_24_nf;
+extern cpuop_func_ce op_e3f8_24_ff;
+extern cpuop_func_ce op_e3f9_24_nf;
+extern cpuop_func_ce op_e3f9_24_ff;
+extern cpuop_func_ce op_e4d0_24_nf;
+extern cpuop_func_ce op_e4d0_24_ff;
+extern cpuop_func_ce op_e4d8_24_nf;
+extern cpuop_func_ce op_e4d8_24_ff;
+extern cpuop_func_ce op_e4e0_24_nf;
+extern cpuop_func_ce op_e4e0_24_ff;
+extern cpuop_func_ce op_e4e8_24_nf;
+extern cpuop_func_ce op_e4e8_24_ff;
+extern cpuop_func_ce op_e4f0_24_nf;
+extern cpuop_func_ce op_e4f0_24_ff;
+extern cpuop_func_ce op_e4f8_24_nf;
+extern cpuop_func_ce op_e4f8_24_ff;
+extern cpuop_func_ce op_e4f9_24_nf;
+extern cpuop_func_ce op_e4f9_24_ff;
+extern cpuop_func_ce op_e5d0_24_nf;
+extern cpuop_func_ce op_e5d0_24_ff;
+extern cpuop_func_ce op_e5d8_24_nf;
+extern cpuop_func_ce op_e5d8_24_ff;
+extern cpuop_func_ce op_e5e0_24_nf;
+extern cpuop_func_ce op_e5e0_24_ff;
+extern cpuop_func_ce op_e5e8_24_nf;
+extern cpuop_func_ce op_e5e8_24_ff;
+extern cpuop_func_ce op_e5f0_24_nf;
+extern cpuop_func_ce op_e5f0_24_ff;
+extern cpuop_func_ce op_e5f8_24_nf;
+extern cpuop_func_ce op_e5f8_24_ff;
+extern cpuop_func_ce op_e5f9_24_nf;
+extern cpuop_func_ce op_e5f9_24_ff;
+extern cpuop_func_ce op_e6d0_24_nf;
+extern cpuop_func_ce op_e6d0_24_ff;
+extern cpuop_func_ce op_e6d8_24_nf;
+extern cpuop_func_ce op_e6d8_24_ff;
+extern cpuop_func_ce op_e6e0_24_nf;
+extern cpuop_func_ce op_e6e0_24_ff;
+extern cpuop_func_ce op_e6e8_24_nf;
+extern cpuop_func_ce op_e6e8_24_ff;
+extern cpuop_func_ce op_e6f0_24_nf;
+extern cpuop_func_ce op_e6f0_24_ff;
+extern cpuop_func_ce op_e6f8_24_nf;
+extern cpuop_func_ce op_e6f8_24_ff;
+extern cpuop_func_ce op_e6f9_24_nf;
+extern cpuop_func_ce op_e6f9_24_ff;
+extern cpuop_func_ce op_e7d0_24_nf;
+extern cpuop_func_ce op_e7d0_24_ff;
+extern cpuop_func_ce op_e7d8_24_nf;
+extern cpuop_func_ce op_e7d8_24_ff;
+extern cpuop_func_ce op_e7e0_24_nf;
+extern cpuop_func_ce op_e7e0_24_ff;
+extern cpuop_func_ce op_e7e8_24_nf;
+extern cpuop_func_ce op_e7e8_24_ff;
+extern cpuop_func_ce op_e7f0_24_nf;
+extern cpuop_func_ce op_e7f0_24_ff;
+extern cpuop_func_ce op_e7f8_24_nf;
+extern cpuop_func_ce op_e7f8_24_ff;
+extern cpuop_func_ce op_e7f9_24_nf;
+extern cpuop_func_ce op_e7f9_24_ff;
+extern cpuop_func_ce op_e8c0_24_nf;
+extern cpuop_func_ce op_e8c0_24_ff;
+extern cpuop_func_ce op_e8d0_24_nf;
+extern cpuop_func_ce op_e8d0_24_ff;
+extern cpuop_func_ce op_e8e8_24_nf;
+extern cpuop_func_ce op_e8e8_24_ff;
+extern cpuop_func_ce op_e8f0_24_nf;
+extern cpuop_func_ce op_e8f0_24_ff;
+extern cpuop_func_ce op_e8f8_24_nf;
+extern cpuop_func_ce op_e8f8_24_ff;
+extern cpuop_func_ce op_e8f9_24_nf;
+extern cpuop_func_ce op_e8f9_24_ff;
+extern cpuop_func_ce op_e8fa_24_nf;
+extern cpuop_func_ce op_e8fa_24_ff;
+extern cpuop_func_ce op_e8fb_24_nf;
+extern cpuop_func_ce op_e8fb_24_ff;
+extern cpuop_func_ce op_e9c0_24_nf;
+extern cpuop_func_ce op_e9c0_24_ff;
+extern cpuop_func_ce op_e9d0_24_nf;
+extern cpuop_func_ce op_e9d0_24_ff;
+extern cpuop_func_ce op_e9e8_24_nf;
+extern cpuop_func_ce op_e9e8_24_ff;
+extern cpuop_func_ce op_e9f0_24_nf;
+extern cpuop_func_ce op_e9f0_24_ff;
+extern cpuop_func_ce op_e9f8_24_nf;
+extern cpuop_func_ce op_e9f8_24_ff;
+extern cpuop_func_ce op_e9f9_24_nf;
+extern cpuop_func_ce op_e9f9_24_ff;
+extern cpuop_func_ce op_e9fa_24_nf;
+extern cpuop_func_ce op_e9fa_24_ff;
+extern cpuop_func_ce op_e9fb_24_nf;
+extern cpuop_func_ce op_e9fb_24_ff;
+extern cpuop_func_ce op_eac0_24_nf;
+extern cpuop_func_ce op_eac0_24_ff;
+extern cpuop_func_ce op_ead0_24_nf;
+extern cpuop_func_ce op_ead0_24_ff;
+extern cpuop_func_ce op_eae8_24_nf;
+extern cpuop_func_ce op_eae8_24_ff;
+extern cpuop_func_ce op_eaf0_24_nf;
+extern cpuop_func_ce op_eaf0_24_ff;
+extern cpuop_func_ce op_eaf8_24_nf;
+extern cpuop_func_ce op_eaf8_24_ff;
+extern cpuop_func_ce op_eaf9_24_nf;
+extern cpuop_func_ce op_eaf9_24_ff;
+extern cpuop_func_ce op_ebc0_24_nf;
+extern cpuop_func_ce op_ebc0_24_ff;
+extern cpuop_func_ce op_ebd0_24_nf;
+extern cpuop_func_ce op_ebd0_24_ff;
+extern cpuop_func_ce op_ebe8_24_nf;
+extern cpuop_func_ce op_ebe8_24_ff;
+extern cpuop_func_ce op_ebf0_24_nf;
+extern cpuop_func_ce op_ebf0_24_ff;
+extern cpuop_func_ce op_ebf8_24_nf;
+extern cpuop_func_ce op_ebf8_24_ff;
+extern cpuop_func_ce op_ebf9_24_nf;
+extern cpuop_func_ce op_ebf9_24_ff;
+extern cpuop_func_ce op_ebfa_24_nf;
+extern cpuop_func_ce op_ebfa_24_ff;
+extern cpuop_func_ce op_ebfb_24_nf;
+extern cpuop_func_ce op_ebfb_24_ff;
+extern cpuop_func_ce op_ecc0_24_nf;
+extern cpuop_func_ce op_ecc0_24_ff;
+extern cpuop_func_ce op_ecd0_24_nf;
+extern cpuop_func_ce op_ecd0_24_ff;
+extern cpuop_func_ce op_ece8_24_nf;
+extern cpuop_func_ce op_ece8_24_ff;
+extern cpuop_func_ce op_ecf0_24_nf;
+extern cpuop_func_ce op_ecf0_24_ff;
+extern cpuop_func_ce op_ecf8_24_nf;
+extern cpuop_func_ce op_ecf8_24_ff;
+extern cpuop_func_ce op_ecf9_24_nf;
+extern cpuop_func_ce op_ecf9_24_ff;
+extern cpuop_func_ce op_edc0_24_nf;
+extern cpuop_func_ce op_edc0_24_ff;
+extern cpuop_func_ce op_edd0_24_nf;
+extern cpuop_func_ce op_edd0_24_ff;
+extern cpuop_func_ce op_ede8_24_nf;
+extern cpuop_func_ce op_ede8_24_ff;
+extern cpuop_func_ce op_edf0_24_nf;
+extern cpuop_func_ce op_edf0_24_ff;
+extern cpuop_func_ce op_edf8_24_nf;
+extern cpuop_func_ce op_edf8_24_ff;
+extern cpuop_func_ce op_edf9_24_nf;
+extern cpuop_func_ce op_edf9_24_ff;
+extern cpuop_func_ce op_edfa_24_nf;
+extern cpuop_func_ce op_edfa_24_ff;
+extern cpuop_func_ce op_edfb_24_nf;
+extern cpuop_func_ce op_edfb_24_ff;
+extern cpuop_func_ce op_eec0_24_nf;
+extern cpuop_func_ce op_eec0_24_ff;
+extern cpuop_func_ce op_eed0_24_nf;
+extern cpuop_func_ce op_eed0_24_ff;
+extern cpuop_func_ce op_eee8_24_nf;
+extern cpuop_func_ce op_eee8_24_ff;
+extern cpuop_func_ce op_eef0_24_nf;
+extern cpuop_func_ce op_eef0_24_ff;
+extern cpuop_func_ce op_eef8_24_nf;
+extern cpuop_func_ce op_eef8_24_ff;
+extern cpuop_func_ce op_eef9_24_nf;
+extern cpuop_func_ce op_eef9_24_ff;
+extern cpuop_func_ce op_efc0_24_nf;
+extern cpuop_func_ce op_efc0_24_ff;
+extern cpuop_func_ce op_efd0_24_nf;
+extern cpuop_func_ce op_efd0_24_ff;
+extern cpuop_func_ce op_efe8_24_nf;
+extern cpuop_func_ce op_efe8_24_ff;
+extern cpuop_func_ce op_eff0_24_nf;
+extern cpuop_func_ce op_eff0_24_ff;
+extern cpuop_func_ce op_eff8_24_nf;
+extern cpuop_func_ce op_eff8_24_ff;
+extern cpuop_func_ce op_eff9_24_nf;
+extern cpuop_func_ce op_eff9_24_ff;
+extern cpuop_func_ce op_f000_24_nf;
+extern cpuop_func_ce op_f000_24_ff;
+extern cpuop_func_ce op_f008_24_nf;
+extern cpuop_func_ce op_f008_24_ff;
+extern cpuop_func_ce op_f010_24_nf;
+extern cpuop_func_ce op_f010_24_ff;
+extern cpuop_func_ce op_f018_24_nf;
+extern cpuop_func_ce op_f018_24_ff;
+extern cpuop_func_ce op_f020_24_nf;
+extern cpuop_func_ce op_f020_24_ff;
+extern cpuop_func_ce op_f028_24_nf;
+extern cpuop_func_ce op_f028_24_ff;
+extern cpuop_func_ce op_f030_24_nf;
+extern cpuop_func_ce op_f030_24_ff;
+extern cpuop_func_ce op_f038_24_nf;
+extern cpuop_func_ce op_f038_24_ff;
+extern cpuop_func_ce op_f039_24_nf;
+extern cpuop_func_ce op_f039_24_ff;
+extern cpuop_func_ce op_f200_24_nf;
+extern cpuop_func_ce op_f200_24_ff;
+extern cpuop_func_ce op_f208_24_nf;
+extern cpuop_func_ce op_f208_24_ff;
+extern cpuop_func_ce op_f210_24_nf;
+extern cpuop_func_ce op_f210_24_ff;
+extern cpuop_func_ce op_f218_24_nf;
+extern cpuop_func_ce op_f218_24_ff;
+extern cpuop_func_ce op_f220_24_nf;
+extern cpuop_func_ce op_f220_24_ff;
+extern cpuop_func_ce op_f228_24_nf;
+extern cpuop_func_ce op_f228_24_ff;
+extern cpuop_func_ce op_f230_24_nf;
+extern cpuop_func_ce op_f230_24_ff;
+extern cpuop_func_ce op_f238_24_nf;
+extern cpuop_func_ce op_f238_24_ff;
+extern cpuop_func_ce op_f239_24_nf;
+extern cpuop_func_ce op_f239_24_ff;
+extern cpuop_func_ce op_f23a_24_nf;
+extern cpuop_func_ce op_f23a_24_ff;
+extern cpuop_func_ce op_f23b_24_nf;
+extern cpuop_func_ce op_f23b_24_ff;
+extern cpuop_func_ce op_f23c_24_nf;
+extern cpuop_func_ce op_f23c_24_ff;
+extern cpuop_func_ce op_f240_24_nf;
+extern cpuop_func_ce op_f240_24_ff;
+extern cpuop_func_ce op_f248_24_nf;
+extern cpuop_func_ce op_f248_24_ff;
+extern cpuop_func_ce op_f250_24_nf;
+extern cpuop_func_ce op_f250_24_ff;
+extern cpuop_func_ce op_f258_24_nf;
+extern cpuop_func_ce op_f258_24_ff;
+extern cpuop_func_ce op_f260_24_nf;
+extern cpuop_func_ce op_f260_24_ff;
+extern cpuop_func_ce op_f268_24_nf;
+extern cpuop_func_ce op_f268_24_ff;
+extern cpuop_func_ce op_f270_24_nf;
+extern cpuop_func_ce op_f270_24_ff;
+extern cpuop_func_ce op_f278_24_nf;
+extern cpuop_func_ce op_f278_24_ff;
+extern cpuop_func_ce op_f279_24_nf;
+extern cpuop_func_ce op_f279_24_ff;
+extern cpuop_func_ce op_f27a_24_nf;
+extern cpuop_func_ce op_f27a_24_ff;
+extern cpuop_func_ce op_f27b_24_nf;
+extern cpuop_func_ce op_f27b_24_ff;
+extern cpuop_func_ce op_f27c_24_nf;
+extern cpuop_func_ce op_f27c_24_ff;
+extern cpuop_func_ce op_f280_24_nf;
+extern cpuop_func_ce op_f280_24_ff;
+extern cpuop_func_ce op_f2c0_24_nf;
+extern cpuop_func_ce op_f2c0_24_ff;
+extern cpuop_func_ce op_f310_24_nf;
+extern cpuop_func_ce op_f310_24_ff;
+extern cpuop_func_ce op_f320_24_nf;
+extern cpuop_func_ce op_f320_24_ff;
+extern cpuop_func_ce op_f328_24_nf;
+extern cpuop_func_ce op_f328_24_ff;
+extern cpuop_func_ce op_f330_24_nf;
+extern cpuop_func_ce op_f330_24_ff;
+extern cpuop_func_ce op_f338_24_nf;
+extern cpuop_func_ce op_f338_24_ff;
+extern cpuop_func_ce op_f339_24_nf;
+extern cpuop_func_ce op_f339_24_ff;
+extern cpuop_func_ce op_f350_24_nf;
+extern cpuop_func_ce op_f350_24_ff;
+extern cpuop_func_ce op_f358_24_nf;
+extern cpuop_func_ce op_f358_24_ff;
+extern cpuop_func_ce op_f368_24_nf;
+extern cpuop_func_ce op_f368_24_ff;
+extern cpuop_func_ce op_f370_24_nf;
+extern cpuop_func_ce op_f370_24_ff;
+extern cpuop_func_ce op_f378_24_nf;
+extern cpuop_func_ce op_f378_24_ff;
+extern cpuop_func_ce op_f379_24_nf;
+extern cpuop_func_ce op_f379_24_ff;
+extern cpuop_func_ce op_f37a_24_nf;
+extern cpuop_func_ce op_f37a_24_ff;
+extern cpuop_func_ce op_f37b_24_nf;
+extern cpuop_func_ce op_f37b_24_ff;
+extern cpuop_func_ce op_f408_24_nf;
+extern cpuop_func_ce op_f408_24_ff;
+extern cpuop_func_ce op_f410_24_nf;
+extern cpuop_func_ce op_f410_24_ff;
+extern cpuop_func_ce op_f418_24_nf;
+extern cpuop_func_ce op_f418_24_ff;
+extern cpuop_func_ce op_f419_24_nf;
+extern cpuop_func_ce op_f419_24_ff;
+extern cpuop_func_ce op_f41a_24_nf;
+extern cpuop_func_ce op_f41a_24_ff;
+extern cpuop_func_ce op_f41b_24_nf;
+extern cpuop_func_ce op_f41b_24_ff;
+extern cpuop_func_ce op_f41c_24_nf;
+extern cpuop_func_ce op_f41c_24_ff;
+extern cpuop_func_ce op_f41d_24_nf;
+extern cpuop_func_ce op_f41d_24_ff;
+extern cpuop_func_ce op_f41e_24_nf;
+extern cpuop_func_ce op_f41e_24_ff;
+extern cpuop_func_ce op_f41f_24_nf;
+extern cpuop_func_ce op_f41f_24_ff;
+extern cpuop_func_ce op_f428_24_nf;
+extern cpuop_func_ce op_f428_24_ff;
+extern cpuop_func_ce op_f430_24_nf;
+extern cpuop_func_ce op_f430_24_ff;
+extern cpuop_func_ce op_f438_24_nf;
+extern cpuop_func_ce op_f438_24_ff;
+extern cpuop_func_ce op_f439_24_nf;
+extern cpuop_func_ce op_f439_24_ff;
+extern cpuop_func_ce op_f43a_24_nf;
+extern cpuop_func_ce op_f43a_24_ff;
+extern cpuop_func_ce op_f43b_24_nf;
+extern cpuop_func_ce op_f43b_24_ff;
+extern cpuop_func_ce op_f43c_24_nf;
+extern cpuop_func_ce op_f43c_24_ff;
+extern cpuop_func_ce op_f43d_24_nf;
+extern cpuop_func_ce op_f43d_24_ff;
+extern cpuop_func_ce op_f43e_24_nf;
+extern cpuop_func_ce op_f43e_24_ff;
+extern cpuop_func_ce op_f43f_24_nf;
+extern cpuop_func_ce op_f43f_24_ff;
+extern cpuop_func_ce op_f500_24_nf;
+extern cpuop_func_ce op_f500_24_ff;
+extern cpuop_func_ce op_f508_24_nf;
+extern cpuop_func_ce op_f508_24_ff;
+extern cpuop_func_ce op_f510_24_nf;
+extern cpuop_func_ce op_f510_24_ff;
+extern cpuop_func_ce op_f518_24_nf;
+extern cpuop_func_ce op_f518_24_ff;
+extern cpuop_func_ce op_f548_24_nf;
+extern cpuop_func_ce op_f548_24_ff;
+extern cpuop_func_ce op_f568_24_nf;
+extern cpuop_func_ce op_f568_24_ff;
+extern cpuop_func_ce op_f588_24_nf;
+extern cpuop_func_ce op_f588_24_ff;
+extern cpuop_func_ce op_f5c8_24_nf;
+extern cpuop_func_ce op_f5c8_24_ff;
+extern cpuop_func_ce op_f600_24_nf;
+extern cpuop_func_ce op_f600_24_ff;
+extern cpuop_func_ce op_f608_24_nf;
+extern cpuop_func_ce op_f608_24_ff;
+extern cpuop_func_ce op_f610_24_nf;
+extern cpuop_func_ce op_f610_24_ff;
+extern cpuop_func_ce op_f618_24_nf;
+extern cpuop_func_ce op_f618_24_ff;
+extern cpuop_func_ce op_f620_24_nf;
+extern cpuop_func_ce op_f620_24_ff;
+extern cpuop_func_ce op_f800_24_nf;
+extern cpuop_func_ce op_f800_24_ff;
+extern cpuop_func op_0000_31_nf;
+extern cpuop_func op_0000_31_ff;
+extern cpuop_func op_0010_31_nf;
+extern cpuop_func op_0010_31_ff;
+extern cpuop_func op_0018_31_nf;
+extern cpuop_func op_0018_31_ff;
+extern cpuop_func op_0020_31_nf;
+extern cpuop_func op_0020_31_ff;
+extern cpuop_func op_0028_31_nf;
+extern cpuop_func op_0028_31_ff;
+extern cpuop_func op_0030_31_nf;
+extern cpuop_func op_0030_31_ff;
+extern cpuop_func op_0038_31_nf;
+extern cpuop_func op_0038_31_ff;
+extern cpuop_func op_0039_31_nf;
+extern cpuop_func op_0039_31_ff;
+extern cpuop_func op_003c_31_nf;
+extern cpuop_func op_003c_31_ff;
+extern cpuop_func op_0040_31_nf;
+extern cpuop_func op_0040_31_ff;
+extern cpuop_func op_0050_31_nf;
+extern cpuop_func op_0050_31_ff;
+extern cpuop_func op_0058_31_nf;
+extern cpuop_func op_0058_31_ff;
+extern cpuop_func op_0060_31_nf;
+extern cpuop_func op_0060_31_ff;
+extern cpuop_func op_0068_31_nf;
+extern cpuop_func op_0068_31_ff;
+extern cpuop_func op_0070_31_nf;
+extern cpuop_func op_0070_31_ff;
+extern cpuop_func op_0078_31_nf;
+extern cpuop_func op_0078_31_ff;
+extern cpuop_func op_0079_31_nf;
+extern cpuop_func op_0079_31_ff;
+extern cpuop_func op_007c_31_nf;
+extern cpuop_func op_007c_31_ff;
+extern cpuop_func op_0080_31_nf;
+extern cpuop_func op_0080_31_ff;
+extern cpuop_func op_0090_31_nf;
+extern cpuop_func op_0090_31_ff;
+extern cpuop_func op_0098_31_nf;
+extern cpuop_func op_0098_31_ff;
+extern cpuop_func op_00a0_31_nf;
+extern cpuop_func op_00a0_31_ff;
+extern cpuop_func op_00a8_31_nf;
+extern cpuop_func op_00a8_31_ff;
+extern cpuop_func op_00b0_31_nf;
+extern cpuop_func op_00b0_31_ff;
+extern cpuop_func op_00b8_31_nf;
+extern cpuop_func op_00b8_31_ff;
+extern cpuop_func op_00b9_31_nf;
+extern cpuop_func op_00b9_31_ff;
+extern cpuop_func op_00d0_31_nf;
+extern cpuop_func op_00d0_31_ff;
+extern cpuop_func op_00e8_31_nf;
+extern cpuop_func op_00e8_31_ff;
+extern cpuop_func op_00f0_31_nf;
+extern cpuop_func op_00f0_31_ff;
+extern cpuop_func op_00f8_31_nf;
+extern cpuop_func op_00f8_31_ff;
+extern cpuop_func op_00f9_31_nf;
+extern cpuop_func op_00f9_31_ff;
+extern cpuop_func op_00fa_31_nf;
+extern cpuop_func op_00fa_31_ff;
+extern cpuop_func op_00fb_31_nf;
+extern cpuop_func op_00fb_31_ff;
+extern cpuop_func op_0100_31_nf;
+extern cpuop_func op_0100_31_ff;
+extern cpuop_func op_0108_31_nf;
+extern cpuop_func op_0108_31_ff;
+extern cpuop_func op_0110_31_nf;
+extern cpuop_func op_0110_31_ff;
+extern cpuop_func op_0118_31_nf;
+extern cpuop_func op_0118_31_ff;
+extern cpuop_func op_0120_31_nf;
+extern cpuop_func op_0120_31_ff;
+extern cpuop_func op_0128_31_nf;
+extern cpuop_func op_0128_31_ff;
+extern cpuop_func op_0130_31_nf;
+extern cpuop_func op_0130_31_ff;
+extern cpuop_func op_0138_31_nf;
+extern cpuop_func op_0138_31_ff;
+extern cpuop_func op_0139_31_nf;
+extern cpuop_func op_0139_31_ff;
+extern cpuop_func op_013a_31_nf;
+extern cpuop_func op_013a_31_ff;
+extern cpuop_func op_013b_31_nf;
+extern cpuop_func op_013b_31_ff;
+extern cpuop_func op_013c_31_nf;
+extern cpuop_func op_013c_31_ff;
+extern cpuop_func op_0140_31_nf;
+extern cpuop_func op_0140_31_ff;
+extern cpuop_func op_0148_31_nf;
+extern cpuop_func op_0148_31_ff;
+extern cpuop_func op_0150_31_nf;
+extern cpuop_func op_0150_31_ff;
+extern cpuop_func op_0158_31_nf;
+extern cpuop_func op_0158_31_ff;
+extern cpuop_func op_0160_31_nf;
+extern cpuop_func op_0160_31_ff;
+extern cpuop_func op_0168_31_nf;
+extern cpuop_func op_0168_31_ff;
+extern cpuop_func op_0170_31_nf;
+extern cpuop_func op_0170_31_ff;
+extern cpuop_func op_0178_31_nf;
+extern cpuop_func op_0178_31_ff;
+extern cpuop_func op_0179_31_nf;
+extern cpuop_func op_0179_31_ff;
+extern cpuop_func op_0180_31_nf;
+extern cpuop_func op_0180_31_ff;
+extern cpuop_func op_0188_31_nf;
+extern cpuop_func op_0188_31_ff;
+extern cpuop_func op_0190_31_nf;
+extern cpuop_func op_0190_31_ff;
+extern cpuop_func op_0198_31_nf;
+extern cpuop_func op_0198_31_ff;
+extern cpuop_func op_01a0_31_nf;
+extern cpuop_func op_01a0_31_ff;
+extern cpuop_func op_01a8_31_nf;
+extern cpuop_func op_01a8_31_ff;
+extern cpuop_func op_01b0_31_nf;
+extern cpuop_func op_01b0_31_ff;
+extern cpuop_func op_01b8_31_nf;
+extern cpuop_func op_01b8_31_ff;
+extern cpuop_func op_01b9_31_nf;
+extern cpuop_func op_01b9_31_ff;
+extern cpuop_func op_01c0_31_nf;
+extern cpuop_func op_01c0_31_ff;
+extern cpuop_func op_01c8_31_nf;
+extern cpuop_func op_01c8_31_ff;
+extern cpuop_func op_01d0_31_nf;
+extern cpuop_func op_01d0_31_ff;
+extern cpuop_func op_01d8_31_nf;
+extern cpuop_func op_01d8_31_ff;
+extern cpuop_func op_01e0_31_nf;
+extern cpuop_func op_01e0_31_ff;
+extern cpuop_func op_01e8_31_nf;
+extern cpuop_func op_01e8_31_ff;
+extern cpuop_func op_01f0_31_nf;
+extern cpuop_func op_01f0_31_ff;
+extern cpuop_func op_01f8_31_nf;
+extern cpuop_func op_01f8_31_ff;
+extern cpuop_func op_01f9_31_nf;
+extern cpuop_func op_01f9_31_ff;
+extern cpuop_func op_0200_31_nf;
+extern cpuop_func op_0200_31_ff;
+extern cpuop_func op_0210_31_nf;
+extern cpuop_func op_0210_31_ff;
+extern cpuop_func op_0218_31_nf;
+extern cpuop_func op_0218_31_ff;
+extern cpuop_func op_0220_31_nf;
+extern cpuop_func op_0220_31_ff;
+extern cpuop_func op_0228_31_nf;
+extern cpuop_func op_0228_31_ff;
+extern cpuop_func op_0230_31_nf;
+extern cpuop_func op_0230_31_ff;
+extern cpuop_func op_0238_31_nf;
+extern cpuop_func op_0238_31_ff;
+extern cpuop_func op_0239_31_nf;
+extern cpuop_func op_0239_31_ff;
+extern cpuop_func op_023c_31_nf;
+extern cpuop_func op_023c_31_ff;
+extern cpuop_func op_0240_31_nf;
+extern cpuop_func op_0240_31_ff;
+extern cpuop_func op_0250_31_nf;
+extern cpuop_func op_0250_31_ff;
+extern cpuop_func op_0258_31_nf;
+extern cpuop_func op_0258_31_ff;
+extern cpuop_func op_0260_31_nf;
+extern cpuop_func op_0260_31_ff;
+extern cpuop_func op_0268_31_nf;
+extern cpuop_func op_0268_31_ff;
+extern cpuop_func op_0270_31_nf;
+extern cpuop_func op_0270_31_ff;
+extern cpuop_func op_0278_31_nf;
+extern cpuop_func op_0278_31_ff;
+extern cpuop_func op_0279_31_nf;
+extern cpuop_func op_0279_31_ff;
+extern cpuop_func op_027c_31_nf;
+extern cpuop_func op_027c_31_ff;
+extern cpuop_func op_0280_31_nf;
+extern cpuop_func op_0280_31_ff;
+extern cpuop_func op_0290_31_nf;
+extern cpuop_func op_0290_31_ff;
+extern cpuop_func op_0298_31_nf;
+extern cpuop_func op_0298_31_ff;
+extern cpuop_func op_02a0_31_nf;
+extern cpuop_func op_02a0_31_ff;
+extern cpuop_func op_02a8_31_nf;
+extern cpuop_func op_02a8_31_ff;
+extern cpuop_func op_02b0_31_nf;
+extern cpuop_func op_02b0_31_ff;
+extern cpuop_func op_02b8_31_nf;
+extern cpuop_func op_02b8_31_ff;
+extern cpuop_func op_02b9_31_nf;
+extern cpuop_func op_02b9_31_ff;
+extern cpuop_func op_02d0_31_nf;
+extern cpuop_func op_02d0_31_ff;
+extern cpuop_func op_02e8_31_nf;
+extern cpuop_func op_02e8_31_ff;
+extern cpuop_func op_02f0_31_nf;
+extern cpuop_func op_02f0_31_ff;
+extern cpuop_func op_02f8_31_nf;
+extern cpuop_func op_02f8_31_ff;
+extern cpuop_func op_02f9_31_nf;
+extern cpuop_func op_02f9_31_ff;
+extern cpuop_func op_02fa_31_nf;
+extern cpuop_func op_02fa_31_ff;
+extern cpuop_func op_02fb_31_nf;
+extern cpuop_func op_02fb_31_ff;
+extern cpuop_func op_0400_31_nf;
+extern cpuop_func op_0400_31_ff;
+extern cpuop_func op_0410_31_nf;
+extern cpuop_func op_0410_31_ff;
+extern cpuop_func op_0418_31_nf;
+extern cpuop_func op_0418_31_ff;
+extern cpuop_func op_0420_31_nf;
+extern cpuop_func op_0420_31_ff;
+extern cpuop_func op_0428_31_nf;
+extern cpuop_func op_0428_31_ff;
+extern cpuop_func op_0430_31_nf;
+extern cpuop_func op_0430_31_ff;
+extern cpuop_func op_0438_31_nf;
+extern cpuop_func op_0438_31_ff;
+extern cpuop_func op_0439_31_nf;
+extern cpuop_func op_0439_31_ff;
+extern cpuop_func op_0440_31_nf;
+extern cpuop_func op_0440_31_ff;
+extern cpuop_func op_0450_31_nf;
+extern cpuop_func op_0450_31_ff;
+extern cpuop_func op_0458_31_nf;
+extern cpuop_func op_0458_31_ff;
+extern cpuop_func op_0460_31_nf;
+extern cpuop_func op_0460_31_ff;
+extern cpuop_func op_0468_31_nf;
+extern cpuop_func op_0468_31_ff;
+extern cpuop_func op_0470_31_nf;
+extern cpuop_func op_0470_31_ff;
+extern cpuop_func op_0478_31_nf;
+extern cpuop_func op_0478_31_ff;
+extern cpuop_func op_0479_31_nf;
+extern cpuop_func op_0479_31_ff;
+extern cpuop_func op_0480_31_nf;
+extern cpuop_func op_0480_31_ff;
+extern cpuop_func op_0490_31_nf;
+extern cpuop_func op_0490_31_ff;
+extern cpuop_func op_0498_31_nf;
+extern cpuop_func op_0498_31_ff;
+extern cpuop_func op_04a0_31_nf;
+extern cpuop_func op_04a0_31_ff;
+extern cpuop_func op_04a8_31_nf;
+extern cpuop_func op_04a8_31_ff;
+extern cpuop_func op_04b0_31_nf;
+extern cpuop_func op_04b0_31_ff;
+extern cpuop_func op_04b8_31_nf;
+extern cpuop_func op_04b8_31_ff;
+extern cpuop_func op_04b9_31_nf;
+extern cpuop_func op_04b9_31_ff;
+extern cpuop_func op_04d0_31_nf;
+extern cpuop_func op_04d0_31_ff;
+extern cpuop_func op_04e8_31_nf;
+extern cpuop_func op_04e8_31_ff;
+extern cpuop_func op_04f0_31_nf;
+extern cpuop_func op_04f0_31_ff;
+extern cpuop_func op_04f8_31_nf;
+extern cpuop_func op_04f8_31_ff;
+extern cpuop_func op_04f9_31_nf;
+extern cpuop_func op_04f9_31_ff;
+extern cpuop_func op_04fa_31_nf;
+extern cpuop_func op_04fa_31_ff;
+extern cpuop_func op_04fb_31_nf;
+extern cpuop_func op_04fb_31_ff;
+extern cpuop_func op_0600_31_nf;
+extern cpuop_func op_0600_31_ff;
+extern cpuop_func op_0610_31_nf;
+extern cpuop_func op_0610_31_ff;
+extern cpuop_func op_0618_31_nf;
+extern cpuop_func op_0618_31_ff;
+extern cpuop_func op_0620_31_nf;
+extern cpuop_func op_0620_31_ff;
+extern cpuop_func op_0628_31_nf;
+extern cpuop_func op_0628_31_ff;
+extern cpuop_func op_0630_31_nf;
+extern cpuop_func op_0630_31_ff;
+extern cpuop_func op_0638_31_nf;
+extern cpuop_func op_0638_31_ff;
+extern cpuop_func op_0639_31_nf;
+extern cpuop_func op_0639_31_ff;
+extern cpuop_func op_0640_31_nf;
+extern cpuop_func op_0640_31_ff;
+extern cpuop_func op_0650_31_nf;
+extern cpuop_func op_0650_31_ff;
+extern cpuop_func op_0658_31_nf;
+extern cpuop_func op_0658_31_ff;
+extern cpuop_func op_0660_31_nf;
+extern cpuop_func op_0660_31_ff;
+extern cpuop_func op_0668_31_nf;
+extern cpuop_func op_0668_31_ff;
+extern cpuop_func op_0670_31_nf;
+extern cpuop_func op_0670_31_ff;
+extern cpuop_func op_0678_31_nf;
+extern cpuop_func op_0678_31_ff;
+extern cpuop_func op_0679_31_nf;
+extern cpuop_func op_0679_31_ff;
+extern cpuop_func op_0680_31_nf;
+extern cpuop_func op_0680_31_ff;
+extern cpuop_func op_0690_31_nf;
+extern cpuop_func op_0690_31_ff;
+extern cpuop_func op_0698_31_nf;
+extern cpuop_func op_0698_31_ff;
+extern cpuop_func op_06a0_31_nf;
+extern cpuop_func op_06a0_31_ff;
+extern cpuop_func op_06a8_31_nf;
+extern cpuop_func op_06a8_31_ff;
+extern cpuop_func op_06b0_31_nf;
+extern cpuop_func op_06b0_31_ff;
+extern cpuop_func op_06b8_31_nf;
+extern cpuop_func op_06b8_31_ff;
+extern cpuop_func op_06b9_31_nf;
+extern cpuop_func op_06b9_31_ff;
+extern cpuop_func op_06c0_31_nf;
+extern cpuop_func op_06c0_31_ff;
+extern cpuop_func op_06c8_31_nf;
+extern cpuop_func op_06c8_31_ff;
+extern cpuop_func op_06d0_31_nf;
+extern cpuop_func op_06d0_31_ff;
+extern cpuop_func op_06e8_31_nf;
+extern cpuop_func op_06e8_31_ff;
+extern cpuop_func op_06f0_31_nf;
+extern cpuop_func op_06f0_31_ff;
+extern cpuop_func op_06f8_31_nf;
+extern cpuop_func op_06f8_31_ff;
+extern cpuop_func op_06f9_31_nf;
+extern cpuop_func op_06f9_31_ff;
+extern cpuop_func op_06fa_31_nf;
+extern cpuop_func op_06fa_31_ff;
+extern cpuop_func op_06fb_31_nf;
+extern cpuop_func op_06fb_31_ff;
+extern cpuop_func op_0800_31_nf;
+extern cpuop_func op_0800_31_ff;
+extern cpuop_func op_0810_31_nf;
+extern cpuop_func op_0810_31_ff;
+extern cpuop_func op_0818_31_nf;
+extern cpuop_func op_0818_31_ff;
+extern cpuop_func op_0820_31_nf;
+extern cpuop_func op_0820_31_ff;
+extern cpuop_func op_0828_31_nf;
+extern cpuop_func op_0828_31_ff;
+extern cpuop_func op_0830_31_nf;
+extern cpuop_func op_0830_31_ff;
+extern cpuop_func op_0838_31_nf;
+extern cpuop_func op_0838_31_ff;
+extern cpuop_func op_0839_31_nf;
+extern cpuop_func op_0839_31_ff;
+extern cpuop_func op_083a_31_nf;
+extern cpuop_func op_083a_31_ff;
+extern cpuop_func op_083b_31_nf;
+extern cpuop_func op_083b_31_ff;
+extern cpuop_func op_0840_31_nf;
+extern cpuop_func op_0840_31_ff;
+extern cpuop_func op_0850_31_nf;
+extern cpuop_func op_0850_31_ff;
+extern cpuop_func op_0858_31_nf;
+extern cpuop_func op_0858_31_ff;
+extern cpuop_func op_0860_31_nf;
+extern cpuop_func op_0860_31_ff;
+extern cpuop_func op_0868_31_nf;
+extern cpuop_func op_0868_31_ff;
+extern cpuop_func op_0870_31_nf;
+extern cpuop_func op_0870_31_ff;
+extern cpuop_func op_0878_31_nf;
+extern cpuop_func op_0878_31_ff;
+extern cpuop_func op_0879_31_nf;
+extern cpuop_func op_0879_31_ff;
+extern cpuop_func op_0880_31_nf;
+extern cpuop_func op_0880_31_ff;
+extern cpuop_func op_0890_31_nf;
+extern cpuop_func op_0890_31_ff;
+extern cpuop_func op_0898_31_nf;
+extern cpuop_func op_0898_31_ff;
+extern cpuop_func op_08a0_31_nf;
+extern cpuop_func op_08a0_31_ff;
+extern cpuop_func op_08a8_31_nf;
+extern cpuop_func op_08a8_31_ff;
+extern cpuop_func op_08b0_31_nf;
+extern cpuop_func op_08b0_31_ff;
+extern cpuop_func op_08b8_31_nf;
+extern cpuop_func op_08b8_31_ff;
+extern cpuop_func op_08b9_31_nf;
+extern cpuop_func op_08b9_31_ff;
+extern cpuop_func op_08c0_31_nf;
+extern cpuop_func op_08c0_31_ff;
+extern cpuop_func op_08d0_31_nf;
+extern cpuop_func op_08d0_31_ff;
+extern cpuop_func op_08d8_31_nf;
+extern cpuop_func op_08d8_31_ff;
+extern cpuop_func op_08e0_31_nf;
+extern cpuop_func op_08e0_31_ff;
+extern cpuop_func op_08e8_31_nf;
+extern cpuop_func op_08e8_31_ff;
+extern cpuop_func op_08f0_31_nf;
+extern cpuop_func op_08f0_31_ff;
+extern cpuop_func op_08f8_31_nf;
+extern cpuop_func op_08f8_31_ff;
+extern cpuop_func op_08f9_31_nf;
+extern cpuop_func op_08f9_31_ff;
+extern cpuop_func op_0a00_31_nf;
+extern cpuop_func op_0a00_31_ff;
+extern cpuop_func op_0a10_31_nf;
+extern cpuop_func op_0a10_31_ff;
+extern cpuop_func op_0a18_31_nf;
+extern cpuop_func op_0a18_31_ff;
+extern cpuop_func op_0a20_31_nf;
+extern cpuop_func op_0a20_31_ff;
+extern cpuop_func op_0a28_31_nf;
+extern cpuop_func op_0a28_31_ff;
+extern cpuop_func op_0a30_31_nf;
+extern cpuop_func op_0a30_31_ff;
+extern cpuop_func op_0a38_31_nf;
+extern cpuop_func op_0a38_31_ff;
+extern cpuop_func op_0a39_31_nf;
+extern cpuop_func op_0a39_31_ff;
+extern cpuop_func op_0a3c_31_nf;
+extern cpuop_func op_0a3c_31_ff;
+extern cpuop_func op_0a40_31_nf;
+extern cpuop_func op_0a40_31_ff;
+extern cpuop_func op_0a50_31_nf;
+extern cpuop_func op_0a50_31_ff;
+extern cpuop_func op_0a58_31_nf;
+extern cpuop_func op_0a58_31_ff;
+extern cpuop_func op_0a60_31_nf;
+extern cpuop_func op_0a60_31_ff;
+extern cpuop_func op_0a68_31_nf;
+extern cpuop_func op_0a68_31_ff;
+extern cpuop_func op_0a70_31_nf;
+extern cpuop_func op_0a70_31_ff;
+extern cpuop_func op_0a78_31_nf;
+extern cpuop_func op_0a78_31_ff;
+extern cpuop_func op_0a79_31_nf;
+extern cpuop_func op_0a79_31_ff;
+extern cpuop_func op_0a7c_31_nf;
+extern cpuop_func op_0a7c_31_ff;
+extern cpuop_func op_0a80_31_nf;
+extern cpuop_func op_0a80_31_ff;
+extern cpuop_func op_0a90_31_nf;
+extern cpuop_func op_0a90_31_ff;
+extern cpuop_func op_0a98_31_nf;
+extern cpuop_func op_0a98_31_ff;
+extern cpuop_func op_0aa0_31_nf;
+extern cpuop_func op_0aa0_31_ff;
+extern cpuop_func op_0aa8_31_nf;
+extern cpuop_func op_0aa8_31_ff;
+extern cpuop_func op_0ab0_31_nf;
+extern cpuop_func op_0ab0_31_ff;
+extern cpuop_func op_0ab8_31_nf;
+extern cpuop_func op_0ab8_31_ff;
+extern cpuop_func op_0ab9_31_nf;
+extern cpuop_func op_0ab9_31_ff;
+extern cpuop_func op_0ad0_31_nf;
+extern cpuop_func op_0ad0_31_ff;
+extern cpuop_func op_0ad8_31_nf;
+extern cpuop_func op_0ad8_31_ff;
+extern cpuop_func op_0ae0_31_nf;
+extern cpuop_func op_0ae0_31_ff;
+extern cpuop_func op_0ae8_31_nf;
+extern cpuop_func op_0ae8_31_ff;
+extern cpuop_func op_0af0_31_nf;
+extern cpuop_func op_0af0_31_ff;
+extern cpuop_func op_0af8_31_nf;
+extern cpuop_func op_0af8_31_ff;
+extern cpuop_func op_0af9_31_nf;
+extern cpuop_func op_0af9_31_ff;
+extern cpuop_func op_0c00_31_nf;
+extern cpuop_func op_0c00_31_ff;
+extern cpuop_func op_0c10_31_nf;
+extern cpuop_func op_0c10_31_ff;
+extern cpuop_func op_0c18_31_nf;
+extern cpuop_func op_0c18_31_ff;
+extern cpuop_func op_0c20_31_nf;
+extern cpuop_func op_0c20_31_ff;
+extern cpuop_func op_0c28_31_nf;
+extern cpuop_func op_0c28_31_ff;
+extern cpuop_func op_0c30_31_nf;
+extern cpuop_func op_0c30_31_ff;
+extern cpuop_func op_0c38_31_nf;
+extern cpuop_func op_0c38_31_ff;
+extern cpuop_func op_0c39_31_nf;
+extern cpuop_func op_0c39_31_ff;
+extern cpuop_func op_0c3a_31_nf;
+extern cpuop_func op_0c3a_31_ff;
+extern cpuop_func op_0c3b_31_nf;
+extern cpuop_func op_0c3b_31_ff;
+extern cpuop_func op_0c40_31_nf;
+extern cpuop_func op_0c40_31_ff;
+extern cpuop_func op_0c50_31_nf;
+extern cpuop_func op_0c50_31_ff;
+extern cpuop_func op_0c58_31_nf;
+extern cpuop_func op_0c58_31_ff;
+extern cpuop_func op_0c60_31_nf;
+extern cpuop_func op_0c60_31_ff;
+extern cpuop_func op_0c68_31_nf;
+extern cpuop_func op_0c68_31_ff;
+extern cpuop_func op_0c70_31_nf;
+extern cpuop_func op_0c70_31_ff;
+extern cpuop_func op_0c78_31_nf;
+extern cpuop_func op_0c78_31_ff;
+extern cpuop_func op_0c79_31_nf;
+extern cpuop_func op_0c79_31_ff;
+extern cpuop_func op_0c7a_31_nf;
+extern cpuop_func op_0c7a_31_ff;
+extern cpuop_func op_0c7b_31_nf;
+extern cpuop_func op_0c7b_31_ff;
+extern cpuop_func op_0c80_31_nf;
+extern cpuop_func op_0c80_31_ff;
+extern cpuop_func op_0c90_31_nf;
+extern cpuop_func op_0c90_31_ff;
+extern cpuop_func op_0c98_31_nf;
+extern cpuop_func op_0c98_31_ff;
+extern cpuop_func op_0ca0_31_nf;
+extern cpuop_func op_0ca0_31_ff;
+extern cpuop_func op_0ca8_31_nf;
+extern cpuop_func op_0ca8_31_ff;
+extern cpuop_func op_0cb0_31_nf;
+extern cpuop_func op_0cb0_31_ff;
+extern cpuop_func op_0cb8_31_nf;
+extern cpuop_func op_0cb8_31_ff;
+extern cpuop_func op_0cb9_31_nf;
+extern cpuop_func op_0cb9_31_ff;
+extern cpuop_func op_0cba_31_nf;
+extern cpuop_func op_0cba_31_ff;
+extern cpuop_func op_0cbb_31_nf;
+extern cpuop_func op_0cbb_31_ff;
+extern cpuop_func op_0cd0_31_nf;
+extern cpuop_func op_0cd0_31_ff;
+extern cpuop_func op_0cd8_31_nf;
+extern cpuop_func op_0cd8_31_ff;
+extern cpuop_func op_0ce0_31_nf;
+extern cpuop_func op_0ce0_31_ff;
+extern cpuop_func op_0ce8_31_nf;
+extern cpuop_func op_0ce8_31_ff;
+extern cpuop_func op_0cf0_31_nf;
+extern cpuop_func op_0cf0_31_ff;
+extern cpuop_func op_0cf8_31_nf;
+extern cpuop_func op_0cf8_31_ff;
+extern cpuop_func op_0cf9_31_nf;
+extern cpuop_func op_0cf9_31_ff;
+extern cpuop_func op_0cfc_31_nf;
+extern cpuop_func op_0cfc_31_ff;
+extern cpuop_func op_0e10_31_nf;
+extern cpuop_func op_0e10_31_ff;
+extern cpuop_func op_0e18_31_nf;
+extern cpuop_func op_0e18_31_ff;
+extern cpuop_func op_0e20_31_nf;
+extern cpuop_func op_0e20_31_ff;
+extern cpuop_func op_0e28_31_nf;
+extern cpuop_func op_0e28_31_ff;
+extern cpuop_func op_0e30_31_nf;
+extern cpuop_func op_0e30_31_ff;
+extern cpuop_func op_0e38_31_nf;
+extern cpuop_func op_0e38_31_ff;
+extern cpuop_func op_0e39_31_nf;
+extern cpuop_func op_0e39_31_ff;
+extern cpuop_func op_0e50_31_nf;
+extern cpuop_func op_0e50_31_ff;
+extern cpuop_func op_0e58_31_nf;
+extern cpuop_func op_0e58_31_ff;
+extern cpuop_func op_0e60_31_nf;
+extern cpuop_func op_0e60_31_ff;
+extern cpuop_func op_0e68_31_nf;
+extern cpuop_func op_0e68_31_ff;
+extern cpuop_func op_0e70_31_nf;
+extern cpuop_func op_0e70_31_ff;
+extern cpuop_func op_0e78_31_nf;
+extern cpuop_func op_0e78_31_ff;
+extern cpuop_func op_0e79_31_nf;
+extern cpuop_func op_0e79_31_ff;
+extern cpuop_func op_0e90_31_nf;
+extern cpuop_func op_0e90_31_ff;
+extern cpuop_func op_0e98_31_nf;
+extern cpuop_func op_0e98_31_ff;
+extern cpuop_func op_0ea0_31_nf;
+extern cpuop_func op_0ea0_31_ff;
+extern cpuop_func op_0ea8_31_nf;
+extern cpuop_func op_0ea8_31_ff;
+extern cpuop_func op_0eb0_31_nf;
+extern cpuop_func op_0eb0_31_ff;
+extern cpuop_func op_0eb8_31_nf;
+extern cpuop_func op_0eb8_31_ff;
+extern cpuop_func op_0eb9_31_nf;
+extern cpuop_func op_0eb9_31_ff;
+extern cpuop_func op_0ed0_31_nf;
+extern cpuop_func op_0ed0_31_ff;
+extern cpuop_func op_0ed8_31_nf;
+extern cpuop_func op_0ed8_31_ff;
+extern cpuop_func op_0ee0_31_nf;
+extern cpuop_func op_0ee0_31_ff;
+extern cpuop_func op_0ee8_31_nf;
+extern cpuop_func op_0ee8_31_ff;
+extern cpuop_func op_0ef0_31_nf;
+extern cpuop_func op_0ef0_31_ff;
+extern cpuop_func op_0ef8_31_nf;
+extern cpuop_func op_0ef8_31_ff;
+extern cpuop_func op_0ef9_31_nf;
+extern cpuop_func op_0ef9_31_ff;
+extern cpuop_func op_0efc_31_nf;
+extern cpuop_func op_0efc_31_ff;
+extern cpuop_func op_1000_31_nf;
+extern cpuop_func op_1000_31_ff;
+extern cpuop_func op_1010_31_nf;
+extern cpuop_func op_1010_31_ff;
+extern cpuop_func op_1018_31_nf;
+extern cpuop_func op_1018_31_ff;
+extern cpuop_func op_1020_31_nf;
+extern cpuop_func op_1020_31_ff;
+extern cpuop_func op_1028_31_nf;
+extern cpuop_func op_1028_31_ff;
+extern cpuop_func op_1030_31_nf;
+extern cpuop_func op_1030_31_ff;
+extern cpuop_func op_1038_31_nf;
+extern cpuop_func op_1038_31_ff;
+extern cpuop_func op_1039_31_nf;
+extern cpuop_func op_1039_31_ff;
+extern cpuop_func op_103a_31_nf;
+extern cpuop_func op_103a_31_ff;
+extern cpuop_func op_103b_31_nf;
+extern cpuop_func op_103b_31_ff;
+extern cpuop_func op_103c_31_nf;
+extern cpuop_func op_103c_31_ff;
+extern cpuop_func op_1080_31_nf;
+extern cpuop_func op_1080_31_ff;
+extern cpuop_func op_1090_31_nf;
+extern cpuop_func op_1090_31_ff;
+extern cpuop_func op_1098_31_nf;
+extern cpuop_func op_1098_31_ff;
+extern cpuop_func op_10a0_31_nf;
+extern cpuop_func op_10a0_31_ff;
+extern cpuop_func op_10a8_31_nf;
+extern cpuop_func op_10a8_31_ff;
+extern cpuop_func op_10b0_31_nf;
+extern cpuop_func op_10b0_31_ff;
+extern cpuop_func op_10b8_31_nf;
+extern cpuop_func op_10b8_31_ff;
+extern cpuop_func op_10b9_31_nf;
+extern cpuop_func op_10b9_31_ff;
+extern cpuop_func op_10ba_31_nf;
+extern cpuop_func op_10ba_31_ff;
+extern cpuop_func op_10bb_31_nf;
+extern cpuop_func op_10bb_31_ff;
+extern cpuop_func op_10bc_31_nf;
+extern cpuop_func op_10bc_31_ff;
+extern cpuop_func op_10c0_31_nf;
+extern cpuop_func op_10c0_31_ff;
+extern cpuop_func op_10d0_31_nf;
+extern cpuop_func op_10d0_31_ff;
+extern cpuop_func op_10d8_31_nf;
+extern cpuop_func op_10d8_31_ff;
+extern cpuop_func op_10e0_31_nf;
+extern cpuop_func op_10e0_31_ff;
+extern cpuop_func op_10e8_31_nf;
+extern cpuop_func op_10e8_31_ff;
+extern cpuop_func op_10f0_31_nf;
+extern cpuop_func op_10f0_31_ff;
+extern cpuop_func op_10f8_31_nf;
+extern cpuop_func op_10f8_31_ff;
+extern cpuop_func op_10f9_31_nf;
+extern cpuop_func op_10f9_31_ff;
+extern cpuop_func op_10fa_31_nf;
+extern cpuop_func op_10fa_31_ff;
+extern cpuop_func op_10fb_31_nf;
+extern cpuop_func op_10fb_31_ff;
+extern cpuop_func op_10fc_31_nf;
+extern cpuop_func op_10fc_31_ff;
+extern cpuop_func op_1100_31_nf;
+extern cpuop_func op_1100_31_ff;
+extern cpuop_func op_1110_31_nf;
+extern cpuop_func op_1110_31_ff;
+extern cpuop_func op_1118_31_nf;
+extern cpuop_func op_1118_31_ff;
+extern cpuop_func op_1120_31_nf;
+extern cpuop_func op_1120_31_ff;
+extern cpuop_func op_1128_31_nf;
+extern cpuop_func op_1128_31_ff;
+extern cpuop_func op_1130_31_nf;
+extern cpuop_func op_1130_31_ff;
+extern cpuop_func op_1138_31_nf;
+extern cpuop_func op_1138_31_ff;
+extern cpuop_func op_1139_31_nf;
+extern cpuop_func op_1139_31_ff;
+extern cpuop_func op_113a_31_nf;
+extern cpuop_func op_113a_31_ff;
+extern cpuop_func op_113b_31_nf;
+extern cpuop_func op_113b_31_ff;
+extern cpuop_func op_113c_31_nf;
+extern cpuop_func op_113c_31_ff;
+extern cpuop_func op_1140_31_nf;
+extern cpuop_func op_1140_31_ff;
+extern cpuop_func op_1150_31_nf;
+extern cpuop_func op_1150_31_ff;
+extern cpuop_func op_1158_31_nf;
+extern cpuop_func op_1158_31_ff;
+extern cpuop_func op_1160_31_nf;
+extern cpuop_func op_1160_31_ff;
+extern cpuop_func op_1168_31_nf;
+extern cpuop_func op_1168_31_ff;
+extern cpuop_func op_1170_31_nf;
+extern cpuop_func op_1170_31_ff;
+extern cpuop_func op_1178_31_nf;
+extern cpuop_func op_1178_31_ff;
+extern cpuop_func op_1179_31_nf;
+extern cpuop_func op_1179_31_ff;
+extern cpuop_func op_117a_31_nf;
+extern cpuop_func op_117a_31_ff;
+extern cpuop_func op_117b_31_nf;
+extern cpuop_func op_117b_31_ff;
+extern cpuop_func op_117c_31_nf;
+extern cpuop_func op_117c_31_ff;
+extern cpuop_func op_1180_31_nf;
+extern cpuop_func op_1180_31_ff;
+extern cpuop_func op_1190_31_nf;
+extern cpuop_func op_1190_31_ff;
+extern cpuop_func op_1198_31_nf;
+extern cpuop_func op_1198_31_ff;
+extern cpuop_func op_11a0_31_nf;
+extern cpuop_func op_11a0_31_ff;
+extern cpuop_func op_11a8_31_nf;
+extern cpuop_func op_11a8_31_ff;
+extern cpuop_func op_11b0_31_nf;
+extern cpuop_func op_11b0_31_ff;
+extern cpuop_func op_11b8_31_nf;
+extern cpuop_func op_11b8_31_ff;
+extern cpuop_func op_11b9_31_nf;
+extern cpuop_func op_11b9_31_ff;
+extern cpuop_func op_11ba_31_nf;
+extern cpuop_func op_11ba_31_ff;
+extern cpuop_func op_11bb_31_nf;
+extern cpuop_func op_11bb_31_ff;
+extern cpuop_func op_11bc_31_nf;
+extern cpuop_func op_11bc_31_ff;
+extern cpuop_func op_11c0_31_nf;
+extern cpuop_func op_11c0_31_ff;
+extern cpuop_func op_11d0_31_nf;
+extern cpuop_func op_11d0_31_ff;
+extern cpuop_func op_11d8_31_nf;
+extern cpuop_func op_11d8_31_ff;
+extern cpuop_func op_11e0_31_nf;
+extern cpuop_func op_11e0_31_ff;
+extern cpuop_func op_11e8_31_nf;
+extern cpuop_func op_11e8_31_ff;
+extern cpuop_func op_11f0_31_nf;
+extern cpuop_func op_11f0_31_ff;
+extern cpuop_func op_11f8_31_nf;
+extern cpuop_func op_11f8_31_ff;
+extern cpuop_func op_11f9_31_nf;
+extern cpuop_func op_11f9_31_ff;
+extern cpuop_func op_11fa_31_nf;
+extern cpuop_func op_11fa_31_ff;
+extern cpuop_func op_11fb_31_nf;
+extern cpuop_func op_11fb_31_ff;
+extern cpuop_func op_11fc_31_nf;
+extern cpuop_func op_11fc_31_ff;
+extern cpuop_func op_13c0_31_nf;
+extern cpuop_func op_13c0_31_ff;
+extern cpuop_func op_13d0_31_nf;
+extern cpuop_func op_13d0_31_ff;
+extern cpuop_func op_13d8_31_nf;
+extern cpuop_func op_13d8_31_ff;
+extern cpuop_func op_13e0_31_nf;
+extern cpuop_func op_13e0_31_ff;
+extern cpuop_func op_13e8_31_nf;
+extern cpuop_func op_13e8_31_ff;
+extern cpuop_func op_13f0_31_nf;
+extern cpuop_func op_13f0_31_ff;
+extern cpuop_func op_13f8_31_nf;
+extern cpuop_func op_13f8_31_ff;
+extern cpuop_func op_13f9_31_nf;
+extern cpuop_func op_13f9_31_ff;
+extern cpuop_func op_13fa_31_nf;
+extern cpuop_func op_13fa_31_ff;
+extern cpuop_func op_13fb_31_nf;
+extern cpuop_func op_13fb_31_ff;
+extern cpuop_func op_13fc_31_nf;
+extern cpuop_func op_13fc_31_ff;
+extern cpuop_func op_2000_31_nf;
+extern cpuop_func op_2000_31_ff;
+extern cpuop_func op_2008_31_nf;
+extern cpuop_func op_2008_31_ff;
+extern cpuop_func op_2010_31_nf;
+extern cpuop_func op_2010_31_ff;
+extern cpuop_func op_2018_31_nf;
+extern cpuop_func op_2018_31_ff;
+extern cpuop_func op_2020_31_nf;
+extern cpuop_func op_2020_31_ff;
+extern cpuop_func op_2028_31_nf;
+extern cpuop_func op_2028_31_ff;
+extern cpuop_func op_2030_31_nf;
+extern cpuop_func op_2030_31_ff;
+extern cpuop_func op_2038_31_nf;
+extern cpuop_func op_2038_31_ff;
+extern cpuop_func op_2039_31_nf;
+extern cpuop_func op_2039_31_ff;
+extern cpuop_func op_203a_31_nf;
+extern cpuop_func op_203a_31_ff;
+extern cpuop_func op_203b_31_nf;
+extern cpuop_func op_203b_31_ff;
+extern cpuop_func op_203c_31_nf;
+extern cpuop_func op_203c_31_ff;
+extern cpuop_func op_2040_31_nf;
+extern cpuop_func op_2040_31_ff;
+extern cpuop_func op_2048_31_nf;
+extern cpuop_func op_2048_31_ff;
+extern cpuop_func op_2050_31_nf;
+extern cpuop_func op_2050_31_ff;
+extern cpuop_func op_2058_31_nf;
+extern cpuop_func op_2058_31_ff;
+extern cpuop_func op_2060_31_nf;
+extern cpuop_func op_2060_31_ff;
+extern cpuop_func op_2068_31_nf;
+extern cpuop_func op_2068_31_ff;
+extern cpuop_func op_2070_31_nf;
+extern cpuop_func op_2070_31_ff;
+extern cpuop_func op_2078_31_nf;
+extern cpuop_func op_2078_31_ff;
+extern cpuop_func op_2079_31_nf;
+extern cpuop_func op_2079_31_ff;
+extern cpuop_func op_207a_31_nf;
+extern cpuop_func op_207a_31_ff;
+extern cpuop_func op_207b_31_nf;
+extern cpuop_func op_207b_31_ff;
+extern cpuop_func op_207c_31_nf;
+extern cpuop_func op_207c_31_ff;
+extern cpuop_func op_2080_31_nf;
+extern cpuop_func op_2080_31_ff;
+extern cpuop_func op_2088_31_nf;
+extern cpuop_func op_2088_31_ff;
+extern cpuop_func op_2090_31_nf;
+extern cpuop_func op_2090_31_ff;
+extern cpuop_func op_2098_31_nf;
+extern cpuop_func op_2098_31_ff;
+extern cpuop_func op_20a0_31_nf;
+extern cpuop_func op_20a0_31_ff;
+extern cpuop_func op_20a8_31_nf;
+extern cpuop_func op_20a8_31_ff;
+extern cpuop_func op_20b0_31_nf;
+extern cpuop_func op_20b0_31_ff;
+extern cpuop_func op_20b8_31_nf;
+extern cpuop_func op_20b8_31_ff;
+extern cpuop_func op_20b9_31_nf;
+extern cpuop_func op_20b9_31_ff;
+extern cpuop_func op_20ba_31_nf;
+extern cpuop_func op_20ba_31_ff;
+extern cpuop_func op_20bb_31_nf;
+extern cpuop_func op_20bb_31_ff;
+extern cpuop_func op_20bc_31_nf;
+extern cpuop_func op_20bc_31_ff;
+extern cpuop_func op_20c0_31_nf;
+extern cpuop_func op_20c0_31_ff;
+extern cpuop_func op_20c8_31_nf;
+extern cpuop_func op_20c8_31_ff;
+extern cpuop_func op_20d0_31_nf;
+extern cpuop_func op_20d0_31_ff;
+extern cpuop_func op_20d8_31_nf;
+extern cpuop_func op_20d8_31_ff;
+extern cpuop_func op_20e0_31_nf;
+extern cpuop_func op_20e0_31_ff;
+extern cpuop_func op_20e8_31_nf;
+extern cpuop_func op_20e8_31_ff;
+extern cpuop_func op_20f0_31_nf;
+extern cpuop_func op_20f0_31_ff;
+extern cpuop_func op_20f8_31_nf;
+extern cpuop_func op_20f8_31_ff;
+extern cpuop_func op_20f9_31_nf;
+extern cpuop_func op_20f9_31_ff;
+extern cpuop_func op_20fa_31_nf;
+extern cpuop_func op_20fa_31_ff;
+extern cpuop_func op_20fb_31_nf;
+extern cpuop_func op_20fb_31_ff;
+extern cpuop_func op_20fc_31_nf;
+extern cpuop_func op_20fc_31_ff;
+extern cpuop_func op_2100_31_nf;
+extern cpuop_func op_2100_31_ff;
+extern cpuop_func op_2108_31_nf;
+extern cpuop_func op_2108_31_ff;
+extern cpuop_func op_2110_31_nf;
+extern cpuop_func op_2110_31_ff;
+extern cpuop_func op_2118_31_nf;
+extern cpuop_func op_2118_31_ff;
+extern cpuop_func op_2120_31_nf;
+extern cpuop_func op_2120_31_ff;
+extern cpuop_func op_2128_31_nf;
+extern cpuop_func op_2128_31_ff;
+extern cpuop_func op_2130_31_nf;
+extern cpuop_func op_2130_31_ff;
+extern cpuop_func op_2138_31_nf;
+extern cpuop_func op_2138_31_ff;
+extern cpuop_func op_2139_31_nf;
+extern cpuop_func op_2139_31_ff;
+extern cpuop_func op_213a_31_nf;
+extern cpuop_func op_213a_31_ff;
+extern cpuop_func op_213b_31_nf;
+extern cpuop_func op_213b_31_ff;
+extern cpuop_func op_213c_31_nf;
+extern cpuop_func op_213c_31_ff;
+extern cpuop_func op_2140_31_nf;
+extern cpuop_func op_2140_31_ff;
+extern cpuop_func op_2148_31_nf;
+extern cpuop_func op_2148_31_ff;
+extern cpuop_func op_2150_31_nf;
+extern cpuop_func op_2150_31_ff;
+extern cpuop_func op_2158_31_nf;
+extern cpuop_func op_2158_31_ff;
+extern cpuop_func op_2160_31_nf;
+extern cpuop_func op_2160_31_ff;
+extern cpuop_func op_2168_31_nf;
+extern cpuop_func op_2168_31_ff;
+extern cpuop_func op_2170_31_nf;
+extern cpuop_func op_2170_31_ff;
+extern cpuop_func op_2178_31_nf;
+extern cpuop_func op_2178_31_ff;
+extern cpuop_func op_2179_31_nf;
+extern cpuop_func op_2179_31_ff;
+extern cpuop_func op_217a_31_nf;
+extern cpuop_func op_217a_31_ff;
+extern cpuop_func op_217b_31_nf;
+extern cpuop_func op_217b_31_ff;
+extern cpuop_func op_217c_31_nf;
+extern cpuop_func op_217c_31_ff;
+extern cpuop_func op_2180_31_nf;
+extern cpuop_func op_2180_31_ff;
+extern cpuop_func op_2188_31_nf;
+extern cpuop_func op_2188_31_ff;
+extern cpuop_func op_2190_31_nf;
+extern cpuop_func op_2190_31_ff;
+extern cpuop_func op_2198_31_nf;
+extern cpuop_func op_2198_31_ff;
+extern cpuop_func op_21a0_31_nf;
+extern cpuop_func op_21a0_31_ff;
+extern cpuop_func op_21a8_31_nf;
+extern cpuop_func op_21a8_31_ff;
+extern cpuop_func op_21b0_31_nf;
+extern cpuop_func op_21b0_31_ff;
+extern cpuop_func op_21b8_31_nf;
+extern cpuop_func op_21b8_31_ff;
+extern cpuop_func op_21b9_31_nf;
+extern cpuop_func op_21b9_31_ff;
+extern cpuop_func op_21ba_31_nf;
+extern cpuop_func op_21ba_31_ff;
+extern cpuop_func op_21bb_31_nf;
+extern cpuop_func op_21bb_31_ff;
+extern cpuop_func op_21bc_31_nf;
+extern cpuop_func op_21bc_31_ff;
+extern cpuop_func op_21c0_31_nf;
+extern cpuop_func op_21c0_31_ff;
+extern cpuop_func op_21c8_31_nf;
+extern cpuop_func op_21c8_31_ff;
+extern cpuop_func op_21d0_31_nf;
+extern cpuop_func op_21d0_31_ff;
+extern cpuop_func op_21d8_31_nf;
+extern cpuop_func op_21d8_31_ff;
+extern cpuop_func op_21e0_31_nf;
+extern cpuop_func op_21e0_31_ff;
+extern cpuop_func op_21e8_31_nf;
+extern cpuop_func op_21e8_31_ff;
+extern cpuop_func op_21f0_31_nf;
+extern cpuop_func op_21f0_31_ff;
+extern cpuop_func op_21f8_31_nf;
+extern cpuop_func op_21f8_31_ff;
+extern cpuop_func op_21f9_31_nf;
+extern cpuop_func op_21f9_31_ff;
+extern cpuop_func op_21fa_31_nf;
+extern cpuop_func op_21fa_31_ff;
+extern cpuop_func op_21fb_31_nf;
+extern cpuop_func op_21fb_31_ff;
+extern cpuop_func op_21fc_31_nf;
+extern cpuop_func op_21fc_31_ff;
+extern cpuop_func op_23c0_31_nf;
+extern cpuop_func op_23c0_31_ff;
+extern cpuop_func op_23c8_31_nf;
+extern cpuop_func op_23c8_31_ff;
+extern cpuop_func op_23d0_31_nf;
+extern cpuop_func op_23d0_31_ff;
+extern cpuop_func op_23d8_31_nf;
+extern cpuop_func op_23d8_31_ff;
+extern cpuop_func op_23e0_31_nf;
+extern cpuop_func op_23e0_31_ff;
+extern cpuop_func op_23e8_31_nf;
+extern cpuop_func op_23e8_31_ff;
+extern cpuop_func op_23f0_31_nf;
+extern cpuop_func op_23f0_31_ff;
+extern cpuop_func op_23f8_31_nf;
+extern cpuop_func op_23f8_31_ff;
+extern cpuop_func op_23f9_31_nf;
+extern cpuop_func op_23f9_31_ff;
+extern cpuop_func op_23fa_31_nf;
+extern cpuop_func op_23fa_31_ff;
+extern cpuop_func op_23fb_31_nf;
+extern cpuop_func op_23fb_31_ff;
+extern cpuop_func op_23fc_31_nf;
+extern cpuop_func op_23fc_31_ff;
+extern cpuop_func op_3000_31_nf;
+extern cpuop_func op_3000_31_ff;
+extern cpuop_func op_3008_31_nf;
+extern cpuop_func op_3008_31_ff;
+extern cpuop_func op_3010_31_nf;
+extern cpuop_func op_3010_31_ff;
+extern cpuop_func op_3018_31_nf;
+extern cpuop_func op_3018_31_ff;
+extern cpuop_func op_3020_31_nf;
+extern cpuop_func op_3020_31_ff;
+extern cpuop_func op_3028_31_nf;
+extern cpuop_func op_3028_31_ff;
+extern cpuop_func op_3030_31_nf;
+extern cpuop_func op_3030_31_ff;
+extern cpuop_func op_3038_31_nf;
+extern cpuop_func op_3038_31_ff;
+extern cpuop_func op_3039_31_nf;
+extern cpuop_func op_3039_31_ff;
+extern cpuop_func op_303a_31_nf;
+extern cpuop_func op_303a_31_ff;
+extern cpuop_func op_303b_31_nf;
+extern cpuop_func op_303b_31_ff;
+extern cpuop_func op_303c_31_nf;
+extern cpuop_func op_303c_31_ff;
+extern cpuop_func op_3040_31_nf;
+extern cpuop_func op_3040_31_ff;
+extern cpuop_func op_3048_31_nf;
+extern cpuop_func op_3048_31_ff;
+extern cpuop_func op_3050_31_nf;
+extern cpuop_func op_3050_31_ff;
+extern cpuop_func op_3058_31_nf;
+extern cpuop_func op_3058_31_ff;
+extern cpuop_func op_3060_31_nf;
+extern cpuop_func op_3060_31_ff;
+extern cpuop_func op_3068_31_nf;
+extern cpuop_func op_3068_31_ff;
+extern cpuop_func op_3070_31_nf;
+extern cpuop_func op_3070_31_ff;
+extern cpuop_func op_3078_31_nf;
+extern cpuop_func op_3078_31_ff;
+extern cpuop_func op_3079_31_nf;
+extern cpuop_func op_3079_31_ff;
+extern cpuop_func op_307a_31_nf;
+extern cpuop_func op_307a_31_ff;
+extern cpuop_func op_307b_31_nf;
+extern cpuop_func op_307b_31_ff;
+extern cpuop_func op_307c_31_nf;
+extern cpuop_func op_307c_31_ff;
+extern cpuop_func op_3080_31_nf;
+extern cpuop_func op_3080_31_ff;
+extern cpuop_func op_3088_31_nf;
+extern cpuop_func op_3088_31_ff;
+extern cpuop_func op_3090_31_nf;
+extern cpuop_func op_3090_31_ff;
+extern cpuop_func op_3098_31_nf;
+extern cpuop_func op_3098_31_ff;
+extern cpuop_func op_30a0_31_nf;
+extern cpuop_func op_30a0_31_ff;
+extern cpuop_func op_30a8_31_nf;
+extern cpuop_func op_30a8_31_ff;
+extern cpuop_func op_30b0_31_nf;
+extern cpuop_func op_30b0_31_ff;
+extern cpuop_func op_30b8_31_nf;
+extern cpuop_func op_30b8_31_ff;
+extern cpuop_func op_30b9_31_nf;
+extern cpuop_func op_30b9_31_ff;
+extern cpuop_func op_30ba_31_nf;
+extern cpuop_func op_30ba_31_ff;
+extern cpuop_func op_30bb_31_nf;
+extern cpuop_func op_30bb_31_ff;
+extern cpuop_func op_30bc_31_nf;
+extern cpuop_func op_30bc_31_ff;
+extern cpuop_func op_30c0_31_nf;
+extern cpuop_func op_30c0_31_ff;
+extern cpuop_func op_30c8_31_nf;
+extern cpuop_func op_30c8_31_ff;
+extern cpuop_func op_30d0_31_nf;
+extern cpuop_func op_30d0_31_ff;
+extern cpuop_func op_30d8_31_nf;
+extern cpuop_func op_30d8_31_ff;
+extern cpuop_func op_30e0_31_nf;
+extern cpuop_func op_30e0_31_ff;
+extern cpuop_func op_30e8_31_nf;
+extern cpuop_func op_30e8_31_ff;
+extern cpuop_func op_30f0_31_nf;
+extern cpuop_func op_30f0_31_ff;
+extern cpuop_func op_30f8_31_nf;
+extern cpuop_func op_30f8_31_ff;
+extern cpuop_func op_30f9_31_nf;
+extern cpuop_func op_30f9_31_ff;
+extern cpuop_func op_30fa_31_nf;
+extern cpuop_func op_30fa_31_ff;
+extern cpuop_func op_30fb_31_nf;
+extern cpuop_func op_30fb_31_ff;
+extern cpuop_func op_30fc_31_nf;
+extern cpuop_func op_30fc_31_ff;
+extern cpuop_func op_3100_31_nf;
+extern cpuop_func op_3100_31_ff;
+extern cpuop_func op_3108_31_nf;
+extern cpuop_func op_3108_31_ff;
+extern cpuop_func op_3110_31_nf;
+extern cpuop_func op_3110_31_ff;
+extern cpuop_func op_3118_31_nf;
+extern cpuop_func op_3118_31_ff;
+extern cpuop_func op_3120_31_nf;
+extern cpuop_func op_3120_31_ff;
+extern cpuop_func op_3128_31_nf;
+extern cpuop_func op_3128_31_ff;
+extern cpuop_func op_3130_31_nf;
+extern cpuop_func op_3130_31_ff;
+extern cpuop_func op_3138_31_nf;
+extern cpuop_func op_3138_31_ff;
+extern cpuop_func op_3139_31_nf;
+extern cpuop_func op_3139_31_ff;
+extern cpuop_func op_313a_31_nf;
+extern cpuop_func op_313a_31_ff;
+extern cpuop_func op_313b_31_nf;
+extern cpuop_func op_313b_31_ff;
+extern cpuop_func op_313c_31_nf;
+extern cpuop_func op_313c_31_ff;
+extern cpuop_func op_3140_31_nf;
+extern cpuop_func op_3140_31_ff;
+extern cpuop_func op_3148_31_nf;
+extern cpuop_func op_3148_31_ff;
+extern cpuop_func op_3150_31_nf;
+extern cpuop_func op_3150_31_ff;
+extern cpuop_func op_3158_31_nf;
+extern cpuop_func op_3158_31_ff;
+extern cpuop_func op_3160_31_nf;
+extern cpuop_func op_3160_31_ff;
+extern cpuop_func op_3168_31_nf;
+extern cpuop_func op_3168_31_ff;
+extern cpuop_func op_3170_31_nf;
+extern cpuop_func op_3170_31_ff;
+extern cpuop_func op_3178_31_nf;
+extern cpuop_func op_3178_31_ff;
+extern cpuop_func op_3179_31_nf;
+extern cpuop_func op_3179_31_ff;
+extern cpuop_func op_317a_31_nf;
+extern cpuop_func op_317a_31_ff;
+extern cpuop_func op_317b_31_nf;
+extern cpuop_func op_317b_31_ff;
+extern cpuop_func op_317c_31_nf;
+extern cpuop_func op_317c_31_ff;
+extern cpuop_func op_3180_31_nf;
+extern cpuop_func op_3180_31_ff;
+extern cpuop_func op_3188_31_nf;
+extern cpuop_func op_3188_31_ff;
+extern cpuop_func op_3190_31_nf;
+extern cpuop_func op_3190_31_ff;
+extern cpuop_func op_3198_31_nf;
+extern cpuop_func op_3198_31_ff;
+extern cpuop_func op_31a0_31_nf;
+extern cpuop_func op_31a0_31_ff;
+extern cpuop_func op_31a8_31_nf;
+extern cpuop_func op_31a8_31_ff;
+extern cpuop_func op_31b0_31_nf;
+extern cpuop_func op_31b0_31_ff;
+extern cpuop_func op_31b8_31_nf;
+extern cpuop_func op_31b8_31_ff;
+extern cpuop_func op_31b9_31_nf;
+extern cpuop_func op_31b9_31_ff;
+extern cpuop_func op_31ba_31_nf;
+extern cpuop_func op_31ba_31_ff;
+extern cpuop_func op_31bb_31_nf;
+extern cpuop_func op_31bb_31_ff;
+extern cpuop_func op_31bc_31_nf;
+extern cpuop_func op_31bc_31_ff;
+extern cpuop_func op_31c0_31_nf;
+extern cpuop_func op_31c0_31_ff;
+extern cpuop_func op_31c8_31_nf;
+extern cpuop_func op_31c8_31_ff;
+extern cpuop_func op_31d0_31_nf;
+extern cpuop_func op_31d0_31_ff;
+extern cpuop_func op_31d8_31_nf;
+extern cpuop_func op_31d8_31_ff;
+extern cpuop_func op_31e0_31_nf;
+extern cpuop_func op_31e0_31_ff;
+extern cpuop_func op_31e8_31_nf;
+extern cpuop_func op_31e8_31_ff;
+extern cpuop_func op_31f0_31_nf;
+extern cpuop_func op_31f0_31_ff;
+extern cpuop_func op_31f8_31_nf;
+extern cpuop_func op_31f8_31_ff;
+extern cpuop_func op_31f9_31_nf;
+extern cpuop_func op_31f9_31_ff;
+extern cpuop_func op_31fa_31_nf;
+extern cpuop_func op_31fa_31_ff;
+extern cpuop_func op_31fb_31_nf;
+extern cpuop_func op_31fb_31_ff;
+extern cpuop_func op_31fc_31_nf;
+extern cpuop_func op_31fc_31_ff;
+extern cpuop_func op_33c0_31_nf;
+extern cpuop_func op_33c0_31_ff;
+extern cpuop_func op_33c8_31_nf;
+extern cpuop_func op_33c8_31_ff;
+extern cpuop_func op_33d0_31_nf;
+extern cpuop_func op_33d0_31_ff;
+extern cpuop_func op_33d8_31_nf;
+extern cpuop_func op_33d8_31_ff;
+extern cpuop_func op_33e0_31_nf;
+extern cpuop_func op_33e0_31_ff;
+extern cpuop_func op_33e8_31_nf;
+extern cpuop_func op_33e8_31_ff;
+extern cpuop_func op_33f0_31_nf;
+extern cpuop_func op_33f0_31_ff;
+extern cpuop_func op_33f8_31_nf;
+extern cpuop_func op_33f8_31_ff;
+extern cpuop_func op_33f9_31_nf;
+extern cpuop_func op_33f9_31_ff;
+extern cpuop_func op_33fa_31_nf;
+extern cpuop_func op_33fa_31_ff;
+extern cpuop_func op_33fb_31_nf;
+extern cpuop_func op_33fb_31_ff;
+extern cpuop_func op_33fc_31_nf;
+extern cpuop_func op_33fc_31_ff;
+extern cpuop_func op_4000_31_nf;
+extern cpuop_func op_4000_31_ff;
+extern cpuop_func op_4010_31_nf;
+extern cpuop_func op_4010_31_ff;
+extern cpuop_func op_4018_31_nf;
+extern cpuop_func op_4018_31_ff;
+extern cpuop_func op_4020_31_nf;
+extern cpuop_func op_4020_31_ff;
+extern cpuop_func op_4028_31_nf;
+extern cpuop_func op_4028_31_ff;
+extern cpuop_func op_4030_31_nf;
+extern cpuop_func op_4030_31_ff;
+extern cpuop_func op_4038_31_nf;
+extern cpuop_func op_4038_31_ff;
+extern cpuop_func op_4039_31_nf;
+extern cpuop_func op_4039_31_ff;
+extern cpuop_func op_4040_31_nf;
+extern cpuop_func op_4040_31_ff;
+extern cpuop_func op_4050_31_nf;
+extern cpuop_func op_4050_31_ff;
+extern cpuop_func op_4058_31_nf;
+extern cpuop_func op_4058_31_ff;
+extern cpuop_func op_4060_31_nf;
+extern cpuop_func op_4060_31_ff;
+extern cpuop_func op_4068_31_nf;
+extern cpuop_func op_4068_31_ff;
+extern cpuop_func op_4070_31_nf;
+extern cpuop_func op_4070_31_ff;
+extern cpuop_func op_4078_31_nf;
+extern cpuop_func op_4078_31_ff;
+extern cpuop_func op_4079_31_nf;
+extern cpuop_func op_4079_31_ff;
+extern cpuop_func op_4080_31_nf;
+extern cpuop_func op_4080_31_ff;
+extern cpuop_func op_4090_31_nf;
+extern cpuop_func op_4090_31_ff;
+extern cpuop_func op_4098_31_nf;
+extern cpuop_func op_4098_31_ff;
+extern cpuop_func op_40a0_31_nf;
+extern cpuop_func op_40a0_31_ff;
+extern cpuop_func op_40a8_31_nf;
+extern cpuop_func op_40a8_31_ff;
+extern cpuop_func op_40b0_31_nf;
+extern cpuop_func op_40b0_31_ff;
+extern cpuop_func op_40b8_31_nf;
+extern cpuop_func op_40b8_31_ff;
+extern cpuop_func op_40b9_31_nf;
+extern cpuop_func op_40b9_31_ff;
+extern cpuop_func op_40c0_31_nf;
+extern cpuop_func op_40c0_31_ff;
+extern cpuop_func op_40d0_31_nf;
+extern cpuop_func op_40d0_31_ff;
+extern cpuop_func op_40d8_31_nf;
+extern cpuop_func op_40d8_31_ff;
+extern cpuop_func op_40e0_31_nf;
+extern cpuop_func op_40e0_31_ff;
+extern cpuop_func op_40e8_31_nf;
+extern cpuop_func op_40e8_31_ff;
+extern cpuop_func op_40f0_31_nf;
+extern cpuop_func op_40f0_31_ff;
+extern cpuop_func op_40f8_31_nf;
+extern cpuop_func op_40f8_31_ff;
+extern cpuop_func op_40f9_31_nf;
+extern cpuop_func op_40f9_31_ff;
+extern cpuop_func op_4100_31_nf;
+extern cpuop_func op_4100_31_ff;
+extern cpuop_func op_4110_31_nf;
+extern cpuop_func op_4110_31_ff;
+extern cpuop_func op_4118_31_nf;
+extern cpuop_func op_4118_31_ff;
+extern cpuop_func op_4120_31_nf;
+extern cpuop_func op_4120_31_ff;
+extern cpuop_func op_4128_31_nf;
+extern cpuop_func op_4128_31_ff;
+extern cpuop_func op_4130_31_nf;
+extern cpuop_func op_4130_31_ff;
+extern cpuop_func op_4138_31_nf;
+extern cpuop_func op_4138_31_ff;
+extern cpuop_func op_4139_31_nf;
+extern cpuop_func op_4139_31_ff;
+extern cpuop_func op_413a_31_nf;
+extern cpuop_func op_413a_31_ff;
+extern cpuop_func op_413b_31_nf;
+extern cpuop_func op_413b_31_ff;
+extern cpuop_func op_413c_31_nf;
+extern cpuop_func op_413c_31_ff;
+extern cpuop_func op_4180_31_nf;
+extern cpuop_func op_4180_31_ff;
+extern cpuop_func op_4190_31_nf;
+extern cpuop_func op_4190_31_ff;
+extern cpuop_func op_4198_31_nf;
+extern cpuop_func op_4198_31_ff;
+extern cpuop_func op_41a0_31_nf;
+extern cpuop_func op_41a0_31_ff;
+extern cpuop_func op_41a8_31_nf;
+extern cpuop_func op_41a8_31_ff;
+extern cpuop_func op_41b0_31_nf;
+extern cpuop_func op_41b0_31_ff;
+extern cpuop_func op_41b8_31_nf;
+extern cpuop_func op_41b8_31_ff;
+extern cpuop_func op_41b9_31_nf;
+extern cpuop_func op_41b9_31_ff;
+extern cpuop_func op_41ba_31_nf;
+extern cpuop_func op_41ba_31_ff;
+extern cpuop_func op_41bb_31_nf;
+extern cpuop_func op_41bb_31_ff;
+extern cpuop_func op_41bc_31_nf;
+extern cpuop_func op_41bc_31_ff;
+extern cpuop_func op_41d0_31_nf;
+extern cpuop_func op_41d0_31_ff;
+extern cpuop_func op_41e8_31_nf;
+extern cpuop_func op_41e8_31_ff;
+extern cpuop_func op_41f0_31_nf;
+extern cpuop_func op_41f0_31_ff;
+extern cpuop_func op_41f8_31_nf;
+extern cpuop_func op_41f8_31_ff;
+extern cpuop_func op_41f9_31_nf;
+extern cpuop_func op_41f9_31_ff;
+extern cpuop_func op_41fa_31_nf;
+extern cpuop_func op_41fa_31_ff;
+extern cpuop_func op_41fb_31_nf;
+extern cpuop_func op_41fb_31_ff;
+extern cpuop_func op_4200_31_nf;
+extern cpuop_func op_4200_31_ff;
+extern cpuop_func op_4210_31_nf;
+extern cpuop_func op_4210_31_ff;
+extern cpuop_func op_4218_31_nf;
+extern cpuop_func op_4218_31_ff;
+extern cpuop_func op_4220_31_nf;
+extern cpuop_func op_4220_31_ff;
+extern cpuop_func op_4228_31_nf;
+extern cpuop_func op_4228_31_ff;
+extern cpuop_func op_4230_31_nf;
+extern cpuop_func op_4230_31_ff;
+extern cpuop_func op_4238_31_nf;
+extern cpuop_func op_4238_31_ff;
+extern cpuop_func op_4239_31_nf;
+extern cpuop_func op_4239_31_ff;
+extern cpuop_func op_4240_31_nf;
+extern cpuop_func op_4240_31_ff;
+extern cpuop_func op_4250_31_nf;
+extern cpuop_func op_4250_31_ff;
+extern cpuop_func op_4258_31_nf;
+extern cpuop_func op_4258_31_ff;
+extern cpuop_func op_4260_31_nf;
+extern cpuop_func op_4260_31_ff;
+extern cpuop_func op_4268_31_nf;
+extern cpuop_func op_4268_31_ff;
+extern cpuop_func op_4270_31_nf;
+extern cpuop_func op_4270_31_ff;
+extern cpuop_func op_4278_31_nf;
+extern cpuop_func op_4278_31_ff;
+extern cpuop_func op_4279_31_nf;
+extern cpuop_func op_4279_31_ff;
+extern cpuop_func op_4280_31_nf;
+extern cpuop_func op_4280_31_ff;
+extern cpuop_func op_4290_31_nf;
+extern cpuop_func op_4290_31_ff;
+extern cpuop_func op_4298_31_nf;
+extern cpuop_func op_4298_31_ff;
+extern cpuop_func op_42a0_31_nf;
+extern cpuop_func op_42a0_31_ff;
+extern cpuop_func op_42a8_31_nf;
+extern cpuop_func op_42a8_31_ff;
+extern cpuop_func op_42b0_31_nf;
+extern cpuop_func op_42b0_31_ff;
+extern cpuop_func op_42b8_31_nf;
+extern cpuop_func op_42b8_31_ff;
+extern cpuop_func op_42b9_31_nf;
+extern cpuop_func op_42b9_31_ff;
+extern cpuop_func op_42c0_31_nf;
+extern cpuop_func op_42c0_31_ff;
+extern cpuop_func op_42d0_31_nf;
+extern cpuop_func op_42d0_31_ff;
+extern cpuop_func op_42d8_31_nf;
+extern cpuop_func op_42d8_31_ff;
+extern cpuop_func op_42e0_31_nf;
+extern cpuop_func op_42e0_31_ff;
+extern cpuop_func op_42e8_31_nf;
+extern cpuop_func op_42e8_31_ff;
+extern cpuop_func op_42f0_31_nf;
+extern cpuop_func op_42f0_31_ff;
+extern cpuop_func op_42f8_31_nf;
+extern cpuop_func op_42f8_31_ff;
+extern cpuop_func op_42f9_31_nf;
+extern cpuop_func op_42f9_31_ff;
+extern cpuop_func op_4400_31_nf;
+extern cpuop_func op_4400_31_ff;
+extern cpuop_func op_4410_31_nf;
+extern cpuop_func op_4410_31_ff;
+extern cpuop_func op_4418_31_nf;
+extern cpuop_func op_4418_31_ff;
+extern cpuop_func op_4420_31_nf;
+extern cpuop_func op_4420_31_ff;
+extern cpuop_func op_4428_31_nf;
+extern cpuop_func op_4428_31_ff;
+extern cpuop_func op_4430_31_nf;
+extern cpuop_func op_4430_31_ff;
+extern cpuop_func op_4438_31_nf;
+extern cpuop_func op_4438_31_ff;
+extern cpuop_func op_4439_31_nf;
+extern cpuop_func op_4439_31_ff;
+extern cpuop_func op_4440_31_nf;
+extern cpuop_func op_4440_31_ff;
+extern cpuop_func op_4450_31_nf;
+extern cpuop_func op_4450_31_ff;
+extern cpuop_func op_4458_31_nf;
+extern cpuop_func op_4458_31_ff;
+extern cpuop_func op_4460_31_nf;
+extern cpuop_func op_4460_31_ff;
+extern cpuop_func op_4468_31_nf;
+extern cpuop_func op_4468_31_ff;
+extern cpuop_func op_4470_31_nf;
+extern cpuop_func op_4470_31_ff;
+extern cpuop_func op_4478_31_nf;
+extern cpuop_func op_4478_31_ff;
+extern cpuop_func op_4479_31_nf;
+extern cpuop_func op_4479_31_ff;
+extern cpuop_func op_4480_31_nf;
+extern cpuop_func op_4480_31_ff;
+extern cpuop_func op_4490_31_nf;
+extern cpuop_func op_4490_31_ff;
+extern cpuop_func op_4498_31_nf;
+extern cpuop_func op_4498_31_ff;
+extern cpuop_func op_44a0_31_nf;
+extern cpuop_func op_44a0_31_ff;
+extern cpuop_func op_44a8_31_nf;
+extern cpuop_func op_44a8_31_ff;
+extern cpuop_func op_44b0_31_nf;
+extern cpuop_func op_44b0_31_ff;
+extern cpuop_func op_44b8_31_nf;
+extern cpuop_func op_44b8_31_ff;
+extern cpuop_func op_44b9_31_nf;
+extern cpuop_func op_44b9_31_ff;
+extern cpuop_func op_44c0_31_nf;
+extern cpuop_func op_44c0_31_ff;
+extern cpuop_func op_44d0_31_nf;
+extern cpuop_func op_44d0_31_ff;
+extern cpuop_func op_44d8_31_nf;
+extern cpuop_func op_44d8_31_ff;
+extern cpuop_func op_44e0_31_nf;
+extern cpuop_func op_44e0_31_ff;
+extern cpuop_func op_44e8_31_nf;
+extern cpuop_func op_44e8_31_ff;
+extern cpuop_func op_44f0_31_nf;
+extern cpuop_func op_44f0_31_ff;
+extern cpuop_func op_44f8_31_nf;
+extern cpuop_func op_44f8_31_ff;
+extern cpuop_func op_44f9_31_nf;
+extern cpuop_func op_44f9_31_ff;
+extern cpuop_func op_44fa_31_nf;
+extern cpuop_func op_44fa_31_ff;
+extern cpuop_func op_44fb_31_nf;
+extern cpuop_func op_44fb_31_ff;
+extern cpuop_func op_44fc_31_nf;
+extern cpuop_func op_44fc_31_ff;
+extern cpuop_func op_4600_31_nf;
+extern cpuop_func op_4600_31_ff;
+extern cpuop_func op_4610_31_nf;
+extern cpuop_func op_4610_31_ff;
+extern cpuop_func op_4618_31_nf;
+extern cpuop_func op_4618_31_ff;
+extern cpuop_func op_4620_31_nf;
+extern cpuop_func op_4620_31_ff;
+extern cpuop_func op_4628_31_nf;
+extern cpuop_func op_4628_31_ff;
+extern cpuop_func op_4630_31_nf;
+extern cpuop_func op_4630_31_ff;
+extern cpuop_func op_4638_31_nf;
+extern cpuop_func op_4638_31_ff;
+extern cpuop_func op_4639_31_nf;
+extern cpuop_func op_4639_31_ff;
+extern cpuop_func op_4640_31_nf;
+extern cpuop_func op_4640_31_ff;
+extern cpuop_func op_4650_31_nf;
+extern cpuop_func op_4650_31_ff;
+extern cpuop_func op_4658_31_nf;
+extern cpuop_func op_4658_31_ff;
+extern cpuop_func op_4660_31_nf;
+extern cpuop_func op_4660_31_ff;
+extern cpuop_func op_4668_31_nf;
+extern cpuop_func op_4668_31_ff;
+extern cpuop_func op_4670_31_nf;
+extern cpuop_func op_4670_31_ff;
+extern cpuop_func op_4678_31_nf;
+extern cpuop_func op_4678_31_ff;
+extern cpuop_func op_4679_31_nf;
+extern cpuop_func op_4679_31_ff;
+extern cpuop_func op_4680_31_nf;
+extern cpuop_func op_4680_31_ff;
+extern cpuop_func op_4690_31_nf;
+extern cpuop_func op_4690_31_ff;
+extern cpuop_func op_4698_31_nf;
+extern cpuop_func op_4698_31_ff;
+extern cpuop_func op_46a0_31_nf;
+extern cpuop_func op_46a0_31_ff;
+extern cpuop_func op_46a8_31_nf;
+extern cpuop_func op_46a8_31_ff;
+extern cpuop_func op_46b0_31_nf;
+extern cpuop_func op_46b0_31_ff;
+extern cpuop_func op_46b8_31_nf;
+extern cpuop_func op_46b8_31_ff;
+extern cpuop_func op_46b9_31_nf;
+extern cpuop_func op_46b9_31_ff;
+extern cpuop_func op_46c0_31_nf;
+extern cpuop_func op_46c0_31_ff;
+extern cpuop_func op_46d0_31_nf;
+extern cpuop_func op_46d0_31_ff;
+extern cpuop_func op_46d8_31_nf;
+extern cpuop_func op_46d8_31_ff;
+extern cpuop_func op_46e0_31_nf;
+extern cpuop_func op_46e0_31_ff;
+extern cpuop_func op_46e8_31_nf;
+extern cpuop_func op_46e8_31_ff;
+extern cpuop_func op_46f0_31_nf;
+extern cpuop_func op_46f0_31_ff;
+extern cpuop_func op_46f8_31_nf;
+extern cpuop_func op_46f8_31_ff;
+extern cpuop_func op_46f9_31_nf;
+extern cpuop_func op_46f9_31_ff;
+extern cpuop_func op_46fa_31_nf;
+extern cpuop_func op_46fa_31_ff;
+extern cpuop_func op_46fb_31_nf;
+extern cpuop_func op_46fb_31_ff;
+extern cpuop_func op_46fc_31_nf;
+extern cpuop_func op_46fc_31_ff;
+extern cpuop_func op_4800_31_nf;
+extern cpuop_func op_4800_31_ff;
+extern cpuop_func op_4808_31_nf;
+extern cpuop_func op_4808_31_ff;
+extern cpuop_func op_4810_31_nf;
+extern cpuop_func op_4810_31_ff;
+extern cpuop_func op_4818_31_nf;
+extern cpuop_func op_4818_31_ff;
+extern cpuop_func op_4820_31_nf;
+extern cpuop_func op_4820_31_ff;
+extern cpuop_func op_4828_31_nf;
+extern cpuop_func op_4828_31_ff;
+extern cpuop_func op_4830_31_nf;
+extern cpuop_func op_4830_31_ff;
+extern cpuop_func op_4838_31_nf;
+extern cpuop_func op_4838_31_ff;
+extern cpuop_func op_4839_31_nf;
+extern cpuop_func op_4839_31_ff;
+extern cpuop_func op_4840_31_nf;
+extern cpuop_func op_4840_31_ff;
+extern cpuop_func op_4848_31_nf;
+extern cpuop_func op_4848_31_ff;
+extern cpuop_func op_4850_31_nf;
+extern cpuop_func op_4850_31_ff;
+extern cpuop_func op_4868_31_nf;
+extern cpuop_func op_4868_31_ff;
+extern cpuop_func op_4870_31_nf;
+extern cpuop_func op_4870_31_ff;
+extern cpuop_func op_4878_31_nf;
+extern cpuop_func op_4878_31_ff;
+extern cpuop_func op_4879_31_nf;
+extern cpuop_func op_4879_31_ff;
+extern cpuop_func op_487a_31_nf;
+extern cpuop_func op_487a_31_ff;
+extern cpuop_func op_487b_31_nf;
+extern cpuop_func op_487b_31_ff;
+extern cpuop_func op_4880_31_nf;
+extern cpuop_func op_4880_31_ff;
+extern cpuop_func op_4890_31_nf;
+extern cpuop_func op_4890_31_ff;
+extern cpuop_func op_48a0_31_nf;
+extern cpuop_func op_48a0_31_ff;
+extern cpuop_func op_48a8_31_nf;
+extern cpuop_func op_48a8_31_ff;
+extern cpuop_func op_48b0_31_nf;
+extern cpuop_func op_48b0_31_ff;
+extern cpuop_func op_48b8_31_nf;
+extern cpuop_func op_48b8_31_ff;
+extern cpuop_func op_48b9_31_nf;
+extern cpuop_func op_48b9_31_ff;
+extern cpuop_func op_48c0_31_nf;
+extern cpuop_func op_48c0_31_ff;
+extern cpuop_func op_48d0_31_nf;
+extern cpuop_func op_48d0_31_ff;
+extern cpuop_func op_48e0_31_nf;
+extern cpuop_func op_48e0_31_ff;
+extern cpuop_func op_48e8_31_nf;
+extern cpuop_func op_48e8_31_ff;
+extern cpuop_func op_48f0_31_nf;
+extern cpuop_func op_48f0_31_ff;
+extern cpuop_func op_48f8_31_nf;
+extern cpuop_func op_48f8_31_ff;
+extern cpuop_func op_48f9_31_nf;
+extern cpuop_func op_48f9_31_ff;
+extern cpuop_func op_49c0_31_nf;
+extern cpuop_func op_49c0_31_ff;
+extern cpuop_func op_4a00_31_nf;
+extern cpuop_func op_4a00_31_ff;
+extern cpuop_func op_4a10_31_nf;
+extern cpuop_func op_4a10_31_ff;
+extern cpuop_func op_4a18_31_nf;
+extern cpuop_func op_4a18_31_ff;
+extern cpuop_func op_4a20_31_nf;
+extern cpuop_func op_4a20_31_ff;
+extern cpuop_func op_4a28_31_nf;
+extern cpuop_func op_4a28_31_ff;
+extern cpuop_func op_4a30_31_nf;
+extern cpuop_func op_4a30_31_ff;
+extern cpuop_func op_4a38_31_nf;
+extern cpuop_func op_4a38_31_ff;
+extern cpuop_func op_4a39_31_nf;
+extern cpuop_func op_4a39_31_ff;
+extern cpuop_func op_4a3a_31_nf;
+extern cpuop_func op_4a3a_31_ff;
+extern cpuop_func op_4a3b_31_nf;
+extern cpuop_func op_4a3b_31_ff;
+extern cpuop_func op_4a3c_31_nf;
+extern cpuop_func op_4a3c_31_ff;
+extern cpuop_func op_4a40_31_nf;
+extern cpuop_func op_4a40_31_ff;
+extern cpuop_func op_4a48_31_nf;
+extern cpuop_func op_4a48_31_ff;
+extern cpuop_func op_4a50_31_nf;
+extern cpuop_func op_4a50_31_ff;
+extern cpuop_func op_4a58_31_nf;
+extern cpuop_func op_4a58_31_ff;
+extern cpuop_func op_4a60_31_nf;
+extern cpuop_func op_4a60_31_ff;
+extern cpuop_func op_4a68_31_nf;
+extern cpuop_func op_4a68_31_ff;
+extern cpuop_func op_4a70_31_nf;
+extern cpuop_func op_4a70_31_ff;
+extern cpuop_func op_4a78_31_nf;
+extern cpuop_func op_4a78_31_ff;
+extern cpuop_func op_4a79_31_nf;
+extern cpuop_func op_4a79_31_ff;
+extern cpuop_func op_4a7a_31_nf;
+extern cpuop_func op_4a7a_31_ff;
+extern cpuop_func op_4a7b_31_nf;
+extern cpuop_func op_4a7b_31_ff;
+extern cpuop_func op_4a7c_31_nf;
+extern cpuop_func op_4a7c_31_ff;
+extern cpuop_func op_4a80_31_nf;
+extern cpuop_func op_4a80_31_ff;
+extern cpuop_func op_4a88_31_nf;
+extern cpuop_func op_4a88_31_ff;
+extern cpuop_func op_4a90_31_nf;
+extern cpuop_func op_4a90_31_ff;
+extern cpuop_func op_4a98_31_nf;
+extern cpuop_func op_4a98_31_ff;
+extern cpuop_func op_4aa0_31_nf;
+extern cpuop_func op_4aa0_31_ff;
+extern cpuop_func op_4aa8_31_nf;
+extern cpuop_func op_4aa8_31_ff;
+extern cpuop_func op_4ab0_31_nf;
+extern cpuop_func op_4ab0_31_ff;
+extern cpuop_func op_4ab8_31_nf;
+extern cpuop_func op_4ab8_31_ff;
+extern cpuop_func op_4ab9_31_nf;
+extern cpuop_func op_4ab9_31_ff;
+extern cpuop_func op_4aba_31_nf;
+extern cpuop_func op_4aba_31_ff;
+extern cpuop_func op_4abb_31_nf;
+extern cpuop_func op_4abb_31_ff;
+extern cpuop_func op_4abc_31_nf;
+extern cpuop_func op_4abc_31_ff;
+extern cpuop_func op_4ac0_31_nf;
+extern cpuop_func op_4ac0_31_ff;
+extern cpuop_func op_4ad0_31_nf;
+extern cpuop_func op_4ad0_31_ff;
+extern cpuop_func op_4ad8_31_nf;
+extern cpuop_func op_4ad8_31_ff;
+extern cpuop_func op_4ae0_31_nf;
+extern cpuop_func op_4ae0_31_ff;
+extern cpuop_func op_4ae8_31_nf;
+extern cpuop_func op_4ae8_31_ff;
+extern cpuop_func op_4af0_31_nf;
+extern cpuop_func op_4af0_31_ff;
+extern cpuop_func op_4af8_31_nf;
+extern cpuop_func op_4af8_31_ff;
+extern cpuop_func op_4af9_31_nf;
+extern cpuop_func op_4af9_31_ff;
+extern cpuop_func op_4c00_31_nf;
+extern cpuop_func op_4c00_31_ff;
+extern cpuop_func op_4c10_31_nf;
+extern cpuop_func op_4c10_31_ff;
+extern cpuop_func op_4c18_31_nf;
+extern cpuop_func op_4c18_31_ff;
+extern cpuop_func op_4c20_31_nf;
+extern cpuop_func op_4c20_31_ff;
+extern cpuop_func op_4c28_31_nf;
+extern cpuop_func op_4c28_31_ff;
+extern cpuop_func op_4c30_31_nf;
+extern cpuop_func op_4c30_31_ff;
+extern cpuop_func op_4c38_31_nf;
+extern cpuop_func op_4c38_31_ff;
+extern cpuop_func op_4c39_31_nf;
+extern cpuop_func op_4c39_31_ff;
+extern cpuop_func op_4c3a_31_nf;
+extern cpuop_func op_4c3a_31_ff;
+extern cpuop_func op_4c3b_31_nf;
+extern cpuop_func op_4c3b_31_ff;
+extern cpuop_func op_4c3c_31_nf;
+extern cpuop_func op_4c3c_31_ff;
+extern cpuop_func op_4c40_31_nf;
+extern cpuop_func op_4c40_31_ff;
+extern cpuop_func op_4c50_31_nf;
+extern cpuop_func op_4c50_31_ff;
+extern cpuop_func op_4c58_31_nf;
+extern cpuop_func op_4c58_31_ff;
+extern cpuop_func op_4c60_31_nf;
+extern cpuop_func op_4c60_31_ff;
+extern cpuop_func op_4c68_31_nf;
+extern cpuop_func op_4c68_31_ff;
+extern cpuop_func op_4c70_31_nf;
+extern cpuop_func op_4c70_31_ff;
+extern cpuop_func op_4c78_31_nf;
+extern cpuop_func op_4c78_31_ff;
+extern cpuop_func op_4c79_31_nf;
+extern cpuop_func op_4c79_31_ff;
+extern cpuop_func op_4c7a_31_nf;
+extern cpuop_func op_4c7a_31_ff;
+extern cpuop_func op_4c7b_31_nf;
+extern cpuop_func op_4c7b_31_ff;
+extern cpuop_func op_4c7c_31_nf;
+extern cpuop_func op_4c7c_31_ff;
+extern cpuop_func op_4c90_31_nf;
+extern cpuop_func op_4c90_31_ff;
+extern cpuop_func op_4c98_31_nf;
+extern cpuop_func op_4c98_31_ff;
+extern cpuop_func op_4ca8_31_nf;
+extern cpuop_func op_4ca8_31_ff;
+extern cpuop_func op_4cb0_31_nf;
+extern cpuop_func op_4cb0_31_ff;
+extern cpuop_func op_4cb8_31_nf;
+extern cpuop_func op_4cb8_31_ff;
+extern cpuop_func op_4cb9_31_nf;
+extern cpuop_func op_4cb9_31_ff;
+extern cpuop_func op_4cba_31_nf;
+extern cpuop_func op_4cba_31_ff;
+extern cpuop_func op_4cbb_31_nf;
+extern cpuop_func op_4cbb_31_ff;
+extern cpuop_func op_4cd0_31_nf;
+extern cpuop_func op_4cd0_31_ff;
+extern cpuop_func op_4cd8_31_nf;
+extern cpuop_func op_4cd8_31_ff;
+extern cpuop_func op_4ce8_31_nf;
+extern cpuop_func op_4ce8_31_ff;
+extern cpuop_func op_4cf0_31_nf;
+extern cpuop_func op_4cf0_31_ff;
+extern cpuop_func op_4cf8_31_nf;
+extern cpuop_func op_4cf8_31_ff;
+extern cpuop_func op_4cf9_31_nf;
+extern cpuop_func op_4cf9_31_ff;
+extern cpuop_func op_4cfa_31_nf;
+extern cpuop_func op_4cfa_31_ff;
+extern cpuop_func op_4cfb_31_nf;
+extern cpuop_func op_4cfb_31_ff;
+extern cpuop_func op_4e40_31_nf;
+extern cpuop_func op_4e40_31_ff;
+extern cpuop_func op_4e50_31_nf;
+extern cpuop_func op_4e50_31_ff;
+extern cpuop_func op_4e58_31_nf;
+extern cpuop_func op_4e58_31_ff;
+extern cpuop_func op_4e60_31_nf;
+extern cpuop_func op_4e60_31_ff;
+extern cpuop_func op_4e68_31_nf;
+extern cpuop_func op_4e68_31_ff;
+extern cpuop_func op_4e70_31_nf;
+extern cpuop_func op_4e70_31_ff;
+extern cpuop_func op_4e71_31_nf;
+extern cpuop_func op_4e71_31_ff;
+extern cpuop_func op_4e72_31_nf;
+extern cpuop_func op_4e72_31_ff;
+extern cpuop_func op_4e73_31_nf;
+extern cpuop_func op_4e73_31_ff;
+extern cpuop_func op_4e74_31_nf;
+extern cpuop_func op_4e74_31_ff;
+extern cpuop_func op_4e75_31_nf;
+extern cpuop_func op_4e75_31_ff;
+extern cpuop_func op_4e76_31_nf;
+extern cpuop_func op_4e76_31_ff;
+extern cpuop_func op_4e77_31_nf;
+extern cpuop_func op_4e77_31_ff;
+extern cpuop_func op_4e7a_31_nf;
+extern cpuop_func op_4e7a_31_ff;
+extern cpuop_func op_4e7b_31_nf;
+extern cpuop_func op_4e7b_31_ff;
+extern cpuop_func op_4e90_31_nf;
+extern cpuop_func op_4e90_31_ff;
+extern cpuop_func op_4ea8_31_nf;
+extern cpuop_func op_4ea8_31_ff;
+extern cpuop_func op_4eb0_31_nf;
+extern cpuop_func op_4eb0_31_ff;
+extern cpuop_func op_4eb8_31_nf;
+extern cpuop_func op_4eb8_31_ff;
+extern cpuop_func op_4eb9_31_nf;
+extern cpuop_func op_4eb9_31_ff;
+extern cpuop_func op_4eba_31_nf;
+extern cpuop_func op_4eba_31_ff;
+extern cpuop_func op_4ebb_31_nf;
+extern cpuop_func op_4ebb_31_ff;
+extern cpuop_func op_4ed0_31_nf;
+extern cpuop_func op_4ed0_31_ff;
+extern cpuop_func op_4ee8_31_nf;
+extern cpuop_func op_4ee8_31_ff;
+extern cpuop_func op_4ef0_31_nf;
+extern cpuop_func op_4ef0_31_ff;
+extern cpuop_func op_4ef8_31_nf;
+extern cpuop_func op_4ef8_31_ff;
+extern cpuop_func op_4ef9_31_nf;
+extern cpuop_func op_4ef9_31_ff;
+extern cpuop_func op_4efa_31_nf;
+extern cpuop_func op_4efa_31_ff;
+extern cpuop_func op_4efb_31_nf;
+extern cpuop_func op_4efb_31_ff;
+extern cpuop_func op_5000_31_nf;
+extern cpuop_func op_5000_31_ff;
+extern cpuop_func op_5010_31_nf;
+extern cpuop_func op_5010_31_ff;
+extern cpuop_func op_5018_31_nf;
+extern cpuop_func op_5018_31_ff;
+extern cpuop_func op_5020_31_nf;
+extern cpuop_func op_5020_31_ff;
+extern cpuop_func op_5028_31_nf;
+extern cpuop_func op_5028_31_ff;
+extern cpuop_func op_5030_31_nf;
+extern cpuop_func op_5030_31_ff;
+extern cpuop_func op_5038_31_nf;
+extern cpuop_func op_5038_31_ff;
+extern cpuop_func op_5039_31_nf;
+extern cpuop_func op_5039_31_ff;
+extern cpuop_func op_5040_31_nf;
+extern cpuop_func op_5040_31_ff;
+extern cpuop_func op_5048_31_nf;
+extern cpuop_func op_5048_31_ff;
+extern cpuop_func op_5050_31_nf;
+extern cpuop_func op_5050_31_ff;
+extern cpuop_func op_5058_31_nf;
+extern cpuop_func op_5058_31_ff;
+extern cpuop_func op_5060_31_nf;
+extern cpuop_func op_5060_31_ff;
+extern cpuop_func op_5068_31_nf;
+extern cpuop_func op_5068_31_ff;
+extern cpuop_func op_5070_31_nf;
+extern cpuop_func op_5070_31_ff;
+extern cpuop_func op_5078_31_nf;
+extern cpuop_func op_5078_31_ff;
+extern cpuop_func op_5079_31_nf;
+extern cpuop_func op_5079_31_ff;
+extern cpuop_func op_5080_31_nf;
+extern cpuop_func op_5080_31_ff;
+extern cpuop_func op_5088_31_nf;
+extern cpuop_func op_5088_31_ff;
+extern cpuop_func op_5090_31_nf;
+extern cpuop_func op_5090_31_ff;
+extern cpuop_func op_5098_31_nf;
+extern cpuop_func op_5098_31_ff;
+extern cpuop_func op_50a0_31_nf;
+extern cpuop_func op_50a0_31_ff;
+extern cpuop_func op_50a8_31_nf;
+extern cpuop_func op_50a8_31_ff;
+extern cpuop_func op_50b0_31_nf;
+extern cpuop_func op_50b0_31_ff;
+extern cpuop_func op_50b8_31_nf;
+extern cpuop_func op_50b8_31_ff;
+extern cpuop_func op_50b9_31_nf;
+extern cpuop_func op_50b9_31_ff;
+extern cpuop_func op_50c0_31_nf;
+extern cpuop_func op_50c0_31_ff;
+extern cpuop_func op_50c8_31_nf;
+extern cpuop_func op_50c8_31_ff;
+extern cpuop_func op_50d0_31_nf;
+extern cpuop_func op_50d0_31_ff;
+extern cpuop_func op_50d8_31_nf;
+extern cpuop_func op_50d8_31_ff;
+extern cpuop_func op_50e0_31_nf;
+extern cpuop_func op_50e0_31_ff;
+extern cpuop_func op_50e8_31_nf;
+extern cpuop_func op_50e8_31_ff;
+extern cpuop_func op_50f0_31_nf;
+extern cpuop_func op_50f0_31_ff;
+extern cpuop_func op_50f8_31_nf;
+extern cpuop_func op_50f8_31_ff;
+extern cpuop_func op_50f9_31_nf;
+extern cpuop_func op_50f9_31_ff;
+extern cpuop_func op_50fa_31_nf;
+extern cpuop_func op_50fa_31_ff;
+extern cpuop_func op_50fb_31_nf;
+extern cpuop_func op_50fb_31_ff;
+extern cpuop_func op_50fc_31_nf;
+extern cpuop_func op_50fc_31_ff;
+extern cpuop_func op_5100_31_nf;
+extern cpuop_func op_5100_31_ff;
+extern cpuop_func op_5110_31_nf;
+extern cpuop_func op_5110_31_ff;
+extern cpuop_func op_5118_31_nf;
+extern cpuop_func op_5118_31_ff;
+extern cpuop_func op_5120_31_nf;
+extern cpuop_func op_5120_31_ff;
+extern cpuop_func op_5128_31_nf;
+extern cpuop_func op_5128_31_ff;
+extern cpuop_func op_5130_31_nf;
+extern cpuop_func op_5130_31_ff;
+extern cpuop_func op_5138_31_nf;
+extern cpuop_func op_5138_31_ff;
+extern cpuop_func op_5139_31_nf;
+extern cpuop_func op_5139_31_ff;
+extern cpuop_func op_5140_31_nf;
+extern cpuop_func op_5140_31_ff;
+extern cpuop_func op_5148_31_nf;
+extern cpuop_func op_5148_31_ff;
+extern cpuop_func op_5150_31_nf;
+extern cpuop_func op_5150_31_ff;
+extern cpuop_func op_5158_31_nf;
+extern cpuop_func op_5158_31_ff;
+extern cpuop_func op_5160_31_nf;
+extern cpuop_func op_5160_31_ff;
+extern cpuop_func op_5168_31_nf;
+extern cpuop_func op_5168_31_ff;
+extern cpuop_func op_5170_31_nf;
+extern cpuop_func op_5170_31_ff;
+extern cpuop_func op_5178_31_nf;
+extern cpuop_func op_5178_31_ff;
+extern cpuop_func op_5179_31_nf;
+extern cpuop_func op_5179_31_ff;
+extern cpuop_func op_5180_31_nf;
+extern cpuop_func op_5180_31_ff;
+extern cpuop_func op_5188_31_nf;
+extern cpuop_func op_5188_31_ff;
+extern cpuop_func op_5190_31_nf;
+extern cpuop_func op_5190_31_ff;
+extern cpuop_func op_5198_31_nf;
+extern cpuop_func op_5198_31_ff;
+extern cpuop_func op_51a0_31_nf;
+extern cpuop_func op_51a0_31_ff;
+extern cpuop_func op_51a8_31_nf;
+extern cpuop_func op_51a8_31_ff;
+extern cpuop_func op_51b0_31_nf;
+extern cpuop_func op_51b0_31_ff;
+extern cpuop_func op_51b8_31_nf;
+extern cpuop_func op_51b8_31_ff;
+extern cpuop_func op_51b9_31_nf;
+extern cpuop_func op_51b9_31_ff;
+extern cpuop_func op_51c0_31_nf;
+extern cpuop_func op_51c0_31_ff;
+extern cpuop_func op_51c8_31_nf;
+extern cpuop_func op_51c8_31_ff;
+extern cpuop_func op_51d0_31_nf;
+extern cpuop_func op_51d0_31_ff;
+extern cpuop_func op_51d8_31_nf;
+extern cpuop_func op_51d8_31_ff;
+extern cpuop_func op_51e0_31_nf;
+extern cpuop_func op_51e0_31_ff;
+extern cpuop_func op_51e8_31_nf;
+extern cpuop_func op_51e8_31_ff;
+extern cpuop_func op_51f0_31_nf;
+extern cpuop_func op_51f0_31_ff;
+extern cpuop_func op_51f8_31_nf;
+extern cpuop_func op_51f8_31_ff;
+extern cpuop_func op_51f9_31_nf;
+extern cpuop_func op_51f9_31_ff;
+extern cpuop_func op_51fa_31_nf;
+extern cpuop_func op_51fa_31_ff;
+extern cpuop_func op_51fb_31_nf;
+extern cpuop_func op_51fb_31_ff;
+extern cpuop_func op_51fc_31_nf;
+extern cpuop_func op_51fc_31_ff;
+extern cpuop_func op_52c0_31_nf;
+extern cpuop_func op_52c0_31_ff;
+extern cpuop_func op_52c8_31_nf;
+extern cpuop_func op_52c8_31_ff;
+extern cpuop_func op_52d0_31_nf;
+extern cpuop_func op_52d0_31_ff;
+extern cpuop_func op_52d8_31_nf;
+extern cpuop_func op_52d8_31_ff;
+extern cpuop_func op_52e0_31_nf;
+extern cpuop_func op_52e0_31_ff;
+extern cpuop_func op_52e8_31_nf;
+extern cpuop_func op_52e8_31_ff;
+extern cpuop_func op_52f0_31_nf;
+extern cpuop_func op_52f0_31_ff;
+extern cpuop_func op_52f8_31_nf;
+extern cpuop_func op_52f8_31_ff;
+extern cpuop_func op_52f9_31_nf;
+extern cpuop_func op_52f9_31_ff;
+extern cpuop_func op_52fa_31_nf;
+extern cpuop_func op_52fa_31_ff;
+extern cpuop_func op_52fb_31_nf;
+extern cpuop_func op_52fb_31_ff;
+extern cpuop_func op_52fc_31_nf;
+extern cpuop_func op_52fc_31_ff;
+extern cpuop_func op_53c0_31_nf;
+extern cpuop_func op_53c0_31_ff;
+extern cpuop_func op_53c8_31_nf;
+extern cpuop_func op_53c8_31_ff;
+extern cpuop_func op_53d0_31_nf;
+extern cpuop_func op_53d0_31_ff;
+extern cpuop_func op_53d8_31_nf;
+extern cpuop_func op_53d8_31_ff;
+extern cpuop_func op_53e0_31_nf;
+extern cpuop_func op_53e0_31_ff;
+extern cpuop_func op_53e8_31_nf;
+extern cpuop_func op_53e8_31_ff;
+extern cpuop_func op_53f0_31_nf;
+extern cpuop_func op_53f0_31_ff;
+extern cpuop_func op_53f8_31_nf;
+extern cpuop_func op_53f8_31_ff;
+extern cpuop_func op_53f9_31_nf;
+extern cpuop_func op_53f9_31_ff;
+extern cpuop_func op_53fa_31_nf;
+extern cpuop_func op_53fa_31_ff;
+extern cpuop_func op_53fb_31_nf;
+extern cpuop_func op_53fb_31_ff;
+extern cpuop_func op_53fc_31_nf;
+extern cpuop_func op_53fc_31_ff;
+extern cpuop_func op_54c0_31_nf;
+extern cpuop_func op_54c0_31_ff;
+extern cpuop_func op_54c8_31_nf;
+extern cpuop_func op_54c8_31_ff;
+extern cpuop_func op_54d0_31_nf;
+extern cpuop_func op_54d0_31_ff;
+extern cpuop_func op_54d8_31_nf;
+extern cpuop_func op_54d8_31_ff;
+extern cpuop_func op_54e0_31_nf;
+extern cpuop_func op_54e0_31_ff;
+extern cpuop_func op_54e8_31_nf;
+extern cpuop_func op_54e8_31_ff;
+extern cpuop_func op_54f0_31_nf;
+extern cpuop_func op_54f0_31_ff;
+extern cpuop_func op_54f8_31_nf;
+extern cpuop_func op_54f8_31_ff;
+extern cpuop_func op_54f9_31_nf;
+extern cpuop_func op_54f9_31_ff;
+extern cpuop_func op_54fa_31_nf;
+extern cpuop_func op_54fa_31_ff;
+extern cpuop_func op_54fb_31_nf;
+extern cpuop_func op_54fb_31_ff;
+extern cpuop_func op_54fc_31_nf;
+extern cpuop_func op_54fc_31_ff;
+extern cpuop_func op_55c0_31_nf;
+extern cpuop_func op_55c0_31_ff;
+extern cpuop_func op_55c8_31_nf;
+extern cpuop_func op_55c8_31_ff;
+extern cpuop_func op_55d0_31_nf;
+extern cpuop_func op_55d0_31_ff;
+extern cpuop_func op_55d8_31_nf;
+extern cpuop_func op_55d8_31_ff;
+extern cpuop_func op_55e0_31_nf;
+extern cpuop_func op_55e0_31_ff;
+extern cpuop_func op_55e8_31_nf;
+extern cpuop_func op_55e8_31_ff;
+extern cpuop_func op_55f0_31_nf;
+extern cpuop_func op_55f0_31_ff;
+extern cpuop_func op_55f8_31_nf;
+extern cpuop_func op_55f8_31_ff;
+extern cpuop_func op_55f9_31_nf;
+extern cpuop_func op_55f9_31_ff;
+extern cpuop_func op_55fa_31_nf;
+extern cpuop_func op_55fa_31_ff;
+extern cpuop_func op_55fb_31_nf;
+extern cpuop_func op_55fb_31_ff;
+extern cpuop_func op_55fc_31_nf;
+extern cpuop_func op_55fc_31_ff;
+extern cpuop_func op_56c0_31_nf;
+extern cpuop_func op_56c0_31_ff;
+extern cpuop_func op_56c8_31_nf;
+extern cpuop_func op_56c8_31_ff;
+extern cpuop_func op_56d0_31_nf;
+extern cpuop_func op_56d0_31_ff;
+extern cpuop_func op_56d8_31_nf;
+extern cpuop_func op_56d8_31_ff;
+extern cpuop_func op_56e0_31_nf;
+extern cpuop_func op_56e0_31_ff;
+extern cpuop_func op_56e8_31_nf;
+extern cpuop_func op_56e8_31_ff;
+extern cpuop_func op_56f0_31_nf;
+extern cpuop_func op_56f0_31_ff;
+extern cpuop_func op_56f8_31_nf;
+extern cpuop_func op_56f8_31_ff;
+extern cpuop_func op_56f9_31_nf;
+extern cpuop_func op_56f9_31_ff;
+extern cpuop_func op_56fa_31_nf;
+extern cpuop_func op_56fa_31_ff;
+extern cpuop_func op_56fb_31_nf;
+extern cpuop_func op_56fb_31_ff;
+extern cpuop_func op_56fc_31_nf;
+extern cpuop_func op_56fc_31_ff;
+extern cpuop_func op_57c0_31_nf;
+extern cpuop_func op_57c0_31_ff;
+extern cpuop_func op_57c8_31_nf;
+extern cpuop_func op_57c8_31_ff;
+extern cpuop_func op_57d0_31_nf;
+extern cpuop_func op_57d0_31_ff;
+extern cpuop_func op_57d8_31_nf;
+extern cpuop_func op_57d8_31_ff;
+extern cpuop_func op_57e0_31_nf;
+extern cpuop_func op_57e0_31_ff;
+extern cpuop_func op_57e8_31_nf;
+extern cpuop_func op_57e8_31_ff;
+extern cpuop_func op_57f0_31_nf;
+extern cpuop_func op_57f0_31_ff;
+extern cpuop_func op_57f8_31_nf;
+extern cpuop_func op_57f8_31_ff;
+extern cpuop_func op_57f9_31_nf;
+extern cpuop_func op_57f9_31_ff;
+extern cpuop_func op_57fa_31_nf;
+extern cpuop_func op_57fa_31_ff;
+extern cpuop_func op_57fb_31_nf;
+extern cpuop_func op_57fb_31_ff;
+extern cpuop_func op_57fc_31_nf;
+extern cpuop_func op_57fc_31_ff;
+extern cpuop_func op_58c0_31_nf;
+extern cpuop_func op_58c0_31_ff;
+extern cpuop_func op_58c8_31_nf;
+extern cpuop_func op_58c8_31_ff;
+extern cpuop_func op_58d0_31_nf;
+extern cpuop_func op_58d0_31_ff;
+extern cpuop_func op_58d8_31_nf;
+extern cpuop_func op_58d8_31_ff;
+extern cpuop_func op_58e0_31_nf;
+extern cpuop_func op_58e0_31_ff;
+extern cpuop_func op_58e8_31_nf;
+extern cpuop_func op_58e8_31_ff;
+extern cpuop_func op_58f0_31_nf;
+extern cpuop_func op_58f0_31_ff;
+extern cpuop_func op_58f8_31_nf;
+extern cpuop_func op_58f8_31_ff;
+extern cpuop_func op_58f9_31_nf;
+extern cpuop_func op_58f9_31_ff;
+extern cpuop_func op_58fa_31_nf;
+extern cpuop_func op_58fa_31_ff;
+extern cpuop_func op_58fb_31_nf;
+extern cpuop_func op_58fb_31_ff;
+extern cpuop_func op_58fc_31_nf;
+extern cpuop_func op_58fc_31_ff;
+extern cpuop_func op_59c0_31_nf;
+extern cpuop_func op_59c0_31_ff;
+extern cpuop_func op_59c8_31_nf;
+extern cpuop_func op_59c8_31_ff;
+extern cpuop_func op_59d0_31_nf;
+extern cpuop_func op_59d0_31_ff;
+extern cpuop_func op_59d8_31_nf;
+extern cpuop_func op_59d8_31_ff;
+extern cpuop_func op_59e0_31_nf;
+extern cpuop_func op_59e0_31_ff;
+extern cpuop_func op_59e8_31_nf;
+extern cpuop_func op_59e8_31_ff;
+extern cpuop_func op_59f0_31_nf;
+extern cpuop_func op_59f0_31_ff;
+extern cpuop_func op_59f8_31_nf;
+extern cpuop_func op_59f8_31_ff;
+extern cpuop_func op_59f9_31_nf;
+extern cpuop_func op_59f9_31_ff;
+extern cpuop_func op_59fa_31_nf;
+extern cpuop_func op_59fa_31_ff;
+extern cpuop_func op_59fb_31_nf;
+extern cpuop_func op_59fb_31_ff;
+extern cpuop_func op_59fc_31_nf;
+extern cpuop_func op_59fc_31_ff;
+extern cpuop_func op_5ac0_31_nf;
+extern cpuop_func op_5ac0_31_ff;
+extern cpuop_func op_5ac8_31_nf;
+extern cpuop_func op_5ac8_31_ff;
+extern cpuop_func op_5ad0_31_nf;
+extern cpuop_func op_5ad0_31_ff;
+extern cpuop_func op_5ad8_31_nf;
+extern cpuop_func op_5ad8_31_ff;
+extern cpuop_func op_5ae0_31_nf;
+extern cpuop_func op_5ae0_31_ff;
+extern cpuop_func op_5ae8_31_nf;
+extern cpuop_func op_5ae8_31_ff;
+extern cpuop_func op_5af0_31_nf;
+extern cpuop_func op_5af0_31_ff;
+extern cpuop_func op_5af8_31_nf;
+extern cpuop_func op_5af8_31_ff;
+extern cpuop_func op_5af9_31_nf;
+extern cpuop_func op_5af9_31_ff;
+extern cpuop_func op_5afa_31_nf;
+extern cpuop_func op_5afa_31_ff;
+extern cpuop_func op_5afb_31_nf;
+extern cpuop_func op_5afb_31_ff;
+extern cpuop_func op_5afc_31_nf;
+extern cpuop_func op_5afc_31_ff;
+extern cpuop_func op_5bc0_31_nf;
+extern cpuop_func op_5bc0_31_ff;
+extern cpuop_func op_5bc8_31_nf;
+extern cpuop_func op_5bc8_31_ff;
+extern cpuop_func op_5bd0_31_nf;
+extern cpuop_func op_5bd0_31_ff;
+extern cpuop_func op_5bd8_31_nf;
+extern cpuop_func op_5bd8_31_ff;
+extern cpuop_func op_5be0_31_nf;
+extern cpuop_func op_5be0_31_ff;
+extern cpuop_func op_5be8_31_nf;
+extern cpuop_func op_5be8_31_ff;
+extern cpuop_func op_5bf0_31_nf;
+extern cpuop_func op_5bf0_31_ff;
+extern cpuop_func op_5bf8_31_nf;
+extern cpuop_func op_5bf8_31_ff;
+extern cpuop_func op_5bf9_31_nf;
+extern cpuop_func op_5bf9_31_ff;
+extern cpuop_func op_5bfa_31_nf;
+extern cpuop_func op_5bfa_31_ff;
+extern cpuop_func op_5bfb_31_nf;
+extern cpuop_func op_5bfb_31_ff;
+extern cpuop_func op_5bfc_31_nf;
+extern cpuop_func op_5bfc_31_ff;
+extern cpuop_func op_5cc0_31_nf;
+extern cpuop_func op_5cc0_31_ff;
+extern cpuop_func op_5cc8_31_nf;
+extern cpuop_func op_5cc8_31_ff;
+extern cpuop_func op_5cd0_31_nf;
+extern cpuop_func op_5cd0_31_ff;
+extern cpuop_func op_5cd8_31_nf;
+extern cpuop_func op_5cd8_31_ff;
+extern cpuop_func op_5ce0_31_nf;
+extern cpuop_func op_5ce0_31_ff;
+extern cpuop_func op_5ce8_31_nf;
+extern cpuop_func op_5ce8_31_ff;
+extern cpuop_func op_5cf0_31_nf;
+extern cpuop_func op_5cf0_31_ff;
+extern cpuop_func op_5cf8_31_nf;
+extern cpuop_func op_5cf8_31_ff;
+extern cpuop_func op_5cf9_31_nf;
+extern cpuop_func op_5cf9_31_ff;
+extern cpuop_func op_5cfa_31_nf;
+extern cpuop_func op_5cfa_31_ff;
+extern cpuop_func op_5cfb_31_nf;
+extern cpuop_func op_5cfb_31_ff;
+extern cpuop_func op_5cfc_31_nf;
+extern cpuop_func op_5cfc_31_ff;
+extern cpuop_func op_5dc0_31_nf;
+extern cpuop_func op_5dc0_31_ff;
+extern cpuop_func op_5dc8_31_nf;
+extern cpuop_func op_5dc8_31_ff;
+extern cpuop_func op_5dd0_31_nf;
+extern cpuop_func op_5dd0_31_ff;
+extern cpuop_func op_5dd8_31_nf;
+extern cpuop_func op_5dd8_31_ff;
+extern cpuop_func op_5de0_31_nf;
+extern cpuop_func op_5de0_31_ff;
+extern cpuop_func op_5de8_31_nf;
+extern cpuop_func op_5de8_31_ff;
+extern cpuop_func op_5df0_31_nf;
+extern cpuop_func op_5df0_31_ff;
+extern cpuop_func op_5df8_31_nf;
+extern cpuop_func op_5df8_31_ff;
+extern cpuop_func op_5df9_31_nf;
+extern cpuop_func op_5df9_31_ff;
+extern cpuop_func op_5dfa_31_nf;
+extern cpuop_func op_5dfa_31_ff;
+extern cpuop_func op_5dfb_31_nf;
+extern cpuop_func op_5dfb_31_ff;
+extern cpuop_func op_5dfc_31_nf;
+extern cpuop_func op_5dfc_31_ff;
+extern cpuop_func op_5ec0_31_nf;
+extern cpuop_func op_5ec0_31_ff;
+extern cpuop_func op_5ec8_31_nf;
+extern cpuop_func op_5ec8_31_ff;
+extern cpuop_func op_5ed0_31_nf;
+extern cpuop_func op_5ed0_31_ff;
+extern cpuop_func op_5ed8_31_nf;
+extern cpuop_func op_5ed8_31_ff;
+extern cpuop_func op_5ee0_31_nf;
+extern cpuop_func op_5ee0_31_ff;
+extern cpuop_func op_5ee8_31_nf;
+extern cpuop_func op_5ee8_31_ff;
+extern cpuop_func op_5ef0_31_nf;
+extern cpuop_func op_5ef0_31_ff;
+extern cpuop_func op_5ef8_31_nf;
+extern cpuop_func op_5ef8_31_ff;
+extern cpuop_func op_5ef9_31_nf;
+extern cpuop_func op_5ef9_31_ff;
+extern cpuop_func op_5efa_31_nf;
+extern cpuop_func op_5efa_31_ff;
+extern cpuop_func op_5efb_31_nf;
+extern cpuop_func op_5efb_31_ff;
+extern cpuop_func op_5efc_31_nf;
+extern cpuop_func op_5efc_31_ff;
+extern cpuop_func op_5fc0_31_nf;
+extern cpuop_func op_5fc0_31_ff;
+extern cpuop_func op_5fc8_31_nf;
+extern cpuop_func op_5fc8_31_ff;
+extern cpuop_func op_5fd0_31_nf;
+extern cpuop_func op_5fd0_31_ff;
+extern cpuop_func op_5fd8_31_nf;
+extern cpuop_func op_5fd8_31_ff;
+extern cpuop_func op_5fe0_31_nf;
+extern cpuop_func op_5fe0_31_ff;
+extern cpuop_func op_5fe8_31_nf;
+extern cpuop_func op_5fe8_31_ff;
+extern cpuop_func op_5ff0_31_nf;
+extern cpuop_func op_5ff0_31_ff;
+extern cpuop_func op_5ff8_31_nf;
+extern cpuop_func op_5ff8_31_ff;
+extern cpuop_func op_5ff9_31_nf;
+extern cpuop_func op_5ff9_31_ff;
+extern cpuop_func op_5ffa_31_nf;
+extern cpuop_func op_5ffa_31_ff;
+extern cpuop_func op_5ffb_31_nf;
+extern cpuop_func op_5ffb_31_ff;
+extern cpuop_func op_5ffc_31_nf;
+extern cpuop_func op_5ffc_31_ff;
+extern cpuop_func op_6000_31_nf;
+extern cpuop_func op_6000_31_ff;
+extern cpuop_func op_6001_31_nf;
+extern cpuop_func op_6001_31_ff;
+extern cpuop_func op_60ff_31_nf;
+extern cpuop_func op_60ff_31_ff;
+extern cpuop_func op_6100_31_nf;
+extern cpuop_func op_6100_31_ff;
+extern cpuop_func op_6101_31_nf;
+extern cpuop_func op_6101_31_ff;
+extern cpuop_func op_61ff_31_nf;
+extern cpuop_func op_61ff_31_ff;
+extern cpuop_func op_6200_31_nf;
+extern cpuop_func op_6200_31_ff;
+extern cpuop_func op_6201_31_nf;
+extern cpuop_func op_6201_31_ff;
+extern cpuop_func op_62ff_31_nf;
+extern cpuop_func op_62ff_31_ff;
+extern cpuop_func op_6300_31_nf;
+extern cpuop_func op_6300_31_ff;
+extern cpuop_func op_6301_31_nf;
+extern cpuop_func op_6301_31_ff;
+extern cpuop_func op_63ff_31_nf;
+extern cpuop_func op_63ff_31_ff;
+extern cpuop_func op_6400_31_nf;
+extern cpuop_func op_6400_31_ff;
+extern cpuop_func op_6401_31_nf;
+extern cpuop_func op_6401_31_ff;
+extern cpuop_func op_64ff_31_nf;
+extern cpuop_func op_64ff_31_ff;
+extern cpuop_func op_6500_31_nf;
+extern cpuop_func op_6500_31_ff;
+extern cpuop_func op_6501_31_nf;
+extern cpuop_func op_6501_31_ff;
+extern cpuop_func op_65ff_31_nf;
+extern cpuop_func op_65ff_31_ff;
+extern cpuop_func op_6600_31_nf;
+extern cpuop_func op_6600_31_ff;
+extern cpuop_func op_6601_31_nf;
+extern cpuop_func op_6601_31_ff;
+extern cpuop_func op_66ff_31_nf;
+extern cpuop_func op_66ff_31_ff;
+extern cpuop_func op_6700_31_nf;
+extern cpuop_func op_6700_31_ff;
+extern cpuop_func op_6701_31_nf;
+extern cpuop_func op_6701_31_ff;
+extern cpuop_func op_67ff_31_nf;
+extern cpuop_func op_67ff_31_ff;
+extern cpuop_func op_6800_31_nf;
+extern cpuop_func op_6800_31_ff;
+extern cpuop_func op_6801_31_nf;
+extern cpuop_func op_6801_31_ff;
+extern cpuop_func op_68ff_31_nf;
+extern cpuop_func op_68ff_31_ff;
+extern cpuop_func op_6900_31_nf;
+extern cpuop_func op_6900_31_ff;
+extern cpuop_func op_6901_31_nf;
+extern cpuop_func op_6901_31_ff;
+extern cpuop_func op_69ff_31_nf;
+extern cpuop_func op_69ff_31_ff;
+extern cpuop_func op_6a00_31_nf;
+extern cpuop_func op_6a00_31_ff;
+extern cpuop_func op_6a01_31_nf;
+extern cpuop_func op_6a01_31_ff;
+extern cpuop_func op_6aff_31_nf;
+extern cpuop_func op_6aff_31_ff;
+extern cpuop_func op_6b00_31_nf;
+extern cpuop_func op_6b00_31_ff;
+extern cpuop_func op_6b01_31_nf;
+extern cpuop_func op_6b01_31_ff;
+extern cpuop_func op_6bff_31_nf;
+extern cpuop_func op_6bff_31_ff;
+extern cpuop_func op_6c00_31_nf;
+extern cpuop_func op_6c00_31_ff;
+extern cpuop_func op_6c01_31_nf;
+extern cpuop_func op_6c01_31_ff;
+extern cpuop_func op_6cff_31_nf;
+extern cpuop_func op_6cff_31_ff;
+extern cpuop_func op_6d00_31_nf;
+extern cpuop_func op_6d00_31_ff;
+extern cpuop_func op_6d01_31_nf;
+extern cpuop_func op_6d01_31_ff;
+extern cpuop_func op_6dff_31_nf;
+extern cpuop_func op_6dff_31_ff;
+extern cpuop_func op_6e00_31_nf;
+extern cpuop_func op_6e00_31_ff;
+extern cpuop_func op_6e01_31_nf;
+extern cpuop_func op_6e01_31_ff;
+extern cpuop_func op_6eff_31_nf;
+extern cpuop_func op_6eff_31_ff;
+extern cpuop_func op_6f00_31_nf;
+extern cpuop_func op_6f00_31_ff;
+extern cpuop_func op_6f01_31_nf;
+extern cpuop_func op_6f01_31_ff;
+extern cpuop_func op_6fff_31_nf;
+extern cpuop_func op_6fff_31_ff;
+extern cpuop_func op_7000_31_nf;
+extern cpuop_func op_7000_31_ff;
+extern cpuop_func op_8000_31_nf;
+extern cpuop_func op_8000_31_ff;
+extern cpuop_func op_8010_31_nf;
+extern cpuop_func op_8010_31_ff;
+extern cpuop_func op_8018_31_nf;
+extern cpuop_func op_8018_31_ff;
+extern cpuop_func op_8020_31_nf;
+extern cpuop_func op_8020_31_ff;
+extern cpuop_func op_8028_31_nf;
+extern cpuop_func op_8028_31_ff;
+extern cpuop_func op_8030_31_nf;
+extern cpuop_func op_8030_31_ff;
+extern cpuop_func op_8038_31_nf;
+extern cpuop_func op_8038_31_ff;
+extern cpuop_func op_8039_31_nf;
+extern cpuop_func op_8039_31_ff;
+extern cpuop_func op_803a_31_nf;
+extern cpuop_func op_803a_31_ff;
+extern cpuop_func op_803b_31_nf;
+extern cpuop_func op_803b_31_ff;
+extern cpuop_func op_803c_31_nf;
+extern cpuop_func op_803c_31_ff;
+extern cpuop_func op_8040_31_nf;
+extern cpuop_func op_8040_31_ff;
+extern cpuop_func op_8050_31_nf;
+extern cpuop_func op_8050_31_ff;
+extern cpuop_func op_8058_31_nf;
+extern cpuop_func op_8058_31_ff;
+extern cpuop_func op_8060_31_nf;
+extern cpuop_func op_8060_31_ff;
+extern cpuop_func op_8068_31_nf;
+extern cpuop_func op_8068_31_ff;
+extern cpuop_func op_8070_31_nf;
+extern cpuop_func op_8070_31_ff;
+extern cpuop_func op_8078_31_nf;
+extern cpuop_func op_8078_31_ff;
+extern cpuop_func op_8079_31_nf;
+extern cpuop_func op_8079_31_ff;
+extern cpuop_func op_807a_31_nf;
+extern cpuop_func op_807a_31_ff;
+extern cpuop_func op_807b_31_nf;
+extern cpuop_func op_807b_31_ff;
+extern cpuop_func op_807c_31_nf;
+extern cpuop_func op_807c_31_ff;
+extern cpuop_func op_8080_31_nf;
+extern cpuop_func op_8080_31_ff;
+extern cpuop_func op_8090_31_nf;
+extern cpuop_func op_8090_31_ff;
+extern cpuop_func op_8098_31_nf;
+extern cpuop_func op_8098_31_ff;
+extern cpuop_func op_80a0_31_nf;
+extern cpuop_func op_80a0_31_ff;
+extern cpuop_func op_80a8_31_nf;
+extern cpuop_func op_80a8_31_ff;
+extern cpuop_func op_80b0_31_nf;
+extern cpuop_func op_80b0_31_ff;
+extern cpuop_func op_80b8_31_nf;
+extern cpuop_func op_80b8_31_ff;
+extern cpuop_func op_80b9_31_nf;
+extern cpuop_func op_80b9_31_ff;
+extern cpuop_func op_80ba_31_nf;
+extern cpuop_func op_80ba_31_ff;
+extern cpuop_func op_80bb_31_nf;
+extern cpuop_func op_80bb_31_ff;
+extern cpuop_func op_80bc_31_nf;
+extern cpuop_func op_80bc_31_ff;
+extern cpuop_func op_80c0_31_nf;
+extern cpuop_func op_80c0_31_ff;
+extern cpuop_func op_80d0_31_nf;
+extern cpuop_func op_80d0_31_ff;
+extern cpuop_func op_80d8_31_nf;
+extern cpuop_func op_80d8_31_ff;
+extern cpuop_func op_80e0_31_nf;
+extern cpuop_func op_80e0_31_ff;
+extern cpuop_func op_80e8_31_nf;
+extern cpuop_func op_80e8_31_ff;
+extern cpuop_func op_80f0_31_nf;
+extern cpuop_func op_80f0_31_ff;
+extern cpuop_func op_80f8_31_nf;
+extern cpuop_func op_80f8_31_ff;
+extern cpuop_func op_80f9_31_nf;
+extern cpuop_func op_80f9_31_ff;
+extern cpuop_func op_80fa_31_nf;
+extern cpuop_func op_80fa_31_ff;
+extern cpuop_func op_80fb_31_nf;
+extern cpuop_func op_80fb_31_ff;
+extern cpuop_func op_80fc_31_nf;
+extern cpuop_func op_80fc_31_ff;
+extern cpuop_func op_8100_31_nf;
+extern cpuop_func op_8100_31_ff;
+extern cpuop_func op_8108_31_nf;
+extern cpuop_func op_8108_31_ff;
+extern cpuop_func op_8110_31_nf;
+extern cpuop_func op_8110_31_ff;
+extern cpuop_func op_8118_31_nf;
+extern cpuop_func op_8118_31_ff;
+extern cpuop_func op_8120_31_nf;
+extern cpuop_func op_8120_31_ff;
+extern cpuop_func op_8128_31_nf;
+extern cpuop_func op_8128_31_ff;
+extern cpuop_func op_8130_31_nf;
+extern cpuop_func op_8130_31_ff;
+extern cpuop_func op_8138_31_nf;
+extern cpuop_func op_8138_31_ff;
+extern cpuop_func op_8139_31_nf;
+extern cpuop_func op_8139_31_ff;
+extern cpuop_func op_8140_31_nf;
+extern cpuop_func op_8140_31_ff;
+extern cpuop_func op_8148_31_nf;
+extern cpuop_func op_8148_31_ff;
+extern cpuop_func op_8150_31_nf;
+extern cpuop_func op_8150_31_ff;
+extern cpuop_func op_8158_31_nf;
+extern cpuop_func op_8158_31_ff;
+extern cpuop_func op_8160_31_nf;
+extern cpuop_func op_8160_31_ff;
+extern cpuop_func op_8168_31_nf;
+extern cpuop_func op_8168_31_ff;
+extern cpuop_func op_8170_31_nf;
+extern cpuop_func op_8170_31_ff;
+extern cpuop_func op_8178_31_nf;
+extern cpuop_func op_8178_31_ff;
+extern cpuop_func op_8179_31_nf;
+extern cpuop_func op_8179_31_ff;
+extern cpuop_func op_8180_31_nf;
+extern cpuop_func op_8180_31_ff;
+extern cpuop_func op_8188_31_nf;
+extern cpuop_func op_8188_31_ff;
+extern cpuop_func op_8190_31_nf;
+extern cpuop_func op_8190_31_ff;
+extern cpuop_func op_8198_31_nf;
+extern cpuop_func op_8198_31_ff;
+extern cpuop_func op_81a0_31_nf;
+extern cpuop_func op_81a0_31_ff;
+extern cpuop_func op_81a8_31_nf;
+extern cpuop_func op_81a8_31_ff;
+extern cpuop_func op_81b0_31_nf;
+extern cpuop_func op_81b0_31_ff;
+extern cpuop_func op_81b8_31_nf;
+extern cpuop_func op_81b8_31_ff;
+extern cpuop_func op_81b9_31_nf;
+extern cpuop_func op_81b9_31_ff;
+extern cpuop_func op_81c0_31_nf;
+extern cpuop_func op_81c0_31_ff;
+extern cpuop_func op_81d0_31_nf;
+extern cpuop_func op_81d0_31_ff;
+extern cpuop_func op_81d8_31_nf;
+extern cpuop_func op_81d8_31_ff;
+extern cpuop_func op_81e0_31_nf;
+extern cpuop_func op_81e0_31_ff;
+extern cpuop_func op_81e8_31_nf;
+extern cpuop_func op_81e8_31_ff;
+extern cpuop_func op_81f0_31_nf;
+extern cpuop_func op_81f0_31_ff;
+extern cpuop_func op_81f8_31_nf;
+extern cpuop_func op_81f8_31_ff;
+extern cpuop_func op_81f9_31_nf;
+extern cpuop_func op_81f9_31_ff;
+extern cpuop_func op_81fa_31_nf;
+extern cpuop_func op_81fa_31_ff;
+extern cpuop_func op_81fb_31_nf;
+extern cpuop_func op_81fb_31_ff;
+extern cpuop_func op_81fc_31_nf;
+extern cpuop_func op_81fc_31_ff;
+extern cpuop_func op_9000_31_nf;
+extern cpuop_func op_9000_31_ff;
+extern cpuop_func op_9010_31_nf;
+extern cpuop_func op_9010_31_ff;
+extern cpuop_func op_9018_31_nf;
+extern cpuop_func op_9018_31_ff;
+extern cpuop_func op_9020_31_nf;
+extern cpuop_func op_9020_31_ff;
+extern cpuop_func op_9028_31_nf;
+extern cpuop_func op_9028_31_ff;
+extern cpuop_func op_9030_31_nf;
+extern cpuop_func op_9030_31_ff;
+extern cpuop_func op_9038_31_nf;
+extern cpuop_func op_9038_31_ff;
+extern cpuop_func op_9039_31_nf;
+extern cpuop_func op_9039_31_ff;
+extern cpuop_func op_903a_31_nf;
+extern cpuop_func op_903a_31_ff;
+extern cpuop_func op_903b_31_nf;
+extern cpuop_func op_903b_31_ff;
+extern cpuop_func op_903c_31_nf;
+extern cpuop_func op_903c_31_ff;
+extern cpuop_func op_9040_31_nf;
+extern cpuop_func op_9040_31_ff;
+extern cpuop_func op_9048_31_nf;
+extern cpuop_func op_9048_31_ff;
+extern cpuop_func op_9050_31_nf;
+extern cpuop_func op_9050_31_ff;
+extern cpuop_func op_9058_31_nf;
+extern cpuop_func op_9058_31_ff;
+extern cpuop_func op_9060_31_nf;
+extern cpuop_func op_9060_31_ff;
+extern cpuop_func op_9068_31_nf;
+extern cpuop_func op_9068_31_ff;
+extern cpuop_func op_9070_31_nf;
+extern cpuop_func op_9070_31_ff;
+extern cpuop_func op_9078_31_nf;
+extern cpuop_func op_9078_31_ff;
+extern cpuop_func op_9079_31_nf;
+extern cpuop_func op_9079_31_ff;
+extern cpuop_func op_907a_31_nf;
+extern cpuop_func op_907a_31_ff;
+extern cpuop_func op_907b_31_nf;
+extern cpuop_func op_907b_31_ff;
+extern cpuop_func op_907c_31_nf;
+extern cpuop_func op_907c_31_ff;
+extern cpuop_func op_9080_31_nf;
+extern cpuop_func op_9080_31_ff;
+extern cpuop_func op_9088_31_nf;
+extern cpuop_func op_9088_31_ff;
+extern cpuop_func op_9090_31_nf;
+extern cpuop_func op_9090_31_ff;
+extern cpuop_func op_9098_31_nf;
+extern cpuop_func op_9098_31_ff;
+extern cpuop_func op_90a0_31_nf;
+extern cpuop_func op_90a0_31_ff;
+extern cpuop_func op_90a8_31_nf;
+extern cpuop_func op_90a8_31_ff;
+extern cpuop_func op_90b0_31_nf;
+extern cpuop_func op_90b0_31_ff;
+extern cpuop_func op_90b8_31_nf;
+extern cpuop_func op_90b8_31_ff;
+extern cpuop_func op_90b9_31_nf;
+extern cpuop_func op_90b9_31_ff;
+extern cpuop_func op_90ba_31_nf;
+extern cpuop_func op_90ba_31_ff;
+extern cpuop_func op_90bb_31_nf;
+extern cpuop_func op_90bb_31_ff;
+extern cpuop_func op_90bc_31_nf;
+extern cpuop_func op_90bc_31_ff;
+extern cpuop_func op_90c0_31_nf;
+extern cpuop_func op_90c0_31_ff;
+extern cpuop_func op_90c8_31_nf;
+extern cpuop_func op_90c8_31_ff;
+extern cpuop_func op_90d0_31_nf;
+extern cpuop_func op_90d0_31_ff;
+extern cpuop_func op_90d8_31_nf;
+extern cpuop_func op_90d8_31_ff;
+extern cpuop_func op_90e0_31_nf;
+extern cpuop_func op_90e0_31_ff;
+extern cpuop_func op_90e8_31_nf;
+extern cpuop_func op_90e8_31_ff;
+extern cpuop_func op_90f0_31_nf;
+extern cpuop_func op_90f0_31_ff;
+extern cpuop_func op_90f8_31_nf;
+extern cpuop_func op_90f8_31_ff;
+extern cpuop_func op_90f9_31_nf;
+extern cpuop_func op_90f9_31_ff;
+extern cpuop_func op_90fa_31_nf;
+extern cpuop_func op_90fa_31_ff;
+extern cpuop_func op_90fb_31_nf;
+extern cpuop_func op_90fb_31_ff;
+extern cpuop_func op_90fc_31_nf;
+extern cpuop_func op_90fc_31_ff;
+extern cpuop_func op_9100_31_nf;
+extern cpuop_func op_9100_31_ff;
+extern cpuop_func op_9108_31_nf;
+extern cpuop_func op_9108_31_ff;
+extern cpuop_func op_9110_31_nf;
+extern cpuop_func op_9110_31_ff;
+extern cpuop_func op_9118_31_nf;
+extern cpuop_func op_9118_31_ff;
+extern cpuop_func op_9120_31_nf;
+extern cpuop_func op_9120_31_ff;
+extern cpuop_func op_9128_31_nf;
+extern cpuop_func op_9128_31_ff;
+extern cpuop_func op_9130_31_nf;
+extern cpuop_func op_9130_31_ff;
+extern cpuop_func op_9138_31_nf;
+extern cpuop_func op_9138_31_ff;
+extern cpuop_func op_9139_31_nf;
+extern cpuop_func op_9139_31_ff;
+extern cpuop_func op_9140_31_nf;
+extern cpuop_func op_9140_31_ff;
+extern cpuop_func op_9148_31_nf;
+extern cpuop_func op_9148_31_ff;
+extern cpuop_func op_9150_31_nf;
+extern cpuop_func op_9150_31_ff;
+extern cpuop_func op_9158_31_nf;
+extern cpuop_func op_9158_31_ff;
+extern cpuop_func op_9160_31_nf;
+extern cpuop_func op_9160_31_ff;
+extern cpuop_func op_9168_31_nf;
+extern cpuop_func op_9168_31_ff;
+extern cpuop_func op_9170_31_nf;
+extern cpuop_func op_9170_31_ff;
+extern cpuop_func op_9178_31_nf;
+extern cpuop_func op_9178_31_ff;
+extern cpuop_func op_9179_31_nf;
+extern cpuop_func op_9179_31_ff;
+extern cpuop_func op_9180_31_nf;
+extern cpuop_func op_9180_31_ff;
+extern cpuop_func op_9188_31_nf;
+extern cpuop_func op_9188_31_ff;
+extern cpuop_func op_9190_31_nf;
+extern cpuop_func op_9190_31_ff;
+extern cpuop_func op_9198_31_nf;
+extern cpuop_func op_9198_31_ff;
+extern cpuop_func op_91a0_31_nf;
+extern cpuop_func op_91a0_31_ff;
+extern cpuop_func op_91a8_31_nf;
+extern cpuop_func op_91a8_31_ff;
+extern cpuop_func op_91b0_31_nf;
+extern cpuop_func op_91b0_31_ff;
+extern cpuop_func op_91b8_31_nf;
+extern cpuop_func op_91b8_31_ff;
+extern cpuop_func op_91b9_31_nf;
+extern cpuop_func op_91b9_31_ff;
+extern cpuop_func op_91c0_31_nf;
+extern cpuop_func op_91c0_31_ff;
+extern cpuop_func op_91c8_31_nf;
+extern cpuop_func op_91c8_31_ff;
+extern cpuop_func op_91d0_31_nf;
+extern cpuop_func op_91d0_31_ff;
+extern cpuop_func op_91d8_31_nf;
+extern cpuop_func op_91d8_31_ff;
+extern cpuop_func op_91e0_31_nf;
+extern cpuop_func op_91e0_31_ff;
+extern cpuop_func op_91e8_31_nf;
+extern cpuop_func op_91e8_31_ff;
+extern cpuop_func op_91f0_31_nf;
+extern cpuop_func op_91f0_31_ff;
+extern cpuop_func op_91f8_31_nf;
+extern cpuop_func op_91f8_31_ff;
+extern cpuop_func op_91f9_31_nf;
+extern cpuop_func op_91f9_31_ff;
+extern cpuop_func op_91fa_31_nf;
+extern cpuop_func op_91fa_31_ff;
+extern cpuop_func op_91fb_31_nf;
+extern cpuop_func op_91fb_31_ff;
+extern cpuop_func op_91fc_31_nf;
+extern cpuop_func op_91fc_31_ff;
+extern cpuop_func op_b000_31_nf;
+extern cpuop_func op_b000_31_ff;
+extern cpuop_func op_b010_31_nf;
+extern cpuop_func op_b010_31_ff;
+extern cpuop_func op_b018_31_nf;
+extern cpuop_func op_b018_31_ff;
+extern cpuop_func op_b020_31_nf;
+extern cpuop_func op_b020_31_ff;
+extern cpuop_func op_b028_31_nf;
+extern cpuop_func op_b028_31_ff;
+extern cpuop_func op_b030_31_nf;
+extern cpuop_func op_b030_31_ff;
+extern cpuop_func op_b038_31_nf;
+extern cpuop_func op_b038_31_ff;
+extern cpuop_func op_b039_31_nf;
+extern cpuop_func op_b039_31_ff;
+extern cpuop_func op_b03a_31_nf;
+extern cpuop_func op_b03a_31_ff;
+extern cpuop_func op_b03b_31_nf;
+extern cpuop_func op_b03b_31_ff;
+extern cpuop_func op_b03c_31_nf;
+extern cpuop_func op_b03c_31_ff;
+extern cpuop_func op_b040_31_nf;
+extern cpuop_func op_b040_31_ff;
+extern cpuop_func op_b048_31_nf;
+extern cpuop_func op_b048_31_ff;
+extern cpuop_func op_b050_31_nf;
+extern cpuop_func op_b050_31_ff;
+extern cpuop_func op_b058_31_nf;
+extern cpuop_func op_b058_31_ff;
+extern cpuop_func op_b060_31_nf;
+extern cpuop_func op_b060_31_ff;
+extern cpuop_func op_b068_31_nf;
+extern cpuop_func op_b068_31_ff;
+extern cpuop_func op_b070_31_nf;
+extern cpuop_func op_b070_31_ff;
+extern cpuop_func op_b078_31_nf;
+extern cpuop_func op_b078_31_ff;
+extern cpuop_func op_b079_31_nf;
+extern cpuop_func op_b079_31_ff;
+extern cpuop_func op_b07a_31_nf;
+extern cpuop_func op_b07a_31_ff;
+extern cpuop_func op_b07b_31_nf;
+extern cpuop_func op_b07b_31_ff;
+extern cpuop_func op_b07c_31_nf;
+extern cpuop_func op_b07c_31_ff;
+extern cpuop_func op_b080_31_nf;
+extern cpuop_func op_b080_31_ff;
+extern cpuop_func op_b088_31_nf;
+extern cpuop_func op_b088_31_ff;
+extern cpuop_func op_b090_31_nf;
+extern cpuop_func op_b090_31_ff;
+extern cpuop_func op_b098_31_nf;
+extern cpuop_func op_b098_31_ff;
+extern cpuop_func op_b0a0_31_nf;
+extern cpuop_func op_b0a0_31_ff;
+extern cpuop_func op_b0a8_31_nf;
+extern cpuop_func op_b0a8_31_ff;
+extern cpuop_func op_b0b0_31_nf;
+extern cpuop_func op_b0b0_31_ff;
+extern cpuop_func op_b0b8_31_nf;
+extern cpuop_func op_b0b8_31_ff;
+extern cpuop_func op_b0b9_31_nf;
+extern cpuop_func op_b0b9_31_ff;
+extern cpuop_func op_b0ba_31_nf;
+extern cpuop_func op_b0ba_31_ff;
+extern cpuop_func op_b0bb_31_nf;
+extern cpuop_func op_b0bb_31_ff;
+extern cpuop_func op_b0bc_31_nf;
+extern cpuop_func op_b0bc_31_ff;
+extern cpuop_func op_b0c0_31_nf;
+extern cpuop_func op_b0c0_31_ff;
+extern cpuop_func op_b0c8_31_nf;
+extern cpuop_func op_b0c8_31_ff;
+extern cpuop_func op_b0d0_31_nf;
+extern cpuop_func op_b0d0_31_ff;
+extern cpuop_func op_b0d8_31_nf;
+extern cpuop_func op_b0d8_31_ff;
+extern cpuop_func op_b0e0_31_nf;
+extern cpuop_func op_b0e0_31_ff;
+extern cpuop_func op_b0e8_31_nf;
+extern cpuop_func op_b0e8_31_ff;
+extern cpuop_func op_b0f0_31_nf;
+extern cpuop_func op_b0f0_31_ff;
+extern cpuop_func op_b0f8_31_nf;
+extern cpuop_func op_b0f8_31_ff;
+extern cpuop_func op_b0f9_31_nf;
+extern cpuop_func op_b0f9_31_ff;
+extern cpuop_func op_b0fa_31_nf;
+extern cpuop_func op_b0fa_31_ff;
+extern cpuop_func op_b0fb_31_nf;
+extern cpuop_func op_b0fb_31_ff;
+extern cpuop_func op_b0fc_31_nf;
+extern cpuop_func op_b0fc_31_ff;
+extern cpuop_func op_b100_31_nf;
+extern cpuop_func op_b100_31_ff;
+extern cpuop_func op_b108_31_nf;
+extern cpuop_func op_b108_31_ff;
+extern cpuop_func op_b110_31_nf;
+extern cpuop_func op_b110_31_ff;
+extern cpuop_func op_b118_31_nf;
+extern cpuop_func op_b118_31_ff;
+extern cpuop_func op_b120_31_nf;
+extern cpuop_func op_b120_31_ff;
+extern cpuop_func op_b128_31_nf;
+extern cpuop_func op_b128_31_ff;
+extern cpuop_func op_b130_31_nf;
+extern cpuop_func op_b130_31_ff;
+extern cpuop_func op_b138_31_nf;
+extern cpuop_func op_b138_31_ff;
+extern cpuop_func op_b139_31_nf;
+extern cpuop_func op_b139_31_ff;
+extern cpuop_func op_b140_31_nf;
+extern cpuop_func op_b140_31_ff;
+extern cpuop_func op_b148_31_nf;
+extern cpuop_func op_b148_31_ff;
+extern cpuop_func op_b150_31_nf;
+extern cpuop_func op_b150_31_ff;
+extern cpuop_func op_b158_31_nf;
+extern cpuop_func op_b158_31_ff;
+extern cpuop_func op_b160_31_nf;
+extern cpuop_func op_b160_31_ff;
+extern cpuop_func op_b168_31_nf;
+extern cpuop_func op_b168_31_ff;
+extern cpuop_func op_b170_31_nf;
+extern cpuop_func op_b170_31_ff;
+extern cpuop_func op_b178_31_nf;
+extern cpuop_func op_b178_31_ff;
+extern cpuop_func op_b179_31_nf;
+extern cpuop_func op_b179_31_ff;
+extern cpuop_func op_b180_31_nf;
+extern cpuop_func op_b180_31_ff;
+extern cpuop_func op_b188_31_nf;
+extern cpuop_func op_b188_31_ff;
+extern cpuop_func op_b190_31_nf;
+extern cpuop_func op_b190_31_ff;
+extern cpuop_func op_b198_31_nf;
+extern cpuop_func op_b198_31_ff;
+extern cpuop_func op_b1a0_31_nf;
+extern cpuop_func op_b1a0_31_ff;
+extern cpuop_func op_b1a8_31_nf;
+extern cpuop_func op_b1a8_31_ff;
+extern cpuop_func op_b1b0_31_nf;
+extern cpuop_func op_b1b0_31_ff;
+extern cpuop_func op_b1b8_31_nf;
+extern cpuop_func op_b1b8_31_ff;
+extern cpuop_func op_b1b9_31_nf;
+extern cpuop_func op_b1b9_31_ff;
+extern cpuop_func op_b1c0_31_nf;
+extern cpuop_func op_b1c0_31_ff;
+extern cpuop_func op_b1c8_31_nf;
+extern cpuop_func op_b1c8_31_ff;
+extern cpuop_func op_b1d0_31_nf;
+extern cpuop_func op_b1d0_31_ff;
+extern cpuop_func op_b1d8_31_nf;
+extern cpuop_func op_b1d8_31_ff;
+extern cpuop_func op_b1e0_31_nf;
+extern cpuop_func op_b1e0_31_ff;
+extern cpuop_func op_b1e8_31_nf;
+extern cpuop_func op_b1e8_31_ff;
+extern cpuop_func op_b1f0_31_nf;
+extern cpuop_func op_b1f0_31_ff;
+extern cpuop_func op_b1f8_31_nf;
+extern cpuop_func op_b1f8_31_ff;
+extern cpuop_func op_b1f9_31_nf;
+extern cpuop_func op_b1f9_31_ff;
+extern cpuop_func op_b1fa_31_nf;
+extern cpuop_func op_b1fa_31_ff;
+extern cpuop_func op_b1fb_31_nf;
+extern cpuop_func op_b1fb_31_ff;
+extern cpuop_func op_b1fc_31_nf;
+extern cpuop_func op_b1fc_31_ff;
+extern cpuop_func op_c000_31_nf;
+extern cpuop_func op_c000_31_ff;
+extern cpuop_func op_c010_31_nf;
+extern cpuop_func op_c010_31_ff;
+extern cpuop_func op_c018_31_nf;
+extern cpuop_func op_c018_31_ff;
+extern cpuop_func op_c020_31_nf;
+extern cpuop_func op_c020_31_ff;
+extern cpuop_func op_c028_31_nf;
+extern cpuop_func op_c028_31_ff;
+extern cpuop_func op_c030_31_nf;
+extern cpuop_func op_c030_31_ff;
+extern cpuop_func op_c038_31_nf;
+extern cpuop_func op_c038_31_ff;
+extern cpuop_func op_c039_31_nf;
+extern cpuop_func op_c039_31_ff;
+extern cpuop_func op_c03a_31_nf;
+extern cpuop_func op_c03a_31_ff;
+extern cpuop_func op_c03b_31_nf;
+extern cpuop_func op_c03b_31_ff;
+extern cpuop_func op_c03c_31_nf;
+extern cpuop_func op_c03c_31_ff;
+extern cpuop_func op_c040_31_nf;
+extern cpuop_func op_c040_31_ff;
+extern cpuop_func op_c050_31_nf;
+extern cpuop_func op_c050_31_ff;
+extern cpuop_func op_c058_31_nf;
+extern cpuop_func op_c058_31_ff;
+extern cpuop_func op_c060_31_nf;
+extern cpuop_func op_c060_31_ff;
+extern cpuop_func op_c068_31_nf;
+extern cpuop_func op_c068_31_ff;
+extern cpuop_func op_c070_31_nf;
+extern cpuop_func op_c070_31_ff;
+extern cpuop_func op_c078_31_nf;
+extern cpuop_func op_c078_31_ff;
+extern cpuop_func op_c079_31_nf;
+extern cpuop_func op_c079_31_ff;
+extern cpuop_func op_c07a_31_nf;
+extern cpuop_func op_c07a_31_ff;
+extern cpuop_func op_c07b_31_nf;
+extern cpuop_func op_c07b_31_ff;
+extern cpuop_func op_c07c_31_nf;
+extern cpuop_func op_c07c_31_ff;
+extern cpuop_func op_c080_31_nf;
+extern cpuop_func op_c080_31_ff;
+extern cpuop_func op_c090_31_nf;
+extern cpuop_func op_c090_31_ff;
+extern cpuop_func op_c098_31_nf;
+extern cpuop_func op_c098_31_ff;
+extern cpuop_func op_c0a0_31_nf;
+extern cpuop_func op_c0a0_31_ff;
+extern cpuop_func op_c0a8_31_nf;
+extern cpuop_func op_c0a8_31_ff;
+extern cpuop_func op_c0b0_31_nf;
+extern cpuop_func op_c0b0_31_ff;
+extern cpuop_func op_c0b8_31_nf;
+extern cpuop_func op_c0b8_31_ff;
+extern cpuop_func op_c0b9_31_nf;
+extern cpuop_func op_c0b9_31_ff;
+extern cpuop_func op_c0ba_31_nf;
+extern cpuop_func op_c0ba_31_ff;
+extern cpuop_func op_c0bb_31_nf;
+extern cpuop_func op_c0bb_31_ff;
+extern cpuop_func op_c0bc_31_nf;
+extern cpuop_func op_c0bc_31_ff;
+extern cpuop_func op_c0c0_31_nf;
+extern cpuop_func op_c0c0_31_ff;
+extern cpuop_func op_c0d0_31_nf;
+extern cpuop_func op_c0d0_31_ff;
+extern cpuop_func op_c0d8_31_nf;
+extern cpuop_func op_c0d8_31_ff;
+extern cpuop_func op_c0e0_31_nf;
+extern cpuop_func op_c0e0_31_ff;
+extern cpuop_func op_c0e8_31_nf;
+extern cpuop_func op_c0e8_31_ff;
+extern cpuop_func op_c0f0_31_nf;
+extern cpuop_func op_c0f0_31_ff;
+extern cpuop_func op_c0f8_31_nf;
+extern cpuop_func op_c0f8_31_ff;
+extern cpuop_func op_c0f9_31_nf;
+extern cpuop_func op_c0f9_31_ff;
+extern cpuop_func op_c0fa_31_nf;
+extern cpuop_func op_c0fa_31_ff;
+extern cpuop_func op_c0fb_31_nf;
+extern cpuop_func op_c0fb_31_ff;
+extern cpuop_func op_c0fc_31_nf;
+extern cpuop_func op_c0fc_31_ff;
+extern cpuop_func op_c100_31_nf;
+extern cpuop_func op_c100_31_ff;
+extern cpuop_func op_c108_31_nf;
+extern cpuop_func op_c108_31_ff;
+extern cpuop_func op_c110_31_nf;
+extern cpuop_func op_c110_31_ff;
+extern cpuop_func op_c118_31_nf;
+extern cpuop_func op_c118_31_ff;
+extern cpuop_func op_c120_31_nf;
+extern cpuop_func op_c120_31_ff;
+extern cpuop_func op_c128_31_nf;
+extern cpuop_func op_c128_31_ff;
+extern cpuop_func op_c130_31_nf;
+extern cpuop_func op_c130_31_ff;
+extern cpuop_func op_c138_31_nf;
+extern cpuop_func op_c138_31_ff;
+extern cpuop_func op_c139_31_nf;
+extern cpuop_func op_c139_31_ff;
+extern cpuop_func op_c140_31_nf;
+extern cpuop_func op_c140_31_ff;
+extern cpuop_func op_c148_31_nf;
+extern cpuop_func op_c148_31_ff;
+extern cpuop_func op_c150_31_nf;
+extern cpuop_func op_c150_31_ff;
+extern cpuop_func op_c158_31_nf;
+extern cpuop_func op_c158_31_ff;
+extern cpuop_func op_c160_31_nf;
+extern cpuop_func op_c160_31_ff;
+extern cpuop_func op_c168_31_nf;
+extern cpuop_func op_c168_31_ff;
+extern cpuop_func op_c170_31_nf;
+extern cpuop_func op_c170_31_ff;
+extern cpuop_func op_c178_31_nf;
+extern cpuop_func op_c178_31_ff;
+extern cpuop_func op_c179_31_nf;
+extern cpuop_func op_c179_31_ff;
+extern cpuop_func op_c188_31_nf;
+extern cpuop_func op_c188_31_ff;
+extern cpuop_func op_c190_31_nf;
+extern cpuop_func op_c190_31_ff;
+extern cpuop_func op_c198_31_nf;
+extern cpuop_func op_c198_31_ff;
+extern cpuop_func op_c1a0_31_nf;
+extern cpuop_func op_c1a0_31_ff;
+extern cpuop_func op_c1a8_31_nf;
+extern cpuop_func op_c1a8_31_ff;
+extern cpuop_func op_c1b0_31_nf;
+extern cpuop_func op_c1b0_31_ff;
+extern cpuop_func op_c1b8_31_nf;
+extern cpuop_func op_c1b8_31_ff;
+extern cpuop_func op_c1b9_31_nf;
+extern cpuop_func op_c1b9_31_ff;
+extern cpuop_func op_c1c0_31_nf;
+extern cpuop_func op_c1c0_31_ff;
+extern cpuop_func op_c1d0_31_nf;
+extern cpuop_func op_c1d0_31_ff;
+extern cpuop_func op_c1d8_31_nf;
+extern cpuop_func op_c1d8_31_ff;
+extern cpuop_func op_c1e0_31_nf;
+extern cpuop_func op_c1e0_31_ff;
+extern cpuop_func op_c1e8_31_nf;
+extern cpuop_func op_c1e8_31_ff;
+extern cpuop_func op_c1f0_31_nf;
+extern cpuop_func op_c1f0_31_ff;
+extern cpuop_func op_c1f8_31_nf;
+extern cpuop_func op_c1f8_31_ff;
+extern cpuop_func op_c1f9_31_nf;
+extern cpuop_func op_c1f9_31_ff;
+extern cpuop_func op_c1fa_31_nf;
+extern cpuop_func op_c1fa_31_ff;
+extern cpuop_func op_c1fb_31_nf;
+extern cpuop_func op_c1fb_31_ff;
+extern cpuop_func op_c1fc_31_nf;
+extern cpuop_func op_c1fc_31_ff;
+extern cpuop_func op_d000_31_nf;
+extern cpuop_func op_d000_31_ff;
+extern cpuop_func op_d010_31_nf;
+extern cpuop_func op_d010_31_ff;
+extern cpuop_func op_d018_31_nf;
+extern cpuop_func op_d018_31_ff;
+extern cpuop_func op_d020_31_nf;
+extern cpuop_func op_d020_31_ff;
+extern cpuop_func op_d028_31_nf;
+extern cpuop_func op_d028_31_ff;
+extern cpuop_func op_d030_31_nf;
+extern cpuop_func op_d030_31_ff;
+extern cpuop_func op_d038_31_nf;
+extern cpuop_func op_d038_31_ff;
+extern cpuop_func op_d039_31_nf;
+extern cpuop_func op_d039_31_ff;
+extern cpuop_func op_d03a_31_nf;
+extern cpuop_func op_d03a_31_ff;
+extern cpuop_func op_d03b_31_nf;
+extern cpuop_func op_d03b_31_ff;
+extern cpuop_func op_d03c_31_nf;
+extern cpuop_func op_d03c_31_ff;
+extern cpuop_func op_d040_31_nf;
+extern cpuop_func op_d040_31_ff;
+extern cpuop_func op_d048_31_nf;
+extern cpuop_func op_d048_31_ff;
+extern cpuop_func op_d050_31_nf;
+extern cpuop_func op_d050_31_ff;
+extern cpuop_func op_d058_31_nf;
+extern cpuop_func op_d058_31_ff;
+extern cpuop_func op_d060_31_nf;
+extern cpuop_func op_d060_31_ff;
+extern cpuop_func op_d068_31_nf;
+extern cpuop_func op_d068_31_ff;
+extern cpuop_func op_d070_31_nf;
+extern cpuop_func op_d070_31_ff;
+extern cpuop_func op_d078_31_nf;
+extern cpuop_func op_d078_31_ff;
+extern cpuop_func op_d079_31_nf;
+extern cpuop_func op_d079_31_ff;
+extern cpuop_func op_d07a_31_nf;
+extern cpuop_func op_d07a_31_ff;
+extern cpuop_func op_d07b_31_nf;
+extern cpuop_func op_d07b_31_ff;
+extern cpuop_func op_d07c_31_nf;
+extern cpuop_func op_d07c_31_ff;
+extern cpuop_func op_d080_31_nf;
+extern cpuop_func op_d080_31_ff;
+extern cpuop_func op_d088_31_nf;
+extern cpuop_func op_d088_31_ff;
+extern cpuop_func op_d090_31_nf;
+extern cpuop_func op_d090_31_ff;
+extern cpuop_func op_d098_31_nf;
+extern cpuop_func op_d098_31_ff;
+extern cpuop_func op_d0a0_31_nf;
+extern cpuop_func op_d0a0_31_ff;
+extern cpuop_func op_d0a8_31_nf;
+extern cpuop_func op_d0a8_31_ff;
+extern cpuop_func op_d0b0_31_nf;
+extern cpuop_func op_d0b0_31_ff;
+extern cpuop_func op_d0b8_31_nf;
+extern cpuop_func op_d0b8_31_ff;
+extern cpuop_func op_d0b9_31_nf;
+extern cpuop_func op_d0b9_31_ff;
+extern cpuop_func op_d0ba_31_nf;
+extern cpuop_func op_d0ba_31_ff;
+extern cpuop_func op_d0bb_31_nf;
+extern cpuop_func op_d0bb_31_ff;
+extern cpuop_func op_d0bc_31_nf;
+extern cpuop_func op_d0bc_31_ff;
+extern cpuop_func op_d0c0_31_nf;
+extern cpuop_func op_d0c0_31_ff;
+extern cpuop_func op_d0c8_31_nf;
+extern cpuop_func op_d0c8_31_ff;
+extern cpuop_func op_d0d0_31_nf;
+extern cpuop_func op_d0d0_31_ff;
+extern cpuop_func op_d0d8_31_nf;
+extern cpuop_func op_d0d8_31_ff;
+extern cpuop_func op_d0e0_31_nf;
+extern cpuop_func op_d0e0_31_ff;
+extern cpuop_func op_d0e8_31_nf;
+extern cpuop_func op_d0e8_31_ff;
+extern cpuop_func op_d0f0_31_nf;
+extern cpuop_func op_d0f0_31_ff;
+extern cpuop_func op_d0f8_31_nf;
+extern cpuop_func op_d0f8_31_ff;
+extern cpuop_func op_d0f9_31_nf;
+extern cpuop_func op_d0f9_31_ff;
+extern cpuop_func op_d0fa_31_nf;
+extern cpuop_func op_d0fa_31_ff;
+extern cpuop_func op_d0fb_31_nf;
+extern cpuop_func op_d0fb_31_ff;
+extern cpuop_func op_d0fc_31_nf;
+extern cpuop_func op_d0fc_31_ff;
+extern cpuop_func op_d100_31_nf;
+extern cpuop_func op_d100_31_ff;
+extern cpuop_func op_d108_31_nf;
+extern cpuop_func op_d108_31_ff;
+extern cpuop_func op_d110_31_nf;
+extern cpuop_func op_d110_31_ff;
+extern cpuop_func op_d118_31_nf;
+extern cpuop_func op_d118_31_ff;
+extern cpuop_func op_d120_31_nf;
+extern cpuop_func op_d120_31_ff;
+extern cpuop_func op_d128_31_nf;
+extern cpuop_func op_d128_31_ff;
+extern cpuop_func op_d130_31_nf;
+extern cpuop_func op_d130_31_ff;
+extern cpuop_func op_d138_31_nf;
+extern cpuop_func op_d138_31_ff;
+extern cpuop_func op_d139_31_nf;
+extern cpuop_func op_d139_31_ff;
+extern cpuop_func op_d140_31_nf;
+extern cpuop_func op_d140_31_ff;
+extern cpuop_func op_d148_31_nf;
+extern cpuop_func op_d148_31_ff;
+extern cpuop_func op_d150_31_nf;
+extern cpuop_func op_d150_31_ff;
+extern cpuop_func op_d158_31_nf;
+extern cpuop_func op_d158_31_ff;
+extern cpuop_func op_d160_31_nf;
+extern cpuop_func op_d160_31_ff;
+extern cpuop_func op_d168_31_nf;
+extern cpuop_func op_d168_31_ff;
+extern cpuop_func op_d170_31_nf;
+extern cpuop_func op_d170_31_ff;
+extern cpuop_func op_d178_31_nf;
+extern cpuop_func op_d178_31_ff;
+extern cpuop_func op_d179_31_nf;
+extern cpuop_func op_d179_31_ff;
+extern cpuop_func op_d180_31_nf;
+extern cpuop_func op_d180_31_ff;
+extern cpuop_func op_d188_31_nf;
+extern cpuop_func op_d188_31_ff;
+extern cpuop_func op_d190_31_nf;
+extern cpuop_func op_d190_31_ff;
+extern cpuop_func op_d198_31_nf;
+extern cpuop_func op_d198_31_ff;
+extern cpuop_func op_d1a0_31_nf;
+extern cpuop_func op_d1a0_31_ff;
+extern cpuop_func op_d1a8_31_nf;
+extern cpuop_func op_d1a8_31_ff;
+extern cpuop_func op_d1b0_31_nf;
+extern cpuop_func op_d1b0_31_ff;
+extern cpuop_func op_d1b8_31_nf;
+extern cpuop_func op_d1b8_31_ff;
+extern cpuop_func op_d1b9_31_nf;
+extern cpuop_func op_d1b9_31_ff;
+extern cpuop_func op_d1c0_31_nf;
+extern cpuop_func op_d1c0_31_ff;
+extern cpuop_func op_d1c8_31_nf;
+extern cpuop_func op_d1c8_31_ff;
+extern cpuop_func op_d1d0_31_nf;
+extern cpuop_func op_d1d0_31_ff;
+extern cpuop_func op_d1d8_31_nf;
+extern cpuop_func op_d1d8_31_ff;
+extern cpuop_func op_d1e0_31_nf;
+extern cpuop_func op_d1e0_31_ff;
+extern cpuop_func op_d1e8_31_nf;
+extern cpuop_func op_d1e8_31_ff;
+extern cpuop_func op_d1f0_31_nf;
+extern cpuop_func op_d1f0_31_ff;
+extern cpuop_func op_d1f8_31_nf;
+extern cpuop_func op_d1f8_31_ff;
+extern cpuop_func op_d1f9_31_nf;
+extern cpuop_func op_d1f9_31_ff;
+extern cpuop_func op_d1fa_31_nf;
+extern cpuop_func op_d1fa_31_ff;
+extern cpuop_func op_d1fb_31_nf;
+extern cpuop_func op_d1fb_31_ff;
+extern cpuop_func op_d1fc_31_nf;
+extern cpuop_func op_d1fc_31_ff;
+extern cpuop_func op_e000_31_nf;
+extern cpuop_func op_e000_31_ff;
+extern cpuop_func op_e008_31_nf;
+extern cpuop_func op_e008_31_ff;
+extern cpuop_func op_e010_31_nf;
+extern cpuop_func op_e010_31_ff;
+extern cpuop_func op_e018_31_nf;
+extern cpuop_func op_e018_31_ff;
+extern cpuop_func op_e020_31_nf;
+extern cpuop_func op_e020_31_ff;
+extern cpuop_func op_e028_31_nf;
+extern cpuop_func op_e028_31_ff;
+extern cpuop_func op_e030_31_nf;
+extern cpuop_func op_e030_31_ff;
+extern cpuop_func op_e038_31_nf;
+extern cpuop_func op_e038_31_ff;
+extern cpuop_func op_e040_31_nf;
+extern cpuop_func op_e040_31_ff;
+extern cpuop_func op_e048_31_nf;
+extern cpuop_func op_e048_31_ff;
+extern cpuop_func op_e050_31_nf;
+extern cpuop_func op_e050_31_ff;
+extern cpuop_func op_e058_31_nf;
+extern cpuop_func op_e058_31_ff;
+extern cpuop_func op_e060_31_nf;
+extern cpuop_func op_e060_31_ff;
+extern cpuop_func op_e068_31_nf;
+extern cpuop_func op_e068_31_ff;
+extern cpuop_func op_e070_31_nf;
+extern cpuop_func op_e070_31_ff;
+extern cpuop_func op_e078_31_nf;
+extern cpuop_func op_e078_31_ff;
+extern cpuop_func op_e080_31_nf;
+extern cpuop_func op_e080_31_ff;
+extern cpuop_func op_e088_31_nf;
+extern cpuop_func op_e088_31_ff;
+extern cpuop_func op_e090_31_nf;
+extern cpuop_func op_e090_31_ff;
+extern cpuop_func op_e098_31_nf;
+extern cpuop_func op_e098_31_ff;
+extern cpuop_func op_e0a0_31_nf;
+extern cpuop_func op_e0a0_31_ff;
+extern cpuop_func op_e0a8_31_nf;
+extern cpuop_func op_e0a8_31_ff;
+extern cpuop_func op_e0b0_31_nf;
+extern cpuop_func op_e0b0_31_ff;
+extern cpuop_func op_e0b8_31_nf;
+extern cpuop_func op_e0b8_31_ff;
+extern cpuop_func op_e0d0_31_nf;
+extern cpuop_func op_e0d0_31_ff;
+extern cpuop_func op_e0d8_31_nf;
+extern cpuop_func op_e0d8_31_ff;
+extern cpuop_func op_e0e0_31_nf;
+extern cpuop_func op_e0e0_31_ff;
+extern cpuop_func op_e0e8_31_nf;
+extern cpuop_func op_e0e8_31_ff;
+extern cpuop_func op_e0f0_31_nf;
+extern cpuop_func op_e0f0_31_ff;
+extern cpuop_func op_e0f8_31_nf;
+extern cpuop_func op_e0f8_31_ff;
+extern cpuop_func op_e0f9_31_nf;
+extern cpuop_func op_e0f9_31_ff;
+extern cpuop_func op_e100_31_nf;
+extern cpuop_func op_e100_31_ff;
+extern cpuop_func op_e108_31_nf;
+extern cpuop_func op_e108_31_ff;
+extern cpuop_func op_e110_31_nf;
+extern cpuop_func op_e110_31_ff;
+extern cpuop_func op_e118_31_nf;
+extern cpuop_func op_e118_31_ff;
+extern cpuop_func op_e120_31_nf;
+extern cpuop_func op_e120_31_ff;
+extern cpuop_func op_e128_31_nf;
+extern cpuop_func op_e128_31_ff;
+extern cpuop_func op_e130_31_nf;
+extern cpuop_func op_e130_31_ff;
+extern cpuop_func op_e138_31_nf;
+extern cpuop_func op_e138_31_ff;
+extern cpuop_func op_e140_31_nf;
+extern cpuop_func op_e140_31_ff;
+extern cpuop_func op_e148_31_nf;
+extern cpuop_func op_e148_31_ff;
+extern cpuop_func op_e150_31_nf;
+extern cpuop_func op_e150_31_ff;
+extern cpuop_func op_e158_31_nf;
+extern cpuop_func op_e158_31_ff;
+extern cpuop_func op_e160_31_nf;
+extern cpuop_func op_e160_31_ff;
+extern cpuop_func op_e168_31_nf;
+extern cpuop_func op_e168_31_ff;
+extern cpuop_func op_e170_31_nf;
+extern cpuop_func op_e170_31_ff;
+extern cpuop_func op_e178_31_nf;
+extern cpuop_func op_e178_31_ff;
+extern cpuop_func op_e180_31_nf;
+extern cpuop_func op_e180_31_ff;
+extern cpuop_func op_e188_31_nf;
+extern cpuop_func op_e188_31_ff;
+extern cpuop_func op_e190_31_nf;
+extern cpuop_func op_e190_31_ff;
+extern cpuop_func op_e198_31_nf;
+extern cpuop_func op_e198_31_ff;
+extern cpuop_func op_e1a0_31_nf;
+extern cpuop_func op_e1a0_31_ff;
+extern cpuop_func op_e1a8_31_nf;
+extern cpuop_func op_e1a8_31_ff;
+extern cpuop_func op_e1b0_31_nf;
+extern cpuop_func op_e1b0_31_ff;
+extern cpuop_func op_e1b8_31_nf;
+extern cpuop_func op_e1b8_31_ff;
+extern cpuop_func op_e1d0_31_nf;
+extern cpuop_func op_e1d0_31_ff;
+extern cpuop_func op_e1d8_31_nf;
+extern cpuop_func op_e1d8_31_ff;
+extern cpuop_func op_e1e0_31_nf;
+extern cpuop_func op_e1e0_31_ff;
+extern cpuop_func op_e1e8_31_nf;
+extern cpuop_func op_e1e8_31_ff;
+extern cpuop_func op_e1f0_31_nf;
+extern cpuop_func op_e1f0_31_ff;
+extern cpuop_func op_e1f8_31_nf;
+extern cpuop_func op_e1f8_31_ff;
+extern cpuop_func op_e1f9_31_nf;
+extern cpuop_func op_e1f9_31_ff;
+extern cpuop_func op_e2d0_31_nf;
+extern cpuop_func op_e2d0_31_ff;
+extern cpuop_func op_e2d8_31_nf;
+extern cpuop_func op_e2d8_31_ff;
+extern cpuop_func op_e2e0_31_nf;
+extern cpuop_func op_e2e0_31_ff;
+extern cpuop_func op_e2e8_31_nf;
+extern cpuop_func op_e2e8_31_ff;
+extern cpuop_func op_e2f0_31_nf;
+extern cpuop_func op_e2f0_31_ff;
+extern cpuop_func op_e2f8_31_nf;
+extern cpuop_func op_e2f8_31_ff;
+extern cpuop_func op_e2f9_31_nf;
+extern cpuop_func op_e2f9_31_ff;
+extern cpuop_func op_e3d0_31_nf;
+extern cpuop_func op_e3d0_31_ff;
+extern cpuop_func op_e3d8_31_nf;
+extern cpuop_func op_e3d8_31_ff;
+extern cpuop_func op_e3e0_31_nf;
+extern cpuop_func op_e3e0_31_ff;
+extern cpuop_func op_e3e8_31_nf;
+extern cpuop_func op_e3e8_31_ff;
+extern cpuop_func op_e3f0_31_nf;
+extern cpuop_func op_e3f0_31_ff;
+extern cpuop_func op_e3f8_31_nf;
+extern cpuop_func op_e3f8_31_ff;
+extern cpuop_func op_e3f9_31_nf;
+extern cpuop_func op_e3f9_31_ff;
+extern cpuop_func op_e4d0_31_nf;
+extern cpuop_func op_e4d0_31_ff;
+extern cpuop_func op_e4d8_31_nf;
+extern cpuop_func op_e4d8_31_ff;
+extern cpuop_func op_e4e0_31_nf;
+extern cpuop_func op_e4e0_31_ff;
+extern cpuop_func op_e4e8_31_nf;
+extern cpuop_func op_e4e8_31_ff;
+extern cpuop_func op_e4f0_31_nf;
+extern cpuop_func op_e4f0_31_ff;
+extern cpuop_func op_e4f8_31_nf;
+extern cpuop_func op_e4f8_31_ff;
+extern cpuop_func op_e4f9_31_nf;
+extern cpuop_func op_e4f9_31_ff;
+extern cpuop_func op_e5d0_31_nf;
+extern cpuop_func op_e5d0_31_ff;
+extern cpuop_func op_e5d8_31_nf;
+extern cpuop_func op_e5d8_31_ff;
+extern cpuop_func op_e5e0_31_nf;
+extern cpuop_func op_e5e0_31_ff;
+extern cpuop_func op_e5e8_31_nf;
+extern cpuop_func op_e5e8_31_ff;
+extern cpuop_func op_e5f0_31_nf;
+extern cpuop_func op_e5f0_31_ff;
+extern cpuop_func op_e5f8_31_nf;
+extern cpuop_func op_e5f8_31_ff;
+extern cpuop_func op_e5f9_31_nf;
+extern cpuop_func op_e5f9_31_ff;
+extern cpuop_func op_e6d0_31_nf;
+extern cpuop_func op_e6d0_31_ff;
+extern cpuop_func op_e6d8_31_nf;
+extern cpuop_func op_e6d8_31_ff;
+extern cpuop_func op_e6e0_31_nf;
+extern cpuop_func op_e6e0_31_ff;
+extern cpuop_func op_e6e8_31_nf;
+extern cpuop_func op_e6e8_31_ff;
+extern cpuop_func op_e6f0_31_nf;
+extern cpuop_func op_e6f0_31_ff;
+extern cpuop_func op_e6f8_31_nf;
+extern cpuop_func op_e6f8_31_ff;
+extern cpuop_func op_e6f9_31_nf;
+extern cpuop_func op_e6f9_31_ff;
+extern cpuop_func op_e7d0_31_nf;
+extern cpuop_func op_e7d0_31_ff;
+extern cpuop_func op_e7d8_31_nf;
+extern cpuop_func op_e7d8_31_ff;
+extern cpuop_func op_e7e0_31_nf;
+extern cpuop_func op_e7e0_31_ff;
+extern cpuop_func op_e7e8_31_nf;
+extern cpuop_func op_e7e8_31_ff;
+extern cpuop_func op_e7f0_31_nf;
+extern cpuop_func op_e7f0_31_ff;
+extern cpuop_func op_e7f8_31_nf;
+extern cpuop_func op_e7f8_31_ff;
+extern cpuop_func op_e7f9_31_nf;
+extern cpuop_func op_e7f9_31_ff;
+extern cpuop_func op_e8c0_31_nf;
+extern cpuop_func op_e8c0_31_ff;
+extern cpuop_func op_e8d0_31_nf;
+extern cpuop_func op_e8d0_31_ff;
+extern cpuop_func op_e8e8_31_nf;
+extern cpuop_func op_e8e8_31_ff;
+extern cpuop_func op_e8f0_31_nf;
+extern cpuop_func op_e8f0_31_ff;
+extern cpuop_func op_e8f8_31_nf;
+extern cpuop_func op_e8f8_31_ff;
+extern cpuop_func op_e8f9_31_nf;
+extern cpuop_func op_e8f9_31_ff;
+extern cpuop_func op_e8fa_31_nf;
+extern cpuop_func op_e8fa_31_ff;
+extern cpuop_func op_e8fb_31_nf;
+extern cpuop_func op_e8fb_31_ff;
+extern cpuop_func op_e9c0_31_nf;
+extern cpuop_func op_e9c0_31_ff;
+extern cpuop_func op_e9d0_31_nf;
+extern cpuop_func op_e9d0_31_ff;
+extern cpuop_func op_e9e8_31_nf;
+extern cpuop_func op_e9e8_31_ff;
+extern cpuop_func op_e9f0_31_nf;
+extern cpuop_func op_e9f0_31_ff;
+extern cpuop_func op_e9f8_31_nf;
+extern cpuop_func op_e9f8_31_ff;
+extern cpuop_func op_e9f9_31_nf;
+extern cpuop_func op_e9f9_31_ff;
+extern cpuop_func op_e9fa_31_nf;
+extern cpuop_func op_e9fa_31_ff;
+extern cpuop_func op_e9fb_31_nf;
+extern cpuop_func op_e9fb_31_ff;
+extern cpuop_func op_eac0_31_nf;
+extern cpuop_func op_eac0_31_ff;
+extern cpuop_func op_ead0_31_nf;
+extern cpuop_func op_ead0_31_ff;
+extern cpuop_func op_eae8_31_nf;
+extern cpuop_func op_eae8_31_ff;
+extern cpuop_func op_eaf0_31_nf;
+extern cpuop_func op_eaf0_31_ff;
+extern cpuop_func op_eaf8_31_nf;
+extern cpuop_func op_eaf8_31_ff;
+extern cpuop_func op_eaf9_31_nf;
+extern cpuop_func op_eaf9_31_ff;
+extern cpuop_func op_ebc0_31_nf;
+extern cpuop_func op_ebc0_31_ff;
+extern cpuop_func op_ebd0_31_nf;
+extern cpuop_func op_ebd0_31_ff;
+extern cpuop_func op_ebe8_31_nf;
+extern cpuop_func op_ebe8_31_ff;
+extern cpuop_func op_ebf0_31_nf;
+extern cpuop_func op_ebf0_31_ff;
+extern cpuop_func op_ebf8_31_nf;
+extern cpuop_func op_ebf8_31_ff;
+extern cpuop_func op_ebf9_31_nf;
+extern cpuop_func op_ebf9_31_ff;
+extern cpuop_func op_ebfa_31_nf;
+extern cpuop_func op_ebfa_31_ff;
+extern cpuop_func op_ebfb_31_nf;
+extern cpuop_func op_ebfb_31_ff;
+extern cpuop_func op_ecc0_31_nf;
+extern cpuop_func op_ecc0_31_ff;
+extern cpuop_func op_ecd0_31_nf;
+extern cpuop_func op_ecd0_31_ff;
+extern cpuop_func op_ece8_31_nf;
+extern cpuop_func op_ece8_31_ff;
+extern cpuop_func op_ecf0_31_nf;
+extern cpuop_func op_ecf0_31_ff;
+extern cpuop_func op_ecf8_31_nf;
+extern cpuop_func op_ecf8_31_ff;
+extern cpuop_func op_ecf9_31_nf;
+extern cpuop_func op_ecf9_31_ff;
+extern cpuop_func op_edc0_31_nf;
+extern cpuop_func op_edc0_31_ff;
+extern cpuop_func op_edd0_31_nf;
+extern cpuop_func op_edd0_31_ff;
+extern cpuop_func op_ede8_31_nf;
+extern cpuop_func op_ede8_31_ff;
+extern cpuop_func op_edf0_31_nf;
+extern cpuop_func op_edf0_31_ff;
+extern cpuop_func op_edf8_31_nf;
+extern cpuop_func op_edf8_31_ff;
+extern cpuop_func op_edf9_31_nf;
+extern cpuop_func op_edf9_31_ff;
+extern cpuop_func op_edfa_31_nf;
+extern cpuop_func op_edfa_31_ff;
+extern cpuop_func op_edfb_31_nf;
+extern cpuop_func op_edfb_31_ff;
+extern cpuop_func op_eec0_31_nf;
+extern cpuop_func op_eec0_31_ff;
+extern cpuop_func op_eed0_31_nf;
+extern cpuop_func op_eed0_31_ff;
+extern cpuop_func op_eee8_31_nf;
+extern cpuop_func op_eee8_31_ff;
+extern cpuop_func op_eef0_31_nf;
+extern cpuop_func op_eef0_31_ff;
+extern cpuop_func op_eef8_31_nf;
+extern cpuop_func op_eef8_31_ff;
+extern cpuop_func op_eef9_31_nf;
+extern cpuop_func op_eef9_31_ff;
+extern cpuop_func op_efc0_31_nf;
+extern cpuop_func op_efc0_31_ff;
+extern cpuop_func op_efd0_31_nf;
+extern cpuop_func op_efd0_31_ff;
+extern cpuop_func op_efe8_31_nf;
+extern cpuop_func op_efe8_31_ff;
+extern cpuop_func op_eff0_31_nf;
+extern cpuop_func op_eff0_31_ff;
+extern cpuop_func op_eff8_31_nf;
+extern cpuop_func op_eff8_31_ff;
+extern cpuop_func op_eff9_31_nf;
+extern cpuop_func op_eff9_31_ff;
+extern cpuop_func op_f000_31_nf;
+extern cpuop_func op_f000_31_ff;
+extern cpuop_func op_f008_31_nf;
+extern cpuop_func op_f008_31_ff;
+extern cpuop_func op_f010_31_nf;
+extern cpuop_func op_f010_31_ff;
+extern cpuop_func op_f018_31_nf;
+extern cpuop_func op_f018_31_ff;
+extern cpuop_func op_f020_31_nf;
+extern cpuop_func op_f020_31_ff;
+extern cpuop_func op_f028_31_nf;
+extern cpuop_func op_f028_31_ff;
+extern cpuop_func op_f030_31_nf;
+extern cpuop_func op_f030_31_ff;
+extern cpuop_func op_f038_31_nf;
+extern cpuop_func op_f038_31_ff;
+extern cpuop_func op_f039_31_nf;
+extern cpuop_func op_f039_31_ff;
+extern cpuop_func op_f200_31_nf;
+extern cpuop_func op_f200_31_ff;
+extern cpuop_func op_f208_31_nf;
+extern cpuop_func op_f208_31_ff;
+extern cpuop_func op_f210_31_nf;
+extern cpuop_func op_f210_31_ff;
+extern cpuop_func op_f218_31_nf;
+extern cpuop_func op_f218_31_ff;
+extern cpuop_func op_f220_31_nf;
+extern cpuop_func op_f220_31_ff;
+extern cpuop_func op_f228_31_nf;
+extern cpuop_func op_f228_31_ff;
+extern cpuop_func op_f230_31_nf;
+extern cpuop_func op_f230_31_ff;
+extern cpuop_func op_f238_31_nf;
+extern cpuop_func op_f238_31_ff;
+extern cpuop_func op_f239_31_nf;
+extern cpuop_func op_f239_31_ff;
+extern cpuop_func op_f23a_31_nf;
+extern cpuop_func op_f23a_31_ff;
+extern cpuop_func op_f23b_31_nf;
+extern cpuop_func op_f23b_31_ff;
+extern cpuop_func op_f23c_31_nf;
+extern cpuop_func op_f23c_31_ff;
+extern cpuop_func op_f240_31_nf;
+extern cpuop_func op_f240_31_ff;
+extern cpuop_func op_f248_31_nf;
+extern cpuop_func op_f248_31_ff;
+extern cpuop_func op_f250_31_nf;
+extern cpuop_func op_f250_31_ff;
+extern cpuop_func op_f258_31_nf;
+extern cpuop_func op_f258_31_ff;
+extern cpuop_func op_f260_31_nf;
+extern cpuop_func op_f260_31_ff;
+extern cpuop_func op_f268_31_nf;
+extern cpuop_func op_f268_31_ff;
+extern cpuop_func op_f270_31_nf;
+extern cpuop_func op_f270_31_ff;
+extern cpuop_func op_f278_31_nf;
+extern cpuop_func op_f278_31_ff;
+extern cpuop_func op_f279_31_nf;
+extern cpuop_func op_f279_31_ff;
+extern cpuop_func op_f27a_31_nf;
+extern cpuop_func op_f27a_31_ff;
+extern cpuop_func op_f27b_31_nf;
+extern cpuop_func op_f27b_31_ff;
+extern cpuop_func op_f27c_31_nf;
+extern cpuop_func op_f27c_31_ff;
+extern cpuop_func op_f280_31_nf;
+extern cpuop_func op_f280_31_ff;
+extern cpuop_func op_f2c0_31_nf;
+extern cpuop_func op_f2c0_31_ff;
+extern cpuop_func op_f310_31_nf;
+extern cpuop_func op_f310_31_ff;
+extern cpuop_func op_f320_31_nf;
+extern cpuop_func op_f320_31_ff;
+extern cpuop_func op_f328_31_nf;
+extern cpuop_func op_f328_31_ff;
+extern cpuop_func op_f330_31_nf;
+extern cpuop_func op_f330_31_ff;
+extern cpuop_func op_f338_31_nf;
+extern cpuop_func op_f338_31_ff;
+extern cpuop_func op_f339_31_nf;
+extern cpuop_func op_f339_31_ff;
+extern cpuop_func op_f350_31_nf;
+extern cpuop_func op_f350_31_ff;
+extern cpuop_func op_f358_31_nf;
+extern cpuop_func op_f358_31_ff;
+extern cpuop_func op_f368_31_nf;
+extern cpuop_func op_f368_31_ff;
+extern cpuop_func op_f370_31_nf;
+extern cpuop_func op_f370_31_ff;
+extern cpuop_func op_f378_31_nf;
+extern cpuop_func op_f378_31_ff;
+extern cpuop_func op_f379_31_nf;
+extern cpuop_func op_f379_31_ff;
+extern cpuop_func op_f37a_31_nf;
+extern cpuop_func op_f37a_31_ff;
+extern cpuop_func op_f37b_31_nf;
+extern cpuop_func op_f37b_31_ff;
+extern cpuop_func op_f408_31_nf;
+extern cpuop_func op_f408_31_ff;
+extern cpuop_func op_f410_31_nf;
+extern cpuop_func op_f410_31_ff;
+extern cpuop_func op_f418_31_nf;
+extern cpuop_func op_f418_31_ff;
+extern cpuop_func op_f419_31_nf;
+extern cpuop_func op_f419_31_ff;
+extern cpuop_func op_f41a_31_nf;
+extern cpuop_func op_f41a_31_ff;
+extern cpuop_func op_f41b_31_nf;
+extern cpuop_func op_f41b_31_ff;
+extern cpuop_func op_f41c_31_nf;
+extern cpuop_func op_f41c_31_ff;
+extern cpuop_func op_f41d_31_nf;
+extern cpuop_func op_f41d_31_ff;
+extern cpuop_func op_f41e_31_nf;
+extern cpuop_func op_f41e_31_ff;
+extern cpuop_func op_f41f_31_nf;
+extern cpuop_func op_f41f_31_ff;
+extern cpuop_func op_f428_31_nf;
+extern cpuop_func op_f428_31_ff;
+extern cpuop_func op_f430_31_nf;
+extern cpuop_func op_f430_31_ff;
+extern cpuop_func op_f438_31_nf;
+extern cpuop_func op_f438_31_ff;
+extern cpuop_func op_f439_31_nf;
+extern cpuop_func op_f439_31_ff;
+extern cpuop_func op_f43a_31_nf;
+extern cpuop_func op_f43a_31_ff;
+extern cpuop_func op_f43b_31_nf;
+extern cpuop_func op_f43b_31_ff;
+extern cpuop_func op_f43c_31_nf;
+extern cpuop_func op_f43c_31_ff;
+extern cpuop_func op_f43d_31_nf;
+extern cpuop_func op_f43d_31_ff;
+extern cpuop_func op_f43e_31_nf;
+extern cpuop_func op_f43e_31_ff;
+extern cpuop_func op_f43f_31_nf;
+extern cpuop_func op_f43f_31_ff;
+extern cpuop_func op_f500_31_nf;
+extern cpuop_func op_f500_31_ff;
+extern cpuop_func op_f508_31_nf;
+extern cpuop_func op_f508_31_ff;
+extern cpuop_func op_f510_31_nf;
+extern cpuop_func op_f510_31_ff;
+extern cpuop_func op_f518_31_nf;
+extern cpuop_func op_f518_31_ff;
+extern cpuop_func op_f548_31_nf;
+extern cpuop_func op_f548_31_ff;
+extern cpuop_func op_f568_31_nf;
+extern cpuop_func op_f568_31_ff;
+extern cpuop_func op_f600_31_nf;
+extern cpuop_func op_f600_31_ff;
+extern cpuop_func op_f608_31_nf;
+extern cpuop_func op_f608_31_ff;
+extern cpuop_func op_f610_31_nf;
+extern cpuop_func op_f610_31_ff;
+extern cpuop_func op_f618_31_nf;
+extern cpuop_func op_f618_31_ff;
+extern cpuop_func op_f620_31_nf;
+extern cpuop_func op_f620_31_ff;
+extern cpuop_func op_0000_32_nf;
+extern cpuop_func op_0000_32_ff;
+extern cpuop_func op_0010_32_nf;
+extern cpuop_func op_0010_32_ff;
+extern cpuop_func op_0018_32_nf;
+extern cpuop_func op_0018_32_ff;
+extern cpuop_func op_0020_32_nf;
+extern cpuop_func op_0020_32_ff;
+extern cpuop_func op_0028_32_nf;
+extern cpuop_func op_0028_32_ff;
+extern cpuop_func op_0030_32_nf;
+extern cpuop_func op_0030_32_ff;
+extern cpuop_func op_0038_32_nf;
+extern cpuop_func op_0038_32_ff;
+extern cpuop_func op_0039_32_nf;
+extern cpuop_func op_0039_32_ff;
+extern cpuop_func op_003c_32_nf;
+extern cpuop_func op_003c_32_ff;
+extern cpuop_func op_0040_32_nf;
+extern cpuop_func op_0040_32_ff;
+extern cpuop_func op_0050_32_nf;
+extern cpuop_func op_0050_32_ff;
+extern cpuop_func op_0058_32_nf;
+extern cpuop_func op_0058_32_ff;
+extern cpuop_func op_0060_32_nf;
+extern cpuop_func op_0060_32_ff;
+extern cpuop_func op_0068_32_nf;
+extern cpuop_func op_0068_32_ff;
+extern cpuop_func op_0070_32_nf;
+extern cpuop_func op_0070_32_ff;
+extern cpuop_func op_0078_32_nf;
+extern cpuop_func op_0078_32_ff;
+extern cpuop_func op_0079_32_nf;
+extern cpuop_func op_0079_32_ff;
+extern cpuop_func op_007c_32_nf;
+extern cpuop_func op_007c_32_ff;
+extern cpuop_func op_0080_32_nf;
+extern cpuop_func op_0080_32_ff;
+extern cpuop_func op_0090_32_nf;
+extern cpuop_func op_0090_32_ff;
+extern cpuop_func op_0098_32_nf;
+extern cpuop_func op_0098_32_ff;
+extern cpuop_func op_00a0_32_nf;
+extern cpuop_func op_00a0_32_ff;
+extern cpuop_func op_00a8_32_nf;
+extern cpuop_func op_00a8_32_ff;
+extern cpuop_func op_00b0_32_nf;
+extern cpuop_func op_00b0_32_ff;
+extern cpuop_func op_00b8_32_nf;
+extern cpuop_func op_00b8_32_ff;
+extern cpuop_func op_00b9_32_nf;
+extern cpuop_func op_00b9_32_ff;
+extern cpuop_func op_00d0_32_nf;
+extern cpuop_func op_00d0_32_ff;
+extern cpuop_func op_00e8_32_nf;
+extern cpuop_func op_00e8_32_ff;
+extern cpuop_func op_00f0_32_nf;
+extern cpuop_func op_00f0_32_ff;
+extern cpuop_func op_00f8_32_nf;
+extern cpuop_func op_00f8_32_ff;
+extern cpuop_func op_00f9_32_nf;
+extern cpuop_func op_00f9_32_ff;
+extern cpuop_func op_00fa_32_nf;
+extern cpuop_func op_00fa_32_ff;
+extern cpuop_func op_00fb_32_nf;
+extern cpuop_func op_00fb_32_ff;
+extern cpuop_func op_0100_32_nf;
+extern cpuop_func op_0100_32_ff;
+extern cpuop_func op_0108_32_nf;
+extern cpuop_func op_0108_32_ff;
+extern cpuop_func op_0110_32_nf;
+extern cpuop_func op_0110_32_ff;
+extern cpuop_func op_0118_32_nf;
+extern cpuop_func op_0118_32_ff;
+extern cpuop_func op_0120_32_nf;
+extern cpuop_func op_0120_32_ff;
+extern cpuop_func op_0128_32_nf;
+extern cpuop_func op_0128_32_ff;
+extern cpuop_func op_0130_32_nf;
+extern cpuop_func op_0130_32_ff;
+extern cpuop_func op_0138_32_nf;
+extern cpuop_func op_0138_32_ff;
+extern cpuop_func op_0139_32_nf;
+extern cpuop_func op_0139_32_ff;
+extern cpuop_func op_013a_32_nf;
+extern cpuop_func op_013a_32_ff;
+extern cpuop_func op_013b_32_nf;
+extern cpuop_func op_013b_32_ff;
+extern cpuop_func op_013c_32_nf;
+extern cpuop_func op_013c_32_ff;
+extern cpuop_func op_0140_32_nf;
+extern cpuop_func op_0140_32_ff;
+extern cpuop_func op_0148_32_nf;
+extern cpuop_func op_0148_32_ff;
+extern cpuop_func op_0150_32_nf;
+extern cpuop_func op_0150_32_ff;
+extern cpuop_func op_0158_32_nf;
+extern cpuop_func op_0158_32_ff;
+extern cpuop_func op_0160_32_nf;
+extern cpuop_func op_0160_32_ff;
+extern cpuop_func op_0168_32_nf;
+extern cpuop_func op_0168_32_ff;
+extern cpuop_func op_0170_32_nf;
+extern cpuop_func op_0170_32_ff;
+extern cpuop_func op_0178_32_nf;
+extern cpuop_func op_0178_32_ff;
+extern cpuop_func op_0179_32_nf;
+extern cpuop_func op_0179_32_ff;
+extern cpuop_func op_0180_32_nf;
+extern cpuop_func op_0180_32_ff;
+extern cpuop_func op_0188_32_nf;
+extern cpuop_func op_0188_32_ff;
+extern cpuop_func op_0190_32_nf;
+extern cpuop_func op_0190_32_ff;
+extern cpuop_func op_0198_32_nf;
+extern cpuop_func op_0198_32_ff;
+extern cpuop_func op_01a0_32_nf;
+extern cpuop_func op_01a0_32_ff;
+extern cpuop_func op_01a8_32_nf;
+extern cpuop_func op_01a8_32_ff;
+extern cpuop_func op_01b0_32_nf;
+extern cpuop_func op_01b0_32_ff;
+extern cpuop_func op_01b8_32_nf;
+extern cpuop_func op_01b8_32_ff;
+extern cpuop_func op_01b9_32_nf;
+extern cpuop_func op_01b9_32_ff;
+extern cpuop_func op_01c0_32_nf;
+extern cpuop_func op_01c0_32_ff;
+extern cpuop_func op_01c8_32_nf;
+extern cpuop_func op_01c8_32_ff;
+extern cpuop_func op_01d0_32_nf;
+extern cpuop_func op_01d0_32_ff;
+extern cpuop_func op_01d8_32_nf;
+extern cpuop_func op_01d8_32_ff;
+extern cpuop_func op_01e0_32_nf;
+extern cpuop_func op_01e0_32_ff;
+extern cpuop_func op_01e8_32_nf;
+extern cpuop_func op_01e8_32_ff;
+extern cpuop_func op_01f0_32_nf;
+extern cpuop_func op_01f0_32_ff;
+extern cpuop_func op_01f8_32_nf;
+extern cpuop_func op_01f8_32_ff;
+extern cpuop_func op_01f9_32_nf;
+extern cpuop_func op_01f9_32_ff;
+extern cpuop_func op_0200_32_nf;
+extern cpuop_func op_0200_32_ff;
+extern cpuop_func op_0210_32_nf;
+extern cpuop_func op_0210_32_ff;
+extern cpuop_func op_0218_32_nf;
+extern cpuop_func op_0218_32_ff;
+extern cpuop_func op_0220_32_nf;
+extern cpuop_func op_0220_32_ff;
+extern cpuop_func op_0228_32_nf;
+extern cpuop_func op_0228_32_ff;
+extern cpuop_func op_0230_32_nf;
+extern cpuop_func op_0230_32_ff;
+extern cpuop_func op_0238_32_nf;
+extern cpuop_func op_0238_32_ff;
+extern cpuop_func op_0239_32_nf;
+extern cpuop_func op_0239_32_ff;
+extern cpuop_func op_023c_32_nf;
+extern cpuop_func op_023c_32_ff;
+extern cpuop_func op_0240_32_nf;
+extern cpuop_func op_0240_32_ff;
+extern cpuop_func op_0250_32_nf;
+extern cpuop_func op_0250_32_ff;
+extern cpuop_func op_0258_32_nf;
+extern cpuop_func op_0258_32_ff;
+extern cpuop_func op_0260_32_nf;
+extern cpuop_func op_0260_32_ff;
+extern cpuop_func op_0268_32_nf;
+extern cpuop_func op_0268_32_ff;
+extern cpuop_func op_0270_32_nf;
+extern cpuop_func op_0270_32_ff;
+extern cpuop_func op_0278_32_nf;
+extern cpuop_func op_0278_32_ff;
+extern cpuop_func op_0279_32_nf;
+extern cpuop_func op_0279_32_ff;
+extern cpuop_func op_027c_32_nf;
+extern cpuop_func op_027c_32_ff;
+extern cpuop_func op_0280_32_nf;
+extern cpuop_func op_0280_32_ff;
+extern cpuop_func op_0290_32_nf;
+extern cpuop_func op_0290_32_ff;
+extern cpuop_func op_0298_32_nf;
+extern cpuop_func op_0298_32_ff;
+extern cpuop_func op_02a0_32_nf;
+extern cpuop_func op_02a0_32_ff;
+extern cpuop_func op_02a8_32_nf;
+extern cpuop_func op_02a8_32_ff;
+extern cpuop_func op_02b0_32_nf;
+extern cpuop_func op_02b0_32_ff;
+extern cpuop_func op_02b8_32_nf;
+extern cpuop_func op_02b8_32_ff;
+extern cpuop_func op_02b9_32_nf;
+extern cpuop_func op_02b9_32_ff;
+extern cpuop_func op_02d0_32_nf;
+extern cpuop_func op_02d0_32_ff;
+extern cpuop_func op_02e8_32_nf;
+extern cpuop_func op_02e8_32_ff;
+extern cpuop_func op_02f0_32_nf;
+extern cpuop_func op_02f0_32_ff;
+extern cpuop_func op_02f8_32_nf;
+extern cpuop_func op_02f8_32_ff;
+extern cpuop_func op_02f9_32_nf;
+extern cpuop_func op_02f9_32_ff;
+extern cpuop_func op_02fa_32_nf;
+extern cpuop_func op_02fa_32_ff;
+extern cpuop_func op_02fb_32_nf;
+extern cpuop_func op_02fb_32_ff;
+extern cpuop_func op_0400_32_nf;
+extern cpuop_func op_0400_32_ff;
+extern cpuop_func op_0410_32_nf;
+extern cpuop_func op_0410_32_ff;
+extern cpuop_func op_0418_32_nf;
+extern cpuop_func op_0418_32_ff;
+extern cpuop_func op_0420_32_nf;
+extern cpuop_func op_0420_32_ff;
+extern cpuop_func op_0428_32_nf;
+extern cpuop_func op_0428_32_ff;
+extern cpuop_func op_0430_32_nf;
+extern cpuop_func op_0430_32_ff;
+extern cpuop_func op_0438_32_nf;
+extern cpuop_func op_0438_32_ff;
+extern cpuop_func op_0439_32_nf;
+extern cpuop_func op_0439_32_ff;
+extern cpuop_func op_0440_32_nf;
+extern cpuop_func op_0440_32_ff;
+extern cpuop_func op_0450_32_nf;
+extern cpuop_func op_0450_32_ff;
+extern cpuop_func op_0458_32_nf;
+extern cpuop_func op_0458_32_ff;
+extern cpuop_func op_0460_32_nf;
+extern cpuop_func op_0460_32_ff;
+extern cpuop_func op_0468_32_nf;
+extern cpuop_func op_0468_32_ff;
+extern cpuop_func op_0470_32_nf;
+extern cpuop_func op_0470_32_ff;
+extern cpuop_func op_0478_32_nf;
+extern cpuop_func op_0478_32_ff;
+extern cpuop_func op_0479_32_nf;
+extern cpuop_func op_0479_32_ff;
+extern cpuop_func op_0480_32_nf;
+extern cpuop_func op_0480_32_ff;
+extern cpuop_func op_0490_32_nf;
+extern cpuop_func op_0490_32_ff;
+extern cpuop_func op_0498_32_nf;
+extern cpuop_func op_0498_32_ff;
+extern cpuop_func op_04a0_32_nf;
+extern cpuop_func op_04a0_32_ff;
+extern cpuop_func op_04a8_32_nf;
+extern cpuop_func op_04a8_32_ff;
+extern cpuop_func op_04b0_32_nf;
+extern cpuop_func op_04b0_32_ff;
+extern cpuop_func op_04b8_32_nf;
+extern cpuop_func op_04b8_32_ff;
+extern cpuop_func op_04b9_32_nf;
+extern cpuop_func op_04b9_32_ff;
+extern cpuop_func op_04d0_32_nf;
+extern cpuop_func op_04d0_32_ff;
+extern cpuop_func op_04e8_32_nf;
+extern cpuop_func op_04e8_32_ff;
+extern cpuop_func op_04f0_32_nf;
+extern cpuop_func op_04f0_32_ff;
+extern cpuop_func op_04f8_32_nf;
+extern cpuop_func op_04f8_32_ff;
+extern cpuop_func op_04f9_32_nf;
+extern cpuop_func op_04f9_32_ff;
+extern cpuop_func op_04fa_32_nf;
+extern cpuop_func op_04fa_32_ff;
+extern cpuop_func op_04fb_32_nf;
+extern cpuop_func op_04fb_32_ff;
+extern cpuop_func op_0600_32_nf;
+extern cpuop_func op_0600_32_ff;
+extern cpuop_func op_0610_32_nf;
+extern cpuop_func op_0610_32_ff;
+extern cpuop_func op_0618_32_nf;
+extern cpuop_func op_0618_32_ff;
+extern cpuop_func op_0620_32_nf;
+extern cpuop_func op_0620_32_ff;
+extern cpuop_func op_0628_32_nf;
+extern cpuop_func op_0628_32_ff;
+extern cpuop_func op_0630_32_nf;
+extern cpuop_func op_0630_32_ff;
+extern cpuop_func op_0638_32_nf;
+extern cpuop_func op_0638_32_ff;
+extern cpuop_func op_0639_32_nf;
+extern cpuop_func op_0639_32_ff;
+extern cpuop_func op_0640_32_nf;
+extern cpuop_func op_0640_32_ff;
+extern cpuop_func op_0650_32_nf;
+extern cpuop_func op_0650_32_ff;
+extern cpuop_func op_0658_32_nf;
+extern cpuop_func op_0658_32_ff;
+extern cpuop_func op_0660_32_nf;
+extern cpuop_func op_0660_32_ff;
+extern cpuop_func op_0668_32_nf;
+extern cpuop_func op_0668_32_ff;
+extern cpuop_func op_0670_32_nf;
+extern cpuop_func op_0670_32_ff;
+extern cpuop_func op_0678_32_nf;
+extern cpuop_func op_0678_32_ff;
+extern cpuop_func op_0679_32_nf;
+extern cpuop_func op_0679_32_ff;
+extern cpuop_func op_0680_32_nf;
+extern cpuop_func op_0680_32_ff;
+extern cpuop_func op_0690_32_nf;
+extern cpuop_func op_0690_32_ff;
+extern cpuop_func op_0698_32_nf;
+extern cpuop_func op_0698_32_ff;
+extern cpuop_func op_06a0_32_nf;
+extern cpuop_func op_06a0_32_ff;
+extern cpuop_func op_06a8_32_nf;
+extern cpuop_func op_06a8_32_ff;
+extern cpuop_func op_06b0_32_nf;
+extern cpuop_func op_06b0_32_ff;
+extern cpuop_func op_06b8_32_nf;
+extern cpuop_func op_06b8_32_ff;
+extern cpuop_func op_06b9_32_nf;
+extern cpuop_func op_06b9_32_ff;
+extern cpuop_func op_06c0_32_nf;
+extern cpuop_func op_06c0_32_ff;
+extern cpuop_func op_06c8_32_nf;
+extern cpuop_func op_06c8_32_ff;
+extern cpuop_func op_06d0_32_nf;
+extern cpuop_func op_06d0_32_ff;
+extern cpuop_func op_06e8_32_nf;
+extern cpuop_func op_06e8_32_ff;
+extern cpuop_func op_06f0_32_nf;
+extern cpuop_func op_06f0_32_ff;
+extern cpuop_func op_06f8_32_nf;
+extern cpuop_func op_06f8_32_ff;
+extern cpuop_func op_06f9_32_nf;
+extern cpuop_func op_06f9_32_ff;
+extern cpuop_func op_06fa_32_nf;
+extern cpuop_func op_06fa_32_ff;
+extern cpuop_func op_06fb_32_nf;
+extern cpuop_func op_06fb_32_ff;
+extern cpuop_func op_0800_32_nf;
+extern cpuop_func op_0800_32_ff;
+extern cpuop_func op_0810_32_nf;
+extern cpuop_func op_0810_32_ff;
+extern cpuop_func op_0818_32_nf;
+extern cpuop_func op_0818_32_ff;
+extern cpuop_func op_0820_32_nf;
+extern cpuop_func op_0820_32_ff;
+extern cpuop_func op_0828_32_nf;
+extern cpuop_func op_0828_32_ff;
+extern cpuop_func op_0830_32_nf;
+extern cpuop_func op_0830_32_ff;
+extern cpuop_func op_0838_32_nf;
+extern cpuop_func op_0838_32_ff;
+extern cpuop_func op_0839_32_nf;
+extern cpuop_func op_0839_32_ff;
+extern cpuop_func op_083a_32_nf;
+extern cpuop_func op_083a_32_ff;
+extern cpuop_func op_083b_32_nf;
+extern cpuop_func op_083b_32_ff;
+extern cpuop_func op_0840_32_nf;
+extern cpuop_func op_0840_32_ff;
+extern cpuop_func op_0850_32_nf;
+extern cpuop_func op_0850_32_ff;
+extern cpuop_func op_0858_32_nf;
+extern cpuop_func op_0858_32_ff;
+extern cpuop_func op_0860_32_nf;
+extern cpuop_func op_0860_32_ff;
+extern cpuop_func op_0868_32_nf;
+extern cpuop_func op_0868_32_ff;
+extern cpuop_func op_0870_32_nf;
+extern cpuop_func op_0870_32_ff;
+extern cpuop_func op_0878_32_nf;
+extern cpuop_func op_0878_32_ff;
+extern cpuop_func op_0879_32_nf;
+extern cpuop_func op_0879_32_ff;
+extern cpuop_func op_0880_32_nf;
+extern cpuop_func op_0880_32_ff;
+extern cpuop_func op_0890_32_nf;
+extern cpuop_func op_0890_32_ff;
+extern cpuop_func op_0898_32_nf;
+extern cpuop_func op_0898_32_ff;
+extern cpuop_func op_08a0_32_nf;
+extern cpuop_func op_08a0_32_ff;
+extern cpuop_func op_08a8_32_nf;
+extern cpuop_func op_08a8_32_ff;
+extern cpuop_func op_08b0_32_nf;
+extern cpuop_func op_08b0_32_ff;
+extern cpuop_func op_08b8_32_nf;
+extern cpuop_func op_08b8_32_ff;
+extern cpuop_func op_08b9_32_nf;
+extern cpuop_func op_08b9_32_ff;
+extern cpuop_func op_08c0_32_nf;
+extern cpuop_func op_08c0_32_ff;
+extern cpuop_func op_08d0_32_nf;
+extern cpuop_func op_08d0_32_ff;
+extern cpuop_func op_08d8_32_nf;
+extern cpuop_func op_08d8_32_ff;
+extern cpuop_func op_08e0_32_nf;
+extern cpuop_func op_08e0_32_ff;
+extern cpuop_func op_08e8_32_nf;
+extern cpuop_func op_08e8_32_ff;
+extern cpuop_func op_08f0_32_nf;
+extern cpuop_func op_08f0_32_ff;
+extern cpuop_func op_08f8_32_nf;
+extern cpuop_func op_08f8_32_ff;
+extern cpuop_func op_08f9_32_nf;
+extern cpuop_func op_08f9_32_ff;
+extern cpuop_func op_0a00_32_nf;
+extern cpuop_func op_0a00_32_ff;
+extern cpuop_func op_0a10_32_nf;
+extern cpuop_func op_0a10_32_ff;
+extern cpuop_func op_0a18_32_nf;
+extern cpuop_func op_0a18_32_ff;
+extern cpuop_func op_0a20_32_nf;
+extern cpuop_func op_0a20_32_ff;
+extern cpuop_func op_0a28_32_nf;
+extern cpuop_func op_0a28_32_ff;
+extern cpuop_func op_0a30_32_nf;
+extern cpuop_func op_0a30_32_ff;
+extern cpuop_func op_0a38_32_nf;
+extern cpuop_func op_0a38_32_ff;
+extern cpuop_func op_0a39_32_nf;
+extern cpuop_func op_0a39_32_ff;
+extern cpuop_func op_0a3c_32_nf;
+extern cpuop_func op_0a3c_32_ff;
+extern cpuop_func op_0a40_32_nf;
+extern cpuop_func op_0a40_32_ff;
+extern cpuop_func op_0a50_32_nf;
+extern cpuop_func op_0a50_32_ff;
+extern cpuop_func op_0a58_32_nf;
+extern cpuop_func op_0a58_32_ff;
+extern cpuop_func op_0a60_32_nf;
+extern cpuop_func op_0a60_32_ff;
+extern cpuop_func op_0a68_32_nf;
+extern cpuop_func op_0a68_32_ff;
+extern cpuop_func op_0a70_32_nf;
+extern cpuop_func op_0a70_32_ff;
+extern cpuop_func op_0a78_32_nf;
+extern cpuop_func op_0a78_32_ff;
+extern cpuop_func op_0a79_32_nf;
+extern cpuop_func op_0a79_32_ff;
+extern cpuop_func op_0a7c_32_nf;
+extern cpuop_func op_0a7c_32_ff;
+extern cpuop_func op_0a80_32_nf;
+extern cpuop_func op_0a80_32_ff;
+extern cpuop_func op_0a90_32_nf;
+extern cpuop_func op_0a90_32_ff;
+extern cpuop_func op_0a98_32_nf;
+extern cpuop_func op_0a98_32_ff;
+extern cpuop_func op_0aa0_32_nf;
+extern cpuop_func op_0aa0_32_ff;
+extern cpuop_func op_0aa8_32_nf;
+extern cpuop_func op_0aa8_32_ff;
+extern cpuop_func op_0ab0_32_nf;
+extern cpuop_func op_0ab0_32_ff;
+extern cpuop_func op_0ab8_32_nf;
+extern cpuop_func op_0ab8_32_ff;
+extern cpuop_func op_0ab9_32_nf;
+extern cpuop_func op_0ab9_32_ff;
+extern cpuop_func op_0ad0_32_nf;
+extern cpuop_func op_0ad0_32_ff;
+extern cpuop_func op_0ad8_32_nf;
+extern cpuop_func op_0ad8_32_ff;
+extern cpuop_func op_0ae0_32_nf;
+extern cpuop_func op_0ae0_32_ff;
+extern cpuop_func op_0ae8_32_nf;
+extern cpuop_func op_0ae8_32_ff;
+extern cpuop_func op_0af0_32_nf;
+extern cpuop_func op_0af0_32_ff;
+extern cpuop_func op_0af8_32_nf;
+extern cpuop_func op_0af8_32_ff;
+extern cpuop_func op_0af9_32_nf;
+extern cpuop_func op_0af9_32_ff;
+extern cpuop_func op_0c00_32_nf;
+extern cpuop_func op_0c00_32_ff;
+extern cpuop_func op_0c10_32_nf;
+extern cpuop_func op_0c10_32_ff;
+extern cpuop_func op_0c18_32_nf;
+extern cpuop_func op_0c18_32_ff;
+extern cpuop_func op_0c20_32_nf;
+extern cpuop_func op_0c20_32_ff;
+extern cpuop_func op_0c28_32_nf;
+extern cpuop_func op_0c28_32_ff;
+extern cpuop_func op_0c30_32_nf;
+extern cpuop_func op_0c30_32_ff;
+extern cpuop_func op_0c38_32_nf;
+extern cpuop_func op_0c38_32_ff;
+extern cpuop_func op_0c39_32_nf;
+extern cpuop_func op_0c39_32_ff;
+extern cpuop_func op_0c3a_32_nf;
+extern cpuop_func op_0c3a_32_ff;
+extern cpuop_func op_0c3b_32_nf;
+extern cpuop_func op_0c3b_32_ff;
+extern cpuop_func op_0c40_32_nf;
+extern cpuop_func op_0c40_32_ff;
+extern cpuop_func op_0c50_32_nf;
+extern cpuop_func op_0c50_32_ff;
+extern cpuop_func op_0c58_32_nf;
+extern cpuop_func op_0c58_32_ff;
+extern cpuop_func op_0c60_32_nf;
+extern cpuop_func op_0c60_32_ff;
+extern cpuop_func op_0c68_32_nf;
+extern cpuop_func op_0c68_32_ff;
+extern cpuop_func op_0c70_32_nf;
+extern cpuop_func op_0c70_32_ff;
+extern cpuop_func op_0c78_32_nf;
+extern cpuop_func op_0c78_32_ff;
+extern cpuop_func op_0c79_32_nf;
+extern cpuop_func op_0c79_32_ff;
+extern cpuop_func op_0c7a_32_nf;
+extern cpuop_func op_0c7a_32_ff;
+extern cpuop_func op_0c7b_32_nf;
+extern cpuop_func op_0c7b_32_ff;
+extern cpuop_func op_0c80_32_nf;
+extern cpuop_func op_0c80_32_ff;
+extern cpuop_func op_0c90_32_nf;
+extern cpuop_func op_0c90_32_ff;
+extern cpuop_func op_0c98_32_nf;
+extern cpuop_func op_0c98_32_ff;
+extern cpuop_func op_0ca0_32_nf;
+extern cpuop_func op_0ca0_32_ff;
+extern cpuop_func op_0ca8_32_nf;
+extern cpuop_func op_0ca8_32_ff;
+extern cpuop_func op_0cb0_32_nf;
+extern cpuop_func op_0cb0_32_ff;
+extern cpuop_func op_0cb8_32_nf;
+extern cpuop_func op_0cb8_32_ff;
+extern cpuop_func op_0cb9_32_nf;
+extern cpuop_func op_0cb9_32_ff;
+extern cpuop_func op_0cba_32_nf;
+extern cpuop_func op_0cba_32_ff;
+extern cpuop_func op_0cbb_32_nf;
+extern cpuop_func op_0cbb_32_ff;
+extern cpuop_func op_0cd0_32_nf;
+extern cpuop_func op_0cd0_32_ff;
+extern cpuop_func op_0cd8_32_nf;
+extern cpuop_func op_0cd8_32_ff;
+extern cpuop_func op_0ce0_32_nf;
+extern cpuop_func op_0ce0_32_ff;
+extern cpuop_func op_0ce8_32_nf;
+extern cpuop_func op_0ce8_32_ff;
+extern cpuop_func op_0cf0_32_nf;
+extern cpuop_func op_0cf0_32_ff;
+extern cpuop_func op_0cf8_32_nf;
+extern cpuop_func op_0cf8_32_ff;
+extern cpuop_func op_0cf9_32_nf;
+extern cpuop_func op_0cf9_32_ff;
+extern cpuop_func op_0cfc_32_nf;
+extern cpuop_func op_0cfc_32_ff;
+extern cpuop_func op_0e10_32_nf;
+extern cpuop_func op_0e10_32_ff;
+extern cpuop_func op_0e18_32_nf;
+extern cpuop_func op_0e18_32_ff;
+extern cpuop_func op_0e20_32_nf;
+extern cpuop_func op_0e20_32_ff;
+extern cpuop_func op_0e28_32_nf;
+extern cpuop_func op_0e28_32_ff;
+extern cpuop_func op_0e30_32_nf;
+extern cpuop_func op_0e30_32_ff;
+extern cpuop_func op_0e38_32_nf;
+extern cpuop_func op_0e38_32_ff;
+extern cpuop_func op_0e39_32_nf;
+extern cpuop_func op_0e39_32_ff;
+extern cpuop_func op_0e50_32_nf;
+extern cpuop_func op_0e50_32_ff;
+extern cpuop_func op_0e58_32_nf;
+extern cpuop_func op_0e58_32_ff;
+extern cpuop_func op_0e60_32_nf;
+extern cpuop_func op_0e60_32_ff;
+extern cpuop_func op_0e68_32_nf;
+extern cpuop_func op_0e68_32_ff;
+extern cpuop_func op_0e70_32_nf;
+extern cpuop_func op_0e70_32_ff;
+extern cpuop_func op_0e78_32_nf;
+extern cpuop_func op_0e78_32_ff;
+extern cpuop_func op_0e79_32_nf;
+extern cpuop_func op_0e79_32_ff;
+extern cpuop_func op_0e90_32_nf;
+extern cpuop_func op_0e90_32_ff;
+extern cpuop_func op_0e98_32_nf;
+extern cpuop_func op_0e98_32_ff;
+extern cpuop_func op_0ea0_32_nf;
+extern cpuop_func op_0ea0_32_ff;
+extern cpuop_func op_0ea8_32_nf;
+extern cpuop_func op_0ea8_32_ff;
+extern cpuop_func op_0eb0_32_nf;
+extern cpuop_func op_0eb0_32_ff;
+extern cpuop_func op_0eb8_32_nf;
+extern cpuop_func op_0eb8_32_ff;
+extern cpuop_func op_0eb9_32_nf;
+extern cpuop_func op_0eb9_32_ff;
+extern cpuop_func op_0ed0_32_nf;
+extern cpuop_func op_0ed0_32_ff;
+extern cpuop_func op_0ed8_32_nf;
+extern cpuop_func op_0ed8_32_ff;
+extern cpuop_func op_0ee0_32_nf;
+extern cpuop_func op_0ee0_32_ff;
+extern cpuop_func op_0ee8_32_nf;
+extern cpuop_func op_0ee8_32_ff;
+extern cpuop_func op_0ef0_32_nf;
+extern cpuop_func op_0ef0_32_ff;
+extern cpuop_func op_0ef8_32_nf;
+extern cpuop_func op_0ef8_32_ff;
+extern cpuop_func op_0ef9_32_nf;
+extern cpuop_func op_0ef9_32_ff;
+extern cpuop_func op_0efc_32_nf;
+extern cpuop_func op_0efc_32_ff;
+extern cpuop_func op_1000_32_nf;
+extern cpuop_func op_1000_32_ff;
+extern cpuop_func op_1010_32_nf;
+extern cpuop_func op_1010_32_ff;
+extern cpuop_func op_1018_32_nf;
+extern cpuop_func op_1018_32_ff;
+extern cpuop_func op_1020_32_nf;
+extern cpuop_func op_1020_32_ff;
+extern cpuop_func op_1028_32_nf;
+extern cpuop_func op_1028_32_ff;
+extern cpuop_func op_1030_32_nf;
+extern cpuop_func op_1030_32_ff;
+extern cpuop_func op_1038_32_nf;
+extern cpuop_func op_1038_32_ff;
+extern cpuop_func op_1039_32_nf;
+extern cpuop_func op_1039_32_ff;
+extern cpuop_func op_103a_32_nf;
+extern cpuop_func op_103a_32_ff;
+extern cpuop_func op_103b_32_nf;
+extern cpuop_func op_103b_32_ff;
+extern cpuop_func op_103c_32_nf;
+extern cpuop_func op_103c_32_ff;
+extern cpuop_func op_1080_32_nf;
+extern cpuop_func op_1080_32_ff;
+extern cpuop_func op_1090_32_nf;
+extern cpuop_func op_1090_32_ff;
+extern cpuop_func op_1098_32_nf;
+extern cpuop_func op_1098_32_ff;
+extern cpuop_func op_10a0_32_nf;
+extern cpuop_func op_10a0_32_ff;
+extern cpuop_func op_10a8_32_nf;
+extern cpuop_func op_10a8_32_ff;
+extern cpuop_func op_10b0_32_nf;
+extern cpuop_func op_10b0_32_ff;
+extern cpuop_func op_10b8_32_nf;
+extern cpuop_func op_10b8_32_ff;
+extern cpuop_func op_10b9_32_nf;
+extern cpuop_func op_10b9_32_ff;
+extern cpuop_func op_10ba_32_nf;
+extern cpuop_func op_10ba_32_ff;
+extern cpuop_func op_10bb_32_nf;
+extern cpuop_func op_10bb_32_ff;
+extern cpuop_func op_10bc_32_nf;
+extern cpuop_func op_10bc_32_ff;
+extern cpuop_func op_10c0_32_nf;
+extern cpuop_func op_10c0_32_ff;
+extern cpuop_func op_10d0_32_nf;
+extern cpuop_func op_10d0_32_ff;
+extern cpuop_func op_10d8_32_nf;
+extern cpuop_func op_10d8_32_ff;
+extern cpuop_func op_10e0_32_nf;
+extern cpuop_func op_10e0_32_ff;
+extern cpuop_func op_10e8_32_nf;
+extern cpuop_func op_10e8_32_ff;
+extern cpuop_func op_10f0_32_nf;
+extern cpuop_func op_10f0_32_ff;
+extern cpuop_func op_10f8_32_nf;
+extern cpuop_func op_10f8_32_ff;
+extern cpuop_func op_10f9_32_nf;
+extern cpuop_func op_10f9_32_ff;
+extern cpuop_func op_10fa_32_nf;
+extern cpuop_func op_10fa_32_ff;
+extern cpuop_func op_10fb_32_nf;
+extern cpuop_func op_10fb_32_ff;
+extern cpuop_func op_10fc_32_nf;
+extern cpuop_func op_10fc_32_ff;
+extern cpuop_func op_1100_32_nf;
+extern cpuop_func op_1100_32_ff;
+extern cpuop_func op_1110_32_nf;
+extern cpuop_func op_1110_32_ff;
+extern cpuop_func op_1118_32_nf;
+extern cpuop_func op_1118_32_ff;
+extern cpuop_func op_1120_32_nf;
+extern cpuop_func op_1120_32_ff;
+extern cpuop_func op_1128_32_nf;
+extern cpuop_func op_1128_32_ff;
+extern cpuop_func op_1130_32_nf;
+extern cpuop_func op_1130_32_ff;
+extern cpuop_func op_1138_32_nf;
+extern cpuop_func op_1138_32_ff;
+extern cpuop_func op_1139_32_nf;
+extern cpuop_func op_1139_32_ff;
+extern cpuop_func op_113a_32_nf;
+extern cpuop_func op_113a_32_ff;
+extern cpuop_func op_113b_32_nf;
+extern cpuop_func op_113b_32_ff;
+extern cpuop_func op_113c_32_nf;
+extern cpuop_func op_113c_32_ff;
+extern cpuop_func op_1140_32_nf;
+extern cpuop_func op_1140_32_ff;
+extern cpuop_func op_1150_32_nf;
+extern cpuop_func op_1150_32_ff;
+extern cpuop_func op_1158_32_nf;
+extern cpuop_func op_1158_32_ff;
+extern cpuop_func op_1160_32_nf;
+extern cpuop_func op_1160_32_ff;
+extern cpuop_func op_1168_32_nf;
+extern cpuop_func op_1168_32_ff;
+extern cpuop_func op_1170_32_nf;
+extern cpuop_func op_1170_32_ff;
+extern cpuop_func op_1178_32_nf;
+extern cpuop_func op_1178_32_ff;
+extern cpuop_func op_1179_32_nf;
+extern cpuop_func op_1179_32_ff;
+extern cpuop_func op_117a_32_nf;
+extern cpuop_func op_117a_32_ff;
+extern cpuop_func op_117b_32_nf;
+extern cpuop_func op_117b_32_ff;
+extern cpuop_func op_117c_32_nf;
+extern cpuop_func op_117c_32_ff;
+extern cpuop_func op_1180_32_nf;
+extern cpuop_func op_1180_32_ff;
+extern cpuop_func op_1190_32_nf;
+extern cpuop_func op_1190_32_ff;
+extern cpuop_func op_1198_32_nf;
+extern cpuop_func op_1198_32_ff;
+extern cpuop_func op_11a0_32_nf;
+extern cpuop_func op_11a0_32_ff;
+extern cpuop_func op_11a8_32_nf;
+extern cpuop_func op_11a8_32_ff;
+extern cpuop_func op_11b0_32_nf;
+extern cpuop_func op_11b0_32_ff;
+extern cpuop_func op_11b8_32_nf;
+extern cpuop_func op_11b8_32_ff;
+extern cpuop_func op_11b9_32_nf;
+extern cpuop_func op_11b9_32_ff;
+extern cpuop_func op_11ba_32_nf;
+extern cpuop_func op_11ba_32_ff;
+extern cpuop_func op_11bb_32_nf;
+extern cpuop_func op_11bb_32_ff;
+extern cpuop_func op_11bc_32_nf;
+extern cpuop_func op_11bc_32_ff;
+extern cpuop_func op_11c0_32_nf;
+extern cpuop_func op_11c0_32_ff;
+extern cpuop_func op_11d0_32_nf;
+extern cpuop_func op_11d0_32_ff;
+extern cpuop_func op_11d8_32_nf;
+extern cpuop_func op_11d8_32_ff;
+extern cpuop_func op_11e0_32_nf;
+extern cpuop_func op_11e0_32_ff;
+extern cpuop_func op_11e8_32_nf;
+extern cpuop_func op_11e8_32_ff;
+extern cpuop_func op_11f0_32_nf;
+extern cpuop_func op_11f0_32_ff;
+extern cpuop_func op_11f8_32_nf;
+extern cpuop_func op_11f8_32_ff;
+extern cpuop_func op_11f9_32_nf;
+extern cpuop_func op_11f9_32_ff;
+extern cpuop_func op_11fa_32_nf;
+extern cpuop_func op_11fa_32_ff;
+extern cpuop_func op_11fb_32_nf;
+extern cpuop_func op_11fb_32_ff;
+extern cpuop_func op_11fc_32_nf;
+extern cpuop_func op_11fc_32_ff;
+extern cpuop_func op_13c0_32_nf;
+extern cpuop_func op_13c0_32_ff;
+extern cpuop_func op_13d0_32_nf;
+extern cpuop_func op_13d0_32_ff;
+extern cpuop_func op_13d8_32_nf;
+extern cpuop_func op_13d8_32_ff;
+extern cpuop_func op_13e0_32_nf;
+extern cpuop_func op_13e0_32_ff;
+extern cpuop_func op_13e8_32_nf;
+extern cpuop_func op_13e8_32_ff;
+extern cpuop_func op_13f0_32_nf;
+extern cpuop_func op_13f0_32_ff;
+extern cpuop_func op_13f8_32_nf;
+extern cpuop_func op_13f8_32_ff;
+extern cpuop_func op_13f9_32_nf;
+extern cpuop_func op_13f9_32_ff;
+extern cpuop_func op_13fa_32_nf;
+extern cpuop_func op_13fa_32_ff;
+extern cpuop_func op_13fb_32_nf;
+extern cpuop_func op_13fb_32_ff;
+extern cpuop_func op_13fc_32_nf;
+extern cpuop_func op_13fc_32_ff;
+extern cpuop_func op_2000_32_nf;
+extern cpuop_func op_2000_32_ff;
+extern cpuop_func op_2008_32_nf;
+extern cpuop_func op_2008_32_ff;
+extern cpuop_func op_2010_32_nf;
+extern cpuop_func op_2010_32_ff;
+extern cpuop_func op_2018_32_nf;
+extern cpuop_func op_2018_32_ff;
+extern cpuop_func op_2020_32_nf;
+extern cpuop_func op_2020_32_ff;
+extern cpuop_func op_2028_32_nf;
+extern cpuop_func op_2028_32_ff;
+extern cpuop_func op_2030_32_nf;
+extern cpuop_func op_2030_32_ff;
+extern cpuop_func op_2038_32_nf;
+extern cpuop_func op_2038_32_ff;
+extern cpuop_func op_2039_32_nf;
+extern cpuop_func op_2039_32_ff;
+extern cpuop_func op_203a_32_nf;
+extern cpuop_func op_203a_32_ff;
+extern cpuop_func op_203b_32_nf;
+extern cpuop_func op_203b_32_ff;
+extern cpuop_func op_203c_32_nf;
+extern cpuop_func op_203c_32_ff;
+extern cpuop_func op_2040_32_nf;
+extern cpuop_func op_2040_32_ff;
+extern cpuop_func op_2048_32_nf;
+extern cpuop_func op_2048_32_ff;
+extern cpuop_func op_2050_32_nf;
+extern cpuop_func op_2050_32_ff;
+extern cpuop_func op_2058_32_nf;
+extern cpuop_func op_2058_32_ff;
+extern cpuop_func op_2060_32_nf;
+extern cpuop_func op_2060_32_ff;
+extern cpuop_func op_2068_32_nf;
+extern cpuop_func op_2068_32_ff;
+extern cpuop_func op_2070_32_nf;
+extern cpuop_func op_2070_32_ff;
+extern cpuop_func op_2078_32_nf;
+extern cpuop_func op_2078_32_ff;
+extern cpuop_func op_2079_32_nf;
+extern cpuop_func op_2079_32_ff;
+extern cpuop_func op_207a_32_nf;
+extern cpuop_func op_207a_32_ff;
+extern cpuop_func op_207b_32_nf;
+extern cpuop_func op_207b_32_ff;
+extern cpuop_func op_207c_32_nf;
+extern cpuop_func op_207c_32_ff;
+extern cpuop_func op_2080_32_nf;
+extern cpuop_func op_2080_32_ff;
+extern cpuop_func op_2088_32_nf;
+extern cpuop_func op_2088_32_ff;
+extern cpuop_func op_2090_32_nf;
+extern cpuop_func op_2090_32_ff;
+extern cpuop_func op_2098_32_nf;
+extern cpuop_func op_2098_32_ff;
+extern cpuop_func op_20a0_32_nf;
+extern cpuop_func op_20a0_32_ff;
+extern cpuop_func op_20a8_32_nf;
+extern cpuop_func op_20a8_32_ff;
+extern cpuop_func op_20b0_32_nf;
+extern cpuop_func op_20b0_32_ff;
+extern cpuop_func op_20b8_32_nf;
+extern cpuop_func op_20b8_32_ff;
+extern cpuop_func op_20b9_32_nf;
+extern cpuop_func op_20b9_32_ff;
+extern cpuop_func op_20ba_32_nf;
+extern cpuop_func op_20ba_32_ff;
+extern cpuop_func op_20bb_32_nf;
+extern cpuop_func op_20bb_32_ff;
+extern cpuop_func op_20bc_32_nf;
+extern cpuop_func op_20bc_32_ff;
+extern cpuop_func op_20c0_32_nf;
+extern cpuop_func op_20c0_32_ff;
+extern cpuop_func op_20c8_32_nf;
+extern cpuop_func op_20c8_32_ff;
+extern cpuop_func op_20d0_32_nf;
+extern cpuop_func op_20d0_32_ff;
+extern cpuop_func op_20d8_32_nf;
+extern cpuop_func op_20d8_32_ff;
+extern cpuop_func op_20e0_32_nf;
+extern cpuop_func op_20e0_32_ff;
+extern cpuop_func op_20e8_32_nf;
+extern cpuop_func op_20e8_32_ff;
+extern cpuop_func op_20f0_32_nf;
+extern cpuop_func op_20f0_32_ff;
+extern cpuop_func op_20f8_32_nf;
+extern cpuop_func op_20f8_32_ff;
+extern cpuop_func op_20f9_32_nf;
+extern cpuop_func op_20f9_32_ff;
+extern cpuop_func op_20fa_32_nf;
+extern cpuop_func op_20fa_32_ff;
+extern cpuop_func op_20fb_32_nf;
+extern cpuop_func op_20fb_32_ff;
+extern cpuop_func op_20fc_32_nf;
+extern cpuop_func op_20fc_32_ff;
+extern cpuop_func op_2100_32_nf;
+extern cpuop_func op_2100_32_ff;
+extern cpuop_func op_2108_32_nf;
+extern cpuop_func op_2108_32_ff;
+extern cpuop_func op_2110_32_nf;
+extern cpuop_func op_2110_32_ff;
+extern cpuop_func op_2118_32_nf;
+extern cpuop_func op_2118_32_ff;
+extern cpuop_func op_2120_32_nf;
+extern cpuop_func op_2120_32_ff;
+extern cpuop_func op_2128_32_nf;
+extern cpuop_func op_2128_32_ff;
+extern cpuop_func op_2130_32_nf;
+extern cpuop_func op_2130_32_ff;
+extern cpuop_func op_2138_32_nf;
+extern cpuop_func op_2138_32_ff;
+extern cpuop_func op_2139_32_nf;
+extern cpuop_func op_2139_32_ff;
+extern cpuop_func op_213a_32_nf;
+extern cpuop_func op_213a_32_ff;
+extern cpuop_func op_213b_32_nf;
+extern cpuop_func op_213b_32_ff;
+extern cpuop_func op_213c_32_nf;
+extern cpuop_func op_213c_32_ff;
+extern cpuop_func op_2140_32_nf;
+extern cpuop_func op_2140_32_ff;
+extern cpuop_func op_2148_32_nf;
+extern cpuop_func op_2148_32_ff;
+extern cpuop_func op_2150_32_nf;
+extern cpuop_func op_2150_32_ff;
+extern cpuop_func op_2158_32_nf;
+extern cpuop_func op_2158_32_ff;
+extern cpuop_func op_2160_32_nf;
+extern cpuop_func op_2160_32_ff;
+extern cpuop_func op_2168_32_nf;
+extern cpuop_func op_2168_32_ff;
+extern cpuop_func op_2170_32_nf;
+extern cpuop_func op_2170_32_ff;
+extern cpuop_func op_2178_32_nf;
+extern cpuop_func op_2178_32_ff;
+extern cpuop_func op_2179_32_nf;
+extern cpuop_func op_2179_32_ff;
+extern cpuop_func op_217a_32_nf;
+extern cpuop_func op_217a_32_ff;
+extern cpuop_func op_217b_32_nf;
+extern cpuop_func op_217b_32_ff;
+extern cpuop_func op_217c_32_nf;
+extern cpuop_func op_217c_32_ff;
+extern cpuop_func op_2180_32_nf;
+extern cpuop_func op_2180_32_ff;
+extern cpuop_func op_2188_32_nf;
+extern cpuop_func op_2188_32_ff;
+extern cpuop_func op_2190_32_nf;
+extern cpuop_func op_2190_32_ff;
+extern cpuop_func op_2198_32_nf;
+extern cpuop_func op_2198_32_ff;
+extern cpuop_func op_21a0_32_nf;
+extern cpuop_func op_21a0_32_ff;
+extern cpuop_func op_21a8_32_nf;
+extern cpuop_func op_21a8_32_ff;
+extern cpuop_func op_21b0_32_nf;
+extern cpuop_func op_21b0_32_ff;
+extern cpuop_func op_21b8_32_nf;
+extern cpuop_func op_21b8_32_ff;
+extern cpuop_func op_21b9_32_nf;
+extern cpuop_func op_21b9_32_ff;
+extern cpuop_func op_21ba_32_nf;
+extern cpuop_func op_21ba_32_ff;
+extern cpuop_func op_21bb_32_nf;
+extern cpuop_func op_21bb_32_ff;
+extern cpuop_func op_21bc_32_nf;
+extern cpuop_func op_21bc_32_ff;
+extern cpuop_func op_21c0_32_nf;
+extern cpuop_func op_21c0_32_ff;
+extern cpuop_func op_21c8_32_nf;
+extern cpuop_func op_21c8_32_ff;
+extern cpuop_func op_21d0_32_nf;
+extern cpuop_func op_21d0_32_ff;
+extern cpuop_func op_21d8_32_nf;
+extern cpuop_func op_21d8_32_ff;
+extern cpuop_func op_21e0_32_nf;
+extern cpuop_func op_21e0_32_ff;
+extern cpuop_func op_21e8_32_nf;
+extern cpuop_func op_21e8_32_ff;
+extern cpuop_func op_21f0_32_nf;
+extern cpuop_func op_21f0_32_ff;
+extern cpuop_func op_21f8_32_nf;
+extern cpuop_func op_21f8_32_ff;
+extern cpuop_func op_21f9_32_nf;
+extern cpuop_func op_21f9_32_ff;
+extern cpuop_func op_21fa_32_nf;
+extern cpuop_func op_21fa_32_ff;
+extern cpuop_func op_21fb_32_nf;
+extern cpuop_func op_21fb_32_ff;
+extern cpuop_func op_21fc_32_nf;
+extern cpuop_func op_21fc_32_ff;
+extern cpuop_func op_23c0_32_nf;
+extern cpuop_func op_23c0_32_ff;
+extern cpuop_func op_23c8_32_nf;
+extern cpuop_func op_23c8_32_ff;
+extern cpuop_func op_23d0_32_nf;
+extern cpuop_func op_23d0_32_ff;
+extern cpuop_func op_23d8_32_nf;
+extern cpuop_func op_23d8_32_ff;
+extern cpuop_func op_23e0_32_nf;
+extern cpuop_func op_23e0_32_ff;
+extern cpuop_func op_23e8_32_nf;
+extern cpuop_func op_23e8_32_ff;
+extern cpuop_func op_23f0_32_nf;
+extern cpuop_func op_23f0_32_ff;
+extern cpuop_func op_23f8_32_nf;
+extern cpuop_func op_23f8_32_ff;
+extern cpuop_func op_23f9_32_nf;
+extern cpuop_func op_23f9_32_ff;
+extern cpuop_func op_23fa_32_nf;
+extern cpuop_func op_23fa_32_ff;
+extern cpuop_func op_23fb_32_nf;
+extern cpuop_func op_23fb_32_ff;
+extern cpuop_func op_23fc_32_nf;
+extern cpuop_func op_23fc_32_ff;
+extern cpuop_func op_3000_32_nf;
+extern cpuop_func op_3000_32_ff;
+extern cpuop_func op_3008_32_nf;
+extern cpuop_func op_3008_32_ff;
+extern cpuop_func op_3010_32_nf;
+extern cpuop_func op_3010_32_ff;
+extern cpuop_func op_3018_32_nf;
+extern cpuop_func op_3018_32_ff;
+extern cpuop_func op_3020_32_nf;
+extern cpuop_func op_3020_32_ff;
+extern cpuop_func op_3028_32_nf;
+extern cpuop_func op_3028_32_ff;
+extern cpuop_func op_3030_32_nf;
+extern cpuop_func op_3030_32_ff;
+extern cpuop_func op_3038_32_nf;
+extern cpuop_func op_3038_32_ff;
+extern cpuop_func op_3039_32_nf;
+extern cpuop_func op_3039_32_ff;
+extern cpuop_func op_303a_32_nf;
+extern cpuop_func op_303a_32_ff;
+extern cpuop_func op_303b_32_nf;
+extern cpuop_func op_303b_32_ff;
+extern cpuop_func op_303c_32_nf;
+extern cpuop_func op_303c_32_ff;
+extern cpuop_func op_3040_32_nf;
+extern cpuop_func op_3040_32_ff;
+extern cpuop_func op_3048_32_nf;
+extern cpuop_func op_3048_32_ff;
+extern cpuop_func op_3050_32_nf;
+extern cpuop_func op_3050_32_ff;
+extern cpuop_func op_3058_32_nf;
+extern cpuop_func op_3058_32_ff;
+extern cpuop_func op_3060_32_nf;
+extern cpuop_func op_3060_32_ff;
+extern cpuop_func op_3068_32_nf;
+extern cpuop_func op_3068_32_ff;
+extern cpuop_func op_3070_32_nf;
+extern cpuop_func op_3070_32_ff;
+extern cpuop_func op_3078_32_nf;
+extern cpuop_func op_3078_32_ff;
+extern cpuop_func op_3079_32_nf;
+extern cpuop_func op_3079_32_ff;
+extern cpuop_func op_307a_32_nf;
+extern cpuop_func op_307a_32_ff;
+extern cpuop_func op_307b_32_nf;
+extern cpuop_func op_307b_32_ff;
+extern cpuop_func op_307c_32_nf;
+extern cpuop_func op_307c_32_ff;
+extern cpuop_func op_3080_32_nf;
+extern cpuop_func op_3080_32_ff;
+extern cpuop_func op_3088_32_nf;
+extern cpuop_func op_3088_32_ff;
+extern cpuop_func op_3090_32_nf;
+extern cpuop_func op_3090_32_ff;
+extern cpuop_func op_3098_32_nf;
+extern cpuop_func op_3098_32_ff;
+extern cpuop_func op_30a0_32_nf;
+extern cpuop_func op_30a0_32_ff;
+extern cpuop_func op_30a8_32_nf;
+extern cpuop_func op_30a8_32_ff;
+extern cpuop_func op_30b0_32_nf;
+extern cpuop_func op_30b0_32_ff;
+extern cpuop_func op_30b8_32_nf;
+extern cpuop_func op_30b8_32_ff;
+extern cpuop_func op_30b9_32_nf;
+extern cpuop_func op_30b9_32_ff;
+extern cpuop_func op_30ba_32_nf;
+extern cpuop_func op_30ba_32_ff;
+extern cpuop_func op_30bb_32_nf;
+extern cpuop_func op_30bb_32_ff;
+extern cpuop_func op_30bc_32_nf;
+extern cpuop_func op_30bc_32_ff;
+extern cpuop_func op_30c0_32_nf;
+extern cpuop_func op_30c0_32_ff;
+extern cpuop_func op_30c8_32_nf;
+extern cpuop_func op_30c8_32_ff;
+extern cpuop_func op_30d0_32_nf;
+extern cpuop_func op_30d0_32_ff;
+extern cpuop_func op_30d8_32_nf;
+extern cpuop_func op_30d8_32_ff;
+extern cpuop_func op_30e0_32_nf;
+extern cpuop_func op_30e0_32_ff;
+extern cpuop_func op_30e8_32_nf;
+extern cpuop_func op_30e8_32_ff;
+extern cpuop_func op_30f0_32_nf;
+extern cpuop_func op_30f0_32_ff;
+extern cpuop_func op_30f8_32_nf;
+extern cpuop_func op_30f8_32_ff;
+extern cpuop_func op_30f9_32_nf;
+extern cpuop_func op_30f9_32_ff;
+extern cpuop_func op_30fa_32_nf;
+extern cpuop_func op_30fa_32_ff;
+extern cpuop_func op_30fb_32_nf;
+extern cpuop_func op_30fb_32_ff;
+extern cpuop_func op_30fc_32_nf;
+extern cpuop_func op_30fc_32_ff;
+extern cpuop_func op_3100_32_nf;
+extern cpuop_func op_3100_32_ff;
+extern cpuop_func op_3108_32_nf;
+extern cpuop_func op_3108_32_ff;
+extern cpuop_func op_3110_32_nf;
+extern cpuop_func op_3110_32_ff;
+extern cpuop_func op_3118_32_nf;
+extern cpuop_func op_3118_32_ff;
+extern cpuop_func op_3120_32_nf;
+extern cpuop_func op_3120_32_ff;
+extern cpuop_func op_3128_32_nf;
+extern cpuop_func op_3128_32_ff;
+extern cpuop_func op_3130_32_nf;
+extern cpuop_func op_3130_32_ff;
+extern cpuop_func op_3138_32_nf;
+extern cpuop_func op_3138_32_ff;
+extern cpuop_func op_3139_32_nf;
+extern cpuop_func op_3139_32_ff;
+extern cpuop_func op_313a_32_nf;
+extern cpuop_func op_313a_32_ff;
+extern cpuop_func op_313b_32_nf;
+extern cpuop_func op_313b_32_ff;
+extern cpuop_func op_313c_32_nf;
+extern cpuop_func op_313c_32_ff;
+extern cpuop_func op_3140_32_nf;
+extern cpuop_func op_3140_32_ff;
+extern cpuop_func op_3148_32_nf;
+extern cpuop_func op_3148_32_ff;
+extern cpuop_func op_3150_32_nf;
+extern cpuop_func op_3150_32_ff;
+extern cpuop_func op_3158_32_nf;
+extern cpuop_func op_3158_32_ff;
+extern cpuop_func op_3160_32_nf;
+extern cpuop_func op_3160_32_ff;
+extern cpuop_func op_3168_32_nf;
+extern cpuop_func op_3168_32_ff;
+extern cpuop_func op_3170_32_nf;
+extern cpuop_func op_3170_32_ff;
+extern cpuop_func op_3178_32_nf;
+extern cpuop_func op_3178_32_ff;
+extern cpuop_func op_3179_32_nf;
+extern cpuop_func op_3179_32_ff;
+extern cpuop_func op_317a_32_nf;
+extern cpuop_func op_317a_32_ff;
+extern cpuop_func op_317b_32_nf;
+extern cpuop_func op_317b_32_ff;
+extern cpuop_func op_317c_32_nf;
+extern cpuop_func op_317c_32_ff;
+extern cpuop_func op_3180_32_nf;
+extern cpuop_func op_3180_32_ff;
+extern cpuop_func op_3188_32_nf;
+extern cpuop_func op_3188_32_ff;
+extern cpuop_func op_3190_32_nf;
+extern cpuop_func op_3190_32_ff;
+extern cpuop_func op_3198_32_nf;
+extern cpuop_func op_3198_32_ff;
+extern cpuop_func op_31a0_32_nf;
+extern cpuop_func op_31a0_32_ff;
+extern cpuop_func op_31a8_32_nf;
+extern cpuop_func op_31a8_32_ff;
+extern cpuop_func op_31b0_32_nf;
+extern cpuop_func op_31b0_32_ff;
+extern cpuop_func op_31b8_32_nf;
+extern cpuop_func op_31b8_32_ff;
+extern cpuop_func op_31b9_32_nf;
+extern cpuop_func op_31b9_32_ff;
+extern cpuop_func op_31ba_32_nf;
+extern cpuop_func op_31ba_32_ff;
+extern cpuop_func op_31bb_32_nf;
+extern cpuop_func op_31bb_32_ff;
+extern cpuop_func op_31bc_32_nf;
+extern cpuop_func op_31bc_32_ff;
+extern cpuop_func op_31c0_32_nf;
+extern cpuop_func op_31c0_32_ff;
+extern cpuop_func op_31c8_32_nf;
+extern cpuop_func op_31c8_32_ff;
+extern cpuop_func op_31d0_32_nf;
+extern cpuop_func op_31d0_32_ff;
+extern cpuop_func op_31d8_32_nf;
+extern cpuop_func op_31d8_32_ff;
+extern cpuop_func op_31e0_32_nf;
+extern cpuop_func op_31e0_32_ff;
+extern cpuop_func op_31e8_32_nf;
+extern cpuop_func op_31e8_32_ff;
+extern cpuop_func op_31f0_32_nf;
+extern cpuop_func op_31f0_32_ff;
+extern cpuop_func op_31f8_32_nf;
+extern cpuop_func op_31f8_32_ff;
+extern cpuop_func op_31f9_32_nf;
+extern cpuop_func op_31f9_32_ff;
+extern cpuop_func op_31fa_32_nf;
+extern cpuop_func op_31fa_32_ff;
+extern cpuop_func op_31fb_32_nf;
+extern cpuop_func op_31fb_32_ff;
+extern cpuop_func op_31fc_32_nf;
+extern cpuop_func op_31fc_32_ff;
+extern cpuop_func op_33c0_32_nf;
+extern cpuop_func op_33c0_32_ff;
+extern cpuop_func op_33c8_32_nf;
+extern cpuop_func op_33c8_32_ff;
+extern cpuop_func op_33d0_32_nf;
+extern cpuop_func op_33d0_32_ff;
+extern cpuop_func op_33d8_32_nf;
+extern cpuop_func op_33d8_32_ff;
+extern cpuop_func op_33e0_32_nf;
+extern cpuop_func op_33e0_32_ff;
+extern cpuop_func op_33e8_32_nf;
+extern cpuop_func op_33e8_32_ff;
+extern cpuop_func op_33f0_32_nf;
+extern cpuop_func op_33f0_32_ff;
+extern cpuop_func op_33f8_32_nf;
+extern cpuop_func op_33f8_32_ff;
+extern cpuop_func op_33f9_32_nf;
+extern cpuop_func op_33f9_32_ff;
+extern cpuop_func op_33fa_32_nf;
+extern cpuop_func op_33fa_32_ff;
+extern cpuop_func op_33fb_32_nf;
+extern cpuop_func op_33fb_32_ff;
+extern cpuop_func op_33fc_32_nf;
+extern cpuop_func op_33fc_32_ff;
+extern cpuop_func op_4000_32_nf;
+extern cpuop_func op_4000_32_ff;
+extern cpuop_func op_4010_32_nf;
+extern cpuop_func op_4010_32_ff;
+extern cpuop_func op_4018_32_nf;
+extern cpuop_func op_4018_32_ff;
+extern cpuop_func op_4020_32_nf;
+extern cpuop_func op_4020_32_ff;
+extern cpuop_func op_4028_32_nf;
+extern cpuop_func op_4028_32_ff;
+extern cpuop_func op_4030_32_nf;
+extern cpuop_func op_4030_32_ff;
+extern cpuop_func op_4038_32_nf;
+extern cpuop_func op_4038_32_ff;
+extern cpuop_func op_4039_32_nf;
+extern cpuop_func op_4039_32_ff;
+extern cpuop_func op_4040_32_nf;
+extern cpuop_func op_4040_32_ff;
+extern cpuop_func op_4050_32_nf;
+extern cpuop_func op_4050_32_ff;
+extern cpuop_func op_4058_32_nf;
+extern cpuop_func op_4058_32_ff;
+extern cpuop_func op_4060_32_nf;
+extern cpuop_func op_4060_32_ff;
+extern cpuop_func op_4068_32_nf;
+extern cpuop_func op_4068_32_ff;
+extern cpuop_func op_4070_32_nf;
+extern cpuop_func op_4070_32_ff;
+extern cpuop_func op_4078_32_nf;
+extern cpuop_func op_4078_32_ff;
+extern cpuop_func op_4079_32_nf;
+extern cpuop_func op_4079_32_ff;
+extern cpuop_func op_4080_32_nf;
+extern cpuop_func op_4080_32_ff;
+extern cpuop_func op_4090_32_nf;
+extern cpuop_func op_4090_32_ff;
+extern cpuop_func op_4098_32_nf;
+extern cpuop_func op_4098_32_ff;
+extern cpuop_func op_40a0_32_nf;
+extern cpuop_func op_40a0_32_ff;
+extern cpuop_func op_40a8_32_nf;
+extern cpuop_func op_40a8_32_ff;
+extern cpuop_func op_40b0_32_nf;
+extern cpuop_func op_40b0_32_ff;
+extern cpuop_func op_40b8_32_nf;
+extern cpuop_func op_40b8_32_ff;
+extern cpuop_func op_40b9_32_nf;
+extern cpuop_func op_40b9_32_ff;
+extern cpuop_func op_40c0_32_nf;
+extern cpuop_func op_40c0_32_ff;
+extern cpuop_func op_40d0_32_nf;
+extern cpuop_func op_40d0_32_ff;
+extern cpuop_func op_40d8_32_nf;
+extern cpuop_func op_40d8_32_ff;
+extern cpuop_func op_40e0_32_nf;
+extern cpuop_func op_40e0_32_ff;
+extern cpuop_func op_40e8_32_nf;
+extern cpuop_func op_40e8_32_ff;
+extern cpuop_func op_40f0_32_nf;
+extern cpuop_func op_40f0_32_ff;
+extern cpuop_func op_40f8_32_nf;
+extern cpuop_func op_40f8_32_ff;
+extern cpuop_func op_40f9_32_nf;
+extern cpuop_func op_40f9_32_ff;
+extern cpuop_func op_4100_32_nf;
+extern cpuop_func op_4100_32_ff;
+extern cpuop_func op_4110_32_nf;
+extern cpuop_func op_4110_32_ff;
+extern cpuop_func op_4118_32_nf;
+extern cpuop_func op_4118_32_ff;
+extern cpuop_func op_4120_32_nf;
+extern cpuop_func op_4120_32_ff;
+extern cpuop_func op_4128_32_nf;
+extern cpuop_func op_4128_32_ff;
+extern cpuop_func op_4130_32_nf;
+extern cpuop_func op_4130_32_ff;
+extern cpuop_func op_4138_32_nf;
+extern cpuop_func op_4138_32_ff;
+extern cpuop_func op_4139_32_nf;
+extern cpuop_func op_4139_32_ff;
+extern cpuop_func op_413a_32_nf;
+extern cpuop_func op_413a_32_ff;
+extern cpuop_func op_413b_32_nf;
+extern cpuop_func op_413b_32_ff;
+extern cpuop_func op_413c_32_nf;
+extern cpuop_func op_413c_32_ff;
+extern cpuop_func op_4180_32_nf;
+extern cpuop_func op_4180_32_ff;
+extern cpuop_func op_4190_32_nf;
+extern cpuop_func op_4190_32_ff;
+extern cpuop_func op_4198_32_nf;
+extern cpuop_func op_4198_32_ff;
+extern cpuop_func op_41a0_32_nf;
+extern cpuop_func op_41a0_32_ff;
+extern cpuop_func op_41a8_32_nf;
+extern cpuop_func op_41a8_32_ff;
+extern cpuop_func op_41b0_32_nf;
+extern cpuop_func op_41b0_32_ff;
+extern cpuop_func op_41b8_32_nf;
+extern cpuop_func op_41b8_32_ff;
+extern cpuop_func op_41b9_32_nf;
+extern cpuop_func op_41b9_32_ff;
+extern cpuop_func op_41ba_32_nf;
+extern cpuop_func op_41ba_32_ff;
+extern cpuop_func op_41bb_32_nf;
+extern cpuop_func op_41bb_32_ff;
+extern cpuop_func op_41bc_32_nf;
+extern cpuop_func op_41bc_32_ff;
+extern cpuop_func op_41d0_32_nf;
+extern cpuop_func op_41d0_32_ff;
+extern cpuop_func op_41e8_32_nf;
+extern cpuop_func op_41e8_32_ff;
+extern cpuop_func op_41f0_32_nf;
+extern cpuop_func op_41f0_32_ff;
+extern cpuop_func op_41f8_32_nf;
+extern cpuop_func op_41f8_32_ff;
+extern cpuop_func op_41f9_32_nf;
+extern cpuop_func op_41f9_32_ff;
+extern cpuop_func op_41fa_32_nf;
+extern cpuop_func op_41fa_32_ff;
+extern cpuop_func op_41fb_32_nf;
+extern cpuop_func op_41fb_32_ff;
+extern cpuop_func op_4200_32_nf;
+extern cpuop_func op_4200_32_ff;
+extern cpuop_func op_4210_32_nf;
+extern cpuop_func op_4210_32_ff;
+extern cpuop_func op_4218_32_nf;
+extern cpuop_func op_4218_32_ff;
+extern cpuop_func op_4220_32_nf;
+extern cpuop_func op_4220_32_ff;
+extern cpuop_func op_4228_32_nf;
+extern cpuop_func op_4228_32_ff;
+extern cpuop_func op_4230_32_nf;
+extern cpuop_func op_4230_32_ff;
+extern cpuop_func op_4238_32_nf;
+extern cpuop_func op_4238_32_ff;
+extern cpuop_func op_4239_32_nf;
+extern cpuop_func op_4239_32_ff;
+extern cpuop_func op_4240_32_nf;
+extern cpuop_func op_4240_32_ff;
+extern cpuop_func op_4250_32_nf;
+extern cpuop_func op_4250_32_ff;
+extern cpuop_func op_4258_32_nf;
+extern cpuop_func op_4258_32_ff;
+extern cpuop_func op_4260_32_nf;
+extern cpuop_func op_4260_32_ff;
+extern cpuop_func op_4268_32_nf;
+extern cpuop_func op_4268_32_ff;
+extern cpuop_func op_4270_32_nf;
+extern cpuop_func op_4270_32_ff;
+extern cpuop_func op_4278_32_nf;
+extern cpuop_func op_4278_32_ff;
+extern cpuop_func op_4279_32_nf;
+extern cpuop_func op_4279_32_ff;
+extern cpuop_func op_4280_32_nf;
+extern cpuop_func op_4280_32_ff;
+extern cpuop_func op_4290_32_nf;
+extern cpuop_func op_4290_32_ff;
+extern cpuop_func op_4298_32_nf;
+extern cpuop_func op_4298_32_ff;
+extern cpuop_func op_42a0_32_nf;
+extern cpuop_func op_42a0_32_ff;
+extern cpuop_func op_42a8_32_nf;
+extern cpuop_func op_42a8_32_ff;
+extern cpuop_func op_42b0_32_nf;
+extern cpuop_func op_42b0_32_ff;
+extern cpuop_func op_42b8_32_nf;
+extern cpuop_func op_42b8_32_ff;
+extern cpuop_func op_42b9_32_nf;
+extern cpuop_func op_42b9_32_ff;
+extern cpuop_func op_42c0_32_nf;
+extern cpuop_func op_42c0_32_ff;
+extern cpuop_func op_42d0_32_nf;
+extern cpuop_func op_42d0_32_ff;
+extern cpuop_func op_42d8_32_nf;
+extern cpuop_func op_42d8_32_ff;
+extern cpuop_func op_42e0_32_nf;
+extern cpuop_func op_42e0_32_ff;
+extern cpuop_func op_42e8_32_nf;
+extern cpuop_func op_42e8_32_ff;
+extern cpuop_func op_42f0_32_nf;
+extern cpuop_func op_42f0_32_ff;
+extern cpuop_func op_42f8_32_nf;
+extern cpuop_func op_42f8_32_ff;
+extern cpuop_func op_42f9_32_nf;
+extern cpuop_func op_42f9_32_ff;
+extern cpuop_func op_4400_32_nf;
+extern cpuop_func op_4400_32_ff;
+extern cpuop_func op_4410_32_nf;
+extern cpuop_func op_4410_32_ff;
+extern cpuop_func op_4418_32_nf;
+extern cpuop_func op_4418_32_ff;
+extern cpuop_func op_4420_32_nf;
+extern cpuop_func op_4420_32_ff;
+extern cpuop_func op_4428_32_nf;
+extern cpuop_func op_4428_32_ff;
+extern cpuop_func op_4430_32_nf;
+extern cpuop_func op_4430_32_ff;
+extern cpuop_func op_4438_32_nf;
+extern cpuop_func op_4438_32_ff;
+extern cpuop_func op_4439_32_nf;
+extern cpuop_func op_4439_32_ff;
+extern cpuop_func op_4440_32_nf;
+extern cpuop_func op_4440_32_ff;
+extern cpuop_func op_4450_32_nf;
+extern cpuop_func op_4450_32_ff;
+extern cpuop_func op_4458_32_nf;
+extern cpuop_func op_4458_32_ff;
+extern cpuop_func op_4460_32_nf;
+extern cpuop_func op_4460_32_ff;
+extern cpuop_func op_4468_32_nf;
+extern cpuop_func op_4468_32_ff;
+extern cpuop_func op_4470_32_nf;
+extern cpuop_func op_4470_32_ff;
+extern cpuop_func op_4478_32_nf;
+extern cpuop_func op_4478_32_ff;
+extern cpuop_func op_4479_32_nf;
+extern cpuop_func op_4479_32_ff;
+extern cpuop_func op_4480_32_nf;
+extern cpuop_func op_4480_32_ff;
+extern cpuop_func op_4490_32_nf;
+extern cpuop_func op_4490_32_ff;
+extern cpuop_func op_4498_32_nf;
+extern cpuop_func op_4498_32_ff;
+extern cpuop_func op_44a0_32_nf;
+extern cpuop_func op_44a0_32_ff;
+extern cpuop_func op_44a8_32_nf;
+extern cpuop_func op_44a8_32_ff;
+extern cpuop_func op_44b0_32_nf;
+extern cpuop_func op_44b0_32_ff;
+extern cpuop_func op_44b8_32_nf;
+extern cpuop_func op_44b8_32_ff;
+extern cpuop_func op_44b9_32_nf;
+extern cpuop_func op_44b9_32_ff;
+extern cpuop_func op_44c0_32_nf;
+extern cpuop_func op_44c0_32_ff;
+extern cpuop_func op_44d0_32_nf;
+extern cpuop_func op_44d0_32_ff;
+extern cpuop_func op_44d8_32_nf;
+extern cpuop_func op_44d8_32_ff;
+extern cpuop_func op_44e0_32_nf;
+extern cpuop_func op_44e0_32_ff;
+extern cpuop_func op_44e8_32_nf;
+extern cpuop_func op_44e8_32_ff;
+extern cpuop_func op_44f0_32_nf;
+extern cpuop_func op_44f0_32_ff;
+extern cpuop_func op_44f8_32_nf;
+extern cpuop_func op_44f8_32_ff;
+extern cpuop_func op_44f9_32_nf;
+extern cpuop_func op_44f9_32_ff;
+extern cpuop_func op_44fa_32_nf;
+extern cpuop_func op_44fa_32_ff;
+extern cpuop_func op_44fb_32_nf;
+extern cpuop_func op_44fb_32_ff;
+extern cpuop_func op_44fc_32_nf;
+extern cpuop_func op_44fc_32_ff;
+extern cpuop_func op_4600_32_nf;
+extern cpuop_func op_4600_32_ff;
+extern cpuop_func op_4610_32_nf;
+extern cpuop_func op_4610_32_ff;
+extern cpuop_func op_4618_32_nf;
+extern cpuop_func op_4618_32_ff;
+extern cpuop_func op_4620_32_nf;
+extern cpuop_func op_4620_32_ff;
+extern cpuop_func op_4628_32_nf;
+extern cpuop_func op_4628_32_ff;
+extern cpuop_func op_4630_32_nf;
+extern cpuop_func op_4630_32_ff;
+extern cpuop_func op_4638_32_nf;
+extern cpuop_func op_4638_32_ff;
+extern cpuop_func op_4639_32_nf;
+extern cpuop_func op_4639_32_ff;
+extern cpuop_func op_4640_32_nf;
+extern cpuop_func op_4640_32_ff;
+extern cpuop_func op_4650_32_nf;
+extern cpuop_func op_4650_32_ff;
+extern cpuop_func op_4658_32_nf;
+extern cpuop_func op_4658_32_ff;
+extern cpuop_func op_4660_32_nf;
+extern cpuop_func op_4660_32_ff;
+extern cpuop_func op_4668_32_nf;
+extern cpuop_func op_4668_32_ff;
+extern cpuop_func op_4670_32_nf;
+extern cpuop_func op_4670_32_ff;
+extern cpuop_func op_4678_32_nf;
+extern cpuop_func op_4678_32_ff;
+extern cpuop_func op_4679_32_nf;
+extern cpuop_func op_4679_32_ff;
+extern cpuop_func op_4680_32_nf;
+extern cpuop_func op_4680_32_ff;
+extern cpuop_func op_4690_32_nf;
+extern cpuop_func op_4690_32_ff;
+extern cpuop_func op_4698_32_nf;
+extern cpuop_func op_4698_32_ff;
+extern cpuop_func op_46a0_32_nf;
+extern cpuop_func op_46a0_32_ff;
+extern cpuop_func op_46a8_32_nf;
+extern cpuop_func op_46a8_32_ff;
+extern cpuop_func op_46b0_32_nf;
+extern cpuop_func op_46b0_32_ff;
+extern cpuop_func op_46b8_32_nf;
+extern cpuop_func op_46b8_32_ff;
+extern cpuop_func op_46b9_32_nf;
+extern cpuop_func op_46b9_32_ff;
+extern cpuop_func op_46c0_32_nf;
+extern cpuop_func op_46c0_32_ff;
+extern cpuop_func op_46d0_32_nf;
+extern cpuop_func op_46d0_32_ff;
+extern cpuop_func op_46d8_32_nf;
+extern cpuop_func op_46d8_32_ff;
+extern cpuop_func op_46e0_32_nf;
+extern cpuop_func op_46e0_32_ff;
+extern cpuop_func op_46e8_32_nf;
+extern cpuop_func op_46e8_32_ff;
+extern cpuop_func op_46f0_32_nf;
+extern cpuop_func op_46f0_32_ff;
+extern cpuop_func op_46f8_32_nf;
+extern cpuop_func op_46f8_32_ff;
+extern cpuop_func op_46f9_32_nf;
+extern cpuop_func op_46f9_32_ff;
+extern cpuop_func op_46fa_32_nf;
+extern cpuop_func op_46fa_32_ff;
+extern cpuop_func op_46fb_32_nf;
+extern cpuop_func op_46fb_32_ff;
+extern cpuop_func op_46fc_32_nf;
+extern cpuop_func op_46fc_32_ff;
+extern cpuop_func op_4800_32_nf;
+extern cpuop_func op_4800_32_ff;
+extern cpuop_func op_4808_32_nf;
+extern cpuop_func op_4808_32_ff;
+extern cpuop_func op_4810_32_nf;
+extern cpuop_func op_4810_32_ff;
+extern cpuop_func op_4818_32_nf;
+extern cpuop_func op_4818_32_ff;
+extern cpuop_func op_4820_32_nf;
+extern cpuop_func op_4820_32_ff;
+extern cpuop_func op_4828_32_nf;
+extern cpuop_func op_4828_32_ff;
+extern cpuop_func op_4830_32_nf;
+extern cpuop_func op_4830_32_ff;
+extern cpuop_func op_4838_32_nf;
+extern cpuop_func op_4838_32_ff;
+extern cpuop_func op_4839_32_nf;
+extern cpuop_func op_4839_32_ff;
+extern cpuop_func op_4840_32_nf;
+extern cpuop_func op_4840_32_ff;
+extern cpuop_func op_4848_32_nf;
+extern cpuop_func op_4848_32_ff;
+extern cpuop_func op_4850_32_nf;
+extern cpuop_func op_4850_32_ff;
+extern cpuop_func op_4868_32_nf;
+extern cpuop_func op_4868_32_ff;
+extern cpuop_func op_4870_32_nf;
+extern cpuop_func op_4870_32_ff;
+extern cpuop_func op_4878_32_nf;
+extern cpuop_func op_4878_32_ff;
+extern cpuop_func op_4879_32_nf;
+extern cpuop_func op_4879_32_ff;
+extern cpuop_func op_487a_32_nf;
+extern cpuop_func op_487a_32_ff;
+extern cpuop_func op_487b_32_nf;
+extern cpuop_func op_487b_32_ff;
+extern cpuop_func op_4880_32_nf;
+extern cpuop_func op_4880_32_ff;
+extern cpuop_func op_4890_32_nf;
+extern cpuop_func op_4890_32_ff;
+extern cpuop_func op_48a0_32_nf;
+extern cpuop_func op_48a0_32_ff;
+extern cpuop_func op_48a8_32_nf;
+extern cpuop_func op_48a8_32_ff;
+extern cpuop_func op_48b0_32_nf;
+extern cpuop_func op_48b0_32_ff;
+extern cpuop_func op_48b8_32_nf;
+extern cpuop_func op_48b8_32_ff;
+extern cpuop_func op_48b9_32_nf;
+extern cpuop_func op_48b9_32_ff;
+extern cpuop_func op_48c0_32_nf;
+extern cpuop_func op_48c0_32_ff;
+extern cpuop_func op_48d0_32_nf;
+extern cpuop_func op_48d0_32_ff;
+extern cpuop_func op_48e0_32_nf;
+extern cpuop_func op_48e0_32_ff;
+extern cpuop_func op_48e8_32_nf;
+extern cpuop_func op_48e8_32_ff;
+extern cpuop_func op_48f0_32_nf;
+extern cpuop_func op_48f0_32_ff;
+extern cpuop_func op_48f8_32_nf;
+extern cpuop_func op_48f8_32_ff;
+extern cpuop_func op_48f9_32_nf;
+extern cpuop_func op_48f9_32_ff;
+extern cpuop_func op_49c0_32_nf;
+extern cpuop_func op_49c0_32_ff;
+extern cpuop_func op_4a00_32_nf;
+extern cpuop_func op_4a00_32_ff;
+extern cpuop_func op_4a10_32_nf;
+extern cpuop_func op_4a10_32_ff;
+extern cpuop_func op_4a18_32_nf;
+extern cpuop_func op_4a18_32_ff;
+extern cpuop_func op_4a20_32_nf;
+extern cpuop_func op_4a20_32_ff;
+extern cpuop_func op_4a28_32_nf;
+extern cpuop_func op_4a28_32_ff;
+extern cpuop_func op_4a30_32_nf;
+extern cpuop_func op_4a30_32_ff;
+extern cpuop_func op_4a38_32_nf;
+extern cpuop_func op_4a38_32_ff;
+extern cpuop_func op_4a39_32_nf;
+extern cpuop_func op_4a39_32_ff;
+extern cpuop_func op_4a3a_32_nf;
+extern cpuop_func op_4a3a_32_ff;
+extern cpuop_func op_4a3b_32_nf;
+extern cpuop_func op_4a3b_32_ff;
+extern cpuop_func op_4a3c_32_nf;
+extern cpuop_func op_4a3c_32_ff;
+extern cpuop_func op_4a40_32_nf;
+extern cpuop_func op_4a40_32_ff;
+extern cpuop_func op_4a48_32_nf;
+extern cpuop_func op_4a48_32_ff;
+extern cpuop_func op_4a50_32_nf;
+extern cpuop_func op_4a50_32_ff;
+extern cpuop_func op_4a58_32_nf;
+extern cpuop_func op_4a58_32_ff;
+extern cpuop_func op_4a60_32_nf;
+extern cpuop_func op_4a60_32_ff;
+extern cpuop_func op_4a68_32_nf;
+extern cpuop_func op_4a68_32_ff;
+extern cpuop_func op_4a70_32_nf;
+extern cpuop_func op_4a70_32_ff;
+extern cpuop_func op_4a78_32_nf;
+extern cpuop_func op_4a78_32_ff;
+extern cpuop_func op_4a79_32_nf;
+extern cpuop_func op_4a79_32_ff;
+extern cpuop_func op_4a7a_32_nf;
+extern cpuop_func op_4a7a_32_ff;
+extern cpuop_func op_4a7b_32_nf;
+extern cpuop_func op_4a7b_32_ff;
+extern cpuop_func op_4a7c_32_nf;
+extern cpuop_func op_4a7c_32_ff;
+extern cpuop_func op_4a80_32_nf;
+extern cpuop_func op_4a80_32_ff;
+extern cpuop_func op_4a88_32_nf;
+extern cpuop_func op_4a88_32_ff;
+extern cpuop_func op_4a90_32_nf;
+extern cpuop_func op_4a90_32_ff;
+extern cpuop_func op_4a98_32_nf;
+extern cpuop_func op_4a98_32_ff;
+extern cpuop_func op_4aa0_32_nf;
+extern cpuop_func op_4aa0_32_ff;
+extern cpuop_func op_4aa8_32_nf;
+extern cpuop_func op_4aa8_32_ff;
+extern cpuop_func op_4ab0_32_nf;
+extern cpuop_func op_4ab0_32_ff;
+extern cpuop_func op_4ab8_32_nf;
+extern cpuop_func op_4ab8_32_ff;
+extern cpuop_func op_4ab9_32_nf;
+extern cpuop_func op_4ab9_32_ff;
+extern cpuop_func op_4aba_32_nf;
+extern cpuop_func op_4aba_32_ff;
+extern cpuop_func op_4abb_32_nf;
+extern cpuop_func op_4abb_32_ff;
+extern cpuop_func op_4abc_32_nf;
+extern cpuop_func op_4abc_32_ff;
+extern cpuop_func op_4ac0_32_nf;
+extern cpuop_func op_4ac0_32_ff;
+extern cpuop_func op_4ad0_32_nf;
+extern cpuop_func op_4ad0_32_ff;
+extern cpuop_func op_4ad8_32_nf;
+extern cpuop_func op_4ad8_32_ff;
+extern cpuop_func op_4ae0_32_nf;
+extern cpuop_func op_4ae0_32_ff;
+extern cpuop_func op_4ae8_32_nf;
+extern cpuop_func op_4ae8_32_ff;
+extern cpuop_func op_4af0_32_nf;
+extern cpuop_func op_4af0_32_ff;
+extern cpuop_func op_4af8_32_nf;
+extern cpuop_func op_4af8_32_ff;
+extern cpuop_func op_4af9_32_nf;
+extern cpuop_func op_4af9_32_ff;
+extern cpuop_func op_4c00_32_nf;
+extern cpuop_func op_4c00_32_ff;
+extern cpuop_func op_4c10_32_nf;
+extern cpuop_func op_4c10_32_ff;
+extern cpuop_func op_4c18_32_nf;
+extern cpuop_func op_4c18_32_ff;
+extern cpuop_func op_4c20_32_nf;
+extern cpuop_func op_4c20_32_ff;
+extern cpuop_func op_4c28_32_nf;
+extern cpuop_func op_4c28_32_ff;
+extern cpuop_func op_4c30_32_nf;
+extern cpuop_func op_4c30_32_ff;
+extern cpuop_func op_4c38_32_nf;
+extern cpuop_func op_4c38_32_ff;
+extern cpuop_func op_4c39_32_nf;
+extern cpuop_func op_4c39_32_ff;
+extern cpuop_func op_4c3a_32_nf;
+extern cpuop_func op_4c3a_32_ff;
+extern cpuop_func op_4c3b_32_nf;
+extern cpuop_func op_4c3b_32_ff;
+extern cpuop_func op_4c3c_32_nf;
+extern cpuop_func op_4c3c_32_ff;
+extern cpuop_func op_4c40_32_nf;
+extern cpuop_func op_4c40_32_ff;
+extern cpuop_func op_4c50_32_nf;
+extern cpuop_func op_4c50_32_ff;
+extern cpuop_func op_4c58_32_nf;
+extern cpuop_func op_4c58_32_ff;
+extern cpuop_func op_4c60_32_nf;
+extern cpuop_func op_4c60_32_ff;
+extern cpuop_func op_4c68_32_nf;
+extern cpuop_func op_4c68_32_ff;
+extern cpuop_func op_4c70_32_nf;
+extern cpuop_func op_4c70_32_ff;
+extern cpuop_func op_4c78_32_nf;
+extern cpuop_func op_4c78_32_ff;
+extern cpuop_func op_4c79_32_nf;
+extern cpuop_func op_4c79_32_ff;
+extern cpuop_func op_4c7a_32_nf;
+extern cpuop_func op_4c7a_32_ff;
+extern cpuop_func op_4c7b_32_nf;
+extern cpuop_func op_4c7b_32_ff;
+extern cpuop_func op_4c7c_32_nf;
+extern cpuop_func op_4c7c_32_ff;
+extern cpuop_func op_4c90_32_nf;
+extern cpuop_func op_4c90_32_ff;
+extern cpuop_func op_4c98_32_nf;
+extern cpuop_func op_4c98_32_ff;
+extern cpuop_func op_4ca8_32_nf;
+extern cpuop_func op_4ca8_32_ff;
+extern cpuop_func op_4cb0_32_nf;
+extern cpuop_func op_4cb0_32_ff;
+extern cpuop_func op_4cb8_32_nf;
+extern cpuop_func op_4cb8_32_ff;
+extern cpuop_func op_4cb9_32_nf;
+extern cpuop_func op_4cb9_32_ff;
+extern cpuop_func op_4cba_32_nf;
+extern cpuop_func op_4cba_32_ff;
+extern cpuop_func op_4cbb_32_nf;
+extern cpuop_func op_4cbb_32_ff;
+extern cpuop_func op_4cd0_32_nf;
+extern cpuop_func op_4cd0_32_ff;
+extern cpuop_func op_4cd8_32_nf;
+extern cpuop_func op_4cd8_32_ff;
+extern cpuop_func op_4ce8_32_nf;
+extern cpuop_func op_4ce8_32_ff;
+extern cpuop_func op_4cf0_32_nf;
+extern cpuop_func op_4cf0_32_ff;
+extern cpuop_func op_4cf8_32_nf;
+extern cpuop_func op_4cf8_32_ff;
+extern cpuop_func op_4cf9_32_nf;
+extern cpuop_func op_4cf9_32_ff;
+extern cpuop_func op_4cfa_32_nf;
+extern cpuop_func op_4cfa_32_ff;
+extern cpuop_func op_4cfb_32_nf;
+extern cpuop_func op_4cfb_32_ff;
+extern cpuop_func op_4e40_32_nf;
+extern cpuop_func op_4e40_32_ff;
+extern cpuop_func op_4e50_32_nf;
+extern cpuop_func op_4e50_32_ff;
+extern cpuop_func op_4e58_32_nf;
+extern cpuop_func op_4e58_32_ff;
+extern cpuop_func op_4e60_32_nf;
+extern cpuop_func op_4e60_32_ff;
+extern cpuop_func op_4e68_32_nf;
+extern cpuop_func op_4e68_32_ff;
+extern cpuop_func op_4e70_32_nf;
+extern cpuop_func op_4e70_32_ff;
+extern cpuop_func op_4e71_32_nf;
+extern cpuop_func op_4e71_32_ff;
+extern cpuop_func op_4e72_32_nf;
+extern cpuop_func op_4e72_32_ff;
+extern cpuop_func op_4e73_32_nf;
+extern cpuop_func op_4e73_32_ff;
+extern cpuop_func op_4e74_32_nf;
+extern cpuop_func op_4e74_32_ff;
+extern cpuop_func op_4e75_32_nf;
+extern cpuop_func op_4e75_32_ff;
+extern cpuop_func op_4e76_32_nf;
+extern cpuop_func op_4e76_32_ff;
+extern cpuop_func op_4e77_32_nf;
+extern cpuop_func op_4e77_32_ff;
+extern cpuop_func op_4e7a_32_nf;
+extern cpuop_func op_4e7a_32_ff;
+extern cpuop_func op_4e7b_32_nf;
+extern cpuop_func op_4e7b_32_ff;
+extern cpuop_func op_4e90_32_nf;
+extern cpuop_func op_4e90_32_ff;
+extern cpuop_func op_4ea8_32_nf;
+extern cpuop_func op_4ea8_32_ff;
+extern cpuop_func op_4eb0_32_nf;
+extern cpuop_func op_4eb0_32_ff;
+extern cpuop_func op_4eb8_32_nf;
+extern cpuop_func op_4eb8_32_ff;
+extern cpuop_func op_4eb9_32_nf;
+extern cpuop_func op_4eb9_32_ff;
+extern cpuop_func op_4eba_32_nf;
+extern cpuop_func op_4eba_32_ff;
+extern cpuop_func op_4ebb_32_nf;
+extern cpuop_func op_4ebb_32_ff;
+extern cpuop_func op_4ed0_32_nf;
+extern cpuop_func op_4ed0_32_ff;
+extern cpuop_func op_4ee8_32_nf;
+extern cpuop_func op_4ee8_32_ff;
+extern cpuop_func op_4ef0_32_nf;
+extern cpuop_func op_4ef0_32_ff;
+extern cpuop_func op_4ef8_32_nf;
+extern cpuop_func op_4ef8_32_ff;
+extern cpuop_func op_4ef9_32_nf;
+extern cpuop_func op_4ef9_32_ff;
+extern cpuop_func op_4efa_32_nf;
+extern cpuop_func op_4efa_32_ff;
+extern cpuop_func op_4efb_32_nf;
+extern cpuop_func op_4efb_32_ff;
+extern cpuop_func op_5000_32_nf;
+extern cpuop_func op_5000_32_ff;
+extern cpuop_func op_5010_32_nf;
+extern cpuop_func op_5010_32_ff;
+extern cpuop_func op_5018_32_nf;
+extern cpuop_func op_5018_32_ff;
+extern cpuop_func op_5020_32_nf;
+extern cpuop_func op_5020_32_ff;
+extern cpuop_func op_5028_32_nf;
+extern cpuop_func op_5028_32_ff;
+extern cpuop_func op_5030_32_nf;
+extern cpuop_func op_5030_32_ff;
+extern cpuop_func op_5038_32_nf;
+extern cpuop_func op_5038_32_ff;
+extern cpuop_func op_5039_32_nf;
+extern cpuop_func op_5039_32_ff;
+extern cpuop_func op_5040_32_nf;
+extern cpuop_func op_5040_32_ff;
+extern cpuop_func op_5048_32_nf;
+extern cpuop_func op_5048_32_ff;
+extern cpuop_func op_5050_32_nf;
+extern cpuop_func op_5050_32_ff;
+extern cpuop_func op_5058_32_nf;
+extern cpuop_func op_5058_32_ff;
+extern cpuop_func op_5060_32_nf;
+extern cpuop_func op_5060_32_ff;
+extern cpuop_func op_5068_32_nf;
+extern cpuop_func op_5068_32_ff;
+extern cpuop_func op_5070_32_nf;
+extern cpuop_func op_5070_32_ff;
+extern cpuop_func op_5078_32_nf;
+extern cpuop_func op_5078_32_ff;
+extern cpuop_func op_5079_32_nf;
+extern cpuop_func op_5079_32_ff;
+extern cpuop_func op_5080_32_nf;
+extern cpuop_func op_5080_32_ff;
+extern cpuop_func op_5088_32_nf;
+extern cpuop_func op_5088_32_ff;
+extern cpuop_func op_5090_32_nf;
+extern cpuop_func op_5090_32_ff;
+extern cpuop_func op_5098_32_nf;
+extern cpuop_func op_5098_32_ff;
+extern cpuop_func op_50a0_32_nf;
+extern cpuop_func op_50a0_32_ff;
+extern cpuop_func op_50a8_32_nf;
+extern cpuop_func op_50a8_32_ff;
+extern cpuop_func op_50b0_32_nf;
+extern cpuop_func op_50b0_32_ff;
+extern cpuop_func op_50b8_32_nf;
+extern cpuop_func op_50b8_32_ff;
+extern cpuop_func op_50b9_32_nf;
+extern cpuop_func op_50b9_32_ff;
+extern cpuop_func op_50c0_32_nf;
+extern cpuop_func op_50c0_32_ff;
+extern cpuop_func op_50c8_32_nf;
+extern cpuop_func op_50c8_32_ff;
+extern cpuop_func op_50d0_32_nf;
+extern cpuop_func op_50d0_32_ff;
+extern cpuop_func op_50d8_32_nf;
+extern cpuop_func op_50d8_32_ff;
+extern cpuop_func op_50e0_32_nf;
+extern cpuop_func op_50e0_32_ff;
+extern cpuop_func op_50e8_32_nf;
+extern cpuop_func op_50e8_32_ff;
+extern cpuop_func op_50f0_32_nf;
+extern cpuop_func op_50f0_32_ff;
+extern cpuop_func op_50f8_32_nf;
+extern cpuop_func op_50f8_32_ff;
+extern cpuop_func op_50f9_32_nf;
+extern cpuop_func op_50f9_32_ff;
+extern cpuop_func op_50fa_32_nf;
+extern cpuop_func op_50fa_32_ff;
+extern cpuop_func op_50fb_32_nf;
+extern cpuop_func op_50fb_32_ff;
+extern cpuop_func op_50fc_32_nf;
+extern cpuop_func op_50fc_32_ff;
+extern cpuop_func op_5100_32_nf;
+extern cpuop_func op_5100_32_ff;
+extern cpuop_func op_5110_32_nf;
+extern cpuop_func op_5110_32_ff;
+extern cpuop_func op_5118_32_nf;
+extern cpuop_func op_5118_32_ff;
+extern cpuop_func op_5120_32_nf;
+extern cpuop_func op_5120_32_ff;
+extern cpuop_func op_5128_32_nf;
+extern cpuop_func op_5128_32_ff;
+extern cpuop_func op_5130_32_nf;
+extern cpuop_func op_5130_32_ff;
+extern cpuop_func op_5138_32_nf;
+extern cpuop_func op_5138_32_ff;
+extern cpuop_func op_5139_32_nf;
+extern cpuop_func op_5139_32_ff;
+extern cpuop_func op_5140_32_nf;
+extern cpuop_func op_5140_32_ff;
+extern cpuop_func op_5148_32_nf;
+extern cpuop_func op_5148_32_ff;
+extern cpuop_func op_5150_32_nf;
+extern cpuop_func op_5150_32_ff;
+extern cpuop_func op_5158_32_nf;
+extern cpuop_func op_5158_32_ff;
+extern cpuop_func op_5160_32_nf;
+extern cpuop_func op_5160_32_ff;
+extern cpuop_func op_5168_32_nf;
+extern cpuop_func op_5168_32_ff;
+extern cpuop_func op_5170_32_nf;
+extern cpuop_func op_5170_32_ff;
+extern cpuop_func op_5178_32_nf;
+extern cpuop_func op_5178_32_ff;
+extern cpuop_func op_5179_32_nf;
+extern cpuop_func op_5179_32_ff;
+extern cpuop_func op_5180_32_nf;
+extern cpuop_func op_5180_32_ff;
+extern cpuop_func op_5188_32_nf;
+extern cpuop_func op_5188_32_ff;
+extern cpuop_func op_5190_32_nf;
+extern cpuop_func op_5190_32_ff;
+extern cpuop_func op_5198_32_nf;
+extern cpuop_func op_5198_32_ff;
+extern cpuop_func op_51a0_32_nf;
+extern cpuop_func op_51a0_32_ff;
+extern cpuop_func op_51a8_32_nf;
+extern cpuop_func op_51a8_32_ff;
+extern cpuop_func op_51b0_32_nf;
+extern cpuop_func op_51b0_32_ff;
+extern cpuop_func op_51b8_32_nf;
+extern cpuop_func op_51b8_32_ff;
+extern cpuop_func op_51b9_32_nf;
+extern cpuop_func op_51b9_32_ff;
+extern cpuop_func op_51c0_32_nf;
+extern cpuop_func op_51c0_32_ff;
+extern cpuop_func op_51c8_32_nf;
+extern cpuop_func op_51c8_32_ff;
+extern cpuop_func op_51d0_32_nf;
+extern cpuop_func op_51d0_32_ff;
+extern cpuop_func op_51d8_32_nf;
+extern cpuop_func op_51d8_32_ff;
+extern cpuop_func op_51e0_32_nf;
+extern cpuop_func op_51e0_32_ff;
+extern cpuop_func op_51e8_32_nf;
+extern cpuop_func op_51e8_32_ff;
+extern cpuop_func op_51f0_32_nf;
+extern cpuop_func op_51f0_32_ff;
+extern cpuop_func op_51f8_32_nf;
+extern cpuop_func op_51f8_32_ff;
+extern cpuop_func op_51f9_32_nf;
+extern cpuop_func op_51f9_32_ff;
+extern cpuop_func op_51fa_32_nf;
+extern cpuop_func op_51fa_32_ff;
+extern cpuop_func op_51fb_32_nf;
+extern cpuop_func op_51fb_32_ff;
+extern cpuop_func op_51fc_32_nf;
+extern cpuop_func op_51fc_32_ff;
+extern cpuop_func op_52c0_32_nf;
+extern cpuop_func op_52c0_32_ff;
+extern cpuop_func op_52c8_32_nf;
+extern cpuop_func op_52c8_32_ff;
+extern cpuop_func op_52d0_32_nf;
+extern cpuop_func op_52d0_32_ff;
+extern cpuop_func op_52d8_32_nf;
+extern cpuop_func op_52d8_32_ff;
+extern cpuop_func op_52e0_32_nf;
+extern cpuop_func op_52e0_32_ff;
+extern cpuop_func op_52e8_32_nf;
+extern cpuop_func op_52e8_32_ff;
+extern cpuop_func op_52f0_32_nf;
+extern cpuop_func op_52f0_32_ff;
+extern cpuop_func op_52f8_32_nf;
+extern cpuop_func op_52f8_32_ff;
+extern cpuop_func op_52f9_32_nf;
+extern cpuop_func op_52f9_32_ff;
+extern cpuop_func op_52fa_32_nf;
+extern cpuop_func op_52fa_32_ff;
+extern cpuop_func op_52fb_32_nf;
+extern cpuop_func op_52fb_32_ff;
+extern cpuop_func op_52fc_32_nf;
+extern cpuop_func op_52fc_32_ff;
+extern cpuop_func op_53c0_32_nf;
+extern cpuop_func op_53c0_32_ff;
+extern cpuop_func op_53c8_32_nf;
+extern cpuop_func op_53c8_32_ff;
+extern cpuop_func op_53d0_32_nf;
+extern cpuop_func op_53d0_32_ff;
+extern cpuop_func op_53d8_32_nf;
+extern cpuop_func op_53d8_32_ff;
+extern cpuop_func op_53e0_32_nf;
+extern cpuop_func op_53e0_32_ff;
+extern cpuop_func op_53e8_32_nf;
+extern cpuop_func op_53e8_32_ff;
+extern cpuop_func op_53f0_32_nf;
+extern cpuop_func op_53f0_32_ff;
+extern cpuop_func op_53f8_32_nf;
+extern cpuop_func op_53f8_32_ff;
+extern cpuop_func op_53f9_32_nf;
+extern cpuop_func op_53f9_32_ff;
+extern cpuop_func op_53fa_32_nf;
+extern cpuop_func op_53fa_32_ff;
+extern cpuop_func op_53fb_32_nf;
+extern cpuop_func op_53fb_32_ff;
+extern cpuop_func op_53fc_32_nf;
+extern cpuop_func op_53fc_32_ff;
+extern cpuop_func op_54c0_32_nf;
+extern cpuop_func op_54c0_32_ff;
+extern cpuop_func op_54c8_32_nf;
+extern cpuop_func op_54c8_32_ff;
+extern cpuop_func op_54d0_32_nf;
+extern cpuop_func op_54d0_32_ff;
+extern cpuop_func op_54d8_32_nf;
+extern cpuop_func op_54d8_32_ff;
+extern cpuop_func op_54e0_32_nf;
+extern cpuop_func op_54e0_32_ff;
+extern cpuop_func op_54e8_32_nf;
+extern cpuop_func op_54e8_32_ff;
+extern cpuop_func op_54f0_32_nf;
+extern cpuop_func op_54f0_32_ff;
+extern cpuop_func op_54f8_32_nf;
+extern cpuop_func op_54f8_32_ff;
+extern cpuop_func op_54f9_32_nf;
+extern cpuop_func op_54f9_32_ff;
+extern cpuop_func op_54fa_32_nf;
+extern cpuop_func op_54fa_32_ff;
+extern cpuop_func op_54fb_32_nf;
+extern cpuop_func op_54fb_32_ff;
+extern cpuop_func op_54fc_32_nf;
+extern cpuop_func op_54fc_32_ff;
+extern cpuop_func op_55c0_32_nf;
+extern cpuop_func op_55c0_32_ff;
+extern cpuop_func op_55c8_32_nf;
+extern cpuop_func op_55c8_32_ff;
+extern cpuop_func op_55d0_32_nf;
+extern cpuop_func op_55d0_32_ff;
+extern cpuop_func op_55d8_32_nf;
+extern cpuop_func op_55d8_32_ff;
+extern cpuop_func op_55e0_32_nf;
+extern cpuop_func op_55e0_32_ff;
+extern cpuop_func op_55e8_32_nf;
+extern cpuop_func op_55e8_32_ff;
+extern cpuop_func op_55f0_32_nf;
+extern cpuop_func op_55f0_32_ff;
+extern cpuop_func op_55f8_32_nf;
+extern cpuop_func op_55f8_32_ff;
+extern cpuop_func op_55f9_32_nf;
+extern cpuop_func op_55f9_32_ff;
+extern cpuop_func op_55fa_32_nf;
+extern cpuop_func op_55fa_32_ff;
+extern cpuop_func op_55fb_32_nf;
+extern cpuop_func op_55fb_32_ff;
+extern cpuop_func op_55fc_32_nf;
+extern cpuop_func op_55fc_32_ff;
+extern cpuop_func op_56c0_32_nf;
+extern cpuop_func op_56c0_32_ff;
+extern cpuop_func op_56c8_32_nf;
+extern cpuop_func op_56c8_32_ff;
+extern cpuop_func op_56d0_32_nf;
+extern cpuop_func op_56d0_32_ff;
+extern cpuop_func op_56d8_32_nf;
+extern cpuop_func op_56d8_32_ff;
+extern cpuop_func op_56e0_32_nf;
+extern cpuop_func op_56e0_32_ff;
+extern cpuop_func op_56e8_32_nf;
+extern cpuop_func op_56e8_32_ff;
+extern cpuop_func op_56f0_32_nf;
+extern cpuop_func op_56f0_32_ff;
+extern cpuop_func op_56f8_32_nf;
+extern cpuop_func op_56f8_32_ff;
+extern cpuop_func op_56f9_32_nf;
+extern cpuop_func op_56f9_32_ff;
+extern cpuop_func op_56fa_32_nf;
+extern cpuop_func op_56fa_32_ff;
+extern cpuop_func op_56fb_32_nf;
+extern cpuop_func op_56fb_32_ff;
+extern cpuop_func op_56fc_32_nf;
+extern cpuop_func op_56fc_32_ff;
+extern cpuop_func op_57c0_32_nf;
+extern cpuop_func op_57c0_32_ff;
+extern cpuop_func op_57c8_32_nf;
+extern cpuop_func op_57c8_32_ff;
+extern cpuop_func op_57d0_32_nf;
+extern cpuop_func op_57d0_32_ff;
+extern cpuop_func op_57d8_32_nf;
+extern cpuop_func op_57d8_32_ff;
+extern cpuop_func op_57e0_32_nf;
+extern cpuop_func op_57e0_32_ff;
+extern cpuop_func op_57e8_32_nf;
+extern cpuop_func op_57e8_32_ff;
+extern cpuop_func op_57f0_32_nf;
+extern cpuop_func op_57f0_32_ff;
+extern cpuop_func op_57f8_32_nf;
+extern cpuop_func op_57f8_32_ff;
+extern cpuop_func op_57f9_32_nf;
+extern cpuop_func op_57f9_32_ff;
+extern cpuop_func op_57fa_32_nf;
+extern cpuop_func op_57fa_32_ff;
+extern cpuop_func op_57fb_32_nf;
+extern cpuop_func op_57fb_32_ff;
+extern cpuop_func op_57fc_32_nf;
+extern cpuop_func op_57fc_32_ff;
+extern cpuop_func op_58c0_32_nf;
+extern cpuop_func op_58c0_32_ff;
+extern cpuop_func op_58c8_32_nf;
+extern cpuop_func op_58c8_32_ff;
+extern cpuop_func op_58d0_32_nf;
+extern cpuop_func op_58d0_32_ff;
+extern cpuop_func op_58d8_32_nf;
+extern cpuop_func op_58d8_32_ff;
+extern cpuop_func op_58e0_32_nf;
+extern cpuop_func op_58e0_32_ff;
+extern cpuop_func op_58e8_32_nf;
+extern cpuop_func op_58e8_32_ff;
+extern cpuop_func op_58f0_32_nf;
+extern cpuop_func op_58f0_32_ff;
+extern cpuop_func op_58f8_32_nf;
+extern cpuop_func op_58f8_32_ff;
+extern cpuop_func op_58f9_32_nf;
+extern cpuop_func op_58f9_32_ff;
+extern cpuop_func op_58fa_32_nf;
+extern cpuop_func op_58fa_32_ff;
+extern cpuop_func op_58fb_32_nf;
+extern cpuop_func op_58fb_32_ff;
+extern cpuop_func op_58fc_32_nf;
+extern cpuop_func op_58fc_32_ff;
+extern cpuop_func op_59c0_32_nf;
+extern cpuop_func op_59c0_32_ff;
+extern cpuop_func op_59c8_32_nf;
+extern cpuop_func op_59c8_32_ff;
+extern cpuop_func op_59d0_32_nf;
+extern cpuop_func op_59d0_32_ff;
+extern cpuop_func op_59d8_32_nf;
+extern cpuop_func op_59d8_32_ff;
+extern cpuop_func op_59e0_32_nf;
+extern cpuop_func op_59e0_32_ff;
+extern cpuop_func op_59e8_32_nf;
+extern cpuop_func op_59e8_32_ff;
+extern cpuop_func op_59f0_32_nf;
+extern cpuop_func op_59f0_32_ff;
+extern cpuop_func op_59f8_32_nf;
+extern cpuop_func op_59f8_32_ff;
+extern cpuop_func op_59f9_32_nf;
+extern cpuop_func op_59f9_32_ff;
+extern cpuop_func op_59fa_32_nf;
+extern cpuop_func op_59fa_32_ff;
+extern cpuop_func op_59fb_32_nf;
+extern cpuop_func op_59fb_32_ff;
+extern cpuop_func op_59fc_32_nf;
+extern cpuop_func op_59fc_32_ff;
+extern cpuop_func op_5ac0_32_nf;
+extern cpuop_func op_5ac0_32_ff;
+extern cpuop_func op_5ac8_32_nf;
+extern cpuop_func op_5ac8_32_ff;
+extern cpuop_func op_5ad0_32_nf;
+extern cpuop_func op_5ad0_32_ff;
+extern cpuop_func op_5ad8_32_nf;
+extern cpuop_func op_5ad8_32_ff;
+extern cpuop_func op_5ae0_32_nf;
+extern cpuop_func op_5ae0_32_ff;
+extern cpuop_func op_5ae8_32_nf;
+extern cpuop_func op_5ae8_32_ff;
+extern cpuop_func op_5af0_32_nf;
+extern cpuop_func op_5af0_32_ff;
+extern cpuop_func op_5af8_32_nf;
+extern cpuop_func op_5af8_32_ff;
+extern cpuop_func op_5af9_32_nf;
+extern cpuop_func op_5af9_32_ff;
+extern cpuop_func op_5afa_32_nf;
+extern cpuop_func op_5afa_32_ff;
+extern cpuop_func op_5afb_32_nf;
+extern cpuop_func op_5afb_32_ff;
+extern cpuop_func op_5afc_32_nf;
+extern cpuop_func op_5afc_32_ff;
+extern cpuop_func op_5bc0_32_nf;
+extern cpuop_func op_5bc0_32_ff;
+extern cpuop_func op_5bc8_32_nf;
+extern cpuop_func op_5bc8_32_ff;
+extern cpuop_func op_5bd0_32_nf;
+extern cpuop_func op_5bd0_32_ff;
+extern cpuop_func op_5bd8_32_nf;
+extern cpuop_func op_5bd8_32_ff;
+extern cpuop_func op_5be0_32_nf;
+extern cpuop_func op_5be0_32_ff;
+extern cpuop_func op_5be8_32_nf;
+extern cpuop_func op_5be8_32_ff;
+extern cpuop_func op_5bf0_32_nf;
+extern cpuop_func op_5bf0_32_ff;
+extern cpuop_func op_5bf8_32_nf;
+extern cpuop_func op_5bf8_32_ff;
+extern cpuop_func op_5bf9_32_nf;
+extern cpuop_func op_5bf9_32_ff;
+extern cpuop_func op_5bfa_32_nf;
+extern cpuop_func op_5bfa_32_ff;
+extern cpuop_func op_5bfb_32_nf;
+extern cpuop_func op_5bfb_32_ff;
+extern cpuop_func op_5bfc_32_nf;
+extern cpuop_func op_5bfc_32_ff;
+extern cpuop_func op_5cc0_32_nf;
+extern cpuop_func op_5cc0_32_ff;
+extern cpuop_func op_5cc8_32_nf;
+extern cpuop_func op_5cc8_32_ff;
+extern cpuop_func op_5cd0_32_nf;
+extern cpuop_func op_5cd0_32_ff;
+extern cpuop_func op_5cd8_32_nf;
+extern cpuop_func op_5cd8_32_ff;
+extern cpuop_func op_5ce0_32_nf;
+extern cpuop_func op_5ce0_32_ff;
+extern cpuop_func op_5ce8_32_nf;
+extern cpuop_func op_5ce8_32_ff;
+extern cpuop_func op_5cf0_32_nf;
+extern cpuop_func op_5cf0_32_ff;
+extern cpuop_func op_5cf8_32_nf;
+extern cpuop_func op_5cf8_32_ff;
+extern cpuop_func op_5cf9_32_nf;
+extern cpuop_func op_5cf9_32_ff;
+extern cpuop_func op_5cfa_32_nf;
+extern cpuop_func op_5cfa_32_ff;
+extern cpuop_func op_5cfb_32_nf;
+extern cpuop_func op_5cfb_32_ff;
+extern cpuop_func op_5cfc_32_nf;
+extern cpuop_func op_5cfc_32_ff;
+extern cpuop_func op_5dc0_32_nf;
+extern cpuop_func op_5dc0_32_ff;
+extern cpuop_func op_5dc8_32_nf;
+extern cpuop_func op_5dc8_32_ff;
+extern cpuop_func op_5dd0_32_nf;
+extern cpuop_func op_5dd0_32_ff;
+extern cpuop_func op_5dd8_32_nf;
+extern cpuop_func op_5dd8_32_ff;
+extern cpuop_func op_5de0_32_nf;
+extern cpuop_func op_5de0_32_ff;
+extern cpuop_func op_5de8_32_nf;
+extern cpuop_func op_5de8_32_ff;
+extern cpuop_func op_5df0_32_nf;
+extern cpuop_func op_5df0_32_ff;
+extern cpuop_func op_5df8_32_nf;
+extern cpuop_func op_5df8_32_ff;
+extern cpuop_func op_5df9_32_nf;
+extern cpuop_func op_5df9_32_ff;
+extern cpuop_func op_5dfa_32_nf;
+extern cpuop_func op_5dfa_32_ff;
+extern cpuop_func op_5dfb_32_nf;
+extern cpuop_func op_5dfb_32_ff;
+extern cpuop_func op_5dfc_32_nf;
+extern cpuop_func op_5dfc_32_ff;
+extern cpuop_func op_5ec0_32_nf;
+extern cpuop_func op_5ec0_32_ff;
+extern cpuop_func op_5ec8_32_nf;
+extern cpuop_func op_5ec8_32_ff;
+extern cpuop_func op_5ed0_32_nf;
+extern cpuop_func op_5ed0_32_ff;
+extern cpuop_func op_5ed8_32_nf;
+extern cpuop_func op_5ed8_32_ff;
+extern cpuop_func op_5ee0_32_nf;
+extern cpuop_func op_5ee0_32_ff;
+extern cpuop_func op_5ee8_32_nf;
+extern cpuop_func op_5ee8_32_ff;
+extern cpuop_func op_5ef0_32_nf;
+extern cpuop_func op_5ef0_32_ff;
+extern cpuop_func op_5ef8_32_nf;
+extern cpuop_func op_5ef8_32_ff;
+extern cpuop_func op_5ef9_32_nf;
+extern cpuop_func op_5ef9_32_ff;
+extern cpuop_func op_5efa_32_nf;
+extern cpuop_func op_5efa_32_ff;
+extern cpuop_func op_5efb_32_nf;
+extern cpuop_func op_5efb_32_ff;
+extern cpuop_func op_5efc_32_nf;
+extern cpuop_func op_5efc_32_ff;
+extern cpuop_func op_5fc0_32_nf;
+extern cpuop_func op_5fc0_32_ff;
+extern cpuop_func op_5fc8_32_nf;
+extern cpuop_func op_5fc8_32_ff;
+extern cpuop_func op_5fd0_32_nf;
+extern cpuop_func op_5fd0_32_ff;
+extern cpuop_func op_5fd8_32_nf;
+extern cpuop_func op_5fd8_32_ff;
+extern cpuop_func op_5fe0_32_nf;
+extern cpuop_func op_5fe0_32_ff;
+extern cpuop_func op_5fe8_32_nf;
+extern cpuop_func op_5fe8_32_ff;
+extern cpuop_func op_5ff0_32_nf;
+extern cpuop_func op_5ff0_32_ff;
+extern cpuop_func op_5ff8_32_nf;
+extern cpuop_func op_5ff8_32_ff;
+extern cpuop_func op_5ff9_32_nf;
+extern cpuop_func op_5ff9_32_ff;
+extern cpuop_func op_5ffa_32_nf;
+extern cpuop_func op_5ffa_32_ff;
+extern cpuop_func op_5ffb_32_nf;
+extern cpuop_func op_5ffb_32_ff;
+extern cpuop_func op_5ffc_32_nf;
+extern cpuop_func op_5ffc_32_ff;
+extern cpuop_func op_6000_32_nf;
+extern cpuop_func op_6000_32_ff;
+extern cpuop_func op_6001_32_nf;
+extern cpuop_func op_6001_32_ff;
+extern cpuop_func op_60ff_32_nf;
+extern cpuop_func op_60ff_32_ff;
+extern cpuop_func op_6100_32_nf;
+extern cpuop_func op_6100_32_ff;
+extern cpuop_func op_6101_32_nf;
+extern cpuop_func op_6101_32_ff;
+extern cpuop_func op_61ff_32_nf;
+extern cpuop_func op_61ff_32_ff;
+extern cpuop_func op_6200_32_nf;
+extern cpuop_func op_6200_32_ff;
+extern cpuop_func op_6201_32_nf;
+extern cpuop_func op_6201_32_ff;
+extern cpuop_func op_62ff_32_nf;
+extern cpuop_func op_62ff_32_ff;
+extern cpuop_func op_6300_32_nf;
+extern cpuop_func op_6300_32_ff;
+extern cpuop_func op_6301_32_nf;
+extern cpuop_func op_6301_32_ff;
+extern cpuop_func op_63ff_32_nf;
+extern cpuop_func op_63ff_32_ff;
+extern cpuop_func op_6400_32_nf;
+extern cpuop_func op_6400_32_ff;
+extern cpuop_func op_6401_32_nf;
+extern cpuop_func op_6401_32_ff;
+extern cpuop_func op_64ff_32_nf;
+extern cpuop_func op_64ff_32_ff;
+extern cpuop_func op_6500_32_nf;
+extern cpuop_func op_6500_32_ff;
+extern cpuop_func op_6501_32_nf;
+extern cpuop_func op_6501_32_ff;
+extern cpuop_func op_65ff_32_nf;
+extern cpuop_func op_65ff_32_ff;
+extern cpuop_func op_6600_32_nf;
+extern cpuop_func op_6600_32_ff;
+extern cpuop_func op_6601_32_nf;
+extern cpuop_func op_6601_32_ff;
+extern cpuop_func op_66ff_32_nf;
+extern cpuop_func op_66ff_32_ff;
+extern cpuop_func op_6700_32_nf;
+extern cpuop_func op_6700_32_ff;
+extern cpuop_func op_6701_32_nf;
+extern cpuop_func op_6701_32_ff;
+extern cpuop_func op_67ff_32_nf;
+extern cpuop_func op_67ff_32_ff;
+extern cpuop_func op_6800_32_nf;
+extern cpuop_func op_6800_32_ff;
+extern cpuop_func op_6801_32_nf;
+extern cpuop_func op_6801_32_ff;
+extern cpuop_func op_68ff_32_nf;
+extern cpuop_func op_68ff_32_ff;
+extern cpuop_func op_6900_32_nf;
+extern cpuop_func op_6900_32_ff;
+extern cpuop_func op_6901_32_nf;
+extern cpuop_func op_6901_32_ff;
+extern cpuop_func op_69ff_32_nf;
+extern cpuop_func op_69ff_32_ff;
+extern cpuop_func op_6a00_32_nf;
+extern cpuop_func op_6a00_32_ff;
+extern cpuop_func op_6a01_32_nf;
+extern cpuop_func op_6a01_32_ff;
+extern cpuop_func op_6aff_32_nf;
+extern cpuop_func op_6aff_32_ff;
+extern cpuop_func op_6b00_32_nf;
+extern cpuop_func op_6b00_32_ff;
+extern cpuop_func op_6b01_32_nf;
+extern cpuop_func op_6b01_32_ff;
+extern cpuop_func op_6bff_32_nf;
+extern cpuop_func op_6bff_32_ff;
+extern cpuop_func op_6c00_32_nf;
+extern cpuop_func op_6c00_32_ff;
+extern cpuop_func op_6c01_32_nf;
+extern cpuop_func op_6c01_32_ff;
+extern cpuop_func op_6cff_32_nf;
+extern cpuop_func op_6cff_32_ff;
+extern cpuop_func op_6d00_32_nf;
+extern cpuop_func op_6d00_32_ff;
+extern cpuop_func op_6d01_32_nf;
+extern cpuop_func op_6d01_32_ff;
+extern cpuop_func op_6dff_32_nf;
+extern cpuop_func op_6dff_32_ff;
+extern cpuop_func op_6e00_32_nf;
+extern cpuop_func op_6e00_32_ff;
+extern cpuop_func op_6e01_32_nf;
+extern cpuop_func op_6e01_32_ff;
+extern cpuop_func op_6eff_32_nf;
+extern cpuop_func op_6eff_32_ff;
+extern cpuop_func op_6f00_32_nf;
+extern cpuop_func op_6f00_32_ff;
+extern cpuop_func op_6f01_32_nf;
+extern cpuop_func op_6f01_32_ff;
+extern cpuop_func op_6fff_32_nf;
+extern cpuop_func op_6fff_32_ff;
+extern cpuop_func op_7000_32_nf;
+extern cpuop_func op_7000_32_ff;
+extern cpuop_func op_8000_32_nf;
+extern cpuop_func op_8000_32_ff;
+extern cpuop_func op_8010_32_nf;
+extern cpuop_func op_8010_32_ff;
+extern cpuop_func op_8018_32_nf;
+extern cpuop_func op_8018_32_ff;
+extern cpuop_func op_8020_32_nf;
+extern cpuop_func op_8020_32_ff;
+extern cpuop_func op_8028_32_nf;
+extern cpuop_func op_8028_32_ff;
+extern cpuop_func op_8030_32_nf;
+extern cpuop_func op_8030_32_ff;
+extern cpuop_func op_8038_32_nf;
+extern cpuop_func op_8038_32_ff;
+extern cpuop_func op_8039_32_nf;
+extern cpuop_func op_8039_32_ff;
+extern cpuop_func op_803a_32_nf;
+extern cpuop_func op_803a_32_ff;
+extern cpuop_func op_803b_32_nf;
+extern cpuop_func op_803b_32_ff;
+extern cpuop_func op_803c_32_nf;
+extern cpuop_func op_803c_32_ff;
+extern cpuop_func op_8040_32_nf;
+extern cpuop_func op_8040_32_ff;
+extern cpuop_func op_8050_32_nf;
+extern cpuop_func op_8050_32_ff;
+extern cpuop_func op_8058_32_nf;
+extern cpuop_func op_8058_32_ff;
+extern cpuop_func op_8060_32_nf;
+extern cpuop_func op_8060_32_ff;
+extern cpuop_func op_8068_32_nf;
+extern cpuop_func op_8068_32_ff;
+extern cpuop_func op_8070_32_nf;
+extern cpuop_func op_8070_32_ff;
+extern cpuop_func op_8078_32_nf;
+extern cpuop_func op_8078_32_ff;
+extern cpuop_func op_8079_32_nf;
+extern cpuop_func op_8079_32_ff;
+extern cpuop_func op_807a_32_nf;
+extern cpuop_func op_807a_32_ff;
+extern cpuop_func op_807b_32_nf;
+extern cpuop_func op_807b_32_ff;
+extern cpuop_func op_807c_32_nf;
+extern cpuop_func op_807c_32_ff;
+extern cpuop_func op_8080_32_nf;
+extern cpuop_func op_8080_32_ff;
+extern cpuop_func op_8090_32_nf;
+extern cpuop_func op_8090_32_ff;
+extern cpuop_func op_8098_32_nf;
+extern cpuop_func op_8098_32_ff;
+extern cpuop_func op_80a0_32_nf;
+extern cpuop_func op_80a0_32_ff;
+extern cpuop_func op_80a8_32_nf;
+extern cpuop_func op_80a8_32_ff;
+extern cpuop_func op_80b0_32_nf;
+extern cpuop_func op_80b0_32_ff;
+extern cpuop_func op_80b8_32_nf;
+extern cpuop_func op_80b8_32_ff;
+extern cpuop_func op_80b9_32_nf;
+extern cpuop_func op_80b9_32_ff;
+extern cpuop_func op_80ba_32_nf;
+extern cpuop_func op_80ba_32_ff;
+extern cpuop_func op_80bb_32_nf;
+extern cpuop_func op_80bb_32_ff;
+extern cpuop_func op_80bc_32_nf;
+extern cpuop_func op_80bc_32_ff;
+extern cpuop_func op_80c0_32_nf;
+extern cpuop_func op_80c0_32_ff;
+extern cpuop_func op_80d0_32_nf;
+extern cpuop_func op_80d0_32_ff;
+extern cpuop_func op_80d8_32_nf;
+extern cpuop_func op_80d8_32_ff;
+extern cpuop_func op_80e0_32_nf;
+extern cpuop_func op_80e0_32_ff;
+extern cpuop_func op_80e8_32_nf;
+extern cpuop_func op_80e8_32_ff;
+extern cpuop_func op_80f0_32_nf;
+extern cpuop_func op_80f0_32_ff;
+extern cpuop_func op_80f8_32_nf;
+extern cpuop_func op_80f8_32_ff;
+extern cpuop_func op_80f9_32_nf;
+extern cpuop_func op_80f9_32_ff;
+extern cpuop_func op_80fa_32_nf;
+extern cpuop_func op_80fa_32_ff;
+extern cpuop_func op_80fb_32_nf;
+extern cpuop_func op_80fb_32_ff;
+extern cpuop_func op_80fc_32_nf;
+extern cpuop_func op_80fc_32_ff;
+extern cpuop_func op_8100_32_nf;
+extern cpuop_func op_8100_32_ff;
+extern cpuop_func op_8108_32_nf;
+extern cpuop_func op_8108_32_ff;
+extern cpuop_func op_8110_32_nf;
+extern cpuop_func op_8110_32_ff;
+extern cpuop_func op_8118_32_nf;
+extern cpuop_func op_8118_32_ff;
+extern cpuop_func op_8120_32_nf;
+extern cpuop_func op_8120_32_ff;
+extern cpuop_func op_8128_32_nf;
+extern cpuop_func op_8128_32_ff;
+extern cpuop_func op_8130_32_nf;
+extern cpuop_func op_8130_32_ff;
+extern cpuop_func op_8138_32_nf;
+extern cpuop_func op_8138_32_ff;
+extern cpuop_func op_8139_32_nf;
+extern cpuop_func op_8139_32_ff;
+extern cpuop_func op_8140_32_nf;
+extern cpuop_func op_8140_32_ff;
+extern cpuop_func op_8148_32_nf;
+extern cpuop_func op_8148_32_ff;
+extern cpuop_func op_8150_32_nf;
+extern cpuop_func op_8150_32_ff;
+extern cpuop_func op_8158_32_nf;
+extern cpuop_func op_8158_32_ff;
+extern cpuop_func op_8160_32_nf;
+extern cpuop_func op_8160_32_ff;
+extern cpuop_func op_8168_32_nf;
+extern cpuop_func op_8168_32_ff;
+extern cpuop_func op_8170_32_nf;
+extern cpuop_func op_8170_32_ff;
+extern cpuop_func op_8178_32_nf;
+extern cpuop_func op_8178_32_ff;
+extern cpuop_func op_8179_32_nf;
+extern cpuop_func op_8179_32_ff;
+extern cpuop_func op_8180_32_nf;
+extern cpuop_func op_8180_32_ff;
+extern cpuop_func op_8188_32_nf;
+extern cpuop_func op_8188_32_ff;
+extern cpuop_func op_8190_32_nf;
+extern cpuop_func op_8190_32_ff;
+extern cpuop_func op_8198_32_nf;
+extern cpuop_func op_8198_32_ff;
+extern cpuop_func op_81a0_32_nf;
+extern cpuop_func op_81a0_32_ff;
+extern cpuop_func op_81a8_32_nf;
+extern cpuop_func op_81a8_32_ff;
+extern cpuop_func op_81b0_32_nf;
+extern cpuop_func op_81b0_32_ff;
+extern cpuop_func op_81b8_32_nf;
+extern cpuop_func op_81b8_32_ff;
+extern cpuop_func op_81b9_32_nf;
+extern cpuop_func op_81b9_32_ff;
+extern cpuop_func op_81c0_32_nf;
+extern cpuop_func op_81c0_32_ff;
+extern cpuop_func op_81d0_32_nf;
+extern cpuop_func op_81d0_32_ff;
+extern cpuop_func op_81d8_32_nf;
+extern cpuop_func op_81d8_32_ff;
+extern cpuop_func op_81e0_32_nf;
+extern cpuop_func op_81e0_32_ff;
+extern cpuop_func op_81e8_32_nf;
+extern cpuop_func op_81e8_32_ff;
+extern cpuop_func op_81f0_32_nf;
+extern cpuop_func op_81f0_32_ff;
+extern cpuop_func op_81f8_32_nf;
+extern cpuop_func op_81f8_32_ff;
+extern cpuop_func op_81f9_32_nf;
+extern cpuop_func op_81f9_32_ff;
+extern cpuop_func op_81fa_32_nf;
+extern cpuop_func op_81fa_32_ff;
+extern cpuop_func op_81fb_32_nf;
+extern cpuop_func op_81fb_32_ff;
+extern cpuop_func op_81fc_32_nf;
+extern cpuop_func op_81fc_32_ff;
+extern cpuop_func op_9000_32_nf;
+extern cpuop_func op_9000_32_ff;
+extern cpuop_func op_9010_32_nf;
+extern cpuop_func op_9010_32_ff;
+extern cpuop_func op_9018_32_nf;
+extern cpuop_func op_9018_32_ff;
+extern cpuop_func op_9020_32_nf;
+extern cpuop_func op_9020_32_ff;
+extern cpuop_func op_9028_32_nf;
+extern cpuop_func op_9028_32_ff;
+extern cpuop_func op_9030_32_nf;
+extern cpuop_func op_9030_32_ff;
+extern cpuop_func op_9038_32_nf;
+extern cpuop_func op_9038_32_ff;
+extern cpuop_func op_9039_32_nf;
+extern cpuop_func op_9039_32_ff;
+extern cpuop_func op_903a_32_nf;
+extern cpuop_func op_903a_32_ff;
+extern cpuop_func op_903b_32_nf;
+extern cpuop_func op_903b_32_ff;
+extern cpuop_func op_903c_32_nf;
+extern cpuop_func op_903c_32_ff;
+extern cpuop_func op_9040_32_nf;
+extern cpuop_func op_9040_32_ff;
+extern cpuop_func op_9048_32_nf;
+extern cpuop_func op_9048_32_ff;
+extern cpuop_func op_9050_32_nf;
+extern cpuop_func op_9050_32_ff;
+extern cpuop_func op_9058_32_nf;
+extern cpuop_func op_9058_32_ff;
+extern cpuop_func op_9060_32_nf;
+extern cpuop_func op_9060_32_ff;
+extern cpuop_func op_9068_32_nf;
+extern cpuop_func op_9068_32_ff;
+extern cpuop_func op_9070_32_nf;
+extern cpuop_func op_9070_32_ff;
+extern cpuop_func op_9078_32_nf;
+extern cpuop_func op_9078_32_ff;
+extern cpuop_func op_9079_32_nf;
+extern cpuop_func op_9079_32_ff;
+extern cpuop_func op_907a_32_nf;
+extern cpuop_func op_907a_32_ff;
+extern cpuop_func op_907b_32_nf;
+extern cpuop_func op_907b_32_ff;
+extern cpuop_func op_907c_32_nf;
+extern cpuop_func op_907c_32_ff;
+extern cpuop_func op_9080_32_nf;
+extern cpuop_func op_9080_32_ff;
+extern cpuop_func op_9088_32_nf;
+extern cpuop_func op_9088_32_ff;
+extern cpuop_func op_9090_32_nf;
+extern cpuop_func op_9090_32_ff;
+extern cpuop_func op_9098_32_nf;
+extern cpuop_func op_9098_32_ff;
+extern cpuop_func op_90a0_32_nf;
+extern cpuop_func op_90a0_32_ff;
+extern cpuop_func op_90a8_32_nf;
+extern cpuop_func op_90a8_32_ff;
+extern cpuop_func op_90b0_32_nf;
+extern cpuop_func op_90b0_32_ff;
+extern cpuop_func op_90b8_32_nf;
+extern cpuop_func op_90b8_32_ff;
+extern cpuop_func op_90b9_32_nf;
+extern cpuop_func op_90b9_32_ff;
+extern cpuop_func op_90ba_32_nf;
+extern cpuop_func op_90ba_32_ff;
+extern cpuop_func op_90bb_32_nf;
+extern cpuop_func op_90bb_32_ff;
+extern cpuop_func op_90bc_32_nf;
+extern cpuop_func op_90bc_32_ff;
+extern cpuop_func op_90c0_32_nf;
+extern cpuop_func op_90c0_32_ff;
+extern cpuop_func op_90c8_32_nf;
+extern cpuop_func op_90c8_32_ff;
+extern cpuop_func op_90d0_32_nf;
+extern cpuop_func op_90d0_32_ff;
+extern cpuop_func op_90d8_32_nf;
+extern cpuop_func op_90d8_32_ff;
+extern cpuop_func op_90e0_32_nf;
+extern cpuop_func op_90e0_32_ff;
+extern cpuop_func op_90e8_32_nf;
+extern cpuop_func op_90e8_32_ff;
+extern cpuop_func op_90f0_32_nf;
+extern cpuop_func op_90f0_32_ff;
+extern cpuop_func op_90f8_32_nf;
+extern cpuop_func op_90f8_32_ff;
+extern cpuop_func op_90f9_32_nf;
+extern cpuop_func op_90f9_32_ff;
+extern cpuop_func op_90fa_32_nf;
+extern cpuop_func op_90fa_32_ff;
+extern cpuop_func op_90fb_32_nf;
+extern cpuop_func op_90fb_32_ff;
+extern cpuop_func op_90fc_32_nf;
+extern cpuop_func op_90fc_32_ff;
+extern cpuop_func op_9100_32_nf;
+extern cpuop_func op_9100_32_ff;
+extern cpuop_func op_9108_32_nf;
+extern cpuop_func op_9108_32_ff;
+extern cpuop_func op_9110_32_nf;
+extern cpuop_func op_9110_32_ff;
+extern cpuop_func op_9118_32_nf;
+extern cpuop_func op_9118_32_ff;
+extern cpuop_func op_9120_32_nf;
+extern cpuop_func op_9120_32_ff;
+extern cpuop_func op_9128_32_nf;
+extern cpuop_func op_9128_32_ff;
+extern cpuop_func op_9130_32_nf;
+extern cpuop_func op_9130_32_ff;
+extern cpuop_func op_9138_32_nf;
+extern cpuop_func op_9138_32_ff;
+extern cpuop_func op_9139_32_nf;
+extern cpuop_func op_9139_32_ff;
+extern cpuop_func op_9140_32_nf;
+extern cpuop_func op_9140_32_ff;
+extern cpuop_func op_9148_32_nf;
+extern cpuop_func op_9148_32_ff;
+extern cpuop_func op_9150_32_nf;
+extern cpuop_func op_9150_32_ff;
+extern cpuop_func op_9158_32_nf;
+extern cpuop_func op_9158_32_ff;
+extern cpuop_func op_9160_32_nf;
+extern cpuop_func op_9160_32_ff;
+extern cpuop_func op_9168_32_nf;
+extern cpuop_func op_9168_32_ff;
+extern cpuop_func op_9170_32_nf;
+extern cpuop_func op_9170_32_ff;
+extern cpuop_func op_9178_32_nf;
+extern cpuop_func op_9178_32_ff;
+extern cpuop_func op_9179_32_nf;
+extern cpuop_func op_9179_32_ff;
+extern cpuop_func op_9180_32_nf;
+extern cpuop_func op_9180_32_ff;
+extern cpuop_func op_9188_32_nf;
+extern cpuop_func op_9188_32_ff;
+extern cpuop_func op_9190_32_nf;
+extern cpuop_func op_9190_32_ff;
+extern cpuop_func op_9198_32_nf;
+extern cpuop_func op_9198_32_ff;
+extern cpuop_func op_91a0_32_nf;
+extern cpuop_func op_91a0_32_ff;
+extern cpuop_func op_91a8_32_nf;
+extern cpuop_func op_91a8_32_ff;
+extern cpuop_func op_91b0_32_nf;
+extern cpuop_func op_91b0_32_ff;
+extern cpuop_func op_91b8_32_nf;
+extern cpuop_func op_91b8_32_ff;
+extern cpuop_func op_91b9_32_nf;
+extern cpuop_func op_91b9_32_ff;
+extern cpuop_func op_91c0_32_nf;
+extern cpuop_func op_91c0_32_ff;
+extern cpuop_func op_91c8_32_nf;
+extern cpuop_func op_91c8_32_ff;
+extern cpuop_func op_91d0_32_nf;
+extern cpuop_func op_91d0_32_ff;
+extern cpuop_func op_91d8_32_nf;
+extern cpuop_func op_91d8_32_ff;
+extern cpuop_func op_91e0_32_nf;
+extern cpuop_func op_91e0_32_ff;
+extern cpuop_func op_91e8_32_nf;
+extern cpuop_func op_91e8_32_ff;
+extern cpuop_func op_91f0_32_nf;
+extern cpuop_func op_91f0_32_ff;
+extern cpuop_func op_91f8_32_nf;
+extern cpuop_func op_91f8_32_ff;
+extern cpuop_func op_91f9_32_nf;
+extern cpuop_func op_91f9_32_ff;
+extern cpuop_func op_91fa_32_nf;
+extern cpuop_func op_91fa_32_ff;
+extern cpuop_func op_91fb_32_nf;
+extern cpuop_func op_91fb_32_ff;
+extern cpuop_func op_91fc_32_nf;
+extern cpuop_func op_91fc_32_ff;
+extern cpuop_func op_b000_32_nf;
+extern cpuop_func op_b000_32_ff;
+extern cpuop_func op_b010_32_nf;
+extern cpuop_func op_b010_32_ff;
+extern cpuop_func op_b018_32_nf;
+extern cpuop_func op_b018_32_ff;
+extern cpuop_func op_b020_32_nf;
+extern cpuop_func op_b020_32_ff;
+extern cpuop_func op_b028_32_nf;
+extern cpuop_func op_b028_32_ff;
+extern cpuop_func op_b030_32_nf;
+extern cpuop_func op_b030_32_ff;
+extern cpuop_func op_b038_32_nf;
+extern cpuop_func op_b038_32_ff;
+extern cpuop_func op_b039_32_nf;
+extern cpuop_func op_b039_32_ff;
+extern cpuop_func op_b03a_32_nf;
+extern cpuop_func op_b03a_32_ff;
+extern cpuop_func op_b03b_32_nf;
+extern cpuop_func op_b03b_32_ff;
+extern cpuop_func op_b03c_32_nf;
+extern cpuop_func op_b03c_32_ff;
+extern cpuop_func op_b040_32_nf;
+extern cpuop_func op_b040_32_ff;
+extern cpuop_func op_b048_32_nf;
+extern cpuop_func op_b048_32_ff;
+extern cpuop_func op_b050_32_nf;
+extern cpuop_func op_b050_32_ff;
+extern cpuop_func op_b058_32_nf;
+extern cpuop_func op_b058_32_ff;
+extern cpuop_func op_b060_32_nf;
+extern cpuop_func op_b060_32_ff;
+extern cpuop_func op_b068_32_nf;
+extern cpuop_func op_b068_32_ff;
+extern cpuop_func op_b070_32_nf;
+extern cpuop_func op_b070_32_ff;
+extern cpuop_func op_b078_32_nf;
+extern cpuop_func op_b078_32_ff;
+extern cpuop_func op_b079_32_nf;
+extern cpuop_func op_b079_32_ff;
+extern cpuop_func op_b07a_32_nf;
+extern cpuop_func op_b07a_32_ff;
+extern cpuop_func op_b07b_32_nf;
+extern cpuop_func op_b07b_32_ff;
+extern cpuop_func op_b07c_32_nf;
+extern cpuop_func op_b07c_32_ff;
+extern cpuop_func op_b080_32_nf;
+extern cpuop_func op_b080_32_ff;
+extern cpuop_func op_b088_32_nf;
+extern cpuop_func op_b088_32_ff;
+extern cpuop_func op_b090_32_nf;
+extern cpuop_func op_b090_32_ff;
+extern cpuop_func op_b098_32_nf;
+extern cpuop_func op_b098_32_ff;
+extern cpuop_func op_b0a0_32_nf;
+extern cpuop_func op_b0a0_32_ff;
+extern cpuop_func op_b0a8_32_nf;
+extern cpuop_func op_b0a8_32_ff;
+extern cpuop_func op_b0b0_32_nf;
+extern cpuop_func op_b0b0_32_ff;
+extern cpuop_func op_b0b8_32_nf;
+extern cpuop_func op_b0b8_32_ff;
+extern cpuop_func op_b0b9_32_nf;
+extern cpuop_func op_b0b9_32_ff;
+extern cpuop_func op_b0ba_32_nf;
+extern cpuop_func op_b0ba_32_ff;
+extern cpuop_func op_b0bb_32_nf;
+extern cpuop_func op_b0bb_32_ff;
+extern cpuop_func op_b0bc_32_nf;
+extern cpuop_func op_b0bc_32_ff;
+extern cpuop_func op_b0c0_32_nf;
+extern cpuop_func op_b0c0_32_ff;
+extern cpuop_func op_b0c8_32_nf;
+extern cpuop_func op_b0c8_32_ff;
+extern cpuop_func op_b0d0_32_nf;
+extern cpuop_func op_b0d0_32_ff;
+extern cpuop_func op_b0d8_32_nf;
+extern cpuop_func op_b0d8_32_ff;
+extern cpuop_func op_b0e0_32_nf;
+extern cpuop_func op_b0e0_32_ff;
+extern cpuop_func op_b0e8_32_nf;
+extern cpuop_func op_b0e8_32_ff;
+extern cpuop_func op_b0f0_32_nf;
+extern cpuop_func op_b0f0_32_ff;
+extern cpuop_func op_b0f8_32_nf;
+extern cpuop_func op_b0f8_32_ff;
+extern cpuop_func op_b0f9_32_nf;
+extern cpuop_func op_b0f9_32_ff;
+extern cpuop_func op_b0fa_32_nf;
+extern cpuop_func op_b0fa_32_ff;
+extern cpuop_func op_b0fb_32_nf;
+extern cpuop_func op_b0fb_32_ff;
+extern cpuop_func op_b0fc_32_nf;
+extern cpuop_func op_b0fc_32_ff;
+extern cpuop_func op_b100_32_nf;
+extern cpuop_func op_b100_32_ff;
+extern cpuop_func op_b108_32_nf;
+extern cpuop_func op_b108_32_ff;
+extern cpuop_func op_b110_32_nf;
+extern cpuop_func op_b110_32_ff;
+extern cpuop_func op_b118_32_nf;
+extern cpuop_func op_b118_32_ff;
+extern cpuop_func op_b120_32_nf;
+extern cpuop_func op_b120_32_ff;
+extern cpuop_func op_b128_32_nf;
+extern cpuop_func op_b128_32_ff;
+extern cpuop_func op_b130_32_nf;
+extern cpuop_func op_b130_32_ff;
+extern cpuop_func op_b138_32_nf;
+extern cpuop_func op_b138_32_ff;
+extern cpuop_func op_b139_32_nf;
+extern cpuop_func op_b139_32_ff;
+extern cpuop_func op_b140_32_nf;
+extern cpuop_func op_b140_32_ff;
+extern cpuop_func op_b148_32_nf;
+extern cpuop_func op_b148_32_ff;
+extern cpuop_func op_b150_32_nf;
+extern cpuop_func op_b150_32_ff;
+extern cpuop_func op_b158_32_nf;
+extern cpuop_func op_b158_32_ff;
+extern cpuop_func op_b160_32_nf;
+extern cpuop_func op_b160_32_ff;
+extern cpuop_func op_b168_32_nf;
+extern cpuop_func op_b168_32_ff;
+extern cpuop_func op_b170_32_nf;
+extern cpuop_func op_b170_32_ff;
+extern cpuop_func op_b178_32_nf;
+extern cpuop_func op_b178_32_ff;
+extern cpuop_func op_b179_32_nf;
+extern cpuop_func op_b179_32_ff;
+extern cpuop_func op_b180_32_nf;
+extern cpuop_func op_b180_32_ff;
+extern cpuop_func op_b188_32_nf;
+extern cpuop_func op_b188_32_ff;
+extern cpuop_func op_b190_32_nf;
+extern cpuop_func op_b190_32_ff;
+extern cpuop_func op_b198_32_nf;
+extern cpuop_func op_b198_32_ff;
+extern cpuop_func op_b1a0_32_nf;
+extern cpuop_func op_b1a0_32_ff;
+extern cpuop_func op_b1a8_32_nf;
+extern cpuop_func op_b1a8_32_ff;
+extern cpuop_func op_b1b0_32_nf;
+extern cpuop_func op_b1b0_32_ff;
+extern cpuop_func op_b1b8_32_nf;
+extern cpuop_func op_b1b8_32_ff;
+extern cpuop_func op_b1b9_32_nf;
+extern cpuop_func op_b1b9_32_ff;
+extern cpuop_func op_b1c0_32_nf;
+extern cpuop_func op_b1c0_32_ff;
+extern cpuop_func op_b1c8_32_nf;
+extern cpuop_func op_b1c8_32_ff;
+extern cpuop_func op_b1d0_32_nf;
+extern cpuop_func op_b1d0_32_ff;
+extern cpuop_func op_b1d8_32_nf;
+extern cpuop_func op_b1d8_32_ff;
+extern cpuop_func op_b1e0_32_nf;
+extern cpuop_func op_b1e0_32_ff;
+extern cpuop_func op_b1e8_32_nf;
+extern cpuop_func op_b1e8_32_ff;
+extern cpuop_func op_b1f0_32_nf;
+extern cpuop_func op_b1f0_32_ff;
+extern cpuop_func op_b1f8_32_nf;
+extern cpuop_func op_b1f8_32_ff;
+extern cpuop_func op_b1f9_32_nf;
+extern cpuop_func op_b1f9_32_ff;
+extern cpuop_func op_b1fa_32_nf;
+extern cpuop_func op_b1fa_32_ff;
+extern cpuop_func op_b1fb_32_nf;
+extern cpuop_func op_b1fb_32_ff;
+extern cpuop_func op_b1fc_32_nf;
+extern cpuop_func op_b1fc_32_ff;
+extern cpuop_func op_c000_32_nf;
+extern cpuop_func op_c000_32_ff;
+extern cpuop_func op_c010_32_nf;
+extern cpuop_func op_c010_32_ff;
+extern cpuop_func op_c018_32_nf;
+extern cpuop_func op_c018_32_ff;
+extern cpuop_func op_c020_32_nf;
+extern cpuop_func op_c020_32_ff;
+extern cpuop_func op_c028_32_nf;
+extern cpuop_func op_c028_32_ff;
+extern cpuop_func op_c030_32_nf;
+extern cpuop_func op_c030_32_ff;
+extern cpuop_func op_c038_32_nf;
+extern cpuop_func op_c038_32_ff;
+extern cpuop_func op_c039_32_nf;
+extern cpuop_func op_c039_32_ff;
+extern cpuop_func op_c03a_32_nf;
+extern cpuop_func op_c03a_32_ff;
+extern cpuop_func op_c03b_32_nf;
+extern cpuop_func op_c03b_32_ff;
+extern cpuop_func op_c03c_32_nf;
+extern cpuop_func op_c03c_32_ff;
+extern cpuop_func op_c040_32_nf;
+extern cpuop_func op_c040_32_ff;
+extern cpuop_func op_c050_32_nf;
+extern cpuop_func op_c050_32_ff;
+extern cpuop_func op_c058_32_nf;
+extern cpuop_func op_c058_32_ff;
+extern cpuop_func op_c060_32_nf;
+extern cpuop_func op_c060_32_ff;
+extern cpuop_func op_c068_32_nf;
+extern cpuop_func op_c068_32_ff;
+extern cpuop_func op_c070_32_nf;
+extern cpuop_func op_c070_32_ff;
+extern cpuop_func op_c078_32_nf;
+extern cpuop_func op_c078_32_ff;
+extern cpuop_func op_c079_32_nf;
+extern cpuop_func op_c079_32_ff;
+extern cpuop_func op_c07a_32_nf;
+extern cpuop_func op_c07a_32_ff;
+extern cpuop_func op_c07b_32_nf;
+extern cpuop_func op_c07b_32_ff;
+extern cpuop_func op_c07c_32_nf;
+extern cpuop_func op_c07c_32_ff;
+extern cpuop_func op_c080_32_nf;
+extern cpuop_func op_c080_32_ff;
+extern cpuop_func op_c090_32_nf;
+extern cpuop_func op_c090_32_ff;
+extern cpuop_func op_c098_32_nf;
+extern cpuop_func op_c098_32_ff;
+extern cpuop_func op_c0a0_32_nf;
+extern cpuop_func op_c0a0_32_ff;
+extern cpuop_func op_c0a8_32_nf;
+extern cpuop_func op_c0a8_32_ff;
+extern cpuop_func op_c0b0_32_nf;
+extern cpuop_func op_c0b0_32_ff;
+extern cpuop_func op_c0b8_32_nf;
+extern cpuop_func op_c0b8_32_ff;
+extern cpuop_func op_c0b9_32_nf;
+extern cpuop_func op_c0b9_32_ff;
+extern cpuop_func op_c0ba_32_nf;
+extern cpuop_func op_c0ba_32_ff;
+extern cpuop_func op_c0bb_32_nf;
+extern cpuop_func op_c0bb_32_ff;
+extern cpuop_func op_c0bc_32_nf;
+extern cpuop_func op_c0bc_32_ff;
+extern cpuop_func op_c0c0_32_nf;
+extern cpuop_func op_c0c0_32_ff;
+extern cpuop_func op_c0d0_32_nf;
+extern cpuop_func op_c0d0_32_ff;
+extern cpuop_func op_c0d8_32_nf;
+extern cpuop_func op_c0d8_32_ff;
+extern cpuop_func op_c0e0_32_nf;
+extern cpuop_func op_c0e0_32_ff;
+extern cpuop_func op_c0e8_32_nf;
+extern cpuop_func op_c0e8_32_ff;
+extern cpuop_func op_c0f0_32_nf;
+extern cpuop_func op_c0f0_32_ff;
+extern cpuop_func op_c0f8_32_nf;
+extern cpuop_func op_c0f8_32_ff;
+extern cpuop_func op_c0f9_32_nf;
+extern cpuop_func op_c0f9_32_ff;
+extern cpuop_func op_c0fa_32_nf;
+extern cpuop_func op_c0fa_32_ff;
+extern cpuop_func op_c0fb_32_nf;
+extern cpuop_func op_c0fb_32_ff;
+extern cpuop_func op_c0fc_32_nf;
+extern cpuop_func op_c0fc_32_ff;
+extern cpuop_func op_c100_32_nf;
+extern cpuop_func op_c100_32_ff;
+extern cpuop_func op_c108_32_nf;
+extern cpuop_func op_c108_32_ff;
+extern cpuop_func op_c110_32_nf;
+extern cpuop_func op_c110_32_ff;
+extern cpuop_func op_c118_32_nf;
+extern cpuop_func op_c118_32_ff;
+extern cpuop_func op_c120_32_nf;
+extern cpuop_func op_c120_32_ff;
+extern cpuop_func op_c128_32_nf;
+extern cpuop_func op_c128_32_ff;
+extern cpuop_func op_c130_32_nf;
+extern cpuop_func op_c130_32_ff;
+extern cpuop_func op_c138_32_nf;
+extern cpuop_func op_c138_32_ff;
+extern cpuop_func op_c139_32_nf;
+extern cpuop_func op_c139_32_ff;
+extern cpuop_func op_c140_32_nf;
+extern cpuop_func op_c140_32_ff;
+extern cpuop_func op_c148_32_nf;
+extern cpuop_func op_c148_32_ff;
+extern cpuop_func op_c150_32_nf;
+extern cpuop_func op_c150_32_ff;
+extern cpuop_func op_c158_32_nf;
+extern cpuop_func op_c158_32_ff;
+extern cpuop_func op_c160_32_nf;
+extern cpuop_func op_c160_32_ff;
+extern cpuop_func op_c168_32_nf;
+extern cpuop_func op_c168_32_ff;
+extern cpuop_func op_c170_32_nf;
+extern cpuop_func op_c170_32_ff;
+extern cpuop_func op_c178_32_nf;
+extern cpuop_func op_c178_32_ff;
+extern cpuop_func op_c179_32_nf;
+extern cpuop_func op_c179_32_ff;
+extern cpuop_func op_c188_32_nf;
+extern cpuop_func op_c188_32_ff;
+extern cpuop_func op_c190_32_nf;
+extern cpuop_func op_c190_32_ff;
+extern cpuop_func op_c198_32_nf;
+extern cpuop_func op_c198_32_ff;
+extern cpuop_func op_c1a0_32_nf;
+extern cpuop_func op_c1a0_32_ff;
+extern cpuop_func op_c1a8_32_nf;
+extern cpuop_func op_c1a8_32_ff;
+extern cpuop_func op_c1b0_32_nf;
+extern cpuop_func op_c1b0_32_ff;
+extern cpuop_func op_c1b8_32_nf;
+extern cpuop_func op_c1b8_32_ff;
+extern cpuop_func op_c1b9_32_nf;
+extern cpuop_func op_c1b9_32_ff;
+extern cpuop_func op_c1c0_32_nf;
+extern cpuop_func op_c1c0_32_ff;
+extern cpuop_func op_c1d0_32_nf;
+extern cpuop_func op_c1d0_32_ff;
+extern cpuop_func op_c1d8_32_nf;
+extern cpuop_func op_c1d8_32_ff;
+extern cpuop_func op_c1e0_32_nf;
+extern cpuop_func op_c1e0_32_ff;
+extern cpuop_func op_c1e8_32_nf;
+extern cpuop_func op_c1e8_32_ff;
+extern cpuop_func op_c1f0_32_nf;
+extern cpuop_func op_c1f0_32_ff;
+extern cpuop_func op_c1f8_32_nf;
+extern cpuop_func op_c1f8_32_ff;
+extern cpuop_func op_c1f9_32_nf;
+extern cpuop_func op_c1f9_32_ff;
+extern cpuop_func op_c1fa_32_nf;
+extern cpuop_func op_c1fa_32_ff;
+extern cpuop_func op_c1fb_32_nf;
+extern cpuop_func op_c1fb_32_ff;
+extern cpuop_func op_c1fc_32_nf;
+extern cpuop_func op_c1fc_32_ff;
+extern cpuop_func op_d000_32_nf;
+extern cpuop_func op_d000_32_ff;
+extern cpuop_func op_d010_32_nf;
+extern cpuop_func op_d010_32_ff;
+extern cpuop_func op_d018_32_nf;
+extern cpuop_func op_d018_32_ff;
+extern cpuop_func op_d020_32_nf;
+extern cpuop_func op_d020_32_ff;
+extern cpuop_func op_d028_32_nf;
+extern cpuop_func op_d028_32_ff;
+extern cpuop_func op_d030_32_nf;
+extern cpuop_func op_d030_32_ff;
+extern cpuop_func op_d038_32_nf;
+extern cpuop_func op_d038_32_ff;
+extern cpuop_func op_d039_32_nf;
+extern cpuop_func op_d039_32_ff;
+extern cpuop_func op_d03a_32_nf;
+extern cpuop_func op_d03a_32_ff;
+extern cpuop_func op_d03b_32_nf;
+extern cpuop_func op_d03b_32_ff;
+extern cpuop_func op_d03c_32_nf;
+extern cpuop_func op_d03c_32_ff;
+extern cpuop_func op_d040_32_nf;
+extern cpuop_func op_d040_32_ff;
+extern cpuop_func op_d048_32_nf;
+extern cpuop_func op_d048_32_ff;
+extern cpuop_func op_d050_32_nf;
+extern cpuop_func op_d050_32_ff;
+extern cpuop_func op_d058_32_nf;
+extern cpuop_func op_d058_32_ff;
+extern cpuop_func op_d060_32_nf;
+extern cpuop_func op_d060_32_ff;
+extern cpuop_func op_d068_32_nf;
+extern cpuop_func op_d068_32_ff;
+extern cpuop_func op_d070_32_nf;
+extern cpuop_func op_d070_32_ff;
+extern cpuop_func op_d078_32_nf;
+extern cpuop_func op_d078_32_ff;
+extern cpuop_func op_d079_32_nf;
+extern cpuop_func op_d079_32_ff;
+extern cpuop_func op_d07a_32_nf;
+extern cpuop_func op_d07a_32_ff;
+extern cpuop_func op_d07b_32_nf;
+extern cpuop_func op_d07b_32_ff;
+extern cpuop_func op_d07c_32_nf;
+extern cpuop_func op_d07c_32_ff;
+extern cpuop_func op_d080_32_nf;
+extern cpuop_func op_d080_32_ff;
+extern cpuop_func op_d088_32_nf;
+extern cpuop_func op_d088_32_ff;
+extern cpuop_func op_d090_32_nf;
+extern cpuop_func op_d090_32_ff;
+extern cpuop_func op_d098_32_nf;
+extern cpuop_func op_d098_32_ff;
+extern cpuop_func op_d0a0_32_nf;
+extern cpuop_func op_d0a0_32_ff;
+extern cpuop_func op_d0a8_32_nf;
+extern cpuop_func op_d0a8_32_ff;
+extern cpuop_func op_d0b0_32_nf;
+extern cpuop_func op_d0b0_32_ff;
+extern cpuop_func op_d0b8_32_nf;
+extern cpuop_func op_d0b8_32_ff;
+extern cpuop_func op_d0b9_32_nf;
+extern cpuop_func op_d0b9_32_ff;
+extern cpuop_func op_d0ba_32_nf;
+extern cpuop_func op_d0ba_32_ff;
+extern cpuop_func op_d0bb_32_nf;
+extern cpuop_func op_d0bb_32_ff;
+extern cpuop_func op_d0bc_32_nf;
+extern cpuop_func op_d0bc_32_ff;
+extern cpuop_func op_d0c0_32_nf;
+extern cpuop_func op_d0c0_32_ff;
+extern cpuop_func op_d0c8_32_nf;
+extern cpuop_func op_d0c8_32_ff;
+extern cpuop_func op_d0d0_32_nf;
+extern cpuop_func op_d0d0_32_ff;
+extern cpuop_func op_d0d8_32_nf;
+extern cpuop_func op_d0d8_32_ff;
+extern cpuop_func op_d0e0_32_nf;
+extern cpuop_func op_d0e0_32_ff;
+extern cpuop_func op_d0e8_32_nf;
+extern cpuop_func op_d0e8_32_ff;
+extern cpuop_func op_d0f0_32_nf;
+extern cpuop_func op_d0f0_32_ff;
+extern cpuop_func op_d0f8_32_nf;
+extern cpuop_func op_d0f8_32_ff;
+extern cpuop_func op_d0f9_32_nf;
+extern cpuop_func op_d0f9_32_ff;
+extern cpuop_func op_d0fa_32_nf;
+extern cpuop_func op_d0fa_32_ff;
+extern cpuop_func op_d0fb_32_nf;
+extern cpuop_func op_d0fb_32_ff;
+extern cpuop_func op_d0fc_32_nf;
+extern cpuop_func op_d0fc_32_ff;
+extern cpuop_func op_d100_32_nf;
+extern cpuop_func op_d100_32_ff;
+extern cpuop_func op_d108_32_nf;
+extern cpuop_func op_d108_32_ff;
+extern cpuop_func op_d110_32_nf;
+extern cpuop_func op_d110_32_ff;
+extern cpuop_func op_d118_32_nf;
+extern cpuop_func op_d118_32_ff;
+extern cpuop_func op_d120_32_nf;
+extern cpuop_func op_d120_32_ff;
+extern cpuop_func op_d128_32_nf;
+extern cpuop_func op_d128_32_ff;
+extern cpuop_func op_d130_32_nf;
+extern cpuop_func op_d130_32_ff;
+extern cpuop_func op_d138_32_nf;
+extern cpuop_func op_d138_32_ff;
+extern cpuop_func op_d139_32_nf;
+extern cpuop_func op_d139_32_ff;
+extern cpuop_func op_d140_32_nf;
+extern cpuop_func op_d140_32_ff;
+extern cpuop_func op_d148_32_nf;
+extern cpuop_func op_d148_32_ff;
+extern cpuop_func op_d150_32_nf;
+extern cpuop_func op_d150_32_ff;
+extern cpuop_func op_d158_32_nf;
+extern cpuop_func op_d158_32_ff;
+extern cpuop_func op_d160_32_nf;
+extern cpuop_func op_d160_32_ff;
+extern cpuop_func op_d168_32_nf;
+extern cpuop_func op_d168_32_ff;
+extern cpuop_func op_d170_32_nf;
+extern cpuop_func op_d170_32_ff;
+extern cpuop_func op_d178_32_nf;
+extern cpuop_func op_d178_32_ff;
+extern cpuop_func op_d179_32_nf;
+extern cpuop_func op_d179_32_ff;
+extern cpuop_func op_d180_32_nf;
+extern cpuop_func op_d180_32_ff;
+extern cpuop_func op_d188_32_nf;
+extern cpuop_func op_d188_32_ff;
+extern cpuop_func op_d190_32_nf;
+extern cpuop_func op_d190_32_ff;
+extern cpuop_func op_d198_32_nf;
+extern cpuop_func op_d198_32_ff;
+extern cpuop_func op_d1a0_32_nf;
+extern cpuop_func op_d1a0_32_ff;
+extern cpuop_func op_d1a8_32_nf;
+extern cpuop_func op_d1a8_32_ff;
+extern cpuop_func op_d1b0_32_nf;
+extern cpuop_func op_d1b0_32_ff;
+extern cpuop_func op_d1b8_32_nf;
+extern cpuop_func op_d1b8_32_ff;
+extern cpuop_func op_d1b9_32_nf;
+extern cpuop_func op_d1b9_32_ff;
+extern cpuop_func op_d1c0_32_nf;
+extern cpuop_func op_d1c0_32_ff;
+extern cpuop_func op_d1c8_32_nf;
+extern cpuop_func op_d1c8_32_ff;
+extern cpuop_func op_d1d0_32_nf;
+extern cpuop_func op_d1d0_32_ff;
+extern cpuop_func op_d1d8_32_nf;
+extern cpuop_func op_d1d8_32_ff;
+extern cpuop_func op_d1e0_32_nf;
+extern cpuop_func op_d1e0_32_ff;
+extern cpuop_func op_d1e8_32_nf;
+extern cpuop_func op_d1e8_32_ff;
+extern cpuop_func op_d1f0_32_nf;
+extern cpuop_func op_d1f0_32_ff;
+extern cpuop_func op_d1f8_32_nf;
+extern cpuop_func op_d1f8_32_ff;
+extern cpuop_func op_d1f9_32_nf;
+extern cpuop_func op_d1f9_32_ff;
+extern cpuop_func op_d1fa_32_nf;
+extern cpuop_func op_d1fa_32_ff;
+extern cpuop_func op_d1fb_32_nf;
+extern cpuop_func op_d1fb_32_ff;
+extern cpuop_func op_d1fc_32_nf;
+extern cpuop_func op_d1fc_32_ff;
+extern cpuop_func op_e000_32_nf;
+extern cpuop_func op_e000_32_ff;
+extern cpuop_func op_e008_32_nf;
+extern cpuop_func op_e008_32_ff;
+extern cpuop_func op_e010_32_nf;
+extern cpuop_func op_e010_32_ff;
+extern cpuop_func op_e018_32_nf;
+extern cpuop_func op_e018_32_ff;
+extern cpuop_func op_e020_32_nf;
+extern cpuop_func op_e020_32_ff;
+extern cpuop_func op_e028_32_nf;
+extern cpuop_func op_e028_32_ff;
+extern cpuop_func op_e030_32_nf;
+extern cpuop_func op_e030_32_ff;
+extern cpuop_func op_e038_32_nf;
+extern cpuop_func op_e038_32_ff;
+extern cpuop_func op_e040_32_nf;
+extern cpuop_func op_e040_32_ff;
+extern cpuop_func op_e048_32_nf;
+extern cpuop_func op_e048_32_ff;
+extern cpuop_func op_e050_32_nf;
+extern cpuop_func op_e050_32_ff;
+extern cpuop_func op_e058_32_nf;
+extern cpuop_func op_e058_32_ff;
+extern cpuop_func op_e060_32_nf;
+extern cpuop_func op_e060_32_ff;
+extern cpuop_func op_e068_32_nf;
+extern cpuop_func op_e068_32_ff;
+extern cpuop_func op_e070_32_nf;
+extern cpuop_func op_e070_32_ff;
+extern cpuop_func op_e078_32_nf;
+extern cpuop_func op_e078_32_ff;
+extern cpuop_func op_e080_32_nf;
+extern cpuop_func op_e080_32_ff;
+extern cpuop_func op_e088_32_nf;
+extern cpuop_func op_e088_32_ff;
+extern cpuop_func op_e090_32_nf;
+extern cpuop_func op_e090_32_ff;
+extern cpuop_func op_e098_32_nf;
+extern cpuop_func op_e098_32_ff;
+extern cpuop_func op_e0a0_32_nf;
+extern cpuop_func op_e0a0_32_ff;
+extern cpuop_func op_e0a8_32_nf;
+extern cpuop_func op_e0a8_32_ff;
+extern cpuop_func op_e0b0_32_nf;
+extern cpuop_func op_e0b0_32_ff;
+extern cpuop_func op_e0b8_32_nf;
+extern cpuop_func op_e0b8_32_ff;
+extern cpuop_func op_e0d0_32_nf;
+extern cpuop_func op_e0d0_32_ff;
+extern cpuop_func op_e0d8_32_nf;
+extern cpuop_func op_e0d8_32_ff;
+extern cpuop_func op_e0e0_32_nf;
+extern cpuop_func op_e0e0_32_ff;
+extern cpuop_func op_e0e8_32_nf;
+extern cpuop_func op_e0e8_32_ff;
+extern cpuop_func op_e0f0_32_nf;
+extern cpuop_func op_e0f0_32_ff;
+extern cpuop_func op_e0f8_32_nf;
+extern cpuop_func op_e0f8_32_ff;
+extern cpuop_func op_e0f9_32_nf;
+extern cpuop_func op_e0f9_32_ff;
+extern cpuop_func op_e100_32_nf;
+extern cpuop_func op_e100_32_ff;
+extern cpuop_func op_e108_32_nf;
+extern cpuop_func op_e108_32_ff;
+extern cpuop_func op_e110_32_nf;
+extern cpuop_func op_e110_32_ff;
+extern cpuop_func op_e118_32_nf;
+extern cpuop_func op_e118_32_ff;
+extern cpuop_func op_e120_32_nf;
+extern cpuop_func op_e120_32_ff;
+extern cpuop_func op_e128_32_nf;
+extern cpuop_func op_e128_32_ff;
+extern cpuop_func op_e130_32_nf;
+extern cpuop_func op_e130_32_ff;
+extern cpuop_func op_e138_32_nf;
+extern cpuop_func op_e138_32_ff;
+extern cpuop_func op_e140_32_nf;
+extern cpuop_func op_e140_32_ff;
+extern cpuop_func op_e148_32_nf;
+extern cpuop_func op_e148_32_ff;
+extern cpuop_func op_e150_32_nf;
+extern cpuop_func op_e150_32_ff;
+extern cpuop_func op_e158_32_nf;
+extern cpuop_func op_e158_32_ff;
+extern cpuop_func op_e160_32_nf;
+extern cpuop_func op_e160_32_ff;
+extern cpuop_func op_e168_32_nf;
+extern cpuop_func op_e168_32_ff;
+extern cpuop_func op_e170_32_nf;
+extern cpuop_func op_e170_32_ff;
+extern cpuop_func op_e178_32_nf;
+extern cpuop_func op_e178_32_ff;
+extern cpuop_func op_e180_32_nf;
+extern cpuop_func op_e180_32_ff;
+extern cpuop_func op_e188_32_nf;
+extern cpuop_func op_e188_32_ff;
+extern cpuop_func op_e190_32_nf;
+extern cpuop_func op_e190_32_ff;
+extern cpuop_func op_e198_32_nf;
+extern cpuop_func op_e198_32_ff;
+extern cpuop_func op_e1a0_32_nf;
+extern cpuop_func op_e1a0_32_ff;
+extern cpuop_func op_e1a8_32_nf;
+extern cpuop_func op_e1a8_32_ff;
+extern cpuop_func op_e1b0_32_nf;
+extern cpuop_func op_e1b0_32_ff;
+extern cpuop_func op_e1b8_32_nf;
+extern cpuop_func op_e1b8_32_ff;
+extern cpuop_func op_e1d0_32_nf;
+extern cpuop_func op_e1d0_32_ff;
+extern cpuop_func op_e1d8_32_nf;
+extern cpuop_func op_e1d8_32_ff;
+extern cpuop_func op_e1e0_32_nf;
+extern cpuop_func op_e1e0_32_ff;
+extern cpuop_func op_e1e8_32_nf;
+extern cpuop_func op_e1e8_32_ff;
+extern cpuop_func op_e1f0_32_nf;
+extern cpuop_func op_e1f0_32_ff;
+extern cpuop_func op_e1f8_32_nf;
+extern cpuop_func op_e1f8_32_ff;
+extern cpuop_func op_e1f9_32_nf;
+extern cpuop_func op_e1f9_32_ff;
+extern cpuop_func op_e2d0_32_nf;
+extern cpuop_func op_e2d0_32_ff;
+extern cpuop_func op_e2d8_32_nf;
+extern cpuop_func op_e2d8_32_ff;
+extern cpuop_func op_e2e0_32_nf;
+extern cpuop_func op_e2e0_32_ff;
+extern cpuop_func op_e2e8_32_nf;
+extern cpuop_func op_e2e8_32_ff;
+extern cpuop_func op_e2f0_32_nf;
+extern cpuop_func op_e2f0_32_ff;
+extern cpuop_func op_e2f8_32_nf;
+extern cpuop_func op_e2f8_32_ff;
+extern cpuop_func op_e2f9_32_nf;
+extern cpuop_func op_e2f9_32_ff;
+extern cpuop_func op_e3d0_32_nf;
+extern cpuop_func op_e3d0_32_ff;
+extern cpuop_func op_e3d8_32_nf;
+extern cpuop_func op_e3d8_32_ff;
+extern cpuop_func op_e3e0_32_nf;
+extern cpuop_func op_e3e0_32_ff;
+extern cpuop_func op_e3e8_32_nf;
+extern cpuop_func op_e3e8_32_ff;
+extern cpuop_func op_e3f0_32_nf;
+extern cpuop_func op_e3f0_32_ff;
+extern cpuop_func op_e3f8_32_nf;
+extern cpuop_func op_e3f8_32_ff;
+extern cpuop_func op_e3f9_32_nf;
+extern cpuop_func op_e3f9_32_ff;
+extern cpuop_func op_e4d0_32_nf;
+extern cpuop_func op_e4d0_32_ff;
+extern cpuop_func op_e4d8_32_nf;
+extern cpuop_func op_e4d8_32_ff;
+extern cpuop_func op_e4e0_32_nf;
+extern cpuop_func op_e4e0_32_ff;
+extern cpuop_func op_e4e8_32_nf;
+extern cpuop_func op_e4e8_32_ff;
+extern cpuop_func op_e4f0_32_nf;
+extern cpuop_func op_e4f0_32_ff;
+extern cpuop_func op_e4f8_32_nf;
+extern cpuop_func op_e4f8_32_ff;
+extern cpuop_func op_e4f9_32_nf;
+extern cpuop_func op_e4f9_32_ff;
+extern cpuop_func op_e5d0_32_nf;
+extern cpuop_func op_e5d0_32_ff;
+extern cpuop_func op_e5d8_32_nf;
+extern cpuop_func op_e5d8_32_ff;
+extern cpuop_func op_e5e0_32_nf;
+extern cpuop_func op_e5e0_32_ff;
+extern cpuop_func op_e5e8_32_nf;
+extern cpuop_func op_e5e8_32_ff;
+extern cpuop_func op_e5f0_32_nf;
+extern cpuop_func op_e5f0_32_ff;
+extern cpuop_func op_e5f8_32_nf;
+extern cpuop_func op_e5f8_32_ff;
+extern cpuop_func op_e5f9_32_nf;
+extern cpuop_func op_e5f9_32_ff;
+extern cpuop_func op_e6d0_32_nf;
+extern cpuop_func op_e6d0_32_ff;
+extern cpuop_func op_e6d8_32_nf;
+extern cpuop_func op_e6d8_32_ff;
+extern cpuop_func op_e6e0_32_nf;
+extern cpuop_func op_e6e0_32_ff;
+extern cpuop_func op_e6e8_32_nf;
+extern cpuop_func op_e6e8_32_ff;
+extern cpuop_func op_e6f0_32_nf;
+extern cpuop_func op_e6f0_32_ff;
+extern cpuop_func op_e6f8_32_nf;
+extern cpuop_func op_e6f8_32_ff;
+extern cpuop_func op_e6f9_32_nf;
+extern cpuop_func op_e6f9_32_ff;
+extern cpuop_func op_e7d0_32_nf;
+extern cpuop_func op_e7d0_32_ff;
+extern cpuop_func op_e7d8_32_nf;
+extern cpuop_func op_e7d8_32_ff;
+extern cpuop_func op_e7e0_32_nf;
+extern cpuop_func op_e7e0_32_ff;
+extern cpuop_func op_e7e8_32_nf;
+extern cpuop_func op_e7e8_32_ff;
+extern cpuop_func op_e7f0_32_nf;
+extern cpuop_func op_e7f0_32_ff;
+extern cpuop_func op_e7f8_32_nf;
+extern cpuop_func op_e7f8_32_ff;
+extern cpuop_func op_e7f9_32_nf;
+extern cpuop_func op_e7f9_32_ff;
+extern cpuop_func op_e8c0_32_nf;
+extern cpuop_func op_e8c0_32_ff;
+extern cpuop_func op_e8d0_32_nf;
+extern cpuop_func op_e8d0_32_ff;
+extern cpuop_func op_e8e8_32_nf;
+extern cpuop_func op_e8e8_32_ff;
+extern cpuop_func op_e8f0_32_nf;
+extern cpuop_func op_e8f0_32_ff;
+extern cpuop_func op_e8f8_32_nf;
+extern cpuop_func op_e8f8_32_ff;
+extern cpuop_func op_e8f9_32_nf;
+extern cpuop_func op_e8f9_32_ff;
+extern cpuop_func op_e8fa_32_nf;
+extern cpuop_func op_e8fa_32_ff;
+extern cpuop_func op_e8fb_32_nf;
+extern cpuop_func op_e8fb_32_ff;
+extern cpuop_func op_e9c0_32_nf;
+extern cpuop_func op_e9c0_32_ff;
+extern cpuop_func op_e9d0_32_nf;
+extern cpuop_func op_e9d0_32_ff;
+extern cpuop_func op_e9e8_32_nf;
+extern cpuop_func op_e9e8_32_ff;
+extern cpuop_func op_e9f0_32_nf;
+extern cpuop_func op_e9f0_32_ff;
+extern cpuop_func op_e9f8_32_nf;
+extern cpuop_func op_e9f8_32_ff;
+extern cpuop_func op_e9f9_32_nf;
+extern cpuop_func op_e9f9_32_ff;
+extern cpuop_func op_e9fa_32_nf;
+extern cpuop_func op_e9fa_32_ff;
+extern cpuop_func op_e9fb_32_nf;
+extern cpuop_func op_e9fb_32_ff;
+extern cpuop_func op_eac0_32_nf;
+extern cpuop_func op_eac0_32_ff;
+extern cpuop_func op_ead0_32_nf;
+extern cpuop_func op_ead0_32_ff;
+extern cpuop_func op_eae8_32_nf;
+extern cpuop_func op_eae8_32_ff;
+extern cpuop_func op_eaf0_32_nf;
+extern cpuop_func op_eaf0_32_ff;
+extern cpuop_func op_eaf8_32_nf;
+extern cpuop_func op_eaf8_32_ff;
+extern cpuop_func op_eaf9_32_nf;
+extern cpuop_func op_eaf9_32_ff;
+extern cpuop_func op_ebc0_32_nf;
+extern cpuop_func op_ebc0_32_ff;
+extern cpuop_func op_ebd0_32_nf;
+extern cpuop_func op_ebd0_32_ff;
+extern cpuop_func op_ebe8_32_nf;
+extern cpuop_func op_ebe8_32_ff;
+extern cpuop_func op_ebf0_32_nf;
+extern cpuop_func op_ebf0_32_ff;
+extern cpuop_func op_ebf8_32_nf;
+extern cpuop_func op_ebf8_32_ff;
+extern cpuop_func op_ebf9_32_nf;
+extern cpuop_func op_ebf9_32_ff;
+extern cpuop_func op_ebfa_32_nf;
+extern cpuop_func op_ebfa_32_ff;
+extern cpuop_func op_ebfb_32_nf;
+extern cpuop_func op_ebfb_32_ff;
+extern cpuop_func op_ecc0_32_nf;
+extern cpuop_func op_ecc0_32_ff;
+extern cpuop_func op_ecd0_32_nf;
+extern cpuop_func op_ecd0_32_ff;
+extern cpuop_func op_ece8_32_nf;
+extern cpuop_func op_ece8_32_ff;
+extern cpuop_func op_ecf0_32_nf;
+extern cpuop_func op_ecf0_32_ff;
+extern cpuop_func op_ecf8_32_nf;
+extern cpuop_func op_ecf8_32_ff;
+extern cpuop_func op_ecf9_32_nf;
+extern cpuop_func op_ecf9_32_ff;
+extern cpuop_func op_edc0_32_nf;
+extern cpuop_func op_edc0_32_ff;
+extern cpuop_func op_edd0_32_nf;
+extern cpuop_func op_edd0_32_ff;
+extern cpuop_func op_ede8_32_nf;
+extern cpuop_func op_ede8_32_ff;
+extern cpuop_func op_edf0_32_nf;
+extern cpuop_func op_edf0_32_ff;
+extern cpuop_func op_edf8_32_nf;
+extern cpuop_func op_edf8_32_ff;
+extern cpuop_func op_edf9_32_nf;
+extern cpuop_func op_edf9_32_ff;
+extern cpuop_func op_edfa_32_nf;
+extern cpuop_func op_edfa_32_ff;
+extern cpuop_func op_edfb_32_nf;
+extern cpuop_func op_edfb_32_ff;
+extern cpuop_func op_eec0_32_nf;
+extern cpuop_func op_eec0_32_ff;
+extern cpuop_func op_eed0_32_nf;
+extern cpuop_func op_eed0_32_ff;
+extern cpuop_func op_eee8_32_nf;
+extern cpuop_func op_eee8_32_ff;
+extern cpuop_func op_eef0_32_nf;
+extern cpuop_func op_eef0_32_ff;
+extern cpuop_func op_eef8_32_nf;
+extern cpuop_func op_eef8_32_ff;
+extern cpuop_func op_eef9_32_nf;
+extern cpuop_func op_eef9_32_ff;
+extern cpuop_func op_efc0_32_nf;
+extern cpuop_func op_efc0_32_ff;
+extern cpuop_func op_efd0_32_nf;
+extern cpuop_func op_efd0_32_ff;
+extern cpuop_func op_efe8_32_nf;
+extern cpuop_func op_efe8_32_ff;
+extern cpuop_func op_eff0_32_nf;
+extern cpuop_func op_eff0_32_ff;
+extern cpuop_func op_eff8_32_nf;
+extern cpuop_func op_eff8_32_ff;
+extern cpuop_func op_eff9_32_nf;
+extern cpuop_func op_eff9_32_ff;
+extern cpuop_func op_f000_32_nf;
+extern cpuop_func op_f000_32_ff;
+extern cpuop_func op_f008_32_nf;
+extern cpuop_func op_f008_32_ff;
+extern cpuop_func op_f010_32_nf;
+extern cpuop_func op_f010_32_ff;
+extern cpuop_func op_f018_32_nf;
+extern cpuop_func op_f018_32_ff;
+extern cpuop_func op_f020_32_nf;
+extern cpuop_func op_f020_32_ff;
+extern cpuop_func op_f028_32_nf;
+extern cpuop_func op_f028_32_ff;
+extern cpuop_func op_f030_32_nf;
+extern cpuop_func op_f030_32_ff;
+extern cpuop_func op_f038_32_nf;
+extern cpuop_func op_f038_32_ff;
+extern cpuop_func op_f039_32_nf;
+extern cpuop_func op_f039_32_ff;
+extern cpuop_func op_f200_32_nf;
+extern cpuop_func op_f200_32_ff;
+extern cpuop_func op_f208_32_nf;
+extern cpuop_func op_f208_32_ff;
+extern cpuop_func op_f210_32_nf;
+extern cpuop_func op_f210_32_ff;
+extern cpuop_func op_f218_32_nf;
+extern cpuop_func op_f218_32_ff;
+extern cpuop_func op_f220_32_nf;
+extern cpuop_func op_f220_32_ff;
+extern cpuop_func op_f228_32_nf;
+extern cpuop_func op_f228_32_ff;
+extern cpuop_func op_f230_32_nf;
+extern cpuop_func op_f230_32_ff;
+extern cpuop_func op_f238_32_nf;
+extern cpuop_func op_f238_32_ff;
+extern cpuop_func op_f239_32_nf;
+extern cpuop_func op_f239_32_ff;
+extern cpuop_func op_f23a_32_nf;
+extern cpuop_func op_f23a_32_ff;
+extern cpuop_func op_f23b_32_nf;
+extern cpuop_func op_f23b_32_ff;
+extern cpuop_func op_f23c_32_nf;
+extern cpuop_func op_f23c_32_ff;
+extern cpuop_func op_f240_32_nf;
+extern cpuop_func op_f240_32_ff;
+extern cpuop_func op_f248_32_nf;
+extern cpuop_func op_f248_32_ff;
+extern cpuop_func op_f250_32_nf;
+extern cpuop_func op_f250_32_ff;
+extern cpuop_func op_f258_32_nf;
+extern cpuop_func op_f258_32_ff;
+extern cpuop_func op_f260_32_nf;
+extern cpuop_func op_f260_32_ff;
+extern cpuop_func op_f268_32_nf;
+extern cpuop_func op_f268_32_ff;
+extern cpuop_func op_f270_32_nf;
+extern cpuop_func op_f270_32_ff;
+extern cpuop_func op_f278_32_nf;
+extern cpuop_func op_f278_32_ff;
+extern cpuop_func op_f279_32_nf;
+extern cpuop_func op_f279_32_ff;
+extern cpuop_func op_f27a_32_nf;
+extern cpuop_func op_f27a_32_ff;
+extern cpuop_func op_f27b_32_nf;
+extern cpuop_func op_f27b_32_ff;
+extern cpuop_func op_f27c_32_nf;
+extern cpuop_func op_f27c_32_ff;
+extern cpuop_func op_f280_32_nf;
+extern cpuop_func op_f280_32_ff;
+extern cpuop_func op_f2c0_32_nf;
+extern cpuop_func op_f2c0_32_ff;
+extern cpuop_func op_f310_32_nf;
+extern cpuop_func op_f310_32_ff;
+extern cpuop_func op_f320_32_nf;
+extern cpuop_func op_f320_32_ff;
+extern cpuop_func op_f328_32_nf;
+extern cpuop_func op_f328_32_ff;
+extern cpuop_func op_f330_32_nf;
+extern cpuop_func op_f330_32_ff;
+extern cpuop_func op_f338_32_nf;
+extern cpuop_func op_f338_32_ff;
+extern cpuop_func op_f339_32_nf;
+extern cpuop_func op_f339_32_ff;
+extern cpuop_func op_f350_32_nf;
+extern cpuop_func op_f350_32_ff;
+extern cpuop_func op_f358_32_nf;
+extern cpuop_func op_f358_32_ff;
+extern cpuop_func op_f368_32_nf;
+extern cpuop_func op_f368_32_ff;
+extern cpuop_func op_f370_32_nf;
+extern cpuop_func op_f370_32_ff;
+extern cpuop_func op_f378_32_nf;
+extern cpuop_func op_f378_32_ff;
+extern cpuop_func op_f379_32_nf;
+extern cpuop_func op_f379_32_ff;
+extern cpuop_func op_f37a_32_nf;
+extern cpuop_func op_f37a_32_ff;
+extern cpuop_func op_f37b_32_nf;
+extern cpuop_func op_f37b_32_ff;
+extern cpuop_func op_0000_33_nf;
+extern cpuop_func op_0000_33_ff;
+extern cpuop_func op_0010_33_nf;
+extern cpuop_func op_0010_33_ff;
+extern cpuop_func op_0018_33_nf;
+extern cpuop_func op_0018_33_ff;
+extern cpuop_func op_0020_33_nf;
+extern cpuop_func op_0020_33_ff;
+extern cpuop_func op_0028_33_nf;
+extern cpuop_func op_0028_33_ff;
+extern cpuop_func op_0030_33_nf;
+extern cpuop_func op_0030_33_ff;
+extern cpuop_func op_0038_33_nf;
+extern cpuop_func op_0038_33_ff;
+extern cpuop_func op_0039_33_nf;
+extern cpuop_func op_0039_33_ff;
+extern cpuop_func op_003c_33_nf;
+extern cpuop_func op_003c_33_ff;
+extern cpuop_func op_0040_33_nf;
+extern cpuop_func op_0040_33_ff;
+extern cpuop_func op_0050_33_nf;
+extern cpuop_func op_0050_33_ff;
+extern cpuop_func op_0058_33_nf;
+extern cpuop_func op_0058_33_ff;
+extern cpuop_func op_0060_33_nf;
+extern cpuop_func op_0060_33_ff;
+extern cpuop_func op_0068_33_nf;
+extern cpuop_func op_0068_33_ff;
+extern cpuop_func op_0070_33_nf;
+extern cpuop_func op_0070_33_ff;
+extern cpuop_func op_0078_33_nf;
+extern cpuop_func op_0078_33_ff;
+extern cpuop_func op_0079_33_nf;
+extern cpuop_func op_0079_33_ff;
+extern cpuop_func op_007c_33_nf;
+extern cpuop_func op_007c_33_ff;
+extern cpuop_func op_0080_33_nf;
+extern cpuop_func op_0080_33_ff;
+extern cpuop_func op_0090_33_nf;
+extern cpuop_func op_0090_33_ff;
+extern cpuop_func op_0098_33_nf;
+extern cpuop_func op_0098_33_ff;
+extern cpuop_func op_00a0_33_nf;
+extern cpuop_func op_00a0_33_ff;
+extern cpuop_func op_00a8_33_nf;
+extern cpuop_func op_00a8_33_ff;
+extern cpuop_func op_00b0_33_nf;
+extern cpuop_func op_00b0_33_ff;
+extern cpuop_func op_00b8_33_nf;
+extern cpuop_func op_00b8_33_ff;
+extern cpuop_func op_00b9_33_nf;
+extern cpuop_func op_00b9_33_ff;
+extern cpuop_func op_00d0_33_nf;
+extern cpuop_func op_00d0_33_ff;
+extern cpuop_func op_00e8_33_nf;
+extern cpuop_func op_00e8_33_ff;
+extern cpuop_func op_00f0_33_nf;
+extern cpuop_func op_00f0_33_ff;
+extern cpuop_func op_00f8_33_nf;
+extern cpuop_func op_00f8_33_ff;
+extern cpuop_func op_00f9_33_nf;
+extern cpuop_func op_00f9_33_ff;
+extern cpuop_func op_00fa_33_nf;
+extern cpuop_func op_00fa_33_ff;
+extern cpuop_func op_00fb_33_nf;
+extern cpuop_func op_00fb_33_ff;
+extern cpuop_func op_0100_33_nf;
+extern cpuop_func op_0100_33_ff;
+extern cpuop_func op_0108_33_nf;
+extern cpuop_func op_0108_33_ff;
+extern cpuop_func op_0110_33_nf;
+extern cpuop_func op_0110_33_ff;
+extern cpuop_func op_0118_33_nf;
+extern cpuop_func op_0118_33_ff;
+extern cpuop_func op_0120_33_nf;
+extern cpuop_func op_0120_33_ff;
+extern cpuop_func op_0128_33_nf;
+extern cpuop_func op_0128_33_ff;
+extern cpuop_func op_0130_33_nf;
+extern cpuop_func op_0130_33_ff;
+extern cpuop_func op_0138_33_nf;
+extern cpuop_func op_0138_33_ff;
+extern cpuop_func op_0139_33_nf;
+extern cpuop_func op_0139_33_ff;
+extern cpuop_func op_013a_33_nf;
+extern cpuop_func op_013a_33_ff;
+extern cpuop_func op_013b_33_nf;
+extern cpuop_func op_013b_33_ff;
+extern cpuop_func op_013c_33_nf;
+extern cpuop_func op_013c_33_ff;
+extern cpuop_func op_0140_33_nf;
+extern cpuop_func op_0140_33_ff;
+extern cpuop_func op_0148_33_nf;
+extern cpuop_func op_0148_33_ff;
+extern cpuop_func op_0150_33_nf;
+extern cpuop_func op_0150_33_ff;
+extern cpuop_func op_0158_33_nf;
+extern cpuop_func op_0158_33_ff;
+extern cpuop_func op_0160_33_nf;
+extern cpuop_func op_0160_33_ff;
+extern cpuop_func op_0168_33_nf;
+extern cpuop_func op_0168_33_ff;
+extern cpuop_func op_0170_33_nf;
+extern cpuop_func op_0170_33_ff;
+extern cpuop_func op_0178_33_nf;
+extern cpuop_func op_0178_33_ff;
+extern cpuop_func op_0179_33_nf;
+extern cpuop_func op_0179_33_ff;
+extern cpuop_func op_0180_33_nf;
+extern cpuop_func op_0180_33_ff;
+extern cpuop_func op_0188_33_nf;
+extern cpuop_func op_0188_33_ff;
+extern cpuop_func op_0190_33_nf;
+extern cpuop_func op_0190_33_ff;
+extern cpuop_func op_0198_33_nf;
+extern cpuop_func op_0198_33_ff;
+extern cpuop_func op_01a0_33_nf;
+extern cpuop_func op_01a0_33_ff;
+extern cpuop_func op_01a8_33_nf;
+extern cpuop_func op_01a8_33_ff;
+extern cpuop_func op_01b0_33_nf;
+extern cpuop_func op_01b0_33_ff;
+extern cpuop_func op_01b8_33_nf;
+extern cpuop_func op_01b8_33_ff;
+extern cpuop_func op_01b9_33_nf;
+extern cpuop_func op_01b9_33_ff;
+extern cpuop_func op_01c0_33_nf;
+extern cpuop_func op_01c0_33_ff;
+extern cpuop_func op_01c8_33_nf;
+extern cpuop_func op_01c8_33_ff;
+extern cpuop_func op_01d0_33_nf;
+extern cpuop_func op_01d0_33_ff;
+extern cpuop_func op_01d8_33_nf;
+extern cpuop_func op_01d8_33_ff;
+extern cpuop_func op_01e0_33_nf;
+extern cpuop_func op_01e0_33_ff;
+extern cpuop_func op_01e8_33_nf;
+extern cpuop_func op_01e8_33_ff;
+extern cpuop_func op_01f0_33_nf;
+extern cpuop_func op_01f0_33_ff;
+extern cpuop_func op_01f8_33_nf;
+extern cpuop_func op_01f8_33_ff;
+extern cpuop_func op_01f9_33_nf;
+extern cpuop_func op_01f9_33_ff;
+extern cpuop_func op_0200_33_nf;
+extern cpuop_func op_0200_33_ff;
+extern cpuop_func op_0210_33_nf;
+extern cpuop_func op_0210_33_ff;
+extern cpuop_func op_0218_33_nf;
+extern cpuop_func op_0218_33_ff;
+extern cpuop_func op_0220_33_nf;
+extern cpuop_func op_0220_33_ff;
+extern cpuop_func op_0228_33_nf;
+extern cpuop_func op_0228_33_ff;
+extern cpuop_func op_0230_33_nf;
+extern cpuop_func op_0230_33_ff;
+extern cpuop_func op_0238_33_nf;
+extern cpuop_func op_0238_33_ff;
+extern cpuop_func op_0239_33_nf;
+extern cpuop_func op_0239_33_ff;
+extern cpuop_func op_023c_33_nf;
+extern cpuop_func op_023c_33_ff;
+extern cpuop_func op_0240_33_nf;
+extern cpuop_func op_0240_33_ff;
+extern cpuop_func op_0250_33_nf;
+extern cpuop_func op_0250_33_ff;
+extern cpuop_func op_0258_33_nf;
+extern cpuop_func op_0258_33_ff;
+extern cpuop_func op_0260_33_nf;
+extern cpuop_func op_0260_33_ff;
+extern cpuop_func op_0268_33_nf;
+extern cpuop_func op_0268_33_ff;
+extern cpuop_func op_0270_33_nf;
+extern cpuop_func op_0270_33_ff;
+extern cpuop_func op_0278_33_nf;
+extern cpuop_func op_0278_33_ff;
+extern cpuop_func op_0279_33_nf;
+extern cpuop_func op_0279_33_ff;
+extern cpuop_func op_027c_33_nf;
+extern cpuop_func op_027c_33_ff;
+extern cpuop_func op_0280_33_nf;
+extern cpuop_func op_0280_33_ff;
+extern cpuop_func op_0290_33_nf;
+extern cpuop_func op_0290_33_ff;
+extern cpuop_func op_0298_33_nf;
+extern cpuop_func op_0298_33_ff;
+extern cpuop_func op_02a0_33_nf;
+extern cpuop_func op_02a0_33_ff;
+extern cpuop_func op_02a8_33_nf;
+extern cpuop_func op_02a8_33_ff;
+extern cpuop_func op_02b0_33_nf;
+extern cpuop_func op_02b0_33_ff;
+extern cpuop_func op_02b8_33_nf;
+extern cpuop_func op_02b8_33_ff;
+extern cpuop_func op_02b9_33_nf;
+extern cpuop_func op_02b9_33_ff;
+extern cpuop_func op_02d0_33_nf;
+extern cpuop_func op_02d0_33_ff;
+extern cpuop_func op_02e8_33_nf;
+extern cpuop_func op_02e8_33_ff;
+extern cpuop_func op_02f0_33_nf;
+extern cpuop_func op_02f0_33_ff;
+extern cpuop_func op_02f8_33_nf;
+extern cpuop_func op_02f8_33_ff;
+extern cpuop_func op_02f9_33_nf;
+extern cpuop_func op_02f9_33_ff;
+extern cpuop_func op_02fa_33_nf;
+extern cpuop_func op_02fa_33_ff;
+extern cpuop_func op_02fb_33_nf;
+extern cpuop_func op_02fb_33_ff;
+extern cpuop_func op_0400_33_nf;
+extern cpuop_func op_0400_33_ff;
+extern cpuop_func op_0410_33_nf;
+extern cpuop_func op_0410_33_ff;
+extern cpuop_func op_0418_33_nf;
+extern cpuop_func op_0418_33_ff;
+extern cpuop_func op_0420_33_nf;
+extern cpuop_func op_0420_33_ff;
+extern cpuop_func op_0428_33_nf;
+extern cpuop_func op_0428_33_ff;
+extern cpuop_func op_0430_33_nf;
+extern cpuop_func op_0430_33_ff;
+extern cpuop_func op_0438_33_nf;
+extern cpuop_func op_0438_33_ff;
+extern cpuop_func op_0439_33_nf;
+extern cpuop_func op_0439_33_ff;
+extern cpuop_func op_0440_33_nf;
+extern cpuop_func op_0440_33_ff;
+extern cpuop_func op_0450_33_nf;
+extern cpuop_func op_0450_33_ff;
+extern cpuop_func op_0458_33_nf;
+extern cpuop_func op_0458_33_ff;
+extern cpuop_func op_0460_33_nf;
+extern cpuop_func op_0460_33_ff;
+extern cpuop_func op_0468_33_nf;
+extern cpuop_func op_0468_33_ff;
+extern cpuop_func op_0470_33_nf;
+extern cpuop_func op_0470_33_ff;
+extern cpuop_func op_0478_33_nf;
+extern cpuop_func op_0478_33_ff;
+extern cpuop_func op_0479_33_nf;
+extern cpuop_func op_0479_33_ff;
+extern cpuop_func op_0480_33_nf;
+extern cpuop_func op_0480_33_ff;
+extern cpuop_func op_0490_33_nf;
+extern cpuop_func op_0490_33_ff;
+extern cpuop_func op_0498_33_nf;
+extern cpuop_func op_0498_33_ff;
+extern cpuop_func op_04a0_33_nf;
+extern cpuop_func op_04a0_33_ff;
+extern cpuop_func op_04a8_33_nf;
+extern cpuop_func op_04a8_33_ff;
+extern cpuop_func op_04b0_33_nf;
+extern cpuop_func op_04b0_33_ff;
+extern cpuop_func op_04b8_33_nf;
+extern cpuop_func op_04b8_33_ff;
+extern cpuop_func op_04b9_33_nf;
+extern cpuop_func op_04b9_33_ff;
+extern cpuop_func op_04d0_33_nf;
+extern cpuop_func op_04d0_33_ff;
+extern cpuop_func op_04e8_33_nf;
+extern cpuop_func op_04e8_33_ff;
+extern cpuop_func op_04f0_33_nf;
+extern cpuop_func op_04f0_33_ff;
+extern cpuop_func op_04f8_33_nf;
+extern cpuop_func op_04f8_33_ff;
+extern cpuop_func op_04f9_33_nf;
+extern cpuop_func op_04f9_33_ff;
+extern cpuop_func op_04fa_33_nf;
+extern cpuop_func op_04fa_33_ff;
+extern cpuop_func op_04fb_33_nf;
+extern cpuop_func op_04fb_33_ff;
+extern cpuop_func op_0600_33_nf;
+extern cpuop_func op_0600_33_ff;
+extern cpuop_func op_0610_33_nf;
+extern cpuop_func op_0610_33_ff;
+extern cpuop_func op_0618_33_nf;
+extern cpuop_func op_0618_33_ff;
+extern cpuop_func op_0620_33_nf;
+extern cpuop_func op_0620_33_ff;
+extern cpuop_func op_0628_33_nf;
+extern cpuop_func op_0628_33_ff;
+extern cpuop_func op_0630_33_nf;
+extern cpuop_func op_0630_33_ff;
+extern cpuop_func op_0638_33_nf;
+extern cpuop_func op_0638_33_ff;
+extern cpuop_func op_0639_33_nf;
+extern cpuop_func op_0639_33_ff;
+extern cpuop_func op_0640_33_nf;
+extern cpuop_func op_0640_33_ff;
+extern cpuop_func op_0650_33_nf;
+extern cpuop_func op_0650_33_ff;
+extern cpuop_func op_0658_33_nf;
+extern cpuop_func op_0658_33_ff;
+extern cpuop_func op_0660_33_nf;
+extern cpuop_func op_0660_33_ff;
+extern cpuop_func op_0668_33_nf;
+extern cpuop_func op_0668_33_ff;
+extern cpuop_func op_0670_33_nf;
+extern cpuop_func op_0670_33_ff;
+extern cpuop_func op_0678_33_nf;
+extern cpuop_func op_0678_33_ff;
+extern cpuop_func op_0679_33_nf;
+extern cpuop_func op_0679_33_ff;
+extern cpuop_func op_0680_33_nf;
+extern cpuop_func op_0680_33_ff;
+extern cpuop_func op_0690_33_nf;
+extern cpuop_func op_0690_33_ff;
+extern cpuop_func op_0698_33_nf;
+extern cpuop_func op_0698_33_ff;
+extern cpuop_func op_06a0_33_nf;
+extern cpuop_func op_06a0_33_ff;
+extern cpuop_func op_06a8_33_nf;
+extern cpuop_func op_06a8_33_ff;
+extern cpuop_func op_06b0_33_nf;
+extern cpuop_func op_06b0_33_ff;
+extern cpuop_func op_06b8_33_nf;
+extern cpuop_func op_06b8_33_ff;
+extern cpuop_func op_06b9_33_nf;
+extern cpuop_func op_06b9_33_ff;
+extern cpuop_func op_06c0_33_nf;
+extern cpuop_func op_06c0_33_ff;
+extern cpuop_func op_06c8_33_nf;
+extern cpuop_func op_06c8_33_ff;
+extern cpuop_func op_06d0_33_nf;
+extern cpuop_func op_06d0_33_ff;
+extern cpuop_func op_06e8_33_nf;
+extern cpuop_func op_06e8_33_ff;
+extern cpuop_func op_06f0_33_nf;
+extern cpuop_func op_06f0_33_ff;
+extern cpuop_func op_06f8_33_nf;
+extern cpuop_func op_06f8_33_ff;
+extern cpuop_func op_06f9_33_nf;
+extern cpuop_func op_06f9_33_ff;
+extern cpuop_func op_06fa_33_nf;
+extern cpuop_func op_06fa_33_ff;
+extern cpuop_func op_06fb_33_nf;
+extern cpuop_func op_06fb_33_ff;
+extern cpuop_func op_0800_33_nf;
+extern cpuop_func op_0800_33_ff;
+extern cpuop_func op_0810_33_nf;
+extern cpuop_func op_0810_33_ff;
+extern cpuop_func op_0818_33_nf;
+extern cpuop_func op_0818_33_ff;
+extern cpuop_func op_0820_33_nf;
+extern cpuop_func op_0820_33_ff;
+extern cpuop_func op_0828_33_nf;
+extern cpuop_func op_0828_33_ff;
+extern cpuop_func op_0830_33_nf;
+extern cpuop_func op_0830_33_ff;
+extern cpuop_func op_0838_33_nf;
+extern cpuop_func op_0838_33_ff;
+extern cpuop_func op_0839_33_nf;
+extern cpuop_func op_0839_33_ff;
+extern cpuop_func op_083a_33_nf;
+extern cpuop_func op_083a_33_ff;
+extern cpuop_func op_083b_33_nf;
+extern cpuop_func op_083b_33_ff;
+extern cpuop_func op_0840_33_nf;
+extern cpuop_func op_0840_33_ff;
+extern cpuop_func op_0850_33_nf;
+extern cpuop_func op_0850_33_ff;
+extern cpuop_func op_0858_33_nf;
+extern cpuop_func op_0858_33_ff;
+extern cpuop_func op_0860_33_nf;
+extern cpuop_func op_0860_33_ff;
+extern cpuop_func op_0868_33_nf;
+extern cpuop_func op_0868_33_ff;
+extern cpuop_func op_0870_33_nf;
+extern cpuop_func op_0870_33_ff;
+extern cpuop_func op_0878_33_nf;
+extern cpuop_func op_0878_33_ff;
+extern cpuop_func op_0879_33_nf;
+extern cpuop_func op_0879_33_ff;
+extern cpuop_func op_0880_33_nf;
+extern cpuop_func op_0880_33_ff;
+extern cpuop_func op_0890_33_nf;
+extern cpuop_func op_0890_33_ff;
+extern cpuop_func op_0898_33_nf;
+extern cpuop_func op_0898_33_ff;
+extern cpuop_func op_08a0_33_nf;
+extern cpuop_func op_08a0_33_ff;
+extern cpuop_func op_08a8_33_nf;
+extern cpuop_func op_08a8_33_ff;
+extern cpuop_func op_08b0_33_nf;
+extern cpuop_func op_08b0_33_ff;
+extern cpuop_func op_08b8_33_nf;
+extern cpuop_func op_08b8_33_ff;
+extern cpuop_func op_08b9_33_nf;
+extern cpuop_func op_08b9_33_ff;
+extern cpuop_func op_08c0_33_nf;
+extern cpuop_func op_08c0_33_ff;
+extern cpuop_func op_08d0_33_nf;
+extern cpuop_func op_08d0_33_ff;
+extern cpuop_func op_08d8_33_nf;
+extern cpuop_func op_08d8_33_ff;
+extern cpuop_func op_08e0_33_nf;
+extern cpuop_func op_08e0_33_ff;
+extern cpuop_func op_08e8_33_nf;
+extern cpuop_func op_08e8_33_ff;
+extern cpuop_func op_08f0_33_nf;
+extern cpuop_func op_08f0_33_ff;
+extern cpuop_func op_08f8_33_nf;
+extern cpuop_func op_08f8_33_ff;
+extern cpuop_func op_08f9_33_nf;
+extern cpuop_func op_08f9_33_ff;
+extern cpuop_func op_0a00_33_nf;
+extern cpuop_func op_0a00_33_ff;
+extern cpuop_func op_0a10_33_nf;
+extern cpuop_func op_0a10_33_ff;
+extern cpuop_func op_0a18_33_nf;
+extern cpuop_func op_0a18_33_ff;
+extern cpuop_func op_0a20_33_nf;
+extern cpuop_func op_0a20_33_ff;
+extern cpuop_func op_0a28_33_nf;
+extern cpuop_func op_0a28_33_ff;
+extern cpuop_func op_0a30_33_nf;
+extern cpuop_func op_0a30_33_ff;
+extern cpuop_func op_0a38_33_nf;
+extern cpuop_func op_0a38_33_ff;
+extern cpuop_func op_0a39_33_nf;
+extern cpuop_func op_0a39_33_ff;
+extern cpuop_func op_0a3c_33_nf;
+extern cpuop_func op_0a3c_33_ff;
+extern cpuop_func op_0a40_33_nf;
+extern cpuop_func op_0a40_33_ff;
+extern cpuop_func op_0a50_33_nf;
+extern cpuop_func op_0a50_33_ff;
+extern cpuop_func op_0a58_33_nf;
+extern cpuop_func op_0a58_33_ff;
+extern cpuop_func op_0a60_33_nf;
+extern cpuop_func op_0a60_33_ff;
+extern cpuop_func op_0a68_33_nf;
+extern cpuop_func op_0a68_33_ff;
+extern cpuop_func op_0a70_33_nf;
+extern cpuop_func op_0a70_33_ff;
+extern cpuop_func op_0a78_33_nf;
+extern cpuop_func op_0a78_33_ff;
+extern cpuop_func op_0a79_33_nf;
+extern cpuop_func op_0a79_33_ff;
+extern cpuop_func op_0a7c_33_nf;
+extern cpuop_func op_0a7c_33_ff;
+extern cpuop_func op_0a80_33_nf;
+extern cpuop_func op_0a80_33_ff;
+extern cpuop_func op_0a90_33_nf;
+extern cpuop_func op_0a90_33_ff;
+extern cpuop_func op_0a98_33_nf;
+extern cpuop_func op_0a98_33_ff;
+extern cpuop_func op_0aa0_33_nf;
+extern cpuop_func op_0aa0_33_ff;
+extern cpuop_func op_0aa8_33_nf;
+extern cpuop_func op_0aa8_33_ff;
+extern cpuop_func op_0ab0_33_nf;
+extern cpuop_func op_0ab0_33_ff;
+extern cpuop_func op_0ab8_33_nf;
+extern cpuop_func op_0ab8_33_ff;
+extern cpuop_func op_0ab9_33_nf;
+extern cpuop_func op_0ab9_33_ff;
+extern cpuop_func op_0ad0_33_nf;
+extern cpuop_func op_0ad0_33_ff;
+extern cpuop_func op_0ad8_33_nf;
+extern cpuop_func op_0ad8_33_ff;
+extern cpuop_func op_0ae0_33_nf;
+extern cpuop_func op_0ae0_33_ff;
+extern cpuop_func op_0ae8_33_nf;
+extern cpuop_func op_0ae8_33_ff;
+extern cpuop_func op_0af0_33_nf;
+extern cpuop_func op_0af0_33_ff;
+extern cpuop_func op_0af8_33_nf;
+extern cpuop_func op_0af8_33_ff;
+extern cpuop_func op_0af9_33_nf;
+extern cpuop_func op_0af9_33_ff;
+extern cpuop_func op_0c00_33_nf;
+extern cpuop_func op_0c00_33_ff;
+extern cpuop_func op_0c10_33_nf;
+extern cpuop_func op_0c10_33_ff;
+extern cpuop_func op_0c18_33_nf;
+extern cpuop_func op_0c18_33_ff;
+extern cpuop_func op_0c20_33_nf;
+extern cpuop_func op_0c20_33_ff;
+extern cpuop_func op_0c28_33_nf;
+extern cpuop_func op_0c28_33_ff;
+extern cpuop_func op_0c30_33_nf;
+extern cpuop_func op_0c30_33_ff;
+extern cpuop_func op_0c38_33_nf;
+extern cpuop_func op_0c38_33_ff;
+extern cpuop_func op_0c39_33_nf;
+extern cpuop_func op_0c39_33_ff;
+extern cpuop_func op_0c3a_33_nf;
+extern cpuop_func op_0c3a_33_ff;
+extern cpuop_func op_0c3b_33_nf;
+extern cpuop_func op_0c3b_33_ff;
+extern cpuop_func op_0c40_33_nf;
+extern cpuop_func op_0c40_33_ff;
+extern cpuop_func op_0c50_33_nf;
+extern cpuop_func op_0c50_33_ff;
+extern cpuop_func op_0c58_33_nf;
+extern cpuop_func op_0c58_33_ff;
+extern cpuop_func op_0c60_33_nf;
+extern cpuop_func op_0c60_33_ff;
+extern cpuop_func op_0c68_33_nf;
+extern cpuop_func op_0c68_33_ff;
+extern cpuop_func op_0c70_33_nf;
+extern cpuop_func op_0c70_33_ff;
+extern cpuop_func op_0c78_33_nf;
+extern cpuop_func op_0c78_33_ff;
+extern cpuop_func op_0c79_33_nf;
+extern cpuop_func op_0c79_33_ff;
+extern cpuop_func op_0c7a_33_nf;
+extern cpuop_func op_0c7a_33_ff;
+extern cpuop_func op_0c7b_33_nf;
+extern cpuop_func op_0c7b_33_ff;
+extern cpuop_func op_0c80_33_nf;
+extern cpuop_func op_0c80_33_ff;
+extern cpuop_func op_0c90_33_nf;
+extern cpuop_func op_0c90_33_ff;
+extern cpuop_func op_0c98_33_nf;
+extern cpuop_func op_0c98_33_ff;
+extern cpuop_func op_0ca0_33_nf;
+extern cpuop_func op_0ca0_33_ff;
+extern cpuop_func op_0ca8_33_nf;
+extern cpuop_func op_0ca8_33_ff;
+extern cpuop_func op_0cb0_33_nf;
+extern cpuop_func op_0cb0_33_ff;
+extern cpuop_func op_0cb8_33_nf;
+extern cpuop_func op_0cb8_33_ff;
+extern cpuop_func op_0cb9_33_nf;
+extern cpuop_func op_0cb9_33_ff;
+extern cpuop_func op_0cba_33_nf;
+extern cpuop_func op_0cba_33_ff;
+extern cpuop_func op_0cbb_33_nf;
+extern cpuop_func op_0cbb_33_ff;
+extern cpuop_func op_0cd0_33_nf;
+extern cpuop_func op_0cd0_33_ff;
+extern cpuop_func op_0cd8_33_nf;
+extern cpuop_func op_0cd8_33_ff;
+extern cpuop_func op_0ce0_33_nf;
+extern cpuop_func op_0ce0_33_ff;
+extern cpuop_func op_0ce8_33_nf;
+extern cpuop_func op_0ce8_33_ff;
+extern cpuop_func op_0cf0_33_nf;
+extern cpuop_func op_0cf0_33_ff;
+extern cpuop_func op_0cf8_33_nf;
+extern cpuop_func op_0cf8_33_ff;
+extern cpuop_func op_0cf9_33_nf;
+extern cpuop_func op_0cf9_33_ff;
+extern cpuop_func op_0cfc_33_nf;
+extern cpuop_func op_0cfc_33_ff;
+extern cpuop_func op_0e10_33_nf;
+extern cpuop_func op_0e10_33_ff;
+extern cpuop_func op_0e18_33_nf;
+extern cpuop_func op_0e18_33_ff;
+extern cpuop_func op_0e20_33_nf;
+extern cpuop_func op_0e20_33_ff;
+extern cpuop_func op_0e28_33_nf;
+extern cpuop_func op_0e28_33_ff;
+extern cpuop_func op_0e30_33_nf;
+extern cpuop_func op_0e30_33_ff;
+extern cpuop_func op_0e38_33_nf;
+extern cpuop_func op_0e38_33_ff;
+extern cpuop_func op_0e39_33_nf;
+extern cpuop_func op_0e39_33_ff;
+extern cpuop_func op_0e50_33_nf;
+extern cpuop_func op_0e50_33_ff;
+extern cpuop_func op_0e58_33_nf;
+extern cpuop_func op_0e58_33_ff;
+extern cpuop_func op_0e60_33_nf;
+extern cpuop_func op_0e60_33_ff;
+extern cpuop_func op_0e68_33_nf;
+extern cpuop_func op_0e68_33_ff;
+extern cpuop_func op_0e70_33_nf;
+extern cpuop_func op_0e70_33_ff;
+extern cpuop_func op_0e78_33_nf;
+extern cpuop_func op_0e78_33_ff;
+extern cpuop_func op_0e79_33_nf;
+extern cpuop_func op_0e79_33_ff;
+extern cpuop_func op_0e90_33_nf;
+extern cpuop_func op_0e90_33_ff;
+extern cpuop_func op_0e98_33_nf;
+extern cpuop_func op_0e98_33_ff;
+extern cpuop_func op_0ea0_33_nf;
+extern cpuop_func op_0ea0_33_ff;
+extern cpuop_func op_0ea8_33_nf;
+extern cpuop_func op_0ea8_33_ff;
+extern cpuop_func op_0eb0_33_nf;
+extern cpuop_func op_0eb0_33_ff;
+extern cpuop_func op_0eb8_33_nf;
+extern cpuop_func op_0eb8_33_ff;
+extern cpuop_func op_0eb9_33_nf;
+extern cpuop_func op_0eb9_33_ff;
+extern cpuop_func op_0ed0_33_nf;
+extern cpuop_func op_0ed0_33_ff;
+extern cpuop_func op_0ed8_33_nf;
+extern cpuop_func op_0ed8_33_ff;
+extern cpuop_func op_0ee0_33_nf;
+extern cpuop_func op_0ee0_33_ff;
+extern cpuop_func op_0ee8_33_nf;
+extern cpuop_func op_0ee8_33_ff;
+extern cpuop_func op_0ef0_33_nf;
+extern cpuop_func op_0ef0_33_ff;
+extern cpuop_func op_0ef8_33_nf;
+extern cpuop_func op_0ef8_33_ff;
+extern cpuop_func op_0ef9_33_nf;
+extern cpuop_func op_0ef9_33_ff;
+extern cpuop_func op_0efc_33_nf;
+extern cpuop_func op_0efc_33_ff;
+extern cpuop_func op_1000_33_nf;
+extern cpuop_func op_1000_33_ff;
+extern cpuop_func op_1010_33_nf;
+extern cpuop_func op_1010_33_ff;
+extern cpuop_func op_1018_33_nf;
+extern cpuop_func op_1018_33_ff;
+extern cpuop_func op_1020_33_nf;
+extern cpuop_func op_1020_33_ff;
+extern cpuop_func op_1028_33_nf;
+extern cpuop_func op_1028_33_ff;
+extern cpuop_func op_1030_33_nf;
+extern cpuop_func op_1030_33_ff;
+extern cpuop_func op_1038_33_nf;
+extern cpuop_func op_1038_33_ff;
+extern cpuop_func op_1039_33_nf;
+extern cpuop_func op_1039_33_ff;
+extern cpuop_func op_103a_33_nf;
+extern cpuop_func op_103a_33_ff;
+extern cpuop_func op_103b_33_nf;
+extern cpuop_func op_103b_33_ff;
+extern cpuop_func op_103c_33_nf;
+extern cpuop_func op_103c_33_ff;
+extern cpuop_func op_1080_33_nf;
+extern cpuop_func op_1080_33_ff;
+extern cpuop_func op_1090_33_nf;
+extern cpuop_func op_1090_33_ff;
+extern cpuop_func op_1098_33_nf;
+extern cpuop_func op_1098_33_ff;
+extern cpuop_func op_10a0_33_nf;
+extern cpuop_func op_10a0_33_ff;
+extern cpuop_func op_10a8_33_nf;
+extern cpuop_func op_10a8_33_ff;
+extern cpuop_func op_10b0_33_nf;
+extern cpuop_func op_10b0_33_ff;
+extern cpuop_func op_10b8_33_nf;
+extern cpuop_func op_10b8_33_ff;
+extern cpuop_func op_10b9_33_nf;
+extern cpuop_func op_10b9_33_ff;
+extern cpuop_func op_10ba_33_nf;
+extern cpuop_func op_10ba_33_ff;
+extern cpuop_func op_10bb_33_nf;
+extern cpuop_func op_10bb_33_ff;
+extern cpuop_func op_10bc_33_nf;
+extern cpuop_func op_10bc_33_ff;
+extern cpuop_func op_10c0_33_nf;
+extern cpuop_func op_10c0_33_ff;
+extern cpuop_func op_10d0_33_nf;
+extern cpuop_func op_10d0_33_ff;
+extern cpuop_func op_10d8_33_nf;
+extern cpuop_func op_10d8_33_ff;
+extern cpuop_func op_10e0_33_nf;
+extern cpuop_func op_10e0_33_ff;
+extern cpuop_func op_10e8_33_nf;
+extern cpuop_func op_10e8_33_ff;
+extern cpuop_func op_10f0_33_nf;
+extern cpuop_func op_10f0_33_ff;
+extern cpuop_func op_10f8_33_nf;
+extern cpuop_func op_10f8_33_ff;
+extern cpuop_func op_10f9_33_nf;
+extern cpuop_func op_10f9_33_ff;
+extern cpuop_func op_10fa_33_nf;
+extern cpuop_func op_10fa_33_ff;
+extern cpuop_func op_10fb_33_nf;
+extern cpuop_func op_10fb_33_ff;
+extern cpuop_func op_10fc_33_nf;
+extern cpuop_func op_10fc_33_ff;
+extern cpuop_func op_1100_33_nf;
+extern cpuop_func op_1100_33_ff;
+extern cpuop_func op_1110_33_nf;
+extern cpuop_func op_1110_33_ff;
+extern cpuop_func op_1118_33_nf;
+extern cpuop_func op_1118_33_ff;
+extern cpuop_func op_1120_33_nf;
+extern cpuop_func op_1120_33_ff;
+extern cpuop_func op_1128_33_nf;
+extern cpuop_func op_1128_33_ff;
+extern cpuop_func op_1130_33_nf;
+extern cpuop_func op_1130_33_ff;
+extern cpuop_func op_1138_33_nf;
+extern cpuop_func op_1138_33_ff;
+extern cpuop_func op_1139_33_nf;
+extern cpuop_func op_1139_33_ff;
+extern cpuop_func op_113a_33_nf;
+extern cpuop_func op_113a_33_ff;
+extern cpuop_func op_113b_33_nf;
+extern cpuop_func op_113b_33_ff;
+extern cpuop_func op_113c_33_nf;
+extern cpuop_func op_113c_33_ff;
+extern cpuop_func op_1140_33_nf;
+extern cpuop_func op_1140_33_ff;
+extern cpuop_func op_1150_33_nf;
+extern cpuop_func op_1150_33_ff;
+extern cpuop_func op_1158_33_nf;
+extern cpuop_func op_1158_33_ff;
+extern cpuop_func op_1160_33_nf;
+extern cpuop_func op_1160_33_ff;
+extern cpuop_func op_1168_33_nf;
+extern cpuop_func op_1168_33_ff;
+extern cpuop_func op_1170_33_nf;
+extern cpuop_func op_1170_33_ff;
+extern cpuop_func op_1178_33_nf;
+extern cpuop_func op_1178_33_ff;
+extern cpuop_func op_1179_33_nf;
+extern cpuop_func op_1179_33_ff;
+extern cpuop_func op_117a_33_nf;
+extern cpuop_func op_117a_33_ff;
+extern cpuop_func op_117b_33_nf;
+extern cpuop_func op_117b_33_ff;
+extern cpuop_func op_117c_33_nf;
+extern cpuop_func op_117c_33_ff;
+extern cpuop_func op_1180_33_nf;
+extern cpuop_func op_1180_33_ff;
+extern cpuop_func op_1190_33_nf;
+extern cpuop_func op_1190_33_ff;
+extern cpuop_func op_1198_33_nf;
+extern cpuop_func op_1198_33_ff;
+extern cpuop_func op_11a0_33_nf;
+extern cpuop_func op_11a0_33_ff;
+extern cpuop_func op_11a8_33_nf;
+extern cpuop_func op_11a8_33_ff;
+extern cpuop_func op_11b0_33_nf;
+extern cpuop_func op_11b0_33_ff;
+extern cpuop_func op_11b8_33_nf;
+extern cpuop_func op_11b8_33_ff;
+extern cpuop_func op_11b9_33_nf;
+extern cpuop_func op_11b9_33_ff;
+extern cpuop_func op_11ba_33_nf;
+extern cpuop_func op_11ba_33_ff;
+extern cpuop_func op_11bb_33_nf;
+extern cpuop_func op_11bb_33_ff;
+extern cpuop_func op_11bc_33_nf;
+extern cpuop_func op_11bc_33_ff;
+extern cpuop_func op_11c0_33_nf;
+extern cpuop_func op_11c0_33_ff;
+extern cpuop_func op_11d0_33_nf;
+extern cpuop_func op_11d0_33_ff;
+extern cpuop_func op_11d8_33_nf;
+extern cpuop_func op_11d8_33_ff;
+extern cpuop_func op_11e0_33_nf;
+extern cpuop_func op_11e0_33_ff;
+extern cpuop_func op_11e8_33_nf;
+extern cpuop_func op_11e8_33_ff;
+extern cpuop_func op_11f0_33_nf;
+extern cpuop_func op_11f0_33_ff;
+extern cpuop_func op_11f8_33_nf;
+extern cpuop_func op_11f8_33_ff;
+extern cpuop_func op_11f9_33_nf;
+extern cpuop_func op_11f9_33_ff;
+extern cpuop_func op_11fa_33_nf;
+extern cpuop_func op_11fa_33_ff;
+extern cpuop_func op_11fb_33_nf;
+extern cpuop_func op_11fb_33_ff;
+extern cpuop_func op_11fc_33_nf;
+extern cpuop_func op_11fc_33_ff;
+extern cpuop_func op_13c0_33_nf;
+extern cpuop_func op_13c0_33_ff;
+extern cpuop_func op_13d0_33_nf;
+extern cpuop_func op_13d0_33_ff;
+extern cpuop_func op_13d8_33_nf;
+extern cpuop_func op_13d8_33_ff;
+extern cpuop_func op_13e0_33_nf;
+extern cpuop_func op_13e0_33_ff;
+extern cpuop_func op_13e8_33_nf;
+extern cpuop_func op_13e8_33_ff;
+extern cpuop_func op_13f0_33_nf;
+extern cpuop_func op_13f0_33_ff;
+extern cpuop_func op_13f8_33_nf;
+extern cpuop_func op_13f8_33_ff;
+extern cpuop_func op_13f9_33_nf;
+extern cpuop_func op_13f9_33_ff;
+extern cpuop_func op_13fa_33_nf;
+extern cpuop_func op_13fa_33_ff;
+extern cpuop_func op_13fb_33_nf;
+extern cpuop_func op_13fb_33_ff;
+extern cpuop_func op_13fc_33_nf;
+extern cpuop_func op_13fc_33_ff;
+extern cpuop_func op_2000_33_nf;
+extern cpuop_func op_2000_33_ff;
+extern cpuop_func op_2008_33_nf;
+extern cpuop_func op_2008_33_ff;
+extern cpuop_func op_2010_33_nf;
+extern cpuop_func op_2010_33_ff;
+extern cpuop_func op_2018_33_nf;
+extern cpuop_func op_2018_33_ff;
+extern cpuop_func op_2020_33_nf;
+extern cpuop_func op_2020_33_ff;
+extern cpuop_func op_2028_33_nf;
+extern cpuop_func op_2028_33_ff;
+extern cpuop_func op_2030_33_nf;
+extern cpuop_func op_2030_33_ff;
+extern cpuop_func op_2038_33_nf;
+extern cpuop_func op_2038_33_ff;
+extern cpuop_func op_2039_33_nf;
+extern cpuop_func op_2039_33_ff;
+extern cpuop_func op_203a_33_nf;
+extern cpuop_func op_203a_33_ff;
+extern cpuop_func op_203b_33_nf;
+extern cpuop_func op_203b_33_ff;
+extern cpuop_func op_203c_33_nf;
+extern cpuop_func op_203c_33_ff;
+extern cpuop_func op_2040_33_nf;
+extern cpuop_func op_2040_33_ff;
+extern cpuop_func op_2048_33_nf;
+extern cpuop_func op_2048_33_ff;
+extern cpuop_func op_2050_33_nf;
+extern cpuop_func op_2050_33_ff;
+extern cpuop_func op_2058_33_nf;
+extern cpuop_func op_2058_33_ff;
+extern cpuop_func op_2060_33_nf;
+extern cpuop_func op_2060_33_ff;
+extern cpuop_func op_2068_33_nf;
+extern cpuop_func op_2068_33_ff;
+extern cpuop_func op_2070_33_nf;
+extern cpuop_func op_2070_33_ff;
+extern cpuop_func op_2078_33_nf;
+extern cpuop_func op_2078_33_ff;
+extern cpuop_func op_2079_33_nf;
+extern cpuop_func op_2079_33_ff;
+extern cpuop_func op_207a_33_nf;
+extern cpuop_func op_207a_33_ff;
+extern cpuop_func op_207b_33_nf;
+extern cpuop_func op_207b_33_ff;
+extern cpuop_func op_207c_33_nf;
+extern cpuop_func op_207c_33_ff;
+extern cpuop_func op_2080_33_nf;
+extern cpuop_func op_2080_33_ff;
+extern cpuop_func op_2088_33_nf;
+extern cpuop_func op_2088_33_ff;
+extern cpuop_func op_2090_33_nf;
+extern cpuop_func op_2090_33_ff;
+extern cpuop_func op_2098_33_nf;
+extern cpuop_func op_2098_33_ff;
+extern cpuop_func op_20a0_33_nf;
+extern cpuop_func op_20a0_33_ff;
+extern cpuop_func op_20a8_33_nf;
+extern cpuop_func op_20a8_33_ff;
+extern cpuop_func op_20b0_33_nf;
+extern cpuop_func op_20b0_33_ff;
+extern cpuop_func op_20b8_33_nf;
+extern cpuop_func op_20b8_33_ff;
+extern cpuop_func op_20b9_33_nf;
+extern cpuop_func op_20b9_33_ff;
+extern cpuop_func op_20ba_33_nf;
+extern cpuop_func op_20ba_33_ff;
+extern cpuop_func op_20bb_33_nf;
+extern cpuop_func op_20bb_33_ff;
+extern cpuop_func op_20bc_33_nf;
+extern cpuop_func op_20bc_33_ff;
+extern cpuop_func op_20c0_33_nf;
+extern cpuop_func op_20c0_33_ff;
+extern cpuop_func op_20c8_33_nf;
+extern cpuop_func op_20c8_33_ff;
+extern cpuop_func op_20d0_33_nf;
+extern cpuop_func op_20d0_33_ff;
+extern cpuop_func op_20d8_33_nf;
+extern cpuop_func op_20d8_33_ff;
+extern cpuop_func op_20e0_33_nf;
+extern cpuop_func op_20e0_33_ff;
+extern cpuop_func op_20e8_33_nf;
+extern cpuop_func op_20e8_33_ff;
+extern cpuop_func op_20f0_33_nf;
+extern cpuop_func op_20f0_33_ff;
+extern cpuop_func op_20f8_33_nf;
+extern cpuop_func op_20f8_33_ff;
+extern cpuop_func op_20f9_33_nf;
+extern cpuop_func op_20f9_33_ff;
+extern cpuop_func op_20fa_33_nf;
+extern cpuop_func op_20fa_33_ff;
+extern cpuop_func op_20fb_33_nf;
+extern cpuop_func op_20fb_33_ff;
+extern cpuop_func op_20fc_33_nf;
+extern cpuop_func op_20fc_33_ff;
+extern cpuop_func op_2100_33_nf;
+extern cpuop_func op_2100_33_ff;
+extern cpuop_func op_2108_33_nf;
+extern cpuop_func op_2108_33_ff;
+extern cpuop_func op_2110_33_nf;
+extern cpuop_func op_2110_33_ff;
+extern cpuop_func op_2118_33_nf;
+extern cpuop_func op_2118_33_ff;
+extern cpuop_func op_2120_33_nf;
+extern cpuop_func op_2120_33_ff;
+extern cpuop_func op_2128_33_nf;
+extern cpuop_func op_2128_33_ff;
+extern cpuop_func op_2130_33_nf;
+extern cpuop_func op_2130_33_ff;
+extern cpuop_func op_2138_33_nf;
+extern cpuop_func op_2138_33_ff;
+extern cpuop_func op_2139_33_nf;
+extern cpuop_func op_2139_33_ff;
+extern cpuop_func op_213a_33_nf;
+extern cpuop_func op_213a_33_ff;
+extern cpuop_func op_213b_33_nf;
+extern cpuop_func op_213b_33_ff;
+extern cpuop_func op_213c_33_nf;
+extern cpuop_func op_213c_33_ff;
+extern cpuop_func op_2140_33_nf;
+extern cpuop_func op_2140_33_ff;
+extern cpuop_func op_2148_33_nf;
+extern cpuop_func op_2148_33_ff;
+extern cpuop_func op_2150_33_nf;
+extern cpuop_func op_2150_33_ff;
+extern cpuop_func op_2158_33_nf;
+extern cpuop_func op_2158_33_ff;
+extern cpuop_func op_2160_33_nf;
+extern cpuop_func op_2160_33_ff;
+extern cpuop_func op_2168_33_nf;
+extern cpuop_func op_2168_33_ff;
+extern cpuop_func op_2170_33_nf;
+extern cpuop_func op_2170_33_ff;
+extern cpuop_func op_2178_33_nf;
+extern cpuop_func op_2178_33_ff;
+extern cpuop_func op_2179_33_nf;
+extern cpuop_func op_2179_33_ff;
+extern cpuop_func op_217a_33_nf;
+extern cpuop_func op_217a_33_ff;
+extern cpuop_func op_217b_33_nf;
+extern cpuop_func op_217b_33_ff;
+extern cpuop_func op_217c_33_nf;
+extern cpuop_func op_217c_33_ff;
+extern cpuop_func op_2180_33_nf;
+extern cpuop_func op_2180_33_ff;
+extern cpuop_func op_2188_33_nf;
+extern cpuop_func op_2188_33_ff;
+extern cpuop_func op_2190_33_nf;
+extern cpuop_func op_2190_33_ff;
+extern cpuop_func op_2198_33_nf;
+extern cpuop_func op_2198_33_ff;
+extern cpuop_func op_21a0_33_nf;
+extern cpuop_func op_21a0_33_ff;
+extern cpuop_func op_21a8_33_nf;
+extern cpuop_func op_21a8_33_ff;
+extern cpuop_func op_21b0_33_nf;
+extern cpuop_func op_21b0_33_ff;
+extern cpuop_func op_21b8_33_nf;
+extern cpuop_func op_21b8_33_ff;
+extern cpuop_func op_21b9_33_nf;
+extern cpuop_func op_21b9_33_ff;
+extern cpuop_func op_21ba_33_nf;
+extern cpuop_func op_21ba_33_ff;
+extern cpuop_func op_21bb_33_nf;
+extern cpuop_func op_21bb_33_ff;
+extern cpuop_func op_21bc_33_nf;
+extern cpuop_func op_21bc_33_ff;
+extern cpuop_func op_21c0_33_nf;
+extern cpuop_func op_21c0_33_ff;
+extern cpuop_func op_21c8_33_nf;
+extern cpuop_func op_21c8_33_ff;
+extern cpuop_func op_21d0_33_nf;
+extern cpuop_func op_21d0_33_ff;
+extern cpuop_func op_21d8_33_nf;
+extern cpuop_func op_21d8_33_ff;
+extern cpuop_func op_21e0_33_nf;
+extern cpuop_func op_21e0_33_ff;
+extern cpuop_func op_21e8_33_nf;
+extern cpuop_func op_21e8_33_ff;
+extern cpuop_func op_21f0_33_nf;
+extern cpuop_func op_21f0_33_ff;
+extern cpuop_func op_21f8_33_nf;
+extern cpuop_func op_21f8_33_ff;
+extern cpuop_func op_21f9_33_nf;
+extern cpuop_func op_21f9_33_ff;
+extern cpuop_func op_21fa_33_nf;
+extern cpuop_func op_21fa_33_ff;
+extern cpuop_func op_21fb_33_nf;
+extern cpuop_func op_21fb_33_ff;
+extern cpuop_func op_21fc_33_nf;
+extern cpuop_func op_21fc_33_ff;
+extern cpuop_func op_23c0_33_nf;
+extern cpuop_func op_23c0_33_ff;
+extern cpuop_func op_23c8_33_nf;
+extern cpuop_func op_23c8_33_ff;
+extern cpuop_func op_23d0_33_nf;
+extern cpuop_func op_23d0_33_ff;
+extern cpuop_func op_23d8_33_nf;
+extern cpuop_func op_23d8_33_ff;
+extern cpuop_func op_23e0_33_nf;
+extern cpuop_func op_23e0_33_ff;
+extern cpuop_func op_23e8_33_nf;
+extern cpuop_func op_23e8_33_ff;
+extern cpuop_func op_23f0_33_nf;
+extern cpuop_func op_23f0_33_ff;
+extern cpuop_func op_23f8_33_nf;
+extern cpuop_func op_23f8_33_ff;
+extern cpuop_func op_23f9_33_nf;
+extern cpuop_func op_23f9_33_ff;
+extern cpuop_func op_23fa_33_nf;
+extern cpuop_func op_23fa_33_ff;
+extern cpuop_func op_23fb_33_nf;
+extern cpuop_func op_23fb_33_ff;
+extern cpuop_func op_23fc_33_nf;
+extern cpuop_func op_23fc_33_ff;
+extern cpuop_func op_3000_33_nf;
+extern cpuop_func op_3000_33_ff;
+extern cpuop_func op_3008_33_nf;
+extern cpuop_func op_3008_33_ff;
+extern cpuop_func op_3010_33_nf;
+extern cpuop_func op_3010_33_ff;
+extern cpuop_func op_3018_33_nf;
+extern cpuop_func op_3018_33_ff;
+extern cpuop_func op_3020_33_nf;
+extern cpuop_func op_3020_33_ff;
+extern cpuop_func op_3028_33_nf;
+extern cpuop_func op_3028_33_ff;
+extern cpuop_func op_3030_33_nf;
+extern cpuop_func op_3030_33_ff;
+extern cpuop_func op_3038_33_nf;
+extern cpuop_func op_3038_33_ff;
+extern cpuop_func op_3039_33_nf;
+extern cpuop_func op_3039_33_ff;
+extern cpuop_func op_303a_33_nf;
+extern cpuop_func op_303a_33_ff;
+extern cpuop_func op_303b_33_nf;
+extern cpuop_func op_303b_33_ff;
+extern cpuop_func op_303c_33_nf;
+extern cpuop_func op_303c_33_ff;
+extern cpuop_func op_3040_33_nf;
+extern cpuop_func op_3040_33_ff;
+extern cpuop_func op_3048_33_nf;
+extern cpuop_func op_3048_33_ff;
+extern cpuop_func op_3050_33_nf;
+extern cpuop_func op_3050_33_ff;
+extern cpuop_func op_3058_33_nf;
+extern cpuop_func op_3058_33_ff;
+extern cpuop_func op_3060_33_nf;
+extern cpuop_func op_3060_33_ff;
+extern cpuop_func op_3068_33_nf;
+extern cpuop_func op_3068_33_ff;
+extern cpuop_func op_3070_33_nf;
+extern cpuop_func op_3070_33_ff;
+extern cpuop_func op_3078_33_nf;
+extern cpuop_func op_3078_33_ff;
+extern cpuop_func op_3079_33_nf;
+extern cpuop_func op_3079_33_ff;
+extern cpuop_func op_307a_33_nf;
+extern cpuop_func op_307a_33_ff;
+extern cpuop_func op_307b_33_nf;
+extern cpuop_func op_307b_33_ff;
+extern cpuop_func op_307c_33_nf;
+extern cpuop_func op_307c_33_ff;
+extern cpuop_func op_3080_33_nf;
+extern cpuop_func op_3080_33_ff;
+extern cpuop_func op_3088_33_nf;
+extern cpuop_func op_3088_33_ff;
+extern cpuop_func op_3090_33_nf;
+extern cpuop_func op_3090_33_ff;
+extern cpuop_func op_3098_33_nf;
+extern cpuop_func op_3098_33_ff;
+extern cpuop_func op_30a0_33_nf;
+extern cpuop_func op_30a0_33_ff;
+extern cpuop_func op_30a8_33_nf;
+extern cpuop_func op_30a8_33_ff;
+extern cpuop_func op_30b0_33_nf;
+extern cpuop_func op_30b0_33_ff;
+extern cpuop_func op_30b8_33_nf;
+extern cpuop_func op_30b8_33_ff;
+extern cpuop_func op_30b9_33_nf;
+extern cpuop_func op_30b9_33_ff;
+extern cpuop_func op_30ba_33_nf;
+extern cpuop_func op_30ba_33_ff;
+extern cpuop_func op_30bb_33_nf;
+extern cpuop_func op_30bb_33_ff;
+extern cpuop_func op_30bc_33_nf;
+extern cpuop_func op_30bc_33_ff;
+extern cpuop_func op_30c0_33_nf;
+extern cpuop_func op_30c0_33_ff;
+extern cpuop_func op_30c8_33_nf;
+extern cpuop_func op_30c8_33_ff;
+extern cpuop_func op_30d0_33_nf;
+extern cpuop_func op_30d0_33_ff;
+extern cpuop_func op_30d8_33_nf;
+extern cpuop_func op_30d8_33_ff;
+extern cpuop_func op_30e0_33_nf;
+extern cpuop_func op_30e0_33_ff;
+extern cpuop_func op_30e8_33_nf;
+extern cpuop_func op_30e8_33_ff;
+extern cpuop_func op_30f0_33_nf;
+extern cpuop_func op_30f0_33_ff;
+extern cpuop_func op_30f8_33_nf;
+extern cpuop_func op_30f8_33_ff;
+extern cpuop_func op_30f9_33_nf;
+extern cpuop_func op_30f9_33_ff;
+extern cpuop_func op_30fa_33_nf;
+extern cpuop_func op_30fa_33_ff;
+extern cpuop_func op_30fb_33_nf;
+extern cpuop_func op_30fb_33_ff;
+extern cpuop_func op_30fc_33_nf;
+extern cpuop_func op_30fc_33_ff;
+extern cpuop_func op_3100_33_nf;
+extern cpuop_func op_3100_33_ff;
+extern cpuop_func op_3108_33_nf;
+extern cpuop_func op_3108_33_ff;
+extern cpuop_func op_3110_33_nf;
+extern cpuop_func op_3110_33_ff;
+extern cpuop_func op_3118_33_nf;
+extern cpuop_func op_3118_33_ff;
+extern cpuop_func op_3120_33_nf;
+extern cpuop_func op_3120_33_ff;
+extern cpuop_func op_3128_33_nf;
+extern cpuop_func op_3128_33_ff;
+extern cpuop_func op_3130_33_nf;
+extern cpuop_func op_3130_33_ff;
+extern cpuop_func op_3138_33_nf;
+extern cpuop_func op_3138_33_ff;
+extern cpuop_func op_3139_33_nf;
+extern cpuop_func op_3139_33_ff;
+extern cpuop_func op_313a_33_nf;
+extern cpuop_func op_313a_33_ff;
+extern cpuop_func op_313b_33_nf;
+extern cpuop_func op_313b_33_ff;
+extern cpuop_func op_313c_33_nf;
+extern cpuop_func op_313c_33_ff;
+extern cpuop_func op_3140_33_nf;
+extern cpuop_func op_3140_33_ff;
+extern cpuop_func op_3148_33_nf;
+extern cpuop_func op_3148_33_ff;
+extern cpuop_func op_3150_33_nf;
+extern cpuop_func op_3150_33_ff;
+extern cpuop_func op_3158_33_nf;
+extern cpuop_func op_3158_33_ff;
+extern cpuop_func op_3160_33_nf;
+extern cpuop_func op_3160_33_ff;
+extern cpuop_func op_3168_33_nf;
+extern cpuop_func op_3168_33_ff;
+extern cpuop_func op_3170_33_nf;
+extern cpuop_func op_3170_33_ff;
+extern cpuop_func op_3178_33_nf;
+extern cpuop_func op_3178_33_ff;
+extern cpuop_func op_3179_33_nf;
+extern cpuop_func op_3179_33_ff;
+extern cpuop_func op_317a_33_nf;
+extern cpuop_func op_317a_33_ff;
+extern cpuop_func op_317b_33_nf;
+extern cpuop_func op_317b_33_ff;
+extern cpuop_func op_317c_33_nf;
+extern cpuop_func op_317c_33_ff;
+extern cpuop_func op_3180_33_nf;
+extern cpuop_func op_3180_33_ff;
+extern cpuop_func op_3188_33_nf;
+extern cpuop_func op_3188_33_ff;
+extern cpuop_func op_3190_33_nf;
+extern cpuop_func op_3190_33_ff;
+extern cpuop_func op_3198_33_nf;
+extern cpuop_func op_3198_33_ff;
+extern cpuop_func op_31a0_33_nf;
+extern cpuop_func op_31a0_33_ff;
+extern cpuop_func op_31a8_33_nf;
+extern cpuop_func op_31a8_33_ff;
+extern cpuop_func op_31b0_33_nf;
+extern cpuop_func op_31b0_33_ff;
+extern cpuop_func op_31b8_33_nf;
+extern cpuop_func op_31b8_33_ff;
+extern cpuop_func op_31b9_33_nf;
+extern cpuop_func op_31b9_33_ff;
+extern cpuop_func op_31ba_33_nf;
+extern cpuop_func op_31ba_33_ff;
+extern cpuop_func op_31bb_33_nf;
+extern cpuop_func op_31bb_33_ff;
+extern cpuop_func op_31bc_33_nf;
+extern cpuop_func op_31bc_33_ff;
+extern cpuop_func op_31c0_33_nf;
+extern cpuop_func op_31c0_33_ff;
+extern cpuop_func op_31c8_33_nf;
+extern cpuop_func op_31c8_33_ff;
+extern cpuop_func op_31d0_33_nf;
+extern cpuop_func op_31d0_33_ff;
+extern cpuop_func op_31d8_33_nf;
+extern cpuop_func op_31d8_33_ff;
+extern cpuop_func op_31e0_33_nf;
+extern cpuop_func op_31e0_33_ff;
+extern cpuop_func op_31e8_33_nf;
+extern cpuop_func op_31e8_33_ff;
+extern cpuop_func op_31f0_33_nf;
+extern cpuop_func op_31f0_33_ff;
+extern cpuop_func op_31f8_33_nf;
+extern cpuop_func op_31f8_33_ff;
+extern cpuop_func op_31f9_33_nf;
+extern cpuop_func op_31f9_33_ff;
+extern cpuop_func op_31fa_33_nf;
+extern cpuop_func op_31fa_33_ff;
+extern cpuop_func op_31fb_33_nf;
+extern cpuop_func op_31fb_33_ff;
+extern cpuop_func op_31fc_33_nf;
+extern cpuop_func op_31fc_33_ff;
+extern cpuop_func op_33c0_33_nf;
+extern cpuop_func op_33c0_33_ff;
+extern cpuop_func op_33c8_33_nf;
+extern cpuop_func op_33c8_33_ff;
+extern cpuop_func op_33d0_33_nf;
+extern cpuop_func op_33d0_33_ff;
+extern cpuop_func op_33d8_33_nf;
+extern cpuop_func op_33d8_33_ff;
+extern cpuop_func op_33e0_33_nf;
+extern cpuop_func op_33e0_33_ff;
+extern cpuop_func op_33e8_33_nf;
+extern cpuop_func op_33e8_33_ff;
+extern cpuop_func op_33f0_33_nf;
+extern cpuop_func op_33f0_33_ff;
+extern cpuop_func op_33f8_33_nf;
+extern cpuop_func op_33f8_33_ff;
+extern cpuop_func op_33f9_33_nf;
+extern cpuop_func op_33f9_33_ff;
+extern cpuop_func op_33fa_33_nf;
+extern cpuop_func op_33fa_33_ff;
+extern cpuop_func op_33fb_33_nf;
+extern cpuop_func op_33fb_33_ff;
+extern cpuop_func op_33fc_33_nf;
+extern cpuop_func op_33fc_33_ff;
+extern cpuop_func op_4000_33_nf;
+extern cpuop_func op_4000_33_ff;
+extern cpuop_func op_4010_33_nf;
+extern cpuop_func op_4010_33_ff;
+extern cpuop_func op_4018_33_nf;
+extern cpuop_func op_4018_33_ff;
+extern cpuop_func op_4020_33_nf;
+extern cpuop_func op_4020_33_ff;
+extern cpuop_func op_4028_33_nf;
+extern cpuop_func op_4028_33_ff;
+extern cpuop_func op_4030_33_nf;
+extern cpuop_func op_4030_33_ff;
+extern cpuop_func op_4038_33_nf;
+extern cpuop_func op_4038_33_ff;
+extern cpuop_func op_4039_33_nf;
+extern cpuop_func op_4039_33_ff;
+extern cpuop_func op_4040_33_nf;
+extern cpuop_func op_4040_33_ff;
+extern cpuop_func op_4050_33_nf;
+extern cpuop_func op_4050_33_ff;
+extern cpuop_func op_4058_33_nf;
+extern cpuop_func op_4058_33_ff;
+extern cpuop_func op_4060_33_nf;
+extern cpuop_func op_4060_33_ff;
+extern cpuop_func op_4068_33_nf;
+extern cpuop_func op_4068_33_ff;
+extern cpuop_func op_4070_33_nf;
+extern cpuop_func op_4070_33_ff;
+extern cpuop_func op_4078_33_nf;
+extern cpuop_func op_4078_33_ff;
+extern cpuop_func op_4079_33_nf;
+extern cpuop_func op_4079_33_ff;
+extern cpuop_func op_4080_33_nf;
+extern cpuop_func op_4080_33_ff;
+extern cpuop_func op_4090_33_nf;
+extern cpuop_func op_4090_33_ff;
+extern cpuop_func op_4098_33_nf;
+extern cpuop_func op_4098_33_ff;
+extern cpuop_func op_40a0_33_nf;
+extern cpuop_func op_40a0_33_ff;
+extern cpuop_func op_40a8_33_nf;
+extern cpuop_func op_40a8_33_ff;
+extern cpuop_func op_40b0_33_nf;
+extern cpuop_func op_40b0_33_ff;
+extern cpuop_func op_40b8_33_nf;
+extern cpuop_func op_40b8_33_ff;
+extern cpuop_func op_40b9_33_nf;
+extern cpuop_func op_40b9_33_ff;
+extern cpuop_func op_40c0_33_nf;
+extern cpuop_func op_40c0_33_ff;
+extern cpuop_func op_40d0_33_nf;
+extern cpuop_func op_40d0_33_ff;
+extern cpuop_func op_40d8_33_nf;
+extern cpuop_func op_40d8_33_ff;
+extern cpuop_func op_40e0_33_nf;
+extern cpuop_func op_40e0_33_ff;
+extern cpuop_func op_40e8_33_nf;
+extern cpuop_func op_40e8_33_ff;
+extern cpuop_func op_40f0_33_nf;
+extern cpuop_func op_40f0_33_ff;
+extern cpuop_func op_40f8_33_nf;
+extern cpuop_func op_40f8_33_ff;
+extern cpuop_func op_40f9_33_nf;
+extern cpuop_func op_40f9_33_ff;
+extern cpuop_func op_4100_33_nf;
+extern cpuop_func op_4100_33_ff;
+extern cpuop_func op_4110_33_nf;
+extern cpuop_func op_4110_33_ff;
+extern cpuop_func op_4118_33_nf;
+extern cpuop_func op_4118_33_ff;
+extern cpuop_func op_4120_33_nf;
+extern cpuop_func op_4120_33_ff;
+extern cpuop_func op_4128_33_nf;
+extern cpuop_func op_4128_33_ff;
+extern cpuop_func op_4130_33_nf;
+extern cpuop_func op_4130_33_ff;
+extern cpuop_func op_4138_33_nf;
+extern cpuop_func op_4138_33_ff;
+extern cpuop_func op_4139_33_nf;
+extern cpuop_func op_4139_33_ff;
+extern cpuop_func op_413a_33_nf;
+extern cpuop_func op_413a_33_ff;
+extern cpuop_func op_413b_33_nf;
+extern cpuop_func op_413b_33_ff;
+extern cpuop_func op_413c_33_nf;
+extern cpuop_func op_413c_33_ff;
+extern cpuop_func op_4180_33_nf;
+extern cpuop_func op_4180_33_ff;
+extern cpuop_func op_4190_33_nf;
+extern cpuop_func op_4190_33_ff;
+extern cpuop_func op_4198_33_nf;
+extern cpuop_func op_4198_33_ff;
+extern cpuop_func op_41a0_33_nf;
+extern cpuop_func op_41a0_33_ff;
+extern cpuop_func op_41a8_33_nf;
+extern cpuop_func op_41a8_33_ff;
+extern cpuop_func op_41b0_33_nf;
+extern cpuop_func op_41b0_33_ff;
+extern cpuop_func op_41b8_33_nf;
+extern cpuop_func op_41b8_33_ff;
+extern cpuop_func op_41b9_33_nf;
+extern cpuop_func op_41b9_33_ff;
+extern cpuop_func op_41ba_33_nf;
+extern cpuop_func op_41ba_33_ff;
+extern cpuop_func op_41bb_33_nf;
+extern cpuop_func op_41bb_33_ff;
+extern cpuop_func op_41bc_33_nf;
+extern cpuop_func op_41bc_33_ff;
+extern cpuop_func op_41d0_33_nf;
+extern cpuop_func op_41d0_33_ff;
+extern cpuop_func op_41e8_33_nf;
+extern cpuop_func op_41e8_33_ff;
+extern cpuop_func op_41f0_33_nf;
+extern cpuop_func op_41f0_33_ff;
+extern cpuop_func op_41f8_33_nf;
+extern cpuop_func op_41f8_33_ff;
+extern cpuop_func op_41f9_33_nf;
+extern cpuop_func op_41f9_33_ff;
+extern cpuop_func op_41fa_33_nf;
+extern cpuop_func op_41fa_33_ff;
+extern cpuop_func op_41fb_33_nf;
+extern cpuop_func op_41fb_33_ff;
+extern cpuop_func op_4200_33_nf;
+extern cpuop_func op_4200_33_ff;
+extern cpuop_func op_4210_33_nf;
+extern cpuop_func op_4210_33_ff;
+extern cpuop_func op_4218_33_nf;
+extern cpuop_func op_4218_33_ff;
+extern cpuop_func op_4220_33_nf;
+extern cpuop_func op_4220_33_ff;
+extern cpuop_func op_4228_33_nf;
+extern cpuop_func op_4228_33_ff;
+extern cpuop_func op_4230_33_nf;
+extern cpuop_func op_4230_33_ff;
+extern cpuop_func op_4238_33_nf;
+extern cpuop_func op_4238_33_ff;
+extern cpuop_func op_4239_33_nf;
+extern cpuop_func op_4239_33_ff;
+extern cpuop_func op_4240_33_nf;
+extern cpuop_func op_4240_33_ff;
+extern cpuop_func op_4250_33_nf;
+extern cpuop_func op_4250_33_ff;
+extern cpuop_func op_4258_33_nf;
+extern cpuop_func op_4258_33_ff;
+extern cpuop_func op_4260_33_nf;
+extern cpuop_func op_4260_33_ff;
+extern cpuop_func op_4268_33_nf;
+extern cpuop_func op_4268_33_ff;
+extern cpuop_func op_4270_33_nf;
+extern cpuop_func op_4270_33_ff;
+extern cpuop_func op_4278_33_nf;
+extern cpuop_func op_4278_33_ff;
+extern cpuop_func op_4279_33_nf;
+extern cpuop_func op_4279_33_ff;
+extern cpuop_func op_4280_33_nf;
+extern cpuop_func op_4280_33_ff;
+extern cpuop_func op_4290_33_nf;
+extern cpuop_func op_4290_33_ff;
+extern cpuop_func op_4298_33_nf;
+extern cpuop_func op_4298_33_ff;
+extern cpuop_func op_42a0_33_nf;
+extern cpuop_func op_42a0_33_ff;
+extern cpuop_func op_42a8_33_nf;
+extern cpuop_func op_42a8_33_ff;
+extern cpuop_func op_42b0_33_nf;
+extern cpuop_func op_42b0_33_ff;
+extern cpuop_func op_42b8_33_nf;
+extern cpuop_func op_42b8_33_ff;
+extern cpuop_func op_42b9_33_nf;
+extern cpuop_func op_42b9_33_ff;
+extern cpuop_func op_42c0_33_nf;
+extern cpuop_func op_42c0_33_ff;
+extern cpuop_func op_42d0_33_nf;
+extern cpuop_func op_42d0_33_ff;
+extern cpuop_func op_42d8_33_nf;
+extern cpuop_func op_42d8_33_ff;
+extern cpuop_func op_42e0_33_nf;
+extern cpuop_func op_42e0_33_ff;
+extern cpuop_func op_42e8_33_nf;
+extern cpuop_func op_42e8_33_ff;
+extern cpuop_func op_42f0_33_nf;
+extern cpuop_func op_42f0_33_ff;
+extern cpuop_func op_42f8_33_nf;
+extern cpuop_func op_42f8_33_ff;
+extern cpuop_func op_42f9_33_nf;
+extern cpuop_func op_42f9_33_ff;
+extern cpuop_func op_4400_33_nf;
+extern cpuop_func op_4400_33_ff;
+extern cpuop_func op_4410_33_nf;
+extern cpuop_func op_4410_33_ff;
+extern cpuop_func op_4418_33_nf;
+extern cpuop_func op_4418_33_ff;
+extern cpuop_func op_4420_33_nf;
+extern cpuop_func op_4420_33_ff;
+extern cpuop_func op_4428_33_nf;
+extern cpuop_func op_4428_33_ff;
+extern cpuop_func op_4430_33_nf;
+extern cpuop_func op_4430_33_ff;
+extern cpuop_func op_4438_33_nf;
+extern cpuop_func op_4438_33_ff;
+extern cpuop_func op_4439_33_nf;
+extern cpuop_func op_4439_33_ff;
+extern cpuop_func op_4440_33_nf;
+extern cpuop_func op_4440_33_ff;
+extern cpuop_func op_4450_33_nf;
+extern cpuop_func op_4450_33_ff;
+extern cpuop_func op_4458_33_nf;
+extern cpuop_func op_4458_33_ff;
+extern cpuop_func op_4460_33_nf;
+extern cpuop_func op_4460_33_ff;
+extern cpuop_func op_4468_33_nf;
+extern cpuop_func op_4468_33_ff;
+extern cpuop_func op_4470_33_nf;
+extern cpuop_func op_4470_33_ff;
+extern cpuop_func op_4478_33_nf;
+extern cpuop_func op_4478_33_ff;
+extern cpuop_func op_4479_33_nf;
+extern cpuop_func op_4479_33_ff;
+extern cpuop_func op_4480_33_nf;
+extern cpuop_func op_4480_33_ff;
+extern cpuop_func op_4490_33_nf;
+extern cpuop_func op_4490_33_ff;
+extern cpuop_func op_4498_33_nf;
+extern cpuop_func op_4498_33_ff;
+extern cpuop_func op_44a0_33_nf;
+extern cpuop_func op_44a0_33_ff;
+extern cpuop_func op_44a8_33_nf;
+extern cpuop_func op_44a8_33_ff;
+extern cpuop_func op_44b0_33_nf;
+extern cpuop_func op_44b0_33_ff;
+extern cpuop_func op_44b8_33_nf;
+extern cpuop_func op_44b8_33_ff;
+extern cpuop_func op_44b9_33_nf;
+extern cpuop_func op_44b9_33_ff;
+extern cpuop_func op_44c0_33_nf;
+extern cpuop_func op_44c0_33_ff;
+extern cpuop_func op_44d0_33_nf;
+extern cpuop_func op_44d0_33_ff;
+extern cpuop_func op_44d8_33_nf;
+extern cpuop_func op_44d8_33_ff;
+extern cpuop_func op_44e0_33_nf;
+extern cpuop_func op_44e0_33_ff;
+extern cpuop_func op_44e8_33_nf;
+extern cpuop_func op_44e8_33_ff;
+extern cpuop_func op_44f0_33_nf;
+extern cpuop_func op_44f0_33_ff;
+extern cpuop_func op_44f8_33_nf;
+extern cpuop_func op_44f8_33_ff;
+extern cpuop_func op_44f9_33_nf;
+extern cpuop_func op_44f9_33_ff;
+extern cpuop_func op_44fa_33_nf;
+extern cpuop_func op_44fa_33_ff;
+extern cpuop_func op_44fb_33_nf;
+extern cpuop_func op_44fb_33_ff;
+extern cpuop_func op_44fc_33_nf;
+extern cpuop_func op_44fc_33_ff;
+extern cpuop_func op_4600_33_nf;
+extern cpuop_func op_4600_33_ff;
+extern cpuop_func op_4610_33_nf;
+extern cpuop_func op_4610_33_ff;
+extern cpuop_func op_4618_33_nf;
+extern cpuop_func op_4618_33_ff;
+extern cpuop_func op_4620_33_nf;
+extern cpuop_func op_4620_33_ff;
+extern cpuop_func op_4628_33_nf;
+extern cpuop_func op_4628_33_ff;
+extern cpuop_func op_4630_33_nf;
+extern cpuop_func op_4630_33_ff;
+extern cpuop_func op_4638_33_nf;
+extern cpuop_func op_4638_33_ff;
+extern cpuop_func op_4639_33_nf;
+extern cpuop_func op_4639_33_ff;
+extern cpuop_func op_4640_33_nf;
+extern cpuop_func op_4640_33_ff;
+extern cpuop_func op_4650_33_nf;
+extern cpuop_func op_4650_33_ff;
+extern cpuop_func op_4658_33_nf;
+extern cpuop_func op_4658_33_ff;
+extern cpuop_func op_4660_33_nf;
+extern cpuop_func op_4660_33_ff;
+extern cpuop_func op_4668_33_nf;
+extern cpuop_func op_4668_33_ff;
+extern cpuop_func op_4670_33_nf;
+extern cpuop_func op_4670_33_ff;
+extern cpuop_func op_4678_33_nf;
+extern cpuop_func op_4678_33_ff;
+extern cpuop_func op_4679_33_nf;
+extern cpuop_func op_4679_33_ff;
+extern cpuop_func op_4680_33_nf;
+extern cpuop_func op_4680_33_ff;
+extern cpuop_func op_4690_33_nf;
+extern cpuop_func op_4690_33_ff;
+extern cpuop_func op_4698_33_nf;
+extern cpuop_func op_4698_33_ff;
+extern cpuop_func op_46a0_33_nf;
+extern cpuop_func op_46a0_33_ff;
+extern cpuop_func op_46a8_33_nf;
+extern cpuop_func op_46a8_33_ff;
+extern cpuop_func op_46b0_33_nf;
+extern cpuop_func op_46b0_33_ff;
+extern cpuop_func op_46b8_33_nf;
+extern cpuop_func op_46b8_33_ff;
+extern cpuop_func op_46b9_33_nf;
+extern cpuop_func op_46b9_33_ff;
+extern cpuop_func op_46c0_33_nf;
+extern cpuop_func op_46c0_33_ff;
+extern cpuop_func op_46d0_33_nf;
+extern cpuop_func op_46d0_33_ff;
+extern cpuop_func op_46d8_33_nf;
+extern cpuop_func op_46d8_33_ff;
+extern cpuop_func op_46e0_33_nf;
+extern cpuop_func op_46e0_33_ff;
+extern cpuop_func op_46e8_33_nf;
+extern cpuop_func op_46e8_33_ff;
+extern cpuop_func op_46f0_33_nf;
+extern cpuop_func op_46f0_33_ff;
+extern cpuop_func op_46f8_33_nf;
+extern cpuop_func op_46f8_33_ff;
+extern cpuop_func op_46f9_33_nf;
+extern cpuop_func op_46f9_33_ff;
+extern cpuop_func op_46fa_33_nf;
+extern cpuop_func op_46fa_33_ff;
+extern cpuop_func op_46fb_33_nf;
+extern cpuop_func op_46fb_33_ff;
+extern cpuop_func op_46fc_33_nf;
+extern cpuop_func op_46fc_33_ff;
+extern cpuop_func op_4800_33_nf;
+extern cpuop_func op_4800_33_ff;
+extern cpuop_func op_4808_33_nf;
+extern cpuop_func op_4808_33_ff;
+extern cpuop_func op_4810_33_nf;
+extern cpuop_func op_4810_33_ff;
+extern cpuop_func op_4818_33_nf;
+extern cpuop_func op_4818_33_ff;
+extern cpuop_func op_4820_33_nf;
+extern cpuop_func op_4820_33_ff;
+extern cpuop_func op_4828_33_nf;
+extern cpuop_func op_4828_33_ff;
+extern cpuop_func op_4830_33_nf;
+extern cpuop_func op_4830_33_ff;
+extern cpuop_func op_4838_33_nf;
+extern cpuop_func op_4838_33_ff;
+extern cpuop_func op_4839_33_nf;
+extern cpuop_func op_4839_33_ff;
+extern cpuop_func op_4840_33_nf;
+extern cpuop_func op_4840_33_ff;
+extern cpuop_func op_4848_33_nf;
+extern cpuop_func op_4848_33_ff;
+extern cpuop_func op_4850_33_nf;
+extern cpuop_func op_4850_33_ff;
+extern cpuop_func op_4868_33_nf;
+extern cpuop_func op_4868_33_ff;
+extern cpuop_func op_4870_33_nf;
+extern cpuop_func op_4870_33_ff;
+extern cpuop_func op_4878_33_nf;
+extern cpuop_func op_4878_33_ff;
+extern cpuop_func op_4879_33_nf;
+extern cpuop_func op_4879_33_ff;
+extern cpuop_func op_487a_33_nf;
+extern cpuop_func op_487a_33_ff;
+extern cpuop_func op_487b_33_nf;
+extern cpuop_func op_487b_33_ff;
+extern cpuop_func op_4880_33_nf;
+extern cpuop_func op_4880_33_ff;
+extern cpuop_func op_4890_33_nf;
+extern cpuop_func op_4890_33_ff;
+extern cpuop_func op_48a0_33_nf;
+extern cpuop_func op_48a0_33_ff;
+extern cpuop_func op_48a8_33_nf;
+extern cpuop_func op_48a8_33_ff;
+extern cpuop_func op_48b0_33_nf;
+extern cpuop_func op_48b0_33_ff;
+extern cpuop_func op_48b8_33_nf;
+extern cpuop_func op_48b8_33_ff;
+extern cpuop_func op_48b9_33_nf;
+extern cpuop_func op_48b9_33_ff;
+extern cpuop_func op_48c0_33_nf;
+extern cpuop_func op_48c0_33_ff;
+extern cpuop_func op_48d0_33_nf;
+extern cpuop_func op_48d0_33_ff;
+extern cpuop_func op_48e0_33_nf;
+extern cpuop_func op_48e0_33_ff;
+extern cpuop_func op_48e8_33_nf;
+extern cpuop_func op_48e8_33_ff;
+extern cpuop_func op_48f0_33_nf;
+extern cpuop_func op_48f0_33_ff;
+extern cpuop_func op_48f8_33_nf;
+extern cpuop_func op_48f8_33_ff;
+extern cpuop_func op_48f9_33_nf;
+extern cpuop_func op_48f9_33_ff;
+extern cpuop_func op_49c0_33_nf;
+extern cpuop_func op_49c0_33_ff;
+extern cpuop_func op_4a00_33_nf;
+extern cpuop_func op_4a00_33_ff;
+extern cpuop_func op_4a10_33_nf;
+extern cpuop_func op_4a10_33_ff;
+extern cpuop_func op_4a18_33_nf;
+extern cpuop_func op_4a18_33_ff;
+extern cpuop_func op_4a20_33_nf;
+extern cpuop_func op_4a20_33_ff;
+extern cpuop_func op_4a28_33_nf;
+extern cpuop_func op_4a28_33_ff;
+extern cpuop_func op_4a30_33_nf;
+extern cpuop_func op_4a30_33_ff;
+extern cpuop_func op_4a38_33_nf;
+extern cpuop_func op_4a38_33_ff;
+extern cpuop_func op_4a39_33_nf;
+extern cpuop_func op_4a39_33_ff;
+extern cpuop_func op_4a3a_33_nf;
+extern cpuop_func op_4a3a_33_ff;
+extern cpuop_func op_4a3b_33_nf;
+extern cpuop_func op_4a3b_33_ff;
+extern cpuop_func op_4a3c_33_nf;
+extern cpuop_func op_4a3c_33_ff;
+extern cpuop_func op_4a40_33_nf;
+extern cpuop_func op_4a40_33_ff;
+extern cpuop_func op_4a48_33_nf;
+extern cpuop_func op_4a48_33_ff;
+extern cpuop_func op_4a50_33_nf;
+extern cpuop_func op_4a50_33_ff;
+extern cpuop_func op_4a58_33_nf;
+extern cpuop_func op_4a58_33_ff;
+extern cpuop_func op_4a60_33_nf;
+extern cpuop_func op_4a60_33_ff;
+extern cpuop_func op_4a68_33_nf;
+extern cpuop_func op_4a68_33_ff;
+extern cpuop_func op_4a70_33_nf;
+extern cpuop_func op_4a70_33_ff;
+extern cpuop_func op_4a78_33_nf;
+extern cpuop_func op_4a78_33_ff;
+extern cpuop_func op_4a79_33_nf;
+extern cpuop_func op_4a79_33_ff;
+extern cpuop_func op_4a7a_33_nf;
+extern cpuop_func op_4a7a_33_ff;
+extern cpuop_func op_4a7b_33_nf;
+extern cpuop_func op_4a7b_33_ff;
+extern cpuop_func op_4a7c_33_nf;
+extern cpuop_func op_4a7c_33_ff;
+extern cpuop_func op_4a80_33_nf;
+extern cpuop_func op_4a80_33_ff;
+extern cpuop_func op_4a88_33_nf;
+extern cpuop_func op_4a88_33_ff;
+extern cpuop_func op_4a90_33_nf;
+extern cpuop_func op_4a90_33_ff;
+extern cpuop_func op_4a98_33_nf;
+extern cpuop_func op_4a98_33_ff;
+extern cpuop_func op_4aa0_33_nf;
+extern cpuop_func op_4aa0_33_ff;
+extern cpuop_func op_4aa8_33_nf;
+extern cpuop_func op_4aa8_33_ff;
+extern cpuop_func op_4ab0_33_nf;
+extern cpuop_func op_4ab0_33_ff;
+extern cpuop_func op_4ab8_33_nf;
+extern cpuop_func op_4ab8_33_ff;
+extern cpuop_func op_4ab9_33_nf;
+extern cpuop_func op_4ab9_33_ff;
+extern cpuop_func op_4aba_33_nf;
+extern cpuop_func op_4aba_33_ff;
+extern cpuop_func op_4abb_33_nf;
+extern cpuop_func op_4abb_33_ff;
+extern cpuop_func op_4abc_33_nf;
+extern cpuop_func op_4abc_33_ff;
+extern cpuop_func op_4ac0_33_nf;
+extern cpuop_func op_4ac0_33_ff;
+extern cpuop_func op_4ad0_33_nf;
+extern cpuop_func op_4ad0_33_ff;
+extern cpuop_func op_4ad8_33_nf;
+extern cpuop_func op_4ad8_33_ff;
+extern cpuop_func op_4ae0_33_nf;
+extern cpuop_func op_4ae0_33_ff;
+extern cpuop_func op_4ae8_33_nf;
+extern cpuop_func op_4ae8_33_ff;
+extern cpuop_func op_4af0_33_nf;
+extern cpuop_func op_4af0_33_ff;
+extern cpuop_func op_4af8_33_nf;
+extern cpuop_func op_4af8_33_ff;
+extern cpuop_func op_4af9_33_nf;
+extern cpuop_func op_4af9_33_ff;
+extern cpuop_func op_4c00_33_nf;
+extern cpuop_func op_4c00_33_ff;
+extern cpuop_func op_4c10_33_nf;
+extern cpuop_func op_4c10_33_ff;
+extern cpuop_func op_4c18_33_nf;
+extern cpuop_func op_4c18_33_ff;
+extern cpuop_func op_4c20_33_nf;
+extern cpuop_func op_4c20_33_ff;
+extern cpuop_func op_4c28_33_nf;
+extern cpuop_func op_4c28_33_ff;
+extern cpuop_func op_4c30_33_nf;
+extern cpuop_func op_4c30_33_ff;
+extern cpuop_func op_4c38_33_nf;
+extern cpuop_func op_4c38_33_ff;
+extern cpuop_func op_4c39_33_nf;
+extern cpuop_func op_4c39_33_ff;
+extern cpuop_func op_4c3a_33_nf;
+extern cpuop_func op_4c3a_33_ff;
+extern cpuop_func op_4c3b_33_nf;
+extern cpuop_func op_4c3b_33_ff;
+extern cpuop_func op_4c3c_33_nf;
+extern cpuop_func op_4c3c_33_ff;
+extern cpuop_func op_4c40_33_nf;
+extern cpuop_func op_4c40_33_ff;
+extern cpuop_func op_4c50_33_nf;
+extern cpuop_func op_4c50_33_ff;
+extern cpuop_func op_4c58_33_nf;
+extern cpuop_func op_4c58_33_ff;
+extern cpuop_func op_4c60_33_nf;
+extern cpuop_func op_4c60_33_ff;
+extern cpuop_func op_4c68_33_nf;
+extern cpuop_func op_4c68_33_ff;
+extern cpuop_func op_4c70_33_nf;
+extern cpuop_func op_4c70_33_ff;
+extern cpuop_func op_4c78_33_nf;
+extern cpuop_func op_4c78_33_ff;
+extern cpuop_func op_4c79_33_nf;
+extern cpuop_func op_4c79_33_ff;
+extern cpuop_func op_4c7a_33_nf;
+extern cpuop_func op_4c7a_33_ff;
+extern cpuop_func op_4c7b_33_nf;
+extern cpuop_func op_4c7b_33_ff;
+extern cpuop_func op_4c7c_33_nf;
+extern cpuop_func op_4c7c_33_ff;
+extern cpuop_func op_4c90_33_nf;
+extern cpuop_func op_4c90_33_ff;
+extern cpuop_func op_4c98_33_nf;
+extern cpuop_func op_4c98_33_ff;
+extern cpuop_func op_4ca8_33_nf;
+extern cpuop_func op_4ca8_33_ff;
+extern cpuop_func op_4cb0_33_nf;
+extern cpuop_func op_4cb0_33_ff;
+extern cpuop_func op_4cb8_33_nf;
+extern cpuop_func op_4cb8_33_ff;
+extern cpuop_func op_4cb9_33_nf;
+extern cpuop_func op_4cb9_33_ff;
+extern cpuop_func op_4cba_33_nf;
+extern cpuop_func op_4cba_33_ff;
+extern cpuop_func op_4cbb_33_nf;
+extern cpuop_func op_4cbb_33_ff;
+extern cpuop_func op_4cd0_33_nf;
+extern cpuop_func op_4cd0_33_ff;
+extern cpuop_func op_4cd8_33_nf;
+extern cpuop_func op_4cd8_33_ff;
+extern cpuop_func op_4ce8_33_nf;
+extern cpuop_func op_4ce8_33_ff;
+extern cpuop_func op_4cf0_33_nf;
+extern cpuop_func op_4cf0_33_ff;
+extern cpuop_func op_4cf8_33_nf;
+extern cpuop_func op_4cf8_33_ff;
+extern cpuop_func op_4cf9_33_nf;
+extern cpuop_func op_4cf9_33_ff;
+extern cpuop_func op_4cfa_33_nf;
+extern cpuop_func op_4cfa_33_ff;
+extern cpuop_func op_4cfb_33_nf;
+extern cpuop_func op_4cfb_33_ff;
+extern cpuop_func op_4e40_33_nf;
+extern cpuop_func op_4e40_33_ff;
+extern cpuop_func op_4e50_33_nf;
+extern cpuop_func op_4e50_33_ff;
+extern cpuop_func op_4e58_33_nf;
+extern cpuop_func op_4e58_33_ff;
+extern cpuop_func op_4e60_33_nf;
+extern cpuop_func op_4e60_33_ff;
+extern cpuop_func op_4e68_33_nf;
+extern cpuop_func op_4e68_33_ff;
+extern cpuop_func op_4e70_33_nf;
+extern cpuop_func op_4e70_33_ff;
+extern cpuop_func op_4e71_33_nf;
+extern cpuop_func op_4e71_33_ff;
+extern cpuop_func op_4e72_33_nf;
+extern cpuop_func op_4e72_33_ff;
+extern cpuop_func op_4e73_33_nf;
+extern cpuop_func op_4e73_33_ff;
+extern cpuop_func op_4e74_33_nf;
+extern cpuop_func op_4e74_33_ff;
+extern cpuop_func op_4e75_33_nf;
+extern cpuop_func op_4e75_33_ff;
+extern cpuop_func op_4e76_33_nf;
+extern cpuop_func op_4e76_33_ff;
+extern cpuop_func op_4e77_33_nf;
+extern cpuop_func op_4e77_33_ff;
+extern cpuop_func op_4e7a_33_nf;
+extern cpuop_func op_4e7a_33_ff;
+extern cpuop_func op_4e7b_33_nf;
+extern cpuop_func op_4e7b_33_ff;
+extern cpuop_func op_4e90_33_nf;
+extern cpuop_func op_4e90_33_ff;
+extern cpuop_func op_4ea8_33_nf;
+extern cpuop_func op_4ea8_33_ff;
+extern cpuop_func op_4eb0_33_nf;
+extern cpuop_func op_4eb0_33_ff;
+extern cpuop_func op_4eb8_33_nf;
+extern cpuop_func op_4eb8_33_ff;
+extern cpuop_func op_4eb9_33_nf;
+extern cpuop_func op_4eb9_33_ff;
+extern cpuop_func op_4eba_33_nf;
+extern cpuop_func op_4eba_33_ff;
+extern cpuop_func op_4ebb_33_nf;
+extern cpuop_func op_4ebb_33_ff;
+extern cpuop_func op_4ed0_33_nf;
+extern cpuop_func op_4ed0_33_ff;
+extern cpuop_func op_4ee8_33_nf;
+extern cpuop_func op_4ee8_33_ff;
+extern cpuop_func op_4ef0_33_nf;
+extern cpuop_func op_4ef0_33_ff;
+extern cpuop_func op_4ef8_33_nf;
+extern cpuop_func op_4ef8_33_ff;
+extern cpuop_func op_4ef9_33_nf;
+extern cpuop_func op_4ef9_33_ff;
+extern cpuop_func op_4efa_33_nf;
+extern cpuop_func op_4efa_33_ff;
+extern cpuop_func op_4efb_33_nf;
+extern cpuop_func op_4efb_33_ff;
+extern cpuop_func op_5000_33_nf;
+extern cpuop_func op_5000_33_ff;
+extern cpuop_func op_5010_33_nf;
+extern cpuop_func op_5010_33_ff;
+extern cpuop_func op_5018_33_nf;
+extern cpuop_func op_5018_33_ff;
+extern cpuop_func op_5020_33_nf;
+extern cpuop_func op_5020_33_ff;
+extern cpuop_func op_5028_33_nf;
+extern cpuop_func op_5028_33_ff;
+extern cpuop_func op_5030_33_nf;
+extern cpuop_func op_5030_33_ff;
+extern cpuop_func op_5038_33_nf;
+extern cpuop_func op_5038_33_ff;
+extern cpuop_func op_5039_33_nf;
+extern cpuop_func op_5039_33_ff;
+extern cpuop_func op_5040_33_nf;
+extern cpuop_func op_5040_33_ff;
+extern cpuop_func op_5048_33_nf;
+extern cpuop_func op_5048_33_ff;
+extern cpuop_func op_5050_33_nf;
+extern cpuop_func op_5050_33_ff;
+extern cpuop_func op_5058_33_nf;
+extern cpuop_func op_5058_33_ff;
+extern cpuop_func op_5060_33_nf;
+extern cpuop_func op_5060_33_ff;
+extern cpuop_func op_5068_33_nf;
+extern cpuop_func op_5068_33_ff;
+extern cpuop_func op_5070_33_nf;
+extern cpuop_func op_5070_33_ff;
+extern cpuop_func op_5078_33_nf;
+extern cpuop_func op_5078_33_ff;
+extern cpuop_func op_5079_33_nf;
+extern cpuop_func op_5079_33_ff;
+extern cpuop_func op_5080_33_nf;
+extern cpuop_func op_5080_33_ff;
+extern cpuop_func op_5088_33_nf;
+extern cpuop_func op_5088_33_ff;
+extern cpuop_func op_5090_33_nf;
+extern cpuop_func op_5090_33_ff;
+extern cpuop_func op_5098_33_nf;
+extern cpuop_func op_5098_33_ff;
+extern cpuop_func op_50a0_33_nf;
+extern cpuop_func op_50a0_33_ff;
+extern cpuop_func op_50a8_33_nf;
+extern cpuop_func op_50a8_33_ff;
+extern cpuop_func op_50b0_33_nf;
+extern cpuop_func op_50b0_33_ff;
+extern cpuop_func op_50b8_33_nf;
+extern cpuop_func op_50b8_33_ff;
+extern cpuop_func op_50b9_33_nf;
+extern cpuop_func op_50b9_33_ff;
+extern cpuop_func op_50c0_33_nf;
+extern cpuop_func op_50c0_33_ff;
+extern cpuop_func op_50c8_33_nf;
+extern cpuop_func op_50c8_33_ff;
+extern cpuop_func op_50d0_33_nf;
+extern cpuop_func op_50d0_33_ff;
+extern cpuop_func op_50d8_33_nf;
+extern cpuop_func op_50d8_33_ff;
+extern cpuop_func op_50e0_33_nf;
+extern cpuop_func op_50e0_33_ff;
+extern cpuop_func op_50e8_33_nf;
+extern cpuop_func op_50e8_33_ff;
+extern cpuop_func op_50f0_33_nf;
+extern cpuop_func op_50f0_33_ff;
+extern cpuop_func op_50f8_33_nf;
+extern cpuop_func op_50f8_33_ff;
+extern cpuop_func op_50f9_33_nf;
+extern cpuop_func op_50f9_33_ff;
+extern cpuop_func op_50fa_33_nf;
+extern cpuop_func op_50fa_33_ff;
+extern cpuop_func op_50fb_33_nf;
+extern cpuop_func op_50fb_33_ff;
+extern cpuop_func op_50fc_33_nf;
+extern cpuop_func op_50fc_33_ff;
+extern cpuop_func op_5100_33_nf;
+extern cpuop_func op_5100_33_ff;
+extern cpuop_func op_5110_33_nf;
+extern cpuop_func op_5110_33_ff;
+extern cpuop_func op_5118_33_nf;
+extern cpuop_func op_5118_33_ff;
+extern cpuop_func op_5120_33_nf;
+extern cpuop_func op_5120_33_ff;
+extern cpuop_func op_5128_33_nf;
+extern cpuop_func op_5128_33_ff;
+extern cpuop_func op_5130_33_nf;
+extern cpuop_func op_5130_33_ff;
+extern cpuop_func op_5138_33_nf;
+extern cpuop_func op_5138_33_ff;
+extern cpuop_func op_5139_33_nf;
+extern cpuop_func op_5139_33_ff;
+extern cpuop_func op_5140_33_nf;
+extern cpuop_func op_5140_33_ff;
+extern cpuop_func op_5148_33_nf;
+extern cpuop_func op_5148_33_ff;
+extern cpuop_func op_5150_33_nf;
+extern cpuop_func op_5150_33_ff;
+extern cpuop_func op_5158_33_nf;
+extern cpuop_func op_5158_33_ff;
+extern cpuop_func op_5160_33_nf;
+extern cpuop_func op_5160_33_ff;
+extern cpuop_func op_5168_33_nf;
+extern cpuop_func op_5168_33_ff;
+extern cpuop_func op_5170_33_nf;
+extern cpuop_func op_5170_33_ff;
+extern cpuop_func op_5178_33_nf;
+extern cpuop_func op_5178_33_ff;
+extern cpuop_func op_5179_33_nf;
+extern cpuop_func op_5179_33_ff;
+extern cpuop_func op_5180_33_nf;
+extern cpuop_func op_5180_33_ff;
+extern cpuop_func op_5188_33_nf;
+extern cpuop_func op_5188_33_ff;
+extern cpuop_func op_5190_33_nf;
+extern cpuop_func op_5190_33_ff;
+extern cpuop_func op_5198_33_nf;
+extern cpuop_func op_5198_33_ff;
+extern cpuop_func op_51a0_33_nf;
+extern cpuop_func op_51a0_33_ff;
+extern cpuop_func op_51a8_33_nf;
+extern cpuop_func op_51a8_33_ff;
+extern cpuop_func op_51b0_33_nf;
+extern cpuop_func op_51b0_33_ff;
+extern cpuop_func op_51b8_33_nf;
+extern cpuop_func op_51b8_33_ff;
+extern cpuop_func op_51b9_33_nf;
+extern cpuop_func op_51b9_33_ff;
+extern cpuop_func op_51c0_33_nf;
+extern cpuop_func op_51c0_33_ff;
+extern cpuop_func op_51c8_33_nf;
+extern cpuop_func op_51c8_33_ff;
+extern cpuop_func op_51d0_33_nf;
+extern cpuop_func op_51d0_33_ff;
+extern cpuop_func op_51d8_33_nf;
+extern cpuop_func op_51d8_33_ff;
+extern cpuop_func op_51e0_33_nf;
+extern cpuop_func op_51e0_33_ff;
+extern cpuop_func op_51e8_33_nf;
+extern cpuop_func op_51e8_33_ff;
+extern cpuop_func op_51f0_33_nf;
+extern cpuop_func op_51f0_33_ff;
+extern cpuop_func op_51f8_33_nf;
+extern cpuop_func op_51f8_33_ff;
+extern cpuop_func op_51f9_33_nf;
+extern cpuop_func op_51f9_33_ff;
+extern cpuop_func op_51fa_33_nf;
+extern cpuop_func op_51fa_33_ff;
+extern cpuop_func op_51fb_33_nf;
+extern cpuop_func op_51fb_33_ff;
+extern cpuop_func op_51fc_33_nf;
+extern cpuop_func op_51fc_33_ff;
+extern cpuop_func op_52c0_33_nf;
+extern cpuop_func op_52c0_33_ff;
+extern cpuop_func op_52c8_33_nf;
+extern cpuop_func op_52c8_33_ff;
+extern cpuop_func op_52d0_33_nf;
+extern cpuop_func op_52d0_33_ff;
+extern cpuop_func op_52d8_33_nf;
+extern cpuop_func op_52d8_33_ff;
+extern cpuop_func op_52e0_33_nf;
+extern cpuop_func op_52e0_33_ff;
+extern cpuop_func op_52e8_33_nf;
+extern cpuop_func op_52e8_33_ff;
+extern cpuop_func op_52f0_33_nf;
+extern cpuop_func op_52f0_33_ff;
+extern cpuop_func op_52f8_33_nf;
+extern cpuop_func op_52f8_33_ff;
+extern cpuop_func op_52f9_33_nf;
+extern cpuop_func op_52f9_33_ff;
+extern cpuop_func op_52fa_33_nf;
+extern cpuop_func op_52fa_33_ff;
+extern cpuop_func op_52fb_33_nf;
+extern cpuop_func op_52fb_33_ff;
+extern cpuop_func op_52fc_33_nf;
+extern cpuop_func op_52fc_33_ff;
+extern cpuop_func op_53c0_33_nf;
+extern cpuop_func op_53c0_33_ff;
+extern cpuop_func op_53c8_33_nf;
+extern cpuop_func op_53c8_33_ff;
+extern cpuop_func op_53d0_33_nf;
+extern cpuop_func op_53d0_33_ff;
+extern cpuop_func op_53d8_33_nf;
+extern cpuop_func op_53d8_33_ff;
+extern cpuop_func op_53e0_33_nf;
+extern cpuop_func op_53e0_33_ff;
+extern cpuop_func op_53e8_33_nf;
+extern cpuop_func op_53e8_33_ff;
+extern cpuop_func op_53f0_33_nf;
+extern cpuop_func op_53f0_33_ff;
+extern cpuop_func op_53f8_33_nf;
+extern cpuop_func op_53f8_33_ff;
+extern cpuop_func op_53f9_33_nf;
+extern cpuop_func op_53f9_33_ff;
+extern cpuop_func op_53fa_33_nf;
+extern cpuop_func op_53fa_33_ff;
+extern cpuop_func op_53fb_33_nf;
+extern cpuop_func op_53fb_33_ff;
+extern cpuop_func op_53fc_33_nf;
+extern cpuop_func op_53fc_33_ff;
+extern cpuop_func op_54c0_33_nf;
+extern cpuop_func op_54c0_33_ff;
+extern cpuop_func op_54c8_33_nf;
+extern cpuop_func op_54c8_33_ff;
+extern cpuop_func op_54d0_33_nf;
+extern cpuop_func op_54d0_33_ff;
+extern cpuop_func op_54d8_33_nf;
+extern cpuop_func op_54d8_33_ff;
+extern cpuop_func op_54e0_33_nf;
+extern cpuop_func op_54e0_33_ff;
+extern cpuop_func op_54e8_33_nf;
+extern cpuop_func op_54e8_33_ff;
+extern cpuop_func op_54f0_33_nf;
+extern cpuop_func op_54f0_33_ff;
+extern cpuop_func op_54f8_33_nf;
+extern cpuop_func op_54f8_33_ff;
+extern cpuop_func op_54f9_33_nf;
+extern cpuop_func op_54f9_33_ff;
+extern cpuop_func op_54fa_33_nf;
+extern cpuop_func op_54fa_33_ff;
+extern cpuop_func op_54fb_33_nf;
+extern cpuop_func op_54fb_33_ff;
+extern cpuop_func op_54fc_33_nf;
+extern cpuop_func op_54fc_33_ff;
+extern cpuop_func op_55c0_33_nf;
+extern cpuop_func op_55c0_33_ff;
+extern cpuop_func op_55c8_33_nf;
+extern cpuop_func op_55c8_33_ff;
+extern cpuop_func op_55d0_33_nf;
+extern cpuop_func op_55d0_33_ff;
+extern cpuop_func op_55d8_33_nf;
+extern cpuop_func op_55d8_33_ff;
+extern cpuop_func op_55e0_33_nf;
+extern cpuop_func op_55e0_33_ff;
+extern cpuop_func op_55e8_33_nf;
+extern cpuop_func op_55e8_33_ff;
+extern cpuop_func op_55f0_33_nf;
+extern cpuop_func op_55f0_33_ff;
+extern cpuop_func op_55f8_33_nf;
+extern cpuop_func op_55f8_33_ff;
+extern cpuop_func op_55f9_33_nf;
+extern cpuop_func op_55f9_33_ff;
+extern cpuop_func op_55fa_33_nf;
+extern cpuop_func op_55fa_33_ff;
+extern cpuop_func op_55fb_33_nf;
+extern cpuop_func op_55fb_33_ff;
+extern cpuop_func op_55fc_33_nf;
+extern cpuop_func op_55fc_33_ff;
+extern cpuop_func op_56c0_33_nf;
+extern cpuop_func op_56c0_33_ff;
+extern cpuop_func op_56c8_33_nf;
+extern cpuop_func op_56c8_33_ff;
+extern cpuop_func op_56d0_33_nf;
+extern cpuop_func op_56d0_33_ff;
+extern cpuop_func op_56d8_33_nf;
+extern cpuop_func op_56d8_33_ff;
+extern cpuop_func op_56e0_33_nf;
+extern cpuop_func op_56e0_33_ff;
+extern cpuop_func op_56e8_33_nf;
+extern cpuop_func op_56e8_33_ff;
+extern cpuop_func op_56f0_33_nf;
+extern cpuop_func op_56f0_33_ff;
+extern cpuop_func op_56f8_33_nf;
+extern cpuop_func op_56f8_33_ff;
+extern cpuop_func op_56f9_33_nf;
+extern cpuop_func op_56f9_33_ff;
+extern cpuop_func op_56fa_33_nf;
+extern cpuop_func op_56fa_33_ff;
+extern cpuop_func op_56fb_33_nf;
+extern cpuop_func op_56fb_33_ff;
+extern cpuop_func op_56fc_33_nf;
+extern cpuop_func op_56fc_33_ff;
+extern cpuop_func op_57c0_33_nf;
+extern cpuop_func op_57c0_33_ff;
+extern cpuop_func op_57c8_33_nf;
+extern cpuop_func op_57c8_33_ff;
+extern cpuop_func op_57d0_33_nf;
+extern cpuop_func op_57d0_33_ff;
+extern cpuop_func op_57d8_33_nf;
+extern cpuop_func op_57d8_33_ff;
+extern cpuop_func op_57e0_33_nf;
+extern cpuop_func op_57e0_33_ff;
+extern cpuop_func op_57e8_33_nf;
+extern cpuop_func op_57e8_33_ff;
+extern cpuop_func op_57f0_33_nf;
+extern cpuop_func op_57f0_33_ff;
+extern cpuop_func op_57f8_33_nf;
+extern cpuop_func op_57f8_33_ff;
+extern cpuop_func op_57f9_33_nf;
+extern cpuop_func op_57f9_33_ff;
+extern cpuop_func op_57fa_33_nf;
+extern cpuop_func op_57fa_33_ff;
+extern cpuop_func op_57fb_33_nf;
+extern cpuop_func op_57fb_33_ff;
+extern cpuop_func op_57fc_33_nf;
+extern cpuop_func op_57fc_33_ff;
+extern cpuop_func op_58c0_33_nf;
+extern cpuop_func op_58c0_33_ff;
+extern cpuop_func op_58c8_33_nf;
+extern cpuop_func op_58c8_33_ff;
+extern cpuop_func op_58d0_33_nf;
+extern cpuop_func op_58d0_33_ff;
+extern cpuop_func op_58d8_33_nf;
+extern cpuop_func op_58d8_33_ff;
+extern cpuop_func op_58e0_33_nf;
+extern cpuop_func op_58e0_33_ff;
+extern cpuop_func op_58e8_33_nf;
+extern cpuop_func op_58e8_33_ff;
+extern cpuop_func op_58f0_33_nf;
+extern cpuop_func op_58f0_33_ff;
+extern cpuop_func op_58f8_33_nf;
+extern cpuop_func op_58f8_33_ff;
+extern cpuop_func op_58f9_33_nf;
+extern cpuop_func op_58f9_33_ff;
+extern cpuop_func op_58fa_33_nf;
+extern cpuop_func op_58fa_33_ff;
+extern cpuop_func op_58fb_33_nf;
+extern cpuop_func op_58fb_33_ff;
+extern cpuop_func op_58fc_33_nf;
+extern cpuop_func op_58fc_33_ff;
+extern cpuop_func op_59c0_33_nf;
+extern cpuop_func op_59c0_33_ff;
+extern cpuop_func op_59c8_33_nf;
+extern cpuop_func op_59c8_33_ff;
+extern cpuop_func op_59d0_33_nf;
+extern cpuop_func op_59d0_33_ff;
+extern cpuop_func op_59d8_33_nf;
+extern cpuop_func op_59d8_33_ff;
+extern cpuop_func op_59e0_33_nf;
+extern cpuop_func op_59e0_33_ff;
+extern cpuop_func op_59e8_33_nf;
+extern cpuop_func op_59e8_33_ff;
+extern cpuop_func op_59f0_33_nf;
+extern cpuop_func op_59f0_33_ff;
+extern cpuop_func op_59f8_33_nf;
+extern cpuop_func op_59f8_33_ff;
+extern cpuop_func op_59f9_33_nf;
+extern cpuop_func op_59f9_33_ff;
+extern cpuop_func op_59fa_33_nf;
+extern cpuop_func op_59fa_33_ff;
+extern cpuop_func op_59fb_33_nf;
+extern cpuop_func op_59fb_33_ff;
+extern cpuop_func op_59fc_33_nf;
+extern cpuop_func op_59fc_33_ff;
+extern cpuop_func op_5ac0_33_nf;
+extern cpuop_func op_5ac0_33_ff;
+extern cpuop_func op_5ac8_33_nf;
+extern cpuop_func op_5ac8_33_ff;
+extern cpuop_func op_5ad0_33_nf;
+extern cpuop_func op_5ad0_33_ff;
+extern cpuop_func op_5ad8_33_nf;
+extern cpuop_func op_5ad8_33_ff;
+extern cpuop_func op_5ae0_33_nf;
+extern cpuop_func op_5ae0_33_ff;
+extern cpuop_func op_5ae8_33_nf;
+extern cpuop_func op_5ae8_33_ff;
+extern cpuop_func op_5af0_33_nf;
+extern cpuop_func op_5af0_33_ff;
+extern cpuop_func op_5af8_33_nf;
+extern cpuop_func op_5af8_33_ff;
+extern cpuop_func op_5af9_33_nf;
+extern cpuop_func op_5af9_33_ff;
+extern cpuop_func op_5afa_33_nf;
+extern cpuop_func op_5afa_33_ff;
+extern cpuop_func op_5afb_33_nf;
+extern cpuop_func op_5afb_33_ff;
+extern cpuop_func op_5afc_33_nf;
+extern cpuop_func op_5afc_33_ff;
+extern cpuop_func op_5bc0_33_nf;
+extern cpuop_func op_5bc0_33_ff;
+extern cpuop_func op_5bc8_33_nf;
+extern cpuop_func op_5bc8_33_ff;
+extern cpuop_func op_5bd0_33_nf;
+extern cpuop_func op_5bd0_33_ff;
+extern cpuop_func op_5bd8_33_nf;
+extern cpuop_func op_5bd8_33_ff;
+extern cpuop_func op_5be0_33_nf;
+extern cpuop_func op_5be0_33_ff;
+extern cpuop_func op_5be8_33_nf;
+extern cpuop_func op_5be8_33_ff;
+extern cpuop_func op_5bf0_33_nf;
+extern cpuop_func op_5bf0_33_ff;
+extern cpuop_func op_5bf8_33_nf;
+extern cpuop_func op_5bf8_33_ff;
+extern cpuop_func op_5bf9_33_nf;
+extern cpuop_func op_5bf9_33_ff;
+extern cpuop_func op_5bfa_33_nf;
+extern cpuop_func op_5bfa_33_ff;
+extern cpuop_func op_5bfb_33_nf;
+extern cpuop_func op_5bfb_33_ff;
+extern cpuop_func op_5bfc_33_nf;
+extern cpuop_func op_5bfc_33_ff;
+extern cpuop_func op_5cc0_33_nf;
+extern cpuop_func op_5cc0_33_ff;
+extern cpuop_func op_5cc8_33_nf;
+extern cpuop_func op_5cc8_33_ff;
+extern cpuop_func op_5cd0_33_nf;
+extern cpuop_func op_5cd0_33_ff;
+extern cpuop_func op_5cd8_33_nf;
+extern cpuop_func op_5cd8_33_ff;
+extern cpuop_func op_5ce0_33_nf;
+extern cpuop_func op_5ce0_33_ff;
+extern cpuop_func op_5ce8_33_nf;
+extern cpuop_func op_5ce8_33_ff;
+extern cpuop_func op_5cf0_33_nf;
+extern cpuop_func op_5cf0_33_ff;
+extern cpuop_func op_5cf8_33_nf;
+extern cpuop_func op_5cf8_33_ff;
+extern cpuop_func op_5cf9_33_nf;
+extern cpuop_func op_5cf9_33_ff;
+extern cpuop_func op_5cfa_33_nf;
+extern cpuop_func op_5cfa_33_ff;
+extern cpuop_func op_5cfb_33_nf;
+extern cpuop_func op_5cfb_33_ff;
+extern cpuop_func op_5cfc_33_nf;
+extern cpuop_func op_5cfc_33_ff;
+extern cpuop_func op_5dc0_33_nf;
+extern cpuop_func op_5dc0_33_ff;
+extern cpuop_func op_5dc8_33_nf;
+extern cpuop_func op_5dc8_33_ff;
+extern cpuop_func op_5dd0_33_nf;
+extern cpuop_func op_5dd0_33_ff;
+extern cpuop_func op_5dd8_33_nf;
+extern cpuop_func op_5dd8_33_ff;
+extern cpuop_func op_5de0_33_nf;
+extern cpuop_func op_5de0_33_ff;
+extern cpuop_func op_5de8_33_nf;
+extern cpuop_func op_5de8_33_ff;
+extern cpuop_func op_5df0_33_nf;
+extern cpuop_func op_5df0_33_ff;
+extern cpuop_func op_5df8_33_nf;
+extern cpuop_func op_5df8_33_ff;
+extern cpuop_func op_5df9_33_nf;
+extern cpuop_func op_5df9_33_ff;
+extern cpuop_func op_5dfa_33_nf;
+extern cpuop_func op_5dfa_33_ff;
+extern cpuop_func op_5dfb_33_nf;
+extern cpuop_func op_5dfb_33_ff;
+extern cpuop_func op_5dfc_33_nf;
+extern cpuop_func op_5dfc_33_ff;
+extern cpuop_func op_5ec0_33_nf;
+extern cpuop_func op_5ec0_33_ff;
+extern cpuop_func op_5ec8_33_nf;
+extern cpuop_func op_5ec8_33_ff;
+extern cpuop_func op_5ed0_33_nf;
+extern cpuop_func op_5ed0_33_ff;
+extern cpuop_func op_5ed8_33_nf;
+extern cpuop_func op_5ed8_33_ff;
+extern cpuop_func op_5ee0_33_nf;
+extern cpuop_func op_5ee0_33_ff;
+extern cpuop_func op_5ee8_33_nf;
+extern cpuop_func op_5ee8_33_ff;
+extern cpuop_func op_5ef0_33_nf;
+extern cpuop_func op_5ef0_33_ff;
+extern cpuop_func op_5ef8_33_nf;
+extern cpuop_func op_5ef8_33_ff;
+extern cpuop_func op_5ef9_33_nf;
+extern cpuop_func op_5ef9_33_ff;
+extern cpuop_func op_5efa_33_nf;
+extern cpuop_func op_5efa_33_ff;
+extern cpuop_func op_5efb_33_nf;
+extern cpuop_func op_5efb_33_ff;
+extern cpuop_func op_5efc_33_nf;
+extern cpuop_func op_5efc_33_ff;
+extern cpuop_func op_5fc0_33_nf;
+extern cpuop_func op_5fc0_33_ff;
+extern cpuop_func op_5fc8_33_nf;
+extern cpuop_func op_5fc8_33_ff;
+extern cpuop_func op_5fd0_33_nf;
+extern cpuop_func op_5fd0_33_ff;
+extern cpuop_func op_5fd8_33_nf;
+extern cpuop_func op_5fd8_33_ff;
+extern cpuop_func op_5fe0_33_nf;
+extern cpuop_func op_5fe0_33_ff;
+extern cpuop_func op_5fe8_33_nf;
+extern cpuop_func op_5fe8_33_ff;
+extern cpuop_func op_5ff0_33_nf;
+extern cpuop_func op_5ff0_33_ff;
+extern cpuop_func op_5ff8_33_nf;
+extern cpuop_func op_5ff8_33_ff;
+extern cpuop_func op_5ff9_33_nf;
+extern cpuop_func op_5ff9_33_ff;
+extern cpuop_func op_5ffa_33_nf;
+extern cpuop_func op_5ffa_33_ff;
+extern cpuop_func op_5ffb_33_nf;
+extern cpuop_func op_5ffb_33_ff;
+extern cpuop_func op_5ffc_33_nf;
+extern cpuop_func op_5ffc_33_ff;
+extern cpuop_func op_6000_33_nf;
+extern cpuop_func op_6000_33_ff;
+extern cpuop_func op_6001_33_nf;
+extern cpuop_func op_6001_33_ff;
+extern cpuop_func op_60ff_33_nf;
+extern cpuop_func op_60ff_33_ff;
+extern cpuop_func op_6100_33_nf;
+extern cpuop_func op_6100_33_ff;
+extern cpuop_func op_6101_33_nf;
+extern cpuop_func op_6101_33_ff;
+extern cpuop_func op_61ff_33_nf;
+extern cpuop_func op_61ff_33_ff;
+extern cpuop_func op_6200_33_nf;
+extern cpuop_func op_6200_33_ff;
+extern cpuop_func op_6201_33_nf;
+extern cpuop_func op_6201_33_ff;
+extern cpuop_func op_62ff_33_nf;
+extern cpuop_func op_62ff_33_ff;
+extern cpuop_func op_6300_33_nf;
+extern cpuop_func op_6300_33_ff;
+extern cpuop_func op_6301_33_nf;
+extern cpuop_func op_6301_33_ff;
+extern cpuop_func op_63ff_33_nf;
+extern cpuop_func op_63ff_33_ff;
+extern cpuop_func op_6400_33_nf;
+extern cpuop_func op_6400_33_ff;
+extern cpuop_func op_6401_33_nf;
+extern cpuop_func op_6401_33_ff;
+extern cpuop_func op_64ff_33_nf;
+extern cpuop_func op_64ff_33_ff;
+extern cpuop_func op_6500_33_nf;
+extern cpuop_func op_6500_33_ff;
+extern cpuop_func op_6501_33_nf;
+extern cpuop_func op_6501_33_ff;
+extern cpuop_func op_65ff_33_nf;
+extern cpuop_func op_65ff_33_ff;
+extern cpuop_func op_6600_33_nf;
+extern cpuop_func op_6600_33_ff;
+extern cpuop_func op_6601_33_nf;
+extern cpuop_func op_6601_33_ff;
+extern cpuop_func op_66ff_33_nf;
+extern cpuop_func op_66ff_33_ff;
+extern cpuop_func op_6700_33_nf;
+extern cpuop_func op_6700_33_ff;
+extern cpuop_func op_6701_33_nf;
+extern cpuop_func op_6701_33_ff;
+extern cpuop_func op_67ff_33_nf;
+extern cpuop_func op_67ff_33_ff;
+extern cpuop_func op_6800_33_nf;
+extern cpuop_func op_6800_33_ff;
+extern cpuop_func op_6801_33_nf;
+extern cpuop_func op_6801_33_ff;
+extern cpuop_func op_68ff_33_nf;
+extern cpuop_func op_68ff_33_ff;
+extern cpuop_func op_6900_33_nf;
+extern cpuop_func op_6900_33_ff;
+extern cpuop_func op_6901_33_nf;
+extern cpuop_func op_6901_33_ff;
+extern cpuop_func op_69ff_33_nf;
+extern cpuop_func op_69ff_33_ff;
+extern cpuop_func op_6a00_33_nf;
+extern cpuop_func op_6a00_33_ff;
+extern cpuop_func op_6a01_33_nf;
+extern cpuop_func op_6a01_33_ff;
+extern cpuop_func op_6aff_33_nf;
+extern cpuop_func op_6aff_33_ff;
+extern cpuop_func op_6b00_33_nf;
+extern cpuop_func op_6b00_33_ff;
+extern cpuop_func op_6b01_33_nf;
+extern cpuop_func op_6b01_33_ff;
+extern cpuop_func op_6bff_33_nf;
+extern cpuop_func op_6bff_33_ff;
+extern cpuop_func op_6c00_33_nf;
+extern cpuop_func op_6c00_33_ff;
+extern cpuop_func op_6c01_33_nf;
+extern cpuop_func op_6c01_33_ff;
+extern cpuop_func op_6cff_33_nf;
+extern cpuop_func op_6cff_33_ff;
+extern cpuop_func op_6d00_33_nf;
+extern cpuop_func op_6d00_33_ff;
+extern cpuop_func op_6d01_33_nf;
+extern cpuop_func op_6d01_33_ff;
+extern cpuop_func op_6dff_33_nf;
+extern cpuop_func op_6dff_33_ff;
+extern cpuop_func op_6e00_33_nf;
+extern cpuop_func op_6e00_33_ff;
+extern cpuop_func op_6e01_33_nf;
+extern cpuop_func op_6e01_33_ff;
+extern cpuop_func op_6eff_33_nf;
+extern cpuop_func op_6eff_33_ff;
+extern cpuop_func op_6f00_33_nf;
+extern cpuop_func op_6f00_33_ff;
+extern cpuop_func op_6f01_33_nf;
+extern cpuop_func op_6f01_33_ff;
+extern cpuop_func op_6fff_33_nf;
+extern cpuop_func op_6fff_33_ff;
+extern cpuop_func op_7000_33_nf;
+extern cpuop_func op_7000_33_ff;
+extern cpuop_func op_8000_33_nf;
+extern cpuop_func op_8000_33_ff;
+extern cpuop_func op_8010_33_nf;
+extern cpuop_func op_8010_33_ff;
+extern cpuop_func op_8018_33_nf;
+extern cpuop_func op_8018_33_ff;
+extern cpuop_func op_8020_33_nf;
+extern cpuop_func op_8020_33_ff;
+extern cpuop_func op_8028_33_nf;
+extern cpuop_func op_8028_33_ff;
+extern cpuop_func op_8030_33_nf;
+extern cpuop_func op_8030_33_ff;
+extern cpuop_func op_8038_33_nf;
+extern cpuop_func op_8038_33_ff;
+extern cpuop_func op_8039_33_nf;
+extern cpuop_func op_8039_33_ff;
+extern cpuop_func op_803a_33_nf;
+extern cpuop_func op_803a_33_ff;
+extern cpuop_func op_803b_33_nf;
+extern cpuop_func op_803b_33_ff;
+extern cpuop_func op_803c_33_nf;
+extern cpuop_func op_803c_33_ff;
+extern cpuop_func op_8040_33_nf;
+extern cpuop_func op_8040_33_ff;
+extern cpuop_func op_8050_33_nf;
+extern cpuop_func op_8050_33_ff;
+extern cpuop_func op_8058_33_nf;
+extern cpuop_func op_8058_33_ff;
+extern cpuop_func op_8060_33_nf;
+extern cpuop_func op_8060_33_ff;
+extern cpuop_func op_8068_33_nf;
+extern cpuop_func op_8068_33_ff;
+extern cpuop_func op_8070_33_nf;
+extern cpuop_func op_8070_33_ff;
+extern cpuop_func op_8078_33_nf;
+extern cpuop_func op_8078_33_ff;
+extern cpuop_func op_8079_33_nf;
+extern cpuop_func op_8079_33_ff;
+extern cpuop_func op_807a_33_nf;
+extern cpuop_func op_807a_33_ff;
+extern cpuop_func op_807b_33_nf;
+extern cpuop_func op_807b_33_ff;
+extern cpuop_func op_807c_33_nf;
+extern cpuop_func op_807c_33_ff;
+extern cpuop_func op_8080_33_nf;
+extern cpuop_func op_8080_33_ff;
+extern cpuop_func op_8090_33_nf;
+extern cpuop_func op_8090_33_ff;
+extern cpuop_func op_8098_33_nf;
+extern cpuop_func op_8098_33_ff;
+extern cpuop_func op_80a0_33_nf;
+extern cpuop_func op_80a0_33_ff;
+extern cpuop_func op_80a8_33_nf;
+extern cpuop_func op_80a8_33_ff;
+extern cpuop_func op_80b0_33_nf;
+extern cpuop_func op_80b0_33_ff;
+extern cpuop_func op_80b8_33_nf;
+extern cpuop_func op_80b8_33_ff;
+extern cpuop_func op_80b9_33_nf;
+extern cpuop_func op_80b9_33_ff;
+extern cpuop_func op_80ba_33_nf;
+extern cpuop_func op_80ba_33_ff;
+extern cpuop_func op_80bb_33_nf;
+extern cpuop_func op_80bb_33_ff;
+extern cpuop_func op_80bc_33_nf;
+extern cpuop_func op_80bc_33_ff;
+extern cpuop_func op_80c0_33_nf;
+extern cpuop_func op_80c0_33_ff;
+extern cpuop_func op_80d0_33_nf;
+extern cpuop_func op_80d0_33_ff;
+extern cpuop_func op_80d8_33_nf;
+extern cpuop_func op_80d8_33_ff;
+extern cpuop_func op_80e0_33_nf;
+extern cpuop_func op_80e0_33_ff;
+extern cpuop_func op_80e8_33_nf;
+extern cpuop_func op_80e8_33_ff;
+extern cpuop_func op_80f0_33_nf;
+extern cpuop_func op_80f0_33_ff;
+extern cpuop_func op_80f8_33_nf;
+extern cpuop_func op_80f8_33_ff;
+extern cpuop_func op_80f9_33_nf;
+extern cpuop_func op_80f9_33_ff;
+extern cpuop_func op_80fa_33_nf;
+extern cpuop_func op_80fa_33_ff;
+extern cpuop_func op_80fb_33_nf;
+extern cpuop_func op_80fb_33_ff;
+extern cpuop_func op_80fc_33_nf;
+extern cpuop_func op_80fc_33_ff;
+extern cpuop_func op_8100_33_nf;
+extern cpuop_func op_8100_33_ff;
+extern cpuop_func op_8108_33_nf;
+extern cpuop_func op_8108_33_ff;
+extern cpuop_func op_8110_33_nf;
+extern cpuop_func op_8110_33_ff;
+extern cpuop_func op_8118_33_nf;
+extern cpuop_func op_8118_33_ff;
+extern cpuop_func op_8120_33_nf;
+extern cpuop_func op_8120_33_ff;
+extern cpuop_func op_8128_33_nf;
+extern cpuop_func op_8128_33_ff;
+extern cpuop_func op_8130_33_nf;
+extern cpuop_func op_8130_33_ff;
+extern cpuop_func op_8138_33_nf;
+extern cpuop_func op_8138_33_ff;
+extern cpuop_func op_8139_33_nf;
+extern cpuop_func op_8139_33_ff;
+extern cpuop_func op_8140_33_nf;
+extern cpuop_func op_8140_33_ff;
+extern cpuop_func op_8148_33_nf;
+extern cpuop_func op_8148_33_ff;
+extern cpuop_func op_8150_33_nf;
+extern cpuop_func op_8150_33_ff;
+extern cpuop_func op_8158_33_nf;
+extern cpuop_func op_8158_33_ff;
+extern cpuop_func op_8160_33_nf;
+extern cpuop_func op_8160_33_ff;
+extern cpuop_func op_8168_33_nf;
+extern cpuop_func op_8168_33_ff;
+extern cpuop_func op_8170_33_nf;
+extern cpuop_func op_8170_33_ff;
+extern cpuop_func op_8178_33_nf;
+extern cpuop_func op_8178_33_ff;
+extern cpuop_func op_8179_33_nf;
+extern cpuop_func op_8179_33_ff;
+extern cpuop_func op_8180_33_nf;
+extern cpuop_func op_8180_33_ff;
+extern cpuop_func op_8188_33_nf;
+extern cpuop_func op_8188_33_ff;
+extern cpuop_func op_8190_33_nf;
+extern cpuop_func op_8190_33_ff;
+extern cpuop_func op_8198_33_nf;
+extern cpuop_func op_8198_33_ff;
+extern cpuop_func op_81a0_33_nf;
+extern cpuop_func op_81a0_33_ff;
+extern cpuop_func op_81a8_33_nf;
+extern cpuop_func op_81a8_33_ff;
+extern cpuop_func op_81b0_33_nf;
+extern cpuop_func op_81b0_33_ff;
+extern cpuop_func op_81b8_33_nf;
+extern cpuop_func op_81b8_33_ff;
+extern cpuop_func op_81b9_33_nf;
+extern cpuop_func op_81b9_33_ff;
+extern cpuop_func op_81c0_33_nf;
+extern cpuop_func op_81c0_33_ff;
+extern cpuop_func op_81d0_33_nf;
+extern cpuop_func op_81d0_33_ff;
+extern cpuop_func op_81d8_33_nf;
+extern cpuop_func op_81d8_33_ff;
+extern cpuop_func op_81e0_33_nf;
+extern cpuop_func op_81e0_33_ff;
+extern cpuop_func op_81e8_33_nf;
+extern cpuop_func op_81e8_33_ff;
+extern cpuop_func op_81f0_33_nf;
+extern cpuop_func op_81f0_33_ff;
+extern cpuop_func op_81f8_33_nf;
+extern cpuop_func op_81f8_33_ff;
+extern cpuop_func op_81f9_33_nf;
+extern cpuop_func op_81f9_33_ff;
+extern cpuop_func op_81fa_33_nf;
+extern cpuop_func op_81fa_33_ff;
+extern cpuop_func op_81fb_33_nf;
+extern cpuop_func op_81fb_33_ff;
+extern cpuop_func op_81fc_33_nf;
+extern cpuop_func op_81fc_33_ff;
+extern cpuop_func op_9000_33_nf;
+extern cpuop_func op_9000_33_ff;
+extern cpuop_func op_9010_33_nf;
+extern cpuop_func op_9010_33_ff;
+extern cpuop_func op_9018_33_nf;
+extern cpuop_func op_9018_33_ff;
+extern cpuop_func op_9020_33_nf;
+extern cpuop_func op_9020_33_ff;
+extern cpuop_func op_9028_33_nf;
+extern cpuop_func op_9028_33_ff;
+extern cpuop_func op_9030_33_nf;
+extern cpuop_func op_9030_33_ff;
+extern cpuop_func op_9038_33_nf;
+extern cpuop_func op_9038_33_ff;
+extern cpuop_func op_9039_33_nf;
+extern cpuop_func op_9039_33_ff;
+extern cpuop_func op_903a_33_nf;
+extern cpuop_func op_903a_33_ff;
+extern cpuop_func op_903b_33_nf;
+extern cpuop_func op_903b_33_ff;
+extern cpuop_func op_903c_33_nf;
+extern cpuop_func op_903c_33_ff;
+extern cpuop_func op_9040_33_nf;
+extern cpuop_func op_9040_33_ff;
+extern cpuop_func op_9048_33_nf;
+extern cpuop_func op_9048_33_ff;
+extern cpuop_func op_9050_33_nf;
+extern cpuop_func op_9050_33_ff;
+extern cpuop_func op_9058_33_nf;
+extern cpuop_func op_9058_33_ff;
+extern cpuop_func op_9060_33_nf;
+extern cpuop_func op_9060_33_ff;
+extern cpuop_func op_9068_33_nf;
+extern cpuop_func op_9068_33_ff;
+extern cpuop_func op_9070_33_nf;
+extern cpuop_func op_9070_33_ff;
+extern cpuop_func op_9078_33_nf;
+extern cpuop_func op_9078_33_ff;
+extern cpuop_func op_9079_33_nf;
+extern cpuop_func op_9079_33_ff;
+extern cpuop_func op_907a_33_nf;
+extern cpuop_func op_907a_33_ff;
+extern cpuop_func op_907b_33_nf;
+extern cpuop_func op_907b_33_ff;
+extern cpuop_func op_907c_33_nf;
+extern cpuop_func op_907c_33_ff;
+extern cpuop_func op_9080_33_nf;
+extern cpuop_func op_9080_33_ff;
+extern cpuop_func op_9088_33_nf;
+extern cpuop_func op_9088_33_ff;
+extern cpuop_func op_9090_33_nf;
+extern cpuop_func op_9090_33_ff;
+extern cpuop_func op_9098_33_nf;
+extern cpuop_func op_9098_33_ff;
+extern cpuop_func op_90a0_33_nf;
+extern cpuop_func op_90a0_33_ff;
+extern cpuop_func op_90a8_33_nf;
+extern cpuop_func op_90a8_33_ff;
+extern cpuop_func op_90b0_33_nf;
+extern cpuop_func op_90b0_33_ff;
+extern cpuop_func op_90b8_33_nf;
+extern cpuop_func op_90b8_33_ff;
+extern cpuop_func op_90b9_33_nf;
+extern cpuop_func op_90b9_33_ff;
+extern cpuop_func op_90ba_33_nf;
+extern cpuop_func op_90ba_33_ff;
+extern cpuop_func op_90bb_33_nf;
+extern cpuop_func op_90bb_33_ff;
+extern cpuop_func op_90bc_33_nf;
+extern cpuop_func op_90bc_33_ff;
+extern cpuop_func op_90c0_33_nf;
+extern cpuop_func op_90c0_33_ff;
+extern cpuop_func op_90c8_33_nf;
+extern cpuop_func op_90c8_33_ff;
+extern cpuop_func op_90d0_33_nf;
+extern cpuop_func op_90d0_33_ff;
+extern cpuop_func op_90d8_33_nf;
+extern cpuop_func op_90d8_33_ff;
+extern cpuop_func op_90e0_33_nf;
+extern cpuop_func op_90e0_33_ff;
+extern cpuop_func op_90e8_33_nf;
+extern cpuop_func op_90e8_33_ff;
+extern cpuop_func op_90f0_33_nf;
+extern cpuop_func op_90f0_33_ff;
+extern cpuop_func op_90f8_33_nf;
+extern cpuop_func op_90f8_33_ff;
+extern cpuop_func op_90f9_33_nf;
+extern cpuop_func op_90f9_33_ff;
+extern cpuop_func op_90fa_33_nf;
+extern cpuop_func op_90fa_33_ff;
+extern cpuop_func op_90fb_33_nf;
+extern cpuop_func op_90fb_33_ff;
+extern cpuop_func op_90fc_33_nf;
+extern cpuop_func op_90fc_33_ff;
+extern cpuop_func op_9100_33_nf;
+extern cpuop_func op_9100_33_ff;
+extern cpuop_func op_9108_33_nf;
+extern cpuop_func op_9108_33_ff;
+extern cpuop_func op_9110_33_nf;
+extern cpuop_func op_9110_33_ff;
+extern cpuop_func op_9118_33_nf;
+extern cpuop_func op_9118_33_ff;
+extern cpuop_func op_9120_33_nf;
+extern cpuop_func op_9120_33_ff;
+extern cpuop_func op_9128_33_nf;
+extern cpuop_func op_9128_33_ff;
+extern cpuop_func op_9130_33_nf;
+extern cpuop_func op_9130_33_ff;
+extern cpuop_func op_9138_33_nf;
+extern cpuop_func op_9138_33_ff;
+extern cpuop_func op_9139_33_nf;
+extern cpuop_func op_9139_33_ff;
+extern cpuop_func op_9140_33_nf;
+extern cpuop_func op_9140_33_ff;
+extern cpuop_func op_9148_33_nf;
+extern cpuop_func op_9148_33_ff;
+extern cpuop_func op_9150_33_nf;
+extern cpuop_func op_9150_33_ff;
+extern cpuop_func op_9158_33_nf;
+extern cpuop_func op_9158_33_ff;
+extern cpuop_func op_9160_33_nf;
+extern cpuop_func op_9160_33_ff;
+extern cpuop_func op_9168_33_nf;
+extern cpuop_func op_9168_33_ff;
+extern cpuop_func op_9170_33_nf;
+extern cpuop_func op_9170_33_ff;
+extern cpuop_func op_9178_33_nf;
+extern cpuop_func op_9178_33_ff;
+extern cpuop_func op_9179_33_nf;
+extern cpuop_func op_9179_33_ff;
+extern cpuop_func op_9180_33_nf;
+extern cpuop_func op_9180_33_ff;
+extern cpuop_func op_9188_33_nf;
+extern cpuop_func op_9188_33_ff;
+extern cpuop_func op_9190_33_nf;
+extern cpuop_func op_9190_33_ff;
+extern cpuop_func op_9198_33_nf;
+extern cpuop_func op_9198_33_ff;
+extern cpuop_func op_91a0_33_nf;
+extern cpuop_func op_91a0_33_ff;
+extern cpuop_func op_91a8_33_nf;
+extern cpuop_func op_91a8_33_ff;
+extern cpuop_func op_91b0_33_nf;
+extern cpuop_func op_91b0_33_ff;
+extern cpuop_func op_91b8_33_nf;
+extern cpuop_func op_91b8_33_ff;
+extern cpuop_func op_91b9_33_nf;
+extern cpuop_func op_91b9_33_ff;
+extern cpuop_func op_91c0_33_nf;
+extern cpuop_func op_91c0_33_ff;
+extern cpuop_func op_91c8_33_nf;
+extern cpuop_func op_91c8_33_ff;
+extern cpuop_func op_91d0_33_nf;
+extern cpuop_func op_91d0_33_ff;
+extern cpuop_func op_91d8_33_nf;
+extern cpuop_func op_91d8_33_ff;
+extern cpuop_func op_91e0_33_nf;
+extern cpuop_func op_91e0_33_ff;
+extern cpuop_func op_91e8_33_nf;
+extern cpuop_func op_91e8_33_ff;
+extern cpuop_func op_91f0_33_nf;
+extern cpuop_func op_91f0_33_ff;
+extern cpuop_func op_91f8_33_nf;
+extern cpuop_func op_91f8_33_ff;
+extern cpuop_func op_91f9_33_nf;
+extern cpuop_func op_91f9_33_ff;
+extern cpuop_func op_91fa_33_nf;
+extern cpuop_func op_91fa_33_ff;
+extern cpuop_func op_91fb_33_nf;
+extern cpuop_func op_91fb_33_ff;
+extern cpuop_func op_91fc_33_nf;
+extern cpuop_func op_91fc_33_ff;
+extern cpuop_func op_b000_33_nf;
+extern cpuop_func op_b000_33_ff;
+extern cpuop_func op_b010_33_nf;
+extern cpuop_func op_b010_33_ff;
+extern cpuop_func op_b018_33_nf;
+extern cpuop_func op_b018_33_ff;
+extern cpuop_func op_b020_33_nf;
+extern cpuop_func op_b020_33_ff;
+extern cpuop_func op_b028_33_nf;
+extern cpuop_func op_b028_33_ff;
+extern cpuop_func op_b030_33_nf;
+extern cpuop_func op_b030_33_ff;
+extern cpuop_func op_b038_33_nf;
+extern cpuop_func op_b038_33_ff;
+extern cpuop_func op_b039_33_nf;
+extern cpuop_func op_b039_33_ff;
+extern cpuop_func op_b03a_33_nf;
+extern cpuop_func op_b03a_33_ff;
+extern cpuop_func op_b03b_33_nf;
+extern cpuop_func op_b03b_33_ff;
+extern cpuop_func op_b03c_33_nf;
+extern cpuop_func op_b03c_33_ff;
+extern cpuop_func op_b040_33_nf;
+extern cpuop_func op_b040_33_ff;
+extern cpuop_func op_b048_33_nf;
+extern cpuop_func op_b048_33_ff;
+extern cpuop_func op_b050_33_nf;
+extern cpuop_func op_b050_33_ff;
+extern cpuop_func op_b058_33_nf;
+extern cpuop_func op_b058_33_ff;
+extern cpuop_func op_b060_33_nf;
+extern cpuop_func op_b060_33_ff;
+extern cpuop_func op_b068_33_nf;
+extern cpuop_func op_b068_33_ff;
+extern cpuop_func op_b070_33_nf;
+extern cpuop_func op_b070_33_ff;
+extern cpuop_func op_b078_33_nf;
+extern cpuop_func op_b078_33_ff;
+extern cpuop_func op_b079_33_nf;
+extern cpuop_func op_b079_33_ff;
+extern cpuop_func op_b07a_33_nf;
+extern cpuop_func op_b07a_33_ff;
+extern cpuop_func op_b07b_33_nf;
+extern cpuop_func op_b07b_33_ff;
+extern cpuop_func op_b07c_33_nf;
+extern cpuop_func op_b07c_33_ff;
+extern cpuop_func op_b080_33_nf;
+extern cpuop_func op_b080_33_ff;
+extern cpuop_func op_b088_33_nf;
+extern cpuop_func op_b088_33_ff;
+extern cpuop_func op_b090_33_nf;
+extern cpuop_func op_b090_33_ff;
+extern cpuop_func op_b098_33_nf;
+extern cpuop_func op_b098_33_ff;
+extern cpuop_func op_b0a0_33_nf;
+extern cpuop_func op_b0a0_33_ff;
+extern cpuop_func op_b0a8_33_nf;
+extern cpuop_func op_b0a8_33_ff;
+extern cpuop_func op_b0b0_33_nf;
+extern cpuop_func op_b0b0_33_ff;
+extern cpuop_func op_b0b8_33_nf;
+extern cpuop_func op_b0b8_33_ff;
+extern cpuop_func op_b0b9_33_nf;
+extern cpuop_func op_b0b9_33_ff;
+extern cpuop_func op_b0ba_33_nf;
+extern cpuop_func op_b0ba_33_ff;
+extern cpuop_func op_b0bb_33_nf;
+extern cpuop_func op_b0bb_33_ff;
+extern cpuop_func op_b0bc_33_nf;
+extern cpuop_func op_b0bc_33_ff;
+extern cpuop_func op_b0c0_33_nf;
+extern cpuop_func op_b0c0_33_ff;
+extern cpuop_func op_b0c8_33_nf;
+extern cpuop_func op_b0c8_33_ff;
+extern cpuop_func op_b0d0_33_nf;
+extern cpuop_func op_b0d0_33_ff;
+extern cpuop_func op_b0d8_33_nf;
+extern cpuop_func op_b0d8_33_ff;
+extern cpuop_func op_b0e0_33_nf;
+extern cpuop_func op_b0e0_33_ff;
+extern cpuop_func op_b0e8_33_nf;
+extern cpuop_func op_b0e8_33_ff;
+extern cpuop_func op_b0f0_33_nf;
+extern cpuop_func op_b0f0_33_ff;
+extern cpuop_func op_b0f8_33_nf;
+extern cpuop_func op_b0f8_33_ff;
+extern cpuop_func op_b0f9_33_nf;
+extern cpuop_func op_b0f9_33_ff;
+extern cpuop_func op_b0fa_33_nf;
+extern cpuop_func op_b0fa_33_ff;
+extern cpuop_func op_b0fb_33_nf;
+extern cpuop_func op_b0fb_33_ff;
+extern cpuop_func op_b0fc_33_nf;
+extern cpuop_func op_b0fc_33_ff;
+extern cpuop_func op_b100_33_nf;
+extern cpuop_func op_b100_33_ff;
+extern cpuop_func op_b108_33_nf;
+extern cpuop_func op_b108_33_ff;
+extern cpuop_func op_b110_33_nf;
+extern cpuop_func op_b110_33_ff;
+extern cpuop_func op_b118_33_nf;
+extern cpuop_func op_b118_33_ff;
+extern cpuop_func op_b120_33_nf;
+extern cpuop_func op_b120_33_ff;
+extern cpuop_func op_b128_33_nf;
+extern cpuop_func op_b128_33_ff;
+extern cpuop_func op_b130_33_nf;
+extern cpuop_func op_b130_33_ff;
+extern cpuop_func op_b138_33_nf;
+extern cpuop_func op_b138_33_ff;
+extern cpuop_func op_b139_33_nf;
+extern cpuop_func op_b139_33_ff;
+extern cpuop_func op_b140_33_nf;
+extern cpuop_func op_b140_33_ff;
+extern cpuop_func op_b148_33_nf;
+extern cpuop_func op_b148_33_ff;
+extern cpuop_func op_b150_33_nf;
+extern cpuop_func op_b150_33_ff;
+extern cpuop_func op_b158_33_nf;
+extern cpuop_func op_b158_33_ff;
+extern cpuop_func op_b160_33_nf;
+extern cpuop_func op_b160_33_ff;
+extern cpuop_func op_b168_33_nf;
+extern cpuop_func op_b168_33_ff;
+extern cpuop_func op_b170_33_nf;
+extern cpuop_func op_b170_33_ff;
+extern cpuop_func op_b178_33_nf;
+extern cpuop_func op_b178_33_ff;
+extern cpuop_func op_b179_33_nf;
+extern cpuop_func op_b179_33_ff;
+extern cpuop_func op_b180_33_nf;
+extern cpuop_func op_b180_33_ff;
+extern cpuop_func op_b188_33_nf;
+extern cpuop_func op_b188_33_ff;
+extern cpuop_func op_b190_33_nf;
+extern cpuop_func op_b190_33_ff;
+extern cpuop_func op_b198_33_nf;
+extern cpuop_func op_b198_33_ff;
+extern cpuop_func op_b1a0_33_nf;
+extern cpuop_func op_b1a0_33_ff;
+extern cpuop_func op_b1a8_33_nf;
+extern cpuop_func op_b1a8_33_ff;
+extern cpuop_func op_b1b0_33_nf;
+extern cpuop_func op_b1b0_33_ff;
+extern cpuop_func op_b1b8_33_nf;
+extern cpuop_func op_b1b8_33_ff;
+extern cpuop_func op_b1b9_33_nf;
+extern cpuop_func op_b1b9_33_ff;
+extern cpuop_func op_b1c0_33_nf;
+extern cpuop_func op_b1c0_33_ff;
+extern cpuop_func op_b1c8_33_nf;
+extern cpuop_func op_b1c8_33_ff;
+extern cpuop_func op_b1d0_33_nf;
+extern cpuop_func op_b1d0_33_ff;
+extern cpuop_func op_b1d8_33_nf;
+extern cpuop_func op_b1d8_33_ff;
+extern cpuop_func op_b1e0_33_nf;
+extern cpuop_func op_b1e0_33_ff;
+extern cpuop_func op_b1e8_33_nf;
+extern cpuop_func op_b1e8_33_ff;
+extern cpuop_func op_b1f0_33_nf;
+extern cpuop_func op_b1f0_33_ff;
+extern cpuop_func op_b1f8_33_nf;
+extern cpuop_func op_b1f8_33_ff;
+extern cpuop_func op_b1f9_33_nf;
+extern cpuop_func op_b1f9_33_ff;
+extern cpuop_func op_b1fa_33_nf;
+extern cpuop_func op_b1fa_33_ff;
+extern cpuop_func op_b1fb_33_nf;
+extern cpuop_func op_b1fb_33_ff;
+extern cpuop_func op_b1fc_33_nf;
+extern cpuop_func op_b1fc_33_ff;
+extern cpuop_func op_c000_33_nf;
+extern cpuop_func op_c000_33_ff;
+extern cpuop_func op_c010_33_nf;
+extern cpuop_func op_c010_33_ff;
+extern cpuop_func op_c018_33_nf;
+extern cpuop_func op_c018_33_ff;
+extern cpuop_func op_c020_33_nf;
+extern cpuop_func op_c020_33_ff;
+extern cpuop_func op_c028_33_nf;
+extern cpuop_func op_c028_33_ff;
+extern cpuop_func op_c030_33_nf;
+extern cpuop_func op_c030_33_ff;
+extern cpuop_func op_c038_33_nf;
+extern cpuop_func op_c038_33_ff;
+extern cpuop_func op_c039_33_nf;
+extern cpuop_func op_c039_33_ff;
+extern cpuop_func op_c03a_33_nf;
+extern cpuop_func op_c03a_33_ff;
+extern cpuop_func op_c03b_33_nf;
+extern cpuop_func op_c03b_33_ff;
+extern cpuop_func op_c03c_33_nf;
+extern cpuop_func op_c03c_33_ff;
+extern cpuop_func op_c040_33_nf;
+extern cpuop_func op_c040_33_ff;
+extern cpuop_func op_c050_33_nf;
+extern cpuop_func op_c050_33_ff;
+extern cpuop_func op_c058_33_nf;
+extern cpuop_func op_c058_33_ff;
+extern cpuop_func op_c060_33_nf;
+extern cpuop_func op_c060_33_ff;
+extern cpuop_func op_c068_33_nf;
+extern cpuop_func op_c068_33_ff;
+extern cpuop_func op_c070_33_nf;
+extern cpuop_func op_c070_33_ff;
+extern cpuop_func op_c078_33_nf;
+extern cpuop_func op_c078_33_ff;
+extern cpuop_func op_c079_33_nf;
+extern cpuop_func op_c079_33_ff;
+extern cpuop_func op_c07a_33_nf;
+extern cpuop_func op_c07a_33_ff;
+extern cpuop_func op_c07b_33_nf;
+extern cpuop_func op_c07b_33_ff;
+extern cpuop_func op_c07c_33_nf;
+extern cpuop_func op_c07c_33_ff;
+extern cpuop_func op_c080_33_nf;
+extern cpuop_func op_c080_33_ff;
+extern cpuop_func op_c090_33_nf;
+extern cpuop_func op_c090_33_ff;
+extern cpuop_func op_c098_33_nf;
+extern cpuop_func op_c098_33_ff;
+extern cpuop_func op_c0a0_33_nf;
+extern cpuop_func op_c0a0_33_ff;
+extern cpuop_func op_c0a8_33_nf;
+extern cpuop_func op_c0a8_33_ff;
+extern cpuop_func op_c0b0_33_nf;
+extern cpuop_func op_c0b0_33_ff;
+extern cpuop_func op_c0b8_33_nf;
+extern cpuop_func op_c0b8_33_ff;
+extern cpuop_func op_c0b9_33_nf;
+extern cpuop_func op_c0b9_33_ff;
+extern cpuop_func op_c0ba_33_nf;
+extern cpuop_func op_c0ba_33_ff;
+extern cpuop_func op_c0bb_33_nf;
+extern cpuop_func op_c0bb_33_ff;
+extern cpuop_func op_c0bc_33_nf;
+extern cpuop_func op_c0bc_33_ff;
+extern cpuop_func op_c0c0_33_nf;
+extern cpuop_func op_c0c0_33_ff;
+extern cpuop_func op_c0d0_33_nf;
+extern cpuop_func op_c0d0_33_ff;
+extern cpuop_func op_c0d8_33_nf;
+extern cpuop_func op_c0d8_33_ff;
+extern cpuop_func op_c0e0_33_nf;
+extern cpuop_func op_c0e0_33_ff;
+extern cpuop_func op_c0e8_33_nf;
+extern cpuop_func op_c0e8_33_ff;
+extern cpuop_func op_c0f0_33_nf;
+extern cpuop_func op_c0f0_33_ff;
+extern cpuop_func op_c0f8_33_nf;
+extern cpuop_func op_c0f8_33_ff;
+extern cpuop_func op_c0f9_33_nf;
+extern cpuop_func op_c0f9_33_ff;
+extern cpuop_func op_c0fa_33_nf;
+extern cpuop_func op_c0fa_33_ff;
+extern cpuop_func op_c0fb_33_nf;
+extern cpuop_func op_c0fb_33_ff;
+extern cpuop_func op_c0fc_33_nf;
+extern cpuop_func op_c0fc_33_ff;
+extern cpuop_func op_c100_33_nf;
+extern cpuop_func op_c100_33_ff;
+extern cpuop_func op_c108_33_nf;
+extern cpuop_func op_c108_33_ff;
+extern cpuop_func op_c110_33_nf;
+extern cpuop_func op_c110_33_ff;
+extern cpuop_func op_c118_33_nf;
+extern cpuop_func op_c118_33_ff;
+extern cpuop_func op_c120_33_nf;
+extern cpuop_func op_c120_33_ff;
+extern cpuop_func op_c128_33_nf;
+extern cpuop_func op_c128_33_ff;
+extern cpuop_func op_c130_33_nf;
+extern cpuop_func op_c130_33_ff;
+extern cpuop_func op_c138_33_nf;
+extern cpuop_func op_c138_33_ff;
+extern cpuop_func op_c139_33_nf;
+extern cpuop_func op_c139_33_ff;
+extern cpuop_func op_c140_33_nf;
+extern cpuop_func op_c140_33_ff;
+extern cpuop_func op_c148_33_nf;
+extern cpuop_func op_c148_33_ff;
+extern cpuop_func op_c150_33_nf;
+extern cpuop_func op_c150_33_ff;
+extern cpuop_func op_c158_33_nf;
+extern cpuop_func op_c158_33_ff;
+extern cpuop_func op_c160_33_nf;
+extern cpuop_func op_c160_33_ff;
+extern cpuop_func op_c168_33_nf;
+extern cpuop_func op_c168_33_ff;
+extern cpuop_func op_c170_33_nf;
+extern cpuop_func op_c170_33_ff;
+extern cpuop_func op_c178_33_nf;
+extern cpuop_func op_c178_33_ff;
+extern cpuop_func op_c179_33_nf;
+extern cpuop_func op_c179_33_ff;
+extern cpuop_func op_c188_33_nf;
+extern cpuop_func op_c188_33_ff;
+extern cpuop_func op_c190_33_nf;
+extern cpuop_func op_c190_33_ff;
+extern cpuop_func op_c198_33_nf;
+extern cpuop_func op_c198_33_ff;
+extern cpuop_func op_c1a0_33_nf;
+extern cpuop_func op_c1a0_33_ff;
+extern cpuop_func op_c1a8_33_nf;
+extern cpuop_func op_c1a8_33_ff;
+extern cpuop_func op_c1b0_33_nf;
+extern cpuop_func op_c1b0_33_ff;
+extern cpuop_func op_c1b8_33_nf;
+extern cpuop_func op_c1b8_33_ff;
+extern cpuop_func op_c1b9_33_nf;
+extern cpuop_func op_c1b9_33_ff;
+extern cpuop_func op_c1c0_33_nf;
+extern cpuop_func op_c1c0_33_ff;
+extern cpuop_func op_c1d0_33_nf;
+extern cpuop_func op_c1d0_33_ff;
+extern cpuop_func op_c1d8_33_nf;
+extern cpuop_func op_c1d8_33_ff;
+extern cpuop_func op_c1e0_33_nf;
+extern cpuop_func op_c1e0_33_ff;
+extern cpuop_func op_c1e8_33_nf;
+extern cpuop_func op_c1e8_33_ff;
+extern cpuop_func op_c1f0_33_nf;
+extern cpuop_func op_c1f0_33_ff;
+extern cpuop_func op_c1f8_33_nf;
+extern cpuop_func op_c1f8_33_ff;
+extern cpuop_func op_c1f9_33_nf;
+extern cpuop_func op_c1f9_33_ff;
+extern cpuop_func op_c1fa_33_nf;
+extern cpuop_func op_c1fa_33_ff;
+extern cpuop_func op_c1fb_33_nf;
+extern cpuop_func op_c1fb_33_ff;
+extern cpuop_func op_c1fc_33_nf;
+extern cpuop_func op_c1fc_33_ff;
+extern cpuop_func op_d000_33_nf;
+extern cpuop_func op_d000_33_ff;
+extern cpuop_func op_d010_33_nf;
+extern cpuop_func op_d010_33_ff;
+extern cpuop_func op_d018_33_nf;
+extern cpuop_func op_d018_33_ff;
+extern cpuop_func op_d020_33_nf;
+extern cpuop_func op_d020_33_ff;
+extern cpuop_func op_d028_33_nf;
+extern cpuop_func op_d028_33_ff;
+extern cpuop_func op_d030_33_nf;
+extern cpuop_func op_d030_33_ff;
+extern cpuop_func op_d038_33_nf;
+extern cpuop_func op_d038_33_ff;
+extern cpuop_func op_d039_33_nf;
+extern cpuop_func op_d039_33_ff;
+extern cpuop_func op_d03a_33_nf;
+extern cpuop_func op_d03a_33_ff;
+extern cpuop_func op_d03b_33_nf;
+extern cpuop_func op_d03b_33_ff;
+extern cpuop_func op_d03c_33_nf;
+extern cpuop_func op_d03c_33_ff;
+extern cpuop_func op_d040_33_nf;
+extern cpuop_func op_d040_33_ff;
+extern cpuop_func op_d048_33_nf;
+extern cpuop_func op_d048_33_ff;
+extern cpuop_func op_d050_33_nf;
+extern cpuop_func op_d050_33_ff;
+extern cpuop_func op_d058_33_nf;
+extern cpuop_func op_d058_33_ff;
+extern cpuop_func op_d060_33_nf;
+extern cpuop_func op_d060_33_ff;
+extern cpuop_func op_d068_33_nf;
+extern cpuop_func op_d068_33_ff;
+extern cpuop_func op_d070_33_nf;
+extern cpuop_func op_d070_33_ff;
+extern cpuop_func op_d078_33_nf;
+extern cpuop_func op_d078_33_ff;
+extern cpuop_func op_d079_33_nf;
+extern cpuop_func op_d079_33_ff;
+extern cpuop_func op_d07a_33_nf;
+extern cpuop_func op_d07a_33_ff;
+extern cpuop_func op_d07b_33_nf;
+extern cpuop_func op_d07b_33_ff;
+extern cpuop_func op_d07c_33_nf;
+extern cpuop_func op_d07c_33_ff;
+extern cpuop_func op_d080_33_nf;
+extern cpuop_func op_d080_33_ff;
+extern cpuop_func op_d088_33_nf;
+extern cpuop_func op_d088_33_ff;
+extern cpuop_func op_d090_33_nf;
+extern cpuop_func op_d090_33_ff;
+extern cpuop_func op_d098_33_nf;
+extern cpuop_func op_d098_33_ff;
+extern cpuop_func op_d0a0_33_nf;
+extern cpuop_func op_d0a0_33_ff;
+extern cpuop_func op_d0a8_33_nf;
+extern cpuop_func op_d0a8_33_ff;
+extern cpuop_func op_d0b0_33_nf;
+extern cpuop_func op_d0b0_33_ff;
+extern cpuop_func op_d0b8_33_nf;
+extern cpuop_func op_d0b8_33_ff;
+extern cpuop_func op_d0b9_33_nf;
+extern cpuop_func op_d0b9_33_ff;
+extern cpuop_func op_d0ba_33_nf;
+extern cpuop_func op_d0ba_33_ff;
+extern cpuop_func op_d0bb_33_nf;
+extern cpuop_func op_d0bb_33_ff;
+extern cpuop_func op_d0bc_33_nf;
+extern cpuop_func op_d0bc_33_ff;
+extern cpuop_func op_d0c0_33_nf;
+extern cpuop_func op_d0c0_33_ff;
+extern cpuop_func op_d0c8_33_nf;
+extern cpuop_func op_d0c8_33_ff;
+extern cpuop_func op_d0d0_33_nf;
+extern cpuop_func op_d0d0_33_ff;
+extern cpuop_func op_d0d8_33_nf;
+extern cpuop_func op_d0d8_33_ff;
+extern cpuop_func op_d0e0_33_nf;
+extern cpuop_func op_d0e0_33_ff;
+extern cpuop_func op_d0e8_33_nf;
+extern cpuop_func op_d0e8_33_ff;
+extern cpuop_func op_d0f0_33_nf;
+extern cpuop_func op_d0f0_33_ff;
+extern cpuop_func op_d0f8_33_nf;
+extern cpuop_func op_d0f8_33_ff;
+extern cpuop_func op_d0f9_33_nf;
+extern cpuop_func op_d0f9_33_ff;
+extern cpuop_func op_d0fa_33_nf;
+extern cpuop_func op_d0fa_33_ff;
+extern cpuop_func op_d0fb_33_nf;
+extern cpuop_func op_d0fb_33_ff;
+extern cpuop_func op_d0fc_33_nf;
+extern cpuop_func op_d0fc_33_ff;
+extern cpuop_func op_d100_33_nf;
+extern cpuop_func op_d100_33_ff;
+extern cpuop_func op_d108_33_nf;
+extern cpuop_func op_d108_33_ff;
+extern cpuop_func op_d110_33_nf;
+extern cpuop_func op_d110_33_ff;
+extern cpuop_func op_d118_33_nf;
+extern cpuop_func op_d118_33_ff;
+extern cpuop_func op_d120_33_nf;
+extern cpuop_func op_d120_33_ff;
+extern cpuop_func op_d128_33_nf;
+extern cpuop_func op_d128_33_ff;
+extern cpuop_func op_d130_33_nf;
+extern cpuop_func op_d130_33_ff;
+extern cpuop_func op_d138_33_nf;
+extern cpuop_func op_d138_33_ff;
+extern cpuop_func op_d139_33_nf;
+extern cpuop_func op_d139_33_ff;
+extern cpuop_func op_d140_33_nf;
+extern cpuop_func op_d140_33_ff;
+extern cpuop_func op_d148_33_nf;
+extern cpuop_func op_d148_33_ff;
+extern cpuop_func op_d150_33_nf;
+extern cpuop_func op_d150_33_ff;
+extern cpuop_func op_d158_33_nf;
+extern cpuop_func op_d158_33_ff;
+extern cpuop_func op_d160_33_nf;
+extern cpuop_func op_d160_33_ff;
+extern cpuop_func op_d168_33_nf;
+extern cpuop_func op_d168_33_ff;
+extern cpuop_func op_d170_33_nf;
+extern cpuop_func op_d170_33_ff;
+extern cpuop_func op_d178_33_nf;
+extern cpuop_func op_d178_33_ff;
+extern cpuop_func op_d179_33_nf;
+extern cpuop_func op_d179_33_ff;
+extern cpuop_func op_d180_33_nf;
+extern cpuop_func op_d180_33_ff;
+extern cpuop_func op_d188_33_nf;
+extern cpuop_func op_d188_33_ff;
+extern cpuop_func op_d190_33_nf;
+extern cpuop_func op_d190_33_ff;
+extern cpuop_func op_d198_33_nf;
+extern cpuop_func op_d198_33_ff;
+extern cpuop_func op_d1a0_33_nf;
+extern cpuop_func op_d1a0_33_ff;
+extern cpuop_func op_d1a8_33_nf;
+extern cpuop_func op_d1a8_33_ff;
+extern cpuop_func op_d1b0_33_nf;
+extern cpuop_func op_d1b0_33_ff;
+extern cpuop_func op_d1b8_33_nf;
+extern cpuop_func op_d1b8_33_ff;
+extern cpuop_func op_d1b9_33_nf;
+extern cpuop_func op_d1b9_33_ff;
+extern cpuop_func op_d1c0_33_nf;
+extern cpuop_func op_d1c0_33_ff;
+extern cpuop_func op_d1c8_33_nf;
+extern cpuop_func op_d1c8_33_ff;
+extern cpuop_func op_d1d0_33_nf;
+extern cpuop_func op_d1d0_33_ff;
+extern cpuop_func op_d1d8_33_nf;
+extern cpuop_func op_d1d8_33_ff;
+extern cpuop_func op_d1e0_33_nf;
+extern cpuop_func op_d1e0_33_ff;
+extern cpuop_func op_d1e8_33_nf;
+extern cpuop_func op_d1e8_33_ff;
+extern cpuop_func op_d1f0_33_nf;
+extern cpuop_func op_d1f0_33_ff;
+extern cpuop_func op_d1f8_33_nf;
+extern cpuop_func op_d1f8_33_ff;
+extern cpuop_func op_d1f9_33_nf;
+extern cpuop_func op_d1f9_33_ff;
+extern cpuop_func op_d1fa_33_nf;
+extern cpuop_func op_d1fa_33_ff;
+extern cpuop_func op_d1fb_33_nf;
+extern cpuop_func op_d1fb_33_ff;
+extern cpuop_func op_d1fc_33_nf;
+extern cpuop_func op_d1fc_33_ff;
+extern cpuop_func op_e000_33_nf;
+extern cpuop_func op_e000_33_ff;
+extern cpuop_func op_e008_33_nf;
+extern cpuop_func op_e008_33_ff;
+extern cpuop_func op_e010_33_nf;
+extern cpuop_func op_e010_33_ff;
+extern cpuop_func op_e018_33_nf;
+extern cpuop_func op_e018_33_ff;
+extern cpuop_func op_e020_33_nf;
+extern cpuop_func op_e020_33_ff;
+extern cpuop_func op_e028_33_nf;
+extern cpuop_func op_e028_33_ff;
+extern cpuop_func op_e030_33_nf;
+extern cpuop_func op_e030_33_ff;
+extern cpuop_func op_e038_33_nf;
+extern cpuop_func op_e038_33_ff;
+extern cpuop_func op_e040_33_nf;
+extern cpuop_func op_e040_33_ff;
+extern cpuop_func op_e048_33_nf;
+extern cpuop_func op_e048_33_ff;
+extern cpuop_func op_e050_33_nf;
+extern cpuop_func op_e050_33_ff;
+extern cpuop_func op_e058_33_nf;
+extern cpuop_func op_e058_33_ff;
+extern cpuop_func op_e060_33_nf;
+extern cpuop_func op_e060_33_ff;
+extern cpuop_func op_e068_33_nf;
+extern cpuop_func op_e068_33_ff;
+extern cpuop_func op_e070_33_nf;
+extern cpuop_func op_e070_33_ff;
+extern cpuop_func op_e078_33_nf;
+extern cpuop_func op_e078_33_ff;
+extern cpuop_func op_e080_33_nf;
+extern cpuop_func op_e080_33_ff;
+extern cpuop_func op_e088_33_nf;
+extern cpuop_func op_e088_33_ff;
+extern cpuop_func op_e090_33_nf;
+extern cpuop_func op_e090_33_ff;
+extern cpuop_func op_e098_33_nf;
+extern cpuop_func op_e098_33_ff;
+extern cpuop_func op_e0a0_33_nf;
+extern cpuop_func op_e0a0_33_ff;
+extern cpuop_func op_e0a8_33_nf;
+extern cpuop_func op_e0a8_33_ff;
+extern cpuop_func op_e0b0_33_nf;
+extern cpuop_func op_e0b0_33_ff;
+extern cpuop_func op_e0b8_33_nf;
+extern cpuop_func op_e0b8_33_ff;
+extern cpuop_func op_e0d0_33_nf;
+extern cpuop_func op_e0d0_33_ff;
+extern cpuop_func op_e0d8_33_nf;
+extern cpuop_func op_e0d8_33_ff;
+extern cpuop_func op_e0e0_33_nf;
+extern cpuop_func op_e0e0_33_ff;
+extern cpuop_func op_e0e8_33_nf;
+extern cpuop_func op_e0e8_33_ff;
+extern cpuop_func op_e0f0_33_nf;
+extern cpuop_func op_e0f0_33_ff;
+extern cpuop_func op_e0f8_33_nf;
+extern cpuop_func op_e0f8_33_ff;
+extern cpuop_func op_e0f9_33_nf;
+extern cpuop_func op_e0f9_33_ff;
+extern cpuop_func op_e100_33_nf;
+extern cpuop_func op_e100_33_ff;
+extern cpuop_func op_e108_33_nf;
+extern cpuop_func op_e108_33_ff;
+extern cpuop_func op_e110_33_nf;
+extern cpuop_func op_e110_33_ff;
+extern cpuop_func op_e118_33_nf;
+extern cpuop_func op_e118_33_ff;
+extern cpuop_func op_e120_33_nf;
+extern cpuop_func op_e120_33_ff;
+extern cpuop_func op_e128_33_nf;
+extern cpuop_func op_e128_33_ff;
+extern cpuop_func op_e130_33_nf;
+extern cpuop_func op_e130_33_ff;
+extern cpuop_func op_e138_33_nf;
+extern cpuop_func op_e138_33_ff;
+extern cpuop_func op_e140_33_nf;
+extern cpuop_func op_e140_33_ff;
+extern cpuop_func op_e148_33_nf;
+extern cpuop_func op_e148_33_ff;
+extern cpuop_func op_e150_33_nf;
+extern cpuop_func op_e150_33_ff;
+extern cpuop_func op_e158_33_nf;
+extern cpuop_func op_e158_33_ff;
+extern cpuop_func op_e160_33_nf;
+extern cpuop_func op_e160_33_ff;
+extern cpuop_func op_e168_33_nf;
+extern cpuop_func op_e168_33_ff;
+extern cpuop_func op_e170_33_nf;
+extern cpuop_func op_e170_33_ff;
+extern cpuop_func op_e178_33_nf;
+extern cpuop_func op_e178_33_ff;
+extern cpuop_func op_e180_33_nf;
+extern cpuop_func op_e180_33_ff;
+extern cpuop_func op_e188_33_nf;
+extern cpuop_func op_e188_33_ff;
+extern cpuop_func op_e190_33_nf;
+extern cpuop_func op_e190_33_ff;
+extern cpuop_func op_e198_33_nf;
+extern cpuop_func op_e198_33_ff;
+extern cpuop_func op_e1a0_33_nf;
+extern cpuop_func op_e1a0_33_ff;
+extern cpuop_func op_e1a8_33_nf;
+extern cpuop_func op_e1a8_33_ff;
+extern cpuop_func op_e1b0_33_nf;
+extern cpuop_func op_e1b0_33_ff;
+extern cpuop_func op_e1b8_33_nf;
+extern cpuop_func op_e1b8_33_ff;
+extern cpuop_func op_e1d0_33_nf;
+extern cpuop_func op_e1d0_33_ff;
+extern cpuop_func op_e1d8_33_nf;
+extern cpuop_func op_e1d8_33_ff;
+extern cpuop_func op_e1e0_33_nf;
+extern cpuop_func op_e1e0_33_ff;
+extern cpuop_func op_e1e8_33_nf;
+extern cpuop_func op_e1e8_33_ff;
+extern cpuop_func op_e1f0_33_nf;
+extern cpuop_func op_e1f0_33_ff;
+extern cpuop_func op_e1f8_33_nf;
+extern cpuop_func op_e1f8_33_ff;
+extern cpuop_func op_e1f9_33_nf;
+extern cpuop_func op_e1f9_33_ff;
+extern cpuop_func op_e2d0_33_nf;
+extern cpuop_func op_e2d0_33_ff;
+extern cpuop_func op_e2d8_33_nf;
+extern cpuop_func op_e2d8_33_ff;
+extern cpuop_func op_e2e0_33_nf;
+extern cpuop_func op_e2e0_33_ff;
+extern cpuop_func op_e2e8_33_nf;
+extern cpuop_func op_e2e8_33_ff;
+extern cpuop_func op_e2f0_33_nf;
+extern cpuop_func op_e2f0_33_ff;
+extern cpuop_func op_e2f8_33_nf;
+extern cpuop_func op_e2f8_33_ff;
+extern cpuop_func op_e2f9_33_nf;
+extern cpuop_func op_e2f9_33_ff;
+extern cpuop_func op_e3d0_33_nf;
+extern cpuop_func op_e3d0_33_ff;
+extern cpuop_func op_e3d8_33_nf;
+extern cpuop_func op_e3d8_33_ff;
+extern cpuop_func op_e3e0_33_nf;
+extern cpuop_func op_e3e0_33_ff;
+extern cpuop_func op_e3e8_33_nf;
+extern cpuop_func op_e3e8_33_ff;
+extern cpuop_func op_e3f0_33_nf;
+extern cpuop_func op_e3f0_33_ff;
+extern cpuop_func op_e3f8_33_nf;
+extern cpuop_func op_e3f8_33_ff;
+extern cpuop_func op_e3f9_33_nf;
+extern cpuop_func op_e3f9_33_ff;
+extern cpuop_func op_e4d0_33_nf;
+extern cpuop_func op_e4d0_33_ff;
+extern cpuop_func op_e4d8_33_nf;
+extern cpuop_func op_e4d8_33_ff;
+extern cpuop_func op_e4e0_33_nf;
+extern cpuop_func op_e4e0_33_ff;
+extern cpuop_func op_e4e8_33_nf;
+extern cpuop_func op_e4e8_33_ff;
+extern cpuop_func op_e4f0_33_nf;
+extern cpuop_func op_e4f0_33_ff;
+extern cpuop_func op_e4f8_33_nf;
+extern cpuop_func op_e4f8_33_ff;
+extern cpuop_func op_e4f9_33_nf;
+extern cpuop_func op_e4f9_33_ff;
+extern cpuop_func op_e5d0_33_nf;
+extern cpuop_func op_e5d0_33_ff;
+extern cpuop_func op_e5d8_33_nf;
+extern cpuop_func op_e5d8_33_ff;
+extern cpuop_func op_e5e0_33_nf;
+extern cpuop_func op_e5e0_33_ff;
+extern cpuop_func op_e5e8_33_nf;
+extern cpuop_func op_e5e8_33_ff;
+extern cpuop_func op_e5f0_33_nf;
+extern cpuop_func op_e5f0_33_ff;
+extern cpuop_func op_e5f8_33_nf;
+extern cpuop_func op_e5f8_33_ff;
+extern cpuop_func op_e5f9_33_nf;
+extern cpuop_func op_e5f9_33_ff;
+extern cpuop_func op_e6d0_33_nf;
+extern cpuop_func op_e6d0_33_ff;
+extern cpuop_func op_e6d8_33_nf;
+extern cpuop_func op_e6d8_33_ff;
+extern cpuop_func op_e6e0_33_nf;
+extern cpuop_func op_e6e0_33_ff;
+extern cpuop_func op_e6e8_33_nf;
+extern cpuop_func op_e6e8_33_ff;
+extern cpuop_func op_e6f0_33_nf;
+extern cpuop_func op_e6f0_33_ff;
+extern cpuop_func op_e6f8_33_nf;
+extern cpuop_func op_e6f8_33_ff;
+extern cpuop_func op_e6f9_33_nf;
+extern cpuop_func op_e6f9_33_ff;
+extern cpuop_func op_e7d0_33_nf;
+extern cpuop_func op_e7d0_33_ff;
+extern cpuop_func op_e7d8_33_nf;
+extern cpuop_func op_e7d8_33_ff;
+extern cpuop_func op_e7e0_33_nf;
+extern cpuop_func op_e7e0_33_ff;
+extern cpuop_func op_e7e8_33_nf;
+extern cpuop_func op_e7e8_33_ff;
+extern cpuop_func op_e7f0_33_nf;
+extern cpuop_func op_e7f0_33_ff;
+extern cpuop_func op_e7f8_33_nf;
+extern cpuop_func op_e7f8_33_ff;
+extern cpuop_func op_e7f9_33_nf;
+extern cpuop_func op_e7f9_33_ff;
+extern cpuop_func op_e8c0_33_nf;
+extern cpuop_func op_e8c0_33_ff;
+extern cpuop_func op_e8d0_33_nf;
+extern cpuop_func op_e8d0_33_ff;
+extern cpuop_func op_e8e8_33_nf;
+extern cpuop_func op_e8e8_33_ff;
+extern cpuop_func op_e8f0_33_nf;
+extern cpuop_func op_e8f0_33_ff;
+extern cpuop_func op_e8f8_33_nf;
+extern cpuop_func op_e8f8_33_ff;
+extern cpuop_func op_e8f9_33_nf;
+extern cpuop_func op_e8f9_33_ff;
+extern cpuop_func op_e8fa_33_nf;
+extern cpuop_func op_e8fa_33_ff;
+extern cpuop_func op_e8fb_33_nf;
+extern cpuop_func op_e8fb_33_ff;
+extern cpuop_func op_e9c0_33_nf;
+extern cpuop_func op_e9c0_33_ff;
+extern cpuop_func op_e9d0_33_nf;
+extern cpuop_func op_e9d0_33_ff;
+extern cpuop_func op_e9e8_33_nf;
+extern cpuop_func op_e9e8_33_ff;
+extern cpuop_func op_e9f0_33_nf;
+extern cpuop_func op_e9f0_33_ff;
+extern cpuop_func op_e9f8_33_nf;
+extern cpuop_func op_e9f8_33_ff;
+extern cpuop_func op_e9f9_33_nf;
+extern cpuop_func op_e9f9_33_ff;
+extern cpuop_func op_e9fa_33_nf;
+extern cpuop_func op_e9fa_33_ff;
+extern cpuop_func op_e9fb_33_nf;
+extern cpuop_func op_e9fb_33_ff;
+extern cpuop_func op_eac0_33_nf;
+extern cpuop_func op_eac0_33_ff;
+extern cpuop_func op_ead0_33_nf;
+extern cpuop_func op_ead0_33_ff;
+extern cpuop_func op_eae8_33_nf;
+extern cpuop_func op_eae8_33_ff;
+extern cpuop_func op_eaf0_33_nf;
+extern cpuop_func op_eaf0_33_ff;
+extern cpuop_func op_eaf8_33_nf;
+extern cpuop_func op_eaf8_33_ff;
+extern cpuop_func op_eaf9_33_nf;
+extern cpuop_func op_eaf9_33_ff;
+extern cpuop_func op_ebc0_33_nf;
+extern cpuop_func op_ebc0_33_ff;
+extern cpuop_func op_ebd0_33_nf;
+extern cpuop_func op_ebd0_33_ff;
+extern cpuop_func op_ebe8_33_nf;
+extern cpuop_func op_ebe8_33_ff;
+extern cpuop_func op_ebf0_33_nf;
+extern cpuop_func op_ebf0_33_ff;
+extern cpuop_func op_ebf8_33_nf;
+extern cpuop_func op_ebf8_33_ff;
+extern cpuop_func op_ebf9_33_nf;
+extern cpuop_func op_ebf9_33_ff;
+extern cpuop_func op_ebfa_33_nf;
+extern cpuop_func op_ebfa_33_ff;
+extern cpuop_func op_ebfb_33_nf;
+extern cpuop_func op_ebfb_33_ff;
+extern cpuop_func op_ecc0_33_nf;
+extern cpuop_func op_ecc0_33_ff;
+extern cpuop_func op_ecd0_33_nf;
+extern cpuop_func op_ecd0_33_ff;
+extern cpuop_func op_ece8_33_nf;
+extern cpuop_func op_ece8_33_ff;
+extern cpuop_func op_ecf0_33_nf;
+extern cpuop_func op_ecf0_33_ff;
+extern cpuop_func op_ecf8_33_nf;
+extern cpuop_func op_ecf8_33_ff;
+extern cpuop_func op_ecf9_33_nf;
+extern cpuop_func op_ecf9_33_ff;
+extern cpuop_func op_edc0_33_nf;
+extern cpuop_func op_edc0_33_ff;
+extern cpuop_func op_edd0_33_nf;
+extern cpuop_func op_edd0_33_ff;
+extern cpuop_func op_ede8_33_nf;
+extern cpuop_func op_ede8_33_ff;
+extern cpuop_func op_edf0_33_nf;
+extern cpuop_func op_edf0_33_ff;
+extern cpuop_func op_edf8_33_nf;
+extern cpuop_func op_edf8_33_ff;
+extern cpuop_func op_edf9_33_nf;
+extern cpuop_func op_edf9_33_ff;
+extern cpuop_func op_edfa_33_nf;
+extern cpuop_func op_edfa_33_ff;
+extern cpuop_func op_edfb_33_nf;
+extern cpuop_func op_edfb_33_ff;
+extern cpuop_func op_eec0_33_nf;
+extern cpuop_func op_eec0_33_ff;
+extern cpuop_func op_eed0_33_nf;
+extern cpuop_func op_eed0_33_ff;
+extern cpuop_func op_eee8_33_nf;
+extern cpuop_func op_eee8_33_ff;
+extern cpuop_func op_eef0_33_nf;
+extern cpuop_func op_eef0_33_ff;
+extern cpuop_func op_eef8_33_nf;
+extern cpuop_func op_eef8_33_ff;
+extern cpuop_func op_eef9_33_nf;
+extern cpuop_func op_eef9_33_ff;
+extern cpuop_func op_efc0_33_nf;
+extern cpuop_func op_efc0_33_ff;
+extern cpuop_func op_efd0_33_nf;
+extern cpuop_func op_efd0_33_ff;
+extern cpuop_func op_efe8_33_nf;
+extern cpuop_func op_efe8_33_ff;
+extern cpuop_func op_eff0_33_nf;
+extern cpuop_func op_eff0_33_ff;
+extern cpuop_func op_eff8_33_nf;
+extern cpuop_func op_eff8_33_ff;
+extern cpuop_func op_eff9_33_nf;
+extern cpuop_func op_eff9_33_ff;
+extern cpuop_func op_f000_33_nf;
+extern cpuop_func op_f000_33_ff;
+extern cpuop_func op_f008_33_nf;
+extern cpuop_func op_f008_33_ff;
+extern cpuop_func op_f010_33_nf;
+extern cpuop_func op_f010_33_ff;
+extern cpuop_func op_f018_33_nf;
+extern cpuop_func op_f018_33_ff;
+extern cpuop_func op_f020_33_nf;
+extern cpuop_func op_f020_33_ff;
+extern cpuop_func op_f028_33_nf;
+extern cpuop_func op_f028_33_ff;
+extern cpuop_func op_f030_33_nf;
+extern cpuop_func op_f030_33_ff;
+extern cpuop_func op_f038_33_nf;
+extern cpuop_func op_f038_33_ff;
+extern cpuop_func op_f039_33_nf;
+extern cpuop_func op_f039_33_ff;
+extern cpuop_func op_f200_33_nf;
+extern cpuop_func op_f200_33_ff;
+extern cpuop_func op_f208_33_nf;
+extern cpuop_func op_f208_33_ff;
+extern cpuop_func op_f210_33_nf;
+extern cpuop_func op_f210_33_ff;
+extern cpuop_func op_f218_33_nf;
+extern cpuop_func op_f218_33_ff;
+extern cpuop_func op_f220_33_nf;
+extern cpuop_func op_f220_33_ff;
+extern cpuop_func op_f228_33_nf;
+extern cpuop_func op_f228_33_ff;
+extern cpuop_func op_f230_33_nf;
+extern cpuop_func op_f230_33_ff;
+extern cpuop_func op_f238_33_nf;
+extern cpuop_func op_f238_33_ff;
+extern cpuop_func op_f239_33_nf;
+extern cpuop_func op_f239_33_ff;
+extern cpuop_func op_f23a_33_nf;
+extern cpuop_func op_f23a_33_ff;
+extern cpuop_func op_f23b_33_nf;
+extern cpuop_func op_f23b_33_ff;
+extern cpuop_func op_f23c_33_nf;
+extern cpuop_func op_f23c_33_ff;
+extern cpuop_func op_f240_33_nf;
+extern cpuop_func op_f240_33_ff;
+extern cpuop_func op_f248_33_nf;
+extern cpuop_func op_f248_33_ff;
+extern cpuop_func op_f250_33_nf;
+extern cpuop_func op_f250_33_ff;
+extern cpuop_func op_f258_33_nf;
+extern cpuop_func op_f258_33_ff;
+extern cpuop_func op_f260_33_nf;
+extern cpuop_func op_f260_33_ff;
+extern cpuop_func op_f268_33_nf;
+extern cpuop_func op_f268_33_ff;
+extern cpuop_func op_f270_33_nf;
+extern cpuop_func op_f270_33_ff;
+extern cpuop_func op_f278_33_nf;
+extern cpuop_func op_f278_33_ff;
+extern cpuop_func op_f279_33_nf;
+extern cpuop_func op_f279_33_ff;
+extern cpuop_func op_f27a_33_nf;
+extern cpuop_func op_f27a_33_ff;
+extern cpuop_func op_f27b_33_nf;
+extern cpuop_func op_f27b_33_ff;
+extern cpuop_func op_f27c_33_nf;
+extern cpuop_func op_f27c_33_ff;
+extern cpuop_func op_f280_33_nf;
+extern cpuop_func op_f280_33_ff;
+extern cpuop_func op_f2c0_33_nf;
+extern cpuop_func op_f2c0_33_ff;
+extern cpuop_func op_f310_33_nf;
+extern cpuop_func op_f310_33_ff;
+extern cpuop_func op_f320_33_nf;
+extern cpuop_func op_f320_33_ff;
+extern cpuop_func op_f328_33_nf;
+extern cpuop_func op_f328_33_ff;
+extern cpuop_func op_f330_33_nf;
+extern cpuop_func op_f330_33_ff;
+extern cpuop_func op_f338_33_nf;
+extern cpuop_func op_f338_33_ff;
+extern cpuop_func op_f339_33_nf;
+extern cpuop_func op_f339_33_ff;
+extern cpuop_func op_f350_33_nf;
+extern cpuop_func op_f350_33_ff;
+extern cpuop_func op_f358_33_nf;
+extern cpuop_func op_f358_33_ff;
+extern cpuop_func op_f368_33_nf;
+extern cpuop_func op_f368_33_ff;
+extern cpuop_func op_f370_33_nf;
+extern cpuop_func op_f370_33_ff;
+extern cpuop_func op_f378_33_nf;
+extern cpuop_func op_f378_33_ff;
+extern cpuop_func op_f379_33_nf;
+extern cpuop_func op_f379_33_ff;
+extern cpuop_func op_f37a_33_nf;
+extern cpuop_func op_f37a_33_ff;
+extern cpuop_func op_f37b_33_nf;
+extern cpuop_func op_f37b_33_ff;
+extern cpuop_func op_f408_33_nf;
+extern cpuop_func op_f408_33_ff;
+extern cpuop_func op_f410_33_nf;
+extern cpuop_func op_f410_33_ff;
+extern cpuop_func op_f418_33_nf;
+extern cpuop_func op_f418_33_ff;
+extern cpuop_func op_f419_33_nf;
+extern cpuop_func op_f419_33_ff;
+extern cpuop_func op_f41a_33_nf;
+extern cpuop_func op_f41a_33_ff;
+extern cpuop_func op_f41b_33_nf;
+extern cpuop_func op_f41b_33_ff;
+extern cpuop_func op_f41c_33_nf;
+extern cpuop_func op_f41c_33_ff;
+extern cpuop_func op_f41d_33_nf;
+extern cpuop_func op_f41d_33_ff;
+extern cpuop_func op_f41e_33_nf;
+extern cpuop_func op_f41e_33_ff;
+extern cpuop_func op_f41f_33_nf;
+extern cpuop_func op_f41f_33_ff;
+extern cpuop_func op_f428_33_nf;
+extern cpuop_func op_f428_33_ff;
+extern cpuop_func op_f430_33_nf;
+extern cpuop_func op_f430_33_ff;
+extern cpuop_func op_f438_33_nf;
+extern cpuop_func op_f438_33_ff;
+extern cpuop_func op_f439_33_nf;
+extern cpuop_func op_f439_33_ff;
+extern cpuop_func op_f43a_33_nf;
+extern cpuop_func op_f43a_33_ff;
+extern cpuop_func op_f43b_33_nf;
+extern cpuop_func op_f43b_33_ff;
+extern cpuop_func op_f43c_33_nf;
+extern cpuop_func op_f43c_33_ff;
+extern cpuop_func op_f43d_33_nf;
+extern cpuop_func op_f43d_33_ff;
+extern cpuop_func op_f43e_33_nf;
+extern cpuop_func op_f43e_33_ff;
+extern cpuop_func op_f43f_33_nf;
+extern cpuop_func op_f43f_33_ff;
+extern cpuop_func op_f500_33_nf;
+extern cpuop_func op_f500_33_ff;
+extern cpuop_func op_f508_33_nf;
+extern cpuop_func op_f508_33_ff;
+extern cpuop_func op_f510_33_nf;
+extern cpuop_func op_f510_33_ff;
+extern cpuop_func op_f518_33_nf;
+extern cpuop_func op_f518_33_ff;
+extern cpuop_func op_f548_33_nf;
+extern cpuop_func op_f548_33_ff;
+extern cpuop_func op_f568_33_nf;
+extern cpuop_func op_f568_33_ff;
+extern cpuop_func op_f588_33_nf;
+extern cpuop_func op_f588_33_ff;
+extern cpuop_func op_f5c8_33_nf;
+extern cpuop_func op_f5c8_33_ff;
+extern cpuop_func op_f600_33_nf;
+extern cpuop_func op_f600_33_ff;
+extern cpuop_func op_f608_33_nf;
+extern cpuop_func op_f608_33_ff;
+extern cpuop_func op_f610_33_nf;
+extern cpuop_func op_f610_33_ff;
+extern cpuop_func op_f618_33_nf;
+extern cpuop_func op_f618_33_ff;
+extern cpuop_func op_f620_33_nf;
+extern cpuop_func op_f620_33_ff;
+extern cpuop_func op_f800_33_nf;
+extern cpuop_func op_f800_33_ff;
+extern cpuop_func op_0000_40_nf;
+extern cpuop_func op_0000_40_ff;
+extern cpuop_func op_0010_40_nf;
+extern cpuop_func op_0010_40_ff;
+extern cpuop_func op_0018_40_nf;
+extern cpuop_func op_0018_40_ff;
+extern cpuop_func op_0020_40_nf;
+extern cpuop_func op_0020_40_ff;
+extern cpuop_func op_0028_40_nf;
+extern cpuop_func op_0028_40_ff;
+extern cpuop_func op_0030_40_nf;
+extern cpuop_func op_0030_40_ff;
+extern cpuop_func op_0038_40_nf;
+extern cpuop_func op_0038_40_ff;
+extern cpuop_func op_0039_40_nf;
+extern cpuop_func op_0039_40_ff;
+extern cpuop_func op_003c_40_nf;
+extern cpuop_func op_003c_40_ff;
+extern cpuop_func op_0040_40_nf;
+extern cpuop_func op_0040_40_ff;
+extern cpuop_func op_0050_40_nf;
+extern cpuop_func op_0050_40_ff;
+extern cpuop_func op_0058_40_nf;
+extern cpuop_func op_0058_40_ff;
+extern cpuop_func op_0060_40_nf;
+extern cpuop_func op_0060_40_ff;
+extern cpuop_func op_0068_40_nf;
+extern cpuop_func op_0068_40_ff;
+extern cpuop_func op_0070_40_nf;
+extern cpuop_func op_0070_40_ff;
+extern cpuop_func op_0078_40_nf;
+extern cpuop_func op_0078_40_ff;
+extern cpuop_func op_0079_40_nf;
+extern cpuop_func op_0079_40_ff;
+extern cpuop_func op_007c_40_nf;
+extern cpuop_func op_007c_40_ff;
+extern cpuop_func op_0080_40_nf;
+extern cpuop_func op_0080_40_ff;
+extern cpuop_func op_0090_40_nf;
+extern cpuop_func op_0090_40_ff;
+extern cpuop_func op_0098_40_nf;
+extern cpuop_func op_0098_40_ff;
+extern cpuop_func op_00a0_40_nf;
+extern cpuop_func op_00a0_40_ff;
+extern cpuop_func op_00a8_40_nf;
+extern cpuop_func op_00a8_40_ff;
+extern cpuop_func op_00b0_40_nf;
+extern cpuop_func op_00b0_40_ff;
+extern cpuop_func op_00b8_40_nf;
+extern cpuop_func op_00b8_40_ff;
+extern cpuop_func op_00b9_40_nf;
+extern cpuop_func op_00b9_40_ff;
+extern cpuop_func op_00d0_40_nf;
+extern cpuop_func op_00d0_40_ff;
+extern cpuop_func op_00e8_40_nf;
+extern cpuop_func op_00e8_40_ff;
+extern cpuop_func op_00f0_40_nf;
+extern cpuop_func op_00f0_40_ff;
+extern cpuop_func op_00f8_40_nf;
+extern cpuop_func op_00f8_40_ff;
+extern cpuop_func op_00f9_40_nf;
+extern cpuop_func op_00f9_40_ff;
+extern cpuop_func op_00fa_40_nf;
+extern cpuop_func op_00fa_40_ff;
+extern cpuop_func op_00fb_40_nf;
+extern cpuop_func op_00fb_40_ff;
+extern cpuop_func op_0100_40_nf;
+extern cpuop_func op_0100_40_ff;
+extern cpuop_func op_0108_40_nf;
+extern cpuop_func op_0108_40_ff;
+extern cpuop_func op_0110_40_nf;
+extern cpuop_func op_0110_40_ff;
+extern cpuop_func op_0118_40_nf;
+extern cpuop_func op_0118_40_ff;
+extern cpuop_func op_0120_40_nf;
+extern cpuop_func op_0120_40_ff;
+extern cpuop_func op_0128_40_nf;
+extern cpuop_func op_0128_40_ff;
+extern cpuop_func op_0130_40_nf;
+extern cpuop_func op_0130_40_ff;
+extern cpuop_func op_0138_40_nf;
+extern cpuop_func op_0138_40_ff;
+extern cpuop_func op_0139_40_nf;
+extern cpuop_func op_0139_40_ff;
+extern cpuop_func op_013a_40_nf;
+extern cpuop_func op_013a_40_ff;
+extern cpuop_func op_013b_40_nf;
+extern cpuop_func op_013b_40_ff;
+extern cpuop_func op_013c_40_nf;
+extern cpuop_func op_013c_40_ff;
+extern cpuop_func op_0140_40_nf;
+extern cpuop_func op_0140_40_ff;
+extern cpuop_func op_0148_40_nf;
+extern cpuop_func op_0148_40_ff;
+extern cpuop_func op_0150_40_nf;
+extern cpuop_func op_0150_40_ff;
+extern cpuop_func op_0158_40_nf;
+extern cpuop_func op_0158_40_ff;
+extern cpuop_func op_0160_40_nf;
+extern cpuop_func op_0160_40_ff;
+extern cpuop_func op_0168_40_nf;
+extern cpuop_func op_0168_40_ff;
+extern cpuop_func op_0170_40_nf;
+extern cpuop_func op_0170_40_ff;
+extern cpuop_func op_0178_40_nf;
+extern cpuop_func op_0178_40_ff;
+extern cpuop_func op_0179_40_nf;
+extern cpuop_func op_0179_40_ff;
+extern cpuop_func op_0180_40_nf;
+extern cpuop_func op_0180_40_ff;
+extern cpuop_func op_0188_40_nf;
+extern cpuop_func op_0188_40_ff;
+extern cpuop_func op_0190_40_nf;
+extern cpuop_func op_0190_40_ff;
+extern cpuop_func op_0198_40_nf;
+extern cpuop_func op_0198_40_ff;
+extern cpuop_func op_01a0_40_nf;
+extern cpuop_func op_01a0_40_ff;
+extern cpuop_func op_01a8_40_nf;
+extern cpuop_func op_01a8_40_ff;
+extern cpuop_func op_01b0_40_nf;
+extern cpuop_func op_01b0_40_ff;
+extern cpuop_func op_01b8_40_nf;
+extern cpuop_func op_01b8_40_ff;
+extern cpuop_func op_01b9_40_nf;
+extern cpuop_func op_01b9_40_ff;
+extern cpuop_func op_01c0_40_nf;
+extern cpuop_func op_01c0_40_ff;
+extern cpuop_func op_01c8_40_nf;
+extern cpuop_func op_01c8_40_ff;
+extern cpuop_func op_01d0_40_nf;
+extern cpuop_func op_01d0_40_ff;
+extern cpuop_func op_01d8_40_nf;
+extern cpuop_func op_01d8_40_ff;
+extern cpuop_func op_01e0_40_nf;
+extern cpuop_func op_01e0_40_ff;
+extern cpuop_func op_01e8_40_nf;
+extern cpuop_func op_01e8_40_ff;
+extern cpuop_func op_01f0_40_nf;
+extern cpuop_func op_01f0_40_ff;
+extern cpuop_func op_01f8_40_nf;
+extern cpuop_func op_01f8_40_ff;
+extern cpuop_func op_01f9_40_nf;
+extern cpuop_func op_01f9_40_ff;
+extern cpuop_func op_0200_40_nf;
+extern cpuop_func op_0200_40_ff;
+extern cpuop_func op_0210_40_nf;
+extern cpuop_func op_0210_40_ff;
+extern cpuop_func op_0218_40_nf;
+extern cpuop_func op_0218_40_ff;
+extern cpuop_func op_0220_40_nf;
+extern cpuop_func op_0220_40_ff;
+extern cpuop_func op_0228_40_nf;
+extern cpuop_func op_0228_40_ff;
+extern cpuop_func op_0230_40_nf;
+extern cpuop_func op_0230_40_ff;
+extern cpuop_func op_0238_40_nf;
+extern cpuop_func op_0238_40_ff;
+extern cpuop_func op_0239_40_nf;
+extern cpuop_func op_0239_40_ff;
+extern cpuop_func op_023c_40_nf;
+extern cpuop_func op_023c_40_ff;
+extern cpuop_func op_0240_40_nf;
+extern cpuop_func op_0240_40_ff;
+extern cpuop_func op_0250_40_nf;
+extern cpuop_func op_0250_40_ff;
+extern cpuop_func op_0258_40_nf;
+extern cpuop_func op_0258_40_ff;
+extern cpuop_func op_0260_40_nf;
+extern cpuop_func op_0260_40_ff;
+extern cpuop_func op_0268_40_nf;
+extern cpuop_func op_0268_40_ff;
+extern cpuop_func op_0270_40_nf;
+extern cpuop_func op_0270_40_ff;
+extern cpuop_func op_0278_40_nf;
+extern cpuop_func op_0278_40_ff;
+extern cpuop_func op_0279_40_nf;
+extern cpuop_func op_0279_40_ff;
+extern cpuop_func op_027c_40_nf;
+extern cpuop_func op_027c_40_ff;
+extern cpuop_func op_0280_40_nf;
+extern cpuop_func op_0280_40_ff;
+extern cpuop_func op_0290_40_nf;
+extern cpuop_func op_0290_40_ff;
+extern cpuop_func op_0298_40_nf;
+extern cpuop_func op_0298_40_ff;
+extern cpuop_func op_02a0_40_nf;
+extern cpuop_func op_02a0_40_ff;
+extern cpuop_func op_02a8_40_nf;
+extern cpuop_func op_02a8_40_ff;
+extern cpuop_func op_02b0_40_nf;
+extern cpuop_func op_02b0_40_ff;
+extern cpuop_func op_02b8_40_nf;
+extern cpuop_func op_02b8_40_ff;
+extern cpuop_func op_02b9_40_nf;
+extern cpuop_func op_02b9_40_ff;
+extern cpuop_func op_02d0_40_nf;
+extern cpuop_func op_02d0_40_ff;
+extern cpuop_func op_02e8_40_nf;
+extern cpuop_func op_02e8_40_ff;
+extern cpuop_func op_02f0_40_nf;
+extern cpuop_func op_02f0_40_ff;
+extern cpuop_func op_02f8_40_nf;
+extern cpuop_func op_02f8_40_ff;
+extern cpuop_func op_02f9_40_nf;
+extern cpuop_func op_02f9_40_ff;
+extern cpuop_func op_02fa_40_nf;
+extern cpuop_func op_02fa_40_ff;
+extern cpuop_func op_02fb_40_nf;
+extern cpuop_func op_02fb_40_ff;
+extern cpuop_func op_0400_40_nf;
+extern cpuop_func op_0400_40_ff;
+extern cpuop_func op_0410_40_nf;
+extern cpuop_func op_0410_40_ff;
+extern cpuop_func op_0418_40_nf;
+extern cpuop_func op_0418_40_ff;
+extern cpuop_func op_0420_40_nf;
+extern cpuop_func op_0420_40_ff;
+extern cpuop_func op_0428_40_nf;
+extern cpuop_func op_0428_40_ff;
+extern cpuop_func op_0430_40_nf;
+extern cpuop_func op_0430_40_ff;
+extern cpuop_func op_0438_40_nf;
+extern cpuop_func op_0438_40_ff;
+extern cpuop_func op_0439_40_nf;
+extern cpuop_func op_0439_40_ff;
+extern cpuop_func op_0440_40_nf;
+extern cpuop_func op_0440_40_ff;
+extern cpuop_func op_0450_40_nf;
+extern cpuop_func op_0450_40_ff;
+extern cpuop_func op_0458_40_nf;
+extern cpuop_func op_0458_40_ff;
+extern cpuop_func op_0460_40_nf;
+extern cpuop_func op_0460_40_ff;
+extern cpuop_func op_0468_40_nf;
+extern cpuop_func op_0468_40_ff;
+extern cpuop_func op_0470_40_nf;
+extern cpuop_func op_0470_40_ff;
+extern cpuop_func op_0478_40_nf;
+extern cpuop_func op_0478_40_ff;
+extern cpuop_func op_0479_40_nf;
+extern cpuop_func op_0479_40_ff;
+extern cpuop_func op_0480_40_nf;
+extern cpuop_func op_0480_40_ff;
+extern cpuop_func op_0490_40_nf;
+extern cpuop_func op_0490_40_ff;
+extern cpuop_func op_0498_40_nf;
+extern cpuop_func op_0498_40_ff;
+extern cpuop_func op_04a0_40_nf;
+extern cpuop_func op_04a0_40_ff;
+extern cpuop_func op_04a8_40_nf;
+extern cpuop_func op_04a8_40_ff;
+extern cpuop_func op_04b0_40_nf;
+extern cpuop_func op_04b0_40_ff;
+extern cpuop_func op_04b8_40_nf;
+extern cpuop_func op_04b8_40_ff;
+extern cpuop_func op_04b9_40_nf;
+extern cpuop_func op_04b9_40_ff;
+extern cpuop_func op_04d0_40_nf;
+extern cpuop_func op_04d0_40_ff;
+extern cpuop_func op_04e8_40_nf;
+extern cpuop_func op_04e8_40_ff;
+extern cpuop_func op_04f0_40_nf;
+extern cpuop_func op_04f0_40_ff;
+extern cpuop_func op_04f8_40_nf;
+extern cpuop_func op_04f8_40_ff;
+extern cpuop_func op_04f9_40_nf;
+extern cpuop_func op_04f9_40_ff;
+extern cpuop_func op_04fa_40_nf;
+extern cpuop_func op_04fa_40_ff;
+extern cpuop_func op_04fb_40_nf;
+extern cpuop_func op_04fb_40_ff;
+extern cpuop_func op_0600_40_nf;
+extern cpuop_func op_0600_40_ff;
+extern cpuop_func op_0610_40_nf;
+extern cpuop_func op_0610_40_ff;
+extern cpuop_func op_0618_40_nf;
+extern cpuop_func op_0618_40_ff;
+extern cpuop_func op_0620_40_nf;
+extern cpuop_func op_0620_40_ff;
+extern cpuop_func op_0628_40_nf;
+extern cpuop_func op_0628_40_ff;
+extern cpuop_func op_0630_40_nf;
+extern cpuop_func op_0630_40_ff;
+extern cpuop_func op_0638_40_nf;
+extern cpuop_func op_0638_40_ff;
+extern cpuop_func op_0639_40_nf;
+extern cpuop_func op_0639_40_ff;
+extern cpuop_func op_0640_40_nf;
+extern cpuop_func op_0640_40_ff;
+extern cpuop_func op_0650_40_nf;
+extern cpuop_func op_0650_40_ff;
+extern cpuop_func op_0658_40_nf;
+extern cpuop_func op_0658_40_ff;
+extern cpuop_func op_0660_40_nf;
+extern cpuop_func op_0660_40_ff;
+extern cpuop_func op_0668_40_nf;
+extern cpuop_func op_0668_40_ff;
+extern cpuop_func op_0670_40_nf;
+extern cpuop_func op_0670_40_ff;
+extern cpuop_func op_0678_40_nf;
+extern cpuop_func op_0678_40_ff;
+extern cpuop_func op_0679_40_nf;
+extern cpuop_func op_0679_40_ff;
+extern cpuop_func op_0680_40_nf;
+extern cpuop_func op_0680_40_ff;
+extern cpuop_func op_0690_40_nf;
+extern cpuop_func op_0690_40_ff;
+extern cpuop_func op_0698_40_nf;
+extern cpuop_func op_0698_40_ff;
+extern cpuop_func op_06a0_40_nf;
+extern cpuop_func op_06a0_40_ff;
+extern cpuop_func op_06a8_40_nf;
+extern cpuop_func op_06a8_40_ff;
+extern cpuop_func op_06b0_40_nf;
+extern cpuop_func op_06b0_40_ff;
+extern cpuop_func op_06b8_40_nf;
+extern cpuop_func op_06b8_40_ff;
+extern cpuop_func op_06b9_40_nf;
+extern cpuop_func op_06b9_40_ff;
+extern cpuop_func op_06c0_40_nf;
+extern cpuop_func op_06c0_40_ff;
+extern cpuop_func op_06c8_40_nf;
+extern cpuop_func op_06c8_40_ff;
+extern cpuop_func op_06d0_40_nf;
+extern cpuop_func op_06d0_40_ff;
+extern cpuop_func op_06e8_40_nf;
+extern cpuop_func op_06e8_40_ff;
+extern cpuop_func op_06f0_40_nf;
+extern cpuop_func op_06f0_40_ff;
+extern cpuop_func op_06f8_40_nf;
+extern cpuop_func op_06f8_40_ff;
+extern cpuop_func op_06f9_40_nf;
+extern cpuop_func op_06f9_40_ff;
+extern cpuop_func op_06fa_40_nf;
+extern cpuop_func op_06fa_40_ff;
+extern cpuop_func op_06fb_40_nf;
+extern cpuop_func op_06fb_40_ff;
+extern cpuop_func op_0800_40_nf;
+extern cpuop_func op_0800_40_ff;
+extern cpuop_func op_0810_40_nf;
+extern cpuop_func op_0810_40_ff;
+extern cpuop_func op_0818_40_nf;
+extern cpuop_func op_0818_40_ff;
+extern cpuop_func op_0820_40_nf;
+extern cpuop_func op_0820_40_ff;
+extern cpuop_func op_0828_40_nf;
+extern cpuop_func op_0828_40_ff;
+extern cpuop_func op_0830_40_nf;
+extern cpuop_func op_0830_40_ff;
+extern cpuop_func op_0838_40_nf;
+extern cpuop_func op_0838_40_ff;
+extern cpuop_func op_0839_40_nf;
+extern cpuop_func op_0839_40_ff;
+extern cpuop_func op_083a_40_nf;
+extern cpuop_func op_083a_40_ff;
+extern cpuop_func op_083b_40_nf;
+extern cpuop_func op_083b_40_ff;
+extern cpuop_func op_0840_40_nf;
+extern cpuop_func op_0840_40_ff;
+extern cpuop_func op_0850_40_nf;
+extern cpuop_func op_0850_40_ff;
+extern cpuop_func op_0858_40_nf;
+extern cpuop_func op_0858_40_ff;
+extern cpuop_func op_0860_40_nf;
+extern cpuop_func op_0860_40_ff;
+extern cpuop_func op_0868_40_nf;
+extern cpuop_func op_0868_40_ff;
+extern cpuop_func op_0870_40_nf;
+extern cpuop_func op_0870_40_ff;
+extern cpuop_func op_0878_40_nf;
+extern cpuop_func op_0878_40_ff;
+extern cpuop_func op_0879_40_nf;
+extern cpuop_func op_0879_40_ff;
+extern cpuop_func op_0880_40_nf;
+extern cpuop_func op_0880_40_ff;
+extern cpuop_func op_0890_40_nf;
+extern cpuop_func op_0890_40_ff;
+extern cpuop_func op_0898_40_nf;
+extern cpuop_func op_0898_40_ff;
+extern cpuop_func op_08a0_40_nf;
+extern cpuop_func op_08a0_40_ff;
+extern cpuop_func op_08a8_40_nf;
+extern cpuop_func op_08a8_40_ff;
+extern cpuop_func op_08b0_40_nf;
+extern cpuop_func op_08b0_40_ff;
+extern cpuop_func op_08b8_40_nf;
+extern cpuop_func op_08b8_40_ff;
+extern cpuop_func op_08b9_40_nf;
+extern cpuop_func op_08b9_40_ff;
+extern cpuop_func op_08c0_40_nf;
+extern cpuop_func op_08c0_40_ff;
+extern cpuop_func op_08d0_40_nf;
+extern cpuop_func op_08d0_40_ff;
+extern cpuop_func op_08d8_40_nf;
+extern cpuop_func op_08d8_40_ff;
+extern cpuop_func op_08e0_40_nf;
+extern cpuop_func op_08e0_40_ff;
+extern cpuop_func op_08e8_40_nf;
+extern cpuop_func op_08e8_40_ff;
+extern cpuop_func op_08f0_40_nf;
+extern cpuop_func op_08f0_40_ff;
+extern cpuop_func op_08f8_40_nf;
+extern cpuop_func op_08f8_40_ff;
+extern cpuop_func op_08f9_40_nf;
+extern cpuop_func op_08f9_40_ff;
+extern cpuop_func op_0a00_40_nf;
+extern cpuop_func op_0a00_40_ff;
+extern cpuop_func op_0a10_40_nf;
+extern cpuop_func op_0a10_40_ff;
+extern cpuop_func op_0a18_40_nf;
+extern cpuop_func op_0a18_40_ff;
+extern cpuop_func op_0a20_40_nf;
+extern cpuop_func op_0a20_40_ff;
+extern cpuop_func op_0a28_40_nf;
+extern cpuop_func op_0a28_40_ff;
+extern cpuop_func op_0a30_40_nf;
+extern cpuop_func op_0a30_40_ff;
+extern cpuop_func op_0a38_40_nf;
+extern cpuop_func op_0a38_40_ff;
+extern cpuop_func op_0a39_40_nf;
+extern cpuop_func op_0a39_40_ff;
+extern cpuop_func op_0a3c_40_nf;
+extern cpuop_func op_0a3c_40_ff;
+extern cpuop_func op_0a40_40_nf;
+extern cpuop_func op_0a40_40_ff;
+extern cpuop_func op_0a50_40_nf;
+extern cpuop_func op_0a50_40_ff;
+extern cpuop_func op_0a58_40_nf;
+extern cpuop_func op_0a58_40_ff;
+extern cpuop_func op_0a60_40_nf;
+extern cpuop_func op_0a60_40_ff;
+extern cpuop_func op_0a68_40_nf;
+extern cpuop_func op_0a68_40_ff;
+extern cpuop_func op_0a70_40_nf;
+extern cpuop_func op_0a70_40_ff;
+extern cpuop_func op_0a78_40_nf;
+extern cpuop_func op_0a78_40_ff;
+extern cpuop_func op_0a79_40_nf;
+extern cpuop_func op_0a79_40_ff;
+extern cpuop_func op_0a7c_40_nf;
+extern cpuop_func op_0a7c_40_ff;
+extern cpuop_func op_0a80_40_nf;
+extern cpuop_func op_0a80_40_ff;
+extern cpuop_func op_0a90_40_nf;
+extern cpuop_func op_0a90_40_ff;
+extern cpuop_func op_0a98_40_nf;
+extern cpuop_func op_0a98_40_ff;
+extern cpuop_func op_0aa0_40_nf;
+extern cpuop_func op_0aa0_40_ff;
+extern cpuop_func op_0aa8_40_nf;
+extern cpuop_func op_0aa8_40_ff;
+extern cpuop_func op_0ab0_40_nf;
+extern cpuop_func op_0ab0_40_ff;
+extern cpuop_func op_0ab8_40_nf;
+extern cpuop_func op_0ab8_40_ff;
+extern cpuop_func op_0ab9_40_nf;
+extern cpuop_func op_0ab9_40_ff;
+extern cpuop_func op_0ad0_40_nf;
+extern cpuop_func op_0ad0_40_ff;
+extern cpuop_func op_0ad8_40_nf;
+extern cpuop_func op_0ad8_40_ff;
+extern cpuop_func op_0ae0_40_nf;
+extern cpuop_func op_0ae0_40_ff;
+extern cpuop_func op_0ae8_40_nf;
+extern cpuop_func op_0ae8_40_ff;
+extern cpuop_func op_0af0_40_nf;
+extern cpuop_func op_0af0_40_ff;
+extern cpuop_func op_0af8_40_nf;
+extern cpuop_func op_0af8_40_ff;
+extern cpuop_func op_0af9_40_nf;
+extern cpuop_func op_0af9_40_ff;
+extern cpuop_func op_0c00_40_nf;
+extern cpuop_func op_0c00_40_ff;
+extern cpuop_func op_0c10_40_nf;
+extern cpuop_func op_0c10_40_ff;
+extern cpuop_func op_0c18_40_nf;
+extern cpuop_func op_0c18_40_ff;
+extern cpuop_func op_0c20_40_nf;
+extern cpuop_func op_0c20_40_ff;
+extern cpuop_func op_0c28_40_nf;
+extern cpuop_func op_0c28_40_ff;
+extern cpuop_func op_0c30_40_nf;
+extern cpuop_func op_0c30_40_ff;
+extern cpuop_func op_0c38_40_nf;
+extern cpuop_func op_0c38_40_ff;
+extern cpuop_func op_0c39_40_nf;
+extern cpuop_func op_0c39_40_ff;
+extern cpuop_func op_0c3a_40_nf;
+extern cpuop_func op_0c3a_40_ff;
+extern cpuop_func op_0c3b_40_nf;
+extern cpuop_func op_0c3b_40_ff;
+extern cpuop_func op_0c40_40_nf;
+extern cpuop_func op_0c40_40_ff;
+extern cpuop_func op_0c50_40_nf;
+extern cpuop_func op_0c50_40_ff;
+extern cpuop_func op_0c58_40_nf;
+extern cpuop_func op_0c58_40_ff;
+extern cpuop_func op_0c60_40_nf;
+extern cpuop_func op_0c60_40_ff;
+extern cpuop_func op_0c68_40_nf;
+extern cpuop_func op_0c68_40_ff;
+extern cpuop_func op_0c70_40_nf;
+extern cpuop_func op_0c70_40_ff;
+extern cpuop_func op_0c78_40_nf;
+extern cpuop_func op_0c78_40_ff;
+extern cpuop_func op_0c79_40_nf;
+extern cpuop_func op_0c79_40_ff;
+extern cpuop_func op_0c7a_40_nf;
+extern cpuop_func op_0c7a_40_ff;
+extern cpuop_func op_0c7b_40_nf;
+extern cpuop_func op_0c7b_40_ff;
+extern cpuop_func op_0c80_40_nf;
+extern cpuop_func op_0c80_40_ff;
+extern cpuop_func op_0c90_40_nf;
+extern cpuop_func op_0c90_40_ff;
+extern cpuop_func op_0c98_40_nf;
+extern cpuop_func op_0c98_40_ff;
+extern cpuop_func op_0ca0_40_nf;
+extern cpuop_func op_0ca0_40_ff;
+extern cpuop_func op_0ca8_40_nf;
+extern cpuop_func op_0ca8_40_ff;
+extern cpuop_func op_0cb0_40_nf;
+extern cpuop_func op_0cb0_40_ff;
+extern cpuop_func op_0cb8_40_nf;
+extern cpuop_func op_0cb8_40_ff;
+extern cpuop_func op_0cb9_40_nf;
+extern cpuop_func op_0cb9_40_ff;
+extern cpuop_func op_0cba_40_nf;
+extern cpuop_func op_0cba_40_ff;
+extern cpuop_func op_0cbb_40_nf;
+extern cpuop_func op_0cbb_40_ff;
+extern cpuop_func op_0cd0_40_nf;
+extern cpuop_func op_0cd0_40_ff;
+extern cpuop_func op_0cd8_40_nf;
+extern cpuop_func op_0cd8_40_ff;
+extern cpuop_func op_0ce0_40_nf;
+extern cpuop_func op_0ce0_40_ff;
+extern cpuop_func op_0ce8_40_nf;
+extern cpuop_func op_0ce8_40_ff;
+extern cpuop_func op_0cf0_40_nf;
+extern cpuop_func op_0cf0_40_ff;
+extern cpuop_func op_0cf8_40_nf;
+extern cpuop_func op_0cf8_40_ff;
+extern cpuop_func op_0cf9_40_nf;
+extern cpuop_func op_0cf9_40_ff;
+extern cpuop_func op_0cfc_40_nf;
+extern cpuop_func op_0cfc_40_ff;
+extern cpuop_func op_0e10_40_nf;
+extern cpuop_func op_0e10_40_ff;
+extern cpuop_func op_0e18_40_nf;
+extern cpuop_func op_0e18_40_ff;
+extern cpuop_func op_0e20_40_nf;
+extern cpuop_func op_0e20_40_ff;
+extern cpuop_func op_0e28_40_nf;
+extern cpuop_func op_0e28_40_ff;
+extern cpuop_func op_0e30_40_nf;
+extern cpuop_func op_0e30_40_ff;
+extern cpuop_func op_0e38_40_nf;
+extern cpuop_func op_0e38_40_ff;
+extern cpuop_func op_0e39_40_nf;
+extern cpuop_func op_0e39_40_ff;
+extern cpuop_func op_0e50_40_nf;
+extern cpuop_func op_0e50_40_ff;
+extern cpuop_func op_0e58_40_nf;
+extern cpuop_func op_0e58_40_ff;
+extern cpuop_func op_0e60_40_nf;
+extern cpuop_func op_0e60_40_ff;
+extern cpuop_func op_0e68_40_nf;
+extern cpuop_func op_0e68_40_ff;
+extern cpuop_func op_0e70_40_nf;
+extern cpuop_func op_0e70_40_ff;
+extern cpuop_func op_0e78_40_nf;
+extern cpuop_func op_0e78_40_ff;
+extern cpuop_func op_0e79_40_nf;
+extern cpuop_func op_0e79_40_ff;
+extern cpuop_func op_0e90_40_nf;
+extern cpuop_func op_0e90_40_ff;
+extern cpuop_func op_0e98_40_nf;
+extern cpuop_func op_0e98_40_ff;
+extern cpuop_func op_0ea0_40_nf;
+extern cpuop_func op_0ea0_40_ff;
+extern cpuop_func op_0ea8_40_nf;
+extern cpuop_func op_0ea8_40_ff;
+extern cpuop_func op_0eb0_40_nf;
+extern cpuop_func op_0eb0_40_ff;
+extern cpuop_func op_0eb8_40_nf;
+extern cpuop_func op_0eb8_40_ff;
+extern cpuop_func op_0eb9_40_nf;
+extern cpuop_func op_0eb9_40_ff;
+extern cpuop_func op_0ed0_40_nf;
+extern cpuop_func op_0ed0_40_ff;
+extern cpuop_func op_0ed8_40_nf;
+extern cpuop_func op_0ed8_40_ff;
+extern cpuop_func op_0ee0_40_nf;
+extern cpuop_func op_0ee0_40_ff;
+extern cpuop_func op_0ee8_40_nf;
+extern cpuop_func op_0ee8_40_ff;
+extern cpuop_func op_0ef0_40_nf;
+extern cpuop_func op_0ef0_40_ff;
+extern cpuop_func op_0ef8_40_nf;
+extern cpuop_func op_0ef8_40_ff;
+extern cpuop_func op_0ef9_40_nf;
+extern cpuop_func op_0ef9_40_ff;
+extern cpuop_func op_0efc_40_nf;
+extern cpuop_func op_0efc_40_ff;
+extern cpuop_func op_1000_40_nf;
+extern cpuop_func op_1000_40_ff;
+extern cpuop_func op_1010_40_nf;
+extern cpuop_func op_1010_40_ff;
+extern cpuop_func op_1018_40_nf;
+extern cpuop_func op_1018_40_ff;
+extern cpuop_func op_1020_40_nf;
+extern cpuop_func op_1020_40_ff;
+extern cpuop_func op_1028_40_nf;
+extern cpuop_func op_1028_40_ff;
+extern cpuop_func op_1030_40_nf;
+extern cpuop_func op_1030_40_ff;
+extern cpuop_func op_1038_40_nf;
+extern cpuop_func op_1038_40_ff;
+extern cpuop_func op_1039_40_nf;
+extern cpuop_func op_1039_40_ff;
+extern cpuop_func op_103a_40_nf;
+extern cpuop_func op_103a_40_ff;
+extern cpuop_func op_103b_40_nf;
+extern cpuop_func op_103b_40_ff;
+extern cpuop_func op_103c_40_nf;
+extern cpuop_func op_103c_40_ff;
+extern cpuop_func op_1080_40_nf;
+extern cpuop_func op_1080_40_ff;
+extern cpuop_func op_1090_40_nf;
+extern cpuop_func op_1090_40_ff;
+extern cpuop_func op_1098_40_nf;
+extern cpuop_func op_1098_40_ff;
+extern cpuop_func op_10a0_40_nf;
+extern cpuop_func op_10a0_40_ff;
+extern cpuop_func op_10a8_40_nf;
+extern cpuop_func op_10a8_40_ff;
+extern cpuop_func op_10b0_40_nf;
+extern cpuop_func op_10b0_40_ff;
+extern cpuop_func op_10b8_40_nf;
+extern cpuop_func op_10b8_40_ff;
+extern cpuop_func op_10b9_40_nf;
+extern cpuop_func op_10b9_40_ff;
+extern cpuop_func op_10ba_40_nf;
+extern cpuop_func op_10ba_40_ff;
+extern cpuop_func op_10bb_40_nf;
+extern cpuop_func op_10bb_40_ff;
+extern cpuop_func op_10bc_40_nf;
+extern cpuop_func op_10bc_40_ff;
+extern cpuop_func op_10c0_40_nf;
+extern cpuop_func op_10c0_40_ff;
+extern cpuop_func op_10d0_40_nf;
+extern cpuop_func op_10d0_40_ff;
+extern cpuop_func op_10d8_40_nf;
+extern cpuop_func op_10d8_40_ff;
+extern cpuop_func op_10e0_40_nf;
+extern cpuop_func op_10e0_40_ff;
+extern cpuop_func op_10e8_40_nf;
+extern cpuop_func op_10e8_40_ff;
+extern cpuop_func op_10f0_40_nf;
+extern cpuop_func op_10f0_40_ff;
+extern cpuop_func op_10f8_40_nf;
+extern cpuop_func op_10f8_40_ff;
+extern cpuop_func op_10f9_40_nf;
+extern cpuop_func op_10f9_40_ff;
+extern cpuop_func op_10fa_40_nf;
+extern cpuop_func op_10fa_40_ff;
+extern cpuop_func op_10fb_40_nf;
+extern cpuop_func op_10fb_40_ff;
+extern cpuop_func op_10fc_40_nf;
+extern cpuop_func op_10fc_40_ff;
+extern cpuop_func op_1100_40_nf;
+extern cpuop_func op_1100_40_ff;
+extern cpuop_func op_1110_40_nf;
+extern cpuop_func op_1110_40_ff;
+extern cpuop_func op_1118_40_nf;
+extern cpuop_func op_1118_40_ff;
+extern cpuop_func op_1120_40_nf;
+extern cpuop_func op_1120_40_ff;
+extern cpuop_func op_1128_40_nf;
+extern cpuop_func op_1128_40_ff;
+extern cpuop_func op_1130_40_nf;
+extern cpuop_func op_1130_40_ff;
+extern cpuop_func op_1138_40_nf;
+extern cpuop_func op_1138_40_ff;
+extern cpuop_func op_1139_40_nf;
+extern cpuop_func op_1139_40_ff;
+extern cpuop_func op_113a_40_nf;
+extern cpuop_func op_113a_40_ff;
+extern cpuop_func op_113b_40_nf;
+extern cpuop_func op_113b_40_ff;
+extern cpuop_func op_113c_40_nf;
+extern cpuop_func op_113c_40_ff;
+extern cpuop_func op_1140_40_nf;
+extern cpuop_func op_1140_40_ff;
+extern cpuop_func op_1150_40_nf;
+extern cpuop_func op_1150_40_ff;
+extern cpuop_func op_1158_40_nf;
+extern cpuop_func op_1158_40_ff;
+extern cpuop_func op_1160_40_nf;
+extern cpuop_func op_1160_40_ff;
+extern cpuop_func op_1168_40_nf;
+extern cpuop_func op_1168_40_ff;
+extern cpuop_func op_1170_40_nf;
+extern cpuop_func op_1170_40_ff;
+extern cpuop_func op_1178_40_nf;
+extern cpuop_func op_1178_40_ff;
+extern cpuop_func op_1179_40_nf;
+extern cpuop_func op_1179_40_ff;
+extern cpuop_func op_117a_40_nf;
+extern cpuop_func op_117a_40_ff;
+extern cpuop_func op_117b_40_nf;
+extern cpuop_func op_117b_40_ff;
+extern cpuop_func op_117c_40_nf;
+extern cpuop_func op_117c_40_ff;
+extern cpuop_func op_1180_40_nf;
+extern cpuop_func op_1180_40_ff;
+extern cpuop_func op_1190_40_nf;
+extern cpuop_func op_1190_40_ff;
+extern cpuop_func op_1198_40_nf;
+extern cpuop_func op_1198_40_ff;
+extern cpuop_func op_11a0_40_nf;
+extern cpuop_func op_11a0_40_ff;
+extern cpuop_func op_11a8_40_nf;
+extern cpuop_func op_11a8_40_ff;
+extern cpuop_func op_11b0_40_nf;
+extern cpuop_func op_11b0_40_ff;
+extern cpuop_func op_11b8_40_nf;
+extern cpuop_func op_11b8_40_ff;
+extern cpuop_func op_11b9_40_nf;
+extern cpuop_func op_11b9_40_ff;
+extern cpuop_func op_11ba_40_nf;
+extern cpuop_func op_11ba_40_ff;
+extern cpuop_func op_11bb_40_nf;
+extern cpuop_func op_11bb_40_ff;
+extern cpuop_func op_11bc_40_nf;
+extern cpuop_func op_11bc_40_ff;
+extern cpuop_func op_11c0_40_nf;
+extern cpuop_func op_11c0_40_ff;
+extern cpuop_func op_11d0_40_nf;
+extern cpuop_func op_11d0_40_ff;
+extern cpuop_func op_11d8_40_nf;
+extern cpuop_func op_11d8_40_ff;
+extern cpuop_func op_11e0_40_nf;
+extern cpuop_func op_11e0_40_ff;
+extern cpuop_func op_11e8_40_nf;
+extern cpuop_func op_11e8_40_ff;
+extern cpuop_func op_11f0_40_nf;
+extern cpuop_func op_11f0_40_ff;
+extern cpuop_func op_11f8_40_nf;
+extern cpuop_func op_11f8_40_ff;
+extern cpuop_func op_11f9_40_nf;
+extern cpuop_func op_11f9_40_ff;
+extern cpuop_func op_11fa_40_nf;
+extern cpuop_func op_11fa_40_ff;
+extern cpuop_func op_11fb_40_nf;
+extern cpuop_func op_11fb_40_ff;
+extern cpuop_func op_11fc_40_nf;
+extern cpuop_func op_11fc_40_ff;
+extern cpuop_func op_13c0_40_nf;
+extern cpuop_func op_13c0_40_ff;
+extern cpuop_func op_13d0_40_nf;
+extern cpuop_func op_13d0_40_ff;
+extern cpuop_func op_13d8_40_nf;
+extern cpuop_func op_13d8_40_ff;
+extern cpuop_func op_13e0_40_nf;
+extern cpuop_func op_13e0_40_ff;
+extern cpuop_func op_13e8_40_nf;
+extern cpuop_func op_13e8_40_ff;
+extern cpuop_func op_13f0_40_nf;
+extern cpuop_func op_13f0_40_ff;
+extern cpuop_func op_13f8_40_nf;
+extern cpuop_func op_13f8_40_ff;
+extern cpuop_func op_13f9_40_nf;
+extern cpuop_func op_13f9_40_ff;
+extern cpuop_func op_13fa_40_nf;
+extern cpuop_func op_13fa_40_ff;
+extern cpuop_func op_13fb_40_nf;
+extern cpuop_func op_13fb_40_ff;
+extern cpuop_func op_13fc_40_nf;
+extern cpuop_func op_13fc_40_ff;
+extern cpuop_func op_2000_40_nf;
+extern cpuop_func op_2000_40_ff;
+extern cpuop_func op_2008_40_nf;
+extern cpuop_func op_2008_40_ff;
+extern cpuop_func op_2010_40_nf;
+extern cpuop_func op_2010_40_ff;
+extern cpuop_func op_2018_40_nf;
+extern cpuop_func op_2018_40_ff;
+extern cpuop_func op_2020_40_nf;
+extern cpuop_func op_2020_40_ff;
+extern cpuop_func op_2028_40_nf;
+extern cpuop_func op_2028_40_ff;
+extern cpuop_func op_2030_40_nf;
+extern cpuop_func op_2030_40_ff;
+extern cpuop_func op_2038_40_nf;
+extern cpuop_func op_2038_40_ff;
+extern cpuop_func op_2039_40_nf;
+extern cpuop_func op_2039_40_ff;
+extern cpuop_func op_203a_40_nf;
+extern cpuop_func op_203a_40_ff;
+extern cpuop_func op_203b_40_nf;
+extern cpuop_func op_203b_40_ff;
+extern cpuop_func op_203c_40_nf;
+extern cpuop_func op_203c_40_ff;
+extern cpuop_func op_2040_40_nf;
+extern cpuop_func op_2040_40_ff;
+extern cpuop_func op_2048_40_nf;
+extern cpuop_func op_2048_40_ff;
+extern cpuop_func op_2050_40_nf;
+extern cpuop_func op_2050_40_ff;
+extern cpuop_func op_2058_40_nf;
+extern cpuop_func op_2058_40_ff;
+extern cpuop_func op_2060_40_nf;
+extern cpuop_func op_2060_40_ff;
+extern cpuop_func op_2068_40_nf;
+extern cpuop_func op_2068_40_ff;
+extern cpuop_func op_2070_40_nf;
+extern cpuop_func op_2070_40_ff;
+extern cpuop_func op_2078_40_nf;
+extern cpuop_func op_2078_40_ff;
+extern cpuop_func op_2079_40_nf;
+extern cpuop_func op_2079_40_ff;
+extern cpuop_func op_207a_40_nf;
+extern cpuop_func op_207a_40_ff;
+extern cpuop_func op_207b_40_nf;
+extern cpuop_func op_207b_40_ff;
+extern cpuop_func op_207c_40_nf;
+extern cpuop_func op_207c_40_ff;
+extern cpuop_func op_2080_40_nf;
+extern cpuop_func op_2080_40_ff;
+extern cpuop_func op_2088_40_nf;
+extern cpuop_func op_2088_40_ff;
+extern cpuop_func op_2090_40_nf;
+extern cpuop_func op_2090_40_ff;
+extern cpuop_func op_2098_40_nf;
+extern cpuop_func op_2098_40_ff;
+extern cpuop_func op_20a0_40_nf;
+extern cpuop_func op_20a0_40_ff;
+extern cpuop_func op_20a8_40_nf;
+extern cpuop_func op_20a8_40_ff;
+extern cpuop_func op_20b0_40_nf;
+extern cpuop_func op_20b0_40_ff;
+extern cpuop_func op_20b8_40_nf;
+extern cpuop_func op_20b8_40_ff;
+extern cpuop_func op_20b9_40_nf;
+extern cpuop_func op_20b9_40_ff;
+extern cpuop_func op_20ba_40_nf;
+extern cpuop_func op_20ba_40_ff;
+extern cpuop_func op_20bb_40_nf;
+extern cpuop_func op_20bb_40_ff;
+extern cpuop_func op_20bc_40_nf;
+extern cpuop_func op_20bc_40_ff;
+extern cpuop_func op_20c0_40_nf;
+extern cpuop_func op_20c0_40_ff;
+extern cpuop_func op_20c8_40_nf;
+extern cpuop_func op_20c8_40_ff;
+extern cpuop_func op_20d0_40_nf;
+extern cpuop_func op_20d0_40_ff;
+extern cpuop_func op_20d8_40_nf;
+extern cpuop_func op_20d8_40_ff;
+extern cpuop_func op_20e0_40_nf;
+extern cpuop_func op_20e0_40_ff;
+extern cpuop_func op_20e8_40_nf;
+extern cpuop_func op_20e8_40_ff;
+extern cpuop_func op_20f0_40_nf;
+extern cpuop_func op_20f0_40_ff;
+extern cpuop_func op_20f8_40_nf;
+extern cpuop_func op_20f8_40_ff;
+extern cpuop_func op_20f9_40_nf;
+extern cpuop_func op_20f9_40_ff;
+extern cpuop_func op_20fa_40_nf;
+extern cpuop_func op_20fa_40_ff;
+extern cpuop_func op_20fb_40_nf;
+extern cpuop_func op_20fb_40_ff;
+extern cpuop_func op_20fc_40_nf;
+extern cpuop_func op_20fc_40_ff;
+extern cpuop_func op_2100_40_nf;
+extern cpuop_func op_2100_40_ff;
+extern cpuop_func op_2108_40_nf;
+extern cpuop_func op_2108_40_ff;
+extern cpuop_func op_2110_40_nf;
+extern cpuop_func op_2110_40_ff;
+extern cpuop_func op_2118_40_nf;
+extern cpuop_func op_2118_40_ff;
+extern cpuop_func op_2120_40_nf;
+extern cpuop_func op_2120_40_ff;
+extern cpuop_func op_2128_40_nf;
+extern cpuop_func op_2128_40_ff;
+extern cpuop_func op_2130_40_nf;
+extern cpuop_func op_2130_40_ff;
+extern cpuop_func op_2138_40_nf;
+extern cpuop_func op_2138_40_ff;
+extern cpuop_func op_2139_40_nf;
+extern cpuop_func op_2139_40_ff;
+extern cpuop_func op_213a_40_nf;
+extern cpuop_func op_213a_40_ff;
+extern cpuop_func op_213b_40_nf;
+extern cpuop_func op_213b_40_ff;
+extern cpuop_func op_213c_40_nf;
+extern cpuop_func op_213c_40_ff;
+extern cpuop_func op_2140_40_nf;
+extern cpuop_func op_2140_40_ff;
+extern cpuop_func op_2148_40_nf;
+extern cpuop_func op_2148_40_ff;
+extern cpuop_func op_2150_40_nf;
+extern cpuop_func op_2150_40_ff;
+extern cpuop_func op_2158_40_nf;
+extern cpuop_func op_2158_40_ff;
+extern cpuop_func op_2160_40_nf;
+extern cpuop_func op_2160_40_ff;
+extern cpuop_func op_2168_40_nf;
+extern cpuop_func op_2168_40_ff;
+extern cpuop_func op_2170_40_nf;
+extern cpuop_func op_2170_40_ff;
+extern cpuop_func op_2178_40_nf;
+extern cpuop_func op_2178_40_ff;
+extern cpuop_func op_2179_40_nf;
+extern cpuop_func op_2179_40_ff;
+extern cpuop_func op_217a_40_nf;
+extern cpuop_func op_217a_40_ff;
+extern cpuop_func op_217b_40_nf;
+extern cpuop_func op_217b_40_ff;
+extern cpuop_func op_217c_40_nf;
+extern cpuop_func op_217c_40_ff;
+extern cpuop_func op_2180_40_nf;
+extern cpuop_func op_2180_40_ff;
+extern cpuop_func op_2188_40_nf;
+extern cpuop_func op_2188_40_ff;
+extern cpuop_func op_2190_40_nf;
+extern cpuop_func op_2190_40_ff;
+extern cpuop_func op_2198_40_nf;
+extern cpuop_func op_2198_40_ff;
+extern cpuop_func op_21a0_40_nf;
+extern cpuop_func op_21a0_40_ff;
+extern cpuop_func op_21a8_40_nf;
+extern cpuop_func op_21a8_40_ff;
+extern cpuop_func op_21b0_40_nf;
+extern cpuop_func op_21b0_40_ff;
+extern cpuop_func op_21b8_40_nf;
+extern cpuop_func op_21b8_40_ff;
+extern cpuop_func op_21b9_40_nf;
+extern cpuop_func op_21b9_40_ff;
+extern cpuop_func op_21ba_40_nf;
+extern cpuop_func op_21ba_40_ff;
+extern cpuop_func op_21bb_40_nf;
+extern cpuop_func op_21bb_40_ff;
+extern cpuop_func op_21bc_40_nf;
+extern cpuop_func op_21bc_40_ff;
+extern cpuop_func op_21c0_40_nf;
+extern cpuop_func op_21c0_40_ff;
+extern cpuop_func op_21c8_40_nf;
+extern cpuop_func op_21c8_40_ff;
+extern cpuop_func op_21d0_40_nf;
+extern cpuop_func op_21d0_40_ff;
+extern cpuop_func op_21d8_40_nf;
+extern cpuop_func op_21d8_40_ff;
+extern cpuop_func op_21e0_40_nf;
+extern cpuop_func op_21e0_40_ff;
+extern cpuop_func op_21e8_40_nf;
+extern cpuop_func op_21e8_40_ff;
+extern cpuop_func op_21f0_40_nf;
+extern cpuop_func op_21f0_40_ff;
+extern cpuop_func op_21f8_40_nf;
+extern cpuop_func op_21f8_40_ff;
+extern cpuop_func op_21f9_40_nf;
+extern cpuop_func op_21f9_40_ff;
+extern cpuop_func op_21fa_40_nf;
+extern cpuop_func op_21fa_40_ff;
+extern cpuop_func op_21fb_40_nf;
+extern cpuop_func op_21fb_40_ff;
+extern cpuop_func op_21fc_40_nf;
+extern cpuop_func op_21fc_40_ff;
+extern cpuop_func op_23c0_40_nf;
+extern cpuop_func op_23c0_40_ff;
+extern cpuop_func op_23c8_40_nf;
+extern cpuop_func op_23c8_40_ff;
+extern cpuop_func op_23d0_40_nf;
+extern cpuop_func op_23d0_40_ff;
+extern cpuop_func op_23d8_40_nf;
+extern cpuop_func op_23d8_40_ff;
+extern cpuop_func op_23e0_40_nf;
+extern cpuop_func op_23e0_40_ff;
+extern cpuop_func op_23e8_40_nf;
+extern cpuop_func op_23e8_40_ff;
+extern cpuop_func op_23f0_40_nf;
+extern cpuop_func op_23f0_40_ff;
+extern cpuop_func op_23f8_40_nf;
+extern cpuop_func op_23f8_40_ff;
+extern cpuop_func op_23f9_40_nf;
+extern cpuop_func op_23f9_40_ff;
+extern cpuop_func op_23fa_40_nf;
+extern cpuop_func op_23fa_40_ff;
+extern cpuop_func op_23fb_40_nf;
+extern cpuop_func op_23fb_40_ff;
+extern cpuop_func op_23fc_40_nf;
+extern cpuop_func op_23fc_40_ff;
+extern cpuop_func op_3000_40_nf;
+extern cpuop_func op_3000_40_ff;
+extern cpuop_func op_3008_40_nf;
+extern cpuop_func op_3008_40_ff;
+extern cpuop_func op_3010_40_nf;
+extern cpuop_func op_3010_40_ff;
+extern cpuop_func op_3018_40_nf;
+extern cpuop_func op_3018_40_ff;
+extern cpuop_func op_3020_40_nf;
+extern cpuop_func op_3020_40_ff;
+extern cpuop_func op_3028_40_nf;
+extern cpuop_func op_3028_40_ff;
+extern cpuop_func op_3030_40_nf;
+extern cpuop_func op_3030_40_ff;
+extern cpuop_func op_3038_40_nf;
+extern cpuop_func op_3038_40_ff;
+extern cpuop_func op_3039_40_nf;
+extern cpuop_func op_3039_40_ff;
+extern cpuop_func op_303a_40_nf;
+extern cpuop_func op_303a_40_ff;
+extern cpuop_func op_303b_40_nf;
+extern cpuop_func op_303b_40_ff;
+extern cpuop_func op_303c_40_nf;
+extern cpuop_func op_303c_40_ff;
+extern cpuop_func op_3040_40_nf;
+extern cpuop_func op_3040_40_ff;
+extern cpuop_func op_3048_40_nf;
+extern cpuop_func op_3048_40_ff;
+extern cpuop_func op_3050_40_nf;
+extern cpuop_func op_3050_40_ff;
+extern cpuop_func op_3058_40_nf;
+extern cpuop_func op_3058_40_ff;
+extern cpuop_func op_3060_40_nf;
+extern cpuop_func op_3060_40_ff;
+extern cpuop_func op_3068_40_nf;
+extern cpuop_func op_3068_40_ff;
+extern cpuop_func op_3070_40_nf;
+extern cpuop_func op_3070_40_ff;
+extern cpuop_func op_3078_40_nf;
+extern cpuop_func op_3078_40_ff;
+extern cpuop_func op_3079_40_nf;
+extern cpuop_func op_3079_40_ff;
+extern cpuop_func op_307a_40_nf;
+extern cpuop_func op_307a_40_ff;
+extern cpuop_func op_307b_40_nf;
+extern cpuop_func op_307b_40_ff;
+extern cpuop_func op_307c_40_nf;
+extern cpuop_func op_307c_40_ff;
+extern cpuop_func op_3080_40_nf;
+extern cpuop_func op_3080_40_ff;
+extern cpuop_func op_3088_40_nf;
+extern cpuop_func op_3088_40_ff;
+extern cpuop_func op_3090_40_nf;
+extern cpuop_func op_3090_40_ff;
+extern cpuop_func op_3098_40_nf;
+extern cpuop_func op_3098_40_ff;
+extern cpuop_func op_30a0_40_nf;
+extern cpuop_func op_30a0_40_ff;
+extern cpuop_func op_30a8_40_nf;
+extern cpuop_func op_30a8_40_ff;
+extern cpuop_func op_30b0_40_nf;
+extern cpuop_func op_30b0_40_ff;
+extern cpuop_func op_30b8_40_nf;
+extern cpuop_func op_30b8_40_ff;
+extern cpuop_func op_30b9_40_nf;
+extern cpuop_func op_30b9_40_ff;
+extern cpuop_func op_30ba_40_nf;
+extern cpuop_func op_30ba_40_ff;
+extern cpuop_func op_30bb_40_nf;
+extern cpuop_func op_30bb_40_ff;
+extern cpuop_func op_30bc_40_nf;
+extern cpuop_func op_30bc_40_ff;
+extern cpuop_func op_30c0_40_nf;
+extern cpuop_func op_30c0_40_ff;
+extern cpuop_func op_30c8_40_nf;
+extern cpuop_func op_30c8_40_ff;
+extern cpuop_func op_30d0_40_nf;
+extern cpuop_func op_30d0_40_ff;
+extern cpuop_func op_30d8_40_nf;
+extern cpuop_func op_30d8_40_ff;
+extern cpuop_func op_30e0_40_nf;
+extern cpuop_func op_30e0_40_ff;
+extern cpuop_func op_30e8_40_nf;
+extern cpuop_func op_30e8_40_ff;
+extern cpuop_func op_30f0_40_nf;
+extern cpuop_func op_30f0_40_ff;
+extern cpuop_func op_30f8_40_nf;
+extern cpuop_func op_30f8_40_ff;
+extern cpuop_func op_30f9_40_nf;
+extern cpuop_func op_30f9_40_ff;
+extern cpuop_func op_30fa_40_nf;
+extern cpuop_func op_30fa_40_ff;
+extern cpuop_func op_30fb_40_nf;
+extern cpuop_func op_30fb_40_ff;
+extern cpuop_func op_30fc_40_nf;
+extern cpuop_func op_30fc_40_ff;
+extern cpuop_func op_3100_40_nf;
+extern cpuop_func op_3100_40_ff;
+extern cpuop_func op_3108_40_nf;
+extern cpuop_func op_3108_40_ff;
+extern cpuop_func op_3110_40_nf;
+extern cpuop_func op_3110_40_ff;
+extern cpuop_func op_3118_40_nf;
+extern cpuop_func op_3118_40_ff;
+extern cpuop_func op_3120_40_nf;
+extern cpuop_func op_3120_40_ff;
+extern cpuop_func op_3128_40_nf;
+extern cpuop_func op_3128_40_ff;
+extern cpuop_func op_3130_40_nf;
+extern cpuop_func op_3130_40_ff;
+extern cpuop_func op_3138_40_nf;
+extern cpuop_func op_3138_40_ff;
+extern cpuop_func op_3139_40_nf;
+extern cpuop_func op_3139_40_ff;
+extern cpuop_func op_313a_40_nf;
+extern cpuop_func op_313a_40_ff;
+extern cpuop_func op_313b_40_nf;
+extern cpuop_func op_313b_40_ff;
+extern cpuop_func op_313c_40_nf;
+extern cpuop_func op_313c_40_ff;
+extern cpuop_func op_3140_40_nf;
+extern cpuop_func op_3140_40_ff;
+extern cpuop_func op_3148_40_nf;
+extern cpuop_func op_3148_40_ff;
+extern cpuop_func op_3150_40_nf;
+extern cpuop_func op_3150_40_ff;
+extern cpuop_func op_3158_40_nf;
+extern cpuop_func op_3158_40_ff;
+extern cpuop_func op_3160_40_nf;
+extern cpuop_func op_3160_40_ff;
+extern cpuop_func op_3168_40_nf;
+extern cpuop_func op_3168_40_ff;
+extern cpuop_func op_3170_40_nf;
+extern cpuop_func op_3170_40_ff;
+extern cpuop_func op_3178_40_nf;
+extern cpuop_func op_3178_40_ff;
+extern cpuop_func op_3179_40_nf;
+extern cpuop_func op_3179_40_ff;
+extern cpuop_func op_317a_40_nf;
+extern cpuop_func op_317a_40_ff;
+extern cpuop_func op_317b_40_nf;
+extern cpuop_func op_317b_40_ff;
+extern cpuop_func op_317c_40_nf;
+extern cpuop_func op_317c_40_ff;
+extern cpuop_func op_3180_40_nf;
+extern cpuop_func op_3180_40_ff;
+extern cpuop_func op_3188_40_nf;
+extern cpuop_func op_3188_40_ff;
+extern cpuop_func op_3190_40_nf;
+extern cpuop_func op_3190_40_ff;
+extern cpuop_func op_3198_40_nf;
+extern cpuop_func op_3198_40_ff;
+extern cpuop_func op_31a0_40_nf;
+extern cpuop_func op_31a0_40_ff;
+extern cpuop_func op_31a8_40_nf;
+extern cpuop_func op_31a8_40_ff;
+extern cpuop_func op_31b0_40_nf;
+extern cpuop_func op_31b0_40_ff;
+extern cpuop_func op_31b8_40_nf;
+extern cpuop_func op_31b8_40_ff;
+extern cpuop_func op_31b9_40_nf;
+extern cpuop_func op_31b9_40_ff;
+extern cpuop_func op_31ba_40_nf;
+extern cpuop_func op_31ba_40_ff;
+extern cpuop_func op_31bb_40_nf;
+extern cpuop_func op_31bb_40_ff;
+extern cpuop_func op_31bc_40_nf;
+extern cpuop_func op_31bc_40_ff;
+extern cpuop_func op_31c0_40_nf;
+extern cpuop_func op_31c0_40_ff;
+extern cpuop_func op_31c8_40_nf;
+extern cpuop_func op_31c8_40_ff;
+extern cpuop_func op_31d0_40_nf;
+extern cpuop_func op_31d0_40_ff;
+extern cpuop_func op_31d8_40_nf;
+extern cpuop_func op_31d8_40_ff;
+extern cpuop_func op_31e0_40_nf;
+extern cpuop_func op_31e0_40_ff;
+extern cpuop_func op_31e8_40_nf;
+extern cpuop_func op_31e8_40_ff;
+extern cpuop_func op_31f0_40_nf;
+extern cpuop_func op_31f0_40_ff;
+extern cpuop_func op_31f8_40_nf;
+extern cpuop_func op_31f8_40_ff;
+extern cpuop_func op_31f9_40_nf;
+extern cpuop_func op_31f9_40_ff;
+extern cpuop_func op_31fa_40_nf;
+extern cpuop_func op_31fa_40_ff;
+extern cpuop_func op_31fb_40_nf;
+extern cpuop_func op_31fb_40_ff;
+extern cpuop_func op_31fc_40_nf;
+extern cpuop_func op_31fc_40_ff;
+extern cpuop_func op_33c0_40_nf;
+extern cpuop_func op_33c0_40_ff;
+extern cpuop_func op_33c8_40_nf;
+extern cpuop_func op_33c8_40_ff;
+extern cpuop_func op_33d0_40_nf;
+extern cpuop_func op_33d0_40_ff;
+extern cpuop_func op_33d8_40_nf;
+extern cpuop_func op_33d8_40_ff;
+extern cpuop_func op_33e0_40_nf;
+extern cpuop_func op_33e0_40_ff;
+extern cpuop_func op_33e8_40_nf;
+extern cpuop_func op_33e8_40_ff;
+extern cpuop_func op_33f0_40_nf;
+extern cpuop_func op_33f0_40_ff;
+extern cpuop_func op_33f8_40_nf;
+extern cpuop_func op_33f8_40_ff;
+extern cpuop_func op_33f9_40_nf;
+extern cpuop_func op_33f9_40_ff;
+extern cpuop_func op_33fa_40_nf;
+extern cpuop_func op_33fa_40_ff;
+extern cpuop_func op_33fb_40_nf;
+extern cpuop_func op_33fb_40_ff;
+extern cpuop_func op_33fc_40_nf;
+extern cpuop_func op_33fc_40_ff;
+extern cpuop_func op_4000_40_nf;
+extern cpuop_func op_4000_40_ff;
+extern cpuop_func op_4010_40_nf;
+extern cpuop_func op_4010_40_ff;
+extern cpuop_func op_4018_40_nf;
+extern cpuop_func op_4018_40_ff;
+extern cpuop_func op_4020_40_nf;
+extern cpuop_func op_4020_40_ff;
+extern cpuop_func op_4028_40_nf;
+extern cpuop_func op_4028_40_ff;
+extern cpuop_func op_4030_40_nf;
+extern cpuop_func op_4030_40_ff;
+extern cpuop_func op_4038_40_nf;
+extern cpuop_func op_4038_40_ff;
+extern cpuop_func op_4039_40_nf;
+extern cpuop_func op_4039_40_ff;
+extern cpuop_func op_4040_40_nf;
+extern cpuop_func op_4040_40_ff;
+extern cpuop_func op_4050_40_nf;
+extern cpuop_func op_4050_40_ff;
+extern cpuop_func op_4058_40_nf;
+extern cpuop_func op_4058_40_ff;
+extern cpuop_func op_4060_40_nf;
+extern cpuop_func op_4060_40_ff;
+extern cpuop_func op_4068_40_nf;
+extern cpuop_func op_4068_40_ff;
+extern cpuop_func op_4070_40_nf;
+extern cpuop_func op_4070_40_ff;
+extern cpuop_func op_4078_40_nf;
+extern cpuop_func op_4078_40_ff;
+extern cpuop_func op_4079_40_nf;
+extern cpuop_func op_4079_40_ff;
+extern cpuop_func op_4080_40_nf;
+extern cpuop_func op_4080_40_ff;
+extern cpuop_func op_4090_40_nf;
+extern cpuop_func op_4090_40_ff;
+extern cpuop_func op_4098_40_nf;
+extern cpuop_func op_4098_40_ff;
+extern cpuop_func op_40a0_40_nf;
+extern cpuop_func op_40a0_40_ff;
+extern cpuop_func op_40a8_40_nf;
+extern cpuop_func op_40a8_40_ff;
+extern cpuop_func op_40b0_40_nf;
+extern cpuop_func op_40b0_40_ff;
+extern cpuop_func op_40b8_40_nf;
+extern cpuop_func op_40b8_40_ff;
+extern cpuop_func op_40b9_40_nf;
+extern cpuop_func op_40b9_40_ff;
+extern cpuop_func op_40c0_40_nf;
+extern cpuop_func op_40c0_40_ff;
+extern cpuop_func op_40d0_40_nf;
+extern cpuop_func op_40d0_40_ff;
+extern cpuop_func op_40d8_40_nf;
+extern cpuop_func op_40d8_40_ff;
+extern cpuop_func op_40e0_40_nf;
+extern cpuop_func op_40e0_40_ff;
+extern cpuop_func op_40e8_40_nf;
+extern cpuop_func op_40e8_40_ff;
+extern cpuop_func op_40f0_40_nf;
+extern cpuop_func op_40f0_40_ff;
+extern cpuop_func op_40f8_40_nf;
+extern cpuop_func op_40f8_40_ff;
+extern cpuop_func op_40f9_40_nf;
+extern cpuop_func op_40f9_40_ff;
+extern cpuop_func op_4100_40_nf;
+extern cpuop_func op_4100_40_ff;
+extern cpuop_func op_4110_40_nf;
+extern cpuop_func op_4110_40_ff;
+extern cpuop_func op_4118_40_nf;
+extern cpuop_func op_4118_40_ff;
+extern cpuop_func op_4120_40_nf;
+extern cpuop_func op_4120_40_ff;
+extern cpuop_func op_4128_40_nf;
+extern cpuop_func op_4128_40_ff;
+extern cpuop_func op_4130_40_nf;
+extern cpuop_func op_4130_40_ff;
+extern cpuop_func op_4138_40_nf;
+extern cpuop_func op_4138_40_ff;
+extern cpuop_func op_4139_40_nf;
+extern cpuop_func op_4139_40_ff;
+extern cpuop_func op_413a_40_nf;
+extern cpuop_func op_413a_40_ff;
+extern cpuop_func op_413b_40_nf;
+extern cpuop_func op_413b_40_ff;
+extern cpuop_func op_413c_40_nf;
+extern cpuop_func op_413c_40_ff;
+extern cpuop_func op_4180_40_nf;
+extern cpuop_func op_4180_40_ff;
+extern cpuop_func op_4190_40_nf;
+extern cpuop_func op_4190_40_ff;
+extern cpuop_func op_4198_40_nf;
+extern cpuop_func op_4198_40_ff;
+extern cpuop_func op_41a0_40_nf;
+extern cpuop_func op_41a0_40_ff;
+extern cpuop_func op_41a8_40_nf;
+extern cpuop_func op_41a8_40_ff;
+extern cpuop_func op_41b0_40_nf;
+extern cpuop_func op_41b0_40_ff;
+extern cpuop_func op_41b8_40_nf;
+extern cpuop_func op_41b8_40_ff;
+extern cpuop_func op_41b9_40_nf;
+extern cpuop_func op_41b9_40_ff;
+extern cpuop_func op_41ba_40_nf;
+extern cpuop_func op_41ba_40_ff;
+extern cpuop_func op_41bb_40_nf;
+extern cpuop_func op_41bb_40_ff;
+extern cpuop_func op_41bc_40_nf;
+extern cpuop_func op_41bc_40_ff;
+extern cpuop_func op_41d0_40_nf;
+extern cpuop_func op_41d0_40_ff;
+extern cpuop_func op_41e8_40_nf;
+extern cpuop_func op_41e8_40_ff;
+extern cpuop_func op_41f0_40_nf;
+extern cpuop_func op_41f0_40_ff;
+extern cpuop_func op_41f8_40_nf;
+extern cpuop_func op_41f8_40_ff;
+extern cpuop_func op_41f9_40_nf;
+extern cpuop_func op_41f9_40_ff;
+extern cpuop_func op_41fa_40_nf;
+extern cpuop_func op_41fa_40_ff;
+extern cpuop_func op_41fb_40_nf;
+extern cpuop_func op_41fb_40_ff;
+extern cpuop_func op_4200_40_nf;
+extern cpuop_func op_4200_40_ff;
+extern cpuop_func op_4210_40_nf;
+extern cpuop_func op_4210_40_ff;
+extern cpuop_func op_4218_40_nf;
+extern cpuop_func op_4218_40_ff;
+extern cpuop_func op_4220_40_nf;
+extern cpuop_func op_4220_40_ff;
+extern cpuop_func op_4228_40_nf;
+extern cpuop_func op_4228_40_ff;
+extern cpuop_func op_4230_40_nf;
+extern cpuop_func op_4230_40_ff;
+extern cpuop_func op_4238_40_nf;
+extern cpuop_func op_4238_40_ff;
+extern cpuop_func op_4239_40_nf;
+extern cpuop_func op_4239_40_ff;
+extern cpuop_func op_4240_40_nf;
+extern cpuop_func op_4240_40_ff;
+extern cpuop_func op_4250_40_nf;
+extern cpuop_func op_4250_40_ff;
+extern cpuop_func op_4258_40_nf;
+extern cpuop_func op_4258_40_ff;
+extern cpuop_func op_4260_40_nf;
+extern cpuop_func op_4260_40_ff;
+extern cpuop_func op_4268_40_nf;
+extern cpuop_func op_4268_40_ff;
+extern cpuop_func op_4270_40_nf;
+extern cpuop_func op_4270_40_ff;
+extern cpuop_func op_4278_40_nf;
+extern cpuop_func op_4278_40_ff;
+extern cpuop_func op_4279_40_nf;
+extern cpuop_func op_4279_40_ff;
+extern cpuop_func op_4280_40_nf;
+extern cpuop_func op_4280_40_ff;
+extern cpuop_func op_4290_40_nf;
+extern cpuop_func op_4290_40_ff;
+extern cpuop_func op_4298_40_nf;
+extern cpuop_func op_4298_40_ff;
+extern cpuop_func op_42a0_40_nf;
+extern cpuop_func op_42a0_40_ff;
+extern cpuop_func op_42a8_40_nf;
+extern cpuop_func op_42a8_40_ff;
+extern cpuop_func op_42b0_40_nf;
+extern cpuop_func op_42b0_40_ff;
+extern cpuop_func op_42b8_40_nf;
+extern cpuop_func op_42b8_40_ff;
+extern cpuop_func op_42b9_40_nf;
+extern cpuop_func op_42b9_40_ff;
+extern cpuop_func op_42c0_40_nf;
+extern cpuop_func op_42c0_40_ff;
+extern cpuop_func op_42d0_40_nf;
+extern cpuop_func op_42d0_40_ff;
+extern cpuop_func op_42d8_40_nf;
+extern cpuop_func op_42d8_40_ff;
+extern cpuop_func op_42e0_40_nf;
+extern cpuop_func op_42e0_40_ff;
+extern cpuop_func op_42e8_40_nf;
+extern cpuop_func op_42e8_40_ff;
+extern cpuop_func op_42f0_40_nf;
+extern cpuop_func op_42f0_40_ff;
+extern cpuop_func op_42f8_40_nf;
+extern cpuop_func op_42f8_40_ff;
+extern cpuop_func op_42f9_40_nf;
+extern cpuop_func op_42f9_40_ff;
+extern cpuop_func op_4400_40_nf;
+extern cpuop_func op_4400_40_ff;
+extern cpuop_func op_4410_40_nf;
+extern cpuop_func op_4410_40_ff;
+extern cpuop_func op_4418_40_nf;
+extern cpuop_func op_4418_40_ff;
+extern cpuop_func op_4420_40_nf;
+extern cpuop_func op_4420_40_ff;
+extern cpuop_func op_4428_40_nf;
+extern cpuop_func op_4428_40_ff;
+extern cpuop_func op_4430_40_nf;
+extern cpuop_func op_4430_40_ff;
+extern cpuop_func op_4438_40_nf;
+extern cpuop_func op_4438_40_ff;
+extern cpuop_func op_4439_40_nf;
+extern cpuop_func op_4439_40_ff;
+extern cpuop_func op_4440_40_nf;
+extern cpuop_func op_4440_40_ff;
+extern cpuop_func op_4450_40_nf;
+extern cpuop_func op_4450_40_ff;
+extern cpuop_func op_4458_40_nf;
+extern cpuop_func op_4458_40_ff;
+extern cpuop_func op_4460_40_nf;
+extern cpuop_func op_4460_40_ff;
+extern cpuop_func op_4468_40_nf;
+extern cpuop_func op_4468_40_ff;
+extern cpuop_func op_4470_40_nf;
+extern cpuop_func op_4470_40_ff;
+extern cpuop_func op_4478_40_nf;
+extern cpuop_func op_4478_40_ff;
+extern cpuop_func op_4479_40_nf;
+extern cpuop_func op_4479_40_ff;
+extern cpuop_func op_4480_40_nf;
+extern cpuop_func op_4480_40_ff;
+extern cpuop_func op_4490_40_nf;
+extern cpuop_func op_4490_40_ff;
+extern cpuop_func op_4498_40_nf;
+extern cpuop_func op_4498_40_ff;
+extern cpuop_func op_44a0_40_nf;
+extern cpuop_func op_44a0_40_ff;
+extern cpuop_func op_44a8_40_nf;
+extern cpuop_func op_44a8_40_ff;
+extern cpuop_func op_44b0_40_nf;
+extern cpuop_func op_44b0_40_ff;
+extern cpuop_func op_44b8_40_nf;
+extern cpuop_func op_44b8_40_ff;
+extern cpuop_func op_44b9_40_nf;
+extern cpuop_func op_44b9_40_ff;
+extern cpuop_func op_44c0_40_nf;
+extern cpuop_func op_44c0_40_ff;
+extern cpuop_func op_44d0_40_nf;
+extern cpuop_func op_44d0_40_ff;
+extern cpuop_func op_44d8_40_nf;
+extern cpuop_func op_44d8_40_ff;
+extern cpuop_func op_44e0_40_nf;
+extern cpuop_func op_44e0_40_ff;
+extern cpuop_func op_44e8_40_nf;
+extern cpuop_func op_44e8_40_ff;
+extern cpuop_func op_44f0_40_nf;
+extern cpuop_func op_44f0_40_ff;
+extern cpuop_func op_44f8_40_nf;
+extern cpuop_func op_44f8_40_ff;
+extern cpuop_func op_44f9_40_nf;
+extern cpuop_func op_44f9_40_ff;
+extern cpuop_func op_44fa_40_nf;
+extern cpuop_func op_44fa_40_ff;
+extern cpuop_func op_44fb_40_nf;
+extern cpuop_func op_44fb_40_ff;
+extern cpuop_func op_44fc_40_nf;
+extern cpuop_func op_44fc_40_ff;
+extern cpuop_func op_4600_40_nf;
+extern cpuop_func op_4600_40_ff;
+extern cpuop_func op_4610_40_nf;
+extern cpuop_func op_4610_40_ff;
+extern cpuop_func op_4618_40_nf;
+extern cpuop_func op_4618_40_ff;
+extern cpuop_func op_4620_40_nf;
+extern cpuop_func op_4620_40_ff;
+extern cpuop_func op_4628_40_nf;
+extern cpuop_func op_4628_40_ff;
+extern cpuop_func op_4630_40_nf;
+extern cpuop_func op_4630_40_ff;
+extern cpuop_func op_4638_40_nf;
+extern cpuop_func op_4638_40_ff;
+extern cpuop_func op_4639_40_nf;
+extern cpuop_func op_4639_40_ff;
+extern cpuop_func op_4640_40_nf;
+extern cpuop_func op_4640_40_ff;
+extern cpuop_func op_4650_40_nf;
+extern cpuop_func op_4650_40_ff;
+extern cpuop_func op_4658_40_nf;
+extern cpuop_func op_4658_40_ff;
+extern cpuop_func op_4660_40_nf;
+extern cpuop_func op_4660_40_ff;
+extern cpuop_func op_4668_40_nf;
+extern cpuop_func op_4668_40_ff;
+extern cpuop_func op_4670_40_nf;
+extern cpuop_func op_4670_40_ff;
+extern cpuop_func op_4678_40_nf;
+extern cpuop_func op_4678_40_ff;
+extern cpuop_func op_4679_40_nf;
+extern cpuop_func op_4679_40_ff;
+extern cpuop_func op_4680_40_nf;
+extern cpuop_func op_4680_40_ff;
+extern cpuop_func op_4690_40_nf;
+extern cpuop_func op_4690_40_ff;
+extern cpuop_func op_4698_40_nf;
+extern cpuop_func op_4698_40_ff;
+extern cpuop_func op_46a0_40_nf;
+extern cpuop_func op_46a0_40_ff;
+extern cpuop_func op_46a8_40_nf;
+extern cpuop_func op_46a8_40_ff;
+extern cpuop_func op_46b0_40_nf;
+extern cpuop_func op_46b0_40_ff;
+extern cpuop_func op_46b8_40_nf;
+extern cpuop_func op_46b8_40_ff;
+extern cpuop_func op_46b9_40_nf;
+extern cpuop_func op_46b9_40_ff;
+extern cpuop_func op_46c0_40_nf;
+extern cpuop_func op_46c0_40_ff;
+extern cpuop_func op_46d0_40_nf;
+extern cpuop_func op_46d0_40_ff;
+extern cpuop_func op_46d8_40_nf;
+extern cpuop_func op_46d8_40_ff;
+extern cpuop_func op_46e0_40_nf;
+extern cpuop_func op_46e0_40_ff;
+extern cpuop_func op_46e8_40_nf;
+extern cpuop_func op_46e8_40_ff;
+extern cpuop_func op_46f0_40_nf;
+extern cpuop_func op_46f0_40_ff;
+extern cpuop_func op_46f8_40_nf;
+extern cpuop_func op_46f8_40_ff;
+extern cpuop_func op_46f9_40_nf;
+extern cpuop_func op_46f9_40_ff;
+extern cpuop_func op_46fa_40_nf;
+extern cpuop_func op_46fa_40_ff;
+extern cpuop_func op_46fb_40_nf;
+extern cpuop_func op_46fb_40_ff;
+extern cpuop_func op_46fc_40_nf;
+extern cpuop_func op_46fc_40_ff;
+extern cpuop_func op_4800_40_nf;
+extern cpuop_func op_4800_40_ff;
+extern cpuop_func op_4808_40_nf;
+extern cpuop_func op_4808_40_ff;
+extern cpuop_func op_4810_40_nf;
+extern cpuop_func op_4810_40_ff;
+extern cpuop_func op_4818_40_nf;
+extern cpuop_func op_4818_40_ff;
+extern cpuop_func op_4820_40_nf;
+extern cpuop_func op_4820_40_ff;
+extern cpuop_func op_4828_40_nf;
+extern cpuop_func op_4828_40_ff;
+extern cpuop_func op_4830_40_nf;
+extern cpuop_func op_4830_40_ff;
+extern cpuop_func op_4838_40_nf;
+extern cpuop_func op_4838_40_ff;
+extern cpuop_func op_4839_40_nf;
+extern cpuop_func op_4839_40_ff;
+extern cpuop_func op_4840_40_nf;
+extern cpuop_func op_4840_40_ff;
+extern cpuop_func op_4848_40_nf;
+extern cpuop_func op_4848_40_ff;
+extern cpuop_func op_4850_40_nf;
+extern cpuop_func op_4850_40_ff;
+extern cpuop_func op_4868_40_nf;
+extern cpuop_func op_4868_40_ff;
+extern cpuop_func op_4870_40_nf;
+extern cpuop_func op_4870_40_ff;
+extern cpuop_func op_4878_40_nf;
+extern cpuop_func op_4878_40_ff;
+extern cpuop_func op_4879_40_nf;
+extern cpuop_func op_4879_40_ff;
+extern cpuop_func op_487a_40_nf;
+extern cpuop_func op_487a_40_ff;
+extern cpuop_func op_487b_40_nf;
+extern cpuop_func op_487b_40_ff;
+extern cpuop_func op_4880_40_nf;
+extern cpuop_func op_4880_40_ff;
+extern cpuop_func op_4890_40_nf;
+extern cpuop_func op_4890_40_ff;
+extern cpuop_func op_48a0_40_nf;
+extern cpuop_func op_48a0_40_ff;
+extern cpuop_func op_48a8_40_nf;
+extern cpuop_func op_48a8_40_ff;
+extern cpuop_func op_48b0_40_nf;
+extern cpuop_func op_48b0_40_ff;
+extern cpuop_func op_48b8_40_nf;
+extern cpuop_func op_48b8_40_ff;
+extern cpuop_func op_48b9_40_nf;
+extern cpuop_func op_48b9_40_ff;
+extern cpuop_func op_48c0_40_nf;
+extern cpuop_func op_48c0_40_ff;
+extern cpuop_func op_48d0_40_nf;
+extern cpuop_func op_48d0_40_ff;
+extern cpuop_func op_48e0_40_nf;
+extern cpuop_func op_48e0_40_ff;
+extern cpuop_func op_48e8_40_nf;
+extern cpuop_func op_48e8_40_ff;
+extern cpuop_func op_48f0_40_nf;
+extern cpuop_func op_48f0_40_ff;
+extern cpuop_func op_48f8_40_nf;
+extern cpuop_func op_48f8_40_ff;
+extern cpuop_func op_48f9_40_nf;
+extern cpuop_func op_48f9_40_ff;
+extern cpuop_func op_49c0_40_nf;
+extern cpuop_func op_49c0_40_ff;
+extern cpuop_func op_4a00_40_nf;
+extern cpuop_func op_4a00_40_ff;
+extern cpuop_func op_4a10_40_nf;
+extern cpuop_func op_4a10_40_ff;
+extern cpuop_func op_4a18_40_nf;
+extern cpuop_func op_4a18_40_ff;
+extern cpuop_func op_4a20_40_nf;
+extern cpuop_func op_4a20_40_ff;
+extern cpuop_func op_4a28_40_nf;
+extern cpuop_func op_4a28_40_ff;
+extern cpuop_func op_4a30_40_nf;
+extern cpuop_func op_4a30_40_ff;
+extern cpuop_func op_4a38_40_nf;
+extern cpuop_func op_4a38_40_ff;
+extern cpuop_func op_4a39_40_nf;
+extern cpuop_func op_4a39_40_ff;
+extern cpuop_func op_4a3a_40_nf;
+extern cpuop_func op_4a3a_40_ff;
+extern cpuop_func op_4a3b_40_nf;
+extern cpuop_func op_4a3b_40_ff;
+extern cpuop_func op_4a3c_40_nf;
+extern cpuop_func op_4a3c_40_ff;
+extern cpuop_func op_4a40_40_nf;
+extern cpuop_func op_4a40_40_ff;
+extern cpuop_func op_4a48_40_nf;
+extern cpuop_func op_4a48_40_ff;
+extern cpuop_func op_4a50_40_nf;
+extern cpuop_func op_4a50_40_ff;
+extern cpuop_func op_4a58_40_nf;
+extern cpuop_func op_4a58_40_ff;
+extern cpuop_func op_4a60_40_nf;
+extern cpuop_func op_4a60_40_ff;
+extern cpuop_func op_4a68_40_nf;
+extern cpuop_func op_4a68_40_ff;
+extern cpuop_func op_4a70_40_nf;
+extern cpuop_func op_4a70_40_ff;
+extern cpuop_func op_4a78_40_nf;
+extern cpuop_func op_4a78_40_ff;
+extern cpuop_func op_4a79_40_nf;
+extern cpuop_func op_4a79_40_ff;
+extern cpuop_func op_4a7a_40_nf;
+extern cpuop_func op_4a7a_40_ff;
+extern cpuop_func op_4a7b_40_nf;
+extern cpuop_func op_4a7b_40_ff;
+extern cpuop_func op_4a7c_40_nf;
+extern cpuop_func op_4a7c_40_ff;
+extern cpuop_func op_4a80_40_nf;
+extern cpuop_func op_4a80_40_ff;
+extern cpuop_func op_4a88_40_nf;
+extern cpuop_func op_4a88_40_ff;
+extern cpuop_func op_4a90_40_nf;
+extern cpuop_func op_4a90_40_ff;
+extern cpuop_func op_4a98_40_nf;
+extern cpuop_func op_4a98_40_ff;
+extern cpuop_func op_4aa0_40_nf;
+extern cpuop_func op_4aa0_40_ff;
+extern cpuop_func op_4aa8_40_nf;
+extern cpuop_func op_4aa8_40_ff;
+extern cpuop_func op_4ab0_40_nf;
+extern cpuop_func op_4ab0_40_ff;
+extern cpuop_func op_4ab8_40_nf;
+extern cpuop_func op_4ab8_40_ff;
+extern cpuop_func op_4ab9_40_nf;
+extern cpuop_func op_4ab9_40_ff;
+extern cpuop_func op_4aba_40_nf;
+extern cpuop_func op_4aba_40_ff;
+extern cpuop_func op_4abb_40_nf;
+extern cpuop_func op_4abb_40_ff;
+extern cpuop_func op_4abc_40_nf;
+extern cpuop_func op_4abc_40_ff;
+extern cpuop_func op_4ac0_40_nf;
+extern cpuop_func op_4ac0_40_ff;
+extern cpuop_func op_4ad0_40_nf;
+extern cpuop_func op_4ad0_40_ff;
+extern cpuop_func op_4ad8_40_nf;
+extern cpuop_func op_4ad8_40_ff;
+extern cpuop_func op_4ae0_40_nf;
+extern cpuop_func op_4ae0_40_ff;
+extern cpuop_func op_4ae8_40_nf;
+extern cpuop_func op_4ae8_40_ff;
+extern cpuop_func op_4af0_40_nf;
+extern cpuop_func op_4af0_40_ff;
+extern cpuop_func op_4af8_40_nf;
+extern cpuop_func op_4af8_40_ff;
+extern cpuop_func op_4af9_40_nf;
+extern cpuop_func op_4af9_40_ff;
+extern cpuop_func op_4c00_40_nf;
+extern cpuop_func op_4c00_40_ff;
+extern cpuop_func op_4c10_40_nf;
+extern cpuop_func op_4c10_40_ff;
+extern cpuop_func op_4c18_40_nf;
+extern cpuop_func op_4c18_40_ff;
+extern cpuop_func op_4c20_40_nf;
+extern cpuop_func op_4c20_40_ff;
+extern cpuop_func op_4c28_40_nf;
+extern cpuop_func op_4c28_40_ff;
+extern cpuop_func op_4c30_40_nf;
+extern cpuop_func op_4c30_40_ff;
+extern cpuop_func op_4c38_40_nf;
+extern cpuop_func op_4c38_40_ff;
+extern cpuop_func op_4c39_40_nf;
+extern cpuop_func op_4c39_40_ff;
+extern cpuop_func op_4c3a_40_nf;
+extern cpuop_func op_4c3a_40_ff;
+extern cpuop_func op_4c3b_40_nf;
+extern cpuop_func op_4c3b_40_ff;
+extern cpuop_func op_4c3c_40_nf;
+extern cpuop_func op_4c3c_40_ff;
+extern cpuop_func op_4c40_40_nf;
+extern cpuop_func op_4c40_40_ff;
+extern cpuop_func op_4c50_40_nf;
+extern cpuop_func op_4c50_40_ff;
+extern cpuop_func op_4c58_40_nf;
+extern cpuop_func op_4c58_40_ff;
+extern cpuop_func op_4c60_40_nf;
+extern cpuop_func op_4c60_40_ff;
+extern cpuop_func op_4c68_40_nf;
+extern cpuop_func op_4c68_40_ff;
+extern cpuop_func op_4c70_40_nf;
+extern cpuop_func op_4c70_40_ff;
+extern cpuop_func op_4c78_40_nf;
+extern cpuop_func op_4c78_40_ff;
+extern cpuop_func op_4c79_40_nf;
+extern cpuop_func op_4c79_40_ff;
+extern cpuop_func op_4c7a_40_nf;
+extern cpuop_func op_4c7a_40_ff;
+extern cpuop_func op_4c7b_40_nf;
+extern cpuop_func op_4c7b_40_ff;
+extern cpuop_func op_4c7c_40_nf;
+extern cpuop_func op_4c7c_40_ff;
+extern cpuop_func op_4c90_40_nf;
+extern cpuop_func op_4c90_40_ff;
+extern cpuop_func op_4c98_40_nf;
+extern cpuop_func op_4c98_40_ff;
+extern cpuop_func op_4ca8_40_nf;
+extern cpuop_func op_4ca8_40_ff;
+extern cpuop_func op_4cb0_40_nf;
+extern cpuop_func op_4cb0_40_ff;
+extern cpuop_func op_4cb8_40_nf;
+extern cpuop_func op_4cb8_40_ff;
+extern cpuop_func op_4cb9_40_nf;
+extern cpuop_func op_4cb9_40_ff;
+extern cpuop_func op_4cba_40_nf;
+extern cpuop_func op_4cba_40_ff;
+extern cpuop_func op_4cbb_40_nf;
+extern cpuop_func op_4cbb_40_ff;
+extern cpuop_func op_4cd0_40_nf;
+extern cpuop_func op_4cd0_40_ff;
+extern cpuop_func op_4cd8_40_nf;
+extern cpuop_func op_4cd8_40_ff;
+extern cpuop_func op_4ce8_40_nf;
+extern cpuop_func op_4ce8_40_ff;
+extern cpuop_func op_4cf0_40_nf;
+extern cpuop_func op_4cf0_40_ff;
+extern cpuop_func op_4cf8_40_nf;
+extern cpuop_func op_4cf8_40_ff;
+extern cpuop_func op_4cf9_40_nf;
+extern cpuop_func op_4cf9_40_ff;
+extern cpuop_func op_4cfa_40_nf;
+extern cpuop_func op_4cfa_40_ff;
+extern cpuop_func op_4cfb_40_nf;
+extern cpuop_func op_4cfb_40_ff;
+extern cpuop_func op_4e40_40_nf;
+extern cpuop_func op_4e40_40_ff;
+extern cpuop_func op_4e50_40_nf;
+extern cpuop_func op_4e50_40_ff;
+extern cpuop_func op_4e58_40_nf;
+extern cpuop_func op_4e58_40_ff;
+extern cpuop_func op_4e60_40_nf;
+extern cpuop_func op_4e60_40_ff;
+extern cpuop_func op_4e68_40_nf;
+extern cpuop_func op_4e68_40_ff;
+extern cpuop_func op_4e70_40_nf;
+extern cpuop_func op_4e70_40_ff;
+extern cpuop_func op_4e71_40_nf;
+extern cpuop_func op_4e71_40_ff;
+extern cpuop_func op_4e72_40_nf;
+extern cpuop_func op_4e72_40_ff;
+extern cpuop_func op_4e73_40_nf;
+extern cpuop_func op_4e73_40_ff;
+extern cpuop_func op_4e74_40_nf;
+extern cpuop_func op_4e74_40_ff;
+extern cpuop_func op_4e75_40_nf;
+extern cpuop_func op_4e75_40_ff;
+extern cpuop_func op_4e76_40_nf;
+extern cpuop_func op_4e76_40_ff;
+extern cpuop_func op_4e77_40_nf;
+extern cpuop_func op_4e77_40_ff;
+extern cpuop_func op_4e7a_40_nf;
+extern cpuop_func op_4e7a_40_ff;
+extern cpuop_func op_4e7b_40_nf;
+extern cpuop_func op_4e7b_40_ff;
+extern cpuop_func op_4e90_40_nf;
+extern cpuop_func op_4e90_40_ff;
+extern cpuop_func op_4ea8_40_nf;
+extern cpuop_func op_4ea8_40_ff;
+extern cpuop_func op_4eb0_40_nf;
+extern cpuop_func op_4eb0_40_ff;
+extern cpuop_func op_4eb8_40_nf;
+extern cpuop_func op_4eb8_40_ff;
+extern cpuop_func op_4eb9_40_nf;
+extern cpuop_func op_4eb9_40_ff;
+extern cpuop_func op_4eba_40_nf;
+extern cpuop_func op_4eba_40_ff;
+extern cpuop_func op_4ebb_40_nf;
+extern cpuop_func op_4ebb_40_ff;
+extern cpuop_func op_4ed0_40_nf;
+extern cpuop_func op_4ed0_40_ff;
+extern cpuop_func op_4ee8_40_nf;
+extern cpuop_func op_4ee8_40_ff;
+extern cpuop_func op_4ef0_40_nf;
+extern cpuop_func op_4ef0_40_ff;
+extern cpuop_func op_4ef8_40_nf;
+extern cpuop_func op_4ef8_40_ff;
+extern cpuop_func op_4ef9_40_nf;
+extern cpuop_func op_4ef9_40_ff;
+extern cpuop_func op_4efa_40_nf;
+extern cpuop_func op_4efa_40_ff;
+extern cpuop_func op_4efb_40_nf;
+extern cpuop_func op_4efb_40_ff;
+extern cpuop_func op_5000_40_nf;
+extern cpuop_func op_5000_40_ff;
+extern cpuop_func op_5010_40_nf;
+extern cpuop_func op_5010_40_ff;
+extern cpuop_func op_5018_40_nf;
+extern cpuop_func op_5018_40_ff;
+extern cpuop_func op_5020_40_nf;
+extern cpuop_func op_5020_40_ff;
+extern cpuop_func op_5028_40_nf;
+extern cpuop_func op_5028_40_ff;
+extern cpuop_func op_5030_40_nf;
+extern cpuop_func op_5030_40_ff;
+extern cpuop_func op_5038_40_nf;
+extern cpuop_func op_5038_40_ff;
+extern cpuop_func op_5039_40_nf;
+extern cpuop_func op_5039_40_ff;
+extern cpuop_func op_5040_40_nf;
+extern cpuop_func op_5040_40_ff;
+extern cpuop_func op_5048_40_nf;
+extern cpuop_func op_5048_40_ff;
+extern cpuop_func op_5050_40_nf;
+extern cpuop_func op_5050_40_ff;
+extern cpuop_func op_5058_40_nf;
+extern cpuop_func op_5058_40_ff;
+extern cpuop_func op_5060_40_nf;
+extern cpuop_func op_5060_40_ff;
+extern cpuop_func op_5068_40_nf;
+extern cpuop_func op_5068_40_ff;
+extern cpuop_func op_5070_40_nf;
+extern cpuop_func op_5070_40_ff;
+extern cpuop_func op_5078_40_nf;
+extern cpuop_func op_5078_40_ff;
+extern cpuop_func op_5079_40_nf;
+extern cpuop_func op_5079_40_ff;
+extern cpuop_func op_5080_40_nf;
+extern cpuop_func op_5080_40_ff;
+extern cpuop_func op_5088_40_nf;
+extern cpuop_func op_5088_40_ff;
+extern cpuop_func op_5090_40_nf;
+extern cpuop_func op_5090_40_ff;
+extern cpuop_func op_5098_40_nf;
+extern cpuop_func op_5098_40_ff;
+extern cpuop_func op_50a0_40_nf;
+extern cpuop_func op_50a0_40_ff;
+extern cpuop_func op_50a8_40_nf;
+extern cpuop_func op_50a8_40_ff;
+extern cpuop_func op_50b0_40_nf;
+extern cpuop_func op_50b0_40_ff;
+extern cpuop_func op_50b8_40_nf;
+extern cpuop_func op_50b8_40_ff;
+extern cpuop_func op_50b9_40_nf;
+extern cpuop_func op_50b9_40_ff;
+extern cpuop_func op_50c0_40_nf;
+extern cpuop_func op_50c0_40_ff;
+extern cpuop_func op_50c8_40_nf;
+extern cpuop_func op_50c8_40_ff;
+extern cpuop_func op_50d0_40_nf;
+extern cpuop_func op_50d0_40_ff;
+extern cpuop_func op_50d8_40_nf;
+extern cpuop_func op_50d8_40_ff;
+extern cpuop_func op_50e0_40_nf;
+extern cpuop_func op_50e0_40_ff;
+extern cpuop_func op_50e8_40_nf;
+extern cpuop_func op_50e8_40_ff;
+extern cpuop_func op_50f0_40_nf;
+extern cpuop_func op_50f0_40_ff;
+extern cpuop_func op_50f8_40_nf;
+extern cpuop_func op_50f8_40_ff;
+extern cpuop_func op_50f9_40_nf;
+extern cpuop_func op_50f9_40_ff;
+extern cpuop_func op_50fa_40_nf;
+extern cpuop_func op_50fa_40_ff;
+extern cpuop_func op_50fb_40_nf;
+extern cpuop_func op_50fb_40_ff;
+extern cpuop_func op_50fc_40_nf;
+extern cpuop_func op_50fc_40_ff;
+extern cpuop_func op_5100_40_nf;
+extern cpuop_func op_5100_40_ff;
+extern cpuop_func op_5110_40_nf;
+extern cpuop_func op_5110_40_ff;
+extern cpuop_func op_5118_40_nf;
+extern cpuop_func op_5118_40_ff;
+extern cpuop_func op_5120_40_nf;
+extern cpuop_func op_5120_40_ff;
+extern cpuop_func op_5128_40_nf;
+extern cpuop_func op_5128_40_ff;
+extern cpuop_func op_5130_40_nf;
+extern cpuop_func op_5130_40_ff;
+extern cpuop_func op_5138_40_nf;
+extern cpuop_func op_5138_40_ff;
+extern cpuop_func op_5139_40_nf;
+extern cpuop_func op_5139_40_ff;
+extern cpuop_func op_5140_40_nf;
+extern cpuop_func op_5140_40_ff;
+extern cpuop_func op_5148_40_nf;
+extern cpuop_func op_5148_40_ff;
+extern cpuop_func op_5150_40_nf;
+extern cpuop_func op_5150_40_ff;
+extern cpuop_func op_5158_40_nf;
+extern cpuop_func op_5158_40_ff;
+extern cpuop_func op_5160_40_nf;
+extern cpuop_func op_5160_40_ff;
+extern cpuop_func op_5168_40_nf;
+extern cpuop_func op_5168_40_ff;
+extern cpuop_func op_5170_40_nf;
+extern cpuop_func op_5170_40_ff;
+extern cpuop_func op_5178_40_nf;
+extern cpuop_func op_5178_40_ff;
+extern cpuop_func op_5179_40_nf;
+extern cpuop_func op_5179_40_ff;
+extern cpuop_func op_5180_40_nf;
+extern cpuop_func op_5180_40_ff;
+extern cpuop_func op_5188_40_nf;
+extern cpuop_func op_5188_40_ff;
+extern cpuop_func op_5190_40_nf;
+extern cpuop_func op_5190_40_ff;
+extern cpuop_func op_5198_40_nf;
+extern cpuop_func op_5198_40_ff;
+extern cpuop_func op_51a0_40_nf;
+extern cpuop_func op_51a0_40_ff;
+extern cpuop_func op_51a8_40_nf;
+extern cpuop_func op_51a8_40_ff;
+extern cpuop_func op_51b0_40_nf;
+extern cpuop_func op_51b0_40_ff;
+extern cpuop_func op_51b8_40_nf;
+extern cpuop_func op_51b8_40_ff;
+extern cpuop_func op_51b9_40_nf;
+extern cpuop_func op_51b9_40_ff;
+extern cpuop_func op_51c0_40_nf;
+extern cpuop_func op_51c0_40_ff;
+extern cpuop_func op_51c8_40_nf;
+extern cpuop_func op_51c8_40_ff;
+extern cpuop_func op_51d0_40_nf;
+extern cpuop_func op_51d0_40_ff;
+extern cpuop_func op_51d8_40_nf;
+extern cpuop_func op_51d8_40_ff;
+extern cpuop_func op_51e0_40_nf;
+extern cpuop_func op_51e0_40_ff;
+extern cpuop_func op_51e8_40_nf;
+extern cpuop_func op_51e8_40_ff;
+extern cpuop_func op_51f0_40_nf;
+extern cpuop_func op_51f0_40_ff;
+extern cpuop_func op_51f8_40_nf;
+extern cpuop_func op_51f8_40_ff;
+extern cpuop_func op_51f9_40_nf;
+extern cpuop_func op_51f9_40_ff;
+extern cpuop_func op_51fa_40_nf;
+extern cpuop_func op_51fa_40_ff;
+extern cpuop_func op_51fb_40_nf;
+extern cpuop_func op_51fb_40_ff;
+extern cpuop_func op_51fc_40_nf;
+extern cpuop_func op_51fc_40_ff;
+extern cpuop_func op_52c0_40_nf;
+extern cpuop_func op_52c0_40_ff;
+extern cpuop_func op_52c8_40_nf;
+extern cpuop_func op_52c8_40_ff;
+extern cpuop_func op_52d0_40_nf;
+extern cpuop_func op_52d0_40_ff;
+extern cpuop_func op_52d8_40_nf;
+extern cpuop_func op_52d8_40_ff;
+extern cpuop_func op_52e0_40_nf;
+extern cpuop_func op_52e0_40_ff;
+extern cpuop_func op_52e8_40_nf;
+extern cpuop_func op_52e8_40_ff;
+extern cpuop_func op_52f0_40_nf;
+extern cpuop_func op_52f0_40_ff;
+extern cpuop_func op_52f8_40_nf;
+extern cpuop_func op_52f8_40_ff;
+extern cpuop_func op_52f9_40_nf;
+extern cpuop_func op_52f9_40_ff;
+extern cpuop_func op_52fa_40_nf;
+extern cpuop_func op_52fa_40_ff;
+extern cpuop_func op_52fb_40_nf;
+extern cpuop_func op_52fb_40_ff;
+extern cpuop_func op_52fc_40_nf;
+extern cpuop_func op_52fc_40_ff;
+extern cpuop_func op_53c0_40_nf;
+extern cpuop_func op_53c0_40_ff;
+extern cpuop_func op_53c8_40_nf;
+extern cpuop_func op_53c8_40_ff;
+extern cpuop_func op_53d0_40_nf;
+extern cpuop_func op_53d0_40_ff;
+extern cpuop_func op_53d8_40_nf;
+extern cpuop_func op_53d8_40_ff;
+extern cpuop_func op_53e0_40_nf;
+extern cpuop_func op_53e0_40_ff;
+extern cpuop_func op_53e8_40_nf;
+extern cpuop_func op_53e8_40_ff;
+extern cpuop_func op_53f0_40_nf;
+extern cpuop_func op_53f0_40_ff;
+extern cpuop_func op_53f8_40_nf;
+extern cpuop_func op_53f8_40_ff;
+extern cpuop_func op_53f9_40_nf;
+extern cpuop_func op_53f9_40_ff;
+extern cpuop_func op_53fa_40_nf;
+extern cpuop_func op_53fa_40_ff;
+extern cpuop_func op_53fb_40_nf;
+extern cpuop_func op_53fb_40_ff;
+extern cpuop_func op_53fc_40_nf;
+extern cpuop_func op_53fc_40_ff;
+extern cpuop_func op_54c0_40_nf;
+extern cpuop_func op_54c0_40_ff;
+extern cpuop_func op_54c8_40_nf;
+extern cpuop_func op_54c8_40_ff;
+extern cpuop_func op_54d0_40_nf;
+extern cpuop_func op_54d0_40_ff;
+extern cpuop_func op_54d8_40_nf;
+extern cpuop_func op_54d8_40_ff;
+extern cpuop_func op_54e0_40_nf;
+extern cpuop_func op_54e0_40_ff;
+extern cpuop_func op_54e8_40_nf;
+extern cpuop_func op_54e8_40_ff;
+extern cpuop_func op_54f0_40_nf;
+extern cpuop_func op_54f0_40_ff;
+extern cpuop_func op_54f8_40_nf;
+extern cpuop_func op_54f8_40_ff;
+extern cpuop_func op_54f9_40_nf;
+extern cpuop_func op_54f9_40_ff;
+extern cpuop_func op_54fa_40_nf;
+extern cpuop_func op_54fa_40_ff;
+extern cpuop_func op_54fb_40_nf;
+extern cpuop_func op_54fb_40_ff;
+extern cpuop_func op_54fc_40_nf;
+extern cpuop_func op_54fc_40_ff;
+extern cpuop_func op_55c0_40_nf;
+extern cpuop_func op_55c0_40_ff;
+extern cpuop_func op_55c8_40_nf;
+extern cpuop_func op_55c8_40_ff;
+extern cpuop_func op_55d0_40_nf;
+extern cpuop_func op_55d0_40_ff;
+extern cpuop_func op_55d8_40_nf;
+extern cpuop_func op_55d8_40_ff;
+extern cpuop_func op_55e0_40_nf;
+extern cpuop_func op_55e0_40_ff;
+extern cpuop_func op_55e8_40_nf;
+extern cpuop_func op_55e8_40_ff;
+extern cpuop_func op_55f0_40_nf;
+extern cpuop_func op_55f0_40_ff;
+extern cpuop_func op_55f8_40_nf;
+extern cpuop_func op_55f8_40_ff;
+extern cpuop_func op_55f9_40_nf;
+extern cpuop_func op_55f9_40_ff;
+extern cpuop_func op_55fa_40_nf;
+extern cpuop_func op_55fa_40_ff;
+extern cpuop_func op_55fb_40_nf;
+extern cpuop_func op_55fb_40_ff;
+extern cpuop_func op_55fc_40_nf;
+extern cpuop_func op_55fc_40_ff;
+extern cpuop_func op_56c0_40_nf;
+extern cpuop_func op_56c0_40_ff;
+extern cpuop_func op_56c8_40_nf;
+extern cpuop_func op_56c8_40_ff;
+extern cpuop_func op_56d0_40_nf;
+extern cpuop_func op_56d0_40_ff;
+extern cpuop_func op_56d8_40_nf;
+extern cpuop_func op_56d8_40_ff;
+extern cpuop_func op_56e0_40_nf;
+extern cpuop_func op_56e0_40_ff;
+extern cpuop_func op_56e8_40_nf;
+extern cpuop_func op_56e8_40_ff;
+extern cpuop_func op_56f0_40_nf;
+extern cpuop_func op_56f0_40_ff;
+extern cpuop_func op_56f8_40_nf;
+extern cpuop_func op_56f8_40_ff;
+extern cpuop_func op_56f9_40_nf;
+extern cpuop_func op_56f9_40_ff;
+extern cpuop_func op_56fa_40_nf;
+extern cpuop_func op_56fa_40_ff;
+extern cpuop_func op_56fb_40_nf;
+extern cpuop_func op_56fb_40_ff;
+extern cpuop_func op_56fc_40_nf;
+extern cpuop_func op_56fc_40_ff;
+extern cpuop_func op_57c0_40_nf;
+extern cpuop_func op_57c0_40_ff;
+extern cpuop_func op_57c8_40_nf;
+extern cpuop_func op_57c8_40_ff;
+extern cpuop_func op_57d0_40_nf;
+extern cpuop_func op_57d0_40_ff;
+extern cpuop_func op_57d8_40_nf;
+extern cpuop_func op_57d8_40_ff;
+extern cpuop_func op_57e0_40_nf;
+extern cpuop_func op_57e0_40_ff;
+extern cpuop_func op_57e8_40_nf;
+extern cpuop_func op_57e8_40_ff;
+extern cpuop_func op_57f0_40_nf;
+extern cpuop_func op_57f0_40_ff;
+extern cpuop_func op_57f8_40_nf;
+extern cpuop_func op_57f8_40_ff;
+extern cpuop_func op_57f9_40_nf;
+extern cpuop_func op_57f9_40_ff;
+extern cpuop_func op_57fa_40_nf;
+extern cpuop_func op_57fa_40_ff;
+extern cpuop_func op_57fb_40_nf;
+extern cpuop_func op_57fb_40_ff;
+extern cpuop_func op_57fc_40_nf;
+extern cpuop_func op_57fc_40_ff;
+extern cpuop_func op_58c0_40_nf;
+extern cpuop_func op_58c0_40_ff;
+extern cpuop_func op_58c8_40_nf;
+extern cpuop_func op_58c8_40_ff;
+extern cpuop_func op_58d0_40_nf;
+extern cpuop_func op_58d0_40_ff;
+extern cpuop_func op_58d8_40_nf;
+extern cpuop_func op_58d8_40_ff;
+extern cpuop_func op_58e0_40_nf;
+extern cpuop_func op_58e0_40_ff;
+extern cpuop_func op_58e8_40_nf;
+extern cpuop_func op_58e8_40_ff;
+extern cpuop_func op_58f0_40_nf;
+extern cpuop_func op_58f0_40_ff;
+extern cpuop_func op_58f8_40_nf;
+extern cpuop_func op_58f8_40_ff;
+extern cpuop_func op_58f9_40_nf;
+extern cpuop_func op_58f9_40_ff;
+extern cpuop_func op_58fa_40_nf;
+extern cpuop_func op_58fa_40_ff;
+extern cpuop_func op_58fb_40_nf;
+extern cpuop_func op_58fb_40_ff;
+extern cpuop_func op_58fc_40_nf;
+extern cpuop_func op_58fc_40_ff;
+extern cpuop_func op_59c0_40_nf;
+extern cpuop_func op_59c0_40_ff;
+extern cpuop_func op_59c8_40_nf;
+extern cpuop_func op_59c8_40_ff;
+extern cpuop_func op_59d0_40_nf;
+extern cpuop_func op_59d0_40_ff;
+extern cpuop_func op_59d8_40_nf;
+extern cpuop_func op_59d8_40_ff;
+extern cpuop_func op_59e0_40_nf;
+extern cpuop_func op_59e0_40_ff;
+extern cpuop_func op_59e8_40_nf;
+extern cpuop_func op_59e8_40_ff;
+extern cpuop_func op_59f0_40_nf;
+extern cpuop_func op_59f0_40_ff;
+extern cpuop_func op_59f8_40_nf;
+extern cpuop_func op_59f8_40_ff;
+extern cpuop_func op_59f9_40_nf;
+extern cpuop_func op_59f9_40_ff;
+extern cpuop_func op_59fa_40_nf;
+extern cpuop_func op_59fa_40_ff;
+extern cpuop_func op_59fb_40_nf;
+extern cpuop_func op_59fb_40_ff;
+extern cpuop_func op_59fc_40_nf;
+extern cpuop_func op_59fc_40_ff;
+extern cpuop_func op_5ac0_40_nf;
+extern cpuop_func op_5ac0_40_ff;
+extern cpuop_func op_5ac8_40_nf;
+extern cpuop_func op_5ac8_40_ff;
+extern cpuop_func op_5ad0_40_nf;
+extern cpuop_func op_5ad0_40_ff;
+extern cpuop_func op_5ad8_40_nf;
+extern cpuop_func op_5ad8_40_ff;
+extern cpuop_func op_5ae0_40_nf;
+extern cpuop_func op_5ae0_40_ff;
+extern cpuop_func op_5ae8_40_nf;
+extern cpuop_func op_5ae8_40_ff;
+extern cpuop_func op_5af0_40_nf;
+extern cpuop_func op_5af0_40_ff;
+extern cpuop_func op_5af8_40_nf;
+extern cpuop_func op_5af8_40_ff;
+extern cpuop_func op_5af9_40_nf;
+extern cpuop_func op_5af9_40_ff;
+extern cpuop_func op_5afa_40_nf;
+extern cpuop_func op_5afa_40_ff;
+extern cpuop_func op_5afb_40_nf;
+extern cpuop_func op_5afb_40_ff;
+extern cpuop_func op_5afc_40_nf;
+extern cpuop_func op_5afc_40_ff;
+extern cpuop_func op_5bc0_40_nf;
+extern cpuop_func op_5bc0_40_ff;
+extern cpuop_func op_5bc8_40_nf;
+extern cpuop_func op_5bc8_40_ff;
+extern cpuop_func op_5bd0_40_nf;
+extern cpuop_func op_5bd0_40_ff;
+extern cpuop_func op_5bd8_40_nf;
+extern cpuop_func op_5bd8_40_ff;
+extern cpuop_func op_5be0_40_nf;
+extern cpuop_func op_5be0_40_ff;
+extern cpuop_func op_5be8_40_nf;
+extern cpuop_func op_5be8_40_ff;
+extern cpuop_func op_5bf0_40_nf;
+extern cpuop_func op_5bf0_40_ff;
+extern cpuop_func op_5bf8_40_nf;
+extern cpuop_func op_5bf8_40_ff;
+extern cpuop_func op_5bf9_40_nf;
+extern cpuop_func op_5bf9_40_ff;
+extern cpuop_func op_5bfa_40_nf;
+extern cpuop_func op_5bfa_40_ff;
+extern cpuop_func op_5bfb_40_nf;
+extern cpuop_func op_5bfb_40_ff;
+extern cpuop_func op_5bfc_40_nf;
+extern cpuop_func op_5bfc_40_ff;
+extern cpuop_func op_5cc0_40_nf;
+extern cpuop_func op_5cc0_40_ff;
+extern cpuop_func op_5cc8_40_nf;
+extern cpuop_func op_5cc8_40_ff;
+extern cpuop_func op_5cd0_40_nf;
+extern cpuop_func op_5cd0_40_ff;
+extern cpuop_func op_5cd8_40_nf;
+extern cpuop_func op_5cd8_40_ff;
+extern cpuop_func op_5ce0_40_nf;
+extern cpuop_func op_5ce0_40_ff;
+extern cpuop_func op_5ce8_40_nf;
+extern cpuop_func op_5ce8_40_ff;
+extern cpuop_func op_5cf0_40_nf;
+extern cpuop_func op_5cf0_40_ff;
+extern cpuop_func op_5cf8_40_nf;
+extern cpuop_func op_5cf8_40_ff;
+extern cpuop_func op_5cf9_40_nf;
+extern cpuop_func op_5cf9_40_ff;
+extern cpuop_func op_5cfa_40_nf;
+extern cpuop_func op_5cfa_40_ff;
+extern cpuop_func op_5cfb_40_nf;
+extern cpuop_func op_5cfb_40_ff;
+extern cpuop_func op_5cfc_40_nf;
+extern cpuop_func op_5cfc_40_ff;
+extern cpuop_func op_5dc0_40_nf;
+extern cpuop_func op_5dc0_40_ff;
+extern cpuop_func op_5dc8_40_nf;
+extern cpuop_func op_5dc8_40_ff;
+extern cpuop_func op_5dd0_40_nf;
+extern cpuop_func op_5dd0_40_ff;
+extern cpuop_func op_5dd8_40_nf;
+extern cpuop_func op_5dd8_40_ff;
+extern cpuop_func op_5de0_40_nf;
+extern cpuop_func op_5de0_40_ff;
+extern cpuop_func op_5de8_40_nf;
+extern cpuop_func op_5de8_40_ff;
+extern cpuop_func op_5df0_40_nf;
+extern cpuop_func op_5df0_40_ff;
+extern cpuop_func op_5df8_40_nf;
+extern cpuop_func op_5df8_40_ff;
+extern cpuop_func op_5df9_40_nf;
+extern cpuop_func op_5df9_40_ff;
+extern cpuop_func op_5dfa_40_nf;
+extern cpuop_func op_5dfa_40_ff;
+extern cpuop_func op_5dfb_40_nf;
+extern cpuop_func op_5dfb_40_ff;
+extern cpuop_func op_5dfc_40_nf;
+extern cpuop_func op_5dfc_40_ff;
+extern cpuop_func op_5ec0_40_nf;
+extern cpuop_func op_5ec0_40_ff;
+extern cpuop_func op_5ec8_40_nf;
+extern cpuop_func op_5ec8_40_ff;
+extern cpuop_func op_5ed0_40_nf;
+extern cpuop_func op_5ed0_40_ff;
+extern cpuop_func op_5ed8_40_nf;
+extern cpuop_func op_5ed8_40_ff;
+extern cpuop_func op_5ee0_40_nf;
+extern cpuop_func op_5ee0_40_ff;
+extern cpuop_func op_5ee8_40_nf;
+extern cpuop_func op_5ee8_40_ff;
+extern cpuop_func op_5ef0_40_nf;
+extern cpuop_func op_5ef0_40_ff;
+extern cpuop_func op_5ef8_40_nf;
+extern cpuop_func op_5ef8_40_ff;
+extern cpuop_func op_5ef9_40_nf;
+extern cpuop_func op_5ef9_40_ff;
+extern cpuop_func op_5efa_40_nf;
+extern cpuop_func op_5efa_40_ff;
+extern cpuop_func op_5efb_40_nf;
+extern cpuop_func op_5efb_40_ff;
+extern cpuop_func op_5efc_40_nf;
+extern cpuop_func op_5efc_40_ff;
+extern cpuop_func op_5fc0_40_nf;
+extern cpuop_func op_5fc0_40_ff;
+extern cpuop_func op_5fc8_40_nf;
+extern cpuop_func op_5fc8_40_ff;
+extern cpuop_func op_5fd0_40_nf;
+extern cpuop_func op_5fd0_40_ff;
+extern cpuop_func op_5fd8_40_nf;
+extern cpuop_func op_5fd8_40_ff;
+extern cpuop_func op_5fe0_40_nf;
+extern cpuop_func op_5fe0_40_ff;
+extern cpuop_func op_5fe8_40_nf;
+extern cpuop_func op_5fe8_40_ff;
+extern cpuop_func op_5ff0_40_nf;
+extern cpuop_func op_5ff0_40_ff;
+extern cpuop_func op_5ff8_40_nf;
+extern cpuop_func op_5ff8_40_ff;
+extern cpuop_func op_5ff9_40_nf;
+extern cpuop_func op_5ff9_40_ff;
+extern cpuop_func op_5ffa_40_nf;
+extern cpuop_func op_5ffa_40_ff;
+extern cpuop_func op_5ffb_40_nf;
+extern cpuop_func op_5ffb_40_ff;
+extern cpuop_func op_5ffc_40_nf;
+extern cpuop_func op_5ffc_40_ff;
+extern cpuop_func op_6000_40_nf;
+extern cpuop_func op_6000_40_ff;
+extern cpuop_func op_6001_40_nf;
+extern cpuop_func op_6001_40_ff;
+extern cpuop_func op_60ff_40_nf;
+extern cpuop_func op_60ff_40_ff;
+extern cpuop_func op_6100_40_nf;
+extern cpuop_func op_6100_40_ff;
+extern cpuop_func op_6101_40_nf;
+extern cpuop_func op_6101_40_ff;
+extern cpuop_func op_61ff_40_nf;
+extern cpuop_func op_61ff_40_ff;
+extern cpuop_func op_6200_40_nf;
+extern cpuop_func op_6200_40_ff;
+extern cpuop_func op_6201_40_nf;
+extern cpuop_func op_6201_40_ff;
+extern cpuop_func op_62ff_40_nf;
+extern cpuop_func op_62ff_40_ff;
+extern cpuop_func op_6300_40_nf;
+extern cpuop_func op_6300_40_ff;
+extern cpuop_func op_6301_40_nf;
+extern cpuop_func op_6301_40_ff;
+extern cpuop_func op_63ff_40_nf;
+extern cpuop_func op_63ff_40_ff;
+extern cpuop_func op_6400_40_nf;
+extern cpuop_func op_6400_40_ff;
+extern cpuop_func op_6401_40_nf;
+extern cpuop_func op_6401_40_ff;
+extern cpuop_func op_64ff_40_nf;
+extern cpuop_func op_64ff_40_ff;
+extern cpuop_func op_6500_40_nf;
+extern cpuop_func op_6500_40_ff;
+extern cpuop_func op_6501_40_nf;
+extern cpuop_func op_6501_40_ff;
+extern cpuop_func op_65ff_40_nf;
+extern cpuop_func op_65ff_40_ff;
+extern cpuop_func op_6600_40_nf;
+extern cpuop_func op_6600_40_ff;
+extern cpuop_func op_6601_40_nf;
+extern cpuop_func op_6601_40_ff;
+extern cpuop_func op_66ff_40_nf;
+extern cpuop_func op_66ff_40_ff;
+extern cpuop_func op_6700_40_nf;
+extern cpuop_func op_6700_40_ff;
+extern cpuop_func op_6701_40_nf;
+extern cpuop_func op_6701_40_ff;
+extern cpuop_func op_67ff_40_nf;
+extern cpuop_func op_67ff_40_ff;
+extern cpuop_func op_6800_40_nf;
+extern cpuop_func op_6800_40_ff;
+extern cpuop_func op_6801_40_nf;
+extern cpuop_func op_6801_40_ff;
+extern cpuop_func op_68ff_40_nf;
+extern cpuop_func op_68ff_40_ff;
+extern cpuop_func op_6900_40_nf;
+extern cpuop_func op_6900_40_ff;
+extern cpuop_func op_6901_40_nf;
+extern cpuop_func op_6901_40_ff;
+extern cpuop_func op_69ff_40_nf;
+extern cpuop_func op_69ff_40_ff;
+extern cpuop_func op_6a00_40_nf;
+extern cpuop_func op_6a00_40_ff;
+extern cpuop_func op_6a01_40_nf;
+extern cpuop_func op_6a01_40_ff;
+extern cpuop_func op_6aff_40_nf;
+extern cpuop_func op_6aff_40_ff;
+extern cpuop_func op_6b00_40_nf;
+extern cpuop_func op_6b00_40_ff;
+extern cpuop_func op_6b01_40_nf;
+extern cpuop_func op_6b01_40_ff;
+extern cpuop_func op_6bff_40_nf;
+extern cpuop_func op_6bff_40_ff;
+extern cpuop_func op_6c00_40_nf;
+extern cpuop_func op_6c00_40_ff;
+extern cpuop_func op_6c01_40_nf;
+extern cpuop_func op_6c01_40_ff;
+extern cpuop_func op_6cff_40_nf;
+extern cpuop_func op_6cff_40_ff;
+extern cpuop_func op_6d00_40_nf;
+extern cpuop_func op_6d00_40_ff;
+extern cpuop_func op_6d01_40_nf;
+extern cpuop_func op_6d01_40_ff;
+extern cpuop_func op_6dff_40_nf;
+extern cpuop_func op_6dff_40_ff;
+extern cpuop_func op_6e00_40_nf;
+extern cpuop_func op_6e00_40_ff;
+extern cpuop_func op_6e01_40_nf;
+extern cpuop_func op_6e01_40_ff;
+extern cpuop_func op_6eff_40_nf;
+extern cpuop_func op_6eff_40_ff;
+extern cpuop_func op_6f00_40_nf;
+extern cpuop_func op_6f00_40_ff;
+extern cpuop_func op_6f01_40_nf;
+extern cpuop_func op_6f01_40_ff;
+extern cpuop_func op_6fff_40_nf;
+extern cpuop_func op_6fff_40_ff;
+extern cpuop_func op_7000_40_nf;
+extern cpuop_func op_7000_40_ff;
+extern cpuop_func op_8000_40_nf;
+extern cpuop_func op_8000_40_ff;
+extern cpuop_func op_8010_40_nf;
+extern cpuop_func op_8010_40_ff;
+extern cpuop_func op_8018_40_nf;
+extern cpuop_func op_8018_40_ff;
+extern cpuop_func op_8020_40_nf;
+extern cpuop_func op_8020_40_ff;
+extern cpuop_func op_8028_40_nf;
+extern cpuop_func op_8028_40_ff;
+extern cpuop_func op_8030_40_nf;
+extern cpuop_func op_8030_40_ff;
+extern cpuop_func op_8038_40_nf;
+extern cpuop_func op_8038_40_ff;
+extern cpuop_func op_8039_40_nf;
+extern cpuop_func op_8039_40_ff;
+extern cpuop_func op_803a_40_nf;
+extern cpuop_func op_803a_40_ff;
+extern cpuop_func op_803b_40_nf;
+extern cpuop_func op_803b_40_ff;
+extern cpuop_func op_803c_40_nf;
+extern cpuop_func op_803c_40_ff;
+extern cpuop_func op_8040_40_nf;
+extern cpuop_func op_8040_40_ff;
+extern cpuop_func op_8050_40_nf;
+extern cpuop_func op_8050_40_ff;
+extern cpuop_func op_8058_40_nf;
+extern cpuop_func op_8058_40_ff;
+extern cpuop_func op_8060_40_nf;
+extern cpuop_func op_8060_40_ff;
+extern cpuop_func op_8068_40_nf;
+extern cpuop_func op_8068_40_ff;
+extern cpuop_func op_8070_40_nf;
+extern cpuop_func op_8070_40_ff;
+extern cpuop_func op_8078_40_nf;
+extern cpuop_func op_8078_40_ff;
+extern cpuop_func op_8079_40_nf;
+extern cpuop_func op_8079_40_ff;
+extern cpuop_func op_807a_40_nf;
+extern cpuop_func op_807a_40_ff;
+extern cpuop_func op_807b_40_nf;
+extern cpuop_func op_807b_40_ff;
+extern cpuop_func op_807c_40_nf;
+extern cpuop_func op_807c_40_ff;
+extern cpuop_func op_8080_40_nf;
+extern cpuop_func op_8080_40_ff;
+extern cpuop_func op_8090_40_nf;
+extern cpuop_func op_8090_40_ff;
+extern cpuop_func op_8098_40_nf;
+extern cpuop_func op_8098_40_ff;
+extern cpuop_func op_80a0_40_nf;
+extern cpuop_func op_80a0_40_ff;
+extern cpuop_func op_80a8_40_nf;
+extern cpuop_func op_80a8_40_ff;
+extern cpuop_func op_80b0_40_nf;
+extern cpuop_func op_80b0_40_ff;
+extern cpuop_func op_80b8_40_nf;
+extern cpuop_func op_80b8_40_ff;
+extern cpuop_func op_80b9_40_nf;
+extern cpuop_func op_80b9_40_ff;
+extern cpuop_func op_80ba_40_nf;
+extern cpuop_func op_80ba_40_ff;
+extern cpuop_func op_80bb_40_nf;
+extern cpuop_func op_80bb_40_ff;
+extern cpuop_func op_80bc_40_nf;
+extern cpuop_func op_80bc_40_ff;
+extern cpuop_func op_80c0_40_nf;
+extern cpuop_func op_80c0_40_ff;
+extern cpuop_func op_80d0_40_nf;
+extern cpuop_func op_80d0_40_ff;
+extern cpuop_func op_80d8_40_nf;
+extern cpuop_func op_80d8_40_ff;
+extern cpuop_func op_80e0_40_nf;
+extern cpuop_func op_80e0_40_ff;
+extern cpuop_func op_80e8_40_nf;
+extern cpuop_func op_80e8_40_ff;
+extern cpuop_func op_80f0_40_nf;
+extern cpuop_func op_80f0_40_ff;
+extern cpuop_func op_80f8_40_nf;
+extern cpuop_func op_80f8_40_ff;
+extern cpuop_func op_80f9_40_nf;
+extern cpuop_func op_80f9_40_ff;
+extern cpuop_func op_80fa_40_nf;
+extern cpuop_func op_80fa_40_ff;
+extern cpuop_func op_80fb_40_nf;
+extern cpuop_func op_80fb_40_ff;
+extern cpuop_func op_80fc_40_nf;
+extern cpuop_func op_80fc_40_ff;
+extern cpuop_func op_8100_40_nf;
+extern cpuop_func op_8100_40_ff;
+extern cpuop_func op_8108_40_nf;
+extern cpuop_func op_8108_40_ff;
+extern cpuop_func op_8110_40_nf;
+extern cpuop_func op_8110_40_ff;
+extern cpuop_func op_8118_40_nf;
+extern cpuop_func op_8118_40_ff;
+extern cpuop_func op_8120_40_nf;
+extern cpuop_func op_8120_40_ff;
+extern cpuop_func op_8128_40_nf;
+extern cpuop_func op_8128_40_ff;
+extern cpuop_func op_8130_40_nf;
+extern cpuop_func op_8130_40_ff;
+extern cpuop_func op_8138_40_nf;
+extern cpuop_func op_8138_40_ff;
+extern cpuop_func op_8139_40_nf;
+extern cpuop_func op_8139_40_ff;
+extern cpuop_func op_8140_40_nf;
+extern cpuop_func op_8140_40_ff;
+extern cpuop_func op_8148_40_nf;
+extern cpuop_func op_8148_40_ff;
+extern cpuop_func op_8150_40_nf;
+extern cpuop_func op_8150_40_ff;
+extern cpuop_func op_8158_40_nf;
+extern cpuop_func op_8158_40_ff;
+extern cpuop_func op_8160_40_nf;
+extern cpuop_func op_8160_40_ff;
+extern cpuop_func op_8168_40_nf;
+extern cpuop_func op_8168_40_ff;
+extern cpuop_func op_8170_40_nf;
+extern cpuop_func op_8170_40_ff;
+extern cpuop_func op_8178_40_nf;
+extern cpuop_func op_8178_40_ff;
+extern cpuop_func op_8179_40_nf;
+extern cpuop_func op_8179_40_ff;
+extern cpuop_func op_8180_40_nf;
+extern cpuop_func op_8180_40_ff;
+extern cpuop_func op_8188_40_nf;
+extern cpuop_func op_8188_40_ff;
+extern cpuop_func op_8190_40_nf;
+extern cpuop_func op_8190_40_ff;
+extern cpuop_func op_8198_40_nf;
+extern cpuop_func op_8198_40_ff;
+extern cpuop_func op_81a0_40_nf;
+extern cpuop_func op_81a0_40_ff;
+extern cpuop_func op_81a8_40_nf;
+extern cpuop_func op_81a8_40_ff;
+extern cpuop_func op_81b0_40_nf;
+extern cpuop_func op_81b0_40_ff;
+extern cpuop_func op_81b8_40_nf;
+extern cpuop_func op_81b8_40_ff;
+extern cpuop_func op_81b9_40_nf;
+extern cpuop_func op_81b9_40_ff;
+extern cpuop_func op_81c0_40_nf;
+extern cpuop_func op_81c0_40_ff;
+extern cpuop_func op_81d0_40_nf;
+extern cpuop_func op_81d0_40_ff;
+extern cpuop_func op_81d8_40_nf;
+extern cpuop_func op_81d8_40_ff;
+extern cpuop_func op_81e0_40_nf;
+extern cpuop_func op_81e0_40_ff;
+extern cpuop_func op_81e8_40_nf;
+extern cpuop_func op_81e8_40_ff;
+extern cpuop_func op_81f0_40_nf;
+extern cpuop_func op_81f0_40_ff;
+extern cpuop_func op_81f8_40_nf;
+extern cpuop_func op_81f8_40_ff;
+extern cpuop_func op_81f9_40_nf;
+extern cpuop_func op_81f9_40_ff;
+extern cpuop_func op_81fa_40_nf;
+extern cpuop_func op_81fa_40_ff;
+extern cpuop_func op_81fb_40_nf;
+extern cpuop_func op_81fb_40_ff;
+extern cpuop_func op_81fc_40_nf;
+extern cpuop_func op_81fc_40_ff;
+extern cpuop_func op_9000_40_nf;
+extern cpuop_func op_9000_40_ff;
+extern cpuop_func op_9010_40_nf;
+extern cpuop_func op_9010_40_ff;
+extern cpuop_func op_9018_40_nf;
+extern cpuop_func op_9018_40_ff;
+extern cpuop_func op_9020_40_nf;
+extern cpuop_func op_9020_40_ff;
+extern cpuop_func op_9028_40_nf;
+extern cpuop_func op_9028_40_ff;
+extern cpuop_func op_9030_40_nf;
+extern cpuop_func op_9030_40_ff;
+extern cpuop_func op_9038_40_nf;
+extern cpuop_func op_9038_40_ff;
+extern cpuop_func op_9039_40_nf;
+extern cpuop_func op_9039_40_ff;
+extern cpuop_func op_903a_40_nf;
+extern cpuop_func op_903a_40_ff;
+extern cpuop_func op_903b_40_nf;
+extern cpuop_func op_903b_40_ff;
+extern cpuop_func op_903c_40_nf;
+extern cpuop_func op_903c_40_ff;
+extern cpuop_func op_9040_40_nf;
+extern cpuop_func op_9040_40_ff;
+extern cpuop_func op_9048_40_nf;
+extern cpuop_func op_9048_40_ff;
+extern cpuop_func op_9050_40_nf;
+extern cpuop_func op_9050_40_ff;
+extern cpuop_func op_9058_40_nf;
+extern cpuop_func op_9058_40_ff;
+extern cpuop_func op_9060_40_nf;
+extern cpuop_func op_9060_40_ff;
+extern cpuop_func op_9068_40_nf;
+extern cpuop_func op_9068_40_ff;
+extern cpuop_func op_9070_40_nf;
+extern cpuop_func op_9070_40_ff;
+extern cpuop_func op_9078_40_nf;
+extern cpuop_func op_9078_40_ff;
+extern cpuop_func op_9079_40_nf;
+extern cpuop_func op_9079_40_ff;
+extern cpuop_func op_907a_40_nf;
+extern cpuop_func op_907a_40_ff;
+extern cpuop_func op_907b_40_nf;
+extern cpuop_func op_907b_40_ff;
+extern cpuop_func op_907c_40_nf;
+extern cpuop_func op_907c_40_ff;
+extern cpuop_func op_9080_40_nf;
+extern cpuop_func op_9080_40_ff;
+extern cpuop_func op_9088_40_nf;
+extern cpuop_func op_9088_40_ff;
+extern cpuop_func op_9090_40_nf;
+extern cpuop_func op_9090_40_ff;
+extern cpuop_func op_9098_40_nf;
+extern cpuop_func op_9098_40_ff;
+extern cpuop_func op_90a0_40_nf;
+extern cpuop_func op_90a0_40_ff;
+extern cpuop_func op_90a8_40_nf;
+extern cpuop_func op_90a8_40_ff;
+extern cpuop_func op_90b0_40_nf;
+extern cpuop_func op_90b0_40_ff;
+extern cpuop_func op_90b8_40_nf;
+extern cpuop_func op_90b8_40_ff;
+extern cpuop_func op_90b9_40_nf;
+extern cpuop_func op_90b9_40_ff;
+extern cpuop_func op_90ba_40_nf;
+extern cpuop_func op_90ba_40_ff;
+extern cpuop_func op_90bb_40_nf;
+extern cpuop_func op_90bb_40_ff;
+extern cpuop_func op_90bc_40_nf;
+extern cpuop_func op_90bc_40_ff;
+extern cpuop_func op_90c0_40_nf;
+extern cpuop_func op_90c0_40_ff;
+extern cpuop_func op_90c8_40_nf;
+extern cpuop_func op_90c8_40_ff;
+extern cpuop_func op_90d0_40_nf;
+extern cpuop_func op_90d0_40_ff;
+extern cpuop_func op_90d8_40_nf;
+extern cpuop_func op_90d8_40_ff;
+extern cpuop_func op_90e0_40_nf;
+extern cpuop_func op_90e0_40_ff;
+extern cpuop_func op_90e8_40_nf;
+extern cpuop_func op_90e8_40_ff;
+extern cpuop_func op_90f0_40_nf;
+extern cpuop_func op_90f0_40_ff;
+extern cpuop_func op_90f8_40_nf;
+extern cpuop_func op_90f8_40_ff;
+extern cpuop_func op_90f9_40_nf;
+extern cpuop_func op_90f9_40_ff;
+extern cpuop_func op_90fa_40_nf;
+extern cpuop_func op_90fa_40_ff;
+extern cpuop_func op_90fb_40_nf;
+extern cpuop_func op_90fb_40_ff;
+extern cpuop_func op_90fc_40_nf;
+extern cpuop_func op_90fc_40_ff;
+extern cpuop_func op_9100_40_nf;
+extern cpuop_func op_9100_40_ff;
+extern cpuop_func op_9108_40_nf;
+extern cpuop_func op_9108_40_ff;
+extern cpuop_func op_9110_40_nf;
+extern cpuop_func op_9110_40_ff;
+extern cpuop_func op_9118_40_nf;
+extern cpuop_func op_9118_40_ff;
+extern cpuop_func op_9120_40_nf;
+extern cpuop_func op_9120_40_ff;
+extern cpuop_func op_9128_40_nf;
+extern cpuop_func op_9128_40_ff;
+extern cpuop_func op_9130_40_nf;
+extern cpuop_func op_9130_40_ff;
+extern cpuop_func op_9138_40_nf;
+extern cpuop_func op_9138_40_ff;
+extern cpuop_func op_9139_40_nf;
+extern cpuop_func op_9139_40_ff;
+extern cpuop_func op_9140_40_nf;
+extern cpuop_func op_9140_40_ff;
+extern cpuop_func op_9148_40_nf;
+extern cpuop_func op_9148_40_ff;
+extern cpuop_func op_9150_40_nf;
+extern cpuop_func op_9150_40_ff;
+extern cpuop_func op_9158_40_nf;
+extern cpuop_func op_9158_40_ff;
+extern cpuop_func op_9160_40_nf;
+extern cpuop_func op_9160_40_ff;
+extern cpuop_func op_9168_40_nf;
+extern cpuop_func op_9168_40_ff;
+extern cpuop_func op_9170_40_nf;
+extern cpuop_func op_9170_40_ff;
+extern cpuop_func op_9178_40_nf;
+extern cpuop_func op_9178_40_ff;
+extern cpuop_func op_9179_40_nf;
+extern cpuop_func op_9179_40_ff;
+extern cpuop_func op_9180_40_nf;
+extern cpuop_func op_9180_40_ff;
+extern cpuop_func op_9188_40_nf;
+extern cpuop_func op_9188_40_ff;
+extern cpuop_func op_9190_40_nf;
+extern cpuop_func op_9190_40_ff;
+extern cpuop_func op_9198_40_nf;
+extern cpuop_func op_9198_40_ff;
+extern cpuop_func op_91a0_40_nf;
+extern cpuop_func op_91a0_40_ff;
+extern cpuop_func op_91a8_40_nf;
+extern cpuop_func op_91a8_40_ff;
+extern cpuop_func op_91b0_40_nf;
+extern cpuop_func op_91b0_40_ff;
+extern cpuop_func op_91b8_40_nf;
+extern cpuop_func op_91b8_40_ff;
+extern cpuop_func op_91b9_40_nf;
+extern cpuop_func op_91b9_40_ff;
+extern cpuop_func op_91c0_40_nf;
+extern cpuop_func op_91c0_40_ff;
+extern cpuop_func op_91c8_40_nf;
+extern cpuop_func op_91c8_40_ff;
+extern cpuop_func op_91d0_40_nf;
+extern cpuop_func op_91d0_40_ff;
+extern cpuop_func op_91d8_40_nf;
+extern cpuop_func op_91d8_40_ff;
+extern cpuop_func op_91e0_40_nf;
+extern cpuop_func op_91e0_40_ff;
+extern cpuop_func op_91e8_40_nf;
+extern cpuop_func op_91e8_40_ff;
+extern cpuop_func op_91f0_40_nf;
+extern cpuop_func op_91f0_40_ff;
+extern cpuop_func op_91f8_40_nf;
+extern cpuop_func op_91f8_40_ff;
+extern cpuop_func op_91f9_40_nf;
+extern cpuop_func op_91f9_40_ff;
+extern cpuop_func op_91fa_40_nf;
+extern cpuop_func op_91fa_40_ff;
+extern cpuop_func op_91fb_40_nf;
+extern cpuop_func op_91fb_40_ff;
+extern cpuop_func op_91fc_40_nf;
+extern cpuop_func op_91fc_40_ff;
+extern cpuop_func op_b000_40_nf;
+extern cpuop_func op_b000_40_ff;
+extern cpuop_func op_b010_40_nf;
+extern cpuop_func op_b010_40_ff;
+extern cpuop_func op_b018_40_nf;
+extern cpuop_func op_b018_40_ff;
+extern cpuop_func op_b020_40_nf;
+extern cpuop_func op_b020_40_ff;
+extern cpuop_func op_b028_40_nf;
+extern cpuop_func op_b028_40_ff;
+extern cpuop_func op_b030_40_nf;
+extern cpuop_func op_b030_40_ff;
+extern cpuop_func op_b038_40_nf;
+extern cpuop_func op_b038_40_ff;
+extern cpuop_func op_b039_40_nf;
+extern cpuop_func op_b039_40_ff;
+extern cpuop_func op_b03a_40_nf;
+extern cpuop_func op_b03a_40_ff;
+extern cpuop_func op_b03b_40_nf;
+extern cpuop_func op_b03b_40_ff;
+extern cpuop_func op_b03c_40_nf;
+extern cpuop_func op_b03c_40_ff;
+extern cpuop_func op_b040_40_nf;
+extern cpuop_func op_b040_40_ff;
+extern cpuop_func op_b048_40_nf;
+extern cpuop_func op_b048_40_ff;
+extern cpuop_func op_b050_40_nf;
+extern cpuop_func op_b050_40_ff;
+extern cpuop_func op_b058_40_nf;
+extern cpuop_func op_b058_40_ff;
+extern cpuop_func op_b060_40_nf;
+extern cpuop_func op_b060_40_ff;
+extern cpuop_func op_b068_40_nf;
+extern cpuop_func op_b068_40_ff;
+extern cpuop_func op_b070_40_nf;
+extern cpuop_func op_b070_40_ff;
+extern cpuop_func op_b078_40_nf;
+extern cpuop_func op_b078_40_ff;
+extern cpuop_func op_b079_40_nf;
+extern cpuop_func op_b079_40_ff;
+extern cpuop_func op_b07a_40_nf;
+extern cpuop_func op_b07a_40_ff;
+extern cpuop_func op_b07b_40_nf;
+extern cpuop_func op_b07b_40_ff;
+extern cpuop_func op_b07c_40_nf;
+extern cpuop_func op_b07c_40_ff;
+extern cpuop_func op_b080_40_nf;
+extern cpuop_func op_b080_40_ff;
+extern cpuop_func op_b088_40_nf;
+extern cpuop_func op_b088_40_ff;
+extern cpuop_func op_b090_40_nf;
+extern cpuop_func op_b090_40_ff;
+extern cpuop_func op_b098_40_nf;
+extern cpuop_func op_b098_40_ff;
+extern cpuop_func op_b0a0_40_nf;
+extern cpuop_func op_b0a0_40_ff;
+extern cpuop_func op_b0a8_40_nf;
+extern cpuop_func op_b0a8_40_ff;
+extern cpuop_func op_b0b0_40_nf;
+extern cpuop_func op_b0b0_40_ff;
+extern cpuop_func op_b0b8_40_nf;
+extern cpuop_func op_b0b8_40_ff;
+extern cpuop_func op_b0b9_40_nf;
+extern cpuop_func op_b0b9_40_ff;
+extern cpuop_func op_b0ba_40_nf;
+extern cpuop_func op_b0ba_40_ff;
+extern cpuop_func op_b0bb_40_nf;
+extern cpuop_func op_b0bb_40_ff;
+extern cpuop_func op_b0bc_40_nf;
+extern cpuop_func op_b0bc_40_ff;
+extern cpuop_func op_b0c0_40_nf;
+extern cpuop_func op_b0c0_40_ff;
+extern cpuop_func op_b0c8_40_nf;
+extern cpuop_func op_b0c8_40_ff;
+extern cpuop_func op_b0d0_40_nf;
+extern cpuop_func op_b0d0_40_ff;
+extern cpuop_func op_b0d8_40_nf;
+extern cpuop_func op_b0d8_40_ff;
+extern cpuop_func op_b0e0_40_nf;
+extern cpuop_func op_b0e0_40_ff;
+extern cpuop_func op_b0e8_40_nf;
+extern cpuop_func op_b0e8_40_ff;
+extern cpuop_func op_b0f0_40_nf;
+extern cpuop_func op_b0f0_40_ff;
+extern cpuop_func op_b0f8_40_nf;
+extern cpuop_func op_b0f8_40_ff;
+extern cpuop_func op_b0f9_40_nf;
+extern cpuop_func op_b0f9_40_ff;
+extern cpuop_func op_b0fa_40_nf;
+extern cpuop_func op_b0fa_40_ff;
+extern cpuop_func op_b0fb_40_nf;
+extern cpuop_func op_b0fb_40_ff;
+extern cpuop_func op_b0fc_40_nf;
+extern cpuop_func op_b0fc_40_ff;
+extern cpuop_func op_b100_40_nf;
+extern cpuop_func op_b100_40_ff;
+extern cpuop_func op_b108_40_nf;
+extern cpuop_func op_b108_40_ff;
+extern cpuop_func op_b110_40_nf;
+extern cpuop_func op_b110_40_ff;
+extern cpuop_func op_b118_40_nf;
+extern cpuop_func op_b118_40_ff;
+extern cpuop_func op_b120_40_nf;
+extern cpuop_func op_b120_40_ff;
+extern cpuop_func op_b128_40_nf;
+extern cpuop_func op_b128_40_ff;
+extern cpuop_func op_b130_40_nf;
+extern cpuop_func op_b130_40_ff;
+extern cpuop_func op_b138_40_nf;
+extern cpuop_func op_b138_40_ff;
+extern cpuop_func op_b139_40_nf;
+extern cpuop_func op_b139_40_ff;
+extern cpuop_func op_b140_40_nf;
+extern cpuop_func op_b140_40_ff;
+extern cpuop_func op_b148_40_nf;
+extern cpuop_func op_b148_40_ff;
+extern cpuop_func op_b150_40_nf;
+extern cpuop_func op_b150_40_ff;
+extern cpuop_func op_b158_40_nf;
+extern cpuop_func op_b158_40_ff;
+extern cpuop_func op_b160_40_nf;
+extern cpuop_func op_b160_40_ff;
+extern cpuop_func op_b168_40_nf;
+extern cpuop_func op_b168_40_ff;
+extern cpuop_func op_b170_40_nf;
+extern cpuop_func op_b170_40_ff;
+extern cpuop_func op_b178_40_nf;
+extern cpuop_func op_b178_40_ff;
+extern cpuop_func op_b179_40_nf;
+extern cpuop_func op_b179_40_ff;
+extern cpuop_func op_b180_40_nf;
+extern cpuop_func op_b180_40_ff;
+extern cpuop_func op_b188_40_nf;
+extern cpuop_func op_b188_40_ff;
+extern cpuop_func op_b190_40_nf;
+extern cpuop_func op_b190_40_ff;
+extern cpuop_func op_b198_40_nf;
+extern cpuop_func op_b198_40_ff;
+extern cpuop_func op_b1a0_40_nf;
+extern cpuop_func op_b1a0_40_ff;
+extern cpuop_func op_b1a8_40_nf;
+extern cpuop_func op_b1a8_40_ff;
+extern cpuop_func op_b1b0_40_nf;
+extern cpuop_func op_b1b0_40_ff;
+extern cpuop_func op_b1b8_40_nf;
+extern cpuop_func op_b1b8_40_ff;
+extern cpuop_func op_b1b9_40_nf;
+extern cpuop_func op_b1b9_40_ff;
+extern cpuop_func op_b1c0_40_nf;
+extern cpuop_func op_b1c0_40_ff;
+extern cpuop_func op_b1c8_40_nf;
+extern cpuop_func op_b1c8_40_ff;
+extern cpuop_func op_b1d0_40_nf;
+extern cpuop_func op_b1d0_40_ff;
+extern cpuop_func op_b1d8_40_nf;
+extern cpuop_func op_b1d8_40_ff;
+extern cpuop_func op_b1e0_40_nf;
+extern cpuop_func op_b1e0_40_ff;
+extern cpuop_func op_b1e8_40_nf;
+extern cpuop_func op_b1e8_40_ff;
+extern cpuop_func op_b1f0_40_nf;
+extern cpuop_func op_b1f0_40_ff;
+extern cpuop_func op_b1f8_40_nf;
+extern cpuop_func op_b1f8_40_ff;
+extern cpuop_func op_b1f9_40_nf;
+extern cpuop_func op_b1f9_40_ff;
+extern cpuop_func op_b1fa_40_nf;
+extern cpuop_func op_b1fa_40_ff;
+extern cpuop_func op_b1fb_40_nf;
+extern cpuop_func op_b1fb_40_ff;
+extern cpuop_func op_b1fc_40_nf;
+extern cpuop_func op_b1fc_40_ff;
+extern cpuop_func op_c000_40_nf;
+extern cpuop_func op_c000_40_ff;
+extern cpuop_func op_c010_40_nf;
+extern cpuop_func op_c010_40_ff;
+extern cpuop_func op_c018_40_nf;
+extern cpuop_func op_c018_40_ff;
+extern cpuop_func op_c020_40_nf;
+extern cpuop_func op_c020_40_ff;
+extern cpuop_func op_c028_40_nf;
+extern cpuop_func op_c028_40_ff;
+extern cpuop_func op_c030_40_nf;
+extern cpuop_func op_c030_40_ff;
+extern cpuop_func op_c038_40_nf;
+extern cpuop_func op_c038_40_ff;
+extern cpuop_func op_c039_40_nf;
+extern cpuop_func op_c039_40_ff;
+extern cpuop_func op_c03a_40_nf;
+extern cpuop_func op_c03a_40_ff;
+extern cpuop_func op_c03b_40_nf;
+extern cpuop_func op_c03b_40_ff;
+extern cpuop_func op_c03c_40_nf;
+extern cpuop_func op_c03c_40_ff;
+extern cpuop_func op_c040_40_nf;
+extern cpuop_func op_c040_40_ff;
+extern cpuop_func op_c050_40_nf;
+extern cpuop_func op_c050_40_ff;
+extern cpuop_func op_c058_40_nf;
+extern cpuop_func op_c058_40_ff;
+extern cpuop_func op_c060_40_nf;
+extern cpuop_func op_c060_40_ff;
+extern cpuop_func op_c068_40_nf;
+extern cpuop_func op_c068_40_ff;
+extern cpuop_func op_c070_40_nf;
+extern cpuop_func op_c070_40_ff;
+extern cpuop_func op_c078_40_nf;
+extern cpuop_func op_c078_40_ff;
+extern cpuop_func op_c079_40_nf;
+extern cpuop_func op_c079_40_ff;
+extern cpuop_func op_c07a_40_nf;
+extern cpuop_func op_c07a_40_ff;
+extern cpuop_func op_c07b_40_nf;
+extern cpuop_func op_c07b_40_ff;
+extern cpuop_func op_c07c_40_nf;
+extern cpuop_func op_c07c_40_ff;
+extern cpuop_func op_c080_40_nf;
+extern cpuop_func op_c080_40_ff;
+extern cpuop_func op_c090_40_nf;
+extern cpuop_func op_c090_40_ff;
+extern cpuop_func op_c098_40_nf;
+extern cpuop_func op_c098_40_ff;
+extern cpuop_func op_c0a0_40_nf;
+extern cpuop_func op_c0a0_40_ff;
+extern cpuop_func op_c0a8_40_nf;
+extern cpuop_func op_c0a8_40_ff;
+extern cpuop_func op_c0b0_40_nf;
+extern cpuop_func op_c0b0_40_ff;
+extern cpuop_func op_c0b8_40_nf;
+extern cpuop_func op_c0b8_40_ff;
+extern cpuop_func op_c0b9_40_nf;
+extern cpuop_func op_c0b9_40_ff;
+extern cpuop_func op_c0ba_40_nf;
+extern cpuop_func op_c0ba_40_ff;
+extern cpuop_func op_c0bb_40_nf;
+extern cpuop_func op_c0bb_40_ff;
+extern cpuop_func op_c0bc_40_nf;
+extern cpuop_func op_c0bc_40_ff;
+extern cpuop_func op_c0c0_40_nf;
+extern cpuop_func op_c0c0_40_ff;
+extern cpuop_func op_c0d0_40_nf;
+extern cpuop_func op_c0d0_40_ff;
+extern cpuop_func op_c0d8_40_nf;
+extern cpuop_func op_c0d8_40_ff;
+extern cpuop_func op_c0e0_40_nf;
+extern cpuop_func op_c0e0_40_ff;
+extern cpuop_func op_c0e8_40_nf;
+extern cpuop_func op_c0e8_40_ff;
+extern cpuop_func op_c0f0_40_nf;
+extern cpuop_func op_c0f0_40_ff;
+extern cpuop_func op_c0f8_40_nf;
+extern cpuop_func op_c0f8_40_ff;
+extern cpuop_func op_c0f9_40_nf;
+extern cpuop_func op_c0f9_40_ff;
+extern cpuop_func op_c0fa_40_nf;
+extern cpuop_func op_c0fa_40_ff;
+extern cpuop_func op_c0fb_40_nf;
+extern cpuop_func op_c0fb_40_ff;
+extern cpuop_func op_c0fc_40_nf;
+extern cpuop_func op_c0fc_40_ff;
+extern cpuop_func op_c100_40_nf;
+extern cpuop_func op_c100_40_ff;
+extern cpuop_func op_c108_40_nf;
+extern cpuop_func op_c108_40_ff;
+extern cpuop_func op_c110_40_nf;
+extern cpuop_func op_c110_40_ff;
+extern cpuop_func op_c118_40_nf;
+extern cpuop_func op_c118_40_ff;
+extern cpuop_func op_c120_40_nf;
+extern cpuop_func op_c120_40_ff;
+extern cpuop_func op_c128_40_nf;
+extern cpuop_func op_c128_40_ff;
+extern cpuop_func op_c130_40_nf;
+extern cpuop_func op_c130_40_ff;
+extern cpuop_func op_c138_40_nf;
+extern cpuop_func op_c138_40_ff;
+extern cpuop_func op_c139_40_nf;
+extern cpuop_func op_c139_40_ff;
+extern cpuop_func op_c140_40_nf;
+extern cpuop_func op_c140_40_ff;
+extern cpuop_func op_c148_40_nf;
+extern cpuop_func op_c148_40_ff;
+extern cpuop_func op_c150_40_nf;
+extern cpuop_func op_c150_40_ff;
+extern cpuop_func op_c158_40_nf;
+extern cpuop_func op_c158_40_ff;
+extern cpuop_func op_c160_40_nf;
+extern cpuop_func op_c160_40_ff;
+extern cpuop_func op_c168_40_nf;
+extern cpuop_func op_c168_40_ff;
+extern cpuop_func op_c170_40_nf;
+extern cpuop_func op_c170_40_ff;
+extern cpuop_func op_c178_40_nf;
+extern cpuop_func op_c178_40_ff;
+extern cpuop_func op_c179_40_nf;
+extern cpuop_func op_c179_40_ff;
+extern cpuop_func op_c188_40_nf;
+extern cpuop_func op_c188_40_ff;
+extern cpuop_func op_c190_40_nf;
+extern cpuop_func op_c190_40_ff;
+extern cpuop_func op_c198_40_nf;
+extern cpuop_func op_c198_40_ff;
+extern cpuop_func op_c1a0_40_nf;
+extern cpuop_func op_c1a0_40_ff;
+extern cpuop_func op_c1a8_40_nf;
+extern cpuop_func op_c1a8_40_ff;
+extern cpuop_func op_c1b0_40_nf;
+extern cpuop_func op_c1b0_40_ff;
+extern cpuop_func op_c1b8_40_nf;
+extern cpuop_func op_c1b8_40_ff;
+extern cpuop_func op_c1b9_40_nf;
+extern cpuop_func op_c1b9_40_ff;
+extern cpuop_func op_c1c0_40_nf;
+extern cpuop_func op_c1c0_40_ff;
+extern cpuop_func op_c1d0_40_nf;
+extern cpuop_func op_c1d0_40_ff;
+extern cpuop_func op_c1d8_40_nf;
+extern cpuop_func op_c1d8_40_ff;
+extern cpuop_func op_c1e0_40_nf;
+extern cpuop_func op_c1e0_40_ff;
+extern cpuop_func op_c1e8_40_nf;
+extern cpuop_func op_c1e8_40_ff;
+extern cpuop_func op_c1f0_40_nf;
+extern cpuop_func op_c1f0_40_ff;
+extern cpuop_func op_c1f8_40_nf;
+extern cpuop_func op_c1f8_40_ff;
+extern cpuop_func op_c1f9_40_nf;
+extern cpuop_func op_c1f9_40_ff;
+extern cpuop_func op_c1fa_40_nf;
+extern cpuop_func op_c1fa_40_ff;
+extern cpuop_func op_c1fb_40_nf;
+extern cpuop_func op_c1fb_40_ff;
+extern cpuop_func op_c1fc_40_nf;
+extern cpuop_func op_c1fc_40_ff;
+extern cpuop_func op_d000_40_nf;
+extern cpuop_func op_d000_40_ff;
+extern cpuop_func op_d010_40_nf;
+extern cpuop_func op_d010_40_ff;
+extern cpuop_func op_d018_40_nf;
+extern cpuop_func op_d018_40_ff;
+extern cpuop_func op_d020_40_nf;
+extern cpuop_func op_d020_40_ff;
+extern cpuop_func op_d028_40_nf;
+extern cpuop_func op_d028_40_ff;
+extern cpuop_func op_d030_40_nf;
+extern cpuop_func op_d030_40_ff;
+extern cpuop_func op_d038_40_nf;
+extern cpuop_func op_d038_40_ff;
+extern cpuop_func op_d039_40_nf;
+extern cpuop_func op_d039_40_ff;
+extern cpuop_func op_d03a_40_nf;
+extern cpuop_func op_d03a_40_ff;
+extern cpuop_func op_d03b_40_nf;
+extern cpuop_func op_d03b_40_ff;
+extern cpuop_func op_d03c_40_nf;
+extern cpuop_func op_d03c_40_ff;
+extern cpuop_func op_d040_40_nf;
+extern cpuop_func op_d040_40_ff;
+extern cpuop_func op_d048_40_nf;
+extern cpuop_func op_d048_40_ff;
+extern cpuop_func op_d050_40_nf;
+extern cpuop_func op_d050_40_ff;
+extern cpuop_func op_d058_40_nf;
+extern cpuop_func op_d058_40_ff;
+extern cpuop_func op_d060_40_nf;
+extern cpuop_func op_d060_40_ff;
+extern cpuop_func op_d068_40_nf;
+extern cpuop_func op_d068_40_ff;
+extern cpuop_func op_d070_40_nf;
+extern cpuop_func op_d070_40_ff;
+extern cpuop_func op_d078_40_nf;
+extern cpuop_func op_d078_40_ff;
+extern cpuop_func op_d079_40_nf;
+extern cpuop_func op_d079_40_ff;
+extern cpuop_func op_d07a_40_nf;
+extern cpuop_func op_d07a_40_ff;
+extern cpuop_func op_d07b_40_nf;
+extern cpuop_func op_d07b_40_ff;
+extern cpuop_func op_d07c_40_nf;
+extern cpuop_func op_d07c_40_ff;
+extern cpuop_func op_d080_40_nf;
+extern cpuop_func op_d080_40_ff;
+extern cpuop_func op_d088_40_nf;
+extern cpuop_func op_d088_40_ff;
+extern cpuop_func op_d090_40_nf;
+extern cpuop_func op_d090_40_ff;
+extern cpuop_func op_d098_40_nf;
+extern cpuop_func op_d098_40_ff;
+extern cpuop_func op_d0a0_40_nf;
+extern cpuop_func op_d0a0_40_ff;
+extern cpuop_func op_d0a8_40_nf;
+extern cpuop_func op_d0a8_40_ff;
+extern cpuop_func op_d0b0_40_nf;
+extern cpuop_func op_d0b0_40_ff;
+extern cpuop_func op_d0b8_40_nf;
+extern cpuop_func op_d0b8_40_ff;
+extern cpuop_func op_d0b9_40_nf;
+extern cpuop_func op_d0b9_40_ff;
+extern cpuop_func op_d0ba_40_nf;
+extern cpuop_func op_d0ba_40_ff;
+extern cpuop_func op_d0bb_40_nf;
+extern cpuop_func op_d0bb_40_ff;
+extern cpuop_func op_d0bc_40_nf;
+extern cpuop_func op_d0bc_40_ff;
+extern cpuop_func op_d0c0_40_nf;
+extern cpuop_func op_d0c0_40_ff;
+extern cpuop_func op_d0c8_40_nf;
+extern cpuop_func op_d0c8_40_ff;
+extern cpuop_func op_d0d0_40_nf;
+extern cpuop_func op_d0d0_40_ff;
+extern cpuop_func op_d0d8_40_nf;
+extern cpuop_func op_d0d8_40_ff;
+extern cpuop_func op_d0e0_40_nf;
+extern cpuop_func op_d0e0_40_ff;
+extern cpuop_func op_d0e8_40_nf;
+extern cpuop_func op_d0e8_40_ff;
+extern cpuop_func op_d0f0_40_nf;
+extern cpuop_func op_d0f0_40_ff;
+extern cpuop_func op_d0f8_40_nf;
+extern cpuop_func op_d0f8_40_ff;
+extern cpuop_func op_d0f9_40_nf;
+extern cpuop_func op_d0f9_40_ff;
+extern cpuop_func op_d0fa_40_nf;
+extern cpuop_func op_d0fa_40_ff;
+extern cpuop_func op_d0fb_40_nf;
+extern cpuop_func op_d0fb_40_ff;
+extern cpuop_func op_d0fc_40_nf;
+extern cpuop_func op_d0fc_40_ff;
+extern cpuop_func op_d100_40_nf;
+extern cpuop_func op_d100_40_ff;
+extern cpuop_func op_d108_40_nf;
+extern cpuop_func op_d108_40_ff;
+extern cpuop_func op_d110_40_nf;
+extern cpuop_func op_d110_40_ff;
+extern cpuop_func op_d118_40_nf;
+extern cpuop_func op_d118_40_ff;
+extern cpuop_func op_d120_40_nf;
+extern cpuop_func op_d120_40_ff;
+extern cpuop_func op_d128_40_nf;
+extern cpuop_func op_d128_40_ff;
+extern cpuop_func op_d130_40_nf;
+extern cpuop_func op_d130_40_ff;
+extern cpuop_func op_d138_40_nf;
+extern cpuop_func op_d138_40_ff;
+extern cpuop_func op_d139_40_nf;
+extern cpuop_func op_d139_40_ff;
+extern cpuop_func op_d140_40_nf;
+extern cpuop_func op_d140_40_ff;
+extern cpuop_func op_d148_40_nf;
+extern cpuop_func op_d148_40_ff;
+extern cpuop_func op_d150_40_nf;
+extern cpuop_func op_d150_40_ff;
+extern cpuop_func op_d158_40_nf;
+extern cpuop_func op_d158_40_ff;
+extern cpuop_func op_d160_40_nf;
+extern cpuop_func op_d160_40_ff;
+extern cpuop_func op_d168_40_nf;
+extern cpuop_func op_d168_40_ff;
+extern cpuop_func op_d170_40_nf;
+extern cpuop_func op_d170_40_ff;
+extern cpuop_func op_d178_40_nf;
+extern cpuop_func op_d178_40_ff;
+extern cpuop_func op_d179_40_nf;
+extern cpuop_func op_d179_40_ff;
+extern cpuop_func op_d180_40_nf;
+extern cpuop_func op_d180_40_ff;
+extern cpuop_func op_d188_40_nf;
+extern cpuop_func op_d188_40_ff;
+extern cpuop_func op_d190_40_nf;
+extern cpuop_func op_d190_40_ff;
+extern cpuop_func op_d198_40_nf;
+extern cpuop_func op_d198_40_ff;
+extern cpuop_func op_d1a0_40_nf;
+extern cpuop_func op_d1a0_40_ff;
+extern cpuop_func op_d1a8_40_nf;
+extern cpuop_func op_d1a8_40_ff;
+extern cpuop_func op_d1b0_40_nf;
+extern cpuop_func op_d1b0_40_ff;
+extern cpuop_func op_d1b8_40_nf;
+extern cpuop_func op_d1b8_40_ff;
+extern cpuop_func op_d1b9_40_nf;
+extern cpuop_func op_d1b9_40_ff;
+extern cpuop_func op_d1c0_40_nf;
+extern cpuop_func op_d1c0_40_ff;
+extern cpuop_func op_d1c8_40_nf;
+extern cpuop_func op_d1c8_40_ff;
+extern cpuop_func op_d1d0_40_nf;
+extern cpuop_func op_d1d0_40_ff;
+extern cpuop_func op_d1d8_40_nf;
+extern cpuop_func op_d1d8_40_ff;
+extern cpuop_func op_d1e0_40_nf;
+extern cpuop_func op_d1e0_40_ff;
+extern cpuop_func op_d1e8_40_nf;
+extern cpuop_func op_d1e8_40_ff;
+extern cpuop_func op_d1f0_40_nf;
+extern cpuop_func op_d1f0_40_ff;
+extern cpuop_func op_d1f8_40_nf;
+extern cpuop_func op_d1f8_40_ff;
+extern cpuop_func op_d1f9_40_nf;
+extern cpuop_func op_d1f9_40_ff;
+extern cpuop_func op_d1fa_40_nf;
+extern cpuop_func op_d1fa_40_ff;
+extern cpuop_func op_d1fb_40_nf;
+extern cpuop_func op_d1fb_40_ff;
+extern cpuop_func op_d1fc_40_nf;
+extern cpuop_func op_d1fc_40_ff;
+extern cpuop_func op_e000_40_nf;
+extern cpuop_func op_e000_40_ff;
+extern cpuop_func op_e008_40_nf;
+extern cpuop_func op_e008_40_ff;
+extern cpuop_func op_e010_40_nf;
+extern cpuop_func op_e010_40_ff;
+extern cpuop_func op_e018_40_nf;
+extern cpuop_func op_e018_40_ff;
+extern cpuop_func op_e020_40_nf;
+extern cpuop_func op_e020_40_ff;
+extern cpuop_func op_e028_40_nf;
+extern cpuop_func op_e028_40_ff;
+extern cpuop_func op_e030_40_nf;
+extern cpuop_func op_e030_40_ff;
+extern cpuop_func op_e038_40_nf;
+extern cpuop_func op_e038_40_ff;
+extern cpuop_func op_e040_40_nf;
+extern cpuop_func op_e040_40_ff;
+extern cpuop_func op_e048_40_nf;
+extern cpuop_func op_e048_40_ff;
+extern cpuop_func op_e050_40_nf;
+extern cpuop_func op_e050_40_ff;
+extern cpuop_func op_e058_40_nf;
+extern cpuop_func op_e058_40_ff;
+extern cpuop_func op_e060_40_nf;
+extern cpuop_func op_e060_40_ff;
+extern cpuop_func op_e068_40_nf;
+extern cpuop_func op_e068_40_ff;
+extern cpuop_func op_e070_40_nf;
+extern cpuop_func op_e070_40_ff;
+extern cpuop_func op_e078_40_nf;
+extern cpuop_func op_e078_40_ff;
+extern cpuop_func op_e080_40_nf;
+extern cpuop_func op_e080_40_ff;
+extern cpuop_func op_e088_40_nf;
+extern cpuop_func op_e088_40_ff;
+extern cpuop_func op_e090_40_nf;
+extern cpuop_func op_e090_40_ff;
+extern cpuop_func op_e098_40_nf;
+extern cpuop_func op_e098_40_ff;
+extern cpuop_func op_e0a0_40_nf;
+extern cpuop_func op_e0a0_40_ff;
+extern cpuop_func op_e0a8_40_nf;
+extern cpuop_func op_e0a8_40_ff;
+extern cpuop_func op_e0b0_40_nf;
+extern cpuop_func op_e0b0_40_ff;
+extern cpuop_func op_e0b8_40_nf;
+extern cpuop_func op_e0b8_40_ff;
+extern cpuop_func op_e0d0_40_nf;
+extern cpuop_func op_e0d0_40_ff;
+extern cpuop_func op_e0d8_40_nf;
+extern cpuop_func op_e0d8_40_ff;
+extern cpuop_func op_e0e0_40_nf;
+extern cpuop_func op_e0e0_40_ff;
+extern cpuop_func op_e0e8_40_nf;
+extern cpuop_func op_e0e8_40_ff;
+extern cpuop_func op_e0f0_40_nf;
+extern cpuop_func op_e0f0_40_ff;
+extern cpuop_func op_e0f8_40_nf;
+extern cpuop_func op_e0f8_40_ff;
+extern cpuop_func op_e0f9_40_nf;
+extern cpuop_func op_e0f9_40_ff;
+extern cpuop_func op_e100_40_nf;
+extern cpuop_func op_e100_40_ff;
+extern cpuop_func op_e108_40_nf;
+extern cpuop_func op_e108_40_ff;
+extern cpuop_func op_e110_40_nf;
+extern cpuop_func op_e110_40_ff;
+extern cpuop_func op_e118_40_nf;
+extern cpuop_func op_e118_40_ff;
+extern cpuop_func op_e120_40_nf;
+extern cpuop_func op_e120_40_ff;
+extern cpuop_func op_e128_40_nf;
+extern cpuop_func op_e128_40_ff;
+extern cpuop_func op_e130_40_nf;
+extern cpuop_func op_e130_40_ff;
+extern cpuop_func op_e138_40_nf;
+extern cpuop_func op_e138_40_ff;
+extern cpuop_func op_e140_40_nf;
+extern cpuop_func op_e140_40_ff;
+extern cpuop_func op_e148_40_nf;
+extern cpuop_func op_e148_40_ff;
+extern cpuop_func op_e150_40_nf;
+extern cpuop_func op_e150_40_ff;
+extern cpuop_func op_e158_40_nf;
+extern cpuop_func op_e158_40_ff;
+extern cpuop_func op_e160_40_nf;
+extern cpuop_func op_e160_40_ff;
+extern cpuop_func op_e168_40_nf;
+extern cpuop_func op_e168_40_ff;
+extern cpuop_func op_e170_40_nf;
+extern cpuop_func op_e170_40_ff;
+extern cpuop_func op_e178_40_nf;
+extern cpuop_func op_e178_40_ff;
+extern cpuop_func op_e180_40_nf;
+extern cpuop_func op_e180_40_ff;
+extern cpuop_func op_e188_40_nf;
+extern cpuop_func op_e188_40_ff;
+extern cpuop_func op_e190_40_nf;
+extern cpuop_func op_e190_40_ff;
+extern cpuop_func op_e198_40_nf;
+extern cpuop_func op_e198_40_ff;
+extern cpuop_func op_e1a0_40_nf;
+extern cpuop_func op_e1a0_40_ff;
+extern cpuop_func op_e1a8_40_nf;
+extern cpuop_func op_e1a8_40_ff;
+extern cpuop_func op_e1b0_40_nf;
+extern cpuop_func op_e1b0_40_ff;
+extern cpuop_func op_e1b8_40_nf;
+extern cpuop_func op_e1b8_40_ff;
+extern cpuop_func op_e1d0_40_nf;
+extern cpuop_func op_e1d0_40_ff;
+extern cpuop_func op_e1d8_40_nf;
+extern cpuop_func op_e1d8_40_ff;
+extern cpuop_func op_e1e0_40_nf;
+extern cpuop_func op_e1e0_40_ff;
+extern cpuop_func op_e1e8_40_nf;
+extern cpuop_func op_e1e8_40_ff;
+extern cpuop_func op_e1f0_40_nf;
+extern cpuop_func op_e1f0_40_ff;
+extern cpuop_func op_e1f8_40_nf;
+extern cpuop_func op_e1f8_40_ff;
+extern cpuop_func op_e1f9_40_nf;
+extern cpuop_func op_e1f9_40_ff;
+extern cpuop_func op_e2d0_40_nf;
+extern cpuop_func op_e2d0_40_ff;
+extern cpuop_func op_e2d8_40_nf;
+extern cpuop_func op_e2d8_40_ff;
+extern cpuop_func op_e2e0_40_nf;
+extern cpuop_func op_e2e0_40_ff;
+extern cpuop_func op_e2e8_40_nf;
+extern cpuop_func op_e2e8_40_ff;
+extern cpuop_func op_e2f0_40_nf;
+extern cpuop_func op_e2f0_40_ff;
+extern cpuop_func op_e2f8_40_nf;
+extern cpuop_func op_e2f8_40_ff;
+extern cpuop_func op_e2f9_40_nf;
+extern cpuop_func op_e2f9_40_ff;
+extern cpuop_func op_e3d0_40_nf;
+extern cpuop_func op_e3d0_40_ff;
+extern cpuop_func op_e3d8_40_nf;
+extern cpuop_func op_e3d8_40_ff;
+extern cpuop_func op_e3e0_40_nf;
+extern cpuop_func op_e3e0_40_ff;
+extern cpuop_func op_e3e8_40_nf;
+extern cpuop_func op_e3e8_40_ff;
+extern cpuop_func op_e3f0_40_nf;
+extern cpuop_func op_e3f0_40_ff;
+extern cpuop_func op_e3f8_40_nf;
+extern cpuop_func op_e3f8_40_ff;
+extern cpuop_func op_e3f9_40_nf;
+extern cpuop_func op_e3f9_40_ff;
+extern cpuop_func op_e4d0_40_nf;
+extern cpuop_func op_e4d0_40_ff;
+extern cpuop_func op_e4d8_40_nf;
+extern cpuop_func op_e4d8_40_ff;
+extern cpuop_func op_e4e0_40_nf;
+extern cpuop_func op_e4e0_40_ff;
+extern cpuop_func op_e4e8_40_nf;
+extern cpuop_func op_e4e8_40_ff;
+extern cpuop_func op_e4f0_40_nf;
+extern cpuop_func op_e4f0_40_ff;
+extern cpuop_func op_e4f8_40_nf;
+extern cpuop_func op_e4f8_40_ff;
+extern cpuop_func op_e4f9_40_nf;
+extern cpuop_func op_e4f9_40_ff;
+extern cpuop_func op_e5d0_40_nf;
+extern cpuop_func op_e5d0_40_ff;
+extern cpuop_func op_e5d8_40_nf;
+extern cpuop_func op_e5d8_40_ff;
+extern cpuop_func op_e5e0_40_nf;
+extern cpuop_func op_e5e0_40_ff;
+extern cpuop_func op_e5e8_40_nf;
+extern cpuop_func op_e5e8_40_ff;
+extern cpuop_func op_e5f0_40_nf;
+extern cpuop_func op_e5f0_40_ff;
+extern cpuop_func op_e5f8_40_nf;
+extern cpuop_func op_e5f8_40_ff;
+extern cpuop_func op_e5f9_40_nf;
+extern cpuop_func op_e5f9_40_ff;
+extern cpuop_func op_e6d0_40_nf;
+extern cpuop_func op_e6d0_40_ff;
+extern cpuop_func op_e6d8_40_nf;
+extern cpuop_func op_e6d8_40_ff;
+extern cpuop_func op_e6e0_40_nf;
+extern cpuop_func op_e6e0_40_ff;
+extern cpuop_func op_e6e8_40_nf;
+extern cpuop_func op_e6e8_40_ff;
+extern cpuop_func op_e6f0_40_nf;
+extern cpuop_func op_e6f0_40_ff;
+extern cpuop_func op_e6f8_40_nf;
+extern cpuop_func op_e6f8_40_ff;
+extern cpuop_func op_e6f9_40_nf;
+extern cpuop_func op_e6f9_40_ff;
+extern cpuop_func op_e7d0_40_nf;
+extern cpuop_func op_e7d0_40_ff;
+extern cpuop_func op_e7d8_40_nf;
+extern cpuop_func op_e7d8_40_ff;
+extern cpuop_func op_e7e0_40_nf;
+extern cpuop_func op_e7e0_40_ff;
+extern cpuop_func op_e7e8_40_nf;
+extern cpuop_func op_e7e8_40_ff;
+extern cpuop_func op_e7f0_40_nf;
+extern cpuop_func op_e7f0_40_ff;
+extern cpuop_func op_e7f8_40_nf;
+extern cpuop_func op_e7f8_40_ff;
+extern cpuop_func op_e7f9_40_nf;
+extern cpuop_func op_e7f9_40_ff;
+extern cpuop_func op_e8c0_40_nf;
+extern cpuop_func op_e8c0_40_ff;
+extern cpuop_func op_e8d0_40_nf;
+extern cpuop_func op_e8d0_40_ff;
+extern cpuop_func op_e8e8_40_nf;
+extern cpuop_func op_e8e8_40_ff;
+extern cpuop_func op_e8f0_40_nf;
+extern cpuop_func op_e8f0_40_ff;
+extern cpuop_func op_e8f8_40_nf;
+extern cpuop_func op_e8f8_40_ff;
+extern cpuop_func op_e8f9_40_nf;
+extern cpuop_func op_e8f9_40_ff;
+extern cpuop_func op_e8fa_40_nf;
+extern cpuop_func op_e8fa_40_ff;
+extern cpuop_func op_e8fb_40_nf;
+extern cpuop_func op_e8fb_40_ff;
+extern cpuop_func op_e9c0_40_nf;
+extern cpuop_func op_e9c0_40_ff;
+extern cpuop_func op_e9d0_40_nf;
+extern cpuop_func op_e9d0_40_ff;
+extern cpuop_func op_e9e8_40_nf;
+extern cpuop_func op_e9e8_40_ff;
+extern cpuop_func op_e9f0_40_nf;
+extern cpuop_func op_e9f0_40_ff;
+extern cpuop_func op_e9f8_40_nf;
+extern cpuop_func op_e9f8_40_ff;
+extern cpuop_func op_e9f9_40_nf;
+extern cpuop_func op_e9f9_40_ff;
+extern cpuop_func op_e9fa_40_nf;
+extern cpuop_func op_e9fa_40_ff;
+extern cpuop_func op_e9fb_40_nf;
+extern cpuop_func op_e9fb_40_ff;
+extern cpuop_func op_eac0_40_nf;
+extern cpuop_func op_eac0_40_ff;
+extern cpuop_func op_ead0_40_nf;
+extern cpuop_func op_ead0_40_ff;
+extern cpuop_func op_eae8_40_nf;
+extern cpuop_func op_eae8_40_ff;
+extern cpuop_func op_eaf0_40_nf;
+extern cpuop_func op_eaf0_40_ff;
+extern cpuop_func op_eaf8_40_nf;
+extern cpuop_func op_eaf8_40_ff;
+extern cpuop_func op_eaf9_40_nf;
+extern cpuop_func op_eaf9_40_ff;
+extern cpuop_func op_ebc0_40_nf;
+extern cpuop_func op_ebc0_40_ff;
+extern cpuop_func op_ebd0_40_nf;
+extern cpuop_func op_ebd0_40_ff;
+extern cpuop_func op_ebe8_40_nf;
+extern cpuop_func op_ebe8_40_ff;
+extern cpuop_func op_ebf0_40_nf;
+extern cpuop_func op_ebf0_40_ff;
+extern cpuop_func op_ebf8_40_nf;
+extern cpuop_func op_ebf8_40_ff;
+extern cpuop_func op_ebf9_40_nf;
+extern cpuop_func op_ebf9_40_ff;
+extern cpuop_func op_ebfa_40_nf;
+extern cpuop_func op_ebfa_40_ff;
+extern cpuop_func op_ebfb_40_nf;
+extern cpuop_func op_ebfb_40_ff;
+extern cpuop_func op_ecc0_40_nf;
+extern cpuop_func op_ecc0_40_ff;
+extern cpuop_func op_ecd0_40_nf;
+extern cpuop_func op_ecd0_40_ff;
+extern cpuop_func op_ece8_40_nf;
+extern cpuop_func op_ece8_40_ff;
+extern cpuop_func op_ecf0_40_nf;
+extern cpuop_func op_ecf0_40_ff;
+extern cpuop_func op_ecf8_40_nf;
+extern cpuop_func op_ecf8_40_ff;
+extern cpuop_func op_ecf9_40_nf;
+extern cpuop_func op_ecf9_40_ff;
+extern cpuop_func op_edc0_40_nf;
+extern cpuop_func op_edc0_40_ff;
+extern cpuop_func op_edd0_40_nf;
+extern cpuop_func op_edd0_40_ff;
+extern cpuop_func op_ede8_40_nf;
+extern cpuop_func op_ede8_40_ff;
+extern cpuop_func op_edf0_40_nf;
+extern cpuop_func op_edf0_40_ff;
+extern cpuop_func op_edf8_40_nf;
+extern cpuop_func op_edf8_40_ff;
+extern cpuop_func op_edf9_40_nf;
+extern cpuop_func op_edf9_40_ff;
+extern cpuop_func op_edfa_40_nf;
+extern cpuop_func op_edfa_40_ff;
+extern cpuop_func op_edfb_40_nf;
+extern cpuop_func op_edfb_40_ff;
+extern cpuop_func op_eec0_40_nf;
+extern cpuop_func op_eec0_40_ff;
+extern cpuop_func op_eed0_40_nf;
+extern cpuop_func op_eed0_40_ff;
+extern cpuop_func op_eee8_40_nf;
+extern cpuop_func op_eee8_40_ff;
+extern cpuop_func op_eef0_40_nf;
+extern cpuop_func op_eef0_40_ff;
+extern cpuop_func op_eef8_40_nf;
+extern cpuop_func op_eef8_40_ff;
+extern cpuop_func op_eef9_40_nf;
+extern cpuop_func op_eef9_40_ff;
+extern cpuop_func op_efc0_40_nf;
+extern cpuop_func op_efc0_40_ff;
+extern cpuop_func op_efd0_40_nf;
+extern cpuop_func op_efd0_40_ff;
+extern cpuop_func op_efe8_40_nf;
+extern cpuop_func op_efe8_40_ff;
+extern cpuop_func op_eff0_40_nf;
+extern cpuop_func op_eff0_40_ff;
+extern cpuop_func op_eff8_40_nf;
+extern cpuop_func op_eff8_40_ff;
+extern cpuop_func op_eff9_40_nf;
+extern cpuop_func op_eff9_40_ff;
+extern cpuop_func op_f000_40_nf;
+extern cpuop_func op_f000_40_ff;
+extern cpuop_func op_f008_40_nf;
+extern cpuop_func op_f008_40_ff;
+extern cpuop_func op_f010_40_nf;
+extern cpuop_func op_f010_40_ff;
+extern cpuop_func op_f018_40_nf;
+extern cpuop_func op_f018_40_ff;
+extern cpuop_func op_f020_40_nf;
+extern cpuop_func op_f020_40_ff;
+extern cpuop_func op_f028_40_nf;
+extern cpuop_func op_f028_40_ff;
+extern cpuop_func op_f030_40_nf;
+extern cpuop_func op_f030_40_ff;
+extern cpuop_func op_f038_40_nf;
+extern cpuop_func op_f038_40_ff;
+extern cpuop_func op_f039_40_nf;
+extern cpuop_func op_f039_40_ff;
+extern cpuop_func op_f200_40_nf;
+extern cpuop_func op_f200_40_ff;
+extern cpuop_func op_f208_40_nf;
+extern cpuop_func op_f208_40_ff;
+extern cpuop_func op_f210_40_nf;
+extern cpuop_func op_f210_40_ff;
+extern cpuop_func op_f218_40_nf;
+extern cpuop_func op_f218_40_ff;
+extern cpuop_func op_f220_40_nf;
+extern cpuop_func op_f220_40_ff;
+extern cpuop_func op_f228_40_nf;
+extern cpuop_func op_f228_40_ff;
+extern cpuop_func op_f230_40_nf;
+extern cpuop_func op_f230_40_ff;
+extern cpuop_func op_f238_40_nf;
+extern cpuop_func op_f238_40_ff;
+extern cpuop_func op_f239_40_nf;
+extern cpuop_func op_f239_40_ff;
+extern cpuop_func op_f23a_40_nf;
+extern cpuop_func op_f23a_40_ff;
+extern cpuop_func op_f23b_40_nf;
+extern cpuop_func op_f23b_40_ff;
+extern cpuop_func op_f23c_40_nf;
+extern cpuop_func op_f23c_40_ff;
+extern cpuop_func op_f240_40_nf;
+extern cpuop_func op_f240_40_ff;
+extern cpuop_func op_f248_40_nf;
+extern cpuop_func op_f248_40_ff;
+extern cpuop_func op_f250_40_nf;
+extern cpuop_func op_f250_40_ff;
+extern cpuop_func op_f258_40_nf;
+extern cpuop_func op_f258_40_ff;
+extern cpuop_func op_f260_40_nf;
+extern cpuop_func op_f260_40_ff;
+extern cpuop_func op_f268_40_nf;
+extern cpuop_func op_f268_40_ff;
+extern cpuop_func op_f270_40_nf;
+extern cpuop_func op_f270_40_ff;
+extern cpuop_func op_f278_40_nf;
+extern cpuop_func op_f278_40_ff;
+extern cpuop_func op_f279_40_nf;
+extern cpuop_func op_f279_40_ff;
+extern cpuop_func op_f27a_40_nf;
+extern cpuop_func op_f27a_40_ff;
+extern cpuop_func op_f27b_40_nf;
+extern cpuop_func op_f27b_40_ff;
+extern cpuop_func op_f27c_40_nf;
+extern cpuop_func op_f27c_40_ff;
+extern cpuop_func op_f280_40_nf;
+extern cpuop_func op_f280_40_ff;
+extern cpuop_func op_f2c0_40_nf;
+extern cpuop_func op_f2c0_40_ff;
+extern cpuop_func op_f310_40_nf;
+extern cpuop_func op_f310_40_ff;
+extern cpuop_func op_f320_40_nf;
+extern cpuop_func op_f320_40_ff;
+extern cpuop_func op_f328_40_nf;
+extern cpuop_func op_f328_40_ff;
+extern cpuop_func op_f330_40_nf;
+extern cpuop_func op_f330_40_ff;
+extern cpuop_func op_f338_40_nf;
+extern cpuop_func op_f338_40_ff;
+extern cpuop_func op_f339_40_nf;
+extern cpuop_func op_f339_40_ff;
+extern cpuop_func op_f350_40_nf;
+extern cpuop_func op_f350_40_ff;
+extern cpuop_func op_f358_40_nf;
+extern cpuop_func op_f358_40_ff;
+extern cpuop_func op_f368_40_nf;
+extern cpuop_func op_f368_40_ff;
+extern cpuop_func op_f370_40_nf;
+extern cpuop_func op_f370_40_ff;
+extern cpuop_func op_f378_40_nf;
+extern cpuop_func op_f378_40_ff;
+extern cpuop_func op_f379_40_nf;
+extern cpuop_func op_f379_40_ff;
+extern cpuop_func op_f37a_40_nf;
+extern cpuop_func op_f37a_40_ff;
+extern cpuop_func op_f37b_40_nf;
+extern cpuop_func op_f37b_40_ff;
+extern cpuop_func op_f408_40_nf;
+extern cpuop_func op_f408_40_ff;
+extern cpuop_func op_f410_40_nf;
+extern cpuop_func op_f410_40_ff;
+extern cpuop_func op_f418_40_nf;
+extern cpuop_func op_f418_40_ff;
+extern cpuop_func op_f419_40_nf;
+extern cpuop_func op_f419_40_ff;
+extern cpuop_func op_f41a_40_nf;
+extern cpuop_func op_f41a_40_ff;
+extern cpuop_func op_f41b_40_nf;
+extern cpuop_func op_f41b_40_ff;
+extern cpuop_func op_f41c_40_nf;
+extern cpuop_func op_f41c_40_ff;
+extern cpuop_func op_f41d_40_nf;
+extern cpuop_func op_f41d_40_ff;
+extern cpuop_func op_f41e_40_nf;
+extern cpuop_func op_f41e_40_ff;
+extern cpuop_func op_f41f_40_nf;
+extern cpuop_func op_f41f_40_ff;
+extern cpuop_func op_f428_40_nf;
+extern cpuop_func op_f428_40_ff;
+extern cpuop_func op_f430_40_nf;
+extern cpuop_func op_f430_40_ff;
+extern cpuop_func op_f438_40_nf;
+extern cpuop_func op_f438_40_ff;
+extern cpuop_func op_f439_40_nf;
+extern cpuop_func op_f439_40_ff;
+extern cpuop_func op_f43a_40_nf;
+extern cpuop_func op_f43a_40_ff;
+extern cpuop_func op_f43b_40_nf;
+extern cpuop_func op_f43b_40_ff;
+extern cpuop_func op_f43c_40_nf;
+extern cpuop_func op_f43c_40_ff;
+extern cpuop_func op_f43d_40_nf;
+extern cpuop_func op_f43d_40_ff;
+extern cpuop_func op_f43e_40_nf;
+extern cpuop_func op_f43e_40_ff;
+extern cpuop_func op_f43f_40_nf;
+extern cpuop_func op_f43f_40_ff;
+extern cpuop_func op_f500_40_nf;
+extern cpuop_func op_f500_40_ff;
+extern cpuop_func op_f508_40_nf;
+extern cpuop_func op_f508_40_ff;
+extern cpuop_func op_f510_40_nf;
+extern cpuop_func op_f510_40_ff;
+extern cpuop_func op_f518_40_nf;
+extern cpuop_func op_f518_40_ff;
+extern cpuop_func op_f548_40_nf;
+extern cpuop_func op_f548_40_ff;
+extern cpuop_func op_f568_40_nf;
+extern cpuop_func op_f568_40_ff;
+extern cpuop_func op_f588_40_nf;
+extern cpuop_func op_f588_40_ff;
+extern cpuop_func op_f5c8_40_nf;
+extern cpuop_func op_f5c8_40_ff;
+extern cpuop_func op_f600_40_nf;
+extern cpuop_func op_f600_40_ff;
+extern cpuop_func op_f608_40_nf;
+extern cpuop_func op_f608_40_ff;
+extern cpuop_func op_f610_40_nf;
+extern cpuop_func op_f610_40_ff;
+extern cpuop_func op_f618_40_nf;
+extern cpuop_func op_f618_40_ff;
+extern cpuop_func op_f620_40_nf;
+extern cpuop_func op_f620_40_ff;
+extern cpuop_func op_f800_40_nf;
+extern cpuop_func op_f800_40_ff;
+extern cpuop_func op_4800_42_nf;
+extern cpuop_func op_4800_42_ff;
+extern cpuop_func op_4810_42_nf;
+extern cpuop_func op_4810_42_ff;
+extern cpuop_func op_4818_42_nf;
+extern cpuop_func op_4818_42_ff;
+extern cpuop_func op_4820_42_nf;
+extern cpuop_func op_4820_42_ff;
+extern cpuop_func op_4828_42_nf;
+extern cpuop_func op_4828_42_ff;
+extern cpuop_func op_4830_42_nf;
+extern cpuop_func op_4830_42_ff;
+extern cpuop_func op_4838_42_nf;
+extern cpuop_func op_4838_42_ff;
+extern cpuop_func op_4839_42_nf;
+extern cpuop_func op_4839_42_ff;
+extern cpuop_func op_8100_42_nf;
+extern cpuop_func op_8100_42_ff;
+extern cpuop_func op_8108_42_nf;
+extern cpuop_func op_8108_42_ff;
+extern cpuop_func op_c100_42_nf;
+extern cpuop_func op_c100_42_ff;
+extern cpuop_func op_c108_42_nf;
+extern cpuop_func op_c108_42_ff;
+extern cpuop_func op_0030_44_nf;
+extern cpuop_func op_0030_44_ff;
+extern cpuop_func op_0070_44_nf;
+extern cpuop_func op_0070_44_ff;
+extern cpuop_func op_00b0_44_nf;
+extern cpuop_func op_00b0_44_ff;
+extern cpuop_func op_0130_44_nf;
+extern cpuop_func op_0130_44_ff;
+extern cpuop_func op_013b_44_nf;
+extern cpuop_func op_013b_44_ff;
+extern cpuop_func op_0170_44_nf;
+extern cpuop_func op_0170_44_ff;
+extern cpuop_func op_01b0_44_nf;
+extern cpuop_func op_01b0_44_ff;
+extern cpuop_func op_01f0_44_nf;
+extern cpuop_func op_01f0_44_ff;
+extern cpuop_func op_0230_44_nf;
+extern cpuop_func op_0230_44_ff;
+extern cpuop_func op_0270_44_nf;
+extern cpuop_func op_0270_44_ff;
+extern cpuop_func op_02b0_44_nf;
+extern cpuop_func op_02b0_44_ff;
+extern cpuop_func op_0430_44_nf;
+extern cpuop_func op_0430_44_ff;
+extern cpuop_func op_0470_44_nf;
+extern cpuop_func op_0470_44_ff;
+extern cpuop_func op_04b0_44_nf;
+extern cpuop_func op_04b0_44_ff;
+extern cpuop_func op_0630_44_nf;
+extern cpuop_func op_0630_44_ff;
+extern cpuop_func op_0670_44_nf;
+extern cpuop_func op_0670_44_ff;
+extern cpuop_func op_06b0_44_nf;
+extern cpuop_func op_06b0_44_ff;
+extern cpuop_func op_0830_44_nf;
+extern cpuop_func op_0830_44_ff;
+extern cpuop_func op_083b_44_nf;
+extern cpuop_func op_083b_44_ff;
+extern cpuop_func op_0870_44_nf;
+extern cpuop_func op_0870_44_ff;
+extern cpuop_func op_08b0_44_nf;
+extern cpuop_func op_08b0_44_ff;
+extern cpuop_func op_08f0_44_nf;
+extern cpuop_func op_08f0_44_ff;
+extern cpuop_func op_0a30_44_nf;
+extern cpuop_func op_0a30_44_ff;
+extern cpuop_func op_0a70_44_nf;
+extern cpuop_func op_0a70_44_ff;
+extern cpuop_func op_0ab0_44_nf;
+extern cpuop_func op_0ab0_44_ff;
+extern cpuop_func op_0c30_44_nf;
+extern cpuop_func op_0c30_44_ff;
+extern cpuop_func op_0c70_44_nf;
+extern cpuop_func op_0c70_44_ff;
+extern cpuop_func op_0cb0_44_nf;
+extern cpuop_func op_0cb0_44_ff;
+extern cpuop_func op_1030_44_nf;
+extern cpuop_func op_1030_44_ff;
+extern cpuop_func op_103b_44_nf;
+extern cpuop_func op_103b_44_ff;
+extern cpuop_func op_10b0_44_nf;
+extern cpuop_func op_10b0_44_ff;
+extern cpuop_func op_10bb_44_nf;
+extern cpuop_func op_10bb_44_ff;
+extern cpuop_func op_10f0_44_nf;
+extern cpuop_func op_10f0_44_ff;
+extern cpuop_func op_10fb_44_nf;
+extern cpuop_func op_10fb_44_ff;
+extern cpuop_func op_1130_44_nf;
+extern cpuop_func op_1130_44_ff;
+extern cpuop_func op_113b_44_nf;
+extern cpuop_func op_113b_44_ff;
+extern cpuop_func op_1170_44_nf;
+extern cpuop_func op_1170_44_ff;
+extern cpuop_func op_117b_44_nf;
+extern cpuop_func op_117b_44_ff;
+extern cpuop_func op_1180_44_nf;
+extern cpuop_func op_1180_44_ff;
+extern cpuop_func op_1190_44_nf;
+extern cpuop_func op_1190_44_ff;
+extern cpuop_func op_1198_44_nf;
+extern cpuop_func op_1198_44_ff;
+extern cpuop_func op_11a0_44_nf;
+extern cpuop_func op_11a0_44_ff;
+extern cpuop_func op_11a8_44_nf;
+extern cpuop_func op_11a8_44_ff;
+extern cpuop_func op_11b0_44_nf;
+extern cpuop_func op_11b0_44_ff;
+extern cpuop_func op_11b8_44_nf;
+extern cpuop_func op_11b8_44_ff;
+extern cpuop_func op_11b9_44_nf;
+extern cpuop_func op_11b9_44_ff;
+extern cpuop_func op_11ba_44_nf;
+extern cpuop_func op_11ba_44_ff;
+extern cpuop_func op_11bb_44_nf;
+extern cpuop_func op_11bb_44_ff;
+extern cpuop_func op_11bc_44_nf;
+extern cpuop_func op_11bc_44_ff;
+extern cpuop_func op_11f0_44_nf;
+extern cpuop_func op_11f0_44_ff;
+extern cpuop_func op_11fb_44_nf;
+extern cpuop_func op_11fb_44_ff;
+extern cpuop_func op_13f0_44_nf;
+extern cpuop_func op_13f0_44_ff;
+extern cpuop_func op_13fb_44_nf;
+extern cpuop_func op_13fb_44_ff;
+extern cpuop_func op_2030_44_nf;
+extern cpuop_func op_2030_44_ff;
+extern cpuop_func op_203b_44_nf;
+extern cpuop_func op_203b_44_ff;
+extern cpuop_func op_2070_44_nf;
+extern cpuop_func op_2070_44_ff;
+extern cpuop_func op_207b_44_nf;
+extern cpuop_func op_207b_44_ff;
+extern cpuop_func op_20b0_44_nf;
+extern cpuop_func op_20b0_44_ff;
+extern cpuop_func op_20bb_44_nf;
+extern cpuop_func op_20bb_44_ff;
+extern cpuop_func op_20f0_44_nf;
+extern cpuop_func op_20f0_44_ff;
+extern cpuop_func op_20fb_44_nf;
+extern cpuop_func op_20fb_44_ff;
+extern cpuop_func op_2130_44_nf;
+extern cpuop_func op_2130_44_ff;
+extern cpuop_func op_213b_44_nf;
+extern cpuop_func op_213b_44_ff;
+extern cpuop_func op_2170_44_nf;
+extern cpuop_func op_2170_44_ff;
+extern cpuop_func op_217b_44_nf;
+extern cpuop_func op_217b_44_ff;
+extern cpuop_func op_2180_44_nf;
+extern cpuop_func op_2180_44_ff;
+extern cpuop_func op_2188_44_nf;
+extern cpuop_func op_2188_44_ff;
+extern cpuop_func op_2190_44_nf;
+extern cpuop_func op_2190_44_ff;
+extern cpuop_func op_2198_44_nf;
+extern cpuop_func op_2198_44_ff;
+extern cpuop_func op_21a0_44_nf;
+extern cpuop_func op_21a0_44_ff;
+extern cpuop_func op_21a8_44_nf;
+extern cpuop_func op_21a8_44_ff;
+extern cpuop_func op_21b0_44_nf;
+extern cpuop_func op_21b0_44_ff;
+extern cpuop_func op_21b8_44_nf;
+extern cpuop_func op_21b8_44_ff;
+extern cpuop_func op_21b9_44_nf;
+extern cpuop_func op_21b9_44_ff;
+extern cpuop_func op_21ba_44_nf;
+extern cpuop_func op_21ba_44_ff;
+extern cpuop_func op_21bb_44_nf;
+extern cpuop_func op_21bb_44_ff;
+extern cpuop_func op_21bc_44_nf;
+extern cpuop_func op_21bc_44_ff;
+extern cpuop_func op_21f0_44_nf;
+extern cpuop_func op_21f0_44_ff;
+extern cpuop_func op_21fb_44_nf;
+extern cpuop_func op_21fb_44_ff;
+extern cpuop_func op_23f0_44_nf;
+extern cpuop_func op_23f0_44_ff;
+extern cpuop_func op_23fb_44_nf;
+extern cpuop_func op_23fb_44_ff;
+extern cpuop_func op_3030_44_nf;
+extern cpuop_func op_3030_44_ff;
+extern cpuop_func op_303b_44_nf;
+extern cpuop_func op_303b_44_ff;
+extern cpuop_func op_3070_44_nf;
+extern cpuop_func op_3070_44_ff;
+extern cpuop_func op_307b_44_nf;
+extern cpuop_func op_307b_44_ff;
+extern cpuop_func op_30b0_44_nf;
+extern cpuop_func op_30b0_44_ff;
+extern cpuop_func op_30bb_44_nf;
+extern cpuop_func op_30bb_44_ff;
+extern cpuop_func op_30f0_44_nf;
+extern cpuop_func op_30f0_44_ff;
+extern cpuop_func op_30fb_44_nf;
+extern cpuop_func op_30fb_44_ff;
+extern cpuop_func op_3130_44_nf;
+extern cpuop_func op_3130_44_ff;
+extern cpuop_func op_313b_44_nf;
+extern cpuop_func op_313b_44_ff;
+extern cpuop_func op_3170_44_nf;
+extern cpuop_func op_3170_44_ff;
+extern cpuop_func op_317b_44_nf;
+extern cpuop_func op_317b_44_ff;
+extern cpuop_func op_3180_44_nf;
+extern cpuop_func op_3180_44_ff;
+extern cpuop_func op_3188_44_nf;
+extern cpuop_func op_3188_44_ff;
+extern cpuop_func op_3190_44_nf;
+extern cpuop_func op_3190_44_ff;
+extern cpuop_func op_3198_44_nf;
+extern cpuop_func op_3198_44_ff;
+extern cpuop_func op_31a0_44_nf;
+extern cpuop_func op_31a0_44_ff;
+extern cpuop_func op_31a8_44_nf;
+extern cpuop_func op_31a8_44_ff;
+extern cpuop_func op_31b0_44_nf;
+extern cpuop_func op_31b0_44_ff;
+extern cpuop_func op_31b8_44_nf;
+extern cpuop_func op_31b8_44_ff;
+extern cpuop_func op_31b9_44_nf;
+extern cpuop_func op_31b9_44_ff;
+extern cpuop_func op_31ba_44_nf;
+extern cpuop_func op_31ba_44_ff;
+extern cpuop_func op_31bb_44_nf;
+extern cpuop_func op_31bb_44_ff;
+extern cpuop_func op_31bc_44_nf;
+extern cpuop_func op_31bc_44_ff;
+extern cpuop_func op_31f0_44_nf;
+extern cpuop_func op_31f0_44_ff;
+extern cpuop_func op_31fb_44_nf;
+extern cpuop_func op_31fb_44_ff;
+extern cpuop_func op_33f0_44_nf;
+extern cpuop_func op_33f0_44_ff;
+extern cpuop_func op_33fb_44_nf;
+extern cpuop_func op_33fb_44_ff;
+extern cpuop_func op_4030_44_nf;
+extern cpuop_func op_4030_44_ff;
+extern cpuop_func op_4070_44_nf;
+extern cpuop_func op_4070_44_ff;
+extern cpuop_func op_40b0_44_nf;
+extern cpuop_func op_40b0_44_ff;
+extern cpuop_func op_40f0_44_nf;
+extern cpuop_func op_40f0_44_ff;
+extern cpuop_func op_41b0_44_nf;
+extern cpuop_func op_41b0_44_ff;
+extern cpuop_func op_41bb_44_nf;
+extern cpuop_func op_41bb_44_ff;
+extern cpuop_func op_41f0_44_nf;
+extern cpuop_func op_41f0_44_ff;
+extern cpuop_func op_41fb_44_nf;
+extern cpuop_func op_41fb_44_ff;
+extern cpuop_func op_4230_44_nf;
+extern cpuop_func op_4230_44_ff;
+extern cpuop_func op_4270_44_nf;
+extern cpuop_func op_4270_44_ff;
+extern cpuop_func op_42b0_44_nf;
+extern cpuop_func op_42b0_44_ff;
+extern cpuop_func op_42f0_44_nf;
+extern cpuop_func op_42f0_44_ff;
+extern cpuop_func op_4430_44_nf;
+extern cpuop_func op_4430_44_ff;
+extern cpuop_func op_4470_44_nf;
+extern cpuop_func op_4470_44_ff;
+extern cpuop_func op_44b0_44_nf;
+extern cpuop_func op_44b0_44_ff;
+extern cpuop_func op_44f0_44_nf;
+extern cpuop_func op_44f0_44_ff;
+extern cpuop_func op_44fb_44_nf;
+extern cpuop_func op_44fb_44_ff;
+extern cpuop_func op_4630_44_nf;
+extern cpuop_func op_4630_44_ff;
+extern cpuop_func op_4670_44_nf;
+extern cpuop_func op_4670_44_ff;
+extern cpuop_func op_46b0_44_nf;
+extern cpuop_func op_46b0_44_ff;
+extern cpuop_func op_46f0_44_nf;
+extern cpuop_func op_46f0_44_ff;
+extern cpuop_func op_46fb_44_nf;
+extern cpuop_func op_46fb_44_ff;
+extern cpuop_func op_4830_44_nf;
+extern cpuop_func op_4830_44_ff;
+extern cpuop_func op_4870_44_nf;
+extern cpuop_func op_4870_44_ff;
+extern cpuop_func op_487b_44_nf;
+extern cpuop_func op_487b_44_ff;
+extern cpuop_func op_48b0_44_nf;
+extern cpuop_func op_48b0_44_ff;
+extern cpuop_func op_48f0_44_nf;
+extern cpuop_func op_48f0_44_ff;
+extern cpuop_func op_4a30_44_nf;
+extern cpuop_func op_4a30_44_ff;
+extern cpuop_func op_4a70_44_nf;
+extern cpuop_func op_4a70_44_ff;
+extern cpuop_func op_4ab0_44_nf;
+extern cpuop_func op_4ab0_44_ff;
+extern cpuop_func op_4ac0_44_nf;
+extern cpuop_func op_4ac0_44_ff;
+extern cpuop_func op_4ad0_44_nf;
+extern cpuop_func op_4ad0_44_ff;
+extern cpuop_func op_4ad8_44_nf;
+extern cpuop_func op_4ad8_44_ff;
+extern cpuop_func op_4ae0_44_nf;
+extern cpuop_func op_4ae0_44_ff;
+extern cpuop_func op_4ae8_44_nf;
+extern cpuop_func op_4ae8_44_ff;
+extern cpuop_func op_4af0_44_nf;
+extern cpuop_func op_4af0_44_ff;
+extern cpuop_func op_4af8_44_nf;
+extern cpuop_func op_4af8_44_ff;
+extern cpuop_func op_4af9_44_nf;
+extern cpuop_func op_4af9_44_ff;
+extern cpuop_func op_4cb0_44_nf;
+extern cpuop_func op_4cb0_44_ff;
+extern cpuop_func op_4cbb_44_nf;
+extern cpuop_func op_4cbb_44_ff;
+extern cpuop_func op_4cf0_44_nf;
+extern cpuop_func op_4cf0_44_ff;
+extern cpuop_func op_4cfb_44_nf;
+extern cpuop_func op_4cfb_44_ff;
+extern cpuop_func op_4eb0_44_nf;
+extern cpuop_func op_4eb0_44_ff;
+extern cpuop_func op_4ebb_44_nf;
+extern cpuop_func op_4ebb_44_ff;
+extern cpuop_func op_4ef0_44_nf;
+extern cpuop_func op_4ef0_44_ff;
+extern cpuop_func op_4efb_44_nf;
+extern cpuop_func op_4efb_44_ff;
+extern cpuop_func op_5030_44_nf;
+extern cpuop_func op_5030_44_ff;
+extern cpuop_func op_5070_44_nf;
+extern cpuop_func op_5070_44_ff;
+extern cpuop_func op_50b0_44_nf;
+extern cpuop_func op_50b0_44_ff;
+extern cpuop_func op_50f0_44_nf;
+extern cpuop_func op_50f0_44_ff;
+extern cpuop_func op_5130_44_nf;
+extern cpuop_func op_5130_44_ff;
+extern cpuop_func op_5170_44_nf;
+extern cpuop_func op_5170_44_ff;
+extern cpuop_func op_51b0_44_nf;
+extern cpuop_func op_51b0_44_ff;
+extern cpuop_func op_51f0_44_nf;
+extern cpuop_func op_51f0_44_ff;
+extern cpuop_func op_52f0_44_nf;
+extern cpuop_func op_52f0_44_ff;
+extern cpuop_func op_53f0_44_nf;
+extern cpuop_func op_53f0_44_ff;
+extern cpuop_func op_54f0_44_nf;
+extern cpuop_func op_54f0_44_ff;
+extern cpuop_func op_55f0_44_nf;
+extern cpuop_func op_55f0_44_ff;
+extern cpuop_func op_56f0_44_nf;
+extern cpuop_func op_56f0_44_ff;
+extern cpuop_func op_57f0_44_nf;
+extern cpuop_func op_57f0_44_ff;
+extern cpuop_func op_58f0_44_nf;
+extern cpuop_func op_58f0_44_ff;
+extern cpuop_func op_59f0_44_nf;
+extern cpuop_func op_59f0_44_ff;
+extern cpuop_func op_5af0_44_nf;
+extern cpuop_func op_5af0_44_ff;
+extern cpuop_func op_5bf0_44_nf;
+extern cpuop_func op_5bf0_44_ff;
+extern cpuop_func op_5cf0_44_nf;
+extern cpuop_func op_5cf0_44_ff;
+extern cpuop_func op_5df0_44_nf;
+extern cpuop_func op_5df0_44_ff;
+extern cpuop_func op_5ef0_44_nf;
+extern cpuop_func op_5ef0_44_ff;
+extern cpuop_func op_5ff0_44_nf;
+extern cpuop_func op_5ff0_44_ff;
+extern cpuop_func op_60ff_44_nf;
+extern cpuop_func op_60ff_44_ff;
+extern cpuop_func op_61ff_44_nf;
+extern cpuop_func op_61ff_44_ff;
+extern cpuop_func op_62ff_44_nf;
+extern cpuop_func op_62ff_44_ff;
+extern cpuop_func op_63ff_44_nf;
+extern cpuop_func op_63ff_44_ff;
+extern cpuop_func op_64ff_44_nf;
+extern cpuop_func op_64ff_44_ff;
+extern cpuop_func op_65ff_44_nf;
+extern cpuop_func op_65ff_44_ff;
+extern cpuop_func op_66ff_44_nf;
+extern cpuop_func op_66ff_44_ff;
+extern cpuop_func op_67ff_44_nf;
+extern cpuop_func op_67ff_44_ff;
+extern cpuop_func op_68ff_44_nf;
+extern cpuop_func op_68ff_44_ff;
+extern cpuop_func op_69ff_44_nf;
+extern cpuop_func op_69ff_44_ff;
+extern cpuop_func op_6aff_44_nf;
+extern cpuop_func op_6aff_44_ff;
+extern cpuop_func op_6bff_44_nf;
+extern cpuop_func op_6bff_44_ff;
+extern cpuop_func op_6cff_44_nf;
+extern cpuop_func op_6cff_44_ff;
+extern cpuop_func op_6dff_44_nf;
+extern cpuop_func op_6dff_44_ff;
+extern cpuop_func op_6eff_44_nf;
+extern cpuop_func op_6eff_44_ff;
+extern cpuop_func op_6fff_44_nf;
+extern cpuop_func op_6fff_44_ff;
+extern cpuop_func op_8030_44_nf;
+extern cpuop_func op_8030_44_ff;
+extern cpuop_func op_803b_44_nf;
+extern cpuop_func op_803b_44_ff;
+extern cpuop_func op_8070_44_nf;
+extern cpuop_func op_8070_44_ff;
+extern cpuop_func op_807b_44_nf;
+extern cpuop_func op_807b_44_ff;
+extern cpuop_func op_80b0_44_nf;
+extern cpuop_func op_80b0_44_ff;
+extern cpuop_func op_80bb_44_nf;
+extern cpuop_func op_80bb_44_ff;
+extern cpuop_func op_80f0_44_nf;
+extern cpuop_func op_80f0_44_ff;
+extern cpuop_func op_80fb_44_nf;
+extern cpuop_func op_80fb_44_ff;
+extern cpuop_func op_8130_44_nf;
+extern cpuop_func op_8130_44_ff;
+extern cpuop_func op_8170_44_nf;
+extern cpuop_func op_8170_44_ff;
+extern cpuop_func op_81b0_44_nf;
+extern cpuop_func op_81b0_44_ff;
+extern cpuop_func op_81f0_44_nf;
+extern cpuop_func op_81f0_44_ff;
+extern cpuop_func op_81fb_44_nf;
+extern cpuop_func op_81fb_44_ff;
+extern cpuop_func op_9030_44_nf;
+extern cpuop_func op_9030_44_ff;
+extern cpuop_func op_903b_44_nf;
+extern cpuop_func op_903b_44_ff;
+extern cpuop_func op_9070_44_nf;
+extern cpuop_func op_9070_44_ff;
+extern cpuop_func op_907b_44_nf;
+extern cpuop_func op_907b_44_ff;
+extern cpuop_func op_90b0_44_nf;
+extern cpuop_func op_90b0_44_ff;
+extern cpuop_func op_90bb_44_nf;
+extern cpuop_func op_90bb_44_ff;
+extern cpuop_func op_90f0_44_nf;
+extern cpuop_func op_90f0_44_ff;
+extern cpuop_func op_90fb_44_nf;
+extern cpuop_func op_90fb_44_ff;
+extern cpuop_func op_9130_44_nf;
+extern cpuop_func op_9130_44_ff;
+extern cpuop_func op_9170_44_nf;
+extern cpuop_func op_9170_44_ff;
+extern cpuop_func op_91b0_44_nf;
+extern cpuop_func op_91b0_44_ff;
+extern cpuop_func op_91f0_44_nf;
+extern cpuop_func op_91f0_44_ff;
+extern cpuop_func op_91fb_44_nf;
+extern cpuop_func op_91fb_44_ff;
+extern cpuop_func op_b030_44_nf;
+extern cpuop_func op_b030_44_ff;
+extern cpuop_func op_b03b_44_nf;
+extern cpuop_func op_b03b_44_ff;
+extern cpuop_func op_b070_44_nf;
+extern cpuop_func op_b070_44_ff;
+extern cpuop_func op_b07b_44_nf;
+extern cpuop_func op_b07b_44_ff;
+extern cpuop_func op_b0b0_44_nf;
+extern cpuop_func op_b0b0_44_ff;
+extern cpuop_func op_b0bb_44_nf;
+extern cpuop_func op_b0bb_44_ff;
+extern cpuop_func op_b0f0_44_nf;
+extern cpuop_func op_b0f0_44_ff;
+extern cpuop_func op_b0fb_44_nf;
+extern cpuop_func op_b0fb_44_ff;
+extern cpuop_func op_b130_44_nf;
+extern cpuop_func op_b130_44_ff;
+extern cpuop_func op_b170_44_nf;
+extern cpuop_func op_b170_44_ff;
+extern cpuop_func op_b1b0_44_nf;
+extern cpuop_func op_b1b0_44_ff;
+extern cpuop_func op_b1f0_44_nf;
+extern cpuop_func op_b1f0_44_ff;
+extern cpuop_func op_b1fb_44_nf;
+extern cpuop_func op_b1fb_44_ff;
+extern cpuop_func op_c030_44_nf;
+extern cpuop_func op_c030_44_ff;
+extern cpuop_func op_c03b_44_nf;
+extern cpuop_func op_c03b_44_ff;
+extern cpuop_func op_c070_44_nf;
+extern cpuop_func op_c070_44_ff;
+extern cpuop_func op_c07b_44_nf;
+extern cpuop_func op_c07b_44_ff;
+extern cpuop_func op_c0b0_44_nf;
+extern cpuop_func op_c0b0_44_ff;
+extern cpuop_func op_c0bb_44_nf;
+extern cpuop_func op_c0bb_44_ff;
+extern cpuop_func op_c0f0_44_nf;
+extern cpuop_func op_c0f0_44_ff;
+extern cpuop_func op_c0fb_44_nf;
+extern cpuop_func op_c0fb_44_ff;
+extern cpuop_func op_c130_44_nf;
+extern cpuop_func op_c130_44_ff;
+extern cpuop_func op_c170_44_nf;
+extern cpuop_func op_c170_44_ff;
+extern cpuop_func op_c1b0_44_nf;
+extern cpuop_func op_c1b0_44_ff;
+extern cpuop_func op_c1f0_44_nf;
+extern cpuop_func op_c1f0_44_ff;
+extern cpuop_func op_c1fb_44_nf;
+extern cpuop_func op_c1fb_44_ff;
+extern cpuop_func op_d030_44_nf;
+extern cpuop_func op_d030_44_ff;
+extern cpuop_func op_d03b_44_nf;
+extern cpuop_func op_d03b_44_ff;
+extern cpuop_func op_d070_44_nf;
+extern cpuop_func op_d070_44_ff;
+extern cpuop_func op_d07b_44_nf;
+extern cpuop_func op_d07b_44_ff;
+extern cpuop_func op_d0b0_44_nf;
+extern cpuop_func op_d0b0_44_ff;
+extern cpuop_func op_d0bb_44_nf;
+extern cpuop_func op_d0bb_44_ff;
+extern cpuop_func op_d0f0_44_nf;
+extern cpuop_func op_d0f0_44_ff;
+extern cpuop_func op_d0fb_44_nf;
+extern cpuop_func op_d0fb_44_ff;
+extern cpuop_func op_d130_44_nf;
+extern cpuop_func op_d130_44_ff;
+extern cpuop_func op_d170_44_nf;
+extern cpuop_func op_d170_44_ff;
+extern cpuop_func op_d1b0_44_nf;
+extern cpuop_func op_d1b0_44_ff;
+extern cpuop_func op_d1f0_44_nf;
+extern cpuop_func op_d1f0_44_ff;
+extern cpuop_func op_d1fb_44_nf;
+extern cpuop_func op_d1fb_44_ff;
+extern cpuop_func op_e0f0_44_nf;
+extern cpuop_func op_e0f0_44_ff;
+extern cpuop_func op_e1f0_44_nf;
+extern cpuop_func op_e1f0_44_ff;
+extern cpuop_func op_e2f0_44_nf;
+extern cpuop_func op_e2f0_44_ff;
+extern cpuop_func op_e3f0_44_nf;
+extern cpuop_func op_e3f0_44_ff;
+extern cpuop_func op_e4f0_44_nf;
+extern cpuop_func op_e4f0_44_ff;
+extern cpuop_func op_e5f0_44_nf;
+extern cpuop_func op_e5f0_44_ff;
+extern cpuop_func op_e6f0_44_nf;
+extern cpuop_func op_e6f0_44_ff;
+extern cpuop_func op_e7f0_44_nf;
+extern cpuop_func op_e7f0_44_ff;
+extern cpuop_func op_40c0_45_nf;
+extern cpuop_func op_40c0_45_ff;
+extern cpuop_func op_40d0_45_nf;
+extern cpuop_func op_40d0_45_ff;
+extern cpuop_func op_40d8_45_nf;
+extern cpuop_func op_40d8_45_ff;
+extern cpuop_func op_40e0_45_nf;
+extern cpuop_func op_40e0_45_ff;
+extern cpuop_func op_40e8_45_nf;
+extern cpuop_func op_40e8_45_ff;
+extern cpuop_func op_40f0_45_nf;
+extern cpuop_func op_40f0_45_ff;
+extern cpuop_func op_40f8_45_nf;
+extern cpuop_func op_40f8_45_ff;
+extern cpuop_func op_40f9_45_nf;
+extern cpuop_func op_40f9_45_ff;
+extern cpuop_func op_4200_45_nf;
+extern cpuop_func op_4200_45_ff;
+extern cpuop_func op_4210_45_nf;
+extern cpuop_func op_4210_45_ff;
+extern cpuop_func op_4218_45_nf;
+extern cpuop_func op_4218_45_ff;
+extern cpuop_func op_4220_45_nf;
+extern cpuop_func op_4220_45_ff;
+extern cpuop_func op_4228_45_nf;
+extern cpuop_func op_4228_45_ff;
+extern cpuop_func op_4230_45_nf;
+extern cpuop_func op_4230_45_ff;
+extern cpuop_func op_4238_45_nf;
+extern cpuop_func op_4238_45_ff;
+extern cpuop_func op_4239_45_nf;
+extern cpuop_func op_4239_45_ff;
+extern cpuop_func op_4240_45_nf;
+extern cpuop_func op_4240_45_ff;
+extern cpuop_func op_4250_45_nf;
+extern cpuop_func op_4250_45_ff;
+extern cpuop_func op_4258_45_nf;
+extern cpuop_func op_4258_45_ff;
+extern cpuop_func op_4260_45_nf;
+extern cpuop_func op_4260_45_ff;
+extern cpuop_func op_4268_45_nf;
+extern cpuop_func op_4268_45_ff;
+extern cpuop_func op_4270_45_nf;
+extern cpuop_func op_4270_45_ff;
+extern cpuop_func op_4278_45_nf;
+extern cpuop_func op_4278_45_ff;
+extern cpuop_func op_4279_45_nf;
+extern cpuop_func op_4279_45_ff;
+extern cpuop_func op_4280_45_nf;
+extern cpuop_func op_4280_45_ff;
+extern cpuop_func op_4290_45_nf;
+extern cpuop_func op_4290_45_ff;
+extern cpuop_func op_4298_45_nf;
+extern cpuop_func op_4298_45_ff;
+extern cpuop_func op_42a0_45_nf;
+extern cpuop_func op_42a0_45_ff;
+extern cpuop_func op_42a8_45_nf;
+extern cpuop_func op_42a8_45_ff;
+extern cpuop_func op_42b0_45_nf;
+extern cpuop_func op_42b0_45_ff;
+extern cpuop_func op_42b8_45_nf;
+extern cpuop_func op_42b8_45_ff;
+extern cpuop_func op_42b9_45_nf;
+extern cpuop_func op_42b9_45_ff;
+extern cpuop_func op_4e73_45_nf;
+extern cpuop_func op_4e73_45_ff;
+extern cpuop_func op_50c0_45_nf;
+extern cpuop_func op_50c0_45_ff;
+extern cpuop_func op_50d0_45_nf;
+extern cpuop_func op_50d0_45_ff;
+extern cpuop_func op_50d8_45_nf;
+extern cpuop_func op_50d8_45_ff;
+extern cpuop_func op_50e0_45_nf;
+extern cpuop_func op_50e0_45_ff;
+extern cpuop_func op_50e8_45_nf;
+extern cpuop_func op_50e8_45_ff;
+extern cpuop_func op_50f0_45_nf;
+extern cpuop_func op_50f0_45_ff;
+extern cpuop_func op_50f8_45_nf;
+extern cpuop_func op_50f8_45_ff;
+extern cpuop_func op_50f9_45_nf;
+extern cpuop_func op_50f9_45_ff;
+extern cpuop_func op_51c0_45_nf;
+extern cpuop_func op_51c0_45_ff;
+extern cpuop_func op_51d0_45_nf;
+extern cpuop_func op_51d0_45_ff;
+extern cpuop_func op_51d8_45_nf;
+extern cpuop_func op_51d8_45_ff;
+extern cpuop_func op_51e0_45_nf;
+extern cpuop_func op_51e0_45_ff;
+extern cpuop_func op_51e8_45_nf;
+extern cpuop_func op_51e8_45_ff;
+extern cpuop_func op_51f0_45_nf;
+extern cpuop_func op_51f0_45_ff;
+extern cpuop_func op_51f8_45_nf;
+extern cpuop_func op_51f8_45_ff;
+extern cpuop_func op_51f9_45_nf;
+extern cpuop_func op_51f9_45_ff;
+extern cpuop_func op_52c0_45_nf;
+extern cpuop_func op_52c0_45_ff;
+extern cpuop_func op_52d0_45_nf;
+extern cpuop_func op_52d0_45_ff;
+extern cpuop_func op_52d8_45_nf;
+extern cpuop_func op_52d8_45_ff;
+extern cpuop_func op_52e0_45_nf;
+extern cpuop_func op_52e0_45_ff;
+extern cpuop_func op_52e8_45_nf;
+extern cpuop_func op_52e8_45_ff;
+extern cpuop_func op_52f0_45_nf;
+extern cpuop_func op_52f0_45_ff;
+extern cpuop_func op_52f8_45_nf;
+extern cpuop_func op_52f8_45_ff;
+extern cpuop_func op_52f9_45_nf;
+extern cpuop_func op_52f9_45_ff;
+extern cpuop_func op_53c0_45_nf;
+extern cpuop_func op_53c0_45_ff;
+extern cpuop_func op_53d0_45_nf;
+extern cpuop_func op_53d0_45_ff;
+extern cpuop_func op_53d8_45_nf;
+extern cpuop_func op_53d8_45_ff;
+extern cpuop_func op_53e0_45_nf;
+extern cpuop_func op_53e0_45_ff;
+extern cpuop_func op_53e8_45_nf;
+extern cpuop_func op_53e8_45_ff;
+extern cpuop_func op_53f0_45_nf;
+extern cpuop_func op_53f0_45_ff;
+extern cpuop_func op_53f8_45_nf;
+extern cpuop_func op_53f8_45_ff;
+extern cpuop_func op_53f9_45_nf;
+extern cpuop_func op_53f9_45_ff;
+extern cpuop_func op_54c0_45_nf;
+extern cpuop_func op_54c0_45_ff;
+extern cpuop_func op_54d0_45_nf;
+extern cpuop_func op_54d0_45_ff;
+extern cpuop_func op_54d8_45_nf;
+extern cpuop_func op_54d8_45_ff;
+extern cpuop_func op_54e0_45_nf;
+extern cpuop_func op_54e0_45_ff;
+extern cpuop_func op_54e8_45_nf;
+extern cpuop_func op_54e8_45_ff;
+extern cpuop_func op_54f0_45_nf;
+extern cpuop_func op_54f0_45_ff;
+extern cpuop_func op_54f8_45_nf;
+extern cpuop_func op_54f8_45_ff;
+extern cpuop_func op_54f9_45_nf;
+extern cpuop_func op_54f9_45_ff;
+extern cpuop_func op_55c0_45_nf;
+extern cpuop_func op_55c0_45_ff;
+extern cpuop_func op_55d0_45_nf;
+extern cpuop_func op_55d0_45_ff;
+extern cpuop_func op_55d8_45_nf;
+extern cpuop_func op_55d8_45_ff;
+extern cpuop_func op_55e0_45_nf;
+extern cpuop_func op_55e0_45_ff;
+extern cpuop_func op_55e8_45_nf;
+extern cpuop_func op_55e8_45_ff;
+extern cpuop_func op_55f0_45_nf;
+extern cpuop_func op_55f0_45_ff;
+extern cpuop_func op_55f8_45_nf;
+extern cpuop_func op_55f8_45_ff;
+extern cpuop_func op_55f9_45_nf;
+extern cpuop_func op_55f9_45_ff;
+extern cpuop_func op_56c0_45_nf;
+extern cpuop_func op_56c0_45_ff;
+extern cpuop_func op_56d0_45_nf;
+extern cpuop_func op_56d0_45_ff;
+extern cpuop_func op_56d8_45_nf;
+extern cpuop_func op_56d8_45_ff;
+extern cpuop_func op_56e0_45_nf;
+extern cpuop_func op_56e0_45_ff;
+extern cpuop_func op_56e8_45_nf;
+extern cpuop_func op_56e8_45_ff;
+extern cpuop_func op_56f0_45_nf;
+extern cpuop_func op_56f0_45_ff;
+extern cpuop_func op_56f8_45_nf;
+extern cpuop_func op_56f8_45_ff;
+extern cpuop_func op_56f9_45_nf;
+extern cpuop_func op_56f9_45_ff;
+extern cpuop_func op_57c0_45_nf;
+extern cpuop_func op_57c0_45_ff;
+extern cpuop_func op_57d0_45_nf;
+extern cpuop_func op_57d0_45_ff;
+extern cpuop_func op_57d8_45_nf;
+extern cpuop_func op_57d8_45_ff;
+extern cpuop_func op_57e0_45_nf;
+extern cpuop_func op_57e0_45_ff;
+extern cpuop_func op_57e8_45_nf;
+extern cpuop_func op_57e8_45_ff;
+extern cpuop_func op_57f0_45_nf;
+extern cpuop_func op_57f0_45_ff;
+extern cpuop_func op_57f8_45_nf;
+extern cpuop_func op_57f8_45_ff;
+extern cpuop_func op_57f9_45_nf;
+extern cpuop_func op_57f9_45_ff;
+extern cpuop_func op_58c0_45_nf;
+extern cpuop_func op_58c0_45_ff;
+extern cpuop_func op_58d0_45_nf;
+extern cpuop_func op_58d0_45_ff;
+extern cpuop_func op_58d8_45_nf;
+extern cpuop_func op_58d8_45_ff;
+extern cpuop_func op_58e0_45_nf;
+extern cpuop_func op_58e0_45_ff;
+extern cpuop_func op_58e8_45_nf;
+extern cpuop_func op_58e8_45_ff;
+extern cpuop_func op_58f0_45_nf;
+extern cpuop_func op_58f0_45_ff;
+extern cpuop_func op_58f8_45_nf;
+extern cpuop_func op_58f8_45_ff;
+extern cpuop_func op_58f9_45_nf;
+extern cpuop_func op_58f9_45_ff;
+extern cpuop_func op_59c0_45_nf;
+extern cpuop_func op_59c0_45_ff;
+extern cpuop_func op_59d0_45_nf;
+extern cpuop_func op_59d0_45_ff;
+extern cpuop_func op_59d8_45_nf;
+extern cpuop_func op_59d8_45_ff;
+extern cpuop_func op_59e0_45_nf;
+extern cpuop_func op_59e0_45_ff;
+extern cpuop_func op_59e8_45_nf;
+extern cpuop_func op_59e8_45_ff;
+extern cpuop_func op_59f0_45_nf;
+extern cpuop_func op_59f0_45_ff;
+extern cpuop_func op_59f8_45_nf;
+extern cpuop_func op_59f8_45_ff;
+extern cpuop_func op_59f9_45_nf;
+extern cpuop_func op_59f9_45_ff;
+extern cpuop_func op_5ac0_45_nf;
+extern cpuop_func op_5ac0_45_ff;
+extern cpuop_func op_5ad0_45_nf;
+extern cpuop_func op_5ad0_45_ff;
+extern cpuop_func op_5ad8_45_nf;
+extern cpuop_func op_5ad8_45_ff;
+extern cpuop_func op_5ae0_45_nf;
+extern cpuop_func op_5ae0_45_ff;
+extern cpuop_func op_5ae8_45_nf;
+extern cpuop_func op_5ae8_45_ff;
+extern cpuop_func op_5af0_45_nf;
+extern cpuop_func op_5af0_45_ff;
+extern cpuop_func op_5af8_45_nf;
+extern cpuop_func op_5af8_45_ff;
+extern cpuop_func op_5af9_45_nf;
+extern cpuop_func op_5af9_45_ff;
+extern cpuop_func op_5bc0_45_nf;
+extern cpuop_func op_5bc0_45_ff;
+extern cpuop_func op_5bd0_45_nf;
+extern cpuop_func op_5bd0_45_ff;
+extern cpuop_func op_5bd8_45_nf;
+extern cpuop_func op_5bd8_45_ff;
+extern cpuop_func op_5be0_45_nf;
+extern cpuop_func op_5be0_45_ff;
+extern cpuop_func op_5be8_45_nf;
+extern cpuop_func op_5be8_45_ff;
+extern cpuop_func op_5bf0_45_nf;
+extern cpuop_func op_5bf0_45_ff;
+extern cpuop_func op_5bf8_45_nf;
+extern cpuop_func op_5bf8_45_ff;
+extern cpuop_func op_5bf9_45_nf;
+extern cpuop_func op_5bf9_45_ff;
+extern cpuop_func op_5cc0_45_nf;
+extern cpuop_func op_5cc0_45_ff;
+extern cpuop_func op_5cd0_45_nf;
+extern cpuop_func op_5cd0_45_ff;
+extern cpuop_func op_5cd8_45_nf;
+extern cpuop_func op_5cd8_45_ff;
+extern cpuop_func op_5ce0_45_nf;
+extern cpuop_func op_5ce0_45_ff;
+extern cpuop_func op_5ce8_45_nf;
+extern cpuop_func op_5ce8_45_ff;
+extern cpuop_func op_5cf0_45_nf;
+extern cpuop_func op_5cf0_45_ff;
+extern cpuop_func op_5cf8_45_nf;
+extern cpuop_func op_5cf8_45_ff;
+extern cpuop_func op_5cf9_45_nf;
+extern cpuop_func op_5cf9_45_ff;
+extern cpuop_func op_5dc0_45_nf;
+extern cpuop_func op_5dc0_45_ff;
+extern cpuop_func op_5dd0_45_nf;
+extern cpuop_func op_5dd0_45_ff;
+extern cpuop_func op_5dd8_45_nf;
+extern cpuop_func op_5dd8_45_ff;
+extern cpuop_func op_5de0_45_nf;
+extern cpuop_func op_5de0_45_ff;
+extern cpuop_func op_5de8_45_nf;
+extern cpuop_func op_5de8_45_ff;
+extern cpuop_func op_5df0_45_nf;
+extern cpuop_func op_5df0_45_ff;
+extern cpuop_func op_5df8_45_nf;
+extern cpuop_func op_5df8_45_ff;
+extern cpuop_func op_5df9_45_nf;
+extern cpuop_func op_5df9_45_ff;
+extern cpuop_func op_5ec0_45_nf;
+extern cpuop_func op_5ec0_45_ff;
+extern cpuop_func op_5ed0_45_nf;
+extern cpuop_func op_5ed0_45_ff;
+extern cpuop_func op_5ed8_45_nf;
+extern cpuop_func op_5ed8_45_ff;
+extern cpuop_func op_5ee0_45_nf;
+extern cpuop_func op_5ee0_45_ff;
+extern cpuop_func op_5ee8_45_nf;
+extern cpuop_func op_5ee8_45_ff;
+extern cpuop_func op_5ef0_45_nf;
+extern cpuop_func op_5ef0_45_ff;
+extern cpuop_func op_5ef8_45_nf;
+extern cpuop_func op_5ef8_45_ff;
+extern cpuop_func op_5ef9_45_nf;
+extern cpuop_func op_5ef9_45_ff;
+extern cpuop_func op_5fc0_45_nf;
+extern cpuop_func op_5fc0_45_ff;
+extern cpuop_func op_5fd0_45_nf;
+extern cpuop_func op_5fd0_45_ff;
+extern cpuop_func op_5fd8_45_nf;
+extern cpuop_func op_5fd8_45_ff;
+extern cpuop_func op_5fe0_45_nf;
+extern cpuop_func op_5fe0_45_ff;
+extern cpuop_func op_5fe8_45_nf;
+extern cpuop_func op_5fe8_45_ff;
+extern cpuop_func op_5ff0_45_nf;
+extern cpuop_func op_5ff0_45_ff;
+extern cpuop_func op_5ff8_45_nf;
+extern cpuop_func op_5ff8_45_ff;
+extern cpuop_func op_5ff9_45_nf;
+extern cpuop_func op_5ff9_45_ff;
diff --git a/src/cpu/custom.c b/src/cpu/custom.c
new file mode 100644
index 0000000..85be3f6
--- /dev/null
+++ b/src/cpu/custom.c
@@ -0,0 +1,542 @@
+/*
+* UAE - The Un*x Amiga Emulator
+*
+* Custom chip emulation
+*
+* Copyright 1995-2002 Bernd Schmidt
+* Copyright 1995 Alessandro Bissacco
+* Copyright 2000-2014 Toni Wilen
+*/
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+#include "compat.h"
+#include "hatari-glue.h"
+#include "options_cpu.h"
+#include "events.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "main.h"
+#include "cpummu.h"
+#include "m68000.h"
+#include "debugui.h"
+#include "debugcpu.h"
+#ifdef WINUAE_FOR_HATARI
+#include "debug.h"
+#endif
+
+#define WRITE_LOG_BUF_SIZE 4096
+
+/* TODO: move custom.c stuff declarations to custom.h? */
+
+#ifdef WINUAE_FOR_HATARI
+/* declared in newcpu.c */
+extern struct regstruct mmu_backup_regs;
+/* declared in events.h */
+unsigned long currcycle;
+/* declared in savestate.h */
+int savestate_state = 0;
+#endif
+
+
+uae_u16 dmacon;
+
+static int extra_cycle;
+
+#if 0
+typedef struct _LARGE_INTEGER
+{
+     union
+     {
+          struct
+          {
+               unsigned long LowPart;
+               long HighPart;
+          };
+          int64_t QuadPart;
+     };
+} LARGE_INTEGER, *PLARGE_INTEGER;
+#endif
+
+
+#ifdef CPUEMU_13
+
+uae_u8 cycle_line[256 + 1];
+
+static void sync_ce020 (void)
+{
+	unsigned long c;
+	int extra;
+
+	c = get_cycles ();
+	extra = c & (CYCLE_UNIT - 1);
+	if (extra) {
+		extra = CYCLE_UNIT - extra;
+		do_cycles (extra);
+	}
+}
+
+#ifndef WINUAE_FOR_HATARI
+#define SETIFCHIP \
+	if (addr < 0xd80000) \
+		last_custom_value1 = v;
+#endif		/* WINUAE_FOR_HATARI */
+
+uae_u32 wait_cpu_cycle_read (uaecptr addr, int mode)
+{
+	uae_u32 v = 0;
+#ifndef WINUAE_FOR_HATARI
+	int hpos;
+
+	hpos = dma_cycle ();
+	x_do_cycles_pre (CYCLE_UNIT);
+
+#ifdef DEBUGGER
+	struct dma_rec *dr = NULL;
+	if (debug_dma) {
+		int reg = 0x1000;
+		if (mode < 0)
+			reg |= 4;
+		else if (mode > 0)
+			reg |= 2;
+		else
+			reg |= 1;
+		dr = record_dma (reg, v, addr, hpos, vpos, DMARECORD_CPU);
+		checknasty (hpos, vpos);
+	}
+#endif
+	if (mode < 0)
+		v = get_long (addr);
+	else if (mode > 0)
+		v = get_word (addr);
+	else if (mode == 0)
+		v = get_byte (addr);
+
+#ifdef DEBUGGER
+	if (debug_dma)
+		dr->dat = v;
+#endif
+
+	x_do_cycles_post (CYCLE_UNIT, v);
+
+	regs.chipset_latch_rw = regs.chipset_latch_read = v;
+	SETIFCHIP
+
+#else						/* WINUAE_FOR_HATARI */
+	x_do_cycles_pre (CYCLE_UNIT);
+
+	if (mode < 0)
+		v = get_long (addr);
+	else if (mode > 0)
+		v = get_word (addr);
+	else if (mode == 0)
+		v = get_byte (addr);
+
+	x_do_cycles_post (CYCLE_UNIT, v);
+#endif						/* WINUAE_FOR_HATARI */
+
+	return v;
+}
+
+uae_u32 wait_cpu_cycle_read_ce020 (uaecptr addr, int mode)
+{
+	uae_u32 v = 0;
+#ifndef WINUAE_FOR_HATARI
+	int hpos;
+
+	sync_ce020 ();
+	hpos = dma_cycle ();
+	x_do_cycles_pre (CYCLE_UNIT);
+
+#ifdef DEBUGGER
+	struct dma_rec *dr = NULL;
+	if (debug_dma) {
+		int reg = 0x1000;
+		if (mode < 0)
+			reg |= 4;
+		else if (mode > 0)
+			reg |= 2;
+		else
+			reg |= 1;
+		dr = record_dma (reg, v, addr, hpos, vpos, DMARECORD_CPU);
+		checknasty (hpos, vpos);
+	}
+#endif
+	if (mode < 0)
+		v = get_long (addr);
+	else if (mode > 0)
+		v = get_word (addr);
+	else if (mode == 0)
+		v = get_byte (addr);
+
+#ifdef DEBUGGER
+	if (debug_dma)
+		dr->dat = v;
+#endif
+	if (currprefs.cpu_model == 68020)
+		x_do_cycles_post (CYCLE_UNIT / 2, v);
+
+	regs.chipset_latch_rw = regs.chipset_latch_read = v;
+	SETIFCHIP
+
+#else						/* WINUAE_FOR_HATARI */
+	sync_ce020 ();
+	x_do_cycles_pre (CYCLE_UNIT);
+
+	if (mode < 0)
+		v = get_long (addr);
+	else if (mode > 0)
+		v = get_word (addr);
+	else if (mode == 0)
+		v = get_byte (addr);
+
+	if (currprefs.cpu_model == 68020)
+		x_do_cycles_post (CYCLE_UNIT / 2, v);
+#endif						/* WINUAE_FOR_HATARI */
+
+	return v;
+}
+
+void wait_cpu_cycle_write (uaecptr addr, int mode, uae_u32 v)
+{
+#ifndef WINUAE_FOR_HATARI
+	int hpos;
+
+	hpos = dma_cycle ();
+	x_do_cycles_pre (CYCLE_UNIT);
+
+#ifdef DEBUGGER
+	if (debug_dma) {
+		int reg = 0x1100;
+		if (mode < 0)
+			reg |= 4;
+		else if (mode > 0)
+			reg |= 2;
+		else
+			reg |= 1;
+		record_dma (reg, v, addr, hpos, vpos, DMARECORD_CPU);
+		checknasty (hpos, vpos);
+	}
+#endif
+
+	if (mode < 0)
+		put_long (addr, v);
+	else if (mode > 0)
+		put_word (addr, v);
+	else if (mode == 0)
+		put_byte (addr, v);
+
+	x_do_cycles_post (CYCLE_UNIT, v);
+
+	regs.chipset_latch_rw = regs.chipset_latch_write = v;
+	SETIFCHIP
+
+#else						/* WINUAE_FOR_HATARI */
+	x_do_cycles_pre (CYCLE_UNIT);
+
+	if (mode < 0)
+		put_long (addr, v);
+	else if (mode > 0)
+		put_word (addr, v);
+	else if (mode == 0)
+		put_byte (addr, v);
+
+	x_do_cycles_post (CYCLE_UNIT, v);
+#endif						/* WINUAE_FOR_HATARI */
+}
+
+void wait_cpu_cycle_write_ce020 (uaecptr addr, int mode, uae_u32 v)
+{
+#ifndef WINUAE_FOR_HATARI
+	int hpos;
+
+	sync_ce020 ();
+	hpos = dma_cycle ();
+	x_do_cycles_pre (CYCLE_UNIT);
+
+#ifdef DEBUGGER
+	if (debug_dma) {
+		int reg = 0x1100;
+		if (mode < 0)
+			reg |= 4;
+		else if (mode > 0)
+			reg |= 2;
+		else
+			reg |= 1;
+		record_dma (reg, v, addr, hpos, vpos, DMARECORD_CPU);
+		checknasty (hpos, vpos);
+	}
+#endif
+
+	if (mode < 0)
+		put_long (addr, v);
+	else if (mode > 0)
+		put_word (addr, v);
+	else if (mode == 0)
+		put_byte (addr, v);
+
+	if (currprefs.cpu_model == 68020)
+		x_do_cycles_post (CYCLE_UNIT / 2, v);
+
+	regs.chipset_latch_rw = regs.chipset_latch_write = v;
+	SETIFCHIP
+
+#else						/* WINUAE_FOR_HATARI */
+	sync_ce020 ();
+	x_do_cycles_pre (CYCLE_UNIT);
+
+	if (mode < 0)
+		put_long (addr, v);
+	else if (mode > 0)
+		put_word (addr, v);
+	else if (mode == 0)
+		put_byte (addr, v);
+
+	if (currprefs.cpu_model == 68020)
+		x_do_cycles_post (CYCLE_UNIT / 2, v);
+#endif						/* WINUAE_FOR_HATARI */
+}
+
+void do_cycles_ce (unsigned long cycles)
+{
+	cycles += extra_cycle;
+	while (cycles >= CYCLE_UNIT) {
+#ifndef WINUAE_FOR_HATARI
+		int hpos = current_hpos () + 1;
+		decide_line (hpos);
+		sync_copper (hpos);
+		decide_fetch_ce (hpos);
+		if (bltstate != BLT_done)
+			decide_blitter (hpos);
+#endif						/* WINUAE_FOR_HATARI */
+		do_cycles (1 * CYCLE_UNIT);
+		cycles -= CYCLE_UNIT;
+	}
+	extra_cycle = cycles;
+}
+
+
+#ifndef WINUAE_FOR_HATARI
+void do_cycles_ce020 (unsigned long cycles)
+#else
+/* [NP] : confusing, because same function name as in cpu_prefetch.h with do_cycles_ce020( int ), */
+/* but here unsigned long parameter is already multiplied by cpucycleunit. */
+/* Requires C++, so we rename to do_cycles_ce020_long() to keep C compatibility */
+void do_cycles_ce020_long (unsigned long cycles)
+#endif
+{
+	unsigned long c;
+#ifndef WINUAE_FOR_HATARI
+	int extra;
+#else
+	unsigned long extra;			/* remove warning "comparison between signed/unsigned" */
+#endif
+
+	if (!cycles)
+		return;
+	c = get_cycles ();
+	extra = c & (CYCLE_UNIT - 1);
+//fprintf ( stderr , "do_cycles_ce020_long %d %d %d\n" , cycles , c , extra );
+	if (extra) {
+		extra = CYCLE_UNIT - extra;
+		if (extra >= cycles) {
+			do_cycles (cycles);
+			return;
+		}
+		do_cycles (extra);
+		cycles -= extra;
+	}
+	c = cycles;
+	while (c) {
+#ifndef WINUAE_FOR_HATARI
+		int hpos = current_hpos () + 1;
+		decide_line (hpos);
+		sync_copper (hpos);
+		decide_fetch_ce (hpos);
+		if (bltstate != BLT_done)
+			decide_blitter (hpos);
+#endif						/* WINUAE_FOR_HATARI */
+		if (c < CYCLE_UNIT)
+			break;
+		do_cycles (1 * CYCLE_UNIT);
+		c -= CYCLE_UNIT;
+	}
+	if (c > 0)
+		do_cycles (c);
+}
+
+int is_cycle_ce (void)
+{
+#ifndef WINUAE_FOR_HATARI
+	int hpos = current_hpos ();
+	return cycle_line[hpos] & CYCLE_MASK;
+
+#else						/* WINUAE_FOR_HATARI */
+	return 0;
+#endif						/* WINUAE_FOR_HATARI */
+}
+
+#endif
+
+
+
+void reset_frame_rate_hack (void)
+{
+#ifndef WINUAE_FOR_HATARI
+        jitcount = 0;
+        if (currprefs.m68k_speed >= 0)
+                return;
+
+        rpt_did_reset = 1;
+        is_syncline = 0;
+        vsyncmintime = read_processor_time () + vsynctimebase;
+        write_log (_T("Resetting frame rate hack\n"));
+#endif						/* WINUAE_FOR_HATARI */
+}
+
+/* Code taken from main.cpp */
+void fixup_cpu (struct uae_prefs *p)
+{
+	if (p->cpu_frequency == 1000000)
+		p->cpu_frequency = 0;
+
+#ifndef WINUAE_FOR_HATARI
+	if (p->cpu_model >= 68030 && p->address_space_24) {
+		error_log (_T("24-bit address space is not supported in 68030/040/060 configurations."));
+		p->address_space_24 = 0;
+	}
+#else
+        /* Hatari : don't force address_space_24=0 for 68030, as the Falcon has a 68030 EC with only 24 bits */
+#endif
+	if (p->cpu_model < 68020 && p->fpu_model && (p->cpu_compatible || p->cpu_cycle_exact)) {
+		error_log (_T("FPU is not supported in 68000/010 configurations."));
+		p->fpu_model = 0;
+	}
+
+	switch (p->cpu_model)
+	{
+	case 68000:
+		p->address_space_24 = 1;
+		break;
+	case 68010:
+		p->address_space_24 = 1;
+		break;
+	case 68020:
+		break;
+	case 68030:
+		break;
+	case 68040:
+		if (p->fpu_model)
+			p->fpu_model = 68040;
+		break;
+	case 68060:
+		if (p->fpu_model)
+			p->fpu_model = 68060;
+		break;
+	}
+
+	if (p->cpu_model < 68020 && p->cachesize) {
+		p->cachesize = 0;
+		error_log (_T("JIT requires 68020 or better CPU."));
+	}
+
+	if (p->cpu_model >= 68040 && p->cachesize && p->cpu_compatible)
+		p->cpu_compatible = false;
+
+	if (p->cpu_model >= 68040 && p->cpu_cycle_exact) {
+		p->cpu_cycle_exact = 0;
+		error_log (_T("68040/060 cycle-exact is not supported."));
+	}
+
+	if ((p->cpu_model < 68030 || p->cachesize) && p->mmu_model) {
+		error_log (_T("MMU emulation requires 68030/040/060 and it is not JIT compatible."));
+		p->mmu_model = 0;
+	}
+
+	if (p->cachesize && p->cpu_cycle_exact) {
+		error_log (_T("JIT and cycle-exact can't be enabled simultaneously."));
+		p->cachesize = 0;
+	}
+	if (p->cachesize && (p->fpu_no_unimplemented || p->int_no_unimplemented)) {
+		error_log (_T("JIT is not compatible with unimplemented CPU/FPU instruction emulation."));
+		p->fpu_no_unimplemented = p->int_no_unimplemented = false;
+	}
+
+#ifndef WINUAE_FOR_HATARI
+	/* [NP] In Hatari, don't change m68k_speed in CE mode */
+	if (p->cpu_cycle_exact && p->m68k_speed < 0)
+		p->m68k_speed = 0;
+#endif
+
+#ifndef WINUAE_FOR_HATARI
+	if (p->immediate_blits && p->blitter_cycle_exact) {
+		error_log (_T("Cycle-exact and immediate blitter can't be enabled simultaneously.\n"));
+		p->immediate_blits = false;
+	}
+	if (p->immediate_blits && p->waiting_blits) {
+		error_log (_T("Immediate blitter and waiting blits can't be enabled simultaneously.\n"));
+		p->waiting_blits = 0;
+	}
+#endif
+	if (p->cpu_cycle_exact)
+		p->cpu_compatible = true;
+}
+
+
+void custom_reset (bool hardreset, bool keyboardreset)
+{
+}
+
+
+// TODO NP remove ?
+#ifndef WINUAE_FOR_HATARI
+/* Code taken from main.cpp*/
+void uae_reset (int hardreset)
+{
+	currprefs.quitstatefile[0] = changed_prefs.quitstatefile[0] = 0;
+
+	if (quit_program == 0) {
+		quit_program = -2;
+		if (hardreset)
+			quit_program = -3;
+	}
+
+}
+#endif
+
+
+/* Code taken from win32.cpp*/
+void fpux_restore (int *v)
+{
+/*#ifndef _WIN64
+	if (v)
+		_controlfp (*v, _MCW_IC | _MCW_RC | _MCW_PC);
+	else
+		_controlfp (fpucontrol, _MCW_IC | _MCW_RC | _MCW_PC);
+#endif
+*/
+}
+
+// TODO NP remove ?
+/* Code taken from win32.cpp*/
+void sleep_millis (int ms)
+{
+/* Laurent : may be coded later (DSL-Delay ?) */
+}
+
+
+/* Code just here to let newcpu.c link (original function is in inprec.cpp) */
+int inprec_open(char *fname, int record)
+{
+	return 0;
+}
+
+// TODO NP remove ?
+#ifndef WINUAE_FOR_HATARI
+int current_hpos (void)
+{
+    return (get_cycles () - eventtab[ev_hsync].oldcycles) / CYCLE_UNIT;
+}
+#endif
+
+
diff --git a/src/cpu/custom.h b/src/cpu/custom.h
new file mode 100644
index 0000000..7531a7c
--- /dev/null
+++ b/src/cpu/custom.h
@@ -0,0 +1,181 @@
+ /*
+  * UAE - The Un*x Amiga Emulator
+  *
+  * custom chip support
+  *
+  * (c) 1995 Bernd Schmidt
+  */
+
+#ifndef WINUAE_CUSTOM_H
+#define WINUAE_CUSTOM_H
+
+/* These are the masks that are ORed together in the chipset_mask option.
+ * If CSMASK_AGA is set, the ECS bits are guaranteed to be set as well.  */
+#define CSMASK_ECS_AGNUS 1
+#define CSMASK_ECS_DENISE 2
+#define CSMASK_AGA 4
+#define CSMASK_MASK (CSMASK_ECS_AGNUS | CSMASK_ECS_DENISE | CSMASK_AGA)
+
+uae_u32 get_copper_address (int copno);
+
+extern int custom_init (void);
+extern void custom_reset (bool hardreset, bool keyboardreset);
+extern int intlev (void);
+extern void dumpcustom (void);
+extern void uae_reset (int hardreset);
+
+extern void do_disk (void);
+extern void do_copper (void);
+
+extern void notice_new_xcolors (void);
+extern void notice_screen_contents_lost (void);
+extern void init_row_map (void);
+extern void init_hz_normal (void);
+extern void init_custom (void);
+
+extern bool picasso_requested_on;
+extern bool picasso_on;
+extern void set_picasso_hack_rate (int hz);
+
+/* Set to 1 to leave out the current frame in average frame time calculation.
+ * Useful if the debugger was active.  */
+extern int bogusframe;
+extern unsigned long int hsync_counter;
+
+extern uae_u16 dmacon;
+extern uae_u16 intena, intreq, intreqr;
+
+extern int current_hpos (void);
+extern int vpos;
+
+extern int find_copper_record (uaecptr, int *, int *);
+
+extern int n_frames;
+
+STATIC_INLINE int dmaen (unsigned int dmamask)
+{
+    return (dmamask & dmacon) && (dmacon & 0x200);
+}
+
+
+#define SPCFLAG_STOP 2
+#define SPCFLAG_COPPER 4
+#define SPCFLAG_INT 8
+//#define SPCFLAG_BRK 16
+//#define SPCFLAG_EXTRA_CYCLES 32
+//#define SPCFLAG_TRACE 64
+//#define SPCFLAG_DOTRACE 128
+//#define SPCFLAG_DOINT 256 /* arg, JIT fails without this.. */
+#define SPCFLAG_BLTNASTY 512
+//#define SPCFLAG_EXEC 1024
+#define SPCFLAG_ACTION_REPLAY 2048
+#define SPCFLAG_TRAP 4096 /* enforcer-hack */
+//#define SPCFLAG_MODE_CHANGE 8192
+#ifdef JIT
+#define SPCFLAG_END_COMPILE 16384
+#endif
+#define SPCFLAG_CHECK 32768
+
+extern uae_u16 adkcon;
+
+extern unsigned int joy0dir, joy1dir;
+extern int joy0button, joy1button;
+
+extern void INTREQ (uae_u16);
+extern void INTREQ_0 (uae_u16);
+extern void INTREQ_f (uae_u16);
+extern void send_interrupt (int num, int delay);
+extern uae_u16 INTREQR (void);
+
+
+#define DMA_AUD0      0x0001
+#define DMA_AUD1      0x0002
+#define DMA_AUD2      0x0004
+#define DMA_AUD3      0x0008
+#define DMA_DISK      0x0010
+#define DMA_SPRITE    0x0020
+#define DMA_BLITTER   0x0040
+#define DMA_COPPER    0x0080
+#define DMA_BITPLANE  0x0100
+#define DMA_MASTER    0x0200
+#define DMA_BLITPRI   0x0400
+
+#define CYCLE_REFRESH	0x01
+#define CYCLE_STROBE	0x02
+#define CYCLE_MISC	0x04
+#define CYCLE_SPRITE	0x08
+#define CYCLE_COPPER	0x10
+#define CYCLE_BLITTER	0x20
+#define CYCLE_CPU	0x40
+#define CYCLE_CPUNASTY	0x80
+
+#ifdef AGA
+/* AGA mode color lookup tables */
+extern unsigned int xredcolors[256], xgreencolors[256], xbluecolors[256];
+#endif
+extern int xredcolor_s, xredcolor_b, xredcolor_m;
+extern int xgreencolor_s, xgreencolor_b, xgreencolor_m;
+extern int xbluecolor_s, xbluecolor_b, xbluecolor_m;
+
+#define RES_LORES 0
+#define RES_HIRES 1
+#define RES_SUPERHIRES 2
+#define RES_MAX 2
+#define VRES_NONDOUBLE 0
+#define VRES_DOUBLE 1
+#define VRES_MAX 1
+
+/* calculate shift depending on resolution (replaced "decided_hires ? 4 : 8") */
+#define RES_SHIFT(res) ((res) == RES_LORES ? 8 : (res) == RES_HIRES ? 4 : 2)
+
+/* get resolution from bplcon0 */
+#if AMIGA_ONLY
+STATIC_INLINE int GET_RES_DENISE (uae_u16 con0)
+{
+    if (!(currprefs.chipset_mask & CSMASK_ECS_DENISE))
+	con0 &= ~0x40;
+    return ((con0) & 0x8000) ? RES_HIRES : ((con0) & 0x40) ? RES_SUPERHIRES : RES_LORES;
+}
+STATIC_INLINE int GET_RES_AGNUS (uae_u16 con0)
+{
+    if (!(currprefs.chipset_mask & CSMASK_ECS_AGNUS))
+	con0 &= ~0x40;
+    return ((con0) & 0x8000) ? RES_HIRES : ((con0) & 0x40) ? RES_SUPERHIRES : RES_LORES;
+}
+#endif // AMIGA_ONLY
+
+/* get sprite width from FMODE */
+#define GET_SPRITEWIDTH(FMODE) ((((FMODE) >> 2) & 3) == 3 ? 64 : (((FMODE) >> 2) & 3) == 0 ? 16 : 32)
+/* Compute the number of bitplanes from a value written to BPLCON0  */
+STATIC_INLINE int GET_PLANES(uae_u16 bplcon0)
+{
+    if ((bplcon0 & 0x0010) && (bplcon0 & 0x7000))
+	return 0;
+    if (bplcon0 & 0x0010)
+	return 8;
+    return (bplcon0 >> 12) & 7;
+}
+
+extern void fpscounter_reset (void);
+extern unsigned long idletime;
+extern int lightpen_x, lightpen_y, lightpen_cx, lightpen_cy;
+
+struct customhack {
+    uae_u16 v;
+    int vpos, hpos;
+};
+void customhack_put (struct customhack *ch, uae_u16 v, int hpos);
+uae_u16 customhack_get (struct customhack *ch, int hpos);
+extern void alloc_cycle_ext (int, int);
+extern bool ispal (void);
+extern int inprec_open(char *fname, int record);
+extern void sleep_millis (int ms);
+
+/* referred by prefetch.h */
+extern uae_u32 wait_cpu_cycle_read (uaecptr addr, int mode);
+extern void wait_cpu_cycle_write (uaecptr addr, int mode, uae_u32 v);
+extern uae_u32 wait_cpu_cycle_read_ce020 (uaecptr addr, int mode);
+extern void wait_cpu_cycle_write_ce020 (uaecptr addr, int mode, uae_u32 v);
+
+#endif /* WINUAE_CUSTOM_H */
+
diff --git a/src/cpu/debug.c b/src/cpu/debug.c
new file mode 100644
index 0000000..1ed2abe
--- /dev/null
+++ b/src/cpu/debug.c
@@ -0,0 +1,5291 @@
+/*
+* UAE - The Un*x Amiga Emulator
+*
+* Debugger
+*
+* (c) 1995 Bernd Schmidt
+* (c) 2006 Toni Wilen
+*
+*/
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+
+#include "main.h"
+#include "hatari-glue.h"
+
+#include 
+#include 
+
+#include "options_cpu.h"
+//#include "uae.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "debug.h"
+//#include "cia.h"
+//#include "xwin.h"
+//#include "identify.h"
+//#include "audio.h"
+//#include "sound.h"
+//#include "disk.h"
+#include "savestate.h"
+//#include "autoconf.h"
+//#include "akiko.h"
+//#include "inputdevice.h"
+//#include "crc32.h"
+//#include "rommgr.h"
+//#include "inputrecord.h"
+#include "cpummu.h"
+#include "cpummu030.h"
+//#include "ppc/ppcd.h"
+//#include "uae/ppc.h"
+
+#ifdef WINUAE_FOR_HATARI
+#include "stMemory.h"
+static int debug_mmu_mode;
+
+#else
+int debugger_active;
+static uaecptr skipaddr_start, skipaddr_end;
+static int skipaddr_doskip;
+static uae_u32 skipins;
+static int do_skip;
+static int debug_rewind;
+static int memwatch_triggered;
+int memwatch_enabled;
+static uae_u16 sr_bpmask, sr_bpvalue;
+int debugging;
+int exception_debugging;
+int no_trace_exceptions;
+int debug_copper = 0;
+int debug_dma = 0;
+int debug_sprite_mask = 0xff;
+int debug_illegal = 0;
+uae_u64 debug_illegal_mask;
+static int debug_mmu_mode;
+static bool break_if_enforcer;
+
+static uaecptr processptr;
+static uae_char *processname;
+
+static uaecptr debug_copper_pc;
+
+extern int audio_channel_mask;
+extern int inputdevice_logging;
+
+void deactivate_debugger (void)
+{
+	debugger_active = 0;
+	debugging = 0;
+	exception_debugging = 0;
+	processptr = 0;
+	xfree (processname);
+	processname = NULL;
+}
+
+void activate_debugger (void)
+{
+	do_skip = 0;
+	if (debugger_active)
+		return;
+	debugger_active = 1;
+	set_special (SPCFLAG_BRK);
+	debugging = 1;
+	mmu_triggered = 0;
+}
+
+bool debug_enforcer(void)
+{
+	if (!break_if_enforcer)
+		return false;
+	activate_debugger();
+	return true;
+}
+
+int firsthist = 0;
+int lasthist = 0;
+static struct regstruct history[MAX_HIST];
+
+static TCHAR help[] = {
+	_T("          HELP for UAE Debugger\n")
+	_T("         -----------------------\n\n")
+	_T("  g [
]         Start execution at the current address or 
.\n")
+	_T("  c                     Dump state of the CIA, disk drives and custom registers.\n")
+	_T("  r                     Dump state of the CPU.\n")
+	_T("  r         Modify CPU registers (Dx,Ax,USP,ISP,VBR,...).\n")
+	_T("  m 
 [] Memory dump starting at 
.\n")
+	_T("  d 
 [] Disassembly starting at 
.\n")
+	_T("  t [instructions]      Step one or more instructions.\n")
+	_T("  z                     Step through one instruction - useful for JSR, DBRA etc.\n")
+	_T("  f                     Step forward until PC in RAM (\"boot block finder\").\n")
+	_T("  f 
           Add/remove breakpoint.\n")
+	_T("  fa 
 [] []\n")
+	_T("                        Find effective address 
.\n")
+	_T("  fi                    Step forward until PC points to RTS, RTD or RTE.\n")
+	_T("  fi            Step forward until PC points to .\n")
+	_T("  fp \"\"/    Step forward until process  or  is active.\n")
+	_T("  fl                    List breakpoints.\n")
+	_T("  fd                    Remove all breakpoints.\n")
+	_T("  fs  |   Wait n scanlines/position.\n")
+	_T("  fc      Wait n color clocks.\n")
+	_T("  fS         Break when (SR & mask) = val.\n")                   
+	_T("  f       Step forward until  <= PC <= .\n")
+	_T("  e                     Dump contents of all custom registers, ea = AGA colors.\n")
+	_T("  i []            Dump contents of interrupt and trap vectors.\n")
+	_T("  il []           Exception breakpoint.\n")
+	_T("  o <0-2|addr> []View memory as Copper instructions.\n")
+	_T("  od                    Enable/disable Copper vpos/hpos tracing.\n")
+	_T("  ot                    Copper single step trace.\n")
+	_T("  ob              Copper breakpoint.\n")
+	_T("  H[H]             Show PC history (HH=full CPU info)  instructions.\n")
+	_T("  C              Search for values like energy or lifes in games.\n")
+	_T("  Cl                    List currently found trainer addresses.\n")
+	_T("  D[idxzs <[max diff]>] Deep trainer. i=new value must be larger, d=smaller,\n")
+	_T("                        x = must be same, z = must be different, s = restart.\n")
+	_T("  W 
  Write into Amiga memory.\n")
+	_T("  W 
 'string' Write into Amiga memory.\n")
+	_T("  w  
   [[.x]] (read/write/opcode/freeze/mustchange).\n")
+	_T("                        Add/remove memory watchpoints.\n")
+	_T("  wd [<0-1>]            Enable illegal access logger. 1 = enable break.\n")
+	_T("  S      Save a block of Amiga memory.\n")
+	_T("  s \"\"/ [] []\n")
+	_T("                        Search for string/bytes.\n")
+	_T("  T or Tt               Show exec tasks and their PCs.\n")
+	_T("  Td,Tl,Tr,Tp,Ts,TS,Ti,TO,TM Show devs, libs, resources, ports, semaphores,\n")
+	_T("                        residents, interrupts, doslist and memorylist.\n")
+	_T("  b                     Step to previous state capture position.\n")
+	_T("  M         Enable or disable audio channels, bitplanes or sprites.\n")
+	_T("  sp  [] Dump sprite information.\n")
+	_T("  di  []   Break on disk access. R=DMA read,W=write,RW=both,P=PIO.\n")
+	_T("                        Also enables level 1 disk logging.\n")
+	_T("  did        Enable disk logging.\n")
+	_T("  dj []  Enable joystick/mouse input debugging.\n")
+	_T("  smc [<0-1>]           Enable self-modifying code detector. 1 = enable break.\n")
+	_T("  dm                    Dump current address space map.\n")
+	_T("  v  []     Show DMA data (accurate only in cycle-exact mode).\n")
+	_T("                        v [-1 to -4] = enable visual DMA debugger.\n")
+	_T("  ?              Hex ($ and 0x)/Bin (%)/Dec (!) converter.\n")
+#ifdef _WIN32
+	_T("  x                     Close debugger.\n")
+	_T("  xx                    Switch between console and GUI debugger.\n")
+	_T("  mg 
          Memory dump starting at 
 in GUI.\n")
+	_T("  dg 
          Disassembly starting at 
 in GUI.\n")
+#endif
+	_T("  q                     Quit the emulator. You don't want to use this command.\n\n")
+};
+
+void debug_help (void)
+{
+	console_out (help);
+}
+
+static int debug_linecounter;
+#define MAX_LINECOUNTER 1000
+
+static int debug_out (const TCHAR *format, ...)
+{
+	va_list parms;
+	TCHAR buffer[4000];
+
+	va_start (parms, format);
+	_vsntprintf (buffer, 4000 - 1, format, parms);
+	va_end (parms);
+
+	console_out (buffer);
+	if (debug_linecounter < MAX_LINECOUNTER)
+		debug_linecounter++;
+	if (debug_linecounter >= MAX_LINECOUNTER)
+		return 0;
+	return 1;
+}
+
+#endif	/* ! WINUAE_FOR_HATARI */
+
+uae_u32 get_byte_debug (uaecptr addr)
+{
+	uae_u32 v = 0xff;
+	if (debug_mmu_mode) {
+		flagtype olds = regs.s;
+		regs.s = (debug_mmu_mode & 4) != 0;
+		TRY(p) {
+			if (currprefs.mmu_model == 68030) {
+				v = mmu030_get_generic (addr, debug_mmu_mode, sz_byte, sz_byte, 0);
+			} else {
+				v = mmu_get_user_byte (addr, regs.s != 0, (debug_mmu_mode & 1) ? true : false, false, sz_byte);
+			}
+		} CATCH(p) {
+		} ENDTRY
+		regs.s = olds;
+	} else {
+#ifndef WINUAE_FOR_HATARI
+		v = get_byte (addr);
+#else
+		v = STMemory_ReadByte ( addr );
+#endif
+	}
+	return v;
+}
+uae_u32 get_word_debug (uaecptr addr)
+{
+	uae_u32 v = 0xffff;
+	if (debug_mmu_mode) {
+		flagtype olds = regs.s;
+		regs.s = (debug_mmu_mode & 4) != 0;
+		TRY(p) {
+			if (currprefs.mmu_model == 68030) {
+				v = mmu030_get_generic (addr, debug_mmu_mode, sz_word, sz_word, 0);
+			} else {
+				v = mmu_get_user_word (addr, regs.s != 0, (debug_mmu_mode & 1) ? true : false, false, sz_word);
+			}
+		} CATCH(p) {
+		} ENDTRY
+		regs.s = olds;
+	} else {
+#ifndef WINUAE_FOR_HATARI
+		v = get_word (addr);
+#else
+		v = STMemory_ReadWord ( addr );
+#endif
+	}
+	return v;
+}
+uae_u32 get_long_debug (uaecptr addr)
+{
+	uae_u32 v = 0xffffffff;
+	if (debug_mmu_mode) {
+		flagtype olds = regs.s;
+		regs.s = (debug_mmu_mode & 4) != 0;
+		TRY(p) {
+			if (currprefs.mmu_model == 68030) {
+				v = mmu030_get_generic (addr, debug_mmu_mode, sz_long, sz_long, 0);
+			} else {
+				v = mmu_get_user_long (addr, regs.s != 0, (debug_mmu_mode & 1) ? true : false, false, sz_long);
+			}
+		} CATCH(p) {
+		} ENDTRY
+		regs.s = olds;
+	} else {
+#ifndef WINUAE_FOR_HATARI
+		v = get_long (addr);
+#else
+		v = STMemory_ReadLong ( addr );
+#endif
+	}
+	return v;
+}
+uae_u32 get_iword_debug (uaecptr addr)
+{
+	if (debug_mmu_mode) {
+		return get_word_debug (addr);
+	} else {
+#ifndef WINUAE_FOR_HATARI
+		if (valid_address (addr, 2))
+			return get_word (addr);
+		return 0xffff;
+#else
+		return get_word_debug (addr);
+#endif
+	}
+}
+uae_u32 get_ilong_debug (uaecptr addr)
+{
+	if (debug_mmu_mode) {
+		return get_long_debug (addr);
+	} else {
+#ifndef WINUAE_FOR_HATARI
+		if (valid_address (addr, 4))
+			return get_long (addr);
+		return 0xffffffff;
+#else
+		return get_long_debug (addr);
+#endif
+	}
+}
+
+#ifndef WINUAE_FOR_HATARI
+int safe_addr (uaecptr addr, int size)
+{
+	if (debug_mmu_mode) {
+		flagtype olds = regs.s;
+		regs.s = (debug_mmu_mode & 4) != 0;
+		TRY(p) {
+			if (currprefs.mmu_model >= 68040)
+				addr = mmu_translate (addr, regs.s != 0, (debug_mmu_mode & 1), false);
+			else
+				addr = mmu030_translate (addr, regs.s != 0, (debug_mmu_mode & 1), false);
+		} CATCH(p) {
+			return 0;
+		} ENDTRY
+		regs.s = olds;
+	}
+	addrbank *ab = &get_mem_bank (addr);
+	if (!ab)
+		return 0;
+	if (ab->flags & ABFLAG_SAFE)
+		return 1;
+	if (!ab->check (addr, size))
+		return 0;
+	if (ab->flags & (ABFLAG_RAM | ABFLAG_ROM | ABFLAG_ROMIN | ABFLAG_SAFE))
+		return 1;
+	return 0;
+}
+
+static bool iscancel (int counter)
+{
+	static int cnt;
+
+	cnt++;
+	if (cnt < counter)
+		return false;
+	cnt = 0;
+	if (!console_isch ())
+		return false;
+	console_getch ();
+	return true;
+}
+
+static bool isoperator(TCHAR **cp)
+{
+	TCHAR c = **cp;
+	return c == '+' || c == '-' || c == '/' || c == '*' || c == '(' || c == ')';
+}
+
+static void ignore_ws (TCHAR **c)
+{
+	while (**c && _istspace(**c))
+		(*c)++;
+}
+static TCHAR peekchar (TCHAR **c)
+{
+	return **c;
+}
+static TCHAR readchar (TCHAR **c)
+{
+	TCHAR cc = **c;
+	(*c)++;
+	return cc;
+}
+static TCHAR next_char (TCHAR **c)
+{
+	ignore_ws (c);
+	return *(*c)++;
+}
+static TCHAR peek_next_char (TCHAR **c)
+{
+	TCHAR *pc = *c;
+	return pc[1];
+}
+static int more_params (TCHAR **c)
+{
+	ignore_ws (c);
+	return (**c) != 0;
+}
+
+static uae_u32 readint (TCHAR **c);
+static uae_u32 readbin (TCHAR **c);
+static uae_u32 readhex (TCHAR **c);
+
+static int readregx (TCHAR **c, uae_u32 *valp)
+{
+	int i;
+	uae_u32 addr;
+	TCHAR *p = *c;
+	TCHAR tmp[10];
+	int extra = 0;
+
+	addr = 0;
+	i = 0;
+	while (p[i]) {
+		tmp[i] = _totupper (p[i]);
+		if (i >= sizeof (tmp) / sizeof (TCHAR) - 1)
+			break;
+		i++;
+	}
+	tmp[i] = 0;
+	if (_totupper (tmp[0]) == 'R') {
+		memmove (tmp, tmp + 1, sizeof (tmp) - sizeof (TCHAR));
+		extra = 1;
+	}
+	if (!_tcsncmp (tmp, _T("USP"), 3)) {
+		addr = regs.usp;
+		(*c) += 3;
+	} else if (!_tcsncmp (tmp, _T("VBR"), 3)) {
+		addr = regs.vbr;
+		(*c) += 3;
+	} else if (!_tcsncmp (tmp, _T("MSP"), 3)) {
+		addr = regs.msp;
+		(*c) += 3;
+	} else if (!_tcsncmp (tmp, _T("ISP"), 3)) {
+		addr = regs.isp;
+		(*c) += 3;
+	} else if (!_tcsncmp (tmp, _T("PC"), 2)) {
+		addr = regs.pc;
+		(*c) += 2;
+	} else if (tmp[0] == 'A' || tmp[0] == 'D') {
+		int reg = 0;
+		if (tmp[0] == 'A')
+			reg += 8;
+		reg += tmp[1] - '0';
+		if (reg < 0 || reg > 15)
+			return 0;
+		addr = regs.regs[reg];
+		(*c) += 2;
+	} else {
+		return 0;
+	}
+	*valp = addr;
+	(*c) += extra;
+	return 1;
+}
+
+static bool readbinx (TCHAR **c, uae_u32 *valp)
+{
+	uae_u32 val = 0;
+	bool first = true;
+
+	ignore_ws (c);
+	for (;;) {
+		TCHAR nc = **c;
+		if (nc != '1' && nc != '0') {
+			if (first)
+				return false;
+			break;
+		}
+		first = false;
+		(*c)++;
+		val <<= 1;
+		if (nc == '1')
+			val |= 1;
+	}
+	*valp = val;
+	return true;
+}
+
+static bool readhexx (TCHAR **c, uae_u32 *valp)
+{
+	uae_u32 val = 0;
+	TCHAR nc;
+
+	ignore_ws (c);
+	if (!isxdigit (peekchar (c)))
+		return false;
+	while (isxdigit (nc = **c)) {
+		(*c)++;
+		val *= 16;
+		nc = _totupper (nc);
+		if (isdigit (nc)) {
+			val += nc - '0';
+		} else {
+			val += nc - 'A' + 10;
+		}
+	}
+	*valp = val;
+	return true;
+}
+
+static bool readintx (TCHAR **c, uae_u32 *valp)
+{
+	uae_u32 val = 0;
+	TCHAR nc;
+	int negative = 0;
+
+	ignore_ws (c);
+	if (**c == '-')
+		negative = 1, (*c)++;
+	if (!isdigit (peekchar (c)))
+		return false;
+	while (isdigit (nc = **c)) {
+		(*c)++;
+		val *= 10;
+		val += nc - '0';
+	}
+	*valp = val * (negative ? -1 : 1);
+	return true;
+}
+
+
+static int checkvaltype2 (TCHAR **c, uae_u32 *val, TCHAR def)
+{
+	TCHAR nc;
+
+	ignore_ws (c);
+	nc = _totupper (**c);
+	if (nc == '!') {
+		(*c)++;
+		return readintx (c, val) ? 1 : 0;
+	}
+	if (nc == '$') {
+		(*c)++;
+		return  readhexx (c, val) ? 1 : 0;
+	}
+	if (nc == '0' && _totupper ((*c)[1]) == 'X') {
+		(*c)+= 2;
+		return  readhexx (c, val) ? 1 : 0;
+	}
+	if (nc == '%') {
+		(*c)++;
+		return readbinx (c, val) ? 1: 0;
+	}
+	if (nc >= 'A' && nc <= 'Z' && nc != 'A' && nc != 'D') {
+		if (readregx (c, val))
+			return 1;
+	}
+	if (def == '!') {
+		return readintx (c, val) ? -1 : 0;
+		return -1;
+	} else if (def == '$') {
+		return readhexx (c, val) ? -1 : 0;
+	} else if (def == '%') {
+		return readbinx (c, val) ? -1 : 0;
+	}
+	return 0;
+}
+
+static int readsize (int val, TCHAR **c)
+{
+	TCHAR cc = _totupper (readchar(c));
+	if (cc == 'B')
+		return 1;
+	if (cc == 'W')
+		return 2;
+	if (cc == '3')
+		return 3;
+	if (cc == 'L')
+		return 4;
+	return 0;
+}
+
+static int checkvaltype (TCHAR **cp, uae_u32 *val, int *size, TCHAR def)
+{
+	TCHAR form[256], *p;
+	bool gotop = false;
+	double out;
+
+	form[0] = 0;
+	*size = 0;
+	p = form;
+	for (;;) {
+		uae_u32 v;
+		if (!checkvaltype2 (cp, &v, def))
+			return 0;
+		*val = v;
+		// stupid but works!
+		_stprintf(p, _T("%u"), v);
+		p += _tcslen (p);
+		if (peekchar (cp) == '.') {
+			readchar (cp);
+			*size = readsize (v, cp);
+		}
+		if (!isoperator (cp))
+			break;
+		gotop = true;
+		*p++= readchar (cp);
+		*p = 0;
+	}
+	if (!gotop) {
+		if (*size == 0) {
+			uae_s32 v = (uae_s32)(*val);
+			if (v > 255 || v < -127) {
+				*size = 2;
+			} else if (v > 65535 || v < -32767) {
+				*size = 4;
+			} else {
+				*size = 1;
+			}
+		}
+		return 1;
+	}
+	if (calc (form, &out)) {
+		*val = (uae_u32)out;
+		if (*size == 0) {
+			uae_s32 v = (uae_s32)(*val);
+			if (v > 255 || v < -127) {
+				*size = 2;
+			} else if (v > 65535 || v < -32767) {
+				*size = 4;
+			} else {
+				*size = 1;
+			}
+		}
+		return 1;
+	}
+	return 0;
+}
+
+
+static uae_u32 readnum (TCHAR **c, int *size, TCHAR def)
+{
+	uae_u32 val;
+	if (checkvaltype (c, &val, size, def))
+		return val;
+	return 0;
+}
+
+static uae_u32 readint (TCHAR **c)
+{
+	int size;
+	return readnum (c, &size, '!');
+}
+static uae_u32 readhex (TCHAR **c)
+{
+	int size;
+	return readnum (c, &size, '$');
+}
+static uae_u32 readbin (TCHAR **c)
+{
+	int size;
+	return readnum (c, &size, '%');
+}
+static uae_u32 readint (TCHAR **c, int *size)
+{
+	return readnum (c, size, '!');
+}
+static uae_u32 readhex (TCHAR **c, int *size)
+{
+	return readnum (c, size, '$');
+}
+
+static int next_string (TCHAR **c, TCHAR *out, int max, int forceupper)
+{
+	TCHAR *p = out;
+	int startmarker = 0;
+
+	if (**c == '\"') {
+		startmarker = 1;
+		(*c)++;
+	}
+	*p = 0;
+	while (**c != 0) {
+		if (**c == '\"' && startmarker)
+			break;
+		if (**c == 32 && !startmarker) {
+			ignore_ws (c);
+			break;
+		}
+		*p = next_char (c);
+		if (forceupper)
+			*p = _totupper(*p);
+		*++p = 0;
+		max--;
+		if (max <= 1)
+			break;
+	}
+	return _tcslen (out);
+}
+
+static void converter (TCHAR **c)
+{
+	uae_u32 v = readint (c);
+	TCHAR s[100];
+	TCHAR *p = s;
+	int i;
+
+	for (i = 0; i < 32; i++)
+		s[i] = (v & (1 << (31 - i))) ? '1' : '0';
+	s[i] = 0;
+	console_out_f (_T("0x%08X = %%%s = %u = %d\n"), v, s, v, (uae_s32)v);
+}
+
+int notinrom (void)
+{
+	uaecptr pc = munge24 (m68k_getpc ());
+	if (pc < 0x00e00000 || pc > 0x00ffffff)
+		return 1;
+	return 0;
+}
+
+static uae_u32 lastaddr (void)
+{
+	if (currprefs.z3fastmem2_size)
+		return z3fastmem2_bank.start + currprefs.z3fastmem2_size;
+	if (currprefs.z3fastmem_size)
+		return z3fastmem_bank.start + currprefs.z3fastmem_size;
+	if (currprefs.z3chipmem_size)
+		return z3chipmem_bank.start + currprefs.z3chipmem_size;
+	if (currprefs.mbresmem_high_size)
+		return a3000hmem_bank.start + currprefs.mbresmem_high_size;
+	if (currprefs.mbresmem_low_size)
+		return a3000lmem_bank.start + currprefs.mbresmem_low_size;
+	if (currprefs.bogomem_size)
+		return bogomem_bank.start + currprefs.bogomem_size;
+	if (currprefs.fastmem_size)
+		return fastmem_bank.start + currprefs.fastmem_size;
+	return currprefs.chipmem_size;
+}
+
+static uaecptr nextaddr2 (uaecptr addr, int *next)
+{
+	uaecptr prev, prevx;
+	int size, sizex;
+
+	if (addr >= lastaddr ()) {
+		*next = -1;
+		return 0xffffffff;
+	}
+	prev = currprefs.z3autoconfig_start + currprefs.z3fastmem_size;
+	size = currprefs.z3fastmem2_size;
+
+	if (currprefs.z3fastmem_size) {
+		prevx = prev;
+		sizex = size;
+		size = currprefs.z3fastmem_size;
+		prev = z3fastmem_bank.start;
+		if (addr == prev + size) {
+			*next = prevx + sizex;
+			return prevx;
+		}
+	}
+	if (currprefs.z3chipmem_size) {
+		prevx = prev;
+		sizex = size;
+		size = currprefs.z3chipmem_size;
+		prev = z3chipmem_bank.start;
+		if (addr == prev + size) {
+			*next = prevx + sizex;
+			return prevx;
+		}
+	}
+	if (currprefs.mbresmem_high_size) {
+		sizex = size;
+		prevx = prev;
+		size = currprefs.mbresmem_high_size;
+		prev = a3000hmem_bank.start;
+		if (addr == prev + size) {
+			*next = prevx + sizex;
+			return prevx;
+		}
+	}
+	if (currprefs.mbresmem_low_size) {
+		prevx = prev;
+		sizex = size;
+		size = currprefs.mbresmem_low_size;
+		prev = a3000lmem_bank.start;
+		if (addr == prev + size) {
+			*next = prevx + sizex;
+			return prevx;
+		}
+	}
+	if (currprefs.bogomem_size) {
+		sizex = size;
+		prevx = prev;
+		size = currprefs.bogomem_size;
+		prev = bogomem_bank.start;
+		if (addr == prev + size) {
+			*next = prevx + sizex;
+			return prevx;
+		}
+	}
+	if (currprefs.fastmem_size) {
+		sizex = size;
+		prevx = prev;
+		size = currprefs.fastmem_size;
+		prev = fastmem_bank.start;
+		if (addr == prev + size) {
+			*next = prevx + sizex;
+			return prevx;
+		}
+	}
+	sizex = size;
+	prevx = prev;
+	size = currprefs.chipmem_size;
+	if (addr == size) {
+		*next = prevx + sizex;
+		return prevx;
+	}
+	if (addr == 1)
+		*next = size;
+	return addr;
+}
+
+static uaecptr nextaddr (uaecptr addr, uaecptr last, uaecptr *end)
+{
+	static uaecptr old;
+	uaecptr paddr = addr;
+	int next = last;
+	if (last && 0) {
+		if (addr >= last)
+			return 0xffffffff;
+		return addr + 1;
+	}
+	if (addr == 0xffffffff) {
+		if (end)
+			*end = currprefs.chipmem_size;
+		return 0;
+	}
+	if (end)
+		next = *end;
+	addr = nextaddr2 (addr + 1, &next);
+	if (end)
+		*end = next;
+	if (old != next) {
+		if (addr != 0xffffffff)
+			console_out_f (_T("Scanning.. %08x - %08x (%s)\n"), addr & 0xffffff00, next, get_mem_bank (addr).name);
+		old = next;
+	}
+#if 0
+	if (next && addr != 0xffffffff) {
+		uaecptr xa = addr;
+		if (xa == 1)
+			xa = 0;
+		console_out_f ("%08X -> %08X (%08X)...\n", xa, xa + next - 1, next);
+	}
+#endif
+	return addr;
+}
+
+uaecptr dumpmem2 (uaecptr addr, TCHAR *out, int osize)
+{
+	int i, cols = 8;
+	int nonsafe = 0;
+
+	if (osize <= (9 + cols * 5 + 1 + 2 * cols))
+		return addr;
+	_stprintf (out, _T("%08X "), addr);
+	for (i = 0; i < cols; i++) {
+		uae_u8 b1, b2;
+		b1 = b2 = 0;
+		if (safe_addr (addr, 1)) {
+			b1 = get_byte_debug (addr + 0);
+			b2 = get_byte_debug (addr + 1);
+			_stprintf (out + 9 + i * 5, _T("%02X%02X "), b1, b2);
+			out[9 + cols * 5 + 1 + i * 2 + 0] = b1 >= 32 && b1 < 127 ? b1 : '.';
+			out[9 + cols * 5 + 1 + i * 2 + 1] = b2 >= 32 && b2 < 127 ? b2 : '.';
+		} else {
+			nonsafe++;
+			_tcscpy (out + 9 + i * 5, _T("**** "));
+			out[9 + cols * 5 + 1 + i * 2 + 0] = '*';
+			out[9 + cols * 5 + 1 + i * 2 + 1] = '*';
+		}
+		addr += 2;
+	}
+	out[9 + cols * 5] = ' ';
+	out[9 + cols * 5 + 1 + 2 * cols] = 0;
+	if (nonsafe == cols) {
+		addrbank *ab = &get_mem_bank (addr);
+		if (ab->name)
+			memcpy (out + (9 + 4 + 1) * sizeof (TCHAR), ab->name, _tcslen (ab->name) * sizeof (TCHAR));
+	}
+	return addr;
+}
+
+static void dumpmem (uaecptr addr, uaecptr *nxmem, int lines)
+{
+	TCHAR line[MAX_LINEWIDTH + 1];
+	for (;lines--;) {
+		addr = dumpmem2 (addr, line, sizeof(line));
+		debug_out (_T("%s"), line);
+		if (!debug_out (_T("\n")))
+			break;
+	}
+	*nxmem = addr;
+}
+
+static void dump_custom_regs (int aga)
+{
+	int len, i, j, end;
+	uae_u8 *p1, *p2, *p3, *p4;
+
+	if (aga) {
+		dump_aga_custom();
+		return;
+	}
+
+	p1 = p2 = save_custom (&len, 0, 1);
+	p1 += 4; // skip chipset type
+	for (i = 0; i < 4; i++) {
+		p4 = p1 + 0xa0 + i * 16;
+		p3 = save_audio (i, &len, 0);
+		p4[0] = p3[12];
+		p4[1] = p3[13];
+		p4[2] = p3[14];
+		p4[3] = p3[15];
+		p4[4] = p3[4];
+		p4[5] = p3[5];
+		p4[6] = p3[8];
+		p4[7] = p3[9];
+		p4[8] = 0;
+		p4[9] = p3[1];
+		p4[10] = p3[10];
+		p4[11] = p3[11];
+		free (p3);
+	}
+	end = 0;
+	while (custd[end].name)
+		end++;
+	end++;
+	end /= 2;
+	for (i = 0; i < end; i++) {
+		uae_u16 v1, v2;
+		int addr1, addr2;
+		j = end + i;
+		addr1 = custd[i].adr & 0x1ff;
+		addr2 = custd[j].adr & 0x1ff;
+		v1 = (p1[addr1 + 0] << 8) | p1[addr1 + 1];
+		v2 = (p1[addr2 + 0] << 8) | p1[addr2 + 1];
+		console_out_f (_T("%03X %s\t%04X\t%03X %s\t%04X\n"),
+			addr1, custd[i].name, v1,
+			addr2, custd[j].name, v2);
+	}
+	free (p2);
+}
+
+static void dump_vectors (uaecptr addr)
+{
+	int i = 0, j = 0;
+
+	if (addr == 0xffffffff)
+		addr = regs.vbr;
+
+	while (int_labels[i].name || trap_labels[j].name) {
+		if (int_labels[i].name) {
+			console_out_f (_T("$%08X %02d: %12s $%08X  "), int_labels[i].adr + addr, int_labels[i].adr / 4,
+				int_labels[i].name, get_long_debug (int_labels[i].adr + addr));
+			i++;
+		}
+		if (trap_labels[j].name) {
+			console_out_f (_T("$%08X %02d: %12s $%08X"), trap_labels[j].adr + addr, trap_labels[j].adr / 4,
+				trap_labels[j].name, get_long_debug (trap_labels[j].adr + addr));
+			j++;
+		}
+		console_out (_T("\n"));
+	}
+}
+
+static void disassemble_wait (FILE *file, unsigned long insn)
+{
+	int vp, hp, ve, he, bfd, v_mask, h_mask;
+	int doout = 0;
+
+	vp = (insn & 0xff000000) >> 24;
+	hp = (insn & 0x00fe0000) >> 16;
+	ve = (insn & 0x00007f00) >> 8;
+	he = (insn & 0x000000fe);
+	bfd = (insn & 0x00008000) >> 15;
+
+	/* bit15 can never be masked out*/
+	v_mask = vp & (ve | 0x80);
+	h_mask = hp & he;
+	if (v_mask > 0) {
+		doout = 1;
+		console_out (_T("vpos "));
+		if (ve != 0x7f) {
+			console_out_f (_T("& 0x%02x "), ve);
+		}
+		console_out_f (_T(">= 0x%02x"), v_mask);
+	}
+	if (he > 0) {
+		if (v_mask > 0) {
+			console_out (_T(" and"));
+		}
+		console_out (_T(" hpos "));
+		if (he != 0xfe) {
+			console_out_f (_T("& 0x%02x "), he);
+		}
+		console_out_f (_T(">= 0x%02x"), h_mask);
+	} else {
+		if (doout)
+			console_out (_T(", "));
+		console_out (_T(", ignore horizontal"));
+	}
+
+	console_out_f (_T("\n                        \t;  VP %02x, VE %02x; HP %02x, HE %02x; BFD %d\n"),
+		vp, ve, hp, he, bfd);
+}
+
+#define NR_COPPER_RECORDS 100000
+/* Record copper activity for the debugger.  */
+struct cop_rec
+{
+	uae_u16 w1, w2;
+	int hpos, vpos;
+	int bhpos, bvpos;
+	uaecptr addr;
+};
+static struct cop_rec *cop_record[2];
+static int nr_cop_records[2], curr_cop_set;
+
+#define NR_DMA_REC_HPOS 256
+#define NR_DMA_REC_VPOS 1000
+static struct dma_rec *dma_record[2];
+static int dma_record_toggle;
+
+void record_dma_reset (void)
+{
+	int v, h;
+	struct dma_rec *dr, *dr2;
+
+	if (!dma_record[0])
+		return;
+	dma_record_toggle ^= 1;
+	dr = dma_record[dma_record_toggle];
+	for (v = 0; v < NR_DMA_REC_VPOS; v++) {
+		for (h = 0; h < NR_DMA_REC_HPOS; h++) {
+			dr2 = &dr[v * NR_DMA_REC_HPOS + h];
+			memset (dr2, 0, sizeof (struct dma_rec));
+			dr2->reg = 0xffff;
+			dr2->addr = 0xffffffff;
+		}
+	}
+}
+
+void record_copper_reset (void)
+{
+	/* Start a new set of copper records.  */
+	curr_cop_set ^= 1;
+	nr_cop_records[curr_cop_set] = 0;
+}
+
+STATIC_INLINE uae_u32 ledcolor (uae_u32 c, uae_u32 *rc, uae_u32 *gc, uae_u32 *bc, uae_u32 *a)
+{
+	uae_u32 v = rc[(c >> 16) & 0xff] | gc[(c >> 8) & 0xff] | bc[(c >> 0) & 0xff];
+	if (a)
+		v |= a[255 - ((c >> 24) & 0xff)];
+	return v;
+}
+
+STATIC_INLINE void putpixel (uae_u8 *buf, int bpp, int x, xcolnr c8)
+{
+	if (x <= 0)
+		return;
+
+	switch (bpp) {
+	case 1:
+		buf[x] = (uae_u8)c8;
+		break;
+	case 2:
+		{
+			uae_u16 *p = (uae_u16*)buf + x;
+			*p = (uae_u16)c8;
+			break;
+		}
+	case 3:
+		/* no 24 bit yet */
+		break;
+	case 4:
+		{
+			uae_u32 *p = (uae_u32*)buf + x;
+			*p = c8;
+			break;
+		}
+	}
+}
+
+#define lc(x) ledcolor (x, xredcolors, xgreencolors, xbluecolors, NULL)
+
+static uae_u32 intlevc[] = { 0x000000, 0x444444, 0x008800, 0xffff00, 0x000088, 0x880000, 0xff0000, 0xffffff };
+
+void debug_draw_cycles (uae_u8 *buf, int bpp, int line, int width, int height, uae_u32 *xredcolors, uae_u32 *xgreencolors, uae_u32 *xbluescolors)
+{
+	int y, x, xx, dx, xplus, yplus;
+	struct dma_rec *dr;
+	int t;
+	uae_u32 cc[DMARECORD_MAX];
+
+	if (debug_dma >= 4)
+		yplus = 2;
+	else
+		yplus = 1;
+	if (debug_dma >= 3)
+		xplus = 2;
+	else
+		xplus = 1;
+
+	t = dma_record_toggle ^ 1;
+	y = line / yplus - 8;
+
+	if (y < 0)
+		return;
+	if (y > maxvpos)
+		return;
+	if (y >= height)
+		return;
+
+	dx = width - xplus * ((maxhpos + 1) & ~1) - 16;
+
+	cc[0] = lc(0x222222);
+	cc[DMARECORD_REFRESH] = lc(0x444444);
+	cc[DMARECORD_CPU] = lc(0x888888);
+	cc[DMARECORD_COPPER] = lc(0xeeee00);
+	cc[DMARECORD_AUDIO] = lc(0xff0000);
+	cc[DMARECORD_BLITTER] = lc(0x008888);
+	cc[DMARECORD_BLITTER_FILL] = lc(0x0088ff);
+	cc[DMARECORD_BLITTER_LINE] = lc(0x00ff00);
+	cc[DMARECORD_BITPLANE] = lc(0x0000ff);
+	cc[DMARECORD_SPRITE] = lc(0xff00ff);
+	cc[DMARECORD_DISK] = lc(0xffffff);
+
+	uae_s8 intlev = 0;
+	for (x = 0; x < maxhpos; x++) {
+		uae_u32 c = cc[0];
+		xx = x * xplus + dx;
+		dr = &dma_record[t][y * NR_DMA_REC_HPOS + x];
+		if (dr->reg != 0xffff) {
+			c = cc[dr->type];
+		}
+		if (dr->intlev > intlev)
+			intlev = dr->intlev;
+		putpixel (buf, bpp, xx + 4, c);
+		if (xplus)
+			putpixel (buf, bpp, xx + 4 + 1, c);
+	}
+	putpixel (buf, bpp, dx + 0, 0);
+	putpixel (buf, bpp, dx + 1, lc(intlevc[intlev]));
+	putpixel (buf, bpp, dx + 2, lc(intlevc[intlev]));
+	putpixel (buf, bpp, dx + 3, 0);
+}
+
+#define HEATMAP_COUNT 50
+static struct memory_heatmap *heatmap;
+struct memory_heatmap
+{
+	uae_u16 cnt;
+	uae_u16 type;
+};
+
+static void memwatch_heatmap (uaecptr addr, int rwi, int size)
+{
+}
+
+static void record_dma_heatmap (uaecptr addr, int type)
+{
+	if (addr >= 0x01000000 || !heatmap)
+		return;
+	struct memory_heatmap *hp = &heatmap[addr / 2];
+	hp->cnt = HEATMAP_COUNT;
+	hp->type = type;
+}
+
+void record_dma_event (int evt, int hpos, int vpos)
+{
+	struct dma_rec *dr;
+
+	if (!dma_record[0])
+		return;
+	if (hpos >= NR_DMA_REC_HPOS || vpos >= NR_DMA_REC_VPOS)
+		return;
+	dr = &dma_record[dma_record_toggle][vpos * NR_DMA_REC_HPOS + hpos];
+	dr->evt |= evt;
+}
+
+struct dma_rec *record_dma (uae_u16 reg, uae_u16 dat, uae_u32 addr, int hpos, int vpos, int type)
+{
+	struct dma_rec *dr;
+
+	if (!heatmap)
+		heatmap = xcalloc (struct memory_heatmap, 16 * 1024 * 1024 / 2);
+	if (!dma_record[0]) {
+		dma_record[0] = xmalloc (struct dma_rec, NR_DMA_REC_HPOS * NR_DMA_REC_VPOS);
+		dma_record[1] = xmalloc (struct dma_rec, NR_DMA_REC_HPOS * NR_DMA_REC_VPOS);
+		dma_record_toggle = 0;
+		record_dma_reset ();
+	}
+	if (hpos >= NR_DMA_REC_HPOS || vpos >= NR_DMA_REC_VPOS)
+		return NULL;
+
+	record_dma_heatmap (addr, type);
+
+	dr = &dma_record[dma_record_toggle][vpos * NR_DMA_REC_HPOS + hpos];
+	if (dr->reg != 0xffff) {
+		write_log (_T("DMA conflict: v=%d h=%d OREG=%04X NREG=%04X\n"), vpos, hpos, dr->reg, reg);
+		return dr;
+	}
+	dr->reg = reg;
+	dr->dat = dat;
+	dr->addr = addr;
+	dr->type = type;
+	dr->intlev = regs.intmask;
+	return dr;
+}
+
+static void decode_dma_record (int hpos, int vpos, int toggle, bool logfile)
+{
+	struct dma_rec *dr;
+	int h, i, maxh, cnt;
+	uae_u32 cycles;
+
+	if (!dma_record[0])
+		return;
+	dr = &dma_record[dma_record_toggle ^ toggle][vpos * NR_DMA_REC_HPOS];
+	if (logfile)
+		write_dlog (_T("Line: %02X %3d HPOS %02X %3d:\n"), vpos, vpos, hpos, hpos);
+	else
+		console_out_f (_T("Line: %02X %3d HPOS %02X %3d:\n"), vpos, vpos, hpos, hpos);
+	h = hpos;
+	dr += hpos;
+	maxh = hpos + 80;
+	if (maxh > maxhpos)
+		maxh = maxhpos;
+	cycles = vsync_cycles;
+	if (toggle)
+		cycles -= maxvpos * maxhpos * CYCLE_UNIT;
+	cnt = 0;
+	while (h < maxh) {
+		int col = 9;
+		int cols = 8;
+		TCHAR l1[81];
+		TCHAR l2[81];
+		TCHAR l3[81];
+		TCHAR l4[81];
+		TCHAR l5[81];
+		for (i = 0; i < cols && h < maxh; i++, h++, dr++) {
+			int cl = i * col, cl2;
+			int r = dr->reg;
+			bool longsize = false;
+			TCHAR *sr;
+
+			sr = _T("    ");
+			if (dr->type == DMARECORD_COPPER)
+				sr = _T("COP ");
+			else if (dr->type == DMARECORD_BLITTER)
+				sr = _T("BLT ");
+			else if (dr->type == DMARECORD_BLITTER_LINE)
+				sr = _T("BLL ");
+			else if (dr->type == DMARECORD_REFRESH)
+				sr = _T("RFS ");
+			else if (dr->type == DMARECORD_AUDIO)
+				sr = _T("AUD ");
+			else if (dr->type == DMARECORD_DISK)
+				sr = _T("DSK ");
+			else if (dr->type == DMARECORD_SPRITE)
+				sr = _T("SPR ");
+			_stprintf (l1 + cl, _T("[%02X %3d]"), h, h);
+			_tcscpy (l4 + cl, _T("        "));
+			if (r != 0xffff) {
+				if (r & 0x1000) {
+					if ((r & 0x0100) == 0x0000)
+						_tcscpy (l2 + cl, _T("  CPU-R  "));
+					else if ((r & 0x0100) == 0x0100)
+						_tcscpy (l2 + cl, _T("  CPU-W  "));
+					if ((r & 0xff) == 4) {
+						l2[cl + 7] = 'L';
+						longsize = true;
+					}
+					if ((r & 0xff) == 2)
+						l2[cl + 7] = 'W';
+					if ((r & 0xff) == 1)
+						l2[cl + 7] = 'B';
+				} else {
+					_stprintf (l2 + cl, _T("%4s %03X"), sr, r);
+				}
+				_stprintf (l3 + cl, longsize ? _T("%08X") : _T("    %04X"), dr->dat);
+				if (dr->addr != 0xffffffff)
+					_stprintf (l4 + cl, _T("%08X"), dr->addr & 0x00ffffff);
+			} else {
+				_tcscpy (l2 + cl, _T("        "));
+				_tcscpy (l3 + cl, _T("        "));
+			}
+			cl2 = cl;
+			if (dr->evt & DMA_EVENT_BLITNASTY)
+				l3[cl2++] = 'N';
+			if (dr->evt & DMA_EVENT_BLITSTARTFINISH)
+				l3[cl2++] = 'B';
+			if (dr->evt & DMA_EVENT_BLITIRQ)
+				l3[cl2++] = 'b';
+			if (dr->evt & DMA_EVENT_BPLFETCHUPDATE)
+				l3[cl2++] = 'p';
+			if (dr->evt & DMA_EVENT_COPPERWAKE)
+				l3[cl2++] = 'W';
+			if (dr->evt & DMA_EVENT_COPPERWANTED)
+				l3[cl2++] = 'c';
+			if (dr->evt & DMA_EVENT_CPUIRQ)
+				l3[cl2++] = 'I';
+			if (dr->evt & DMA_EVENT_INTREQ)
+				l3[cl2++] = 'i';
+			_stprintf (l5 + cl, _T("%08X"), cycles + (vpos * maxhpos + (hpos + cnt)) * CYCLE_UNIT);
+			if (i < cols - 1 && h < maxh - 1) {
+				l1[cl + col - 1] = 32;
+				l2[cl + col - 1] = 32;
+				l3[cl + col - 1] = 32;
+				l4[cl + col - 1] = 32;
+				l5[cl + col - 1] = 32;
+			}
+			cnt++;
+		}
+		if (logfile) {
+			write_dlog (_T("%s\n"), l1);
+			write_dlog (_T("%s\n"), l2);
+			write_dlog (_T("%s\n"), l3);
+			write_dlog (_T("%s\n"), l4);
+			write_dlog (_T("%s\n"), l5);
+			write_dlog (_T("\n"));
+		} else {
+			console_out_f (_T("%s\n"), l1);
+			console_out_f (_T("%s\n"), l2);
+			console_out_f (_T("%s\n"), l3);
+			console_out_f (_T("%s\n"), l4);
+			console_out_f (_T("%s\n"), l5);
+			console_out_f (_T("\n"));
+		}
+	}
+}
+void log_dma_record (void)
+{
+	if (!input_record && !input_play)
+		return;
+	if (!debug_dma)
+		debug_dma = 1;
+	decode_dma_record (0, 0, 0, true);
+}
+
+static void init_record_copper(void)
+{
+	if (!cop_record[0]) {
+		cop_record[0] = xmalloc(struct cop_rec, NR_COPPER_RECORDS);
+		cop_record[1] = xmalloc(struct cop_rec, NR_COPPER_RECORDS);
+	}
+}
+
+void record_copper_blitwait (uaecptr addr, int hpos, int vpos)
+{
+	int t = nr_cop_records[curr_cop_set];
+	init_record_copper();
+	cop_record[curr_cop_set][t].bhpos = hpos;
+	cop_record[curr_cop_set][t].bvpos = vpos;
+}
+
+void record_copper (uaecptr addr, uae_u16 word1, uae_u16 word2, int hpos, int vpos)
+{
+	int t = nr_cop_records[curr_cop_set];
+	init_record_copper();
+	if (t < NR_COPPER_RECORDS) {
+		cop_record[curr_cop_set][t].addr = addr;
+		cop_record[curr_cop_set][t].w1 = word1;
+		cop_record[curr_cop_set][t].w2 = word2;
+		cop_record[curr_cop_set][t].hpos = hpos;
+		cop_record[curr_cop_set][t].vpos = vpos;
+		cop_record[curr_cop_set][t].bvpos = -1;
+		nr_cop_records[curr_cop_set] = t + 1;
+	}
+	if (debug_copper & 2) { /* trace */
+		debug_copper &= ~2;
+		activate_debugger ();
+	}
+	if ((debug_copper & 4) && addr >= debug_copper_pc && addr <= debug_copper_pc + 3) {
+		debug_copper &= ~4;
+		activate_debugger ();
+	}
+}
+
+static struct cop_rec *find_copper_records (uaecptr addr)
+{
+	int s = curr_cop_set ^ 1;
+	int t = nr_cop_records[s];
+	int i;
+	for (i = 0; i < t; i++) {
+		if (cop_record[s][i].addr == addr)
+			return &cop_record[s][i];
+	}
+	return 0;
+}
+
+/* simple decode copper by Mark Cox */
+static void decode_copper_insn (FILE* file, uae_u16 mword1, uae_u16 mword2, unsigned long addr)
+{
+	struct cop_rec *cr = NULL;
+	uae_u32 insn_type, insn;
+	TCHAR here = ' ';
+	TCHAR record[] = _T("          ");
+
+	if ((cr = find_copper_records (addr))) {
+		_stprintf (record, _T(" [%03x %03x]"), cr->vpos, cr->hpos);
+		insn = (cr->w1 << 16) | cr->w2;
+	} else {
+		insn = (mword1 << 16) | mword2;
+	}
+
+	insn_type = insn & 0x00010001;
+
+	if (get_copper_address (-1) >= addr && get_copper_address(-1) <= addr + 3)
+		here = '*';
+
+	console_out_f (_T("%c%08x: %04x %04x%s\t;%c "), here, addr, insn >> 16, insn & 0xFFFF, record, insn != ((mword1 << 16) | mword2) ? '!' : ' ');
+
+	switch (insn_type) {
+	case 0x00010000: /* WAIT insn */
+		console_out (_T("Wait for "));
+		disassemble_wait (file, insn);
+
+		if (insn == 0xfffffffe)
+			console_out (_T("                           \t;  End of Copperlist\n"));
+
+		break;
+
+	case 0x00010001: /* SKIP insn */
+		console_out (_T("Skip if "));
+		disassemble_wait (file, insn);
+		break;
+
+	case 0x00000000:
+	case 0x00000001: /* MOVE insn */
+		{
+			int addr = (insn >> 16) & 0x1fe;
+			int i = 0;
+			while (custd[i].name) {
+				if (custd[i].adr == addr + 0xdff000)
+					break;
+				i++;
+			}
+			if (custd[i].name)
+				console_out_f (_T("%s := 0x%04x\n"), custd[i].name, insn & 0xffff);
+			else
+				console_out_f (_T("%04x := 0x%04x\n"), addr, insn & 0xffff);
+		}
+		break;
+
+	default:
+		abort ();
+	}
+
+	if (cr && cr->bvpos >= 0) {
+		console_out_f (_T("                 BLT [%03x %03x]\n"), cr->bvpos, cr->bhpos);
+	}
+}
+
+static uaecptr decode_copperlist (FILE* file, uaecptr address, int nolines)
+{
+	while (nolines-- > 0) {
+		decode_copper_insn (file, chipmem_wget_indirect (address), chipmem_wget_indirect (address + 2), address);
+		address += 4;
+	}
+	return address;
+	/* You may wonder why I don't stop this at the end of the copperlist?
+	* Well, often nice things are hidden at the end and it is debatable the actual
+	* values that mean the end of the copperlist */
+}
+
+static int copper_debugger (TCHAR **c)
+{
+	static uaecptr nxcopper;
+	uae_u32 maddr;
+	int lines;
+
+	if (**c == 'd') {
+		next_char (c);
+		if (debug_copper)
+			debug_copper = 0;
+		else
+			debug_copper = 1;
+		console_out_f (_T("Copper debugger %s.\n"), debug_copper ? _T("enabled") : _T("disabled"));
+	} else if (**c == 't') {
+		debug_copper = 1|2;
+		return 1;
+	} else if (**c == 'b') {
+		(*c)++;
+		debug_copper = 1|4;
+		if (more_params (c)) {
+			debug_copper_pc = readhex (c);
+			console_out_f (_T("Copper breakpoint @0x%08x\n"), debug_copper_pc);
+		} else {
+			debug_copper &= ~4;
+		}
+	} else {
+		if (more_params (c)) {
+			maddr = readhex (c);
+			if (maddr == 1 || maddr == 2)
+				maddr = get_copper_address (maddr);
+			else if (maddr == 0)
+				maddr = get_copper_address (-1);
+		} else
+			maddr = nxcopper;
+
+		if (more_params (c))
+			lines = readhex (c);
+		else
+			lines = 20;
+
+		nxcopper = decode_copperlist (stdout, maddr, lines);
+	}
+	return 0;
+}
+
+#define MAX_CHEAT_VIEW 100
+struct trainerstruct {
+	uaecptr addr;
+	int size;
+};
+
+static struct trainerstruct *trainerdata;
+static int totaltrainers;
+
+static void clearcheater(void)
+{
+	if (!trainerdata)
+		trainerdata =  xmalloc(struct trainerstruct, MAX_CHEAT_VIEW);
+	memset(trainerdata, 0, sizeof (struct trainerstruct) * MAX_CHEAT_VIEW);
+	totaltrainers = 0;
+}
+static int addcheater(uaecptr addr, int size)
+{
+	if (totaltrainers >= MAX_CHEAT_VIEW)
+		return 0;
+	trainerdata[totaltrainers].addr = addr;
+	trainerdata[totaltrainers].size = size;
+	totaltrainers++;
+	return 1;
+}
+static void listcheater(int mode, int size)
+{
+	int i, skip;
+
+	if (!trainerdata)
+		return;
+	if (mode)
+		skip = 6;
+	else
+		skip = 8;
+	for(i = 0; i < totaltrainers; i++) {
+		struct trainerstruct *ts = &trainerdata[i];
+		uae_u16 b;
+
+		if (size) {
+			b = get_byte_debug (ts->addr);
+		} else {
+			b = get_word_debug (ts->addr);
+		}
+		if (mode)
+			console_out_f (_T("%08X=%04X "), ts->addr, b);
+		else
+			console_out_f (_T("%08X "), ts->addr);
+		if ((i % skip) == skip)
+			console_out (_T("\n"));
+	}
+}
+
+static void deepcheatsearch (TCHAR **c)
+{
+	static int first = 1;
+	static uae_u8 *memtmp;
+	static int memsize, memsize2;
+	uae_u8 *p1, *p2;
+	uaecptr addr, end;
+	int i, wasmodified, nonmodified;
+	static int size;
+	static int inconly, deconly, maxdiff;
+	int addrcnt, cnt;
+	TCHAR v;
+
+	v = _totupper (**c);
+
+	if(!memtmp || v == 'S') {
+		maxdiff = 0x10000;
+		inconly = 0;
+		deconly = 0;
+		size = 1;
+	}
+
+	if (**c)
+		(*c)++;
+	ignore_ws (c);
+	if ((**c) == '1' || (**c) == '2') {
+		size = **c - '0';
+		(*c)++;
+	}
+	if (more_params (c))
+		maxdiff = readint (c);
+
+	if (!memtmp || v == 'S') {
+		first = 1;
+		xfree (memtmp);
+		memsize = 0;
+		addr = 0xffffffff;
+		while ((addr = nextaddr (addr, 0, &end)) != 0xffffffff)  {
+			memsize += end - addr;
+			addr = end - 1;
+		}
+		memsize2 = (memsize + 7) / 8;
+		memtmp = xmalloc (uae_u8, memsize + memsize2);
+		if (!memtmp)
+			return;
+		memset (memtmp + memsize, 0xff, memsize2);
+		p1 = memtmp;
+		addr = 0xffffffff;
+		while ((addr = nextaddr (addr, 0, &end)) != 0xffffffff) {
+			for (i = addr; i < end; i++)
+				*p1++ = get_byte_debug (i);
+			addr = end - 1;
+		}
+		console_out (_T("Deep trainer first pass complete.\n"));
+		return;
+	}
+	inconly = deconly = 0;
+	wasmodified = v == 'X' ? 0 : 1;
+	nonmodified = v == 'Z' ? 1 : 0;
+	if (v == 'I')
+		inconly = 1;
+	if (v == 'D')
+		deconly = 1;
+	p1 = memtmp;
+	p2 = memtmp + memsize;
+	addrcnt = 0;
+	cnt = 0;
+	addr = 0xffffffff;
+	while ((addr = nextaddr (addr, 0, NULL)) != 0xffffffff) {
+		uae_s32 b, b2;
+		int doremove = 0;
+		int addroff = addrcnt >> 3;
+		int addrmask ;
+
+		if (size == 1) {
+			b = (uae_s8)get_byte_debug (addr);
+			b2 = (uae_s8)p1[addrcnt];
+			addrmask = 1 << (addrcnt & 7);
+		} else {
+			b = (uae_s16)get_word_debug (addr);
+			b2 = (uae_s16)((p1[addrcnt] << 8) | p1[addrcnt + 1]);
+			addrmask = 3 << (addrcnt & 7);
+		}
+
+		if (p2[addroff] & addrmask) {
+			if (wasmodified && !nonmodified) {
+				int diff = b - b2;
+				if (b == b2)
+					doremove = 1;
+				if (abs(diff) > maxdiff)
+					doremove = 1;
+				if (inconly && diff < 0)
+					doremove = 1;
+				if (deconly && diff > 0)
+					doremove = 1;
+			} else if (nonmodified && b == b2) {
+				doremove = 1;
+			} else if (!wasmodified && b != b2) {
+				doremove = 1;
+			}
+			if (doremove)
+				p2[addroff] &= ~addrmask;
+			else
+				cnt++;
+		}
+		if (size == 1) {
+			p1[addrcnt] = b;
+			addrcnt++;
+		} else {
+			p1[addrcnt] = b >> 8;
+			p1[addrcnt + 1] = b >> 0;
+			addr = nextaddr (addr, 0, NULL);
+			if (addr == 0xffffffff)
+				break;
+			addrcnt += 2;
+		}
+		if  (iscancel (65536)) {
+			console_out_f (_T("Aborted at %08X\n"), addr);
+			break;
+		}
+	}
+
+	console_out_f (_T("%d addresses found\n"), cnt);
+	if (cnt <= MAX_CHEAT_VIEW) {
+		clearcheater ();
+		cnt = 0;
+		addrcnt = 0;
+		addr = 0xffffffff;
+		while ((addr = nextaddr(addr, 0, NULL)) != 0xffffffff) {
+			int addroff = addrcnt >> 3;
+			int addrmask = (size == 1 ? 1 : 3) << (addrcnt & 7);
+			if (p2[addroff] & addrmask)
+				addcheater (addr, size);
+			addrcnt += size;
+			cnt++;
+		}
+		if (cnt > 0)
+			console_out (_T("\n"));
+		listcheater (1, size);
+	} else {
+		console_out (_T("Now continue with 'g' and use 'D' again after you have lost another life\n"));
+	}
+}
+
+/* cheat-search by Toni Wilen (originally by Holger Jakob) */
+static void cheatsearch (TCHAR **c)
+{
+	static uae_u8 *vlist;
+	static int listsize;
+	static int first = 1;
+	static int size = 1;
+	uae_u32 val, memcnt, prevmemcnt;
+	int i, count, vcnt, memsize;
+	uaecptr addr, end;
+
+	memsize = 0;
+	addr = 0xffffffff;
+	while ((addr = nextaddr (addr, 0, &end)) != 0xffffffff)  {
+		memsize += end - addr;
+		addr = end - 1;
+	}
+
+	if (_totupper (**c) == 'L') {
+		listcheater (1, size);
+		return;
+	}
+	ignore_ws (c);
+	if (!more_params (c)) {
+		first = 1;
+		console_out (_T("Search reset\n"));
+		xfree (vlist);
+		listsize = memsize;
+		vlist = xcalloc (uae_u8, listsize >> 3);
+		return;
+	}
+	if (first)
+		val = readint (c, &size);
+	else
+		val = readint (c);
+
+	if (vlist == NULL) {
+		listsize = memsize;
+		vlist = xcalloc (uae_u8, listsize >> 3);
+	}
+
+	count = 0;
+	vcnt = 0;
+
+	clearcheater ();
+	addr = 0xffffffff;
+	prevmemcnt = memcnt = 0;
+	while ((addr = nextaddr (addr, 0, &end)) != 0xffffffff) {
+		if (addr + size < end) {
+			for (i = 0; i < size; i++) {
+				int shift = (size - i - 1) * 8;
+				if (get_byte_debug (addr + i) != ((val >> shift) & 0xff))
+					break;
+			}
+			if (i == size) {
+				int voffset = memcnt >> 3;
+				int vmask = 1 << (memcnt & 7);
+				if (!first) {
+					while (prevmemcnt < memcnt) {
+						vlist[prevmemcnt >> 3] &= ~(1 << (prevmemcnt & 7));
+						prevmemcnt++;
+					}
+					if (vlist[voffset] & vmask) {
+						count++;
+						addcheater(addr, size);
+					} else {
+						vlist[voffset] &= ~vmask;
+					}
+					prevmemcnt = memcnt + 1;
+				} else {
+					vlist[voffset] |= vmask;
+					count++;
+				}
+			}
+		}
+		memcnt++;
+		if  (iscancel (65536)) {
+			console_out_f (_T("Aborted at %08X\n"), addr);
+			break;
+		}
+	}
+	if (!first) {
+		while (prevmemcnt < memcnt) {
+			vlist[prevmemcnt >> 3] &= ~(1 << (prevmemcnt & 7));
+			prevmemcnt++;
+		}
+		listcheater (0, size);
+	}
+	console_out_f (_T("Found %d possible addresses with 0x%X (%u) (%d bytes)\n"), count, val, val, size);
+	if (count > 0)
+		console_out (_T("Now continue with 'g' and use 'C' with a different value\n"));
+	first = 0;
+}
+
+struct breakpoint_node bpnodes[BREAKPOINT_TOTAL];
+static addrbank **debug_mem_banks;
+static addrbank *debug_mem_area;
+struct memwatch_node mwnodes[MEMWATCH_TOTAL];
+static struct memwatch_node mwhit;
+static int addressspaceheatmap;
+
+static uae_u8 *illgdebug, *illghdebug;
+static int illgdebug_break;
+
+static void illg_free (void)
+{
+	xfree (illgdebug);
+	illgdebug = NULL;
+	xfree (illghdebug);
+	illghdebug = NULL;
+}
+
+static void illg_init (void)
+{
+	int i;
+	uae_u8 c = 3;
+	uaecptr addr, end;
+
+	illgdebug = xcalloc (uae_u8, 0x01000000);
+	illghdebug = xcalloc (uae_u8, 65536);
+	if (!illgdebug || !illghdebug) {
+		illg_free();
+		return;
+	}
+	addr = 0xffffffff;
+	while ((addr = nextaddr (addr, 0, &end)) != 0xffffffff)  {
+		if (end < 0x01000000) {
+			memset (illgdebug + addr, c, end - addr);
+		} else {
+			uae_u32 s = addr >> 16;
+			uae_u32 e = end >> 16;
+			memset (illghdebug + s, c, e - s);
+		}
+		addr = end - 1;
+	}
+	if (currprefs.rtgmem_size)
+		memset (illghdebug + (gfxmem_bank.start >> 16), 3, currprefs.rtgmem_size >> 16);
+
+	i = 0;
+	while (custd[i].name) {
+		int rw = custd[i].rw;
+		illgdebug[custd[i].adr] = rw;
+		illgdebug[custd[i].adr + 1] = rw;
+		i++;
+	}
+	for (i = 0; i < 16; i++) { /* CIAs */
+		if (i == 11)
+			continue;
+		illgdebug[0xbfe001 + i * 0x100] = c;
+		illgdebug[0xbfd000 + i * 0x100] = c;
+	}
+	memset (illgdebug + 0xf80000, 1, 512 * 1024); /* KS ROM */
+	memset (illgdebug + 0xdc0000, c, 0x3f); /* clock */
+#ifdef CDTV
+	if (currprefs.cs_cdtvram) {
+		memset (illgdebug + 0xdc8000, c, 4096); /* CDTV batt RAM */
+		memset (illgdebug + 0xf00000, 1, 256 * 1024); /* CDTV ext ROM */
+	}
+#endif
+#ifdef CD32
+	if (currprefs.cs_cd32cd) {
+		memset (illgdebug + AKIKO_BASE, c, AKIKO_BASE_END - AKIKO_BASE);
+		memset (illgdebug + 0xe00000, 1, 512 * 1024); /* CD32 ext ROM */
+	}
+#endif
+	if (currprefs.cs_ksmirror_e0)
+		memset (illgdebug + 0xe00000, 1, 512 * 1024);
+	if (currprefs.cs_ksmirror_a8)
+		memset (illgdebug + 0xa80000, 1, 2 * 512 * 1024);
+#ifdef FILESYS
+	if (uae_boot_rom_type) /* filesys "rom" */
+		memset (illgdebug + rtarea_base, 1, 0x10000);
+#endif
+	if (currprefs.cs_ide > 0)
+		memset (illgdebug + 0xdd0000, 3, 65536);
+}
+
+/* add special custom register check here */
+static void illg_debug_check (uaecptr addr, int rwi, int size, uae_u32 val)
+{
+	return;
+}
+
+static void illg_debug_do (uaecptr addr, int rwi, int size, uae_u32 val)
+{
+	uae_u8 mask;
+	uae_u32 pc = m68k_getpc ();
+	int i;
+
+	for (i = size - 1; i >= 0; i--) {
+		uae_u8 v = val >> (i * 8);
+		uae_u32 ad = addr + i;
+		if (ad >= 0x01000000)
+			mask = illghdebug[ad >> 16];
+		else
+			mask = illgdebug[ad];
+		if ((mask & 3) == 3)
+			return;
+		if (mask & 0x80) {
+			illg_debug_check (ad, rwi, size, val);
+		} else if ((mask & 3) == 0) {
+			if (rwi & 2)
+				console_out_f (_T("W: %08X=%02X PC=%08X\n"), ad, v, pc);
+			else if (rwi & 1)
+				console_out_f (_T("R: %08X    PC=%08X\n"), ad, pc);
+			if (illgdebug_break)
+				activate_debugger ();
+		} else if (!(mask & 1) && (rwi & 1)) {
+			console_out_f (_T("RO: %08X=%02X PC=%08X\n"), ad, v, pc);
+			if (illgdebug_break)
+				activate_debugger ();
+		} else if (!(mask & 2) && (rwi & 2)) {
+			console_out_f (_T("WO: %08X    PC=%08X\n"), ad, pc);
+			if (illgdebug_break)
+				activate_debugger ();
+		}
+	}
+}
+
+static int debug_mem_off (uaecptr *addrp)
+{
+	uaecptr addr = *addrp;
+	addrbank *ba;
+	int offset = munge24 (addr) >> 16;
+	if (!debug_mem_banks)
+		return offset;
+	ba = debug_mem_banks[offset];
+	if (!ba)
+		return offset;
+	if (ba->mask || ba->startmask)
+		addr = (addr & ba->mask) | ba->startmask;
+	*addrp = addr;
+	return offset;
+}
+
+struct smc_item {
+	uae_u32 addr;
+	uae_u8 cnt;
+};
+
+static int smc_size, smc_mode;
+static struct smc_item *smc_table;
+
+static void smc_free (void)
+{
+	if (smc_table)
+		console_out (_T("SMCD disabled\n"));
+	xfree(smc_table);
+	smc_mode = 0;
+	smc_table = NULL;
+}
+
+static void initialize_memwatch (int mode);
+static void smc_detect_init (TCHAR **c)
+{
+	int v, i;
+
+	ignore_ws (c);
+	v = readint (c);
+	smc_free ();
+	smc_size = 1 << 24;
+	if (currprefs.z3fastmem_size)
+		smc_size = currprefs.z3autoconfig_start + currprefs.z3fastmem_size;
+	smc_size += 4;
+	smc_table = xmalloc (struct smc_item, smc_size);
+	if (!smc_table)
+		return;
+	for (i = 0; i < smc_size; i++) {
+		smc_table[i].addr = 0xffffffff;
+		smc_table[i].cnt = 0;
+	}
+	if (!memwatch_enabled)
+		initialize_memwatch (0);
+	if (v)
+		smc_mode = 1;
+	console_out_f (_T("SMCD enabled. Break=%d\n"), smc_mode);
+}
+
+#define SMC_MAXHITS 8
+static void smc_detector (uaecptr addr, int rwi, int size, uae_u32 *valp)
+{
+	int i, hitcnt;
+	uaecptr hitaddr, hitpc;
+
+	if (!smc_table)
+		return;
+	if (addr >= smc_size)
+		return;
+	if (rwi == 2) {
+		for (i = 0; i < size; i++) {
+			if (smc_table[addr + i].cnt < SMC_MAXHITS) {
+				smc_table[addr + i].addr = m68k_getpc ();
+			}
+		}
+		return;
+	}
+	hitpc = smc_table[addr].addr;
+	if (hitpc == 0xffffffff)
+		return;
+	hitaddr = addr;
+	hitcnt = 0;
+	while (addr < smc_size && smc_table[addr].addr != 0xffffffff) {
+		smc_table[addr++].addr = 0xffffffff;
+		hitcnt++;
+	}
+	if ((hitpc & 0xFFF80000) == 0xF80000)
+		return;
+	if (currprefs.cpu_model == 68000 && currprefs.cpu_compatible) {
+		/* ignore single-word unconditional jump instructions
+		* (instruction prefetch from PC+2 can cause false positives) */
+		if (regs.irc == 0x4e75 || regs.irc == 4e74 || regs.irc == 0x4e72 || regs.irc == 0x4e77)
+			return; /* RTS, RTD, RTE, RTR */
+		if ((regs.irc & 0xff00) == 0x6000 && (regs.irc & 0x00ff) != 0 && (regs.irc & 0x00ff) != 0xff)
+			return; /* BRA.B */
+	}
+	if (hitcnt < 100) {
+		smc_table[hitaddr].cnt++;
+		console_out_f (_T("SMC at %08X - %08X (%d) from %08X\n"),
+			hitaddr, hitaddr + hitcnt, hitcnt, hitpc);
+		if (smc_mode)
+			activate_debugger ();
+		if (smc_table[hitaddr].cnt >= SMC_MAXHITS)
+			console_out_f (_T("* hit count >= %d, future hits ignored\n"), SMC_MAXHITS);
+	}
+}
+
+uae_u8 *save_debug_memwatch (int *len, uae_u8 *dstptr)
+{
+	uae_u8 *dstbak, *dst;
+	int total;
+
+	total = 0;
+	for (int i = 0; i < MEMWATCH_TOTAL; i++) {
+		if (mwnodes[i].size > 0)
+			total++;
+	}
+	if (!total)
+		return NULL;
+
+	if (dstptr)
+		dstbak = dst = dstptr;
+	else
+		dstbak = dst = xmalloc (uae_u8, 1000);
+	save_u32 (1);
+	save_u8 (total);
+	for (int i = 0; i < MEMWATCH_TOTAL; i++) {
+		struct memwatch_node *m = &mwnodes[i];
+		if (m->size <= 0)
+			continue;
+		save_store_pos ();
+		save_u8 (i);
+		save_u8 (m->modval_written);
+		save_u8 (m->mustchange);
+		save_u8 (m->frozen);
+		save_u8 (m->val_enabled);
+		save_u8 (m->rwi);
+		save_u32 (m->addr);
+		save_u32 (m->size);
+		save_u32 (m->modval);
+		save_u32 (m->val_mask);
+		save_u32 (m->val_size);
+		save_u32 (m->val);
+		save_u32 (m->pc);
+		save_u32 (m->access_mask);
+		save_u32 (m->reg);
+		save_store_size ();
+	}
+	*len = dst - dstbak;
+	return dstbak;
+}
+
+uae_u8 *restore_debug_memwatch (uae_u8 *src)
+{
+	if (restore_u32 () != 1)
+		return src;
+	int total = restore_u8 ();
+	for (int i = 0; i < total; i++) {
+		restore_store_pos ();
+		int idx = restore_u8 ();
+		struct memwatch_node *m = &mwnodes[idx];
+		m->modval_written = restore_u8 ();
+		m->mustchange = restore_u8 ();
+		m->frozen = restore_u8 ();
+		m->val_enabled = restore_u8 ();
+		m->rwi = restore_u8 ();
+		m->addr = restore_u32 ();
+		m->size = restore_u32 ();
+		m->modval = restore_u32 ();
+		m->val_mask = restore_u32 ();
+		m->val_size = restore_u32 ();
+		m->val = restore_u32 ();
+		m->pc = restore_u32 ();
+		m->access_mask = restore_u32();
+		m->reg = restore_u32();
+		restore_store_size ();
+	}
+	return src;
+}
+
+void restore_debug_memwatch_finish (void)
+{
+	for (int i = 0; i < MEMWATCH_TOTAL; i++) {
+		struct memwatch_node *m = &mwnodes[i];
+		if (m->size) {
+			if (!memwatch_enabled)
+				initialize_memwatch (0);
+			return;
+		}
+	}
+}
+
+static int memwatch_func (uaecptr addr, int rwi, int size, uae_u32 *valp, uae_u32 accessmask, uae_u32 reg)
+{
+	int i, brk;
+	uae_u32 val = *valp;
+
+	if (illgdebug)
+		illg_debug_do (addr, rwi, size, val);
+
+	if (addressspaceheatmap)
+		memwatch_heatmap (addr, rwi, size);
+
+	addr = munge24 (addr);
+	if (smc_table && (rwi >= 2))
+		smc_detector (addr, rwi, size, valp);
+	for (i = 0; i < MEMWATCH_TOTAL; i++) {
+		struct memwatch_node *m = &mwnodes[i];
+		uaecptr addr2 = m->addr;
+		uaecptr addr3 = addr2 + m->size;
+		int rwi2 = m->rwi;
+		uae_u32 oldval = 0;
+		int isoldval = 0;
+
+		brk = 0;
+		if (m->size == 0)
+			continue;
+		if (!(rwi & rwi2))
+			continue;
+		if (!(m->access_mask & accessmask))
+			continue;
+
+		if (addr >= addr2 && addr < addr3)
+			brk = 1;
+		if (!brk && size == 2 && (addr + 1 >= addr2 && addr + 1 < addr3))
+			brk = 1;
+		if (!brk && size == 4 && ((addr + 2 >= addr2 && addr + 2 < addr3) || (addr + 3 >= addr2 && addr + 3 < addr3)))
+			brk = 1;
+
+		if (!brk)
+			continue;
+		if (mem_banks[addr >> 16]->check (addr, size)) {
+			uae_u8 *p = mem_banks[addr >> 16]->xlateaddr (addr);
+			if (size == 1)
+				oldval = p[0];
+			else if (size == 2)
+				oldval = (p[0] << 8) | p[1];
+			else
+				oldval = (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | (p[3] << 0);
+			isoldval = 1;
+		}
+
+		if (!m->frozen && m->val_enabled) {
+			int trigger = 0;
+			uae_u32 mask = m->size == 4 ? 0xffffffff : (1 << (m->size * 8)) - 1;
+			uae_u32 mval = m->val;
+			int scnt = size;
+			for (;;) {
+				if (((mval & mask) & m->val_mask) == ((val & mask) & m->val_mask))
+					trigger = 1;
+				if (mask & 0x80000000)
+					break;
+				if (m->size == 1) {
+					mask <<= 8;
+					mval <<= 8;
+					scnt--;
+				} else if (m->size == 2) {
+					mask <<= 16;
+					scnt -= 2;
+					mval <<= 16;
+				} else {
+					scnt -= 4;
+				}
+				if (scnt <= 0)
+					break;
+			}
+			if (!trigger)
+				continue;
+		}
+
+		if (m->mustchange && rwi == 2 && isoldval) {
+			if (oldval == *valp)
+				continue;
+		}
+
+		if (m->modval_written) {
+			if (!rwi) {
+				brk = 0;
+			} else if (m->modval_written == 1) {
+				m->modval_written = 2;
+				m->modval = val;
+				brk = 0;
+			} else if (m->modval == val) {
+				brk = 0;
+			}
+		}
+		if (m->frozen) {
+			if (m->val_enabled) {
+				int shift = (addr + size - 1) - (m->addr + m->val_size - 1);
+				uae_u32 sval;
+				uae_u32 mask;
+
+				if (m->val_size == 4)
+					mask = 0xffffffff;
+				else if (m->val_size == 2)
+					mask = 0x0000ffff;
+				else
+					mask = 0x000000ff;
+
+				sval = m->val;
+				if (shift < 0) {
+					shift = -8 * shift;
+					sval >>= shift;
+					mask >>= shift;
+				} else {
+					shift = 8 * shift;
+					sval <<= shift;
+					mask <<= shift;
+				}
+				*valp = (sval & mask) | ((*valp) & ~mask);
+				write_log (_T("%p %p %08x %08x %d\n"), addr, m->addr, *valp, mask, shift);
+				return 1;
+			}
+			return 0;
+		}
+		//	if (!notinrom ())
+		//	    return 1;
+		mwhit.pc = M68K_GETPC;
+		mwhit.addr = addr;
+		mwhit.rwi = rwi;
+		mwhit.size = size;
+		mwhit.val = 0;
+		mwhit.access_mask = accessmask;
+		mwhit.reg = reg;
+		if (mwhit.rwi & 2)
+			mwhit.val = val;
+		memwatch_triggered = i + 1;
+		debugging = 1;
+		set_special (SPCFLAG_BRK);
+		return 1;
+	}
+	return 1;
+}
+
+#endif	/* WINUAE_FOR_HATARI */
+#if 0
+
+static int mmu_hit (uaecptr addr, int size, int rwi, uae_u32 *v);
+
+static uae_u32 REGPARAM2 mmu_lget (uaecptr addr)
+{
+	int off = debug_mem_off (&addr);
+	uae_u32 v = 0;
+	if (!mmu_hit (addr, 4, 0, &v))
+		v = debug_mem_banks[off]->lget (addr);
+	return v;
+}
+static uae_u32 REGPARAM2 mmu_wget (uaecptr addr)
+{
+	int off = debug_mem_off (&addr);
+	uae_u32 v = 0;
+	if (!mmu_hit (addr, 2, 0, &v))
+		v = debug_mem_banks[off]->wget (addr);
+	return v;
+}
+static uae_u32 REGPARAM2 mmu_bget (uaecptr addr)
+{
+	int off = debug_mem_off (&addr);
+	uae_u32 v = 0;
+	if (!mmu_hit(addr, 1, 0, &v))
+		v = debug_mem_banks[off]->bget (addr);
+	return v;
+}
+static void REGPARAM2 mmu_lput (uaecptr addr, uae_u32 v)
+{
+	int off = debug_mem_off (&addr);
+	if (!mmu_hit (addr, 4, 1, &v))
+		debug_mem_banks[off]->lput (addr, v);
+}
+static void REGPARAM2 mmu_wput (uaecptr addr, uae_u32 v)
+{
+	int off = debug_mem_off (&addr);
+	if (!mmu_hit (addr, 2, 1, &v))
+		debug_mem_banks[off]->wput (addr, v);
+}
+static void REGPARAM2 mmu_bput (uaecptr addr, uae_u32 v)
+{
+	int off = debug_mem_off (&addr);
+	if (!mmu_hit (addr, 1, 1, &v))
+		debug_mem_banks[off]->bput (addr, v);
+}
+
+static uae_u32 REGPARAM2 debug_lget (uaecptr addr)
+{
+	uae_u32 off = debug_mem_off (&addr);
+	uae_u32 v;
+	v = debug_mem_banks[off]->lget (addr);
+	memwatch_func (addr, 1, 4, &v, MW_MASK_CPU, 0);
+	return v;
+}
+static uae_u32 REGPARAM2 mmu_lgeti (uaecptr addr)
+{
+	int off = debug_mem_off (&addr);
+	uae_u32 v = 0;
+	if (!mmu_hit (addr, 4, 4, &v))
+		v = debug_mem_banks[off]->lgeti (addr);
+	return v;
+}
+static uae_u32 REGPARAM2 mmu_wgeti (uaecptr addr)
+{
+	int off = debug_mem_off (&addr);
+	uae_u32 v = 0;
+	if (!mmu_hit (addr, 2, 4, &v))
+		v = debug_mem_banks[off]->wgeti (addr);
+	return v;
+}
+
+static uae_u32 REGPARAM2 debug_wget (uaecptr addr)
+{
+	int off = debug_mem_off (&addr);
+	uae_u32 v;
+	v = debug_mem_banks[off]->wget (addr);
+	memwatch_func (addr, 1, 2, &v, MW_MASK_CPU, 0);
+	return v;
+}
+static uae_u32 REGPARAM2 debug_bget (uaecptr addr)
+{
+	int off = debug_mem_off (&addr);
+	uae_u32 v;
+	v = debug_mem_banks[off]->bget (addr);
+	memwatch_func (addr, 1, 1, &v, MW_MASK_CPU, 0);
+	return v;
+}
+static uae_u32 REGPARAM2 debug_lgeti (uaecptr addr)
+{
+	int off = debug_mem_off (&addr);
+	uae_u32 v;
+	v = debug_mem_banks[off]->lgeti (addr);
+	memwatch_func (addr, 4, 4, &v, MW_MASK_CPU, 0);
+	return v;
+}
+static uae_u32 REGPARAM2 debug_wgeti (uaecptr addr)
+{
+	int off = debug_mem_off (&addr);
+	uae_u32 v;
+	v = debug_mem_banks[off]->wgeti (addr);
+	memwatch_func (addr, 4, 2, &v, MW_MASK_CPU, 0);
+	return v;
+}
+static void REGPARAM2 debug_lput (uaecptr addr, uae_u32 v)
+{
+	int off = debug_mem_off (&addr);
+	if (memwatch_func (addr, 2, 4, &v, MW_MASK_CPU, 0))
+		debug_mem_banks[off]->lput (addr, v);
+}
+static void REGPARAM2 debug_wput (uaecptr addr, uae_u32 v)
+{
+	int off = debug_mem_off (&addr);
+	if (memwatch_func (addr, 2, 2, &v, MW_MASK_CPU, 0))
+		debug_mem_banks[off]->wput (addr, v);
+}
+static void REGPARAM2 debug_bput (uaecptr addr, uae_u32 v)
+{
+	int off = debug_mem_off (&addr);
+	if (memwatch_func (addr, 2, 1, &v, MW_MASK_CPU, 0))
+		debug_mem_banks[off]->bput (addr, v);
+}
+static int REGPARAM2 debug_check (uaecptr addr, uae_u32 size)
+{
+	return debug_mem_banks[munge24 (addr) >> 16]->check (addr, size);
+}
+static uae_u8 *REGPARAM2 debug_xlate (uaecptr addr)
+{
+	return debug_mem_banks[munge24 (addr) >> 16]->xlateaddr (addr);
+}
+
+uae_u16 debug_wputpeekdma_chipset (uaecptr addr, uae_u32 v, uae_u32 mask, int reg)
+{
+	if (!memwatch_enabled)
+		return v;
+	addr &= 0x1fe;
+	addr += 0xdff000;
+	memwatch_func (addr, 2, 2, &v, mask, reg);
+	return v;
+}
+uae_u16 debug_wputpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int reg)
+{
+	if (!memwatch_enabled)
+		return v;
+	if (debug_mem_banks[addr >> 16] == NULL)
+		return v;
+	if (!currprefs.z3chipmem_size)
+		addr &= chipmem_bank.mask;
+	memwatch_func (addr & chipmem_bank.mask, 2, 2, &v, mask, reg);
+	return v;
+}
+uae_u16 debug_wgetpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int reg)
+{
+	uae_u32 vv = v;
+	if (!memwatch_enabled)
+		return v;
+	if (debug_mem_banks[addr >> 16] == NULL)
+		return v;
+	if (!currprefs.z3chipmem_size)
+		addr &= chipmem_bank.mask;
+	memwatch_func (addr, 1, 2, &vv, mask, reg);
+	return vv;
+}
+
+void debug_putlpeek (uaecptr addr, uae_u32 v)
+{
+	if (!memwatch_enabled)
+		return;
+	memwatch_func (addr, 2, 4, &v, MW_MASK_CPU, 0);
+}
+void debug_wputpeek (uaecptr addr, uae_u32 v)
+{
+	if (!memwatch_enabled)
+		return;
+	memwatch_func (addr, 2, 2, &v, MW_MASK_CPU, 0);
+}
+void debug_bputpeek (uaecptr addr, uae_u32 v)
+{
+	if (!memwatch_enabled)
+		return;
+	memwatch_func (addr, 2, 1, &v, MW_MASK_CPU, 0);
+}
+void debug_bgetpeek (uaecptr addr, uae_u32 v)
+{
+	uae_u32 vv = v;
+	if (!memwatch_enabled)
+		return;
+	memwatch_func (addr, 1, 1, &vv, MW_MASK_CPU, 0);
+}
+void debug_wgetpeek (uaecptr addr, uae_u32 v)
+{
+	uae_u32 vv = v;
+	if (!memwatch_enabled)
+		return;
+	memwatch_func (addr, 1, 2, &vv, MW_MASK_CPU, 0);
+}
+void debug_lgetpeek (uaecptr addr, uae_u32 v)
+{
+	uae_u32 vv = v;
+	if (!memwatch_enabled)
+		return;
+	memwatch_func (addr, 1, 4, &vv, MW_MASK_CPU, 0);
+}
+
+#ifndef WINUAE_FOR_HATARI
+
+struct membank_store
+{
+	addrbank *addr;
+	addrbank newbank;
+	int banknr;
+};
+
+static struct membank_store *membank_stores;
+static int membank_total;
+#define MEMWATCH_STORE_SLOTS 32
+
+static void memwatch_reset (void)
+{
+	for (int i = 0; i < membank_total; i++) {
+		addrbank *ab = debug_mem_banks[i];
+		if (!ab)
+			continue;
+		map_banks_quick (ab, i, 1, 1);
+	}
+	for (int i = 0; membank_stores[i].addr; i++) {
+		struct membank_store *ms = &membank_stores[i];
+		xfree ((char*)ms->newbank.name);
+		memset (ms, 0, sizeof (struct membank_store));
+		ms->addr = NULL;
+	}
+	memset (debug_mem_banks, 0, membank_total * sizeof (addrbank*));
+}
+
+static void memwatch_remap (uaecptr addr)
+{
+	int mode = 0;
+	int i;
+	int banknr;
+	struct membank_store *ms;
+	addrbank *bank;
+	addrbank *newbank = NULL;
+
+	addr &= ~65535;
+	banknr = addr >> 16;
+	if (debug_mem_banks[banknr])
+		return;
+	bank = mem_banks[banknr];
+	for (i = 0 ; i < MEMWATCH_STORE_SLOTS; i++) {
+		ms = &membank_stores[i];
+		if (ms->addr == NULL)
+			break;
+		if (ms->addr == bank) {
+			newbank = &ms->newbank;
+			break;
+		}
+	}
+	if (i >= MEMWATCH_STORE_SLOTS)
+		return;
+	if (!newbank) {
+		TCHAR tmp[200];
+		_stprintf (tmp, _T("%s [D]"), bank->name);
+		ms->addr = bank;
+		ms->banknr = banknr;
+		newbank = &ms->newbank;
+		memcpy (newbank, bank, sizeof addrbank);
+		newbank->bget = mode ? mmu_bget : debug_bget;
+		newbank->wget = mode ? mmu_wget : debug_wget;
+		newbank->lget = mode ? mmu_lget : debug_lget;
+		newbank->bput = mode ? mmu_bput : debug_bput;
+		newbank->wput = mode ? mmu_wput : debug_wput;
+		newbank->lput = mode ? mmu_lput : debug_lput;
+		newbank->check = debug_check;
+		newbank->xlateaddr = debug_xlate;
+		newbank->wgeti = mode ? mmu_wgeti : debug_wgeti;
+		newbank->lgeti = mode ? mmu_lgeti : debug_lgeti;
+		newbank->name = my_strdup (tmp);
+		if (!newbank->mask)
+			newbank->mask = -1;
+	}
+	debug_mem_banks[banknr] = bank;
+	map_banks_quick (newbank, banknr, 1, 1);
+	// map aliases
+	for (i = 0; i < membank_total; i++) {
+		uaecptr addr2 = i << 16;
+		addrbank *ab = &get_mem_bank(addr2);
+		if (ab != ms->addr)
+			continue;
+		if ((addr2 & ab->mask) == (addr & bank->mask)) {
+			debug_mem_banks[i] = ms->addr;
+			map_banks_quick (newbank, i, 1, 1);
+		}
+	}
+}
+
+static void memwatch_setup (void)
+{
+	memwatch_reset ();
+	for (int i = 0; i < MEMWATCH_TOTAL; i++) {
+		struct memwatch_node *m = &mwnodes[i];
+		uae_u32 size = 0;
+		if (!m->size)
+			continue;
+		while (size < m->size) {
+			memwatch_remap (m->addr + size);
+			size += 65536;
+		}
+	}
+}
+
+static int deinitialize_memwatch (void)
+{
+	int oldmode;
+
+	if (!memwatch_enabled && !mmu_enabled)
+		return -1;
+	memwatch_reset ();
+	oldmode = mmu_enabled ? 1 : 0;
+	xfree (debug_mem_banks);
+	debug_mem_banks = NULL;
+	xfree (debug_mem_area);
+	debug_mem_area = NULL;
+	xfree (membank_stores);
+	membank_stores = NULL;
+	memwatch_enabled = 0;
+	mmu_enabled = 0;
+	xfree (illgdebug);
+	illgdebug = 0;
+	return oldmode;
+}
+
+static void initialize_memwatch (int mode)
+{
+	membank_total = currprefs.address_space_24 ? 256 : 65536;
+	deinitialize_memwatch ();
+	debug_mem_banks = xcalloc (addrbank*, membank_total);
+	debug_mem_area = xcalloc (addrbank, membank_total);
+	membank_stores = xcalloc (struct membank_store, MEMWATCH_STORE_SLOTS);
+#if 0
+	int i, j, as;
+	addrbank *a1, *a2, *oa;
+	oa = NULL;
+	for (i = 0; i < as; i++) {
+		a1 = debug_mem_banks[i] = debug_mem_area + i;
+		a2 = mem_banks[i];
+		if (a2 != oa) {
+			for (j = 0; membank_stores[j].addr; j++) {
+				if (membank_stores[j].addr == a2)
+					break;
+			}
+			if (membank_stores[j].addr == NULL) {
+				membank_stores[j].addr = a2;
+				memcpy (&membank_stores[j].store, a2, sizeof (addrbank));
+			}
+		}
+		memcpy (a1, a2, sizeof (addrbank));
+	}
+	for (i = 0; i < as; i++) {
+		a2 = mem_banks[i];
+		a2->bget = mode ? mmu_bget : debug_bget;
+		a2->wget = mode ? mmu_wget : debug_wget;
+		a2->lget = mode ? mmu_lget : debug_lget;
+		a2->bput = mode ? mmu_bput : debug_bput;
+		a2->wput = mode ? mmu_wput : debug_wput;
+		a2->lput = mode ? mmu_lput : debug_lput;
+		a2->check = debug_check;
+		a2->xlateaddr = debug_xlate;
+		a2->wgeti = mode ? mmu_wgeti : debug_wgeti;
+		a2->lgeti = mode ? mmu_lgeti : debug_lgeti;
+	}
+#endif
+	if (mode)
+		mmu_enabled = 1;
+	else
+		memwatch_enabled = 1;
+}
+
+int debug_bankchange (int mode)
+{
+	if (mode == -1) {
+		int v = deinitialize_memwatch ();
+		if (v < 0)
+			return -2;
+		return v;
+	}
+	if (mode >= 0) {
+		initialize_memwatch (mode);
+		memwatch_setup ();
+	}
+	return -1;
+}
+
+addrbank *get_mem_bank_real(uaecptr addr)
+{
+	addrbank *ab = &get_mem_bank(addr);
+	if (!memwatch_enabled)
+		return ab;
+	addrbank *ab2 = debug_mem_banks[addr >> 16];
+	if (ab2)
+		return ab2;
+	return ab;
+}
+
+struct mw_acc
+{
+	uae_u32 mask;
+	const TCHAR *name;
+};
+
+static const struct mw_acc memwatch_access_masks[] =
+{
+	{ MW_MASK_ALL, _T("ALL") },
+	{ MW_MASK_ALL & ~MW_MASK_CPU, _T("DMA") },
+	{ MW_MASK_BLITTER_A | MW_MASK_BLITTER_B | MW_MASK_BLITTER_C | MW_MASK_BLITTER_D, _T("BLT") },
+	{ MW_MASK_AUDIO_0 | MW_MASK_AUDIO_1 | MW_MASK_AUDIO_2 | MW_MASK_AUDIO_3, _T("AUD") },
+	{ MW_MASK_BPL_0 | MW_MASK_BPL_1 | MW_MASK_BPL_2 | MW_MASK_BPL_3 | 
+	  MW_MASK_BPL_4 | MW_MASK_BPL_5 | MW_MASK_BPL_6 | MW_MASK_BPL_7 , _T("BPL") },
+	{ MW_MASK_SPR_0 | MW_MASK_SPR_1 | MW_MASK_SPR_2 | MW_MASK_SPR_3 |
+	  MW_MASK_SPR_4 | MW_MASK_SPR_5 | MW_MASK_SPR_6 | MW_MASK_SPR_7, _T("SPR") },
+	
+	{ MW_MASK_CPU, _T("CPU") },
+	{ MW_MASK_COPPER, _T("COP") },
+	{ MW_MASK_BLITTER_A, _T("BLTA") },
+	{ MW_MASK_BLITTER_B, _T("BLTB") },
+	{ MW_MASK_BLITTER_C, _T("BLTC") },
+	{ MW_MASK_BLITTER_D, _T("BLTD") },
+	{ MW_MASK_DISK, _T("DSK") },
+	{ MW_MASK_AUDIO_0, _T("AUD0") },
+	{ MW_MASK_AUDIO_1, _T("AUD1") },
+	{ MW_MASK_AUDIO_2, _T("AUD2") },
+	{ MW_MASK_AUDIO_3, _T("AUD3") },
+	{ MW_MASK_BPL_0, _T("BPL0") },
+	{ MW_MASK_BPL_1, _T("BPL1") },
+	{ MW_MASK_BPL_2, _T("BPL2") },
+	{ MW_MASK_BPL_3, _T("BPL3") },
+	{ MW_MASK_BPL_4, _T("BPL4") },
+	{ MW_MASK_BPL_5, _T("BPL5") },
+	{ MW_MASK_BPL_6, _T("BPL6") },
+	{ MW_MASK_BPL_7, _T("BPL7") },
+	{ MW_MASK_SPR_0, _T("SPR0") },
+	{ MW_MASK_SPR_1, _T("SPR1") },
+	{ MW_MASK_SPR_2, _T("SPR2") },
+	{ MW_MASK_SPR_3, _T("SPR3") },
+	{ MW_MASK_SPR_4, _T("SPR4") },
+	{ MW_MASK_SPR_5, _T("SPR5") },
+	{ MW_MASK_SPR_6, _T("SPR6") },
+	{ MW_MASK_SPR_7, _T("SPR7") },
+	NULL
+};
+
+static TCHAR *getsizechar (int size)
+{
+	if (size == 4)
+		return _T(".l");
+	if (size == 3)
+		return _T(".3");
+	if (size == 2)
+		return _T(".w");
+	if (size == 1)
+		return _T(".b");
+	return _T("");
+}
+
+void memwatch_dump2 (TCHAR *buf, int bufsize, int num)
+{
+	int i;
+	struct memwatch_node *mwn;
+
+	if (buf)
+		memset (buf, 0, bufsize * sizeof (TCHAR));
+	for (i = 0; i < MEMWATCH_TOTAL; i++) {
+		if ((num >= 0 && num == i) || (num < 0)) {
+			uae_u32 usedmask = 0;
+			mwn = &mwnodes[i];
+			if (mwn->size == 0)
+				continue;
+			buf = buf_out (buf, &bufsize, _T("%2d: %08X - %08X (%d) %c%c%c"),
+				i, mwn->addr, mwn->addr + (mwn->size - 1), mwn->size,
+				(mwn->rwi & 1) ? 'R' : ' ', (mwn->rwi & 2) ? 'W' : ' ', (mwn->rwi & 4) ? 'I' : ' ');
+			if (mwn->frozen)
+				buf = buf_out (buf, &bufsize, _T(" F"));
+			if (mwn->val_enabled)
+				buf = buf_out (buf, &bufsize, _T(" =%X%s"), mwn->val, getsizechar (mwn->val_size));
+			if (mwn->modval_written)
+				buf = buf_out (buf, &bufsize, _T(" =M"));
+			if (mwn->mustchange)
+				buf = buf_out (buf, &bufsize, _T(" C"));
+			for (int j = 0; memwatch_access_masks[j].mask; j++) {
+				uae_u32 mask = memwatch_access_masks[j].mask;
+				if ((mwn->access_mask & mask) == mask && (usedmask & mask) == 0) {
+					buf = buf_out(buf, &bufsize, _T(" "));
+					buf = buf_out(buf, &bufsize, memwatch_access_masks[j].name);
+					usedmask |= mask;
+				}
+			}
+			buf = buf_out (buf, &bufsize, _T("\n"));
+		}
+	}
+}
+
+static void memwatch_dump (int num)
+{
+	TCHAR *buf;
+	int multiplier = num < 0 ? MEMWATCH_TOTAL : 1;
+
+	buf = xmalloc (TCHAR, 50 * multiplier);
+	if (!buf)
+		return;
+	memwatch_dump2 (buf, 50 * multiplier, num);
+	f_out (stdout, _T("%s"), buf);
+	xfree (buf);
+}
+
+static void memwatch (TCHAR **c)
+{
+	int num;
+	struct memwatch_node *mwn;
+	TCHAR nc, *cp;
+
+	if (!memwatch_enabled) {
+		initialize_memwatch (0);
+		console_out (_T("Memwatch breakpoints enabled\n"));
+	}
+
+	cp = *c;
+	ignore_ws (c);
+	if (!more_params (c)) {
+		memwatch_dump (-1);
+		return;
+	}
+	nc = next_char (c);
+	if (nc == '-') {
+		deinitialize_memwatch ();
+		console_out (_T("Memwatch breakpoints disabled\n"));
+		return;
+	}
+	if (nc == 'd') {
+		if (illgdebug) {
+			ignore_ws (c);
+			if (more_params (c)) {
+				uae_u32 addr = readhex (c);
+				uae_u32 len = 1;
+				if (more_params (c))
+					len = readhex (c);
+				console_out_f (_T("Cleared logging addresses %08X - %08X\n"), addr, addr + len);
+				while (len > 0) {
+					addr &= 0xffffff;
+					illgdebug[addr] = 7;
+					addr++;
+					len--;
+				}
+			} else {
+				illg_free();
+				console_out (_T("Illegal memory access logging disabled\n"));
+			}
+		} else {
+			illg_init ();
+			ignore_ws (c);
+			illgdebug_break = 0;
+			if (more_params (c))
+				illgdebug_break = 1;
+			console_out_f (_T("Illegal memory access logging enabled. Break=%d\n"), illgdebug_break);
+		}
+		return;
+	}
+	*c = cp;
+	num = readint (c);
+	if (num < 0 || num >= MEMWATCH_TOTAL)
+		return;
+	mwn = &mwnodes[num];
+	mwn->size = 0;
+	ignore_ws (c);
+	if (!more_params (c)) {
+		console_out_f (_T("Memwatch %d removed\n"), num);
+		memwatch_setup ();
+		return;
+	}
+	mwn->addr = readhex (c);
+	mwn->size = 1;
+	mwn->rwi = 7;
+	mwn->val_enabled = 0;
+	mwn->val_mask = 0xffffffff;
+	mwn->val = 0;
+	mwn->access_mask = 0;
+	mwn->reg = 0xffffffff;
+	mwn->frozen = 0;
+	mwn->modval_written = 0;
+	ignore_ws (c);
+	if (more_params (c)) {
+		mwn->size = readhex (c);
+		ignore_ws (c);
+		if (more_params (c)) {
+			TCHAR *cs = *c;
+			while (*cs) {
+				for (int i = 0; memwatch_access_masks[i].mask; i++) {
+					const TCHAR *n = memwatch_access_masks[i].name;
+					int len = _tcslen(n);
+					if (!_tcsnicmp(cs, n, len)) {
+						if (cs[len] == 0 || cs[len] == 10 || cs[len] == 13) {
+							mwn->access_mask |= memwatch_access_masks[i].mask;
+							while (len > 0) {
+								len--;
+								cs[len] = ' ';
+							}
+						}
+					}
+				}
+				cs++;
+			}
+			ignore_ws (c);
+			if (more_params(c)) {
+				for (;;) {
+					TCHAR ncc = peek_next_char(c);
+					TCHAR nc = _totupper (next_char (c));
+					if (mwn->rwi == 7)
+						mwn->rwi = 0;
+					if (nc == 'F')
+						mwn->frozen = 1;
+					if (nc == 'W')
+						mwn->rwi |= 2;
+					if (nc == 'I')
+						mwn->rwi |= 4;
+					if (nc == 'R')
+						mwn->rwi |= 1;
+					if (ncc == ' ')
+						break;
+					if (!more_params(c))
+						break;
+				}
+				ignore_ws (c);
+			}
+			if (more_params (c)) {
+				if (_totupper (**c) == 'M') {
+					mwn->modval_written = 1;
+				} else if (_totupper (**c) == 'C') {
+					mwn->mustchange = 1;
+				} else {
+					mwn->val = readhex (c, &mwn->val_size);
+					mwn->val_enabled = 1;
+				}
+			}
+		}
+	}
+	if (!mwn->access_mask)
+		mwn->access_mask = MW_MASK_CPU;
+	if (mwn->frozen && mwn->rwi == 0)
+		mwn->rwi = 3;
+	memwatch_setup ();
+	memwatch_dump (num);
+}
+
+static void writeintomem (TCHAR **c)
+{
+	uae_u32 addr = 0;
+	uae_u32 val = 0;
+	TCHAR cc;
+	int len = 1;
+
+	ignore_ws(c);
+	addr = readhex (c);
+
+	ignore_ws (c);
+	if (!more_params (c))
+		return;
+	cc = peekchar (c);
+	if (cc == '\'' || cc == '\"') {
+		next_char (c);
+		while (more_params (c)) {
+			TCHAR str[2];
+			char *astr;
+			cc = next_char (c);
+			if (cc == '\'' || cc == '\"')
+				break;
+			str[0] = cc;
+			str[1] = 0;
+			astr = ua (str);
+			put_byte (addr, astr[0]);
+			xfree (astr);
+			addr++;
+		}
+	} else {
+		for (;;) {
+			ignore_ws (c);
+			if (!more_params (c))
+				break;
+			val = readhex (c, &len);
+		
+			if (len == 4) {
+				put_long (addr, val);
+				cc = 'L';
+			} else if (len == 2) {
+				put_word (addr, val);
+				cc = 'W';
+			} else if (len == 1) {
+				put_byte (addr, val);
+				cc = 'B';
+			} else {
+				break;
+			}
+			console_out_f (_T("Wrote %X (%u) at %08X.%c\n"), val, val, addr, cc);
+			addr += len;
+		}
+	}
+}
+
+static uae_u8 *dump_xlate (uae_u32 addr)
+{
+	if (!mem_banks[addr >> 16]->check (addr, 1))
+		return NULL;
+	return mem_banks[addr >> 16]->xlateaddr (addr);
+}
+
+#if 0
+#define UAE_MEMORY_REGIONS_MAX 64
+#define UAE_MEMORY_REGION_NAME_LENGTH 64
+
+#define UAE_MEMORY_REGION_RAM (1 << 0)
+#define UAE_MEMORY_REGION_ALIAS (1 << 1)
+#define UAE_MEMORY_REGION_MIRROR (1 << 2)
+
+typedef struct UaeMemoryRegion {
+	uaecptr start;
+	int size;
+	TCHAR name[UAE_MEMORY_REGION_NAME_LENGTH];
+	TCHAR rom_name[UAE_MEMORY_REGION_NAME_LENGTH];
+	uaecptr alias;
+	int flags;
+} UaeMemoryRegion;
+
+typedef struct UaeMemoryMap {
+	UaeMemoryRegion regions[UAE_MEMORY_REGIONS_MAX];
+	int num_regions;
+} UaeMemoryMap;
+#endif
+
+static void memory_map_dump_3(UaeMemoryMap *map, int log)
+{
+	bool imold;
+	int i, j, max;
+	addrbank *a1 = mem_banks[0];
+	TCHAR txt[256];
+
+	map->num_regions = 0;
+	imold = currprefs.illegal_mem;
+	currprefs.illegal_mem = false;
+	max = currprefs.address_space_24 ? 256 : 65536;
+	j = 0;
+	for (i = 0; i < max + 1; i++) {
+		addrbank *a2 = NULL;
+		if (i < max)
+			a2 = mem_banks[i];
+		if (a1 != a2) {
+			int k, mirrored, mirrored2, size, size_out;
+			TCHAR size_ext;
+			uae_u8 *caddr;
+			TCHAR tmp[MAX_DPATH];
+			const TCHAR *name = a1->name;
+			struct addrbank_sub *sb = a1->sub_banks;
+			int bankoffset = 0;
+			int region_size;
+
+			k = j;
+			caddr = dump_xlate (k << 16);
+			mirrored = caddr ? 1 : 0;
+			k++;
+			while (k < i && caddr) {
+				if (dump_xlate (k << 16) == caddr)
+					mirrored++;
+				k++;
+			}
+			mirrored2 = mirrored;
+			if (mirrored2 == 0)
+				mirrored2 = 1;
+
+			while (bankoffset < 65536) {
+				int bankoffset2 = bankoffset;
+				if (sb) {
+					uaecptr daddr;
+					if (!sb->bank)
+						break;
+					daddr = (j << 16) | bankoffset;
+					a1 = get_sub_bank(&daddr);
+					name = a1->name;
+					for (;;) {
+						bankoffset2 += MEMORY_MIN_SUBBANK;
+						if (bankoffset2 >= 65536)
+							break;
+						daddr = (j << 16) | bankoffset2;
+						addrbank *dab = get_sub_bank(&daddr);
+						if (dab != a1)
+							break;
+					}
+					sb++;
+					size = (bankoffset2 - bankoffset) / 1024;
+					region_size = size * 1024;
+				} else {
+					size = (i - j) << (16 - 10);
+					region_size = ((i - j) << 16) / mirrored2;
+				}
+
+				if (name == NULL)
+					name = _T("");
+
+				size_out = size;
+				size_ext = 'K';
+				if (j >= 256 && (size_out / mirrored2 >= 1024) && !((size_out / mirrored2) & 1023)) {
+					size_out /= 1024;
+					size_ext = 'M';
+				}
+#if 1
+				_stprintf (txt, _T("%08X %7d%c/%d = %7d%c %s"), (j << 16) | bankoffset, size_out, size_ext,
+					mirrored, mirrored ? size_out / mirrored : size_out, size_ext, name);
+#endif
+				tmp[0] = 0;
+				if ((a1->flags & ABFLAG_ROM) && mirrored) {
+					TCHAR *p = txt + _tcslen (txt);
+					uae_u32 crc = 0xffffffff;
+					if (a1->check(((j << 16) | bankoffset), (size * 1024) / mirrored))
+						crc = get_crc32 (a1->xlateaddr((j << 16) | bankoffset), (size * 1024) / mirrored);
+					struct romdata *rd = getromdatabycrc (crc);
+					_stprintf (p, _T(" (%08X)"), crc);
+					if (rd) {
+						tmp[0] = '=';
+						getromname (rd, tmp + 1);
+						_tcscat (tmp, _T("\n"));
+					}
+				}
+
+				if (a1 != &dummy_bank) {
+					for (int m = 0; m < mirrored2; m++) {
+						UaeMemoryRegion *r = &map->regions[map->num_regions];
+						r->start = (j << 16) + bankoffset + region_size * m;
+						r->size = region_size;
+						r->flags = 0;
+						r->memory = NULL;
+						r->memory = dump_xlate((j << 16) | bankoffset);
+						if (r->memory)
+							r->flags |= UAE_MEMORY_REGION_RAM;
+						/* just to make it easier to spot in debugger */
+						r->alias = 0xffffffff;
+						if (m >= 0) {
+							r->alias = j << 16;
+							r->flags |= UAE_MEMORY_REGION_ALIAS | UAE_MEMORY_REGION_MIRROR;
+						}
+						_stprintf(r->name, _T("%s"), name);
+						_stprintf(r->rom_name, _T("%s"), tmp);
+						map->num_regions += 1;
+					}
+				}
+
+#if 1
+				_tcscat (txt, _T("\n"));
+				if (log > 0)
+					write_log (txt);
+				else if (log == 0)
+					console_out (txt);
+				if (tmp[0]) {
+					if (log > 0)
+						write_log (tmp);
+					else if (log == 0)
+						console_out (tmp);
+				}
+#endif
+				if (!sb)
+					break;
+				bankoffset = bankoffset2;
+			}
+			j = i;
+			a1 = a2;
+		}
+	}
+	currprefs.illegal_mem = imold;
+}
+
+void uae_memory_map(UaeMemoryMap *map)
+{
+	memory_map_dump_3(map, -1);
+}
+
+static void memory_map_dump_2 (int log)
+{
+	UaeMemoryMap map;
+	memory_map_dump_3(&map, log);
+#if 0
+	for (int i = 0; i < map.num_regions; i++) {
+		TCHAR txt[256];
+		UaeMemoryRegion *r = &map.regions[i];
+		int size = r->size / 1024;
+		TCHAR size_ext = 'K';
+		int mirrored = 1;
+		int size_out = 0;
+		_stprintf (txt, _T("%08X %7u%c/%d = %7u%c %s\n"), r->start, size, size_ext,
+			r->flags & UAE_MEMORY_REGION_RAM, size, size_ext, r->name);
+		if (log)
+			write_log (_T("%s"), txt);
+		else
+			console_out (txt);
+		if (r->rom_name[0]) {
+			if (log)
+				write_log (_T("%s"), r->rom_name);
+			else
+				console_out (r->rom_name);
+		}
+	}
+#endif
+}
+
+void memory_map_dump (void)
+ {
+ 	memory_map_dump_2 (1);
+}
+
+STATIC_INLINE uaecptr BPTR2APTR (uaecptr addr)
+{
+	return addr << 2;
+}
+static TCHAR *BSTR2CSTR (uae_u8 *bstr)
+{
+	TCHAR *s;
+	char *cstr = xmalloc (char, bstr[0] + 1);
+	if (cstr) {
+		memcpy (cstr, bstr + 1, bstr[0]);
+		cstr[bstr[0]] = 0;
+	}
+	s = au (cstr);
+	xfree (cstr);
+	return s;
+}
+
+static void print_task_info (uaecptr node, bool nonactive)
+{
+	TCHAR *s;
+	int process = get_byte_debug (node + 8) == 13 ? 1 : 0;
+
+	console_out_f (_T("%08X: "), node);
+	s = au ((char*)get_real_address (get_long_debug (node + 10)));
+	console_out_f (process ? _T("PROCESS '%s'\n") : _T("TASK    '%s'\n"), s);
+	xfree (s);
+	if (process) {
+		uaecptr cli = BPTR2APTR (get_long_debug (node + 172));
+		int tasknum = get_long_debug (node + 140);
+		if (cli && tasknum) {
+			uae_u8 *command_bstr = get_real_address (BPTR2APTR (get_long_debug (cli + 16)));
+			TCHAR *command = BSTR2CSTR (command_bstr);
+			console_out_f (_T(" [%d, '%s']\n"), tasknum, command);
+			xfree (command);
+		} else {
+			console_out (_T("\n"));
+		}
+	}
+	if (nonactive) {
+		uae_u32 sigwait = get_long_debug(node + 22);
+		if (sigwait)
+			console_out_f(_T("          Waiting signals: %08x\n"), sigwait);
+		uae_u32 sp = get_long_debug(node + 54) + 70;
+		uae_u32 pc = get_long_debug(sp);
+		console_out_f(_T("          SP: %08x PC: %08x\n"), sp, pc);
+	}
+}
+
+static void show_exec_tasks (void)
+{
+	uaecptr execbase = get_long_debug (4);
+	uaecptr taskready = execbase + 406;
+	uaecptr taskwait = execbase + 420;
+	uaecptr node;
+	console_out_f (_T("Execbase at 0x%08X\n"), execbase);
+	console_out (_T("Current:\n"));
+	node = get_long_debug (execbase + 276);
+	print_task_info (node, false);
+	console_out_f (_T("Ready:\n"));
+	node = get_long_debug (taskready);
+	while (node && get_long_debug(node)) {
+		print_task_info (node, true);
+		node = get_long_debug (node);
+	}
+	console_out (_T("Waiting:\n"));
+	node = get_long_debug (taskwait);
+	while (node && get_long_debug(node)) {
+		print_task_info (node, true);
+		node = get_long_debug (node);
+	}
+}
+
+static uaecptr get_base (const uae_char *name, int offset)
+{
+	uaecptr v = get_long_debug (4);
+	addrbank *b = &get_mem_bank(v);
+
+	if (!b || !b->check (v, 400) || !(b->flags & ABFLAG_RAM))
+		return 0;
+	v += offset;
+	while (v = get_long_debug (v)) {
+		uae_u32 v2;
+		uae_u8 *p;
+		b = &get_mem_bank (v);
+		if (!b || !b->check (v, 32) || (!(b->flags & ABFLAG_RAM) && !(b->flags & ABFLAG_ROMIN)))
+			goto fail;
+		v2 = get_long_debug (v + 10); // name
+		b = &get_mem_bank (v2);
+		if (!b || !b->check (v2, 20))
+			goto fail;
+		if ((b->flags & ABFLAG_ROM) || (b->flags & ABFLAG_RAM) || (b->flags & ABFLAG_ROMIN)) {
+			p = b->xlateaddr (v2);
+			if (!memcmp (p, name, strlen (name) + 1))
+				return v;
+		}
+	}
+	return 0;
+fail:
+	return 0xffffffff;
+}
+
+static TCHAR *getfrombstr(uaecptr pp)
+{
+	uae_u8 *p = get_real_address ((uaecptr)(pp << 2));
+	TCHAR *s = xmalloc (TCHAR, p[0] + 1);
+	return au_copy (s, p[0] + 1, (char*)p + 1);
+}
+
+// read one byte from expansion autoconfig ROM
+static void copyromdata(uae_u8 bustype, uaecptr rom, int offset, uae_u8 *out, int size)
+{
+	switch (bustype & 0xc0)
+	{
+	case 0x00: // nibble
+		while (size-- > 0) {
+			*out++ = (get_byte_debug(rom + offset * 4 + 0) & 0xf0) | ((get_byte_debug(rom + offset * 4 + 2) & 0xf0) >> 4);
+			offset++;
+		}
+		break;
+	case 0x40: // byte
+		while (size-- > 0) {
+			*out++ = get_byte_debug(rom + offset * 2);
+			offset++;
+		}
+		break;
+	case 0x80: // word
+	default:
+		while (size-- > 0) {
+			*out++ = get_byte_debug(rom + offset);
+			offset++;
+		}
+		break;
+	}
+}
+
+static void show_exec_lists (TCHAR *t)
+{
+	uaecptr execbase = get_long_debug (4);
+	uaecptr list = 0, node;
+	TCHAR c = t[0];
+	TCHAR c2 = t[1];
+
+	if (c == 'o' || c == 'O') { // doslist
+		uaecptr dosbase = get_base ("dos.library", 378);
+		if (dosbase) {
+			uaecptr rootnode = get_long_debug (dosbase + 34);
+			uaecptr dosinfo = get_long_debug (rootnode + 24) << 2;
+			console_out_f (_T("ROOTNODE: %08x DOSINFO: %08x\n"), rootnode, dosinfo);
+			uaecptr doslist = get_long_debug (dosinfo + 4) << 2;
+			while (doslist) {
+				int type = get_long_debug (doslist + 4);
+				uaecptr msgport = get_long_debug (doslist + 8);
+				TCHAR *name = getfrombstr (get_long_debug (doslist + 40));
+				console_out_f (_T("%08x: %d %08x '%s'\n"), doslist, type, msgport, name);
+				if (type == 0) {
+					uaecptr fssm = get_long_debug(doslist + 28) << 2;
+					console_out_f (_T(" - H=%08x Stack=%5d Pri=%2d Start=%08x Seg=%08x GV=%08x\n"),
+						get_long_debug (doslist + 16) << 2, get_long_debug (doslist + 20),
+						get_long_debug (doslist + 24), fssm,
+						get_long_debug (doslist + 32) << 2, get_long_debug (doslist + 36));
+					if (fssm >= 0x100 && (fssm & 3) == 0) {
+						TCHAR *unitname = getfrombstr(get_long_debug(fssm + 4));
+						console_out_f (_T("   %s:%d %08x\n"), unitname, get_long_debug(fssm), get_long_debug(fssm + 8));
+						uaecptr de = get_long_debug(fssm + 8) << 2;
+						if (de) {
+							console_out_f (_T("    TableSize       %u\n"), get_long_debug(de + 0));
+							console_out_f (_T("    SizeBlock       %u\n"), get_long_debug(de + 4));
+							console_out_f (_T("    SecOrg          %u\n"), get_long_debug(de + 8));
+							console_out_f (_T("    Surfaces        %u\n"), get_long_debug(de + 12));
+							console_out_f (_T("    SectorPerBlock  %u\n"), get_long_debug(de + 16));
+							console_out_f (_T("    BlocksPerTrack  %u\n"), get_long_debug(de + 20));
+							console_out_f (_T("    Reserved        %u\n"), get_long_debug(de + 24));
+							console_out_f (_T("    PreAlloc        %u\n"), get_long_debug(de + 28));
+							console_out_f (_T("    Interleave      %u\n"), get_long_debug(de + 32));
+							console_out_f (_T("    LowCyl          %u\n"), get_long_debug(de + 36));
+							console_out_f (_T("    HighCyl         %u (Total %u)\n"), get_long_debug(de + 40), get_long_debug(de + 40) - get_long_debug(de + 36) + 1);
+							console_out_f (_T("    NumBuffers      %u\n"), get_long_debug(de + 44));
+							console_out_f (_T("    BufMemType      0x%08x\n"), get_long_debug(de + 48));
+							console_out_f (_T("    MaxTransfer     0x%08x\n"), get_long_debug(de + 52));
+							console_out_f (_T("    Mask            0x%08x\n"), get_long_debug(de + 56));
+							console_out_f (_T("    BootPri         %d\n"), get_long_debug(de + 60));
+							console_out_f (_T("    DosType         0x%08x\n"), get_long_debug(de + 64));
+						}
+						xfree(unitname);
+					}
+				}
+				xfree (name);
+				doslist = get_long_debug (doslist) << 2;
+			}
+		} else {
+			console_out_f (_T("can't find dos.library\n"));
+		}
+		return;
+	} else if (c == 'i' || c == 'I') { // interrupts
+		static const int it[] = {  1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0 };
+		static const int it2[] = { 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7 };
+		list = execbase + 84;
+		for (int i = 0; i < 16; i++) {
+			console_out_f (_T("%2d %d: %08x\n"), i + 1, it2[i], list);
+			if (it[i]) {
+				console_out_f (_T("  [H] %08x\n"), get_long_debug (list));
+				node = get_long_debug (list + 8);
+				if (node) {
+					uae_u8 *addr = get_real_address (get_long_debug (node + 10));
+					TCHAR *name = addr ? au ((char*)addr) : au("");
+					console_out_f (_T("      %08x (C=%08X D=%08X) '%s'\n"), node, get_long_debug (list + 4), get_long_debug (list), name);
+					xfree (name);
+				}
+			} else {
+				int cnt = 0;
+				node = get_long_debug (list);
+				node = get_long_debug (node);
+				while (get_long_debug (node)) {
+					uae_u8 *addr = get_real_address (get_long_debug (node + 10));
+					TCHAR *name = addr ? au ((char*)addr) : au("");
+					console_out_f (_T("  [S] %08x (C=%08x D=%08X) '%s'\n"), node, get_long_debug (node + 18), get_long_debug (node + 14), name);
+					if (i == 4 - 1 || i == 14 - 1) {
+						if (!_tcsicmp (name, _T("cia-a")) || !_tcsicmp (name, _T("cia-b"))) {
+							static const TCHAR *ciai[] = { _T("A"), _T("B"), _T("ALRM"), _T("SP"), _T("FLG") };
+							uaecptr cia = node + 22;
+							for (int j = 0; j < 5; j++) {
+								uaecptr ciap = get_long_debug (cia);
+								console_out_f (_T("        %5s: %08x"), ciai[j], ciap);
+								if (ciap) {
+									uae_u8 *addr2 = get_real_address (get_long_debug (ciap + 10));
+									TCHAR *name2 = addr ? au ((char*)addr2) : au("");
+									console_out_f (_T(" (C=%08x D=%08X) '%s'"), get_long_debug (ciap + 18), get_long_debug (ciap + 14), name2);
+									xfree (name2);
+								}
+								console_out_f (_T("\n"));
+								cia += 4;
+							}
+						}
+					}
+					xfree (name);
+					node = get_long_debug (node);
+					cnt++;
+				}
+				if (!cnt)
+					console_out_f (_T("  [S] \n"));
+			}
+			list += 12;
+		}
+		return;
+	} else if (c == 'e') { // expansion
+		uaecptr expbase = get_base("expansion.library", 378);
+		if (expbase) {
+			list = get_long_debug(expbase + 60);
+			while (list && get_long_debug(list)) {
+				uae_u32 addr = get_long_debug(list + 32);
+				uae_u16 rom_vector = get_word_debug(list + 16 + 10);
+				uae_u8 type = get_byte_debug(list + 16 + 0);
+				console_out_f(_T("%02x %02x %08x %08x %04x %02x %08x %04x (%u/%u)\n"),
+					type, get_byte_debug(list + 16 + 2),
+					addr, get_long_debug(list + 36),
+					get_word_debug(list + 16 + 4), get_byte_debug(list + 16 + 1),
+					get_long_debug(list + 16 + 6), rom_vector,
+					get_word_debug(list + 16 + 4), get_byte_debug(list + 16 + 1));
+				if ((type & 0x10)) {
+					uae_u8 diagarea[256];
+					uae_u16 nameoffset;
+					uaecptr rom = addr + rom_vector;
+					uae_u8 config = get_byte_debug(rom);
+					copyromdata(config, rom, 0, diagarea, 16);
+					nameoffset = (diagarea[8] << 8) | diagarea[9];
+					console_out_f(_T(" %02x %02x Size %04x Diag %04x Boot %04x Name %04x %04x %04x\n"),
+						diagarea[0], diagarea[1],
+						(diagarea[2] << 8) | diagarea[3],
+						(diagarea[4] << 8) | diagarea[5],
+						(diagarea[6] << 8) | diagarea[7],
+						nameoffset,
+						(diagarea[10] << 8) | diagarea[11],
+						(diagarea[12] << 8) | diagarea[13]);
+					if (nameoffset != 0 && nameoffset != 0xffff) {
+						copyromdata(config, rom, nameoffset, diagarea, 256);
+						diagarea[sizeof diagarea - 1] = 0;
+						TCHAR *str = au((char*)diagarea);
+						console_out_f(_T(" '%s'\n"), str);
+						xfree(str);
+					}
+				}
+				list = get_long_debug(list);
+			}
+		}
+	} else if (c == 'R') { // residents
+		list = get_long_debug(execbase + 300);
+		while (list) {
+			uaecptr resident = get_long_debug (list);
+			if (!resident)
+				break;
+			if (resident & 0x80000000) {
+				console_out_f (_T("-> %08X\n"), resident & 0x7fffffff);
+				list = resident & 0x7fffffff;
+				continue;
+			}
+			uae_u8 *addr;
+			addr = get_real_address (get_long_debug (resident + 14));
+			TCHAR *name1 = addr ? au ((char*)addr) : au("");
+			my_trim (name1);
+			addr = get_real_address (get_long_debug (resident + 18));
+			TCHAR *name2 = addr ? au ((char*)addr) : au("");
+			my_trim (name2);
+			console_out_f (_T("%08X %08X: %02X %3d %02X %+3.3d '%s' ('%s')\n"),
+				list, resident,
+				get_byte_debug (resident + 10), get_byte_debug (resident + 11),
+				get_byte_debug (resident + 12), (uae_s8)get_byte_debug (resident + 13),
+				name1, name2);
+			xfree (name2);
+			xfree (name1);
+			list += 4;
+		}
+		return;
+	} else if (c == 'f' || c== 'F') { // filesystem.resource
+		uaecptr fs = get_base ("FileSystem.resource", 336);
+		if (fs) {
+			static const TCHAR *fsnames[] = {
+				_T("DosType"),
+				_T("Version"),
+				_T("PatchFlags"),
+				_T("Type"),
+				_T("Task"),
+				_T("Lock"),
+				_T("Handler"),
+				_T("StackSize"),
+				_T("Priority"),
+				_T("Startup"),
+				_T("SegList"),
+				_T("GlobalVec"),
+				NULL
+			};
+			uae_u8 *addr = get_real_address (get_long_debug (fs + 14));
+			TCHAR *name = addr ? au ((char*)addr) : au ("");
+			my_trim (name);
+			console_out_f (_T("%08x: '%s'\n"), fs, name);
+			xfree (name);
+			node = get_long_debug (fs + 18);
+			while (get_long_debug (node)) {
+				TCHAR *name = au ((char*)get_real_address (get_long_debug (node + 10)));
+				my_trim (name);
+				console_out_f (_T("%08x: '%s'\n"), node, name);
+				xfree (name);
+				for (int i = 0; fsnames[i]; i++) {
+					uae_u32 v = get_long_debug (node + 14 + i * 4);
+					console_out_f (_T("%16s = %08x %d\n"), fsnames[i], v, v);
+				}
+				console_out_f (_T("\n"));
+				node = get_long_debug (node);
+			}
+
+		} else {
+			console_out_f (_T("FileSystem.resource not found.\n"));
+		}
+		return;
+	} else if (c == 'm' || c == 'M') { // memory
+		list = execbase + 322;
+		node = get_long_debug (list);
+		while (get_long_debug (node)) {
+			TCHAR *name = au ((char*)get_real_address (get_long_debug (node + 10)));
+			uae_u16 v = get_word_debug (node + 8);
+			console_out_f (_T("%08x %d %d %s\n"), node, (int)((v >> 8) & 0xff), (uae_s8)(v & 0xff), name);
+			xfree (name);
+			console_out_f (_T("Attributes %04x First %08x Lower %08x Upper %08x Free %d\n"),
+				get_word_debug (node + 14), get_long_debug (node + 16), get_long_debug (node + 20), 
+				get_long_debug (node + 24), get_long_debug (node + 28));
+			uaecptr mc = get_long_debug (node + 16);
+			while (mc) {
+				uae_u32 mc1 = get_long_debug (mc);
+				uae_u32 mc2 = get_long_debug (mc + 4);
+				console_out_f (_T(" %08x: %08x-%08x,%08x,%08x (%d)\n"), mc, mc, mc + mc2, mc1, mc2, mc2);
+				mc = mc1;
+			}
+			console_out_f (_T("\n"));
+			node = get_long_debug (node);
+		}
+		return;
+	}
+
+	bool full = false;
+	switch (c)
+	{
+	case 'r': // resources
+		list = execbase + 336;
+		break;
+	case 'd': // devices
+		list = execbase + 350;
+		full = true;
+		break;
+	case 'l': // libraries
+		list = execbase + 378;
+		full = true;
+		break;
+	case 'p': // ports
+		list = execbase + 392;
+		break;
+	case 's': // semaphores
+		list = execbase + 532;
+		break;
+	}
+	if (list == 0)
+		return;
+	node = get_long_debug (list);
+	while (get_long_debug (node)) {
+		TCHAR *name = au ((char*)get_real_address (get_long_debug (node + 10)));
+		uae_u16 v = get_word_debug (node + 8);
+		console_out_f (_T("%08x %d %d"), node, (int)((v >> 8) & 0xff), (uae_s8)(v & 0xff));
+		if (full) {
+			uae_u16 ver = get_word_debug(node + 20);
+			uae_u16 rev = get_word_debug(node + 22);
+			uae_u32 op = get_word_debug(node + 32);
+			console_out_f(_T(" %d.%d %d"), ver, rev, op);
+		}
+		console_out_f(_T(" %s"), name);
+		xfree (name);
+		if (full) {
+			uaecptr idstring = get_long_debug(node + 24);
+			if (idstring) {
+				name = au((char*)get_real_address(idstring));
+				console_out_f(_T(" (%s)"), name);
+				xfree(name);
+			}
+		}
+		console_out_f(_T("\n"));
+		node = get_long_debug (node);
+	}
+}
+
+static void breakfunc(uae_u32 v)
+{
+	write_log(_T("Cycle breakpoint hit\n"));
+	debugging = 1;
+	set_special (SPCFLAG_BRK);
+}
+
+static int cycle_breakpoint(TCHAR **c)
+{
+	TCHAR nc = (*c)[0];
+	next_char(c);
+	if (more_params(c)) {
+		int count = readint(c);
+		if (nc == 's') {
+			if (more_params(c)) {
+				int hp = readint(c);
+				if (count >= vpos) {
+					count = vpos - count;
+				} else {
+					count += maxvpos - vpos;
+				}
+				count *= maxhpos;
+				if (hp >= current_hpos()) {
+					count += hp - current_hpos();
+				} else {
+					count += maxhpos - current_hpos();
+				}
+			} else {
+				count *= maxhpos;
+			}
+		}
+		event2_newevent_x(-1, count, 0, breakfunc);
+		return 1;
+	}
+	return 0;
+}
+
+#if 0
+static int trace_same_insn_count;
+static uae_u8 trace_insn_copy[10];
+static struct regstruct trace_prev_regs;
+#endif
+static uaecptr nextpc;
+
+int instruction_breakpoint (TCHAR **c)
+{
+	struct breakpoint_node *bpn;
+	int i;
+
+	if (more_params (c)) {
+		TCHAR nc = _totupper ((*c)[0]);
+		if (nc == 'S') {
+			next_char (c);
+			sr_bpvalue = sr_bpmask = 0;
+			if (more_params (c)) {
+				sr_bpmask = 0xffff;
+				sr_bpvalue = readhex (c);
+				if (more_params (c))
+					sr_bpmask = readhex (c);
+			}
+			console_out_f (_T("SR breakpoint, value=%04X, mask=%04X\n"), sr_bpvalue, sr_bpmask);
+			return 0;
+		} else if (nc == 'I') {
+			next_char (c);
+			if (more_params (c))
+				skipins = readhex (c);
+			else
+				skipins = 0x10000;
+			do_skip = 1;
+			skipaddr_doskip = 1;
+			return 1;
+		} else if (nc == 'D' && (*c)[1] == 0) {
+			for (i = 0; i < BREAKPOINT_TOTAL; i++)
+				bpnodes[i].enabled = 0;
+			console_out (_T("All breakpoints removed\n"));
+			return 0;
+		} else if (nc == 'L') {
+			int got = 0;
+			for (i = 0; i < BREAKPOINT_TOTAL; i++) {
+				bpn = &bpnodes[i];
+				if (!bpn->enabled)
+					continue;
+				console_out_f (_T("%8X "), bpn->addr);
+				got = 1;
+			}
+			if (!got)
+				console_out (_T("No breakpoints\n"));
+			else
+				console_out (_T("\n"));
+			return 0;
+		}
+		skipaddr_doskip = 1;
+		skipaddr_start = readhex (c);
+		if (more_params (c)) {
+			skipaddr_end = readhex (c);
+		} else {
+			for (i = 0; i < BREAKPOINT_TOTAL; i++) {
+				bpn = &bpnodes[i];
+				if (bpn->enabled && bpn->addr == skipaddr_start) {
+					bpn->enabled = 0;
+					console_out (_T("Breakpoint removed\n"));
+					skipaddr_start = 0xffffffff;
+					skipaddr_doskip = 0;
+					return 0;
+				}
+			}
+			for (i = 0; i < BREAKPOINT_TOTAL; i++) {
+				bpn = &bpnodes[i];
+				if (bpn->enabled)
+					continue;
+				bpn->addr = skipaddr_start;
+				bpn->enabled = 1;
+				console_out (_T("Breakpoint added\n"));
+				skipaddr_start = 0xffffffff;
+				skipaddr_doskip = 0;
+				break;
+			}
+			return 0;
+		}
+	}
+#if 0
+	if (skipaddr_start == 0xC0DEDBAD) {
+		trace_same_insn_count = 0;
+		logfile = fopen ("uae.trace", "w");
+		memcpy (trace_insn_copy, regs.pc_p, 10);
+		memcpy (&trace_prev_regs, ®s, sizeof regs);
+	}
+#endif
+	do_skip = 1;
+	skipaddr_doskip = -1;
+	return 1;
+}
+
+static int process_breakpoint (TCHAR **c)
+{
+	processptr = 0;
+	xfree (processname);
+	processname = NULL;
+	if (!more_params (c))
+		return 0;
+	if (**c == '\"') {
+		TCHAR pn[200];
+		next_string (c, pn, 200, 0);
+		processname = ua (pn);
+	} else {
+		processptr = readhex (c);
+	}
+	do_skip = 1;
+	skipaddr_doskip = 1;
+	skipaddr_start = 0;
+	return 1;
+}
+
+static void savemem (TCHAR **cc)
+{
+	uae_u8 b;
+	uae_u32 src, src2, len, len2;
+	TCHAR *name;
+	FILE *fp;
+
+	if (!more_params (cc))
+		goto S_argh;
+
+	name = *cc;
+	while (**cc != '\0' && !isspace (**cc))
+		(*cc)++;
+	if (!isspace (**cc))
+		goto S_argh;
+
+	**cc = '\0';
+	(*cc)++;
+	if (!more_params (cc))
+		goto S_argh;
+	src2 = src = readhex (cc);
+	if (!more_params (cc))
+		goto S_argh;
+	len2 = len = readhex (cc);
+	fp = _tfopen (name, _T("wb"));
+	if (fp == NULL) {
+		console_out_f (_T("Couldn't open file '%s'\n"), name);
+		return;
+	}
+	while (len > 0) {
+		b = get_byte_debug (src);
+		src++;
+		len--;
+		if (fwrite (&b, 1, 1, fp) != 1) {
+			console_out (_T("Error writing file\n"));
+			break;
+		}
+	}
+	fclose (fp);
+	if (len == 0)
+		console_out_f (_T("Wrote %08X - %08X (%d bytes) to '%s'\n"),
+		src2, src2 + len2, len2, name);
+	return;
+S_argh:
+	console_out (_T("S-command needs more arguments!\n"));
+}
+
+static void searchmem (TCHAR **cc)
+{
+	int i, sslen, got, val, stringmode;
+	uae_u8 ss[256];
+	uae_u32 addr, endaddr;
+	TCHAR nc;
+
+	got = 0;
+	sslen = 0;
+	stringmode = 0;
+	ignore_ws (cc);
+	if (**cc == '"') {
+		stringmode = 1;
+		(*cc)++;
+		while (**cc != '"' && **cc != 0) {
+			ss[sslen++] = tolower (**cc);
+			(*cc)++;
+		}
+		if (**cc != 0)
+			(*cc)++;
+	} else {
+		for (;;) {
+			if (**cc == 32 || **cc == 0)
+				break;
+			nc = _totupper (next_char (cc));
+			if (isspace (nc))
+				break;
+			if (isdigit(nc))
+				val = nc - '0';
+			else
+				val = nc - 'A' + 10;
+			if (val < 0 || val > 15)
+				return;
+			val *= 16;
+			if (**cc == 32 || **cc == 0)
+				break;
+			nc = _totupper (next_char (cc));
+			if (isspace (nc))
+				break;
+			if (isdigit(nc))
+				val += nc - '0';
+			else
+				val += nc - 'A' + 10;
+			if (val < 0 || val > 255)
+				return;
+			ss[sslen++] = (uae_u8)val;
+		}
+	}
+	if (sslen == 0)
+		return;
+	ignore_ws (cc);
+	addr = 0;
+	endaddr = lastaddr ();
+	if (more_params (cc)) {
+		addr = readhex (cc);
+		if (more_params (cc))
+			endaddr = readhex (cc);
+	}
+	console_out_f (_T("Searching from %08X to %08X..\n"), addr, endaddr);
+	while ((addr = nextaddr (addr, endaddr, NULL)) != 0xffffffff) {
+		if (addr == endaddr)
+			break;
+		for (i = 0; i < sslen; i++) {
+			uae_u8 b = get_byte_debug (addr + i);
+			if (stringmode) {
+				if (tolower (b) != ss[i])
+					break;
+			} else {
+				if (b != ss[i])
+					break;
+			}
+		}
+		if (i == sslen) {
+			got++;
+			console_out_f (_T(" %08X"), addr);
+			if (got > 100) {
+				console_out (_T("\nMore than 100 results, aborting.."));
+				break;
+			}
+		}
+		if  (iscancel (65536)) {
+			console_out_f (_T("Aborted at %08X\n"), addr);
+			break;
+		}
+	}
+	if (!got)
+		console_out (_T("nothing found"));
+	console_out (_T("\n"));
+}
+
+static int staterecorder (TCHAR **cc)
+{
+#if 0
+	TCHAR nc;
+
+	if (!more_params (cc)) {
+		if (savestate_dorewind (1)) {
+			debug_rewind = 1;
+			return 1;
+		}
+		return 0;
+	}
+	nc = next_char (cc);
+	if (nc == 'l') {
+		savestate_listrewind ();
+		return 0;
+	}
+#endif
+	return 0;
+}
+
+static int debugtest_modes[DEBUGTEST_MAX];
+static const TCHAR *debugtest_names[] = {
+	_T("Blitter"), _T("Keyboard"), _T("Floppy")
+};
+
+void debugtest (enum debugtest_item di, const TCHAR *format, ...)
+{
+	va_list parms;
+	TCHAR buffer[1000];
+
+	if (!debugtest_modes[di])
+		return;
+	va_start (parms, format);
+	_vsntprintf (buffer, 1000 - 1, format, parms);
+	va_end (parms);
+	write_log (_T("%s PC=%08X: %s\n"), debugtest_names[di], M68K_GETPC, buffer);
+	if (debugtest_modes[di] == 2)
+		activate_debugger ();
+}
+
+static void debugtest_set (TCHAR **inptr)
+{
+	int i, val, val2;
+	ignore_ws (inptr);
+
+	val2 = 1;
+	if (!more_params (inptr)) {
+		for (i = 0; i < DEBUGTEST_MAX; i++)
+			debugtest_modes[i] = 0;
+		console_out (_T("All debugtests disabled\n"));
+		return;
+	}
+	val = readint (inptr);
+	if (more_params (inptr)) {
+		val2 = readint (inptr);
+		if (val2 > 0)
+			val2 = 2;
+	}
+	if (val < 0) {
+		for (i = 0; i < DEBUGTEST_MAX; i++)
+			debugtest_modes[i] = val2;
+		console_out (_T("All debugtests enabled\n"));
+		return;
+	}
+	if (val >= 0 && val < DEBUGTEST_MAX) {
+		if (debugtest_modes[val])
+			debugtest_modes[val] = 0;
+		else
+			debugtest_modes[val] = val2;
+		console_out_f (_T("Debugtest '%s': %s. break = %s\n"),
+			debugtest_names[val], debugtest_modes[val] ? _T("on") :_T("off"), val2 == 2 ? _T("on") : _T("off"));
+	}
+}
+
+static void debug_sprite (TCHAR **inptr)
+{
+	uaecptr saddr, addr, addr2;
+	int xpos, xpos_ecs;
+	int ypos, ypos_ecs;
+	int ypose, ypose_ecs;
+	int attach;
+	uae_u64 w1, w2, ww1, ww2;
+	int size = 1, width;
+	int ecs, sh10;
+	int y, i;
+	TCHAR tmp[80];
+	int max = 2;
+
+	addr2 = 0;
+	ignore_ws (inptr);
+	addr = readhex (inptr);
+	ignore_ws (inptr);
+	if (more_params (inptr))
+		size = readhex (inptr);
+	if (size != 1 && size != 2 && size != 4) {
+		addr2 = size;
+		ignore_ws (inptr);
+		if (more_params (inptr))
+			size = readint (inptr);
+		if (size != 1 && size != 2 && size != 4)
+			size = 1;
+	}
+	for (;;) {
+		ecs = 0;
+		sh10 = 0;
+		saddr = addr;
+		width = size * 16;
+		w1 = get_word_debug (addr);
+		w2 = get_word_debug (addr + size * 2);
+		console_out_f (_T("    %06X "), addr);
+		for (i = 0; i < size * 2; i++)
+			console_out_f (_T("%04X "), get_word_debug (addr + i * 2));
+		console_out_f (_T("\n"));
+
+		ypos = w1 >> 8;
+		xpos = w1 & 255;
+		ypose = w2 >> 8;
+		attach = (w2 & 0x80) ? 1 : 0;
+		if (w2 & 4)
+			ypos |= 256;
+		if (w2 & 2)
+			ypose |= 256;
+		ypos_ecs = ypos;
+		ypose_ecs = ypose;
+		if (w2 & 0x40)
+			ypos_ecs |= 512;
+		if (w2 & 0x20)
+			ypose_ecs |= 512;
+		xpos <<= 1;
+		if (w2 & 0x01)
+			xpos |= 1;
+		xpos_ecs = xpos << 2;
+		if (w2 & 0x10)
+			xpos_ecs |= 2;
+		if (w2 & 0x08)
+			xpos_ecs |= 1;
+		if (w2 & (0x40 | 0x20 | 0x10 | 0x08))
+			ecs = 1;
+		if (w1 & 0x80)
+			sh10 = 1;
+		if (ypose < ypos)
+			ypose += 256;
+
+		for (y = ypos; y < ypose; y++) {
+			int x;
+			addr += size * 4;
+			if (addr2)
+				addr2 += size * 4;
+			if (size == 1) {
+				w1 = get_word_debug (addr);
+				w2 = get_word_debug (addr + 2);
+				if (addr2) {
+					ww1 = get_word_debug (addr2);
+					ww2 = get_word_debug (addr2 + 2);
+				}
+			} else if (size == 2) {
+				w1 = get_long_debug (addr);
+				w2 = get_long_debug (addr + 4);
+				if (addr2) {
+					ww1 = get_long_debug (addr2);
+					ww2 = get_long_debug (addr2 + 4);
+				}
+			} else if (size == 4) {
+				w1 = get_long_debug (addr + 0);
+				w2 = get_long_debug (addr + 8);
+				w1 <<= 32;
+				w2 <<= 32;
+				w1 |= get_long_debug (addr + 4);
+				w2 |= get_long_debug (addr + 12);
+				if (addr2) {
+					ww1 = get_long_debug (addr2 + 0);
+					ww2 = get_long_debug (addr2 + 8);
+					ww1 <<= 32;
+					ww2 <<= 32;
+					ww1 |= get_long_debug (addr2 + 4);
+					ww2 |= get_long_debug (addr2 + 12);
+				}
+			}
+			width = size * 16;
+			for (x = 0; x < width; x++) {
+				int v1 = w1 & 1;
+				int v2 = w2 & 1;
+				int v = v1 * 2 + v2;
+				w1 >>= 1;
+				w2 >>= 1;
+				if (addr2) {
+					int vv1 = ww1 & 1;
+					int vv2 = ww2 & 1;
+					int vv = vv1 * 2 + vv2;
+					vv1 >>= 1;
+					vv2 >>= 1;
+					v *= 4;
+					v += vv;
+					tmp[width - (x + 1)] = v >= 10 ? 'A' + v - 10 : v + '0';
+				} else {
+					tmp[width - (x + 1)] = v + '0';
+				}
+			}
+			tmp[width] = 0;
+			console_out_f (_T("%3d %06X %s\n"), y, addr, tmp);
+		}
+
+		console_out_f (_T("Sprite address %08X, width = %d\n"), saddr, size * 16);
+		console_out_f (_T("OCS: StartX=%d StartY=%d EndY=%d\n"), xpos, ypos, ypose);
+		console_out_f (_T("ECS: StartX=%d (%d.%d) StartY=%d EndY=%d%s\n"), xpos_ecs, xpos_ecs / 4, xpos_ecs & 3, ypos_ecs, ypose_ecs, ecs ? _T(" (*)") : _T(""));
+		console_out_f (_T("Attach: %d. AGA SSCAN/SH10 bit: %d\n"), attach, sh10);
+
+		addr += size * 4;
+		if (get_word_debug (addr) == 0 && get_word_debug (addr + size * 4) == 0)
+			break;
+		max--;
+		if (max <= 0)
+			break;
+	}
+
+}
+
+int debug_write_memory_16 (uaecptr addr, uae_u16 v)
+{
+	addrbank *ad;
+	
+	ad = &get_mem_bank (addr);
+	if (ad) {
+		ad->wput (addr, v);
+		return 1;
+	}
+	return -1;
+}
+int debug_write_memory_8 (uaecptr addr, uae_u8 v)
+{
+	addrbank *ad;
+	
+	ad = &get_mem_bank (addr);
+	if (ad) {
+		ad->bput (addr, v);
+		return 1;
+	}
+	return -1;
+}
+int debug_peek_memory_16 (uaecptr addr)
+{
+	addrbank *ad;
+	
+	ad = &get_mem_bank (addr);
+	if (ad->flags & (ABFLAG_RAM | ABFLAG_ROM | ABFLAG_ROMIN | ABFLAG_SAFE))
+		return ad->wget (addr);
+	if (ad == &custom_bank) {
+		addr &= 0x1fe;
+		return (ar_custom[addr + 0] << 8) | ar_custom[addr + 1];
+	}
+	return -1;
+}
+int debug_read_memory_16 (uaecptr addr)
+{
+	addrbank *ad;
+	
+	ad = &get_mem_bank (addr);
+	if (ad)
+		return ad->wget (addr);
+	return -1;
+}
+int debug_read_memory_8 (uaecptr addr)
+{
+	addrbank *ad;
+	
+	ad = &get_mem_bank (addr);
+	if (ad)
+		return ad->bget (addr);
+	return -1;
+}
+
+static void disk_debug (TCHAR **inptr)
+{
+	TCHAR parm[10];
+	int i;
+
+	if (**inptr == 'd') {
+		(*inptr)++;
+		ignore_ws (inptr);
+		disk_debug_logging = readint (inptr);
+		console_out_f (_T("Disk logging level %d\n"), disk_debug_logging);
+		return;
+	}
+	disk_debug_mode = 0;
+	disk_debug_track = -1;
+	ignore_ws (inptr);
+	if (!next_string (inptr, parm, sizeof (parm) / sizeof (TCHAR), 1))
+		goto end;
+	for (i = 0; i < _tcslen(parm); i++) {
+		if (parm[i] == 'R')
+			disk_debug_mode |= DISK_DEBUG_DMA_READ;
+		if (parm[i] == 'W')
+			disk_debug_mode |= DISK_DEBUG_DMA_WRITE;
+		if (parm[i] == 'P')
+			disk_debug_mode |= DISK_DEBUG_PIO;
+	}
+	if (more_params(inptr))
+		disk_debug_track = readint (inptr);
+	if (disk_debug_track < 0 || disk_debug_track > 2 * 83)
+		disk_debug_track = -1;
+	if (disk_debug_logging == 0)
+		disk_debug_logging = 1;
+end:
+	console_out_f (_T("Disk breakpoint mode %c%c%c track %d\n"),
+		disk_debug_mode & DISK_DEBUG_DMA_READ ? 'R' : '-',
+		disk_debug_mode & DISK_DEBUG_DMA_WRITE ? 'W' : '-',
+		disk_debug_mode & DISK_DEBUG_PIO ? 'P' : '-',
+		disk_debug_track);
+}
+
+static void find_ea (TCHAR **inptr)
+{
+	uae_u32 ea, sea, dea;
+	uaecptr addr, end;
+	int hits = 0;
+
+	addr = 0;
+	end = lastaddr ();
+	ea = readhex (inptr);
+	if (more_params(inptr)) {
+		addr = readhex (inptr);
+		if (more_params(inptr))
+			end = readhex (inptr);
+	}
+	console_out_f (_T("Searching from %08X to %08X\n"), addr, end);
+	while((addr = nextaddr (addr, end, &end)) != 0xffffffff) {
+		if ((addr & 1) == 0 && addr + 6 <= end) {
+			sea = 0xffffffff;
+			dea = 0xffffffff;
+			m68k_disasm_ea (addr, NULL, 1, &sea, &dea);
+			if (ea == sea || ea == dea) {
+				m68k_disasm (addr, NULL, 1);
+				hits++;
+				if (hits > 100) {
+					console_out_f (_T("Too many hits. End addr = %08X\n"), addr);
+					break;
+				}
+			}
+			if  (iscancel (65536)) {
+				console_out_f (_T("Aborted at %08X\n"), addr);
+				break;
+			}
+		}
+	}
+}
+
+static void m68k_modify (TCHAR **inptr)
+{
+	uae_u32 v;
+	TCHAR parm[10];
+	TCHAR c1, c2;
+	int i;
+
+	if (!next_string (inptr, parm, sizeof (parm) / sizeof (TCHAR), 1))
+		return;
+	c1 = _totupper (parm[0]);
+	c2 = 99;
+	if (c1 == 'A' || c1 == 'D' || c1 == 'P') {
+		c2 = _totupper (parm[1]);
+		if (isdigit (c2))
+			c2 -= '0';
+		else
+			c2 = 99;
+	}
+	v = readhex (inptr);
+	if (c1 == 'A' && c2 < 8)
+		regs.regs[8 + c2] = v;
+	else if (c1 == 'D' && c2 < 8)
+		regs.regs[c2] = v;
+	else if (c1 == 'P' && c2 == 0)
+		regs.irc = v;
+	else if (c1 == 'P' && c2 == 1)
+		regs.ir = v;
+	else if (!_tcscmp (parm, _T("SR"))) {
+		regs.sr = v;
+		MakeFromSR ();
+	} else if (!_tcscmp (parm, _T("CCR"))) {
+		regs.sr = (regs.sr & ~31) | (v & 31);
+		MakeFromSR ();
+	} else if (!_tcscmp (parm, _T("USP"))) {
+		regs.usp = v;
+	} else if (!_tcscmp (parm, _T("ISP"))) {
+		regs.isp = v;
+	} else if (!_tcscmp (parm, _T("PC"))) {
+		m68k_setpc (v);
+		fill_prefetch ();
+	} else {
+		for (i = 0; m2cregs[i].regname; i++) {
+			if (!_tcscmp (parm, m2cregs[i].regname))
+				val_move2c2 (m2cregs[i].regno, v);
+		}
+	}
+}
+
+static void ppc_disasm(uaecptr addr, uaecptr *nextpc, int cnt)
+{
+	PPCD_CB disa;
+
+	while(cnt-- > 0) {
+		uae_u32 instr = get_long_debug(addr);
+		disa.pc = addr;
+		disa.instr = instr;
+		PPCDisasm(&disa);
+		TCHAR *mnemo = au(disa.mnemonic);
+		TCHAR *ops = au(disa.operands);
+		console_out_f(_T("%08X  %08X  %-12s%-30s\n"), addr, instr, mnemo, ops);
+		xfree(ops);
+		xfree(mnemo);
+		addr += 4;
+	}
+	if (nextpc)
+		*nextpc = addr;
+}
+
+static uaecptr nxdis, nxmem;
+static bool ppcmode;
+
+static BOOL debug_line (TCHAR *input)
+{
+	TCHAR cmd, *inptr;
+	uaecptr addr;
+
+	inptr = input;
+	cmd = next_char (&inptr);
+
+	switch (cmd)
+	{
+		case 'c': dumpcia (); dumpdisk (); dumpcustom (); break;
+		case 'i':
+		{
+			if (*inptr == 'l') {
+				next_char (&inptr);
+				if (more_params (&inptr)) {
+					debug_illegal_mask = readhex (&inptr);
+				} else {
+					debug_illegal_mask = debug_illegal ? 0 : -1;
+					debug_illegal_mask &= ~((uae_u64)255 << 24); // mask interrupts
+				}
+				console_out_f (_T("Exception breakpoint mask: %0I64X\n"), debug_illegal_mask);
+				debug_illegal = debug_illegal_mask ? 1 : 0;
+			} else {
+				addr = 0xffffffff;
+				if (more_params (&inptr))
+					addr = readhex (&inptr);
+				dump_vectors (addr);
+			}
+			break;
+		}
+		case 'e': dump_custom_regs (tolower(*inptr) == 'a'); break;
+		case 'r':
+			{
+				if (*inptr == 'c')
+					m68k_dumpcache ();
+				else if (more_params(&inptr))
+					m68k_modify (&inptr);
+				else
+					m68k_dumpstate (&nextpc);
+			}
+			break;
+		case 'D': deepcheatsearch (&inptr); break;
+		case 'C': cheatsearch (&inptr); break;
+		case 'W': writeintomem (&inptr); break;
+		case 'w': memwatch (&inptr); break;
+		case 'S': savemem (&inptr); break;
+		case 's':
+			if (*inptr == 'c') {
+				screenshot (1, 1);
+			} else if (*inptr == 'p') {
+				inptr++;
+				debug_sprite (&inptr);
+			} else if (*inptr == 'm') {
+				if (*(inptr + 1) == 'c') {
+					next_char (&inptr);
+					next_char (&inptr);
+					if (!smc_table)
+						smc_detect_init (&inptr);
+					else
+						smc_free ();
+				}
+			} else {
+				searchmem (&inptr);
+			}
+			break;
+		case 'd':
+			{
+				if (*inptr == 'i') {
+					next_char (&inptr);
+					disk_debug (&inptr);
+				} else if (*inptr == 'j') {
+					inptr++;
+					inputdevice_logging = 1 | 2;
+					if (more_params (&inptr))
+						inputdevice_logging = readint (&inptr);
+					console_out_f (_T("Input logging level %d\n"), inputdevice_logging);
+				} else if (*inptr == 'm') {
+					memory_map_dump_2 (0);
+				} else if (*inptr == 't') {
+					next_char (&inptr);
+					debugtest_set (&inptr);
+#ifdef _WIN32
+				} else if (*inptr == 'g') {
+					extern void update_disassembly (uae_u32);
+					next_char (&inptr);
+					if (more_params (&inptr))
+						update_disassembly (readhex (&inptr));
+#endif
+				} else {
+					uae_u32 daddr;
+					int count;
+					if (*inptr == 'p') {
+						ppcmode = true;
+						next_char(&inptr);
+					} else if(*inptr == 'o') {
+						ppcmode = false;
+						next_char(&inptr);
+					}
+					if (more_params (&inptr))
+						daddr = readhex (&inptr);
+					else
+						daddr = nxdis;
+					if (more_params (&inptr))
+						count = readhex (&inptr);
+					else
+						count = 10;
+					if (ppcmode) {
+						ppc_disasm(daddr, &nxdis, count);
+					} else {
+						m68k_disasm (daddr, &nxdis, count);
+					}
+				}
+			}
+			break;
+		case 'T':
+			if (inptr[0] == 't' || inptr[0] == 0)
+				show_exec_tasks ();
+			else
+				show_exec_lists (&inptr[0]);
+			break;
+		case 't':
+			no_trace_exceptions = 0;
+			if (*inptr != 't') {
+				if (more_params (&inptr))
+					skipaddr_doskip = readint (&inptr);
+				if (skipaddr_doskip <= 0 || skipaddr_doskip > 10000)
+					skipaddr_doskip = 1;
+			} else {
+				no_trace_exceptions = 1;
+			}
+			set_special (SPCFLAG_BRK);
+			exception_debugging = 1;
+			return true;
+		case 'z':
+			skipaddr_start = nextpc;
+			skipaddr_doskip = 1;
+			do_skip = 1;
+			exception_debugging = 1;
+			return true;
+
+		case 'f':
+			if (inptr[0] == 'a') {
+				next_char (&inptr);
+				find_ea (&inptr);
+			} else if (inptr[0] == 'p') {
+				inptr++;
+				if (process_breakpoint (&inptr))
+					return true;
+			} else if (inptr[0] == 'c' || inptr[0] == 's') {
+				if (cycle_breakpoint(&inptr))
+					return true;
+			} else if (inptr[0] == 'e' && inptr[1] == 'n') {
+				break_if_enforcer = break_if_enforcer ? false : true;
+				console_out_f(_T("Break when enforcer hit: %s\n"), break_if_enforcer ? _T("enabled") : _T("disabled"));
+			} else {
+				if (instruction_breakpoint (&inptr))
+					return true;
+			}
+			break;
+
+		case 'q':
+			uae_quit();
+			deactivate_debugger();
+			return true;
+
+		case 'g':
+			if (more_params (&inptr)) {
+				m68k_setpc (readhex (&inptr));
+				fill_prefetch ();
+			}
+			deactivate_debugger();
+			return true;
+
+		case 'x':
+			if (_totupper(inptr[0]) == 'X') {
+				debugger_change(-1);
+			} else {
+				deactivate_debugger();
+				close_console();
+				return true;
+			}
+			break;
+
+		case 'H':
+			{
+				int count, temp, badly, skip;
+				uae_u32 addr = 0;
+				uae_u32 oldpc = m68k_getpc ();
+				struct regstruct save_regs = regs;
+
+				badly = 0;
+				if (inptr[0] == 'H') {
+					badly = 1;
+					inptr++;
+				}
+
+				if (more_params(&inptr))
+					count = readint (&inptr);
+				else
+					count = 10;
+				if (count > 1000) {
+					addr = count;
+					count = MAX_HIST;
+				}
+				if (count < 0)
+					break;
+				skip = count;
+				if (more_params (&inptr))
+					skip = count - readint (&inptr);
+
+				temp = lasthist;
+				while (count-- > 0 && temp != firsthist) {
+					if (temp == 0)
+						temp = MAX_HIST - 1;
+					else
+						temp--;
+				}
+				while (temp != lasthist) {
+					regs = history[temp];
+					if (history[temp].pc == addr || addr == 0) {
+						m68k_setpc (history[temp].pc);
+						if (badly) {
+							m68k_dumpstate (NULL);
+						} else {
+							console_out_f(_T("%2d "), history[temp].intmask ? history[temp].intmask : (history[temp].s ? -1 : 0));
+							m68k_disasm (history[temp].pc, NULL, 1);
+						}
+						if (addr && history[temp].pc == addr)
+							break;
+					}
+					if (skip-- < 0)
+						break;
+					if (++temp == MAX_HIST)
+						temp = 0;
+				}
+				regs = save_regs;
+				m68k_setpc (oldpc);
+			}
+			break;
+		case 'M':
+			if (more_params (&inptr)) {
+				switch (next_char (&inptr))
+				{
+				case 'a':
+					if (more_params (&inptr))
+						audio_channel_mask = readhex (&inptr);
+					console_out_f (_T("Audio mask = %02X\n"), audio_channel_mask);
+					break;
+				case 's':
+					if (more_params (&inptr))
+						debug_sprite_mask = readhex (&inptr);
+					console_out_f (_T("Sprite mask: %02X\n"), debug_sprite_mask);
+					break;
+				case 'b':
+					if (more_params (&inptr)) {
+						debug_bpl_mask = readhex (&inptr) & 0xff;
+						if (more_params (&inptr))
+							debug_bpl_mask_one = readhex (&inptr) & 0xff;
+						notice_screen_contents_lost ();
+					}
+					console_out_f (_T("Bitplane mask: %02X (%02X)\n"), debug_bpl_mask, debug_bpl_mask_one);
+					break;
+				}
+			}
+			break;
+		case 'm':
+			{
+				uae_u32 maddr;
+				int lines;
+#ifdef _WIN32
+				if (*inptr == 'g') {
+					extern void update_memdump (uae_u32);
+					next_char (&inptr);
+					if (more_params (&inptr))
+						update_memdump (readhex (&inptr));
+					break;
+				}
+#endif
+				if (*inptr == 'm' && inptr[1] == 'u') {
+					if (currprefs.mmu_model) {
+						inptr += 2;
+						if (more_params (&inptr))
+							debug_mmu_mode = readint (&inptr);
+						else
+							debug_mmu_mode = 0;
+						console_out_f (_T("MMU translation function code = %d\n"), debug_mmu_mode);
+					}
+					break;
+				}
+				if (more_params (&inptr)) {
+					maddr = readhex (&inptr);
+				} else {
+					maddr = nxmem;
+				}
+				if (more_params (&inptr))
+					lines = readhex (&inptr);
+				else
+					lines = 20;
+				dumpmem (maddr, &nxmem, lines);
+			}
+			break;
+		case 'v':
+		case 'V':
+			{
+				int v1 = vpos, v2 = 0;
+				if (more_params (&inptr))
+					v1 = readint (&inptr);
+				if (more_params (&inptr))
+					v2 = readint (&inptr);
+				if (debug_dma) {
+					decode_dma_record (v2, v1, cmd == 'v', false);
+				} else {
+					debug_dma = v1 < 0 ? -v1 : 1;
+					console_out_f (_T("DMA debugger enabled, mode=%d.\n"), debug_dma);
+				}
+			}
+			break;
+		case 'o':
+			{
+				if (copper_debugger (&inptr)) {
+					debugger_active = 0;
+					debugging = 0;
+					return true;
+				}
+				break;
+			}
+		case 'O':
+			break;
+		case 'b':
+			if (staterecorder (&inptr))
+				return true;
+			break;
+		case 'U':
+			if (currprefs.mmu_model && more_params (&inptr)) {
+				int i;
+				uaecptr addrl = readhex (&inptr);
+				uaecptr addrp;
+				console_out_f (_T("%08X translates to:\n"), addrl);
+				for (i = 0; i < 4; i++) {
+					bool super = (i & 2) != 0;
+					bool data = (i & 1) != 0;
+					console_out_f (_T("S%dD%d="), super, data);
+					TRY(prb) {
+						if (currprefs.mmu_model >= 68040)
+							addrp = mmu_translate (addrl, super, data, false);
+						else
+							addrp = mmu030_translate (addrl, super, data, false);
+						console_out_f (_T("%08X"), addrp);
+						TRY(prb2) {
+							if (currprefs.mmu_model >= 68040)
+								addrp = mmu_translate (addrl, super, data, true);
+							else
+								addrp = mmu030_translate (addrl, super, data, true);
+							console_out_f (_T(" RW"));
+						} CATCH(prb2) {
+							console_out_f (_T(" RO"));
+						} ENDTRY
+					} CATCH(prb) {
+						console_out_f (_T("***********"));
+					} ENDTRY
+					console_out_f (_T(" "));
+				}
+				console_out_f (_T("\n"));
+			}
+			break;
+		case 'h':
+		case '?':
+			if (more_params (&inptr))
+				converter (&inptr);
+			else
+				debug_help ();
+			break;
+	}
+	return false;
+}
+
+static void debug_1 (void)
+{
+	TCHAR input[MAX_LINEWIDTH];
+
+	m68k_dumpstate (&nextpc);
+	nxdis = nextpc; nxmem = 0;
+	debugger_active = 1;
+
+	for (;;) {
+		int v;
+
+		if (!debugger_active)
+			return;
+		update_debug_info ();
+		console_out (_T(">"));
+		console_flush ();
+		debug_linecounter = 0;
+		v = console_get (input, MAX_LINEWIDTH);
+		if (v < 0)
+			return;
+		if (v == 0)
+			continue;
+		if (debug_line (input))
+			return;
+	}
+}
+
+static void addhistory (void)
+{
+	uae_u32 pc = m68k_getpc ();
+	//    if (!notinrom())
+	//	return;
+	history[lasthist] = regs;
+	history[lasthist].pc = m68k_getpc ();
+	if (++lasthist == MAX_HIST)
+		lasthist = 0;
+	if (lasthist == firsthist) {
+		if (++firsthist == MAX_HIST) firsthist = 0;
+	}
+}
+
+static void debug_continue(void)
+{
+	set_special (SPCFLAG_BRK);
+}
+
+
+void debug (void)
+{
+	int i;
+	int wasactive;
+
+	if (savestate_state)
+		return;
+
+	bogusframe = 1;
+	addhistory ();
+
+#if 0
+	if (do_skip && skipaddr_start == 0xC0DEDBAD) {
+		if (trace_same_insn_count > 0) {
+			if (memcmp (trace_insn_copy, regs.pc_p, 10) == 0
+				&& memcmp (trace_prev_regs.regs, regs.regs, sizeof regs.regs) == 0)
+			{
+				trace_same_insn_count++;
+				return;
+			}
+		}
+		if (trace_same_insn_count > 1)
+			fprintf (logfile, "[ repeated %d times ]\n", trace_same_insn_count);
+		m68k_dumpstate (logfile, &nextpc);
+		trace_same_insn_count = 1;
+		memcpy (trace_insn_copy, regs.pc_p, 10);
+		memcpy (&trace_prev_regs, ®s, sizeof regs);
+	}
+#endif
+
+	if (!memwatch_triggered) {
+		if (do_skip) {
+			uae_u32 pc;
+			uae_u16 opcode;
+			int bp = 0;
+
+			pc = munge24 (m68k_getpc ());
+			opcode = currprefs.cpu_model < 68020 && (currprefs.cpu_compatible || currprefs.cpu_cycle_exact) ? regs.ir : get_word_debug (pc);
+
+			for (i = 0; i < BREAKPOINT_TOTAL; i++) {
+				if (!bpnodes[i].enabled)
+					continue;
+				if (bpnodes[i].addr == pc) {
+					bp = 1;
+					console_out_f (_T("Breakpoint at %08X\n"), pc);
+					break;
+				}
+			}
+
+			if (skipaddr_doskip) {
+				if (skipaddr_start == pc)
+					bp = 1;
+				if ((processptr || processname) && notinrom()) {
+					uaecptr execbase = get_long_debug (4);
+					uaecptr activetask = get_long_debug (execbase + 276);
+					int process = get_byte_debug (activetask + 8) == 13 ? 1 : 0;
+					char *name = (char*)get_real_address (get_long_debug (activetask + 10));
+					if (process) {
+						uaecptr cli = BPTR2APTR(get_long_debug (activetask + 172));
+						uaecptr seglist = 0;
+
+						uae_char *command = NULL;
+						if (cli) {
+							if (processname)
+								command = (char*)get_real_address (BPTR2APTR(get_long_debug (cli + 16)));
+							seglist = BPTR2APTR(get_long_debug (cli + 60));
+						} else {
+							seglist = BPTR2APTR(get_long_debug (activetask + 128));
+							seglist = BPTR2APTR(get_long_debug (seglist + 12));
+						}
+						if (activetask == processptr || (processname && (!stricmp (name, processname) || (command && command[0] && !strnicmp (command + 1, processname, command[0]) && processname[command[0]] == 0)))) {
+							while (seglist) {
+								uae_u32 size = get_long_debug (seglist - 4) - 4;
+								if (pc >= (seglist + 4) && pc < (seglist + size)) {
+									bp = 1;
+									break;
+								}
+								seglist = BPTR2APTR(get_long_debug (seglist));
+							}
+						}
+					}
+				} else if (skipins != 0xffffffff) {
+					if (skipins == 0x10000) {
+						if (opcode == 0x4e75 || opcode == 0x4e73 || opcode == 0x4e77)
+							bp = 1;
+					} else if (opcode == skipins)
+						bp = 1;
+				} else if (skipaddr_start == 0xffffffff && skipaddr_doskip < 0) {
+					if ((pc < 0xe00000 || pc >= 0x1000000) && opcode != 0x4ef9)
+						bp = 1;
+				} else if (skipaddr_start == 0xffffffff && skipaddr_doskip > 0) {
+					bp = 1;
+				} else if (skipaddr_end != 0xffffffff) {
+					if (pc >= skipaddr_start && pc < skipaddr_end)
+						bp = 1;
+				}
+			}
+			if (sr_bpmask || sr_bpvalue) {
+				MakeSR ();
+				if ((regs.sr & sr_bpmask) == sr_bpvalue) {
+					console_out (_T("SR breakpoint\n"));
+					bp = 1;
+				}
+			}
+			if (!bp) {
+				debug_continue();
+				return;
+			}
+		}
+	} else {
+		console_out_f (_T("Memwatch %d: break at %08X.%c %c%c%c %08X PC=%08X "), memwatch_triggered - 1, mwhit.addr,
+			mwhit.size == 1 ? 'B' : (mwhit.size == 2 ? 'W' : 'L'),
+			(mwhit.rwi & 1) ? 'R' : ' ', (mwhit.rwi & 2) ? 'W' : ' ', (mwhit.rwi & 4) ? 'I' : ' ',
+			mwhit.val, mwhit.pc);
+		for (i = 0; memwatch_access_masks[i].mask; i++) {
+			if (mwhit.access_mask == memwatch_access_masks[i].mask)
+				console_out_f (_T("%s (%03x)\n"), memwatch_access_masks[i].name, mwhit.reg);
+		}
+		memwatch_triggered = 0;
+	}
+	if (skipaddr_doskip > 0) {
+		skipaddr_doskip--;
+		if (skipaddr_doskip > 0) {
+			debug_continue();
+			return;
+		}
+	}
+
+	wasactive = ismouseactive ();
+#ifdef WITH_PPC
+	uae_ppc_pause(1);
+#endif
+	inputdevice_unacquire ();
+	pause_sound ();
+	setmouseactive (0);
+	activate_console ();
+	do_skip = 0;
+	skipaddr_start = 0xffffffff;
+	skipaddr_end = 0xffffffff;
+	skipins = 0xffffffff;
+	skipaddr_doskip = 0;
+	exception_debugging = 0;
+	debug_rewind = 0;
+	processptr = 0;
+#if 0
+	if (!currprefs.statecapture) {
+		changed_prefs.statecapture = currprefs.statecapture = 1;
+		savestate_init ();
+	}
+#endif
+	debug_1 ();
+	if (!debug_rewind && !currprefs.cachesize
+#ifdef FILESYS
+		&& nr_units () == 0
+#endif
+		) {
+			savestate_capture (1);
+	}
+	for (i = 0; i < BREAKPOINT_TOTAL; i++) {
+		if (bpnodes[i].enabled)
+			do_skip = 1;
+	}
+	if (sr_bpmask || sr_bpvalue)
+		do_skip = 1;
+	if (do_skip) {
+		set_special (SPCFLAG_BRK);
+		debugging = -1;
+	}
+	resume_sound ();
+	inputdevice_acquire (TRUE);
+#ifdef WITH_PPC
+	uae_ppc_pause(0);
+#endif
+	setmouseactive (wasactive ? 2 : 0);
+}
+
+const TCHAR *debuginfo (int mode)
+{
+	static TCHAR txt[100];
+	uae_u32 pc = M68K_GETPC;
+	_stprintf (txt, _T("PC=%08X INS=%04X %04X %04X"),
+		pc, get_word_debug (pc), get_word_debug (pc + 2), get_word_debug (pc + 4));
+	return txt;
+}
+
+#endif	/* WINUAE_FOR_HATARI */
+
+void mmu_disasm (uaecptr pc, int lines)
+{
+	debug_mmu_mode = regs.s ? 6 : 2;
+	m68k_dumpstate (0xffffffff, NULL);
+	m68k_disasm (pc, NULL, lines);
+}
+
+static int mmu_logging;
+
+#define MMU_PAGE_SHIFT 16
+
+struct mmudata {
+	uae_u32 flags;
+	uae_u32 addr;
+	uae_u32 len;
+	uae_u32 remap;
+	uae_u32 p_addr;
+};
+
+static struct mmudata *mmubanks;
+static uae_u32 mmu_struct, mmu_callback, mmu_regs;
+static uae_u32 mmu_fault_bank_addr, mmu_fault_addr;
+static int mmu_fault_size, mmu_fault_rw;
+static int mmu_slots;
+static struct regstruct mmur;
+
+struct mmunode {
+	struct mmudata *mmubank;
+	struct mmunode *next;
+};
+static struct mmunode **mmunl;
+extern regstruct mmu_backup_regs;
+
+#define MMU_READ_U (1 << 0)
+#define MMU_WRITE_U (1 << 1)
+#define MMU_READ_S (1 << 2)
+#define MMU_WRITE_S (1 << 3)
+#define MMU_READI_U (1 << 4)
+#define MMU_READI_S (1 << 5)
+
+#define MMU_MAP_READ_U (1 << 8)
+#define MMU_MAP_WRITE_U (1 << 9)
+#define MMU_MAP_READ_S (1 << 10)
+#define MMU_MAP_WRITE_S (1 << 11)
+#define MMU_MAP_READI_U (1 << 12)
+#define MMU_MAP_READI_S (1 << 13)
+
+void mmu_do_hit (void)
+{
+	int i;
+	uaecptr p;
+	uae_u32 pc;
+
+	mmu_triggered = 0;
+	pc = m68k_getpc ();
+	p = mmu_regs + 18 * 4;
+	put_long (p, pc);
+	regs = mmu_backup_regs;
+	regs.intmask = 7;
+	regs.t0 = regs.t1 = 0;
+	if (!regs.s) {
+		regs.usp = m68k_areg (regs, 7);
+		if (currprefs.cpu_model >= 68020)
+			m68k_areg (regs, 7) = regs.m ? regs.msp : regs.isp;
+		else
+			m68k_areg (regs, 7) = regs.isp;
+		regs.s = 1;
+	}
+	MakeSR ();
+	m68k_setpc (mmu_callback);
+	fill_prefetch ();
+
+	if (currprefs.cpu_model > 68000) {
+		for (i = 0 ; i < 9; i++) {
+			m68k_areg (regs, 7) -= 4;
+			put_long (m68k_areg (regs, 7), 0);
+		}
+		m68k_areg (regs, 7) -= 4;
+		put_long (m68k_areg (regs, 7), mmu_fault_addr);
+		m68k_areg (regs, 7) -= 2;
+		put_word (m68k_areg (regs, 7), 0); /* WB1S */
+		m68k_areg (regs, 7) -= 2;
+		put_word (m68k_areg (regs, 7), 0); /* WB2S */
+		m68k_areg (regs, 7) -= 2;
+		put_word (m68k_areg (regs, 7), 0); /* WB3S */
+		m68k_areg (regs, 7) -= 2;
+		put_word (m68k_areg (regs, 7),
+			(mmu_fault_rw ? 0 : 0x100) | (mmu_fault_size << 5)); /* SSW */
+		m68k_areg (regs, 7) -= 4;
+		put_long (m68k_areg (regs, 7), mmu_fault_bank_addr);
+		m68k_areg (regs, 7) -= 2;
+		put_word (m68k_areg (regs, 7), 0x7002);
+	}
+	m68k_areg (regs, 7) -= 4;
+	put_long (m68k_areg (regs, 7), get_long_debug (p - 4));
+	m68k_areg (regs, 7) -= 2;
+	put_word (m68k_areg (regs, 7), mmur.sr);
+#ifdef JIT
+	set_special(SPCFLAG_END_COMPILE);
+#endif
+}
+
+static void mmu_do_hit_pre (struct mmudata *md, uaecptr addr, int size, int rwi, uae_u32 v)
+{
+	uae_u32 p, pc;
+	int i;
+
+	mmur = regs;
+	pc = m68k_getpc ();
+	if (mmu_logging)
+		console_out_f (_T("MMU: hit %08X SZ=%d RW=%d V=%08X PC=%08X\n"), addr, size, rwi, v, pc);
+
+	p = mmu_regs;
+	put_long (p, 0); p += 4;
+	for (i = 0; i < 16; i++) {
+		put_long (p, regs.regs[i]);
+		p += 4;
+	}
+	put_long (p, pc); p += 4;
+	put_long (p, 0); p += 4;
+	put_long (p, regs.usp); p += 4;
+	put_long (p, regs.isp); p += 4;
+	put_long (p, regs.msp); p += 4;
+	put_word (p, regs.sr); p += 2;
+	put_word (p, (size << 1) | ((rwi & 2) ? 1 : 0)); /* size and rw */ p += 2;
+	put_long (p, addr); /* fault address */ p += 4;
+	put_long (p, md->p_addr); /* bank address */ p += 4;
+	put_long (p, v); p += 4;
+	mmu_fault_addr = addr;
+	mmu_fault_bank_addr = md->p_addr;
+	mmu_fault_size = size;
+	mmu_fault_rw = rwi;
+	mmu_triggered = 1;
+}
+
+static int mmu_hit (uaecptr addr, int size, int rwi, uae_u32 *v)
+{
+	int s, trig;
+	uae_u32 flags;
+	struct mmudata *md;
+	struct mmunode *mn;
+
+	if (mmu_triggered)
+		return 1;
+
+	mn = mmunl[addr >> MMU_PAGE_SHIFT];
+	if (mn == NULL)
+		return 0;
+
+	s = regs.s;
+	while (mn) {
+		md = mn->mmubank;
+		if (addr >= md->addr && addr < md->addr + md->len) {
+			flags = md->flags;
+			if (flags & (MMU_MAP_READ_U | MMU_MAP_WRITE_U | MMU_MAP_READ_S | MMU_MAP_WRITE_S | MMU_MAP_READI_U | MMU_MAP_READI_S)) {
+				trig = 0;
+				if (!s && (flags & MMU_MAP_READ_U) && (rwi & 1))
+					trig = 1;
+				if (!s && (flags & MMU_MAP_WRITE_U) && (rwi & 2))
+					trig = 1;
+				if (s && (flags & MMU_MAP_READ_S) && (rwi & 1))
+					trig = 1;
+				if (s && (flags & MMU_MAP_WRITE_S) && (rwi & 2))
+					trig = 1;
+				if (!s && (flags & MMU_MAP_READI_U) && (rwi & 4))
+					trig = 1;
+				if (s && (flags & MMU_MAP_READI_S) && (rwi & 4))
+					trig = 1;
+				if (trig) {
+					uaecptr maddr = md->remap + (addr - md->addr);
+					if (maddr == addr) /* infinite mmu hit loop? no thanks.. */
+						return 1;
+					if (mmu_logging)
+						console_out_f (_T("MMU: remap %08X -> %08X SZ=%d RW=%d\n"), addr, maddr, size, rwi);
+					if ((rwi & 2)) {
+						switch (size)
+						{
+						case 4:
+							put_long (maddr, *v);
+							break;
+						case 2:
+							put_word (maddr, *v);
+							break;
+						case 1:
+							put_byte (maddr, *v);
+							break;
+						}
+					} else {
+						switch (size)
+						{
+						case 4:
+							*v = get_long_debug (maddr);
+							break;
+						case 2:
+							*v = get_word_debug (maddr);
+							break;
+						case 1:
+							*v = get_byte_debug (maddr);
+							break;
+						}
+					}
+					return 1;
+				}
+			}
+			if (flags & (MMU_READ_U | MMU_WRITE_U | MMU_READ_S | MMU_WRITE_S | MMU_READI_U | MMU_READI_S)) {
+				trig = 0;
+				if (!s && (flags & MMU_READ_U) && (rwi & 1))
+					trig = 1;
+				if (!s && (flags & MMU_WRITE_U) && (rwi & 2))
+					trig = 1;
+				if (s && (flags & MMU_READ_S) && (rwi & 1))
+					trig = 1;
+				if (s && (flags & MMU_WRITE_S) && (rwi & 2))
+					trig = 1;
+				if (!s && (flags & MMU_READI_U) && (rwi & 4))
+					trig = 1;
+				if (s && (flags & MMU_READI_S) && (rwi & 4))
+					trig = 1;
+				if (trig) {
+					mmu_do_hit_pre (md, addr, size, rwi, *v);
+					return 1;
+				}
+			}
+		}
+		mn = mn->next;
+	}
+	return 0;
+}
+
+static void mmu_free_node(struct mmunode *mn)
+{
+	if (!mn)
+		return;
+	mmu_free_node (mn->next);
+	xfree (mn);
+}
+
+static void mmu_free(void)
+{
+	struct mmunode *mn;
+	int i;
+
+	for (i = 0; i < mmu_slots; i++) {
+		mn = mmunl[i];
+		mmu_free_node (mn);
+	}
+	xfree (mmunl);
+	mmunl = NULL;
+	xfree (mmubanks);
+	mmubanks = NULL;
+}
+
+static int getmmubank(struct mmudata *snptr, uaecptr p)
+{
+	snptr->flags = get_long_debug (p);
+	if (snptr->flags == 0xffffffff)
+		return 1;
+	snptr->addr = get_long_debug (p + 4);
+	snptr->len = get_long_debug (p + 8);
+	snptr->remap = get_long_debug (p + 12);
+	snptr->p_addr = p;
+	return 0;
+}
+
+int mmu_init(int mode, uaecptr parm, uaecptr parm2)
+{
+	uaecptr p, p2, banks;
+	int size;
+	struct mmudata *snptr;
+	struct mmunode *mn;
+	static int wasjit;
+#ifdef JIT
+	if (currprefs.cachesize) {
+		wasjit = currprefs.cachesize;
+		changed_prefs.cachesize = 0;
+		console_out (_T("MMU: JIT disabled\n"));
+		check_prefs_changed_comp ();
+	}
+	if (mode == 0) {
+		if (mmu_enabled) {
+			mmu_free ();
+			deinitialize_memwatch ();
+			console_out (_T("MMU: disabled\n"));
+			changed_prefs.cachesize = wasjit;
+		}
+		mmu_logging = 0;
+		return 1;
+	}
+#endif
+
+	if (mode == 1) {
+		if (!mmu_enabled)
+			return 0xffffffff;
+		return mmu_struct;
+	}
+
+	p = parm;
+	mmu_struct = p;
+	if (get_long_debug (p) != 1) {
+		console_out_f (_T("MMU: version mismatch %d <> %d\n"), get_long_debug (p), 1);
+		return 0;
+	}
+	p += 4;
+	mmu_logging = get_long_debug (p) & 1;
+	p += 4;
+	mmu_callback = get_long_debug (p);
+	p += 4;
+	mmu_regs = get_long_debug (p);
+	p += 4;
+
+	if (mode == 3) {
+		int off;
+		uaecptr addr = get_long_debug (parm2 + 4);
+		if (!mmu_enabled)
+			return 0;
+		off = addr >> MMU_PAGE_SHIFT;
+		mn = mmunl[off];
+		while (mn) {
+			if (mn->mmubank->p_addr == parm2) {
+				getmmubank(mn->mmubank, parm2);
+				if (mmu_logging)
+					console_out_f (_T("MMU: bank update %08X: %08X - %08X %08X\n"),
+					mn->mmubank->flags, mn->mmubank->addr, mn->mmubank->len + mn->mmubank->addr,
+					mn->mmubank->remap);
+			}
+			mn = mn->next;
+		}
+		return 1;
+	}
+
+	mmu_slots = 1 << ((currprefs.address_space_24 ? 24 : 32) - MMU_PAGE_SHIFT);
+	mmunl = xcalloc (struct mmunode*, mmu_slots);
+	size = 1;
+	p2 = get_long_debug (p);
+	while (get_long_debug (p2) != 0xffffffff) {
+		p2 += 16;
+		size++;
+	}
+	p = banks = get_long_debug (p);
+	snptr = mmubanks = xmalloc (struct mmudata, size);
+	for (;;) {
+		int off;
+		if (getmmubank(snptr, p))
+			break;
+		p += 16;
+		off = snptr->addr >> MMU_PAGE_SHIFT;
+		if (mmunl[off] == NULL) {
+			mn = mmunl[off] = xcalloc (struct mmunode, 1);
+		} else {
+			mn = mmunl[off];
+			while (mn->next)
+				mn = mn->next;
+			mn = mn->next = xcalloc (struct mmunode, 1);
+		}
+		mn->mmubank = snptr;
+		snptr++;
+	}
+
+	initialize_memwatch (1);
+	console_out_f (_T("MMU: enabled, %d banks, CB=%08X S=%08X BNK=%08X SF=%08X, %d*%d\n"),
+		size - 1, mmu_callback, parm, banks, mmu_regs, mmu_slots, 1 << MMU_PAGE_SHIFT);
+	set_special (SPCFLAG_BRK);
+	return 1;
+}
+
+void debug_parser (const TCHAR *cmd, TCHAR *out, uae_u32 outsize)
+{
+	TCHAR empty[2] = { 0 };
+	TCHAR *input = my_strdup (cmd);
+	if (out == NULL && outsize == 0) {
+		setconsolemode (empty, 1);
+	} else if (out != NULL && outsize > 0) {
+		out[0] = 0;
+		setconsolemode (out, outsize);
+	}
+	debug_line (input);
+	setconsolemode (NULL, 0);
+	xfree (input);
+}
+
+#endif
diff --git a/src/cpu/debug.h b/src/cpu/debug.h
new file mode 100644
index 0000000..da58c2f
--- /dev/null
+++ b/src/cpu/debug.h
@@ -0,0 +1,177 @@
+ /*
+  * UAE - The Un*x Amiga Emulator
+  *
+  * Debugger
+  *
+  * (c) 1995 Bernd Schmidt
+  *
+  */
+
+#ifdef DEBUGGER
+
+#define	MAX_HIST 500
+#define MAX_LINEWIDTH 100
+
+extern int debugging;
+extern int memwatch_enabled;
+extern int exception_debugging;
+extern int debug_copper;
+extern int debug_dma;
+extern int debug_sprite_mask;
+extern int debug_bpl_mask, debug_bpl_mask_one;
+extern int debugger_active;
+extern int debug_illegal;
+extern uae_u64 debug_illegal_mask;
+
+extern void debug (void);
+extern void debugger_change (int mode);
+extern void activate_debugger (void);
+extern void deactivate_debugger (void);
+extern int notinrom (void);
+extern const TCHAR *debuginfo (int);
+extern void record_copper (uaecptr addr, uae_u16 word1, uae_u16 word2, int hpos, int vpos);
+extern void record_copper_blitwait (uaecptr addr, int hpos, int vpos);
+extern void record_copper_reset (void);
+extern int mmu_init (int, uaecptr,uaecptr);
+extern void mmu_do_hit (void);
+extern void dump_aga_custom (void);
+extern void memory_map_dump (void);
+extern void debug_help (void);
+extern uaecptr dumpmem2 (uaecptr addr, TCHAR *out, int osize);
+extern void update_debug_info (void);
+extern int instruction_breakpoint (TCHAR **c);
+extern int debug_bankchange (int);
+extern void log_dma_record (void);
+extern void debug_parser (const TCHAR *cmd, TCHAR *out, uae_u32 outsize);
+extern void mmu_disasm (uaecptr pc, int lines);
+extern int debug_read_memory_16 (uaecptr addr);
+extern int debug_peek_memory_16 (uaecptr addr);
+extern int debug_read_memory_8 (uaecptr addr);
+extern int debug_peek_memory_8 (uaecptr addr);
+extern int debug_write_memory_16 (uaecptr addr, uae_u16 v);
+extern int debug_write_memory_8 (uaecptr addr, uae_u8 v);
+extern bool debug_enforcer(void);
+
+#define BREAKPOINT_TOTAL 20
+struct breakpoint_node {
+    uaecptr addr;
+    int enabled;
+};
+extern struct breakpoint_node bpnodes[BREAKPOINT_TOTAL];
+
+#define MW_MASK_CPU				0x00000001
+#define MW_MASK_BLITTER_A		0x00000002
+#define MW_MASK_BLITTER_B		0x00000004
+#define MW_MASK_BLITTER_C		0x00000008
+#define MW_MASK_BLITTER_D		0x00000010
+#define MW_MASK_COPPER			0x00000020
+#define MW_MASK_DISK			0x00000040
+#define MW_MASK_AUDIO_0			0x00000080
+#define MW_MASK_AUDIO_1			0x00000100
+#define MW_MASK_AUDIO_2			0x00000200
+#define MW_MASK_AUDIO_3			0x00000400
+#define MW_MASK_BPL_0			0x00000800
+#define MW_MASK_BPL_1			0x00001000
+#define MW_MASK_BPL_2			0x00002000
+#define MW_MASK_BPL_3			0x00004000
+#define MW_MASK_BPL_4			0x00008000
+#define MW_MASK_BPL_5			0x00010000
+#define MW_MASK_BPL_6			0x00020000
+#define MW_MASK_BPL_7			0x00040000
+#define MW_MASK_SPR_0			0x00080000
+#define MW_MASK_SPR_1			0x00100000
+#define MW_MASK_SPR_2			0x00200000
+#define MW_MASK_SPR_3			0x00400000
+#define MW_MASK_SPR_4			0x00800000
+#define MW_MASK_SPR_5			0x01000000
+#define MW_MASK_SPR_6			0x02000000
+#define MW_MASK_SPR_7			0x04000000
+#define MW_MASK_ALL				(0x08000000 - 1)
+
+#define MEMWATCH_TOTAL 20
+struct memwatch_node {
+	uaecptr addr;
+	int size;
+	int rwi;
+	uae_u32 val, val_mask, access_mask;
+	int val_size, val_enabled;
+	int mustchange;
+	uae_u32 modval;
+	int modval_written;
+	int frozen;
+	uae_u32 reg;
+	uaecptr pc;
+};
+extern struct memwatch_node mwnodes[MEMWATCH_TOTAL];
+
+extern void memwatch_dump2 (TCHAR *buf, int bufsize, int num);
+
+uae_u16 debug_wgetpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int reg);
+uae_u16 debug_wputpeekdma_chipram (uaecptr addr, uae_u32 v, uae_u32 mask, int reg);
+uae_u16 debug_wputpeekdma_chipset (uaecptr addr, uae_u32 v, uae_u32 mask, int reg);
+void debug_lgetpeek (uaecptr addr, uae_u32 v);
+void debug_wgetpeek (uaecptr addr, uae_u32 v);
+void debug_bgetpeek (uaecptr addr, uae_u32 v);
+void debug_bputpeek (uaecptr addr, uae_u32 v);
+void debug_wputpeek (uaecptr addr, uae_u32 v);
+void debug_lputpeek (uaecptr addr, uae_u32 v);
+
+uae_u32 get_byte_debug (uaecptr addr);
+uae_u32 get_word_debug (uaecptr addr);
+uae_u32 get_long_debug (uaecptr addr);
+uae_u32 get_ilong_debug (uaecptr addr);
+uae_u32 get_iword_debug (uaecptr addr);
+
+
+enum debugtest_item { DEBUGTEST_BLITTER, DEBUGTEST_KEYBOARD, DEBUGTEST_FLOPPY, DEBUGTEST_MAX };
+void debugtest (enum debugtest_item, const TCHAR *, ...);
+
+struct dma_rec
+{
+    uae_u16 reg;
+    uae_u32 dat;
+    uae_u32 addr;
+    uae_u16 evt;
+    int type;
+	uae_s8 intlev;
+};
+
+#define DMA_EVENT_BLITIRQ 1
+#define DMA_EVENT_BLITNASTY 2
+#define DMA_EVENT_BLITSTARTFINISH 4
+#define DMA_EVENT_BPLFETCHUPDATE 8
+#define DMA_EVENT_COPPERWAKE 16
+#define DMA_EVENT_CPUIRQ 32
+#define DMA_EVENT_INTREQ 64
+#define DMA_EVENT_COPPERWANTED 128
+
+#define DMARECORD_REFRESH 1
+#define DMARECORD_CPU 2
+#define DMARECORD_COPPER 3
+#define DMARECORD_AUDIO 4
+#define DMARECORD_BLITTER 5
+#define DMARECORD_BLITTER_FILL 6
+#define DMARECORD_BLITTER_LINE 7
+#define DMARECORD_BITPLANE 8
+#define DMARECORD_SPRITE 9
+#define DMARECORD_DISK 10
+#define DMARECORD_MAX 11
+
+extern struct dma_rec *record_dma (uae_u16 reg, uae_u16 dat, uae_u32 addr, int hpos, int vpos, int type);
+extern void record_dma_reset (void);
+extern void record_dma_event (int evt, int hpos, int vpos);
+extern void debug_draw_cycles (uae_u8 *buf, int bpp, int line, int width, int height, uae_u32 *xredcolors, uae_u32 *xgreencolors, uae_u32 *xbluescolors);
+
+#else
+
+STATIC_INLINE void activate_debugger (void) { };
+#ifdef WINUAE_FOR_HATARI
+uae_u32 get_byte_debug (uaecptr addr);
+uae_u32 get_word_debug (uaecptr addr);
+uae_u32 get_long_debug (uaecptr addr);
+uae_u32 get_ilong_debug (uaecptr addr);
+uae_u32 get_iword_debug (uaecptr addr);
+extern void mmu_do_hit (void);
+#endif
+
+#endif
diff --git a/src/cpu/events.c b/src/cpu/events.c
new file mode 100644
index 0000000..ca80644
--- /dev/null
+++ b/src/cpu/events.c
@@ -0,0 +1,225 @@
+/*
+* UAE - The Un*x Amiga Emulator
+*
+* Event stuff
+*
+* Copyright 1995-2002 Bernd Schmidt
+* Copyright 1995 Alessandro Bissacco
+* Copyright 2000-2012 Toni Wilen
+*/
+
+#include "main.h"
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+
+#include "options_cpu.h"
+#include "events.h"
+#include "memory.h"
+#include "newcpu.h"
+//#include "uae/ppc.h"
+
+static const int pissoff_nojit_value = 256 * CYCLE_UNIT;
+
+#ifndef WINUAE_FOR_HATARI
+unsigned long int event_cycles, nextevent, currcycle;
+int is_syncline, is_syncline_end;
+long cycles_to_next_event;
+long max_cycles_to_next_event;
+long cycles_to_hsync_event;
+unsigned long start_cycles;
+bool event_wait;
+
+frame_time_t vsyncmintime, vsyncmaxtime, vsyncwaittime;
+int vsynctimebase;
+int event2_count;
+
+void events_schedule (void)
+{
+	int i;
+
+	unsigned long int mintime = ~0L;
+	for (i = 0; i < ev_max; i++) {
+		if (eventtab[i].active) {
+			unsigned long int eventtime = eventtab[i].evtime - currcycle;
+			if (eventtime < mintime)
+				mintime = eventtime;
+		}
+	}
+	nextevent = currcycle + mintime;
+}
+#endif
+
+void do_cycles_slow (unsigned long cycles_to_add)
+{
+#ifndef WINUAE_FOR_HATARI
+	if ((pissoff -= cycles_to_add) >= 0)
+		return;
+
+	cycles_to_add = -pissoff;
+	pissoff = 0;
+
+	while ((nextevent - currcycle) <= cycles_to_add) {
+		int i;
+
+		/* Keep only CPU emulation running while waiting for sync point. */
+		if (is_syncline) {
+			if (!vblank_found_chipset) {
+				if (is_syncline > 0) {
+					int rpt = read_processor_time ();
+					int v = rpt - vsyncmintime;
+					int v2 = rpt - is_syncline_end;
+					if (v > vsynctimebase || v < -vsynctimebase) {
+						v = 0;
+					}
+					if (v < 0 && v2 < 0 && event_wait) {
+
+#ifdef WITH_PPC
+						if (ppc_state) {
+							if (is_syncline == 1) {
+								uae_ppc_execute_check();
+							} else {
+								uae_ppc_execute_quick();
+							}
+						}
+#endif
+						if (currprefs.cachesize)
+							pissoff = pissoff_value;
+						else
+							pissoff = pissoff_nojit_value;
+						return;
+					}
+				} else if (is_syncline < 0) {
+					int rpt = read_processor_time ();
+					int v = rpt - is_syncline_end;
+					if (v < 0 && event_wait) {
+
+#ifdef WITH_PPC
+						if (ppc_state) {
+							uae_ppc_execute_check();
+						}
+#endif
+						if (currprefs.cachesize)
+							pissoff = pissoff_value;
+						else
+							pissoff = pissoff_nojit_value;
+						return;
+					}
+				}
+			}
+			is_syncline = 0;
+		}
+
+		cycles_to_add -= nextevent - currcycle;
+		currcycle = nextevent;
+
+		for (i = 0; i < ev_max; i++) {
+			if (eventtab[i].active && eventtab[i].evtime == currcycle) {
+				if (eventtab[i].handler == NULL) {
+					gui_message(_T("eventtab[%d].handler is null!\n"), i);
+					eventtab[i].active = 0;
+				} else {
+					(*eventtab[i].handler)();
+				}
+			}
+		}
+		events_schedule ();
+
+
+	}
+#endif
+	currcycle += cycles_to_add;
+}
+
+#ifndef WINUAE_FOR_HATARI
+void MISC_handler (void)
+{
+	static bool dorecheck;
+	bool recheck;
+	int i;
+	evt mintime;
+	evt ct = get_cycles ();
+	static int recursive;
+
+	if (recursive) {
+		dorecheck = true;
+		return;
+	}
+	recursive++;
+	eventtab[ev_misc].active = 0;
+	recheck = true;
+	while (recheck) {
+		recheck = false;
+		mintime = ~0L;
+		for (i = 0; i < ev2_max; i++) {
+			if (eventtab2[i].active) {
+				if (eventtab2[i].evtime == ct) {
+					eventtab2[i].active = false;
+					event2_count--;
+					eventtab2[i].handler (eventtab2[i].data);
+					if (dorecheck || eventtab2[i].active) {
+						recheck = true;
+						dorecheck = false;
+					}
+				} else {
+					evt eventtime = eventtab2[i].evtime - ct;
+					if (eventtime < mintime)
+						mintime = eventtime;
+				}
+			}
+		}
+	}
+	if (mintime != ~0UL) {
+		eventtab[ev_misc].active = true;
+		eventtab[ev_misc].oldcycles = ct;
+		eventtab[ev_misc].evtime = ct + mintime;
+		events_schedule ();
+	}
+	recursive--;
+}
+
+
+void event2_newevent_xx (int no, evt t, uae_u32 data, evfunc2 func)
+{
+	evt et;
+	static int next = ev2_misc;
+
+	et = t + get_cycles ();
+	if (no < 0) {
+		no = next;
+		for (;;) {
+			if (!eventtab2[no].active) {
+				event2_count++;
+				break;
+			}
+			if (eventtab2[no].evtime == et && eventtab2[no].handler == func && eventtab2[no].data == data)
+				break;
+			no++;
+			if (no == ev2_max)
+				no = ev2_misc;
+			if (no == next) {
+				write_log (_T("out of event2's!\n"));
+				return;
+			}
+		}
+		next = no;
+	}
+	eventtab2[no].active = true;
+	eventtab2[no].evtime = et;
+	eventtab2[no].handler = func;
+	eventtab2[no].data = data;
+	MISC_handler ();
+}
+
+int current_hpos (void)
+{
+	int hp = current_hpos_safe ();
+	if (hp < 0 || hp > 256) {
+		gui_message(_T("hpos = %d!?\n"), hp);
+		hp = 0;
+	}
+	return hp;
+}
+#endif
+
+
diff --git a/src/cpu/events.h b/src/cpu/events.h
new file mode 100644
index 0000000..b1979e2
--- /dev/null
+++ b/src/cpu/events.h
@@ -0,0 +1,165 @@
+#ifndef EVENTS_H
+#define EVENTS_H
+
+ /*
+  * UAE - The Un*x Amiga Emulator
+  *
+  * Events
+  * These are best for low-frequency events. Having too many of them,
+  * or using them for events that occur too frequently, can cause massive
+  * slowdown.
+  *
+  * Copyright 1995-1998 Bernd Schmidt
+  */
+
+#undef EVENT_DEBUG
+
+#include "rpt.h"
+
+extern frame_time_t vsyncmintime, vsyncmaxtime, vsyncwaittime;
+extern int vsynctimebase, syncbase;
+extern void reset_frame_rate_hack (void);
+extern unsigned long int vsync_cycles;
+extern unsigned long start_cycles;
+extern int event2_count;
+extern bool event_wait;
+
+extern void compute_vsynctime (void);
+extern void init_eventtab (void);
+extern void do_cycles_ce (unsigned long cycles);
+////extern void do_cycles_ce_internal (unsigned long cycles);
+#ifndef WINUAE_FOR_HATARI
+extern void do_cycles_ce020 (unsigned long cycles);
+///extern void do_cycles_ce020_internal (unsigned long cycles);
+#else
+/* [NP] avoid conflict with do_cycles_ce020( int ) in cpu_prefetch.h */
+extern void do_cycles_ce020_long (unsigned long cycles);
+///extern void do_cycles_ce020_internal_long (unsigned long cycles);
+#endif
+extern void events_schedule (void);
+extern void do_cycles_slow (unsigned long cycles_to_add);
+extern void do_cycles_fast (unsigned long cycles_to_add);
+
+extern int is_cycle_ce (void);
+
+extern unsigned long currcycle, nextevent;
+extern int is_syncline, is_syncline_end;
+typedef void (*evfunc)(void);
+typedef void (*evfunc2)(uae_u32);
+
+typedef unsigned long int evt;
+
+struct ev
+{
+    bool active;
+    evt evtime, oldcycles;
+    evfunc handler;
+};
+
+struct ev2
+{
+    bool active;
+    evt evtime;
+    uae_u32 data;
+    evfunc2 handler;
+};
+
+enum {
+    ev_cia, ev_audio, ev_misc, ev_hsync,
+    ev_max
+};
+
+enum {
+    ev2_blitter, ev2_disk, ev2_misc,
+    ev2_max = 12
+};
+
+extern int pissoff_value;
+extern signed long pissoff;
+
+#define countdown pissoff
+#define do_cycles do_cycles_slow
+
+extern struct ev eventtab[ev_max];
+extern struct ev2 eventtab2[ev2_max];
+
+extern volatile bool vblank_found_chipset;
+extern volatile bool vblank_found_rtg;
+extern int hpos_offset;
+extern int maxhpos;
+
+STATIC_INLINE void cycles_do_special (void)
+{
+#ifdef JIT
+	if (currprefs.cachesize) {
+		if (pissoff >= 0)
+			pissoff = -1;
+	} else
+#endif
+	{
+		pissoff = 0;
+	}
+}
+
+STATIC_INLINE void do_extra_cycles (unsigned long cycles_to_add)
+{
+	pissoff -= cycles_to_add;
+}
+
+STATIC_INLINE unsigned long int get_cycles (void)
+{
+	return currcycle;
+}
+
+STATIC_INLINE void set_cycles (unsigned long int x)
+{
+	currcycle = x;
+	eventtab[ev_hsync].oldcycles = x;
+#ifdef EVT_DEBUG
+	if (currcycle & (CYCLE_UNIT - 1))
+		write_log (_T("%x\n"), currcycle);
+#endif
+}
+
+STATIC_INLINE int current_hpos_safe (void)
+{
+    int hp = (get_cycles () - eventtab[ev_hsync].oldcycles) / CYCLE_UNIT;
+	return hp;
+}
+
+extern int current_hpos(void);
+
+STATIC_INLINE bool cycles_in_range (unsigned long endcycles)
+{
+	signed long c = get_cycles ();
+	return (signed long)endcycles - c > 0;
+}
+
+extern void MISC_handler (void);
+extern void event2_newevent_xx (int no, evt t, uae_u32 data, evfunc2 func);
+
+STATIC_INLINE void event2_newevent_x (int no, evt t, uae_u32 data, evfunc2 func)
+{
+	if (((int)t) <= 0) {
+		func (data);
+		return;
+	}
+	event2_newevent_xx (no, t * CYCLE_UNIT, data, func);
+}
+
+STATIC_INLINE void event2_newevent (int no, evt t, uae_u32 data)
+{
+	event2_newevent_x (no, t, data, eventtab2[no].handler);
+}
+STATIC_INLINE void event2_newevent2 (evt t, uae_u32 data, evfunc2 func)
+{
+	event2_newevent_x (-1, t, data, func);
+}
+
+STATIC_INLINE void event2_remevent (int no)
+{
+	eventtab2[no].active = 0;
+}
+
+
+#endif
diff --git a/src/cpu/fpp-ieee-be.h b/src/cpu/fpp-ieee-be.h
new file mode 100644
index 0000000..061c7ab
--- /dev/null
+++ b/src/cpu/fpp-ieee-be.h
@@ -0,0 +1,64 @@
+ /*
+  * UAE - The Un*x Amiga Emulator
+  *
+  * MC68881 emulation
+  * Support functions for IEEE compatible host CPUs.
+  * These functions use a GCC extension (type punning through unions) and
+  * should only be compiled with compilers that support this.
+  *
+  * Copyright 1999 Sam Jordan
+  */
+
+STATIC_INLINE double to_single (uae_u32 value)
+{
+    union {
+	float f;
+	uae_u32 u;
+    } val;
+
+    val.u = value;
+    return val.f;
+}
+
+STATIC_INLINE uae_u32 from_single (double src)
+{
+    union {
+	float f;
+	uae_u32 u;
+    } val;
+
+    val.f = src;
+    return val.u;
+}
+
+STATIC_INLINE double to_double(uae_u32 wrd1, uae_u32 wrd2)
+{
+    union {
+	double d;
+	uae_u32 u[2];
+    } val;
+
+    val.u[0] = wrd1;
+    val.u[1] = wrd2;
+    return val.d;
+}
+
+STATIC_INLINE void from_double(double src, uae_u32 * wrd1, uae_u32 * wrd2)
+{
+    union {
+	double d;
+	uae_u32 u[2];
+    } val;
+
+    val.d = src;
+    *wrd1 = val.u[0];
+    *wrd2 = val.u[1];
+}
+
+#define HAVE_from_double
+#define HAVE_to_double
+#define HAVE_from_single
+#define HAVE_to_single
+
+/* Get the rest of the conversion functions defined.  */
+#include "fpp-unknown.h"
diff --git a/src/cpu/fpp-unknown.h b/src/cpu/fpp-unknown.h
new file mode 100644
index 0000000..aa99164
--- /dev/null
+++ b/src/cpu/fpp-unknown.h
@@ -0,0 +1,139 @@
+ /*
+  * UAE - The Un*x Amiga Emulator
+  *
+  * MC68881 emulation
+  *
+  * Conversion routines for hosts with unknown floating point format.
+  *
+  * Copyright 1996 Herman ten Brugge
+  */
+
+#ifndef HAVE_to_single
+STATIC_INLINE double to_single (uae_u32 value)
+{
+    double frac;
+
+    if ((value & 0x7fffffff) == 0)
+	return (0.0);
+    frac = (double) ((value & 0x7fffff) | 0x800000) / 8388608.0;
+    if (value & 0x80000000)
+	frac = -frac;
+    return (ldexp (frac, ((value >> 23) & 0xff) - 127));
+}
+#endif
+
+#ifndef HAVE_from_single
+STATIC_INLINE uae_u32 from_single (double src)
+{
+    int expon;
+    uae_u32 tmp;
+    double frac;
+
+    if (src == 0.0)
+	return 0;
+    if (src < 0) {
+	tmp = 0x80000000;
+	src = -src;
+    } else {
+	tmp = 0;
+    }
+    frac = frexp (src, &expon);
+    frac += 0.5 / 16777216.0;
+    if (frac >= 1.0) {
+	frac /= 2.0;
+	expon++;
+    }
+    return (tmp | (((expon + 127 - 1) & 0xff) << 23) |
+	    (((int) (frac * 16777216.0)) & 0x7fffff));
+}
+#endif
+
+#ifndef HAVE_to_exten
+STATIC_INLINE double to_exten(uae_u32 wrd1, uae_u32 wrd2, uae_u32 wrd3)
+{
+    double frac;
+
+    if ((wrd1 & 0x7fff0000) == 0 && wrd2 == 0 && wrd3 == 0)
+	return 0.0;
+    frac = (double) wrd2 / 2147483648.0 +
+	(double) wrd3 / 9223372036854775808.0;
+    if (wrd1 & 0x80000000)
+	frac = -frac;
+    return ldexp (frac, ((wrd1 >> 16) & 0x7fff) - 16383);
+}
+#endif
+
+#ifndef HAVE_from_exten
+STATIC_INLINE void from_exten(double src, uae_u32 * wrd1, uae_u32 * wrd2, uae_u32 * wrd3)
+{
+    int expon;
+    double frac;
+
+    if (src == 0.0) {
+	*wrd1 = 0;
+	*wrd2 = 0;
+	*wrd3 = 0;
+	return;
+    }
+    if (src < 0) {
+	*wrd1 = 0x80000000;
+	src = -src;
+    } else {
+	*wrd1 = 0;
+    }
+    frac = frexp (src, &expon);
+    frac += 0.5 / 18446744073709551616.0;
+    if (frac >= 1.0) {
+	frac /= 2.0;
+	expon++;
+    }
+    *wrd1 |= (((expon + 16383 - 1) & 0x7fff) << 16);
+    *wrd2 = (uae_u32) (frac * 4294967296.0);
+    *wrd3 = (uae_u32) (frac * 18446744073709551616.0 - *wrd2 * 4294967296.0);
+}
+#endif
+
+#ifndef HAVE_to_double
+STATIC_INLINE double to_double(uae_u32 wrd1, uae_u32 wrd2)
+{
+    double frac;
+
+    if ((wrd1 & 0x7fffffff) == 0 && wrd2 == 0)
+	return 0.0;
+    frac = (double) ((wrd1 & 0xfffff) | 0x100000) / 1048576.0 +
+	(double) wrd2 / 4503599627370496.0;
+    if (wrd1 & 0x80000000)
+	frac = -frac;
+    return ldexp (frac, ((wrd1 >> 20) & 0x7ff) - 1023);
+}
+#endif
+
+#ifndef HAVE_from_double
+STATIC_INLINE void from_double(double src, uae_u32 * wrd1, uae_u32 * wrd2)
+{
+    int expon;
+    int tmp;
+    double frac;
+
+    if (src == 0.0) {
+	*wrd1 = 0;
+	*wrd2 = 0;
+	return;
+    }
+    if (src < 0) {
+	*wrd1 = 0x80000000;
+	src = -src;
+    } else {
+	*wrd1 = 0;
+    }
+    frac = frexp (src, &expon);
+    frac += 0.5 / 9007199254740992.0;
+    if (frac >= 1.0) {
+	frac /= 2.0;
+	expon++;
+    }
+    tmp = (uae_u32) (frac * 2097152.0);
+    *wrd1 |= (((expon + 1023 - 1) & 0x7ff) << 20) | (tmp & 0xfffff);
+    *wrd2 = (uae_u32) (frac * 9007199254740992.0 - tmp * 4294967296.0);
+}
+#endif
diff --git a/src/cpu/fpp.c b/src/cpu/fpp.c
new file mode 100644
index 0000000..074353e
--- /dev/null
+++ b/src/cpu/fpp.c
@@ -0,0 +1,3237 @@
+/*
+* UAE - The Un*x Amiga Emulator
+*
+* MC68881/68882/68040/68060 FPU emulation
+*
+* Copyright 1996 Herman ten Brugge
+* Modified 2005 Peter Keunecke
+* 68040+ exceptions and more by Toni Wilen
+*/
+
+#define __USE_ISOC9X  /* We might be able to pick up a NaN */
+
+#include 
+#include 
+#include 
+
+#include "main.h"
+#include "hatari-glue.h"
+
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+
+#ifdef _MSC_VER
+#pragma fenv_access(on)
+#endif
+
+#include "options_cpu.h"
+#include "memory.h"
+#include "custom.h"
+#include "events.h"
+#include "newcpu.h"
+#include "md-fpp.h"
+#include "savestate.h"
+#include "cpu_prefetch.h"
+#include "cpummu.h"
+#include "cpummu030.h"
+//#include "debug.h"
+
+#ifdef WITH_SOFTFLOAT
+#include "softfloatx80.h"
+#endif
+
+#ifdef X86_MSVC_ASSEMBLY
+#define X86_MSVC_ASSEMBLY_FPU
+#define NATIVE_FPUCW
+#endif
+
+#define DEBUG_FPP 0
+#define EXCEPTION_FPP 1
+
+STATIC_INLINE int isinrom (void)
+{
+	return (munge24 (m68k_getpc ()) & 0xFFF80000) == 0xF80000 && !currprefs.mmu_model;
+}
+
+#ifdef WITH_SOFTFLOAT
+static uae_u32 xhex_pi[]    ={0x2168c235, 0xc90fdaa2, 0x4000};
+uae_u32 xhex_exp_1[] ={0xa2bb4a9a, 0xadf85458, 0x4000};
+static uae_u32 xhex_l2_e[]  ={0x5c17f0bc, 0xb8aa3b29, 0x3fff};
+static uae_u32 xhex_ln_2[]  ={0xd1cf79ac, 0xb17217f7, 0x3ffe};
+uae_u32 xhex_ln_10[] ={0xaaa8ac17, 0x935d8ddd, 0x4000};
+uae_u32 xhex_l10_2[] ={0xfbcff798, 0x9a209a84, 0x3ffd};
+uae_u32 xhex_l10_e[] ={0x37287195, 0xde5bd8a9, 0x3ffd};
+uae_u32 xhex_1e16[]  ={0x04000000, 0x8e1bc9bf, 0x4034};
+uae_u32 xhex_1e32[]  ={0x2b70b59e, 0x9dc5ada8, 0x4069};
+uae_u32 xhex_1e64[]  ={0xffcfa6d5, 0xc2781f49, 0x40d3};
+uae_u32 xhex_1e128[] ={0x80e98ce0, 0x93ba47c9, 0x41a8};
+uae_u32 xhex_1e256[] ={0x9df9de8e, 0xaa7eebfb, 0x4351};
+uae_u32 xhex_1e512[] ={0xa60e91c7, 0xe319a0ae, 0x46a3};
+uae_u32 xhex_1e1024[]={0x81750c17, 0xc9767586, 0x4d48};
+uae_u32 xhex_1e2048[]={0xc53d5de5, 0x9e8b3b5d, 0x5a92};
+uae_u32 xhex_1e4096[]={0x8a20979b, 0xc4605202, 0x7525};
+static uae_u32 xhex_inf[]   ={0x00000000, 0x00000000, 0x7fff};
+static uae_u32 xhex_nan[]   ={0xffffffff, 0xffffffff, 0x7fff};
+static uae_u32 xhex_snan[]  ={0xffffffff, 0xbfffffff, 0x7fff};
+#endif
+
+#if USE_LONG_DOUBLE
+static long double *fp_pi     = (long double *)xhex_pi;
+static long double *fp_exp_1  = (long double *)xhex_exp_1;
+static long double *fp_l2_e   = (long double *)xhex_l2_e;
+static long double *fp_ln_2   = (long double *)xhex_ln_2;
+static long double *fp_ln_10  = (long double *)xhex_ln_10;
+static long double *fp_l10_2  = (long double *)xhex_l10_2;
+static long double *fp_l10_e  = (long double *)xhex_l10_e;
+static long double *fp_1e16   = (long double *)xhex_1e16;
+static long double *fp_1e32   = (long double *)xhex_1e32;
+static long double *fp_1e64   = (long double *)xhex_1e64;
+static long double *fp_1e128  = (long double *)xhex_1e128;
+static long double *fp_1e256  = (long double *)xhex_1e256;
+static long double *fp_1e512  = (long double *)xhex_1e512;
+static long double *fp_1e1024 = (long double *)xhex_1e1024;
+static long double *fp_1e2048 = (long double *)xhex_1e2048;
+static long double *fp_1e4096 = (long double *)xhex_1e4096;
+//static long double *fp_inf    = (long double *)xhex_inf;
+static long double *fp_nan    = (long double *)xhex_nan;
+#else
+static uae_u32 dhex_pi[]    ={0x54442D18, 0x400921FB};
+static uae_u32 dhex_exp_1[] ={0x8B145769, 0x4005BF0A};
+static uae_u32 dhex_l2_e[]  ={0x652B82FE, 0x3FF71547};
+static uae_u32 dhex_ln_2[]  ={0xFEFA39EF, 0x3FE62E42};
+static uae_u32 dhex_ln_10[] ={0xBBB55516, 0x40026BB1};
+static uae_u32 dhex_l10_2[] ={0x509F79FF, 0x3FD34413};
+static uae_u32 dhex_l10_e[] ={0x1526E50E, 0x3FDBCB7B};
+static uae_u32 dhex_1e16[]  ={0x37E08000, 0x4341C379};
+static uae_u32 dhex_1e32[]  ={0xB5056E17, 0x4693B8B5};
+static uae_u32 dhex_1e64[]  ={0xE93FF9F5, 0x4D384F03};
+static uae_u32 dhex_1e128[] ={0xF9301D32, 0x5A827748};
+static uae_u32 dhex_1e256[] ={0x7F73BF3C, 0x75154FDD};
+static uae_u32 dhex_inf[]   ={0x00000000, 0x7ff00000};
+static uae_u32 dhex_nan[]   ={0xffffffff, 0x7fffffff};
+static double *fp_pi     = (double *)dhex_pi;
+static double *fp_exp_1  = (double *)dhex_exp_1;
+static double *fp_l2_e   = (double *)dhex_l2_e;
+static double *fp_ln_2   = (double *)dhex_ln_2;
+static double *fp_ln_10  = (double *)dhex_ln_10;
+static double *fp_l10_2  = (double *)dhex_l10_2;
+static double *fp_l10_e  = (double *)dhex_l10_e;
+static double *fp_1e16   = (double *)dhex_1e16;
+static double *fp_1e32   = (double *)dhex_1e32;
+static double *fp_1e64   = (double *)dhex_1e64;
+static double *fp_1e128  = (double *)dhex_1e128;
+static double *fp_1e256  = (double *)dhex_1e256;
+static double *fp_1e512  = (double *)dhex_inf;
+static double *fp_1e1024 = (double *)dhex_inf;
+static double *fp_1e2048 = (double *)dhex_inf;
+static double *fp_1e4096 = (double *)dhex_inf;
+//static double *fp_inf    = (double *)dhex_inf;
+static double *fp_nan    = (double *)dhex_nan;
+#endif
+double fp_1e8 = 1.0e8;
+float  fp_1e0 = 1, fp_1e1 = 10, fp_1e2 = 100, fp_1e4 = 10000;
+static bool fpu_mmu_fixup;
+
+#define FFLAG_Z	    0x4000
+#define FFLAG_N	    0x0100
+#define FFLAG_NAN   0x0400
+
+
+#ifdef WITH_SOFTFLOAT
+static floatx80 fxsizes[6] = { 0 };
+static floatx80 fxzero;
+static floatx80 fx_1e0, fx_1e1, fx_1e2, fx_1e4, fx_1e8;
+struct float_status_t fxstatus;
+#endif
+static fptype fsizes[] = { -128.0, 127.0, -32768.0, 32767.0, -2147483648.0, 2147483647.0 };
+
+#define FP_INEXACT (1 << 9)
+#define FP_DIVBYZERO (1 << 10)
+#define FP_UNDERFLOW (1 << 11)
+#define FP_OVERFLOW (1 << 12)
+#define FP_OPERAND (1 << 13)
+#define FP_SNAN (1 << 14)
+#define FP_BSUN (1 << 15)
+
+STATIC_INLINE void MAKE_FPSR (fptype *fp)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat)
+		return;
+#endif
+	/*int status = fetestexcept (FE_ALL_EXCEPT);
+	if (status) {
+		if (status & FE_INEXACT)
+			regs.fp_result_status |= FP_INEXACT;
+		if (status & FE_DIVBYZERO)
+			regs.fp_result_status |= FP_DIVBYZERO;
+		if (status & FE_UNDERFLOW)
+			regs.fp_result_status |= FP_UNDERFLOW;
+		if (status & FE_OVERFLOW)
+			regs.fp_result_status |= FP_OVERFLOW;
+		if (status & FE_INVALID)
+			regs.fp_result_status |= FP_OPERAND;
+	}*/
+	regs.fp_result.fp = *fp;
+}
+
+#ifdef WITH_SOFTFLOAT
+STATIC_INLINE void MAKE_FPSR_SOFTFLOAT(floatx80 fx)
+{
+	if (fxstatus.float_exception_flags & float_flag_invalid)
+		regs.fp_result_status |= FP_OPERAND;
+	if (fxstatus.float_exception_flags & float_flag_divbyzero)
+		regs.fp_result_status |= FP_DIVBYZERO;
+	if (fxstatus.float_exception_flags & float_flag_overflow)
+		regs.fp_result_status |= FP_OVERFLOW;
+	if (fxstatus.float_exception_flags & float_flag_underflow)
+		regs.fp_result_status |= FP_UNDERFLOW;
+	if (fxstatus.float_exception_flags & float_flag_inexact)
+		regs.fp_result_status |= FP_INEXACT;
+	regs.fp_result.fpx = fx;
+}
+#endif
+
+STATIC_INLINE void CLEAR_STATUS (void)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat)
+		return;
+#endif
+	//feclearexcept (FE_ALL_EXCEPT);
+}
+
+#ifdef WITH_SOFTFLOAT
+static void softfloat_set(floatx80 *fx, uae_u32 *f)
+{
+	fx->exp = (uae_u16)f[2];
+	fx->fraction = ((uae_u64)f[1] << 32) | f[0];
+}
+static void softfloat_get(floatx80 *fx, uae_u32 *f)
+{
+	f[2] = fx->exp;
+	f[1] = fx->fraction >> 32;
+	f[0] = (uae_u32)fx->fraction;
+}
+#endif
+
+static void fpnan (fpdata *fpd)
+{
+	fpd->fp = *fp_nan;
+#ifdef WITH_SOFTFLOAT
+	softfloat_set(&fpd->fpx, xhex_nan);
+#endif
+}
+
+static void fpclear (fpdata *fpd)
+{
+	fpd->fp = 0;
+#ifdef WITH_SOFTFLOAT
+	fpd->fpx = int32_to_floatx80(0);
+#endif
+}
+static void fpset (fpdata *fpd, uae_s32 val)
+{
+	fpd->fp = (fptype)val;
+#ifdef WITH_SOFTFLOAT
+	fpd->fpx = int32_to_floatx80(val);
+#endif
+}
+
+void to_single(fpdata *fpd, uae_u32 value)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat) {
+		float32 f = value;
+		fpd->fpx = float32_to_floatx80(f, fxstatus);
+	} else
+#endif
+		fpd->fp = to_single_x(value);
+}
+static uae_u32 from_single(fpdata *fpd)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat) {
+		float32 f = floatx80_to_float32(fpd->fpx, fxstatus);
+		return f;
+	} else
+#endif
+		return from_single_x(fpd->fp);
+}
+void to_double(fpdata *fpd, uae_u32 wrd1, uae_u32 wrd2)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat) {
+		float64 f = ((float64)wrd1 << 32) | wrd2;
+		fpd->fpx = float64_to_floatx80(f, fxstatus);
+	} else
+#endif
+		fpd->fp = to_double_x(wrd1, wrd2);
+}
+static void from_double(fpdata *fpd, uae_u32 *wrd1, uae_u32 *wrd2)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat) {
+		float64 f = floatx80_to_float64(fpd->fpx, fxstatus);
+		*wrd1 = f >> 32;
+		*wrd2 = (uae_u32)f;
+		return;
+	} else
+#endif
+		return from_double_x(fpd->fp, wrd1, wrd2);
+}
+void to_exten(fpdata *fpd, uae_u32 wrd1, uae_u32 wrd2, uae_u32 wrd3)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat) {
+		fpd->fpx.exp = wrd1 >> 16;
+		fpd->fpx.fraction = ((uae_u64)wrd2 << 32) | wrd3;
+#if 0
+		if ((currprefs.fpu_model == 68881 || currprefs.fpu_model == 68882) || currprefs.fpu_no_unimplemented) {
+			// automatically fix denormals if 6888x or no implemented emulation
+			Bit64u Sig = extractFloatx80Frac(fpd->fpx);
+			Bit32s Exp = extractFloatx80Exp(fpd->fpx);
+			if (Exp == 0 && Sig != 0)
+				normalizeFloatx80Subnormal(Sig, &Exp, &Sig);
+		}
+#endif
+	} else
+#endif
+		to_exten_x(&fpd->fp, wrd1, wrd2, wrd3);
+}
+static void from_exten(fpdata *fpd, uae_u32 * wrd1, uae_u32 * wrd2, uae_u32 * wrd3)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat) {
+		*wrd1 = fpd->fpx.exp << 16;
+		*wrd2 = fpd->fpx.fraction >> 32;
+		*wrd3 = (uae_u32)fpd->fpx.fraction;
+	} else
+#endif
+		from_exten_x(fpd->fp, wrd1, wrd2, wrd3);
+}
+
+
+#if 0
+static void normalize(uae_u32 *pwrd1, uae_u32 *pwrd2, uae_u32 *pwrd3)
+{
+	uae_u32 wrd1 = *pwrd1;
+	uae_u32 wrd2 = *pwrd2;
+	uae_u32 wrd3 = *pwrd3;
+	int exp = (wrd1 >> 16) & 0x7fff;
+	// Normalize if unnormal.
+	if (exp != 0 && exp != 0x7fff && !(wrd2 & 0x80000000)) {
+		while (!(wrd2 & 0x80000000) && (wrd2 || wrd3)) {
+			wrd2 <<= 1;
+			if (wrd3 & 0x80000000)
+				wrd2 |= 1;
+			wrd3 <<= 1;
+			exp--;
+		}
+		if (exp < 0)
+			exp = 0;
+		if (!wrd2 && !wrd3)
+			exp = 0;
+		*pwrd1 = (wrd1 & 0x80000000) | (exp << 16);
+		*pwrd2 = wrd2;
+		*pwrd3 = wrd3;
+	}
+}
+#endif
+
+static bool fpu_get_constant_fp(fpdata *fp, int cr)
+{
+	fptype f;
+	switch (cr & 0x7f)
+	{
+		case 0x00:
+		f = *fp_pi;
+		break;
+		case 0x0b:
+		f = *fp_l10_2;
+		break;
+		case 0x0c:
+		f = *fp_exp_1;
+		break;
+		case 0x0d:
+		f = *fp_l2_e;
+		break;
+		case 0x0e:
+		f = *fp_l10_e;
+		break;
+		case 0x0f:
+		f = 0.0;
+		break;
+		case 0x30:
+		f = *fp_ln_2;
+		break;
+		case 0x31:
+		f = *fp_ln_10;
+		break;
+		case 0x32:
+		f = (fptype)fp_1e0;
+		break;
+		case 0x33:
+		f = (fptype)fp_1e1;
+		break;
+		case 0x34:
+		f = (fptype)fp_1e2;
+		break;
+		case 0x35:
+		f = (fptype)fp_1e4;
+		break;
+		case 0x36:
+		f = (fptype)fp_1e8;
+		break;
+		case 0x37:
+		f = *fp_1e16;
+		break;
+		case 0x38:
+		f = *fp_1e32;
+		break;
+		case 0x39:
+		f = *fp_1e64;
+		break;
+		case 0x3a:
+		f = *fp_1e128;
+		break;
+		case 0x3b:
+		f = *fp_1e256;
+		break;
+		case 0x3c:
+		f = *fp_1e512;
+		break;
+		case 0x3d:
+		f = *fp_1e1024;
+		break;
+		case 0x3e:
+		f = *fp_1e2048;
+		break;
+		case 0x3f:
+		f = *fp_1e4096;
+		break;
+		default:
+		return false;
+	}
+	fp->fp = f;
+	return true;
+}
+
+#ifdef WITH_SOFTFLOAT
+static bool fpu_get_constant_softfloat(fpdata *fp, int cr)
+{
+	uae_u32 *f = NULL;
+	floatx80 fx;
+
+	switch (cr & 0x7f)
+	{
+		case 0x00:
+		f = xhex_pi;
+		break;
+		case 0x0b:
+		f = xhex_l10_2;
+		break;
+		case 0x0c:
+		f = xhex_exp_1;
+		break;
+		case 0x0d:
+		f = xhex_l2_e;
+		break;
+		case 0x0e:
+		f = xhex_l10_e;
+		break;
+		case 0x0f:
+		fx = fxzero;
+		break;
+		case 0x30:
+		f = xhex_ln_2;
+		break;
+		case 0x31:
+		f = xhex_ln_10;
+		break;
+		case 0x32:
+		fx = fx_1e0;
+		break;
+		case 0x33:
+		fx = fx_1e1;
+		break;
+		case 0x34:
+		fx = fx_1e2;
+		break;
+		case 0x35:
+		fx = fx_1e4;
+		break;
+		case 0x36:
+		fx = fx_1e8;
+		break;
+		case 0x37:
+		f = xhex_1e16;
+		break;
+		case 0x38:
+		f = xhex_1e32;
+		break;
+		case 0x39:
+		f = xhex_1e64;
+		break;
+		case 0x3a:
+		f = xhex_1e128;
+		break;
+		case 0x3b:
+		f = xhex_1e256;
+		break;
+		case 0x3c:
+		f = xhex_1e512;
+		break;
+		case 0x3d:
+		f = xhex_1e1024;
+		break;
+		case 0x3e:
+		f = xhex_1e2048;
+		break;
+		case 0x3f:
+		f = xhex_1e4096;
+		break;
+		default:
+		return false;
+	}
+	if (f)
+		softfloat_set(&fp->fpx, f);
+	else
+		fp->fpx = fx;
+	return true;
+}
+#endif
+
+bool fpu_get_constant(fpdata *fp, int cr)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat)
+		return fpu_get_constant_softfloat(fp, cr);
+#endif
+	return fpu_get_constant_fp(fp, cr);
+}
+
+static void native_set_fpucw (uae_u32 m68k_cw)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat) {
+		switch((m68k_cw >> 6) & 3)
+		{
+			case 0: // X
+			default: // undefined
+				fxstatus.float_rounding_precision = 80;
+			break;
+			case 1: // S
+				fxstatus.float_rounding_precision = 32;
+			break;
+			case 2: // D
+				fxstatus.float_rounding_precision = 64;
+			break;
+		}
+		switch((m68k_cw >> 4) & 3)
+		{
+			case 0: // to neareset
+				fxstatus.float_rounding_precision = float_round_nearest_even;
+			break;
+			case 1: // to zero
+				fxstatus.float_rounding_mode = float_round_to_zero;
+			break;
+			case 2: // to minus
+				fxstatus.float_rounding_mode = float_round_down;
+			break;
+			case 3: // to plus
+				fxstatus.float_rounding_mode = float_round_up;
+			break;
+		}
+	} else
+#endif
+	{
+#ifdef NATIVE_FPUCW
+#ifdef _WIN32
+		static int ex = 0;
+		// RN, RZ, RM, RP
+		static const unsigned int fp87_round[4] = { _RC_NEAR, _RC_CHOP, _RC_DOWN, _RC_UP };
+		// Extend X, Single S, Double D, Undefined
+		static const unsigned int fp87_prec[4] = { _PC_64 , _PC_24 , _PC_53, 0 };
+#ifdef WIN64
+		_controlfp (ex | fp87_round[(m68k_cw >> 4) & 3], _MCW_RC);
+#else
+		_control87 (ex | fp87_round[(m68k_cw >> 4) & 3] | fp87_prec[(m68k_cw >> 6) & 3], _MCW_RC | _MCW_PC);
+#endif
+#else
+	static const uae_u16 x87_cw_tab[] = {
+		0x137f, 0x1f7f, 0x177f, 0x1b7f,	/* Extended */
+		0x107f, 0x1c7f, 0x147f, 0x187f,	/* Single */
+		0x127f, 0x1e7f, 0x167f, 0x1a7f,	/* Double */
+		0x137f, 0x1f7f, 0x177f, 0x1b7f	/* undefined */
+	};
+#if USE_X86_FPUCW
+		uae_u16 x87_cw = x87_cw_tab[(m68k_cw >> 4) & 0xf];
+
+#if defined(X86_MSVC_ASSEMBLY)
+		__asm {
+			fldcw word ptr x87_cw
+		}
+#elif defined(X86_ASSEMBLY)
+		__asm__ ("fldcw %0" : : "m" (*&x87_cw));
+#endif
+#endif
+#endif
+#endif
+	}
+}
+
+#if defined(uae_s64) /* Close enough for government work? */
+typedef uae_s64 tointtype;
+#else
+typedef uae_s32 tointtype;
+#endif
+
+/*
+static void fpu_format_error (void)
+{
+	uaecptr newpc;
+	regs.t0 = regs.t1 = 0;
+	MakeSR ();
+	if (!regs.s) {
+		regs.usp = m68k_areg (regs, 7);
+		m68k_areg (regs, 7) = regs.isp;
+	}
+	regs.s = 1;
+	m68k_areg (regs, 7) -= 2;
+	x_put_long (m68k_areg (regs, 7), 0x0000 + 14 * 4);
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), m68k_getpc ());
+	m68k_areg (regs, 7) -= 2;
+	x_put_long (m68k_areg (regs, 7), regs.sr);
+	newpc = x_get_long (regs.vbr + 14 * 4);
+	m68k_setpc (newpc);
+#ifdef JIT
+	set_special (SPCFLAG_END_COMPILE);
+#endif
+	regs.fp_exception = true;
+}
+*/
+
+#define FPU_EXP_UNIMP_INS 0
+#define FPU_EXP_DISABLED 1
+#define FPU_EXP_UNIMP_DATATYPE_PRE 2
+#define FPU_EXP_UNIMP_DATATYPE_POST 3
+#define FPU_EXP_UNIMP_DATATYPE_PACKED_PRE 4
+#define FPU_EXP_UNIMP_DATATYPE_PACKED_POST 5
+#define FPU_EXP_UNIMP_EA 6
+
+
+static void fpu_op_unimp (uae_u16 opcode, uae_u16 extra, uae_u32 ea, uaecptr oldpc, int type, fpdata *src, int reg, int size)
+{
+	/* 68040 unimplemented/68060 FPU disabled exception.
+	* Line F exception with different stack frame.. */
+	int vector = 11;
+	uaecptr newpc = m68k_getpc (); // next instruction
+	static int warned = 20;
+
+	regs.t0 = regs.t1 = 0;
+	MakeSR ();
+	if (!regs.s) {
+		regs.usp = m68k_areg (regs, 7);
+		if (currprefs.cpu_model == 68060) {
+			m68k_areg (regs, 7) = regs.isp;
+		} else if (currprefs.cpu_model >= 68020) {
+			m68k_areg (regs, 7) = regs.m ? regs.msp : regs.isp;
+		} else {
+			m68k_areg (regs, 7) = regs.isp;
+		}
+		regs.s = 1;
+		if (currprefs.mmu_model)
+			mmu_set_super (regs.s != 0);
+	}
+	regs.fpu_exp_state = 1;
+	if (currprefs.cpu_model == 68060) {
+		regs.fpiar = oldpc;
+		regs.exp_extra = extra;
+		regs.exp_opcode = opcode;
+		regs.exp_size = size;
+		if (src)
+			regs.exp_src1 = *src;
+		regs.exp_type = type;
+		if (type == FPU_EXP_DISABLED) {
+			// current PC
+			newpc = oldpc;
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), oldpc);
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), ea);
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), 0x4000 + vector * 4);
+		} else if (type == FPU_EXP_UNIMP_INS) {
+			// PC = next instruction
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), ea);
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), 0x2000 + vector * 4);
+		} else if (type == FPU_EXP_UNIMP_DATATYPE_PACKED_PRE || type == FPU_EXP_UNIMP_DATATYPE_PACKED_POST || type == FPU_EXP_UNIMP_DATATYPE_PRE || type == FPU_EXP_UNIMP_DATATYPE_POST) {
+			regs.fpu_exp_state = 2; // EXC frame
+			// PC = next instruction
+			vector = 55;
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), ea);
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), 0x2000 + vector * 4);
+		} else { // FPU_EXP_UNIMP_EA
+			// current PC
+			newpc = oldpc;
+			vector = 60;
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), 0x0000 + vector * 4);
+		}
+	} else if (currprefs.cpu_model == 68040) {
+		regs.fpiar = oldpc;
+		regs.exp_extra = extra;
+		regs.exp_opcode = opcode;
+		regs.exp_size = size;
+		if (src)
+			regs.exp_src1 = *src;
+		regs.exp_type = type;
+		if (reg >= 0)
+			regs.exp_src2 = regs.fp[reg];
+		else
+			fpclear (®s.exp_src2);
+		if (type == FPU_EXP_UNIMP_INS || type == FPU_EXP_DISABLED) {
+			// PC = next instruction
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), ea);
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), 0x2000 + vector * 4);
+		} else if (type == FPU_EXP_UNIMP_DATATYPE_PACKED_PRE || type == FPU_EXP_UNIMP_DATATYPE_PACKED_POST || type == FPU_EXP_UNIMP_DATATYPE_PRE || type == FPU_EXP_UNIMP_DATATYPE_POST) {
+			// PC = next instruction
+			vector = 55;
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), ea);
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), 0x2000 + vector * 4);
+			regs.fpu_exp_state = 2; // BUSY frame
+		}
+	}
+	oldpc = newpc;
+	m68k_areg (regs, 7) -= 4;
+	x_put_long (m68k_areg (regs, 7), newpc);
+	m68k_areg (regs, 7) -= 2;
+	x_put_word (m68k_areg (regs, 7), regs.sr);
+	newpc = x_get_long (regs.vbr + vector * 4);
+	if (warned > 0) {
+		write_log (_T("FPU EXCEPTION %d OP=%04X-%04X EA=%08X PC=%08X -> %08X\n"), type, opcode, extra, ea, oldpc, newpc);
+#if EXCEPTION_FPP == 0
+		warned--;
+#endif
+	}
+	regs.fp_exception = true;
+	m68k_setpc (newpc);
+#ifdef JIT
+	set_special (SPCFLAG_END_COMPILE);
+#endif
+}
+
+static void fpu_op_illg2 (uae_u16 opcode, uae_u16 extra, uae_u32 ea, uaecptr oldpc)
+{
+	if ((currprefs.cpu_model == 68060 && (currprefs.fpu_model == 0 || (regs.pcr & 2)))
+		|| (currprefs.cpu_model == 68040 && currprefs.fpu_model == 0)) {
+			fpu_op_unimp (opcode, extra, ea, oldpc, FPU_EXP_DISABLED, NULL, -1, -1);
+			return;
+	}
+	regs.fp_exception = true;
+	m68k_setpc (oldpc);
+	op_illg (opcode);
+}
+
+static void fpu_op_illg (uae_u16 opcode, uae_u16 extra, uaecptr oldpc)
+{
+	fpu_op_illg2 (opcode, extra, 0, oldpc);
+}
+
+
+static void fpu_noinst (uae_u16 opcode, uaecptr pc)
+{
+#if EXCEPTION_FPP
+	write_log (_T("Unknown FPU instruction %04X %08X\n"), opcode, pc);
+#endif
+	regs.fp_exception = true;
+	m68k_setpc (pc);
+	op_illg (opcode);
+}
+
+static bool fault_if_no_fpu (uae_u16 opcode, uae_u16 extra, uaecptr ea, uaecptr oldpc)
+{
+	if ((regs.pcr & 2) || currprefs.fpu_model <= 0) {
+#if EXCEPTION_FPP
+		write_log (_T("no FPU: %04X-%04X PC=%08X\n"), opcode, extra, oldpc);
+#endif
+		fpu_op_illg2 (opcode, extra, ea, oldpc);
+		return true;
+	}
+	return false;
+}
+
+static bool fault_if_unimplemented_680x0 (uae_u16 opcode, uae_u16 extra, uaecptr ea, uaecptr oldpc, fpdata *src, int reg)
+{
+	if (fault_if_no_fpu (opcode, extra, ea, oldpc))
+		return true;
+	if (currprefs.cpu_model >= 68040 && currprefs.fpu_model && currprefs.fpu_no_unimplemented) {
+		if ((extra & (0x8000 | 0x2000)) != 0)
+			return false;
+		if ((extra & 0xfc00) == 0x5c00) {
+			// FMOVECR
+			fpu_op_unimp (opcode, extra, ea, oldpc, FPU_EXP_UNIMP_INS, src, reg, -1);
+			return true;
+		}
+		uae_u16 v = extra & 0x7f;
+		switch (v)
+		{
+			case 0x01: /* FINT */
+			case 0x03: /* FINTRZ */
+			// Unimplemented only in 68040.
+			if (currprefs.cpu_model == 68040) {
+				fpu_op_unimp (opcode, extra, ea, oldpc, FPU_EXP_UNIMP_INS, src, reg, -1);
+				return true;
+			}
+			return false;
+			case 0x02: /* FSINH */
+			case 0x06: /* FLOGNP1 */
+			case 0x08: /* FETOXM1 */
+			case 0x09: /* FTANH */
+			case 0x0a: /* FATAN */
+			case 0x0c: /* FASIN */
+			case 0x0d: /* FATANH */
+			case 0x0e: /* FSIN */
+			case 0x0f: /* FTAN */
+			case 0x10: /* FETOX */
+			case 0x11: /* FTWOTOX */
+			case 0x12: /* FTENTOX */
+			case 0x14: /* FLOGN */
+			case 0x15: /* FLOG10 */
+			case 0x16: /* FLOG2 */
+			case 0x19: /* FCOSH */
+			case 0x1c: /* FACOS */
+			case 0x1d: /* FCOS */
+			case 0x1e: /* FGETEXP */
+			case 0x1f: /* FGETMAN */
+			case 0x30: /* FSINCOS */
+			case 0x31: /* FSINCOS */
+			case 0x32: /* FSINCOS */
+			case 0x33: /* FSINCOS */
+			case 0x34: /* FSINCOS */
+			case 0x35: /* FSINCOS */
+			case 0x36: /* FSINCOS */
+			case 0x37: /* FSINCOS */
+			case 0x21: /* FMOD */
+			case 0x25: /* FREM */
+			case 0x26: /* FSCALE */
+			fpu_op_unimp (opcode, extra, ea, oldpc, FPU_EXP_UNIMP_INS, src, reg, -1);
+			return true;
+		}
+	}
+	return false;
+}
+
+static bool fault_if_unimplemented_6888x (uae_u16 opcode, uae_u16 extra, uaecptr oldpc)
+{
+	if ((currprefs.fpu_model == 68881 || currprefs.fpu_model == 68882) && currprefs.fpu_no_unimplemented) {
+		uae_u16 v = extra & 0x7f;
+		/* 68040/68060 only variants. 6888x = F-line exception. */
+		switch (v)
+		{
+			case 0x62: /* FSADD */
+			case 0x66: /* FDADD */
+			case 0x68: /* FSSUB */
+			case 0x6c: /* FDSUB */
+			case 0x5a: /* FSNEG */
+			case 0x5e: /* FDNEG */
+			case 0x58: /* FSABS */
+			case 0x5c: /* FDABS */
+			case 0x63: /* FSMUL */
+			case 0x67: /* FDMUL */
+			case 0x41: /* FSSQRT */
+			case 0x45: /* FDSQRT */
+			fpu_noinst (opcode, oldpc);
+			return true;
+		}
+	}
+	return false;
+}
+
+static bool fault_if_60 (uae_u16 opcode, uae_u16 extra, uaecptr ea, uaecptr oldpc, int type)
+{
+	if (currprefs.cpu_model == 68060 && currprefs.fpu_model && currprefs.fpu_no_unimplemented) {
+		fpu_op_unimp (opcode, extra, ea, oldpc, type, NULL, -1, -1);
+		return true;
+	}
+	return false;
+}
+
+static bool fault_if_4060 (uae_u16 opcode, uae_u16 extra, uaecptr ea, uaecptr oldpc, int type, fpdata *src, uae_u32 *pack)
+{
+	if (currprefs.cpu_model >= 68040 && currprefs.fpu_model && currprefs.fpu_no_unimplemented) {
+		if (pack) {
+			regs.exp_pack[0] = pack[0];
+			regs.exp_pack[1] = pack[1];
+			regs.exp_pack[2] = pack[2];
+		}
+		fpu_op_unimp (opcode, extra, ea, oldpc, type, src, -1, -1);
+		return true;
+	}
+	return false;
+}
+
+static bool fault_if_no_fpu_u (uae_u16 opcode, uae_u16 extra, uaecptr ea, uaecptr oldpc)
+{
+	if (fault_if_no_fpu (opcode, extra, ea, oldpc))
+		return true;
+	if (currprefs.cpu_model == 68060 && currprefs.fpu_model && currprefs.fpu_no_unimplemented) {
+		// 68060 FTRAP, FDBcc or FScc are not implemented.
+		fpu_op_unimp (opcode, extra, ea, oldpc, FPU_EXP_UNIMP_INS, NULL, -1, -1);
+		return true;
+	}
+	return false;
+}
+
+static bool fault_if_no_6888x (uae_u16 opcode, uae_u16 extra, uaecptr oldpc)
+{
+	if (currprefs.cpu_model < 68040 && currprefs.fpu_model <= 0) {
+#if EXCEPTION_FPP
+		write_log (_T("6888x no FPU: %04X-%04X PC=%08X\n"), opcode, extra, oldpc);
+#endif
+		m68k_setpc (oldpc);
+		regs.fp_exception = true;
+		op_illg (opcode);
+		return true;
+	}
+	return false;
+}
+
+static int get_fpu_version (void)
+{
+	int v = 0;
+
+	switch (currprefs.fpu_model)
+	{
+	case 68881:
+	case 68882:
+		v = 0x1f;
+		break;
+	case 68040:
+		if (currprefs.fpu_revision == 0x40)
+			v = 0x40;
+		else
+			v = 0x41;
+		break;
+	}
+	return v;
+}
+
+static void fpu_null (void)
+{
+	int i;
+	regs.fpu_state = 0;
+	regs.fpu_exp_state = 0;
+	regs.fpcr = 0;
+	regs.fpsr = 0;
+	regs.fpiar = 0;
+	fpclear (®s.fp_result);
+	for (i = 0; i < 8; i++)
+		fpnan (®s.fp[i]);
+}
+
+#define fp_round_to_minus_infinity(x) floor(x)
+#define fp_round_to_plus_infinity(x) ceil(x)
+#define fp_round_to_zero(x)	((x) >= 0.0 ? floor(x) : ceil(x))
+#define fp_round_to_nearest(x) ((x) >= 0.0 ? (int)((x) + 0.5) : (int)((x) - 0.5))
+
+static tointtype toint(fpdata *src, int size)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat) {
+		if (floatx80_compare(src->fpx, fxsizes[size * 2 + 0], fxstatus) == float_relation_greater)
+			return floatx80_to_int32(fxsizes[size * 2 + 0], fxstatus);	
+		if (floatx80_compare(src->fpx, fxsizes[size * 2 + 1], fxstatus) == float_relation_less)
+			return floatx80_to_int32(fxsizes[size * 2 + 1], fxstatus);
+		return floatx80_to_int32(src->fpx, fxstatus);
+	} else
+#endif
+	{
+		fptype fp = src->fp;
+		if (fp < fsizes[size * 2 + 0])
+			fp = fsizes[size * 2 + 0];
+		if (fp > fsizes[size * 2 + 1])
+			fp = fsizes[size * 2 + 1];
+	#if defined(X86_MSVC_ASSEMBLY_FPU)
+		{
+			fptype tmp_fp;
+			__asm {
+				fld  LDPTR fp
+				frndint
+				fstp LDPTR tmp_fp
+			}
+			return (tointtype)tmp_fp;
+		}
+	#else /* no X86_MSVC */
+		{
+			int result = (int)fp;
+			switch (regs.fpcr & 0x30)
+			{
+				case FPCR_ROUND_ZERO:
+					result = (int)fp_round_to_zero (fp);
+					break;
+				case FPCR_ROUND_MINF:
+					result = (int)fp_round_to_minus_infinity (fp);
+					break;
+				case FPCR_ROUND_NEAR:
+					result = fp_round_to_nearest (fp);
+					break;
+				case FPCR_ROUND_PINF:
+					result = (int)fp_round_to_plus_infinity (fp);
+					break;
+			}
+			return result;
+		}
+	#endif
+	}
+}
+
+static bool fp_is_snan(fpdata *fpd)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat)
+		return floatx80_is_signaling_nan(fpd->fpx) != 0;
+#endif
+	return false;
+}
+static bool fp_is_nan (fpdata *fpd)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat)
+		return floatx80_is_nan(fpd->fpx) != 0;
+#endif
+#ifdef HAVE_ISNAN
+	return isnan(fpd->fp) != 0;
+#else
+	return false;
+#endif
+}
+static bool fp_is_infinity (fpdata *fpd)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat) {
+		float_class_t fc = floatx80_class(fpd->fpx);
+		return fc == float_negative_inf || fc == float_positive_inf;
+	}
+#endif
+#ifdef _MSC_VER
+	return !_finite (fpd->fp);
+#elif defined(HAVE_ISINF)
+	return isinf (fpd->fp);
+#else
+	return false;
+#endif
+}
+static bool fp_is_zero(fpdata *fpd)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat)
+		return floatx80_compare_quiet(fpd->fpx, fxzero, fxstatus) == float_relation_equal;
+#endif
+	return fpd->fp == 0.0;
+}
+static bool fp_is_neg(fpdata *fpd)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat)
+		return extractFloatx80Sign(fpd->fpx) != 0;
+#endif
+	return fpd->fp < 0.0;
+}
+
+uae_u32 fpp_get_fpsr (void)
+{
+	uae_u32 answer = regs.fpsr & 0x00ff00f8;
+
+	// exception status byte
+	answer |= regs.fp_result_status;
+	if (fp_is_snan(®s.fp_result))
+		answer |= 1 << 14;
+
+	// accrued exception byte
+	if (answer & ((1 << 14)  | (1 << 13)))
+		answer |= 0x80; // IOP = SNAN | OPERR
+	if (answer & (1 << 12))
+		answer |= 0x40; // OVFL = OVFL
+	if (answer & ((1 << 11) | (1 << 9)))
+		answer |= 0x20; // UNFL = UNFL | INEX2
+	if (answer & (1 << 10))
+		answer |= 0x10; // DZ = DZ
+	if (answer & ((1 << 12) | (1 << 9) | (1 << 8)))
+		answer |= 0x08; // INEX = INEX1 | INEX2 | OVFL 
+
+	regs.fpsr = answer;
+
+	// condition code byte
+	if (fp_is_nan (®s.fp_result)) {
+		answer |= 1 << 24;
+	} else {
+		if (fp_is_zero(®s.fp_result))
+			answer |= 1 << 26;
+		if (fp_is_infinity (®s.fp_result))
+			answer |= 1 << 25;
+	}
+	if (fp_is_neg(®s.fp_result))
+		answer |= 1 << 27;
+	return answer;
+}
+
+static void update_fpsr (uae_u32 v)
+{
+	regs.fp_result_status = v;
+	fpp_get_fpsr ();
+}
+
+STATIC_INLINE void set_fpsr (uae_u32 x)
+{
+	regs.fpsr = x;
+	regs.fp_result_status = 0;
+
+	if (x & 0x01000000)
+		fpnan (®s.fp_result);
+	else if (x & 0x04000000)
+		fpset (®s.fp_result, 0);
+	else if (x & 0x08000000)
+		fpset (®s.fp_result, -1);
+	else
+		fpset (®s.fp_result, 1);
+}
+
+static uae_u32 get_ftag (uae_u32 w1, uae_u32 w2, uae_u32 w3, int size)
+{
+	int exp = (w1 >> 16) & 0x7fff;
+	
+	if (exp == 0) {
+		if (!w2 && !w3)
+			return 1; // ZERO
+		if (size == 0 || size == 1)
+			return 5; // Single/double DENORMAL
+		return 4; // Extended DENORMAL or UNNORMAL
+	} else if (exp == 0x7fff)  {
+		int s = w2 >> 30;
+		int z = (w2 & 0x3fffffff) == 0 && w3 == 0;
+		if ((s == 0 && !z) || (s == 2 && !z))
+			return 2; // INF
+		return 3; // NAN
+	} else {
+		if (!(w2 & 0x80000000))
+			return 4; // Extended UNNORMAL
+		return 0; // NORMAL
+	}
+}
+
+/* single   : S  8*E 23*F */
+/* double   : S 11*E 52*F */
+/* extended : S 15*E 64*F */
+/* E = 0 & F = 0 -> 0 */
+/* E = MAX & F = 0 -> Infin */
+/* E = MAX & F # 0 -> NotANumber */
+/* E = biased by 127 (single) ,1023 (double) ,16383 (extended) */
+
+static void to_pack (fpdata *fpd, uae_u32 *wrd)
+{
+	fptype d;
+	char *cp;
+	char str[100];
+
+	cp = str;
+	if (wrd[0] & 0x80000000)
+		*cp++ = '-';
+	*cp++ = (wrd[0] & 0xf) + '0';
+	*cp++ = '.';
+	*cp++ = ((wrd[1] >> 28) & 0xf) + '0';
+	*cp++ = ((wrd[1] >> 24) & 0xf) + '0';
+	*cp++ = ((wrd[1] >> 20) & 0xf) + '0';
+	*cp++ = ((wrd[1] >> 16) & 0xf) + '0';
+	*cp++ = ((wrd[1] >> 12) & 0xf) + '0';
+	*cp++ = ((wrd[1] >> 8) & 0xf) + '0';
+	*cp++ = ((wrd[1] >> 4) & 0xf) + '0';
+	*cp++ = ((wrd[1] >> 0) & 0xf) + '0';
+	*cp++ = ((wrd[2] >> 28) & 0xf) + '0';
+	*cp++ = ((wrd[2] >> 24) & 0xf) + '0';
+	*cp++ = ((wrd[2] >> 20) & 0xf) + '0';
+	*cp++ = ((wrd[2] >> 16) & 0xf) + '0';
+	*cp++ = ((wrd[2] >> 12) & 0xf) + '0';
+	*cp++ = ((wrd[2] >> 8) & 0xf) + '0';
+	*cp++ = ((wrd[2] >> 4) & 0xf) + '0';
+	*cp++ = ((wrd[2] >> 0) & 0xf) + '0';
+	*cp++ = 'E';
+	if (wrd[0] & 0x40000000)
+		*cp++ = '-';
+	*cp++ = ((wrd[0] >> 24) & 0xf) + '0';
+	*cp++ = ((wrd[0] >> 20) & 0xf) + '0';
+	*cp++ = ((wrd[0] >> 16) & 0xf) + '0';
+	*cp = 0;
+#if USE_LONG_DOUBLE
+	sscanf (str, "%Le", &d);
+#else
+	sscanf (str, "%le", &d);
+#endif
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat) {
+		uae_u32 wrd[3];
+		from_exten_x(d, &wrd[0], &wrd[1], &wrd[2]);
+		softfloat_set(&fpd->fpx, wrd);
+	} else
+#endif
+		fpd->fp = d;
+}
+
+static void from_pack (fpdata *src, uae_u32 *wrd, int kfactor)
+{
+	int i, j, t;
+	int exp;
+	int ndigits;
+	char *cp, *strp;
+	char str[100];
+	fptype fp;
+
+	wrd[0] = wrd[1] = wrd[2] = 0;
+
+	if (fp_is_nan (src) || fp_is_infinity (src)) {
+		wrd[0] |= (1 << 30) | (1 << 29) | (1 << 30); // YY=1
+		wrd[0] |= 0xfff << 16; // Exponent=FFF
+		// TODO: mantissa should be set if NAN
+		return;
+	}
+
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat) {
+		uae_u32 out[3];
+		softfloat_get(&src->fpx, out);
+		to_exten_x(&fp, out[0], out[1], out[2]);
+	} else
+#endif
+		fp = src->fp;
+
+#if USE_LONG_DOUBLE
+	sprintf (str, "%#.17Le", fp);
+#else
+	sprintf (str, "%#.17e", fp);
+#endif
+	
+	// get exponent
+	cp = str;
+	while (*cp++ != 'e');
+	if (*cp == '+')
+		cp++;
+	exp = atoi (cp);
+
+	// remove trailing zeros
+	cp = str;
+	while (*cp != 'e')
+		cp++;
+	cp[0] = 0;
+	cp--;
+	while (cp > str && *cp == '0') {
+		*cp = 0;
+		cp--;
+	}
+
+	cp = str;
+	// get sign
+	if (*cp == '-') {
+		cp++;
+		wrd[0] = 0x80000000;
+	} else if (*cp == '+') {
+		cp++;
+	}
+	strp = cp;
+
+	if (kfactor <= 0) {
+		ndigits = abs (exp) + (-kfactor) + 1;
+	} else {
+		if (kfactor > 17) {
+			kfactor = 17;
+			//update_fpsr (FE_INVALID);
+		}
+		ndigits = kfactor;
+	}
+
+	if (ndigits < 0)
+		ndigits = 0;
+	if (ndigits > 16)
+		ndigits = 16;
+
+	// remove decimal point
+	strp[1] = strp[0];
+	strp++;
+	// add trailing zeros
+	i = strlen (strp);
+	cp = strp + i;
+	while (i < ndigits) {
+		*cp++ = '0';
+		i++;
+	}
+	i = ndigits + 1;
+	while (i < 17) {
+		strp[i] = 0;
+		i++;
+	}
+	*cp = 0;
+	i = ndigits - 1;
+	// need to round?
+	if (i >= 0 && strp[i + 1] >= '5') {
+		while (i >= 0) {
+			strp[i]++;
+			if (strp[i] <= '9')
+				break;
+			if (i == 0) {
+				strp[i] = '1';
+				exp++;
+			} else {
+				strp[i] = '0';
+			}
+			i--;
+		}
+	}
+	strp[ndigits] = 0;
+
+	// store first digit of mantissa
+	cp = strp;
+	wrd[0] |= *cp++ - '0';
+
+	// store rest of mantissa
+	for (j = 1; j < 3; j++) {
+		for (i = 0; i < 8; i++) {
+			wrd[j] <<= 4;
+			if (*cp >= '0' && *cp <= '9')
+				wrd[j] |= *cp++ - '0';
+		}
+	}
+
+	// exponent
+	if (exp < 0) {
+		wrd[0] |= 0x40000000;
+		exp = -exp;
+	}
+	if (exp > 9999) // ??
+		exp = 9999;
+	if (exp > 999) {
+		int d = exp / 1000;
+		wrd[0] |= d << 12;
+		exp -= d * 1000;
+		//update_fpsr (FE_INVALID);
+	}
+	i = 100;
+	t = 0;
+	while (i >= 1) {
+		int d = exp / i;
+		t <<= 4;
+		t |= d;
+		exp -= d * i;
+		i /= 10;
+	}
+	wrd[0] |= t << 16;
+}
+
+// 68040/060 does not support denormals
+static bool fault_if_no_denormal_support_pre(uae_u16 opcode, uae_u16 extra, uaecptr ea, uaecptr oldpc, fpdata *fpd, int size)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.cpu_model >= 68040 && currprefs.fpu_model && currprefs.fpu_no_unimplemented && currprefs.fpu_softfloat) {
+		Bit64u Sig = extractFloatx80Frac(fpd->fpx);
+		Bit32s Exp = extractFloatx80Exp(fpd->fpx);
+		if (Exp == 0 && Sig != 0) {
+			fpu_op_unimp(opcode, extra, ea, oldpc, FPU_EXP_UNIMP_DATATYPE_PRE, fpd, -1, size);
+			return true;
+		}
+	}
+#endif
+	return false;
+}
+static bool fault_if_no_denormal_support_post(uae_u16 opcode, uae_u16 extra, uaecptr ea, uaecptr oldpc, fpdata *fpd, int size)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat && currprefs.cpu_model >= 68040 && currprefs.fpu_model && currprefs.fpu_no_unimplemented) {
+		Bit64u Sig = extractFloatx80Frac(fpd->fpx);
+		Bit32s Exp = extractFloatx80Exp(fpd->fpx);
+		if (Exp == 0 && Sig != 0) {
+			fpu_op_unimp(opcode, extra, ea, oldpc, FPU_EXP_UNIMP_DATATYPE_POST, fpd, -1, size);
+			return true;
+		}
+	}
+#endif
+	return false;
+}
+
+static int get_fp_value (uae_u32 opcode, uae_u16 extra, fpdata *src, uaecptr oldpc, uae_u32 *adp)
+{
+	int size, mode, reg;
+	uae_u32 ad = 0;
+	static const int sz1[8] = { 4, 4, 12, 12, 2, 8, 1, 0 };
+	static const int sz2[8] = { 4, 4, 12, 12, 2, 8, 2, 0 };
+	uae_u32 exts[3];
+	int doext = 0;
+
+	if (!(extra & 0x4000)) {
+		if (fault_if_no_fpu (opcode, extra, 0, oldpc))
+			return -1;
+		*src = regs.fp[(extra >> 10) & 7];
+		if (fault_if_no_denormal_support_pre(opcode, extra, 0, oldpc, src, 2))
+			return -1;
+		return 1;
+	}
+	mode = (opcode >> 3) & 7;
+	reg = opcode & 7;
+	size = (extra >> 10) & 7;
+
+	switch (mode) {
+		case 0:
+			switch (size)
+			{
+				case 6:
+					fpset(src, (uae_s8) m68k_dreg (regs, reg));
+					break;
+				case 4:
+					fpset(src, (uae_s16) m68k_dreg (regs, reg));
+					break;
+				case 0:
+					fpset(src, (uae_s32) m68k_dreg (regs, reg));
+					break;
+				case 1:
+					to_single (src, m68k_dreg (regs, reg));
+					if (fault_if_no_denormal_support_pre(opcode, extra, 0, oldpc, src, 0))
+						return -1;
+					break;
+				default:
+					return 0;
+			}
+			return 1;
+		case 1:
+			return 0;
+		case 2:
+			ad = m68k_areg (regs, reg);
+			break;
+		case 3:
+			if (currprefs.mmu_model) {
+				mmufixup[0].reg = reg;
+				mmufixup[0].value = m68k_areg (regs, reg);
+				fpu_mmu_fixup = true;
+			}
+			ad = m68k_areg (regs, reg);
+			m68k_areg (regs, reg) += reg == 7 ? sz2[size] : sz1[size];
+			break;
+		case 4:
+			if (currprefs.mmu_model) {
+				mmufixup[0].reg = reg;
+				mmufixup[0].value = m68k_areg (regs, reg);
+				fpu_mmu_fixup = true;
+			}
+			m68k_areg (regs, reg) -= reg == 7 ? sz2[size] : sz1[size];
+			ad = m68k_areg (regs, reg);
+			break;
+		case 5:
+			ad = m68k_areg (regs, reg) + (uae_s32) (uae_s16) x_cp_next_iword ();
+			break;
+		case 6:
+			ad = x_cp_get_disp_ea_020 (m68k_areg (regs, reg), 0);
+			break;
+		case 7:
+			switch (reg)
+			{
+				case 0: // (xxx).W
+					ad = (uae_s32) (uae_s16) x_cp_next_iword ();
+					break;
+				case 1: // (xxx).L
+					ad = x_cp_next_ilong ();
+					break;
+				case 2: // (d16,PC)
+					ad = m68k_getpc ();
+					ad += (uae_s32) (uae_s16) x_cp_next_iword ();
+					break;
+				case 3: // (d8,PC,Xn)+
+					ad = x_cp_get_disp_ea_020 (m68k_getpc (), 0);
+					break;
+				case 4: // #imm
+					doext = 1;
+					switch (size)
+					{
+						case 0: // L
+						case 1: // S
+						exts[0] = x_cp_next_ilong ();
+						break;
+						case 2: // X
+						case 3: // P
+						// 68060 and immediate X or P: unimplemented effective address
+						if (fault_if_60 (opcode, extra, ad, oldpc, FPU_EXP_UNIMP_EA))
+							return -1;
+						exts[0] = x_cp_next_ilong ();
+						exts[1] = x_cp_next_ilong ();
+						exts[2] = x_cp_next_ilong ();
+						break;
+						case 4: // W
+						exts[0] = x_cp_next_iword ();
+						break;
+						case 5: // D
+						exts[0] = x_cp_next_ilong ();
+						exts[1] = x_cp_next_ilong ();
+						break;
+						case 6: // B
+						exts[0] = x_cp_next_iword ();
+						break;
+					}
+					break;
+				default:
+					return 0;
+			}
+	}
+
+	*adp = ad;
+
+	if (currprefs.fpu_model == 68060 && fault_if_unimplemented_680x0 (opcode, extra, ad, oldpc, src, -1))
+		return -1;
+
+	switch (size)
+	{
+		case 0:
+			fpset(src, (uae_s32) (doext ? exts[0] : x_cp_get_long (ad)));
+			break;
+		case 1:
+			to_single (src, (doext ? exts[0] : x_cp_get_long (ad)));
+			if (fault_if_no_denormal_support_pre(opcode, extra, 0, oldpc, src, 0))
+				return -1;
+			break;
+		case 2:
+			{
+				uae_u32 wrd1, wrd2, wrd3;
+				wrd1 = (doext ? exts[0] : x_cp_get_long (ad));
+				ad += 4;
+				wrd2 = (doext ? exts[1] : x_cp_get_long (ad));
+				ad += 4;
+				wrd3 = (doext ? exts[2] : x_cp_get_long (ad));
+				to_exten (src, wrd1, wrd2, wrd3);
+				if (fault_if_no_denormal_support_pre(opcode, extra, 0, oldpc, src, 2))
+					return -1;
+			}
+			break;
+		case 3:
+			{
+				uae_u32 wrd[3];
+				uae_u32 adold = ad;
+				if (currprefs.cpu_model == 68060) {
+					if (fault_if_4060 (opcode, extra, adold, oldpc, FPU_EXP_UNIMP_DATATYPE_PACKED_PRE, NULL, wrd))
+						return -1;
+				}
+				wrd[0] = (doext ? exts[0] : x_cp_get_long (ad));
+				ad += 4;
+				wrd[1] = (doext ? exts[1] : x_cp_get_long (ad));
+				ad += 4;
+				wrd[2] = (doext ? exts[2] : x_cp_get_long (ad));
+				if (fault_if_4060 (opcode, extra, adold, oldpc, FPU_EXP_UNIMP_DATATYPE_PACKED_PRE, NULL, wrd))
+					return -1;
+				to_pack (src, wrd);
+				return 1;
+			}
+			break;
+		case 4:
+			fpset(src, (uae_s16) (doext ? exts[0] : x_cp_get_word (ad)));
+			break;
+		case 5:
+			{
+				uae_u32 wrd1, wrd2;
+				wrd1 = (doext ? exts[0] : x_cp_get_long (ad));
+				ad += 4;
+				wrd2 = (doext ? exts[1] : x_cp_get_long (ad));
+				to_double (src, wrd1, wrd2);
+				if (fault_if_no_denormal_support_pre(opcode, extra, 0, oldpc, src, 1))
+					return -1;
+			}
+			break;
+		case 6:
+			fpset(src, (uae_s8) (doext ? exts[0] : x_cp_get_byte (ad)));
+			break;
+		default:
+			return 0;
+	}
+	return 1;
+}
+
+static int put_fp_value (fpdata *value, uae_u32 opcode, uae_u16 extra, uaecptr oldpc)
+{
+	int size, mode, reg;
+	uae_u32 ad = 0;
+	static int sz1[8] = { 4, 4, 12, 12, 2, 8, 1, 0 };
+	static int sz2[8] = { 4, 4, 12, 12, 2, 8, 2, 0 };
+
+#if DEBUG_FPP
+	if (!isinrom ())
+		write_log (_T("PUTFP: %f %04X %04X\n"), value, opcode, extra);
+#endif
+	if (!(extra & 0x4000)) {
+		if (fault_if_no_fpu (opcode, extra, 0, oldpc))
+			return 1;
+		regs.fp[(extra >> 10) & 7] = *value;
+		return 1;
+	}
+	reg = opcode & 7;
+	mode = (opcode >> 3) & 7;
+	size = (extra >> 10) & 7;
+	ad = -1;
+	switch (mode)
+	{
+		case 0:
+			switch (size)
+			{
+				case 6:
+					m68k_dreg (regs, reg) = (uae_u32)(((toint (value, 0) & 0xff)
+						| (m68k_dreg (regs, reg) & ~0xff)));
+					break;
+				case 4:
+					m68k_dreg (regs, reg) = (uae_u32)(((toint (value, 1) & 0xffff)
+						| (m68k_dreg (regs, reg) & ~0xffff)));
+					break;
+				case 0:
+					m68k_dreg (regs, reg) = (uae_u32)toint (value, 2);
+					break;
+				case 1:
+					m68k_dreg (regs, reg) = from_single (value);
+					break;
+				default:
+					return 0;
+			}
+			return 1;
+		case 1:
+			return 0;
+		case 2:
+			ad = m68k_areg (regs, reg);
+			break;
+		case 3:
+			if (currprefs.mmu_model) {
+				mmufixup[0].reg = reg;
+				mmufixup[0].value = m68k_areg (regs, reg);
+				fpu_mmu_fixup = true;
+			}
+			ad = m68k_areg (regs, reg);
+			m68k_areg (regs, reg) += reg == 7 ? sz2[size] : sz1[size];
+			break;
+		case 4:
+			if (currprefs.mmu_model) {
+				mmufixup[0].reg = reg;
+				mmufixup[0].value = m68k_areg (regs, reg);
+				fpu_mmu_fixup = true;
+			}
+			m68k_areg (regs, reg) -= reg == 7 ? sz2[size] : sz1[size];
+			ad = m68k_areg (regs, reg);
+			break;
+		case 5:
+			ad = m68k_areg (regs, reg) + (uae_s32) (uae_s16) x_cp_next_iword ();
+			break;
+		case 6:
+			ad = x_cp_get_disp_ea_020 (m68k_areg (regs, reg), 0);
+			break;
+		case 7:
+			switch (reg)
+			{
+				case 0:
+					ad = (uae_s32) (uae_s16) x_cp_next_iword ();
+					break;
+				case 1:
+					ad = x_cp_next_ilong ();
+					break;
+				case 2:
+					ad = m68k_getpc ();
+					ad += (uae_s32) (uae_s16) x_cp_next_iword ();
+					break;
+				case 3:
+					ad = x_cp_get_disp_ea_020 (m68k_getpc (), 0);
+					break;
+				default:
+					return 0;
+			}
+	}
+
+	if (fault_if_no_fpu (opcode, extra, ad, oldpc))
+		return 1;
+
+	switch (size)
+	{
+		case 0:
+			if (fault_if_no_denormal_support_post(opcode, extra, ad, oldpc, value, 2))
+				return 1;
+			x_cp_put_long(ad, (uae_u32)toint(value, 2));
+			break;
+		case 1:
+			if (fault_if_no_denormal_support_post(opcode, extra, ad, oldpc, value, 2))
+				return -1;
+			x_cp_put_long(ad, from_single(value));
+			break;
+		case 2:
+			{
+				uae_u32 wrd1, wrd2, wrd3;
+				if (fault_if_no_denormal_support_post(opcode, extra, ad, oldpc, value, 2))
+					return 1;
+				from_exten(value, &wrd1, &wrd2, &wrd3);
+				x_cp_put_long (ad, wrd1);
+				ad += 4;
+				x_cp_put_long (ad, wrd2);
+				ad += 4;
+				x_cp_put_long (ad, wrd3);
+			}
+			break;
+		case 3: // Packed-Decimal Real with Static k-Factor
+		case 7: // Packed-Decimal Real with Dynamic k-Factor (P{Dn}) (reg to memory only)
+			{
+				uae_u32 wrd[3];
+				int kfactor;
+				if (fault_if_4060 (opcode, extra, ad, oldpc, FPU_EXP_UNIMP_DATATYPE_PACKED_POST, value, NULL))
+					return 1;
+				kfactor = size == 7 ? m68k_dreg (regs, (extra >> 4) & 7) : extra;
+				kfactor &= 127;
+				if (kfactor & 64)
+					kfactor |= ~63;
+				from_pack (value, wrd, kfactor);
+				x_cp_put_long (ad, wrd[0]);
+				ad += 4;
+				x_cp_put_long (ad, wrd[1]);
+				ad += 4;
+				x_cp_put_long (ad, wrd[2]);
+			}
+			break;
+		case 4:
+			if (fault_if_no_denormal_support_post(opcode, extra, ad, oldpc, value, 2))
+				return 1;
+			x_cp_put_word(ad, (uae_s16)toint(value, 1));
+			break;
+		case 5:
+			{
+				uae_u32 wrd1, wrd2;
+				if (fault_if_no_denormal_support_post(opcode, extra, ad, oldpc, value, 1))
+					return -1;
+				from_double(value, &wrd1, &wrd2);
+				x_cp_put_long (ad, wrd1);
+				ad += 4;
+				x_cp_put_long (ad, wrd2);
+			}
+			break;
+		case 6:
+			if (fault_if_no_denormal_support_post(opcode, extra, ad, oldpc, value, 2))
+				return 1;
+			x_cp_put_byte(ad, (uae_s8)toint(value, 0));
+			break;
+		default:
+			return 0;
+	}
+	return 1;
+}
+
+STATIC_INLINE int get_fp_ad (uae_u32 opcode, uae_u32 * ad)
+{
+	int mode;
+	int reg;
+
+	mode = (opcode >> 3) & 7;
+	reg = opcode & 7;
+	switch (mode)
+	{
+		case 0:
+		case 1:
+			return 0;
+		case 2:
+			*ad = m68k_areg (regs, reg);
+			break;
+		case 3:
+			*ad = m68k_areg (regs, reg);
+			break;
+		case 4:
+			*ad = m68k_areg (regs, reg);
+			break;
+		case 5:
+			*ad = m68k_areg (regs, reg) + (uae_s32) (uae_s16) x_cp_next_iword ();
+			break;
+		case 6:
+			*ad = x_cp_get_disp_ea_020 (m68k_areg (regs, reg), 0);
+			break;
+		case 7:
+			switch (reg)
+			{
+				case 0:
+					*ad = (uae_s32) (uae_s16) x_cp_next_iword ();
+					break;
+				case 1:
+					*ad = x_cp_next_ilong ();
+					break;
+				case 2:
+					*ad = m68k_getpc ();
+					*ad += (uae_s32) (uae_s16) x_cp_next_iword ();
+					break;
+				case 3:
+					*ad = x_cp_get_disp_ea_020 (m68k_getpc (), 0);
+					break;
+				default:
+					return 0;
+			}
+	}
+	return 1;
+}
+
+int fpp_cond (int condition)
+{
+	int NotANumber, Z, N;
+
+	NotANumber = fp_is_nan(®s.fp_result);
+	N = fp_is_neg(®s.fp_result);
+	Z = fp_is_zero(®s.fp_result);
+
+	if ((condition & 0x10) && NotANumber)
+		regs.fp_result_status |= FP_BSUN;
+
+	switch (condition)
+	{
+		case 0x00:
+			return 0;
+		case 0x01:
+			return Z;
+		case 0x02:
+			return !(NotANumber || Z || N);
+		case 0x03:
+			return Z || !(NotANumber || N);
+		case 0x04:
+			return N && !(NotANumber || Z);
+		case 0x05:
+			return Z || (N && !NotANumber);
+		case 0x06:
+			return !(NotANumber || Z);
+		case 0x07:
+			return !NotANumber;
+		case 0x08:
+			return NotANumber;
+		case 0x09:
+			return NotANumber || Z;
+		case 0x0a:
+			return NotANumber || !(N || Z);
+		case 0x0b:
+			return NotANumber || Z || !N;
+		case 0x0c:
+			return NotANumber || (N && !Z);
+		case 0x0d:
+			return NotANumber || Z || N;
+		case 0x0e:
+			return !Z;
+		case 0x0f:
+			return 1;
+		case 0x10:
+			return 0;
+		case 0x11:
+			return Z;
+		case 0x12:
+			return !(NotANumber || Z || N);
+		case 0x13:
+			return Z || !(NotANumber || N);
+		case 0x14:
+			return N && !(NotANumber || Z);
+		case 0x15:
+			return Z || (N && !NotANumber);
+		case 0x16:
+			return !(NotANumber || Z);
+		case 0x17:
+			return !NotANumber;
+		case 0x18:
+			return NotANumber;
+		case 0x19:
+			return NotANumber || Z;
+		case 0x1a:
+			return NotANumber || !(N || Z);
+		case 0x1b:
+			return NotANumber || Z || !N;
+		case 0x1c:
+			return NotANumber || (N && !Z);
+		case 0x1d:
+			return NotANumber || Z || N;
+		case 0x1e:
+			return !Z;
+		case 0x1f:
+			return 1;
+	}
+	return -1;
+}
+
+static void maybe_idle_state (void)
+{
+	// conditional floating point instruction does not change state
+	// from null to idle on 68040/060.
+	if (currprefs.fpu_model == 68881 || currprefs.fpu_model == 68882)
+		regs.fpu_state = 1;
+}
+
+void fpuop_dbcc (uae_u32 opcode, uae_u16 extra)
+{
+	uaecptr pc = m68k_getpc ();
+	uae_s32 disp;
+	int cc;
+
+	regs.fp_exception = false;
+#if DEBUG_FPP
+	if (!isinrom ())
+		write_log (_T("fdbcc_opp at %08x\n"), m68k_getpc ());
+#endif
+	if (fault_if_no_6888x (opcode, extra, pc - 4))
+		return;
+
+	disp = (uae_s32) (uae_s16) x_cp_next_iword ();
+	if (fault_if_no_fpu_u (opcode, extra, pc + disp, pc - 4))
+		return;
+	regs.fpiar = pc - 4;
+	maybe_idle_state ();
+	cc = fpp_cond (extra & 0x3f);
+	if (cc < 0) {
+		fpu_op_illg (opcode, extra, regs.fpiar);
+	} else if (!cc) {
+		int reg = opcode & 0x7;
+
+		m68k_dreg (regs, reg) = ((m68k_dreg (regs, reg) & 0xffff0000)
+			| (((m68k_dreg (regs, reg) & 0xffff) - 1) & 0xffff));
+		if ((m68k_dreg (regs, reg) & 0xffff) != 0xffff) {
+			m68k_setpc (pc + disp);
+			regs.fp_branch = true;
+		}
+	}
+}
+
+void fpuop_scc (uae_u32 opcode, uae_u16 extra)
+{
+	uae_u32 ad = 0;
+	int cc;
+	uaecptr pc = m68k_getpc () - 4;
+
+	regs.fp_exception = false;
+#if DEBUG_FPP
+	if (!isinrom ())
+		write_log (_T("fscc_opp at %08x\n"), m68k_getpc ());
+#endif
+
+	if (fault_if_no_6888x (opcode, extra, pc))
+		return;
+
+	if (opcode & 0x38) {
+		if (get_fp_ad (opcode, &ad) == 0) {
+			fpu_noinst (opcode, regs.fpiar);
+			return;
+		}
+	}
+
+	if (fault_if_no_fpu_u (opcode, extra, ad, pc))
+		return;
+
+	regs.fpiar = pc;
+	maybe_idle_state ();
+	cc = fpp_cond (extra & 0x3f);
+	if (cc < 0) {
+		fpu_op_illg (opcode, extra, regs.fpiar);
+	} else if ((opcode & 0x38) == 0) {
+		m68k_dreg (regs, opcode & 7) = (m68k_dreg (regs, opcode & 7) & ~0xff) | (cc ? 0xff : 0x00);
+	} else {
+		x_cp_put_byte (ad, cc ? 0xff : 0x00);
+	}
+}
+
+void fpuop_trapcc (uae_u32 opcode, uaecptr oldpc, uae_u16 extra)
+{
+	int cc;
+
+	regs.fp_exception = false;
+#if DEBUG_FPP
+	if (!isinrom ())
+		write_log (_T("ftrapcc_opp at %08x\n"), m68k_getpc ());
+#endif
+	if (fault_if_no_fpu_u (opcode, extra, 0, oldpc))
+		return;
+
+	regs.fpiar = oldpc;
+	maybe_idle_state ();
+	cc = fpp_cond (extra & 0x3f);
+	if (cc < 0) {
+		fpu_op_illg (opcode, extra, oldpc);
+	} else if (cc) {
+		Exception (7);
+	}
+}
+
+void fpuop_bcc (uae_u32 opcode, uaecptr oldpc, uae_u32 extra)
+{
+	int cc;
+
+	regs.fp_exception = false;
+#if DEBUG_FPP
+	if (!isinrom ())
+		write_log (_T("fbcc_opp at %08x\n"), m68k_getpc ());
+#endif
+	if (fault_if_no_fpu (opcode, extra, 0, oldpc - 2))
+		return;
+
+	regs.fpiar = oldpc - 2;
+	maybe_idle_state ();
+	cc = fpp_cond (opcode & 0x3f);
+	if (cc < 0) {
+		fpu_op_illg (opcode, extra, oldpc - 2);
+	} else if (cc) {
+		if ((opcode & 0x40) == 0)
+			extra = (uae_s32) (uae_s16) extra;
+		m68k_setpc (oldpc + extra);
+		regs.fp_branch = true;
+	}
+}
+
+void fpuop_save (uae_u32 opcode)
+{
+	uae_u32 ad;
+	int incr = (opcode & 0x38) == 0x20 ? -1 : 1;
+	int fpu_version = get_fpu_version ();
+	uaecptr pc = m68k_getpc () - 2;
+	int i;
+
+	regs.fp_exception = false;
+#if DEBUG_FPP
+	if (!isinrom ())
+		write_log (_T("fsave_opp at %08x\n"), m68k_getpc ());
+#endif
+
+	if (fault_if_no_6888x (opcode, 0, pc))
+		return;
+
+	if (get_fp_ad (opcode, &ad) == 0) {
+		fpu_op_illg (opcode, 0, pc);
+		return;
+	}
+
+	if (fault_if_no_fpu (opcode, 0, ad, pc))
+		return;
+
+	if (currprefs.fpu_model == 68060) {
+		/* 12 byte 68060 NULL/IDLE/EXCP frame.  */
+		int frame_size = 12;
+		uae_u32 frame_id, frame_v1, frame_v2;
+		
+		if (regs.fpu_exp_state > 1) {
+			uae_u32 src1[3];
+			from_exten (®s.exp_src1, &src1[0], &src1[1], &src1[2]);
+			frame_id = 0x0000e000 | src1[0];
+			frame_v1 = src1[1];
+			frame_v2 = src1[2];
+
+#if EXCEPTION_FPP
+#if USE_LONG_DOUBLE
+			write_log(_T("68060 FSAVE EXCP %Le\n"), regs.exp_src1.fp);
+#else
+			write_log(_T("68060 FSAVE EXCP %e\n"), regs.exp_src1.fp);
+#endif
+#endif
+
+		} else {
+			frame_id = regs.fpu_state == 0 ? 0x00000000 : 0x00006000;
+			frame_v1 = 0;
+			frame_v2 = 0;
+		}
+		if (incr < 0)
+			ad -= frame_size;
+		x_put_long (ad, frame_id);
+		ad += 4;
+		x_put_long (ad, frame_v1);
+		ad += 4;
+		x_put_long (ad, frame_v2);
+		ad += 4;
+		if (incr < 0)
+			ad -= frame_size;
+	} else if (currprefs.fpu_model == 68040) {
+		if (!regs.fpu_exp_state) {
+			/* 4 byte 68040 NULL/IDLE frame.  */
+			uae_u32 frame_id = regs.fpu_state == 0 ? 0 : fpu_version << 24;
+			if (incr < 0) {
+				ad -= 4;
+				x_put_long (ad, frame_id);
+			} else {
+				x_put_long (ad, frame_id);
+				ad += 4;
+			}
+		} else {
+			/* 44 (rev $40) and 52 (rev $41) byte 68040 unimplemented instruction frame */
+			/* 96 byte 68040 busy frame */
+			int frame_size = regs.fpu_exp_state == 2 ? 0x64 : (fpu_version >= 0x41 ? 0x34 : 0x2c);
+			uae_u32 frame_id = ((fpu_version << 8) | (frame_size - 4)) << 16;
+			uae_u32 src1[3], src2[3];
+			uae_u32 stag, dtag;
+			uae_u32 extra = regs.exp_extra;
+
+			from_exten(®s.exp_src1, &src1[0], &src1[1], &src1[2]);
+			from_exten(®s.exp_src2, &src2[0], &src2[1], &src2[2]);
+			stag = get_ftag(src1[0], src1[1], src1[2], regs.exp_size);
+			dtag = get_ftag(src2[0], src2[1], src2[2], -1);
+			if ((extra & 0x7f) == 4) // FSQRT 4->5
+				extra |= 1;
+
+#if EXCEPTION_FPP
+			write_log(_T("68040 FSAVE %d (%d), CMDREG=%04X"), regs.exp_type, frame_size, extra);
+			if (regs.exp_type == FPU_EXP_UNIMP_DATATYPE_PACKED_PRE) {
+				write_log(_T(" PACKED %08x-%08x-%08x"), regs.exp_pack[0], regs.exp_pack[1], regs.exp_pack[2]);
+			} else if (regs.exp_type == FPU_EXP_UNIMP_DATATYPE_PACKED_POST) {
+#if USE_LONG_DOUBLE
+				write_log(_T(" SRC=%Le (%08x-%08x-%08x %d), DST=%Le (%08x-%08x-%08x %d)"), regs.exp_src1.fp, src1[0], src1[1], src1[2], stag, regs.exp_src2.fp, src2[0], src2[1], src2[2], dtag);
+#else
+				write_log(_T(" SRC=%e (%08x-%08x-%08x %d), DST=%e (%08x-%08x-%08x %d)"), regs.exp_src1.fp, src1[0], src1[1], src1[2], stag, regs.exp_src2.fp, src2[0], src2[1], src2[2], dtag);
+#endif
+			}
+			write_log(_T("\n"));
+#endif
+
+			if (incr < 0)
+				ad -= frame_size;
+			x_put_long (ad, frame_id);
+			ad += 4;
+			if (regs.fpu_exp_state == 2) {
+				/* BUSY frame */
+				x_put_long(ad, 0);
+				ad += 4;
+				x_put_long(ad, 0); // CU_SAVEPC (Software shouldn't care)
+				ad += 4;
+				x_put_long(ad, 0);
+				ad += 4;
+				x_put_long(ad, 0);
+				ad += 4;
+				x_put_long(ad, 0);
+				ad += 4;
+				x_put_long(ad, 0); // WBTS/WBTE (No E3 emulated yet)
+				ad += 4;
+				x_put_long(ad, 0); // WBTM
+				ad += 4;
+				x_put_long(ad, 0); // WBTM
+				ad += 4;
+				x_put_long(ad, 0);
+				ad += 4;
+				x_put_long(ad, regs.fpiar); // FPIARCU (same as FPU PC or something else?)
+				ad += 4;
+				x_put_long(ad, 0);
+				ad += 4;
+				x_put_long(ad, 0);
+				ad += 4;
+			}
+			if (fpu_version >= 0x41 || regs.fpu_exp_state == 2) {
+				x_put_long (ad, ((extra & (0x200 | 0x100 | 0x80)) | (extra & (0x40 | 0x02 | 0x01)) | ((extra >> 1) & (0x04 | 0x08 | 0x10)) | ((extra & 0x04) ? 0x20 : 0x00)) << 16); // CMDREG3B
+				ad += 4;
+				x_put_long (ad, 0);
+				ad += 4;
+			}
+			x_put_long (ad, stag << 29); // STAG
+			ad += 4;
+			x_put_long (ad, extra << 16); // CMDREG1B
+			ad += 4;
+			x_put_long (ad, dtag << 29); // DTAG
+			ad += 4;
+			if (fpu_version >= 0x41 || regs.fpu_exp_state == 2) {
+				x_put_long(ad, (regs.exp_type == FPU_EXP_UNIMP_DATATYPE_PACKED_PRE ? 1 << 26 : 0) | (regs.exp_type == FPU_EXP_UNIMP_DATATYPE_PACKED_POST ? 1 << 20 : 0)); // E1 and T
+				ad += 4;
+			} else {
+				x_put_long(ad, (regs.exp_type == FPU_EXP_UNIMP_DATATYPE_PACKED_PRE || regs.exp_type == FPU_EXP_UNIMP_DATATYPE_PACKED_POST) ? 1 << 26 : 0); // E1
+				ad += 4;
+			}
+			if (regs.exp_type == FPU_EXP_UNIMP_DATATYPE_PACKED_PRE) {
+				x_put_long (ad, 0); // FPTS/FPTE
+				ad += 4;
+				x_put_long (ad, 0); // FPTM
+				ad += 4;
+				x_put_long (ad, regs.exp_pack[0]); // FPTM
+				ad += 4;
+				x_put_long (ad, 0); // ETS/ETE
+				ad += 4;
+				x_put_long (ad, regs.exp_pack[1]); // ETM
+				ad += 4;
+				x_put_long (ad, regs.exp_pack[2]); // ETM
+				ad += 4;
+			} else {
+				x_put_long (ad, src2[0]); // FPTS/FPTE
+				ad += 4;
+				x_put_long (ad, src2[1]); // FPTM
+				ad += 4;
+				x_put_long (ad, src2[2]); // FPTM
+				ad += 4;
+				x_put_long (ad, src1[0]); // ETS/ETE
+				ad += 4;
+				x_put_long (ad, src1[1]); // ETM
+				ad += 4;
+				x_put_long (ad, src1[2]); // ETM
+				ad += 4;
+			}
+			if (incr < 0)
+				ad -= frame_size;
+		}
+	} else { /* 68881/68882 */
+		int frame_size_real = currprefs.fpu_model == 68882 ? 0x3c : 0x1c;;
+		int frame_size = regs.fpu_state == 0 ? 0 : frame_size_real;
+		uae_u32 frame_id = regs.fpu_state == 0 ? ((frame_size_real - 4) << 16) : (fpu_version << 24) | ((frame_size_real - 4) << 16);
+	
+		if (currprefs.mmu_model) {
+			if (incr < 0) {
+				for (i = 0; i < (frame_size / 4) - 1; i++) {
+					ad -= 4;
+					if (mmu030_state[0] == i) {
+						x_put_long (ad, i == 0 ? 0x70000000 : 0x00000000);
+						mmu030_state[0]++;
+					}
+				}
+				ad -= 4;
+				if (mmu030_state[0] == (frame_size / 4) - 1 || (mmu030_state[0] == 0 && frame_size == 0)) {
+					x_put_long (ad, frame_id);
+					mmu030_state[0]++;
+				}
+			} else {
+				if (mmu030_state[0] == 0) {
+					x_put_long (ad, frame_id);
+					mmu030_state[0]++;
+				}
+				ad += 4;
+				for (i = 0; i < (frame_size / 4) - 1; i++) {
+					if (mmu030_state[0] == i + 1) {
+						x_put_long (ad, i == (frame_size / 4) - 2 ? 0x70000000 : 0x00000000);
+						mmu030_state[0]++;
+					}
+					ad += 4;
+				}
+			}
+		} else {
+			if (incr < 0) {
+				for (i = 0; i < (frame_size / 4) - 1; i++) {
+					ad -= 4;
+					x_put_long (ad, i == 0 ? 0x70000000 : 0x00000000);
+				}
+				ad -= 4;
+				x_put_long (ad, frame_id);
+			} else {
+				x_put_long (ad, frame_id);
+				ad += 4;
+				for (i = 0; i < (frame_size / 4) - 1; i++) {
+					x_put_long (ad, i == (frame_size / 4) - 2 ? 0x70000000 : 0x00000000);
+					ad += 4;
+				}
+			}
+		}
+	}
+
+	if ((opcode & 0x38) == 0x18)
+		m68k_areg (regs, opcode & 7) = ad;
+	if ((opcode & 0x38) == 0x20)
+		m68k_areg (regs, opcode & 7) = ad;
+	regs.fpu_exp_state = 0;
+}
+
+void fpuop_restore (uae_u32 opcode)
+{
+#ifndef WINUAE_FOR_HATARI
+	int fpu_version = get_fpu_version (); // TODO: check version of stack frame
+#endif
+	uaecptr pc = m68k_getpc () - 2;
+	uae_u32 ad;
+	uae_u32 d;
+	int incr = (opcode & 0x38) == 0x20 ? -1 : 1;
+
+	regs.fp_exception = false;
+#if DEBUG_FPP
+	if (!isinrom ())
+		write_log (_T("frestore_opp at %08x\n"), m68k_getpc ());
+#endif
+
+	if (fault_if_no_6888x (opcode, 0, pc))
+		return;
+
+	if (get_fp_ad (opcode, &ad) == 0) {
+		fpu_op_illg (opcode, 0, pc);
+		return;
+	}
+
+	if (fault_if_no_fpu (opcode, 0, ad, pc))
+		return;
+	regs.fpiar = pc;
+
+	if (incr < 0) {
+		ad -= 4;
+		d = x_get_long (ad);
+	} else {
+		d = x_get_long (ad);
+		ad += 4;
+	}
+
+	if (currprefs.fpu_model == 68060) {
+		int ff = (d >> 8) & 0xff;
+		uae_u32 v1, v2;
+
+		if (incr < 0) {
+			ad -= 4;
+			v1 = x_get_long (ad);
+			ad -= 4;
+			v2 = x_get_long (ad);
+		} else {
+			v1 = x_get_long (ad);
+			ad += 4;
+			v2 = x_get_long (ad);
+			ad += 4;
+		}
+		if (ff == 0x60) {
+			regs.fpu_state = 1;
+			regs.fpu_exp_state = 0;
+		} else if (ff == 0xe0) {
+			regs.fpu_exp_state = 1;
+			to_exten (®s.exp_src1, d & 0xffff0000, v1, v2);
+		} else if (ff) {
+			write_log (_T("FRESTORE invalid frame format %X!\n"), (d >> 8) & 0xff);
+		} else {
+			fpu_null ();
+		}
+	} else {
+		if ((d & 0xff000000) != 0) {
+			regs.fpu_state = 1;
+			if (incr < 0)
+				ad -= (d >> 16) & 0xff;
+			else
+				ad += (d >> 16) & 0xff;
+		} else {
+			fpu_null ();
+		}
+	}
+
+	if ((opcode & 0x38) == 0x18)
+		m68k_areg (regs, opcode & 7) = ad;
+	if ((opcode & 0x38) == 0x20)
+		m68k_areg (regs, opcode & 7) = ad;
+}
+
+static uaecptr fmovem2mem (uaecptr ad, uae_u32 list, int incr, int regdir)
+{
+	int reg;
+
+	// 68030 MMU state saving is annoying!
+	if (currprefs.mmu_model == 68030) {
+		int idx = 0;
+		int r;
+		int i;
+		uae_u32 wrd[3];
+		mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;
+		for (r = 0; r < 8; r++) {
+			if (regdir < 0)
+				reg = 7 - r;
+			else
+				reg = r;
+			if (list & 0x80) {
+				from_exten(®s.fp[reg], &wrd[0], &wrd[1], &wrd[2]);
+				if (incr < 0)
+					ad -= 3 * 4;
+				for (i = 0; i < 3; i++) {
+					if (mmu030_state[0] == idx * 3 + i) {
+						if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+							mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+						}
+						else {
+							mmu030_data_buffer = wrd[i];
+							x_put_long(ad + i * 4, wrd[i]);
+						}
+						mmu030_state[0]++;
+					}
+				}
+				if (incr > 0)
+					ad += 3 * 4;
+				idx++;
+			}
+			list <<= 1;
+		}
+	} else {
+		int r;
+		for (r = 0; r < 8; r++) {
+			uae_u32 wrd1, wrd2, wrd3;
+			if (regdir < 0)
+				reg = 7 - r;
+			else
+				reg = r;
+			if (list & 0x80) {
+				from_exten(®s.fp[reg], &wrd1, &wrd2, &wrd3);
+				if (incr < 0)
+					ad -= 3 * 4;
+				x_put_long(ad + 0, wrd1);
+				x_put_long(ad + 4, wrd2);
+				x_put_long(ad + 8, wrd3);
+				if (incr > 0)
+					ad += 3 * 4;
+			}
+			list <<= 1;
+		}
+	}
+	return ad;
+}
+
+static uaecptr fmovem2fpp (uaecptr ad, uae_u32 list, int incr, int regdir)
+{
+	int reg;
+
+	if (currprefs.mmu_model == 68030) {
+		uae_u32 wrd[3];
+		int idx = 0;
+		int r;
+		int i;
+		mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1 | MMU030_STATEFLAG1_FMOVEM;
+		if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)
+			ad = mmu030_ad[mmu030_idx].val;
+		else
+			mmu030_ad[mmu030_idx].val = ad;
+		for (r = 0; r < 8; r++) {
+			if (regdir < 0)
+				reg = 7 - r;
+			else
+				reg = r;
+			if (list & 0x80) {
+				if (incr < 0)
+					ad -= 3 * 4;
+				for (i = 0; i < 3; i++) {
+					if (mmu030_state[0] == idx * 3 + i) {
+						if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {
+							mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;
+							wrd[i] = mmu030_data_buffer;
+						} else {
+							wrd[i] = x_get_long (ad + i * 4);
+						}
+						// save first two entries if 2nd or 3rd get_long() faults.
+						if (i == 0 || i == 1)
+							mmu030_fmovem_store[i] = wrd[i];
+						mmu030_state[0]++;
+						if (i == 2)
+							to_exten (®s.fp[reg], mmu030_fmovem_store[0], mmu030_fmovem_store[1], wrd[2]);
+					}
+				}
+				if (incr > 0)
+					ad += 3 * 4;
+				idx++;
+			}
+			list <<= 1;
+		}
+	} else {
+		int r;
+		for (r = 0; r < 8; r++) {
+			uae_u32 wrd1, wrd2, wrd3;
+			if (regdir < 0)
+				reg = 7 - r;
+			else
+				reg = r;
+			if (list & 0x80) {
+				if (incr < 0)
+					ad -= 3 * 4;
+				wrd1 = x_get_long (ad + 0);
+				wrd2 = x_get_long (ad + 4);
+				wrd3 = x_get_long (ad + 8);
+				if (incr > 0)
+					ad += 3 * 4;
+				to_exten (®s.fp[reg], wrd1, wrd2, wrd3);
+			}
+			list <<= 1;
+		}
+	}
+	return ad;
+}
+
+// round to float
+static void fround (int reg)
+{
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat) {
+		float32 f = floatx80_to_float32(regs.fp[reg].fpx, fxstatus);
+		regs.fp[reg].fpx = float32_to_floatx80(f, fxstatus);
+	} else
+#endif
+		regs.fp[reg].fp = (float)regs.fp[reg].fp;
+}
+
+static bool arithmetic_fp(fptype src, int reg, int extra)
+{
+	bool sgl = false;
+	switch (extra & 0x7f)
+	{
+		case 0x00: /* FMOVE */
+		case 0x40: /* Explicit rounding. This is just a quick fix. */
+		case 0x44: /* Same for all other cases that have three choices */
+			regs.fp[reg].fp = src;        /* Brian King was here. */
+			/* to register needs FPSR updated. See Motorola 68K Manual. */
+			break;
+		case 0x01: /* FINT */
+			/* need to take the current rounding mode into account */
+#if defined(X86_MSVC_ASSEMBLY_FPU)
+			{
+				fptype tmp_fp;
+				__asm {
+					fld  LDPTR src
+					frndint
+					fstp LDPTR tmp_fp
+				}
+				regs.fp[reg].fp = tmp_fp;
+			}
+#else /* no X86_MSVC */
+			switch (regs.fpcr & 0x30)
+			{
+				case FPCR_ROUND_NEAR:
+					regs.fp[reg].fp = fp_round_to_nearest(src);
+					break;
+				case FPCR_ROUND_ZERO:
+					regs.fp[reg].fp = fp_round_to_zero(src);
+					break;
+				case FPCR_ROUND_MINF:
+					regs.fp[reg].fp = fp_round_to_minus_infinity(src);
+					break;
+				case FPCR_ROUND_PINF:
+					regs.fp[reg].fp = fp_round_to_plus_infinity(src);
+					break;
+				default: /* never reached */
+					regs.fp[reg].fp = src;
+					break;
+			}
+#endif /* X86_MSVC */
+			break;
+		case 0x02: /* FSINH */
+			regs.fp[reg].fp = sinh (src);
+			break;
+		case 0x03: /* FINTRZ */
+			regs.fp[reg].fp = fp_round_to_zero (src);
+			break;
+		case 0x04: /* FSQRT */
+		case 0x41: /* FSSQRT */
+		case 0x45: /* FDSQRT */
+			regs.fp[reg].fp = sqrt (src);
+			break;
+		case 0x06: /* FLOGNP1 */
+			regs.fp[reg].fp = log (src + 1.0);
+			break;
+		case 0x08: /* FETOXM1 */
+			regs.fp[reg].fp = exp (src) - 1.0;
+			break;
+		case 0x09: /* FTANH */
+			regs.fp[reg].fp = tanh (src);
+			break;
+		case 0x0a: /* FATAN */
+			regs.fp[reg].fp = atan (src);
+			break;
+		case 0x0c: /* FASIN */
+			regs.fp[reg].fp = asin (src);
+			break;
+		case 0x0d: /* FATANH */
+			regs.fp[reg].fp = atanh (src);
+			break;
+		case 0x0e: /* FSIN */
+			regs.fp[reg].fp = sin (src);
+			break;
+		case 0x0f: /* FTAN */
+			regs.fp[reg].fp = tan (src);
+			break;
+		case 0x10: /* FETOX */
+			regs.fp[reg].fp = exp (src);
+			break;
+		case 0x11: /* FTWOTOX */
+			regs.fp[reg].fp = pow (2.0, src);
+			break;
+		case 0x12: /* FTENTOX */
+			regs.fp[reg].fp = pow (10.0, src);
+			break;
+		case 0x14: /* FLOGN */
+			regs.fp[reg].fp = log (src);
+			break;
+		case 0x15: /* FLOG10 */
+			regs.fp[reg].fp = log10 (src);
+			break;
+		case 0x16: /* FLOG2 */
+			regs.fp[reg].fp = *fp_l2_e * log (src);
+			break;
+		case 0x18: /* FABS */
+		case 0x58: /* FSABS */
+		case 0x5c: /* FDABS */
+			regs.fp[reg].fp = src < 0 ? -src : src;
+			break;
+		case 0x19: /* FCOSH */
+			regs.fp[reg].fp = cosh (src);
+			break;
+		case 0x1a: /* FNEG */
+		case 0x5a: /* FSNEG */
+		case 0x5e: /* FDNEG */
+			regs.fp[reg].fp = -src;
+			break;
+		case 0x1c: /* FACOS */
+			regs.fp[reg].fp = acos (src);
+			break;
+		case 0x1d: /* FCOS */
+			regs.fp[reg].fp = cos (src);
+			break;
+		case 0x1e: /* FGETEXP */
+			{
+				if (src == 0) {
+					regs.fp[reg].fp = 0;
+				} else {
+					int expon;
+					frexp (src, &expon);
+					regs.fp[reg].fp = (double) (expon - 1);
+				}
+			}
+			break;
+		case 0x1f: /* FGETMAN */
+			{
+				if (src == 0) {
+					regs.fp[reg].fp = 0;
+				} else {
+					int expon;
+					regs.fp[reg].fp = frexp (src, &expon) * 2.0;
+				}
+			}
+			break;
+		case 0x20: /* FDIV */
+		case 0x60: /* FSDIV */
+		case 0x64: /* FDDIV */
+			regs.fp[reg].fp /= src;
+			break;
+		case 0x21: /* FMOD */
+			{
+				fptype quot = fp_round_to_zero(regs.fp[reg].fp / src);
+				regs.fp[reg].fp = regs.fp[reg].fp - quot * src;
+			}
+			break;
+		case 0x22: /* FADD */
+		case 0x62: /* FSADD */
+		case 0x66: /* FDADD */
+			regs.fp[reg].fp += src;
+			break;
+		case 0x23: /* FMUL */
+		case 0x63: /* FSMUL */
+		case 0x67: /* FDMUL */
+			regs.fp[reg].fp *= src;
+			break;
+		case 0x24: /* FSGLDIV */
+			regs.fp[reg].fp /= src;
+			sgl = true;
+			break;
+		case 0x25: /* FREM */
+			{
+				fptype quot = fp_round_to_nearest(regs.fp[reg].fp / src);
+				regs.fp[reg].fp = regs.fp[reg].fp - quot * src;
+			}
+			break;
+		case 0x26: /* FSCALE */
+			if (src != 0) {
+#ifdef ldexp
+				regs.fp[reg] = ldexp (regs.fp[reg], (int) src);
+#else
+				regs.fp[reg].fp *= exp (*fp_ln_2 * (int) src);
+#endif
+			}
+			break;
+		case 0x27: /* FSGLMUL */
+			regs.fp[reg].fp *= src;
+			sgl = true;
+			break;
+		case 0x28: /* FSUB */
+		case 0x68: /* FSSUB */
+		case 0x6c: /* FDSUB */
+			regs.fp[reg].fp -= src;
+			break;
+		case 0x30: /* FSINCOS */
+		case 0x31:
+		case 0x32:
+		case 0x33:
+		case 0x34:
+		case 0x35:
+		case 0x36:
+		case 0x37:
+			regs.fp[extra & 7].fp = cos (src);
+			regs.fp[reg].fp = sin (src);
+			break;
+		case 0x38: /* FCMP */
+			{
+				fptype tmp = regs.fp[reg].fp - src;
+				regs.fpsr = 0;
+				MAKE_FPSR (&tmp);
+			}
+			return true;
+		case 0x3a: /* FTST */
+			regs.fpsr = 0;
+			MAKE_FPSR (&src);
+			return true;
+		default:
+			return false;
+	}
+	// round to float?
+	if (sgl || (extra & 0x44) == 0x40)
+		fround (reg);
+	MAKE_FPSR (®s.fp[reg].fp);
+	return true;
+}
+
+#ifdef WITH_SOFTFLOAT
+static bool arithmetic_softfloat(floatx80 *srcd, int reg, int extra)
+{
+	floatx80 fx = *srcd;
+	floatx80 f = regs.fp[reg].fpx;
+	int float_rounding_mode;
+	bool sgl = false;
+	Bit64u q;
+
+	// SNAN -> QNAN if SNAN interrupt is not enabled
+	if (floatx80_is_signaling_nan(fx) && !(regs.fpcr & 0x4000)) {
+		fx.fraction |= 0x40000000;
+	}
+
+	switch (extra & 0x7f)
+	{
+		case 0x00: /* FMOVE */
+		case 0x40:
+		case 0x44:
+			regs.fp[reg].fpx = fx;	
+			break;
+		case 0x01: /* FINT */
+			regs.fp[reg].fpx = floatx80_round_to_int(fx, fxstatus);
+			break;
+		case 0x03: /* FINTRZ */
+			float_rounding_mode = fxstatus.float_rounding_mode;
+			fxstatus.float_rounding_mode = float_round_to_zero;
+			regs.fp[reg].fpx = floatx80_round_to_int(fx, fxstatus);
+			float_rounding_mode = fxstatus.float_rounding_mode;
+			break;
+		case 0x04: /* FSQRT */
+		case 0x41: /* FSSQRT */
+		case 0x45: /* FDSQRT */
+			regs.fp[reg].fpx = floatx80_sqrt(fx, fxstatus);
+			break;
+		case 0x18: /* FABS */
+		case 0x58: /* FSABS */
+		case 0x5c: /* FDABS */
+			regs.fp[reg].fpx = floatx80_abs(fx);
+			break;
+		case 0x1a: /* FNEG */
+		case 0x5a: /* FSNEG */
+		case 0x5e: /* FDNEG */
+			// same here..
+			regs.fp[reg].fpx = floatx80_chs(fx);
+			break;
+		case 0x20: /* FDIV */
+		case 0x60: /* FSDIV */
+		case 0x64: /* FDDIV */
+			regs.fp[reg].fpx = floatx80_div(f, fx, fxstatus);
+			break;
+		case 0x22: /* FADD */
+		case 0x62: /* FSADD */
+		case 0x66: /* FDADD */
+			regs.fp[reg].fpx = floatx80_add(f, fx, fxstatus);
+			break;
+		case 0x23: /* FMUL */
+		case 0x63: /* FSMUL */
+		case 0x67: /* FDMUL */
+			regs.fp[reg].fpx = floatx80_mul(f, fx, fxstatus);
+			break;
+		case 0x24: /* FSGLDIV */
+			regs.fp[reg].fpx = floatx80_div(f, fx, fxstatus);
+			sgl = true;
+			break;
+		case 0x25: /* FREM */
+			floatx80_ieee754_remainder(f, fx, regs.fp[reg].fpx, q, fxstatus);
+			break;
+		case 0x27: /* FSGLMUL */
+			regs.fp[reg].fpx = floatx80_mul(f, fx, fxstatus);
+			sgl = true;
+			break;
+		case 0x28: /* FSUB */
+		case 0x68: /* FSSUB */
+		case 0x6c: /* FDSUB */
+			regs.fp[reg].fpx = floatx80_sub(f, fx, fxstatus);
+			break;
+		case 0x38: /* FCMP */
+			f = floatx80_sub(f, fx, fxstatus);
+			regs.fpsr = 0;
+			MAKE_FPSR_SOFTFLOAT(f);
+			return true;
+		case 0x3a: /* FTST */
+			regs.fpsr = 0;
+			MAKE_FPSR_SOFTFLOAT(f);
+			return true;
+
+		case 0x1d: /* FCOS */
+			fcos(f, fxstatus);
+			regs.fp[reg].fpx = f;
+			break;
+		case 0x0e: /* FSIN */
+			fsin(f, fxstatus);
+			regs.fp[reg].fpx = f;
+			break;
+		case 0x0f: /* FTAN */
+			ftan(f, fxstatus);
+			regs.fp[reg].fpx = f;
+			break;
+		case 0x30: /* FSINCOS */
+		case 0x31: /* FSINCOS */
+		case 0x32: /* FSINCOS */
+		case 0x33: /* FSINCOS */
+		case 0x34: /* FSINCOS */
+		case 0x35: /* FSINCOS */
+		case 0x36: /* FSINCOS */
+		case 0x37: /* FSINCOS */
+			fsincos(f, ®s.fp[extra & 7].fpx, ®s.fp[reg].fpx, fxstatus);
+			break;
+
+			// some of following are supported by softfloat, later..
+		case 0x06: /* FLOGNP1 */
+		case 0x08: /* FETOXM1 */
+		case 0x09: /* FTANH */
+		case 0x0a: /* FATAN */
+		case 0x0c: /* FASIN */
+		case 0x0d: /* FATANH */
+		case 0x10: /* FETOX */
+		case 0x11: /* FTWOTOX */
+		case 0x12: /* FTENTOX */
+		case 0x14: /* FLOGN */
+		case 0x15: /* FLOG10 */
+		case 0x16: /* FLOG2 */
+		case 0x19: /* FCOSH */
+		case 0x1c: /* FACOS */
+		case 0x1e: /* FGETEXP */
+		case 0x1f: /* FGETMAN */
+			{
+				// This is horribly ineffective..
+				fptype fp;
+				uae_u32 out[3];
+				// convert softfloat to raw words
+				softfloat_get(&fx, out);
+				// convert to double/long double
+				to_exten_x(&fp, out[0], out[1], out[2]);
+				// emulate instruction using normal fpu code
+				if (!arithmetic_fp(fp, reg, extra))
+					return false;
+				// convert back to raw
+				from_exten_x(regs.fp[reg].fp, &out[0], &out[1], &out[2]);
+				// convert to softfloat internal format
+				softfloat_set(®s.fp[reg].fpx, out);
+				MAKE_FPSR_SOFTFLOAT(regs.fp[reg].fpx);
+			}
+			break;
+	}
+	return true;
+}
+#endif
+
+static void fpuop_arithmetic2 (uae_u32 opcode, uae_u16 extra)
+{
+	int reg = -1;
+	int v;
+	fpdata srcd;
+	uaecptr pc = m68k_getpc () - 4;
+	uaecptr ad = 0;
+
+#if DEBUG_FPP
+	if (!isinrom ())
+		write_log (_T("FPP %04x %04x at %08x\n"), opcode & 0xffff, extra, pc);
+#endif
+	if (fault_if_no_6888x (opcode, extra, pc))
+		return;
+
+	switch ((extra >> 13) & 0x7)
+	{
+		case 3:
+			if (put_fp_value (®s.fp[(extra >> 7) & 7], opcode, extra, pc) == 0)
+				fpu_noinst (opcode, pc);
+			return;
+
+		case 4:
+		case 5:
+			if ((opcode & 0x38) == 0) {
+				if (fault_if_no_fpu (opcode, extra, 0, pc))
+					return;
+				if (extra & 0x2000) {
+					if (extra & 0x1000)
+						m68k_dreg (regs, opcode & 7) = regs.fpcr & 0xffff;
+					if (extra & 0x0800)
+						m68k_dreg (regs, opcode & 7) = fpp_get_fpsr ();
+					if (extra & 0x0400)
+						m68k_dreg (regs, opcode & 7) = regs.fpiar;
+				} else {
+					if (extra & 0x1000) {
+						regs.fpcr = m68k_dreg (regs, opcode & 7);
+						native_set_fpucw (regs.fpcr);
+					}
+					if (extra & 0x0800)
+						set_fpsr (m68k_dreg (regs, opcode & 7));
+					if (extra & 0x0400)
+						regs.fpiar = m68k_dreg (regs, opcode & 7);
+				}
+			} else if ((opcode & 0x38) == 0x08) {
+				if (fault_if_no_fpu (opcode, extra, 0, pc))
+					return;
+				if (extra & 0x2000) {
+					if (extra & 0x1000)
+						m68k_areg (regs, opcode & 7) = regs.fpcr & 0xffff;
+					if (extra & 0x0800)
+						m68k_areg (regs, opcode & 7) = fpp_get_fpsr ();
+					if (extra & 0x0400)
+						m68k_areg (regs, opcode & 7) = regs.fpiar;
+				} else {
+					if (extra & 0x1000) {
+						regs.fpcr = m68k_areg (regs, opcode & 7);
+						native_set_fpucw (regs.fpcr);
+					}
+					if (extra & 0x0800)
+						set_fpsr (m68k_areg (regs, opcode & 7));
+					if (extra & 0x0400)
+						regs.fpiar = m68k_areg (regs, opcode & 7);
+				}
+			} else if ((opcode & 0x3f) == 0x3c) {
+				if (fault_if_no_fpu (opcode, extra, 0, pc))
+					return;
+				if ((extra & 0x2000) == 0) {
+					uae_u32 ext[3];
+					// 68060 FMOVEM.L #imm,more than 1 control register: unimplemented EA
+					uae_u16 bits = extra & (0x1000 | 0x0800 | 0x0400);
+					if (bits && bits != 0x1000 && bits != 0x0800 && bits != 0x400) {
+						if (fault_if_60 (opcode, extra, ad, pc, FPU_EXP_UNIMP_EA))
+							return;
+					}
+					// fetch first, use only after all data has been fetched
+					ext[0] = ext[1] = ext[2] = 0;
+					if (extra & 0x1000)
+						ext[0] = x_cp_next_ilong ();
+					if (extra & 0x0800)
+						ext[1] = x_cp_next_ilong ();
+					if (extra & 0x0400)
+						ext[2] = x_cp_next_ilong ();
+					if (extra & 0x1000) {
+						regs.fpcr = ext[0];
+						native_set_fpucw (regs.fpcr);
+					}
+					if (extra & 0x0800)
+						set_fpsr (ext[1]);
+					if (extra & 0x0400)
+						regs.fpiar = ext[2];
+				}
+			} else if (extra & 0x2000) {
+				/* FMOVEM FPP->memory */
+				uae_u32 ad;
+				int incr = 0;
+
+				if (get_fp_ad (opcode, &ad) == 0) {
+					fpu_noinst (opcode, pc);
+					return;
+				}
+				if (fault_if_no_fpu (opcode, extra, ad, pc))
+					return;
+
+				if ((opcode & 0x38) == 0x20) {
+					if (extra & 0x1000)
+						incr += 4;
+					if (extra & 0x0800)
+						incr += 4;
+					if (extra & 0x0400)
+						incr += 4;
+				}
+				ad -= incr;
+				if (extra & 0x1000) {
+					x_cp_put_long (ad, regs.fpcr & 0xffff);
+					ad += 4;
+				}
+				if (extra & 0x0800) {
+					x_cp_put_long (ad, fpp_get_fpsr ());
+					ad += 4;
+				}
+				if (extra & 0x0400) {
+					x_cp_put_long (ad, regs.fpiar);
+					ad += 4;
+				}
+				ad -= incr;
+				if ((opcode & 0x38) == 0x18)
+					m68k_areg (regs, opcode & 7) = ad;
+				if ((opcode & 0x38) == 0x20)
+					m68k_areg (regs, opcode & 7) = ad;
+			} else {
+				/* FMOVEM memory->FPP */
+				uae_u32 ad;
+				int incr = 0;
+
+				if (get_fp_ad (opcode, &ad) == 0) {
+					fpu_noinst (opcode, pc);
+					return;
+				}
+				if (fault_if_no_fpu (opcode, extra, ad, pc))
+					return;
+
+				if((opcode & 0x38) == 0x20) {
+					if (extra & 0x1000)
+						incr += 4;
+					if (extra & 0x0800)
+						incr += 4;
+					if (extra & 0x0400)
+						incr += 4;
+					ad = ad - incr;
+				}
+				if (extra & 0x1000) {
+					regs.fpcr = x_cp_get_long (ad);
+					native_set_fpucw (regs.fpcr);
+					ad += 4;
+				}
+				if (extra & 0x0800) {
+					set_fpsr (x_cp_get_long (ad));
+					ad += 4;
+				}
+				if (extra & 0x0400) {
+					regs.fpiar = x_cp_get_long (ad);
+					ad += 4;
+				}
+				if ((opcode & 0x38) == 0x18)
+					m68k_areg (regs, opcode & 7) = ad;
+				if ((opcode & 0x38) == 0x20)
+					m68k_areg (regs, opcode & 7) = ad - incr;
+			}
+			return;
+
+		case 6:
+		case 7:
+			{
+				uae_u32 ad, list = 0;
+				int incr = 1;
+				int regdir = 1;
+				if (get_fp_ad (opcode, &ad) == 0) {
+					fpu_noinst (opcode, pc);
+					return;
+				}
+				if (fault_if_no_fpu (opcode, extra, ad, pc))
+					return;
+				switch ((extra >> 11) & 3)
+				{
+					case 0:	/* static pred */
+						list = extra & 0xff;
+						regdir = -1;
+						break;
+					case 1:	/* dynamic pred */
+						if (fault_if_60 (opcode, extra, ad, pc, FPU_EXP_UNIMP_EA))
+							return;
+						list = m68k_dreg (regs, (extra >> 4) & 3) & 0xff;
+						regdir = -1;
+						break;
+					case 2:	/* static postinc */
+						list = extra & 0xff;
+						break;
+					case 3:	/* dynamic postinc */
+						if (fault_if_60 (opcode, extra, ad, pc, FPU_EXP_UNIMP_EA))
+							return;
+						list = m68k_dreg (regs, (extra >> 4) & 3) & 0xff;
+						break;
+				}
+				if ((opcode & 0x38) == 0x20) // -(an)
+					incr = -1;
+				if (extra & 0x2000) {
+					/* FMOVEM FPP->memory */
+					ad = fmovem2mem (ad, list, incr, regdir);
+				} else {
+					/* FMOVEM memory->FPP */
+					ad = fmovem2fpp (ad, list, incr, regdir);
+				}
+				if ((opcode & 0x38) == 0x18 || (opcode & 0x38) == 0x20)
+					m68k_areg (regs, opcode & 7) = ad;
+			}
+			return;
+
+		case 0:
+		case 2: /* Extremely common */
+			regs.fpiar = pc;
+			reg = (extra >> 7) & 7;
+			if ((extra & 0xfc00) == 0x5c00) {
+				if (fault_if_no_fpu (opcode, extra, 0, pc))
+					return;
+				if (fault_if_unimplemented_680x0 (opcode, extra, ad, pc, &srcd, reg))
+					return;
+				CLEAR_STATUS ();
+				if (!fpu_get_constant(®s.fp[reg], extra)) {
+					fpu_noinst(opcode, pc);
+					return;
+				}
+				MAKE_FPSR (®s.fp[reg].fp);
+				return;
+			}
+
+			// 6888x does not have special exceptions, check immediately
+			if (fault_if_unimplemented_6888x (opcode, extra, pc))
+				return;
+
+			v = get_fp_value (opcode, extra, &srcd, pc, &ad);
+			if (v <= 0) {
+				if (v == 0)
+					fpu_noinst (opcode, pc);
+				return;
+			}
+
+			// get_fp_value() checked this, but only if EA was nonzero (non-register)
+			if (fault_if_unimplemented_680x0 (opcode, extra, ad, pc, &srcd, reg))
+				return;
+
+			regs.fpiar =  pc;
+
+			CLEAR_STATUS ();
+#ifdef WITH_SOFTFLOAT
+			if (currprefs.fpu_softfloat)
+				v = arithmetic_softfloat(&srcd.fpx, reg, extra);
+			else
+#endif
+				v = arithmetic_fp(srcd.fp, reg, extra);
+			if (!v)
+				fpu_noinst (opcode, pc);
+			return;
+		default:
+		break;
+	}
+	fpu_noinst (opcode, pc);
+}
+
+void fpuop_arithmetic (uae_u32 opcode, uae_u16 extra)
+{
+	regs.fpu_state = 1;
+	regs.fp_exception = false;
+	fpu_mmu_fixup = false;
+	fpuop_arithmetic2 (opcode, extra);
+	if (fpu_mmu_fixup) {
+		mmufixup[0].reg = -1;
+	}
+#ifdef WITH_SOFTFLOAT
+	if (currprefs.fpu_softfloat) {
+		// Any exception status bit and matching exception enable bits set?
+		if ((regs.fpcr >> 8) & (regs.fpsr >> 8)) {
+			uae_u32 mask = regs.fpcr >> 8;
+			int vector = 0;
+			for (int i = 7; i >= 0; i--) {
+				if (mask & (1 << i)) {
+					if (i > 0)
+						i--;
+					vector = i + 48;
+					break;
+				}
+			}
+			// logging only so far
+			write_log (_T("FPU exception: %08x %d!\n"), regs.fpsr, vector);
+		}
+	}
+#endif
+}
+
+void fpu_reset (void)
+{
+	regs.fpcr = regs.fpsr = regs.fpiar = 0;
+	regs.fpu_exp_state = 0;
+	fpset (®s.fp_result, 1);
+	native_set_fpucw (regs.fpcr);
+	fpux_restore (NULL);
+
+#ifdef WITH_SOFTFLOAT
+	fxsizes[0] = int32_to_floatx80(-128);
+	fxsizes[1] = int32_to_floatx80(127);
+	fxsizes[2] = int32_to_floatx80(-32768);
+	fxsizes[3] = int32_to_floatx80(32767);
+	fxsizes[4] = int32_to_floatx80(-2147483648);
+	fxsizes[5] = int32_to_floatx80(2147483647);
+	fxzero = int32_to_floatx80(0);
+	fx_1e0 = int32_to_floatx80(1);
+	fx_1e1 = int32_to_floatx80(10);
+	fx_1e2 = int32_to_floatx80(100);
+	fx_1e4 = int32_to_floatx80(10000);
+	fx_1e8 = int32_to_floatx80(100000000);
+#endif
+}
+
+uae_u8 *restore_fpu (uae_u8 *src)
+{
+	uae_u32 w1, w2, w3;
+	int i;
+	uae_u32 flags;
+
+	changed_prefs.fpu_model = currprefs.fpu_model = restore_u32 ();
+	flags = restore_u32 ();
+	for (i = 0; i < 8; i++) {
+		w1 = restore_u16 () << 16;
+		w2 = restore_u32 ();
+		w3 = restore_u32 ();
+		to_exten (®s.fp[i], w1, w2, w3);
+	}
+	regs.fpcr = restore_u32 ();
+	native_set_fpucw (regs.fpcr);
+	regs.fpsr = restore_u32 ();
+	regs.fpiar = restore_u32 ();
+	if (flags & 0x80000000) {
+		restore_u32 ();
+		restore_u32 ();
+	}
+	if (flags & 0x40000000) {
+		w1 = restore_u16() << 16;
+		w2 = restore_u32();
+		w3 = restore_u32();
+		to_exten(®s.exp_src1, w1, w2, w3);
+		w1 = restore_u16() << 16;
+		w2 = restore_u32();
+		w3 = restore_u32();
+		to_exten(®s.exp_src2, w1, w2, w3);
+		regs.exp_pack[0] = restore_u32();
+		regs.exp_pack[1] = restore_u32();
+		regs.exp_pack[2] = restore_u32();
+		regs.exp_opcode = restore_u16();
+		regs.exp_extra = restore_u16();
+		regs.exp_type = restore_u16();
+	}
+	regs.fpu_state = (flags & 1) ? 0 : 1;
+	regs.fpu_exp_state = (flags & 2) ? 1 : 0;
+	if (flags & 4)
+		regs.fpu_exp_state = 2;
+	write_log(_T("FPU: %d\n"), currprefs.fpu_model);
+	return src;
+}
+
+uae_u8 *save_fpu (int *len, uae_u8 *dstptr)
+{
+	uae_u32 w1, w2, w3;
+	uae_u8 *dstbak, *dst;
+	int i;
+
+	*len = 0;
+#ifndef WINUAE_FOR_HATARI
+        /* Under Hatari, we save all FPU variables, even if fpu_model==0 */
+	if (currprefs.fpu_model == 0)
+		return 0;
+#endif
+	if (dstptr)
+		dstbak = dst = dstptr;
+	else
+		dstbak = dst = xmalloc (uae_u8, 4+4+8*10+4+4+4+4+4+2*10+3*(4+2));
+	save_u32 (currprefs.fpu_model);
+	save_u32 (0x80000000 | 0x40000000 | (regs.fpu_state == 0 ? 1 : 0) | (regs.fpu_exp_state ? 2 : 0) | (regs.fpu_exp_state > 1 ? 4 : 0));
+	for (i = 0; i < 8; i++) {
+		from_exten (®s.fp[i], &w1, &w2, &w3);
+		save_u16 (w1 >> 16);
+		save_u32 (w2);
+		save_u32 (w3);
+	}
+	save_u32 (regs.fpcr);
+	save_u32 (regs.fpsr);
+	save_u32 (regs.fpiar);
+
+	save_u32 (-1);
+	save_u32 (0);
+
+	from_exten(®s.exp_src1, &w1, &w2, &w3);
+	save_u16(w1 >> 16);
+	save_u32(w2);
+	save_u32(w3);
+	from_exten(®s.exp_src2, &w1, &w2, &w3);
+	save_u16(w1 >> 16);
+	save_u32(w2);
+	save_u32(w3);
+	save_u32(regs.exp_pack[0]);
+	save_u32(regs.exp_pack[1]);
+	save_u32(regs.exp_pack[2]);
+	save_u16(regs.exp_opcode);
+	save_u16(regs.exp_extra);
+	save_u16(regs.exp_type);
+
+	*len = dst - dstbak;
+	return dstbak;
+}
+
+#ifdef _MSC_VER
+#pragma fenv_access(off)
+#endif
diff --git a/src/cpu/gencpu.c b/src/cpu/gencpu.c
new file mode 100644
index 0000000..a07e918
--- /dev/null
+++ b/src/cpu/gencpu.c
@@ -0,0 +1,6080 @@
+/*
+* UAE - The Un*x Amiga Emulator
+*
+* MC68000 emulation generator
+*
+* This is a fairly stupid program that generates a lot of case labels that
+* can be #included in a switch statement.
+* As an alternative, it can generate functions that handle specific
+* MC68000 instructions, plus a prototype header file and a function pointer
+* array to look up the function for an opcode.
+* Error checking is bad, an illegal table68k file will cause the program to
+* call abort().
+* The generated code is sometimes sub-optimal, an optimizing compiler should
+* take care of this.
+*
+* The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
+*
+* Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
+*/
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+#include 
+#include 
+
+#include "readcpu.h"
+
+char *ua (const char *s) {
+	        return strdup(s);
+}
+
+#define BOOL_TYPE "int"
+/* Define the minimal 680x0 where NV flags are not affected by xBCD instructions.  */
+#define xBCD_KEEPS_NV_FLAGS 4
+
+static FILE *headerfile;
+static FILE *stblfile;
+
+static int using_prefetch, using_indirect, using_mmu;
+static int using_prefetch_020, using_ce020;
+static int using_exception_3;
+static int using_bus_error;
+static int using_ce;
+static int using_tracer;
+static int using_waitstates;
+static int using_simple_cycles;
+static int cpu_level;
+static int count_read, count_write, count_cycles, count_ncycles;
+static int count_cycles_ce020;
+static int count_read_ea, count_write_ea, count_cycles_ea;
+static const char *mmu_postfix;
+static int memory_cycle_cnt;
+static int did_prefetch;
+static int ipl_fetched;
+
+static int optimized_flags;
+
+#ifdef WINUAE_FOR_HATARI
+long nCurInstrCycPos;				/* Hatari only : Stores where we have to patch in the current cycles value */
+#endif
+
+#define GF_APDI 1
+#define GF_AD8R 2
+#define GF_PC8R 4
+#define GF_AA 7
+#define GF_NOREFILL 8
+#define GF_PREFETCH 16
+#define GF_FC 32
+#define GF_MOVE 64
+#define GF_IR2IRC 128
+#define GF_LRMW 256
+#define GF_NOFAULTPC 512
+#define GF_RMW 1024
+#define GF_OPCE020 2048
+
+/* For the current opcode, the next lower level that will have different code.
+* Initialized to -1 for each opcode. If it remains unchanged, indicates we
+* are done with that opcode.  */
+static int next_cpu_level;
+
+static int *opcode_map;
+static int *opcode_next_clev;
+static int *opcode_last_postfix;
+static unsigned long *counts;
+static int generate_stbl;
+static int mmufixupcnt;
+static int mmufixupstate;
+static int disp020cnt;
+static bool candormw;
+static bool genastore_done;
+static char rmw_varname[100];
+
+#define GENA_GETV_NO_FETCH	0
+#define GENA_GETV_FETCH		1
+#define GENA_GETV_FETCH_ALIGN	2
+#define GENA_MOVEM_DO_INC	0
+#define GENA_MOVEM_NO_INC	1
+#define GENA_MOVEM_MOVE16	2
+
+static const char *srcl, *dstl;
+static const char *srcw, *dstw;
+static const char *srcb, *dstb;
+static const char *srcblrmw, *srcwlrmw, *srcllrmw;
+static const char *dstblrmw, *dstwlrmw, *dstllrmw;
+static const char *srcbrmw, *srcwrmw, *srclrmw;
+static const char *dstbrmw, *dstwrmw, *dstlrmw;
+static const char *prefetch_long, *prefetch_word;
+static const char *srcli, *srcwi, *srcbi, *nextl, *nextw;
+static const char *srcld, *dstld;
+static const char *srcwd, *dstwd;
+static const char *do_cycles, *disp000, *disp020, *getpc;
+
+#define fetchmode_fea 1
+#define fetchmode_cea 2
+#define fetchmode_fiea 3
+#define fetchmode_ciea 4
+#define fetchmode_jea 5
+
+NORETURN static void term (void)
+{
+	printf("Abort!\n");
+	abort ();
+}
+NORETURN static void term_err (const char *err)
+{
+	printf ("%s\n", err);
+	term ();
+}
+
+static void read_counts (void)
+{
+	FILE *file;
+	unsigned int opcode, count, total;
+	char name[20];
+	int nr = 0;
+	memset (counts, 0, 65536 * sizeof *counts);
+
+	count = 0;
+	file = fopen ("frequent.68k", "r");
+	if (file) {
+		if (fscanf (file, "Total: %u\n", &total) == 0) {
+			abort ();
+		}
+		while (fscanf (file, "%x: %u %s\n", &opcode, &count, name) == 3) {
+			opcode_next_clev[nr] = 5;
+			opcode_last_postfix[nr] = -1;
+			opcode_map[nr++] = opcode;
+			counts[opcode] = count;
+		}
+		fclose (file);
+	}
+	if (nr == nr_cpuop_funcs)
+		return;
+	for (opcode = 0; opcode < 0x10000; opcode++) {
+		if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
+			&& counts[opcode] == 0)
+		{
+			opcode_next_clev[nr] = 5;
+			opcode_last_postfix[nr] = -1;
+			opcode_map[nr++] = opcode;
+			counts[opcode] = count;
+		}
+	}
+	if (nr != nr_cpuop_funcs)
+		term ();
+}
+
+static char endlabelstr[80];
+static int endlabelno = 0;
+static int need_endlabel;
+static int genamode_cnt, genamode8r_offset[2];;
+
+static int n_braces, limit_braces;
+static int m68k_pc_offset, m68k_pc_offset_old;
+static int m68k_pc_total;
+static int branch_inst;
+static int insn_n_cycles, insn_n_cycles020;
+static int ir2irc;
+
+static int tail_ce020, total_ce020, head_in_ea_ce020;
+static bool head_ce020_cycs_done, tail_ce020_done;
+static int subhead_ce020;
+static struct instr *curi_ce020;
+static bool no_prefetch_ce020;
+static bool got_ea_ce020;
+
+static void fpulimit (void)
+{
+	if (limit_braces)
+		return;
+	printf ("\n#ifdef FPUEMU\n");
+	limit_braces = n_braces;
+	n_braces = 0;
+}
+#ifndef WINUAE_FOR_HATARI
+static void cpulimit (void)
+{
+	printf ("#ifndef CPUEMU_68000_ONLY\n");
+}
+#endif
+
+static int s_count_read, s_count_write, s_count_cycles, s_count_ncycles;
+
+static void push_ins_cnt(void)
+{
+	s_count_read = count_read;
+	s_count_write = count_write;
+	s_count_cycles = count_cycles;
+	s_count_ncycles = count_ncycles;
+}
+static void pop_ins_cnt(void)
+{
+	count_read = s_count_read;
+	count_write = s_count_write;
+	count_cycles = s_count_cycles;
+	count_ncycles = s_count_ncycles;
+}
+
+static bool isce020(void)
+{
+	if (!using_ce020)
+		return false;
+	if (using_ce020 >= 3)
+		return false;
+	return true;
+}
+static bool isprefetch020(void)
+{
+	if (!using_prefetch_020)
+		return false;
+	if (using_prefetch_020 >= 3)
+		return false;
+	return true;
+}
+
+static void addcycles_ce020_2 (int cycles, const char *s)
+{
+	if (!isce020())
+		return;
+	if (cycles > 0) {
+		if (s == NULL)
+			printf ("\t%s (%d);\n", do_cycles, cycles);
+		else
+			printf ("\t%s (%d); /* %s */\n", do_cycles, cycles, s);
+	}
+	count_cycles += cycles;
+	count_cycles_ce020 += cycles;
+}
+static void addcycles_ce020 (int cycles)
+{
+	addcycles_ce020_2 (cycles, NULL);
+}
+
+static void get_prefetch_020 (void)
+{
+	if (!isprefetch020() || no_prefetch_ce020)
+		return;
+	printf ("\tregs.irc = %s (%d);\n", prefetch_word, m68k_pc_offset);
+}
+static void get_prefetch_020_0 (void)
+{
+	if (!isprefetch020() || no_prefetch_ce020)
+		return;
+	printf ("\tregs.irc = %s (0);\n", prefetch_word);
+}
+
+static void get_prefetch_020_continue(void)
+{
+	if (!isprefetch020())
+		return;
+	if (using_ce020)
+		printf("\tcontinue_ce020_prefetch();\n");
+	else
+		printf ("\tcontinue_020_prefetch();\n");
+}
+
+static void returntail (bool iswrite)
+{
+	if (!isce020()) {
+		if (isprefetch020()) {
+			if (!tail_ce020_done) {
+				if (!did_prefetch)
+					get_prefetch_020 ();
+				did_prefetch = 1;
+				tail_ce020_done = true;
+			}
+		}
+		return;
+	}
+	if (!tail_ce020_done) {
+		total_ce020 -= 2;
+#if 0
+		if (iswrite) {
+			printf("\t/* C - %d = %d */\n", memory_cycle_cnt, total_ce020 - memory_cycle_cnt);
+			total_ce020 -= memory_cycle_cnt;
+		} else {
+			printf("\t/* C = %d */\n", total_ce020);
+		}
+#endif
+		if (0 && total_ce020 <= 0) {
+			printf ("\t/* C was zero */\n");
+			total_ce020 = 1;
+		}
+		if (!did_prefetch)
+			get_prefetch_020 ();
+		if (total_ce020 > 0)
+			addcycles_ce020 (total_ce020);
+
+		//printf ("\tregs.irc = %s;\n", prefetch_word);
+		if (0 && total_ce020 >= 2) {
+			printf ("\top_cycles = get_cycles () - op_cycles;\n");
+			printf ("\top_cycles /= cpucycleunit;\n");
+			printf ("\tif (op_cycles < %d) {\n", total_ce020);
+			printf ("\t\tdo_cycles_ce020 ((%d) - op_cycles);\n", total_ce020);
+			printf ("\t}\n");
+		}
+#if 0
+		if (tail_ce020 > 0) {
+			printf ("\tregs.ce020_tail = %d * cpucycleunit;\n", tail_ce020);
+			printf ("\tregs.ce020_tail_cycles = get_cycles () + regs.ce020_tail;\n");
+		} else {
+			printf ("\tregs.ce020_tail = 0;\n");
+		}
+#endif
+		tail_ce020_done = true;
+	}
+}
+
+
+static void returncycles (const char *s, int cycles)
+{
+	if (using_ce || using_ce020) {
+#if 0
+		if (tail_ce020 == 0)
+			printf ("\tregs.ce020memcycles -= 2 * cpucycleunit; /* T=0 */ \n");
+		else if (tail_ce020 == 1)
+			printf ("\tregs.ce020memcycles -= 1 * cpucycleunit; /* T=1 */ \n");
+		else if (tail_ce020 == 2)
+			printf ("\tregs.ce020memcycles -= 0 * cpucycleunit; /* T=2 */\n");
+#endif
+		printf ("%sreturn;\n", s);
+		return;
+	}
+	if (using_simple_cycles)
+		printf ("%sreturn %d * CYCLE_UNIT / 2 + count_cycles;\n", s, cycles);
+	else
+		printf ("%sreturn %d * CYCLE_UNIT / 2;\n", s, cycles);
+}
+
+static void addcycles_ce020_4 (const char *name, int head, int tail, int cycles)
+{
+	if (!isce020())
+		return;
+	if (!head && !tail && !cycles)
+		return;
+	printf ("\t/* %s H:%d,T:%d,C:%d */\n", name, head, tail, cycles);
+}
+static void addcycles_ce020_5 (const char *name, int head, int tail, int cycles, int ophead)
+{
+	if (!isce020())
+		return;
+	if (!head && !tail && !cycles && !ophead) {
+		printf ("\t/* OP zero */\n");
+		return;
+	}
+	count_cycles += cycles;
+	if (!ophead) {
+		addcycles_ce020_4 (name, head, tail, cycles);
+	} else if (ophead > 0) {
+		printf ("\t/* %s H:%d-,T:%d,C:%d */\n", name, head, tail, cycles);
+	} else {
+		printf ("\t/* %s H:%d+,T:%d,C:%d */\n", name, head, tail, cycles);
+	}
+}
+
+static void addcycles000_nonces(const char *s, const char *sc)
+{
+	if (using_simple_cycles) {
+		printf("%scount_cycles += (%s) * CYCLE_UNIT / 2;\n", s, sc);
+		count_ncycles++;
+	}
+}
+static void addcycles000_nonce(const char *s, int c)
+{
+	if (using_simple_cycles) {
+		printf("%scount_cycles += %d * CYCLE_UNIT / 2;\n", s, c);
+		count_ncycles++;
+	}
+}
+
+static void addcycles000_onlyce (int cycles)
+{
+	if (using_ce) {
+		printf ("\t%s (%d);\n", do_cycles, cycles);
+	}
+}
+
+static void addcycles000 (int cycles)
+{
+	if (using_ce) {
+		printf ("\t%s (%d);\n", do_cycles, cycles);
+	}
+	count_cycles += cycles;
+}
+
+#ifndef WINUAE_FOR_HATARI
+static void addcycles000_2 (const char *s, int cycles)
+{
+	if (using_ce) {
+		printf ("%s%s (%d);\n", s, do_cycles, cycles);
+	}
+	count_cycles += cycles;
+}
+#endif
+
+
+static void addcycles000_3 (const char *s)
+{
+	if (using_ce) {
+		printf ("%sif (cycles > 0) %s (cycles);\n", s, do_cycles);
+	}
+	count_ncycles++;
+}
+
+static int isreg (amodes mode)
+{
+	if (mode == Dreg || mode == Areg)
+		return 1;
+	return 0;
+}
+
+static void start_brace (void)
+{
+	n_braces++;
+	printf ("{");
+}
+
+static void close_brace (void)
+{
+	assert (n_braces > 0);
+	n_braces--;
+	printf ("}");
+}
+
+static void finish_braces (void)
+{
+	while (n_braces > 0)
+		close_brace ();
+}
+
+static void pop_braces (int to)
+{
+	while (n_braces > to)
+		close_brace ();
+}
+
+static int bit_size (int size)
+{
+	switch (size) {
+	case sz_byte: return 8;
+	case sz_word: return 16;
+	case sz_long: return 32;
+	default: term ();
+	}
+	return 0;
+}
+
+static const char *bit_mask (int size)
+{
+	switch (size) {
+	case sz_byte: return "0xff";
+	case sz_word: return "0xffff";
+	case sz_long: return "0xffffffff";
+	default: term ();
+	}
+	return 0;
+}
+
+static void add_mmu040_movem (int movem)
+{
+	if (movem != 3)
+		return;
+	printf ("\tif (mmu040_movem) {\n");
+	printf ("\t\tsrca = mmu040_movem_ea;\n");
+	printf ("\t} else\n");
+	start_brace ();
+}
+
+static void gen_nextilong2 (const char *type, const char *name, int flags, int movem)
+{
+	int r = m68k_pc_offset;
+	m68k_pc_offset += 4;
+
+	printf ("\t%s %s;\n", type, name);
+	add_mmu040_movem (movem);
+	if (using_ce020) {
+		if (flags & GF_NOREFILL)
+			//**printf("\t%s = %s (%d);\n", name, prefetch_long_buffer, r);
+			printf("\t%s = %s (%d);\n", name, prefetch_long, r);
+		else
+			printf("\t%s = %s (%d);\n", name, prefetch_long, r);
+		count_read += 2;
+	} else if (using_ce) {
+		/* we must do this because execution order of (something | something2) is not defined */
+		if (flags & GF_NOREFILL) {
+			printf ("\t%s = %s (%d) << 16;\n", name, prefetch_word, r + 2);
+			count_read++;
+			printf ("\t%s |= regs.irc;\n", name);
+		} else {
+			printf ("\t%s = %s (%d) << 16;\n", name, prefetch_word, r + 2);
+			count_read++;
+			printf ("\t%s |= %s (%d);\n", name, prefetch_word, r + 4);
+			count_read++;
+		}
+	} else {
+		if (using_prefetch) {
+			if (flags & GF_NOREFILL) {
+				printf ("\t%s = %s (%d) << 16;\n", name, prefetch_word, r + 2);
+				count_read++;
+				printf ("\t%s |= regs.irc;\n", name);
+				insn_n_cycles += 4;
+			} else {
+				printf ("\t%s = %s (%d) << 16;\n", name, prefetch_word, r + 2);
+				count_read += 2;
+				printf ("\t%s |= %s (%d);\n", name, prefetch_word, r + 4);
+				insn_n_cycles += 8;
+			}
+		} else {
+			insn_n_cycles += 8;
+			printf ("\t%s = %s (%d);\n", name, prefetch_long, r);
+		}
+	}
+}
+static void gen_nextilong (const char *type, const char *name, int flags)
+{
+	gen_nextilong2 (type, name, flags, 0);
+}
+
+static const char *gen_nextiword (int flags)
+{
+	static char buffer[80];
+	int r = m68k_pc_offset;
+	m68k_pc_offset += 2;
+
+	if (using_ce020) {
+		if (flags & GF_NOREFILL)
+			//**sprintf(buffer, "%s (%d)", prefetch_word_buffer, r);
+			sprintf(buffer, "%s (%d)", prefetch_word, r);
+		else
+			sprintf(buffer, "%s (%d)", prefetch_word, r);
+		count_read++;
+	} else if (using_ce) {
+		if (flags & GF_NOREFILL) {
+			strcpy (buffer, "regs.irc");
+		} else {
+			sprintf (buffer, "%s (%d)", prefetch_word, r + 2);
+			count_read++;
+		}
+	} else {
+		if (using_prefetch) {
+			if (flags & GF_NOREFILL) {
+				strcpy (buffer, "regs.irc");
+			} else {
+				sprintf (buffer, "%s (%d)", prefetch_word, r + 2);
+				count_read++;
+				insn_n_cycles += 4;
+			}
+		} else {
+			sprintf (buffer, "%s (%d)", prefetch_word, r);
+			insn_n_cycles += 4;
+		}
+	}
+	return buffer;
+}
+
+static const char *gen_nextibyte (int flags)
+{
+	static char buffer[80];
+	int r = m68k_pc_offset;
+	m68k_pc_offset += 2;
+
+	if (using_ce020 || using_prefetch_020) {
+		if (flags & GF_NOREFILL)
+			//**sprintf(buffer, "(uae_u8)%s (%d)", prefetch_word_buffer, r);
+			sprintf(buffer, "(uae_u8)%s (%d)", prefetch_word, r);
+		else
+			sprintf(buffer, "(uae_u8)%s (%d)", prefetch_word, r);
+		count_read++;
+	} else if (using_ce) {
+		if (flags & GF_NOREFILL) {
+			strcpy (buffer, "(uae_u8)regs.irc");
+		} else {
+			sprintf (buffer, "(uae_u8)%s (%d)", prefetch_word, r + 2);
+			count_read++;
+		}
+	} else {
+		insn_n_cycles += 4;
+		if (using_prefetch) {
+			if (flags & GF_NOREFILL) {
+				strcpy (buffer, "(uae_u8)regs.irc");
+			} else {
+				sprintf (buffer, "(uae_u8)%s (%d)", prefetch_word, r + 2);
+				insn_n_cycles += 4;
+				count_read++;
+			}
+		} else {
+			sprintf (buffer, "%s (%d)", srcbi, r);
+			insn_n_cycles += 4;
+		}
+	}
+	return buffer;
+}
+
+static void makefromsr (void)
+{
+	printf ("\tMakeFromSR();\n");
+	if (using_ce || isce020())
+		printf ("\tregs.ipl_pin = intlev ();\n");
+}
+
+static void check_ipl (void)
+{
+	if (ipl_fetched)
+		return;
+	if (using_ce || isce020())
+		printf ("\tipl_fetch ();\n");
+	ipl_fetched = 1;
+}
+
+static void single_check_ipl(void)
+{
+	check_ipl();
+	ipl_fetched = 2;
+
+}
+/* this is not true, it seems to be microcode controller */
+
+/* Apparently interrupt state is sampled
+ * during any memory access. Because we don't
+ * know if there are future memory accesses,
+ * we'll check each memory access after prefetch
+ * and recheck interrupt state again.
+ */
+static void check_ipl_again (void)
+{
+	if (ipl_fetched != 1)
+		return;
+	if (using_ce)
+		printf ("\tipl_fetch ();\n");
+}
+
+static void irc2ir_2 (bool dozero)
+{
+	if (!using_prefetch)
+		return;
+	if (ir2irc)
+		return;
+	ir2irc = 1;
+	printf ("\tregs.ir = regs.irc;\n");
+	if (dozero)
+		printf ("\tregs.irc = 0;\n");
+	check_ipl ();
+}
+static void irc2ir (void)
+{
+	irc2ir_2 (false);
+}
+
+static void fill_prefetch_2 (void)
+{
+	if (!using_prefetch)
+		return;
+	printf ("\t%s (%d);\n", prefetch_word, m68k_pc_offset + 2);
+	did_prefetch = 1;
+	ir2irc = 0;
+	count_read++;
+	insn_n_cycles += 4;
+}
+
+static void fill_prefetch_1 (int o)
+{
+	if (using_prefetch) {
+		printf ("\t%s (%d);\n", prefetch_word, o);
+		did_prefetch = 1;
+		ir2irc = 0;
+		count_read++;
+		insn_n_cycles += 4;
+	}
+}
+
+static void fill_prefetch_full (void)
+{
+	if (using_prefetch) {
+		fill_prefetch_1 (0);
+		irc2ir ();
+		fill_prefetch_1 (2);
+	} else if (isprefetch020()) {
+		did_prefetch = 2;
+		total_ce020 -= 4;
+		returntail (false);
+		if (cpu_level >= 3)
+			printf ("\tfill_prefetch_030 ();\n");
+		else if (cpu_level == 2)
+			printf ("\tfill_prefetch_020 ();\n");
+	}
+}
+
+// 68000 and 68010 only
+static void fill_prefetch_full_000 (void)
+{
+	if (!using_prefetch)
+		return;
+	fill_prefetch_full ();
+}
+
+// 68020+
+static void fill_prefetch_full_020 (void)
+{
+	if (!using_prefetch_020)
+		return;
+	fill_prefetch_full ();
+}
+
+static void fill_prefetch_0 (void)
+{
+	if (!using_prefetch)
+		return;
+	printf ("\t%s (0);\n", prefetch_word);
+	did_prefetch = 1;
+	ir2irc = 0;
+	count_read++;
+	insn_n_cycles += 4;
+}
+
+#ifndef WINUAE_FOR_HATARI
+static void dummy_prefetch (void)
+{
+	int o = m68k_pc_offset + 2;
+	if (!using_prefetch)
+		return;
+	printf ("\t%s (%d);\n", srcwi, o);
+	count_read++;
+	insn_n_cycles += 4;
+}
+#endif
+
+static void fill_prefetch_next_1 (void)
+{
+	irc2ir ();
+	fill_prefetch_1 (m68k_pc_offset + 2);
+}
+
+static void fill_prefetch_next (void)
+{
+	if (using_prefetch) {
+		fill_prefetch_next_1 ();
+	}
+//	if (using_prefetch_020) {
+//		printf ("\t%s (%d);\n", prefetch_word, m68k_pc_offset);
+//		did_prefetch = 1;
+//	}
+}
+
+static void fill_prefetch_finish (void)
+{
+	if (did_prefetch)
+		return;
+	if (using_prefetch) {
+		fill_prefetch_1 (m68k_pc_offset);
+	}
+	if (using_prefetch_020) {
+		did_prefetch = 1;
+	}
+}
+
+static void setpc (const char *format, ...)
+{
+	va_list parms;
+	char buffer[1000];
+
+	va_start (parms, format);
+	_vsnprintf (buffer, 1000 - 1, format, parms);
+	va_end (parms);
+
+	if (using_mmu || using_prefetch || using_prefetch_020)
+		printf ("\tm68k_setpci (%s);\n", buffer);
+	else
+		printf ("\tm68k_setpc (%s);\n", buffer);
+}
+
+static void incpc (const char *format, ...)
+{
+	va_list parms;
+	char buffer[1000];
+
+	va_start (parms, format);
+	_vsnprintf (buffer, 1000 - 1, format, parms);
+	va_end (parms);
+
+	if (using_mmu || using_prefetch || using_prefetch_020)
+		printf ("\tm68k_incpci (%s);\n", buffer);
+	else
+		printf ("\tm68k_incpc (%s);\n", buffer);
+}
+
+static void sync_m68k_pc (void)
+{
+	m68k_pc_offset_old = m68k_pc_offset;
+	if (m68k_pc_offset == 0)
+		return;
+	incpc ("%d", m68k_pc_offset);
+	m68k_pc_total += m68k_pc_offset;
+	m68k_pc_offset = 0;
+}
+
+static void clear_m68k_offset(void)
+{
+	m68k_pc_total += m68k_pc_offset;
+	m68k_pc_offset = 0;
+}
+
+static void sync_m68k_pc_noreset (void)
+{
+	sync_m68k_pc ();
+	m68k_pc_offset = m68k_pc_offset_old;
+}
+
+static void addmmufixup (const char *reg)
+{
+	if (!using_mmu)
+		return;
+	if (using_mmu == 68040 && (mmufixupstate || mmufixupcnt > 0))
+		return;
+	printf ("\tmmufixup[%d].reg = %s;\n", mmufixupcnt, reg);
+	printf ("\tmmufixup[%d].value = m68k_areg (regs, %s);\n", mmufixupcnt, reg);
+	mmufixupstate |= 1 << mmufixupcnt;
+	mmufixupcnt++;
+}
+
+static void clearmmufixup (int cnt)
+{
+	if (mmufixupstate & (1 << cnt)) {
+		printf ("\tmmufixup[%d].reg = -1;\n", cnt);
+		mmufixupstate &= ~(1 << cnt);
+	}
+}
+
+static void gen_set_fault_pc (void)
+{
+	if (using_mmu != 68040)
+		return;
+	sync_m68k_pc ();
+	printf ("\tregs.instruction_pc = %s;\n", getpc);
+	printf ("\tmmu_restart = false;\n");
+	m68k_pc_offset = 0;
+	clearmmufixup (0);
+}
+
+static void syncmovepc (int getv, int flags)
+{
+#if 0
+	if (!(flags & GF_MOVE))
+		return;
+	if (getv == 1) {
+		sync_m68k_pc ();
+		//fill_prefetch_next ();
+	}
+#endif
+}
+
+static void head_cycs (int h)
+{
+	if (head_ce020_cycs_done)
+		return;
+	if (h < 0)
+		return;
+	//printf ("\tdo_sync_tail (%d);\n", h);
+	//printf ("\tdo_head_cycles_ce020 (%d);\n", h);
+	head_ce020_cycs_done = true;
+	tail_ce020 = -1;
+}
+
+static void add_head_cycs (int h)
+{
+	if (!isce020())
+		return;
+	head_ce020_cycs_done = false;
+	head_cycs (h);
+}
+
+static void addopcycles_ce20 (int h, int t, int c, int subhead)
+{
+	head_cycs (h);
+
+	//c = 0;
+#if 0
+	if (tail_ce020 == 1)
+		printf ("\tregs.ce020memcycles -= 1 * cpucycleunit; /* T=1 */ \n");
+	else if (tail_ce020 == 2)
+		printf ("\tregs.ce020memcycles -= 2 * cpucycleunit; /* T=2 */\n");
+#endif
+	if (1 && !subhead && (h > 0 || t > 0 || c > 0) && got_ea_ce020) {
+		if (!did_prefetch) {
+			get_prefetch_020 ();
+			did_prefetch = 1;
+		}
+		if (1) {
+			if (h > 0) {
+				printf ("\tif (regs.ce020memcycles > %d * cpucycleunit)\n", h);
+				printf ("\t\tregs.ce020memcycles = %d * cpucycleunit;\n", h);
+			} else {
+				printf ("\tregs.ce020memcycles = 0;\n");
+			}
+		}
+	}
+
+#if 0
+	if (tail_ce020 >= 0 && h >= 0 && head_in_ea_ce020 == 0) {
+		int largest = tail_ce020 > h ? tail_ce020: h;
+		if (tail_ce020 != h) {
+			//printf ("\tdo_cycles_ce020 (%d - %d);\n", tail_ce020 > h ? tail_ce020 : h, tail_ce020 > h ? h : tail_ce020);
+			//printf ("\tdo_cycles_ce020 (%d - %d);\n", tail_ce020 > h ? tail_ce020 : h, tail_ce020 > h ? h : tail_ce020);
+			if (h) {
+				printf ("\tregs.ce020memcycles -= %d * cpucycleunit;\n", h);
+				printf ("\tif (regs.ce020memcycles < 0) {\n");
+				//printf ("\t\tx_do_cycles (-regs.ce020memcycles);\n");
+				printf ("\t\tregs.ce020memcycles = 0;\n");
+				printf ("\t}\n");
+			} else {
+				printf ("\tregs.ce020memcycles = 0;\n");
+			}
+			//printf ("\tregs.ce020memcycles = 0;\n");
+
+#if 0
+		if (tail_ce020)
+			printf ("\tregs.ce020_tail = get_cycles () - regs.ce020_tail;\n");
+		else
+			printf ("\tregs.ce020_tail = 0;\n");
+		printf ("\tif (regs.ce020_tail < %d * cpucycleunit)\n", largest);
+		printf ("\t\tx_do_cycles (%d * cpucycleunit - regs.ce020_tail);\n", largest);
+#endif
+		} else if (h) {
+			printf ("\t/* ea tail == op head (%d) */\n", h);
+
+			printf ("\tregs.ce020memcycles -= %d * cpucycleunit;\n", h);
+			printf ("\tif (regs.ce020memcycles < 0) {\n");
+			//printf ("\t\tx_do_cycles (-regs.ce020memcycles);\n");
+			printf ("\t\tregs.ce020memcycles = 0;\n");
+			printf ("\t}\n");
+		}
+	}
+#endif
+
+	if (h < 0)
+		h = 0;
+	
+	//c = 0;
+	
+	// c = internal cycles needed after head cycles and before tail cycles. Not total cycles.
+	addcycles_ce020_5 ("op", h, t, c - h - t, -subhead);
+	//printf ("\tregs.irc = get_word_ce020_prefetch (%d);\n", m68k_pc_offset);
+#if 0
+	if (c - h - t > 0) {
+		printf ("\t%s (%d);\n", do_cycles, c - h - t);
+		count_cycles_ce020 += c;
+		count_cycles += c;
+	}
+#endif
+	//printf ("\tregs.ce020_tail = 0;\n");
+	total_ce020 = c;
+	tail_ce020 = t;
+//	if (total_ce020 >= 2)
+//		printf ("\tint op_cycles = get_cycles ();\n");
+}
+
+static void addop_ce020 (struct instr *curi, int subhead)
+{
+	if (!isce020())
+		return;
+	int h = curi->head;
+	int t = curi->tail;
+	int c = curi->clocks;
+#if 0
+	if ((((curi->sduse & 2) && !isreg (curi->smode)) || (((curi->sduse >> 4) & 2) && !isreg (curi->dmode))) && using_waitstates) {
+		t += using_waitstates;
+		c += using_waitstates;
+	}
+#endif
+	addopcycles_ce20 (h, t, c, -subhead);
+}
+
+static void addcycles_ea_ce020_5 (const char *ea, int h, int t, int c, int oph)
+{
+	head_cycs (h + oph);
+
+//	if (!h && !h && !c && !oph)
+//		return;
+
+	c = c - h - t;
+
+	//c = 0;
+
+	if (!oph) {
+		printf ("\t/* ea H:%d,T:%d,C:%d %s */\n", h, t, c, ea);
+	} else {
+		if (oph && t)
+			term_err ("Both op head and tail can't be non-zero");
+		if (oph > 0) {
+			printf ("\t/* ea H:%d+%d=%d,T:%d,C:%d %s */\n", h, oph, h + oph, t, c, ea);
+			h += oph;
+		} else {
+			printf ("\t/* ea H:%d-%d=%d,T:%d,C:%d %s */\n", h, -oph, h + oph, t, c, ea);
+			h += oph;
+		}
+	}
+
+	if (h) {
+		printf ("\tif (regs.ce020memcycles > %d * cpucycleunit)\n", h);
+		printf ("\t\tregs.ce020memcycles = %d * cpucycleunit;\n", h);
+	} else {
+		printf ("\tregs.ce020memcycles = 0;\n");
+	}
+
+	if (1 && c > 0) {
+		printf ("\t%s (%d);\n", do_cycles, c);
+		count_cycles += c;
+	}
+	tail_ce020 = t;
+	head_in_ea_ce020 = oph;
+	got_ea_ce020 = true;
+//	if (t > 0)
+//		printf ("\tregs.ce020_tail = get_cycles () + %d * cpucycleunit;\n", t);
+}
+static void addcycles_ea_ce020_4 (const char *ea, int h, int t, int c)
+{
+	addcycles_ea_ce020_5 (ea, h, t, c, 0);
+}
+
+#define SETCE020(h2,t2,c2) { h = h2; t = t2; c = c2; }
+#define SETCE020H(h2,t2,c2) { h = h2; oph = curi ? curi->head : 0; t = t2; c = c2; }
+
+static int gence020cycles_fiea (struct instr *curi, wordsizes ssize, amodes dmode)
+{
+	bool l = ssize == sz_long;
+	int h = 0, t = 0, c = 0, oph = 0;
+	switch ((int)dmode)
+	{
+	case Dreg:
+	case Areg:
+		if (!l)
+			SETCE020H(2, 0, 2)
+		else
+			SETCE020H(4, 0, 4)
+		break;
+	case Aind: // (An)
+		if (!l)
+			SETCE020(1, 1, 3)
+		else
+			SETCE020(1, 0, 4)
+		break;
+	case Aipi: // (An)+
+		if (!l)
+			SETCE020(2, 1, 5)
+		else
+			SETCE020(4, 1, 7)
+		break;
+	case Apdi: // -(An)
+		if (!l)
+			SETCE020(2, 2, 4)
+		else
+			SETCE020(2, 0, 4)
+		break;
+	case Ad8r: // (d8,An,Xn)
+	case PC8r: // (d8,PC,Xn)
+		if (!l)
+			SETCE020(6, 2, 8)
+		else
+			SETCE020(8, 2, 10)
+		break;
+	case Ad16: // (d16,An)
+	case PC16: // (d16,PC)
+		if (!l)
+			SETCE020(2, 0, 4)
+		else
+			SETCE020(4, 0, 6)
+		break;
+	case absw:
+		if (!l)
+			SETCE020(4, 2, 6)
+		else
+			SETCE020(6, 2, 8)
+		break;
+	case absl:
+		if (!l)
+			SETCE020(3, 0, 6)
+		else
+			SETCE020(5, 0, 8)
+		break;
+	}
+	addcycles_ea_ce020_5 ("fiea", h, t, c, oph);
+	return oph;
+}
+
+
+static int gence020cycles_ciea (struct instr *curi, wordsizes ssize, amodes dmode)
+{
+	int h = 0, t = 0, c = 0, oph = 0;
+	bool l = ssize == sz_long;
+	switch ((int)dmode)
+	{
+	case Dreg:
+	case Areg:
+		if (!l)
+			SETCE020H(2, 0, 2)
+		else
+			SETCE020H(4, 0, 4)
+		break;
+	case Aind: // (An)
+		if (!l)
+			SETCE020H(2, 0, 2)
+		else
+			SETCE020H(4, 0, 4)
+		break;
+	case Aipi: // (An)+
+		if (!l)
+			SETCE020(2, 0, 4)
+		else
+			SETCE020(4, 0, 6)
+		break;
+	case Apdi: // -(An)
+		if (!l)
+			SETCE020H(2, 0, 2)
+		else
+			SETCE020H(4, 0, 4)
+		break;
+	case Ad8r: // (d8,An,Xn)
+	case PC8r: // (d8,PC,Xn)
+		if (!l)
+			SETCE020H(6, 0, 6)
+		else
+			SETCE020H(8, 0, 8)
+		break;
+	case Ad16: // (d16,An)
+	case PC16: // (d16,PC)
+		if (!l)
+			SETCE020H(4, 0, 4)
+		else
+			SETCE020H(6, 0, 6)
+		break;
+	case absw:
+		if (!l)
+			SETCE020H(4, 0, 4)
+		else
+			SETCE020H(6, 0, 6)
+		break;
+	case absl:
+		if (!l)
+			SETCE020H(6, 0, 6)
+		else
+			SETCE020H(8, 0, 8)
+		break;
+	}
+	addcycles_ea_ce020_5 ("ciea", h, t, c, oph);
+	return oph;
+}
+
+
+static int gence020cycles_fea (amodes mode)
+{
+	int h = 0, t = 0, c = 0, ws = 0;
+	switch ((int)mode)
+	{
+	case Dreg:
+	case Areg:
+		SETCE020(0, 0, 0)
+		break;
+	case Aind: // (An)
+		ws++;
+		SETCE020(1, 1, 3)
+		break;
+	case Aipi: // (An)+
+		ws++;
+		SETCE020(0, 1, 3)
+		break;
+	case Apdi: // -(An)
+		ws++;
+		SETCE020(2, 2, 4)
+		break;
+	case Ad8r: // (d8,An,Xn)
+	case PC8r: // (d8,PC,Xn)
+		ws++;
+		SETCE020(4, 2, 6)
+		break;
+	case Ad16: // (d16,An)
+	case PC16: // (d16,PC)
+		ws++;
+		SETCE020(2, 2, 4)
+		break;
+	case absw:
+		ws++;
+		SETCE020(2, 2, 4)
+		break;
+	case absl:
+		ws++;
+		SETCE020(1, 0, 4)
+		break;
+	}
+#if 0
+	if (using_waitstates) {
+		t += ws * using_waitstates;
+		c += ws * using_waitstates;
+	}
+#endif
+	addcycles_ea_ce020_4 ("fea", h, t, c);
+	return 0;
+}
+
+static int gence020cycles_cea (struct instr *curi, amodes mode)
+{
+	int h = 0, t = 0, c = 0, oph = 0;
+	switch ((int)mode)
+	{
+	case Dreg:
+	case Areg:
+		SETCE020(0, 0, 0);
+		break;
+	case Aind: // (An)
+		SETCE020H(2 + h, 0, 2);
+		break;
+	case Aipi: // (An)+
+		SETCE020(0, 0, 2);
+		break;
+	case Apdi: // -(An)
+		SETCE020H(2, 0, 2)
+		break;
+	case Ad8r: // (d8,An,Xn)
+	case PC8r: // (d8,PC,Xn)
+		SETCE020H(4, 0, 4)
+		break;
+	case Ad16: // (d16,An)
+	case PC16: // (d16,PC)
+		SETCE020H(2, 0, 2)
+		break;
+	case absw:
+		SETCE020H(2, 0, 2)
+		break;
+	case absl:
+		SETCE020H(4, 0, 4)
+		break;
+	}
+	addcycles_ea_ce020_5 ("cea", h, t, c, oph);
+	return oph;
+}
+
+static int gence020cycles_jea (struct instr *curi, amodes mode)
+{
+	int h = 0, t = 0, c = 0, oph = 0;
+	switch ((int)mode)
+	{
+	case Aind: // (An)
+		SETCE020H(2, 0, 2)
+		break;
+	case Ad16: // (d16,An)
+	case PC16: // (d16,PC)
+		SETCE020H(4, 0, 4)
+		break;
+	case absw:
+		SETCE020H(2, 0, 2)
+		break;
+	case absl:
+		SETCE020H(2, 0, 2)
+		break;
+	}
+	addcycles_ea_ce020_5 ("jea", h, t, c, oph);
+	return oph;
+}
+
+static void next_level_000 (void)
+{
+	if (next_cpu_level < 0)
+		next_cpu_level = 0;
+}
+
+static void maybeaddop_ce020 (int flags)
+{
+	if (flags & GF_OPCE020)
+		addop_ce020 (curi_ce020, subhead_ce020);
+}
+
+
+/* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
+* the calling routine handles Apdi and Aipi modes.
+* gb-- movem == 2 means the same thing but for a MOVE16 instruction */
+
+/* fixup indicates if we want to fix up adress registers in pre decrement
+* or post increment mode now (0) or later (1). A value of 2 will then be
+* used to do the actual fix up. This allows to do all memory readings
+* before any register is modified, and so to rerun operation without
+* side effect in case a bus fault is generated by any memory access.
+* XJ - 2006/11/13 */
+
+static void genamode2x (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags, int fetchmode)
+{
+	char namea[100];
+	bool rmw = false;
+	int pc_68000_offset = m68k_pc_offset;
+	int pc_68000_offset_fetch = 0;
+	int pc_68000_offset_store = 0;
+
+	sprintf (namea, "%sa", name);
+	if ((flags & GF_RMW) && using_mmu == 68060) {
+		strcpy (rmw_varname, name);
+		candormw = true;
+		rmw = true;
+	}
+
+	if (mode == Ad8r || mode == PC8r) {
+		genamode8r_offset[genamode_cnt] = m68k_pc_total + m68k_pc_offset;
+		genamode_cnt++;
+	}
+
+	start_brace ();
+
+	switch (mode) {
+	case Dreg:
+		if (movem)
+			term ();
+		if (getv == 1)
+			switch (size) {
+			case sz_byte:
+#ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
+				/* This causes the target compiler to generate better code on few systems */
+				printf ("\tuae_s8 %s = ((uae_u8*)&m68k_dreg (regs, %s))[3];\n", name, reg);
+#else
+				printf ("\tuae_s8 %s = m68k_dreg (regs, %s);\n", name, reg);
+#endif
+				break;
+			case sz_word:
+#ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
+				printf ("\tuae_s16 %s = ((uae_s16*)&m68k_dreg (regs, %s))[1];\n", name, reg);
+#else
+				printf ("\tuae_s16 %s = m68k_dreg (regs, %s);\n", name, reg);
+#endif
+				break;
+			case sz_long:
+				printf ("\tuae_s32 %s = m68k_dreg (regs, %s);\n", name, reg);
+				break;
+			default:
+				term ();
+		}
+		maybeaddop_ce020 (flags);
+		syncmovepc (getv, flags);
+		return;
+	case Areg:
+		if (movem)
+			term ();
+		if (getv == 1)
+			switch (size) {
+			case sz_word:
+				printf ("\tuae_s16 %s = m68k_areg (regs, %s);\n", name, reg);
+				break;
+			case sz_long:
+				printf ("\tuae_s32 %s = m68k_areg (regs, %s);\n", name, reg);
+				break;
+			default:
+				term ();
+		}
+		maybeaddop_ce020 (flags);
+		syncmovepc (getv, flags);
+		return;
+	case Aind: // (An)
+		switch (fetchmode)
+		{
+			case fetchmode_fea:
+			addcycles_ce020 (1);
+			break;
+			case fetchmode_cea:
+			addcycles_ce020 (2);
+			break;
+			case fetchmode_jea:
+			addcycles_ce020 (2);
+			break;
+		}
+		printf ("\tuaecptr %sa;\n", name);
+		add_mmu040_movem (movem);
+		printf ("\t%sa = m68k_areg (regs, %s);\n", name, reg);
+		break;
+	case Aipi: // (An)+
+		switch (fetchmode)
+		{
+			case fetchmode_fea:
+			addcycles_ce020 (1);
+			break;
+			case fetchmode_cea:
+			break;
+		}
+		printf ("\tuaecptr %sa;\n", name);
+		add_mmu040_movem (movem);
+		printf ("\t%sa = m68k_areg (regs, %s);\n", name, reg);
+		break;
+	case Apdi: // -(An)
+		switch (fetchmode)
+		{
+			case fetchmode_fea:
+			case fetchmode_cea:
+			addcycles_ce020 (2);
+			break;
+		}
+		printf ("\tuaecptr %sa;\n", name);
+		add_mmu040_movem (movem);
+		switch (size) {
+		case sz_byte:
+			if (movem)
+				printf ("\t%sa = m68k_areg (regs, %s);\n", name, reg);
+			else
+				printf ("\t%sa = m68k_areg (regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
+			break;
+		case sz_word:
+			printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
+			break;
+		case sz_long:
+			printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
+			break;
+		default:
+			term ();
+		}
+		if (!(flags & GF_APDI)) {
+			addcycles000 (2);
+			insn_n_cycles += 2;
+			count_cycles_ea += 2;
+			pc_68000_offset_fetch += 2;
+		}
+		break;
+	case Ad16: // (d16,An)
+		printf ("\tuaecptr %sa;\n", name);
+		add_mmu040_movem (movem);
+		printf ("\t%sa = m68k_areg (regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword (flags));
+		count_read_ea++; 
+		break;
+	case PC16: // (d16,PC)
+		printf ("\tuaecptr %sa;\n", name);
+		add_mmu040_movem (movem);
+		printf ("\t%sa = %s + %d;\n", name, getpc, m68k_pc_offset);
+		printf ("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
+		break;
+	case Ad8r: // (d8,An,Xn)
+		switch (fetchmode)
+		{
+			case fetchmode_fea:
+			addcycles_ce020 (4);
+			break;
+			case fetchmode_cea:
+			case fetchmode_jea:
+			break;
+		}
+		printf ("\tuaecptr %sa;\n", name);
+		if (cpu_level > 1) {
+			if (next_cpu_level < 1)
+				next_cpu_level = 1;
+			sync_m68k_pc ();
+			add_mmu040_movem (movem);
+			start_brace ();
+			/* This would ordinarily be done in gen_nextiword, which we bypass.  */
+			insn_n_cycles += 4;
+			printf ("\t%sa = %s (m68k_areg (regs, %s), %d);\n", name, disp020, reg, disp020cnt++);
+		} else {
+			if (!(flags & GF_AD8R)) {
+				addcycles000 (2);
+				insn_n_cycles += 2;
+				count_cycles_ea += 2;
+#ifdef WINUAE_FOR_HATARI
+				/* Hatari : on 68000 ST, Ad8r causes an unaligned memory prefetch and take 2 cycles more */
+				/* JSR, JMP, LEA and PEA are handled separately */
+				/* We add 2 cycles only in 68000 prefetch mode, 68000 CE mode is handled at the memory access level */
+				if ( using_prefetch && !using_ce )
+					printf ("\tBusCyclePenalty += 2;\n");
+#endif
+			}
+			if ((flags & GF_NOREFILL) && using_prefetch) {
+				printf ("\t%sa = %s (m68k_areg (regs, %s), regs.irc);\n", name, disp000, reg);
+			} else {
+				printf ("\t%sa = %s (m68k_areg (regs, %s), %s);\n", name, disp000, reg, gen_nextiword (flags));
+			}
+			count_read_ea++; 
+		}
+		break;
+	case PC8r: // (d8,PC,Xn)
+		switch (fetchmode)
+		{
+			case fetchmode_fea:
+			addcycles_ce020 (4);
+			break;
+			case fetchmode_cea:
+			case fetchmode_jea:
+			break;
+		}
+		printf ("\tuaecptr tmppc;\n");
+		printf ("\tuaecptr %sa;\n", name);
+		if (cpu_level > 1) {
+			if (next_cpu_level < 1)
+				next_cpu_level = 1;
+			sync_m68k_pc ();
+			add_mmu040_movem (movem);
+			start_brace ();
+			/* This would ordinarily be done in gen_nextiword, which we bypass.  */
+			insn_n_cycles += 4;
+			printf ("\ttmppc = %s;\n", getpc);
+			printf ("\t%sa = %s (tmppc, %d);\n", name, disp020, disp020cnt++);
+		} else {
+			printf ("\ttmppc = %s + %d;\n", getpc, m68k_pc_offset);
+			if (!(flags & GF_PC8R)) {
+				addcycles000 (2);
+				insn_n_cycles += 2;
+				count_cycles_ea += 2;
+#ifdef WINUAE_FOR_HATARI
+				/* Hatari : on 68000 ST, Ad8r causes an unaligned memory prefetch and take 2 cycles more */
+				/* JSR, JMP, LEA and PEA are handled separately */
+				/* We add 2 cycles only in 68000 prefetch mode, 68000 CE mode is handled at the memory access level */
+				if ( using_prefetch && !using_ce )
+					printf ("\tBusCyclePenalty += 2;\n");
+#endif
+			}
+			if ((flags & GF_NOREFILL) && using_prefetch) {
+				printf ("\t%sa = %s (tmppc, regs.irc);\n", name, disp000);
+			} else {
+				printf ("\t%sa = %s (tmppc, %s);\n", name, disp000, gen_nextiword (flags));
+			}
+		}
+
+		break;
+	case absw:
+		printf ("\tuaecptr %sa;\n", name);
+		add_mmu040_movem (movem);
+		printf ("\t%sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
+		pc_68000_offset_fetch += 2;
+		break;
+	case absl:
+		gen_nextilong2 ("uaecptr", namea, flags, movem);
+		count_read_ea += 2;
+		pc_68000_offset_fetch += 4;
+		pc_68000_offset_store += 2;
+		break;
+	case imm:
+		// fetch immediate address
+		if (getv != 1)
+			term ();
+		insn_n_cycles020++;
+		switch (size) {
+		case sz_byte:
+			printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
+			count_read_ea++;
+			break;
+		case sz_word:
+			printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
+			count_read_ea++;
+			break;
+		case sz_long:
+			gen_nextilong ("uae_s32", name, flags);
+			count_read_ea += 2;
+			break;
+		default:
+			term ();
+		}
+		maybeaddop_ce020 (flags);
+		syncmovepc (getv, flags);
+		return;
+	case imm0:
+		if (getv != 1)
+			term ();
+		printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
+		count_read_ea++;
+		maybeaddop_ce020 (flags);
+		syncmovepc (getv, flags);
+		return;
+	case imm1:
+		if (getv != 1)
+			term ();
+		printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
+		count_read_ea++;
+		maybeaddop_ce020 (flags);
+		syncmovepc (getv, flags);
+		return;
+	case imm2:
+		if (getv != 1)
+			term ();
+		gen_nextilong ("uae_s32", name, flags);
+		count_read_ea += 2;
+		maybeaddop_ce020 (flags);
+		syncmovepc (getv, flags);
+		return;
+	case immi:
+		if (getv != 1)
+			term ();
+		printf ("\tuae_u32 %s = %s;\n", name, reg);
+		maybeaddop_ce020 (flags);
+		syncmovepc (getv, flags);
+		return;
+	default:
+		term ();
+	}
+
+	syncmovepc (getv, flags);
+	maybeaddop_ce020 (flags);
+
+	/* We get here for all non-reg non-immediate addressing modes to
+	* actually fetch the value. */
+
+	int exception_pc_offset = 0;
+	if (getv == 2) {
+		// store
+		if (pc_68000_offset) {
+			exception_pc_offset = pc_68000_offset + pc_68000_offset_store + 2;
+		}
+	} else {
+		// fetch
+		pc_68000_offset_fetch += 2;
+		exception_pc_offset = pc_68000_offset_fetch;
+	}
+
+	if ((using_prefetch || using_ce) && using_exception_3 && getv != 0 && size != sz_byte) {
+		printf ("\tif (%sa & 1) {\n", name);
+		if (exception_pc_offset)
+			incpc("%d", exception_pc_offset);
+		printf ("\t\texception3_%s(opcode, %sa);\n", getv == 2 ? "write" : "read", name);
+		printf ("\t\tgoto %s;\n", endlabelstr);
+		printf ("\t}\n");
+		need_endlabel = 1;
+		start_brace ();
+	}
+
+	if ((using_prefetch || using_ce) && using_bus_error && getv != 0) {
+		if (exception_pc_offset)
+			printf("\tbus_error_offset = %d;\n", exception_pc_offset);
+	}
+
+	if (flags & GF_PREFETCH)
+		fill_prefetch_next ();
+	else if (flags & GF_IR2IRC)
+		irc2ir_2 (true);
+
+	if (getv == 1) {
+		start_brace ();
+		if (using_ce020 || using_prefetch_020) {
+			switch (size) {
+			case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = %s (%sa);\n", name, srcb, name); count_read++; break;
+			case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = %s (%sa);\n", name, srcw, name); count_read++; break;
+			case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = %s (%sa);\n", name, srcl, name); count_read += 2; break;
+			default: term ();
+			}
+		} else if (using_ce || using_prefetch) {
+			switch (size) {
+			case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = %s (%sa);\n", name, srcb, name); count_read++; break;
+			case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = %s (%sa);\n", name, srcw, name); count_read++; break;
+			case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = %s (%sa) << 16; %s |= %s (%sa + 2);\n", name, srcw, name, name, srcw, name); count_read += 2; break;
+			default: term ();
+			}
+		} else if (using_mmu) {
+			if (flags & GF_FC) {
+				switch (size) {
+				case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = sfc%s_get_byte (%sa);\n", name, mmu_postfix, name); break;
+				case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = sfc%s_get_word (%sa);\n", name, mmu_postfix, name); break;
+				case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = sfc%s_get_long (%sa);\n", name, mmu_postfix, name); break;
+				default: term ();
+				}
+			} else {
+				switch (size) {
+				case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = %s (%sa);\n", name, (flags & GF_LRMW) ? srcblrmw : (rmw ? srcbrmw : srcb), name); break;
+				case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = %s (%sa);\n", name, (flags & GF_LRMW) ? srcwlrmw : (rmw ? srcwrmw : srcw), name); break;
+				case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = %s (%sa);\n", name, (flags & GF_LRMW) ? srcllrmw : (rmw ? srclrmw : srcl), name); break;
+				default: term ();
+				}
+			}
+		} else {
+			switch (size) {
+			case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = %s (%sa);\n", name, srcb, name); count_read++; break;
+			case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = %s (%sa);\n", name, srcw, name); count_read++; break;
+			case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = %s (%sa);\n", name, srcl, name); count_read += 2; break;
+			default: term ();
+			}
+		}
+	}
+
+	/* We now might have to fix up the register for pre-dec or post-inc
+	* addressing modes. */
+	if (!movem)
+		switch (mode) {
+		case Aipi:
+			addmmufixup (reg);
+			switch (size) {
+			case sz_byte:
+				printf ("\tm68k_areg (regs, %s) += areg_byteinc[%s];\n", reg, reg);
+				break;
+			case sz_word:
+				printf ("\tm68k_areg (regs, %s) += 2;\n", reg);
+				break;
+			case sz_long:
+				printf ("\tm68k_areg (regs, %s) += 4;\n", reg);
+				break;
+			default:
+				term ();
+			}
+			break;
+		case Apdi:
+			addmmufixup (reg);
+			printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
+			break;
+		default:
+			break;
+	}
+
+	if (movem == 3) {
+		close_brace ();
+	}
+}
+
+static void genamode2 (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
+{
+	genamode2x (mode, reg, size, name, getv, movem, flags, -1);
+}
+
+static void genamode (struct instr *curi, amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
+{
+	int oldfixup = mmufixupstate;
+	int subhead = 0;
+	if (isce020() && curi) {
+		switch (curi->fetchmode)
+		{
+		case fetchmode_fea:
+			subhead = gence020cycles_fea (mode);
+		break;
+		case fetchmode_cea:
+			subhead = gence020cycles_cea (curi, mode);
+		break;
+		case fetchmode_jea:
+			subhead = gence020cycles_jea (curi, mode);
+		break;
+		}
+		genamode2x (mode, reg, size, name, getv, movem, flags, curi->fetchmode);
+	} else {
+		genamode2 (mode, reg, size, name, getv, movem, flags);
+	}
+	if (using_mmu == 68040 && (oldfixup & 1)) {
+		// we have fixup already active = this genamode call is destination mode and we can now clear previous source fixup.
+		clearmmufixup (0);
+	}
+	if (isce020() && curi)
+		addop_ce020 (curi, subhead);
+}
+
+static void genamode3 (struct instr *curi, amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
+{
+	int oldfixup = mmufixupstate;
+	genamode2x (mode, reg, size, name, getv, movem, flags, curi ? curi->fetchmode : -1);
+	if (using_mmu == 68040 && (oldfixup & 1)) {
+		// we have fixup already active = this genamode call is destination mode and we can now clear previous source fixup.
+		clearmmufixup (0);
+	}
+}
+
+static void genamodedual (struct instr *curi, amodes smode, const char *sreg, wordsizes ssize, const char *sname, int sgetv, int sflags,
+					   amodes dmode, const char *dreg, wordsizes dsize, const char *dname, int dgetv, int dflags)
+{
+	int subhead = 0;
+	bool eadmode = false;
+
+	if (isce020()) {
+		switch (curi->fetchmode)
+		{
+		case fetchmode_fea:
+			if (smode >= imm || isreg (smode)) {
+				subhead = gence020cycles_fea (dmode);
+				eadmode = true;
+			} else {
+				subhead = gence020cycles_fea (smode);
+			}
+		break;
+		case fetchmode_cea:
+			subhead = gence020cycles_cea (curi, smode);
+		break;
+		case fetchmode_fiea:
+			subhead = gence020cycles_fiea (curi, ssize, dmode);
+		break;
+		case fetchmode_ciea:
+			subhead = gence020cycles_ciea (curi, ssize, dmode);
+		break;
+		case fetchmode_jea:
+			subhead = gence020cycles_jea (curi, smode);
+		break;
+		default:
+			printf ("\t/* No EA */\n");
+		break;
+		}
+	}
+	subhead_ce020 = subhead;
+	curi_ce020 = curi;
+	genamode3 (curi, smode, sreg, ssize, sname, sgetv, 0, sflags);
+	genamode3 (NULL, dmode, dreg, dsize, dname, dgetv, 0, dflags | (eadmode == true ? GF_OPCE020 : 0));
+	if (eadmode == false)
+		maybeaddop_ce020 (GF_OPCE020);
+}
+
+static void genastore_2 (const char *from, amodes mode, const char *reg, wordsizes size, const char *to, int store_dir, int flags)
+{
+	if (candormw) {
+		if (strcmp (rmw_varname, to) != 0)
+			candormw = false;
+	}
+	genastore_done = true;
+	returntail (mode != Dreg && mode != Areg);
+
+	switch (mode) {
+	case Dreg:
+		switch (size) {
+		case sz_byte:
+			printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
+			break;
+		case sz_word:
+			printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
+			break;
+		case sz_long:
+			printf ("\tm68k_dreg (regs, %s) = (%s);\n", reg, from);
+			break;
+		default:
+			term ();
+		}
+		break;
+	case Areg:
+		switch (size) {
+		case sz_word:
+			printf ("\tm68k_areg (regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
+			break;
+		case sz_long:
+			printf ("\tm68k_areg (regs, %s) = (%s);\n", reg, from);
+			break;
+		default:
+			term ();
+		}
+		break;
+	case Aind:
+	case Aipi:
+	case Apdi:
+	case Ad16:
+	case Ad8r:
+	case absw:
+	case absl:
+	case PC16:
+	case PC8r:
+		if (!(flags & GF_NOFAULTPC))
+			gen_set_fault_pc ();
+		if (using_ce020 || using_prefetch_020) {
+			switch (size) {
+			case sz_byte:
+				printf ("\t%s (%sa, %s);\n", dstb, to, from);
+				count_write++;
+				break;
+			case sz_word:
+				if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
+					term ();
+				printf ("\t%s (%sa, %s);\n", dstw, to, from);
+				count_write++;
+				break;
+			case sz_long:
+				if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
+					term ();
+				printf ("\t%s (%sa, %s);\n", dstl, to, from);
+				count_write += 2;
+				break;
+			default:
+				term ();
+			}
+		} else if (using_ce) {
+			switch (size) {
+			case sz_byte:
+				check_ipl_again();
+				printf ("\tx_put_byte (%sa, %s);\n", to, from);
+				count_write++;
+				break;
+			case sz_word:
+				if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
+					term ();
+				check_ipl_again();
+				printf ("\tx_put_word (%sa, %s);\n", to, from);
+				count_write++;
+				break;
+			case sz_long:
+				if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
+					term ();
+				if (store_dir) {
+					printf ("\t%s (%sa + 2, %s);\n", dstw, to, from);
+					check_ipl_again();
+					printf ("%s (%sa, %s >> 16);\n", dstw, to, from);
+				} else {
+					printf ("\t%s (%sa, %s >> 16);\n", dstw, to, from);
+					check_ipl_again();
+					printf ("\t%s (%sa + 2, %s);\n", dstw, to, from);
+				}
+				count_write += 2;
+				break;
+			default:
+				term ();
+			}
+		} else if (using_mmu) {
+			switch (size) {
+			case sz_byte:
+				insn_n_cycles += 4;
+				if (flags & GF_FC)
+					printf ("\tdfc%s_put_byte (%sa, %s);\n", mmu_postfix, to, from);
+				else
+					printf ("\t%s (%sa, %s);\n", (flags & GF_LRMW) ? dstblrmw : (candormw ? dstbrmw : dstb), to, from);
+				break;
+			case sz_word:
+				insn_n_cycles += 4;
+				if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
+					term ();
+				if (flags & GF_FC)
+					printf ("\tdfc%s_put_word (%sa, %s);\n", mmu_postfix, to, from);
+				else
+					printf ("\t%s (%sa, %s);\n", (flags & GF_LRMW) ? dstwlrmw : (candormw ? dstwrmw : dstw), to, from);
+				break;
+			case sz_long:
+				insn_n_cycles += 8;
+				if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
+					term ();
+				if (flags & GF_FC)
+					printf ("\tdfc%s_put_long (%sa, %s);\n", mmu_postfix, to, from);
+				else
+					printf ("\t%s (%sa, %s);\n", (flags & GF_LRMW) ? dstllrmw : (candormw ? dstlrmw : dstl), to, from);
+				break;
+			default:
+				term ();
+			}
+		} else if (using_prefetch) {
+			switch (size) {
+			case sz_byte:
+				insn_n_cycles += 4;
+				printf ("\t%s (%sa, %s);\n", dstb, to, from);
+				count_write++;
+				break;
+			case sz_word:
+				insn_n_cycles += 4;
+				if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
+					term ();
+				printf ("\t%s (%sa, %s);\n", dstw, to, from);
+				count_write++;
+				break;
+			case sz_long:
+				insn_n_cycles += 8;
+				if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
+					term ();
+				if (store_dir)
+					printf ("\t%s (%sa + 2, %s); %s (%sa, %s >> 16);\n", dstw, to, from, dstw, to, from);
+				else
+					printf ("\t%s (%sa, %s >> 16); %s (%sa + 2, %s);\n", dstw, to, from, dstw, to, from);
+				count_write += 2;
+				break;
+			default:
+				term ();
+			}
+		} else {
+			switch (size) {
+			case sz_byte:
+				insn_n_cycles += 4;
+				printf ("\t%s (%sa, %s);\n", dstb, to, from);
+				count_write++;
+				break;
+			case sz_word:
+				insn_n_cycles += 4;
+				if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
+					term ();
+				printf ("\t%s (%sa, %s);\n", dstw, to, from);
+				count_write++;
+				break;
+			case sz_long:
+				insn_n_cycles += 8;
+				if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
+					term ();
+				printf ("\t%s (%sa, %s);\n", dstl, to, from);
+				count_write += 2;
+				break;
+			default:
+				term ();
+			}
+		}
+		break;
+	case imm:
+	case imm0:
+	case imm1:
+	case imm2:
+	case immi:
+		term ();
+		break;
+	default:
+		term ();
+	}
+}
+
+static void genastore (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
+{
+	genastore_2 (from, mode, reg, size, to, 0, 0);
+}
+static void genastore_tas (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
+{
+	genastore_2 (from, mode, reg, size, to, 0, GF_LRMW);
+}
+static void genastore_cas (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
+{
+	genastore_2 (from, mode, reg, size, to, 0, GF_LRMW | GF_NOFAULTPC);
+}
+static void genastore_rev (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
+{
+	genastore_2 (from, mode, reg, size, to, 1, 0);
+}
+static void genastore_fc (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
+{
+	genastore_2 (from, mode, reg, size, to, 1, GF_FC);
+}
+
+static void movem_mmu060 (const char *code, int size, bool put, bool aipi, bool apdi)
+{
+	const char *index;
+	int dphase;
+	int i;
+	if (apdi) {
+		dphase = 1;
+		index = "movem_index2";
+	} else {
+		dphase = 0;
+		index = "movem_index1";
+	}
+
+	if (!put) {
+		printf("\tuae_u32 tmp[16];\n");
+		printf("\tint tmpreg[16];\n");
+		printf("\tint idx = 0;\n");
+		for (i = 0; i < 2; i++) {
+			char reg;
+			if (i == dphase)
+				reg = 'd';
+			else
+				reg = 'a';
+			printf ("\twhile (%cmask) {\n", reg);
+			if (apdi)
+				printf ("\t\tsrca -= %d;\n", size);
+			printf ("\t\ttmpreg[idx] = %s[%cmask] + %d;\n", index, reg, i == dphase ? 0 : 8);
+			printf ("\t\ttmp[idx++] = %s;\n", code);
+			if (!apdi)
+				printf ("\t\tsrca += %d;\n", size);
+			printf ("\t\t%cmask = movem_next[%cmask];\n", reg, reg);
+			printf ("\t}\n");
+		}
+		if (aipi || apdi)
+			printf ("\tm68k_areg (regs, dstreg) = srca;\n");
+		printf ("\twhile (--idx >= 0) {\n");
+		printf ("\t\tregs.regs[tmpreg[idx]] = tmp[idx];\n");
+		printf ("\t}\n");
+	} else {
+		for (i = 0; i < 2; i++) {
+			char reg;
+			if (i == dphase)
+				reg = 'd';
+			else
+				reg = 'a';
+			printf ("\twhile (%cmask) {\n", reg);
+			if (apdi)
+				printf ("\t\tsrca -= %d;\n", size);
+			if (put) {
+				printf ("\t\t%s, m68k_%creg (regs, %s[%cmask]));\n", code, reg, index, reg);
+			} else {
+				printf ("\t\tm68k_%creg (regs, %s[%cmask]) = %s;\n", reg, index, reg, code);
+			}
+			if (!apdi)
+				printf ("\t\tsrca += %d;\n", size);
+			printf ("\t\t%cmask = movem_next[%cmask];\n", reg, reg);
+			printf ("\t}\n");
+		}
+		if (aipi || apdi)
+			printf ("\tm68k_areg (regs, dstreg) = srca;\n");
+	}
+}
+
+static bool mmu040_special_movem (uae_u16 opcode)
+{
+	if (using_mmu != 68040)
+		return false;
+	return true;
+//	return (((((opcode >> 3) & 7) == 7) && ((opcode & 7) == 2 || (opcode & 7) == 3)) || ((opcode >> 3) & 7) == 6);
+}
+
+static void movem_mmu040 (const char *code, int size, bool put, bool aipi, bool apdi, uae_u16 opcode)
+{
+	const char *index;
+	int dphase;
+	int i;
+
+	if (apdi) {
+		dphase = 1;
+		index = "movem_index2";
+	} else {
+		dphase = 0;
+		index = "movem_index1";
+	}
+
+	printf ("\tmmu040_movem = 1;\n");
+	printf ("\tmmu040_movem_ea = srca;\n");
+
+	for (i = 0; i < 2; i++) {
+		char reg;
+		if (i == dphase)
+			reg = 'd';
+		else
+			reg = 'a';
+		printf ("\twhile (%cmask) {\n", reg);
+		if (apdi)
+			printf ("\t\tsrca -= %d;\n", size);
+		if (put) {
+			printf ("\t\t%s, m68k_%creg (regs, %s[%cmask]));\n", code, reg, index, reg);
+		} else {
+			printf ("\t\tm68k_%creg (regs, %s[%cmask]) = %s;\n", reg, index, reg, code);
+		}
+		if (!apdi)
+			printf ("\t\tsrca += %d;\n", size);
+		printf ("\t\t%cmask = movem_next[%cmask];\n", reg, reg);
+		printf ("\t}\n");
+	}
+	if (aipi || apdi)
+		printf ("\tm68k_areg (regs, dstreg) = srca;\n");
+	printf ("\tmmu040_movem = 0;\n");
+}
+
+/* 68030 MMU does not restore register state if it bus faults.
+ * (also there wouldn't be enough space in stack frame to store all registers)
+ */
+static void movem_mmu030 (const char *code, int size, bool put, bool aipi, bool apdi)
+{
+	const char *index;
+	int dphase;
+	int i;
+	if (apdi) {
+		dphase = 1;
+		index = "movem_index2";
+	} else {
+		dphase = 0;
+		index = "movem_index1";
+	}
+	printf ("\tmmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;\n");
+	printf ("\tint movem_cnt = 0;\n");
+	if (!put) {
+		printf ("\tuae_u32 val;\n");
+		printf ("\tif (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2)\n");
+		printf ("\t\tsrca = mmu030_ad[mmu030_idx].val;\n");
+		printf ("\telse\n");
+		printf ("\t\tmmu030_ad[mmu030_idx].val = srca;\n");
+	}
+	for (i = 0; i < 2; i++) {
+		char reg;
+		if (i == dphase)
+			reg = 'd';
+		else
+			reg = 'a';
+		printf ("\twhile (%cmask) {\n", reg);
+		if (apdi)
+			printf ("\t\tsrca -= %d;\n", size);
+		printf ("\t\tif (mmu030_state[0] == movem_cnt) {\n");
+		printf ("\t\t\tif (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {\n");
+		printf ("\t\t\t\tmmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;\n");
+		if (!put)
+			printf ("\t\t\t\tval = %smmu030_data_buffer;\n", size == 2 ? "(uae_s32)(uae_s16)" : "");
+		printf ("\t\t\t} else {\n");
+		if (put)
+			printf ("\t\t\t\t%s, (mmu030_data_buffer = m68k_%creg (regs, %s[%cmask])));\n", code, reg, index, reg);
+		else
+			printf ("\t\t\t\tval = %s;\n", code);
+		printf ("\t\t\t}\n");
+		if (!put) {
+			printf ("\t\t\tm68k_%creg (regs, %s[%cmask]) = val;\n", reg, index, reg);
+		}
+		printf ("\t\t\tmmu030_state[0]++;\n");
+		printf ("\t\t}\n");
+		if (!apdi)
+			printf ("\t\tsrca += %d;\n", size);
+		printf ("\t\tmovem_cnt++;\n");
+		printf ("\t\t%cmask = movem_next[%cmask];\n", reg, reg);
+		printf ("\t}\n");
+	}
+	if (aipi || apdi)
+		printf ("\tm68k_areg (regs, dstreg) = srca;\n");
+}
+
+static void genmovemel (uae_u16 opcode)
+{
+	char getcode[100];
+	int size = table68k[opcode].size == sz_long ? 4 : 2;
+
+	if (table68k[opcode].size == sz_long) {
+		sprintf (getcode, "%s (srca)", srcld);
+	} else {
+		sprintf (getcode, "(uae_s32)(uae_s16)%s (srca)", srcwd);
+	}
+	count_read += table68k[opcode].size == sz_long ? 2 : 1;
+	printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
+	printf ("\tuae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
+	genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, mmu040_special_movem (opcode) ? 3 : 1, GF_MOVE);
+	addcycles_ce020 (8 - 2);
+	start_brace ();
+	if (using_mmu == 68030) {
+		movem_mmu030 (getcode, size, false, table68k[opcode].dmode == Aipi, false);
+	} else if (using_mmu == 68060) {
+		movem_mmu060 (getcode, size, false, table68k[opcode].dmode == Aipi, false);
+	} else if (using_mmu == 68040) {
+		movem_mmu040 (getcode, size, false, table68k[opcode].dmode == Aipi, false, opcode);
+	} else {
+		printf ("\twhile (dmask) {\n");
+		printf ("\t\tm68k_dreg (regs, movem_index1[dmask]) = %s; srca += %d; dmask = movem_next[dmask];\n", getcode, size);
+		//addcycles_ce020 (1);
+		printf ("\t}\n");
+		printf ("\twhile (amask) {\n");
+		printf ("\t\tm68k_areg (regs, movem_index1[amask]) = %s; srca += %d; amask = movem_next[amask];\n", getcode, size);
+		//addcycles_ce020 (1);
+		printf ("\t}\n");
+		if (table68k[opcode].dmode == Aipi) {
+			printf ("\tm68k_areg (regs, dstreg) = srca;\n");
+			count_read++;
+		}
+	}
+	count_ncycles++;
+	fill_prefetch_next ();
+	get_prefetch_020 ();
+}
+
+static void genmovemel_ce (uae_u16 opcode)
+{
+	int size = table68k[opcode].size == sz_long ? 4 : 2;
+	printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
+	printf ("\tuae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
+	printf ("\tuae_u32 v;\n");
+	if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
+		addcycles000 (2);
+	genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA | GF_MOVE);
+	start_brace ();
+	if (table68k[opcode].size == sz_long) {
+		printf ("\twhile (dmask) {\n");
+		printf ("\t\tv = %s (srca) << 16;\n", srcw);
+		printf ("\t\tv |= %s (srca + 2);\n", srcw);
+		printf ("\t\tm68k_dreg (regs, movem_index1[dmask]) = v;\n");
+		printf ("\t\tsrca += %d;\n", size);
+		printf ("\t\tdmask = movem_next[dmask];\n");
+		addcycles000_nonce("\t\t", 8);
+		printf ("\t}\n");
+		printf ("\twhile (amask) {\n");
+		printf ("\t\tv = %s (srca) << 16;\n", srcw);
+		printf ("\t\tv |= %s (srca + 2);\n", srcw);
+		printf ("\t\tm68k_areg (regs, movem_index1[amask]) = v;\n");
+		printf ("\t\tsrca += %d;\n", size);
+		printf ("\t\tamask = movem_next[amask];\n");
+		addcycles000_nonce("\t\t", 8);
+		printf ("\t}\n");
+	} else {
+		printf ("\twhile (dmask) {\n");
+		printf ("\t\tm68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)%s (srca);\n", srcw);
+		printf ("\t\tsrca += %d;\n", size);
+		printf ("\t\tdmask = movem_next[dmask];\n");
+		addcycles000_nonce("\t\t", 4);
+		printf ("\t}\n");
+		printf ("\twhile (amask) {\n");
+		printf ("\t\tm68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)%s (srca);\n", srcw);
+		printf ("\t\tsrca += %d;\n", size);
+		printf ("\t\tamask = movem_next[amask];\n");
+		addcycles000_nonce("\t\t", 4);
+		printf ("\t}\n");
+	}
+	printf ("\t%s (srca);\n", srcw); // and final extra word fetch that goes nowhere..
+	count_read++;
+	if (table68k[opcode].dmode == Aipi)
+		printf ("\tm68k_areg (regs, dstreg) = srca;\n");
+	count_ncycles++;
+	fill_prefetch_next ();
+}
+
+static void genmovemle (uae_u16 opcode)
+{
+	char putcode[100];
+	int size = table68k[opcode].size == sz_long ? 4 : 2;
+
+	if (table68k[opcode].size == sz_long) {
+		sprintf (putcode, "%s (srca", dstld);
+	} else {
+		sprintf (putcode, "%s (srca", dstwd);
+	}
+	count_write += table68k[opcode].size == sz_long ? 2 : 1;
+
+	printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
+	genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, mmu040_special_movem (opcode) ? 3 : 1, GF_MOVE);
+	addcycles_ce020 (4 - 2);
+	start_brace ();
+	if (using_mmu >= 68030) {
+		if (table68k[opcode].dmode == Apdi)
+			printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
+		else
+			printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
+		if (using_mmu == 68030)
+			movem_mmu030 (putcode, size, true, false, table68k[opcode].dmode == Apdi);
+		else if (using_mmu == 68060)
+			movem_mmu060 (putcode, size, true, false, table68k[opcode].dmode == Apdi);
+		else if (using_mmu == 68040)
+			movem_mmu040 (putcode, size, true, false, table68k[opcode].dmode == Apdi, opcode);
+	} else {
+		if (table68k[opcode].dmode == Apdi) {
+			printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
+			if (!using_mmu)
+				printf ("\tint type = get_cpu_model () >= 68020;\n");
+			printf ("\twhile (amask) {\n");
+			printf ("\t\tsrca -= %d;\n", size);
+
+			printf ("\t\tif (!type || movem_index2[amask] != dstreg)\n");
+			printf ("\t\t\t%s, m68k_areg (regs, movem_index2[amask]));\n", putcode);
+			printf ("\t\telse\n");
+			printf ("\t\t\t%s, m68k_areg (regs, movem_index2[amask]) - %d);\n", putcode, size);
+
+			printf ("\t\tamask = movem_next[amask];\n");
+			printf ("\t}\n");
+			printf ("\twhile (dmask) { srca -= %d; %s, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }\n",
+				size, putcode);
+			printf ("\tm68k_areg (regs, dstreg) = srca;\n");
+		} else {
+			printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
+			printf ("\twhile (dmask) { %s, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; }\n",
+				putcode, size);
+			printf ("\twhile (amask) { %s, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask]; }\n",
+				putcode, size);
+		}
+	}
+	count_ncycles++;
+	fill_prefetch_next ();
+	get_prefetch_020 ();
+}
+
+static void genmovemle_ce (uae_u16 opcode)
+{
+	int size = table68k[opcode].size == sz_long ? 4 : 2;
+
+	printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
+	if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
+		addcycles000 (2);
+	genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA | GF_MOVE);
+	start_brace ();
+	if (table68k[opcode].size == sz_long) {
+		if (table68k[opcode].dmode == Apdi) {
+			printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
+			printf ("\twhile (amask) {\n");
+			printf ("\t\tsrca -= %d;\n", size);
+			printf ("\t\t%s (srca, m68k_areg (regs, movem_index2[amask]) >> 16);\n", dstw);
+			printf ("\t\t%s (srca + 2, m68k_areg (regs, movem_index2[amask]));\n", dstw);
+			printf ("\t\tamask = movem_next[amask];\n");
+			addcycles000_nonce("\t\t", 8);
+			printf ("\t}\n");
+			printf ("\twhile (dmask) {\n");
+			printf ("\t\tsrca -= %d;\n", size);
+			printf ("\t\t%s (srca, m68k_dreg (regs, movem_index2[dmask]) >> 16);\n", dstw);
+			printf ("\t\t%s (srca + 2, m68k_dreg (regs, movem_index2[dmask]));\n", dstw);
+			printf ("\t\tdmask = movem_next[dmask];\n");
+			addcycles000_nonce("\t\t", 8);
+			printf ("\t}\n");
+			printf ("\tm68k_areg (regs, dstreg) = srca;\n");
+		} else {
+			printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
+			printf ("\twhile (dmask) {\n");
+			printf ("\t\t%s (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16);\n", dstw);
+			printf ("\t\t%s (srca + 2, m68k_dreg (regs, movem_index1[dmask]));\n", dstw);
+			printf ("\t\tsrca += %d;\n", size);
+			printf ("\t\tdmask = movem_next[dmask];\n");
+			addcycles000_nonce("\t\t", 8);
+			printf ("\t}\n");
+			printf ("\twhile (amask) {\n");
+			printf ("\t\t%s (srca, m68k_areg (regs, movem_index1[amask]) >> 16);\n", dstw);
+			printf ("\t\t%s (srca + 2, m68k_areg (regs, movem_index1[amask]));\n", dstw);
+			printf ("\t\tsrca += %d;\n", size);
+			printf ("\t\tamask = movem_next[amask];\n");
+			addcycles000_nonce("\t\t", 8);
+			printf ("\t}\n");
+		}
+	} else {
+		if (table68k[opcode].dmode == Apdi) {
+			printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
+			printf ("\twhile (amask) {\n");
+			printf ("\t\tsrca -= %d;\n", size);
+			printf ("\t\t%s (srca, m68k_areg (regs, movem_index2[amask]));\n", dstw);
+			printf ("\tamask = movem_next[amask];\n");
+			addcycles000_nonce("\t\t", 4);
+			printf ("\t}\n");
+			printf ("\twhile (dmask) {\n");
+			printf ("\t\tsrca -= %d;\n", size);
+			printf ("\t\t%s (srca, m68k_dreg (regs, movem_index2[dmask]));\n", dstw);
+			printf ("\t\tdmask = movem_next[dmask];\n");
+			addcycles000_nonce("\t\t", 4);
+			printf ("\t}\n");
+			printf ("\tm68k_areg (regs, dstreg) = srca;\n");
+		} else {
+			printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
+			printf ("\twhile (dmask) {\n");
+			printf ("\t\t%s (srca, m68k_dreg (regs, movem_index1[dmask]));\n", dstw);
+			printf ("\t\tsrca += %d;\n", size);
+			printf ("\t\tdmask = movem_next[dmask];\n");
+			addcycles000_nonce("\t\t", 4);
+			printf ("\t}\n");
+			printf ("\twhile (amask) {\n");
+			printf ("\t\t%s (srca, m68k_areg (regs, movem_index1[amask]));\n", dstw);
+			printf ("\t\tsrca += %d;\n", size);
+			printf ("\t\tamask = movem_next[amask];\n");
+			addcycles000_nonce("\t\t", 4);
+			printf ("\t}\n");
+		}
+	}
+	count_ncycles++;
+	fill_prefetch_next ();
+}
+
+static void duplicate_carry (int n)
+{
+	int i;
+	for (i = 0; i <= n; i++)
+		printf ("\t");
+	printf ("COPY_CARRY ();\n");
+}
+
+typedef enum
+{
+	flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_z, flag_zn,
+	flag_av, flag_sv
+}
+flagtypes;
+
+static void genflags_normal (flagtypes type, wordsizes size, const char *value, const char *src, const char *dst)
+{
+	char vstr[100], sstr[100], dstr[100];
+	char usstr[100], udstr[100];
+	char unsstr[100], undstr[100];
+
+	switch (size) {
+	case sz_byte:
+		strcpy (vstr, "((uae_s8)(");
+		strcpy (usstr, "((uae_u8)(");
+		break;
+	case sz_word:
+		strcpy (vstr, "((uae_s16)(");
+		strcpy (usstr, "((uae_u16)(");
+		break;
+	case sz_long:
+		strcpy (vstr, "((uae_s32)(");
+		strcpy (usstr, "((uae_u32)(");
+		break;
+	default:
+		term ();
+	}
+	strcpy (unsstr, usstr);
+
+	strcpy (sstr, vstr);
+	strcpy (dstr, vstr);
+	strcat (vstr, value);
+	strcat (vstr, "))");
+	strcat (dstr, dst);
+	strcat (dstr, "))");
+	strcat (sstr, src);
+	strcat (sstr, "))");
+
+	strcpy (udstr, usstr);
+	strcat (udstr, dst);
+	strcat (udstr, "))");
+	strcat (usstr, src);
+	strcat (usstr, "))");
+
+	strcpy (undstr, unsstr);
+	strcat (unsstr, "-");
+	strcat (undstr, "~");
+	strcat (undstr, dst);
+	strcat (undstr, "))");
+	strcat (unsstr, src);
+	strcat (unsstr, "))");
+
+	switch (type) {
+	case flag_logical_noclobber:
+	case flag_logical:
+	case flag_z:
+	case flag_zn:
+	case flag_av:
+	case flag_sv:
+	case flag_addx:
+	case flag_subx:
+		break;
+
+	case flag_add:
+		start_brace ();
+		printf ("uae_u32 %s = %s + %s;\n", value, udstr, usstr);
+		break;
+	case flag_sub:
+	case flag_cmp:
+		start_brace ();
+		printf ("uae_u32 %s = %s - %s;\n", value, udstr, usstr);
+		break;
+	}
+
+	switch ((int)type) {
+	case flag_logical_noclobber:
+	case flag_logical:
+	case flag_zn:
+		break;
+
+	case flag_add:
+	case flag_sub:
+	case flag_addx:
+	case flag_subx:
+	case flag_cmp:
+	case flag_av:
+	case flag_sv:
+		start_brace ();
+		printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
+		printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
+		printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
+		break;
+	}
+
+	switch (type) {
+	case flag_logical:
+		printf ("\tCLEAR_CZNV ();\n");
+		printf ("\tSET_ZFLG (%s == 0);\n", vstr);
+		printf ("\tSET_NFLG (%s < 0);\n", vstr);
+		break;
+	case flag_logical_noclobber:
+		printf ("\tSET_ZFLG (%s == 0);\n", vstr);
+		printf ("\tSET_NFLG (%s < 0);\n", vstr);
+		break;
+	case flag_av:
+		printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
+		break;
+	case flag_sv:
+		printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
+		break;
+	case flag_z:
+		printf ("\tSET_ZFLG (GET_ZFLG () & (%s == 0));\n", vstr);
+		break;
+	case flag_zn:
+		printf ("\tSET_ZFLG (GET_ZFLG () & (%s == 0));\n", vstr);
+		printf ("\tSET_NFLG (%s < 0);\n", vstr);
+		break;
+	case flag_add:
+		printf ("\tSET_ZFLG (%s == 0);\n", vstr);
+		printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
+		printf ("\tSET_CFLG (%s < %s);\n", undstr, usstr);
+		duplicate_carry (0);
+		printf ("\tSET_NFLG (flgn != 0);\n");
+		break;
+	case flag_sub:
+		printf ("\tSET_ZFLG (%s == 0);\n", vstr);
+		printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
+		printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
+		duplicate_carry (0);
+		printf ("\tSET_NFLG (flgn != 0);\n");
+		break;
+	case flag_addx:
+		printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
+		printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
+		duplicate_carry (0);
+		break;
+	case flag_subx:
+		printf ("\tSET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
+		printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
+		duplicate_carry (0);
+		break;
+	case flag_cmp:
+		printf ("\tSET_ZFLG (%s == 0);\n", vstr);
+		printf ("\tSET_VFLG ((flgs != flgo) && (flgn != flgo));\n");
+		printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
+		printf ("\tSET_NFLG (flgn != 0);\n");
+		break;
+	}
+}
+
+static void genflags (flagtypes type, wordsizes size, const char *value, const char *src, const char *dst)
+{
+	/* Temporarily deleted 68k/ARM flag optimizations.  I'd prefer to have
+	them in the appropriate m68k.h files and use just one copy of this
+	code here.  The API can be changed if necessary.  */
+	if (optimized_flags) {
+		switch (type) {
+		case flag_add:
+		case flag_sub:
+			start_brace ();
+			printf ("\tuae_u32 %s;\n", value);
+			break;
+
+		default:
+			break;
+		}
+
+		/* At least some of those casts are fairly important! */
+		switch (type) {
+		case flag_logical_noclobber:
+			printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
+			if (strcmp (value, "0") == 0) {
+				printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
+			} else {
+				switch ((int)size) {
+				case sz_byte: printf ("\toptflag_testb (regs, (uae_s8)(%s));\n", value); break;
+				case sz_word: printf ("\toptflag_testw (regs, (uae_s16)(%s));\n", value); break;
+				case sz_long: printf ("\toptflag_testl (regs, (uae_s32)(%s));\n", value); break;
+				}
+				printf ("\tIOR_CZNV (oldcznv);\n");
+			}
+			printf ("\t}\n");
+			return;
+		case flag_logical:
+			if (strcmp (value, "0") == 0) {
+				printf ("\tSET_CZNV (FLAGVAL_Z);\n");
+			} else {
+				switch ((int)size) {
+				case sz_byte: printf ("\toptflag_testb (regs, (uae_s8)(%s));\n", value); break;
+				case sz_word: printf ("\toptflag_testw (regs, (uae_s16)(%s));\n", value); break;
+				case sz_long: printf ("\toptflag_testl (regs, (uae_s32)(%s));\n", value); break;
+				}
+			}
+			return;
+
+		case flag_add:
+			switch ((int)size) {
+			case sz_byte: printf ("\toptflag_addb (regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
+			case sz_word: printf ("\toptflag_addw (regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
+			case sz_long: printf ("\toptflag_addl (regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
+			}
+			return;
+
+		case flag_sub:
+			switch ((int)size) {
+			case sz_byte: printf ("\toptflag_subb (regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
+			case sz_word: printf ("\toptflag_subw (regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
+			case sz_long: printf ("\toptflag_subl (regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
+			}
+			return;
+
+		case flag_cmp:
+			switch ((int)size) {
+			case sz_byte: printf ("\toptflag_cmpb (regs, (uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
+			case sz_word: printf ("\toptflag_cmpw (regs, (uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
+			case sz_long: printf ("\toptflag_cmpl (regs, (uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
+			}
+			return;
+
+		default:
+			break;
+		}
+	}
+
+	genflags_normal (type, size, value, src, dst);
+}
+
+static void force_range_for_rox (const char *var, wordsizes size)
+{
+	/* Could do a modulo operation here... which one is faster? */
+	switch ((int)size) {
+	case sz_long:
+		printf ("\tif (%s >= 33) %s -= 33;\n", var, var);
+		break;
+	case sz_word:
+		printf ("\tif (%s >= 34) %s -= 34;\n", var, var);
+		printf ("\tif (%s >= 17) %s -= 17;\n", var, var);
+		break;
+	case sz_byte:
+		printf ("\tif (%s >= 36) %s -= 36;\n", var, var);
+		printf ("\tif (%s >= 18) %s -= 18;\n", var, var);
+		printf ("\tif (%s >= 9) %s -= 9;\n", var, var);
+		break;
+	}
+}
+
+static const char *cmask (wordsizes size)
+{
+	switch (size) {
+	case sz_byte: return "0x80";
+	case sz_word: return "0x8000";
+	case sz_long: return "0x80000000";
+	default: term ();
+	}
+}
+
+static int source_is_imm1_8 (struct instr *i)
+{
+	return i->stype == 3;
+}
+
+static void shift_ce (amodes dmode, int size)
+{
+	if (isreg (dmode)) {
+		int c = size == sz_long ? 4 : 2;
+		if (using_ce) {
+			printf ("\t{\n");
+			printf ("\t\tint cycles = %d;\n", c);
+			printf ("\t\tcycles += 2 * ccnt;\n");
+			addcycles000_3 ("\t\t");
+			printf ("\t}\n");
+		}
+		addcycles000_nonces("\t", "2 * ccnt");
+		count_cycles += c;
+		count_ncycles++;
+	}
+}
+
+// BCHG/BSET/BCLR Dx,Dx or #xx,Dx adds 2 cycles if bit number > 15 
+static void bsetcycles (struct instr *curi)
+{
+	if (curi->size == sz_byte) {
+		printf ("\tsrc &= 7;\n");
+	} else {
+		printf ("\tsrc &= 31;\n");
+		if (isreg (curi->dmode)) {
+			addcycles000 (2);
+			if (curi->mnemo != i_BTST) {
+				if (using_ce)
+					printf ("\tif (src > 15) %s (2);\n", do_cycles);
+				addcycles000_nonce("\tif (src > 15) ", 2);
+				count_ncycles++;
+			}
+		}
+	}
+}
+
+static int islongimm (struct instr *curi)
+{
+	return (curi->size == sz_long && (curi->smode == Dreg || curi->smode == imm || curi->smode == Areg));
+}
+
+
+static void resetvars (void)
+{
+	insn_n_cycles = using_prefetch ? 0 : 4;
+	insn_n_cycles020 = 0;
+	genamode_cnt = 0;
+	genamode8r_offset[0] = genamode8r_offset[1] = 0;
+	m68k_pc_total = 0;
+	branch_inst = 0;
+
+	ir2irc = 0;
+	mmufixupcnt = 0;
+	mmufixupstate = 0;
+	disp020cnt = 0;
+	candormw = false;
+	genastore_done = false;
+	rmw_varname[0] = 0;
+	tail_ce020 = 0;
+	total_ce020 = 0;
+	tail_ce020_done = false;
+	head_in_ea_ce020 = 0;
+	head_ce020_cycs_done = false;
+	no_prefetch_ce020 = false;
+	got_ea_ce020 = false;
+	
+	prefetch_long = NULL;
+	srcli = NULL;
+	srcbi = NULL;
+	disp000 = "get_disp_ea_000";
+	disp020 = "get_disp_ea_020";
+	nextw = NULL;
+	nextl = NULL;
+	do_cycles = "do_cycles";
+	srcwd = srcld = NULL;
+	dstwd = dstld = NULL;
+	srcblrmw = NULL;
+	srcwlrmw = NULL;
+	srcllrmw = NULL;
+	dstblrmw = NULL;
+	dstwlrmw = NULL;
+	dstllrmw = NULL;
+	getpc = "m68k_getpc ()";
+
+	if (using_indirect) {
+		// tracer
+		getpc = "m68k_getpci ()";
+		if (!using_ce020 && !using_prefetch_020 && !using_ce) {
+			// generic + indirect
+			disp020 = "x_get_disp_ea_020";
+			prefetch_long = "get_iilong_jit";
+			prefetch_word = "get_iiword_jit";
+			nextw = "next_iiword_jit";
+			nextl = "next_iilong_jit";
+			srcli = "get_iilong_jit";
+			srcwi = "get_iiword_jit";
+			srcbi = "get_iibyte_jit";
+			srcl = "x_get_long";
+			dstl = "x_put_long";
+			srcw = "x_get_word";
+			dstw = "x_put_word";
+			srcb = "x_get_byte";
+			dstb = "x_put_byte";
+			getpc = "m68k_getpc()"; // special jit support
+		} else if (!using_ce020 && !using_prefetch_020) {
+			prefetch_word = "get_word_ce000_prefetch";
+			srcli = "x_get_ilong";
+			srcwi = "x_get_iword";
+			srcbi = "x_get_ibyte";
+			srcl = "x_get_long";
+			dstl = "x_put_long";
+			srcw = "x_get_word";
+			dstw = "x_put_word";
+			srcb = "x_get_byte";
+			dstb = "x_put_byte";
+			do_cycles = "do_cycles_ce000_internal";
+		} else if (using_ce020 == 1) {
+			/* x_ not used if it redirects to
+			 * get_word_ce020_prefetch()
+			 */
+			disp020 = "x_get_disp_ea_ce020";
+			prefetch_word = "get_word_ce020_prefetch";
+			prefetch_long = "get_long_ce020_prefetch";
+			srcli = "x_get_ilong";
+			srcwi = "x_get_iword";
+			srcbi = "x_get_ibyte";
+			srcl = "x_get_long";
+			dstl = "x_put_long";
+			srcw = "x_get_word";
+			dstw = "x_put_word";
+			srcb = "x_get_byte";
+			dstb = "x_put_byte";
+			do_cycles = "do_cycles_ce020_internal";
+			nextw = "next_iword_020ce";
+			nextl = "next_ilong_020ce";
+		} else if (using_ce020 == 2) {
+			// 68030 CE
+			disp020 = "x_get_disp_ea_ce030";
+			prefetch_long = "get_long_ce030_prefetch";
+			prefetch_word = "get_word_ce030_prefetch";
+			srcli = "x_get_ilong";
+			srcwi = "x_get_iword";
+			srcbi = "x_get_ibyte";
+			srcl = "x_get_long";
+			dstl = "x_put_long";
+			srcw = "x_get_word";
+			dstw = "x_put_word";
+			srcb = "x_get_byte";
+			dstb = "x_put_byte";
+			do_cycles = "do_cycles_ce020_internal";
+			nextw = "next_iword_030ce";
+			nextl = "next_ilong_030ce";
+		} else if (using_ce020 == 3) {
+			// 68040/060 CE
+			disp020 = "x_get_disp_ea_040";
+			prefetch_long = "get_ilong_cache_040";
+			prefetch_word = "get_iword_cache_040";
+			srcli = "x_get_ilong";
+			srcwi = "x_get_iword";
+			srcbi = "x_get_ibyte";
+			srcl = "x_get_long";
+			dstl = "x_put_long";
+			srcw = "x_get_word";
+			dstw = "x_put_word";
+			srcb = "x_get_byte";
+			dstb = "x_put_byte";
+			do_cycles = "do_cycles_ce020_internal";
+			nextw = "next_iword_cache040";
+			nextl = "next_ilong_cache040";
+		} else if (using_prefetch_020 == 1) {
+			disp020 = "x_get_disp_ea_020";
+			prefetch_word = "get_word_020_prefetch";
+			prefetch_long = "get_long_020_prefetch";
+			srcli = "x_get_ilong";
+			srcwi = "x_get_iword";
+			srcbi = "x_get_ibyte";
+			srcl = "x_get_long";
+			dstl = "x_put_long";
+			srcw = "x_get_word";
+			dstw = "x_put_word";
+			srcb = "x_get_byte";
+			dstb = "x_put_byte";
+			nextw = "next_iword_020_prefetch";
+			nextl = "next_ilong_020_prefetch";
+		} else if (using_prefetch_020 == 2) {
+			disp020 = "x_get_disp_ea_020";
+			prefetch_word = "get_word_030_prefetch";
+			prefetch_long = "get_long_030_prefetch";
+			srcli = "x_get_ilong";
+			srcwi = "x_get_iword";
+			srcbi = "x_get_ibyte";
+			srcl = "x_get_long";
+			dstl = "x_put_long";
+			srcw = "x_get_word";
+			dstw = "x_put_word";
+			srcb = "x_get_byte";
+			dstb = "x_put_byte";
+			nextw = "next_iword_030_prefetch";
+			nextl = "next_ilong_030_prefetch";
+		}
+#if 0
+	} else if (using_ce020) {
+		disp020 = "x_get_disp_ea_020";
+		do_cycles = "do_cycles_ce020";
+		if (using_ce020 == 2) {
+			// 68030/40/60 CE
+			prefetch_long = "get_long_ce030_prefetch";
+			prefetch_word = "get_word_ce030_prefetch";
+			nextw = "next_iword_030ce";
+			nextl = "next_ilong_030ce";
+			srcli = "get_word_ce030_prefetch";
+			srcwi = "get_long_ce030_prefetch";
+			srcl = "get_long_ce030";
+			dstl = "put_long_ce030";
+			srcw = "get_word_ce030";
+			dstw = "put_word_ce030";
+			srcb = "get_byte_ce030";
+			dstb = "put_byte_ce030";
+		} else {
+			// 68020 CE
+			prefetch_long = "get_long_ce020_prefetch";
+			prefetch_word = "get_word_ce020_prefetch";
+			nextw = "next_iword_020ce";
+			nextl = "next_ilong_020ce";
+			srcli = "get_word_ce020_prefetch";
+			srcwi = "get_long_ce020_prefetch";
+			srcl = "get_long_ce020";
+			dstl = "put_long_ce020";
+			srcw = "get_word_ce020";
+			dstw = "put_word_ce020";
+			srcb = "get_byte_ce020";
+			dstb = "put_byte_ce020";
+		}
+#endif
+	} else if (using_mmu == 68030) {
+		// 68030 MMU
+		disp020 = "get_disp_ea_020_mmu030";
+		prefetch_long = "get_ilong_mmu030_state";
+		prefetch_word = "get_iword_mmu030_state";
+		nextw = "next_iword_mmu030_state";
+		nextl = "next_ilong_mmu030_state";
+		srcli = "get_ilong_mmu030_state";
+		srcwi = "get_iword_mmu030_state";
+		srcbi = "get_ibyte_mmu030_state";
+		srcl = "get_long_mmu030_state";
+		dstl = "put_long_mmu030_state";
+		srcw = "get_word_mmu030_state";
+		dstw = "put_word_mmu030_state";
+		srcb = "get_byte_mmu030_state";
+		dstb = "put_byte_mmu030_state";
+		srcblrmw = "get_lrmw_byte_mmu030_state";
+		srcwlrmw = "get_lrmw_word_mmu030_state";
+		srcllrmw = "get_lrmw_long_mmu030_state";
+		dstblrmw = "put_lrmw_byte_mmu030_state";
+		dstwlrmw = "put_lrmw_word_mmu030_state";
+		dstllrmw = "put_lrmw_long_mmu030_state";
+		srcld = "get_long_mmu030";
+		srcwd = "get_word_mmu030";
+		dstld = "put_long_mmu030";
+		dstwd = "put_word_mmu030";
+		getpc = "m68k_getpci ()";
+	} else if (using_mmu == 68040) {
+		// 68040 MMU
+		disp020 = "x_get_disp_ea_020";
+		prefetch_long = "get_ilong_mmu040";
+		prefetch_word = "get_iword_mmu040";
+		nextw = "next_iword_mmu040";
+		nextl = "next_ilong_mmu040";
+		srcli = "get_ilong_mmu040";
+		srcwi = "get_iword_mmu040";
+		srcbi = "get_ibyte_mmu040";
+		srcl = "get_long_mmu040";
+		dstl = "put_long_mmu040";
+		srcw = "get_word_mmu040";
+		dstw = "put_word_mmu040";
+		srcb = "get_byte_mmu040";
+		dstb = "put_byte_mmu040";
+		srcblrmw = "get_lrmw_byte_mmu040";
+		srcwlrmw = "get_lrmw_word_mmu040";
+		srcllrmw = "get_lrmw_long_mmu040";
+		dstblrmw = "put_lrmw_byte_mmu040";
+		dstwlrmw = "put_lrmw_word_mmu040";
+		dstllrmw = "put_lrmw_long_mmu040";
+		getpc = "m68k_getpci ()";
+	} else if (using_mmu) {
+		// 68060 MMU
+		disp020 = "x_get_disp_ea_020";
+		prefetch_long = "get_ilong_mmu060";
+		prefetch_word = "get_iword_mmu060";
+		nextw = "next_iword_mmu060";
+		nextl = "next_ilong_mmu060";
+		srcli = "get_ilong_mmu060";
+		srcwi = "get_iword_mmu060";
+		srcbi = "get_ibyte_mmu060";
+		srcl = "get_long_mmu060";
+		dstl = "put_long_mmu060";
+		srcw = "get_word_mmu060";
+		dstw = "put_word_mmu060";
+		srcb = "get_byte_mmu060";
+		dstb = "put_byte_mmu060";
+		srcblrmw = "get_lrmw_byte_mmu060";
+		srcwlrmw = "get_lrmw_word_mmu060";
+		srcllrmw = "get_lrmw_long_mmu060";
+		dstblrmw = "put_lrmw_byte_mmu060";
+		dstwlrmw = "put_lrmw_word_mmu060";
+		dstllrmw = "put_lrmw_long_mmu060";
+		// 68060 only: also non-locked read-modify-write accesses are reported
+		srcbrmw = "get_rmw_byte_mmu060";
+		srcwrmw = "get_rmw_word_mmu060";
+		srclrmw = "get_rmw_long_mmu060";
+		dstbrmw = "put_rmw_byte_mmu060";
+		dstwrmw = "put_rmw_word_mmu060";
+		dstlrmw = "put_rmw_long_mmu060";
+		getpc = "m68k_getpci ()";
+	} else if (using_ce) {
+		// 68000 ce
+		prefetch_word = "get_word_ce000_prefetch";
+		srcwi = "get_wordi_ce000";
+		srcl = "get_long_ce000";
+		dstl = "put_long_ce000";
+		srcw = "get_word_ce000";
+		dstw = "put_word_ce000";
+		srcb = "get_byte_ce000";
+		dstb = "put_byte_ce000";
+		do_cycles = "do_cycles_ce000";
+		getpc = "m68k_getpci ()";
+	} else if (using_prefetch) {
+		// 68000 prefetch
+		prefetch_word = "get_word_prefetch";
+		prefetch_long = "get_long_prefetch";
+		srcwi = "get_wordi_prefetch";
+		srcl = "get_long_prefetch";
+		dstl = "put_long_prefetch";
+		srcw = "get_word_prefetch_addr";
+		dstw = "put_word_prefetch";
+		srcb = "get_byte_prefetch";
+		dstb = "put_byte_prefetch";
+		getpc = "m68k_getpci ()";
+	} else {
+		// generic + direct
+		prefetch_long = "get_dilong";
+		prefetch_word = "get_diword";
+		nextw = "next_diword";
+		nextl = "next_dilong";
+		srcli = "get_dilong";
+		srcwi = "get_diword";
+		srcbi = "get_dibyte";
+		srcl = "get_long";
+		dstl = "put_long";
+		srcw = "get_word";
+		dstw = "put_word";
+		srcb = "get_byte";
+		dstb = "put_byte";
+	}
+	if (!dstld)
+		dstld = dstl;
+	if (!dstwd)
+		dstwd = dstw;
+	if (!srcld)
+		srcld = srcl;
+	if (!srcwd)
+		srcwd = srcw;
+	if (!srcblrmw) {
+		srcblrmw = srcb;
+		srcwlrmw = srcw;
+		srcllrmw = srcl;
+		dstblrmw = dstb;
+		dstwlrmw = dstw;
+		dstllrmw = dstl;
+	}
+
+}
+
+static void gen_opcode (unsigned int opcode)
+{
+	struct instr *curi = table68k + opcode;
+
+	resetvars ();
+
+#ifdef WINUAE_FOR_HATARI
+        /* Hatari : Store the family of the instruction (used to check for pairing on ST,
+         * for non-CPU cycles calculation and profiling)
+         */
+        printf ("\tOpcodeFamily = %d;\n", curi->mnemo);
+        /* leave some space for patching in the current cycles later */
+        if (!using_ce020) {
+                printf("\tCurrentInstrCycles =     \n");
+                nCurInstrCycPos = ftell(stdout) - 5;
+        }
+#endif
+
+	start_brace ();
+
+	m68k_pc_offset = 2;
+
+	switch (curi->plev) {
+	case 0: /* not privileged */
+		break;
+	case 1: /* unprivileged only on 68000 */
+		if (cpu_level == 0)
+			break;
+		if (next_cpu_level < 0)
+			next_cpu_level = 0;
+
+		/* fall through */
+	case 2: /* priviledged */
+		printf ("if (!regs.s) { Exception (8); goto %s; }\n", endlabelstr);
+		need_endlabel = 1;
+		start_brace ();
+		break;
+	case 3: /* privileged if size == word */
+		if (curi->size == sz_byte)
+			break;
+		printf ("if (!regs.s) { Exception (8); goto %s; }\n", endlabelstr);
+		need_endlabel = 1;
+		start_brace ();
+		break;
+	}
+	switch (curi->mnemo) {
+	case i_OR:
+	case i_AND:
+	case i_EOR:
+	{
+		// documentaion error: and.l #imm,dn = 2 idle, not 1 idle (same as OR and EOR)
+		int c = 0;
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "src", 1, 0,
+			curi->dmode, "dstreg", curi->size, "dst", 1, GF_RMW);
+//		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+//		genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_RMW);
+		printf ("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
+		genflags (flag_logical, curi->size, "src", "", "");
+		if (curi->dmode == Dreg && curi->size == sz_long) {
+			c += 2;
+			if (curi->smode == imm || curi->smode == Dreg)
+				c += 2;
+		}
+		fill_prefetch_next ();
+		if (c > 0)
+			addcycles000 (c);
+		genastore_rev ("src", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+	}
+	// all SR/CCR modifications does full prefetch
+	case i_ORSR:
+	case i_EORSR:
+		printf ("\tMakeSR ();\n");
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		if (curi->size == sz_byte) {
+			printf ("\tsrc &= 0xFF;\n");
+		}
+		addcycles000 (8);
+		if (cpu_level <= 1) {
+			sync_m68k_pc ();
+			fill_prefetch_full ();
+		} else {
+			fill_prefetch_next ();
+		}
+		printf ("\tregs.sr %c= src;\n", curi->mnemo == i_EORSR ? '^' : '|');
+		makefromsr ();
+		break;
+	case i_ANDSR:
+		printf ("\tMakeSR ();\n");
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		if (curi->size == sz_byte) {
+			printf ("\tsrc |= 0xFF00;\n");
+		}
+		addcycles000 (8);
+		if (cpu_level <= 1) {
+			sync_m68k_pc ();
+			fill_prefetch_full ();
+		} else {
+			fill_prefetch_next ();
+		}
+		printf ("\tregs.sr &= src;\n");
+		makefromsr ();
+		break;
+	case i_SUB:
+	{
+		int c = 0;
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "src", 1, 0,
+			curi->dmode, "dstreg", curi->size, "dst", 1, GF_RMW);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_RMW);
+		if (curi->dmode == Dreg) {
+			if (curi->size == sz_long) {
+				c += 2;
+				if (curi->smode == imm || curi->smode == immi || curi->smode == Dreg || curi->smode == Areg)
+					c += 2;
+			}
+		}
+		fill_prefetch_next ();
+		if (c > 0)
+			addcycles000 (c);
+		start_brace ();
+		genflags (flag_sub, curi->size, "newv", "src", "dst");
+		genastore_rev ("newv", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+	}
+	case i_SUBA:
+	{
+		int c = 0;
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "src", 1, 0,
+			curi->dmode, "dstreg", sz_long, "dst", 1, GF_RMW);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", sz_long, "dst", 1, 0, GF_RMW);
+		if (curi->smode == immi) {
+			// SUBAQ.x is always 8 cycles
+			c += 4;
+		} else {
+			c = curi->size == sz_long ? 2 : 4;
+			if (islongimm (curi))
+				c += 2;
+		}
+		fill_prefetch_next ();
+		if (c > 0)
+			addcycles000 (c);
+		start_brace ();
+		printf ("\tuae_u32 newv = dst - src;\n");
+		genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
+		break;
+	}
+	case i_SUBX:
+		if (!isreg (curi->smode))
+			addcycles000 (2);
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
+		genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA | GF_RMW);
+		fill_prefetch_next ();
+		if (curi->size == sz_long && isreg (curi->smode))
+			addcycles000 (4);
+		start_brace ();
+		printf ("\tuae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);\n");
+		genflags (flag_subx, curi->size, "newv", "src", "dst");
+		genflags (flag_zn, curi->size, "newv", "", "");
+		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+	case i_SBCD:
+		if (!isreg (curi->smode))
+			addcycles000 (2);
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
+		genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA | GF_RMW);
+		fill_prefetch_next ();
+		start_brace ();
+		printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
+		printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
+		printf ("\tuae_u16 newv, tmp_newv;\n");
+		printf ("\tint bcd = 0;\n");
+		printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
+		printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
+		printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
+		printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);\n");
+		duplicate_carry (0);
+		/* Manual says bits NV are undefined though a real 68040/060 don't change them */
+		if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
+			if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
+				next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
+			genflags (flag_z, curi->size, "newv", "", "");
+		} else {
+			genflags (flag_zn, curi->size, "newv", "", "");
+			printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
+		}
+		if (isreg (curi->smode)) {
+			addcycles000 (2);
+		}
+		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+	case i_ADD:
+	{
+		int c = 0;
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "src", 1, 0,
+			curi->dmode, "dstreg", curi->size, "dst", 1, GF_RMW);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_RMW);
+		if (curi->dmode == Dreg) {
+			if (curi->size == sz_long) {
+				c += 2;
+				if (curi->smode == imm || curi->smode == immi || curi->smode == Dreg || curi->smode == Areg)
+					c += 2;
+			}
+		}
+		fill_prefetch_next ();
+		if (c > 0)
+			addcycles000 (c);
+		start_brace ();
+		genflags (flag_add, curi->size, "newv", "src", "dst");
+		genastore_rev ("newv", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+	}
+	case i_ADDA:
+	{
+		int c = 0;
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "src", 1, 0,
+			curi->dmode, "dstreg", sz_long, "dst", 1, GF_RMW);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", sz_long, "dst", 1, 0, GF_RMW);
+		if (curi->smode == immi) {
+			// ADDAQ.x is always 8 cycles
+			c += 4;
+		} else {
+			c = curi->size == sz_long ? 2 : 4;
+			if (islongimm (curi))
+				c += 2;
+		}
+		fill_prefetch_next ();
+		if (c > 0)
+			addcycles000 (c);
+		start_brace ();
+		printf ("\tuae_u32 newv = dst + src;\n");
+		genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
+		break;
+	}
+	case i_ADDX:
+		if (!isreg (curi->smode))
+			addcycles000 (2);
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
+		genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA | GF_RMW);
+		fill_prefetch_next ();
+		if (curi->size == sz_long && isreg (curi->smode))
+			addcycles000 (4);
+		start_brace ();
+		printf ("\tuae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);\n");
+		genflags (flag_addx, curi->size, "newv", "src", "dst");
+		genflags (flag_zn, curi->size, "newv", "", "");
+		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+	case i_ABCD:
+		if (!isreg (curi->smode))
+			addcycles000 (2);
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
+		genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA | GF_RMW);
+		fill_prefetch_next ();
+		start_brace ();
+		printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);\n");
+		printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
+		printf ("\tuae_u16 newv, tmp_newv;\n");
+		printf ("\tint cflg;\n");
+		printf ("\tnewv = tmp_newv = newv_hi + newv_lo;");
+		printf ("\tif (newv_lo > 9) { newv += 6; }\n");
+		printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
+		printf ("\tif (cflg) newv += 0x60;\n");
+		printf ("\tSET_CFLG (cflg);\n");
+		duplicate_carry (0);
+		/* Manual says bits NV are undefined though a real 68040 don't change them */
+		if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
+			if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
+				next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
+			genflags (flag_z, curi->size, "newv", "", "");
+		}
+		else {
+			genflags (flag_zn, curi->size, "newv", "", "");
+			printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
+		}
+		if (isreg (curi->smode)) {
+			addcycles000 (2);
+		}
+		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+	case i_NEG:
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		if (isreg (curi->smode) && curi->size == sz_long)
+			addcycles000 (2);
+		start_brace ();
+		genflags (flag_sub, curi->size, "dst", "src", "0");
+		genastore_rev ("dst", curi->smode, "srcreg", curi->size, "src");
+		break;
+	case i_NEGX:
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		if (isreg (curi->smode) && curi->size == sz_long)
+			addcycles000 (2);
+		start_brace ();
+		printf ("\tuae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);\n");
+		genflags (flag_subx, curi->size, "newv", "src", "0");
+		genflags (flag_zn, curi->size, "newv", "", "");
+		genastore_rev ("newv", curi->smode, "srcreg", curi->size, "src");
+		break;
+	case i_NBCD:
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_RMW);
+		if (isreg (curi->smode))
+			addcycles000 (2);
+		fill_prefetch_next ();
+		start_brace ();
+		printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
+		printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
+		printf ("\tuae_u16 newv;\n");
+#ifndef WINUAE_FOR_HATARI
+		printf ("\tint cflg, tmp_newv;\n");
+		printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
+		printf ("\ttmp_newv = newv = newv_hi + newv_lo;\n");
+#else
+		/* Hatari : use 2 cases to avoid 'tmp_newv' set but not used */
+		if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
+			printf ("\tint cflg;\n");
+			printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
+			printf ("\tnewv = newv_hi + newv_lo;\n");
+		}
+		else {
+			printf ("\tint cflg, tmp_newv;\n");
+			printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
+			printf ("\ttmp_newv = newv = newv_hi + newv_lo;\n");
+		}
+#endif
+		printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
+		printf ("\tif (cflg) newv -= 0x60;\n");
+		printf ("\tSET_CFLG (cflg);\n");
+		duplicate_carry(0);
+		/* Manual says bits NV are undefined though a real 68040 don't change them */
+		if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
+			if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
+				next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
+			genflags (flag_z, curi->size, "newv", "", "");
+		}
+		else {
+			genflags (flag_zn, curi->size, "newv", "", "");
+			printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
+		}
+		genastore ("newv", curi->smode, "srcreg", curi->size, "src");
+		break;
+	case i_CLR:
+		next_level_000 ();
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", cpu_level == 0 ? 1 : 2, 0, 0);
+		fill_prefetch_next ();
+		if (isreg (curi->smode) && curi->size == sz_long)
+			addcycles000 (2);
+		genflags (flag_logical, curi->size, "0", "", "");
+		genastore_rev ("0", curi->smode, "srcreg", curi->size, "src");
+		break;
+	case i_NOT:
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		if (isreg (curi->smode) && curi->size == sz_long)
+			addcycles000 (2);
+		start_brace ();
+		printf ("\tuae_u32 dst = ~src;\n");
+		genflags (flag_logical, curi->size, "dst", "", "");
+		genastore_rev ("dst", curi->smode, "srcreg", curi->size, "src");
+		break;
+	case i_TST:
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		fill_prefetch_next ();
+		genflags (flag_logical, curi->size, "src", "", "");
+		break;
+	case i_BTST:
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "src", 1, 0,
+			curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_IR2IRC);
+		fill_prefetch_next ();
+		bsetcycles (curi);
+		printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
+		break;
+	case i_BCHG:
+	case i_BCLR:
+	case i_BSET:
+		// on 68000 these have weird side-effect, if EA points to write-only custom register
+		//during instruction's read access CPU data lines appear as zero to outside world,
+		// (normally previously fetched data appears in data lines if reading write-only register)
+		// this allows stupid things like bset #2,$dff096 to work "correctly"
+		// NOTE: above can't be right.
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "src", 1, 0,
+			curi->dmode, "dstreg", curi->size, "dst", 1, GF_RMW);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_IR2IRC | GF_RMW);
+		fill_prefetch_next ();
+		bsetcycles (curi);
+		// bclr needs 1 extra cycle
+		if (curi->mnemo == i_BCLR && curi->dmode == Dreg)
+			addcycles000 (2);
+		if (curi->mnemo == i_BCHG) {
+			printf ("\tdst ^= (1 << src);\n");
+			printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
+		} else if (curi->mnemo == i_BCLR) {
+			printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
+			printf ("\tdst &= ~(1 << src);\n");
+		} else if (curi->mnemo == i_BSET) {
+			printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
+			printf ("\tdst |= (1 << src);\n");
+		}
+		genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+	case i_CMPM:
+		// confirmed
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "src", 1, GF_AA,
+			curi->dmode, "dstreg", curi->size, "dst", 1, GF_AA);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
+		fill_prefetch_next ();
+		start_brace ();
+		genflags (flag_cmp, curi->size, "newv", "src", "dst");
+		break;
+	case i_CMP:
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "src", 1, 0,
+			curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
+		fill_prefetch_next ();
+		if (curi->dmode == Dreg && curi->size == sz_long)
+			addcycles000 (2);
+		start_brace ();
+		genflags (flag_cmp, curi->size, "newv", "src", "dst");
+		break;
+	case i_CMPA:
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "src", 1, 0,
+			curi->dmode, "dstreg", sz_long, "dst", 1, 0);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
+		fill_prefetch_next ();
+		addcycles000 (2);
+		start_brace ();
+		genflags (flag_cmp, sz_long, "newv", "src", "dst");
+		break;
+		/* The next two are coded a little unconventional, but they are doing
+		* weird things... */
+	case i_MVPRM: // MOVEP R->M
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		printf ("\tuaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
+#ifndef WINUAE_FOR_HATARI
+		if (curi->size == sz_word) {
+			printf ("\t%s (memp, src >> 8);\n\t%s (memp + 2, src);\n", dstb, dstb);
+			count_write += 2;
+		} else {
+			printf ("\t%s (memp, src >> 24);\n\t%s (memp + 2, src >> 16);\n", dstb, dstb);
+			printf ("\t%s (memp + 4, src >> 8);\n\t%s (memp + 6, src);\n", dstb, dstb);
+			count_write += 4;
+		}
+#else
+		/* Hatari : Use MovepByteNbr to keep track of each individual byte access inside a movep */
+		if (curi->size == sz_word) {
+			printf ("\tMovepByteNbr=1; \t%s (memp, src >> 8);\n\tMovepByteNbr=2; \t%s (memp + 2, src);\n", dstb, dstb);
+			count_write += 2;
+		} else {
+			printf ("\tMovepByteNbr=1; \t%s (memp, src >> 24);\n\tMovepByteNbr=2; \t%s (memp + 2, src >> 16);\n", dstb, dstb);
+			printf ("\tMovepByteNbr=3; \t%s (memp + 4, src >> 8);\n\tMovepByteNbr=4; \t%s (memp + 6, src);\n", dstb, dstb);
+			count_write += 4;
+		}
+		printf ("\tMovepByteNbr=0;\n");
+#endif
+		fill_prefetch_next ();
+		break;
+	case i_MVPMR: // MOVEP M->R
+		printf ("\tuaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
+		genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
+#ifndef WINUAE_FOR_HATARI
+		if (curi->size == sz_word) {
+			printf ("\tuae_u16 val = ((%s (memp) & 0xff) << 8) + (%s (memp + 2) & 0xff);\n", srcb, srcb);
+			count_read += 2;
+		} else {
+			printf ("\tuae_u32 val = ((%s (memp) & 0xff) << 24) + ((%s (memp + 2) & 0xff) << 16)\n", srcb, srcb);
+			printf ("              + ((%s (memp + 4) & 0xff) << 8) + (%s (memp + 6) & 0xff);\n", srcb, srcb);
+			count_read += 4;
+		}
+#else
+		/* Hatari : Use MovepByteNbr to keep track of each individual byte access inside a movep */
+		if (curi->size == sz_word) {
+			printf ("\tuae_u16 val;\n");
+			printf ("\tMovepByteNbr=1; val = ((%s (memp) & 0xff) << 8);\n", srcb);
+			printf ("\tMovepByteNbr=2; val += (%s (memp + 2) & 0xff);\n", srcb);
+			count_read += 2;
+		} else {
+			printf ("\tuae_u32 val;\n");
+			printf ("\tMovepByteNbr=1; val = ((%s (memp) & 0xff) << 24);\n", srcb);
+			printf ("\tMovepByteNbr=2; val += ((%s (memp + 2) & 0xff) << 16);\n", srcb);
+			printf ("\tMovepByteNbr=3; val += ((%s (memp + 4) & 0xff) << 8);\n", srcb);
+			printf ("\tMovepByteNbr=4; val += (%s (memp + 6) & 0xff);\n", srcb);
+			count_read += 4;
+		}
+		printf ("\tMovepByteNbr=0;\n");
+#endif
+		fill_prefetch_next ();
+		genastore ("val", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+	case i_MOVE:
+	case i_MOVEA:
+		{
+			/* 2 MOVE instruction variants have special prefetch sequence:
+			* - MOVE ,-(An) = prefetch is before writes (Apdi)
+			* - MOVE memory,(xxx).L = 2 prefetches after write
+			* - move.x #imm = prefetch is done before write
+			* - all others = prefetch is done after writes
+			*
+			* - move.x xxx,[at least 1 extension word here] = fetch 1 extension word before (xxx)
+			*
+			*/
+			if (isce020()) {
+				// MOVE is too complex to handle in table68k
+				int h = 0, t = 0, c = 0, subhead = 0;
+				bool fea = false;
+				if (curi->smode == immi && isreg (curi->dmode)) {
+					// MOVEQ
+					h = 2; t = 0; c = 0;
+				} else if (isreg (curi->smode) && isreg (curi->dmode)) {
+					// MOVE Rn,Rn
+					h = 2; t = 0; c = 2;
+				} else if (isreg (curi->dmode)) {
+					// MOVE EA,Rn
+					h = 0; t = 0; c = 2;
+					fea = true;
+				} else if (curi->dmode == Aind) {
+					if (isreg (curi->smode)) {
+						// MOVE Rn,(An)
+						h = 0; t = 1; c = 3;
+					} else {
+						// MOVE SOURCE,(An)
+						h = 2; t = 0; c = 4;
+						fea = true;
+					}
+				} else if (curi->dmode == Aipi) {
+					if (isreg (curi->smode)) {
+						// MOVE Rn,(An)+
+						h = 0; t = 1; c = 3;
+					} else {
+						// MOVE SOURCE,(An)+
+						h = 2; t = 0; c = 4;
+						fea = true;
+					}
+				} else if (curi->dmode == Apdi) {
+					if (isreg (curi->smode)) {
+						// MOVE Rn,-(An)
+						h = 0; t = 2; c = 4;
+					} else {
+						// MOVE SOURCE,-(An)
+						h = 2; t = 0; c = 4;
+						fea = true;
+					}
+				} else if (curi->dmode == Ad16) {
+					// MOVE EA,(d16,An)
+					h = 2; t = 0; c = 4;
+					fea = true;
+				} else if (curi->dmode == Ad8r) {
+					h = 4; t = 0; c = 6;
+					fea = true;
+				} else if (curi->dmode == absw) {
+					// MOVE EA,xxx.W
+					h = 2; t = 0; c = 4;
+					fea = true;
+				} else if (curi->dmode == absl) {
+					// MOVE EA,xxx.L
+					h = 0; t = 0; c = 6;
+					fea = true;
+				} else {
+					h = 4; t = 0; c = 6;
+					fea = true;
+				}
+				if (fea) {
+					if (curi->smode == imm)
+						subhead = gence020cycles_fiea (curi, curi->size, Dreg);
+					else
+						subhead = gence020cycles_fea (curi->smode);
+				}
+				genamode2x (curi->smode, "srcreg", curi->size, "src", 1, 0, 0, fea ? fetchmode_fea : -1);
+				genamode2 (curi->dmode, "dstreg", curi->size, "dst", 2, 0, GF_MOVE);
+				addopcycles_ce20 (h, t, c, -subhead);
+				if (curi->mnemo == i_MOVEA && curi->size == sz_word)
+					printf ("\tsrc = (uae_s32)(uae_s16)src;\n");
+				if (curi->mnemo == i_MOVE)
+					genflags (flag_logical, curi->size, "src", "", "");
+				genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
+				sync_m68k_pc ();
+
+			} else {
+				int prefetch_done = 0, flags;
+				int dualprefetch = curi->dmode == absl && (curi->smode != Dreg && curi->smode != Areg && curi->smode != imm);
+				genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+				flags = GF_MOVE | GF_APDI;
+				//if (curi->size == sz_long && (curi->smode == Dreg || curi->smode == Areg))
+				//	flags &= ~GF_APDI;
+				flags |= dualprefetch ? GF_NOREFILL : 0;
+				genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, flags);
+				if (curi->mnemo == i_MOVEA && curi->size == sz_word)
+					printf ("\tsrc = (uae_s32)(uae_s16)src;\n");
+				if (curi->dmode == Apdi) {
+					fill_prefetch_next ();
+					prefetch_done = 1;
+				}
+				if (curi->mnemo == i_MOVE)
+					genflags (flag_logical, curi->size, "src", "", "");
+
+				if (curi->size == sz_long) {
+					if ((curi->dmode == Ad16 || curi->dmode == PC16) && curi->smode == imm) {
+						// lots more needed..
+						// move.l x,absl
+						// move.l (an),x(an)
+						single_check_ipl();
+					}
+				}
+				genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
+				sync_m68k_pc ();
+				if (dualprefetch) {
+					fill_prefetch_full_000 ();
+					prefetch_done = 1;
+				}
+				if (!prefetch_done)
+					fill_prefetch_next ();
+			}
+		}
+		break;
+	case i_MVSR2: // MOVE FROM SR
+		genamode (curi, curi->smode, "srcreg", sz_word, "src", 2, 0, 0);
+		if (isreg (curi->smode)) {
+			fill_prefetch_next ();
+			addcycles000 (2);
+		} else {
+			// write to memory, dummy write to same address, X-flag seems to be always set
+			if (cpu_level <= 1 && curi->size == sz_word) {
+				printf ("\t%s (srca, regs.sr | 0x0010);\n", dstw);
+				count_write++;
+			}
+			fill_prefetch_next ();
+		}
+		printf ("\tMakeSR ();\n");
+		// real write
+		if (curi->size == sz_byte)
+			genastore ("regs.sr & 0xff", curi->smode, "srcreg", sz_word, "src");
+		else
+			genastore ("regs.sr", curi->smode, "srcreg", sz_word, "src");
+		break;
+	case i_MV2SR: // MOVE TO SR
+		genamode (curi, curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
+		if (curi->size == sz_byte) {
+			// MOVE TO CCR
+			addcycles000 (4);
+			printf ("\tMakeSR ();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
+		} else {
+			// MOVE TO SR
+			addcycles000 (4);
+			printf ("\tregs.sr = src;\n");
+		}
+		makefromsr ();
+		if (cpu_level <= 1) {
+			// 68000 does 2xprefetch
+			sync_m68k_pc ();
+			fill_prefetch_full ();
+		} else {
+			fill_prefetch_next ();
+		}
+		break;
+	case i_SWAP:
+		genamode (curi, curi->smode, "srcreg", sz_long, "src", 1, 0, 0);
+		fill_prefetch_next ();
+		start_brace ();
+		printf ("\tuae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
+		genflags (flag_logical, sz_long, "dst", "", "");
+		genastore ("dst", curi->smode, "srcreg", sz_long, "src");
+		break;
+	case i_EXG:
+		// confirmed
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "src", 1, 0,
+			curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
+		fill_prefetch_next ();
+		addcycles000 (2);
+		genastore ("dst", curi->smode, "srcreg", curi->size, "src");
+		genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+	case i_EXT:
+		// confirmed
+		genamode (curi, curi->smode, "srcreg", sz_long, "src", 1, 0, 0);
+		fill_prefetch_next ();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u32 dst = (uae_s32)(uae_s8)src;\n"); break;
+		case sz_word: printf ("\tuae_u16 dst = (uae_s16)(uae_s8)src;\n"); break;
+		case sz_long: printf ("\tuae_u32 dst = (uae_s32)(uae_s16)src;\n"); break;
+		default: term ();
+		}
+		genflags (flag_logical,
+			curi->size == sz_word ? sz_word : sz_long, "dst", "", "");
+		genastore ("dst", curi->smode, "srcreg",
+			curi->size == sz_word ? sz_word : sz_long, "src");
+		break;
+	case i_MVMEL:
+		// confirmed
+		if (using_ce || using_prefetch)
+			genmovemel_ce (opcode);
+		else
+			genmovemel (opcode);
+		tail_ce020_done = true;
+		break;
+	case i_MVMLE:
+		// confirmed
+		if (using_ce || using_prefetch)
+			genmovemle_ce (opcode);
+		else
+			genmovemle (opcode);
+		tail_ce020_done = true;
+		break;
+	case i_TRAP:
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		gen_set_fault_pc ();
+		sync_m68k_pc ();
+		printf ("\tException (src + 32);\n");
+		did_prefetch = 1;
+		branch_inst = 2;
+		clear_m68k_offset();
+		break;
+	case i_MVR2USP:
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		fill_prefetch_next ();
+		printf ("\tregs.usp = src;\n");
+		break;
+	case i_MVUSP2R:
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 2, 0, 0);
+		fill_prefetch_next ();
+		genastore ("regs.usp", curi->smode, "srcreg", curi->size, "src");
+		break;
+	case i_RESET:
+		fill_prefetch_next ();
+		printf ("\tcpureset ();\n");
+		sync_m68k_pc ();
+		addcycles000 (128);
+		if (using_prefetch) {
+			printf ("\t%s (2);\n", prefetch_word);
+			clear_m68k_offset();
+		}
+		break;
+	case i_NOP:
+		fill_prefetch_next ();
+		break;
+	case i_STOP:
+		if (using_prefetch) {
+			printf ("\tregs.sr = regs.irc;\n");
+			m68k_pc_offset += 2;
+		} else {
+			genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+			printf ("\tregs.sr = src;\n");
+		}
+		addcycles000(4);
+		makefromsr ();
+		printf ("\tm68k_setstopped ();\n");
+		sync_m68k_pc ();
+		// STOP does not prefetch anything
+		did_prefetch = -1;
+		break;
+	case i_LPSTOP: /* 68060 */
+		printf ("\tuae_u16 sw = %s (2);\n", srcwi);
+		printf ("\tuae_u16 sr;\n");
+		printf ("\tif (sw != (0x100|0x80|0x40)) { Exception (4); goto %s; }\n", endlabelstr);
+		printf ("\tsr = %s (4);\n", srcwi);
+		printf ("\tif (!(sr & 0x8000)) { Exception (8); goto %s; }\n", endlabelstr);
+		printf ("\tregs.sr = sr;\n");
+		makefromsr ();
+		printf ("\tm68k_setstopped();\n");
+		m68k_pc_offset += 4;
+		sync_m68k_pc ();
+		fill_prefetch_full ();
+		break;
+	case i_RTE:
+		addop_ce020 (curi, 0);
+		next_level_000 ();
+		if (cpu_level == 0) {
+			genamode (NULL, Aipi, "7", sz_word, "sr", 1, 0, GF_NOREFILL);
+			genamode (NULL, Aipi, "7", sz_long, "pc", 1, 0, GF_NOREFILL);
+			printf ("\tregs.sr = sr;\n");
+			printf ("\tif (pc & 1) {\n");
+			printf ("\t\texception3i (0x%04X, pc);\n", opcode);
+			printf ("\t\tgoto %s;\n", endlabelstr);
+			printf ("\t}\n");
+			setpc ("pc");
+			makefromsr ();
+		} else if (cpu_level == 1 && using_prefetch) {
+		    int old_brace_level = n_braces;
+			printf ("\tuae_u16 newsr; uae_u32 newpc;\n");
+			printf ("\tfor (;;) {\n");
+			printf ("\t\tuaecptr a = m68k_areg (regs, 7);\n");
+			printf ("\t\tuae_u16 sr = %s (a);\n", srcw);
+			count_read++;
+			printf ("\t\tuae_u32 pc = %s (a + 2) << 16; pc |= %s (a + 4);\n", srcw, srcw);
+			count_read += 2;
+			printf ("\t\tuae_u16 format = %s (a + 2 + 4);\n", srcw);
+			count_read++;
+			printf ("\t\tint frame = format >> 12;\n");
+			printf ("\t\tint offset = 8;\n");
+			printf ("\t\tnewsr = sr; newpc = pc;\n");
+		    printf ("\t\tif (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }\n");
+		    printf ("\t\telse if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }\n");
+		    printf ("\t\telse { m68k_areg (regs, 7) += offset; Exception (14); goto %s; }\n", endlabelstr);
+		    printf ("\t\tregs.sr = newsr; MakeFromSR ();\n}\n");
+		    pop_braces (old_brace_level);
+		    printf ("\tregs.sr = newsr;\n");
+			makefromsr ();
+		    printf ("\tif (newpc & 1) {\n");
+		    printf ("\t\texception3i (0x%04X, newpc);\n", opcode);
+			printf ("\t\tgoto %s;\n", endlabelstr);
+			printf ("\t}\n");
+		    setpc ("newpc");
+			check_ipl ();
+		    need_endlabel = 1;
+		} else {
+		    int old_brace_level = n_braces;
+		    printf ("\tuae_u16 newsr; uae_u32 newpc;\n");
+			printf ("\tfor (;;) {\n");
+			printf ("\t\tuaecptr a = m68k_areg (regs, 7);\n");
+			printf ("\t\tuae_u16 sr = %s (a);\n", srcw);
+			count_read++;
+			printf ("\t\tuae_u32 pc = %s (a + 2);\n", srcl);
+			count_read += 2;
+			printf ("\t\tuae_u16 format = %s (a + 2 + 4);\n", srcw);
+			count_read++;
+			printf ("\t\tint frame = format >> 12;\n");
+			printf ("\t\tint offset = 8;\n");
+			printf ("\t\tnewsr = sr; newpc = pc;\n");
+			addcycles_ce020 (6);
+		    printf ("\t\tif (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }\n");
+		    printf ("\t\telse if (frame == 0x1) { m68k_areg (regs, 7) += offset; }\n");
+		    printf ("\t\telse if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }\n");
+		    if (using_mmu == 68060) {
+				printf ("\t\telse if (frame == 0x4) { m68k_do_rte_mmu060 (a); m68k_areg (regs, 7) += offset + 8; break; }\n");
+			} else {
+				printf ("\t\telse if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }\n");
+			}
+		    printf ("\t\telse if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }\n");
+			if (using_mmu == 68040) {
+		    	printf ("\t\telse if (frame == 0x7) { m68k_do_rte_mmu040 (a); m68k_areg (regs, 7) += offset + 52; break; }\n");
+			} else {
+		    	printf ("\t\telse if (frame == 0x7) { m68k_areg (regs, 7) += offset + 52; break; }\n");
+			}
+			printf ("\t\telse if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }\n");
+			if (using_mmu == 68030) {
+				printf ("\t\telse if (frame == 0xa) { m68k_do_rte_mmu030 (a); break; }\n");
+			    printf ("\t\telse if (frame == 0xb) { m68k_do_rte_mmu030 (a); break; }\n");
+			} else {
+				printf ("\t\telse if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }\n");
+			    printf ("\t\telse if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }\n");
+			}
+		    printf ("\t\telse { m68k_areg (regs, 7) += offset; Exception (14); goto %s; }\n", endlabelstr);
+		    printf ("\t\tregs.sr = newsr;\n");
+			makefromsr ();
+			printf ("}\n");
+		    pop_braces (old_brace_level);
+		    printf ("\tregs.sr = newsr;\n");
+			addcycles_ce020 (4);
+			makefromsr ();
+		    printf ("\tif (newpc & 1) {\n");
+		    printf ("\t\texception3i (0x%04X, newpc);\n", opcode);
+			printf ("\t\tgoto %s;\n", endlabelstr);
+			printf ("\t}\n");
+		    setpc ("newpc");
+			check_ipl ();
+		    need_endlabel = 1;
+		}
+		/* PC is set and prefetch filled. */
+		clear_m68k_offset();
+		tail_ce020_done = true;
+		fill_prefetch_full ();
+		branch_inst = 1;
+		break;
+	case i_RTD:
+		addop_ce020 (curi, 0);
+		if (using_mmu) {
+			genamode (curi, curi->smode, "srcreg", curi->size, "offs", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
+			genamode (NULL, Aipi, "7", sz_long, "pc", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
+			printf ("\tm68k_areg(regs, 7) += offs;\n");
+		} else {
+			genamode (NULL, Aipi, "7", sz_long, "pc", 1, 0, 0);
+			genamode (curi, curi->smode, "srcreg", curi->size, "offs", 1, 0, 0);
+			printf ("\tm68k_areg (regs, 7) += offs;\n");
+		}
+	    printf ("\tif (pc & 1) {\n");
+	    printf ("\t\texception3i (0x%04X, pc);\n", opcode);
+		printf ("\t\tgoto %s;\n", endlabelstr);
+		printf ("\t}\n");
+		setpc ("pc");
+		/* PC is set and prefetch filled. */
+		clear_m68k_offset();
+		tail_ce020_done = true;
+		fill_prefetch_full ();
+	    need_endlabel = 1;
+		branch_inst = 1;
+		break;
+	case i_LINK:
+		// ce confirmed
+		if (using_mmu) {
+			addmmufixup ("srcreg");
+			genamode (NULL, curi->dmode, "dstreg", curi->size, "offs", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
+			genamode (NULL, Apdi, "7", sz_long, "old", GENA_GETV_FETCH_ALIGN, GENA_MOVEM_DO_INC, 0);
+			genamode (NULL, curi->smode, "srcreg", sz_long, "src", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
+			genastore ("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
+			printf ("\tm68k_areg(regs, 7) += offs;\n");
+			genastore ("src", Apdi, "7", sz_long, "old");
+		} else {
+			addop_ce020 (curi, 0);
+			genamode (NULL, Apdi, "7", sz_long, "old", 2, 0, GF_AA);
+			genamode (NULL, curi->smode, "srcreg", sz_long, "src", 1, 0, GF_AA);
+			genamode (NULL, curi->dmode, "dstreg", curi->size, "offs", 1, 0, 0);
+			genastore ("src", Apdi, "7", sz_long, "old");
+			genastore ("m68k_areg (regs, 7)", curi->smode, "srcreg", sz_long, "src");
+			printf ("\tm68k_areg (regs, 7) += offs;\n");
+			fill_prefetch_next ();
+		}
+		break;
+	case i_UNLK:
+		// ce confirmed
+		if (using_mmu) {
+			genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+			printf ("\tuae_s32 old = %s (src);\n", srcl);
+			printf ("\tm68k_areg (regs, 7) = src + 4;\n");
+			printf ("\tm68k_areg (regs, srcreg) = old;\n");
+		} else {
+			genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+			printf ("\tm68k_areg (regs, 7) = src;\n");
+			genamode (NULL, Aipi, "7", sz_long, "old", 1, 0, 0);
+			fill_prefetch_next ();
+			genastore ("old", curi->smode, "srcreg", curi->size, "src");
+		}
+		break;
+	case i_RTS:
+		addop_ce020 (curi, 0);
+		printf ("\tuaecptr pc = %s;\n", getpc);
+		if (using_indirect && !using_ce020 && !using_prefetch_020 && !using_ce) {
+			printf("\tm68k_do_rtsi_jit ();\n");
+		} else if (using_ce020 == 1) {
+			add_head_cycs (1);
+			printf ("\tm68k_do_rts_ce020 ();\n");
+		} else if (using_ce020 == 2) {
+			add_head_cycs (1);
+			printf ("\tm68k_do_rts_ce030 ();\n");
+		} else if (using_ce) {
+			printf ("\tm68k_do_rts_ce ();\n");
+		} else if (using_mmu) {
+			printf ("\tm68k_do_rts_mmu%s ();\n", mmu_postfix);
+		} else if (using_prefetch || using_prefetch_020) {
+			printf ("\tm68k_do_rtsi ();\n");
+		} else {
+			printf ("\tm68k_do_rts ();\n");
+		}
+	    printf ("\tif (%s & 1) {\n", getpc);
+		printf ("\t\tuaecptr faultpc = %s;\n", getpc);
+		setpc ("pc");
+		printf ("\t\texception3i (0x%04X, faultpc);\n", opcode);
+		printf ("\t\tgoto %s;\n", endlabelstr);
+		printf ("\t}\n");
+		count_read += 2;
+		clear_m68k_offset();
+		fill_prefetch_full ();
+	    need_endlabel = 1;
+		branch_inst = 1;
+		break;
+	case i_TRAPV:
+		sync_m68k_pc ();
+		fill_prefetch_next ();
+		printf ("\tif (GET_VFLG ()) {\n");
+		printf ("\t\tException (7);\n");
+		printf ("\t\tgoto %s;\n", endlabelstr);
+		printf ("\t}\n");
+		need_endlabel = 1;
+		break;
+	case i_RTR:
+		printf ("\tuaecptr oldpc = %s;\n", getpc);
+		printf ("\tMakeSR ();\n");
+		genamode (NULL, Aipi, "7", sz_word, "sr", 1, 0, 0);
+		genamode (NULL, Aipi, "7", sz_long, "pc", 1, 0, 0);
+		printf ("\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
+		printf ("\tregs.sr |= sr;\n");
+		setpc ("pc");
+		makefromsr ();
+		printf ("\tif (%s & 1) {\n", getpc);
+		printf ("\t\tuaecptr faultpc = %s;\n", getpc);
+		setpc ("oldpc");
+		printf ("\t\texception3i (0x%04X, faultpc);\n", opcode);
+		printf ("\t\tgoto %s;\n", endlabelstr);
+		printf ("\t}\n");
+		clear_m68k_offset();
+		fill_prefetch_full ();
+	    need_endlabel = 1;
+		branch_inst = 1;
+		tail_ce020_done = true;
+		break;
+	case i_JSR:
+		// possible idle cycle, prefetch from new address, stack high return addr, stack low, prefetch
+		no_prefetch_ce020 = true;
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA|GF_NOREFILL);
+		start_brace ();
+		printf ("\tuaecptr oldpc = %s + %d;\n", getpc, m68k_pc_offset);
+		if (using_exception_3) {
+			printf ("\tif (srca & 1) {\n");
+			printf ("\t\texception3i (opcode, srca);\n");
+			printf ("\t\tgoto %s;\n", endlabelstr);
+			printf ("\t}\n");
+			need_endlabel = 1;
+		}
+		if (using_mmu) {
+			printf ("\t%s (m68k_areg (regs, 7) - 4, oldpc);\n", dstl);
+			printf ("\tm68k_areg (regs, 7) -= 4;\n");
+			setpc ("srca");
+			clear_m68k_offset();
+		} else {
+			if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16)
+				addcycles000 (2);
+			if (curi->smode == Ad8r || curi->smode == PC8r) {
+				addcycles000 (6);
+#ifdef WINUAE_FOR_HATARI
+				/* Hatari : JSR in Ad8r and PC8r mode takes 22 cycles, but on ST it takes 24 cycles */
+				/* because of an unaligned memory prefetch in this EA mode */
+				/* We add 2 cycles only in 68000 prefetch mode, 68000 CE mode is handled at the memory access level */
+				if ( using_prefetch && !using_ce )
+					addcycles000 (2);
+#endif
+				if (cpu_level <= 1 && using_prefetch)
+					printf ("\toldpc += 2;\n");
+			}
+			setpc ("srca");
+			clear_m68k_offset();
+			fill_prefetch_1 (0);
+			printf ("\tm68k_areg (regs, 7) -= 4;\n");
+			if (using_ce || using_prefetch) {
+				printf ("\t%s (m68k_areg (regs, 7), oldpc >> 16);\n", dstw);
+				printf ("\t%s (m68k_areg (regs, 7) + 2, oldpc);\n", dstw);
+			} else {
+				printf ("\t%s (m68k_areg (regs, 7), oldpc);\n", dstl);
+			}
+		}
+		count_write += 2;
+		fill_prefetch_full_020 ();
+		fill_prefetch_next ();
+		branch_inst = 1;
+		break;
+	case i_JMP:
+		no_prefetch_ce020 = true;
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA|GF_NOREFILL);
+		if (using_exception_3) {
+			printf ("\tif (srca & 1) {\n");
+			printf ("\t\texception3i (opcode, srca);\n");
+			printf ("\t\tgoto %s;\n", endlabelstr);
+			printf ("\t}\n");
+			need_endlabel = 1;
+		}
+		if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16)
+			addcycles000 (2);
+		if (curi->smode == Ad8r || curi->smode == PC8r) {
+			addcycles000 (6);
+#ifdef WINUAE_FOR_HATARI
+			/* Hatari : JMP in Ad8r and PC8r mode takes 22 cycles, but on ST it takes 24 cycles */
+			/* because of an unaligned memory prefetch in this EA mode */
+			/* We add 2 cycles only in 68000 prefetch mode, 68000 CE mode is handled at the memory access level */
+			if ( using_prefetch && !using_ce )
+				addcycles000 (2);
+#endif
+		}
+		setpc ("srca");
+		clear_m68k_offset();
+		fill_prefetch_full ();
+		branch_inst = 1;
+		break;
+	case i_BSR:
+		// .b/.w = idle cycle, store high, store low, 2xprefetch
+		if (isce020())
+			no_prefetch_ce020 = true;
+		printf ("\tuae_s32 s;\n");
+		if (curi->size == sz_long) {
+			if (next_cpu_level < 1)
+				next_cpu_level = 1;
+		}
+		if (curi->size == sz_long && cpu_level < 2) {
+			printf ("\tuae_u32 src = 0xffffffff;\n");
+		} else {
+			genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA|GF_NOREFILL);
+		}
+		printf ("\ts = (uae_s32)src + 2;\n");
+		if (using_exception_3) {
+			printf ("\tif (src & 1) {\n");
+			printf ("\t\texception3b (opcode, %s + s, 0, 1, %s + s);\n", getpc, getpc);
+			printf ("\t\tgoto %s;\n", endlabelstr);
+			printf ("\t}\n");
+			need_endlabel = 1;
+		}
+		addcycles000 (2);
+		if (using_indirect && !using_ce020 && !using_prefetch_020 && !using_ce) {
+			printf("\tm68k_do_bsri_jit (%s + %d, s);\n", getpc, m68k_pc_offset);
+		} else if (using_ce020 == 1) {
+			printf ("\tm68k_do_bsr_ce020 (%s + %d, s);\n", getpc, m68k_pc_offset);
+		} else if (using_ce020 == 2) {
+			printf ("\tm68k_do_bsr_ce030 (%s + %d, s);\n", getpc, m68k_pc_offset);
+		} else if (using_ce) {
+			printf ("\tm68k_do_bsr_ce (%s + %d, s);\n", getpc, m68k_pc_offset);
+		} else if (using_mmu) {
+			printf ("\tm68k_do_bsr_mmu%s (%s + %d, s);\n", mmu_postfix, getpc, m68k_pc_offset);
+		} else if (using_prefetch || using_prefetch_020) {
+			printf ("\tm68k_do_bsri (%s + %d, s);\n", getpc, m68k_pc_offset);
+		} else {
+			printf ("\tm68k_do_bsr (%s + %d, s);\n", getpc, m68k_pc_offset);
+		}
+		count_write += 2;
+		clear_m68k_offset();
+		fill_prefetch_full ();
+		branch_inst = 1;
+		break;
+	case i_Bcc:
+		tail_ce020_done = true;
+		if (curi->size == sz_long) {
+			if (cpu_level < 2) {
+				addcycles000 (2);
+				printf ("\tif (cctrue (%d)) {\n", curi->cc);
+				printf ("\t\texception3i (opcode, %s + 1);\n", getpc);
+				printf ("\t\tgoto %s;\n", endlabelstr);
+				printf ("\t}\n");
+				sync_m68k_pc ();
+				addcycles000 (2);
+				irc2ir ();
+				fill_prefetch_2 ();
+				need_endlabel = 1;
+				goto bccl_not68020;
+			} else {
+				if (next_cpu_level < 1)
+					next_cpu_level = 1;
+			}
+		}
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | (cpu_level < 2 ? GF_NOREFILL : 0));
+		addcycles000 (2);
+		printf ("\tif (!cctrue (%d)) goto didnt_jump;\n", curi->cc);
+		if (using_exception_3) {
+			printf ("\tif (src & 1) {\n");
+			printf ("\t\texception3i (opcode, %s + 2 + (uae_s32)src);\n", getpc);
+			printf ("\t\tgoto %s;\n", endlabelstr);
+			printf ("\t}\n");
+			need_endlabel = 1;
+		}
+		push_ins_cnt();
+		if (using_prefetch) {
+			incpc ("(uae_s32)src + 2");
+			fill_prefetch_full_000 ();
+			if (using_ce)
+				printf ("\treturn;\n");
+			else
+				printf ("\treturn 10 * CYCLE_UNIT / 2;\n");
+		} else {
+			incpc ("(uae_s32)src + 2");
+			add_head_cycs (6);
+			fill_prefetch_full_020 ();
+			returncycles ("\t", 10);
+		}
+		pop_ins_cnt();
+		printf ("didnt_jump:;\n");
+		need_endlabel = 1;
+		sync_m68k_pc ();
+		addcycles000 (2);
+		get_prefetch_020_continue ();
+		if (curi->size == sz_byte) {
+			irc2ir ();
+			add_head_cycs (4);
+			fill_prefetch_2 ();
+		} else if (curi->size == sz_word) {
+			add_head_cycs (6);
+			fill_prefetch_full_000 ();
+		} else {
+			add_head_cycs (6);
+			fill_prefetch_full_000 ();
+		}
+		insn_n_cycles = curi->size == sz_byte ? 8 : 12;
+		branch_inst = 1;
+bccl_not68020:
+		break;
+	case i_LEA:
+		if (curi->smode == Ad8r || curi->smode == PC8r)
+			addcycles000 (2);
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "src", 0, GF_AA,
+			curi->dmode, "dstreg", curi->size, "dst", 2, GF_AA);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, GF_AA);
+		if (curi->smode == Ad8r || curi->smode == PC8r) {
+			addcycles000 (2);
+#ifdef WINUAE_FOR_HATARI
+			/* Hatari : LEA in Ad8r and PC8r mode takes 12 cycles, but on ST it takes 14 cycles */
+			/* because of an unaligned memory prefetch in this EA mode */
+			/* We add 2 cycles only in 68000 prefetch mode, 68000 CE mode is handled at the memory access level */
+			if ( using_prefetch && !using_ce )
+				addcycles000 (2);
+#endif
+		}
+		fill_prefetch_next ();
+		genastore ("srca", curi->dmode, "dstreg", curi->size, "dst");
+		break;
+	case i_PEA:
+		if (curi->smode == Ad8r || curi->smode == PC8r)
+			addcycles000 (2);
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA);
+		genamode (NULL, Apdi, "7", sz_long, "dst", 2, 0, GF_AA);
+		if (!(curi->smode == absw || curi->smode == absl))
+			fill_prefetch_next ();
+		if (curi->smode == Ad8r || curi->smode == PC8r) {
+			addcycles000 (2);
+#ifdef WINUAE_FOR_HATARI
+			/* Hatari : PEA in Ad8r and PC8r mode takes 20 cycles, but on ST it takes 22 cycles */
+			/* because of an unaligned memory prefetch in this EA mode */
+			/* We add 2 cycles only in 68000 prefetch mode, 68000 CE mode is handled at the memory access level */
+			if ( using_prefetch && !using_ce )
+				addcycles000 (2);
+#endif
+		}
+		genastore ("srca", Apdi, "7", sz_long, "dst");
+		if ((curi->smode == absw || curi->smode == absl))
+			fill_prefetch_next ();
+		break;
+	case i_DBcc:
+		// cc true: idle cycle, prefetch
+		// cc false, counter expired: idle cycle, prefetch (from branch address), 2xprefetch (from next address)
+		// cc false, counter not expired: idle cycle, prefetch
+		tail_ce020_done = true;
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "src", 1, GF_AA | (cpu_level < 2 ? GF_NOREFILL : 0),
+			curi->dmode, "dstreg", curi->size, "offs", 1, GF_AA | (cpu_level < 2 ? GF_NOREFILL : 0));
+		//genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_NOREFILL);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "offs", 1, 0, GF_AA | GF_NOREFILL);
+		printf ("\tuaecptr oldpc = %s;\n", getpc);
+		addcycles000_nonce("\t\t", 2);
+		addcycles000 (2);
+		push_ins_cnt();
+		printf ("\tif (!cctrue (%d)) {\n", curi->cc);
+		incpc ("(uae_s32)offs + 2");
+		printf ("\t");
+		fill_prefetch_1 (0);
+		printf ("\t");
+		genastore ("(src - 1)", curi->smode, "srcreg", curi->size, "src");
+
+		printf ("\t\tif (src) {\n");
+		if (using_exception_3) {
+			printf ("\t\t\tif (offs & 1) {\n");
+			printf ("\t\t\t\texception3i (opcode, %s + 2 + (uae_s32)offs + 2);\n", getpc);
+			printf ("\t\t\t\tgoto %s;\n", endlabelstr);
+			printf ("\t\t\t}\n");
+			need_endlabel = 1;
+		}
+		irc2ir ();
+		add_head_cycs (6);
+		fill_prefetch_1 (2);
+		fill_prefetch_full_020 ();
+		returncycles ("\t\t\t", 8);
+		printf ("\t\t}\n");
+		add_head_cycs (10);
+		addcycles000_nonce("\t\t", 2);
+		printf ("\t} else {\n");
+		addcycles000_onlyce(2);
+		addcycles000_nonce("\t\t", 2);
+		printf ("\t}\n");
+		pop_ins_cnt();
+		setpc ("oldpc + %d", m68k_pc_offset);
+		clear_m68k_offset();
+		get_prefetch_020_continue ();
+		fill_prefetch_full_000 ();
+		insn_n_cycles = 12;
+		need_endlabel = 1;
+		branch_inst = 1;
+		break;
+	case i_Scc:
+		// confirmed
+		next_level_000 ();
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", cpu_level == 0 ? 1 : 2, 0, 0);
+		start_brace ();
+		fill_prefetch_next();
+		start_brace ();
+		printf ("\tint val = cctrue (%d) ? 0xff : 0;\n", curi->cc);
+		if (isreg (curi->smode)) {
+			if (using_ce)
+				printf ("\tint cycles = val ? 2 : 0;\n");
+			addcycles000_3 ("\t");
+			addcycles000_nonces("\t", "(val ? 2 : 0)");
+		}
+		genastore ("val", curi->smode, "srcreg", curi->size, "src");
+		break;
+	case i_DIVU:
+		tail_ce020_done	= true;
+		genamodedual (curi,
+			curi->smode, "srcreg", sz_word, "src", 1, 0,
+			curi->dmode, "dstreg", sz_long, "dst", 1, 0);
+		printf ("\tCLEAR_CZNV ();\n");
+		printf ("\tif (src == 0) {\n");
+		if (cpu_level > 1)
+			printf ("\t\tdivbyzero_special (0, dst);\n");
+		incpc ("%d", m68k_pc_offset);
+		printf ("\t\tException (5);\n");
+		printf ("\t\tgoto %s;\n", endlabelstr);
+		printf ("\t} else {\n");
+		printf ("\t\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
+		printf ("\t\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
+		if (using_ce) {
+			start_brace ();
+			printf ("\t\tint cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4;\n");
+			addcycles000_3 ("\t\t");
+		}
+		addcycles000_nonces("\t\t", "(getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4");
+		fill_prefetch_next ();
+		/* The N flag appears to be set each time there is an overflow.
+		 * Weird. but 68020 only sets N when dst is negative.. */
+		printf ("\t\tif (newv > 0xffff) {\n");
+		printf ("\t\t\tSET_VFLG (1);\n");
+#ifdef UNDEF68020
+		if (cpu_level >= 2)
+			printf ("\t\t\tif (currprefs.cpu_level == 0 || dst < 0) SET_NFLG (®s, 1);\n");
+		else /* ??? some 68000 revisions may not set NFLG when overflow happens.. */
+#endif
+			printf ("\t\t\tSET_NFLG (1);\n");
+		printf ("\t\t} else {\n");
+		printf ("\t\t"); genflags (flag_logical, sz_word, "newv", "", "");
+		printf ("\t\t\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
+		printf ("\t\t"); genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
+		printf ("\t\t}\n");
+		sync_m68k_pc ();
+		printf ("\t}\n");
+		count_ncycles++;
+		insn_n_cycles += 136 - (136 - 76) / 2; /* average */
+		need_endlabel = 1;
+		tail_ce020_done	= false;
+		returntail (false);
+		break;
+	case i_DIVS:
+		tail_ce020_done	= true;
+		genamodedual (curi,
+			curi->smode, "srcreg", sz_word, "src", 1, 0,
+			curi->dmode, "dstreg", sz_long, "dst", 1, 0);
+		printf ("\tif (src == 0) {\n");
+		if (cpu_level > 1)
+			printf ("\t\tdivbyzero_special (1, dst);\n");
+		incpc ("%d", m68k_pc_offset);
+		printf ("\t\tException (5);\n");
+		printf ("\t\tgoto %s;\n", endlabelstr);
+		printf ("\t}\n");
+		printf ("\tCLEAR_CZNV ();\n");
+		if (using_ce) {
+			start_brace ();
+			printf ("\t\tint cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4;\n");
+			addcycles000_3 ("\t\t");
+		}
+		addcycles000_nonces("\t\t", "(getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4");
+		fill_prefetch_next ();
+		printf ("\tif (dst == 0x80000000 && src == -1) {\n");
+		printf ("\t\tSET_VFLG (1);\n");
+		printf ("\t\tSET_NFLG (1);\n");
+		printf ("\t} else {\n");
+		printf ("\t\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
+		printf ("\t\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
+		printf ("\t\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {\n");
+		printf ("\t\t\tSET_VFLG (1);\n");
+#ifdef UNDEF68020
+		if (cpu_level > 0)
+			printf ("\t\t\tif (currprefs.cpu_level == 0) SET_NFLG (®s, 1);\n");
+		else
+#endif
+			printf ("\t\t\tSET_NFLG (1);\n");
+		printf ("\t\t} else {\n");
+		printf ("\t\t\tif (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;\n");
+		genflags (flag_logical, sz_word, "newv", "", "");
+		printf ("\t\t\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
+		printf ("\t\t"); genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
+		printf ("\t\t}\n");
+		printf ("\t}\n");
+		sync_m68k_pc ();
+		count_ncycles++;
+		insn_n_cycles += 156 - (156 - 120) / 2; /* average */
+		need_endlabel = 1;
+		tail_ce020_done	= false;
+		returntail (false);
+		break;
+	case i_MULU:
+		genamodedual (curi,
+			curi->smode, "srcreg", sz_word, "src", 1, 0,
+			curi->dmode, "dstreg", sz_word, "dst", 1, 0);
+		fill_prefetch_next();
+		start_brace ();
+		printf ("\tuae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;\n");
+		if (using_ce)
+			printf ("\tint cycles = 38 - 4, bits;\n");
+		else if (using_prefetch)
+			printf ("\tint bits;\n");
+		genflags (flag_logical, sz_long, "newv", "", "");
+		if (using_ce) {
+			printf ("\tfor(bits = 0; bits < 16 && src; bits++, src >>= 1)\n");
+			printf ("\t\tif (src & 1) cycles += 2;\n");
+			addcycles000_3 ("\t");
+		}
+		addcycles000_nonce("\tfor(bits = 0; bits < 16 && src; bits++, src >>= 1)\n\t\tif (src & 1) ", 2);
+		genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
+		sync_m68k_pc ();
+		count_cycles += 38 - 4;
+		count_ncycles++;
+		insn_n_cycles += (70 - 38) / 2 + 38; /* average */
+		break;
+	case i_MULS:
+		genamodedual (curi,
+			curi->smode, "srcreg", sz_word, "src", 1, 0,
+			curi->dmode, "dstreg", sz_word, "dst", 1, 0);
+		fill_prefetch_next();
+		start_brace ();
+		printf ("\tuae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;\n");
+		if (using_ce) {
+			printf ("\tint cycles = 38 - 4, bits;\n");
+			printf ("\tuae_u32 usrc;\n");
+		} else if (using_prefetch) {
+			printf ("\tint bits;\n");
+			printf ("\tuae_u32 usrc;\n");
+		}
+		genflags (flag_logical, sz_long, "newv", "", "");
+		if (using_ce) {
+			printf ("\tusrc = ((uae_u32)src) << 1;\n");
+			printf ("\tfor(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)\n");
+			printf ("\t\tif ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;\n");
+			addcycles000_3 ("\t");
+		}
+		addcycles000_nonce("\tusrc = ((uae_u32)src) << 1;\n\tfor(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)\n\t\tif ((usrc & 3) == 1 || (usrc & 3) == 2) ", 2);
+		genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
+		count_cycles += 38 - 4;
+		count_ncycles++;
+		insn_n_cycles += (70 - 38) / 2 + 38; /* average */
+		break;
+	case i_CHK:
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
+		sync_m68k_pc ();
+		addcycles000 (4);
+		printf ("\tif (dst > src) {\n");
+		printf ("\t\tSET_NFLG (0);\n");
+		printf ("\t\tException (6);\n");
+		printf ("\t\tgoto %s;\n", endlabelstr);
+		printf ("\t}\n");
+		addcycles000 (2);
+		printf ("\tif ((uae_s32)dst < 0) {\n");
+		printf ("\t\tSET_NFLG (1);\n");
+		printf ("\t\tException (6);\n");
+		printf ("\t\tgoto %s;\n", endlabelstr);
+		printf ("\t}\n");
+		fill_prefetch_next ();
+		need_endlabel = 1;
+		break;
+	case i_CHK2:
+		genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
+		genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
+		fill_prefetch_0 ();
+		printf ("\t{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
+		switch (curi->size) {
+		case sz_byte:
+			printf ("\tlower = (uae_s32)(uae_s8)%s (dsta); upper = (uae_s32)(uae_s8)%s (dsta + 1);\n", srcb, srcb);
+			printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;\n");
+			break;
+		case sz_word:
+			printf ("\tlower = (uae_s32)(uae_s16)%s (dsta); upper = (uae_s32)(uae_s16)%s (dsta + 2);\n", srcw, srcw);
+			printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;\n");
+			break;
+		case sz_long:
+			printf ("\tlower = %s (dsta); upper = %s (dsta + 4);\n", srcl, srcl);
+			break;
+		default:
+			term ();
+		}
+		printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
+		printf ("\tSET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
+		printf ("\tif ((extra & 0x800) && GET_CFLG ()) { Exception (6); goto %s; }\n}\n", endlabelstr);
+		need_endlabel = 1;
+		break;
+
+	case i_ASR:
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "cnt", 1, 0,
+			curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
+		case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
+		printf ("\tint ccnt = cnt & 63;\n");
+		printf ("\tcnt &= 63;\n");
+		printf ("\tCLEAR_CZNV ();\n");
+		printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
+		printf ("\t\tval = %s & (uae_u32)-sign;\n", bit_mask (curi->size));
+		printf ("\t\tSET_CFLG (sign);\n");
+		duplicate_carry (1);
+		if (source_is_imm1_8 (curi))
+			printf ("\t} else {\n");
+		else
+			printf ("\t} else if (cnt > 0) {\n");
+		printf ("\t\tval >>= cnt - 1;\n");
+		printf ("\t\tSET_CFLG (val & 1);\n");
+		duplicate_carry (1);
+		printf ("\t\tval >>= 1;\n");
+		printf ("\t\tval |= (%s << (%d - cnt)) & (uae_u32)-sign;\n",
+			bit_mask (curi->size),
+			bit_size (curi->size));
+		printf ("\t\tval &= %s;\n", bit_mask (curi->size));
+		printf ("\t}\n");
+		genflags (flag_logical_noclobber, curi->size, "val", "", "");
+		shift_ce (curi->dmode, curi->size);
+		genastore ("val", curi->dmode, "dstreg", curi->size, "data");
+		break;
+	case i_ASL:
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "cnt", 1, 0,
+			curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
+		case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tint ccnt = cnt & 63;\n");
+		printf ("\tcnt &= 63;\n");
+		printf ("\tCLEAR_CZNV ();\n");
+		printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
+		printf ("\t\tSET_VFLG (val != 0);\n");
+		printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
+			bit_size (curi->size));
+		duplicate_carry (1);
+		printf ("\t\tval = 0;\n");
+		if (source_is_imm1_8 (curi))
+			printf ("\t} else {\n");
+		else
+			printf ("\t} else if (cnt > 0) {\n");
+		printf ("\t\tuae_u32 mask = (%s << (%d - cnt)) & %s;\n",
+			bit_mask (curi->size),
+			bit_size (curi->size) - 1,
+			bit_mask (curi->size));
+		printf ("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
+		printf ("\t\tval <<= cnt - 1;\n");
+		printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
+		duplicate_carry (1);
+		printf ("\t\tval <<= 1;\n");
+		printf ("\t\tval &= %s;\n", bit_mask (curi->size));
+		printf ("\t}\n");
+		genflags (flag_logical_noclobber, curi->size, "val", "", "");
+		shift_ce (curi->dmode, curi->size);
+		genastore ("val", curi->dmode, "dstreg", curi->size, "data");
+		break;
+	case i_LSR:
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "cnt", 1, 0,
+			curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
+		case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tint ccnt = cnt & 63;\n");
+		printf ("\tcnt &= 63;\n");
+		printf ("\tCLEAR_CZNV ();\n");
+		printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
+		printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
+			bit_size (curi->size), bit_size (curi->size) - 1);
+		duplicate_carry (1);
+		printf ("\t\tval = 0;\n");
+		if (source_is_imm1_8 (curi))
+			printf ("\t} else {\n");
+		else
+			printf ("\t} else if (cnt > 0) {\n");
+		printf ("\t\tval >>= cnt - 1;\n");
+		printf ("\t\tSET_CFLG (val & 1);\n");
+		duplicate_carry (1);
+		printf ("\t\tval >>= 1;\n");
+		printf ("\t}\n");
+		genflags (flag_logical_noclobber, curi->size, "val", "", "");
+		shift_ce (curi->dmode, curi->size);
+		genastore ("val", curi->dmode, "dstreg", curi->size, "data");
+		break;
+	case i_LSL:
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "cnt", 1, 0,
+			curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
+		case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tint ccnt = cnt & 63;\n");
+		printf ("\tcnt &= 63;\n");
+		printf ("\tCLEAR_CZNV ();\n");
+		printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
+		printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n", bit_size (curi->size));
+		duplicate_carry (1);
+		printf ("\t\tval = 0;\n");
+		if (source_is_imm1_8 (curi))
+			printf ("\t} else {\n");
+		else
+			printf ("\t} else if (cnt > 0) {\n");
+		printf ("\t\tval <<= (cnt - 1);\n");
+		printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
+		duplicate_carry (1);
+		printf ("\t\tval <<= 1;\n");
+		printf ("\tval &= %s;\n", bit_mask (curi->size));
+		printf ("\t}\n");
+		genflags (flag_logical_noclobber, curi->size, "val", "", "");
+		shift_ce (curi->dmode, curi->size);
+		genastore ("val", curi->dmode, "dstreg", curi->size, "data");
+		break;
+	case i_ROL:
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "cnt", 1, 0,
+			curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
+		case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tint ccnt = cnt & 63;\n");
+		printf ("\tcnt &= 63;\n");
+		printf ("\tCLEAR_CZNV ();\n");
+		if (source_is_imm1_8 (curi))
+			printf ("{");
+		else
+			printf ("\tif (cnt > 0) {\n");
+		printf ("\tuae_u32 loval;\n");
+		printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
+		printf ("\tloval = val >> (%d - cnt);\n", bit_size (curi->size));
+		printf ("\tval <<= cnt;\n");
+		printf ("\tval |= loval;\n");
+		printf ("\tval &= %s;\n", bit_mask (curi->size));
+		printf ("\tSET_CFLG (val & 1);\n");
+		printf ("}\n");
+		genflags (flag_logical_noclobber, curi->size, "val", "", "");
+		shift_ce (curi->dmode, curi->size);
+		genastore ("val", curi->dmode, "dstreg", curi->size, "data");
+		break;
+	case i_ROR:
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "cnt", 1, 0,
+			curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
+		case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tint ccnt = cnt & 63;\n");
+		printf ("\tcnt &= 63;\n");
+		printf ("\tCLEAR_CZNV ();\n");
+		if (source_is_imm1_8 (curi))
+			printf ("{");
+		else
+			printf ("\tif (cnt > 0) {");
+		printf ("\tuae_u32 hival;\n");
+		printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
+		printf ("\thival = val << (%d - cnt);\n", bit_size (curi->size));
+		printf ("\tval >>= cnt;\n");
+		printf ("\tval |= hival;\n");
+		printf ("\tval &= %s;\n", bit_mask (curi->size));
+		printf ("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
+		printf ("\t}\n");
+		genflags (flag_logical_noclobber, curi->size, "val", "", "");
+		shift_ce (curi->dmode, curi->size);
+		genastore ("val", curi->dmode, "dstreg", curi->size, "data");
+		break;
+	case i_ROXL:
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "cnt", 1, 0,
+			curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
+		case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tint ccnt = cnt & 63;\n");
+		printf ("\tcnt &= 63;\n");
+		printf ("\tCLEAR_CZNV ();\n");
+		if (source_is_imm1_8 (curi))
+			printf ("{");
+		else {
+			force_range_for_rox ("cnt", curi->size);
+			printf ("\tif (cnt > 0) {\n");
+		}
+		printf ("\tcnt--;\n");
+		printf ("\t{\n\tuae_u32 carry;\n");
+		printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
+		printf ("\tcarry = loval & 1;\n");
+		printf ("\tval = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);\n");
+		printf ("\tSET_XFLG (carry);\n");
+		printf ("\tval &= %s;\n", bit_mask (curi->size));
+		printf ("\t} }\n");
+		printf ("\tSET_CFLG (GET_XFLG ());\n");
+		genflags (flag_logical_noclobber, curi->size, "val", "", "");
+		shift_ce (curi->dmode, curi->size);
+		genastore ("val", curi->dmode, "dstreg", curi->size, "data");
+		break;
+	case i_ROXR:
+		genamodedual (curi,
+			curi->smode, "srcreg", curi->size, "cnt", 1, 0,
+			curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
+		//genamode (curi, curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
+		//genamode (curi, curi->dmode, "dstreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
+		case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tint ccnt = cnt & 63;\n");
+		printf ("\tcnt &= 63;\n");
+		printf ("\tCLEAR_CZNV ();\n");
+		if (source_is_imm1_8 (curi))
+			printf ("{");
+		else {
+			force_range_for_rox ("cnt", curi->size);
+			printf ("\tif (cnt > 0) {\n");
+		}
+		printf ("\tcnt--;\n");
+		printf ("\t{\n\tuae_u32 carry;\n");
+		printf ("\tuae_u32 hival = (val << 1) | GET_XFLG ();\n");
+		printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
+		printf ("\tval >>= cnt;\n");
+		printf ("\tcarry = val & 1;\n");
+		printf ("\tval >>= 1;\n");
+		printf ("\tval |= hival;\n");
+		printf ("\tSET_XFLG (carry);\n");
+		printf ("\tval &= %s;\n", bit_mask (curi->size));
+		printf ("\t} }\n");
+		printf ("\tSET_CFLG (GET_XFLG ());\n");
+		genflags (flag_logical_noclobber, curi->size, "val", "", "");
+		shift_ce (curi->dmode, curi->size);
+		genastore ("val", curi->dmode, "dstreg", curi->size, "data");
+		break;
+	case i_ASRW:
+		genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
+		case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
+		printf ("\tuae_u32 cflg = val & 1;\n");
+		printf ("\tval = (val >> 1) | sign;\n");
+		genflags (flag_logical, curi->size, "val", "", "");
+		printf ("\tSET_CFLG (cflg);\n");
+		duplicate_carry (0);
+		genastore ("val", curi->smode, "srcreg", curi->size, "data");
+		break;
+	case i_ASLW:
+		genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
+		case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
+		printf ("\tuae_u32 sign2;\n");
+		printf ("\tval <<= 1;\n");
+		genflags (flag_logical, curi->size, "val", "", "");
+		printf ("\tsign2 = %s & val;\n", cmask (curi->size));
+		printf ("\tSET_CFLG (sign != 0);\n");
+		duplicate_carry (0);
+		printf ("\tSET_VFLG (GET_VFLG () | (sign2 != sign));\n");
+		genastore ("val", curi->smode, "srcreg", curi->size, "data");
+		break;
+	case i_LSRW:
+		genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
+		case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tuae_u32 carry = val & 1;\n");
+		printf ("\tval >>= 1;\n");
+		genflags (flag_logical, curi->size, "val", "", "");
+		printf ("\tSET_CFLG (carry);\n");
+		duplicate_carry (0);
+		genastore ("val", curi->smode, "srcreg", curi->size, "data");
+		break;
+	case i_LSLW:
+		genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
+		case sz_word: printf ("\tuae_u16 val = data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
+		printf ("\tval <<= 1;\n");
+		genflags (flag_logical, curi->size, "val", "", "");
+		printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
+		duplicate_carry (0);
+		genastore ("val", curi->smode, "srcreg", curi->size, "data");
+		break;
+	case i_ROLW:
+		genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
+		case sz_word: printf ("\tuae_u16 val = data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
+		printf ("\tval <<= 1;\n");
+		printf ("\tif (carry)  val |= 1;\n");
+		genflags (flag_logical, curi->size, "val", "", "");
+		printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
+		genastore ("val", curi->smode, "srcreg", curi->size, "data");
+		break;
+	case i_RORW:
+		genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
+		case sz_word: printf ("\tuae_u16 val = data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tuae_u32 carry = val & 1;\n");
+		printf ("\tval >>= 1;\n");
+		printf ("\tif (carry) val |= %s;\n", cmask (curi->size));
+		genflags (flag_logical, curi->size, "val", "", "");
+		printf ("\tSET_CFLG (carry);\n");
+		genastore ("val", curi->smode, "srcreg", curi->size, "data");
+		break;
+	case i_ROXLW:
+		genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
+		case sz_word: printf ("\tuae_u16 val = data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
+		printf ("\tval <<= 1;\n");
+		printf ("\tif (GET_XFLG ()) val |= 1;\n");
+		genflags (flag_logical, curi->size, "val", "", "");
+		printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
+		duplicate_carry (0);
+		genastore ("val", curi->smode, "srcreg", curi->size, "data");
+		break;
+	case i_ROXRW:
+		genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
+		fill_prefetch_next ();
+		start_brace ();
+		switch (curi->size) {
+		case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
+		case sz_word: printf ("\tuae_u16 val = data;\n"); break;
+		case sz_long: printf ("\tuae_u32 val = data;\n"); break;
+		default: term ();
+		}
+		printf ("\tuae_u32 carry = val & 1;\n");
+		printf ("\tval >>= 1;\n");
+		printf ("\tif (GET_XFLG ()) val |= %s;\n", cmask (curi->size));
+		genflags (flag_logical, curi->size, "val", "", "");
+		printf ("\tSET_CFLG (carry);\n");
+		duplicate_carry (0);
+		genastore ("val", curi->smode, "srcreg", curi->size, "data");
+		break;
+	case i_MOVEC2:
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		fill_prefetch_next ();
+		start_brace ();
+		printf ("\tint regno = (src >> 12) & 15;\n");
+		printf ("\tuae_u32 *regp = regs.regs + regno;\n");
+		printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
+		break;
+	case i_MOVE2C:
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
+		fill_prefetch_next ();
+		start_brace ();
+		printf ("\tint regno = (src >> 12) & 15;\n");
+		printf ("\tuae_u32 *regp = regs.regs + regno;\n");
+		printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
+		break;
+	case i_CAS:
+		{
+			int old_brace_level;
+			genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_LRMW);
+			genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_LRMW);
+			if (cpu_level == 5 && curi->size > 0) {
+				printf ("\tif ((dsta & %d) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {\n", curi->size == 1 ? 1 : 3);
+				if (curi->dmode == Aipi || curi->dmode == Apdi)
+					printf ("\t\tm68k_areg (regs, dstreg) %c= %d;\n", curi->dmode == Aipi ? '-' : '+', 1 << curi->size);
+				sync_m68k_pc_noreset ();
+				printf ("\t\top_unimpl (opcode);\n");
+				printf ("\t\tgoto %s;\n", endlabelstr);
+				printf ("\t}\n");
+				need_endlabel = 1;
+			}
+			fill_prefetch_0 ();
+			start_brace ();
+			printf ("\tint ru = (src >> 6) & 7;\n");
+			printf ("\tint rc = src & 7;\n");
+			genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, rc)", "dst");
+			gen_set_fault_pc ();
+			printf ("\tif (GET_ZFLG ()) ");
+			old_brace_level = n_braces;
+			start_brace ();
+			printf ("\n\t");
+			genastore_cas ("(m68k_dreg (regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
+			printf ("\t");
+			pop_braces (old_brace_level);
+			printf ("else");
+			start_brace ();
+			printf ("\n");
+			get_prefetch_020 ();
+			if (cpu_level >= 4) {
+				// apparently 68040/060 needs to always write at the end of RMW cycle
+				printf ("\t");
+				genastore_cas ("dst", curi->dmode, "dstreg", curi->size, "dst");
+			}
+			switch (curi->size) {
+				case sz_byte:
+				printf ("\t\tm68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);\n");
+				break;
+				case sz_word:
+				printf ("\t\tm68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);\n");
+				break;
+				default:
+				printf ("\t\tm68k_dreg(regs, rc) = dst;\n");
+				break;
+			}
+			pop_braces (old_brace_level);
+		}
+		break;
+	case i_CAS2:
+		genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, GF_LRMW);
+		printf ("\tuae_u32 rn1 = regs.regs[(extra >> 28) & 15];\n");
+		printf ("\tuae_u32 rn2 = regs.regs[(extra >> 12) & 15];\n");
+		if (curi->size == sz_word) {
+			int old_brace_level = n_braces;
+			printf ("\tuae_u16 dst1 = %s (rn1), dst2 = %s (rn2);\n", srcwlrmw, srcwlrmw);
+			genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, (extra >> 16) & 7)", "dst1");
+			printf ("\tif (GET_ZFLG ()) {\n");
+			genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, extra & 7)", "dst2");
+			printf ("\tif (GET_ZFLG ()) {\n");
+			printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 22) & 7));\n", dstwlrmw);
+			printf ("\t%s (rn2, m68k_dreg (regs, (extra >> 6) & 7));\n", dstwlrmw);
+			printf ("\t}}\n");
+			pop_braces (old_brace_level);
+			printf ("\tif (! GET_ZFLG ()) {\n");
+			printf ("\tm68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
+			printf ("\tm68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
+			printf ("\t}\n");
+		} else {
+			int old_brace_level = n_braces;
+			printf ("\tuae_u32 dst1 = %s (rn1), dst2 = %s (rn2);\n", srcllrmw, srcllrmw);
+			genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, (extra >> 16) & 7)", "dst1");
+			printf ("\tif (GET_ZFLG ()) {\n");
+			genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, extra & 7)", "dst2");
+			printf ("\tif (GET_ZFLG ()) {\n");
+			printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 22) & 7));\n", dstllrmw);
+			printf ("\t%s (rn2, m68k_dreg (regs, (extra >> 6) & 7));\n", dstllrmw);
+			printf ("\t}}\n");
+			pop_braces (old_brace_level);
+			printf ("\tif (! GET_ZFLG ()) {\n");
+			printf ("\tm68k_dreg (regs, (extra >> 6) & 7) = dst2;\n");
+			printf ("\tm68k_dreg (regs, (extra >> 22) & 7) = dst1;\n");
+			printf ("\t}\n");
+		}
+		break;
+	case i_MOVES: /* ignore DFC and SFC when using_mmu == false */
+		{
+			int old_brace_level;
+			tail_ce020_done	= true;
+			genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
+			printf ("\tif (extra & 0x800)\n");
+			{
+				int old_m68k_pc_offset = m68k_pc_offset;
+				old_brace_level = n_braces;
+				start_brace ();
+				printf ("\tuae_u32 src = regs.regs[(extra >> 12) & 15];\n");
+				genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
+				genastore_fc ("src", curi->dmode, "dstreg", curi->size, "dst");
+				pop_braces (old_brace_level);
+				m68k_pc_offset = old_m68k_pc_offset;
+			}
+			printf ("else");
+			{
+				start_brace ();
+				genamode (curi, curi->dmode, "dstreg", curi->size, "src", 1, 0, GF_FC);
+				printf ("\tif (extra & 0x8000) {\n");
+				switch (curi->size) {
+				case sz_byte: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;\n"); break;
+				case sz_word: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;\n"); break;
+				case sz_long: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = src;\n"); break;
+				default: term ();
+				}
+				printf ("\t} else {\n");
+				genastore ("src", Dreg, "(extra >> 12) & 7", curi->size, "");
+				printf ("\t}\n");
+				if (using_mmu == 68040)
+					sync_m68k_pc ();
+				pop_braces (old_brace_level);
+			}
+			tail_ce020_done	= false;
+			returntail (false);
+		}
+		break;
+	case i_BKPT:		/* only needed for hardware emulators */
+		sync_m68k_pc ();
+		printf ("\top_illg (opcode);\n");
+		break;
+	case i_CALLM:		/* not present in 68030 */
+		sync_m68k_pc ();
+		printf ("\top_illg (opcode);\n");
+		break;
+	case i_RTM:		/* not present in 68030 */
+		sync_m68k_pc ();
+		printf ("\top_illg (opcode);\n");
+		break;
+	case i_TRAPcc:
+		if (curi->smode != am_unknown && curi->smode != am_illg)
+			genamode (curi, curi->smode, "srcreg", curi->size, "dummy", 1, 0, 0);
+		fill_prefetch_0 ();
+		printf ("\tif (cctrue (%d)) { Exception (7); goto %s; }\n", curi->cc, endlabelstr);
+		need_endlabel = 1;
+		break;
+	case i_DIVL:
+		genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
+		genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
+		sync_m68k_pc ();
+		printf ("\tif (!m68k_divl(opcode, dst, extra)) goto %s;\n", endlabelstr);
+		need_endlabel = 1;
+		break;
+	case i_MULL:
+		genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
+		genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
+		sync_m68k_pc ();
+		printf ("\tif (!m68k_mull(opcode, dst, extra)) goto %s;\n", endlabelstr);
+		need_endlabel = 1;
+		break;
+	case i_BFTST:
+	case i_BFEXTU:
+	case i_BFCHG:
+	case i_BFEXTS:
+	case i_BFCLR:
+	case i_BFFFO:
+	case i_BFSET:
+	case i_BFINS:
+		{
+			const char *getb, *putb;
+
+			if (using_mmu == 68060 && (curi->mnemo == i_BFCHG || curi->mnemo == i_BFCLR ||  curi->mnemo == i_BFSET ||  curi->mnemo == i_BFINS)) {
+				getb = "mmu060_get_rmw_bitfield";
+				putb = "mmu060_put_rmw_bitfield";
+			} else if (using_mmu || using_ce020 || using_indirect) {
+				getb = "x_get_bitfield";
+				putb = "x_put_bitfield";
+			} else {
+				getb = "get_bitfield";
+				putb = "put_bitfield";
+			}
+
+			genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
+			genamode (curi, curi->dmode, "dstreg", sz_long, "dst", 2, 0, 0);
+			start_brace ();
+			printf ("\tuae_u32 bdata[2];\n");
+			printf ("\tuae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
+			printf ("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
+			if (curi->dmode == Dreg) {
+				printf ("\tuae_u32 tmp = m68k_dreg(regs, dstreg);\n");
+				printf ("\toffset &= 0x1f;\n");
+				printf ("\ttmp = (tmp << offset) | (tmp >> (32 - offset));\n");
+				printf ("\tbdata[0] = tmp & ((1 << (32 - width)) - 1);\n");
+			} else {
+				printf ("\tuae_u32 tmp;\n");
+				printf ("\tdsta += offset >> 3;\n");
+				printf ("\ttmp = %s (dsta, bdata, offset, width);\n", getb);
+			}
+			printf ("\tSET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);\n");
+			if (curi->mnemo == i_BFEXTS)
+				printf ("\ttmp = (uae_s32)tmp >> (32 - width);\n");
+			else
+				printf ("\ttmp >>= (32 - width);\n");
+			printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
+			switch (curi->mnemo) {
+			case i_BFTST:
+				break;
+			case i_BFEXTU:
+			case i_BFEXTS:
+				printf ("\tm68k_dreg (regs, (extra >> 12) & 7) = tmp;\n");
+				break;
+			case i_BFCHG:
+				printf ("\ttmp = tmp ^ (0xffffffffu >> (32 - width));\n");
+				break;
+			case i_BFCLR:
+				printf ("\ttmp = 0;\n");
+				break;
+			case i_BFFFO:
+				printf ("\t{ uae_u32 mask = 1 << (width - 1);\n");
+				printf ("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}\n");
+				printf ("\tm68k_dreg (regs, (extra >> 12) & 7) = offset;\n");
+				break;
+			case i_BFSET:
+				printf ("\ttmp = 0xffffffffu >> (32 - width);\n");
+				break;
+			case i_BFINS:
+				printf ("\ttmp = m68k_dreg (regs, (extra >> 12) & 7);\n");
+				printf ("\ttmp = tmp & (0xffffffffu >> (32 - width));\n");
+				printf ("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
+				printf ("\tSET_ZFLG (tmp == 0);\n");
+				break;
+			default:
+				break;
+			}
+			if (curi->mnemo == i_BFCHG
+				|| curi->mnemo == i_BFCLR
+				|| curi->mnemo == i_BFSET
+				|| curi->mnemo == i_BFINS) {
+					if (curi->dmode == Dreg) {
+						printf ("\ttmp = bdata[0] | (tmp << (32 - width));\n");
+						printf ("\tm68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));\n");
+					} else {
+						printf ("\t%s(dsta, bdata, tmp, offset, width);\n", putb);
+					}
+			}
+		}
+		break;
+	case i_PACK:
+		if (curi->smode == Dreg) {
+			printf ("\tuae_u16 val = m68k_dreg (regs, srcreg) + %s;\n", gen_nextiword (0));
+			printf ("\tm68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
+		} else {
+			printf ("\tuae_u16 val;\n");
+			addmmufixup ("srcreg");
+			printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
+			printf ("\tval = (uae_u16)(%s (m68k_areg (regs, srcreg)) & 0xff);\n", srcb);
+			printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
+			printf ("\tval = (val | ((uae_u16)(%s (m68k_areg (regs, srcreg)) & 0xff) << 8)) + %s;\n", srcb, gen_nextiword (0));
+			addmmufixup ("dstreg");
+			printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
+			gen_set_fault_pc ();
+			printf ("\t%s (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n", dstb);
+		}
+		break;
+	case i_UNPK:
+		if (curi->smode == Dreg) {
+			printf ("\tuae_u16 val = m68k_dreg (regs, srcreg);\n");
+			printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword (0));
+			printf ("\tm68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
+		} else {
+			printf ("\tuae_u16 val;\n");
+			addmmufixup ("srcreg");
+			printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
+			printf ("\tval = (uae_u16)(%s (m68k_areg (regs, srcreg)) & 0xff);\n", srcb);
+			printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword (0));
+			addmmufixup ("dstreg");
+			if (cpu_level >= 2) {
+				printf ("\tm68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];\n");
+				printf ("\t%s (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);\n", dstb);
+				printf ("\t%s (m68k_areg (regs, dstreg), val >> 8);\n", dstb);
+			} else {
+				printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
+				printf ("\t%s (m68k_areg (regs, dstreg),val);\n", dstb);
+				printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
+				gen_set_fault_pc ();
+				printf ("\t%s (m68k_areg (regs, dstreg),val >> 8);\n", dstb);
+			}
+		}
+		break;
+	case i_TAS:
+		genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_LRMW);
+		genflags (flag_logical, curi->size, "src", "", "");
+		if (!isreg (curi->smode))
+			addcycles000 (2);
+		fill_prefetch_next ();
+		printf ("\tsrc |= 0x80;\n");
+		if (cpu_level >= 2 || curi->smode == Dreg || !using_ce) {
+			if (next_cpu_level < 2)
+				next_cpu_level = 2 - 1;
+			genastore_tas ("src", curi->smode, "srcreg", curi->size, "src");
+		} else {
+			printf ("\tif (!is_cycle_ce ()) {\n");
+			genastore ("src", curi->smode, "srcreg", curi->size, "src");
+			printf ("\t} else {\n");
+			printf ("\t\t%s (4);\n", do_cycles);
+			addcycles000_nonce("\t\t", 4);
+			printf ("\t}\n");
+		}
+		break;
+	case i_FPP:
+		fpulimit();
+		genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
+		sync_m68k_pc ();
+		printf ("\tfpuop_arithmetic(opcode, extra);\n");
+		if (using_prefetch || using_prefetch_020) {
+			printf ("\tif (regs.fp_exception) goto %s;\n", endlabelstr);
+			need_endlabel = 1;
+		}
+		break;
+	case i_FDBcc:
+		fpulimit();
+		genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
+		sync_m68k_pc ();
+		printf ("\tfpuop_dbcc (opcode, extra);\n");
+		if (using_prefetch || using_prefetch_020) {
+			printf ("\tif (regs.fp_exception) goto %s;\n", endlabelstr);
+			printf ("\tif (regs.fp_branch) {\n");
+			printf ("\t\tregs.fp_branch = false;\n");
+			printf ("\t\tfill_prefetch();\n");
+			printf ("\t\tgoto %s;\n", endlabelstr);
+			printf ("\t}\n");
+			need_endlabel = 1;
+		}
+		break;
+	case i_FScc:
+		fpulimit();
+		genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
+		sync_m68k_pc ();
+		printf ("\tfpuop_scc (opcode, extra);\n");
+		if (using_prefetch || using_prefetch_020) {
+			printf ("\tif (regs.fp_exception) goto %s;\n", endlabelstr);
+			need_endlabel = 1;
+		}
+		break;
+	case i_FTRAPcc:
+		fpulimit();
+		printf ("\tuaecptr oldpc = %s;\n", getpc);
+		printf ("\tuae_u16 extra = %s;\n", gen_nextiword (0));
+		if (curi->smode != am_unknown && curi->smode != am_illg)
+			genamode (curi, curi->smode, "srcreg", curi->size, "dummy", 1, 0, 0);
+		sync_m68k_pc ();
+		printf ("\tfpuop_trapcc (opcode, oldpc, extra);\n");
+		if (using_prefetch || using_prefetch_020) {
+			printf ("\tif (regs.fp_exception) goto %s;\n", endlabelstr);
+			need_endlabel = 1;
+		}
+		break;
+	case i_FBcc:
+		fpulimit();
+		sync_m68k_pc ();
+		start_brace ();
+		printf ("\tuaecptr pc = %s;\n", getpc);
+		genamode (curi, curi->dmode, "srcreg", curi->size, "extra", 1, 0, 0);
+		sync_m68k_pc ();
+		printf ("\tfpuop_bcc (opcode, pc,extra);\n");
+		if (using_prefetch || using_prefetch_020) {
+			printf ("\tif (regs.fp_exception) goto %s;\n", endlabelstr);
+			printf ("\tif (regs.fp_branch) {\n");
+			printf ("\t\tregs.fp_branch = false;\n");
+			printf ("\t\tfill_prefetch();\n");
+			printf ("\t\tgoto %s;\n", endlabelstr);
+			printf ("\t}\n");
+			need_endlabel = 1;
+		}
+		break;
+	case i_FSAVE:
+		fpulimit();
+		sync_m68k_pc ();
+		printf ("\tfpuop_save (opcode);\n");
+		if (using_prefetch || using_prefetch_020) {
+			printf ("\tif (regs.fp_exception) goto %s;\n", endlabelstr);
+			need_endlabel = 1;
+		}
+		break;
+	case i_FRESTORE:
+		fpulimit();
+		sync_m68k_pc ();
+		printf ("\tfpuop_restore (opcode);\n");
+		if (using_prefetch || using_prefetch_020) {
+			printf ("\tif (regs.fp_exception) goto %s;\n", endlabelstr);
+			need_endlabel = 1;
+		}
+		break;
+
+	case i_CINVL:
+	case i_CINVP:
+	case i_CINVA:
+	case i_CPUSHL:
+	case i_CPUSHP:
+	case i_CPUSHA:
+		printf ("\tflush_cpu_caches_040(opcode);\n");
+		if (using_mmu)
+			printf ("\tflush_mmu%s(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);\n", mmu_postfix);
+		printf ("\tif (opcode & 0x80)\n");
+		printf ("\t\tflush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);\n");
+		break;
+
+	case i_MOVE16:
+		{
+			if ((opcode & 0xfff8) == 0xf620) {
+				/* MOVE16 (Ax)+,(Ay)+ */
+				printf ("\tuae_u32 v[4];\n");
+				printf ("\tuaecptr mems = m68k_areg (regs, srcreg) & ~15, memd;\n");
+				printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword (0));
+				printf ("\tmemd = m68k_areg (regs, dstreg) & ~15;\n");
+				if (using_mmu >= 68040) {
+					printf ("\tget_move16_mmu (mems, v);\n");
+					printf ("\tput_move16_mmu (memd, v);\n");
+				} else {
+					printf ("\tv[0] = %s (mems);\n", srcl);
+					printf ("\tv[1] = %s (mems + 4);\n", srcl);
+					printf ("\tv[2] = %s (mems + 8);\n", srcl);
+					printf ("\tv[3] = %s (mems + 12);\n", srcl);
+					printf ("\t%s (memd , v[0]);\n", dstl);
+					printf ("\t%s (memd + 4, v[1]);\n", dstl);
+					printf ("\t%s (memd + 8, v[2]);\n", dstl);
+					printf ("\t%s (memd + 12, v[3]);\n", dstl);
+				}
+				printf ("\tif (srcreg != dstreg)\n");
+				printf ("\t\tm68k_areg (regs, srcreg) += 16;\n");
+				printf ("\tm68k_areg (regs, dstreg) += 16;\n");
+			} else {
+				/* Other variants */
+				printf ("\tuae_u32 v[4];\n");
+				genamode (curi, curi->smode, "srcreg", curi->size, "mems", 0, 2, 0);
+				genamode (curi, curi->dmode, "dstreg", curi->size, "memd", 0, 2, 0);
+				if (using_mmu == 68040) {
+					printf ("\tget_move16_mmu (memsa, mmu040_move16);\n");
+					printf ("\tput_move16_mmu (memda, mmu040_move16);\n");
+				} else if (using_mmu == 68060) {
+					printf ("\tget_move16_mmu (memsa, v);\n");
+					printf ("\tput_move16_mmu (memda, v);\n");
+				} else {
+					printf ("\tmemsa &= ~15;\n");
+					printf ("\tmemda &= ~15;\n");
+					printf ("\tv[0] = %s (memsa);\n", srcl);
+					printf ("\tv[1] = %s (memsa + 4);\n", srcl);
+					printf ("\tv[2] = %s (memsa + 8);\n", srcl);
+					printf ("\tv[3] = %s (memsa + 12);\n", srcl);
+					printf ("\t%s (memda , v[0]);\n", dstl);
+					printf ("\t%s (memda + 4, v[1]);\n", dstl);
+					printf ("\t%s (memda + 8, v[2]);\n", dstl);
+					printf ("\t%s (memda + 12, v[3]);\n", dstl);
+				}
+				if ((opcode & 0xfff8) == 0xf600)
+					printf ("\tm68k_areg (regs, srcreg) += 16;\n");
+				else if ((opcode & 0xfff8) == 0xf608)
+					printf ("\tm68k_areg (regs, dstreg) += 16;\n");
+			}
+		}
+		break;
+
+	case i_PFLUSHN:
+	case i_PFLUSH:
+	case i_PFLUSHAN:
+	case i_PFLUSHA:
+	case i_PLPAR:
+	case i_PLPAW:
+	case i_PTESTR:
+	case i_PTESTW:
+		sync_m68k_pc ();
+		printf ("\tmmu_op (opcode, 0);\n");
+		break;
+	case i_MMUOP030:
+		printf ("\tuaecptr pc = %s;\n", getpc);
+		printf ("\tuae_u16 extra = %s (2);\n", prefetch_word);
+		m68k_pc_offset += 2;
+		sync_m68k_pc ();
+		if (curi->smode == Areg || curi->smode == Dreg)
+			printf("\tuae_u16 extraa = 0;\n");
+		else
+			genamode (curi, curi->smode, "srcreg", curi->size, "extra", 0, 0, 0);
+		sync_m68k_pc ();
+		if (using_ce020 || using_prefetch_020) {
+			printf ("\tif (mmu_op30 (pc, opcode, extra, extraa)) goto %s;\n", endlabelstr);
+			need_endlabel = 1;
+		} else {
+			printf ("\tmmu_op30 (pc, opcode, extra, extraa);\n");
+		}
+		break;
+	default:
+		term ();
+		break;
+	}
+	if (!genastore_done)
+		returntail (0);
+	finish_braces ();
+	if (limit_braces) {
+		printf ("\n#endif\n");
+		n_braces = limit_braces;
+		limit_braces = 0;
+		finish_braces ();
+	}
+	if (did_prefetch >= 0)
+		fill_prefetch_finish ();
+	sync_m68k_pc ();
+	did_prefetch = 0;
+	ipl_fetched = 0;
+}
+
+static void generate_includes (FILE * f, int id)
+{
+        fprintf (f, "#include \"main.h\"\n");
+//	fprintf (f, "#include \"sysconfig.h\"\n");
+	fprintf (f, "#include \"sysdeps.h\"\n");
+//	fprintf (f, "#include \"options.h\"\n");
+        fprintf (f, "#include \"hatari-glue.h\"\n");
+        fprintf (f, "#include \"maccess.h\"\n");
+	fprintf (f, "#include \"memory.h\"\n");
+	fprintf (f, "#include \"custom.h\"\n");
+//	fprintf (f, "#include \"events.h\"\n");
+	fprintf (f, "#include \"newcpu.h\"\n");
+	fprintf (f, "#include \"cpu_prefetch.h\"\n");
+	fprintf (f, "#include \"cputbl.h\"\n");
+	if (id == 31 || id == 33)
+		fprintf (f, "#include \"cpummu.h\"\n");
+	else if (id == 32)
+		fprintf (f, "#include \"cpummu030.h\"\n");
+
+	fprintf (f, "#define CPUFUNC(x) x##_ff\n"
+		"#define SET_CFLG_ALWAYS(x) SET_CFLG(x)\n"
+		"#define SET_NFLG_ALWAYS(x) SET_NFLG(x)\n"
+		"#ifdef NOFLAGS\n"
+		"#include \"noflags.h\"\n"
+		"#endif\n");
+}
+
+static int postfix;
+
+
+static char *decodeEA (amodes mode, wordsizes size)
+{
+	static char buffer[80];
+
+	buffer[0] = 0;
+	switch (mode){
+	case Dreg:
+		strcpy (buffer,"Dn");
+		break;
+	case Areg:
+		strcpy (buffer,"An");
+		break;
+	case Aind:
+		strcpy (buffer,"(An)");
+		break;
+	case Aipi:
+		strcpy (buffer,"(An)+");
+		break;
+	case Apdi:
+		strcpy (buffer,"-(An)");
+		break;
+	case Ad16:
+		strcpy (buffer,"(d16,An)");
+		break;
+	case Ad8r:
+		strcpy (buffer,"(d8,An,Xn)");
+		break;
+	case PC16:
+		strcpy (buffer,"(d16,PC)");
+		break;
+	case PC8r:
+		strcpy (buffer,"(d8,PC,Xn)");
+		break;
+	case absw:
+		strcpy (buffer,"(xxx).W");
+		break;
+	case absl:
+		strcpy (buffer,"(xxx).L");
+		break;
+	case imm:
+		switch (size){
+		case sz_byte:
+			strcpy (buffer,"#.B");
+			break;
+		case sz_word:
+			strcpy (buffer,"#.W");
+			break;
+		case sz_long:
+			strcpy (buffer,"#.L");
+			break;
+		default:
+			break;
+		}
+		break;
+	case imm0:
+		strcpy (buffer,"#.B");
+		break;
+	case imm1:
+		strcpy (buffer,"#.W");
+		break;
+	case imm2:
+		strcpy (buffer,"#.L");
+		break;
+	case immi:
+		strcpy (buffer,"#");
+		break;
+
+	default:
+		break;
+	}
+	return buffer;
+}
+
+static const char *m68k_cc[] = {
+	"T",
+	"F",
+	"HI",
+	"LS",
+	"CC",
+	"CS",
+	"NE",
+	"EQ",
+	"VC",
+	"VS",
+	"PL",
+	"MI",
+	"GE",
+	"LT",
+	"GT",
+	"LE"
+};
+
+static char *outopcode (int opcode)
+{
+	static char out[100];
+	struct instr *ins;
+	int i;
+
+	ins = &table68k[opcode];
+	for (i = 0; lookuptab[i].name[0]; i++) {
+		if (ins->mnemo == lookuptab[i].mnemo)
+			break;
+	}
+	{
+		char *s = ua (lookuptab[i].name);
+		strcpy (out, s);
+		xfree (s);
+	}
+	if (ins->smode == immi)
+		strcat (out, "Q");
+	if (ins->size == sz_byte)
+		strcat (out,".B");
+	if (ins->size == sz_word)
+		strcat (out,".W");
+	if (ins->size == sz_long)
+		strcat (out,".L");
+	strcat (out," ");
+	if (ins->suse)
+		strcat (out, decodeEA (ins->smode, ins->size));
+	if (ins->duse) {
+		if (ins->suse) strcat (out,",");
+		strcat (out, decodeEA (ins->dmode, ins->size));
+	}
+	if (ins->mnemo == i_DBcc || ins->mnemo == i_Scc || ins->mnemo == i_Bcc || ins->mnemo == i_TRAPcc) {
+		strcat (out, " (");
+		strcat (out, m68k_cc[table68k[opcode].cc]);
+		strcat (out, ")");
+	}
+
+	return out;
+}
+
+struct cputbl_tmp
+{
+	uae_s16 length;
+	uae_s8 disp020[2];
+	uae_u8 branch;
+};
+static struct cputbl_tmp cputbltmp[65536];
+
+static void generate_one_opcode (int rp, const char *extra)
+{
+	int idx;
+	uae_u16 smsk, dmsk;
+	unsigned int opcode = opcode_map[rp];
+	int i68000 = table68k[opcode].clev > 0;
+
+	if (table68k[opcode].mnemo == i_ILLG
+		|| table68k[opcode].clev > cpu_level)
+		return;
+
+	for (idx = 0; lookuptab[idx].name[0]; idx++) {
+		if (table68k[opcode].mnemo == lookuptab[idx].mnemo)
+			break;
+	}
+
+	if (table68k[opcode].handler != -1)
+		return;
+
+	if (opcode_next_clev[rp] != cpu_level) {
+		char *name = ua (lookuptab[idx].name);
+		if (generate_stbl)
+			fprintf (stblfile, "{ %sCPUFUNC(op_%04x_%d%s), 0x%04x, %d, { %d, %d }, %d }, /* %s */\n",
+				(using_ce || using_ce020) ? "(cpuop_func*)" : "",
+				opcode, opcode_last_postfix[rp],
+				extra, opcode,
+				cputbltmp[opcode].length, cputbltmp[opcode].disp020[0], cputbltmp[opcode].disp020[1], cputbltmp[opcode].branch, name);
+		xfree (name);
+		return;
+	}
+	fprintf (headerfile, "extern %s op_%04x_%d%s_nf;\n",
+		(using_ce || using_ce020) ? "cpuop_func_ce" : "cpuop_func", opcode, postfix, extra);
+	fprintf (headerfile, "extern %s op_%04x_%d%s_ff;\n",
+		(using_ce || using_ce020) ? "cpuop_func_ce" : "cpuop_func", opcode, postfix, extra);
+	printf ("/* %s */\n", outopcode (opcode));
+	if (i68000)
+		printf("#ifndef CPUEMU_68000_ONLY\n");
+	printf ("%s REGPARAM2 CPUFUNC(op_%04x_%d%s)(uae_u32 opcode)\n{\n", (using_ce || using_ce020) ? "void" : "uae_u32", opcode, postfix, extra);
+	if (using_simple_cycles)
+		printf("\tint count_cycles = 0;\n");
+
+	switch (table68k[opcode].stype) {
+	case 0: smsk = 7; break;
+	case 1: smsk = 255; break;
+	case 2: smsk = 15; break;
+	case 3: smsk = 7; break;
+	case 4: smsk = 7; break;
+	case 5: smsk = 63; break;
+	case 7: smsk = 3; break;
+	default: term ();
+	}
+	dmsk = 7;
+
+	next_cpu_level = -1;
+	if (table68k[opcode].suse
+		&& table68k[opcode].smode != imm && table68k[opcode].smode != imm0
+		&& table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
+		&& table68k[opcode].smode != absw && table68k[opcode].smode != absl
+		&& table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
+	{
+		if (table68k[opcode].spos == -1) {
+			if (((int) table68k[opcode].sreg) >= 128)
+				printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
+			else
+				printf ("\tuae_u32 srcreg = %d;\n", (int) table68k[opcode].sreg);
+		} else {
+			char source[100];
+			int pos = table68k[opcode].spos;
+
+			if (pos)
+				sprintf (source, "((opcode >> %d) & %d)", pos, smsk);
+			else
+				sprintf (source, "(opcode & %d)", smsk);
+
+			if (table68k[opcode].stype == 3)
+				printf ("\tuae_u32 srcreg = imm8_table[%s];\n", source);
+			else if (table68k[opcode].stype == 1)
+				printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
+			else
+				printf ("\tuae_u32 srcreg = %s;\n", source);
+		}
+	}
+	if (table68k[opcode].duse
+		/* Yes, the dmode can be imm, in case of LINK or DBcc */
+		&& table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
+		&& table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
+		&& table68k[opcode].dmode != absw && table68k[opcode].dmode != absl)
+	{
+		if (table68k[opcode].dpos == -1) {
+			if (((int) table68k[opcode].dreg) >= 128)
+				printf ("\tuae_u32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
+			else
+				printf ("\tuae_u32 dstreg = %d;\n", (int) table68k[opcode].dreg);
+		} else {
+			int pos = table68k[opcode].dpos;
+			if (pos)
+				printf ("\tuae_u32 dstreg = (opcode >> %d) & %d;\n",
+				pos, dmsk);
+			else
+				printf ("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
+		}
+	}
+	need_endlabel = 0;
+	endlabelno++;
+	sprintf (endlabelstr, "l_%d", endlabelno);
+	count_read = count_write = count_ncycles = count_cycles = 0;
+	count_cycles_ce020 = 0;
+	count_read_ea = count_write_ea = count_cycles_ea = 0;
+	gen_opcode (opcode);
+	if (need_endlabel)
+		printf ("%s: ;\n", endlabelstr);
+	clearmmufixup (0);
+	clearmmufixup (1);
+	if (using_ce || using_prefetch) {
+		if (count_read + count_write + count_cycles == 0)
+			count_cycles = 4;
+		returncycles ("", (count_read + count_write) * 4 + count_cycles);
+		printf ("}");
+		printf (" /* %d%s (%d/%d)",
+			(count_read + count_write) * 4 + count_cycles, count_ncycles ? "+" : "", count_read, count_write);
+		printf (" */\n");
+#ifdef WINUAE_FOR_HATARI
+		insn_n_cycles = (count_read + count_write) * 4 + count_cycles;
+#endif
+//printf ( "pom_%d %s %x %d\n" , postfix , lookuptab[idx].name , opcode , (count_read + count_write) * 4 + count_cycles );
+	} else if (count_read + count_write) {
+		returncycles ("", (count_read + count_write) * 4 + count_cycles);
+		printf ("}");
+		printf("\n");
+#ifdef WINUAE_FOR_HATARI
+		insn_n_cycles = (count_read + count_write) * 4 + count_cycles;
+#endif
+//printf ( "pom_%d %s %x %d\n" , postfix , lookuptab[idx].name , opcode , (count_read + count_write) * 4 + count_cycles );
+	} else {
+		returncycles ("", insn_n_cycles);
+		printf ("}");
+		printf("\n");
+//printf ( "pom_%d %s %x %d\n" , postfix , lookuptab[idx].name , opcode , insn_n_cycles );
+	}
+	printf ("\n");
+	if (i68000)
+		printf("#endif\n");
+	opcode_next_clev[rp] = next_cpu_level;
+	opcode_last_postfix[rp] = postfix;
+
+	if ((opcode & 0xf000) == 0xf000)
+		m68k_pc_total = -1;
+	cputbltmp[opcode].length = m68k_pc_total;
+
+	cputbltmp[opcode].disp020[0] = 0;
+	if (genamode8r_offset[0] > 0)
+		cputbltmp[opcode].disp020[0] = m68k_pc_total - genamode8r_offset[0] + 2;
+	cputbltmp[opcode].disp020[1] = 0;
+	if (genamode8r_offset[1] > 0)
+		cputbltmp[opcode].disp020[1] = m68k_pc_total - genamode8r_offset[1] + 2;
+
+	cputbltmp[opcode].branch = branch_inst;
+
+#ifdef WINUAE_FOR_HATARI
+        /* Hatari only : Now patch in the instruction cycles at the beginning of the function: */
+	if (!using_ce020) {
+		fseek(stdout, nCurInstrCycPos, SEEK_SET);
+		printf("%d;", insn_n_cycles);
+		fseek(stdout, 0, SEEK_END);
+	}
+#endif
+
+	if (generate_stbl) {
+		char *name = ua (lookuptab[idx].name);
+		if (i68000)
+			fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n");
+		fprintf (stblfile, "{ %sCPUFUNC(op_%04x_%d%s), 0x%04x, %d, { %d, %d }, %d }, /* %s */\n",
+			(using_ce || using_ce020) ? "(cpuop_func*)" : "",
+			opcode, postfix, extra, opcode,
+			cputbltmp[opcode].length, cputbltmp[opcode].disp020[0], cputbltmp[opcode].disp020[1], cputbltmp[opcode].branch, name);
+		if (i68000)
+			fprintf (stblfile, "#endif\n");
+		xfree (name);
+	}
+}
+
+static void generate_func (const char *extra)
+{
+	int j, rp;
+
+	/* sam: this is for people with low memory (eg. me :)) */
+	printf ("\n"
+		"#if !defined(PART_1) && !defined(PART_2) && "
+		"!defined(PART_3) && !defined(PART_4) && "
+		"!defined(PART_5) && !defined(PART_6) && "
+		"!defined(PART_7) && !defined(PART_8)"
+		"\n"
+		"#define PART_1 1\n"
+		"#define PART_2 1\n"
+		"#define PART_3 1\n"
+		"#define PART_4 1\n"
+		"#define PART_5 1\n"
+		"#define PART_6 1\n"
+		"#define PART_7 1\n"
+		"#define PART_8 1\n"
+		"#endif\n\n");
+
+	rp = 0;
+	for(j = 1; j <= 8; ++j) {
+		int k = (j * nr_cpuop_funcs) / 8;
+		printf ("#ifdef PART_%d\n",j);
+		for (; rp < k; rp++)
+			generate_one_opcode (rp, extra);
+		printf ("#endif\n\n");
+	}
+
+	if (generate_stbl)
+		fprintf (stblfile, "{ 0, 0 }};\n");
+}
+
+static void generate_cpu (int id, int mode)
+{
+	char fname[100];
+	const char *extra, *extraup;
+	static int postfix2 = -1;
+	int rp;
+
+	using_tracer = mode;
+	extra = "";
+	extraup = "";
+	if (using_tracer) {
+		extra = "_t";
+		extraup = "_T";
+	}
+
+	postfix = id;
+	if (id == 0 || id == 11 || id == 13 || id == 20 || id == 21 || id == 22 || id == 23 || id == 24 || id == 31 || id == 32 || id == 33 || id == 40) {
+		if (generate_stbl)
+			fprintf (stblfile, "#ifdef CPUEMU_%d%s\n", postfix, extraup);
+		postfix2 = postfix;
+		sprintf (fname, "cpuemu_%d%s.c", postfix, extra);
+		if (freopen (fname, "wb", stdout) == NULL) {
+			abort ();
+		}
+		generate_includes (stdout, id);
+	}
+
+	using_indirect = 0;
+	using_exception_3 = 1;
+	using_prefetch = 0;
+	using_prefetch_020 = 0;
+	using_ce = 0;
+	using_ce020 = 0;
+	using_mmu = 0;
+	using_waitstates = 0;
+	memory_cycle_cnt = 4;
+	mmu_postfix = "";
+	using_simple_cycles = 0;
+
+#ifdef WINUAE_FOR_HATARI
+	using_bus_error = 1;				/* Enable code to handle bus error */
+#endif
+
+	if (id == 11 || id == 12) { // 11 = 68010 prefetch, 12 = 68000 prefetch
+		cpu_level = id == 11 ? 1 : 0;
+		using_prefetch = 1;
+		using_exception_3 = 1;
+		using_simple_cycles = 1;
+		if (id == 11) {
+			read_counts ();
+			for (rp = 0; rp < nr_cpuop_funcs; rp++)
+				opcode_next_clev[rp] = cpu_level;
+		}
+	} else if (id == 13 || id == 14) { // 13 = 68010 cycle-exact, 14 = 68000 cycle-exact
+		cpu_level = id == 13 ? 1 : 0;
+		using_prefetch = 1;
+		using_exception_3 = 1;
+		using_ce = 1;
+		if (id == 13) {
+			read_counts ();
+			for (rp = 0; rp < nr_cpuop_funcs; rp++)
+				opcode_next_clev[rp] = cpu_level;
+		}
+	} else if (id == 20) { // 68020 prefetch
+		cpu_level = 2;
+		using_prefetch_020 = 1;
+		read_counts ();
+		for (rp = 0; rp < nr_cpuop_funcs; rp++)
+			opcode_next_clev[rp] = cpu_level;
+	} else if (id == 21) { // 68020 cycle-exact
+		cpu_level = 2;
+		using_ce020 = 1;
+		using_prefetch_020 = 1;
+		// timing tables are from 030 which has 2
+		// clock memory accesses, 68020 has 3 clock
+		// memory accesses
+		using_waitstates = 1;
+		memory_cycle_cnt = 3;
+		read_counts ();
+		for (rp = 0; rp < nr_cpuop_funcs; rp++)
+			opcode_next_clev[rp] = cpu_level;
+	} else if (id == 22) { // 68030 prefetch
+		cpu_level = 3;
+		using_prefetch_020 = 2;
+		read_counts ();
+		for (rp = 0; rp < nr_cpuop_funcs; rp++)
+			opcode_next_clev[rp] = cpu_level;
+	} else if (id == 23) { // 68030 "cycle-exact"
+		cpu_level = 3;
+		using_ce020 = 2;
+		using_prefetch_020 = 2;
+		memory_cycle_cnt = 2;
+		read_counts ();
+		for (rp = 0; rp < nr_cpuop_funcs; rp++)
+			opcode_next_clev[rp] = cpu_level;
+	} else if (id == 24 || id == 25) { // 68040/060 "cycle-exact"
+		cpu_level = id == 24 ? 5 : 4;
+		using_ce020 = 3;
+		using_prefetch_020 = 3;
+		memory_cycle_cnt = 0;
+		if (id == 24) {
+			read_counts();
+			for (rp = 0; rp < nr_cpuop_funcs; rp++)
+				opcode_next_clev[rp] = cpu_level;
+		}
+	} else if (id == 31) { // 31 = 68040 MMU
+		mmu_postfix = "040";
+		cpu_level = 4;
+		using_mmu = 68040;
+		read_counts ();
+		for (rp = 0; rp < nr_cpuop_funcs; rp++)
+			opcode_next_clev[rp] = cpu_level;
+	} else if (id == 32) { // 32 = 68030 MMU
+		mmu_postfix = "030";
+		cpu_level = 3;
+		using_mmu = 68030;
+		read_counts ();
+		for (rp = 0; rp < nr_cpuop_funcs; rp++)
+			opcode_next_clev[rp] = cpu_level;
+	} else if (id == 33) { // 33 = 68060 MMU
+		mmu_postfix = "060";
+		cpu_level = 5;
+		using_mmu = 68060;
+		read_counts ();
+		for (rp = 0; rp < nr_cpuop_funcs; rp++)
+			opcode_next_clev[rp] = cpu_level;
+	} else if (id < 6) {
+		cpu_level = 5 - (id - 0); // "generic" + direct
+	} else if (id >= 40 && id < 46) {
+		cpu_level = 5 - (id - 40); // "generic" + indirect
+		if (id == 40) {
+			read_counts();
+			for (rp = 0; rp < nr_cpuop_funcs; rp++)
+				opcode_next_clev[rp] = cpu_level;
+		}
+	}
+	using_indirect = using_ce || using_ce020 || using_prefetch_020 || id >= 40;
+
+	if (generate_stbl) {
+		if ((id > 0 && id < 6) || (id >= 20 && id < 40) || (id > 40 && id < 46))
+			fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n");
+		fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d%s)[] = {\n", postfix, extra);
+	}
+	endlabelno = id * 10000;
+	generate_func (extra);
+	if (generate_stbl) {
+		if ((id > 0 && id < 6) || (id >= 20 && id < 40) || (id > 40 && id < 46))
+			fprintf (stblfile, "#endif /* CPUEMU_68000_ONLY */\n");
+		if (postfix2 >= 0)
+			fprintf (stblfile, "#endif /* CPUEMU_%d%s */\n", postfix2, extraup);
+	}
+	postfix2 = -1;
+}
+
+int main(int argc, char *argv[])
+{
+	int i;
+
+	read_table68k ();
+	do_merges ();
+
+	opcode_map =  xmalloc (int, nr_cpuop_funcs);
+	opcode_last_postfix = xmalloc (int, nr_cpuop_funcs);
+	opcode_next_clev = xmalloc (int, nr_cpuop_funcs);
+	counts = xmalloc (unsigned long, 65536);
+	read_counts ();
+
+	/* It would be a lot nicer to put all in one file (we'd also get rid of
+	* cputbl.h that way), but cpuopti can't cope.  That could be fixed, but
+	* I don't dare to touch the 68k version.  */
+
+	headerfile = fopen ("cputbl.h", "wb");
+
+	stblfile = fopen ("cpustbl.c", "wb");
+	generate_includes (stblfile, 0);
+
+	for (i = 0; i <= 45; i++) {
+		if ((i >= 6 && i < 11) || (i > 14 && i < 20) || (i > 25 && i < 31) || (i > 33 && i < 40))
+			continue;
+		generate_stbl = 1;
+		generate_cpu (i, 0);
+	}
+
+	free (table68k);
+	return 0;
+}
+
+void write_log (const TCHAR *format,...)
+{
+}
diff --git a/src/cpu/hatari-glue.c b/src/cpu/hatari-glue.c
new file mode 100644
index 0000000..d5c4fe9
--- /dev/null
+++ b/src/cpu/hatari-glue.c
@@ -0,0 +1,260 @@
+/*
+  Hatari - hatari-glue.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  This file contains some code to glue the UAE CPU core to the rest of the
+  emulator and Hatari's "illegal" opcodes.
+*/
+const char HatariGlue_fileid[] = "Hatari hatari-glue.c : " __DATE__ " " __TIME__;
+
+
+#include 
+
+#include "main.h"
+#include "configuration.h"
+#include "cycInt.h"
+#include "tos.h"
+#include "gemdos.h"
+#include "natfeats.h"
+#include "cart.h"
+#include "vdi.h"
+#include "stMemory.h"
+#include "ikbd.h"
+#include "screen.h"
+#include "video.h"
+#include "psg.h"
+#include "mfp.h"
+#include "fdc.h"
+
+#include "sysdeps.h"
+#include "options_cpu.h"
+#include "maccess.h"
+#include "memory.h"
+#include "m68000.h"
+#include "newcpu.h"
+#include "cpu_prefetch.h"
+#include "hatari-glue.h"
+
+
+struct uae_prefs currprefs, changed_prefs;
+
+int pendingInterrupts = 0;
+
+
+/**
+ * Reset custom chips
+ * In case the RESET instruction is called, we must reset all the peripherals
+ * connected to the CPU's reset pin.
+ */
+void customreset(void)
+{
+	pendingInterrupts = 0;
+
+	/* Reset the IKBD */
+	IKBD_Reset ( false );
+
+	/* Reseting the GLUE video chip should also set freq/res register to 0 */
+	Video_Reset_Glue ();
+
+        /* Reset the YM2149 (stop any sound) */
+        PSG_Reset ();
+
+	/* Reset the MFP */
+	MFP_Reset ();
+
+	/* Reset the FDC */
+	FDC_Reset ( false );
+}
+
+
+/**
+ * Return interrupt number (1 - 7), -1 means no interrupt.
+ * Note that the interrupt stays pending if it can't be executed yet
+ * due to the interrupt level field in the SR.
+ */
+int intlev(void)
+{
+	if ( pendingInterrupts & (1 << 6) )		/* MFP/DSP interrupt ? */
+		return 6;
+	else if ( pendingInterrupts & (1 << 4) )	/* VBL interrupt ? */
+		return 4;
+	else if ( pendingInterrupts & (1 << 2) )	/* HBL interrupt ? */
+		return 2;
+
+	return -1;
+}
+
+/**
+ * Initialize 680x0 emulation
+ */
+int Init680x0(void)
+{
+	currprefs.cpu_level = changed_prefs.cpu_level = ConfigureParams.System.nCpuLevel;
+
+	switch (currprefs.cpu_level) {
+		case 0 : currprefs.cpu_model = 68000; break;
+		case 1 : currprefs.cpu_model = 68010; break;
+		case 2 : currprefs.cpu_model = 68020; break;
+		case 3 : currprefs.cpu_model = 68030; break;
+		case 4 : currprefs.cpu_model = 68040; break;
+		case 5 : currprefs.cpu_model = 68060; break;
+		default: fprintf (stderr, "Init680x0() : Error, cpu_level unknown\n");
+	}
+	
+	currprefs.cpu_compatible = changed_prefs.cpu_compatible = ConfigureParams.System.bCompatibleCpu;
+	currprefs.address_space_24 = changed_prefs.address_space_24 = ConfigureParams.System.bAddressSpace24;
+	currprefs.cpu_cycle_exact = changed_prefs.cpu_cycle_exact = ConfigureParams.System.bCycleExactCpu;
+	currprefs.fpu_model = changed_prefs.fpu_model = ConfigureParams.System.n_FPUType;
+	currprefs.fpu_strict = changed_prefs.fpu_strict = ConfigureParams.System.bCompatibleFPU;
+
+	/* Set the MMU model by taking the same value as CPU model */
+	/* MMU is only supported for CPU >=68030 */
+	currprefs.mmu_model = changed_prefs.mmu_model = 0;				/* MMU disabled by default */
+	if ( ( ConfigureParams.System.bMMU ) && ( currprefs.cpu_model >= 68030 ) )
+		currprefs.mmu_model = changed_prefs.mmu_model = currprefs.cpu_model;	/* MMU enabled */
+
+	init_m68k();
+
+	return true;
+}
+
+
+/**
+ * Deinitialize 680x0 emulation
+ */
+void Exit680x0(void)
+{
+	memory_uninit();
+
+	free(table68k);
+	table68k = NULL;
+}
+
+
+/**
+ * Execute a 'NOP' opcode (increment PC by 2 bytes and take care
+ * of prefetch at the CPU level depending on the current CPU mode)
+ * This is used to return from Gemdos / Natfeats interception, by ignoring
+ * the intercepted opcode and executing a NOP instead once the work has been done.
+ */
+static void	CpuDoNOP ( void )
+{
+	(*cpufunctbl[0X4E71])(0x4E71);
+}
+
+
+/**
+ * This function will be called at system init by the cartridge routine
+ * (after gemdos init, before booting floppies).
+ * The GEMDOS vector (#$84) is setup and we also initialize the connected
+ * drive mask and Line-A  variables (for an extended VDI resolution) from here.
+ */
+uae_u32 OpCode_SysInit(uae_u32 opcode)
+{
+	/* Add any drives mapped by TOS in the interim */
+	ConnectedDriveMask |= STMemory_ReadLong(0x4c2);
+	/* Initialize the connected drive mask */
+	STMemory_WriteLong(0x4c2, ConnectedDriveMask);
+
+	if (!bInitGemDOS)
+	{
+		/* Init on boot - see cart.c */
+		GemDOS_Boot();
+
+		/* Update LineA for extended VDI res
+		 * D0: LineA base, A1: Font base
+		 */
+		VDI_LineA(regs.regs[0], regs.regs[9]);
+	}
+
+	CpuDoNOP ();
+	return 4 * CYCLE_UNIT / 2;
+}
+
+
+/**
+ * Intercept GEMDOS calls.
+ * Used for GEMDOS HD emulation (see gemdos.c).
+ */
+uae_u32 OpCode_GemDos(uae_u32 opcode)
+{
+	GemDOS_OpCode();    /* handler code in gemdos.c */
+
+	CpuDoNOP ();
+	return 4 * CYCLE_UNIT / 2;
+}
+
+
+/**
+ * This is called after completion of each VDI call
+ */
+uae_u32 OpCode_VDI(uae_u32 opcode)
+{
+	Uint32 pc = M68000_GetPC();
+
+	/* this is valid only after VDI trap, called from cartridge code */
+	if (VDI_OldPC && pc >= 0xfa0000 && pc < 0xfc0000)
+	{
+		VDI_Complete();
+
+		/* Set PC back to where originated from to continue instruction decoding */
+		m68k_setpc(VDI_OldPC);
+		VDI_OldPC = 0;
+	}
+	else
+	{
+		/* illegal instruction */
+		op_illg(opcode);
+	}
+
+	fill_prefetch();
+	return 4 * CYCLE_UNIT / 2;
+}
+
+
+/**
+ * Emulator Native Features ID opcode interception.
+ */
+uae_u32 OpCode_NatFeat_ID(uae_u32 opcode)
+{
+	Uint32 stack = Regs[REG_A7] + SIZE_LONG;	/* skip return address */
+
+	if (NatFeat_ID(stack, &(Regs[REG_D0]))) {
+		CpuDoNOP ();
+	}
+	return 4 * CYCLE_UNIT / 2;
+}
+
+/**
+ * Emulator Native Features call opcode interception.
+ */
+uae_u32 OpCode_NatFeat_Call(uae_u32 opcode)
+{
+	Uint32 stack = Regs[REG_A7] + SIZE_LONG;	/* skip return address */
+	Uint16 SR = M68000_GetSR();
+	bool super;
+
+	super = ((SR & SR_SUPERMODE) == SR_SUPERMODE);
+	if (NatFeat_Call(stack, super, &(Regs[REG_D0]))) {
+		CpuDoNOP ();
+	}
+	return 4 * CYCLE_UNIT / 2;
+}
+
+
+
+
+
+TCHAR* buf_out (TCHAR *buffer, int *bufsize, const TCHAR *format, ...) {
+    va_list parms;
+    if (buffer == NULL) {
+        return 0;
+    }
+    va_start (parms, format);
+    vsnprintf (buffer, (*bufsize) - 1, format, parms);
+    va_end (parms);
+    *bufsize -= _tcslen (buffer);
+    return buffer + _tcslen (buffer);
+}
diff --git a/src/cpu/hatari-glue.h b/src/cpu/hatari-glue.h
new file mode 100644
index 0000000..50a7baa
--- /dev/null
+++ b/src/cpu/hatari-glue.h
@@ -0,0 +1,31 @@
+/*
+  Hatari - hatari-glue.h
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+*/
+
+#ifndef HATARI_GLUE_H
+#define HATARI_GLUE_H
+
+#include "sysdeps.h"
+#include "options_cpu.h"
+#include "cycles.h"
+
+extern int pendingInterrupts;
+
+extern void customreset(void);
+extern int intlev (void);
+extern int Init680x0(void);
+extern void Exit680x0(void);
+
+extern uae_u32 OpCode_GemDos(uae_u32 opcode);
+extern uae_u32 OpCode_SysInit(uae_u32 opcode);
+extern uae_u32 OpCode_VDI(uae_u32 opcode);
+extern uae_u32 OpCode_NatFeat_ID(uae_u32 opcode);
+extern uae_u32 OpCode_NatFeat_Call(uae_u32 opcode);
+
+#define write_log printf
+
+
+#endif /* HATARI_GLUE_H */
diff --git a/src/cpu/jit/codegen_x86.c b/src/cpu/jit/codegen_x86.c
new file mode 100644
index 0000000..e2c87bf
--- /dev/null
+++ b/src/cpu/jit/codegen_x86.c
@@ -0,0 +1,4754 @@
+/*
+ *  compiler/codegen_x86.cpp - IA-32 code generator
+ *
+ *  Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ *
+ *  Adaptation for Basilisk II and improvements, copyright 2000-2005
+ *    Gwenole Beauchesne
+ *
+ *  Basilisk II (C) 1997-2008 Christian Bauer
+ *
+ *  Portions related to CPU detection come from linux/arch/i386/kernel/setup.c
+ *  
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/* This should eventually end up in machdep/, but for now, x86 is the
+   only target, and it's easier this way... */
+
+#include "flags_x86.h"
+
+/*************************************************************************
+ * Some basic information about the the target CPU                       *
+ *************************************************************************/
+
+#define EAX_INDEX 0
+#define ECX_INDEX 1
+#define EDX_INDEX 2
+#define EBX_INDEX 3
+#define ESP_INDEX 4
+#define EBP_INDEX 5
+#define ESI_INDEX 6
+#define EDI_INDEX 7
+#if defined(__x86_64__)
+#define R8_INDEX  8
+#define R9_INDEX  9
+#define R10_INDEX 10
+#define R11_INDEX 11
+#define R12_INDEX 12
+#define R13_INDEX 13
+#define R14_INDEX 14
+#define R15_INDEX 15
+#endif
+/* XXX this has to match X86_Reg8H_Base + 4 */
+#define AH_INDEX (0x10+4+EAX_INDEX)
+#define CH_INDEX (0x10+4+ECX_INDEX)
+#define DH_INDEX (0x10+4+EDX_INDEX)
+#define BH_INDEX (0x10+4+EBX_INDEX)
+
+/* The register in which subroutines return an integer return value */
+#define REG_RESULT EAX_INDEX
+
+/* The registers subroutines take their first and second argument in */
+#if defined( _MSC_VER ) && !defined( USE_NORMAL_CALLING_CONVENTION )
+/* Handle the _fastcall parameters of ECX and EDX */
+#define REG_PAR1 ECX_INDEX
+#define REG_PAR2 EDX_INDEX
+#elif defined(__x86_64__)
+#define REG_PAR1 EDI_INDEX
+#define REG_PAR2 ESI_INDEX
+#else
+#define REG_PAR1 EAX_INDEX
+#define REG_PAR2 EDX_INDEX
+#endif
+
+#define REG_PC_PRE EAX_INDEX /* The register we use for preloading regs.pc_p */
+#if defined( _MSC_VER ) && !defined( USE_NORMAL_CALLING_CONVENTION )
+#define REG_PC_TMP EAX_INDEX
+#else
+#define REG_PC_TMP ECX_INDEX /* Another register that is not the above */
+#endif
+
+#define SHIFTCOUNT_NREG ECX_INDEX  /* Register that can be used for shiftcount.
+			      -1 if any reg will do */
+#define MUL_NREG1 EAX_INDEX /* %eax will hold the low 32 bits after a 32x32 mul */
+#define MUL_NREG2 EDX_INDEX /* %edx will hold the high 32 bits */
+
+#define STACK_ALIGN		16
+#define STACK_OFFSET	sizeof(void *)
+
+uae_s8 always_used[]={4,-1};
+#if defined(__x86_64__)
+uae_s8 can_byte[]={0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,-1};
+uae_s8 can_word[]={0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,-1};
+#else
+uae_s8 can_byte[]={0,1,2,3,-1};
+uae_s8 can_word[]={0,1,2,3,5,6,7,-1};
+#endif
+
+#if USE_OPTIMIZED_CALLS
+/* Make sure interpretive core does not use cpuopti */
+uae_u8 call_saved[]={0,0,0,1,1,1,1,1};
+#error FIXME: code not ready
+#else
+/* cpuopti mutate instruction handlers to assume registers are saved
+   by the caller */
+uae_u8 call_saved[]={0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0};
+#endif
+
+/* This *should* be the same as call_saved. But:
+   - We might not really know which registers are saved, and which aren't,
+     so we need to preserve some, but don't want to rely on everyone else
+     also saving those registers
+   - Special registers (such like the stack pointer) should not be "preserved"
+     by pushing, even though they are "saved" across function calls
+*/
+#if defined(__x86_64__)
+/* callee-saved registers as defined by Linux AMD64 ABI: rbx, rbp, rsp, r12 - r15 */
+/* preserve r11 because it's generally used to hold pointers to functions */
+static const uae_u8 need_to_preserve[]={0,0,0,1,0,1,0,0,0,0,0,1,1,1,1,1};
+#else
+/* callee-saved registers as defined by System V IA-32 ABI: edi, esi, ebx, ebp */
+static const uae_u8 need_to_preserve[]={0,0,0,1,0,1,1,1};
+#endif
+
+/* Whether classes of instructions do or don't clobber the native flags */
+#define CLOBBER_MOV
+#define CLOBBER_LEA
+#define CLOBBER_CMOV
+#define CLOBBER_POP
+#define CLOBBER_PUSH
+#define CLOBBER_SUB  clobber_flags()
+#define CLOBBER_SBB  clobber_flags()
+#define CLOBBER_CMP  clobber_flags()
+#define CLOBBER_ADD  clobber_flags()
+#define CLOBBER_ADC  clobber_flags()
+#define CLOBBER_AND  clobber_flags()
+#define CLOBBER_OR   clobber_flags()
+#define CLOBBER_XOR  clobber_flags()
+
+#define CLOBBER_ROL  clobber_flags()
+#define CLOBBER_ROR  clobber_flags()
+#define CLOBBER_SHLL clobber_flags()
+#define CLOBBER_SHRL clobber_flags()
+#define CLOBBER_SHRA clobber_flags()
+#define CLOBBER_TEST clobber_flags()
+#define CLOBBER_CL16 
+#define CLOBBER_CL8  
+#define CLOBBER_SE32
+#define CLOBBER_SE16
+#define CLOBBER_SE8
+#define CLOBBER_ZE32
+#define CLOBBER_ZE16
+#define CLOBBER_ZE8
+#define CLOBBER_SW16 clobber_flags()
+#define CLOBBER_SW32
+#define CLOBBER_SETCC
+#define CLOBBER_MUL  clobber_flags()
+#define CLOBBER_BT   clobber_flags()
+#define CLOBBER_BSF  clobber_flags()
+
+/* The older code generator is now deprecated.  */
+#define USE_NEW_RTASM 1
+
+#if USE_NEW_RTASM
+
+#if defined(__x86_64__)
+#define X86_TARGET_64BIT		1
+/* The address override prefix causes a 5 cycles penalty on Intel Core
+   processors. Another solution would be to decompose the load in an LEA,
+   MOV (to zero-extend), MOV (from memory): is it better? */
+#define ADDR32					x86_emit_byte(0x67),
+#else
+#define ADDR32					/**/
+#endif
+#define X86_FLAT_REGISTERS		0
+#define X86_OPTIMIZE_ALU		1
+#define X86_OPTIMIZE_ROTSHI		1
+#include "codegen_x86.h"
+
+#define x86_emit_byte(B)		emit_byte(B)
+#define x86_emit_word(W)		emit_word(W)
+#define x86_emit_long(L)		emit_long(L)
+#define x86_emit_quad(Q)		emit_quad(Q)
+#define x86_get_target()		get_target()
+#define x86_emit_failure(MSG)	jit_fail(MSG, __FILE__, __LINE__, __FUNCTION__)
+
+static void jit_fail(const char *msg, const char *file, int line, const char *function)
+{
+	fprintf(stderr, "JIT failure in function %s from file %s at line %d: %s\n",
+			function, file, line, msg);
+	abort();
+}
+
+LOWFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r))
+{
+#if defined(__x86_64__)
+	PUSHQr(r);
+#else
+	PUSHLr(r);
+#endif
+}
+LENDFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r))
+
+LOWFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
+{
+#if defined(__x86_64__)
+	POPQr(r);
+#else
+	POPLr(r);
+#endif
+}
+LENDFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
+
+LOWFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
+{
+#if defined(__x86_64__)
+	POPQm(d, X86_NOREG, X86_NOREG, 1);
+#else
+	POPLm(d, X86_NOREG, X86_NOREG, 1);
+#endif
+}
+LENDFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
+
+LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
+{
+	BTLir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b))
+{
+	BTLrr(b, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b))
+
+LOWFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i))
+{
+	BTCLir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b))
+{
+	BTCLrr(b, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b))
+
+LOWFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i))
+{
+	BTRLir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b))
+{
+	BTRLrr(b, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b))
+
+LOWFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i))
+{
+	BTSLir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b))
+{
+	BTSLrr(b, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b))
+
+LOWFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i))
+{
+	SUBWir(i, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i))
+
+LOWFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s))
+{
+	MOVLmr(s, X86_NOREG, X86_NOREG, 1, d);
+}
+LENDFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s))
+
+LOWFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s))
+{
+	MOVLim(s, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s))
+
+LOWFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s))
+{
+	MOVWim(s, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s))
+
+LOWFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s))
+{
+	MOVBim(s, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s))
+
+LOWFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i))
+{
+	ROLBim(i, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i))
+{
+	ROLBir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i))
+{
+	ROLWir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i))
+{
+	ROLLir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r))
+{
+	ROLLrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r))
+{
+	ROLWrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r))
+{
+	ROLBrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r))
+{
+	SHLLrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r))
+{
+	SHLWrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r))
+{
+	SHLBrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i))
+{
+	RORBir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i))
+{
+	RORWir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i))
+
+LOWFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s))
+{
+	ORLmr(s, X86_NOREG, X86_NOREG, 1, d);
+}
+LENDFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s))
+
+LOWFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i))
+{
+	RORLir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r))
+{
+	RORLrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r))
+{
+	RORWrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r))
+{
+	RORBrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r))
+{
+	SHRLrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r))
+{
+	SHRWrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r))
+{
+	SHRBrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r))
+{
+	SARLrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r))
+{
+	SARWrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r))
+{
+	SARBrr(r, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i))
+{
+	SHLLir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i))
+{
+	SHLWir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i))
+{
+	SHLBir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i))
+{
+	SHRLir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i))
+{
+	SHRWir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i))
+{
+	SHRBir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i))
+{
+	SARLir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i))
+{
+	SARWir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i))
+{
+	SARBir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i))
+
+LOWFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah))
+{
+	SAHF();
+}
+LENDFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah))
+
+LOWFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax))
+{
+	CPUID();
+}
+LENDFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax))
+
+LOWFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah))
+{
+	LAHF();
+}
+LENDFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah))
+
+LOWFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc))
+{
+	SETCCir(cc, d);
+}
+LENDFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc))
+
+LOWFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc))
+{
+	SETCCim(cc, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc))
+
+LOWFUNC(READ,NONE,3,raw_cmov_b_rr,(RW1 d, R1 s, IMM cc))
+{
+	/* replacement using branch and mov */
+	int8 *target_p = (int8 *)x86_get_target() + 1;
+	JCCSii(cc^1, 0);
+	MOVBrr(s, d);
+	*target_p = (uintptr)x86_get_target() - ((uintptr)target_p + 1);
+}
+LENDFUNC(READ,NONE,3,raw_cmov_b_rr,(RW1 d, R1 s, IMM cc))
+
+LOWFUNC(READ,NONE,3,raw_cmov_w_rr,(RW2 d, R2 s, IMM cc))
+{
+	if (have_cmov)
+		CMOVWrr(cc, s, d);
+	else { /* replacement using branch and mov */
+		int8 *target_p = (int8 *)x86_get_target() + 1;
+		JCCSii(cc^1, 0);
+		MOVWrr(s, d);
+	    *target_p = (uintptr)x86_get_target() - ((uintptr)target_p + 1);
+	}
+}
+LENDFUNC(READ,NONE,3,raw_cmov_w_rr,(RW2 d, R2 s, IMM cc))
+
+LOWFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc))
+{
+	if (have_cmov)
+		CMOVLrr(cc, s, d);
+	else { /* replacement using branch and mov */
+		int8 *target_p = (int8 *)x86_get_target() + 1;
+		JCCSii(cc^1, 0);
+		MOVLrr(s, d);
+	    *target_p = (uintptr)x86_get_target() - ((uintptr)target_p + 1);
+	}
+}
+LENDFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc))
+
+LOWFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s))
+{
+	BSFLrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s))
+
+LOWFUNC(NONE,NONE,2,raw_sign_extend_32_rr,(W4 d, R4 s))
+{
+	MOVSLQrr(s, d);
+}
+LENDFUNC(NONE,NONE,2,raw_sign_extend_32_rr,(W4 d, R4 s))
+
+LOWFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s))
+{
+	MOVSWLrr(s, d);
+}
+LENDFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s))
+
+LOWFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s))
+{
+	MOVSBLrr(s, d);
+}
+LENDFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s))
+
+LOWFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s))
+{
+	MOVZWLrr(s, d);
+}
+LENDFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s))
+
+LOWFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s))
+{
+	MOVZBLrr(s, d);
+}
+LENDFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s))
+
+LOWFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s))
+{
+	IMULLrr(s, d);
+}
+LENDFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s))
+
+LOWFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s))
+{
+	if (d!=MUL_NREG1 || s!=MUL_NREG2) {
+	write_log("Bad register in IMUL: d=%d, s=%d\n",d,s);
+	abort();
+	}
+	IMULLr(s);
+}
+LENDFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s))
+
+LOWFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s))
+{
+	if (d!=MUL_NREG1 || s!=MUL_NREG2) {
+	write_log("Bad register in MUL: d=%d, s=%d\n",d,s);
+	abort();
+	}
+	MULLr(s);
+}
+LENDFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s))
+
+LOWFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s))
+{
+	abort(); /* %^$&%^$%#^ x86! */
+}
+LENDFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s))
+
+LOWFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s))
+{
+	MOVBrr(s, d);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s))
+
+LOWFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s))
+{
+	MOVWrr(s, d);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s))
+
+LOWFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor))
+{
+	ADDR32 MOVLmr(0, baser, index, factor, d);
+}
+LENDFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor))
+
+LOWFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor))
+{
+	ADDR32 MOVWmr(0, baser, index, factor, d);
+}
+LENDFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor))
+
+LOWFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor))
+{
+	ADDR32 MOVBmr(0, baser, index, factor, d);
+}
+LENDFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor))
+
+LOWFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s))
+{
+	ADDR32 MOVLrm(s, 0, baser, index, factor);
+}
+LENDFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s))
+
+LOWFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s))
+{
+	ADDR32 MOVWrm(s, 0, baser, index, factor);
+}
+LENDFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s))
+
+LOWFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s))
+{
+	ADDR32 MOVBrm(s, 0, baser, index, factor);
+}
+LENDFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s))
+
+LOWFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s))
+{
+	ADDR32 MOVLrm(s, base, baser, index, factor);
+}
+LENDFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s))
+
+LOWFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s))
+{
+	ADDR32 MOVWrm(s, base, baser, index, factor);
+}
+LENDFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s))
+
+LOWFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s))
+{
+	ADDR32 MOVBrm(s, base, baser, index, factor);
+}
+LENDFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s))
+
+LOWFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor))
+{
+	ADDR32 MOVLmr(base, baser, index, factor, d);
+}
+LENDFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor))
+
+LOWFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor))
+{
+	ADDR32 MOVWmr(base, baser, index, factor, d);
+}
+LENDFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor))
+
+LOWFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor))
+{
+	ADDR32 MOVBmr(base, baser, index, factor, d);
+}
+LENDFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor))
+
+LOWFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor))
+{
+	ADDR32 MOVLmr(base, X86_NOREG, index, factor, d);
+}
+LENDFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor))
+
+LOWFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond))
+{
+	if (have_cmov)
+		ADDR32 CMOVLmr(cond, base, X86_NOREG, index, factor, d);
+	else { /* replacement using branch and mov */
+		int8 *target_p = (int8 *)x86_get_target() + 1;
+		JCCSii(cond^1, 0);
+		ADDR32 MOVLmr(base, X86_NOREG, index, factor, d);
+	    *target_p = (uintptr)x86_get_target() - ((uintptr)target_p + 1);
+	}
+}
+LENDFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond))
+
+LOWFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond))
+{
+	if (have_cmov)
+		CMOVLmr(cond, mem, X86_NOREG, X86_NOREG, 1, d);
+	else { /* replacement using branch and mov */
+		int8 *target_p = (int8 *)x86_get_target() + 1;
+		JCCSii(cond^1, 0);
+		MOVLmr(mem, X86_NOREG, X86_NOREG, 1, d);
+	    *target_p = (uintptr)x86_get_target() - ((uintptr)target_p + 1);
+	}
+}
+LENDFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond))
+
+LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
+{
+	ADDR32 MOVLmr(offset, s, X86_NOREG, 1, d);
+}
+LENDFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
+{
+	ADDR32 MOVWmr(offset, s, X86_NOREG, 1, d);
+}
+LENDFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
+{
+	ADDR32 MOVBmr(offset, s, X86_NOREG, 1, d);
+}
+LENDFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset))
+{
+	ADDR32 MOVLmr(offset, s, X86_NOREG, 1, d);
+}
+LENDFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset))
+{
+	ADDR32 MOVWmr(offset, s, X86_NOREG, 1, d);
+}
+LENDFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset))
+{
+	ADDR32 MOVBmr(offset, s, X86_NOREG, 1, d);
+}
+LENDFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
+{
+	ADDR32 MOVLim(i, offset, d, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
+{
+	ADDR32 MOVWim(i, offset, d, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
+{
+	ADDR32 MOVBim(i, offset, d, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
+{
+	ADDR32 MOVLrm(s, offset, d, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
+{
+	ADDR32 MOVWrm(s, offset, d, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
+{
+	ADDR32 MOVBrm(s, offset, d, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
+
+LOWFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset))
+{
+	LEALmr(offset, s, X86_NOREG, 1, d);
+}
+LENDFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
+{
+	LEALmr(offset, s, index, factor, d);
+}
+LENDFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
+
+LOWFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor))
+{
+	LEALmr(0, s, index, factor, d);
+}
+LENDFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor))
+
+LOWFUNC(NONE,NONE,4,raw_lea_l_r_scaled,(W4 d, R4 index, IMM factor))
+{
+	LEALmr(0, X86_NOREG, index, factor, d);
+}
+LENDFUNC(NONE,NONE,4,raw_lea_l_r_scaled,(W4 d, R4 index, IMM factor))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset))
+{
+	ADDR32 MOVLrm(s, offset, d, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset))
+{
+	ADDR32 MOVWrm(s, offset, d, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset))
+{
+	ADDR32 MOVBrm(s, offset, d, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset))
+
+LOWFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r))
+{
+	BSWAPLr(r);
+}
+LENDFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r))
+
+LOWFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r))
+{
+	ROLWir(8, r);
+}
+LENDFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r))
+
+LOWFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s))
+{
+	MOVLrr(s, d);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s))
+
+LOWFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s))
+{
+	MOVLrm(s, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s))
+
+LOWFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s))
+{
+	MOVWrm(s, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s))
+
+LOWFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s))
+{
+	MOVWmr(s, X86_NOREG, X86_NOREG, 1, d);
+}
+LENDFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s))
+
+LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
+{
+	MOVBrm(s, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
+
+LOWFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s))
+{
+	MOVBmr(s, X86_NOREG, X86_NOREG, 1, d);
+}
+LENDFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s))
+
+LOWFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s))
+{
+	MOVLir(s, d);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s))
+
+LOWFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
+{
+	MOVWir(s, d);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
+
+LOWFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
+{
+	MOVBir(s, d);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
+
+LOWFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s))
+{
+	ADCLim(s, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s))
+
+LOWFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s)) 
+{
+	ADDLim(s, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s)) 
+
+LOWFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s)) 
+{
+	ADDWim(s, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s)) 
+
+LOWFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s)) 
+{
+	ADDBim(s, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s)) 
+
+LOWFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i))
+{
+	TESTLir(i, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s))
+{
+	TESTLrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s))
+
+LOWFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s))
+{
+	TESTWrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s))
+
+LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
+{
+	TESTBrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
+
+LOWFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
+{
+	XORLir(i, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
+{
+	ANDLir(i, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i))
+{
+	ANDWir(i, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s))
+{
+	ANDLrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s))
+
+LOWFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s))
+{
+	ANDWrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s))
+
+LOWFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s))
+{
+	ANDBrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s))
+
+LOWFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i))
+{
+	ORLir(i, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s))
+{
+	ORLrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s))
+
+LOWFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s))
+{
+	ORWrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s))
+
+LOWFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s))
+{
+	ORBrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s))
+
+LOWFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s))
+{
+	ADCLrr(s, d);
+}
+LENDFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s))
+
+LOWFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s))
+{
+	ADCWrr(s, d);
+}
+LENDFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s))
+
+LOWFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s))
+{
+	ADCBrr(s, d);
+}
+LENDFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s))
+
+LOWFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s))
+{
+	ADDLrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s))
+
+LOWFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s))
+{
+	ADDWrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s))
+
+LOWFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s))
+{
+	ADDBrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s))
+
+LOWFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i))
+{
+	SUBLir(i, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i))
+{
+	SUBBir(i, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i))
+{
+	ADDLir(i, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i))
+{
+	ADDWir(i, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i))
+{
+	ADDBir(i, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i))
+
+LOWFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s))
+{
+	SBBLrr(s, d);
+}
+LENDFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s))
+
+LOWFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s))
+{
+	SBBWrr(s, d);
+}
+LENDFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s))
+
+LOWFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s))
+{
+	SBBBrr(s, d);
+}
+LENDFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s))
+
+LOWFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s))
+{
+	SUBLrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s))
+
+LOWFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s))
+{
+	SUBWrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s))
+
+LOWFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s))
+{
+	SUBBrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s))
+
+LOWFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s))
+{
+	CMPLrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s))
+
+LOWFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i))
+{
+	CMPLir(i, r);
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s))
+{
+	CMPWrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s))
+
+LOWFUNC(WRITE,READ,2,raw_cmp_b_mi,(MEMR d, IMM s))
+{
+	CMPBim(s, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
+
+LOWFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i))
+{
+	CMPBir(i, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s))
+{
+	CMPBrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s))
+
+LOWFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor))
+{
+	ADDR32 CMPLmr(offset, X86_NOREG, index, factor, d);
+}
+LENDFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor))
+
+LOWFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s))
+{
+	XORLrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s))
+
+LOWFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s))
+{
+	XORWrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s))
+
+LOWFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s))
+{
+	XORBrr(s, d);
+}
+LENDFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s))
+
+LOWFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s))
+{
+	SUBLim(s, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s))
+
+LOWFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
+{
+	CMPLim(s, d, X86_NOREG, X86_NOREG, 1);
+}
+LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
+
+LOWFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
+{
+	XCHGLrr(r2, r1);
+}
+LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
+
+LOWFUNC(NONE,NONE,2,raw_xchg_b_rr,(RW4 r1, RW4 r2))
+{
+	XCHGBrr(r2, r1);
+}
+LENDFUNC(NONE,NONE,2,raw_xchg_b_rr,(RW4 r1, RW4 r2))
+
+LOWFUNC(READ,WRITE,0,raw_pushfl,(void))
+{
+	PUSHF();
+}
+LENDFUNC(READ,WRITE,0,raw_pushfl,(void))
+
+LOWFUNC(WRITE,READ,0,raw_popfl,(void))
+{
+	POPF();
+}
+LENDFUNC(WRITE,READ,0,raw_popfl,(void))
+
+/* Generate floating-point instructions */
+static inline void x86_fadd_m(MEMR s)
+{
+	FADDLm(s,X86_NOREG,X86_NOREG,1);
+}
+
+#else
+
+const bool optimize_accum		= true;
+const bool optimize_imm8		= true;
+const bool optimize_shift_once	= true;
+
+/*************************************************************************
+ * Actual encoding of the instructions on the target CPU                 *
+ *************************************************************************/
+
+static __inline__ int isaccum(int r)
+{
+	return (r == EAX_INDEX);
+}
+
+static __inline__ int isbyte(uae_s32 x)
+{
+	return (x>=-128 && x<=127);
+}
+
+static __inline__ int isword(uae_s32 x)
+{
+	return (x>=-32768 && x<=32767);
+}
+
+LOWFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r))
+{
+	emit_byte(0x50+r);
+}
+LENDFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r))
+
+LOWFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
+{
+	emit_byte(0x58+r);
+}
+LENDFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
+
+LOWFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
+{
+	emit_byte(0x8f);
+	emit_byte(0x05);
+	emit_long(d);
+}
+LENDFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
+
+LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
+{
+	emit_byte(0x0f);
+	emit_byte(0xba);
+	emit_byte(0xe0+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b))
+{
+	emit_byte(0x0f);
+	emit_byte(0xa3);
+	emit_byte(0xc0+8*b+r);
+}
+LENDFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b))
+
+LOWFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i))
+{
+	emit_byte(0x0f);
+	emit_byte(0xba);
+	emit_byte(0xf8+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b))
+{
+	emit_byte(0x0f);
+	emit_byte(0xbb);
+	emit_byte(0xc0+8*b+r);
+}
+LENDFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b))
+
+
+LOWFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i))
+{
+	emit_byte(0x0f);
+	emit_byte(0xba);
+	emit_byte(0xf0+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b))
+{
+	emit_byte(0x0f);
+	emit_byte(0xb3);
+	emit_byte(0xc0+8*b+r);
+}
+LENDFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b))
+
+LOWFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i))
+{
+	emit_byte(0x0f);
+	emit_byte(0xba);
+	emit_byte(0xe8+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b))
+{
+	emit_byte(0x0f);
+	emit_byte(0xab);
+	emit_byte(0xc0+8*b+r);
+}
+LENDFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b))
+
+LOWFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i))
+{
+    emit_byte(0x66);
+    if (isbyte(i)) {
+	emit_byte(0x83);
+	emit_byte(0xe8+d);
+	emit_byte(i);
+    }
+    else {
+	if (optimize_accum && isaccum(d))
+	emit_byte(0x2d);
+	else {
+	emit_byte(0x81);
+	emit_byte(0xe8+d);
+	}
+	emit_word(i);
+    }
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i))
+
+
+LOWFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s))
+{
+    emit_byte(0x8b);
+    emit_byte(0x05+8*d);
+    emit_long(s);
+}
+LENDFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s))
+
+LOWFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s))
+{
+    emit_byte(0xc7);
+    emit_byte(0x05);
+    emit_long(d);
+    emit_long(s);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s))
+
+LOWFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s))
+{
+    emit_byte(0x66);
+    emit_byte(0xc7);
+    emit_byte(0x05);
+    emit_long(d);
+    emit_word(s);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s))
+
+LOWFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s))
+{
+    emit_byte(0xc6);
+    emit_byte(0x05);
+    emit_long(d);
+    emit_byte(s);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s))
+
+LOWFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i))
+{
+	if (optimize_shift_once && (i == 1)) {
+	emit_byte(0xd0);
+	emit_byte(0x05);
+	emit_long(d);
+	}
+	else {
+    emit_byte(0xc0);
+    emit_byte(0x05);
+    emit_long(d);
+    emit_byte(i);
+	}
+}
+LENDFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i))
+{
+	if (optimize_shift_once && (i == 1)) {
+    emit_byte(0xd0);
+    emit_byte(0xc0+r);
+	}
+	else {
+    emit_byte(0xc0);
+    emit_byte(0xc0+r);
+    emit_byte(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i))
+{
+    emit_byte(0x66);
+    emit_byte(0xc1);
+    emit_byte(0xc0+r);
+    emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i))
+{
+	if (optimize_shift_once && (i == 1)) {
+    emit_byte(0xd1);
+    emit_byte(0xc0+r);
+	}
+	else {
+    emit_byte(0xc1);
+    emit_byte(0xc0+r);
+    emit_byte(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r))
+{
+    emit_byte(0xd3);
+    emit_byte(0xc0+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r))
+{
+    emit_byte(0x66);
+    emit_byte(0xd3);
+    emit_byte(0xc0+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r))
+{
+    emit_byte(0xd2);
+    emit_byte(0xc0+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r))
+{
+    emit_byte(0xd3);
+    emit_byte(0xe0+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r))
+{
+    emit_byte(0x66);
+    emit_byte(0xd3);
+    emit_byte(0xe0+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r))
+{
+    emit_byte(0xd2);
+    emit_byte(0xe0+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i))
+{
+	if (optimize_shift_once && (i == 1)) {
+    emit_byte(0xd0);
+    emit_byte(0xc8+r);
+	}
+	else {
+    emit_byte(0xc0);
+    emit_byte(0xc8+r);
+    emit_byte(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i))
+{
+    emit_byte(0x66);
+    emit_byte(0xc1);
+    emit_byte(0xc8+r);
+    emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i))
+
+// gb-- used for making an fpcr value in compemu_fpp.cpp
+LOWFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s))
+{
+    emit_byte(0x0b);
+    emit_byte(0x05+8*d);
+    emit_long(s);
+}
+LENDFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s))
+
+LOWFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i))
+{
+	if (optimize_shift_once && (i == 1)) {
+    emit_byte(0xd1);
+    emit_byte(0xc8+r);
+	}
+	else {
+    emit_byte(0xc1);
+    emit_byte(0xc8+r);
+    emit_byte(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r))
+{
+    emit_byte(0xd3);
+    emit_byte(0xc8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r))
+{
+    emit_byte(0x66);
+    emit_byte(0xd3);
+    emit_byte(0xc8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r))
+{
+    emit_byte(0xd2);
+    emit_byte(0xc8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r))
+{
+    emit_byte(0xd3);
+    emit_byte(0xe8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r))
+{
+    emit_byte(0x66);
+    emit_byte(0xd3);
+    emit_byte(0xe8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r))
+{
+    emit_byte(0xd2);
+    emit_byte(0xe8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r))
+{
+    emit_byte(0xd3);
+    emit_byte(0xf8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r))
+{
+    emit_byte(0x66);
+    emit_byte(0xd3);
+    emit_byte(0xf8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r))
+{
+    emit_byte(0xd2);
+    emit_byte(0xf8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r))
+
+LOWFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i))
+{
+	if (optimize_shift_once && (i == 1)) {
+    emit_byte(0xd1);
+    emit_byte(0xe0+r);
+	}
+	else {
+    emit_byte(0xc1);
+    emit_byte(0xe0+r);
+    emit_byte(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i))
+{
+    emit_byte(0x66);
+    emit_byte(0xc1);
+    emit_byte(0xe0+r);
+    emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i))
+{
+	if (optimize_shift_once && (i == 1)) {
+    emit_byte(0xd0);
+    emit_byte(0xe0+r);
+	}
+	else {
+    emit_byte(0xc0);
+    emit_byte(0xe0+r);
+    emit_byte(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i))
+{
+	if (optimize_shift_once && (i == 1)) {
+    emit_byte(0xd1);
+    emit_byte(0xe8+r);
+	}
+	else {
+    emit_byte(0xc1);
+    emit_byte(0xe8+r);
+    emit_byte(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i))
+{
+    emit_byte(0x66);
+    emit_byte(0xc1);
+    emit_byte(0xe8+r);
+    emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i))
+{
+	if (optimize_shift_once && (i == 1)) {
+    emit_byte(0xd0);
+    emit_byte(0xe8+r);
+	}
+	else {
+    emit_byte(0xc0);
+    emit_byte(0xe8+r);
+    emit_byte(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i))
+{
+	if (optimize_shift_once && (i == 1)) {
+    emit_byte(0xd1);
+    emit_byte(0xf8+r);
+	}
+	else {
+    emit_byte(0xc1);
+    emit_byte(0xf8+r);
+    emit_byte(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i))
+{
+    emit_byte(0x66);
+    emit_byte(0xc1);
+    emit_byte(0xf8+r);
+    emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i))
+{
+	if (optimize_shift_once && (i == 1)) {
+    emit_byte(0xd0);
+    emit_byte(0xf8+r);
+	}
+	else {
+    emit_byte(0xc0);
+    emit_byte(0xf8+r);
+    emit_byte(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i))
+
+LOWFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah))
+{
+    emit_byte(0x9e);
+}
+LENDFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah))
+
+LOWFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax))
+{
+    emit_byte(0x0f);
+    emit_byte(0xa2);
+}
+LENDFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax))
+
+LOWFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah))
+{
+    emit_byte(0x9f);
+}
+LENDFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah))
+
+LOWFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc))
+{
+    emit_byte(0x0f);
+    emit_byte(0x90+cc);
+    emit_byte(0xc0+d);
+}
+LENDFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc))
+
+LOWFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc))
+{
+    emit_byte(0x0f);
+    emit_byte(0x90+cc);
+    emit_byte(0x05);
+    emit_long(d);
+}
+LENDFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc))
+
+LOWFUNC(READ,NONE,3,raw_cmov_b_rr,(RW1 d, R1 s, IMM cc))
+{
+	/* replacement using branch and mov */
+	int uncc=(cc^1);
+	emit_byte(0x70+uncc); 
+	emit_byte(3);  /* skip next 2 bytes if not cc=true */
+    emit_byte(0x88);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(READ,NONE,3,raw_cmov_b_rr,(RW1 d, R1 s, IMM cc))
+
+LOWFUNC(READ,NONE,3,raw_cmov_w_rr,(RW2 d, R2 s, IMM cc))
+{
+    if (have_cmov) {
+	emit_byte(0x66);
+	emit_byte(0x0f);
+	emit_byte(0x40+cc);
+	emit_byte(0xc0+8*d+s);
+    }
+    else { /* replacement using branch and mov */
+	int uncc=(cc^1);
+	emit_byte(0x70+uncc); 
+	emit_byte(3);  /* skip next 3 bytes if not cc=true */
+	emit_byte(0x66);
+	emit_byte(0x89);
+	emit_byte(0xc0+8*s+d);
+    }
+}
+LENDFUNC(READ,NONE,3,raw_cmov_w_rr,(RW2 d, R2 s, IMM cc))
+
+LOWFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc))
+{
+    if (have_cmov) {
+	emit_byte(0x0f);
+	emit_byte(0x40+cc);
+	emit_byte(0xc0+8*d+s);
+    }
+    else { /* replacement using branch and mov */
+	int uncc=(cc^1);
+	emit_byte(0x70+uncc); 
+	emit_byte(2);  /* skip next 2 bytes if not cc=true */
+	emit_byte(0x89);
+	emit_byte(0xc0+8*s+d);
+    }
+}
+LENDFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc))
+
+LOWFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s))
+{
+    emit_byte(0x0f);
+    emit_byte(0xbc);
+    emit_byte(0xc0+8*d+s);
+}
+LENDFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s))
+
+LOWFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s))
+{
+    emit_byte(0x0f);
+    emit_byte(0xbf);
+    emit_byte(0xc0+8*d+s);
+}
+LENDFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s))
+
+LOWFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s))
+{
+    emit_byte(0x0f);
+    emit_byte(0xbe);
+    emit_byte(0xc0+8*d+s);
+}
+LENDFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s))
+
+LOWFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s))
+{
+    emit_byte(0x0f);
+    emit_byte(0xb7);
+    emit_byte(0xc0+8*d+s);
+}
+LENDFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s))
+
+LOWFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s))
+{
+    emit_byte(0x0f);
+    emit_byte(0xb6);
+    emit_byte(0xc0+8*d+s);
+}
+LENDFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s))
+
+LOWFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s))
+{
+    emit_byte(0x0f);
+    emit_byte(0xaf);
+    emit_byte(0xc0+8*d+s);
+}
+LENDFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s))
+
+LOWFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s))
+{
+    if (d!=MUL_NREG1 || s!=MUL_NREG2)
+	abort();
+    emit_byte(0xf7);
+    emit_byte(0xea);
+}
+LENDFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s))
+
+LOWFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s))
+{
+    if (d!=MUL_NREG1 || s!=MUL_NREG2) {
+	printf("Bad register in MUL: d=%d, s=%d\n",d,s);
+	abort();
+    }
+    emit_byte(0xf7);
+    emit_byte(0xe2);
+}
+LENDFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s))
+
+LOWFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s))
+{
+    abort(); /* %^$&%^$%#^ x86! */
+    emit_byte(0x0f);
+    emit_byte(0xaf);
+    emit_byte(0xc0+8*d+s);
+}
+LENDFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s))
+
+LOWFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s))
+{
+    emit_byte(0x88);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s))
+
+LOWFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s))
+{
+    emit_byte(0x66);
+    emit_byte(0x89);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s))
+
+LOWFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor))
+{
+    int isebp=(baser==5)?0x40:0;
+    int fi;
+    
+    switch(factor) {
+     case 1: fi=0; break;
+     case 2: fi=1; break;
+     case 4: fi=2; break;
+     case 8: fi=3; break;
+     default: abort();
+    }
+
+
+    emit_byte(0x8b);
+    emit_byte(0x04+8*d+isebp);
+    emit_byte(baser+8*index+0x40*fi);
+    if (isebp)
+	emit_byte(0x00);
+}
+LENDFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor))
+
+LOWFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor))
+{
+    int fi;
+    int isebp;
+    
+    switch(factor) {
+     case 1: fi=0; break;
+     case 2: fi=1; break;
+     case 4: fi=2; break;
+     case 8: fi=3; break;
+     default: abort();
+    }
+    isebp=(baser==5)?0x40:0;
+    
+    emit_byte(0x66);
+    emit_byte(0x8b);
+    emit_byte(0x04+8*d+isebp);
+    emit_byte(baser+8*index+0x40*fi);
+    if (isebp)
+	emit_byte(0x00);
+}
+LENDFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor))
+
+LOWFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor))
+{
+   int fi;
+  int isebp;
+
+  switch(factor) {
+  case 1: fi=0; break;
+  case 2: fi=1; break;
+  case 4: fi=2; break;
+  case 8: fi=3; break;
+  default: abort();
+  }
+  isebp=(baser==5)?0x40:0;
+
+   emit_byte(0x8a);
+    emit_byte(0x04+8*d+isebp);
+    emit_byte(baser+8*index+0x40*fi);
+    if (isebp)
+	emit_byte(0x00);
+}
+LENDFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor))
+
+LOWFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s))
+{
+  int fi;
+  int isebp;
+
+  switch(factor) {
+  case 1: fi=0; break;
+  case 2: fi=1; break;
+  case 4: fi=2; break;
+  case 8: fi=3; break;
+  default: abort();
+  }
+
+  
+  isebp=(baser==5)?0x40:0;
+
+    emit_byte(0x89);
+    emit_byte(0x04+8*s+isebp);
+    emit_byte(baser+8*index+0x40*fi);
+    if (isebp)
+	emit_byte(0x00);
+}
+LENDFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s))
+
+LOWFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s))
+{
+  int fi;
+  int isebp;
+
+  switch(factor) {
+  case 1: fi=0; break;
+  case 2: fi=1; break;
+  case 4: fi=2; break;
+  case 8: fi=3; break;
+  default: abort();
+  }
+  isebp=(baser==5)?0x40:0;
+
+    emit_byte(0x66);
+    emit_byte(0x89);
+    emit_byte(0x04+8*s+isebp);
+    emit_byte(baser+8*index+0x40*fi);
+    if (isebp)
+	emit_byte(0x00);
+}
+LENDFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s))
+
+LOWFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s))
+{
+  int fi;
+  int isebp;
+
+  switch(factor) {
+  case 1: fi=0; break;
+  case 2: fi=1; break;
+  case 4: fi=2; break;
+  case 8: fi=3; break;
+  default: abort();
+  }
+  isebp=(baser==5)?0x40:0;
+
+    emit_byte(0x88);
+    emit_byte(0x04+8*s+isebp);
+    emit_byte(baser+8*index+0x40*fi);
+    if (isebp)
+	emit_byte(0x00);
+}
+LENDFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s))
+
+LOWFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s))
+{
+  int fi;
+
+  switch(factor) {
+  case 1: fi=0; break;
+  case 2: fi=1; break;
+  case 4: fi=2; break;
+  case 8: fi=3; break;
+  default: abort();
+  }
+
+    emit_byte(0x89);
+    emit_byte(0x84+8*s);
+    emit_byte(baser+8*index+0x40*fi);
+    emit_long(base);
+}
+LENDFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s))
+
+LOWFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s))
+{
+  int fi;
+
+  switch(factor) {
+  case 1: fi=0; break;
+  case 2: fi=1; break;
+  case 4: fi=2; break;
+  case 8: fi=3; break;
+  default: abort();
+  }
+
+    emit_byte(0x66);
+    emit_byte(0x89);
+    emit_byte(0x84+8*s);
+    emit_byte(baser+8*index+0x40*fi);
+    emit_long(base);
+}
+LENDFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s))
+
+LOWFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s))
+{
+  int fi;
+
+  switch(factor) {
+  case 1: fi=0; break;
+  case 2: fi=1; break;
+  case 4: fi=2; break;
+  case 8: fi=3; break;
+  default: abort();
+  }
+
+    emit_byte(0x88);
+    emit_byte(0x84+8*s);
+    emit_byte(baser+8*index+0x40*fi);
+    emit_long(base);
+}
+LENDFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s))
+
+LOWFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor))
+{
+  int fi;
+
+  switch(factor) {
+  case 1: fi=0; break;
+  case 2: fi=1; break;
+  case 4: fi=2; break;
+  case 8: fi=3; break;
+  default: abort();
+  }
+
+    emit_byte(0x8b);
+    emit_byte(0x84+8*d);
+    emit_byte(baser+8*index+0x40*fi);
+    emit_long(base);
+}
+LENDFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor))
+
+LOWFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor))
+{
+  int fi;
+
+  switch(factor) {
+  case 1: fi=0; break;
+  case 2: fi=1; break;
+  case 4: fi=2; break;
+  case 8: fi=3; break;
+  default: abort();
+  }
+
+    emit_byte(0x66);
+    emit_byte(0x8b);
+    emit_byte(0x84+8*d);
+    emit_byte(baser+8*index+0x40*fi);
+    emit_long(base);
+}
+LENDFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor))
+
+LOWFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor))
+{
+  int fi;
+
+  switch(factor) {
+  case 1: fi=0; break;
+  case 2: fi=1; break;
+  case 4: fi=2; break;
+  case 8: fi=3; break;
+  default: abort();
+  }
+
+    emit_byte(0x8a);
+    emit_byte(0x84+8*d);
+    emit_byte(baser+8*index+0x40*fi);
+    emit_long(base);
+}
+LENDFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor))
+
+LOWFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor))
+{
+  int fi;
+  switch(factor) {
+  case 1: fi=0; break;
+  case 2: fi=1; break;
+  case 4: fi=2; break;
+  case 8: fi=3; break;
+  default: 
+    fprintf(stderr,"Bad factor %d in mov_l_rm_indexed!\n",factor);
+    abort();
+  }
+    emit_byte(0x8b);
+    emit_byte(0x04+8*d);
+    emit_byte(0x05+8*index+64*fi);
+    emit_long(base);
+}
+LENDFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor))
+
+LOWFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond))
+{
+    int fi;
+    switch(factor) {
+     case 1: fi=0; break;
+     case 2: fi=1; break;
+     case 4: fi=2; break;
+     case 8: fi=3; break;
+     default: 
+	fprintf(stderr,"Bad factor %d in mov_l_rm_indexed!\n",factor);
+	abort();
+    }
+    if (have_cmov) {
+	emit_byte(0x0f);
+	emit_byte(0x40+cond);
+	emit_byte(0x04+8*d);
+	emit_byte(0x05+8*index+64*fi);
+	emit_long(base);
+    }
+    else { /* replacement using branch and mov */
+	int uncc=(cond^1);
+	emit_byte(0x70+uncc); 
+	emit_byte(7);  /* skip next 7 bytes if not cc=true */
+	emit_byte(0x8b);
+	emit_byte(0x04+8*d);
+	emit_byte(0x05+8*index+64*fi);
+	emit_long(base);
+    }
+}
+LENDFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond))
+
+LOWFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond))
+{
+    if (have_cmov) {
+	emit_byte(0x0f);
+	emit_byte(0x40+cond);
+	emit_byte(0x05+8*d);
+	emit_long(mem);
+    }
+    else { /* replacement using branch and mov */
+	int uncc=(cond^1);
+	emit_byte(0x70+uncc); 
+	emit_byte(6);  /* skip next 6 bytes if not cc=true */
+	emit_byte(0x8b);
+	emit_byte(0x05+8*d);
+	emit_long(mem);
+    }
+}
+LENDFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond))
+
+LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
+{
+	Dif(!isbyte(offset)) abort();
+    emit_byte(0x8b);
+    emit_byte(0x40+8*d+s);
+    emit_byte(offset);
+}
+LENDFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
+{
+	Dif(!isbyte(offset)) abort();
+    emit_byte(0x66);
+    emit_byte(0x8b);
+    emit_byte(0x40+8*d+s);
+    emit_byte(offset);
+}
+LENDFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
+{
+	Dif(!isbyte(offset)) abort();
+    emit_byte(0x8a);
+    emit_byte(0x40+8*d+s);
+    emit_byte(offset);
+}
+LENDFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset))
+{
+    emit_byte(0x8b);
+    emit_byte(0x80+8*d+s);
+    emit_long(offset);
+}
+LENDFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset))
+{
+    emit_byte(0x66);
+    emit_byte(0x8b);
+    emit_byte(0x80+8*d+s);
+    emit_long(offset);
+}
+LENDFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset))
+{
+    emit_byte(0x8a);
+    emit_byte(0x80+8*d+s);
+    emit_long(offset);
+}
+LENDFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
+{
+	Dif(!isbyte(offset)) abort();
+    emit_byte(0xc7);
+    emit_byte(0x40+d);
+    emit_byte(offset);
+    emit_long(i);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
+{
+	Dif(!isbyte(offset)) abort();
+    emit_byte(0x66);
+    emit_byte(0xc7);
+    emit_byte(0x40+d);
+    emit_byte(offset);
+    emit_word(i);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
+{
+	Dif(!isbyte(offset)) abort();
+    emit_byte(0xc6);
+    emit_byte(0x40+d);
+    emit_byte(offset);
+    emit_byte(i);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
+{
+	Dif(!isbyte(offset)) abort();
+    emit_byte(0x89);
+    emit_byte(0x40+8*s+d);
+    emit_byte(offset);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
+{
+	Dif(!isbyte(offset)) abort();
+    emit_byte(0x66);
+    emit_byte(0x89);
+    emit_byte(0x40+8*s+d);
+    emit_byte(offset);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
+{
+	Dif(!isbyte(offset)) abort();
+    emit_byte(0x88);
+    emit_byte(0x40+8*s+d);
+    emit_byte(offset);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
+
+LOWFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset))
+{
+	if (optimize_imm8 && isbyte(offset)) {
+    emit_byte(0x8d);
+	emit_byte(0x40+8*d+s);
+	emit_byte(offset);
+	}
+	else {
+    emit_byte(0x8d);
+	emit_byte(0x80+8*d+s);
+	emit_long(offset);
+	}
+}
+LENDFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
+{
+  int fi;
+  
+  switch(factor) {
+  case 1: fi=0; break;
+  case 2: fi=1; break;
+  case 4: fi=2; break;
+  case 8: fi=3; break;
+  default: abort();
+  }
+
+	if (optimize_imm8 && isbyte(offset)) {
+    emit_byte(0x8d);
+	emit_byte(0x44+8*d);
+	emit_byte(0x40*fi+8*index+s);
+	emit_byte(offset);
+	}
+	else {
+    emit_byte(0x8d);
+	emit_byte(0x84+8*d);
+	emit_byte(0x40*fi+8*index+s);
+	emit_long(offset);
+	}
+}
+LENDFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
+
+LOWFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor))
+{
+  int isebp=(s==5)?0x40:0;
+  int fi;
+  
+  switch(factor) {
+  case 1: fi=0; break;
+  case 2: fi=1; break;
+  case 4: fi=2; break;
+  case 8: fi=3; break;
+  default: abort();
+  }
+
+    emit_byte(0x8d);
+    emit_byte(0x04+8*d+isebp);
+    emit_byte(0x40*fi+8*index+s);
+    if (isebp)
+      emit_byte(0);
+}
+LENDFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset))
+{
+	if (optimize_imm8 && isbyte(offset)) {
+    emit_byte(0x89);
+    emit_byte(0x40+8*s+d);
+    emit_byte(offset);
+	}
+	else {
+    emit_byte(0x89);
+    emit_byte(0x80+8*s+d);
+    emit_long(offset);
+	}
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset))
+{
+    emit_byte(0x66);
+    emit_byte(0x89);
+    emit_byte(0x80+8*s+d);
+    emit_long(offset);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset))
+
+LOWFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset))
+{
+	if (optimize_imm8 && isbyte(offset)) {
+    emit_byte(0x88);
+    emit_byte(0x40+8*s+d);
+    emit_byte(offset);
+	}
+	else {
+    emit_byte(0x88);
+    emit_byte(0x80+8*s+d);
+    emit_long(offset);
+	}
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset))
+
+LOWFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r))
+{
+    emit_byte(0x0f);
+    emit_byte(0xc8+r);
+}
+LENDFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r))
+
+LOWFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r))
+{
+    emit_byte(0x66);
+    emit_byte(0xc1);
+    emit_byte(0xc0+r);
+    emit_byte(0x08);
+}
+LENDFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r))
+
+LOWFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s))
+{
+    emit_byte(0x89);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s))
+
+LOWFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s))
+{
+    emit_byte(0x89);
+    emit_byte(0x05+8*s);
+    emit_long(d);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s))
+
+LOWFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s))
+{
+    emit_byte(0x66);
+    emit_byte(0x89);
+    emit_byte(0x05+8*s);
+    emit_long(d);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s))
+
+LOWFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s))
+{
+    emit_byte(0x66);
+    emit_byte(0x8b);
+    emit_byte(0x05+8*d);
+    emit_long(s);
+}
+LENDFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s))
+
+LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
+{
+    emit_byte(0x88);
+    emit_byte(0x05+8*(s&0xf)); /* XXX this handles %ah case (defined as 0x10+4) and others */
+    emit_long(d);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
+
+LOWFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s))
+{
+    emit_byte(0x8a);
+    emit_byte(0x05+8*d);
+    emit_long(s);
+}
+LENDFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s))
+
+LOWFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s))
+{
+    emit_byte(0xb8+d);
+    emit_long(s);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s))
+
+LOWFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
+{
+    emit_byte(0x66);
+    emit_byte(0xb8+d);
+    emit_word(s);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
+
+LOWFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
+{
+    emit_byte(0xb0+d);
+    emit_byte(s);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
+
+LOWFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s))
+{
+    emit_byte(0x81);
+    emit_byte(0x15);
+    emit_long(d);
+    emit_long(s);
+}
+LENDFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s))
+
+LOWFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s)) 
+{
+	if (optimize_imm8 && isbyte(s)) {
+    emit_byte(0x83);
+    emit_byte(0x05);
+    emit_long(d);
+    emit_byte(s);
+	}
+	else {
+    emit_byte(0x81);
+    emit_byte(0x05);
+    emit_long(d);
+    emit_long(s);
+	}
+}
+LENDFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s)) 
+
+LOWFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s)) 
+{
+    emit_byte(0x66);
+    emit_byte(0x81);
+    emit_byte(0x05);
+    emit_long(d);
+    emit_word(s);
+}
+LENDFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s)) 
+
+LOWFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s)) 
+{
+    emit_byte(0x80);
+    emit_byte(0x05);
+    emit_long(d);
+    emit_byte(s);
+}
+LENDFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s)) 
+
+LOWFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i))
+{
+	if (optimize_accum && isaccum(d))
+	emit_byte(0xa9);
+	else {
+    emit_byte(0xf7);
+    emit_byte(0xc0+d);
+	}
+    emit_long(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s))
+{
+    emit_byte(0x85);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s))
+
+LOWFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s))
+{
+    emit_byte(0x66);
+    emit_byte(0x85);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s))
+
+LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
+{
+    emit_byte(0x84);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
+
+LOWFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
+{
+    emit_byte(0x81);
+    emit_byte(0xf0+d);
+    emit_long(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
+{
+	if (optimize_imm8 && isbyte(i)) {
+	emit_byte(0x83);
+	emit_byte(0xe0+d);
+	emit_byte(i);
+	}
+	else {
+	if (optimize_accum && isaccum(d))
+	emit_byte(0x25);
+	else {
+	emit_byte(0x81);
+	emit_byte(0xe0+d);
+	}
+	emit_long(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i))
+{
+	emit_byte(0x66);
+	if (optimize_imm8 && isbyte(i)) {
+	emit_byte(0x83);
+	emit_byte(0xe0+d);
+	emit_byte(i);
+	}
+	else {
+	if (optimize_accum && isaccum(d))
+	emit_byte(0x25);
+	else {
+	emit_byte(0x81);
+	emit_byte(0xe0+d);
+	}
+	emit_word(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s))
+{
+    emit_byte(0x21);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s))
+
+LOWFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s))
+{
+    emit_byte(0x66);
+    emit_byte(0x21);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s))
+
+LOWFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s))
+{
+    emit_byte(0x20);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s))
+
+LOWFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i))
+{
+	if (optimize_imm8 && isbyte(i)) {
+    emit_byte(0x83);
+    emit_byte(0xc8+d);
+    emit_byte(i);
+	}
+	else {
+	if (optimize_accum && isaccum(d))
+	emit_byte(0x0d);
+	else {
+    emit_byte(0x81);
+    emit_byte(0xc8+d);
+	}
+    emit_long(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s))
+{
+    emit_byte(0x09);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s))
+
+LOWFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s))
+{
+    emit_byte(0x66);
+    emit_byte(0x09);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s))
+
+LOWFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s))
+{
+    emit_byte(0x08);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s))
+
+LOWFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s))
+{
+    emit_byte(0x11);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s))
+
+LOWFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s))
+{
+    emit_byte(0x66);
+    emit_byte(0x11);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s))
+
+LOWFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s))
+{
+    emit_byte(0x10);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s))
+
+LOWFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s))
+{
+    emit_byte(0x01);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s))
+
+LOWFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s))
+{
+    emit_byte(0x66);
+    emit_byte(0x01);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s))
+
+LOWFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s))
+{
+    emit_byte(0x00);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s))
+
+LOWFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i))
+{
+  if (isbyte(i)) {
+    emit_byte(0x83);
+    emit_byte(0xe8+d);
+    emit_byte(i);
+  }
+  else {
+    if (optimize_accum && isaccum(d))
+    emit_byte(0x2d);
+    else {
+    emit_byte(0x81);
+    emit_byte(0xe8+d);
+    }
+    emit_long(i);
+  }
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i))
+{
+	if (optimize_accum && isaccum(d))
+	emit_byte(0x2c);
+	else {
+    emit_byte(0x80);
+    emit_byte(0xe8+d);
+	}
+    emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i))
+{
+    if (isbyte(i)) {
+	emit_byte(0x83);
+	emit_byte(0xc0+d);
+	emit_byte(i);
+    }
+    else {
+	if (optimize_accum && isaccum(d))
+	emit_byte(0x05);
+	else {
+	emit_byte(0x81);
+	emit_byte(0xc0+d);
+	}
+	emit_long(i);
+    }
+}
+LENDFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i))
+{
+	emit_byte(0x66);
+    if (isbyte(i)) {
+	emit_byte(0x83);
+	emit_byte(0xc0+d);
+	emit_byte(i);
+    }
+    else {
+	if (optimize_accum && isaccum(d))
+	emit_byte(0x05);
+	else {
+	emit_byte(0x81);
+	emit_byte(0xc0+d);
+	}
+	emit_word(i);
+    }
+}
+LENDFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i))
+{
+	if (optimize_accum && isaccum(d))
+	emit_byte(0x04);
+	else {
+	emit_byte(0x80);
+	emit_byte(0xc0+d);
+	}
+    emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i))
+
+LOWFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s))
+{
+    emit_byte(0x19);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s))
+
+LOWFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s))
+{
+    emit_byte(0x66);
+    emit_byte(0x19);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s))
+
+LOWFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s))
+{
+    emit_byte(0x18);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s))
+
+LOWFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s))
+{
+    emit_byte(0x29);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s))
+
+LOWFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s))
+{
+    emit_byte(0x66);
+    emit_byte(0x29);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s))
+
+LOWFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s))
+{
+    emit_byte(0x28);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s))
+
+LOWFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s))
+{
+    emit_byte(0x39);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s))
+
+LOWFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i))
+{
+	if (optimize_imm8 && isbyte(i)) {
+    emit_byte(0x83);
+    emit_byte(0xf8+r);
+    emit_byte(i);
+	}
+	else {
+	if (optimize_accum && isaccum(r))
+	emit_byte(0x3d);
+	else {
+    emit_byte(0x81);
+    emit_byte(0xf8+r);
+	}
+    emit_long(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s))
+{
+    emit_byte(0x66);
+    emit_byte(0x39);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s))
+
+LOWFUNC(WRITE,READ,2,raw_cmp_b_mi,(MEMR d, IMM s))
+{
+    emit_byte(0x80);
+    emit_byte(0x3d);
+    emit_long(d);
+    emit_byte(s);
+}
+LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
+
+LOWFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i))
+{
+  if (optimize_accum && isaccum(d))
+  emit_byte(0x3c);
+  else {
+  emit_byte(0x80);
+  emit_byte(0xf8+d);
+  }
+  emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i))
+
+LOWFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s))
+{
+    emit_byte(0x38);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s))
+
+LOWFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor))
+{
+    int fi;
+    
+    switch(factor) {
+     case 1: fi=0; break;
+     case 2: fi=1; break;
+     case 4: fi=2; break;
+     case 8: fi=3; break;
+     default: abort();
+    }
+    emit_byte(0x39);
+    emit_byte(0x04+8*d);
+    emit_byte(5+8*index+0x40*fi);
+    emit_long(offset);
+}
+LENDFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor))
+
+LOWFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s))
+{
+    emit_byte(0x31);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s))
+
+LOWFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s))
+{
+    emit_byte(0x66);
+    emit_byte(0x31);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s))
+
+LOWFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s))
+{
+    emit_byte(0x30);
+    emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s))
+
+LOWFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s))
+{
+	if (optimize_imm8 && isbyte(s)) {
+    emit_byte(0x83);
+    emit_byte(0x2d);
+    emit_long(d);
+    emit_byte(s);
+	}
+	else {
+    emit_byte(0x81);
+    emit_byte(0x2d);
+    emit_long(d);
+    emit_long(s);
+	}
+}
+LENDFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s))
+
+LOWFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
+{
+	if (optimize_imm8 && isbyte(s)) {
+    emit_byte(0x83);
+    emit_byte(0x3d);
+    emit_long(d);
+    emit_byte(s);
+	}
+	else {
+    emit_byte(0x81);
+    emit_byte(0x3d);
+    emit_long(d);
+    emit_long(s);
+	}
+}
+LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
+
+LOWFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
+{
+  emit_byte(0x87);
+  emit_byte(0xc0+8*r1+r2);
+}
+LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
+
+LOWFUNC(NONE,NONE,2,raw_xchg_b_rr,(RW4 r1, RW4 r2))
+{
+  emit_byte(0x86);
+  emit_byte(0xc0+8*(r1&0xf)+(r2&0xf)); /* XXX this handles upper-halves registers (e.g. %ah defined as 0x10+4) */
+}
+LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
+
+/*************************************************************************
+ * FIXME: mem access modes probably wrong                                *
+ *************************************************************************/
+
+LOWFUNC(READ,WRITE,0,raw_pushfl,(void))
+{
+	emit_byte(0x9c);
+}
+LENDFUNC(READ,WRITE,0,raw_pushfl,(void))
+
+LOWFUNC(WRITE,READ,0,raw_popfl,(void))
+{
+	emit_byte(0x9d);
+}
+LENDFUNC(WRITE,READ,0,raw_popfl,(void))
+
+/* Generate floating-point instructions */
+static inline void x86_fadd_m(MEMR s)
+{
+	emit_byte(0xdc);
+	emit_byte(0x05);
+	emit_long(s);
+}
+
+#endif
+
+/*************************************************************************
+ * Unoptimizable stuff --- jump                                          *
+ *************************************************************************/
+
+static __inline__ void raw_call_r(R4 r)
+{
+#if USE_NEW_RTASM
+    CALLsr(r);
+#else
+    emit_byte(0xff);
+    emit_byte(0xd0+r);
+#endif
+}
+
+static __inline__ void raw_call_m_indexed(uae_u32 base, uae_u32 r, uae_u32 m)
+{
+#if USE_NEW_RTASM
+    CALLsm(base, X86_NOREG, r, m);
+#else
+    int mu;
+    switch(m) {
+     case 1: mu=0; break;
+     case 2: mu=1; break;
+     case 4: mu=2; break;
+     case 8: mu=3; break;
+     default: abort();
+    }
+    emit_byte(0xff);
+    emit_byte(0x14);
+    emit_byte(0x05+8*r+0x40*mu);
+    emit_long(base);
+#endif
+}
+
+static __inline__ void raw_jmp_r(R4 r)
+{
+#if USE_NEW_RTASM
+    JMPsr(r);
+#else
+    emit_byte(0xff);
+    emit_byte(0xe0+r);
+#endif
+}
+
+static __inline__ void raw_jmp_m_indexed(uae_u32 base, uae_u32 r, uae_u32 m)
+{
+#if USE_NEW_RTASM
+    JMPsm(base, X86_NOREG, r, m);
+#else
+    int mu;
+    switch(m) {
+     case 1: mu=0; break;
+     case 2: mu=1; break;
+     case 4: mu=2; break;
+     case 8: mu=3; break;
+     default: abort();
+    }
+    emit_byte(0xff);
+    emit_byte(0x24);
+    emit_byte(0x05+8*r+0x40*mu);
+    emit_long(base);
+#endif
+}
+
+static __inline__ void raw_jmp_m(uae_u32 base)
+{
+    emit_byte(0xff);
+    emit_byte(0x25);
+    emit_long(base);
+}
+
+
+static __inline__ void raw_call(uae_u32 t)
+{
+#if USE_NEW_RTASM
+    CALLm(t);
+#else
+    emit_byte(0xe8);
+    emit_long(t-(uae_u32)target-4);
+#endif
+}
+
+static __inline__ void raw_jmp(uae_u32 t)
+{
+#if USE_NEW_RTASM
+    JMPm(t);
+#else
+    emit_byte(0xe9);
+    emit_long(t-(uae_u32)target-4);
+#endif
+}
+
+static __inline__ void raw_jl(uae_u32 t)
+{
+    emit_byte(0x0f);
+    emit_byte(0x8c);
+    emit_long(t-(uintptr)target-4);
+}
+
+static __inline__ void raw_jz(uae_u32 t)
+{
+    emit_byte(0x0f);
+    emit_byte(0x84);
+    emit_long(t-(uintptr)target-4);
+}
+
+static __inline__ void raw_jnz(uae_u32 t)
+{
+    emit_byte(0x0f);
+    emit_byte(0x85);
+    emit_long(t-(uintptr)target-4);
+}
+
+static __inline__ void raw_jnz_l_oponly(void)
+{
+    emit_byte(0x0f); 
+    emit_byte(0x85); 
+}
+
+static __inline__ void raw_jcc_l_oponly(int cc)
+{
+    emit_byte(0x0f); 
+    emit_byte(0x80+cc); 
+}
+
+static __inline__ void raw_jnz_b_oponly(void)
+{
+    emit_byte(0x75); 
+}
+
+static __inline__ void raw_jz_b_oponly(void)
+{
+    emit_byte(0x74); 
+}
+
+static __inline__ void raw_jcc_b_oponly(int cc)
+{
+	emit_byte(0x70+cc);
+}
+
+static __inline__ void raw_jmp_l_oponly(void)
+{
+    emit_byte(0xe9); 
+}
+
+static __inline__ void raw_jmp_b_oponly(void)
+{
+    emit_byte(0xeb); 
+}
+
+static __inline__ void raw_ret(void)
+{
+    emit_byte(0xc3);  
+}
+
+static __inline__ void raw_nop(void)
+{
+    emit_byte(0x90);
+}
+
+static __inline__ void raw_emit_nop_filler(int nbytes)
+{
+  /* Source: GNU Binutils 2.12.90.0.15 */
+  /* Various efficient no-op patterns for aligning code labels.
+     Note: Don't try to assemble the instructions in the comments.
+     0L and 0w are not legal.  */
+  static const uae_u8 f32_1[] =
+    {0x90};									/* nop					*/
+  static const uae_u8 f32_2[] =
+    {0x89,0xf6};							/* movl %esi,%esi		*/
+  static const uae_u8 f32_3[] =
+    {0x8d,0x76,0x00};						/* leal 0(%esi),%esi	*/
+  static const uae_u8 f32_4[] =
+    {0x8d,0x74,0x26,0x00};					/* leal 0(%esi,1),%esi	*/
+  static const uae_u8 f32_5[] =
+    {0x90,									/* nop					*/
+     0x8d,0x74,0x26,0x00};					/* leal 0(%esi,1),%esi	*/
+  static const uae_u8 f32_6[] =
+    {0x8d,0xb6,0x00,0x00,0x00,0x00};		/* leal 0L(%esi),%esi	*/
+  static const uae_u8 f32_7[] =
+    {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00};	/* leal 0L(%esi,1),%esi */
+  static const uae_u8 f32_8[] =
+    {0x90,									/* nop					*/
+     0x8d,0xb4,0x26,0x00,0x00,0x00,0x00};	/* leal 0L(%esi,1),%esi */
+  static const uae_u8 f32_9[] =
+    {0x89,0xf6,								/* movl %esi,%esi		*/
+     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};	/* leal 0L(%edi,1),%edi */
+  static const uae_u8 f32_10[] =
+    {0x8d,0x76,0x00,						/* leal 0(%esi),%esi	*/
+     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};	/* leal 0L(%edi,1),%edi */
+  static const uae_u8 f32_11[] =
+    {0x8d,0x74,0x26,0x00,					/* leal 0(%esi,1),%esi	*/
+     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};	/* leal 0L(%edi,1),%edi */
+  static const uae_u8 f32_12[] =
+    {0x8d,0xb6,0x00,0x00,0x00,0x00,			/* leal 0L(%esi),%esi	*/
+     0x8d,0xbf,0x00,0x00,0x00,0x00};		/* leal 0L(%edi),%edi	*/
+  static const uae_u8 f32_13[] =
+    {0x8d,0xb6,0x00,0x00,0x00,0x00,			/* leal 0L(%esi),%esi	*/
+     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};	/* leal 0L(%edi,1),%edi */
+  static const uae_u8 f32_14[] =
+    {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00,	/* leal 0L(%esi,1),%esi */
+     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};	/* leal 0L(%edi,1),%edi */
+  static const uae_u8 f32_15[] =
+    {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90,	/* jmp .+15; lotsa nops	*/
+     0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
+  static const uae_u8 f32_16[] =
+    {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90,	/* jmp .+15; lotsa nops	*/
+     0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
+  static const uae_u8 *const f32_patt[] = {
+    f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
+    f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
+  };
+  static const uae_u8 prefixes[4] = { 0x66, 0x66, 0x66, 0x66 };
+
+#if defined(__x86_64__)
+  /* The recommended way to pad 64bit code is to use NOPs preceded by
+     maximally four 0x66 prefixes.  Balance the size of nops.  */
+  if (nbytes == 0)
+	  return;
+
+  int i;
+  int nnops = (nbytes + 3) / 4;
+  int len = nbytes / nnops;
+  int remains = nbytes - nnops * len;
+
+  for (i = 0; i < remains; i++) {
+	  emit_block(prefixes, len);
+	  raw_nop();
+  }
+  for (; i < nnops; i++) {
+	  emit_block(prefixes, len - 1);
+	  raw_nop();
+  }
+#else
+  int nloops = nbytes / 16;
+  while (nloops-- > 0)
+	emit_block(f32_16, sizeof(f32_16));
+
+  nbytes %= 16;
+  if (nbytes)
+	emit_block(f32_patt[nbytes - 1], nbytes);
+#endif
+}
+
+
+/*************************************************************************
+ * Flag handling, to and fro UAE flag register                           *
+ *************************************************************************/
+
+static __inline__ void raw_flags_evicted(int r)
+{
+  //live.state[FLAGTMP].status=CLEAN;
+  live.state[FLAGTMP].status=INMEM;
+  live.state[FLAGTMP].realreg=-1;
+  /* We just "evicted" FLAGTMP. */
+  if (live.nat[r].nholds!=1) {
+      /* Huh? */
+      abort();
+  }
+  live.nat[r].nholds=0;
+}
+
+#define FLAG_NREG1_FLAGREG 0  /* Set to -1 if any register will do */
+static __inline__ void raw_flags_to_reg_FLAGREG(int r)
+{
+  raw_lahf(0);  /* Most flags in AH */
+  //raw_setcc(r,0); /* V flag in AL */
+  raw_setcc_m((uintptr)live.state[FLAGTMP].mem,0); 
+  
+#if 1   /* Let's avoid those nasty partial register stalls */
+  //raw_mov_b_mr((uintptr)live.state[FLAGTMP].mem,r);
+  raw_mov_b_mr(((uintptr)live.state[FLAGTMP].mem)+1,AH_INDEX);
+  raw_flags_evicted(r);
+#endif
+}
+
+#define FLAG_NREG2_FLAGREG 0  /* Set to -1 if any register will do */
+static __inline__ void raw_reg_to_flags_FLAGREG(int r)
+{
+  raw_cmp_b_ri(r,-127); /* set V */
+  raw_sahf(0);
+}
+
+#define FLAG_NREG3_FLAGREG 0  /* Set to -1 if any register will do */
+static __inline__ void raw_flags_set_zero_FLAGREG(int s, int tmp)
+{
+    raw_mov_l_rr(tmp,s);
+    raw_lahf(s); /* flags into ah */
+    raw_and_l_ri(s,0xffffbfff);
+    raw_and_l_ri(tmp,0x00004000);
+    raw_xor_l_ri(tmp,0x00004000);
+    raw_or_l(s,tmp);
+    raw_sahf(s);
+}
+
+static __inline__ void raw_flags_init_FLAGREG(void) { }
+
+#define FLAG_NREG1_FLAGSTK -1  /* Set to -1 if any register will do */
+static __inline__ void raw_flags_to_reg_FLAGSTK(int r)
+{
+	raw_pushfl();
+	raw_pop_l_r(r);
+	raw_mov_l_mr((uintptr)live.state[FLAGTMP].mem,r);
+	raw_flags_evicted(r);
+}
+
+#define FLAG_NREG2_FLAGSTK -1  /* Set to -1 if any register will do */
+static __inline__ void raw_reg_to_flags_FLAGSTK(int r)
+{
+	raw_push_l_r(r);
+	raw_popfl();
+}
+
+#define FLAG_NREG3_FLAGSTK -1  /* Set to -1 if any register will do */
+static __inline__ void raw_flags_set_zero_FLAGSTK(int s, int tmp)
+{
+    raw_mov_l_rr(tmp,s);
+    raw_pushfl();
+    raw_pop_l_r(s);
+    raw_and_l_ri(s,0xffffffbf);
+    raw_and_l_ri(tmp,0x00000040);
+    raw_xor_l_ri(tmp,0x00000040);
+    raw_or_l(s,tmp);
+    raw_push_l_r(s);
+    raw_popfl();
+}
+
+static __inline__ void raw_flags_init_FLAGSTK(void) { }
+
+#if defined(__x86_64__)
+/* Try to use the LAHF/SETO method on x86_64 since it is faster.
+   This can't be the default because some older CPUs don't support
+   LAHF/SAHF in long mode.  */
+static int FLAG_NREG1_FLAGGEN = 0;
+static __inline__ void raw_flags_to_reg_FLAGGEN(int r)
+{
+	if (have_lahf_lm) {
+		// NOTE: the interpreter uses the normal EFLAGS layout
+		//   pushf/popf CF(0) ZF( 6) SF( 7) OF(11)
+		//   sahf/lahf  CF(8) ZF(14) SF(15) OF( 0)
+		assert(r == 0);
+		raw_setcc(r,0);					/* V flag in AL */
+		raw_lea_l_r_scaled(0,0,8);		/* move it to its EFLAGS location */
+		raw_mov_b_mr(((uintptr)live.state[FLAGTMP].mem)+1,0);
+		raw_lahf(0);					/* most flags in AH */
+		raw_mov_b_mr((uintptr)live.state[FLAGTMP].mem,AH_INDEX);
+		raw_flags_evicted(r);
+	}
+	else
+		raw_flags_to_reg_FLAGSTK(r);
+}
+
+static int FLAG_NREG2_FLAGGEN = 0;
+static __inline__ void raw_reg_to_flags_FLAGGEN(int r)
+{
+	if (have_lahf_lm) {
+		raw_xchg_b_rr(0,AH_INDEX);
+		raw_cmp_b_ri(r,-120); /* set V */
+		raw_sahf(0);
+	}
+	else
+		raw_reg_to_flags_FLAGSTK(r);
+}
+
+static int FLAG_NREG3_FLAGGEN = 0;
+static __inline__ void raw_flags_set_zero_FLAGGEN(int s, int tmp)
+{
+	if (have_lahf_lm)
+		raw_flags_set_zero_FLAGREG(s, tmp);
+	else
+		raw_flags_set_zero_FLAGSTK(s, tmp);
+}
+
+static __inline__ void raw_flags_init_FLAGGEN(void)
+{
+	if (have_lahf_lm) {
+		FLAG_NREG1_FLAGGEN = FLAG_NREG1_FLAGREG;
+		FLAG_NREG2_FLAGGEN = FLAG_NREG2_FLAGREG;
+		FLAG_NREG1_FLAGGEN = FLAG_NREG3_FLAGREG;
+	}
+	else {
+		FLAG_NREG1_FLAGGEN = FLAG_NREG1_FLAGSTK;
+		FLAG_NREG2_FLAGGEN = FLAG_NREG2_FLAGSTK;
+		FLAG_NREG1_FLAGGEN = FLAG_NREG3_FLAGSTK;
+	}
+}
+#endif
+
+#ifdef SAHF_SETO_PROFITABLE
+#define FLAG_SUFFIX FLAGREG
+#elif defined __x86_64__
+#define FLAG_SUFFIX FLAGGEN
+#else
+#define FLAG_SUFFIX FLAGSTK
+#endif
+
+#define FLAG_GLUE_2(x, y)		x ## _ ## y
+#define FLAG_GLUE_1(x, y)		FLAG_GLUE_2(x, y)
+#define FLAG_GLUE(x)			FLAG_GLUE_1(x, FLAG_SUFFIX)
+
+#define raw_flags_init			FLAG_GLUE(raw_flags_init)
+#define FLAG_NREG1				FLAG_GLUE(FLAG_NREG1)
+#define raw_flags_to_reg		FLAG_GLUE(raw_flags_to_reg)
+#define FLAG_NREG2				FLAG_GLUE(FLAG_NREG2)
+#define raw_reg_to_flags		FLAG_GLUE(raw_reg_to_flags)
+#define FLAG_NREG3				FLAG_GLUE(FLAG_NREG3)
+#define raw_flags_set_zero		FLAG_GLUE(raw_flags_set_zero)
+
+/* Apparently, there are enough instructions between flag store and
+   flag reload to avoid the partial memory stall */
+static __inline__ void raw_load_flagreg(uae_u32 target, uae_u32 r)
+{
+#if 1
+    raw_mov_l_rm(target,(uintptr)live.state[r].mem);
+#else
+    raw_mov_b_rm(target,(uintptr)live.state[r].mem);
+    raw_mov_b_rm(target+4,((uintptr)live.state[r].mem)+1);
+#endif
+}
+
+/* FLAGX is byte sized, and we *do* write it at that size */
+static __inline__ void raw_load_flagx(uae_u32 target, uae_u32 r)
+{
+    if (live.nat[target].canbyte)
+	raw_mov_b_rm(target,(uintptr)live.state[r].mem);
+    else if (live.nat[target].canword)
+	raw_mov_w_rm(target,(uintptr)live.state[r].mem);
+    else
+	raw_mov_l_rm(target,(uintptr)live.state[r].mem);
+}
+
+static __inline__ void raw_dec_sp(int off)
+{
+    if (off) raw_sub_l_ri(ESP_INDEX,off);
+}
+
+static __inline__ void raw_inc_sp(int off)
+{
+    if (off) raw_add_l_ri(ESP_INDEX,off);
+}
+
+/*************************************************************************
+ * Handling mistaken direct memory access                                *
+ *************************************************************************/
+
+// gb-- I don't need that part for JIT Basilisk II
+#if defined(NATMEM_OFFSET) && 0
+#include 
+#include 
+
+#define SIG_READ 1
+#define SIG_WRITE 2
+
+static int in_handler=0;
+static uae_u8 veccode[256];
+
+static void vec(int x, struct sigcontext sc)
+{
+    uae_u8* i=(uae_u8*)sc.eip;
+    uae_u32 addr=sc.cr2;
+    int r=-1;
+    int size=4;
+    int dir=-1;
+    int len=0;
+    int j;
+    
+    write_log("fault address is %08x at %08x\n",sc.cr2,sc.eip);
+    if (!canbang) 
+	write_log("Not happy! Canbang is 0 in SIGSEGV handler!\n");
+    if (in_handler) 
+	write_log("Argh --- Am already in a handler. Shouldn't happen!\n");
+
+    if (canbang && i>=compiled_code && i<=current_compile_p) {
+	if (*i==0x66) {
+	    i++;
+	    size=2;
+	    len++;
+	}
+	
+	switch(i[0]) {
+	 case 0x8a:
+                                  	    if ((i[1]&0xc0)==0x80) {
+		r=(i[1]>>3)&7;
+		dir=SIG_READ;
+		size=1;
+		len+=6;
+		break;
+	    }
+	    break;
+	 case 0x88:
+	    if ((i[1]&0xc0)==0x80) {
+		r=(i[1]>>3)&7;
+		dir=SIG_WRITE;
+		size=1;
+		len+=6;
+		break;
+	    }
+	    break;
+	 case 0x8b:
+	    if ((i[1]&0xc0)==0x80) {
+		r=(i[1]>>3)&7;
+		dir=SIG_READ;
+		len+=6;
+		break;
+	    }
+	    if ((i[1]&0xc0)==0x40) {
+		r=(i[1]>>3)&7;
+		dir=SIG_READ;
+		len+=3;
+		break;
+	    }
+	    break;
+	 case 0x89:
+	    if ((i[1]&0xc0)==0x80) {
+		r=(i[1]>>3)&7;
+		dir=SIG_WRITE;
+		len+=6;
+		break;
+	    }
+	    if ((i[1]&0xc0)==0x40) {
+		r=(i[1]>>3)&7;
+		dir=SIG_WRITE;
+		len+=3;
+		break;
+	    }
+	    break;
+	}	
+    }
+
+    if (r!=-1) { 
+	void* pr=NULL;
+	write_log("register was %d, direction was %d, size was %d\n",r,dir,size);
+	
+	switch(r) {
+	 case 0: pr=&(sc.eax); break;
+	 case 1: pr=&(sc.ecx); break;
+	 case 2: pr=&(sc.edx); break;
+	 case 3: pr=&(sc.ebx); break;
+	 case 4: pr=(size>1)?NULL:(((uae_u8*)&(sc.eax))+1); break;
+	 case 5: pr=(size>1)?
+		     (void*)(&(sc.ebp)):
+			 (void*)(((uae_u8*)&(sc.ecx))+1); break;
+	 case 6: pr=(size>1)?
+		     (void*)(&(sc.esi)):
+			 (void*)(((uae_u8*)&(sc.edx))+1); break;
+	 case 7: pr=(size>1)?
+		     (void*)(&(sc.edi)):
+			 (void*)(((uae_u8*)&(sc.ebx))+1); break;
+	 default: abort();
+	}
+	if (pr) {
+	    blockinfo* bi;
+
+	    if (currprefs.comp_oldsegv) {
+	    addr-=NATMEM_OFFSET;
+
+	    if ((addr>=0x10000000 && addr<0x40000000) ||
+		(addr>=0x50000000)) {
+		write_log("Suspicious address in %x SEGV handler.\n",addr);
+	    }
+	    if (dir==SIG_READ) {
+		switch(size) {
+		 case 1: *((uae_u8*)pr)=get_byte(addr); break;
+		 case 2: *((uae_u16*)pr)=get_word(addr); break;
+		 case 4: *((uae_u32*)pr)=get_long(addr); break;
+		 default: abort();
+		}
+	    }
+	    else { /* write */
+		switch(size) {
+		 case 1: put_byte(addr,*((uae_u8*)pr)); break;
+		 case 2: put_word(addr,*((uae_u16*)pr)); break;
+		 case 4: put_long(addr,*((uae_u32*)pr)); break;
+		 default: abort();
+		}
+	    }
+	    write_log("Handled one access!\n");
+	    fflush(stdout);
+	    segvcount++;
+	    sc.eip+=len;
+	    }
+	    else {
+		void* tmp=target;
+		int i;
+		uae_u8 vecbuf[5];
+		
+		addr-=NATMEM_OFFSET;
+		
+		if ((addr>=0x10000000 && addr<0x40000000) ||
+		    (addr>=0x50000000)) {
+		    write_log("Suspicious address in %x SEGV handler.\n",addr);
+		}
+		
+		target=(uae_u8*)sc.eip;
+		for (i=0;i<5;i++)
+		    vecbuf[i]=target[i];
+		emit_byte(0xe9);
+		emit_long((uintptr)veccode-(uintptr)target-4);
+		write_log("Create jump to %p\n",veccode);
+	    
+		write_log("Handled one access!\n");
+		fflush(stdout);
+		segvcount++;
+		
+		target=veccode;
+
+		if (dir==SIG_READ) {
+		    switch(size) {
+		     case 1: raw_mov_b_ri(r,get_byte(addr)); break;
+		     case 2: raw_mov_w_ri(r,get_byte(addr)); break;
+		     case 4: raw_mov_l_ri(r,get_byte(addr)); break;
+		     default: abort();
+		    }
+		}
+		else { /* write */
+		    switch(size) {
+		     case 1: put_byte(addr,*((uae_u8*)pr)); break;
+		     case 2: put_word(addr,*((uae_u16*)pr)); break;
+		     case 4: put_long(addr,*((uae_u32*)pr)); break;
+		     default: abort();
+		    }
+		}
+		for (i=0;i<5;i++)
+		    raw_mov_b_mi(sc.eip+i,vecbuf[i]);
+		raw_mov_l_mi((uintptr)&in_handler,0);
+		emit_byte(0xe9);
+		emit_long(sc.eip+len-(uintptr)target-4);
+		in_handler=1;
+		target=tmp;
+	    }
+	    bi=active;
+	    while (bi) {
+		if (bi->handler && 
+		    (uae_u8*)bi->direct_handler<=i &&
+		    (uae_u8*)bi->nexthandler>i) {
+		    write_log("deleted trigger (%p<%p<%p) %p\n",
+			      bi->handler,
+			      i,
+			      bi->nexthandler,
+			      bi->pc_p);
+		    invalidate_block(bi);
+		    raise_in_cl_list(bi);
+		    set_special(0);
+		    return;
+		}
+		bi=bi->next;
+	    }
+	    /* Not found in the active list. Might be a rom routine that
+	       is in the dormant list */
+	    bi=dormant;
+	    while (bi) {
+		if (bi->handler && 
+		    (uae_u8*)bi->direct_handler<=i &&
+		    (uae_u8*)bi->nexthandler>i) {
+		    write_log("deleted trigger (%p<%p<%p) %p\n",
+			      bi->handler,
+			      i,
+			      bi->nexthandler,
+			      bi->pc_p);
+		    invalidate_block(bi);
+		    raise_in_cl_list(bi);
+		    set_special(0);
+		    return;
+		}
+		bi=bi->next;
+	    }
+	    write_log("Huh? Could not find trigger!\n");
+	    return;
+	}
+    }
+    write_log("Can't handle access!\n");
+    for (j=0;j<10;j++) {
+	write_log("instruction byte %2d is %02x\n",j,i[j]);
+    }
+    write_log("Please send the above info (starting at \"fault address\") to\n"
+	   "bmeyer@csse.monash.edu.au\n"
+	   "This shouldn't happen ;-)\n");
+    fflush(stdout);
+    signal(SIGSEGV,SIG_DFL);  /* returning here will cause a "real" SEGV */
+}
+#endif
+
+
+/*************************************************************************
+ * Checking for CPU features                                             *
+ *************************************************************************/
+
+struct cpuinfo_x86 {
+  uae_u8	x86;			// CPU family
+  uae_u8	x86_vendor;		// CPU vendor
+  uae_u8	x86_processor;	// CPU canonical processor type
+  uae_u8	x86_brand_id;	// CPU BrandID if supported, yield 0 otherwise
+  uae_u32	x86_hwcap;
+  uae_u8	x86_model;
+  uae_u8	x86_mask;
+  int		cpuid_level;    // Maximum supported CPUID level, -1=no CPUID
+  char		x86_vendor_id[16];
+};
+struct cpuinfo_x86 cpuinfo;
+
+enum {
+  X86_VENDOR_INTEL		= 0,
+  X86_VENDOR_CYRIX		= 1,
+  X86_VENDOR_AMD		= 2,
+  X86_VENDOR_UMC		= 3,
+  X86_VENDOR_NEXGEN		= 4,
+  X86_VENDOR_CENTAUR	= 5,
+  X86_VENDOR_RISE		= 6,
+  X86_VENDOR_TRANSMETA	= 7,
+  X86_VENDOR_NSC		= 8,
+  X86_VENDOR_UNKNOWN	= 0xff
+};
+
+enum {
+  X86_PROCESSOR_I386,                       /* 80386 */
+  X86_PROCESSOR_I486,                       /* 80486DX, 80486SX, 80486DX[24] */
+  X86_PROCESSOR_PENTIUM,
+  X86_PROCESSOR_PENTIUMPRO,
+  X86_PROCESSOR_K6,
+  X86_PROCESSOR_ATHLON,
+  X86_PROCESSOR_PENTIUM4,
+  X86_PROCESSOR_X86_64,
+  X86_PROCESSOR_max
+};
+
+static const char * x86_processor_string_table[X86_PROCESSOR_max] = {
+  "80386",
+  "80486",
+  "Pentium",
+  "PentiumPro",
+  "K6",
+  "Athlon",
+  "Pentium4",
+  "x86-64"
+};
+
+static struct ptt {
+  const int align_loop;
+  const int align_loop_max_skip;
+  const int align_jump;
+  const int align_jump_max_skip;
+  const int align_func;
+}
+x86_alignments[X86_PROCESSOR_max] = {
+  {  4,  3,  4,  3,  4 },
+  { 16, 15, 16, 15, 16 },
+  { 16,  7, 16,  7, 16 },
+  { 16, 15, 16,  7, 16 },
+  { 32,  7, 32,  7, 32 },
+  { 16,  7, 16,  7, 16 },
+  {  0,  0,  0,  0,  0 },
+  { 16,  7, 16,  7, 16 }
+};
+
+static void
+x86_get_cpu_vendor(struct cpuinfo_x86 *c)
+{
+	char *v = c->x86_vendor_id;
+
+	if (!strcmp(v, "GenuineIntel"))
+		c->x86_vendor = X86_VENDOR_INTEL;
+	else if (!strcmp(v, "AuthenticAMD"))
+		c->x86_vendor = X86_VENDOR_AMD;
+	else if (!strcmp(v, "CyrixInstead"))
+		c->x86_vendor = X86_VENDOR_CYRIX;
+	else if (!strcmp(v, "Geode by NSC"))
+		c->x86_vendor = X86_VENDOR_NSC;
+	else if (!strcmp(v, "UMC UMC UMC "))
+		c->x86_vendor = X86_VENDOR_UMC;
+	else if (!strcmp(v, "CentaurHauls"))
+		c->x86_vendor = X86_VENDOR_CENTAUR;
+	else if (!strcmp(v, "NexGenDriven"))
+		c->x86_vendor = X86_VENDOR_NEXGEN;
+	else if (!strcmp(v, "RiseRiseRise"))
+		c->x86_vendor = X86_VENDOR_RISE;
+	else if (!strcmp(v, "GenuineTMx86") ||
+		 !strcmp(v, "TransmetaCPU"))
+		c->x86_vendor = X86_VENDOR_TRANSMETA;
+	else
+		c->x86_vendor = X86_VENDOR_UNKNOWN;
+}
+
+static void
+cpuid(uae_u32 op, uae_u32 *eax, uae_u32 *ebx, uae_u32 *ecx, uae_u32 *edx)
+{
+  const int CPUID_SPACE = 4096;
+  uae_u8* cpuid_space = (uae_u8 *)vm_acquire(CPUID_SPACE);
+  if (cpuid_space == VM_MAP_FAILED)
+    abort();
+  vm_protect(cpuid_space, CPUID_SPACE, VM_PAGE_READ | VM_PAGE_WRITE | VM_PAGE_EXECUTE);
+
+  static uae_u32 s_op, s_eax, s_ebx, s_ecx, s_edx;
+  uae_u8* tmp=get_target();
+
+  s_op = op;
+  set_target(cpuid_space);
+  raw_push_l_r(0); /* eax */
+  raw_push_l_r(1); /* ecx */
+  raw_push_l_r(2); /* edx */
+  raw_push_l_r(3); /* ebx */
+  raw_mov_l_rm(0,(uintptr)&s_op);
+  raw_cpuid(0);
+  raw_mov_l_mr((uintptr)&s_eax,0);
+  raw_mov_l_mr((uintptr)&s_ebx,3);
+  raw_mov_l_mr((uintptr)&s_ecx,1);
+  raw_mov_l_mr((uintptr)&s_edx,2);
+  raw_pop_l_r(3);
+  raw_pop_l_r(2);
+  raw_pop_l_r(1);
+  raw_pop_l_r(0);
+  raw_ret();
+  set_target(tmp);
+
+  ((cpuop_func*)cpuid_space)(0);
+  if (eax != NULL) *eax = s_eax;
+  if (ebx != NULL) *ebx = s_ebx;
+  if (ecx != NULL) *ecx = s_ecx;
+  if (edx != NULL) *edx = s_edx;
+
+  vm_release(cpuid_space, CPUID_SPACE);
+}
+
+static void
+raw_init_cpu(void)
+{
+  struct cpuinfo_x86 *c = &cpuinfo;
+
+  /* Defaults */
+  c->x86_processor = X86_PROCESSOR_max;
+  c->x86_vendor = X86_VENDOR_UNKNOWN;
+  c->cpuid_level = -1;				/* CPUID not detected */
+  c->x86_model = c->x86_mask = 0;	/* So far unknown... */
+  c->x86_vendor_id[0] = '\0';		/* Unset */
+  c->x86_hwcap = 0;
+  
+  /* Get vendor name */
+  c->x86_vendor_id[12] = '\0';
+  cpuid(0x00000000,
+		(uae_u32 *)&c->cpuid_level,
+		(uae_u32 *)&c->x86_vendor_id[0],
+		(uae_u32 *)&c->x86_vendor_id[8],
+		(uae_u32 *)&c->x86_vendor_id[4]);
+  x86_get_cpu_vendor(c);
+
+  /* Intel-defined flags: level 0x00000001 */
+  c->x86_brand_id = 0;
+  if ( c->cpuid_level >= 0x00000001 ) {
+	uae_u32 tfms, brand_id;
+	cpuid(0x00000001, &tfms, &brand_id, NULL, &c->x86_hwcap);
+	c->x86 = (tfms >> 8) & 15;
+	if (c->x86 == 0xf)
+		c->x86 += (tfms >> 20) & 0xff; /* extended family */
+	c->x86_model = (tfms >> 4) & 15;
+	if (c->x86_model == 0xf)
+		c->x86_model |= (tfms >> 12) & 0xf0; /* extended model */
+	c->x86_brand_id = brand_id & 0xff;
+	c->x86_mask = tfms & 15;
+  } else {
+	/* Have CPUID level 0 only - unheard of */
+	c->x86 = 4;
+  }
+
+  /* AMD-defined flags: level 0x80000001 */
+  uae_u32 xlvl;
+  cpuid(0x80000000, &xlvl, NULL, NULL, NULL);
+  if ( (xlvl & 0xffff0000) == 0x80000000 ) {
+	if ( xlvl >= 0x80000001 ) {
+	  uae_u32 features, extra_features;
+	  cpuid(0x80000001, NULL, NULL, &extra_features, &features);
+	  if (features & (1 << 29)) {
+		/* Assume x86-64 if long mode is supported */
+		c->x86_processor = X86_PROCESSOR_X86_64;
+	  }
+	  if (extra_features & (1 << 0))
+		  have_lahf_lm = true;
+	}
+  }
+	  
+  /* Canonicalize processor ID */
+  switch (c->x86) {
+  case 3:
+	c->x86_processor = X86_PROCESSOR_I386;
+	break;
+  case 4:
+	c->x86_processor = X86_PROCESSOR_I486;
+	break;
+  case 5:
+	if (c->x86_vendor == X86_VENDOR_AMD)
+	  c->x86_processor = X86_PROCESSOR_K6;
+	else
+	  c->x86_processor = X86_PROCESSOR_PENTIUM;
+	break;
+  case 6:
+	if (c->x86_vendor == X86_VENDOR_AMD)
+	  c->x86_processor = X86_PROCESSOR_ATHLON;
+	else
+	  c->x86_processor = X86_PROCESSOR_PENTIUMPRO;
+	break;
+  case 15:
+	  if (c->x86_processor == X86_PROCESSOR_max) {
+		  switch (c->x86_vendor) {
+		  case X86_VENDOR_INTEL:
+			  c->x86_processor = X86_PROCESSOR_PENTIUM4;
+			  break;
+		  case X86_VENDOR_AMD:
+			  /* Assume a 32-bit Athlon processor if not in long mode */
+			  c->x86_processor = X86_PROCESSOR_ATHLON;
+			  break;
+		  }
+	  }
+	  break;
+  }
+  if (c->x86_processor == X86_PROCESSOR_max) {
+	c->x86_processor = X86_PROCESSOR_I386;
+	fprintf(stderr, "Error: unknown processor type, assuming i386\n");
+	fprintf(stderr, "  Family  : %d\n", c->x86);
+	fprintf(stderr, "  Model   : %d\n", c->x86_model);
+	fprintf(stderr, "  Mask    : %d\n", c->x86_mask);
+	fprintf(stderr, "  Vendor  : %s [%d]\n", c->x86_vendor_id, c->x86_vendor);
+	if (c->x86_brand_id)
+	  fprintf(stderr, "  BrandID : %02x\n", c->x86_brand_id);
+  }
+
+  /* Have CMOV support? */
+  have_cmov = c->x86_hwcap & (1 << 15);
+#if defined(__x86_64__)
+  if (!have_cmov) {
+	  write_log("x86-64 implementations are bound to have CMOV!\n");
+	  abort();
+  }
+#endif
+
+  /* Can the host CPU suffer from partial register stalls? */
+  have_rat_stall = (c->x86_vendor == X86_VENDOR_INTEL);
+#if 1
+  /* It appears that partial register writes are a bad idea even on
+	 AMD K7 cores, even though they are not supposed to have the
+	 dreaded rat stall. Why? Anyway, that's why we lie about it ;-) */
+  if (c->x86_processor == X86_PROCESSOR_ATHLON)
+	have_rat_stall = true;
+#endif
+
+  /* Alignments */
+  if (tune_alignment) {
+	align_loops = x86_alignments[c->x86_processor].align_loop;
+	align_jumps = x86_alignments[c->x86_processor].align_jump;
+  }
+
+  write_log("Max CPUID level=%d Processor is %s [%s]\n",
+			c->cpuid_level, c->x86_vendor_id,
+			x86_processor_string_table[c->x86_processor]);
+
+  raw_flags_init();
+}
+
+static bool target_check_bsf(void)
+{
+	bool mismatch = false;
+	for (int g_ZF = 0; g_ZF <= 1; g_ZF++) {
+	for (int g_CF = 0; g_CF <= 1; g_CF++) {
+	for (int g_OF = 0; g_OF <= 1; g_OF++) {
+	for (int g_SF = 0; g_SF <= 1; g_SF++) {
+		for (int value = -1; value <= 1; value++) {
+			unsigned long flags = (g_SF << 7) | (g_OF << 11) | (g_ZF << 6) | g_CF;
+			unsigned long tmp = value;
+			__asm__ __volatile__ ("push %0; popf; bsf %1,%1; pushf; pop %0"
+								  : "+r" (flags), "+r" (tmp) : : "cc");
+			int OF = (flags >> 11) & 1;
+			int SF = (flags >>  7) & 1;
+			int ZF = (flags >>  6) & 1;
+			int CF = flags & 1;
+			tmp = (value == 0);
+			if (ZF != tmp || SF != g_SF || OF != g_OF || CF != g_CF)
+				mismatch = true;
+		}
+	}}}}
+	if (mismatch)
+		write_log("Target CPU defines all flags on BSF instruction\n");
+	return !mismatch;
+}
+
+
+/*************************************************************************
+ * FPU stuff                                                             *
+ *************************************************************************/
+
+
+static __inline__ void raw_fp_init(void)
+{
+    int i;
+    
+    for (i=0;i1) {
+	emit_byte(0x9b);
+	emit_byte(0xdb);
+	emit_byte(0xe3);
+	live.tos=-1;
+    }
+#endif
+    while (live.tos>=1) {
+	emit_byte(0xde);
+	emit_byte(0xd9);
+	live.tos-=2;
+    }
+    while (live.tos>=0) {
+	emit_byte(0xdd);
+	emit_byte(0xd8);
+	live.tos--;
+    }
+    raw_fp_init();
+}
+
+static __inline__ void make_tos(int r)
+{
+    int p,q;
+
+    if (live.spos[r]<0) { /* Register not yet on stack */
+	emit_byte(0xd9);
+	emit_byte(0xe8);  /* Push '1' on the stack, just to grow it */
+	live.tos++;
+	live.spos[r]=live.tos;
+	live.onstack[live.tos]=r;
+	return;
+    }
+    /* Register is on stack */
+    if (live.tos==live.spos[r])
+	return;
+    p=live.spos[r];
+    q=live.onstack[live.tos];
+
+    emit_byte(0xd9);
+    emit_byte(0xc8+live.tos-live.spos[r]);  /* exchange it with top of stack */
+    live.onstack[live.tos]=r;
+    live.spos[r]=live.tos;
+    live.onstack[p]=q;
+    live.spos[q]=p;
+}
+
+static __inline__ void make_tos2(int r, int r2)
+{
+    int q;
+
+    make_tos(r2); /* Put the reg that's supposed to end up in position2
+		     on top */
+
+    if (live.spos[r]<0) { /* Register not yet on stack */
+	make_tos(r); /* This will extend the stack */
+	return;
+    }
+    /* Register is on stack */
+    emit_byte(0xd9);
+    emit_byte(0xc9); /* Move r2 into position 2 */
+
+    q=live.onstack[live.tos-1];
+    live.onstack[live.tos]=q;
+    live.spos[q]=live.tos;
+    live.onstack[live.tos-1]=r2;
+    live.spos[r2]=live.tos-1;
+
+    make_tos(r); /* And r into 1 */
+}
+
+static __inline__ int stackpos(int r)
+{
+    if (live.spos[r]<0)
+	abort();
+    if (live.tos=0) {
+	/* source is on top of stack, and we already have the dest */
+	int dd=stackpos(d);
+	emit_byte(0xdd);
+	emit_byte(0xd0+dd);
+    }
+    else {
+	emit_byte(0xd9);
+	emit_byte(0xc0+ds); /* duplicate source on tos */
+	tos_make(d); /* store to destination, pop if necessary */
+    }
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s))
+
+LOWFUNC(NONE,READ,4,raw_fldcw_m_indexed,(R4 index, IMM base))
+{
+    emit_byte(0xd9);
+    emit_byte(0xa8+index);
+    emit_long(base);
+}
+LENDFUNC(NONE,READ,4,raw_fldcw_m_indexed,(R4 index, IMM base))
+
+
+LOWFUNC(NONE,NONE,2,raw_fsqrt_rr,(FW d, FR s))
+{
+    int ds;
+
+    if (d!=s) {
+	usereg(s);
+	ds=stackpos(s);
+	emit_byte(0xd9);
+	emit_byte(0xc0+ds); /* duplicate source */
+	emit_byte(0xd9);
+	emit_byte(0xfa); /* take square root */
+	tos_make(d); /* store to destination */
+    }
+    else {
+	make_tos(d);
+	emit_byte(0xd9);
+	emit_byte(0xfa); /* take square root */
+    }	
+}
+LENDFUNC(NONE,NONE,2,raw_fsqrt_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fabs_rr,(FW d, FR s))
+{
+    int ds;
+
+    if (d!=s) {
+	usereg(s);
+	ds=stackpos(s);
+	emit_byte(0xd9);
+	emit_byte(0xc0+ds); /* duplicate source */
+	emit_byte(0xd9);
+	emit_byte(0xe1); /* take fabs */
+	tos_make(d); /* store to destination */
+    }
+    else {
+	make_tos(d);
+	emit_byte(0xd9);
+	emit_byte(0xe1); /* take fabs */
+    }	
+}
+LENDFUNC(NONE,NONE,2,raw_fabs_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_frndint_rr,(FW d, FR s))
+{
+    int ds;
+
+    if (d!=s) {
+	usereg(s);
+	ds=stackpos(s);
+	emit_byte(0xd9);
+	emit_byte(0xc0+ds); /* duplicate source */
+	emit_byte(0xd9);
+	emit_byte(0xfc); /* take frndint */
+	tos_make(d); /* store to destination */
+    }
+    else {
+	make_tos(d);
+	emit_byte(0xd9);
+	emit_byte(0xfc); /* take frndint */
+    }	
+}
+LENDFUNC(NONE,NONE,2,raw_frndint_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fcos_rr,(FW d, FR s))
+{
+    int ds;
+
+    if (d!=s) {
+	usereg(s);
+	ds=stackpos(s);
+	emit_byte(0xd9);
+	emit_byte(0xc0+ds); /* duplicate source */
+	emit_byte(0xd9);
+	emit_byte(0xff); /* take cos */
+	tos_make(d); /* store to destination */
+    }
+    else {
+	make_tos(d);
+	emit_byte(0xd9);
+	emit_byte(0xff); /* take cos */
+    }	
+}
+LENDFUNC(NONE,NONE,2,raw_fcos_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fsin_rr,(FW d, FR s))
+{
+    int ds;
+
+    if (d!=s) {
+	usereg(s);
+	ds=stackpos(s);
+	emit_byte(0xd9);
+	emit_byte(0xc0+ds); /* duplicate source */
+	emit_byte(0xd9);
+	emit_byte(0xfe); /* take sin */
+	tos_make(d); /* store to destination */
+    }
+    else {
+	make_tos(d);
+	emit_byte(0xd9);
+	emit_byte(0xfe); /* take sin */
+    }	
+}
+LENDFUNC(NONE,NONE,2,raw_fsin_rr,(FW d, FR s))
+
+static const double one=1;
+LOWFUNC(NONE,NONE,2,raw_ftwotox_rr,(FW d, FR s))
+{
+    int ds;
+
+    usereg(s);
+    ds=stackpos(s);
+    emit_byte(0xd9);
+    emit_byte(0xc0+ds); /* duplicate source */
+
+    emit_byte(0xd9);
+    emit_byte(0xc0);  /* duplicate top of stack. Now up to 8 high */
+    emit_byte(0xd9);
+    emit_byte(0xfc);  /* rndint */
+    emit_byte(0xd9);
+    emit_byte(0xc9);  /* swap top two elements */
+    emit_byte(0xd8);
+    emit_byte(0xe1);  /* subtract rounded from original */
+    emit_byte(0xd9);
+    emit_byte(0xf0);  /* f2xm1 */
+    x86_fadd_m((uintptr)&one);  /* Add '1' without using extra stack space */
+    emit_byte(0xd9);
+    emit_byte(0xfd);  /* and scale it */
+    emit_byte(0xdd);
+    emit_byte(0xd9);  /* take he rounded value off */
+    tos_make(d); /* store to destination */
+}
+LENDFUNC(NONE,NONE,2,raw_ftwotox_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fetox_rr,(FW d, FR s))
+{
+    int ds;
+
+    usereg(s);
+    ds=stackpos(s);
+    emit_byte(0xd9);
+    emit_byte(0xc0+ds); /* duplicate source */
+    emit_byte(0xd9);
+    emit_byte(0xea);   /* fldl2e */
+    emit_byte(0xde);
+    emit_byte(0xc9);  /* fmulp --- multiply source by log2(e) */
+
+    emit_byte(0xd9);
+    emit_byte(0xc0);  /* duplicate top of stack. Now up to 8 high */
+    emit_byte(0xd9);
+    emit_byte(0xfc);  /* rndint */
+    emit_byte(0xd9);
+    emit_byte(0xc9);  /* swap top two elements */
+    emit_byte(0xd8);
+    emit_byte(0xe1);  /* subtract rounded from original */
+    emit_byte(0xd9);
+    emit_byte(0xf0);  /* f2xm1 */
+    x86_fadd_m((uintptr)&one);  /* Add '1' without using extra stack space */
+    emit_byte(0xd9);
+    emit_byte(0xfd);  /* and scale it */
+    emit_byte(0xdd);
+    emit_byte(0xd9);  /* take he rounded value off */
+    tos_make(d); /* store to destination */
+}
+LENDFUNC(NONE,NONE,2,raw_fetox_rr,(FW d, FR s))
+ 
+LOWFUNC(NONE,NONE,2,raw_flog2_rr,(FW d, FR s))
+{
+    int ds;
+
+    usereg(s);
+    ds=stackpos(s);
+    emit_byte(0xd9);
+    emit_byte(0xc0+ds); /* duplicate source */
+    emit_byte(0xd9);
+    emit_byte(0xe8); /* push '1' */
+    emit_byte(0xd9);
+    emit_byte(0xc9); /* swap top two */
+    emit_byte(0xd9);
+    emit_byte(0xf1); /* take 1*log2(x) */
+    tos_make(d); /* store to destination */
+}
+LENDFUNC(NONE,NONE,2,raw_flog2_rr,(FW d, FR s))
+
+
+LOWFUNC(NONE,NONE,2,raw_fneg_rr,(FW d, FR s))
+{
+    int ds;
+
+    if (d!=s) {
+	usereg(s);
+	ds=stackpos(s);
+	emit_byte(0xd9);
+	emit_byte(0xc0+ds); /* duplicate source */
+	emit_byte(0xd9);
+	emit_byte(0xe0); /* take fchs */
+	tos_make(d); /* store to destination */
+    }
+    else {
+	make_tos(d);
+	emit_byte(0xd9);
+	emit_byte(0xe0); /* take fchs */
+    }	
+}
+LENDFUNC(NONE,NONE,2,raw_fneg_rr,(FW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fadd_rr,(FRW d, FR s))
+{
+    int ds;
+
+    usereg(s);
+    usereg(d);
+    
+    if (live.spos[s]==live.tos) {
+	/* Source is on top of stack */
+	ds=stackpos(d);
+	emit_byte(0xdc);
+	emit_byte(0xc0+ds); /* add source to dest*/
+    }
+    else {
+	make_tos(d);
+	ds=stackpos(s);
+	
+	emit_byte(0xd8);
+	emit_byte(0xc0+ds); /* add source to dest*/
+    }
+}
+LENDFUNC(NONE,NONE,2,raw_fadd_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fsub_rr,(FRW d, FR s))
+{
+    int ds;
+
+    usereg(s);
+    usereg(d);
+    
+    if (live.spos[s]==live.tos) {
+	/* Source is on top of stack */
+	ds=stackpos(d);
+	emit_byte(0xdc);
+	emit_byte(0xe8+ds); /* sub source from dest*/
+    }
+    else {
+	make_tos(d);
+	ds=stackpos(s);
+	
+	emit_byte(0xd8);
+	emit_byte(0xe0+ds); /* sub src from dest */
+    }
+}
+LENDFUNC(NONE,NONE,2,raw_fsub_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fcmp_rr,(FR d, FR s))
+{
+    int ds;
+
+    usereg(s);
+    usereg(d);
+    
+    make_tos(d);
+    ds=stackpos(s);
+
+    emit_byte(0xdd);
+    emit_byte(0xe0+ds); /* cmp dest with source*/
+}
+LENDFUNC(NONE,NONE,2,raw_fcmp_rr,(FR d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fmul_rr,(FRW d, FR s))
+{
+    int ds;
+
+    usereg(s);
+    usereg(d);
+    
+    if (live.spos[s]==live.tos) {
+	/* Source is on top of stack */
+	ds=stackpos(d);
+	emit_byte(0xdc);
+	emit_byte(0xc8+ds); /* mul dest by source*/
+    }
+    else {
+	make_tos(d);
+	ds=stackpos(s);
+	
+	emit_byte(0xd8);
+	emit_byte(0xc8+ds); /* mul dest by source*/
+    }
+}
+LENDFUNC(NONE,NONE,2,raw_fmul_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_fdiv_rr,(FRW d, FR s))
+{
+    int ds;
+
+    usereg(s);
+    usereg(d);
+    
+    if (live.spos[s]==live.tos) {
+	/* Source is on top of stack */
+	ds=stackpos(d);
+	emit_byte(0xdc);
+	emit_byte(0xf8+ds); /* div dest by source */
+    }
+    else {
+	make_tos(d);
+	ds=stackpos(s);
+	
+	emit_byte(0xd8);
+	emit_byte(0xf0+ds); /* div dest by source*/
+    }
+}
+LENDFUNC(NONE,NONE,2,raw_fdiv_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_frem_rr,(FRW d, FR s))
+{
+    int ds;
+
+    usereg(s);
+    usereg(d);
+    
+    make_tos2(d,s);
+    ds=stackpos(s);
+
+    if (ds!=1) {
+	printf("Failed horribly in raw_frem_rr! ds is %d\n",ds);
+	abort();
+    }
+    emit_byte(0xd9);
+    emit_byte(0xf8); /* take rem from dest by source */
+}
+LENDFUNC(NONE,NONE,2,raw_frem_rr,(FRW d, FR s))
+
+LOWFUNC(NONE,NONE,2,raw_frem1_rr,(FRW d, FR s))
+{
+    int ds;
+
+    usereg(s);
+    usereg(d);
+    
+    make_tos2(d,s);
+    ds=stackpos(s);
+
+    if (ds!=1) {
+	printf("Failed horribly in raw_frem1_rr! ds is %d\n",ds);
+	abort();
+    }
+    emit_byte(0xd9);
+    emit_byte(0xf5); /* take rem1 from dest by source */
+}
+LENDFUNC(NONE,NONE,2,raw_frem1_rr,(FRW d, FR s))
+
+
+LOWFUNC(NONE,NONE,1,raw_ftst_r,(FR r))
+{
+    make_tos(r);
+    emit_byte(0xd9);  /* ftst */
+    emit_byte(0xe4);
+}
+LENDFUNC(NONE,NONE,1,raw_ftst_r,(FR r))
+
+/* %eax register is clobbered if target processor doesn't support fucomi */
+#define FFLAG_NREG_CLOBBER_CONDITION !have_cmov
+#define FFLAG_NREG EAX_INDEX
+
+static __inline__ void raw_fflags_into_flags(int r)
+{
+    int p;
+
+    usereg(r);
+    p=stackpos(r);
+
+    emit_byte(0xd9);
+    emit_byte(0xee); /* Push 0 */
+    emit_byte(0xd9);
+    emit_byte(0xc9+p); /* swap top two around */
+	if (have_cmov) {
+		// gb-- fucomi is for P6 cores only, not K6-2 then...
+    	emit_byte(0xdb);
+    	emit_byte(0xe9+p); /* fucomi them */
+	}
+	else {
+		emit_byte(0xdd);
+		emit_byte(0xe1+p); /* fucom them */
+		emit_byte(0x9b);
+		emit_byte(0xdf);
+		emit_byte(0xe0); /* fstsw ax */
+		raw_sahf(0); /* sahf */
+	}
+    emit_byte(0xdd);
+    emit_byte(0xd9+p);  /* store value back, and get rid of 0 */
+}
diff --git a/src/cpu/jit/codegen_x86.h b/src/cpu/jit/codegen_x86.h
new file mode 100644
index 0000000..86066b1
--- /dev/null
+++ b/src/cpu/jit/codegen_x86.h
@@ -0,0 +1,2424 @@
+/******************** -*- mode: C; tab-width: 8 -*- ********************
+ *
+ *	Run-time assembler for IA-32 and AMD64
+ *
+ ***********************************************************************/
+
+
+/***********************************************************************
+ *
+ *  This file is derived from CCG.
+ *
+ *  Copyright 1999, 2000, 2001, 2002, 2003 Ian Piumarta
+ *
+ *  Adaptations and enhancements for AMD64 support, Copyright 2003-2008
+ *    Gwenole Beauchesne
+ *
+ *  Basilisk II (C) 1997-2008 Christian Bauer
+ *  
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ ***********************************************************************/
+
+#ifndef X86_RTASM_H
+#define X86_RTASM_H
+
+/* NOTES
+ *
+ *	o Best viewed on a 1024x768 screen with fixed-6x10 font ;-)
+ *
+ * TODO
+ *
+ *	o Fix FIXMEs
+ *	o i387 FPU instructions
+ *	o SSE instructions
+ *	o Optimize for cases where register numbers are not integral constants
+ */
+
+/* --- Configuration ------------------------------------------------------- */
+
+/* Define to settle a "flat" register set, i.e. different regno for
+   each size variant.  */
+#ifndef X86_FLAT_REGISTERS
+#define X86_FLAT_REGISTERS	1
+#endif
+
+/* Define to generate x86-64 code.  */
+#ifndef X86_TARGET_64BIT
+#define X86_TARGET_64BIT	0
+#endif
+
+/* Define to optimize ALU instructions.  */
+#ifndef X86_OPTIMIZE_ALU
+#define X86_OPTIMIZE_ALU	1
+#endif
+
+/* Define to optimize rotate/shift instructions.  */
+#ifndef X86_OPTIMIZE_ROTSHI
+#define X86_OPTIMIZE_ROTSHI	1
+#endif
+
+/* Define to optimize absolute addresses for RIP relative addressing.  */
+#ifndef X86_RIP_RELATIVE_ADDR
+#define X86_RIP_RELATIVE_ADDR	1
+#endif 
+
+
+/* --- Macros -------------------------------------------------------------- */
+
+/* Functions used to emit code.
+ *
+ *	x86_emit_byte(B)
+ *	x86_emit_word(W)
+ *	x86_emit_long(L)
+ */
+
+/* Get pointer to current code
+ *
+ *	x86_get_target()
+ */
+
+/* Abort assembler, fatal failure.
+ *
+ *	x86_emit_failure(MSG)
+ */
+
+#define x86_emit_failure0(MSG) (x86_emit_failure(MSG),0)
+
+
+/* --- Register set -------------------------------------------------------- */
+
+enum {
+  X86_RIP         = -2,
+#if X86_FLAT_REGISTERS
+  X86_NOREG       = 0,
+  X86_Reg8L_Base  = 0x10,
+  X86_Reg8H_Base  = 0x20,
+  X86_Reg16_Base  = 0x30,
+  X86_Reg32_Base  = 0x40,
+  X86_Reg64_Base  = 0x50,
+  X86_RegMMX_Base = 0x60,
+  X86_RegXMM_Base = 0x70,
+#else
+  X86_NOREG       = -1,
+  X86_Reg8L_Base  = 0,
+  X86_Reg8H_Base  = 16,
+  X86_Reg16_Base  = 0,
+  X86_Reg32_Base  = 0,
+  X86_Reg64_Base  = 0,
+  X86_RegMMX_Base = 0,
+  X86_RegXMM_Base = 0,
+#endif
+};
+
+enum {
+  X86_AL  = X86_Reg8L_Base,
+  X86_CL,   X86_DL,   X86_BL,
+  X86_SPL,  X86_BPL,  X86_SIL,  X86_DIL,
+  X86_R8B,  X86_R9B,  X86_R10B, X86_R11B,
+  X86_R12B, X86_R13B, X86_R14B, X86_R15B,
+  X86_AH  = X86_Reg8H_Base + 4,
+  X86_CH,   X86_DH,   X86_BH
+};
+
+enum {
+  X86_AX  = X86_Reg16_Base,
+  X86_CX,   X86_DX,   X86_BX,
+  X86_SP,   X86_BP,   X86_SI,   X86_DI,
+  X86_R8W,  X86_R9W,  X86_R10W, X86_R11W,
+  X86_R12W, X86_R13W, X86_R14W, X86_R15W
+};
+
+enum {
+  X86_EAX = X86_Reg32_Base,
+  X86_ECX,  X86_EDX,  X86_EBX,
+  X86_ESP,  X86_EBP,  X86_ESI,  X86_EDI,
+  X86_R8D,  X86_R9D,  X86_R10D, X86_R11D,
+  X86_R12D, X86_R13D, X86_R14D, X86_R15D
+};
+
+enum {
+  X86_RAX = X86_Reg64_Base,
+  X86_RCX,  X86_RDX,  X86_RBX,
+  X86_RSP,  X86_RBP,  X86_RSI,  X86_RDI,
+  X86_R8,   X86_R9,   X86_R10,  X86_R11,
+  X86_R12,  X86_R13,  X86_R14,  X86_R15
+};
+
+enum {
+  X86_MM0 = X86_RegMMX_Base,
+  X86_MM1,  X86_MM2,  X86_MM3,
+  X86_MM4,  X86_MM5,  X86_MM6,  X86_MM7,
+};
+
+enum {
+  X86_XMM0 = X86_RegXMM_Base,
+  X86_XMM1,  X86_XMM2,  X86_XMM3,
+  X86_XMM4,  X86_XMM5,  X86_XMM6,  X86_XMM7,
+  X86_XMM8,  X86_XMM9,  X86_XMM10, X86_XMM11,
+  X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15
+};
+
+/* Register control and access
+ *
+ *	_r0P(R)	Null register?
+ *	_rIP(R)	RIP register?
+ *	_rXP(R)	Extended register?
+ *
+ *	_rC(R)	Class of register (only valid if X86_FLAT_REGISTERS)
+ *	_rR(R)	Full register number
+ *	_rN(R)	Short register number for encoding
+ *
+ *	_r1(R)	8-bit register ID
+ *	_r2(R)	16-bit register ID
+ *	_r4(R)	32-bit register ID
+ *	_r8(R)	64-bit register ID
+ *	_rM(R)	MMX register ID
+ *	_rX(R)	XMM register ID
+ *	_rA(R)	Address register ID used for EA calculation
+ */
+
+#define _r0P(R)		((int)(R) == (int)X86_NOREG)
+#define _rIP(R)		(X86_TARGET_64BIT ? ((int)(R) == (int)X86_RIP) : 0)
+
+#if X86_FLAT_REGISTERS
+#define _rC(R)		((R) & 0xf0)
+#define _rR(R)		((R) & 0x0f)
+#define _rN(R)		((R) & 0x07)
+#define _rXP(R)		((R) > 0 && _rR(R) > 7)
+#else
+#define _rN(R)		((R) & 0x07)
+#define _rR(R)		(int(R))
+#define _rXP(R)		(_rR(R) > 7 && _rR(R) < 16)
+#endif
+
+#if !defined(_ASM_SAFETY) || ! X86_FLAT_REGISTERS
+#define _r1(R)		_rN(R)
+#define _r2(R)		_rN(R)
+#define _r4(R)		_rN(R)
+#define _r8(R)		_rN(R)
+#define _rA(R)		_rN(R)
+#define _rM(R)		_rN(R)
+#define _rX(R)		_rN(R)
+#else
+#define _r1(R)		( ((_rC(R) & (X86_Reg8L_Base | X86_Reg8H_Base)) != 0)	? _rN(R) : x86_emit_failure0( "8-bit register required"))
+#define _r2(R)		( (_rC(R) == X86_Reg16_Base)				? _rN(R) : x86_emit_failure0("16-bit register required"))
+#define _r4(R)		( (_rC(R) == X86_Reg32_Base)				? _rN(R) : x86_emit_failure0("32-bit register required"))
+#define _r8(R)		( (_rC(R) == X86_Reg64_Base)				? _rN(R) : x86_emit_failure0("64-bit register required"))
+#define _rA(R)		( X86_TARGET_64BIT ? \
+			( (_rC(R) == X86_Reg64_Base)				? _rN(R) : x86_emit_failure0("not a valid 64-bit base/index expression")) : \
+			( (_rC(R) == X86_Reg32_Base)				? _rN(R) : x86_emit_failure0("not a valid 32-bit base/index expression")) )
+#define _rM(R)		( (_rC(R) == X86_RegMMX_Base)				? _rN(R) : x86_emit_failure0("MMX register required"))
+#define _rX(R)		( (_rC(R) == X86_RegXMM_Base)				? _rN(R) : x86_emit_failure0("SSE register required"))
+#endif
+
+#define _rSP()		(X86_TARGET_64BIT ? (int)X86_RSP : (int)X86_ESP)
+#define _r1e8lP(R)	(int(R) >= X86_SPL && int(R) <= X86_DIL)
+#define _rbpP(R)	(_rR(R) == _rR(X86_RBP))
+#define _rspP(R)	(_rR(R) == _rR(X86_RSP))
+#define _rbp13P(R)	(_rN(R) == _rN(X86_RBP))
+#define _rsp12P(R)	(_rN(R) == _rN(X86_RSP))
+
+
+/* ========================================================================= */
+/* --- UTILITY ------------------------------------------------------------- */
+/* ========================================================================= */
+
+typedef signed char	_sc;
+typedef unsigned char	_uc;
+typedef signed short	_ss;
+typedef unsigned short	_us;
+typedef signed int	_sl;
+typedef unsigned int	_ul;
+
+#define _UC(X)		((_uc  )(unsigned long)(X))
+#define _US(X)		((_us  )(unsigned long)(X))
+#define _SL(X)		((_sl  )(unsigned long)(X))
+#define _UL(X)		((_ul  )(unsigned long)(X))
+
+#define _PUC(X)		((_uc *)(X))
+#define _PUS(X)		((_us *)(X))
+#define _PSL(X)		((_sl *)(X))
+#define _PUL(X)		((_ul *)(X))
+
+#define _B(B)		x86_emit_byte((B))
+#define _W(W)		x86_emit_word((W))
+#define _L(L)		x86_emit_long((L))
+#define _Q(Q)		x86_emit_quad((Q))
+
+#define _MASK(N)	((unsigned)((1<<(N)))-1)
+#define _siP(N,I)	(!((((unsigned)(I))^(((unsigned)(I))<<1))&~_MASK(N)))
+#define _uiP(N,I)	(!(((unsigned)(I))&~_MASK(N)))
+#define _suiP(N,I)	(_siP(N,I) | _uiP(N,I))
+
+#ifndef _ASM_SAFETY
+#define _ck_s(W,I)	(_UL(I) & _MASK(W))
+#define _ck_u(W,I)    	(_UL(I) & _MASK(W))
+#define _ck_su(W,I)    	(_UL(I) & _MASK(W))
+#define _ck_d(W,I)    	(_UL(I) & _MASK(W))
+#else
+#define _ck_s(W,I)	(_siP(W,I) ? (_UL(I) & _MASK(W)) : x86_emit_failure0(  "signed integer `"#I"' too large for "#W"-bit field"))
+#define _ck_u(W,I)    	(_uiP(W,I) ? (_UL(I) & _MASK(W)) : x86_emit_failure0("unsigned integer `"#I"' too large for "#W"-bit field"))
+#define _ck_su(W,I)    	(_suiP(W,I) ? (_UL(I) & _MASK(W)) : x86_emit_failure0(        "integer `"#I"' too large for "#W"-bit field"))
+#define _ck_d(W,I)    	(_siP(W,I) ? (_UL(I) & _MASK(W)) : x86_emit_failure0(    "displacement `"#I"' too large for "#W"-bit field"))
+#endif
+
+#define _s0P(I)		((I)==0)
+#define _s8P(I)		_siP(8,I)
+#define _s16P(I)	_siP(16,I)
+#define _u8P(I)		_uiP(8,I)
+#define _u16P(I)	_uiP(16,I)
+
+#define _su8(I)		_ck_su(8,I)
+#define _su16(I)	_ck_su(16,I)
+
+#define _s1(I)          _ck_s( 1,I)
+#define _s2(I)          _ck_s( 2,I)
+#define _s3(I)          _ck_s( 3,I)
+#define _s4(I)          _ck_s( 4,I)
+#define _s5(I)          _ck_s( 5,I)
+#define _s6(I)          _ck_s( 6,I)
+#define _s7(I)          _ck_s( 7,I)
+#define _s8(I)          _ck_s( 8,I)
+#define _s9(I)          _ck_s( 9,I)
+#define _s10(I)         _ck_s(10,I)
+#define _s11(I)         _ck_s(11,I)
+#define _s12(I)         _ck_s(12,I)
+#define _s13(I)         _ck_s(13,I)
+#define _s14(I)         _ck_s(14,I)
+#define _s15(I)         _ck_s(15,I)
+#define _s16(I)         _ck_s(16,I)
+#define _s17(I)         _ck_s(17,I)
+#define _s18(I)         _ck_s(18,I)
+#define _s19(I)         _ck_s(19,I)
+#define _s20(I)         _ck_s(20,I)
+#define _s21(I)         _ck_s(21,I)
+#define _s22(I)         _ck_s(22,I)
+#define _s23(I)         _ck_s(23,I)
+#define _s24(I)         _ck_s(24,I)
+#define _s25(I)         _ck_s(25,I)
+#define _s26(I)         _ck_s(26,I)
+#define _s27(I)         _ck_s(27,I)
+#define _s28(I)         _ck_s(28,I)
+#define _s29(I)         _ck_s(29,I)
+#define _s30(I)         _ck_s(30,I)
+#define _s31(I)         _ck_s(31,I)
+#define _u1(I)          _ck_u( 1,I)
+#define _u2(I)          _ck_u( 2,I)
+#define _u3(I)          _ck_u( 3,I)
+#define _u4(I)          _ck_u( 4,I)
+#define _u5(I)          _ck_u( 5,I)
+#define _u6(I)          _ck_u( 6,I)
+#define _u7(I)          _ck_u( 7,I)
+#define _u8(I)          _ck_u( 8,I)
+#define _u9(I)          _ck_u( 9,I)
+#define _u10(I)         _ck_u(10,I)
+#define _u11(I)         _ck_u(11,I)
+#define _u12(I)         _ck_u(12,I)
+#define _u13(I)         _ck_u(13,I)
+#define _u14(I)         _ck_u(14,I)
+#define _u15(I)         _ck_u(15,I)
+#define _u16(I)         _ck_u(16,I)
+#define _u17(I)         _ck_u(17,I)
+#define _u18(I)         _ck_u(18,I)
+#define _u19(I)         _ck_u(19,I)
+#define _u20(I)         _ck_u(20,I)
+#define _u21(I)         _ck_u(21,I)
+#define _u22(I)         _ck_u(22,I)
+#define _u23(I)         _ck_u(23,I)
+#define _u24(I)         _ck_u(24,I)
+#define _u25(I)         _ck_u(25,I)
+#define _u26(I)         _ck_u(26,I)
+#define _u27(I)         _ck_u(27,I)
+#define _u28(I)         _ck_u(28,I)
+#define _u29(I)         _ck_u(29,I)
+#define _u30(I)         _ck_u(30,I)
+#define _u31(I)         _ck_u(31,I)
+
+/* ========================================================================= */
+/* --- ASSEMBLER ----------------------------------------------------------- */
+/* ========================================================================= */
+
+#define _b00		0
+#define _b01		1
+#define _b10		2
+#define _b11		3
+
+#define _b000		0
+#define _b001		1
+#define _b010		2
+#define _b011		3
+#define _b100		4
+#define _b101		5
+#define _b110		6
+#define _b111		7
+
+#define _OFF4(D)	(_UL(D) - _UL(x86_get_target()))
+#define _CKD8(D)	_ck_d(8, ((_uc) _OFF4(D)) )
+
+#define _D8(D)		(_B(0), ((*(_PUC(x86_get_target())-1))= _CKD8(D)))
+#define _D32(D)		(_L(0), ((*(_PUL(x86_get_target())-1))= _OFF4(D)))
+
+#ifndef _ASM_SAFETY
+# define _M(M)		(M)
+# define _r(R)		(R)
+# define _m(M)		(M)
+# define _s(S)		(S)
+# define _i(I)		(I)
+# define _b(B)		(B)
+#else
+# define _M(M)		(((M)>3) ? x86_emit_failure0("internal error: mod = " #M) : (M))
+# define _r(R)		(((R)>7) ? x86_emit_failure0("internal error: reg = " #R) : (R))
+# define _m(M)		(((M)>7) ? x86_emit_failure0("internal error: r/m = " #M) : (M))
+# define _s(S)		(((S)>3) ? x86_emit_failure0("internal error: memory scale = " #S) : (S))
+# define _i(I)		(((I)>7) ? x86_emit_failure0("internal error: memory index = " #I) : (I))
+# define _b(B)		(((B)>7) ? x86_emit_failure0("internal error: memory base = "  #B) : (B))
+#endif
+
+#define _Mrm(Md,R,M)	_B((_M(Md)<<6)|(_r(R)<<3)|_m(M))
+#define _SIB(Sc,I, B)	_B((_s(Sc)<<6)|(_i(I)<<3)|_b(B))
+
+#define _SCL(S)		((((S)==1) ? _b00 : \
+			 (((S)==2) ? _b01 : \
+			 (((S)==4) ? _b10 : \
+			 (((S)==8) ? _b11 : x86_emit_failure0("illegal scale: " #S))))))
+
+
+/* --- Memory subformats - urgh! ------------------------------------------- */
+
+/* _r_D() is RIP addressing mode if X86_TARGET_64BIT, use _r_DSIB() instead */
+#define _r_D(	R, D	  )	(_Mrm(_b00,_rN(R),_b101 )		             ,_L((_sl)(D)))
+#define _r_DSIB(R, D      )	(_Mrm(_b00,_rN(R),_b100 ),_SIB(_SCL(1),_b100 ,_b101 ),_L((_sl)(D)))
+#define _r_0B(	R,   B    )	(_Mrm(_b00,_rN(R),_rA(B))			                   )
+#define _r_0BIS(R,   B,I,S)	(_Mrm(_b00,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_rA(B))              )
+#define _r_1B(	R, D,B    )	(_Mrm(_b01,_rN(R),_rA(B))		             ,_B((_sc)(D)))
+#define _r_1BIS(R, D,B,I,S)	(_Mrm(_b01,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_rA(B)),_B((_sc)(D)))
+#define _r_4B(	R, D,B    )	(_Mrm(_b10,_rN(R),_rA(B))		             ,_L((_sl)(D)))
+#define _r_4IS( R, D,I,S)	(_Mrm(_b00,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_b101 ),_L((_sl)(D)))
+#define _r_4BIS(R, D,B,I,S)	(_Mrm(_b10,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_rA(B)),_L((_sl)(D)))
+
+#define _r_DB(  R, D,B    )	((_s0P(D) && (!_rbp13P(B)) ? _r_0B  (R,  B    ) : (_s8P(D) ? _r_1B(  R,D,B    ) : _r_4B(  R,D,B    ))))
+#define _r_DBIS(R, D,B,I,S)	((_s0P(D) && (!_rbp13P(B)) ? _r_0BIS(R,  B,I,S) : (_s8P(D) ? _r_1BIS(R,D,B,I,S) : _r_4BIS(R,D,B,I,S))))
+
+/* Use RIP-addressing in 64-bit mode, if possible */
+#define _x86_RIP_addressing_possible(D,O)	(X86_RIP_RELATIVE_ADDR && \
+						((uintptr)x86_get_target() + 4 + (O) - (D) <= 0xffffffff))
+
+#define _r_X(   R, D,B,I,S,O)	(_r0P(I) ? (_r0P(B)    ? (!X86_TARGET_64BIT ? _r_D(R,D) : \
+					                 (_x86_RIP_addressing_possible(D, O) ? \
+				                          _r_D(R, (D) - ((uintptr)x86_get_target() + 4 + (O))) : \
+				                          _r_DSIB(R,D))) : \
+				           (_rIP(B)    ? _r_D   (R,D                )   : \
+				           (_rsp12P(B) ? _r_DBIS(R,D,_rSP(),_rSP(),1)   : \
+						         _r_DB  (R,D,     B       ))))  : \
+				 (_r0P(B)	       ? _r_4IS (R,D,	         I,S)   : \
+				 (!_rspP(I)            ? _r_DBIS(R,D,     B,     I,S)   : \
+						         x86_emit_failure("illegal index register: %esp"))))
+
+
+/* --- Instruction formats ------------------------------------------------- */
+
+#define _m32only(X)		(! X86_TARGET_64BIT ? X : x86_emit_failure("invalid instruction in 64-bit mode"))
+#define _m64only(X)		(  X86_TARGET_64BIT ? X : x86_emit_failure("invalid instruction in 32-bit mode"))
+#define _m64(X)			(  X86_TARGET_64BIT ? X : ((void)0)						)
+
+/*	 _format						     Opcd	  ModR/M dN(rB,rI,Sc)	  imm... */
+
+#define	 _d16()					   (		  _B(0x66	)				  )
+#define	  _O(	     OP				)  (		  _B(  OP	)				  )
+#define	  _Or(	     OP,R			)  (		  _B( (OP)|_r(R))				  )
+#define	 _OO(	     OP				)  ( _B((OP)>>8), _B(( (OP)      )&0xff)			  )
+#define	 _OOr(	     OP,R			)  ( _B((OP)>>8), _B(( (OP)|_r(R))&0xff)			  )
+#define	  _Os(	     OP,B			)  (	_s8P(B) ? _B(((OP)|_b10)) : _B(OP)			  )
+#define	    _sW(			     W	)  (				       _s8P(W) ? _B(W):_W(W)	  )
+#define	    _sL(			     L	)  (				       _s8P(L) ? _B(L):_L(L)	  )
+#define	    _sWO(			     W	)  (				       _s8P(W) ?    1 :   2	  )
+#define	    _sLO(			     L	)  (				       _s8P(L) ?    1 :   4	  )
+#define	  _O_B(	     OP			    ,B	)  (	    _O	    (  OP  )			      ,_B(B)	  )
+#define	  _O_W(	     OP			    ,W	)  (	    _O	    (  OP  )			      ,_W(W)	  )
+#define	  _O_L(	     OP			    ,L	)  (	    _O	    (  OP  )			      ,_L(L)	  )
+#define	  _OO_L(     OP			    ,L	)  (	   _OO	    (  OP  )			      ,_L(L)	  )
+#define	  _O_D8(     OP			    ,D	)  (	    _O	    (  OP  )			     ,_D8(D)	  )
+#define	  _O_D32(     OP		    ,D	)  (	    _O	    (  OP  )			     ,_D32(D)	  )
+#define	 _OO_D32(     OP		    ,D	)  (	   _OO	    (  OP  )			     ,_D32(D)	  )
+#define	  _Os_sW(    OP			    ,W	)  (	    _Os	    (  OP,W)			     ,_sW(W)	  )
+#define	  _Os_sL(    OP			    ,L	)  (	    _Os	    (  OP,L)			     ,_sL(L)	  )
+#define	  _O_W_B(    OP			    ,W,B)  (	    _O	    (  OP  )			      ,_W(W),_B(B))
+#define	  _Or_B(     OP,R		    ,B	)  (	    _Or	    (  OP,R)			      ,_B(B)	  )
+#define	  _Or_W(     OP,R		    ,W	)  (	    _Or	    (  OP,R)			      ,_W(W)	  )
+#define	  _Or_L(     OP,R		    ,L	)  (	    _Or	    (  OP,R)			      ,_L(L)	  )
+#define	  _Or_Q(     OP,R		    ,Q	)  (	    _Or	    (  OP,R)			      ,_Q(Q)	  )
+#define	  _O_Mrm(    OP	 ,MO,R,M		)  (	    _O	    (  OP  ),_Mrm(MO,R,M	    )		  )
+#define	 _OO_Mrm(    OP	 ,MO,R,M		)  (	   _OO	    (  OP  ),_Mrm(MO,R,M	    )		  )
+#define	  _O_Mrm_B(  OP	 ,MO,R,M	    ,B	)  (	    _O	    (  OP  ),_Mrm(MO,R,M	    ) ,_B(B)	  )
+#define	  _O_Mrm_W(  OP	 ,MO,R,M	    ,W	)  (	    _O	    (  OP  ),_Mrm(MO,R,M	    ) ,_W(W)	  )
+#define	  _O_Mrm_L(  OP	 ,MO,R,M	    ,L	)  (	    _O	    (  OP  ),_Mrm(MO,R,M	    ) ,_L(L)	  )
+#define	 _OO_Mrm_B(  OP	 ,MO,R,M	    ,B	)  (	   _OO	    (  OP  ),_Mrm(MO,R,M	    ) ,_B(B)	  )
+#define	  _Os_Mrm_sW(OP	 ,MO,R,M	    ,W	)  (	    _Os	    (  OP,W),_Mrm(MO,R,M	    ),_sW(W)	  )
+#define	  _Os_Mrm_sL(OP	 ,MO,R,M	    ,L	)  (	    _Os	    (  OP,L),_Mrm(MO,R,M	    ),_sL(L)	  )
+#define	  _O_r_X(    OP	    ,R	,MD,MB,MI,MS	)  (	    _O	    (  OP  ),_r_X(   R	,MD,MB,MI,MS,0)		  )
+#define	 _OO_r_X(    OP	    ,R	,MD,MB,MI,MS	)  (	   _OO	    (  OP  ),_r_X(   R	,MD,MB,MI,MS,0)		  )
+#define	  _O_r_X_B(  OP	    ,R	,MD,MB,MI,MS,B	)  (	    _O	    (  OP  ),_r_X(   R	,MD,MB,MI,MS,1) ,_B(B)	  )
+#define	  _O_r_X_W(  OP	    ,R	,MD,MB,MI,MS,W	)  (	    _O	    (  OP  ),_r_X(   R	,MD,MB,MI,MS,2) ,_W(W)	  )
+#define	  _O_r_X_L(  OP	    ,R	,MD,MB,MI,MS,L	)  (	    _O	    (  OP  ),_r_X(   R	,MD,MB,MI,MS,4) ,_L(L)	  )
+#define	 _OO_r_X_B(  OP	    ,R	,MD,MB,MI,MS,B	)  (	   _OO	    (  OP  ),_r_X(   R	,MD,MB,MI,MS,1) ,_B(B)	  )
+#define	  _Os_r_X_sW(OP	    ,R	,MD,MB,MI,MS,W	)  (	    _Os	    (  OP,W),_r_X(   R	,MD,MB,MI,MS,_sWO(W)),_sW(W))
+#define	  _Os_r_X_sL(OP	    ,R	,MD,MB,MI,MS,L	)  (	    _Os	    (  OP,L),_r_X(   R	,MD,MB,MI,MS,_sLO(L)),_sL(L))
+#define	  _O_X_B(    OP		,MD,MB,MI,MS,B	)  (	    _O_r_X_B(  OP	    ,0	,MD,MB,MI,MS	 ,B)	  )
+#define	  _O_X_W(    OP		,MD,MB,MI,MS,W	)  (	    _O_r_X_W(  OP	    ,0	,MD,MB,MI,MS	 ,W)	  )
+#define	  _O_X_L(    OP		,MD,MB,MI,MS,L	)  (	    _O_r_X_L(  OP	    ,0	,MD,MB,MI,MS	 ,L)	  )
+
+
+/* --- REX prefixes -------------------------------------------------------- */
+
+#define _VOID()			((void)0)
+#define _BIT(X)			(!!(X))
+#define _d64(W,R,X,B)		(_B(0x40|(W)<<3|(R)<<2|(X)<<1|(B)))
+
+#define __REXwrxb(L,W,R,X,B)	((W|R|X|B) || (L) ? _d64(W,R,X,B) : _VOID())
+#define __REXwrx_(L,W,R,X,MR)	(__REXwrxb(L,W,R,X,_BIT(_rIP(MR)?0:_rXP(MR))))
+#define __REXw_x_(L,W,R,X,MR)	(__REXwrx_(L,W,_BIT(_rXP(R)),X,MR))
+#define __REX_reg(RR)		(__REXwrxb(0,0,0,00,_BIT(_rXP(RR))))
+#define __REX_mem(MB,MI)	(__REXwrxb(0,0,0,_BIT(_rXP(MI)),_BIT(_rXP(MB))))
+
+// FIXME: can't mix new (SPL,BPL,SIL,DIL) with (AH,BH,CH,DH)
+#define _REXBrr(RR,MR)		_m64(__REXw_x_(_r1e8lP(RR)||_r1e8lP(MR),0,RR,0,MR))
+#define _REXBmr(MB,MI,RD)	_m64(__REXw_x_(_r1e8lP(RD)||_r1e8lP(MB),0,RD,_BIT(_rXP(MI)),MB))
+#define _REXBrm(RS,MB,MI)	_REXBmr(MB,MI,RS)
+
+#define _REXBLrr(RR,MR)		_m64(__REXw_x_(_r1e8lP(MR),0,RR,0,MR))
+#define _REXLrr(RR,MR)		_m64(__REXw_x_(0,0,RR,0,MR))
+#define _REXLmr(MB,MI,RD)	_m64(__REXw_x_(0,0,RD,_BIT(_rXP(MI)),MB))
+#define _REXLrm(RS,MB,MI)	_REXLmr(MB,MI,RS)
+#define _REXLr(RR)		_m64(__REX_reg(RR))
+#define _REXLm(MB,MI)		_m64(__REX_mem(MB,MI))
+
+#define _REXQrr(RR,MR)		_m64only(__REXw_x_(0,1,RR,0,MR))
+#define _REXQmr(MB,MI,RD)	_m64only(__REXw_x_(0,1,RD,_BIT(_rXP(MI)),MB))
+#define _REXQrm(RS,MB,MI)	_REXQmr(MB,MI,RS)
+#define _REXQr(RR)		_m64only(__REX_reg(RR))
+#define _REXQm(MB,MI)		_m64only(__REX_mem(MB,MI))
+
+
+/* ========================================================================= */
+/* --- Fully-qualified intrinsic instructions ------------------------------ */
+/* ========================================================================= */
+
+/*	OPCODE	+ i	= immediate operand
+ *		+ r	= register operand
+ *		+ m	= memory operand (disp,base,index,scale)
+ *		+ sr/sm	= a star preceding a register or memory
+ *		+ 0	= top of stack register (for FPU instructions)
+ *
+ *	NOTE in x86-64 mode: a memory operand with only a valid
+ *	displacement value will lead to the expect absolute mode. If
+ *	RIP addressing is necessary, X86_RIP shall be used as the base
+ *	register argument.
+ */
+
+/* --- ALU instructions ---------------------------------------------------- */
+
+enum {
+  X86_ADD = 0,
+  X86_OR  = 1,
+  X86_ADC = 2,
+  X86_SBB = 3,
+  X86_AND = 4,
+  X86_SUB = 5,
+  X86_XOR = 6,
+  X86_CMP = 7,
+};
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+
+#define _ALUBrr(OP,RS, RD)		(_REXBrr(RS, RD),		_O_Mrm		(((OP) << 3)	,_b11,_r1(RS),_r1(RD)				))
+#define _ALUBmr(OP, MD, MB, MI, MS, RD)	(_REXBmr(MB, MI, RD),		_O_r_X		(((OP) << 3) + 2     ,_r1(RD)		,MD,MB,MI,MS		))
+#define _ALUBrm(OP, RS, MD, MB, MI, MS)	(_REXBrm(RS, MB, MI),		_O_r_X		(((OP) << 3)	     ,_r1(RS)		,MD,MB,MI,MS		))
+#define _ALUBir(OP, IM, RD)		(X86_OPTIMIZE_ALU && ((RD) == X86_AL) ? \
+					(_REXBrr(0, RD),		_O_B		(((OP) << 3) + 4					,_su8(IM))) : \
+					(_REXBrr(0, RD),		_O_Mrm_B	(0x80		,_b11,OP     ,_r1(RD)			,_su8(IM))) )
+#define _ALUBim(OP, IM, MD, MB, MI, MS)	(_REXBrm(0, MB, MI),		_O_r_X_B	(0x80		     ,OP		,MD,MB,MI,MS	,_su8(IM)))
+
+#define _ALUWrr(OP, RS, RD)		(_d16(), _REXLrr(RS, RD),	_O_Mrm		(((OP) << 3) + 1,_b11,_r2(RS),_r2(RD)				))
+#define _ALUWmr(OP, MD, MB, MI, MS, RD)	(_d16(), _REXLmr(MB, MI, RD),	_O_r_X		(((OP) << 3) + 3     ,_r2(RD)		,MD,MB,MI,MS		))
+#define _ALUWrm(OP, RS, MD, MB, MI, MS)	(_d16(), _REXLrm(RS, MB, MI),	_O_r_X		(((OP) << 3) + 1     ,_r2(RS)		,MD,MB,MI,MS		))
+#define _ALUWir(OP, IM, RD)		(X86_OPTIMIZE_ALU && ((RD) == X86_AX) ? \
+					(_d16(), _REXLrr(0, RD),	_O_W		(((OP) << 3) + 5					,_su16(IM))) : \
+					(_d16(), _REXLrr(0, RD),	_Os_Mrm_sW	(0x81		,_b11,OP     ,_r2(RD)			,_su16(IM))) )
+#define _ALUWim(OP, IM, MD, MB, MI, MS)	(_d16(), _REXLrm(0, MB, MI),	_Os_r_X_sW	(0x81		     ,OP		,MD,MB,MI,MS	,_su16(IM)))
+
+#define _ALULrr(OP, RS, RD)		(_REXLrr(RS, RD),		_O_Mrm		(((OP) << 3) + 1,_b11,_r4(RS),_r4(RD)				))
+#define _ALULmr(OP, MD, MB, MI, MS, RD)	(_REXLmr(MB, MI, RD),		_O_r_X		(((OP) << 3) + 3     ,_r4(RD)		,MD,MB,MI,MS		))
+#define _ALULrm(OP, RS, MD, MB, MI, MS)	(_REXLrm(RS, MB, MI),		_O_r_X		(((OP) << 3) + 1     ,_r4(RS)		,MD,MB,MI,MS		))
+#define _ALULir(OP, IM, RD)		(X86_OPTIMIZE_ALU && ((RD) == X86_EAX) ? \
+					(_REXLrr(0, RD),		_O_L		(((OP) << 3) + 5					,IM	)) : \
+					(_REXLrr(0, RD),		_Os_Mrm_sL	(0x81		,_b11,OP     ,_r4(RD)			,IM	)) )
+#define _ALULim(OP, IM, MD, MB, MI, MS)	(_REXLrm(0, MB, MI),		_Os_r_X_sL	(0x81		     ,OP		,MD,MB,MI,MS	,IM	))
+
+#define _ALUQrr(OP, RS, RD)		(_REXQrr(RS, RD),		_O_Mrm		(((OP) << 3) + 1,_b11,_r8(RS),_r8(RD)				))
+#define _ALUQmr(OP, MD, MB, MI, MS, RD)	(_REXQmr(MB, MI, RD),		_O_r_X		(((OP) << 3) + 3     ,_r8(RD)		,MD,MB,MI,MS		))
+#define _ALUQrm(OP, RS, MD, MB, MI, MS)	(_REXQrm(RS, MB, MI),		_O_r_X		(((OP) << 3) + 1     ,_r8(RS)		,MD,MB,MI,MS		))
+#define _ALUQir(OP, IM, RD)		(X86_OPTIMIZE_ALU && ((RD) == X86_RAX) ? \
+					(_REXQrr(0, RD),		_O_L		(((OP) << 3) + 5					,IM	)) : \
+					(_REXQrr(0, RD),		_Os_Mrm_sL	(0x81		,_b11,OP     ,_r8(RD)			,IM	)) )
+#define _ALUQim(OP, IM, MD, MB, MI, MS)	(_REXQrm(0, MB, MI),		_Os_r_X_sL	(0x81		     ,OP		,MD,MB,MI,MS	,IM	))
+
+#define ADCBrr(RS, RD)			_ALUBrr(X86_ADC, RS, RD)
+#define ADCBmr(MD, MB, MI, MS, RD)	_ALUBmr(X86_ADC, MD, MB, MI, MS, RD)
+#define ADCBrm(RS, MD, MB, MI, MS)	_ALUBrm(X86_ADC, RS, MD, MB, MI, MS)
+#define ADCBir(IM, RD)			_ALUBir(X86_ADC, IM, RD)
+#define ADCBim(IM, MD, MB, MI, MS)	_ALUBim(X86_ADC, IM, MD, MB, MI, MS)
+
+#define ADCWrr(RS, RD)			_ALUWrr(X86_ADC, RS, RD)
+#define ADCWmr(MD, MB, MI, MS, RD)	_ALUWmr(X86_ADC, MD, MB, MI, MS, RD)
+#define ADCWrm(RS, MD, MB, MI, MS)	_ALUWrm(X86_ADC, RS, MD, MB, MI, MS)
+#define ADCWir(IM, RD)			_ALUWir(X86_ADC, IM, RD)
+#define ADCWim(IM, MD, MB, MI, MS)	_ALUWim(X86_ADC, IM, MD, MB, MI, MS)
+
+#define ADCLrr(RS, RD)			_ALULrr(X86_ADC, RS, RD)
+#define ADCLmr(MD, MB, MI, MS, RD)	_ALULmr(X86_ADC, MD, MB, MI, MS, RD)
+#define ADCLrm(RS, MD, MB, MI, MS)	_ALULrm(X86_ADC, RS, MD, MB, MI, MS)
+#define ADCLir(IM, RD)			_ALULir(X86_ADC, IM, RD)
+#define ADCLim(IM, MD, MB, MI, MS)	_ALULim(X86_ADC, IM, MD, MB, MI, MS)
+
+#define ADCQrr(RS, RD)			_ALUQrr(X86_ADC, RS, RD)
+#define ADCQmr(MD, MB, MI, MS, RD)	_ALUQmr(X86_ADC, MD, MB, MI, MS, RD)
+#define ADCQrm(RS, MD, MB, MI, MS)	_ALUQrm(X86_ADC, RS, MD, MB, MI, MS)
+#define ADCQir(IM, RD)			_ALUQir(X86_ADC, IM, RD)
+#define ADCQim(IM, MD, MB, MI, MS)	_ALUQim(X86_ADC, IM, MD, MB, MI, MS)
+
+#define ADDBrr(RS, RD)			_ALUBrr(X86_ADD, RS, RD)
+#define ADDBmr(MD, MB, MI, MS, RD)	_ALUBmr(X86_ADD, MD, MB, MI, MS, RD)
+#define ADDBrm(RS, MD, MB, MI, MS)	_ALUBrm(X86_ADD, RS, MD, MB, MI, MS)
+#define ADDBir(IM, RD)			_ALUBir(X86_ADD, IM, RD)
+#define ADDBim(IM, MD, MB, MI, MS)	_ALUBim(X86_ADD, IM, MD, MB, MI, MS)
+
+#define ADDWrr(RS, RD)			_ALUWrr(X86_ADD, RS, RD)
+#define ADDWmr(MD, MB, MI, MS, RD)	_ALUWmr(X86_ADD, MD, MB, MI, MS, RD)
+#define ADDWrm(RS, MD, MB, MI, MS)	_ALUWrm(X86_ADD, RS, MD, MB, MI, MS)
+#define ADDWir(IM, RD)			_ALUWir(X86_ADD, IM, RD)
+#define ADDWim(IM, MD, MB, MI, MS)	_ALUWim(X86_ADD, IM, MD, MB, MI, MS)
+
+#define ADDLrr(RS, RD)			_ALULrr(X86_ADD, RS, RD)
+#define ADDLmr(MD, MB, MI, MS, RD)	_ALULmr(X86_ADD, MD, MB, MI, MS, RD)
+#define ADDLrm(RS, MD, MB, MI, MS)	_ALULrm(X86_ADD, RS, MD, MB, MI, MS)
+#define ADDLir(IM, RD)			_ALULir(X86_ADD, IM, RD)
+#define ADDLim(IM, MD, MB, MI, MS)	_ALULim(X86_ADD, IM, MD, MB, MI, MS)
+
+#define ADDQrr(RS, RD)			_ALUQrr(X86_ADD, RS, RD)
+#define ADDQmr(MD, MB, MI, MS, RD)	_ALUQmr(X86_ADD, MD, MB, MI, MS, RD)
+#define ADDQrm(RS, MD, MB, MI, MS)	_ALUQrm(X86_ADD, RS, MD, MB, MI, MS)
+#define ADDQir(IM, RD)			_ALUQir(X86_ADD, IM, RD)
+#define ADDQim(IM, MD, MB, MI, MS)	_ALUQim(X86_ADD, IM, MD, MB, MI, MS)
+
+#define ANDBrr(RS, RD)			_ALUBrr(X86_AND, RS, RD)
+#define ANDBmr(MD, MB, MI, MS, RD)	_ALUBmr(X86_AND, MD, MB, MI, MS, RD)
+#define ANDBrm(RS, MD, MB, MI, MS)	_ALUBrm(X86_AND, RS, MD, MB, MI, MS)
+#define ANDBir(IM, RD)			_ALUBir(X86_AND, IM, RD)
+#define ANDBim(IM, MD, MB, MI, MS)	_ALUBim(X86_AND, IM, MD, MB, MI, MS)
+
+#define ANDWrr(RS, RD)			_ALUWrr(X86_AND, RS, RD)
+#define ANDWmr(MD, MB, MI, MS, RD)	_ALUWmr(X86_AND, MD, MB, MI, MS, RD)
+#define ANDWrm(RS, MD, MB, MI, MS)	_ALUWrm(X86_AND, RS, MD, MB, MI, MS)
+#define ANDWir(IM, RD)			_ALUWir(X86_AND, IM, RD)
+#define ANDWim(IM, MD, MB, MI, MS)	_ALUWim(X86_AND, IM, MD, MB, MI, MS)
+
+#define ANDLrr(RS, RD)			_ALULrr(X86_AND, RS, RD)
+#define ANDLmr(MD, MB, MI, MS, RD)	_ALULmr(X86_AND, MD, MB, MI, MS, RD)
+#define ANDLrm(RS, MD, MB, MI, MS)	_ALULrm(X86_AND, RS, MD, MB, MI, MS)
+#define ANDLir(IM, RD)			_ALULir(X86_AND, IM, RD)
+#define ANDLim(IM, MD, MB, MI, MS)	_ALULim(X86_AND, IM, MD, MB, MI, MS)
+
+#define ANDQrr(RS, RD)			_ALUQrr(X86_AND, RS, RD)
+#define ANDQmr(MD, MB, MI, MS, RD)	_ALUQmr(X86_AND, MD, MB, MI, MS, RD)
+#define ANDQrm(RS, MD, MB, MI, MS)	_ALUQrm(X86_AND, RS, MD, MB, MI, MS)
+#define ANDQir(IM, RD)			_ALUQir(X86_AND, IM, RD)
+#define ANDQim(IM, MD, MB, MI, MS)	_ALUQim(X86_AND, IM, MD, MB, MI, MS)
+
+#define CMPBrr(RS, RD)			_ALUBrr(X86_CMP, RS, RD)
+#define CMPBmr(MD, MB, MI, MS, RD)	_ALUBmr(X86_CMP, MD, MB, MI, MS, RD)
+#define CMPBrm(RS, MD, MB, MI, MS)	_ALUBrm(X86_CMP, RS, MD, MB, MI, MS)
+#define CMPBir(IM, RD)			_ALUBir(X86_CMP, IM, RD)
+#define CMPBim(IM, MD, MB, MI, MS)	_ALUBim(X86_CMP, IM, MD, MB, MI, MS)
+
+#define CMPWrr(RS, RD)			_ALUWrr(X86_CMP, RS, RD)
+#define CMPWmr(MD, MB, MI, MS, RD)	_ALUWmr(X86_CMP, MD, MB, MI, MS, RD)
+#define CMPWrm(RS, MD, MB, MI, MS)	_ALUWrm(X86_CMP, RS, MD, MB, MI, MS)
+#define CMPWir(IM, RD)			_ALUWir(X86_CMP, IM, RD)
+#define CMPWim(IM, MD, MB, MI, MS)	_ALUWim(X86_CMP, IM, MD, MB, MI, MS)
+
+#define CMPLrr(RS, RD)			_ALULrr(X86_CMP, RS, RD)
+#define CMPLmr(MD, MB, MI, MS, RD)	_ALULmr(X86_CMP, MD, MB, MI, MS, RD)
+#define CMPLrm(RS, MD, MB, MI, MS)	_ALULrm(X86_CMP, RS, MD, MB, MI, MS)
+#define CMPLir(IM, RD)			_ALULir(X86_CMP, IM, RD)
+#define CMPLim(IM, MD, MB, MI, MS)	_ALULim(X86_CMP, IM, MD, MB, MI, MS)
+
+#define CMPQrr(RS, RD)			_ALUQrr(X86_CMP, RS, RD)
+#define CMPQmr(MD, MB, MI, MS, RD)	_ALUQmr(X86_CMP, MD, MB, MI, MS, RD)
+#define CMPQrm(RS, MD, MB, MI, MS)	_ALUQrm(X86_CMP, RS, MD, MB, MI, MS)
+#define CMPQir(IM, RD)			_ALUQir(X86_CMP, IM, RD)
+#define CMPQim(IM, MD, MB, MI, MS)	_ALUQim(X86_CMP, IM, MD, MB, MI, MS)
+
+#define ORBrr(RS, RD)			_ALUBrr(X86_OR, RS, RD)
+#define ORBmr(MD, MB, MI, MS, RD)	_ALUBmr(X86_OR, MD, MB, MI, MS, RD)
+#define ORBrm(RS, MD, MB, MI, MS)	_ALUBrm(X86_OR, RS, MD, MB, MI, MS)
+#define ORBir(IM, RD)			_ALUBir(X86_OR, IM, RD)
+#define ORBim(IM, MD, MB, MI, MS)	_ALUBim(X86_OR, IM, MD, MB, MI, MS)
+
+#define ORWrr(RS, RD)			_ALUWrr(X86_OR, RS, RD)
+#define ORWmr(MD, MB, MI, MS, RD)	_ALUWmr(X86_OR, MD, MB, MI, MS, RD)
+#define ORWrm(RS, MD, MB, MI, MS)	_ALUWrm(X86_OR, RS, MD, MB, MI, MS)
+#define ORWir(IM, RD)			_ALUWir(X86_OR, IM, RD)
+#define ORWim(IM, MD, MB, MI, MS)	_ALUWim(X86_OR, IM, MD, MB, MI, MS)
+
+#define ORLrr(RS, RD)			_ALULrr(X86_OR, RS, RD)
+#define ORLmr(MD, MB, MI, MS, RD)	_ALULmr(X86_OR, MD, MB, MI, MS, RD)
+#define ORLrm(RS, MD, MB, MI, MS)	_ALULrm(X86_OR, RS, MD, MB, MI, MS)
+#define ORLir(IM, RD)			_ALULir(X86_OR, IM, RD)
+#define ORLim(IM, MD, MB, MI, MS)	_ALULim(X86_OR, IM, MD, MB, MI, MS)
+
+#define ORQrr(RS, RD)			_ALUQrr(X86_OR, RS, RD)
+#define ORQmr(MD, MB, MI, MS, RD)	_ALUQmr(X86_OR, MD, MB, MI, MS, RD)
+#define ORQrm(RS, MD, MB, MI, MS)	_ALUQrm(X86_OR, RS, MD, MB, MI, MS)
+#define ORQir(IM, RD)			_ALUQir(X86_OR, IM, RD)
+#define ORQim(IM, MD, MB, MI, MS)	_ALUQim(X86_OR, IM, MD, MB, MI, MS)
+
+#define SBBBrr(RS, RD)			_ALUBrr(X86_SBB, RS, RD)
+#define SBBBmr(MD, MB, MI, MS, RD)	_ALUBmr(X86_SBB, MD, MB, MI, MS, RD)
+#define SBBBrm(RS, MD, MB, MI, MS)	_ALUBrm(X86_SBB, RS, MD, MB, MI, MS)
+#define SBBBir(IM, RD)			_ALUBir(X86_SBB, IM, RD)
+#define SBBBim(IM, MD, MB, MI, MS)	_ALUBim(X86_SBB, IM, MD, MB, MI, MS)
+
+#define SBBWrr(RS, RD)			_ALUWrr(X86_SBB, RS, RD)
+#define SBBWmr(MD, MB, MI, MS, RD)	_ALUWmr(X86_SBB, MD, MB, MI, MS, RD)
+#define SBBWrm(RS, MD, MB, MI, MS)	_ALUWrm(X86_SBB, RS, MD, MB, MI, MS)
+#define SBBWir(IM, RD)			_ALUWir(X86_SBB, IM, RD)
+#define SBBWim(IM, MD, MB, MI, MS)	_ALUWim(X86_SBB, IM, MD, MB, MI, MS)
+
+#define SBBLrr(RS, RD)			_ALULrr(X86_SBB, RS, RD)
+#define SBBLmr(MD, MB, MI, MS, RD)	_ALULmr(X86_SBB, MD, MB, MI, MS, RD)
+#define SBBLrm(RS, MD, MB, MI, MS)	_ALULrm(X86_SBB, RS, MD, MB, MI, MS)
+#define SBBLir(IM, RD)			_ALULir(X86_SBB, IM, RD)
+#define SBBLim(IM, MD, MB, MI, MS)	_ALULim(X86_SBB, IM, MD, MB, MI, MS)
+
+#define SBBQrr(RS, RD)			_ALUQrr(X86_SBB, RS, RD)
+#define SBBQmr(MD, MB, MI, MS, RD)	_ALUQmr(X86_SBB, MD, MB, MI, MS, RD)
+#define SBBQrm(RS, MD, MB, MI, MS)	_ALUQrm(X86_SBB, RS, MD, MB, MI, MS)
+#define SBBQir(IM, RD)			_ALUQir(X86_SBB, IM, RD)
+#define SBBQim(IM, MD, MB, MI, MS)	_ALUQim(X86_SBB, IM, MD, MB, MI, MS)
+
+#define SUBBrr(RS, RD)			_ALUBrr(X86_SUB, RS, RD)
+#define SUBBmr(MD, MB, MI, MS, RD)	_ALUBmr(X86_SUB, MD, MB, MI, MS, RD)
+#define SUBBrm(RS, MD, MB, MI, MS)	_ALUBrm(X86_SUB, RS, MD, MB, MI, MS)
+#define SUBBir(IM, RD)			_ALUBir(X86_SUB, IM, RD)
+#define SUBBim(IM, MD, MB, MI, MS)	_ALUBim(X86_SUB, IM, MD, MB, MI, MS)
+
+#define SUBWrr(RS, RD)			_ALUWrr(X86_SUB, RS, RD)
+#define SUBWmr(MD, MB, MI, MS, RD)	_ALUWmr(X86_SUB, MD, MB, MI, MS, RD)
+#define SUBWrm(RS, MD, MB, MI, MS)	_ALUWrm(X86_SUB, RS, MD, MB, MI, MS)
+#define SUBWir(IM, RD)			_ALUWir(X86_SUB, IM, RD)
+#define SUBWim(IM, MD, MB, MI, MS)	_ALUWim(X86_SUB, IM, MD, MB, MI, MS)
+
+#define SUBLrr(RS, RD)			_ALULrr(X86_SUB, RS, RD)
+#define SUBLmr(MD, MB, MI, MS, RD)	_ALULmr(X86_SUB, MD, MB, MI, MS, RD)
+#define SUBLrm(RS, MD, MB, MI, MS)	_ALULrm(X86_SUB, RS, MD, MB, MI, MS)
+#define SUBLir(IM, RD)			_ALULir(X86_SUB, IM, RD)
+#define SUBLim(IM, MD, MB, MI, MS)	_ALULim(X86_SUB, IM, MD, MB, MI, MS)
+
+#define SUBQrr(RS, RD)			_ALUQrr(X86_SUB, RS, RD)
+#define SUBQmr(MD, MB, MI, MS, RD)	_ALUQmr(X86_SUB, MD, MB, MI, MS, RD)
+#define SUBQrm(RS, MD, MB, MI, MS)	_ALUQrm(X86_SUB, RS, MD, MB, MI, MS)
+#define SUBQir(IM, RD)			_ALUQir(X86_SUB, IM, RD)
+#define SUBQim(IM, MD, MB, MI, MS)	_ALUQim(X86_SUB, IM, MD, MB, MI, MS)
+
+#define XORBrr(RS, RD)			_ALUBrr(X86_XOR, RS, RD)
+#define XORBmr(MD, MB, MI, MS, RD)	_ALUBmr(X86_XOR, MD, MB, MI, MS, RD)
+#define XORBrm(RS, MD, MB, MI, MS)	_ALUBrm(X86_XOR, RS, MD, MB, MI, MS)
+#define XORBir(IM, RD)			_ALUBir(X86_XOR, IM, RD)
+#define XORBim(IM, MD, MB, MI, MS)	_ALUBim(X86_XOR, IM, MD, MB, MI, MS)
+
+#define XORWrr(RS, RD)			_ALUWrr(X86_XOR, RS, RD)
+#define XORWmr(MD, MB, MI, MS, RD)	_ALUWmr(X86_XOR, MD, MB, MI, MS, RD)
+#define XORWrm(RS, MD, MB, MI, MS)	_ALUWrm(X86_XOR, RS, MD, MB, MI, MS)
+#define XORWir(IM, RD)			_ALUWir(X86_XOR, IM, RD)
+#define XORWim(IM, MD, MB, MI, MS)	_ALUWim(X86_XOR, IM, MD, MB, MI, MS)
+
+#define XORLrr(RS, RD)			_ALULrr(X86_XOR, RS, RD)
+#define XORLmr(MD, MB, MI, MS, RD)	_ALULmr(X86_XOR, MD, MB, MI, MS, RD)
+#define XORLrm(RS, MD, MB, MI, MS)	_ALULrm(X86_XOR, RS, MD, MB, MI, MS)
+#define XORLir(IM, RD)			_ALULir(X86_XOR, IM, RD)
+#define XORLim(IM, MD, MB, MI, MS)	_ALULim(X86_XOR, IM, MD, MB, MI, MS)
+
+#define XORQrr(RS, RD)			_ALUQrr(X86_XOR, RS, RD)
+#define XORQmr(MD, MB, MI, MS, RD)	_ALUQmr(X86_XOR, MD, MB, MI, MS, RD)
+#define XORQrm(RS, MD, MB, MI, MS)	_ALUQrm(X86_XOR, RS, MD, MB, MI, MS)
+#define XORQir(IM, RD)			_ALUQir(X86_XOR, IM, RD)
+#define XORQim(IM, MD, MB, MI, MS)	_ALUQim(X86_XOR, IM, MD, MB, MI, MS)
+
+
+/* --- Shift/Rotate instructions ------------------------------------------- */
+
+enum {
+  X86_ROL = 0,
+  X86_ROR = 1,
+  X86_RCL = 2,
+  X86_RCR = 3,
+  X86_SHL = 4,
+  X86_SHR = 5,
+  X86_SAR = 7,
+};
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+
+#define _ROTSHIBir(OP,IM,RD)		(X86_OPTIMIZE_ROTSHI && ((IM) == 1) ? \
+					(_REXBrr(0, RD),		_O_Mrm		(0xd0		,_b11,OP,_r1(RD)				)) : \
+					(_REXBrr(0, RD),		_O_Mrm_B	(0xc0		,_b11,OP,_r1(RD)			,_u8(IM))) )
+#define _ROTSHIBim(OP,IM,MD,MB,MI,MS)	(X86_OPTIMIZE_ROTSHI && ((IM) == 1) ? \
+					(_REXBrm(0, MB, MI),		_O_r_X		(0xd0		     ,OP		,MD,MB,MI,MS		)) : \
+					(_REXBrm(0, MB, MI),		_O_r_X_B	(0xc0		     ,OP		,MD,MB,MI,MS	,_u8(IM))) )
+#define _ROTSHIBrr(OP,RS,RD)		(((RS) == X86_CL) ? \
+					(_REXBrr(RS, RD),		_O_Mrm		(0xd2		,_b11,OP,_r1(RD)				)) : \
+									x86_emit_failure("source register must be CL"					)  )
+#define _ROTSHIBrm(OP,RS,MD,MB,MI,MS)	(((RS) == X86_CL) ? \
+					(_REXBrm(RS, MB, MI),		_O_r_X		(0xd2		     ,OP		,MD,MB,MI,MS		)) : \
+									x86_emit_failure("source register must be CL"					)  )
+
+#define _ROTSHIWir(OP,IM,RD)		(X86_OPTIMIZE_ROTSHI && ((IM) == 1) ? \
+					(_d16(), _REXLrr(0, RD),	_O_Mrm		(0xd1		,_b11,OP,_r2(RD)				)) : \
+					(_d16(), _REXLrr(0, RD),	_O_Mrm_B	(0xc1		,_b11,OP,_r2(RD)			,_u8(IM))) )
+#define _ROTSHIWim(OP,IM,MD,MB,MI,MS)	(X86_OPTIMIZE_ROTSHI && ((IM) == 1) ? \
+					(_d16(), _REXLrm(0, MB, MI),	_O_r_X		(0xd1		     ,OP		,MD,MB,MI,MS		)) : \
+					(_d16(), _REXLrm(0, MB, MI),	_O_r_X_B	(0xc1		     ,OP		,MD,MB,MI,MS	,_u8(IM))) )
+#define _ROTSHIWrr(OP,RS,RD)		(((RS) == X86_CL) ? \
+					(_d16(), _REXLrr(RS, RD),	_O_Mrm		(0xd3		,_b11,OP,_r2(RD)				)) : \
+									x86_emit_failure("source register must be CL"					)  )
+#define _ROTSHIWrm(OP,RS,MD,MB,MI,MS)	(((RS) == X86_CL) ? \
+					(_d16(), _REXLrm(RS, MB, MI),	_O_r_X		(0xd3		     ,OP		,MD,MB,MI,MS		)) : \
+									x86_emit_failure("source register must be CL"					)  )
+
+#define _ROTSHILir(OP,IM,RD)		(X86_OPTIMIZE_ROTSHI && ((IM) == 1) ? \
+					(_REXLrr(0, RD),		_O_Mrm		(0xd1		,_b11,OP,_r4(RD)				)) : \
+					(_REXLrr(0, RD),		_O_Mrm_B	(0xc1		,_b11,OP,_r4(RD)			,_u8(IM))) )
+#define _ROTSHILim(OP,IM,MD,MB,MI,MS)	(X86_OPTIMIZE_ROTSHI && ((IM) == 1) ? \
+					(_REXLrm(0, MB, MI),		_O_r_X		(0xd1		     ,OP		,MD,MB,MI,MS		)) : \
+					(_REXLrm(0, MB, MI),		_O_r_X_B	(0xc1		     ,OP		,MD,MB,MI,MS	,_u8(IM))) )
+#define _ROTSHILrr(OP,RS,RD)		(((RS) == X86_CL) ? \
+					(_REXLrr(RS, RD),		_O_Mrm		(0xd3		,_b11,OP,_r4(RD)				)) : \
+									x86_emit_failure("source register must be CL"					)  )
+#define _ROTSHILrm(OP,RS,MD,MB,MI,MS)	(((RS) == X86_CL) ? \
+					(_REXLrm(RS, MB, MI),		_O_r_X		(0xd3		     ,OP		,MD,MB,MI,MS		)) : \
+									x86_emit_failure("source register must be CL"					)  )
+
+#define _ROTSHIQir(OP,IM,RD)		(X86_OPTIMIZE_ROTSHI && ((IM) == 1) ? \
+					(_REXQrr(0, RD),		_O_Mrm		(0xd1		,_b11,OP,_r8(RD)				)) : \
+					(_REXQrr(0, RD),		_O_Mrm_B	(0xc1		,_b11,OP,_r8(RD)			,_u8(IM))) )
+#define _ROTSHIQim(OP,IM,MD,MB,MI,MS)	(X86_OPTIMIZE_ROTSHI && ((IM) == 1) ? \
+					(_REXQrm(0, MB, MI),		_O_r_X		(0xd1		     ,OP		,MD,MB,MI,MS		)) : \
+					(_REXQrm(0, MB, MI),		_O_r_X_B	(0xc1		     ,OP		,MD,MB,MI,MS	,_u8(IM))) )
+#define _ROTSHIQrr(OP,RS,RD)		(((RS) == X86_CL) ? \
+					(_REXQrr(RS, RD),		_O_Mrm		(0xd3		,_b11,OP,_r8(RD)				)) : \
+									x86_emit_failure("source register must be CL"					)  )
+#define _ROTSHIQrm(OP,RS,MD,MB,MI,MS)	(((RS) == X86_CL) ? \
+					(_REXQrm(RS, MB, MI),		_O_r_X		(0xd3		     ,OP		,MD,MB,MI,MS		)) : \
+									x86_emit_failure("source register must be CL"					)  )
+
+#define ROLBir(IM, RD)			_ROTSHIBir(X86_ROL, IM, RD)
+#define ROLBim(IM, MD, MB, MI, MS)	_ROTSHIBim(X86_ROL, IM, MD, MB, MI, MS)
+#define ROLBrr(RS, RD)			_ROTSHIBrr(X86_ROL, RS, RD)
+#define ROLBrm(RS, MD, MB, MI, MS)	_ROTSHIBrm(X86_ROL, RS, MD, MB, MI, MS)
+
+#define ROLWir(IM, RD)			_ROTSHIWir(X86_ROL, IM, RD)
+#define ROLWim(IM, MD, MB, MI, MS)	_ROTSHIWim(X86_ROL, IM, MD, MB, MI, MS)
+#define ROLWrr(RS, RD)			_ROTSHIWrr(X86_ROL, RS, RD)
+#define ROLWrm(RS, MD, MB, MI, MS)	_ROTSHIWrm(X86_ROL, RS, MD, MB, MI, MS)
+
+#define ROLLir(IM, RD)			_ROTSHILir(X86_ROL, IM, RD)
+#define ROLLim(IM, MD, MB, MI, MS)	_ROTSHILim(X86_ROL, IM, MD, MB, MI, MS)
+#define ROLLrr(RS, RD)			_ROTSHILrr(X86_ROL, RS, RD)
+#define ROLLrm(RS, MD, MB, MI, MS)	_ROTSHILrm(X86_ROL, RS, MD, MB, MI, MS)
+
+#define ROLQir(IM, RD)			_ROTSHIQir(X86_ROL, IM, RD)
+#define ROLQim(IM, MD, MB, MI, MS)	_ROTSHIQim(X86_ROL, IM, MD, MB, MI, MS)
+#define ROLQrr(RS, RD)			_ROTSHIQrr(X86_ROL, RS, RD)
+#define ROLQrm(RS, MD, MB, MI, MS)	_ROTSHIQrm(X86_ROL, RS, MD, MB, MI, MS)
+
+#define RORBir(IM, RD)			_ROTSHIBir(X86_ROR, IM, RD)
+#define RORBim(IM, MD, MB, MI, MS)	_ROTSHIBim(X86_ROR, IM, MD, MB, MI, MS)
+#define RORBrr(RS, RD)			_ROTSHIBrr(X86_ROR, RS, RD)
+#define RORBrm(RS, MD, MB, MI, MS)	_ROTSHIBrm(X86_ROR, RS, MD, MB, MI, MS)
+
+#define RORWir(IM, RD)			_ROTSHIWir(X86_ROR, IM, RD)
+#define RORWim(IM, MD, MB, MI, MS)	_ROTSHIWim(X86_ROR, IM, MD, MB, MI, MS)
+#define RORWrr(RS, RD)			_ROTSHIWrr(X86_ROR, RS, RD)
+#define RORWrm(RS, MD, MB, MI, MS)	_ROTSHIWrm(X86_ROR, RS, MD, MB, MI, MS)
+
+#define RORLir(IM, RD)			_ROTSHILir(X86_ROR, IM, RD)
+#define RORLim(IM, MD, MB, MI, MS)	_ROTSHILim(X86_ROR, IM, MD, MB, MI, MS)
+#define RORLrr(RS, RD)			_ROTSHILrr(X86_ROR, RS, RD)
+#define RORLrm(RS, MD, MB, MI, MS)	_ROTSHILrm(X86_ROR, RS, MD, MB, MI, MS)
+
+#define RORQir(IM, RD)			_ROTSHIQir(X86_ROR, IM, RD)
+#define RORQim(IM, MD, MB, MI, MS)	_ROTSHIQim(X86_ROR, IM, MD, MB, MI, MS)
+#define RORQrr(RS, RD)			_ROTSHIQrr(X86_ROR, RS, RD)
+#define RORQrm(RS, MD, MB, MI, MS)	_ROTSHIQrm(X86_ROR, RS, MD, MB, MI, MS)
+
+#define RCLBir(IM, RD)			_ROTSHIBir(X86_RCL, IM, RD)
+#define RCLBim(IM, MD, MB, MI, MS)	_ROTSHIBim(X86_RCL, IM, MD, MB, MI, MS)
+#define RCLBrr(RS, RD)			_ROTSHIBrr(X86_RCL, RS, RD)
+#define RCLBrm(RS, MD, MB, MI, MS)	_ROTSHIBrm(X86_RCL, RS, MD, MB, MI, MS)
+
+#define RCLWir(IM, RD)			_ROTSHIWir(X86_RCL, IM, RD)
+#define RCLWim(IM, MD, MB, MI, MS)	_ROTSHIWim(X86_RCL, IM, MD, MB, MI, MS)
+#define RCLWrr(RS, RD)			_ROTSHIWrr(X86_RCL, RS, RD)
+#define RCLWrm(RS, MD, MB, MI, MS)	_ROTSHIWrm(X86_RCL, RS, MD, MB, MI, MS)
+
+#define RCLLir(IM, RD)			_ROTSHILir(X86_RCL, IM, RD)
+#define RCLLim(IM, MD, MB, MI, MS)	_ROTSHILim(X86_RCL, IM, MD, MB, MI, MS)
+#define RCLLrr(RS, RD)			_ROTSHILrr(X86_RCL, RS, RD)
+#define RCLLrm(RS, MD, MB, MI, MS)	_ROTSHILrm(X86_RCL, RS, MD, MB, MI, MS)
+
+#define RCLQir(IM, RD)			_ROTSHIQir(X86_RCL, IM, RD)
+#define RCLQim(IM, MD, MB, MI, MS)	_ROTSHIQim(X86_RCL, IM, MD, MB, MI, MS)
+#define RCLQrr(RS, RD)			_ROTSHIQrr(X86_RCL, RS, RD)
+#define RCLQrm(RS, MD, MB, MI, MS)	_ROTSHIQrm(X86_RCL, RS, MD, MB, MI, MS)
+
+#define RCRBir(IM, RD)			_ROTSHIBir(X86_RCR, IM, RD)
+#define RCRBim(IM, MD, MB, MI, MS)	_ROTSHIBim(X86_RCR, IM, MD, MB, MI, MS)
+#define RCRBrr(RS, RD)			_ROTSHIBrr(X86_RCR, RS, RD)
+#define RCRBrm(RS, MD, MB, MI, MS)	_ROTSHIBrm(X86_RCR, RS, MD, MB, MI, MS)
+
+#define RCRWir(IM, RD)			_ROTSHIWir(X86_RCR, IM, RD)
+#define RCRWim(IM, MD, MB, MI, MS)	_ROTSHIWim(X86_RCR, IM, MD, MB, MI, MS)
+#define RCRWrr(RS, RD)			_ROTSHIWrr(X86_RCR, RS, RD)
+#define RCRWrm(RS, MD, MB, MI, MS)	_ROTSHIWrm(X86_RCR, RS, MD, MB, MI, MS)
+
+#define RCRLir(IM, RD)			_ROTSHILir(X86_RCR, IM, RD)
+#define RCRLim(IM, MD, MB, MI, MS)	_ROTSHILim(X86_RCR, IM, MD, MB, MI, MS)
+#define RCRLrr(RS, RD)			_ROTSHILrr(X86_RCR, RS, RD)
+#define RCRLrm(RS, MD, MB, MI, MS)	_ROTSHILrm(X86_RCR, RS, MD, MB, MI, MS)
+
+#define RCRQir(IM, RD)			_ROTSHIQir(X86_RCR, IM, RD)
+#define RCRQim(IM, MD, MB, MI, MS)	_ROTSHIQim(X86_RCR, IM, MD, MB, MI, MS)
+#define RCRQrr(RS, RD)			_ROTSHIQrr(X86_RCR, RS, RD)
+#define RCRQrm(RS, MD, MB, MI, MS)	_ROTSHIQrm(X86_RCR, RS, MD, MB, MI, MS)
+
+#define SHLBir(IM, RD)			_ROTSHIBir(X86_SHL, IM, RD)
+#define SHLBim(IM, MD, MB, MI, MS)	_ROTSHIBim(X86_SHL, IM, MD, MB, MI, MS)
+#define SHLBrr(RS, RD)			_ROTSHIBrr(X86_SHL, RS, RD)
+#define SHLBrm(RS, MD, MB, MI, MS)	_ROTSHIBrm(X86_SHL, RS, MD, MB, MI, MS)
+
+#define SHLWir(IM, RD)			_ROTSHIWir(X86_SHL, IM, RD)
+#define SHLWim(IM, MD, MB, MI, MS)	_ROTSHIWim(X86_SHL, IM, MD, MB, MI, MS)
+#define SHLWrr(RS, RD)			_ROTSHIWrr(X86_SHL, RS, RD)
+#define SHLWrm(RS, MD, MB, MI, MS)	_ROTSHIWrm(X86_SHL, RS, MD, MB, MI, MS)
+
+#define SHLLir(IM, RD)			_ROTSHILir(X86_SHL, IM, RD)
+#define SHLLim(IM, MD, MB, MI, MS)	_ROTSHILim(X86_SHL, IM, MD, MB, MI, MS)
+#define SHLLrr(RS, RD)			_ROTSHILrr(X86_SHL, RS, RD)
+#define SHLLrm(RS, MD, MB, MI, MS)	_ROTSHILrm(X86_SHL, RS, MD, MB, MI, MS)
+
+#define SHLQir(IM, RD)			_ROTSHIQir(X86_SHL, IM, RD)
+#define SHLQim(IM, MD, MB, MI, MS)	_ROTSHIQim(X86_SHL, IM, MD, MB, MI, MS)
+#define SHLQrr(RS, RD)			_ROTSHIQrr(X86_SHL, RS, RD)
+#define SHLQrm(RS, MD, MB, MI, MS)	_ROTSHIQrm(X86_SHL, RS, MD, MB, MI, MS)
+
+#define SHRBir(IM, RD)			_ROTSHIBir(X86_SHR, IM, RD)
+#define SHRBim(IM, MD, MB, MI, MS)	_ROTSHIBim(X86_SHR, IM, MD, MB, MI, MS)
+#define SHRBrr(RS, RD)			_ROTSHIBrr(X86_SHR, RS, RD)
+#define SHRBrm(RS, MD, MB, MI, MS)	_ROTSHIBrm(X86_SHR, RS, MD, MB, MI, MS)
+
+#define SHRWir(IM, RD)			_ROTSHIWir(X86_SHR, IM, RD)
+#define SHRWim(IM, MD, MB, MI, MS)	_ROTSHIWim(X86_SHR, IM, MD, MB, MI, MS)
+#define SHRWrr(RS, RD)			_ROTSHIWrr(X86_SHR, RS, RD)
+#define SHRWrm(RS, MD, MB, MI, MS)	_ROTSHIWrm(X86_SHR, RS, MD, MB, MI, MS)
+
+#define SHRLir(IM, RD)			_ROTSHILir(X86_SHR, IM, RD)
+#define SHRLim(IM, MD, MB, MI, MS)	_ROTSHILim(X86_SHR, IM, MD, MB, MI, MS)
+#define SHRLrr(RS, RD)			_ROTSHILrr(X86_SHR, RS, RD)
+#define SHRLrm(RS, MD, MB, MI, MS)	_ROTSHILrm(X86_SHR, RS, MD, MB, MI, MS)
+
+#define SHRQir(IM, RD)			_ROTSHIQir(X86_SHR, IM, RD)
+#define SHRQim(IM, MD, MB, MI, MS)	_ROTSHIQim(X86_SHR, IM, MD, MB, MI, MS)
+#define SHRQrr(RS, RD)			_ROTSHIQrr(X86_SHR, RS, RD)
+#define SHRQrm(RS, MD, MB, MI, MS)	_ROTSHIQrm(X86_SHR, RS, MD, MB, MI, MS)
+
+#define SALBir				SHLBir
+#define SALBim				SHLBim
+#define SALBrr				SHLBrr
+#define SALBrm				SHLBrm
+
+#define SALWir				SHLWir
+#define SALWim				SHLWim
+#define SALWrr				SHLWrr
+#define SALWrm				SHLWrm
+
+#define SALLir				SHLLir
+#define SALLim				SHLLim
+#define SALLrr				SHLLrr
+#define SALLrm				SHLLrm
+
+#define SALQir				SHLQir
+#define SALQim				SHLQim
+#define SALQrr				SHLQrr
+#define SALQrm				SHLQrm
+
+#define SARBir(IM, RD)			_ROTSHIBir(X86_SAR, IM, RD)
+#define SARBim(IM, MD, MB, MI, MS)	_ROTSHIBim(X86_SAR, IM, MD, MB, MI, MS)
+#define SARBrr(RS, RD)			_ROTSHIBrr(X86_SAR, RS, RD)
+#define SARBrm(RS, MD, MB, MI, MS)	_ROTSHIBrm(X86_SAR, RS, MD, MB, MI, MS)
+
+#define SARWir(IM, RD)			_ROTSHIWir(X86_SAR, IM, RD)
+#define SARWim(IM, MD, MB, MI, MS)	_ROTSHIWim(X86_SAR, IM, MD, MB, MI, MS)
+#define SARWrr(RS, RD)			_ROTSHIWrr(X86_SAR, RS, RD)
+#define SARWrm(RS, MD, MB, MI, MS)	_ROTSHIWrm(X86_SAR, RS, MD, MB, MI, MS)
+
+#define SARLir(IM, RD)			_ROTSHILir(X86_SAR, IM, RD)
+#define SARLim(IM, MD, MB, MI, MS)	_ROTSHILim(X86_SAR, IM, MD, MB, MI, MS)
+#define SARLrr(RS, RD)			_ROTSHILrr(X86_SAR, RS, RD)
+#define SARLrm(RS, MD, MB, MI, MS)	_ROTSHILrm(X86_SAR, RS, MD, MB, MI, MS)
+
+#define SARQir(IM, RD)			_ROTSHIQir(X86_SAR, IM, RD)
+#define SARQim(IM, MD, MB, MI, MS)	_ROTSHIQim(X86_SAR, IM, MD, MB, MI, MS)
+#define SARQrr(RS, RD)			_ROTSHIQrr(X86_SAR, RS, RD)
+#define SARQrm(RS, MD, MB, MI, MS)	_ROTSHIQrm(X86_SAR, RS, MD, MB, MI, MS)
+
+
+/* --- Bit test instructions ----------------------------------------------- */
+
+enum {
+  X86_BT  = 4,
+  X86_BTS = 5,
+  X86_BTR = 6,
+  X86_BTC = 7,
+};
+
+/*									_format		Opcd		 ,Mod ,r      ,m	,mem=dsp+sib	,imm... */
+
+#define _BTWir(OP, IM, RD)		(_d16(), _REXLrr(0, RD),	_OO_Mrm_B	(0x0fba		 ,_b11,OP     ,_r2(RD)			,_u8(IM)))
+#define _BTWim(OP, IM, MD, MB, MI, MS)	(_d16(), _REXLrm(0, MB, MI),	_OO_r_X_B	(0x0fba		      ,OP		,MD,MB,MI,MS	,_u8(IM)))
+#define _BTWrr(OP, RS, RD)		(_d16(), _REXLrr(RS, RD),	_OO_Mrm		(0x0f83|((OP)<<3),_b11,_r2(RS),_r2(RD)				))
+#define _BTWrm(OP, RS, MD, MB, MI, MS)	(_d16(), _REXLrm(RS, MB, MI),	_OO_r_X		(0x0f83|((OP)<<3)     ,_r2(RS)		,MD,MB,MI,MS		))
+
+#define _BTLir(OP, IM, RD)		(_REXLrr(0, RD),		_OO_Mrm_B	(0x0fba		 ,_b11,OP     ,_r4(RD)			,_u8(IM)))
+#define _BTLim(OP, IM, MD, MB, MI, MS)	(_REXLrm(0, MB, MI),		_OO_r_X_B	(0x0fba		      ,OP		,MD,MB,MI,MS	,_u8(IM)))
+#define _BTLrr(OP, RS, RD)		(_REXLrr(RS, RD),		_OO_Mrm		(0x0f83|((OP)<<3),_b11,_r4(RS),_r4(RD)				))
+#define _BTLrm(OP, RS, MD, MB, MI, MS)	(_REXLrm(RS, MB, MI),		_OO_r_X		(0x0f83|((OP)<<3)     ,_r4(RS)		,MD,MB,MI,MS		))
+
+#define _BTQir(OP, IM, RD)		(_REXQrr(0, RD),		_OO_Mrm_B	(0x0fba		 ,_b11,OP     ,_r8(RD)			,_u8(IM)))
+#define _BTQim(OP, IM, MD, MB, MI, MS)	(_REXQrm(0, MB, MI),		_OO_r_X_B	(0x0fba		      ,OP		,MD,MB,MI,MS	,_u8(IM)))
+#define _BTQrr(OP, RS, RD)		(_REXQrr(RS, RD),		_OO_Mrm		(0x0f83|((OP)<<3),_b11,_r8(RS),_r8(RD)				))
+#define _BTQrm(OP, RS, MD, MB, MI, MS)	(_REXQrm(RS, MB, MI),		_OO_r_X		(0x0f83|((OP)<<3)     ,_r8(RS)		,MD,MB,MI,MS		))
+
+#define BTWir(IM, RD)			_BTWir(X86_BT, IM, RD)
+#define BTWim(IM, MD, MB, MI, MS)	_BTWim(X86_BT, IM, MD, MB, MI, MS)
+#define BTWrr(RS, RD)			_BTWrr(X86_BT, RS, RD)
+#define BTWrm(RS, MD, MB, MI, MS)	_BTWrm(X86_BT, RS, MD, MB, MI, MS)
+
+#define BTLir(IM, RD)			_BTLir(X86_BT, IM, RD)
+#define BTLim(IM, MD, MB, MI, MS)	_BTLim(X86_BT, IM, MD, MB, MI, MS)
+#define BTLrr(RS, RD)			_BTLrr(X86_BT, RS, RD)
+#define BTLrm(RS, MD, MB, MI, MS)	_BTLrm(X86_BT, RS, MD, MB, MI, MS)
+
+#define BTQir(IM, RD)			_BTQir(X86_BT, IM, RD)
+#define BTQim(IM, MD, MB, MI, MS)	_BTQim(X86_BT, IM, MD, MB, MI, MS)
+#define BTQrr(RS, RD)			_BTQrr(X86_BT, RS, RD)
+#define BTQrm(RS, MD, MB, MI, MS)	_BTQrm(X86_BT, RS, MD, MB, MI, MS)
+
+#define BTCWir(IM, RD)			_BTWir(X86_BTC, IM, RD)
+#define BTCWim(IM, MD, MB, MI, MS)	_BTWim(X86_BTC, IM, MD, MB, MI, MS)
+#define BTCWrr(RS, RD)			_BTWrr(X86_BTC, RS, RD)
+#define BTCWrm(RS, MD, MB, MI, MS)	_BTWrm(X86_BTC, RS, MD, MB, MI, MS)
+
+#define BTCLir(IM, RD)			_BTLir(X86_BTC, IM, RD)
+#define BTCLim(IM, MD, MB, MI, MS)	_BTLim(X86_BTC, IM, MD, MB, MI, MS)
+#define BTCLrr(RS, RD)			_BTLrr(X86_BTC, RS, RD)
+#define BTCLrm(RS, MD, MB, MI, MS)	_BTLrm(X86_BTC, RS, MD, MB, MI, MS)
+
+#define BTCQir(IM, RD)			_BTQir(X86_BTC, IM, RD)
+#define BTCQim(IM, MD, MB, MI, MS)	_BTQim(X86_BTC, IM, MD, MB, MI, MS)
+#define BTCQrr(RS, RD)			_BTQrr(X86_BTC, RS, RD)
+#define BTCQrm(RS, MD, MB, MI, MS)	_BTQrm(X86_BTC, RS, MD, MB, MI, MS)
+
+#define BTRWir(IM, RD)			_BTWir(X86_BTR, IM, RD)
+#define BTRWim(IM, MD, MB, MI, MS)	_BTWim(X86_BTR, IM, MD, MB, MI, MS)
+#define BTRWrr(RS, RD)			_BTWrr(X86_BTR, RS, RD)
+#define BTRWrm(RS, MD, MB, MI, MS)	_BTWrm(X86_BTR, RS, MD, MB, MI, MS)
+
+#define BTRLir(IM, RD)			_BTLir(X86_BTR, IM, RD)
+#define BTRLim(IM, MD, MB, MI, MS)	_BTLim(X86_BTR, IM, MD, MB, MI, MS)
+#define BTRLrr(RS, RD)			_BTLrr(X86_BTR, RS, RD)
+#define BTRLrm(RS, MD, MB, MI, MS)	_BTLrm(X86_BTR, RS, MD, MB, MI, MS)
+
+#define BTRQir(IM, RD)			_BTQir(X86_BTR, IM, RD)
+#define BTRQim(IM, MD, MB, MI, MS)	_BTQim(X86_BTR, IM, MD, MB, MI, MS)
+#define BTRQrr(RS, RD)			_BTQrr(X86_BTR, RS, RD)
+#define BTRQrm(RS, MD, MB, MI, MS)	_BTQrm(X86_BTR, RS, MD, MB, MI, MS)
+
+#define BTSWir(IM, RD)			_BTWir(X86_BTS, IM, RD)
+#define BTSWim(IM, MD, MB, MI, MS)	_BTWim(X86_BTS, IM, MD, MB, MI, MS)
+#define BTSWrr(RS, RD)			_BTWrr(X86_BTS, RS, RD)
+#define BTSWrm(RS, MD, MB, MI, MS)	_BTWrm(X86_BTS, RS, MD, MB, MI, MS)
+
+#define BTSLir(IM, RD)			_BTLir(X86_BTS, IM, RD)
+#define BTSLim(IM, MD, MB, MI, MS)	_BTLim(X86_BTS, IM, MD, MB, MI, MS)
+#define BTSLrr(RS, RD)			_BTLrr(X86_BTS, RS, RD)
+#define BTSLrm(RS, MD, MB, MI, MS)	_BTLrm(X86_BTS, RS, MD, MB, MI, MS)
+
+#define BTSQir(IM, RD)			_BTQir(X86_BTS, IM, RD)
+#define BTSQim(IM, MD, MB, MI, MS)	_BTQim(X86_BTS, IM, MD, MB, MI, MS)
+#define BTSQrr(RS, RD)			_BTQrr(X86_BTS, RS, RD)
+#define BTSQrm(RS, MD, MB, MI, MS)	_BTQrm(X86_BTS, RS, MD, MB, MI, MS)
+
+
+/* --- Move instructions --------------------------------------------------- */
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+
+#define MOVBrr(RS, RD)			(_REXBrr(RS, RD),		_O_Mrm		(0x88		,_b11,_r1(RS),_r1(RD)				))
+#define MOVBmr(MD, MB, MI, MS, RD)	(_REXBmr(MB, MI, RD),		_O_r_X		(0x8a		     ,_r1(RD)		,MD,MB,MI,MS		))
+#define MOVBrm(RS, MD, MB, MI, MS)	(_REXBrm(RS, MB, MI),		_O_r_X		(0x88		     ,_r1(RS)		,MD,MB,MI,MS		))
+#define MOVBir(IM,  R)			(_REXBrr(0, R),			_Or_B		(0xb0,_r1(R)						,_su8(IM)))
+#define MOVBim(IM, MD, MB, MI, MS)	(_REXBrm(0, MB, MI),		_O_X_B		(0xc6					,MD,MB,MI,MS	,_su8(IM)))
+
+#define MOVWrr(RS, RD)			(_d16(), _REXLrr(RS, RD),	_O_Mrm		(0x89		,_b11,_r2(RS),_r2(RD)				))
+#define MOVWmr(MD, MB, MI, MS, RD)	(_d16(), _REXLmr(MB, MI, RD),	_O_r_X		(0x8b		     ,_r2(RD)		,MD,MB,MI,MS		))
+#define MOVWrm(RS, MD, MB, MI, MS)	(_d16(), _REXLrm(RS, MB, MI),	_O_r_X		(0x89		     ,_r2(RS)		,MD,MB,MI,MS		))
+#define MOVWir(IM,  R)			(_d16(), _REXLrr(0, R),		_Or_W		(0xb8,_r2(R)						,_su16(IM)))
+#define MOVWim(IM, MD, MB, MI, MS)	(_d16(), _REXLrm(0, MB, MI),	_O_X_W		(0xc7					,MD,MB,MI,MS	,_su16(IM)))
+
+#define MOVLrr(RS, RD)			(_REXLrr(RS, RD),		_O_Mrm		(0x89		,_b11,_r4(RS),_r4(RD)				))
+#define MOVLmr(MD, MB, MI, MS, RD)	(_REXLmr(MB, MI, RD),		_O_r_X		(0x8b		     ,_r4(RD)		,MD,MB,MI,MS		))
+#define MOVLrm(RS, MD, MB, MI, MS)	(_REXLrm(RS, MB, MI),		_O_r_X		(0x89		     ,_r4(RS)		,MD,MB,MI,MS		))
+#define MOVLir(IM,  R)			(_REXLrr(0, R),			_Or_L		(0xb8,_r4(R)						,IM	))
+#define MOVLim(IM, MD, MB, MI, MS)	(_REXLrm(0, MB, MI),		_O_X_L		(0xc7					,MD,MB,MI,MS	,IM	))
+
+#define MOVQrr(RS, RD)			(_REXQrr(RS, RD),		_O_Mrm		(0x89		,_b11,_r8(RS),_r8(RD)				))
+#define MOVQmr(MD, MB, MI, MS, RD)	(_REXQmr(MB, MI, RD),		_O_r_X		(0x8b		     ,_r8(RD)		,MD,MB,MI,MS		))
+#define MOVQrm(RS, MD, MB, MI, MS)	(_REXQrm(RS, MB, MI),		_O_r_X		(0x89		     ,_r8(RS)		,MD,MB,MI,MS		))
+#define MOVQir(IM,  R)			(_REXQrr(0, R),			_Or_Q		(0xb8,_r8(R)						,IM	))
+#define MOVQim(IM, MD, MB, MI, MS)	(_REXQrm(0, MB, MI),		_O_X_L		(0xc7					,MD,MB,MI,MS	,IM	))
+
+
+/* --- Unary and Multiply/Divide instructions ------------------------------ */
+
+enum {
+  X86_NOT  = 2,
+  X86_NEG  = 3,
+  X86_MUL  = 4,
+  X86_IMUL = 5,
+  X86_DIV  = 6,
+  X86_IDIV = 7,
+};
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+
+#define _UNARYBr(OP, RS)		(_REXBrr(0, RS),		_O_Mrm		(0xf6		,_b11,OP    ,_r1(RS)				))
+#define _UNARYBm(OP, MD, MB, MI, MS)	(_REXBrm(0, MB, MI),		_O_r_X		(0xf6		     ,OP		,MD,MB,MI,MS		))
+#define _UNARYWr(OP, RS)		(_d16(), _REXLrr(0, RS),	_O_Mrm		(0xf7		,_b11,OP    ,_r2(RS)				))
+#define _UNARYWm(OP, MD, MB, MI, MS)	(_d16(), _REXLmr(MB, MI, 0),	_O_r_X		(0xf7		     ,OP		,MD,MB,MI,MS		))
+#define _UNARYLr(OP, RS)		(_REXLrr(0, RS),		_O_Mrm		(0xf7		,_b11,OP    ,_r4(RS)				))
+#define _UNARYLm(OP, MD, MB, MI, MS)	(_REXLmr(MB, MI, 0),		_O_r_X		(0xf7		     ,OP		,MD,MB,MI,MS		))
+#define _UNARYQr(OP, RS)		(_REXQrr(0, RS),		_O_Mrm		(0xf7		,_b11,OP    ,_r8(RS)				))
+#define _UNARYQm(OP, MD, MB, MI, MS)	(_REXQmr(MB, MI, 0),		_O_r_X		(0xf7		     ,OP		,MD,MB,MI,MS		))
+
+#define NOTBr(RS)			_UNARYBr(X86_NOT, RS)
+#define NOTBm(MD, MB, MI, MS)		_UNARYBm(X86_NOT, MD, MB, MI, MS)
+#define NOTWr(RS)			_UNARYWr(X86_NOT, RS)
+#define NOTWm(MD, MB, MI, MS)		_UNARYWm(X86_NOT, MD, MB, MI, MS)
+#define NOTLr(RS)			_UNARYLr(X86_NOT, RS)
+#define NOTLm(MD, MB, MI, MS)		_UNARYLm(X86_NOT, MD, MB, MI, MS)
+#define NOTQr(RS)			_UNARYQr(X86_NOT, RS)
+#define NOTQm(MD, MB, MI, MS)		_UNARYQm(X86_NOT, MD, MB, MI, MS)
+
+#define NEGBr(RS)			_UNARYBr(X86_NEG, RS)
+#define NEGBm(MD, MB, MI, MS)		_UNARYBm(X86_NEG, MD, MB, MI, MS)
+#define NEGWr(RS)			_UNARYWr(X86_NEG, RS)
+#define NEGWm(MD, MB, MI, MS)		_UNARYWm(X86_NEG, MD, MB, MI, MS)
+#define NEGLr(RS)			_UNARYLr(X86_NEG, RS)
+#define NEGLm(MD, MB, MI, MS)		_UNARYLm(X86_NEG, MD, MB, MI, MS)
+#define NEGQr(RS)			_UNARYQr(X86_NEG, RS)
+#define NEGQm(MD, MB, MI, MS)		_UNARYQm(X86_NEG, MD, MB, MI, MS)
+
+#define MULBr(RS)			_UNARYBr(X86_MUL, RS)
+#define MULBm(MD, MB, MI, MS)		_UNARYBm(X86_MUL, MD, MB, MI, MS)
+#define MULWr(RS)			_UNARYWr(X86_MUL, RS)
+#define MULWm(MD, MB, MI, MS)		_UNARYWm(X86_MUL, MD, MB, MI, MS)
+#define MULLr(RS)			_UNARYLr(X86_MUL, RS)
+#define MULLm(MD, MB, MI, MS)		_UNARYLm(X86_MUL, MD, MB, MI, MS)
+#define MULQr(RS)			_UNARYQr(X86_MUL, RS)
+#define MULQm(MD, MB, MI, MS)		_UNARYQm(X86_MUL, MD, MB, MI, MS)
+
+#define IMULBr(RS)			_UNARYBr(X86_IMUL, RS)
+#define IMULBm(MD, MB, MI, MS)		_UNARYBm(X86_IMUL, MD, MB, MI, MS)
+#define IMULWr(RS)			_UNARYWr(X86_IMUL, RS)
+#define IMULWm(MD, MB, MI, MS)		_UNARYWm(X86_IMUL, MD, MB, MI, MS)
+#define IMULLr(RS)			_UNARYLr(X86_IMUL, RS)
+#define IMULLm(MD, MB, MI, MS)		_UNARYLm(X86_IMUL, MD, MB, MI, MS)
+#define IMULQr(RS)			_UNARYQr(X86_IMUL, RS)
+#define IMULQm(MD, MB, MI, MS)		_UNARYQm(X86_IMUL, MD, MB, MI, MS)
+
+#define DIVBr(RS)			_UNARYBr(X86_DIV, RS)
+#define DIVBm(MD, MB, MI, MS)		_UNARYBm(X86_DIV, MD, MB, MI, MS)
+#define DIVWr(RS)			_UNARYWr(X86_DIV, RS)
+#define DIVWm(MD, MB, MI, MS)		_UNARYWm(X86_DIV, MD, MB, MI, MS)
+#define DIVLr(RS)			_UNARYLr(X86_DIV, RS)
+#define DIVLm(MD, MB, MI, MS)		_UNARYLm(X86_DIV, MD, MB, MI, MS)
+#define DIVQr(RS)			_UNARYQr(X86_DIV, RS)
+#define DIVQm(MD, MB, MI, MS)		_UNARYQm(X86_DIV, MD, MB, MI, MS)
+
+#define IDIVBr(RS)			_UNARYBr(X86_IDIV, RS)
+#define IDIVBm(MD, MB, MI, MS)		_UNARYBm(X86_IDIV, MD, MB, MI, MS)
+#define IDIVWr(RS)			_UNARYWr(X86_IDIV, RS)
+#define IDIVWm(MD, MB, MI, MS)		_UNARYWm(X86_IDIV, MD, MB, MI, MS)
+#define IDIVLr(RS)			_UNARYLr(X86_IDIV, RS)
+#define IDIVLm(MD, MB, MI, MS)		_UNARYLm(X86_IDIV, MD, MB, MI, MS)
+#define IDIVQr(RS)			_UNARYQr(X86_IDIV, RS)
+#define IDIVQm(MD, MB, MI, MS)		_UNARYQm(X86_IDIV, MD, MB, MI, MS)
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+
+#define IMULWrr(RS, RD)			(_d16(), _REXLrr(RD, RS),	_OO_Mrm		(0x0faf		,_b11,_r2(RD),_r2(RS)				))
+#define IMULWmr(MD, MB, MI, MS, RD)	(_d16(), _REXLmr(MB, MI, RD),	_OO_r_X		(0x0faf		     ,_r2(RD)		,MD,MB,MI,MS		))
+
+#define IMULWirr(IM,RS,RD)		(_d16(), _REXLrr(RS, RD),	_Os_Mrm_sW	(0x69		,_b11,_r2(RS),_r2(RD)			,_su16(IM)	))
+#define IMULWimr(IM,MD,MB,MI,MS,RD)	(_d16(), _REXLmr(MB, MI, RD),	_Os_r_X_sW	(0x69		     ,_r2(RD)		,MD,MB,MI,MS	,_su16(IM)	))
+
+#define IMULLir(IM, RD)			(_REXLrr(0, RD),		_Os_Mrm_sL	(0x69		,_b11,_r4(RD),_r4(RD)			,IM	))
+#define IMULLrr(RS, RD)			(_REXLrr(RD, RS),		_OO_Mrm		(0x0faf		,_b11,_r4(RD),_r4(RS)				))
+#define IMULLmr(MD, MB, MI, MS, RD)	(_REXLmr(MB, MI, RD),		_OO_r_X		(0x0faf		     ,_r4(RD)		,MD,MB,MI,MS		))
+
+#define IMULQir(IM, RD)			(_REXQrr(0, RD),		_Os_Mrm_sL	(0x69		,_b11,_r8(RD),_r8(RD)			,IM	))
+#define IMULQrr(RS, RD)			(_REXQrr(RD, RS),		_OO_Mrm		(0x0faf		,_b11,_r8(RD),_r8(RS)				))
+#define IMULQmr(MD, MB, MI, MS, RD)	(_REXQmr(MB, MI, RD),		_OO_r_X		(0x0faf		     ,_r8(RD)		,MD,MB,MI,MS		))
+
+#define IMULLirr(IM,RS,RD)		(_REXLrr(RS, RD),		_Os_Mrm_sL	(0x69		,_b11,_r4(RS),_r4(RD)			,IM	))
+#define IMULLimr(IM,MD,MB,MI,MS,RD)	(_REXLmr(MB, MI, RD),		_Os_r_X_sL	(0x69		     ,_r4(RD)		,MD,MB,MI,MS	,IM	))
+
+#define IMULQirr(IM,RS,RD)		(_REXQrr(RS, RD),		_Os_Mrm_sL	(0x69		,_b11,_r8(RS),_r8(RD)			,IM	))
+#define IMULQimr(IM,MD,MB,MI,MS,RD)	(_REXQmr(MB, MI, RD),		_Os_r_X_sL	(0x69		     ,_r8(RD)		,MD,MB,MI,MS	,IM	))
+
+
+/* --- Control Flow related instructions ----------------------------------- */
+
+enum {
+  X86_CC_O   = 0x0,
+  X86_CC_NO  = 0x1,
+  X86_CC_NAE = 0x2,
+  X86_CC_B   = 0x2,
+  X86_CC_C   = 0x2,
+  X86_CC_AE  = 0x3,
+  X86_CC_NB  = 0x3,
+  X86_CC_NC  = 0x3,
+  X86_CC_E   = 0x4,
+  X86_CC_Z   = 0x4,
+  X86_CC_NE  = 0x5,
+  X86_CC_NZ  = 0x5,
+  X86_CC_BE  = 0x6,
+  X86_CC_NA  = 0x6,
+  X86_CC_A   = 0x7,
+  X86_CC_NBE = 0x7,
+  X86_CC_S   = 0x8,
+  X86_CC_NS  = 0x9,
+  X86_CC_P   = 0xa,
+  X86_CC_PE  = 0xa,
+  X86_CC_NP  = 0xb,
+  X86_CC_PO  = 0xb,
+  X86_CC_L   = 0xc,
+  X86_CC_NGE = 0xc,
+  X86_CC_GE  = 0xd,
+  X86_CC_NL  = 0xd,
+  X86_CC_LE  = 0xe,
+  X86_CC_NG  = 0xe,
+  X86_CC_G   = 0xf,
+  X86_CC_NLE = 0xf,
+};
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+
+// FIXME: no prefix is availble to encode a 32-bit operand size in 64-bit mode
+#define CALLm(M)							_O_D32		(0xe8					,(int)(M)		)
+#define _CALLLsr(R)			(_REXLrr(0, R),			_O_Mrm		(0xff		,_b11,_b010,_r4(R)				))
+#define _CALLQsr(R)			(_REXLrr(0, R),			_O_Mrm		(0xff		,_b11,_b010,_r8(R)				))
+#define CALLsr(R)			( X86_TARGET_64BIT ? _CALLQsr(R) : _CALLLsr(R))
+#define CALLsm(D,B,I,S)			(_REXLrm(0, B, I),		_O_r_X		(0xff		     ,_b010		,(int)(D),B,I,S		))
+
+// FIXME: no prefix is availble to encode a 32-bit operand size in 64-bit mode
+#define JMPSm(M)							_O_D8		(0xeb					,(int)(M)		)
+#define JMPm(M)								_O_D32		(0xe9					,(int)(M)		)
+#define _JMPLsr(R)			(_REXLrr(0, R),			_O_Mrm		(0xff		,_b11,_b100,_r4(R)				))
+#define _JMPQsr(R)			(_REXLrr(0, R),			_O_Mrm		(0xff		,_b11,_b100,_r8(R)				))
+#define JMPsr(R)			( X86_TARGET_64BIT ? _JMPQsr(R) : _JMPLsr(R))
+#define JMPsm(D,B,I,S)			(_REXLrm(0, B, I),		_O_r_X		(0xff		     ,_b100		,(int)(D),B,I,S		))
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+#define JCCSii(CC, D)							_O_B		(0x70|(CC)				,(_sc)(int)(D)		)
+#define JCCSim(CC, D)							_O_D8		(0x70|(CC)				,(int)(D)		)
+#define JOSm(D)				JCCSim(X86_CC_O,   D)
+#define JNOSm(D)			JCCSim(X86_CC_NO,  D)
+#define JBSm(D)				JCCSim(X86_CC_B,   D)
+#define JNAESm(D)			JCCSim(X86_CC_NAE, D)
+#define JNBSm(D)			JCCSim(X86_CC_NB,  D)
+#define JAESm(D)			JCCSim(X86_CC_AE,  D)
+#define JESm(D)				JCCSim(X86_CC_E,   D)
+#define JZSm(D)				JCCSim(X86_CC_Z,   D)
+#define JNESm(D)			JCCSim(X86_CC_NE,  D)
+#define JNZSm(D)			JCCSim(X86_CC_NZ,  D)
+#define JBESm(D)			JCCSim(X86_CC_BE,  D)
+#define JNASm(D)			JCCSim(X86_CC_NA,  D)
+#define JNBESm(D)			JCCSim(X86_CC_NBE, D)
+#define JASm(D)				JCCSim(X86_CC_A,   D)
+#define JSSm(D)				JCCSim(X86_CC_S,   D)
+#define JNSSm(D)			JCCSim(X86_CC_NS,  D)
+#define JPSm(D)				JCCSim(X86_CC_P,   D)
+#define JPESm(D)			JCCSim(X86_CC_PE,  D)
+#define JNPSm(D)			JCCSim(X86_CC_NP,  D)
+#define JPOSm(D)			JCCSim(X86_CC_PO,  D)
+#define JLSm(D)				JCCSim(X86_CC_L,   D)
+#define JNGESm(D)			JCCSim(X86_CC_NGE, D)
+#define JNLSm(D)			JCCSim(X86_CC_NL,  D)
+#define JGESm(D)			JCCSim(X86_CC_GE,  D)
+#define JLESm(D)			JCCSim(X86_CC_LE,  D)
+#define JNGSm(D)			JCCSim(X86_CC_NG,  D)
+#define JNLESm(D)			JCCSim(X86_CC_NLE, D)
+#define JGSm(D)				JCCSim(X86_CC_G,   D)
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+#define JCCii(CC, D)							_OO_L		(0x0f80|(CC)				,(int)(D)		)
+#define JCCim(CC, D)							_OO_D32		(0x0f80|(CC)				,(int)(D)		)
+#define JOm(D)				JCCim(X86_CC_O,   D)
+#define JNOm(D)				JCCim(X86_CC_NO,  D)
+#define JBm(D)				JCCim(X86_CC_B,   D)
+#define JNAEm(D)			JCCim(X86_CC_NAE, D)
+#define JNBm(D)				JCCim(X86_CC_NB,  D)
+#define JAEm(D)				JCCim(X86_CC_AE,  D)
+#define JEm(D)				JCCim(X86_CC_E,   D)
+#define JZm(D)				JCCim(X86_CC_Z,   D)
+#define JNEm(D)				JCCim(X86_CC_NE,  D)
+#define JNZm(D)				JCCim(X86_CC_NZ,  D)
+#define JBEm(D)				JCCim(X86_CC_BE,  D)
+#define JNAm(D)				JCCim(X86_CC_NA,  D)
+#define JNBEm(D)			JCCim(X86_CC_NBE, D)
+#define JAm(D)				JCCim(X86_CC_A,   D)
+#define JSm(D)				JCCim(X86_CC_S,   D)
+#define JNSm(D)				JCCim(X86_CC_NS,  D)
+#define JPm(D)				JCCim(X86_CC_P,   D)
+#define JPEm(D)				JCCim(X86_CC_PE,  D)
+#define JNPm(D)				JCCim(X86_CC_NP,  D)
+#define JPOm(D)				JCCim(X86_CC_PO,  D)
+#define JLm(D)				JCCim(X86_CC_L,   D)
+#define JNGEm(D)			JCCim(X86_CC_NGE, D)
+#define JNLm(D)				JCCim(X86_CC_NL,  D)
+#define JGEm(D)				JCCim(X86_CC_GE,  D)
+#define JLEm(D)				JCCim(X86_CC_LE,  D)
+#define JNGm(D)				JCCim(X86_CC_NG,  D)
+#define JNLEm(D)			JCCim(X86_CC_NLE, D)
+#define JGm(D)				JCCim(X86_CC_G,   D)
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+#define SETCCir(CC, RD)			(_REXBrr(0, RD),		_OO_Mrm		(0x0f90|(CC)	,_b11,_b000,_r1(RD)				))
+#define SETOr(RD)			SETCCir(X86_CC_O,   RD)
+#define SETNOr(RD)			SETCCir(X86_CC_NO,  RD)
+#define SETBr(RD)			SETCCir(X86_CC_B,   RD)
+#define SETNAEr(RD)			SETCCir(X86_CC_NAE, RD)
+#define SETNBr(RD)			SETCCir(X86_CC_NB,  RD)
+#define SETAEr(RD)			SETCCir(X86_CC_AE,  RD)
+#define SETEr(RD)			SETCCir(X86_CC_E,   RD)
+#define SETZr(RD)			SETCCir(X86_CC_Z,   RD)
+#define SETNEr(RD)			SETCCir(X86_CC_NE,  RD)
+#define SETNZr(RD)			SETCCir(X86_CC_NZ,  RD)
+#define SETBEr(RD)			SETCCir(X86_CC_BE,  RD)
+#define SETNAr(RD)			SETCCir(X86_CC_NA,  RD)
+#define SETNBEr(RD)			SETCCir(X86_CC_NBE, RD)
+#define SETAr(RD)			SETCCir(X86_CC_A,   RD)
+#define SETSr(RD)			SETCCir(X86_CC_S,   RD)
+#define SETNSr(RD)			SETCCir(X86_CC_NS,  RD)
+#define SETPr(RD)			SETCCir(X86_CC_P,   RD)
+#define SETPEr(RD)			SETCCir(X86_CC_PE,  RD)
+#define SETNPr(RD)			SETCCir(X86_CC_NP,  RD)
+#define SETPOr(RD)			SETCCir(X86_CC_PO,  RD)
+#define SETLr(RD)			SETCCir(X86_CC_L,   RD)
+#define SETNGEr(RD)			SETCCir(X86_CC_NGE, RD)
+#define SETNLr(RD)			SETCCir(X86_CC_NL,  RD)
+#define SETGEr(RD)			SETCCir(X86_CC_GE,  RD)
+#define SETLEr(RD)			SETCCir(X86_CC_LE,  RD)
+#define SETNGr(RD)			SETCCir(X86_CC_NG,  RD)
+#define SETNLEr(RD)			SETCCir(X86_CC_NLE, RD)
+#define SETGr(RD)			SETCCir(X86_CC_G,   RD)
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+#define SETCCim(CC,MD,MB,MI,MS)		(_REXBrm(0, MB, MI),		_OO_r_X		(0x0f90|(CC)	     ,_b000		,MD,MB,MI,MS		))
+#define SETOm(D, B, I, S)		SETCCim(X86_CC_O,   D, B, I, S)
+#define SETNOm(D, B, I, S)		SETCCim(X86_CC_NO,  D, B, I, S)
+#define SETBm(D, B, I, S)		SETCCim(X86_CC_B,   D, B, I, S)
+#define SETNAEm(D, B, I, S)		SETCCim(X86_CC_NAE, D, B, I, S)
+#define SETNBm(D, B, I, S)		SETCCim(X86_CC_NB,  D, B, I, S)
+#define SETAEm(D, B, I, S)		SETCCim(X86_CC_AE,  D, B, I, S)
+#define SETEm(D, B, I, S)		SETCCim(X86_CC_E,   D, B, I, S)
+#define SETZm(D, B, I, S)		SETCCim(X86_CC_Z,   D, B, I, S)
+#define SETNEm(D, B, I, S)		SETCCim(X86_CC_NE,  D, B, I, S)
+#define SETNZm(D, B, I, S)		SETCCim(X86_CC_NZ,  D, B, I, S)
+#define SETBEm(D, B, I, S)		SETCCim(X86_CC_BE,  D, B, I, S)
+#define SETNAm(D, B, I, S)		SETCCim(X86_CC_NA,  D, B, I, S)
+#define SETNBEm(D, B, I, S)		SETCCim(X86_CC_NBE, D, B, I, S)
+#define SETAm(D, B, I, S)		SETCCim(X86_CC_A,   D, B, I, S)
+#define SETSm(D, B, I, S)		SETCCim(X86_CC_S,   D, B, I, S)
+#define SETNSm(D, B, I, S)		SETCCim(X86_CC_NS,  D, B, I, S)
+#define SETPm(D, B, I, S)		SETCCim(X86_CC_P,   D, B, I, S)
+#define SETPEm(D, B, I, S)		SETCCim(X86_CC_PE,  D, B, I, S)
+#define SETNPm(D, B, I, S)		SETCCim(X86_CC_NP,  D, B, I, S)
+#define SETPOm(D, B, I, S)		SETCCim(X86_CC_PO,  D, B, I, S)
+#define SETLm(D, B, I, S)		SETCCim(X86_CC_L,   D, B, I, S)
+#define SETNGEm(D, B, I, S)		SETCCim(X86_CC_NGE, D, B, I, S)
+#define SETNLm(D, B, I, S)		SETCCim(X86_CC_NL,  D, B, I, S)
+#define SETGEm(D, B, I, S)		SETCCim(X86_CC_GE,  D, B, I, S)
+#define SETLEm(D, B, I, S)		SETCCim(X86_CC_LE,  D, B, I, S)
+#define SETNGm(D, B, I, S)		SETCCim(X86_CC_NG,  D, B, I, S)
+#define SETNLEm(D, B, I, S)		SETCCim(X86_CC_NLE, D, B, I, S)
+#define SETGm(D, B, I, S)		SETCCim(X86_CC_G,   D, B, I, S)
+
+/*									_format		Opcd		,Mod ,r	     ,m		,mem=dsp+sib	,imm... */
+#define CMOVWrr(CC,RS,RD)		(_d16(), _REXLrr(RD, RS),	_OO_Mrm		(0x0f40|(CC)	,_b11,_r2(RD),_r2(RS)				))
+#define CMOVWmr(CC,MD,MB,MI,MS,RD)	(_d16(), _REXLmr(MB, MI, RD),	_OO_r_X		(0x0f40|(CC)	     ,_r2(RD)		,MD,MB,MI,MS		))
+#define CMOVLrr(CC,RS,RD)		(_REXLrr(RD, RS),		_OO_Mrm		(0x0f40|(CC)	,_b11,_r4(RD),_r4(RS)				))
+#define CMOVLmr(CC,MD,MB,MI,MS,RD)	(_REXLmr(MB, MI, RD),		_OO_r_X		(0x0f40|(CC)	     ,_r4(RD)		,MD,MB,MI,MS		))
+#define CMOVQrr(CC,RS,RD)		(_REXQrr(RD, RS),		_OO_Mrm		(0x0f40|(CC)	,_b11,_r8(RD),_r8(RS)				))
+#define CMOVQmr(CC,MD,MB,MI,MS,RD)	(_REXQmr(MB, MI, RD),		_OO_r_X		(0x0f40|(CC)	     ,_r8(RD)		,MD,MB,MI,MS		))
+
+
+/* --- Push/Pop instructions ----------------------------------------------- */
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+
+#define POPWr(RD)			_m32only((_d16(),		_Or		(0x58,_r2(RD)							)))
+#define POPWm(MD, MB, MI, MS)		_m32only((_d16(),		_O_r_X		(0x8f		     ,_b000		,MD,MB,MI,MS		)))
+
+#define POPLr(RD)			_m32only(			_Or		(0x58,_r4(RD)							))
+#define POPLm(MD, MB, MI, MS)		_m32only(			_O_r_X		(0x8f		     ,_b000		,MD,MB,MI,MS		))
+
+#define POPQr(RD)			_m64only((_REXQr(RD),		_Or		(0x58,_r8(RD)							)))
+#define POPQm(MD, MB, MI, MS)		_m64only((_REXQm(MB, MI), 	_O_r_X		(0x8f		     ,_b000		,MD,MB,MI,MS		)))
+
+#define PUSHWr(RS)			_m32only((_d16(),		_Or		(0x50,_r2(RS)							)))
+#define PUSHWm(MD, MB, MI, MS)		_m32only((_d16(),		_O_r_X		(0xff,		     ,_b110		,MD,MB,MI,MS		)))
+#define PUSHWi(IM)			_m32only((_d16(),		_Os_sW		(0x68							,IM	)))
+
+#define PUSHLr(RS)			_m32only(			_Or		(0x50,_r4(RS)							))
+#define PUSHLm(MD, MB, MI, MS)		_m32only(			_O_r_X		(0xff		     ,_b110		,MD,MB,MI,MS		))
+#define PUSHLi(IM)			_m32only(			_Os_sL		(0x68							,IM	))
+
+#define PUSHQr(RS)			_m64only((_REXQr(RS),		_Or		(0x50,_r8(RS)							)))
+#define PUSHQm(MD, MB, MI, MS)		_m64only((_REXQm(MB, MI),	_O_r_X		(0xff		     ,_b110		,MD,MB,MI,MS		)))
+#define PUSHQi(IM)			_m64only(			_Os_sL		(0x68							,IM	))
+
+#define POPA()				(_d16(),			_O		(0x61								))
+#define POPAD()								_O		(0x61								)
+
+#define PUSHA()				(_d16(),			_O		(0x60								))
+#define PUSHAD()							_O		(0x60								)
+
+#define POPF()								_O		(0x9d								)
+#define PUSHF()								_O		(0x9c								)
+
+
+/* --- Test instructions --------------------------------------------------- */
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+
+#define TESTBrr(RS, RD)			(_REXBrr(RS, RD),		_O_Mrm		(0x84		,_b11,_r1(RS),_r1(RD)				))
+#define TESTBrm(RS, MD, MB, MI, MS)	(_REXBrm(RS, MB, MI),		_O_r_X		(0x84		     ,_r1(RS)		,MD,MB,MI,MS		))
+#define TESTBir(IM, RD)			(X86_OPTIMIZE_ALU && ((RD) == X86_AL) ? \
+					(_REXBrr(0, RD),		_O_B		(0xa8							,_u8(IM))) : \
+					(_REXBrr(0, RD),		_O_Mrm_B	(0xf6		,_b11,_b000  ,_r1(RD)			,_u8(IM))) )
+#define TESTBim(IM, MD, MB, MI, MS)	(_REXBrm(0, MB, MI),		_O_r_X_B	(0xf6		     ,_b000		,MD,MB,MI,MS	,_u8(IM)))
+
+#define TESTWrr(RS, RD)			(_d16(), _REXLrr(RS, RD),	_O_Mrm		(0x85		,_b11,_r2(RS),_r2(RD)				))
+#define TESTWrm(RS, MD, MB, MI, MS)	(_d16(), _REXLrm(RS, MB, MI),	_O_r_X		(0x85		     ,_r2(RS)		,MD,MB,MI,MS		))
+#define TESTWir(IM, RD)			(X86_OPTIMIZE_ALU && ((RD) == X86_AX) ? \
+					(_d16(), _REXLrr(0, RD),	_O_W		(0xa9							,_u16(IM))) : \
+					(_d16(), _REXLrr(0, RD),	_O_Mrm_W	(0xf7		,_b11,_b000  ,_r2(RD)			,_u16(IM))) )
+#define TESTWim(IM, MD, MB, MI, MS)	(_d16(), _REXLrm(0, MB, MI),	_O_r_X_W	(0xf7		     ,_b000		,MD,MB,MI,MS	,_u16(IM)))
+
+#define TESTLrr(RS, RD)			(_REXLrr(RS, RD),		_O_Mrm		(0x85		,_b11,_r4(RS),_r4(RD)				))
+#define TESTLrm(RS, MD, MB, MI, MS)	(_REXLrm(RS, MB, MI),		_O_r_X		(0x85		     ,_r4(RS)		,MD,MB,MI,MS		))
+#define TESTLir(IM, RD)			(X86_OPTIMIZE_ALU && ((RD) == X86_EAX) ? \
+					(_REXLrr(0, RD),		_O_L		(0xa9							,IM	)) : \
+					(_REXLrr(0, RD),		_O_Mrm_L	(0xf7		,_b11,_b000  ,_r4(RD)			,IM	)) )
+#define TESTLim(IM, MD, MB, MI, MS)	(_REXLrm(0, MB, MI),		_O_r_X_L	(0xf7		     ,_b000		,MD,MB,MI,MS	,IM	))
+
+#define TESTQrr(RS, RD)			(_REXQrr(RS, RD),		_O_Mrm		(0x85		,_b11,_r8(RS),_r8(RD)				))
+#define TESTQrm(RS, MD, MB, MI, MS)	(_REXQrm(RS, MB, MI),		_O_r_X		(0x85		     ,_r8(RS)		,MD,MB,MI,MS		))
+#define TESTQir(IM, RD)			(X86_OPTIMIZE_ALU && ((RD) == X86_RAX) ? \
+					(_REXQrr(0, RD),		_O_L		(0xa9							,IM	)) : \
+					(_REXQrr(0, RD),		_O_Mrm_L	(0xf7		,_b11,_b000  ,_r8(RD)			,IM	)) )
+#define TESTQim(IM, MD, MB, MI, MS)	(_REXQrm(0, MB, MI),		_O_r_X_L	(0xf7		     ,_b000		,MD,MB,MI,MS	,IM	))
+
+
+/* --- Exchange instructions ----------------------------------------------- */
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+
+#define CMPXCHGBrr(RS, RD)		(_REXBrr(RS, RD),		_OO_Mrm		(0x0fb0		,_b11,_r1(RS),_r1(RD)				))
+#define CMPXCHGBrm(RS, MD, MB, MI, MS)	(_REXBrm(RS, MB, MI),		_OO_r_X		(0x0fb0		     ,_r1(RS)		,MD,MB,MI,MS		))
+
+#define CMPXCHGWrr(RS, RD)		(_d16(), _REXLrr(RS, RD),	_OO_Mrm		(0x0fb1		,_b11,_r2(RS),_r2(RD)				))
+#define CMPXCHGWrm(RS, MD, MB, MI, MS)	(_d16(), _REXLrm(RS, MB, MI),	_OO_r_X		(0x0fb1		     ,_r2(RS)		,MD,MB,MI,MS		))
+
+#define CMPXCHGLrr(RS, RD)		(_REXLrr(RS, RD),		_OO_Mrm		(0x0fb1		,_b11,_r4(RS),_r4(RD)				))
+#define CMPXCHGLrm(RS, MD, MB, MI, MS)	(_REXLrm(RS, MB, MI),		_OO_r_X		(0x0fb1		     ,_r4(RS)		,MD,MB,MI,MS		))
+
+#define CMPXCHGQrr(RS, RD)		(_REXQrr(RS, RD),		_OO_Mrm		(0x0fb1		,_b11,_r8(RS),_r8(RD)				))
+#define CMPXCHGQrm(RS, MD, MB, MI, MS)	(_REXQrm(RS, MB, MI),		_OO_r_X		(0x0fb1		     ,_r8(RS)		,MD,MB,MI,MS		))
+
+#define XADDBrr(RS, RD)			(_REXBrr(RS, RD),		_OO_Mrm		(0x0fc0		,_b11,_r1(RS),_r1(RD)				))
+#define XADDBrm(RS, MD, MB, MI, MS)	(_REXBrm(RS, MB, MI),		_OO_r_X		(0x0fc0		     ,_r1(RS)		,MD,MB,MI,MS		))
+
+#define XADDWrr(RS, RD)			(_d16(), _REXLrr(RS, RD),	_OO_Mrm		(0x0fc1		,_b11,_r2(RS),_r2(RD)				))
+#define XADDWrm(RS, MD, MB, MI, MS)	(_d16(), _REXLrm(RS, MB, MI),	_OO_r_X		(0x0fc1		     ,_r2(RS)		,MD,MB,MI,MS		))
+
+#define XADDLrr(RS, RD)			(_REXLrr(RS, RD),		_OO_Mrm		(0x0fc1		,_b11,_r4(RS),_r4(RD)				))
+#define XADDLrm(RS, MD, MB, MI, MS)	(_REXLrm(RS, MB, MI),		_OO_r_X		(0x0fc1		     ,_r4(RS)		,MD,MB,MI,MS		))
+
+#define XADDQrr(RS, RD)			(_REXQrr(RS, RD),		_OO_Mrm		(0x0fc1		,_b11,_r8(RS),_r8(RD)				))
+#define XADDQrm(RS, MD, MB, MI, MS)	(_REXQrm(RS, MB, MI),		_OO_r_X		(0x0fc1		     ,_r8(RS)		,MD,MB,MI,MS		))
+
+#define XCHGBrr(RS, RD)			(_REXBrr(RS, RD),		_O_Mrm		(0x86		,_b11,_r1(RS),_r1(RD)				))
+#define XCHGBrm(RS, MD, MB, MI, MS)	(_REXBrm(RS, MB, MI),		_O_r_X		(0x86		     ,_r1(RS)		,MD,MB,MI,MS		))
+
+#define XCHGWrr(RS, RD)			(_d16(), _REXLrr(RS, RD),	_O_Mrm		(0x87		,_b11,_r2(RS),_r2(RD)				))
+#define XCHGWrm(RS, MD, MB, MI, MS)	(_d16(), _REXLrm(RS, MB, MI),	_O_r_X		(0x87		     ,_r2(RS)		,MD,MB,MI,MS		))
+
+#define XCHGLrr(RS, RD)			(_REXLrr(RS, RD),		_O_Mrm		(0x87		,_b11,_r4(RS),_r4(RD)				))
+#define XCHGLrm(RS, MD, MB, MI, MS)	(_REXLrm(RS, MB, MI),		_O_r_X		(0x87		     ,_r4(RS)		,MD,MB,MI,MS		))
+
+#define XCHGQrr(RS, RD)			(_REXQrr(RS, RD),		_O_Mrm		(0x87		,_b11,_r8(RS),_r8(RD)				))
+#define XCHGQrm(RS, MD, MB, MI, MS)	(_REXQrm(RS, MB, MI),		_O_r_X		(0x87		     ,_r8(RS)		,MD,MB,MI,MS		))
+
+
+/* --- Increment/Decrement instructions ------------------------------------ */
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+
+#define DECBm(MD, MB, MI, MS)		(_REXBrm(0, MB, MI),		_O_r_X		(0xfe		     ,_b001		,MD,MB,MI,MS		))
+#define DECBr(RD)			(_REXBrr(0, RD),		_O_Mrm		(0xfe		,_b11,_b001  ,_r1(RD)				))
+
+#define DECWm(MD, MB, MI, MS)		(_d16(), _REXLrm(0, MB, MI),	_O_r_X		(0xff		     ,_b001		,MD,MB,MI,MS		))
+#define DECWr(RD)			(! X86_TARGET_64BIT ? (_d16(),	_Or		(0x48,_r2(RD)							)) : \
+					(_d16(), _REXLrr(0, RD),	_O_Mrm		(0xff		,_b11,_b001  ,_r2(RD)				)))
+
+#define DECLm(MD, MB, MI, MS)		(_REXLrm(0, MB, MI),		_O_r_X		(0xff		     ,_b001		,MD,MB,MI,MS		))
+#define DECLr(RD)			(! X86_TARGET_64BIT ?	 	_Or		(0x48,_r4(RD)							) : \
+					(_REXLrr(0, RD),		_O_Mrm		(0xff		,_b11,_b001  ,_r4(RD)				)))
+
+#define DECQm(MD, MB, MI, MS)		(_REXQrm(0, MB, MI),		_O_r_X		(0xff		     ,_b001		,MD,MB,MI,MS		))
+#define DECQr(RD)			(_REXQrr(0, RD),		_O_Mrm		(0xff		,_b11,_b001  ,_r8(RD)				))
+
+#define INCBm(MD, MB, MI, MS)		(_REXBrm(0, MB, MI),		_O_r_X		(0xfe		     ,_b000		,MD,MB,MI,MS		))
+#define INCBr(RD)			(_REXBrr(0, RD),		_O_Mrm		(0xfe		,_b11,_b000  ,_r1(RD)				))
+
+#define INCWm(MD, MB, MI, MS)		(_d16(), _REXLrm(0, MB, MI),	_O_r_X		(0xff		     ,_b000		,MD,MB,MI,MS		))
+#define INCWr(RD)			(! X86_TARGET_64BIT ? (_d16(),	_Or		(0x40,_r2(RD)							)) : \
+					(_d16(), _REXLrr(0, RD),	_O_Mrm		(0xff		,_b11,_b000  ,_r2(RD)				)) )
+
+#define INCLm(MD, MB, MI, MS)		(_REXLrm(0, MB, MI),		_O_r_X		(0xff		     ,_b000		,MD,MB,MI,MS		))
+#define INCLr(RD)			(! X86_TARGET_64BIT ? 		_Or		(0x40,_r4(RD)							) : \
+					(_REXLrr(0, RD),		_O_Mrm		(0xff		,_b11,_b000  ,_r4(RD)				)))
+
+#define INCQm(MD, MB, MI, MS)		(_REXQrm(0, MB, MI),		_O_r_X		(0xff		     ,_b000		,MD,MB,MI,MS		))
+#define INCQr(RD)			(_REXQrr(0, RD),		_O_Mrm		(0xff		,_b11,_b000  ,_r8(RD)				))
+
+
+/* --- Misc instructions --------------------------------------------------- */
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+
+#define BSFWrr(RS, RD)			(_d16(), _REXLrr(RD, RS),	_OO_Mrm		(0x0fbc		,_b11,_r2(RD),_r2(RS)				))
+#define BSFWmr(MD, MB, MI, MS, RD)	(_d16(), _REXLmr(MB, MI, RD),	_OO_r_X		(0x0fbc		     ,_r2(RD)		,MD,MB,MI,MS		))
+#define BSRWrr(RS, RD)			(_d16(), _REXLrr(RD, RS),	_OO_Mrm		(0x0fbd		,_b11,_r2(RD),_r2(RS)				))
+#define BSRWmr(MD, MB, MI, MS, RD)	(_d16(), _REXLmr(MB, MI, RD),	_OO_r_X		(0x0fbd		     ,_r2(RD)		,MD,MB,MI,MS		))
+
+#define BSFLrr(RS, RD)			(_REXLrr(RD, RS),		_OO_Mrm		(0x0fbc		,_b11,_r4(RD),_r4(RS)				))
+#define BSFLmr(MD, MB, MI, MS, RD)	(_REXLmr(MB, MI, RD),		_OO_r_X		(0x0fbc		     ,_r4(RD)		,MD,MB,MI,MS		))
+#define BSRLrr(RS, RD)			(_REXLrr(RD, RS),		_OO_Mrm		(0x0fbd		,_b11,_r4(RD),_r4(RS)				))
+#define BSRLmr(MD, MB, MI, MS, RD)	(_REXLmr(MB, MI, RD),		_OO_r_X		(0x0fbd		     ,_r4(RD)		,MD,MB,MI,MS		))
+
+#define BSFQrr(RS, RD)			(_REXQrr(RD, RS),		_OO_Mrm		(0x0fbc		,_b11,_r8(RD),_r8(RS)				))
+#define BSFQmr(MD, MB, MI, MS, RD)	(_REXQmr(MB, MI, RD),		_OO_r_X		(0x0fbc		     ,_r8(RD)		,MD,MB,MI,MS		))
+#define BSRQrr(RS, RD)			(_REXQrr(RD, RS),		_OO_Mrm		(0x0fbd		,_b11,_r8(RD),_r8(RS)				))
+#define BSRQmr(MD, MB, MI, MS, RD)	(_REXQmr(MB, MI, RD),		_OO_r_X		(0x0fbd		     ,_r8(RD)		,MD,MB,MI,MS		))
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+
+#define MOVSBWrr(RS, RD)		(_d16(), _REXBLrr(RD, RS),	_OO_Mrm		(0x0fbe		,_b11,_r2(RD),_r1(RS)				))
+#define MOVSBWmr(MD, MB, MI, MS, RD)	(_d16(), _REXLmr(MB, MI, RD),	_OO_r_X		(0x0fbe		     ,_r2(RD)		,MD,MB,MI,MS		))
+#define MOVZBWrr(RS, RD)		(_d16(), _REXBLrr(RD, RS),	_OO_Mrm		(0x0fb6		,_b11,_r2(RD),_r1(RS)				))
+#define MOVZBWmr(MD, MB, MI, MS, RD)	(_d16(), _REXLmr(MB, MI, RD),	_OO_r_X		(0x0fb6		     ,_r2(RD)		,MD,MB,MI,MS		))
+
+#define MOVSBLrr(RS, RD)		(_REXBLrr(RD, RS),		_OO_Mrm		(0x0fbe		,_b11,_r4(RD),_r1(RS)				))
+#define MOVSBLmr(MD, MB, MI, MS, RD)	(_REXLmr(MB, MI, RD),		_OO_r_X		(0x0fbe		     ,_r4(RD)		,MD,MB,MI,MS		))
+#define MOVZBLrr(RS, RD)		(_REXBLrr(RD, RS),		_OO_Mrm		(0x0fb6		,_b11,_r4(RD),_r1(RS)				))
+#define MOVZBLmr(MD, MB, MI, MS, RD)	(_REXLmr(MB, MI, RD),		_OO_r_X		(0x0fb6		     ,_r4(RD)		,MD,MB,MI,MS		))
+
+#define MOVSBQrr(RS, RD)		(_REXQrr(RD, RS),		_OO_Mrm		(0x0fbe		,_b11,_r8(RD),_r1(RS)				))
+#define MOVSBQmr(MD, MB, MI, MS, RD)	(_REXQmr(MB, MI, RD),		_OO_r_X		(0x0fbe		     ,_r8(RD)		,MD,MB,MI,MS		))
+#define MOVZBQrr(RS, RD)		(_REXQrr(RD, RS),		_OO_Mrm		(0x0fb6		,_b11,_r8(RD),_r1(RS)				))
+#define MOVZBQmr(MD, MB, MI, MS, RD)	(_REXQmr(MB, MI, RD),		_OO_r_X		(0x0fb6		     ,_r8(RD)		,MD,MB,MI,MS		))
+
+#define MOVSWLrr(RS, RD)		(_REXLrr(RD, RS),		_OO_Mrm		(0x0fbf		,_b11,_r4(RD),_r2(RS)				))
+#define MOVSWLmr(MD, MB, MI, MS, RD)	(_REXLmr(MB, MI, RD),		_OO_r_X		(0x0fbf		     ,_r4(RD)		,MD,MB,MI,MS		))
+#define MOVZWLrr(RS, RD)		(_REXLrr(RD, RS),		_OO_Mrm		(0x0fb7		,_b11,_r4(RD),_r2(RS)				))
+#define MOVZWLmr(MD, MB, MI, MS, RD)	(_REXLmr(MB, MI, RD),		_OO_r_X		(0x0fb7		     ,_r4(RD)		,MD,MB,MI,MS		))
+
+#define MOVSWQrr(RS, RD)		_m64only((_REXQrr(RD, RS),	_OO_Mrm		(0x0fbf		,_b11,_r8(RD),_r2(RS)				)))
+#define MOVSWQmr(MD, MB, MI, MS, RD)	_m64only((_REXQmr(MB, MI, RD),	_OO_r_X		(0x0fbf		     ,_r8(RD)		,MD,MB,MI,MS		)))
+#define MOVZWQrr(RS, RD)		_m64only((_REXQrr(RD, RS),	_OO_Mrm		(0x0fb7		,_b11,_r8(RD),_r2(RS)				)))
+#define MOVZWQmr(MD, MB, MI, MS, RD)	_m64only((_REXQmr(MB, MI, RD),	_OO_r_X		(0x0fb7		     ,_r8(RD)		,MD,MB,MI,MS		)))
+
+#define MOVSLQrr(RS, RD)		_m64only((_REXQrr(RD, RS),	_O_Mrm		(0x63		,_b11,_r8(RD),_r4(RS)				)))
+#define MOVSLQmr(MD, MB, MI, MS, RD)	_m64only((_REXQmr(MB, MI, RD),	_O_r_X		(0x63		     ,_r8(RD)		,MD,MB,MI,MS		)))
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+
+#define LEALmr(MD, MB, MI, MS, RD)	(_REXLmr(MB, MI, RD),		_O_r_X		(0x8d		     ,_r4(RD)		,MD,MB,MI,MS		))
+#define LEAQmr(MD, MB, MI, MS, RD)	(_REXQmr(MB, MI, RD),		_O_r_X		(0x8d		     ,_r4(RD)		,MD,MB,MI,MS		))
+
+#define BSWAPLr(R)			(_REXLrr(0, R),			_OOr		(0x0fc8,_r4(R)							))
+#define BSWAPQr(R)			(_REXQrr(0, R),			_OOr		(0x0fc8,_r8(R)							))
+
+#define CLC()								_O		(0xf8								)
+#define STC()								_O		(0xf9								)
+#define CMC()								_O		(0xf5								)
+
+#define CLD()								_O		(0xfc								)
+#define STD()								_O		(0xfd								)
+
+#define CBTW()				(_d16(),			_O		(0x98								))
+#define CWTL()								_O		(0x98								)
+#define CLTQ()				_m64only(_REXQrr(0, 0),		_O		(0x98								))
+
+#define CBW				CBTW
+#define CWDE				CWTL
+#define CDQE				CLTQ
+
+#define CWTD()				(_d16(),			_O		(0x99								))
+#define CLTD()								_O		(0x99								)
+#define CQTO()				_m64only(_REXQrr(0, 0),		_O		(0x99								))
+
+#define CWD				CWTD
+#define CDQ				CLTD
+#define CQO				CQTO
+
+#define LAHF()								_O		(0x9f								)
+#define SAHF()								_O		(0x9e								)
+
+/*									_format		Opcd		,Mod ,r	    ,m		,mem=dsp+sib	,imm... */
+
+#define CPUID()								_OO		(0x0fa2								)
+#define RDTSC()								_OO		(0xff31								)
+
+#define ENTERii(W, B)							_O_W_B		(0xc8						  ,_su16(W),_su8(B))
+
+#define LEAVE()								_O		(0xc9								)
+#define RET()								_O		(0xc3								)
+#define RETi(IM)							_O_W		(0xc2							,_su16(IM))
+
+#define NOP()								_O		(0x90								)
+
+
+/* --- Media 64-bit instructions ------------------------------------------- */
+
+enum {
+  X86_MMX_PABSB		= 0x1c, // 2P
+  X86_MMX_PABSW		= 0x1d, // 2P
+  X86_MMX_PABSD		= 0x1e, // 2P
+  X86_MMX_PACKSSWB	= 0x63,
+  X86_MMX_PACKSSDW	= 0x6b,
+  X86_MMX_PACKUSWB	= 0x67,
+  X86_MMX_PADDB		= 0xfc,
+  X86_MMX_PADDW		= 0xfd,
+  X86_MMX_PADDD		= 0xfe,
+  X86_MMX_PADDQ		= 0xd4,
+  X86_MMX_PADDSB	= 0xec,
+  X86_MMX_PADDSW	= 0xed,
+  X86_MMX_PADDUSB	= 0xdc,
+  X86_MMX_PADDUSW	= 0xdd,
+  X86_MMX_PAND		= 0xdb,
+  X86_MMX_PANDN		= 0xdf,
+  X86_MMX_PAVGB		= 0xe0,
+  X86_MMX_PAVGW		= 0xe3,
+  X86_MMX_PCMPEQB	= 0x74,
+  X86_MMX_PCMPEQW	= 0x75,
+  X86_MMX_PCMPEQD	= 0x76,
+  X86_MMX_PCMPGTB	= 0x64,
+  X86_MMX_PCMPGTW	= 0x65,
+  X86_MMX_PCMPGTD	= 0x66,
+  X86_MMX_PEXTRW	= 0xc5, // 64, /r ib
+  X86_MMX_PHADDW	= 0x01, // 2P
+  X86_MMX_PHADDD	= 0x02, // 2P
+  X86_MMX_PHADDSW	= 0x03, // 2P
+  X86_MMX_PHSUBW	= 0x05, // 2P
+  X86_MMX_PHSUBD	= 0x06, // 2P
+  X86_MMX_PHSUBSW	= 0x07, // 2P
+  X86_MMX_PINSRW	= 0xc4, // 64, /r ib
+  X86_MMX_PMADDUBSW	= 0x04, // 2P
+  X86_MMX_PMADDWD	= 0xf5,
+  X86_MMX_PMAXSW	= 0xee,
+  X86_MMX_PMAXUB	= 0xde,
+  X86_MMX_PMINSW	= 0xea,
+  X86_MMX_PMINUB	= 0xda,
+  X86_MMX_PMOVMSKB	= 0xd7, // 64
+  X86_MMX_PMULHRSW	= 0x0b, // 2P
+  X86_MMX_PMULHUW	= 0xe4,
+  X86_MMX_PMULHW	= 0xe5,
+  X86_MMX_PMULLW	= 0xd5,
+  X86_MMX_PMULUDQ	= 0xf4,
+  X86_MMX_POR		= 0xeb,
+  X86_MMX_PSADBW	= 0xf6,
+  X86_MMX_PSHUFB	= 0x00, // 2P
+  X86_MMX_PSHUFW	= 0x70, // /r ib
+  X86_MMX_PSIGNB	= 0x08, // 2P
+  X86_MMX_PSIGNW	= 0x09, // 2P
+  X86_MMX_PSIGND	= 0x0a, // 2P
+  X86_MMX_PSLLW		= 0xf1,
+  X86_MMX_PSLLWi	= 0x71, // /6 ib
+  X86_MMX_PSLLD		= 0xf2,
+  X86_MMX_PSLLDi	= 0x72, // /6 ib
+  X86_MMX_PSLLQ		= 0xf3,
+  X86_MMX_PSLLQi	= 0x73, // /6 ib
+  X86_MMX_PSRAW		= 0xe1,
+  X86_MMX_PSRAWi	= 0x71, // /4 ib
+  X86_MMX_PSRAD		= 0xe2,
+  X86_MMX_PSRADi	= 0x72, // /4 ib
+  X86_MMX_PSRLW		= 0xd1,
+  X86_MMX_PSRLWi	= 0x71, // /2 ib
+  X86_MMX_PSRLD		= 0xd2,
+  X86_MMX_PSRLDi	= 0x72, // /2 ib
+  X86_MMX_PSRLQ		= 0xd3,
+  X86_MMX_PSRLQi	= 0x73, // /2 ib
+  X86_MMX_PSUBB		= 0xf8,
+  X86_MMX_PSUBW		= 0xf9,
+  X86_MMX_PSUBD		= 0xfa,
+  X86_MMX_PSUBQ		= 0xfb,
+  X86_MMX_PSUBSB	= 0xe8,
+  X86_MMX_PSUBSW	= 0xe9,
+  X86_MMX_PSUBUSB	= 0xd8,
+  X86_MMX_PSUBUSW	= 0xd9,
+  X86_MMX_PUNPCKHBW	= 0x68,
+  X86_MMX_PUNPCKHWD	= 0x69,
+  X86_MMX_PUNPCKHDQ	= 0x6a,
+  X86_MMX_PUNPCKLBW	= 0x60,
+  X86_MMX_PUNPCKLWD	= 0x61,
+  X86_MMX_PUNPCKLDQ	= 0x62,
+  X86_MMX_PXOR		= 0xef,
+};
+
+#define __MMXLrr(OP,RS,RSA,RD,RDA)		(_REXLrr(RD, RS),	_OO_Mrm		(0x0f00|(OP)	,_b11,RDA(RD),RSA(RS)				))
+#define __MMXLmr(OP,MD,MB,MI,MS,RD,RDA)		(_REXLmr(MB, MI, RD),	_OO_r_X		(0x0f00|(OP)	     ,RDA(RD)		,MD,MB,MI,MS		))
+#define __MMXLrm(OP,RS,RSA,MD,MB,MI,MS)		(_REXLrm(RS, MB, MI),	_OO_r_X		(0x0f00|(OP)	     ,RSA(RS)		,MD,MB,MI,MS		))
+#define __MMXLirr(OP,IM,RS,RSA,RD,RDA)		(_REXLrr(RD, RS),	_OO_Mrm_B	(0x0f00|(OP)	,_b11,RDA(RD),RSA(RS)			,_u8(IM)))
+#define __MMXLimr(OP,IM,MD,MB,MI,MS,RD,RDA)	(_REXLmr(MB, MI, RS),	_OO_r_X_B	(0x0f00|(OP)	     ,RDA(RD)		,MD,MB,MI,MS	,_u8(IM)))
+#define __MMXQrr(OP,RS,RSA,RD,RDA)		(_REXQrr(RD, RS),	_OO_Mrm		(0x0f00|(OP)	,_b11,RDA(RD),RSA(RS)				))
+#define __MMXQmr(OP,MD,MB,MI,MS,RD,RDA)		(_REXQmr(MB, MI, RD),	_OO_r_X		(0x0f00|(OP)	     ,RDA(RD)		,MD,MB,MI,MS		))
+#define __MMXQrm(OP,RS,RSA,MD,MB,MI,MS)		(_REXQrm(RS, MB, MI),	_OO_r_X		(0x0f00|(OP)	     ,RSA(RS)		,MD,MB,MI,MS		))
+#define __MMXQirr(OP,IM,RS,RSA,RD,RDA)		(_REXQrr(RD, RS),	_OO_Mrm_B	(0x0f00|(OP)	,_b11,RDA(RD),RSA(RS)			,_u8(IM)))
+#define __MMXQimr(OP,IM,MD,MB,MI,MS,RD,RDA)	(_REXQmr(MB, MI, RS),	_OO_r_X_B	(0x0f00|(OP)	     ,RDA(RD)		,MD,MB,MI,MS	,_u8(IM)))
+#define __MMX1Lrr(PX,OP,RS,RSA,RD,RDA)		(_REXLrr(RD, RS),	_B(0x0f),_OO_Mrm(((PX)<<8)|(OP)	,_b11,RDA(RD),RSA(RS)				))
+#define __MMX1Lmr(PX,OP,MD,MB,MI,MS,RD,RDA)	(_REXLmr(MB, MI, RD),	_B(0x0f),_OO_r_X(((PX)<<8)|(OP)	     ,RDA(RD)		,MD,MB,MI,MS		))
+#define __MMX1Lrm(PX,OP,RS,RSA,MD,MB,MI,MS)	(_REXLrm(RS, MB, MI),	_B(0x0f),_OO_r_X(((PX)<<8)|(OP)	     ,RSA(RS)		,MD,MB,MI,MS		))
+
+#define _MMXLrr(OP,RS,RD)		__MMXLrr(OP,RS,_rM,RD,_rM)
+#define _MMXLmr(OP,MD,MB,MI,MS,RD)	__MMXLmr(OP,MD,MB,MI,MS,RD,_rM)
+#define _MMXLrm(OP,RS,MD,MB,MI,MS)	__MMXLrm(OP,RS,_rM,MD,MB,MI,MS)
+#define _MMXQrr(OP,RS,RD)		__MMXQrr(OP,RS,_rM,RD,_rM)
+#define _MMXQmr(OP,MD,MB,MI,MS,RD)	__MMXQmr(OP,MD,MB,MI,MS,RD,_rM)
+#define _MMXQrm(OP,RS,MD,MB,MI,MS)	__MMXQrm(OP,RS,_rM,MD,MB,MI,MS)
+#define _2P_MMXLrr(OP,RS,RD)		__MMX1Lrr(0x38, OP,RS,_rM,RD,_rM)
+#define _2P_MMXLmr(OP,MD,MB,MI,MS,RD)	__MMX1Lmr(0x38, OP,MD,MB,MI,MS,RD,_rM)
+#define _2P_MMXLrm(OP,RS,MD,MB,MI,MS)	__MMX1Lrm(0x38, OP,RS,_rM,MD,MB,MI,MS)
+
+#define MMX_MOVDMDrr(RS, RD)		__MMXLrr(0x6e, RS,_r4, RD,_rM)
+#define MMX_MOVQMDrr(RS, RD)		__MMXQrr(0x6e, RS,_r8, RD,_rM)
+#define MMX_MOVDMSrr(RS, RD)		__MMXLrr(0x7e, RD,_r4, RS,_rM)
+#define MMX_MOVQMSrr(RS, RD)		__MMXQrr(0x7e, RD,_r8, RS,_rM)
+
+#define MMX_MOVDmr(MD, MB, MI, MS, RD)	_MMXLmr(0x6e, MD, MB, MI, MS, RD)
+#define MMX_MOVDrm(RS, MD, MB, MI, MS)	_MMXLrm(0x7e, RS, MD, MB, MI, MS)
+#define MMX_MOVQrr(RS, RD)		_MMXLrr(0x6f, RS, RD)
+#define MMX_MOVQmr(MD, MB, MI, MS, RD)	_MMXLmr(0x6f, MD, MB, MI, MS, RD)
+#define MMX_MOVQrm(RS, MD, MB, MI, MS)	_MMXLrm(0x7f, RS, MD, MB, MI, MS)
+
+// Original MMX instructions
+#define MMX_PACKSSWBrr(RS, RD)		_MMXLrr(X86_MMX_PACKSSWB,RS,RD)
+#define MMX_PACKSSWBmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PACKSSWB, MD, MB, MI, MS, RD)
+#define MMX_PACKSSDWrr(RS, RD)		_MMXLrr(X86_MMX_PACKSSDW,RS,RD)
+#define MMX_PACKSSDWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PACKSSDW, MD, MB, MI, MS, RD)
+#define MMX_PACKUSWBrr(RS, RD)		_MMXLrr(X86_MMX_PACKUSWB,RS,RD)
+#define MMX_PACKUSWBmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PACKUSWB, MD, MB, MI, MS, RD)
+#define MMX_PADDBrr(RS, RD)		_MMXLrr(X86_MMX_PADDB,RS,RD)
+#define MMX_PADDBmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PADDB, MD, MB, MI, MS, RD)
+#define MMX_PADDWrr(RS, RD)		_MMXLrr(X86_MMX_PADDW,RS,RD)
+#define MMX_PADDWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PADDW, MD, MB, MI, MS, RD)
+#define MMX_PADDDrr(RS, RD)		_MMXLrr(X86_MMX_PADDD,RS,RD)
+#define MMX_PADDDmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PADDD, MD, MB, MI, MS, RD)
+#define MMX_PADDQrr(RS, RD)		_MMXLrr(X86_MMX_PADDQ,RS,RD)
+#define MMX_PADDQmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PADDQ, MD, MB, MI, MS, RD)
+#define MMX_PADDSBrr(RS, RD)		_MMXLrr(X86_MMX_PADDSB,RS,RD)
+#define MMX_PADDSBmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PADDSB, MD, MB, MI, MS, RD)
+#define MMX_PADDSWrr(RS, RD)		_MMXLrr(X86_MMX_PADDSW,RS,RD)
+#define MMX_PADDSWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PADDSW, MD, MB, MI, MS, RD)
+#define MMX_PADDUSBrr(RS, RD)		_MMXLrr(X86_MMX_PADDUSB,RS,RD)
+#define MMX_PADDUSBmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PADDUSB, MD, MB, MI, MS, RD)
+#define MMX_PADDUSWrr(RS, RD)		_MMXLrr(X86_MMX_PADDUSW,RS,RD)
+#define MMX_PADDUSWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PADDUSW, MD, MB, MI, MS, RD)
+#define MMX_PANDrr(RS, RD)		_MMXLrr(X86_MMX_PAND,RS,RD)
+#define MMX_PANDmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PAND, MD, MB, MI, MS, RD)
+#define MMX_PANDNrr(RS, RD)		_MMXLrr(X86_MMX_PANDN,RS,RD)
+#define MMX_PANDNmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PANDN, MD, MB, MI, MS, RD)
+#define MMX_PAVGBrr(RS, RD)		_MMXLrr(X86_MMX_PAVGB,RS,RD)
+#define MMX_PAVGBmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PAVGB, MD, MB, MI, MS, RD)
+#define MMX_PAVGWrr(RS, RD)		_MMXLrr(X86_MMX_PAVGW,RS,RD)
+#define MMX_PAVGWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PAVGW, MD, MB, MI, MS, RD)
+#define MMX_PCMPEQBrr(RS, RD)		_MMXLrr(X86_MMX_PCMPEQB,RS,RD)
+#define MMX_PCMPEQBmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PCMPEQB, MD, MB, MI, MS, RD)
+#define MMX_PCMPEQWrr(RS, RD)		_MMXLrr(X86_MMX_PCMPEQW,RS,RD)
+#define MMX_PCMPEQWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PCMPEQW, MD, MB, MI, MS, RD)
+#define MMX_PCMPEQDrr(RS, RD)		_MMXLrr(X86_MMX_PCMPEQD,RS,RD)
+#define MMX_PCMPEQDmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PCMPEQD, MD, MB, MI, MS, RD)
+#define MMX_PCMPGTBrr(RS, RD)		_MMXLrr(X86_MMX_PCMPGTB,RS,RD)
+#define MMX_PCMPGTBmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PCMPGTB, MD, MB, MI, MS, RD)
+#define MMX_PCMPGTWrr(RS, RD)		_MMXLrr(X86_MMX_PCMPGTW,RS,RD)
+#define MMX_PCMPGTWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PCMPGTW, MD, MB, MI, MS, RD)
+#define MMX_PCMPGTDrr(RS, RD)		_MMXLrr(X86_MMX_PCMPGTD,RS,RD)
+#define MMX_PCMPGTDmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PCMPGTD, MD, MB, MI, MS, RD)
+#define MMX_PMADDWDrr(RS, RD)		_MMXLrr(X86_MMX_PMADDWD,RS,RD)
+#define MMX_PMADDWDmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PMADDWD, MD, MB, MI, MS, RD)
+#define MMX_PMAXSWrr(RS, RD)		_MMXLrr(X86_MMX_PMAXSW,RS,RD)
+#define MMX_PMAXSWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PMAXSW, MD, MB, MI, MS, RD)
+#define MMX_PMAXUBrr(RS, RD)		_MMXLrr(X86_MMX_PMAXUB,RS,RD)
+#define MMX_PMAXUBmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PMAXUB, MD, MB, MI, MS, RD)
+#define MMX_PMINSWrr(RS, RD)		_MMXLrr(X86_MMX_PMINSW,RS,RD)
+#define MMX_PMINSWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PMINSW, MD, MB, MI, MS, RD)
+#define MMX_PMINUBrr(RS, RD)		_MMXLrr(X86_MMX_PMINUB,RS,RD)
+#define MMX_PMINUBmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PMINUB, MD, MB, MI, MS, RD)
+#define MMX_PMULHUWrr(RS, RD)		_MMXLrr(X86_MMX_PMULHUW,RS,RD)
+#define MMX_PMULHUWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PMULHUW, MD, MB, MI, MS, RD)
+#define MMX_PMULHWrr(RS, RD)		_MMXLrr(X86_MMX_PMULHW,RS,RD)
+#define MMX_PMULHWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PMULHW, MD, MB, MI, MS, RD)
+#define MMX_PMULLWrr(RS, RD)		_MMXLrr(X86_MMX_PMULLW,RS,RD)
+#define MMX_PMULLWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PMULLW, MD, MB, MI, MS, RD)
+#define MMX_PMULUDQrr(RS, RD)		_MMXLrr(X86_MMX_PMULUDQ,RS,RD)
+#define MMX_PMULUDQmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PMULUDQ, MD, MB, MI, MS, RD)
+#define MMX_PORrr(RS, RD)		_MMXLrr(X86_MMX_POR,RS,RD)
+#define MMX_PORmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_POR, MD, MB, MI, MS, RD)
+#define MMX_PSADBWrr(RS, RD)		_MMXLrr(X86_MMX_PSADBW,RS,RD)
+#define MMX_PSADBWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSADBW, MD, MB, MI, MS, RD)
+#define MMX_PSLLWir(IM, RD)		__MMXLirr(X86_MMX_PSLLWi, IM, RD,_rM, _b110,_rN)
+#define MMX_PSLLWrr(RS, RD)		_MMXLrr(X86_MMX_PSLLW,RS,RD)
+#define MMX_PSLLWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSLLW, MD, MB, MI, MS, RD)
+#define MMX_PSLLDir(IM, RD)		__MMXLirr(X86_MMX_PSLLDi, IM, RD,_rM, _b110,_rN)
+#define MMX_PSLLDrr(RS, RD)		_MMXLrr(X86_MMX_PSLLD,RS,RD)
+#define MMX_PSLLDmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSLLD, MD, MB, MI, MS, RD)
+#define MMX_PSLLQir(IM, RD)		__MMXLirr(X86_MMX_PSLLQi, IM, RD,_rM, _b110,_rN)
+#define MMX_PSLLQrr(RS, RD)		_MMXLrr(X86_MMX_PSLLQ,RS,RD)
+#define MMX_PSLLQmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSLLQ, MD, MB, MI, MS, RD)
+#define MMX_PSRAWir(IM, RD)		__MMXLirr(X86_MMX_PSRAWi, IM, RD,_rM, _b100,_rN)
+#define MMX_PSRAWrr(RS, RD)		_MMXLrr(X86_MMX_PSRAW,RS,RD)
+#define MMX_PSRAWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSRAW, MD, MB, MI, MS, RD)
+#define MMX_PSRADir(IM, RD)		__MMXLirr(X86_MMX_PSRADi, IM, RD,_rM, _b100,_rN)
+#define MMX_PSRADrr(RS, RD)		_MMXLrr(X86_MMX_PSRAD,RS,RD)
+#define MMX_PSRADmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSRAD, MD, MB, MI, MS, RD)
+#define MMX_PSRLWir(IM, RD)		__MMXLirr(X86_MMX_PSRLWi, IM, RD,_rM, _b010,_rN)
+#define MMX_PSRLWrr(RS, RD)		_MMXLrr(X86_MMX_PSRLW,RS,RD)
+#define MMX_PSRLWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSRLW, MD, MB, MI, MS, RD)
+#define MMX_PSRLDir(IM, RD)		__MMXLirr(X86_MMX_PSRLDi, IM, RD,_rM, _b010,_rN)
+#define MMX_PSRLDrr(RS, RD)		_MMXLrr(X86_MMX_PSRLD,RS,RD)
+#define MMX_PSRLDmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSRLD, MD, MB, MI, MS, RD)
+#define MMX_PSRLQir(IM, RD)		__MMXLirr(X86_MMX_PSRLQi, IM, RD,_rM, _b010,_rN)
+#define MMX_PSRLQrr(RS, RD)		_MMXLrr(X86_MMX_PSRLQ,RS,RD)
+#define MMX_PSRLQmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSRLQ, MD, MB, MI, MS, RD)
+#define MMX_PSUBBrr(RS, RD)		_MMXLrr(X86_MMX_PSUBB,RS,RD)
+#define MMX_PSUBBmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSUBB, MD, MB, MI, MS, RD)
+#define MMX_PSUBWrr(RS, RD)		_MMXLrr(X86_MMX_PSUBW,RS,RD)
+#define MMX_PSUBWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSUBW, MD, MB, MI, MS, RD)
+#define MMX_PSUBDrr(RS, RD)		_MMXLrr(X86_MMX_PSUBD,RS,RD)
+#define MMX_PSUBDmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSUBD, MD, MB, MI, MS, RD)
+#define MMX_PSUBQrr(RS, RD)		_MMXLrr(X86_MMX_PSUBQ,RS,RD)
+#define MMX_PSUBQmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSUBQ, MD, MB, MI, MS, RD)
+#define MMX_PSUBSBrr(RS, RD)		_MMXLrr(X86_MMX_PSUBSB,RS,RD)
+#define MMX_PSUBSBmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSUBSB, MD, MB, MI, MS, RD)
+#define MMX_PSUBSWrr(RS, RD)		_MMXLrr(X86_MMX_PSUBSW,RS,RD)
+#define MMX_PSUBSWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSUBSW, MD, MB, MI, MS, RD)
+#define MMX_PSUBUSBrr(RS, RD)		_MMXLrr(X86_MMX_PSUBUSB,RS,RD)
+#define MMX_PSUBUSBmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSUBUSB, MD, MB, MI, MS, RD)
+#define MMX_PSUBUSWrr(RS, RD)		_MMXLrr(X86_MMX_PSUBUSW,RS,RD)
+#define MMX_PSUBUSWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PSUBUSW, MD, MB, MI, MS, RD)
+#define MMX_PUNPCKHBWrr(RS, RD)		_MMXLrr(X86_MMX_PUNPCKHBW,RS,RD)
+#define MMX_PUNPCKHBWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PUNPCKHBW, MD, MB, MI, MS, RD)
+#define MMX_PUNPCKHWDrr(RS, RD)		_MMXLrr(X86_MMX_PUNPCKHWD,RS,RD)
+#define MMX_PUNPCKHWDmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PUNPCKHWD, MD, MB, MI, MS, RD)
+#define MMX_PUNPCKHDQrr(RS, RD)		_MMXLrr(X86_MMX_PUNPCKHDQ,RS,RD)
+#define MMX_PUNPCKHDQmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PUNPCKHDQ, MD, MB, MI, MS, RD)
+#define MMX_PUNPCKLBWrr(RS, RD)		_MMXLrr(X86_MMX_PUNPCKLBW,RS,RD)
+#define MMX_PUNPCKLBWmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PUNPCKLBW, MD, MB, MI, MS, RD)
+#define MMX_PUNPCKLWDrr(RS, RD)		_MMXLrr(X86_MMX_PUNPCKLWD,RS,RD)
+#define MMX_PUNPCKLWDmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PUNPCKLWD, MD, MB, MI, MS, RD)
+#define MMX_PUNPCKLDQrr(RS, RD)		_MMXLrr(X86_MMX_PUNPCKLDQ,RS,RD)
+#define MMX_PUNPCKLDQmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PUNPCKLDQ, MD, MB, MI, MS, RD)
+#define MMX_PXORrr(RS, RD)		_MMXLrr(X86_MMX_PXOR,RS,RD)
+#define MMX_PXORmr(MD,MB,MI,MS,RD)	_MMXLmr(X86_MMX_PXOR, MD, MB, MI, MS, RD)
+
+#define MMX_PSHUFWirr(IM, RS, RD)		__MMXLirr(X86_MMX_PSHUFW, IM, RS,_rM, RD,_rM)
+#define MMX_PSHUFWimr(IM, MD, MB, MI, MS, RD)	__MMXLimr(X86_MMX_PSHUFW, IM, MD, MB, MI, MS, RD,_rM)
+#define MMX_PEXTRWLirr(IM, RS, RD)		__MMXLirr(X86_MMX_PEXTRW, IM, RS,_rM, RD,_r4)
+#define MMX_PEXTRWQirr(IM, RS, RD)		__MMXQirr(X86_MMX_PEXTRW, IM, RS,_rM, RD,_r8)
+#define MMX_PINSRWLirr(IM, RS, RD)		__MMXLirr(X86_MMX_PINSRW, IM, RS,_r4, RD,_rM)
+#define MMX_PINSRWLimr(IM, MD, MB, MI, MS, RD)	__MMXLimr(X86_MMX_PINSRW, IM, MD, MB, MI, MS, RD,_r4)
+#define MMX_PINSRWQirr(IM, RS, RD)		__MMXQirr(X86_MMX_PINSRW, IM, RS,_r4, RD,_rM)
+#define MMX_PINSRWQimr(IM, MD, MB, MI, MS, RD)	__MMXQimr(X86_MMX_PINSRW, IM, MD, MB, MI, MS, RD,_r8)
+
+// Additionnal MMX instructions, brought by SSSE3 ISA
+#define MMX_PABSBrr(RS, RD)		_2P_MMXLrr(X86_MMX_PABSB,RS,RD)
+#define MMX_PABSBmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PABSB, MD, MB, MI, MS, RD)
+#define MMX_PABSWrr(RS, RD)		_2P_MMXLrr(X86_MMX_PABSW,RS,RD)
+#define MMX_PABSWmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PABSW, MD, MB, MI, MS, RD)
+#define MMX_PABSDrr(RS, RD)		_2P_MMXLrr(X86_MMX_PABSD,RS,RD)
+#define MMX_PABSDmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PABSD, MD, MB, MI, MS, RD)
+#define MMX_PHADDWrr(RS, RD)		_2P_MMXLrr(X86_MMX_PHADDW,RS,RD)
+#define MMX_PHADDWmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PHADDW, MD, MB, MI, MS, RD)
+#define MMX_PHADDDrr(RS, RD)		_2P_MMXLrr(X86_MMX_PHADDD,RS,RD)
+#define MMX_PHADDDmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PHADDD, MD, MB, MI, MS, RD)
+#define MMX_PHADDSWrr(RS, RD)		_2P_MMXLrr(X86_MMX_PHADDSW,RS,RD)
+#define MMX_PHADDSWmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PHADDSW, MD, MB, MI, MS, RD)
+#define MMX_PHSUBWrr(RS, RD)		_2P_MMXLrr(X86_MMX_PHSUBW,RS,RD)
+#define MMX_PHSUBWmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PHSUBW, MD, MB, MI, MS, RD)
+#define MMX_PHSUBDrr(RS, RD)		_2P_MMXLrr(X86_MMX_PHSUBD,RS,RD)
+#define MMX_PHSUBDmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PHSUBD, MD, MB, MI, MS, RD)
+#define MMX_PHSUBSWrr(RS, RD)		_2P_MMXLrr(X86_MMX_PHSUBSW,RS,RD)
+#define MMX_PHSUBSWmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PHSUBSW, MD, MB, MI, MS, RD)
+#define MMX_PMADDUBSWrr(RS, RD)		_2P_MMXLrr(X86_MMX_PMADDUBSW,RS,RD)
+#define MMX_PMADDUBSWmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PMADDUBSW, MD, MB, MI, MS, RD)
+#define MMX_PMULHRSWrr(RS, RD)		_2P_MMXLrr(X86_MMX_PMULHRSW,RS,RD)
+#define MMX_PMULHRSWmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PMULHRSW, MD, MB, MI, MS, RD)
+#define MMX_PSHUFBrr(RS, RD)		_2P_MMXLrr(X86_MMX_PSHUFB,RS,RD)
+#define MMX_PSHUFBmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PSHUFB, MD, MB, MI, MS, RD)
+#define MMX_PSIGNBrr(RS, RD)		_2P_MMXLrr(X86_MMX_PSIGNB,RS,RD)
+#define MMX_PSIGNBmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PSIGNB, MD, MB, MI, MS, RD)
+#define MMX_PSIGNWrr(RS, RD)		_2P_MMXLrr(X86_MMX_PSIGNW,RS,RD)
+#define MMX_PSIGNWmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PSIGNW, MD, MB, MI, MS, RD)
+#define MMX_PSIGNDrr(RS, RD)		_2P_MMXLrr(X86_MMX_PSIGND,RS,RD)
+#define MMX_PSIGNDmr(MD,MB,MI,MS,RD)	_2P_MMXLmr(X86_MMX_PSIGND, MD, MB, MI, MS, RD)
+
+#define EMMS()								_OO		(0x0f77								)
+
+
+/* --- Media 128-bit instructions ------------------------------------------ */
+
+enum {
+  X86_SSE_CC_EQ		= 0,
+  X86_SSE_CC_LT		= 1,
+  X86_SSE_CC_GT		= 1,
+  X86_SSE_CC_LE		= 2,
+  X86_SSE_CC_GE		= 2,
+  X86_SSE_CC_U		= 3,
+  X86_SSE_CC_NEQ	= 4,
+  X86_SSE_CC_NLT	= 5,
+  X86_SSE_CC_NGT	= 5,
+  X86_SSE_CC_NLE	= 6,
+  X86_SSE_CC_NGE	= 6,
+  X86_SSE_CC_O		= 7
+};
+
+enum {
+  X86_SSE_UCOMI  = 0x2e,
+  X86_SSE_COMI   = 0x2f,
+  X86_SSE_CMP		= 0xc2,
+  X86_SSE_SQRT   = 0x51,
+  X86_SSE_RSQRT  = 0x52,
+  X86_SSE_RCP    = 0x53,
+  X86_SSE_AND    = 0x54,
+  X86_SSE_ANDN   = 0x55,
+  X86_SSE_OR     = 0x56,
+  X86_SSE_XOR    = 0x57,
+  X86_SSE_ADD    = 0x58,
+  X86_SSE_MUL    = 0x59,
+  X86_SSE_SUB    = 0x5c,
+  X86_SSE_MIN    = 0x5d,
+  X86_SSE_DIV    = 0x5e,
+  X86_SSE_MAX    = 0x5f,
+  X86_SSE_CVTDQ2PD	= 0xe6,
+  X86_SSE_CVTDQ2PS	= 0x5b,
+  X86_SSE_CVTPD2DQ	= 0xe6,
+  X86_SSE_CVTPD2PI	= 0x2d,
+  X86_SSE_CVTPD2PS	= 0x5a,
+  X86_SSE_CVTPI2PD	= 0x2a,
+  X86_SSE_CVTPI2PS	= 0x2a,
+  X86_SSE_CVTPS2DQ	= 0x5b,
+  X86_SSE_CVTPS2PD	= 0x5a,
+  X86_SSE_CVTPS2PI	= 0x2d,
+  X86_SSE_CVTSD2SI	= 0x2d,
+  X86_SSE_CVTSD2SS	= 0x5a,
+  X86_SSE_CVTSI2SD	= 0x2a,
+  X86_SSE_CVTSI2SS	= 0x2a,
+  X86_SSE_CVTSS2SD	= 0x5a,
+  X86_SSE_CVTSS2SI	= 0x2d,
+  X86_SSE_CVTTPD2PI	= 0x2c,
+  X86_SSE_CVTTPD2DQ	= 0xe6,
+  X86_SSE_CVTTPS2DQ	= 0x5b,
+  X86_SSE_CVTTPS2PI	= 0x2c,
+  X86_SSE_CVTTSD2SI	= 0x2c,
+  X86_SSE_CVTTSS2SI	= 0x2c,
+  X86_SSE_MOVMSK	= 0x50,
+  X86_SSE_PACKSSDW	= 0x6b,
+  X86_SSE_PACKSSWB	= 0x63,
+  X86_SSE_PACKUSWB	= 0x67,
+  X86_SSE_PADDB		= 0xfc,
+  X86_SSE_PADDD		= 0xfe,
+  X86_SSE_PADDQ		= 0xd4,
+  X86_SSE_PADDSB	= 0xec,
+  X86_SSE_PADDSW	= 0xed,
+  X86_SSE_PADDUSB	= 0xdc,
+  X86_SSE_PADDUSW	= 0xdd,
+  X86_SSE_PADDW		= 0xfd,
+  X86_SSE_PAND		= 0xdb,
+  X86_SSE_PANDN		= 0xdf,
+  X86_SSE_PAVGB		= 0xe0,
+  X86_SSE_PAVGW		= 0xe3,
+  X86_SSE_PCMPEQB	= 0x74,
+  X86_SSE_PCMPEQD	= 0x76,
+  X86_SSE_PCMPEQW	= 0x75,
+  X86_SSE_PCMPGTB	= 0x64,
+  X86_SSE_PCMPGTD	= 0x66,
+  X86_SSE_PCMPGTW	= 0x65,
+  X86_SSE_PMADDWD	= 0xf5,
+  X86_SSE_PMAXSW	= 0xee,
+  X86_SSE_PMAXUB	= 0xde,
+  X86_SSE_PMINSW	= 0xea,
+  X86_SSE_PMINUB	= 0xda,
+  X86_SSE_PMOVMSKB	= 0xd7,
+  X86_SSE_PMULHUW	= 0xe4,
+  X86_SSE_PMULHW	= 0xe5,
+  X86_SSE_PMULLW	= 0xd5,
+  X86_SSE_PMULUDQ	= 0xf4,
+  X86_SSE_POR		= 0xeb,
+  X86_SSE_PSADBW	= 0xf6,
+  X86_SSE_PSLLD		= 0xf2,
+  X86_SSE_PSLLQ		= 0xf3,
+  X86_SSE_PSLLW		= 0xf1,
+  X86_SSE_PSRAD		= 0xe2,
+  X86_SSE_PSRAW		= 0xe1,
+  X86_SSE_PSRLD		= 0xd2,
+  X86_SSE_PSRLQ		= 0xd3,
+  X86_SSE_PSRLW		= 0xd1,
+  X86_SSE_PSUBB		= 0xf8,
+  X86_SSE_PSUBD		= 0xfa,
+  X86_SSE_PSUBQ		= 0xfb,
+  X86_SSE_PSUBSB	= 0xe8,
+  X86_SSE_PSUBSW	= 0xe9,
+  X86_SSE_PSUBUSB	= 0xd8,
+  X86_SSE_PSUBUSW	= 0xd9,
+  X86_SSE_PSUBW		= 0xf9,
+  X86_SSE_PUNPCKHBW	= 0x68,
+  X86_SSE_PUNPCKHDQ	= 0x6a,
+  X86_SSE_PUNPCKHQDQ	= 0x6d,
+  X86_SSE_PUNPCKHWD	= 0x69,
+  X86_SSE_PUNPCKLBW	= 0x60,
+  X86_SSE_PUNPCKLDQ	= 0x62,
+  X86_SSE_PUNPCKLQDQ	= 0x6c,
+  X86_SSE_PUNPCKLWD	= 0x61,
+  X86_SSE_PXOR		= 0xef,
+  X86_SSSE3_PSHUFB	= 0x00,
+};
+
+/*									_format		Opcd		,Mod ,r	     ,m		,mem=dsp+sib	,imm... */
+
+#define _SSSE3Lrr(OP1,OP2,RS,RSA,RD,RDA)	(_B(0x66), _REXLrr(RD,RD),	_B(0x0f), _OO_Mrm	(((OP1)<<8)|(OP2)	,_b11,RDA(RD),RSA(RS)				))
+#define _SSSE3Lmr(OP1,OP2,MD,MB,MI,MS,RD,RDA)	(_B(0x66), _REXLmr(MB, MI, RD),	_B(0x0f), _OO_r_X	(((OP1)<<8)|(OP2)	     ,RDA(RD)		,MD,MB,MI,MS		))
+#define _SSSE3Lirr(OP1,OP2,IM,RS,RD)		(_B(0x66), _REXLrr(RD, RS),	_B(0x0f), _OO_Mrm_B	(((OP1)<<8)|(OP2)	,_b11,_rX(RD),_rX(RS)			,_u8(IM)))
+#define _SSSE3Limr(OP1,OP2,IM,MD,MB,MI,MS,RD)	(_B(0x66), _REXLmr(MB, MI, RD),	_B(0x0f), _OO_r_X_B	(((OP1)<<8)|(OP2)	     ,_rX(RD)		,MD,MB,MI,MS	,_u8(IM)))
+
+#define __SSELir(OP,MO,IM,RD)		(_REXLrr(0, RD),		_OO_Mrm_B	(0x0f00|(OP)	,_b11,MO     ,_rX(RD)			,_u8(IM)))
+#define __SSELim(OP,MO,IM,MD,MB,MI,MS)	(_REXLrm(0, MB, MI),		_OO_r_X_B	(0x0f00|(OP)	     ,MO		,MD,MB,MI,MS	,_u8(IM)))
+#define __SSELrr(OP,RS,RSA,RD,RDA)	(_REXLrr(RD, RS),		_OO_Mrm		(0x0f00|(OP)	,_b11,RDA(RD),RSA(RS)				))
+#define __SSELmr(OP,MD,MB,MI,MS,RD,RDA)	(_REXLmr(MB, MI, RD),		_OO_r_X		(0x0f00|(OP)	     ,RDA(RD)		,MD,MB,MI,MS		))
+#define __SSELrm(OP,RS,RSA,MD,MB,MI,MS)	(_REXLrm(RS, MB, MI),		_OO_r_X		(0x0f00|(OP)	     ,RSA(RS)		,MD,MB,MI,MS		))
+#define __SSELirr(OP,IM,RS,RD)		(_REXLrr(RD, RS),		_OO_Mrm_B	(0x0f00|(OP)	,_b11,_rX(RD),_rX(RS)			,_u8(IM)))
+#define __SSELimr(OP,IM,MD,MB,MI,MS,RD)	(_REXLmr(MB, MI, RD),		_OO_r_X_B	(0x0f00|(OP)	     ,_rX(RD)		,MD,MB,MI,MS	,_u8(IM)))
+
+#define __SSEQrr(OP,RS,RSA,RD,RDA)	(_REXQrr(RD, RS),		_OO_Mrm		(0x0f00|(OP)	,_b11,RDA(RD),RSA(RS)				))
+#define __SSEQmr(OP,MD,MB,MI,MS,RD,RDA)	(_REXQmr(MB, MI, RD),		_OO_r_X		(0x0f00|(OP)	     ,RDA(RD)		,MD,MB,MI,MS		))
+#define __SSEQrm(OP,RS,RSA,MD,MB,MI,MS)	(_REXQrm(RS, MB, MI),		_OO_r_X		(0x0f00|(OP)	     ,RSA(RS)		,MD,MB,MI,MS		))
+
+#define _SSELrr(PX,OP,RS,RSA,RD,RDA)					(_B(PX), __SSELrr(OP, RS, RSA, RD, RDA))
+#define _SSELmr(PX,OP,MD,MB,MI,MS,RD,RDA)				(_B(PX), __SSELmr(OP, MD, MB, MI, MS, RD, RDA))
+#define _SSELrm(PX,OP,RS,RSA,MD,MB,MI,MS)				(_B(PX), __SSELrm(OP, RS, RSA, MD, MB, MI, MS))
+#define _SSELir(PX,OP,MO,IM,RD)						(_B(PX), __SSELir(OP, MO, IM, RD))
+#define _SSELim(PX,OP,MO,IM,MD,MB,MI,MS)				(_B(PX), __SSELim(OP, MO, IM, MD, MB, MI, MS))
+#define _SSELirr(PX,OP,IM,RS,RD)					(_B(PX), __SSELirr(OP, IM, RS, RD))
+#define _SSELimr(PX,OP,IM,MD,MB,MI,MS,RD)				(_B(PX), __SSELimr(OP, IM, MD, MB, MI, MS, RD))
+
+#define _SSEQrr(PX,OP,RS,RSA,RD,RDA)					(_B(PX), __SSEQrr(OP, RS, RSA, RD, RDA))
+#define _SSEQmr(PX,OP,MD,MB,MI,MS,RD,RDA)				(_B(PX), __SSEQmr(OP, MD, MB, MI, MS, RD, RDA))
+#define _SSEQrm(PX,OP,RS,RSA,MD,MB,MI,MS)				(_B(PX), __SSEQrm(OP, RS, RSA, MD, MB, MI, MS))
+
+#define _SSEPSrr(OP,RS,RD)		__SSELrr(      OP, RS,_rX, RD,_rX)
+#define _SSEPSmr(OP,MD,MB,MI,MS,RD)	__SSELmr(      OP, MD, MB, MI, MS, RD,_rX)
+#define _SSEPSrm(OP,RS,MD,MB,MI,MS)	__SSELrm(      OP, RS,_rX, MD, MB, MI, MS)
+#define _SSEPSirr(OP,IM,RS,RD)		__SSELirr(     OP, IM, RS, RD)
+#define _SSEPSimr(OP,IM,MD,MB,MI,MS,RD)	__SSELimr(     OP, IM, MD, MB, MI, MS, RD)
+
+#define _SSEPDrr(OP,RS,RD)		 _SSELrr(0x66, OP, RS,_rX, RD,_rX)
+#define _SSEPDmr(OP,MD,MB,MI,MS,RD)	 _SSELmr(0x66, OP, MD, MB, MI, MS, RD,_rX)
+#define _SSEPDrm(OP,RS,MD,MB,MI,MS)	 _SSELrm(0x66, OP, RS,_rX, MD, MB, MI, MS)
+#define _SSEPDirr(OP,IM,RS,RD)		 _SSELirr(0x66, OP, IM, RS, RD)
+#define _SSEPDimr(OP,IM,MD,MB,MI,MS,RD)	 _SSELimr(0x66, OP, IM, MD, MB, MI, MS, RD)
+
+#define _SSESSrr(OP,RS,RD)		 _SSELrr(0xf3, OP, RS,_rX, RD,_rX)
+#define _SSESSmr(OP,MD,MB,MI,MS,RD)	 _SSELmr(0xf3, OP, MD, MB, MI, MS, RD,_rX)
+#define _SSESSrm(OP,RS,MD,MB,MI,MS)	 _SSELrm(0xf3, OP, RS,_rX, MD, MB, MI, MS)
+#define _SSESSirr(OP,IM,RS,RD)		 _SSELirr(0xf3, OP, IM, RS, RD)
+#define _SSESSimr(OP,IM,MD,MB,MI,MS,RD)	 _SSELimr(0xf3, OP, IM, MD, MB, MI, MS, RD)
+
+#define _SSESDrr(OP,RS,RD)		 _SSELrr(0xf2, OP, RS,_rX, RD,_rX)
+#define _SSESDmr(OP,MD,MB,MI,MS,RD)	 _SSELmr(0xf2, OP, MD, MB, MI, MS, RD,_rX)
+#define _SSESDrm(OP,RS,MD,MB,MI,MS)	 _SSELrm(0xf2, OP, RS,_rX, MD, MB, MI, MS)
+#define _SSESDirr(OP,IM,RS,RD)		 _SSELirr(0xf2, OP, IM, RS, RD)
+#define _SSESDimr(OP,IM,MD,MB,MI,MS,RD)	 _SSELimr(0xf2, OP, IM, MD, MB, MI, MS, RD)
+
+#define ADDPSrr(RS, RD)			_SSEPSrr(X86_SSE_ADD, RS, RD)
+#define ADDPSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_ADD, MD, MB, MI, MS, RD)
+#define ADDPDrr(RS, RD)			_SSEPDrr(X86_SSE_ADD, RS, RD)
+#define ADDPDmr(MD, MB, MI, MS, RD)	_SSEPDmr(X86_SSE_ADD, MD, MB, MI, MS, RD)
+
+#define ADDSSrr(RS, RD)			_SSESSrr(X86_SSE_ADD, RS, RD)
+#define ADDSSmr(MD, MB, MI, MS, RD)	_SSESSmr(X86_SSE_ADD, MD, MB, MI, MS, RD)
+#define ADDSDrr(RS, RD)			_SSESDrr(X86_SSE_ADD, RS, RD)
+#define ADDSDmr(MD, MB, MI, MS, RD)	_SSESDmr(X86_SSE_ADD, MD, MB, MI, MS, RD)
+
+#define ANDNPSrr(RS, RD)		_SSEPSrr(X86_SSE_ANDN, RS, RD)
+#define ANDNPSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_ANDN, MD, MB, MI, MS, RD)
+#define ANDNPDrr(RS, RD)		_SSEPDrr(X86_SSE_ANDN, RS, RD)
+#define ANDNPDmr(MD, MB, MI, MS, RD)	_SSEPDmr(X86_SSE_ANDN, MD, MB, MI, MS, RD)
+
+#define ANDPSrr(RS, RD)			_SSEPSrr(X86_SSE_AND, RS, RD)
+#define ANDPSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_AND, MD, MB, MI, MS, RD)
+#define ANDPDrr(RS, RD)			_SSEPDrr(X86_SSE_AND, RS, RD)
+#define ANDPDmr(MD, MB, MI, MS, RD)	_SSEPDmr(X86_SSE_AND, MD, MB, MI, MS, RD)
+
+#define CMPPSrr(IM, RS, RD)		_SSEPSirr(X86_SSE_CMP, IM, RS, RD)
+#define CMPPSmr(IM, MD, MB, MI, MS, RD)	_SSEPSimr(X86_SSE_CMP, IM, MD, MB, MI, MS, RD)
+#define CMPPDrr(IM, RS, RD)		_SSEPDirr(X86_SSE_CMP, IM, RS, RD)
+#define CMPPDmr(IM, MD, MB, MI, MS, RD)	_SSEPDimr(X86_SSE_CMP, IM, MD, MB, MI, MS, RD)
+
+#define CMPSSrr(IM, RS, RD)		_SSESSirr(X86_SSE_CMP, IM, RS, RD)
+#define CMPSSmr(IM, MD, MB, MI, MS, RD)	_SSESSimr(X86_SSE_CMP, IM, MD, MB, MI, MS, RD)
+#define CMPSDrr(IM, RS, RD)		_SSESDirr(X86_SSE_CMP, IM, RS, RD)
+#define CMPSDmr(IM, MD, MB, MI, MS, RD)	_SSESDimr(X86_SSE_CMP, IM, MD, MB, MI, MS, RD)
+
+#define DIVPSrr(RS, RD)			_SSEPSrr(X86_SSE_DIV, RS, RD)
+#define DIVPSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_DIV, MD, MB, MI, MS, RD)
+#define DIVPDrr(RS, RD)			_SSEPDrr(X86_SSE_DIV, RS, RD)
+#define DIVPDmr(MD, MB, MI, MS, RD)	_SSEPDmr(X86_SSE_DIV, MD, MB, MI, MS, RD)
+
+#define DIVSSrr(RS, RD)			_SSESSrr(X86_SSE_DIV, RS, RD)
+#define DIVSSmr(MD, MB, MI, MS, RD)	_SSESSmr(X86_SSE_DIV, MD, MB, MI, MS, RD)
+#define DIVSDrr(RS, RD)			_SSESDrr(X86_SSE_DIV, RS, RD)
+#define DIVSDmr(MD, MB, MI, MS, RD)	_SSESDmr(X86_SSE_DIV, MD, MB, MI, MS, RD)
+
+#define MAXPSrr(RS, RD)			_SSEPSrr(X86_SSE_MAX, RS, RD)
+#define MAXPSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_MAX, MD, MB, MI, MS, RD)
+#define MAXPDrr(RS, RD)			_SSEPDrr(X86_SSE_MAX, RS, RD)
+#define MAXPDmr(MD, MB, MI, MS, RD)	_SSEPDmr(X86_SSE_MAX, MD, MB, MI, MS, RD)
+
+#define MAXSSrr(RS, RD)			_SSESSrr(X86_SSE_MAX, RS, RD)
+#define MAXSSmr(MD, MB, MI, MS, RD)	_SSESSmr(X86_SSE_MAX, MD, MB, MI, MS, RD)
+#define MAXSDrr(RS, RD)			_SSESDrr(X86_SSE_MAX, RS, RD)
+#define MAXSDmr(MD, MB, MI, MS, RD)	_SSESDmr(X86_SSE_MAX, MD, MB, MI, MS, RD)
+
+#define MINPSrr(RS, RD)			_SSEPSrr(X86_SSE_MIN, RS, RD)
+#define MINPSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_MIN, MD, MB, MI, MS, RD)
+#define MINPDrr(RS, RD)			_SSEPDrr(X86_SSE_MIN, RS, RD)
+#define MINPDmr(MD, MB, MI, MS, RD)	_SSEPDmr(X86_SSE_MIN, MD, MB, MI, MS, RD)
+
+#define MINSSrr(RS, RD)			_SSESSrr(X86_SSE_MIN, RS, RD)
+#define MINSSmr(MD, MB, MI, MS, RD)	_SSESSmr(X86_SSE_MIN, MD, MB, MI, MS, RD)
+#define MINSDrr(RS, RD)			_SSESDrr(X86_SSE_MIN, RS, RD)
+#define MINSDmr(MD, MB, MI, MS, RD)	_SSESDmr(X86_SSE_MIN, MD, MB, MI, MS, RD)
+
+#define MULPSrr(RS, RD)			_SSEPSrr(X86_SSE_MUL, RS, RD)
+#define MULPSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_MUL, MD, MB, MI, MS, RD)
+#define MULPDrr(RS, RD)			_SSEPDrr(X86_SSE_MUL, RS, RD)
+#define MULPDmr(MD, MB, MI, MS, RD)	_SSEPDmr(X86_SSE_MUL, MD, MB, MI, MS, RD)
+
+#define MULSSrr(RS, RD)			_SSESSrr(X86_SSE_MUL, RS, RD)
+#define MULSSmr(MD, MB, MI, MS, RD)	_SSESSmr(X86_SSE_MUL, MD, MB, MI, MS, RD)
+#define MULSDrr(RS, RD)			_SSESDrr(X86_SSE_MUL, RS, RD)
+#define MULSDmr(MD, MB, MI, MS, RD)	_SSESDmr(X86_SSE_MUL, MD, MB, MI, MS, RD)
+
+#define ORPSrr(RS, RD)			_SSEPSrr(X86_SSE_OR, RS, RD)
+#define ORPSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_OR, MD, MB, MI, MS, RD)
+#define ORPDrr(RS, RD)			_SSEPDrr(X86_SSE_OR, RS, RD)
+#define ORPDmr(MD, MB, MI, MS, RD)	_SSEPDmr(X86_SSE_OR, MD, MB, MI, MS, RD)
+
+#define RCPPSrr(RS, RD)			_SSEPSrr(X86_SSE_RCP, RS, RD)
+#define RCPPSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_RCP, MD, MB, MI, MS, RD)
+#define RCPSSrr(RS, RD)			_SSESSrr(X86_SSE_RCP, RS, RD)
+#define RCPSSmr(MD, MB, MI, MS, RD)	_SSESSmr(X86_SSE_RCP, MD, MB, MI, MS, RD)
+
+#define RSQRTPSrr(RS, RD)		_SSEPSrr(X86_SSE_RSQRT, RS, RD)
+#define RSQRTPSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_RSQRT, MD, MB, MI, MS, RD)
+#define RSQRTSSrr(RS, RD)		_SSESSrr(X86_SSE_RSQRT, RS, RD)
+#define RSQRTSSmr(MD, MB, MI, MS, RD)	_SSESSmr(X86_SSE_RSQRT, MD, MB, MI, MS, RD)
+
+#define SQRTPSrr(RS, RD)		_SSEPSrr(X86_SSE_SQRT, RS, RD)
+#define SQRTPSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_SQRT, MD, MB, MI, MS, RD)
+#define SQRTPDrr(RS, RD)		_SSEPDrr(X86_SSE_SQRT, RS, RD)
+#define SQRTPDmr(MD, MB, MI, MS, RD)	_SSEPDmr(X86_SSE_SQRT, MD, MB, MI, MS, RD)
+
+#define SQRTSSrr(RS, RD)		_SSESSrr(X86_SSE_SQRT, RS, RD)
+#define SQRTSSmr(MD, MB, MI, MS, RD)	_SSESSmr(X86_SSE_SQRT, MD, MB, MI, MS, RD)
+#define SQRTSDrr(RS, RD)		_SSESDrr(X86_SSE_SQRT, RS, RD)
+#define SQRTSDmr(MD, MB, MI, MS, RD)	_SSESDmr(X86_SSE_SQRT, MD, MB, MI, MS, RD)
+
+#define SUBPSrr(RS, RD)			_SSEPSrr(X86_SSE_SUB, RS, RD)
+#define SUBPSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_SUB, MD, MB, MI, MS, RD)
+#define SUBPDrr(RS, RD)			_SSEPDrr(X86_SSE_SUB, RS, RD)
+#define SUBPDmr(MD, MB, MI, MS, RD)	_SSEPDmr(X86_SSE_SUB, MD, MB, MI, MS, RD)
+
+#define SUBSSrr(RS, RD)			_SSESSrr(X86_SSE_SUB, RS, RD)
+#define SUBSSmr(MD, MB, MI, MS, RD)	_SSESSmr(X86_SSE_SUB, MD, MB, MI, MS, RD)
+#define SUBSDrr(RS, RD)			_SSESDrr(X86_SSE_SUB, RS, RD)
+#define SUBSDmr(MD, MB, MI, MS, RD)	_SSESDmr(X86_SSE_SUB, MD, MB, MI, MS, RD)
+
+#define XORPSrr(RS, RD)			_SSEPSrr(X86_SSE_XOR, RS, RD)
+#define XORPSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_XOR, MD, MB, MI, MS, RD)
+#define XORPDrr(RS, RD)			_SSEPDrr(X86_SSE_XOR, RS, RD)
+#define XORPDmr(MD, MB, MI, MS, RD)	_SSEPDmr(X86_SSE_XOR, MD, MB, MI, MS, RD)
+
+#define COMISSrr(RS, RD)		_SSEPSrr(X86_SSE_COMI, RS, RD)
+#define COMISSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_COMI, MD, MB, MI, MS, RD)
+#define COMISDrr(RS, RD)		_SSEPDrr(X86_SSE_COMI, RS, RD)
+#define COMISDmr(MD, MB, MI, MS, RD)	_SSEPDmr(X86_SSE_COMI, MD, MB, MI, MS, RD)
+
+#define UCOMISSrr(RS, RD)		_SSEPSrr(X86_SSE_UCOMI, RS, RD)
+#define UCOMISSmr(MD, MB, MI, MS, RD)	_SSEPSmr(X86_SSE_UCOMI, MD, MB, MI, MS, RD)
+#define UCOMISDrr(RS, RD)		_SSEPDrr(X86_SSE_UCOMI, RS, RD)
+#define UCOMISDmr(MD, MB, MI, MS, RD)	_SSEPDmr(X86_SSE_UCOMI, MD, MB, MI, MS, RD)
+
+#define MOVAPSrr(RS, RD)		_SSEPSrr(0x28, RS, RD)
+#define MOVAPSmr(MD, MB, MI, MS, RD)	_SSEPSmr(0x28, MD, MB, MI, MS, RD)
+#define MOVAPSrm(RS, MD, MB, MI, MS)	_SSEPSrm(0x29, RS, MD, MB, MI, MS)
+
+#define MOVAPDrr(RS, RD)		_SSEPDrr(0x28, RS, RD)
+#define MOVAPDmr(MD, MB, MI, MS, RD)	_SSEPDmr(0x28, MD, MB, MI, MS, RD)
+#define MOVAPDrm(RS, MD, MB, MI, MS)	_SSEPDrm(0x29, RS, MD, MB, MI, MS)
+
+#define CVTDQ2PDrr(RS, RD)		 _SSELrr(0xf3, X86_SSE_CVTDQ2PD, RS,_rX, RD,_rX)
+#define CVTDQ2PDmr(MD, MB, MI, MS, RD)	 _SSELmr(0xf3, X86_SSE_CVTDQ2PD, MD, MB, MI, MS, RD,_rX)
+#define CVTDQ2PSrr(RS, RD)		__SSELrr(      X86_SSE_CVTDQ2PS, RS,_rX, RD,_rX)
+#define CVTDQ2PSmr(MD, MB, MI, MS, RD)	__SSELmr(      X86_SSE_CVTDQ2PS, MD, MB, MI, MS, RD,_rX)
+#define CVTPD2DQrr(RS, RD)		 _SSELrr(0xf2, X86_SSE_CVTPD2DQ, RS,_rX, RD,_rX)
+#define CVTPD2DQmr(MD, MB, MI, MS, RD)	 _SSELmr(0xf2, X86_SSE_CVTPD2DQ, MD, MB, MI, MS, RD,_rX)
+#define CVTPD2PIrr(RS, RD)		 _SSELrr(0x66, X86_SSE_CVTPD2PI, RS,_rX, RD,_rM)
+#define CVTPD2PImr(MD, MB, MI, MS, RD)	 _SSELmr(0x66, X86_SSE_CVTPD2PI, MD, MB, MI, MS, RD,_rM)
+#define CVTPD2PSrr(RS, RD)		 _SSELrr(0x66, X86_SSE_CVTPD2PS, RS,_rX, RD,_rX)
+#define CVTPD2PSmr(MD, MB, MI, MS, RD)	 _SSELmr(0x66, X86_SSE_CVTPD2PS, MD, MB, MI, MS, RD,_rX)
+#define CVTPI2PDrr(RS, RD)		 _SSELrr(0x66, X86_SSE_CVTPI2PD, RS,_rM, RD,_rX)
+#define CVTPI2PDmr(MD, MB, MI, MS, RD)	 _SSELmr(0x66, X86_SSE_CVTPI2PD, MD, MB, MI, MS, RD,_rX)
+#define CVTPI2PSrr(RS, RD)		__SSELrr(      X86_SSE_CVTPI2PS, RS,_rM, RD,_rX)
+#define CVTPI2PSmr(MD, MB, MI, MS, RD)	__SSELmr(      X86_SSE_CVTPI2PS, MD, MB, MI, MS, RD,_rX)
+#define CVTPS2DQrr(RS, RD)		 _SSELrr(0x66, X86_SSE_CVTPS2DQ, RS,_rX, RD,_rX)
+#define CVTPS2DQmr(MD, MB, MI, MS, RD)	 _SSELmr(0x66, X86_SSE_CVTPS2DQ, MD, MB, MI, MS, RD,_rX)
+#define CVTPS2PDrr(RS, RD)		__SSELrr(      X86_SSE_CVTPS2PD, RS,_rX, RD,_rX)
+#define CVTPS2PDmr(MD, MB, MI, MS, RD)	__SSELmr(      X86_SSE_CVTPS2PD, MD, MB, MI, MS, RD,_rX)
+#define CVTPS2PIrr(RS, RD)		__SSELrr(      X86_SSE_CVTPS2PI, RS,_rX, RD,_rM)
+#define CVTPS2PImr(MD, MB, MI, MS, RD)	__SSELmr(      X86_SSE_CVTPS2PI, MD, MB, MI, MS, RD,_rM)
+#define CVTSD2SILrr(RS, RD)		 _SSELrr(0xf2, X86_SSE_CVTSD2SI, RS,_rX, RD,_r4)
+#define CVTSD2SILmr(MD, MB, MI, MS, RD)	 _SSELmr(0xf2, X86_SSE_CVTSD2SI, MD, MB, MI, MS, RD,_r4)
+#define CVTSD2SIQrr(RS, RD)		 _SSEQrr(0xf2, X86_SSE_CVTSD2SI, RS,_rX, RD,_r8)
+#define CVTSD2SIQmr(MD, MB, MI, MS, RD)	 _SSEQmr(0xf2, X86_SSE_CVTSD2SI, MD, MB, MI, MS, RD,_r8)
+#define CVTSD2SSrr(RS, RD)		 _SSELrr(0xf2, X86_SSE_CVTSD2SS, RS,_rX, RD,_rX)
+#define CVTSD2SSmr(MD, MB, MI, MS, RD)	 _SSELmr(0xf2, X86_SSE_CVTSD2SS, MD, MB, MI, MS, RD,_rX)
+#define CVTSI2SDLrr(RS, RD)		 _SSELrr(0xf2, X86_SSE_CVTSI2SD, RS,_r4, RD,_rX)
+#define CVTSI2SDLmr(MD, MB, MI, MS, RD)	 _SSELmr(0xf2, X86_SSE_CVTSI2SD, MD, MB, MI, MS, RD,_rX)
+#define CVTSI2SDQrr(RS, RD)		 _SSEQrr(0xf2, X86_SSE_CVTSI2SD, RS,_r8, RD,_rX)
+#define CVTSI2SDQmr(MD, MB, MI, MS, RD)	 _SSEQmr(0xf2, X86_SSE_CVTSI2SD, MD, MB, MI, MS, RD,_rX)
+#define CVTSI2SSLrr(RS, RD)		 _SSELrr(0xf3, X86_SSE_CVTSI2SS, RS,_r4, RD,_rX)
+#define CVTSI2SSLmr(MD, MB, MI, MS, RD)	 _SSELmr(0xf3, X86_SSE_CVTSI2SS, MD, MB, MI, MS, RD,_rX)
+#define CVTSI2SSQrr(RS, RD)		 _SSEQrr(0xf3, X86_SSE_CVTSI2SS, RS,_r8, RD,_rX)
+#define CVTSI2SSQmr(MD, MB, MI, MS, RD)	 _SSEQmr(0xf3, X86_SSE_CVTSI2SS, MD, MB, MI, MS, RD,_rX)
+#define CVTSS2SDrr(RS, RD)		 _SSELrr(0xf3, X86_SSE_CVTSS2SD, RS,_rX, RD,_rX)
+#define CVTSS2SDmr(MD, MB, MI, MS, RD)	 _SSELmr(0xf3, X86_SSE_CVTSS2SD, MD, MB, MI, MS, RD,_rX)
+#define CVTSS2SILrr(RS, RD)		 _SSELrr(0xf3, X86_SSE_CVTSS2SI, RS,_rX, RD,_r4)
+#define CVTSS2SILmr(MD, MB, MI, MS, RD)	 _SSELmr(0xf3, X86_SSE_CVTSS2SI, MD, MB, MI, MS, RD,_r4)
+#define CVTSS2SIQrr(RS, RD)		 _SSEQrr(0xf3, X86_SSE_CVTSS2SI, RS,_rX, RD,_r8)
+#define CVTSS2SIQmr(MD, MB, MI, MS, RD)	 _SSEQmr(0xf3, X86_SSE_CVTSS2SI, MD, MB, MI, MS, RD,_r8)
+#define CVTTPD2PIrr(RS, RD)		 _SSELrr(0x66, X86_SSE_CVTTPD2PI, RS,_rX, RD,_rM)
+#define CVTTPD2PImr(MD, MB, MI, MS, RD)	 _SSELmr(0x66, X86_SSE_CVTTPD2PI, MD, MB, MI, MS, RD,_rM)
+#define CVTTPD2DQrr(RS, RD)		 _SSELrr(0x66, X86_SSE_CVTTPD2DQ, RS,_rX, RD,_rX)
+#define CVTTPD2DQmr(MD, MB, MI, MS, RD)	 _SSELmr(0x66, X86_SSE_CVTTPD2DQ, MD, MB, MI, MS, RD,_rX)
+#define CVTTPS2DQrr(RS, RD)		 _SSELrr(0xf3, X86_SSE_CVTTPS2DQ, RS,_rX, RD,_rX)
+#define CVTTPS2DQmr(MD, MB, MI, MS, RD)	 _SSELmr(0xf3, X86_SSE_CVTTPS2DQ, MD, MB, MI, MS, RD,_rX)
+#define CVTTPS2PIrr(RS, RD)		__SSELrr(      X86_SSE_CVTTPS2PI, RS,_rX, RD,_rM)
+#define CVTTPS2PImr(MD, MB, MI, MS, RD)	__SSELmr(      X86_SSE_CVTTPS2PI, MD, MB, MI, MS, RD,_rM)
+#define CVTTSD2SILrr(RS, RD)		 _SSELrr(0xf2, X86_SSE_CVTTSD2SI, RS,_rX, RD,_r4)
+#define CVTTSD2SILmr(MD, MB, MI, MS, RD) _SSELmr(0xf2, X86_SSE_CVTTSD2SI, MD, MB, MI, MS, RD,_r4)
+#define CVTTSD2SIQrr(RS, RD)		 _SSEQrr(0xf2, X86_SSE_CVTTSD2SI, RS,_rX, RD,_r8)
+#define CVTTSD2SIQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf2, X86_SSE_CVTTSD2SI, MD, MB, MI, MS, RD,_r8)
+#define CVTTSS2SILrr(RS, RD)		 _SSELrr(0xf3, X86_SSE_CVTTSS2SI, RS,_rX, RD,_r4)
+#define CVTTSS2SILmr(MD, MB, MI, MS, RD) _SSELmr(0xf3, X86_SSE_CVTTSS2SI, MD, MB, MI, MS, RD,_r4)
+#define CVTTSS2SIQrr(RS, RD)		 _SSEQrr(0xf3, X86_SSE_CVTTSS2SI, RS,_rX, RD,_r8)
+#define CVTTSS2SIQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf3, X86_SSE_CVTTSS2SI, MD, MB, MI, MS, RD,_r8)
+
+#define MOVDXDrr(RS, RD)		 _SSELrr(0x66, 0x6e, RS,_r4, RD,_rX)
+#define MOVDXDmr(MD, MB, MI, MS, RD)	 _SSELmr(0x66, 0x6e, MD, MB, MI, MS, RD,_rX)
+#define MOVQXDrr(RS, RD)		 _SSEQrr(0x66, 0x6e, RS,_r8, RD,_rX)
+#define MOVQXDmr(MD, MB, MI, MS, RD)	 _SSEQmr(0x66, 0x6e, MD, MB, MI, MS, RD,_rX)
+
+#define MOVDXSrr(RS, RD)		 _SSELrr(0x66, 0x7e, RD,_r4, RS,_rX)
+#define MOVDXSrm(RS, MD, MB, MI, MS)	 _SSELrm(0x66, 0x7e, RS,_rX, MD, MB, MI, MS)
+#define MOVQXSrr(RS, RD)		 _SSEQrr(0x66, 0x7e, RD,_r8, RS,_rX)
+#define MOVQXSrm(RS, MD, MB, MI, MS)	 _SSEQrm(0x66, 0x7e, RS,_rX, MD, MB, MI, MS)
+
+#define MOVDLMrr(RS, RD)		__SSELrr(      0x6e, RS,_r4, RD,_rM)
+#define MOVDLMmr(MD, MB, MI, MS, RD)	__SSELmr(      0x6e, MD, MB, MI, MS, RD,_rM)
+#define MOVDQMrr(RS, RD)		__SSEQrr(      0x6e, RS,_r8, RD,_rM)
+#define MOVDQMmr(MD, MB, MI, MS, RD)	__SSEQmr(      0x6e, MD, MB, MI, MS, RD,_rM)
+
+#define MOVDMLrr(RS, RD)		__SSELrr(      0x7e, RS,_rM, RD,_r4)
+#define MOVDMLrm(RS, MD, MB, MI, MS)	__SSELrm(      0x7e, RS,_rM, MD, MB, MI, MS)
+#define MOVDMQrr(RS, RD)		__SSEQrr(      0x7e, RS,_rM, RD,_r8)
+#define MOVDMQrm(RS, MD, MB, MI, MS)	__SSEQrm(      0x7e, RS,_rM, MD, MB, MI, MS)
+
+#define MOVDQ2Qrr(RS, RD)		 _SSELrr(0xf2, 0xd6, RS,_rX, RD,_rM)
+#define MOVMSKPSrr(RS, RD)		__SSELrr(      0x50, RS,_rX, RD,_r4)
+#define MOVMSKPDrr(RS, RD)		 _SSELrr(0x66, 0x50, RS,_rX, RD,_r4)
+
+#define MOVHLPSrr(RS, RD)		__SSELrr(      0x12, RS,_rX, RD,_rX)
+#define MOVLHPSrr(RS, RD)		__SSELrr(      0x16, RS,_rX, RD,_rX)
+
+#define MOVDQArr(RS, RD)		 _SSELrr(0x66, 0x6f, RS,_rX, RD,_rX)
+#define MOVDQAmr(MD, MB, MI, MS, RD)	 _SSELmr(0x66, 0x6f, MD, MB, MI, MS, RD,_rX)
+#define MOVDQArm(RS, MD, MB, MI, MS)	 _SSELrm(0x66, 0x7f, RS,_rX, MD, MB, MI, MS)
+
+#define MOVDQUrr(RS, RD)		 _SSELrr(0xf3, 0x6f, RS,_rX, RD,_rX)
+#define MOVDQUmr(MD, MB, MI, MS, RD)	 _SSELmr(0xf3, 0x6f, MD, MB, MI, MS, RD,_rX)
+#define MOVDQUrm(RS, MD, MB, MI, MS)	 _SSELrm(0xf3, 0x7f, RS,_rX, MD, MB, MI, MS)
+
+#define MOVHPDmr(MD, MB, MI, MS, RD)	 _SSELmr(0x66, 0x16, MD, MB, MI, MS, RD,_rX)
+#define MOVHPDrm(RS, MD, MB, MI, MS)	 _SSELrm(0x66, 0x17, RS,_rX, MD, MB, MI, MS)
+#define MOVHPSmr(MD, MB, MI, MS, RD)	__SSELmr(      0x16, MD, MB, MI, MS, RD,_rX)
+#define MOVHPSrm(RS, MD, MB, MI, MS)	__SSELrm(      0x17, RS,_rX, MD, MB, MI, MS)
+
+#define MOVLPDmr(MD, MB, MI, MS, RD)	 _SSELmr(0x66, 0x12, MD, MB, MI, MS, RD,_rX)
+#define MOVLPDrm(RS, MD, MB, MI, MS)	 _SSELrm(0x66, 0x13, RS,_rX, MD, MB, MI, MS)
+#define MOVLPSmr(MD, MB, MI, MS, RD)	__SSELmr(      0x12, MD, MB, MI, MS, RD,_rX)
+#define MOVLPSrm(RS, MD, MB, MI, MS)	__SSELrm(      0x13, RS,_rX, MD, MB, MI, MS)
+
+
+/* --- FLoating-Point instructions ----------------------------------------- */
+
+#define _ESCmi(D,B,I,S,OP)	(_REXLrm(0,B,I), _O_r_X(0xd8|(OP & 7), (OP >> 3), D,B,I,S))
+
+#define FLDr(R)			_OOr(0xd9c0,_rN(R))
+#define FLDLm(D,B,I,S)		_ESCmi(D,B,I,S,005)
+#define FLDSm(D,B,I,S)		_ESCmi(D,B,I,S,001)
+#define FLDTm(D,B,I,S)		_ESCmi(D,B,I,S,053)
+
+#define FSTr(R)			_OOr(0xddd0,_rN(R))
+#define FSTSm(D,B,I,S)		_ESCmi(D,B,I,S,021)
+#define FSTLm(D,B,I,S)		_ESCmi(D,B,I,S,025)
+
+#define FSTPr(R)		_OOr(0xddd8,_rN(R))
+#define FSTPSm(D,B,I,S)		_ESCmi(D,B,I,S,031)
+#define FSTPLm(D,B,I,S)		_ESCmi(D,B,I,S,035)
+#define FSTPTm(D,B,I,S)		_ESCmi(D,B,I,S,073)
+
+#define FADDr0(R)		_OOr(0xd8c0,_rN(R))
+#define FADD0r(R)		_OOr(0xdcc0,_rN(R))
+#define FADDP0r(R)		_OOr(0xdec0,_rN(R))
+#define FADDSm(D,B,I,S)		_ESCmi(D,B,I,S,000)
+#define FADDLm(D,B,I,S)		_ESCmi(D,B,I,S,004)
+
+#define FSUBSm(D,B,I,S)		_ESCmi(D,B,I,S,040)
+#define FSUBLm(D,B,I,S)		_ESCmi(D,B,I,S,044)
+#define FSUBr0(R)		_OOr(0xd8e0,_rN(R))
+#define FSUB0r(R)		_OOr(0xdce8,_rN(R))
+#define FSUBP0r(R)		_OOr(0xdee8,_rN(R))
+
+#define FSUBRr0(R)		_OOr(0xd8e8,_rN(R))
+#define FSUBR0r(R)		_OOr(0xdce0,_rN(R))
+#define FSUBRP0r(R)		_OOr(0xdee0,_rN(R))
+#define FSUBRSm(D,B,I,S)	_ESCmi(D,B,I,S,050)
+#define FSUBRLm(D,B,I,S)	_ESCmi(D,B,I,S,054)
+
+#define FMULr0(R)		_OOr(0xd8c8,_rN(R))
+#define FMUL0r(R)		_OOr(0xdcc8,_rN(R))
+#define FMULP0r(R)		_OOr(0xdec8,_rN(R))
+#define FMULSm(D,B,I,S)		_ESCmi(D,B,I,S,010)
+#define FMULLm(D,B,I,S)		_ESCmi(D,B,I,S,014)
+
+#define FDIVr0(R)		_OOr(0xd8f0,_rN(R))
+#define FDIV0r(R)		_OOr(0xdcf8,_rN(R))
+#define FDIVP0r(R)		_OOr(0xdef8,_rN(R))
+#define FDIVSm(D,B,I,S)		_ESCmi(D,B,I,S,060)
+#define FDIVLm(D,B,I,S)		_ESCmi(D,B,I,S,064)
+
+#define FDIVRr0(R)		_OOr(0xd8f8,_rN(R))
+#define FDIVR0r(R)		_OOr(0xdcf0,_rN(R))
+#define FDIVRP0r(R)		_OOr(0xdef0,_rN(R))
+#define FDIVRSm(D,B,I,S)	_ESCmi(D,B,I,S,070)
+#define FDIVRLm(D,B,I,S)	_ESCmi(D,B,I,S,074)
+
+#define FCMOVBr0(R)		_OOr(0xdac0,_rN(R))
+#define FCMOVBEr0(R)		_OOr(0xdad0,_rN(R))
+#define FCMOVEr0(R)		_OOr(0xdac8,_rN(R))
+#define FCMOVNBr0(R)		_OOr(0xdbc0,_rN(R))
+#define FCMOVNBEr0(R)		_OOr(0xdbd0,_rN(R))
+#define FCMOVNEr0(R)		_OOr(0xdbc8,_rN(R))
+#define FCMOVNUr0(R)		_OOr(0xdbd8,_rN(R))
+#define FCMOVUr0(R)		_OOr(0xdad8,_rN(R))
+#define FCOMIr0(R)		_OOr(0xdbf0,_rN(R))
+#define FCOMIPr0(R)		_OOr(0xdff0,_rN(R))
+
+#define FCOMr(R)		_OOr(0xd8d0,_rN(R))
+#define FCOMSm(D,B,I,S)		_ESCmi(D,B,I,S,020)
+#define FCOMLm(D,B,I,S)		_ESCmi(D,B,I,S,024)
+
+#define FCOMPr(R)		_OOr(0xd8d8,_rN(R))
+#define FCOMPSm(D,B,I,S)	_ESCmi(D,B,I,S,030)
+#define FCOMPLm(D,B,I,S)	_ESCmi(D,B,I,S,034)
+
+#define FUCOMIr0(R)		_OOr(0xdbe8,_rN(R))
+#define FUCOMIPr0(R)		_OOr(0xdfe8,_rN(R))
+#define FUCOMPr(R)		_OOr(0xdde8,_rN(R))
+#define FUCOMr(R)		_OOr(0xdde0,_rN(R))
+
+#define FIADDLm(D,B,I,S)	_ESCmi(D,B,I,S,002)
+#define FICOMLm(D,B,I,S)	_ESCmi(D,B,I,S,022)
+#define FICOMPLm(D,B,I,S)	_ESCmi(D,B,I,S,032)
+#define FIDIVLm(D,B,I,S)	_ESCmi(D,B,I,S,062)
+#define FIDIVRLm(D,B,I,S)	_ESCmi(D,B,I,S,072)
+#define FILDLm(D,B,I,S)		_ESCmi(D,B,I,S,003)
+#define FILDQm(D,B,I,S)		_ESCmi(D,B,I,S,057)
+#define FIMULLm(D,B,I,S)	_ESCmi(D,B,I,S,012)
+#define FISTLm(D,B,I,S)		_ESCmi(D,B,I,S,023)
+#define FISTPLm(D,B,I,S)	_ESCmi(D,B,I,S,033)
+#define FISTPQm(D,B,I,S)	_ESCmi(D,B,I,S,077)
+#define FISUBLm(D,B,I,S)	_ESCmi(D,B,I,S,042)
+#define FISUBRLm(D,B,I,S)	_ESCmi(D,B,I,S,052)
+
+#define FREEr(R)		_OOr(0xddc0,_rN(R))
+#define FXCHr(R)		_OOr(0xd9c8,_rN(R))
+
+#endif /* X86_RTASM_H */
diff --git a/src/cpu/jit/compemu.h b/src/cpu/jit/compemu.h
new file mode 100644
index 0000000..8636de2
--- /dev/null
+++ b/src/cpu/jit/compemu.h
@@ -0,0 +1,582 @@
+
+#include "flags_x86.h"
+
+#ifdef CPU_64_BIT
+typedef uae_u64 uintptr;
+#else
+typedef uae_u32 uintptr;
+#endif
+
+/* Flags for Bernie during development/debugging. Should go away eventually */
+#define DISTRUST_CONSISTENT_MEM 0
+#define TAGMASK 0x000fffff
+#define TAGSIZE (TAGMASK+1)
+#define MAXRUN 1024
+
+extern uae_u8* start_pc_p;
+extern uae_u32 start_pc;
+
+#define cacheline(x) (((uae_u32)x)&TAGMASK)
+
+typedef struct {
+  uae_u16* location;
+  uae_u8  cycles;
+  uae_u8  specmem;
+  uae_u8  dummy2;
+  uae_u8  dummy3;
+} cpu_history;
+
+struct blockinfo_t;
+
+typedef union {
+    cpuop_func* handler;
+    struct blockinfo_t* bi;
+} cacheline;
+
+extern signed long pissoff;
+
+#define USE_OPTIMIZER 0
+#define USE_LOW_OPTIMIZER 0
+#define USE_ALIAS 1
+#define USE_F_ALIAS 1
+#define USE_SOFT_FLUSH 1
+#define USE_OFFSET 1
+#define COMP_DEBUG 1
+
+#if COMP_DEBUG
+#define Dif(x) if (x)
+#else
+#define Dif(x) if (0)
+#endif
+
+#define SCALE 2
+#define MAXCYCLES (1000 * CYCLE_UNIT)
+#define MAXREGOPT 65536
+
+#define BYTES_PER_INST 10240  /* paranoid ;-) */
+#define LONGEST_68K_INST 16 /* The number of bytes the longest possible
+			       68k instruction takes */
+#define MAX_CHECKSUM_LEN 2048 /* The maximum size we calculate checksums
+				 for. Anything larger will be flushed
+				 unconditionally even with SOFT_FLUSH */
+#define MAX_HOLD_BI 3  /* One for the current block, and up to two
+			  for jump targets */
+
+#define INDIVIDUAL_INST 0
+#define FLAG_C    0x0010
+#define FLAG_V    0x0008
+#define FLAG_Z    0x0004
+#define FLAG_N    0x0002
+#define FLAG_X    0x0001
+#define FLAG_CZNV (FLAG_C | FLAG_Z | FLAG_N | FLAG_V)
+#define FLAG_ZNV  (FLAG_Z | FLAG_N | FLAG_V)
+
+#define KILLTHERAT 1  /* Set to 1 to avoid some partial_rat_stalls */
+
+/* Whether to preserve registers across calls to JIT compiled routines */
+#if defined X86_ASSEMBLY
+#define USE_PUSH_POP 0
+#else
+#define USE_PUSH_POP 1
+#endif
+
+#define N_REGS 8  /* really only 7, but they are numbered 0,1,2,3,5,6,7 */
+#define N_FREGS 6 /* That leaves us two positions on the stack to play with */
+
+/* Functions exposed to newcpu, or to what was moved from newcpu.c to
+ * compemu_support.c */
+extern void init_comp(void);
+extern void flush(int save_regs);
+extern void small_flush(int save_regs);
+extern void set_target(uae_u8* t);
+extern void freescratch(void);
+extern void build_comp(void);
+extern void set_cache_state(int enabled);
+extern int get_cache_state(void);
+extern uae_u32 get_jitted_size(void);
+#ifdef JIT
+extern void flush_icache(uaecptr ptr, int n);
+extern void flush_icache_hard(uaecptr ptr, int n);
+#endif
+extern void alloc_cache(void);
+extern void compile_block(cpu_history* pc_hist, int blocklen, int totcyles);
+extern int check_for_cache_miss(void);
+
+
+#define scaled_cycles(x) (currprefs.m68k_speed<0?(((x)/SCALE)?(((x)/SCALE= REGALLOC */
+#define DECLARE(func) extern void func; extern void do_##func
+#else
+#define REGALLOC_O 2000000
+#define PEEPHOLE_O 2000000
+#define DECLARE(func) extern void func
+#endif
+
+
+/* What we expose to the outside */
+DECLARE(bt_l_ri(R4 r, IMM i));
+DECLARE(bt_l_rr(R4 r, R4 b));
+DECLARE(btc_l_ri(RW4 r, IMM i));
+DECLARE(btc_l_rr(RW4 r, R4 b));
+DECLARE(bts_l_ri(RW4 r, IMM i));
+DECLARE(bts_l_rr(RW4 r, R4 b));
+DECLARE(btr_l_ri(RW4 r, IMM i));
+DECLARE(btr_l_rr(RW4 r, R4 b));
+DECLARE(mov_l_rm(W4 d, IMM s));
+DECLARE(call_r(R4 r));
+DECLARE(sub_l_mi(IMM d, IMM s));
+DECLARE(mov_l_mi(IMM d, IMM s));
+DECLARE(mov_w_mi(IMM d, IMM s));
+DECLARE(mov_b_mi(IMM d, IMM s));
+DECLARE(rol_b_ri(RW1 r, IMM i));
+DECLARE(rol_w_ri(RW2 r, IMM i));
+DECLARE(rol_l_ri(RW4 r, IMM i));
+DECLARE(rol_l_rr(RW4 d, R1 r));
+DECLARE(rol_w_rr(RW2 d, R1 r));
+DECLARE(rol_b_rr(RW1 d, R1 r));
+DECLARE(shll_l_rr(RW4 d, R1 r));
+DECLARE(shll_w_rr(RW2 d, R1 r));
+DECLARE(shll_b_rr(RW1 d, R1 r));
+DECLARE(ror_b_ri(R1 r, IMM i));
+DECLARE(ror_w_ri(R2 r, IMM i));
+DECLARE(ror_l_ri(R4 r, IMM i));
+DECLARE(ror_l_rr(R4 d, R1 r));
+DECLARE(ror_w_rr(R2 d, R1 r));
+DECLARE(ror_b_rr(R1 d, R1 r));
+DECLARE(shrl_l_rr(RW4 d, R1 r));
+DECLARE(shrl_w_rr(RW2 d, R1 r));
+DECLARE(shrl_b_rr(RW1 d, R1 r));
+DECLARE(shra_l_rr(RW4 d, R1 r));
+DECLARE(shra_w_rr(RW2 d, R1 r));
+DECLARE(shra_b_rr(RW1 d, R1 r));
+DECLARE(shll_l_ri(RW4 r, IMM i));
+DECLARE(shll_w_ri(RW2 r, IMM i));
+DECLARE(shll_b_ri(RW1 r, IMM i));
+DECLARE(shrl_l_ri(RW4 r, IMM i));
+DECLARE(shrl_w_ri(RW2 r, IMM i));
+DECLARE(shrl_b_ri(RW1 r, IMM i));
+DECLARE(shra_l_ri(RW4 r, IMM i));
+DECLARE(shra_w_ri(RW2 r, IMM i));
+DECLARE(shra_b_ri(RW1 r, IMM i));
+DECLARE(setcc(W1 d, IMM cc));
+DECLARE(setcc_m(IMM d, IMM cc));
+DECLARE(cmov_b_rr(RW1 d, R1 s, IMM cc));
+DECLARE(cmov_w_rr(RW2 d, R2 s, IMM cc));
+DECLARE(cmov_l_rr(RW4 d, R4 s, IMM cc));
+DECLARE(cmov_l_rm(RW4 d, IMM s, IMM cc));
+DECLARE(bsf_l_rr(W4 d, R4 s));
+DECLARE(pop_m(IMM d));
+DECLARE(push_m(IMM d));
+DECLARE(pop_l(W4 d));
+DECLARE(push_l_i(IMM i));
+DECLARE(push_l(R4 s));
+DECLARE(clear_16(RW4 r));
+DECLARE(clear_8(RW4 r));
+DECLARE(sign_extend_16_rr(W4 d, R2 s));
+DECLARE(sign_extend_8_rr(W4 d, R1 s));
+DECLARE(zero_extend_16_rr(W4 d, R2 s));
+DECLARE(zero_extend_8_rr(W4 d, R1 s));
+DECLARE(imul_64_32(RW4 d, RW4 s));
+DECLARE(mul_64_32(RW4 d, RW4 s));
+DECLARE(imul_32_32(RW4 d, R4 s));
+DECLARE(mov_b_rr(W1 d, R1 s));
+DECLARE(mov_w_rr(W2 d, R2 s));
+DECLARE(mov_l_rrm_indexed(W4 d, R4 baser, R4 index));
+DECLARE(mov_w_rrm_indexed(W2 d, R4 baser, R4 index));
+DECLARE(mov_b_rrm_indexed(W1 d, R4 baser, R4 index));
+DECLARE(mov_l_mrr_indexed(R4 baser, R4 index, R4 s));
+DECLARE(mov_w_mrr_indexed(R4 baser, R4 index, R2 s));
+DECLARE(mov_b_mrr_indexed(R4 baser, R4 index, R1 s));
+DECLARE(mov_l_rm_indexed(W4 d, IMM base, R4 index));
+DECLARE(mov_l_rR(W4 d, R4 s, IMM offset));
+DECLARE(mov_w_rR(W2 d, R4 s, IMM offset));
+DECLARE(mov_b_rR(W1 d, R4 s, IMM offset));
+DECLARE(mov_l_brR(W4 d, R4 s, IMM offset));
+DECLARE(mov_w_brR(W2 d, R4 s, IMM offset));
+DECLARE(mov_b_brR(W1 d, R4 s, IMM offset));
+DECLARE(mov_l_Ri(R4 d, IMM i, IMM offset));
+DECLARE(mov_w_Ri(R4 d, IMM i, IMM offset));
+DECLARE(mov_b_Ri(R4 d, IMM i, IMM offset));
+DECLARE(mov_l_Rr(R4 d, R4 s, IMM offset));
+DECLARE(mov_w_Rr(R4 d, R2 s, IMM offset));
+DECLARE(mov_b_Rr(R4 d, R1 s, IMM offset));
+DECLARE(lea_l_brr(W4 d, R4 s, IMM offset));
+DECLARE(lea_l_brr_indexed(W4 d, R4 s, R4 index, IMM factor, IMM offset));
+DECLARE(mov_l_bRr(R4 d, R4 s, IMM offset));
+DECLARE(mov_w_bRr(R4 d, R2 s, IMM offset));
+DECLARE(mov_b_bRr(R4 d, R1 s, IMM offset));
+DECLARE(gen_bswap_32(RW4 r));
+DECLARE(gen_bswap_16(RW2 r));
+DECLARE(mov_l_rr(W4 d, R4 s));
+DECLARE(mov_l_mr(IMM d, R4 s));
+DECLARE(mov_w_mr(IMM d, R2 s));
+DECLARE(mov_w_rm(W2 d, IMM s));
+DECLARE(mov_b_mr(IMM d, R1 s));
+DECLARE(mov_b_rm(W1 d, IMM s));
+DECLARE(mov_l_ri(W4 d, IMM s));
+DECLARE(mov_w_ri(W2 d, IMM s));
+DECLARE(mov_b_ri(W1 d, IMM s));
+DECLARE(add_l_mi(IMM d, IMM s) );
+DECLARE(add_w_mi(IMM d, IMM s) );
+DECLARE(add_b_mi(IMM d, IMM s) );
+DECLARE(test_l_ri(R4 d, IMM i));
+DECLARE(test_l_rr(R4 d, R4 s));
+DECLARE(test_w_rr(R2 d, R2 s));
+DECLARE(test_b_rr(R1 d, R1 s));
+DECLARE(and_l_ri(RW4 d, IMM i));
+DECLARE(and_l(RW4 d, R4 s));
+DECLARE(and_w(RW2 d, R2 s));
+DECLARE(and_b(RW1 d, R1 s));
+DECLARE(or_l_ri(RW4 d, IMM i));
+DECLARE(or_l(RW4 d, R4 s));
+DECLARE(or_w(RW2 d, R2 s));
+DECLARE(or_b(RW1 d, R1 s));
+DECLARE(adc_l(RW4 d, R4 s));
+DECLARE(adc_w(RW2 d, R2 s));
+DECLARE(adc_b(RW1 d, R1 s));
+DECLARE(add_l(RW4 d, R4 s));
+DECLARE(add_w(RW2 d, R2 s));
+DECLARE(add_b(RW1 d, R1 s));
+DECLARE(sub_l_ri(RW4 d, IMM i));
+DECLARE(sub_w_ri(RW2 d, IMM i));
+DECLARE(sub_b_ri(RW1 d, IMM i));
+DECLARE(add_l_ri(RW4 d, IMM i));
+DECLARE(add_w_ri(RW2 d, IMM i));
+DECLARE(add_b_ri(RW1 d, IMM i));
+DECLARE(sbb_l(RW4 d, R4 s));
+DECLARE(sbb_w(RW2 d, R2 s));
+DECLARE(sbb_b(RW1 d, R1 s));
+DECLARE(sub_l(RW4 d, R4 s));
+DECLARE(sub_w(RW2 d, R2 s));
+DECLARE(sub_b(RW1 d, R1 s));
+DECLARE(cmp_l(R4 d, R4 s));
+DECLARE(cmp_l_ri(R4 r, IMM i));
+DECLARE(cmp_w(R2 d, R2 s));
+DECLARE(cmp_b(R1 d, R1 s));
+DECLARE(xor_l(RW4 d, R4 s));
+DECLARE(xor_w(RW2 d, R2 s));
+DECLARE(xor_b(RW1 d, R1 s));
+DECLARE(live_flags(void));
+DECLARE(dont_care_flags(void));
+DECLARE(duplicate_carry(void));
+DECLARE(restore_carry(void));
+DECLARE(start_needflags(void));
+DECLARE(end_needflags(void));
+DECLARE(make_flags_live(void));
+DECLARE(call_r_11(R4 r, W4 out1, R4 in1, IMM osize, IMM isize));
+DECLARE(call_r_02(R4 r, R4 in1, R4 in2, IMM isize1, IMM isize2));
+DECLARE(readmem_new(R4 address, W4 dest, IMM offset, IMM size, W4 tmp));
+DECLARE(writemem_new(R4 address, R4 source, IMM offset, IMM size, W4 tmp));
+DECLARE(forget_about(W4 r));
+DECLARE(nop(void));
+
+DECLARE(f_forget_about(FW r));
+DECLARE(fmov_pi(FW r));
+DECLARE(fmov_log10_2(FW r));
+DECLARE(fmov_log2_e(FW r));
+DECLARE(fmov_loge_2(FW r));
+DECLARE(fmov_1(FW r));
+DECLARE(fmov_0(FW r));
+DECLARE(fmov_rm(FW r, MEMR m));
+DECLARE(fmov_mr(MEMW m, FR r));
+DECLARE(fmovi_rm(FW r, MEMR m));
+DECLARE(fmovi_mrb(MEMW m, FR r, double *bounds));
+DECLARE(fmovs_rm(FW r, MEMR m));
+DECLARE(fmovs_mr(MEMW m, FR r));
+DECLARE(fcuts_r(FRW r));
+DECLARE(fcut_r(FRW r));
+DECLARE(fmov_ext_mr(MEMW m, FR r));
+DECLARE(fmov_ext_rm(FW r, MEMR m));
+DECLARE(fmov_rr(FW d, FR s));
+DECLARE(fldcw_m_indexed(R4 index, IMM base));
+DECLARE(ftst_r(FR r));
+DECLARE(dont_care_fflags(void));
+DECLARE(fsqrt_rr(FW d, FR s));
+DECLARE(fabs_rr(FW d, FR s));
+DECLARE(frndint_rr(FW d, FR s));
+DECLARE(fgetexp_rr(FW d, FR s));
+DECLARE(fgetman_rr(FW d, FR s));
+DECLARE(fsin_rr(FW d, FR s));
+DECLARE(fcos_rr(FW d, FR s));
+DECLARE(ftan_rr(FW d, FR s));
+DECLARE(fsincos_rr(FW d, FW c, FR s));
+DECLARE(fscale_rr(FRW d, FR s));
+DECLARE(ftwotox_rr(FW d, FR s));
+DECLARE(fetox_rr(FW d, FR s));
+DECLARE(fetoxM1_rr(FW d, FR s));
+DECLARE(ftentox_rr(FW d, FR s));
+DECLARE(flog2_rr(FW d, FR s));
+DECLARE(flogN_rr(FW d, FR s));
+DECLARE(flogNP1_rr(FW d, FR s));
+DECLARE(flog10_rr(FW d, FR s));
+DECLARE(fasin_rr(FW d, FR s));
+DECLARE(facos_rr(FW d, FR s));
+DECLARE(fatan_rr(FW d, FR s));
+DECLARE(fatanh_rr(FW d, FR s));
+DECLARE(fsinh_rr(FW d, FR s));
+DECLARE(fcosh_rr(FW d, FR s));
+DECLARE(ftanh_rr(FW d, FR s));
+DECLARE(fneg_rr(FW d, FR s));
+DECLARE(fadd_rr(FRW d, FR s));
+DECLARE(fsub_rr(FRW d, FR s));
+DECLARE(fmul_rr(FRW d, FR s));
+DECLARE(frem_rr(FRW d, FR s));
+DECLARE(frem1_rr(FRW d, FR s));
+DECLARE(fdiv_rr(FRW d, FR s));
+DECLARE(fcmp_rr(FR d, FR s));
+DECLARE(fflags_into_flags(W2 tmp));
+
+extern int failure;
+#define FAIL(x) do { failure|=x; } while (0)
+
+/* Convenience functions exposed to gencomp */
+extern uae_u32 m68k_pc_offset;
+extern void readbyte(int address, int dest, int tmp);
+extern void readword(int address, int dest, int tmp);
+extern void readlong(int address, int dest, int tmp);
+extern void writebyte(int address, int source, int tmp);
+extern void writeword(int address, int source, int tmp);
+extern void writelong(int address, int source, int tmp);
+extern void writeword_clobber(int address, int source, int tmp);
+extern void writelong_clobber(int address, int source, int tmp);
+extern void get_n_addr(int address, int dest, int tmp);
+extern void get_n_addr_jmp(int address, int dest, int tmp);
+extern void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp);
+extern int kill_rodent(int r);
+extern void sync_m68k_pc(void);
+extern uae_u32 get_const(int r);
+extern int  is_const(int r);
+extern void register_branch(uae_u32 not_taken, uae_u32 taken, uae_u8 cond);
+extern void empty_optimizer(void);
+
+#define comp_get_ibyte(o) do_get_mem_byte((uae_u8 *)(comp_pc_p + (o) + 1))
+#define comp_get_iword(o) do_get_mem_word((uae_u16 *)(comp_pc_p + (o)))
+#define comp_get_ilong(o) do_get_mem_long((uae_u32 *)(comp_pc_p + (o)))
+
+struct blockinfo_t;
+
+typedef struct dep_t {
+  uae_u32*            jmp_off;
+  struct blockinfo_t* target;
+  struct dep_t**      prev_p;
+  struct dep_t*       next;
+} dependency;
+
+typedef struct blockinfo_t {
+    uae_s32 count;
+    cpuop_func* direct_handler_to_use;
+    cpuop_func* handler_to_use;
+    /* The direct handler does not check for the correct address */
+
+    cpuop_func* handler;
+    cpuop_func* direct_handler;
+
+    cpuop_func* direct_pen;
+    cpuop_func* direct_pcc;
+
+    uae_u8* nexthandler;
+    uae_u8* pc_p;
+
+    uae_u32 c1;
+    uae_u32 c2;
+    uae_u32 len;
+
+    struct blockinfo_t* next_same_cl;
+    struct blockinfo_t** prev_same_cl_p;
+    struct blockinfo_t* next;
+    struct blockinfo_t** prev_p;
+
+    uae_u32 min_pcp;
+    uae_u8 optlevel;
+    uae_u8 needed_flags;
+    uae_u8 status;
+    uae_u8 havestate;
+
+    dependency  dep[2];  /* Holds things we depend on */
+    dependency* deplist; /* List of things that depend on this */
+    smallstate  env;
+} blockinfo;
+
+#define BI_NEW 0
+#define BI_COUNTING 1
+#define BI_TARGETTED 2
+
+typedef struct {
+    uae_u8 type;
+    uae_u8 reg;
+    uae_u32 next;
+} regacc;
+
+void execute_normal(void);
+void exec_nostats(void);
+void do_nothing(void);
+
+void comp_fdbcc_opp (uae_u32 opcode, uae_u16 extra);
+void comp_fscc_opp (uae_u32 opcode, uae_u16 extra);
+void comp_ftrapcc_opp (uae_u32 opcode, uaecptr oldpc);
+void comp_fbcc_opp (uae_u32 opcode);
+void comp_fsave_opp (uae_u32 opcode);
+void comp_frestore_opp (uae_u32 opcode);
+void comp_fpp_opp (uae_u32 opcode, uae_u16 extra);
diff --git a/src/cpu/jit/compemu_codegen.h b/src/cpu/jit/compemu_codegen.h
new file mode 100644
index 0000000..2f415d7
--- /dev/null
+++ b/src/cpu/jit/compemu_codegen.h
@@ -0,0 +1,607 @@
+/*
+ *  compiler/compemu.h - Public interface and definitions
+ *
+ *  Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ *
+ *  Adaptation for Basilisk II and improvements, copyright 2000-2005
+ *    Gwenole Beauchesne
+ *
+ *  Basilisk II (C) 1997-2008 Christian Bauer
+ *  
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef COMPEMU_H
+#define COMPEMU_H
+
+#ifdef JIT
+
+#if defined __i386__ || defined __x86_64__
+#include "flags_x86.h"
+#else
+#error "Unsupported JIT compiler for this architecture"
+#endif
+
+#if JIT_DEBUG
+/* dump some information (m68k block, x86 block addresses) about the compiler state */
+extern void compiler_dumpstate(void);
+#endif
+
+/* Now that we do block chaining, and also have linked lists on each tag,
+   TAGMASK can be much smaller and still do its job. Saves several megs
+   of memory! */
+#define TAGMASK 0x0000ffff
+#define TAGSIZE (TAGMASK+1)
+#define MAXRUN 1024
+#define cacheline(x) (((uintptr)x)&TAGMASK)
+
+extern uae_u8* start_pc_p;
+extern uae_u32 start_pc;
+
+struct blockinfo_t;
+
+struct cpu_history {
+	uae_u16 * location;
+};
+
+union cacheline {
+	cpuop_func * handler;
+	blockinfo_t * bi;
+};
+
+/* Use new spill/reload strategy when calling external functions */
+#define USE_OPTIMIZED_CALLS 0
+#if USE_OPTIMIZED_CALLS
+#error implementation in progress
+#endif
+
+/* (gb) When on, this option can save save up to 30% compilation time
+ *  when many lazy flushes occur (e.g. apps in MacOS 8.x).
+ */
+#define USE_SEPARATE_BIA 1
+
+/* Use chain of checksum_info_t to compute the block checksum */
+#define USE_CHECKSUM_INFO 1
+
+/* Use code inlining, aka follow-up of constant jumps */
+#define USE_INLINING 1
+
+/* Inlining requires the chained checksuming information */
+#if USE_INLINING
+#undef  USE_CHECKSUM_INFO
+#define USE_CHECKSUM_INFO 1
+#endif
+
+/* Does flush_icache_range() only check for blocks falling in the requested range? */
+#define LAZY_FLUSH_ICACHE_RANGE 0
+
+#define USE_F_ALIAS 1
+#define USE_OFFSET 1
+#define COMP_DEBUG 1
+
+#if COMP_DEBUG
+#define Dif(x) if (x)
+#else
+#define Dif(x) if (0)
+#endif
+
+#define SCALE 2
+
+#define BYTES_PER_INST 10240  /* paranoid ;-) */
+#define LONGEST_68K_INST 16 /* The number of bytes the longest possible
+			       68k instruction takes */
+#define MAX_CHECKSUM_LEN 2048 /* The maximum size we calculate checksums
+				 for. Anything larger will be flushed
+				 unconditionally even with SOFT_FLUSH */
+#define MAX_HOLD_BI 3  /* One for the current block, and up to two
+			  for jump targets */
+
+#define INDIVIDUAL_INST 0
+#if 1
+// gb-- my format from readcpu.cpp is not the same
+#define FLAG_X    0x0010
+#define FLAG_N    0x0008
+#define FLAG_Z    0x0004
+#define FLAG_V    0x0002
+#define FLAG_C    0x0001
+#else
+#define FLAG_C    0x0010
+#define FLAG_V    0x0008
+#define FLAG_Z    0x0004
+#define FLAG_N    0x0002
+#define FLAG_X    0x0001
+#endif
+#define FLAG_CZNV (FLAG_C | FLAG_Z | FLAG_N | FLAG_V)
+#define FLAG_ZNV  (FLAG_Z | FLAG_N | FLAG_V)
+
+#define KILLTHERAT 1  /* Set to 1 to avoid some partial_rat_stalls */
+
+#if defined(__x86_64__)
+#define N_REGS 16 /* really only 15, but they are numbered 0-3,5-15 */
+#else
+#define N_REGS 8  /* really only 7, but they are numbered 0,1,2,3,5,6,7 */
+#endif
+#define N_FREGS 6 /* That leaves us two positions on the stack to play with */
+
+/* Functions exposed to newcpu, or to what was moved from newcpu.c to
+ * compemu_support.c */
+extern void compiler_init(void);
+extern void compiler_exit(void);
+extern bool compiler_use_jit(void);
+extern void init_comp(void);
+extern void flush(int save_regs);
+extern void small_flush(int save_regs);
+extern void set_target(uae_u8* t);
+extern uae_u8* get_target(void);
+extern void freescratch(void);
+extern void build_comp(void);
+extern void set_cache_state(int enabled);
+extern int get_cache_state(void);
+extern uae_u32 get_jitted_size(void);
+extern void (*flush_icache)(int n);
+extern void alloc_cache(void);
+extern int check_for_cache_miss(void);
+
+/* JIT FPU compilation */
+extern void comp_fpp_opp (uae_u32 opcode, uae_u16 extra);
+extern void comp_fbcc_opp (uae_u32 opcode);
+extern void comp_fscc_opp (uae_u32 opcode, uae_u16 extra);
+
+extern uae_u32 needed_flags;
+extern cacheline cache_tags[];
+extern uae_u8* comp_pc_p;
+extern void* pushall_call_handler;
+
+#define VREGS 32
+#define VFREGS 16
+
+#define INMEM 1
+#define CLEAN 2
+#define DIRTY 3
+#define UNDEF 4
+#define ISCONST 5
+
+typedef struct {
+  uae_u32* mem;
+  uae_u32 val;
+  uae_u8 is_swapped;
+  uae_u8 status;
+  uae_s8 realreg; /* gb-- realreg can hold -1 */
+  uae_u8 realind; /* The index in the holds[] array */
+  uae_u8 needflush;
+  uae_u8 validsize;
+  uae_u8 dirtysize;
+  uae_u8 dummy;
+} reg_status;
+
+typedef struct {
+  uae_u32* mem;
+  double val;
+  uae_u8 status;
+  uae_s8 realreg; /* gb-- realreg can hold -1 */
+  uae_u8 realind;  
+  uae_u8 needflush;
+} freg_status;
+
+#define PC_P 16
+#define FLAGX 17
+#define FLAGTMP 18
+#define NEXT_HANDLER 19
+#define S1 20
+#define S2 21
+#define S3 22
+#define S4 23
+#define S5 24
+#define S6 25
+#define S7 26
+#define S8 27
+#define S9 28
+#define S10 29
+#define S11 30
+#define S12 31
+
+#define FP_RESULT 8
+#define FS1 9
+#define FS2 10
+#define FS3 11
+
+typedef struct {
+  uae_u32 touched;
+  uae_s8 holds[VREGS];
+  uae_u8 nholds;
+  uae_u8 canbyte;
+  uae_u8 canword;
+  uae_u8 locked;
+} n_status;
+
+typedef struct {
+  uae_u32 touched;
+  uae_s8 holds[VFREGS];
+  uae_u8 nholds;
+  uae_u8 locked;
+} fn_status;
+
+/* For flag handling */
+#define NADA 1
+#define TRASH 2
+#define VALID 3
+
+/* needflush values */
+#define NF_SCRATCH   0
+#define NF_TOMEM     1
+#define NF_HANDLER   2
+
+typedef struct {
+    /* Integer part */
+    reg_status state[VREGS];
+    n_status   nat[N_REGS];
+    uae_u32 flags_on_stack;
+    uae_u32 flags_in_flags;
+    uae_u32 flags_are_important;
+    /* FPU part */
+    freg_status fate[VFREGS];
+    fn_status   fat[N_FREGS];
+
+    /* x86 FPU part */
+    uae_s8 spos[N_FREGS];
+    uae_s8 onstack[6];
+    uae_s8 tos;
+} bigstate;
+
+typedef struct {
+  /* Integer part */
+  char virt[VREGS];
+  char nat[N_REGS];
+} smallstate;
+
+extern bigstate live;
+extern int touchcnt;
+
+
+#define IMM uae_s32
+#define R1  uae_u32
+#define R2  uae_u32
+#define R4  uae_u32
+#define W1  uae_u32
+#define W2  uae_u32
+#define W4  uae_u32
+#define RW1 uae_u32
+#define RW2 uae_u32
+#define RW4 uae_u32
+#define MEMR uae_u32
+#define MEMW uae_u32
+#define MEMRW uae_u32
+
+#define FW   uae_u32
+#define FR   uae_u32
+#define FRW  uae_u32
+
+#define MIDFUNC(nargs,func,args) void func args
+#define MENDFUNC(nargs,func,args) 
+#define COMPCALL(func) func
+
+#define LOWFUNC(flags,mem,nargs,func,args) static __inline__ void func args
+#define LENDFUNC(flags,mem,nargs,func,args) 
+
+/* What we expose to the outside */
+#define DECLARE_MIDFUNC(func) extern void func
+DECLARE_MIDFUNC(bt_l_ri(R4 r, IMM i));
+DECLARE_MIDFUNC(bt_l_rr(R4 r, R4 b));
+DECLARE_MIDFUNC(btc_l_ri(RW4 r, IMM i));
+DECLARE_MIDFUNC(btc_l_rr(RW4 r, R4 b));
+DECLARE_MIDFUNC(bts_l_ri(RW4 r, IMM i));
+DECLARE_MIDFUNC(bts_l_rr(RW4 r, R4 b));
+DECLARE_MIDFUNC(btr_l_ri(RW4 r, IMM i));
+DECLARE_MIDFUNC(btr_l_rr(RW4 r, R4 b));
+DECLARE_MIDFUNC(mov_l_rm(W4 d, IMM s));
+DECLARE_MIDFUNC(call_r(R4 r));
+DECLARE_MIDFUNC(sub_l_mi(IMM d, IMM s));
+DECLARE_MIDFUNC(mov_l_mi(IMM d, IMM s));
+DECLARE_MIDFUNC(mov_w_mi(IMM d, IMM s));
+DECLARE_MIDFUNC(mov_b_mi(IMM d, IMM s));
+DECLARE_MIDFUNC(rol_b_ri(RW1 r, IMM i));
+DECLARE_MIDFUNC(rol_w_ri(RW2 r, IMM i));
+DECLARE_MIDFUNC(rol_l_ri(RW4 r, IMM i));
+DECLARE_MIDFUNC(rol_l_rr(RW4 d, R1 r));
+DECLARE_MIDFUNC(rol_w_rr(RW2 d, R1 r));
+DECLARE_MIDFUNC(rol_b_rr(RW1 d, R1 r));
+DECLARE_MIDFUNC(shll_l_rr(RW4 d, R1 r));
+DECLARE_MIDFUNC(shll_w_rr(RW2 d, R1 r));
+DECLARE_MIDFUNC(shll_b_rr(RW1 d, R1 r));
+DECLARE_MIDFUNC(ror_b_ri(R1 r, IMM i));
+DECLARE_MIDFUNC(ror_w_ri(R2 r, IMM i));
+DECLARE_MIDFUNC(ror_l_ri(R4 r, IMM i));
+DECLARE_MIDFUNC(ror_l_rr(R4 d, R1 r));
+DECLARE_MIDFUNC(ror_w_rr(R2 d, R1 r));
+DECLARE_MIDFUNC(ror_b_rr(R1 d, R1 r));
+DECLARE_MIDFUNC(shrl_l_rr(RW4 d, R1 r));
+DECLARE_MIDFUNC(shrl_w_rr(RW2 d, R1 r));
+DECLARE_MIDFUNC(shrl_b_rr(RW1 d, R1 r));
+DECLARE_MIDFUNC(shra_l_rr(RW4 d, R1 r));
+DECLARE_MIDFUNC(shra_w_rr(RW2 d, R1 r));
+DECLARE_MIDFUNC(shra_b_rr(RW1 d, R1 r));
+DECLARE_MIDFUNC(shll_l_ri(RW4 r, IMM i));
+DECLARE_MIDFUNC(shll_w_ri(RW2 r, IMM i));
+DECLARE_MIDFUNC(shll_b_ri(RW1 r, IMM i));
+DECLARE_MIDFUNC(shrl_l_ri(RW4 r, IMM i));
+DECLARE_MIDFUNC(shrl_w_ri(RW2 r, IMM i));
+DECLARE_MIDFUNC(shrl_b_ri(RW1 r, IMM i));
+DECLARE_MIDFUNC(shra_l_ri(RW4 r, IMM i));
+DECLARE_MIDFUNC(shra_w_ri(RW2 r, IMM i));
+DECLARE_MIDFUNC(shra_b_ri(RW1 r, IMM i));
+DECLARE_MIDFUNC(setcc(W1 d, IMM cc));
+DECLARE_MIDFUNC(setcc_m(IMM d, IMM cc));
+DECLARE_MIDFUNC(cmov_b_rr(RW1 d, R1 s, IMM cc));
+DECLARE_MIDFUNC(cmov_w_rr(RW2 d, R2 s, IMM cc));
+DECLARE_MIDFUNC(cmov_l_rr(RW4 d, R4 s, IMM cc));
+DECLARE_MIDFUNC(cmov_l_rm(RW4 d, IMM s, IMM cc));
+DECLARE_MIDFUNC(bsf_l_rr(W4 d, R4 s));
+DECLARE_MIDFUNC(pop_m(IMM d));
+DECLARE_MIDFUNC(push_m(IMM d));
+DECLARE_MIDFUNC(pop_l(W4 d));
+DECLARE_MIDFUNC(push_l_i(IMM i));
+DECLARE_MIDFUNC(push_l(R4 s));
+DECLARE_MIDFUNC(clear_16(RW4 r));
+DECLARE_MIDFUNC(clear_8(RW4 r));
+DECLARE_MIDFUNC(sign_extend_16_rr(W4 d, R2 s));
+DECLARE_MIDFUNC(sign_extend_8_rr(W4 d, R1 s));
+DECLARE_MIDFUNC(zero_extend_16_rr(W4 d, R2 s));
+DECLARE_MIDFUNC(zero_extend_8_rr(W4 d, R1 s));
+DECLARE_MIDFUNC(imul_64_32(RW4 d, RW4 s));
+DECLARE_MIDFUNC(mul_64_32(RW4 d, RW4 s));
+DECLARE_MIDFUNC(imul_32_32(RW4 d, R4 s));
+DECLARE_MIDFUNC(mul_32_32(RW4 d, R4 s));
+DECLARE_MIDFUNC(mov_b_rr(W1 d, R1 s));
+DECLARE_MIDFUNC(mov_w_rr(W2 d, R2 s));
+DECLARE_MIDFUNC(mov_l_rrm_indexed(W4 d,R4 baser, R4 index, IMM factor));
+DECLARE_MIDFUNC(mov_w_rrm_indexed(W2 d, R4 baser, R4 index, IMM factor));
+DECLARE_MIDFUNC(mov_b_rrm_indexed(W1 d, R4 baser, R4 index, IMM factor));
+DECLARE_MIDFUNC(mov_l_mrr_indexed(R4 baser, R4 index, IMM factor, R4 s));
+DECLARE_MIDFUNC(mov_w_mrr_indexed(R4 baser, R4 index, IMM factor, R2 s));
+DECLARE_MIDFUNC(mov_b_mrr_indexed(R4 baser, R4 index, IMM factor, R1 s));
+DECLARE_MIDFUNC(mov_l_bmrr_indexed(IMM base, R4 baser, R4 index, IMM factor, R4 s));
+DECLARE_MIDFUNC(mov_w_bmrr_indexed(IMM base, R4 baser, R4 index, IMM factor, R2 s));
+DECLARE_MIDFUNC(mov_b_bmrr_indexed(IMM base, R4 baser, R4 index, IMM factor, R1 s));
+DECLARE_MIDFUNC(mov_l_brrm_indexed(W4 d, IMM base, R4 baser, R4 index, IMM factor));
+DECLARE_MIDFUNC(mov_w_brrm_indexed(W2 d, IMM base, R4 baser, R4 index, IMM factor));
+DECLARE_MIDFUNC(mov_b_brrm_indexed(W1 d, IMM base, R4 baser, R4 index, IMM factor));
+DECLARE_MIDFUNC(mov_l_rm_indexed(W4 d, IMM base, R4 index, IMM factor));
+DECLARE_MIDFUNC(mov_l_rR(W4 d, R4 s, IMM offset));
+DECLARE_MIDFUNC(mov_w_rR(W2 d, R4 s, IMM offset));
+DECLARE_MIDFUNC(mov_b_rR(W1 d, R4 s, IMM offset));
+DECLARE_MIDFUNC(mov_l_brR(W4 d, R4 s, IMM offset));
+DECLARE_MIDFUNC(mov_w_brR(W2 d, R4 s, IMM offset));
+DECLARE_MIDFUNC(mov_b_brR(W1 d, R4 s, IMM offset));
+DECLARE_MIDFUNC(mov_l_Ri(R4 d, IMM i, IMM offset));
+DECLARE_MIDFUNC(mov_w_Ri(R4 d, IMM i, IMM offset));
+DECLARE_MIDFUNC(mov_b_Ri(R4 d, IMM i, IMM offset));
+DECLARE_MIDFUNC(mov_l_Rr(R4 d, R4 s, IMM offset));
+DECLARE_MIDFUNC(mov_w_Rr(R4 d, R2 s, IMM offset));
+DECLARE_MIDFUNC(mov_b_Rr(R4 d, R1 s, IMM offset));
+DECLARE_MIDFUNC(lea_l_brr(W4 d, R4 s, IMM offset));
+DECLARE_MIDFUNC(lea_l_brr_indexed(W4 d, R4 s, R4 index, IMM factor, IMM offset));
+DECLARE_MIDFUNC(lea_l_rr_indexed(W4 d, R4 s, R4 index, IMM factor));
+DECLARE_MIDFUNC(mov_l_bRr(R4 d, R4 s, IMM offset));
+DECLARE_MIDFUNC(mov_w_bRr(R4 d, R2 s, IMM offset));
+DECLARE_MIDFUNC(mov_b_bRr(R4 d, R1 s, IMM offset));
+DECLARE_MIDFUNC(bswap_32(RW4 r));
+DECLARE_MIDFUNC(bswap_16(RW2 r));
+DECLARE_MIDFUNC(mov_l_rr(W4 d, R4 s));
+DECLARE_MIDFUNC(mov_l_mr(IMM d, R4 s));
+DECLARE_MIDFUNC(mov_w_mr(IMM d, R2 s));
+DECLARE_MIDFUNC(mov_w_rm(W2 d, IMM s));
+DECLARE_MIDFUNC(mov_b_mr(IMM d, R1 s));
+DECLARE_MIDFUNC(mov_b_rm(W1 d, IMM s));
+DECLARE_MIDFUNC(mov_l_ri(W4 d, IMM s));
+DECLARE_MIDFUNC(mov_w_ri(W2 d, IMM s));
+DECLARE_MIDFUNC(mov_b_ri(W1 d, IMM s));
+DECLARE_MIDFUNC(add_l_mi(IMM d, IMM s) );
+DECLARE_MIDFUNC(add_w_mi(IMM d, IMM s) );
+DECLARE_MIDFUNC(add_b_mi(IMM d, IMM s) );
+DECLARE_MIDFUNC(test_l_ri(R4 d, IMM i));
+DECLARE_MIDFUNC(test_l_rr(R4 d, R4 s));
+DECLARE_MIDFUNC(test_w_rr(R2 d, R2 s));
+DECLARE_MIDFUNC(test_b_rr(R1 d, R1 s));
+DECLARE_MIDFUNC(and_l_ri(RW4 d, IMM i));
+DECLARE_MIDFUNC(and_l(RW4 d, R4 s));
+DECLARE_MIDFUNC(and_w(RW2 d, R2 s));
+DECLARE_MIDFUNC(and_b(RW1 d, R1 s));
+DECLARE_MIDFUNC(or_l_rm(RW4 d, IMM s));
+DECLARE_MIDFUNC(or_l_ri(RW4 d, IMM i));
+DECLARE_MIDFUNC(or_l(RW4 d, R4 s));
+DECLARE_MIDFUNC(or_w(RW2 d, R2 s));
+DECLARE_MIDFUNC(or_b(RW1 d, R1 s));
+DECLARE_MIDFUNC(adc_l(RW4 d, R4 s));
+DECLARE_MIDFUNC(adc_w(RW2 d, R2 s));
+DECLARE_MIDFUNC(adc_b(RW1 d, R1 s));
+DECLARE_MIDFUNC(add_l(RW4 d, R4 s));
+DECLARE_MIDFUNC(add_w(RW2 d, R2 s));
+DECLARE_MIDFUNC(add_b(RW1 d, R1 s));
+DECLARE_MIDFUNC(sub_l_ri(RW4 d, IMM i));
+DECLARE_MIDFUNC(sub_w_ri(RW2 d, IMM i));
+DECLARE_MIDFUNC(sub_b_ri(RW1 d, IMM i));
+DECLARE_MIDFUNC(add_l_ri(RW4 d, IMM i));
+DECLARE_MIDFUNC(add_w_ri(RW2 d, IMM i));
+DECLARE_MIDFUNC(add_b_ri(RW1 d, IMM i));
+DECLARE_MIDFUNC(sbb_l(RW4 d, R4 s));
+DECLARE_MIDFUNC(sbb_w(RW2 d, R2 s));
+DECLARE_MIDFUNC(sbb_b(RW1 d, R1 s));
+DECLARE_MIDFUNC(sub_l(RW4 d, R4 s));
+DECLARE_MIDFUNC(sub_w(RW2 d, R2 s));
+DECLARE_MIDFUNC(sub_b(RW1 d, R1 s));
+DECLARE_MIDFUNC(cmp_l(R4 d, R4 s));
+DECLARE_MIDFUNC(cmp_l_ri(R4 r, IMM i));
+DECLARE_MIDFUNC(cmp_w(R2 d, R2 s));
+DECLARE_MIDFUNC(cmp_b(R1 d, R1 s));
+DECLARE_MIDFUNC(xor_l(RW4 d, R4 s));
+DECLARE_MIDFUNC(xor_w(RW2 d, R2 s));
+DECLARE_MIDFUNC(xor_b(RW1 d, R1 s));
+DECLARE_MIDFUNC(live_flags(void));
+DECLARE_MIDFUNC(dont_care_flags(void));
+DECLARE_MIDFUNC(duplicate_carry(void));
+DECLARE_MIDFUNC(restore_carry(void));
+DECLARE_MIDFUNC(start_needflags(void));
+DECLARE_MIDFUNC(end_needflags(void));
+DECLARE_MIDFUNC(make_flags_live(void));
+DECLARE_MIDFUNC(call_r_11(R4 r, W4 out1, R4 in1, IMM osize, IMM isize));
+DECLARE_MIDFUNC(call_r_02(R4 r, R4 in1, R4 in2, IMM isize1, IMM isize2));
+DECLARE_MIDFUNC(forget_about(W4 r));
+DECLARE_MIDFUNC(nop(void));
+
+DECLARE_MIDFUNC(f_forget_about(FW r));
+DECLARE_MIDFUNC(fmov_pi(FW r));
+DECLARE_MIDFUNC(fmov_log10_2(FW r));
+DECLARE_MIDFUNC(fmov_log2_e(FW r));
+DECLARE_MIDFUNC(fmov_loge_2(FW r));
+DECLARE_MIDFUNC(fmov_1(FW r));
+DECLARE_MIDFUNC(fmov_0(FW r));
+DECLARE_MIDFUNC(fmov_rm(FW r, MEMR m));
+DECLARE_MIDFUNC(fmovi_rm(FW r, MEMR m));
+DECLARE_MIDFUNC(fmovi_mr(MEMW m, FR r));
+DECLARE_MIDFUNC(fmovs_rm(FW r, MEMR m));
+DECLARE_MIDFUNC(fmovs_mr(MEMW m, FR r));
+DECLARE_MIDFUNC(fmov_mr(MEMW m, FR r));
+DECLARE_MIDFUNC(fmov_ext_mr(MEMW m, FR r));
+DECLARE_MIDFUNC(fmov_ext_rm(FW r, MEMR m));
+DECLARE_MIDFUNC(fmov_rr(FW d, FR s));
+DECLARE_MIDFUNC(fldcw_m_indexed(R4 index, IMM base));
+DECLARE_MIDFUNC(ftst_r(FR r));
+DECLARE_MIDFUNC(dont_care_fflags(void));
+DECLARE_MIDFUNC(fsqrt_rr(FW d, FR s));
+DECLARE_MIDFUNC(fabs_rr(FW d, FR s));
+DECLARE_MIDFUNC(frndint_rr(FW d, FR s));
+DECLARE_MIDFUNC(fsin_rr(FW d, FR s));
+DECLARE_MIDFUNC(fcos_rr(FW d, FR s));
+DECLARE_MIDFUNC(ftwotox_rr(FW d, FR s));
+DECLARE_MIDFUNC(fetox_rr(FW d, FR s));
+DECLARE_MIDFUNC(flog2_rr(FW d, FR s));
+DECLARE_MIDFUNC(fneg_rr(FW d, FR s));
+DECLARE_MIDFUNC(fadd_rr(FRW d, FR s));
+DECLARE_MIDFUNC(fsub_rr(FRW d, FR s));
+DECLARE_MIDFUNC(fmul_rr(FRW d, FR s));
+DECLARE_MIDFUNC(frem_rr(FRW d, FR s));
+DECLARE_MIDFUNC(frem1_rr(FRW d, FR s));
+DECLARE_MIDFUNC(fdiv_rr(FRW d, FR s));
+DECLARE_MIDFUNC(fcmp_rr(FR d, FR s));
+DECLARE_MIDFUNC(fflags_into_flags(W2 tmp));
+#undef DECLARE_MIDFUNC
+
+extern int failure;
+#define FAIL(x) do { failure|=x; } while (0)
+
+/* Convenience functions exposed to gencomp */
+extern uae_u32 m68k_pc_offset;
+extern void readbyte(int address, int dest, int tmp);
+extern void readword(int address, int dest, int tmp);
+extern void readlong(int address, int dest, int tmp);
+extern void writebyte(int address, int source, int tmp);
+extern void writeword(int address, int source, int tmp);
+extern void writelong(int address, int source, int tmp);
+extern void writeword_clobber(int address, int source, int tmp);
+extern void writelong_clobber(int address, int source, int tmp);
+extern void get_n_addr(int address, int dest, int tmp);
+extern void get_n_addr_jmp(int address, int dest, int tmp);
+extern void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp);
+/* Set native Z flag only if register is zero */
+extern void set_zero(int r, int tmp);
+extern int kill_rodent(int r);
+extern void sync_m68k_pc(void);
+extern uae_u32 get_const(int r);
+extern int  is_const(int r);
+extern void register_branch(uae_u32 not_taken, uae_u32 taken, uae_u8 cond);
+
+#define comp_get_ibyte(o) do_get_mem_byte((uae_u8 *)(comp_pc_p + (o) + 1))
+#define comp_get_iword(o) do_get_mem_word((uae_u16 *)(comp_pc_p + (o)))
+#define comp_get_ilong(o) do_get_mem_long((uae_u32 *)(comp_pc_p + (o)))
+
+struct blockinfo_t;
+
+typedef struct dep_t {
+  uae_u32*            jmp_off;
+  struct blockinfo_t* target;
+  struct blockinfo_t* source;
+  struct dep_t**      prev_p;
+  struct dep_t*       next;
+} dependency;
+
+typedef struct checksum_info_t {
+  uae_u8 *start_p;
+  uae_u32 length;
+  struct checksum_info_t *next;
+} checksum_info;
+
+typedef struct blockinfo_t {
+    uae_s32 count;
+    cpuop_func* direct_handler_to_use;
+    cpuop_func* handler_to_use;
+    /* The direct handler does not check for the correct address */
+
+    cpuop_func* handler; 
+    cpuop_func* direct_handler;
+
+    cpuop_func* direct_pen;
+    cpuop_func* direct_pcc;
+
+    uae_u8* pc_p;
+    
+    uae_u32 c1;     
+    uae_u32 c2;
+#if USE_CHECKSUM_INFO
+    checksum_info *csi;
+#else
+    uae_u32 len;
+    uae_u32 min_pcp; 
+#endif
+
+    struct blockinfo_t* next_same_cl;
+    struct blockinfo_t** prev_same_cl_p;  
+    struct blockinfo_t* next;
+    struct blockinfo_t** prev_p; 
+
+    uae_u8 optlevel;  
+    uae_u8 needed_flags;  
+    uae_u8 status;  
+    uae_u8 havestate;
+    
+    dependency  dep[2];  /* Holds things we depend on */
+    dependency* deplist; /* List of things that depend on this */
+    smallstate  env;
+	
+#if JIT_DEBUG
+	/* (gb) size of the compiled block (direct handler) */
+	uae_u32 direct_handler_size;
+#endif
+} blockinfo;
+
+#define BI_INVALID 0
+#define BI_ACTIVE 1
+#define BI_NEED_RECOMP 2
+#define BI_NEED_CHECK 3
+#define BI_CHECKING 4
+#define BI_COMPILING 5
+#define BI_FINALIZING 6
+
+void execute_normal(void);
+void exec_nostats(void);
+void do_nothing(void);
+
+#else
+
+static __inline__ void flush_icache(int) { }
+static __inline__ void build_comp() { }
+
+#endif /* !USE_JIT */
+
+#endif /* COMPEMU_H */
diff --git a/src/cpu/jit/compemu_fpp.c b/src/cpu/jit/compemu_fpp.c
new file mode 100644
index 0000000..eb5752d
--- /dev/null
+++ b/src/cpu/jit/compemu_fpp.c
@@ -0,0 +1,1461 @@
+/*
+  * UAE - The Un*x Amiga Emulator
+  *
+  * MC68881 emulation
+  *
+  * Copyright 1996 Herman ten Brugge
+  * Adapted for JIT compilation (c) Bernd Meyer, 2000
+  * Modified 2005 Peter Keunecke
+  */
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+
+#include "options.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "ersatz.h"
+#include "md-fpp.h"
+#include "compemu.h"
+
+#if defined(JIT)
+uae_u32 temp_fp[] = { 0, 0, 0 };  /* To convert between FP and  */
+
+/* 128 words, indexed through the low byte of the 68k fpu control word */
+static const uae_u16 x86_fpucw[] = {
+	0x137f, 0x137f, 0x137f, 0x137f, 0x137f, 0x137f, 0x137f, 0x137f, /* E-RN */
+	0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, /* E-RZ */
+	0x177f, 0x177f, 0x177f, 0x177f, 0x177f, 0x177f, 0x177f, 0x177f, /* E-RD */
+	0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, /* E-RU */
+
+	0x107f, 0x107f, 0x107f, 0x107f, 0x107f, 0x107f, 0x107f, 0x107f, /* S-RN */
+	0x1c7f, 0x1c7f, 0x1c7f, 0x1c7f, 0x1c7f, 0x1c7f, 0x1c7f, 0x1c7f, /* S-RZ */
+	0x147f, 0x147f, 0x147f, 0x147f, 0x147f, 0x147f, 0x147f, 0x147f, /* S-RD */
+	0x187f, 0x187f, 0x187f, 0x187f, 0x187f, 0x187f, 0x187f, 0x187f, /* S-RU */
+
+	0x127f, 0x127f, 0x127f, 0x127f, 0x127f, 0x127f, 0x127f, 0x127f, /* D-RN */
+	0x1e7f, 0x1e7f, 0x1e7f, 0x1e7f, 0x1e7f, 0x1e7f, 0x1e7f, 0x1e7f, /* D-RZ */
+	0x167f, 0x167f, 0x167f, 0x167f, 0x167f, 0x167f, 0x167f, 0x167f, /* D-RD */
+	0x1a7f, 0x1a7f, 0x1a7f, 0x1a7f, 0x1a7f, 0x1a7f, 0x1a7f, 0x1a7f, /* D-RU */
+
+	0x137f, 0x137f, 0x137f, 0x137f, 0x137f, 0x137f, 0x137f, 0x137f, /* ?-RN */
+	0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, 0x1f7f, /* ?-RZ */
+	0x177f, 0x177f, 0x177f, 0x177f, 0x177f, 0x177f, 0x177f, 0x177f, /* ?-RD */
+	0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f, 0x1b7f  /* ?-RU */
+};
+static const int sz1[8] = { 4, 4, 12, 12, 2, 8, 1, 0 };
+static const int sz2[8] = { 4, 4, 12, 12, 2, 8, 2, 0 };
+
+static struct {
+	double b[2];
+	double w[2];
+	double l[2];
+} clamp_bounds = {
+	{ -128.0, 127.0 },
+	{ -32768.0, 32767.0 },
+	{ -2147483648.0, 2147483647.0 }
+};
+
+/* return the required floating point precision or -1 for failure, 0=E, 1=S, 2=D */
+STATIC_INLINE int comp_fp_get (uae_u32 opcode, uae_u16 extra, int treg)
+{
+	int reg = opcode & 7;
+	int mode = (opcode >> 3) & 7;
+	int size = (extra >> 10) & 7;
+
+	if (size == 3 || size == 7) /* 3 = packed decimal, 7 is not defined */
+		return -1;
+	switch (mode) {
+		case 0: /* Dn */
+		switch (size) {
+			case 0: /* Long */
+			mov_l_mr ((uae_u32) temp_fp, reg);
+			fmovi_rm (treg, (uae_u32) temp_fp);
+			return 2;
+			case 1: /* Single */
+			mov_l_mr ((uae_u32) temp_fp, reg);
+			fmovs_rm (treg, (uae_u32) temp_fp);
+			return 1;
+			case 4: /* Word */
+			sign_extend_16_rr (S1, reg);
+			mov_l_mr ((uae_u32) temp_fp, S1);
+			fmovi_rm (treg, (uae_u32) temp_fp);
+			return 1;
+			case 6: /* Byte */
+			sign_extend_8_rr (S1, reg);
+			mov_l_mr ((uae_u32) temp_fp, S1);
+			fmovi_rm (treg, (uae_u32) temp_fp);
+			return 1;
+			default:
+			return -1;
+		}
+		case 1: /* An,  invalid mode */
+		return -1;
+		case 2: /* (An) */
+		mov_l_rr (S1, reg + 8);
+		break;
+		case 3: /* (An)+ */
+		mov_l_rr (S1, reg + 8);
+		lea_l_brr (reg + 8, reg + 8, (reg == 7 ? sz2[size] : sz1[size]));
+		break;
+		case 4: /* -(An) */
+		lea_l_brr (reg + 8, reg + 8, -(reg == 7 ? sz2[size] : sz1[size]));
+		mov_l_rr (S1, reg + 8);
+		break;
+		case 5: /* (d16,An)  */
+		{
+			uae_u32 off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+			mov_l_rr (S1, reg + 8);
+			lea_l_brr (S1, S1, off);
+			break;
+		}
+		case 6: /* (d8,An,Xn) or (bd,An,Xn) or ([bd,An,Xn],od) or ([bd,An],Xn,od) */
+		{
+			uae_u32 dp = comp_get_iword ((m68k_pc_offset += 2) - 2);
+			calc_disp_ea_020 (reg + 8, dp, S1, S2);
+			break;
+		}
+		case 7:
+		switch (reg) {
+			case 0: /* (xxx).W */
+			{
+				uae_u32 off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+				mov_l_ri (S1, off);
+				break;
+			}
+			case 1: /* (xxx).L */
+			{
+				uae_u32 off = comp_get_ilong ((m68k_pc_offset += 4) - 4);
+				mov_l_ri (S1, off);
+				break;
+			}
+			case 2: /* (d16,PC) */
+			{
+				uae_u32 address = start_pc + ((uae_char*) comp_pc_p - (uae_char*) start_pc_p) +
+					m68k_pc_offset;
+				uae_s32 PC16off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+				mov_l_ri (S1, address + PC16off);
+				break;
+			}
+			case 3: /* (d8,PC,Xn) or (bd,PC,Xn) or ([bd,PC,Xn],od) or ([bd,PC],Xn,od) */
+			return -1; /* rarely used, fallback to non-JIT */
+			case 4: /* # < data >; Constants should be converted just once by the JIT */
+			m68k_pc_offset += sz2[size];
+			switch (size) {
+				case 0:
+				{
+					uae_s32 li = comp_get_ilong(m68k_pc_offset - 4);
+					float si = (float)li;
+
+					if (li == (int)si) {
+						//write_log ("converted immediate LONG constant to SINGLE\n");
+						mov_l_mi((uae_u32)temp_fp, *(uae_u32 *)&si);
+						fmovs_rm(treg, (uae_u32)temp_fp);
+						return 1;
+					}
+					//write_log ("immediate LONG constant\n");
+					mov_l_mi((uae_u32)temp_fp, *(uae_u32 *)&li);
+					fmovi_rm(treg, (uae_u32)temp_fp);
+					return 2;
+				}
+				case 1:
+				//write_log (_T("immediate SINGLE constant\n"));
+				mov_l_mi((uae_u32)temp_fp, comp_get_ilong(m68k_pc_offset - 4));
+				fmovs_rm(treg, (uae_u32)temp_fp);
+				return 1;
+				case 2:
+				//write_log (_T("immediate LONG DOUBLE constant\n"));
+				mov_l_mi((uae_u32)temp_fp, comp_get_ilong(m68k_pc_offset - 4));
+				mov_l_mi(((uae_u32)temp_fp) + 4, comp_get_ilong(m68k_pc_offset - 8));
+				mov_l_mi(((uae_u32)temp_fp) + 8, (uae_u32)comp_get_iword(m68k_pc_offset - 12));
+				fmov_ext_rm(treg, (uae_u32)temp_fp);
+				return 0;
+				case 4:
+				{
+					float si = (float)(uae_s16)comp_get_iword(m68k_pc_offset-2);
+
+					//write_log (_T("converted immediate WORD constant %f to SINGLE\n"), si);
+					mov_l_mi((uae_u32)temp_fp,*(uae_u32 *)&si);
+					fmovs_rm(treg,(uae_u32)temp_fp);
+					return 1;
+				}
+				case 5:
+				{
+					uae_u32 longarray[] = { comp_get_ilong(m68k_pc_offset - 4),
+						comp_get_ilong(m68k_pc_offset - 8) };
+					float si = (float)*(double *)longarray;
+
+					if (*(double *)longarray == (double)si) {
+						//write_log (_T("SPEED GAIN: converted a DOUBLE constant to SINGLE\n"));
+						mov_l_mi((uae_u32)temp_fp, *(uae_u32 *)&si);
+						fmovs_rm(treg, (uae_u32)temp_fp);
+						return 1;
+					}
+					//write_log (_T("immediate DOUBLE constant\n"));
+					mov_l_mi((uae_u32)temp_fp, longarray[0]);
+					mov_l_mi(((uae_u32)temp_fp) + 4, longarray[1]);
+					fmov_rm(treg, (uae_u32)temp_fp);
+					return 2;
+				}
+				case 6:
+				{
+					float si = (float)(uae_s8)comp_get_ibyte(m68k_pc_offset - 2);
+
+					//write_log (_T("converted immediate BYTE constant to SINGLE\n"));
+					mov_l_mi((uae_u32)temp_fp, *(uae_u32 *)&si);
+					fmovs_rm(treg, (uae_u32)temp_fp);
+					return 1;
+				}
+				default: /* never reached */
+				return -1;
+			}
+			default: /* never reached */
+			return -1;
+		}
+	}
+
+	switch (size) {
+		case 0: /* Long */
+		readlong (S1, S2, S3);
+		mov_l_mr ((uae_u32) temp_fp, S2);
+		fmovi_rm (treg, (uae_u32) temp_fp);
+		return 2;
+		case 1: /* Single */
+		readlong (S1, S2, S3);
+		mov_l_mr ((uae_u32) temp_fp, S2);
+		fmovs_rm (treg, (uae_u32) temp_fp);
+		return 1;
+		case 2: /* Long Double */
+		readword (S1, S2, S3);
+		mov_w_mr (((uae_u32) temp_fp) + 8, S2);
+		add_l_ri (S1, 4);
+		readlong (S1, S2, S3);
+		mov_l_mr (((uae_u32) temp_fp) + 4, S2);
+		add_l_ri (S1, 4);
+		readlong (S1, S2, S3);
+		mov_l_mr (((uae_u32) temp_fp), S2);
+		fmov_ext_rm (treg, (uae_u32) (temp_fp));
+		return 0;
+		case 4: /* Word */
+		readword (S1, S2, S3);
+		sign_extend_16_rr (S2, S2);
+		mov_l_mr ((uae_u32) temp_fp, S2);
+		fmovi_rm (treg, (uae_u32) temp_fp);
+		return 1;
+		case 5: /* Double */
+		readlong (S1, S2, S3);
+		mov_l_mr (((uae_u32) temp_fp) + 4, S2);
+		add_l_ri (S1, 4);
+		readlong (S1, S2, S3);
+		mov_l_mr (((uae_u32) temp_fp), S2);
+		fmov_rm (treg, (uae_u32) temp_fp);
+		return 2;
+		case 6: /* Byte */
+		readbyte (S1, S2, S3);
+		sign_extend_8_rr (S2, S2);
+		mov_l_mr ((uae_u32) temp_fp, S2);
+		fmovi_rm (treg, (uae_u32) temp_fp);
+		return 1;
+		default:
+		return -1;
+	}
+	return -1;
+}
+
+/* return of -1 means failure, >=0 means OK */
+STATIC_INLINE int comp_fp_put (uae_u32 opcode, uae_u16 extra)
+{
+	int reg = opcode & 7;
+	int sreg = (extra >> 7) & 7;
+	int mode = (opcode >> 3) & 7;
+	int size = (extra >> 10) & 7;
+
+	if (size == 3 || size == 7) /* 3 = packed decimal, 7 is not defined */
+		return -1;
+	switch (mode) {
+		case 0: /* Dn */
+		switch (size) {
+			case 0: /* FMOVE.L FPx, Dn */
+#if USE_X86_FPUCW && 0
+			if (!(regs.fpcr & 0xf0)) { /* if extended round to nearest */
+				mov_l_ri(S1,0x10); /* use extended round to zero mode */
+				fldcw_m_indexed(S1,(uae_u32)x86_fpucw);
+				fmovi_mrb((uae_u32)temp_fp,sreg, clamp_bounds.l);
+				mov_l_rm(reg,(uae_u32)temp_fp);
+				mov_l_rm(S1,(uae_u32)®s.fpcr);
+				and_l_ri(S1,0xf0); /* restore control word */
+				fldcw_m_indexed(S1,(uae_u32)x86_fpucw);
+				return 0;
+			}
+#endif
+			fmovi_mrb ((uae_u32) temp_fp, sreg, clamp_bounds.l);
+			mov_l_rm (reg, (uae_u32) temp_fp);
+			return 0;
+			case 1: /* FMOVE.S FPx, Dn */
+			fmovs_mr ((uae_u32) temp_fp, sreg);
+			mov_l_rm (reg, (uae_u32) temp_fp);
+			return 0;
+			case 4: /* FMOVE.W FPx, Dn */
+#if USE_X86_FPUCW && 0
+			if (!(regs.fpcr & 0xf0)) { /* if extended round to nearest */
+				mov_l_ri(S1,0x10); /* use extended round to zero mode */
+				fldcw_m_indexed(S1,(uae_u32)x86_fpucw);
+				fmovi_mrb((uae_u32)temp_fp,sreg, clamp_bounds.w);
+				mov_w_rm(reg,(uae_u32)temp_fp);
+				mov_l_rm(S1,(uae_u32)®s.fpcr);
+				and_l_ri(S1,0xf0); /* restore control word */
+				fldcw_m_indexed(S1,(uae_u32)x86_fpucw);
+				return 0;
+			}
+#endif
+			fmovi_mrb ((uae_u32) temp_fp, sreg, clamp_bounds.w);
+			mov_w_rm (reg, (uae_u32) temp_fp);
+			return 0;
+			case 6: /* FMOVE.B FPx, Dn */
+#if USE_X86_FPUCW && 0
+			if (!(regs.fpcr & 0xf0)) { /* if extended round to nearest */
+				mov_l_ri(S1,0x10); /* use extended round to zero mode */
+				fldcw_m_indexed(S1,(uae_u32)x86_fpucw);
+				fmovi_mrb((uae_u32)temp_fp,sreg, clamp_bounds.b);
+				mov_b_rm(reg,(uae_u32)temp_fp);
+				mov_l_rm(S1,(uae_u32)®s.fpcr);
+				and_l_ri(S1,0xf0); /* restore control word */
+				fldcw_m_indexed(S1,(uae_u32)x86_fpucw);
+				return 0;
+			}
+#endif
+			fmovi_mrb ((uae_u32) temp_fp, sreg, clamp_bounds.b);
+			mov_b_rm (reg, (uae_u32) temp_fp);
+			return 0;
+			default:
+			return -1;
+		}
+		case 1: /* An, invalid mode */
+		return -1;
+		case 2: /* (An) */
+		mov_l_rr (S1, reg + 8);
+		break;
+		case 3: /* (An)+ */
+		mov_l_rr (S1, reg + 8);
+		lea_l_brr (reg + 8, reg + 8, (reg == 7 ? sz2[size] : sz1[size]));
+		break;
+		case 4: /* -(An) */
+		lea_l_brr (reg + 8, reg + 8, -(reg == 7 ? sz2[size] : sz1[size]));
+		mov_l_rr (S1, reg + 8);
+		break;
+		case 5: /* (d16,An) */
+		{
+			uae_u32 off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+			mov_l_rr (S1, reg + 8);
+			add_l_ri (S1, off);
+			break;
+		}
+		case 6: /* (d8,An,Xn) or (bd,An,Xn) or ([bd,An,Xn],od) or ([bd,An],Xn,od) */
+		{
+			uae_u32 dp = comp_get_iword ((m68k_pc_offset += 2) - 2);
+			calc_disp_ea_020 (reg + 8, dp, S1, S2);
+			break;
+		}
+		case 7:
+		switch (reg) {
+			case 0: /* (xxx).W */
+			{
+				uae_u32 off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+				mov_l_ri (S1, off);
+				break;
+			}
+			case 1: /* (xxx).L */
+			{
+				uae_u32 off = comp_get_ilong ((m68k_pc_offset += 4) - 4);
+				mov_l_ri (S1, off);
+				break;
+			}
+			default: /* All other modes are not allowed for FPx to  */
+			write_log (_T ("JIT FMOVE FPx, Mode is not allowed %04x %04x\n"), opcode, extra);
+			return -1;
+		}
+	}
+	switch (size) {
+		case 0: /* Long */
+		fmovi_mrb ((uae_u32) temp_fp, sreg, clamp_bounds.l);
+		mov_l_rm (S2, (uae_u32) temp_fp);
+		writelong_clobber (S1, S2, S3);
+		return 0;
+		case 1: /* Single */
+		fmovs_mr ((uae_u32) temp_fp, sreg);
+		mov_l_rm (S2, (uae_u32) temp_fp);
+		writelong_clobber (S1, S2, S3);
+		return 0;
+		case 2:/* Long Double */
+		fmov_ext_mr ((uae_u32) temp_fp, sreg);
+		mov_w_rm (S2, (uae_u32) temp_fp + 8);
+		writeword_clobber (S1, S2, S3);
+		add_l_ri (S1, 4);
+		mov_l_rm (S2, (uae_u32) temp_fp + 4);
+		writelong_clobber (S1, S2, S3);
+		add_l_ri (S1, 4);
+		mov_l_rm (S2, (uae_u32) temp_fp);
+		writelong_clobber (S1, S2, S3);
+		return 0;
+		case 4: /* Word */
+		fmovi_mrb ((uae_u32) temp_fp, sreg, clamp_bounds.w);
+		mov_l_rm (S2, (uae_u32) temp_fp);
+		writeword_clobber (S1, S2, S3);
+		return 0;
+		case 5: /* Double */
+		fmov_mr ((uae_u32) temp_fp, sreg);
+		mov_l_rm (S2, (uae_u32) temp_fp + 4);
+		writelong_clobber (S1, S2, S3);
+		add_l_ri (S1, 4);
+		mov_l_rm (S2, (uae_u32) temp_fp);
+		writelong_clobber (S1, S2, S3);
+		return 0;
+		case 6: /* Byte */
+		fmovi_mrb ((uae_u32) temp_fp, sreg, clamp_bounds.b);
+		mov_l_rm (S2, (uae_u32) temp_fp);
+		writebyte (S1, S2, S3);
+		return 0;
+		default:
+		return -1;
+	}
+	return -1;
+}
+
+/* return -1 for failure, or register number for success */
+STATIC_INLINE int comp_fp_adr (uae_u32 opcode)
+{
+	uae_s32 off;
+	int mode = (opcode >> 3) & 7;
+	int reg = opcode & 7;
+
+	switch (mode) {
+		case 2:
+		case 3:
+		case 4:
+		mov_l_rr (S1, 8 + reg);
+		return S1;
+		case 5:
+		off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+		mov_l_rr (S1, 8 + reg);
+		add_l_ri (S1, off);
+		return S1;
+		case 7:
+		switch (reg) {
+			case 0:
+			off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+			mov_l_ri (S1, off);
+			return S1;
+			case 1:
+			off = comp_get_ilong ((m68k_pc_offset += 4) - 4);
+			mov_l_ri (S1, off);
+			return S1;
+		}
+		default:
+		return -1;
+	}
+}
+
+void comp_fdbcc_opp (uae_u32 opcode, uae_u16 extra)
+{
+	FAIL (1);
+	return;
+}
+
+void comp_fscc_opp (uae_u32 opcode, uae_u16 extra)
+{
+	int reg;
+
+	if (!currprefs.compfpu) {
+		FAIL (1);
+		return;
+	}
+
+#if DEBUG_FPP
+	write_log (_T("JIT: fscc_opp at %08lx\n"), M68K_GETPC);
+#endif
+
+	if (extra & 0x20) {  /* only cc from 00 to 1f are defined */
+		FAIL (1);
+		return;
+	}
+	if ((opcode & 0x38) != 0) { /* We can only do to integer register */
+		FAIL (1);
+		return;
+	}
+
+	fflags_into_flags (S2);
+	reg = (opcode & 7);
+
+	mov_l_ri (S1, 255);
+	mov_l_ri (S4, 0);
+	switch (extra & 0x0f) { /* according to fpp.c, the 0x10 bit is ignored */
+		case 0: break;  /* set never */
+		case 1: mov_l_rr (S2, S4);
+			cmov_l_rr (S4, S1, 4);
+			cmov_l_rr (S4, S2, 10); break;
+		case 2: cmov_l_rr (S4, S1, 7); break;
+		case 3: cmov_l_rr (S4, S1, 3); break;
+		case 4: mov_l_rr (S2, S4);
+			cmov_l_rr (S4, S1, 2);
+			cmov_l_rr (S4, S2, 10); break;
+		case 5: mov_l_rr (S2, S4);
+			cmov_l_rr (S4, S1, 6);
+			cmov_l_rr (S4, S2, 10); break;
+		case 6: cmov_l_rr (S4, S1, 5); break;
+		case 7: cmov_l_rr (S4, S1, 11); break;
+		case 8: cmov_l_rr (S4, S1, 10); break;
+		case 9: cmov_l_rr (S4, S1, 4); break;
+		case 10: cmov_l_rr (S4, S1, 10); cmov_l_rr (S4, S1, 7); break;
+		case 11: cmov_l_rr (S4, S1, 4); cmov_l_rr (S4, S1, 3); break;
+		case 12: cmov_l_rr (S4, S1, 2); break;
+		case 13: cmov_l_rr (S4, S1, 6); break;
+		case 14: cmov_l_rr (S4, S1, 5); cmov_l_rr (S4, S1, 10); break;
+		case 15: mov_l_rr (S4, S1); break;
+	}
+
+	if (!(opcode & 0x38))
+		mov_b_rr (reg, S4);
+#if 0
+	else {
+		abort();
+		if (!comp_fp_adr (opcode)) {
+			m68k_setpc (m68k_getpc () - 4);
+			op_illg (opcode);
+		}
+		else
+			put_byte (ad, cc ? 0xff : 0x00);
+	}
+#endif
+}
+
+void comp_ftrapcc_opp (uae_u32 opcode, uaecptr oldpc)
+{
+	FAIL (1);
+	return;
+}
+
+extern unsigned long foink3, oink;
+
+void comp_fbcc_opp (uae_u32 opcode)
+{
+	uae_u32 start_68k_offset = m68k_pc_offset;
+	uae_u32 off, v1, v2;
+	int cc;
+
+	if (!currprefs.compfpu) {
+		FAIL (1);
+		return;
+	}
+
+	if (opcode & 0x20) {  /* only cc from 00 to 1f are defined */
+		FAIL (1);
+		return;
+	}
+	if (!(opcode & 0x40)) {
+		off = (uae_s32) (uae_s16) comp_get_iword ((m68k_pc_offset += 2) - 2);
+	}
+	else {
+		off = comp_get_ilong ((m68k_pc_offset += 4) - 4);
+	}
+	mov_l_ri (S1, (uae_u32)
+			  (comp_pc_p + off - (m68k_pc_offset - start_68k_offset)));
+	mov_l_ri (PC_P, (uae_u32) comp_pc_p);
+
+	/* Now they are both constant. Might as well fold in m68k_pc_offset */
+	add_l_ri (S1, m68k_pc_offset);
+	add_l_ri (PC_P, m68k_pc_offset);
+	m68k_pc_offset = 0;
+
+	/* according to fpp.c, the 0x10 bit is ignored
+	   (it handles exception handling, which we don't
+	   do, anyway ;-) */
+	cc = opcode & 0x0f;
+	v1 = get_const (PC_P);
+	v2 = get_const (S1);
+	fflags_into_flags (S2);
+
+	// mov_l_mi((uae_u32)&foink3,cc);
+	switch (cc) {
+		case 0: break;  /* jump never */
+		case 1:
+		mov_l_rr (S2, PC_P);
+		cmov_l_rr (PC_P, S1, 4);
+		cmov_l_rr (PC_P, S2, 10); break;
+		case 2: register_branch (v1, v2, 7); break;
+		case 3: register_branch (v1, v2, 3); break;
+		case 4:
+		mov_l_rr (S2, PC_P);
+		cmov_l_rr (PC_P, S1, 2);
+		cmov_l_rr (PC_P, S2, 10); break;
+		case 5:
+		mov_l_rr (S2, PC_P);
+		cmov_l_rr (PC_P, S1, 6);
+		cmov_l_rr (PC_P, S2, 10); break;
+		case 6: register_branch (v1, v2, 5); break;
+		case 7: register_branch (v1, v2, 11); break;
+		case 8: register_branch (v1, v2, 10); break;
+		case 9: register_branch (v1, v2, 4); break;
+		case 10:
+		cmov_l_rr (PC_P, S1, 10);
+		cmov_l_rr (PC_P, S1, 7); break;
+		case 11:
+		cmov_l_rr (PC_P, S1, 4);
+		cmov_l_rr (PC_P, S1, 3); break;
+		case 12: register_branch (v1, v2, 2); break;
+		case 13: register_branch (v1, v2, 6); break;
+		case 14:
+		cmov_l_rr (PC_P, S1, 5);
+		cmov_l_rr (PC_P, S1, 10); break;
+		case 15: mov_l_rr (PC_P, S1); break;
+	}
+}
+
+/* Floating point conditions
+   The "NotANumber" part could be problematic; Howver, when NaN is
+   encountered, the ftst instruction sets bot N and Z to 1 on the x87,
+   so quite often things just fall into place. This is probably not
+   accurate wrt the 68k FPU, but it is *as* accurate as this was before.
+   However, some more thought should go into fixing this stuff up so
+   it accurately emulates the 68k FPU.
+   >==> 7) & 7;
+	int source = (extra >> 13) & 7;
+	int	opmode = extra & 0x7f;
+
+	if (!currprefs.compfpu) {
+		FAIL (1);
+		return;
+	}
+	switch (source) {
+		case 3: /* FMOVE FPx,  */
+		if (comp_fp_put (opcode, extra) < 0)
+			FAIL (1);
+		return;
+		case 4: /* FMOVE.L  , ControlReg */
+		if (!(opcode & 0x30)) { /* Dn or An */
+			if (extra & 0x1000) { /* FPCR */
+				mov_l_mr ((uae_u32) ®s.fpcr, opcode & 15);
+#if USE_X86_FPUCW
+				mov_l_rr (S1, opcode & 15);
+				and_l_ri (S1, 0xf0);
+				fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+#endif
+				return;
+			}
+			if (extra & 0x0800) { /* FPSR */
+				FAIL (1);
+				return;
+				// set_fpsr(m68k_dreg (regs, opcode & 15));
+			}
+			if (extra & 0x0400) { /* FPIAR */
+				mov_l_mr ((uae_u32) ®s.fpiar, opcode & 15); return;
+			}
+		}
+		else if ((opcode & 0x3f) == 0x3c) {
+			if (extra & 0x1000) { /* FPCR */
+				uae_u32 val = comp_get_ilong ((m68k_pc_offset += 4) - 4);
+				mov_l_mi ((uae_u32) ®s.fpcr, val);
+#if USE_X86_FPUCW
+				mov_l_ri (S1, val & 0xf0);
+				fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+#endif
+				return;
+			}
+			if (extra & 0x0800) { /* FPSR */
+				FAIL (1);
+				return;
+			}
+			if (extra & 0x0400) { /* FPIAR */
+				uae_u32 val = comp_get_ilong ((m68k_pc_offset += 4) - 4);
+				mov_l_mi ((uae_u32) ®s.fpiar, val);
+				return;
+			}
+		}
+		FAIL (1);
+		return;
+		case 5: /* FMOVE.L  ControlReg,  */
+		if (!(opcode & 0x30)) { /* Dn or An */
+			if (extra & 0x1000) { /* FPCR */
+				mov_l_rm (opcode & 15, (uae_u32) ®s.fpcr); return;
+			}
+			if (extra & 0x0800) { /* FPSR */
+				FAIL (1);
+				return;
+			}
+			if (extra & 0x0400) { /* FPIAR */
+				mov_l_rm (opcode & 15, (uae_u32) ®s.fpiar); return;
+			}
+		}
+		FAIL (1);
+		return;
+		case 6:
+		case 7:
+		{
+			uae_u32 list = 0;
+			int incr = 0;
+			if (extra & 0x2000) {
+				int ad;
+
+				/* FMOVEM FPP->memory */
+				switch ((extra >> 11) & 3) { /* Get out early if failure */
+					case 0:
+					case 2:
+					break;
+					case 1:
+					case 3:
+					default:
+					FAIL (1); return;
+				}
+				ad = comp_fp_adr (opcode);
+				if (ad < 0) {
+					m68k_setpc (m68k_getpc () - 4);
+					op_illg (opcode);
+					return;
+				}
+				switch ((extra >> 11) & 3) {
+					case 0:	/* static pred */
+					list = extra & 0xff;
+					incr = -1;
+					break;
+					case 2:	/* static postinc */
+					list = extra & 0xff;
+					incr = 1;
+					break;
+					case 1:	/* dynamic pred */
+					case 3:	/* dynamic postinc */
+					abort ();
+				}
+				if (incr < 0) { /* Predecrement */
+					for (reg = 7; reg >= 0; reg--) {
+						if (list & 0x80) {
+							fmov_ext_mr ((uintptr) temp_fp, reg);
+							sub_l_ri (ad, 4);
+							mov_l_rm (S2, (uintptr) temp_fp);
+							writelong_clobber (ad, S2, S3);
+							sub_l_ri (ad, 4);
+							mov_l_rm (S2, (uintptr) temp_fp + 4);
+							writelong_clobber (ad, S2, S3);
+							sub_l_ri (ad, 4);
+							mov_w_rm (S2, (uintptr) temp_fp + 8);
+							writeword_clobber (ad, S2, S3);
+						}
+						list <<= 1;
+					}
+				} else { /* Postincrement */
+					for (reg = 0; reg <= 7; reg++) {
+						if (list & 0x80) {
+							fmov_ext_mr ((uintptr) temp_fp, reg);
+							mov_w_rm (S2, (uintptr) temp_fp + 8);
+							writeword_clobber (ad, S2, S3);
+							add_l_ri (ad, 4);
+							mov_l_rm (S2, (uintptr) temp_fp + 4);
+							writelong_clobber (ad, S2, S3);
+							add_l_ri (ad, 4);
+							mov_l_rm (S2, (uintptr) temp_fp);
+							writelong_clobber (ad, S2, S3);
+							add_l_ri (ad, 4);
+						}
+						list <<= 1;
+					}
+				}
+				if ((opcode & 0x38) == 0x18)
+					mov_l_rr ((opcode & 7) + 8, ad);
+				if ((opcode & 0x38) == 0x20)
+					mov_l_rr ((opcode & 7) + 8, ad);
+			} else {
+				/* FMOVEM memory->FPP */
+
+				int ad;
+				switch ((extra >> 11) & 3) { /* Get out early if failure */
+					case 0:
+					case 2:
+					break;
+					case 1:
+					case 3:
+					default:
+					FAIL (1); return;
+				}
+				ad = comp_fp_adr (opcode);
+				if (ad < 0) {
+					m68k_setpc (m68k_getpc () - 4);
+					op_illg (opcode);
+					return;
+				}
+				switch ((extra >> 11) & 3) {
+					case 0:	/* static pred */
+					list = extra & 0xff;
+					incr = -1;
+					break;
+					case 2:	/* static postinc */
+					list = extra & 0xff;
+					incr = 1;
+					break;
+					case 1:	/* dynamic pred */
+					case 3:	/* dynamic postinc */
+					abort ();
+				}
+
+				if (incr < 0) {
+					// not reached
+					for (reg = 7; reg >= 0; reg--) {
+						if (list & 0x80) {
+							sub_l_ri (ad, 4);
+							readlong (ad, S2, S3);
+							mov_l_mr ((uintptr) (temp_fp), S2);
+							sub_l_ri (ad, 4);
+							readlong (ad, S2, S3);
+							mov_l_mr ((uintptr) (temp_fp) +4, S2);
+							sub_l_ri (ad, 4);
+							readword (ad, S2, S3);
+							mov_w_mr (((uintptr) temp_fp) + 8, S2);
+							fmov_ext_rm (reg, (uintptr) (temp_fp));
+						}
+						list <<= 1;
+					}
+				} else {
+					for (reg = 0; reg <= 7; reg++) {
+						if (list & 0x80) {
+							readword (ad, S2, S3);
+							mov_w_mr (((uintptr) temp_fp) + 8, S2);
+							add_l_ri (ad, 4);
+							readlong (ad, S2, S3);
+							mov_l_mr ((uintptr) (temp_fp) +4, S2);
+							add_l_ri (ad, 4);
+							readlong (ad, S2, S3);
+							mov_l_mr ((uintptr) (temp_fp), S2);
+							add_l_ri (ad, 4);
+							fmov_ext_rm (reg, (uintptr) (temp_fp));
+						}
+						list <<= 1;
+					}
+				}
+				if ((opcode & 0x38) == 0x18)
+					mov_l_rr ((opcode & 7) + 8, ad);
+				if ((opcode & 0x38) == 0x20)
+					mov_l_rr ((opcode & 7) + 8, ad);
+			}
+		}
+		return;
+#if 0
+		case 6: /* FMOVEM  , FPx-FPz */
+		if (!(extra & 0x0800)) {
+			uae_u32 list = extra & 0xff;
+			int ad;
+			if ((ad = comp_fp_adr(opcode)) < 0) {FAIL(1);return;}
+			while (list) {
+				if  (extra & 0x1000) { /* postincrement */
+					readword(ad,S2,S3);
+					mov_w_mr(((uae_u32)temp_fp)+8,S2);
+					add_l_ri(ad,4);
+					readlong(ad,S2,S3);
+					mov_l_mr((uae_u32)(temp_fp)+4,S2);
+					add_l_ri(ad,4);
+					readlong(ad,S2,S3);
+					mov_l_mr((uae_u32)(temp_fp),S2);
+					add_l_ri(ad,4);
+					fmov_ext_rm(fpp_movem_index1[list],(uae_u32)(temp_fp));
+				} else { /* predecrement */
+					sub_l_ri(ad,4);
+					readlong(ad,S2,S3);
+					mov_l_mr((uae_u32)(temp_fp),S2);
+					sub_l_ri(ad,4);
+					readlong(ad,S2,S3);
+					mov_l_mr((uae_u32)(temp_fp)+4,S2);
+					sub_l_ri(ad,4);
+					readword(ad,S2,S3);
+					mov_w_mr(((uae_u32)temp_fp)+8,S2);
+					fmov_ext_rm(fpp_movem_index2[list],(uae_u32)(temp_fp));
+				}
+				list = fpp_movem_next[list];
+			}
+			if ((opcode & 0x38) == 0x18)
+				mov_l_rr((opcode & 7)+8,ad);
+			return;
+		} /* no break for dynamic register list */
+		case 7: /* FMOVEM  FPx-FPz,  */
+		if (!(extra & 0x0800)) {
+			uae_u32 list = extra & 0xff;
+			int ad;
+			if ((ad = comp_fp_adr(opcode)) < 0) {FAIL(1);return;}
+			while (list) {
+				if (extra & 0x1000) { /* postincrement */
+					fmov_ext_mr((uae_u32)temp_fp,fpp_movem_index2[list]);
+					mov_w_rm(S2,(uae_u32)temp_fp+8);
+					writeword_clobber(ad,S2,S3);
+					add_l_ri(ad,4);
+					mov_l_rm(S2,(uae_u32)temp_fp+4);
+					writelong_clobber(ad,S2,S3);
+					add_l_ri(ad,4);
+					mov_l_rm(S2,(uae_u32)temp_fp);
+					writelong_clobber(ad,S2,S3);
+					add_l_ri(ad,4);
+				} else { /* predecrement */
+					fmov_ext_mr((uae_u32)temp_fp,fpp_movem_index2[list]);
+					sub_l_ri(ad,4);
+					mov_l_rm(S2,(uae_u32)temp_fp);
+					writelong_clobber(ad,S2,S3);
+					sub_l_ri(ad,4);
+					mov_l_rm(S2,(uae_u32)temp_fp+4);
+					writelong_clobber(ad,S2,S3);
+					sub_l_ri(ad,4);
+					mov_w_rm(S2,(uae_u32)temp_fp+8);
+					writeword_clobber(ad,S2,S3);
+				}
+				list = fpp_movem_next[list];
+			}
+			if ((opcode & 0x38) == 0x20)
+				mov_l_rr((opcode & 7)+8,ad);
+			return;
+		} /* no break */
+		write_log (_T("fallback from JIT FMOVEM dynamic register list\n"));
+		FAIL(1);
+		return;
+#endif
+		case 2: /* from  to FPx */
+		dont_care_fflags ();
+		if ((extra & 0xfc00) == 0x5c00) { /* FMOVECR */
+			//write_log (_T("JIT FMOVECR %x\n"), opmode);
+			switch (opmode) {
+				case 0x00:
+				fmov_pi (dreg);
+				break;
+				case 0x0b:
+				fmov_ext_rm (dreg, (uae_u32) &xhex_l10_2);
+				break;
+				case 0x0c:
+				fmov_ext_rm (dreg, (uae_u32) &xhex_exp_1);
+				break;
+				case 0x0d:
+				fmov_log2_e (dreg);
+				break;
+				case 0x0e:
+				fmov_ext_rm (dreg, (uae_u32) &xhex_l10_e);
+				break;
+				case 0x0f:
+				fmov_0 (dreg);
+				break;
+				case 0x30:
+				fmov_loge_2 (dreg);
+				break;
+				case 0x31:
+				fmov_ext_rm (dreg, (uae_u32) &xhex_ln_10);
+				break;
+				case 0x32:
+				fmov_1 (dreg);
+				break;
+				case 0x33:
+				fmovs_rm (dreg, (uae_u32) &fp_1e1);
+				break;
+				case 0x34:
+				fmovs_rm (dreg, (uae_u32) &fp_1e2);
+				break;
+				case 0x35:
+				fmovs_rm (dreg, (uae_u32) &fp_1e4);
+				break;
+				case 0x36:
+				fmov_rm (dreg, (uae_u32) &fp_1e8);
+				break;
+				case 0x37:
+				fmov_ext_rm (dreg, (uae_u32) &xhex_1e16);
+				break;
+				case 0x38:
+				fmov_ext_rm (dreg, (uae_u32) &xhex_1e32);
+				break;
+				case 0x39:
+				fmov_ext_rm (dreg, (uae_u32) &xhex_1e64);
+				break;
+				case 0x3a:
+				fmov_ext_rm (dreg, (uae_u32) &xhex_1e128);
+				break;
+				case 0x3b:
+				fmov_ext_rm (dreg, (uae_u32) &xhex_1e256);
+				break;
+				case 0x3c:
+				fmov_ext_rm (dreg, (uae_u32) &xhex_1e512);
+				break;
+				case 0x3d:
+				fmov_ext_rm (dreg, (uae_u32) &xhex_1e1024);
+				break;
+				case 0x3e:
+				fmov_ext_rm (dreg, (uae_u32) &xhex_1e2048);
+				break;
+				case 0x3f:
+				fmov_ext_rm (dreg, (uae_u32) &xhex_1e4096);
+				break;
+				default:
+				FAIL (1);
+				return;
+			}
+			fmov_rr (FP_RESULT, dreg);
+			return;
+		}
+		if (opmode & 0x20) /* two operands, so we need a scratch reg */
+			sreg = FS1;
+		else /* one operand only, thus we can load the argument into dreg */
+			sreg = dreg;
+		if ((prec = comp_fp_get (opcode, extra, sreg)) < 0) {
+			FAIL (1);
+			return;
+		}
+		if (!opmode) { /* FMOVE  ,FPx */
+			fmov_rr (FP_RESULT, dreg);
+			return;
+		}
+		/* no break here for  to dreg */
+		case 0: /* directly from sreg to dreg */
+		if (!source) { /* no  */
+			dont_care_fflags ();
+			sreg = (extra >> 10) & 7;
+		}
+		switch (opmode) {
+			case 0x00: /* FMOVE */
+			fmov_rr (dreg, sreg);
+			break;
+			case 0x01: /* FINT */
+			frndint_rr (dreg, sreg);
+			break;
+			case 0x02: /* FSINH */
+			fsinh_rr (dreg, sreg);
+			break;
+			case 0x03: /* FINTRZ */
+#if USE_X86_FPUCW /* if we have control over the CW, we can do this */
+			if (0 && (regs.fpcr & 0xf0) == 0x10) /* maybe unsafe, because this test is done */
+				frndint_rr (dreg, sreg); /* during the JIT compilation and not at runtime */
+			else {
+				mov_l_ri (S1, 0x10); /* extended round to zero */
+				fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+				frndint_rr (dreg, sreg);
+				mov_l_rm (S1, (uae_u32) ®s.fpcr);
+				and_l_ri (S1, 0xf0); /* restore control word */
+				fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+			}
+			break;
+#endif
+			FAIL (1);
+			return;
+			case 0x04: /* FSQRT */
+			fsqrt_rr (dreg, sreg);
+			break;
+			case 0x06: /* FLOGNP1 */
+			flogNP1_rr (dreg, sreg);
+			break;
+			case 0x08: /* FETOXM1 */
+			fetoxM1_rr (dreg, sreg);
+			break;
+			case 0x09: /* FTANH */
+			ftanh_rr (dreg, sreg);
+			break;
+			case 0x0a: /* FATAN */
+			fatan_rr (dreg, sreg);
+			break;
+			case 0x0c: /* FASIN */
+			fasin_rr (dreg, sreg);
+			break;
+			case 0x0d: /* FATANH */
+			fatanh_rr (dreg, sreg);
+			break;
+			case 0x0e: /* FSIN */
+			fsin_rr (dreg, sreg);
+			break;
+			case 0x0f: /* FTAN */
+			ftan_rr (dreg, sreg);
+			break;
+			case 0x10: /* FETOX */
+			fetox_rr (dreg, sreg);
+			break;
+			case 0x11: /* FTWOTOX */
+			ftwotox_rr (dreg, sreg);
+			break;
+			case 0x12: /* FTENTOX */
+			ftentox_rr (dreg, sreg);
+			break;
+			case 0x14: /* FLOGN */
+			flogN_rr (dreg, sreg);
+			break;
+			case 0x15: /* FLOG10 */
+			flog10_rr (dreg, sreg);
+			break;
+			case 0x16: /* FLOG2 */
+			flog2_rr (dreg, sreg);
+			break;
+			case 0x18: /* FABS */
+			fabs_rr (dreg, sreg);
+			break;
+			case 0x19: /* FCOSH */
+			fcosh_rr (dreg, sreg);
+			break;
+			case 0x1a: /* FNEG */
+			fneg_rr (dreg, sreg);
+			break;
+			case 0x1c: /* FACOS */
+#if USE_X86_FPUCW
+			if ((regs.fpcr & 0x30) != 0x10) { /* use round to zero */
+				mov_l_ri (S1, (regs.fpcr & 0xC0) | 0x10);
+				fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+				facos_rr (dreg, sreg);
+				mov_l_rm (S1, (uae_u32) ®s.fpcr);
+				and_l_ri (S1, 0xf0); /* restore control word */
+				fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+				break;
+			}
+#endif
+			facos_rr (dreg, sreg);
+			break;
+			case 0x1d: /* FCOS */
+			fcos_rr (dreg, sreg);
+			break;
+			case 0x1e: /* FGETEXP */
+			fgetexp_rr (dreg, sreg);
+			break;
+			case 0x1f: /* FGETMAN */
+			fgetman_rr (dreg, sreg);
+			break;
+			case 0x20: /* FDIV */
+			fdiv_rr (dreg, sreg);
+			break;
+			case 0x21: /* FMOD */
+			frem_rr (dreg, sreg);
+			break;
+			case 0x22: /* FADD */
+			fadd_rr (dreg, sreg);
+			break;
+			case 0x23: /* FMUL */
+			fmul_rr (dreg, sreg);
+			break;
+			case 0x24: /* FSGLDIV  is not exactly the same as FSDIV, */
+			/* because both operands should be SINGLE precision, too */
+			case 0x60: /* FSDIV */
+			fdiv_rr (dreg, sreg);
+			if (!currprefs.fpu_strict) /* faster, but less strict rounding */
+				break;
+#if USE_X86_FPUCW
+			if ((regs.fpcr & 0xC0) == 0x40) /* if SINGLE precision */
+				break;
+#endif
+			fcuts_r (dreg);
+			break;
+			case 0x25: /* FREM */
+			frem1_rr (dreg, sreg);
+			break;
+			case 0x26: /* FSCALE */
+			fscale_rr (dreg, sreg);
+			break;
+			case 0x27: /* FSGLMUL is not exactly the same as FSMUL, */
+			/* because both operands should be SINGLE precision, too */
+			case 0x63: /* FSMUL */
+			fmul_rr (dreg, sreg);
+			if (!currprefs.fpu_strict) /* faster, but less strict rounding */
+				break;
+#if USE_X86_FPUCW
+			if ((regs.fpcr & 0xC0) == 0x40) /* if SINGLE precision */
+				break;
+#endif
+			fcuts_r (dreg);
+			break;
+			case 0x28: /* FSUB */
+			fsub_rr (dreg, sreg);
+			break;
+			case 0x30: /* FSINCOS */
+			case 0x31:
+			case 0x32:
+			case 0x33:
+			case 0x34:
+			case 0x35:
+			case 0x36:
+			case 0x37:
+			if (dreg == (extra & 7))
+				fsin_rr (dreg, sreg);
+			else
+				fsincos_rr (dreg, extra & 7, sreg);
+			break;
+			case 0x38: /* FCMP */
+			fmov_rr (FP_RESULT, dreg);
+			fsub_rr (FP_RESULT, sreg);
+			return;
+			case 0x3a: /* FTST */
+			fmov_rr (FP_RESULT, sreg);
+			return;
+			case 0x40: /* FSMOVE */
+			if (prec == 1 || !currprefs.fpu_strict) {
+				if (sreg != dreg) /* no  */
+					fmov_rr (dreg, sreg);
+			}
+			else {
+				fmovs_mr ((uae_u32) temp_fp, sreg);
+				fmovs_rm (dreg, (uae_u32) temp_fp);
+			}
+			break;
+			case 0x44: /* FDMOVE */
+			if (prec || !currprefs.fpu_strict) {
+				if (sreg != dreg) /* no  */
+					fmov_rr (dreg, sreg);
+			}
+			else {
+				fmov_mr ((uae_u32) temp_fp, sreg);
+				fmov_rm (dreg, (uae_u32) temp_fp);
+			}
+			break;
+			case 0x41: /* FSSQRT */
+			fsqrt_rr (dreg, sreg);
+			if (!currprefs.fpu_strict) /* faster, but less strict rounding */
+				break;
+#if USE_X86_FPUCW
+			if ((regs.fpcr & 0xC0) == 0x40) /* if SINGLE precision */
+				break;
+#endif
+			fcuts_r (dreg);
+			break;
+			case 0x45: /* FDSQRT */
+			if (!currprefs.fpu_strict) { /* faster, but less strict rounding */
+				fsqrt_rr (dreg, sreg);
+				break;
+			}
+#if USE_X86_FPUCW
+			if (regs.fpcr & 0xC0) { /* if we don't have EXTENDED precision */
+				if ((regs.fpcr & 0xC0) == 0x80) /* if we have DOUBLE */
+					fsqrt_rr (dreg, sreg);
+				else { /* if we have SINGLE presision, force DOUBLE */
+					mov_l_ri (S1, (regs.fpcr & 0x30) | 0x80);
+					fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+					fsqrt_rr (dreg, sreg);
+					mov_l_rm (S1, (uae_u32) ®s.fpcr);
+					and_l_ri (S1, 0xf0); /* restore control word */
+					fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+				}
+				break;
+			}
+#endif		/* in case of EXTENDED precision, just reduce the result to DOUBLE */
+			fsqrt_rr (dreg, sreg);
+			fcut_r (dreg);
+			break;
+			case 0x58: /* FSABS */
+			fabs_rr (dreg, sreg);
+			if (prec != 1 && currprefs.fpu_strict)
+				fcuts_r (dreg);
+			break;
+			case 0x5a: /* FSNEG */
+			fneg_rr (dreg, sreg);
+			if (prec != 1 && currprefs.fpu_strict)
+				fcuts_r (dreg);
+			break;
+			case 0x5c: /* FDABS */
+			fabs_rr (dreg, sreg);
+			if (!prec && currprefs.fpu_strict)
+				fcut_r (dreg);
+			break;
+			case 0x5e: /* FDNEG */
+			fneg_rr (dreg, sreg);
+			if (!prec && currprefs.fpu_strict)
+				fcut_r (dreg);
+			break;
+			case 0x62: /* FSADD */
+			fadd_rr (dreg, sreg);
+			if (!currprefs.fpu_strict) /* faster, but less strict rounding */
+				break;
+#if USE_X86_FPUCW
+			if ((regs.fpcr & 0xC0) == 0x40) /* if SINGLE precision */
+				break;
+#endif
+			fcuts_r (dreg);
+			break;
+			case 0x64: /* FDDIV */
+			if (!currprefs.fpu_strict) { /* faster, but less strict rounding */
+				fdiv_rr (dreg, sreg);
+				break;
+			}
+#if USE_X86_FPUCW
+			if (regs.fpcr & 0xC0) { /* if we don't have EXTENDED precision */
+				if ((regs.fpcr & 0xC0) == 0x80) /* if we have DOUBLE */
+					fdiv_rr (dreg, sreg);
+				else { /* if we have SINGLE presision, force DOUBLE */
+					mov_l_ri (S1, (regs.fpcr & 0x30) | 0x80);
+					fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+					fdiv_rr (dreg, sreg);
+					mov_l_rm (S1, (uae_u32) ®s.fpcr);
+					and_l_ri (S1, 0xf0); /* restore control word */
+					fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+				}
+				break;
+			}
+#endif		/* in case of EXTENDED precision, just reduce the result to DOUBLE */
+			fdiv_rr (dreg, sreg);
+			fcut_r (dreg);
+			break;
+			case 0x66: /* FDADD */
+			if (!currprefs.fpu_strict) { /* faster, but less strict rounding */
+				fadd_rr (dreg, sreg);
+				break;
+			}
+#if USE_X86_FPUCW
+			if (regs.fpcr & 0xC0) { /* if we don't have EXTENDED precision */
+				if ((regs.fpcr & 0xC0) == 0x80) /* if we have DOUBLE */
+					fadd_rr (dreg, sreg);
+				else { /* if we have SINGLE presision, force DOUBLE */
+					mov_l_ri (S1, (regs.fpcr & 0x30) | 0x80);
+					fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+					fadd_rr (dreg, sreg);
+					mov_l_rm (S1, (uae_u32) ®s.fpcr);
+					and_l_ri (S1, 0xf0); /* restore control word */
+					fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+				}
+				break;
+			}
+#endif		/* in case of EXTENDED precision, just reduce the result to DOUBLE */
+			fadd_rr (dreg, sreg);
+			fcut_r (dreg);
+			break;
+			case 0x67: /* FDMUL */
+			if (!currprefs.fpu_strict) { /* faster, but less strict rounding */
+				fmul_rr (dreg, sreg);
+				break;
+			}
+#if USE_X86_FPUCW
+			if (regs.fpcr & 0xC0) { /* if we don't have EXTENDED precision */
+				if ((regs.fpcr & 0xC0) == 0x80) /* if we have DOUBLE */
+					fmul_rr (dreg, sreg);
+				else { /* if we have SINGLE presision, force DOUBLE */
+					mov_l_ri (S1, (regs.fpcr & 0x30) | 0x80);
+					fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+					fmul_rr (dreg, sreg);
+					mov_l_rm (S1, (uae_u32) ®s.fpcr);
+					and_l_ri (S1, 0xf0); /* restore control word */
+					fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+				}
+				break;
+			}
+#endif		/* in case of EXTENDED precision, just reduce the result to DOUBLE */
+			fmul_rr (dreg, sreg);
+			fcut_r (dreg);
+			break;
+			case 0x68: /* FSSUB */
+			fsub_rr (dreg, sreg);
+			if (!currprefs.fpu_strict) /* faster, but less strict rounding */
+				break;
+#if USE_X86_FPUCW
+			if ((regs.fpcr & 0xC0) == 0x40) /* if SINGLE precision */
+				break;
+#endif
+			fcuts_r (dreg);
+			break;
+			case 0x6c: /* FDSUB */
+			if (!currprefs.fpu_strict) { /* faster, but less strict rounding */
+				fsub_rr (dreg, sreg);
+				break;
+			}
+#if USE_X86_FPUCW
+			if (regs.fpcr & 0xC0) { /* if we don't have EXTENDED precision */
+				if ((regs.fpcr & 0xC0) == 0x80) /* if we have DOUBLE */
+					fsub_rr (dreg, sreg);
+				else { /* if we have SINGLE presision, force DOUBLE */
+					mov_l_ri (S1, (regs.fpcr & 0x30) | 0x80);
+					fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+					fsub_rr (dreg, sreg);
+					mov_l_rm (S1, (uae_u32) ®s.fpcr);
+					and_l_ri (S1, 0xf0); /* restore control word */
+					fldcw_m_indexed (S1, (uae_u32) x86_fpucw);
+				}
+				break;
+			}
+#endif		/* in case of EXTENDED precision, just reduce the result to DOUBLE */
+			fsub_rr (dreg, sreg);
+			fcut_r (dreg);
+			break;
+			default:
+			FAIL (1);
+			return;
+		}
+		fmov_rr (FP_RESULT, dreg);
+		return;
+		default:
+		write_log (_T ("Unsupported JIT-FPU instruction: 0x%04x %04x\n"), opcode, extra);
+		FAIL (1);
+		return;
+	}
+}
+#endif
diff --git a/src/cpu/jit/compemu_optimizer_x86.c b/src/cpu/jit/compemu_optimizer_x86.c
new file mode 100644
index 0000000..f84fdc6
--- /dev/null
+++ b/src/cpu/jit/compemu_optimizer_x86.c
@@ -0,0 +1,421 @@
+#if USE_LOW_OPTIMIZER
+/* Welcome to the magical world of cpp ;-) */
+
+/* This was broken by the advent of FPU emulation. It also didn't
+   provide any useful speedup while it worked. *Sigh* Someone fix my
+   software, please ;-) */
+
+#define MAXLOPTINST 100
+
+#define LDECISION currprefs.comp_lowopt
+
+#define lopt_op0(dummy) lopt_store_op0(
+#define lopt_op1(a1) lopt_store_op1(LOPT_##a1,
+#define lopt_op2(a1,a2) lopt_store_op2(LOPT_##a1,LOPT_##a2,
+#define lopt_op3(a1,a2,a3) lopt_store_op3(LOPT_##a1,LOPT_##a2,LOPT_##a3,
+#define lopt_op4(a1,a2,a3,a4) lopt_store_op4(LOPT_##a1,LOPT_##a2,LOPT_##a3,LOPT_##a4,
+#define lopt_op5(a1,a2,a3,a4,a5) lopt_store_op5(LOPT_##a1,LOPT_##a2,LOPT_##a3,LOPT_##a4,LOPT_##a5,
+
+#define ldirect0(dummy) ()
+#define ldirect1(a1) (LDIR_##a1)
+#define ldirect2(a1,a2) (LDIR_##a1,LDIR_##a2)
+#define ldirect3(a1,a2,a3) (LDIR_##a1,LDIR_##a2,LDIR_##a3)
+#define ldirect4(a1,a2,a3,a4) (LDIR_##a1,LDIR_##a2,LDIR_##a3,LDIR_##a4)
+#define ldirect5(a1,a2,a3,a4,a5) (LDIR_##a1,LDIR_##a2,LDIR_##a3,LDIR_##a4,LDIR_##a5)
+
+#define NONE 0
+#define READ 1
+#define WRITE 2
+#define RMW (READ|WRITE)
+
+#define SIZE1 4
+#define SIZE2 8
+#define SIZE4 12
+#define FLOAT 16
+#define SIZEMASK 12
+
+#define LIMM NONE
+#define LR1  (READ | SIZE1)
+#define LR2  (READ | SIZE2)
+#define LR4  (READ | SIZE4)
+#define LW1  (WRITE | SIZE1)
+#define LW2  (WRITE | SIZE2)
+#define LW4  (WRITE | SIZE4)
+#define LRW1 (RMW | SIZE1)
+#define LRW2 (RMW | SIZE2)
+#define LRW4 (RMW | SIZE4)
+#define LFW  (READ | FLOAT)
+#define LFR  (WRITE | FLOAT)
+#define LFRW (RMW | FLOAT)
+#define LMEMR NONE
+#define LMEMW NONE
+#define LMEMRW NONE
+
+#define LOPT_IMM LIMM,
+#define LOPT_R1  LR1 ,
+#define LOPT_R2  LR2 ,
+#define LOPT_R4  LR4 ,
+#define LOPT_W1  LW1 ,
+#define LOPT_W2  LW2 ,
+#define LOPT_W4  LW4 ,
+#define LOPT_RW1 LRW1,
+#define LOPT_RW2 LRW2,
+#define LOPT_RW4 LRW4,
+#define LOPT_FR  LFR,
+#define LOPT_FW  LFW,
+#define LOPT_FRW LFRW,
+#define LOPT_MEMR LMEMR,
+#define LOPT_MEMW LMEMW,
+#define LOPT_MEMRW LMEMRW,
+
+#define LDIR_IMM
+#define LDIR_R1
+#define LDIR_R2
+#define LDIR_R4
+#define LDIR_W1
+#define LDIR_W2
+#define LDIR_W4
+#define LDIR_RW1
+#define LDIR_RW2
+#define LDIR_RW4
+#define LDIR_FW
+#define LDIR_FR
+#define LDIR_FRW
+#define LDIR_MEMR
+#define LDIR_MEMW
+#define LDIR_MEMRW
+
+
+#undef LOWFUNC
+#undef LENDFUNC
+
+#define LOWFUNC(flags,mem,nargs,func,args) \
+  STATIC_INLINE void do_##func args
+
+#define LENDFUNC(flags,mem,nargs,func,args) \
+  STATIC_INLINE void func args \
+  { \
+  if (LDECISION) { \
+    lopt_op##nargs##args do_##func, mem, flags); \
+  } else { \
+    do_##func ldirect##nargs##args; \
+  } \
+  }
+
+typedef struct lopt_inst_rec {
+    void* func;
+    uae_u32 args[5];
+    uae_u8 argtype[5];
+    uae_s8 nargs;
+    uae_u8 mem;
+    uae_u8 flags;
+} lopt_inst;
+
+
+
+static lopt_inst linst[MAXLOPTINST];
+static int lopt_index=0;
+
+STATIC_INLINE int argsize(int type)
+{
+    return type&SIZEMASK;
+}
+
+STATIC_INLINE int reads_mem(int i) {
+    return linst[i].mem & READ;
+}
+
+
+STATIC_INLINE int access_reg(int i, int r, int mode)
+{
+    int k;
+    for (k=0;k=i-4 && j>=0 && !depends_on(i,j)) {
+		j--;
+	    }
+	    if (j!=i-1) {
+		lopt_inst x=linst[i];
+		int k=i;
+
+		j++;
+		while (k>j) {
+		    linst[k]=linst[k-1];
+		    k--;
+		}
+		linst[j]=x;
+	    }
+	}
+    }
+}
+
+
+typedef void lopt_handler0(void);
+typedef void lopt_handler1(uae_u32);
+typedef void lopt_handler2(uae_u32,uae_u32);
+typedef void lopt_handler3(uae_u32,uae_u32,uae_u32);
+typedef void lopt_handler4(uae_u32,uae_u32,uae_u32,uae_u32);
+typedef void lopt_handler5(uae_u32,uae_u32,uae_u32,uae_u32,uae_u32);
+
+static void lopt_emit_all(void)
+{
+    int i;
+    lopt_inst* x;
+    static int inemit=0;
+
+    if (inemit) {
+	printf("WARNING: lopt_emit is not reentrant!\n");
+    }
+    inemit=1;
+
+    low_peephole();
+
+    for (i=0;inargs) {
+	 case 0: ((lopt_handler0*)x->func)(); break;
+	 case 1: ((lopt_handler1*)x->func)(x->args[0]); break;
+	 case 2: ((lopt_handler2*)x->func)(x->args[0],x->args[1]); break;
+	 case 3: ((lopt_handler3*)x->func)(x->args[0],x->args[1],x->args[2]); break;
+	 case 4: ((lopt_handler4*)x->func)(x->args[0],x->args[1],x->args[2],
+					   x->args[3]); break;
+	 case 5: ((lopt_handler5*)x->func)(x->args[0],x->args[1],x->args[2],
+					   x->args[3],x->args[4]); break;
+	 default: abort();
+	}
+    }
+    lopt_index=0;
+    inemit=0;
+}
+
+STATIC_INLINE void low_advance(void)
+{
+  lopt_index++;
+  if (lopt_index==MAXLOPTINST)
+    lopt_emit_all();
+}
+
+STATIC_INLINE void lopt_store_op0(void* lfuncptr, uae_u32 lmem,
+				      uae_u32 lflags)
+{
+  linst[lopt_index].func=lfuncptr;
+  linst[lopt_index].mem=lmem;
+  linst[lopt_index].flags=lflags;
+  linst[lopt_index].nargs=0;
+  low_advance();
+}
+
+STATIC_INLINE void lopt_store_op1(uae_u8 t1, uae_u32 a1,
+				      void* lfuncptr, uae_u32 lmem,
+				      uae_u32 lflags)
+{
+  linst[lopt_index].func=lfuncptr;
+  linst[lopt_index].mem=lmem;
+  linst[lopt_index].flags=lflags;
+  linst[lopt_index].nargs=1;
+  linst[lopt_index].argtype[0]=t1;
+  linst[lopt_index].args[0]=a1;
+  low_advance();
+}
+
+STATIC_INLINE void lopt_store_op2(uae_u8 t1, uae_u32 a1,
+				      uae_u8 t2, uae_u32 a2,
+				      void* lfuncptr, uae_u32 lmem,
+				      uae_u32 lflags)
+{
+  linst[lopt_index].func=lfuncptr;
+  linst[lopt_index].mem=lmem;
+  linst[lopt_index].flags=lflags;
+  linst[lopt_index].nargs=2;
+  linst[lopt_index].argtype[0]=t1;
+  linst[lopt_index].args[0]=a1;
+  linst[lopt_index].argtype[1]=t2;
+  linst[lopt_index].args[1]=a2;
+  low_advance();
+}
+
+STATIC_INLINE void lopt_store_op3(uae_u8 t1, uae_u32 a1,
+				      uae_u8 t2, uae_u32 a2,
+				      uae_u8 t3, uae_u32 a3,
+				      void* lfuncptr, uae_u32 lmem,
+				      uae_u32 lflags)
+{
+  linst[lopt_index].func=lfuncptr;
+  linst[lopt_index].mem=lmem;
+  linst[lopt_index].flags=lflags;
+  linst[lopt_index].nargs=3;
+  linst[lopt_index].argtype[0]=t1;
+  linst[lopt_index].args[0]=a1;
+  linst[lopt_index].argtype[1]=t2;
+  linst[lopt_index].args[1]=a2;
+  linst[lopt_index].argtype[2]=t3;
+  linst[lopt_index].args[2]=a3;
+  low_advance();
+}
+
+STATIC_INLINE void lopt_store_op4(uae_u8 t1, uae_u32 a1,
+				      uae_u8 t2, uae_u32 a2,
+				      uae_u8 t3, uae_u32 a3,
+				      uae_u8 t4, uae_u32 a4,
+				      void* lfuncptr, uae_u32 lmem,
+				      uae_u32 lflags)
+{
+  linst[lopt_index].func=lfuncptr;
+  linst[lopt_index].mem=lmem;
+  linst[lopt_index].flags=lflags;
+  linst[lopt_index].nargs=4;
+  linst[lopt_index].argtype[0]=t1;
+  linst[lopt_index].args[0]=a1;
+  linst[lopt_index].argtype[1]=t2;
+  linst[lopt_index].args[1]=a2;
+  linst[lopt_index].argtype[2]=t3;
+  linst[lopt_index].args[2]=a3;
+  linst[lopt_index].argtype[3]=t4;
+  linst[lopt_index].args[3]=a4;
+  low_advance();
+}
+
+STATIC_INLINE void lopt_store_op5(uae_u8 t1, uae_u32 a1,
+				      uae_u8 t2, uae_u32 a2,
+				      uae_u8 t3, uae_u32 a3,
+				      uae_u8 t4, uae_u32 a4,
+				      uae_u8 t5, uae_u32 a5,
+				      void* lfuncptr, uae_u32 lmem,
+				      uae_u32 lflags)
+{
+  linst[lopt_index].func=lfuncptr;
+  linst[lopt_index].mem=lmem;
+  linst[lopt_index].flags=lflags;
+  linst[lopt_index].nargs=5;
+  linst[lopt_index].argtype[0]=t1;
+  linst[lopt_index].args[0]=a1;
+  linst[lopt_index].argtype[1]=t2;
+  linst[lopt_index].args[1]=a2;
+  linst[lopt_index].argtype[2]=t3;
+  linst[lopt_index].args[2]=a3;
+  linst[lopt_index].argtype[3]=t4;
+  linst[lopt_index].args[3]=a4;
+  linst[lopt_index].argtype[4]=t5;
+  linst[lopt_index].args[4]=a5;
+  low_advance();
+}
+
+STATIC_INLINE void empty_low_optimizer(void)
+{
+  lopt_emit_all();
+}
+
+#else
+#define lopt_emit_all()
+#define empty_low_optimizer()
+#endif
diff --git a/src/cpu/jit/compemu_raw_x86.c b/src/cpu/jit/compemu_raw_x86.c
new file mode 100644
index 0000000..7e4d6f8
--- /dev/null
+++ b/src/cpu/jit/compemu_raw_x86.c
@@ -0,0 +1,4011 @@
+/* This should eventually end up in machdep/, but for now, x86 is the
+only target, and it's easier this way... */
+
+/*************************************************************************
+* Some basic information about the the target CPU                       *
+*************************************************************************/
+
+#define EAX_INDEX 0
+#define ECX_INDEX 1
+#define EDX_INDEX 2
+#define EBX_INDEX 3
+#define ESP_INDEX 4
+#define EBP_INDEX 5
+#define ESI_INDEX 6
+#define EDI_INDEX 7
+#if defined(__x86_64__)
+#define R8_INDEX  8
+#define R9_INDEX  9
+#define R10_INDEX 10
+#define R11_INDEX 11
+#define R12_INDEX 12
+#define R13_INDEX 13
+#define R14_INDEX 14
+#define R15_INDEX 15
+#endif
+/* XXX this has to match X86_Reg8H_Base + 4 */
+#define AH_INDEX (0x10+4+EAX_INDEX)
+#define CH_INDEX (0x10+4+ECX_INDEX)
+#define DH_INDEX (0x10+4+EDX_INDEX)
+#define BH_INDEX (0x10+4+EBX_INDEX)
+
+/* The register in which subroutines return an integer return value */
+#define REG_RESULT EAX_INDEX
+
+/* The registers subroutines take their first and second argument in */
+#if defined(_WIN32)
+/* Handle the _fastcall parameters of ECX and EDX */
+#define REG_PAR1 ECX_INDEX
+#define REG_PAR2 EDX_INDEX
+#elif defined(__x86_64__)
+#define REG_PAR1 EDI_INDEX
+#define REG_PAR2 ESI_INDEX
+#else
+#define REG_PAR1 EAX_INDEX
+#define REG_PAR2 EDX_INDEX
+#endif
+
+#if defined(_WIN32)
+#define REG_PC_PRE EAX_INDEX /* The register we use for preloading regs.pc_p */
+#define REG_PC_TMP ECX_INDEX
+#define SHIFTCOUNT_NREG ECX_INDEX  /* Register that can be used for shiftcount. -1 if any reg will do */
+#else
+#define REG_PC_PRE EAX_INDEX /* The register we use for preloading regs.pc_p */
+#define REG_PC_TMP ECX_INDEX /* Another register that is not the above */
+#define SHIFTCOUNT_NREG ECX_INDEX  /* Register that can be used for shiftcount. -1 if any reg will do */
+#endif
+
+#define MUL_NREG1 EAX_INDEX /* %eax will hold the low 32 bits after a 32x32 mul */
+#define MUL_NREG2 EDX_INDEX /* %edx will hold the high 32 bits */
+
+#define STACK_ALIGN		16
+#define STACK_OFFSET	sizeof(void *)
+
+uae_u8 always_used[]={4,0xff};
+#if defined(__x86_64__)
+uae_s8 can_byte[]={0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,-1};
+uae_s8 can_word[]={0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,-1};
+#else
+uae_u8 can_byte[]={0,1,2,3,0xff};
+uae_u8 can_word[]={0,1,2,3,5,6,7,0xff};
+#endif
+
+uae_u8 call_saved[]={0,0,0,0,1,0,0,0};
+
+/* This *should* be the same as call_saved. But:
+- We might not really know which registers are saved, and which aren't,
+so we need to preserve some, but don't want to rely on everyone else
+also saving those registers
+- Special registers (such like the stack pointer) should not be "preserved"
+by pushing, even though they are "saved" across function calls
+*/
+uae_u8 need_to_preserve[]={1,1,1,1,0,1,1,1};
+
+/* Whether classes of instructions do or don't clobber the native flags */
+#define CLOBBER_MOV
+#define CLOBBER_LEA
+#define CLOBBER_CMOV
+#define CLOBBER_POP
+#define CLOBBER_PUSH
+#define CLOBBER_SUB  clobber_flags()
+#define CLOBBER_SBB  clobber_flags()
+#define CLOBBER_CMP  clobber_flags()
+#define CLOBBER_ADD  clobber_flags()
+#define CLOBBER_ADC  clobber_flags()
+#define CLOBBER_AND  clobber_flags()
+#define CLOBBER_OR   clobber_flags()
+#define CLOBBER_XOR  clobber_flags()
+
+#define CLOBBER_ROL  clobber_flags()
+#define CLOBBER_ROR  clobber_flags()
+#define CLOBBER_SHLL clobber_flags()
+#define CLOBBER_SHRL clobber_flags()
+#define CLOBBER_SHRA clobber_flags()
+#define CLOBBER_TEST clobber_flags()
+#define CLOBBER_CL16
+#define CLOBBER_CL8
+#define CLOBBER_SE16
+#define CLOBBER_SE8
+#define CLOBBER_ZE16
+#define CLOBBER_ZE8
+#define CLOBBER_SW16 clobber_flags()
+#define CLOBBER_SW32
+#define CLOBBER_SETCC
+#define CLOBBER_MUL  clobber_flags()
+#define CLOBBER_BT   clobber_flags()
+#define CLOBBER_BSF  clobber_flags()
+
+/*************************************************************************
+* Actual encoding of the instructions on the target CPU                 *
+*************************************************************************/
+
+//#include "compemu_optimizer_x86.c"
+
+STATIC_INLINE uae_u16 swap16(uae_u16 x)
+{
+	return ((x&0xff00)>>8)|((x&0x00ff)<<8);
+}
+
+STATIC_INLINE uae_u32 swap32(uae_u32 x)
+{
+	return ((x&0xff00)<<8)|((x&0x00ff)<<24)|((x&0xff0000)>>8)|((x&0xff000000)>>24);
+}
+
+STATIC_INLINE int isbyte(uae_s32 x)
+{
+	return (x>=-128 && x<=127);
+}
+
+LOWFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r))
+{
+	emit_byte(0x50+r);
+}
+LENDFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r))
+
+	LOWFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
+{
+	emit_byte(0x58+r);
+}
+LENDFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
+{
+	emit_byte(0x0f);
+	emit_byte(0xba);
+	emit_byte(0xe0+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b))
+{
+	emit_byte(0x0f);
+	emit_byte(0xa3);
+	emit_byte(0xc0+8*b+r);
+}
+LENDFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b))
+
+	LOWFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i))
+{
+	emit_byte(0x0f);
+	emit_byte(0xba);
+	emit_byte(0xf8+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b))
+{
+	emit_byte(0x0f);
+	emit_byte(0xbb);
+	emit_byte(0xc0+8*b+r);
+}
+LENDFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b))
+
+
+	LOWFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i))
+{
+	emit_byte(0x0f);
+	emit_byte(0xba);
+	emit_byte(0xf0+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b))
+{
+	emit_byte(0x0f);
+	emit_byte(0xb3);
+	emit_byte(0xc0+8*b+r);
+}
+LENDFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b))
+
+	LOWFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i))
+{
+	emit_byte(0x0f);
+	emit_byte(0xba);
+	emit_byte(0xe8+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b))
+{
+	emit_byte(0x0f);
+	emit_byte(0xab);
+	emit_byte(0xc0+8*b+r);
+}
+LENDFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b))
+
+	LOWFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i))
+{
+	emit_byte(0x66);
+	if (isbyte(i)) {
+		emit_byte(0x83);
+		emit_byte(0xe8+d);
+		emit_byte(i);
+	}
+	else {
+		emit_byte(0x81);
+		emit_byte(0xe8+d);
+		emit_word(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i))
+
+
+	LOWFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s))
+{
+	emit_byte(0xc7);
+	emit_byte(0x05);
+	emit_long(d);
+	emit_long(s);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s))
+
+	LOWFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s))
+{
+	emit_byte(0x66);
+	emit_byte(0xc7);
+	emit_byte(0x05);
+	emit_long(d);
+	emit_word(s);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s))
+
+	LOWFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s))
+{
+	emit_byte(0xc6);
+	emit_byte(0x05);
+	emit_long(d);
+	emit_byte(s);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s))
+
+	LOWFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i))
+{
+	emit_byte(0xc0);
+	emit_byte(0x05);
+	emit_long(d);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i))
+{
+	emit_byte(0xc0);
+	emit_byte(0xc0+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i))
+{
+	emit_byte(0x66);
+	emit_byte(0xc1);
+	emit_byte(0xc0+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i))
+{
+	emit_byte(0xc1);
+	emit_byte(0xc0+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r))
+{
+	emit_byte(0xd3);
+	emit_byte(0xc0+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r))
+{
+	emit_byte(0x66);
+	emit_byte(0xd3);
+	emit_byte(0xc0+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r))
+{
+	emit_byte(0xd2);
+	emit_byte(0xc0+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r))
+{
+	emit_byte(0xd3);
+	emit_byte(0xe0+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r))
+{
+	emit_byte(0x66);
+	emit_byte(0xd3);
+	emit_byte(0xe0+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r))
+{
+	emit_byte(0xd2);
+	emit_byte(0xe0+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i))
+{
+	emit_byte(0xc0);
+	emit_byte(0xc8+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i))
+{
+	emit_byte(0x66);
+	emit_byte(0xc1);
+	emit_byte(0xc8+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i))
+{
+	emit_byte(0xc1);
+	emit_byte(0xc8+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r))
+{
+	emit_byte(0xd3);
+	emit_byte(0xc8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r))
+{
+	emit_byte(0x66);
+	emit_byte(0xd3);
+	emit_byte(0xc8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r))
+{
+	emit_byte(0xd2);
+	emit_byte(0xc8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r))
+{
+	emit_byte(0xd3);
+	emit_byte(0xe8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r))
+{
+	emit_byte(0x66);
+	emit_byte(0xd3);
+	emit_byte(0xe8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r))
+{
+	emit_byte(0xd2);
+	emit_byte(0xe8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r))
+{
+	emit_byte(0xd3);
+	emit_byte(0xf8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r))
+{
+	emit_byte(0x66);
+	emit_byte(0xd3);
+	emit_byte(0xf8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r))
+{
+	emit_byte(0xd2);
+	emit_byte(0xf8+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r))
+
+	LOWFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i))
+{
+	emit_byte(0xc1);
+	emit_byte(0xe0+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i))
+{
+	emit_byte(0x66);
+	emit_byte(0xc1);
+	emit_byte(0xe0+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i))
+{
+	emit_byte(0xc0);
+	emit_byte(0xe0+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i))
+{
+	emit_byte(0xc1);
+	emit_byte(0xe8+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i))
+{
+	emit_byte(0x66);
+	emit_byte(0xc1);
+	emit_byte(0xe8+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i))
+{
+	emit_byte(0xc0);
+	emit_byte(0xe8+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i))
+{
+	emit_byte(0xc1);
+	emit_byte(0xf8+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i))
+{
+	emit_byte(0x66);
+	emit_byte(0xc1);
+	emit_byte(0xf8+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i))
+{
+	emit_byte(0xc0);
+	emit_byte(0xf8+r);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah))
+{
+	emit_byte(0x9e);
+}
+LENDFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah))
+
+	LOWFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax))
+{
+	emit_byte(0x0f);
+	emit_byte(0xa2);
+}
+LENDFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax))
+
+	LOWFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah))
+{
+	emit_byte(0x9f);
+}
+LENDFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah))
+
+	LOWFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc))
+{
+	emit_byte(0x0f);
+	emit_byte(0x90+cc);
+	emit_byte(0xc0+d);
+}
+LENDFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc))
+
+	LOWFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc))
+{
+	emit_byte(0x0f);
+	emit_byte(0x90+cc);
+	emit_byte(0x05);
+	emit_long(d);
+}
+LENDFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc))
+
+	LOWFUNC(READ,NONE,3,raw_cmov_b_rr,(RW1 d, R1 s, IMM cc))
+{
+	/* replacement using branch and mov */
+	int uncc=(cc^1);
+	emit_byte(0x70+uncc);
+	emit_byte(3);  /* skip next 2 bytes if not cc=true */
+	emit_byte(0x88);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(READ,NONE,3,raw_cmov_b_rr,(RW1 d, R1 s, IMM cc))
+
+	LOWFUNC(READ,NONE,3,raw_cmov_w_rr,(RW2 d, R2 s, IMM cc))
+{
+	if (have_cmov) {
+		emit_byte(0x66);
+		emit_byte(0x0f);
+		emit_byte(0x40+cc);
+		emit_byte(0xc0+8*d+s);
+	}
+	else { /* replacement using branch and mov */
+		int uncc=(cc^1);
+		emit_byte(0x70+uncc);
+		emit_byte(3);  /* skip next 3 bytes if not cc=true */
+		emit_byte(0x66);
+		emit_byte(0x89);
+		emit_byte(0xc0+8*s+d);
+	}
+}
+LENDFUNC(READ,NONE,3,raw_cmov_w_rr,(RW2 d, R2 s, IMM cc))
+
+	LOWFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc))
+{
+	if (have_cmov) {
+		emit_byte(0x0f);
+		emit_byte(0x40+cc);
+		emit_byte(0xc0+8*d+s);
+	}
+	else { /* replacement using branch and mov */
+		int uncc=(cc^1);
+		emit_byte(0x70+uncc);
+		emit_byte(2);  /* skip next 2 bytes if not cc=true */
+		emit_byte(0x89);
+		emit_byte(0xc0+8*s+d);
+	}
+}
+LENDFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc))
+
+	LOWFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s))
+{
+	emit_byte(0x0f);
+	emit_byte(0xbc);
+	emit_byte(0xc0+8*d+s);
+}
+LENDFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s))
+
+	LOWFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s))
+{
+	emit_byte(0x0f);
+	emit_byte(0xbf);
+	emit_byte(0xc0+8*d+s);
+}
+LENDFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s))
+
+	LOWFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s))
+{
+	emit_byte(0x0f);
+	emit_byte(0xbe);
+	emit_byte(0xc0+8*d+s);
+}
+LENDFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s))
+
+	LOWFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s))
+{
+	emit_byte(0x0f);
+	emit_byte(0xb7);
+	emit_byte(0xc0+8*d+s);
+}
+LENDFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s))
+
+	LOWFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s))
+{
+	emit_byte(0x0f);
+	emit_byte(0xb6);
+	emit_byte(0xc0+8*d+s);
+}
+LENDFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s))
+
+	LOWFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s))
+{
+	emit_byte(0x0f);
+	emit_byte(0xaf);
+	emit_byte(0xc0+8*d+s);
+}
+LENDFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s))
+
+	LOWFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s))
+{
+#ifdef JIT_DEBUG
+	if (d!=MUL_NREG1 || s!=MUL_NREG2) {
+		write_log (_T("JIT: Bad register in IMUL: d=%d, s=%d\n"),d,s);
+		abort();
+	}
+#endif
+	emit_byte(0xf7);
+	emit_byte(0xea);
+}
+LENDFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s))
+
+	LOWFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s))
+{
+#ifdef JIT_DEBUG
+	if (d!=MUL_NREG1 || s!=MUL_NREG2) {
+		write_log (_T("JIT: Bad register in MUL: d=%d, s=%d\n"),d,s);
+		abort();
+	}
+#endif
+	emit_byte(0xf7);
+	emit_byte(0xe2);
+}
+LENDFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s))
+
+	LOWFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s))
+{
+	emit_byte(0x88);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s))
+
+	LOWFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s))
+{
+	emit_byte(0x66);
+	emit_byte(0x89);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s))
+
+	LOWFUNC(NONE,READ,3,raw_mov_l_rrm_indexed,(W4 d, R4 baser, R4 index))
+{
+	emit_byte(0x8b);
+	if (baser==5) {
+		emit_byte(0x44+8*d);
+		emit_byte(8*index+baser);
+		emit_byte(0);
+		return;
+	}
+	emit_byte(0x04+8*d);
+	emit_byte(8*index+baser);
+}
+LENDFUNC(NONE,READ,3,raw_mov_l_rrm_indexed,(W4 d, R4 baser, R4 index))
+
+	LOWFUNC(NONE,READ,3,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index))
+{
+	emit_byte(0x66);
+	emit_byte(0x8b);
+	if (baser==5) {
+		emit_byte(0x44+8*d);
+		emit_byte(8*index+baser);
+		emit_byte(0);
+		return;
+	}
+	emit_byte(0x04+8*d);
+	emit_byte(8*index+baser);
+}
+LENDFUNC(NONE,READ,3,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index))
+
+	LOWFUNC(NONE,READ,3,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index))
+{
+	emit_byte(0x8a);
+	if (baser==5) {
+		emit_byte(0x44+8*d);
+		emit_byte(8*index+baser);
+		emit_byte(0);
+		return;
+	}
+	emit_byte(0x04+8*d);
+	emit_byte(8*index+baser);
+}
+LENDFUNC(NONE,READ,3,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index))
+
+	LOWFUNC(NONE,WRITE,3,raw_mov_l_mrr_indexed,(R4 baser, R4 index, R4 s))
+{
+	emit_byte(0x89);
+	if (baser==5) {
+		emit_byte(0x44+8*s);
+		emit_byte(8*index+baser);
+		emit_byte(0);
+		return;
+	}
+	emit_byte(0x04+8*s);
+	emit_byte(8*index+baser);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_l_mrr_indexed,(R4 baser, R4 index, R4 s))
+
+	LOWFUNC(NONE,WRITE,3,raw_mov_w_mrr_indexed,(R4 baser, R4 index, R2 s))
+{
+	emit_byte(0x66);
+	emit_byte(0x89);
+	if (baser==5) {
+		emit_byte(0x44+8*s);
+		emit_byte(8*index+baser);
+		emit_byte(0);
+		return;
+	}
+	emit_byte(0x04+8*s);
+	emit_byte(8*index+baser);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_w_mrr_indexed,(R4 baser, R4 index, R2 s))
+
+	LOWFUNC(NONE,WRITE,3,raw_mov_b_mrr_indexed,(R4 baser, R4 index, R1 s))
+{
+	emit_byte(0x88);
+	if (baser==5) {
+		emit_byte(0x44+8*s);
+		emit_byte(8*index+baser);
+		emit_byte(0);
+		return;
+	}
+	emit_byte(0x04+8*s);
+	emit_byte(8*index+baser);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_b_mrr_indexed,(R4 baser, R4 index, R1 s))
+
+	LOWFUNC(NONE,READ,3,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index))
+{
+	emit_byte(0x8b);
+	emit_byte(0x04+8*d);
+	emit_byte(0x85+8*index);
+	emit_long(base);
+}
+LENDFUNC(NONE,READ,3,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index))
+
+	LOWFUNC(NONE,READ,4,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM cond))
+{
+	if (have_cmov) {
+		emit_byte(0x0f);
+		emit_byte(0x40+cond);
+	}
+	else { /* replacement using branch and mov */
+		int uncc=(cond^1);
+		emit_byte(0x70+uncc);
+		emit_byte(7);  /* skip next 7 bytes if not cc=true */
+		emit_byte(0x8b);
+	}
+	emit_byte(0x04+8*d);
+	emit_byte(0x85+8*index);
+	emit_long(base);
+}
+LENDFUNC(NONE,READ,4,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM cond))
+
+	LOWFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond))
+{
+	if (have_cmov) {
+		emit_byte(0x0f);
+		emit_byte(0x40+cond);
+		emit_byte(0x05+8*d);
+		emit_long(mem);
+	}
+	else { /* replacement using branch and mov */
+		int uncc=(cond^1);
+		emit_byte(0x70+uncc);
+		emit_byte(6);  /* skip next 6 bytes if not cc=true */
+		emit_byte(0x8b);
+		emit_byte(0x05+8*d);
+		emit_long(mem);
+	}
+}
+LENDFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond))
+
+	LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
+{
+	emit_byte(0x8b);
+	emit_byte(0x40+8*d+s);
+	emit_byte(offset);
+}
+LENDFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
+
+	LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
+{
+	emit_byte(0x66);
+	emit_byte(0x8b);
+	emit_byte(0x40+8*d+s);
+	emit_byte(offset);
+}
+LENDFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
+
+	LOWFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
+{
+	emit_byte(0x8a);
+	emit_byte(0x40+8*d+s);
+	emit_byte(offset);
+}
+LENDFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
+
+	LOWFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset))
+{
+	emit_byte(0x8b);
+	emit_byte(0x80+8*d+s);
+	emit_long(offset);
+}
+LENDFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset))
+
+	LOWFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset))
+{
+	emit_byte(0x66);
+	emit_byte(0x8b);
+	emit_byte(0x80+8*d+s);
+	emit_long(offset);
+}
+LENDFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset))
+
+	LOWFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset))
+{
+	emit_byte(0x8a);
+	emit_byte(0x80+8*d+s);
+	emit_long(offset);
+}
+LENDFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset))
+
+	LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
+{
+	emit_byte(0xc7);
+	emit_byte(0x40+d);
+	emit_byte(offset);
+	emit_long(i);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
+
+	LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
+{
+	emit_byte(0x66);
+	emit_byte(0xc7);
+	emit_byte(0x40+d);
+	emit_byte(offset);
+	emit_word(i);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
+
+	LOWFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
+{
+	emit_byte(0xc6);
+	emit_byte(0x40+d);
+	emit_byte(offset);
+	emit_byte(i);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
+
+	LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
+{
+	emit_byte(0x89);
+	emit_byte(0x40+8*s+d);
+	emit_byte(offset);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
+
+	LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
+{
+	emit_byte(0x66);
+	emit_byte(0x89);
+	emit_byte(0x40+8*s+d);
+	emit_byte(offset);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
+
+	LOWFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
+{
+	emit_byte(0x88);
+	emit_byte(0x40+8*s+d);
+	emit_byte(offset);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
+
+	LOWFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset))
+{
+	emit_byte(0x8d);
+	emit_byte(0x80+8*d+s);
+	emit_long(offset);
+}
+LENDFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset))
+
+	LOWFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
+{
+	emit_byte(0x8d);
+	if (!offset) {
+		if (s!=5) {
+			emit_byte(0x04+8*d);
+			emit_byte(0x40*factor+8*index+s);
+			return;
+		}
+		emit_byte(0x44+8*d);
+		emit_byte(0x40*factor+8*index+s);
+		emit_byte(0);
+		return;
+	}
+	emit_byte(0x84+8*d);
+	emit_byte(0x40*factor+8*index+s);
+	emit_long(offset);
+}
+LENDFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
+
+	LOWFUNC(NONE,NONE,3,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index))
+{
+	emit_byte(0x8d);
+	if (s==5) {
+		emit_byte(0x44+8*d);
+		emit_byte(8*index+s);
+		emit_byte(0);
+		return;
+	}
+	emit_byte(0x04+8*d);
+	emit_byte(8*index+s);
+}
+LENDFUNC(NONE,NONE,3,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index))
+
+	LOWFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset))
+{
+	emit_byte(0x89);
+	emit_byte(0x80+8*s+d);
+	emit_long(offset);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset))
+
+	LOWFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset))
+{
+	emit_byte(0x66);
+	emit_byte(0x89);
+	emit_byte(0x80+8*s+d);
+	emit_long(offset);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset))
+
+	LOWFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset))
+{
+	emit_byte(0x88);
+	emit_byte(0x80+8*s+d);
+	emit_long(offset);
+}
+LENDFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset))
+
+	LOWFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r))
+{
+	emit_byte(0x0f);
+	emit_byte(0xc8+r);
+}
+LENDFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r))
+
+	LOWFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r))
+{
+	emit_byte(0x66);
+	emit_byte(0xc1);
+	emit_byte(0xc0+r);
+	emit_byte(0x08);
+}
+LENDFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r))
+
+	LOWFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s))
+{
+	emit_byte(0x89);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s))
+
+	LOWFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s))
+{
+	emit_byte(0x89);
+	emit_byte(0x05+8*s);
+	emit_long(d);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s))
+
+	LOWFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s))
+{
+	emit_byte(0x8b);
+	emit_byte(0x05+8*d);
+	emit_long(s);
+}
+LENDFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s))
+
+	LOWFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s))
+{
+	emit_byte(0x66);
+	emit_byte(0x89);
+	emit_byte(0x05+8*s);
+	emit_long(d);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s))
+
+	LOWFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s))
+{
+	emit_byte(0x66);
+	emit_byte(0x8b);
+	emit_byte(0x05+8*d);
+	emit_long(s);
+}
+LENDFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s))
+
+	LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
+{
+	emit_byte(0x88);
+	emit_byte(0x05+8*s);
+	emit_long(d);
+}
+LENDFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
+
+	LOWFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s))
+{
+	emit_byte(0x8a);
+	emit_byte(0x05+8*d);
+	emit_long(s);
+}
+LENDFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s))
+
+	LOWFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s))
+{
+	emit_byte(0xb8+d);
+	emit_long(s);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s))
+
+	LOWFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
+{
+	emit_byte(0x66);
+	emit_byte(0xb8+d);
+	emit_word(s);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
+
+	LOWFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
+{
+	emit_byte(0xb0+d);
+	emit_byte(s);
+}
+LENDFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
+
+	LOWFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s))
+{
+	emit_byte(0x81);
+	emit_byte(0x15);
+	emit_long(d);
+	emit_long(s);
+}
+LENDFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s))
+
+	LOWFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s))
+{
+	emit_byte(0x81);
+	emit_byte(0x05);
+	emit_long(d);
+	emit_long(s);
+}
+LENDFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s))
+
+	LOWFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s))
+{
+	emit_byte(0x66);
+	emit_byte(0x81);
+	emit_byte(0x05);
+	emit_long(d);
+	emit_word(s);
+}
+LENDFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s))
+
+	LOWFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s))
+{
+	emit_byte(0x80);
+	emit_byte(0x05);
+	emit_long(d);
+	emit_byte(s);
+}
+LENDFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s))
+
+	LOWFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i))
+{
+	emit_byte(0xf7);
+	emit_byte(0xc0+d);
+	emit_long(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s))
+{
+	emit_byte(0x85);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s))
+{
+	emit_byte(0x66);
+	emit_byte(0x85);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
+{
+	emit_byte(0x84);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
+{
+	emit_byte(0x81);
+	emit_byte(0xe0+d);
+	emit_long(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i))
+{
+	emit_byte(0x66);
+	emit_byte(0x81);
+	emit_byte(0xe0+d);
+	emit_word(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s))
+{
+	emit_byte(0x21);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s))
+{
+	emit_byte(0x66);
+	emit_byte(0x21);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s))
+{
+	emit_byte(0x20);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i))
+{
+	emit_byte(0x81);
+	emit_byte(0xc8+d);
+	emit_long(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s))
+{
+	emit_byte(0x09);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s))
+{
+	emit_byte(0x66);
+	emit_byte(0x09);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s))
+{
+	emit_byte(0x08);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s))
+
+	LOWFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s))
+{
+	emit_byte(0x11);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s))
+
+	LOWFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s))
+{
+	emit_byte(0x66);
+	emit_byte(0x11);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s))
+
+	LOWFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s))
+{
+	emit_byte(0x10);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s))
+{
+	emit_byte(0x01);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s))
+{
+	emit_byte(0x66);
+	emit_byte(0x01);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s))
+{
+	emit_byte(0x00);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i))
+{
+	if (isbyte(i)) {
+		emit_byte(0x83);
+		emit_byte(0xe8+d);
+		emit_byte(i);
+	}
+	else {
+		emit_byte(0x81);
+		emit_byte(0xe8+d);
+		emit_long(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i))
+{
+	emit_byte(0x80);
+	emit_byte(0xe8+d);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i))
+{
+	if (isbyte(i)) {
+		emit_byte(0x83);
+		emit_byte(0xc0+d);
+		emit_byte(i);
+	}
+	else {
+		emit_byte(0x81);
+		emit_byte(0xc0+d);
+		emit_long(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i))
+{
+	if (isbyte(i)) {
+		emit_byte(0x66);
+		emit_byte(0x83);
+		emit_byte(0xc0+d);
+		emit_byte(i);
+	}
+	else {
+		emit_byte(0x66);
+		emit_byte(0x81);
+		emit_byte(0xc0+d);
+		emit_word(i);
+	}
+}
+LENDFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i))
+{
+	emit_byte(0x80);
+	emit_byte(0xc0+d);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i))
+
+	LOWFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s))
+{
+	emit_byte(0x19);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s))
+
+	LOWFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s))
+{
+	emit_byte(0x66);
+	emit_byte(0x19);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s))
+
+	LOWFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s))
+{
+	emit_byte(0x18);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s))
+{
+	emit_byte(0x29);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s))
+{
+	emit_byte(0x66);
+	emit_byte(0x29);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s))
+{
+	emit_byte(0x28);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s))
+{
+	emit_byte(0x39);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i))
+{
+	emit_byte(0x81);
+	emit_byte(0xf8+r);
+	emit_long(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s))
+{
+	emit_byte(0x66);
+	emit_byte(0x39);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i))
+{
+	emit_byte(0x80);
+	emit_byte(0xf8+d);
+	emit_byte(i);
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i))
+
+	LOWFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s))
+{
+	emit_byte(0x38);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s))
+{
+	emit_byte(0x31);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s))
+{
+	emit_byte(0x66);
+	emit_byte(0x31);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s))
+
+	LOWFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s))
+{
+	emit_byte(0x30);
+	emit_byte(0xc0+8*s+d);
+}
+LENDFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s))
+
+	LOWFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s))
+{
+	emit_byte(0x81);
+	emit_byte(0x2d);
+	emit_long(d);
+	emit_long(s);
+}
+LENDFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s))
+
+	LOWFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
+{
+	emit_byte(0x81);
+	emit_byte(0x3d);
+	emit_long(d);
+	emit_long(s);
+}
+LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
+
+	LOWFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
+{
+	emit_byte(0x87);
+	emit_byte(0xc0+8*r1+r2);
+}
+LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
+
+	LOWFUNC(READ,WRITE,0,raw_pushfl,(void))
+{
+	emit_byte(0x9c);
+}
+LENDFUNC(READ,WRITE,0,raw_pushfl,(void))
+
+	LOWFUNC(WRITE,READ,0,raw_popfl,(void))
+{
+	emit_byte(0x9d);
+}
+LENDFUNC(WRITE,READ,0,raw_popfl,(void))
+
+	/*************************************************************************
+	* Unoptimizable stuff --- jump                                          *
+	*************************************************************************/
+
+	STATIC_INLINE void raw_call_r(R4 r)
+{
+	lopt_emit_all();
+	emit_byte(0xff);
+	emit_byte(0xd0+r);
+}
+
+STATIC_INLINE void raw_jmp_r(R4 r)
+{
+	lopt_emit_all();
+	emit_byte(0xff);
+	emit_byte(0xe0+r);
+}
+
+STATIC_INLINE void raw_jmp_m_indexed(uae_u32 base, uae_u32 r, uae_u32 m)
+{
+	int sib;
+
+	switch (m) {
+	case 1: sib = 0x05; break;
+	case 2: sib = 0x45; break;
+	case 4: sib = 0x85; break;
+	case 8: sib = 0xC5; break;
+	default: abort();
+	}
+	lopt_emit_all();
+	emit_byte(0xff);
+	emit_byte(0x24);
+	emit_byte(8*r+sib);
+	emit_long(base);
+}
+
+STATIC_INLINE void raw_jmp_m(uae_u32 base)
+{
+	lopt_emit_all();
+	emit_byte(0xff);
+	emit_byte(0x25);
+	emit_long(base);
+}
+
+STATIC_INLINE void raw_call(uae_u32 t)
+{
+	lopt_emit_all();
+	emit_byte(0xe8);
+	emit_long(t-(uae_u32)target-4);
+}
+
+STATIC_INLINE void raw_jmp(uae_u32 t)
+{
+	lopt_emit_all();
+	emit_byte(0xe9);
+	emit_long(t-(uae_u32)target-4);
+}
+
+STATIC_INLINE void raw_jl(uae_u32 t)
+{
+	lopt_emit_all();
+	emit_byte(0x0f);
+	emit_byte(0x8c);
+	emit_long(t-(uae_u32)target-4);
+}
+
+STATIC_INLINE void raw_jz(uae_u32 t)
+{
+	lopt_emit_all();
+	emit_byte(0x0f);
+	emit_byte(0x84);
+	emit_long(t-(uae_u32)target-4);
+}
+
+STATIC_INLINE void raw_jnz(uae_u32 t)
+{
+	lopt_emit_all();
+	emit_byte(0x0f);
+	emit_byte(0x85);
+	emit_long(t-(uae_u32)target-4);
+}
+
+STATIC_INLINE void raw_jnz_l_oponly(void)
+{
+	lopt_emit_all();
+	emit_byte(0x0f);
+	emit_byte(0x85);
+}
+
+STATIC_INLINE void raw_jcc_l_oponly(int cc)
+{
+	lopt_emit_all();
+	emit_byte(0x0f);
+	emit_byte(0x80+cc);
+}
+
+STATIC_INLINE void raw_jnz_b_oponly(void)
+{
+	lopt_emit_all();
+	emit_byte(0x75);
+}
+
+STATIC_INLINE void raw_jz_b_oponly(void)
+{
+	lopt_emit_all();
+	emit_byte(0x74);
+}
+
+STATIC_INLINE void raw_jmp_l_oponly(void)
+{
+	lopt_emit_all();
+	emit_byte(0xe9);
+}
+
+STATIC_INLINE void raw_jmp_b_oponly(void)
+{
+	lopt_emit_all();
+	emit_byte(0xeb);
+}
+
+STATIC_INLINE void raw_ret(void)
+{
+	lopt_emit_all();
+	emit_byte(0xc3);
+}
+
+STATIC_INLINE void raw_nop(void)
+{
+	lopt_emit_all();
+	emit_byte(0x90);
+}
+
+
+/*************************************************************************
+* Flag handling, to and fro UAE flag register                           *
+*************************************************************************/
+
+
+#define FLAG_NREG1 0  /* Set to -1 if any register will do */
+
+STATIC_INLINE void raw_flags_to_reg(int r)
+{
+	raw_lahf(0);  /* Most flags in AH */
+	//raw_setcc(r,0); /* V flag in AL */
+	raw_setcc_m((uae_u32)live.state[FLAGTMP].mem,0);
+
+#if 1   /* Let's avoid those nasty partial register stalls */
+	//raw_mov_b_mr((uae_u32)live.state[FLAGTMP].mem,r);
+	raw_mov_b_mr(((uae_u32)live.state[FLAGTMP].mem)+1,r+4);
+	//live.state[FLAGTMP].status=CLEAN;
+	live.state[FLAGTMP].status=INMEM;
+	live.state[FLAGTMP].realreg=-1;
+	/* We just "evicted" FLAGTMP. */
+	if (live.nat[r].nholds!=1) {
+		/* Huh? */
+		abort();
+	}
+	live.nat[r].nholds=0;
+#endif
+}
+
+#define FLAG_NREG2 0  /* Set to -1 if any register will do */
+STATIC_INLINE void raw_reg_to_flags(int r)
+{
+	raw_cmp_b_ri(r,-127); /* set V */
+	raw_sahf(0);
+}
+
+/* Apparently, there are enough instructions between flag store and
+flag reload to avoid the partial memory stall */
+STATIC_INLINE void raw_load_flagreg(uae_u32 target, uae_u32 r)
+{
+#if 1
+	raw_mov_l_rm(target,(uae_u32)live.state[r].mem);
+#else
+	raw_mov_b_rm(target,(uae_u32)live.state[r].mem);
+	raw_mov_b_rm(target+4,((uae_u32)live.state[r].mem)+1);
+#endif
+}
+
+/* FLAGX is word-sized */
+STATIC_INLINE void raw_load_flagx(uae_u32 target, uae_u32 r)
+{
+	if (live.nat[target].canword)
+		raw_mov_w_rm(target,(uae_u32)live.state[r].mem);
+	else
+		raw_mov_l_rm(target,(uae_u32)live.state[r].mem);
+}
+
+#define NATIVE_FLAG_Z 0x40
+#define NATIVE_CC_EQ  4
+STATIC_INLINE void raw_flags_set_zero(int f, int r, int t)
+{
+	// FIXME: this is really suboptimal
+	raw_pushfl();
+	raw_pop_l_r(f);
+	raw_and_l_ri(f,~NATIVE_FLAG_Z);
+	raw_test_l_rr(r,r);
+	raw_mov_l_ri(r,0);
+	raw_mov_l_ri(t,NATIVE_FLAG_Z);
+	raw_cmov_l_rr(r,t,NATIVE_CC_EQ);
+	raw_or_l(f,r);
+	raw_push_l_r(f);
+	raw_popfl();
+}
+
+STATIC_INLINE void raw_inc_sp(int off)
+{
+	raw_add_l_ri(4,off);
+}
+
+/*************************************************************************
+* Handling mistaken direct memory access                                *
+*************************************************************************/
+
+
+#ifdef NATMEM_OFFSET
+#ifdef _WIN32 // %%% BRIAN KING WAS HERE %%%
+#include 
+#else
+#include 
+#endif
+#include 
+
+#define SIG_READ 1
+#define SIG_WRITE 2
+
+static int in_handler=0;
+static uae_u8 *veccode;
+
+#ifdef _WIN32
+
+#if defined(CPU_64_BIT)
+#define ctxPC (pContext->Rip)
+#else
+#define ctxPC (pContext->Eip)
+#endif
+
+int EvalException (LPEXCEPTION_POINTERS blah, int n_except)
+{
+	PEXCEPTION_RECORD pExceptRecord = NULL;
+	PCONTEXT          pContext = NULL;
+
+	uae_u8* i = NULL;
+	uae_u32 addr = 0;
+	int r=-1;
+	int size=4;
+	int dir=-1;
+	int len=0;
+
+	if (n_except != STATUS_ACCESS_VIOLATION || !canbang || currprefs.cachesize == 0)
+		return EXCEPTION_CONTINUE_SEARCH;
+
+	pExceptRecord = blah->ExceptionRecord;
+	pContext = blah->ContextRecord;
+
+	if (pContext)
+		i = (uae_u8 *)ctxPC;
+	if (pExceptRecord)
+		addr = (uae_u32)(pExceptRecord->ExceptionInformation[1]);
+#ifdef JIT_DEBUG
+	write_log (_T("JIT: fault address is 0x%x at 0x%x\n"),addr,i);
+#endif
+	if (!canbang || !currprefs.cachesize)
+		return EXCEPTION_CONTINUE_SEARCH;
+
+	if (in_handler)
+		write_log (_T("JIT: Argh --- Am already in a handler. Shouldn't happen!\n"));
+
+	if (canbang && i>=compiled_code && i<=current_compile_p) {
+		if (*i==0x66) {
+			i++;
+			size=2;
+			len++;
+		}
+
+		switch(i[0]) {
+		case 0x8a:
+			if ((i[1]&0xc0)==0x80) {
+				r=(i[1]>>3)&7;
+				dir=SIG_READ;
+				size=1;
+				len+=6;
+				break;
+			}
+			break;
+		case 0x88:
+			if ((i[1]&0xc0)==0x80) {
+				r=(i[1]>>3)&7;
+				dir=SIG_WRITE;
+				size=1;
+				len+=6;
+				break;
+			}
+			break;
+		case 0x8b:
+			switch(i[1]&0xc0) {
+			case 0x80:
+				r=(i[1]>>3)&7;
+				dir=SIG_READ;
+				len+=6;
+				break;
+			case 0x40:
+				r=(i[1]>>3)&7;
+				dir=SIG_READ;
+				len+=3;
+				break;
+			case 0x00:
+				r=(i[1]>>3)&7;
+				dir=SIG_READ;
+				len+=2;
+				break;
+			default:
+				break;
+			}
+			break;
+		case 0x89:
+			switch(i[1]&0xc0) {
+			case 0x80:
+				r=(i[1]>>3)&7;
+				dir=SIG_WRITE;
+				len+=6;
+				break;
+			case 0x40:
+				r=(i[1]>>3)&7;
+				dir=SIG_WRITE;
+				len+=3;
+				break;
+			case 0x00:
+				r=(i[1]>>3)&7;
+				dir=SIG_WRITE;
+				len+=2;
+				break;
+			}
+			break;
+		}
+	}
+
+	if (r!=-1) {
+		void* pr=NULL;
+#ifdef JIT_DEBUG
+		write_log (_T("JIT: register was %d, direction was %d, size was %d\n"),r,dir,size);
+#endif
+
+		switch(r) {
+#if defined(CPU_64_BIT)
+		case 0: pr=&(pContext->Rax); break;
+		case 1: pr=&(pContext->Rcx); break;
+		case 2: pr=&(pContext->Rdx); break;
+		case 3: pr=&(pContext->Rbx); break;
+		case 4: pr=(size>1)?NULL:(((uae_u8*)&(pContext->Rax))+1); break;
+		case 5: pr=(size>1)?
+					(void*)(&(pContext->Rbp)):
+			(void*)(((uae_u8*)&(pContext->Rcx))+1); break;
+		case 6: pr=(size>1)?
+					(void*)(&(pContext->Rsi)):
+			(void*)(((uae_u8*)&(pContext->Rdx))+1); break;
+		case 7: pr=(size>1)?
+					(void*)(&(pContext->Rdi)):
+			(void*)(((uae_u8*)&(pContext->Rbx))+1); break;
+#else
+		case 0: pr=&(pContext->Eax); break;
+		case 1: pr=&(pContext->Ecx); break;
+		case 2: pr=&(pContext->Edx); break;
+		case 3: pr=&(pContext->Ebx); break;
+		case 4: pr=(size>1)?NULL:(((uae_u8*)&(pContext->Eax))+1); break;
+		case 5: pr=(size>1)?
+					(void*)(&(pContext->Ebp)):
+			(void*)(((uae_u8*)&(pContext->Ecx))+1); break;
+		case 6: pr=(size>1)?
+					(void*)(&(pContext->Esi)):
+			(void*)(((uae_u8*)&(pContext->Edx))+1); break;
+		case 7: pr=(size>1)?
+					(void*)(&(pContext->Edi)):
+			(void*)(((uae_u8*)&(pContext->Ebx))+1); break;
+#endif
+		default: abort();
+		}
+		if (pr) {
+			blockinfo* bi;
+
+			if (currprefs.comp_oldsegv) {
+				addr-=(uae_u32)NATMEM_OFFSET;
+
+#ifdef JIT_DEBUG
+				if ((addr>=0x10000000 && addr<0x40000000) ||
+					(addr>=0x50000000)) {
+						write_log (_T("JIT: Suspicious address 0x%x in SEGV handler.\n"),addr);
+				}
+#endif
+				if (dir==SIG_READ) {
+					switch (size) {
+					case 1: *((uae_u8*)pr)=get_byte (addr); break;
+					case 2: *((uae_u16*)pr)=swap16(get_word (addr)); break;
+					case 4: *((uae_u32*)pr)=swap32(get_long (addr)); break;
+					default: abort();
+					}
+				}
+				else { /* write */
+					switch (size) {
+					case 1: put_byte (addr,*((uae_u8*)pr)); break;
+					case 2: put_word (addr,swap16(*((uae_u16*)pr))); break;
+					case 4: put_long (addr,swap32(*((uae_u32*)pr))); break;
+					default: abort();
+					}
+				}
+#ifdef JIT_DEBUG
+				write_log (_T("JIT: Handled one access!\n"));
+#endif
+				fflush(stdout);
+				segvcount++;
+				ctxPC+=len;
+			}
+			else {
+				void* tmp=target;
+				int i;
+				uae_u8 vecbuf[5];
+
+				addr-=(uae_u32)NATMEM_OFFSET;
+
+#ifdef JIT_DEBUG
+				if ((addr>=0x10000000 && addr<0x40000000) ||
+					(addr>=0x50000000)) {
+						write_log (_T("JIT: Suspicious address 0x%x in SEGV handler.\n"),addr);
+				}
+#endif
+
+				target=(uae_u8*)ctxPC;
+				for (i=0;i<5;i++)
+					vecbuf[i]=target[i];
+				emit_byte(0xe9);
+				emit_long((uae_u32)veccode-(uae_u32)target-4);
+#ifdef JIT_DEBUG
+
+				write_log (_T("JIT: Create jump to %p\n"),veccode);
+				write_log (_T("JIT: Handled one access!\n"));
+#endif
+				segvcount++;
+
+				target=veccode;
+
+				if (dir==SIG_READ) {
+					switch(size) {
+					case 1: raw_mov_b_ri(r,get_byte (addr)); break;
+					case 2: raw_mov_w_ri(r,swap16(get_word (addr))); break;
+					case 4: raw_mov_l_ri(r,swap32(get_long (addr))); break;
+					default: abort();
+					}
+				}
+				else { /* write */
+					switch(size) {
+					case 1: put_byte (addr,*((uae_u8*)pr)); break;
+					case 2: put_word (addr,swap16(*((uae_u16*)pr))); break;
+					case 4: put_long (addr,swap32(*((uae_u32*)pr))); break;
+					default: abort();
+					}
+				}
+				for (i=0;i<5;i++)
+					raw_mov_b_mi(ctxPC+i,vecbuf[i]);
+				raw_mov_l_mi((uae_u32)&in_handler,0);
+				emit_byte(0xe9);
+				emit_long(ctxPC+len-(uae_u32)target-4);
+				in_handler=1;
+				target=(uae_u8*)tmp;
+			}
+			bi=active;
+			while (bi) {
+				if (bi->handler &&
+					(uae_u8*)bi->direct_handler<=i &&
+					(uae_u8*)bi->nexthandler>i) {
+#ifdef JIT_DEBUG
+						write_log (_T("JIT: deleted trigger (%p<%p<%p) %p\n"),
+							bi->handler,
+							i,
+							bi->nexthandler,
+							bi->pc_p);
+#endif
+						invalidate_block(bi);
+						raise_in_cl_list(bi);
+						set_special(0);
+						return EXCEPTION_CONTINUE_EXECUTION;
+				}
+				bi=bi->next;
+			}
+			/* Not found in the active list. Might be a rom routine that
+			is in the dormant list */
+			bi=dormant;
+			while (bi) {
+				if (bi->handler &&
+					(uae_u8*)bi->direct_handler<=i &&
+					(uae_u8*)bi->nexthandler>i) {
+#ifdef JIT_DEBUG
+						write_log (_T("JIT: deleted trigger (%p<%p<%p) %p\n"),
+							bi->handler,
+							i,
+							bi->nexthandler,
+							bi->pc_p);
+#endif
+						invalidate_block(bi);
+						raise_in_cl_list(bi);
+						set_special(0);
+						return EXCEPTION_CONTINUE_EXECUTION;
+				}
+				bi=bi->next;
+			}
+#ifdef JIT_DEBUG
+			write_log (_T("JIT: Huh? Could not find trigger!\n"));
+#endif
+			return EXCEPTION_CONTINUE_EXECUTION;
+		}
+	}
+	write_log (_T("JIT: Can't handle access %08X!\n"), i);
+#if 0
+	if (i)
+	{
+		int j;
+
+		for (j=0;j<10;j++) {
+			write_log (_T("JIT: instruction byte %2d is 0x%02x\n"),j,i[j]);
+		}
+	}
+	write_log (_T("Please send the above info (starting at \"fault address\") to\n")
+		_T("bmeyer@csse.monash.edu.au\n")
+		_T("This shouldn't happen ;-)\n"));
+#endif
+	return EXCEPTION_CONTINUE_SEARCH;
+}
+#else
+static void vec(int x, struct sigcontext sc)
+{
+	uae_u8* i=(uae_u8*)sc.eip;
+	uae_u32 addr=sc.cr2;
+	int r=-1;
+	int size=4;
+	int dir=-1;
+	int len=0;
+	int j;
+
+	write_log (_T("JIT: fault address is %08x at %08x\n"),sc.cr2,sc.eip);
+	if (!canbang)
+		write_log (_T("JIT: Not happy! Canbang is 0 in SIGSEGV handler!\n"));
+	if (in_handler)
+		write_log (_T("JIT: Argh --- Am already in a handler. Shouldn't happen!\n"));
+
+	if (canbang && i>=compiled_code && i<=current_compile_p) {
+		if (*i==0x66) {
+			i++;
+			size=2;
+			len++;
+		}
+
+		switch(i[0]) {
+		case 0x8a:
+			if ((i[1]&0xc0)==0x80) {
+				r=(i[1]>>3)&7;
+				dir=SIG_READ;
+				size=1;
+				len+=6;
+				break;
+			}
+			break;
+		case 0x88:
+			if ((i[1]&0xc0)==0x80) {
+				r=(i[1]>>3)&7;
+				dir=SIG_WRITE;
+				size=1;
+				len+=6;
+				break;
+			}
+			break;
+
+		case 0x8b:
+			switch(i[1]&0xc0) {
+			case 0x80:
+				r=(i[1]>>3)&7;
+				dir=SIG_READ;
+				len+=6;
+				break;
+			case 0x40:
+				r=(i[1]>>3)&7;
+				dir=SIG_READ;
+				len+=3;
+				break;
+			case 0x00:
+				r=(i[1]>>3)&7;
+				dir=SIG_READ;
+				len+=2;
+				break;
+			default:
+				break;
+			}
+			break;
+
+		case 0x89:
+			switch(i[1]&0xc0) {
+			case 0x80:
+				r=(i[1]>>3)&7;
+				dir=SIG_WRITE;
+				len+=6;
+				break;
+			case 0x40:
+				r=(i[1]>>3)&7;
+				dir=SIG_WRITE;
+				len+=3;
+				break;
+			case 0x00:
+				r=(i[1]>>3)&7;
+				dir=SIG_WRITE;
+				len+=2;
+				break;
+			}
+			break;
+		}
+	}
+
+	if (r!=-1) {
+		void* pr=NULL;
+		write_log (_T("JIT: register was %d, direction was %d, size was %d\n"),r,dir,size);
+
+		switch(r) {
+		case 0: pr=&(sc.eax); break;
+		case 1: pr=&(sc.ecx); break;
+		case 2: pr=&(sc.edx); break;
+		case 3: pr=&(sc.ebx); break;
+		case 4: pr=(size>1)?NULL:(((uae_u8*)&(sc.eax))+1); break;
+		case 5: pr=(size>1)?
+					(void*)(&(sc.ebp)):
+			(void*)(((uae_u8*)&(sc.ecx))+1); break;
+		case 6: pr=(size>1)?
+					(void*)(&(sc.esi)):
+			(void*)(((uae_u8*)&(sc.edx))+1); break;
+		case 7: pr=(size>1)?
+					(void*)(&(sc.edi)):
+			(void*)(((uae_u8*)&(sc.ebx))+1); break;
+		default: abort();
+		}
+		if (pr) {
+			blockinfo* bi;
+
+			if (currprefs.comp_oldsegv) {
+				addr-=NATMEM_OFFSET;
+
+				if ((addr>=0x10000000 && addr<0x40000000) ||
+					(addr>=0x50000000)) {
+						write_log (_T("JIT: Suspicious address in %x SEGV handler.\n"),addr);
+				}
+				if (dir==SIG_READ) {
+					switch(size) {
+					case 1: *((uae_u8*)pr)=get_byte (addr); break;
+					case 2: *((uae_u16*)pr)=get_word (addr); break;
+					case 4: *((uae_u32*)pr)=get_long (addr); break;
+					default: abort();
+					}
+				}
+				else { /* write */
+					switch(size) {
+					case 1: put_byte (addr,*((uae_u8*)pr)); break;
+					case 2: put_word (addr,*((uae_u16*)pr)); break;
+					case 4: put_long (addr,*((uae_u32*)pr)); break;
+					default: abort();
+					}
+				}
+				write_log (_T("JIT: Handled one access!\n"));
+				fflush(stdout);
+				segvcount++;
+				sc.eip+=len;
+			}
+			else {
+				void* tmp=target;
+				int i;
+				uae_u8 vecbuf[5];
+
+				addr-=NATMEM_OFFSET;
+
+				if ((addr>=0x10000000 && addr<0x40000000) ||
+					(addr>=0x50000000)) {
+						write_log (_T("JIT: Suspicious address 0x%x in SEGV handler.\n"),addr);
+				}
+
+				target=(uae_u8*)sc.eip;
+				for (i=0;i<5;i++)
+					vecbuf[i]=target[i];
+				emit_byte(0xe9);
+				emit_long((uae_u32)veccode-(uae_u32)target-4);
+				write_log (_T("JIT: Create jump to %p\n"),veccode);
+
+				write_log (_T("JIT: Handled one access!\n"));
+				segvcount++;
+
+				target=veccode;
+
+				if (dir==SIG_READ) {
+					switch(size) {
+					case 1: raw_mov_b_ri(r,get_byte (addr)); break;
+					case 2: raw_mov_w_ri(r,get_word (addr)); break;
+					case 4: raw_mov_l_ri(r,get_long (addr)); break;
+					default: abort();
+					}
+				}
+				else { /* write */
+					switch(size) {
+					case 1: put_byte (addr,*((uae_u8*)pr)); break;
+					case 2: put_word (addr,*((uae_u16*)pr)); break;
+					case 4: put_long (addr,*((uae_u32*)pr)); break;
+					default: abort();
+					}
+				}
+				for (i=0;i<5;i++)
+					raw_mov_b_mi(sc.eip+i,vecbuf[i]);
+				raw_mov_l_mi((uae_u32)&in_handler,0);
+				emit_byte(0xe9);
+				emit_long(sc.eip+len-(uae_u32)target-4);
+				in_handler=1;
+				target=tmp;
+			}
+			bi=active;
+			while (bi) {
+				if (bi->handler &&
+					(uae_u8*)bi->direct_handler<=i &&
+					(uae_u8*)bi->nexthandler>i) {
+						write_log (_T("JIT: deleted trigger (%p<%p<%p) %p\n"),
+							bi->handler,
+							i,
+							bi->nexthandler,
+							bi->pc_p);
+						invalidate_block(bi);
+						raise_in_cl_list(bi);
+						set_special(0);
+						return;
+				}
+				bi=bi->next;
+			}
+			/* Not found in the active list. Might be a rom routine that
+			is in the dormant list */
+			bi=dormant;
+			while (bi) {
+				if (bi->handler &&
+					(uae_u8*)bi->direct_handler<=i &&
+					(uae_u8*)bi->nexthandler>i) {
+						write_log (_T("JIT: deleted trigger (%p<%p<%p) %p\n"),
+							bi->handler,
+							i,
+							bi->nexthandler,
+							bi->pc_p);
+						invalidate_block(bi);
+						raise_in_cl_list(bi);
+						set_special(0);
+						return;
+				}
+				bi=bi->next;
+			}
+			write_log (_T("JIT: Huh? Could not find trigger!\n"));
+			return;
+		}
+	}
+	write_log (_T("JIT: Can't handle access!\n"));
+	for (j=0;j<10;j++) {
+		write_log (_T("JIT: instruction byte %2d is %02x\n"),j,i[j]);
+	}
+#if 0
+	write_log (_T("Please send the above info (starting at \"fault address\") to\n")
+		"bmeyer@csse.monash.edu.au\n"
+		"This shouldn't happen ;-)\n");
+	fflush(stdout);
+#endif
+	signal(SIGSEGV,SIG_DFL);  /* returning here will cause a "real" SEGV */
+}
+#endif
+#endif
+
+/*************************************************************************
+* Checking for CPU features                                             *
+*************************************************************************/
+
+struct cpuinfo_x86 {
+	uae_u8	x86;			// CPU family
+	uae_u8	x86_vendor;		// CPU vendor
+	uae_u8	x86_processor;	// CPU canonical processor type
+	uae_u8	x86_brand_id;	// CPU BrandID if supported, yield 0 otherwise
+	uae_u32	x86_hwcap;
+	uae_u8	x86_model;
+	uae_u8	x86_mask;
+	int		cpuid_level;    // Maximum supported CPUID level, -1=no CPUID
+	char		x86_vendor_id[16];
+};
+struct cpuinfo_x86 cpuinfo;
+
+enum {
+	X86_VENDOR_INTEL		= 0,
+	X86_VENDOR_CYRIX		= 1,
+	X86_VENDOR_AMD		= 2,
+	X86_VENDOR_UMC		= 3,
+	X86_VENDOR_NEXGEN		= 4,
+	X86_VENDOR_CENTAUR	= 5,
+	X86_VENDOR_RISE		= 6,
+	X86_VENDOR_TRANSMETA	= 7,
+	X86_VENDOR_NSC		= 8,
+	X86_VENDOR_UNKNOWN	= 0xff
+};
+
+enum {
+	X86_PROCESSOR_I386,                       /* 80386 */
+	X86_PROCESSOR_I486,                       /* 80486DX, 80486SX, 80486DX[24] */
+	X86_PROCESSOR_PENTIUM,
+	X86_PROCESSOR_PENTIUMPRO,
+	X86_PROCESSOR_K6,
+	X86_PROCESSOR_ATHLON,
+	X86_PROCESSOR_PENTIUM4,
+	X86_PROCESSOR_K8,
+	X86_PROCESSOR_max
+};
+
+static struct ptt {
+	const int align_loop;
+	const int align_loop_max_skip;
+	const int align_jump;
+	const int align_jump_max_skip;
+	const int align_func;
+}
+x86_alignments[X86_PROCESSOR_max + 1] = {
+	{  4,  3,  4,  3,  4 },
+	{ 16, 15, 16, 15, 16 },
+	{ 16,  7, 16,  7, 16 },
+	{ 16, 15, 16,  7, 16 },
+	{ 32,  7, 32,  7, 32 },
+	{ 16,  7, 16,  7, 16 },
+	{  0,  0,  0,  0,  0 },
+	{ 16,  7, 16,  7, 16 },
+	{  0,  0,  0,  0,  0 }
+};
+
+static void
+	x86_get_cpu_vendor(struct cpuinfo_x86 *c)
+{
+	char *v = c->x86_vendor_id;
+
+	if (!strcmp(v, "GenuineIntel"))
+		c->x86_vendor = X86_VENDOR_INTEL;
+	else if (!strcmp(v, "AuthenticAMD"))
+		c->x86_vendor = X86_VENDOR_AMD;
+	else if (!strcmp(v, "CyrixInstead"))
+		c->x86_vendor = X86_VENDOR_CYRIX;
+	else if (!strcmp(v, "Geode by NSC"))
+		c->x86_vendor = X86_VENDOR_NSC;
+	else if (!strcmp(v, "UMC UMC UMC "))
+		c->x86_vendor = X86_VENDOR_UMC;
+	else if (!strcmp(v, "CentaurHauls"))
+		c->x86_vendor = X86_VENDOR_CENTAUR;
+	else if (!strcmp(v, "NexGenDriven"))
+		c->x86_vendor = X86_VENDOR_NEXGEN;
+	else if (!strcmp(v, "RiseRiseRise"))
+		c->x86_vendor = X86_VENDOR_RISE;
+	else if (!strcmp(v, "GenuineTMx86") ||
+		!strcmp(v, "TransmetaCPU"))
+		c->x86_vendor = X86_VENDOR_TRANSMETA;
+	else
+		c->x86_vendor = X86_VENDOR_UNKNOWN;
+}
+
+static void cpuid(uae_u32 op, uae_u32 *eax, uae_u32 *ebx, uae_u32 *ecx, uae_u32 *edx)
+{
+	const int CPUID_SPACE = 4096;
+	uae_u8* cpuid_space = (uae_u8*)cache_alloc(CPUID_SPACE);
+	static uae_u32 s_op, s_eax, s_ebx, s_ecx, s_edx;
+	uae_u8* tmp=get_target();
+
+	s_op = op;
+	set_target(cpuid_space);
+	raw_push_l_r(0); /* eax */
+	raw_push_l_r(1); /* ecx */
+	raw_push_l_r(2); /* edx */
+	raw_push_l_r(3); /* ebx */
+	raw_mov_l_rm(0,(uintptr)&s_op);
+	raw_cpuid(0);
+	raw_mov_l_mr((uintptr)&s_eax,0);
+	raw_mov_l_mr((uintptr)&s_ebx,3);
+	raw_mov_l_mr((uintptr)&s_ecx,1);
+	raw_mov_l_mr((uintptr)&s_edx,2);
+	raw_pop_l_r(3);
+	raw_pop_l_r(2);
+	raw_pop_l_r(1);
+	raw_pop_l_r(0);
+	raw_ret();
+	set_target(tmp);
+
+	((compop_func*)cpuid_space)(0);
+	if (eax != NULL) *eax = s_eax;
+	if (ebx != NULL) *ebx = s_ebx;
+	if (ecx != NULL) *ecx = s_ecx;
+	if (edx != NULL) *edx = s_edx;
+
+	cache_free (cpuid_space);
+}
+
+static void raw_init_cpu(void)
+{
+	struct cpuinfo_x86 *c = &cpuinfo;
+	uae_u32 xlvl;
+
+	/* Defaults */
+	c->x86_processor = X86_PROCESSOR_max;
+	c->x86_vendor = X86_VENDOR_UNKNOWN;
+	c->cpuid_level = -1;				/* CPUID not detected */
+	c->x86_model = c->x86_mask = 0;	/* So far unknown... */
+	c->x86_vendor_id[0] = '\0';		/* Unset */
+	c->x86_hwcap = 0;
+
+	/* Get vendor name */
+	c->x86_vendor_id[12] = '\0';
+	cpuid(0x00000000,
+		(uae_u32 *)&c->cpuid_level,
+		(uae_u32 *)&c->x86_vendor_id[0],
+		(uae_u32 *)&c->x86_vendor_id[8],
+		(uae_u32 *)&c->x86_vendor_id[4]);
+	x86_get_cpu_vendor(c);
+
+	/* Intel-defined flags: level 0x00000001 */
+	c->x86_brand_id = 0;
+	if ( c->cpuid_level >= 0x00000001 ) {
+		uae_u32 tfms, brand_id;
+		cpuid(0x00000001, &tfms, &brand_id, NULL, &c->x86_hwcap);
+		c->x86 = (tfms >> 8) & 15;
+		c->x86_model = (tfms >> 4) & 15;
+		c->x86_brand_id = brand_id & 0xff;
+		if ( (c->x86_vendor == X86_VENDOR_AMD) &&
+			(c->x86 == 0xf)) {
+				/* AMD Extended Family and Model Values */
+				c->x86 += (tfms >> 20) & 0xff;
+				c->x86_model += (tfms >> 12) & 0xf0;
+		}
+		c->x86_mask = tfms & 15;
+	} else {
+		/* Have CPUID level 0 only - unheard of */
+		c->x86 = 4;
+	}
+
+	/* AMD-defined flags: level 0x80000001 */
+	cpuid(0x80000000, &xlvl, NULL, NULL, NULL);
+	if ( (xlvl & 0xffff0000) == 0x80000000 ) {
+		if ( xlvl >= 0x80000001 ) {
+			uae_u32 features;
+			cpuid(0x80000001, NULL, NULL, NULL, &features);
+			if (features & (1 << 29)) {
+				/* Assume x86-64 if long mode is supported */
+				c->x86_processor = X86_PROCESSOR_K8;
+			}
+		}
+	}
+
+	/* Canonicalize processor ID */
+	switch (c->x86) {
+	case 3:
+		c->x86_processor = X86_PROCESSOR_I386;
+		break;
+	case 4:
+		c->x86_processor = X86_PROCESSOR_I486;
+		break;
+	case 5:
+		if (c->x86_vendor == X86_VENDOR_AMD)
+			c->x86_processor = X86_PROCESSOR_K6;
+		else
+			c->x86_processor = X86_PROCESSOR_PENTIUM;
+		break;
+	case 6:
+		if (c->x86_vendor == X86_VENDOR_AMD)
+			c->x86_processor = X86_PROCESSOR_ATHLON;
+		else
+			c->x86_processor = X86_PROCESSOR_PENTIUMPRO;
+		break;
+	case 15:
+		if (c->x86_vendor == X86_VENDOR_INTEL) {
+			/* Assume any BrandID >= 8 and family == 15 yields a Pentium 4 */
+			if (c->x86_brand_id >= 8)
+				c->x86_processor = X86_PROCESSOR_PENTIUM4;
+		}
+		if (c->x86_vendor == X86_VENDOR_AMD) {
+			/* Assume an Athlon processor if family == 15 and it was not
+			detected as an x86-64 so far */
+			if (c->x86_processor == X86_PROCESSOR_max)
+				c->x86_processor = X86_PROCESSOR_ATHLON;
+		}
+		break;
+	}
+
+	/* Have CMOV support? */
+	have_cmov = c->x86_hwcap & (1 << 15);
+
+#if 0
+	/* Can the host CPU suffer from partial register stalls? */
+	have_rat_stall = (c->x86_vendor == X86_VENDOR_INTEL);
+	/* It appears that partial register writes are a bad idea even on
+	AMD K7 cores, even though they are not supposed to have the
+	dreaded rat stall. Why? Anyway, that's why we lie about it ;-) */
+	if (c->x86_processor == X86_PROCESSOR_ATHLON)
+		have_rat_stall = 1;
+#endif
+	have_rat_stall = 1;
+
+	/* Alignments */
+	if (tune_alignment) {
+		align_loops = x86_alignments[c->x86_processor].align_loop;
+		align_jumps = x86_alignments[c->x86_processor].align_jump;
+	}
+	{ 
+		TCHAR *s = au (c->x86_vendor_id);
+		write_log (_T("CPUID level=%d, Family=%d, Model=%d, Mask=%d, Vendor=%s [%d]\n"),
+			c->cpuid_level, c->x86, c->x86_model, c->x86_mask, s, c->x86_vendor);
+		xfree (s);
+	}
+}
+
+#if 0
+static int target_check_bsf(void)
+{
+	int mismatch = 0;
+	for (int g_ZF = 0; g_ZF <= 1; g_ZF++) {
+		for (int g_CF = 0; g_CF <= 1; g_CF++) {
+			for (int g_OF = 0; g_OF <= 1; g_OF++) {
+				for (int g_SF = 0; g_SF <= 1; g_SF++) {
+					for (int value = -1; value <= 1; value++) {
+						unsigned long flags = (g_SF << 7) | (g_OF << 11) | (g_ZF << 6) | g_CF;
+						unsigned long tmp = value;
+						__asm__ __volatile__ ("push %0; popf; bsf %1,%1; pushf; pop %0"
+							: "+r" (flags), "+r" (tmp) : : "cc");
+						int OF = (flags >> 11) & 1;
+						int SF = (flags >>  7) & 1;
+						int ZF = (flags >>  6) & 1;
+						int CF = flags & 1;
+						tmp = (value == 0);
+						if (ZF != tmp || SF != g_SF || OF != g_OF || CF != g_CF)
+							mismatch = true;
+					}
+				}}}}
+	if (mismatch)
+		write_log (_T("Target CPU defines all flags on BSF instruction\n"));
+	return !mismatch;
+}
+#endif
+
+#if 0
+
+/*************************************************************************
+* Checking for CPU features                                             *
+*************************************************************************/
+
+typedef struct {
+	uae_u32 eax;
+	uae_u32 ecx;
+	uae_u32 edx;
+	uae_u32 ebx;
+} x86_regs;
+
+
+/* This could be so much easier if it could make assumptions about the
+compiler... */
+
+static uae_u32 cpuid_ptr;
+static uae_u32 cpuid_level;
+
+static x86_regs cpuid(uae_u32 level)
+{
+	x86_regs answer;
+	uae_u8 *cpuid_space;
+	void* tmp=get_target();
+
+	cpuid_ptr=(uae_u32)&answer;
+	cpuid_level=level;
+
+	cpuid_space = cache_alloc (256);
+	set_target(cpuid_space);
+	raw_push_l_r(0); /* eax */
+	raw_push_l_r(1); /* ecx */
+	raw_push_l_r(2); /* edx */
+	raw_push_l_r(3); /* ebx */
+	raw_push_l_r(7); /* edi */
+	raw_mov_l_rm(0,(uae_u32)&cpuid_level);
+	raw_cpuid(0);
+	raw_mov_l_rm(7,(uae_u32)&cpuid_ptr);
+	raw_mov_l_Rr(7,0,0);
+	raw_mov_l_Rr(7,1,4);
+	raw_mov_l_Rr(7,2,8);
+	raw_mov_l_Rr(7,3,12);
+	raw_pop_l_r(7);
+	raw_pop_l_r(3);
+	raw_pop_l_r(2);
+	raw_pop_l_r(1);
+	raw_pop_l_r(0);
+	raw_ret();
+	set_target(tmp);
+
+	((cpuop_func*)cpuid_space)(0);
+	cache_free (cpuid_space);
+	return answer;
+}
+
+static void raw_init_cpu(void)
+{
+	x86_regs x;
+	uae_u32 maxlev;
+
+	x=cpuid(0);
+	maxlev=x.eax;
+	write_log (_T("Max CPUID level=%d Processor is %c%c%c%c%c%c%c%c%c%c%c%c\n"),
+		maxlev,
+		x.ebx,
+		x.ebx>>8,
+		x.ebx>>16,
+		x.ebx>>24,
+		x.edx,
+		x.edx>>8,
+		x.edx>>16,
+		x.edx>>24,
+		x.ecx,
+		x.ecx>>8,
+		x.ecx>>16,
+		x.ecx>>24
+		);
+	have_rat_stall=(x.ecx==0x6c65746e);
+
+	if (maxlev>=1) {
+		x=cpuid(1);
+		if (x.edx&(1<<15))
+			have_cmov=1;
+	}
+	have_rat_stall=1;
+#if 0
+	if (!have_cmov)
+		have_rat_stall=0;
+#endif
+#if 0
+	write_log (_T("have_cmov=%d, avoid_cmov=%d, have_rat_stall=%d\n"),
+		have_cmov,currprefs.avoid_cmov,have_rat_stall);
+	if (currprefs.avoid_cmov) {
+		write_log (_T("Disabling cmov use despite processor claiming to support it!\n"));
+		have_cmov=0;
+	}
+#else
+	/* Dear Bernie, I don't want to keep around options which are useless, and not
+	represented in the GUI anymore... Is this okay? */
+	write_log (_T("have_cmov=%d, have_rat_stall=%d\n"), have_cmov, have_rat_stall);
+#endif
+#if 0   /* For testing of non-cmov code! */
+	have_cmov=0;
+#endif
+#if 0 /* It appears that partial register writes are a bad idea even on
+	AMD K7 cores, even though they are not supposed to have the
+	dreaded rat stall. Why? Anyway, that's why we lie about it ;-) */
+	if (have_cmov)
+		have_rat_stall=1;
+#endif
+}
+#endif
+
+/*************************************************************************
+* FPU stuff                                                             *
+*************************************************************************/
+
+
+STATIC_INLINE void raw_fp_init(void)
+{
+	int i;
+
+	for (i=0;i1) {
+		emit_byte(0x9b);
+		emit_byte(0xdb);
+		emit_byte(0xe3);
+		live.tos=-1;
+	}
+#endif
+	while (live.tos>=1) {
+		emit_byte(0xde);
+		emit_byte(0xd9);
+		live.tos-=2;
+	}
+	while (live.tos>=0) {
+		emit_byte(0xdd);
+		emit_byte(0xd8);
+		live.tos--;
+	}
+	raw_fp_init();
+}
+
+STATIC_INLINE void make_tos(int r)
+{
+	int p,q;
+
+	if (live.spos[r]<0) { /* Register not yet on stack */
+		emit_byte(0xd9);
+		emit_byte(0xe8);  /* Push '1' on the stack, just to grow it */
+		live.tos++;
+		live.spos[r]=live.tos;
+		live.onstack[live.tos]=r;
+		return;
+	}
+	/* Register is on stack */
+	if (live.tos==live.spos[r])
+		return;
+	p=live.spos[r];
+	q=live.onstack[live.tos];
+
+	emit_byte(0xd9);
+	emit_byte(0xc8+live.tos-live.spos[r]);  /* exchange it with top of stack */
+	live.onstack[live.tos]=r;
+	live.spos[r]=live.tos;
+	live.onstack[p]=q;
+	live.spos[q]=p;
+}
+
+STATIC_INLINE int stackpos(int r)
+{
+	if (live.spos[r]<0)
+		abort();
+	if (live.tos=0) {
+		/* source is on top of stack, and we already have the dest */
+		int dd=stackpos(d);
+		emit_byte(0xdd);
+		emit_byte(0xd0+dd);
+	}
+	else {
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* duplicate source on tos */
+		tos_make(d); /* store to destination, pop if necessary */
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,READ,2,raw_fldcw_m_indexed,(R4 index, IMM base))
+{
+	emit_byte(0xd9);
+	emit_byte(0xa8+index);
+	emit_long(base);
+}
+LENDFUNC(NONE,READ,2,raw_fldcw_m_indexed,(R4 index, IMM base))
+
+	LOWFUNC(NONE,NONE,2,raw_fsqrt_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (d!=s) {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+		emit_byte(0xd9);
+		emit_byte(0xfa);    /* fsqrt sqrt(x) */
+		tos_make(d);        /* store to destination */
+	}
+	else {
+		make_tos(d);
+		emit_byte(0xd9);
+		emit_byte(0xfa);    /* fsqrt y=sqrt(x) */
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fsqrt_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fabs_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (d!=s) {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+		emit_byte(0xd9);
+		emit_byte(0xe1);    /* fabs abs(x) */
+		tos_make(d);        /* store to destination */
+	}
+	else {
+		make_tos(d);
+		emit_byte(0xd9);
+		emit_byte(0xe1);    /* fabs y=abs(x) */
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fabs_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_frndint_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (d!=s) {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+		emit_byte(0xd9);
+		emit_byte(0xfc);    /* frndint int(x) */
+		tos_make(d);        /* store to destination */
+	}
+	else {
+		make_tos(d);
+		emit_byte(0xd9);
+		emit_byte(0xfc);    /* frndint y=int(x) */
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_frndint_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fgetexp_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (d!=s) {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+		emit_byte(0xd9);
+		emit_byte(0xf4);    /* fxtract exp push man */
+		emit_byte(0xdd);
+		emit_byte(0xd8);    /* fstp just pop man */
+		tos_make(d);        /* store exp to destination */
+	}
+	else {
+		make_tos(d);        /* tos=x=y */
+		emit_byte(0xd9);
+		emit_byte(0xf4);    /* fxtract exp push man */
+		emit_byte(0xdd);
+		emit_byte(0xd8);    /* fstp just pop man */
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fgetexp_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fgetman_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (d!=s) {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+		emit_byte(0xd9);
+		emit_byte(0xf4);    /* fxtract exp push man */
+		emit_byte(0xdd);
+		emit_byte(0xd9);    /* fstp copy man up & pop */
+		tos_make(d);        /* store man to destination */
+	}
+	else {
+		make_tos(d);        /* tos=x=y */
+		emit_byte(0xd9);
+		emit_byte(0xf4);    /* fxtract exp push man */
+		emit_byte(0xdd);
+		emit_byte(0xd9);    /* fstp copy man up & pop */
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fgetman_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fsin_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (d!=s) {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+		emit_byte(0xd9);
+		emit_byte(0xfe);    /* fsin sin(x) */
+		tos_make(d);        /* store to destination */
+	}
+	else {
+		make_tos(d);
+		emit_byte(0xd9);
+		emit_byte(0xfe);    /* fsin y=sin(x) */
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fsin_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fcos_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (d!=s) {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+		emit_byte(0xd9);
+		emit_byte(0xff);    /* fcos cos(x) */
+		tos_make(d);        /* store to destination */
+	}
+	else {
+		make_tos(d);
+		emit_byte(0xd9);
+		emit_byte(0xff);    /* fcos y=cos(x) */
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fcos_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_ftan_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (d!=s) {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+		emit_byte(0xd9);
+		emit_byte(0xf2);    /* fptan tan(x)=y/1.0 */
+		emit_byte(0xdd);
+		emit_byte(0xd8);    /* fstp pop 1.0 */
+		tos_make(d);        /* store to destination */
+	}
+	else {
+		make_tos(d);
+		emit_byte(0xd9);
+		emit_byte(0xf2);    /* fptan tan(x)=y/1.0 */
+		emit_byte(0xdd);
+		emit_byte(0xd8);    /* fstp pop 1.0 */
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_ftan_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,3,raw_fsincos_rr,(FW d, FW c, FR s))
+{
+	int ds;
+
+	if (s==d) {
+		//write_log (_T("FSINCOS src = dest\n"));
+		make_tos(s);
+		emit_byte(0xd9);
+		emit_byte(0xfb); /* fsincos sin(x) push cos(x) */
+		tos_make(c);     /* store cos(x) to c */
+		return;
+	}
+
+	ds=stackpos(s);
+	emit_byte(0xd9);
+	emit_byte(0xc0+ds);  /* fld x */
+	emit_byte(0xd9);
+	emit_byte(0xfb);     /* fsincos sin(x) push cos(x) */
+	if (live.spos[c]<0) {
+		if (live.spos[d]<0) { /* occupy both regs directly */
+			live.tos++;
+			live.spos[d]=live.tos;
+			live.onstack[live.tos]=d; /* sin(x) comes first */
+			live.tos++;
+			live.spos[c]=live.tos;
+			live.onstack[live.tos]=c;
+		}
+		else {
+			emit_byte(0xd9);
+			emit_byte(0xc9); /* fxch swap cos(x) with sin(x) */
+			emit_byte(0xdd); /* store sin(x) to d & pop */
+			emit_byte(0xd8+(live.tos+2)-live.spos[d]);
+			live.tos++;      /* occupy a reg for cos(x) here */
+			live.spos[c]=live.tos;
+			live.onstack[live.tos]=c;
+		}
+	}
+	else {
+		emit_byte(0xdd); /* store cos(x) to c & pop */
+		emit_byte(0xd8+(live.tos+2)-live.spos[c]);
+		tos_make(d);     /* store sin(x) to destination */
+	}
+}
+LENDFUNC(NONE,NONE,3,raw_fsincos_rr,(FW d, FW c, FR s))
+
+	float one=1;
+
+LOWFUNC(NONE,NONE,2,raw_fscale_rr,(FRW d, FR s))
+{
+	int ds;
+
+	if (live.spos[d]==live.tos && live.spos[s]==live.tos-1) {
+		//write_log (_T("fscale found x in TOS-1 and y in TOS\n"));
+		emit_byte(0xd9);
+		emit_byte(0xfd);    /* fscale y*(2^x) */
+	}
+	else {
+		make_tos(s);        /* tos=x */
+		ds=stackpos(d);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld y */
+		emit_byte(0xd9);
+		emit_byte(0xfd);    /* fscale y*(2^x) */
+		tos_make(d);        /* store y=y*(2^x) */
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fscale_rr,(FRW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_ftwotox_rr,(FW d, FR s))
+{
+	int ds;
+
+	ds=stackpos(s);
+	emit_byte(0xd9);
+	emit_byte(0xc0+ds); /* fld x */
+	emit_byte(0xd9);
+	emit_byte(0xfc);    /* frndint int(x) */
+	emit_byte(0xd9);
+	emit_byte(0xc1+ds); /* fld x again */
+	emit_byte(0xd8);
+	emit_byte(0xe1);    /* fsub frac(x) = x - int(x) */
+	emit_byte(0xd9);
+	emit_byte(0xf0);    /* f2xm1 (2^frac(x))-1 */
+	emit_byte(0xd8);
+	emit_byte(0x05);
+	emit_long((uae_u32)&one); /* fadd (2^frac(x))-1 + 1 */
+	emit_byte(0xd9);
+	emit_byte(0xfd);    /* fscale (2^frac(x))*2^int(x) */
+	emit_byte(0xdd);
+	emit_byte(0xd9);    /* fstp copy & pop */
+	tos_make(d);        /* store y=2^x */
+}
+LENDFUNC(NONE,NONE,2,raw_ftwotox_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fetox_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (s==d)
+		make_tos(s);
+	else {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xea);    /* fldl2e log2(e) */
+	emit_byte(0xd8);
+	emit_byte(0xc9);    /* fmul x*log2(e) */
+	emit_byte(0xdd);
+	emit_byte(0xd1);    /* fst copy up */
+	emit_byte(0xd9);
+	emit_byte(0xfc);    /* frndint int(x*log2(e)) */
+	emit_byte(0xd9);
+	emit_byte(0xc9);    /* fxch swap top two elements */
+	emit_byte(0xd8);
+	emit_byte(0xe1);    /* fsub x*log2(e) - int(x*log2(e))  */
+	emit_byte(0xd9);
+	emit_byte(0xf0);    /* f2xm1 (2^frac(x))-1 */
+	emit_byte(0xd8);
+	emit_byte(0x05);
+	emit_long((uae_u32)&one);  /* fadd (2^frac(x))-1 + 1 */
+	emit_byte(0xd9);
+	emit_byte(0xfd);    /* fscale (2^frac(x))*2^int(x*log2(e)) */
+	emit_byte(0xdd);
+	emit_byte(0xd9);    /* fstp copy & pop */
+	if (s!=d)
+		tos_make(d);    /* store y=e^x */
+}
+LENDFUNC(NONE,NONE,2,raw_fetox_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fetoxM1_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (s==d)
+		make_tos(s);
+	else {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xea);    /* fldl2e log2(e) */
+	emit_byte(0xd8);
+	emit_byte(0xc9);    /* fmul x*log2(e) */
+	emit_byte(0xdd);
+	emit_byte(0xd1);    /* fst copy up */
+	emit_byte(0xd9);
+	emit_byte(0xfc);    /* frndint int(x*log2(e)) */
+	emit_byte(0xd9);
+	emit_byte(0xc9);    /* fxch swap top two elements */
+	emit_byte(0xd8);
+	emit_byte(0xe1);    /* fsub x*log2(e) - int(x*log2(e))  */
+	emit_byte(0xd9);
+	emit_byte(0xf0);    /* f2xm1 (2^frac(x))-1 */
+	emit_byte(0xd9);
+	emit_byte(0xfd);    /* fscale ((2^frac(x))-1)*2^int(x*log2(e)) */
+	emit_byte(0xdd);
+	emit_byte(0xd9);    /* fstp copy & pop */
+	if (s!=d)
+		tos_make(d);    /* store y=(e^x)-1 */
+}
+LENDFUNC(NONE,NONE,2,raw_fetoxM1_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_ftentox_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (s==d)
+		make_tos(s);
+	else {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xe9);    /* fldl2t log2(10) */
+	emit_byte(0xd8);
+	emit_byte(0xc9);    /* fmul x*log2(10) */
+	emit_byte(0xdd);
+	emit_byte(0xd1);    /* fst copy up */
+	emit_byte(0xd9);
+	emit_byte(0xfc);    /* frndint int(x*log2(10)) */
+	emit_byte(0xd9);
+	emit_byte(0xc9);    /* fxch swap top two elements */
+	emit_byte(0xd8);
+	emit_byte(0xe1);    /* fsub x*log2(10) - int(x*log2(10))  */
+	emit_byte(0xd9);
+	emit_byte(0xf0);    /* f2xm1 (2^frac(x))-1 */
+	emit_byte(0xd8);
+	emit_byte(0x05);
+	emit_long((uae_u32)&one);  /* fadd (2^frac(x))-1 + 1 */
+	emit_byte(0xd9);
+	emit_byte(0xfd);    /* fscale (2^frac(x))*2^int(x*log2(10)) */
+	emit_byte(0xdd);
+	emit_byte(0xd9);    /* fstp copy & pop */
+	if (s!=d)
+		tos_make(d);    /* store y=10^x */
+}
+LENDFUNC(NONE,NONE,2,raw_ftentox_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_flog2_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (s==d)
+		make_tos(s);
+	else {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xe8);    /* fld1 1 */
+	emit_byte(0xd9);
+	emit_byte(0xc9);    /* fxch swap 1 with x */
+	emit_byte(0xd9);
+	emit_byte(0xf1);    /* fyl2x 1*log2(x) */
+	if (s!=d)
+		tos_make(d);    /* store y=log2(x) */
+}
+LENDFUNC(NONE,NONE,2,raw_flog2_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_flogN_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (s==d)
+		make_tos(s);
+	else {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xed);    /* fldln2 logN(2) */
+	emit_byte(0xd9);
+	emit_byte(0xc9);    /* fxch swap logN(2) with x */
+	emit_byte(0xd9);
+	emit_byte(0xf1);    /* fyl2x logN(2)*log2(x) */
+	if (s!=d)
+		tos_make(d);    /* store y=logN(x) */
+}
+LENDFUNC(NONE,NONE,2,raw_flogN_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_flogNP1_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (s==d)
+		make_tos(s);
+	else {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xed);    /* fldln2 logN(2) */
+	emit_byte(0xd9);
+	emit_byte(0xc9);    /* fxch swap logN(2) with x */
+	emit_byte(0xd9);
+	emit_byte(0xf9);    /* fyl2xp1 logN(2)*log2(x+1) */
+	if (s!=d)
+		tos_make(d);    /* store y=logN(x+1) */
+}
+LENDFUNC(NONE,NONE,2,raw_flogNP1_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_flog10_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (s==d)
+		make_tos(s);
+	else {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xec);    /* fldlg2 log10(2) */
+	emit_byte(0xd9);
+	emit_byte(0xc9);    /* fxch swap log10(2) with x */
+	emit_byte(0xd9);
+	emit_byte(0xf1);    /* fyl2x log10(2)*log2(x) */
+	if (s!=d)
+		tos_make(d);    /* store y=log10(x) */
+}
+LENDFUNC(NONE,NONE,2,raw_flog10_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fasin_rr,(FW d, FR s))
+{
+	int ds;
+
+	ds=stackpos(s);
+	emit_byte(0xd9);
+	emit_byte(0xc0+ds); /* fld x */
+	emit_byte(0xd8);
+	emit_byte(0xc8);    /* fmul x*x */
+	emit_byte(0xd9);
+	emit_byte(0xe8);    /* fld 1.0 */
+	emit_byte(0xde);
+	emit_byte(0xe1);    /* fsubrp 1 - (x^2) */
+	emit_byte(0xd9);
+	emit_byte(0xfa);    /* fsqrt sqrt(1-(x^2)) */
+	emit_byte(0xd9);
+	emit_byte(0xc1+ds); /* fld x again */
+	emit_byte(0xd9);
+	emit_byte(0xc9);    /* fxch swap x with sqrt(1-(x^2))  */
+	emit_byte(0xd9);
+	emit_byte(0xf3);    /* fpatan atan(x/sqrt(1-(x^2))) & pop */
+	tos_make(d);        /* store y=asin(x) */
+}
+LENDFUNC(NONE,NONE,2,raw_fasin_rr,(FW d, FR s))
+
+	static uae_u32 pihalf[] = {0x2168c234, 0xc90fdaa2, 0x3fff}; // LSB=0 to get acos(1)=0
+LOWFUNC(NONE,NONE,2,raw_facos_rr,(FW d, FR s))
+{
+	int ds;
+
+	ds=stackpos(s);
+	emit_byte(0xd9);
+	emit_byte(0xc0+ds); /* fld x */
+	emit_byte(0xd8);
+	emit_byte(0xc8);    /* fmul x*x */
+	emit_byte(0xd9);
+	emit_byte(0xe8);    /* fld 1.0 */
+	emit_byte(0xde);
+	emit_byte(0xe1);    /* fsubrp 1 - (x^2) */
+	emit_byte(0xd9);
+	emit_byte(0xfa);    /* fsqrt sqrt(1-(x^2)) */
+	emit_byte(0xd9);
+	emit_byte(0xc1+ds); /* fld x again */
+	emit_byte(0xd9);
+	emit_byte(0xc9);    /* fxch swap x with sqrt(1-(x^2))  */
+	emit_byte(0xd9);
+	emit_byte(0xf3);    /* fpatan atan(x/sqrt(1-(x^2))) & pop */
+	emit_byte(0xdb);
+	emit_byte(0x2d);
+	emit_long((uae_u32)&pihalf); /* fld load pi/2 from pihalf */
+	emit_byte(0xde);
+	emit_byte(0xe1);    /* fsubrp pi/2 - asin(x) & pop */
+	tos_make(d);        /* store y=acos(x) */
+}
+LENDFUNC(NONE,NONE,2,raw_facos_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fatan_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (s==d)
+		make_tos(s);
+	else {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xe8);    /* fld 1.0 */
+	emit_byte(0xd9);
+	emit_byte(0xf3);    /* fpatan atan(x)/1  & pop*/
+	if (s!=d)
+		tos_make(d);    /* store y=atan(x) */
+}
+LENDFUNC(NONE,NONE,2,raw_fatan_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fatanh_rr,(FW d, FR s))
+{
+	int ds;
+
+	ds=stackpos(s);
+	emit_byte(0xd9);
+	emit_byte(0xc0+ds); /* fld x */
+	emit_byte(0xd9);
+	emit_byte(0xe8);    /* fld 1.0 */
+	emit_byte(0xdc);
+	emit_byte(0xc1);    /* fadd 1 + x */
+	emit_byte(0xd8);
+	emit_byte(0xe2+ds); /* fsub 1 - x */
+	emit_byte(0xde);
+	emit_byte(0xf9);    /* fdivp (1+x)/(1-x) */
+	emit_byte(0xd9);
+	emit_byte(0xed);    /* fldl2e logN(2) */
+	emit_byte(0xd9);
+	emit_byte(0xc9);    /* fxch swap logN(2) with (1+x)/(1-x) */
+	emit_byte(0xd9);
+	emit_byte(0xf1);    /* fyl2x logN(2)*log2((1+x)/(1-x)) pop */
+	emit_byte(0xd9);
+	emit_byte(0xe8);    /* fld 1.0 */
+	emit_byte(0xd9);
+	emit_byte(0xe0);    /* fchs -1.0 */
+	emit_byte(0xd9);
+	emit_byte(0xc9);    /* fxch swap */
+	emit_byte(0xd9);
+	emit_byte(0xfd);    /* fscale logN((1+x)/(1-x)) * 2^(-1) */
+	emit_byte(0xdd);
+	emit_byte(0xd9);    /* fstp copy & pop */
+	tos_make(d);        /* store y=atanh(x) */
+}
+LENDFUNC(NONE,NONE,2,raw_fatanh_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fsinh_rr,(FW d, FR s))
+{
+	int ds,tr;
+
+	tr=live.onstack[live.tos+3];
+	if (s==d)
+		make_tos(s);
+	else {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xea);     /* fldl2e log2(e) */
+	emit_byte(0xd8);
+	emit_byte(0xc9);     /* fmul x*log2(e) */
+	emit_byte(0xdd);
+	emit_byte(0xd1);     /* fst copy x*log2(e) */
+	if (tr>=0) {
+		emit_byte(0xd9);
+		emit_byte(0xca); /* fxch swap with temp-reg */
+		emit_byte(0x83);
+		emit_byte(0xc4);
+		emit_byte(0xf4); /* add -12 to esp */
+		emit_byte(0xdb);
+		emit_byte(0x3c);
+		emit_byte(0x24); /* fstp store temp-reg to [esp] & pop */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xe0);     /* fchs -x*log2(e) */
+	emit_byte(0xd9);
+	emit_byte(0xc0);     /* fld -x*log2(e) again */
+	emit_byte(0xd9);
+	emit_byte(0xfc);     /* frndint int(-x*log2(e)) */
+	emit_byte(0xd9);
+	emit_byte(0xc9);     /* fxch swap */
+	emit_byte(0xd8);
+	emit_byte(0xe1);     /* fsub -x*log2(e) - int(-x*log2(e))  */
+	emit_byte(0xd9);
+	emit_byte(0xf0);     /* f2xm1 (2^frac(x))-1 */
+	emit_byte(0xd8);
+	emit_byte(0x05);
+	emit_long((uae_u32)&one);  /* fadd (2^frac(x))-1 + 1 */
+	emit_byte(0xd9);
+	emit_byte(0xfd);     /* fscale (2^frac(x))*2^int(x*log2(e)) */
+	emit_byte(0xd9);
+	emit_byte(0xca);     /* fxch swap e^-x with x*log2(e) in tr */
+	emit_byte(0xdd);
+	emit_byte(0xd1);     /* fst copy x*log2(e) */
+	emit_byte(0xd9);
+	emit_byte(0xfc);     /* frndint int(x*log2(e)) */
+	emit_byte(0xd9);
+	emit_byte(0xc9);     /* fxch swap */
+	emit_byte(0xd8);
+	emit_byte(0xe1);     /* fsub x*log2(e) - int(x*log2(e))  */
+	emit_byte(0xd9);
+	emit_byte(0xf0);     /* f2xm1 (2^frac(x))-1 */
+	emit_byte(0xd8);
+	emit_byte(0x05);
+	emit_long((uae_u32)&one);  /* fadd (2^frac(x))-1 + 1 */
+	emit_byte(0xd9);
+	emit_byte(0xfd);     /* fscale (2^frac(x))*2^int(x*log2(e)) */
+	emit_byte(0xdd);
+	emit_byte(0xd9);     /* fstp copy e^x & pop */
+	if (tr>=0) {
+		emit_byte(0xdb);
+		emit_byte(0x2c);
+		emit_byte(0x24); /* fld load temp-reg from [esp] */
+		emit_byte(0xd9);
+		emit_byte(0xca); /* fxch swap temp-reg with e^-x in tr */
+		emit_byte(0xde);
+		emit_byte(0xe9); /* fsubp (e^x)-(e^-x) */
+		emit_byte(0x83);
+		emit_byte(0xc4);
+		emit_byte(0x0c); /* delayed add +12 to esp */
+	}
+	else {
+		emit_byte(0xde);
+		emit_byte(0xe1); /* fsubrp (e^x)-(e^-x) */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xe8);     /* fld 1.0 */
+	emit_byte(0xd9);
+	emit_byte(0xe0);     /* fchs -1.0 */
+	emit_byte(0xd9);
+	emit_byte(0xc9);     /* fxch swap */
+	emit_byte(0xd9);
+	emit_byte(0xfd);     /* fscale ((e^x)-(e^-x))/2 */
+	emit_byte(0xdd);
+	emit_byte(0xd9);     /* fstp copy & pop */
+	if (s!=d)
+		tos_make(d);     /* store y=sinh(x) */
+}
+LENDFUNC(NONE,NONE,2,raw_fsinh_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fcosh_rr,(FW d, FR s))
+{
+	int ds,tr;
+
+	tr=live.onstack[live.tos+3];
+	if (s==d)
+		make_tos(s);
+	else {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xea);     /* fldl2e log2(e) */
+	emit_byte(0xd8);
+	emit_byte(0xc9);     /* fmul x*log2(e) */
+	emit_byte(0xdd);
+	emit_byte(0xd1);     /* fst copy x*log2(e) */
+	if (tr>=0) {
+		emit_byte(0xd9);
+		emit_byte(0xca); /* fxch swap with temp-reg */
+		emit_byte(0x83);
+		emit_byte(0xc4);
+		emit_byte(0xf4); /* add -12 to esp */
+		emit_byte(0xdb);
+		emit_byte(0x3c);
+		emit_byte(0x24); /* fstp store temp-reg to [esp] & pop */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xe0);     /* fchs -x*log2(e) */
+	emit_byte(0xd9);
+	emit_byte(0xc0);     /* fld -x*log2(e) again */
+	emit_byte(0xd9);
+	emit_byte(0xfc);     /* frndint int(-x*log2(e)) */
+	emit_byte(0xd9);
+	emit_byte(0xc9);     /* fxch swap */
+	emit_byte(0xd8);
+	emit_byte(0xe1);     /* fsub -x*log2(e) - int(-x*log2(e))  */
+	emit_byte(0xd9);
+	emit_byte(0xf0);     /* f2xm1 (2^frac(x))-1 */
+	emit_byte(0xd8);
+	emit_byte(0x05);
+	emit_long((uae_u32)&one);  /* fadd (2^frac(x))-1 + 1 */
+	emit_byte(0xd9);
+	emit_byte(0xfd);     /* fscale (2^frac(x))*2^int(x*log2(e)) */
+	emit_byte(0xd9);
+	emit_byte(0xca);     /* fxch swap e^-x with x*log2(e) in tr */
+	emit_byte(0xdd);
+	emit_byte(0xd1);     /* fst copy x*log2(e) */
+	emit_byte(0xd9);
+	emit_byte(0xfc);     /* frndint int(x*log2(e)) */
+	emit_byte(0xd9);
+	emit_byte(0xc9);     /* fxch swap */
+	emit_byte(0xd8);
+	emit_byte(0xe1);     /* fsub x*log2(e) - int(x*log2(e))  */
+	emit_byte(0xd9);
+	emit_byte(0xf0);     /* f2xm1 (2^frac(x))-1 */
+	emit_byte(0xd8);
+	emit_byte(0x05);
+	emit_long((uae_u32)&one);  /* fadd (2^frac(x))-1 + 1 */
+	emit_byte(0xd9);
+	emit_byte(0xfd);     /* fscale (2^frac(x))*2^int(x*log2(e)) */
+	emit_byte(0xdd);
+	emit_byte(0xd9);     /* fstp copy e^x & pop */
+	if (tr>=0) {
+		emit_byte(0xdb);
+		emit_byte(0x2c);
+		emit_byte(0x24); /* fld load temp-reg from [esp] */
+		emit_byte(0xd9);
+		emit_byte(0xca); /* fxch swap temp-reg with e^-x in tr */
+		emit_byte(0x83);
+		emit_byte(0xc4);
+		emit_byte(0x0c); /* delayed add +12 to esp */
+	}
+	emit_byte(0xde);
+	emit_byte(0xc1);     /* faddp (e^x)+(e^-x) */
+	emit_byte(0xd9);
+	emit_byte(0xe8);     /* fld 1.0 */
+	emit_byte(0xd9);
+	emit_byte(0xe0);     /* fchs -1.0 */
+	emit_byte(0xd9);
+	emit_byte(0xc9);     /* fxch swap */
+	emit_byte(0xd9);
+	emit_byte(0xfd);     /* fscale ((e^x)+(e^-x))/2 */
+	emit_byte(0xdd);
+	emit_byte(0xd9);     /* fstp copy & pop */
+	if (s!=d)
+		tos_make(d);     /* store y=cosh(x) */
+}
+LENDFUNC(NONE,NONE,2,raw_fcosh_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_ftanh_rr,(FW d, FR s))
+{
+	int ds,tr;
+
+	tr=live.onstack[live.tos+3];
+	if (s==d)
+		make_tos(s);
+	else {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld x */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xea);     /* fldl2e log2(e) */
+	emit_byte(0xd8);
+	emit_byte(0xc9);     /* fmul x*log2(e) */
+	emit_byte(0xdd);
+	emit_byte(0xd1);     /* fst copy x*log2(e) */
+	if (tr>=0) {
+		emit_byte(0xd9);
+		emit_byte(0xca); /* fxch swap with temp-reg */
+		emit_byte(0x83);
+		emit_byte(0xc4);
+		emit_byte(0xf4); /* add -12 to esp */
+		emit_byte(0xdb);
+		emit_byte(0x3c);
+		emit_byte(0x24); /* fstp store temp-reg to [esp] & pop */
+	}
+	emit_byte(0xd9);
+	emit_byte(0xe0);     /* fchs -x*log2(e) */
+	emit_byte(0xd9);
+	emit_byte(0xc0);     /* fld -x*log2(e) again */
+	emit_byte(0xd9);
+	emit_byte(0xfc);     /* frndint int(-x*log2(e)) */
+	emit_byte(0xd9);
+	emit_byte(0xc9);     /* fxch swap */
+	emit_byte(0xd8);
+	emit_byte(0xe1);     /* fsub -x*log2(e) - int(-x*log2(e))  */
+	emit_byte(0xd9);
+	emit_byte(0xf0);     /* f2xm1 (2^frac(x))-1 */
+	emit_byte(0xd8);
+	emit_byte(0x05);
+	emit_long((uae_u32)&one);  /* fadd (2^frac(x))-1 + 1 */
+	emit_byte(0xd9);
+	emit_byte(0xfd);     /* fscale (2^frac(x))*2^int(x*log2(e)) */
+	emit_byte(0xd9);
+	emit_byte(0xca);     /* fxch swap e^-x with x*log2(e) */
+	emit_byte(0xdd);
+	emit_byte(0xd1);     /* fst copy x*log2(e) */
+	emit_byte(0xd9);
+	emit_byte(0xfc);     /* frndint int(x*log2(e)) */
+	emit_byte(0xd9);
+	emit_byte(0xc9);     /* fxch swap */
+	emit_byte(0xd8);
+	emit_byte(0xe1);     /* fsub x*log2(e) - int(x*log2(e))  */
+	emit_byte(0xd9);
+	emit_byte(0xf0);     /* f2xm1 (2^frac(x))-1 */
+	emit_byte(0xd8);
+	emit_byte(0x05);
+	emit_long((uae_u32)&one);  /* fadd (2^frac(x))-1 + 1 */
+	emit_byte(0xd9);
+	emit_byte(0xfd);     /* fscale (2^frac(x))*2^int(x*log2(e)) */
+	emit_byte(0xdd);
+	emit_byte(0xd1);     /* fst copy e^x */
+	emit_byte(0xd8);
+	emit_byte(0xc2);     /* fadd (e^x)+(e^-x) */
+	emit_byte(0xd9);
+	emit_byte(0xca);     /* fxch swap with e^-x */
+	emit_byte(0xde);
+	emit_byte(0xe9);     /* fsubp (e^x)-(e^-x) */
+	if (tr>=0) {
+		emit_byte(0xdb);
+		emit_byte(0x2c);
+		emit_byte(0x24); /* fld load temp-reg from [esp] */
+		emit_byte(0xd9);
+		emit_byte(0xca); /* fxch swap temp-reg with e^-x in tr */
+		emit_byte(0xde);
+		emit_byte(0xf9); /* fdivp ((e^x)-(e^-x))/((e^x)+(e^-x)) */
+		emit_byte(0x83);
+		emit_byte(0xc4);
+		emit_byte(0x0c); /* delayed add +12 to esp */
+	}
+	else {
+		emit_byte(0xde);
+		emit_byte(0xf1); /* fdivrp ((e^x)-(e^-x))/((e^x)+(e^-x)) */
+	}
+	if (s!=d)
+		tos_make(d);     /* store y=tanh(x) */
+}
+LENDFUNC(NONE,NONE,2,raw_ftanh_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fneg_rr,(FW d, FR s))
+{
+	int ds;
+
+	if (d!=s) {
+		ds=stackpos(s);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* duplicate source */
+		emit_byte(0xd9);
+		emit_byte(0xe0); /* take fchs */
+		tos_make(d); /* store to destination */
+	}
+	else {
+		make_tos(d);
+		emit_byte(0xd9);
+		emit_byte(0xe0); /* take fchs */
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fneg_rr,(FW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fadd_rr,(FRW d, FR s))
+{
+	int ds;
+
+	if (live.spos[s]==live.tos) {
+		/* Source is on top of stack */
+		ds=stackpos(d);
+		emit_byte(0xdc);
+		emit_byte(0xc0+ds); /* add source to dest*/
+	}
+	else {
+		make_tos(d);
+		ds=stackpos(s);
+
+		emit_byte(0xd8);
+		emit_byte(0xc0+ds); /* add source to dest*/
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fadd_rr,(FRW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fsub_rr,(FRW d, FR s))
+{
+	int ds;
+
+	if (live.spos[s]==live.tos) {
+		/* Source is on top of stack */
+		ds=stackpos(d);
+		emit_byte(0xdc);
+		emit_byte(0xe8+ds); /* sub source from dest*/
+	}
+	else {
+		make_tos(d);
+		ds=stackpos(s);
+
+		emit_byte(0xd8);
+		emit_byte(0xe0+ds); /* sub src from dest */
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fsub_rr,(FRW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fcmp_rr,(FR d, FR s))
+{
+	int ds;
+
+	make_tos(d);
+	ds=stackpos(s);
+
+	emit_byte(0xdd);
+	emit_byte(0xe0+ds); /* cmp dest with source*/
+}
+LENDFUNC(NONE,NONE,2,raw_fcmp_rr,(FR d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fmul_rr,(FRW d, FR s))
+{
+	int ds;
+
+	if (live.spos[s]==live.tos) {
+		/* Source is on top of stack */
+		ds=stackpos(d);
+		emit_byte(0xdc);
+		emit_byte(0xc8+ds); /* mul dest by source*/
+	}
+	else {
+		make_tos(d);
+		ds=stackpos(s);
+
+		emit_byte(0xd8);
+		emit_byte(0xc8+ds); /* mul dest by source*/
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fmul_rr,(FRW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_fdiv_rr,(FRW d, FR s))
+{
+	int ds;
+
+	if (live.spos[s]==live.tos) {
+		/* Source is on top of stack */
+		ds=stackpos(d);
+		emit_byte(0xdc);
+		emit_byte(0xf8+ds); /* div dest by source */
+	}
+	else {
+		make_tos(d);
+		ds=stackpos(s);
+
+		emit_byte(0xd8);
+		emit_byte(0xf0+ds); /* div dest by source*/
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_fdiv_rr,(FRW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_frem_rr,(FRW d, FR s))
+{
+	int ds;
+
+	if (live.spos[d]==live.tos && live.spos[s]==live.tos-1) {
+		//write_log (_T("frem found x in TOS-1 and y in TOS\n"));
+		emit_byte(0xd9);
+		emit_byte(0xf8);    /* fprem rem(y/x) */
+	}
+	else {
+		make_tos(s);        /* tos=x */
+		ds=stackpos(d);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld y */
+		emit_byte(0xd9);
+		emit_byte(0xf8);    /* fprem rem(y/x) */
+		tos_make(d);        /* store y=rem(y/x) */
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_frem_rr,(FRW d, FR s))
+
+	LOWFUNC(NONE,NONE,2,raw_frem1_rr,(FRW d, FR s))
+{
+	int ds;
+
+	if (live.spos[d]==live.tos && live.spos[s]==live.tos-1) {
+		//write_log (_T("frem1 found x in TOS-1 and y in TOS\n"));
+		emit_byte(0xd9);
+		emit_byte(0xf5);    /* fprem1 rem1(y/x) */
+	}
+	else {
+		make_tos(s);        /* tos=x */
+		ds=stackpos(d);
+		emit_byte(0xd9);
+		emit_byte(0xc0+ds); /* fld y */
+		emit_byte(0xd9);
+		emit_byte(0xf5);    /* fprem1 rem1(y/x) */
+		tos_make(d);        /* store y=rem(y/x) */
+	}
+}
+LENDFUNC(NONE,NONE,2,raw_frem1_rr,(FRW d, FR s))
+
+	LOWFUNC(NONE,NONE,1,raw_ftst_r,(FR r))
+{
+	make_tos(r);
+	emit_byte(0xd9);  /* ftst */
+	emit_byte(0xe4);
+}
+LENDFUNC(NONE,NONE,1,raw_ftst_r,(FR r))
+
+	STATIC_INLINE void raw_fflags_into_flags(int r)
+{
+	int p;
+
+	usereg(r);
+	p=stackpos(r);
+
+	emit_byte(0xd9);
+	emit_byte(0xee); /* Push 0 */
+	emit_byte(0xd9);
+	emit_byte(0xc9+p); /* swap top two around */
+	if (have_cmov) {
+		// gb-- fucomi is for P6 cores only, not K6-2 then...
+		emit_byte(0xdb);
+		emit_byte(0xe9+p); /* fucomi them */
+	}
+	else {
+		emit_byte(0xdd);
+		emit_byte(0xe1+p); /* fucom them */
+		emit_byte(0x9b);
+		emit_byte(0xdf);
+		emit_byte(0xe0); /* fstsw ax */
+		raw_sahf(0); /* sahf */
+	}
+	emit_byte(0xdd);
+	emit_byte(0xd9+p);  /* store value back, and get rid of 0 */
+}
diff --git a/src/cpu/jit/compemu_support.c b/src/cpu/jit/compemu_support.c
new file mode 100644
index 0000000..89cd8f1
--- /dev/null
+++ b/src/cpu/jit/compemu_support.c
@@ -0,0 +1,6254 @@
+
+#define writemem_special writemem
+#define readmem_special  readmem
+
+#define USE_MATCHSTATE 0
+#include "sysconfig.h"
+#include "sysdeps.h"
+
+#if defined(JIT)
+
+#include "options.h"
+#include "events.h"
+#include "include/memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "comptbl.h"
+#include "compemu.h"
+
+
+#define NATMEM_OFFSETX (uae_u32)NATMEM_OFFSET
+
+// %%% BRIAN KING WAS HERE %%%
+extern bool canbang;
+#include 
+extern void jit_abort(const TCHAR*,...);
+compop_func *compfunctbl[65536];
+compop_func *nfcompfunctbl[65536];
+#ifdef NOFLAGS_SUPPORT
+compop_func *nfcpufunctbl[65536];
+#endif
+uae_u8* comp_pc_p;
+
+uae_u8* start_pc_p;
+uae_u32 start_pc;
+uae_u32 current_block_pc_p;
+uae_u32 current_block_start_target;
+uae_u32 needed_flags;
+static uae_u32 next_pc_p;
+static uae_u32 taken_pc_p;
+static int     branch_cc;
+int segvcount=0;
+int soft_flush_count=0;
+int hard_flush_count=0;
+int compile_count=0;
+int checksum_count=0;
+static uae_u8* current_compile_p=NULL;
+static uae_u8* max_compile_start;
+uae_u8* compiled_code=NULL;
+static uae_s32 reg_alloc_run;
+
+static int		lazy_flush		= 1;	// Flag: lazy translation cache invalidation
+static int		avoid_fpu		= 1;	// Flag: compile FPU instructions ?
+static int		have_cmov		= 0;	// target has CMOV instructions ?
+static int		have_rat_stall		= 1;	// target has partial register stalls ?
+const int		tune_alignment		= 1;	// Tune code alignments for running CPU ?
+const int		tune_nop_fillers	= 1;	// Tune no-op fillers for architecture
+
+static int		setzflg_uses_bsf	= 0;	// setzflg virtual instruction can use native BSF instruction correctly?
+static int		align_loops		= 32;	// Align the start of loops
+static int		align_jumps		= 32;	// Align the start of jumps
+
+void* pushall_call_handler=NULL;
+static void* popall_do_nothing=NULL;
+static void* popall_exec_nostats=NULL;
+static void* popall_execute_normal=NULL;
+static void* popall_cache_miss=NULL;
+static void* popall_recompile_block=NULL;
+static void* popall_check_checksum=NULL;
+
+extern uae_u32 oink;
+extern unsigned long foink3;
+extern unsigned long foink;
+
+/* The 68k only ever executes from even addresses. So right now, we
+waste half the entries in this array
+UPDATE: We now use those entries to store the start of the linked
+lists that we maintain for each hash result. */
+static cacheline cache_tags[TAGSIZE];
+static int letit=0;
+static blockinfo* hold_bi[MAX_HOLD_BI];
+static blockinfo* active;
+static blockinfo* dormant;
+
+op_properties prop[65536];
+
+#ifdef NOFLAGS_SUPPORT
+/* 68040 */
+extern const struct comptbl op_smalltbl_0_nf[];
+#endif
+extern const struct comptbl op_smalltbl_0_comp_nf[];
+extern const struct comptbl op_smalltbl_0_comp_ff[];
+#ifdef NOFLAGS_SUPPORT
+/* 68020 + 68881 */
+extern const struct cputbl op_smalltbl_1_nf[];
+/* 68020 */
+extern const struct cputbl op_smalltbl_2_nf[];
+/* 68010 */
+extern const struct cputbl op_smalltbl_3_nf[];
+/* 68000 */
+extern const struct cputbl op_smalltbl_4_nf[];
+/* 68000 slow but compatible.  */
+extern const struct cputbl op_smalltbl_5_nf[];
+#endif
+
+static bigstate live;
+static smallstate empty_ss;
+static smallstate default_ss;
+static int optlev;
+
+static int writereg(int r, int size);
+static void unlock(int r);
+static void setlock(int r);
+static int readreg_specific(int r, int size, int spec);
+static int writereg_specific(int r, int size, int spec);
+static void prepare_for_call_1(void);
+static void prepare_for_call_2(void);
+static void align_target(uae_u32 a);
+
+static uae_s32 nextused[VREGS];
+
+static uae_u8 *popallspace;
+
+uae_u32 m68k_pc_offset;
+
+/* Some arithmetic operations can be optimized away if the operands
+are known to be constant. But that's only a good idea when the
+side effects they would have on the flags are not important. This
+variable indicates whether we need the side effects or not
+*/
+uae_u32 needflags=0;
+
+/* Flag handling is complicated.
+
+x86 instructions create flags, which quite often are exactly what we
+want. So at times, the "68k" flags are actually in the x86 flags.
+
+Then again, sometimes we do x86 instructions that clobber the x86
+flags, but don't represent a corresponding m68k instruction. In that
+case, we have to save them.
+
+We used to save them to the stack, but now store them back directly
+into the regflags.cznv of the traditional emulation. Thus some odd
+names.
+
+So flags can be in either of two places (used to be three; boy were
+things complicated back then!); And either place can contain either
+valid flags or invalid trash (and on the stack, there was also the
+option of "nothing at all", now gone). A couple of variables keep
+track of the respective states.
+
+To make things worse, we might or might not be interested in the flags.
+by default, we are, but a call to dont_care_flags can change that
+until the next call to live_flags. If we are not, pretty much whatever
+is in the register and/or the native flags is seen as valid.
+*/
+
+
+STATIC_INLINE blockinfo* get_blockinfo(uae_u32 cl)
+{
+	return cache_tags[cl+1].bi;
+}
+
+STATIC_INLINE blockinfo* get_blockinfo_addr(void* addr)
+{
+	blockinfo*  bi=get_blockinfo(cacheline(addr));
+
+	while (bi) {
+		if (bi->pc_p==addr)
+			return bi;
+		bi=bi->next_same_cl;
+	}
+	return NULL;
+}
+
+
+/*******************************************************************
+* All sorts of list related functions for all of the lists        *
+*******************************************************************/
+
+STATIC_INLINE void remove_from_cl_list(blockinfo* bi)
+{
+	uae_u32 cl=cacheline(bi->pc_p);
+
+	if (bi->prev_same_cl_p)
+		*(bi->prev_same_cl_p)=bi->next_same_cl;
+	if (bi->next_same_cl)
+		bi->next_same_cl->prev_same_cl_p=bi->prev_same_cl_p;
+	if (cache_tags[cl+1].bi)
+		cache_tags[cl].handler=cache_tags[cl+1].bi->handler_to_use;
+	else
+		cache_tags[cl].handler=(cpuop_func*)popall_execute_normal;
+}
+
+STATIC_INLINE void remove_from_list(blockinfo* bi)
+{
+	if (bi->prev_p)
+		*(bi->prev_p)=bi->next;
+	if (bi->next)
+		bi->next->prev_p=bi->prev_p;
+}
+
+STATIC_INLINE void remove_from_lists(blockinfo* bi)
+{
+	remove_from_list(bi);
+	remove_from_cl_list(bi);
+}
+
+STATIC_INLINE void add_to_cl_list(blockinfo* bi)
+{
+	uae_u32 cl=cacheline(bi->pc_p);
+
+	if (cache_tags[cl+1].bi)
+		cache_tags[cl+1].bi->prev_same_cl_p=&(bi->next_same_cl);
+	bi->next_same_cl=cache_tags[cl+1].bi;
+
+	cache_tags[cl+1].bi=bi;
+	bi->prev_same_cl_p=&(cache_tags[cl+1].bi);
+
+	cache_tags[cl].handler=bi->handler_to_use;
+}
+
+STATIC_INLINE void raise_in_cl_list(blockinfo* bi)
+{
+	remove_from_cl_list(bi);
+	add_to_cl_list(bi);
+}
+
+STATIC_INLINE void add_to_active(blockinfo* bi)
+{
+	if (active)
+		active->prev_p=&(bi->next);
+	bi->next=active;
+
+	active=bi;
+	bi->prev_p=&active;
+}
+
+STATIC_INLINE void add_to_dormant(blockinfo* bi)
+{
+	if (dormant)
+		dormant->prev_p=&(bi->next);
+	bi->next=dormant;
+
+	dormant=bi;
+	bi->prev_p=&dormant;
+}
+
+STATIC_INLINE void remove_dep(dependency* d)
+{
+	if (d->prev_p)
+		*(d->prev_p)=d->next;
+	if (d->next)
+		d->next->prev_p=d->prev_p;
+	d->prev_p=NULL;
+	d->next=NULL;
+}
+
+/* This block's code is about to be thrown away, so it no longer
+depends on anything else */
+STATIC_INLINE void remove_deps(blockinfo* bi)
+{
+	remove_dep(&(bi->dep[0]));
+	remove_dep(&(bi->dep[1]));
+}
+
+STATIC_INLINE void adjust_jmpdep(dependency* d, void* a)
+{
+	*(d->jmp_off)=(uae_u32)a-((uae_u32)d->jmp_off+4);
+}
+
+/********************************************************************
+* Soft flush handling support functions                            *
+********************************************************************/
+
+STATIC_INLINE void set_dhtu(blockinfo* bi, void* dh)
+{
+	//write_log (_T("JIT: bi is %p\n"),bi);
+	if (dh!=bi->direct_handler_to_use) {
+		dependency* x=bi->deplist;
+		//write_log (_T("JIT: bi->deplist=%p\n"),bi->deplist);
+		while (x) {
+			//write_log (_T("JIT: x is %p\n"),x);
+			//write_log (_T("JIT: x->next is %p\n"),x->next);
+			//write_log (_T("JIT: x->prev_p is %p\n"),x->prev_p);
+
+			if (x->jmp_off) {
+				adjust_jmpdep(x,dh);
+			}
+			x=x->next;
+		}
+		bi->direct_handler_to_use=(cpuop_func*)dh;
+	}
+}
+
+STATIC_INLINE void invalidate_block(blockinfo* bi)
+{
+	int i;
+
+	bi->optlevel=0;
+	bi->count=currprefs.optcount[0]-1;
+	bi->handler=NULL;
+	bi->handler_to_use=(cpuop_func*)popall_execute_normal;
+	bi->direct_handler=NULL;
+	set_dhtu(bi,bi->direct_pen);
+	bi->needed_flags=0xff;
+
+	for (i=0;i<2;i++) {
+		bi->dep[i].jmp_off=NULL;
+		bi->dep[i].target=NULL;
+	}
+	remove_deps(bi);
+}
+
+STATIC_INLINE void create_jmpdep(blockinfo* bi, int i, uae_u32* jmpaddr, uae_u32 target)
+{
+	blockinfo*  tbi=get_blockinfo_addr((void*)target);
+
+	Dif(!tbi) {
+		jit_abort (_T("JIT: Could not create jmpdep!\n"));
+	}
+	bi->dep[i].jmp_off=jmpaddr;
+	bi->dep[i].target=tbi;
+	bi->dep[i].next=tbi->deplist;
+	if (bi->dep[i].next)
+		bi->dep[i].next->prev_p=&(bi->dep[i].next);
+	bi->dep[i].prev_p=&(tbi->deplist);
+	tbi->deplist=&(bi->dep[i]);
+}
+
+STATIC_INLINE void big_to_small_state(bigstate* b, smallstate* s)
+{
+	int i;
+	int count=0;
+
+	for (i=0;inat[i].validsize=0;
+		s->nat[i].dirtysize=0;
+		if (b->nat[i].nholds) {
+			int index=b->nat[i].nholds-1;
+			int r=b->nat[i].holds[index];
+			s->nat[i].holds=r;
+			s->nat[i].validsize=b->state[r].validsize;
+			s->nat[i].dirtysize=b->state[r].dirtysize;
+			count++;
+		}
+	}
+	write_log (_T("JIT: count=%d\n"),count);
+	for (i=0;inat[i].dirtysize=0;
+	}
+}
+
+STATIC_INLINE void attached_state(blockinfo* bi)
+{
+	bi->havestate=1;
+	if (bi->direct_handler_to_use==bi->direct_handler)
+		set_dhtu(bi,bi->direct_pen);
+	bi->direct_handler=bi->direct_pen;
+	bi->status=BI_TARGETTED;
+}
+
+STATIC_INLINE blockinfo* get_blockinfo_addr_new(void* addr, int setstate)
+{
+	blockinfo*  bi=get_blockinfo_addr(addr);
+	int i;
+
+#if USE_OPTIMIZER
+	if (reg_alloc_run)
+		return NULL;
+#endif
+	if (!bi) {
+		for (i=0;ipc_p=(uae_u8*)addr;
+				invalidate_block(bi);
+				add_to_active(bi);
+				add_to_cl_list(bi);
+
+			}
+		}
+	}
+	if (!bi) {
+		jit_abort (_T("JIT: Looking for blockinfo, can't find free one\n"));
+	}
+
+#if USE_MATCHSTATE
+	if (setstate &&
+		!bi->havestate) {
+			big_to_small_state(&live,&(bi->env));
+			attached_state(bi);
+	}
+#endif
+	return bi;
+}
+
+static void prepare_block(blockinfo* bi);
+
+STATIC_INLINE void alloc_blockinfos(void)
+{
+	int i;
+	blockinfo* bi;
+
+	for (i=0;i>24)&0xff) | ((oldv>>8)&0xff00) |
+		((oldv<<8)&0xff0000) | ((oldv<<24)&0xff000000);
+}
+
+
+void set_target(uae_u8* t)
+{
+	lopt_emit_all();
+	target=t;
+}
+
+STATIC_INLINE uae_u8* get_target_noopt(void)
+{
+	return target;
+}
+
+STATIC_INLINE uae_u8* get_target(void)
+{
+	lopt_emit_all();
+	return get_target_noopt();
+}
+
+
+/********************************************************************
+* Getting the information about the target CPU                     *
+********************************************************************/
+
+#include "compemu_raw_x86.cpp"
+
+
+/********************************************************************
+* Flags status handling. EMIT TIME!                                *
+********************************************************************/
+
+static void bt_l_ri_noclobber(R4 r, IMM i);
+
+static void make_flags_live_internal(void)
+{
+	if (live.flags_in_flags==VALID)
+		return;
+	Dif (live.flags_on_stack==TRASH) {
+		jit_abort (_T("JIT: Want flags, got something on stack, but it is TRASH\n"));
+	}
+	if (live.flags_on_stack==VALID) {
+		int tmp;
+		tmp=readreg_specific(FLAGTMP,4,FLAG_NREG2);
+		raw_reg_to_flags(tmp);
+		unlock(tmp);
+
+		live.flags_in_flags=VALID;
+		return;
+	}
+	jit_abort (_T("JIT: Huh? live.flags_in_flags=%d, live.flags_on_stack=%d, but need to make live\n"),
+		live.flags_in_flags,live.flags_on_stack);
+}
+
+static void flags_to_stack(void)
+{
+	if (live.flags_on_stack==VALID)
+		return;
+	if (!live.flags_are_important) {
+		live.flags_on_stack=VALID;
+		return;
+	}
+	Dif (live.flags_in_flags!=VALID)
+		jit_abort (_T("flags_to_stack != VALID"));
+	else  {
+		int tmp;
+		tmp=writereg_specific(FLAGTMP,4,FLAG_NREG1);
+		raw_flags_to_reg(tmp);
+		unlock(tmp);
+	}
+	live.flags_on_stack=VALID;
+}
+
+STATIC_INLINE void clobber_flags(void)
+{
+	if (live.flags_in_flags==VALID && live.flags_on_stack!=VALID)
+		flags_to_stack();
+	live.flags_in_flags=TRASH;
+}
+
+/* Prepare for leaving the compiled stuff */
+STATIC_INLINE void flush_flags(void)
+{
+	flags_to_stack();
+	return;
+}
+
+int touchcnt;
+
+/********************************************************************
+* register allocation per block logging                            *
+********************************************************************/
+
+static uae_s8 vstate[VREGS];
+static uae_s8 nstate[N_REGS];
+
+#define L_UNKNOWN -127
+#define L_UNAVAIL -1
+#define L_NEEDED -2
+#define L_UNNEEDED -3
+
+STATIC_INLINE void log_startblock(void)
+{
+	int i;
+	for (i=0;i0) {
+		free_nreg(bestreg);
+	}
+	if (isinreg(r)) {
+		int rr=live.state[r].realreg;
+		/* This will happen if we read a partially dirty register at a
+		bigger size */
+		Dif (willclobber || live.state[r].validsize>=size)
+			jit_abort (_T("willclobber || live.state[r].validsize>=size"));
+		Dif (live.nat[rr].nholds!=1)
+			jit_abort (_T("live.nat[rr].nholds!=1"));
+		if (size==4 && live.state[r].validsize==2) {
+			log_isused(bestreg);
+			raw_mov_l_rm(bestreg,(uae_u32)live.state[r].mem);
+			raw_bswap_32(bestreg);
+			raw_zero_extend_16_rr(rr,rr);
+			raw_zero_extend_16_rr(bestreg,bestreg);
+			raw_bswap_32(bestreg);
+			raw_lea_l_rr_indexed(rr,rr,bestreg);
+			live.state[r].validsize=4;
+			live.nat[rr].touched=touchcnt++;
+			return rr;
+		}
+		if (live.state[r].validsize==1) {
+			/* Nothing yet */
+		}
+		evict(r);
+	}
+
+	if (!willclobber) {
+		if (live.state[r].status!=UNDEF) {
+			if (isconst(r)) {
+				raw_mov_l_ri(bestreg,live.state[r].val);
+				live.state[r].val=0;
+				live.state[r].dirtysize=4;
+				set_status(r,DIRTY);
+				log_isused(bestreg);
+			}
+			else {
+				if (r==FLAGTMP)
+					raw_load_flagreg(bestreg,r);
+				else if (r==FLAGX)
+					raw_load_flagx(bestreg,r);
+				else {
+					raw_mov_l_rm(bestreg,(uae_u32)live.state[r].mem);
+				}
+				live.state[r].dirtysize=0;
+				set_status(r,CLEAN);
+				log_isreg(bestreg,r);
+			}
+		}
+		else {
+			live.state[r].val=0;
+			live.state[r].dirtysize=0;
+			set_status(r,CLEAN);
+			log_isused(bestreg);
+		}
+		live.state[r].validsize=4;
+	}
+	else { /* this is the easiest way, but not optimal. FIXME! */
+		/* Now it's trickier, but hopefully still OK */
+		if (!isconst(r) || size==4) {
+			live.state[r].validsize=size;
+			live.state[r].dirtysize=size;
+			live.state[r].val=0;
+			set_status(r,DIRTY);
+			if (size==4)
+				log_isused(bestreg);
+			else
+				log_isreg(bestreg,r);
+		}
+		else {
+			if (live.state[r].status!=UNDEF)
+				raw_mov_l_ri(bestreg,live.state[r].val);
+			live.state[r].val=0;
+			live.state[r].validsize=4;
+			live.state[r].dirtysize=4;
+			set_status(r,DIRTY);
+			log_isused(bestreg);
+		}
+	}
+	live.state[r].realreg=bestreg;
+	live.state[r].realind=live.nat[bestreg].nholds;
+	live.nat[bestreg].touched=touchcnt++;
+	live.nat[bestreg].holds[live.nat[bestreg].nholds]=r;
+	live.nat[bestreg].nholds++;
+
+	return bestreg;
+}
+
+static  int alloc_reg(int r, int size, int willclobber)
+{
+	return alloc_reg_hinted(r,size,willclobber,-1);
+}
+
+static  void unlock(int r)
+{
+	Dif (!live.nat[r].locked)
+		jit_abort (_T("unlock %d not locked"), r);
+	live.nat[r].locked--;
+}
+
+static  void setlock(int r)
+{
+	live.nat[r].locked++;
+}
+
+
+static void mov_nregs(int d, int s)
+{
+	int ns=live.nat[s].nholds;
+	int nd=live.nat[d].nholds;
+	int i;
+
+	if (s==d)
+		return;
+
+	if (nd>0)
+		free_nreg(d);
+
+	raw_mov_l_rr(d,s);
+	log_isused(d);
+
+	for (i=0;i=size) {
+		n=live.state[r].realreg;
+		switch(size) {
+		case 1:
+			if (live.nat[n].canbyte || spec>=0) {
+				answer=n;
+			}
+			break;
+		case 2:
+			if (live.nat[n].canword || spec>=0) {
+				answer=n;
+			}
+			break;
+		case 4:
+			answer=n;
+			break;
+		default: abort();
+		}
+		if (answer<0)
+			evict(r);
+	}
+	/* either the value was in memory to start with, or it was evicted and
+	is in memory now */
+	if (answer<0) {
+		answer=alloc_reg_hinted(r,spec>=0?4:size,0,spec);
+	}
+
+	if (spec>=0 && spec!=answer) {
+		/* Too bad */
+		mov_nregs(spec,answer);
+		answer=spec;
+	}
+	live.nat[answer].locked++;
+	live.nat[answer].touched=touchcnt++;
+	return answer;
+}
+
+
+
+static int readreg(int r, int size)
+{
+	return readreg_general(r,size,-1,0);
+}
+
+static int readreg_specific(int r, int size, int spec)
+{
+	return readreg_general(r,size,spec,0);
+}
+
+static int readreg_offset(int r, int size)
+{
+	return readreg_general(r,size,-1,1);
+}
+
+
+STATIC_INLINE int writereg_general(int r, int size, int spec)
+{
+	int n;
+	int answer=-1;
+
+	if (size<4) {
+		remove_offset(r,spec);
+	}
+
+	make_exclusive(r,size,spec);
+	if (isinreg(r)) {
+		int nvsize=size>live.state[r].validsize?size:live.state[r].validsize;
+		int ndsize=size>live.state[r].dirtysize?size:live.state[r].dirtysize;
+		n=live.state[r].realreg;
+
+		Dif (live.nat[n].nholds!=1)
+			jit_abort (_T("live.nat[%d].nholds!=1"), n);
+		switch(size) {
+		case 1:
+			if (live.nat[n].canbyte || spec>=0) {
+				live.state[r].dirtysize=ndsize;
+				live.state[r].validsize=nvsize;
+				answer=n;
+			}
+			break;
+		case 2:
+			if (live.nat[n].canword || spec>=0) {
+				live.state[r].dirtysize=ndsize;
+				live.state[r].validsize=nvsize;
+				answer=n;
+			}
+			break;
+		case 4:
+			live.state[r].dirtysize=ndsize;
+			live.state[r].validsize=nvsize;
+			answer=n;
+			break;
+		default: abort();
+		}
+		if (answer<0)
+			evict(r);
+	}
+	/* either the value was in memory to start with, or it was evicted and
+	is in memory now */
+	if (answer<0) {
+		answer=alloc_reg_hinted(r,size,1,spec);
+	}
+	if (spec>=0 && spec!=answer) {
+		mov_nregs(spec,answer);
+		answer=spec;
+	}
+	if (live.state[r].status==UNDEF)
+		live.state[r].validsize=4;
+	live.state[r].dirtysize=size>live.state[r].dirtysize?size:live.state[r].dirtysize;
+	live.state[r].validsize=size>live.state[r].validsize?size:live.state[r].validsize;
+
+	live.nat[answer].locked++;
+	live.nat[answer].touched=touchcnt++;
+	if (size==4) {
+		live.state[r].val=0;
+	}
+	else {
+		Dif (live.state[r].val) {
+			jit_abort (_T("JIT: Problem with val\n"));
+		}
+	}
+	set_status(r,DIRTY);
+	return answer;
+}
+
+static int writereg(int r, int size)
+{
+	return writereg_general(r,size,-1);
+}
+
+static int writereg_specific(int r, int size, int spec)
+{
+	return writereg_general(r,size,spec);
+}
+
+STATIC_INLINE int rmw_general(int r, int wsize, int rsize, int spec)
+{
+	int n;
+	int answer=-1;
+
+	if (live.state[r].status==UNDEF) {
+		write_log (_T("JIT: WARNING: Unexpected read of undefined register %d\n"),r);
+	}
+	remove_offset(r,spec);
+	make_exclusive(r,0,spec);
+
+	Dif (wsize=rsize) {
+		n=live.state[r].realreg;
+		Dif (live.nat[n].nholds!=1)
+			jit_abort (_T("live.nat[n].nholds!=1"), n);
+
+		switch(rsize) {
+		case 1:
+			if (live.nat[n].canbyte || spec>=0) {
+				answer=n;
+			}
+			break;
+		case 2:
+			if (live.nat[n].canword || spec>=0) {
+				answer=n;
+			}
+			break;
+		case 4:
+			answer=n;
+			break;
+		default: abort();
+		}
+		if (answer<0)
+			evict(r);
+	}
+	/* either the value was in memory to start with, or it was evicted and
+	is in memory now */
+	if (answer<0) {
+		answer=alloc_reg_hinted(r,spec>=0?4:rsize,0,spec);
+	}
+
+	if (spec>=0 && spec!=answer) {
+		/* Too bad */
+		mov_nregs(spec,answer);
+		answer=spec;
+	}
+	if (wsize>live.state[r].dirtysize)
+		live.state[r].dirtysize=wsize;
+	if (wsize>live.state[r].validsize)
+		live.state[r].validsize=wsize;
+	set_status(r,DIRTY);
+
+	live.nat[answer].locked++;
+	live.nat[answer].touched=touchcnt++;
+
+	Dif (live.state[r].val) {
+		jit_abort (_T("JIT: Problem with val(rmw)\n"));
+	}
+	return answer;
+}
+
+static int rmw(int r, int wsize, int rsize)
+{
+	return rmw_general(r,wsize,rsize,-1);
+}
+
+static int rmw_specific(int r, int wsize, int rsize, int spec)
+{
+	return rmw_general(r,wsize,rsize,spec);
+}
+
+
+/* needed for restoring the carry flag on non-P6 cores */
+static void bt_l_ri_noclobber(R4 r, IMM i)
+{
+	int size=4;
+	if (i<16)
+		size=2;
+	r=readreg(r,size);
+	raw_bt_l_ri(r,i);
+	unlock(r);
+}
+
+/********************************************************************
+* FPU register status handling. EMIT TIME!                         *
+********************************************************************/
+
+static  void f_tomem(int r)
+{
+	if (live.fate[r].status==DIRTY) {
+#if USE_LONG_DOUBLE
+		raw_fmov_ext_mr((uae_u32)live.fate[r].mem,live.fate[r].realreg);
+#else
+		raw_fmov_mr((uae_u32)live.fate[r].mem,live.fate[r].realreg);
+#endif
+		live.fate[r].status=CLEAN;
+	}
+}
+
+static  void f_tomem_drop(int r)
+{
+	if (live.fate[r].status==DIRTY) {
+#if USE_LONG_DOUBLE
+		raw_fmov_ext_mr_drop((uae_u32)live.fate[r].mem,live.fate[r].realreg);
+#else
+		raw_fmov_mr_drop((uae_u32)live.fate[r].mem,live.fate[r].realreg);
+#endif
+		live.fate[r].status=INMEM;
+	}
+}
+
+
+STATIC_INLINE int f_isinreg(int r)
+{
+	return live.fate[r].status==CLEAN || live.fate[r].status==DIRTY;
+}
+
+static void f_evict(int r)
+{
+	int rr;
+
+	if (!f_isinreg(r))
+		return;
+	rr=live.fate[r].realreg;
+	if (live.fat[rr].nholds==1)
+		f_tomem_drop(r);
+	else
+		f_tomem(r);
+
+	Dif (live.fat[rr].locked &&
+		live.fat[rr].nholds==1) {
+			jit_abort (_T("JIT: FPU register %d in nreg %d is locked!\n"),r,live.fate[r].realreg);
+	}
+
+	live.fat[rr].nholds--;
+	if (live.fat[rr].nholds!=live.fate[r].realind) { /* Was not last */
+		int topreg=live.fat[rr].holds[live.fat[rr].nholds];
+		int thisind=live.fate[r].realind;
+		live.fat[rr].holds[thisind]=topreg;
+		live.fate[topreg].realind=thisind;
+	}
+	live.fate[r].status=INMEM;
+	live.fate[r].realreg=-1;
+}
+
+STATIC_INLINE void f_free_nreg(int r)
+{
+	int i=live.fat[r].nholds;
+
+	while (i) {
+		int vr;
+
+		--i;
+		vr=live.fat[r].holds[i];
+		f_evict(vr);
+	}
+	Dif (live.fat[r].nholds!=0) {
+		jit_abort (_T("JIT: Failed to free nreg %d, nholds is %d\n"),r,live.fat[r].nholds);
+	}
+}
+
+
+/* Use with care! */
+STATIC_INLINE void f_isclean(int r)
+{
+	if (!f_isinreg(r))
+		return;
+	live.fate[r].status=CLEAN;
+}
+
+STATIC_INLINE void f_disassociate(int r)
+{
+	f_isclean(r);
+	f_evict(r);
+}
+
+
+
+static  int f_alloc_reg(int r, int willclobber)
+{
+	int bestreg;
+	uae_s32 when;
+	int i;
+	uae_s32 badness;
+	bestreg=-1;
+	when=2000000000;
+	for (i=N_FREGS;i--;) {
+		badness=live.fat[i].touched;
+		if (live.fat[i].nholds==0)
+			badness=0;
+
+		if (!live.fat[i].locked && badness0) {
+		f_free_nreg(bestreg);
+	}
+	if (f_isinreg(r)) {
+		f_evict(r);
+	}
+
+	if (!willclobber) {
+		if (live.fate[r].status!=UNDEF) {
+#if USE_LONG_DOUBLE
+			raw_fmov_ext_rm(bestreg,(uae_u32)live.fate[r].mem);
+#else
+			raw_fmov_rm(bestreg,(uae_u32)live.fate[r].mem);
+#endif
+		}
+		live.fate[r].status=CLEAN;
+	}
+	else {
+		live.fate[r].status=DIRTY;
+	}
+	live.fate[r].realreg=bestreg;
+	live.fate[r].realind=live.fat[bestreg].nholds;
+	live.fat[bestreg].touched=touchcnt++;
+	live.fat[bestreg].holds[live.fat[bestreg].nholds]=r;
+	live.fat[bestreg].nholds++;
+
+	return bestreg;
+}
+
+static  void f_unlock(int r)
+{
+	Dif (!live.fat[r].locked)
+		jit_abort (_T("unlock %d"), r);
+	live.fat[r].locked--;
+}
+
+static  void f_setlock(int r)
+{
+	live.fat[r].locked++;
+}
+
+STATIC_INLINE int f_readreg(int r)
+{
+	int n;
+	int answer=-1;
+
+	if (f_isinreg(r)) {
+		n=live.fate[r].realreg;
+		answer=n;
+	}
+	/* either the value was in memory to start with, or it was evicted and
+	is in memory now */
+	if (answer<0)
+		answer=f_alloc_reg(r,0);
+
+	live.fat[answer].locked++;
+	live.fat[answer].touched=touchcnt++;
+	return answer;
+}
+
+STATIC_INLINE void f_make_exclusive(int r, int clobber)
+{
+	freg_status oldstate;
+	int rr=live.fate[r].realreg;
+	int nr;
+	int nind;
+	int ndirt=0;
+	int i;
+
+	if (!f_isinreg(r))
+		return;
+	if (live.fat[rr].nholds==1)
+		return;
+	for (i=0;i>=i;
+		return;
+	}
+	CLOBBER_SHRL;
+	r=rmw(r,4,4);
+	raw_shrl_l_ri(r,i);
+	unlock(r);
+}
+MENDFUNC(2,shrl_l_ri,(RW4 r, IMM i))
+
+	MIDFUNC(2,shrl_w_ri,(RW2 r, IMM i))
+{
+	if (!i && !needflags)
+		return;
+	CLOBBER_SHRL;
+	r=rmw(r,2,2);
+	raw_shrl_w_ri(r,i);
+	unlock(r);
+}
+MENDFUNC(2,shrl_w_ri,(RW2 r, IMM i))
+
+	MIDFUNC(2,shrl_b_ri,(RW1 r, IMM i))
+{
+	if (!i && !needflags)
+		return;
+	CLOBBER_SHRL;
+	r=rmw(r,1,1);
+	raw_shrl_b_ri(r,i);
+	unlock(r);
+}
+MENDFUNC(2,shrl_b_ri,(RW1 r, IMM i))
+
+	MIDFUNC(2,shra_l_ri,(RW4 r, IMM i))
+{
+	if (!i && !needflags)
+		return;
+	CLOBBER_SHRA;
+	r=rmw(r,4,4);
+	raw_shra_l_ri(r,i);
+	unlock(r);
+}
+MENDFUNC(2,shra_l_ri,(RW4 r, IMM i))
+
+	MIDFUNC(2,shra_w_ri,(RW2 r, IMM i))
+{
+	if (!i && !needflags)
+		return;
+	CLOBBER_SHRA;
+	r=rmw(r,2,2);
+	raw_shra_w_ri(r,i);
+	unlock(r);
+}
+MENDFUNC(2,shra_w_ri,(RW2 r, IMM i))
+
+	MIDFUNC(2,shra_b_ri,(RW1 r, IMM i))
+{
+	if (!i && !needflags)
+		return;
+	CLOBBER_SHRA;
+	r=rmw(r,1,1);
+	raw_shra_b_ri(r,i);
+	unlock(r);
+}
+MENDFUNC(2,shra_b_ri,(RW1 r, IMM i))
+
+	MIDFUNC(2,shra_l_rr,(RW4 d, R1 r))
+{
+	if (isconst(r)) {
+		COMPCALL(shra_l_ri)(d,(uae_u8)live.state[r].val);
+		return;
+	}
+	CLOBBER_SHRA;
+	r=readreg_specific(r,1,SHIFTCOUNT_NREG);
+	d=rmw(d,4,4);
+	Dif (r!=1) {
+		jit_abort (_T("JIT: Illegal register %d in raw_rol_b\n"),r);
+	}
+	raw_shra_l_rr(d,r) ;
+	unlock(r);
+	unlock(d);
+}
+MENDFUNC(2,shra_l_rr,(RW4 d, R1 r))
+
+	MIDFUNC(2,shra_w_rr,(RW2 d, R1 r))
+{ /* Can only do this with r==1, i.e. cl */
+
+	if (isconst(r)) {
+		COMPCALL(shra_w_ri)(d,(uae_u8)live.state[r].val);
+		return;
+	}
+	CLOBBER_SHRA;
+	r=readreg_specific(r,1,SHIFTCOUNT_NREG);
+	d=rmw(d,2,2);
+	Dif (r!=1) {
+		jit_abort (_T("JIT: Illegal register %d in raw_shra_b\n"),r);
+	}
+	raw_shra_w_rr(d,r) ;
+	unlock(r);
+	unlock(d);
+}
+MENDFUNC(2,shra_w_rr,(RW2 d, R1 r))
+
+	MIDFUNC(2,shra_b_rr,(RW1 d, R1 r))
+{ /* Can only do this with r==1, i.e. cl */
+
+	if (isconst(r)) {
+		COMPCALL(shra_b_ri)(d,(uae_u8)live.state[r].val);
+		return;
+	}
+
+	CLOBBER_SHRA;
+	r=readreg_specific(r,1,SHIFTCOUNT_NREG);
+	d=rmw(d,1,1);
+	Dif (r!=1) {
+		jit_abort (_T("JIT: Illegal register %d in raw_shra_b\n"),r);
+	}
+	raw_shra_b_rr(d,r) ;
+	unlock(r);
+	unlock(d);
+}
+MENDFUNC(2,shra_b_rr,(RW1 d, R1 r))
+
+	MIDFUNC(2,setcc,(W1 d, IMM cc))
+{
+	CLOBBER_SETCC;
+	d=writereg(d,1);
+	raw_setcc(d,cc);
+	unlock(d);
+}
+MENDFUNC(2,setcc,(W1 d, IMM cc))
+
+	MIDFUNC(2,setcc_m,(IMM d, IMM cc))
+{
+	CLOBBER_SETCC;
+	raw_setcc_m(d,cc);
+}
+MENDFUNC(2,setcc_m,(IMM d, IMM cc))
+
+	MIDFUNC(3,cmov_b_rr,(RW1 d, R1 s, IMM cc))
+{
+	if (d==s)
+		return;
+	CLOBBER_CMOV;
+	s=readreg(s,1);
+	d=rmw(d,1,1);
+	raw_cmov_b_rr(d,s,cc);
+	unlock(s);
+	unlock(d);
+}
+MENDFUNC(3,cmov_b_rr,(RW1 d, R1 s, IMM cc))
+
+	MIDFUNC(3,cmov_w_rr,(RW2 d, R2 s, IMM cc))
+{
+	if (d==s)
+		return;
+	CLOBBER_CMOV;
+	s=readreg(s,2);
+	d=rmw(d,2,2);
+	raw_cmov_w_rr(d,s,cc);
+	unlock(s);
+	unlock(d);
+}
+MENDFUNC(3,cmov_w_rr,(RW2 d, R2 s, IMM cc))
+
+	MIDFUNC(3,cmov_l_rr,(RW4 d, R4 s, IMM cc))
+{
+	if (d==s)
+		return;
+	CLOBBER_CMOV;
+	s=readreg(s,4);
+	d=rmw(d,4,4);
+	raw_cmov_l_rr(d,s,cc);
+	unlock(s);
+	unlock(d);
+}
+MENDFUNC(3,cmov_l_rr,(RW4 d, R4 s, IMM cc))
+
+	MIDFUNC(1,setzflg_l,(RW4 r))
+{
+	if (setzflg_uses_bsf) {
+		CLOBBER_BSF;
+		r=rmw(r,4,4);
+		raw_bsf_l_rr(r,r);
+		unlock(r);
+	}
+	else {
+		Dif (live.flags_in_flags!=VALID) {
+			jit_abort (_T("JIT: setzflg() wanted flags in native flags, they are %d\n"),
+				live.flags_in_flags);
+		}
+		r=readreg(r,4);
+		{
+			int f=writereg(S11,4);
+			int t=writereg(S12,4);
+			raw_flags_set_zero(f,r,t);
+			unlock(f);
+			unlock(r);
+			unlock(t);
+		}
+	}
+}
+MENDFUNC(1,setzflg_l,(RW4 r))
+
+	MIDFUNC(3,cmov_l_rm,(RW4 d, IMM s, IMM cc))
+{
+	CLOBBER_CMOV;
+	d=rmw(d,4,4);
+	raw_cmov_l_rm(d,s,cc);
+	unlock(d);
+}
+MENDFUNC(3,cmov_l_rm,(RW4 d, IMM s, IMM cc))
+
+	MIDFUNC(2,bsf_l_rr,(W4 d, R4 s))
+{
+	CLOBBER_BSF;
+	s=readreg(s,4);
+	d=writereg(d,4);
+	raw_bsf_l_rr(d,s);
+	unlock(s);
+	unlock(d);
+}
+MENDFUNC(2,bsf_l_rr,(W4 d, R4 s))
+
+	MIDFUNC(2,imul_32_32,(RW4 d, R4 s))
+{
+	CLOBBER_MUL;
+	s=readreg(s,4);
+	d=rmw(d,4,4);
+	raw_imul_32_32(d,s);
+	unlock(s);
+	unlock(d);
+}
+MENDFUNC(2,imul_32_32,(RW4 d, R4 s))
+
+	MIDFUNC(2,imul_64_32,(RW4 d, RW4 s))
+{
+	CLOBBER_MUL;
+	s=rmw_specific(s,4,4,MUL_NREG2);
+	d=rmw_specific(d,4,4,MUL_NREG1);
+	raw_imul_64_32(d,s);
+	unlock(s);
+	unlock(d);
+}
+MENDFUNC(2,imul_64_32,(RW4 d, RW4 s))
+
+	MIDFUNC(2,mul_64_32,(RW4 d, RW4 s))
+{
+	CLOBBER_MUL;
+	s=rmw_specific(s,4,4,MUL_NREG2);
+	d=rmw_specific(d,4,4,MUL_NREG1);
+	raw_mul_64_32(d,s);
+	unlock(s);
+	unlock(d);
+}
+MENDFUNC(2,mul_64_32,(RW4 d, RW4 s))
+
+	MIDFUNC(2,sign_extend_16_rr,(W4 d, R2 s))
+{
+	int isrmw;
+
+	if (isconst(s)) {
+		set_const(d,(uae_s32)(uae_s16)live.state[s].val);
+		return;
+	}
+
+	CLOBBER_SE16;
+	isrmw=(s==d);
+	if (!isrmw) {
+		s=readreg(s,2);
+		d=writereg(d,4);
+	}
+	else {  /* If we try to lock this twice, with different sizes, we
+			are int trouble! */
+		s=d=rmw(s,4,2);
+	}
+	raw_sign_extend_16_rr(d,s);
+	if (!isrmw) {
+		unlock(d);
+		unlock(s);
+	}
+	else {
+		unlock(s);
+	}
+}
+MENDFUNC(2,sign_extend_16_rr,(W4 d, R2 s))
+
+	MIDFUNC(2,sign_extend_8_rr,(W4 d, R1 s))
+{
+	int isrmw;
+
+	if (isconst(s)) {
+		set_const(d,(uae_s32)(uae_s8)live.state[s].val);
+		return;
+	}
+
+	isrmw=(s==d);
+	CLOBBER_SE8;
+	if (!isrmw) {
+		s=readreg(s,1);
+		d=writereg(d,4);
+	}
+	else {  /* If we try to lock this twice, with different sizes, we
+			are int trouble! */
+		s=d=rmw(s,4,1);
+	}
+
+	raw_sign_extend_8_rr(d,s);
+
+	if (!isrmw) {
+		unlock(d);
+		unlock(s);
+	}
+	else {
+		unlock(s);
+	}
+}
+MENDFUNC(2,sign_extend_8_rr,(W4 d, R1 s))
+
+	MIDFUNC(2,zero_extend_16_rr,(W4 d, R2 s))
+{
+	int isrmw;
+
+	if (isconst(s)) {
+		set_const(d,(uae_u32)(uae_u16)live.state[s].val);
+		return;
+	}
+
+	isrmw=(s==d);
+	CLOBBER_ZE16;
+	if (!isrmw) {
+		s=readreg(s,2);
+		d=writereg(d,4);
+	}
+	else {  /* If we try to lock this twice, with different sizes, we
+			are int trouble! */
+		s=d=rmw(s,4,2);
+	}
+	raw_zero_extend_16_rr(d,s);
+	if (!isrmw) {
+		unlock(d);
+		unlock(s);
+	}
+	else {
+		unlock(s);
+	}
+}
+MENDFUNC(2,zero_extend_16_rr,(W4 d, R2 s))
+
+	MIDFUNC(2,zero_extend_8_rr,(W4 d, R1 s))
+{
+	int isrmw;
+	if (isconst(s)) {
+		set_const(d,(uae_u32)(uae_u8)live.state[s].val);
+		return;
+	}
+
+	isrmw=(s==d);
+	CLOBBER_ZE8;
+	if (!isrmw) {
+		s=readreg(s,1);
+		d=writereg(d,4);
+	}
+	else {  /* If we try to lock this twice, with different sizes, we
+			are int trouble! */
+		s=d=rmw(s,4,1);
+	}
+
+	raw_zero_extend_8_rr(d,s);
+
+	if (!isrmw) {
+		unlock(d);
+		unlock(s);
+	}
+	else {
+		unlock(s);
+	}
+}
+MENDFUNC(2,zero_extend_8_rr,(W4 d, R1 s))
+
+	MIDFUNC(2,mov_b_rr,(W1 d, R1 s))
+{
+	if (d==s)
+		return;
+	if (isconst(s)) {
+		COMPCALL(mov_b_ri)(d,(uae_u8)live.state[s].val);
+		return;
+	}
+
+	CLOBBER_MOV;
+	s=readreg(s,1);
+	d=writereg(d,1);
+	raw_mov_b_rr(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,mov_b_rr,(W1 d, R1 s))
+
+	MIDFUNC(2,mov_w_rr,(W2 d, R2 s))
+{
+	if (d==s)
+		return;
+	if (isconst(s)) {
+		COMPCALL(mov_w_ri)(d,(uae_u16)live.state[s].val);
+		return;
+	}
+
+	CLOBBER_MOV;
+	s=readreg(s,2);
+	d=writereg(d,2);
+	raw_mov_w_rr(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,mov_w_rr,(W2 d, R2 s))
+
+	MIDFUNC(3,mov_l_rrm_indexed,(W4 d,R4 baser, R4 index))
+{
+	CLOBBER_MOV;
+	baser=readreg(baser,4);
+	index=readreg(index,4);
+	d=writereg(d,4);
+
+	raw_mov_l_rrm_indexed(d,baser,index);
+	unlock(d);
+	unlock(baser);
+	unlock(index);
+}
+MENDFUNC(3,mov_l_rrm_indexed,(W4 d,R4 baser, R4 index))
+
+	MIDFUNC(3,mov_w_rrm_indexed,(W2 d, R4 baser, R4 index))
+{
+	CLOBBER_MOV;
+	baser=readreg(baser,4);
+	index=readreg(index,4);
+	d=writereg(d,2);
+
+	raw_mov_w_rrm_indexed(d,baser,index);
+	unlock(d);
+	unlock(baser);
+	unlock(index);
+}
+MENDFUNC(3,mov_w_rrm_indexed,(W2 d, R4 baser, R4 index))
+
+	MIDFUNC(3,mov_b_rrm_indexed,(W1 d, R4 baser, R4 index))
+{
+	CLOBBER_MOV;
+	baser=readreg(baser,4);
+	index=readreg(index,4);
+	d=writereg(d,1);
+
+	raw_mov_b_rrm_indexed(d,baser,index);
+
+	unlock(d);
+	unlock(baser);
+	unlock(index);
+}
+MENDFUNC(3,mov_b_rrm_indexed,(W1 d, R4 baser, R4 index))
+
+	MIDFUNC(3,mov_l_mrr_indexed,(R4 baser, R4 index, R4 s))
+{
+	CLOBBER_MOV;
+	baser=readreg(baser,4);
+	index=readreg(index,4);
+	s=readreg(s,4);
+
+	Dif (baser==s || index==s)
+		jit_abort (_T("mov_l_mrr_indexed"));
+
+	raw_mov_l_mrr_indexed(baser,index,s);
+	unlock(s);
+	unlock(baser);
+	unlock(index);
+}
+MENDFUNC(3,mov_l_mrr_indexed,(R4 baser, R4 index, R4 s))
+
+	MIDFUNC(3,mov_w_mrr_indexed,(R4 baser, R4 index, R2 s))
+{
+	CLOBBER_MOV;
+	baser=readreg(baser,4);
+	index=readreg(index,4);
+	s=readreg(s,2);
+
+	raw_mov_w_mrr_indexed(baser,index,s);
+	unlock(s);
+	unlock(baser);
+	unlock(index);
+}
+MENDFUNC(3,mov_w_mrr_indexed,(R4 baser, R4 index, R2 s))
+
+	MIDFUNC(3,mov_b_mrr_indexed,(R4 baser, R4 index, R1 s))
+{
+	CLOBBER_MOV;
+	s=readreg(s,1);
+	baser=readreg(baser,4);
+	index=readreg(index,4);
+
+	raw_mov_b_mrr_indexed(baser,index,s);
+	unlock(s);
+	unlock(baser);
+	unlock(index);
+}
+MENDFUNC(3,mov_b_mrr_indexed,(R4 baser, R4 index, R1 s))
+
+	/* Read a long from base+4*index */
+	MIDFUNC(3,mov_l_rm_indexed,(W4 d, IMM base, R4 index))
+{
+	int indexreg=index;
+
+	if (isconst(index)) {
+		COMPCALL(mov_l_rm)(d,base+4*live.state[index].val);
+		return;
+	}
+
+	CLOBBER_MOV;
+	index=readreg_offset(index,4);
+	base+=get_offset(indexreg)*4;
+	d=writereg(d,4);
+
+	raw_mov_l_rm_indexed(d,base,index);
+	unlock(index);
+	unlock(d);
+}
+MENDFUNC(3,mov_l_rm_indexed,(W4 d, IMM base, R4 index))
+
+	/* read the long at the address contained in s+offset and store in d */
+	MIDFUNC(3,mov_l_rR,(W4 d, R4 s, IMM offset))
+{
+	if (isconst(s)) {
+		COMPCALL(mov_l_rm)(d,live.state[s].val+offset);
+		return;
+	}
+	CLOBBER_MOV;
+	s=readreg(s,4);
+	d=writereg(d,4);
+
+	raw_mov_l_rR(d,s,offset);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(3,mov_l_rR,(W4 d, R4 s, IMM offset))
+
+	/* read the word at the address contained in s+offset and store in d */
+	MIDFUNC(3,mov_w_rR,(W2 d, R4 s, IMM offset))
+{
+	if (isconst(s)) {
+		COMPCALL(mov_w_rm)(d,live.state[s].val+offset);
+		return;
+	}
+	CLOBBER_MOV;
+	s=readreg(s,4);
+	d=writereg(d,2);
+
+	raw_mov_w_rR(d,s,offset);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(3,mov_w_rR,(W2 d, R4 s, IMM offset))
+
+	/* read the word at the address contained in s+offset and store in d */
+	MIDFUNC(3,mov_b_rR,(W1 d, R4 s, IMM offset))
+{
+	if (isconst(s)) {
+		COMPCALL(mov_b_rm)(d,live.state[s].val+offset);
+		return;
+	}
+	CLOBBER_MOV;
+	s=readreg(s,4);
+	d=writereg(d,1);
+
+	raw_mov_b_rR(d,s,offset);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(3,mov_b_rR,(W1 d, R4 s, IMM offset))
+
+	/* read the long at the address contained in s+offset and store in d */
+	MIDFUNC(3,mov_l_brR,(W4 d, R4 s, IMM offset))
+{
+	int sreg=s;
+	if (isconst(s)) {
+		COMPCALL(mov_l_rm)(d,live.state[s].val+offset);
+		return;
+	}
+	CLOBBER_MOV;
+	s=readreg_offset(s,4);
+	offset+=get_offset(sreg);
+	d=writereg(d,4);
+
+	raw_mov_l_brR(d,s,offset);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(3,mov_l_brR,(W4 d, R4 s, IMM offset))
+
+	/* read the word at the address contained in s+offset and store in d */
+	MIDFUNC(3,mov_w_brR,(W2 d, R4 s, IMM offset))
+{
+	int sreg=s;
+	if (isconst(s)) {
+		COMPCALL(mov_w_rm)(d,live.state[s].val+offset);
+		return;
+	}
+	CLOBBER_MOV;
+	remove_offset(d,-1);
+	s=readreg_offset(s,4);
+	offset+=get_offset(sreg);
+	d=writereg(d,2);
+
+	raw_mov_w_brR(d,s,offset);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(3,mov_w_brR,(W2 d, R4 s, IMM offset))
+
+	/* read the word at the address contained in s+offset and store in d */
+	MIDFUNC(3,mov_b_brR,(W1 d, R4 s, IMM offset))
+{
+	int sreg=s;
+	if (isconst(s)) {
+		COMPCALL(mov_b_rm)(d,live.state[s].val+offset);
+		return;
+	}
+	CLOBBER_MOV;
+	remove_offset(d,-1);
+	s=readreg_offset(s,4);
+	offset+=get_offset(sreg);
+	d=writereg(d,1);
+
+	raw_mov_b_brR(d,s,offset);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(3,mov_b_brR,(W1 d, R4 s, IMM offset))
+
+	MIDFUNC(3,mov_l_Ri,(R4 d, IMM i, IMM offset))
+{
+	int dreg=d;
+	if (isconst(d)) {
+		COMPCALL(mov_l_mi)(live.state[d].val+offset,i);
+		return;
+	}
+
+	CLOBBER_MOV;
+	d=readreg_offset(d,4);
+	offset+=get_offset(dreg);
+	raw_mov_l_Ri(d,i,offset);
+	unlock(d);
+}
+MENDFUNC(3,mov_l_Ri,(R4 d, IMM i, IMM offset))
+
+	MIDFUNC(3,mov_w_Ri,(R4 d, IMM i, IMM offset))
+{
+	int dreg=d;
+	if (isconst(d)) {
+		COMPCALL(mov_w_mi)(live.state[d].val+offset,i);
+		return;
+	}
+
+	CLOBBER_MOV;
+	d=readreg_offset(d,4);
+	offset+=get_offset(dreg);
+	raw_mov_w_Ri(d,i,offset);
+	unlock(d);
+}
+MENDFUNC(3,mov_w_Ri,(R4 d, IMM i, IMM offset))
+
+	MIDFUNC(3,mov_b_Ri,(R4 d, IMM i, IMM offset))
+{
+	int dreg=d;
+	if (isconst(d)) {
+		COMPCALL(mov_b_mi)(live.state[d].val+offset,i);
+		return;
+	}
+
+	CLOBBER_MOV;
+	d=readreg_offset(d,4);
+	offset+=get_offset(dreg);
+	raw_mov_b_Ri(d,i,offset);
+	unlock(d);
+}
+MENDFUNC(3,mov_b_Ri,(R4 d, IMM i, IMM offset))
+
+	/* Warning! OFFSET is byte sized only! */
+	MIDFUNC(3,mov_l_Rr,(R4 d, R4 s, IMM offset))
+{
+	if (isconst(d)) {
+		COMPCALL(mov_l_mr)(live.state[d].val+offset,s);
+		return;
+	}
+	if (isconst(s)) {
+		COMPCALL(mov_l_Ri)(d,live.state[s].val,offset);
+		return;
+	}
+
+	CLOBBER_MOV;
+	s=readreg(s,4);
+	d=readreg(d,4);
+
+	raw_mov_l_Rr(d,s,offset);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(3,mov_l_Rr,(R4 d, R4 s, IMM offset))
+
+	MIDFUNC(3,mov_w_Rr,(R4 d, R2 s, IMM offset))
+{
+	if (isconst(d)) {
+		COMPCALL(mov_w_mr)(live.state[d].val+offset,s);
+		return;
+	}
+	if (isconst(s)) {
+		COMPCALL(mov_w_Ri)(d,(uae_u16)live.state[s].val,offset);
+		return;
+	}
+
+	CLOBBER_MOV;
+	s=readreg(s,2);
+	d=readreg(d,4);
+	raw_mov_w_Rr(d,s,offset);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(3,mov_w_Rr,(R4 d, R2 s, IMM offset))
+
+	MIDFUNC(3,mov_b_Rr,(R4 d, R1 s, IMM offset))
+{
+	if (isconst(d)) {
+		COMPCALL(mov_b_mr)(live.state[d].val+offset,s);
+		return;
+	}
+	if (isconst(s)) {
+		COMPCALL(mov_b_Ri)(d,(uae_u8)live.state[s].val,offset);
+		return;
+	}
+
+	CLOBBER_MOV;
+	s=readreg(s,1);
+	d=readreg(d,4);
+	raw_mov_b_Rr(d,s,offset);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(3,mov_b_Rr,(R4 d, R1 s, IMM offset))
+
+	MIDFUNC(3,lea_l_brr,(W4 d, R4 s, IMM offset))
+{
+	if (isconst(s)) {
+		COMPCALL(mov_l_ri)(d,live.state[s].val+offset);
+		return;
+	}
+#if USE_OFFSET
+	if (d==s) {
+		add_offset(d,offset);
+		return;
+	}
+#endif
+	CLOBBER_LEA;
+	s=readreg(s,4);
+	d=writereg(d,4);
+	raw_lea_l_brr(d,s,offset);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(3,lea_l_brr,(W4 d, R4 s, IMM offset))
+
+	MIDFUNC(5,lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
+{
+	CLOBBER_LEA;
+	s=readreg(s,4);
+	index=readreg(index,4);
+	d=writereg(d,4);
+
+	raw_lea_l_brr_indexed(d,s,index,factor,offset);
+	unlock(d);
+	unlock(index);
+	unlock(s);
+}
+MENDFUNC(5,lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
+
+	/* write d to the long at the address contained in s+offset */
+	MIDFUNC(3,mov_l_bRr,(R4 d, R4 s, IMM offset))
+{
+	int dreg=d;
+	if (isconst(d)) {
+		COMPCALL(mov_l_mr)(live.state[d].val+offset,s);
+		return;
+	}
+
+	CLOBBER_MOV;
+	s=readreg(s,4);
+	d=readreg_offset(d,4);
+	offset+=get_offset(dreg);
+
+	raw_mov_l_bRr(d,s,offset);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(3,mov_l_bRr,(R4 d, R4 s, IMM offset))
+
+	/* write the word at the address contained in s+offset and store in d */
+	MIDFUNC(3,mov_w_bRr,(R4 d, R2 s, IMM offset))
+{
+	int dreg=d;
+
+	if (isconst(d)) {
+		COMPCALL(mov_w_mr)(live.state[d].val+offset,s);
+		return;
+	}
+
+	CLOBBER_MOV;
+	s=readreg(s,2);
+	d=readreg_offset(d,4);
+	offset+=get_offset(dreg);
+	raw_mov_w_bRr(d,s,offset);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(3,mov_w_bRr,(R4 d, R2 s, IMM offset))
+
+	MIDFUNC(3,mov_b_bRr,(R4 d, R1 s, IMM offset))
+{
+	int dreg=d;
+	if (isconst(d)) {
+		COMPCALL(mov_b_mr)(live.state[d].val+offset,s);
+		return;
+	}
+
+	CLOBBER_MOV;
+	s=readreg(s,1);
+	d=readreg_offset(d,4);
+	offset+=get_offset(dreg);
+	raw_mov_b_bRr(d,s,offset);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(3,mov_b_bRr,(R4 d, R1 s, IMM offset))
+
+	MIDFUNC(1,gen_bswap_32,(RW4 r))
+{
+	int reg=r;
+
+	if (isconst(r)) {
+		uae_u32 oldv=live.state[r].val;
+		live.state[r].val=reverse32(oldv);
+		return;
+	}
+
+	CLOBBER_SW32;
+	r=rmw(r,4,4);
+	raw_bswap_32(r);
+	unlock(r);
+}
+MENDFUNC(1,gen_bswap_32,(RW4 r))
+
+	MIDFUNC(1,gen_bswap_16,(RW2 r))
+{
+	if (isconst(r)) {
+		uae_u32 oldv=live.state[r].val;
+		live.state[r].val=((oldv>>8)&0xff) | ((oldv<<8)&0xff00) |
+			(oldv&0xffff0000);
+		return;
+	}
+
+	CLOBBER_SW16;
+	r=rmw(r,2,2);
+
+	raw_bswap_16(r);
+	unlock(r);
+}
+MENDFUNC(1,gen_bswap_16,(RW2 r))
+
+
+
+	MIDFUNC(2,mov_l_rr,(W4 d, R4 s))
+{
+	int olds;
+
+	if (d==s) { /* How pointless! */
+		return;
+	}
+	if (isconst(s)) {
+		COMPCALL(mov_l_ri)(d,live.state[s].val);
+		return;
+	}
+#if USE_ALIAS
+	olds=s;
+	disassociate(d);
+	s=readreg_offset(s,4);
+	live.state[d].realreg=s;
+	live.state[d].realind=live.nat[s].nholds;
+	live.state[d].val=live.state[olds].val;
+	live.state[d].validsize=4;
+	live.state[d].dirtysize=4;
+	set_status(d,DIRTY);
+
+	live.nat[s].holds[live.nat[s].nholds]=d;
+	live.nat[s].nholds++;
+	log_clobberreg(d);
+
+	/* write_log (_T("JIT: Added %d to nreg %d(%d), now holds %d regs\n"),
+	d,s,live.state[d].realind,live.nat[s].nholds); */
+	unlock(s);
+#else
+	CLOBBER_MOV;
+	s=readreg(s,4);
+	d=writereg(d,4);
+
+	raw_mov_l_rr(d,s);
+	unlock(d);
+	unlock(s);
+#endif
+}
+MENDFUNC(2,mov_l_rr,(W4 d, R4 s))
+
+	MIDFUNC(2,mov_l_mr,(IMM d, R4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(mov_l_mi)(d,live.state[s].val);
+		return;
+	}
+	CLOBBER_MOV;
+	s=readreg(s,4);
+
+	raw_mov_l_mr(d,s);
+	unlock(s);
+}
+MENDFUNC(2,mov_l_mr,(IMM d, R4 s))
+
+
+	MIDFUNC(2,mov_w_mr,(IMM d, R2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(mov_w_mi)(d,(uae_u16)live.state[s].val);
+		return;
+	}
+	CLOBBER_MOV;
+	s=readreg(s,2);
+
+	raw_mov_w_mr(d,s);
+	unlock(s);
+}
+MENDFUNC(2,mov_w_mr,(IMM d, R2 s))
+
+	MIDFUNC(2,mov_w_rm,(W2 d, IMM s))
+{
+	CLOBBER_MOV;
+	d=writereg(d,2);
+
+	raw_mov_w_rm(d,s);
+	unlock(d);
+}
+MENDFUNC(2,mov_w_rm,(W2 d, IMM s))
+
+	MIDFUNC(2,mov_b_mr,(IMM d, R1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(mov_b_mi)(d,(uae_u8)live.state[s].val);
+		return;
+	}
+
+	CLOBBER_MOV;
+	s=readreg(s,1);
+
+	raw_mov_b_mr(d,s);
+	unlock(s);
+}
+MENDFUNC(2,mov_b_mr,(IMM d, R1 s))
+
+	MIDFUNC(2,mov_b_rm,(W1 d, IMM s))
+{
+	CLOBBER_MOV;
+	d=writereg(d,1);
+
+	raw_mov_b_rm(d,s);
+	unlock(d);
+}
+MENDFUNC(2,mov_b_rm,(W1 d, IMM s))
+
+	MIDFUNC(2,mov_l_ri,(W4 d, IMM s))
+{
+	set_const(d,s);
+	return;
+}
+MENDFUNC(2,mov_l_ri,(W4 d, IMM s))
+
+	MIDFUNC(2,mov_w_ri,(W2 d, IMM s))
+{
+	CLOBBER_MOV;
+	d=writereg(d,2);
+
+	raw_mov_w_ri(d,s);
+	unlock(d);
+}
+MENDFUNC(2,mov_w_ri,(W2 d, IMM s))
+
+	MIDFUNC(2,mov_b_ri,(W1 d, IMM s))
+{
+	CLOBBER_MOV;
+	d=writereg(d,1);
+
+	raw_mov_b_ri(d,s);
+	unlock(d);
+}
+MENDFUNC(2,mov_b_ri,(W1 d, IMM s))
+
+
+	MIDFUNC(2,add_l_mi,(IMM d, IMM s))
+{
+	CLOBBER_ADD;
+	raw_add_l_mi(d,s) ;
+}
+MENDFUNC(2,add_l_mi,(IMM d, IMM s))
+
+	MIDFUNC(2,add_w_mi,(IMM d, IMM s))
+{
+	CLOBBER_ADD;
+	raw_add_w_mi(d,s) ;
+}
+MENDFUNC(2,add_w_mi,(IMM d, IMM s))
+
+	MIDFUNC(2,add_b_mi,(IMM d, IMM s))
+{
+	CLOBBER_ADD;
+	raw_add_b_mi(d,s) ;
+}
+MENDFUNC(2,add_b_mi,(IMM d, IMM s))
+
+
+	MIDFUNC(2,test_l_ri,(R4 d, IMM i))
+{
+	CLOBBER_TEST;
+	d=readreg(d,4);
+
+	raw_test_l_ri(d,i);
+	unlock(d);
+}
+MENDFUNC(2,test_l_ri,(R4 d, IMM i))
+
+	MIDFUNC(2,test_l_rr,(R4 d, R4 s))
+{
+	CLOBBER_TEST;
+	d=readreg(d,4);
+	s=readreg(s,4);
+
+	raw_test_l_rr(d,s);;
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,test_l_rr,(R4 d, R4 s))
+
+	MIDFUNC(2,test_w_rr,(R2 d, R2 s))
+{
+	CLOBBER_TEST;
+	d=readreg(d,2);
+	s=readreg(s,2);
+
+	raw_test_w_rr(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,test_w_rr,(R2 d, R2 s))
+
+	MIDFUNC(2,test_b_rr,(R1 d, R1 s))
+{
+	CLOBBER_TEST;
+	d=readreg(d,1);
+	s=readreg(s,1);
+
+	raw_test_b_rr(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,test_b_rr,(R1 d, R1 s))
+
+	MIDFUNC(2,and_l_ri,(RW4 d, IMM i))
+{
+	if (isconst (d) && ! needflags) {
+		live.state[d].val &= i;
+		return;
+	}
+
+	CLOBBER_AND;
+	d=rmw(d,4,4);
+
+	raw_and_l_ri(d,i);
+	unlock(d);
+}
+MENDFUNC(2,and_l_ri,(RW4 d, IMM i))
+
+	MIDFUNC(2,and_l,(RW4 d, R4 s))
+{
+	CLOBBER_AND;
+	s=readreg(s,4);
+	d=rmw(d,4,4);
+
+	raw_and_l(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,and_l,(RW4 d, R4 s))
+
+	MIDFUNC(2,and_w,(RW2 d, R2 s))
+{
+	CLOBBER_AND;
+	s=readreg(s,2);
+	d=rmw(d,2,2);
+
+	raw_and_w(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,and_w,(RW2 d, R2 s))
+
+	MIDFUNC(2,and_b,(RW1 d, R1 s))
+{
+	CLOBBER_AND;
+	s=readreg(s,1);
+	d=rmw(d,1,1);
+
+	raw_and_b(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,and_b,(RW1 d, R1 s))
+
+	MIDFUNC(2,or_l_ri,(RW4 d, IMM i))
+{
+	if (isconst(d) && !needflags) {
+		live.state[d].val|=i;
+		return;
+	}
+	CLOBBER_OR;
+	d=rmw(d,4,4);
+
+	raw_or_l_ri(d,i);
+	unlock(d);
+}
+MENDFUNC(2,or_l_ri,(RW4 d, IMM i))
+
+	MIDFUNC(2,or_l,(RW4 d, R4 s))
+{
+	if (isconst(d) && isconst(s) && !needflags) {
+		live.state[d].val|=live.state[s].val;
+		return;
+	}
+	CLOBBER_OR;
+	s=readreg(s,4);
+	d=rmw(d,4,4);
+
+	raw_or_l(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,or_l,(RW4 d, R4 s))
+
+	MIDFUNC(2,or_w,(RW2 d, R2 s))
+{
+	CLOBBER_OR;
+	s=readreg(s,2);
+	d=rmw(d,2,2);
+
+	raw_or_w(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,or_w,(RW2 d, R2 s))
+
+	MIDFUNC(2,or_b,(RW1 d, R1 s))
+{
+	CLOBBER_OR;
+	s=readreg(s,1);
+	d=rmw(d,1,1);
+
+	raw_or_b(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,or_b,(RW1 d, R1 s))
+
+	MIDFUNC(2,adc_l,(RW4 d, R4 s))
+{
+	CLOBBER_ADC;
+	s=readreg(s,4);
+	d=rmw(d,4,4);
+
+	raw_adc_l(d,s);
+
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,adc_l,(RW4 d, R4 s))
+
+	MIDFUNC(2,adc_w,(RW2 d, R2 s))
+{
+	CLOBBER_ADC;
+	s=readreg(s,2);
+	d=rmw(d,2,2);
+
+	raw_adc_w(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,adc_w,(RW2 d, R2 s))
+
+	MIDFUNC(2,adc_b,(RW1 d, R1 s))
+{
+	CLOBBER_ADC;
+	s=readreg(s,1);
+	d=rmw(d,1,1);
+
+	raw_adc_b(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,adc_b,(RW1 d, R1 s))
+
+	MIDFUNC(2,add_l,(RW4 d, R4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(add_l_ri)(d,live.state[s].val);
+		return;
+	}
+
+	CLOBBER_ADD;
+	s=readreg(s,4);
+	d=rmw(d,4,4);
+
+	raw_add_l(d,s);
+
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,add_l,(RW4 d, R4 s))
+
+	MIDFUNC(2,add_w,(RW2 d, R2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(add_w_ri)(d,(uae_u16)live.state[s].val);
+		return;
+	}
+
+	CLOBBER_ADD;
+	s=readreg(s,2);
+	d=rmw(d,2,2);
+
+	raw_add_w(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,add_w,(RW2 d, R2 s))
+
+	MIDFUNC(2,add_b,(RW1 d, R1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(add_b_ri)(d,(uae_u8)live.state[s].val);
+		return;
+	}
+
+	CLOBBER_ADD;
+	s=readreg(s,1);
+	d=rmw(d,1,1);
+
+	raw_add_b(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,add_b,(RW1 d, R1 s))
+
+	MIDFUNC(2,sub_l_ri,(RW4 d, IMM i))
+{
+	if (!i && !needflags)
+		return;
+	if (isconst(d) && !needflags) {
+		live.state[d].val-=i;
+		return;
+	}
+#if USE_OFFSET
+	if (!needflags) {
+		add_offset(d,-(signed)i);
+		return;
+	}
+#endif
+
+	CLOBBER_SUB;
+	d=rmw(d,4,4);
+
+	raw_sub_l_ri(d,i);
+	unlock(d);
+}
+MENDFUNC(2,sub_l_ri,(RW4 d, IMM i))
+
+	MIDFUNC(2,sub_w_ri,(RW2 d, IMM i))
+{
+	if (!i && !needflags)
+		return;
+
+	CLOBBER_SUB;
+	d=rmw(d,2,2);
+
+	raw_sub_w_ri(d,i);
+	unlock(d);
+}
+MENDFUNC(2,sub_w_ri,(RW2 d, IMM i))
+
+	MIDFUNC(2,sub_b_ri,(RW1 d, IMM i))
+{
+	if (!i && !needflags)
+		return;
+
+	CLOBBER_SUB;
+	d=rmw(d,1,1);
+
+	raw_sub_b_ri(d,i);
+
+	unlock(d);
+}
+MENDFUNC(2,sub_b_ri,(RW1 d, IMM i))
+
+	MIDFUNC(2,add_l_ri,(RW4 d, IMM i))
+{
+	if (!i && !needflags)
+		return;
+	if (isconst(d) && !needflags) {
+		live.state[d].val+=i;
+		return;
+	}
+#if USE_OFFSET
+	if (!needflags) {
+		add_offset(d,i);
+		return;
+	}
+#endif
+	CLOBBER_ADD;
+	d=rmw(d,4,4);
+	raw_add_l_ri(d,i);
+	unlock(d);
+}
+MENDFUNC(2,add_l_ri,(RW4 d, IMM i))
+
+	MIDFUNC(2,add_w_ri,(RW2 d, IMM i))
+{
+	if (!i && !needflags)
+		return;
+
+	CLOBBER_ADD;
+	d=rmw(d,2,2);
+
+	raw_add_w_ri(d,i);
+	unlock(d);
+}
+MENDFUNC(2,add_w_ri,(RW2 d, IMM i))
+
+	MIDFUNC(2,add_b_ri,(RW1 d, IMM i))
+{
+	if (!i && !needflags)
+		return;
+
+	CLOBBER_ADD;
+	d=rmw(d,1,1);
+
+	raw_add_b_ri(d,i);
+
+	unlock(d);
+}
+MENDFUNC(2,add_b_ri,(RW1 d, IMM i))
+
+	MIDFUNC(2,sbb_l,(RW4 d, R4 s))
+{
+	CLOBBER_SBB;
+	s=readreg(s,4);
+	d=rmw(d,4,4);
+
+	raw_sbb_l(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,sbb_l,(RW4 d, R4 s))
+
+	MIDFUNC(2,sbb_w,(RW2 d, R2 s))
+{
+	CLOBBER_SBB;
+	s=readreg(s,2);
+	d=rmw(d,2,2);
+
+	raw_sbb_w(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,sbb_w,(RW2 d, R2 s))
+
+	MIDFUNC(2,sbb_b,(RW1 d, R1 s))
+{
+	CLOBBER_SBB;
+	s=readreg(s,1);
+	d=rmw(d,1,1);
+
+	raw_sbb_b(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,sbb_b,(RW1 d, R1 s))
+
+	MIDFUNC(2,sub_l,(RW4 d, R4 s))
+{
+	if (isconst(s)) {
+		COMPCALL(sub_l_ri)(d,live.state[s].val);
+		return;
+	}
+
+	CLOBBER_SUB;
+	s=readreg(s,4);
+	d=rmw(d,4,4);
+
+	raw_sub_l(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,sub_l,(RW4 d, R4 s))
+
+	MIDFUNC(2,sub_w,(RW2 d, R2 s))
+{
+	if (isconst(s)) {
+		COMPCALL(sub_w_ri)(d,(uae_u16)live.state[s].val);
+		return;
+	}
+
+	CLOBBER_SUB;
+	s=readreg(s,2);
+	d=rmw(d,2,2);
+
+	raw_sub_w(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,sub_w,(RW2 d, R2 s))
+
+	MIDFUNC(2,sub_b,(RW1 d, R1 s))
+{
+	if (isconst(s)) {
+		COMPCALL(sub_b_ri)(d,(uae_u8)live.state[s].val);
+		return;
+	}
+
+	CLOBBER_SUB;
+	s=readreg(s,1);
+	d=rmw(d,1,1);
+
+	raw_sub_b(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,sub_b,(RW1 d, R1 s))
+
+	MIDFUNC(2,cmp_l,(R4 d, R4 s))
+{
+	CLOBBER_CMP;
+	s=readreg(s,4);
+	d=readreg(d,4);
+
+	raw_cmp_l(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,cmp_l,(R4 d, R4 s))
+
+	MIDFUNC(2,cmp_l_ri,(R4 r, IMM i))
+{
+	CLOBBER_CMP;
+	r=readreg(r,4);
+
+	raw_cmp_l_ri(r,i);
+	unlock(r);
+}
+MENDFUNC(2,cmp_l_ri,(R4 r, IMM i))
+
+	MIDFUNC(2,cmp_w,(R2 d, R2 s))
+{
+	CLOBBER_CMP;
+	s=readreg(s,2);
+	d=readreg(d,2);
+
+	raw_cmp_w(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,cmp_w,(R2 d, R2 s))
+
+	MIDFUNC(2,cmp_b,(R1 d, R1 s))
+{
+	CLOBBER_CMP;
+	s=readreg(s,1);
+	d=readreg(d,1);
+
+	raw_cmp_b(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,cmp_b,(R1 d, R1 s))
+
+
+	MIDFUNC(2,xor_l,(RW4 d, R4 s))
+{
+	CLOBBER_XOR;
+	s=readreg(s,4);
+	d=rmw(d,4,4);
+
+	raw_xor_l(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,xor_l,(RW4 d, R4 s))
+
+	MIDFUNC(2,xor_w,(RW2 d, R2 s))
+{
+	CLOBBER_XOR;
+	s=readreg(s,2);
+	d=rmw(d,2,2);
+
+	raw_xor_w(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,xor_w,(RW2 d, R2 s))
+
+	MIDFUNC(2,xor_b,(RW1 d, R1 s))
+{
+	CLOBBER_XOR;
+	s=readreg(s,1);
+	d=rmw(d,1,1);
+
+	raw_xor_b(d,s);
+	unlock(d);
+	unlock(s);
+}
+MENDFUNC(2,xor_b,(RW1 d, R1 s))
+
+	MIDFUNC(5,call_r_11,(W4 out1, R4 r, R4 in1, IMM osize, IMM isize))
+{
+	clobber_flags();
+	remove_all_offsets();
+	if (osize==4) {
+		if (out1!=in1 && out1!=r) {
+			COMPCALL(forget_about)(out1);
+		}
+	}
+	else {
+		tomem_c(out1);
+	}
+
+	in1=readreg_specific(in1,isize,REG_PAR1);
+	r=readreg(r,4);
+	prepare_for_call_1();  /* This should ensure that there won't be
+						   any need for swapping nregs in prepare_for_call_2
+						   */
+#if USE_NORMAL_CALLING_CONVENTION
+	raw_push_l_r(in1);
+#endif
+	unlock(in1);
+	unlock(r);
+
+	prepare_for_call_2();
+	raw_call_r(r);
+
+#if USE_NORMAL_CALLING_CONVENTION
+	raw_inc_sp(4);
+#endif
+
+
+	live.nat[REG_RESULT].holds[0]=out1;
+	live.nat[REG_RESULT].nholds=1;
+	live.nat[REG_RESULT].touched=touchcnt++;
+
+	live.state[out1].realreg=REG_RESULT;
+	live.state[out1].realind=0;
+	live.state[out1].val=0;
+	live.state[out1].validsize=osize;
+	live.state[out1].dirtysize=osize;
+	set_status(out1,DIRTY);
+}
+MENDFUNC(5,call_r_11,(W4 out1, R4 r, R4 in1, IMM osize, IMM isize))
+
+	MIDFUNC(5,call_r_02,(R4 r, R4 in1, R4 in2, IMM isize1, IMM isize2))
+{
+	clobber_flags();
+	remove_all_offsets();
+	in1=readreg_specific(in1,isize1,REG_PAR1);
+	in2=readreg_specific(in2,isize2,REG_PAR2);
+	r=readreg(r,4);
+	prepare_for_call_1();  /* This should ensure that there won't be
+						   any need for swapping nregs in prepare_for_call_2
+						   */
+#if USE_NORMAL_CALLING_CONVENTION
+	raw_push_l_r(in2);
+	raw_push_l_r(in1);
+#endif
+	unlock(r);
+	unlock(in1);
+	unlock(in2);
+	prepare_for_call_2();
+	raw_call_r(r);
+#if USE_NORMAL_CALLING_CONVENTION
+	raw_inc_sp(8);
+#endif
+}
+MENDFUNC(5,call_r_02,(R4 r, R4 in1, R4 in2, IMM isize1, IMM isize2))
+
+	MIDFUNC(1,forget_about,(W4 r))
+{
+	if (isinreg(r))
+		disassociate(r);
+	live.state[r].val=0;
+	set_status(r,UNDEF);
+}
+MENDFUNC(1,forget_about,(W4 r))
+
+	MIDFUNC(0,nop,(void))
+{
+	raw_nop();
+}
+MENDFUNC(0,nop,(void))
+
+	MIDFUNC(1,f_forget_about,(FW r))
+{
+	if (f_isinreg(r))
+		f_disassociate(r);
+	live.fate[r].status=UNDEF;
+}
+MENDFUNC(1,f_forget_about,(FW r))
+
+	MIDFUNC(1,fmov_pi,(FW r))
+{
+	r=f_writereg(r);
+	raw_fmov_pi(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fmov_pi,(FW r))
+
+	MIDFUNC(1,fmov_log10_2,(FW r))
+{
+	r=f_writereg(r);
+	raw_fmov_log10_2(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fmov_log10_2,(FW r))
+
+	MIDFUNC(1,fmov_log2_e,(FW r))
+{
+	r=f_writereg(r);
+	raw_fmov_log2_e(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fmov_log2_e,(FW r))
+
+	MIDFUNC(1,fmov_loge_2,(FW r))
+{
+	r=f_writereg(r);
+	raw_fmov_loge_2(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fmov_loge_2,(FW r))
+
+	MIDFUNC(1,fmov_1,(FW r))
+{
+	r=f_writereg(r);
+	raw_fmov_1(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fmov_1,(FW r))
+
+	MIDFUNC(1,fmov_0,(FW r))
+{
+	r=f_writereg(r);
+	raw_fmov_0(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fmov_0,(FW r))
+
+	MIDFUNC(2,fmov_rm,(FW r, MEMR m))
+{
+	r=f_writereg(r);
+	raw_fmov_rm(r,m);
+	f_unlock(r);
+}
+MENDFUNC(2,fmov_rm,(FW r, MEMR m))
+
+	MIDFUNC(2,fmovi_rm,(FW r, MEMR m))
+{
+	r=f_writereg(r);
+	raw_fmovi_rm(r,m);
+	f_unlock(r);
+}
+MENDFUNC(2,fmovi_rm,(FW r, MEMR m))
+
+	MIDFUNC(3,fmovi_mrb,(MEMW m, FR r, double *bounds))
+{
+	r=f_readreg(r);
+	raw_fmovi_mrb(m,r,bounds);
+	f_unlock(r);
+}
+MENDFUNC(3,fmovi_mrb,(MEMW m, FR r, double *bounds))
+
+	MIDFUNC(2,fmovs_rm,(FW r, MEMR m))
+{
+	r=f_writereg(r);
+	raw_fmovs_rm(r,m);
+	f_unlock(r);
+}
+MENDFUNC(2,fmovs_rm,(FW r, MEMR m))
+
+	MIDFUNC(2,fmovs_mr,(MEMW m, FR r))
+{
+	r=f_readreg(r);
+	raw_fmovs_mr(m,r);
+	f_unlock(r);
+}
+MENDFUNC(2,fmovs_mr,(MEMW m, FR r))
+
+	MIDFUNC(1,fcuts_r,(FRW r))
+{
+	r=f_rmw(r);
+	raw_fcuts_r(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fcuts_r,(FRW r))
+
+	MIDFUNC(1,fcut_r,(FRW r))
+{
+	r=f_rmw(r);
+	raw_fcut_r(r);
+	f_unlock(r);
+}
+MENDFUNC(1,fcut_r,(FRW r))
+
+	MIDFUNC(2,fmov_ext_mr,(MEMW m, FR r))
+{
+	r=f_readreg(r);
+	raw_fmov_ext_mr(m,r);
+	f_unlock(r);
+}
+MENDFUNC(2,fmov_ext_mr,(MEMW m, FR r))
+
+	MIDFUNC(2,fmov_mr,(MEMW m, FR r))
+{
+	r=f_readreg(r);
+	raw_fmov_mr(m,r);
+	f_unlock(r);
+}
+MENDFUNC(2,fmov_mr,(MEMW m, FR r))
+
+	MIDFUNC(2,fmov_ext_rm,(FW r, MEMR m))
+{
+	r=f_writereg(r);
+	raw_fmov_ext_rm(r,m);
+	f_unlock(r);
+}
+MENDFUNC(2,fmov_ext_rm,(FW r, MEMR m))
+
+	MIDFUNC(2,fmov_rr,(FW d, FR s))
+{
+	if (d==s) { /* How pointless! */
+		return;
+	}
+#if USE_F_ALIAS
+	f_disassociate(d);
+	s=f_readreg(s);
+	live.fate[d].realreg=s;
+	live.fate[d].realind=live.fat[s].nholds;
+	live.fate[d].status=DIRTY;
+	live.fat[s].holds[live.fat[s].nholds]=d;
+	live.fat[s].nholds++;
+	f_unlock(s);
+#else
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fmov_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+#endif
+}
+MENDFUNC(2,fmov_rr,(FW d, FR s))
+
+	MIDFUNC(2,fldcw_m_indexed,(R4 index, IMM base))
+{
+	index=readreg(index,4);
+
+	raw_fldcw_m_indexed(index,base);
+	unlock(index);
+}
+MENDFUNC(2,fldcw_m_indexed,(R4 index, IMM base))
+
+	MIDFUNC(1,ftst_r,(FR r))
+{
+	r=f_readreg(r);
+	raw_ftst_r(r);
+	f_unlock(r);
+}
+MENDFUNC(1,ftst_r,(FR r))
+
+	MIDFUNC(0,dont_care_fflags,(void))
+{
+	f_disassociate(FP_RESULT);
+}
+MENDFUNC(0,dont_care_fflags,(void))
+
+	MIDFUNC(2,fsqrt_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fsqrt_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fsqrt_rr,(FW d, FR s))
+
+	MIDFUNC(2,fabs_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fabs_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fabs_rr,(FW d, FR s))
+
+	MIDFUNC(2,frndint_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_frndint_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,frndint_rr,(FW d, FR s))
+
+	MIDFUNC(2,fgetexp_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fgetexp_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fgetexp_rr,(FW d, FR s))
+
+	MIDFUNC(2,fgetman_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fgetman_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fgetman_rr,(FW d, FR s))
+
+	MIDFUNC(2,fsin_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fsin_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fsin_rr,(FW d, FR s))
+
+	MIDFUNC(2,fcos_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fcos_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fcos_rr,(FW d, FR s))
+
+	MIDFUNC(2,ftan_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_ftan_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,ftan_rr,(FW d, FR s))
+
+	MIDFUNC(3,fsincos_rr,(FW d, FW c, FR s))
+{
+	s=f_readreg(s);  /* s for source */
+	d=f_writereg(d); /* d for sine   */
+	c=f_writereg(c); /* c for cosine */
+	raw_fsincos_rr(d,c,s);
+	f_unlock(s);
+	f_unlock(d);
+	f_unlock(c);
+}
+MENDFUNC(3,fsincos_rr,(FW d, FW c, FR s))
+
+	MIDFUNC(2,fscale_rr,(FRW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_rmw(d);
+	raw_fscale_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fscale_rr,(FRW d, FR s))
+
+	MIDFUNC(2,ftwotox_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_ftwotox_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,ftwotox_rr,(FW d, FR s))
+
+	MIDFUNC(2,fetox_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fetox_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fetox_rr,(FW d, FR s))
+
+	MIDFUNC(2,fetoxM1_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fetoxM1_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fetoxM1_rr,(FW d, FR s))
+
+	MIDFUNC(2,ftentox_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_ftentox_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,ftentox_rr,(FW d, FR s))
+
+	MIDFUNC(2,flog2_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_flog2_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,flog2_rr,(FW d, FR s))
+
+	MIDFUNC(2,flogN_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_flogN_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,flogN_rr,(FW d, FR s))
+
+	MIDFUNC(2,flogNP1_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_flogNP1_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,flogNP1_rr,(FW d, FR s))
+
+	MIDFUNC(2,flog10_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_flog10_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,flog10_rr,(FW d, FR s))
+
+	MIDFUNC(2,fasin_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fasin_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fasin_rr,(FW d, FR s))
+
+	MIDFUNC(2,facos_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_facos_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,facos_rr,(FW d, FR s))
+
+	MIDFUNC(2,fatan_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fatan_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fatan_rr,(FW d, FR s))
+
+	MIDFUNC(2,fatanh_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fatanh_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fatanh_rr,(FW d, FR s))
+
+	MIDFUNC(2,fsinh_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fsinh_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fsinh_rr,(FW d, FR s))
+
+	MIDFUNC(2,fcosh_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fcosh_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fcosh_rr,(FW d, FR s))
+
+	MIDFUNC(2,ftanh_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_ftanh_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,ftanh_rr,(FW d, FR s))
+
+	MIDFUNC(2,fneg_rr,(FW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_writereg(d);
+	raw_fneg_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fneg_rr,(FW d, FR s))
+
+	MIDFUNC(2,fadd_rr,(FRW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_rmw(d);
+	raw_fadd_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fadd_rr,(FRW d, FR s))
+
+	MIDFUNC(2,fsub_rr,(FRW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_rmw(d);
+	raw_fsub_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fsub_rr,(FRW d, FR s))
+
+	MIDFUNC(2,fcmp_rr,(FR d, FR s))
+{
+	d=f_readreg(d);
+	s=f_readreg(s);
+	raw_fcmp_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fcmp_rr,(FR d, FR s))
+
+	MIDFUNC(2,fdiv_rr,(FRW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_rmw(d);
+	raw_fdiv_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fdiv_rr,(FRW d, FR s))
+
+	MIDFUNC(2,frem_rr,(FRW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_rmw(d);
+	raw_frem_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,frem_rr,(FRW d, FR s))
+
+	MIDFUNC(2,frem1_rr,(FRW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_rmw(d);
+	raw_frem1_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,frem1_rr,(FRW d, FR s))
+
+	MIDFUNC(2,fmul_rr,(FRW d, FR s))
+{
+	s=f_readreg(s);
+	d=f_rmw(d);
+	raw_fmul_rr(d,s);
+	f_unlock(s);
+	f_unlock(d);
+}
+MENDFUNC(2,fmul_rr,(FRW d, FR s))
+
+	/********************************************************************
+	* Support functions exposed to gencomp. CREATE time                *
+	********************************************************************/
+
+	int kill_rodent(int r)
+{
+	return KILLTHERAT &&
+		have_rat_stall &&
+		(live.state[r].status==INMEM ||
+		live.state[r].status==CLEAN ||
+		live.state[r].status==ISCONST ||
+		live.state[r].dirtysize==4);
+}
+
+uae_u32 get_const(int r)
+{
+#if USE_OPTIMIZER
+	if (!reg_alloc_run)
+#endif
+		Dif (!isconst(r)) {
+			jit_abort (_T("JIT: Register %d should be constant, but isn't\n"),r);
+	}
+	return live.state[r].val;
+}
+
+void sync_m68k_pc(void)
+{
+	if (m68k_pc_offset) {
+		add_l_ri(PC_P,m68k_pc_offset);
+		comp_pc_p+=m68k_pc_offset;
+		m68k_pc_offset=0;
+	}
+}
+
+/********************************************************************
+* Support functions exposed to newcpu                              *
+********************************************************************/
+
+uae_u32 scratch[VREGS];
+fptype fscratch[VFREGS];
+
+void init_comp(void)
+{
+	int i;
+	uae_u8* cb=can_byte;
+	uae_u8* cw=can_word;
+	uae_u8* au=always_used;
+
+	for (i=0;i1)
+		jit_abort (_T("vinton"));
+	if (live.nat[n].nholds && depthnat[i].validsize)
+			vton[s->nat[i].holds]=i;
+
+	flush_flags(); /* low level */
+	sync_m68k_pc(); /* mid level */
+
+	/* We don't do FREGS yet, so this is raw flush() code */
+	for (i=0;is->nat[vton[i]].dirtysize)
+				tomem(i);
+			/* Fall-through! */
+		case CLEAN:
+			if (vton[i]==-1 ||
+				live.state[i].validsizenat[vton[i]].validsize)
+				evict(i);
+			else
+				make_exclusive(i,0,-1);
+			break;
+		case INMEM:
+			break;
+		case UNDEF:
+			break;
+		default:
+			write_log (_T("JIT: Weird status: %d\n"),live.state[i].status);
+			abort();
+		}
+	}
+
+	/* Quick consistency check */
+	for (i=0;is->nat[n].dirtysize)
+				abort;
+			if (live.state[i].validsizenat[n].validsize)
+				abort;
+			live.state[i].dirtysize=s->nat[n].dirtysize;
+			live.state[i].validsize=s->nat[n].validsize;
+			if (live.state[i].dirtysize)
+				set_status(i,DIRTY);
+			break;
+		case UNDEF:
+			break;
+		}
+		if (n!=-1)
+			live.nat[n].touched=touchcnt++;
+	}
+}
+#else
+STATIC_INLINE void match_states(smallstate* s)
+{
+	flush(1);
+}
+#endif
+
+/* Only do this if you really mean it! The next call should be to init!*/
+void flush(int save_regs)
+{
+	int i;
+
+	log_flush();
+	flush_flags(); /* low level */
+	sync_m68k_pc(); /* mid level */
+
+	if (save_regs) {
+		for (i=0;i=(uae_u32)kickmem_bank.baseaddr &&
+		addr<(uae_u32)kickmem_bank.baseaddr+8*65536);
+}
+
+static void flush_all(void)
+{
+	int i;
+
+	log_flush();
+	for (i=0;i0)
+			free_nreg(i);
+
+	for (i=0;i0)
+			f_free_nreg(i);
+
+	live.flags_in_flags=TRASH;  /* Note: We assume we already rescued the
+								flags at the very start of the call_r
+								functions! */
+}
+
+
+/********************************************************************
+* Memory access and related functions, CREATE time                 *
+********************************************************************/
+
+void register_branch(uae_u32 not_taken, uae_u32 taken, uae_u8 cond)
+{
+	next_pc_p=not_taken;
+	taken_pc_p=taken;
+	branch_cc=cond;
+}
+
+static uae_u32 get_handler_address(uae_u32 addr)
+{
+	uae_u32 cl=cacheline(addr);
+	blockinfo* bi=get_blockinfo_addr_new((void*)addr,0);
+
+#if USE_OPTIMIZER
+	if (!bi && reg_alloc_run)
+		return 0;
+#endif
+	return (uae_u32)&(bi->direct_handler_to_use);
+}
+
+static uae_u32 get_handler(uae_u32 addr)
+{
+	uae_u32 cl=cacheline(addr);
+	blockinfo* bi=get_blockinfo_addr_new((void*)addr,0);
+
+#if USE_OPTIMIZER
+	if (!bi && reg_alloc_run)
+		return 0;
+#endif
+	return (uae_u32)bi->direct_handler_to_use;
+}
+
+static void load_handler(int reg, uae_u32 addr)
+{
+	mov_l_rm(reg,get_handler_address(addr));
+}
+
+/* This version assumes that it is writing *real* memory, and *will* fail
+*  if that assumption is wrong! No branches, no second chances, just
+*  straight go-for-it attitude */
+
+static void writemem_real(int address, int source, int offset, int size, int tmp, int clobber)
+{
+	int f=tmp;
+
+#ifdef NATMEM_OFFSET
+	if (canbang) {  /* Woohoo! go directly at the memory! */
+		if (clobber)
+			f=source;
+		switch(size) {
+		case 1: mov_b_bRr(address,source,NATMEM_OFFSETX); break;
+		case 2: mov_w_rr(f,source); gen_bswap_16(f); mov_w_bRr(address,f,NATMEM_OFFSETX); break;
+		case 4: mov_l_rr(f,source); gen_bswap_32(f); mov_l_bRr(address,f,NATMEM_OFFSETX); break;
+		}
+		forget_about(tmp);
+		forget_about(f);
+		return;
+	}
+#endif
+
+	mov_l_rr(f,address);
+	shrl_l_ri(f,16);  /* The index into the baseaddr table */
+	mov_l_rm_indexed(f,(uae_u32)(baseaddr),f);
+
+	if (address==source) { /* IBrowse does this! */
+		if (size > 1) {
+			add_l(f,address); /* f now holds the final address */
+			switch (size) {
+			case 2: gen_bswap_16(source); mov_w_Rr(f,source,0);
+				gen_bswap_16(source); return;
+			case 4: gen_bswap_32(source); mov_l_Rr(f,source,0);
+				gen_bswap_32(source); return;
+			}
+		}
+	}
+	switch (size) { /* f now holds the offset */
+	case 1: mov_b_mrr_indexed(address,f,source); break;
+	case 2: gen_bswap_16(source); mov_w_mrr_indexed(address,f,source);
+		gen_bswap_16(source); break;	   /* base, index, source */
+	case 4: gen_bswap_32(source); mov_l_mrr_indexed(address,f,source);
+		gen_bswap_32(source); break;
+	}
+}
+
+STATIC_INLINE void writemem(int address, int source, int offset, int size, int tmp)
+{
+	int f=tmp;
+
+	mov_l_rr(f,address);
+	shrl_l_ri(f,16);   /* The index into the mem bank table */
+	mov_l_rm_indexed(f,(uae_u32)mem_banks,f);
+	/* Now f holds a pointer to the actual membank */
+	mov_l_rR(f,f,offset);
+	/* Now f holds the address of the b/w/lput function */
+	call_r_02(f,address,source,4,size);
+	forget_about(tmp);
+}
+
+void writebyte(int address, int source, int tmp)
+{
+	int distrust = currprefs.comptrustbyte;
+#if 0
+	switch (currprefs.comptrustbyte) {
+	case 0: distrust=0; break;
+	case 1: distrust=1; break;
+	case 2: distrust=((start_pc&0xF80000)==0xF80000); break;
+	case 3: distrust=!have_done_picasso; break;
+	default: abort();
+	}
+#endif
+	if ((special_mem&S_WRITE) || distrust)
+		writemem_special(address,source,20,1,tmp);
+	else
+		writemem_real(address,source,20,1,tmp,0);
+}
+
+STATIC_INLINE void writeword_general(int address, int source, int tmp,
+	int clobber)
+{
+	int distrust = currprefs.comptrustword;
+#if 0
+	switch (currprefs.comptrustword) {
+	case 0: distrust=0; break;
+	case 1: distrust=1; break;
+	case 2: distrust=((start_pc&0xF80000)==0xF80000); break;
+	case 3: distrust=!have_done_picasso; break;
+	default: abort();
+	}
+#endif
+	if ((special_mem&S_WRITE) || distrust)
+		writemem_special(address,source,16,2,tmp);
+	else
+		writemem_real(address,source,16,2,tmp,clobber);
+}
+
+void writeword_clobber(int address, int source, int tmp)
+{
+	writeword_general(address,source,tmp,1);
+}
+
+void writeword(int address, int source, int tmp)
+{
+	writeword_general(address,source,tmp,0);
+}
+
+STATIC_INLINE void writelong_general(int address, int source, int tmp,
+	int clobber)
+{
+	int  distrust = currprefs.comptrustlong;
+#if 0
+	switch (currprefs.comptrustlong) {
+	case 0: distrust=0; break;
+	case 1: distrust=1; break;
+	case 2: distrust=((start_pc&0xF80000)==0xF80000); break;
+	case 3: distrust=!have_done_picasso; break;
+	default: abort();
+	}
+#endif
+	if ((special_mem&S_WRITE) || distrust)
+		writemem_special(address,source,12,4,tmp);
+	else
+		writemem_real(address,source,12,4,tmp,clobber);
+}
+
+void writelong_clobber(int address, int source, int tmp)
+{
+	writelong_general(address,source,tmp,1);
+}
+
+void writelong(int address, int source, int tmp)
+{
+	writelong_general(address,source,tmp,0);
+}
+
+
+
+/* This version assumes that it is reading *real* memory, and *will* fail
+*  if that assumption is wrong! No branches, no second chances, just
+*  straight go-for-it attitude */
+
+static void readmem_real(int address, int dest, int offset, int size, int tmp)
+{
+	int f=tmp;
+
+	if (size==4 && address!=dest)
+		f=dest;
+
+#ifdef NATMEM_OFFSET
+	if (canbang) {  /* Woohoo! go directly at the memory! */
+		switch(size) {
+		case 1: mov_b_brR(dest,address,NATMEM_OFFSETX); break;
+		case 2: mov_w_brR(dest,address,NATMEM_OFFSETX); gen_bswap_16(dest); break;
+		case 4: mov_l_brR(dest,address,NATMEM_OFFSETX); gen_bswap_32(dest); break;
+		}
+		forget_about(tmp);
+		return;
+	}
+#endif
+
+	mov_l_rr(f,address);
+	shrl_l_ri(f,16);   /* The index into the baseaddr table */
+	mov_l_rm_indexed(f,(uae_u32)baseaddr,f);
+	/* f now holds the offset */
+
+	switch(size) {
+	case 1: mov_b_rrm_indexed(dest,address,f); break;
+	case 2: mov_w_rrm_indexed(dest,address,f); gen_bswap_16(dest); break;
+	case 4: mov_l_rrm_indexed(dest,address,f); gen_bswap_32(dest); break;
+	}
+	forget_about(tmp);
+}
+
+
+
+STATIC_INLINE void readmem(int address, int dest, int offset, int size, int tmp)
+{
+	int f=tmp;
+
+	mov_l_rr(f,address);
+	shrl_l_ri(f,16);   /* The index into the mem bank table */
+	mov_l_rm_indexed(f,(uae_u32)mem_banks,f);
+	/* Now f holds a pointer to the actual membank */
+	mov_l_rR(f,f,offset);
+	/* Now f holds the address of the b/w/lget function */
+	call_r_11(dest,f,address,size,4);
+	forget_about(tmp);
+}
+
+void readbyte(int address, int dest, int tmp)
+{
+	int distrust = currprefs.comptrustbyte;
+#if 0
+	switch (currprefs.comptrustbyte) {
+	case 0: distrust=0; break;
+	case 1: distrust=1; break;
+	case 2: distrust=((start_pc&0xF80000)==0xF80000); break;
+	case 3: distrust=!have_done_picasso; break;
+	default: abort();
+	}
+#endif
+	if ((special_mem&S_READ) || distrust)
+		readmem_special(address,dest,8,1,tmp);
+	else
+		readmem_real(address,dest,8,1,tmp);
+}
+
+void readword(int address, int dest, int tmp)
+{
+	int distrust = currprefs.comptrustword;
+#if 0
+	switch (currprefs.comptrustword) {
+	case 0: distrust=0; break;
+	case 1: distrust=1; break;
+	case 2: distrust=((start_pc&0xF80000)==0xF80000); break;
+	case 3: distrust=!have_done_picasso; break;
+	default: abort();
+	}
+#endif
+	if ((special_mem&S_READ) || distrust)
+		readmem_special(address,dest,4,2,tmp);
+	else
+		readmem_real(address,dest,4,2,tmp);
+}
+
+void readlong(int address, int dest, int tmp)
+{
+	int distrust = currprefs.comptrustlong;
+#if 0
+	switch (currprefs.comptrustlong) {
+	case 0: distrust=0; break;
+	case 1: distrust=1; break;
+	case 2: distrust=((start_pc&0xF80000)==0xF80000); break;
+	case 3: distrust=!have_done_picasso; break;
+	default: abort();
+	}
+#endif
+	if ((special_mem&S_READ) || distrust)
+		readmem_special(address,dest,0,4,tmp);
+	else
+		readmem_real(address,dest,0,4,tmp);
+}
+
+
+
+/* This one might appear a bit odd... */
+STATIC_INLINE void get_n_addr_old(int address, int dest, int tmp)
+{
+	readmem(address,dest,24,4,tmp);
+}
+
+STATIC_INLINE void get_n_addr_real(int address, int dest, int tmp)
+{
+	int f=tmp;
+	if (address!=dest)
+		f=dest;
+
+#ifdef NATMEM_OFFSET
+	if (canbang) {
+		lea_l_brr(dest,address,NATMEM_OFFSETX);
+		forget_about(tmp);
+		return;
+	}
+#endif
+	mov_l_rr(f,address);
+	mov_l_rr(dest,address); // gb-- nop if dest==address
+	shrl_l_ri(f,16);
+	mov_l_rm_indexed(f,(uae_u32)baseaddr,f);
+	add_l(dest,f);
+	forget_about(tmp);
+}
+
+void get_n_addr(int address, int dest, int tmp)
+{
+	int distrust = currprefs.comptrustnaddr;
+#if 0
+	switch (currprefs.comptrustnaddr) {
+	case 0: distrust=0; break;
+	case 1: distrust=1; break;
+	case 2: distrust=((start_pc&0xF80000)==0xF80000); break;
+	case 3: distrust=!have_done_picasso; break;
+	default: abort();
+	}
+#endif
+	if (special_mem || distrust)
+		get_n_addr_old(address,dest,tmp);
+	else
+		get_n_addr_real(address,dest,tmp);
+}
+
+void get_n_addr_jmp(int address, int dest, int tmp)
+{
+#if 0 /* For this, we need to get the same address as the rest of UAE
+would --- otherwise we end up translating everything twice */
+	get_n_addr(address,dest,tmp);
+#else
+	int f=tmp;
+	if (address!=dest)
+		f=dest;
+	mov_l_rr(f,address);
+	shrl_l_ri(f,16);   /* The index into the baseaddr bank table */
+	mov_l_rm_indexed(dest,(uae_u32)baseaddr,f);
+	add_l(dest,address);
+	and_l_ri (dest, ~1);
+	forget_about(tmp);
+#endif
+}
+
+/* base, target and tmp are registers, but dp is the actual opcode extension word */
+void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp)
+{
+	int reg = (dp >> 12) & 15;
+	int regd_shift=(dp >> 9) & 3;
+
+	if (dp & 0x100) {
+		int ignorebase=(dp&0x80);
+		int ignorereg=(dp&0x40);
+		int addbase=0;
+		int outer=0;
+
+		if ((dp & 0x30) == 0x20) addbase = (uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2);
+		if ((dp & 0x30) == 0x30) addbase = comp_get_ilong((m68k_pc_offset+=4)-4);
+
+		if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2);
+		if ((dp & 0x3) == 0x3) outer = comp_get_ilong((m68k_pc_offset+=4)-4);
+
+		if ((dp & 0x4) == 0) {  /* add regd *before* the get_long */
+			if (!ignorereg) {
+				if ((dp & 0x800) == 0)
+					sign_extend_16_rr(target,reg);
+				else
+					mov_l_rr(target,reg);
+				shll_l_ri(target,regd_shift);
+			}
+			else
+				mov_l_ri(target,0);
+
+			/* target is now regd */
+			if (!ignorebase)
+				add_l(target,base);
+			add_l_ri(target,addbase);
+			if (dp&0x03) readlong(target,target,tmp);
+		} else { /* do the getlong first, then add regd */
+			if (!ignorebase) {
+				mov_l_rr(target,base);
+				add_l_ri(target,addbase);
+			}
+			else
+				mov_l_ri(target,addbase);
+			if (dp&0x03) readlong(target,target,tmp);
+
+			if (!ignorereg) {
+				if ((dp & 0x800) == 0)
+					sign_extend_16_rr(tmp,reg);
+				else
+					mov_l_rr(tmp,reg);
+				shll_l_ri(tmp,regd_shift);
+				/* tmp is now regd */
+				add_l(target,tmp);
+			}
+		}
+		add_l_ri(target,outer);
+	}
+	else { /* 68000 version */
+		if ((dp & 0x800) == 0) { /* Sign extend */
+			sign_extend_16_rr(target,reg);
+			lea_l_brr_indexed(target,base,target,regd_shift,(uae_s32)(uae_s8)dp);
+		}
+		else {
+			lea_l_brr_indexed(target,base,reg,regd_shift,(uae_s32)(uae_s8)dp);
+		}
+	}
+	forget_about(tmp);
+}
+
+STATIC_INLINE unsigned int cft_map (unsigned int f)
+{
+	return ((f >> 8) & 255) | ((f & 255) << 8);
+}
+
+void set_cache_state(int enabled)
+{
+	if (enabled!=letit)
+		flush_icache_hard(0, 3);
+	letit=enabled;
+}
+
+int get_cache_state(void)
+{
+	return letit;
+}
+
+uae_u32 get_jitted_size(void)
+{
+	if (compiled_code)
+		return current_compile_p-compiled_code;
+	return 0;
+}
+
+void alloc_cache(void)
+{
+	if (compiled_code) {
+		flush_icache_hard(0, 3);
+		cache_free(compiled_code);
+	}
+	if (veccode == NULL)
+		veccode = cache_alloc (256);
+	if (popallspace == NULL)
+		popallspace = cache_alloc (1024);
+	compiled_code = NULL;
+	if (currprefs.cachesize == 0)
+		return;
+
+	while (!compiled_code && currprefs.cachesize) {
+		compiled_code=cache_alloc(currprefs.cachesize*1024);
+		if (!compiled_code)
+			currprefs.cachesize/=2;
+	}
+	if (compiled_code) {
+		max_compile_start=compiled_code+currprefs.cachesize*1024-BYTES_PER_INST;
+		current_compile_p=compiled_code;
+	}
+}
+
+static void calc_checksum(blockinfo* bi, uae_u32* c1, uae_u32* c2)
+{
+	uae_u32 k1=0;
+	uae_u32 k2=0;
+	uae_s32 len=bi->len;
+	uae_u32 tmp=bi->min_pcp;
+	uae_u32* pos;
+
+	len+=(tmp&3);
+	tmp&=(~3);
+	pos=(uae_u32*)tmp;
+
+	if (len<0 || len>MAX_CHECKSUM_LEN) {
+		*c1=0;
+		*c2=0;
+	}
+	else {
+		while (len>0) {
+			k1+=*pos;
+			k2^=*pos;
+			pos++;
+			len-=4;
+		}
+		*c1=k1;
+		*c2=k2;
+	}
+}
+
+static void show_checksum(blockinfo* bi)
+{
+	uae_u32 k1=0;
+	uae_u32 k2=0;
+	uae_s32 len=bi->len;
+	uae_u32 tmp=(uae_u32)bi->pc_p;
+	uae_u32* pos;
+
+	len+=(tmp&3);
+	tmp&=(~3);
+	pos=(uae_u32*)tmp;
+
+	if (len<0 || len>MAX_CHECKSUM_LEN) {
+		return;
+	}
+	else {
+		while (len>0) {
+			write_log (_T("%08x "),*pos);
+			pos++;
+			len-=4;
+		}
+		write_log (_T(" bla\n"));
+	}
+}
+
+
+int check_for_cache_miss(void)
+{
+	blockinfo* bi=get_blockinfo_addr(regs.pc_p);
+
+	if (bi) {
+		int cl=cacheline(regs.pc_p);
+		if (bi!=cache_tags[cl+1].bi) {
+			raise_in_cl_list(bi);
+			return 1;
+		}
+	}
+	return 0;
+}
+
+
+static void recompile_block(void)
+{
+	/* An existing block's countdown code has expired. We need to make
+	sure that execute_normal doesn't refuse to recompile due to a
+	perceived cache miss... */
+	blockinfo*  bi=get_blockinfo_addr(regs.pc_p);
+
+	Dif (!bi)
+		jit_abort (_T("recompile_block"));
+	raise_in_cl_list(bi);
+	execute_normal();
+	return;
+}
+
+static void cache_miss(void)
+{
+	blockinfo*  bi=get_blockinfo_addr(regs.pc_p);
+	uae_u32     cl=cacheline(regs.pc_p);
+	blockinfo*  bi2=get_blockinfo(cl);
+
+	if (!bi) {
+		execute_normal(); /* Compile this block now */
+		return;
+	}
+	Dif (!bi2 || bi==bi2) {
+		jit_abort (_T("Unexplained cache miss %p %p\n"),bi,bi2);
+	}
+	raise_in_cl_list(bi);
+	return;
+}
+
+static void check_checksum(void)
+{
+	blockinfo*  bi=get_blockinfo_addr(regs.pc_p);
+	uae_u32     cl=cacheline(regs.pc_p);
+	blockinfo*  bi2=get_blockinfo(cl);
+
+	uae_u32     c1,c2;
+
+	checksum_count++;
+	/* These are not the droids you are looking for...  */
+	if (!bi) {
+		/* Whoever is the primary target is in a dormant state, but
+		calling it was accidental, and we should just compile this
+		new block */
+		execute_normal();
+		return;
+	}
+	if (bi!=bi2) {
+		/* The block was hit accidentally, but it does exist. Cache miss */
+		cache_miss();
+		return;
+	}
+
+	if (bi->c1 || bi->c2)
+		calc_checksum(bi,&c1,&c2);
+	else {
+		c1=c2=1;  /* Make sure it doesn't match */
+	}
+	if (c1==bi->c1 && c2==bi->c2) {
+		/* This block is still OK. So we reactivate. Of course, that
+		means we have to move it into the needs-to-be-flushed list */
+		bi->handler_to_use=bi->handler;
+		set_dhtu(bi,bi->direct_handler);
+
+		/*	write_log (_T("JIT: reactivate %p/%p (%x %x/%x %x)\n"),bi,bi->pc_p,
+		c1,c2,bi->c1,bi->c2);*/
+		remove_from_list(bi);
+		add_to_active(bi);
+		raise_in_cl_list(bi);
+	}
+	else {
+		/* This block actually changed. We need to invalidate it,
+		and set it up to be recompiled */
+		/* write_log (_T("JIT: discard %p/%p (%x %x/%x %x)\n"),bi,bi->pc_p,
+		c1,c2,bi->c1,bi->c2); */
+		invalidate_block(bi);
+		raise_in_cl_list(bi);
+		execute_normal();
+	}
+}
+
+
+STATIC_INLINE void create_popalls(void)
+{
+	int i,r;
+
+	current_compile_p=popallspace;
+	set_target(current_compile_p);
+#if USE_PUSH_POP
+	/* If we can't use gcc inline assembly, we need to pop some
+	registers before jumping back to the various get-out routines.
+	This generates the code for it.
+	*/
+	popall_do_nothing=current_compile_p;
+	for (i=0;idirect_pen=(cpuop_func*)get_target();
+	raw_mov_l_rm(0,(uae_u32)&(bi->pc_p));
+	raw_mov_l_mr((uae_u32)®s.pc_p,0);
+	raw_jmp((uae_u32)popall_execute_normal);
+
+	align_target(32);
+	bi->direct_pcc=(cpuop_func*)get_target();
+	raw_mov_l_rm(0,(uae_u32)&(bi->pc_p));
+	raw_mov_l_mr((uae_u32)®s.pc_p,0);
+	raw_jmp((uae_u32)popall_check_checksum);
+
+	align_target(32);
+	current_compile_p=get_target();
+
+	bi->deplist=NULL;
+	for (i=0;i<2;i++) {
+		bi->dep[i].prev_p=NULL;
+		bi->dep[i].next=NULL;
+	}
+	bi->env=default_ss;
+	bi->status=BI_NEW;
+	bi->havestate=0;
+	//bi->env=empty_ss;
+}
+
+void compemu_reset(void)
+{
+	set_cache_state(0);
+}
+
+void build_comp(void)
+{
+	int i;
+	int jumpcount=0;
+	unsigned long opcode;
+	const struct comptbl* tbl=op_smalltbl_0_comp_ff;
+	const struct comptbl* nftbl=op_smalltbl_0_comp_nf;
+	int count;
+#ifdef NOFLAGS_SUPPORT
+	struct comptbl *nfctbl = (currprefs.cpu_level >= 5 ? op_smalltbl_0_nf
+		: currprefs.cpu_level == 4 ? op_smalltbl_1_nf
+		: (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) ? op_smalltbl_2_nf
+		: currprefs.cpu_level == 1 ? op_smalltbl_3_nf
+		: ! currprefs.cpu_compatible ? op_smalltbl_4_nf
+		: op_smalltbl_5_nf);
+#endif
+	raw_init_cpu();
+#ifdef NATMEM_OFFSET
+	write_log (_T("JIT: Setting signal handler\n"));
+#ifndef _WIN32
+	signal(SIGSEGV,vec);
+#endif
+#endif
+	write_log (_T("JIT: Building Compiler function table\n"));
+	for (opcode = 0; opcode < 65536; opcode++) {
+#ifdef NOFLAGS_SUPPORT
+		nfcpufunctbl[opcode] = op_illg;
+#endif
+		compfunctbl[opcode] = NULL;
+		nfcompfunctbl[opcode] = NULL;
+		prop[opcode].use_flags = 0x1f;
+		prop[opcode].set_flags = 0x1f;
+		prop[opcode].is_jump=1;
+	}
+
+	for (i = 0; tbl[i].opcode < 65536; i++) {
+		int isjmp=(tbl[i].specific&1);
+		int isaddx=(tbl[i].specific&8);
+		int iscjmp=(tbl[i].specific&16);
+
+		prop[tbl[i].opcode].is_jump=isjmp;
+		prop[tbl[i].opcode].is_const_jump=iscjmp;
+		prop[tbl[i].opcode].is_addx=isaddx;
+		compfunctbl[tbl[i].opcode] = tbl[i].handler;
+	}
+	for (i = 0; nftbl[i].opcode < 65536; i++) {
+		nfcompfunctbl[nftbl[i].opcode] = nftbl[i].handler;
+#ifdef NOFLAGS_SUPPORT
+		nfcpufunctbl[nftbl[i].opcode] = nfctbl[i].handler;
+#endif
+	}
+
+#ifdef NOFLAGS_SUPPORT
+	for (i = 0; nfctbl[i].handler; i++) {
+		nfcpufunctbl[nfctbl[i].opcode] = nfctbl[i].handler;
+	}
+#endif
+
+	for (opcode = 0; opcode < 65536; opcode++) {
+		compop_func *f;
+		compop_func *nff;
+#ifdef NOFLAGS_SUPPORT
+		compop_func *nfcf;
+#endif
+		int isjmp,isaddx,iscjmp;
+		int lvl;
+
+		lvl = (currprefs.cpu_model - 68000) / 10;
+		if (lvl > 4)
+			lvl--;
+		if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > lvl)
+			continue;
+
+		if (table68k[opcode].handler != -1) {
+			f = compfunctbl[table68k[opcode].handler];
+			nff = nfcompfunctbl[table68k[opcode].handler];
+#ifdef NOFLAGS_SUPPORT
+			nfcf = nfcpufunctbl[table68k[opcode].handler];
+#endif
+			isjmp=prop[table68k[opcode].handler].is_jump;
+			iscjmp=prop[table68k[opcode].handler].is_const_jump;
+			isaddx=prop[table68k[opcode].handler].is_addx;
+			prop[opcode].is_jump=isjmp;
+			prop[opcode].is_const_jump=iscjmp;
+			prop[opcode].is_addx=isaddx;
+			compfunctbl[opcode] = f;
+			nfcompfunctbl[opcode] = nff;
+#ifdef NOFLAGS_SUPPORT
+			Dif (nfcf == op_illg)
+				abort();
+			nfcpufunctbl[opcode] = nfcf;
+#endif
+		}
+		prop[opcode].set_flags =table68k[opcode].flagdead;
+		prop[opcode].use_flags =table68k[opcode].flaglive;
+		/* Unconditional jumps don't evaluate condition codes, so they
+		don't actually use any flags themselves */
+		if (prop[opcode].is_const_jump)
+			prop[opcode].use_flags=0;
+	}
+#ifdef NOFLAGS_SUPPORT
+	for (i = 0; nfctbl[i].handler != NULL; i++) {
+		if (nfctbl[i].specific)
+			nfcpufunctbl[tbl[i].opcode] = nfctbl[i].handler;
+	}
+#endif
+
+	count=0;
+	for (opcode = 0; opcode < 65536; opcode++) {
+		if (compfunctbl[opcode])
+			count++;
+	}
+	write_log (_T("JIT: Supposedly %d compileable opcodes!\n"),count);
+
+	/* Initialise state */
+	alloc_cache();
+	create_popalls();
+	reset_lists();
+
+	for (i=0;ipc_p)].handler=(cpuop_func*)popall_execute_normal;
+		cache_tags[cacheline(bi->pc_p)+1].bi=NULL;
+		bi=bi->next;
+	}
+	bi=dormant;
+	while(bi) {
+		cache_tags[cacheline(bi->pc_p)].handler=(cpuop_func*)popall_execute_normal;
+		cache_tags[cacheline(bi->pc_p)+1].bi=NULL;
+		bi=bi->next;
+	}
+
+	reset_lists();
+	if (!compiled_code)
+		return;
+	current_compile_p=compiled_code;
+	set_special(0); /* To get out of compiled code */
+}
+
+
+/* "Soft flushing" --- instead of actually throwing everything away,
+we simply mark everything as "needs to be checked".
+*/
+
+void flush_icache(uaecptr ptr, int n)
+{
+	blockinfo* bi;
+	blockinfo* bi2;
+
+	if (currprefs.comp_hardflush) {
+		flush_icache_hard(ptr, n);
+		return;
+	}
+	soft_flush_count++;
+	if (!active)
+		return;
+
+	bi=active;
+	while (bi) {
+		uae_u32 cl=cacheline(bi->pc_p);
+		if (!bi->handler) {
+			/* invalidated block */
+			if (bi==cache_tags[cl+1].bi)
+				cache_tags[cl].handler=(cpuop_func*)popall_execute_normal;
+			bi->handler_to_use=(cpuop_func*)popall_execute_normal;
+			set_dhtu(bi,bi->direct_pen);
+		} else {
+			if (bi==cache_tags[cl+1].bi)
+				cache_tags[cl].handler=(cpuop_func*)popall_check_checksum;
+			bi->handler_to_use=(cpuop_func*)popall_check_checksum;
+			set_dhtu(bi,bi->direct_pcc);
+		}
+		bi2=bi;
+		bi=bi->next;
+	}
+	/* bi2 is now the last entry in the active list */
+	bi2->next=dormant;
+	if (dormant)
+		dormant->prev_p=&(bi2->next);
+
+	dormant=active;
+	active->prev_p=&dormant;
+	active=NULL;
+}
+
+
+static void catastrophe(void)
+{
+	jit_abort (_T("catastprophe"));
+}
+
+int failure;
+
+
+void compile_block(cpu_history* pc_hist, int blocklen, int totcycles)
+{
+	if (letit && compiled_code && currprefs.cpu_model>=68020) {
+
+		/* OK, here we need to 'compile' a block */
+		int i;
+		int r;
+		int was_comp=0;
+		uae_u8 liveflags[MAXRUN+1];
+		uae_u32 max_pcp=(uae_u32)pc_hist[0].location;
+		uae_u32 min_pcp=max_pcp;
+		uae_u32 cl=cacheline(pc_hist[0].location);
+		void* specflags=(void*)®s.spcflags;
+		blockinfo* bi=NULL;
+		blockinfo* bi2;
+		int extra_len=0;
+
+		compile_count++;
+		if (current_compile_p>=max_compile_start)
+			flush_icache_hard(0, 3);
+
+		alloc_blockinfos();
+
+		bi=get_blockinfo_addr_new(pc_hist[0].location,0);
+		bi2=get_blockinfo(cl);
+
+		optlev=bi->optlevel;
+		if (bi->handler) {
+			Dif (bi!=bi2) {
+				/* I don't think it can happen anymore. Shouldn't, in
+				any case. So let's make sure... */
+				jit_abort (_T("JIT: WOOOWOO count=%d, ol=%d %p %p\n"),
+					bi->count,bi->optlevel,bi->handler_to_use,
+					cache_tags[cl].handler);
+			}
+
+			Dif (bi->count!=-1 && bi->status!=BI_TARGETTED) {
+				/* What the heck? We are not supposed to be here! */
+				jit_abort (_T("BI_TARGETTED"));
+			}
+		}
+		if (bi->count==-1) {
+			optlev++;
+			while (!currprefs.optcount[optlev])
+				optlev++;
+			bi->count=currprefs.optcount[optlev]-1;
+		}
+		current_block_pc_p=(uae_u32)pc_hist[0].location;
+
+		remove_deps(bi); /* We are about to create new code */
+		bi->optlevel=optlev;
+		bi->pc_p=(uae_u8*)pc_hist[0].location;
+
+		liveflags[blocklen]=0x1f; /* All flags needed afterwards */
+		i=blocklen;
+		while (i--) {
+			uae_u16* currpcp=pc_hist[i].location;
+			int op=cft_map(*currpcp);
+
+			if ((uae_u32)currpcpmax_pcp)
+				max_pcp=(uae_u32)currpcp;
+
+			if (currprefs.compnf) {
+				liveflags[i]=((liveflags[i+1]&
+					(~prop[op].set_flags))|
+					prop[op].use_flags);
+				if (prop[op].is_addx && (liveflags[i+1]&FLAG_Z)==0)
+					liveflags[i]&= ~FLAG_Z;
+			}
+			else {
+				liveflags[i]=0x1f;
+			}
+		}
+
+		bi->needed_flags=liveflags[0];
+
+		/* This is the non-direct handler */
+		align_target(32);
+		set_target(get_target()+1);
+		align_target(16);
+		/* Now aligned at n*32+16 */
+
+		bi->handler=
+			bi->handler_to_use=(cpuop_func*)get_target();
+		raw_cmp_l_mi((uae_u32)®s.pc_p,(uae_u32)pc_hist[0].location);
+		raw_jnz((uae_u32)popall_cache_miss);
+		/* This was 16 bytes on the x86, so now aligned on (n+1)*32 */
+
+		was_comp=0;
+
+#if USE_MATCHSTATE
+		comp_pc_p=(uae_u8*)pc_hist[0].location;
+		init_comp();
+		match_states(&(bi->env));
+		was_comp=1;
+#endif
+
+		bi->direct_handler=(cpuop_func*)get_target();
+		set_dhtu(bi,bi->direct_handler);
+		current_block_start_target=(uae_u32)get_target();
+
+		if (bi->count>=0) { /* Need to generate countdown code */
+			raw_mov_l_mi((uae_u32)®s.pc_p,(uae_u32)pc_hist[0].location);
+			raw_sub_l_mi((uae_u32)&(bi->count),1);
+			raw_jl((uae_u32)popall_recompile_block);
+		}
+		if (optlev==0) { /* No need to actually translate */
+			/* Execute normally without keeping stats */
+			raw_mov_l_mi((uae_u32)®s.pc_p,(uae_u32)pc_hist[0].location);
+			raw_jmp((uae_u32)popall_exec_nostats);
+		}
+		else {
+			reg_alloc_run=0;
+			next_pc_p=0;
+			taken_pc_p=0;
+			branch_cc=0;
+
+			log_startblock();
+			for (i=0;i1) {
+						failure=0;
+						if (!was_comp) {
+							comp_pc_p=(uae_u8*)pc_hist[i].location;
+							init_comp();
+						}
+						was_comp++;
+
+						comptbl[opcode](opcode);
+						freescratch();
+						if (!(liveflags[i+1] & FLAG_CZNV)) {
+							/* We can forget about flags */
+							dont_care_flags();
+						}
+#if INDIVIDUAL_INST
+						flush(1);
+						nop();
+						flush(1);
+						was_comp=0;
+#endif
+					}
+					else
+						failure=1;
+					if (failure) {
+						if (was_comp) {
+							flush(1);
+							was_comp=0;
+						}
+						raw_mov_l_ri(REG_PAR1,(uae_u32)opcode);
+						raw_mov_l_ri(REG_PAR2,(uae_u32)®s);
+#if USE_NORMAL_CALLING_CONVENTION
+						raw_push_l_r(REG_PAR2);
+						raw_push_l_r(REG_PAR1);
+#endif
+						raw_mov_l_mi((uae_u32)®s.pc_p,
+							(uae_u32)pc_hist[i].location);
+						raw_call((uae_u32)cputbl[opcode]);
+						//raw_add_l_mi((uae_u32)&oink,1); // FIXME
+#if USE_NORMAL_CALLING_CONVENTION
+						raw_inc_sp(8);
+#endif
+						/*if (needed_flags)
+						raw_mov_l_mi((uae_u32)&foink3,(uae_u32)opcode+65536);
+						else
+						raw_mov_l_mi((uae_u32)&foink3,(uae_u32)opcode);
+						*/
+
+						if (ineeded_flags;
+
+					if (x==0xff || 1) {  /* To be on the safe side */
+						uae_u16* next=(uae_u16*)next_pc_p;
+						uae_u16 op=cft_map(*next);
+
+						x=0x1f;
+						x&=(~prop[op].set_flags);
+						x|=prop[op].use_flags;
+					}
+
+					x|=bi2->needed_flags;
+					if (!(x & FLAG_CZNV)) {
+						/* We can forget about flags */
+						dont_care_flags();
+						extra_len+=2; /* The next instruction now is part of this
+									  block */
+					}
+
+			}
+#endif
+
+			if (next_pc_p) { /* A branch was registered */
+				uae_u32 t1=next_pc_p;
+				uae_u32 t2=taken_pc_p;
+				int     cc=branch_cc;
+
+				uae_u32* branchadd;
+				uae_u32* tba;
+				bigstate tmp;
+				blockinfo* tbi;
+
+				if (taken_pc_penv));
+				//flush(1); /* Can only get here if was_comp==1 */
+				raw_sub_l_mi((uae_u32)&countdown,scaled_cycles(totcycles));
+				raw_jcc_l_oponly(9);
+				tba=(uae_u32*)get_target();
+				emit_long(get_handler(t1)-((uae_u32)tba+4));
+				raw_mov_l_mi((uae_u32)®s.pc_p,t1);
+				raw_jmp((uae_u32)popall_do_nothing);
+				create_jmpdep(bi,0,tba,t1);
+
+				align_target(16);
+				/* not-predicted outcome */
+				*branchadd=(uae_u32)get_target()-((uae_u32)branchadd+4);
+				live=tmp; /* Ouch again */
+				tbi=get_blockinfo_addr_new((void*)t2,1);
+				match_states(&(tbi->env));
+
+				//flush(1); /* Can only get here if was_comp==1 */
+				raw_sub_l_mi((uae_u32)&countdown,scaled_cycles(totcycles));
+				raw_jcc_l_oponly(9);
+				tba=(uae_u32*)get_target();
+				emit_long(get_handler(t2)-((uae_u32)tba+4));
+				raw_mov_l_mi((uae_u32)®s.pc_p,t2);
+				raw_jmp((uae_u32)popall_do_nothing);
+				create_jmpdep(bi,1,tba,t2);
+			}
+			else
+			{
+				if (was_comp) {
+					flush(1);
+				}
+
+				/* Let's find out where next_handler is... */
+				if (was_comp && isinreg(PC_P)) {
+					int r2;
+
+					r=live.state[PC_P].realreg;
+
+					if (r==0)
+						r2=1;
+					else
+						r2=0;
+
+					raw_and_l_ri(r,TAGMASK);
+					raw_mov_l_ri(r2,(uae_u32)popall_do_nothing);
+					raw_sub_l_mi((uae_u32)&countdown,scaled_cycles(totcycles));
+					raw_cmov_l_rm_indexed(r2,(uae_u32)cache_tags,r,9);
+					raw_jmp_r(r2);
+				}
+				else if (was_comp && isconst(PC_P)) {
+					uae_u32 v=live.state[PC_P].val;
+					uae_u32* tba;
+					blockinfo* tbi;
+
+					tbi=get_blockinfo_addr_new((void*)v,1);
+					match_states(&(tbi->env));
+
+					raw_sub_l_mi((uae_u32)&countdown,scaled_cycles(totcycles));
+					raw_jcc_l_oponly(9);
+					tba=(uae_u32*)get_target();
+					emit_long(get_handler(v)-((uae_u32)tba+4));
+					raw_mov_l_mi((uae_u32)®s.pc_p,v);
+					raw_jmp((uae_u32)popall_do_nothing);
+					create_jmpdep(bi,0,tba,v);
+				}
+				else {
+					int r2;
+
+					r=REG_PC_TMP;
+					raw_mov_l_rm(r,(uae_u32)®s.pc_p);
+					if (r==0)
+						r2=1;
+					else
+						r2=0;
+
+					raw_and_l_ri(r,TAGMASK);
+					raw_mov_l_ri(r2,(uae_u32)popall_do_nothing);
+					raw_sub_l_mi((uae_u32)&countdown,scaled_cycles(totcycles));
+					raw_cmov_l_rm_indexed(r2,(uae_u32)cache_tags,r,9);
+					raw_jmp_r(r2);
+				}
+			}
+		}
+
+		if (next_pc_p+extra_len>=max_pcp &&
+			next_pc_p+extra_lenlen=max_pcp-min_pcp;
+		bi->min_pcp=min_pcp;
+
+		remove_from_list(bi);
+		if (isinrom(min_pcp) && isinrom(max_pcp))
+			add_to_dormant(bi); /* No need to checksum it on cache flush.
+								Please don't start changing ROMs in
+								flight! */
+		else {
+			calc_checksum(bi,&(bi->c1),&(bi->c2));
+			add_to_active(bi);
+		}
+
+		log_dump();
+		align_target(32);
+		current_compile_p=get_target();
+
+		raise_in_cl_list(bi);
+		bi->nexthandler=current_compile_p;
+
+		/* We will flush soon, anyway, so let's do it now */
+		if (current_compile_p>=max_compile_start)
+			flush_icache_hard(0, 3);
+
+		do_extra_cycles(totcycles); /* for the compilation time */
+	}
+}
+
+#endif
diff --git a/src/cpu/jit/compemu_support_codegen.c b/src/cpu/jit/compemu_support_codegen.c
new file mode 100644
index 0000000..56cbaff
--- /dev/null
+++ b/src/cpu/jit/compemu_support_codegen.c
@@ -0,0 +1,7140 @@
+/*
+ *  compiler/compemu_support.cpp - Core dynamic translation engine
+ *
+ *  Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
+ *
+ *  Adaptation for Basilisk II and improvements, copyright 2000-2005
+ *    Gwenole Beauchesne
+ *
+ *  Basilisk II (C) 1997-2008 Christian Bauer
+ *  
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#if 0
+#if !REAL_ADDRESSING && !DIRECT_ADDRESSING
+#error "Only Real or Direct Addressing is supported with the JIT Compiler"
+#endif
+
+#if X86_ASSEMBLY && !SAHF_SETO_PROFITABLE
+#error "Only [LS]AHF scheme to [gs]et flags is supported with the JIT Compiler"
+#endif
+#endif
+
+/* NOTE: support for AMD64 assumes translation cache and other code
+ * buffers are allocated into a 32-bit address space because (i) B2/JIT
+ * code is not 64-bit clean and (ii) it's faster to resolve branches
+ * that way.
+ */
+#if 0
+#if !defined(__i386__) && !defined(__x86_64__)
+#error "Only IA-32 and X86-64 targets are supported with the JIT Compiler"
+#endif
+#endif
+
+#define USE_MATCH 0
+
+/* kludge for Brian, so he can compile under MSVC++ */
+#define USE_NORMAL_CALLING_CONVENTION 0
+
+#ifndef WIN32
+#include 
+#include 
+#include 
+#endif
+
+#include 
+#include 
+#include 
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+#if 0
+#include "cpu_emulation.h"
+#include "main.h"
+#include "prefs.h"
+#include "user_strings.h"
+#include "vm_alloc.h"
+#endif
+
+//#include "machdep/m68k.h"
+#include "custom.h"
+#include "memory.h"
+//#include "readcpu.h"
+#include "newcpu.h"
+#include "comptbl.h"
+#include "jit/compemu_codegen.h"
+#include "fpu/fpu.h"
+#include "fpu/flags.h"
+
+#define DEBUG 1
+#include "debug.h"
+
+#ifdef ENABLE_MON
+#include "mon.h"
+#endif
+
+#ifndef WIN32
+#define PROFILE_COMPILE_TIME		1
+#define PROFILE_UNTRANSLATED_INSNS	1
+#endif
+
+#if defined(__x86_64__) && 0
+#define RECORD_REGISTER_USAGE		1
+#endif
+
+#ifdef WIN32
+#undef write_log
+#define write_log dummy_write_log
+static void dummy_write_log(const char *, ...) { }
+#endif
+
+#if JIT_DEBUG
+#undef abort
+#define abort() do { \
+	fprintf(stderr, "Abort in file %s at line %d\n", __FILE__, __LINE__); \
+	exit(EXIT_FAILURE); \
+} while (0)
+#endif
+
+#if RECORD_REGISTER_USAGE
+static uint64 reg_count[16];
+static int reg_count_local[16];
+
+static int reg_count_compare(const void *ap, const void *bp)
+{
+    const int a = *((int *)ap);
+    const int b = *((int *)bp);
+    return reg_count[b] - reg_count[a];
+}
+#endif
+
+#if PROFILE_COMPILE_TIME
+#include 
+static uae_u32 compile_count	= 0;
+static clock_t compile_time		= 0;
+static clock_t emul_start_time	= 0;
+static clock_t emul_end_time	= 0;
+#endif
+
+#if PROFILE_UNTRANSLATED_INSNS
+const int untranslated_top_ten = 20;
+static uae_u32 raw_cputbl_count[65536] = { 0, };
+static uae_u16 opcode_nums[65536];
+
+static int untranslated_compfn(const void *e1, const void *e2)
+{
+	return raw_cputbl_count[*(const uae_u16 *)e1] < raw_cputbl_count[*(const uae_u16 *)e2];
+}
+#endif
+
+static compop_func *compfunctbl[65536];
+static compop_func *nfcompfunctbl[65536];
+static cpuop_func *nfcpufunctbl[65536];
+uae_u8* comp_pc_p;
+
+// From newcpu.cpp
+extern bool quit_program;
+
+// gb-- Extra data for Basilisk II/JIT
+#if JIT_DEBUG
+static bool		JITDebug			= false;	// Enable runtime disassemblers through mon?
+#else
+const bool		JITDebug			= false;	// Don't use JIT debug mode at all
+#endif
+#if USE_INLINING
+static bool		follow_const_jumps	= true;		// Flag: translation through constant jumps	
+#else
+const bool		follow_const_jumps	= false;
+#endif
+
+const uae_u32	MIN_CACHE_SIZE		= 1024;		// Minimal translation cache size (1 MB)
+static uae_u32	cache_size			= 0;		// Size of total cache allocated for compiled blocks
+static uae_u32	current_cache_size	= 0;		// Cache grows upwards: how much has been consumed already
+static bool		lazy_flush			= true;		// Flag: lazy translation cache invalidation
+static bool		avoid_fpu			= true;		// Flag: compile FPU instructions ?
+static bool		have_cmov			= false;	// target has CMOV instructions ?
+static bool		have_lahf_lm		= true;		// target has LAHF supported in long mode ?
+static bool		have_rat_stall		= true;		// target has partial register stalls ?
+const bool		tune_alignment		= true;		// Tune code alignments for running CPU ?
+const bool		tune_nop_fillers	= true;		// Tune no-op fillers for architecture
+static bool		setzflg_uses_bsf	= false;	// setzflg virtual instruction can use native BSF instruction correctly?
+static int		align_loops			= 32;		// Align the start of loops
+static int		align_jumps			= 32;		// Align the start of jumps
+static int		optcount[10]		= {
+	10,		// How often a block has to be executed before it is translated
+	0,		// How often to use naive translation
+	0, 0, 0, 0,
+	-1, -1, -1, -1
+};
+
+struct op_properties {
+	uae_u8 use_flags;
+	uae_u8 set_flags;
+	uae_u8 is_addx;
+	uae_u8 cflow;
+};
+static op_properties prop[65536];
+
+static inline int end_block(uae_u32 opcode)
+{
+	return (prop[opcode].cflow & fl_end_block);
+}
+
+static inline bool is_const_jump(uae_u32 opcode)
+{
+	return (prop[opcode].cflow == fl_const_jump);
+}
+
+static inline bool may_trap(uae_u32 opcode)
+{
+	return (prop[opcode].cflow & fl_trap);
+}
+
+static inline unsigned int cft_map (unsigned int f)
+{
+#ifndef HAVE_GET_WORD_UNSWAPPED
+    return f;
+#else
+    return ((f >> 8) & 255) | ((f & 255) << 8);
+#endif
+}
+
+uae_u8* start_pc_p;
+uae_u32 start_pc;
+uae_u32 current_block_pc_p;
+static uintptr current_block_start_target;
+uae_u32 needed_flags;
+static uintptr next_pc_p;
+static uintptr taken_pc_p;
+static int branch_cc;
+static int redo_current_block;
+
+int segvcount=0;
+int soft_flush_count=0;
+int hard_flush_count=0;
+int checksum_count=0;
+static uae_u8* current_compile_p=NULL;
+static uae_u8* max_compile_start;
+static uae_u8* compiled_code=NULL;
+static uae_s32 reg_alloc_run;
+const int POPALLSPACE_SIZE = 1024; /* That should be enough space */
+static uae_u8* popallspace=NULL;
+
+void* pushall_call_handler=NULL;
+static void* popall_do_nothing=NULL;
+static void* popall_exec_nostats=NULL;
+static void* popall_execute_normal=NULL;
+static void* popall_cache_miss=NULL;
+static void* popall_recompile_block=NULL;
+static void* popall_check_checksum=NULL;
+
+/* The 68k only ever executes from even addresses. So right now, we
+ * waste half the entries in this array
+ * UPDATE: We now use those entries to store the start of the linked
+ * lists that we maintain for each hash result.
+ */
+cacheline cache_tags[TAGSIZE];
+int letit=0;
+blockinfo* hold_bi[MAX_HOLD_BI];
+blockinfo* active;
+blockinfo* dormant;
+
+/* 68040 */
+extern struct cputbl op_smalltbl_0_nf[];
+extern struct comptbl op_smalltbl_0_comp_nf[];
+extern struct comptbl op_smalltbl_0_comp_ff[];
+
+/* 68020 + 68881 */
+extern struct cputbl op_smalltbl_1_nf[];
+
+/* 68020 */
+extern struct cputbl op_smalltbl_2_nf[];
+
+/* 68010 */
+extern struct cputbl op_smalltbl_3_nf[];
+
+/* 68000 */
+extern struct cputbl op_smalltbl_4_nf[];
+
+/* 68000 slow but compatible.  */
+extern struct cputbl op_smalltbl_5_nf[];
+
+static void flush_icache_hard(int n);
+static void flush_icache_lazy(int n);
+static void flush_icache_none(int n);
+void (*flush_icache)(int n) = flush_icache_none;
+
+
+
+bigstate live;
+smallstate empty_ss;
+smallstate default_ss;
+static int optlev;
+
+static int writereg(int r, int size);
+static void unlock2(int r);
+static void setlock(int r);
+static int readreg_specific(int r, int size, int spec);
+static int writereg_specific(int r, int size, int spec);
+static void prepare_for_call_1(void);
+static void prepare_for_call_2(void);
+static void align_target(uae_u32 a);
+
+static uae_s32 nextused[VREGS];
+
+uae_u32 m68k_pc_offset;
+
+/* Some arithmetic ooperations can be optimized away if the operands
+ * are known to be constant. But that's only a good idea when the
+ * side effects they would have on the flags are not important. This
+ * variable indicates whether we need the side effects or not
+ */
+uae_u32 needflags=0;
+
+/* Flag handling is complicated.
+ *
+ * x86 instructions create flags, which quite often are exactly what we
+ * want. So at times, the "68k" flags are actually in the x86 flags.
+ *
+ * Then again, sometimes we do x86 instructions that clobber the x86
+ * flags, but don't represent a corresponding m68k instruction. In that
+ * case, we have to save them.
+ *
+ * We used to save them to the stack, but now store them back directly
+ * into the regflags.cznv of the traditional emulation. Thus some odd
+ * names.
+ *
+ * So flags can be in either of two places (used to be three; boy were
+ * things complicated back then!); And either place can contain either
+ * valid flags or invalid trash (and on the stack, there was also the
+ * option of "nothing at all", now gone). A couple of variables keep
+ * track of the respective states.
+ *
+ * To make things worse, we might or might not be interested in the flags.
+ * by default, we are, but a call to dont_care_flags can change that
+ * until the next call to live_flags. If we are not, pretty much whatever
+ * is in the register and/or the native flags is seen as valid.
+ */
+
+static __inline__ blockinfo* get_blockinfo(uae_u32 cl)
+{
+    return cache_tags[cl+1].bi;
+}
+
+static __inline__ blockinfo* get_blockinfo_addr(void* addr)
+{
+    blockinfo*  bi=get_blockinfo(cacheline(addr));
+
+    while (bi) {
+	if (bi->pc_p==addr)
+	    return bi;
+	bi=bi->next_same_cl;
+    }
+    return NULL;
+}
+
+		
+/*******************************************************************
+ * All sorts of list related functions for all of the lists        *
+ *******************************************************************/
+
+static __inline__ void remove_from_cl_list(blockinfo* bi)
+{
+    uae_u32 cl=cacheline(bi->pc_p);
+
+    if (bi->prev_same_cl_p) 
+	*(bi->prev_same_cl_p)=bi->next_same_cl;
+    if (bi->next_same_cl)
+	bi->next_same_cl->prev_same_cl_p=bi->prev_same_cl_p;
+    if (cache_tags[cl+1].bi)
+	cache_tags[cl].handler=cache_tags[cl+1].bi->handler_to_use;
+    else
+	cache_tags[cl].handler=(cpuop_func *)popall_execute_normal;
+}
+
+static __inline__ void remove_from_list(blockinfo* bi)
+{
+    if (bi->prev_p) 
+	*(bi->prev_p)=bi->next;
+    if (bi->next)
+	bi->next->prev_p=bi->prev_p;
+}
+
+static __inline__ void remove_from_lists(blockinfo* bi)
+{
+    remove_from_list(bi);
+    remove_from_cl_list(bi);
+}
+
+static __inline__ void add_to_cl_list(blockinfo* bi)
+{
+    uae_u32 cl=cacheline(bi->pc_p);
+    
+    if (cache_tags[cl+1].bi)
+	cache_tags[cl+1].bi->prev_same_cl_p=&(bi->next_same_cl);
+    bi->next_same_cl=cache_tags[cl+1].bi;
+
+    cache_tags[cl+1].bi=bi;
+    bi->prev_same_cl_p=&(cache_tags[cl+1].bi);
+	
+    cache_tags[cl].handler=bi->handler_to_use;
+}
+
+static __inline__ void raise_in_cl_list(blockinfo* bi)
+{
+    remove_from_cl_list(bi);
+    add_to_cl_list(bi);
+}
+
+static __inline__ void add_to_active(blockinfo* bi)
+{
+    if (active) 
+	active->prev_p=&(bi->next);
+    bi->next=active;
+
+    active=bi;
+    bi->prev_p=&active;
+}
+
+static __inline__ void add_to_dormant(blockinfo* bi)
+{
+    if (dormant) 
+	dormant->prev_p=&(bi->next);
+    bi->next=dormant;
+
+    dormant=bi;
+    bi->prev_p=&dormant;
+}
+
+static __inline__ void remove_dep(dependency* d)
+{
+    if (d->prev_p) 
+	*(d->prev_p)=d->next;
+    if (d->next)
+	d->next->prev_p=d->prev_p;
+    d->prev_p=NULL;
+    d->next=NULL;
+}
+
+/* This block's code is about to be thrown away, so it no longer
+   depends on anything else */
+static __inline__ void remove_deps(blockinfo* bi)
+{
+    remove_dep(&(bi->dep[0]));
+    remove_dep(&(bi->dep[1]));
+}
+
+static __inline__ void adjust_jmpdep(dependency* d, cpuop_func* a)
+{
+    *(d->jmp_off)=(uintptr)a-((uintptr)d->jmp_off+4);
+}
+
+/********************************************************************
+ * Soft flush handling support functions                            *
+ ********************************************************************/
+
+static __inline__ void set_dhtu(blockinfo* bi, cpuop_func* dh)
+{
+    //write_log("bi is %p\n",bi);
+    if (dh!=bi->direct_handler_to_use) {
+	dependency* x=bi->deplist;
+	//write_log("bi->deplist=%p\n",bi->deplist);
+	while (x) {
+	    //write_log("x is %p\n",x);
+	    //write_log("x->next is %p\n",x->next);
+	    //write_log("x->prev_p is %p\n",x->prev_p);
+	    
+	    if (x->jmp_off) {
+		adjust_jmpdep(x,dh);
+	    }
+	    x=x->next;
+	}
+	bi->direct_handler_to_use=dh;
+    }
+}
+
+static __inline__ void invalidate_block(blockinfo* bi)
+{
+    int i;
+
+    bi->optlevel=0;
+    bi->count=optcount[0]-1;
+    bi->handler=NULL;
+    bi->handler_to_use=(cpuop_func *)popall_execute_normal;
+    bi->direct_handler=NULL;
+    set_dhtu(bi,bi->direct_pen);
+    bi->needed_flags=0xff;
+	bi->status=BI_INVALID;
+    for (i=0;i<2;i++) {
+	bi->dep[i].jmp_off=NULL;
+	bi->dep[i].target=NULL;
+    }
+    remove_deps(bi);
+}
+
+static __inline__ void create_jmpdep(blockinfo* bi, int i, uae_u32* jmpaddr, uae_u32 target)
+{
+    blockinfo*  tbi=get_blockinfo_addr((void*)(uintptr)target);
+    
+    Dif(!tbi) {
+	write_log("Could not create jmpdep!\n");
+	abort();
+    }
+    bi->dep[i].jmp_off=jmpaddr;
+	bi->dep[i].source=bi;
+    bi->dep[i].target=tbi;
+    bi->dep[i].next=tbi->deplist;
+    if (bi->dep[i].next) 
+	bi->dep[i].next->prev_p=&(bi->dep[i].next);
+    bi->dep[i].prev_p=&(tbi->deplist);
+    tbi->deplist=&(bi->dep[i]);
+}
+
+static __inline__ void block_need_recompile(blockinfo * bi)
+{
+  uae_u32 cl = cacheline(bi->pc_p);
+  
+  set_dhtu(bi, bi->direct_pen);
+  bi->direct_handler = bi->direct_pen;
+  
+  bi->handler_to_use = (cpuop_func *)popall_execute_normal;
+  bi->handler = (cpuop_func *)popall_execute_normal;
+  if (bi == cache_tags[cl + 1].bi)
+	cache_tags[cl].handler = (cpuop_func *)popall_execute_normal;
+  bi->status = BI_NEED_RECOMP;
+}
+
+static __inline__ void mark_callers_recompile(blockinfo * bi)
+{
+  dependency *x = bi->deplist;
+
+  while (x)	{
+	dependency *next = x->next;	/* This disappears when we mark for
+								 * recompilation and thus remove the
+								 * blocks from the lists */
+	if (x->jmp_off) {
+	  blockinfo *cbi = x->source;
+
+	  Dif(cbi->status == BI_INVALID) {
+		// write_log("invalid block in dependency list\n"); // FIXME?
+		// abort();
+	  }
+	  if (cbi->status == BI_ACTIVE || cbi->status == BI_NEED_CHECK) {
+		block_need_recompile(cbi);
+		mark_callers_recompile(cbi);
+	  }
+	  else if (cbi->status == BI_COMPILING) {
+		redo_current_block = 1;
+	  }
+	  else if (cbi->status == BI_NEED_RECOMP) {
+		/* nothing */
+	  }
+	  else {
+		//write_log("Status %d in mark_callers\n",cbi->status); // FIXME?
+	  }
+	}
+	x = next;
+  }
+}
+
+static __inline__ blockinfo* get_blockinfo_addr_new(void* addr, int setstate)
+{
+    blockinfo*  bi=get_blockinfo_addr(addr);
+    int i;
+
+    if (!bi) {
+	for (i=0;ipc_p=(uae_u8 *)addr;
+		invalidate_block(bi);
+		add_to_active(bi);
+		add_to_cl_list(bi);
+		
+	    }
+	}
+    }
+    if (!bi) {
+	write_log("Looking for blockinfo, can't find free one\n");
+	abort();
+    }
+    return bi;
+}
+
+static void prepare_block(blockinfo* bi);
+
+/* Managment of blockinfos.
+
+   A blockinfo struct is allocated whenever a new block has to be
+   compiled. If the list of free blockinfos is empty, we allocate a new
+   pool of blockinfos and link the newly created blockinfos altogether
+   into the list of free blockinfos. Otherwise, we simply pop a structure
+   off the free list.
+
+   Blockinfo are lazily deallocated, i.e. chained altogether in the
+   list of free blockinfos whenvever a translation cache flush (hard or
+   soft) request occurs.
+*/
+
+template< class T >
+class LazyBlockAllocator
+{
+	enum {
+		kPoolSize = 1 + 4096 / sizeof(T)
+	};
+	struct Pool {
+		T chunk[kPoolSize];
+		Pool * next;
+	};
+	Pool * mPools;
+	T * mChunks;
+public:
+	LazyBlockAllocator() : mPools(0), mChunks(0) { }
+	~LazyBlockAllocator();
+	T * acquire();
+	void release(T * const);
+};
+
+template< class T >
+LazyBlockAllocator::~LazyBlockAllocator()
+{
+	Pool * currentPool = mPools;
+	while (currentPool) {
+		Pool * deadPool = currentPool;
+		currentPool = currentPool->next;
+		free(deadPool);
+	}
+}
+
+template< class T >
+T * LazyBlockAllocator::acquire()
+{
+	if (!mChunks) {
+		// There is no chunk left, allocate a new pool and link the
+		// chunks into the free list
+		Pool * newPool = (Pool *)malloc(sizeof(Pool));
+		for (T * chunk = &newPool->chunk[0]; chunk < &newPool->chunk[kPoolSize]; chunk++) {
+			chunk->next = mChunks;
+			mChunks = chunk;
+		}
+		newPool->next = mPools;
+		mPools = newPool;
+	}
+	T * chunk = mChunks;
+	mChunks = chunk->next;
+	return chunk;
+}
+
+template< class T >
+void LazyBlockAllocator::release(T * const chunk)
+{
+	chunk->next = mChunks;
+	mChunks = chunk;
+}
+
+template< class T >
+class HardBlockAllocator
+{
+public:
+	T * acquire() {
+		T * data = (T *)current_compile_p;
+		current_compile_p += sizeof(T);
+		return data;
+	}
+
+	void release(T * const chunk) {
+		// Deallocated on invalidation
+	}
+};
+
+#if USE_SEPARATE_BIA
+static LazyBlockAllocator BlockInfoAllocator;
+static LazyBlockAllocator ChecksumInfoAllocator;
+#else
+static HardBlockAllocator BlockInfoAllocator;
+static HardBlockAllocator ChecksumInfoAllocator;
+#endif
+
+static __inline__ checksum_info *alloc_checksum_info(void)
+{
+	checksum_info *csi = ChecksumInfoAllocator.acquire();
+	csi->next = NULL;
+	return csi;
+}
+
+static __inline__ void free_checksum_info(checksum_info *csi)
+{
+	csi->next = NULL;
+	ChecksumInfoAllocator.release(csi);
+}
+
+static __inline__ void free_checksum_info_chain(checksum_info *csi)
+{
+	while (csi != NULL) {
+		checksum_info *csi2 = csi->next;
+		free_checksum_info(csi);
+		csi = csi2;
+	}
+}
+
+static __inline__ blockinfo *alloc_blockinfo(void)
+{
+	blockinfo *bi = BlockInfoAllocator.acquire();
+#if USE_CHECKSUM_INFO
+	bi->csi = NULL;
+#endif
+	return bi;
+}
+
+static __inline__ void free_blockinfo(blockinfo *bi)
+{
+#if USE_CHECKSUM_INFO
+	free_checksum_info_chain(bi->csi);
+	bi->csi = NULL;
+#endif
+	BlockInfoAllocator.release(bi);
+}
+
+static __inline__ void alloc_blockinfos(void) 
+{
+    int i;
+    blockinfo* bi;
+
+    for (i=0;i>24)&0xff) | ((v>>8)&0xff00) | ((v<<8)&0xff0000) | ((v<<24)&0xff000000);
+#endif
+}
+
+/********************************************************************
+ * Getting the information about the target CPU                     *
+ ********************************************************************/
+
+#include "codegen_x86.cpp"
+
+void set_target(uae_u8* t)
+{
+    target=t;
+}
+
+static __inline__ uae_u8* get_target_noopt(void)
+{
+    return target;
+}
+
+__inline__ uae_u8* get_target(void)
+{
+    return get_target_noopt();
+}
+
+
+/********************************************************************
+ * Flags status handling. EMIT TIME!                                *
+ ********************************************************************/
+
+static void bt_l_ri_noclobber(R4 r, IMM i);
+
+static void make_flags_live_internal(void)
+{
+    if (live.flags_in_flags==VALID)
+	return;
+    Dif (live.flags_on_stack==TRASH) {
+	write_log("Want flags, got something on stack, but it is TRASH\n");
+	abort();
+    }
+    if (live.flags_on_stack==VALID) {
+	int tmp;
+	tmp=readreg_specific(FLAGTMP,4,FLAG_NREG2);
+	raw_reg_to_flags(tmp);
+	unlock2(tmp);
+
+	live.flags_in_flags=VALID;
+	return;
+    }
+    write_log("Huh? live.flags_in_flags=%d, live.flags_on_stack=%d, but need to make live\n",
+	   live.flags_in_flags,live.flags_on_stack);
+    abort();
+}
+
+static void flags_to_stack(void)
+{
+    if (live.flags_on_stack==VALID)
+	return;
+    if (!live.flags_are_important) {
+	live.flags_on_stack=VALID;
+	return;
+    }
+    Dif (live.flags_in_flags!=VALID)
+	abort();
+    else  {
+	int tmp;
+	tmp=writereg_specific(FLAGTMP,4,FLAG_NREG1);
+	raw_flags_to_reg(tmp);
+	unlock2(tmp);
+    }
+    live.flags_on_stack=VALID;
+}
+
+static __inline__ void clobber_flags(void)
+{
+    if (live.flags_in_flags==VALID && live.flags_on_stack!=VALID)
+	flags_to_stack();
+    live.flags_in_flags=TRASH;
+}
+
+/* Prepare for leaving the compiled stuff */
+static __inline__ void flush_flags(void)
+{
+    flags_to_stack();
+    return;
+}
+
+int touchcnt;
+
+/********************************************************************
+ * Partial register flushing for optimized calls                    *
+ ********************************************************************/
+
+struct regusage {
+	uae_u16 rmask;
+	uae_u16 wmask;
+};
+
+static inline void ru_set(uae_u16 *mask, int reg)
+{
+#if USE_OPTIMIZED_CALLS
+	*mask |= 1 << reg;
+#endif
+}
+
+static inline bool ru_get(const uae_u16 *mask, int reg)
+{
+#if USE_OPTIMIZED_CALLS
+	return (*mask & (1 << reg));
+#else
+	/* Default: instruction reads & write to register */
+	return true;
+#endif
+}
+
+static inline void ru_set_read(regusage *ru, int reg)
+{
+	ru_set(&ru->rmask, reg);
+}
+
+static inline void ru_set_write(regusage *ru, int reg)
+{
+	ru_set(&ru->wmask, reg);
+}
+
+static inline bool ru_read_p(const regusage *ru, int reg)
+{
+	return ru_get(&ru->rmask, reg);
+}
+
+static inline bool ru_write_p(const regusage *ru, int reg)
+{
+	return ru_get(&ru->wmask, reg);
+}
+
+static void ru_fill_ea(regusage *ru, int reg, amodes mode,
+					   wordsizes size, int write_mode)
+{
+	switch (mode) {
+	case Areg:
+		reg += 8;
+		/* fall through */
+	case Dreg:
+		ru_set(write_mode ? &ru->wmask : &ru->rmask, reg);
+		break;
+	case Ad16:
+		/* skip displacment */
+		m68k_pc_offset += 2;
+	case Aind:
+	case Aipi:
+	case Apdi:
+		ru_set_read(ru, reg+8);
+		break;
+	case Ad8r:
+		ru_set_read(ru, reg+8);
+		/* fall through */
+	case PC8r: {
+		uae_u16 dp = comp_get_iword((m68k_pc_offset+=2)-2);
+		reg = (dp >> 12) & 15;
+		ru_set_read(ru, reg);
+		if (dp & 0x100)
+			m68k_pc_offset += (((dp & 0x30) >> 3) & 7) + ((dp & 3) * 2);
+		break;
+	}
+	case PC16:
+	case absw:
+	case imm0:
+	case imm1:
+		m68k_pc_offset += 2;
+		break;
+	case absl:
+	case imm2:
+		m68k_pc_offset += 4;
+		break;
+	case immi:
+		m68k_pc_offset += (size == sz_long) ? 4 : 2;
+		break;
+	}
+}
+
+/* TODO: split into a static initialization part and a dynamic one
+   (instructions depending on extension words) */
+static void ru_fill(regusage *ru, uae_u32 opcode)
+{
+	m68k_pc_offset += 2;
+
+	/* Default: no register is used or written to */
+	ru->rmask = 0;
+	ru->wmask = 0;
+
+	uae_u32 real_opcode = cft_map(opcode);
+	struct instr *dp = &table68k[real_opcode];
+
+	bool rw_dest = true;
+	bool handled = false;
+
+	/* Handle some instructions specifically */
+	uae_u16 reg, ext;
+	switch (dp->mnemo) {
+	case i_BFCHG:
+	case i_BFCLR:
+	case i_BFEXTS:
+	case i_BFEXTU:
+	case i_BFFFO:
+	case i_BFINS:
+	case i_BFSET:
+	case i_BFTST:
+		ext = comp_get_iword((m68k_pc_offset+=2)-2);
+		if (ext & 0x800) ru_set_read(ru, (ext >> 6) & 7);
+		if (ext & 0x020) ru_set_read(ru, ext & 7);
+		ru_fill_ea(ru, dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, 1);
+		if (dp->dmode == Dreg)
+			ru_set_read(ru, dp->dreg);
+		switch (dp->mnemo) {
+		case i_BFEXTS:
+		case i_BFEXTU:
+		case i_BFFFO:
+			ru_set_write(ru, (ext >> 12) & 7);
+			break;
+		case i_BFINS:
+			ru_set_read(ru, (ext >> 12) & 7);
+			/* fall through */
+		case i_BFCHG:
+		case i_BFCLR:
+		case i_BSET:
+			if (dp->dmode == Dreg)
+				ru_set_write(ru, dp->dreg);
+			break;
+		}
+		handled = true;
+		rw_dest = false;
+		break;
+
+	case i_BTST:
+		rw_dest = false;
+		break;
+
+	case i_CAS:
+	{
+		ext = comp_get_iword((m68k_pc_offset+=2)-2);
+		int Du = ext & 7;
+		ru_set_read(ru, Du);
+		int Dc = (ext >> 6) & 7;
+		ru_set_read(ru, Dc);
+		ru_set_write(ru, Dc);
+		break;
+	}
+	case i_CAS2:
+	{
+		int Dc1, Dc2, Du1, Du2, Rn1, Rn2;
+		ext = comp_get_iword((m68k_pc_offset+=2)-2);
+		Rn1 = (ext >> 12) & 15;
+		Du1 = (ext >> 6) & 7;
+		Dc1 = ext & 7;
+		ru_set_read(ru, Rn1);
+		ru_set_read(ru, Du1);
+		ru_set_read(ru, Dc1);
+		ru_set_write(ru, Dc1);
+		ext = comp_get_iword((m68k_pc_offset+=2)-2);
+		Rn2 = (ext >> 12) & 15;
+		Du2 = (ext >> 6) & 7;
+		Dc2 = ext & 7;
+		ru_set_read(ru, Rn2);
+		ru_set_read(ru, Du2);
+		ru_set_write(ru, Dc2);
+		break;
+	}
+	case i_DIVL: case i_MULL:
+		m68k_pc_offset += 2;
+		break;
+	case i_LEA:
+	case i_MOVE: case i_MOVEA: case i_MOVE16:
+		rw_dest = false;
+		break;
+	case i_PACK: case i_UNPK:
+		rw_dest = false;
+		m68k_pc_offset += 2;
+		break;
+	case i_TRAPcc:
+		m68k_pc_offset += (dp->size == sz_long) ? 4 : 2;
+		break;
+	case i_RTR:
+		/* do nothing, just for coverage debugging */
+		break;
+	/* TODO: handle EXG instruction */
+	}
+
+	/* Handle A-Traps better */
+	if ((real_opcode & 0xf000) == 0xa000) {
+		handled = true;
+	}
+
+	/* Handle EmulOps better */
+	if ((real_opcode & 0xff00) == 0x7100) {
+		handled = true;
+		ru->rmask = 0xffff;
+		ru->wmask = 0;
+	}
+
+	if (dp->suse && !handled)
+		ru_fill_ea(ru, dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, 0);
+
+	if (dp->duse && !handled)
+		ru_fill_ea(ru, dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, 1);
+
+	if (rw_dest)
+		ru->rmask |= ru->wmask;
+
+	handled = handled || dp->suse || dp->duse;
+
+	/* Mark all registers as used/written if the instruction may trap */
+	if (may_trap(opcode)) {
+		handled = true;
+		ru->rmask = 0xffff;
+		ru->wmask = 0xffff;
+	}
+
+	if (!handled) {
+		write_log("ru_fill: %04x = { %04x, %04x }\n",
+				  real_opcode, ru->rmask, ru->wmask);
+		abort();
+	}
+}
+
+/********************************************************************
+ * register allocation per block logging                            *
+ ********************************************************************/
+
+static uae_s8 vstate[VREGS];
+static uae_s8 vwritten[VREGS];
+static uae_s8 nstate[N_REGS];
+
+#define L_UNKNOWN -127
+#define L_UNAVAIL -1
+#define L_NEEDED -2
+#define L_UNNEEDED -3
+
+static __inline__ void big_to_small_state(bigstate * b, smallstate * s)
+{
+  int i;
+	
+  for (i = 0; i < VREGS; i++)
+	s->virt[i] = vstate[i];
+  for (i = 0; i < N_REGS; i++)
+	s->nat[i] = nstate[i];
+}
+
+static __inline__ int callers_need_recompile(bigstate * b, smallstate * s)
+{
+  int i;
+  int reverse = 0;
+
+  for (i = 0; i < VREGS; i++) {
+	if (vstate[i] != L_UNNEEDED && s->virt[i] == L_UNNEEDED)
+	  return 1;
+	if (vstate[i] == L_UNNEEDED && s->virt[i] != L_UNNEEDED)
+	  reverse++;
+  }
+  for (i = 0; i < N_REGS; i++) {
+	if (nstate[i] >= 0 && nstate[i] != s->nat[i])
+	  return 1;
+	if (nstate[i] < 0 && s->nat[i] >= 0)
+	  reverse++;
+  }
+  if (reverse >= 2 && USE_MATCH)
+	return 1;	/* In this case, it might be worth recompiling the
+				 * callers */
+  return 0;
+}
+
+static __inline__ void log_startblock(void)
+{
+  int i;
+
+  for (i = 0; i < VREGS; i++) {
+	vstate[i] = L_UNKNOWN;
+	vwritten[i] = 0;
+  }
+  for (i = 0; i < N_REGS; i++)
+	nstate[i] = L_UNKNOWN;
+}
+
+/* Using an n-reg for a temp variable */
+static __inline__ void log_isused(int n)
+{
+  if (nstate[n] == L_UNKNOWN)
+	nstate[n] = L_UNAVAIL;
+}
+
+static __inline__ void log_visused(int r)
+{
+  if (vstate[r] == L_UNKNOWN)
+	vstate[r] = L_NEEDED;
+}
+
+static __inline__ void do_load_reg(int n, int r)
+{
+  if (r == FLAGTMP)
+	raw_load_flagreg(n, r);
+  else if (r == FLAGX)
+	raw_load_flagx(n, r);
+  else
+	raw_mov_l_rm(n, (uintptr) live.state[r].mem);
+}
+
+static __inline__ void check_load_reg(int n, int r)
+{
+  raw_mov_l_rm(n, (uintptr) live.state[r].mem);
+}
+
+static __inline__ void log_vwrite(int r)
+{
+  vwritten[r] = 1;
+}
+
+/* Using an n-reg to hold a v-reg */
+static __inline__ void log_isreg(int n, int r)
+{
+  static int count = 0;
+  
+  if (nstate[n] == L_UNKNOWN && r < 16 && !vwritten[r] && USE_MATCH)
+	nstate[n] = r;
+  else {
+	do_load_reg(n, r);
+	if (nstate[n] == L_UNKNOWN)
+	  nstate[n] = L_UNAVAIL;
+  }
+  if (vstate[r] == L_UNKNOWN)
+	vstate[r] = L_NEEDED;
+}
+
+static __inline__ void log_clobberreg(int r)
+{
+  if (vstate[r] == L_UNKNOWN)
+	vstate[r] = L_UNNEEDED;
+}
+
+/* This ends all possibility of clever register allocation */
+
+static __inline__ void log_flush(void)
+{
+  int i;
+  
+  for (i = 0; i < VREGS; i++)
+	if (vstate[i] == L_UNKNOWN)
+	  vstate[i] = L_NEEDED;
+  for (i = 0; i < N_REGS; i++)
+	if (nstate[i] == L_UNKNOWN)
+	  nstate[i] = L_UNAVAIL;
+}
+
+static __inline__ void log_dump(void)
+{
+  int i;
+  
+  return;
+  
+  write_log("----------------------\n");
+  for (i = 0; i < N_REGS; i++) {
+	switch (nstate[i]) {
+	case L_UNKNOWN:
+	  write_log("Nat %d : UNKNOWN\n", i);
+	  break;
+	case L_UNAVAIL:
+	  write_log("Nat %d : UNAVAIL\n", i);
+	  break;
+	default:
+	  write_log("Nat %d : %d\n", i, nstate[i]);
+	  break;
+	}
+  }
+  for (i = 0; i < VREGS; i++) {
+	if (vstate[i] == L_UNNEEDED)
+	  write_log("Virt %d: UNNEEDED\n", i);
+  }
+}
+
+/********************************************************************
+ * register status handling. EMIT TIME!                             *
+ ********************************************************************/
+
+static __inline__ void set_status(int r, int status)
+{
+	if (status == ISCONST)
+		log_clobberreg(r);
+    live.state[r].status=status;
+}
+
+static __inline__ int isinreg(int r)
+{
+    return live.state[r].status==CLEAN || live.state[r].status==DIRTY;
+}
+
+static __inline__ void adjust_nreg(int r, uae_u32 val)
+{
+    if (!val)
+	return;
+    raw_lea_l_brr(r,r,val);
+}
+
+static  void tomem(int r)
+{
+    int rr=live.state[r].realreg;
+
+    if (isinreg(r)) {
+	if (live.state[r].val && live.nat[rr].nholds==1
+		&& !live.nat[rr].locked) {
+	    // write_log("RemovingA offset %x from reg %d (%d) at %p\n",
+	    //   live.state[r].val,r,rr,target); 
+	    adjust_nreg(rr,live.state[r].val);
+	    live.state[r].val=0;
+	    live.state[r].dirtysize=4;
+	    set_status(r,DIRTY);
+	}
+    }
+
+    if (live.state[r].status==DIRTY) {
+	switch (live.state[r].dirtysize) {
+	 case 1: raw_mov_b_mr((uintptr)live.state[r].mem,rr); break;
+	 case 2: raw_mov_w_mr((uintptr)live.state[r].mem,rr); break;
+	 case 4: raw_mov_l_mr((uintptr)live.state[r].mem,rr); break;
+	 default: abort();
+	}
+	log_vwrite(r);
+	set_status(r,CLEAN);
+	live.state[r].dirtysize=0;
+    }
+}
+
+static __inline__ int isconst(int r)
+{
+    return live.state[r].status==ISCONST;
+}
+
+int is_const(int r)
+{
+    return isconst(r);
+}
+
+static __inline__ void writeback_const(int r)
+{
+    if (!isconst(r))
+	return;
+    Dif (live.state[r].needflush==NF_HANDLER) {
+	write_log("Trying to write back constant NF_HANDLER!\n");
+	abort();
+    }
+
+    raw_mov_l_mi((uintptr)live.state[r].mem,live.state[r].val);
+	log_vwrite(r);
+    live.state[r].val=0;
+    set_status(r,INMEM);
+}
+
+static __inline__ void tomem_c(int r)
+{
+    if (isconst(r)) {
+	writeback_const(r);
+    }
+    else
+	tomem(r);
+}
+
+static  void evict(int r)
+{
+    int rr;
+
+    if (!isinreg(r))
+	return;
+    tomem(r);
+    rr=live.state[r].realreg;
+
+    Dif (live.nat[rr].locked &&
+	live.nat[rr].nholds==1) {
+	write_log("register %d in nreg %d is locked!\n",r,live.state[r].realreg);
+	abort();
+    }
+
+    live.nat[rr].nholds--;
+    if (live.nat[rr].nholds!=live.state[r].realind) { /* Was not last */
+	int topreg=live.nat[rr].holds[live.nat[rr].nholds];
+	int thisind=live.state[r].realind;
+	
+	live.nat[rr].holds[thisind]=topreg;
+	live.state[topreg].realind=thisind;
+    }
+    live.state[r].realreg=-1;
+    set_status(r,INMEM);
+}
+
+static __inline__ void free_nreg(int r)
+{
+    int i=live.nat[r].nholds;
+
+    while (i) {
+	int vr;
+
+	--i;
+	vr=live.nat[r].holds[i];
+	evict(vr);
+    }
+    Dif (live.nat[r].nholds!=0) {
+	write_log("Failed to free nreg %d, nholds is %d\n",r,live.nat[r].nholds);
+	abort();
+    }
+}
+
+/* Use with care! */
+static __inline__ void isclean(int r)
+{
+    if (!isinreg(r))
+	return;
+    live.state[r].validsize=4;
+    live.state[r].dirtysize=0;
+    live.state[r].val=0;
+    set_status(r,CLEAN);
+}
+
+static __inline__ void disassociate(int r)
+{
+    isclean(r);
+    evict(r);
+}
+
+static __inline__ void set_const(int r, uae_u32 val)
+{
+    disassociate(r);
+    live.state[r].val=val;
+    set_status(r,ISCONST);
+}
+
+static __inline__ uae_u32 get_offset(int r)
+{
+    return live.state[r].val;
+}
+
+static  int alloc_reg_hinted(int r, int size, int willclobber, int hint)
+{
+    int bestreg;
+    uae_s32 when;
+    int i;
+    uae_s32 badness=0; /* to shut up gcc */
+    bestreg=-1;
+    when=2000000000;
+
+    /* XXX use a regalloc_order table? */
+    for (i=0;i0) {
+	free_nreg(bestreg);
+    }
+    if (isinreg(r)) {
+	int rr=live.state[r].realreg;
+	/* This will happen if we read a partially dirty register at a
+	   bigger size */
+	Dif (willclobber || live.state[r].validsize>=size)
+	    abort();
+	Dif (live.nat[rr].nholds!=1)
+	    abort();
+	if (size==4 && live.state[r].validsize==2) {
+		log_isused(bestreg);
+		log_visused(r);
+	    raw_mov_l_rm(bestreg,(uintptr)live.state[r].mem);
+	    raw_bswap_32(bestreg);
+	    raw_zero_extend_16_rr(rr,rr);
+	    raw_zero_extend_16_rr(bestreg,bestreg);
+	    raw_bswap_32(bestreg);
+	    raw_lea_l_brr_indexed(rr,rr,bestreg,1,0);
+	    live.state[r].validsize=4;
+	    live.nat[rr].touched=touchcnt++;
+	    return rr;
+	}
+	if (live.state[r].validsize==1) {
+	    /* Nothing yet */
+	}
+	evict(r);
+    }
+
+    if (!willclobber) {
+	if (live.state[r].status!=UNDEF) {
+	    if (isconst(r)) {
+		raw_mov_l_ri(bestreg,live.state[r].val);
+		live.state[r].val=0;
+		live.state[r].dirtysize=4;
+		set_status(r,DIRTY);
+		log_isused(bestreg);
+	    }
+	    else {
+		log_isreg(bestreg, r);  /* This will also load it! */
+		live.state[r].dirtysize=0;
+		set_status(r,CLEAN);
+	    }
+	}
+	else {
+	    live.state[r].val=0;
+	    live.state[r].dirtysize=0;
+	    set_status(r,CLEAN);
+		log_isused(bestreg);
+	}
+	live.state[r].validsize=4;
+    }
+    else { /* this is the easiest way, but not optimal. FIXME! */
+	/* Now it's trickier, but hopefully still OK */
+	if (!isconst(r) || size==4) {
+	    live.state[r].validsize=size;
+	    live.state[r].dirtysize=size;
+	    live.state[r].val=0;
+	    set_status(r,DIRTY);
+		if (size == 4) {
+			log_clobberreg(r);
+			log_isused(bestreg);
+		}
+		else {
+			log_visused(r);
+			log_isused(bestreg);
+		}
+	}
+	else {
+	    if (live.state[r].status!=UNDEF)
+		raw_mov_l_ri(bestreg,live.state[r].val);
+	    live.state[r].val=0;
+	    live.state[r].validsize=4;
+	    live.state[r].dirtysize=4;
+	    set_status(r,DIRTY);
+		log_isused(bestreg);
+	}
+    }
+    live.state[r].realreg=bestreg;
+    live.state[r].realind=live.nat[bestreg].nholds;
+    live.nat[bestreg].touched=touchcnt++;
+    live.nat[bestreg].holds[live.nat[bestreg].nholds]=r;
+    live.nat[bestreg].nholds++;
+
+    return bestreg;
+}
+
+static  int alloc_reg(int r, int size, int willclobber)
+{
+    return alloc_reg_hinted(r,size,willclobber,-1);
+}
+
+static  void unlock2(int r)
+{
+    Dif (!live.nat[r].locked)
+	abort();
+    live.nat[r].locked--;
+}
+
+static  void setlock(int r)
+{
+    live.nat[r].locked++;
+}
+
+
+static void mov_nregs(int d, int s)
+{
+    int ns=live.nat[s].nholds;
+    int nd=live.nat[d].nholds;
+    int i;
+
+    if (s==d)
+	return;
+
+    if (nd>0) 
+	free_nreg(d);
+
+	log_isused(d);
+    raw_mov_l_rr(d,s);
+
+    for (i=0;i=size) {
+	n=live.state[r].realreg;
+	switch(size) {
+	 case 1: 
+	    if (live.nat[n].canbyte || spec>=0) { 
+		answer=n; 
+	    }
+	    break;
+	 case 2: 
+	    if (live.nat[n].canword || spec>=0) { 
+		answer=n; 
+	    }
+	    break;
+	 case 4: 
+	    answer=n; 
+	    break;
+	 default: abort();
+	}
+	if (answer<0)
+	    evict(r);
+    }
+    /* either the value was in memory to start with, or it was evicted and 
+       is in memory now */
+    if (answer<0) {
+	answer=alloc_reg_hinted(r,spec>=0?4:size,0,spec);
+    }
+
+    if (spec>=0 && spec!=answer) {
+	/* Too bad */
+	mov_nregs(spec,answer);
+	answer=spec;
+    }
+    live.nat[answer].locked++;
+    live.nat[answer].touched=touchcnt++;
+    return answer;
+}
+
+
+
+static int readreg(int r, int size)
+{
+    return readreg_general(r,size,-1,0);
+}
+
+static int readreg_specific(int r, int size, int spec)
+{
+    return readreg_general(r,size,spec,0);
+}
+
+static int readreg_offset(int r, int size)
+{
+    return readreg_general(r,size,-1,1);
+}
+
+/* writereg_general(r, size, spec)
+ *
+ * INPUT
+ * - r    : mid-layer register
+ * - size : requested size (1/2/4)
+ * - spec : -1 if find or make a register free, otherwise specifies
+ *          the physical register to use in any case
+ *
+ * OUTPUT
+ * - hard (physical, x86 here) register allocated to virtual register r
+ */
+static __inline__ int writereg_general(int r, int size, int spec)
+{
+    int n;
+    int answer=-1;
+
+    record_register(r);
+    if (size<4) {
+	remove_offset(r,spec);
+    }
+
+    make_exclusive(r,size,spec);
+    if (isinreg(r)) {
+	int nvsize=size>live.state[r].validsize?size:live.state[r].validsize;
+	int ndsize=size>live.state[r].dirtysize?size:live.state[r].dirtysize;
+	n=live.state[r].realreg;
+
+	Dif (live.nat[n].nholds!=1)
+	    abort();
+	switch(size) {
+	 case 1: 
+	    if (live.nat[n].canbyte || spec>=0) { 
+		live.state[r].dirtysize=ndsize;
+		live.state[r].validsize=nvsize;
+		answer=n;
+	    }
+	    break;
+	 case 2: 
+	    if (live.nat[n].canword || spec>=0) { 
+		live.state[r].dirtysize=ndsize;
+		live.state[r].validsize=nvsize;
+		answer=n;
+	    }
+	    break;
+	 case 4: 
+	    live.state[r].dirtysize=ndsize;
+	    live.state[r].validsize=nvsize;
+	    answer=n;
+	    break;
+	 default: abort();
+	}
+	if (answer<0)
+	    evict(r);
+    }
+    /* either the value was in memory to start with, or it was evicted and 
+       is in memory now */
+    if (answer<0) {
+	answer=alloc_reg_hinted(r,size,1,spec);
+    }
+    if (spec>=0 && spec!=answer) {
+	mov_nregs(spec,answer);
+	answer=spec;
+    }
+    if (live.state[r].status==UNDEF)
+	live.state[r].validsize=4;
+    live.state[r].dirtysize=size>live.state[r].dirtysize?size:live.state[r].dirtysize;
+    live.state[r].validsize=size>live.state[r].validsize?size:live.state[r].validsize;
+    
+    live.nat[answer].locked++;
+    live.nat[answer].touched=touchcnt++;
+    if (size==4) {
+	live.state[r].val=0;
+    }
+    else {
+	Dif (live.state[r].val) {
+	    write_log("Problem with val\n");
+	    abort();
+	}
+    }
+    set_status(r,DIRTY);
+    return answer;
+}
+
+static int writereg(int r, int size)
+{
+    return writereg_general(r,size,-1);
+}
+
+static int writereg_specific(int r, int size, int spec)
+{
+    return writereg_general(r,size,spec);
+}
+
+static __inline__ int rmw_general(int r, int wsize, int rsize, int spec)
+{
+    int n;
+    int answer=-1;
+    
+    record_register(r);
+	if (live.state[r].status==UNDEF) {
+		write_log("WARNING: Unexpected read of undefined register %d\n",r);
+	}
+    remove_offset(r,spec);
+    make_exclusive(r,0,spec);
+
+    Dif (wsize=rsize) {
+	n=live.state[r].realreg;
+	Dif (live.nat[n].nholds!=1)
+	    abort();
+
+	switch(rsize) {
+	 case 1: 
+	    if (live.nat[n].canbyte || spec>=0) { 
+		answer=n; 
+	    }
+	    break;
+	 case 2: 
+	    if (live.nat[n].canword || spec>=0) { 
+		answer=n; 
+	    }
+	    break;
+	 case 4: 
+	    answer=n; 
+	    break;
+	 default: abort();
+	}
+	if (answer<0)
+	    evict(r);
+    }
+    /* either the value was in memory to start with, or it was evicted and 
+       is in memory now */
+    if (answer<0) {
+	answer=alloc_reg_hinted(r,spec>=0?4:rsize,0,spec);
+    }
+
+    if (spec>=0 && spec!=answer) {
+	/* Too bad */
+	mov_nregs(spec,answer);
+	answer=spec;
+    }
+    if (wsize>live.state[r].dirtysize)
+	live.state[r].dirtysize=wsize;
+    if (wsize>live.state[r].validsize)
+	live.state[r].validsize=wsize;
+    set_status(r,DIRTY);
+
+    live.nat[answer].locked++;
+    live.nat[answer].touched=touchcnt++;
+
+    Dif (live.state[r].val) {
+	write_log("Problem with val(rmw)\n");
+	abort();
+    }
+    return answer;
+}
+
+static int rmw(int r, int wsize, int rsize) 
+{
+    return rmw_general(r,wsize,rsize,-1);
+}
+
+static int rmw_specific(int r, int wsize, int rsize, int spec) 
+{
+    return rmw_general(r,wsize,rsize,spec);
+}
+
+
+/* needed for restoring the carry flag on non-P6 cores */
+static void bt_l_ri_noclobber(R4 r, IMM i)
+{
+    int size=4;
+    if (i<16)
+	size=2;
+    r=readreg(r,size);
+    raw_bt_l_ri(r,i);
+    unlock2(r);
+}
+
+/********************************************************************
+ * FPU register status handling. EMIT TIME!                         *
+ ********************************************************************/
+
+static  void f_tomem(int r)
+{
+    if (live.fate[r].status==DIRTY) {
+#if USE_LONG_DOUBLE
+	raw_fmov_ext_mr((uintptr)live.fate[r].mem,live.fate[r].realreg); 
+#else
+	raw_fmov_mr((uintptr)live.fate[r].mem,live.fate[r].realreg); 
+#endif
+	live.fate[r].status=CLEAN;
+    }
+}
+
+static  void f_tomem_drop(int r)
+{
+    if (live.fate[r].status==DIRTY) {
+#if USE_LONG_DOUBLE
+	raw_fmov_ext_mr_drop((uintptr)live.fate[r].mem,live.fate[r].realreg); 
+#else
+	raw_fmov_mr_drop((uintptr)live.fate[r].mem,live.fate[r].realreg); 
+#endif
+	live.fate[r].status=INMEM;
+    }
+}
+
+
+static __inline__ int f_isinreg(int r)
+{
+    return live.fate[r].status==CLEAN || live.fate[r].status==DIRTY;
+}
+
+static void f_evict(int r)
+{
+    int rr;
+
+    if (!f_isinreg(r))
+	return;
+    rr=live.fate[r].realreg;
+    if (live.fat[rr].nholds==1)
+	f_tomem_drop(r);
+    else
+	f_tomem(r);
+
+    Dif (live.fat[rr].locked &&
+	live.fat[rr].nholds==1) {
+	write_log("FPU register %d in nreg %d is locked!\n",r,live.fate[r].realreg);
+	abort();
+    }
+
+    live.fat[rr].nholds--;
+    if (live.fat[rr].nholds!=live.fate[r].realind) { /* Was not last */
+	int topreg=live.fat[rr].holds[live.fat[rr].nholds];
+	int thisind=live.fate[r].realind;
+	live.fat[rr].holds[thisind]=topreg;
+	live.fate[topreg].realind=thisind;
+    }
+    live.fate[r].status=INMEM;
+    live.fate[r].realreg=-1;
+}
+
+static __inline__ void f_free_nreg(int r)
+{
+    int i=live.fat[r].nholds;
+
+    while (i) {
+	int vr;
+
+	--i;
+	vr=live.fat[r].holds[i];
+	f_evict(vr);
+    }
+    Dif (live.fat[r].nholds!=0) {
+	write_log("Failed to free nreg %d, nholds is %d\n",r,live.fat[r].nholds);
+	abort();
+    }
+}
+
+
+/* Use with care! */
+static __inline__ void f_isclean(int r)
+{
+    if (!f_isinreg(r))
+	return;
+    live.fate[r].status=CLEAN;
+}
+
+static __inline__ void f_disassociate(int r)
+{
+    f_isclean(r);
+    f_evict(r);
+}
+
+
+
+static  int f_alloc_reg(int r, int willclobber)
+{
+    int bestreg;
+    uae_s32 when;
+    int i;
+    uae_s32 badness;
+    bestreg=-1;
+    when=2000000000;
+    for (i=N_FREGS;i--;) {
+	badness=live.fat[i].touched;
+	if (live.fat[i].nholds==0)
+	    badness=0;
+
+	if (!live.fat[i].locked && badness0) {
+	f_free_nreg(bestreg);
+    }
+    if (f_isinreg(r)) {
+	f_evict(r);
+    }
+
+    if (!willclobber) {
+	if (live.fate[r].status!=UNDEF) {
+#if USE_LONG_DOUBLE
+	    raw_fmov_ext_rm(bestreg,(uintptr)live.fate[r].mem);
+#else
+	    raw_fmov_rm(bestreg,(uintptr)live.fate[r].mem);
+#endif
+	}
+	live.fate[r].status=CLEAN;
+    }
+    else { 
+	live.fate[r].status=DIRTY;
+    }
+    live.fate[r].realreg=bestreg;
+    live.fate[r].realind=live.fat[bestreg].nholds;
+    live.fat[bestreg].touched=touchcnt++;
+    live.fat[bestreg].holds[live.fat[bestreg].nholds]=r;
+    live.fat[bestreg].nholds++;
+
+    return bestreg;
+}
+
+static  void f_unlock(int r)
+{
+    Dif (!live.fat[r].locked)
+	abort();
+    live.fat[r].locked--;
+}
+
+static  void f_setlock(int r)
+{
+    live.fat[r].locked++;
+}
+
+static __inline__ int f_readreg(int r)
+{
+    int n;
+    int answer=-1;
+
+    if (f_isinreg(r)) {
+	n=live.fate[r].realreg;
+	answer=n; 
+    }
+    /* either the value was in memory to start with, or it was evicted and 
+       is in memory now */
+    if (answer<0) 
+	answer=f_alloc_reg(r,0);
+
+    live.fat[answer].locked++;
+    live.fat[answer].touched=touchcnt++;
+    return answer;
+}
+
+static __inline__ void f_make_exclusive(int r, int clobber)
+{
+    freg_status oldstate;
+    int rr=live.fate[r].realreg;
+    int nr;
+    int nind;
+    int ndirt=0;
+    int i;
+
+    if (!f_isinreg(r))
+	return;
+    if (live.fat[rr].nholds==1)
+	return;
+    for (i=0;i>=i;
+	return;
+    }
+    CLOBBER_SHRL;
+    r=rmw(r,4,4);
+    raw_shrl_l_ri(r,i);
+    unlock2(r);
+}
+MENDFUNC(2,shrl_l_ri,(RW4 r, IMM i))
+
+MIDFUNC(2,shrl_w_ri,(RW2 r, IMM i))
+{
+    if (!i && !needflags)
+	return;
+    CLOBBER_SHRL;
+    r=rmw(r,2,2);
+    raw_shrl_w_ri(r,i);
+    unlock2(r);
+}
+MENDFUNC(2,shrl_w_ri,(RW2 r, IMM i))
+
+MIDFUNC(2,shrl_b_ri,(RW1 r, IMM i))
+{
+    if (!i && !needflags)
+	return;
+    CLOBBER_SHRL;
+    r=rmw(r,1,1);
+    raw_shrl_b_ri(r,i);
+    unlock2(r);
+}
+MENDFUNC(2,shrl_b_ri,(RW1 r, IMM i))
+
+MIDFUNC(2,shra_l_ri,(RW4 r, IMM i))
+{
+    if (!i && !needflags)
+	return;
+    CLOBBER_SHRA;
+    r=rmw(r,4,4);
+    raw_shra_l_ri(r,i);
+    unlock2(r);
+}
+MENDFUNC(2,shra_l_ri,(RW4 r, IMM i))
+
+MIDFUNC(2,shra_w_ri,(RW2 r, IMM i))
+{
+    if (!i && !needflags)
+	return;
+    CLOBBER_SHRA;
+    r=rmw(r,2,2);
+    raw_shra_w_ri(r,i);
+    unlock2(r);
+}
+MENDFUNC(2,shra_w_ri,(RW2 r, IMM i))
+
+MIDFUNC(2,shra_b_ri,(RW1 r, IMM i))
+{
+    if (!i && !needflags)
+	return;
+    CLOBBER_SHRA;
+    r=rmw(r,1,1);
+    raw_shra_b_ri(r,i);
+    unlock2(r);
+}
+MENDFUNC(2,shra_b_ri,(RW1 r, IMM i))
+
+MIDFUNC(2,shra_l_rr,(RW4 d, R1 r)) 
+{ 
+    if (isconst(r)) {
+	COMPCALL(shra_l_ri)(d,(uae_u8)live.state[r].val);
+	return;
+    }
+    CLOBBER_SHRA;
+    r=readreg_specific(r,1,SHIFTCOUNT_NREG);
+    d=rmw(d,4,4);
+    Dif (r!=1) {
+	write_log("Illegal register %d in raw_rol_b\n",r);
+	abort();
+    }
+    raw_shra_l_rr(d,r) ;
+    unlock2(r);
+    unlock2(d);
+}
+MENDFUNC(2,shra_l_rr,(RW4 d, R1 r)) 
+
+MIDFUNC(2,shra_w_rr,(RW2 d, R1 r)) 
+{ /* Can only do this with r==1, i.e. cl */
+  
+    if (isconst(r)) {
+	COMPCALL(shra_w_ri)(d,(uae_u8)live.state[r].val);
+	return;
+    }
+    CLOBBER_SHRA;
+    r=readreg_specific(r,1,SHIFTCOUNT_NREG);
+    d=rmw(d,2,2);
+    Dif (r!=1) {
+	write_log("Illegal register %d in raw_shra_b\n",r);
+	abort();
+    }
+    raw_shra_w_rr(d,r) ;
+    unlock2(r);
+    unlock2(d);
+}
+MENDFUNC(2,shra_w_rr,(RW2 d, R1 r)) 
+
+MIDFUNC(2,shra_b_rr,(RW1 d, R1 r)) 
+{ /* Can only do this with r==1, i.e. cl */
+  
+    if (isconst(r)) {
+	COMPCALL(shra_b_ri)(d,(uae_u8)live.state[r].val);
+	return;
+    }
+
+    CLOBBER_SHRA;
+    r=readreg_specific(r,1,SHIFTCOUNT_NREG);
+    d=rmw(d,1,1);
+    Dif (r!=1) {
+	write_log("Illegal register %d in raw_shra_b\n",r);
+	abort();
+    }
+    raw_shra_b_rr(d,r) ;
+    unlock2(r);
+    unlock2(d);
+}
+MENDFUNC(2,shra_b_rr,(RW1 d, R1 r)) 
+
+
+MIDFUNC(2,setcc,(W1 d, IMM cc))
+{
+    CLOBBER_SETCC;
+    d=writereg(d,1);
+    raw_setcc(d,cc);
+    unlock2(d);
+}
+MENDFUNC(2,setcc,(W1 d, IMM cc))
+
+MIDFUNC(2,setcc_m,(IMM d, IMM cc))
+{
+    CLOBBER_SETCC;
+    raw_setcc_m(d,cc);
+}
+MENDFUNC(2,setcc_m,(IMM d, IMM cc))
+
+MIDFUNC(3,cmov_b_rr,(RW1 d, R1 s, IMM cc))
+{
+    if (d==s)
+	return;
+    CLOBBER_CMOV;
+    s=readreg(s,1);
+    d=rmw(d,1,1);
+    raw_cmov_b_rr(d,s,cc);
+    unlock2(s);
+    unlock2(d);
+}
+MENDFUNC(3,cmov_b_rr,(RW1 d, R1 s, IMM cc))
+
+MIDFUNC(3,cmov_w_rr,(RW2 d, R2 s, IMM cc))
+{
+    if (d==s)
+	return;
+    CLOBBER_CMOV;
+    s=readreg(s,2);
+    d=rmw(d,2,2);
+    raw_cmov_w_rr(d,s,cc);
+    unlock2(s);
+    unlock2(d);
+}
+MENDFUNC(3,cmov_w_rr,(RW2 d, R2 s, IMM cc))
+
+MIDFUNC(3,cmov_l_rr,(RW4 d, R4 s, IMM cc))
+{
+    if (d==s)
+	return;
+    CLOBBER_CMOV;
+    s=readreg(s,4);
+    d=rmw(d,4,4);
+    raw_cmov_l_rr(d,s,cc);
+    unlock2(s);
+    unlock2(d);
+}
+MENDFUNC(3,cmov_l_rr,(RW4 d, R4 s, IMM cc))
+
+MIDFUNC(3,cmov_l_rm,(RW4 d, IMM s, IMM cc))
+{
+    CLOBBER_CMOV;
+    d=rmw(d,4,4);
+    raw_cmov_l_rm(d,s,cc);
+    unlock2(d);
+}
+MENDFUNC(3,cmov_l_rm,(RW4 d, IMM s, IMM cc))
+
+MIDFUNC(2,bsf_l_rr,(W4 d, W4 s))
+{
+    CLOBBER_BSF;
+    s = readreg(s, 4);
+    d = writereg(d, 4);
+    raw_bsf_l_rr(d, s);
+    unlock2(s);
+    unlock2(d);
+}
+MENDFUNC(2,bsf_l_rr,(W4 d, W4 s))
+
+/* Set the Z flag depending on the value in s. Note that the
+   value has to be 0 or -1 (or, more precisely, for non-zero
+   values, bit 14 must be set)! */
+MIDFUNC(2,simulate_bsf,(W4 tmp, RW4 s))
+{
+    CLOBBER_BSF;
+    s=rmw_specific(s,4,4,FLAG_NREG3);
+    tmp=writereg(tmp,4);
+    raw_flags_set_zero(s, tmp);
+    unlock2(tmp);
+    unlock2(s);
+}
+MENDFUNC(2,simulate_bsf,(W4 tmp, RW4 s))
+
+MIDFUNC(2,imul_32_32,(RW4 d, R4 s))
+{
+    CLOBBER_MUL;
+    s=readreg(s,4);
+    d=rmw(d,4,4);
+    raw_imul_32_32(d,s);
+    unlock2(s);
+    unlock2(d);
+}
+MENDFUNC(2,imul_32_32,(RW4 d, R4 s))
+
+MIDFUNC(2,imul_64_32,(RW4 d, RW4 s))
+{
+    CLOBBER_MUL;
+    s=rmw_specific(s,4,4,MUL_NREG2);
+    d=rmw_specific(d,4,4,MUL_NREG1);
+    raw_imul_64_32(d,s);
+    unlock2(s);
+    unlock2(d);
+}
+MENDFUNC(2,imul_64_32,(RW4 d, RW4 s))
+
+MIDFUNC(2,mul_64_32,(RW4 d, RW4 s))
+{
+    CLOBBER_MUL;
+    s=rmw_specific(s,4,4,MUL_NREG2);
+    d=rmw_specific(d,4,4,MUL_NREG1);
+    raw_mul_64_32(d,s);
+    unlock2(s);
+    unlock2(d);
+}
+MENDFUNC(2,mul_64_32,(RW4 d, RW4 s))
+
+MIDFUNC(2,mul_32_32,(RW4 d, R4 s))
+{
+    CLOBBER_MUL;
+    s=readreg(s,4);
+    d=rmw(d,4,4);
+    raw_mul_32_32(d,s);
+    unlock2(s);
+    unlock2(d);
+}
+MENDFUNC(2,mul_32_32,(RW4 d, R4 s))
+
+#if SIZEOF_VOID_P == 8
+MIDFUNC(2,sign_extend_32_rr,(W4 d, R2 s))
+{
+    int isrmw;
+
+    if (isconst(s)) {
+	set_const(d,(uae_s32)live.state[s].val);
+	return;
+    }
+
+    CLOBBER_SE32;
+    isrmw=(s==d);
+    if (!isrmw) {
+	s=readreg(s,4);
+	d=writereg(d,4);
+    }
+    else {  /* If we try to lock this twice, with different sizes, we
+	       are int trouble! */
+	s=d=rmw(s,4,4);
+    }
+    raw_sign_extend_32_rr(d,s);
+    if (!isrmw) {
+	unlock2(d);
+	unlock2(s);
+    }
+    else {
+	unlock2(s);
+    }
+}
+MENDFUNC(2,sign_extend_32_rr,(W4 d, R2 s))
+#endif
+
+MIDFUNC(2,sign_extend_16_rr,(W4 d, R2 s))
+{
+    int isrmw;
+
+    if (isconst(s)) {
+	set_const(d,(uae_s32)(uae_s16)live.state[s].val);
+	return;
+    }
+
+    CLOBBER_SE16;
+    isrmw=(s==d);
+    if (!isrmw) {
+	s=readreg(s,2);
+	d=writereg(d,4);
+    }
+    else {  /* If we try to lock this twice, with different sizes, we
+	       are int trouble! */
+	s=d=rmw(s,4,2);
+    }
+    raw_sign_extend_16_rr(d,s);
+    if (!isrmw) {
+	unlock2(d);
+	unlock2(s);
+    }
+    else {
+	unlock2(s);
+    }
+}
+MENDFUNC(2,sign_extend_16_rr,(W4 d, R2 s))
+
+MIDFUNC(2,sign_extend_8_rr,(W4 d, R1 s))
+{
+    int isrmw;
+
+    if (isconst(s)) {
+	set_const(d,(uae_s32)(uae_s8)live.state[s].val);
+	return;
+    }
+
+    isrmw=(s==d);
+    CLOBBER_SE8;
+    if (!isrmw) {
+	s=readreg(s,1);
+	d=writereg(d,4);
+    }
+    else {  /* If we try to lock this twice, with different sizes, we
+	       are int trouble! */
+	s=d=rmw(s,4,1);
+    }
+  
+    raw_sign_extend_8_rr(d,s);
+
+    if (!isrmw) {
+	unlock2(d);
+	unlock2(s);
+    }
+    else {
+	unlock2(s);
+    }
+}
+MENDFUNC(2,sign_extend_8_rr,(W4 d, R1 s))
+
+
+MIDFUNC(2,zero_extend_16_rr,(W4 d, R2 s))
+{
+    int isrmw;
+
+    if (isconst(s)) {
+	set_const(d,(uae_u32)(uae_u16)live.state[s].val);
+	return;
+    }
+
+    isrmw=(s==d);
+    CLOBBER_ZE16;
+    if (!isrmw) {
+	s=readreg(s,2);
+	d=writereg(d,4);
+    }
+    else {  /* If we try to lock this twice, with different sizes, we
+	       are int trouble! */
+	s=d=rmw(s,4,2);
+    }
+    raw_zero_extend_16_rr(d,s);
+    if (!isrmw) {
+	unlock2(d);
+	unlock2(s);
+    }
+    else {
+	unlock2(s);
+    }
+}
+MENDFUNC(2,zero_extend_16_rr,(W4 d, R2 s))
+
+MIDFUNC(2,zero_extend_8_rr,(W4 d, R1 s))
+{
+    int isrmw;
+    if (isconst(s)) {
+	set_const(d,(uae_u32)(uae_u8)live.state[s].val);
+	return;
+    }
+
+    isrmw=(s==d);
+    CLOBBER_ZE8;
+    if (!isrmw) {
+	s=readreg(s,1);
+	d=writereg(d,4);
+    }
+    else {  /* If we try to lock this twice, with different sizes, we
+	       are int trouble! */
+	s=d=rmw(s,4,1);
+    }
+  
+    raw_zero_extend_8_rr(d,s);
+
+    if (!isrmw) {
+	unlock2(d);
+	unlock2(s);
+    }
+    else {
+	unlock2(s);
+    }
+}
+MENDFUNC(2,zero_extend_8_rr,(W4 d, R1 s))
+
+MIDFUNC(2,mov_b_rr,(W1 d, R1 s))
+{
+    if (d==s)
+	return;
+    if (isconst(s)) {
+	COMPCALL(mov_b_ri)(d,(uae_u8)live.state[s].val);
+	return;
+    }
+
+    CLOBBER_MOV;
+    s=readreg(s,1);
+    d=writereg(d,1);
+    raw_mov_b_rr(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,mov_b_rr,(W1 d, R1 s))
+
+MIDFUNC(2,mov_w_rr,(W2 d, R2 s))
+{
+    if (d==s)
+	return;
+    if (isconst(s)) {
+	COMPCALL(mov_w_ri)(d,(uae_u16)live.state[s].val);
+	return;
+    }
+
+    CLOBBER_MOV;
+    s=readreg(s,2);
+    d=writereg(d,2);
+    raw_mov_w_rr(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,mov_w_rr,(W2 d, R2 s))
+
+
+MIDFUNC(4,mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor))
+{
+    CLOBBER_MOV;
+    baser=readreg(baser,4);
+    index=readreg(index,4);
+    d=writereg(d,4);
+
+    raw_mov_l_rrm_indexed(d,baser,index,factor);
+    unlock2(d);
+    unlock2(baser);
+    unlock2(index);
+}
+MENDFUNC(4,mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor))
+
+MIDFUNC(4,mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor))
+{
+    CLOBBER_MOV;
+    baser=readreg(baser,4);
+    index=readreg(index,4);
+    d=writereg(d,2);
+
+    raw_mov_w_rrm_indexed(d,baser,index,factor);
+    unlock2(d);
+    unlock2(baser);
+    unlock2(index);
+}
+MENDFUNC(4,mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor))
+
+MIDFUNC(4,mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor))
+{
+    CLOBBER_MOV;
+    baser=readreg(baser,4);
+    index=readreg(index,4);
+    d=writereg(d,1);
+
+    raw_mov_b_rrm_indexed(d,baser,index,factor);
+
+    unlock2(d);
+    unlock2(baser);
+    unlock2(index);
+}
+MENDFUNC(4,mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor))
+
+
+MIDFUNC(4,mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s))
+{
+    CLOBBER_MOV;
+    baser=readreg(baser,4);
+    index=readreg(index,4);
+    s=readreg(s,4);
+
+    Dif (baser==s || index==s) 
+	abort();
+
+
+    raw_mov_l_mrr_indexed(baser,index,factor,s);
+    unlock2(s);
+    unlock2(baser);
+    unlock2(index);
+}
+MENDFUNC(4,mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s))
+
+MIDFUNC(4,mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s))
+{
+    CLOBBER_MOV;
+    baser=readreg(baser,4);
+    index=readreg(index,4);
+    s=readreg(s,2);
+
+    raw_mov_w_mrr_indexed(baser,index,factor,s);
+    unlock2(s);
+    unlock2(baser);
+    unlock2(index);
+}
+MENDFUNC(4,mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s))
+
+MIDFUNC(4,mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s))
+{
+    CLOBBER_MOV;
+    s=readreg(s,1);
+    baser=readreg(baser,4);
+    index=readreg(index,4);
+
+    raw_mov_b_mrr_indexed(baser,index,factor,s);
+    unlock2(s);
+    unlock2(baser);
+    unlock2(index);
+}
+MENDFUNC(4,mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s))
+
+
+MIDFUNC(5,mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s))
+{
+    int basereg=baser;
+    int indexreg=index;
+
+    CLOBBER_MOV;
+    s=readreg(s,4);
+    baser=readreg_offset(baser,4);
+    index=readreg_offset(index,4);
+
+    base+=get_offset(basereg);
+    base+=factor*get_offset(indexreg);
+
+    raw_mov_l_bmrr_indexed(base,baser,index,factor,s);
+    unlock2(s);
+    unlock2(baser);
+    unlock2(index);
+}
+MENDFUNC(5,mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s))
+
+MIDFUNC(5,mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s))
+{
+    int basereg=baser;
+    int indexreg=index;
+
+    CLOBBER_MOV;
+    s=readreg(s,2);
+    baser=readreg_offset(baser,4);
+    index=readreg_offset(index,4);
+
+    base+=get_offset(basereg);
+    base+=factor*get_offset(indexreg);
+
+    raw_mov_w_bmrr_indexed(base,baser,index,factor,s);
+    unlock2(s);
+    unlock2(baser);
+    unlock2(index);
+}
+MENDFUNC(5,mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s))
+
+MIDFUNC(5,mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s))
+{
+    int basereg=baser;
+    int indexreg=index;
+
+    CLOBBER_MOV;
+    s=readreg(s,1);
+    baser=readreg_offset(baser,4);
+    index=readreg_offset(index,4);
+
+    base+=get_offset(basereg);
+    base+=factor*get_offset(indexreg);
+
+    raw_mov_b_bmrr_indexed(base,baser,index,factor,s);
+    unlock2(s);
+    unlock2(baser);
+    unlock2(index);
+}
+MENDFUNC(5,mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s))
+
+
+
+/* Read a long from base+baser+factor*index */
+MIDFUNC(5,mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor))
+{
+    int basereg=baser;
+    int indexreg=index;
+
+    CLOBBER_MOV;
+    baser=readreg_offset(baser,4);
+    index=readreg_offset(index,4);
+    base+=get_offset(basereg);
+    base+=factor*get_offset(indexreg);    
+    d=writereg(d,4);
+    raw_mov_l_brrm_indexed(d,base,baser,index,factor);
+    unlock2(d);
+    unlock2(baser);
+    unlock2(index);
+}
+MENDFUNC(5,mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor))
+
+
+MIDFUNC(5,mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor))
+{
+    int basereg=baser;
+    int indexreg=index;
+
+    CLOBBER_MOV;
+    remove_offset(d,-1);
+    baser=readreg_offset(baser,4);
+    index=readreg_offset(index,4);
+    base+=get_offset(basereg);
+    base+=factor*get_offset(indexreg);    
+    d=writereg(d,2);
+    raw_mov_w_brrm_indexed(d,base,baser,index,factor);
+    unlock2(d);
+    unlock2(baser);
+    unlock2(index);
+}
+MENDFUNC(5,mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor))
+
+
+MIDFUNC(5,mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor))
+{
+    int basereg=baser;
+    int indexreg=index;
+
+    CLOBBER_MOV;
+    remove_offset(d,-1);
+    baser=readreg_offset(baser,4);
+    index=readreg_offset(index,4);
+    base+=get_offset(basereg);
+    base+=factor*get_offset(indexreg);    
+    d=writereg(d,1);
+    raw_mov_b_brrm_indexed(d,base,baser,index,factor);
+    unlock2(d);
+    unlock2(baser);
+    unlock2(index);
+}
+MENDFUNC(5,mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor))
+
+/* Read a long from base+factor*index */
+MIDFUNC(4,mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor))
+{
+    int indexreg=index;
+
+    if (isconst(index)) {
+	COMPCALL(mov_l_rm)(d,base+factor*live.state[index].val);
+	return;
+    }
+
+    CLOBBER_MOV;
+    index=readreg_offset(index,4);
+    base+=get_offset(indexreg)*factor;
+    d=writereg(d,4);
+
+    raw_mov_l_rm_indexed(d,base,index,factor);
+    unlock2(index);
+    unlock2(d);
+}
+MENDFUNC(4,mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor))
+
+
+/* read the long at the address contained in s+offset and store in d */
+MIDFUNC(3,mov_l_rR,(W4 d, R4 s, IMM offset))
+{
+    if (isconst(s)) {
+	COMPCALL(mov_l_rm)(d,live.state[s].val+offset);
+	return;
+    }
+    CLOBBER_MOV;
+    s=readreg(s,4);
+    d=writereg(d,4);
+
+    raw_mov_l_rR(d,s,offset);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(3,mov_l_rR,(W4 d, R4 s, IMM offset))
+
+/* read the word at the address contained in s+offset and store in d */
+MIDFUNC(3,mov_w_rR,(W2 d, R4 s, IMM offset))
+{
+    if (isconst(s)) {
+	COMPCALL(mov_w_rm)(d,live.state[s].val+offset);
+	return;
+    }
+    CLOBBER_MOV;
+    s=readreg(s,4);
+    d=writereg(d,2);
+
+    raw_mov_w_rR(d,s,offset);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(3,mov_w_rR,(W2 d, R4 s, IMM offset))
+
+/* read the word at the address contained in s+offset and store in d */
+MIDFUNC(3,mov_b_rR,(W1 d, R4 s, IMM offset))
+{
+    if (isconst(s)) {
+	COMPCALL(mov_b_rm)(d,live.state[s].val+offset);
+	return;
+    }
+    CLOBBER_MOV;
+    s=readreg(s,4);
+    d=writereg(d,1);
+
+    raw_mov_b_rR(d,s,offset);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(3,mov_b_rR,(W1 d, R4 s, IMM offset))
+
+/* read the long at the address contained in s+offset and store in d */
+MIDFUNC(3,mov_l_brR,(W4 d, R4 s, IMM offset))
+{
+    int sreg=s;
+    if (isconst(s)) {
+	COMPCALL(mov_l_rm)(d,live.state[s].val+offset);
+	return;
+    }
+    CLOBBER_MOV;
+    s=readreg_offset(s,4);
+    offset+=get_offset(sreg);
+    d=writereg(d,4);
+    
+    raw_mov_l_brR(d,s,offset);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(3,mov_l_brR,(W4 d, R4 s, IMM offset))
+
+/* read the word at the address contained in s+offset and store in d */
+MIDFUNC(3,mov_w_brR,(W2 d, R4 s, IMM offset))
+{
+    int sreg=s;
+    if (isconst(s)) {
+	COMPCALL(mov_w_rm)(d,live.state[s].val+offset);
+	return;
+    }
+    CLOBBER_MOV;
+    remove_offset(d,-1);
+    s=readreg_offset(s,4);
+    offset+=get_offset(sreg);
+    d=writereg(d,2);
+
+    raw_mov_w_brR(d,s,offset);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(3,mov_w_brR,(W2 d, R4 s, IMM offset))
+
+/* read the word at the address contained in s+offset and store in d */
+MIDFUNC(3,mov_b_brR,(W1 d, R4 s, IMM offset))
+{
+    int sreg=s;
+    if (isconst(s)) {
+	COMPCALL(mov_b_rm)(d,live.state[s].val+offset);
+	return;
+    }
+    CLOBBER_MOV;
+    remove_offset(d,-1);
+    s=readreg_offset(s,4);
+    offset+=get_offset(sreg);
+    d=writereg(d,1);
+
+    raw_mov_b_brR(d,s,offset);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(3,mov_b_brR,(W1 d, R4 s, IMM offset))
+
+MIDFUNC(3,mov_l_Ri,(R4 d, IMM i, IMM offset))
+{
+    int dreg=d;
+    if (isconst(d)) {
+	COMPCALL(mov_l_mi)(live.state[d].val+offset,i);
+	return;
+    }
+
+    CLOBBER_MOV;
+    d=readreg_offset(d,4);
+    offset+=get_offset(dreg);
+    raw_mov_l_Ri(d,i,offset);
+    unlock2(d);
+}
+MENDFUNC(3,mov_l_Ri,(R4 d, IMM i, IMM offset))
+
+MIDFUNC(3,mov_w_Ri,(R4 d, IMM i, IMM offset))
+{
+    int dreg=d;
+    if (isconst(d)) {
+	COMPCALL(mov_w_mi)(live.state[d].val+offset,i);
+	return;
+    }
+
+    CLOBBER_MOV;
+    d=readreg_offset(d,4);
+    offset+=get_offset(dreg);
+    raw_mov_w_Ri(d,i,offset);
+    unlock2(d);
+}
+MENDFUNC(3,mov_w_Ri,(R4 d, IMM i, IMM offset))
+
+MIDFUNC(3,mov_b_Ri,(R4 d, IMM i, IMM offset))
+{
+    int dreg=d;
+    if (isconst(d)) {
+	COMPCALL(mov_b_mi)(live.state[d].val+offset,i);
+	return;
+    }
+
+    CLOBBER_MOV;
+    d=readreg_offset(d,4);
+    offset+=get_offset(dreg);
+    raw_mov_b_Ri(d,i,offset);
+    unlock2(d);
+}
+MENDFUNC(3,mov_b_Ri,(R4 d, IMM i, IMM offset))
+
+     /* Warning! OFFSET is byte sized only! */
+MIDFUNC(3,mov_l_Rr,(R4 d, R4 s, IMM offset))
+{
+    if (isconst(d)) {
+	COMPCALL(mov_l_mr)(live.state[d].val+offset,s);
+	return;
+    }
+    if (isconst(s)) {
+	COMPCALL(mov_l_Ri)(d,live.state[s].val,offset);
+	return;
+    }
+
+    CLOBBER_MOV;
+    s=readreg(s,4);
+    d=readreg(d,4);
+
+    raw_mov_l_Rr(d,s,offset);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(3,mov_l_Rr,(R4 d, R4 s, IMM offset))
+
+MIDFUNC(3,mov_w_Rr,(R4 d, R2 s, IMM offset))
+{
+    if (isconst(d)) {
+	COMPCALL(mov_w_mr)(live.state[d].val+offset,s);
+	return;
+    }
+    if (isconst(s)) {
+	COMPCALL(mov_w_Ri)(d,(uae_u16)live.state[s].val,offset);
+	return;
+    }
+
+    CLOBBER_MOV;
+    s=readreg(s,2);
+    d=readreg(d,4);
+    raw_mov_w_Rr(d,s,offset);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(3,mov_w_Rr,(R4 d, R2 s, IMM offset))
+
+MIDFUNC(3,mov_b_Rr,(R4 d, R1 s, IMM offset))
+{
+    if (isconst(d)) {
+	COMPCALL(mov_b_mr)(live.state[d].val+offset,s);
+	return;
+    }
+    if (isconst(s)) {
+	COMPCALL(mov_b_Ri)(d,(uae_u8)live.state[s].val,offset);
+	return;
+    }
+
+    CLOBBER_MOV;
+    s=readreg(s,1);
+    d=readreg(d,4);
+    raw_mov_b_Rr(d,s,offset);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(3,mov_b_Rr,(R4 d, R1 s, IMM offset))
+
+MIDFUNC(3,lea_l_brr,(W4 d, R4 s, IMM offset))
+{
+    if (isconst(s)) {
+	COMPCALL(mov_l_ri)(d,live.state[s].val+offset);
+	return;
+    }
+#if USE_OFFSET
+    if (d==s) {
+	add_offset(d,offset);
+	return;
+    }
+#endif
+    CLOBBER_LEA;
+    s=readreg(s,4);
+    d=writereg(d,4);
+    raw_lea_l_brr(d,s,offset);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(3,lea_l_brr,(W4 d, R4 s, IMM offset))
+
+MIDFUNC(5,lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
+{
+    if (!offset) {
+	COMPCALL(lea_l_rr_indexed)(d,s,index,factor);
+	return;
+    }
+    CLOBBER_LEA;
+    s=readreg(s,4);
+    index=readreg(index,4);
+    d=writereg(d,4);
+
+    raw_lea_l_brr_indexed(d,s,index,factor,offset);
+    unlock2(d);
+    unlock2(index);
+    unlock2(s);
+}
+MENDFUNC(5,lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
+
+MIDFUNC(4,lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor))
+{
+    CLOBBER_LEA;
+    s=readreg(s,4);
+    index=readreg(index,4);
+    d=writereg(d,4);
+
+    raw_lea_l_rr_indexed(d,s,index,factor);
+    unlock2(d);
+    unlock2(index);
+    unlock2(s);
+}
+MENDFUNC(4,lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor))
+
+/* write d to the long at the address contained in s+offset */
+MIDFUNC(3,mov_l_bRr,(R4 d, R4 s, IMM offset))
+{
+    int dreg=d;
+    if (isconst(d)) {
+	COMPCALL(mov_l_mr)(live.state[d].val+offset,s);
+	return;
+    }
+
+    CLOBBER_MOV;
+    s=readreg(s,4);
+    d=readreg_offset(d,4);
+    offset+=get_offset(dreg);
+
+    raw_mov_l_bRr(d,s,offset);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(3,mov_l_bRr,(R4 d, R4 s, IMM offset))
+
+/* write the word at the address contained in s+offset and store in d */
+MIDFUNC(3,mov_w_bRr,(R4 d, R2 s, IMM offset))
+{
+    int dreg=d;
+
+    if (isconst(d)) {
+	COMPCALL(mov_w_mr)(live.state[d].val+offset,s);
+	return;
+    }
+
+    CLOBBER_MOV;
+    s=readreg(s,2);
+    d=readreg_offset(d,4);
+    offset+=get_offset(dreg);
+    raw_mov_w_bRr(d,s,offset);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(3,mov_w_bRr,(R4 d, R2 s, IMM offset))
+
+MIDFUNC(3,mov_b_bRr,(R4 d, R1 s, IMM offset))
+{
+    int dreg=d;
+    if (isconst(d)) {
+	COMPCALL(mov_b_mr)(live.state[d].val+offset,s);
+	return;
+    }
+
+    CLOBBER_MOV;
+    s=readreg(s,1);
+    d=readreg_offset(d,4);
+    offset+=get_offset(dreg);
+    raw_mov_b_bRr(d,s,offset);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(3,mov_b_bRr,(R4 d, R1 s, IMM offset))
+
+MIDFUNC(1,bswap_32,(RW4 r))
+{
+    int reg=r;
+
+    if (isconst(r)) {
+	uae_u32 oldv=live.state[r].val;
+	live.state[r].val=reverse32(oldv);
+	return;
+    }
+    
+    CLOBBER_SW32;
+    r=rmw(r,4,4);  
+    raw_bswap_32(r);
+    unlock2(r);
+}
+MENDFUNC(1,bswap_32,(RW4 r))
+
+MIDFUNC(1,bswap_16,(RW2 r))
+{
+    if (isconst(r)) {
+	uae_u32 oldv=live.state[r].val;
+	live.state[r].val=((oldv>>8)&0xff) | ((oldv<<8)&0xff00) |
+	    (oldv&0xffff0000);
+	return;
+    }
+
+    CLOBBER_SW16;
+    r=rmw(r,2,2);
+  
+    raw_bswap_16(r);
+    unlock2(r);
+}
+MENDFUNC(1,bswap_16,(RW2 r))
+
+
+
+MIDFUNC(2,mov_l_rr,(W4 d, R4 s))
+{
+    int olds;
+
+    if (d==s) { /* How pointless! */
+	return;
+    }
+    if (isconst(s)) {
+	COMPCALL(mov_l_ri)(d,live.state[s].val);
+	return;
+    }
+    olds=s;
+    disassociate(d);
+    s=readreg_offset(s,4);
+    live.state[d].realreg=s;
+    live.state[d].realind=live.nat[s].nholds;
+    live.state[d].val=live.state[olds].val;
+    live.state[d].validsize=4;
+    live.state[d].dirtysize=4;
+    set_status(d,DIRTY);
+
+    live.nat[s].holds[live.nat[s].nholds]=d;
+    live.nat[s].nholds++;
+    log_clobberreg(d);
+    /* write_log("Added %d to nreg %d(%d), now holds %d regs\n",
+       d,s,live.state[d].realind,live.nat[s].nholds); */
+    unlock2(s);
+}
+MENDFUNC(2,mov_l_rr,(W4 d, R4 s))
+
+MIDFUNC(2,mov_l_mr,(IMM d, R4 s))
+{
+    if (isconst(s)) {
+	COMPCALL(mov_l_mi)(d,live.state[s].val);
+	return;
+    }
+    CLOBBER_MOV;
+    s=readreg(s,4);
+
+    raw_mov_l_mr(d,s);
+    unlock2(s);
+}
+MENDFUNC(2,mov_l_mr,(IMM d, R4 s))
+
+
+MIDFUNC(2,mov_w_mr,(IMM d, R2 s))
+{
+    if (isconst(s)) {
+	COMPCALL(mov_w_mi)(d,(uae_u16)live.state[s].val);
+	return;
+    }
+    CLOBBER_MOV;
+    s=readreg(s,2);
+
+    raw_mov_w_mr(d,s);
+    unlock2(s);
+}
+MENDFUNC(2,mov_w_mr,(IMM d, R2 s))
+
+MIDFUNC(2,mov_w_rm,(W2 d, IMM s))
+{
+    CLOBBER_MOV;
+    d=writereg(d,2);
+
+    raw_mov_w_rm(d,s);
+    unlock2(d);
+}
+MENDFUNC(2,mov_w_rm,(W2 d, IMM s))
+
+MIDFUNC(2,mov_b_mr,(IMM d, R1 s))
+{
+    if (isconst(s)) {
+	COMPCALL(mov_b_mi)(d,(uae_u8)live.state[s].val);
+	return;
+    }
+
+    CLOBBER_MOV;
+    s=readreg(s,1);
+
+    raw_mov_b_mr(d,s);
+    unlock2(s);
+}
+MENDFUNC(2,mov_b_mr,(IMM d, R1 s))
+
+MIDFUNC(2,mov_b_rm,(W1 d, IMM s))
+{
+    CLOBBER_MOV;
+    d=writereg(d,1);
+
+    raw_mov_b_rm(d,s);
+    unlock2(d);
+}
+MENDFUNC(2,mov_b_rm,(W1 d, IMM s))
+
+MIDFUNC(2,mov_l_ri,(W4 d, IMM s))
+{
+    set_const(d,s);
+    return;
+}
+MENDFUNC(2,mov_l_ri,(W4 d, IMM s))
+
+MIDFUNC(2,mov_w_ri,(W2 d, IMM s))
+{
+    CLOBBER_MOV;
+    d=writereg(d,2);
+
+    raw_mov_w_ri(d,s);
+    unlock2(d);
+}
+MENDFUNC(2,mov_w_ri,(W2 d, IMM s))
+
+MIDFUNC(2,mov_b_ri,(W1 d, IMM s))
+{
+    CLOBBER_MOV;
+    d=writereg(d,1);
+
+    raw_mov_b_ri(d,s);
+    unlock2(d);
+}
+MENDFUNC(2,mov_b_ri,(W1 d, IMM s))
+
+
+MIDFUNC(2,add_l_mi,(IMM d, IMM s)) 
+{
+    CLOBBER_ADD;
+    raw_add_l_mi(d,s) ;
+}
+MENDFUNC(2,add_l_mi,(IMM d, IMM s)) 
+
+MIDFUNC(2,add_w_mi,(IMM d, IMM s)) 
+{
+    CLOBBER_ADD;
+    raw_add_w_mi(d,s) ;
+}
+MENDFUNC(2,add_w_mi,(IMM d, IMM s)) 
+
+MIDFUNC(2,add_b_mi,(IMM d, IMM s)) 
+{
+    CLOBBER_ADD;
+    raw_add_b_mi(d,s) ;
+}
+MENDFUNC(2,add_b_mi,(IMM d, IMM s)) 
+
+
+MIDFUNC(2,test_l_ri,(R4 d, IMM i))
+{
+    CLOBBER_TEST;
+    d=readreg(d,4);
+
+    raw_test_l_ri(d,i);
+    unlock2(d);
+}
+MENDFUNC(2,test_l_ri,(R4 d, IMM i))
+
+MIDFUNC(2,test_l_rr,(R4 d, R4 s))
+{
+    CLOBBER_TEST;
+    d=readreg(d,4);
+    s=readreg(s,4);
+
+    raw_test_l_rr(d,s);;
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,test_l_rr,(R4 d, R4 s))
+
+MIDFUNC(2,test_w_rr,(R2 d, R2 s))
+{
+    CLOBBER_TEST;
+    d=readreg(d,2);
+    s=readreg(s,2);
+
+    raw_test_w_rr(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,test_w_rr,(R2 d, R2 s))
+
+MIDFUNC(2,test_b_rr,(R1 d, R1 s))
+{
+    CLOBBER_TEST;
+    d=readreg(d,1);
+    s=readreg(s,1);
+
+    raw_test_b_rr(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,test_b_rr,(R1 d, R1 s))
+
+
+MIDFUNC(2,and_l_ri,(RW4 d, IMM i))
+{
+	if (isconst(d) && !needflags) {
+		live.state[d].val &= i;
+		return;
+	}
+
+    CLOBBER_AND;
+    d=rmw(d,4,4);
+
+    raw_and_l_ri(d,i);
+    unlock2(d);
+}
+MENDFUNC(2,and_l_ri,(RW4 d, IMM i))
+
+MIDFUNC(2,and_l,(RW4 d, R4 s))
+{
+    CLOBBER_AND;
+    s=readreg(s,4);
+    d=rmw(d,4,4);
+
+    raw_and_l(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,and_l,(RW4 d, R4 s))
+
+MIDFUNC(2,and_w,(RW2 d, R2 s))
+{
+    CLOBBER_AND;
+    s=readreg(s,2);
+    d=rmw(d,2,2);
+
+    raw_and_w(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,and_w,(RW2 d, R2 s))
+
+MIDFUNC(2,and_b,(RW1 d, R1 s))
+{
+    CLOBBER_AND;
+    s=readreg(s,1);
+    d=rmw(d,1,1);
+
+    raw_and_b(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,and_b,(RW1 d, R1 s))
+
+// gb-- used for making an fpcr value in compemu_fpp.cpp
+MIDFUNC(2,or_l_rm,(RW4 d, IMM s))
+{
+    CLOBBER_OR;
+    d=rmw(d,4,4);
+	
+    raw_or_l_rm(d,s);
+    unlock2(d);
+}
+MENDFUNC(2,or_l_rm,(RW4 d, IMM s))
+
+MIDFUNC(2,or_l_ri,(RW4 d, IMM i))
+{
+    if (isconst(d) && !needflags) {
+	live.state[d].val|=i;
+	return;
+    }
+    CLOBBER_OR;
+    d=rmw(d,4,4);
+
+    raw_or_l_ri(d,i);
+    unlock2(d);
+}
+MENDFUNC(2,or_l_ri,(RW4 d, IMM i))
+
+MIDFUNC(2,or_l,(RW4 d, R4 s))
+{
+    if (isconst(d) && isconst(s) && !needflags) {
+	live.state[d].val|=live.state[s].val;
+	return;
+    }
+    CLOBBER_OR;
+    s=readreg(s,4);
+    d=rmw(d,4,4);
+
+    raw_or_l(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,or_l,(RW4 d, R4 s))
+
+MIDFUNC(2,or_w,(RW2 d, R2 s))
+{
+    CLOBBER_OR;
+    s=readreg(s,2);
+    d=rmw(d,2,2);
+
+    raw_or_w(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,or_w,(RW2 d, R2 s))
+
+MIDFUNC(2,or_b,(RW1 d, R1 s))
+{
+    CLOBBER_OR;
+    s=readreg(s,1);
+    d=rmw(d,1,1);
+
+    raw_or_b(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,or_b,(RW1 d, R1 s))
+
+MIDFUNC(2,adc_l,(RW4 d, R4 s))
+{
+    CLOBBER_ADC;
+    s=readreg(s,4);
+    d=rmw(d,4,4);
+
+    raw_adc_l(d,s);
+
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,adc_l,(RW4 d, R4 s))
+
+MIDFUNC(2,adc_w,(RW2 d, R2 s))
+{
+    CLOBBER_ADC;
+    s=readreg(s,2);
+    d=rmw(d,2,2);
+
+    raw_adc_w(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,adc_w,(RW2 d, R2 s))
+
+MIDFUNC(2,adc_b,(RW1 d, R1 s))
+{
+    CLOBBER_ADC;
+    s=readreg(s,1);
+    d=rmw(d,1,1);
+
+    raw_adc_b(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,adc_b,(RW1 d, R1 s))
+
+MIDFUNC(2,add_l,(RW4 d, R4 s))
+{
+    if (isconst(s)) {
+	COMPCALL(add_l_ri)(d,live.state[s].val);
+	return;
+    }
+
+    CLOBBER_ADD;
+    s=readreg(s,4);
+    d=rmw(d,4,4);
+
+    raw_add_l(d,s);
+
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,add_l,(RW4 d, R4 s))
+
+MIDFUNC(2,add_w,(RW2 d, R2 s))
+{
+    if (isconst(s)) {
+	COMPCALL(add_w_ri)(d,(uae_u16)live.state[s].val);
+	return;
+    }
+
+    CLOBBER_ADD;
+    s=readreg(s,2);
+    d=rmw(d,2,2);
+
+    raw_add_w(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,add_w,(RW2 d, R2 s))
+
+MIDFUNC(2,add_b,(RW1 d, R1 s))
+{
+    if (isconst(s)) {
+	COMPCALL(add_b_ri)(d,(uae_u8)live.state[s].val);
+	return;
+    }
+
+    CLOBBER_ADD;
+    s=readreg(s,1);
+    d=rmw(d,1,1);
+
+    raw_add_b(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,add_b,(RW1 d, R1 s))
+
+MIDFUNC(2,sub_l_ri,(RW4 d, IMM i))
+{
+    if (!i && !needflags)
+	return;
+    if (isconst(d) && !needflags) {
+	live.state[d].val-=i;
+	return;
+    }
+#if USE_OFFSET 
+    if (!needflags) {
+	add_offset(d,-i);
+	return;
+    }
+#endif
+
+    CLOBBER_SUB;
+    d=rmw(d,4,4);
+
+    raw_sub_l_ri(d,i);
+    unlock2(d);
+}
+MENDFUNC(2,sub_l_ri,(RW4 d, IMM i))
+
+MIDFUNC(2,sub_w_ri,(RW2 d, IMM i))
+{
+    if (!i && !needflags)
+	return;
+
+    CLOBBER_SUB;
+    d=rmw(d,2,2);
+
+    raw_sub_w_ri(d,i);
+    unlock2(d);
+}
+MENDFUNC(2,sub_w_ri,(RW2 d, IMM i))
+
+MIDFUNC(2,sub_b_ri,(RW1 d, IMM i))
+{
+    if (!i && !needflags)
+	return;
+
+    CLOBBER_SUB;
+    d=rmw(d,1,1);
+
+    raw_sub_b_ri(d,i);
+
+    unlock2(d);
+}
+MENDFUNC(2,sub_b_ri,(RW1 d, IMM i))
+
+MIDFUNC(2,add_l_ri,(RW4 d, IMM i))
+{
+    if (!i && !needflags)
+	return;
+    if (isconst(d) && !needflags) {
+	live.state[d].val+=i;
+	return;
+    }
+#if USE_OFFSET 
+    if (!needflags) {
+	add_offset(d,i);
+	return;
+    }
+#endif
+    CLOBBER_ADD;
+    d=rmw(d,4,4);
+    raw_add_l_ri(d,i);
+    unlock2(d);
+}
+MENDFUNC(2,add_l_ri,(RW4 d, IMM i))
+
+MIDFUNC(2,add_w_ri,(RW2 d, IMM i))
+{
+    if (!i && !needflags)
+	return;
+
+    CLOBBER_ADD;
+    d=rmw(d,2,2);
+
+    raw_add_w_ri(d,i);
+    unlock2(d);
+}
+MENDFUNC(2,add_w_ri,(RW2 d, IMM i))
+
+MIDFUNC(2,add_b_ri,(RW1 d, IMM i))
+{
+    if (!i && !needflags)
+	return;
+
+    CLOBBER_ADD;
+    d=rmw(d,1,1);
+
+    raw_add_b_ri(d,i);
+
+    unlock2(d);
+}
+MENDFUNC(2,add_b_ri,(RW1 d, IMM i))
+
+MIDFUNC(2,sbb_l,(RW4 d, R4 s))
+{
+    CLOBBER_SBB;
+    s=readreg(s,4);
+    d=rmw(d,4,4);
+
+    raw_sbb_l(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,sbb_l,(RW4 d, R4 s))
+
+MIDFUNC(2,sbb_w,(RW2 d, R2 s))
+{
+    CLOBBER_SBB;
+    s=readreg(s,2);
+    d=rmw(d,2,2);
+
+    raw_sbb_w(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,sbb_w,(RW2 d, R2 s))
+
+MIDFUNC(2,sbb_b,(RW1 d, R1 s))
+{
+    CLOBBER_SBB;
+    s=readreg(s,1);
+    d=rmw(d,1,1);
+
+    raw_sbb_b(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,sbb_b,(RW1 d, R1 s))
+
+MIDFUNC(2,sub_l,(RW4 d, R4 s))
+{
+    if (isconst(s)) {
+	COMPCALL(sub_l_ri)(d,live.state[s].val);
+	return;
+    }
+
+    CLOBBER_SUB;
+    s=readreg(s,4);
+    d=rmw(d,4,4);
+
+    raw_sub_l(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,sub_l,(RW4 d, R4 s))
+
+MIDFUNC(2,sub_w,(RW2 d, R2 s))
+{
+    if (isconst(s)) {
+	COMPCALL(sub_w_ri)(d,(uae_u16)live.state[s].val);
+	return;
+    }
+
+    CLOBBER_SUB;
+    s=readreg(s,2);
+    d=rmw(d,2,2);
+
+    raw_sub_w(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,sub_w,(RW2 d, R2 s))
+
+MIDFUNC(2,sub_b,(RW1 d, R1 s))
+{
+    if (isconst(s)) {
+	COMPCALL(sub_b_ri)(d,(uae_u8)live.state[s].val);
+	return;
+    }
+
+    CLOBBER_SUB;
+    s=readreg(s,1);
+    d=rmw(d,1,1);
+
+    raw_sub_b(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,sub_b,(RW1 d, R1 s))
+
+MIDFUNC(2,cmp_l,(R4 d, R4 s))
+{
+    CLOBBER_CMP;
+    s=readreg(s,4);
+    d=readreg(d,4);
+
+    raw_cmp_l(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,cmp_l,(R4 d, R4 s))
+
+MIDFUNC(2,cmp_l_ri,(R4 r, IMM i))
+{
+    CLOBBER_CMP;
+    r=readreg(r,4);
+
+    raw_cmp_l_ri(r,i);
+    unlock2(r);
+}
+MENDFUNC(2,cmp_l_ri,(R4 r, IMM i))
+
+MIDFUNC(2,cmp_w,(R2 d, R2 s))
+{
+    CLOBBER_CMP;
+    s=readreg(s,2);
+    d=readreg(d,2);
+
+    raw_cmp_w(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,cmp_w,(R2 d, R2 s))
+
+MIDFUNC(2,cmp_b,(R1 d, R1 s))
+{
+    CLOBBER_CMP;
+    s=readreg(s,1);
+    d=readreg(d,1);
+
+    raw_cmp_b(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,cmp_b,(R1 d, R1 s))
+
+
+MIDFUNC(2,xor_l,(RW4 d, R4 s))
+{
+    CLOBBER_XOR;
+    s=readreg(s,4);
+    d=rmw(d,4,4);
+
+    raw_xor_l(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,xor_l,(RW4 d, R4 s))
+
+MIDFUNC(2,xor_w,(RW2 d, R2 s))
+{
+    CLOBBER_XOR;
+    s=readreg(s,2);
+    d=rmw(d,2,2);
+
+    raw_xor_w(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,xor_w,(RW2 d, R2 s))
+
+MIDFUNC(2,xor_b,(RW1 d, R1 s))
+{
+    CLOBBER_XOR;
+    s=readreg(s,1);
+    d=rmw(d,1,1);
+
+    raw_xor_b(d,s);
+    unlock2(d);
+    unlock2(s);
+}
+MENDFUNC(2,xor_b,(RW1 d, R1 s))
+
+MIDFUNC(5,call_r_11,(W4 out1, R4 r, R4 in1, IMM osize, IMM isize))
+{
+    clobber_flags();
+    remove_all_offsets();
+    if (osize==4) {
+	if (out1!=in1 && out1!=r) {
+	    COMPCALL(forget_about)(out1);
+	}
+    }
+    else {
+	tomem_c(out1);
+    }
+
+    in1=readreg_specific(in1,isize,REG_PAR1);
+    r=readreg(r,4);
+    prepare_for_call_1();  /* This should ensure that there won't be
+			      any need for swapping nregs in prepare_for_call_2
+			   */
+#if USE_NORMAL_CALLING_CONVENTION
+    raw_push_l_r(in1);
+#endif
+    unlock2(in1);
+    unlock2(r);
+
+    prepare_for_call_2();
+    raw_call_r(r);
+
+#if USE_NORMAL_CALLING_CONVENTION
+    raw_inc_sp(4);
+#endif
+
+
+    live.nat[REG_RESULT].holds[0]=out1;
+    live.nat[REG_RESULT].nholds=1;
+    live.nat[REG_RESULT].touched=touchcnt++;
+
+    live.state[out1].realreg=REG_RESULT;
+    live.state[out1].realind=0;
+    live.state[out1].val=0;
+    live.state[out1].validsize=osize;
+    live.state[out1].dirtysize=osize;
+    set_status(out1,DIRTY);
+}
+MENDFUNC(5,call_r_11,(W4 out1, R4 r, R4 in1, IMM osize, IMM isize))
+
+MIDFUNC(5,call_r_02,(R4 r, R4 in1, R4 in2, IMM isize1, IMM isize2))
+{
+    clobber_flags();
+    remove_all_offsets();
+    in1=readreg_specific(in1,isize1,REG_PAR1);
+    in2=readreg_specific(in2,isize2,REG_PAR2);
+    r=readreg(r,4);
+    prepare_for_call_1();  /* This should ensure that there won't be
+			      any need for swapping nregs in prepare_for_call_2
+			   */
+#if USE_NORMAL_CALLING_CONVENTION
+    raw_push_l_r(in2);
+    raw_push_l_r(in1);
+#endif
+    unlock2(r);
+    unlock2(in1);
+    unlock2(in2);
+    prepare_for_call_2();
+    raw_call_r(r);
+#if USE_NORMAL_CALLING_CONVENTION
+    raw_inc_sp(8);
+#endif
+}
+MENDFUNC(5,call_r_02,(R4 r, R4 in1, R4 in2, IMM isize1, IMM isize2))
+
+/* forget_about() takes a mid-layer register */
+MIDFUNC(1,forget_about,(W4 r))
+{
+    if (isinreg(r))
+	disassociate(r);
+    live.state[r].val=0;
+    set_status(r,UNDEF);
+}
+MENDFUNC(1,forget_about,(W4 r))
+
+MIDFUNC(0,nop,(void))
+{
+    raw_nop();
+}
+MENDFUNC(0,nop,(void))
+
+
+MIDFUNC(1,f_forget_about,(FW r))
+{
+    if (f_isinreg(r))
+	f_disassociate(r);
+    live.fate[r].status=UNDEF;
+}
+MENDFUNC(1,f_forget_about,(FW r))
+
+MIDFUNC(1,fmov_pi,(FW r))
+{
+    r=f_writereg(r);
+    raw_fmov_pi(r);
+    f_unlock(r);
+}
+MENDFUNC(1,fmov_pi,(FW r))
+
+MIDFUNC(1,fmov_log10_2,(FW r))
+{
+    r=f_writereg(r);
+    raw_fmov_log10_2(r);
+    f_unlock(r);
+}
+MENDFUNC(1,fmov_log10_2,(FW r))
+
+MIDFUNC(1,fmov_log2_e,(FW r))
+{
+    r=f_writereg(r);
+    raw_fmov_log2_e(r);
+    f_unlock(r);
+}
+MENDFUNC(1,fmov_log2_e,(FW r))
+
+MIDFUNC(1,fmov_loge_2,(FW r))
+{
+    r=f_writereg(r);
+    raw_fmov_loge_2(r);
+    f_unlock(r);
+}
+MENDFUNC(1,fmov_loge_2,(FW r))
+
+MIDFUNC(1,fmov_1,(FW r))
+{
+    r=f_writereg(r);
+    raw_fmov_1(r);
+    f_unlock(r);
+}
+MENDFUNC(1,fmov_1,(FW r))
+
+MIDFUNC(1,fmov_0,(FW r))
+{
+    r=f_writereg(r);
+    raw_fmov_0(r);
+    f_unlock(r);
+}
+MENDFUNC(1,fmov_0,(FW r))
+
+MIDFUNC(2,fmov_rm,(FW r, MEMR m))
+{
+    r=f_writereg(r);
+    raw_fmov_rm(r,m);
+    f_unlock(r);
+}
+MENDFUNC(2,fmov_rm,(FW r, MEMR m))
+
+MIDFUNC(2,fmovi_rm,(FW r, MEMR m))
+{
+    r=f_writereg(r);
+    raw_fmovi_rm(r,m);
+    f_unlock(r);
+}
+MENDFUNC(2,fmovi_rm,(FW r, MEMR m))
+
+MIDFUNC(2,fmovi_mr,(MEMW m, FR r))
+{
+    r=f_readreg(r);
+    raw_fmovi_mr(m,r);
+    f_unlock(r);
+}
+MENDFUNC(2,fmovi_mr,(MEMW m, FR r))
+
+MIDFUNC(2,fmovs_rm,(FW r, MEMR m))
+{
+    r=f_writereg(r);
+    raw_fmovs_rm(r,m);
+    f_unlock(r);
+}
+MENDFUNC(2,fmovs_rm,(FW r, MEMR m))
+
+MIDFUNC(2,fmovs_mr,(MEMW m, FR r))
+{
+    r=f_readreg(r);
+    raw_fmovs_mr(m,r);
+    f_unlock(r);
+}
+MENDFUNC(2,fmovs_mr,(MEMW m, FR r))
+
+MIDFUNC(2,fmov_ext_mr,(MEMW m, FR r))
+{
+    r=f_readreg(r);
+    raw_fmov_ext_mr(m,r);
+    f_unlock(r);
+}
+MENDFUNC(2,fmov_ext_mr,(MEMW m, FR r))
+
+MIDFUNC(2,fmov_mr,(MEMW m, FR r))
+{
+    r=f_readreg(r);
+    raw_fmov_mr(m,r);
+    f_unlock(r);
+}
+MENDFUNC(2,fmov_mr,(MEMW m, FR r))
+
+MIDFUNC(2,fmov_ext_rm,(FW r, MEMR m))
+{
+    r=f_writereg(r);
+    raw_fmov_ext_rm(r,m);
+    f_unlock(r);
+}
+MENDFUNC(2,fmov_ext_rm,(FW r, MEMR m))
+
+MIDFUNC(2,fmov_rr,(FW d, FR s))
+{
+    if (d==s) { /* How pointless! */
+	return;
+    }
+#if USE_F_ALIAS
+    f_disassociate(d);
+    s=f_readreg(s);
+    live.fate[d].realreg=s;
+    live.fate[d].realind=live.fat[s].nholds;
+    live.fate[d].status=DIRTY;
+    live.fat[s].holds[live.fat[s].nholds]=d;
+    live.fat[s].nholds++;
+    f_unlock(s);
+#else
+    s=f_readreg(s);
+    d=f_writereg(d);
+    raw_fmov_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+#endif
+}
+MENDFUNC(2,fmov_rr,(FW d, FR s))
+
+MIDFUNC(2,fldcw_m_indexed,(R4 index, IMM base))
+{
+    index=readreg(index,4);
+
+    raw_fldcw_m_indexed(index,base);
+    unlock2(index);
+}
+MENDFUNC(2,fldcw_m_indexed,(R4 index, IMM base))
+
+MIDFUNC(1,ftst_r,(FR r))
+{
+    r=f_readreg(r);
+    raw_ftst_r(r);
+    f_unlock(r);
+}
+MENDFUNC(1,ftst_r,(FR r))
+
+MIDFUNC(0,dont_care_fflags,(void))
+{
+    f_disassociate(FP_RESULT);
+}
+MENDFUNC(0,dont_care_fflags,(void))
+
+MIDFUNC(2,fsqrt_rr,(FW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_writereg(d);
+    raw_fsqrt_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,fsqrt_rr,(FW d, FR s))
+
+MIDFUNC(2,fabs_rr,(FW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_writereg(d);
+    raw_fabs_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,fabs_rr,(FW d, FR s))
+
+MIDFUNC(2,fsin_rr,(FW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_writereg(d);
+    raw_fsin_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,fsin_rr,(FW d, FR s))
+
+MIDFUNC(2,fcos_rr,(FW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_writereg(d);
+    raw_fcos_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,fcos_rr,(FW d, FR s))
+
+MIDFUNC(2,ftwotox_rr,(FW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_writereg(d);
+    raw_ftwotox_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,ftwotox_rr,(FW d, FR s))
+
+MIDFUNC(2,fetox_rr,(FW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_writereg(d);
+    raw_fetox_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,fetox_rr,(FW d, FR s))
+
+MIDFUNC(2,frndint_rr,(FW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_writereg(d);
+    raw_frndint_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,frndint_rr,(FW d, FR s))
+
+MIDFUNC(2,flog2_rr,(FW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_writereg(d);
+    raw_flog2_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,flog2_rr,(FW d, FR s))
+
+MIDFUNC(2,fneg_rr,(FW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_writereg(d);
+    raw_fneg_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,fneg_rr,(FW d, FR s))
+
+MIDFUNC(2,fadd_rr,(FRW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_rmw(d);
+    raw_fadd_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,fadd_rr,(FRW d, FR s))
+
+MIDFUNC(2,fsub_rr,(FRW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_rmw(d);
+    raw_fsub_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,fsub_rr,(FRW d, FR s))
+
+MIDFUNC(2,fcmp_rr,(FR d, FR s))
+{
+    d=f_readreg(d);
+    s=f_readreg(s);
+    raw_fcmp_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,fcmp_rr,(FR d, FR s))
+
+MIDFUNC(2,fdiv_rr,(FRW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_rmw(d);
+    raw_fdiv_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,fdiv_rr,(FRW d, FR s))
+
+MIDFUNC(2,frem_rr,(FRW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_rmw(d);
+    raw_frem_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,frem_rr,(FRW d, FR s))
+
+MIDFUNC(2,frem1_rr,(FRW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_rmw(d);
+    raw_frem1_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,frem1_rr,(FRW d, FR s))
+
+MIDFUNC(2,fmul_rr,(FRW d, FR s))
+{
+    s=f_readreg(s);
+    d=f_rmw(d);
+    raw_fmul_rr(d,s);
+    f_unlock(s);
+    f_unlock(d);
+}
+MENDFUNC(2,fmul_rr,(FRW d, FR s))
+
+/********************************************************************
+ * Support functions exposed to gencomp. CREATE time                *
+ ********************************************************************/
+
+void set_zero(int r, int tmp)
+{
+    if (setzflg_uses_bsf)
+	bsf_l_rr(r,r);
+    else
+	simulate_bsf(tmp,r);
+}
+
+int kill_rodent(int r)
+{
+    return KILLTHERAT && 
+		have_rat_stall &&
+	(live.state[r].status==INMEM || 
+	 live.state[r].status==CLEAN || 
+	 live.state[r].status==ISCONST || 
+	 live.state[r].dirtysize==4);
+}
+
+uae_u32 get_const(int r)
+{
+	Dif (!isconst(r)) {
+	    write_log("Register %d should be constant, but isn't\n",r);
+	    abort();
+	}
+    return live.state[r].val;
+}
+
+void sync_m68k_pc(void)
+{
+    if (m68k_pc_offset) {
+	add_l_ri(PC_P,m68k_pc_offset);
+	comp_pc_p+=m68k_pc_offset;
+	m68k_pc_offset=0;
+    }
+}
+    
+/********************************************************************
+ * Scratch registers management                                     *
+ ********************************************************************/
+
+struct scratch_t {
+	uae_u32		regs[VREGS];
+	fpu_register	fregs[VFREGS];
+};
+
+static scratch_t scratch;
+
+/********************************************************************
+ * Support functions exposed to newcpu                              *
+ ********************************************************************/
+
+static inline const char *str_on_off(bool b)
+{
+	return b ? "on" : "off";
+}
+
+void compiler_init(void)
+{
+	static bool initialized = false;
+	if (initialized)
+		return;
+
+#if JIT_DEBUG
+	// JIT debug mode ?
+	JITDebug = PrefsFindBool("jitdebug");
+#endif
+	write_log(" : enable runtime disassemblers : %s\n", JITDebug ? "yes" : "no");
+	
+#ifdef USE_JIT_FPU
+	// Use JIT compiler for FPU instructions ?
+	avoid_fpu = !PrefsFindBool("jitfpu");
+#else
+	// JIT FPU is always disabled
+	avoid_fpu = true;
+#endif
+	write_log(" : compile FPU instructions : %s\n", !avoid_fpu ? "yes" : "no");
+	
+	// Get size of the translation cache (in KB)
+	cache_size = PrefsFindInt32("jitcachesize");
+	write_log(" : requested translation cache size : %d KB\n", cache_size);
+	
+	// Initialize target CPU (check for features, e.g. CMOV, rat stalls)
+	raw_init_cpu();
+	setzflg_uses_bsf = target_check_bsf();
+	write_log(" : target processor has CMOV instructions : %s\n", have_cmov ? "yes" : "no");
+	write_log(" : target processor can suffer from partial register stalls : %s\n", have_rat_stall ? "yes" : "no");
+	write_log(" : alignment for loops, jumps are %d, %d\n", align_loops, align_jumps);
+	
+	// Translation cache flush mechanism
+	lazy_flush = PrefsFindBool("jitlazyflush");
+	write_log(" : lazy translation cache invalidation : %s\n", str_on_off(lazy_flush));
+	flush_icache = lazy_flush ? flush_icache_lazy : flush_icache_hard;
+	
+	// Compiler features
+	write_log(" : register aliasing : %s\n", str_on_off(1));
+	write_log(" : FP register aliasing : %s\n", str_on_off(USE_F_ALIAS));
+	write_log(" : lazy constant offsetting : %s\n", str_on_off(USE_OFFSET));
+#if USE_INLINING
+	follow_const_jumps = PrefsFindBool("jitinline");
+#endif
+	write_log(" : translate through constant jumps : %s\n", str_on_off(follow_const_jumps));
+	write_log(" : separate blockinfo allocation : %s\n", str_on_off(USE_SEPARATE_BIA));
+	
+	// Build compiler tables
+	build_comp();
+	
+	initialized = true;
+	
+#if PROFILE_UNTRANSLATED_INSNS
+	write_log(" : gather statistics on untranslated insns count\n");
+#endif
+
+#if PROFILE_COMPILE_TIME
+	write_log(" : gather statistics on translation time\n");
+	emul_start_time = clock();
+#endif
+}
+
+void compiler_exit(void)
+{
+#if PROFILE_COMPILE_TIME
+	emul_end_time = clock();
+#endif
+	
+	// Deallocate translation cache
+	if (compiled_code) {
+		vm_release(compiled_code, cache_size * 1024);
+		compiled_code = 0;
+	}
+
+	// Deallocate popallspace
+	if (popallspace) {
+		vm_release(popallspace, POPALLSPACE_SIZE);
+		popallspace = 0;
+	}
+	
+#if PROFILE_COMPILE_TIME
+	write_log("### Compile Block statistics\n");
+	write_log("Number of calls to compile_block : %d\n", compile_count);
+	uae_u32 emul_time = emul_end_time - emul_start_time;
+	write_log("Total emulation time   : %.1f sec\n", double(emul_time)/double(CLOCKS_PER_SEC));
+	write_log("Total compilation time : %.1f sec (%.1f%%)\n", double(compile_time)/double(CLOCKS_PER_SEC),
+		100.0*double(compile_time)/double(emul_time));
+	write_log("\n");
+#endif
+
+#if PROFILE_UNTRANSLATED_INSNS
+	uae_u64 untranslated_count = 0;
+	for (int i = 0; i < 65536; i++) {
+		opcode_nums[i] = i;
+		untranslated_count += raw_cputbl_count[i];
+	}
+	write_log("Sorting out untranslated instructions count...\n");
+	qsort(opcode_nums, 65536, sizeof(uae_u16), untranslated_compfn);
+	write_log("\nRank  Opc      Count Name\n");
+	for (int i = 0; i < untranslated_top_ten; i++) {
+		uae_u32 count = raw_cputbl_count[opcode_nums[i]];
+		struct instr *dp;
+		struct mnemolookup *lookup;
+		if (!count)
+			break;
+		dp = table68k + opcode_nums[i];
+		for (lookup = lookuptab; lookup->mnemo != dp->mnemo; lookup++)
+			;
+		write_log("%03d: %04x %10lu %s\n", i, opcode_nums[i], count, lookup->name);
+	}
+#endif
+
+#if RECORD_REGISTER_USAGE
+	int reg_count_ids[16];
+	uint64 tot_reg_count = 0;
+	for (int i = 0; i < 16; i++) {
+	    reg_count_ids[i] = i;
+	    tot_reg_count += reg_count[i];
+	}
+	qsort(reg_count_ids, 16, sizeof(int), reg_count_compare);
+	uint64 cum_reg_count = 0;
+	for (int i = 0; i < 16; i++) {
+	    int r = reg_count_ids[i];
+	    cum_reg_count += reg_count[r];
+	    printf("%c%d : %16ld %2.1f%% [%2.1f]\n", r < 8 ? 'D' : 'A', r % 8,
+		   reg_count[r],
+		   100.0*double(reg_count[r])/double(tot_reg_count),
+		   100.0*double(cum_reg_count)/double(tot_reg_count));
+	}
+#endif
+}
+
+bool compiler_use_jit(void)
+{
+	// Check for the "jit" prefs item
+	if (!PrefsFindBool("jit"))
+		return false;
+	
+	// Don't use JIT if translation cache size is less then MIN_CACHE_SIZE KB
+	if (PrefsFindInt32("jitcachesize") < MIN_CACHE_SIZE) {
+		write_log(" : translation cache size is less than %d KB. Disabling JIT.\n", MIN_CACHE_SIZE);
+		return false;
+	}
+	
+	// Enable JIT for 68020+ emulation only
+	if (CPUType < 2) {
+		write_log(" : JIT is not supported in 680%d0 emulation mode, disabling.\n", CPUType);
+		return false;
+	}
+
+	return true;
+}
+
+void init_comp(void)
+{
+    int i;
+    uae_s8* cb=can_byte;
+    uae_s8* cw=can_word;
+    uae_s8* au=always_used;
+
+#if RECORD_REGISTER_USAGE
+    for (i=0;i<16;i++)
+	reg_count_local[i] = 0;
+#endif
+
+    for (i=0;i= (uintptr)ROMBaseHost) && (addr < (uintptr)ROMBaseHost + ROMSize));
+}
+
+static void flush_all(void)
+{
+    int i;
+
+	log_flush();
+    for (i=0;i0)
+	    free_nreg(i);
+
+    for (i=0;i0)
+	    f_free_nreg(i);
+
+    live.flags_in_flags=TRASH;  /* Note: We assume we already rescued the
+				   flags at the very start of the call_r
+				   functions! */
+}
+
+/********************************************************************
+ * Memory access and related functions, CREATE time                 *
+ ********************************************************************/
+
+void register_branch(uae_u32 not_taken, uae_u32 taken, uae_u8 cond)
+{
+    next_pc_p=not_taken;
+    taken_pc_p=taken;
+    branch_cc=cond;
+}
+
+
+static uae_u32 get_handler_address(uae_u32 addr)
+{
+    uae_u32 cl=cacheline(addr);
+    blockinfo* bi=get_blockinfo_addr_new((void*)(uintptr)addr,0);
+    return (uintptr)&(bi->direct_handler_to_use);
+}
+
+static uae_u32 get_handler(uae_u32 addr)
+{
+    uae_u32 cl=cacheline(addr);
+    blockinfo* bi=get_blockinfo_addr_new((void*)(uintptr)addr,0);
+    return (uintptr)bi->direct_handler_to_use;
+}
+
+static void load_handler(int reg, uae_u32 addr)
+{
+    mov_l_rm(reg,get_handler_address(addr));
+}
+
+/* This version assumes that it is writing *real* memory, and *will* fail
+ *  if that assumption is wrong! No branches, no second chances, just
+ *  straight go-for-it attitude */
+
+static void writemem_real(int address, int source, int size, int tmp, int clobber)
+{
+    int f=tmp;
+
+	if (clobber)
+	    f=source;
+
+	switch(size) {
+	 case 1: mov_b_bRr(address,source,MEMBaseDiff); break; 
+	 case 2: mov_w_rr(f,source); bswap_16(f); mov_w_bRr(address,f,MEMBaseDiff); break;
+	 case 4: mov_l_rr(f,source); bswap_32(f); mov_l_bRr(address,f,MEMBaseDiff); break;
+	}
+	forget_about(tmp);
+	forget_about(f);
+}
+
+void writebyte(int address, int source, int tmp)
+{
+	writemem_real(address,source,1,tmp,0);
+}
+
+static __inline__ void writeword_general(int address, int source, int tmp,
+					 int clobber)
+{
+	writemem_real(address,source,2,tmp,clobber);
+}
+
+void writeword_clobber(int address, int source, int tmp)
+{
+    writeword_general(address,source,tmp,1);
+}
+
+void writeword(int address, int source, int tmp)
+{
+    writeword_general(address,source,tmp,0);
+}
+
+static __inline__ void writelong_general(int address, int source, int tmp, 
+					 int clobber)
+{
+	writemem_real(address,source,4,tmp,clobber);
+}
+
+void writelong_clobber(int address, int source, int tmp)
+{
+    writelong_general(address,source,tmp,1);
+}
+
+void writelong(int address, int source, int tmp)
+{
+    writelong_general(address,source,tmp,0);
+}
+
+
+
+/* This version assumes that it is reading *real* memory, and *will* fail
+ *  if that assumption is wrong! No branches, no second chances, just
+ *  straight go-for-it attitude */
+
+static void readmem_real(int address, int dest, int size, int tmp)
+{
+    int f=tmp; 
+
+    if (size==4 && address!=dest)
+	f=dest;
+
+	switch(size) {
+	 case 1: mov_b_brR(dest,address,MEMBaseDiff); break; 
+	 case 2: mov_w_brR(dest,address,MEMBaseDiff); bswap_16(dest); break;
+	 case 4: mov_l_brR(dest,address,MEMBaseDiff); bswap_32(dest); break;
+	}
+	forget_about(tmp);
+}
+
+void readbyte(int address, int dest, int tmp)
+{
+	readmem_real(address,dest,1,tmp);
+}
+
+void readword(int address, int dest, int tmp)
+{
+	readmem_real(address,dest,2,tmp);
+}
+
+void readlong(int address, int dest, int tmp)
+{
+	readmem_real(address,dest,4,tmp);
+}
+
+void get_n_addr(int address, int dest, int tmp)
+{
+	// a is the register containing the virtual address
+	// after the offset had been fetched
+	int a=tmp;
+	
+	// f is the register that will contain the offset
+	int f=tmp;
+	
+	// a == f == tmp if (address == dest)
+	if (address!=dest) {
+	a=address;
+	f=dest;
+	}
+
+#if REAL_ADDRESSING
+	mov_l_rr(dest, address);
+#elif DIRECT_ADDRESSING
+	lea_l_brr(dest,address,MEMBaseDiff);
+#endif
+	forget_about(tmp);
+}
+
+void get_n_addr_jmp(int address, int dest, int tmp)
+{
+	/* For this, we need to get the same address as the rest of UAE
+	 would --- otherwise we end up translating everything twice */
+    get_n_addr(address,dest,tmp);
+}
+
+
+/* base is a register, but dp is an actual value. 
+   target is a register, as is tmp */
+void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp)
+{
+    int reg = (dp >> 12) & 15;
+    int regd_shift=(dp >> 9) & 3;
+
+    if (dp & 0x100) {
+	int ignorebase=(dp&0x80);
+	int ignorereg=(dp&0x40);
+	int addbase=0;
+	int outer=0;
+    
+	if ((dp & 0x30) == 0x20) addbase = (uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2);
+	if ((dp & 0x30) == 0x30) addbase = comp_get_ilong((m68k_pc_offset+=4)-4);
+
+	if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)comp_get_iword((m68k_pc_offset+=2)-2);
+	if ((dp & 0x3) == 0x3) outer = comp_get_ilong((m68k_pc_offset+=4)-4);
+
+	if ((dp & 0x4) == 0) {  /* add regd *before* the get_long */
+	    if (!ignorereg) {
+		if ((dp & 0x800) == 0) 
+		    sign_extend_16_rr(target,reg);
+		else
+		    mov_l_rr(target,reg);
+		shll_l_ri(target,regd_shift);
+	    }
+	    else
+		mov_l_ri(target,0);
+
+	    /* target is now regd */
+	    if (!ignorebase)
+		add_l(target,base);
+	    add_l_ri(target,addbase);
+	    if (dp&0x03) readlong(target,target,tmp);
+	} else { /* do the getlong first, then add regd */
+	    if (!ignorebase) {
+		mov_l_rr(target,base);
+		add_l_ri(target,addbase);
+	    }
+	    else
+		mov_l_ri(target,addbase);
+	    if (dp&0x03) readlong(target,target,tmp);
+
+	    if (!ignorereg) {
+		if ((dp & 0x800) == 0) 
+		    sign_extend_16_rr(tmp,reg);
+		else
+		    mov_l_rr(tmp,reg);
+		shll_l_ri(tmp,regd_shift);
+		/* tmp is now regd */
+		add_l(target,tmp);
+	    }
+	}
+	add_l_ri(target,outer);
+    }
+    else { /* 68000 version */
+	if ((dp & 0x800) == 0) { /* Sign extend */
+	    sign_extend_16_rr(target,reg);
+	    lea_l_brr_indexed(target,base,target,1<= CODE_ALLOC_MAX_ATTEMPTS)
+		return NULL;
+
+	return do_alloc_code(size, depth + 1);
+#else
+	uint8 *code = (uint8 *)vm_acquire(size);
+	return code == VM_MAP_FAILED ? NULL : code;
+#endif
+}
+
+static inline uint8 *alloc_code(uint32 size)
+{
+	uint8 *ptr = do_alloc_code(size, 0);
+	/* allocated code must fit in 32-bit boundaries */
+	assert((uintptr)ptr <= 0xffffffff);
+	return ptr;
+}
+
+void alloc_cache(void)
+{
+	if (compiled_code) {
+		flush_icache_hard(6);
+		vm_release(compiled_code, cache_size * 1024);
+		compiled_code = 0;
+	}
+	
+	if (cache_size == 0)
+		return;
+	
+	while (!compiled_code && cache_size) {
+		if ((compiled_code = alloc_code(cache_size * 1024)) == NULL) {
+			compiled_code = 0;
+			cache_size /= 2;
+		}
+	}
+	vm_protect(compiled_code, cache_size * 1024, VM_PAGE_READ | VM_PAGE_WRITE | VM_PAGE_EXECUTE);
+	
+	if (compiled_code) {
+		write_log(" : actual translation cache size : %d KB at 0x%08X\n", cache_size, compiled_code);
+		max_compile_start = compiled_code + cache_size*1024 - BYTES_PER_INST;
+		current_compile_p = compiled_code;
+		current_cache_size = 0;
+	}
+}
+
+
+
+extern void op_illg_1 (uae_u32 opcode) REGPARAM;
+
+static void calc_checksum(blockinfo* bi, uae_u32* c1, uae_u32* c2)
+{
+    uae_u32 k1 = 0;
+    uae_u32 k2 = 0;
+
+#if USE_CHECKSUM_INFO
+    checksum_info *csi = bi->csi;
+	Dif(!csi) abort();
+	while (csi) {
+		uae_s32 len = csi->length;
+		uintptr tmp = (uintptr)csi->start_p;
+#else
+		uae_s32 len = bi->len;
+		uintptr tmp = (uintptr)bi->min_pcp;
+#endif
+		uae_u32*pos;
+
+		len += (tmp & 3);
+		tmp &= ~((uintptr)3);
+		pos = (uae_u32 *)tmp;
+
+		if (len >= 0 && len <= MAX_CHECKSUM_LEN) {
+			while (len > 0) {
+				k1 += *pos;
+				k2 ^= *pos;
+				pos++;
+				len -= 4;
+			}
+		}
+
+#if USE_CHECKSUM_INFO
+		csi = csi->next;
+	}
+#endif
+
+	*c1 = k1;
+	*c2 = k2;
+}
+
+#if 0
+static void show_checksum(CSI_TYPE* csi)
+{
+    uae_u32 k1=0;
+    uae_u32 k2=0;
+    uae_s32 len=CSI_LENGTH(csi);
+    uae_u32 tmp=(uintptr)CSI_START_P(csi);
+    uae_u32* pos;
+
+    len+=(tmp&3);
+    tmp&=(~3);
+    pos=(uae_u32*)tmp;
+
+    if (len<0 || len>MAX_CHECKSUM_LEN) {
+	return;
+    }
+    else {
+	while (len>0) {
+	    write_log("%08x ",*pos);
+	    pos++;
+	    len-=4;
+	}
+	write_log(" bla\n");
+    }
+}
+#endif
+
+
+int check_for_cache_miss(void)
+{
+    blockinfo* bi=get_blockinfo_addr(regs.pc_p);
+    
+    if (bi) {
+	int cl=cacheline(regs.pc_p);
+	if (bi!=cache_tags[cl+1].bi) {
+	    raise_in_cl_list(bi);
+	    return 1;
+	}
+    }
+    return 0;
+}
+
+    
+static void recompile_block(void)
+{
+    /* An existing block's countdown code has expired. We need to make
+       sure that execute_normal doesn't refuse to recompile due to a
+       perceived cache miss... */
+    blockinfo*  bi=get_blockinfo_addr(regs.pc_p);
+
+    Dif (!bi) 
+	abort();
+    raise_in_cl_list(bi);
+    execute_normal();
+    return;
+}
+static void cache_miss(void)
+{
+    blockinfo*  bi=get_blockinfo_addr(regs.pc_p);
+    uae_u32     cl=cacheline(regs.pc_p);
+    blockinfo*  bi2=get_blockinfo(cl);
+
+    if (!bi) {
+	execute_normal(); /* Compile this block now */
+	return;
+    }
+    Dif (!bi2 || bi==bi2) {
+	write_log("Unexplained cache miss %p %p\n",bi,bi2);
+	abort();
+    }
+    raise_in_cl_list(bi);
+    return;
+}
+
+static int called_check_checksum(blockinfo* bi);
+
+static inline int block_check_checksum(blockinfo* bi) 
+{
+    uae_u32     c1,c2;
+    bool        isgood;
+    
+    if (bi->status!=BI_NEED_CHECK)
+	return 1;  /* This block is in a checked state */
+    
+    checksum_count++;
+
+    if (bi->c1 || bi->c2)
+	calc_checksum(bi,&c1,&c2);
+    else {
+	c1=c2=1;  /* Make sure it doesn't match */
+	}
+    
+    isgood=(c1==bi->c1 && c2==bi->c2);
+
+    if (isgood) { 
+	/* This block is still OK. So we reactivate. Of course, that
+	   means we have to move it into the needs-to-be-flushed list */
+	bi->handler_to_use=bi->handler;
+	set_dhtu(bi,bi->direct_handler);
+	bi->status=BI_CHECKING;
+	isgood=called_check_checksum(bi);
+    }
+    if (isgood) {
+	/*	write_log("reactivate %p/%p (%x %x/%x %x)\n",bi,bi->pc_p,
+		c1,c2,bi->c1,bi->c2);*/
+	remove_from_list(bi);
+	add_to_active(bi);
+	raise_in_cl_list(bi);
+	bi->status=BI_ACTIVE;
+    }
+    else {
+	/* This block actually changed. We need to invalidate it,
+	   and set it up to be recompiled */
+	/* write_log("discard %p/%p (%x %x/%x %x)\n",bi,bi->pc_p,
+	   c1,c2,bi->c1,bi->c2); */
+	invalidate_block(bi);
+	raise_in_cl_list(bi);
+    }
+    return isgood;
+}
+
+static int called_check_checksum(blockinfo* bi) 
+{
+    dependency* x=bi->deplist;
+    int isgood=1;
+    int i;
+    
+    for (i=0;i<2 && isgood;i++) {
+	if (bi->dep[i].jmp_off) {
+	    isgood=block_check_checksum(bi->dep[i].target);
+	}
+    }
+    return isgood;
+}
+
+static void check_checksum(void) 
+{
+    blockinfo*  bi=get_blockinfo_addr(regs.pc_p);
+    uae_u32     cl=cacheline(regs.pc_p);
+    blockinfo*  bi2=get_blockinfo(cl);
+
+    /* These are not the droids you are looking for...  */
+    if (!bi) {
+	/* Whoever is the primary target is in a dormant state, but
+	   calling it was accidental, and we should just compile this
+	   new block */
+	execute_normal();
+	return;
+    }
+    if (bi!=bi2) {
+	/* The block was hit accidentally, but it does exist. Cache miss */
+	cache_miss();
+	return;
+    }
+
+    if (!block_check_checksum(bi))
+	execute_normal();
+}
+
+static __inline__ void match_states(blockinfo* bi)
+{
+    int i;
+    smallstate* s=&(bi->env);
+    
+    if (bi->status==BI_NEED_CHECK) {
+	block_check_checksum(bi);
+    }
+    if (bi->status==BI_ACTIVE || 
+	bi->status==BI_FINALIZING) {  /* Deal with the *promises* the 
+					 block makes (about not using 
+					 certain vregs) */
+	for (i=0;i<16;i++) {
+	    if (s->virt[i]==L_UNNEEDED) {
+		// write_log("unneeded reg %d at %p\n",i,target);
+		COMPCALL(forget_about)(i); // FIXME
+	    }
+	}
+    }
+    flush(1);
+
+    /* And now deal with the *demands* the block makes */
+    for (i=0;inat[i];
+	if (v>=0) {
+	    // printf("Loading reg %d into %d at %p\n",v,i,target);
+	    readreg_specific(v,4,i);
+	    // do_load_reg(i,v);
+	    // setlock(i);
+	}
+    }
+    for (i=0;inat[i];
+	if (v>=0) {
+	    unlock2(i);
+	}
+    }
+}
+
+static __inline__ void create_popalls(void)
+{
+  int i,r;
+
+  if ((popallspace = alloc_code(POPALLSPACE_SIZE)) == NULL) {
+	  write_log("FATAL: Could not allocate popallspace!\n");
+	  abort();
+  }
+  vm_protect(popallspace, POPALLSPACE_SIZE, VM_PAGE_READ | VM_PAGE_WRITE);
+
+  int stack_space = STACK_OFFSET;
+  for (i=0;idirect_pen=(cpuop_func *)get_target();
+    raw_mov_l_rm(0,(uintptr)&(bi->pc_p));
+    raw_mov_l_mr((uintptr)®s.pc_p,0);
+    raw_jmp((uintptr)popall_execute_normal);
+
+    align_target(align_jumps);
+    bi->direct_pcc=(cpuop_func *)get_target();
+    raw_mov_l_rm(0,(uintptr)&(bi->pc_p));
+    raw_mov_l_mr((uintptr)®s.pc_p,0);
+    raw_jmp((uintptr)popall_check_checksum);
+    current_compile_p=get_target();
+
+    bi->deplist=NULL;
+    for (i=0;i<2;i++) {
+	bi->dep[i].prev_p=NULL;
+	bi->dep[i].next=NULL;
+    }
+    bi->env=default_ss;
+    bi->status=BI_INVALID;
+    bi->havestate=0;
+    //bi->env=empty_ss;
+}
+
+// OPCODE is in big endian format, use cft_map() beforehand, if needed.
+static inline void reset_compop(int opcode)
+{
+	compfunctbl[opcode] = NULL;
+	nfcompfunctbl[opcode] = NULL;
+}
+
+static int read_opcode(const char *p)
+{
+	int opcode = 0;
+	for (int i = 0; i < 4; i++) {
+		int op = p[i];
+		switch (op) {
+		case '0': case '1': case '2': case '3': case '4':
+		case '5': case '6': case '7': case '8': case '9':
+			opcode = (opcode << 4) | (op - '0');
+			break;
+		case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
+			opcode = (opcode << 4) | ((op - 'a') + 10);
+			break;
+		case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
+			opcode = (opcode << 4) | ((op - 'A') + 10);
+			break;
+		default:
+			return -1;
+		}
+	}
+	return opcode;
+}
+
+static bool merge_blacklist()
+{
+	const char *blacklist = PrefsFindString("jitblacklist");
+	if (blacklist) {
+		const char *p = blacklist;
+		for (;;) {
+			if (*p == 0)
+				return true;
+
+			int opcode1 = read_opcode(p);
+			if (opcode1 < 0)
+				return false;
+			p += 4;
+
+			int opcode2 = opcode1;
+			if (*p == '-') {
+				p++;
+				opcode2 = read_opcode(p);
+				if (opcode2 < 0)
+					return false;
+				p += 4;
+			}
+
+			if (*p == 0 || *p == ',' || *p == ';') {
+				write_log(" : blacklist opcodes : %04x-%04x\n", opcode1, opcode2);
+				for (int opcode = opcode1; opcode <= opcode2; opcode++)
+					reset_compop(cft_map(opcode));
+
+				if (*p == ',' || *p++ == ';')
+					continue;
+
+				return true;
+			}
+
+			return false;
+		}
+	}
+	return true;
+}
+
+void build_comp(void) 
+{
+	int i;
+    int jumpcount=0;
+    unsigned long opcode;
+    struct comptbl* tbl=op_smalltbl_0_comp_ff;
+    struct comptbl* nftbl=op_smalltbl_0_comp_nf;
+    int count;
+	int cpu_level = 0;			// 68000 (default)
+	if (CPUType == 4)
+		cpu_level = 4;			// 68040 with FPU
+	else {
+		if (FPUType)
+			cpu_level = 3;		// 68020 with FPU
+		else if (CPUType >= 2)
+			cpu_level = 2;		// 68020
+		else if (CPUType == 1)
+			cpu_level = 1;
+	}
+    struct cputbl *nfctbl = (
+				   cpu_level == 4 ? op_smalltbl_0_nf
+			     : cpu_level == 3 ? op_smalltbl_1_nf
+			     : cpu_level == 2 ? op_smalltbl_2_nf
+			     : cpu_level == 1 ? op_smalltbl_3_nf
+			     : op_smalltbl_4_nf);
+
+    write_log (" : building compiler function tables\n");
+	
+	for (opcode = 0; opcode < 65536; opcode++) {
+		reset_compop(opcode);
+		nfcpufunctbl[opcode] = op_illg_1;
+		prop[opcode].use_flags = 0x1f;
+		prop[opcode].set_flags = 0x1f;
+		prop[opcode].cflow = fl_trap; // ILLEGAL instructions do trap
+	}
+	
+	for (i = 0; tbl[i].opcode < 65536; i++) {
+		int cflow = table68k[tbl[i].opcode].cflow;
+		if (follow_const_jumps && (tbl[i].specific & 16))
+			cflow = fl_const_jump;
+		else
+			cflow &= ~fl_const_jump;
+		prop[cft_map(tbl[i].opcode)].cflow = cflow;
+
+		int uses_fpu = tbl[i].specific & 32;
+		if (uses_fpu && avoid_fpu)
+			compfunctbl[cft_map(tbl[i].opcode)] = NULL;
+		else
+			compfunctbl[cft_map(tbl[i].opcode)] = tbl[i].handler;
+	}
+
+    for (i = 0; nftbl[i].opcode < 65536; i++) {
+		int uses_fpu = tbl[i].specific & 32;
+		if (uses_fpu && avoid_fpu)
+			nfcompfunctbl[cft_map(nftbl[i].opcode)] = NULL;
+		else
+			nfcompfunctbl[cft_map(nftbl[i].opcode)] = nftbl[i].handler;
+		
+		nfcpufunctbl[cft_map(nftbl[i].opcode)] = nfctbl[i].handler;
+    }
+
+	for (i = 0; nfctbl[i].handler; i++) {
+		nfcpufunctbl[cft_map(nfctbl[i].opcode)] = nfctbl[i].handler;
+	}
+
+    for (opcode = 0; opcode < 65536; opcode++) {
+		compop_func *f;
+		compop_func *nff;
+		cpuop_func *nfcf;
+		int isaddx,cflow;
+
+		if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level)
+			continue;
+
+		if (table68k[opcode].handler != -1) {
+			f = compfunctbl[cft_map(table68k[opcode].handler)];
+			nff = nfcompfunctbl[cft_map(table68k[opcode].handler)];
+			nfcf = nfcpufunctbl[cft_map(table68k[opcode].handler)];
+			cflow = prop[cft_map(table68k[opcode].handler)].cflow;
+			isaddx = prop[cft_map(table68k[opcode].handler)].is_addx;
+			prop[cft_map(opcode)].cflow = cflow;
+			prop[cft_map(opcode)].is_addx = isaddx;
+			compfunctbl[cft_map(opcode)] = f;
+			nfcompfunctbl[cft_map(opcode)] = nff;
+			Dif (nfcf == op_illg_1)
+			abort();
+			nfcpufunctbl[cft_map(opcode)] = nfcf;
+		}
+		prop[cft_map(opcode)].set_flags = table68k[opcode].flagdead;
+		prop[cft_map(opcode)].use_flags = table68k[opcode].flaglive;
+		/* Unconditional jumps don't evaluate condition codes, so they
+		 * don't actually use any flags themselves */
+		if (prop[cft_map(opcode)].cflow & fl_const_jump)
+			prop[cft_map(opcode)].use_flags = 0;
+    }
+	for (i = 0; nfctbl[i].handler != NULL; i++) {
+		if (nfctbl[i].specific)
+			nfcpufunctbl[cft_map(tbl[i].opcode)] = nfctbl[i].handler;
+	}
+
+	/* Merge in blacklist */
+	if (!merge_blacklist())
+		write_log(" : blacklist merge failure!\n");
+
+    count=0;
+    for (opcode = 0; opcode < 65536; opcode++) {
+	if (compfunctbl[cft_map(opcode)])
+	    count++;
+    }
+	write_log(" : supposedly %d compileable opcodes!\n",count);
+
+    /* Initialise state */
+    create_popalls();
+    alloc_cache();
+    reset_lists();
+
+    for (i=0;ipc_p)].handler=(cpuop_func *)popall_execute_normal;
+	cache_tags[cacheline(bi->pc_p)+1].bi=NULL;
+	dbi=bi; bi=bi->next;
+	free_blockinfo(dbi);
+    }
+    bi=dormant;
+    while(bi) {
+	cache_tags[cacheline(bi->pc_p)].handler=(cpuop_func *)popall_execute_normal;
+	cache_tags[cacheline(bi->pc_p)+1].bi=NULL;
+	dbi=bi; bi=bi->next;
+	free_blockinfo(dbi);
+    }
+
+    reset_lists();
+    if (!compiled_code)
+	return;
+    current_compile_p=compiled_code;
+	SPCFLAGS_SET( SPCFLAG_JIT_EXEC_RETURN ); /* To get out of compiled code */
+}
+
+
+/* "Soft flushing" --- instead of actually throwing everything away,
+   we simply mark everything as "needs to be checked". 
+*/
+
+static inline void flush_icache_lazy(int n)
+{
+    uae_u32 i;
+    blockinfo* bi;
+    blockinfo* bi2;
+
+        soft_flush_count++;
+	if (!active)
+	    return;
+
+	bi=active;
+	while (bi) {
+	    uae_u32 cl=cacheline(bi->pc_p);
+		if (bi->status==BI_INVALID ||
+			bi->status==BI_NEED_RECOMP) { 
+		if (bi==cache_tags[cl+1].bi) 
+		    cache_tags[cl].handler=(cpuop_func *)popall_execute_normal;
+		bi->handler_to_use=(cpuop_func *)popall_execute_normal;
+		set_dhtu(bi,bi->direct_pen);
+	    bi->status=BI_INVALID;
+	    }
+	    else {
+		if (bi==cache_tags[cl+1].bi) 
+		    cache_tags[cl].handler=(cpuop_func *)popall_check_checksum;
+		bi->handler_to_use=(cpuop_func *)popall_check_checksum;
+		set_dhtu(bi,bi->direct_pcc);
+		bi->status=BI_NEED_CHECK;
+	    }
+	    bi2=bi;
+	    bi=bi->next;
+	}
+	/* bi2 is now the last entry in the active list */
+	bi2->next=dormant;
+	if (dormant)
+	    dormant->prev_p=&(bi2->next);
+    
+	dormant=active;
+	active->prev_p=&dormant;
+	active=NULL;
+}
+
+void flush_icache_range(uae_u8 *start_p, uae_u32 length)
+{
+	if (!active)
+		return;
+
+#if LAZY_FLUSH_ICACHE_RANGE
+	blockinfo *bi = active;
+	while (bi) {
+#if USE_CHECKSUM_INFO
+		bool candidate = false;
+		for (checksum_info *csi = bi->csi; csi; csi = csi->next) {
+			if (((start_p - csi->start_p) < csi->length) ||
+				((csi->start_p - start_p) < length)) {
+				candidate = true;
+				break;
+			}
+		}
+#else
+		// Assume system is consistent and would invalidate the right range
+		const bool candidate = (bi->pc_p - start_p) < length;
+#endif
+		blockinfo *dbi = bi;
+		bi = bi->next;
+		if (candidate) {
+			uae_u32 cl = cacheline(dbi->pc_p);
+			if (dbi->status == BI_INVALID || dbi->status == BI_NEED_RECOMP) {
+				if (dbi == cache_tags[cl+1].bi) 
+					cache_tags[cl].handler = (cpuop_func *)popall_execute_normal;
+				dbi->handler_to_use = (cpuop_func *)popall_execute_normal;
+				set_dhtu(dbi, dbi->direct_pen);
+				dbi->status = BI_INVALID;
+			}
+			else {
+				if (dbi == cache_tags[cl+1].bi) 
+					cache_tags[cl].handler = (cpuop_func *)popall_check_checksum;
+				dbi->handler_to_use = (cpuop_func *)popall_check_checksum;
+				set_dhtu(dbi, dbi->direct_pcc);
+				dbi->status = BI_NEED_CHECK;
+			}
+			remove_from_list(dbi);
+			add_to_dormant(dbi);
+		}
+	}
+	return;
+#endif
+	flush_icache(-1);
+}
+
+static void catastrophe(void)
+{
+    abort();
+}
+
+int failure;
+
+#define TARGET_M68K		0
+#define TARGET_POWERPC	1
+#define TARGET_X86		2
+#define TARGET_X86_64	3
+#if defined(i386) || defined(__i386__)
+#define TARGET_NATIVE	TARGET_X86
+#endif
+#if defined(powerpc) || defined(__powerpc__)
+#define TARGET_NATIVE	TARGET_POWERPC
+#endif
+#if defined(x86_64) || defined(__x86_64__)
+#define TARGET_NATIVE	TARGET_X86_64
+#endif
+
+#ifdef ENABLE_MON
+static uae_u32 mon_read_byte_jit(uintptr addr)
+{
+	uae_u8 *m = (uae_u8 *)addr;
+	return (uintptr)(*m);
+}
+ 
+static void mon_write_byte_jit(uintptr addr, uae_u32 b)
+{
+	uae_u8 *m = (uae_u8 *)addr;
+	*m = b;
+}
+#endif
+
+void disasm_block(int target, uint8 * start, size_t length)
+{
+	if (!JITDebug)
+		return;
+	
+#if defined(JIT_DEBUG) && defined(ENABLE_MON)
+	char disasm_str[200];
+	sprintf(disasm_str, "%s $%x $%x",
+			target == TARGET_M68K ? "d68" :
+			target == TARGET_X86 ? "d86" :
+			target == TARGET_X86_64 ? "d8664" :
+			target == TARGET_POWERPC ? "d" : "x",
+			start, start + length - 1);
+	
+	uae_u32 (*old_mon_read_byte)(uintptr) = mon_read_byte;
+	void (*old_mon_write_byte)(uintptr, uae_u32) = mon_write_byte;
+	
+	mon_read_byte = mon_read_byte_jit;
+	mon_write_byte = mon_write_byte_jit;
+	
+	char *arg[5] = {"mon", "-m", "-r", disasm_str, NULL};
+	mon(4, arg);
+	
+	mon_read_byte = old_mon_read_byte;
+	mon_write_byte = old_mon_write_byte;
+#endif
+}
+
+static void disasm_native_block(uint8 *start, size_t length)
+{
+	disasm_block(TARGET_NATIVE, start, length);
+}
+
+static void disasm_m68k_block(uint8 *start, size_t length)
+{
+	disasm_block(TARGET_M68K, start, length);
+}
+
+#ifdef HAVE_GET_WORD_UNSWAPPED
+# define DO_GET_OPCODE(a) (do_get_mem_word_unswapped((uae_u16 *)(a)))
+#else
+# define DO_GET_OPCODE(a) (do_get_mem_word((uae_u16 *)(a)))
+#endif
+
+#if JIT_DEBUG
+static uae_u8 *last_regs_pc_p = 0;
+static uae_u8 *last_compiled_block_addr = 0;
+
+void compiler_dumpstate(void)
+{
+	if (!JITDebug)
+		return;
+	
+	write_log("### Host addresses\n");
+	write_log("MEM_BASE    : %x\n", MEMBaseDiff);
+	write_log("PC_P        : %p\n", ®s.pc_p);
+	write_log("SPCFLAGS    : %p\n", ®s.spcflags);
+	write_log("D0-D7       : %p-%p\n", ®s.regs[0], ®s.regs[7]);
+	write_log("A0-A7       : %p-%p\n", ®s.regs[8], ®s.regs[15]);
+	write_log("\n");
+	
+	write_log("### M68k processor state\n");
+	m68k_dumpstate(0);
+	write_log("\n");
+	
+	write_log("### Block in Mac address space\n");
+	write_log("M68K block   : %p\n",
+			  (void *)(uintptr)get_virtual_address(last_regs_pc_p));
+	write_log("Native block : %p (%d bytes)\n",
+			  (void *)(uintptr)get_virtual_address(last_compiled_block_addr),
+			  get_blockinfo_addr(last_regs_pc_p)->direct_handler_size);
+	write_log("\n");
+}
+#endif
+
+static void compile_block(cpu_history* pc_hist, int blocklen)
+{
+    if (letit && compiled_code) {
+#if PROFILE_COMPILE_TIME
+	compile_count++;
+	clock_t start_time = clock();
+#endif
+#if JIT_DEBUG
+	bool disasm_block = false;
+#endif
+	
+	/* OK, here we need to 'compile' a block */
+	int i;
+	int r;
+	int was_comp=0;
+	uae_u8 liveflags[MAXRUN+1];
+#if USE_CHECKSUM_INFO
+	bool trace_in_rom = isinrom((uintptr)pc_hist[0].location);
+	uintptr max_pcp=(uintptr)pc_hist[blocklen - 1].location;
+	uintptr min_pcp=max_pcp;
+#else
+	uintptr max_pcp=(uintptr)pc_hist[0].location;
+	uintptr min_pcp=max_pcp;
+#endif
+	uae_u32 cl=cacheline(pc_hist[0].location);
+	void* specflags=(void*)®s.spcflags;
+	blockinfo* bi=NULL;
+	blockinfo* bi2;
+	int extra_len=0;
+
+	redo_current_block=0;
+	if (current_compile_p>=max_compile_start)
+	    flush_icache_hard(7);
+
+	alloc_blockinfos();
+
+	bi=get_blockinfo_addr_new(pc_hist[0].location,0);
+	bi2=get_blockinfo(cl);
+
+	optlev=bi->optlevel;
+	if (bi->status!=BI_INVALID) {
+	    Dif (bi!=bi2) { 
+		/* I don't think it can happen anymore. Shouldn't, in 
+		   any case. So let's make sure... */
+		write_log("WOOOWOO count=%d, ol=%d %p %p\n",
+		       bi->count,bi->optlevel,bi->handler_to_use,
+		       cache_tags[cl].handler);
+		abort();
+	    }
+
+	    Dif (bi->count!=-1 && bi->status!=BI_NEED_RECOMP) {
+		write_log("bi->count=%d, bi->status=%d\n",bi->count,bi->status);
+		/* What the heck? We are not supposed to be here! */
+		abort();
+	    }
+	}	
+	if (bi->count==-1) {
+	    optlev++;
+	    while (!optcount[optlev])
+		optlev++;
+	    bi->count=optcount[optlev]-1;
+	}
+	current_block_pc_p=(uintptr)pc_hist[0].location;
+	
+	remove_deps(bi); /* We are about to create new code */
+	bi->optlevel=optlev;
+	bi->pc_p=(uae_u8*)pc_hist[0].location;
+#if USE_CHECKSUM_INFO
+	free_checksum_info_chain(bi->csi);
+	bi->csi = NULL;
+#endif
+	
+	liveflags[blocklen]=0x1f; /* All flags needed afterwards */
+	i=blocklen;
+	while (i--) {
+	    uae_u16* currpcp=pc_hist[i].location;
+	    uae_u32 op=DO_GET_OPCODE(currpcp);
+
+#if USE_CHECKSUM_INFO
+		trace_in_rom = trace_in_rom && isinrom((uintptr)currpcp);
+		if (follow_const_jumps && is_const_jump(op)) {
+			checksum_info *csi = alloc_checksum_info();
+			csi->start_p = (uae_u8 *)min_pcp;
+			csi->length = max_pcp - min_pcp + LONGEST_68K_INST;
+			csi->next = bi->csi;
+			bi->csi = csi;
+			max_pcp = (uintptr)currpcp;
+		}
+		min_pcp = (uintptr)currpcp;
+#else
+	    if ((uintptr)currpcpmax_pcp)
+		max_pcp=(uintptr)currpcp;
+#endif
+
+		liveflags[i]=((liveflags[i+1]&
+			       (~prop[op].set_flags))|
+			      prop[op].use_flags);
+		if (prop[op].is_addx && (liveflags[i+1]&FLAG_Z)==0)
+		    liveflags[i]&= ~FLAG_Z;
+	}
+
+#if USE_CHECKSUM_INFO
+	checksum_info *csi = alloc_checksum_info();
+	csi->start_p = (uae_u8 *)min_pcp;
+	csi->length = max_pcp - min_pcp + LONGEST_68K_INST;
+	csi->next = bi->csi;
+	bi->csi = csi;
+#endif
+
+	bi->needed_flags=liveflags[0];
+
+	align_target(align_loops);
+	was_comp=0;
+
+	bi->direct_handler=(cpuop_func *)get_target();
+	set_dhtu(bi,bi->direct_handler);
+	bi->status=BI_COMPILING;
+	current_block_start_target=(uintptr)get_target();
+	
+	log_startblock();
+	
+	if (bi->count>=0) { /* Need to generate countdown code */
+	    raw_mov_l_mi((uintptr)®s.pc_p,(uintptr)pc_hist[0].location);
+	    raw_sub_l_mi((uintptr)&(bi->count),1);
+	    raw_jl((uintptr)popall_recompile_block);
+	}
+	if (optlev==0) { /* No need to actually translate */
+	    /* Execute normally without keeping stats */
+	    raw_mov_l_mi((uintptr)®s.pc_p,(uintptr)pc_hist[0].location);
+	    raw_jmp((uintptr)popall_exec_nostats); 
+	}
+	else {
+	    reg_alloc_run=0;
+	    next_pc_p=0;
+	    taken_pc_p=0;
+	    branch_cc=0;
+		
+	    comp_pc_p=(uae_u8*)pc_hist[0].location;
+	    init_comp();
+	    was_comp=1;
+
+#ifdef USE_CPU_EMUL_SERVICES
+	    raw_sub_l_mi((uintptr)&emulated_ticks,blocklen);
+	    raw_jcc_b_oponly(NATIVE_CC_GT);
+	    uae_s8 *branchadd=(uae_s8*)get_target();
+	    emit_byte(0);
+	    raw_call((uintptr)cpu_do_check_ticks);
+	    *branchadd=(uintptr)get_target()-((uintptr)branchadd+1);
+#endif
+
+#if JIT_DEBUG
+		if (JITDebug) {
+			raw_mov_l_mi((uintptr)&last_regs_pc_p,(uintptr)pc_hist[0].location);
+			raw_mov_l_mi((uintptr)&last_compiled_block_addr,current_block_start_target);
+		}
+#endif
+		
+	    for (i=0;i1) { 
+		    failure=0;
+		    if (!was_comp) {
+			comp_pc_p=(uae_u8*)pc_hist[i].location;
+			init_comp();
+		    }
+		    was_comp=1;
+
+		    comptbl[opcode](opcode);
+		    freescratch();
+		    if (!(liveflags[i+1] & FLAG_CZNV)) { 
+			/* We can forget about flags */
+			dont_care_flags();
+		    }
+#if INDIVIDUAL_INST 
+		    flush(1);
+		    nop();
+		    flush(1);
+		    was_comp=0;
+#endif
+		}
+		
+		if (failure) {
+		    if (was_comp) {
+			flush(1);
+			was_comp=0;
+		    }
+		    raw_mov_l_ri(REG_PAR1,(uae_u32)opcode);
+#if USE_NORMAL_CALLING_CONVENTION
+		    raw_push_l_r(REG_PAR1);
+#endif
+		    raw_mov_l_mi((uintptr)®s.pc_p,
+				 (uintptr)pc_hist[i].location);
+		    raw_call((uintptr)cputbl[opcode]);
+#if PROFILE_UNTRANSLATED_INSNS
+			// raw_cputbl_count[] is indexed with plain opcode (in m68k order)
+			raw_add_l_mi((uintptr)&raw_cputbl_count[cft_map(opcode)],1);
+#endif
+#if USE_NORMAL_CALLING_CONVENTION
+		    raw_inc_sp(4);
+#endif
+		    
+		    if (i < blocklen - 1) {
+			uae_s8* branchadd;
+			
+			raw_mov_l_rm(0,(uintptr)specflags);
+			raw_test_l_rr(0,0);
+			raw_jz_b_oponly();
+			branchadd=(uae_s8 *)get_target();
+			emit_byte(0);
+			raw_jmp((uintptr)popall_do_nothing);
+			*branchadd=(uintptr)get_target()-(uintptr)branchadd-1;
+		    }
+		}
+	    }
+#if 1 /* This isn't completely kosher yet; It really needs to be
+	 be integrated into a general inter-block-dependency scheme */
+	    if (next_pc_p && taken_pc_p &&
+		was_comp && taken_pc_p==current_block_pc_p) {
+		blockinfo* bi1=get_blockinfo_addr_new((void*)next_pc_p,0);
+		blockinfo* bi2=get_blockinfo_addr_new((void*)taken_pc_p,0);
+		uae_u8 x=bi1->needed_flags;
+		
+		if (x==0xff || 1) {  /* To be on the safe side */
+		    uae_u16* next=(uae_u16*)next_pc_p;
+		    uae_u32 op=DO_GET_OPCODE(next);
+
+		    x=0x1f;
+		    x&=(~prop[op].set_flags);
+		    x|=prop[op].use_flags;
+		}
+		
+		x|=bi2->needed_flags;
+		if (!(x & FLAG_CZNV)) { 
+		    /* We can forget about flags */
+		    dont_care_flags();
+		    extra_len+=2; /* The next instruction now is part of this
+				     block */
+		}
+		    
+	    }
+#endif
+		log_flush();
+
+	    if (next_pc_p) { /* A branch was registered */
+		uintptr t1=next_pc_p;
+		uintptr t2=taken_pc_p;
+		int     cc=branch_cc;
+		
+		uae_u32* branchadd;
+		uae_u32* tba;
+		bigstate tmp;
+		blockinfo* tbi;
+
+		if (taken_pc_penv))) {
+	    mark_callers_recompile(bi);
+	}
+
+	big_to_small_state(&live,&(bi->env));
+#endif
+
+#if USE_CHECKSUM_INFO
+	remove_from_list(bi);
+	if (trace_in_rom) {
+		// No need to checksum that block trace on cache invalidation
+		free_checksum_info_chain(bi->csi);
+		bi->csi = NULL;
+		add_to_dormant(bi);
+	}
+	else {
+	    calc_checksum(bi,&(bi->c1),&(bi->c2));
+		add_to_active(bi);
+	}
+#else
+	if (next_pc_p+extra_len>=max_pcp && 
+	    next_pc_p+extra_lenlen=max_pcp-min_pcp;
+	bi->min_pcp=min_pcp;
+	
+	remove_from_list(bi);
+	if (isinrom(min_pcp) && isinrom(max_pcp)) {
+	    add_to_dormant(bi); /* No need to checksum it on cache flush.
+				   Please don't start changing ROMs in
+				   flight! */
+	}
+	else {
+	    calc_checksum(bi,&(bi->c1),&(bi->c2));
+	    add_to_active(bi);
+	}
+#endif
+	
+	current_cache_size += get_target() - (uae_u8 *)current_compile_p;
+	
+#if JIT_DEBUG
+	if (JITDebug)
+		bi->direct_handler_size = get_target() - (uae_u8 *)current_block_start_target;
+	
+	if (JITDebug && disasm_block) {
+		uaecptr block_addr = start_pc + ((char *)pc_hist[0].location - (char *)start_pc_p);
+		D(bug("M68K block @ 0x%08x (%d insns)\n", block_addr, blocklen));
+		uae_u32 block_size = ((uae_u8 *)pc_hist[blocklen - 1].location - (uae_u8 *)pc_hist[0].location) + 1;
+		disasm_m68k_block((uae_u8 *)pc_hist[0].location, block_size);
+		D(bug("Compiled block @ 0x%08x\n", pc_hist[0].location));
+		disasm_native_block((uae_u8 *)current_block_start_target, bi->direct_handler_size);
+		getchar();
+	}
+#endif
+	
+	log_dump();
+	align_target(align_jumps);
+
+	/* This is the non-direct handler */
+	bi->handler=
+	    bi->handler_to_use=(cpuop_func *)get_target();
+	raw_cmp_l_mi((uintptr)®s.pc_p,(uintptr)pc_hist[0].location);
+	raw_jnz((uintptr)popall_cache_miss);
+	comp_pc_p=(uae_u8*)pc_hist[0].location;
+
+	bi->status=BI_FINALIZING;
+	init_comp();
+	match_states(bi);
+	flush(1);
+
+	raw_jmp((uintptr)bi->direct_handler);
+
+	current_compile_p=get_target();
+	raise_in_cl_list(bi);
+	
+	/* We will flush soon, anyway, so let's do it now */
+	if (current_compile_p>=max_compile_start)
+		flush_icache_hard(7);
+	
+	bi->status=BI_ACTIVE;
+	if (redo_current_block)
+	    block_need_recompile(bi);
+	
+#if PROFILE_COMPILE_TIME
+	compile_time += (clock() - start_time);
+#endif
+    }
+
+    /* Account for compilation time */
+    cpu_do_check_ticks();
+}
+
+void do_nothing(void)
+{
+    /* What did you expect this to do? */
+}
+
+void exec_nostats(void)
+{
+	for (;;)  { 
+		uae_u32 opcode = GET_OPCODE;
+#if FLIGHT_RECORDER
+		m68k_record_step(m68k_getpc());
+#endif
+		(*cpufunctbl[opcode])(opcode);
+		cpu_check_ticks();
+		if (end_block(opcode) || SPCFLAGS_TEST(SPCFLAG_ALL)) {
+			return; /* We will deal with the spcflags in the caller */
+		}
+	}
+}
+
+void execute_normal(void)
+{
+	if (!check_for_cache_miss()) {
+		cpu_history pc_hist[MAXRUN];
+		int blocklen = 0;
+#if REAL_ADDRESSING || DIRECT_ADDRESSING
+		start_pc_p = regs.pc_p;
+		start_pc = get_virtual_address(regs.pc_p);
+#else
+		start_pc_p = regs.pc_oldp;  
+		start_pc = regs.pc; 
+#endif
+		for (;;)  { /* Take note: This is the do-it-normal loop */
+			pc_hist[blocklen++].location = (uae_u16 *)regs.pc_p;
+			uae_u32 opcode = GET_OPCODE;
+#if FLIGHT_RECORDER
+			m68k_record_step(m68k_getpc());
+#endif
+			(*cpufunctbl[opcode])(opcode);
+			cpu_check_ticks();
+			if (end_block(opcode) || SPCFLAGS_TEST(SPCFLAG_ALL) || blocklen>=MAXRUN) {
+				compile_block(pc_hist, blocklen);
+				return; /* We will deal with the spcflags in the caller */
+			}
+			/* No need to check regs.spcflags, because if they were set,
+			we'd have ended up inside that "if" */
+		}
+	}
+}
+
+typedef void (*compiled_handler)(void);
+
+static void m68k_do_compile_execute(void)
+{
+	for (;;) {
+		((compiled_handler)(pushall_call_handler))();
+		/* Whenever we return from that, we should check spcflags */
+		if (SPCFLAGS_TEST(SPCFLAG_ALL)) {
+			if (m68k_do_specialties ())
+				return;
+		}
+	}
+}
+
+void m68k_compile_execute (void)
+{
+    for (;;) {
+	  if (quit_program)
+		break;
+	  m68k_do_compile_execute();
+    }
+}
diff --git a/src/cpu/jit/comptbl.h b/src/cpu/jit/comptbl.h
new file mode 100644
index 0000000..b0e9af7
--- /dev/null
+++ b/src/cpu/jit/comptbl.h
@@ -0,0 +1,2823 @@
+#ifdef NOFLAGS_SUPPORT
+/* 68040 */
+extern const struct comptbl op_smalltbl_0_nf[];
+#endif
+extern const struct comptbl op_smalltbl_0_comp_nf[];
+extern const struct comptbl op_smalltbl_0_comp_ff[];
+extern compop_func op_0_0_comp_ff;
+extern compop_func op_10_0_comp_ff;
+extern compop_func op_18_0_comp_ff;
+extern compop_func op_20_0_comp_ff;
+extern compop_func op_28_0_comp_ff;
+extern compop_func op_30_0_comp_ff;
+extern compop_func op_38_0_comp_ff;
+extern compop_func op_39_0_comp_ff;
+extern compop_func op_40_0_comp_ff;
+extern compop_func op_50_0_comp_ff;
+extern compop_func op_58_0_comp_ff;
+extern compop_func op_60_0_comp_ff;
+extern compop_func op_68_0_comp_ff;
+extern compop_func op_70_0_comp_ff;
+extern compop_func op_78_0_comp_ff;
+extern compop_func op_79_0_comp_ff;
+extern compop_func op_80_0_comp_ff;
+extern compop_func op_90_0_comp_ff;
+extern compop_func op_98_0_comp_ff;
+extern compop_func op_a0_0_comp_ff;
+extern compop_func op_a8_0_comp_ff;
+extern compop_func op_b0_0_comp_ff;
+extern compop_func op_b8_0_comp_ff;
+extern compop_func op_b9_0_comp_ff;
+extern compop_func op_100_0_comp_ff;
+extern compop_func op_110_0_comp_ff;
+extern compop_func op_118_0_comp_ff;
+extern compop_func op_120_0_comp_ff;
+extern compop_func op_128_0_comp_ff;
+extern compop_func op_130_0_comp_ff;
+extern compop_func op_138_0_comp_ff;
+extern compop_func op_139_0_comp_ff;
+extern compop_func op_13a_0_comp_ff;
+extern compop_func op_13b_0_comp_ff;
+extern compop_func op_13c_0_comp_ff;
+extern compop_func op_140_0_comp_ff;
+extern compop_func op_150_0_comp_ff;
+extern compop_func op_158_0_comp_ff;
+extern compop_func op_160_0_comp_ff;
+extern compop_func op_168_0_comp_ff;
+extern compop_func op_170_0_comp_ff;
+extern compop_func op_178_0_comp_ff;
+extern compop_func op_179_0_comp_ff;
+extern compop_func op_17a_0_comp_ff;
+extern compop_func op_17b_0_comp_ff;
+extern compop_func op_180_0_comp_ff;
+extern compop_func op_190_0_comp_ff;
+extern compop_func op_198_0_comp_ff;
+extern compop_func op_1a0_0_comp_ff;
+extern compop_func op_1a8_0_comp_ff;
+extern compop_func op_1b0_0_comp_ff;
+extern compop_func op_1b8_0_comp_ff;
+extern compop_func op_1b9_0_comp_ff;
+extern compop_func op_1ba_0_comp_ff;
+extern compop_func op_1bb_0_comp_ff;
+extern compop_func op_1c0_0_comp_ff;
+extern compop_func op_1d0_0_comp_ff;
+extern compop_func op_1d8_0_comp_ff;
+extern compop_func op_1e0_0_comp_ff;
+extern compop_func op_1e8_0_comp_ff;
+extern compop_func op_1f0_0_comp_ff;
+extern compop_func op_1f8_0_comp_ff;
+extern compop_func op_1f9_0_comp_ff;
+extern compop_func op_1fa_0_comp_ff;
+extern compop_func op_1fb_0_comp_ff;
+extern compop_func op_200_0_comp_ff;
+extern compop_func op_210_0_comp_ff;
+extern compop_func op_218_0_comp_ff;
+extern compop_func op_220_0_comp_ff;
+extern compop_func op_228_0_comp_ff;
+extern compop_func op_230_0_comp_ff;
+extern compop_func op_238_0_comp_ff;
+extern compop_func op_239_0_comp_ff;
+extern compop_func op_240_0_comp_ff;
+extern compop_func op_250_0_comp_ff;
+extern compop_func op_258_0_comp_ff;
+extern compop_func op_260_0_comp_ff;
+extern compop_func op_268_0_comp_ff;
+extern compop_func op_270_0_comp_ff;
+extern compop_func op_278_0_comp_ff;
+extern compop_func op_279_0_comp_ff;
+extern compop_func op_280_0_comp_ff;
+extern compop_func op_290_0_comp_ff;
+extern compop_func op_298_0_comp_ff;
+extern compop_func op_2a0_0_comp_ff;
+extern compop_func op_2a8_0_comp_ff;
+extern compop_func op_2b0_0_comp_ff;
+extern compop_func op_2b8_0_comp_ff;
+extern compop_func op_2b9_0_comp_ff;
+extern compop_func op_400_0_comp_ff;
+extern compop_func op_410_0_comp_ff;
+extern compop_func op_418_0_comp_ff;
+extern compop_func op_420_0_comp_ff;
+extern compop_func op_428_0_comp_ff;
+extern compop_func op_430_0_comp_ff;
+extern compop_func op_438_0_comp_ff;
+extern compop_func op_439_0_comp_ff;
+extern compop_func op_440_0_comp_ff;
+extern compop_func op_450_0_comp_ff;
+extern compop_func op_458_0_comp_ff;
+extern compop_func op_460_0_comp_ff;
+extern compop_func op_468_0_comp_ff;
+extern compop_func op_470_0_comp_ff;
+extern compop_func op_478_0_comp_ff;
+extern compop_func op_479_0_comp_ff;
+extern compop_func op_480_0_comp_ff;
+extern compop_func op_490_0_comp_ff;
+extern compop_func op_498_0_comp_ff;
+extern compop_func op_4a0_0_comp_ff;
+extern compop_func op_4a8_0_comp_ff;
+extern compop_func op_4b0_0_comp_ff;
+extern compop_func op_4b8_0_comp_ff;
+extern compop_func op_4b9_0_comp_ff;
+extern compop_func op_600_0_comp_ff;
+extern compop_func op_610_0_comp_ff;
+extern compop_func op_618_0_comp_ff;
+extern compop_func op_620_0_comp_ff;
+extern compop_func op_628_0_comp_ff;
+extern compop_func op_630_0_comp_ff;
+extern compop_func op_638_0_comp_ff;
+extern compop_func op_639_0_comp_ff;
+extern compop_func op_640_0_comp_ff;
+extern compop_func op_650_0_comp_ff;
+extern compop_func op_658_0_comp_ff;
+extern compop_func op_660_0_comp_ff;
+extern compop_func op_668_0_comp_ff;
+extern compop_func op_670_0_comp_ff;
+extern compop_func op_678_0_comp_ff;
+extern compop_func op_679_0_comp_ff;
+extern compop_func op_680_0_comp_ff;
+extern compop_func op_690_0_comp_ff;
+extern compop_func op_698_0_comp_ff;
+extern compop_func op_6a0_0_comp_ff;
+extern compop_func op_6a8_0_comp_ff;
+extern compop_func op_6b0_0_comp_ff;
+extern compop_func op_6b8_0_comp_ff;
+extern compop_func op_6b9_0_comp_ff;
+extern compop_func op_800_0_comp_ff;
+extern compop_func op_810_0_comp_ff;
+extern compop_func op_818_0_comp_ff;
+extern compop_func op_820_0_comp_ff;
+extern compop_func op_828_0_comp_ff;
+extern compop_func op_830_0_comp_ff;
+extern compop_func op_838_0_comp_ff;
+extern compop_func op_839_0_comp_ff;
+extern compop_func op_83a_0_comp_ff;
+extern compop_func op_83b_0_comp_ff;
+extern compop_func op_840_0_comp_ff;
+extern compop_func op_850_0_comp_ff;
+extern compop_func op_858_0_comp_ff;
+extern compop_func op_860_0_comp_ff;
+extern compop_func op_868_0_comp_ff;
+extern compop_func op_870_0_comp_ff;
+extern compop_func op_878_0_comp_ff;
+extern compop_func op_879_0_comp_ff;
+extern compop_func op_87a_0_comp_ff;
+extern compop_func op_87b_0_comp_ff;
+extern compop_func op_880_0_comp_ff;
+extern compop_func op_890_0_comp_ff;
+extern compop_func op_898_0_comp_ff;
+extern compop_func op_8a0_0_comp_ff;
+extern compop_func op_8a8_0_comp_ff;
+extern compop_func op_8b0_0_comp_ff;
+extern compop_func op_8b8_0_comp_ff;
+extern compop_func op_8b9_0_comp_ff;
+extern compop_func op_8ba_0_comp_ff;
+extern compop_func op_8bb_0_comp_ff;
+extern compop_func op_8c0_0_comp_ff;
+extern compop_func op_8d0_0_comp_ff;
+extern compop_func op_8d8_0_comp_ff;
+extern compop_func op_8e0_0_comp_ff;
+extern compop_func op_8e8_0_comp_ff;
+extern compop_func op_8f0_0_comp_ff;
+extern compop_func op_8f8_0_comp_ff;
+extern compop_func op_8f9_0_comp_ff;
+extern compop_func op_8fa_0_comp_ff;
+extern compop_func op_8fb_0_comp_ff;
+extern compop_func op_a00_0_comp_ff;
+extern compop_func op_a10_0_comp_ff;
+extern compop_func op_a18_0_comp_ff;
+extern compop_func op_a20_0_comp_ff;
+extern compop_func op_a28_0_comp_ff;
+extern compop_func op_a30_0_comp_ff;
+extern compop_func op_a38_0_comp_ff;
+extern compop_func op_a39_0_comp_ff;
+extern compop_func op_a40_0_comp_ff;
+extern compop_func op_a50_0_comp_ff;
+extern compop_func op_a58_0_comp_ff;
+extern compop_func op_a60_0_comp_ff;
+extern compop_func op_a68_0_comp_ff;
+extern compop_func op_a70_0_comp_ff;
+extern compop_func op_a78_0_comp_ff;
+extern compop_func op_a79_0_comp_ff;
+extern compop_func op_a80_0_comp_ff;
+extern compop_func op_a90_0_comp_ff;
+extern compop_func op_a98_0_comp_ff;
+extern compop_func op_aa0_0_comp_ff;
+extern compop_func op_aa8_0_comp_ff;
+extern compop_func op_ab0_0_comp_ff;
+extern compop_func op_ab8_0_comp_ff;
+extern compop_func op_ab9_0_comp_ff;
+extern compop_func op_c00_0_comp_ff;
+extern compop_func op_c10_0_comp_ff;
+extern compop_func op_c18_0_comp_ff;
+extern compop_func op_c20_0_comp_ff;
+extern compop_func op_c28_0_comp_ff;
+extern compop_func op_c30_0_comp_ff;
+extern compop_func op_c38_0_comp_ff;
+extern compop_func op_c39_0_comp_ff;
+extern compop_func op_c3a_0_comp_ff;
+extern compop_func op_c3b_0_comp_ff;
+extern compop_func op_c40_0_comp_ff;
+extern compop_func op_c50_0_comp_ff;
+extern compop_func op_c58_0_comp_ff;
+extern compop_func op_c60_0_comp_ff;
+extern compop_func op_c68_0_comp_ff;
+extern compop_func op_c70_0_comp_ff;
+extern compop_func op_c78_0_comp_ff;
+extern compop_func op_c79_0_comp_ff;
+extern compop_func op_c7a_0_comp_ff;
+extern compop_func op_c7b_0_comp_ff;
+extern compop_func op_c80_0_comp_ff;
+extern compop_func op_c90_0_comp_ff;
+extern compop_func op_c98_0_comp_ff;
+extern compop_func op_ca0_0_comp_ff;
+extern compop_func op_ca8_0_comp_ff;
+extern compop_func op_cb0_0_comp_ff;
+extern compop_func op_cb8_0_comp_ff;
+extern compop_func op_cb9_0_comp_ff;
+extern compop_func op_cba_0_comp_ff;
+extern compop_func op_cbb_0_comp_ff;
+extern compop_func op_1000_0_comp_ff;
+extern compop_func op_1010_0_comp_ff;
+extern compop_func op_1018_0_comp_ff;
+extern compop_func op_1020_0_comp_ff;
+extern compop_func op_1028_0_comp_ff;
+extern compop_func op_1030_0_comp_ff;
+extern compop_func op_1038_0_comp_ff;
+extern compop_func op_1039_0_comp_ff;
+extern compop_func op_103a_0_comp_ff;
+extern compop_func op_103b_0_comp_ff;
+extern compop_func op_103c_0_comp_ff;
+extern compop_func op_1080_0_comp_ff;
+extern compop_func op_1090_0_comp_ff;
+extern compop_func op_1098_0_comp_ff;
+extern compop_func op_10a0_0_comp_ff;
+extern compop_func op_10a8_0_comp_ff;
+extern compop_func op_10b0_0_comp_ff;
+extern compop_func op_10b8_0_comp_ff;
+extern compop_func op_10b9_0_comp_ff;
+extern compop_func op_10ba_0_comp_ff;
+extern compop_func op_10bb_0_comp_ff;
+extern compop_func op_10bc_0_comp_ff;
+extern compop_func op_10c0_0_comp_ff;
+extern compop_func op_10d0_0_comp_ff;
+extern compop_func op_10d8_0_comp_ff;
+extern compop_func op_10e0_0_comp_ff;
+extern compop_func op_10e8_0_comp_ff;
+extern compop_func op_10f0_0_comp_ff;
+extern compop_func op_10f8_0_comp_ff;
+extern compop_func op_10f9_0_comp_ff;
+extern compop_func op_10fa_0_comp_ff;
+extern compop_func op_10fb_0_comp_ff;
+extern compop_func op_10fc_0_comp_ff;
+extern compop_func op_1100_0_comp_ff;
+extern compop_func op_1110_0_comp_ff;
+extern compop_func op_1118_0_comp_ff;
+extern compop_func op_1120_0_comp_ff;
+extern compop_func op_1128_0_comp_ff;
+extern compop_func op_1130_0_comp_ff;
+extern compop_func op_1138_0_comp_ff;
+extern compop_func op_1139_0_comp_ff;
+extern compop_func op_113a_0_comp_ff;
+extern compop_func op_113b_0_comp_ff;
+extern compop_func op_113c_0_comp_ff;
+extern compop_func op_1140_0_comp_ff;
+extern compop_func op_1150_0_comp_ff;
+extern compop_func op_1158_0_comp_ff;
+extern compop_func op_1160_0_comp_ff;
+extern compop_func op_1168_0_comp_ff;
+extern compop_func op_1170_0_comp_ff;
+extern compop_func op_1178_0_comp_ff;
+extern compop_func op_1179_0_comp_ff;
+extern compop_func op_117a_0_comp_ff;
+extern compop_func op_117b_0_comp_ff;
+extern compop_func op_117c_0_comp_ff;
+extern compop_func op_1180_0_comp_ff;
+extern compop_func op_1190_0_comp_ff;
+extern compop_func op_1198_0_comp_ff;
+extern compop_func op_11a0_0_comp_ff;
+extern compop_func op_11a8_0_comp_ff;
+extern compop_func op_11b0_0_comp_ff;
+extern compop_func op_11b8_0_comp_ff;
+extern compop_func op_11b9_0_comp_ff;
+extern compop_func op_11ba_0_comp_ff;
+extern compop_func op_11bb_0_comp_ff;
+extern compop_func op_11bc_0_comp_ff;
+extern compop_func op_11c0_0_comp_ff;
+extern compop_func op_11d0_0_comp_ff;
+extern compop_func op_11d8_0_comp_ff;
+extern compop_func op_11e0_0_comp_ff;
+extern compop_func op_11e8_0_comp_ff;
+extern compop_func op_11f0_0_comp_ff;
+extern compop_func op_11f8_0_comp_ff;
+extern compop_func op_11f9_0_comp_ff;
+extern compop_func op_11fa_0_comp_ff;
+extern compop_func op_11fb_0_comp_ff;
+extern compop_func op_11fc_0_comp_ff;
+extern compop_func op_13c0_0_comp_ff;
+extern compop_func op_13d0_0_comp_ff;
+extern compop_func op_13d8_0_comp_ff;
+extern compop_func op_13e0_0_comp_ff;
+extern compop_func op_13e8_0_comp_ff;
+extern compop_func op_13f0_0_comp_ff;
+extern compop_func op_13f8_0_comp_ff;
+extern compop_func op_13f9_0_comp_ff;
+extern compop_func op_13fa_0_comp_ff;
+extern compop_func op_13fb_0_comp_ff;
+extern compop_func op_13fc_0_comp_ff;
+extern compop_func op_2000_0_comp_ff;
+extern compop_func op_2008_0_comp_ff;
+extern compop_func op_2010_0_comp_ff;
+extern compop_func op_2018_0_comp_ff;
+extern compop_func op_2020_0_comp_ff;
+extern compop_func op_2028_0_comp_ff;
+extern compop_func op_2030_0_comp_ff;
+extern compop_func op_2038_0_comp_ff;
+extern compop_func op_2039_0_comp_ff;
+extern compop_func op_203a_0_comp_ff;
+extern compop_func op_203b_0_comp_ff;
+extern compop_func op_203c_0_comp_ff;
+extern compop_func op_2040_0_comp_ff;
+extern compop_func op_2048_0_comp_ff;
+extern compop_func op_2050_0_comp_ff;
+extern compop_func op_2058_0_comp_ff;
+extern compop_func op_2060_0_comp_ff;
+extern compop_func op_2068_0_comp_ff;
+extern compop_func op_2070_0_comp_ff;
+extern compop_func op_2078_0_comp_ff;
+extern compop_func op_2079_0_comp_ff;
+extern compop_func op_207a_0_comp_ff;
+extern compop_func op_207b_0_comp_ff;
+extern compop_func op_207c_0_comp_ff;
+extern compop_func op_2080_0_comp_ff;
+extern compop_func op_2088_0_comp_ff;
+extern compop_func op_2090_0_comp_ff;
+extern compop_func op_2098_0_comp_ff;
+extern compop_func op_20a0_0_comp_ff;
+extern compop_func op_20a8_0_comp_ff;
+extern compop_func op_20b0_0_comp_ff;
+extern compop_func op_20b8_0_comp_ff;
+extern compop_func op_20b9_0_comp_ff;
+extern compop_func op_20ba_0_comp_ff;
+extern compop_func op_20bb_0_comp_ff;
+extern compop_func op_20bc_0_comp_ff;
+extern compop_func op_20c0_0_comp_ff;
+extern compop_func op_20c8_0_comp_ff;
+extern compop_func op_20d0_0_comp_ff;
+extern compop_func op_20d8_0_comp_ff;
+extern compop_func op_20e0_0_comp_ff;
+extern compop_func op_20e8_0_comp_ff;
+extern compop_func op_20f0_0_comp_ff;
+extern compop_func op_20f8_0_comp_ff;
+extern compop_func op_20f9_0_comp_ff;
+extern compop_func op_20fa_0_comp_ff;
+extern compop_func op_20fb_0_comp_ff;
+extern compop_func op_20fc_0_comp_ff;
+extern compop_func op_2100_0_comp_ff;
+extern compop_func op_2108_0_comp_ff;
+extern compop_func op_2110_0_comp_ff;
+extern compop_func op_2118_0_comp_ff;
+extern compop_func op_2120_0_comp_ff;
+extern compop_func op_2128_0_comp_ff;
+extern compop_func op_2130_0_comp_ff;
+extern compop_func op_2138_0_comp_ff;
+extern compop_func op_2139_0_comp_ff;
+extern compop_func op_213a_0_comp_ff;
+extern compop_func op_213b_0_comp_ff;
+extern compop_func op_213c_0_comp_ff;
+extern compop_func op_2140_0_comp_ff;
+extern compop_func op_2148_0_comp_ff;
+extern compop_func op_2150_0_comp_ff;
+extern compop_func op_2158_0_comp_ff;
+extern compop_func op_2160_0_comp_ff;
+extern compop_func op_2168_0_comp_ff;
+extern compop_func op_2170_0_comp_ff;
+extern compop_func op_2178_0_comp_ff;
+extern compop_func op_2179_0_comp_ff;
+extern compop_func op_217a_0_comp_ff;
+extern compop_func op_217b_0_comp_ff;
+extern compop_func op_217c_0_comp_ff;
+extern compop_func op_2180_0_comp_ff;
+extern compop_func op_2188_0_comp_ff;
+extern compop_func op_2190_0_comp_ff;
+extern compop_func op_2198_0_comp_ff;
+extern compop_func op_21a0_0_comp_ff;
+extern compop_func op_21a8_0_comp_ff;
+extern compop_func op_21b0_0_comp_ff;
+extern compop_func op_21b8_0_comp_ff;
+extern compop_func op_21b9_0_comp_ff;
+extern compop_func op_21ba_0_comp_ff;
+extern compop_func op_21bb_0_comp_ff;
+extern compop_func op_21bc_0_comp_ff;
+extern compop_func op_21c0_0_comp_ff;
+extern compop_func op_21c8_0_comp_ff;
+extern compop_func op_21d0_0_comp_ff;
+extern compop_func op_21d8_0_comp_ff;
+extern compop_func op_21e0_0_comp_ff;
+extern compop_func op_21e8_0_comp_ff;
+extern compop_func op_21f0_0_comp_ff;
+extern compop_func op_21f8_0_comp_ff;
+extern compop_func op_21f9_0_comp_ff;
+extern compop_func op_21fa_0_comp_ff;
+extern compop_func op_21fb_0_comp_ff;
+extern compop_func op_21fc_0_comp_ff;
+extern compop_func op_23c0_0_comp_ff;
+extern compop_func op_23c8_0_comp_ff;
+extern compop_func op_23d0_0_comp_ff;
+extern compop_func op_23d8_0_comp_ff;
+extern compop_func op_23e0_0_comp_ff;
+extern compop_func op_23e8_0_comp_ff;
+extern compop_func op_23f0_0_comp_ff;
+extern compop_func op_23f8_0_comp_ff;
+extern compop_func op_23f9_0_comp_ff;
+extern compop_func op_23fa_0_comp_ff;
+extern compop_func op_23fb_0_comp_ff;
+extern compop_func op_23fc_0_comp_ff;
+extern compop_func op_3000_0_comp_ff;
+extern compop_func op_3008_0_comp_ff;
+extern compop_func op_3010_0_comp_ff;
+extern compop_func op_3018_0_comp_ff;
+extern compop_func op_3020_0_comp_ff;
+extern compop_func op_3028_0_comp_ff;
+extern compop_func op_3030_0_comp_ff;
+extern compop_func op_3038_0_comp_ff;
+extern compop_func op_3039_0_comp_ff;
+extern compop_func op_303a_0_comp_ff;
+extern compop_func op_303b_0_comp_ff;
+extern compop_func op_303c_0_comp_ff;
+extern compop_func op_3040_0_comp_ff;
+extern compop_func op_3048_0_comp_ff;
+extern compop_func op_3050_0_comp_ff;
+extern compop_func op_3058_0_comp_ff;
+extern compop_func op_3060_0_comp_ff;
+extern compop_func op_3068_0_comp_ff;
+extern compop_func op_3070_0_comp_ff;
+extern compop_func op_3078_0_comp_ff;
+extern compop_func op_3079_0_comp_ff;
+extern compop_func op_307a_0_comp_ff;
+extern compop_func op_307b_0_comp_ff;
+extern compop_func op_307c_0_comp_ff;
+extern compop_func op_3080_0_comp_ff;
+extern compop_func op_3088_0_comp_ff;
+extern compop_func op_3090_0_comp_ff;
+extern compop_func op_3098_0_comp_ff;
+extern compop_func op_30a0_0_comp_ff;
+extern compop_func op_30a8_0_comp_ff;
+extern compop_func op_30b0_0_comp_ff;
+extern compop_func op_30b8_0_comp_ff;
+extern compop_func op_30b9_0_comp_ff;
+extern compop_func op_30ba_0_comp_ff;
+extern compop_func op_30bb_0_comp_ff;
+extern compop_func op_30bc_0_comp_ff;
+extern compop_func op_30c0_0_comp_ff;
+extern compop_func op_30c8_0_comp_ff;
+extern compop_func op_30d0_0_comp_ff;
+extern compop_func op_30d8_0_comp_ff;
+extern compop_func op_30e0_0_comp_ff;
+extern compop_func op_30e8_0_comp_ff;
+extern compop_func op_30f0_0_comp_ff;
+extern compop_func op_30f8_0_comp_ff;
+extern compop_func op_30f9_0_comp_ff;
+extern compop_func op_30fa_0_comp_ff;
+extern compop_func op_30fb_0_comp_ff;
+extern compop_func op_30fc_0_comp_ff;
+extern compop_func op_3100_0_comp_ff;
+extern compop_func op_3108_0_comp_ff;
+extern compop_func op_3110_0_comp_ff;
+extern compop_func op_3118_0_comp_ff;
+extern compop_func op_3120_0_comp_ff;
+extern compop_func op_3128_0_comp_ff;
+extern compop_func op_3130_0_comp_ff;
+extern compop_func op_3138_0_comp_ff;
+extern compop_func op_3139_0_comp_ff;
+extern compop_func op_313a_0_comp_ff;
+extern compop_func op_313b_0_comp_ff;
+extern compop_func op_313c_0_comp_ff;
+extern compop_func op_3140_0_comp_ff;
+extern compop_func op_3148_0_comp_ff;
+extern compop_func op_3150_0_comp_ff;
+extern compop_func op_3158_0_comp_ff;
+extern compop_func op_3160_0_comp_ff;
+extern compop_func op_3168_0_comp_ff;
+extern compop_func op_3170_0_comp_ff;
+extern compop_func op_3178_0_comp_ff;
+extern compop_func op_3179_0_comp_ff;
+extern compop_func op_317a_0_comp_ff;
+extern compop_func op_317b_0_comp_ff;
+extern compop_func op_317c_0_comp_ff;
+extern compop_func op_3180_0_comp_ff;
+extern compop_func op_3188_0_comp_ff;
+extern compop_func op_3190_0_comp_ff;
+extern compop_func op_3198_0_comp_ff;
+extern compop_func op_31a0_0_comp_ff;
+extern compop_func op_31a8_0_comp_ff;
+extern compop_func op_31b0_0_comp_ff;
+extern compop_func op_31b8_0_comp_ff;
+extern compop_func op_31b9_0_comp_ff;
+extern compop_func op_31ba_0_comp_ff;
+extern compop_func op_31bb_0_comp_ff;
+extern compop_func op_31bc_0_comp_ff;
+extern compop_func op_31c0_0_comp_ff;
+extern compop_func op_31c8_0_comp_ff;
+extern compop_func op_31d0_0_comp_ff;
+extern compop_func op_31d8_0_comp_ff;
+extern compop_func op_31e0_0_comp_ff;
+extern compop_func op_31e8_0_comp_ff;
+extern compop_func op_31f0_0_comp_ff;
+extern compop_func op_31f8_0_comp_ff;
+extern compop_func op_31f9_0_comp_ff;
+extern compop_func op_31fa_0_comp_ff;
+extern compop_func op_31fb_0_comp_ff;
+extern compop_func op_31fc_0_comp_ff;
+extern compop_func op_33c0_0_comp_ff;
+extern compop_func op_33c8_0_comp_ff;
+extern compop_func op_33d0_0_comp_ff;
+extern compop_func op_33d8_0_comp_ff;
+extern compop_func op_33e0_0_comp_ff;
+extern compop_func op_33e8_0_comp_ff;
+extern compop_func op_33f0_0_comp_ff;
+extern compop_func op_33f8_0_comp_ff;
+extern compop_func op_33f9_0_comp_ff;
+extern compop_func op_33fa_0_comp_ff;
+extern compop_func op_33fb_0_comp_ff;
+extern compop_func op_33fc_0_comp_ff;
+extern compop_func op_4000_0_comp_ff;
+extern compop_func op_4010_0_comp_ff;
+extern compop_func op_4018_0_comp_ff;
+extern compop_func op_4020_0_comp_ff;
+extern compop_func op_4028_0_comp_ff;
+extern compop_func op_4030_0_comp_ff;
+extern compop_func op_4038_0_comp_ff;
+extern compop_func op_4039_0_comp_ff;
+extern compop_func op_4040_0_comp_ff;
+extern compop_func op_4050_0_comp_ff;
+extern compop_func op_4058_0_comp_ff;
+extern compop_func op_4060_0_comp_ff;
+extern compop_func op_4068_0_comp_ff;
+extern compop_func op_4070_0_comp_ff;
+extern compop_func op_4078_0_comp_ff;
+extern compop_func op_4079_0_comp_ff;
+extern compop_func op_4080_0_comp_ff;
+extern compop_func op_4090_0_comp_ff;
+extern compop_func op_4098_0_comp_ff;
+extern compop_func op_40a0_0_comp_ff;
+extern compop_func op_40a8_0_comp_ff;
+extern compop_func op_40b0_0_comp_ff;
+extern compop_func op_40b8_0_comp_ff;
+extern compop_func op_40b9_0_comp_ff;
+extern compop_func op_41d0_0_comp_ff;
+extern compop_func op_41e8_0_comp_ff;
+extern compop_func op_41f0_0_comp_ff;
+extern compop_func op_41f8_0_comp_ff;
+extern compop_func op_41f9_0_comp_ff;
+extern compop_func op_41fa_0_comp_ff;
+extern compop_func op_41fb_0_comp_ff;
+extern compop_func op_4200_0_comp_ff;
+extern compop_func op_4210_0_comp_ff;
+extern compop_func op_4218_0_comp_ff;
+extern compop_func op_4220_0_comp_ff;
+extern compop_func op_4228_0_comp_ff;
+extern compop_func op_4230_0_comp_ff;
+extern compop_func op_4238_0_comp_ff;
+extern compop_func op_4239_0_comp_ff;
+extern compop_func op_4240_0_comp_ff;
+extern compop_func op_4250_0_comp_ff;
+extern compop_func op_4258_0_comp_ff;
+extern compop_func op_4260_0_comp_ff;
+extern compop_func op_4268_0_comp_ff;
+extern compop_func op_4270_0_comp_ff;
+extern compop_func op_4278_0_comp_ff;
+extern compop_func op_4279_0_comp_ff;
+extern compop_func op_4280_0_comp_ff;
+extern compop_func op_4290_0_comp_ff;
+extern compop_func op_4298_0_comp_ff;
+extern compop_func op_42a0_0_comp_ff;
+extern compop_func op_42a8_0_comp_ff;
+extern compop_func op_42b0_0_comp_ff;
+extern compop_func op_42b8_0_comp_ff;
+extern compop_func op_42b9_0_comp_ff;
+extern compop_func op_4400_0_comp_ff;
+extern compop_func op_4410_0_comp_ff;
+extern compop_func op_4418_0_comp_ff;
+extern compop_func op_4420_0_comp_ff;
+extern compop_func op_4428_0_comp_ff;
+extern compop_func op_4430_0_comp_ff;
+extern compop_func op_4438_0_comp_ff;
+extern compop_func op_4439_0_comp_ff;
+extern compop_func op_4440_0_comp_ff;
+extern compop_func op_4450_0_comp_ff;
+extern compop_func op_4458_0_comp_ff;
+extern compop_func op_4460_0_comp_ff;
+extern compop_func op_4468_0_comp_ff;
+extern compop_func op_4470_0_comp_ff;
+extern compop_func op_4478_0_comp_ff;
+extern compop_func op_4479_0_comp_ff;
+extern compop_func op_4480_0_comp_ff;
+extern compop_func op_4490_0_comp_ff;
+extern compop_func op_4498_0_comp_ff;
+extern compop_func op_44a0_0_comp_ff;
+extern compop_func op_44a8_0_comp_ff;
+extern compop_func op_44b0_0_comp_ff;
+extern compop_func op_44b8_0_comp_ff;
+extern compop_func op_44b9_0_comp_ff;
+extern compop_func op_4600_0_comp_ff;
+extern compop_func op_4610_0_comp_ff;
+extern compop_func op_4618_0_comp_ff;
+extern compop_func op_4620_0_comp_ff;
+extern compop_func op_4628_0_comp_ff;
+extern compop_func op_4630_0_comp_ff;
+extern compop_func op_4638_0_comp_ff;
+extern compop_func op_4639_0_comp_ff;
+extern compop_func op_4640_0_comp_ff;
+extern compop_func op_4650_0_comp_ff;
+extern compop_func op_4658_0_comp_ff;
+extern compop_func op_4660_0_comp_ff;
+extern compop_func op_4668_0_comp_ff;
+extern compop_func op_4670_0_comp_ff;
+extern compop_func op_4678_0_comp_ff;
+extern compop_func op_4679_0_comp_ff;
+extern compop_func op_4680_0_comp_ff;
+extern compop_func op_4690_0_comp_ff;
+extern compop_func op_4698_0_comp_ff;
+extern compop_func op_46a0_0_comp_ff;
+extern compop_func op_46a8_0_comp_ff;
+extern compop_func op_46b0_0_comp_ff;
+extern compop_func op_46b8_0_comp_ff;
+extern compop_func op_46b9_0_comp_ff;
+extern compop_func op_4808_0_comp_ff;
+extern compop_func op_4840_0_comp_ff;
+extern compop_func op_4850_0_comp_ff;
+extern compop_func op_4868_0_comp_ff;
+extern compop_func op_4870_0_comp_ff;
+extern compop_func op_4878_0_comp_ff;
+extern compop_func op_4879_0_comp_ff;
+extern compop_func op_487a_0_comp_ff;
+extern compop_func op_487b_0_comp_ff;
+extern compop_func op_4880_0_comp_ff;
+extern compop_func op_4890_0_comp_ff;
+extern compop_func op_48a0_0_comp_ff;
+extern compop_func op_48a8_0_comp_ff;
+extern compop_func op_48b0_0_comp_ff;
+extern compop_func op_48b8_0_comp_ff;
+extern compop_func op_48b9_0_comp_ff;
+extern compop_func op_48c0_0_comp_ff;
+extern compop_func op_48d0_0_comp_ff;
+extern compop_func op_48e0_0_comp_ff;
+extern compop_func op_48e8_0_comp_ff;
+extern compop_func op_48f0_0_comp_ff;
+extern compop_func op_48f8_0_comp_ff;
+extern compop_func op_48f9_0_comp_ff;
+extern compop_func op_49c0_0_comp_ff;
+extern compop_func op_4a00_0_comp_ff;
+extern compop_func op_4a10_0_comp_ff;
+extern compop_func op_4a18_0_comp_ff;
+extern compop_func op_4a20_0_comp_ff;
+extern compop_func op_4a28_0_comp_ff;
+extern compop_func op_4a30_0_comp_ff;
+extern compop_func op_4a38_0_comp_ff;
+extern compop_func op_4a39_0_comp_ff;
+extern compop_func op_4a3a_0_comp_ff;
+extern compop_func op_4a3b_0_comp_ff;
+extern compop_func op_4a40_0_comp_ff;
+extern compop_func op_4a48_0_comp_ff;
+extern compop_func op_4a50_0_comp_ff;
+extern compop_func op_4a58_0_comp_ff;
+extern compop_func op_4a60_0_comp_ff;
+extern compop_func op_4a68_0_comp_ff;
+extern compop_func op_4a70_0_comp_ff;
+extern compop_func op_4a78_0_comp_ff;
+extern compop_func op_4a79_0_comp_ff;
+extern compop_func op_4a7a_0_comp_ff;
+extern compop_func op_4a7b_0_comp_ff;
+extern compop_func op_4a80_0_comp_ff;
+extern compop_func op_4a88_0_comp_ff;
+extern compop_func op_4a90_0_comp_ff;
+extern compop_func op_4a98_0_comp_ff;
+extern compop_func op_4aa0_0_comp_ff;
+extern compop_func op_4aa8_0_comp_ff;
+extern compop_func op_4ab0_0_comp_ff;
+extern compop_func op_4ab8_0_comp_ff;
+extern compop_func op_4ab9_0_comp_ff;
+extern compop_func op_4aba_0_comp_ff;
+extern compop_func op_4abb_0_comp_ff;
+extern compop_func op_4c90_0_comp_ff;
+extern compop_func op_4c98_0_comp_ff;
+extern compop_func op_4ca8_0_comp_ff;
+extern compop_func op_4cb0_0_comp_ff;
+extern compop_func op_4cb8_0_comp_ff;
+extern compop_func op_4cb9_0_comp_ff;
+extern compop_func op_4cba_0_comp_ff;
+extern compop_func op_4cbb_0_comp_ff;
+extern compop_func op_4cd0_0_comp_ff;
+extern compop_func op_4cd8_0_comp_ff;
+extern compop_func op_4ce8_0_comp_ff;
+extern compop_func op_4cf0_0_comp_ff;
+extern compop_func op_4cf8_0_comp_ff;
+extern compop_func op_4cf9_0_comp_ff;
+extern compop_func op_4cfa_0_comp_ff;
+extern compop_func op_4cfb_0_comp_ff;
+extern compop_func op_4e50_0_comp_ff;
+extern compop_func op_4e58_0_comp_ff;
+extern compop_func op_4e71_0_comp_ff;
+extern compop_func op_4e74_0_comp_ff;
+extern compop_func op_4e75_0_comp_ff;
+extern compop_func op_4e90_0_comp_ff;
+extern compop_func op_4ea8_0_comp_ff;
+extern compop_func op_4eb0_0_comp_ff;
+extern compop_func op_4eb8_0_comp_ff;
+extern compop_func op_4eb9_0_comp_ff;
+extern compop_func op_4eba_0_comp_ff;
+extern compop_func op_4ebb_0_comp_ff;
+extern compop_func op_4ed0_0_comp_ff;
+extern compop_func op_4ee8_0_comp_ff;
+extern compop_func op_4ef0_0_comp_ff;
+extern compop_func op_4ef8_0_comp_ff;
+extern compop_func op_4ef9_0_comp_ff;
+extern compop_func op_4efa_0_comp_ff;
+extern compop_func op_4efb_0_comp_ff;
+extern compop_func op_5000_0_comp_ff;
+extern compop_func op_5010_0_comp_ff;
+extern compop_func op_5018_0_comp_ff;
+extern compop_func op_5020_0_comp_ff;
+extern compop_func op_5028_0_comp_ff;
+extern compop_func op_5030_0_comp_ff;
+extern compop_func op_5038_0_comp_ff;
+extern compop_func op_5039_0_comp_ff;
+extern compop_func op_5040_0_comp_ff;
+extern compop_func op_5048_0_comp_ff;
+extern compop_func op_5050_0_comp_ff;
+extern compop_func op_5058_0_comp_ff;
+extern compop_func op_5060_0_comp_ff;
+extern compop_func op_5068_0_comp_ff;
+extern compop_func op_5070_0_comp_ff;
+extern compop_func op_5078_0_comp_ff;
+extern compop_func op_5079_0_comp_ff;
+extern compop_func op_5080_0_comp_ff;
+extern compop_func op_5088_0_comp_ff;
+extern compop_func op_5090_0_comp_ff;
+extern compop_func op_5098_0_comp_ff;
+extern compop_func op_50a0_0_comp_ff;
+extern compop_func op_50a8_0_comp_ff;
+extern compop_func op_50b0_0_comp_ff;
+extern compop_func op_50b8_0_comp_ff;
+extern compop_func op_50b9_0_comp_ff;
+extern compop_func op_50c0_0_comp_ff;
+extern compop_func op_50c8_0_comp_ff;
+extern compop_func op_50d0_0_comp_ff;
+extern compop_func op_50d8_0_comp_ff;
+extern compop_func op_50e0_0_comp_ff;
+extern compop_func op_50e8_0_comp_ff;
+extern compop_func op_50f0_0_comp_ff;
+extern compop_func op_50f8_0_comp_ff;
+extern compop_func op_50f9_0_comp_ff;
+extern compop_func op_5100_0_comp_ff;
+extern compop_func op_5110_0_comp_ff;
+extern compop_func op_5118_0_comp_ff;
+extern compop_func op_5120_0_comp_ff;
+extern compop_func op_5128_0_comp_ff;
+extern compop_func op_5130_0_comp_ff;
+extern compop_func op_5138_0_comp_ff;
+extern compop_func op_5139_0_comp_ff;
+extern compop_func op_5140_0_comp_ff;
+extern compop_func op_5148_0_comp_ff;
+extern compop_func op_5150_0_comp_ff;
+extern compop_func op_5158_0_comp_ff;
+extern compop_func op_5160_0_comp_ff;
+extern compop_func op_5168_0_comp_ff;
+extern compop_func op_5170_0_comp_ff;
+extern compop_func op_5178_0_comp_ff;
+extern compop_func op_5179_0_comp_ff;
+extern compop_func op_5180_0_comp_ff;
+extern compop_func op_5188_0_comp_ff;
+extern compop_func op_5190_0_comp_ff;
+extern compop_func op_5198_0_comp_ff;
+extern compop_func op_51a0_0_comp_ff;
+extern compop_func op_51a8_0_comp_ff;
+extern compop_func op_51b0_0_comp_ff;
+extern compop_func op_51b8_0_comp_ff;
+extern compop_func op_51b9_0_comp_ff;
+extern compop_func op_51c0_0_comp_ff;
+extern compop_func op_51c8_0_comp_ff;
+extern compop_func op_51d0_0_comp_ff;
+extern compop_func op_51d8_0_comp_ff;
+extern compop_func op_51e0_0_comp_ff;
+extern compop_func op_51e8_0_comp_ff;
+extern compop_func op_51f0_0_comp_ff;
+extern compop_func op_51f8_0_comp_ff;
+extern compop_func op_51f9_0_comp_ff;
+extern compop_func op_52c0_0_comp_ff;
+extern compop_func op_52c8_0_comp_ff;
+extern compop_func op_52d0_0_comp_ff;
+extern compop_func op_52d8_0_comp_ff;
+extern compop_func op_52e0_0_comp_ff;
+extern compop_func op_52e8_0_comp_ff;
+extern compop_func op_52f0_0_comp_ff;
+extern compop_func op_52f8_0_comp_ff;
+extern compop_func op_52f9_0_comp_ff;
+extern compop_func op_53c0_0_comp_ff;
+extern compop_func op_53c8_0_comp_ff;
+extern compop_func op_53d0_0_comp_ff;
+extern compop_func op_53d8_0_comp_ff;
+extern compop_func op_53e0_0_comp_ff;
+extern compop_func op_53e8_0_comp_ff;
+extern compop_func op_53f0_0_comp_ff;
+extern compop_func op_53f8_0_comp_ff;
+extern compop_func op_53f9_0_comp_ff;
+extern compop_func op_54c0_0_comp_ff;
+extern compop_func op_54c8_0_comp_ff;
+extern compop_func op_54d0_0_comp_ff;
+extern compop_func op_54d8_0_comp_ff;
+extern compop_func op_54e0_0_comp_ff;
+extern compop_func op_54e8_0_comp_ff;
+extern compop_func op_54f0_0_comp_ff;
+extern compop_func op_54f8_0_comp_ff;
+extern compop_func op_54f9_0_comp_ff;
+extern compop_func op_55c0_0_comp_ff;
+extern compop_func op_55c8_0_comp_ff;
+extern compop_func op_55d0_0_comp_ff;
+extern compop_func op_55d8_0_comp_ff;
+extern compop_func op_55e0_0_comp_ff;
+extern compop_func op_55e8_0_comp_ff;
+extern compop_func op_55f0_0_comp_ff;
+extern compop_func op_55f8_0_comp_ff;
+extern compop_func op_55f9_0_comp_ff;
+extern compop_func op_56c0_0_comp_ff;
+extern compop_func op_56c8_0_comp_ff;
+extern compop_func op_56d0_0_comp_ff;
+extern compop_func op_56d8_0_comp_ff;
+extern compop_func op_56e0_0_comp_ff;
+extern compop_func op_56e8_0_comp_ff;
+extern compop_func op_56f0_0_comp_ff;
+extern compop_func op_56f8_0_comp_ff;
+extern compop_func op_56f9_0_comp_ff;
+extern compop_func op_57c0_0_comp_ff;
+extern compop_func op_57c8_0_comp_ff;
+extern compop_func op_57d0_0_comp_ff;
+extern compop_func op_57d8_0_comp_ff;
+extern compop_func op_57e0_0_comp_ff;
+extern compop_func op_57e8_0_comp_ff;
+extern compop_func op_57f0_0_comp_ff;
+extern compop_func op_57f8_0_comp_ff;
+extern compop_func op_57f9_0_comp_ff;
+extern compop_func op_5ac0_0_comp_ff;
+extern compop_func op_5ac8_0_comp_ff;
+extern compop_func op_5ad0_0_comp_ff;
+extern compop_func op_5ad8_0_comp_ff;
+extern compop_func op_5ae0_0_comp_ff;
+extern compop_func op_5ae8_0_comp_ff;
+extern compop_func op_5af0_0_comp_ff;
+extern compop_func op_5af8_0_comp_ff;
+extern compop_func op_5af9_0_comp_ff;
+extern compop_func op_5bc0_0_comp_ff;
+extern compop_func op_5bc8_0_comp_ff;
+extern compop_func op_5bd0_0_comp_ff;
+extern compop_func op_5bd8_0_comp_ff;
+extern compop_func op_5be0_0_comp_ff;
+extern compop_func op_5be8_0_comp_ff;
+extern compop_func op_5bf0_0_comp_ff;
+extern compop_func op_5bf8_0_comp_ff;
+extern compop_func op_5bf9_0_comp_ff;
+extern compop_func op_5cc0_0_comp_ff;
+extern compop_func op_5cc8_0_comp_ff;
+extern compop_func op_5cd0_0_comp_ff;
+extern compop_func op_5cd8_0_comp_ff;
+extern compop_func op_5ce0_0_comp_ff;
+extern compop_func op_5ce8_0_comp_ff;
+extern compop_func op_5cf0_0_comp_ff;
+extern compop_func op_5cf8_0_comp_ff;
+extern compop_func op_5cf9_0_comp_ff;
+extern compop_func op_5dc0_0_comp_ff;
+extern compop_func op_5dc8_0_comp_ff;
+extern compop_func op_5dd0_0_comp_ff;
+extern compop_func op_5dd8_0_comp_ff;
+extern compop_func op_5de0_0_comp_ff;
+extern compop_func op_5de8_0_comp_ff;
+extern compop_func op_5df0_0_comp_ff;
+extern compop_func op_5df8_0_comp_ff;
+extern compop_func op_5df9_0_comp_ff;
+extern compop_func op_5ec0_0_comp_ff;
+extern compop_func op_5ec8_0_comp_ff;
+extern compop_func op_5ed0_0_comp_ff;
+extern compop_func op_5ed8_0_comp_ff;
+extern compop_func op_5ee0_0_comp_ff;
+extern compop_func op_5ee8_0_comp_ff;
+extern compop_func op_5ef0_0_comp_ff;
+extern compop_func op_5ef8_0_comp_ff;
+extern compop_func op_5ef9_0_comp_ff;
+extern compop_func op_5fc0_0_comp_ff;
+extern compop_func op_5fc8_0_comp_ff;
+extern compop_func op_5fd0_0_comp_ff;
+extern compop_func op_5fd8_0_comp_ff;
+extern compop_func op_5fe0_0_comp_ff;
+extern compop_func op_5fe8_0_comp_ff;
+extern compop_func op_5ff0_0_comp_ff;
+extern compop_func op_5ff8_0_comp_ff;
+extern compop_func op_5ff9_0_comp_ff;
+extern compop_func op_6000_0_comp_ff;
+extern compop_func op_6001_0_comp_ff;
+extern compop_func op_60ff_0_comp_ff;
+extern compop_func op_6100_0_comp_ff;
+extern compop_func op_6101_0_comp_ff;
+extern compop_func op_6200_0_comp_ff;
+extern compop_func op_6201_0_comp_ff;
+extern compop_func op_62ff_0_comp_ff;
+extern compop_func op_6300_0_comp_ff;
+extern compop_func op_6301_0_comp_ff;
+extern compop_func op_63ff_0_comp_ff;
+extern compop_func op_6400_0_comp_ff;
+extern compop_func op_6401_0_comp_ff;
+extern compop_func op_64ff_0_comp_ff;
+extern compop_func op_6500_0_comp_ff;
+extern compop_func op_6501_0_comp_ff;
+extern compop_func op_65ff_0_comp_ff;
+extern compop_func op_6600_0_comp_ff;
+extern compop_func op_6601_0_comp_ff;
+extern compop_func op_66ff_0_comp_ff;
+extern compop_func op_6700_0_comp_ff;
+extern compop_func op_6701_0_comp_ff;
+extern compop_func op_67ff_0_comp_ff;
+extern compop_func op_6a00_0_comp_ff;
+extern compop_func op_6a01_0_comp_ff;
+extern compop_func op_6aff_0_comp_ff;
+extern compop_func op_6b00_0_comp_ff;
+extern compop_func op_6b01_0_comp_ff;
+extern compop_func op_6bff_0_comp_ff;
+extern compop_func op_6c00_0_comp_ff;
+extern compop_func op_6c01_0_comp_ff;
+extern compop_func op_6cff_0_comp_ff;
+extern compop_func op_6d00_0_comp_ff;
+extern compop_func op_6d01_0_comp_ff;
+extern compop_func op_6dff_0_comp_ff;
+extern compop_func op_6e00_0_comp_ff;
+extern compop_func op_6e01_0_comp_ff;
+extern compop_func op_6eff_0_comp_ff;
+extern compop_func op_6f00_0_comp_ff;
+extern compop_func op_6f01_0_comp_ff;
+extern compop_func op_6fff_0_comp_ff;
+extern compop_func op_7000_0_comp_ff;
+extern compop_func op_8000_0_comp_ff;
+extern compop_func op_8010_0_comp_ff;
+extern compop_func op_8018_0_comp_ff;
+extern compop_func op_8020_0_comp_ff;
+extern compop_func op_8028_0_comp_ff;
+extern compop_func op_8030_0_comp_ff;
+extern compop_func op_8038_0_comp_ff;
+extern compop_func op_8039_0_comp_ff;
+extern compop_func op_803a_0_comp_ff;
+extern compop_func op_803b_0_comp_ff;
+extern compop_func op_803c_0_comp_ff;
+extern compop_func op_8040_0_comp_ff;
+extern compop_func op_8050_0_comp_ff;
+extern compop_func op_8058_0_comp_ff;
+extern compop_func op_8060_0_comp_ff;
+extern compop_func op_8068_0_comp_ff;
+extern compop_func op_8070_0_comp_ff;
+extern compop_func op_8078_0_comp_ff;
+extern compop_func op_8079_0_comp_ff;
+extern compop_func op_807a_0_comp_ff;
+extern compop_func op_807b_0_comp_ff;
+extern compop_func op_807c_0_comp_ff;
+extern compop_func op_8080_0_comp_ff;
+extern compop_func op_8090_0_comp_ff;
+extern compop_func op_8098_0_comp_ff;
+extern compop_func op_80a0_0_comp_ff;
+extern compop_func op_80a8_0_comp_ff;
+extern compop_func op_80b0_0_comp_ff;
+extern compop_func op_80b8_0_comp_ff;
+extern compop_func op_80b9_0_comp_ff;
+extern compop_func op_80ba_0_comp_ff;
+extern compop_func op_80bb_0_comp_ff;
+extern compop_func op_80bc_0_comp_ff;
+extern compop_func op_8110_0_comp_ff;
+extern compop_func op_8118_0_comp_ff;
+extern compop_func op_8120_0_comp_ff;
+extern compop_func op_8128_0_comp_ff;
+extern compop_func op_8130_0_comp_ff;
+extern compop_func op_8138_0_comp_ff;
+extern compop_func op_8139_0_comp_ff;
+extern compop_func op_8150_0_comp_ff;
+extern compop_func op_8158_0_comp_ff;
+extern compop_func op_8160_0_comp_ff;
+extern compop_func op_8168_0_comp_ff;
+extern compop_func op_8170_0_comp_ff;
+extern compop_func op_8178_0_comp_ff;
+extern compop_func op_8179_0_comp_ff;
+extern compop_func op_8190_0_comp_ff;
+extern compop_func op_8198_0_comp_ff;
+extern compop_func op_81a0_0_comp_ff;
+extern compop_func op_81a8_0_comp_ff;
+extern compop_func op_81b0_0_comp_ff;
+extern compop_func op_81b8_0_comp_ff;
+extern compop_func op_81b9_0_comp_ff;
+extern compop_func op_9000_0_comp_ff;
+extern compop_func op_9010_0_comp_ff;
+extern compop_func op_9018_0_comp_ff;
+extern compop_func op_9020_0_comp_ff;
+extern compop_func op_9028_0_comp_ff;
+extern compop_func op_9030_0_comp_ff;
+extern compop_func op_9038_0_comp_ff;
+extern compop_func op_9039_0_comp_ff;
+extern compop_func op_903a_0_comp_ff;
+extern compop_func op_903b_0_comp_ff;
+extern compop_func op_903c_0_comp_ff;
+extern compop_func op_9040_0_comp_ff;
+extern compop_func op_9048_0_comp_ff;
+extern compop_func op_9050_0_comp_ff;
+extern compop_func op_9058_0_comp_ff;
+extern compop_func op_9060_0_comp_ff;
+extern compop_func op_9068_0_comp_ff;
+extern compop_func op_9070_0_comp_ff;
+extern compop_func op_9078_0_comp_ff;
+extern compop_func op_9079_0_comp_ff;
+extern compop_func op_907a_0_comp_ff;
+extern compop_func op_907b_0_comp_ff;
+extern compop_func op_907c_0_comp_ff;
+extern compop_func op_9080_0_comp_ff;
+extern compop_func op_9088_0_comp_ff;
+extern compop_func op_9090_0_comp_ff;
+extern compop_func op_9098_0_comp_ff;
+extern compop_func op_90a0_0_comp_ff;
+extern compop_func op_90a8_0_comp_ff;
+extern compop_func op_90b0_0_comp_ff;
+extern compop_func op_90b8_0_comp_ff;
+extern compop_func op_90b9_0_comp_ff;
+extern compop_func op_90ba_0_comp_ff;
+extern compop_func op_90bb_0_comp_ff;
+extern compop_func op_90bc_0_comp_ff;
+extern compop_func op_90c0_0_comp_ff;
+extern compop_func op_90c8_0_comp_ff;
+extern compop_func op_90d0_0_comp_ff;
+extern compop_func op_90d8_0_comp_ff;
+extern compop_func op_90e0_0_comp_ff;
+extern compop_func op_90e8_0_comp_ff;
+extern compop_func op_90f0_0_comp_ff;
+extern compop_func op_90f8_0_comp_ff;
+extern compop_func op_90f9_0_comp_ff;
+extern compop_func op_90fa_0_comp_ff;
+extern compop_func op_90fb_0_comp_ff;
+extern compop_func op_90fc_0_comp_ff;
+extern compop_func op_9100_0_comp_ff;
+extern compop_func op_9108_0_comp_ff;
+extern compop_func op_9110_0_comp_ff;
+extern compop_func op_9118_0_comp_ff;
+extern compop_func op_9120_0_comp_ff;
+extern compop_func op_9128_0_comp_ff;
+extern compop_func op_9130_0_comp_ff;
+extern compop_func op_9138_0_comp_ff;
+extern compop_func op_9139_0_comp_ff;
+extern compop_func op_9140_0_comp_ff;
+extern compop_func op_9148_0_comp_ff;
+extern compop_func op_9150_0_comp_ff;
+extern compop_func op_9158_0_comp_ff;
+extern compop_func op_9160_0_comp_ff;
+extern compop_func op_9168_0_comp_ff;
+extern compop_func op_9170_0_comp_ff;
+extern compop_func op_9178_0_comp_ff;
+extern compop_func op_9179_0_comp_ff;
+extern compop_func op_9180_0_comp_ff;
+extern compop_func op_9188_0_comp_ff;
+extern compop_func op_9190_0_comp_ff;
+extern compop_func op_9198_0_comp_ff;
+extern compop_func op_91a0_0_comp_ff;
+extern compop_func op_91a8_0_comp_ff;
+extern compop_func op_91b0_0_comp_ff;
+extern compop_func op_91b8_0_comp_ff;
+extern compop_func op_91b9_0_comp_ff;
+extern compop_func op_91c0_0_comp_ff;
+extern compop_func op_91c8_0_comp_ff;
+extern compop_func op_91d0_0_comp_ff;
+extern compop_func op_91d8_0_comp_ff;
+extern compop_func op_91e0_0_comp_ff;
+extern compop_func op_91e8_0_comp_ff;
+extern compop_func op_91f0_0_comp_ff;
+extern compop_func op_91f8_0_comp_ff;
+extern compop_func op_91f9_0_comp_ff;
+extern compop_func op_91fa_0_comp_ff;
+extern compop_func op_91fb_0_comp_ff;
+extern compop_func op_91fc_0_comp_ff;
+extern compop_func op_b000_0_comp_ff;
+extern compop_func op_b010_0_comp_ff;
+extern compop_func op_b018_0_comp_ff;
+extern compop_func op_b020_0_comp_ff;
+extern compop_func op_b028_0_comp_ff;
+extern compop_func op_b030_0_comp_ff;
+extern compop_func op_b038_0_comp_ff;
+extern compop_func op_b039_0_comp_ff;
+extern compop_func op_b03a_0_comp_ff;
+extern compop_func op_b03b_0_comp_ff;
+extern compop_func op_b03c_0_comp_ff;
+extern compop_func op_b040_0_comp_ff;
+extern compop_func op_b048_0_comp_ff;
+extern compop_func op_b050_0_comp_ff;
+extern compop_func op_b058_0_comp_ff;
+extern compop_func op_b060_0_comp_ff;
+extern compop_func op_b068_0_comp_ff;
+extern compop_func op_b070_0_comp_ff;
+extern compop_func op_b078_0_comp_ff;
+extern compop_func op_b079_0_comp_ff;
+extern compop_func op_b07a_0_comp_ff;
+extern compop_func op_b07b_0_comp_ff;
+extern compop_func op_b07c_0_comp_ff;
+extern compop_func op_b080_0_comp_ff;
+extern compop_func op_b088_0_comp_ff;
+extern compop_func op_b090_0_comp_ff;
+extern compop_func op_b098_0_comp_ff;
+extern compop_func op_b0a0_0_comp_ff;
+extern compop_func op_b0a8_0_comp_ff;
+extern compop_func op_b0b0_0_comp_ff;
+extern compop_func op_b0b8_0_comp_ff;
+extern compop_func op_b0b9_0_comp_ff;
+extern compop_func op_b0ba_0_comp_ff;
+extern compop_func op_b0bb_0_comp_ff;
+extern compop_func op_b0bc_0_comp_ff;
+extern compop_func op_b0c0_0_comp_ff;
+extern compop_func op_b0c8_0_comp_ff;
+extern compop_func op_b0d0_0_comp_ff;
+extern compop_func op_b0d8_0_comp_ff;
+extern compop_func op_b0e0_0_comp_ff;
+extern compop_func op_b0e8_0_comp_ff;
+extern compop_func op_b0f0_0_comp_ff;
+extern compop_func op_b0f8_0_comp_ff;
+extern compop_func op_b0f9_0_comp_ff;
+extern compop_func op_b0fa_0_comp_ff;
+extern compop_func op_b0fb_0_comp_ff;
+extern compop_func op_b0fc_0_comp_ff;
+extern compop_func op_b100_0_comp_ff;
+extern compop_func op_b108_0_comp_ff;
+extern compop_func op_b110_0_comp_ff;
+extern compop_func op_b118_0_comp_ff;
+extern compop_func op_b120_0_comp_ff;
+extern compop_func op_b128_0_comp_ff;
+extern compop_func op_b130_0_comp_ff;
+extern compop_func op_b138_0_comp_ff;
+extern compop_func op_b139_0_comp_ff;
+extern compop_func op_b140_0_comp_ff;
+extern compop_func op_b148_0_comp_ff;
+extern compop_func op_b150_0_comp_ff;
+extern compop_func op_b158_0_comp_ff;
+extern compop_func op_b160_0_comp_ff;
+extern compop_func op_b168_0_comp_ff;
+extern compop_func op_b170_0_comp_ff;
+extern compop_func op_b178_0_comp_ff;
+extern compop_func op_b179_0_comp_ff;
+extern compop_func op_b180_0_comp_ff;
+extern compop_func op_b188_0_comp_ff;
+extern compop_func op_b190_0_comp_ff;
+extern compop_func op_b198_0_comp_ff;
+extern compop_func op_b1a0_0_comp_ff;
+extern compop_func op_b1a8_0_comp_ff;
+extern compop_func op_b1b0_0_comp_ff;
+extern compop_func op_b1b8_0_comp_ff;
+extern compop_func op_b1b9_0_comp_ff;
+extern compop_func op_b1c0_0_comp_ff;
+extern compop_func op_b1c8_0_comp_ff;
+extern compop_func op_b1d0_0_comp_ff;
+extern compop_func op_b1d8_0_comp_ff;
+extern compop_func op_b1e0_0_comp_ff;
+extern compop_func op_b1e8_0_comp_ff;
+extern compop_func op_b1f0_0_comp_ff;
+extern compop_func op_b1f8_0_comp_ff;
+extern compop_func op_b1f9_0_comp_ff;
+extern compop_func op_b1fa_0_comp_ff;
+extern compop_func op_b1fb_0_comp_ff;
+extern compop_func op_b1fc_0_comp_ff;
+extern compop_func op_c000_0_comp_ff;
+extern compop_func op_c010_0_comp_ff;
+extern compop_func op_c018_0_comp_ff;
+extern compop_func op_c020_0_comp_ff;
+extern compop_func op_c028_0_comp_ff;
+extern compop_func op_c030_0_comp_ff;
+extern compop_func op_c038_0_comp_ff;
+extern compop_func op_c039_0_comp_ff;
+extern compop_func op_c03a_0_comp_ff;
+extern compop_func op_c03b_0_comp_ff;
+extern compop_func op_c03c_0_comp_ff;
+extern compop_func op_c040_0_comp_ff;
+extern compop_func op_c050_0_comp_ff;
+extern compop_func op_c058_0_comp_ff;
+extern compop_func op_c060_0_comp_ff;
+extern compop_func op_c068_0_comp_ff;
+extern compop_func op_c070_0_comp_ff;
+extern compop_func op_c078_0_comp_ff;
+extern compop_func op_c079_0_comp_ff;
+extern compop_func op_c07a_0_comp_ff;
+extern compop_func op_c07b_0_comp_ff;
+extern compop_func op_c07c_0_comp_ff;
+extern compop_func op_c080_0_comp_ff;
+extern compop_func op_c090_0_comp_ff;
+extern compop_func op_c098_0_comp_ff;
+extern compop_func op_c0a0_0_comp_ff;
+extern compop_func op_c0a8_0_comp_ff;
+extern compop_func op_c0b0_0_comp_ff;
+extern compop_func op_c0b8_0_comp_ff;
+extern compop_func op_c0b9_0_comp_ff;
+extern compop_func op_c0ba_0_comp_ff;
+extern compop_func op_c0bb_0_comp_ff;
+extern compop_func op_c0bc_0_comp_ff;
+extern compop_func op_c0c0_0_comp_ff;
+extern compop_func op_c0d0_0_comp_ff;
+extern compop_func op_c0d8_0_comp_ff;
+extern compop_func op_c0e0_0_comp_ff;
+extern compop_func op_c0e8_0_comp_ff;
+extern compop_func op_c0f0_0_comp_ff;
+extern compop_func op_c0f8_0_comp_ff;
+extern compop_func op_c0f9_0_comp_ff;
+extern compop_func op_c0fa_0_comp_ff;
+extern compop_func op_c0fb_0_comp_ff;
+extern compop_func op_c0fc_0_comp_ff;
+extern compop_func op_c110_0_comp_ff;
+extern compop_func op_c118_0_comp_ff;
+extern compop_func op_c120_0_comp_ff;
+extern compop_func op_c128_0_comp_ff;
+extern compop_func op_c130_0_comp_ff;
+extern compop_func op_c138_0_comp_ff;
+extern compop_func op_c139_0_comp_ff;
+extern compop_func op_c140_0_comp_ff;
+extern compop_func op_c148_0_comp_ff;
+extern compop_func op_c150_0_comp_ff;
+extern compop_func op_c158_0_comp_ff;
+extern compop_func op_c160_0_comp_ff;
+extern compop_func op_c168_0_comp_ff;
+extern compop_func op_c170_0_comp_ff;
+extern compop_func op_c178_0_comp_ff;
+extern compop_func op_c179_0_comp_ff;
+extern compop_func op_c188_0_comp_ff;
+extern compop_func op_c190_0_comp_ff;
+extern compop_func op_c198_0_comp_ff;
+extern compop_func op_c1a0_0_comp_ff;
+extern compop_func op_c1a8_0_comp_ff;
+extern compop_func op_c1b0_0_comp_ff;
+extern compop_func op_c1b8_0_comp_ff;
+extern compop_func op_c1b9_0_comp_ff;
+extern compop_func op_c1c0_0_comp_ff;
+extern compop_func op_c1d0_0_comp_ff;
+extern compop_func op_c1d8_0_comp_ff;
+extern compop_func op_c1e0_0_comp_ff;
+extern compop_func op_c1e8_0_comp_ff;
+extern compop_func op_c1f0_0_comp_ff;
+extern compop_func op_c1f8_0_comp_ff;
+extern compop_func op_c1f9_0_comp_ff;
+extern compop_func op_c1fa_0_comp_ff;
+extern compop_func op_c1fb_0_comp_ff;
+extern compop_func op_c1fc_0_comp_ff;
+extern compop_func op_d000_0_comp_ff;
+extern compop_func op_d010_0_comp_ff;
+extern compop_func op_d018_0_comp_ff;
+extern compop_func op_d020_0_comp_ff;
+extern compop_func op_d028_0_comp_ff;
+extern compop_func op_d030_0_comp_ff;
+extern compop_func op_d038_0_comp_ff;
+extern compop_func op_d039_0_comp_ff;
+extern compop_func op_d03a_0_comp_ff;
+extern compop_func op_d03b_0_comp_ff;
+extern compop_func op_d03c_0_comp_ff;
+extern compop_func op_d040_0_comp_ff;
+extern compop_func op_d048_0_comp_ff;
+extern compop_func op_d050_0_comp_ff;
+extern compop_func op_d058_0_comp_ff;
+extern compop_func op_d060_0_comp_ff;
+extern compop_func op_d068_0_comp_ff;
+extern compop_func op_d070_0_comp_ff;
+extern compop_func op_d078_0_comp_ff;
+extern compop_func op_d079_0_comp_ff;
+extern compop_func op_d07a_0_comp_ff;
+extern compop_func op_d07b_0_comp_ff;
+extern compop_func op_d07c_0_comp_ff;
+extern compop_func op_d080_0_comp_ff;
+extern compop_func op_d088_0_comp_ff;
+extern compop_func op_d090_0_comp_ff;
+extern compop_func op_d098_0_comp_ff;
+extern compop_func op_d0a0_0_comp_ff;
+extern compop_func op_d0a8_0_comp_ff;
+extern compop_func op_d0b0_0_comp_ff;
+extern compop_func op_d0b8_0_comp_ff;
+extern compop_func op_d0b9_0_comp_ff;
+extern compop_func op_d0ba_0_comp_ff;
+extern compop_func op_d0bb_0_comp_ff;
+extern compop_func op_d0bc_0_comp_ff;
+extern compop_func op_d0c0_0_comp_ff;
+extern compop_func op_d0c8_0_comp_ff;
+extern compop_func op_d0d0_0_comp_ff;
+extern compop_func op_d0d8_0_comp_ff;
+extern compop_func op_d0e0_0_comp_ff;
+extern compop_func op_d0e8_0_comp_ff;
+extern compop_func op_d0f0_0_comp_ff;
+extern compop_func op_d0f8_0_comp_ff;
+extern compop_func op_d0f9_0_comp_ff;
+extern compop_func op_d0fa_0_comp_ff;
+extern compop_func op_d0fb_0_comp_ff;
+extern compop_func op_d0fc_0_comp_ff;
+extern compop_func op_d100_0_comp_ff;
+extern compop_func op_d108_0_comp_ff;
+extern compop_func op_d110_0_comp_ff;
+extern compop_func op_d118_0_comp_ff;
+extern compop_func op_d120_0_comp_ff;
+extern compop_func op_d128_0_comp_ff;
+extern compop_func op_d130_0_comp_ff;
+extern compop_func op_d138_0_comp_ff;
+extern compop_func op_d139_0_comp_ff;
+extern compop_func op_d140_0_comp_ff;
+extern compop_func op_d148_0_comp_ff;
+extern compop_func op_d150_0_comp_ff;
+extern compop_func op_d158_0_comp_ff;
+extern compop_func op_d160_0_comp_ff;
+extern compop_func op_d168_0_comp_ff;
+extern compop_func op_d170_0_comp_ff;
+extern compop_func op_d178_0_comp_ff;
+extern compop_func op_d179_0_comp_ff;
+extern compop_func op_d180_0_comp_ff;
+extern compop_func op_d188_0_comp_ff;
+extern compop_func op_d190_0_comp_ff;
+extern compop_func op_d198_0_comp_ff;
+extern compop_func op_d1a0_0_comp_ff;
+extern compop_func op_d1a8_0_comp_ff;
+extern compop_func op_d1b0_0_comp_ff;
+extern compop_func op_d1b8_0_comp_ff;
+extern compop_func op_d1b9_0_comp_ff;
+extern compop_func op_d1c0_0_comp_ff;
+extern compop_func op_d1c8_0_comp_ff;
+extern compop_func op_d1d0_0_comp_ff;
+extern compop_func op_d1d8_0_comp_ff;
+extern compop_func op_d1e0_0_comp_ff;
+extern compop_func op_d1e8_0_comp_ff;
+extern compop_func op_d1f0_0_comp_ff;
+extern compop_func op_d1f8_0_comp_ff;
+extern compop_func op_d1f9_0_comp_ff;
+extern compop_func op_d1fa_0_comp_ff;
+extern compop_func op_d1fb_0_comp_ff;
+extern compop_func op_d1fc_0_comp_ff;
+extern compop_func op_e000_0_comp_ff;
+extern compop_func op_e008_0_comp_ff;
+extern compop_func op_e018_0_comp_ff;
+extern compop_func op_e020_0_comp_ff;
+extern compop_func op_e028_0_comp_ff;
+extern compop_func op_e038_0_comp_ff;
+extern compop_func op_e040_0_comp_ff;
+extern compop_func op_e048_0_comp_ff;
+extern compop_func op_e058_0_comp_ff;
+extern compop_func op_e060_0_comp_ff;
+extern compop_func op_e068_0_comp_ff;
+extern compop_func op_e078_0_comp_ff;
+extern compop_func op_e080_0_comp_ff;
+extern compop_func op_e088_0_comp_ff;
+extern compop_func op_e098_0_comp_ff;
+extern compop_func op_e0a0_0_comp_ff;
+extern compop_func op_e0a8_0_comp_ff;
+extern compop_func op_e0b8_0_comp_ff;
+extern compop_func op_e100_0_comp_ff;
+extern compop_func op_e108_0_comp_ff;
+extern compop_func op_e118_0_comp_ff;
+extern compop_func op_e120_0_comp_ff;
+extern compop_func op_e128_0_comp_ff;
+extern compop_func op_e138_0_comp_ff;
+extern compop_func op_e140_0_comp_ff;
+extern compop_func op_e148_0_comp_ff;
+extern compop_func op_e158_0_comp_ff;
+extern compop_func op_e160_0_comp_ff;
+extern compop_func op_e168_0_comp_ff;
+extern compop_func op_e178_0_comp_ff;
+extern compop_func op_e180_0_comp_ff;
+extern compop_func op_e188_0_comp_ff;
+extern compop_func op_e198_0_comp_ff;
+extern compop_func op_e1a0_0_comp_ff;
+extern compop_func op_e1a8_0_comp_ff;
+extern compop_func op_e1b8_0_comp_ff;
+extern compop_func op_f200_0_comp_ff;
+extern compop_func op_f208_0_comp_ff;
+extern compop_func op_f210_0_comp_ff;
+extern compop_func op_f218_0_comp_ff;
+extern compop_func op_f220_0_comp_ff;
+extern compop_func op_f228_0_comp_ff;
+extern compop_func op_f230_0_comp_ff;
+extern compop_func op_f238_0_comp_ff;
+extern compop_func op_f239_0_comp_ff;
+extern compop_func op_f23a_0_comp_ff;
+extern compop_func op_f23b_0_comp_ff;
+extern compop_func op_f23c_0_comp_ff;
+extern compop_func op_f240_0_comp_ff;
+extern compop_func op_f250_0_comp_ff;
+extern compop_func op_f258_0_comp_ff;
+extern compop_func op_f260_0_comp_ff;
+extern compop_func op_f268_0_comp_ff;
+extern compop_func op_f270_0_comp_ff;
+extern compop_func op_f278_0_comp_ff;
+extern compop_func op_f279_0_comp_ff;
+extern compop_func op_f280_0_comp_ff;
+extern compop_func op_f2c0_0_comp_ff;
+extern compop_func op_f600_0_comp_ff;
+extern compop_func op_f608_0_comp_ff;
+extern compop_func op_f610_0_comp_ff;
+extern compop_func op_f618_0_comp_ff;
+extern compop_func op_f620_0_comp_ff;
+extern compop_func op_0_0_comp_nf;
+extern compop_func op_10_0_comp_nf;
+extern compop_func op_18_0_comp_nf;
+extern compop_func op_20_0_comp_nf;
+extern compop_func op_28_0_comp_nf;
+extern compop_func op_30_0_comp_nf;
+extern compop_func op_38_0_comp_nf;
+extern compop_func op_39_0_comp_nf;
+extern compop_func op_40_0_comp_nf;
+extern compop_func op_50_0_comp_nf;
+extern compop_func op_58_0_comp_nf;
+extern compop_func op_60_0_comp_nf;
+extern compop_func op_68_0_comp_nf;
+extern compop_func op_70_0_comp_nf;
+extern compop_func op_78_0_comp_nf;
+extern compop_func op_79_0_comp_nf;
+extern compop_func op_80_0_comp_nf;
+extern compop_func op_90_0_comp_nf;
+extern compop_func op_98_0_comp_nf;
+extern compop_func op_a0_0_comp_nf;
+extern compop_func op_a8_0_comp_nf;
+extern compop_func op_b0_0_comp_nf;
+extern compop_func op_b8_0_comp_nf;
+extern compop_func op_b9_0_comp_nf;
+extern compop_func op_100_0_comp_nf;
+extern compop_func op_110_0_comp_nf;
+extern compop_func op_118_0_comp_nf;
+extern compop_func op_120_0_comp_nf;
+extern compop_func op_128_0_comp_nf;
+extern compop_func op_130_0_comp_nf;
+extern compop_func op_138_0_comp_nf;
+extern compop_func op_139_0_comp_nf;
+extern compop_func op_13a_0_comp_nf;
+extern compop_func op_13b_0_comp_nf;
+extern compop_func op_13c_0_comp_nf;
+extern compop_func op_140_0_comp_nf;
+extern compop_func op_150_0_comp_nf;
+extern compop_func op_158_0_comp_nf;
+extern compop_func op_160_0_comp_nf;
+extern compop_func op_168_0_comp_nf;
+extern compop_func op_170_0_comp_nf;
+extern compop_func op_178_0_comp_nf;
+extern compop_func op_179_0_comp_nf;
+extern compop_func op_17a_0_comp_nf;
+extern compop_func op_17b_0_comp_nf;
+extern compop_func op_180_0_comp_nf;
+extern compop_func op_190_0_comp_nf;
+extern compop_func op_198_0_comp_nf;
+extern compop_func op_1a0_0_comp_nf;
+extern compop_func op_1a8_0_comp_nf;
+extern compop_func op_1b0_0_comp_nf;
+extern compop_func op_1b8_0_comp_nf;
+extern compop_func op_1b9_0_comp_nf;
+extern compop_func op_1ba_0_comp_nf;
+extern compop_func op_1bb_0_comp_nf;
+extern compop_func op_1c0_0_comp_nf;
+extern compop_func op_1d0_0_comp_nf;
+extern compop_func op_1d8_0_comp_nf;
+extern compop_func op_1e0_0_comp_nf;
+extern compop_func op_1e8_0_comp_nf;
+extern compop_func op_1f0_0_comp_nf;
+extern compop_func op_1f8_0_comp_nf;
+extern compop_func op_1f9_0_comp_nf;
+extern compop_func op_1fa_0_comp_nf;
+extern compop_func op_1fb_0_comp_nf;
+extern compop_func op_200_0_comp_nf;
+extern compop_func op_210_0_comp_nf;
+extern compop_func op_218_0_comp_nf;
+extern compop_func op_220_0_comp_nf;
+extern compop_func op_228_0_comp_nf;
+extern compop_func op_230_0_comp_nf;
+extern compop_func op_238_0_comp_nf;
+extern compop_func op_239_0_comp_nf;
+extern compop_func op_240_0_comp_nf;
+extern compop_func op_250_0_comp_nf;
+extern compop_func op_258_0_comp_nf;
+extern compop_func op_260_0_comp_nf;
+extern compop_func op_268_0_comp_nf;
+extern compop_func op_270_0_comp_nf;
+extern compop_func op_278_0_comp_nf;
+extern compop_func op_279_0_comp_nf;
+extern compop_func op_280_0_comp_nf;
+extern compop_func op_290_0_comp_nf;
+extern compop_func op_298_0_comp_nf;
+extern compop_func op_2a0_0_comp_nf;
+extern compop_func op_2a8_0_comp_nf;
+extern compop_func op_2b0_0_comp_nf;
+extern compop_func op_2b8_0_comp_nf;
+extern compop_func op_2b9_0_comp_nf;
+extern compop_func op_400_0_comp_nf;
+extern compop_func op_410_0_comp_nf;
+extern compop_func op_418_0_comp_nf;
+extern compop_func op_420_0_comp_nf;
+extern compop_func op_428_0_comp_nf;
+extern compop_func op_430_0_comp_nf;
+extern compop_func op_438_0_comp_nf;
+extern compop_func op_439_0_comp_nf;
+extern compop_func op_440_0_comp_nf;
+extern compop_func op_450_0_comp_nf;
+extern compop_func op_458_0_comp_nf;
+extern compop_func op_460_0_comp_nf;
+extern compop_func op_468_0_comp_nf;
+extern compop_func op_470_0_comp_nf;
+extern compop_func op_478_0_comp_nf;
+extern compop_func op_479_0_comp_nf;
+extern compop_func op_480_0_comp_nf;
+extern compop_func op_490_0_comp_nf;
+extern compop_func op_498_0_comp_nf;
+extern compop_func op_4a0_0_comp_nf;
+extern compop_func op_4a8_0_comp_nf;
+extern compop_func op_4b0_0_comp_nf;
+extern compop_func op_4b8_0_comp_nf;
+extern compop_func op_4b9_0_comp_nf;
+extern compop_func op_600_0_comp_nf;
+extern compop_func op_610_0_comp_nf;
+extern compop_func op_618_0_comp_nf;
+extern compop_func op_620_0_comp_nf;
+extern compop_func op_628_0_comp_nf;
+extern compop_func op_630_0_comp_nf;
+extern compop_func op_638_0_comp_nf;
+extern compop_func op_639_0_comp_nf;
+extern compop_func op_640_0_comp_nf;
+extern compop_func op_650_0_comp_nf;
+extern compop_func op_658_0_comp_nf;
+extern compop_func op_660_0_comp_nf;
+extern compop_func op_668_0_comp_nf;
+extern compop_func op_670_0_comp_nf;
+extern compop_func op_678_0_comp_nf;
+extern compop_func op_679_0_comp_nf;
+extern compop_func op_680_0_comp_nf;
+extern compop_func op_690_0_comp_nf;
+extern compop_func op_698_0_comp_nf;
+extern compop_func op_6a0_0_comp_nf;
+extern compop_func op_6a8_0_comp_nf;
+extern compop_func op_6b0_0_comp_nf;
+extern compop_func op_6b8_0_comp_nf;
+extern compop_func op_6b9_0_comp_nf;
+extern compop_func op_800_0_comp_nf;
+extern compop_func op_810_0_comp_nf;
+extern compop_func op_818_0_comp_nf;
+extern compop_func op_820_0_comp_nf;
+extern compop_func op_828_0_comp_nf;
+extern compop_func op_830_0_comp_nf;
+extern compop_func op_838_0_comp_nf;
+extern compop_func op_839_0_comp_nf;
+extern compop_func op_83a_0_comp_nf;
+extern compop_func op_83b_0_comp_nf;
+extern compop_func op_840_0_comp_nf;
+extern compop_func op_850_0_comp_nf;
+extern compop_func op_858_0_comp_nf;
+extern compop_func op_860_0_comp_nf;
+extern compop_func op_868_0_comp_nf;
+extern compop_func op_870_0_comp_nf;
+extern compop_func op_878_0_comp_nf;
+extern compop_func op_879_0_comp_nf;
+extern compop_func op_87a_0_comp_nf;
+extern compop_func op_87b_0_comp_nf;
+extern compop_func op_880_0_comp_nf;
+extern compop_func op_890_0_comp_nf;
+extern compop_func op_898_0_comp_nf;
+extern compop_func op_8a0_0_comp_nf;
+extern compop_func op_8a8_0_comp_nf;
+extern compop_func op_8b0_0_comp_nf;
+extern compop_func op_8b8_0_comp_nf;
+extern compop_func op_8b9_0_comp_nf;
+extern compop_func op_8ba_0_comp_nf;
+extern compop_func op_8bb_0_comp_nf;
+extern compop_func op_8c0_0_comp_nf;
+extern compop_func op_8d0_0_comp_nf;
+extern compop_func op_8d8_0_comp_nf;
+extern compop_func op_8e0_0_comp_nf;
+extern compop_func op_8e8_0_comp_nf;
+extern compop_func op_8f0_0_comp_nf;
+extern compop_func op_8f8_0_comp_nf;
+extern compop_func op_8f9_0_comp_nf;
+extern compop_func op_8fa_0_comp_nf;
+extern compop_func op_8fb_0_comp_nf;
+extern compop_func op_a00_0_comp_nf;
+extern compop_func op_a10_0_comp_nf;
+extern compop_func op_a18_0_comp_nf;
+extern compop_func op_a20_0_comp_nf;
+extern compop_func op_a28_0_comp_nf;
+extern compop_func op_a30_0_comp_nf;
+extern compop_func op_a38_0_comp_nf;
+extern compop_func op_a39_0_comp_nf;
+extern compop_func op_a40_0_comp_nf;
+extern compop_func op_a50_0_comp_nf;
+extern compop_func op_a58_0_comp_nf;
+extern compop_func op_a60_0_comp_nf;
+extern compop_func op_a68_0_comp_nf;
+extern compop_func op_a70_0_comp_nf;
+extern compop_func op_a78_0_comp_nf;
+extern compop_func op_a79_0_comp_nf;
+extern compop_func op_a80_0_comp_nf;
+extern compop_func op_a90_0_comp_nf;
+extern compop_func op_a98_0_comp_nf;
+extern compop_func op_aa0_0_comp_nf;
+extern compop_func op_aa8_0_comp_nf;
+extern compop_func op_ab0_0_comp_nf;
+extern compop_func op_ab8_0_comp_nf;
+extern compop_func op_ab9_0_comp_nf;
+extern compop_func op_c00_0_comp_nf;
+extern compop_func op_c10_0_comp_nf;
+extern compop_func op_c18_0_comp_nf;
+extern compop_func op_c20_0_comp_nf;
+extern compop_func op_c28_0_comp_nf;
+extern compop_func op_c30_0_comp_nf;
+extern compop_func op_c38_0_comp_nf;
+extern compop_func op_c39_0_comp_nf;
+extern compop_func op_c3a_0_comp_nf;
+extern compop_func op_c3b_0_comp_nf;
+extern compop_func op_c40_0_comp_nf;
+extern compop_func op_c50_0_comp_nf;
+extern compop_func op_c58_0_comp_nf;
+extern compop_func op_c60_0_comp_nf;
+extern compop_func op_c68_0_comp_nf;
+extern compop_func op_c70_0_comp_nf;
+extern compop_func op_c78_0_comp_nf;
+extern compop_func op_c79_0_comp_nf;
+extern compop_func op_c7a_0_comp_nf;
+extern compop_func op_c7b_0_comp_nf;
+extern compop_func op_c80_0_comp_nf;
+extern compop_func op_c90_0_comp_nf;
+extern compop_func op_c98_0_comp_nf;
+extern compop_func op_ca0_0_comp_nf;
+extern compop_func op_ca8_0_comp_nf;
+extern compop_func op_cb0_0_comp_nf;
+extern compop_func op_cb8_0_comp_nf;
+extern compop_func op_cb9_0_comp_nf;
+extern compop_func op_cba_0_comp_nf;
+extern compop_func op_cbb_0_comp_nf;
+extern compop_func op_1000_0_comp_nf;
+extern compop_func op_1010_0_comp_nf;
+extern compop_func op_1018_0_comp_nf;
+extern compop_func op_1020_0_comp_nf;
+extern compop_func op_1028_0_comp_nf;
+extern compop_func op_1030_0_comp_nf;
+extern compop_func op_1038_0_comp_nf;
+extern compop_func op_1039_0_comp_nf;
+extern compop_func op_103a_0_comp_nf;
+extern compop_func op_103b_0_comp_nf;
+extern compop_func op_103c_0_comp_nf;
+extern compop_func op_1080_0_comp_nf;
+extern compop_func op_1090_0_comp_nf;
+extern compop_func op_1098_0_comp_nf;
+extern compop_func op_10a0_0_comp_nf;
+extern compop_func op_10a8_0_comp_nf;
+extern compop_func op_10b0_0_comp_nf;
+extern compop_func op_10b8_0_comp_nf;
+extern compop_func op_10b9_0_comp_nf;
+extern compop_func op_10ba_0_comp_nf;
+extern compop_func op_10bb_0_comp_nf;
+extern compop_func op_10bc_0_comp_nf;
+extern compop_func op_10c0_0_comp_nf;
+extern compop_func op_10d0_0_comp_nf;
+extern compop_func op_10d8_0_comp_nf;
+extern compop_func op_10e0_0_comp_nf;
+extern compop_func op_10e8_0_comp_nf;
+extern compop_func op_10f0_0_comp_nf;
+extern compop_func op_10f8_0_comp_nf;
+extern compop_func op_10f9_0_comp_nf;
+extern compop_func op_10fa_0_comp_nf;
+extern compop_func op_10fb_0_comp_nf;
+extern compop_func op_10fc_0_comp_nf;
+extern compop_func op_1100_0_comp_nf;
+extern compop_func op_1110_0_comp_nf;
+extern compop_func op_1118_0_comp_nf;
+extern compop_func op_1120_0_comp_nf;
+extern compop_func op_1128_0_comp_nf;
+extern compop_func op_1130_0_comp_nf;
+extern compop_func op_1138_0_comp_nf;
+extern compop_func op_1139_0_comp_nf;
+extern compop_func op_113a_0_comp_nf;
+extern compop_func op_113b_0_comp_nf;
+extern compop_func op_113c_0_comp_nf;
+extern compop_func op_1140_0_comp_nf;
+extern compop_func op_1150_0_comp_nf;
+extern compop_func op_1158_0_comp_nf;
+extern compop_func op_1160_0_comp_nf;
+extern compop_func op_1168_0_comp_nf;
+extern compop_func op_1170_0_comp_nf;
+extern compop_func op_1178_0_comp_nf;
+extern compop_func op_1179_0_comp_nf;
+extern compop_func op_117a_0_comp_nf;
+extern compop_func op_117b_0_comp_nf;
+extern compop_func op_117c_0_comp_nf;
+extern compop_func op_1180_0_comp_nf;
+extern compop_func op_1190_0_comp_nf;
+extern compop_func op_1198_0_comp_nf;
+extern compop_func op_11a0_0_comp_nf;
+extern compop_func op_11a8_0_comp_nf;
+extern compop_func op_11b0_0_comp_nf;
+extern compop_func op_11b8_0_comp_nf;
+extern compop_func op_11b9_0_comp_nf;
+extern compop_func op_11ba_0_comp_nf;
+extern compop_func op_11bb_0_comp_nf;
+extern compop_func op_11bc_0_comp_nf;
+extern compop_func op_11c0_0_comp_nf;
+extern compop_func op_11d0_0_comp_nf;
+extern compop_func op_11d8_0_comp_nf;
+extern compop_func op_11e0_0_comp_nf;
+extern compop_func op_11e8_0_comp_nf;
+extern compop_func op_11f0_0_comp_nf;
+extern compop_func op_11f8_0_comp_nf;
+extern compop_func op_11f9_0_comp_nf;
+extern compop_func op_11fa_0_comp_nf;
+extern compop_func op_11fb_0_comp_nf;
+extern compop_func op_11fc_0_comp_nf;
+extern compop_func op_13c0_0_comp_nf;
+extern compop_func op_13d0_0_comp_nf;
+extern compop_func op_13d8_0_comp_nf;
+extern compop_func op_13e0_0_comp_nf;
+extern compop_func op_13e8_0_comp_nf;
+extern compop_func op_13f0_0_comp_nf;
+extern compop_func op_13f8_0_comp_nf;
+extern compop_func op_13f9_0_comp_nf;
+extern compop_func op_13fa_0_comp_nf;
+extern compop_func op_13fb_0_comp_nf;
+extern compop_func op_13fc_0_comp_nf;
+extern compop_func op_2000_0_comp_nf;
+extern compop_func op_2008_0_comp_nf;
+extern compop_func op_2010_0_comp_nf;
+extern compop_func op_2018_0_comp_nf;
+extern compop_func op_2020_0_comp_nf;
+extern compop_func op_2028_0_comp_nf;
+extern compop_func op_2030_0_comp_nf;
+extern compop_func op_2038_0_comp_nf;
+extern compop_func op_2039_0_comp_nf;
+extern compop_func op_203a_0_comp_nf;
+extern compop_func op_203b_0_comp_nf;
+extern compop_func op_203c_0_comp_nf;
+extern compop_func op_2040_0_comp_nf;
+extern compop_func op_2048_0_comp_nf;
+extern compop_func op_2050_0_comp_nf;
+extern compop_func op_2058_0_comp_nf;
+extern compop_func op_2060_0_comp_nf;
+extern compop_func op_2068_0_comp_nf;
+extern compop_func op_2070_0_comp_nf;
+extern compop_func op_2078_0_comp_nf;
+extern compop_func op_2079_0_comp_nf;
+extern compop_func op_207a_0_comp_nf;
+extern compop_func op_207b_0_comp_nf;
+extern compop_func op_207c_0_comp_nf;
+extern compop_func op_2080_0_comp_nf;
+extern compop_func op_2088_0_comp_nf;
+extern compop_func op_2090_0_comp_nf;
+extern compop_func op_2098_0_comp_nf;
+extern compop_func op_20a0_0_comp_nf;
+extern compop_func op_20a8_0_comp_nf;
+extern compop_func op_20b0_0_comp_nf;
+extern compop_func op_20b8_0_comp_nf;
+extern compop_func op_20b9_0_comp_nf;
+extern compop_func op_20ba_0_comp_nf;
+extern compop_func op_20bb_0_comp_nf;
+extern compop_func op_20bc_0_comp_nf;
+extern compop_func op_20c0_0_comp_nf;
+extern compop_func op_20c8_0_comp_nf;
+extern compop_func op_20d0_0_comp_nf;
+extern compop_func op_20d8_0_comp_nf;
+extern compop_func op_20e0_0_comp_nf;
+extern compop_func op_20e8_0_comp_nf;
+extern compop_func op_20f0_0_comp_nf;
+extern compop_func op_20f8_0_comp_nf;
+extern compop_func op_20f9_0_comp_nf;
+extern compop_func op_20fa_0_comp_nf;
+extern compop_func op_20fb_0_comp_nf;
+extern compop_func op_20fc_0_comp_nf;
+extern compop_func op_2100_0_comp_nf;
+extern compop_func op_2108_0_comp_nf;
+extern compop_func op_2110_0_comp_nf;
+extern compop_func op_2118_0_comp_nf;
+extern compop_func op_2120_0_comp_nf;
+extern compop_func op_2128_0_comp_nf;
+extern compop_func op_2130_0_comp_nf;
+extern compop_func op_2138_0_comp_nf;
+extern compop_func op_2139_0_comp_nf;
+extern compop_func op_213a_0_comp_nf;
+extern compop_func op_213b_0_comp_nf;
+extern compop_func op_213c_0_comp_nf;
+extern compop_func op_2140_0_comp_nf;
+extern compop_func op_2148_0_comp_nf;
+extern compop_func op_2150_0_comp_nf;
+extern compop_func op_2158_0_comp_nf;
+extern compop_func op_2160_0_comp_nf;
+extern compop_func op_2168_0_comp_nf;
+extern compop_func op_2170_0_comp_nf;
+extern compop_func op_2178_0_comp_nf;
+extern compop_func op_2179_0_comp_nf;
+extern compop_func op_217a_0_comp_nf;
+extern compop_func op_217b_0_comp_nf;
+extern compop_func op_217c_0_comp_nf;
+extern compop_func op_2180_0_comp_nf;
+extern compop_func op_2188_0_comp_nf;
+extern compop_func op_2190_0_comp_nf;
+extern compop_func op_2198_0_comp_nf;
+extern compop_func op_21a0_0_comp_nf;
+extern compop_func op_21a8_0_comp_nf;
+extern compop_func op_21b0_0_comp_nf;
+extern compop_func op_21b8_0_comp_nf;
+extern compop_func op_21b9_0_comp_nf;
+extern compop_func op_21ba_0_comp_nf;
+extern compop_func op_21bb_0_comp_nf;
+extern compop_func op_21bc_0_comp_nf;
+extern compop_func op_21c0_0_comp_nf;
+extern compop_func op_21c8_0_comp_nf;
+extern compop_func op_21d0_0_comp_nf;
+extern compop_func op_21d8_0_comp_nf;
+extern compop_func op_21e0_0_comp_nf;
+extern compop_func op_21e8_0_comp_nf;
+extern compop_func op_21f0_0_comp_nf;
+extern compop_func op_21f8_0_comp_nf;
+extern compop_func op_21f9_0_comp_nf;
+extern compop_func op_21fa_0_comp_nf;
+extern compop_func op_21fb_0_comp_nf;
+extern compop_func op_21fc_0_comp_nf;
+extern compop_func op_23c0_0_comp_nf;
+extern compop_func op_23c8_0_comp_nf;
+extern compop_func op_23d0_0_comp_nf;
+extern compop_func op_23d8_0_comp_nf;
+extern compop_func op_23e0_0_comp_nf;
+extern compop_func op_23e8_0_comp_nf;
+extern compop_func op_23f0_0_comp_nf;
+extern compop_func op_23f8_0_comp_nf;
+extern compop_func op_23f9_0_comp_nf;
+extern compop_func op_23fa_0_comp_nf;
+extern compop_func op_23fb_0_comp_nf;
+extern compop_func op_23fc_0_comp_nf;
+extern compop_func op_3000_0_comp_nf;
+extern compop_func op_3008_0_comp_nf;
+extern compop_func op_3010_0_comp_nf;
+extern compop_func op_3018_0_comp_nf;
+extern compop_func op_3020_0_comp_nf;
+extern compop_func op_3028_0_comp_nf;
+extern compop_func op_3030_0_comp_nf;
+extern compop_func op_3038_0_comp_nf;
+extern compop_func op_3039_0_comp_nf;
+extern compop_func op_303a_0_comp_nf;
+extern compop_func op_303b_0_comp_nf;
+extern compop_func op_303c_0_comp_nf;
+extern compop_func op_3040_0_comp_nf;
+extern compop_func op_3048_0_comp_nf;
+extern compop_func op_3050_0_comp_nf;
+extern compop_func op_3058_0_comp_nf;
+extern compop_func op_3060_0_comp_nf;
+extern compop_func op_3068_0_comp_nf;
+extern compop_func op_3070_0_comp_nf;
+extern compop_func op_3078_0_comp_nf;
+extern compop_func op_3079_0_comp_nf;
+extern compop_func op_307a_0_comp_nf;
+extern compop_func op_307b_0_comp_nf;
+extern compop_func op_307c_0_comp_nf;
+extern compop_func op_3080_0_comp_nf;
+extern compop_func op_3088_0_comp_nf;
+extern compop_func op_3090_0_comp_nf;
+extern compop_func op_3098_0_comp_nf;
+extern compop_func op_30a0_0_comp_nf;
+extern compop_func op_30a8_0_comp_nf;
+extern compop_func op_30b0_0_comp_nf;
+extern compop_func op_30b8_0_comp_nf;
+extern compop_func op_30b9_0_comp_nf;
+extern compop_func op_30ba_0_comp_nf;
+extern compop_func op_30bb_0_comp_nf;
+extern compop_func op_30bc_0_comp_nf;
+extern compop_func op_30c0_0_comp_nf;
+extern compop_func op_30c8_0_comp_nf;
+extern compop_func op_30d0_0_comp_nf;
+extern compop_func op_30d8_0_comp_nf;
+extern compop_func op_30e0_0_comp_nf;
+extern compop_func op_30e8_0_comp_nf;
+extern compop_func op_30f0_0_comp_nf;
+extern compop_func op_30f8_0_comp_nf;
+extern compop_func op_30f9_0_comp_nf;
+extern compop_func op_30fa_0_comp_nf;
+extern compop_func op_30fb_0_comp_nf;
+extern compop_func op_30fc_0_comp_nf;
+extern compop_func op_3100_0_comp_nf;
+extern compop_func op_3108_0_comp_nf;
+extern compop_func op_3110_0_comp_nf;
+extern compop_func op_3118_0_comp_nf;
+extern compop_func op_3120_0_comp_nf;
+extern compop_func op_3128_0_comp_nf;
+extern compop_func op_3130_0_comp_nf;
+extern compop_func op_3138_0_comp_nf;
+extern compop_func op_3139_0_comp_nf;
+extern compop_func op_313a_0_comp_nf;
+extern compop_func op_313b_0_comp_nf;
+extern compop_func op_313c_0_comp_nf;
+extern compop_func op_3140_0_comp_nf;
+extern compop_func op_3148_0_comp_nf;
+extern compop_func op_3150_0_comp_nf;
+extern compop_func op_3158_0_comp_nf;
+extern compop_func op_3160_0_comp_nf;
+extern compop_func op_3168_0_comp_nf;
+extern compop_func op_3170_0_comp_nf;
+extern compop_func op_3178_0_comp_nf;
+extern compop_func op_3179_0_comp_nf;
+extern compop_func op_317a_0_comp_nf;
+extern compop_func op_317b_0_comp_nf;
+extern compop_func op_317c_0_comp_nf;
+extern compop_func op_3180_0_comp_nf;
+extern compop_func op_3188_0_comp_nf;
+extern compop_func op_3190_0_comp_nf;
+extern compop_func op_3198_0_comp_nf;
+extern compop_func op_31a0_0_comp_nf;
+extern compop_func op_31a8_0_comp_nf;
+extern compop_func op_31b0_0_comp_nf;
+extern compop_func op_31b8_0_comp_nf;
+extern compop_func op_31b9_0_comp_nf;
+extern compop_func op_31ba_0_comp_nf;
+extern compop_func op_31bb_0_comp_nf;
+extern compop_func op_31bc_0_comp_nf;
+extern compop_func op_31c0_0_comp_nf;
+extern compop_func op_31c8_0_comp_nf;
+extern compop_func op_31d0_0_comp_nf;
+extern compop_func op_31d8_0_comp_nf;
+extern compop_func op_31e0_0_comp_nf;
+extern compop_func op_31e8_0_comp_nf;
+extern compop_func op_31f0_0_comp_nf;
+extern compop_func op_31f8_0_comp_nf;
+extern compop_func op_31f9_0_comp_nf;
+extern compop_func op_31fa_0_comp_nf;
+extern compop_func op_31fb_0_comp_nf;
+extern compop_func op_31fc_0_comp_nf;
+extern compop_func op_33c0_0_comp_nf;
+extern compop_func op_33c8_0_comp_nf;
+extern compop_func op_33d0_0_comp_nf;
+extern compop_func op_33d8_0_comp_nf;
+extern compop_func op_33e0_0_comp_nf;
+extern compop_func op_33e8_0_comp_nf;
+extern compop_func op_33f0_0_comp_nf;
+extern compop_func op_33f8_0_comp_nf;
+extern compop_func op_33f9_0_comp_nf;
+extern compop_func op_33fa_0_comp_nf;
+extern compop_func op_33fb_0_comp_nf;
+extern compop_func op_33fc_0_comp_nf;
+extern compop_func op_4000_0_comp_nf;
+extern compop_func op_4010_0_comp_nf;
+extern compop_func op_4018_0_comp_nf;
+extern compop_func op_4020_0_comp_nf;
+extern compop_func op_4028_0_comp_nf;
+extern compop_func op_4030_0_comp_nf;
+extern compop_func op_4038_0_comp_nf;
+extern compop_func op_4039_0_comp_nf;
+extern compop_func op_4040_0_comp_nf;
+extern compop_func op_4050_0_comp_nf;
+extern compop_func op_4058_0_comp_nf;
+extern compop_func op_4060_0_comp_nf;
+extern compop_func op_4068_0_comp_nf;
+extern compop_func op_4070_0_comp_nf;
+extern compop_func op_4078_0_comp_nf;
+extern compop_func op_4079_0_comp_nf;
+extern compop_func op_4080_0_comp_nf;
+extern compop_func op_4090_0_comp_nf;
+extern compop_func op_4098_0_comp_nf;
+extern compop_func op_40a0_0_comp_nf;
+extern compop_func op_40a8_0_comp_nf;
+extern compop_func op_40b0_0_comp_nf;
+extern compop_func op_40b8_0_comp_nf;
+extern compop_func op_40b9_0_comp_nf;
+extern compop_func op_41d0_0_comp_nf;
+extern compop_func op_41e8_0_comp_nf;
+extern compop_func op_41f0_0_comp_nf;
+extern compop_func op_41f8_0_comp_nf;
+extern compop_func op_41f9_0_comp_nf;
+extern compop_func op_41fa_0_comp_nf;
+extern compop_func op_41fb_0_comp_nf;
+extern compop_func op_4200_0_comp_nf;
+extern compop_func op_4210_0_comp_nf;
+extern compop_func op_4218_0_comp_nf;
+extern compop_func op_4220_0_comp_nf;
+extern compop_func op_4228_0_comp_nf;
+extern compop_func op_4230_0_comp_nf;
+extern compop_func op_4238_0_comp_nf;
+extern compop_func op_4239_0_comp_nf;
+extern compop_func op_4240_0_comp_nf;
+extern compop_func op_4250_0_comp_nf;
+extern compop_func op_4258_0_comp_nf;
+extern compop_func op_4260_0_comp_nf;
+extern compop_func op_4268_0_comp_nf;
+extern compop_func op_4270_0_comp_nf;
+extern compop_func op_4278_0_comp_nf;
+extern compop_func op_4279_0_comp_nf;
+extern compop_func op_4280_0_comp_nf;
+extern compop_func op_4290_0_comp_nf;
+extern compop_func op_4298_0_comp_nf;
+extern compop_func op_42a0_0_comp_nf;
+extern compop_func op_42a8_0_comp_nf;
+extern compop_func op_42b0_0_comp_nf;
+extern compop_func op_42b8_0_comp_nf;
+extern compop_func op_42b9_0_comp_nf;
+extern compop_func op_4400_0_comp_nf;
+extern compop_func op_4410_0_comp_nf;
+extern compop_func op_4418_0_comp_nf;
+extern compop_func op_4420_0_comp_nf;
+extern compop_func op_4428_0_comp_nf;
+extern compop_func op_4430_0_comp_nf;
+extern compop_func op_4438_0_comp_nf;
+extern compop_func op_4439_0_comp_nf;
+extern compop_func op_4440_0_comp_nf;
+extern compop_func op_4450_0_comp_nf;
+extern compop_func op_4458_0_comp_nf;
+extern compop_func op_4460_0_comp_nf;
+extern compop_func op_4468_0_comp_nf;
+extern compop_func op_4470_0_comp_nf;
+extern compop_func op_4478_0_comp_nf;
+extern compop_func op_4479_0_comp_nf;
+extern compop_func op_4480_0_comp_nf;
+extern compop_func op_4490_0_comp_nf;
+extern compop_func op_4498_0_comp_nf;
+extern compop_func op_44a0_0_comp_nf;
+extern compop_func op_44a8_0_comp_nf;
+extern compop_func op_44b0_0_comp_nf;
+extern compop_func op_44b8_0_comp_nf;
+extern compop_func op_44b9_0_comp_nf;
+extern compop_func op_4600_0_comp_nf;
+extern compop_func op_4610_0_comp_nf;
+extern compop_func op_4618_0_comp_nf;
+extern compop_func op_4620_0_comp_nf;
+extern compop_func op_4628_0_comp_nf;
+extern compop_func op_4630_0_comp_nf;
+extern compop_func op_4638_0_comp_nf;
+extern compop_func op_4639_0_comp_nf;
+extern compop_func op_4640_0_comp_nf;
+extern compop_func op_4650_0_comp_nf;
+extern compop_func op_4658_0_comp_nf;
+extern compop_func op_4660_0_comp_nf;
+extern compop_func op_4668_0_comp_nf;
+extern compop_func op_4670_0_comp_nf;
+extern compop_func op_4678_0_comp_nf;
+extern compop_func op_4679_0_comp_nf;
+extern compop_func op_4680_0_comp_nf;
+extern compop_func op_4690_0_comp_nf;
+extern compop_func op_4698_0_comp_nf;
+extern compop_func op_46a0_0_comp_nf;
+extern compop_func op_46a8_0_comp_nf;
+extern compop_func op_46b0_0_comp_nf;
+extern compop_func op_46b8_0_comp_nf;
+extern compop_func op_46b9_0_comp_nf;
+extern compop_func op_4808_0_comp_nf;
+extern compop_func op_4840_0_comp_nf;
+extern compop_func op_4850_0_comp_nf;
+extern compop_func op_4868_0_comp_nf;
+extern compop_func op_4870_0_comp_nf;
+extern compop_func op_4878_0_comp_nf;
+extern compop_func op_4879_0_comp_nf;
+extern compop_func op_487a_0_comp_nf;
+extern compop_func op_487b_0_comp_nf;
+extern compop_func op_4880_0_comp_nf;
+extern compop_func op_4890_0_comp_nf;
+extern compop_func op_48a0_0_comp_nf;
+extern compop_func op_48a8_0_comp_nf;
+extern compop_func op_48b0_0_comp_nf;
+extern compop_func op_48b8_0_comp_nf;
+extern compop_func op_48b9_0_comp_nf;
+extern compop_func op_48c0_0_comp_nf;
+extern compop_func op_48d0_0_comp_nf;
+extern compop_func op_48e0_0_comp_nf;
+extern compop_func op_48e8_0_comp_nf;
+extern compop_func op_48f0_0_comp_nf;
+extern compop_func op_48f8_0_comp_nf;
+extern compop_func op_48f9_0_comp_nf;
+extern compop_func op_49c0_0_comp_nf;
+extern compop_func op_4a00_0_comp_nf;
+extern compop_func op_4a10_0_comp_nf;
+extern compop_func op_4a18_0_comp_nf;
+extern compop_func op_4a20_0_comp_nf;
+extern compop_func op_4a28_0_comp_nf;
+extern compop_func op_4a30_0_comp_nf;
+extern compop_func op_4a38_0_comp_nf;
+extern compop_func op_4a39_0_comp_nf;
+extern compop_func op_4a3a_0_comp_nf;
+extern compop_func op_4a3b_0_comp_nf;
+extern compop_func op_4a40_0_comp_nf;
+extern compop_func op_4a48_0_comp_nf;
+extern compop_func op_4a50_0_comp_nf;
+extern compop_func op_4a58_0_comp_nf;
+extern compop_func op_4a60_0_comp_nf;
+extern compop_func op_4a68_0_comp_nf;
+extern compop_func op_4a70_0_comp_nf;
+extern compop_func op_4a78_0_comp_nf;
+extern compop_func op_4a79_0_comp_nf;
+extern compop_func op_4a7a_0_comp_nf;
+extern compop_func op_4a7b_0_comp_nf;
+extern compop_func op_4a80_0_comp_nf;
+extern compop_func op_4a88_0_comp_nf;
+extern compop_func op_4a90_0_comp_nf;
+extern compop_func op_4a98_0_comp_nf;
+extern compop_func op_4aa0_0_comp_nf;
+extern compop_func op_4aa8_0_comp_nf;
+extern compop_func op_4ab0_0_comp_nf;
+extern compop_func op_4ab8_0_comp_nf;
+extern compop_func op_4ab9_0_comp_nf;
+extern compop_func op_4aba_0_comp_nf;
+extern compop_func op_4abb_0_comp_nf;
+extern compop_func op_4c00_0_comp_nf;
+extern compop_func op_4c10_0_comp_nf;
+extern compop_func op_4c18_0_comp_nf;
+extern compop_func op_4c20_0_comp_nf;
+extern compop_func op_4c28_0_comp_nf;
+extern compop_func op_4c30_0_comp_nf;
+extern compop_func op_4c38_0_comp_nf;
+extern compop_func op_4c39_0_comp_nf;
+extern compop_func op_4c3a_0_comp_nf;
+extern compop_func op_4c3b_0_comp_nf;
+extern compop_func op_4c3c_0_comp_nf;
+extern compop_func op_4c90_0_comp_nf;
+extern compop_func op_4c98_0_comp_nf;
+extern compop_func op_4ca8_0_comp_nf;
+extern compop_func op_4cb0_0_comp_nf;
+extern compop_func op_4cb8_0_comp_nf;
+extern compop_func op_4cb9_0_comp_nf;
+extern compop_func op_4cba_0_comp_nf;
+extern compop_func op_4cbb_0_comp_nf;
+extern compop_func op_4cd0_0_comp_nf;
+extern compop_func op_4cd8_0_comp_nf;
+extern compop_func op_4ce8_0_comp_nf;
+extern compop_func op_4cf0_0_comp_nf;
+extern compop_func op_4cf8_0_comp_nf;
+extern compop_func op_4cf9_0_comp_nf;
+extern compop_func op_4cfa_0_comp_nf;
+extern compop_func op_4cfb_0_comp_nf;
+extern compop_func op_4e50_0_comp_nf;
+extern compop_func op_4e58_0_comp_nf;
+extern compop_func op_4e71_0_comp_nf;
+extern compop_func op_4e74_0_comp_nf;
+extern compop_func op_4e75_0_comp_nf;
+extern compop_func op_4e90_0_comp_nf;
+extern compop_func op_4ea8_0_comp_nf;
+extern compop_func op_4eb0_0_comp_nf;
+extern compop_func op_4eb8_0_comp_nf;
+extern compop_func op_4eb9_0_comp_nf;
+extern compop_func op_4eba_0_comp_nf;
+extern compop_func op_4ebb_0_comp_nf;
+extern compop_func op_4ed0_0_comp_nf;
+extern compop_func op_4ee8_0_comp_nf;
+extern compop_func op_4ef0_0_comp_nf;
+extern compop_func op_4ef8_0_comp_nf;
+extern compop_func op_4ef9_0_comp_nf;
+extern compop_func op_4efa_0_comp_nf;
+extern compop_func op_4efb_0_comp_nf;
+extern compop_func op_5000_0_comp_nf;
+extern compop_func op_5010_0_comp_nf;
+extern compop_func op_5018_0_comp_nf;
+extern compop_func op_5020_0_comp_nf;
+extern compop_func op_5028_0_comp_nf;
+extern compop_func op_5030_0_comp_nf;
+extern compop_func op_5038_0_comp_nf;
+extern compop_func op_5039_0_comp_nf;
+extern compop_func op_5040_0_comp_nf;
+extern compop_func op_5048_0_comp_nf;
+extern compop_func op_5050_0_comp_nf;
+extern compop_func op_5058_0_comp_nf;
+extern compop_func op_5060_0_comp_nf;
+extern compop_func op_5068_0_comp_nf;
+extern compop_func op_5070_0_comp_nf;
+extern compop_func op_5078_0_comp_nf;
+extern compop_func op_5079_0_comp_nf;
+extern compop_func op_5080_0_comp_nf;
+extern compop_func op_5088_0_comp_nf;
+extern compop_func op_5090_0_comp_nf;
+extern compop_func op_5098_0_comp_nf;
+extern compop_func op_50a0_0_comp_nf;
+extern compop_func op_50a8_0_comp_nf;
+extern compop_func op_50b0_0_comp_nf;
+extern compop_func op_50b8_0_comp_nf;
+extern compop_func op_50b9_0_comp_nf;
+extern compop_func op_50c0_0_comp_nf;
+extern compop_func op_50c8_0_comp_nf;
+extern compop_func op_50d0_0_comp_nf;
+extern compop_func op_50d8_0_comp_nf;
+extern compop_func op_50e0_0_comp_nf;
+extern compop_func op_50e8_0_comp_nf;
+extern compop_func op_50f0_0_comp_nf;
+extern compop_func op_50f8_0_comp_nf;
+extern compop_func op_50f9_0_comp_nf;
+extern compop_func op_5100_0_comp_nf;
+extern compop_func op_5110_0_comp_nf;
+extern compop_func op_5118_0_comp_nf;
+extern compop_func op_5120_0_comp_nf;
+extern compop_func op_5128_0_comp_nf;
+extern compop_func op_5130_0_comp_nf;
+extern compop_func op_5138_0_comp_nf;
+extern compop_func op_5139_0_comp_nf;
+extern compop_func op_5140_0_comp_nf;
+extern compop_func op_5148_0_comp_nf;
+extern compop_func op_5150_0_comp_nf;
+extern compop_func op_5158_0_comp_nf;
+extern compop_func op_5160_0_comp_nf;
+extern compop_func op_5168_0_comp_nf;
+extern compop_func op_5170_0_comp_nf;
+extern compop_func op_5178_0_comp_nf;
+extern compop_func op_5179_0_comp_nf;
+extern compop_func op_5180_0_comp_nf;
+extern compop_func op_5188_0_comp_nf;
+extern compop_func op_5190_0_comp_nf;
+extern compop_func op_5198_0_comp_nf;
+extern compop_func op_51a0_0_comp_nf;
+extern compop_func op_51a8_0_comp_nf;
+extern compop_func op_51b0_0_comp_nf;
+extern compop_func op_51b8_0_comp_nf;
+extern compop_func op_51b9_0_comp_nf;
+extern compop_func op_51c0_0_comp_nf;
+extern compop_func op_51c8_0_comp_nf;
+extern compop_func op_51d0_0_comp_nf;
+extern compop_func op_51d8_0_comp_nf;
+extern compop_func op_51e0_0_comp_nf;
+extern compop_func op_51e8_0_comp_nf;
+extern compop_func op_51f0_0_comp_nf;
+extern compop_func op_51f8_0_comp_nf;
+extern compop_func op_51f9_0_comp_nf;
+extern compop_func op_52c0_0_comp_nf;
+extern compop_func op_52c8_0_comp_nf;
+extern compop_func op_52d0_0_comp_nf;
+extern compop_func op_52d8_0_comp_nf;
+extern compop_func op_52e0_0_comp_nf;
+extern compop_func op_52e8_0_comp_nf;
+extern compop_func op_52f0_0_comp_nf;
+extern compop_func op_52f8_0_comp_nf;
+extern compop_func op_52f9_0_comp_nf;
+extern compop_func op_53c0_0_comp_nf;
+extern compop_func op_53c8_0_comp_nf;
+extern compop_func op_53d0_0_comp_nf;
+extern compop_func op_53d8_0_comp_nf;
+extern compop_func op_53e0_0_comp_nf;
+extern compop_func op_53e8_0_comp_nf;
+extern compop_func op_53f0_0_comp_nf;
+extern compop_func op_53f8_0_comp_nf;
+extern compop_func op_53f9_0_comp_nf;
+extern compop_func op_54c0_0_comp_nf;
+extern compop_func op_54c8_0_comp_nf;
+extern compop_func op_54d0_0_comp_nf;
+extern compop_func op_54d8_0_comp_nf;
+extern compop_func op_54e0_0_comp_nf;
+extern compop_func op_54e8_0_comp_nf;
+extern compop_func op_54f0_0_comp_nf;
+extern compop_func op_54f8_0_comp_nf;
+extern compop_func op_54f9_0_comp_nf;
+extern compop_func op_55c0_0_comp_nf;
+extern compop_func op_55c8_0_comp_nf;
+extern compop_func op_55d0_0_comp_nf;
+extern compop_func op_55d8_0_comp_nf;
+extern compop_func op_55e0_0_comp_nf;
+extern compop_func op_55e8_0_comp_nf;
+extern compop_func op_55f0_0_comp_nf;
+extern compop_func op_55f8_0_comp_nf;
+extern compop_func op_55f9_0_comp_nf;
+extern compop_func op_56c0_0_comp_nf;
+extern compop_func op_56c8_0_comp_nf;
+extern compop_func op_56d0_0_comp_nf;
+extern compop_func op_56d8_0_comp_nf;
+extern compop_func op_56e0_0_comp_nf;
+extern compop_func op_56e8_0_comp_nf;
+extern compop_func op_56f0_0_comp_nf;
+extern compop_func op_56f8_0_comp_nf;
+extern compop_func op_56f9_0_comp_nf;
+extern compop_func op_57c0_0_comp_nf;
+extern compop_func op_57c8_0_comp_nf;
+extern compop_func op_57d0_0_comp_nf;
+extern compop_func op_57d8_0_comp_nf;
+extern compop_func op_57e0_0_comp_nf;
+extern compop_func op_57e8_0_comp_nf;
+extern compop_func op_57f0_0_comp_nf;
+extern compop_func op_57f8_0_comp_nf;
+extern compop_func op_57f9_0_comp_nf;
+extern compop_func op_5ac0_0_comp_nf;
+extern compop_func op_5ac8_0_comp_nf;
+extern compop_func op_5ad0_0_comp_nf;
+extern compop_func op_5ad8_0_comp_nf;
+extern compop_func op_5ae0_0_comp_nf;
+extern compop_func op_5ae8_0_comp_nf;
+extern compop_func op_5af0_0_comp_nf;
+extern compop_func op_5af8_0_comp_nf;
+extern compop_func op_5af9_0_comp_nf;
+extern compop_func op_5bc0_0_comp_nf;
+extern compop_func op_5bc8_0_comp_nf;
+extern compop_func op_5bd0_0_comp_nf;
+extern compop_func op_5bd8_0_comp_nf;
+extern compop_func op_5be0_0_comp_nf;
+extern compop_func op_5be8_0_comp_nf;
+extern compop_func op_5bf0_0_comp_nf;
+extern compop_func op_5bf8_0_comp_nf;
+extern compop_func op_5bf9_0_comp_nf;
+extern compop_func op_5cc0_0_comp_nf;
+extern compop_func op_5cc8_0_comp_nf;
+extern compop_func op_5cd0_0_comp_nf;
+extern compop_func op_5cd8_0_comp_nf;
+extern compop_func op_5ce0_0_comp_nf;
+extern compop_func op_5ce8_0_comp_nf;
+extern compop_func op_5cf0_0_comp_nf;
+extern compop_func op_5cf8_0_comp_nf;
+extern compop_func op_5cf9_0_comp_nf;
+extern compop_func op_5dc0_0_comp_nf;
+extern compop_func op_5dc8_0_comp_nf;
+extern compop_func op_5dd0_0_comp_nf;
+extern compop_func op_5dd8_0_comp_nf;
+extern compop_func op_5de0_0_comp_nf;
+extern compop_func op_5de8_0_comp_nf;
+extern compop_func op_5df0_0_comp_nf;
+extern compop_func op_5df8_0_comp_nf;
+extern compop_func op_5df9_0_comp_nf;
+extern compop_func op_5ec0_0_comp_nf;
+extern compop_func op_5ec8_0_comp_nf;
+extern compop_func op_5ed0_0_comp_nf;
+extern compop_func op_5ed8_0_comp_nf;
+extern compop_func op_5ee0_0_comp_nf;
+extern compop_func op_5ee8_0_comp_nf;
+extern compop_func op_5ef0_0_comp_nf;
+extern compop_func op_5ef8_0_comp_nf;
+extern compop_func op_5ef9_0_comp_nf;
+extern compop_func op_5fc0_0_comp_nf;
+extern compop_func op_5fc8_0_comp_nf;
+extern compop_func op_5fd0_0_comp_nf;
+extern compop_func op_5fd8_0_comp_nf;
+extern compop_func op_5fe0_0_comp_nf;
+extern compop_func op_5fe8_0_comp_nf;
+extern compop_func op_5ff0_0_comp_nf;
+extern compop_func op_5ff8_0_comp_nf;
+extern compop_func op_5ff9_0_comp_nf;
+extern compop_func op_6000_0_comp_nf;
+extern compop_func op_6001_0_comp_nf;
+extern compop_func op_60ff_0_comp_nf;
+extern compop_func op_6100_0_comp_nf;
+extern compop_func op_6101_0_comp_nf;
+extern compop_func op_6200_0_comp_nf;
+extern compop_func op_6201_0_comp_nf;
+extern compop_func op_62ff_0_comp_nf;
+extern compop_func op_6300_0_comp_nf;
+extern compop_func op_6301_0_comp_nf;
+extern compop_func op_63ff_0_comp_nf;
+extern compop_func op_6400_0_comp_nf;
+extern compop_func op_6401_0_comp_nf;
+extern compop_func op_64ff_0_comp_nf;
+extern compop_func op_6500_0_comp_nf;
+extern compop_func op_6501_0_comp_nf;
+extern compop_func op_65ff_0_comp_nf;
+extern compop_func op_6600_0_comp_nf;
+extern compop_func op_6601_0_comp_nf;
+extern compop_func op_66ff_0_comp_nf;
+extern compop_func op_6700_0_comp_nf;
+extern compop_func op_6701_0_comp_nf;
+extern compop_func op_67ff_0_comp_nf;
+extern compop_func op_6a00_0_comp_nf;
+extern compop_func op_6a01_0_comp_nf;
+extern compop_func op_6aff_0_comp_nf;
+extern compop_func op_6b00_0_comp_nf;
+extern compop_func op_6b01_0_comp_nf;
+extern compop_func op_6bff_0_comp_nf;
+extern compop_func op_6c00_0_comp_nf;
+extern compop_func op_6c01_0_comp_nf;
+extern compop_func op_6cff_0_comp_nf;
+extern compop_func op_6d00_0_comp_nf;
+extern compop_func op_6d01_0_comp_nf;
+extern compop_func op_6dff_0_comp_nf;
+extern compop_func op_6e00_0_comp_nf;
+extern compop_func op_6e01_0_comp_nf;
+extern compop_func op_6eff_0_comp_nf;
+extern compop_func op_6f00_0_comp_nf;
+extern compop_func op_6f01_0_comp_nf;
+extern compop_func op_6fff_0_comp_nf;
+extern compop_func op_7000_0_comp_nf;
+extern compop_func op_8000_0_comp_nf;
+extern compop_func op_8010_0_comp_nf;
+extern compop_func op_8018_0_comp_nf;
+extern compop_func op_8020_0_comp_nf;
+extern compop_func op_8028_0_comp_nf;
+extern compop_func op_8030_0_comp_nf;
+extern compop_func op_8038_0_comp_nf;
+extern compop_func op_8039_0_comp_nf;
+extern compop_func op_803a_0_comp_nf;
+extern compop_func op_803b_0_comp_nf;
+extern compop_func op_803c_0_comp_nf;
+extern compop_func op_8040_0_comp_nf;
+extern compop_func op_8050_0_comp_nf;
+extern compop_func op_8058_0_comp_nf;
+extern compop_func op_8060_0_comp_nf;
+extern compop_func op_8068_0_comp_nf;
+extern compop_func op_8070_0_comp_nf;
+extern compop_func op_8078_0_comp_nf;
+extern compop_func op_8079_0_comp_nf;
+extern compop_func op_807a_0_comp_nf;
+extern compop_func op_807b_0_comp_nf;
+extern compop_func op_807c_0_comp_nf;
+extern compop_func op_8080_0_comp_nf;
+extern compop_func op_8090_0_comp_nf;
+extern compop_func op_8098_0_comp_nf;
+extern compop_func op_80a0_0_comp_nf;
+extern compop_func op_80a8_0_comp_nf;
+extern compop_func op_80b0_0_comp_nf;
+extern compop_func op_80b8_0_comp_nf;
+extern compop_func op_80b9_0_comp_nf;
+extern compop_func op_80ba_0_comp_nf;
+extern compop_func op_80bb_0_comp_nf;
+extern compop_func op_80bc_0_comp_nf;
+extern compop_func op_8110_0_comp_nf;
+extern compop_func op_8118_0_comp_nf;
+extern compop_func op_8120_0_comp_nf;
+extern compop_func op_8128_0_comp_nf;
+extern compop_func op_8130_0_comp_nf;
+extern compop_func op_8138_0_comp_nf;
+extern compop_func op_8139_0_comp_nf;
+extern compop_func op_8150_0_comp_nf;
+extern compop_func op_8158_0_comp_nf;
+extern compop_func op_8160_0_comp_nf;
+extern compop_func op_8168_0_comp_nf;
+extern compop_func op_8170_0_comp_nf;
+extern compop_func op_8178_0_comp_nf;
+extern compop_func op_8179_0_comp_nf;
+extern compop_func op_8190_0_comp_nf;
+extern compop_func op_8198_0_comp_nf;
+extern compop_func op_81a0_0_comp_nf;
+extern compop_func op_81a8_0_comp_nf;
+extern compop_func op_81b0_0_comp_nf;
+extern compop_func op_81b8_0_comp_nf;
+extern compop_func op_81b9_0_comp_nf;
+extern compop_func op_9000_0_comp_nf;
+extern compop_func op_9010_0_comp_nf;
+extern compop_func op_9018_0_comp_nf;
+extern compop_func op_9020_0_comp_nf;
+extern compop_func op_9028_0_comp_nf;
+extern compop_func op_9030_0_comp_nf;
+extern compop_func op_9038_0_comp_nf;
+extern compop_func op_9039_0_comp_nf;
+extern compop_func op_903a_0_comp_nf;
+extern compop_func op_903b_0_comp_nf;
+extern compop_func op_903c_0_comp_nf;
+extern compop_func op_9040_0_comp_nf;
+extern compop_func op_9048_0_comp_nf;
+extern compop_func op_9050_0_comp_nf;
+extern compop_func op_9058_0_comp_nf;
+extern compop_func op_9060_0_comp_nf;
+extern compop_func op_9068_0_comp_nf;
+extern compop_func op_9070_0_comp_nf;
+extern compop_func op_9078_0_comp_nf;
+extern compop_func op_9079_0_comp_nf;
+extern compop_func op_907a_0_comp_nf;
+extern compop_func op_907b_0_comp_nf;
+extern compop_func op_907c_0_comp_nf;
+extern compop_func op_9080_0_comp_nf;
+extern compop_func op_9088_0_comp_nf;
+extern compop_func op_9090_0_comp_nf;
+extern compop_func op_9098_0_comp_nf;
+extern compop_func op_90a0_0_comp_nf;
+extern compop_func op_90a8_0_comp_nf;
+extern compop_func op_90b0_0_comp_nf;
+extern compop_func op_90b8_0_comp_nf;
+extern compop_func op_90b9_0_comp_nf;
+extern compop_func op_90ba_0_comp_nf;
+extern compop_func op_90bb_0_comp_nf;
+extern compop_func op_90bc_0_comp_nf;
+extern compop_func op_90c0_0_comp_nf;
+extern compop_func op_90c8_0_comp_nf;
+extern compop_func op_90d0_0_comp_nf;
+extern compop_func op_90d8_0_comp_nf;
+extern compop_func op_90e0_0_comp_nf;
+extern compop_func op_90e8_0_comp_nf;
+extern compop_func op_90f0_0_comp_nf;
+extern compop_func op_90f8_0_comp_nf;
+extern compop_func op_90f9_0_comp_nf;
+extern compop_func op_90fa_0_comp_nf;
+extern compop_func op_90fb_0_comp_nf;
+extern compop_func op_90fc_0_comp_nf;
+extern compop_func op_9100_0_comp_nf;
+extern compop_func op_9108_0_comp_nf;
+extern compop_func op_9110_0_comp_nf;
+extern compop_func op_9118_0_comp_nf;
+extern compop_func op_9120_0_comp_nf;
+extern compop_func op_9128_0_comp_nf;
+extern compop_func op_9130_0_comp_nf;
+extern compop_func op_9138_0_comp_nf;
+extern compop_func op_9139_0_comp_nf;
+extern compop_func op_9140_0_comp_nf;
+extern compop_func op_9148_0_comp_nf;
+extern compop_func op_9150_0_comp_nf;
+extern compop_func op_9158_0_comp_nf;
+extern compop_func op_9160_0_comp_nf;
+extern compop_func op_9168_0_comp_nf;
+extern compop_func op_9170_0_comp_nf;
+extern compop_func op_9178_0_comp_nf;
+extern compop_func op_9179_0_comp_nf;
+extern compop_func op_9180_0_comp_nf;
+extern compop_func op_9188_0_comp_nf;
+extern compop_func op_9190_0_comp_nf;
+extern compop_func op_9198_0_comp_nf;
+extern compop_func op_91a0_0_comp_nf;
+extern compop_func op_91a8_0_comp_nf;
+extern compop_func op_91b0_0_comp_nf;
+extern compop_func op_91b8_0_comp_nf;
+extern compop_func op_91b9_0_comp_nf;
+extern compop_func op_91c0_0_comp_nf;
+extern compop_func op_91c8_0_comp_nf;
+extern compop_func op_91d0_0_comp_nf;
+extern compop_func op_91d8_0_comp_nf;
+extern compop_func op_91e0_0_comp_nf;
+extern compop_func op_91e8_0_comp_nf;
+extern compop_func op_91f0_0_comp_nf;
+extern compop_func op_91f8_0_comp_nf;
+extern compop_func op_91f9_0_comp_nf;
+extern compop_func op_91fa_0_comp_nf;
+extern compop_func op_91fb_0_comp_nf;
+extern compop_func op_91fc_0_comp_nf;
+extern compop_func op_b000_0_comp_nf;
+extern compop_func op_b010_0_comp_nf;
+extern compop_func op_b018_0_comp_nf;
+extern compop_func op_b020_0_comp_nf;
+extern compop_func op_b028_0_comp_nf;
+extern compop_func op_b030_0_comp_nf;
+extern compop_func op_b038_0_comp_nf;
+extern compop_func op_b039_0_comp_nf;
+extern compop_func op_b03a_0_comp_nf;
+extern compop_func op_b03b_0_comp_nf;
+extern compop_func op_b03c_0_comp_nf;
+extern compop_func op_b040_0_comp_nf;
+extern compop_func op_b048_0_comp_nf;
+extern compop_func op_b050_0_comp_nf;
+extern compop_func op_b058_0_comp_nf;
+extern compop_func op_b060_0_comp_nf;
+extern compop_func op_b068_0_comp_nf;
+extern compop_func op_b070_0_comp_nf;
+extern compop_func op_b078_0_comp_nf;
+extern compop_func op_b079_0_comp_nf;
+extern compop_func op_b07a_0_comp_nf;
+extern compop_func op_b07b_0_comp_nf;
+extern compop_func op_b07c_0_comp_nf;
+extern compop_func op_b080_0_comp_nf;
+extern compop_func op_b088_0_comp_nf;
+extern compop_func op_b090_0_comp_nf;
+extern compop_func op_b098_0_comp_nf;
+extern compop_func op_b0a0_0_comp_nf;
+extern compop_func op_b0a8_0_comp_nf;
+extern compop_func op_b0b0_0_comp_nf;
+extern compop_func op_b0b8_0_comp_nf;
+extern compop_func op_b0b9_0_comp_nf;
+extern compop_func op_b0ba_0_comp_nf;
+extern compop_func op_b0bb_0_comp_nf;
+extern compop_func op_b0bc_0_comp_nf;
+extern compop_func op_b0c0_0_comp_nf;
+extern compop_func op_b0c8_0_comp_nf;
+extern compop_func op_b0d0_0_comp_nf;
+extern compop_func op_b0d8_0_comp_nf;
+extern compop_func op_b0e0_0_comp_nf;
+extern compop_func op_b0e8_0_comp_nf;
+extern compop_func op_b0f0_0_comp_nf;
+extern compop_func op_b0f8_0_comp_nf;
+extern compop_func op_b0f9_0_comp_nf;
+extern compop_func op_b0fa_0_comp_nf;
+extern compop_func op_b0fb_0_comp_nf;
+extern compop_func op_b0fc_0_comp_nf;
+extern compop_func op_b100_0_comp_nf;
+extern compop_func op_b108_0_comp_nf;
+extern compop_func op_b110_0_comp_nf;
+extern compop_func op_b118_0_comp_nf;
+extern compop_func op_b120_0_comp_nf;
+extern compop_func op_b128_0_comp_nf;
+extern compop_func op_b130_0_comp_nf;
+extern compop_func op_b138_0_comp_nf;
+extern compop_func op_b139_0_comp_nf;
+extern compop_func op_b140_0_comp_nf;
+extern compop_func op_b148_0_comp_nf;
+extern compop_func op_b150_0_comp_nf;
+extern compop_func op_b158_0_comp_nf;
+extern compop_func op_b160_0_comp_nf;
+extern compop_func op_b168_0_comp_nf;
+extern compop_func op_b170_0_comp_nf;
+extern compop_func op_b178_0_comp_nf;
+extern compop_func op_b179_0_comp_nf;
+extern compop_func op_b180_0_comp_nf;
+extern compop_func op_b188_0_comp_nf;
+extern compop_func op_b190_0_comp_nf;
+extern compop_func op_b198_0_comp_nf;
+extern compop_func op_b1a0_0_comp_nf;
+extern compop_func op_b1a8_0_comp_nf;
+extern compop_func op_b1b0_0_comp_nf;
+extern compop_func op_b1b8_0_comp_nf;
+extern compop_func op_b1b9_0_comp_nf;
+extern compop_func op_b1c0_0_comp_nf;
+extern compop_func op_b1c8_0_comp_nf;
+extern compop_func op_b1d0_0_comp_nf;
+extern compop_func op_b1d8_0_comp_nf;
+extern compop_func op_b1e0_0_comp_nf;
+extern compop_func op_b1e8_0_comp_nf;
+extern compop_func op_b1f0_0_comp_nf;
+extern compop_func op_b1f8_0_comp_nf;
+extern compop_func op_b1f9_0_comp_nf;
+extern compop_func op_b1fa_0_comp_nf;
+extern compop_func op_b1fb_0_comp_nf;
+extern compop_func op_b1fc_0_comp_nf;
+extern compop_func op_c000_0_comp_nf;
+extern compop_func op_c010_0_comp_nf;
+extern compop_func op_c018_0_comp_nf;
+extern compop_func op_c020_0_comp_nf;
+extern compop_func op_c028_0_comp_nf;
+extern compop_func op_c030_0_comp_nf;
+extern compop_func op_c038_0_comp_nf;
+extern compop_func op_c039_0_comp_nf;
+extern compop_func op_c03a_0_comp_nf;
+extern compop_func op_c03b_0_comp_nf;
+extern compop_func op_c03c_0_comp_nf;
+extern compop_func op_c040_0_comp_nf;
+extern compop_func op_c050_0_comp_nf;
+extern compop_func op_c058_0_comp_nf;
+extern compop_func op_c060_0_comp_nf;
+extern compop_func op_c068_0_comp_nf;
+extern compop_func op_c070_0_comp_nf;
+extern compop_func op_c078_0_comp_nf;
+extern compop_func op_c079_0_comp_nf;
+extern compop_func op_c07a_0_comp_nf;
+extern compop_func op_c07b_0_comp_nf;
+extern compop_func op_c07c_0_comp_nf;
+extern compop_func op_c080_0_comp_nf;
+extern compop_func op_c090_0_comp_nf;
+extern compop_func op_c098_0_comp_nf;
+extern compop_func op_c0a0_0_comp_nf;
+extern compop_func op_c0a8_0_comp_nf;
+extern compop_func op_c0b0_0_comp_nf;
+extern compop_func op_c0b8_0_comp_nf;
+extern compop_func op_c0b9_0_comp_nf;
+extern compop_func op_c0ba_0_comp_nf;
+extern compop_func op_c0bb_0_comp_nf;
+extern compop_func op_c0bc_0_comp_nf;
+extern compop_func op_c0c0_0_comp_nf;
+extern compop_func op_c0d0_0_comp_nf;
+extern compop_func op_c0d8_0_comp_nf;
+extern compop_func op_c0e0_0_comp_nf;
+extern compop_func op_c0e8_0_comp_nf;
+extern compop_func op_c0f0_0_comp_nf;
+extern compop_func op_c0f8_0_comp_nf;
+extern compop_func op_c0f9_0_comp_nf;
+extern compop_func op_c0fa_0_comp_nf;
+extern compop_func op_c0fb_0_comp_nf;
+extern compop_func op_c0fc_0_comp_nf;
+extern compop_func op_c110_0_comp_nf;
+extern compop_func op_c118_0_comp_nf;
+extern compop_func op_c120_0_comp_nf;
+extern compop_func op_c128_0_comp_nf;
+extern compop_func op_c130_0_comp_nf;
+extern compop_func op_c138_0_comp_nf;
+extern compop_func op_c139_0_comp_nf;
+extern compop_func op_c140_0_comp_nf;
+extern compop_func op_c148_0_comp_nf;
+extern compop_func op_c150_0_comp_nf;
+extern compop_func op_c158_0_comp_nf;
+extern compop_func op_c160_0_comp_nf;
+extern compop_func op_c168_0_comp_nf;
+extern compop_func op_c170_0_comp_nf;
+extern compop_func op_c178_0_comp_nf;
+extern compop_func op_c179_0_comp_nf;
+extern compop_func op_c188_0_comp_nf;
+extern compop_func op_c190_0_comp_nf;
+extern compop_func op_c198_0_comp_nf;
+extern compop_func op_c1a0_0_comp_nf;
+extern compop_func op_c1a8_0_comp_nf;
+extern compop_func op_c1b0_0_comp_nf;
+extern compop_func op_c1b8_0_comp_nf;
+extern compop_func op_c1b9_0_comp_nf;
+extern compop_func op_c1c0_0_comp_nf;
+extern compop_func op_c1d0_0_comp_nf;
+extern compop_func op_c1d8_0_comp_nf;
+extern compop_func op_c1e0_0_comp_nf;
+extern compop_func op_c1e8_0_comp_nf;
+extern compop_func op_c1f0_0_comp_nf;
+extern compop_func op_c1f8_0_comp_nf;
+extern compop_func op_c1f9_0_comp_nf;
+extern compop_func op_c1fa_0_comp_nf;
+extern compop_func op_c1fb_0_comp_nf;
+extern compop_func op_c1fc_0_comp_nf;
+extern compop_func op_d000_0_comp_nf;
+extern compop_func op_d010_0_comp_nf;
+extern compop_func op_d018_0_comp_nf;
+extern compop_func op_d020_0_comp_nf;
+extern compop_func op_d028_0_comp_nf;
+extern compop_func op_d030_0_comp_nf;
+extern compop_func op_d038_0_comp_nf;
+extern compop_func op_d039_0_comp_nf;
+extern compop_func op_d03a_0_comp_nf;
+extern compop_func op_d03b_0_comp_nf;
+extern compop_func op_d03c_0_comp_nf;
+extern compop_func op_d040_0_comp_nf;
+extern compop_func op_d048_0_comp_nf;
+extern compop_func op_d050_0_comp_nf;
+extern compop_func op_d058_0_comp_nf;
+extern compop_func op_d060_0_comp_nf;
+extern compop_func op_d068_0_comp_nf;
+extern compop_func op_d070_0_comp_nf;
+extern compop_func op_d078_0_comp_nf;
+extern compop_func op_d079_0_comp_nf;
+extern compop_func op_d07a_0_comp_nf;
+extern compop_func op_d07b_0_comp_nf;
+extern compop_func op_d07c_0_comp_nf;
+extern compop_func op_d080_0_comp_nf;
+extern compop_func op_d088_0_comp_nf;
+extern compop_func op_d090_0_comp_nf;
+extern compop_func op_d098_0_comp_nf;
+extern compop_func op_d0a0_0_comp_nf;
+extern compop_func op_d0a8_0_comp_nf;
+extern compop_func op_d0b0_0_comp_nf;
+extern compop_func op_d0b8_0_comp_nf;
+extern compop_func op_d0b9_0_comp_nf;
+extern compop_func op_d0ba_0_comp_nf;
+extern compop_func op_d0bb_0_comp_nf;
+extern compop_func op_d0bc_0_comp_nf;
+extern compop_func op_d0c0_0_comp_nf;
+extern compop_func op_d0c8_0_comp_nf;
+extern compop_func op_d0d0_0_comp_nf;
+extern compop_func op_d0d8_0_comp_nf;
+extern compop_func op_d0e0_0_comp_nf;
+extern compop_func op_d0e8_0_comp_nf;
+extern compop_func op_d0f0_0_comp_nf;
+extern compop_func op_d0f8_0_comp_nf;
+extern compop_func op_d0f9_0_comp_nf;
+extern compop_func op_d0fa_0_comp_nf;
+extern compop_func op_d0fb_0_comp_nf;
+extern compop_func op_d0fc_0_comp_nf;
+extern compop_func op_d100_0_comp_nf;
+extern compop_func op_d108_0_comp_nf;
+extern compop_func op_d110_0_comp_nf;
+extern compop_func op_d118_0_comp_nf;
+extern compop_func op_d120_0_comp_nf;
+extern compop_func op_d128_0_comp_nf;
+extern compop_func op_d130_0_comp_nf;
+extern compop_func op_d138_0_comp_nf;
+extern compop_func op_d139_0_comp_nf;
+extern compop_func op_d140_0_comp_nf;
+extern compop_func op_d148_0_comp_nf;
+extern compop_func op_d150_0_comp_nf;
+extern compop_func op_d158_0_comp_nf;
+extern compop_func op_d160_0_comp_nf;
+extern compop_func op_d168_0_comp_nf;
+extern compop_func op_d170_0_comp_nf;
+extern compop_func op_d178_0_comp_nf;
+extern compop_func op_d179_0_comp_nf;
+extern compop_func op_d180_0_comp_nf;
+extern compop_func op_d188_0_comp_nf;
+extern compop_func op_d190_0_comp_nf;
+extern compop_func op_d198_0_comp_nf;
+extern compop_func op_d1a0_0_comp_nf;
+extern compop_func op_d1a8_0_comp_nf;
+extern compop_func op_d1b0_0_comp_nf;
+extern compop_func op_d1b8_0_comp_nf;
+extern compop_func op_d1b9_0_comp_nf;
+extern compop_func op_d1c0_0_comp_nf;
+extern compop_func op_d1c8_0_comp_nf;
+extern compop_func op_d1d0_0_comp_nf;
+extern compop_func op_d1d8_0_comp_nf;
+extern compop_func op_d1e0_0_comp_nf;
+extern compop_func op_d1e8_0_comp_nf;
+extern compop_func op_d1f0_0_comp_nf;
+extern compop_func op_d1f8_0_comp_nf;
+extern compop_func op_d1f9_0_comp_nf;
+extern compop_func op_d1fa_0_comp_nf;
+extern compop_func op_d1fb_0_comp_nf;
+extern compop_func op_d1fc_0_comp_nf;
+extern compop_func op_e000_0_comp_nf;
+extern compop_func op_e008_0_comp_nf;
+extern compop_func op_e018_0_comp_nf;
+extern compop_func op_e020_0_comp_nf;
+extern compop_func op_e028_0_comp_nf;
+extern compop_func op_e038_0_comp_nf;
+extern compop_func op_e040_0_comp_nf;
+extern compop_func op_e048_0_comp_nf;
+extern compop_func op_e058_0_comp_nf;
+extern compop_func op_e060_0_comp_nf;
+extern compop_func op_e068_0_comp_nf;
+extern compop_func op_e078_0_comp_nf;
+extern compop_func op_e080_0_comp_nf;
+extern compop_func op_e088_0_comp_nf;
+extern compop_func op_e098_0_comp_nf;
+extern compop_func op_e0a0_0_comp_nf;
+extern compop_func op_e0a8_0_comp_nf;
+extern compop_func op_e0b8_0_comp_nf;
+extern compop_func op_e100_0_comp_nf;
+extern compop_func op_e108_0_comp_nf;
+extern compop_func op_e118_0_comp_nf;
+extern compop_func op_e120_0_comp_nf;
+extern compop_func op_e128_0_comp_nf;
+extern compop_func op_e138_0_comp_nf;
+extern compop_func op_e140_0_comp_nf;
+extern compop_func op_e148_0_comp_nf;
+extern compop_func op_e158_0_comp_nf;
+extern compop_func op_e160_0_comp_nf;
+extern compop_func op_e168_0_comp_nf;
+extern compop_func op_e178_0_comp_nf;
+extern compop_func op_e180_0_comp_nf;
+extern compop_func op_e188_0_comp_nf;
+extern compop_func op_e198_0_comp_nf;
+extern compop_func op_e1a0_0_comp_nf;
+extern compop_func op_e1a8_0_comp_nf;
+extern compop_func op_e1b8_0_comp_nf;
+extern compop_func op_f200_0_comp_nf;
+extern compop_func op_f208_0_comp_nf;
+extern compop_func op_f210_0_comp_nf;
+extern compop_func op_f218_0_comp_nf;
+extern compop_func op_f220_0_comp_nf;
+extern compop_func op_f228_0_comp_nf;
+extern compop_func op_f230_0_comp_nf;
+extern compop_func op_f238_0_comp_nf;
+extern compop_func op_f239_0_comp_nf;
+extern compop_func op_f23a_0_comp_nf;
+extern compop_func op_f23b_0_comp_nf;
+extern compop_func op_f23c_0_comp_nf;
+extern compop_func op_f240_0_comp_nf;
+extern compop_func op_f250_0_comp_nf;
+extern compop_func op_f258_0_comp_nf;
+extern compop_func op_f260_0_comp_nf;
+extern compop_func op_f268_0_comp_nf;
+extern compop_func op_f270_0_comp_nf;
+extern compop_func op_f278_0_comp_nf;
+extern compop_func op_f279_0_comp_nf;
+extern compop_func op_f280_0_comp_nf;
+extern compop_func op_f2c0_0_comp_nf;
+extern compop_func op_f600_0_comp_nf;
+extern compop_func op_f608_0_comp_nf;
+extern compop_func op_f610_0_comp_nf;
+extern compop_func op_f618_0_comp_nf;
+extern compop_func op_f620_0_comp_nf;
diff --git a/src/cpu/jit/gencomp.c b/src/cpu/jit/gencomp.c
new file mode 100644
index 0000000..6750279
--- /dev/null
+++ b/src/cpu/jit/gencomp.c
@@ -0,0 +1,3263 @@
+/*
+ * UAE - The Un*x Amiga Emulator
+ *
+ * MC68000 compilation generator
+ *
+ * Based on work Copyright 1995, 1996 Bernd Schmidt. Changes Copyright 2000
+ * Bernd Meyer
+ */
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+#include 
+
+#include "readcpu.h"
+
+#include 
+#include 
+
+#define BOOL_TYPE "int"
+#define failure global_failure=1
+#define FAILURE global_failure=1
+#define isjump  global_isjump=1
+#define is_const_jump global_iscjump=1;
+#define isaddx  global_isaddx=1
+#define uses_cmov global_cmov=1
+#define mayfail global_mayfail=1
+
+int hack_opcode;
+
+static int global_failure;
+static int global_isjump;
+static int global_iscjump;
+static int global_isaddx;
+static int global_cmov;
+static int long_opcode;
+static int global_mayfail;
+
+static char endstr[1000];
+static char lines[100000];
+static int comp_index=0;
+
+static int cond_codes_x86[]={-1,-1,7,6,3,2,5,4,-1,-1,9,8,13,12,15,14};
+
+static void comprintf(const char* format, ...)
+{
+    va_list args;
+
+    va_start(args,format);
+    comp_index+=vsprintf(lines+comp_index,format,args);
+}
+
+static void com_discard(void)
+{
+    comp_index=0;
+}
+
+static void com_flush(void)
+{
+    int i;
+    for (i=0;i 0);
+    n_braces--;
+    comprintf ("}");
+}
+
+static void
+finish_braces (void)
+{
+    while (n_braces > 0)
+	close_brace ();
+}
+
+static void
+pop_braces (int to)
+{
+    while (n_braces > to)
+	close_brace ();
+}
+
+static int
+bit_size (int size)
+{
+    switch (size)
+    {
+     case sz_byte:
+	return 8;
+     case sz_word:
+	return 16;
+     case sz_long:
+	return 32;
+     default:
+	abort ();
+    }
+    return 0;
+}
+
+static const char *
+bit_mask (int size)
+{
+    switch (size)
+    {
+     case sz_byte:
+	return "0xff";
+     case sz_word:
+	return "0xffff";
+     case sz_long:
+	return "0xffffffff";
+     default:
+	abort ();
+    }
+    return 0;
+}
+
+static __inline__ void gen_update_next_handler(void)
+{
+    return; /* Can anything clever be done here? */
+}
+
+static void gen_writebyte (char* address, char* source)
+{
+    comprintf("\twritebyte(%s,%s,scratchie);\n",address,source);
+}
+
+static void gen_writeword (char* address, char* source)
+{
+    comprintf("\twriteword(%s,%s,scratchie);\n",address,source);
+}
+
+static void gen_writelong (char* address, char* source)
+{
+    comprintf("\twritelong(%s,%s,scratchie);\n",address,source);
+}
+
+static void gen_readbyte (char* address, char* dest)
+{
+    comprintf("\treadbyte(%s,%s,scratchie);\n",address,dest);
+}
+
+static void gen_readword (char* address, char* dest)
+{
+    comprintf("\treadword(%s,%s,scratchie);\n",address,dest);
+}
+
+static void gen_readlong (char* address, char* dest)
+{
+    comprintf("\treadlong(%s,%s,scratchie);\n",address,dest);
+}
+
+
+
+static const char *
+gen_nextilong (void)
+{
+    static char buffer[80];
+
+    sprintf (buffer, "comp_get_ilong((m68k_pc_offset+=4)-4)");
+    insn_n_cycles += 4;
+
+    long_opcode=1;
+    return buffer;
+}
+
+static const char *
+gen_nextiword (void)
+{
+    static char buffer[80];
+
+    sprintf (buffer, "comp_get_iword((m68k_pc_offset+=2)-2)");
+    insn_n_cycles+=2;
+
+    long_opcode=1;
+    return buffer;
+}
+
+static const char *
+gen_nextibyte (void)
+{
+    static char buffer[80];
+
+    sprintf (buffer, "comp_get_ibyte((m68k_pc_offset+=2)-2)");
+    insn_n_cycles += 2;
+
+    long_opcode=1;
+    return buffer;
+}
+
+static void
+sync_m68k_pc (void)
+{
+    comprintf("\t if (m68k_pc_offset>JIT_M68K_PC_SYNC) sync_m68k_pc();\n");
+}
+
+
+/* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
+ * the calling routine handles Apdi and Aipi modes. */
+static void
+genamode (amodes mode, char *reg, wordsizes size, char *name, int getv, int movem)
+{
+    start_brace ();
+    switch (mode)
+    {
+     case Dreg: /* Do we need to check dodgy here? */
+	if (movem)
+	    abort ();
+	if (getv == 1 || getv==2) {
+	    /* We generate the variable even for getv==2, so we can use
+	       it as a destination for MOVE */
+	    comprintf ("\tint %s=%s;\n",name,reg);
+	}
+	return;
+
+     case Areg:
+	if (movem)
+	    abort ();
+	if (getv == 1 || getv==2) {
+	    /* see above */
+	    comprintf ("\tint %s=dodgy?scratchie++:%s+8;\n",name,reg);
+	    if (getv==1) {
+		comprintf ("\tif (dodgy) \n");
+		comprintf ("\t\tmov_l_rr(%s,%s+8);\n",name, reg);
+	    }
+	}
+	return;
+
+     case Aind:
+	comprintf ("\tint %sa=dodgy?scratchie++:%s+8;\n",name,reg);
+	comprintf ("\tif (dodgy) \n");
+	comprintf ("\t\tmov_l_rr(%sa,%s+8);\n",name, reg);
+	break;
+     case Aipi:
+	comprintf ("\tint %sa=scratchie++;\n",name,reg);
+	comprintf ("\tmov_l_rr(%sa,%s+8);\n",name, reg);
+	break;
+     case Apdi:
+	switch (size)
+	{
+	 case sz_byte:
+	    if (movem) {
+		comprintf ("\tint %sa=dodgy?scratchie++:%s+8;\n",name,reg);
+		comprintf ("\tif (dodgy) \n");
+		comprintf("\tmov_l_rr(%sa,8+%s);\n",name,reg);
+	    }
+	    else {
+		start_brace();
+		comprintf ("\tint %sa=dodgy?scratchie++:%s+8;\n",name,reg);
+		comprintf("\tlea_l_brr(%s+8,%s+8,(uae_s32)-areg_byteinc[%s]);\n",reg,reg,reg);
+		comprintf ("\tif (dodgy) \n");
+		comprintf("\tmov_l_rr(%sa,8+%s);\n",name,reg);
+	    }
+	    break;
+	 case sz_word:
+	    if (movem) {
+		comprintf ("\tint %sa=dodgy?scratchie++:%s+8;\n",name,reg);
+		comprintf ("\tif (dodgy) \n");
+		comprintf("\tmov_l_rr(%sa,8+%s);\n",name,reg);
+	    }
+	    else {
+		start_brace();
+		comprintf ("\tint %sa=dodgy?scratchie++:%s+8;\n",name,reg);
+		comprintf("\tlea_l_brr(%s+8,%s+8,-2);\n",reg,reg);
+		comprintf ("\tif (dodgy) \n");
+		comprintf("\tmov_l_rr(%sa,8+%s);\n",name,reg);
+	    }
+	    break;
+	 case sz_long:
+	    if (movem) {
+		comprintf ("\tint %sa=dodgy?scratchie++:%s+8;\n",name,reg);
+		comprintf ("\tif (dodgy) \n");
+		comprintf("\tmov_l_rr(%sa,8+%s);\n",name,reg);
+	    }
+	    else {
+		start_brace();
+		comprintf ("\tint %sa=dodgy?scratchie++:%s+8;\n",name,reg);
+		comprintf("\tlea_l_brr(%s+8,%s+8,-4);\n",reg,reg);
+		comprintf ("\tif (dodgy) \n");
+		comprintf("\tmov_l_rr(%sa,8+%s);\n",name,reg);
+	    }
+	    break;
+	 default:
+	    abort ();
+	}
+	break;
+     case Ad16:
+	comprintf("\tint %sa=scratchie++;\n",name);
+	comprintf("\tmov_l_rr(%sa,8+%s);\n",name,reg);
+	comprintf("\tlea_l_brr(%sa,%sa,(uae_s32)(uae_s16)%s);\n",name,name,gen_nextiword());
+	break;
+     case Ad8r:
+	comprintf("\tint %sa=scratchie++;\n",name);
+	comprintf("\tcalc_disp_ea_020(%s+8,%s,%sa,scratchie);\n",
+		  reg,gen_nextiword(),name);
+	break;
+
+     case PC16:
+	comprintf("\tint %sa=scratchie++;\n",name);
+	comprintf("\tuae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;\n");
+	comprintf ("\tuae_s32 PC16off = (uae_s32)(uae_s16)%s;\n", gen_nextiword ());
+	comprintf("\tmov_l_ri(%sa,address+PC16off);\n",name);
+	break;
+
+     case PC8r:
+	comprintf("\tint pctmp=scratchie++;\n");
+	comprintf("\tint %sa=scratchie++;\n",name);
+	comprintf("\tuae_u32 address=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;\n");
+	start_brace();
+	comprintf("\tmov_l_ri(pctmp,address);\n");
+
+	comprintf("\tcalc_disp_ea_020(pctmp,%s,%sa,scratchie);\n",
+		  gen_nextiword(),name);
+	break;
+     case absw:
+	comprintf ("\tint %sa = scratchie++;\n",name);
+	comprintf ("\tmov_l_ri(%sa,(uae_s32)(uae_s16)%s);\n", name, gen_nextiword ());
+	break;
+     case absl:
+	comprintf ("\tint %sa = scratchie++;\n",name);
+	comprintf ("\tmov_l_ri(%sa,%s); /* absl */\n", name, gen_nextilong ());
+	break;
+     case imm:
+	if (getv != 1)
+	    abort ();
+	switch (size)
+	{
+	 case sz_byte:
+	    comprintf ("\tint %s = scratchie++;\n",name);
+	    comprintf ("\tmov_l_ri(%s,(uae_s32)(uae_s8)%s);\n", name, gen_nextibyte ());
+	    break;
+	 case sz_word:
+	    comprintf ("\tint %s = scratchie++;\n",name);
+	    comprintf ("\tmov_l_ri(%s,(uae_s32)(uae_s16)%s);\n", name, gen_nextiword ());
+	    break;
+	 case sz_long:
+	    comprintf ("\tint %s = scratchie++;\n",name);
+	    comprintf ("\tmov_l_ri(%s,%s);\n", name, gen_nextilong ());
+	    break;
+	 default:
+	    abort ();
+	}
+	return;
+     case imm0:
+	if (getv != 1)
+	    abort ();
+	comprintf ("\tint %s = scratchie++;\n",name);
+	comprintf ("\tmov_l_ri(%s,(uae_s32)(uae_s8)%s);\n", name, gen_nextibyte ());
+	return;
+     case imm1:
+	if (getv != 1)
+	    abort ();
+	comprintf ("\tint %s = scratchie++;\n",name);
+	comprintf ("\tmov_l_ri(%s,(uae_s32)(uae_s16)%s);\n", name, gen_nextiword ());
+	return;
+     case imm2:
+	if (getv != 1)
+	    abort ();
+	comprintf ("\tint %s = scratchie++;\n",name);
+	comprintf ("\tmov_l_ri(%s,%s);\n", name, gen_nextilong ());
+	return;
+     case immi:
+	if (getv != 1)
+	    abort ();
+	comprintf ("\tint %s = scratchie++;\n",name);
+	comprintf ("\tmov_l_ri(%s,%s);\n", name, reg);
+	return;
+     default:
+	abort ();
+    }
+
+    /* We get here for all non-reg non-immediate addressing modes to
+     * actually fetch the value. */
+    if (getv == 1)
+    {
+	char astring[80];
+	sprintf(astring,"%sa",name);
+	switch (size)
+	{
+	 case sz_byte:
+	    insn_n_cycles += 2;
+	    break;
+	 case sz_word:
+	    insn_n_cycles += 2;
+	    break;
+	 case sz_long:
+	    insn_n_cycles += 4;
+	    break;
+	 default:
+	    abort ();
+	}
+	start_brace ();
+	comprintf("\tint %s=scratchie++;\n",name);
+	switch (size)
+	{
+	 case sz_byte:
+	    gen_readbyte(astring,name);
+	    break;
+	 case sz_word:
+	    gen_readword(astring,name);
+	    break;
+	 case sz_long:
+	    gen_readlong(astring,name);
+	    break;
+	 default:
+	    abort ();
+	}
+    }
+
+    /* We now might have to fix up the register for pre-dec or post-inc
+     * addressing modes. */
+    if (!movem) {
+	switch (mode)
+	{
+	 case Aipi:
+	    switch (size)
+	    {
+	     case sz_byte:
+		comprintf("\tlea_l_brr(%s+8,%s+8,areg_byteinc[%s]);\n",reg,reg,reg);
+		break;
+	     case sz_word:
+		comprintf("\tlea_l_brr(%s+8,%s+8,2);\n",reg,reg,reg);
+		break;
+	     case sz_long:
+		comprintf("\tlea_l_brr(%s+8,%s+8,4);\n",reg,reg);
+		break;
+	     default:
+		abort ();
+	    }
+	    break;
+	 case Apdi:
+	    break;
+	 default:
+	    break;
+	}
+    }
+}
+
+static void
+genastore (char *from, amodes mode, char *reg, wordsizes size, char *to)
+{
+    switch (mode)
+    {
+     case Dreg:
+	switch (size)
+	{
+	 case sz_byte:
+	    comprintf("\tif(%s!=%s)\n",reg,from);
+	    comprintf ("\t\tmov_b_rr(%s,%s);\n", reg, from);
+	    break;
+	 case sz_word:
+	    comprintf("\tif(%s!=%s)\n",reg,from);
+	    comprintf ("\t\tmov_w_rr(%s,%s);\n", reg, from);
+	    break;
+	 case sz_long:
+	    comprintf("\tif(%s!=%s)\n",reg,from);
+	    comprintf ("\t\tmov_l_rr(%s,%s);\n", reg, from);
+	    break;
+	 default:
+	    abort ();
+	}
+	break;
+     case Areg:
+	switch (size)
+	{
+	 case sz_word:
+	    comprintf("\tif(%s+8!=%s)\n",reg,from);
+	    comprintf ("\t\tmov_w_rr(%s+8,%s);\n", reg, from);
+	    break;
+	 case sz_long:
+	    comprintf("\tif(%s+8!=%s)\n",reg,from);
+	    comprintf ("\t\tmov_l_rr(%s+8,%s);\n", reg, from);
+	    break;
+	 default:
+	    abort ();
+	}
+	break;
+
+     case Apdi:
+     case absw:
+     case PC16:
+     case PC8r:
+     case Ad16:
+     case Ad8r:
+     case Aipi:
+     case Aind:
+     case absl:
+     {
+	 char astring[80];
+	 sprintf(astring,"%sa",to);
+
+	 switch (size)
+	 {
+	  case sz_byte:
+	     insn_n_cycles += 2;
+	     gen_writebyte(astring,from);
+	     break;
+	  case sz_word:
+	     insn_n_cycles += 2;
+	     gen_writeword(astring,from);
+	     break;
+	  case sz_long:
+	     insn_n_cycles += 4;
+	     gen_writelong(astring,from);
+	     break;
+	  default:
+	     abort ();
+	 }
+     }
+     break;
+     case imm:
+     case imm0:
+     case imm1:
+     case imm2:
+     case immi:
+	abort ();
+	break;
+     default:
+	abort ();
+    }
+}
+static void genmov16(uae_u32 opcode, struct instr *curi)
+{
+    comprintf("\tint src=scratchie++;\n");
+    comprintf("\tint dst=scratchie++;\n");
+
+    if ((opcode & 0xfff8) == 0xf620) {
+	/* MOVE16 (Ax)+,(Ay)+ */
+	comprintf("\tuae_u16 dstreg=((%s)>>12)&0x07;\n", gen_nextiword());
+	comprintf("\tmov_l_rr(src,8+srcreg);\n");
+	comprintf("\tmov_l_rr(dst,8+dstreg);\n");
+    } else {
+	/* Other variants */
+	genamode (curi->smode, "srcreg", curi->size, "src", 0, 2);
+	genamode (curi->dmode, "dstreg", curi->size, "dst", 0, 2);
+	comprintf("\tmov_l_rr(src,srca);\n");
+	comprintf("\tmov_l_rr(dst,dsta);\n");
+    }
+
+    /* Align on 16-byte boundaries */
+    comprintf("\tand_l_ri(src,~15);\n");
+    comprintf("\tand_l_ri(dst,~15);\n");
+
+
+    if ((opcode & 0xfff8) == 0xf620) {
+	comprintf("\tif (srcreg != dstreg)\n");
+	comprintf("\tadd_l_ri(srcreg+8,16);\n");
+	comprintf("\tadd_l_ri(dstreg+8,16);\n");
+    } else if ((opcode & 0xfff8) == 0xf600)
+	comprintf("\tadd_l_ri(srcreg+8,16);\n");
+    else if ((opcode & 0xfff8) == 0xf608)
+	comprintf("\tadd_l_ri(dstreg+8,16);\n");
+
+    comprintf("\tif (special_mem) {\n");
+    comprintf("\t\tint tmp=scratchie;\n");
+    comprintf("\tscratchie+=4;\n"
+	      "\treadlong(src,tmp,scratchie);\n"
+	      "\twritelong_clobber(dst,tmp,scratchie);\n"
+	      "\tadd_l_ri(src,4);\n"
+	      "\tadd_l_ri(dst,4);\n"
+	      "\treadlong(src,tmp,scratchie);\n"
+	      "\twritelong_clobber(dst,tmp,scratchie);\n"
+	      "\tadd_l_ri(src,4);\n"
+	      "\tadd_l_ri(dst,4);\n"
+	      "\treadlong(src,tmp,scratchie);\n"
+	      "\twritelong_clobber(dst,tmp,scratchie);\n"
+	      "\tadd_l_ri(src,4);\n"
+	      "\tadd_l_ri(dst,4);\n"
+	      "\treadlong(src,tmp,scratchie);\n"
+	      "\twritelong_clobber(dst,tmp,scratchie);\n");
+    comprintf("\t} else {\n");
+    comprintf("\t\tint tmp=scratchie;\n");
+    comprintf("\tscratchie+=4;\n");
+    comprintf("\tget_n_addr(src,src,scratchie);\n"
+	      "\tget_n_addr(dst,dst,scratchie);\n"
+	      "\tmov_l_rR(tmp+0,src,0);\n"
+	      "\tmov_l_rR(tmp+1,src,4);\n"
+	      "\tmov_l_rR(tmp+2,src,8);\n"
+	      "\tmov_l_rR(tmp+3,src,12);\n"
+	      "\tmov_l_Rr(dst,tmp+0,0);\n"
+	      "\tforget_about(tmp+0);\n"
+	      "\tmov_l_Rr(dst,tmp+1,4);\n"
+	      "\tforget_about(tmp+1);\n"
+	      "\tmov_l_Rr(dst,tmp+2,8);\n"
+	      "\tforget_about(tmp+2);\n"
+	      "\tmov_l_Rr(dst,tmp+3,12);\t}\n");
+
+}
+
+#if 0
+static void genmov16(void)
+{
+    comprintf("\tint src=scratchie++;\n"
+	      "\tuae_u16 dstreg=((%s)>>12)&0x07;\n",gen_nextiword());
+    comprintf("\tint dst=scratchie++;\n"
+	      "\tint tmp=scratchie;\n"
+	      "\tscratchie+=4;\n"
+	      "\tmov_l_rr(src,8+srcreg);\n"
+	      "\tand_l_ri(src,~15);\n"
+	      "\tmov_l_rr(dst,8+dstreg);\n"
+	      "\tand_l_ri(dst,~15);\n"
+	      "\tadd_l_ri(srcreg+8,16);\n"
+	      "\tadd_l_ri(dstreg+8,16);\n");
+
+    comprintf("\tif (special_mem) {\n"
+	      "\treadlong(src,tmp,scratchie);\n"
+	      "\twritelong_clobber(dst,tmp,scratchie);\n"
+	      "\tadd_l_ri(src,4);\n"
+	      "\tadd_l_ri(dst,4);\n"
+	      "\treadlong(src,tmp,scratchie);\n"
+	      "\twritelong_clobber(dst,tmp,scratchie);\n"
+	      "\tadd_l_ri(src,4);\n"
+	      "\tadd_l_ri(dst,4);\n"
+	      "\treadlong(src,tmp,scratchie);\n"
+	      "\twritelong_clobber(dst,tmp,scratchie);\n"
+	      "\tadd_l_ri(src,4);\n"
+	      "\tadd_l_ri(dst,4);\n"
+	      "\treadlong(src,tmp,scratchie);\n"
+	      "\twritelong_clobber(dst,tmp,scratchie);\n");
+    comprintf("\t} else {\n");
+    comprintf("\tget_n_addr(src,src,scratchie);\n"
+	      "\tget_n_addr(dst,dst,scratchie);\n"
+	      "\tmov_l_rR(tmp+0,src,0);\n"
+	      "\tmov_l_rR(tmp+1,src,4);\n"
+	      "\tmov_l_rR(tmp+2,src,8);\n"
+	      "\tmov_l_rR(tmp+3,src,12);\n"
+	      "\tmov_l_Rr(dst,tmp+0,0);\n"
+	      "\tforget_about(tmp+0);\n"
+	      "\tmov_l_Rr(dst,tmp+1,4);\n"
+	      "\tforget_about(tmp+1);\n"
+	      "\tmov_l_Rr(dst,tmp+2,8);\n"
+	      "\tforget_about(tmp+2);\n"
+	      "\tmov_l_Rr(dst,tmp+3,12);\n"
+	      "\t}\n");
+}
+#endif
+
+static void
+genmovemel (uae_u16 opcode)
+{
+    comprintf ("\tuae_u16 mask = %s;\n", gen_nextiword ());
+    comprintf ("\tint native=scratchie++;\n");
+    comprintf ("\tint i;\n");
+    comprintf ("\tint offset=0;\n");
+    genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
+	if (table68k[opcode].size == sz_long)
+	    comprintf("\tif (1 && !special_mem) {\n");
+	else
+	    comprintf("\tif (1 && !special_mem) {\n");
+
+    /* Fast but unsafe...  */
+    comprintf("\t\tget_n_addr(srca,native,scratchie);\n");
+
+
+    comprintf("\t\tfor (i=0;i<16;i++) {\n"
+	      "\t\t\tif ((mask>>i)&1) {\n");
+    switch(table68k[opcode].size) {
+     case sz_long:
+	comprintf("\t\t\t\tmov_l_rR(i,native,offset);\n"
+		  "\t\t\t\tgen_bswap_32(i);\n"
+		  "\t\t\t\toffset+=4;\n");
+	break;
+     case sz_word:
+	comprintf("\t\t\t\tmov_w_rR(i,native,offset);\n"
+		  "\t\t\t\tgen_bswap_16(i);\n"
+		  "\t\t\t\tsign_extend_16_rr(i,i);\n"
+		  "\t\t\t\toffset+=2;\n");
+	break;
+     default: abort();
+    }
+    comprintf("\t\t\t}\n"
+	      "\t\t}\n");
+    if (table68k[opcode].dmode == Aipi) {
+	comprintf("\t\tlea_l_brr(8+dstreg,srca,offset);\n");
+    }
+    /* End fast but unsafe.   */
+
+    comprintf("\t} else {\n");
+
+    comprintf ("\t\tint tmp=scratchie++;\n");
+
+    comprintf("\t\tmov_l_rr(tmp,srca);\n");
+    comprintf("\t\tfor (i=0;i<16;i++) {\n"
+	      "\t\t\tif ((mask>>i)&1) {\n");
+    switch(table68k[opcode].size) {
+    case sz_long:
+	comprintf("\t\t\t\treadlong(tmp,i,scratchie);\n"
+		  "\t\t\t\tadd_l_ri(tmp,4);\n");
+	break;
+    case sz_word:
+	comprintf("\t\t\t\treadword(tmp,i,scratchie);\n"
+		  "\t\t\t\tadd_l_ri(tmp,2);\n");
+	break;
+    default: abort();
+    }
+
+    comprintf("\t\t\t}\n"
+	      "\t\t}\n");
+    if (table68k[opcode].dmode == Aipi) {
+	comprintf("\t\tmov_l_rr(8+dstreg,tmp);\n");
+    }
+    comprintf("\t}\n");
+
+}
+
+
+static void
+genmovemle (uae_u16 opcode)
+{
+    comprintf ("\tuae_u16 mask = %s;\n", gen_nextiword ());
+    comprintf ("\tint native=scratchie++;\n");
+    comprintf ("\tint i;\n");
+    comprintf ("\tint tmp=scratchie++;\n");
+    comprintf ("\tsigned char offset=0;\n");
+    genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1);
+
+    /* *Sigh* Some clever geek realized that the fastest way to copy a
+       buffer from main memory to the gfx card is by using movmle. Good
+       on her, but unfortunately, gfx mem isn't "real" mem, and thus that
+       act of cleverness means that movmle must pay attention to special_mem,
+       or Genetic Species is a rather boring-looking game ;-) */
+	if (table68k[opcode].size == sz_long)
+	    comprintf("\tif (1 && !special_mem) {\n");
+	else
+	    comprintf("\tif (1 && !special_mem) {\n");
+    comprintf("\tget_n_addr(srca,native,scratchie);\n");
+
+    if (table68k[opcode].dmode!=Apdi) {
+	comprintf("\tfor (i=0;i<16;i++) {\n"
+		  "\t\tif ((mask>>i)&1) {\n");
+	switch(table68k[opcode].size) {
+	 case sz_long:
+	    comprintf("\t\t\tmov_l_rr(tmp,i);\n"
+		      "\t\t\tgen_bswap_32(tmp);\n"
+		      "\t\t\tmov_l_Rr(native,tmp,offset);\n"
+		      "\t\t\toffset+=4;\n");
+	    break;
+	 case sz_word:
+	    comprintf("\t\t\tmov_l_rr(tmp,i);\n"
+		      "\t\t\tgen_bswap_16(tmp);\n"
+		      "\t\t\tmov_w_Rr(native,tmp,offset);\n"
+		      "\t\t\toffset+=2;\n");
+	    break;
+	 default: abort();
+	}
+    } else {  /* Pre-decrement */
+	comprintf("\tfor (i=0;i<16;i++) {\n"
+		  "\t\tif ((mask>>i)&1) {\n");
+	switch(table68k[opcode].size) {
+	 case sz_long:
+	    comprintf("\t\t\toffset-=4;\n"
+		      "\t\t\tmov_l_rr(tmp,15-i);\n"
+		      "\t\t\tgen_bswap_32(tmp);\n"
+		      "\t\t\tmov_l_Rr(native,tmp,offset);\n"
+		      );
+	    break;
+	 case sz_word:
+	    comprintf("\t\t\toffset-=2;\n"
+		      "\t\t\tmov_l_rr(tmp,15-i);\n"
+		      "\t\t\tgen_bswap_16(tmp);\n"
+		      "\t\t\tmov_w_Rr(native,tmp,offset);\n"
+		      );
+	    break;
+	 default: abort();
+	}
+    }
+
+    comprintf("\t\t}\n"
+	      "\t}");
+    if (table68k[opcode].dmode == Apdi) {
+	comprintf("\t\t\tlea_l_brr(8+dstreg,srca,(uae_s32)offset);\n");
+    }
+    comprintf("\t} else {\n");
+
+    if (table68k[opcode].dmode!=Apdi) {
+	comprintf("\tmov_l_rr(tmp,srca);\n");
+	comprintf("\tfor (i=0;i<16;i++) {\n"
+		  "\t\tif ((mask>>i)&1) {\n");
+	switch(table68k[opcode].size) {
+	 case sz_long:
+	    comprintf("\t\t\twritelong(tmp,i,scratchie);\n"
+		      "\t\t\tadd_l_ri(tmp,4);\n");
+	    break;
+	 case sz_word:
+	    comprintf("\t\t\twriteword(tmp,i,scratchie);\n"
+		      "\t\t\tadd_l_ri(tmp,2);\n");
+	    break;
+	 default: abort();
+	}
+    }
+    else {  /* Pre-decrement */
+	comprintf("\tfor (i=0;i<16;i++) {\n"
+		  "\t\tif ((mask>>i)&1) {\n");
+	switch(table68k[opcode].size) {
+	 case sz_long:
+	    comprintf("\t\t\tsub_l_ri(srca,4);\n"
+		      "\t\t\twritelong(srca,15-i,scratchie);\n");
+	    break;
+	 case sz_word:
+	    comprintf("\t\t\tsub_l_ri(srca,2);\n"
+		      "\t\t\twriteword(srca,15-i,scratchie);\n");
+	    break;
+	 default: abort();
+	}
+    }
+
+
+    comprintf("\t\t}\n"
+	      "\t}");
+    if (table68k[opcode].dmode == Apdi) {
+	comprintf("\t\t\tmov_l_rr(8+dstreg,srca);\n");
+    }
+    comprintf("\t}\n");
+}
+
+
+static void
+duplicate_carry (void)
+{
+    comprintf ("\tif (needed_flags&FLAG_X) duplicate_carry();\n");
+}
+
+typedef enum
+{
+    flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp,
+    flag_addx, flag_subx, flag_zn, flag_av, flag_sv, flag_and, flag_or,
+    flag_eor, flag_mov
+}
+flagtypes;
+
+
+static void
+genflags (flagtypes type, wordsizes size, char *value, char *src, char *dst)
+{
+    if (noflags) {
+	switch(type) {
+	 case flag_cmp:
+	    comprintf("\tdont_care_flags();\n");
+	    comprintf("/* Weird --- CMP with noflags ;-) */\n");
+	    return;
+	 case flag_add:
+	 case flag_sub:
+	    comprintf("\tdont_care_flags();\n");
+	    {
+		char* op;
+		switch(type) {
+		 case flag_add: op="add"; break;
+		 case flag_sub: op="sub"; break;
+		 default: abort();
+		}
+		switch (size)
+		{
+		 case sz_byte:
+		    comprintf("\t%s_b(%s,%s);\n",op,dst,src);
+		    break;
+		 case sz_word:
+		    comprintf("\t%s_w(%s,%s);\n",op,dst,src);
+		    break;
+		 case sz_long:
+		    comprintf("\t%s_l(%s,%s);\n",op,dst,src);
+		    break;
+		}
+		return;
+	    }
+	    break;
+
+	 case flag_and:
+	    comprintf("\tdont_care_flags();\n");
+	    switch (size)
+	    {
+	     case sz_byte:
+		comprintf("if (kill_rodent(dst)) {\n");
+		comprintf("\tzero_extend_8_rr(scratchie,%s);\n",src);
+		comprintf("\tor_l_ri(scratchie,0xffffff00);\n");
+		comprintf("\tand_l(%s,scratchie);\n",dst);
+		comprintf("\tforget_about(scratchie);\n");
+		comprintf("\t} else \n"
+			  "\tand_b(%s,%s);\n",dst,src);
+		break;
+	     case sz_word:
+		comprintf("if (kill_rodent(dst)) {\n");
+		comprintf("\tzero_extend_16_rr(scratchie,%s);\n",src);
+		comprintf("\tor_l_ri(scratchie,0xffff0000);\n");
+		comprintf("\tand_l(%s,scratchie);\n",dst);
+		comprintf("\tforget_about(scratchie);\n");
+		comprintf("\t} else \n"
+			  "\tand_w(%s,%s);\n",dst,src);
+		break;
+	     case sz_long:
+		comprintf("\tand_l(%s,%s);\n",dst,src);
+		break;
+	    }
+	    return;
+
+	 case flag_mov:
+	    comprintf("\tdont_care_flags();\n");
+	    switch (size)
+	    {
+	     case sz_byte:
+		comprintf("if (kill_rodent(dst)) {\n");
+		comprintf("\tzero_extend_8_rr(scratchie,%s);\n",src);
+		comprintf("\tand_l_ri(%s,0xffffff00);\n",dst);
+		comprintf("\tor_l(%s,scratchie);\n",dst);
+		comprintf("\tforget_about(scratchie);\n");
+		comprintf("\t} else \n"
+			  "\tmov_b_rr(%s,%s);\n",dst,src);
+		break;
+	     case sz_word:
+		comprintf("if (kill_rodent(dst)) {\n");
+		comprintf("\tzero_extend_16_rr(scratchie,%s);\n",src);
+		comprintf("\tand_l_ri(%s,0xffff0000);\n",dst);
+		comprintf("\tor_l(%s,scratchie);\n",dst);
+		comprintf("\tforget_about(scratchie);\n");
+		comprintf("\t} else \n"
+			  "\tmov_w_rr(%s,%s);\n",dst,src);
+		break;
+	     case sz_long:
+		comprintf("\tmov_l_rr(%s,%s);\n",dst,src);
+		break;
+	    }
+	    return;
+
+	 case flag_or:
+	 case flag_eor:
+	    comprintf("\tdont_care_flags();\n");
+	    start_brace();
+	    {
+		char* op;
+		switch(type) {
+		 case flag_or:  op="or"; break;
+		 case flag_eor: op="xor"; break;
+		 default: abort();
+		}
+		switch (size)
+		{
+		 case sz_byte:
+		    comprintf("if (kill_rodent(dst)) {\n");
+		    comprintf("\tzero_extend_8_rr(scratchie,%s);\n",src);
+		    comprintf("\t%s_l(%s,scratchie);\n",op,dst);
+		    comprintf("\tforget_about(scratchie);\n");
+		    comprintf("\t} else \n"
+			      "\t%s_b(%s,%s);\n",op,dst,src);
+		    break;
+		 case sz_word:
+		    comprintf("if (kill_rodent(dst)) {\n");
+		    comprintf("\tzero_extend_16_rr(scratchie,%s);\n",src);
+		    comprintf("\t%s_l(%s,scratchie);\n",op,dst);
+		    comprintf("\tforget_about(scratchie);\n");
+		    comprintf("\t} else \n"
+			      "\t%s_w(%s,%s);\n",op,dst,src);
+		    break;
+		 case sz_long:
+		    comprintf("\t%s_l(%s,%s);\n",op,dst,src);
+		    break;
+		}
+		close_brace();
+		return;
+	    }
+
+
+	 case flag_addx:
+	 case flag_subx:
+
+	    comprintf("\tdont_care_flags();\n");
+	    {
+		char* op;
+		switch(type) {
+		 case flag_addx: op="adc"; break;
+		 case flag_subx: op="sbb"; break;
+		 default: abort();
+		}
+		comprintf("\trestore_carry();\n"); /* Reload the X flag into C */
+		switch (size)
+		{
+		 case sz_byte:
+		    comprintf("\t%s_b(%s,%s);\n",op,dst,src);
+		    break;
+		 case sz_word:
+		    comprintf("\t%s_w(%s,%s);\n",op,dst,src);
+		    break;
+		 case sz_long:
+		    comprintf("\t%s_l(%s,%s);\n",op,dst,src);
+		    break;
+		}
+		return;
+	    }
+	    break;
+	 default: return;
+	}
+    }
+
+    /* Need the flags, but possibly not all of them */
+    switch (type)
+    {
+     case flag_logical_noclobber:
+	failure;
+
+     case flag_and:
+     case flag_or:
+     case flag_eor:
+	comprintf("\tdont_care_flags();\n");
+	start_brace();
+	{
+	    char* op;
+	    switch(type) {
+	     case flag_and: op="and"; break;
+	     case flag_or:  op="or"; break;
+	     case flag_eor: op="xor"; break;
+	     default: abort();
+	    }
+	    switch (size)
+	    {
+	     case sz_byte:
+		comprintf("\tstart_needflags();\n"
+			  "\t%s_b(%s,%s);\n",op,dst,src);
+		break;
+	     case sz_word:
+		comprintf("\tstart_needflags();\n"
+			  "\t%s_w(%s,%s);\n",op,dst,src);
+		break;
+	     case sz_long:
+		comprintf("\tstart_needflags();\n"
+			  "\t%s_l(%s,%s);\n",op,dst,src);
+		break;
+	    }
+	    comprintf("\tlive_flags();\n");
+	    comprintf("\tend_needflags();\n");
+	    close_brace();
+	    return;
+	}
+
+     case flag_mov:
+	comprintf("\tdont_care_flags();\n");
+	start_brace();
+	{
+	    switch (size)
+	    {
+	     case sz_byte:
+		comprintf("\tif (%s!=%s) {\n",src,dst);
+		comprintf("\tmov_b_ri(%s,0);\n"
+			  "\tstart_needflags();\n",dst);
+		comprintf("\tor_b(%s,%s);\n",dst,src);
+		comprintf("\t} else {\n");
+		comprintf("\tmov_b_rr(%s,%s);\n",dst,src);
+		comprintf("\ttest_b_rr(%s,%s);\n",dst,dst);
+		comprintf("\t}\n");
+		break;
+	     case sz_word:
+		comprintf("\tif (%s!=%s) {\n",src,dst);
+		comprintf("\tmov_w_ri(%s,0);\n"
+			  "\tstart_needflags();\n",dst);
+		comprintf("\tor_w(%s,%s);\n",dst,src);
+		comprintf("\t} else {\n");
+		comprintf("\tmov_w_rr(%s,%s);\n",dst,src);
+		comprintf("\ttest_w_rr(%s,%s);\n",dst,dst);
+		comprintf("\t}\n");
+		break;
+	     case sz_long:
+		comprintf("\tif (%s!=%s) {\n",src,dst);
+		comprintf("\tmov_l_ri(%s,0);\n"
+			  "\tstart_needflags();\n",dst);
+		comprintf("\tor_l(%s,%s);\n",dst,src);
+		comprintf("\t} else {\n");
+		comprintf("\tmov_l_rr(%s,%s);\n",dst,src);
+		comprintf("\ttest_l_rr(%s,%s);\n",dst,dst);
+		comprintf("\t}\n");
+		break;
+	    }
+	    comprintf("\tlive_flags();\n");
+	    comprintf("\tend_needflags();\n");
+	    close_brace();
+	    return;
+	}
+
+     case flag_logical:
+	comprintf("\tdont_care_flags();\n");
+	start_brace();
+	switch (size)
+	{
+	 case sz_byte:
+	    comprintf("\tstart_needflags();\n"
+		      "\ttest_b_rr(%s,%s);\n",value,value);
+	    break;
+	 case sz_word:
+	    comprintf("\tstart_needflags();\n"
+		      "\ttest_w_rr(%s,%s);\n",value,value);
+	    break;
+	 case sz_long:
+	    comprintf("\tstart_needflags();\n"
+		      "\ttest_l_rr(%s,%s);\n",value,value);
+	    break;
+	}
+	comprintf("\tlive_flags();\n");
+	comprintf("\tend_needflags();\n");
+	close_brace();
+	return;
+
+
+     case flag_add:
+     case flag_sub:
+     case flag_cmp:
+	comprintf("\tdont_care_flags();\n");
+	{
+	    char* op;
+	    switch(type) {
+	     case flag_add: op="add"; break;
+	     case flag_sub: op="sub"; break;
+	     case flag_cmp: op="cmp"; break;
+	     default: abort();
+	    }
+	    switch (size)
+	    {
+	     case sz_byte:
+		comprintf("\tstart_needflags();\n"
+			  "\t%s_b(%s,%s);\n",op,dst,src);
+		break;
+	     case sz_word:
+		comprintf("\tstart_needflags();\n"
+			  "\t%s_w(%s,%s);\n",op,dst,src);
+		break;
+	     case sz_long:
+		comprintf("\tstart_needflags();\n"
+			  "\t%s_l(%s,%s);\n",op,dst,src);
+		break;
+	    }
+	    comprintf("\tlive_flags();\n");
+	    comprintf("\tend_needflags();\n");
+	    if (type!=flag_cmp) {
+		duplicate_carry();
+	    }
+	    comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+
+	    return;
+	}
+
+     case flag_addx:
+     case flag_subx:
+		 uses_cmov;
+	comprintf("\tdont_care_flags();\n");
+	{
+	    char* op;
+	    switch(type) {
+	     case flag_addx: op="adc"; break;
+	     case flag_subx: op="sbb"; break;
+	     default: abort();
+	    }
+	    start_brace();
+	    comprintf("\tint zero=scratchie++;\n"
+		      "\tint one=scratchie++;\n"
+		      "\tif (needed_flags&FLAG_Z) {\n"
+		      "\tmov_l_ri(zero,0);\n"
+		      "\tmov_l_ri(one,1);\n"
+		      "\tmake_flags_live();\n"
+		      "\tcmov_l_rr(zero,one,5);\n"
+		      "\t}\n");
+	    comprintf("\trestore_carry();\n"); /* Reload the X flag into C */
+	    switch (size)
+	    {
+	     case sz_byte:
+		comprintf("\tstart_needflags();\n"
+			  "\t%s_b(%s,%s);\n",op,dst,src);
+		break;
+	     case sz_word:
+		comprintf("\tstart_needflags();\n"
+			  "\t%s_w(%s,%s);\n",op,dst,src);
+		break;
+	     case sz_long:
+		comprintf("\tstart_needflags();\n"
+			  "\t%s_l(%s,%s);\n",op,dst,src);
+		break;
+	    }
+	    comprintf("\tlive_flags();\n");
+	    comprintf("\tif (needed_flags&FLAG_Z) {\n"
+		      "\tcmov_l_rr(zero,one,5);\n"
+		      "\tsetzflg_l(zero);\n"
+		      "\tlive_flags();\n"
+		      "\t}\n");
+	    comprintf("\tend_needflags();\n");
+	    duplicate_carry();
+	    comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	    return;
+	}
+     default:
+	failure;
+	break;
+    }
+}
+
+static void
+force_range_for_rox (const char *var, wordsizes size)
+{
+    /* Could do a modulo operation here... which one is faster? */
+    switch (size)
+    {
+     case sz_long:
+	comprintf ("\tif (%s >= 33) %s -= 33;\n", var, var);
+	break;
+     case sz_word:
+	comprintf ("\tif (%s >= 34) %s -= 34;\n", var, var);
+	comprintf ("\tif (%s >= 17) %s -= 17;\n", var, var);
+	break;
+     case sz_byte:
+	comprintf ("\tif (%s >= 36) %s -= 36;\n", var, var);
+	comprintf ("\tif (%s >= 18) %s -= 18;\n", var, var);
+	comprintf ("\tif (%s >= 9) %s -= 9;\n", var, var);
+	break;
+    }
+}
+
+static const char *
+cmask (wordsizes size)
+{
+    switch (size)
+    {
+     case sz_byte:
+	return "0x80";
+     case sz_word:
+	return "0x8000";
+     case sz_long:
+	return "0x80000000";
+     default:
+	abort ();
+    }
+}
+
+static int
+source_is_imm1_8 (struct instr *i)
+{
+    return i->stype == 3;
+}
+
+static int  /* returns zero for success, non-zero for failure */
+gen_opcode (unsigned long int opcode)
+{
+    struct instr *curi = table68k + opcode;
+    char* ssize=NULL;
+
+    insn_n_cycles = 2;
+    global_failure=0;
+    long_opcode=0;
+    global_isjump=0;
+    global_iscjump=0;
+    global_isaddx=0;
+    global_cmov=0;
+    global_mayfail=0;
+    hack_opcode=opcode;
+    endstr[0]=0;
+
+    start_brace ();
+    comprintf("\tuae_u8 scratchie=S1;\n");
+    switch (curi->plev)
+    {
+     case 0:			/* not privileged */
+	break;
+     case 1:			/* unprivileged only on 68000 */
+	if (cpu_level == 0)
+	    break;
+	if (next_cpu_level < 0)
+	    next_cpu_level = 0;
+
+	/* fall through */
+     case 2:			/* priviledged */
+	failure;   /* Easy ones first */
+	break;
+     case 3:			/* privileged if size == word */
+	if (curi->size == sz_byte)
+	    break;
+	failure;
+	break;
+    }
+    switch (curi->size) {
+     case sz_byte: ssize="b"; break;
+     case sz_word: ssize="w"; break;
+     case sz_long: ssize="l"; break;
+     default: abort();
+    }
+
+    switch (curi->mnemo)
+    {
+     case i_OR:
+     case i_AND:
+     case i_EOR:
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	switch(curi->mnemo) {
+	 case i_OR: genflags (flag_or, curi->size, "", "src", "dst"); break;
+	 case i_AND: genflags (flag_and, curi->size, "", "src", "dst"); break;
+	 case i_EOR: genflags (flag_eor, curi->size, "", "src", "dst"); break;
+	}
+	genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
+	break;
+
+     case i_ORSR:
+     case i_EORSR:
+	failure;
+	isjump;
+	break;
+     case i_ANDSR:
+	failure;
+	isjump;
+	break;
+     case i_SUB:
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	genflags (flag_sub, curi->size, "", "src", "dst");
+	genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
+	break;
+     case i_SUBA:
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint tmp=scratchie++;\n");
+	switch(curi->size) {
+	 case sz_byte: comprintf("\tsign_extend_8_rr(tmp,src);\n"); break;
+	 case sz_word: comprintf("\tsign_extend_16_rr(tmp,src);\n"); break;
+	 case sz_long: comprintf("\ttmp=src;\n"); break;
+	 default: abort();
+	}
+	comprintf("\tsub_l(dst,tmp);\n");
+	genastore ("dst", curi->dmode, "dstreg", sz_long, "dst");
+	break;
+     case i_SUBX:
+	isaddx;
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	genflags (flag_subx, curi->size, "", "src", "dst");
+	genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
+	break;
+     case i_SBCD:
+	failure;
+	/* I don't think so! */
+	break;
+     case i_ADD:
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	genflags (flag_add, curi->size, "", "src", "dst");
+	genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
+	break;
+     case i_ADDA:
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint tmp=scratchie++;\n");
+	switch(curi->size) {
+	 case sz_byte: comprintf("\tsign_extend_8_rr(tmp,src);\n"); break;
+	 case sz_word: comprintf("\tsign_extend_16_rr(tmp,src);\n"); break;
+	 case sz_long: comprintf("\ttmp=src;\n"); break;
+	 default: abort();
+	}
+	comprintf("\tadd_l(dst,tmp);\n");
+	genastore ("dst", curi->dmode, "dstreg", sz_long, "dst");
+	break;
+     case i_ADDX:
+	isaddx;
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+	genflags (flag_addx, curi->size, "", "src", "dst");
+	genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
+	break;
+     case i_ABCD:
+	failure;
+	/* No BCD maths for me.... */
+	break;
+     case i_NEG:
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace ();
+	comprintf("\tint dst=scratchie++;\n");
+	comprintf("\tmov_l_ri(dst,0);\n");
+	genflags (flag_sub, curi->size, "", "src", "dst");
+	genastore ("dst", curi->smode, "srcreg", curi->size, "src");
+	break;
+     case i_NEGX:
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace ();
+	comprintf("\tint dst=scratchie++;\n");
+	comprintf("\tmov_l_ri(dst,0);\n");
+	genflags (flag_subx, curi->size, "", "src", "dst");
+	genastore ("dst", curi->smode, "srcreg", curi->size, "src");
+	break;
+
+     case i_NBCD:
+	failure;
+	/* Nope! */
+	break;
+     case i_CLR:
+	genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
+	start_brace();
+	comprintf("\tint dst=scratchie++;\n");
+	comprintf("\tmov_l_ri(dst,0);\n");
+	genflags (flag_logical, curi->size, "dst", "", "");
+	genastore ("dst", curi->smode, "srcreg", curi->size, "src");
+	break;
+     case i_NOT:
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	start_brace ();
+	comprintf("\tint dst=scratchie++;\n");
+	comprintf("\tmov_l_ri(dst,0xffffffff);\n");
+	genflags (flag_eor, curi->size, "", "src", "dst");
+	genastore ("dst", curi->smode, "srcreg", curi->size, "src");
+	break;
+     case i_TST:
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genflags (flag_logical, curi->size, "src", "", "");
+	break;
+     case i_BCHG:
+     case i_BCLR:
+     case i_BSET:
+     case i_BTST:
+			genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint s=scratchie++;\n"
+		  "\tmov_l_rr(s,src);\n");
+	if (curi->size == sz_byte)
+	    comprintf("\tand_l_ri(s,7);\n");
+	else
+	    comprintf("\tand_l_ri(s,31);\n");
+
+	{
+	    char* op;
+	    int need_write=1;
+
+	    switch(curi->mnemo) {
+	     case i_BCHG: op="btc"; break;
+	     case i_BCLR: op="btr"; break;
+	     case i_BSET: op="bts"; break;
+	     case i_BTST: op="bt"; need_write=0; break;
+	    }
+	    comprintf("\t%s_l_rr(dst,s);\n"  /* Answer now in C */
+				  "\tsbb_l(s,s);\n" /* s is 0 if bit was 0, -1 otherwise */
+				  "\tmake_flags_live();\n" /* Get the flags back */
+				  "\tdont_care_flags();\n",op);
+		if (!noflags) {
+		  comprintf("\tstart_needflags();\n"
+					"\tsetzflg_l(s);\n"
+					"\tlive_flags();\n"
+					"\tend_needflags();\n");
+		}
+	    if (need_write)
+		genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
+	}
+	break;
+	/*if (!noflags) {
+	    failure;
+	    break;
+	}
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint s=scratchie++;\n"
+		  "\tmov_l_rr(s,src);\n");
+	if (curi->size == sz_byte)
+	    comprintf("\tand_l_ri(s,7);\n");
+	else
+	    comprintf("\tand_l_ri(s,31);\n");
+
+	{
+	    char* op;
+	    int need_write=1;
+
+	    switch(curi->mnemo) {
+	     case i_BCHG: op="btc"; break;
+	     case i_BCLR: op="btr"; break;
+	     case i_BSET: op="bts"; break;
+	     case i_BTST: op="bt"; need_write=0; break;
+	    }
+	    comprintf("\t%s_l_rr(dst,s);\n"  // Answer now in C
+		      "\tsbb_l(s,s);\n" // s is 0 if bit was 0,  -1 otherwise
+		      "\tmake_flags_live();\n" // Get the flags back
+		      "\tdont_care_flags();\n"
+		      "\tstart_needflags();\n"
+		      "\tbsf_l_rr(s,s);\n"
+		      "\tlive_flags();\n"
+		      "\tend_needflags();\n",op);
+	    if (need_write)
+		genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
+	}
+	break;
+*/
+     case i_CMPM:
+     case i_CMP:
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace ();
+	genflags (flag_cmp, curi->size, "", "src", "dst");
+	break;
+     case i_CMPA:
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint tmps=scratchie++;\n");
+	switch(curi->size) {
+	 case sz_byte: comprintf("\tsign_extend_8_rr(tmps,src);\n"); break;
+	 case sz_word: comprintf("\tsign_extend_16_rr(tmps,src);\n"); break;
+	 case sz_long: comprintf("tmps=src;\n"); break;
+	 default: abort();
+	}
+	genflags (flag_cmp, sz_long, "", "tmps", "dst");
+	break;
+	/* The next two are coded a little unconventional, but they are doing
+	 * weird things... */
+     case i_MVPRM:
+	isjump;
+	failure;
+	break;
+     case i_MVPMR:
+	isjump;
+	failure;
+	break;
+     case i_MOVE:
+	switch(curi->dmode) {
+	 case Dreg:
+	 case Areg:
+	    genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	    genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
+	    genflags (flag_mov, curi->size, "", "src", "dst");
+	    genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
+	    break;
+	 default: /* It goes to memory, not a register */
+	    genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	    genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
+	    genflags (flag_logical, curi->size, "src", "", "");
+	    genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
+	    break;
+	}
+	break;
+     case i_MOVEA:
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
+
+	start_brace();
+	comprintf("\tint tmps=scratchie++;\n");
+	switch(curi->size) {
+	 case sz_word: comprintf("\tsign_extend_16_rr(dst,src);\n"); break;
+	 case sz_long: comprintf("\tmov_l_rr(dst,src);\n"); break;
+	 default: abort();
+	}
+	genastore ("dst", curi->dmode, "dstreg", sz_long, "dst");
+	break;
+
+     case i_MVSR2:
+	isjump;
+	failure;
+	break;
+     case i_MV2SR:
+	isjump;
+	failure;
+	break;
+     case i_SWAP:
+	genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
+	comprintf("\tdont_care_flags();\n");
+	comprintf("\trol_l_ri(src,16);\n");
+	genflags (flag_logical, sz_long, "src", "", "");
+	genastore ("src", curi->smode, "srcreg", sz_long, "src");
+	break;
+     case i_EXG:
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	start_brace();
+	comprintf("\tint tmp=scratchie++;\n"
+		  "\tmov_l_rr(tmp,src);\n");
+	genastore ("dst", curi->smode, "srcreg", curi->size, "src");
+	genastore ("tmp", curi->dmode, "dstreg", curi->size, "dst");
+	break;
+     case i_EXT:
+	genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
+	comprintf("\tdont_care_flags();\n");
+	start_brace ();
+	switch (curi->size)
+	{
+	 case sz_byte:
+	    comprintf ("\tint dst = src;\n"
+		       "\tsign_extend_8_rr(src,src);\n");
+	    break;
+	 case sz_word:
+	    comprintf ("\tint dst = scratchie++;\n"
+		       "\tsign_extend_8_rr(dst,src);\n");
+	    break;
+	 case sz_long:
+	    comprintf ("\tint dst = src;\n"
+		       "\tsign_extend_16_rr(src,src);\n");
+	    break;
+	 default:
+	    abort ();
+	}
+	genflags (flag_logical,
+		  curi->size == sz_word ? sz_word : sz_long, "dst", "", "");
+	genastore ("dst", curi->smode, "srcreg",
+		   curi->size == sz_word ? sz_word : sz_long, "src");
+	break;
+     case i_MVMEL:
+	genmovemel (opcode);
+	break;
+     case i_MVMLE:
+	genmovemle (opcode);
+	break;
+     case i_TRAP:
+	isjump;
+	failure;
+	break;
+     case i_MVR2USP:
+	isjump;
+	failure;
+	break;
+     case i_MVUSP2R:
+	isjump;
+	failure;
+	break;
+     case i_RESET:
+	isjump;
+	failure;
+	break;
+     case i_NOP:
+	break;
+     case i_STOP:
+	isjump;
+	failure;
+	break;
+     case i_RTE:
+	isjump;
+	failure;
+	break;
+     case i_RTD:
+	genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0);
+	/* offs is constant */
+	comprintf("\tadd_l_ri(offs,4);\n");
+	start_brace();
+	comprintf("\tint newad=scratchie++;\n"
+		  "\treadlong(15,newad,scratchie);\n"
+		  "\tand_l_ri(newad,~1);\n"
+		  "\tmov_l_mr((uae_u32)®s.pc,newad);\n"
+		  "\tget_n_addr_jmp(newad,PC_P,scratchie);\n"
+		  "\tmov_l_mr((uae_u32)®s.pc_oldp,PC_P);\n"
+		  "\tm68k_pc_offset=0;\n"
+		  "\tadd_l(15,offs);\n");
+	gen_update_next_handler();
+	isjump;
+	break;
+     case i_LINK:
+	genamode (curi->smode, "srcreg", sz_long, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
+	comprintf("\tsub_l_ri(15,4);\n"
+		  "\twritelong_clobber(15,src,scratchie);\n"
+		  "\tmov_l_rr(src,15);\n");
+	if (curi->size==sz_word)
+	    comprintf("\tsign_extend_16_rr(offs,offs);\n");
+	comprintf("\tadd_l(15,offs);\n");
+	genastore ("src", curi->smode, "srcreg", sz_long, "src");
+	break;
+     case i_UNLK:
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	comprintf("\tmov_l_rr(15,src);\n"
+		  "\treadlong(15,src,scratchie);\n"
+		  "\tadd_l_ri(15,4);\n");
+	genastore ("src", curi->smode, "srcreg", curi->size, "src");
+	break;
+     case i_RTS:
+	comprintf("\tint newad=scratchie++;\n"
+		  "\treadlong(15,newad,scratchie);\n"
+		  "\tand_l_ri(newad,~1);\n"
+		  "\tmov_l_mr((uae_u32)®s.pc,newad);\n"
+		  "\tget_n_addr_jmp(newad,PC_P,scratchie);\n"
+		  "\tmov_l_mr((uae_u32)®s.pc_oldp,PC_P);\n"
+		  "\tm68k_pc_offset=0;\n"
+		  "\tlea_l_brr(15,15,4);\n");
+	gen_update_next_handler();
+	isjump;
+	break;
+     case i_TRAPV:
+	isjump;
+	failure;
+	break;
+     case i_RTR:
+	isjump;
+	failure;
+	break;
+     case i_JSR:
+	isjump;
+	genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
+	start_brace();
+	comprintf("\tuae_u32 retadd=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;\n");
+	comprintf("\tint ret=scratchie++;\n"
+		  "\tmov_l_ri(ret,retadd);\n"
+		  "\tsub_l_ri(15,4);\n"
+		  "\twritelong_clobber(15,ret,scratchie);\n");
+	comprintf("\tand_l_ri(srca,~1);\n"
+		  "\tmov_l_mr((uae_u32)®s.pc,srca);\n"
+		  "\tget_n_addr_jmp(srca,PC_P,scratchie);\n"
+		  "\tmov_l_mr((uae_u32)®s.pc_oldp,PC_P);\n"
+		  "\tm68k_pc_offset=0;\n");
+	gen_update_next_handler();
+	break;
+     case i_JMP:
+	isjump;
+	genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
+	comprintf("\tand_l_ri(srca,~1);\n"
+		  "\tmov_l_mr((uae_u32)®s.pc,srca);\n"
+		  "\tget_n_addr_jmp(srca,PC_P,scratchie);\n"
+		  "\tmov_l_mr((uae_u32)®s.pc_oldp,PC_P);\n"
+		  "\tm68k_pc_offset=0;\n");
+	gen_update_next_handler();
+	break;
+     case i_BSR:
+	if (curi->size==sz_long)
+	    failure;
+	is_const_jump;
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	comprintf("\tand_l_ri(src,~1);\n");
+	start_brace();
+	comprintf("\tuae_u32 retadd=start_pc+((char *)comp_pc_p-(char *)start_pc_p)+m68k_pc_offset;\n");
+	comprintf("\tint ret=scratchie++;\n"
+		  "\tmov_l_ri(ret,retadd);\n"
+		  "\tsub_l_ri(15,4);\n"
+		  "\twritelong_clobber(15,ret,scratchie);\n");
+	comprintf("\tadd_l_ri(src,m68k_pc_offset_thisinst+2);\n");
+	comprintf("\tm68k_pc_offset=0;\n");
+	comprintf("\tadd_l(PC_P,src);\n");
+
+	comprintf("\tcomp_pc_p=(uae_u8*)get_const(PC_P);\n");
+	break;
+     case i_Bcc:
+	comprintf("\tuae_u32 v1,v2;\n");
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	/* That source is an immediate, so we can clobber it with abandon */
+	switch(curi->size) {
+	 case sz_byte: comprintf("\tsign_extend_8_rr(src,src);\n"); break;
+	 case sz_word: comprintf("\tsign_extend_16_rr(src,src);\n"); break;
+	 case sz_long: break;
+	}
+	comprintf("\tand_l_ri(src,~1);\n");
+	comprintf("\tsub_l_ri(src,m68k_pc_offset-m68k_pc_offset_thisinst-2);\n");
+	/* Leave the following as "add" --- it will allow it to be optimized
+	   away due to src being a constant ;-) */
+	comprintf("\tadd_l_ri(src,(uae_u32)comp_pc_p);\n");
+	comprintf("\tmov_l_ri(PC_P,(uae_u32)comp_pc_p);\n");
+	/* Now they are both constant. Might as well fold in m68k_pc_offset */
+	comprintf("\tadd_l_ri(src,m68k_pc_offset);\n");
+	comprintf("\tadd_l_ri(PC_P,m68k_pc_offset);\n");
+	comprintf("\tm68k_pc_offset=0;\n");
+
+	if (curi->cc>=2) {
+	    comprintf("\tv1=get_const(PC_P);\n"
+		      "\tv2=get_const(src);\n"
+		      "\tregister_branch(v1,v2,%d);\n",
+		      cond_codes_x86[curi->cc]);
+	    comprintf("\tmake_flags_live();\n"); /* Load the flags */
+	    isjump;
+	}
+	else {
+	    is_const_jump;
+	}
+
+	switch(curi->cc) {
+	 case 0:  /* Unconditional jump */
+	    comprintf("\tmov_l_rr(PC_P,src);\n");
+	    comprintf("\tcomp_pc_p=(uae_u8*)get_const(PC_P);\n");
+	    break;
+	 case 1: break; /* This is silly! */
+	 case 8: failure; break;  /* Work out details! FIXME */
+	 case 9: failure; break;  /* Not critical, though! */
+
+	 case 2:
+	 case 3:
+	 case 4:
+	 case 5:
+	 case 6:
+	 case 7:
+	 case 10:
+	 case 11:
+	 case 12:
+	 case 13:
+	 case 14:
+	 case 15:
+	    break;
+	 default: abort();
+	}
+	break;
+     case i_LEA:
+	genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0);
+	genastore ("srca", curi->dmode, "dstreg", curi->size, "dst");
+	break;
+     case i_PEA:
+	if (table68k[opcode].smode==Areg ||
+	    table68k[opcode].smode==Aind ||
+	    table68k[opcode].smode==Aipi ||
+	    table68k[opcode].smode==Apdi ||
+	    table68k[opcode].smode==Ad16 ||
+	    table68k[opcode].smode==Ad8r)
+	    comprintf("if (srcreg==7) dodgy=1;\n");
+
+	genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
+	genamode (Apdi, "7", sz_long, "dst", 2, 0);
+	genastore ("srca", Apdi, "7", sz_long, "dst");
+	break;
+     case i_DBcc:
+	isjump;
+	uses_cmov;
+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0);
+
+	/* That offs is an immediate, so we can clobber it with abandon */
+	switch(curi->size) {
+	 case sz_word: comprintf("\tsign_extend_16_rr(offs,offs);\n"); break;
+	 default: abort();  /* Seems this only comes in word flavour */
+	}
+	comprintf("\tsub_l_ri(offs,m68k_pc_offset-m68k_pc_offset_thisinst-2);\n");
+	comprintf("\tadd_l_ri(offs,(uae_u32)comp_pc_p);\n"); /* New PC,
+								once the
+								offset_68k is
+								* also added */
+	/* Let's fold in the m68k_pc_offset at this point */
+	comprintf("\tadd_l_ri(offs,m68k_pc_offset);\n");
+	comprintf("\tadd_l_ri(PC_P,m68k_pc_offset);\n");
+	comprintf("\tm68k_pc_offset=0;\n");
+
+	start_brace();
+	comprintf("\tint nsrc=scratchie++;\n");
+
+	if (curi->cc>=2) {
+	    comprintf("\tmake_flags_live();\n"); /* Load the flags */
+	}
+
+	if (curi->size!=sz_word)
+	    abort();
+
+
+	switch(curi->cc) {
+	 case 0: /* This is an elaborate nop? */
+	    break;
+	 case 1:
+	    comprintf("\tstart_needflags();\n");
+	    comprintf("\tsub_w_ri(src,1);\n");
+	    comprintf("\t end_needflags();\n");
+	    start_brace();
+	    comprintf("\tuae_u32 v2;\n"
+		      "\tuae_u32 v1=get_const(PC_P);\n");
+	    comprintf("\tv2=get_const(offs);\n"
+		      "\tregister_branch(v1,v2,3);\n");
+	    break;
+
+	 case 8: failure; break;  /* Work out details! FIXME */
+	 case 9: failure; break;  /* Not critical, though! */
+
+	 case 2:
+	 case 3:
+	 case 4:
+	 case 5:
+	 case 6:
+	 case 7:
+	 case 10:
+	 case 11:
+	 case 12:
+	 case 13:
+	 case 14:
+	 case 15:
+	    comprintf("\tmov_l_rr(nsrc,src);\n");
+	    comprintf("\tlea_l_brr(scratchie,src,(uae_s32)-1);\n"
+		      "\tmov_w_rr(src,scratchie);\n");
+	    comprintf("\tcmov_l_rr(offs,PC_P,%d);\n",
+		      cond_codes_x86[curi->cc]);
+	    comprintf("\tcmov_l_rr(src,nsrc,%d);\n",
+		      cond_codes_x86[curi->cc]);
+	    /* OK, now for cc=true, we have src==nsrc and offs==PC_P,
+	       so whether we move them around doesn't matter. However,
+	       if cc=false, we have offs==jump_pc, and src==nsrc-1 */
+
+	    comprintf("\t start_needflags();\n");
+	    comprintf("\ttest_w_rr(nsrc,nsrc);\n");
+	    comprintf("\t end_needflags();\n");
+	    comprintf("\tcmov_l_rr(PC_P,offs,5);\n");
+	    break;
+	 default: abort();
+	}
+	genastore ("src", curi->smode, "srcreg", curi->size, "src");
+	gen_update_next_handler();
+	break;
+
+     case i_Scc:
+	genamode (curi->smode, "srcreg", curi->size, "src", 2, 0);
+	start_brace ();
+	comprintf ("\tint val = scratchie++;\n");
+
+	/* We set val to 0 if we really should use 255, and to 1 for real 0 */
+	switch(curi->cc) {
+	 case 0:  /* Unconditional set */
+	    comprintf("\tmov_l_ri(val,0);\n");
+	    break;
+	 case 1:
+	    /* Unconditional not-set */
+	    comprintf("\tmov_l_ri(val,1);\n");
+	    break;
+	 case 8: failure; break;  /* Work out details! FIXME */
+	 case 9: failure; break;  /* Not critical, though! */
+
+	 case 2:
+	 case 3:
+	 case 4:
+	 case 5:
+	 case 6:
+	 case 7:
+	 case 10:
+	 case 11:
+	 case 12:
+	 case 13:
+	 case 14:
+	 case 15:
+	    comprintf("\tmake_flags_live();\n"); /* Load the flags */
+	    /* All condition codes can be inverted by changing the LSB */
+	    comprintf("\tsetcc(val,%d);\n",
+		      cond_codes_x86[curi->cc]^1); break;
+	 default: abort();
+	}
+	comprintf("\tsub_b_ri(val,1);\n");
+	genastore ("val", curi->smode, "srcreg", curi->size, "src");
+	break;
+     case i_DIVU:
+	isjump;
+	failure;
+	break;
+     case i_DIVS:
+	isjump;
+	failure;
+	break;
+     case i_MULU:
+	comprintf("\tdont_care_flags();\n");
+	genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
+	/* To do 16x16 unsigned multiplication, we actually use
+	   32x32 signed, and zero-extend the registers first.
+	   That solves the problem of MUL needing dedicated registers
+	   on the x86 */
+	comprintf("\tzero_extend_16_rr(scratchie,src);\n"
+		  "\tzero_extend_16_rr(dst,dst);\n"
+		  "\timul_32_32(dst,scratchie);\n");
+	genflags (flag_logical, sz_long, "dst", "", "");
+	genastore ("dst", curi->dmode, "dstreg", sz_long, "dst");
+	break;
+     case i_MULS:
+	comprintf("\tdont_care_flags();\n");
+	genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
+	genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0);
+	comprintf("\tsign_extend_16_rr(scratchie,src);\n"
+		  "\tsign_extend_16_rr(dst,dst);\n"
+		  "\timul_32_32(dst,scratchie);\n");
+	genflags (flag_logical, sz_long, "dst", "", "");
+	genastore ("dst", curi->dmode, "dstreg", sz_long, "dst");
+	break;
+     case i_CHK:
+	isjump;
+	failure;
+	break;
+
+     case i_CHK2:
+	isjump;
+	failure;
+	break;
+
+     case i_ASR:
+	mayfail;
+	if (curi->smode==Dreg) {
+	    comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+		"  FAIL(1);\n"
+		"  return 0;\n"
+		"} \n");
+	    start_brace();
+	}
+	comprintf("\tdont_care_flags();\n");
+
+	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	if (curi->smode!=immi) {
+	    if (!noflags) {
+		uses_cmov;
+		start_brace();
+		comprintf("\tint highmask;\n"
+			  "\tint width;\n"
+			  "\tint cdata=scratchie++;\n"
+			  "\tint tmpcnt=scratchie++;\n"
+			  "\tint highshift=scratchie++;\n");
+		comprintf("\tmov_l_rr(tmpcnt,cnt);\n"
+			  "\tand_l_ri(tmpcnt,63);\n"
+			  "\tmov_l_ri(cdata,0);\n"
+			  "\tcmov_l_rr(cdata,data,5);\n");
+		/* cdata is now either data (for shift count!=0) or
+		   0 (for shift count==0) */
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshra_b_rr(data,cnt);\n"
+					 "\thighmask=0x38;\n"
+					 "\twidth=8;\n");
+		 break;
+		 case sz_word: comprintf("\tshra_w_rr(data,cnt);\n"
+					 "\thighmask=0x30;\n"
+					 "\twidth=16;\n");
+		 break;
+		 case sz_long: comprintf("\tshra_l_rr(data,cnt);\n"
+					 "\thighmask=0x20;\n"
+					 "\twidth=32;\n");
+		 break;
+		 default: abort();
+		}
+		comprintf("test_l_ri(cnt,highmask);\n"
+			  "mov_l_ri(highshift,0);\n"
+			  "mov_l_ri(scratchie,width/2);\n"
+			  "cmov_l_rr(highshift,scratchie,5);\n");
+		/* The x86 masks out bits, so we now make sure that things
+		   really get shifted as much as planned */
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshra_b_rr(data,highshift);\n");break;
+		 case sz_word: comprintf("\tshra_w_rr(data,highshift);\n");break;
+		 case sz_long: comprintf("\tshra_l_rr(data,highshift);\n");break;
+		 default: abort();
+		}
+		/* And again */
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshra_b_rr(data,highshift);\n");break;
+		 case sz_word: comprintf("\tshra_w_rr(data,highshift);\n");break;
+		 case sz_long: comprintf("\tshra_l_rr(data,highshift);\n");break;
+		 default: abort();
+		}
+
+		/* Result of shift is now in data. Now we need to determine
+		   the carry by shifting cdata one less */
+		comprintf("\tsub_l_ri(tmpcnt,1);\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshra_b_rr(cdata,tmpcnt);\n");break;
+		 case sz_word: comprintf("\tshra_w_rr(cdata,tmpcnt);\n");break;
+		 case sz_long: comprintf("\tshra_l_rr(cdata,tmpcnt);\n");break;
+		 default: abort();
+		}
+		/* If the shift count was higher than the width, we need
+		   to pick up the sign from data */
+		comprintf("test_l_ri(tmpcnt,highmask);\n"
+			  "cmov_l_rr(cdata,data,5);\n");
+		/* And create the flags */
+		comprintf("\tstart_needflags();\n");
+		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
+		 case sz_word: comprintf("\t  test_w_rr(data,data);\n"); break;
+		 case sz_long: comprintf("\t  test_l_rr(data,data);\n"); break;
+		}
+		comprintf("\t bt_l_ri(cdata,0);\n"); /* Set C */
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		comprintf("\t duplicate_carry();\n");
+		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
+	    }
+	    else {
+		uses_cmov;
+		start_brace();
+		comprintf("\tint highmask;\n"
+			  "\tint width;\n"
+			  "\tint highshift=scratchie++;\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshra_b_rr(data,cnt);\n"
+					 "\thighmask=0x38;\n"
+					 "\twidth=8;\n");
+		 break;
+		 case sz_word: comprintf("\tshra_w_rr(data,cnt);\n"
+					 "\thighmask=0x30;\n"
+					 "\twidth=16;\n");
+		 break;
+		 case sz_long: comprintf("\tshra_l_rr(data,cnt);\n"
+					 "\thighmask=0x20;\n"
+					 "\twidth=32;\n");
+		 break;
+		 default: abort();
+		}
+		comprintf("test_l_ri(cnt,highmask);\n"
+			  "mov_l_ri(highshift,0);\n"
+			  "mov_l_ri(scratchie,width/2);\n"
+			  "cmov_l_rr(highshift,scratchie,5);\n");
+		/* The x86 masks out bits, so we now make sure that things
+		   really get shifted as much as planned */
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshra_b_rr(data,highshift);\n");break;
+		 case sz_word: comprintf("\tshra_w_rr(data,highshift);\n");break;
+		 case sz_long: comprintf("\tshra_l_rr(data,highshift);\n");break;
+		 default: abort();
+		}
+		/* And again */
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshra_b_rr(data,highshift);\n");break;
+		 case sz_word: comprintf("\tshra_w_rr(data,highshift);\n");break;
+		 case sz_long: comprintf("\tshra_l_rr(data,highshift);\n");break;
+		 default: abort();
+		}
+		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
+	    }
+	}
+	else {
+	    start_brace();
+	    comprintf("\tint tmp=scratchie++;\n"
+		      "\tint bp;\n"
+		      "\tmov_l_rr(tmp,data);\n");
+	    switch(curi->size) {
+	     case sz_byte: comprintf("\tshra_b_ri(data,srcreg);\n"
+				     "\tbp=srcreg-1;\n"); break;
+	     case sz_word: comprintf("\tshra_w_ri(data,srcreg);\n"
+				     "\tbp=srcreg-1;\n"); break;
+	     case sz_long: comprintf("\tshra_l_ri(data,srcreg);\n"
+				     "\tbp=srcreg-1;\n"); break;
+	     default: abort();
+	    }
+
+	    if (!noflags) {
+		comprintf("\tstart_needflags();\n");
+		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
+		 case sz_word: comprintf("\t  test_w_rr(data,data);\n"); break;
+		 case sz_long: comprintf("\t  test_l_rr(data,data);\n"); break;
+		}
+		comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		comprintf("\t duplicate_carry();\n");
+		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	    }
+	    genastore ("data", curi->dmode, "dstreg", curi->size, "data");
+	}
+	break;
+
+     case i_ASL:
+	mayfail;
+	if (curi->smode==Dreg) {
+	    comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+		"  FAIL(1);\n"
+		"  return 0;\n"
+		"} \n");
+	    start_brace();
+	}
+	comprintf("\tdont_care_flags();\n");
+	/* Except for the handling of the V flag, this is identical to
+	   LSL. The handling of V is, uhm, unpleasant, so if it's needed,
+	   let the normal emulation handle it. Shoulders of giants kinda
+	   thing ;-) */
+	comprintf("if (needed_flags & FLAG_V) {\n"
+		  "  FAIL(1);\n"
+		  "  return 0;\n"
+		  "} \n");
+
+	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	if (curi->smode!=immi) {
+	    if (!noflags) {
+		uses_cmov;
+		start_brace();
+		comprintf("\tint highmask;\n"
+			  "\tint cdata=scratchie++;\n"
+			  "\tint tmpcnt=scratchie++;\n");
+		comprintf("\tmov_l_rr(tmpcnt,cnt);\n"
+			  "\tand_l_ri(tmpcnt,63);\n"
+			  "\tmov_l_ri(cdata,0);\n"
+			  "\tcmov_l_rr(cdata,data,5);\n");
+		/* cdata is now either data (for shift count!=0) or
+		   0 (for shift count==0) */
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshll_b_rr(data,cnt);\n"
+					 "\thighmask=0x38;\n");
+		 break;
+		 case sz_word: comprintf("\tshll_w_rr(data,cnt);\n"
+					 "\thighmask=0x30;\n");
+		 break;
+		 case sz_long: comprintf("\tshll_l_rr(data,cnt);\n"
+					 "\thighmask=0x20;\n");
+		 break;
+		 default: abort();
+		}
+		comprintf("test_l_ri(cnt,highmask);\n"
+			  "mov_l_ri(scratchie,0);\n"
+			  "cmov_l_rr(scratchie,data,4);\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break;
+		 case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break;
+		 case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break;
+		 default: abort();
+		}
+		/* Result of shift is now in data. Now we need to determine
+		   the carry by shifting cdata one less */
+		comprintf("\tsub_l_ri(tmpcnt,1);\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshll_b_rr(cdata,tmpcnt);\n");break;
+		 case sz_word: comprintf("\tshll_w_rr(cdata,tmpcnt);\n");break;
+		 case sz_long: comprintf("\tshll_l_rr(cdata,tmpcnt);\n");break;
+		 default: abort();
+		}
+		comprintf("test_l_ri(tmpcnt,highmask);\n"
+			  "mov_l_ri(scratchie,0);\n"
+			  "cmov_l_rr(cdata,scratchie,5);\n");
+		/* And create the flags */
+		comprintf("\tstart_needflags();\n");
+
+		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n");
+		    comprintf("\t bt_l_ri(cdata,7);\n"); break;
+		 case sz_word: comprintf("\t  test_w_rr(data,data);\n");
+		    comprintf("\t bt_l_ri(cdata,15);\n"); break;
+		 case sz_long: comprintf("\t  test_l_rr(data,data);\n");
+		    comprintf("\t bt_l_ri(cdata,31);\n"); break;
+		}
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		comprintf("\t duplicate_carry();\n");
+		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
+	    }
+	    else {
+		uses_cmov;
+		start_brace();
+		comprintf("\tint highmask;\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshll_b_rr(data,cnt);\n"
+					 "\thighmask=0x38;\n");
+		    break;
+		 case sz_word: comprintf("\tshll_w_rr(data,cnt);\n"
+					 "\thighmask=0x30;\n");
+		    break;
+		 case sz_long: comprintf("\tshll_l_rr(data,cnt);\n"
+					 "\thighmask=0x20;\n");
+		    break;
+		 default: abort();
+		}
+		comprintf("test_l_ri(cnt,highmask);\n"
+			  "mov_l_ri(scratchie,0);\n"
+			  "cmov_l_rr(scratchie,data,4);\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break;
+		 case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break;
+		 case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break;
+		 default: abort();
+		}
+		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
+	    }
+	}
+	else {
+	    start_brace();
+	    comprintf("\tint tmp=scratchie++;\n"
+		      "\tint bp;\n"
+		      "\tmov_l_rr(tmp,data);\n");
+	    switch(curi->size) {
+	     case sz_byte: comprintf("\tshll_b_ri(data,srcreg);\n"
+				     "\tbp=8-srcreg;\n"); break;
+	     case sz_word: comprintf("\tshll_w_ri(data,srcreg);\n"
+				     "\tbp=16-srcreg;\n"); break;
+	     case sz_long: comprintf("\tshll_l_ri(data,srcreg);\n"
+				     "\tbp=32-srcreg;\n"); break;
+	     default: abort();
+	    }
+
+	    if (!noflags) {
+		comprintf("\tstart_needflags();\n");
+		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
+		 case sz_word: comprintf("\t  test_w_rr(data,data);\n"); break;
+		 case sz_long: comprintf("\t  test_l_rr(data,data);\n"); break;
+		}
+		comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		comprintf("\t duplicate_carry();\n");
+		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	    }
+	    genastore ("data", curi->dmode, "dstreg", curi->size, "data");
+	}
+	break;
+
+     case i_LSR:
+	mayfail;
+	if (curi->smode==Dreg) {
+	    comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+		"  FAIL(1);\n"
+		"  return 0;\n"
+		"} \n");
+	    start_brace();
+	}
+	comprintf("\tdont_care_flags();\n");
+
+	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	if (curi->smode!=immi) {
+	    if (!noflags) {
+		uses_cmov;
+		start_brace();
+		comprintf("\tint highmask;\n"
+			  "\tint cdata=scratchie++;\n"
+			  "\tint tmpcnt=scratchie++;\n");
+		comprintf("\tmov_l_rr(tmpcnt,cnt);\n"
+			  "\tand_l_ri(tmpcnt,63);\n"
+			  "\tmov_l_ri(cdata,0);\n"
+			  "\tcmov_l_rr(cdata,data,5);\n");
+		/* cdata is now either data (for shift count!=0) or
+		   0 (for shift count==0) */
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshrl_b_rr(data,cnt);\n"
+					 "\thighmask=0x38;\n");
+		 break;
+		 case sz_word: comprintf("\tshrl_w_rr(data,cnt);\n"
+					 "\thighmask=0x30;\n");
+		 break;
+		 case sz_long: comprintf("\tshrl_l_rr(data,cnt);\n"
+					 "\thighmask=0x20;\n");
+		 break;
+		 default: abort();
+		}
+		comprintf("test_l_ri(cnt,highmask);\n"
+			  "mov_l_ri(scratchie,0);\n"
+			  "cmov_l_rr(scratchie,data,4);\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break;
+		 case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break;
+		 case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break;
+		 default: abort();
+		}
+		/* Result of shift is now in data. Now we need to determine
+		   the carry by shifting cdata one less */
+		comprintf("\tsub_l_ri(tmpcnt,1);\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshrl_b_rr(cdata,tmpcnt);\n");break;
+		 case sz_word: comprintf("\tshrl_w_rr(cdata,tmpcnt);\n");break;
+		 case sz_long: comprintf("\tshrl_l_rr(cdata,tmpcnt);\n");break;
+		 default: abort();
+		}
+		comprintf("test_l_ri(tmpcnt,highmask);\n"
+			  "mov_l_ri(scratchie,0);\n"
+			  "cmov_l_rr(cdata,scratchie,5);\n");
+		/* And create the flags */
+		comprintf("\tstart_needflags();\n");
+		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
+		 case sz_word: comprintf("\t  test_w_rr(data,data);\n"); break;
+		 case sz_long: comprintf("\t  test_l_rr(data,data);\n"); break;
+		}
+		comprintf("\t bt_l_ri(cdata,0);\n"); /* Set C */
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		comprintf("\t duplicate_carry();\n");
+		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
+	    }
+	    else {
+		uses_cmov;
+		start_brace();
+		comprintf("\tint highmask;\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshrl_b_rr(data,cnt);\n"
+					 "\thighmask=0x38;\n");
+		    break;
+		 case sz_word: comprintf("\tshrl_w_rr(data,cnt);\n"
+					 "\thighmask=0x30;\n");
+		    break;
+		 case sz_long: comprintf("\tshrl_l_rr(data,cnt);\n"
+					 "\thighmask=0x20;\n");
+		    break;
+		 default: abort();
+		}
+		comprintf("test_l_ri(cnt,highmask);\n"
+			  "mov_l_ri(scratchie,0);\n"
+			  "cmov_l_rr(scratchie,data,4);\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break;
+		 case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break;
+		 case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break;
+		 default: abort();
+		}
+		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
+	    }
+	}
+	else {
+	    start_brace();
+	    comprintf("\tint tmp=scratchie++;\n"
+		      "\tint bp;\n"
+		      "\tmov_l_rr(tmp,data);\n");
+	    switch(curi->size) {
+	     case sz_byte: comprintf("\tshrl_b_ri(data,srcreg);\n"
+				     "\tbp=srcreg-1;\n"); break;
+	     case sz_word: comprintf("\tshrl_w_ri(data,srcreg);\n"
+				     "\tbp=srcreg-1;\n"); break;
+	     case sz_long: comprintf("\tshrl_l_ri(data,srcreg);\n"
+				     "\tbp=srcreg-1;\n"); break;
+	     default: abort();
+	    }
+
+	    if (!noflags) {
+		comprintf("\tstart_needflags();\n");
+		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
+		 case sz_word: comprintf("\t  test_w_rr(data,data);\n"); break;
+		 case sz_long: comprintf("\t  test_l_rr(data,data);\n"); break;
+		}
+		comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		comprintf("\t duplicate_carry();\n");
+		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	    }
+	    genastore ("data", curi->dmode, "dstreg", curi->size, "data");
+	}
+	break;
+
+     case i_LSL:
+	comprintf("\tdont_care_flags();\n");
+
+	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	if (curi->smode!=immi) {
+	    if (!noflags) {
+		uses_cmov;
+		start_brace();
+		comprintf("\tint highmask;\n"
+			  "\tint cdata=scratchie++;\n"
+			  "\tint tmpcnt=scratchie++;\n");
+		comprintf("\tmov_l_rr(tmpcnt,cnt);\n"
+			  "\tand_l_ri(tmpcnt,63);\n"
+			  "\tmov_l_ri(cdata,0);\n"
+			  "\tcmov_l_rr(cdata,data,5);\n");
+		/* cdata is now either data (for shift count!=0) or
+		   0 (for shift count==0) */
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshll_b_rr(data,cnt);\n"
+					 "\thighmask=0x38;\n");
+		 break;
+		 case sz_word: comprintf("\tshll_w_rr(data,cnt);\n"
+					 "\thighmask=0x30;\n");
+		 break;
+		 case sz_long: comprintf("\tshll_l_rr(data,cnt);\n"
+					 "\thighmask=0x20;\n");
+		 break;
+		 default: abort();
+		}
+		comprintf("test_l_ri(cnt,highmask);\n"
+			  "mov_l_ri(scratchie,0);\n"
+			  "cmov_l_rr(scratchie,data,4);\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break;
+		 case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break;
+		 case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break;
+		 default: abort();
+		}
+		/* Result of shift is now in data. Now we need to determine
+		   the carry by shifting cdata one less */
+		comprintf("\tsub_l_ri(tmpcnt,1);\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshll_b_rr(cdata,tmpcnt);\n");break;
+		 case sz_word: comprintf("\tshll_w_rr(cdata,tmpcnt);\n");break;
+		 case sz_long: comprintf("\tshll_l_rr(cdata,tmpcnt);\n");break;
+		 default: abort();
+		}
+		comprintf("test_l_ri(tmpcnt,highmask);\n"
+			  "mov_l_ri(scratchie,0);\n"
+			  "cmov_l_rr(cdata,scratchie,5);\n");
+		/* And create the flags */
+		comprintf("\tstart_needflags();\n");
+		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n");
+		    comprintf("\t bt_l_ri(cdata,7);\n"); break;
+		 case sz_word: comprintf("\t  test_w_rr(data,data);\n");
+		    comprintf("\t bt_l_ri(cdata,15);\n"); break;
+		 case sz_long: comprintf("\t  test_l_rr(data,data);\n");
+		    comprintf("\t bt_l_ri(cdata,31);\n"); break;
+		}
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		comprintf("\t duplicate_carry();\n");
+		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
+	    }
+	    else {
+		uses_cmov;
+		start_brace();
+		comprintf("\tint highmask;\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tshll_b_rr(data,cnt);\n"
+					 "\thighmask=0x38;\n");
+		    break;
+		 case sz_word: comprintf("\tshll_w_rr(data,cnt);\n"
+					 "\thighmask=0x30;\n");
+		    break;
+		 case sz_long: comprintf("\tshll_l_rr(data,cnt);\n"
+					 "\thighmask=0x20;\n");
+		    break;
+		 default: abort();
+		}
+		comprintf("test_l_ri(cnt,highmask);\n"
+			  "mov_l_ri(scratchie,0);\n"
+			  "cmov_l_rr(scratchie,data,4);\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break;
+		 case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break;
+		 case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break;
+		 default: abort();
+		}
+		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
+	    }
+	}
+	else {
+	    start_brace();
+	    comprintf("\tint tmp=scratchie++;\n"
+		      "\tint bp;\n"
+		      "\tmov_l_rr(tmp,data);\n");
+	    switch(curi->size) {
+	     case sz_byte: comprintf("\tshll_b_ri(data,srcreg);\n"
+				     "\tbp=8-srcreg;\n"); break;
+	     case sz_word: comprintf("\tshll_w_ri(data,srcreg);\n"
+				     "\tbp=16-srcreg;\n"); break;
+	     case sz_long: comprintf("\tshll_l_ri(data,srcreg);\n"
+				     "\tbp=32-srcreg;\n"); break;
+	     default: abort();
+	    }
+
+	    if (!noflags) {
+		comprintf("\tstart_needflags();\n");
+		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+		switch(curi->size) {
+		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
+		 case sz_word: comprintf("\t  test_w_rr(data,data);\n"); break;
+		 case sz_long: comprintf("\t  test_l_rr(data,data);\n"); break;
+		}
+		comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */
+		comprintf("\t live_flags();\n");
+		comprintf("\t end_needflags();\n");
+		comprintf("\t duplicate_carry();\n");
+		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	    }
+	    genastore ("data", curi->dmode, "dstreg", curi->size, "data");
+	}
+	break;
+
+     case i_ROL:
+	mayfail;
+	if (curi->smode==Dreg) {
+	    comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+		"  FAIL(1);\n"
+		"  return 0;\n"
+		"} \n");
+	    start_brace();
+	}
+	comprintf("\tdont_care_flags();\n");
+	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	start_brace ();
+
+	switch(curi->size) {
+	 case sz_long: comprintf("\t rol_l_rr(data,cnt);\n"); break;
+	 case sz_word: comprintf("\t rol_w_rr(data,cnt);\n"); break;
+	 case sz_byte: comprintf("\t rol_b_rr(data,cnt);\n"); break;
+	}
+
+	if (!noflags) {
+	    comprintf("\tstart_needflags();\n");
+	    comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+	    switch(curi->size) {
+	     case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
+	     case sz_word: comprintf("\t  test_w_rr(data,data);\n"); break;
+	     case sz_long: comprintf("\t  test_l_rr(data,data);\n"); break;
+	    }
+	    comprintf("\t bt_l_ri(data,0x00);\n"); /* Set C */
+	    comprintf("\t live_flags();\n");
+	    comprintf("\t end_needflags();\n");
+	}
+	genastore ("data", curi->dmode, "dstreg", curi->size, "data");
+	break;
+
+     case i_ROR:
+	mayfail;
+	if (curi->smode==Dreg) {
+	    comprintf("if ((uae_u32)srcreg==(uae_u32)dstreg) {\n"
+		"  FAIL(1);\n"
+		"  return 0;\n"
+		"} \n");
+	    start_brace();
+	}
+	comprintf("\tdont_care_flags();\n");
+	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
+	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
+	start_brace ();
+
+	switch(curi->size) {
+	 case sz_long: comprintf("\t ror_l_rr(data,cnt);\n"); break;
+	 case sz_word: comprintf("\t ror_w_rr(data,cnt);\n"); break;
+	 case sz_byte: comprintf("\t ror_b_rr(data,cnt);\n"); break;
+	}
+
+	if (!noflags) {
+	    comprintf("\tstart_needflags();\n");
+	    comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+	    switch(curi->size) {
+	     case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
+	     case sz_word: comprintf("\t  test_w_rr(data,data);\n"); break;
+	     case sz_long: comprintf("\t  test_l_rr(data,data);\n"); break;
+	    }
+	    switch(curi->size) {
+	     case sz_byte: comprintf("\t bt_l_ri(data,0x07);\n"); break;
+	     case sz_word: comprintf("\t bt_l_ri(data,0x0f);\n"); break;
+	     case sz_long: comprintf("\t bt_l_ri(data,0x1f);\n"); break;
+	    }
+	    comprintf("\t live_flags();\n");
+	    comprintf("\t end_needflags();\n");
+	}
+	genastore ("data", curi->dmode, "dstreg", curi->size, "data");
+	break;
+
+     case i_ROXL:
+	failure;
+	break;
+     case i_ROXR:
+	failure;
+	break;
+     case i_ASRW:
+	failure;
+	break;
+     case i_ASLW:
+	failure;
+	break;
+     case i_LSRW:
+	failure;
+	break;
+     case i_LSLW:
+	failure;
+	break;
+     case i_ROLW:
+	failure;
+	break;
+     case i_RORW:
+	failure;
+	break;
+     case i_ROXLW:
+	failure;
+	break;
+     case i_ROXRW:
+	failure;
+	break;
+     case i_MOVEC2:
+	isjump;
+	failure;
+	break;
+     case i_MOVE2C:
+	isjump;
+	failure;
+	break;
+     case i_CAS:
+	failure;
+	break;
+     case i_CAS2:
+	failure;
+	break;
+     case i_MOVES:		/* ignore DFC and SFC because we have no MMU */
+	isjump;
+	failure;
+	break;
+     case i_BKPT:		/* only needed for hardware emulators */
+	isjump;
+	failure;
+	break;
+     case i_CALLM:		/* not present in 68030 */
+	isjump;
+	failure;
+	break;
+     case i_RTM:		/* not present in 68030 */
+	isjump;
+	failure;
+	break;
+     case i_TRAPcc:
+	isjump;
+	failure;
+	break;
+     case i_DIVL:
+	isjump;
+	failure;
+	break;
+     case i_MULL:
+	if (!noflags) {
+	    failure;
+	    break;
+	}
+	comprintf("\tuae_u16 extra=%s;\n",gen_nextiword());
+	comprintf("\tint r2=(extra>>12)&7;\n"
+		  "\tint tmp=scratchie++;\n");
+
+	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
+	/* The two operands are in dst and r2 */
+	comprintf("\tif (extra&0x0400) {\n" /* Need full 64 bit result */
+		  "\tint r3=(extra&7);\n"
+		  "\tmov_l_rr(r3,dst);\n"); /* operands now in r3 and r2 */
+	comprintf("\tif (extra&0x0800) { \n" /* signed */
+		  "\t\timul_64_32(r2,r3);\n"
+		  "\t} else { \n"
+		  "\t\tmul_64_32(r2,r3);\n"
+		  "\t} \n");
+	/* The result is in r2/tmp, with r2 holding the lower 32 bits */
+	comprintf("\t} else {\n");  /* Only want 32 bit result */
+	/* operands in dst and r2, result foes into r2 */
+	/* shouldn't matter whether it's signed or unsigned?!? */
+	comprintf("\timul_32_32(r2,dst);\n"
+		  "\t}\n");
+	break;
+
+     case i_BFTST:
+     case i_BFEXTU:
+     case i_BFCHG:
+     case i_BFEXTS:
+     case i_BFCLR:
+     case i_BFFFO:
+     case i_BFSET:
+     case i_BFINS:
+	failure;
+	break;
+     case i_PACK:
+	failure;
+	break;
+     case i_UNPK:
+	failure;
+	break;
+     case i_TAS:
+	failure;
+	break;
+     case i_FPP:
+	mayfail;
+	comprintf("\tuae_u16 extra=%s;\n",gen_nextiword());
+	comprintf("\tcomp_fpp_opp(opcode,extra);\n");
+	break;
+     case i_FBcc:
+	isjump;
+	uses_cmov;
+	mayfail;
+	comprintf("\tcomp_fbcc_opp(opcode);\n");
+	break;
+     case i_FDBcc:
+	isjump;
+	failure;
+	break;
+     case i_FScc:
+	mayfail;
+	uses_cmov;
+	comprintf("\tuae_u16 extra=%s;\n",gen_nextiword());
+	comprintf("\tcomp_fscc_opp(opcode,extra);\n");
+	break;
+     case i_FTRAPcc:
+	isjump;
+	failure;
+	break;
+     case i_FSAVE:
+	failure;
+	break;
+     case i_FRESTORE:
+	failure;
+	break;
+
+     case i_CINVL:
+     case i_CINVP:
+     case i_CINVA:
+	isjump;  /* Not really, but it's probably a good idea to stop
+		    translating at this point */
+	failure;
+	comprintf ("\tflush_icache();\n");  /* Differentiate a bit more? */
+	break;
+     case i_CPUSHL:
+     case i_CPUSHP:
+     case i_CPUSHA:
+	isjump;  /* Not really, but it's probably a good idea to stop
+		    translating at this point */
+	failure;
+	break;
+     case i_MOVE16:
+	//if ((opcode & 0xfff8) == 0xf620) {
+	    genmov16(opcode,curi);
+	//} else {
+	//    isjump;
+	//    failure;
+	//}
+	break;
+
+     case i_MMUOP030:
+     case i_PFLUSHN:
+     case i_PFLUSH:
+     case i_PFLUSHAN:
+     case i_PFLUSHA:
+     case i_PLPAR:
+     case i_PLPAW:
+     case i_PTESTR:
+     case i_PTESTW:
+     case i_LPSTOP:
+	isjump;
+	failure;
+	break;
+     default:
+	abort ();
+	break;
+    }
+    comprintf("%s",endstr);
+    finish_braces ();
+    sync_m68k_pc ();
+    if (global_mayfail)
+	comprintf("\tif (failure)  m68k_pc_offset=m68k_pc_offset_thisinst;\n");
+    return global_failure;
+}
+
+static void
+generate_includes (FILE * f, int bigger)
+{
+    fprintf (f, "#include \"sysconfig.h\"\n");
+    fprintf (f, "#if defined(JIT)\n");
+    fprintf (f, "#include \"sysdeps.h\"\n");
+	if (bigger)
+		fprintf (f, "#include \"options.h\"\n");
+    fprintf (f, "#include \"memory.h\"\n");
+    fprintf (f, "#include \"newcpu.h\"\n");
+    fprintf (f, "#include \"comptbl.h\"\n");
+}
+
+static int postfix;
+
+
+static char *decodeEA (amodes mode, wordsizes size)
+{
+	static char buffer[80];
+
+	buffer[0] = 0;
+	switch (mode){
+	case Dreg:
+		strcpy (buffer,"Dn");
+		break;
+	case Areg:
+		strcpy (buffer,"An");
+		break;
+	case Aind:
+		strcpy (buffer,"(An)");
+		break;
+	case Aipi:
+		strcpy (buffer,"(An)+");
+		break;
+	case Apdi:
+		strcpy (buffer,"-(An)");
+		break;
+	case Ad16:
+		strcpy (buffer,"(d16,An)");
+		break;
+	case Ad8r:
+		strcpy (buffer,"(d8,An,Xn)");
+		break;
+	case PC16:
+		strcpy (buffer,"(d16,PC)");
+		break;
+	case PC8r:
+		strcpy (buffer,"(d8,PC,Xn)");
+		break;
+	case absw:
+		strcpy (buffer,"(xxx).W");
+		break;
+	case absl:
+		strcpy (buffer,"(xxx).L");
+		break;
+	case imm:
+		switch (size){
+		case sz_byte:
+			strcpy (buffer,"#.B");
+			break;
+		case sz_word:
+			strcpy (buffer,"#.W");
+			break;
+		case sz_long:
+			strcpy (buffer,"#.L");
+			break;
+		default:
+			break;
+		}
+		break;
+	case imm0:
+		strcpy (buffer,"#.B");
+		break;
+	case imm1:
+		strcpy (buffer,"#.W");
+		break;
+	case imm2:
+		strcpy (buffer,"#.L");
+		break;
+	case immi:
+		strcpy (buffer,"#");
+		break;
+
+	default:
+		break;
+	}
+	return buffer;
+}
+
+static char *outopcode (int opcode)
+{
+	static char out[100];
+	struct instr *ins;
+	int i;
+
+	ins = &table68k[opcode];
+	for (i = 0; lookuptab[i].name[0]; i++) {
+		if (ins->mnemo == lookuptab[i].mnemo)
+			break;
+	}
+	{
+		char *s = ua (lookuptab[i].name);
+		strcpy (out, s);
+		xfree (s);
+	}
+	if (ins->smode == immi)
+		strcat (out, "Q");
+	if (ins->size == sz_byte)
+		strcat (out,".B");
+	if (ins->size == sz_word)
+		strcat (out,".W");
+	if (ins->size == sz_long)
+		strcat (out,".L");
+	strcat (out," ");
+	if (ins->suse)
+		strcat (out, decodeEA (ins->smode, ins->size));
+	if (ins->duse) {
+		if (ins->suse) strcat (out,",");
+		strcat (out, decodeEA (ins->dmode, ins->size));
+	}
+	return out;
+}
+
+static void
+generate_one_opcode (int rp, int noflags)
+{
+    int i;
+    uae_u16 smsk, dmsk;
+    long int opcode = opcode_map[rp];
+    int aborted=0;
+    int have_srcreg=0;
+    int have_dstreg=0;
+
+    if (table68k[opcode].mnemo == i_ILLG
+	|| table68k[opcode].clev > cpu_level)
+	return;
+
+    for (i = 0; lookuptab[i].name[0]; i++)
+    {
+	if (table68k[opcode].mnemo == lookuptab[i].mnemo)
+	    break;
+    }
+
+    if (table68k[opcode].handler != -1)
+	return;
+
+    switch (table68k[opcode].stype)
+    {
+    case 0: smsk = 7; break;
+    case 1: smsk = 255; break;
+    case 2: smsk = 15;	break;
+    case 3: smsk = 7; break;
+    case 4: smsk = 7; break;
+    case 5: smsk = 63; break;
+    case 7: smsk = 3; break;
+    default: abort ();
+    }
+    dmsk = 7;
+
+    next_cpu_level = -1;
+    if (table68k[opcode].suse
+	&& table68k[opcode].smode != imm && table68k[opcode].smode != imm0
+	&& table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
+	&& table68k[opcode].smode != absw && table68k[opcode].smode != absl
+	&& table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
+    {
+	have_srcreg=1;
+	if (table68k[opcode].spos == -1)
+	{
+	    if (((int) table68k[opcode].sreg) >= 128)
+		comprintf ("\tuae_s32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
+	    else
+		comprintf ("\tuae_s32 srcreg = %d;\n", (int) table68k[opcode].sreg);
+	}
+	else
+	{
+	    char source[100];
+	    int pos = table68k[opcode].spos;
+
+	    if (pos)
+		sprintf (source, "((opcode >> %d) & %d)", pos, smsk);
+	    else
+		sprintf (source, "(opcode & %d)", smsk);
+
+	    if (table68k[opcode].stype == 3)
+		comprintf ("\tuae_s32 srcreg = imm8_table[%s];\n", source);
+	    else if (table68k[opcode].stype == 1)
+		comprintf ("\tuae_s32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
+	    else
+		comprintf ("\tuae_s32 srcreg = %s;\n", source);
+	}
+    }
+    if (table68k[opcode].duse
+	/* Yes, the dmode can be imm, in case of LINK or DBcc */
+	&& table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
+	&& table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
+	&& table68k[opcode].dmode != absw && table68k[opcode].dmode != absl)
+    {
+	have_dstreg=1;
+	if (table68k[opcode].dpos == -1)
+	{
+	    if (((int) table68k[opcode].dreg) >= 128)
+		comprintf ("\tuae_s32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
+	    else
+		comprintf ("\tuae_s32 dstreg = %d;\n", (int) table68k[opcode].dreg);
+	}
+	else
+	{
+	    int pos = table68k[opcode].dpos;
+
+	    if (pos)
+		comprintf ("\tuae_u32 dstreg = (opcode >> %d) & %d;\n",
+			   pos, dmsk);
+	    else
+		comprintf ("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
+	}
+    }
+
+    if (have_srcreg && have_dstreg &&
+	(table68k[opcode].dmode==Areg ||
+	 table68k[opcode].dmode==Aind ||
+	 table68k[opcode].dmode==Aipi ||
+	 table68k[opcode].dmode==Apdi ||
+	 table68k[opcode].dmode==Ad16 ||
+	 table68k[opcode].dmode==Ad8r) &&
+	(table68k[opcode].smode==Areg ||
+	 table68k[opcode].smode==Aind ||
+	 table68k[opcode].smode==Aipi ||
+	 table68k[opcode].smode==Apdi ||
+	 table68k[opcode].smode==Ad16 ||
+	 table68k[opcode].smode==Ad8r)
+	) {
+	comprintf("\tuae_u32 dodgy=(srcreg==(uae_s32)dstreg);\n");
+    }
+    else {
+	comprintf("\tuae_u32 dodgy=0;\n");
+    }
+    comprintf("\tuae_u32 m68k_pc_offset_thisinst=m68k_pc_offset;\n");
+    comprintf("\tm68k_pc_offset+=2;\n");
+
+    aborted=gen_opcode (opcode);
+    {
+	int flags=0;
+	if (global_isjump) flags|=1;
+	if (long_opcode)   flags|=2;
+	if (global_cmov)   flags|=4;
+	if (global_isaddx) flags|=8;
+	if (global_iscjump) flags|=16;
+	comprintf ("return 0;\n");
+	comprintf ("}\n");
+
+	char *name = ua (lookuptab[i].name);
+	if (aborted) {
+	    fprintf (stblfile, "{ NULL, %ld, 0x%08x }, /* %s */\n", opcode, flags, name);
+	    com_discard();
+	} else {
+		printf ("/* %s */\n", outopcode (opcode));
+		if (noflags) {
+		fprintf (stblfile, "{ op_%lx_%d_comp_nf, %ld, 0x%08x }, /* %s */\n", opcode, postfix, opcode, flags, name);
+		fprintf (headerfile, "extern compop_func op_%lx_%d_comp_nf;\n", opcode, postfix);
+		printf ("uae_u32 REGPARAM2 op_%lx_%d_comp_nf(uae_u32 opcode)\n{\n", opcode, postfix);
+	    } else {
+		fprintf (stblfile, "{ op_%lx_%d_comp_ff, %ld, 0x%08x }, /* %s */\n", opcode, postfix, opcode, flags, name);
+		fprintf (headerfile, "extern compop_func op_%lx_%d_comp_ff;\n", opcode, postfix);
+		printf ("uae_u32 REGPARAM2 op_%lx_%d_comp_ff(uae_u32 opcode)\n{\n", opcode, postfix);
+	    }
+	    com_flush();
+	}
+	xfree (name);
+    }
+    opcode_next_clev[rp] = next_cpu_level;
+    opcode_last_postfix[rp] = postfix;
+}
+
+static void
+generate_func (int noflags)
+{
+    int i, j, rp;
+
+    using_prefetch = 0;
+    using_exception_3 = 0;
+    for (i = 0; i < 1; i++) /* We only do one level! */
+    {
+	cpu_level = 5 - i;
+	postfix = i;
+
+	if (noflags)
+	    fprintf (stblfile, "const struct comptbl op_smalltbl_%d_comp_nf[] = {\n", postfix);
+	else
+	    fprintf (stblfile, "const struct comptbl op_smalltbl_%d_comp_ff[] = {\n", postfix);
+
+
+	/* sam: this is for people with low memory (eg. me :)) */
+	printf ("\n"
+		 "#if !defined(PART_1) && !defined(PART_2) && "
+		 "!defined(PART_3) && !defined(PART_4) && "
+		 "!defined(PART_5) && !defined(PART_6) && "
+		 "!defined(PART_7) && !defined(PART_8)"
+		 "\n"
+		 "#define PART_1 1\n"
+		 "#define PART_2 1\n"
+		 "#define PART_3 1\n"
+		 "#define PART_4 1\n"
+		 "#define PART_5 1\n"
+		 "#define PART_6 1\n"
+		 "#define PART_7 1\n"
+		 "#define PART_8 1\n"
+		 "#endif\n\n"
+		 "extern void setzflg_l(uae_u32);\n"
+		 "extern void comp_fpp_opp();\n"
+		 "extern void comp_fscc_opp();\n"
+		 "extern void comp_fbcc_opp();\n\n");
+
+	printf ("#define JIT_M68K_PC_SYNC 100\n\n");
+
+	rp = 0;
+	for (j = 1; j <= 8; ++j)
+	{
+	    int k = (j * nr_cpuop_funcs) / 8;
+	    printf ("#ifdef PART_%d\n", j);
+	    for (; rp < k; rp++)
+		generate_one_opcode (rp,noflags);
+	    printf ("#endif\n\n");
+	}
+
+	fprintf (stblfile, "{ 0, 65536, 0 }};\n");
+    }
+
+}
+
+int
+main (int argc, char **argv)
+{
+    read_table68k ();
+    do_merges ();
+
+    opcode_map = xmalloc (int, nr_cpuop_funcs);
+    opcode_last_postfix = xmalloc (int, nr_cpuop_funcs);
+    opcode_next_clev = xmalloc (int, nr_cpuop_funcs);
+    counts = xmalloc (unsigned long, 65536);
+    read_counts ();
+
+    /* It would be a lot nicer to put all in one file (we'd also get rid of
+     * cputbl.h that way), but cpuopti can't cope.  That could be fixed, but
+     * I don't dare to touch the 68k version.  */
+
+    headerfile = fopen ("jit/comptbl.h", "wb");
+
+	fprintf (headerfile, "" \
+		"#ifdef NOFLAGS_SUPPORT\n" \
+		"/* 68040 */\n" \
+		"extern const struct comptbl op_smalltbl_0_nf[];\n" \
+		"#endif\n" \
+		"extern const struct comptbl op_smalltbl_0_comp_nf[];\n" \
+		"extern const struct comptbl op_smalltbl_0_comp_ff[];\n" \
+		"");
+	
+	stblfile = fopen ("jit/compstbl.cpp", "wb");
+    freopen ("jit/compemu.cpp", "wb", stdout);
+
+    generate_includes (stdout, 1);
+    generate_includes (stblfile, 1);
+
+    printf("#include \"compemu.h\"\n");
+
+    noflags=0;
+    generate_func (noflags);
+
+
+    opcode_map = xmalloc (int, nr_cpuop_funcs);
+    opcode_last_postfix = xmalloc (int, nr_cpuop_funcs);
+    opcode_next_clev = xmalloc (int, nr_cpuop_funcs);
+    counts = xmalloc (unsigned long, 65536);
+    read_counts ();
+    noflags=1;
+    generate_func (noflags);
+
+    printf ("#endif\n");
+    fprintf (stblfile, "#endif\n");
+
+    free (table68k);
+    return 0;
+}
+
+void write_log (const TCHAR *format,...)
+{
+}
diff --git a/src/cpu/m68k.h b/src/cpu/m68k.h
new file mode 100644
index 0000000..8d120d6
--- /dev/null
+++ b/src/cpu/m68k.h
@@ -0,0 +1,94 @@
+/*
+  * UAE - The Un*x Amiga Emulator
+  *
+  * MC68000 emulation - machine dependent bits
+  *
+  * Copyright 1996 Bernd Schmidt
+  * Copyright 2004-2005 Richard Drummond
+  */
+
+ /*
+  * Machine dependent structure for holding the 68k CCR flags
+  */
+struct flag_struct {
+    unsigned int cznv;
+    unsigned int x;
+};
+
+extern struct flag_struct regflags;
+
+/*
+ * The bits in the cznv field in the above structure are assigned to
+ * allow the easy mirroring of the x86 condition flags. (For example,
+ * from the AX register - the x86 overflow flag can be copied to AL
+ * with a setto %AL instr and the other flags copied to AH with an
+ * lahf instr).
+ *
+ * The 68k CZNV flags are thus assinged in cznv as:
+ *
+ * <--AL-->  <--AH-->
+ * 76543210  FEDCBA98 --------- ---------
+ * xxxxxxxV  NZxxxxxC xxxxxxxxx xxxxxxxxx
+ */
+
+#define FLAGBIT_N	15
+#define FLAGBIT_Z	14
+#define FLAGBIT_C	8
+#define FLAGBIT_V	0
+#define FLAGBIT_X	8
+
+#define FLAGVAL_N	(1 << FLAGBIT_N)
+#define FLAGVAL_Z 	(1 << FLAGBIT_Z)
+#define FLAGVAL_C	(1 << FLAGBIT_C)
+#define FLAGVAL_V	(1 << FLAGBIT_V)
+#define FLAGVAL_X	(1 << FLAGBIT_X)
+
+#define SET_ZFLG(y)	(regflags.cznv = (regflags.cznv & ~FLAGVAL_Z) | (((y) ? 1 : 0) << FLAGBIT_Z))
+#define SET_CFLG(y)	(regflags.cznv = (regflags.cznv & ~FLAGVAL_C) | (((y) ? 1 : 0) << FLAGBIT_C))
+#define SET_VFLG(y)	(regflags.cznv = (regflags.cznv & ~FLAGVAL_V) | (((y) ? 1 : 0) << FLAGBIT_V))
+#define SET_NFLG(y)	(regflags.cznv = (regflags.cznv & ~FLAGVAL_N) | (((y) ? 1 : 0) << FLAGBIT_N))
+#define SET_XFLG(y)	(regflags.x    = ((y) ? 1 : 0) << FLAGBIT_X)
+
+#define GET_ZFLG()	((regflags.cznv >> FLAGBIT_Z) & 1)
+#define GET_CFLG()	((regflags.cznv >> FLAGBIT_C) & 1)
+#define GET_VFLG()	((regflags.cznv >> FLAGBIT_V) & 1)
+#define GET_NFLG()	((regflags.cznv >> FLAGBIT_N) & 1)
+#define GET_XFLG()	((regflags.x    >> FLAGBIT_X) & 1)
+
+#define CLEAR_CZNV()	(regflags.cznv  = 0)
+#define GET_CZNV()	(regflags.cznv)
+#define IOR_CZNV(X)	(regflags.cznv |= (X))
+#define SET_CZNV(X)	(regflags.cznv  = (X))
+
+#define COPY_CARRY() (regflags.x = regflags.cznv)
+
+
+/*
+ * Test CCR condition
+ */
+STATIC_INLINE int cctrue (int cc)
+{
+    uae_u32 cznv = regflags.cznv;
+
+    switch (cc) {
+	case 0:  return 1;								/*				T  */
+	case 1:  return 0;								/*				F  */
+	case 2:  return (cznv & (FLAGVAL_C | FLAGVAL_Z)) == 0;				/* !CFLG && !ZFLG		HI */
+	case 3:  return (cznv & (FLAGVAL_C | FLAGVAL_Z)) != 0;				/*  CFLG || ZFLG		LS */
+	case 4:  return (cznv & FLAGVAL_C) == 0;					/* !CFLG			CC */
+	case 5:  return (cznv & FLAGVAL_C) != 0;					/*  CFLG			CS */
+	case 6:  return (cznv & FLAGVAL_Z) == 0;					/* !ZFLG			NE */
+	case 7:  return (cznv & FLAGVAL_Z) != 0;					/*  ZFLG			EQ */
+	case 8:  return (cznv & FLAGVAL_V) == 0;					/* !VFLG			VC */
+	case 9:  return (cznv & FLAGVAL_V) != 0;					/*  VFLG			VS */
+	case 10: return (cznv & FLAGVAL_N) == 0;					/* !NFLG			PL */
+	case 11: return (cznv & FLAGVAL_N) != 0;					/*  NFLG			MI */
+	case 12: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) == 0;	/*  NFLG == VFLG		GE */
+	case 13: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) != 0;	/*  NFLG != VFLG		LT */
+	case 14: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V);				/* ZFLG && (NFLG == VFLG)	GT */
+		 return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) == 0;
+	case 15: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V);				/* ZFLG && (NFLG != VFLG)	LE */
+		 return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) != 0;
+    }
+    return 0;
+}
diff --git a/src/cpu/maccess.h b/src/cpu/maccess.h
new file mode 100644
index 0000000..f4ab60a
--- /dev/null
+++ b/src/cpu/maccess.h
@@ -0,0 +1,113 @@
+ /*
+  * UAE - The Un*x Amiga Emulator - CPU core
+  *
+  * Big endian memory access functions.
+  *
+  * Copyright 1996 Bernd Schmidt
+  *
+  * Adaptation to Hatari by Thomas Huth, Eero Tamminen
+  *
+  * This file is distributed under the GNU General Public License, version 2
+  * or at your option any later version. Read the file gpl.txt for details.
+  */
+
+#ifndef UAE_MACCESS_H
+#define UAE_MACCESS_H
+
+
+/* Can the actual CPU access unaligned memory? */
+#ifndef CPU_CAN_ACCESS_UNALIGNED
+# if defined(__i386__) || defined(powerpc) || defined(__mc68020__)
+#  define CPU_CAN_ACCESS_UNALIGNED 1
+# else
+#  define CPU_CAN_ACCESS_UNALIGNED 0
+# endif
+#endif
+
+
+/* If the CPU can access unaligned memory, use these accelerated functions: */
+#if CPU_CAN_ACCESS_UNALIGNED
+
+#include 
+
+
+static inline uae_u32 do_get_mem_long(void *a)
+{
+	return SDL_SwapBE32(*(uae_u32 *)a);
+}
+
+static inline uae_u16 do_get_mem_word(void *a)
+{
+	return SDL_SwapBE16(*(uae_u16 *)a);
+}
+
+
+static inline void do_put_mem_long(void *a, uae_u32 v)
+{
+	*(uae_u32 *)a = SDL_SwapBE32(v);
+}
+
+static inline void do_put_mem_word(void *a, uae_u16 v)
+{
+	*(uae_u16 *)a = SDL_SwapBE16(v);
+}
+
+
+#else  /* Cpu can not access unaligned memory: */
+
+
+static inline uae_u32 do_get_mem_long(void *a)
+{
+	uae_u8 *b = (uae_u8 *)a;
+
+	return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
+}
+
+static inline uae_u16 do_get_mem_word(void *a)
+{
+	uae_u8 *b = (uae_u8 *)a;
+
+	return (b[0] << 8) | b[1];
+}
+
+
+static inline void do_put_mem_long(void *a, uae_u32 v)
+{
+	uae_u8 *b = (uae_u8 *)a;
+
+	b[0] = v >> 24;
+	b[1] = v >> 16;    
+	b[2] = v >> 8;
+	b[3] = v;
+}
+
+static inline void do_put_mem_word(void *a, uae_u16 v)
+{
+	uae_u8 *b = (uae_u8 *)a;
+
+	b[0] = v >> 8;
+	b[1] = v;
+}
+
+
+#endif  /* CPU_CAN_ACCESS_UNALIGNED */
+
+
+/* These are same for all architectures: */
+
+static inline uae_u8 do_get_mem_byte(uae_u8 *a)
+{
+	return *a;
+}
+
+static inline void do_put_mem_byte(uae_u8 *a, uae_u8 v)
+{
+	*a = v;
+}
+
+
+#define call_mem_get_func(func, addr) ((*func)(addr))
+#define call_mem_put_func(func, addr, v) ((*func)(addr, v))
+
+
+#endif /* UAE_MACCESS_H */
diff --git a/src/cpu/md-fpp.h b/src/cpu/md-fpp.h
new file mode 100644
index 0000000..d7cb788
--- /dev/null
+++ b/src/cpu/md-fpp.h
@@ -0,0 +1,243 @@
+ /*
+  * UAE - The Un*x Amiga Emulator
+  *
+  * MC68881 emulation
+  *
+  * Conversion routines for hosts knowing floating point format.
+  *
+  * Copyright 1996 Herman ten Brugge
+  * Modified 2005 Peter Keunecke
+  */
+
+#define	FPCR_ROUNDING_MODE	0x00000030
+#define	FPCR_ROUND_NEAR		0x00000000
+#define	FPCR_ROUND_ZERO		0x00000010
+#define	FPCR_ROUND_MINF		0x00000020
+#define	FPCR_ROUND_PINF		0x00000030
+
+#define	FPCR_ROUNDING_PRECISION	0x000000c0
+#define	FPCR_PRECISION_SINGLE	0x00000040
+#define	FPCR_PRECISION_DOUBLE	0x00000080
+#define FPCR_PRECISION_EXTENDED	0x00000000
+
+extern void to_single(fpdata *fpd, uae_u32 value);
+extern void to_double(fpdata *fpd, uae_u32 wrd1, uae_u32 wrd2);
+extern void to_exten(fpdata *fpd, uae_u32 wrd1, uae_u32 wrd2, uae_u32 wrd3);
+
+STATIC_INLINE void exten_zeronormalize(uae_u32 *pwrd1, uae_u32 *pwrd2, uae_u32 *pwrd3)
+{
+	uae_u32 wrd1 = *pwrd1;
+	uae_u32 wrd2 = *pwrd2;
+	uae_u32 wrd3 = *pwrd3;
+	int exp = (wrd1 >> 16) & 0x7fff;
+	// Force zero if mantissa is zero but exponent is non-zero
+	// M68k FPU automatically convert them to plain zeros.
+	// x86 FPU considers them invalid values
+	if (exp != 0 && exp != 0x7fff && !wrd2 && !wrd3) {
+		*pwrd1 = (wrd1 & 0x80000000);
+	}
+}
+
+#if USE_LONG_DOUBLE
+STATIC_INLINE void to_exten_x(fptype *fp, uae_u32 wrd1, uae_u32 wrd2, uae_u32 wrd3)
+{
+	// force correct long double alignment
+	union
+	{
+		long double lf;
+		uae_u32 longarray[3];
+	} uld;
+	exten_zeronormalize(&wrd1, &wrd2, &wrd3);
+	// little endian order
+	uld.longarray[0] = wrd3;
+	uld.longarray[1] = wrd2;
+	uld.longarray[2] = wrd1 >> 16;
+	long double *longdoublewords = (long double *)uld.longarray;
+	*fp = *longdoublewords;
+}
+#define HAVE_to_exten
+
+STATIC_INLINE void from_exten_x(fptype fp, uae_u32 * wrd1, uae_u32 * wrd2, uae_u32 * wrd3)
+{
+	uae_u32 *longarray = (uae_u32 *)&fp;
+	uae_u16 *finalword = (uae_u16 *)(((uae_u8*)&fp) + 8);
+
+	*wrd1 = finalword[0] << 16;
+	*wrd2 = longarray[1];
+	*wrd3 = longarray[0]; // little endian
+}
+#define HAVE_from_exten
+#endif /* USE_LONG_DOUBLE */
+
+#if defined(X86_MSVC_ASSEMBLY_FPU)
+#ifndef HAVE_to_single
+#define HAVE_to_single
+STATIC_INLINE double to_single_x (uae_u32 longvalue)
+{
+	double floatfake;
+
+	__asm {
+		fld dword ptr longvalue;
+		fstp qword ptr floatfake;
+	}
+	return floatfake;
+}
+#endif
+
+#ifndef HAVE_from_single
+#define HAVE_from_single
+STATIC_INLINE uae_u32 from_single_x (double floatfake)
+{
+	uae_u32 longvalue;
+
+	__asm {
+		fld qword ptr floatfake;
+		fstp dword ptr longvalue;
+	}
+	return longvalue;
+}
+#endif
+
+#ifndef HAVE_to_exten
+#define HAVE_to_exten
+STATIC_INLINE void to_exten_x(fptype *fp, uae_u32 wrd1, uae_u32 wrd2, uae_u32 wrd3)
+{
+	uae_u32 longarray[3];
+	double  extenfake;
+
+	exten_normalize(&wrd1, &wrd2, &wrd3);
+	longarray[0] = wrd3; // littlen endian
+	longarray[1] = wrd2;
+	longarray[2] = wrd2 >> 16;
+
+	__asm {
+		fld tbyte ptr longarray;
+		fstp qword ptr extenfake;
+	}
+	*fp = extenfake;
+}
+#endif
+
+#ifndef HAVE_from_exten
+#define HAVE_from_exten
+STATIC_INLINE void from_exten_x(fptype fp, uae_u32 * wrd1, uae_u32 * wrd2, uae_u32 * wrd3)
+{
+	fptype src = fp;
+	uae_u32 longarray[3], *srcarray = (uae_u32 *)&src;
+	__asm {
+		fld qword ptr src;
+		fstp tbyte ptr longarray;
+	}
+	*wrd1 = (longarray[2] & 0xffff) <<16;
+	*wrd2 =  longarray[1];
+	*wrd3 =  longarray[0]; // little endian
+	if (!srcarray[0] && (srcarray[1] == 0x7ff00000 || srcarray[1] == 0xfff00000))
+		*wrd2 = 0; // The MSB of the mantissa was set wrongly for infinity, causing a NaN
+}
+#endif
+#endif /* X86_MSVC_ASSEMBLY */
+
+#ifndef HAVE_to_single
+#define HAVE_to_single
+STATIC_INLINE double to_single_x (uae_u32 value)
+{
+	union {
+		float f;
+		uae_u32 u;
+	} val;
+
+	val.u = value;
+	return val.f;
+}
+#endif
+
+#ifndef HAVE_from_single
+#define HAVE_from_single
+STATIC_INLINE uae_u32 from_single_x (double src)
+{
+	union {
+		float f;
+		uae_u32 u;
+	} val;
+
+	val.f = (float) src;
+	return val.u;
+}
+#endif
+
+#ifndef HAVE_to_double
+#define HAVE_to_double
+STATIC_INLINE double to_double_x(uae_u32 wrd1, uae_u32 wrd2)
+{
+	union {
+		double d;
+		uae_u32 u[2];
+	} val;
+
+	val.u[0] = wrd2; // little endian
+	val.u[1] = wrd1;
+	return val.d;
+}
+#endif
+
+#ifndef HAVE_from_double
+#define HAVE_from_double
+STATIC_INLINE void from_double_x(double src, uae_u32 * wrd1, uae_u32 * wrd2)
+{
+	uae_u32 *longarray = (uae_u32 *)&src;
+
+	*wrd1 = longarray[1]; // little endian
+	*wrd2 = longarray[0];
+}
+#endif
+
+static const double twoto32 = 4294967296.0;
+#ifndef HAVE_to_exten
+#define HAVE_to_exten
+STATIC_INLINE void to_exten_x(fptype *fp, uae_u32 wrd1, uae_u32 wrd2, uae_u32 wrd3)
+{
+	double frac;
+	exten_zeronormalize(&wrd1, &wrd2, &wrd3);
+	if ((wrd1 & 0x7fff0000) == 0 && wrd2 == 0 && wrd3 == 0) {
+		*fp = (wrd1 & 0x80000000) ? -0.0 : +0.0;
+		return;
+	}
+	frac = ((double)wrd2 + ((double)wrd3 / twoto32)) / 2147483648.0;
+	if (wrd1 & 0x80000000)
+		frac = -frac;
+	*fp = ldexp (frac, ((wrd1 >> 16) & 0x7fff) - 16383);
+}
+#endif
+
+#ifndef HAVE_from_exten
+#define HAVE_from_exten
+STATIC_INLINE void from_exten_x(fptype fp, uae_u32 * wrd1, uae_u32 * wrd2, uae_u32 * wrd3)
+{
+	int expon;
+	double frac;
+	fptype v;
+
+	v = fp;
+	if (v == 0.0) {
+		*wrd1 = signbit(v) ? 0x80000000 : 0;
+		*wrd2 = 0;
+		*wrd3 = 0;
+		return;
+	}
+	if (v < 0) {
+		*wrd1 = 0x80000000;
+		v = -v;
+	} else {
+		*wrd1 = 0;
+	}
+	frac = frexp (v, &expon);
+	frac += 0.5 / (twoto32 * twoto32);
+	if (frac >= 1.0) {
+		frac /= 2.0;
+		expon++;
+	}
+	*wrd1 |= (((expon + 16383 - 1) & 0x7fff) << 16);
+	*wrd2 = (uae_u32) (frac * twoto32);
+	*wrd3 = (uae_u32) ((frac * twoto32 - *wrd2) * twoto32);
+}
+#endif
diff --git a/src/cpu/memory.c b/src/cpu/memory.c
new file mode 100644
index 0000000..cc6d098
--- /dev/null
+++ b/src/cpu/memory.c
@@ -0,0 +1,1582 @@
+ /*
+  * UAE - The Un*x Amiga Emulator - CPU core
+  *
+  * Memory management
+  *
+  * (c) 1995 Bernd Schmidt
+  *
+  * Adaptation to Hatari by Thomas Huth
+  *
+  * This file is distributed under the GNU General Public License, version 2
+  * or at your option any later version. Read the file gpl.txt for details.
+  */
+const char Memory_fileid[] = "Hatari memory.c : " __DATE__ " " __TIME__;
+
+#include 
+#include "config.h"
+#include "sysdeps.h"
+#include "hatari-glue.h"
+#include "maccess.h"
+#include "memory.h"
+
+#include "main.h"
+#include "tos.h"
+#include "ide.h"
+#include "ioMem.h"
+#include "reset.h"
+#include "stMemory.h"
+#include "m68000.h"
+#include "configuration.h"
+
+#include "newcpu.h"
+
+
+/* Set illegal_mem to 1 for debug output: */
+#define illegal_mem 1
+
+static int illegal_count = 50;
+
+static uae_u32 STmem_size;
+uae_u32 TTmem_size = 0;
+static uae_u32 TTmem_mask;
+
+#define STmem_start  0x00000000
+#define ROMmem_start 0x00E00000
+#define IdeMem_start 0x00F00000
+#define IOmem_start  0x00FF0000
+#define TTmem_start  0x01000000			/* TOS 3 and TOS 4 always expect extra RAM at this address */
+#define TTmem_end    0x80000000			/* Max value for end of TT ram, which gives 2047 MB */
+
+#define IdeMem_size  65536
+#define IOmem_size  65536
+#define ROMmem_size (0x00FF0000 - 0x00E00000)  /* So we cover both possible ROM regions + cartridge */
+
+#define STmem_mask  0x00ffffff
+#define ROMmem_mask 0x00ffffff
+#define IdeMem_mask  (IdeMem_size - 1)
+#define IOmem_mask  (IOmem_size - 1)
+
+/* Some prototypes: */
+static int STmem_check (uaecptr addr, uae_u32 size) REGPARAM;
+static uae_u8 *STmem_xlate (uaecptr addr) REGPARAM;
+
+
+
+#ifdef WINUAE_FOR_HATARI
+#undef NATMEM_OFFSET
+#endif
+
+#ifdef NATMEM_OFFSET
+bool canbang;
+int candirect = -1;
+#endif
+
+#ifdef JIT
+/* Set by each memory handler that does not simply access real memory. */
+int special_mem;
+#endif
+
+#ifdef NATMEM_OFFSET
+static bool isdirectjit (void)
+{
+	return currprefs.cachesize && !currprefs.comptrustbyte;
+}
+
+static bool canjit (void)
+{
+	if (currprefs.cpu_model < 68020 || currprefs.address_space_24)
+		return false;
+	return true;
+}
+static bool needmman (void)
+{
+	if (!currprefs.jit_direct_compatible_memory)
+		return false;
+#ifdef _WIN32
+	return true;
+#endif
+	if (canjit ())
+		return true;
+	return false;
+}
+
+static void nocanbang (void)
+{
+	canbang = 0;
+}
+#endif
+
+uae_u8 ce_banktype[65536];
+uae_u8 ce_cachable[65536];
+
+
+/* The address space setting used during the last reset.  */
+static bool last_address_space_24;
+
+addrbank *mem_banks[MEMORY_BANKS];
+
+/* This has two functions. It either holds a host address that, when added
+to the 68k address, gives the host address corresponding to that 68k
+address (in which case the value in this array is even), OR it holds the
+same value as mem_banks, for those banks that have baseaddr==0. In that
+case, bit 0 is set (the memory access routines will take care of it).  */
+
+uae_u8 *baseaddr[MEMORY_BANKS];
+
+#ifdef NO_INLINE_MEMORY_ACCESS
+__inline__ uae_u32 longget (uaecptr addr)
+{
+	return call_mem_get_func (get_mem_bank (addr).lget, addr);
+}
+__inline__ uae_u32 wordget (uaecptr addr)
+{
+	return call_mem_get_func (get_mem_bank (addr).wget, addr);
+}
+__inline__ uae_u32 byteget (uaecptr addr)
+{
+	return call_mem_get_func (get_mem_bank (addr).bget, addr);
+}
+__inline__ void longput (uaecptr addr, uae_u32 l)
+{
+	call_mem_put_func (get_mem_bank (addr).lput, addr, l);
+}
+__inline__ void wordput (uaecptr addr, uae_u32 w)
+{
+	call_mem_put_func (get_mem_bank (addr).wput, addr, w);
+}
+__inline__ void byteput (uaecptr addr, uae_u32 b)
+{
+	call_mem_put_func (get_mem_bank (addr).bput, addr, b);
+}
+#endif
+
+int addr_valid (const TCHAR *txt, uaecptr addr, uae_u32 len)
+{
+	addrbank *ab = &get_mem_bank(addr);
+	if (ab == 0 || !(ab->flags & (ABFLAG_RAM | ABFLAG_ROM)) || addr < 0x100 || len > 16777215 || !valid_address (addr, len)) {
+		write_log (_T("corrupt %s pointer %x (%d) detected!\n"), txt, addr, len);
+		return 0;
+	}
+	return 1;
+}
+
+static int illegal_count;
+
+static uae_u32 REGPARAM3 dummy_lget (uaecptr) REGPARAM;
+static uae_u32 REGPARAM3 dummy_wget (uaecptr) REGPARAM;
+static uae_u32 REGPARAM3 dummy_bget (uaecptr) REGPARAM;
+static void REGPARAM3 dummy_lput (uaecptr, uae_u32) REGPARAM;
+static void REGPARAM3 dummy_wput (uaecptr, uae_u32) REGPARAM;
+static void REGPARAM3 dummy_bput (uaecptr, uae_u32) REGPARAM;
+static int REGPARAM3 dummy_check (uaecptr addr, uae_u32 size) REGPARAM;
+
+#define	MAX_ILG 200
+#define NONEXISTINGDATA 0
+//#define NONEXISTINGDATA 0xffffffff
+
+
+
+
+static void print_illegal_counted(const char *txt, uaecptr addr)
+{
+    if (!illegal_mem || illegal_count <= 0)
+        return;
+
+    write_log("%s at %08lx\n", txt, (long)addr);
+    if (--illegal_count == 0)
+        write_log("Suppressing further messages about illegal memory accesses.\n");
+}
+
+
+/* **** A dummy bank that only contains zeros **** */
+/* TODO [NP] : in many cases, we should not return 0 but a value depending on the data */
+/* last accessed on the bus */
+
+static void dummylog (int rw, uaecptr addr, int size, uae_u32 val, int ins)
+{
+#ifndef WINUAE_FOR_HATARI
+	if (illegal_count >= MAX_ILG && MAX_ILG > 0)
+		return;
+	/* ignore Zorro3 expansion space */
+	if (addr >= 0xff000000 && addr <= 0xff000200)
+		return;
+	/* autoconfig and extended rom */
+	if (addr >= 0xe00000 && addr <= 0xf7ffff)
+		return;
+	/* motherboard ram */
+	if (addr >= 0x08000000 && addr <= 0x08000007)
+		return;
+	if (addr >= 0x07f00000 && addr <= 0x07f00007)
+		return;
+	if (addr >= 0x07f7fff0 && addr <= 0x07ffffff)
+		return;
+	if (MAX_ILG >= 0)
+		illegal_count++;
+#endif
+	if (ins) {
+		write_log (_T("WARNING: Illegal opcode %cget at %08x PC=%x\n"),
+			size == 2 ? 'w' : 'l', addr, M68K_GETPC);
+	} else if (rw) {
+		write_log (_T("Illegal %cput at %08x=%08x PC=%x\n"),
+			size == 1 ? 'b' : size == 2 ? 'w' : 'l', addr, val, M68K_GETPC);
+	} else {
+		write_log (_T("Illegal %cget at %08x PC=%x\n"),
+			size == 1 ? 'b' : size == 2 ? 'w' : 'l', addr, M68K_GETPC);
+	}
+}
+
+void dummy_put (uaecptr addr, int size, uae_u32 val)
+{
+#ifndef WINUAE_FOR_HATARI
+#if FLASHEMU
+	if (addr >= 0xf00000 && addr < 0xf80000 && size < 2)
+		flash_write(addr, val);
+#endif
+	if (gary_nonrange(addr) || (size > 1 && gary_nonrange(addr + size - 1))) {
+		if (gary_timeout)
+			gary_wait (addr, size, true);
+		if (gary_toenb && currprefs.mmu_model)
+			exception2 (addr, true, size, regs.s ? 4 : 0);
+	}
+
+#else
+	/* Hatari : do nothing in case of dummy_put */
+#endif
+}
+
+uae_u32 dummy_get (uaecptr addr, int size, bool inst)
+{
+	uae_u32 v = NONEXISTINGDATA;
+
+#ifndef WINUAE_FOR_HATARI
+#if FLASHEMU
+	if (addr >= 0xf00000 && addr < 0xf80000 && size < 2) {
+		if (addr < 0xf60000)
+			return flash_read(addr);
+		return 8;
+	}
+#endif
+
+	if (gary_nonrange(addr) || (size > 1 && gary_nonrange(addr + size - 1))) {
+		if (gary_timeout)
+			gary_wait (addr, size, false);
+		if (gary_toenb)
+			exception2 (addr, false, size, (regs.s ? 4 : 0) | (inst ? 0 : 1));
+		return v;
+	}
+
+	if (currprefs.cpu_model >= 68040)
+		return v;
+	if (!currprefs.cpu_compatible)
+		return v;
+	if (currprefs.address_space_24)
+		addr &= 0x00ffffff;
+	if (addr >= 0x10000000)
+		return v;
+	if ((currprefs.cpu_model <= 68010) || (currprefs.cpu_model == 68020 && (currprefs.chipset_mask & CSMASK_AGA) && currprefs.address_space_24)) {
+		if (size == 4) {
+			v = regs.db & 0xffff;
+			if (addr & 1)
+				v = (v << 8) | (v >> 8);
+			v = (v << 16) | v;
+		} else if (size == 2) {
+			v = regs.db & 0xffff;
+			if (addr & 1)
+				v = (v << 8) | (v >> 8);
+		} else {
+			v = regs.db;
+			v = (addr & 1) ? (v & 0xff) : ((v >> 8) & 0xff);
+		}
+	}
+#if 0
+	if (addr >= 0x10000000)
+		write_log (_T("%08X %d = %08x\n"), addr, size, v);
+#endif
+
+#else
+	/* Hatari : TODO returns 0 for now, but we should use last databus value */
+	v = 0;
+#endif
+	return v;
+}
+
+static uae_u32 REGPARAM2 dummy_lget (uaecptr addr)
+{
+#ifdef JIT
+	special_mem |= S_READ;
+#endif
+	if (illegal_mem)
+		dummylog (0, addr, 4, 0, 0);
+	return dummy_get (addr, 4, false);
+}
+uae_u32 REGPARAM2 dummy_lgeti (uaecptr addr)
+{
+#ifdef JIT
+	special_mem |= S_READ;
+#endif
+	if (illegal_mem)
+		dummylog (0, addr, 4, 0, 1);
+	return dummy_get (addr, 4, true);
+}
+
+static uae_u32 REGPARAM2 dummy_wget (uaecptr addr)
+{
+#ifdef JIT
+	special_mem |= S_READ;
+#endif
+#if 0
+	if (addr == 0xb0b000) {
+		extern uae_u16 isideint(void);
+		return isideint();
+	}
+#endif
+	if (illegal_mem)
+		dummylog (0, addr, 2, 0, 0);
+	return dummy_get (addr, 2, false);
+}
+uae_u32 REGPARAM2 dummy_wgeti (uaecptr addr)
+{
+#ifdef JIT
+	special_mem |= S_READ;
+#endif
+	if (illegal_mem)
+		dummylog (0, addr, 2, 0, 1);
+	return dummy_get (addr, 2, true);
+}
+
+static uae_u32 REGPARAM2 dummy_bget (uaecptr addr)
+{
+#ifdef JIT
+	special_mem |= S_READ;
+#endif
+	if (illegal_mem)
+		dummylog (0, addr, 1, 0, 0);
+	return dummy_get (addr, 1, false);
+}
+
+static void REGPARAM2 dummy_lput (uaecptr addr, uae_u32 l)
+{
+#ifdef JIT
+	special_mem |= S_WRITE;
+#endif
+	if (illegal_mem)
+		dummylog (1, addr, 4, l, 0);
+	dummy_put (addr, 4, l);
+}
+static void REGPARAM2 dummy_wput (uaecptr addr, uae_u32 w)
+{
+#ifdef JIT
+	special_mem |= S_WRITE;
+#endif
+	if (illegal_mem)
+		dummylog (1, addr, 2, w, 0);
+	dummy_put (addr, 2, w);
+}
+static void REGPARAM2 dummy_bput (uaecptr addr, uae_u32 b)
+{
+#ifdef JIT
+	special_mem |= S_WRITE;
+#endif
+	if (illegal_mem)
+		dummylog (1, addr, 1, b, 0);
+	dummy_put (addr, 1, b);
+}
+
+static int REGPARAM2 dummy_check (uaecptr addr, uae_u32 size)
+{
+#ifdef JIT
+	special_mem |= S_READ;
+#endif
+	return 0;
+}
+
+static uae_u8 *dummy_xlate(uaecptr addr)
+{
+    write_log("Your Atari program just did something terribly stupid:"
+              " dummy_xlate($%x)\n", addr);
+    /*Reset_Warm();*/
+    return STmem_xlate(addr);  /* So we don't crash. */
+}
+
+
+#ifndef WINUAE_FOR_HATARI
+static void REGPARAM2 none_put (uaecptr addr, uae_u32 v)
+{
+#ifdef JIT
+	special_mem |= S_WRITE;
+#endif
+}
+static uae_u32 REGPARAM2 ones_get (uaecptr addr)
+{
+#ifdef JIT
+	special_mem |= S_READ;
+#endif
+	return 0xffffffff;
+}
+
+addrbank *get_sub_bank(uaecptr *paddr)
+{
+	int i;
+	uaecptr addr = *paddr;
+	addrbank *ab = &get_mem_bank(addr);
+	struct addrbank_sub *sb = ab->sub_banks;
+	if (!sb)
+		return &dummy_bank;
+	for (i = 0; sb[i].bank; i++) {
+		int offset = addr & 65535;
+		if (offset < sb[i + 1].offset) {
+			uae_u32 mask = sb[i].mask;
+			uae_u32 maskval = sb[i].maskval;
+			if ((offset & mask) == maskval) {
+				*paddr = addr - sb[i].suboffset;
+				return sb[i].bank;
+			}
+		}
+	}
+	*paddr = addr - sb[i - 1].suboffset;
+	return sb[i - 1].bank;
+}
+uae_u32 REGPARAM3 sub_bank_lget (uaecptr addr) REGPARAM
+{
+	addrbank *ab = get_sub_bank(&addr);
+	return ab->lget(addr);
+}
+uae_u32 REGPARAM3 sub_bank_wget(uaecptr addr) REGPARAM
+{
+	addrbank *ab = get_sub_bank(&addr);
+	return ab->wget(addr);
+}
+uae_u32 REGPARAM3 sub_bank_bget(uaecptr addr) REGPARAM
+{
+	addrbank *ab = get_sub_bank(&addr);
+	return ab->bget(addr);
+}
+void REGPARAM3 sub_bank_lput(uaecptr addr, uae_u32 v) REGPARAM
+{
+	addrbank *ab = get_sub_bank(&addr);
+	ab->lput(addr, v);
+}
+void REGPARAM3 sub_bank_wput(uaecptr addr, uae_u32 v) REGPARAM
+{
+	addrbank *ab = get_sub_bank(&addr);
+	ab->wput(addr, v);
+}
+void REGPARAM3 sub_bank_bput(uaecptr addr, uae_u32 v) REGPARAM
+{
+	addrbank *ab = get_sub_bank(&addr);
+	
+/* last accessed on the bus */ab->bput(addr, v);
+}
+uae_u32 REGPARAM3 sub_bank_lgeti(uaecptr addr) REGPARAM
+{
+	addrbank *ab = get_sub_bank(&addr);
+	return ab->lgeti(addr);
+}
+uae_u32 REGPARAM3 sub_bank_wgeti(uaecptr addr) REGPARAM
+{
+	addrbank *ab = get_sub_bank(&addr);
+	return ab->wgeti(addr);
+}
+int REGPARAM3 sub_bank_check(uaecptr addr, uae_u32 size) REGPARAM
+{
+	addrbank *ab = get_sub_bank(&addr);
+	return ab->check(addr, size);
+}
+uae_u8 *REGPARAM3 sub_bank_xlate(uaecptr addr) REGPARAM
+{
+	addrbank *ab = get_sub_bank(&addr);
+	return ab->xlateaddr(addr);
+}
+#endif
+
+
+/* **** This memory bank only generates bus errors **** */
+
+static uae_u32 BusErrMem_lget(uaecptr addr)
+{
+    print_illegal_counted("Bus error lget", addr);
+
+    M68000_BusError(addr, 1, BUS_ERROR_SIZE_LONG, BUS_ERROR_ACCESS_DATA);
+    return 0;
+}
+
+static uae_u32 BusErrMem_wget(uaecptr addr)
+{
+    print_illegal_counted("Bus error wget", addr);
+
+    M68000_BusError(addr, 1, BUS_ERROR_SIZE_WORD, BUS_ERROR_ACCESS_DATA);
+    return 0;
+}
+
+static uae_u32 BusErrMem_bget(uaecptr addr)
+{
+    print_illegal_counted("Bus error bget", addr);
+
+    M68000_BusError(addr, 1, BUS_ERROR_SIZE_BYTE, BUS_ERROR_ACCESS_DATA);
+    return 0;
+}
+
+static void BusErrMem_lput(uaecptr addr, uae_u32 l)
+{
+    print_illegal_counted("Bus error lput", addr);
+
+    M68000_BusError(addr, 0, BUS_ERROR_SIZE_LONG, BUS_ERROR_ACCESS_DATA);
+}
+
+static void BusErrMem_wput(uaecptr addr, uae_u32 w)
+{
+    print_illegal_counted("Bus error wput", addr);
+
+    M68000_BusError(addr, 0, BUS_ERROR_SIZE_WORD, BUS_ERROR_ACCESS_DATA);
+}
+
+static void BusErrMem_bput(uaecptr addr, uae_u32 b)
+{
+    print_illegal_counted("Bus error bput", addr);
+
+    M68000_BusError(addr, 0, BUS_ERROR_SIZE_BYTE, BUS_ERROR_ACCESS_DATA);
+}
+
+static int BusErrMem_check(uaecptr addr, uae_u32 size)
+{
+    if (illegal_mem)
+	write_log ("Bus error check at %08lx\n", (long)addr);
+
+    return 0;
+}
+
+static uae_u8 *BusErrMem_xlate (uaecptr addr)
+{
+    write_log("Your Atari program just did something terribly stupid:"
+              " BusErrMem_xlate($%x)\n", addr);
+
+    /*M68000_BusError(addr);*/
+    return STmem_xlate(addr);  /* So we don't crash. */
+}
+
+
+/* **** ST RAM memory **** */
+
+/*static uae_u8 *STmemory;*/
+#define STmemory STRam
+
+static uae_u32 STmem_lget(uaecptr addr)
+{
+    addr -= STmem_start & STmem_mask;
+    addr &= STmem_mask;
+    return do_get_mem_long(STmemory + addr);
+}
+
+static uae_u32 STmem_wget(uaecptr addr)
+{
+    addr -= STmem_start & STmem_mask;
+    addr &= STmem_mask;
+    return do_get_mem_word(STmemory + addr);
+}
+
+static uae_u32 STmem_bget(uaecptr addr)
+{
+    addr -= STmem_start & STmem_mask;
+    addr &= STmem_mask;
+    return STmemory[addr];
+}
+
+static void STmem_lput(uaecptr addr, uae_u32 l)
+{
+    addr -= STmem_start & STmem_mask;
+    addr &= STmem_mask;
+    do_put_mem_long(STmemory + addr, l);
+}
+
+static void STmem_wput(uaecptr addr, uae_u32 w)
+{
+    addr -= STmem_start & STmem_mask;
+    addr &= STmem_mask;
+    do_put_mem_word(STmemory + addr, w);
+}
+
+static void STmem_bput(uaecptr addr, uae_u32 b)
+{
+    addr -= STmem_start & STmem_mask;
+    addr &= STmem_mask;
+    STmemory[addr] = b;
+}
+
+static int STmem_check(uaecptr addr, uae_u32 size)
+{
+    addr -= STmem_start & STmem_mask;
+    addr &= STmem_mask;
+    return (addr + size) <= STmem_size;
+}
+
+static uae_u8 *STmem_xlate(uaecptr addr)
+{
+    addr -= STmem_start & STmem_mask;
+    addr &= STmem_mask;
+    return STmemory + addr;
+}
+
+
+/*
+ * **** ST RAM system memory ****
+ * We need a separate mem bank for this region since the first 0x800 bytes on
+ * the ST can only be accessed in supervisor mode. Note that the very first
+ * 8 bytes of the ST memory are also a mirror of the TOS ROM, so they are write
+ * protected!
+ */
+static uae_u32 SysMem_lget(uaecptr addr)
+{
+    addr -= STmem_start & STmem_mask;
+    addr &= STmem_mask;
+
+    if(addr < 0x800 && !regs.s)
+    {
+      M68000_BusError(addr, 1, BUS_ERROR_SIZE_LONG, BUS_ERROR_ACCESS_DATA);
+      return 0;
+    }
+
+    return do_get_mem_long(STmemory + addr);
+}
+
+static uae_u32 SysMem_wget(uaecptr addr)
+{
+    addr -= STmem_start & STmem_mask;
+    addr &= STmem_mask;
+
+    if(addr < 0x800 && !regs.s)
+    {
+      M68000_BusError(addr, 1, BUS_ERROR_SIZE_WORD, BUS_ERROR_ACCESS_DATA);
+      return 0;
+    }
+
+    return do_get_mem_word(STmemory + addr);
+}
+
+static uae_u32 SysMem_bget(uaecptr addr)
+{
+    addr -= STmem_start & STmem_mask;
+    addr &= STmem_mask;
+
+    if(addr < 0x800 && !regs.s)
+    {
+      M68000_BusError(addr, 1, BUS_ERROR_SIZE_BYTE, BUS_ERROR_ACCESS_DATA);
+      return 0;
+    }
+
+    return STmemory[addr];
+}
+
+static void SysMem_lput(uaecptr addr, uae_u32 l)
+{
+    addr -= STmem_start & STmem_mask;
+    addr &= STmem_mask;
+
+    if(addr < 0x8 || (addr < 0x800 && !regs.s))
+    {
+      M68000_BusError(addr, 0, BUS_ERROR_SIZE_LONG, BUS_ERROR_ACCESS_DATA);
+      return;
+    }
+
+    do_put_mem_long(STmemory + addr, l);
+}
+
+static void SysMem_wput(uaecptr addr, uae_u32 w)
+{
+    addr -= STmem_start & STmem_mask;
+    addr &= STmem_mask;
+
+    if(addr < 0x8 || (addr < 0x800 && !regs.s))
+    {
+      M68000_BusError(addr, 0, BUS_ERROR_SIZE_WORD, BUS_ERROR_ACCESS_DATA);
+      return;
+    }
+
+    do_put_mem_word(STmemory + addr, w);
+}
+
+static void SysMem_bput(uaecptr addr, uae_u32 b)
+{
+    addr -= STmem_start & STmem_mask;
+    addr &= STmem_mask;
+
+    if(addr < 0x8 || (addr < 0x800 && !regs.s))
+    {
+      M68000_BusError(addr, 0, BUS_ERROR_SIZE_BYTE, BUS_ERROR_ACCESS_DATA);
+      return;
+    }
+
+    STmemory[addr] = b;
+}
+
+
+/*
+ * **** Void memory ****
+ * Between the ST-RAM end and the 4 MB barrier, there is a void memory space:
+ * Reading always returns the same value and writing does nothing at all.
+ * [NP] : this is not correct, reading does not always return 0, when there's
+ * no memory, it will return the latest data that was read on the bus.
+ * In many cases, this will return the word that was just read in the 68000's
+ * prefetch register to decode the next opcode (tested on a real STF)
+ */
+
+static uae_u32 VoidMem_lget(uaecptr addr)
+{
+    return 0;
+}
+
+static uae_u32 VoidMem_wget(uaecptr addr)
+{
+    return 0;
+}
+
+static uae_u32 VoidMem_bget(uaecptr addr)
+{
+    return 0;
+}
+
+static void VoidMem_lput(uaecptr addr, uae_u32 l)
+{
+}
+
+static void VoidMem_wput(uaecptr addr, uae_u32 w)
+{
+}
+
+static void VoidMem_bput (uaecptr addr, uae_u32 b)
+{
+}
+
+static int VoidMem_check(uaecptr addr, uae_u32 size)
+{
+    if (illegal_mem)
+	write_log ("Void memory check at %08lx\n", (long)addr);
+
+    return 0;
+}
+
+static uae_u8 *VoidMem_xlate (uaecptr addr)
+{
+    write_log("Your Atari program just did something terribly stupid:"
+              " VoidMem_xlate($%x)\n", addr);
+
+    return STmem_xlate(addr);  /* So we don't crash. */
+}
+
+
+/* **** TT fast memory **** */
+
+uae_u8 *TTmemory;
+
+static uae_u32 TTmem_lget(uaecptr addr)
+{
+    addr -= TTmem_start & TTmem_mask;
+    addr &= TTmem_mask;
+    return do_get_mem_long(TTmemory + addr);
+}
+
+static uae_u32 TTmem_wget(uaecptr addr)
+{
+    addr -= TTmem_start & TTmem_mask;
+    addr &= TTmem_mask;
+    return do_get_mem_word(TTmemory + addr);
+}
+
+static uae_u32 TTmem_bget(uaecptr addr)
+{
+    addr -= TTmem_start & TTmem_mask;
+    addr &= TTmem_mask;
+    return TTmemory[addr];
+}
+
+static void TTmem_lput(uaecptr addr, uae_u32 l)
+{
+    addr -= TTmem_start & TTmem_mask;
+    addr &= TTmem_mask;
+    do_put_mem_long(TTmemory + addr, l);
+}
+
+static void TTmem_wput(uaecptr addr, uae_u32 w)
+{
+    addr -= TTmem_start & TTmem_mask;
+    addr &= TTmem_mask;
+    do_put_mem_word(TTmemory + addr, w);
+}
+
+static void TTmem_bput(uaecptr addr, uae_u32 b)
+{
+    addr -= TTmem_start & TTmem_mask;
+    addr &= TTmem_mask;
+    TTmemory[addr] = b;
+}
+
+static int TTmem_check(uaecptr addr, uae_u32 size)
+{
+    addr -= TTmem_start & TTmem_mask;
+    addr &= TTmem_mask;
+    return (addr + size) <= TTmem_size;
+}
+
+static uae_u8 *TTmem_xlate(uaecptr addr)
+{
+    addr -= TTmem_start & TTmem_mask;
+    addr &= TTmem_mask;
+    return TTmemory + addr;
+}
+
+
+/* **** ROM memory **** */
+
+uae_u8 *ROMmemory;
+
+static uae_u32 ROMmem_lget(uaecptr addr)
+{
+    addr -= ROMmem_start & ROMmem_mask;
+    addr &= ROMmem_mask;
+    return do_get_mem_long(ROMmemory + addr);
+}
+
+static uae_u32 ROMmem_wget(uaecptr addr)
+{
+    addr -= ROMmem_start & ROMmem_mask;
+    addr &= ROMmem_mask;
+    return do_get_mem_word(ROMmemory + addr);
+}
+
+static uae_u32 ROMmem_bget(uaecptr addr)
+{
+    addr -= ROMmem_start & ROMmem_mask;
+    addr &= ROMmem_mask;
+    return ROMmemory[addr];
+}
+
+static void ROMmem_lput(uaecptr addr, uae_u32 b)
+{
+    print_illegal_counted("Illegal ROMmem lput", addr);
+
+    M68000_BusError(addr, 0, BUS_ERROR_SIZE_LONG, BUS_ERROR_ACCESS_DATA);
+}
+
+static void ROMmem_wput(uaecptr addr, uae_u32 b)
+{
+    print_illegal_counted("Illegal ROMmem wput", addr);
+
+    M68000_BusError(addr, 0, BUS_ERROR_SIZE_WORD, BUS_ERROR_ACCESS_DATA);
+}
+
+static void ROMmem_bput(uaecptr addr, uae_u32 b)
+{
+    print_illegal_counted("Illegal ROMmem bput", addr);
+
+    M68000_BusError(addr, 0, BUS_ERROR_SIZE_BYTE, BUS_ERROR_ACCESS_DATA);
+}
+
+static int ROMmem_check(uaecptr addr, uae_u32 size)
+{
+    addr -= ROMmem_start & ROMmem_mask;
+    addr &= ROMmem_mask;
+    return (addr + size) <= ROMmem_size;
+}
+
+static uae_u8 *ROMmem_xlate(uaecptr addr)
+{
+    addr -= ROMmem_start & ROMmem_mask;
+    addr &= ROMmem_mask;
+    return ROMmemory + addr;
+}
+
+
+/* IDE controller IO memory */
+/* see also ide.c */
+
+static uae_u8 *IdeMemory;
+
+static int IdeMem_check(uaecptr addr, uae_u32 size)
+{
+    addr -= IdeMem_start;
+    addr &= IdeMem_mask;
+    return (addr + size) <= IdeMem_size;
+}
+
+static uae_u8 *IdeMem_xlate(uaecptr addr)
+{
+    addr -= IdeMem_start;
+    addr &= IdeMem_mask;
+    return IdeMemory + addr;
+}
+
+
+/* Hardware IO memory */
+/* see also ioMem.c */
+
+uae_u8 *IOmemory;
+
+static int IOmem_check(uaecptr addr, uae_u32 size)
+{
+    addr -= IOmem_start;
+    addr &= IOmem_mask;
+    return (addr + size) <= IOmem_size;
+}
+
+static uae_u8 *IOmem_xlate(uaecptr addr)
+{
+    addr -= IOmem_start;
+    addr &= IOmem_mask;
+    return IOmemory + addr;
+}
+
+
+
+/* **** Address banks **** */
+
+static addrbank dummy_bank =
+{
+    dummy_lget, dummy_wget, dummy_bget,
+    dummy_lput, dummy_wput, dummy_bput,
+    dummy_xlate, dummy_check, NULL, NULL, NULL,
+    dummy_lget, dummy_wget, ABFLAG_NONE
+//	dummy_lgeti, dummy_wgeti, ABFLAG_NONE
+};
+
+static addrbank BusErrMem_bank =
+{
+    BusErrMem_lget, BusErrMem_wget, BusErrMem_bget,
+    BusErrMem_lput, BusErrMem_wput, BusErrMem_bput,
+    BusErrMem_xlate, BusErrMem_check, NULL, "bus_err_mem" , "BusError memory",
+    BusErrMem_lget, BusErrMem_wget, ABFLAG_NONE
+};
+
+static addrbank STmem_bank =
+{
+    STmem_lget, STmem_wget, STmem_bget,
+    STmem_lput, STmem_wput, STmem_bput,
+    STmem_xlate, STmem_check, NULL, "st_mem" , "ST memory",
+    STmem_lget, STmem_wget, ABFLAG_RAM
+};
+
+static addrbank SysMem_bank =
+{
+    SysMem_lget, SysMem_wget, SysMem_bget,
+    SysMem_lput, SysMem_wput, SysMem_bput,
+    STmem_xlate, STmem_check, NULL, "sys_mem" , "Sys memory",
+    SysMem_lget, SysMem_wget, ABFLAG_RAM
+};
+
+static addrbank VoidMem_bank =
+{
+    VoidMem_lget, VoidMem_wget, VoidMem_bget,
+    VoidMem_lput, VoidMem_wput, VoidMem_bput,
+    VoidMem_xlate, VoidMem_check, NULL, "void_mem" , "Void memory",
+    VoidMem_lget, VoidMem_wget, ABFLAG_NONE
+};
+
+static addrbank TTmem_bank =
+{
+    TTmem_lget, TTmem_wget, TTmem_bget,
+    TTmem_lput, TTmem_wput, TTmem_bput,
+    TTmem_xlate, TTmem_check, NULL, "tt_mem" , "TT memory",
+    TTmem_lget, TTmem_wget, ABFLAG_RAM			/* NP TODO : use ABFLAG_RAM_TT for non DMA RAM */
+};
+
+static addrbank ROMmem_bank =
+{
+    ROMmem_lget, ROMmem_wget, ROMmem_bget,
+    ROMmem_lput, ROMmem_wput, ROMmem_bput,
+    ROMmem_xlate, ROMmem_check, NULL, "rom_mem" , "ROM memory",
+    ROMmem_lget, ROMmem_wget, ABFLAG_ROM
+};
+
+static addrbank IdeMem_bank =
+{
+    Ide_Mem_lget, Ide_Mem_wget, Ide_Mem_bget,
+    Ide_Mem_lput, Ide_Mem_wput, Ide_Mem_bput,
+    IdeMem_xlate, IdeMem_check, NULL, "ide_mem" , "IDE memory",
+    Ide_Mem_lget, Ide_Mem_wget, ABFLAG_IO
+};
+
+static addrbank IOmem_bank =
+{
+    IoMem_lget, IoMem_wget, IoMem_bget,
+    IoMem_lput, IoMem_wput, IoMem_bput,
+    IOmem_xlate, IOmem_check, NULL, "io_mem" , "IO memory",
+    IoMem_lget, IoMem_wget, ABFLAG_IO
+};
+
+
+#ifdef WINUAE_FOR_HATARI
+#undef NATMEM_OFFSET			/* Don't use shm in Hatari */
+#endif
+
+#ifndef NATMEM_OFFSET
+//extern uae_u8 *natmem_offset, *natmem_offset_end;
+
+bool mapped_malloc (addrbank *ab)
+{
+	ab->startmask = ab->start;
+	ab->baseaddr = xcalloc (uae_u8, ab->allocated + 4);
+	return ab->baseaddr != NULL; 
+}
+
+void mapped_free (addrbank *ab)
+{
+	xfree(ab->baseaddr);
+	ab->baseaddr = NULL; 
+}
+
+#else
+
+#include 
+#include 
+#include 
+#include 
+
+shmpiece *shm_start;
+
+static void dumplist (void)
+{
+	shmpiece *x = shm_start;
+	write_log (_T("Start Dump:\n"));
+	while (x) {
+		write_log (_T("this=%p,Native %p,id %d,prev=%p,next=%p,size=0x%08x\n"),
+			x, x->native_address, x->id, x->prev, x->next, x->size);
+		x = x->next;
+	}
+	write_log (_T("End Dump:\n"));
+}
+
+static shmpiece *find_shmpiece (uae_u8 *base, bool safe)
+{
+	shmpiece *x = shm_start;
+
+	while (x && x->native_address != base)
+		x = x->next;
+	if (!x) {
+#ifndef WINUAE_FOR_HATARI
+		if (safe || bogomem_aliasing)
+#else
+		if (safe)
+#endif
+			return 0;
+		write_log (_T("NATMEM: Failure to find mapping at %08X, %p\n"), base - NATMEM_OFFSET, base);
+		nocanbang ();
+		return 0;
+	}
+	return x;
+}
+
+static void delete_shmmaps (uae_u32 start, uae_u32 size)
+{
+	if (!needmman ())
+		return;
+
+	while (size) {
+		uae_u8 *base = mem_banks[bankindex (start)]->baseaddr;
+		if (base) {
+			shmpiece *x;
+			//base = ((uae_u8*)NATMEM_OFFSET)+start;
+
+			x = find_shmpiece (base, true);
+			if (!x)
+				return;
+
+			if (x->size > size) {
+				if (isdirectjit ())
+					write_log (_T("NATMEM WARNING: size mismatch mapping at %08x (size %08x, delsize %08x)\n"),start,x->size,size);
+				size = x->size;
+			}
+
+			shmdt (x->native_address);
+			size -= x->size;
+			start += x->size;
+			if (x->next)
+				x->next->prev = x->prev;	/* remove this one from the list */
+			if (x->prev)
+				x->prev->next = x->next;
+			else
+				shm_start = x->next;
+			xfree (x);
+		} else {
+			size -= 0x10000;
+			start += 0x10000;
+		}
+	}
+}
+
+static void add_shmmaps (uae_u32 start, addrbank *what)
+{
+	shmpiece *x = shm_start;
+	shmpiece *y;
+	uae_u8 *base = what->baseaddr;
+
+	if (!needmman ())
+		return;
+
+	if (!base)
+		return;
+
+	x = find_shmpiece (base, false);
+	if (!x)
+		return;
+
+	y = xmalloc (shmpiece, 1);
+	*y = *x;
+	base = ((uae_u8 *) NATMEM_OFFSET) + start;
+	y->native_address = (uae_u8*)shmat (y->id, base, 0);
+	if (y->native_address == (void *) -1) {
+		write_log (_T("NATMEM: Failure to map existing at %08x (%p)\n"), start, base);
+		dumplist ();
+		nocanbang ();
+		return;
+	}
+	y->next = shm_start;
+	y->prev = NULL;
+	if (y->next)
+		y->next->prev = y;
+	shm_start = y;
+}
+
+#define MAPPED_MALLOC_DEBUG 0
+
+bool mapped_malloc (addrbank *ab)
+{
+	int id;
+	void *answer;
+	shmpiece *x;
+	bool rtgmem = (ab->flags & ABFLAG_RTG) != 0;
+	static int recurse;
+
+	ab->startmask = ab->start;
+	if (!needmman () && (!rtgmem || currprefs.cpu_model < 68020)) {
+		nocanbang ();
+		ab->flags &= ~ABFLAG_DIRECTMAP;
+		if (ab->flags & ABFLAG_NOALLOC) {
+#if MAPPED_MALLOC_DEBUG
+			write_log(_T("mapped_malloc noalloc %s\n"), ab->name);
+#endif
+			return true;
+		}
+		ab->baseaddr = xcalloc (uae_u8, ab->allocated + 4);
+#if MAPPED_MALLOC_DEBUG
+		write_log(_T("mapped_malloc nodirect %s %p\n"), ab->name, ab->baseaddr);
+#endif
+		return ab->baseaddr != NULL;
+	}
+
+	id = shmget (IPC_PRIVATE, ab->allocated, 0x1ff, ab->label);
+	if (id == -1) {
+		nocanbang ();
+		if (recurse)
+			return NULL;
+		recurse++;
+		mapped_malloc (ab);
+		recurse--;
+		return ab->baseaddr != NULL;
+	}
+	if (!(ab->flags & ABFLAG_NOALLOC)) {
+		answer = shmat (ab, id, 0, 0);
+		shmctl (id, IPC_RMID, NULL);
+	} else {
+		answer = ab->baseaddr;
+	}
+	if (answer != (void *) -1) {
+		x = xmalloc (shmpiece, 1);
+		x->native_address = (uae_u8*)answer;
+		x->id = id;
+		x->size = ab->allocated;
+		x->name = ab->label;
+		x->next = shm_start;
+		x->prev = NULL;
+		if (x->next)
+			x->next->prev = x;
+		shm_start = x;
+		ab->baseaddr = x->native_address;
+		ab->flags |= ABFLAG_DIRECTMAP;
+#if MAPPED_MALLOC_DEBUG
+		write_log(_T("mapped_malloc direct %s %p\n"), ab->name, ab->baseaddr);
+#endif
+		return ab->baseaddr != NULL;
+	}
+	if (recurse)
+		return NULL;
+	nocanbang ();
+	recurse++;
+	mapped_malloc (ab);
+	recurse--;
+#if MAPPED_MALLOC_DEBUG
+	write_log(_T("mapped_malloc indirect %s %p\n"), ab->name, ab->baseaddr);
+#endif
+	return ab->baseaddr != NULL;}
+
+#endif
+
+static void init_mem_banks (void)
+{
+	int i;
+
+	for (i = 0; i < MEMORY_BANKS; i++)
+		put_mem_bank (i << 16, &dummy_bank, 0);
+#ifdef NATMEM_OFFSET
+	delete_shmmaps (0, 0xFFFF0000);
+#endif
+}
+
+
+
+#ifdef WINUAE_FOR_HATARI
+/*
+ * Check if an address points to a memory region that causes bus error
+ * Returns true if region gives bus error
+ */
+bool memory_region_bus_error ( uaecptr addr )
+{
+	return mem_banks[bankindex(addr)] == &BusErrMem_bank;
+}
+#endif
+
+
+/*
+ * Initialize some extra parameters for the memory banks in CE mode
+ * By default, we set all banks to CHIP16 and not cachable
+ *
+ * Possible values for ce_banktype :
+ *  CE_MEMBANK_CHIP16	shared between CPU and DMA, bus width = 16 bits
+ *  CE_MEMBANK_CHIP32	shared between CPU and DMA, bus width = 16 bits (AGA chipset)
+ *  CE_MEMBANK_FAST16	accessible only to the CPU,  bus width = 16 bits
+ *  CE_MEMBANK_FAST32 	accessible only to the CPU,  bus width = 32 bits
+ *  CE_MEMBANK_CIA	Amiga only, for CIA chips
+ *
+ * Possible values for ce_cachable :
+ *  bit 0 : cachable yes/no (for 68030 data cache)
+ *  bit 1 : burst mode allowed when caching yes/no (for 68030 data cache)
+ *	(not used, check for CE_MEMBANK_FAST32 instead)
+ */
+static void init_ce_banks (void)
+{
+	/* Default to CHIP16 */
+	memset (ce_banktype, CE_MEMBANK_CHIP16, sizeof ce_banktype);
+
+	/* Default to not cachable */
+	memset (ce_cachable, 0, sizeof ce_cachable);
+}
+
+
+/*
+ * For CE mode, set banktype and cachable for a memory region
+ */
+static void fill_ce_banks (int start, int size, int banktype, int cachable )
+{
+	int i;
+
+	for ( i=start ; i 512*1024) {
+	STmem_size >>= 1;
+	STmemory = (uae_u8 *)malloc (STmem_size);
+	if (STmemory)
+	    write_log ("Reducing STmem size to %dkb\n", STmem_size >> 10);
+    }
+    if (!STmemory) {
+	write_log ("virtual memory exhausted (STmemory)!\n");
+	SDL_Quit();
+	exit(1);
+    }
+
+#else
+
+    /* STmemory points to the 16 MiB STRam array, we just have to set up
+     * the remaining pointers here: */
+    ROMmemory = STRam + ROMmem_start;
+    IdeMemory = STRam + IdeMem_start;
+    IOmemory = STRam + IOmem_start;
+
+#endif
+
+    init_mem_banks();
+    init_ce_banks();
+
+    /* Set the infos about memory pointers for each mem bank, used for direct memory access in stMemory.c */
+    STmem_bank.baseaddr = STmemory;
+    STmem_bank.mask = STmem_mask;
+    STmem_bank.start = STmem_start;
+
+    SysMem_bank.baseaddr = STmemory;
+    SysMem_bank.mask = STmem_mask;
+    SysMem_bank.start = STmem_start;
+
+    dummy_bank.baseaddr = NULL;				/* No real memory allocated for this region */
+    VoidMem_bank.baseaddr = NULL;			/* No real memory allocated for this region */
+    BusErrMem_bank.baseaddr = NULL;			/* No real memory allocated for this region */
+
+
+    /* Map the ST system RAM: */
+    map_banks_ce(&SysMem_bank, 0x00, 1, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_CACHABLE);
+    /* Between STRamEnd and 4MB barrier, there is void space: */
+    map_banks_ce(&VoidMem_bank, 0x08, 0x38, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_NOT_CACHABLE);
+    /* Space between 4MB barrier and TOS ROM causes a bus error: */
+    map_banks_ce(&BusErrMem_bank, 0x400000 >> 16, 0xA0, 0 , CE_MEMBANK_CHIP16, CE_MEMBANK_NOT_CACHABLE);
+    /* Now map main ST RAM, overwriting the void and bus error regions if necessary: */
+    map_banks_ce(&STmem_bank, 0x01, (STmem_size >> 16) - 1, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_CACHABLE);
+
+
+    /* Handle extra RAM on TT and Falcon starting at 0x1000000 and up to 0x80000000 */
+    /* This requires the CPU to use 32 bit addressing */
+    TTmemory = NULL;
+    if ( ConfigureParams.System.bAddressSpace24 == false )
+    {
+	/* If there's no extra RAM on a TT, region 0x01000000 - 0x80000000 (2047 MB) must return bus errors */
+	if ( ConfigureParams.System.nMachineType == MACHINE_TT )
+	    map_banks_ce ( &BusErrMem_bank, TTmem_start >> 16, ( TTmem_end - TTmem_start ) >> 16, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_NOT_CACHABLE);
+
+	if ( TTmem_size > 0 )
+	{
+	    TTmemory = (uae_u8 *)malloc ( TTmem_size );
+
+	    if ( TTmemory != NULL )
+	    {
+		/* 32 bit RAM for CPU only + cache/burst allowed */
+		map_banks_ce ( &TTmem_bank, TTmem_start >> 16, TTmem_size >> 16, 0, CE_MEMBANK_FAST32, CE_MEMBANK_CACHABLE_BURST );
+		TTmem_mask = 0xffffffff;
+		TTmem_bank.baseaddr = TTmemory;
+		TTmem_bank.mask = TTmem_mask;
+		TTmem_bank.start = TTmem_start;
+	    }
+	    else
+	    {
+		write_log ("can't allocate %d MB for TT RAM\n" , TTmem_size / ( 1024*1024 ) );
+		TTmem_size = 0;
+	    }
+	}
+    }
+
+
+    /* ROM memory: */
+    /* Depending on which ROM version we are using, the other ROM region is illegal! */
+    if(nNewRomMemStart == 0xFC0000)
+    {
+        map_banks_ce(&ROMmem_bank, 0xFC0000 >> 16, 0x3, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_CACHABLE);	/* [NP] FIXME test needed on real STF, could be FAST16 in fact */
+        map_banks_ce(&BusErrMem_bank, 0xE00000 >> 16, 0x10, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_NOT_CACHABLE);
+    }
+    else if(nNewRomMemStart == 0xE00000)
+    {
+        map_banks_ce(&ROMmem_bank, 0xE00000 >> 16, 0x10, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_CACHABLE);	/* [NP] FIXME test needed on real STF, could be FAST16 in fact */
+        map_banks_ce(&BusErrMem_bank, 0xFC0000 >> 16, 0x3, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_NOT_CACHABLE);
+    }
+    else
+    {
+        write_log("Illegal ROM memory start!\n");
+    }
+
+    /* Cartridge memory: */
+    map_banks_ce(&ROMmem_bank, 0xFA0000 >> 16, 0x2, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_CACHABLE);		/* [NP] FIXME test needed on real STF, could be FAST16 in fact */
+    ROMmem_bank.baseaddr = ROMmemory;
+    ROMmem_bank.mask = ROMmem_mask;
+    ROMmem_bank.start = ROMmem_start;
+
+    /* IO memory: */
+    map_banks_ce(&IOmem_bank, IOmem_start>>16, 0x1, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_NOT_CACHABLE);
+    IOmem_bank.baseaddr = IOmemory;
+    IOmem_bank.mask = IOmem_mask;
+    IOmem_bank.start = IOmem_start;
+
+    /* IDE controller memory region: */
+    map_banks_ce(&IdeMem_bank, IdeMem_start >> 16, 0x1, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_NOT_CACHABLE);	/* IDE controller on the Falcon */
+    IdeMem_bank.baseaddr = IdeMemory;
+    IdeMem_bank.mask = IdeMem_mask;
+    IdeMem_bank.start = IdeMem_start ;
+
+    /* Illegal memory regions cause a bus error on the ST: */
+    map_banks_ce(&BusErrMem_bank, 0xF10000 >> 16, 0x9, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_NOT_CACHABLE);
+
+
+    /* If MMU is disabled on TT/Falcon and we use full 32 bit addressing */
+    /* then we remap memory 00xxxxxx to FFxxxxxx (as a minimal replacement */
+    /* for the MMU's tables). Else, we get some crashes when booting TOS 3 and 4 */
+    if ( ( ConfigureParams.System.bAddressSpace24 == false )
+      && ( ConfigureParams.System.bMMU == false )
+      && ( ( ConfigureParams.System.nMachineType == MACHINE_TT )
+	|| ( ConfigureParams.System.nMachineType == MACHINE_FALCON ) ) )
+    {
+      /* Copy all 256 banks 0x0000-0x00FF to banks 0xFF00-0xFFFF */
+      for ( addr=0x0 ; addr<=0x00ffffff ; addr+=0x10000 )
+	{
+	  //printf ( "put mem %x %x\n" , addr , addr|0xff000000 );
+	  put_mem_bank ( 0xff000000|addr , &get_mem_bank ( addr ) , 0 );
+
+	  /* Copy the CE parameters */
+	  ce_banktype[ (0xff000000|addr)>>16 ] = ce_banktype[ addr>>16 ];
+	  ce_cachable[ (0xff000000|addr)>>16 ] = ce_cachable[ addr>>16 ];
+	}
+    }
+
+    illegal_count = 50;
+}
+
+
+/*
+ * Uninitialize the memory banks.
+ */
+void memory_uninit (void)
+{
+    /* Here, we free allocated memory from memory_init */
+    if (TTmemory) {
+	free(TTmemory);
+	TTmemory = NULL;
+    }
+
+#if ENABLE_SMALL_MEM
+
+    if (STmemory) {
+	free(STmemory);
+	STmemory = NULL;
+    }
+
+    if (ROMmemory) {
+	free(ROMmemory);
+	ROMmemory = NULL;
+    }
+
+#endif  /* ENABLE_SMALL_MEM */
+}
+
+
+static void map_banks2 (addrbank *bank, int start, int size, int realsize, int quick)
+{
+#ifndef WINUAE_FOR_HATARI
+	int bnr, old;
+	unsigned long int hioffs = 0, endhioffs = 0x100;
+	addrbank *orgbank = bank;
+	uae_u32 realstart = start;
+#else
+	int bnr;
+	unsigned long int hioffs = 0, endhioffs = 0x100;
+	uae_u32 realstart = start;
+#endif
+
+//printf ( "map %x %x 24=%d\n" , start<<16 , size<<16 , currprefs.address_space_24 );
+#ifndef WINUAE_FOR_HATARI
+	if (quick <= 0)
+		old = debug_bankchange (-1);
+#endif
+	flush_icache_hard (0, 3); /* Sure don't want to keep any old mappings around! */
+#ifdef NATMEM_OFFSET
+	if (!quick)
+		delete_shmmaps (start << 16, size << 16);
+#endif
+
+	if (!realsize)
+		realsize = size << 16;
+
+	if ((size << 16) < realsize) {
+		write_log (_T("Broken mapping, size=%x, realsize=%x\nStart is %x\n"),
+			size, realsize, start);
+	}
+
+#ifndef ADDRESS_SPACE_24BIT
+	if (start >= 0x100) {
+		int real_left = 0;
+		for (bnr = start; bnr < start + size; bnr++) {
+			if (!real_left) {
+				realstart = bnr;
+				real_left = realsize >> 16;
+#ifdef NATMEM_OFFSET
+				if (!quick)
+					add_shmmaps (realstart << 16, bank);
+#endif
+			}
+			put_mem_bank (bnr << 16, bank, realstart << 16);
+			real_left--;
+		}
+#ifndef WINUAE_FOR_HATARI
+		if (quick <= 0)
+			debug_bankchange (old);
+#endif
+		return;
+	}
+#endif
+	if (last_address_space_24)
+		endhioffs = 0x10000;
+#ifdef ADDRESS_SPACE_24BIT
+	endhioffs = 0x100;
+#endif
+	for (hioffs = 0; hioffs < endhioffs; hioffs += 0x100) {
+		int real_left = 0;
+		for (bnr = start; bnr < start + size; bnr++) {
+			if (!real_left) {
+				realstart = bnr + hioffs;
+				real_left = realsize >> 16;
+#ifdef NATMEM_OFFSET
+				if (!quick)
+					add_shmmaps (realstart << 16, bank);
+#endif
+			}
+			put_mem_bank ((bnr + hioffs) << 16, bank, realstart << 16);
+			real_left--;
+		}
+	}
+#ifndef WINUAE_FOR_HATARI
+	if (quick <= 0)
+		debug_bankchange (old);
+	fill_ce_banks ();
+#endif
+}
+
+void map_banks (addrbank *bank, int start, int size, int realsize)
+{
+	map_banks2 (bank, start, size, realsize, 0);
+}
+void map_banks_quick (addrbank *bank, int start, int size, int realsize)
+{
+	map_banks2 (bank, start, size, realsize, 1);
+}
+void map_banks_nojitdirect (addrbank *bank, int start, int size, int realsize)
+{
+	map_banks2 (bank, start, size, realsize, -1);
+}
+
+void map_banks_ce (addrbank *bank, int start, int size, int realsize , int banktype, int cachable )
+{
+	map_banks2 (bank, start, size, realsize, 0);
+	fill_ce_banks (start, size, banktype, cachable );
+}
+
+
+
+
+void memory_hardreset (void)
+{
+}
diff --git a/src/cpu/memory.h b/src/cpu/memory.h
new file mode 100644
index 0000000..bf625a3
--- /dev/null
+++ b/src/cpu/memory.h
@@ -0,0 +1,596 @@
+/*
+* UAE - The Un*x Amiga Emulator
+*
+* memory management
+*
+* Copyright 1995 Bernd Schmidt
+*/
+
+#ifndef MEMORY_H
+#define MEMORY_H
+
+extern void memory_reset (void);
+
+#ifdef JIT
+extern int special_mem;
+
+extern uae_u8 *cache_alloc (int);
+extern void cache_free (uae_u8*);
+#endif
+
+#define S_READ 1
+#define S_WRITE 2
+
+bool init_shm (void);
+void free_shm (void);
+bool preinit_shm (void);
+extern bool canbang;
+extern bool jit_direct_compatible_memory;
+
+#define Z3BASE_UAE 0x10000000
+#define Z3BASE_REAL 0x40000000
+
+#ifdef ADDRESS_SPACE_24BIT
+#define MEMORY_BANKS 256
+#define MEMORY_RANGE_MASK ((1<<24)-1)
+#else
+#define MEMORY_BANKS 65536
+#define MEMORY_RANGE_MASK (~0)
+#endif
+
+typedef uae_u32 (REGPARAM3 *mem_get_func)(uaecptr) REGPARAM;
+typedef void (REGPARAM3 *mem_put_func)(uaecptr, uae_u32) REGPARAM;
+typedef uae_u8 *(REGPARAM3 *xlate_func)(uaecptr) REGPARAM;
+typedef int (REGPARAM3 *check_func)(uaecptr, uae_u32) REGPARAM;
+
+extern uae_u8 *address_space, *good_address_map;
+extern uae_u32 max_z3fastmem;
+
+extern uae_u32 wait_cpu_cycle_read (uaecptr addr, int mode);
+extern void wait_cpu_cycle_write (uaecptr addr, int mode, uae_u32 v);
+extern uae_u32 wait_cpu_cycle_read_ce020 (uaecptr addr, int mode);
+extern void wait_cpu_cycle_write_ce020 (uaecptr addr, int mode, uae_u32 v);
+
+#undef DIRECT_MEMFUNCS_SUCCESSFUL
+#include "maccess.h"
+
+#define chipmem_start_addr 0x00000000
+#define bogomem_start_addr 0x00C00000
+
+#define ROM_SIZE_512 524288
+#define ROM_SIZE_256 262144
+#define ROM_SIZE_128 131072
+
+extern bool ersatzkickfile;
+extern bool cloanto_rom, kickstart_rom;
+extern uae_u16 kickstart_version;
+extern int uae_boot_rom_type;
+extern int uae_boot_rom_size;
+extern uaecptr rtarea_base;
+
+extern uae_u8* baseaddr[];
+
+enum
+{
+	ABFLAG_UNK = 0, ABFLAG_RAM = 1, ABFLAG_ROM = 2, ABFLAG_ROMIN = 4, ABFLAG_IO = 8,
+	ABFLAG_NONE = 16, ABFLAG_SAFE = 32, ABFLAG_INDIRECT = 64, ABFLAG_NOALLOC = 128,
+	ABFLAG_RTG = 256, ABFLAG_THREADSAFE = 512, ABFLAG_DIRECTMAP = 1024
+};
+typedef struct {
+	/* These ones should be self-explanatory... */
+	mem_get_func lget, wget, bget;
+	mem_put_func lput, wput, bput;
+	/* Use xlateaddr to translate an Amiga address to a uae_u8 * that can
+	* be used to address memory without calling the wget/wput functions.
+	* This doesn't work for all memory banks, so this function may call
+	* abort(). */
+	xlate_func xlateaddr;
+	/* To prevent calls to abort(), use check before calling xlateaddr.
+	* It checks not only that the memory bank can do xlateaddr, but also
+	* that the pointer points to an area of at least the specified size.
+	* This is used for example to translate bitplane pointers in custom.c */
+	check_func check;
+	/* For those banks that refer to real memory, we can save the whole trouble
+	of going through function calls, and instead simply grab the memory
+	ourselves. This holds the memory address where the start of memory is
+	for this particular bank. */
+	uae_u8 *baseaddr;
+	const TCHAR *label;
+	const TCHAR *name;
+	/* for instruction opcode/operand fetches */
+	mem_get_func lgeti, wgeti;
+	int flags;
+	struct addrbank_sub *sub_banks;
+	uae_u32 mask;
+	uae_u32 startmask;
+	uae_u32 start;
+	uae_u32 allocated;
+} addrbank;
+
+#define MEMORY_MIN_SUBBANK 1024
+struct addrbank_sub
+{
+	addrbank *bank;
+	uae_u32 offset;
+	uae_u32 suboffset;
+	uae_u32 mask;
+	uae_u32 maskval;
+};
+
+#define CE_MEMBANK_FAST32 0
+#define CE_MEMBANK_CHIP16 1
+#define CE_MEMBANK_CHIP32 2
+#define CE_MEMBANK_CIA 3
+#define CE_MEMBANK_FAST16 4
+#ifdef WINUAE_FOR_HATARI
+#define CE_MEMBANK_NOT_CACHABLE		0
+#define CE_MEMBANK_CACHABLE		(1)
+#define CE_MEMBANK_CACHABLE_BURST	(1|2)
+#endif
+extern uae_u8 ce_banktype[65536], ce_cachable[65536];
+
+#ifdef JIT
+#define MEMORY_LGET(name, nojit) \
+static uae_u32 REGPARAM3 name ## _lget (uaecptr) REGPARAM; \
+static uae_u32 REGPARAM2 name ## _lget (uaecptr addr) \
+{ \
+	uae_u8 *m; \
+	if (nojit) special_mem |= S_READ; \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	m = name ## _bank.baseaddr + addr; \
+	return do_get_mem_long ((uae_u32 *)m); \
+}
+#define MEMORY_WGET(name, nojit) \
+static uae_u32 REGPARAM3 name ## _wget (uaecptr) REGPARAM; \
+static uae_u32 REGPARAM2 name ## _wget (uaecptr addr) \
+{ \
+	uae_u8 *m; \
+	if (nojit) special_mem |= S_READ; \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	m = name ## _bank.baseaddr + addr; \
+	return do_get_mem_word ((uae_u16 *)m); \
+}
+#define MEMORY_BGET(name, nojit) \
+static uae_u32 REGPARAM3 name ## _bget (uaecptr) REGPARAM; \
+static uae_u32 REGPARAM2 name ## _bget (uaecptr addr) \
+{ \
+	if (nojit) special_mem |= S_READ; \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	return name ## _bank.baseaddr[addr]; \
+}
+#define MEMORY_LPUT(name, nojit) \
+static void REGPARAM3 name ## _lput (uaecptr, uae_u32) REGPARAM; \
+static void REGPARAM2 name ## _lput (uaecptr addr, uae_u32 l) \
+{ \
+	uae_u8 *m;  \
+	if (nojit) special_mem |= S_WRITE; \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	m = name ## _bank.baseaddr + addr; \
+	do_put_mem_long ((uae_u32 *)m, l); \
+}
+#define MEMORY_WPUT(name, nojit) \
+static void REGPARAM3 name ## _wput (uaecptr, uae_u32) REGPARAM; \
+static void REGPARAM2 name ## _wput (uaecptr addr, uae_u32 w) \
+{ \
+	uae_u8 *m;  \
+	if (nojit) special_mem |= S_WRITE; \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	m = name ## _bank.baseaddr + addr; \
+	do_put_mem_word ((uae_u16 *)m, w); \
+}
+#define MEMORY_BPUT(name, nojit) \
+static void REGPARAM3 name ## _bput (uaecptr, uae_u32) REGPARAM; \
+static void REGPARAM2 name ## _bput (uaecptr addr, uae_u32 b) \
+{ \
+	if (nojit) special_mem |= S_WRITE; \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	name ## _bank.baseaddr[addr] = b; \
+}
+#define MEMORY_CHECK(name) \
+static int REGPARAM3 name ## _check (uaecptr addr, uae_u32 size) REGPARAM; \
+static int REGPARAM2 name ## _check (uaecptr addr, uae_u32 size) \
+{ \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	return (addr + size) <= name ## _bank.allocated; \
+}
+#define MEMORY_XLATE(name) \
+static uae_u8 *REGPARAM3 name ## _xlate (uaecptr addr) REGPARAM; \
+static uae_u8 *REGPARAM2 name ## _xlate (uaecptr addr) \
+{ \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	return name ## _bank.baseaddr + addr; \
+}
+#else
+#define MEMORY_LGET(name, nojit) \
+static uae_u32 REGPARAM3 name ## _lget (uaecptr) REGPARAM; \
+static uae_u32 REGPARAM2 name ## _lget (uaecptr addr) \
+{ \
+	uae_u8 *m; \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	m = name ## _bank.baseaddr + addr; \
+	return do_get_mem_long ((uae_u32 *)m); \
+}
+#define MEMORY_WGET(name, nojit) \
+static uae_u32 REGPARAM3 name ## _wget (uaecptr) REGPARAM; \
+static uae_u32 REGPARAM2 name ## _wget (uaecptr addr) \
+{ \
+	uae_u8 *m; \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	m = name ## _bank.baseaddr + addr; \
+	return do_get_mem_word ((uae_u16 *)m); \
+}
+#define MEMORY_BGET(name, nojit) \
+static uae_u32 REGPARAM3 name ## _bget (uaecptr) REGPARAM; \
+static uae_u32 REGPARAM2 name ## _bget (uaecptr addr) \
+{ \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	return name ## _bank.baseaddr[addr]; \
+}
+#define MEMORY_LPUT(name, nojit) \
+static void REGPARAM3 name ## _lput (uaecptr, uae_u32) REGPARAM; \
+static void REGPARAM2 name ## _lput (uaecptr addr, uae_u32 l) \
+{ \
+	uae_u8 *m;  \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	m = name ## _bank.baseaddr + addr; \
+	do_put_mem_long ((uae_u32 *)m, l); \
+}
+#define MEMORY_WPUT(name, nojit) \
+static void REGPARAM3 name ## _wput (uaecptr, uae_u32) REGPARAM; \
+static void REGPARAM2 name ## _wput (uaecptr addr, uae_u32 w) \
+{ \
+	uae_u8 *m;  \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	m = name ## _bank.baseaddr + addr; \
+	do_put_mem_word ((uae_u16 *)m, w); \
+}
+#define MEMORY_BPUT(name, nojit) \
+static void REGPARAM3 name ## _bput (uaecptr, uae_u32) REGPARAM; \
+static void REGPARAM2 name ## _bput (uaecptr addr, uae_u32 b) \
+{ \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	name ## _bank.baseaddr[addr] = b; \
+}
+#define MEMORY_CHECK(name) \
+static int REGPARAM3 name ## _check (uaecptr addr, uae_u32 size) REGPARAM; \
+static int REGPARAM2 name ## _check (uaecptr addr, uae_u32 size) \
+{ \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	return (addr + size) <= name ## _bank.allocated; \
+}
+#define MEMORY_XLATE(name) \
+static uae_u8 *REGPARAM3 name ## _xlate (uaecptr addr) REGPARAM; \
+static uae_u8 *REGPARAM2 name ## _xlate (uaecptr addr) \
+{ \
+	addr -= name ## _bank.start & name ## _bank.mask; \
+	addr &= name ## _bank.mask; \
+	return name ## _bank.baseaddr + addr; \
+}
+#endif
+
+#define DECLARE_MEMORY_FUNCTIONS(name) \
+ static uae_u32 REGPARAM3 name ## _lget (uaecptr) REGPARAM; \
+ static uae_u32 REGPARAM3 name ## _lgeti (uaecptr) REGPARAM; \
+ static uae_u32 REGPARAM3 name ## _wget (uaecptr) REGPARAM; \
+ static uae_u32 REGPARAM3 name ## _wgeti (uaecptr) REGPARAM; \
+ static uae_u32 REGPARAM3 name ## _bget (uaecptr) REGPARAM; \
+ static void REGPARAM3 name ## _lput (uaecptr, uae_u32) REGPARAM; \
+ static void REGPARAM3 name ## _wput (uaecptr, uae_u32) REGPARAM; \
+ static void REGPARAM3 name ## _bput (uaecptr, uae_u32) REGPARAM; \
+ static int REGPARAM3 name ## _check (uaecptr addr, uae_u32 size) REGPARAM; \
+ static uae_u8 *REGPARAM3 name ## _xlate (uaecptr addr) REGPARAM;
+
+#define MEMORY_FUNCTIONS(name) \
+MEMORY_LGET(name, 0); \
+MEMORY_WGET(name, 0); \
+MEMORY_BGET(name, 0); \
+MEMORY_LPUT(name, 0); \
+MEMORY_WPUT(name, 0); \
+MEMORY_BPUT(name, 0); \
+MEMORY_CHECK(name); \
+MEMORY_XLATE(name);
+
+#define MEMORY_FUNCTIONS_NOJIT(name) \
+MEMORY_LGET(name, 1); \
+MEMORY_WGET(name, 1); \
+MEMORY_BGET(name, 1); \
+MEMORY_LPUT(name, 1); \
+MEMORY_WPUT(name, 1); \
+MEMORY_BPUT(name, 1); \
+MEMORY_CHECK(name); \
+MEMORY_XLATE(name);
+
+extern addrbank chipmem_bank;
+extern addrbank chipmem_agnus_bank;
+extern addrbank chipmem_bank_ce2;
+extern addrbank kickmem_bank;
+extern addrbank custom_bank;
+extern addrbank filesys_bank;
+extern addrbank expamem_bank;
+extern addrbank expamem_null, expamem_none;
+extern addrbank fastmem_bank;
+extern addrbank fastmem_nojit_bank;
+extern addrbank fastmem2_bank;
+extern addrbank fastmem2_nojit_bank;
+
+extern addrbank bogomem_bank;
+extern addrbank custmem1_bank;
+extern addrbank custmem2_bank;
+
+
+extern uae_u32 last_custom_value1;
+
+/* Default memory access functions */
+
+extern void dummy_put (uaecptr addr, int size, uae_u32 val);
+extern uae_u32 dummy_get (uaecptr addr, int size, bool inst);
+
+extern int REGPARAM3 default_check(uaecptr addr, uae_u32 size) REGPARAM;
+extern uae_u8 *REGPARAM3 default_xlate(uaecptr addr) REGPARAM;
+/* 680x0 opcode fetches */
+extern uae_u32 REGPARAM3 dummy_lgeti (uaecptr addr) REGPARAM;
+extern uae_u32 REGPARAM3 dummy_wgeti (uaecptr addr) REGPARAM;
+
+/* sub bank support */
+extern uae_u32 REGPARAM3 sub_bank_lget (uaecptr) REGPARAM;
+extern uae_u32 REGPARAM3 sub_bank_wget(uaecptr) REGPARAM;
+extern uae_u32 REGPARAM3 sub_bank_bget(uaecptr) REGPARAM;
+extern void REGPARAM3 sub_bank_lput(uaecptr, uae_u32) REGPARAM;
+extern void REGPARAM3 sub_bank_wput(uaecptr, uae_u32) REGPARAM;
+extern void REGPARAM3 sub_bank_bput(uaecptr, uae_u32) REGPARAM;
+extern uae_u32 REGPARAM3 sub_bank_lgeti(uaecptr) REGPARAM;
+extern uae_u32 REGPARAM3 sub_bank_wgeti(uaecptr) REGPARAM;
+extern int REGPARAM3 sub_bank_check(uaecptr addr, uae_u32 size) REGPARAM;
+extern uae_u8 *REGPARAM3 sub_bank_xlate(uaecptr addr) REGPARAM;
+extern addrbank *get_sub_bank(uaecptr *addr);
+
+#define bankindex(addr) (((uaecptr)(addr)) >> 16)
+
+extern addrbank *mem_banks[MEMORY_BANKS];
+
+#ifdef JIT
+extern uae_u8 *baseaddr[MEMORY_BANKS];
+#endif
+
+#define get_mem_bank(addr) (*mem_banks[bankindex(addr)])
+extern addrbank *get_mem_bank_real(uaecptr);
+
+#ifdef JIT
+#define put_mem_bank(addr, b, realstart) do { \
+	(mem_banks[bankindex(addr)] = (b)); \
+	if ((b)->baseaddr) \
+	baseaddr[bankindex(addr)] = (b)->baseaddr - (realstart); \
+	else \
+	baseaddr[bankindex(addr)] = (uae_u8*)(((uae_u8*)b)+1); \
+} while (0)
+#else
+#define put_mem_bank(addr, b, realstart) \
+	(mem_banks[bankindex(addr)] = (b));
+#endif
+
+#ifdef WINUAE_FOR_HATARI
+extern bool memory_region_bus_error ( uaecptr addr );
+#endif
+extern void memory_init(uae_u32 nNewSTMemSize, uae_u32 nNewTTMemSize, uae_u32 nNewRomMemStart);
+extern void memory_uninit (void);
+extern void map_banks (addrbank *bank, int first, int count, int realsize);
+extern void map_banks_quick (addrbank *bank, int first, int count, int realsize);
+extern void map_banks_nojitdirect (addrbank *bank, int first, int count, int realsize);
+extern void map_banks_cond (addrbank *bank, int first, int count, int realsize);
+#ifdef WINUAE_FOR_HATARI
+extern void map_banks_ce (addrbank *bank, int first, int count, int realsize, int banktype, int cachable);
+#endif
+extern void memory_hardreset (void);
+extern void memory_clear (void);
+extern void free_fastmemory (int);
+
+#define longget(addr) (call_mem_get_func(get_mem_bank(addr).lget, addr))
+#define wordget(addr) (call_mem_get_func(get_mem_bank(addr).wget, addr))
+#define byteget(addr) (call_mem_get_func(get_mem_bank(addr).bget, addr))
+#define longgeti(addr) (call_mem_get_func(get_mem_bank(addr).lgeti, addr))
+#define wordgeti(addr) (call_mem_get_func(get_mem_bank(addr).wgeti, addr))
+#define longput(addr,l) (call_mem_put_func(get_mem_bank(addr).lput, addr, l))
+#define wordput(addr,w) (call_mem_put_func(get_mem_bank(addr).wput, addr, w))
+#define byteput(addr,b) (call_mem_put_func(get_mem_bank(addr).bput, addr, b))
+
+STATIC_INLINE uae_u32 get_long (uaecptr addr)
+{
+	return longget (addr);
+}
+STATIC_INLINE uae_u32 get_word (uaecptr addr)
+{
+	return wordget (addr);
+}
+STATIC_INLINE uae_u32 get_byte (uaecptr addr)
+{
+	return byteget (addr);
+}
+STATIC_INLINE uae_u32 get_longi(uaecptr addr)
+{
+	return longgeti (addr);
+}
+STATIC_INLINE uae_u32 get_wordi(uaecptr addr)
+{
+	return wordgeti (addr);
+}
+
+/*
+* Read a host pointer from addr
+*/
+#if SIZEOF_VOID_P == 4
+# define get_pointer(addr) ((void *)get_long (addr))
+#else
+# if SIZEOF_VOID_P == 8
+STATIC_INLINE void *get_pointer (uaecptr addr)
+{
+	const unsigned int n = SIZEOF_VOID_P / 4;
+	union {
+		void    *ptr;
+		uae_u32  longs[SIZEOF_VOID_P / 4];
+	} p;
+	unsigned int i;
+
+	for (i = 0; i < n; i++) {
+#ifdef WORDS_BIGENDIAN
+		p.longs[i]     = get_long (addr + i * 4);
+#else
+		p.longs[n - 1 - i] = get_long (addr + i * 4);
+#endif
+	}
+	return p.ptr;
+}
+# else
+#  error "Unknown or unsupported pointer size."
+# endif
+#endif
+
+STATIC_INLINE void put_long (uaecptr addr, uae_u32 l)
+{
+	longput(addr, l);
+}
+STATIC_INLINE void put_word (uaecptr addr, uae_u32 w)
+{
+	wordput(addr, w);
+}
+STATIC_INLINE void put_byte (uaecptr addr, uae_u32 b)
+{
+	byteput(addr, b);
+}
+
+extern void put_long_slow (uaecptr addr, uae_u32 v);
+extern void put_word_slow (uaecptr addr, uae_u32 v);
+extern void put_byte_slow (uaecptr addr, uae_u32 v);
+extern uae_u32 get_long_slow (uaecptr addr);
+extern uae_u32 get_word_slow (uaecptr addr);
+extern uae_u32 get_byte_slow (uaecptr addr);
+
+
+/*
+* Store host pointer v at addr
+*/
+#if SIZEOF_VOID_P == 4
+# define put_pointer(addr, p) (put_long ((addr), (uae_u32)(p)))
+#else
+# if SIZEOF_VOID_P == 8
+STATIC_INLINE void put_pointer (uaecptr addr, void *v)
+{
+	const unsigned int n = SIZEOF_VOID_P / 4;
+	union {
+		void    *ptr;
+		uae_u32  longs[SIZEOF_VOID_P / 4];
+	} p;
+	unsigned int i;
+
+	p.ptr = v;
+
+	for (i = 0; i < n; i++) {
+#ifdef WORDS_BIGENDIAN
+		put_long (addr + i * 4, p.longs[i]);
+#else
+		put_long (addr + i * 4, p.longs[n - 1 - i]);
+#endif
+	}
+}
+# endif
+#endif
+
+STATIC_INLINE uae_u8 *get_real_address (uaecptr addr)
+{
+	return get_mem_bank (addr).xlateaddr(addr);
+}
+
+STATIC_INLINE int valid_address (uaecptr addr, uae_u32 size)
+{
+	return get_mem_bank (addr).check(addr, size);
+}
+
+extern int addr_valid (const TCHAR*, uaecptr,uae_u32);
+
+/* For faster access in custom chip emulation.  */
+extern void REGPARAM3 chipmem_lput (uaecptr, uae_u32) REGPARAM;
+extern void REGPARAM3 chipmem_wput (uaecptr, uae_u32) REGPARAM;
+extern void REGPARAM3 chipmem_bput (uaecptr, uae_u32) REGPARAM;
+
+extern uae_u32 REGPARAM3 chipmem_agnus_wget (uaecptr) REGPARAM;
+extern void REGPARAM3 chipmem_agnus_wput (uaecptr, uae_u32) REGPARAM;
+
+/* 68020+ Chip RAM DMA contention emulation */
+extern void REGPARAM3 chipmem_bput_c2 (uaecptr, uae_u32) REGPARAM;
+
+extern uae_u32 (REGPARAM3 *chipmem_lget_indirect)(uaecptr) REGPARAM;
+extern uae_u32 (REGPARAM3 *chipmem_wget_indirect)(uaecptr) REGPARAM;
+extern uae_u32 (REGPARAM3 *chipmem_bget_indirect)(uaecptr) REGPARAM;
+extern void (REGPARAM3 *chipmem_lput_indirect)(uaecptr, uae_u32) REGPARAM;
+extern void (REGPARAM3 *chipmem_wput_indirect)(uaecptr, uae_u32) REGPARAM;
+extern void (REGPARAM3 *chipmem_bput_indirect)(uaecptr, uae_u32) REGPARAM;
+extern int (REGPARAM3 *chipmem_check_indirect)(uaecptr, uae_u32) REGPARAM;
+extern uae_u8 *(REGPARAM3 *chipmem_xlate_indirect)(uaecptr) REGPARAM;
+
+#ifdef NATMEM_OFFSET
+
+typedef struct shmpiece_reg {
+	uae_u8 *native_address;
+	int id;
+	uae_u32 size;
+	const TCHAR *name;
+	struct shmpiece_reg *next;
+	struct shmpiece_reg *prev;
+} shmpiece;
+
+extern shmpiece *shm_start;
+
+#endif
+
+extern bool mapped_malloc (addrbank*);
+extern void mapped_free (addrbank*);
+extern void clearexec (void);
+
+extern uaecptr strcpyha_safe (uaecptr dst, const uae_char *src);
+extern uae_char *strcpyah_safe (uae_char *dst, uaecptr src, int maxsize);
+extern void memcpyha_safe (uaecptr dst, const uae_u8 *src, int size);
+extern void memcpyha (uaecptr dst, const uae_u8 *src, int size);
+extern void memcpyah_safe (uae_u8 *dst, uaecptr src, int size);
+extern void memcpyah (uae_u8 *dst, uaecptr src, int size);
+
+
+#define UAE_MEMORY_REGIONS_MAX 64
+#define UAE_MEMORY_REGION_NAME_LENGTH 64
+
+#define UAE_MEMORY_REGION_RAM (1 << 0)
+#define UAE_MEMORY_REGION_ALIAS (1 << 1)
+#define UAE_MEMORY_REGION_MIRROR (1 << 2)
+
+/* Get a list of memory regions in the Amiga address space */
+
+typedef struct UaeMemoryRegion {
+	uaecptr start;
+	int size;
+	TCHAR name[UAE_MEMORY_REGION_NAME_LENGTH];
+	TCHAR rom_name[UAE_MEMORY_REGION_NAME_LENGTH];
+	uaecptr alias;
+	int flags;
+	uae_u8 *memory;
+} UaeMemoryRegion;
+
+typedef struct UaeMemoryMap {
+	UaeMemoryRegion regions[UAE_MEMORY_REGIONS_MAX];
+	int num_regions;
+} UaeMemoryMap;
+
+void uae_memory_map(UaeMemoryMap *map);
+#endif /* MEMORY_H */
diff --git a/src/cpu/mmu_common.h b/src/cpu/mmu_common.h
new file mode 100644
index 0000000..82ae15b
--- /dev/null
+++ b/src/cpu/mmu_common.h
@@ -0,0 +1,159 @@
+
+#ifndef MMU_COMMON_H
+#define MMU_COMMON_H
+
+#define MMUDEBUG 0
+#define MMUINSDEBUG 0
+#define MMUDEBUGMISC 0
+
+#ifdef _MSC_VER
+#define unlikely(x) x
+#define likely(x) x
+#endif
+
+#ifdef __cplusplus
+struct m68k_exception {
+	int prb;
+	m68k_exception (int exc) : prb (exc) {}
+	operator int() { return prb; }
+};
+#define SAVE_EXCEPTION
+#define RESTORE_EXCEPTION
+#define TRY(var) try
+#define CATCH(var) catch(m68k_exception var)
+#define THROW(n) throw m68k_exception(n)
+#define THROW_AGAIN(var) throw
+#define ENDTRY
+#else
+/* we are in plain C, just use a stack of long jumps */
+#include 
+extern jmp_buf __exbuf;
+extern int     __exvalue;
+#define TRY(DUMMY)       __exvalue=setjmp(__exbuf);       \
+                  if (__exvalue==0) { __pushtry(&__exbuf);
+#define CATCH(x)  __poptry(); } else {m68k_exception x=__exvalue; x=x;
+#define ENDTRY    __poptry();}
+#define THROW(x) if (__is_catched()) {longjmp(__exbuf,x);}
+#define THROW_AGAIN(var) if (__is_catched()) longjmp(*__poptry(),__exvalue)
+#define SAVE_EXCEPTION
+#define RESTORE_EXCEPTION
+jmp_buf* __poptry(void);
+void __pushtry(jmp_buf *j);
+int __is_catched(void);
+
+typedef  int m68k_exception;
+
+#endif
+
+/* special status word (access error stack frame) */
+/* 68060 */
+#define MMU_FSLW_MA		0x08000000
+#define MMU_FSLW_LK		0x02000000
+#define MMU_FSLW_R		0x01000000
+#define MMU_FSLW_W		0x00800000
+#define MMU_FSLW_SIZE_L	0x00000000 /* Note: wrong in mc68060 manual! */
+#define MMU_FSLW_SIZE_B	0x00200000
+#define MMU_FSLW_SIZE_W	0x00400000
+#define MMU_FSLW_SIZE_D	0x00600000
+#define MMU_FSLW_TT		0x00180000
+#define MMU_FSLW_TT_N	0x00000000 /* Normal access */
+#define MMU_FSLW_TT_16  0x00080000 /* MOVE16 */
+#define MMU_FSLW_TM		0x00070000 /* = function code */
+#define MMU_FSLW_IO		0x00008000
+#define MMU_FSLW_PBE	0x00004000
+#define MMU_FSLW_SBE	0x00002000
+#define MMU_FSLW_PTA	0x00001000
+#define MMU_FSLW_PTB	0x00000800
+#define MMU_FSLW_IL		0x00000400
+#define MMU_FSLW_PF		0x00000200
+#define MMU_FSLW_SP		0x00000100
+#define MMU_FSLW_WP		0x00000080
+#define MMU_FSLW_TWE	0x00000040
+#define MMU_FSLW_RE		0x00000020
+#define MMU_FSLW_WE		0x00000010
+#define MMU_FSLW_TTR	0x00000008
+#define MMU_FSLW_BPE	0x00000004
+#define MMU_FSLW_SEE	0x00000001
+/* 68040 */
+#define MMU_SSW_TM		0x0007
+#define MMU_SSW_TT		0x0018
+#define MMU_SSW_TT1		0x0010
+#define MMU_SSW_TT0		0x0008
+#define MMU_SSW_SIZE	0x0060
+#define MMU_SSW_SIZE_B	0x0020
+#define MMU_SSW_SIZE_W	0x0040
+#define MMU_SSW_SIZE_L	0x0000
+#define MMU_SSW_SIZE_CL	0x0060
+#define MMU_SSW_RW		0x0100
+#define MMU_SSW_LK		0x0200
+#define MMU_SSW_ATC		0x0400
+#define MMU_SSW_MA		0x0800
+#define MMU_SSW_CM	0x1000
+#define MMU_SSW_CT	0x2000
+#define MMU_SSW_CU	0x4000
+#define MMU_SSW_CP	0x8000
+/* 68030 */
+#define MMU030_SSW_FC       0x8000
+#define MMU030_SSW_FB       0x4000
+#define MMU030_SSW_RC       0x2000
+#define MMU030_SSW_RB       0x1000
+#define MMU030_SSW_DF       0x0100
+#define MMU030_SSW_RM       0x0080
+#define MMU030_SSW_RW       0x0040
+#define MMU030_SSW_SIZE_MASK    0x0030
+#define MMU030_SSW_SIZE_B       0x0010
+#define MMU030_SSW_SIZE_W       0x0020
+#define MMU030_SSW_SIZE_L       0x0000
+#define MMU030_SSW_FC_MASK      0x0007
+
+
+#define ALWAYS_INLINE __inline
+
+// take care of 2 kinds of alignement, bus size and page
+#if 1
+static ALWAYS_INLINE bool is_unaligned(uaecptr addr, int size)
+{
+    return unlikely((addr & (size - 1)) && (addr ^ (addr + size - 1)) & regs.mmu_page_size);
+}
+#else
+static ALWAYS_INLINE bool is_unaligned(uaecptr addr, int size)
+{
+    return (addr & (size - 1));
+}
+#endif
+
+static ALWAYS_INLINE void phys_put_long(uaecptr addr, uae_u32 l)
+{
+    longput(addr, l);
+}
+static ALWAYS_INLINE void phys_put_word(uaecptr addr, uae_u32 w)
+{
+    wordput(addr, w);
+}
+static ALWAYS_INLINE void phys_put_byte(uaecptr addr, uae_u32 b)
+{
+    byteput(addr, b);
+}
+static ALWAYS_INLINE uae_u32 phys_get_long(uaecptr addr)
+{
+    return longget (addr);
+}
+static ALWAYS_INLINE uae_u32 phys_get_word(uaecptr addr)
+{
+    return wordget (addr);
+}
+static ALWAYS_INLINE uae_u32 phys_get_byte(uaecptr addr)
+{
+    return byteget (addr);
+}
+
+extern uae_u32(*x_phys_get_iword)(uaecptr);
+extern uae_u32(*x_phys_get_ilong)(uaecptr);
+extern uae_u32(*x_phys_get_byte)(uaecptr);
+extern uae_u32(*x_phys_get_word)(uaecptr);
+extern uae_u32(*x_phys_get_long)(uaecptr);
+extern void(*x_phys_put_byte)(uaecptr, uae_u32);
+extern void(*x_phys_put_word)(uaecptr, uae_u32);
+extern void(*x_phys_put_long)(uaecptr, uae_u32);
+
+#endif
diff --git a/src/cpu/newcpu.c b/src/cpu/newcpu.c
new file mode 100644
index 0000000..2666c61
--- /dev/null
+++ b/src/cpu/newcpu.c
@@ -0,0 +1,8571 @@
+/*
+* UAE - The Un*x Amiga Emulator
+*
+* MC68000 emulation
+*
+* (c) 1995 Bernd Schmidt
+*/
+
+#define MMUOP_DEBUG 2
+#define DEBUG_CD32CDTVIO 0
+#define EXCEPTION3_DEBUGGER 0
+#define CPUTRACE_DEBUG 0
+
+#define MORE_ACCURATE_68020_PIPELINE 1
+
+#include "main.h"
+#include "compat.h"
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+
+#include "hatari-glue.h"
+
+#include "options_cpu.h"
+#include "events.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "cpummu.h"
+#include "cpummu030.h"
+#include "cpu_prefetch.h"
+#include "savestate.h"
+#include "md-fpp.h"
+#ifdef WINUAE_FOR_HATARI
+#include "debug.h"
+#endif
+
+#include "m68000.h"
+#include "reset.h"
+#include "cycInt.h"
+#include "mfp.h"
+#include "tos.h"
+#include "vdi.h"
+#include "cart.h"
+#include "dialog.h"
+#include "bios.h"
+#include "xbios.h"
+#include "screen.h"
+#include "video.h"
+#include "options.h"
+#include "dsp.h"
+#include "log.h"
+#include "debugui.h"
+#include "debugcpu.h"
+#include "stMemory.h"
+
+
+#ifdef JIT
+#include "jit/compemu.h"
+#include 
+#else
+/* Need to have these somewhere */
+#ifndef WINUAE_FOR_HATARI
+bool check_prefs_changed_comp (void) { return false; }
+#endif
+#endif
+/* For faster JIT cycles handling */
+signed long pissoff = 0;
+
+/* Opcode of faulting instruction */
+static uae_u16 last_op_for_exception_3;
+/* PC at fault time */
+static uaecptr last_addr_for_exception_3;
+/* Address that generated the exception */
+static uaecptr last_fault_for_exception_3;
+/* read (0) or write (1) access */
+static bool last_writeaccess_for_exception_3;
+/* instruction (1) or data (0) access */
+static bool last_instructionaccess_for_exception_3;
+/* not instruction */
+static bool last_notinstruction_for_exception_3;
+/* set when writing exception stack frame */
+static int exception_in_exception;
+
+int mmu_enabled, mmu_triggered;
+int cpu_cycles;
+int bus_error_offset;
+#ifndef WINUAE_FOR_HATARI
+static int baseclock;
+#endif
+int m68k_pc_indirect;
+bool m68k_interrupt_delay;
+static bool m68k_reset_delay;
+static int cpu_prefs_changed_flag;
+
+int cpucycleunit;
+int cpu_tracer;
+
+const int areg_byteinc[] = { 1, 1, 1, 1, 1, 1, 1, 2 };
+const int imm8_table[] = { 8, 1, 2, 3, 4, 5, 6, 7 };
+
+int movem_index1[256];
+int movem_index2[256];
+int movem_next[256];
+
+cpuop_func *cpufunctbl[65536];
+
+struct cputbl_data
+{
+	uae_s16 length;
+	uae_s8 disp020[2];
+	uae_u8 branch;
+};
+static struct cputbl_data cpudatatbl[65536];
+
+struct mmufixup mmufixup[2];
+
+#define COUNT_INSTRS 0
+#define MC68060_PCR   0x04300000
+#define MC68EC060_PCR 0x04310000
+
+static uae_u64 fake_srp_030, fake_crp_030;
+static uae_u32 fake_tt0_030, fake_tt1_030, fake_tc_030;
+static uae_u16 fake_mmusr_030;
+
+static struct cache020 caches020[CACHELINES020];
+static struct cache030 icaches030[CACHELINES030];
+static struct cache030 dcaches030[CACHELINES030];
+static int icachelinecnt, dcachelinecnt;
+static struct cache040 icaches040[CACHESETS040];
+static struct cache040 dcaches040[CACHESETS040];
+
+
+#ifdef WINUAE_FOR_HATARI
+int OpcodeFamily;
+int BusCyclePenalty = 0;
+
+FILE *console_out_FILE = NULL;
+#endif
+
+
+#if COUNT_INSTRS
+static unsigned long int instrcount[65536];
+static uae_u16 opcodenums[65536];
+
+static int compfn (const void *el1, const void *el2)
+{
+	return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
+}
+
+static TCHAR *icountfilename (void)
+{
+	TCHAR *name = getenv ("INSNCOUNT");
+	if (name)
+		return name;
+	return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
+}
+
+void dump_counts (void)
+{
+	FILE *f = fopen (icountfilename (), "w");
+	unsigned long int total;
+	int i;
+
+	write_log (_T("Writing instruction count file...\n"));
+	for (i = 0; i < 65536; i++) {
+		opcodenums[i] = i;
+		total += instrcount[i];
+	}
+	qsort (opcodenums, 65536, sizeof (uae_u16), compfn);
+
+	fprintf (f, "Total: %lu\n", total);
+	for (i=0; i < 65536; i++) {
+		unsigned long int cnt = instrcount[opcodenums[i]];
+		struct instr *dp;
+		struct mnemolookup *lookup;
+		if (!cnt)
+			break;
+		dp = table68k + opcodenums[i];
+		for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
+			;
+		fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
+	}
+	fclose (f);
+}
+#else
+void dump_counts (void)
+{
+}
+#endif
+
+/*
+
+ ok, all this to "record" current instruction state
+ for later 100% cycle-exact restoring
+
+ */
+
+static uae_u32 (*x2_prefetch)(int);
+static uae_u32 (*x2_prefetch_long)(int);
+static uae_u32 (*x2_next_iword)(void);
+static uae_u32 (*x2_next_ilong)(void);
+static uae_u32 (*x2_get_ilong)(int);
+static uae_u32 (*x2_get_iword)(int);
+static uae_u32 (*x2_get_ibyte)(int);
+static uae_u32 (*x2_get_long)(uaecptr);
+static uae_u32 (*x2_get_word)(uaecptr);
+static uae_u32 (*x2_get_byte)(uaecptr);
+static void (*x2_put_long)(uaecptr,uae_u32);
+static void (*x2_put_word)(uaecptr,uae_u32);
+static void (*x2_put_byte)(uaecptr,uae_u32);
+static void (*x2_do_cycles)(unsigned long);
+static void (*x2_do_cycles_pre)(unsigned long);
+static void (*x2_do_cycles_post)(unsigned long, uae_u32);
+
+uae_u32 (*x_prefetch)(int);
+uae_u32 (*x_next_iword)(void);
+uae_u32 (*x_next_ilong)(void);
+uae_u32 (*x_get_ilong)(int);
+uae_u32 (*x_get_iword)(int);
+uae_u32 (*x_get_ibyte)(int);
+uae_u32 (*x_get_long)(uaecptr);
+uae_u32 (*x_get_word)(uaecptr);
+uae_u32 (*x_get_byte)(uaecptr);
+void (*x_put_long)(uaecptr,uae_u32);
+void (*x_put_word)(uaecptr,uae_u32);
+void (*x_put_byte)(uaecptr,uae_u32);
+
+uae_u32 (*x_cp_next_iword)(void);
+uae_u32 (*x_cp_next_ilong)(void);
+uae_u32 (*x_cp_get_long)(uaecptr);
+uae_u32 (*x_cp_get_word)(uaecptr);
+uae_u32 (*x_cp_get_byte)(uaecptr);
+void (*x_cp_put_long)(uaecptr,uae_u32);
+void (*x_cp_put_word)(uaecptr,uae_u32);
+void (*x_cp_put_byte)(uaecptr,uae_u32);
+uae_u32 (REGPARAM3 *x_cp_get_disp_ea_020)(uae_u32 base, int idx) REGPARAM;
+
+void (*x_do_cycles)(unsigned long);
+void (*x_do_cycles_pre)(unsigned long);
+void (*x_do_cycles_post)(unsigned long, uae_u32);
+
+uae_u32(*x_phys_get_iword)(uaecptr);
+uae_u32(*x_phys_get_ilong)(uaecptr);
+uae_u32(*x_phys_get_byte)(uaecptr);
+uae_u32(*x_phys_get_word)(uaecptr);
+uae_u32(*x_phys_get_long)(uaecptr);
+void(*x_phys_put_byte)(uaecptr, uae_u32);
+void(*x_phys_put_word)(uaecptr, uae_u32);
+void(*x_phys_put_long)(uaecptr, uae_u32);
+
+static void set_x_cp_funcs(void)
+{
+	x_cp_put_long = x_put_long;
+	x_cp_put_word = x_put_word;
+	x_cp_put_byte = x_put_byte;
+	x_cp_get_long = x_get_long;
+	x_cp_get_word = x_get_word;
+	x_cp_get_byte = x_get_byte;
+	x_cp_next_iword = x_next_iword;
+	x_cp_next_ilong = x_next_ilong;
+	x_cp_get_disp_ea_020 = x_get_disp_ea_020;
+
+	if (currprefs.mmu_model == 68030) {
+		x_cp_put_long = put_long_mmu030_state;
+		x_cp_put_word = put_word_mmu030_state;
+		x_cp_put_byte = put_byte_mmu030_state;
+		x_cp_get_long = get_long_mmu030_state;
+		x_cp_get_word = get_word_mmu030_state;
+		x_cp_get_byte = get_byte_mmu030_state;
+		x_cp_next_iword = next_iword_mmu030_state;
+		x_cp_next_ilong = next_ilong_mmu030_state;
+		x_cp_get_disp_ea_020 = get_disp_ea_020_mmu030;
+	}
+}
+
+static struct cputracestruct cputrace;
+
+#if CPUTRACE_DEBUG
+static void validate_trace (void)
+{
+	for (int i = 0; i < cputrace.memoryoffset; i++) {
+		struct cputracememory *ctm = &cputrace.ctm[i];
+		if (ctm->data == 0xdeadf00d) {
+			write_log (_T("unfinished write operation %d %08x\n"), i, ctm->addr);
+		}
+	}
+}
+#endif
+
+static void debug_trace (void)
+{
+	if (cputrace.writecounter > 10000 || cputrace.readcounter > 10000)
+		write_log (_T("cputrace.readcounter=%d cputrace.writecounter=%d\n"), cputrace.readcounter, cputrace.writecounter);
+}
+
+STATIC_INLINE void clear_trace (void)
+{
+#if CPUTRACE_DEBUG
+	validate_trace ();
+#endif
+	struct cputracememory *ctm = &cputrace.ctm[cputrace.memoryoffset++];
+	ctm->mode = 0;
+	cputrace.cyclecounter = 0;
+	cputrace.cyclecounter_pre = cputrace.cyclecounter_post = 0;
+}
+static void set_trace (uaecptr addr, int accessmode, int size)
+{
+#if CPUTRACE_DEBUG
+	validate_trace ();
+#endif
+	struct cputracememory *ctm = &cputrace.ctm[cputrace.memoryoffset++];
+	ctm->addr = addr;
+	ctm->data = 0xdeadf00d;
+	ctm->mode = accessmode | (size << 4);
+	cputrace.cyclecounter_pre = -1;
+	if (accessmode == 1)
+		cputrace.writecounter++;
+	else
+		cputrace.readcounter++;
+	debug_trace ();
+}
+static void add_trace (uaecptr addr, uae_u32 val, int accessmode, int size)
+{
+	if (cputrace.memoryoffset < 1) {
+#if CPUTRACE_DEBUG
+		write_log (_T("add_trace memoryoffset=%d!\n"), cputrace.memoryoffset);
+#endif
+		return;
+	}
+	int mode = accessmode | (size << 4);
+	struct cputracememory *ctm = &cputrace.ctm[cputrace.memoryoffset - 1];
+	ctm->addr = addr;
+	ctm->data = val;
+	if (!ctm->mode) {
+		ctm->mode = mode;
+		if (accessmode == 1)
+			cputrace.writecounter++;
+		else
+			cputrace.readcounter++;
+	}
+	debug_trace ();
+	cputrace.cyclecounter_pre = cputrace.cyclecounter_post = 0;
+}
+
+
+static void check_trace2 (void)
+{
+	if (cputrace.readcounter || cputrace.writecounter ||
+		cputrace.cyclecounter || cputrace.cyclecounter_pre || cputrace.cyclecounter_post)
+		write_log (_T("CPU tracer invalid state during playback!\n"));
+}
+
+static bool check_trace (void)
+{
+	if (!cpu_tracer)
+		return true;
+	if (!cputrace.readcounter && !cputrace.writecounter && !cputrace.cyclecounter) {
+		if (cpu_tracer != -2) {
+			write_log (_T("CPU trace: dma_cycle() enabled. %08x %08x NOW=%08lx\n"),
+				cputrace.cyclecounter_pre, cputrace.cyclecounter_post, get_cycles ());
+			cpu_tracer = -2; // dma_cycle() allowed to work now
+		}
+	}
+	if (cputrace.readcounter || cputrace.writecounter ||
+		cputrace.cyclecounter || cputrace.cyclecounter_pre || cputrace.cyclecounter_post)
+		return false;
+	x_prefetch = x2_prefetch;
+	x_get_ilong = x2_get_ilong;
+	x_get_iword = x2_get_iword;
+	x_get_ibyte = x2_get_ibyte;
+	x_next_iword = x2_next_iword;
+	x_next_ilong = x2_next_ilong;
+	x_put_long = x2_put_long;
+	x_put_word = x2_put_word;
+	x_put_byte = x2_put_byte;
+	x_get_long = x2_get_long;
+	x_get_word = x2_get_word;
+	x_get_byte = x2_get_byte;
+	x_do_cycles = x2_do_cycles;
+	x_do_cycles_pre = x2_do_cycles_pre;
+	x_do_cycles_post = x2_do_cycles_post;
+	set_x_cp_funcs();
+	write_log (_T("CPU tracer playback complete. STARTCYCLES=%08x NOWCYCLES=%08lx\n"), cputrace.startcycles, get_cycles ());
+	cputrace.needendcycles = 1;
+	cpu_tracer = 0;
+	return true;
+}
+
+static bool get_trace (uaecptr addr, int accessmode, int size, uae_u32 *data)
+{
+	int mode = accessmode | (size << 4);
+	int i;
+	for (i = 0; i < cputrace.memoryoffset; i++) {
+		struct cputracememory *ctm = &cputrace.ctm[i];
+		if (ctm->addr == addr && ctm->mode == mode) {
+			ctm->mode = 0;
+			write_log (_T("CPU trace: GET %d: PC=%08x %08x=%08x %d %d %08x/%08x/%08x %d/%d (%08lx)\n"),
+				i, cputrace.pc, addr, ctm->data, accessmode, size,
+				cputrace.cyclecounter, cputrace.cyclecounter_pre, cputrace.cyclecounter_post,
+				cputrace.readcounter, cputrace.writecounter, get_cycles ());
+			if (accessmode == 1)
+				cputrace.writecounter--;
+			else
+				cputrace.readcounter--;
+			if (cputrace.writecounter == 0 && cputrace.readcounter == 0) {
+				if (cputrace.cyclecounter_post) {
+					int c = cputrace.cyclecounter_post;
+					cputrace.cyclecounter_post = 0;
+					x_do_cycles (c);
+				} else if (cputrace.cyclecounter_pre) {
+					check_trace ();
+					*data = ctm->data;
+					return true; // argh, need to rerun the memory access..
+				}
+			}
+			check_trace ();
+			*data = ctm->data;
+			return false;
+		}
+	}
+	if (cputrace.cyclecounter_post) {
+		int c = cputrace.cyclecounter_post;
+		cputrace.cyclecounter_post = 0;
+		check_trace ();
+		check_trace2 ();
+		x_do_cycles (c);
+		return false;
+	}
+	gui_message (_T("CPU trace: GET %08x %d %d NOT FOUND!\n"), addr, accessmode, size);
+	check_trace ();
+	*data = 0;
+	return false;
+}
+
+static uae_u32 cputracefunc_x_prefetch (int o)
+{
+	uae_u32 pc = m68k_getpc ();
+	set_trace (pc + o, 2, 2);
+	uae_u32 v = x2_prefetch (o);
+	add_trace (pc + o, v, 2, 2);
+	return v;
+}
+static uae_u32 cputracefunc2_x_prefetch (int o)
+{
+	uae_u32 v;
+	if (get_trace (m68k_getpc () + o, 2, 2, &v)) {
+		v = x2_prefetch (o);
+		check_trace2 ();
+	}
+	return v;
+}
+
+static uae_u32 cputracefunc_x_next_iword (void)
+{
+	uae_u32 pc = m68k_getpc ();
+	set_trace (pc, 2, 2);
+	uae_u32 v = x2_next_iword ();
+	add_trace (pc, v, 2, 2);
+	return v;
+}
+static uae_u32 cputracefunc_x_next_ilong (void)
+{
+	uae_u32 pc = m68k_getpc ();
+	set_trace (pc, 2, 4);
+	uae_u32 v = x2_next_ilong ();
+	add_trace (pc, v, 2, 4);
+	return v;
+}
+static uae_u32 cputracefunc2_x_next_iword (void)
+{
+	uae_u32 v;
+	if (get_trace (m68k_getpc (), 2, 2, &v)) {
+		v = x2_next_iword ();
+		check_trace2 ();
+	}
+	return v;
+}
+static uae_u32 cputracefunc2_x_next_ilong (void)
+{
+	uae_u32 v;
+	if (get_trace (m68k_getpc (), 2, 4, &v)) {
+		v = x2_next_ilong ();
+		check_trace2 ();
+	}
+	return v;
+}
+
+static uae_u32 cputracefunc_x_get_ilong (int o)
+{
+	uae_u32 pc = m68k_getpc ();
+	set_trace (pc + o, 2, 4);
+	uae_u32 v = x2_get_ilong (o);
+	add_trace (pc + o, v, 2, 4);
+	return v;
+}
+static uae_u32 cputracefunc_x_get_iword (int o)
+{
+	uae_u32 pc = m68k_getpc ();
+	set_trace (pc + o, 2, 2);
+	uae_u32 v = x2_get_iword (o);
+	add_trace (pc + o, v, 2, 2);
+	return v;
+}
+static uae_u32 cputracefunc_x_get_ibyte (int o)
+{
+	uae_u32 pc = m68k_getpc ();
+	set_trace (pc + o, 2, 1);
+	uae_u32 v = x2_get_ibyte (o);
+	add_trace (pc + o, v, 2, 1);
+	return v;
+}
+static uae_u32 cputracefunc2_x_get_ilong (int o)
+{
+	uae_u32 v;
+	if (get_trace (m68k_getpc () + o, 2, 4, &v)) {
+		v = x2_get_ilong (o);
+		check_trace2 ();
+	}
+	return v;
+}
+static uae_u32 cputracefunc2_x_get_iword (int o)
+{
+	uae_u32 v;
+	if (get_trace (m68k_getpc () + o, 2, 2, &v)) {
+		v = x2_get_iword (o);
+		check_trace2 ();
+	}
+	return v;
+}
+static uae_u32 cputracefunc2_x_get_ibyte (int o)
+{
+	uae_u32 v;
+	if (get_trace (m68k_getpc () + o, 2, 1, &v)) {
+		v = x2_get_ibyte (o);
+		check_trace2 ();
+	}
+	return v;
+}
+
+static uae_u32 cputracefunc_x_get_long (uaecptr o)
+{
+	set_trace (o, 0, 4);
+	uae_u32 v = x2_get_long (o);
+	add_trace (o, v, 0, 4);
+	return v;
+}
+static uae_u32 cputracefunc_x_get_word (uaecptr o)
+{
+	set_trace (o, 0, 2);
+	uae_u32 v = x2_get_word (o);
+	add_trace (o, v, 0, 2);
+	return v;
+}
+static uae_u32 cputracefunc_x_get_byte (uaecptr o)
+{
+	set_trace (o, 0, 1);
+	uae_u32 v = x2_get_byte (o);
+	add_trace (o, v, 0, 1);
+	return v;
+}
+static uae_u32 cputracefunc2_x_get_long (uaecptr o)
+{
+	uae_u32 v;
+	if (get_trace (o, 0, 4, &v)) {
+		v = x2_get_long (o);
+		check_trace2 ();
+	}
+	return v;
+}
+static uae_u32 cputracefunc2_x_get_word (uaecptr o)
+{
+	uae_u32 v;
+	if (get_trace (o, 0, 2, &v)) {
+		v = x2_get_word (o);
+		check_trace2 ();
+	}
+	return v;
+}
+static uae_u32 cputracefunc2_x_get_byte (uaecptr o)
+{
+	uae_u32 v;
+	if (get_trace (o, 0, 1, &v)) {
+		v = x2_get_byte (o);
+		check_trace2 ();
+	}
+	return v;
+}
+
+static void cputracefunc_x_put_long (uaecptr o, uae_u32 val)
+{
+	clear_trace ();
+	add_trace (o, val, 1, 4);
+	x2_put_long (o, val);
+}
+static void cputracefunc_x_put_word (uaecptr o, uae_u32 val)
+{
+	clear_trace ();
+	add_trace (o, val, 1, 2);
+	x2_put_word (o, val);
+}
+static void cputracefunc_x_put_byte (uaecptr o, uae_u32 val)
+{
+	clear_trace ();
+	add_trace (o, val, 1, 1);
+	x2_put_byte (o, val);
+}
+static void cputracefunc2_x_put_long (uaecptr o, uae_u32 val)
+{
+	uae_u32 v;
+	if (get_trace (o, 1, 4, &v)) {
+		x2_put_long (o, val);
+		check_trace2 ();
+	}
+	if (v != val)
+		write_log (_T("cputracefunc2_x_put_long %d <> %d\n"), v, val);
+}
+static void cputracefunc2_x_put_word (uaecptr o, uae_u32 val)
+{
+	uae_u32 v;
+	if (get_trace (o, 1, 2, &v)) {
+		x2_put_word (o, val);
+		check_trace2 ();
+	}
+	if (v != val)
+		write_log (_T("cputracefunc2_x_put_word %d <> %d\n"), v, val);
+}
+static void cputracefunc2_x_put_byte (uaecptr o, uae_u32 val)
+{
+	uae_u32 v;
+	if (get_trace (o, 1, 1, &v)) {
+		x2_put_byte (o, val);
+		check_trace2 ();
+	}
+	if (v != val)
+		write_log (_T("cputracefunc2_x_put_byte %d <> %d\n"), v, val);
+}
+
+static void cputracefunc_x_do_cycles (unsigned long cycles)
+{
+	while (cycles >= CYCLE_UNIT) {
+		cputrace.cyclecounter += CYCLE_UNIT;
+		cycles -= CYCLE_UNIT;
+		x2_do_cycles (CYCLE_UNIT);
+	}
+	if (cycles > 0) {
+		cputrace.cyclecounter += cycles;
+		x2_do_cycles (cycles);
+	}
+}
+
+static void cputracefunc2_x_do_cycles (unsigned long cycles)
+{
+	if (cputrace.cyclecounter > (long)cycles) {
+		cputrace.cyclecounter -= cycles;
+		return;
+	}
+	cycles -= cputrace.cyclecounter;
+	cputrace.cyclecounter = 0;
+	check_trace ();
+	x_do_cycles = x2_do_cycles;
+	if (cycles > 0)
+		x_do_cycles (cycles);
+}
+
+static void cputracefunc_x_do_cycles_pre (unsigned long cycles)
+{
+	cputrace.cyclecounter_post = 0;
+	cputrace.cyclecounter_pre = 0;
+	while (cycles >= CYCLE_UNIT) {
+		cycles -= CYCLE_UNIT;
+		cputrace.cyclecounter_pre += CYCLE_UNIT;
+		x2_do_cycles (CYCLE_UNIT);
+	}
+	if (cycles > 0) {
+		x2_do_cycles (cycles);
+		cputrace.cyclecounter_pre += cycles;
+	}
+	cputrace.cyclecounter_pre = 0;
+}
+// cyclecounter_pre = how many cycles we need to SWALLOW
+// -1 = rerun whole access
+static void cputracefunc2_x_do_cycles_pre (unsigned long cycles)
+{
+	if (cputrace.cyclecounter_pre == -1) {
+		cputrace.cyclecounter_pre = 0;
+		check_trace ();
+		check_trace2 ();
+		x_do_cycles (cycles);
+		return;
+	}
+	if (cputrace.cyclecounter_pre > (long)cycles) {
+		cputrace.cyclecounter_pre -= cycles;
+		return;
+	}
+	cycles -= cputrace.cyclecounter_pre;
+	cputrace.cyclecounter_pre = 0;
+	check_trace ();
+	if (cycles > 0)
+		x_do_cycles (cycles);
+}
+
+static void cputracefunc_x_do_cycles_post (unsigned long cycles, uae_u32 v)
+{
+	if (cputrace.memoryoffset < 1) {
+#if CPUTRACE_DEBUG
+		write_log (_T("cputracefunc_x_do_cycles_post memoryoffset=%d!\n"), cputrace.memoryoffset);
+#endif
+		return;
+	}
+	struct cputracememory *ctm = &cputrace.ctm[cputrace.memoryoffset - 1];
+	ctm->data = v;
+	cputrace.cyclecounter_post = cycles;
+	cputrace.cyclecounter_pre = 0;
+	while (cycles >= CYCLE_UNIT) {
+		cycles -= CYCLE_UNIT;
+		cputrace.cyclecounter_post -= CYCLE_UNIT;
+		x2_do_cycles (CYCLE_UNIT);
+	}
+	if (cycles > 0) {
+		cputrace.cyclecounter_post -= cycles;
+		x2_do_cycles (cycles);
+	}
+	cputrace.cyclecounter_post = 0;
+}
+// cyclecounter_post = how many cycles we need to WAIT
+static void cputracefunc2_x_do_cycles_post (unsigned long cycles, uae_u32 v)
+{
+	uae_u32 c;
+	if (cputrace.cyclecounter_post) {
+		c = cputrace.cyclecounter_post;
+		cputrace.cyclecounter_post = 0;
+	} else {
+		c = cycles;
+	}
+	check_trace ();
+	if (c > 0)
+		x_do_cycles (c);
+}
+
+static void do_cycles_post (unsigned long cycles, uae_u32 v)
+{
+	do_cycles (cycles);
+}
+static void do_cycles_ce_post (unsigned long cycles, uae_u32 v)
+{
+	do_cycles_ce (cycles);
+}
+static void do_cycles_ce020_post (unsigned long cycles, uae_u32 v)
+{
+#ifndef WINUAE_FOR_HATARI
+	do_cycles_ce020 (cycles);
+#else
+	do_cycles_ce020_long (cycles);
+#endif
+}
+
+static void set_x_ifetches(void)
+{
+	if (m68k_pc_indirect) {
+		if (currprefs.cachesize) {
+			// indirect via addrbank
+			x_get_ilong = get_iilong_jit;
+			x_get_iword = get_iiword_jit;
+			x_get_ibyte = get_iibyte_jit;
+			x_next_iword = next_iiword_jit;
+			x_next_ilong = next_iilong_jit;
+		} else {
+			// indirect via addrbank
+			x_get_ilong = get_iilong;
+			x_get_iword = get_iiword;
+			x_get_ibyte = get_iibyte;
+			x_next_iword = next_iiword;
+			x_next_ilong = next_iilong;
+		}
+	} else {
+		// direct to memory
+		x_get_ilong = get_dilong;
+		x_get_iword = get_diword;
+		x_get_ibyte = get_dibyte;
+		x_next_iword = next_diword;
+		x_next_ilong = next_dilong;
+	}
+}
+
+// indirect memory access functions
+static void set_x_funcs (void)
+{
+	if (currprefs.mmu_model) {
+		if (currprefs.cpu_model == 68060) {
+			x_prefetch = get_iword_mmu060;
+			x_get_ilong = get_ilong_mmu060;
+			x_get_iword = get_iword_mmu060;
+			x_get_ibyte = get_ibyte_mmu060;
+			x_next_iword = next_iword_mmu060;
+			x_next_ilong = next_ilong_mmu060;
+			x_put_long = put_long_mmu060;
+			x_put_word = put_word_mmu060;
+			x_put_byte = put_byte_mmu060;
+			x_get_long = get_long_mmu060;
+			x_get_word = get_word_mmu060;
+			x_get_byte = get_byte_mmu060;
+		} else if (currprefs.cpu_model == 68040) {
+			x_prefetch = get_iword_mmu040;
+			x_get_ilong = get_ilong_mmu040;
+			x_get_iword = get_iword_mmu040;
+			x_get_ibyte = get_ibyte_mmu040;
+			x_next_iword = next_iword_mmu040;
+			x_next_ilong = next_ilong_mmu040;
+			x_put_long = put_long_mmu040;
+			x_put_word = put_word_mmu040;
+			x_put_byte = put_byte_mmu040;
+			x_get_long = get_long_mmu040;
+			x_get_word = get_word_mmu040;
+			x_get_byte = get_byte_mmu040;
+		} else {
+			x_prefetch = get_iword_mmu030;
+			x_get_ilong = get_ilong_mmu030;
+			x_get_iword = get_iword_mmu030;
+			x_get_ibyte = get_ibyte_mmu030;
+			x_next_iword = next_iword_mmu030;
+			x_next_ilong = next_ilong_mmu030;
+			x_put_long = put_long_mmu030;
+			x_put_word = put_word_mmu030;
+			x_put_byte = put_byte_mmu030;
+			x_get_long = get_long_mmu030;
+			x_get_word = get_word_mmu030;
+			x_get_byte = get_byte_mmu030;
+		}
+		x_do_cycles = do_cycles;
+		x_do_cycles_pre = do_cycles;
+		x_do_cycles_post = do_cycles_post;
+	} else if (currprefs.cpu_model < 68020) {
+		// 68000/010
+		if (currprefs.cpu_cycle_exact) {
+			x_prefetch = get_word_ce000_prefetch;
+			x_get_ilong = NULL;
+			x_get_iword = get_wordi_ce000;
+			x_get_ibyte = NULL;
+			x_next_iword = NULL;
+			x_next_ilong = NULL;
+			x_put_long = put_long_ce000;
+			x_put_word = put_word_ce000;
+			x_put_byte = put_byte_ce000;
+			x_get_long = get_long_ce000;
+			x_get_word = get_word_ce000;
+			x_get_byte = get_byte_ce000;
+			x_do_cycles = do_cycles_ce;
+			x_do_cycles_pre = do_cycles_ce;
+			x_do_cycles_post = do_cycles_ce_post;
+		} else if (currprefs.cpu_compatible) {
+			x_prefetch = get_word_prefetch;
+			x_get_ilong = NULL;
+			x_get_iword = get_iiword;
+			x_get_ibyte = get_iibyte;
+			x_next_iword = NULL;
+			x_next_ilong = NULL;
+			x_put_long = put_long;
+			x_put_word = put_word;
+			x_put_byte = put_byte;
+			x_get_long = get_long;
+			x_get_word = get_word;
+			x_get_byte = get_byte;
+			x_do_cycles = do_cycles;
+			x_do_cycles_pre = do_cycles;
+			x_do_cycles_post = do_cycles_post;
+		} else {
+			x_prefetch = NULL;
+			x_get_ilong = get_dilong;
+			x_get_iword = get_diword;
+			x_get_ibyte = get_dibyte;
+			x_next_iword = next_diword;
+			x_next_ilong = next_dilong;
+			x_put_long = put_long;
+			x_put_word = put_word;
+			x_put_byte = put_byte;
+			x_get_long = get_long;
+			x_get_word = get_word;
+			x_get_byte = get_byte;
+			x_do_cycles = do_cycles;
+			x_do_cycles_pre = do_cycles;
+			x_do_cycles_post = do_cycles_post;
+		}
+	} else if (!currprefs.cpu_cycle_exact) {
+		// 68020+ no ce
+		if (currprefs.cpu_compatible) {
+			if (currprefs.cpu_model == 68020 && !currprefs.cachesize) {
+				x_prefetch = get_word_prefetch;
+				x_get_ilong = get_long_020_prefetch;
+				x_get_iword = get_word_020_prefetch;
+				x_get_ibyte = NULL;
+				x_next_iword = next_iword_020_prefetch;
+				x_next_ilong = next_ilong_020_prefetch;
+				x_put_long = put_long;
+				x_put_word = put_word;
+				x_put_byte = put_byte;
+				x_get_long = get_long;
+				x_get_word = get_word;
+				x_get_byte = get_byte;
+				x_do_cycles = do_cycles;
+				x_do_cycles_pre = do_cycles;
+				x_do_cycles_post = do_cycles_post;
+			} else if (currprefs.cpu_model == 68030 && !currprefs.cachesize) {
+				x_prefetch = get_word_prefetch;
+				x_get_ilong = get_long_030_prefetch;
+				x_get_iword = get_word_030_prefetch;
+				x_get_ibyte = NULL;
+				x_next_iword = next_iword_030_prefetch;
+				x_next_ilong = next_ilong_030_prefetch;
+				x_put_long = put_long;
+				x_put_word = put_word;
+				x_put_byte = put_byte;
+				x_get_long = get_long;
+				x_get_word = get_word;
+				x_get_byte = get_byte;
+				x_do_cycles = do_cycles;
+				x_do_cycles_pre = do_cycles;
+				x_do_cycles_post = do_cycles_post;
+			} else if (currprefs.cpu_model < 68040) {
+				// JIT or 68030+ does not have real prefetch only emulation
+				x_prefetch = NULL;
+				set_x_ifetches();
+				x_put_long = put_long;
+				x_put_word = put_word;
+				x_put_byte = put_byte;
+				x_get_long = get_long;
+				x_get_word = get_word;
+				x_get_byte = get_byte;
+				x_do_cycles = do_cycles;
+				x_do_cycles_pre = do_cycles;
+				x_do_cycles_post = do_cycles_post;
+			} else {
+				x_prefetch = NULL;
+				x_get_ilong = get_ilong_cache_040;
+				x_get_iword = get_iword_cache_040;
+				x_get_ibyte = NULL;
+				x_next_iword = next_iword_cache040;
+				x_next_ilong = next_ilong_cache040;
+				x_put_long = put_long_cache_040;
+				x_put_word = put_word_cache_040;
+				x_put_byte = put_byte_cache_040;
+				x_get_long = get_long_cache_040;
+				x_get_word = get_word_cache_040;
+				x_get_byte = get_byte_cache_040;
+				x_do_cycles = do_cycles;
+				x_do_cycles_pre = do_cycles;
+				x_do_cycles_post = do_cycles_post;
+			}
+		} else {
+			x_prefetch = NULL;
+			set_x_ifetches();
+			x_put_long = put_long;
+			x_put_word = put_word;
+			x_put_byte = put_byte;
+			x_get_long = get_long;
+			x_get_word = get_word;
+			x_get_byte = get_byte;
+			x_do_cycles = do_cycles;
+			x_do_cycles_pre = do_cycles;
+			x_do_cycles_post = do_cycles_post;
+		}
+		// 68020+ cycle exact
+	} else if (currprefs.cpu_model == 68020) {
+		x_prefetch = get_word_ce020_prefetch;
+		x_get_ilong = get_long_ce020_prefetch;
+		x_get_iword = get_word_ce020_prefetch;
+		x_get_ibyte = NULL;
+		x_next_iword = next_iword_020ce;
+		x_next_ilong = next_ilong_020ce;
+		x_put_long = put_long_ce020;
+		x_put_word = put_word_ce020;
+		x_put_byte = put_byte_ce020;
+		x_get_long = get_long_ce020;
+		x_get_word = get_word_ce020;
+		x_get_byte = get_byte_ce020;
+#ifndef WINUAE_FOR_HATARI
+		x_do_cycles = do_cycles_ce020;
+		x_do_cycles_pre = do_cycles_ce020;
+		x_do_cycles_post = do_cycles_ce020_post;
+#else
+		x_do_cycles = do_cycles_ce020_long;
+		x_do_cycles_pre = do_cycles_ce020_long;
+		x_do_cycles_post = do_cycles_ce020_post;
+#endif
+	} else if (currprefs.cpu_model == 68030) {
+		x_prefetch = get_word_ce030_prefetch;
+		x_get_ilong = get_long_ce030_prefetch;
+		x_get_iword = get_word_ce030_prefetch;
+		x_get_ibyte = NULL;
+		x_next_iword = next_iword_030ce;
+		x_next_ilong = next_ilong_030ce;
+		x_put_long = put_long_ce030;
+		x_put_word = put_word_ce030;
+		x_put_byte = put_byte_ce030;
+		x_get_long = get_long_ce030;
+		x_get_word = get_word_ce030;
+		x_get_byte = get_byte_ce030;
+#ifndef WINUAE_FOR_HATARI
+		x_do_cycles = do_cycles_ce020;
+		x_do_cycles_pre = do_cycles_ce020;
+		x_do_cycles_post = do_cycles_ce020_post;
+#else
+		x_do_cycles = do_cycles_ce020_long;
+		x_do_cycles_pre = do_cycles_ce020_long;
+		x_do_cycles_post = do_cycles_ce020_post;
+#endif
+	} else if (currprefs.cpu_model >= 68040) {
+		x_prefetch = NULL;
+		x_get_ilong = get_ilong_cache_040;
+		x_get_iword = get_iword_cache_040;
+		x_get_ibyte = NULL;
+		x_next_iword = next_iword_cache040;
+		x_next_ilong = next_ilong_cache040;
+		x_put_long = put_long_cache_040;
+		x_put_word = put_word_cache_040;
+		x_put_byte = put_byte_cache_040;
+		x_get_long = get_long_cache_040;
+		x_get_word = get_word_cache_040;
+		x_get_byte = get_byte_cache_040;
+#ifndef WINUAE_FOR_HATARI
+		x_do_cycles = do_cycles_ce020;
+		x_do_cycles_pre = do_cycles_ce020;
+		x_do_cycles_post = do_cycles_ce020_post;
+#else
+		x_do_cycles = do_cycles_ce020_long;
+		x_do_cycles_pre = do_cycles_ce020_long;
+		x_do_cycles_post = do_cycles_ce020_post;
+#endif
+	}
+	x2_prefetch = x_prefetch;
+	x2_get_ilong = x_get_ilong;
+	x2_get_iword = x_get_iword;
+	x2_get_ibyte = x_get_ibyte;
+	x2_next_iword = x_next_iword;
+	x2_next_ilong = x_next_ilong;
+	x2_put_long = x_put_long;
+	x2_put_word = x_put_word;
+	x2_put_byte = x_put_byte;
+	x2_get_long = x_get_long;
+	x2_get_word = x_get_word;
+	x2_get_byte = x_get_byte;
+	x2_do_cycles = x_do_cycles;
+	x2_do_cycles_pre = x_do_cycles_pre;
+	x2_do_cycles_post = x_do_cycles_post;
+
+	if (cpu_tracer > 0) {
+		x_prefetch = cputracefunc_x_prefetch;
+		x_get_ilong = cputracefunc_x_get_ilong;
+		x_get_iword = cputracefunc_x_get_iword;
+		x_get_ibyte = cputracefunc_x_get_ibyte;
+		x_next_iword = cputracefunc_x_next_iword;
+		x_next_ilong = cputracefunc_x_next_ilong;
+		x_put_long = cputracefunc_x_put_long;
+		x_put_word = cputracefunc_x_put_word;
+		x_put_byte = cputracefunc_x_put_byte;
+		x_get_long = cputracefunc_x_get_long;
+		x_get_word = cputracefunc_x_get_word;
+		x_get_byte = cputracefunc_x_get_byte;
+		x_do_cycles = cputracefunc_x_do_cycles;
+		x_do_cycles_pre = cputracefunc_x_do_cycles_pre;
+		x_do_cycles_post = cputracefunc_x_do_cycles_post;
+	} else if (cpu_tracer < 0) {
+		if (!check_trace ()) {
+			x_prefetch = cputracefunc2_x_prefetch;
+			x_get_ilong = cputracefunc2_x_get_ilong;
+			x_get_iword = cputracefunc2_x_get_iword;
+			x_get_ibyte = cputracefunc2_x_get_ibyte;
+			x_next_iword = cputracefunc2_x_next_iword;
+			x_next_ilong = cputracefunc2_x_next_ilong;
+			x_put_long = cputracefunc2_x_put_long;
+			x_put_word = cputracefunc2_x_put_word;
+			x_put_byte = cputracefunc2_x_put_byte;
+			x_get_long = cputracefunc2_x_get_long;
+			x_get_word = cputracefunc2_x_get_word;
+			x_get_byte = cputracefunc2_x_get_byte;
+			x_do_cycles = cputracefunc2_x_do_cycles;
+			x_do_cycles_pre = cputracefunc2_x_do_cycles_pre;
+			x_do_cycles_post = cputracefunc2_x_do_cycles_post;
+		}
+	}
+
+	set_x_cp_funcs();
+	mmu_set_funcs();
+	mmu030_set_funcs();
+
+}
+
+bool can_cpu_tracer (void)
+{
+	return (currprefs.cpu_model == 68000 || currprefs.cpu_model == 68020) && currprefs.cpu_cycle_exact;
+}
+
+bool is_cpu_tracer (void)
+{
+	return cpu_tracer > 0;
+}
+bool set_cpu_tracer (bool state)
+{
+	if (cpu_tracer < 0)
+		return false;
+	int old = cpu_tracer;
+#ifndef WINUAE_FOR_HATARI
+	if (input_record)
+		state = true;
+#endif
+	cpu_tracer = 0;
+	if (state && can_cpu_tracer ()) {
+		cpu_tracer = 1;
+		set_x_funcs ();
+		if (old != cpu_tracer)
+			write_log (_T("CPU tracer enabled\n"));
+	}
+	if (old > 0 && state == false) {
+		set_x_funcs ();
+		write_log (_T("CPU tracer disabled\n"));
+	}
+	return is_cpu_tracer ();
+}
+
+void flush_cpu_caches(bool force)
+{
+	bool doflush = currprefs.cpu_compatible || currprefs.cpu_cycle_exact;
+	int i;
+
+	if (currprefs.cpu_model == 68020) {
+		if (regs.cacr & 0x08) { // clear instr cache
+			for (i = 0; i < CACHELINES020; i++)
+				caches020[i].valid = 0;
+			regs.cacr &= ~0x08;
+		}
+		if (regs.cacr & 0x04) { // clear entry in instr cache
+			caches020[(regs.caar >> 2) & (CACHELINES020 - 1)].valid = 0;
+			regs.cacr &= ~0x04;
+		}
+	} else if (currprefs.cpu_model == 68030) {
+		if (regs.cacr & 0x08) { // clear instr cache
+			if (doflush) {
+				for (i = 0; i < CACHELINES030; i++) {
+					icaches030[i].valid[0] = 0;
+					icaches030[i].valid[1] = 0;
+					icaches030[i].valid[2] = 0;
+					icaches030[i].valid[3] = 0;
+				}
+			}
+			regs.cacr &= ~0x08;
+		}
+		if (regs.cacr & 0x04) { // clear entry in instr cache
+			icaches030[(regs.caar >> 4) & (CACHELINES030 - 1)].valid[(regs.caar >> 2) & 3] = 0;
+			regs.cacr &= ~0x04;
+		}
+		if (regs.cacr & 0x800) { // clear data cache
+			if (doflush) {
+				for (i = 0; i < CACHELINES030; i++) {
+					dcaches030[i].valid[0] = 0;
+					dcaches030[i].valid[1] = 0;
+					dcaches030[i].valid[2] = 0;
+					dcaches030[i].valid[3] = 0;
+				}
+			}
+			regs.cacr &= ~0x800;
+		}
+		if (regs.cacr & 0x400) { // clear entry in data cache
+			dcaches030[(regs.caar >> 4) & (CACHELINES030 - 1)].valid[(regs.caar >> 2) & 3] = 0;
+			regs.cacr &= ~0x400;
+		}
+	} else if (currprefs.cpu_model >= 68040) {
+		icachelinecnt = 0;
+		dcachelinecnt = 0;
+		if (doflush) {
+			for (i = 0; i < CACHESETS040; i++) {
+				icaches040[i].valid[0] = 0;
+				icaches040[i].valid[1] = 0;
+				icaches040[i].valid[2] = 0;
+				icaches040[i].valid[3] = 0;
+			}
+		}
+	}
+}
+
+void flush_cpu_caches_040(uae_u16 opcode)
+{
+	int cache = (opcode >> 6) & 3;
+	if (!(cache & 2))
+			return;
+	flush_cpu_caches(true);
+}
+
+void set_cpu_caches (bool flush)
+{
+	regs.prefetch020addr = 0xffffffff;
+	regs.cacheholdingaddr020 = 0xffffffff;
+
+#ifdef JIT
+	if (currprefs.cachesize) {
+		if (currprefs.cpu_model < 68040) {
+			set_cache_state (regs.cacr & 1);
+			if (regs.cacr & 0x08) {
+				flush_icache (0, 3);
+			}
+		} else {
+			set_cache_state ((regs.cacr & 0x8000) ? 1 : 0);
+		}
+	}
+#endif
+	flush_cpu_caches(flush);
+}
+
+STATIC_INLINE void count_instr (unsigned int opcode)
+{
+}
+
+static uae_u32 REGPARAM2 op_illg_1 (uae_u32 opcode)
+{
+	op_illg (opcode);
+	return 4;
+}
+static uae_u32 REGPARAM2 op_unimpl_1 (uae_u32 opcode)
+{
+	if ((opcode & 0xf000) == 0xf000 || currprefs.cpu_model < 68060)
+		op_illg (opcode);
+	else
+		op_unimpl (opcode);
+	return 4;
+}
+
+// generic+direct, generic+indirect, more compatible, cycle-exact, mmu
+static const struct cputbl *cputbls[6][5] =
+{
+	// 68000
+	{ op_smalltbl_5_ff, op_smalltbl_45_ff, op_smalltbl_12_ff, op_smalltbl_14_ff, NULL },
+	// 68010
+	{ op_smalltbl_4_ff, op_smalltbl_44_ff, op_smalltbl_11_ff, op_smalltbl_13_ff, NULL },
+	// 68020
+	{ op_smalltbl_3_ff, op_smalltbl_43_ff, op_smalltbl_20_ff, op_smalltbl_21_ff, NULL },
+	// 68030
+	{ op_smalltbl_2_ff, op_smalltbl_42_ff, op_smalltbl_22_ff, op_smalltbl_23_ff, op_smalltbl_32_ff },
+	// 68040
+	{ op_smalltbl_1_ff, op_smalltbl_41_ff, op_smalltbl_25_ff, op_smalltbl_25_ff, op_smalltbl_31_ff },
+	// 68060
+	{ op_smalltbl_0_ff, op_smalltbl_40_ff, op_smalltbl_24_ff, op_smalltbl_24_ff, op_smalltbl_33_ff }
+};
+
+static void build_cpufunctbl (void)
+{
+	int i, opcnt;
+	unsigned long opcode;
+	const struct cputbl *tbl = 0;
+	int lvl, mode;
+
+	if (!currprefs.cachesize) {
+		if (currprefs.mmu_model)
+			mode = 4;
+		else if (currprefs.cpu_cycle_exact)
+			mode = 3;
+		else if (currprefs.cpu_compatible)
+			mode = 2;
+		else
+			mode = 0;
+		m68k_pc_indirect = mode != 0 ? 1 : 0;
+	} else {
+		mode = 0;
+		m68k_pc_indirect = 0;
+		if (currprefs.comptrustbyte) {
+			mode = 1;
+			m68k_pc_indirect = -1;
+		}
+	}
+	lvl = (currprefs.cpu_model - 68000) / 10;
+	if (lvl == 6)
+		lvl = 5;
+	tbl = cputbls[lvl][mode];
+
+	if (tbl == NULL) {
+		write_log (_T("no CPU emulation cores available CPU=%d!"), currprefs.cpu_model);
+		abort ();
+	}
+
+	for (opcode = 0; opcode < 65536; opcode++)
+		cpufunctbl[opcode] = op_illg_1;
+	for (i = 0; tbl[i].handler != NULL; i++) {
+		opcode = tbl[i].opcode;
+		cpufunctbl[opcode] = tbl[i].handler;
+		cpudatatbl[opcode].length = tbl[i].length;
+		cpudatatbl[opcode].disp020[0] = tbl[i].disp020[0];
+		cpudatatbl[opcode].disp020[1] = tbl[i].disp020[1];
+		cpudatatbl[opcode].branch = tbl[i].branch;
+	}
+
+	/* hack fpu to 68000/68010 mode */
+	if (currprefs.fpu_model && currprefs.cpu_model < 68020) {
+		tbl = op_smalltbl_3_ff;
+		for (i = 0; tbl[i].handler != NULL; i++) {
+			if ((tbl[i].opcode & 0xfe00) == 0xf200) {
+				cpufunctbl[tbl[i].opcode] = tbl[i].handler;
+				cpudatatbl[tbl[i].opcode].length = tbl[i].length;
+				cpudatatbl[tbl[i].opcode].disp020[0] = tbl[i].disp020[0];
+				cpudatatbl[tbl[i].opcode].disp020[1] = tbl[i].disp020[1];
+				cpudatatbl[tbl[i].opcode].branch = tbl[i].branch;
+			}
+		}
+	}
+
+	opcnt = 0;
+	for (opcode = 0; opcode < 65536; opcode++) {
+		cpuop_func *f;
+		struct instr *table = &table68k[opcode];
+
+		if (table->mnemo == i_ILLG)
+			continue;		
+
+		/* unimplemented opcode? */
+		if (table->unimpclev > 0 && lvl >= table->unimpclev) {
+			if (currprefs.int_no_unimplemented && currprefs.cpu_model == 68060) {
+				cpufunctbl[opcode] = op_unimpl_1;
+				continue;
+			} else {
+				// emulate 68060 unimplemented instructions if int_no_unimplemented=false
+				if (currprefs.cpu_model != 68060 && table->unimpclev != 5) {
+					cpufunctbl[opcode] = op_illg_1;
+					continue;
+				}
+			}
+		}
+
+		if (currprefs.fpu_model && currprefs.cpu_model < 68020) {
+			/* more hack fpu to 68000/68010 mode */
+			if (table->clev > lvl && (opcode & 0xfe00) != 0xf200)
+				continue;
+		} else if (table->clev > lvl) {
+			continue;
+		}
+
+		if (table->handler != -1) {
+			int idx = table->handler;
+			f = cpufunctbl[idx];
+			if (f == op_illg_1)
+				abort ();
+			cpufunctbl[opcode] = f;
+			memcpy(&cpudatatbl[opcode], &cpudatatbl[idx], sizeof(struct cputbl_data));
+			opcnt++;
+		}
+	}
+	write_log (_T("Building CPU, %d opcodes (%d %d %d)\n"),
+		opcnt, lvl,
+		currprefs.cpu_cycle_exact ? -1 : currprefs.cpu_compatible ? 1 : 0, currprefs.address_space_24);
+#ifdef JIT
+	build_comp ();
+#endif
+
+	write_log(_T("CPU=%d, FPU=%d, MMU=%d, JIT%s=%d."),
+			  currprefs.cpu_model, currprefs.fpu_model,
+			  currprefs.mmu_model,
+			  currprefs.cachesize ? (currprefs.compfpu ? _T("=CPU/FPU") : _T("=CPU")) : _T(""),
+			  currprefs.cachesize);
+
+	regs.address_space_mask = 0xffffffff;
+#ifndef WINUAE_FOR_HATARI
+	if (currprefs.cpu_compatible) {
+		if (currprefs.address_space_24 && currprefs.cpu_model >= 68040)
+			currprefs.address_space_24 = false;
+	}
+#else
+	/* Hatari : don't force address_space_24=0 for 68030, as the Falcon has a 68030 LC with only 24 bits */
+	/* TODO ? Force address_space_24=0 for 68040 ? */
+#endif
+	m68k_interrupt_delay = false;
+	if (currprefs.cpu_cycle_exact) {
+		if (tbl == op_smalltbl_14_ff || tbl == op_smalltbl_13_ff || tbl == op_smalltbl_21_ff || tbl == op_smalltbl_23_ff)
+			m68k_interrupt_delay = true;
+	}
+
+	if (currprefs.cpu_cycle_exact) {
+		if (currprefs.cpu_model == 68000)
+			write_log(_T(" prefetch and cycle-exact"));
+		else
+			write_log(_T(" ~cycle-exact"));
+	} else if (currprefs.cpu_compatible) {
+		if (currprefs.cpu_model <= 68020) {
+			write_log(_T(" prefetch"));
+		} else {
+			write_log(_T(" fake prefetch"));
+		}
+	}
+	if (currprefs.m68k_speed < 0)
+		write_log(_T(" fast"));
+	if (currprefs.int_no_unimplemented && currprefs.cpu_model == 68060) {
+		write_log(_T(" no unimplemented integer instructions"));
+	}
+	if (currprefs.fpu_no_unimplemented && currprefs.fpu_model) {
+		write_log(_T(" no unimplemented floating point instructions"));
+	}
+	if (currprefs.address_space_24) {
+		regs.address_space_mask = 0x00ffffff;
+		write_log(_T(" 24-bit"));
+	}
+	write_log(_T("\n"));
+
+	set_cpu_caches (true);
+}
+
+#define CYCLES_DIV 8192
+static unsigned long cycles_mult;
+
+static void update_68k_cycles (void)
+{
+fprintf ( stderr , "update cyc speed %d throttle %f clock_mult %d\n", currprefs.m68k_speed, currprefs.m68k_speed_throttle, changed_prefs.cpu_clock_multiplier );
+	cycles_mult = 0;
+#ifndef WINUAE_FOR_HATARI
+	/* [NP] Don't adjust cycles_mult in Hatari and ignore m68k_speed (forced to 0) */
+	if (currprefs.m68k_speed >= 0 && !currprefs.cpu_cycle_exact) {
+		if (currprefs.m68k_speed_throttle < 0) {
+			cycles_mult = (unsigned long)(CYCLES_DIV * 1000 / (1000 + currprefs.m68k_speed_throttle));
+		} else if (currprefs.m68k_speed_throttle > 0) {
+			cycles_mult = (unsigned long)(CYCLES_DIV * 1000 / (1000 + currprefs.m68k_speed_throttle));
+		}
+	}
+	if (currprefs.m68k_speed == 0) {
+		if (currprefs.cpu_model >= 68040) {
+			if (!cycles_mult)
+				cycles_mult = CYCLES_DIV / 8;
+			else
+				cycles_mult /= 8;
+		} else if (currprefs.cpu_model >= 68020) {
+			if (!cycles_mult)
+				cycles_mult = CYCLES_DIV / 4;
+			else
+				cycles_mult /= 4;
+		}
+	}
+#endif
+
+	currprefs.cpu_clock_multiplier = changed_prefs.cpu_clock_multiplier;
+	currprefs.cpu_frequency = changed_prefs.cpu_frequency;
+
+#ifndef WINUAE_FOR_HATARI
+	baseclock = (currprefs.ntscmode ? CHIPSET_CLOCK_NTSC : CHIPSET_CLOCK_PAL) * 8;
+#endif
+	cpucycleunit = CYCLE_UNIT / 2;
+	if (currprefs.cpu_clock_multiplier) {
+		if (currprefs.cpu_clock_multiplier >= 256) {
+			cpucycleunit = CYCLE_UNIT / (currprefs.cpu_clock_multiplier >> 8);
+		} else {
+			cpucycleunit = CYCLE_UNIT * currprefs.cpu_clock_multiplier;
+		}
+		if (currprefs.cpu_model >= 68040)
+			cpucycleunit /= 2;
+#ifndef WINUAE_FOR_HATARI		/* [NP] TODO : handle any cpu frequency, not just mulltiplier ? */
+	} else if (currprefs.cpu_frequency) {
+		cpucycleunit = CYCLE_UNIT * baseclock / currprefs.cpu_frequency;
+#endif
+	} else if (currprefs.cpu_cycle_exact && currprefs.cpu_clock_multiplier == 0) {
+		if (currprefs.cpu_model >= 68040) {
+			cpucycleunit = CYCLE_UNIT / 16;
+		} if (currprefs.cpu_model == 68030) {
+			cpucycleunit = CYCLE_UNIT / 8;
+		} else if (currprefs.cpu_model == 68020) {
+			cpucycleunit = CYCLE_UNIT / 4;
+		} else {
+			cpucycleunit = CYCLE_UNIT / 2;
+		}
+	}
+	if (cpucycleunit < 1)
+		cpucycleunit = 1;
+	if (currprefs.cpu_cycle_exact)
+		write_log (_T("CPU cycleunit: %d (%.3f)\n"), cpucycleunit, (float)cpucycleunit / CYCLE_UNIT);
+write_log (_T("CPU cycleunit: %d (%.3f)\n"), cpucycleunit, (float)cpucycleunit / CYCLE_UNIT);
+#ifndef WINUAE_FOR_HATARI
+	set_config_changed ();
+#endif
+}
+
+static void prefs_changed_cpu (void)
+{
+	fixup_cpu (&changed_prefs);
+	currprefs.cpu_model = changed_prefs.cpu_model;
+	currprefs.fpu_model = changed_prefs.fpu_model;
+	currprefs.mmu_model = changed_prefs.mmu_model;
+	currprefs.cpu_compatible = changed_prefs.cpu_compatible;
+	currprefs.cpu_cycle_exact = changed_prefs.cpu_cycle_exact;
+	currprefs.int_no_unimplemented = changed_prefs.int_no_unimplemented;
+	currprefs.fpu_no_unimplemented = changed_prefs.fpu_no_unimplemented;
+	currprefs.blitter_cycle_exact = changed_prefs.blitter_cycle_exact;
+}
+
+static int check_prefs_changed_cpu2(void)
+{
+	int changed = 0;
+
+#ifdef JIT
+	changed = check_prefs_changed_comp() ? 1 : 0;
+#endif
+	if (changed
+		|| currprefs.cpu_model != changed_prefs.cpu_model
+		|| currprefs.fpu_model != changed_prefs.fpu_model
+		|| currprefs.mmu_model != changed_prefs.mmu_model
+		|| currprefs.int_no_unimplemented != changed_prefs.int_no_unimplemented
+		|| currprefs.fpu_no_unimplemented != changed_prefs.fpu_no_unimplemented
+		|| currprefs.cpu_compatible != changed_prefs.cpu_compatible
+		|| currprefs.cpu_cycle_exact != changed_prefs.cpu_cycle_exact) {
+			cpu_prefs_changed_flag |= 1;
+#ifdef WINUAE_FOR_HATARI
+			/* When changing CPU prefs in Hatari we reset the emulation, */
+			/* so new cpu table should be built now, not in m68k_go() */
+//			uaecptr pc = m68k_getpc();
+			prefs_changed_cpu();
+			build_cpufunctbl();
+// done in m68k_go :
+//			m68k_setpc_normal(pc);
+//			fill_prefetch();
+#endif
+	}
+	if (changed
+		|| currprefs.m68k_speed != changed_prefs.m68k_speed
+		|| currprefs.m68k_speed_throttle != changed_prefs.m68k_speed_throttle
+		|| currprefs.cpu_clock_multiplier != changed_prefs.cpu_clock_multiplier
+		|| currprefs.reset_delay != changed_prefs.reset_delay
+		|| currprefs.cpu_frequency != changed_prefs.cpu_frequency) {
+			cpu_prefs_changed_flag |= 2;
+	}
+	return cpu_prefs_changed_flag;
+}
+
+void check_prefs_changed_cpu(void)
+{
+#ifndef WINUAE_FOR_HATARI
+	return;				/* [NP] TODO : handle cpu change on the fly ? */
+	if (!config_changed)
+		return;
+#else
+
+	currprefs.cpu_idle = changed_prefs.cpu_idle;
+	currprefs.ppc_cpu_idle = changed_prefs.ppc_cpu_idle;
+	currprefs.reset_delay = changed_prefs.reset_delay;
+
+	if (check_prefs_changed_cpu2()) {
+		set_special(SPCFLAG_MODE_CHANGE);
+		reset_frame_rate_hack();
+	}
+#endif
+}
+
+void init_m68k (void)
+{
+	int i;
+
+	prefs_changed_cpu ();
+	update_68k_cycles ();
+
+	for (i = 0 ; i < 256 ; i++) {
+		int j;
+		for (j = 0 ; j < 8 ; j++) {
+			if (i & (1 << j)) break;
+		}
+		movem_index1[i] = j;
+		movem_index2[i] = 7 - j;
+		movem_next[i] = i & (~(1 << j));
+	}
+
+#if COUNT_INSTRS
+	{
+		FILE *f = fopen (icountfilename (), "r");
+		memset (instrcount, 0, sizeof instrcount);
+		if (f) {
+			uae_u32 opcode, count, total;
+			TCHAR name[20];
+			write_log (_T("Reading instruction count file...\n"));
+			fscanf (f, "Total: %lu\n", &total);
+			while (fscanf (f, "%x: %lu %s\n", &opcode, &count, name) == 3) {
+				instrcount[opcode] = count;
+			}
+			fclose (f);
+		}
+	}
+#endif
+
+	read_table68k ();
+	do_merges ();
+
+	write_log (_T("%d CPU functions\n"), nr_cpuop_funcs);
+
+	build_cpufunctbl ();
+	set_x_funcs ();
+
+#ifdef JIT
+	/* We need to check whether NATMEM settings have changed
+	* before starting the CPU */
+	check_prefs_changed_comp ();
+#endif
+}
+
+struct regstruct regs, mmu_backup_regs;
+struct flag_struct regflags;
+static int m68kpc_offset;
+
+#if 0
+#define get_ibyte_1(o) get_byte (regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
+#define get_iword_1(o) get_word (regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
+#define get_ilong_1(o) get_long (regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
+#endif
+
+static uaecptr ShowEA (void *f, uaecptr pc, uae_u16 opcode, int reg, amodes mode, wordsizes size, TCHAR *buf, uae_u32 *eaddr, int safemode)
+{
+	uae_u16 dp;
+	uae_s8 disp8;
+	uae_s16 disp16;
+	int r;
+	uae_u32 dispreg;
+	uaecptr addr = pc;
+	uae_s32 offset = 0;
+	TCHAR buffer[80];
+
+	switch (mode){
+	case Dreg:
+		_stprintf (buffer, _T("D%d"), reg);
+		break;
+	case Areg:
+		_stprintf (buffer, _T("A%d"), reg);
+		break;
+	case Aind:
+		_stprintf (buffer, _T("(A%d)"), reg);
+		addr = regs.regs[reg + 8];
+		break;
+	case Aipi:
+		_stprintf (buffer, _T("(A%d)+"), reg);
+		addr = regs.regs[reg + 8];
+		break;
+	case Apdi:
+		_stprintf (buffer, _T("-(A%d)"), reg);
+		addr = regs.regs[reg + 8];
+		break;
+	case Ad16:
+		{
+			TCHAR offtxt[80];
+			disp16 = get_iword_debug (pc); pc += 2;
+			if (disp16 < 0)
+				_stprintf (offtxt, _T("-$%04x"), -disp16);
+			else
+				_stprintf (offtxt, _T("$%04x"), disp16);
+			addr = m68k_areg (regs, reg) + disp16;
+			_stprintf (buffer, _T("(A%d, %s) == $%08x"), reg, offtxt, addr);
+		}
+		break;
+	case Ad8r:
+		dp = get_iword_debug (pc); pc += 2;
+		disp8 = dp & 0xFF;
+		r = (dp & 0x7000) >> 12;
+		dispreg = dp & 0x8000 ? m68k_areg (regs, r) : m68k_dreg (regs, r);
+		if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
+		dispreg <<= (dp >> 9) & 3;
+
+		if (dp & 0x100) {
+			uae_s32 outer = 0, disp = 0;
+			uae_s32 base = m68k_areg (regs, reg);
+			TCHAR name[10];
+			_stprintf (name, _T("A%d, "), reg);
+			if (dp & 0x80) { base = 0; name[0] = 0; }
+			if (dp & 0x40) dispreg = 0;
+			if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_debug (pc); pc += 2; }
+			if ((dp & 0x30) == 0x30) { disp = get_ilong_debug (pc); pc += 4; }
+			base += disp;
+
+			if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_debug (pc); pc += 2; }
+			if ((dp & 0x3) == 0x3) { outer = get_ilong_debug (pc); pc += 4; }
+
+			if (!(dp & 4)) base += dispreg;
+			if ((dp & 3) && !safemode) base = get_ilong_debug (base);
+			if (dp & 4) base += dispreg;
+
+			addr = base + outer;
+			_stprintf (buffer, _T("(%s%c%d.%c*%d+%d)+%d == $%08x"), name,
+				dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
+				1 << ((dp >> 9) & 3),
+				disp, outer, addr);
+		} else {
+			addr = m68k_areg (regs, reg) + (uae_s32)((uae_s8)disp8) + dispreg;
+			_stprintf (buffer, _T("(A%d, %c%d.%c*%d, $%02x) == $%08x"), reg,
+				dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
+				1 << ((dp >> 9) & 3), disp8, addr);
+		}
+		break;
+	case PC16:
+		disp16 = get_iword_debug (pc); pc += 2;
+		addr += (uae_s16)disp16;
+		_stprintf (buffer, _T("(PC,$%04x) == $%08x"), disp16 & 0xffff, addr);
+		break;
+	case PC8r:
+		dp = get_iword_debug (pc); pc += 2;
+		disp8 = dp & 0xFF;
+		r = (dp & 0x7000) >> 12;
+		dispreg = dp & 0x8000 ? m68k_areg (regs, r) : m68k_dreg (regs, r);
+		if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
+		dispreg <<= (dp >> 9) & 3;
+
+		if (dp & 0x100) {
+			uae_s32 outer = 0, disp = 0;
+			uae_s32 base = addr;
+			TCHAR name[10];
+			_stprintf (name, _T("PC, "));
+			if (dp & 0x80) { base = 0; name[0] = 0; }
+			if (dp & 0x40) dispreg = 0;
+			if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_debug (pc); pc += 2; }
+			if ((dp & 0x30) == 0x30) { disp = get_ilong_debug (pc); pc += 4; }
+			base += disp;
+
+			if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_debug (pc); pc += 2; }
+			if ((dp & 0x3) == 0x3) { outer = get_ilong_debug (pc); pc += 4; }
+
+			if (!(dp & 4)) base += dispreg;
+			if ((dp & 3) && !safemode) base = get_ilong_debug (base);
+			if (dp & 4) base += dispreg;
+
+			addr = base + outer;
+			_stprintf (buffer, _T("(%s%c%d.%c*%d+%d)+%d == $%08x"), name,
+				dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
+				1 << ((dp >> 9) & 3),
+				disp, outer, addr);
+		} else {
+			addr += (uae_s32)((uae_s8)disp8) + dispreg;
+			_stprintf (buffer, _T("(PC, %c%d.%c*%d, $%02x) == $%08x"), dp & 0x8000 ? 'A' : 'D',
+				(int)r, dp & 0x800 ? 'L' : 'W',  1 << ((dp >> 9) & 3),
+				disp8, addr);
+		}
+		break;
+	case absw:
+		addr = (uae_s32)(uae_s16)get_iword_debug (pc);
+		_stprintf (buffer, _T("$%08x"), addr);
+		pc += 2;
+		break;
+	case absl:
+		addr = get_ilong_debug (pc);
+		_stprintf (buffer, _T("$%08x"), addr);
+		pc += 4;
+		break;
+	case imm:
+		switch (size){
+		case sz_byte:
+			_stprintf (buffer, _T("#$%02x"), (get_iword_debug (pc) & 0xff));
+			pc += 2;
+			break;
+		case sz_word:
+			_stprintf (buffer, _T("#$%04x"), (get_iword_debug (pc) & 0xffff));
+			pc += 2;
+			break;
+		case sz_long:
+			_stprintf(buffer, _T("#$%08x"), (get_ilong_debug(pc)));
+			pc += 4;
+			break;
+		case sz_single:
+			{
+				fpdata fp;
+				to_single(&fp, get_ilong_debug(pc));
+				_stprintf(buffer, _T("#%e"), fp.fp);
+				pc += 4;
+			}
+			break;
+		case sz_double:
+			{
+				fpdata fp;
+				to_double(&fp, get_ilong_debug(pc), get_ilong_debug(pc + 4));
+				_stprintf(buffer, _T("#%e"), fp.fp);
+				pc += 8;
+			}
+			break;
+		case sz_extended:
+		{
+			fpdata fp;
+			to_exten(&fp, get_ilong_debug(pc), get_ilong_debug(pc + 4), get_ilong_debug(pc + 8));
+#if USE_LONG_DOUBLE
+			_stprintf(buffer, _T("#%Le"), fp.fp);
+#else
+			_stprintf(buffer, _T("#%e"), fp.fp);
+#endif
+			pc += 12;
+			break;
+		}
+		case sz_packed:
+			_stprintf(buffer, _T("#$%08x%08x%08x"), get_ilong_debug(pc), get_ilong_debug(pc + 4), get_ilong_debug(pc + 8));
+			pc += 12;
+			break;
+		default:
+			break;
+		}
+		break;
+	case imm0:
+		offset = (uae_s32)(uae_s8)get_iword_debug (pc);
+		_stprintf (buffer, _T("#$%02x"), (uae_u32)(offset & 0xff));
+		addr = pc + 2 + offset;
+		pc += 2;
+		break;
+	case imm1:
+		offset = (uae_s32)(uae_s16)get_iword_debug (pc);
+		buffer[0] = 0;
+		_stprintf (buffer, _T("#$%04x"), (uae_u32)(offset & 0xffff));
+		addr = pc + offset;
+		pc += 2;
+		break;
+	case imm2:
+		offset = (uae_s32)get_ilong_debug (pc);
+		_stprintf (buffer, _T("#$%08x"), (uae_u32)offset);
+		addr = pc + offset;
+		pc += 4;
+		break;
+	case immi:
+		offset = (uae_s32)(uae_s8)(reg & 0xff);
+		_stprintf (buffer, _T("#$%08x"), (uae_u32)offset);
+		addr = pc + offset;
+		break;
+	default:
+		break;
+	}
+	if (buf == 0)
+		f_out (f, _T("%s"), buffer);
+	else
+		_tcscat (buf, buffer);
+	if (eaddr)
+		*eaddr = addr;
+	return pc;
+}
+
+#if 0
+/* The plan is that this will take over the job of exception 3 handling -
+* the CPU emulation functions will just do a longjmp to m68k_go whenever
+* they hit an odd address. */
+static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
+{
+	uae_u16 dp;
+	uae_s8 disp8;
+	uae_s16 disp16;
+	int r;
+	uae_u32 dispreg;
+	uaecptr addr;
+	uae_s32 offset = 0;
+
+	switch (mode){
+	case Dreg:
+		*val = m68k_dreg (regs, reg);
+		return 1;
+	case Areg:
+		*val = m68k_areg (regs, reg);
+		return 1;
+
+	case Aind:
+	case Aipi:
+		addr = m68k_areg (regs, reg);
+		break;
+	case Apdi:
+		addr = m68k_areg (regs, reg);
+		break;
+	case Ad16:
+		disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
+		addr = m68k_areg (regs, reg) + (uae_s16)disp16;
+		break;
+	case Ad8r:
+		addr = m68k_areg (regs, reg);
+d8r_common:
+		dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
+		disp8 = dp & 0xFF;
+		r = (dp & 0x7000) >> 12;
+		dispreg = dp & 0x8000 ? m68k_areg (regs, r) : m68k_dreg (regs, r);
+		if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
+		dispreg <<= (dp >> 9) & 3;
+
+		if (dp & 0x100) {
+			uae_s32 outer = 0, disp = 0;
+			uae_s32 base = addr;
+			if (dp & 0x80) base = 0;
+			if (dp & 0x40) dispreg = 0;
+			if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
+			if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
+			base += disp;
+
+			if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
+			if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
+
+			if (!(dp & 4)) base += dispreg;
+			if (dp & 3) base = get_long (base);
+			if (dp & 4) base += dispreg;
+
+			addr = base + outer;
+		} else {
+			addr += (uae_s32)((uae_s8)disp8) + dispreg;
+		}
+		break;
+	case PC16:
+		addr = m68k_getpc () + m68kpc_offset;
+		disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
+		addr += (uae_s16)disp16;
+		break;
+	case PC8r:
+		addr = m68k_getpc () + m68kpc_offset;
+		goto d8r_common;
+	case absw:
+		addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
+		m68kpc_offset += 2;
+		break;
+	case absl:
+		addr = get_ilong_1 (m68kpc_offset);
+		m68kpc_offset += 4;
+		break;
+	case imm:
+		switch (size){
+		case sz_byte:
+			*val = get_iword_1 (m68kpc_offset) & 0xff;
+			m68kpc_offset += 2;
+			break;
+		case sz_word:
+			*val = get_iword_1 (m68kpc_offset) & 0xffff;
+			m68kpc_offset += 2;
+			break;
+		case sz_long:
+			*val = get_ilong_1 (m68kpc_offset);
+			m68kpc_offset += 4;
+			break;
+		default:
+			break;
+		}
+		return 1;
+	case imm0:
+		*val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
+		m68kpc_offset += 2;
+		return 1;
+	case imm1:
+		*val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
+		m68kpc_offset += 2;
+		return 1;
+	case imm2:
+		*val = get_ilong_1 (m68kpc_offset);
+		m68kpc_offset += 4;
+		return 1;
+	case immi:
+		*val = (uae_s32)(uae_s8)(reg & 0xff);
+		return 1;
+	default:
+		addr = 0;
+		break;
+	}
+	if ((addr & 1) == 0)
+		return 1;
+
+	last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
+	last_fault_for_exception_3 = addr;
+	last_writeaccess_for_exception_3 = 0;
+	last_instructionaccess_for_exception_3 = 0;
+	return 0;
+}
+#endif
+
+int get_cpu_model (void)
+{
+	return currprefs.cpu_model;
+}
+
+#ifndef WINUAE_FOR_HATARI
+STATIC_INLINE int in_rom (uaecptr pc)
+{
+	return (munge24 (pc) & 0xFFF80000) == 0xF80000;
+}
+
+STATIC_INLINE int in_rtarea (uaecptr pc)
+{
+	return (munge24 (pc) & 0xFFFF0000) == rtarea_base && uae_boot_rom_type;
+}
+#endif
+
+STATIC_INLINE void wait_memory_cycles (void)
+{
+	if (regs.memory_waitstate_cycles) {
+		x_do_cycles(regs.memory_waitstate_cycles);
+		regs.memory_waitstate_cycles = 0;
+	}
+	if (regs.ce020extracycles >= 16) {
+		regs.ce020extracycles = 0;
+		x_do_cycles(4 * CYCLE_UNIT);
+	}
+}
+
+STATIC_INLINE int adjust_cycles (int cycles)
+{
+	int mc = regs.memory_waitstate_cycles;
+	regs.memory_waitstate_cycles = 0;
+	if (currprefs.m68k_speed < 0 || cycles_mult == 0)
+		return cycles + mc;
+	cycles *= cycles_mult;
+	cycles /= CYCLES_DIV;
+	return cycles + mc;
+}
+
+void REGPARAM2 MakeSR (void)
+{
+	regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
+		| (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
+		| (GET_XFLG () << 4) | (GET_NFLG () << 3)
+		| (GET_ZFLG () << 2) | (GET_VFLG () << 1)
+		|  GET_CFLG ());
+}
+
+void SetSR (uae_u16 sr)
+{
+	regs.sr &= 0xff00;
+	regs.sr |= sr;
+
+	SET_XFLG ((regs.sr >> 4) & 1);
+	SET_NFLG ((regs.sr >> 3) & 1);
+	SET_ZFLG ((regs.sr >> 2) & 1);
+	SET_VFLG ((regs.sr >> 1) & 1);
+	SET_CFLG (regs.sr & 1);
+}
+
+void REGPARAM2 MakeFromSR (void)
+{
+	int oldm = regs.m;
+	int olds = regs.s;
+
+	SET_XFLG ((regs.sr >> 4) & 1);
+	SET_NFLG ((regs.sr >> 3) & 1);
+	SET_ZFLG ((regs.sr >> 2) & 1);
+	SET_VFLG ((regs.sr >> 1) & 1);
+	SET_CFLG (regs.sr & 1);
+	if (regs.t1 == ((regs.sr >> 15) & 1) &&
+		regs.t0 == ((regs.sr >> 14) & 1) &&
+		regs.s  == ((regs.sr >> 13) & 1) &&
+		regs.m  == ((regs.sr >> 12) & 1) &&
+		regs.intmask == ((regs.sr >> 8) & 7))
+		return;
+	regs.t1 = (regs.sr >> 15) & 1;
+	regs.t0 = (regs.sr >> 14) & 1;
+	regs.s  = (regs.sr >> 13) & 1;
+	regs.m  = (regs.sr >> 12) & 1;
+	regs.intmask = (regs.sr >> 8) & 7;
+	if (currprefs.cpu_model >= 68020) {
+		/* 68060 does not have MSP but does have M-bit.. */
+		if (currprefs.cpu_model >= 68060)
+			regs.msp = regs.isp;
+		if (olds != regs.s) {
+			if (olds) {
+				if (oldm)
+					regs.msp = m68k_areg (regs, 7);
+				else
+					regs.isp = m68k_areg (regs, 7);
+				m68k_areg (regs, 7) = regs.usp;
+			} else {
+				regs.usp = m68k_areg (regs, 7);
+				m68k_areg (regs, 7) = regs.m ? regs.msp : regs.isp;
+			}
+		} else if (olds && oldm != regs.m) {
+			if (oldm) {
+				regs.msp = m68k_areg (regs, 7);
+				m68k_areg (regs, 7) = regs.isp;
+			} else {
+				regs.isp = m68k_areg (regs, 7);
+				m68k_areg (regs, 7) = regs.msp;
+			}
+		}
+		if (currprefs.cpu_model >= 68060)
+			regs.t0 = 0;
+	} else {
+		regs.t0 = regs.m = 0;
+		if (olds != regs.s) {
+			if (olds) {
+				regs.isp = m68k_areg (regs, 7);
+				m68k_areg (regs, 7) = regs.usp;
+			} else {
+				regs.usp = m68k_areg (regs, 7);
+				m68k_areg (regs, 7) = regs.isp;
+			}
+		}
+	}
+	if (currprefs.mmu_model)
+		mmu_set_super (regs.s != 0);
+
+	doint ();
+	if (regs.t1 || regs.t0)
+		set_special (SPCFLAG_TRACE);
+	else
+		/* Keep SPCFLAG_DOTRACE, we still want a trace exception for
+		SR-modifying instructions (including STOP).  */
+		unset_special (SPCFLAG_TRACE);
+}
+
+static void exception_trace (int nr)
+{
+	unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
+	if (regs.t1 && !regs.t0) {
+		/* trace stays pending if exception is div by zero, chk,
+		* trapv or trap #x
+		*/
+		if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47))
+			set_special (SPCFLAG_DOTRACE);
+	}
+	regs.t1 = regs.t0 = regs.m = 0;
+}
+
+static void exception_debug (int nr)
+{
+#ifdef DEBUGGER
+	if (!exception_debugging)
+		return;
+	console_out_f (_T("Exception %d, PC=%08X\n"), nr, M68K_GETPC);
+#endif
+#ifdef WINUAE_FOR_HATARI
+	DebugUI_Exceptions(nr, M68K_GETPC);
+#endif
+}
+
+#ifdef CPUEMU_13
+
+/* cycle-exact exception handler, 68000 only */
+
+/*
+
+Address/Bus Error:
+
+- 8 idle cycles
+- write PC low word
+- write SR
+- write PC high word
+- write instruction word
+- write fault address low word
+- write status code
+- write fault address high word
+- 2 idle cycles
+- read exception address high word
+- read exception address low word
+- prefetch
+- 2 idle cycles
+- prefetch
+
+Division by Zero:
+
+- 8 idle cycles
+- write PC low word
+- write SR
+- write PC high word
+- read exception address high word
+- read exception address low word
+- prefetch
+- 2 idle cycles
+- prefetch
+
+Traps:
+
+- 4 idle cycles
+- write PC low word
+- write SR
+- write PC high word
+- read exception address high word
+- read exception address low word
+- prefetch
+- 2 idle cycles
+- prefetch
+
+TrapV:
+
+(- normal prefetch done by TRAPV)
+- write PC low word
+- write SR
+- write PC high word
+- read exception address high word
+- read exception address low word
+- prefetch
+- 2 idle cycles
+- prefetch
+
+CHK:
+
+- 8 idle cycles
+- write PC low word
+- write SR
+- write PC high word
+- read exception address high word
+- read exception address low word
+- prefetch
+- 2 idle cycles
+- prefetch
+
+Illegal Instruction:
+Privilege violation:
+Line A:
+Line F:
+
+- 4 idle cycles
+- write PC low word
+- write SR
+- write PC high word
+- read exception address high word
+- read exception address low word
+- prefetch
+- 2 idle cycles
+- prefetch
+
+Interrupt:
+
+- 6 idle cycles
+- write PC low word
+- read exception number byte from (0xfffff1 | (interrupt number << 1))
+- 4 idle cycles
+- write SR
+- write PC high word
+- read exception address high word
+- read exception address low word
+- prefetch
+- 2 idle cycles
+- prefetch
+
+*/
+
+static int iack_cycle(int nr)
+{
+	int vector;
+
+#ifndef WINUAE_FOR_HATARI
+	if (1) {
+		// non-autovectored
+		vector = x_get_byte(0x00fffff1 | ((nr - 24) << 1));
+		if (currprefs.cpu_cycle_exact)
+			x_do_cycles(4 * cpucycleunit);
+	} else {
+		// autovectored
+
+	}
+#else
+	int iack_start = CPU_IACK_CYCLES_START;
+	int e_cycles;
+
+	/* In cycle exact mode, the cycles before reaching IACK are already counted */
+	if ( currprefs.cpu_cycle_exact )
+		iack_start = 0;
+
+	/* Pending bits / vector number can change before the end of the IACK sequence. */
+	/* We need to handle MFP/DSP and HBL/VBL cases for this. */
+	/* - Level 6 (MFP/DSP) use vectored interrupts */
+	/* - Level 2 (HBL) and 4 (VBL) use auto-vectored interrupts and require sync with E-clock */
+	vector = nr;
+	if ( nr == 30 )								/* MFP or DSP */
+        {
+		vector = -1;
+		if (bDspEnabled)						/* Check DSP first */
+		{
+			/* TODO : For DSP, we just get the vector, we don't add IACK cycles */
+			vector = DSP_ProcessIACK ();
+		}
+
+		if ( vector < 0 )						/* No DSP, check MFP */
+		{
+			M68000_AddCycles ( iack_start + CPU_IACK_CYCLES_MFP );
+	      // TODO : add CE cycles too
+			CPU_IACK = true;
+			while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
+				CALL_VAR(PendingInterruptFunction);
+			vector = MFP_ProcessIACK ( nr );
+			CPU_IACK = false;
+		}
+	}
+	else if ( ( nr == 26 ) || ( nr == 28 ) )				/* HBL / VBL */
+	{
+		iack_start -= 2;			/* [NP] work in progress for e clock, TODO we need to check the complete sequence of interrupt micro code */
+		e_cycles = M68000_WaitEClock ();
+		//fprintf ( stderr , "wait e clock %d\n" , e_cycles);
+
+		M68000_AddCycles ( iack_start + CPU_IACK_CYCLES_VIDEO + e_cycles );
+	// TODO : add CE cycles too
+		CPU_IACK = true;
+		while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
+			CALL_VAR(PendingInterruptFunction);
+		if ( MFP_UpdateNeeded == true )
+			MFP_UpdateIRQ ( 0 );					/* update MFP's state if some internal timers related to MFP expired */
+		pendingInterrupts &= ~( 1 << ( nr - 24 ) );			/* clear HBL or VBL pending bit */
+		CPU_IACK = false;
+	}
+
+	/* TODO If there was no DSP and no MFP IRQ, then we have a spurious interrupt */
+	/* In that case, we use vector 24 and we jump to $60 */
+	if ( vector < 0 )
+	{
+	}
+#endif
+	return vector;
+}
+
+static void Exception_ce000 (int nr)
+{
+	uae_u32 currpc = m68k_getpc (), newpc;
+	int sv = regs.s;
+	int start, interrupt;
+	int vector_nr = nr;
+
+//fprintf ( stderr , "ex in %d %ld\n" , nr , currcycle );
+currcycle=0;
+	start = 6;
+#ifndef WINUAE_FOR_HATARI
+	interrupt = nr >= 24 && nr < 24 + 8;
+#else
+	if ( nr >= 24 && nr < 24 + 8 )
+		interrupt = 1;
+#endif
+	if (!interrupt) {
+		start = 8;
+		if (nr == 7) // TRAPV
+			start = 0;
+		else if (nr >= 32 && nr < 32 + 16) // TRAP #x
+			start = 4;
+		else if (nr == 4 || nr == 8 || nr == 10 || nr == 11) // ILLG, PRIV, LINEA, LINEF
+			start = 4;
+	}
+
+	if (start)
+		x_do_cycles (start * cpucycleunit);
+
+#ifdef WINUAE_FOR_HATARI
+	LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x SR %x\n",
+		nr, currpc, regs.instruction_pc, STMemory_ReadLong (regs.vbr + 4*nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3, regs.sr);
+#endif
+	exception_debug (nr);
+	MakeSR ();
+
+#ifdef WINUAE_FOR_HATARI
+	/* Handle Hatari GEM and BIOS traps */
+	if (nr == 0x22) {
+		/* Intercept VDI & AES exceptions (Trap #2) */
+		if (bVdiAesIntercept && VDI_AES_Entry()) {
+			/* Set 'PC' to address of 'VDI_OPCODE' illegal instruction.
+			* This will call OpCode_VDI() after completion of Trap call!
+			* This is used to modify specific VDI return vectors contents.
+			*/
+			VDI_OldPC = currpc;
+			currpc = CART_VDI_OPCODE_ADDR;
+		}
+	}
+	else if (nr == 0x2d) {
+		/* Intercept BIOS (Trap #13) calls */
+		if (Bios())  return;
+	}
+	else if (nr == 0x2e) {
+		/* Intercept XBIOS (Trap #14) calls */
+		if (XBios())  return;
+	}
+#endif
+
+	if (!regs.s) {
+		regs.usp = m68k_areg (regs, 7);
+		m68k_areg (regs, 7) = regs.isp;
+		regs.s = 1;
+	}
+	if (nr == 2 || nr == 3) { /* 2=bus error, 3=address error */
+		if ((m68k_areg(regs, 7) & 1) || exception_in_exception < 0) {
+			cpu_halt (2);
+			return;
+		}
+		uae_u16 mode = (sv ? 4 : 0) | (last_instructionaccess_for_exception_3 ? 2 : 1);
+		mode |= last_writeaccess_for_exception_3 ? 0 : 16;
+		mode |= last_notinstruction_for_exception_3 ? 8 : 0;
+		// undocumented bits seem to contain opcode
+		mode |= last_op_for_exception_3 & ~31;
+		m68k_areg (regs, 7) -= 14;
+		exception_in_exception = -1;
+		x_put_word (m68k_areg (regs, 7) + 12, last_addr_for_exception_3);
+		x_put_word (m68k_areg (regs, 7) + 8, regs.sr);
+		x_put_word (m68k_areg (regs, 7) + 10, last_addr_for_exception_3 >> 16);
+		x_put_word (m68k_areg (regs, 7) + 6, last_op_for_exception_3);
+		x_put_word (m68k_areg (regs, 7) + 4, last_fault_for_exception_3);
+		x_put_word (m68k_areg (regs, 7) + 0, mode);
+		x_put_word (m68k_areg (regs, 7) + 2, last_fault_for_exception_3 >> 16);
+		x_do_cycles (2 * cpucycleunit);
+		write_log (_T("Exception %d (%04x %x) at %x -> %x!\n"),
+			nr, last_op_for_exception_3, last_addr_for_exception_3, currpc, get_long_debug (4 * nr));
+#ifdef WINUAE_FOR_HATARI
+		fprintf(stderr,"%s Error at address $%x, PC=$%x addr_e3=%x op_e3=%x\n", nr==2?"Bus":"Address", last_fault_for_exception_3, currpc, last_addr_for_exception_3 , last_op_for_exception_3);
+#endif
+		goto kludge_me_do;
+	}
+	if (currprefs.cpu_model == 68010) {
+		// 68010 creates only format 0 and 8 stack frames
+		m68k_areg (regs, 7) -= 8;
+		if (m68k_areg(regs, 7) & 1) {
+			exception3_notinstruction(regs.ir, m68k_areg(regs, 7) + 4);
+			return;
+		}
+		exception_in_exception = 1;
+		x_put_word (m68k_areg (regs, 7) + 4, currpc); // write low address
+		if (interrupt)
+			vector_nr = iack_cycle(nr);
+		x_put_word (m68k_areg (regs, 7) + 0, regs.sr); // write SR
+		x_put_word (m68k_areg (regs, 7) + 2, currpc >> 16); // write high address
+		x_put_word (m68k_areg (regs, 7) + 6, vector_nr * 4);
+	} else {
+		m68k_areg (regs, 7) -= 6;
+		if (m68k_areg(regs, 7) & 1) {
+			exception3_notinstruction(regs.ir, m68k_areg(regs, 7) + 4);
+			return;
+		}
+		exception_in_exception = 1;
+		x_put_word (m68k_areg (regs, 7) + 4, currpc); // write low address
+		if (interrupt)
+			vector_nr = iack_cycle(nr);
+		x_put_word (m68k_areg (regs, 7) + 0, regs.sr); // write SR
+		x_put_word (m68k_areg (regs, 7) + 2, currpc >> 16); // write high address
+	}
+kludge_me_do:
+	newpc = x_get_word (regs.vbr + 4 * vector_nr) << 16; // read high address
+	newpc |= x_get_word (regs.vbr + 4 * vector_nr + 2); // read low address
+	exception_in_exception = 0;
+	if (newpc & 1) {
+		if (nr == 2 || nr == 3)
+			cpu_halt (2);
+		else
+			exception3_notinstruction(regs.ir, newpc);
+		return;
+	}
+	m68k_setpc (newpc);
+	regs.ir = x_get_word (m68k_getpc ()); // prefetch 1
+	x_do_cycles (2 * cpucycleunit);
+	regs.irc = x_get_word (m68k_getpc () + 2); // prefetch 2
+#ifdef JIT
+	set_special (SPCFLAG_END_COMPILE);
+#endif
+	exception_trace (nr);
+
+//fprintf ( stderr , "ex out %d %ld\n" , nr , currcycle );
+#ifdef WINUAE_FOR_HATARI
+	/* FIXME : Above code already counts 36 cycles for interrupt, add the remaining ST cycles */
+	/* This is temporary, code should be in iack_cycle() */
+	M68000_AddCycles(currcycle * 2 / CYCLE_UNIT);
+
+	/* Handle exception cycles (special case for MFP) */
+	if ( nr == 30 ) {
+		//M68000_AddCycles(44+12-CPU_IACK_CYCLES_MFP);	/* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
+		M68000_AddCycles(44-36);	/* MFP interrupt, 'nr' can be in a different range depending on $fffa17 */
+	}
+	else if (nr >= 24 && nr <= 31) {
+		if ( nr == 26 )					/* HBL */
+			//M68000_AddCycles(44+12-CPU_IACK_CYCLES_VIDEO);	/* Video Interrupt */
+			M68000_AddCycles(44-36);	/* Video Interrupt */
+		else if ( nr == 28 ) 				/* VBL */
+			//M68000_AddCycles(44+12-CPU_IACK_CYCLES_VIDEO);	/* Video Interrupt */
+			M68000_AddCycles(44-36);	/* Video Interrupt */
+		else
+			//M68000_AddCycles(44+4);			/* Other Interrupts */
+			M68000_AddCycles(44-36);			/* Other Interrupts */
+	}
+#endif
+}
+#endif
+
+static uae_u32 exception_pc (int nr)
+{
+	// bus error, address error, illegal instruction, privilege violation, a-line, f-line
+	if (nr == 2 || nr == 3 || nr == 4 || nr == 8 || nr == 10 || nr == 11)
+		return regs.instruction_pc;
+	return m68k_getpc ();
+}
+
+static void Exception_build_stack_frame (uae_u32 oldpc, uae_u32 currpc, uae_u32 ssw, int nr, int format)
+{
+    int i;
+   
+#if 0
+    if (nr < 24 || nr > 31) { // do not print debugging for interrupts
+        write_log(_T("Building exception stack frame (format %X)\n"), format);
+    }
+#endif
+
+    switch (format) {
+        case 0x0: // four word stack frame
+        case 0x1: // throwaway four word stack frame
+            break;
+        case 0x2: // six word stack frame
+            m68k_areg (regs, 7) -= 4;
+            x_put_long (m68k_areg (regs, 7), oldpc);
+            break;
+        case 0x7: // access error stack frame (68040)
+
+			for (i = 3; i >= 0; i--) {
+				// WB1D/PD0,PD1,PD2,PD3
+                m68k_areg (regs, 7) -= 4;
+                x_put_long (m68k_areg (regs, 7), mmu040_move16[i]);
+			}
+
+            m68k_areg (regs, 7) -= 4;
+            x_put_long (m68k_areg (regs, 7), 0); // WB1A
+			m68k_areg (regs, 7) -= 4;
+            x_put_long (m68k_areg (regs, 7), 0); // WB2D
+            m68k_areg (regs, 7) -= 4;
+            x_put_long (m68k_areg (regs, 7), regs.wb2_address); // WB2A
+			m68k_areg (regs, 7) -= 4;
+            x_put_long (m68k_areg (regs, 7), regs.wb3_data); // WB3D
+            m68k_areg (regs, 7) -= 4;
+            x_put_long (m68k_areg (regs, 7), regs.mmu_fault_addr); // WB3A
+
+			m68k_areg (regs, 7) -= 4;
+            x_put_long (m68k_areg (regs, 7), regs.mmu_fault_addr); // FA
+            
+			m68k_areg (regs, 7) -= 2;
+            x_put_word (m68k_areg (regs, 7), 0);
+            m68k_areg (regs, 7) -= 2;
+            x_put_word (m68k_areg (regs, 7), regs.wb2_status);
+            regs.wb2_status = 0;
+            m68k_areg (regs, 7) -= 2;
+            x_put_word (m68k_areg (regs, 7), regs.wb3_status);
+            regs.wb3_status = 0;
+
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), ssw);
+            m68k_areg (regs, 7) -= 4;
+            x_put_long (m68k_areg (regs, 7), regs.mmu_effective_addr);
+            break;
+        case 0x9: // coprocessor mid-instruction stack frame (68020, 68030)
+            m68k_areg (regs, 7) -= 4;
+            x_put_long (m68k_areg (regs, 7), 0);
+            m68k_areg (regs, 7) -= 4;
+            x_put_long (m68k_areg (regs, 7), 0);
+            m68k_areg (regs, 7) -= 4;
+            x_put_long (m68k_areg (regs, 7), oldpc);
+            break;
+        case 0x3: // floating point post-instruction stack frame (68040)
+        case 0x8: // bus and address error stack frame (68010)
+            write_log(_T("Exception stack frame format %X not implemented\n"), format);
+            return;
+        case 0x4: // floating point unimplemented stack frame (68LC040, 68EC040)
+				// or 68060 bus access fault stack frame
+			if (currprefs.cpu_model == 68040) {
+				// this is actually created in fpp.c
+				write_log(_T("Exception stack frame format %X not implemented\n"), format);
+				return;
+			}
+			// 68060 bus access fault
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), regs.mmu_fslw);
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), regs.mmu_fault_addr);
+			break;
+		case 0xB: // long bus cycle fault stack frame (68020, 68030)
+			// We always use B frame because it is easier to emulate,
+			// our PC always points at start of instruction but A frame assumes
+			// it is + 2 and handling this properly is not easy.
+			// Store state information to internal register space
+			for (i = 0; i < mmu030_idx + 1; i++) {
+				m68k_areg (regs, 7) -= 4;
+				x_put_long (m68k_areg (regs, 7), mmu030_ad[i].val);
+			}
+			while (i < 9) {
+				uae_u32 v = 0;
+				m68k_areg (regs, 7) -= 4;
+				// mmu030_idx is always small enough if instruction is FMOVEM.
+				if (mmu030_state[1] & MMU030_STATEFLAG1_FMOVEM) {
+					if (i == 7)
+						v = mmu030_fmovem_store[0];
+					else if (i == 8)
+						v = mmu030_fmovem_store[1];
+				}
+				x_put_long (m68k_areg (regs, 7), v);
+				i++;
+			}
+			 // version & internal information (We store index here)
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), mmu030_idx);
+			// 3* internal registers
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), mmu030_state[2]);
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), mmu030_state[1]);
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), mmu030_state[0]);
+			// data input buffer = fault address
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), regs.mmu_fault_addr);
+			// 2xinternal
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), 0);
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), 0);
+			// stage b address
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), mm030_stageb_address);
+			// 2xinternal
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), mmu030_disp_store[1]);
+		/* fall through */
+		case 0xA: // short bus cycle fault stack frame (68020, 68030)
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), mmu030_disp_store[0]);
+			m68k_areg (regs, 7) -= 4;
+			 // Data output buffer = value that was going to be written
+			x_put_long (m68k_areg (regs, 7), (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM1) ? mmu030_data_buffer : mmu030_ad[mmu030_idx].val);
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), mmu030_opcode);  // Internal register (opcode storage)
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), regs.mmu_fault_addr); // data cycle fault address
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), 0);  // Instr. pipe stage B
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), 0);  // Instr. pipe stage C
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), ssw);
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), 0);  // Internal register
+			break;
+		default:
+            write_log(_T("Unknown exception stack frame format: %X\n"), format);
+            return;
+    }
+    m68k_areg (regs, 7) -= 2;
+    x_put_word (m68k_areg (regs, 7), (format << 12) | (nr * 4));
+    m68k_areg (regs, 7) -= 4;
+    x_put_long (m68k_areg (regs, 7), currpc);
+    m68k_areg (regs, 7) -= 2;
+    x_put_word (m68k_areg (regs, 7), regs.sr);
+}
+
+
+// 68030 MMU
+static void Exception_mmu030 (int nr, uaecptr oldpc)
+{
+    uae_u32 currpc = m68k_getpc (), newpc;
+	int interrupt;
+
+#ifndef WINUAE_FOR_HATARI
+	interrupt = nr >= 24 && nr < 24 + 8;
+#else
+	if ( nr >= 24 && nr < 24 + 8 )
+		interrupt = 1;
+#endif
+
+#ifdef WINUAE_FOR_HATARI
+	if (interrupt)
+		nr = iack_cycle(nr);
+#endif
+
+#ifdef WINUAE_FOR_HATARI
+	LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x SR %x\n",
+		nr, currpc, regs.instruction_pc, STMemory_ReadLong (regs.vbr + 4*nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3, regs.sr);
+#endif
+    exception_debug (nr);
+    MakeSR ();
+    
+    if (!regs.s) {
+        regs.usp = m68k_areg (regs, 7);
+        m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
+        regs.s = 1;
+        mmu_set_super (1);
+    }
+ 
+#if 0
+    if (nr < 24 || nr > 31) { // do not print debugging for interrupts
+        write_log (_T("Exception_mmu030: Exception %i: %08x %08x %08x\n"),
+                   nr, currpc, oldpc, regs.mmu_fault_addr);
+    }
+#endif
+
+#if 0
+	write_log (_T("Exception %d -> %08x\n", nr, newpc));
+#endif
+
+
+    newpc = x_get_long (regs.vbr + 4 * nr);
+
+	if (regs.m && interrupt) { /* M + Interrupt */
+        Exception_build_stack_frame (oldpc, currpc, regs.mmu_ssw, nr, 0x0);
+		MakeSR ();
+		regs.m = 0;
+		regs.msp = m68k_areg (regs, 7);
+		m68k_areg (regs, 7) = regs.isp;
+        Exception_build_stack_frame (oldpc, currpc, regs.mmu_ssw, nr, 0x1);
+    } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9 || nr == 56) {
+        Exception_build_stack_frame (oldpc, currpc, regs.mmu_ssw, nr, 0x2);
+    } else if (nr == 2) {
+        Exception_build_stack_frame (oldpc, currpc, regs.mmu_ssw, nr,  0xB);
+    } else if (nr == 3) {
+		regs.mmu_fault_addr = last_fault_for_exception_3;
+		mmu030_state[0] = mmu030_state[1] = 0;
+		mmu030_data_buffer = 0;
+        Exception_build_stack_frame (last_fault_for_exception_3, currpc, MMU030_SSW_RW | MMU030_SSW_SIZE_W | (regs.s ? 6 : 2), nr,  0xA);
+    } else {
+        Exception_build_stack_frame (oldpc, currpc, regs.mmu_ssw, nr, 0x0);
+    }
+    
+	if (newpc & 1) {
+		if (nr == 2 || nr == 3)
+			cpu_halt (2);
+		else
+			exception3_read(regs.ir, newpc);
+		return;
+	}
+	m68k_setpci (newpc);
+	fill_prefetch ();
+	exception_trace (nr);
+}
+
+// 68040/060 MMU
+static void Exception_mmu (int nr, uaecptr oldpc)
+{
+	uae_u32 currpc = m68k_getpc (), newpc;
+	int interrupt;
+
+#ifndef WINUAE_FOR_HATARI
+	interrupt = nr >= 24 && nr < 24 + 8;
+#else
+	if ( nr >= 24 && nr < 24 + 8 )
+		interrupt = 1;
+#endif
+
+#ifdef WINUAE_FOR_HATARI
+	if (interrupt)
+		nr = iack_cycle(nr);
+#endif
+
+#ifdef WINUAE_FOR_HATARI
+	LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x SR %x\n",
+		nr, currpc, regs.instruction_pc, STMemory_ReadLong (regs.vbr + 4*nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3, regs.sr);
+#endif
+	exception_debug (nr);
+	MakeSR ();
+
+	if (!regs.s) {
+		regs.usp = m68k_areg (regs, 7);
+		if (currprefs.cpu_model == 68060) {
+			m68k_areg (regs, 7) = regs.isp;
+			if (interrupt)
+				regs.m = 0;
+		} else if (currprefs.cpu_model >= 68020) {
+			m68k_areg (regs, 7) = regs.m ? regs.msp : regs.isp;
+		} else {
+			m68k_areg (regs, 7) = regs.isp;
+		}
+		regs.s = 1;
+		mmu_set_super (1);
+	}
+    
+	newpc = x_get_long (regs.vbr + 4 * nr);
+#if 0
+	write_log (_T("Exception %d: %08x -> %08x\n"), nr, currpc, newpc);
+#endif
+
+	if (nr == 2) { // bus error
+        //write_log (_T("Exception_mmu %08x %08x %08x\n"), currpc, oldpc, regs.mmu_fault_addr);
+        if (currprefs.mmu_model == 68040)
+			Exception_build_stack_frame(oldpc, currpc, regs.mmu_ssw, nr, 0x7);
+		else
+			Exception_build_stack_frame(oldpc, currpc, regs.mmu_fslw, nr, 0x4);
+	} else if (nr == 3) { // address error
+        Exception_build_stack_frame(last_fault_for_exception_3, currpc, 0, nr, 0x2);
+		write_log (_T("Exception %d (%x) at %x -> %x!\n"), nr, last_fault_for_exception_3, currpc, get_long_debug (regs.vbr + 4 * nr));
+	} else if (nr == 5 || nr == 6 || nr == 7 || nr == 9) {
+        Exception_build_stack_frame(oldpc, currpc, regs.mmu_ssw, nr, 0x2);
+	} else if (regs.m && interrupt) { /* M + Interrupt */
+        Exception_build_stack_frame(oldpc, currpc, regs.mmu_ssw, nr, 0x1);
+	} else if (nr == 61) {
+        Exception_build_stack_frame(oldpc, regs.instruction_pc, regs.mmu_ssw, nr, 0x0);
+	} else {
+        Exception_build_stack_frame(oldpc, currpc, regs.mmu_ssw, nr, 0x0);
+	}
+    
+	if (newpc & 1) {
+		if (nr == 2 || nr == 3)
+			cpu_halt (2);
+		else
+			exception3_read(regs.ir, newpc);
+		return;
+	}
+	m68k_setpci (newpc);
+	fill_prefetch ();
+	exception_trace (nr);
+}
+
+static void add_approximate_exception_cycles(int nr)
+{
+	int cycles;
+
+	if (currprefs.cpu_model > 68000)
+		return;
+#ifndef WINUAE_FOR_HATARI
+	if (nr >= 24 && nr <= 31) {
+		/* Interrupts */
+		cycles = 44 + 4; 
+#else
+	if ( nr >= 24 && nr <= 31 ) {
+		/* Atari's specific interrupts take 56 cycles instead of 44 */
+		/* We must subtract IACK cycles already counted into iack_cycle() */
+		if ( nr == 30 )					/* MFP/DSP */
+			cycles = 56-CPU_IACK_CYCLES_START-CPU_IACK_CYCLES_MFP;
+		else if ( nr == 28 )				/* VBL */
+			cycles = 56-CPU_IACK_CYCLES_START-CPU_IACK_CYCLES_VIDEO;
+		else if ( nr == 26 )				/* HBL */
+			cycles = 56-CPU_IACK_CYCLES_START- CPU_IACK_CYCLES_VIDEO;
+		else
+			cycles = 44+4;				/* Other interrupts */
+#endif
+	} else if (nr >= 32 && nr <= 47) {
+		/* Trap (total is 34, but cpuemux.c already adds 4) */ 
+		cycles = 34 -4;
+	} else {
+		switch (nr)
+		{
+			case 2: cycles = 50; break;		/* Bus error */
+			case 3: cycles = 50; break;		/* Address error */
+			case 4: cycles = 34; break;		/* Illegal instruction */
+			case 5: cycles = 38; break;		/* Division by zero */
+			case 6: cycles = 40; break;		/* CHK */
+			case 7: cycles = 34; break;		/* TRAPV */
+			case 8: cycles = 34; break;		/* Privilege violation */
+			case 9: cycles = 34; break;		/* Trace */
+			case 10: cycles = 34; break;	/* Line-A */
+			case 11: cycles = 34; break;	/* Line-F */
+			default:
+			cycles = 4;
+			break;
+		}
+	}
+#ifdef WINUAE_FOR_HATARI
+	M68000_AddCycles ( cycles );
+#endif
+	cycles = adjust_cycles(cycles * CYCLE_UNIT / 2);
+	x_do_cycles(cycles);
+}
+
+static void Exception_normal (int nr)
+{
+	uae_u32 currpc, newpc;
+	int sv = regs.s;
+	int interrupt;
+	int vector_nr = nr;
+
+	interrupt = nr >= 24 && nr < 24 + 8;
+
+/* [NP] TODO : factorize in Hatari_Exception_Intercept() */
+#ifdef WINUAE_FOR_HATARI
+	if (nr == 0x22) {
+		/* Intercept VDI & AES exceptions (Trap #2) */
+		if (bVdiAesIntercept && VDI_AES_Entry()) {
+			/* Set 'PC' to address of 'VDI_OPCODE' illegal instruction.
+			 * This will call OpCode_VDI() after completion of Trap call!
+			 * This is used to modify specific VDI return vectors contents.
+			*/
+			currpc = m68k_getpc ();
+			VDI_OldPC = currpc;
+			currpc = CART_VDI_OPCODE_ADDR;
+		}
+	}
+	else if (nr == 0x2d) {
+		/* Intercept BIOS (Trap #13) calls */
+		if (Bios())  return;
+	}
+	else if (nr == 0x2e) {
+		/* Intercept XBIOS (Trap #14) calls */
+		if (XBios())  return;
+	}
+#endif
+
+#ifndef WINUAE_FOR_HATARI
+	if (interrupt && currprefs.cpu_model <= 68010)
+#else
+	if (interrupt)
+#endif
+		vector_nr = iack_cycle(nr);
+
+	exception_debug (nr);
+	MakeSR ();
+
+	if (!regs.s) {
+		regs.usp = m68k_areg (regs, 7);
+		if (currprefs.cpu_model == 68060) {
+			m68k_areg (regs, 7) = regs.isp;
+			if (interrupt)
+				regs.m = 0;
+		} else if (currprefs.cpu_model >= 68020) {
+			m68k_areg (regs, 7) = regs.m ? regs.msp : regs.isp;
+		} else {
+			m68k_areg (regs, 7) = regs.isp;
+		}
+		regs.s = 1;
+		if (currprefs.mmu_model)
+			mmu_set_super (regs.s != 0);
+	}
+
+	if (m68k_areg(regs, 7) & 1) {
+		if (nr == 2 || nr == 3)
+			cpu_halt (2);
+		else
+			exception3_notinstruction(regs.ir, m68k_areg(regs, 7));
+		return;
+	}
+	if ((nr == 2 || nr == 3) && exception_in_exception < 0) {
+		cpu_halt (2);
+		return;
+	}
+
+	if (currprefs.cpu_model > 68000) {
+		currpc = exception_pc (nr);
+#ifdef WINUAE_FOR_HATARI
+		LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d vector %x currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x SR %x\n",
+			nr, 4*vector_nr , currpc, regs.instruction_pc, STMemory_ReadLong (regs.vbr + 4*vector_nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3, regs.sr);
+#endif
+		if (nr == 2 || nr == 3) {
+			int i;
+			if (currprefs.cpu_model >= 68040) {
+				if (nr == 2) {
+					if (currprefs.mmu_model) {
+						// 68040 mmu bus error
+						for (i = 0 ; i < 7 ; i++) {
+							m68k_areg (regs, 7) -= 4;
+							x_put_long (m68k_areg (regs, 7), 0);
+						}
+						m68k_areg (regs, 7) -= 4;
+						x_put_long (m68k_areg (regs, 7), regs.wb3_data);
+						m68k_areg (regs, 7) -= 4;
+						x_put_long (m68k_areg (regs, 7), regs.mmu_fault_addr);
+						m68k_areg (regs, 7) -= 4;
+						x_put_long (m68k_areg (regs, 7), regs.mmu_fault_addr);
+						m68k_areg (regs, 7) -= 2;
+						x_put_word (m68k_areg (regs, 7), 0);
+						m68k_areg (regs, 7) -= 2;
+						x_put_word (m68k_areg (regs, 7), 0);
+						m68k_areg (regs, 7) -= 2;
+						x_put_word (m68k_areg (regs, 7), regs.wb3_status);
+						regs.wb3_status = 0;
+						m68k_areg (regs, 7) -= 2;
+						x_put_word (m68k_areg (regs, 7), regs.mmu_ssw);
+						m68k_areg (regs, 7) -= 4;
+						x_put_long (m68k_areg (regs, 7), regs.mmu_fault_addr);
+
+						m68k_areg (regs, 7) -= 2;
+						x_put_word (m68k_areg (regs, 7), 0x7000 + vector_nr * 4);
+						m68k_areg (regs, 7) -= 4;
+						x_put_long (m68k_areg (regs, 7), regs.instruction_pc);
+						m68k_areg (regs, 7) -= 2;
+						x_put_word (m68k_areg (regs, 7), regs.sr);
+						newpc = x_get_long (regs.vbr + 4 * vector_nr);
+						if (newpc & 1) {
+							if (nr == 2 || nr == 3)
+								cpu_halt (2);
+							else
+								exception3_read(regs.ir, newpc);
+							return;
+						}
+						m68k_setpc (newpc);
+#ifdef JIT
+						set_special (SPCFLAG_END_COMPILE);
+#endif
+						exception_trace (nr);
+						return;
+
+					} else {
+
+						// 68040 bus error (not really, some garbage?)
+						for (i = 0 ; i < 18 ; i++) {
+							m68k_areg (regs, 7) -= 2;
+							x_put_word (m68k_areg (regs, 7), 0);
+						}
+						m68k_areg (regs, 7) -= 4;
+						x_put_long (m68k_areg (regs, 7), last_fault_for_exception_3);
+						m68k_areg (regs, 7) -= 2;
+						x_put_word (m68k_areg (regs, 7), 0);
+						m68k_areg (regs, 7) -= 2;
+						x_put_word (m68k_areg (regs, 7), 0);
+						m68k_areg (regs, 7) -= 2;
+						x_put_word (m68k_areg (regs, 7), 0);
+						m68k_areg (regs, 7) -= 2;
+						x_put_word (m68k_areg (regs, 7), 0x0140 | (sv ? 6 : 2)); /* SSW */
+						m68k_areg (regs, 7) -= 4;
+						x_put_long (m68k_areg (regs, 7), last_addr_for_exception_3);
+						m68k_areg (regs, 7) -= 2;
+						x_put_word (m68k_areg (regs, 7), 0x7000 + vector_nr * 4);
+						m68k_areg (regs, 7) -= 4;
+						x_put_long (m68k_areg (regs, 7), regs.instruction_pc);
+						m68k_areg (regs, 7) -= 2;
+						x_put_word (m68k_areg (regs, 7), regs.sr);
+						goto kludge_me_do;
+
+					}
+
+				} else {
+					m68k_areg (regs, 7) -= 4;
+					x_put_long (m68k_areg (regs, 7), last_fault_for_exception_3);
+					m68k_areg (regs, 7) -= 2;
+					x_put_word (m68k_areg (regs, 7), 0x2000 + vector_nr * 4);
+				}
+			} else {
+				// 68020 address error
+				uae_u16 ssw = (sv ? 4 : 0) | (last_instructionaccess_for_exception_3 ? 2 : 1);
+				ssw |= last_writeaccess_for_exception_3 ? 0 : 0x40;
+				ssw |= 0x20;
+				for (i = 0 ; i < 36; i++) {
+					m68k_areg (regs, 7) -= 2;
+					x_put_word (m68k_areg (regs, 7), 0);
+				}
+				m68k_areg (regs, 7) -= 4;
+				x_put_long (m68k_areg (regs, 7), last_fault_for_exception_3);
+				m68k_areg (regs, 7) -= 2;
+				x_put_word (m68k_areg (regs, 7), 0);
+				m68k_areg (regs, 7) -= 2;
+				x_put_word (m68k_areg (regs, 7), 0);
+				m68k_areg (regs, 7) -= 2;
+				x_put_word (m68k_areg (regs, 7), 0);
+				m68k_areg (regs, 7) -= 2;
+				x_put_word (m68k_areg (regs, 7), ssw);
+				m68k_areg (regs, 7) -= 2;
+				x_put_word (m68k_areg (regs, 7), 0xb000 + vector_nr * 4);
+			}
+			write_log (_T("Exception %d (%x) at %x -> %x!\n"), nr, regs.instruction_pc, currpc, get_long_debug (regs.vbr + 4 * vector_nr));
+		} else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), regs.instruction_pc);
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), 0x2000 + vector_nr * 4);
+		} else if (regs.m && interrupt) { /* M + Interrupt */
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), vector_nr * 4);
+			m68k_areg (regs, 7) -= 4;
+			x_put_long (m68k_areg (regs, 7), currpc);
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), regs.sr);
+			regs.sr |= (1 << 13);
+			regs.msp = m68k_areg (regs, 7);
+			regs.m = 0;
+			m68k_areg (regs, 7) = regs.isp;
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), 0x1000 + vector_nr * 4);
+		} else {
+			m68k_areg (regs, 7) -= 2;
+			x_put_word (m68k_areg (regs, 7), vector_nr * 4);
+		}
+	} else {
+		add_approximate_exception_cycles(nr);
+		currpc = m68k_getpc ();
+#ifdef WINUAE_FOR_HATARI
+		LOG_TRACE(TRACE_CPU_EXCEPTION, "cpu exception %d vector %x currpc %x buspc %x newpc %x fault_e3 %x op_e3 %hx addr_e3 %x SR %x\n",
+			nr, 4*vector_nr , currpc, regs.instruction_pc, STMemory_ReadLong (regs.vbr + 4*vector_nr), last_fault_for_exception_3, last_op_for_exception_3, last_addr_for_exception_3, regs.sr);
+#endif
+		if (nr == 2 || nr == 3) {
+			// 68000 address error
+			uae_u16 mode = (sv ? 4 : 0) | (last_instructionaccess_for_exception_3 ? 2 : 1);
+			mode |= last_writeaccess_for_exception_3 ? 0 : 16;
+			mode |= last_notinstruction_for_exception_3 ? 8 : 0;
+			// undocumented bits seem to contain opcode
+			mode |= last_op_for_exception_3 & ~31;
+			m68k_areg (regs, 7) -= 14;
+			exception_in_exception = -1;
+			x_put_word (m68k_areg (regs, 7) + 0, mode);
+			x_put_long (m68k_areg (regs, 7) + 2, last_fault_for_exception_3);
+			x_put_word (m68k_areg (regs, 7) + 6, last_op_for_exception_3);
+			x_put_word (m68k_areg (regs, 7) + 8, regs.sr);
+			x_put_long (m68k_areg (regs, 7) + 10, last_addr_for_exception_3);
+			write_log (_T("Exception %d (%x) at %x -> %x!\n"), nr, last_fault_for_exception_3, currpc, get_long_debug (regs.vbr + 4 * vector_nr));
+#ifdef WINUAE_FOR_HATARI
+			fprintf(stderr,"%s Error at address $%x, PC=$%x addr_e3=%x op_e3=%x\n", nr==2?"Bus":"Address", last_fault_for_exception_3, currpc, last_addr_for_exception_3 , last_op_for_exception_3);
+#endif
+			goto kludge_me_do;
+		}
+	}
+	m68k_areg (regs, 7) -= 4;
+#ifndef WINUAE_FOR_HATARI
+	/* TODO NP check exception_pc() is fixed and remove ifndef */
+	x_put_long (m68k_areg (regs, 7), currpc);
+#else
+	x_put_long (m68k_areg (regs, 7), m68k_getpc ());
+#endif
+	m68k_areg (regs, 7) -= 2;
+	x_put_word (m68k_areg (regs, 7), regs.sr);
+kludge_me_do:
+	newpc = x_get_long (regs.vbr + 4 * vector_nr);
+	exception_in_exception = 0;
+	if (newpc & 1) {
+		if (nr == 2 || nr == 3)
+			cpu_halt (2);
+		else
+			exception3_notinstruction(regs.ir, newpc);
+		return;
+	}
+	m68k_setpc (newpc);
+#ifdef JIT
+	set_special (SPCFLAG_END_COMPILE);
+#endif
+	fill_prefetch ();
+	exception_trace (nr);
+}
+
+// address = format $2 stack frame address field
+static void ExceptionX (int nr, uaecptr address)
+{
+	regs.exception = nr;
+	if (cpu_tracer) {
+		cputrace.state = nr;
+	}
+
+#ifdef JIT
+	if (currprefs.cachesize)
+		regs.instruction_pc = address == -1 ? m68k_getpc () : address;
+#endif
+#ifdef CPUEMU_13
+	if (currprefs.cpu_cycle_exact && currprefs.cpu_model <= 68010)
+		Exception_ce000 (nr);
+	else
+#endif
+		if (currprefs.mmu_model) {
+			if (currprefs.cpu_model == 68030)
+				Exception_mmu030 (nr, m68k_getpc ());
+			else
+				Exception_mmu (nr, m68k_getpc ());
+		} else {
+			Exception_normal (nr);
+		}
+
+#ifndef WINUAE_FOR_HATARI
+	if (debug_illegal && !in_rom (M68K_GETPC)) {
+		if (nr <= 63 && (debug_illegal_mask & ((uae_u64)1 << nr))) {
+			write_log (_T("Exception %d breakpoint\n"), nr);
+			activate_debugger ();
+		}
+	}
+#endif
+	regs.exception = 0;
+	if (cpu_tracer) {
+		cputrace.state = 0;
+	}
+}
+
+void REGPARAM2 Exception (int nr)
+{
+	ExceptionX (nr, -1);
+}
+void REGPARAM2 ExceptionL (int nr, uaecptr address)
+{
+	ExceptionX (nr, address);
+}
+
+static void do_interrupt (int nr)
+{
+#ifndef WINUAE_FOR_HATARI
+	if (debug_dma)
+		record_dma_event (DMA_EVENT_CPUIRQ, current_hpos (), vpos);
+
+	if (inputrecord_debug & 2) {
+		if (input_record > 0)
+			inprec_recorddebug_cpu (2);
+		else if (input_play > 0)
+			inprec_playdebug_cpu (2);
+	}
+#endif
+
+	regs.stopped = 0;
+	unset_special (SPCFLAG_STOP);
+	assert (nr < 8 && nr >= 0);
+
+	Exception (nr + 24);
+
+	regs.intmask = nr;
+	doint ();
+}
+
+void NMI (void)
+{
+	do_interrupt (7);
+}
+
+static void m68k_reset_sr(void)
+{
+	SET_XFLG ((regs.sr >> 4) & 1);
+	SET_NFLG ((regs.sr >> 3) & 1);
+	SET_ZFLG ((regs.sr >> 2) & 1);
+	SET_VFLG ((regs.sr >> 1) & 1);
+	SET_CFLG (regs.sr & 1);
+	regs.t1 = (regs.sr >> 15) & 1;
+	regs.t0 = (regs.sr >> 14) & 1;
+	regs.s  = (regs.sr >> 13) & 1;
+	regs.m  = (regs.sr >> 12) & 1;
+	regs.intmask = (regs.sr >> 8) & 7;
+	/* set stack pointer */
+	if (regs.s)
+		m68k_areg (regs, 7) = regs.isp;
+	else
+		m68k_areg (regs, 7) = regs.usp;
+}
+
+static void m68k_reset2(bool hardreset)
+{
+	uae_u32 v;
+
+	regs.halted = 0;
+#ifndef WINUAE_FOR_HATARI
+	gui_data.cpu_halted = 0;
+	gui_led (LED_CPU, 0, -1);
+#endif
+
+	regs.spcflags = 0;
+	m68k_reset_delay = 0;
+	regs.ipl = regs.ipl_pin = 0;
+
+#ifdef SAVESTATE
+	if (isrestore ()) {
+		m68k_reset_sr();
+		m68k_setpc_normal (regs.pc);
+		return;
+	} else {
+		m68k_reset_delay = currprefs.reset_delay;
+		set_special(SPCFLAG_CHECK);
+	}
+#endif
+	regs.s = 1;
+#ifndef WINUAE_FOR_HATARI
+	if (currprefs.cpuboard_type) {
+       		uaecptr stack;
+		v = cpuboard_get_reset_pc(&stack);
+		m68k_areg (regs, 7) = stack;
+	} else {
+		v = get_long (4);
+		m68k_areg (regs, 7) = get_long (0);
+      	}
+#else
+	v = get_long (4);
+	m68k_areg (regs, 7) = get_long (0);
+#endif
+	m68k_setpc_normal(v);
+	regs.m = 0;
+	regs.stopped = 0;
+	regs.t1 = 0;
+	regs.t0 = 0;
+	SET_ZFLG (0);
+	SET_XFLG (0);
+	SET_CFLG (0);
+	SET_VFLG (0);
+	SET_NFLG (0);
+	regs.intmask = 7;
+	regs.vbr = regs.sfc = regs.dfc = 0;
+	regs.irc = 0xffff;
+#ifdef FPUEMU
+	fpu_reset ();
+#endif
+	regs.caar = regs.cacr = 0;
+	regs.itt0 = regs.itt1 = regs.dtt0 = regs.dtt1 = 0;
+	regs.tcr = regs.mmusr = regs.urp = regs.srp = regs.buscr = 0;
+	mmu_tt_modified (); 
+	if (currprefs.cpu_model == 68020) {
+		regs.cacr |= 8;
+		set_cpu_caches (false);
+	}
+
+	mmufixup[0].reg = -1;
+	mmufixup[1].reg = -1;
+	if (currprefs.mmu_model >= 68040) {
+		mmu_reset ();
+		mmu_set_tc (regs.tcr);
+		mmu_set_super (regs.s != 0);
+	} else if (currprefs.mmu_model == 68030) {
+		mmu030_reset (hardreset || regs.halted);
+	} else {
+#ifndef WINUAE_FOR_HATARI
+		a3000_fakekick (0);
+#endif
+		/* only (E)nable bit is zeroed when CPU is reset, A3000 SuperKickstart expects this */
+		fake_tc_030 &= ~0x80000000;
+		fake_tt0_030 &= ~0x80000000;
+		fake_tt1_030 &= ~0x80000000;
+		if (hardreset || regs.halted) {
+			fake_srp_030 = fake_crp_030 = 0;
+			fake_tt0_030 = fake_tt1_030 = fake_tc_030 = 0;
+		}
+		fake_mmusr_030 = 0;
+	}
+
+	/* 68060 FPU is not compatible with 68040,
+	* 68060 accelerators' boot ROM disables the FPU
+	*/
+	regs.pcr = 0;
+	if (currprefs.cpu_model == 68060) {
+		regs.pcr = currprefs.fpu_model == 68060 ? MC68060_PCR : MC68EC060_PCR;
+		regs.pcr |= (currprefs.cpu060_revision & 0xff) << 8;
+#ifndef WINUAE_FOR_HATARI
+		if (kickstart_rom)
+			regs.pcr |= 2; /* disable FPU */
+#endif
+	}
+	regs.ce020memcycles = 0;
+	fill_prefetch ();
+}
+void m68k_reset(void)
+{
+	m68k_reset2(false);
+}
+
+
+void REGPARAM2 op_unimpl (uae_u16 opcode)
+{
+	static int warned;
+	if (warned < 20) {
+		write_log (_T("68060 unimplemented opcode %04X, PC=%08x\n"), opcode, regs.instruction_pc);
+		warned++;
+	}
+	ExceptionL (61, regs.instruction_pc);
+}
+
+uae_u32 REGPARAM2 op_illg (uae_u32 opcode)
+{
+	uaecptr pc = m68k_getpc ();
+	static int warned;
+
+#ifndef WINUAE_FOR_HATARI
+	int inrom = in_rom (pc);
+	int inrt = in_rtarea (pc);
+
+	if (cloanto_rom && (opcode & 0xF100) == 0x7100) {
+		m68k_dreg (regs, (opcode >> 9) & 7) = (uae_s8)(opcode & 0xFF);
+		m68k_incpc_normal (2);
+		fill_prefetch ();
+		return 4;
+	}
+
+	if (opcode == 0x4E7B && inrom) {
+		if (get_long (0x10) == 0) {
+			notify_user (NUMSG_KS68020);
+			uae_restart (-1, NULL);
+		}
+	}
+
+#ifdef AUTOCONFIG
+	if (opcode == 0xFF0D && inrt) {
+		/* User-mode STOP replacement */
+		m68k_setstopped ();
+		return 4;
+	}
+
+	if ((opcode & 0xF000) == 0xA000 && inrt) {
+		/* Calltrap. */
+		m68k_incpc_normal (2);
+		m68k_handle_trap(opcode & 0xFFF);
+		fill_prefetch ();
+		return 4;
+	}
+#endif
+#endif
+
+	if ((opcode & 0xF000) == 0xF000) {
+#ifndef WINUAE_FOR_HATARI
+		if (warned < 20) {
+			write_log(_T("B-Trap %04X at %08X -> %08X\n"), opcode, pc, get_long_debug(regs.vbr + 0x2c));
+			warned++;
+		}
+#endif
+		Exception (0xB);
+		//activate_debugger ();
+		return 4;
+	}
+	if ((opcode & 0xF000) == 0xA000) {
+#ifndef WINUAE_FOR_HATARI
+		if (warned < 20) {
+			write_log(_T("A-Trap %04X at %08X -> %08X\n"), opcode, pc, get_long_debug(regs.vbr + 0x28));
+			warned++;
+		}
+#endif
+		Exception (0xA);
+		//activate_debugger();
+		return 4;
+	}
+	if (warned < 20) {
+		write_log (_T("Illegal instruction: %04x at %08X -> %08X\n"), opcode, pc, get_long_debug(regs.vbr + 0x10));
+		warned++;
+		//activate_debugger();
+	}
+
+	Exception (4);
+	return 4;
+}
+
+#ifdef CPUEMU_0
+
+static bool mmu_op30fake_pmove (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
+{
+	int mode = (opcode >> 3) & 7;
+	int rreg = opcode & 7;
+	int preg = (next >> 10) & 31;
+	int rw = (next >> 9) & 1;
+	int fd = (next >> 8) & 1;
+	const TCHAR *reg = NULL;
+	uae_u32 otc = fake_tc_030;
+	int siz;
+
+	// Dn, An, (An)+, -(An), immediate and PC-relative not allowed
+	if (mode == 0 || mode == 1 || mode == 3 || mode == 4 || mode == 6 || (mode == 7 && rreg > 1)) {
+		op_illg (opcode);
+		return true;
+	}
+
+	switch (preg)
+	{
+	case 0x10: // TC
+		reg = _T("TC");
+		siz = 4;
+		if (rw)
+			x_put_long (extra, fake_tc_030);
+		else
+			fake_tc_030 = x_get_long (extra);
+		break;
+	case 0x12: // SRP
+		reg = _T("SRP");
+		siz = 8;
+		if (rw) {
+			x_put_long (extra, fake_srp_030 >> 32);
+			x_put_long (extra + 4, (uae_u32)fake_srp_030);
+		} else {
+			fake_srp_030 = (uae_u64)x_get_long (extra) << 32;
+			fake_srp_030 |= x_get_long (extra + 4);
+		}
+		break;
+	case 0x13: // CRP
+		reg = _T("CRP");
+		siz = 8;
+		if (rw) {
+			x_put_long (extra, fake_crp_030 >> 32);
+			x_put_long (extra + 4, (uae_u32)fake_crp_030);
+		} else {
+			fake_crp_030 = (uae_u64)x_get_long (extra) << 32;
+			fake_crp_030 |= x_get_long (extra + 4);
+		}
+		break;
+	case 0x18: // MMUSR
+		reg = _T("MMUSR");
+		siz = 2;
+		if (rw)
+			x_put_word (extra, fake_mmusr_030);
+		else
+			fake_mmusr_030 = x_get_word (extra);
+		break;
+	case 0x02: // TT0
+		reg = _T("TT0");
+		siz = 4;
+		if (rw)
+			x_put_long (extra, fake_tt0_030);
+		else
+			fake_tt0_030 = x_get_long (extra);
+		break;
+	case 0x03: // TT1
+		reg = _T("TT1");
+		siz = 4;
+		if (rw)
+			x_put_long (extra, fake_tt1_030);
+		else
+			fake_tt1_030 = x_get_long (extra);
+		break;
+	}
+
+	if (!reg) {
+		op_illg (opcode);
+		return true;
+	}
+#if MMUOP_DEBUG > 0
+	{
+		uae_u32 val;
+		if (siz == 8) {
+			uae_u32 val2 = x_get_long (extra);
+			val = x_get_long (extra + 4);
+			if (rw)
+				write_log (_T("PMOVE %s,%08X%08X"), reg, val2, val);
+			else
+				write_log (_T("PMOVE %08X%08X,%s"), val2, val, reg);
+		} else {
+			if (siz == 4)
+				val = x_get_long (extra);
+			else
+				val = x_get_word (extra);
+			if (rw)
+				write_log (_T("PMOVE %s,%08X"), reg, val);
+			else
+				write_log (_T("PMOVE %08X,%s"), val, reg);
+		}
+		write_log (_T(" PC=%08X\n"), pc);
+	}
+#endif
+#ifndef WINUAE_FOR_HATARI
+	if ((currprefs.cs_mbdmac & 1) && currprefs.mbresmem_low_size > 0) {
+		if (otc != fake_tc_030) {
+			a3000_fakekick (fake_tc_030 & 0x80000000);
+		}
+	}
+#endif
+	return false;
+}
+
+static bool mmu_op30fake_ptest (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
+{
+#if MMUOP_DEBUG > 0
+	TCHAR tmp[10];
+
+	tmp[0] = 0;
+	if ((next >> 8) & 1)
+		_stprintf (tmp, _T(",A%d"), (next >> 4) & 15);
+	write_log (_T("PTEST%c %02X,%08X,#%X%s PC=%08X\n"),
+		((next >> 9) & 1) ? 'W' : 'R', (next & 15), extra, (next >> 10) & 7, tmp, pc);
+#endif
+	fake_mmusr_030 = 0;
+	return false;
+}
+
+static bool mmu_op30fake_pflush (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
+{
+	int mode = (opcode >> 3) & 7;
+	int rreg = opcode & 7;
+	int flushmode = (next >> 10) & 7;
+	int fc = next & 31;
+	int mask = (next >> 5) & 3;
+	TCHAR fname[100];
+
+	switch (flushmode)
+	{
+	case 6:
+		// Dn, An, (An)+, -(An), immediate and PC-relative not allowed
+		if (mode == 0 || mode == 1 || mode == 3 || mode == 4 || mode == 6 || (mode == 7 && rreg > 1)) {
+			op_illg (opcode);
+			return true;
+		}
+		_stprintf (fname, _T("FC=%x MASK=%x EA=%08x"), fc, mask, 0);
+		break;
+	case 4:
+		_stprintf (fname, _T("FC=%x MASK=%x"), fc, mask);
+		break;
+	case 1:
+		_tcscpy (fname, _T("ALL"));
+		break;
+	default:
+		op_illg (opcode);
+		return true;
+	}
+#if MMUOP_DEBUG > 0
+	write_log (_T("PFLUSH %s PC=%08X\n"), fname, pc);
+#endif
+	return false;
+}
+
+// 68030 (68851) MMU instructions only
+bool mmu_op30 (uaecptr pc, uae_u32 opcode, uae_u16 extra, uaecptr extraa)
+{
+	if (currprefs.mmu_model) {
+		if (extra & 0x8000) {
+			return mmu_op30_ptest (pc, opcode, extra, extraa);
+		} else if ((extra&0xE000)==0x2000 && (extra & 0x1C00)) {
+			return mmu_op30_pflush (pc, opcode, extra, extraa);
+		} else if ((extra&0xE000)==0x2000 && !(extra & 0x1C00)) {
+	        return mmu_op30_pload (pc, opcode, extra, extraa);
+		} else {
+			return mmu_op30_pmove (pc, opcode, extra, extraa);
+		}
+		return false;
+	}
+
+	int type = extra >> 13;
+
+	switch (type)
+	{
+	case 0:
+	case 2:
+	case 3:
+		return mmu_op30fake_pmove (pc, opcode, extra, extraa);
+	break;
+	case 1:
+		return mmu_op30fake_pflush (pc, opcode, extra, extraa);
+	break;
+	case 4:
+		return mmu_op30fake_ptest (pc, opcode, extra, extraa);
+	break;
+	default:
+		op_illg (opcode);
+		return true;
+	break;
+	}
+}
+
+// 68040+ MMU instructions only
+void mmu_op (uae_u32 opcode, uae_u32 extra)
+{
+	if (currprefs.mmu_model) {
+		mmu_op_real (opcode, extra);
+		return;
+	}
+#if MMUOP_DEBUG > 1
+	write_log (_T("mmu_op %04X PC=%08X\n"), opcode, m68k_getpc ());
+#endif
+	if ((opcode & 0xFE0) == 0x0500) {
+		/* PFLUSH */
+		regs.mmusr = 0;
+#if MMUOP_DEBUG > 0
+		write_log (_T("PFLUSH\n"));
+#endif
+		return;
+	} else if ((opcode & 0x0FD8) == 0x548) {
+		if (currprefs.cpu_model < 68060) { /* PTEST not in 68060 */
+			/* PTEST */
+#if MMUOP_DEBUG > 0
+			write_log (_T("PTEST\n"));
+#endif
+			return;
+		}
+	} else if ((opcode & 0x0FB8) == 0x588) {
+		/* PLPA */
+		if (currprefs.cpu_model == 68060) {
+#if MMUOP_DEBUG > 0
+			write_log (_T("PLPA\n"));
+#endif
+			return;
+		}
+	}
+#if MMUOP_DEBUG > 0
+	write_log (_T("Unknown MMU OP %04X\n"), opcode);
+#endif
+	m68k_setpc_normal (m68k_getpc () - 2);
+	op_illg (opcode);
+}
+
+#endif
+
+static uaecptr last_trace_ad = 0;
+
+static void do_trace (void)
+{
+	if (regs.t0 && currprefs.cpu_model >= 68020) {
+		uae_u16 opcode;
+		/* should also include TRAP, CHK, SR modification FPcc */
+		/* probably never used so why bother */
+		/* We can afford this to be inefficient... */
+		m68k_setpc_normal (m68k_getpc ());
+		fill_prefetch ();
+		opcode = x_get_word (regs.pc);
+		if (opcode == 0x4e73 			/* RTE */
+			|| opcode == 0x4e74 		/* RTD */
+			|| opcode == 0x4e75 		/* RTS */
+			|| opcode == 0x4e77 		/* RTR */
+			|| opcode == 0x4e76 		/* TRAPV */
+			|| (opcode & 0xffc0) == 0x4e80 	/* JSR */
+			|| (opcode & 0xffc0) == 0x4ec0 	/* JMP */
+			|| (opcode & 0xff00) == 0x6100	/* BSR */
+			|| ((opcode & 0xf000) == 0x6000	/* Bcc */
+			&& cctrue ((opcode >> 8) & 0xf))
+			|| ((opcode & 0xf0f0) == 0x5050	/* DBcc */
+			&& !cctrue ((opcode >> 8) & 0xf)
+			&& (uae_s16)m68k_dreg (regs, opcode & 7) != 0))
+		{
+			last_trace_ad = m68k_getpc ();
+			unset_special (SPCFLAG_TRACE);
+			set_special (SPCFLAG_DOTRACE);
+		}
+	} else if (regs.t1) {
+		last_trace_ad = m68k_getpc ();
+		unset_special (SPCFLAG_TRACE);
+		set_special (SPCFLAG_DOTRACE);
+	}
+}
+
+static void check_uae_int_request(void)
+{
+#ifndef WINUAE_FOR_HATARI
+	if (uae_int_requested || uaenet_int_requested) {
+		if ((uae_int_requested & 0x00ff) || uaenet_int_requested)
+			INTREQ_f(0x8000 | 0x0008);
+		if (uae_int_requested & 0xff00)
+			INTREQ_f(0x8000 | 0x2000);
+		set_special(SPCFLAG_INT);
+	}
+#endif
+}
+
+void cpu_sleep_millis(int ms)
+{
+#ifndef WINUAE_FOR_HATARI
+#ifdef WITH_PPC
+	int state = ppc_state;
+	if (state)
+		uae_ppc_spinlock_release();
+#endif
+	sleep_millis_main(ms);
+#ifdef WITH_PPC
+	if (state)
+		uae_ppc_spinlock_get();
+#endif
+#endif
+}
+
+#define PPC_HALTLOOP_SCANLINES 25
+// ppc_cpu_idle
+// 0 = busy
+// 1-9 = wait, levels
+// 10 = max wait
+
+static bool haltloop(void)
+{
+#ifndef WINUAE_FOR_HATARI
+#ifdef WITH_PPC
+	if (regs.halted < 0) {
+		int rpt_end = 0;
+		int ovpos = vpos;
+
+		while (regs.halted) {
+			int vsynctimeline = vsynctimebase / (maxvpos_display + 1);
+			int lines;
+			int rpt_scanline = read_processor_time();
+			int rpt_end = rpt_scanline + vsynctimeline;
+
+			// See expansion handling.
+			// Dialog must be opened from main thread.
+			if (regs.halted == -2) {
+				regs.halted = -1;
+				notify_user (NUMSG_UAEBOOTROM_PPC);
+			}
+
+			if (currprefs.ppc_cpu_idle) {
+
+				int maxlines = 100 - (currprefs.ppc_cpu_idle - 1) * 10;
+				int i;
+
+				event_wait = false;
+				for (i = 0; i < ev_max; i++) {
+					if (i == ev_hsync)
+						continue;
+					if (i == ev_audio)
+						continue;
+					if (!eventtab[i].active)
+						continue;
+					if (eventtab[i].evtime - currcycle < maxlines * maxhpos * CYCLE_UNIT)
+						break;
+				}
+				if (currprefs.ppc_cpu_idle >= 10 || (i == ev_max && vpos > 0 && vpos < maxvpos - maxlines)) {
+					cpu_sleep_millis(1);
+				}
+				check_uae_int_request();
+				uae_ppc_execute_check();
+
+				lines = (read_processor_time() - rpt_scanline) / vsynctimeline + 1;
+
+			} else {
+
+				event_wait = true;
+				lines = 0;
+
+			}
+
+			if (lines > maxvpos / 2)
+				lines = maxvpos / 2;
+
+			while (lines-- >= 0) {
+				ovpos = vpos;
+				while (ovpos == vpos) {
+					x_do_cycles(8 * CYCLE_UNIT);
+					uae_ppc_execute_check();
+					if (regs.spcflags & SPCFLAG_COPPER)
+						do_copper();
+					if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
+						if (regs.spcflags & SPCFLAG_BRK) {
+							unset_special(SPCFLAG_BRK);
+#ifdef DEBUGGER
+							if (debugging)
+								debug();
+#endif
+						}
+						return true;
+					}
+				}
+
+				// sync chipset with real time
+				for (;;) {
+					check_uae_int_request();
+					ppc_interrupt(intlev());
+					uae_ppc_execute_check();
+					if (event_wait)
+						break;
+					int d = read_processor_time() - rpt_end;
+					if (d < -2 * vsynctimeline || d >= 0)
+						break;
+				}
+			}
+
+
+		}
+
+	} else  {
+#endif
+		while (regs.halted) {
+			static int prevvpos;
+			if (vpos == 0 && prevvpos) {
+				prevvpos = 0;
+				cpu_sleep_millis(8);
+			}
+			if (vpos)
+				prevvpos = 1;
+			x_do_cycles(8 * CYCLE_UNIT);
+
+			if (regs.spcflags & SPCFLAG_COPPER)
+				do_copper();
+
+			if (regs.spcflags) {
+				if ((regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)))
+					return true;
+			}
+		}
+#ifdef WITH_PPC
+	}
+#endif
+
+	return false;
+#else
+	/* In Hatari, we don't use the halt state, we do a reset */
+	return false;
+#endif
+}
+
+#ifdef WITH_PPC
+static bool uae_ppc_poll_check_halt(void)
+{
+	if (regs.halted) {
+		if (haltloop())
+			return true;
+	}
+	return false;
+}
+#endif
+
+
+// handle interrupt delay (few cycles)
+STATIC_INLINE bool time_for_interrupt (void)
+{
+	return regs.ipl > regs.intmask || regs.ipl == 7;
+}
+
+void doint (void)
+{
+#ifdef WITH_PPC
+	if (ppc_state) {
+		if (!ppc_interrupt(intlev()))
+			return;
+	}
+#endif
+	if (m68k_interrupt_delay) {
+		regs.ipl_pin = intlev ();
+		unset_special (SPCFLAG_INT);
+		return;
+	}
+	if (currprefs.cpu_compatible && currprefs.cpu_model < 68020)
+		set_special (SPCFLAG_INT);
+	else
+		set_special (SPCFLAG_DOINT);
+}
+
+#ifndef WINUAE_FOR_HATARI
+#define IDLETIME (currprefs.cpu_idle * sleep_resolution / 1000)
+#endif
+
+#ifdef WINUAE_FOR_HATARI
+/*
+ * Handle special flags
+ */
+
+static bool do_specialties_interrupt (int Pending)
+{
+#if ENABLE_DSP_EMU
+    /* Check for DSP int first (if enabled) (level 6) */
+    if (regs.spcflags & SPCFLAG_DSP) {
+       if (DSP_ProcessIRQ() == true)
+         return true;
+    }
+#endif
+
+    /* Check for MFP ints (level 6) */
+    if (regs.spcflags & SPCFLAG_MFP) {
+       if (MFP_ProcessIRQ() == true)
+         return true;					/* MFP exception was generated, no higher interrupt can happen */
+    }
+
+    /* No MFP int, check for VBL/HBL ints (levels 4/2) */
+    if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
+	int intr = intlev ();
+	/* SPCFLAG_DOINT will be enabled again in MakeFromSR to handle pending interrupts! */
+//	unset_special (SPCFLAG_DOINT);
+	unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
+	if (intr != -1 && intr > regs.intmask) {
+	    do_interrupt (intr);			/* process the interrupt */
+	    return true;
+	}
+    }
+
+    return false;					/* no interrupt was found */
+}
+#endif
+
+static int do_specialties (int cycles)
+{
+	if (regs.spcflags & SPCFLAG_MODE_CHANGE)
+		return 1;
+	
+#ifndef WINUAE_FOR_HATARI
+	if (regs.spcflags & SPCFLAG_CHECK) {
+		if (regs.halted) {
+			if (haltloop())
+				return 1;
+		}
+		if (m68k_reset_delay) {
+			int vsynccnt = 60;
+			int vsyncstate = -1;
+			while (vsynccnt > 0 && !quit_program) {
+				x_do_cycles(8 * CYCLE_UNIT);
+				if (regs.spcflags & SPCFLAG_COPPER)
+					do_copper();
+				if (timeframes != vsyncstate) {
+					vsyncstate = timeframes;
+					vsynccnt--;
+				}
+			}
+		}
+		m68k_reset_delay = 0;
+		unset_special(SPCFLAG_CHECK);
+	}
+#endif
+
+#ifdef ACTION_REPLAY
+#ifdef ACTION_REPLAY_HRTMON
+	if ((regs.spcflags & SPCFLAG_ACTION_REPLAY) && hrtmon_flag != ACTION_REPLAY_INACTIVE) {
+		int isinhrt = (m68k_getpc () >= hrtmem_start && m68k_getpc () < hrtmem_start + hrtmem_size);
+		/* exit from HRTMon? */
+		if (hrtmon_flag == ACTION_REPLAY_ACTIVE && !isinhrt)
+			hrtmon_hide ();
+		/* HRTMon breakpoint? (not via IRQ7) */
+		if (hrtmon_flag == ACTION_REPLAY_IDLE && isinhrt)
+			hrtmon_breakenter ();
+		if (hrtmon_flag == ACTION_REPLAY_ACTIVATE)
+			hrtmon_enter ();
+	}
+#endif
+	if ((regs.spcflags & SPCFLAG_ACTION_REPLAY) && action_replay_flag != ACTION_REPLAY_INACTIVE) {
+		/*if (action_replay_flag == ACTION_REPLAY_ACTIVE && !is_ar_pc_in_rom ())*/
+		/*	write_log (_T("PC:%p\n"), m68k_getpc ());*/
+
+		if (action_replay_flag == ACTION_REPLAY_ACTIVATE || action_replay_flag == ACTION_REPLAY_DORESET)
+			action_replay_enter ();
+		if ((action_replay_flag == ACTION_REPLAY_HIDE || action_replay_flag == ACTION_REPLAY_ACTIVE) && !is_ar_pc_in_rom ()) {
+			action_replay_hide ();
+			unset_special (SPCFLAG_ACTION_REPLAY);
+		}
+		if (action_replay_flag == ACTION_REPLAY_WAIT_PC) {
+			/*write_log (_T("Waiting for PC: %p, current PC= %p\n"), wait_for_pc, m68k_getpc ());*/
+			if (m68k_getpc () == wait_for_pc) {
+				action_replay_flag = ACTION_REPLAY_ACTIVATE; /* Activate after next instruction. */
+			}
+		}
+	}
+#endif
+
+#ifndef WINUAE_FOR_HATARI
+	if (regs.spcflags & SPCFLAG_COPPER)
+		do_copper ();
+#endif
+
+#ifdef JIT
+	unset_special (SPCFLAG_END_COMPILE);   /* has done its job */
+#endif
+
+#ifndef WINUAE_FOR_HATARI
+	while ((regs.spcflags & SPCFLAG_BLTNASTY) && dmaen (DMA_BLITTER) && cycles > 0 && !currprefs.blitter_cycle_exact) {
+		int c = blitnasty ();
+		if (c < 0) {
+			break;
+		} else if (c > 0) {
+			cycles -= c * CYCLE_UNIT * 2;
+			if (cycles < CYCLE_UNIT)
+				cycles = 0;
+		} else {
+			c = 4;
+		}
+		x_do_cycles (c * CYCLE_UNIT);
+		if (regs.spcflags & SPCFLAG_COPPER)
+			do_copper ();
+#ifdef WITH_PPC
+		if (ppc_state)  {
+			if (uae_ppc_poll_check_halt())
+				return true;
+			uae_ppc_execute_check();
+		}
+#endif
+	}
+#endif
+
+#ifdef WINUAE_FOR_HATARI
+	if (regs.spcflags & SPCFLAG_BUSERROR) {
+		/* We can not execute bus errors directly in the memory handler
+		* functions since the PC should point to the address of the next
+		* instruction, so we're executing the bus errors here: */
+		unset_special(SPCFLAG_BUSERROR);
+		Exception(2);
+	}
+#endif
+
+	if (regs.spcflags & SPCFLAG_DOTRACE)
+		Exception (9);
+
+#ifndef WINUAE_FOR_HATARI
+	if (regs.spcflags & SPCFLAG_TRAP) {
+		unset_special (SPCFLAG_TRAP);
+		Exception (3);
+	}
+#endif
+	bool first = true;
+	while ((regs.spcflags & SPCFLAG_STOP) && !(regs.spcflags & SPCFLAG_BRK)) {
+	isstopped:
+#ifndef WINUAE_FOR_HATARI
+		check_uae_int_request();
+		{
+			extern void bsdsock_fake_int_handler (void);
+			extern int volatile bsd_int_requested;
+			if (bsd_int_requested)
+				bsdsock_fake_int_handler ();
+		}
+#endif
+
+		if (cpu_tracer > 0) {
+			cputrace.stopped = regs.stopped;
+			cputrace.intmask = regs.intmask;
+			cputrace.sr = regs.sr;
+			cputrace.state = 1;
+			cputrace.pc = m68k_getpc ();
+			cputrace.memoryoffset = 0;
+			cputrace.cyclecounter = cputrace.cyclecounter_pre = cputrace.cyclecounter_post = 0;
+			cputrace.readcounter = cputrace.writecounter = 0;
+		}
+		if (!first)
+			x_do_cycles (currprefs.cpu_cycle_exact ? 2 * CYCLE_UNIT : 4 * CYCLE_UNIT);
+
+#ifdef WINUAE_FOR_HATARI
+		if (!first)
+		{
+			if ( currprefs.cpu_cycle_exact )
+				M68000_AddCycles(2);
+			else						/* TODO [NP] : always do only M68000_AddCycles(2) ? */
+				M68000_AddCycles(4);
+		}
+
+		/* It is possible one or more ints happen at the same time */
+		/* We must process them during the same cpu cycle then choose the highest priority one */
+		while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) )
+			CALL_VAR(PendingInterruptFunction);
+		if ( MFP_UpdateNeeded == true )
+			MFP_UpdateIRQ ( 0 );
+
+		/* Check is there's an interrupt to process (could be a delayed MFP interrupt) */
+		if (regs.spcflags & SPCFLAG_MFP) {
+			MFP_DelayIRQ ();			/* Handle IRQ propagation */
+			M68000_Update_intlev ();		/* Refresh the list of pending interrupts */
+		}
+#endif
+		first = false;
+#ifndef WINUAE_FOR_HATARI
+		if (regs.spcflags & SPCFLAG_COPPER)
+			do_copper ();
+#endif
+
+		if (m68k_interrupt_delay) {
+			ipl_fetch ();
+			if (time_for_interrupt ()) {
+				do_interrupt (regs.ipl);
+			}
+		} else {
+			if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
+				int intr = intlev ();
+				unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
+#ifdef WITH_PPC
+				bool m68kint = true;
+				if (ppc_state) {
+					m68kint = ppc_interrupt(intr);
+				}
+				if (m68kint) {
+#endif
+					if (intr > 0 && intr > regs.intmask)
+						do_interrupt (intr);
+#ifdef WITH_PPC
+				}
+#endif
+			}
+		}
+
+		if (regs.spcflags & SPCFLAG_MODE_CHANGE) {
+			m68k_resumestopped();
+			return 1;
+		}
+
+#ifdef WITH_PPC
+		if (ppc_state) {
+			uae_ppc_execute_check();
+			uae_ppc_poll_check_halt();
+		}
+#endif
+
+	}
+
+	if (regs.spcflags & SPCFLAG_TRACE)
+		do_trace ();
+
+#ifdef WINUAE_FOR_HATARI
+	if (regs.spcflags & SPCFLAG_MFP) {
+		MFP_DelayIRQ ();			/* Handle IRQ propagation */
+		M68000_Update_intlev ();		/* Refresh the list of pending interrupts */
+	}
+#endif
+
+	if (m68k_interrupt_delay) {
+		if (time_for_interrupt ()) {
+			do_interrupt (regs.ipl);
+		}
+	} else {
+		if (regs.spcflags & SPCFLAG_INT) {
+			int intr = intlev ();
+			unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
+			if (intr > 0 && (intr > regs.intmask || intr == 7))
+				do_interrupt (intr);
+		}
+	}
+
+	if (regs.spcflags & SPCFLAG_DOINT) {
+		unset_special (SPCFLAG_DOINT);
+		set_special (SPCFLAG_INT);
+	}
+
+#ifdef WINUAE_FOR_HATARI
+        if (regs.spcflags & SPCFLAG_DEBUGGER)
+		DebugCpu_Check();
+#endif
+
+	if (regs.spcflags & SPCFLAG_BRK) {
+		unset_special(SPCFLAG_BRK);
+#ifdef DEBUGGER
+		if (debugging) {
+			debug();
+			if (regs.stopped)
+				goto isstopped;
+		}
+#endif
+#ifdef WINUAE_FOR_HATARI
+		return 1;			/* Exit the upper run_xxx() function */
+#endif
+	}
+
+	return 0;
+}
+
+//static uae_u32 pcs[1000];
+
+#ifndef WINUAE_FOR_HATARI
+#if DEBUG_CD32CDTVIO
+
+static uae_u32 cd32nextpc, cd32request;
+
+static void out_cd32io2 (void)
+{
+	uae_u32 request = cd32request;
+	write_log (_T("%08x returned\n"), request);
+	//write_log (_T("ACTUAL=%d ERROR=%d\n"), get_long (request + 32), get_byte (request + 31));
+	cd32nextpc = 0;
+	cd32request = 0;
+}
+
+static void out_cd32io (uae_u32 pc)
+{
+	TCHAR out[100];
+	int ioreq = 0;
+	uae_u32 request = m68k_areg (regs, 1);
+
+	if (pc == cd32nextpc) {
+		out_cd32io2 ();
+		return;
+	}
+	out[0] = 0;
+	switch (pc)
+	{
+	case 0xe57cc0:
+	case 0xf04c34:
+		_stprintf (out, _T("opendevice"));
+		break;
+	case 0xe57ce6:
+	case 0xf04c56:
+		_stprintf (out, _T("closedevice"));
+		break;
+	case 0xe57e44:
+	case 0xf04f2c:
+		_stprintf (out, _T("beginio"));
+		ioreq = 1;
+		break;
+	case 0xe57ef2:
+	case 0xf0500e:
+		_stprintf (out, _T("abortio"));
+		ioreq = -1;
+		break;
+	}
+	if (out[0] == 0)
+		return;
+	if (cd32request)
+		write_log (_T("old request still not returned!\n"));
+	cd32request = request;
+	cd32nextpc = get_long (m68k_areg (regs, 7));
+	write_log (_T("%s A1=%08X\n"), out, request);
+	if (ioreq) {
+		static int cnt = 0;
+		int cmd = get_word (request + 28);
+#if 0
+		if (cmd == 33) {
+			uaecptr data = get_long (request + 40);
+			write_log (_T("CD_CONFIG:\n"));
+			for (int i = 0; i < 16; i++) {
+				write_log (_T("%08X=%08X\n"), get_long (data), get_long (data + 4));
+				data += 8;
+			}
+		}
+#endif
+#if 0
+		if (cmd == 37) {
+			cnt--;
+			if (cnt <= 0)
+				activate_debugger ();
+		}
+#endif
+		write_log (_T("CMD=%d DATA=%08X LEN=%d %OFF=%d PC=%x\n"),
+			cmd, get_long (request + 40),
+			get_long (request + 36), get_long (request + 44), M68K_GETPC);
+	}
+	if (ioreq < 0)
+		;//activate_debugger ();
+}
+
+#endif
+#endif
+
+static void bus_error(void)
+{
+	TRY (prb2) {
+		Exception (2);
+	} CATCH (prb2) {
+		cpu_halt (1);
+	} ENDTRY
+}
+
+#ifndef CPUEMU_11
+
+static void m68k_run_1 (void)
+{
+}
+
+#else
+
+/* It's really sad to have two almost identical functions for this, but we
+do it all for performance... :(
+This version emulates 68000's prefetch "cache" */
+static void m68k_run_1 (void)
+{
+	struct regstruct *r = ®s;
+	bool exit = false;
+printf ( "run_1\n" );
+
+	while (!exit) {
+		TRY (prb) {
+			while (!exit) {
+				r->opcode = r->ir;
+
+				count_instr (r->opcode);
+
+#ifdef WINUAE_FOR_HATARI
+				//m68k_dumpstate_file(stderr, NULL);
+				if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
+				{
+					int FrameCycles, HblCounterVideo, LineCycles;
+
+					Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+
+					LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
+					m68k_disasm_file(stderr, m68k_getpc (), NULL, 1);
+				}
+#endif
+
+#ifndef WINUAE_FOR_HATARI
+#if DEBUG_CD32CDTVIO
+				out_cd32io (m68k_getpc ());
+#endif
+#endif
+
+#if 0
+				int pc = m68k_getpc ();
+				if (pc == 0xdff002)
+					write_log (_T("hip\n"));
+				if (pc != pcs[0] && (pc < 0xd00000 || pc > 0x1000000)) {
+					memmove (pcs + 1, pcs, 998 * 4);
+					pcs[0] = pc;
+					//write_log (_T("%08X-%04X "), pc, r->opcode);
+				}
+#endif
+				do_cycles (cpu_cycles);
+				r->instruction_pc = m68k_getpc ();
+				cpu_cycles = (*cpufunctbl[r->opcode])(r->opcode);
+				cpu_cycles = adjust_cycles (cpu_cycles);
+
+#ifdef WINUAE_FOR_HATARI
+				M68000_AddCyclesWithPairing(cpu_cycles * 2 / CYCLE_UNIT);
+
+				if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
+					/* Add some extra cycles to simulate a wait state */
+					unset_special(SPCFLAG_EXTRA_CYCLES);
+					M68000_AddCycles(nWaitStateCycles);
+					nWaitStateCycles = 0;
+				}
+
+				/* We can have several interrupts at the same time before the next CPU instruction */
+				/* We must check for pending interrupt and call do_specialties_interrupt() only */
+				/* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
+				/* and prevent exiting the STOP state when calling do_specialties() after. */
+				/* For performance, we first test PendingInterruptCount, then regs.spcflags */
+				while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
+					CALL_VAR(PendingInterruptFunction);		/* call the interrupt handler */
+				if ( MFP_UpdateNeeded == true )
+					MFP_UpdateIRQ ( 0 );
+#endif
+
+				if (r->spcflags) {
+					if (do_specialties (cpu_cycles))
+						exit = true;
+				}
+				regs.ipl = regs.ipl_pin;
+				if (!currprefs.cpu_compatible || (currprefs.cpu_cycle_exact && currprefs.cpu_model <= 68010))
+					exit = true;
+			}
+		} CATCH (prb) {
+			bus_error();
+			if (r->spcflags) {
+				if (do_specialties(cpu_cycles))
+					exit = true;
+			}
+			regs.ipl = regs.ipl_pin;
+		} ENDTRY
+	}
+}
+
+#endif /* CPUEMU_11 */
+
+#ifndef CPUEMU_13
+
+static void m68k_run_1_ce (void)
+{
+}
+
+#else
+
+/* cycle-exact m68k_run () */
+
+static void m68k_run_1_ce (void)
+{
+	struct regstruct *r = ®s;
+	bool first = true;
+	bool exit = false;
+printf ( "run_1_ce\n" );
+
+	while (!exit) {
+		TRY (prb) {
+			if (first) {
+				if (cpu_tracer < 0) {
+					memcpy (&r->regs, &cputrace.regs, 16 * sizeof (uae_u32));
+					r->ir = cputrace.ir;
+					r->irc = cputrace.irc;
+					r->sr = cputrace.sr;
+					r->usp = cputrace.usp;
+					r->isp = cputrace.isp;
+					r->intmask = cputrace.intmask;
+					r->stopped = cputrace.stopped;
+					m68k_setpc (cputrace.pc);
+					if (!r->stopped) {
+						if (cputrace.state > 1) {
+							write_log (_T("CPU TRACE: EXCEPTION %d\n"), cputrace.state);
+							Exception (cputrace.state);
+						} else if (cputrace.state == 1) {
+							write_log (_T("CPU TRACE: %04X\n"), cputrace.opcode);
+							(*cpufunctbl[cputrace.opcode])(cputrace.opcode);
+						}
+					} else {
+						write_log (_T("CPU TRACE: STOPPED\n"));
+					}
+					if (r->stopped)
+						set_special (SPCFLAG_STOP);
+					set_cpu_tracer (false);
+					goto cont;
+				}
+				set_cpu_tracer (false);
+				first = false;
+			}
+
+			while (!exit) {
+				r->opcode = r->ir;
+
+#ifdef WINUAE_FOR_HATARI
+				//m68k_dumpstate_file(stderr, NULL);
+				if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
+				{
+					int FrameCycles, HblCounterVideo, LineCycles;
+
+					Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+
+					LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
+					m68k_disasm_file(stderr, m68k_getpc (), NULL, 1);
+				}
+#endif
+
+#ifndef WINUAE_FOR_HATARI
+#if DEBUG_CD32CDTVIO
+				out_cd32io (m68k_getpc ());
+#endif
+#endif
+				if (cpu_tracer) {
+					memcpy (&cputrace.regs, &r->regs, 16 * sizeof (uae_u32));
+					cputrace.opcode = r->opcode;
+					cputrace.ir = r->ir;
+					cputrace.irc = r->irc;
+					cputrace.sr = r->sr;
+					cputrace.usp = r->usp;
+					cputrace.isp = r->isp;
+					cputrace.intmask = r->intmask;
+					cputrace.stopped = r->stopped;
+					cputrace.state = 1;
+					cputrace.pc = m68k_getpc ();
+					cputrace.startcycles = get_cycles ();
+					cputrace.memoryoffset = 0;
+					cputrace.cyclecounter = cputrace.cyclecounter_pre = cputrace.cyclecounter_post = 0;
+					cputrace.readcounter = cputrace.writecounter = 0;
+				}
+
+#ifndef WINUAE_FOR_HATARI
+				if (inputrecord_debug & 4) {
+					if (input_record > 0)
+						inprec_recorddebug_cpu (1);
+					else if (input_play > 0)
+						inprec_playdebug_cpu (1);
+				}
+#endif
+
+#ifdef WINUAE_FOR_HATARI
+				currcycle = 0;
+#endif
+
+				r->instruction_pc = m68k_getpc ();
+				(*cpufunctbl[r->opcode])(r->opcode);
+				wait_memory_cycles();			// TODO NP : ici, ou plus bas ?
+#ifdef WINUAE_FOR_HATARI
+//fprintf ( stderr, "cyc_1ce %d\n" , currcycle );
+				/* HACK for Hatari: Adding cycles should of course not be done
+				* here in CE mode (so this should be removed later), but until
+				* we're really there, this helps to get this mode running
+				* at least to a basic extend! */
+				M68000_AddCyclesWithPairing(currcycle * 2 / CYCLE_UNIT);
+
+				if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
+					/* Add some extra cycles to simulate a wait state */
+					unset_special(SPCFLAG_EXTRA_CYCLES);
+					M68000_AddCycles(nWaitStateCycles);
+					nWaitStateCycles = 0;
+				}
+
+				while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
+					CALL_VAR(PendingInterruptFunction);		/* call the interrupt handler */
+				if ( MFP_UpdateNeeded == true )
+					MFP_UpdateIRQ ( 0 );
+#endif
+
+				if (cpu_tracer) {
+					cputrace.state = 0;
+				}
+cont:
+				if (cputrace.needendcycles) {
+					cputrace.needendcycles = 0;
+					write_log (_T("STARTCYCLES=%08x ENDCYCLES=%08lx\n"), cputrace.startcycles, get_cycles ());
+#ifndef WINUAE_FOR_HATARI
+					log_dma_record ();
+#endif
+				}
+
+				if (r->spcflags || time_for_interrupt ()) {
+					if (do_specialties (0))
+						exit = true;
+				}
+
+				if (!currprefs.cpu_cycle_exact || currprefs.cpu_model > 68010)
+					exit = true;
+			}
+		} CATCH (prb) {
+			bus_error();
+			if (r->spcflags || time_for_interrupt()) {
+				if (do_specialties(0))
+					exit = true;
+			}
+		} ENDTRY
+	}
+}
+
+#endif
+
+#ifdef CPUEMU_20
+// emulate simple prefetch
+static uae_u16 get_word_020_prefetchf (uae_u32 pc)
+{
+	if (pc == regs.prefetch020addr) {
+		uae_u16 v = regs.prefetch020[0];
+		regs.prefetch020[0] = regs.prefetch020[1];
+		regs.prefetch020[1] = regs.prefetch020[2];
+		regs.prefetch020[2] = x_get_word (pc + 6);
+		regs.prefetch020addr += 2;
+		return v;
+	} else if (pc == regs.prefetch020addr + 2) {
+		uae_u16 v = regs.prefetch020[1];
+		regs.prefetch020[0] = regs.prefetch020[2];
+		regs.prefetch020[1] = x_get_word (pc + 4);
+		regs.prefetch020[2] = x_get_word (pc + 6);
+		regs.prefetch020addr = pc + 2;
+		return v;
+	} else if (pc == regs.prefetch020addr + 4) {
+		uae_u16 v = regs.prefetch020[2];
+		regs.prefetch020[0] = x_get_word (pc + 2);
+		regs.prefetch020[1] = x_get_word (pc + 4);
+		regs.prefetch020[2] = x_get_word (pc + 6);
+		regs.prefetch020addr = pc + 2;
+		return v;
+	} else {
+		regs.prefetch020addr = pc + 2;
+		regs.prefetch020[0] = x_get_word (pc + 2);
+		regs.prefetch020[1] = x_get_word (pc + 4);
+		regs.prefetch020[2] = x_get_word (pc + 6);
+		return x_get_word (pc);
+	}
+}
+#endif
+
+#ifdef JIT  /* Completely different run_2 replacement */
+
+void do_nothing (void)
+{
+	/* What did you expect this to do? */
+	do_cycles (0);
+	/* I bet you didn't expect *that* ;-) */
+}
+
+void exec_nostats (void)
+{
+	struct regstruct *r = ®s;
+
+	for (;;)
+	{
+		if (currprefs.cpu_compatible) {
+			r->opcode = get_word_020_prefetchf(m68k_getpc());
+		} else {
+			r->opcode = x_get_iword(0);
+		}
+		cpu_cycles = (*cpufunctbl[r->opcode])(r->opcode);
+		cpu_cycles = adjust_cycles (cpu_cycles);
+		do_cycles (cpu_cycles);
+
+#ifdef WITH_PPC
+		if (ppc_state)
+			ppc_interrupt(intlev());
+#endif
+#ifdef WINUAE_FOR_HATARI
+		if (end_block(r->opcode) || r->spcflags)
+#else
+
+		if (end_block(r->opcode) || r->spcflags || uae_int_requested || uaenet_int_requested)
+#endif
+			return; /* We will deal with the spcflags in the caller */
+	}
+}
+
+void execute_normal (void)
+{
+	struct regstruct *r = ®s;
+	int blocklen;
+	cpu_history pc_hist[MAXRUN];
+	int total_cycles;
+
+	if (check_for_cache_miss ())
+		return;
+
+	total_cycles = 0;
+	blocklen = 0;
+	start_pc_p = r->pc_oldp;
+	start_pc = r->pc;
+	for (;;) {
+		/* Take note: This is the do-it-normal loop */
+		regs.instruction_pc = m68k_getpc ();
+		if (currprefs.cpu_compatible) {
+			r->opcode = get_word_020_prefetchf (regs.instruction_pc);
+		} else {
+			r->opcode = x_get_iword(0);
+		}
+
+		special_mem = DISTRUST_CONSISTENT_MEM;
+		pc_hist[blocklen].location = (uae_u16*)r->pc_p;
+
+		cpu_cycles = (*cpufunctbl[r->opcode])(r->opcode);
+		cpu_cycles = adjust_cycles (cpu_cycles);
+		do_cycles (cpu_cycles);
+		total_cycles += cpu_cycles;
+		pc_hist[blocklen].specmem = special_mem;
+		blocklen++;
+#ifdef WINUAE_FOR_HATARI
+		if (end_block (r->opcode) || blocklen >= MAXRUN || r->spcflags) {
+#else
+		if (end_block (r->opcode) || blocklen >= MAXRUN || r->spcflags || uae_int_requested || uaenet_int_requested) {
+#endif
+			compile_block (pc_hist, blocklen, total_cycles);
+			return; /* We will deal with the spcflags in the caller */
+		}
+		/* No need to check regs.spcflags, because if they were set,
+		we'd have ended up inside that "if" */
+
+#ifdef WITH_PPC
+		if (ppc_state)
+			ppc_interrupt(intlev());
+#endif
+	}
+}
+
+typedef void compiled_handler (void);
+
+static void m68k_run_jit (void)
+{
+printf ( "run_jit\n" );
+	for (;;) {
+#ifdef WINUAE_FOR_HATARI
+		//m68k_dumpstate_file(stderr, NULL);
+		if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
+		{
+			int FrameCycles, HblCounterVideo, LineCycles;
+			Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+			LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
+			m68k_disasm_file(stderr, m68k_getpc (), NULL, 1);
+		}
+#endif
+
+		((compiled_handler*)(pushall_call_handler))();
+		/* Whenever we return from that, we should check spcflags */
+#ifndef WINUAE_FOR_HATARI
+		check_uae_int_request();
+#endif
+		if (regs.spcflags) {
+			if (do_specialties (0)) {
+				return;
+			}
+		}
+	}
+}
+#endif /* JIT */
+
+#ifndef CPUEMU_0
+
+static void m68k_run_2 (void)
+{
+}
+
+#else
+
+static void opcodedebug (uae_u32 pc, uae_u16 opcode, bool full)
+{
+	struct mnemolookup *lookup;
+	struct instr *dp;
+	uae_u32 addr;
+	int fault;
+
+	if (cpufunctbl[opcode] == op_illg_1)
+		opcode = 0x4AFC;
+	dp = table68k + opcode;
+	for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
+		;
+	fault = 0;
+	TRY(prb) {
+		addr = mmu_translate (pc, (regs.mmu_ssw & 4) ? 1 : 0, 0, 0);
+	} CATCH (prb) {
+		fault = 1;
+	} ENDTRY
+	if (!fault) {
+		TCHAR buf[100];
+		if (full)
+			write_log (_T("mmufixup=%d %04x %04x\n"), mmufixup[0].reg, regs.wb3_status, regs.mmu_ssw);
+		m68k_disasm_2 (buf, sizeof buf / sizeof (TCHAR), addr, NULL, 1, NULL, NULL, 0);
+		write_log (_T("%s\n"), buf);
+		if (full)
+			m68k_dumpstate (NULL);
+	}
+}
+
+void cpu_halt (int id)
+{
+#ifndef WINUAE_FOR_HATARI
+	// id < 0: m68k halted, PPC active.
+	// id > 0: emulation halted.
+	if (!regs.halted) {
+		write_log (_T("CPU halted: reason = %d PC=%08x\n"), id, M68K_GETPC);
+		regs.halted = id;
+		gui_data.cpu_halted = id;
+		gui_led(LED_CPU, 0, -1);
+		if (id >= 0) {
+			regs.intmask = 7;
+			MakeSR ();
+			audio_deactivate ();
+		}
+		set_special(SPCFLAG_CHECK);
+	}
+
+#else
+	Dialog_HaltDlg();
+#endif
+}
+
+#ifdef CPUEMU_33
+/* [NP] TODO : use 68060 in Hatari ? with DSP ? */
+/* MMU 68060  */
+static void m68k_run_mmu060 (void)
+{
+	struct flag_struct f;
+	int halt = 0;
+printf ( "run_mmu060\n" );
+
+	while (!halt) {
+		TRY (prb) {
+			for (;;) {
+				f.cznv = regflags.cznv;
+				f.x = regflags.x;
+				regs.instruction_pc = m68k_getpc ();
+
+				do_cycles (cpu_cycles);
+
+				mmu_opcode = -1;
+				mmu060_state = 0;
+				mmu_opcode = regs.opcode = x_prefetch (0);
+				mmu060_state = 1;
+
+				count_instr (regs.opcode);
+				cpu_cycles = (*cpufunctbl[regs.opcode])(regs.opcode);
+
+				cpu_cycles = adjust_cycles (cpu_cycles);
+
+				if (regs.spcflags) {
+					if (do_specialties (cpu_cycles))
+						return;
+				}
+			}
+		} CATCH (prb) {
+
+			m68k_setpci (regs.instruction_pc);
+			regflags.cznv = f.cznv;
+			regflags.x = f.x;
+
+			if (mmufixup[0].reg >= 0) {
+				m68k_areg (regs, mmufixup[0].reg) = mmufixup[0].value;
+				mmufixup[0].reg = -1;
+			}
+			if (mmufixup[1].reg >= 0) {
+				m68k_areg (regs, mmufixup[1].reg) = mmufixup[1].value;
+				mmufixup[1].reg = -1;
+			}
+
+			TRY (prb2) {
+				Exception (prb);
+			} CATCH (prb2) {
+				halt = 1;
+			} ENDTRY
+		} ENDTRY
+	}
+	cpu_halt(halt);
+}
+
+#endif
+
+#ifdef CPUEMU_31
+
+/* Aranym MMU 68040  */
+static void m68k_run_mmu040 (void)
+{
+	struct flag_struct f;
+	int halt = 0;
+printf ( "run_mmu040\n" );
+
+	while (!halt) {
+		TRY (prb) {
+			for (;;) {
+#ifdef WINUAE_FOR_HATARI
+				//m68k_dumpstate_file(stderr, NULL);
+				if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
+				{
+					int FrameCycles, HblCounterVideo, LineCycles;
+					Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+					LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
+					m68k_disasm_file(stderr, m68k_getpc (), NULL, 1);
+				}
+#endif
+				f.cznv = regflags.cznv;
+				f.x = regflags.x;
+				mmu_restart = true;
+				regs.instruction_pc = m68k_getpc ();
+
+				do_cycles (cpu_cycles);
+
+				mmu_opcode = -1;
+				mmu_opcode = regs.opcode = x_prefetch (0);
+				count_instr (regs.opcode);
+				cpu_cycles = (*cpufunctbl[regs.opcode])(regs.opcode);
+				cpu_cycles = adjust_cycles (cpu_cycles);
+
+#ifdef WINUAE_FOR_HATARI
+				M68000_AddCycles(cpu_cycles * 2 / CYCLE_UNIT);
+
+				if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
+					/* Add some extra cycles to simulate a wait state */
+					unset_special(SPCFLAG_EXTRA_CYCLES);
+					M68000_AddCycles(nWaitStateCycles);
+					nWaitStateCycles = 0;
+				}
+
+				/* We can have several interrupts at the same time before the next CPU instruction */
+				/* We must check for pending interrupt and call do_specialties_interrupt() only */
+				/* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
+				/* and prevent exiting the STOP state when calling do_specialties() after. */
+				/* For performance, we first test PendingInterruptCount, then regs.spcflags */
+				while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
+					CALL_VAR(PendingInterruptFunction);		/* call the interrupt handler */
+				if ( MFP_UpdateNeeded == true )
+					MFP_UpdateIRQ ( 0 );
+#endif
+
+				if (regs.spcflags) {
+					if (do_specialties (cpu_cycles))
+						return;
+				}
+
+#ifdef WINUAE_FOR_HATARI
+				/* Run DSP 56k code if necessary */
+				if (bDspEnabled) {
+					DSP_Run(2 * cpu_cycles * 2 / CYCLE_UNIT);
+				}
+#endif
+			}
+		} CATCH (prb) {
+
+			if (mmu_restart) {
+				/* restore state if instruction restart */
+				regflags.cznv = f.cznv;
+				regflags.x = f.x;
+				m68k_setpci (regs.instruction_pc);
+			}
+
+			if (mmufixup[0].reg >= 0) {
+				m68k_areg (regs, mmufixup[0].reg) = mmufixup[0].value;
+				mmufixup[0].reg = -1;
+			}
+
+			TRY (prb2) {
+				Exception (prb);
+			} CATCH (prb2) {
+				halt = 1;
+			} ENDTRY
+		} ENDTRY
+	}
+	cpu_halt(halt);
+}
+
+#endif
+
+#ifdef CPUEMU_32
+
+// Previous MMU 68030
+static void m68k_run_mmu030 (void)
+{
+	struct flag_struct f;
+	int halt = 0;
+printf ( "run_mmu030\n" );
+
+	mmu030_opcode_stageb = -1;
+	mmu030_fake_prefetch = -1;
+	while(!halt) {
+		TRY (prb) {
+			for (;;) {
+				int cnt;
+insretry:
+#ifdef WINUAE_FOR_HATARI
+				//m68k_dumpstate_file(stderr, NULL);
+				if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
+				{
+					int FrameCycles, HblCounterVideo, LineCycles;
+					Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+					LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
+					m68k_disasm_file(stderr, m68k_getpc (), NULL, 1);
+				}
+#endif
+				regs.instruction_pc = m68k_getpc ();
+				f.cznv = regflags.cznv;
+				f.x = regflags.x;
+
+				mmu030_state[0] = mmu030_state[1] = mmu030_state[2] = 0;
+				mmu030_opcode = -1;
+				if (mmu030_fake_prefetch >= 0) {
+					regs.opcode = mmu030_fake_prefetch;
+					// use fake prefetch opcode only if mapping changed
+					uaecptr new_addr = mmu030_translate(regs.instruction_pc, regs.s != 0, false, false);
+					if (mmu030_fake_prefetch_addr != new_addr) {
+						regs.opcode = mmu030_fake_prefetch;
+						write_log(_T("MMU030 fake prefetch remap: %04x, %08x -> %08x\n"), mmu030_fake_prefetch, mmu030_fake_prefetch_addr, new_addr);
+					} else {
+						if (mmu030_opcode_stageb < 0) {
+							regs.opcode = x_prefetch (0);
+						} else {
+							regs.opcode = mmu030_opcode_stageb;
+							mmu030_opcode_stageb = -1;
+						}
+					}
+					mmu030_fake_prefetch = -1;
+				} else if (mmu030_opcode_stageb < 0) {
+					regs.opcode = x_prefetch (0);
+				} else {
+					regs.opcode = mmu030_opcode_stageb;
+					mmu030_opcode_stageb = -1;
+				}
+
+				mmu030_opcode = regs.opcode;
+				mmu030_ad[0].done = false;
+
+				cnt = 50;
+				for (;;) {
+					regs.opcode = mmu030_opcode;
+					mmu030_idx = 0;
+					count_instr (regs.opcode);
+					do_cycles (cpu_cycles);
+					mmu030_retry = false;
+
+					cpu_cycles = (*cpufunctbl[regs.opcode])(regs.opcode);
+					cnt--; // so that we don't get in infinite loop if things go horribly wrong
+					if (!mmu030_retry)
+						break;
+					if (cnt < 0) {
+						cpu_halt (9);
+						break;
+					}
+					if (mmu030_retry && mmu030_opcode == -1)
+						goto insretry; // urgh
+				}
+
+				mmu030_opcode = -1;
+
+				cpu_cycles = adjust_cycles (cpu_cycles);
+
+#ifdef WINUAE_FOR_HATARI
+				M68000_AddCycles(cpu_cycles * 2 / CYCLE_UNIT);
+
+				if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
+					/* Add some extra cycles to simulate a wait state */
+					unset_special(SPCFLAG_EXTRA_CYCLES);
+					M68000_AddCycles(nWaitStateCycles);
+					nWaitStateCycles = 0;
+				}
+
+				/* We can have several interrupts at the same time before the next CPU instruction */
+				/* We must check for pending interrupt and call do_specialties_interrupt() only */
+				/* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
+				/* and prevent exiting the STOP state when calling do_specialties() after. */
+				/* For performance, we first test PendingInterruptCount, then regs.spcflags */
+				while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
+					CALL_VAR(PendingInterruptFunction);		/* call the interrupt handler */
+				if ( MFP_UpdateNeeded == true )
+					MFP_UpdateIRQ ( 0 );
+#endif
+				if (regs.spcflags) {
+					if (do_specialties (cpu_cycles))
+						return;
+				}
+
+#ifdef WINUAE_FOR_HATARI
+				/* Run DSP 56k code if necessary */
+				if (bDspEnabled) {
+					DSP_Run(2 * cpu_cycles * 2 / CYCLE_UNIT);
+				}
+#endif
+			}
+		} CATCH (prb) {
+
+			regflags.cznv = f.cznv;
+			regflags.x = f.x;
+
+			m68k_setpci (regs.instruction_pc);
+
+			if (mmufixup[0].reg >= 0) {
+				m68k_areg (regs, mmufixup[0].reg) = mmufixup[0].value;
+				mmufixup[0].reg = -1;
+			}
+			if (mmufixup[1].reg >= 0) {
+				m68k_areg (regs, mmufixup[1].reg) = mmufixup[1].value;
+				mmufixup[1].reg = -1;
+			}
+
+			TRY (prb2) {
+				Exception (prb);
+			} CATCH (prb2) {
+				halt = 1;
+			} ENDTRY
+		} ENDTRY
+	}
+	cpu_halt (halt);
+}
+
+#endif
+
+
+/* "cycle exact" 68040/060 */
+
+static void m68k_run_3ce (void)
+{
+	struct regstruct *r = ®s;
+	bool exit = false;
+printf ( "run_3ce\n" );
+
+	while (!exit) {
+		TRY(prb) {
+			while (!exit) {
+#ifdef WINUAE_FOR_HATARI
+				//m68k_dumpstate_file(stderr, NULL);
+				if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
+				{
+					int FrameCycles, HblCounterVideo, LineCycles;
+					Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+					LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
+					m68k_disasm_file(stderr, m68k_getpc (), NULL, 1);
+				}
+#endif
+				r->instruction_pc = m68k_getpc();
+				r->opcode = get_iword_cache_040(0);
+				// "prefetch"
+				if (regs.cacr & 0x8000)
+					fill_icache040(r->instruction_pc + 16);
+
+				(*cpufunctbl[r->opcode])(r->opcode);
+
+#ifdef WINUAE_FOR_HATARI
+//fprintf ( stderr, "cyc_3ce %d\n" , currcycle );
+				M68000_AddCycles(currcycle * 2 / CYCLE_UNIT);
+
+				if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
+					/* Add some extra cycles to simulate a wait state */
+					unset_special(SPCFLAG_EXTRA_CYCLES);
+					M68000_AddCycles(nWaitStateCycles);
+					nWaitStateCycles = 0;
+				}
+
+				/* We can have several interrupts at the same time before the next CPU instruction */
+				/* We must check for pending interrupt and call do_specialties_interrupt() only */
+				/* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
+				/* and prevent exiting the STOP state when calling do_specialties() after. */
+				/* For performance, we first test PendingInterruptCount, then regs.spcflags */
+				while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
+					CALL_VAR(PendingInterruptFunction);		/* call the interrupt handler */
+				if ( MFP_UpdateNeeded == true )
+					MFP_UpdateIRQ ( 0 );
+#endif
+				if (r->spcflags) {
+					if (do_specialties (0))
+						exit = true;
+				}
+
+#ifdef WINUAE_FOR_HATARI
+				/* Run DSP 56k code if necessary */
+				if (bDspEnabled) {
+					DSP_Run(2 * currcycle * 2 / CYCLE_UNIT);
+				}
+#endif
+			}
+		} CATCH(prb) {
+			bus_error();
+			if (r->spcflags) {
+				if (do_specialties(0))
+					exit = true;
+			}
+		} ENDTRY
+	}
+}
+
+/* "prefetch" 68040/060 */
+
+static void m68k_run_3p(void)
+{
+	struct regstruct *r = ®s;
+	bool exit = false;
+	int cycles;
+printf ( "run_3p\n" );
+
+	while (!exit)  {
+		TRY(prb) {
+			while (!exit) {
+#ifdef WINUAE_FOR_HATARI
+				//m68k_dumpstate_file(stderr, NULL);
+				if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
+				{
+					int FrameCycles, HblCounterVideo, LineCycles;
+					Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+					LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
+					m68k_disasm_file(stderr, m68k_getpc (), NULL, 1);
+				}
+#endif
+				r->instruction_pc = m68k_getpc();
+				r->opcode = get_iword_cache_040(0);
+				// "prefetch"
+				if (regs.cacr & 0x8000)
+					fill_icache040(r->instruction_pc + 16);
+
+				(*cpufunctbl[r->opcode])(r->opcode);
+
+				cpu_cycles = 1 * CYCLE_UNIT;
+				cycles = adjust_cycles(cpu_cycles);
+				do_cycles(cycles);
+#ifdef WINUAE_FOR_HATARI
+				M68000_AddCycles(cycles * 2 / CYCLE_UNIT);
+
+				if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
+					/* Add some extra cycles to simulate a wait state */
+					unset_special(SPCFLAG_EXTRA_CYCLES);
+					M68000_AddCycles(nWaitStateCycles);
+					nWaitStateCycles = 0;
+				}
+
+				/* We can have several interrupts at the same time before the next CPU instruction */
+				/* We must check for pending interrupt and call do_specialties_interrupt() only */
+				/* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
+				/* and prevent exiting the STOP state when calling do_specialties() after. */
+				/* For performance, we first test PendingInterruptCount, then regs.spcflags */
+				while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
+					CALL_VAR(PendingInterruptFunction);		/* call the interrupt handler */
+				if ( MFP_UpdateNeeded == true )
+					MFP_UpdateIRQ ( 0 );
+#endif
+
+				if (r->spcflags) {
+					if (do_specialties(0))
+						exit = true;
+				}
+
+#ifdef WINUAE_FOR_HATARI
+				/* Run DSP 56k code if necessary */
+				if (bDspEnabled) {
+					DSP_Run(2 * cycles * 2 / CYCLE_UNIT);
+				}
+#endif
+			}
+		} CATCH(prb) {
+			bus_error();
+			if (r->spcflags) {
+				if (do_specialties(0))
+					exit = true;
+			}
+		} ENDTRY
+	}
+}
+
+/* "cycle exact" 68020/030  */
+
+STATIC_INLINE struct cache030 *getcache030 (struct cache030 *cp, uaecptr addr, uae_u32 *tagp, int *lwsp);
+static void m68k_run_2ce (void)
+{
+	struct regstruct *r = ®s;
+	bool exit = false;
+	bool first = true;
+printf ( "run_2ce\n" );
+
+	while (!exit) {
+		TRY(prb) {
+			if (first) {
+				if (cpu_tracer < 0) {
+					memcpy (&r->regs, &cputrace.regs, 16 * sizeof (uae_u32));
+					r->ir = cputrace.ir;
+					r->irc = cputrace.irc;
+					r->sr = cputrace.sr;
+					r->usp = cputrace.usp;
+					r->isp = cputrace.isp;
+					r->intmask = cputrace.intmask;
+					r->stopped = cputrace.stopped;
+
+					r->msp = cputrace.msp;
+					r->vbr = cputrace.vbr;
+					r->caar = cputrace.caar;
+					r->cacr = cputrace.cacr;
+					r->cacheholdingdata020 = cputrace.cacheholdingdata020;
+					r->cacheholdingaddr020 = cputrace.cacheholdingaddr020;
+					r->prefetch020addr = cputrace.prefetch020addr;
+					memcpy (&r->prefetch020, &cputrace.prefetch020, CPU_PIPELINE_MAX * sizeof (uae_u32));
+					memcpy (&caches020, &cputrace.caches020, sizeof caches020);
+
+					m68k_setpc (cputrace.pc);
+					if (!r->stopped) {
+						if (cputrace.state > 1)
+							Exception (cputrace.state);
+						else if (cputrace.state == 1)
+							(*cpufunctbl[cputrace.opcode])(cputrace.opcode);
+					}
+					if (regs.stopped)
+						set_special (SPCFLAG_STOP);
+					set_cpu_tracer (false);
+					goto cont;
+				}
+				set_cpu_tracer (false);
+				first = false;
+			}
+
+			while (!exit) {
+				static int prevopcode;
+#ifdef WINUAE_FOR_HATARI
+				//m68k_dumpstate_file(stderr, NULL);
+				if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
+				{
+					int FrameCycles, HblCounterVideo, LineCycles;
+					Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+					LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
+					m68k_disasm_file(stderr, m68k_getpc (), NULL, 1);
+#if 0
+// logs to debug data cache issues
+struct cache030 *c1 ,*c2;
+        int lws1, lws2;
+        uae_u32 tag1, tag2;
+c1 = getcache030 (dcaches030, (uaecptr)0x27ece, &tag1, &lws1);
+c2 = getcache030 (dcaches030, (uaecptr)0x7f8192+4, &tag2, &lws2);
+fprintf ( stderr , "cache valid %d tag1 %x lws1 %x ctag %x data %x mem=%x\n" , c1->valid[lws1] , tag1 , lws1 , c1->tag , c1->data[lws1] , get_long(0x27ece) );
+//fprintf ( stderr , "cache valid %d tag2 %x lws2 %x ctag %x data %x mem=%x\n" , c2->valid[lws2] , tag2 , lws2 , c2->tag , c2->data[lws2] , get_long(0x7f8192+4) );
+#endif
+				}
+
+				currcycle = 0;
+#endif
+				r->instruction_pc = m68k_getpc ();
+
+				if (regs.irc == 0xfffb) {
+					gui_message (_T("OPCODE %04X HAS FAULTY PREFETCH! PC=%08X"), prevopcode, r->instruction_pc);
+				}
+
+				//write_log (_T("%x %04x\n"), r->instruction_pc, regs.irc);
+
+				r->opcode = regs.irc;
+				prevopcode = r->opcode;
+				regs.irc = 0xfffb;
+
+				//write_log (_T("%08x %04x\n"), r->instruction_pc, opcode);
+
+#ifndef WINUAE_FOR_HATARI
+#if DEBUG_CD32CDTVIO
+				out_cd32io (r->instruction_pc);
+#endif
+#endif
+
+				if (cpu_tracer) {
+
+#if CPUTRACE_DEBUG
+					validate_trace ();
+#endif
+					memcpy (&cputrace.regs, &r->regs, 16 * sizeof (uae_u32));
+					cputrace.opcode = r->opcode;
+					cputrace.ir = r->ir;
+					cputrace.irc = r->irc;
+					cputrace.sr = r->sr;
+					cputrace.usp = r->usp;
+					cputrace.isp = r->isp;
+					cputrace.intmask = r->intmask;
+					cputrace.stopped = r->stopped;
+					cputrace.state = 1;
+					cputrace.pc = m68k_getpc ();
+
+					cputrace.msp = r->msp;
+					cputrace.vbr = r->vbr;
+					cputrace.caar = r->caar;
+					cputrace.cacr = r->cacr;
+					cputrace.cacheholdingdata020 = r->cacheholdingdata020;
+					cputrace.cacheholdingaddr020 = r->cacheholdingaddr020;
+					cputrace.prefetch020addr = r->prefetch020addr;
+					memcpy (&cputrace.prefetch020, &r->prefetch020, CPU_PIPELINE_MAX * sizeof (uae_u32));
+					memcpy (&cputrace.caches020, &caches020, sizeof caches020);
+
+					cputrace.memoryoffset = 0;
+					cputrace.cyclecounter = cputrace.cyclecounter_pre = cputrace.cyclecounter_post = 0;
+					cputrace.readcounter = cputrace.writecounter = 0;
+				}
+
+#ifndef WINUAE_FOR_HATARI
+				if (inputrecord_debug & 4) {
+					if (input_record > 0)
+						inprec_recorddebug_cpu (1);
+					else if (input_play > 0)
+						inprec_playdebug_cpu (1);
+				}
+#endif
+
+				(*cpufunctbl[r->opcode])(r->opcode);
+		
+				wait_memory_cycles();
+
+#ifdef WINUAE_FOR_HATARI
+//fprintf ( stderr, "cyc_2ce %d\n" , currcycle );
+				M68000_AddCycles(currcycle * 2 / CYCLE_UNIT);
+
+				if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
+					/* Add some extra cycles to simulate a wait state */
+					unset_special(SPCFLAG_EXTRA_CYCLES);
+					M68000_AddCycles(nWaitStateCycles);
+					nWaitStateCycles = 0;
+				}
+
+				/* We can have several interrupts at the same time before the next CPU instruction */
+				/* We must check for pending interrupt and call do_specialties_interrupt() only */
+				/* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
+				/* and prevent exiting the STOP state when calling do_specialties() after. */
+				/* For performance, we first test PendingInterruptCount, then regs.spcflags */
+				while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
+					CALL_VAR(PendingInterruptFunction);		/* call the interrupt handler */
+				if ( MFP_UpdateNeeded == true )
+					MFP_UpdateIRQ ( 0 );
+#endif
+
+cont:
+				if (r->spcflags || time_for_interrupt ()) {
+					if (do_specialties (0))
+						exit = true;
+				}
+
+#ifdef WINUAE_FOR_HATARI
+				/* Run DSP 56k code if necessary */
+				if (bDspEnabled) {
+//fprintf ( stderr, "dsp cyc_2ce %d\n" , currcycle );
+					DSP_Run(2 * currcycle * 2 / CYCLE_UNIT);
+				}
+#endif
+
+				regs.ipl = regs.ipl_pin;
+
+			}
+		} CATCH(prb) {
+			bus_error();
+			if (r->spcflags || time_for_interrupt()) {
+				if (do_specialties(0)) {
+					exit = true;
+					regs.ipl = regs.ipl_pin;
+				}
+			}
+		} ENDTRY
+	}
+}
+
+#ifdef CPUEMU_20
+
+// full prefetch 020 (more compatible)
+static void m68k_run_2p (void)
+{
+	struct regstruct *r = ®s;
+	bool exit = false;
+printf ( "run_2p\n" );
+
+	while (!exit) {
+		TRY(prb) {
+			while (!exit) {
+#ifdef WINUAE_FOR_HATARI
+				//m68k_dumpstate_file(stderr, NULL);
+				if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
+				{
+					int FrameCycles, HblCounterVideo, LineCycles;
+					Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+					LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
+					m68k_disasm_file(stderr, m68k_getpc (), NULL, 1);
+				}
+#endif
+				r->instruction_pc = m68k_getpc ();
+
+#ifndef WINUAE_FOR_HATARI
+#if DEBUG_CD32CDTVIO
+				out_cd32io (m68k_getpc ());
+#endif
+#endif
+
+				x_do_cycles (cpu_cycles);
+
+				r->opcode = regs.irc;
+				count_instr (r->opcode);
+
+				cpu_cycles = (*cpufunctbl[r->opcode])(r->opcode);
+				cpu_cycles = adjust_cycles (cpu_cycles);
+#ifdef WINUAE_FOR_HATARI
+				M68000_AddCycles(cpu_cycles * 2 / CYCLE_UNIT);
+
+				if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
+					/* Add some extra cycles to simulate a wait state */
+					unset_special(SPCFLAG_EXTRA_CYCLES);
+					M68000_AddCycles(nWaitStateCycles);
+					nWaitStateCycles = 0;
+				}
+
+				/* We can have several interrupts at the same time before the next CPU instruction */
+				/* We must check for pending interrupt and call do_specialties_interrupt() only */
+				/* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
+				/* and prevent exiting the STOP state when calling do_specialties() after. */
+				/* For performance, we first test PendingInterruptCount, then regs.spcflags */
+				while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
+					CALL_VAR(PendingInterruptFunction);		/* call the interrupt handler */
+				if ( MFP_UpdateNeeded == true )
+					MFP_UpdateIRQ ( 0 );
+#endif
+
+				if (r->spcflags) {
+					if (do_specialties (cpu_cycles))
+						exit = true;
+				}
+
+#ifdef WINUAE_FOR_HATARI
+				/* Run DSP 56k code if necessary */
+				if (bDspEnabled) {
+					DSP_Run(2 * cpu_cycles * 2 / CYCLE_UNIT);
+				}
+#endif
+
+				ipl_fetch ();
+			}
+		} CATCH(prb) {
+			bus_error();
+			if (r->spcflags) {
+				if (do_specialties(cpu_cycles))
+					exit = true;;
+			}
+			ipl_fetch();
+		} ENDTRY
+	}
+}
+
+#endif
+
+//static int used[65536];
+
+/* Same thing, but don't use prefetch to get opcode.  */
+static void m68k_run_2 (void)
+{
+//	static int done;
+	struct regstruct *r = ®s;
+	bool exit = false;
+printf ( "run_2\n" );
+
+	while (!exit) {
+		TRY(prb) {
+			while (!exit) {
+#ifdef WINUAE_FOR_HATARI
+				//m68k_dumpstate_file(stderr, NULL);
+				if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
+				{
+					int FrameCycles, HblCounterVideo, LineCycles;
+					Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+					LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
+					m68k_disasm_file(stderr, m68k_getpc (), NULL, 1);
+				}
+#endif
+				r->instruction_pc = m68k_getpc ();
+
+				r->opcode = x_get_iword(0);
+				count_instr (r->opcode);
+
+				do_cycles (cpu_cycles);
+
+				cpu_cycles = (*cpufunctbl[r->opcode])(r->opcode);
+				cpu_cycles = adjust_cycles (cpu_cycles);
+#ifdef WINUAE_FOR_HATARI
+//fprintf ( stderr , "cyc_2 %d\n" , cpu_cycles );
+				M68000_AddCyclesWithPairing(cpu_cycles * 2 / CYCLE_UNIT);
+
+				if (regs.spcflags & SPCFLAG_EXTRA_CYCLES) {
+					/* Add some extra cycles to simulate a wait state */
+					unset_special(SPCFLAG_EXTRA_CYCLES);
+					M68000_AddCycles(nWaitStateCycles);
+					nWaitStateCycles = 0;
+				}
+
+				/* We can have several interrupts at the same time before the next CPU instruction */
+				/* We must check for pending interrupt and call do_specialties_interrupt() only */
+				/* if the cpu is not in the STOP state. Else, the int could be acknowledged now */
+				/* and prevent exiting the STOP state when calling do_specialties() after. */
+				/* For performance, we first test PendingInterruptCount, then regs.spcflags */
+				while ( ( PendingInterruptCount <= 0 ) && ( PendingInterruptFunction ) && ( ( regs.spcflags & SPCFLAG_STOP ) == 0 ) )
+					CALL_VAR(PendingInterruptFunction);		/* call the interrupt handler */
+				if ( MFP_UpdateNeeded == true )
+					MFP_UpdateIRQ ( 0 );
+#endif
+
+				if (r->spcflags) {
+					if (do_specialties (cpu_cycles))
+						exit = true;
+				}
+
+#ifdef WINUAE_FOR_HATARI
+				/* Run DSP 56k code if necessary */
+				if (bDspEnabled) {
+					DSP_Run(2 * cpu_cycles * 2 / CYCLE_UNIT);
+				}
+#endif
+			}
+		} CATCH(prb) {
+			bus_error();
+			if (r->spcflags) {
+				if (do_specialties(cpu_cycles))
+					exit = true;
+			}
+		} ENDTRY
+	}
+}
+
+/* fake MMU 68k  */
+static void m68k_run_mmu (void)
+{
+printf ( "run_mmu\n" );
+	for (;;) {
+#ifdef WINUAE_FOR_HATARI
+		//m68k_dumpstate_file(stderr, NULL);
+		if (LOG_TRACE_LEVEL(TRACE_CPU_DISASM))
+		{
+			int FrameCycles, HblCounterVideo, LineCycles;
+			Video_GetPosition ( &FrameCycles , &HblCounterVideo , &LineCycles );
+			LOG_TRACE_PRINT ( "cpu video_cyc=%6d %3d@%3d : " , FrameCycles, LineCycles, HblCounterVideo );
+			m68k_disasm_file(stderr, m68k_getpc (), NULL, 1);
+		}
+#endif
+		regs.opcode = get_iiword (0);
+		do_cycles (cpu_cycles);
+		mmu_backup_regs = regs;
+		cpu_cycles = (*cpufunctbl[regs.opcode])(regs.opcode);
+		cpu_cycles = adjust_cycles (cpu_cycles);
+		if (mmu_triggered)
+			mmu_do_hit ();
+		if (regs.spcflags) {
+			if (do_specialties (cpu_cycles))
+				return;
+		}
+	}
+}
+
+#endif /* CPUEMU_0 */
+
+int in_m68k_go = 0;
+
+static void exception2_handle (uaecptr addr, uaecptr fault)
+{
+	last_addr_for_exception_3 = addr;
+	last_fault_for_exception_3 = fault;
+	last_writeaccess_for_exception_3 = 0;
+	last_instructionaccess_for_exception_3 = 0;
+	Exception (2);
+}
+
+static bool cpu_hardreset, cpu_keyboardreset;
+
+bool is_hardreset(void)
+{
+	return cpu_hardreset;
+}
+bool is_keyboardreset(void)
+{
+	return  cpu_keyboardreset;
+}
+
+void m68k_go (int may_quit)
+{
+#ifndef WINUAE_FOR_HATARI
+	int hardboot = 1;
+	int startup = 1;
+#endif
+
+	if (in_m68k_go || !may_quit) {
+		write_log (_T("Bug! m68k_go is not reentrant.\n"));
+		abort ();
+	}
+
+	reset_frame_rate_hack ();
+	update_68k_cycles ();
+#ifndef WINUAE_FOR_HATARI
+	start_cycles = 0;
+#endif
+
+	set_cpu_tracer (false);
+
+	cpu_prefs_changed_flag = 0;
+	in_m68k_go++;
+	for (;;) {
+		void (*run_func)(void);
+
+#ifdef WINUAE_FOR_HATARI
+		/* Exit hatari ? */
+		if (bQuitProgram == true)
+			break;
+#endif
+
+		cputrace.state = -1;
+
+#ifndef WINUAE_FOR_HATARI
+		if (currprefs.inprecfile[0] && input_play) {
+			inprec_open (currprefs.inprecfile, NULL);
+			changed_prefs.inprecfile[0] = currprefs.inprecfile[0] = 0;
+			quit_program = UAE_RESET;
+		}
+		if (input_play || input_record)
+			inprec_startup ();
+
+		if (quit_program > 0) {
+			int restored = 0;
+			cpu_keyboardreset = quit_program == UAE_RESET_KEYBOARD;
+			cpu_hardreset = ((quit_program == UAE_RESET_HARD ? 1 : 0) | hardboot) != 0;
+
+			if (quit_program == UAE_QUIT)
+				break;
+
+			hsync_counter = 0;
+			vsync_counter = 0;
+			quit_program = 0;
+			hardboot = 0;
+
+#ifdef SAVESTATE
+			if (savestate_state == STATE_DORESTORE)
+				savestate_state = STATE_RESTORE;
+			if (savestate_state == STATE_RESTORE)
+				restore_state (savestate_fname);
+			else if (savestate_state == STATE_REWIND)
+				savestate_rewind ();
+#endif
+#ifndef WINUAE_FOR_HATARI
+			set_cycles (start_cycles);
+#endif
+			custom_reset (cpu_hardreset != 0, cpu_keyboardreset);
+			m68k_reset2 (cpu_hardreset != 0);
+			if (cpu_hardreset) {
+				memory_clear ();
+				write_log (_T("hardreset, memory cleared\n"));
+			}
+			cpu_hardreset = false;
+#ifdef SAVESTATE
+			/* We may have been restoring state, but we're done now.  */
+			if (isrestore ()) {
+				if (debug_dma) {
+					record_dma_reset ();
+					record_dma_reset ();
+				}
+				savestate_restore_finish ();
+				memory_map_dump ();
+				if (currprefs.mmu_model == 68030) {
+					mmu030_decode_tc (tc_030);
+				} else if (currprefs.mmu_model >= 68040) {
+					mmu_set_tc (regs.tcr);
+				}
+				startup = 1;
+				restored = 1;
+			}
+#endif
+			if (currprefs.produce_sound == 0)
+				eventtab[ev_audio].active = 0;
+			m68k_setpc_normal (regs.pc);
+			check_prefs_changed_audio ();
+
+			if (!restored || hsync_counter == 0)
+				savestate_check ();
+			if (input_record == INPREC_RECORD_START)
+				input_record = INPREC_RECORD_NORMAL;
+			statusline_clear();
+		} else {
+			if (input_record == INPREC_RECORD_START) {
+				input_record = INPREC_RECORD_NORMAL;
+				savestate_init ();
+				hsync_counter = 0;
+				vsync_counter = 0;
+				savestate_check ();
+			}
+		}
+
+		if (changed_prefs.inprecfile[0] && input_record)
+			inprec_prepare_record (savestate_fname[0] ? savestate_fname : NULL);
+#endif
+
+		set_cpu_tracer (false);
+
+#ifdef DEBUGGER
+		if (debugging)
+			debug ();
+#endif
+/* [NP] TODO : allow changing cpu on the fly ? */
+#ifndef WINUAE_FOR_HATARI
+		if (regs.spcflags & SPCFLAG_MODE_CHANGE) {
+			if (cpu_prefs_changed_flag & 1) {
+				uaecptr pc = m68k_getpc();
+				prefs_changed_cpu();
+				build_cpufunctbl();
+				m68k_setpc_normal(pc);
+				fill_prefetch();
+			}
+			if (cpu_prefs_changed_flag & 2) {
+				fixup_cpu(&changed_prefs);
+				currprefs.m68k_speed = changed_prefs.m68k_speed;
+				currprefs.m68k_speed_throttle = changed_prefs.m68k_speed_throttle;
+				update_68k_cycles();
+			}
+			cpu_prefs_changed_flag = 0;
+		}
+#else
+		/* [NP] : in Hatari, build_cpufunctbl() is called directly from check_prefs_changed_cpu2() */
+		/* so we just need to set PC here */
+		if (regs.spcflags & SPCFLAG_MODE_CHANGE) {
+			if (cpu_prefs_changed_flag & 1) {
+printf ( "cpu change %d\n" , cpu_prefs_changed_flag );
+				uaecptr pc = m68k_getpc();
+				m68k_setpc_normal(pc);
+				fill_prefetch();
+			}
+			cpu_prefs_changed_flag = 0;
+		}
+#endif
+
+		set_x_funcs();
+#ifndef WINUAE_FOR_HATARI
+		if (startup) {
+			custom_prepare ();
+			protect_roms (true);
+		}
+		startup = 0;
+		event_wait = true;
+#endif
+		unset_special(SPCFLAG_MODE_CHANGE);
+
+		if (regs.halted) {
+			cpu_halt (regs.halted);
+			if (regs.halted < 0) {
+				haltloop();
+				continue;
+			}
+		}
+
+#if 0
+		if (mmu_enabled && !currprefs.cachesize) {
+			run_func = m68k_run_mmu;
+		} else {
+#endif
+			run_func = currprefs.cpu_cycle_exact && currprefs.cpu_model <= 68010 ? m68k_run_1_ce :
+				currprefs.cpu_compatible && currprefs.cpu_model <= 68010 ? m68k_run_1 :
+#ifdef JIT
+				currprefs.cpu_model >= 68020 && currprefs.cachesize ? m68k_run_jit :
+#endif
+				currprefs.cpu_model == 68030 && currprefs.mmu_model ? m68k_run_mmu030 :
+				currprefs.cpu_model == 68040 && currprefs.mmu_model ? m68k_run_mmu040 :
+				currprefs.cpu_model == 68060 && currprefs.mmu_model ? m68k_run_mmu060 :
+
+				currprefs.cpu_model >= 68040 && currprefs.cpu_cycle_exact ? m68k_run_3ce :
+				currprefs.cpu_model >= 68020 && currprefs.cpu_cycle_exact ? m68k_run_2ce :
+
+				currprefs.cpu_model <= 68020 && currprefs.cpu_compatible ? m68k_run_2p :
+				currprefs.cpu_model == 68030 && currprefs.cpu_compatible ? m68k_run_2p :
+				currprefs.cpu_model >= 68040 && currprefs.cpu_compatible ? m68k_run_3p :
+
+				m68k_run_2;
+#if 0
+		}
+#endif
+		run_func();
+printf ( "exit m68k_run\n" );
+	}
+#ifndef WINUAE_FOR_HATARI
+	protect_roms (false);
+#endif
+	in_m68k_go--;
+}
+
+#if 0
+static void m68k_verify (uaecptr addr, uaecptr *nextpc)
+{
+	uae_u16 opcode, val;
+	struct instr *dp;
+
+	opcode = get_iword_1 (0);
+	last_op_for_exception_3 = opcode;
+	m68kpc_offset = 2;
+
+	if (cpufunctbl[opcode] == op_illg_1) {
+		opcode = 0x4AFC;
+	}
+	dp = table68k + opcode;
+
+	if (dp->suse) {
+		if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
+			Exception (3, 0);
+			return;
+		}
+	}
+	if (dp->duse) {
+		if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
+			Exception (3, 0);
+			return;
+		}
+	}
+}
+#endif
+
+static const TCHAR *ccnames[] =
+{
+	_T("T "),_T("F "),_T("HI"),_T("LS"),_T("CC"),_T("CS"),_T("NE"),_T("EQ"),
+	_T("VC"),_T("VS"),_T("PL"),_T("MI"),_T("GE"),_T("LT"),_T("GT"),_T("LE")
+};
+static const TCHAR *fpccnames[] =
+{
+	_T("F"),
+	_T("EQ"),
+	_T("OGT"),
+	_T("OGE"),
+	_T("OLT"),
+	_T("OLE"),
+	_T("OGL"),
+	_T("OR"),
+	_T("UN"),
+	_T("UEQ"),
+	_T("UGT"),
+	_T("UGE"),
+	_T("ULT"),
+	_T("ULE"),
+	_T("NE"),
+	_T("T"),
+	_T("SF"),
+	_T("SEQ"),
+	_T("GT"),
+	_T("GE"),
+	_T("LT"),
+	_T("LE"),
+	_T("GL"),
+	_T("GLE"),
+	_T("NGLE"),
+	_T("NGL"),
+	_T("NLE"),
+	_T("NLT"),
+	_T("NGE"),
+	_T("NGT"),
+	_T("SNE"),
+	_T("ST")
+};
+static const TCHAR *fpuopcodes[] =
+{
+	_T("FMOVE"),
+	_T("FINT"),
+	_T("FSINH"),
+	_T("FINTRZ"),
+	_T("FSQRT"),
+	NULL,
+	_T("FLOGNP1"),
+	NULL,
+	_T("FETOXM1"),
+	_T("FTANH"),
+	_T("FATAN"),
+	NULL,
+	_T("FASIN"),
+	_T("FATANH"),
+	_T("FSIN"),
+	_T("FTAN"),
+	_T("FETOX"),	// 0x10
+	_T("FTWOTOX"),
+	_T("FTENTOX"),
+	NULL,
+	_T("FLOGN"),
+	_T("FLOG10"),
+	_T("FLOG2"),
+	NULL,
+	_T("FABS"),
+	_T("FCOSH"),
+	_T("FNEG"),
+	NULL,
+	_T("FACOS"),
+	_T("FCOS"),
+	_T("FGETEXP"),
+	_T("FGETMAN"),
+	_T("FDIV"),		// 0x20
+	_T("FMOD"),
+	_T("FADD"),
+	_T("FMUL"),
+	_T("FSGLDIV"),
+	_T("FREM"),
+	_T("FSCALE"),
+	_T("FSGLMUL"),
+	_T("FSUB"),
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	_T("FSINCOS"),	// 0x30
+	_T("FSINCOS"),
+	_T("FSINCOS"),
+	_T("FSINCOS"),
+	_T("FSINCOS"),
+	_T("FSINCOS"),
+	_T("FSINCOS"),
+	_T("FSINCOS"),
+	_T("FCMP"),
+	NULL,
+	_T("FTST"),
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL
+};
+
+static const TCHAR *movemregs[] =
+{
+	_T("D0"),
+	_T("D1"),
+	_T("D2"),
+	_T("D3"),
+	_T("D4"),
+	_T("D5"),
+	_T("D6"),
+	_T("D7"),
+	_T("A0"),
+	_T("A1"),
+	_T("A2"),
+	_T("A3"),
+	_T("A4"),
+	_T("A5"),
+	_T("A6"),
+	_T("A7"),
+	_T("FP0"),
+	_T("FP1"),
+	_T("FP2"),
+	_T("FP3"),
+	_T("FP4"),
+	_T("FP5"),
+	_T("FP6"),
+	_T("FP7"),
+	_T("FPCR"),
+	_T("FPSR"),
+	_T("FPIAR")
+};
+
+static void addmovemreg (TCHAR *out, int *prevreg, int *lastreg, int *first, int reg, int fpmode)
+{
+	TCHAR *p = out + _tcslen (out);
+	if (*prevreg < 0) {
+		*prevreg = reg;
+		*lastreg = reg;
+		return;
+	}
+	if (reg < 0 || fpmode == 2 || (*prevreg) + 1 != reg || (reg & 8) != ((*prevreg & 8))) {
+		_stprintf (p, _T("%s%s"), (*first) ? _T("") : _T("/"), movemregs[*lastreg]);
+		p = p + _tcslen (p);
+		if ((*lastreg) + 2 == reg) {
+			_stprintf (p, _T("/%s"), movemregs[*prevreg]);
+		} else if ((*lastreg) != (*prevreg)) {
+			_stprintf (p, _T("-%s"), movemregs[*prevreg]);
+		}
+		*lastreg = reg;
+		*first = 0;
+	}
+	*prevreg = reg;
+}
+
+static void movemout (TCHAR *out, uae_u16 mask, int mode, int fpmode)
+{
+	unsigned int dmask, amask;
+	int prevreg = -1, lastreg = -1, first = 1;
+	int i;
+
+	if (mode == Apdi && !fpmode) {
+		uae_u8 dmask2;
+		uae_u8 amask2;
+		
+		amask2 = mask & 0xff;
+		dmask2 = (mask >> 8) & 0xff;
+		dmask = 0;
+		amask = 0;
+		for (i = 0; i < 8; i++) {
+			if (dmask2 & (1 << i))
+				dmask |= 1 << (7 - i);
+			if (amask2 & (1 << i))
+				amask |= 1 << (7 - i);
+		}
+	} else {
+		dmask = mask & 0xff;
+		amask = (mask >> 8) & 0xff;
+		if (fpmode == 1 && mode != Apdi) {
+			uae_u8 dmask2 = dmask;
+			dmask = 0;
+			for (i = 0; i < 8; i++) {
+				if (dmask2 & (1 << i))
+					dmask |= 1 << (7 - i);
+			}
+		}
+	}
+	if (fpmode) {
+		while (dmask) { addmovemreg(out, &prevreg, &lastreg, &first, movem_index1[dmask] + (fpmode == 2 ? 24 : 16), fpmode); dmask = movem_next[dmask]; }
+	} else {
+		while (dmask) { addmovemreg (out, &prevreg, &lastreg, &first, movem_index1[dmask], fpmode); dmask = movem_next[dmask]; }
+		while (amask) { addmovemreg (out, &prevreg, &lastreg, &first, movem_index1[amask] + 8, fpmode); amask = movem_next[amask]; }
+	}
+	addmovemreg(out, &prevreg, &lastreg, &first, -1, fpmode);
+}
+
+static const TCHAR *fpsizes[] = {
+	_T("L"),
+	_T("S"),
+	_T("X"),
+	_T("P"),
+	_T("W"),
+	_T("D"),
+	_T("B"),
+	_T("P")
+};
+static const int fpsizeconv[] = {
+	sz_long,
+	sz_single,
+	sz_extended,
+	sz_packed,
+	sz_word,
+	sz_double,
+	sz_byte,
+	sz_packed
+};
+
+static void disasm_size (TCHAR *instrname, struct instr *dp)
+{
+	if (dp->unsized) {
+		_tcscat(instrname, _T(" "));
+		return;
+	}
+	switch (dp->size)
+	{
+	case sz_byte:
+		_tcscat (instrname, _T(".B "));
+		break;
+	case sz_word:
+		_tcscat (instrname, _T(".W "));
+		break;
+	case sz_long:
+		_tcscat (instrname, _T(".L "));
+		break;
+	default:
+		_tcscat (instrname, _T(" "));
+		break;
+	}
+}
+
+void m68k_disasm_2 (TCHAR *buf, int bufsize, uaecptr pc, uaecptr *nextpc, int cnt, uae_u32 *seaddr, uae_u32 *deaddr, int safemode)
+{
+	uae_u32 seaddr2;
+	uae_u32 deaddr2;
+
+	if (buf)
+		memset (buf, 0, bufsize * sizeof (TCHAR));
+	if (!table68k)
+		return;
+	while (cnt-- > 0) {
+		TCHAR instrname[100], *ccpt;
+		int i;
+		uae_u32 opcode;
+		uae_u16 extra;
+		struct mnemolookup *lookup;
+		struct instr *dp;
+		uaecptr oldpc;
+		uaecptr m68kpc_illg = 0;
+		bool illegal = false;
+
+		seaddr2 = deaddr2 = 0;
+		oldpc = pc;
+		opcode = get_word_debug (pc);
+		extra = get_word_debug (pc + 2);
+		if (cpufunctbl[opcode] == op_illg_1 || cpufunctbl[opcode] == op_unimpl_1) {
+			m68kpc_illg = pc + 2;
+			illegal = TRUE;
+		}
+
+		dp = table68k + opcode;
+		if (dp->mnemo == i_ILLG) {
+			illegal = FALSE;
+			opcode = 0x4AFC;
+			dp = table68k + opcode;
+		}
+		for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
+			;
+
+		buf = buf_out (buf, &bufsize, _T("%08X "), pc);
+
+		pc += 2;
+		
+		if (lookup->friendlyname)
+			_tcscpy (instrname, lookup->friendlyname);
+		else
+			_tcscpy (instrname, lookup->name);
+		ccpt = _tcsstr (instrname, _T("cc"));
+		if (ccpt != 0) {
+			if ((opcode & 0xf000) == 0xf000)
+				_tcscpy (ccpt, fpccnames[extra & 0x1f]);
+			else
+				_tcsncpy (ccpt, ccnames[dp->cc], 2);
+		}
+		disasm_size (instrname, dp);
+
+		if (lookup->mnemo == i_MOVEC2 || lookup->mnemo == i_MOVE2C) {
+			uae_u16 imm = extra;
+			uae_u16 creg = imm & 0x0fff;
+			uae_u16 r = imm >> 12;
+			TCHAR regs[16];
+			const TCHAR *cname = _T("?");
+			int i;
+			for (i = 0; m2cregs[i].regname; i++) {
+				if (m2cregs[i].regno == creg)
+					break;
+			}
+			_stprintf (regs, _T("%c%d"), r >= 8 ? 'A' : 'D', r >= 8 ? r - 8 : r);
+			if (m2cregs[i].regname)
+				cname = m2cregs[i].regname;
+			if (lookup->mnemo == i_MOVE2C) {
+				_tcscat (instrname, regs);
+				_tcscat (instrname, _T(","));
+				_tcscat (instrname, cname);
+			} else {
+				_tcscat (instrname, cname);
+				_tcscat (instrname, _T(","));
+				_tcscat (instrname, regs);
+			}
+			pc += 2;
+		} else if (lookup->mnemo == i_MVMEL) {
+			uae_u16 mask = extra;
+			pc += 2;
+			pc = ShowEA (0, pc, opcode, dp->dreg, dp->dmode, dp->size, instrname, deaddr, safemode);
+			_tcscat (instrname, _T(","));
+			movemout (instrname, mask, dp->dmode, 0);
+		} else if (lookup->mnemo == i_MVMLE) {
+			uae_u16 mask = extra;
+			pc += 2;
+			movemout(instrname, mask, dp->dmode, 0);
+			_tcscat(instrname, _T(","));
+			pc = ShowEA(0, pc, opcode, dp->dreg, dp->dmode, dp->size, instrname, deaddr, safemode);
+		} else if (lookup->mnemo == i_DIVL || lookup->mnemo == i_MULL) {
+			TCHAR *p;
+			pc = ShowEA(0, pc, opcode, dp->dreg, dp->dmode, dp->size, instrname, &seaddr2, safemode);
+			extra = get_word_debug(pc);
+			pc += 2;
+			p = instrname + _tcslen(instrname);
+			if (extra & 0x0400)
+				_stprintf(p, _T(",D%d:D%d"), extra & 7, (extra >> 12) & 7);
+			else
+				_stprintf(p, _T(",D%d"), (extra >> 12) & 7);
+		} else if (lookup->mnemo == i_MOVES) {
+			TCHAR *p;
+			pc += 2;
+			if (!(extra & 0x1000)) {
+				pc = ShowEA(0, pc, opcode, dp->dreg, dp->dmode, dp->size, instrname, &seaddr2, safemode);
+				p = instrname + _tcslen(instrname);
+				_stprintf(p, _T(",%c%d"), (extra & 0x8000) ? 'A' : 'D', (extra >> 12) & 7);
+			} else {
+				p = instrname + _tcslen(instrname);
+				_stprintf(p, _T("%c%d,"), (extra & 0x8000) ? 'A' : 'D', (extra >> 12) & 7);
+				pc = ShowEA(0, pc, opcode, dp->dreg, dp->dmode, dp->size, instrname, &seaddr2, safemode);
+			}
+		} else if (lookup->mnemo == i_BFEXTS || lookup->mnemo == i_BFEXTU ||
+				   lookup->mnemo == i_BFCHG || lookup->mnemo == i_BFCLR ||
+				   lookup->mnemo == i_BFFFO || lookup->mnemo == i_BFINS ||
+				   lookup->mnemo == i_BFSET || lookup->mnemo == i_BFTST) {
+			TCHAR *p;
+			int reg = -1;
+
+			pc += 2;
+			p = instrname + _tcslen(instrname);
+			if (lookup->mnemo == i_BFEXTS || lookup->mnemo == i_BFEXTU || lookup->mnemo == i_BFFFO || lookup->mnemo == i_BFINS)
+				reg = (extra >> 12) & 7;
+			if (lookup->mnemo == i_BFINS)
+				_stprintf(p, _T("D%d,"), reg);
+			pc = ShowEA(0, pc, opcode, dp->dreg, dp->dmode, dp->size, instrname, &seaddr2, safemode);
+			_tcscat(instrname, _T(" {"));
+			p = instrname + _tcslen(instrname);
+			if (extra & 0x0800)
+				_stprintf(p, _T("D%d"), (extra >> 6) & 7);
+			else
+				_stprintf(p, _T("%d"), (extra >> 6) & 31);
+			_tcscat(instrname, _T(":"));
+			p = instrname + _tcslen(instrname);
+			if (extra & 0x0020)
+				_stprintf(p, _T("D%d"), extra & 7);
+			else
+				_stprintf(p, _T("%d"), extra  & 31);
+			_tcscat(instrname, _T("}"));
+			p = instrname + _tcslen(instrname);
+			if (lookup->mnemo == i_BFFFO || lookup->mnemo == i_BFEXTS || lookup->mnemo == i_BFEXTU)
+				_stprintf(p, _T(",D%d"), reg);
+		} else if (lookup->mnemo == i_CPUSHA || lookup->mnemo == i_CPUSHL || lookup->mnemo == i_CPUSHP ||
+			lookup->mnemo == i_CINVA || lookup->mnemo == i_CINVL || lookup->mnemo == i_CINVP) {
+			if ((opcode & 0xc0) == 0xc0)
+				_tcscat(instrname, _T("BC"));
+			else if (opcode & 0x80)
+				_tcscat(instrname, _T("IC"));
+			else if (opcode & 0x40)
+				_tcscat(instrname, _T("DC"));
+			else
+				_tcscat(instrname, _T("?"));
+			if (lookup->mnemo == i_CPUSHL || lookup->mnemo == i_CPUSHP || lookup->mnemo == i_CINVL || lookup->mnemo == i_CINVP) {
+				TCHAR *p = instrname + _tcslen(instrname);
+				_stprintf(p, _T(",(A%d)"), opcode & 7);
+			}
+		} else if (lookup->mnemo == i_FPP) {
+			TCHAR *p;
+			int ins = extra & 0x3f;
+			int size = (extra >> 10) & 7;
+
+			pc += 2;
+			if ((extra & 0xfc00) == 0x5c00) { // FMOVECR (=i_FPP with source specifier = 7)
+				fpdata fp;
+				if (fpu_get_constant(&fp, extra))
+#if USE_LONG_DOUBLE
+					_stprintf(instrname, _T("FMOVECR.X #%Le,FP%d"), fp.fp, (extra >> 7) & 7);
+#else
+					_stprintf(instrname, _T("FMOVECR.X #%e,FP%d"), fp.fp, (extra >> 7) & 7);
+#endif
+				else
+					_stprintf(instrname, _T("FMOVECR.X #?,FP%d"), (extra >> 7) & 7);
+			} else if ((extra & 0x8000) == 0x8000) { // FMOVEM
+				int dr = (extra >> 13) & 1;
+				int mode;
+				int dreg = (extra >> 4) & 7;
+				int regmask, fpmode;
+				
+				if (extra & 0x4000) {
+					mode = (extra >> 11) & 3;
+					regmask = extra & 0xff;  // FMOVEM FPx
+					fpmode = 1;
+					_tcscpy(instrname, _T("FMOVEM.X "));
+				} else {
+					mode = 0;
+					regmask = (extra >> 10) & 7;  // FMOVEM control
+					fpmode = 2;
+					_tcscpy(instrname, _T("FMOVEM.L "));
+					if (regmask == 1 || regmask == 2 || regmask == 4)
+						_tcscpy(instrname, _T("FMOVE.L "));
+				}
+				p = instrname + _tcslen(instrname);
+				if (dr) {
+					if (mode & 1)
+						_stprintf(instrname, _T("D%d"), dreg);
+					else
+						movemout(instrname, regmask, dp->dmode, fpmode);
+					_tcscat(instrname, _T(","));
+					pc = ShowEA(0, pc, opcode, dp->dreg, dp->dmode, dp->size, instrname, deaddr, safemode);
+				} else {
+					pc = ShowEA(0, pc, opcode, dp->dreg, dp->dmode, dp->size, instrname, deaddr, safemode);
+					_tcscat(instrname, _T(","));
+					p = instrname + _tcslen(instrname);
+					if (mode & 1)
+						_stprintf(p, _T("D%d"), dreg);
+					else
+						movemout(p, regmask, dp->dmode, fpmode);
+				}
+			} else {
+				if (fpuopcodes[ins])
+					_tcscpy(instrname, fpuopcodes[ins]);
+				else
+					_tcscpy(instrname, _T("F?"));
+
+				if ((extra & 0xe000) == 0x6000) { // FMOVE to memory
+					int kfactor = extra & 0x7f;
+					_tcscpy(instrname, _T("FMOVE."));
+					_tcscat(instrname, fpsizes[size]);
+					_tcscat(instrname, _T(" "));
+					p = instrname + _tcslen(instrname);
+					_stprintf(p, _T("FP%d,"), (extra >> 7) & 7);
+					pc = ShowEA(0, pc, opcode, dp->dreg, dp->dmode, fpsizeconv[size], instrname, &deaddr2, safemode);
+					p = instrname + _tcslen(instrname);
+					if (size == 7) {
+						_stprintf(p, _T(" {D%d}"), (kfactor >> 4));
+					} else if (kfactor) {
+						if (kfactor & 0x40)
+							kfactor |= ~0x3f;
+						_stprintf(p, _T(" {%d}"), kfactor);
+					}
+				} else {
+					if (extra & 0x4000) { // source is EA
+						_tcscat(instrname, _T("."));
+						_tcscat(instrname, fpsizes[size]);
+						_tcscat(instrname, _T(" "));
+						pc = ShowEA(0, pc, opcode, dp->dreg, dp->dmode, fpsizeconv[size], instrname, &seaddr2, safemode);
+					} else { // source is FPx
+						p = instrname + _tcslen(instrname);
+						_stprintf(p, _T(".X FP%d"), (extra >> 10) & 7);
+					}
+					p = instrname + _tcslen(instrname);
+					if ((extra & 0x4000) || (((extra >> 7) & 7) != ((extra >> 10) & 7)))
+						_stprintf(p, _T(",FP%d"), (extra >> 7) & 7);
+					if (ins >= 0x30 && ins < 0x38) { // FSINCOS
+						p = instrname + _tcslen(instrname);
+						_stprintf(p, _T(",FP%d"), extra & 7);
+					}
+				}
+			}
+		} else if ((opcode & 0xf000) == 0xa000) {
+			_tcscpy(instrname, _T("A-LINE"));
+		} else {
+			if (dp->suse) {
+				pc = ShowEA (0, pc, opcode, dp->sreg, dp->smode, dp->size, instrname, &seaddr2, safemode);
+			}
+			if (dp->suse && dp->duse)
+				_tcscat (instrname, _T(","));
+			if (dp->duse) {
+				pc = ShowEA (0, pc, opcode, dp->dreg, dp->dmode, dp->size, instrname, &deaddr2, safemode);
+			}
+		}
+
+		for (i = 0; i < (int)(pc - oldpc) / 2 && i < 5; i++) {
+			buf = buf_out (buf, &bufsize, _T("%04x "), get_word_debug (oldpc + i * 2));
+		}
+		while (i++ < 5)
+			buf = buf_out (buf, &bufsize, _T("     "));
+
+		if (illegal)
+			buf = buf_out (buf, &bufsize, _T("[ "));
+		buf = buf_out (buf, &bufsize, instrname);
+		if (illegal)
+			buf = buf_out (buf, &bufsize, _T(" ]"));
+
+		if (ccpt != 0) {
+			uaecptr addr2 = deaddr2 ? deaddr2 : seaddr2;
+			if (deaddr)
+				*deaddr = pc;
+			if ((opcode & 0xf000) == 0xf000) {
+				if (fpp_cond(dp->cc)) {
+					buf = buf_out(buf, &bufsize, _T(" == $%08x (T)"), addr2);
+				} else {
+					buf = buf_out(buf, &bufsize, _T(" == $%08x (F)"), addr2);
+				}
+			} else {
+				if (cctrue (dp->cc)) {
+					buf = buf_out (buf, &bufsize, _T(" == $%08x (T)"), addr2);
+				} else {
+					buf = buf_out (buf, &bufsize, _T(" == $%08x (F)"), addr2);
+				}
+			}
+		} else if ((opcode & 0xff00) == 0x6100) { /* BSR */
+			if (deaddr)
+				*deaddr = pc;
+			buf = buf_out (buf, &bufsize, _T(" == $%08x"), seaddr2);
+		}
+		buf = buf_out (buf, &bufsize, _T("\n"));
+
+		if (illegal)
+			pc =  m68kpc_illg;
+	}
+	if (nextpc)
+		*nextpc = pc;
+	if (seaddr)
+		*seaddr = seaddr2;
+	if (deaddr)
+		*deaddr = deaddr2;
+}
+
+void m68k_disasm_ea (uaecptr addr, uaecptr *nextpc, int cnt, uae_u32 *seaddr, uae_u32 *deaddr)
+{
+	TCHAR *buf;
+
+	buf = xmalloc (TCHAR, (MAX_LINEWIDTH + 1) * cnt);
+	if (!buf)
+		return;
+	m68k_disasm_2 (buf, (MAX_LINEWIDTH + 1) * cnt, addr, nextpc, cnt, seaddr, deaddr, 1);
+	xfree (buf);
+}
+void m68k_disasm (uaecptr addr, uaecptr *nextpc, int cnt)
+{
+	TCHAR *buf;
+
+	buf = xmalloc (TCHAR, (MAX_LINEWIDTH + 1) * cnt);
+	if (!buf)
+		return;
+	m68k_disasm_2 (buf, (MAX_LINEWIDTH + 1) * cnt, addr, nextpc, cnt, NULL, NULL, 0);
+	console_out_f (_T("%s"), buf);
+	xfree (buf);
+}
+void m68k_disasm_file (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
+{
+	TCHAR *buf;
+
+	buf = xmalloc (TCHAR, (MAX_LINEWIDTH + 1) * cnt);
+	if (!buf)
+		return;
+	console_out_FILE = f;
+	m68k_disasm_2 (buf, (MAX_LINEWIDTH + 1) * cnt, addr, nextpc, cnt, NULL, NULL, 0);
+	f_out (f, _T("%s"), buf);
+	xfree (buf);
+	console_out_FILE = NULL;
+}
+
+/*************************************************************
+Disasm the m68kcode at the given address into instrname
+and instrcode
+*************************************************************/
+void sm68k_disasm (TCHAR *instrname, TCHAR *instrcode, uaecptr addr, uaecptr *nextpc)
+{
+	TCHAR *ccpt;
+	uae_u32 opcode;
+	struct mnemolookup *lookup;
+	struct instr *dp;
+	uaecptr pc, oldpc;
+
+	pc = oldpc = addr;
+	opcode = get_word_debug (pc);
+	if (cpufunctbl[opcode] == op_illg_1) {
+		opcode = 0x4AFC;
+	}
+	dp = table68k + opcode;
+	for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++);
+
+	pc += 2;
+
+	_tcscpy (instrname, lookup->name);
+	ccpt = _tcsstr (instrname, _T("cc"));
+	if (ccpt != 0) {
+		_tcsncpy (ccpt, ccnames[dp->cc], 2);
+	}
+	switch (dp->size){
+	case sz_byte: _tcscat (instrname, _T(".B ")); break;
+	case sz_word: _tcscat (instrname, _T(".W ")); break;
+	case sz_long: _tcscat (instrname, _T(".L ")); break;
+	default: _tcscat (instrname, _T("   ")); break;
+	}
+
+	if (dp->suse) {
+		pc = ShowEA (0, pc, opcode, dp->sreg, dp->smode, dp->size, instrname, NULL, 0);
+	}
+	if (dp->suse && dp->duse)
+		_tcscat (instrname, _T(","));
+	if (dp->duse) {
+		pc = ShowEA (0, pc, opcode, dp->dreg, dp->dmode, dp->size, instrname, NULL, 0);
+	}
+	if (instrcode)
+	{
+		int i;
+		for (i = 0; i < (int)(pc - oldpc) / 2; i++)
+		{
+			_stprintf (instrcode, _T("%04x "), get_iword_debug (oldpc + i * 2));
+			instrcode += _tcslen (instrcode);
+		}
+	}
+	if (nextpc)
+		*nextpc = pc;
+}
+
+struct cpum2c m2cregs[] = {
+	{ 0, _T("SFC") },
+	{ 1, _T("DFC") },
+	{ 2, _T("CACR") },
+	{ 3, _T("TC") },
+	{ 4, _T("ITT0") },
+	{ 5, _T("ITT1") },
+	{ 6, _T("DTT0") },
+	{ 7, _T("DTT1") },
+	{ 8, _T("BUSC") },
+	{ 0x800, _T("USP") },
+	{ 0x801, _T("VBR") },
+	{ 0x802, _T("CAAR") },
+	{ 0x803, _T("MSP") },
+	{ 0x804, _T("ISP") },
+	{ 0x805, _T("MMUS") },
+	{ 0x806, _T("URP") },
+	{ 0x807, _T("SRP") },
+	{ 0x808, _T("PCR") },
+    { -1, NULL }
+};
+
+void m68k_dumpstate_2 (uaecptr pc, uaecptr *nextpc)
+{
+	int i, j;
+
+	for (i = 0; i < 8; i++){
+		console_out_f (_T("  D%d %08X "), i, m68k_dreg (regs, i));
+		if ((i & 3) == 3) console_out_f (_T("\n"));
+	}
+	for (i = 0; i < 8; i++){
+		console_out_f (_T("  A%d %08X "), i, m68k_areg (regs, i));
+		if ((i & 3) == 3) console_out_f (_T("\n"));
+	}
+	if (regs.s == 0)
+		regs.usp = m68k_areg (regs, 7);
+	if (regs.s && regs.m)
+		regs.msp = m68k_areg (regs, 7);
+	if (regs.s && regs.m == 0)
+		regs.isp = m68k_areg (regs, 7);
+	j = 2;
+	console_out_f (_T("USP  %08X ISP  %08X "), regs.usp, regs.isp);
+	for (i = 0; m2cregs[i].regno>= 0; i++) {
+		if (!movec_illg (m2cregs[i].regno)) {
+			if (!_tcscmp (m2cregs[i].regname, _T("USP")) || !_tcscmp (m2cregs[i].regname, _T("ISP")))
+				continue;
+			if (j > 0 && (j % 4) == 0)
+				console_out_f (_T("\n"));
+			console_out_f (_T("%-4s %08X "), m2cregs[i].regname, val_move2c (m2cregs[i].regno));
+			j++;
+		}
+	}
+	if (j > 0)
+		console_out_f (_T("\n"));
+		console_out_f (_T("T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d STP=%d\n"),
+		regs.t1, regs.t0, regs.s, regs.m,
+		GET_XFLG (), GET_NFLG (), GET_ZFLG (),
+		GET_VFLG (), GET_CFLG (),
+		regs.intmask, regs.stopped);
+#ifdef FPUEMU
+	if (currprefs.fpu_model) {
+		uae_u32 fpsr;
+		for (i = 0; i < 8; i++){
+			console_out_f (_T("FP%d: %g "), i, regs.fp[i].fp);
+			if ((i & 3) == 3)
+				console_out_f (_T("\n"));
+		}
+		fpsr = fpp_get_fpsr ();
+		console_out_f (_T("FPSR: %04X FPCR: %08x FPIAR: %08x N=%d Z=%d I=%d NAN=%d\n"),
+			fpsr, regs.fpcr, regs.fpiar,
+			(fpsr & 0x8000000) != 0,
+			(fpsr & 0x4000000) != 0,
+			(fpsr & 0x2000000) != 0,
+			(fpsr & 0x1000000) != 0);
+	}
+#endif
+	if (currprefs.mmu_model == 68030) {
+#ifndef WINUAE_FOR_HATARI
+		console_out_f (_T("SRP: %llX CRP: %llX\n"), srp_030, crp_030);
+#else
+
+		console_out_f (_T("SRP: %"PRIX64" CRP: %"PRIX64"\n"), srp_030, crp_030);
+#endif
+		console_out_f (_T("TT0: %08X TT1: %08X TC: %08X\n"), tt0_030, tt1_030, tc_030);
+	}
+	if (currprefs.cpu_compatible && currprefs.cpu_model == 68000) {
+		struct instr *dp;
+		struct mnemolookup *lookup1, *lookup2;
+		dp = table68k + regs.irc;
+		for (lookup1 = lookuptab; lookup1->mnemo != dp->mnemo; lookup1++);
+		dp = table68k + regs.ir;
+		for (lookup2 = lookuptab; lookup2->mnemo != dp->mnemo; lookup2++);
+		console_out_f (_T("Prefetch %04x (%s) %04x (%s) Chip latch %08X\n"), regs.irc, lookup1->name, regs.ir, lookup2->name, regs.chipset_latch_rw);
+	}
+
+	if (pc != 0xffffffff) {
+		m68k_disasm (pc, nextpc, 1);
+		if (nextpc)
+			console_out_f (_T("Next PC: %08x\n"), *nextpc);
+	}
+}
+void m68k_dumpstate (uaecptr *nextpc)
+{
+	m68k_dumpstate_2 (m68k_getpc (), nextpc);
+}
+#ifdef WINUAE_FOR_HATARI
+void m68k_dumpstate_file (FILE *f, uaecptr *nextpc)
+{
+	console_out_FILE = f;
+	m68k_dumpstate_2 (m68k_getpc (), nextpc);
+	console_out_FILE = NULL;
+}
+#endif
+void m68k_dumpcache (void)
+{
+	int i , j;
+
+	if (!currprefs.cpu_compatible)
+		return;
+	if (currprefs.cpu_model == 68020) {
+		for (i = 0; i < CACHELINES020; i += 4) {
+			for (j = 0; j < 4; j++) {
+				int s = i + j;
+				uaecptr addr;
+				struct cache020 *c = &caches020[s];
+				addr = c->tag & ~1;
+				addr |= s << 2;
+				console_out_f (_T("%08X:%08X%c "), addr, c->data, c->valid ? '*' : ' ');
+			}
+			console_out_f (_T("\n"));
+		}
+	} else if (currprefs.cpu_model == 68030) {
+		for (i = 0; i < CACHELINES030; i++) {
+			struct cache030 *c = &icaches030[i];
+			uaecptr addr;
+			addr = c->tag & ~1;
+			addr |= i << 4;
+			console_out_f (_T("%08X: "), addr);
+			for (j = 0; j < 4; j++) {
+				console_out_f (_T("%08X%c "), c->data[j], c->valid[j] ? '*' : ' ');
+			}
+			console_out_f (_T("\n"));
+		}
+	}
+}
+
+#ifdef SAVESTATE
+
+/* CPU save/restore code */
+
+#define CPUTYPE_EC 1
+#define CPUMODE_HALT 1
+
+uae_u8 *restore_cpu (uae_u8 *src)
+{
+	int i, j , flags, model;
+	uae_u32 l;
+
+	currprefs.cpu_model = changed_prefs.cpu_model = model = restore_u32 ();
+	flags = restore_u32 ();
+	changed_prefs.address_space_24 = 0;
+	if (flags & CPUTYPE_EC)
+		changed_prefs.address_space_24 = 1;
+	currprefs.address_space_24 = changed_prefs.address_space_24;
+	currprefs.cpu_compatible = changed_prefs.cpu_compatible;
+	currprefs.cpu_cycle_exact = changed_prefs.cpu_cycle_exact;
+	currprefs.blitter_cycle_exact = changed_prefs.blitter_cycle_exact;
+	currprefs.cpu_frequency = changed_prefs.cpu_frequency = 0;
+	currprefs.cpu_clock_multiplier = changed_prefs.cpu_clock_multiplier = 0;
+	for (i = 0; i < 15; i++)
+		regs.regs[i] = restore_u32 ();
+	regs.pc = restore_u32 ();
+	regs.irc = restore_u16 ();
+	regs.ir = restore_u16 ();
+	regs.usp = restore_u32 ();
+	regs.isp = restore_u32 ();
+	regs.sr = restore_u16 ();
+printf ( "restore %x %x %x\n" , regs.usp , regs.isp , regs.sr );
+	l = restore_u32 ();
+	if (l & CPUMODE_HALT) {
+		regs.stopped = 1;
+	} else {
+		regs.stopped = 0;
+	}
+	if (model >= 68010) {
+		regs.dfc = restore_u32 ();
+		regs.sfc = restore_u32 ();
+		regs.vbr = restore_u32 ();
+	}
+	if (model >= 68020) {
+		regs.caar = restore_u32 ();
+		regs.cacr = restore_u32 ();
+		regs.msp = restore_u32 ();
+	}
+	if (model >= 68030) {
+		crp_030 = fake_crp_030 = restore_u64 ();
+		srp_030 = fake_srp_030 = restore_u64 ();
+		tt0_030 = fake_tt0_030 = restore_u32 ();
+		tt1_030 = fake_tt1_030 = restore_u32 ();
+		tc_030 = fake_tc_030 = restore_u32 ();
+		mmusr_030 = fake_mmusr_030 = restore_u16 ();
+	}
+	if (model >= 68040) {
+		regs.itt0 = restore_u32 ();
+		regs.itt1 = restore_u32 ();
+		regs.dtt0 = restore_u32 ();
+		regs.dtt1 = restore_u32 ();
+		regs.tcr = restore_u32 ();
+		regs.urp = restore_u32 ();
+		regs.srp = restore_u32 ();
+	}
+	if (model >= 68060) {
+		regs.buscr = restore_u32 ();
+		regs.pcr = restore_u32 ();
+	}
+	if (flags & 0x80000000) {
+		int khz = restore_u32 ();
+		restore_u32 ();
+		if (khz > 0 && khz < 800000)
+			currprefs.m68k_speed = changed_prefs.m68k_speed = 0;
+	}
+	set_cpu_caches (true);
+	if (flags & 0x40000000) {
+		if (model == 68020) {
+			for (i = 0; i < CACHELINES020; i++) {
+				caches020[i].data = restore_u32 ();
+				caches020[i].tag = restore_u32 ();
+				caches020[i].valid = restore_u8 () != 0;
+			}
+			regs.prefetch020addr = restore_u32 ();
+			regs.cacheholdingaddr020 = restore_u32 ();
+			regs.cacheholdingdata020 = restore_u32 ();
+			if (flags & 0x20000000) {
+				// 2.7.0 new
+				for (i = 0; i < CPU_PIPELINE_MAX; i++)
+					regs.prefetch020[i] = restore_u32 ();
+			} else {
+				for (i = 0; i < CPU_PIPELINE_MAX; i++)
+					regs.prefetch020[i] = restore_u16 ();
+			}
+		} else if (model == 68030) {
+			for (i = 0; i < CACHELINES030; i++) {
+				for (j = 0; j < 4; j++) {
+					icaches030[i].data[j] = restore_u32 ();
+					icaches030[i].valid[j] = restore_u8 () != 0;
+				}
+				icaches030[i].tag = restore_u32 ();
+			}
+			for (i = 0; i < CACHELINES030; i++) {
+				for (j = 0; j < 4; j++) {
+					dcaches030[i].data[j] = restore_u32 ();
+					dcaches030[i].valid[j] = restore_u8 () != 0;
+				}
+				dcaches030[i].tag = restore_u32 ();
+			}
+			regs.prefetch020addr = restore_u32 ();
+			regs.cacheholdingaddr020 = restore_u32 ();
+			regs.cacheholdingdata020 = restore_u32 ();
+			for (i = 0; i < CPU_PIPELINE_MAX; i++)
+				regs.prefetch020[i] = restore_u32 ();
+		} else if (model == 68040) {
+			if (flags & 0x8000000) {
+				for (i = 0; i < CACHESETS040; i++) {
+					for (j = 0; j < CACHELINES040; j++) {
+						icaches040[i].data[j][0] = restore_u32();
+						icaches040[i].data[j][1] = restore_u32();
+						icaches040[i].data[j][2] = restore_u32();
+						icaches040[i].data[j][3] = restore_u32();
+						icaches040[i].tag[j] = restore_u32();
+						icaches040[i].valid[j] = restore_u16() & 1;
+					}
+				}
+				regs.prefetch020addr = restore_u32();
+				regs.cacheholdingaddr020 = restore_u32();
+				regs.cacheholdingdata020 = restore_u32();
+				for (i = 0; i < CPU_PIPELINE_MAX; i++)
+					regs.prefetch020[i] = restore_u32();
+			}
+		}
+		if (model >= 68020) {
+			regs.ce020memcycles = restore_u32 ();
+			restore_u32 ();
+		}
+	}
+	if (flags & 0x10000000) {
+		regs.chipset_latch_rw = restore_u32 ();
+		regs.chipset_latch_read = restore_u32 ();
+		regs.chipset_latch_write = restore_u32 ();
+	}
+
+	m68k_reset_sr();
+
+	write_log (_T("CPU: %d%s%03d, PC=%08X\n"),
+		model / 1000, flags & 1 ? _T("EC") : _T(""), model % 1000, regs.pc);
+
+	return src;
+}
+
+static void fill_prefetch_quick (void)
+{
+	if (currprefs.cpu_model >= 68020) {
+		fill_prefetch ();
+		return;
+	}
+	// old statefile compatibility, this needs to done,
+	// even in 68000 cycle-exact mode
+	regs.ir = get_word (m68k_getpc ());
+	regs.irc = get_word (m68k_getpc () + 2);
+}
+
+void restore_cpu_finish (void)
+{
+	init_m68k ();
+	m68k_setpc_normal (regs.pc);
+	doint ();
+	fill_prefetch_quick ();
+printf ( "SR %x %x %x %x\n" , regs.sr , regs.isp , regs.usp , regs.regs[15] );
+#ifndef WINUAE_FOR_HATARI
+	set_cycles (start_cycles);
+	events_schedule ();
+#endif
+	if (regs.stopped)
+		set_special (SPCFLAG_STOP);
+	//activate_debugger ();
+}
+
+uae_u8 *save_cpu_trace (int *len, uae_u8 *dstptr)
+{
+	uae_u8 *dstbak, *dst;
+	int i;
+
+	if (cputrace.state <= 0)
+		return NULL;
+
+	if (dstptr)
+		dstbak = dst = dstptr;
+	else
+		dstbak = dst = xmalloc (uae_u8, 1000);
+
+	save_u32 (2 | 4 | 8);
+	save_u16 (cputrace.opcode);
+	for (i = 0; i < 16; i++)
+		save_u32 (cputrace.regs[i]);
+	save_u32 (cputrace.pc);
+	save_u16 (cputrace.irc);
+	save_u16 (cputrace.ir);
+	save_u32 (cputrace.usp);
+	save_u32 (cputrace.isp);
+	save_u16 (cputrace.sr);
+	save_u16 (cputrace.intmask);
+	save_u16 ((cputrace.stopped ? 1 : 0) | (regs.stopped ? 2 : 0));
+	save_u16 (cputrace.state);
+	save_u32 (cputrace.cyclecounter);
+	save_u32 (cputrace.cyclecounter_pre);
+	save_u32 (cputrace.cyclecounter_post);
+	save_u32 (cputrace.readcounter);
+	save_u32 (cputrace.writecounter);
+	save_u32 (cputrace.memoryoffset);
+	write_log (_T("CPUT SAVE: PC=%08x C=%08X %08x %08x %08x %d %d %d\n"),
+		cputrace.pc, cputrace.startcycles,
+		cputrace.cyclecounter, cputrace.cyclecounter_pre, cputrace.cyclecounter_post,
+		cputrace.readcounter, cputrace.writecounter, cputrace.memoryoffset);
+	for (i = 0; i < cputrace.memoryoffset; i++) {
+		save_u32 (cputrace.ctm[i].addr);
+		save_u32 (cputrace.ctm[i].data);
+		save_u32 (cputrace.ctm[i].mode);
+		write_log (_T("CPUT%d: %08x %08x %08x\n"), i, cputrace.ctm[i].addr, cputrace.ctm[i].data, cputrace.ctm[i].mode);
+	}
+	save_u32 (cputrace.startcycles);
+
+	if (currprefs.cpu_model == 68020) {
+		for (i = 0; i < CACHELINES020; i++) {
+			save_u32 (cputrace.caches020[i].data);
+			save_u32 (cputrace.caches020[i].tag);
+			save_u8 (cputrace.caches020[i].valid ? 1 : 0);
+		}
+		save_u32 (cputrace.prefetch020addr);
+		save_u32 (cputrace.cacheholdingaddr020);
+		save_u32 (cputrace.cacheholdingdata020);
+		for (i = 0; i < CPU_PIPELINE_MAX; i++)
+			save_u16 (cputrace.prefetch020[i]);
+		for (i = 0; i < CPU_PIPELINE_MAX; i++)
+			save_u32 (cputrace.prefetch020[i]);
+	}
+
+	*len = dst - dstbak;
+	cputrace.needendcycles = 1;
+	return dstbak;
+}
+
+uae_u8 *restore_cpu_trace (uae_u8 *src)
+{
+	int i;
+
+	cpu_tracer = 0;
+	cputrace.state = 0;
+	uae_u32 v = restore_u32 ();
+	if (!(v & 2))
+		return src;
+	cputrace.opcode = restore_u16 ();
+	for (i = 0; i < 16; i++)
+		cputrace.regs[i] = restore_u32 ();
+	cputrace.pc = restore_u32 ();
+	cputrace.irc = restore_u16 ();
+	cputrace.ir = restore_u16 ();
+	cputrace.usp = restore_u32 ();
+	cputrace.isp = restore_u32 ();
+	cputrace.sr = restore_u16 ();
+	cputrace.intmask = restore_u16 ();
+	cputrace.stopped = restore_u16 ();
+	cputrace.state = restore_u16 ();
+	cputrace.cyclecounter = restore_u32 ();
+	cputrace.cyclecounter_pre = restore_u32 ();
+	cputrace.cyclecounter_post = restore_u32 ();
+	cputrace.readcounter = restore_u32 ();
+	cputrace.writecounter = restore_u32 ();
+	cputrace.memoryoffset = restore_u32 ();
+	for (i = 0; i < cputrace.memoryoffset; i++) {
+		cputrace.ctm[i].addr = restore_u32 ();
+		cputrace.ctm[i].data = restore_u32 ();
+		cputrace.ctm[i].mode = restore_u32 ();
+	}
+	cputrace.startcycles = restore_u32 ();
+
+	if (v & 4) {
+		if (currprefs.cpu_model == 68020) {
+			for (i = 0; i < CACHELINES020; i++) {
+				cputrace.caches020[i].data = restore_u32 ();
+				cputrace.caches020[i].tag = restore_u32 ();
+				cputrace.caches020[i].valid = restore_u8 () != 0;
+			}
+			cputrace.prefetch020addr = restore_u32 ();
+			cputrace.cacheholdingaddr020 = restore_u32 ();
+			cputrace.cacheholdingdata020 = restore_u32 ();
+			for (i = 0; i < CPU_PIPELINE_MAX; i++)
+				cputrace.prefetch020[i] = restore_u16 ();
+			if (v & 8) {
+				for (i = 0; i < CPU_PIPELINE_MAX; i++)
+					cputrace.prefetch020[i] = restore_u32 ();
+			}
+		}
+	}
+
+	cputrace.needendcycles = 1;
+	if (v && cputrace.state) {
+		if (currprefs.cpu_model > 68000) {
+			if (v & 4)
+				cpu_tracer = -1;
+			// old format?
+			if ((v & (4 | 8)) != (4 | 8))
+				cpu_tracer = 0;
+		} else {
+			cpu_tracer = -1;
+		}
+	}
+
+	return src;
+}
+
+uae_u8 *restore_cpu_extra (uae_u8 *src)
+{
+	restore_u32 ();
+	uae_u32 flags = restore_u32 ();
+
+	currprefs.cpu_cycle_exact = changed_prefs.cpu_cycle_exact = (flags & 1) ? true : false;
+	currprefs.blitter_cycle_exact = changed_prefs.blitter_cycle_exact = currprefs.cpu_cycle_exact;
+	currprefs.cpu_compatible = changed_prefs.cpu_compatible = (flags & 2) ? true : false;
+	currprefs.cpu_frequency = changed_prefs.cpu_frequency = restore_u32 ();
+	currprefs.cpu_clock_multiplier = changed_prefs.cpu_clock_multiplier = restore_u32 ();
+	//currprefs.cachesize = changed_prefs.cachesize = (flags & 8) ? 8192 : 0;
+
+	currprefs.m68k_speed = changed_prefs.m68k_speed = 0;
+	if (flags & 4)
+		currprefs.m68k_speed = changed_prefs.m68k_speed = -1;
+	if (flags & 16)
+		currprefs.m68k_speed = changed_prefs.m68k_speed = (flags >> 24) * CYCLE_UNIT;
+
+	currprefs.cpu060_revision = changed_prefs.cpu060_revision = restore_u8 ();
+	currprefs.fpu_revision = changed_prefs.fpu_revision = restore_u8 ();
+
+	return src;
+}
+
+uae_u8 *save_cpu_extra (int *len, uae_u8 *dstptr)
+{
+	uae_u8 *dstbak, *dst;
+	uae_u32 flags;
+
+	if (dstptr)
+		dstbak = dst = dstptr;
+	else
+		dstbak = dst = xmalloc (uae_u8, 1000);
+	save_u32 (0); // version
+	flags = 0;
+	flags |= currprefs.cpu_cycle_exact ? 1 : 0;
+	flags |= currprefs.cpu_compatible ? 2 : 0;
+	flags |= currprefs.m68k_speed < 0 ? 4 : 0;
+	flags |= currprefs.cachesize > 0 ? 8 : 0;
+	flags |= currprefs.m68k_speed > 0 ? 16 : 0;
+	if (currprefs.m68k_speed > 0)
+		flags |= (currprefs.m68k_speed / CYCLE_UNIT) << 24;
+	save_u32 (flags);
+	save_u32 (currprefs.cpu_frequency);
+	save_u32 (currprefs.cpu_clock_multiplier);
+	save_u8 (currprefs.cpu060_revision);
+	save_u8 (currprefs.fpu_revision);
+	*len = dst - dstbak;
+	return dstbak;
+}
+
+uae_u8 *save_cpu (int *len, uae_u8 *dstptr)
+{
+	uae_u8 *dstbak, *dst;
+	int model, i, j, khz;
+
+	if (dstptr)
+		dstbak = dst = dstptr;
+	else
+		dstbak = dst = xmalloc (uae_u8, 1000);
+	model = currprefs.cpu_model;
+	save_u32 (model);					/* MODEL */
+	save_u32(0x80000000 | 0x40000000 | 0x20000000 | 0x10000000 | 0x8000000 |(currprefs.address_space_24 ? 1 : 0)); /* FLAGS */
+	for (i = 0;i < 15; i++)
+		save_u32 (regs.regs[i]);		/* D0-D7 A0-A6 */
+	save_u32 (m68k_getpc ());			/* PC */
+	save_u16 (regs.irc);				/* prefetch */
+	save_u16 (regs.ir);					/* instruction prefetch */
+	MakeSR ();
+	save_u32 (!regs.s ? regs.regs[15] : regs.usp);	/* USP */
+	save_u32 (regs.s ? regs.regs[15] : regs.isp);	/* ISP */
+	save_u16 (regs.sr);								/* SR/CCR */
+	save_u32 (regs.stopped ? CPUMODE_HALT : 0);		/* flags */
+	if (model >= 68010) {
+		save_u32 (regs.dfc);			/* DFC */
+		save_u32 (regs.sfc);			/* SFC */
+		save_u32 (regs.vbr);			/* VBR */
+	}
+	if (model >= 68020) {
+		save_u32 (regs.caar);			/* CAAR */
+		save_u32 (regs.cacr);			/* CACR */
+		save_u32 (regs.msp);			/* MSP */
+	}
+	if (model >= 68030) {
+		if (currprefs.mmu_model) {
+			save_u64 (crp_030);				/* CRP */
+			save_u64 (srp_030);				/* SRP */
+			save_u32 (tt0_030);				/* TT0/AC0 */
+			save_u32 (tt1_030);				/* TT1/AC1 */
+			save_u32 (tc_030);				/* TCR */
+			save_u16 (mmusr_030);			/* MMUSR/ACUSR */
+		} else {
+			save_u64 (fake_crp_030);		/* CRP */
+			save_u64 (fake_srp_030);		/* SRP */
+			save_u32 (fake_tt0_030);		/* TT0/AC0 */
+			save_u32 (fake_tt1_030);		/* TT1/AC1 */
+			save_u32 (fake_tc_030);			/* TCR */
+			save_u16 (fake_mmusr_030);		/* MMUSR/ACUSR */
+		}
+	}
+	if (model >= 68040) {
+		save_u32 (regs.itt0);			/* ITT0 */
+		save_u32 (regs.itt1);			/* ITT1 */
+		save_u32 (regs.dtt0);			/* DTT0 */
+		save_u32 (regs.dtt1);			/* DTT1 */
+		save_u32 (regs.tcr);			/* TCR */
+		save_u32 (regs.urp);			/* URP */
+		save_u32 (regs.srp);			/* SRP */
+	}
+	if (model >= 68060) {
+		save_u32 (regs.buscr);			/* BUSCR */
+		save_u32 (regs.pcr);			/* PCR */
+	}
+	khz = -1;
+	if (currprefs.m68k_speed == 0) {
+		khz = currprefs.ntscmode ? 715909 : 709379;
+		if (currprefs.cpu_model >= 68020)
+			khz *= 2;
+	}
+	save_u32 (khz); // clock rate in KHz: -1 = fastest possible
+	save_u32 (0); // spare
+	if (model == 68020) {
+		for (i = 0; i < CACHELINES020; i++) {
+			save_u32 (caches020[i].data);
+			save_u32 (caches020[i].tag);
+			save_u8 (caches020[i].valid ? 1 : 0);
+		}
+		save_u32 (regs.prefetch020addr);
+		save_u32 (regs.cacheholdingaddr020);
+		save_u32 (regs.cacheholdingdata020);
+		for (i = 0; i < CPU_PIPELINE_MAX; i++)
+			save_u32 (regs.prefetch020[i]);
+	} else if (model == 68030) {
+		for (i = 0; i < CACHELINES030; i++) {
+			for (j = 0; j < 4; j++) {
+				save_u32 (icaches030[i].data[j]);
+				save_u8 (icaches030[i].valid[j] ? 1 : 0);
+			}
+			save_u32 (icaches030[i].tag);
+		}
+		for (i = 0; i < CACHELINES030; i++) {
+			for (j = 0; j < 4; j++) {
+				save_u32 (dcaches030[i].data[j]);
+				save_u8 (dcaches030[i].valid[j] ? 1 : 0);
+			}
+			save_u32 (dcaches030[i].tag);
+		}
+		save_u32 (regs.prefetch020addr);
+		save_u32 (regs.cacheholdingaddr020);
+		save_u32 (regs.cacheholdingdata020);
+		for (i = 0; i < CPU_PIPELINE_MAX; i++)
+			save_u32 (regs.prefetch020[i]);
+	} else if (model >= 68040) {
+		for (i = 0; i < CACHESETS040; i++) {
+			for (j = 0; j < CACHELINES040; j++) {
+				save_u32(icaches040[i].data[j][0]);
+				save_u32(icaches040[i].data[j][1]);
+				save_u32(icaches040[i].data[j][2]);
+				save_u32(icaches040[i].data[j][3]);
+				save_u32(icaches040[i].tag[j]);
+				save_u16(icaches040[i].valid[j] ? 1 : 0);
+			}
+		}
+		save_u32(regs.prefetch020addr);
+		save_u32(regs.cacheholdingaddr020);
+		save_u32(regs.cacheholdingdata020);
+		for (i = 0; i < CPU_PIPELINE_MAX; i++)
+			save_u32(regs.prefetch020[i]);
+	}
+	if (currprefs.cpu_model >= 68020) {
+		save_u32 (regs.ce020memcycles);
+		save_u32 (0);
+	}
+	save_u32 (regs.chipset_latch_rw);
+	save_u32 (regs.chipset_latch_read);
+	save_u32 (regs.chipset_latch_write);
+	*len = dst - dstbak;
+	return dstbak;
+}
+
+uae_u8 *save_mmu (int *len, uae_u8 *dstptr)
+{
+	uae_u8 *dstbak, *dst;
+	int model;
+
+	model = currprefs.mmu_model;
+#ifndef WINUAE_FOR_HATARI
+        /* Under Hatari, we save all MMU variables, even if mmu_model==0 */
+	if (model != 68030 && model != 68040 && model != 68060)
+		return NULL;
+#endif
+	if (dstptr)
+		dstbak = dst = dstptr;
+	else
+		dstbak = dst = xmalloc (uae_u8, 1000);
+	save_u32 (model);	/* MODEL */
+	save_u32 (0);		/* FLAGS */
+	*len = dst - dstbak;
+	return dstbak;
+}
+
+uae_u8 *restore_mmu (uae_u8 *src)
+{
+	int flags, model;
+
+	changed_prefs.mmu_model = model = restore_u32 ();
+	flags = restore_u32 ();
+	write_log (_T("MMU: %d\n"), model);
+	return src;
+}
+
+#endif /* SAVESTATE */
+
+static void exception3f (uae_u32 opcode, uaecptr addr, bool writeaccess, bool instructionaccess, bool notinstruction, uaecptr pc, bool plus2)
+{
+	if (currprefs.cpu_model >= 68040)
+		addr &= ~1;
+	if (currprefs.cpu_model >= 68020) {
+		if (pc == 0xffffffff)
+			last_addr_for_exception_3 = regs.instruction_pc;
+		else
+			last_addr_for_exception_3 = pc;
+	} else if (pc == 0xffffffff) {
+		last_addr_for_exception_3 = m68k_getpc ();
+		if (plus2)
+			last_addr_for_exception_3 += 2;
+	} else {
+		last_addr_for_exception_3 = pc;
+	}
+	last_fault_for_exception_3 = addr;
+	last_op_for_exception_3 = opcode;
+	last_writeaccess_for_exception_3 = writeaccess;
+	last_instructionaccess_for_exception_3 = instructionaccess;
+	last_notinstruction_for_exception_3 = notinstruction;
+	Exception (3);
+#if EXCEPTION3_DEBUGGER
+	activate_debugger();
+#endif
+}
+
+void exception3_notinstruction(uae_u32 opcode, uaecptr addr)
+{
+	exception3f (opcode, addr, true, false, true, 0xffffffff, false);
+}
+void exception3_read(uae_u32 opcode, uaecptr addr)
+{
+	exception3f (opcode, addr, false, 0, false, 0xffffffff, false);
+}
+void exception3_write(uae_u32 opcode, uaecptr addr)
+{
+	exception3f (opcode, addr, true, 0, false, 0xffffffff, false);
+}
+void exception3i (uae_u32 opcode, uaecptr addr)
+{
+	exception3f (opcode, addr, 0, 1, false, 0xffffffff, true);
+}
+void exception3b (uae_u32 opcode, uaecptr addr, bool w, bool i, uaecptr pc)
+{
+	exception3f (opcode, addr, w, i, false, pc, true);
+}
+
+void exception2 (uaecptr addr, bool read, int size, uae_u32 fc)
+{
+	if (currprefs.mmu_model) {
+		if (currprefs.mmu_model == 68030) {
+			uae_u32 flags = size == 1 ? MMU030_SSW_SIZE_B : (size == 2 ? MMU030_SSW_SIZE_W : MMU030_SSW_SIZE_L);
+			mmu030_page_fault (addr, read, flags, fc);
+		} else {
+			mmu_bus_error (addr, fc, read == false, size, false, 0, true);
+		}
+	} else {
+		last_addr_for_exception_3 = m68k_getpc() + bus_error_offset;
+		last_fault_for_exception_3 = addr;
+		last_writeaccess_for_exception_3 = read == 0;
+		last_instructionaccess_for_exception_3 = (fc & 1) == 0;
+		last_op_for_exception_3 = regs.opcode;
+		last_notinstruction_for_exception_3 = exception_in_exception != 0;
+		THROW(2);
+	}
+}
+
+void cpureset (void)
+{
+    /* RESET hasn't increased PC yet, 1 word offset */
+	uaecptr pc;
+#ifndef WINUAE_FOR_HATARI
+	uaecptr ksboot = 0xf80002 - 2;
+	uae_u16 ins;
+#endif
+	addrbank *ab;
+
+	m68k_reset_delay = currprefs.reset_delay;
+	set_special(SPCFLAG_CHECK);
+#ifndef WINUAE_FOR_HATARI
+	send_internalevent(INTERNALEVENT_CPURESET);
+	if ((currprefs.cpu_compatible || currprefs.cpu_cycle_exact) && currprefs.cpu_model <= 68020) {
+		custom_reset (false, false);
+		return;
+	}
+#endif
+	pc = m68k_getpc () + 2;
+	ab = &get_mem_bank (pc);
+	if (ab->check (pc, 2)) {
+		write_log (_T("CPU reset PC=%x (%s)..\n"), pc - 2, ab->name);
+#ifndef WINUAE_FOR_HATARI
+		ins = get_word (pc);
+		custom_reset (false, false);
+		// did memory disappear under us?
+		if (ab == &get_mem_bank (pc))
+			return;
+		// it did
+		if ((ins & ~7) == 0x4ed0) {
+			int reg = ins & 7;
+			uae_u32 addr = m68k_areg (regs, reg);
+			if (addr < 0x80000)
+				addr += 0xf80000;
+			write_log (_T("reset/jmp (ax) combination at %08x emulated -> %x\n"), pc, addr);
+			m68k_setpc_normal (addr - 2);
+			return;
+		}
+#else
+		customreset ();		/* From hatari-glue.c */
+		return;
+#endif
+	}
+	// the best we can do, jump directly to ROM entrypoint
+	// (which is probably what program wanted anyway)
+#ifndef WINUAE_FOR_HATARI
+	write_log (_T("CPU Reset PC=%x (%s), invalid memory -> %x.\n"), pc, ab->name, ksboot + 2);
+	custom_reset (false, false);
+	m68k_setpc_normal (ksboot);
+#else
+	write_log (_T("CPU Reset PC=%x (%s), invalid memory\n"), pc, ab->name);
+	customreset ();			/* From hatari-glue.c */
+#endif
+}
+
+
+void m68k_setstopped (void)
+{
+	regs.stopped = 1;
+	/* A traced STOP instruction drops through immediately without
+	actually stopping.  */
+	if ((regs.spcflags & SPCFLAG_DOTRACE) == 0)
+		set_special (SPCFLAG_STOP);
+	else
+		m68k_resumestopped ();
+}
+
+void m68k_resumestopped (void)
+{
+	if (!regs.stopped)
+		return;
+	regs.stopped = 0;
+	if (currprefs.cpu_cycle_exact) {
+		if (currprefs.cpu_model == 68000)
+			x_do_cycles (6 * cpucycleunit);
+	}
+	fill_prefetch ();
+	unset_special (SPCFLAG_STOP);
+}
+
+// this one is really simple and easy
+static void fill_icache020 (uae_u32 addr, uae_u32 (*fetch)(uaecptr))
+{
+	int index;
+	uae_u32 tag;
+	uae_u32 data;
+	struct cache020 *c;
+
+	addr &= ~3;
+	if (regs.cacheholdingaddr020 == addr)
+		return;
+	index = (addr >> 2) & (CACHELINES020 - 1);
+	tag = regs.s | (addr & ~((CACHELINES020 << 2) - 1));
+	c = &caches020[index];
+	if (c->valid && c->tag == tag) {
+		// cache hit
+		regs.cacheholdingaddr020 = addr;
+		regs.cacheholdingdata020 = c->data;
+#ifdef WINUAE_FOR_HATARI
+		CpuInstruction.I_Cache_hit++;
+#endif
+		return;
+	}
+	// cache miss
+	// Prefetch apparently can be queued by bus controller
+	// even if bus controller is currently processing
+	// previous data access.
+	// Other combinations are not possible.
+	if (!regs.ce020memcycle_data)
+		regs.ce020memcycles = 0;
+	regs.ce020memcycle_data = false;
+	unsigned long cycs = get_cycles ();
+	data = fetch (addr);
+	// add as available "free" internal CPU time.
+	cycs = get_cycles () - cycs;
+	regs.ce020memcycles += cycs;
+	if (!(regs.cacr & 2)) {
+		c->tag = tag;
+		c->valid = !!(regs.cacr & 1);
+		c->data = data;
+	}
+	regs.cacheholdingaddr020 = addr;
+	regs.cacheholdingdata020 = data;
+#ifdef WINUAE_FOR_HATARI
+	CpuInstruction.I_Cache_miss++;
+#endif
+}
+
+#if MORE_ACCURATE_68020_PIPELINE
+#define PIPELINE_DEBUG 0
+#if PIPELINE_DEBUG
+static uae_u16 pipeline_opcode;
+#endif
+static void pipeline_020(uae_u16 w, uaecptr pc)
+{
+	if (regs.pipeline_pos < 0)
+		return;
+	if (regs.pipeline_pos > 0) {
+		// handle annoying 68020+ addressing modes
+		if (regs.pipeline_pos == regs.pipeline_r8[0]) {
+			regs.pipeline_r8[0] = 0;
+			if (w & 0x100) {
+				int extra = 0;
+				if ((w & 0x30) == 0x20)
+					extra += 2;
+				if ((w & 0x30) == 0x30)
+					extra += 4;
+				if ((w & 0x03) == 0x02)
+					extra += 2;
+				if ((w & 0x03) == 0x03)
+					extra += 4;
+				regs.pipeline_pos += extra;
+			}
+			return;
+		}
+		if (regs.pipeline_pos == regs.pipeline_r8[1]) {
+			regs.pipeline_r8[1] = 0;
+			if (w & 0x100) {
+				int extra = 0;
+				if ((w & 0x30) == 0x20)
+					extra += 2;
+				if ((w & 0x30) == 0x30)
+					extra += 4;
+				if ((w & 0x03) == 0x02)
+					extra += 2;
+				if ((w & 0x03) == 0x03)
+					extra += 4;
+				regs.pipeline_pos += extra;
+			}
+			return;
+		}
+	}
+	if (regs.pipeline_pos > 2) {
+		regs.pipeline_pos -= 2;
+		// If stop set, prefetches stop 1 word early.
+		if (regs.pipeline_stop > 0 && regs.pipeline_pos == 2)
+			regs.pipeline_stop = -1;
+		return;
+	}
+	if (regs.pipeline_stop) {
+		regs.pipeline_stop = -1;
+		return;
+	}
+#if PIPELINE_DEBUG
+	pipeline_opcode = w;
+#endif
+	regs.pipeline_r8[0] = cpudatatbl[w].disp020[0];
+	regs.pipeline_r8[1] = cpudatatbl[w].disp020[1];
+	regs.pipeline_pos = cpudatatbl[w].length;
+#if PIPELINE_DEBUG
+	if (!regs.pipeline_pos) {
+		write_log(_T("Opcode %04x has no size PC=%08x!\n"), w, pc);
+	}
+#endif
+	int branch = cpudatatbl[w].branch;
+	if (regs.pipeline_pos > 0 && branch) {
+		// Short branches (Bcc.s) still do one more prefetch.
+#if 0
+		// RTS and other unconditional single opcode instruction stop immediately.
+		if (branch == 2) {
+			// Immediate stop
+			regs.pipeline_stop = -1;
+		} else {
+			// Stop 1 word early than normally
+			regs.pipeline_stop = 1;
+		}
+#else
+		regs.pipeline_stop = 1;
+#endif
+	}
+}
+
+// Not exactly right, requires logic analyzer checks.
+void continue_ce020_prefetch(void)
+{
+	fill_prefetch_020();
+}
+void continue_020_prefetch(void)
+{
+	fill_prefetch_020();
+}
+#endif
+
+uae_u32 get_word_ce020_prefetch (int o)
+{
+	uae_u32 pc = m68k_getpc () + o;
+	uae_u32 v;
+
+	if (pc & 2) {
+		v = regs.prefetch020[0] & 0xffff;
+#if MORE_ACCURATE_68020_PIPELINE
+		pipeline_020(regs.prefetch020[1], pc );
+#endif
+		regs.prefetch020[0] = regs.prefetch020[1];
+		// branch instruction detected in pipeline: stop fetches until branch executed.
+		if (!MORE_ACCURATE_68020_PIPELINE || regs.pipeline_stop >= 0) {
+			fill_icache020 (pc + 2 + 4, mem_access_delay_longi_read_ce020);
+			regs.prefetch020[1] = regs.cacheholdingdata020;
+		}
+		regs.db = regs.prefetch020[0] >> 16;
+	} else {
+		v = regs.prefetch020[0] >> 16;
+#if MORE_ACCURATE_68020_PIPELINE
+		pipeline_020(regs.prefetch020[1] >> 16, pc);
+#endif
+		regs.db = regs.prefetch020[1] >> 16;
+	}
+	do_cycles_ce020_internal (2);
+	return v;
+}
+
+uae_u32 get_word_020_prefetch (int o)
+{
+	uae_u32 pc = m68k_getpc () + o;
+	uae_u32 v;
+
+	if (pc & 2) {
+		v = regs.prefetch020[0] & 0xffff;
+#if MORE_ACCURATE_68020_PIPELINE
+		pipeline_020(regs.prefetch020[1], pc);
+#endif
+		regs.prefetch020[0] = regs.prefetch020[1];
+		if (!MORE_ACCURATE_68020_PIPELINE || regs.pipeline_stop >= 0) {
+			fill_icache020 (pc + 2 + 4, get_longi);
+			regs.prefetch020[1] = regs.cacheholdingdata020;
+		}
+		regs.db = regs.prefetch020[0] >> 16;
+	} else {
+		v = regs.prefetch020[0] >> 16;
+#if MORE_ACCURATE_68020_PIPELINE
+		pipeline_020(regs.prefetch020[1] >> 16, pc);
+#endif
+		regs.db = regs.prefetch020[0];
+	}
+//if ( ( v & 0xffff ) != ( get_word(pc) & 0xffff ) )
+//  fprintf ( stderr , "prefetch mismatch pc=%x prefetch=%x != mem=%x, i-cache error ?\n" , pc , v&0xffff , get_word(pc)&0xffff );
+	return v;
+}
+
+// these are also used by 68030.
+
+#define RESET_CE020_CYCLES \
+	regs.ce020memcycles = 0; \
+	regs.ce020memcycle_data = true;
+#define STORE_CE020_CYCLES \
+	unsigned long cycs = get_cycles ()
+#define ADD_CE020_CYCLES \
+	regs.ce020memcycles += get_cycles () - cycs
+
+uae_u32 mem_access_delay_long_read_ce020 (uaecptr addr)
+{
+	uae_u32 v;
+	RESET_CE020_CYCLES;
+	STORE_CE020_CYCLES;
+	switch (ce_banktype[addr >> 16])
+	{
+	case CE_MEMBANK_CHIP16:
+		v  = wait_cpu_cycle_read_ce020 (addr + 0, 1) << 16;
+		v |= wait_cpu_cycle_read_ce020 (addr + 2, 1) <<  0;
+		break;
+	case CE_MEMBANK_CHIP32:
+		if ((addr & 3) != 0) {
+			v  = wait_cpu_cycle_read_ce020 (addr + 0, 1) << 16;
+			v |= wait_cpu_cycle_read_ce020 (addr + 2, 1) <<  0;
+		} else {
+			v = wait_cpu_cycle_read_ce020 (addr, -1);
+		}
+		break;
+	case CE_MEMBANK_FAST32:
+		v = get_long (addr);
+		if ((addr & 3) != 0)
+			do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v);
+		else
+			do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v);
+		break;
+	case CE_MEMBANK_FAST16:
+		v = get_long (addr);
+		do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v);
+		break;
+	default:
+		v = get_long (addr);
+		break;
+	}
+	ADD_CE020_CYCLES;
+	return v;
+}
+
+uae_u32 mem_access_delay_longi_read_ce020 (uaecptr addr)
+{
+	uae_u32 v;
+	switch (ce_banktype[addr >> 16])
+	{
+	case CE_MEMBANK_CHIP16:
+		v  = wait_cpu_cycle_read_ce020 (addr + 0, 1) << 16;
+		v |= wait_cpu_cycle_read_ce020 (addr + 2, 1) <<  0;
+		break;
+	case CE_MEMBANK_CHIP32:
+		if ((addr & 3) != 0) {
+			v  = wait_cpu_cycle_read_ce020 (addr + 0, 1) << 16;
+			v |= wait_cpu_cycle_read_ce020 (addr + 2, 1) <<  0;
+		} else {
+			v = wait_cpu_cycle_read_ce020 (addr, -1);
+		}
+		break;
+	case CE_MEMBANK_FAST32:
+		v = get_longi (addr);
+		if ((addr & 3) != 0)
+			do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v);
+		else
+			do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v);
+		break;
+	case CE_MEMBANK_FAST16:
+		v = get_longi (addr);
+		do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v);
+		break;
+	default:
+		v = get_longi (addr);
+		break;
+	}
+	return v;
+}
+
+uae_u32 mem_access_delay_word_read_ce020 (uaecptr addr)
+{
+	uae_u32 v;
+	RESET_CE020_CYCLES;
+	STORE_CE020_CYCLES;
+	switch (ce_banktype[addr >> 16])
+	{
+	case CE_MEMBANK_CHIP16:
+	case CE_MEMBANK_CHIP32:
+		if ((addr & 3) == 3) {
+			v  = wait_cpu_cycle_read_ce020 (addr + 0, 0) << 8;
+			v |= wait_cpu_cycle_read_ce020 (addr + 1, 0) << 0;
+		} else {
+			v = wait_cpu_cycle_read_ce020 (addr, 1);
+		}
+		break;
+	case CE_MEMBANK_FAST16:
+	case CE_MEMBANK_FAST32:
+		v = get_word (addr);
+		if ((addr & 3) == 3)
+			do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v);
+		else
+			do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v);
+		 break;
+	default:
+		 v = get_word (addr);
+		break;
+	}
+	ADD_CE020_CYCLES;
+	return v;
+}
+
+uae_u32 mem_access_delay_byte_read_ce020 (uaecptr addr)
+{
+	uae_u32 v;
+	RESET_CE020_CYCLES;
+	STORE_CE020_CYCLES;
+	switch (ce_banktype[addr >> 16])
+	{
+	case CE_MEMBANK_CHIP16:
+	case CE_MEMBANK_CHIP32:
+		v = wait_cpu_cycle_read_ce020 (addr, 0);
+		break;
+	case CE_MEMBANK_FAST16:
+	case CE_MEMBANK_FAST32:
+		v = get_byte (addr);
+		do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v);
+		break;
+	default:
+		v = get_byte (addr);
+		break;
+	}
+	ADD_CE020_CYCLES;
+	return v;
+}
+
+void mem_access_delay_byte_write_ce020 (uaecptr addr, uae_u32 v)
+{
+	RESET_CE020_CYCLES;
+	STORE_CE020_CYCLES;
+	switch (ce_banktype[addr >> 16])
+	{
+	case CE_MEMBANK_CHIP16:
+	case CE_MEMBANK_CHIP32:
+		wait_cpu_cycle_write_ce020 (addr, 0, v);
+		break;
+	case CE_MEMBANK_FAST16:
+	case CE_MEMBANK_FAST32:
+		put_byte (addr, v);
+		do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v);
+		break;
+	default:
+		put_byte (addr, v);
+	break;
+	}
+	ADD_CE020_CYCLES;
+}
+
+void mem_access_delay_word_write_ce020 (uaecptr addr, uae_u32 v)
+{
+	RESET_CE020_CYCLES;
+	STORE_CE020_CYCLES;
+	switch (ce_banktype[addr >> 16])
+	{
+	case CE_MEMBANK_CHIP16:
+	case CE_MEMBANK_CHIP32:
+		if ((addr & 3) == 3) {
+			wait_cpu_cycle_write_ce020 (addr + 0, 0, (v >> 8) & 0xff);
+			wait_cpu_cycle_write_ce020 (addr + 1, 0, (v >> 0) & 0xff);
+		} else {
+			wait_cpu_cycle_write_ce020 (addr + 0, 1, v);
+		}
+		break;
+	case CE_MEMBANK_FAST16:
+	case CE_MEMBANK_FAST32:
+		put_word (addr, v);
+		if ((addr & 3) == 3)
+			do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v);
+		else
+			do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v);
+		break;
+	default:
+		put_word (addr, v);
+	break;
+	}
+	ADD_CE020_CYCLES;
+}
+
+void mem_access_delay_long_write_ce020 (uaecptr addr, uae_u32 v)
+{
+	RESET_CE020_CYCLES;
+	STORE_CE020_CYCLES;
+	switch (ce_banktype[addr >> 16])
+	{
+	case CE_MEMBANK_CHIP16:
+		wait_cpu_cycle_write_ce020 (addr + 0, 1, (v >> 16) & 0xffff);
+		wait_cpu_cycle_write_ce020 (addr + 2, 1, (v >>  0) & 0xffff);
+		break;
+	case CE_MEMBANK_CHIP32:
+		if ((addr & 3) == 3) {
+			wait_cpu_cycle_write_ce020 (addr + 0, 1, (v >> 16) & 0xffff);
+			wait_cpu_cycle_write_ce020 (addr + 2, 1, (v >>  0) & 0xffff);
+		} else {
+			wait_cpu_cycle_write_ce020 (addr + 0, -1, v);
+		}
+		break;
+	case CE_MEMBANK_FAST32:
+		put_long (addr, v);
+		if ((addr & 3) != 0)
+			do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v);
+		else
+			do_cycles_ce020_mem (1 * CPU020_MEM_CYCLE, v);
+		break;
+	case CE_MEMBANK_FAST16:
+		put_long (addr, v);
+		do_cycles_ce020_mem (2 * CPU020_MEM_CYCLE, v);
+		break;
+	default:
+		put_long (addr, v);
+		break;
+	}
+	ADD_CE020_CYCLES;
+}
+
+
+// 68030 caches aren't so simple as 68020 cache..
+STATIC_INLINE struct cache030 *getcache030 (struct cache030 *cp, uaecptr addr, uae_u32 *tagp, int *lwsp)
+{
+	int index, lws;
+	uae_u32 tag;
+	struct cache030 *c;
+
+	addr &= ~3;
+	index = (addr >> 4) & (CACHELINES030 - 1);
+	tag = regs.s | (addr & ~((CACHELINES030 << 4) - 1));
+	lws = (addr >> 2) & 3;
+	c = &cp[index];
+	*tagp = tag;
+	*lwsp = lws;
+	return c;
+}
+
+STATIC_INLINE void update_cache030 (struct cache030 *c, uae_u32 val, uae_u32 tag, int lws)
+{
+	if (c->tag != tag)
+		c->valid[0] = c->valid[1] = c->valid[2] = c->valid[3] = false;
+	c->tag = tag;
+	c->valid[lws] = true;
+	c->data[lws] = val;
+}
+
+static void fill_icache030 (uae_u32 addr)
+{
+	int lws;
+	uae_u32 tag;
+	uae_u32 data;
+	struct cache030 *c;
+//fprintf ( stderr , "fill ica %x\n" , addr );
+
+	addr &= ~3;
+	if (regs.cacheholdingaddr020 == addr)
+		return;
+	c = getcache030 (icaches030, addr, &tag, &lws);
+	if (c->valid[lws] && c->tag == tag) {
+		// cache hit
+		regs.cacheholdingaddr020 = addr;
+		regs.cacheholdingdata020 = c->data[lws];
+//fprintf ( stderr , "fill ica %x -> hit %x\n" , addr , regs.cacheholdingdata020 );
+#ifdef WINUAE_FOR_HATARI
+		CpuInstruction.I_Cache_hit++;
+#endif
+		return;
+	}
+
+	// cache miss
+	if (currprefs.cpu_cycle_exact) {
+		if (!regs.ce020memcycle_data)
+			regs.ce020memcycles = 0;
+		regs.ce020memcycle_data = false;
+		unsigned long cycs = get_cycles ();
+		data = mem_access_delay_longi_read_ce020 (addr);
+		// add as available "free" internal CPU time.
+		cycs = get_cycles () - cycs;
+		regs.ce020memcycles += cycs;
+	} else {
+		data = get_longi (addr);
+	}
+	if ((regs.cacr & 3) == 1) { // not frozen and enabled
+//fprintf ( stderr , "fill ica %x -> update %x\n" , addr , data );
+		update_cache030 (c, data, tag, lws);
+	}
+	if ((regs.cacr & 0x11) == 0x11 && lws == 0 && !c->valid[1] && !c->valid[2] && !c->valid[3] && ce_banktype[addr >> 16] == CE_MEMBANK_FAST32) {
+//fprintf ( stderr , "fill ica %x -> burst %x\n" , addr , data );
+		// do burst fetch if cache enabled, not frozen, all slots invalid, no chip ram
+		c->data[1] = get_longi (addr + 4);
+		c->data[2] = get_longi (addr + 8);
+		c->data[3] = get_longi (addr + 12);
+		if (currprefs.cpu_cycle_exact)
+			do_cycles_ce020_mem (3 * (CPU020_MEM_CYCLE - 1), c->data[3]);
+		c->valid[1] = c->valid[2] = c->valid[3] = true;
+	}
+	regs.cacheholdingaddr020 = addr;
+	regs.cacheholdingdata020 = data;
+//fprintf ( stderr , "fill ica %x -> miss %x\n" , addr , regs.cacheholdingdata020 );
+#ifdef WINUAE_FOR_HATARI
+	CpuInstruction.I_Cache_miss++;
+#endif
+}
+
+STATIC_INLINE bool cancache030 (uaecptr addr)
+{
+//return false;
+	return ce_cachable[addr >> 16] != 0;
+}
+
+// and finally the worst part, 68030 data cache..
+static void write_dcache030x (uaecptr addr, uae_u32 val, int size)
+{
+	struct cache030 *c1, *c2;
+	int lws1, lws2;
+	uae_u32 tag1, tag2;
+	int aligned = addr & 3;
+	int wa = regs.cacr & 0x2000;
+	int hit;
+
+	if (!(regs.cacr & 0x100)) // data cache disabled?
+		return;
+	if (!cancache030 (addr))
+		return;
+
+	c1 = getcache030 (dcaches030, addr, &tag1, &lws1);
+
+	// easy one
+	if (size == 2 && aligned == 0 && wa == 1) {
+		update_cache030 (c1, val, tag1, lws1);
+//fprintf ( stderr , "write cache1 %x %x %d tag1 %x lws1 %x tag2 %x lws2 %x ctag %x data %x\n", addr, val, size, tag1, lws1, tag2, lws2, c1->tag , c1->data[lws1] );
+		return;
+	}
+
+	hit = ( c1->tag == tag1 && c1->valid[lws1] );
+	if ( hit || wa ) {
+		if (size == 2) {
+			if (hit) {
+				c1->data[lws1] &= ~(0xffffffff >> (aligned * 8));
+				c1->data[lws1] |= val >> (aligned * 8);
+			}
+			else
+				c1->valid[lws1] = false;
+		} else if (size == 1) {
+			if (hit) {
+				c1->data[lws1] &= ~(0xffff0000 >> (aligned * 8));
+				c1->data[lws1] |= (val<<16) >> (aligned * 8);
+			}
+			else
+				c1->valid[lws1] = false;
+		} else if (size == 0) {
+			if (hit) {
+				c1->data[lws1] &= ~(0xff000000 >> (aligned * 8));
+				c1->data[lws1] |= (val<<24) >> (aligned * 8);
+			}
+			else
+				c1->valid[lws1] = false;
+		}
+	}
+
+	// do we need to update a 2nd cache entry ?
+	if ( (size == 0) || (size == 1 && aligned <= 2) || (size == 2 && aligned == 0) )
+		return;
+
+	c2 = getcache030 (dcaches030, addr + 4, &tag2, &lws2);
+//fprintf ( stderr , "write cache2 %x %x %d tag1 %x lws1 %x tag2 %x lws2 %x ctag %x data %x\n", addr, val, size, tag1, lws1, tag2, lws2, c2->tag , c2->data[lws2] );
+	hit = ( c2->tag == tag2 && c2->valid[lws2] );
+	if ( hit || wa ) {
+		if (size == 2) {
+			if (hit) {
+				c2->data[lws2] &= 0xffffffff >> (aligned * 8);
+				c2->data[lws2] |= val << ((4 - aligned) * 8);
+			}
+			else
+				c2->valid[lws2] = false;
+		} else if (size == 1) {
+			if (hit) {
+				c2->data[lws2] &= 0x00ffffff;
+				c2->data[lws2] |= val << 24;
+			}
+			else
+				c2->valid[lws2] = false;
+		}
+	}
+}
+
+void write_dcache030(uaecptr addr, uae_u32 v, int size)
+{
+//fprintf ( stderr , "write dcache %x %x %d\n" , addr , v , size );
+	write_dcache030x(addr, v, size);
+	if (currprefs.cpu_cycle_exact) {
+		if (size == 2)
+			mem_access_delay_long_write_ce020(addr, v);
+		else if (size == 1)
+			mem_access_delay_word_write_ce020(addr, v);
+		else
+			mem_access_delay_byte_write_ce020(addr, v);
+	} else {
+		if (size == 2)
+			put_long(addr, v);
+		else if (size == 1)
+			put_word(addr, v);
+		else
+			put_byte(addr, v);
+	}
+}
+
+// [HATARI] Define next line to check for 68030 data cache mismatch after every write
+//#define WINUAE_FOR_HATARI_DEBUG_CACHE
+#ifdef WINUAE_FOR_HATARI_DEBUG_CACHE
+uae_u32 read_dcache030_0 (uaecptr addr, int size);
+uae_u32 read_dcache030 (uaecptr addr, int size)
+{
+  uae_u32 v;
+
+  v = read_dcache030_0 ( addr , size );
+  if (!(regs.cacr & 0x100) || !cancache030 (addr))
+    return v;
+  if ( ( ( size==2 ) && ( v != get_long ( addr ) ) )
+    || ( ( size==1 ) && ( (v&0xffff) != (get_word ( addr ) & 0xffff) ) )
+    || ( ( size==0 ) && ( (v&0xff) != (get_byte ( addr ) & 0xff ) ) ) )
+    fprintf ( stderr , "d-cache mismatch pc=%x addr=%x size=%d cache=%x != mem=%x, d-cache error ?\n" , m68k_getpc(), addr, size, v , get_long(addr) );
+  return v;
+}
+uae_u32 read_dcache030_0 (uaecptr addr, int size)
+#else
+uae_u32 read_dcache030 (uaecptr addr, int size)
+#endif
+{
+	struct cache030 *c1, *c2;
+	int lws1, lws2;
+	uae_u32 tag1, tag2;
+	int aligned = addr & 3;
+	uae_u32 v1, v2;
+
+	if (!(regs.cacr & 0x100) || !cancache030 (addr)) { // data cache disabled?
+		if (currprefs.cpu_cycle_exact) {
+			if (size == 2)
+				return mem_access_delay_long_read_ce020 (addr);
+			else if (size == 1)
+				return mem_access_delay_word_read_ce020 (addr);
+			else
+				return mem_access_delay_byte_read_ce020 (addr);
+		} else {
+			if (size == 2)
+				return get_long (addr);
+			else if (size == 1)
+				return get_word (addr);
+			else
+				return get_byte (addr);
+		}
+	}
+	c1 = getcache030 (dcaches030, addr, &tag1, &lws1);
+	addr &= ~3;
+	if (!c1->valid[lws1] || c1->tag != tag1) {
+		v1 = currprefs.cpu_cycle_exact ? mem_access_delay_long_read_ce020 (addr) : get_long (addr);
+		update_cache030 (c1, v1, tag1, lws1);
+//fprintf ( stderr , "read cache %x %x %d tag1 %x lws1 %x tag2 %x lws2 %x ref %x\n", addr, v1, size, tag1, lws1, tag2, lws2 , get_long (0x1f81ec) );
+#ifdef WINUAE_FOR_HATARI
+		CpuInstruction.D_Cache_miss++;
+#endif
+	} else {
+		v1 = c1->data[lws1];
+#ifndef WINUAE_FOR_HATARI
+		if (uae_boot_rom_type > 0) {
+			// this check and fix is needed for UAE filesystem handler because it runs in host side and in
+			// separate thread. No way to access via cache without locking that would cause major slowdown
+			// and unneeded complexity
+			uae_u32 tv = get_long(addr);
+			if (tv != v1) {
+				write_log(_T("data cache mismatch %d %d %08x %08x != %08x %08x %d PC=%08x\n"),
+					size, aligned, addr, tv, v1, tag1, lws1, M68K_GETPC);
+				v1 = tv;
+			}
+		}
+#else
+		CpuInstruction.D_Cache_hit++;
+#endif
+	}
+
+	// only one long fetch needed?
+	if (size == 0) {
+		v1 >>= (3 - aligned) * 8;
+		return v1;
+	} else if (size == 1 && aligned <= 2) {
+		v1 >>= (2 - aligned) * 8;
+		return v1;
+	} else if (size == 2 && aligned == 0) {
+		if ((regs.cacr & 0x1100) == 0x1100 && lws1 == 0 && !c1->valid[1] && !c1->valid[2] && !c1->valid[3] && ce_banktype[addr >> 16] == CE_MEMBANK_FAST32) {
+			// do burst fetch if cache enabled, not frozen, all slots invalid, no chip ram
+			c1->data[1] = get_long (addr + 4);
+			c1->data[2] = get_long (addr + 8);
+			c1->data[3] = get_long (addr + 12);
+			do_cycles_ce020_mem (3 * (CPU020_MEM_CYCLE - 1), c1->data[3]);
+			c1->valid[1] = c1->valid[2] = c1->valid[3] = true;
+		}
+		return v1;
+	}
+	// no, need another one
+	addr += 4;
+	c2 = getcache030 (dcaches030, addr, &tag2, &lws2);
+	if (!c2->valid[lws2] || c2->tag != tag2) {
+		v2 = currprefs.cpu_cycle_exact ? mem_access_delay_long_read_ce020 (addr) : get_long (addr);
+		update_cache030 (c2, v2, tag2, lws2);
+//fprintf ( stderr , "read cache %x %x %d tag1 %x lws1 %x tag2 %x lws2 %x\n", addr, v1, size, tag1, lws1, tag2, lws2 );
+#ifdef WINUAE_FOR_HATARI
+		CpuInstruction.D_Cache_miss++;
+#endif
+	} else {
+		v2 = c2->data[lws2];
+#ifndef WINUAE_FOR_HATARI
+		if (uae_boot_rom_type > 0) {
+			uae_u32 tv = get_long(addr);
+			if (tv != v2) {
+				write_log (_T("data cache mismatch %d %d %08x %08x != %08x %08x %d PC=%08x\n"),
+					size, aligned, addr, get_long (addr), v2, tag2, lws2, M68K_GETPC);
+				v2 = tv;
+			}
+		}
+#else
+		CpuInstruction.D_Cache_hit++;
+#endif
+	} 
+
+	if (size == 1 && aligned == 3)
+		return (v1 << 8) | (v2 >> 24);
+	else if (size == 2 && aligned == 1)
+		return (v1 << 8) | (v2 >> 24);
+	else if (size == 2 && aligned == 2)
+		return (v1 << 16) | (v2 >> 16);
+	else if (size == 2 && aligned == 3)
+		return (v1 << 24) | (v2 >> 8);
+
+	write_log (_T("dcache030 weirdness!?\n"));
+	return 0;
+}
+
+uae_u32 get_word_ce030_prefetch (int o)
+{
+	uae_u32 pc = m68k_getpc () + o;
+	uae_u32 v;
+
+	if (pc & 2) {
+		v = regs.prefetch020[0] & 0xffff;
+#if MORE_ACCURATE_68020_PIPELINE
+		pipeline_020(regs.prefetch020[1], pc);
+#endif
+		regs.prefetch020[0] = regs.prefetch020[1];
+		// branch instruction detected in pipeline: stop fetches until branch executed.
+		if (!MORE_ACCURATE_68020_PIPELINE || regs.pipeline_stop >= 0) {
+			fill_icache030 (pc + 2 + 4);
+			regs.prefetch020[1] = regs.cacheholdingdata020;
+		}
+	} else {
+		v = regs.prefetch020[0] >> 16;
+#if MORE_ACCURATE_68020_PIPELINE
+		pipeline_020(regs.prefetch020[1] >> 16, pc);
+#endif
+	}
+	do_cycles_ce020_internal (2);
+	return v;
+}
+
+uae_u32 get_word_030_prefetch(int o)
+{
+	uae_u32 pc = m68k_getpc() + o;
+	uae_u32 v;
+
+	if (pc & 2) {
+		v = regs.prefetch020[0] & 0xffff;
+#if MORE_ACCURATE_68020_PIPELINE
+		pipeline_020(regs.prefetch020[1], pc);
+#endif
+		regs.prefetch020[0] = regs.prefetch020[1];
+		// branch instruction detected in pipeline: stop fetches until branch executed.
+		if (!MORE_ACCURATE_68020_PIPELINE || regs.pipeline_stop >= 0) {
+			fill_icache030(pc + 2 + 4);
+			regs.prefetch020[1] = regs.cacheholdingdata020;
+		}
+	} else {
+		v = regs.prefetch020[0] >> 16;
+#if MORE_ACCURATE_68020_PIPELINE
+		pipeline_020(regs.prefetch020[1] >> 16, pc);
+#endif
+	}
+	return v;
+}
+
+uae_u32 get_word_icache030(uaecptr addr)
+{
+	fill_icache030(addr);
+	return regs.cacheholdingdata020 >> ((addr & 2) ? 0 : 16);
+}
+uae_u32 get_long_icache030(uaecptr addr)
+{
+	uae_u32 v;
+	fill_icache030(addr);
+	if ((addr & 2) == 0)
+		return regs.cacheholdingdata020;
+	v = regs.cacheholdingdata020 << 16;
+	fill_icache030(addr + 4);
+	v |= regs.cacheholdingdata020 >> 16;
+	return v;
+}
+
+uae_u32 fill_icache040(uae_u32 addr)
+{
+	int index, i, lws;
+	uae_u32 tag;
+	struct cache040 *c;
+	int line;
+
+	if (!(regs.cacr & 0x8000)) {
+		uae_u32 addr2 = addr & ~15;
+		lws = (addr >> 2) & 3;
+		addr &= ~3;
+		if (regs.prefetch020addr == addr2)
+			return regs.prefetch020[lws];
+		regs.prefetch020addr = addr2;
+		if (currprefs.cpu_cycle_exact) {
+			regs.prefetch020[0] = mem_access_delay_longi_read_ce020(addr2 +  0);
+			regs.prefetch020[1] = mem_access_delay_longi_read_ce020(addr2 +  4);
+			regs.prefetch020[2] = mem_access_delay_longi_read_ce020(addr2 +  8);
+			regs.prefetch020[3] = mem_access_delay_longi_read_ce020(addr2 + 12);
+		} else {
+			regs.prefetch020[0] = get_longi(addr2 +  0);
+			regs.prefetch020[1] = get_longi(addr2 +  4);
+			regs.prefetch020[2] = get_longi(addr2 +  8);
+			regs.prefetch020[3] = get_longi(addr2 + 12);
+			x_do_cycles(4 * cpucycleunit);
+		}
+		return regs.prefetch020[lws];
+	}
+
+	index = (addr >> 4) & (CACHESETS040 - 1);
+	tag = regs.s | (addr & ~((CACHESETS040 << 4) - 1));
+	lws = (addr >> 2) & 3;
+	addr &= ~15;
+	c = &icaches040[index];
+	for (i = 0; i < CACHELINES040; i++) {
+		if (c->valid[i] && c->tag[i] == tag) {
+			// cache hit
+			icachelinecnt++;
+			x_do_cycles(1 * cpucycleunit);
+#ifdef WINUAE_FOR_HATARI
+			CpuInstruction.I_Cache_hit++;
+#endif
+			return c->data[i][lws];
+		}
+	}
+	// cache miss
+	if (c->valid[0] && c->valid[1] && c->valid[2] && c->valid[3]) {
+		line = (icachelinecnt >> 1) & (CACHELINES040 - 1);
+	}
+	else {
+		for (line = 0; line < CACHELINES040; line++) {
+			if (c->valid[line] == false)
+				break;
+		}
+	}
+	c->tag[line] = tag;
+	c->valid[line] = true;
+	if (currprefs.cpu_cycle_exact) {
+		c->data[line][0] = mem_access_delay_longi_read_ce020(addr +  0);
+		c->data[line][1] = mem_access_delay_longi_read_ce020(addr +  4);
+		c->data[line][2] = mem_access_delay_longi_read_ce020(addr +  8);
+		c->data[line][3] = mem_access_delay_longi_read_ce020(addr + 12);
+	} else {
+		c->data[line][0] = get_longi(addr +  0);
+		c->data[line][1] = get_longi(addr +  4);
+		c->data[line][2] = get_longi(addr +  8);
+		c->data[line][3] = get_longi(addr + 12);
+		x_do_cycles(4 * cpucycleunit);
+	}
+#ifdef WINUAE_FOR_HATARI
+	CpuInstruction.I_Cache_miss++;
+#endif
+	return c->data[line][lws];
+}
+
+#if 0
+static bool is_dcache040(uae_u32 addr)
+{
+	int index, i, lws;
+	uae_u32 tag;
+	struct cache040 *c;
+
+	addr &= ~15;
+	index = (addr >> 4) & (CACHESETS040 - 1);
+	tag = regs.s | (addr & ~((CACHESETS040 << 4) - 1));
+	lws = (addr >> 2) & 3;
+	c = &dcaches040[index];
+	for (i = 0; i < CACHELINES040; i++) {
+		if (c->valid[i] && c->tag[i] == tag) {
+			return true;
+		}
+	}
+	return false;
+}
+
+uae_u32 read_dcache040(uae_u32 addr)
+{
+	int index, i, lws;
+	uae_u32 tag;
+	struct cache040 *c;
+	int line;
+
+	addr &= ~15;
+	index = (addr >> 4) & (CACHESETS040 - 1);
+	tag = regs.s | (addr & ~((CACHESETS040 << 4) - 1));
+	lws = (addr >> 2) & 3;
+	c = &dcaches040[index];
+	for (i = 0; i < CACHELINES040; i++) {
+		if (c->valid[i] && c->tag[i] == tag) {
+			// cache hit
+			dcachelinecnt++;
+			return c->data[i][lws];
+		}
+	}
+	// cache miss
+	if (c->valid[0] && c->valid[1] && c->valid[2] && c->valid[3]) {
+		line = (icachelinecnt >> 1) & (CACHELINES040 - 1);
+		for (i = 0; i < 4; i++) {
+			if (c->dirty[line][i]) {
+				c->dirty[line][i] = false;
+				mem_access_delay_long_write_ce020(addr + i * 4, c->data[line][i]);
+			}
+		}
+	}
+	else {
+		for (line = 0; line < CACHELINES040; line++) {
+			if (c->valid[line] == false)
+				break;
+		}
+	}
+	c->tag[line] = tag;
+	c->valid[line] = true;
+	c->data[line][0] = mem_access_delay_long_read_ce020(addr + 0);
+	c->data[line][1] = mem_access_delay_long_read_ce020(addr + 4);
+	c->data[line][2] = mem_access_delay_long_read_ce020(addr + 8);
+	c->data[line][3] = mem_access_delay_long_read_ce020(addr + 12);
+	regs.cacheholdingaddr020 = addr;
+}
+
+void write_dcache040(uae_u32 addr, uae_u32 val)
+{
+	int index, i, lws;
+	uae_u32 tag;
+	struct cache040 *c;
+	int line;
+
+	addr &= ~15;
+	index = (addr >> 4) & (CACHESETS040 - 1);
+	tag = regs.s | (addr & ~((CACHESETS040 << 4) - 1));
+	lws = (addr >> 2) & 3;
+	c = &dcaches040[index];
+	for (i = 0; i < CACHELINES040; i++) {
+		if (c->valid[i] && c->tag[i] == tag) {
+			// cache hit
+			dcachelinecnt++;
+			c->data[i][lws] = val;
+			mem_access_delay_long_write_ce020(addr + i * 4, c->data[i][lws]);
+			//c->dirty[i][lws] = true;
+		}
+	}
+#if 0
+	// cache miss
+	if (c->valid[0] && c->valid[1] && c->valid[2] && c->valid[3]) {
+		line = (icachelinecnt >> 1) & (CACHELINES040 - 1);
+		for (i = 0; i < 4; i++) {
+			if (c->dirty[line][i]) {
+				c->dirty[line][i] = false;
+				mem_access_delay_long_write_ce020(addr + i * 4, c->data[line][i]);
+			}
+		}
+	}
+	else {
+		for (line = 0; line < CACHELINES040; line++) {
+			if (c->valid[line] == false)
+				break;
+		}
+	}
+	c->tag[line] = tag;
+	c->valid[line] = true;
+	c->data[line][0] = mem_access_delay_long_read_ce020(addr + 0);
+	c->data[line][1] = mem_access_delay_long_read_ce020(addr + 4);
+	c->data[line][2] = mem_access_delay_long_read_ce020(addr + 8);
+	c->data[line][3] = mem_access_delay_long_read_ce020(addr + 12);
+	c->data[line][lws] = val;
+	c->dirty[line][lws] = true;
+#endif
+}
+#endif
+
+// really unoptimized
+uae_u32 get_word_icache040(uaecptr addr)
+{
+	uae_u32 v = fill_icache040(addr);
+	return v >> ((addr & 2) ? 0 : 16);
+}
+uae_u32 get_long_icache040(uaecptr addr)
+{
+	uae_u32 v1, v2;
+	v1 = fill_icache040(addr);
+	if ((addr & 2) == 0)
+		return v1;
+	v2 = fill_icache040(addr + 4);
+	return (v2 >> 16) | (v1 << 16);
+}
+uae_u32 get_ilong_cache_040(int o)
+{
+	return get_long_icache040(m68k_getpci() + o);
+}
+uae_u32 get_iword_cache_040(int o)
+{
+	return get_word_icache040(m68k_getpci() + o);
+}
+
+STATIC_INLINE bool nocache040(uaecptr addr)
+{
+	if (!currprefs.cpu_cycle_exact)
+		return false;
+	if (!(regs.cacr & 0x80000000))
+		return true;
+	if (addr >= 0xd80000 && addr < 0xc00000)
+		return true;
+	if (addr >= 0xe80000 && addr < 0xf00000)
+		return true;
+	return false;
+}
+
+void put_long_cache_040(uaecptr addr, uae_u32 v)
+{
+#if 1
+	if (nocache040(addr))
+		mem_access_delay_long_write_ce020(addr, v);
+	else
+		put_long(addr, v);
+#else
+	if ((addr & 2) == 0) {
+		if (is_dcache040(addr))
+			write_dcache040(addr, v);
+		else if (currprefs.cpu_cycle_exact)
+			mem_access_delay_long_write_ce020(addr, v);
+		else
+			put_long(addr, v);
+	} else {
+		uae_u32 vp;
+		if (is_dcache040(addr)) {
+			vp = read_dcache040(addr);
+			vp &= 0xffff0000;
+			vp |= v >> 16;
+			write_dcache040(addr, vp);
+		} else if (currprefs.cpu_cycle_exact) {
+			mem_access_delay_word_write_ce020(addr + 0, v >> 16);
+		} else {
+			put_word(addr + 0, v >> 16);
+		}
+		if (is_dcache040(addr + 4)) {
+			vp = read_dcache040(addr + 4);
+			vp &= 0x0000ffff;
+			vp |= v << 16;
+			write_dcache040(addr + 4, vp);
+		} else if (currprefs.cpu_cycle_exact) {
+			mem_access_delay_word_write_ce020(addr + 2, v);
+		} else {
+			put_word(addr + 2, v);
+		}
+	}
+#endif
+}
+void put_word_cache_040(uaecptr addr, uae_u32 v)
+{
+#if 1
+	if (nocache040(addr))
+		mem_access_delay_word_write_ce020(addr, v);
+	else
+		put_word(addr, v);
+#else
+	if (is_dcache040(addr)) {
+		uae_u32 vp;
+		vp = read_dcache040(addr);
+		if (addr & 2) {
+			vp &= 0xffff0000;
+			vp |= v & 0xffff;
+		} else {
+			vp &= 0x0000ffff;
+			vp |= v << 16;
+		}
+		write_dcache040(addr, vp);
+	} else if (currprefs.cpu_cycle_exact) {
+		mem_access_delay_word_write_ce020(addr, v);
+	} else {
+		put_word(addr, v);
+	}
+#endif
+}
+void put_byte_cache_040(uaecptr addr, uae_u32 v)
+{
+#if 1
+	if (nocache040(addr))
+		mem_access_delay_byte_write_ce020(addr, v);
+	else
+		put_byte(addr, v);
+#else
+	if (is_dcache040(addr)) {
+		uae_u32 vp;
+		uae_u32 mask = 0xff000000 >> (addr & 3);
+		vp = read_dcache040(addr);
+		vp &= ~mask;
+		vp |= (v << (3 - (addr & 3))) & mask;
+		write_dcache040(addr, vp);
+	} else if (currprefs.cpu_cycle_exact) {
+		mem_access_delay_byte_write_ce020(addr, v);
+	} else {
+		put_byte(addr, v);
+	}
+#endif
+}
+
+uae_u32 get_long_cache_040(uaecptr addr)
+{
+#if 1
+	if (nocache040(addr))
+		return mem_access_delay_long_read_ce020(addr);
+	else
+		return get_long(addr);
+#else
+	uae_u32 v1, v2;
+	v1 = read_dcache040(addr);
+	if ((addr & 2) == 0)
+		return v1;
+	v2 = read_dcache040(addr + 4);
+	return (v2 >> 16) | (v1 << 16);
+#endif
+}
+uae_u32 get_word_cache_040(uaecptr addr)
+{
+#if 1
+	if (nocache040(addr))
+		return mem_access_delay_word_read_ce020(addr);
+	else
+		return get_word(addr);
+#else
+	uae_u32 v = read_dcache040(addr);
+	return v >> ((addr & 2) ? 0 : 16);
+#endif
+}
+uae_u32 get_byte_cache_040(uaecptr addr)
+{
+#if 1
+	if (nocache040(addr))
+		return mem_access_delay_byte_read_ce020(addr);
+	else
+		return get_byte(addr);
+#else
+	uae_u32 v = read_dcache040(addr);
+	return v >> (8 * (3 - (addr & 3)));
+#endif
+}
+uae_u32 next_iword_cache040(void)
+{
+	uae_u32 r = get_word_icache040(m68k_getpci());
+	m68k_incpci(2);
+	return r;
+}
+uae_u32 next_ilong_cache040(void)
+{
+	uae_u32 r = get_long_icache040(m68k_getpci());
+	m68k_incpci(4);
+	return r;
+}
+
+void flush_dcache (uaecptr addr, int size)
+{
+	int i;
+	if (!currprefs.cpu_cycle_exact && !currprefs.cpu_compatible)
+		return;
+	if (currprefs.cpu_model >= 68030) {
+		for (i = 0; i < CACHELINES030; i++) {
+			dcaches030[i].valid[0] = 0;
+			dcaches030[i].valid[1] = 0;
+			dcaches030[i].valid[2] = 0;
+			dcaches030[i].valid[3] = 0;
+		}
+	}
+}
+
+#ifdef WINUAE_FOR_HATARI
+void flush_instr_cache (uaecptr addr, int size)
+{
+	int i;
+	if (!currprefs.cpu_cycle_exact && !currprefs.cpu_compatible)
+		return;
+	if (currprefs.cpu_model == 68020) {
+		for (i = 0; i < CACHELINES020; i++)
+			caches020[i].valid = 0;
+	}
+	else if (currprefs.cpu_model == 68030) {
+		for (i = 0; i < CACHELINES030; i++) {
+			icaches030[i].valid[0] = 0;
+			icaches030[i].valid[1] = 0;
+			icaches030[i].valid[2] = 0;
+			icaches030[i].valid[3] = 0;
+		}
+	}
+	else if (currprefs.cpu_model >= 68040) {
+		icachelinecnt = 0;
+		dcachelinecnt = 0;
+		for (i = 0; i < CACHESETS040; i++) {
+			icaches040[i].valid[0] = 0;
+			icaches040[i].valid[1] = 0;
+			icaches040[i].valid[2] = 0;
+			icaches040[i].valid[3] = 0;
+		}
+	}
+}
+#endif
+
+void fill_prefetch_030 (void)
+{
+	uaecptr pc = m68k_getpc ();
+	uaecptr pc2 = pc;
+	pc &= ~3;
+	regs.pipeline_pos = 0;
+	regs.pipeline_stop = 0;
+
+	fill_icache030 (pc);
+	if (currprefs.cpu_cycle_exact)
+		do_cycles_ce020_internal(2);
+	regs.prefetch020[0] = regs.cacheholdingdata020;
+
+	fill_icache030 (pc + 4);
+	if (currprefs.cpu_cycle_exact)
+		do_cycles_ce020_internal(2);
+	regs.prefetch020[1] = regs.cacheholdingdata020;
+
+#if MORE_ACCURATE_68020_PIPELINE
+	if (pc2 & 2) {
+		pipeline_020(regs.prefetch020[0], pc);
+		pipeline_020(regs.prefetch020[1] >> 16, pc);
+	} else {
+		pipeline_020(regs.prefetch020[0] >> 16, pc);
+		pipeline_020(regs.prefetch020[0], pc);
+	}
+#endif
+
+	if (currprefs.cpu_cycle_exact)
+		regs.irc = get_word_ce030_prefetch (0);
+	else
+		regs.irc = get_word_030_prefetch(0);
+}
+
+void fill_prefetch_020 (void)
+{
+	uaecptr pc = m68k_getpc ();
+	uaecptr pc2 = pc;
+	pc &= ~3;
+	uae_u32 (*fetch)(uaecptr) = currprefs.cpu_cycle_exact ? mem_access_delay_longi_read_ce020 : get_longi;
+	regs.pipeline_pos = 0;
+	regs.pipeline_stop = 0;
+	regs.pipeline_r8[0] = regs.pipeline_r8[1] = -1;
+
+	fill_icache020 (pc, fetch);
+	if (currprefs.cpu_cycle_exact)
+		do_cycles_ce020_internal(2);
+	regs.prefetch020[0] = regs.cacheholdingdata020;
+
+	fill_icache020 (pc + 4, fetch);
+	if (currprefs.cpu_cycle_exact)
+		do_cycles_ce020_internal(2);
+	regs.prefetch020[1] = regs.cacheholdingdata020;
+
+#if MORE_ACCURATE_68020_PIPELINE
+	if (pc2 & 2) {
+		pipeline_020(regs.prefetch020[0], pc);
+		pipeline_020(regs.prefetch020[1] >> 16, pc);
+	} else {
+		pipeline_020(regs.prefetch020[0] >> 16, pc);
+		pipeline_020(regs.prefetch020[0], pc);
+	}
+#endif
+
+	if (currprefs.cpu_cycle_exact)
+		regs.irc = get_word_ce020_prefetch (0);
+	else
+		regs.irc = get_word_020_prefetch (0);
+}
+
+void fill_prefetch (void)
+{
+	regs.pipeline_pos = 0;
+	if (currprefs.cachesize)
+		return;
+	if (!currprefs.cpu_compatible)
+		return;
+	if (currprefs.cpu_model >= 68040) {
+		if (currprefs.cpu_compatible || currprefs.cpu_cycle_exact) {
+			fill_icache040(m68k_getpc() + 16);
+			fill_icache040(m68k_getpc());
+		}
+	} else if (currprefs.cpu_model == 68020) {
+		fill_prefetch_020 ();
+	} else if (currprefs.cpu_model == 68030) {
+		fill_prefetch_030 ();
+	} else if (currprefs.cpu_model <= 68010) {
+		uaecptr pc = m68k_getpc ();
+		regs.ir = x_get_word (pc);
+		regs.irc = x_get_word (pc + 2);
+	}
+}
+
diff --git a/src/cpu/newcpu.h b/src/cpu/newcpu.h
new file mode 100644
index 0000000..27f6e04
--- /dev/null
+++ b/src/cpu/newcpu.h
@@ -0,0 +1,718 @@
+/*
+* UAE - The Un*x Amiga Emulator
+*
+* MC68000 emulation
+*
+* Copyright 1995 Bernd Schmidt
+*/
+
+#ifndef NEWCPU_H
+#define NEWCPU_H
+
+#include "readcpu.h"
+#include "m68k.h"
+#include "compat.h"
+#include "maccess.h"
+#include "events.h"
+#include "memory.h"
+#include "custom.h"
+
+/* Possible exceptions sources for M68000_Exception() and Exception() */
+// TODO : remove when not used anymore in m68000.c
+#define M68000_EXC_SRC_CPU	1	/* Direct CPU exception */
+#define M68000_EXC_SRC_AUTOVEC	2	/* Auto-vector exception (e.g. VBL) */
+#define M68000_EXC_SRC_INT_MFP	3	/* MFP interrupt exception */
+#define M68000_EXC_SRC_INT_DSP	4	/* DSP interrupt exception */
+
+
+/* Special flags */
+#define SPCFLAG_DEBUGGER 1
+#define SPCFLAG_STOP 2
+#define SPCFLAG_BUSERROR 4
+#define SPCFLAG_INT 8
+#define SPCFLAG_BRK 0x10
+#define SPCFLAG_EXTRA_CYCLES 0x20
+#define SPCFLAG_TRACE 0x40
+#define SPCFLAG_DOTRACE 0x80
+#define SPCFLAG_DOINT 0x100
+#define SPCFLAG_MFP 0x200
+#define SPCFLAG_EXEC 0x400
+#define SPCFLAG_MODE_CHANGE 0x800
+#define SPCFLAG_DSP 0x1000
+
+
+#ifdef WITH_SOFTFLOAT
+#include 
+#endif
+
+#ifndef SET_CFLG
+
+#define SET_CFLG(x) (CFLG() = (x))
+#define SET_NFLG(x) (NFLG() = (x))
+#define SET_VFLG(x) (VFLG() = (x))
+#define SET_ZFLG(x) (ZFLG() = (x))
+#define SET_XFLG(x) (XFLG() = (x))
+
+#define GET_CFLG() CFLG()
+#define GET_NFLG() NFLG()
+#define GET_VFLG() VFLG()
+#define GET_ZFLG() ZFLG()
+#define GET_XFLG() XFLG()
+
+#define CLEAR_CZNV() do { \
+	SET_CFLG (0); \
+	SET_ZFLG (0); \
+	SET_NFLG (0); \
+	SET_VFLG (0); \
+} while (0)
+
+#define COPY_CARRY() (SET_XFLG (GET_CFLG ()))
+#endif
+
+extern const int areg_byteinc[];
+extern const int imm8_table[];
+
+extern int movem_index1[256];
+extern int movem_index2[256];
+extern int movem_next[256];
+
+#ifdef FPUEMU
+extern int fpp_movem_index1[256];
+extern int fpp_movem_index2[256];
+extern int fpp_movem_next[256];
+#endif
+
+extern int bus_error_offset;
+
+typedef uae_u32 REGPARAM3 cpuop_func (uae_u32) REGPARAM;
+typedef void REGPARAM3 cpuop_func_ce (uae_u32) REGPARAM;
+
+struct cputbl {
+	cpuop_func *handler;
+	uae_u16 opcode;
+	uae_s8 length;
+	uae_s8 disp020[2];
+	uae_u8 branch;
+};
+
+#ifdef JIT
+typedef uae_u32 REGPARAM3 compop_func (uae_u32) REGPARAM;
+
+struct comptbl {
+	compop_func *handler;
+	uae_u32 opcode;
+	int specific;
+};
+#endif
+
+extern uae_u32 REGPARAM3 op_illg (uae_u32) REGPARAM;
+extern void REGPARAM3 op_unimpl (uae_u16) REGPARAM;
+
+typedef uae_u8 flagtype;
+
+#ifdef FPUEMU
+
+#ifdef USE_LONG_DOUBLE
+typedef long double fptype;
+#define LDPTR tbyte ptr
+#else
+typedef double fptype;
+#define LDPTR qword ptr
+#endif
+#endif
+
+#define MAX68020CYCLES 4
+
+#define CPU_PIPELINE_MAX 4
+#define CPU000_MEM_CYCLE 4
+#define CPU000_CLOCK_MULT 2
+#define CPU020_MEM_CYCLE 3
+#define CPU020_CLOCK_MULT 4
+
+#define CACHELINES020 64
+struct cache020
+{
+	uae_u32 data;
+	uae_u32 tag;
+	bool valid;
+};
+
+#define CACHELINES030 16
+struct cache030
+{
+	uae_u32 data[4];
+	bool valid[4];
+	uae_u32 tag;
+};
+
+#define CACHESETS040 64
+#define CACHELINES040 4
+struct cache040
+{
+	uae_u32 data[CACHELINES040][4];
+	bool dirty[CACHELINES040][4];
+	bool valid[CACHELINES040];
+	uae_u32 tag[CACHELINES040];
+};
+
+struct mmufixup
+{
+    int reg;
+    uae_u32 value;
+};
+extern struct mmufixup mmufixup[2];
+
+typedef struct
+{
+	fptype fp;
+#ifdef WITH_SOFTFLOAT
+	floatx80 fpx;
+#endif
+} fpdata;
+
+struct regstruct
+{
+	uae_u32 regs[16];
+
+	uae_u32 pc;
+	uae_u8 *pc_p;
+	uae_u8 *pc_oldp;
+	uae_u16 opcode;
+	uae_u32 instruction_pc;
+
+	uae_u16 irc, ir, db;
+	uae_u32 spcflags;
+	uae_u32 last_prefetch;
+	uae_u32 chipset_latch_rw;
+	uae_u32 chipset_latch_read;
+	uae_u32 chipset_latch_write;
+
+	uaecptr usp, isp, msp;
+	uae_u16 sr;
+	flagtype t1;
+	flagtype t0;
+	flagtype s;
+	flagtype m;
+	flagtype x;
+	flagtype stopped;
+	int halted;
+	int exception;
+	int intmask;
+	int ipl, ipl_pin;
+
+	uae_u32 vbr, sfc, dfc;
+
+#ifdef FPUEMU
+	fpdata fp[8];
+	fpdata fp_result;
+	uae_u32 fp_result_status;
+	uae_u32 fpcr, fpsr, fpiar;
+	uae_u32 fpu_state;
+	uae_u32 fpu_exp_state;
+	fpdata exp_src1, exp_src2;
+	uae_u32 exp_pack[3];
+	uae_u16 exp_opcode, exp_extra, exp_type;
+	uae_u16 exp_size;
+	bool fp_exception;
+	bool fp_branch;
+#endif
+#ifndef CPUEMU_68000_ONLY
+	uae_u32 cacr, caar;
+	uae_u32 itt0, itt1, dtt0, dtt1;
+	uae_u32 tcr, mmusr, urp, srp, buscr;
+	uae_u32 mmu_fslw;
+	uae_u32 mmu_fault_addr, mmu_effective_addr;
+	uae_u16 mmu_ssw;
+	uae_u32 wb2_address;
+	uae_u32 wb3_data;
+	uae_u8 wb3_status, wb2_status;
+	int mmu_enabled;
+	int mmu_page_size;
+#endif
+
+	uae_u32 pcr;
+	uae_u32 address_space_mask;
+
+	uae_u32 prefetch020[CPU_PIPELINE_MAX];
+	uae_u32 prefetch020addr;
+	uae_u32 cacheholdingdata020;
+	uae_u32 cacheholdingaddr020;
+	int pipeline_pos;
+	int pipeline_r8[2];
+	int pipeline_stop;
+	int ce020memcycles;
+	int ce020extracycles;
+	bool ce020memcycle_data;
+	int ce020_tail;
+	frame_time_t ce020_tail_cycles;
+	int memory_waitstate_cycles;
+};
+
+extern struct regstruct regs;
+
+#define MAX_CPUTRACESIZE 128
+struct cputracememory
+{
+	uae_u32 addr;
+	uae_u32 data;
+	int mode;
+};
+
+struct cputracestruct
+{
+	uae_u32 regs[16];
+	uae_u32 usp, isp, pc;
+	uae_u16 ir, irc, sr, opcode;
+	int intmask, stopped, state;
+
+	uae_u32 msp, vbr;
+	uae_u32 cacr, caar;
+	uae_u32 prefetch020[CPU_PIPELINE_MAX];
+	uae_u32 prefetch020addr;
+	uae_u32 cacheholdingdata020;
+	uae_u32 cacheholdingaddr020;
+	struct cache020 caches020[CACHELINES020];
+
+	uae_u32 startcycles;
+	int needendcycles;
+	int memoryoffset;
+	int cyclecounter, cyclecounter_pre, cyclecounter_post;
+	int readcounter, writecounter;
+	struct cputracememory ctm[MAX_CPUTRACESIZE];
+};
+
+STATIC_INLINE uae_u32 munge24 (uae_u32 x)
+{
+	return x & regs.address_space_mask;
+}
+
+extern int mmu_enabled, mmu_triggered;
+extern int cpu_cycles;
+extern int cpucycleunit;
+extern int m68k_pc_indirect;
+STATIC_INLINE void set_special (uae_u32 x)
+{
+	regs.spcflags |= x;
+	cycles_do_special ();
+}
+
+STATIC_INLINE void unset_special (uae_u32 x)
+{
+	regs.spcflags &= ~x;
+}
+
+#define m68k_dreg(r,num) ((r).regs[(num)])
+#define m68k_areg(r,num) (((r).regs + 8)[(num)])
+
+extern uae_u32(*x_prefetch)(int);
+extern uae_u32(*x_get_byte)(uaecptr addr);
+extern uae_u32(*x_get_word)(uaecptr addr);
+extern uae_u32(*x_get_long)(uaecptr addr);
+extern void(*x_put_byte)(uaecptr addr, uae_u32 v);
+extern void(*x_put_word)(uaecptr addr, uae_u32 v);
+extern void(*x_put_long)(uaecptr addr, uae_u32 v);
+extern uae_u32(*x_next_iword)(void);
+extern uae_u32(*x_next_ilong)(void);
+extern uae_u32(*x_get_ilong)(int);
+extern uae_u32(*x_get_iword)(int);
+extern uae_u32(*x_get_ibyte)(int);
+
+extern uae_u32(*x_cp_get_byte)(uaecptr addr);
+extern uae_u32(*x_cp_get_word)(uaecptr addr);
+extern uae_u32(*x_cp_get_long)(uaecptr addr);
+extern void(*x_cp_put_byte)(uaecptr addr, uae_u32 v);
+extern void(*x_cp_put_word)(uaecptr addr, uae_u32 v);
+extern void(*x_cp_put_long)(uaecptr addr, uae_u32 v);
+extern uae_u32(*x_cp_next_iword)(void);
+extern uae_u32(*x_cp_next_ilong)(void);
+
+extern uae_u32(REGPARAM3 *x_cp_get_disp_ea_020)(uae_u32 base, int idx) REGPARAM;
+
+/* direct (regs.pc_p) access */
+
+STATIC_INLINE void m68k_setpc(uaecptr newpc)
+{
+	regs.pc_p = regs.pc_oldp = get_real_address(newpc);
+	regs.instruction_pc = regs.pc = newpc;
+}
+STATIC_INLINE uaecptr m68k_getpc(void)
+{
+	return (uaecptr)(regs.pc + ((uae_u8*)regs.pc_p - (uae_u8*)regs.pc_oldp));
+}
+#define M68K_GETPC m68k_getpc()
+STATIC_INLINE uaecptr m68k_getpc_p(uae_u8 *p)
+{
+	return (uaecptr)(regs.pc + ((uae_u8*)p - (uae_u8*)regs.pc_oldp));
+}
+STATIC_INLINE void m68k_incpc(int o)
+{
+	regs.pc_p += o;
+}
+
+STATIC_INLINE uae_u32 get_dibyte(int o)
+{
+	return do_get_mem_byte((uae_u8 *)((regs).pc_p + (o) + 1));
+}
+STATIC_INLINE uae_u32 get_diword(int o)
+{
+	return do_get_mem_word((uae_u16 *)((regs).pc_p + (o)));
+}
+STATIC_INLINE uae_u32 get_dilong(int o)
+{
+	return do_get_mem_long((uae_u32 *)((regs).pc_p + (o)));
+}
+STATIC_INLINE uae_u32 next_diword(void)
+{
+	uae_u32 r = do_get_mem_word((uae_u16 *)((regs).pc_p));
+	m68k_incpc(2);
+	return r;
+}
+STATIC_INLINE uae_u32 next_dilong(void)
+{
+	uae_u32 r = do_get_mem_long((uae_u32 *)((regs).pc_p));
+	m68k_incpc(4);
+	return r;
+}
+
+STATIC_INLINE void m68k_do_bsr(uaecptr oldpc, uae_s32 offset)
+{
+	m68k_areg(regs, 7) -= 4;
+	put_long(m68k_areg(regs, 7), oldpc);
+	m68k_incpc(offset);
+}
+STATIC_INLINE void m68k_do_rts(void)
+{
+	uae_u32 newpc = get_long(m68k_areg(regs, 7));
+	m68k_setpc(newpc);
+	m68k_areg(regs, 7) += 4;
+}
+
+/* indirect (regs.pc) access */
+
+STATIC_INLINE void m68k_setpci(uaecptr newpc)
+{
+	regs.instruction_pc = regs.pc = newpc;
+}
+STATIC_INLINE uaecptr m68k_getpci(void)
+{
+	return regs.pc;
+}
+STATIC_INLINE void m68k_incpci(int o)
+{
+	regs.pc += o;
+}
+
+STATIC_INLINE uae_u32 get_iibyte(int o)
+{
+	return get_wordi(m68k_getpci() + (o)) & 0xff;
+}
+STATIC_INLINE uae_u32 get_iiword(int o)
+{
+	return get_wordi(m68k_getpci() + (o));
+}
+STATIC_INLINE uae_u32 get_iilong(int o)
+{
+	return get_longi(m68k_getpci () + (o));
+}
+
+STATIC_INLINE uae_u32 next_iibyte (void)
+{
+	uae_u32 r = get_iibyte (0);
+	m68k_incpci (2);
+	return r;
+}
+STATIC_INLINE uae_u32 next_iiword (void)
+{
+	uae_u32 r = get_iiword (0);
+	m68k_incpci (2);
+	return r;
+}
+STATIC_INLINE uae_u32 next_iiwordi (void)
+{
+	uae_u32 r = get_wordi(m68k_getpci());
+	m68k_incpci (2);
+	return r;
+}
+STATIC_INLINE uae_u32 next_iilong (void)
+{
+	uae_u32 r = get_iilong(0);
+	m68k_incpci (4);
+	return r;
+}
+STATIC_INLINE uae_u32 next_iilongi (void)
+{
+	uae_u32 r = get_longi (m68k_getpci ());
+	m68k_incpci (4);
+	return r;
+}
+
+STATIC_INLINE void m68k_do_bsri(uaecptr oldpc, uae_s32 offset)
+{
+	m68k_areg(regs, 7) -= 4;
+	put_long(m68k_areg(regs, 7), oldpc);
+	m68k_incpci(offset);
+}
+STATIC_INLINE void m68k_do_rtsi(void)
+{
+	uae_u32 newpc = get_long(m68k_areg(regs, 7));
+	m68k_setpci(newpc);
+	m68k_areg(regs, 7) += 4;
+}
+
+/* indirect jit friendly versions */
+
+STATIC_INLINE uae_u32 get_iibyte_jit(int o)
+{
+	return get_wordi(m68k_getpc() + (o)) & 0xff;
+}
+STATIC_INLINE uae_u32 get_iiword_jit(int o)
+{
+	return get_wordi(m68k_getpc() + (o));
+}
+STATIC_INLINE uae_u32 get_iilong_jit(int o)
+{
+	return get_longi(m68k_getpc() + (o));
+}
+STATIC_INLINE uae_u32 next_iiword_jit(void)
+{
+	uae_u32 r = get_wordi(m68k_getpc());
+	m68k_incpc(2);
+	return r;
+}
+STATIC_INLINE uae_u32 next_iilong_jit(void)
+{
+	uae_u32 r = get_longi(m68k_getpc());
+	m68k_incpc(4);
+	return r;
+}
+STATIC_INLINE void m68k_do_bsri_jit(uaecptr oldpc, uae_s32 offset)
+{
+	m68k_areg(regs, 7) -= 4;
+	x_put_long(m68k_areg(regs, 7), oldpc);
+	m68k_incpc(offset);
+}
+STATIC_INLINE void m68k_do_rtsi_jit(void)
+{
+	uae_u32 newpc = x_get_long(m68k_areg(regs, 7));
+	m68k_setpc(newpc);
+	m68k_areg(regs, 7) += 4;
+}
+
+/* common access */
+
+STATIC_INLINE void m68k_incpc_normal(int o)
+{
+	if (m68k_pc_indirect > 0)
+		m68k_incpci(o);
+	else
+		m68k_incpc(o);
+}
+
+STATIC_INLINE void m68k_setpc_normal(uaecptr pc)
+{
+	if (m68k_pc_indirect > 0) {
+		regs.pc_p = regs.pc_oldp = 0;
+		m68k_setpci(pc);
+	} else {
+		m68k_setpc(pc);
+	}
+}
+
+extern void write_dcache030(uaecptr, uae_u32, int);
+extern uae_u32 read_dcache030(uaecptr, int);
+extern uae_u32 get_word_icache030(uaecptr addr);
+extern uae_u32 get_long_icache030(uaecptr addr);
+
+uae_u32 fill_icache040(uae_u32 addr);
+extern void put_long_cache_040(uaecptr, uae_u32);
+extern void put_word_cache_040(uaecptr, uae_u32);
+extern void put_byte_cache_040(uaecptr, uae_u32);
+extern uae_u32 get_ilong_cache_040(int);
+extern uae_u32 get_iword_cache_040(int);
+extern uae_u32 get_long_cache_040(uaecptr);
+extern uae_u32 get_word_cache_040(uaecptr);
+extern uae_u32 get_byte_cache_040(uaecptr);
+extern uae_u32 next_iword_cache040(void);
+extern uae_u32 next_ilong_cache040(void);
+extern uae_u32 get_word_icache040(uaecptr addr);
+extern uae_u32 get_long_icache040(uaecptr addr);
+
+extern void (*x_do_cycles)(unsigned long);
+extern void (*x_do_cycles_pre)(unsigned long);
+extern void (*x_do_cycles_post)(unsigned long, uae_u32);
+
+extern uae_u32 REGPARAM3 x_get_disp_ea_020 (uae_u32 base, int idx) REGPARAM;
+extern uae_u32 REGPARAM3 x_get_disp_ea_ce020 (uae_u32 base, int idx) REGPARAM;
+extern uae_u32 REGPARAM3 x_get_disp_ea_ce030 (uae_u32 base, int idx) REGPARAM;
+extern uae_u32 REGPARAM3 x_get_disp_ea_040(uae_u32 base, int idx) REGPARAM;
+extern uae_u32 REGPARAM3 x_get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM;
+extern void REGPARAM3 x_put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM;
+
+extern void m68k_setstopped (void);
+extern void m68k_resumestopped (void);
+
+extern uae_u32 REGPARAM3 get_disp_ea_020 (uae_u32 base, int idx) REGPARAM;
+extern uae_u32 REGPARAM3 get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM;
+extern void REGPARAM3 put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM;
+
+extern void m68k_disasm_ea (uaecptr addr, uaecptr *nextpc, int cnt, uae_u32 *seaddr, uae_u32 *deaddr);
+extern void m68k_disasm (uaecptr addr, uaecptr *nextpc, int cnt);
+extern void m68k_disasm_2 (TCHAR *buf, int bufsize, uaecptr addr, uaecptr *nextpc, int cnt, uae_u32 *seaddr, uae_u32 *deaddr, int safemode);
+extern void sm68k_disasm (TCHAR*, TCHAR*, uaecptr addr, uaecptr *nextpc);
+extern int get_cpu_model (void);
+#ifdef WINUAE_FOR_HATARI
+extern void m68k_disasm_file (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt);
+#endif
+
+extern void set_cpu_caches (bool flush);
+extern void flush_cpu_caches(bool flush);
+extern void flush_cpu_caches_040(uae_u16 opcode);
+extern void REGPARAM3 MakeSR (void) REGPARAM;
+extern void SetSR (uae_u16 sr);
+extern void REGPARAM3 MakeFromSR (void) REGPARAM;
+extern void REGPARAM3 Exception (int) REGPARAM;
+extern void REGPARAM3 ExceptionL (int, uaecptr) REGPARAM;
+extern void NMI (void);
+extern void NMI_delayed (void);
+extern void prepare_interrupt (uae_u32);
+extern void doint (void);
+extern void dump_counts (void);
+extern int m68k_move2c (int, uae_u32 *);
+extern int m68k_movec2 (int, uae_u32 *);
+extern bool m68k_divl (uae_u32, uae_u32, uae_u16);
+extern bool m68k_mull (uae_u32, uae_u32, uae_u16);
+extern void init_m68k (void);
+extern void init_m68k_full (void);
+extern void m68k_go (int);
+extern void m68k_dumpstate (uaecptr *);
+extern void m68k_dumpstate_2 (uaecptr, uaecptr *);
+extern void m68k_dumpstate_file (FILE *f, uaecptr *);
+extern void m68k_dumpcache (void);
+extern int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor);
+extern int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor);
+extern void divbyzero_special (bool issigned, uae_s32 dst);
+extern void m68k_do_rte (void);
+extern void protect_roms (bool);
+extern void unprotect_maprom (void);
+extern bool is_hardreset(void);
+extern bool is_keyboardreset(void);
+
+extern void mmu_op (uae_u32, uae_u32);
+extern bool mmu_op30 (uaecptr, uae_u32, uae_u16, uaecptr);
+
+extern void fpuop_arithmetic(uae_u32, uae_u16);
+extern void fpuop_dbcc(uae_u32, uae_u16);
+extern void fpuop_scc(uae_u32, uae_u16);
+extern void fpuop_trapcc(uae_u32, uaecptr, uae_u16);
+extern void fpuop_bcc(uae_u32, uaecptr, uae_u32);
+extern void fpuop_save(uae_u32);
+extern void fpuop_restore(uae_u32);
+extern uae_u32 fpp_get_fpsr (void);
+extern void fpu_reset (void);
+extern void fpux_save (int*);
+extern void fpux_restore (int*);
+extern bool fpu_get_constant(fpdata *fp, int cr);
+extern int fpp_cond(int condition);
+
+extern void exception3_read (uae_u32 opcode, uaecptr addr);
+extern void exception3_write (uae_u32 opcode, uaecptr addr);
+extern void exception3_notinstruction(uae_u32 opcode, uaecptr addr);
+extern void exception3i (uae_u32 opcode, uaecptr addr);
+extern void exception3b (uae_u32 opcode, uaecptr addr, bool w, bool i, uaecptr pc);
+extern void exception2 (uaecptr addr, bool read, int size, uae_u32 fc);
+extern void exception2_fake (uaecptr addr);
+extern void m68k_reset (void);
+extern void cpureset (void);
+extern void cpu_halt (int id);
+extern void cpu_sleep_millis(int ms);
+
+extern void fill_prefetch (void);
+extern void fill_prefetch_020 (void);
+extern void fill_prefetch_030 (void);
+
+#ifdef WINUAE_FOR_HATARI
+//extern void m68k_reset (bool hardreset);	// TODO remove
+#endif
+
+#define CPU_OP_NAME(a) op ## a
+
+/* 68060 */
+extern const struct cputbl op_smalltbl_0_ff[];
+extern const struct cputbl op_smalltbl_40_ff[];
+extern const struct cputbl op_smalltbl_24_ff[]; // CE
+extern const struct cputbl op_smalltbl_33_ff[]; // MMU
+/* 68040 */
+extern const struct cputbl op_smalltbl_1_ff[];
+extern const struct cputbl op_smalltbl_41_ff[];
+extern const struct cputbl op_smalltbl_25_ff[]; // CE
+extern const struct cputbl op_smalltbl_31_ff[]; // MMU
+/* 68030 */
+extern const struct cputbl op_smalltbl_2_ff[];
+extern const struct cputbl op_smalltbl_42_ff[];
+extern const struct cputbl op_smalltbl_22_ff[]; // prefetch
+extern const struct cputbl op_smalltbl_23_ff[]; // CE
+extern const struct cputbl op_smalltbl_32_ff[]; // MMU
+/* 68020 */
+extern const struct cputbl op_smalltbl_3_ff[];
+extern const struct cputbl op_smalltbl_43_ff[];
+extern const struct cputbl op_smalltbl_20_ff[]; // prefetch
+extern const struct cputbl op_smalltbl_21_ff[]; // CE
+/* 68010 */
+extern const struct cputbl op_smalltbl_4_ff[];
+extern const struct cputbl op_smalltbl_44_ff[];
+extern const struct cputbl op_smalltbl_11_ff[]; // prefetch
+extern const struct cputbl op_smalltbl_13_ff[]; // CE
+/* 68000 */
+extern const struct cputbl op_smalltbl_5_ff[];
+extern const struct cputbl op_smalltbl_45_ff[];
+extern const struct cputbl op_smalltbl_12_ff[]; // prefetch
+extern const struct cputbl op_smalltbl_14_ff[]; // CE
+
+extern cpuop_func *cpufunctbl[65536] ASM_SYM_FOR_FUNC ("cpufunctbl");
+
+#ifdef JIT
+extern void flush_icache(uaecptr, int);
+extern void flush_icache_hard(uaecptr, int);
+extern void compemu_reset(void);
+extern bool check_prefs_changed_comp (void);
+#else
+#define flush_icache(uaecptr, int) do {} while (0)
+#define flush_icache_hard(uaecptr, int) do {} while (0)
+#endif
+extern void flush_dcache (uaecptr, int);
+#ifdef WINUAE_FOR_HATARI
+extern void flush_instr_cache (uaecptr, int);
+#endif
+extern void flush_mmu (uaecptr, int);
+
+extern int movec_illg (int regno);
+extern uae_u32 val_move2c (int regno);
+extern void val_move2c2 (int regno, uae_u32 val);
+struct cpum2c {
+	int regno;
+	const TCHAR *regname;
+};
+extern struct cpum2c m2cregs[];
+
+extern bool is_cpu_tracer (void);
+extern bool set_cpu_tracer (bool force);
+extern bool can_cpu_tracer (void);
+
+#ifdef WINUAE_FOR_HATARI
+/*** Hatari ***/
+
+/* Family of the latest instruction executed (to check for pairing) */
+extern int OpcodeFamily;			/* see instrmnem in readcpu.h */
+
+/* How many cycles to add to the current instruction in case a "misaligned" bus acces is made */
+/* (e.g. used when addressing mode is d8(an,ix)) */
+extern int BusCyclePenalty;
+
+/* To redirect WinUAE's prints to our own file */
+extern FILE *console_out_FILE;
+
+/*** Hatari ***/
+#endif
+
+#endif
+
diff --git a/src/cpu/newcpu_common.c b/src/cpu/newcpu_common.c
new file mode 100644
index 0000000..f5c1a47
--- /dev/null
+++ b/src/cpu/newcpu_common.c
@@ -0,0 +1,1042 @@
+
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+
+#define MOVEC_DEBUG 0
+
+#include "main.h"
+#include "hatari-glue.h"
+
+#include "options_cpu.h"
+#include "memory.h"
+#include "newcpu.h"
+#include "cpummu.h"
+#include "cpummu030.h"
+#include "cpu_prefetch.h"
+
+void val_move2c2 (int regno, uae_u32 val)
+{
+	switch (regno) {
+	case 0: regs.sfc = val; break;
+	case 1: regs.dfc = val; break;
+	case 2: regs.cacr = val; break;
+	case 3: regs.tcr = val; break;
+	case 4: regs.itt0 = val; break;
+	case 5: regs.itt1 = val; break;
+	case 6: regs.dtt0 = val; break;
+	case 7: regs.dtt1 = val; break;
+	case 8: regs.buscr = val; break;
+	case 0x800: regs.usp = val; break;
+	case 0x801: regs.vbr = val; break;
+	case 0x802: regs.caar = val; break;
+	case 0x803: regs.msp = val; break;
+	case 0x804: regs.isp = val; break;
+	case 0x805: regs.mmusr = val; break;
+	case 0x806: regs.urp = val; break;
+	case 0x807: regs.srp = val; break;
+	case 0x808: regs.pcr = val; break;
+	}
+}
+
+uae_u32 val_move2c (int regno)
+{
+	switch (regno) {
+	case 0: return regs.sfc;
+	case 1: return regs.dfc;
+	case 2: return regs.cacr;
+	case 3: return regs.tcr;
+	case 4: return regs.itt0;
+	case 5: return regs.itt1;
+	case 6: return regs.dtt0;
+	case 7: return regs.dtt1;
+	case 8: return regs.buscr;
+	case 0x800: return regs.usp;
+	case 0x801: return regs.vbr;
+	case 0x802: return regs.caar;
+	case 0x803: return regs.msp;
+	case 0x804: return regs.isp;
+	case 0x805: return regs.mmusr;
+	case 0x806: return regs.urp;
+	case 0x807: return regs.srp;
+	case 0x808: return regs.pcr;
+	default: return 0;
+	}
+}
+
+#ifndef CPUEMU_68000_ONLY
+
+int movec_illg (int regno)
+{
+	int regno2 = regno & 0x7ff;
+
+	if (currprefs.cpu_model == 68060) {
+		if (regno <= 8)
+			return 0;
+		if (regno == 0x800 || regno == 0x801 ||
+			regno == 0x806 || regno == 0x807 || regno == 0x808)
+			return 0;
+		return 1;
+	} else if (currprefs.cpu_model == 68010) {
+		if (regno2 < 2)
+			return 0;
+		return 1;
+	} else if (currprefs.cpu_model == 68020) {
+		if (regno == 3)
+			return 1; /* 68040/060 only */
+		/* 4 is >=68040, but 0x804 is in 68020 */
+		if (regno2 < 4 || regno == 0x804)
+			return 0;
+		return 1;
+	} else if (currprefs.cpu_model == 68030) {
+		if (regno2 <= 2)
+			return 0;
+		if (regno == 0x803 || regno == 0x804)
+			return 0;
+		return 1;
+	} else if (currprefs.cpu_model == 68040) {
+		if (regno == 0x802)
+			return 1; /* 68020/030 only */
+		if (regno2 < 8) return 0;
+		return 1;
+	}
+	return 1;
+}
+
+int m68k_move2c (int regno, uae_u32 *regp)
+{
+#if MOVEC_DEBUG > 0
+	write_log (_T("move2c %04X <- %08X PC=%x\n"), regno, *regp, M68K_GETPC);
+#endif
+	if (movec_illg (regno)) {
+		op_illg (0x4E7B);
+		return 0;
+	} else {
+		switch (regno) {
+		case 0: regs.sfc = *regp & 7; break;
+		case 1: regs.dfc = *regp & 7; break;
+		case 2:
+			{
+				uae_u32 cacr_mask = 0;
+				if (currprefs.cpu_model == 68020)
+					cacr_mask = 0x0000000f;
+				else if (currprefs.cpu_model == 68030)
+					cacr_mask = 0x00003f1f;
+				else if (currprefs.cpu_model == 68040)
+					cacr_mask = 0x80008000;
+				else if (currprefs.cpu_model == 68060)
+					cacr_mask = 0xf8e0e000;
+				regs.cacr = *regp & cacr_mask;
+				set_cpu_caches (false);
+			}
+			break;
+			/* 68040/060 only */
+		case 3:
+			regs.tcr = *regp & (currprefs.cpu_model == 68060 ? 0xfffe : 0xc000);
+			if (currprefs.mmu_model)
+				mmu_set_tc (regs.tcr);
+			break;
+
+			/* no differences between 68040 and 68060 */
+		case 4: regs.itt0 = *regp & 0xffffe364; mmu_tt_modified (); break;
+		case 5: regs.itt1 = *regp & 0xffffe364; mmu_tt_modified (); break;
+		case 6: regs.dtt0 = *regp & 0xffffe364; mmu_tt_modified (); break;
+		case 7: regs.dtt1 = *regp & 0xffffe364; mmu_tt_modified (); break;
+			/* 68060 only */
+		case 8: regs.buscr = *regp & 0xf0000000; break;
+
+		case 0x800: regs.usp = *regp; break;
+		case 0x801: regs.vbr = *regp; break;
+		case 0x802: regs.caar = *regp; break;
+		case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg (regs, 7) = regs.msp; break;
+		case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg (regs, 7) = regs.isp; break;
+			/* 68040 only */
+		case 0x805: regs.mmusr = *regp; break;
+			/* 68040/060 */
+		case 0x806: regs.urp = *regp & 0xfffffe00; break;
+		case 0x807: regs.srp = *regp & 0xfffffe00; break;
+			/* 68060 only */
+		case 0x808:
+			{
+				uae_u32 opcr = regs.pcr;
+				regs.pcr &= ~(0x40 | 2 | 1);
+				regs.pcr |= (*regp) & (0x40 | 2 | 1);
+				if (currprefs.fpu_model <= 0)
+					regs.pcr |= 2;
+				if (((opcr ^ regs.pcr) & 2) == 2) {
+					write_log (_T("68060 FPU state: %s\n"), regs.pcr & 2 ? _T("disabled") : _T("enabled"));
+					/* flush possible already translated FPU instructions */
+					flush_icache (0, 3);
+				}
+			}
+			break;
+		default:
+			op_illg (0x4E7B);
+			return 0;
+		}
+	}
+	return 1;
+}
+
+int m68k_movec2 (int regno, uae_u32 *regp)
+{
+#if MOVEC_DEBUG > 0
+	write_log (_T("movec2 %04X PC=%x\n"), regno, M68K_GETPC);
+#endif
+	if (movec_illg (regno)) {
+		op_illg (0x4E7A);
+		return 0;
+	} else {
+		switch (regno) {
+		case 0: *regp = regs.sfc; break;
+		case 1: *regp = regs.dfc; break;
+		case 2:
+			{
+				uae_u32 v = regs.cacr;
+				uae_u32 cacr_mask = 0;
+				if (currprefs.cpu_model == 68020)
+					cacr_mask = 0x00000003;
+				else if (currprefs.cpu_model == 68030)
+					cacr_mask = 0x00003313;
+				else if (currprefs.cpu_model == 68040)
+					cacr_mask = 0x80008000;
+				else if (currprefs.cpu_model == 68060)
+					cacr_mask = 0xf880e000;
+				*regp = v & cacr_mask;
+			}
+			break;
+		case 3: *regp = regs.tcr; break;
+		case 4: *regp = regs.itt0; break;
+		case 5: *regp = regs.itt1; break;
+		case 6: *regp = regs.dtt0; break;
+		case 7: *regp = regs.dtt1; break;
+		case 8: *regp = regs.buscr; break;
+
+		case 0x800: *regp = regs.usp; break;
+		case 0x801: *regp = regs.vbr; break;
+		case 0x802: *regp = regs.caar; break;
+		case 0x803: *regp = regs.m == 1 ? m68k_areg (regs, 7) : regs.msp; break;
+		case 0x804: *regp = regs.m == 0 ? m68k_areg (regs, 7) : regs.isp; break;
+		case 0x805: *regp = regs.mmusr; break;
+		case 0x806: *regp = regs.urp; break;
+		case 0x807: *regp = regs.srp; break;
+		case 0x808: *regp = regs.pcr; break;
+
+		default:
+			op_illg (0x4E7A);
+			return 0;
+		}
+	}
+#if MOVEC_DEBUG > 0
+	write_log (_T("-> %08X\n"), *regp);
+#endif
+	return 1;
+}
+
+#endif
+
+
+/*
+* extract bitfield data from memory and return it in the MSBs
+* bdata caches the unmodified data for put_bitfield()
+*/
+uae_u32 REGPARAM2 get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width)
+{
+	uae_u32 tmp, res, mask;
+
+	offset &= 7;
+	mask = 0xffffffffu << (32 - width);
+	switch ((offset + width + 7) >> 3) {
+	case 1:
+		tmp = get_byte (src);
+		res = tmp << (24 + offset);
+		bdata[0] = tmp & ~(mask >> (24 + offset));
+		break;
+	case 2:
+		tmp = get_word (src);
+		res = tmp << (16 + offset);
+		bdata[0] = tmp & ~(mask >> (16 + offset));
+		break;
+	case 3:
+		tmp = get_word (src);
+		res = tmp << (16 + offset);
+		bdata[0] = tmp & ~(mask >> (16 + offset));
+		tmp = get_byte (src + 2);
+		res |= tmp << (8 + offset);
+		bdata[1] = tmp & ~(mask >> (8 + offset));
+		break;
+	case 4:
+		tmp = get_long (src);
+		res = tmp << offset;
+		bdata[0] = tmp & ~(mask >> offset);
+		break;
+	case 5:
+		tmp = get_long (src);
+		res = tmp << offset;
+		bdata[0] = tmp & ~(mask >> offset);
+		tmp = get_byte (src + 4);
+		res |= tmp >> (8 - offset);
+		bdata[1] = tmp & ~(mask << (8 - offset));
+		break;
+	default:
+		/* Panic? */
+		write_log (_T("get_bitfield() can't happen %d\n"), (offset + width + 7) >> 3);
+		res = 0;
+		break;
+	}
+	return res;
+}
+/*
+* write bitfield data (in the LSBs) back to memory, upper bits
+* must be cleared already.
+*/
+void REGPARAM2 put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width)
+{
+	offset = (offset & 7) + width;
+	switch ((offset + 7) >> 3) {
+	case 1:
+		put_byte (dst, bdata[0] | (val << (8 - offset)));
+		break;
+	case 2:
+		put_word (dst, bdata[0] | (val << (16 - offset)));
+		break;
+	case 3:
+		put_word (dst, bdata[0] | (val >> (offset - 16)));
+		put_byte (dst + 2, bdata[1] | (val << (24 - offset)));
+		break;
+	case 4:
+		put_long (dst, bdata[0] | (val << (32 - offset)));
+		break;
+	case 5:
+		put_long (dst, bdata[0] | (val >> (offset - 32)));
+		put_byte (dst + 4, bdata[1] | (val << (40 - offset)));
+		break;
+	default:
+		write_log (_T("put_bitfield() can't happen %d\n"), (offset + 7) >> 3);
+		break;
+	}
+}
+
+uae_u32 REGPARAM2 x_get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width)
+{
+	uae_u32 tmp1, tmp2, res, mask;
+
+	offset &= 7;
+	mask = 0xffffffffu << (32 - width);
+	switch ((offset + width + 7) >> 3) {
+	case 1:
+		tmp1 = x_cp_get_byte (src);
+		res = tmp1 << (24 + offset);
+		bdata[0] = tmp1 & ~(mask >> (24 + offset));
+		break;
+	case 2:
+		tmp1 = x_cp_get_word (src);
+		res = tmp1 << (16 + offset);
+		bdata[0] = tmp1 & ~(mask >> (16 + offset));
+		break;
+	case 3:
+		tmp1 = x_cp_get_word (src);
+		tmp2 = x_cp_get_byte (src + 2);
+		res = tmp1 << (16 + offset);
+		bdata[0] = tmp1 & ~(mask >> (16 + offset));
+		res |= tmp2 << (8 + offset);
+		bdata[1] = tmp2 & ~(mask >> (8 + offset));
+		break;
+	case 4:
+		tmp1 = x_cp_get_long (src);
+		res = tmp1 << offset;
+		bdata[0] = tmp1 & ~(mask >> offset);
+		break;
+	case 5:
+		tmp1 = x_cp_get_long (src);
+		tmp2 = x_cp_get_byte (src + 4);
+		res = tmp1 << offset;
+		bdata[0] = tmp1 & ~(mask >> offset);
+		res |= tmp2 >> (8 - offset);
+		bdata[1] = tmp2 & ~(mask << (8 - offset));
+		break;
+	default:
+		/* Panic? */
+		write_log (_T("x_get_bitfield() can't happen %d\n"), (offset + width + 7) >> 3);
+		res = 0;
+		break;
+	}
+	return res;
+}
+
+void REGPARAM2 x_put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width)
+{
+	offset = (offset & 7) + width;
+	switch ((offset + 7) >> 3) {
+	case 1:
+		x_cp_put_byte (dst, bdata[0] | (val << (8 - offset)));
+		break;
+	case 2:
+		x_cp_put_word (dst, bdata[0] | (val << (16 - offset)));
+		break;
+	case 3:
+		x_cp_put_word (dst, bdata[0] | (val >> (offset - 16)));
+		x_cp_put_byte (dst + 2, bdata[1] | (val << (24 - offset)));
+		break;
+	case 4:
+		x_cp_put_long (dst, bdata[0] | (val << (32 - offset)));
+		break;
+	case 5:
+		x_cp_put_long (dst, bdata[0] | (val >> (offset - 32)));
+		x_cp_put_byte (dst + 4, bdata[1] | (val << (40 - offset)));
+		break;
+	default:
+		write_log (_T("x_put_bitfield() can't happen %d\n"), (offset + 7) >> 3);
+		break;
+	}
+}
+
+uae_u32 REGPARAM2 get_disp_ea_020 (uae_u32 base, int idx)
+{
+	uae_u16 dp = next_diword ();
+	int reg = (dp >> 12) & 15;
+	uae_s32 regd = regs.regs[reg];
+	if ((dp & 0x800) == 0)
+		regd = (uae_s32)(uae_s16)regd;
+	regd <<= (dp >> 9) & 3;
+	if (dp & 0x100) {
+		uae_s32 outer = 0;
+		if (dp & 0x80) base = 0;
+		if (dp & 0x40) regd = 0;
+
+		if ((dp & 0x30) == 0x20)
+			base += (uae_s32)(uae_s16) next_diword ();
+		if ((dp & 0x30) == 0x30)
+			base += next_dilong ();
+
+		if ((dp & 0x3) == 0x2)
+			outer = (uae_s32)(uae_s16) next_diword ();
+		if ((dp & 0x3) == 0x3)
+			outer = next_dilong ();
+
+		if ((dp & 0x4) == 0)
+			base += regd;
+		if (dp & 0x3)
+			base = get_long (base);
+		if (dp & 0x4)
+			base += regd;
+
+		return base + outer;
+	} else {
+		return base + (uae_s32)((uae_s8)dp) + regd;
+	}
+}
+
+uae_u32 REGPARAM2 x_get_disp_ea_020 (uae_u32 base, int idx)
+{
+	uae_u16 dp = x_next_iword ();
+	int reg = (dp >> 12) & 15;
+	int cycles = 0;
+	uae_u32 v;
+
+	uae_s32 regd = regs.regs[reg];
+	if ((dp & 0x800) == 0)
+		regd = (uae_s32)(uae_s16)regd;
+	regd <<= (dp >> 9) & 3;
+	if (dp & 0x100) {
+		uae_s32 outer = 0;
+		if (dp & 0x80)
+			base = 0;
+		if (dp & 0x40)
+			regd = 0;
+
+		if ((dp & 0x30) == 0x20) {
+			base += (uae_s32)(uae_s16) x_next_iword ();
+			cycles++;
+		}
+		if ((dp & 0x30) == 0x30) {
+			base += x_next_ilong ();
+			cycles++;
+		}
+
+		if ((dp & 0x3) == 0x2) {
+			outer = (uae_s32)(uae_s16) x_next_iword ();
+			cycles++;
+		}
+		if ((dp & 0x3) == 0x3) {
+			outer = x_next_ilong ();
+			cycles++;
+		}
+
+		if ((dp & 0x4) == 0) {
+			base += regd;
+			cycles++;
+		}
+		if (dp & 0x3) {
+			base = x_get_long (base);
+			cycles++;
+		}
+		if (dp & 0x4) {
+			base += regd;
+			cycles++;
+		}
+		v = base + outer;
+	} else {
+		v = base + (uae_s32)((uae_s8)dp) + regd;
+	}
+	if (cycles && currprefs.cpu_cycle_exact)
+		x_do_cycles (cycles * cpucycleunit);
+	return v;
+}
+
+uae_u32 REGPARAM2 x_get_disp_ea_ce030 (uae_u32 base, int idx)
+{
+	uae_u16 dp = next_iword_030ce ();
+	int reg = (dp >> 12) & 15;
+	uae_u32 v;
+
+	uae_s32 regd = regs.regs[reg];
+	if ((dp & 0x800) == 0)
+		regd = (uae_s32)(uae_s16)regd;
+	regd <<= (dp >> 9) & 3;
+	if (dp & 0x100) {
+		uae_s32 outer = 0;
+		if (dp & 0x80)
+			base = 0;
+		if (dp & 0x40)
+			regd = 0;
+
+		if ((dp & 0x30) == 0x20) {
+			base += (uae_s32)(uae_s16) next_iword_030ce ();
+		}
+		if ((dp & 0x30) == 0x30) {
+			base += next_ilong_030ce ();
+		}
+
+		if ((dp & 0x3) == 0x2) {
+			outer = (uae_s32)(uae_s16) next_iword_030ce ();
+		}
+		if ((dp & 0x3) == 0x3) {
+			outer = next_ilong_030ce ();
+		}
+
+		if ((dp & 0x4) == 0) {
+			base += regd;
+		}
+		if (dp & 0x3) {
+			base = x_get_long (base);
+		}
+		if (dp & 0x4) {
+			base += regd;
+		}
+		v = base + outer;
+	} else {
+		v = base + (uae_s32)((uae_s8)dp) + regd;
+	}
+	return v;
+}
+
+uae_u32 REGPARAM2 x_get_disp_ea_ce020 (uae_u32 base, int idx)
+{
+	uae_u16 dp = next_iword_020ce ();
+	int reg = (dp >> 12) & 15;
+	uae_u32 v;
+
+	uae_s32 regd = regs.regs[reg];
+	if ((dp & 0x800) == 0)
+		regd = (uae_s32)(uae_s16)regd;
+	regd <<= (dp >> 9) & 3;
+	if (dp & 0x100) {
+		uae_s32 outer = 0;
+		if (dp & 0x80)
+			base = 0;
+		if (dp & 0x40)
+			regd = 0;
+
+		if ((dp & 0x30) == 0x20) {
+			base += (uae_s32)(uae_s16) next_iword_020ce ();
+		}
+		if ((dp & 0x30) == 0x30) {
+			base += next_ilong_020ce ();
+		}
+
+		if ((dp & 0x3) == 0x2) {
+			outer = (uae_s32)(uae_s16) next_iword_020ce ();
+		}
+		if ((dp & 0x3) == 0x3) {
+			outer = next_ilong_020ce ();
+		}
+
+		if ((dp & 0x4) == 0) {
+			base += regd;
+		}
+		if (dp & 0x3) {
+			base = x_get_long (base);
+		}
+		if (dp & 0x4) {
+			base += regd;
+		}
+		v = base + outer;
+	} else {
+		v = base + (uae_s32)((uae_s8)dp) + regd;
+	}
+	return v;
+}
+
+uae_u32 REGPARAM2 x_get_disp_ea_040(uae_u32 base, int idx)
+{
+	uae_u16 dp = next_iword_cache040();
+	int reg = (dp >> 12) & 15;
+	uae_s32 regd = regs.regs[reg];
+	if ((dp & 0x800) == 0)
+		regd = (uae_s32)(uae_s16)regd;
+	regd <<= (dp >> 9) & 3;
+	if (dp & 0x100) {
+		uae_s32 outer = 0;
+		if (dp & 0x80) base = 0;
+		if (dp & 0x40) regd = 0;
+
+		if ((dp & 0x30) == 0x20)
+			base += (uae_s32)(uae_s16)next_iword_cache040();
+		if ((dp & 0x30) == 0x30)
+			base += next_ilong_cache040();
+
+		if ((dp & 0x3) == 0x2)
+			outer = (uae_s32)(uae_s16)next_iword_cache040();
+		if ((dp & 0x3) == 0x3)
+			outer = next_ilong_cache040();
+
+		if ((dp & 0x4) == 0)
+			base += regd;
+		if (dp & 0x3)
+			base = x_get_long(base);
+		if (dp & 0x4)
+			base += regd;
+
+		return base + outer;
+	}
+	else {
+		return base + (uae_s32)((uae_s8)dp) + regd;
+	}
+}
+
+/*
+* Compute exact number of CPU cycles taken
+* by DIVU and DIVS on a 68000 processor.
+*
+* Copyright (c) 2005 by Jorge Cwik, pasti@fxatari.com
+*
+* This is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This software is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this software; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*
+*/
+
+
+/*
+
+The routines below take dividend and divisor as parameters.
+They return 0 if division by zero, or exact number of cycles otherwise.
+
+The number of cycles returned assumes a register operand.
+Effective address time must be added if memory operand.
+
+For 68000 only (not 68010, 68012, 68020, etc).
+Probably valid for 68008 after adding the extra prefetch cycle.
+
+
+Best and worst cases for register operand:
+(Note the difference with the documented range.)
+
+
+DIVU:
+
+Overflow (always): 10 cycles.
+Worst case: 136 cycles.
+Best case: 76 cycles.
+
+
+DIVS:
+
+Absolute overflow: 16-18 cycles.
+Signed overflow is not detected prematurely.
+
+Worst case: 156 cycles.
+Best case without signed overflow: 122 cycles.
+Best case with signed overflow: 120 cycles
+
+
+*/
+
+int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor)
+{
+	int mcycles;
+	uae_u32 hdivisor;
+	int i;
+
+	if (divisor == 0)
+		return 0;
+
+	// Overflow
+	if ((dividend >> 16) >= divisor)
+		return (mcycles = 5) * 2;
+
+	mcycles = 38;
+	hdivisor = divisor << 16;
+
+	for (i = 0; i < 15; i++) {
+		uae_u32 temp;
+		temp = dividend;
+
+		dividend <<= 1;
+
+		// If carry from shift
+		if ((uae_s32)temp < 0)
+			dividend -= hdivisor;
+		else {
+			mcycles += 2;
+			if (dividend >= hdivisor) {
+				dividend -= hdivisor;
+				mcycles--;
+			}
+		}
+	}
+	return mcycles * 2;
+}
+
+int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor)
+{
+	int mcycles;
+	uae_u32 aquot;
+	int i;
+
+	if (divisor == 0)
+		return 0;
+
+	mcycles = 6;
+
+	if (dividend < 0)
+		mcycles++;
+
+	// Check for absolute overflow
+	if (((uae_u32)abs (dividend) >> 16) >= (uae_u16)abs (divisor))
+		return (mcycles + 2) * 2;
+
+	// Absolute quotient
+	aquot = (uae_u32) abs (dividend) / (uae_u16)abs (divisor);
+
+	mcycles += 55;
+
+	if (divisor >= 0) {
+		if (dividend >= 0)
+			mcycles--;
+		else
+			mcycles++;
+	}
+
+	// Count 15 msbits in absolute of quotient
+
+	for (i = 0; i < 15; i++) {
+		if ((uae_s16)aquot >= 0)
+			mcycles++;
+		aquot <<= 1;
+	}
+
+	return mcycles * 2;
+}
+
+/* 68000 Z=1. NVC=0
+ * 68020 and 68030: Signed: Z=1 NVC=0. Unsigned: V=1, N= 68040) {
+		SET_CFLG (0);
+	} else {
+		// 68000/010
+		CLEAR_CZNV ();
+	}
+}
+
+#ifndef CPUEMU_68000_ONLY
+
+STATIC_INLINE int div_unsigned (uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem)
+{
+	uae_u32 q = 0, cbit = 0;
+	int i;
+
+	if (div <= src_hi) {
+		return 1;
+	}
+	for (i = 0 ; i < 32 ; i++) {
+		cbit = src_hi & 0x80000000ul;
+		src_hi <<= 1;
+		if (src_lo & 0x80000000ul) src_hi++;
+		src_lo <<= 1;
+		q = q << 1;
+		if (cbit || div <= src_hi) {
+			q |= 1;
+			src_hi -= div;
+		}
+	}
+	*quot = q;
+	*rem = src_hi;
+	return 0;
+}
+
+bool m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra)
+{
+	if ((extra & 0x400) && currprefs.int_no_unimplemented && currprefs.cpu_model == 68060) {
+		op_unimpl (opcode);
+		return false;
+	}
+	if (src == 0) {
+		Exception (5);
+		return false;
+	}
+#if defined (uae_s64)
+	if (extra & 0x800) {
+		/* signed variant */
+		uae_s64 a = (uae_s64)(uae_s32)m68k_dreg (regs, (extra >> 12) & 7);
+		uae_s64 quot, rem;
+
+		if (extra & 0x400) {
+			a &= 0xffffffffu;
+			a |= (uae_s64)m68k_dreg (regs, extra & 7) << 32;
+		}
+
+		if (a == 0x8000000000000000 && src == ~0u) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+			SET_CFLG (0);
+		} else {
+			rem = a % (uae_s64)(uae_s32)src;
+			quot = a / (uae_s64)(uae_s32)src;
+			if ((quot & UVAL64 (0xffffffff80000000)) != 0
+				&& (quot & UVAL64 (0xffffffff80000000)) != UVAL64 (0xffffffff80000000))
+			{
+				SET_VFLG (1);
+				SET_NFLG (1);
+				SET_CFLG (0);
+			} else {
+				if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
+				SET_VFLG (0);
+				SET_CFLG (0);
+				SET_ZFLG (((uae_s32)quot) == 0);
+				SET_NFLG (((uae_s32)quot) < 0);
+				m68k_dreg (regs, extra & 7) = (uae_u32)rem;
+				m68k_dreg (regs, (extra >> 12) & 7) = (uae_u32)quot;
+			}
+		}
+	} else {
+		/* unsigned */
+		uae_u64 a = (uae_u64)(uae_u32)m68k_dreg (regs, (extra >> 12) & 7);
+		uae_u64 quot, rem;
+
+		if (extra & 0x400) {
+			a &= 0xffffffffu;
+			a |= (uae_u64)m68k_dreg (regs, extra & 7) << 32;
+		}
+		rem = a % (uae_u64)src;
+		quot = a / (uae_u64)src;
+		if (quot > 0xffffffffu) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+			SET_CFLG (0);
+		} else {
+			SET_VFLG (0);
+			SET_CFLG (0);
+			SET_ZFLG (((uae_s32)quot) == 0);
+			SET_NFLG (((uae_s32)quot) < 0);
+			m68k_dreg (regs, extra & 7) = (uae_u32)rem;
+			m68k_dreg (regs, (extra >> 12) & 7) = (uae_u32)quot;
+		}
+	}
+#else
+	if (extra & 0x800) {
+		/* signed variant */
+		uae_s32 lo = (uae_s32)m68k_dreg (regs, (extra >> 12) & 7);
+		uae_s32 hi = lo < 0 ? -1 : 0;
+		uae_s32 save_high;
+		uae_u32 quot, rem;
+		uae_u32 sign;
+
+		if (extra & 0x400) {
+			hi = (uae_s32)m68k_dreg (regs, extra & 7);
+		}
+		save_high = hi;
+		sign = (hi ^ src);
+		if (hi < 0) {
+			hi = ~hi;
+			lo = -lo;
+			if (lo == 0) hi++;
+		}
+		if ((uae_s32)src < 0) src = -src;
+		if (div_unsigned (hi, lo, src, ", &rem) ||
+			(sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
+				SET_VFLG (1);
+				SET_NFLG (1);
+				SET_CFLG (0);
+		} else {
+			if (sign & 0x80000000) quot = -quot;
+			if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
+			SET_VFLG (0);
+			SET_CFLG (0);
+			SET_ZFLG (((uae_s32)quot) == 0);
+			SET_NFLG (((uae_s32)quot) < 0);
+			m68k_dreg (regs, extra & 7) = rem;
+			m68k_dreg (regs, (extra >> 12) & 7) = quot;
+		}
+	} else {
+		/* unsigned */
+		uae_u32 lo = (uae_u32)m68k_dreg (regs, (extra >> 12) & 7);
+		uae_u32 hi = 0;
+		uae_u32 quot, rem;
+
+		if (extra & 0x400) {
+			hi = (uae_u32)m68k_dreg (regs, extra & 7);
+		}
+		if (div_unsigned (hi, lo, src, ", &rem)) {
+			SET_VFLG (1);
+			SET_NFLG (1);
+			SET_CFLG (0);
+		} else {
+			SET_VFLG (0);
+			SET_CFLG (0);
+			SET_ZFLG (((uae_s32)quot) == 0);
+			SET_NFLG (((uae_s32)quot) < 0);
+			m68k_dreg (regs, extra & 7) = rem;
+			m68k_dreg (regs, (extra >> 12) & 7) = quot;
+		}
+	}
+#endif
+	return true;
+}
+
+STATIC_INLINE void mul_unsigned (uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
+{
+	uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
+	uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
+	uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
+	uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
+	uae_u32 lo;
+
+	lo = r0 + ((r1 << 16) & 0xffff0000ul);
+	if (lo < r0) r3++;
+	r0 = lo;
+	lo = r0 + ((r2 << 16) & 0xffff0000ul);
+	if (lo < r0) r3++;
+	r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
+	*dst_lo = lo;
+	*dst_hi = r3;
+}
+
+bool m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
+{
+	if ((extra & 0x400) && currprefs.int_no_unimplemented && currprefs.cpu_model == 68060) {
+		op_unimpl (opcode);
+		return false;
+	}
+#if defined (uae_s64)
+	if (extra & 0x800) {
+		/* signed variant */
+		uae_s64 a = (uae_s64)(uae_s32)m68k_dreg (regs, (extra >> 12) & 7);
+
+		a *= (uae_s64)(uae_s32)src;
+		SET_VFLG (0);
+		SET_CFLG (0);
+		SET_ZFLG (a == 0);
+		SET_NFLG (a < 0);
+		if (extra & 0x400)
+			m68k_dreg (regs, extra & 7) = (uae_u32)(a >> 32);
+		else if ((a & UVAL64 (0xffffffff80000000)) != 0
+			&& (a & UVAL64 (0xffffffff80000000)) != UVAL64 (0xffffffff80000000))
+		{
+			SET_VFLG (1);
+		}
+		m68k_dreg (regs, (extra >> 12) & 7) = (uae_u32)a;
+	} else {
+		/* unsigned */
+		uae_u64 a = (uae_u64)(uae_u32)m68k_dreg (regs, (extra >> 12) & 7);
+
+		a *= (uae_u64)src;
+		SET_VFLG (0);
+		SET_CFLG (0);
+		SET_ZFLG (a == 0);
+		SET_NFLG (((uae_s64)a) < 0);
+		if (extra & 0x400)
+			m68k_dreg (regs, extra & 7) = (uae_u32)(a >> 32);
+		else if ((a & UVAL64 (0xffffffff00000000)) != 0) {
+			SET_VFLG (1);
+		}
+		m68k_dreg (regs, (extra >> 12) & 7) = (uae_u32)a;
+	}
+#else
+	if (extra & 0x800) {
+		/* signed variant */
+		uae_s32 src1, src2;
+		uae_u32 dst_lo, dst_hi;
+		uae_u32 sign;
+
+		src1 = (uae_s32)src;
+		src2 = (uae_s32)m68k_dreg (regs, (extra >> 12) & 7);
+		sign = (src1 ^ src2);
+		if (src1 < 0) src1 = -src1;
+		if (src2 < 0) src2 = -src2;
+		mul_unsigned ((uae_u32)src1, (uae_u32)src2, &dst_hi, &dst_lo);
+		if (sign & 0x80000000) {
+			dst_hi = ~dst_hi;
+			dst_lo = -dst_lo;
+			if (dst_lo == 0) dst_hi++;
+		}
+		SET_VFLG (0);
+		SET_CFLG (0);
+		SET_ZFLG (dst_hi == 0 && dst_lo == 0);
+		SET_NFLG (((uae_s32)dst_hi) < 0);
+		if (extra & 0x400)
+			m68k_dreg (regs, extra & 7) = dst_hi;
+		else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
+			&& ((dst_hi & 0xffffffff) != 0xffffffff
+			|| (dst_lo & 0x80000000) != 0x80000000))
+		{
+			SET_VFLG (1);
+		}
+		m68k_dreg (regs, (extra >> 12) & 7) = dst_lo;
+	} else {
+		/* unsigned */
+		uae_u32 dst_lo, dst_hi;
+
+		mul_unsigned (src, (uae_u32)m68k_dreg (regs, (extra >> 12) & 7), &dst_hi, &dst_lo);
+
+		SET_VFLG (0);
+		SET_CFLG (0);
+		SET_ZFLG (dst_hi == 0 && dst_lo == 0);
+		SET_NFLG (((uae_s32)dst_hi) < 0);
+		if (extra & 0x400)
+			m68k_dreg (regs, extra & 7) = dst_hi;
+		else if (dst_hi != 0) {
+			SET_VFLG (1);
+		}
+		m68k_dreg (regs, (extra >> 12) & 7) = dst_lo;
+	}
+#endif
+	return true;
+}
+
+#endif
diff --git a/src/cpu/options_cpu.h b/src/cpu/options_cpu.h
new file mode 100644
index 0000000..e4986e3
--- /dev/null
+++ b/src/cpu/options_cpu.h
@@ -0,0 +1,797 @@
+/*
+  Hatari - options_cpu.h
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+*/
+
+#ifndef OPTIONS_CPU_H
+#define OPTIONS_CPU_H
+
+#ifndef WINUAE_FOR_HATARI
+#define UAEMAJOR 3
+#define UAEMINOR 1
+#define UAESUBREV 0
+
+typedef enum { KBD_LANG_US, KBD_LANG_DK, KBD_LANG_DE, KBD_LANG_SE, KBD_LANG_FR, KBD_LANG_IT, KBD_LANG_ES } KbdLang;
+
+extern long int version;
+
+#define MAX_PATHS 8
+
+struct multipath {
+	TCHAR path[MAX_PATHS][PATH_MAX];
+};
+
+struct strlist {
+	struct strlist *next;
+	TCHAR *option, *value;
+	int unknown;
+};
+
+#define MAX_TOTAL_SCSI_DEVICES 8
+
+/* maximum number native input devices supported (single type) */
+#define MAX_INPUT_DEVICES 20
+/* maximum number of native input device's buttons and axles supported */
+#define MAX_INPUT_DEVICE_EVENTS 256
+/* 4 different customization settings */
+#define MAX_INPUT_SETTINGS 4
+#define GAMEPORT_INPUT_SETTINGS 3 // last slot is for gameport panel mappings
+
+#define MAX_INPUT_SUB_EVENT 8
+#define MAX_INPUT_SUB_EVENT_ALL 9
+#define SPARE_SUB_EVENT 8
+
+#define INTERNALEVENT_COUNT 1
+
+struct uae_input_device {
+	TCHAR *name;
+	TCHAR *configname;
+	uae_s16 eventid[MAX_INPUT_DEVICE_EVENTS][MAX_INPUT_SUB_EVENT_ALL];
+	TCHAR *custom[MAX_INPUT_DEVICE_EVENTS][MAX_INPUT_SUB_EVENT_ALL];
+	uae_u64 flags[MAX_INPUT_DEVICE_EVENTS][MAX_INPUT_SUB_EVENT_ALL];
+	uae_s8 port[MAX_INPUT_DEVICE_EVENTS][MAX_INPUT_SUB_EVENT_ALL];
+	uae_s16 extra[MAX_INPUT_DEVICE_EVENTS];
+	uae_s8 enabled;
+};
+
+#define MAX_JPORTS 4
+#define NORMAL_JPORTS 2
+#define MAX_JPORTNAME 128
+struct jport {
+	int id;
+	int mode; // 0=def,1=mouse,2=joy,3=anajoy,4=lightpen
+	int autofire;
+	TCHAR name[MAX_JPORTNAME];
+	TCHAR configname[MAX_JPORTNAME];
+	bool nokeyboardoverride;
+};
+#define JPORT_NONE -1
+#define JPORT_CUSTOM -2
+#define JPORT_AF_NORMAL 1
+#define JPORT_AF_TOGGLE 2
+#define JPORT_AF_ALWAYS 3
+
+#define KBTYPE_AMIGA 0
+#define KBTYPE_PC1 1
+#define KBTYPE_PC2 2
+
+#define MAX_SPARE_DRIVES 20
+#define MAX_CUSTOM_MEMORY_ADDRS 2
+
+#define CONFIG_TYPE_ALL -1
+#define CONFIG_TYPE_DEFAULT 0
+#define CONFIG_TYPE_HARDWARE 1
+#define CONFIG_TYPE_HOST 2
+#define CONFIG_TYPE_NORESET 4
+#define CONFIG_BLEN 2560
+
+#define TABLET_OFF 0
+#define TABLET_MOUSEHACK 1
+#define TABLET_REAL 2
+
+#ifdef WITH_SLIRP
+#define MAX_SLIRP_REDIRS 32
+struct slirp_redir
+{
+	int proto;
+	int srcport;
+	int dstport;
+	unsigned long addr;
+};
+#endif
+
+struct cdslot
+{
+	TCHAR name[MAX_DPATH];
+	bool inuse;
+	bool delayed;
+	bool temporary;
+	int type;
+};
+struct floppyslot
+{
+	TCHAR df[MAX_DPATH];
+	int dfxtype;
+	int dfxclick;
+	TCHAR dfxclickexternal[256];
+	bool forcedwriteprotect;
+};
+
+#define ASPECTMULT 1024
+#define WH_NATIVE 1
+struct wh {
+	int x, y;
+	int width, height;
+	int special;
+};
+
+#define MOUNT_CONFIG_SIZE 30
+#define UAEDEV_DIR 0
+#define UAEDEV_HDF 1
+#define UAEDEV_CD 2
+#define UAEDEV_TAPE 3
+
+#define BOOTPRI_NOAUTOBOOT -128
+#define BOOTPRI_NOAUTOMOUNT -129
+#define ISAUTOBOOT(ci) ((ci)->bootpri > BOOTPRI_NOAUTOBOOT)
+#define ISAUTOMOUNT(ci) ((ci)->bootpri > BOOTPRI_NOAUTOMOUNT)
+struct uaedev_config_info {
+	int type;
+	TCHAR devname[MAX_DPATH];
+	TCHAR volname[MAX_DPATH];
+	TCHAR rootdir[MAX_DPATH];
+	bool readonly;
+	int bootpri;
+	TCHAR filesys[MAX_DPATH];
+	int lowcyl;
+	int highcyl; // zero if detected from size
+	int cyls; // calculated/corrected highcyl
+	int surfaces;
+	int sectors;
+	int reserved;
+	int blocksize;
+	int controller_type;
+	int controller_type_unit;
+	int controller_unit;
+	int controller_media_type; // 1 = CF IDE, 0 = normal
+	int unit_feature_level;
+	bool physical_geometry; // if false: use defaults
+	int pcyls, pheads, psecs;
+	int flags;
+	int buffers;
+	int bufmemtype;
+	int stacksize;
+	int priority;
+	uae_u32 mask;
+	int maxtransfer;
+	uae_u32 dostype;
+	int unit;
+	int interleave;
+	int sectorsperblock;
+	int forceload;
+	int device_emu_unit;
+	bool inject_icons;
+};
+
+struct uaedev_config_data
+{
+	struct uaedev_config_info ci;
+	int configoffset; // HD config entry index
+	int unitnum; // scsi unit number (if tape currently)
+};
+
+enum { CP_GENERIC = 1, CP_CDTV, CP_CDTVCR, CP_CD32, CP_A500, CP_A500P, CP_A600, CP_A1000,
+	CP_A1200, CP_A2000, CP_A3000, CP_A3000T, CP_A4000, CP_A4000T, CP_VELVET };
+
+#define IDE_A600A1200 1
+#define IDE_A4000 2
+
+#define GFX_WINDOW 0
+#define GFX_FULLSCREEN 1
+#define GFX_FULLWINDOW 2
+
+#define AUTOSCALE_NONE 0
+#define AUTOSCALE_STATIC_AUTO 1
+#define AUTOSCALE_STATIC_NOMINAL 2
+#define AUTOSCALE_STATIC_MAX 3
+#define AUTOSCALE_NORMAL 4
+#define AUTOSCALE_RESIZE 5
+#define AUTOSCALE_CENTER 6
+#define AUTOSCALE_MANUAL 7 // use gfx_xcenter_pos and gfx_ycenter_pos
+#define AUTOSCALE_INTEGER 8
+#define AUTOSCALE_INTEGER_AUTOSCALE 9
+#define AUTOSCALE_SEPARATOR 10
+#define AUTOSCALE_OVERSCAN_BLANK 11
+
+#define MONITOREMU_NONE 0
+#define MONITOREMU_AUTO 1
+#define MONITOREMU_A2024 2
+#define MONITOREMU_GRAFFITI 3
+#define MONITOREMU_HAM_E 4
+#define MONITOREMU_HAM_E_PLUS 5
+#define MONITOREMU_VIDEODAC18 6
+#define MONITOREMU_AVIDEO12 7
+#define MONITOREMU_AVIDEO24 8
+#define MONITOREMU_FIRECRACKER24 9
+#define MONITOREMU_DCTV 10
+
+#define MAX_FILTERSHADERS 4
+
+#define MAX_CHIPSET_REFRESH 10
+#define MAX_CHIPSET_REFRESH_TOTAL (MAX_CHIPSET_REFRESH + 2)
+#define CHIPSET_REFRESH_PAL (MAX_CHIPSET_REFRESH + 0)
+#define CHIPSET_REFRESH_NTSC (MAX_CHIPSET_REFRESH + 1)
+struct chipset_refresh
+{
+	int index;
+	bool locked;
+	bool rtg;
+	int horiz;
+	int vert;
+	int lace;
+	int ntsc;
+	int vsync;
+	int framelength;
+	double rate;
+	TCHAR label[16];
+	TCHAR commands[256];
+};
+
+#define APMODE_NATIVE 0
+#define APMODE_RTG 1
+
+struct apmode
+{
+	int gfx_fullscreen;
+	int gfx_display;
+	int gfx_vsync;
+	// 0 = immediate flip
+	// -1 = wait for flip, before frame ends
+	// 1 = wait for flip, after new frame has started
+	int gfx_vflip;
+	// doubleframemode strobo
+	bool gfx_strobo;
+	int gfx_vsyncmode;
+	int gfx_backbuffers;
+	bool gfx_interlaced;
+	int gfx_refreshrate;
+};
+
+#define MAX_LUA_STATES 16
+
+
+struct gfx_filterdata
+{
+	int gfx_filter;
+	TCHAR gfx_filtershader[2 * MAX_FILTERSHADERS + 1][MAX_DPATH];
+	TCHAR gfx_filtermask[2 * MAX_FILTERSHADERS + 1][MAX_DPATH];
+	TCHAR gfx_filteroverlay[MAX_DPATH];
+	struct wh gfx_filteroverlay_pos;
+	int gfx_filteroverlay_overscan;
+	int gfx_filter_scanlines;
+	int gfx_filter_scanlineratio;
+	int gfx_filter_scanlinelevel;
+	float gfx_filter_horiz_zoom, gfx_filter_vert_zoom;
+	float gfx_filter_horiz_zoom_mult, gfx_filter_vert_zoom_mult;
+	float gfx_filter_horiz_offset, gfx_filter_vert_offset;
+	int gfx_filter_left_border, gfx_filter_right_border;
+	int gfx_filter_top_border, gfx_filter_bottom_border;
+	int gfx_filter_filtermode;
+	int gfx_filter_bilinear;
+	int gfx_filter_noise, gfx_filter_blur;
+	int gfx_filter_saturation, gfx_filter_luminance, gfx_filter_contrast;
+	int gfx_filter_gamma, gfx_filter_gamma_ch[3];
+	int gfx_filter_keep_aspect, gfx_filter_aspect;
+	int gfx_filter_autoscale;
+	int gfx_filter_keep_autoscale_aspect;
+};
+
+#define MAX_DUPLICATE_EXPANSION_BOARDS 4
+#define MAX_EXPANSION_BOARDS 4
+struct romconfig
+{
+	TCHAR romfile[MAX_DPATH];
+	TCHAR romident[256];
+	uae_u32 board_ram_size;
+	bool autoboot_disabled;
+	int device_id;
+	int device_settings;
+	int subtype;
+	void *unitdata;
+};
+#define MAX_BOARD_ROMS 2
+struct boardromconfig
+{
+	int device_type;
+	int device_num;
+	struct romconfig roms[MAX_BOARD_ROMS];
+};
+
+#define Z3MAPPING_AUTO 0
+#define Z3MAPPING_UAE 1
+#define Z3MAPPING_REAL 2
+
+#endif		/* !WINUAE_FOR_HATARI */
+
+struct uae_prefs {
+#ifndef WINUAE_FOR_HATARI
+	struct strlist *all_lines;
+
+	TCHAR description[256];
+	TCHAR info[256];
+	int config_version;
+	TCHAR config_hardware_path[MAX_DPATH];
+	TCHAR config_host_path[MAX_DPATH];
+	TCHAR config_window_title[256];
+
+	bool illegal_mem;
+	bool use_serial;
+	bool serial_demand;
+	bool serial_hwctsrts;
+	bool serial_direct;
+	int serial_stopbits;
+	int serial_crlf;
+	bool parallel_demand;
+	int parallel_matrix_emulation;
+	bool parallel_postscript_emulation;
+	bool parallel_postscript_detection;
+	int parallel_autoflush_time;
+	TCHAR ghostscript_parameters[256];
+	bool use_gfxlib;
+	bool socket_emu;
+
+	bool start_debugger;
+	bool start_gui;
+
+	KbdLang keyboard_lang;
+
+	int produce_sound;
+	int sound_stereo;
+	int sound_stereo_separation;
+	int sound_mixed_stereo_delay;
+	int sound_freq;
+	int sound_maxbsiz;
+	int sound_interpol;
+	int sound_filter;
+	int sound_filter_type;
+	int sound_volume_master;
+	int sound_volume_paula;
+	int sound_volume_cd;
+	int sound_volume_board;
+	bool sound_stereo_swap_paula;
+	bool sound_stereo_swap_ahi;
+	bool sound_auto;
+	bool sound_cdaudio;
+
+	int sampler_freq;
+	int sampler_buffer;
+	bool sampler_stereo;
+#endif
+
+	int comptrustbyte;
+	int comptrustword;
+	int comptrustlong;
+	int comptrustnaddr;
+	bool compnf;
+	bool compfpu;
+	bool comp_midopt;
+	bool comp_lowopt;
+	bool fpu_strict;
+	bool fpu_softfloat;
+
+	bool comp_hardflush;
+	bool comp_constjump;
+	bool comp_oldsegv;
+
+	int cachesize;
+	int optcount[10];
+
+	bool avoid_cmov;
+
+#ifndef WINUAE_FOR_HATARI
+	int gfx_framerate, gfx_autoframerate;
+	struct wh gfx_size_win;
+	struct wh gfx_size_fs;
+	struct wh gfx_size;
+	struct wh gfx_size_win_xtra[6];
+	struct wh gfx_size_fs_xtra[6];
+	bool gfx_autoresolution_vga;
+	int gfx_autoresolution;
+	int gfx_autoresolution_delay;
+	int gfx_autoresolution_minv, gfx_autoresolution_minh;
+	bool gfx_scandoubler;
+	struct apmode gfx_apmode[2];
+	int gfx_resolution;
+	int gfx_vresolution;
+	int gfx_lores_mode;
+	int gfx_pscanlines, gfx_iscanlines;
+	int gfx_xcenter, gfx_ycenter;
+	int gfx_xcenter_pos, gfx_ycenter_pos;
+	int gfx_xcenter_size, gfx_ycenter_size;
+	int gfx_max_horizontal, gfx_max_vertical;
+	int gfx_saturation, gfx_luminance, gfx_contrast, gfx_gamma, gfx_gamma_ch[3];
+	bool gfx_blackerthanblack;
+	int gfx_api;
+	int color_mode;
+	int gfx_extrawidth;
+	bool lightboost_strobo;
+
+	struct gfx_filterdata gf[2];
+
+	float rtg_horiz_zoom_mult;
+	float rtg_vert_zoom_mult;
+
+	bool immediate_blits;
+	int waiting_blits;
+	unsigned int chipset_mask;
+#endif
+	bool ntscmode;
+#ifndef WINUAE_FOR_HATARI
+	bool genlock;
+	int monitoremu;
+	double chipset_refreshrate;
+	struct chipset_refresh cr[MAX_CHIPSET_REFRESH + 2];
+	int cr_selected;
+	int collision_level;
+	int leds_on_screen;
+	int leds_on_screen_mask[2];
+	struct wh osd_pos;
+	int keyboard_leds[3];
+	bool keyboard_leds_in_use;
+	int scsi;
+	bool sana2;
+	bool uaeserial;
+	int catweasel;
+#endif
+	int cpu_idle;
+	int ppc_cpu_idle;
+	bool cpu_cycle_exact;
+	int cpu_clock_multiplier;
+	int cpu_frequency;
+	bool blitter_cycle_exact;
+#ifndef WINUAE_FOR_HATARI
+	int floppy_speed;
+	int floppy_write_length;
+	int floppy_random_bits_min;
+	int floppy_random_bits_max;
+	int floppy_auto_ext2;
+	int cd_speed;
+	bool tod_hack;
+	uae_u32 maprom;
+	int boot_rom;
+	bool rom_readwrite;
+	int turbo_emulation;
+	bool headless;
+	int filesys_limit;
+	int filesys_max_name;
+	int filesys_max_file_size;
+	bool filesys_inject_icons;
+	TCHAR filesys_inject_icons_tool[MAX_DPATH];
+	TCHAR filesys_inject_icons_project[MAX_DPATH];
+	TCHAR filesys_inject_icons_drawer[MAX_DPATH];
+	int uaescsidevmode;
+#endif
+	bool reset_delay;
+
+#ifndef WINUAE_FOR_HATARI
+	int cs_compatible;
+	int cs_ciaatod;
+	int cs_rtc;
+	int cs_rtc_adjust;
+	int cs_rtc_adjust_mode;
+	bool cs_ksmirror_e0;
+	bool cs_ksmirror_a8;
+	bool cs_ciaoverlay;
+	bool cs_cd32cd;
+	bool cs_cd32c2p;
+	bool cs_cd32nvram;
+	bool cs_cd32fmv;
+	int cs_cd32nvram_size;
+	bool cs_cdtvcd;
+	bool cs_cdtvram;
+	int cs_cdtvcard;
+	int cs_ide;
+	bool cs_pcmcia;
+	bool cs_a1000ram;
+	int cs_fatgaryrev;
+	int cs_ramseyrev;
+	int cs_agnusrev;
+	int cs_deniserev;
+	int cs_mbdmac;
+	bool cs_cdtvscsi;
+	bool cs_cdtvcr;
+	bool cs_df0idhw;
+	bool cs_slowmemisfast;
+	bool cs_resetwarning;
+	bool cs_denisenoehb;
+	bool cs_dipagnus;
+	bool cs_agnusbltbusybug;
+	bool cs_ciatodbug;
+	bool cs_z3autoconfig;
+	bool cs_1mchipjumper;
+	bool cs_cia6526;
+	int cs_hacks;
+
+	struct boardromconfig expansionboard[MAX_EXPANSION_BOARDS];
+
+	TCHAR romfile[MAX_DPATH];
+	TCHAR romident[256];
+	TCHAR romextfile[MAX_DPATH];
+	uae_u32 romextfile2addr;
+	TCHAR romextfile2[MAX_DPATH];
+	TCHAR romextident[256];
+	TCHAR flashfile[MAX_DPATH];
+	TCHAR rtcfile[MAX_DPATH];
+	TCHAR cartfile[MAX_DPATH];
+	TCHAR cartident[256];
+	int cart_internal;
+	TCHAR pci_devices[256];
+	TCHAR prtname[256];
+	TCHAR sername[256];
+	TCHAR a2065name[MAX_DPATH];
+	TCHAR picassoivromfile[MAX_DPATH];
+	struct cdslot cdslots[MAX_TOTAL_SCSI_DEVICES];
+	TCHAR quitstatefile[MAX_DPATH];
+	TCHAR statefile[MAX_DPATH];
+	TCHAR inprecfile[MAX_DPATH];
+	bool inprec_autoplay;
+
+	struct multipath path_floppy;
+	struct multipath path_hardfile;
+	struct multipath path_rom;
+	struct multipath path_cd;
+#endif
+
+	int m68k_speed;
+	double m68k_speed_throttle;
+	int cpu_level;				/* Hatari */
+	int cpu_model;
+	int mmu_model;
+	int cpu060_revision;
+	int fpu_model;
+	int fpu_revision;
+	int ppc_mode;
+	TCHAR ppc_model[32];
+	bool cpu_compatible;
+	bool int_no_unimplemented;
+	bool fpu_no_unimplemented;
+	bool address_space_24;
+#ifndef WINUAE_FOR_HATARI
+	bool picasso96_nocustom;
+	int picasso96_modeflags;
+
+	uae_u32 z3autoconfig_start;
+	uae_u32 z3fastmem_size, z3fastmem2_size;
+	uae_u32 z3chipmem_size;
+	uae_u32 z3chipmem_start;
+	uae_u32 fastmem_size, fastmem2_size;
+	bool fastmem_autoconfig;
+	uae_u32 chipmem_size;
+	uae_u32 bogomem_size;
+	uae_u32 mbresmem_low_size;
+	uae_u32 mbresmem_high_size;
+	uae_u32 mem25bit_size;
+	uae_u32 rtgmem_size;
+	int cpuboard_type;
+	int cpuboard_subtype;
+	int cpuboard_settings;
+	uae_u32 cpuboardmem1_size;
+	uae_u32 cpuboardmem2_size;
+	int ppc_implementation;
+	bool rtg_hardwareinterrupt;
+	bool rtg_hardwaresprite;
+	int rtgmem_type;
+	bool rtg_more_compatible;
+	uae_u32 custom_memory_addrs[MAX_CUSTOM_MEMORY_ADDRS];
+	uae_u32 custom_memory_sizes[MAX_CUSTOM_MEMORY_ADDRS];
+
+	bool kickshifter;
+	bool filesys_no_uaefsdb;
+	bool filesys_custom_uaefsdb;
+	bool mmkeyboard;
+	int uae_hide;
+	bool clipboard_sharing;
+	bool native_code;
+	bool uae_hide_autoconfig;
+	int z3_mapping_mode;
+	bool sound_toccata;
+	bool sound_toccata_mixer;
+
+	int mountitems;
+	struct uaedev_config_data mountconfig[MOUNT_CONFIG_SIZE];
+
+	int nr_floppies;
+	struct floppyslot floppyslots[4];
+	bool floppy_read_only;
+	TCHAR dfxlist[MAX_SPARE_DRIVES][MAX_DPATH];
+	int dfxclickvolume;
+	int dfxclickvolume_disk[4];
+	int dfxclickvolume_empty[4];
+	int dfxclickchannelmask;
+
+	TCHAR luafiles[MAX_LUA_STATES][MAX_DPATH];
+
+	/* Target specific options */
+
+	bool win32_middle_mouse;
+	bool win32_logfile;
+	bool win32_notaskbarbutton;
+	bool win32_nonotificationicon;
+	bool win32_alwaysontop;
+	bool win32_powersavedisabled;
+	bool win32_minimize_inactive;
+	int win32_statusbar;
+	bool win32_start_minimized;
+	bool win32_start_uncaptured;
+
+	int win32_active_capture_priority;
+	bool win32_active_nocapture_pause;
+	bool win32_active_nocapture_nosound;
+	int win32_inactive_priority;
+	bool win32_inactive_pause;
+	bool win32_inactive_nosound;
+	int win32_inactive_input;
+	int win32_iconified_priority;
+	bool win32_iconified_pause;
+	bool win32_iconified_nosound;
+	int win32_iconified_input;
+
+	bool win32_rtgmatchdepth;
+	bool win32_rtgallowscaling;
+	int win32_rtgscaleaspectratio;
+	int win32_rtgvblankrate;
+	bool win32_borderless;
+	bool win32_ctrl_F11_is_quit;
+	bool win32_automount_removable;
+	bool win32_automount_drives;
+	bool win32_automount_cddrives;
+	bool win32_automount_netdrives;
+	bool win32_automount_removabledrives;
+	int win32_midioutdev;
+	int win32_midiindev;
+	bool win32_midirouter;
+	int win32_uaescsimode;
+	int win32_soundcard;
+	int win32_samplersoundcard;
+	bool win32_norecyclebin;
+	int win32_guikey;
+	int win32_kbledmode;
+	bool win32_blankmonitors;
+	TCHAR win32_commandpathstart[MAX_DPATH];
+	TCHAR win32_commandpathend[MAX_DPATH];
+	TCHAR win32_parjoyport0[MAX_DPATH];
+	TCHAR win32_parjoyport1[MAX_DPATH];
+	TCHAR win32_guipage[32];
+	TCHAR win32_guiactivepage[32];
+	bool win32_filesystem_mangle_reserved_names;
+#ifdef WITH_SLIRP
+	struct slirp_redir slirp_redirs[MAX_SLIRP_REDIRS]; 
+#endif
+	int statecapturerate, statecapturebuffersize;
+
+	/* input */
+
+	struct jport jports[MAX_JPORTS];
+	int input_selected_setting;
+	int input_joymouse_multiplier;
+	int input_joymouse_deadzone;
+	int input_joystick_deadzone;
+	int input_joymouse_speed;
+	int input_analog_joystick_mult;
+	int input_analog_joystick_offset;
+	int input_autofire_linecnt;
+	int input_mouse_speed;
+	int input_tablet;
+	bool tablet_library;
+	bool input_magic_mouse;
+	int input_magic_mouse_cursor;
+	int input_keyboard_type;
+	int input_autoswitch;
+	struct uae_input_device joystick_settings[MAX_INPUT_SETTINGS][MAX_INPUT_DEVICES];
+	struct uae_input_device mouse_settings[MAX_INPUT_SETTINGS][MAX_INPUT_DEVICES];
+	struct uae_input_device keyboard_settings[MAX_INPUT_SETTINGS][MAX_INPUT_DEVICES];
+	struct uae_input_device internalevent_settings[MAX_INPUT_SETTINGS][INTERNALEVENT_COUNT];
+	TCHAR input_config_name[GAMEPORT_INPUT_SETTINGS][256];
+	int dongle;
+	int input_contact_bounce;
+#endif
+};
+
+#ifndef WINUAE_FOR_HATARI
+extern int config_changed;
+extern void config_check_vsync (void);
+extern void set_config_changed (void);
+
+/* Contains the filename of .uaerc */
+extern TCHAR optionsfile[];
+extern void save_options (struct zfile *, struct uae_prefs *, int);
+
+extern void cfgfile_write (struct zfile *, const TCHAR *option, const TCHAR *format,...);
+extern void cfgfile_dwrite (struct zfile *, const TCHAR *option, const TCHAR *format,...);
+extern void cfgfile_target_write (struct zfile *, const TCHAR *option, const TCHAR *format,...);
+extern void cfgfile_target_dwrite (struct zfile *, const TCHAR *option, const TCHAR *format,...);
+
+extern void cfgfile_write_bool (struct zfile *f, const TCHAR *option, bool b);
+extern void cfgfile_dwrite_bool (struct zfile *f,const  TCHAR *option, bool b);
+extern void cfgfile_target_write_bool (struct zfile *f, const TCHAR *option, bool b);
+extern void cfgfile_target_dwrite_bool (struct zfile *f, const TCHAR *option, bool b);
+
+extern void cfgfile_write_str (struct zfile *f, const TCHAR *option, const TCHAR *value);
+extern void cfgfile_dwrite_str (struct zfile *f, const TCHAR *option, const TCHAR *value);
+extern void cfgfile_target_write_str (struct zfile *f, const TCHAR *option, const TCHAR *value);
+extern void cfgfile_target_dwrite_str (struct zfile *f, const TCHAR *option, const TCHAR *value);
+
+extern void cfgfile_backup (const TCHAR *path);
+extern struct uaedev_config_data *add_filesys_config (struct uae_prefs *p, int index, struct uaedev_config_info*);
+extern bool get_hd_geometry (struct uaedev_config_info *);
+extern void uci_set_defaults (struct uaedev_config_info *uci, bool rdb);
+
+extern void error_log (const TCHAR*, ...);
+extern TCHAR *get_error_log (void);
+extern bool is_error_log (void);
+
+extern void default_prefs (struct uae_prefs *, int);
+extern void discard_prefs (struct uae_prefs *, int);
+
+int parse_cmdline_option (struct uae_prefs *, TCHAR, const TCHAR*);
+
+extern int cfgfile_yesno (const TCHAR *option, const TCHAR *value, const TCHAR *name, bool *location);
+extern int cfgfile_intval (const TCHAR *option, const TCHAR *value, const TCHAR *name, int *location, int scale);
+extern int cfgfile_strval (const TCHAR *option, const TCHAR *value, const TCHAR *name, int *location, const TCHAR *table[], int more);
+extern int cfgfile_string (const TCHAR *option, const TCHAR *value, const TCHAR *name, TCHAR *location, int maxsz);
+extern TCHAR *cfgfile_subst_path (const TCHAR *path, const TCHAR *subst, const TCHAR *file);
+
+extern TCHAR *target_expand_environment (const TCHAR *path);
+extern int target_parse_option (struct uae_prefs *, const TCHAR *option, const TCHAR *value);
+extern void target_save_options (struct zfile*, struct uae_prefs *);
+extern void target_default_options (struct uae_prefs *, int type);
+extern void target_fixup_options (struct uae_prefs *);
+extern int target_cfgfile_load (struct uae_prefs *, const TCHAR *filename, int type, int isdefault);
+extern void cfgfile_save_options (struct zfile *f, struct uae_prefs *p, int type);
+extern int target_get_display (const TCHAR*);
+extern const TCHAR *target_get_display_name (int, bool);
+
+extern int cfgfile_load (struct uae_prefs *p, const TCHAR *filename, int *type, int ignorelink, int userconfig);
+extern int cfgfile_save (struct uae_prefs *p, const TCHAR *filename, int);
+extern void cfgfile_parse_line (struct uae_prefs *p, TCHAR *, int);
+extern void cfgfile_parse_lines (struct uae_prefs *p, const TCHAR *, int);
+extern int cfgfile_parse_option (struct uae_prefs *p, const TCHAR *option, TCHAR *value, int);
+extern int cfgfile_get_description (const TCHAR *filename, TCHAR *description, TCHAR *hostlink, TCHAR *hardwarelink, int *type);
+extern void cfgfile_show_usage (void);
+extern int cfgfile_searchconfig(const TCHAR *in, int index, TCHAR *out, int outsize);
+extern uae_u32 cfgfile_uaelib (int mode, uae_u32 name, uae_u32 dst, uae_u32 maxlen);
+extern uae_u32 cfgfile_uaelib_modify (uae_u32 mode, uae_u32 parms, uae_u32 size, uae_u32 out, uae_u32 outsize);
+extern uae_u32 cfgfile_modify (uae_u32 index, const TCHAR *parms, uae_u32 size, TCHAR *out, uae_u32 outsize);
+extern void cfgfile_addcfgparam (TCHAR *);
+extern int built_in_prefs (struct uae_prefs *p, int model, int config, int compa, int romcheck);
+extern int built_in_chipset_prefs (struct uae_prefs *p);
+extern int built_in_cpuboard_prefs(struct uae_prefs *p);
+extern int cmdlineparser (const TCHAR *s, TCHAR *outp[], int max);
+extern int cfgfile_configuration_change (int);
+extern void fixup_prefs_dimensions (struct uae_prefs *prefs);
+extern void fixup_prefs (struct uae_prefs *prefs);
+extern void fixup_cpu (struct uae_prefs *prefs);
+bool cfgfile_board_enabled(struct uae_prefs *p, int romtype, int devnum);
+
+extern void check_prefs_changed_custom (void);
+extern void check_prefs_changed_cpu (void);
+extern void check_prefs_changed_audio (void);
+extern void check_prefs_changed_cd (void);
+extern int check_prefs_changed_gfx (void);
+
+extern struct uae_prefs currprefs, changed_prefs;
+
+extern int machdep_init (void);
+extern void machdep_free (void);
+
+#else		/* !WINUAE_FOR_HATARI */
+
+extern struct uae_prefs currprefs, changed_prefs;
+extern void fixup_cpu (struct uae_prefs *prefs);
+extern void check_prefs_changed_cpu (void);
+
+#endif
+
+#endif /* OPTIONS_CPU_H */
diff --git a/src/cpu/readcpu.c b/src/cpu/readcpu.c
new file mode 100644
index 0000000..0f4fa16
--- /dev/null
+++ b/src/cpu/readcpu.c
@@ -0,0 +1,875 @@
+/*
+* UAE - The Un*x Amiga Emulator
+*
+* Read 68000 CPU specs from file "table68k"
+*
+* Copyright 1995,1996 Bernd Schmidt
+*/
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+#include 
+#include 
+
+#include "readcpu.h"
+
+int nr_cpuop_funcs;
+
+struct mnemolookup lookuptab[] = {
+	{ i_ILLG, _T("ILLEGAL") },
+	{ i_OR, _T("OR") },
+	{ i_CHK, _T("CHK") },
+	{ i_CHK2, _T("CHK2") },
+	{ i_AND, _T("AND") },
+	{ i_EOR, _T("EOR") },
+	{ i_ORSR, _T("ORSR") },
+	{ i_ANDSR, _T("ANDSR") },
+	{ i_EORSR, _T("EORSR") },
+	{ i_SUB, _T("SUB") },
+	{ i_SUBA, _T("SUBA") },
+	{ i_SUBX, _T("SUBX") },
+	{ i_SBCD, _T("SBCD") },
+	{ i_ADD, _T("ADD") },
+	{ i_ADDA, _T("ADDA") },
+	{ i_ADDX, _T("ADDX") },
+	{ i_ABCD, _T("ABCD") },
+	{ i_NEG, _T("NEG") },
+	{ i_NEGX, _T("NEGX") },
+	{ i_NBCD, _T("NBCD") },
+	{ i_CLR, _T("CLR") },
+	{ i_NOT, _T("NOT") },
+	{ i_TST, _T("TST") },
+	{ i_BTST, _T("BTST") },
+	{ i_BCHG, _T("BCHG") },
+	{ i_BCLR, _T("BCLR") },
+	{ i_BSET, _T("BSET") },
+	{ i_CMP, _T("CMP") },
+	{ i_CMPM, _T("CMPM") },
+	{ i_CMPA, _T("CMPA") },
+	{ i_MVPRM, _T("MVPRM") },
+	{ i_MVPMR, _T("MVPMR") },
+	{ i_MOVE, _T("MOVE") },
+	{ i_MOVEA, _T("MOVEA") },
+	{ i_MVSR2, _T("MVSR2") },
+	{ i_MV2SR, _T("MV2SR") },
+	{ i_SWAP, _T("SWAP") },
+	{ i_EXG, _T("EXG") },
+	{ i_EXT, _T("EXT") },
+	{ i_MVMEL, _T("MVMEL"), _T("MOVEM") },
+	{ i_MVMLE, _T("MVMLE"), _T("MOVEM") },
+	{ i_TRAP, _T("TRAP") },
+	{ i_MVR2USP, _T("MVR2USP") },
+	{ i_MVUSP2R, _T("MVUSP2R") },
+	{ i_NOP, _T("NOP") },
+	{ i_RESET, _T("RESET") },
+	{ i_RTE, _T("RTE") },
+	{ i_RTD, _T("RTD") },
+	{ i_LINK, _T("LINK") },
+	{ i_UNLK, _T("UNLK") },
+	{ i_RTS, _T("RTS") },
+	{ i_STOP, _T("STOP") },
+	{ i_TRAPV, _T("TRAPV") },
+	{ i_RTR, _T("RTR") },
+	{ i_JSR, _T("JSR") },
+	{ i_JMP, _T("JMP") },
+	{ i_BSR, _T("BSR") },
+	{ i_Bcc, _T("Bcc") },
+	{ i_LEA, _T("LEA") },
+	{ i_PEA, _T("PEA") },
+	{ i_DBcc, _T("DBcc") },
+	{ i_Scc, _T("Scc") },
+	{ i_DIVU, _T("DIVU") },
+	{ i_DIVS, _T("DIVS") },
+	{ i_MULU, _T("MULU") },
+	{ i_MULS, _T("MULS") },
+	{ i_ASR, _T("ASR") },
+	{ i_ASL, _T("ASL") },
+	{ i_LSR, _T("LSR") },
+	{ i_LSL, _T("LSL") },
+	{ i_ROL, _T("ROL") },
+	{ i_ROR, _T("ROR") },
+	{ i_ROXL, _T("ROXL") },
+	{ i_ROXR, _T("ROXR") },
+	{ i_ASRW, _T("ASRW") },
+	{ i_ASLW, _T("ASLW") },
+	{ i_LSRW, _T("LSRW") },
+	{ i_LSLW, _T("LSLW") },
+	{ i_ROLW, _T("ROLW") },
+	{ i_RORW, _T("RORW") },
+	{ i_ROXLW, _T("ROXLW") },
+	{ i_ROXRW, _T("ROXRW") },
+
+	{ i_MOVE2C, _T("MOVE2C"), _T("MOVEC") },
+	{ i_MOVEC2, _T("MOVEC2"), _T("MOVEC") },
+	{ i_CAS, _T("CAS") },
+	{ i_CAS2, _T("CAS2") },
+	{ i_MULL, _T("MULL") },
+	{ i_DIVL, _T("DIVL") },
+	{ i_BFTST, _T("BFTST") },
+	{ i_BFEXTU, _T("BFEXTU") },
+	{ i_BFCHG, _T("BFCHG") },
+	{ i_BFEXTS, _T("BFEXTS") },
+	{ i_BFCLR, _T("BFCLR") },
+	{ i_BFFFO, _T("BFFFO") },
+	{ i_BFSET, _T("BFSET") },
+	{ i_BFINS, _T("BFINS") },
+	{ i_PACK, _T("PACK") },
+	{ i_UNPK, _T("UNPK") },
+	{ i_TAS, _T("TAS") },
+	{ i_BKPT, _T("BKPT") },
+	{ i_CALLM, _T("CALLM") },
+	{ i_RTM, _T("RTM") },
+	{ i_TRAPcc, _T("TRAPcc") },
+	{ i_MOVES, _T("MOVES") },
+	{ i_FPP, _T("FPP") },
+	{ i_FDBcc, _T("FDBcc") },
+	{ i_FScc, _T("FScc") },
+	{ i_FTRAPcc, _T("FTRAPcc") },
+	{ i_FBcc, _T("FBcc") },
+	{ i_FBcc, _T("FBcc") },
+	{ i_FSAVE, _T("FSAVE") },
+	{ i_FRESTORE, _T("FRESTORE") },
+
+	{ i_CINVL, _T("CINVL") },
+	{ i_CINVP, _T("CINVP") },
+	{ i_CINVA, _T("CINVA") },
+	{ i_CPUSHL, _T("CPUSHL") },
+	{ i_CPUSHP, _T("CPUSHP") },
+	{ i_CPUSHA, _T("CPUSHA") },
+	{ i_MOVE16, _T("MOVE16") },
+
+	{ i_MMUOP030, _T("MMUOP030") },
+	{ i_PFLUSHN, _T("PFLUSHN") },
+	{ i_PFLUSH, _T("PFLUSH") },
+	{ i_PFLUSHAN, _T("PFLUSHAN") },
+	{ i_PFLUSHA, _T("PFLUSHA") },
+
+	{ i_PLPAR, _T("PLPAR") },
+	{ i_PLPAW, _T("PLPAW") },
+	{ i_PTESTR, _T("PTESTR") },
+	{ i_PTESTW, _T("PTESTW") },
+
+	{ i_LPSTOP, _T("LPSTOP") },
+	{ i_ILLG, _T("") },
+};
+
+struct instr *table68k;
+
+static amodes mode_from_str (const TCHAR *str)
+{
+	if (_tcsncmp (str, _T("Dreg"), 4) == 0) return Dreg;
+	if (_tcsncmp (str, _T("Areg"), 4) == 0) return Areg;
+	if (_tcsncmp (str, _T("Aind"), 4) == 0) return Aind;
+	if (_tcsncmp (str, _T("Apdi"), 4) == 0) return Apdi;
+	if (_tcsncmp (str, _T("Aipi"), 4) == 0) return Aipi;
+	if (_tcsncmp (str, _T("Ad16"), 4) == 0) return Ad16;
+	if (_tcsncmp (str, _T("Ad8r"), 4) == 0) return Ad8r;
+	if (_tcsncmp (str, _T("absw"), 4) == 0) return absw;
+	if (_tcsncmp (str, _T("absl"), 4) == 0) return absl;
+	if (_tcsncmp (str, _T("PC16"), 4) == 0) return PC16;
+	if (_tcsncmp (str, _T("PC8r"), 4) == 0) return PC8r;
+	if (_tcsncmp (str, _T("Immd"), 4) == 0) return imm;
+	abort ();
+	return 0;
+}
+
+STATIC_INLINE amodes mode_from_mr (int mode, int reg)
+{
+	switch (mode) {
+	case 0: return Dreg;
+	case 1: return Areg;
+	case 2: return Aind;
+	case 3: return Aipi;
+	case 4: return Apdi;
+	case 5: return Ad16;
+	case 6: return Ad8r;
+	case 7:
+		switch (reg) {
+		case 0: return absw;
+		case 1: return absl;
+		case 2: return PC16;
+		case 3: return PC8r;
+		case 4: return imm;
+		case 5:
+		case 6:
+		case 7: return am_illg;
+		}
+	}
+	abort ();
+	return 0;
+}
+
+static void build_insn (int insn)
+{
+	int find = -1;
+	int variants;
+	int isjmp = 0;
+	struct instr_def id;
+	const TCHAR *opcstr;
+	int i;
+
+	int flaglive = 0, flagdead = 0;
+
+	id = defs68k[insn];
+
+	/* Note: We treat anything with unknown flags as a jump. That
+	is overkill, but "the programmer" was lazy quite often, and
+	*this* programmer can't be bothered to work out what can and
+	can't trap. Usually, this will be overwritten with the gencomp
+	based information, anyway. */
+
+	for (i = 0; i < 5; i++) {
+		switch (id.flaginfo[i].flagset){
+		case fa_unset: break;
+		case fa_isjmp: isjmp = 1; break;
+		case fa_isbranch: isjmp = 1; break;
+		case fa_zero: flagdead |= 1 << i; break;
+		case fa_one: flagdead |= 1 << i; break;
+		case fa_dontcare: flagdead |= 1 << i; break;
+		case fa_unknown: isjmp = 1; flagdead = -1; goto out1;
+		case fa_set: flagdead |= 1 << i; break;
+		}
+	}
+
+out1:
+	for (i = 0; i < 5; i++) {
+		switch (id.flaginfo[i].flaguse) {
+		case fu_unused: break;
+		case fu_isjmp: isjmp = 1; flaglive |= 1 << i; break;
+		case fu_maybecc: isjmp = 1; flaglive |= 1 << i; break;
+		case fu_unknown: isjmp = 1; flaglive |= 1 << i; break;
+		case fu_used: flaglive |= 1 << i; break;
+		}
+	}
+
+	opcstr = id.opcstr;
+	for (variants = 0; variants < (1 << id.n_variable); variants++) {
+		int bitcnt[lastbit];
+		int bitval[lastbit];
+		int bitpos[lastbit];
+		int i;
+		uae_u16 opc = id.bits;
+		uae_u16 msk, vmsk;
+		int pos = 0;
+		int mnp = 0;
+		int bitno = 0;
+		int unsized = 1;
+		TCHAR mnemonic[10];
+		int mnemo;
+
+		wordsizes sz = sz_long;
+		int srcgather = 0, dstgather = 0;
+		int usesrc = 0, usedst = 0;
+		int srctype = 0;
+		int srcpos = -1, dstpos = -1;
+
+		amodes srcmode = am_unknown, destmode = am_unknown;
+		int srcreg = -1, destreg = -1;
+
+		for (i = 0; i < lastbit; i++)
+			bitcnt[i] = bitval[i] = 0;
+
+		vmsk = 1 << id.n_variable;
+
+		for (i = 0, msk = 0x8000; i < 16; i++, msk >>= 1) {
+			if (!(msk & id.mask)) {
+				int currbit = id.bitpos[bitno++];
+				int bit_set;
+				vmsk >>= 1;
+				bit_set = variants & vmsk ? 1 : 0;
+				if (bit_set)
+					opc |= msk;
+				bitpos[currbit] = 15 - i;
+				bitcnt[currbit]++;
+				bitval[currbit] <<= 1;
+				bitval[currbit] |= bit_set;
+			}
+		}
+
+		if (bitval[bitj] == 0) bitval[bitj] = 8;
+		/* first check whether this one does not match after all */
+		if (bitval[bitz] == 3 || bitval[bitC] == 1)
+			continue;
+		if (bitcnt[bitI] && (bitval[bitI] == 0x00 || bitval[bitI] == 0xff))
+			continue;
+
+		/* bitI and bitC get copied to biti and bitc */
+		if (bitcnt[bitI]) {
+			bitval[biti] = bitval[bitI]; bitpos[biti] = bitpos[bitI];
+		}
+		if (bitcnt[bitC])
+			bitval[bitc] = bitval[bitC];
+
+		pos = 0;
+		while (opcstr[pos] && !_istspace(opcstr[pos])) {
+			if (opcstr[pos] == '.') {
+				pos++;
+				unsized = 0;
+				switch (opcstr[pos]) {
+
+				case 'B': sz = sz_byte; break;
+				case 'W': sz = sz_word; break;
+				case 'L': sz = sz_long; break;
+				case 'z':
+					switch (bitval[bitz]) {
+					case 0: sz = sz_byte; break;
+					case 1: sz = sz_word; break;
+					case 2: sz = sz_long; break;
+					default: abort();
+					}
+					break;
+				default: abort();
+				}
+			} else {
+				mnemonic[mnp] = opcstr[pos];
+				if (mnemonic[mnp] == 'f') {
+					find = -1;
+					switch (bitval[bitf]) {
+					case 0: mnemonic[mnp] = 'R'; break;
+					case 1: mnemonic[mnp] = 'L'; break;
+					default: abort();
+					}
+				}
+				mnp++;
+			}
+			pos++;
+		}
+		mnemonic[mnp] = 0;
+
+		/* now, we have read the mnemonic and the size */
+		while (opcstr[pos] && _istspace(opcstr[pos]))
+			pos++;
+
+		/* A goto a day keeps the D******a away. */
+		if (opcstr[pos] == 0)
+			goto endofline;
+
+		/* parse the source address */
+		usesrc = 1;
+		switch (opcstr[pos++]) {
+		case 'D':
+			srcmode = Dreg;
+			switch (opcstr[pos++]) {
+			case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;
+			case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;
+			default: abort();
+			}
+			break;
+		case 'A':
+			srcmode = Areg;
+			switch (opcstr[pos++]) {
+			case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;
+			case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;
+			default: abort();
+			}
+			switch (opcstr[pos]) {
+			case 'p': srcmode = Apdi; pos++; break;
+			case 'P': srcmode = Aipi; pos++; break;
+			case 'a': srcmode = Aind; pos++; break;
+			}
+			break;
+		case 'L':
+			srcmode = absl;
+			break;
+		case '#':
+			switch (opcstr[pos++]) {
+			case 'z': srcmode = imm; break;
+			case '0': srcmode = imm0; break;
+			case '1': srcmode = imm1; break;
+			case '2': srcmode = imm2; break;
+			case 'i': srcmode = immi; srcreg = (uae_s32)(uae_s8)bitval[biti];
+				if (CPU_EMU_SIZE < 4) {
+					/* Used for branch instructions */
+					srctype = 1;
+					srcgather = 1;
+					srcpos = bitpos[biti];
+				}
+				break;
+			case 'j': srcmode = immi; srcreg = bitval[bitj];
+				if (CPU_EMU_SIZE < 3) {
+					/* 1..8 for ADDQ/SUBQ and rotshi insns */
+					srcgather = 1;
+					srctype = 3;
+					srcpos = bitpos[bitj];
+				}
+				break;
+			case 'J': srcmode = immi; srcreg = bitval[bitJ];
+				if (CPU_EMU_SIZE < 5) {
+					/* 0..15 */
+					srcgather = 1;
+					srctype = 2;
+					srcpos = bitpos[bitJ];
+				}
+				break;
+			case 'k': srcmode = immi; srcreg = bitval[bitk];
+				if (CPU_EMU_SIZE < 3) {
+					srcgather = 1;
+					srctype = 4;
+					srcpos = bitpos[bitk];
+				}
+				break;
+			case 'K': srcmode = immi; srcreg = bitval[bitK];
+				if (CPU_EMU_SIZE < 5) {
+					/* 0..15 */
+					srcgather = 1;
+					srctype = 5;
+					srcpos = bitpos[bitK];
+				}
+				break;
+			case 'p': srcmode = immi; srcreg = bitval[bitK];
+				if (CPU_EMU_SIZE < 5) {
+					/* 0..3 */
+					srcgather = 1;
+					srctype = 7;
+					srcpos = bitpos[bitp];
+				}
+				break;
+			default: abort();
+			}
+			break;
+		case 'd':
+			srcreg = bitval[bitD];
+			srcmode = mode_from_mr(bitval[bitd],bitval[bitD]);
+			if (srcmode == am_illg)
+				continue;
+			if (CPU_EMU_SIZE < 2 &&
+				(srcmode == Areg || srcmode == Dreg || srcmode == Aind
+				|| srcmode == Ad16 || srcmode == Ad8r || srcmode == Aipi
+				|| srcmode == Apdi))
+			{
+				srcgather = 1; srcpos = bitpos[bitD];
+			}
+			if (opcstr[pos] == '[') {
+				pos++;
+				if (opcstr[pos] == '!') {
+					/* exclusion */
+					do {
+						pos++;
+						if (mode_from_str(opcstr+pos) == srcmode)
+							goto nomatch;
+						pos += 4;
+					} while (opcstr[pos] == ',');
+					pos++;
+				} else {
+					if (opcstr[pos+4] == '-') {
+						/* replacement */
+						if (mode_from_str(opcstr+pos) == srcmode)
+							srcmode = mode_from_str(opcstr+pos+5);
+						else
+							goto nomatch;
+						pos += 10;
+					} else {
+						/* normal */
+						while(mode_from_str(opcstr+pos) != srcmode) {
+							pos += 4;
+							if (opcstr[pos] == ']')
+								goto nomatch;
+							pos++;
+						}
+						while(opcstr[pos] != ']') pos++;
+						pos++;
+						break;
+					}
+				}
+			}
+			/* Some addressing modes are invalid as destination */
+			if (srcmode == imm || srcmode == PC16 || srcmode == PC8r)
+				goto nomatch;
+			break;
+		case 's':
+			srcreg = bitval[bitS];
+			srcmode = mode_from_mr(bitval[bits],bitval[bitS]);
+
+			if (srcmode == am_illg)
+				continue;
+			if (CPU_EMU_SIZE < 2 &&
+				(srcmode == Areg || srcmode == Dreg || srcmode == Aind
+				|| srcmode == Ad16 || srcmode == Ad8r || srcmode == Aipi
+				|| srcmode == Apdi))
+			{
+				srcgather = 1; srcpos = bitpos[bitS];
+			}
+			if (opcstr[pos] == '[') {
+				pos++;
+				if (opcstr[pos] == '!') {
+					/* exclusion */
+					do {
+						pos++;
+						if (mode_from_str(opcstr+pos) == srcmode)
+							goto nomatch;
+						pos += 4;
+					} while (opcstr[pos] == ',');
+					pos++;
+				} else {
+					if (opcstr[pos+4] == '-') {
+						/* replacement */
+						if (mode_from_str(opcstr+pos) == srcmode)
+							srcmode = mode_from_str(opcstr+pos+5);
+						else
+							goto nomatch;
+						pos += 10;
+					} else {
+						/* normal */
+						while(mode_from_str(opcstr+pos) != srcmode) {
+							pos += 4;
+							if (opcstr[pos] == ']')
+								goto nomatch;
+							pos++;
+						}
+						while(opcstr[pos] != ']') pos++;
+						pos++;
+					}
+				}
+			}
+			break;
+		default: abort();
+		}
+		/* safety check - might have changed */
+		if (srcmode != Areg && srcmode != Dreg && srcmode != Aind
+			&& srcmode != Ad16 && srcmode != Ad8r && srcmode != Aipi
+			&& srcmode != Apdi && srcmode != immi)
+		{
+			srcgather = 0;
+		}
+		if (srcmode == Areg && sz == sz_byte)
+			goto nomatch;
+
+		if (opcstr[pos] != ',')
+			goto endofline;
+		pos++;
+
+		/* parse the destination address */
+		usedst = 1;
+		switch (opcstr[pos++]) {
+		case 'D':
+			destmode = Dreg;
+			switch (opcstr[pos++]) {
+			case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break;
+			case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break;
+			default: abort();
+			}
+			if (dstpos < 0 || dstpos >= 32)
+				abort ();
+			break;
+		case 'A':
+			destmode = Areg;
+			switch (opcstr[pos++]) {
+			case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break;
+			case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break;
+			case 'x': destreg = 0; dstgather = 0; dstpos = 0; break;
+			default: abort();
+			}
+			if (dstpos < 0 || dstpos >= 32)
+				abort ();
+			switch (opcstr[pos]) {
+			case 'p': destmode = Apdi; pos++; break;
+			case 'P': destmode = Aipi; pos++; break;
+			}
+			break;
+		case 'L':
+			destmode = absl;
+			break;
+		case '#':
+			switch (opcstr[pos++]) {
+			case 'z': destmode = imm; break;
+			case '0': destmode = imm0; break;
+			case '1': destmode = imm1; break;
+			case '2': destmode = imm2; break;
+			case 'i': destmode = immi; destreg = (uae_s32)(uae_s8)bitval[biti]; break;
+			case 'j': destmode = immi; destreg = bitval[bitj]; break;
+			case 'J': destmode = immi; destreg = bitval[bitJ]; break;
+			case 'k': destmode = immi; destreg = bitval[bitk]; break;
+			case 'K': destmode = immi; destreg = bitval[bitK]; break;
+			default: abort();
+			}
+			break;
+		case 'd':
+			destreg = bitval[bitD];
+			destmode = mode_from_mr(bitval[bitd],bitval[bitD]);
+			if (destmode == am_illg)
+				continue;
+			if (CPU_EMU_SIZE < 1 &&
+				(destmode == Areg || destmode == Dreg || destmode == Aind
+				|| destmode == Ad16 || destmode == Ad8r || destmode == Aipi
+				|| destmode == Apdi))
+			{
+				dstgather = 1; dstpos = bitpos[bitD];
+			}
+
+			if (opcstr[pos] == '[') {
+				pos++;
+				if (opcstr[pos] == '!') {
+					/* exclusion */
+					do {
+						pos++;
+						if (mode_from_str(opcstr+pos) == destmode)
+							goto nomatch;
+						pos += 4;
+					} while (opcstr[pos] == ',');
+					pos++;
+				} else {
+					if (opcstr[pos+4] == '-') {
+						/* replacement */
+						if (mode_from_str(opcstr+pos) == destmode)
+							destmode = mode_from_str(opcstr+pos+5);
+						else
+							goto nomatch;
+						pos += 10;
+					} else {
+						/* normal */
+						while(mode_from_str(opcstr+pos) != destmode) {
+							pos += 4;
+							if (opcstr[pos] == ']')
+								goto nomatch;
+							pos++;
+						}
+						while(opcstr[pos] != ']') pos++;
+						pos++;
+						break;
+					}
+				}
+			}
+			/* Some addressing modes are invalid as destination */
+			if (destmode == imm || destmode == PC16 || destmode == PC8r)
+				goto nomatch;
+			break;
+		case 's':
+			destreg = bitval[bitS];
+			destmode = mode_from_mr(bitval[bits],bitval[bitS]);
+
+			if (destmode == am_illg)
+				continue;
+			if (CPU_EMU_SIZE < 1 &&
+				(destmode == Areg || destmode == Dreg || destmode == Aind
+				|| destmode == Ad16 || destmode == Ad8r || destmode == Aipi
+				|| destmode == Apdi))
+			{
+				dstgather = 1; dstpos = bitpos[bitS];
+			}
+
+			if (opcstr[pos] == '[') {
+				pos++;
+				if (opcstr[pos] == '!') {
+					/* exclusion */
+					do {
+						pos++;
+						if (mode_from_str(opcstr+pos) == destmode)
+							goto nomatch;
+						pos += 4;
+					} while (opcstr[pos] == ',');
+					pos++;
+				} else {
+					if (opcstr[pos+4] == '-') {
+						/* replacement */
+						if (mode_from_str(opcstr+pos) == destmode)
+							destmode = mode_from_str(opcstr+pos+5);
+						else
+							goto nomatch;
+						pos += 10;
+					} else {
+						/* normal */
+						while(mode_from_str(opcstr+pos) != destmode) {
+							pos += 4;
+							if (opcstr[pos] == ']')
+								goto nomatch;
+							pos++;
+						}
+						while(opcstr[pos] != ']') pos++;
+						pos++;
+					}
+				}
+			}
+			break;
+		default: abort();
+		}
+		/* safety check - might have changed */
+		if (destmode != Areg && destmode != Dreg && destmode != Aind
+			&& destmode != Ad16 && destmode != Ad8r && destmode != Aipi
+			&& destmode != Apdi)
+		{
+			dstgather = 0;
+		}
+
+		if (destmode == Areg && sz == sz_byte)
+			goto nomatch;
+#if 0
+		if (sz == sz_byte && (destmode == Aipi || destmode == Apdi)) {
+			dstgather = 0;
+		}
+#endif
+endofline:
+		/* now, we have a match */
+		if (table68k[opc].mnemo != i_ILLG)
+			;//write_log (_T("Double match: %x: %s\n"), opc, opcstr);
+		if (find == -1) {
+			for (find = 0;; find++) {
+				if (_tcscmp (mnemonic, lookuptab[find].name) == 0) {
+					table68k[opc].mnemo = lookuptab[find].mnemo;
+					break;
+				}
+				if (_tcslen (lookuptab[find].name) == 0)
+					abort();
+			}
+		}
+		else {
+			table68k[opc].mnemo = lookuptab[find].mnemo;
+		}
+		table68k[opc].cc = bitval[bitc];
+		mnemo = table68k[opc].mnemo;
+		if (mnemo == i_BTST
+			|| mnemo == i_BSET
+			|| mnemo == i_BCLR
+			|| mnemo == i_BCHG)
+		{
+			sz = destmode == Dreg ? sz_long : sz_byte;
+			unsized = 0;
+		}
+		if (mnemo == i_JSR || mnemo == i_JMP) {
+			unsized = 1;
+		}
+
+		table68k[opc].size = sz;
+		table68k[opc].unsized = unsized;
+		table68k[opc].sduse = id.sduse;
+		table68k[opc].sreg = srcreg;
+		table68k[opc].dreg = destreg;
+		table68k[opc].smode = srcmode;
+		table68k[opc].dmode = destmode;
+		table68k[opc].spos = srcgather ? srcpos : -1;
+		table68k[opc].dpos = dstgather ? dstpos : -1;
+		table68k[opc].suse = usesrc;
+		table68k[opc].duse = usedst;
+		table68k[opc].stype = srctype;
+		table68k[opc].plev = id.plevel;
+		table68k[opc].clev = id.cpulevel;
+		table68k[opc].unimpclev = id.unimpcpulevel;
+		table68k[opc].head = id.head;
+		table68k[opc].tail = id.tail;
+		table68k[opc].clocks = id.clocks;
+		table68k[opc].fetchmode = id.fetchmode;
+
+#if 0
+		for (i = 0; i < 5; i++) {
+			table68k[opc].flaginfo[i].flagset = id.flaginfo[i].flagset;
+			table68k[opc].flaginfo[i].flaguse = id.flaginfo[i].flaguse;
+		}
+#endif
+		table68k[opc].flagdead = flagdead;
+		table68k[opc].flaglive = flaglive;
+		table68k[opc].isjmp = isjmp;
+nomatch:
+		/* FOO! */;
+	}
+}
+
+
+void read_table68k (void)
+{
+	int i;
+
+	free (table68k);
+	table68k = xmalloc (struct instr, 65536);
+	for (i = 0; i < 65536; i++) {
+		table68k[i].mnemo = i_ILLG;
+		table68k[i].handler = -1;
+	}
+	for (i = 0; i < n_defs68k; i++) {
+		build_insn (i);
+	}
+}
+
+static int imismatch;
+
+static void handle_merges (long int opcode)
+{
+	uae_u16 smsk;
+	uae_u16 dmsk;
+	int sbitdst, dstend;
+	int srcreg, dstreg;
+
+	if (table68k[opcode].spos == -1) {
+		sbitdst = 1; smsk = 0;
+	} else {
+		switch (table68k[opcode].stype) {
+		case 0:
+			smsk = 7; sbitdst = 8; break;
+		case 1:
+			smsk = 255; sbitdst = 256; break;
+		case 2:
+			smsk = 15; sbitdst = 16; break;
+		case 3:
+			smsk = 7; sbitdst = 8; break;
+		case 4:
+			smsk = 7; sbitdst = 8; break;
+		case 5:
+			smsk = 63; sbitdst = 64; break;
+		case 7:
+			smsk = 3; sbitdst = 4; break;
+		default:
+			smsk = 0; sbitdst = 0;
+			abort();
+			break;
+		}
+		smsk <<= table68k[opcode].spos;
+	}
+	if (table68k[opcode].dpos == -1) {
+		dstend = 1; dmsk = 0;
+	} else {
+		dmsk = 7 << table68k[opcode].dpos;
+		dstend = 8;
+	}
+	for (srcreg=0; srcreg < sbitdst; srcreg++) {
+		for (dstreg=0; dstreg < dstend; dstreg++) {
+			uae_u16 code = (uae_u16)opcode;
+
+			code = (code & ~smsk) | (srcreg << table68k[opcode].spos);
+			code = (code & ~dmsk) | (dstreg << table68k[opcode].dpos);
+
+			/* Check whether this is in fact the same instruction.
+			* The instructions should never differ, except for the
+			* Bcc.(BW) case. */
+			if (table68k[code].mnemo != table68k[opcode].mnemo
+				|| table68k[code].size != table68k[opcode].size
+				|| table68k[code].suse != table68k[opcode].suse
+				|| table68k[code].duse != table68k[opcode].duse)
+			{
+				imismatch++; continue;
+			}
+			if (table68k[opcode].suse
+				&& (table68k[opcode].spos != table68k[code].spos
+				|| table68k[opcode].smode != table68k[code].smode
+				|| table68k[opcode].stype != table68k[code].stype))
+			{
+				imismatch++; continue;
+			}
+			if (table68k[opcode].duse
+				&& (table68k[opcode].dpos != table68k[code].dpos
+				|| table68k[opcode].dmode != table68k[code].dmode))
+			{
+				imismatch++; continue;
+			}
+
+			if (code != opcode)
+				table68k[code].handler = opcode;
+		}
+	}
+}
+
+void do_merges (void)
+{
+	long int opcode;
+	int nr = 0;
+	imismatch = 0;
+	for (opcode = 0; opcode < 65536; opcode++) {
+		if (table68k[opcode].handler != -1 || table68k[opcode].mnemo == i_ILLG)
+			continue;
+		nr++;
+		handle_merges (opcode);
+	}
+	nr_cpuop_funcs = nr;
+}
+
+int get_no_mismatches (void)
+{
+	return imismatch;
+}
diff --git a/src/cpu/readcpu.h b/src/cpu/readcpu.h
new file mode 100644
index 0000000..758ed49
--- /dev/null
+++ b/src/cpu/readcpu.h
@@ -0,0 +1,118 @@
+#ifndef READCPU_H
+#define READCPU_H
+
+ENUMDECL {
+  Dreg, Areg, Aind, Aipi, Apdi, Ad16, Ad8r,
+  absw, absl, PC16, PC8r, imm, imm0, imm1, imm2, immi, am_unknown, am_illg
+} ENUMNAME (amodes);
+
+ENUMDECL {
+    i_ILLG,
+
+    i_OR, i_AND, i_EOR, i_ORSR, i_ANDSR, i_EORSR,
+    i_SUB, i_SUBA, i_SUBX, i_SBCD,
+    i_ADD, i_ADDA, i_ADDX, i_ABCD,
+    i_NEG, i_NEGX, i_NBCD, i_CLR, i_NOT, i_TST,
+    i_BTST, i_BCHG, i_BCLR, i_BSET,
+    i_CMP, i_CMPM, i_CMPA,
+    i_MVPRM, i_MVPMR, i_MOVE, i_MOVEA, i_MVSR2, i_MV2SR,
+    i_SWAP, i_EXG, i_EXT, i_MVMEL, i_MVMLE,
+    i_TRAP, i_MVR2USP, i_MVUSP2R, i_RESET, i_NOP, i_STOP, i_RTE, i_RTD,
+    i_LINK, i_UNLK,
+    i_RTS, i_TRAPV, i_RTR,
+    i_JSR, i_JMP, i_BSR, i_Bcc,
+    i_LEA, i_PEA, i_DBcc, i_Scc,
+    i_DIVU, i_DIVS, i_MULU, i_MULS,
+    i_ASR, i_ASL, i_LSR, i_LSL, i_ROL, i_ROR, i_ROXL, i_ROXR,
+    i_ASRW, i_ASLW, i_LSRW, i_LSLW, i_ROLW, i_RORW, i_ROXLW, i_ROXRW,
+    i_CHK,i_CHK2,
+    i_MOVEC2, i_MOVE2C, i_CAS, i_CAS2, i_DIVL, i_MULL,
+    i_BFTST,i_BFEXTU,i_BFCHG,i_BFEXTS,i_BFCLR,i_BFFFO,i_BFSET,i_BFINS,
+    i_PACK, i_UNPK, i_TAS, i_BKPT, i_CALLM, i_RTM, i_TRAPcc, i_MOVES,
+    i_FPP, i_FDBcc, i_FScc, i_FTRAPcc, i_FBcc, i_FSAVE, i_FRESTORE,
+    i_CINVL, i_CINVP, i_CINVA, i_CPUSHL, i_CPUSHP, i_CPUSHA, i_MOVE16,
+    i_MMUOP030, i_PFLUSHN, i_PFLUSH, i_PFLUSHAN, i_PFLUSHA,
+    i_PLPAR, i_PLPAW, i_PTESTR, i_PTESTW,
+    i_LPSTOP,
+	MAX_OPCODE_FAMILY
+} ENUMNAME (instrmnem);
+
+struct mnemolookup {
+    instrmnem mnemo;
+    const TCHAR *name;
+    const TCHAR *friendlyname;
+};
+
+extern struct mnemolookup lookuptab[];
+
+ENUMDECL {
+    sz_byte, sz_word, sz_long, sz_single, sz_double, sz_extended, sz_packed
+} ENUMNAME (wordsizes);
+
+ENUMDECL {
+    fa_set, fa_unset, fa_zero, fa_one, fa_dontcare, fa_unknown, fa_isjmp,
+    fa_isbranch
+} ENUMNAME (flagaffect);
+
+ENUMDECL {
+    fu_used, fu_unused, fu_maybecc, fu_unknown, fu_isjmp
+} ENUMNAME (flaguse);
+
+ENUMDECL {
+    bit0, bit1, bitc, bitC, bitf, biti, bitI, bitj, bitJ, bitk, bitK,
+    bits, bitS, bitd, bitD, bitr, bitR, bitz, bitp, lastbit
+} ENUMNAME (bitvals);
+
+struct instr_def {
+    unsigned int bits;
+    int n_variable;
+    uae_u8 bitpos[16];
+    unsigned int mask;
+    int cpulevel;
+	int unimpcpulevel;
+    int plevel;
+    struct {
+	unsigned int flaguse:3;
+	unsigned int flagset:3;
+    } flaginfo[5];
+    uae_u8 sduse;
+    const TCHAR *opcstr;
+	// 68020/030 timing
+	int head, tail, clocks, fetchmode;
+};
+
+extern struct instr_def defs68k[];
+extern int n_defs68k;
+
+extern struct instr {
+    long int handler;
+    unsigned char dreg;
+    unsigned char sreg;
+    signed char dpos;
+    signed char spos;
+    unsigned char sduse;
+    int flagdead:8, flaglive:8;
+    unsigned int mnemo:8;
+    unsigned int cc:4;
+    unsigned int plev:2;
+    unsigned int size:2;
+	unsigned int unsized:1;
+    unsigned int smode:5;
+    unsigned int stype:3;
+    unsigned int dmode:5;
+    unsigned int suse:1;
+    unsigned int duse:1;
+    unsigned int unused1:1;
+    unsigned int clev:3, unimpclev:3;
+    unsigned int isjmp:1;
+    unsigned int unused2:1;
+	char head, tail, clocks, fetchmode;
+} *table68k;
+
+extern void read_table68k (void);
+extern void do_merges (void);
+extern int get_no_mismatches (void);
+extern int nr_cpuop_funcs;
+
+#endif /* READCPU_H */
+
diff --git a/src/cpu/rpt.h b/src/cpu/rpt.h
new file mode 100644
index 0000000..e4aea4a
--- /dev/null
+++ b/src/cpu/rpt.h
@@ -0,0 +1,16 @@
+/*
+  * UAE - The Un*x Amiga Emulator
+  *
+  * Definitions for accessing cycle counters on a given machine, if possible.
+  *
+  * Copyright 1997, 1998 Bernd Schmidt
+  * Copyright 1999 Brian King - Win32 specific
+  */
+#ifndef _RPT_H_
+#define _RPT_H_
+
+typedef unsigned long frame_time_t;
+extern frame_time_t read_processor_time (void);
+extern uae_u32 read_system_time (void);
+
+#endif
diff --git a/src/cpu/savestate.h b/src/cpu/savestate.h
new file mode 100644
index 0000000..165c2cd
--- /dev/null
+++ b/src/cpu/savestate.h
@@ -0,0 +1,265 @@
+ /*
+  * UAE - The Un*x Amiga Emulator
+  *
+  * Save/restore emulator state
+  *
+  * (c) 1999-2001 Toni Wilen
+  */
+
+
+/* functions to save byte,word or long word
+ * independent of CPU's endianess */
+
+#ifdef WINUAE_FOR_HATARI
+extern void save_u64(uae_u64 data);
+extern void save_u32(uae_u32 data);
+extern void save_u16(uae_u16 data);
+extern void save_u8(uae_u8 data);
+extern uae_u64 restore_u64(void);
+extern uae_u32 restore_u32(void);
+extern uae_u16 restore_u16(void);
+extern uae_u8 restore_u8(void);
+
+#else
+
+extern void save_store_pos_func (uae_u8 **);
+extern void save_store_size_func (uae_u8 **);
+extern void restore_store_pos_func (uae_u8 **);
+extern void restore_store_size_func (uae_u8 **);
+
+#define save_store_pos() save_store_pos_func (&dst)
+#define save_store_size() save_store_size_func (&dst)
+#define restore_store_pos() restore_store_pos_func (&src)
+#define restore_store_size() restore_store_size_func (&src)
+
+extern void save_u64_func (uae_u8 **, uae_u64);
+extern void save_u32_func (uae_u8 **, uae_u32);
+extern void save_u16_func (uae_u8 **, uae_u16);
+extern void save_u8_func (uae_u8 **, uae_u8);
+
+extern uae_u64 restore_u64_func (uae_u8 **);
+extern uae_u32 restore_u32_func (uae_u8 **);
+extern uae_u16 restore_u16_func (uae_u8 **);
+extern uae_u8 restore_u8_func (uae_u8 **);
+#endif
+
+extern void save_string_func (uae_u8 **, const TCHAR*);
+extern TCHAR *restore_string_func (uae_u8 **);
+
+#define SAVESTATE_PATH 0
+#define SAVESTATE_PATH_FLOPPY 1
+#define SAVESTATE_PATH_VDIR 2
+#define SAVESTATE_PATH_HDF 3
+#define SAVESTATE_PATH_HD 4
+#define SAVESTATE_PATH_CD 5
+
+extern void save_path_func (uae_u8 **, const TCHAR*, int type);
+extern TCHAR *restore_path_func (uae_u8 **, int type);
+
+#ifndef WINUAE_FOR_HATARI
+#define save_u64(x) save_u64_func (&dst, (x))
+#define save_u32(x) save_u32_func (&dst, (x))
+#define save_u16(x) save_u16_func (&dst, (x))
+#define save_u8(x) save_u8_func (&dst, (x))
+
+#define restore_u64() restore_u64_func (&src)
+#define restore_u32() restore_u32_func (&src)
+#define restore_u16() restore_u16_func (&src)
+#define restore_u8() restore_u8_func (&src)
+#endif
+
+#define save_string(x) save_string_func (&dst, (x))
+#define restore_string() restore_string_func (&src)
+
+#define save_path(x, p) save_path_func (&dst, (x), p)
+#define restore_path(p) restore_path_func (&src, p)
+
+
+/* save, restore and initialize routines for Amiga's subsystems */
+
+extern uae_u8 *restore_cpu (uae_u8 *);
+extern void restore_cpu_finish (void);
+extern uae_u8 *save_cpu (int *, uae_u8 *);
+extern uae_u8 *restore_cpu_extra (uae_u8 *);
+extern uae_u8 *save_cpu_extra (int *, uae_u8 *);
+extern uae_u8 *save_cpu_trace (int *, uae_u8 *);
+extern uae_u8 *restore_cpu_trace (uae_u8 *);
+
+extern uae_u8 *restore_mmu (uae_u8 *);
+extern uae_u8 *save_mmu (int *, uae_u8 *);
+
+extern uae_u8 *restore_fpu (uae_u8 *);
+extern uae_u8 *save_fpu (int *, uae_u8 *);
+
+extern uae_u8 *restore_disk (int, uae_u8 *);
+extern uae_u8 *save_disk (int, int *, uae_u8 *, bool);
+extern uae_u8 *restore_floppy (uae_u8 *src);
+extern uae_u8 *save_floppy (int *len, uae_u8 *);
+extern uae_u8 *save_disk2 (int num, int *len, uae_u8 *dstptr);
+extern uae_u8 *restore_disk2 (int num,uae_u8 *src);
+extern void DISK_save_custom  (uae_u32 *pdskpt, uae_u16 *pdsklen, uae_u16 *pdsksync, uae_u16 *pdskbytr);
+extern void DISK_restore_custom  (uae_u32 pdskpt, uae_u16 pdsklength, uae_u16 pdskbytr);
+extern void restore_disk_finish (void);
+
+extern uae_u8 *restore_custom (uae_u8 *);
+extern uae_u8 *save_custom (int *, uae_u8 *, int);
+extern uae_u8 *restore_custom_extra (uae_u8 *);
+extern uae_u8 *save_custom_extra (int *, uae_u8 *);
+
+extern uae_u8 *restore_custom_sprite (int num, uae_u8 *src);
+extern uae_u8 *save_custom_sprite (int num, int *len, uae_u8 *);
+
+extern uae_u8 *restore_custom_agacolors (uae_u8 *src);
+extern uae_u8 *save_custom_agacolors (int *len, uae_u8 *);
+
+extern uae_u8 *restore_custom_event_delay (uae_u8 *src);
+extern uae_u8 *save_custom_event_delay (int *len, uae_u8 *dstptr);
+
+extern uae_u8 *restore_blitter (uae_u8 *src);
+extern uae_u8 *save_blitter (int *len, uae_u8 *);
+extern uae_u8 *restore_blitter_new (uae_u8 *src);
+extern uae_u8 *save_blitter_new (int *len, uae_u8 *);
+extern void restore_blitter_finish (void);
+
+extern uae_u8 *restore_audio (int, uae_u8 *);
+extern uae_u8 *save_audio (int, int *, uae_u8 *);
+extern void restore_audio_finish (void);
+
+extern uae_u8 *restore_cia (int, uae_u8 *);
+extern uae_u8 *save_cia (int, int *, uae_u8 *);
+extern void restore_cia_finish (void);
+extern void restore_cia_start (void);
+
+extern uae_u8 *restore_expansion (uae_u8 *);
+extern uae_u8 *save_expansion (int *, uae_u8 *);
+
+extern uae_u8 *restore_p96 (uae_u8 *);
+extern uae_u8 *save_p96 (int *, uae_u8 *);
+extern void restore_p96_finish (void);
+
+extern uae_u8 *restore_keyboard (uae_u8 *);
+extern uae_u8 *save_keyboard (int *,uae_u8*);
+
+extern uae_u8 *restore_akiko (uae_u8 *src);
+extern uae_u8 *save_akiko (int *len, uae_u8*);
+extern void restore_akiko_finish (void);
+
+extern uae_u8 *restore_cdtv (uae_u8 *src);
+extern uae_u8 *save_cdtv (int *len, uae_u8*);
+extern void restore_cdtv_finish (void);
+
+extern uae_u8 *restore_cdtv_dmac (uae_u8 *src);
+extern uae_u8 *save_cdtv_dmac (int *len, uae_u8*);
+extern uae_u8 *restore_scsi_dmac (int wdtype, uae_u8 *src);
+extern uae_u8 *save_scsi_dmac (int wdtype, int *len, uae_u8*);
+
+extern uae_u8 *save_scsi_device (int wdtype, int num, int *len, uae_u8 *dstptr);
+extern uae_u8 *restore_scsi_device (int wdtype, uae_u8 *src);
+
+extern uae_u8 *save_scsidev (int num, int *len, uae_u8 *dstptr);
+extern uae_u8 *restore_scsidev (uae_u8 *src);
+
+extern uae_u8 *restore_filesys (uae_u8 *src);
+extern uae_u8 *save_filesys (int num, int *len);
+extern uae_u8 *restore_filesys_common (uae_u8 *src);
+extern uae_u8 *save_filesys_common (int *len);
+extern int save_filesys_cando(void);
+
+extern uae_u8 *restore_gayle(uae_u8 *src);
+extern uae_u8 *save_gayle (int *len, uae_u8*);
+extern uae_u8 *restore_gayle_ide (uae_u8 *src);
+extern uae_u8 *save_gayle_ide (int num, int *len, uae_u8*);
+
+extern uae_u8 *save_cd (int num, int *len);
+extern uae_u8 *restore_cd (int, uae_u8 *src);
+extern void restore_cd_finish (void);
+
+extern uae_u8 *save_configuration (int *len, bool fullconfig);
+extern uae_u8 *restore_configuration (uae_u8 *src);
+extern uae_u8 *save_log (int, int *len);
+//extern uae_u8 *restore_log (uae_u8 *src);
+
+extern uae_u8 *restore_input (uae_u8 *src);
+extern uae_u8 *save_input (int *len, uae_u8 *dstptr);
+
+extern uae_u8 *restore_inputstate (uae_u8 *src);
+extern uae_u8 *save_inputstate (int *len, uae_u8 *dstptr);
+extern void clear_inputstate (void);
+
+extern uae_u8 *save_a2065 (int *len, uae_u8 *dstptr);
+extern uae_u8 *restore_a2065 (uae_u8 *src);
+extern void restore_a2065_finish (void);
+
+extern uae_u8 *restore_debug_memwatch (uae_u8 *src);
+extern uae_u8 *save_debug_memwatch (int *len, uae_u8 *dstptr);
+extern void restore_debug_memwatch_finish (void);
+
+extern uae_u8 *save_cycles (int *len, uae_u8 *dstptr);
+extern uae_u8 *restore_cycles (uae_u8 *src);
+
+extern void restore_cram (int, size_t);
+extern void restore_bram (int, size_t);
+extern void restore_fram (int, size_t, int);
+extern void restore_zram (int, size_t, int);
+extern void restore_bootrom (int, size_t);
+extern void restore_pram (int, size_t);
+extern void restore_a3000lram (int, size_t);
+extern void restore_a3000hram (int, size_t);
+
+extern void restore_ram (size_t, uae_u8*);
+
+extern uae_u8 *save_cram (int *);
+extern uae_u8 *save_bram (int *);
+extern uae_u8 *save_fram (int *, int);
+extern uae_u8 *save_zram (int *, int);
+extern uae_u8 *save_bootrom (int *);
+extern uae_u8 *save_pram (int *);
+extern uae_u8 *save_a3000lram (int *);
+extern uae_u8 *save_a3000hram (int *);
+
+extern uae_u8 *restore_rom (uae_u8 *);
+extern uae_u8 *save_rom (int, int *, uae_u8 *);
+
+extern uae_u8 *restore_action_replay (uae_u8 *);
+extern uae_u8 *save_action_replay (int *, uae_u8 *);
+extern uae_u8 *restore_hrtmon (uae_u8 *);
+extern uae_u8 *save_hrtmon (int *, uae_u8 *);
+
+extern void savestate_initsave (const TCHAR *filename, int docompress, int nodialogs, bool save);
+extern int save_state (const TCHAR *filename, const TCHAR *description);
+extern void restore_state (const TCHAR *filename);
+extern void savestate_restore_finish (void);
+extern void savestate_memorysave (void);
+
+
+extern void custom_save_state (void);
+extern void custom_prepare_savestate (void);
+
+extern bool savestate_check (void);
+
+#define STATE_SAVE 1
+#define STATE_RESTORE 2
+#define STATE_DOSAVE 4
+#define STATE_DORESTORE 8
+#define STATE_REWIND 16
+#define STATE_DOREWIND 32
+
+extern int savestate_state;
+extern TCHAR savestate_fname[MAX_DPATH];
+extern struct zfile *savestate_file;
+
+STATIC_INLINE bool isrestore (void)
+{
+	return savestate_state == STATE_RESTORE || savestate_state == STATE_REWIND;
+}
+
+extern void savestate_quick (int slot, int save);
+
+extern void savestate_capture (int);
+extern void savestate_free (void);
+extern void savestate_init (void);
+extern void savestate_rewind (void);
+extern int savestate_dorewind (int);
+extern void savestate_listrewind (void);
+extern void statefile_save_recording (const TCHAR*);
+extern void savestate_capture_request (void);
diff --git a/src/cpu/sysconfig.h b/src/cpu/sysconfig.h
new file mode 100644
index 0000000..72718a5
--- /dev/null
+++ b/src/cpu/sysconfig.h
@@ -0,0 +1,184 @@
+/*
+  Hatari - sysconfig.h
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  This file contains needed auto generated includes and defines needed by WinUae CPU core.
+  The aim is to have minimum changes in WinUae CPU core for next updates
+*/
+
+#ifndef HATARI_SYSCONFIG_H
+#define HATARI_SYSCONFIG_H
+
+#define SUPPORT_THREADS
+#define MAX_DPATH 1000
+
+//#define X86_MSVC_ASSEMBLY
+#define X86_MSVC_ASSEMBLY_MEMACCESS
+#define OPTIMIZED_FLAGS
+//#define __i386__
+
+#ifndef UAE_MINI
+
+//#define DEBUGGER
+#define FILESYS /* filesys emulation */
+#define UAE_FILESYS_THREADS
+//#define AUTOCONFIG /* autoconfig support, fast ram, harddrives etc.. */
+//#define JIT /* JIT compiler support */
+#define NATMEM_OFFSET natmem_offset
+#define USE_NORMAL_CALLING_CONVENTION 0
+#define USE_X86_FPUCW 1
+#define WINDDK /* Windows DDK available, keyboard leds and harddrive support */
+#define CATWEASEL /* Catweasel MK2/3 support */
+#define AHI /* AHI sound emulation */
+#define ENFORCER /* UAE Enforcer */
+#define ECS_DENISE /* ECS DENISE new features */
+#define AGA /* AGA chipset emulation (ECS_DENISE must be enabled) */
+#define CD32 /* CD32 emulation */
+#define CDTV /* CDTV emulation */
+#define D3D /* D3D display filter support */
+//#define OPENGL /* OpenGL display filter support */
+#define PARALLEL_PORT /* parallel port emulation */
+#define PARALLEL_DIRECT /* direct parallel port emulation */
+#define SERIAL_PORT /* serial port emulation */
+#define SERIAL_ENET /* serial port UDP transport */
+#define SCSIEMU /* uaescsi.device emulation */
+#define UAESERIAL /* uaeserial.device emulation */
+#define FPUEMU /* FPU emulation */
+#define FPU_UAE
+//#define WITH_SOFTFLOAT
+#define MMUEMU /* Aranym 68040 MMU */
+#define FULLMMU /* Aranym 68040 MMU */
+#define CPUEMU_0 /* generic 680x0 emulation with direct memory access */
+#define CPUEMU_11 /* 68000/68010 prefetch emulation */
+#define CPUEMU_13 /* 68000/68010 cycle-exact cpu&blitter */
+#define CPUEMU_20 /* 68020 prefetch */
+#define CPUEMU_21 /* 68020 "cycle-exact" + blitter */
+#define CPUEMU_22 /* 68030 prefetch */
+#define CPUEMU_23 /* 68030 "cycle-exact" + blitter */
+#define CPUEMU_24 /* 68060 "cycle-exact" + blitter */
+#define CPUEMU_25 /* 68040 "cycle-exact" + blitter */
+#define CPUEMU_31 /* Aranym 68040 MMU */
+#define CPUEMU_32 /* Previous 68030 MMU */
+#define CPUEMU_33 /* 68060 MMU */
+#define CPUEMU_40 /* generic 680x0 with indirect memory access */
+//#define ACTION_REPLAY /* Action Replay 1/2/3 support */
+#define PICASSO96 /* Picasso96 display card emulation */
+#define UAEGFX_INTERNAL /* built-in libs:picasso96/uaegfx.card */
+#define BSDSOCKET /* bsdsocket.library emulation */
+#define CAPS /* CAPS-image support */
+#define FDI2RAW /* FDI 1.0 and 2.x image support */
+#define AVIOUTPUT /* Avioutput support */
+#define PROWIZARD /* Pro-Wizard module ripper */
+#define ARCADIA /* Arcadia arcade system */
+#define ARCHIVEACCESS /* ArchiveAccess decompression library */
+#define LOGITECHLCD /* Logitech G15 LCD */
+#define SAVESTATE /* State file support */
+#define A2091 /* A590/A2091 SCSI */
+#define A2065 /* A2065 Ethernet card */
+#define NCR /* A4000T/A4091, 53C710/53C770 SCSI */
+#define NCR9X /* 53C9X SCSI */
+#define SANA2 /* SANA2 network driver */
+#define AMAX /* A-Max ROM adapater emulation */
+#define RETROPLATFORM /* Cloanto RetroPlayer support */
+
+#else
+
+/* #define SINGLEFILE */
+
+#define CUSTOM_SIMPLE /* simplified custom chipset emulation */
+#define CPUEMU_0
+#define CPUEMU_68000_ONLY /* drop 68010+ commands from CPUEMU_0 */
+#define ADDRESS_SPACE_24BIT
+#ifndef UAE_NOGUI
+#define D3D
+#define OPENGL
+#endif
+#define CAPS
+#define CPUEMU_13
+#define CPUEMU_11
+
+
+#endif
+
+#define WITH_SCSI_IOCTL
+#define WITH_SCSI_SPTI
+
+#define UAE_RAND_MAX RAND_MAX
+
+#ifdef _DEBUG
+#define _CRTDBG_MAP_ALLOC
+#include 
+#include 
+#endif
+
+#ifdef WIN64
+#undef X86_MSVC_ASSEMBLY_MEMACCESS
+#undef X86_MSVC_ASSEMBLY
+#undef JIT
+#define X64_MSVC_ASSEMBLY
+#define CPU_64_BIT
+#define SIZEOF_VOID_P 8
+#else
+#define SIZEOF_VOID_P 4
+#endif
+
+#if !defined(AHI)
+#undef ENFORCER
+#endif
+
+/* Define if utime(file, NULL) sets file's timestamp to the present.  */
+#define HAVE_UTIME_NULL 1
+
+/* Define as __inline if that's what the C compiler calls it.  */
+/* #undef inline */
+#define __inline__ __inline
+#define __volatile__ volatile
+
+/* Define as the return type of signal handlers (int or void).  */
+#define RETSIGTYPE void
+
+/* Define if you have the ANSI C header files.  */
+#define STDC_HEADERS 1
+
+/* Define if you can safely include both  and .  */
+#ifdef __GNUC__
+#define TIME_WITH_SYS_TIME 1
+#endif
+
+#ifdef _WIN32_WCE
+#define NO_TIME_H 1
+#endif
+
+/* Define if the X Window System is missing or not being used.  */
+#define X_DISPLAY_MISSING 1
+
+/* The number of bytes in a __int64.  */
+#define SIZEOF___INT64 8
+
+/* The number of bytes in a char.  */
+#define SIZEOF_CHAR 1
+
+/* The number of bytes in a int.  */
+#define SIZEOF_INT 4
+
+/* The number of bytes in a long.  */
+#define SIZEOF_LONG 4
+
+/* The number of bytes in a long long.  */
+#define SIZEOF_LONG_LONG 8
+
+/* The number of bytes in a short.  */
+#define SIZEOF_SHORT 2
+
+#define SIZEOF_FLOAT 4
+#define SIZEOF_DOUBLE 8
+
+#define HAVE_ISNAN
+#define HAVE_ISINF
+
+/* Define to 1 if `S_un' is a member of `struct in_addr'. */
+#define HAVE_STRUCT_IN_ADDR_S_UN 1
+
+#endif
diff --git a/src/cpu/sysdeps.h b/src/cpu/sysdeps.h
new file mode 100644
index 0000000..eb2769f
--- /dev/null
+++ b/src/cpu/sysdeps.h
@@ -0,0 +1,586 @@
+#ifndef UAE_SYSDEPS_H
+#define UAE_SYSDEPS_H
+
+/*
+  * UAE - The Un*x Amiga Emulator
+  *
+  * Try to include the right system headers and get other system-specific
+  * stuff right & other collected kludges.
+  *
+  * If you think about modifying this, think twice. Some systems rely on
+  * the exact order of the #include statements. That's also the reason
+  * why everything gets included unconditionally regardless of whether
+  * it's actually needed by the .c file.
+  *
+  * Copyright 1996, 1997 Bernd Schmidt
+  */
+//#include 
+//using namespace std;
+
+#include 
+#include 
+#include 
+#include 
+#include 
+//#include 
+#include "compat.h"
+
+#ifndef __STDC__
+#ifndef _MSC_VER
+#error "Your compiler is not ANSI. Get a real one."
+#endif
+#endif
+
+#include 
+
+#ifdef HAVE_SYS_TYPES_H
+#include 
+#endif
+
+#ifdef HAVE_VALUES_H
+#include 
+#endif
+
+#ifdef HAVE_STRINGS_H
+#include 
+#endif
+#ifdef HAVE_STRING_H
+#include 
+#endif
+
+#ifdef HAVE_UNISTD_H
+#include 
+#endif
+#ifdef HAVE_FCNTL_H
+#include 
+#endif
+
+#ifdef HAVE_UTIME_H
+#include 
+#endif
+
+#ifdef HAVE_SYS_STAT_H
+#include 
+#endif
+
+#if TIME_WITH_SYS_TIME
+# include 
+# include 
+#else
+# if HAVE_SYS_TIME_H
+#  include 
+# else
+#  include 
+# endif
+#endif
+
+#if HAVE_DIRENT_H
+# include 
+#else
+# define dirent direct
+# if HAVE_SYS_NDIR_H
+#  include 
+# endif
+# if HAVE_SYS_DIR_H
+#  include 
+# endif
+# if HAVE_NDIR_H
+#  include 
+# endif
+#endif
+
+#ifdef HAVE_SYS_UTIME_H
+# include 
+#endif
+
+#include 
+#include 
+
+#if EEXIST == ENOTEMPTY
+#define BROKEN_OS_PROBABLY_AIX
+#endif
+
+#ifdef __NeXT__
+#define S_IRUSR S_IREAD
+#define S_IWUSR S_IWRITE
+#define S_IXUSR S_IEXEC
+#define S_ISDIR(val) (S_IFDIR & val)
+struct utimbuf
+{
+    time_t actime;
+    time_t modtime;
+};
+#endif
+
+#if defined(__GNUC__) && defined(AMIGA)
+/* gcc on the amiga need that __attribute((regparm)) must */
+/* be defined in function prototypes as well as in        */
+/* function definitions !                                 */
+#define REGPARAM2 REGPARAM
+#else /* not(GCC & AMIGA) */
+#define REGPARAM2
+#endif
+
+/* sam: some definitions so that SAS/C can compile UAE */
+#if defined(__SASC) && defined(AMIGA)
+#define REGPARAM2
+#define REGPARAM
+#define S_IRUSR S_IREAD
+#define S_IWUSR S_IWRITE
+#define S_IXUSR S_IEXECUTE
+#define S_ISDIR(val) (S_IFDIR & val)
+#define mkdir(x,y) mkdir(x)
+#define truncate(x,y) 0
+#define creat(x,y) open("T:creat",O_CREAT|O_TEMP|O_RDWR) /* sam: for zfile.c */
+#define strcasecmp stricmp
+#define utime(file,time) 0
+struct utimbuf
+{
+    time_t actime;
+    time_t modtime;
+};
+#endif
+
+#if defined(WARPUP)
+#include "devices/timer.h"
+#include "osdep/posixemu.h"
+#define REGPARAM
+#define REGPARAM2
+#define RETSIGTYPE
+#define USE_ZFILE
+#define strcasecmp stricmp
+#define memcpy q_memcpy
+#define memset q_memset
+#define strdup my_strdup
+#define random uaerand
+#define creat(x,y) open("T:creat",O_CREAT|O_RDWR|O_TRUNC,777)
+extern void* q_memset(void*,int,size_t);
+extern void* q_memcpy(void*,const void*,size_t);
+#endif
+
+#ifdef __DOS__
+#include 
+#include 
+#endif
+
+/* Acorn specific stuff */
+#ifdef ACORN
+
+#define S_IRUSR S_IREAD
+#define S_IWUSR S_IWRITE
+#define S_IXUSR S_IEXEC
+
+#define strcasecmp stricmp
+
+#endif
+
+#ifndef L_tmpnam
+#define L_tmpnam 128 /* ought to be safe */
+#endif
+
+/* If char has more then 8 bits, good night. */
+typedef unsigned char uae_u8;
+typedef signed char uae_s8;
+typedef char uae_char;
+
+typedef struct { uae_u8 RGB[3]; } RGB;
+
+#if SIZEOF_SHORT == 2
+typedef unsigned short uae_u16;
+typedef short uae_s16;
+#elif SIZEOF_INT == 2
+typedef unsigned int uae_u16;
+typedef int uae_s16;
+#else
+#error No 2 byte type, you lose.
+#endif
+
+#if SIZEOF_INT == 4
+typedef unsigned int uae_u32;
+typedef int uae_s32;
+#elif SIZEOF_LONG == 4
+typedef unsigned long uae_u32;
+typedef long uae_s32;
+#else
+#error No 4 byte type, you lose.
+#endif
+
+typedef uae_u32 uaecptr;
+
+#undef uae_s64
+#undef uae_u64
+
+#if SIZEOF_LONG_LONG == 8
+#define uae_s64 long long
+#define uae_u64 unsigned long long
+#define VAL64(a) (a ## LL)
+#define UVAL64(a) (a ## uLL)
+#elif SIZEOF___INT64 == 8
+#define uae_s64 __int64
+#define uae_u64 unsigned __int64
+#define VAL64(a) (a)
+#define UVAL64(a) (a)
+#elif SIZEOF_LONG == 8
+#define uae_s64 long;
+#define uae_u64 unsigned long;
+#define VAL64(a) (a ## l)
+#define UVAL64(a) (a ## ul)
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifdef HAVE_STRDUP
+#define my_strdup _tcsdup
+#else
+extern TCHAR *my_strdup (const TCHAR*s);
+#endif
+extern TCHAR *my_strdup_ansi (const char*);
+extern TCHAR *au (const char*);
+extern char *ua (const TCHAR*);
+extern TCHAR *aucp (const char *s, unsigned int cp);
+extern char *uacp (const TCHAR *s, unsigned int cp);
+extern TCHAR *au_fs (const char*);
+extern char *ua_fs (const TCHAR*, int);
+extern char *ua_copy (char *dst, int maxlen, const TCHAR *src);
+extern TCHAR *au_copy (TCHAR *dst, int maxlen, const char *src);
+extern char *ua_fs_copy (char *dst, int maxlen, const TCHAR *src, int defchar);
+extern TCHAR *au_fs_copy (TCHAR *dst, int maxlen, const char *src);
+extern char *uutf8 (const TCHAR *s);
+extern TCHAR *utf8u (const char *s);
+extern void unicode_init (void);
+extern void to_lower (TCHAR *s, int len);
+extern void to_upper (TCHAR *s, int len);
+/* We can only rely on GNU C getting enums right. Mickeysoft VSC++ is known
+ * to have problems, and it's likely that other compilers choke too. */
+#ifdef __GNUC__
+#define ENUMDECL typedef enum
+#define ENUMNAME(name) name
+
+/* While we're here, make abort more useful.  */
+/*#define abort() \
+  do { \
+    write_log ("Internal error; file %s, line %d\n", __FILE__, __LINE__); \
+    (abort) (); \
+} while (0)
+*/#else
+#define ENUMDECL enum
+#define ENUMNAME(name) ; typedef int name
+#endif
+
+/*
+ * Porters to weird systems, look! This is the preferred way to get
+ * filesys.c (and other stuff) running on your system. Define the
+ * appropriate macros and implement wrappers in a machine-specific file.
+ *
+ * I guess the Mac port could use this (Ernesto?)
+ */
+
+#undef DONT_HAVE_POSIX
+#undef DONT_HAVE_REAL_POSIX /* define if open+delete doesn't do what it should */
+#undef DONT_HAVE_STDIO
+#undef DONT_HAVE_MALLOC
+
+#if defined(WARPUP)
+#define DONT_HAVE_POSIX
+#endif
+
+#if defined _WIN32
+
+#if defined __WATCOMC__
+
+#define O_NDELAY 0
+#include 
+#define dirent direct
+#define mkdir(a,b) mkdir(a)
+#define strcasecmp stricmp
+
+#elif defined __MINGW32__
+
+#define O_NDELAY 0
+#define mkdir(a,b) mkdir(a)
+
+#elif defined _MSC_VER
+
+#ifdef HAVE_GETTIMEOFDAY
+#include  // for 'struct timeval' definition
+extern void gettimeofday( struct timeval *tv, void *blah );
+#endif
+
+#define O_NDELAY 0
+
+#define FILEFLAG_DIR     0x1
+#define FILEFLAG_ARCHIVE 0x2
+#define FILEFLAG_WRITE   0x4
+#define FILEFLAG_READ    0x8
+#define FILEFLAG_EXECUTE 0x10
+#define FILEFLAG_SCRIPT  0x20
+#define FILEFLAG_PURE    0x40
+
+#ifdef REGPARAM2
+#undef REGPARAM2
+#endif
+#define REGPARAM2 __fastcall
+#define REGPARAM3 __fastcall
+#define REGPARAM
+
+#include 
+#define O_BINARY _O_BINARY
+#define O_WRONLY _O_WRONLY
+#define O_RDONLY _O_RDONLY
+#define O_RDWR   _O_RDWR
+#define O_CREAT  _O_CREAT
+#define O_TRUNC  _O_TRUNC
+#define strcasecmp _tcsicmp 
+#define strncasecmp _tcsncicmp 
+#define W_OK 0x2
+#define R_OK 0x4
+#define STAT struct stat
+#define DIR struct DIR
+struct direct
+{
+    TCHAR d_name[1];
+};
+#include 
+#define utimbuf __utimbuf64
+#define USE_ZFILE
+
+#undef S_ISDIR
+#undef S_IWUSR
+#undef S_IRUSR
+#undef S_IXUSR
+#define S_ISDIR(a) (a&FILEFLAG_DIR)
+#define S_ISARC(a) (a&FILEFLAG_ARCHIVE)
+#define S_IWUSR FILEFLAG_WRITE
+#define S_IRUSR FILEFLAG_READ
+#define S_IXUSR FILEFLAG_EXECUTE
+
+/* These are prototypes for functions from the Win32 posixemu file */
+extern void get_time (time_t t, long* days, long* mins, long* ticks);
+extern time_t put_time (long days, long mins, long ticks);
+
+/* #define DONT_HAVE_POSIX - don't need all of Mathias' posixemu_functions, just a subset (below) */
+#define chmod(a,b) posixemu_chmod ((a), (b))
+extern int posixemu_chmod (const TCHAR *, int);
+#define stat(a,b) posixemu_stat ((a), (b))
+extern int posixemu_stat (const TCHAR *, struct _stat64 *);
+#define mkdir(x,y) mkdir(x)
+#define truncate posixemu_truncate
+extern int posixemu_truncate (const TCHAR *, long int);
+#define utime posixemu_utime
+extern int posixemu_utime (const TCHAR *, struct utimbuf *);
+#define opendir posixemu_opendir
+extern DIR * posixemu_opendir (const TCHAR *);
+#define readdir posixemu_readdir
+extern struct dirent* posixemu_readdir (DIR *);
+#define closedir posixemu_closedir
+extern void posixemu_closedir (DIR *);
+
+#endif
+
+#endif /* _WIN32 */
+
+#ifdef DONT_HAVE_POSIX
+
+#define access posixemu_access
+extern int posixemu_access (const TCHAR *, int);
+#define open posixemu_open
+extern int posixemu_open (const TCHAR *, int, int);
+#define close posixemu_close
+extern void posixemu_close (int);
+#define read posixemu_read
+extern int posixemu_read (int, TCHAR *, int);
+#define write posixemu_write
+extern int posixemu_write (int, const TCHAR *, int);
+#undef lseek
+#define lseek posixemu_seek
+extern int posixemu_seek (int, int, int);
+#define stat(a,b) posixemu_stat ((a), (b))
+extern int posixemu_stat (const TCHAR *, STAT *);
+#define mkdir posixemu_mkdir
+extern int mkdir (const TCHAR *, int);
+#define rmdir posixemu_rmdir
+extern int posixemu_rmdir (const TCHAR *);
+#define unlink posixemu_unlink
+extern int posixemu_unlink (const TCHAR *);
+#define truncate posixemu_truncate
+extern int posixemu_truncate (const TCHAR *, long int);
+#define rename posixemu_rename
+extern int posixemu_rename (const TCHAR *, const TCHAR *);
+#define chmod posixemu_chmod
+extern int posixemu_chmod (const TCHAR *, int);
+#define tmpnam posixemu_tmpnam
+extern void posixemu_tmpnam (TCHAR *);
+#define utime posixemu_utime
+extern int posixemu_utime (const TCHAR *, struct utimbuf *);
+#define opendir posixemu_opendir
+extern DIR * posixemu_opendir (const TCHAR *);
+#define readdir posixemu_readdir
+extern struct dirent* readdir (DIR *);
+#define closedir posixemu_closedir
+extern void closedir (DIR *);
+
+/* This isn't the best place for this, but it fits reasonably well. The logic
+ * is that you probably don't have POSIX errnos if you don't have the above
+ * functions. */
+extern long dos_errno (void);
+
+#endif
+
+#ifdef DONT_HAVE_STDIO
+
+extern FILE *stdioemu_fopen (const TCHAR *, const TCHAR *);
+#define fopen(a,b) stdioemu_fopen(a, b)
+extern int stdioemu_fseek (FILE *, int, int);
+#define fseek(a,b,c) stdioemu_fseek(a, b, c)
+extern int stdioemu_fread (TCHAR *, int, int, FILE *);
+#define fread(a,b,c,d) stdioemu_fread(a, b, c, d)
+extern int stdioemu_fwrite (const TCHAR *, int, int, FILE *);
+#define fwrite(a,b,c,d) stdioemu_fwrite(a, b, c, d)
+extern int stdioemu_ftell (FILE *);
+#define ftell(a) stdioemu_ftell(a)
+extern int stdioemu_fclose (FILE *);
+#define fclose(a) stdioemu_fclose(a)
+
+#endif
+
+#ifdef DONT_HAVE_MALLOC
+
+#define malloc(a) mallocemu_malloc(a)
+extern void *mallocemu_malloc (int size);
+#define free(a) mallocemu_free(a)
+extern void mallocemu_free (void *ptr);
+
+#endif
+
+#ifdef X86_ASSEMBLY
+#define ASM_SYM_FOR_FUNC(a) __asm__(a)
+#else
+#define ASM_SYM_FOR_FUNC(a)
+#endif
+
+//#include "target.h"
+
+#ifdef UAE_CONSOLE
+#undef write_log
+#define write_log write_log_standard
+#endif
+
+#if __GNUC__ - 1 > 1 || __GNUC_MINOR__ - 1 > 6
+extern void write_log (const TCHAR *, ...) __attribute__ ((format (printf, 1, 2)));
+#else
+extern void write_log (const TCHAR *, ...);
+#endif
+extern void write_dlog (const TCHAR *, ...);
+extern int read_log(void);
+
+extern void flush_log (void);
+extern void close_console (void);
+extern void reopen_console (void);
+//extern void console_out (const TCHAR *);
+//extern void console_out_f (const TCHAR *, ...);
+extern void console_flush (void);
+extern int console_get (TCHAR *, int);
+extern TCHAR console_getch (void);
+//extern void f_out (void *, const TCHAR *, ...);
+extern TCHAR* buf_out (TCHAR *buffer, int *bufsize, const TCHAR *format, ...);
+//extern void gui_message (const TCHAR *,...);
+extern int gui_message_multibutton (int flags, const TCHAR *format,...);
+#define write_log_err write_log
+extern void logging_init (void);
+extern FILE *log_open (const TCHAR *name, int append, int bootlog);
+extern void log_close (FILE *f);
+
+
+#ifndef O_BINARY
+#define O_BINARY 0
+#endif
+
+#ifndef STATIC_INLINE
+#if __GNUC__ - 1 > 1 && __GNUC_MINOR__ - 1 >= 0
+#define STATIC_INLINE static __inline__ __attribute__ ((always_inline))
+#define NOINLINE __attribute__ ((noinline))
+#define NORETURN __attribute__ ((noreturn))
+#elif _MSC_VER
+#define STATIC_INLINE static __forceinline
+#define NOINLINE __declspec(noinline)
+#define NORETURN __declspec(noreturn)
+#else
+#define STATIC_INLINE static __inline__
+#define NOINLINE
+#define NORETURN
+#endif
+#endif
+
+/* Every Amiga hardware clock cycle takes this many "virtual" cycles.  This
+   used to be hardcoded as 1, but using higher values allows us to time some
+   stuff more precisely.
+   512 is the official value from now on - it can't change, unless we want
+   _another_ config option "finegrain2_m68k_speed".
+
+   We define this value here rather than in events.h so that gencpu.c sees
+   it.  */
+#define CYCLE_UNIT 512
+
+/* This one is used by cfgfile.c.  We could reduce the CYCLE_UNIT back to 1,
+   I'm not 100% sure this code is bug free yet.  */
+#define OFFICIAL_CYCLE_UNIT 512
+
+/*
+ * You can specify numbers from 0 to 5 here. It is possible that higher
+ * numbers will make the CPU emulation slightly faster, but if the setting
+ * is too high, you will run out of memory while compiling.
+ * Best to leave this as it is.
+ */
+#define CPU_EMU_SIZE 0
+
+/*
+ * Byte-swapping functions
+ */
+
+/* Try to use system bswap_16/bswap_32 functions. */
+#if defined HAVE_BSWAP_16 && defined HAVE_BSWAP_32
+# include 
+#  ifdef HAVE_BYTESWAP_H
+#  include 
+# endif
+#else
+/* Else, if using SDL, try SDL's endian functions. */
+# ifdef USE_SDL
+#  include 
+#  define bswap_16(x) SDL_Swap16(x)
+#  define bswap_32(x) SDL_Swap32(x)
+# else
+/* Otherwise, we'll roll our own. */
+#  define bswap_16(x) (((x) >> 8) | (((x) & 0xFF) << 8))
+#  define bswap_32(x) (((x) << 24) | (((x) << 8) & 0x00FF0000) | (((x) >> 8) & 0x0000FF00) | ((x) >> 24))
+# endif
+#endif
+
+#endif
+
+#ifndef __cplusplus
+
+#define xmalloc(T, N) malloc(sizeof (T) * (N))
+#define xcalloc(T, N) calloc(sizeof (T), N)
+#define xfree(T) free(T)
+#define xrealloc(T, TP, N) realloc(TP, sizeof (T) * (N))
+
+#if 0
+extern void *xmalloc (size_t);
+extern void *xcalloc (size_t, size_t);
+extern void xfree (const void*);
+#endif
+
+#else
+
+#define xmalloc(T, N) static_cast(malloc (sizeof (T) * (N)))
+#define xcalloc(T, N) static_cast(calloc (sizeof (T), N))
+#define xrealloc(T, TP, N) static_cast(realloc (TP, sizeof (T) * (N)))
+#define xfree(T) free(T)
+
+#endif
diff --git a/src/cpu/table68k b/src/cpu/table68k
new file mode 100644
index 0000000..3652398
--- /dev/null
+++ b/src/cpu/table68k
@@ -0,0 +1,518 @@
+% 0: bit 0
+% 1: bit 1
+% c: condition code
+% C: condition codes, except F
+% f: direction
+% i: immediate
+% I: immediate, except 00 and ff
+% j: immediate 1..8
+% J: immediate 0..15
+% k: immediate 0..7
+% K: immediate 0..63
+% p: immediate 0..3 (CINV and CPUSH: cache field)
+% s: source mode
+% S: source reg
+% d: dest mode
+% D: dest reg
+% r: reg
+% z: size
+%
+% Actually, a sssSSS may appear as a destination, and
+% vice versa. The only difference between sssSSS and
+% dddDDD are the valid addressing modes. There is
+% no match for immediate and pc-rel. addressing modes
+% in case of dddDDD.
+%
+% Arp: --> -(Ar)
+% ArP: --> (Ar)+
+% Ara: --> (Ar)
+% L: (xxx.L)
+%
+% Fields on a line: 
+% 16 chars bitpattern : 
+% CPU level / privilege level :
+%   CPU level 0: 68000
+%             1: 68010
+%             2: 68020
+%             3: 68030
+%             4: 68040
+%             5: 68060
+%			  [Everything from 68020 possibly allows for FPU emulation]
+%   Unimplemented after:
+%             0: Normal
+%             3: Not implemented in 68030 and later
+%             4: Not implemented in 68040 and later
+%             5: Not implemented in 68060
+%   privilege level 0: not privileged
+%                   1: unprivileged only on 68000 (check regs.s)
+%                   2: privileged                 (check regs.s)
+%                   3: privileged if size == word (check regs.s)
+% Flags set by instruction: XNZVC :
+% Flags used by instruction: XNZVC :
+%   - means flag unaffected / unused
+%   0 means flag reset
+%   1 means flag set
+%   ? means programmer was too lazy to check or instruction may trap
+%   + means instruction is conditional branch 
+%     everything else means flag set/used
+%   / means instruction is unconditional branch/call
+%   x means flag is unknown and well-behaved programs shouldn't check it
+% srcaddr status destaddr status :
+%   bitmasks of
+%   1 means fetched
+%   2 means stored
+%   4 means jump offset
+%   8 means jump address
+% instruction
+% optional line feed and 68030 Head/Tail/Cycles/ea calculation
+%
+
+0000 0000 0011 1100:000:XNZVC:XNZVC:10: ORSR.B  #1
+0000 0000 0111 1100:002:?????:?????:10: ORSR.W  #1
+0000 0zz0 11ss sSSS:250:?????:?????:11: CHK2.z  #1,s[!Dreg,Areg,Aipi,Apdi,Immd]
+
+0000 0000 zzdd dDDD:000:-NZ00:-----:13: OR.z    #z,d[Dreg]
+- 2 0 2 fiea
+0000 0000 zzdd dDDD:000:-NZ00:-----:13: OR.z    #z,d[!Areg,Dreg]
+- 0 1 3 fiea
+
+0000 0010 0011 1100:000:XNZVC:XNZVC:10: ANDSR.B #1
+0000 0010 0111 1100:002:?????:?????:10: ANDSR.W #1
+
+0000 0010 zzdd dDDD:000:-NZ00:-----:13: AND.z   #z,d[Dreg]
+- 2 0 2 fiea
+0000 0010 zzdd dDDD:000:-NZ00:-----:13: AND.z   #z,d[!Areg,Dreg]
+- 0 1 3 fiea
+0000 0100 zzdd dDDD:000:XNZVC:-----:13: SUB.z   #z,d[Dreg]
+- 2 0 2 fiea
+0000 0100 zzdd dDDD:000:XNZVC:-----:13: SUB.z   #z,d[!Areg,Dreg]
+- 0 1 3 fiea
+0000 0110 zzdd dDDD:000:XNZVC:-----:13: ADD.z   #z,d[Dreg]
+- 2 0 2 fiea
+0000 0110 zzdd dDDD:000:XNZVC:-----:13: ADD.z   #z,d[!Areg,Dreg]
+- 0 1 3 fiea
+
+0000 0110 11ss sSSS:230:?????:?????:10: CALLM   s[!Dreg,Areg,Aipi,Apdi,Immd]
+0000 0110 11ss sSSS:230:?????:?????:10: RTM     s[Dreg,Areg]
+
+0000 1000 00ss sSSS:000:--Z--:-----:11: BTST    #1,s[Dreg]
+- 4 0 4
+0000 1000 00ss sSSS:000:--Z--:-----:11: BTST    #1,s[!Areg,Dreg,Immd]
+- 0 0 4 fiea
+0000 1000 01ss sSSS:000:--Z--:-----:13: BCHG    #1,s[Dreg]
+- 6 0 6
+0000 1000 01ss sSSS:000:--Z--:-----:13: BCHG    #1,s[!Areg,Dreg,Immd,PC8r,PC16]
+- 0 0 6 fiea
+0000 1000 10ss sSSS:000:--Z--:-----:13: BCLR    #1,s[Dreg]
+- 6 0 6
+0000 1000 10ss sSSS:000:--Z--:-----:13: BCLR    #1,s[!Areg,Dreg,Immd,PC8r,PC16]
+- 0 0 6 fiea
+0000 1000 11ss sSSS:000:--Z--:-----:13: BSET    #1,s[Dreg]
+- 6 0 6
+0000 1000 11ss sSSS:000:--Z--:-----:13: BSET    #1,s[!Areg,Dreg,Immd,PC8r,PC16]
+- 0 0 6 fiea
+
+0000 1010 0011 1100:000:XNZVC:XNZVC:10: EORSR.B #1
+0000 1010 0111 1100:002:?????:?????:10: EORSR.W #1
+
+0000 1010 zzdd dDDD:000:-NZ00:-----:13: EOR.z   #z,d[Dreg]
+- 2 0 2 fiea
+0000 1010 zzdd dDDD:000:-NZ00:-----:13: EOR.z   #z,d[!Areg,Dreg]
+- 0 1 3 fiea
+0000 1100 zzss sSSS:000:-NZVC:-----:11: CMP.z   #z,s[Dreg]
+- 2 0 2 fiea
+0000 1100 zzss sSSS:000:-NZVC:-----:11: CMP.z   #z,s[!Areg,Dreg,Immd,PC8r,PC16]
+- 0 0 2 fiea
+0000 1100 zzss sSSS:200:-NZVC:-----:11: CMP.z   #z,s[PC8r,PC16]
+- 0 0 2 fiea
+
+0000 1010 11ss sSSS:200:?????:?????:13: CAS.B   #1,s[!Dreg,Areg,Immd,PC8r,PC16]
+0000 1100 11ss sSSS:200:?????:?????:13: CAS.W   #1,s[!Dreg,Areg,Immd,PC8r,PC16]
+0000 1100 1111 1100:250:?????:?????:10: CAS2.W  #2
+0000 1110 zzss sSSS:202:?????:?????:13: MOVES.z #1,s[!Dreg,Areg,Immd,PC8r,PC16]
+0000 1110 11ss sSSS:200:?????:?????:13: CAS.L   #1,s[!Dreg,Areg,Immd,PC8r,PC16]
+0000 1110 1111 1100:250:?????:?????:10: CAS2.L  #2
+
+0000 rrr1 00dd dDDD:050:-----:-----:12: MVPMR.W d[Areg-Ad16],Dr
+0000 rrr1 01dd dDDD:050:-----:-----:12: MVPMR.L d[Areg-Ad16],Dr
+0000 rrr1 10dd dDDD:050:-----:-----:12: MVPRM.W Dr,d[Areg-Ad16]
+0000 rrr1 11dd dDDD:050:-----:-----:12: MVPRM.L Dr,d[Areg-Ad16]
+
+0000 rrr1 00ss sSSS:000:--Z--:-----:11: BTST    Dr,s[Dreg]
+- 4 0 4
+0000 rrr1 00ss sSSS:000:--Z--:-----:11: BTST    Dr,s[!Areg,Dreg]
+- 0 0 4 fea
+0000 rrr1 01ss sSSS:000:--Z--:-----:13: BCHG    Dr,s[Dreg]
+- 6 0 6
+0000 rrr1 01ss sSSS:000:--Z--:-----:13: BCHG    Dr,s[!Areg,Dreg,Immd,PC8r,PC16]
+- 0 0 6 fea
+0000 rrr1 10ss sSSS:000:--Z--:-----:13: BCLR    Dr,s[Dreg]
+- 6 0 6
+0000 rrr1 10ss sSSS:000:--Z--:-----:13: BCLR    Dr,s[!Areg,Dreg,Immd,PC8r,PC16]
+- 0 0 6 fea
+0000 rrr1 11ss sSSS:000:--Z--:-----:13: BSET    Dr,s[Dreg]
+- 6 0 6
+0000 rrr1 11ss sSSS:000:--Z--:-----:13: BSET    Dr,s[!Areg,Dreg,Immd,PC8r,PC16]
+- 0 0 6 fea
+
+% Move cycles are special cased in gencpu.c
+0001 DDDd ddss sSSS:000:-NZ00:-----:12: MOVE.B  s,d[!Areg]
+0011 DDDd ddss sSSS:000:-----:-----:12: MOVEA.W s,d[Areg]
+0011 DDDd ddss sSSS:000:-NZ00:-----:12: MOVE.W  s,d[!Areg]
+0010 DDDd ddss sSSS:000:-----:-----:12: MOVEA.L s,d[Areg]
+0010 DDDd ddss sSSS:000:-NZ00:-----:12: MOVE.L  s,d[!Areg]
+
+0100 0000 zzdd dDDD:000:XxZxC:X-Z--:30: NEGX.z  d[Dreg]
+- 2 0 2
+0100 0000 zzdd dDDD:000:XxZxC:X-Z--:30: NEGX.z  d[!Areg,Dreg]
+- 0 1 3 fea
+0100 0000 11dd dDDD:001:?????:?????:10: MVSR2.W d[Dreg]
+- 2 0 4
+0100 0000 11dd dDDD:001:?????:?????:10: MVSR2.W d[!Areg,Dreg]
+- 2 0 4 cea
+0100 0010 zzdd dDDD:000:-0100:-----:20: CLR.z   d[Dreg]
+- 2 0 2
+0100 0010 zzdd dDDD:000:-0100:-----:20: CLR.z   d[!Areg,Dreg]
+- 0 1 3 cea
+0100 0010 11dd dDDD:100:?????:?????:10: MVSR2.B d[Dreg]
+- 2 0 4
+0100 0010 11dd dDDD:100:?????:?????:10: MVSR2.B d[!Areg,Dreg]
+- 2 0 4 cea
+0100 0100 zzdd dDDD:000:XNZVC:-----:30: NEG.z   d[Dreg]
+- 2 0 2
+0100 0100 zzdd dDDD:000:XNZVC:-----:30: NEG.z   d[!Areg,Dreg]
+- 0 1 3 fea
+0100 0100 11ss sSSS:000:XNZVC:-----:10: MV2SR.B s[Dreg]
+- 4 0 4
+0100 0100 11ss sSSS:000:XNZVC:-----:10: MV2SR.B s[!Areg,Dreg]
+- 0 0 4 fea
+0100 0110 zzdd dDDD:000:-NZ00:-----:30: NOT.z   d[Dreg]
+- 2 0 2
+0100 0110 zzdd dDDD:000:-NZ00:-----:30: NOT.z   d[!Areg,Dreg]
+- 0 1 3 fea
+0100 0110 11ss sSSS:002:?????:?????:10: MV2SR.W s[!Areg]
+- 0 0 8 fea
+0100 1000 0000 1rrr:200:-----:-----:31: LINK.L  Ar,#2
+- 2 0 6
+0100 1000 00dd dDDD:000:X?Z?C:X-Z--:30: NBCD.B  d[!Areg]
+- 0 0 6
+
+0100 1000 0100 1kkk:200:?????:?????:10: BKPT    #k
+
+0100 1000 01ss sSSS:000:-NZ00:-----:30: SWAP.W  s[Dreg]         
+- 4 0 4
+0100 1000 01ss sSSS:000:-----:-----:00: PEA.L   s[!Dreg,Areg,Aipi,Apdi,Immd]
+- 0 2 4 cea
+0100 1000 10dd dDDD:000:-NZ00:-----:30: EXT.W   d[Dreg]
+- 4 0 4
+
+0100 1000 10dd dDDD:000:-----:-----:02: MVMLE.W #1,d[!Dreg,Areg,Aipi]
+
+0100 1000 11dd dDDD:000:-NZ00:-----:30: EXT.L   d[Dreg]
+- 4 0 4
+
+0100 1000 11dd dDDD:000:-----:-----:02: MVMLE.L #1,d[!Dreg,Areg,Aipi]
+
+0100 1001 11dd dDDD:200:-NZ00:-----:30: EXT.B   d[Dreg]         
+- 4 0 4
+0100 1010 zzss sSSS:000:-NZ00:-----:10: TST.z   s[Dreg]
+- 0 0 2
+0100 1010 zzss sSSS:000:-NZ00:-----:10: TST.z   s[!Areg,Dreg,PC16,PC8r,Immd]
+- 0 0 2 fea
+0100 1010 zzss sSSS:200:-NZ00:-----:10: TST.z   s[Areg,PC16,PC8r,Immd]
+- 0 0 2 fea
+0100 1010 11dd dDDD:000:?????:?????:30: TAS.B   d[Dreg]
+- 0 0 2
+0100 1010 11dd dDDD:000:?????:?????:30: TAS.B   d[!Areg,Dreg]
+- 0 0 2 fea
+
+0100 1010 1111 1100:000:?????:?????:00: ILLEGAL
+
+0100 1100 00ss sSSS:200:-NZVC:-----:13: MULL.L  #1,s[!Areg]
+- 2 0 30 fiea
+0100 1100 01ss sSSS:200:?????:?????:13: DIVL.L  #1,s[!Areg]
+- 0 0 50 fiea
+
+0100 1100 10ss sSSS:000:-----:-----:01: MVMEL.W #1,s[!Dreg,Areg,Apdi,Immd]
+0100 1100 11ss sSSS:000:-----:-----:01: MVMEL.L #1,s[!Dreg,Areg,Apdi,Immd]
+0100 1110 0100 JJJJ:000:-----:XNZVC:10: TRAP    #J
+
+0100 1110 0101 0rrr:000:-----:-----:31: LINK.W  Ar,#1
+- 0 0 4
+0100 1110 0101 1rrr:000:-----:-----:30: UNLK.L  Ar
+- 0 0 5
+0100 1110 0110 0rrr:002:-----:-----:10: MVR2USP.L Ar
+- 4 0 4
+0100 1110 0110 1rrr:002:-----:-----:20: MVUSP2R.L Ar
+- 4 0 4
+0100 1110 0111 0000:002:-----:-----:00: RESET
+- 0 0 518
+0100 1110 0111 0001:000:-----:-----:00: NOP
+- 0 0 2
+0100 1110 0111 0010:002:XNZVC:-----:10: STOP    #1
+- 0 0 8
+0100 1110 0111 0011:002:XNZVC:-----:00: RTE
+- 1 9 18
+0100 1110 0111 0100:100:?????:?????:10: RTD     #1
+
+- 2 0 10
+0100 1110 0111 0101:000:-----:-----:00: RTS
+- 1 0 9
+
+0100 1110 0111 0110:000:-----:XNZVC:00: TRAPV
+
+0100 1110 0111 0111:000:XNZVC:-----:00: RTR
+- 1 0 12
+
+0100 1110 0111 1010:102:?????:?????:10: MOVEC2  #1
+- 6 0 6
+0100 1110 0111 1011:102:?????:?????:10: MOVE2C  #1
+- 6 0 6
+0100 1110 10ss sSSS:000://///://///:80: JSR.L   s[!Dreg,Areg,Aipi,Apdi,Immd]
+- 0 0 4 jea
+
+0100 rrr1 00ss sSSS:200:?????:?????:11: CHK.L   s[!Areg],Dr
+0100 rrr1 10ss sSSS:000:?????:?????:11: CHK.W   s[!Areg],Dr
+
+0100 1110 11ss sSSS:000://///://///:80: JMP.L   s[!Dreg,Areg,Aipi,Apdi,Immd]
+- 4 0 4 jea
+0100 rrr1 11ss sSSS:000:-----:-----:02: LEA.L   s[!Dreg,Areg,Aipi,Apdi,Immd],Ar
+- 2 0 2 cea
+
+0101 jjj0 01dd dDDD:000:-----:-----:13: ADDA.W  #j,d[Areg]
+- 2 0 2
+0101 jjj0 10dd dDDD:000:-----:-----:13: ADDA.L  #j,d[Areg]
+- 2 0 2
+0101 jjj0 zzdd dDDD:000:XNZVC:-----:13: ADD.z   #j,d[Dreg]
+- 2 0 2
+0101 jjj0 zzdd dDDD:000:XNZVC:-----:13: ADD.z   #j,d[!Areg,Dreg]
+- 0 1 3 fea
+0101 jjj1 01dd dDDD:000:-----:-----:13: SUBA.W  #j,d[Areg]
+- 2 0 2
+0101 jjj1 10dd dDDD:000:-----:-----:13: SUBA.L  #j,d[Areg]
+- 2 0 2
+0101 jjj1 zzdd dDDD:000:XNZVC:-----:13: SUB.z   #j,d[Dreg]
+- 2 0 2
+0101 jjj1 zzdd dDDD:000:XNZVC:-----:13: SUB.z   #j,d[!Areg,Dreg]
+- 0 1 3 fea
+0101 cccc 1100 1rrr:000:-----:-++++:31: DBcc.W  Dr,#1
+- -1 0 0
+0101 cccc 11dd dDDD:000:-----:-++++:20: Scc.B   d[Dreg]
+- 0 0 2
+0101 cccc 11dd dDDD:000:-----:-++++:20: Scc.B   d[!Areg,Dreg]
+- 0 0 2 cea
+
+0101 cccc 1111 1010:200:?????:?????:10: TRAPcc  #1
+0101 cccc 1111 1011:200:?????:?????:10: TRAPcc  #2
+0101 cccc 1111 1100:200:?????:?????:00: TRAPcc
+
+% Bxx.L is 68020 only, but setting the CPU level to 2 would give illegal
+% instruction exceptions when compiling a 68000 only emulation, which isn't
+% what we want either.
+0110 0001 0000 0000:000://///://///:40: BSR.W   #1
+- 2 0 6
+0110 0001 IIII IIII:000://///://///:40: BSR.B   #i
+- 2 0 6
+0110 0001 1111 1111:000://///://///:40: BSR.L   #2
+- 2 0 6
+0110 CCCC 0000 0000:000:-----:-++++:40: Bcc.W   #1
+- -1 0 0
+0110 CCCC IIII IIII:000:-----:-++++:40: Bcc.B   #i
+- -1 0 0
+0110 CCCC 1111 1111:000:-----:-++++:40: Bcc.L   #2
+- -1 0 0
+
+0111 rrr0 iiii iiii:000:-NZ00:-----:12: MOVE.L  #i,Dr
+
+1000 rrr0 zzss sSSS:000:-NZ00:-----:13: OR.z    s[Dreg],Dr
+- 2 0 2
+1000 rrr0 zzss sSSS:000:-NZ00:-----:13: OR.z    s[!Areg,Dreg],Dr
+- 0 0 2 fea
+
+1000 rrr0 11ss sSSS:000:?????:?????:13: DIVU.W  s[Dreg],Dr
+- 2 0 54
+1000 rrr0 11ss sSSS:000:?????:?????:13: DIVU.W  s[!Areg,Dreg],Dr
+- 0 0 54 fea
+
+1000 rrr1 00dd dDDD:000:XxZxC:X-Z--:13: SBCD.B  d[Dreg],Dr
+- 0 0 4
+1000 rrr1 00dd dDDD:000:XxZxC:X-Z--:13: SBCD.B  d[Areg-Apdi],Arp      
+- 2 1 13
+
+1000 rrr1 zzdd dDDD:000:-NZ00:-----:13: OR.z    Dr,d[!Areg,Dreg]
+- 0 1 3 fea
+
+1000 rrr1 01dd dDDD:200:?????:?????:12: PACK    d[Dreg],Dr
+- 6 0 6
+1000 rrr1 01dd dDDD:200:?????:?????:12: PACK    d[Areg-Apdi],Arp
+- 2 1 11
+1000 rrr1 10dd dDDD:200:?????:?????:12: UNPK    d[Dreg],Dr
+- 8 0 8
+1000 rrr1 10dd dDDD:200:?????:?????:12: UNPK    d[Areg-Apdi],Arp
+- 2 1 11
+
+1000 rrr1 11ss sSSS:000:?????:?????:13: DIVS.W  s[Dreg],Dr
+- 2 0 54
+1000 rrr1 11ss sSSS:000:?????:?????:13: DIVS.W  s[!Areg,Dreg],Dr
+- 0 0 54 fea
+
+1001 rrr0 zzss sSSS:000:XNZVC:-----:13: SUB.z   s[Areg,Dreg],Dr
+- 2 0 2
+1001 rrr0 zzss sSSS:000:XNZVC:-----:13: SUB.z   s[!Areg,Dreg],Dr
+- 0 0 2 fea
+1001 rrr0 11ss sSSS:000:-----:-----:13: SUBA.W  s[Areg,Dreg],Ar
+- 4 0 4
+1001 rrr0 11ss sSSS:000:-----:-----:13: SUBA.W  s[!Areg,Dreg],Ar
+- 0 0 4 fea
+
+1001 rrr1 zzdd dDDD:000:XNZVC:X-Z--:13: SUBX.z  d[Dreg],Dr
+- 2 0 2
+1001 rrr1 zzdd dDDD:000:XNZVC:X-Z--:13: SUBX.z  d[Areg-Apdi],Arp
+- 2 1 9
+
+1001 rrr1 zzdd dDDD:000:XNZVC:-----:13: SUB.z   Dr,d[!Areg,Dreg]
+- 0 1 3 fea
+1001 rrr1 11ss sSSS:000:-----:-----:13: SUBA.L  s[Areg,Dreg],Ar
+- 2 0 2
+1001 rrr1 11ss sSSS:000:-----:-----:13: SUBA.L  s[!Areg,Dreg],Ar
+- 0 0 2 fea
+
+1011 rrr0 zzss sSSS:000:-NZVC:-----:11: CMP.z   s[Areg,Dreg],Dr
+- 2 0 2
+1011 rrr0 zzss sSSS:000:-NZVC:-----:11: CMP.z   s[!Areg,Dreg],Dr
+- 0 0 2 fea
+1011 rrr0 11ss sSSS:000:-NZVC:-----:11: CMPA.W  s[Areg,Dreg],Ar
+- 4 0 4
+1011 rrr0 11ss sSSS:000:-NZVC:-----:11: CMPA.W  s[!Areg,Dreg],Ar
+- 0 0 4 fea
+1011 rrr1 11ss sSSS:000:-NZVC:-----:11: CMPA.L  s[Areg,Dreg],Ar
+- 4 0 4
+1011 rrr1 11ss sSSS:000:-NZVC:-----:11: CMPA.L  s[!Areg,Dreg],Ar
+- 0 0 4 fea
+1011 rrr1 zzdd dDDD:000:-NZVC:-----:11: CMPM.z  d[Areg-Aipi],ArP
+- 0 0 8
+1011 rrr1 zzdd dDDD:000:-NZ00:-----:13: EOR.z   Dr,d[Dreg]
+- 2 0 2
+1011 rrr1 zzdd dDDD:000:-NZ00:-----:13: EOR.z   Dr,d[!Areg,Dreg]
+- 0 1 3 fea
+
+1100 rrr0 zzss sSSS:000:-NZ00:-----:13: AND.z   s[Dreg],Dr
+- 2 0 2 fea
+1100 rrr0 zzss sSSS:000:-NZ00:-----:13: AND.z   s[!Areg,Dreg],Dr
+- 0 1 3 fea
+1100 rrr0 11ss sSSS:000:-NZ00:-----:13: MULU.W  s[!Areg],Dr
+- 2 0 25 fea
+
+1100 rrr1 00dd dDDD:000:XxZxC:X-Z--:13: ABCD.B  d[Dreg],Dr
+- 0 0 4
+1100 rrr1 00dd dDDD:000:XxZxC:X-Z--:13: ABCD.B  d[Areg-Apdi],Arp
+- 2 1 13
+
+1100 rrr1 zzdd dDDD:000:-NZ00:-----:13: AND.z   Dr,d[!Areg,Dreg]
+- 0 1 3 fea
+1100 rrr1 01dd dDDD:000:-----:-----:33: EXG.L   Dr,d[Dreg]      
+- 4 0 4
+1100 rrr1 01dd dDDD:000:-----:-----:33: EXG.L   Ar,d[Areg]            
+- 4 0 4
+1100 rrr1 10dd dDDD:000:-----:-----:33: EXG.L   Dr,d[Areg]      
+- 4 0 4
+1100 rrr1 11ss sSSS:000:-NZ00:-----:13: MULS.W  s[!Areg],Dr
+- 2 0 25 fea
+
+1101 rrr0 zzss sSSS:000:XNZVC:-----:13: ADD.z   s[Areg,Dreg],Dr
+- 2 0 2
+1101 rrr0 zzss sSSS:000:XNZVC:-----:13: ADD.z   s[!Areg,Dreg],Dr
+- 0 0 2 fea
+1101 rrr0 11ss sSSS:000:-----:-----:13: ADDA.W  s[Areg,Dreg],Ar
+- 0 0 4
+1101 rrr0 11ss sSSS:000:-----:-----:13: ADDA.W  s[!Areg,Dreg],Ar
+- 4 0 4 fea
+
+1101 rrr1 zzdd dDDD:000:XNZVC:X-Z--:13: ADDX.z  d[Dreg],Dr
+- 2 0 2
+1101 rrr1 zzdd dDDD:000:XNZVC:X-Z--:13: ADDX.z  d[Areg-Apdi],Arp
+- 2 1 9
+
+1101 rrr1 zzdd dDDD:000:XNZVC:-----:13: ADD.z   Dr,d[!Areg,Dreg]
+- 0 1 3 fea
+1101 rrr1 11ss sSSS:000:-----:-----:13: ADDA.L  s[Areg,Dreg],Ar
+- 2 0 2
+1101 rrr1 11ss sSSS:000:-----:-----:13: ADDA.L  s[!Areg,Dreg],Ar
+- 0 0 2 fea
+
+1110 jjjf zz00 0RRR:000:XNZVC:-----:13: ASf.z   #j,DR
+- 2 0 6
+1110 jjjf zz00 1RRR:000:XNZ0C:-----:13: LSf.z   #j,DR
+- 4 0 4
+1110 jjjf zz01 0RRR:000:XNZ0C:X----:13: ROXf.z  #j,DR
+- 10 0 12
+1110 jjjf zz01 1RRR:000:-NZ0C:-----:13: ROf.z   #j,DR
+- 4 0 6
+1110 rrrf zz10 0RRR:000:XNZVC:X----:13: ASf.z   Dr,DR
+- 4 0 6
+1110 rrrf zz10 1RRR:000:XNZ0C:X----:13: LSf.z   Dr,DR
+- 6 0 6
+1110 rrrf zz11 0RRR:000:XNZ0C:X----:13: ROXf.z  Dr,DR
+- 10 0 12
+1110 rrrf zz11 1RRR:000:-NZ0C:-----:13: ROf.z   Dr,DR
+- 6 0 8
+1110 000f 11dd dDDD:000:XNZVC:-----:13: ASfW.W  d[!Dreg,Areg]
+- 0 0 4 fea
+1110 001f 11dd dDDD:000:XNZ0C:-----:13: LSfW.W  d[!Dreg,Areg]
+- 0 0 4 fea
+1110 010f 11dd dDDD:000:XNZ0C:X----:13: ROXfW.W d[!Dreg,Areg]
+- 0 0 4 fea
+1110 011f 11dd dDDD:000:-NZ0C:-----:13: ROfW.W  d[!Dreg,Areg]
+- 0 0 6 fea
+
+1110 1000 11ss sSSS:200:?????:?????:11: BFTST   #1,s[!Areg,Apdi,Aipi,Immd]
+1110 1001 11ss sSSS:200:?????:?????:11: BFEXTU  #1,s[!Areg,Apdi,Aipi,Immd]
+1110 1010 11ss sSSS:200:?????:?????:13: BFCHG   #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
+1110 1011 11ss sSSS:200:?????:?????:11: BFEXTS  #1,s[!Areg,Apdi,Aipi,Immd]
+1110 1100 11ss sSSS:200:?????:?????:13: BFCLR   #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
+1110 1101 11ss sSSS:200:?????:?????:11: BFFFO   #1,s[!Areg,Apdi,Aipi,Immd]
+1110 1110 11ss sSSS:200:?????:?????:13: BFSET   #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
+1110 1111 11ss sSSS:200:?????:?????:13: BFINS   #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
+
+% floating point co processor
+1111 0010 00ss sSSS:200:?????:?????:11: FPP      #1,s
+1111 0010 01ss sSSS:200:?????:?????:11: FDBcc    #1,s[Areg-Dreg]
+1111 0010 01ss sSSS:200:?????:?????:11: FScc     #1,s[!Areg,Immd,PC8r,PC16]
+1111 0010 0111 1010:200:?????:?????:10: FTRAPcc  #1
+1111 0010 0111 1011:200:?????:?????:10: FTRAPcc  #2
+1111 0010 0111 1100:200:?????:?????:00: FTRAPcc
+1111 0010 10KK KKKK:200:?????:?????:11: FBcc     #K,#1
+1111 0010 11KK KKKK:200:?????:?????:11: FBcc     #K,#2
+1111 0011 00ss sSSS:202:?????:?????:20: FSAVE    s[!Dreg,Areg,Aipi,Immd,PC8r,PC16]
+1111 0011 01ss sSSS:202:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd]
+
+% 68030 MMU (allowed addressing modes not checked!)
+1111 0000 00ss sSSS:342:?????:?????:11: MMUOP030 s[Dreg,Areg,Apdi,Aipi,Aind,Ad16,Ad8r,absl,absw],#1
+
+% 68040/68060 instructions
+1111 0100 pp00 1rrr:402:-----:-----:02: CINVL    #p,Ar
+1111 0100 pp01 0rrr:402:-----:-----:02: CINVP    #p,Ar
+1111 0100 pp01 1rrr:402:-----:-----:00: CINVA    #p
+1111 0100 pp10 1rrr:402:-----:-----:02: CPUSHL   #p,Ar
+1111 0100 pp11 0rrr:402:-----:-----:02: CPUSHP   #p,Ar
+1111 0100 pp11 1rrr:402:-----:-----:00: CPUSHA   #p
+1111 0101 0000 0rrr:402:-----:-----:00: PFLUSHN  Ara
+1111 0101 0000 1rrr:402:-----:-----:00: PFLUSH   Ara
+1111 0101 0001 0rrr:402:-----:-----:00: PFLUSHAN Ara
+1111 0101 0001 1rrr:402:-----:-----:00: PFLUSHA  Ara
+% 68040 only
+1111 0101 0100 1rrr:452:-----:-----:00: PTESTW   Ara
+1111 0101 0110 1rrr:452:-----:-----:00: PTESTR   Ara
+
+% destination register number is encoded in the following word
+1111 0110 0010 0rrr:400:-----:-----:12: MOVE16   ArP,AxP
+1111 0110 00ss sSSS:400:-----:-----:12: MOVE16   s[Dreg-Aipi],L
+1111 0110 00dd dDDD:400:-----:-----:12: MOVE16   L,d[Areg-Aipi]
+1111 0110 00ss sSSS:400:-----:-----:12: MOVE16   s[Aind],L
+1111 0110 00dd dDDD:400:-----:-----:12: MOVE16   L,d[Aipi-Aind]
+
+% 68060
+1111 1000 0000 0000:502:?????:?????:10: LPSTOP   #1
+1111 0101 1000 1rrr:502:-----:-----:00: PLPAW    Ara
+1111 0101 1100 1rrr:502:-----:-----:00: PLPAR    Ara
+
diff --git a/src/cpu/winuae_readme.txt b/src/cpu/winuae_readme.txt
new file mode 100644
index 0000000..f962d37
--- /dev/null
+++ b/src/cpu/winuae_readme.txt
@@ -0,0 +1,16 @@
+		The CPU core in this directory is based on
+			WinUAE 3.1.0 (08/06/2015)
+
+
+To update to a newer WinUAE's version, a diff should be made between
+WinUAE 3.1.0 sources and the newer sources, then the resulting patch
+should be applied to the files in this directory.
+
+Most files are similar to WinUAE's ones, so patches should apply in
+most cases ; except custom.c and memory.c which contain too much
+Amiga specific code and were trimmed down and might need manual editing
+to apply patches.
+
+If you update to a newer WinUAE's version, also update the version at the
+top of this file to keep track of the reference version used for the CPU core.
+
diff --git a/src/createBlankImage.c b/src/createBlankImage.c
new file mode 100644
index 0000000..d8648af
--- /dev/null
+++ b/src/createBlankImage.c
@@ -0,0 +1,187 @@
+/*
+  Hatari - createBlankImage.c
+ 
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+ 
+  Create blank .ST/.MSA disk images.
+*/
+const char CreateBlankImage_fileid[] = "Hatari createBlankImage.c : " __DATE__ " " __TIME__;
+
+#include "main.h"
+#include "configuration.h"
+#include "dim.h"
+#include "file.h"
+#include "floppy.h"
+#include "log.h"
+#include "msa.h"
+#include "st.h"
+#include "createBlankImage.h"
+
+/*-----------------------------------------------------------------------*/
+/*
+           40 track SS   40 track DS   80 track SS   80 track DS
+ 0- 1   Branch instruction to boot program if executable
+ 2- 7   'Loader'
+ 8-10   24-bit serial number
+11-12   BPS    512           512           512           512
+13      SPC     1             2             2             2
+14-15   RES     1             1             1             1
+16      FAT     2             2             2             2
+17-18   DIR     64           112           112           112
+19-20   SEC    360           720           720          1440
+21      MEDIA  $FC           $FD           $F8           $F9  (isn't used by ST-BIOS)
+22-23   SPF     2             2             5             5
+24-25   SPT     9             9             9             9
+26-27   SIDE    1             2             1             2
+28-29   HID     0             0             0             0
+510-511 CHECKSUM
+*/
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Calculate the size of a disk in dialog.
+ */
+static int CreateBlankImage_GetDiskImageCapacity(int nTracks, int nSectors, int nSides)
+{
+	/* Find size of disk image */
+	return nTracks*nSectors*nSides*NUMBYTESPERSECTOR;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Write a short integer to addr using little endian byte order
+ * (needed for 16 bit values in the bootsector of the disk image).
+ */
+static inline void WriteShortLE(void *addr, Uint16 val)
+{
+	Uint8 *p = (Uint8 *)addr;
+
+	p[0] = (Uint8)val;
+	p[1] = (Uint8)(val >> 8);
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Create .ST/.MSA disk image according to 'Tracks,Sector,Sides' and save
+ * it under given filename.
+ * Return true if saving succeeded, false otherwise.
+ */
+bool CreateBlankImage_CreateFile(const char *pszFileName, int nTracks, int nSectors, int nSides)
+{
+	Uint8 *pDiskFile;
+	unsigned long nDiskSize;
+	unsigned short int SPC, nDir, MediaByte, SPF;
+	bool bRet = false;
+	int drive;
+
+	/* HD/ED disks are all double sided */
+	if (nSectors >= 18)
+		nSides = 2;
+
+	/* Calculate size of disk image */
+	nDiskSize = CreateBlankImage_GetDiskImageCapacity(nTracks, nSectors, nSides);
+
+	/* Allocate space for our 'file', and blank */
+	pDiskFile = malloc(nDiskSize);
+	if (pDiskFile == NULL)
+	{
+		perror("Error while creating blank disk image");
+		return false;
+	}
+	memset(pDiskFile, 0, nDiskSize);                      /* Clear buffer */
+
+	/* Fill in boot-sector */
+	pDiskFile[0] = 0xE9;                                  /* Needed for MS-DOS compatibility */
+	memset(pDiskFile+2, 0x4e, 6);                         /* 2-7 'Loader' */
+
+	WriteShortLE(pDiskFile+8, rand());                    /* 8-10 24-bit serial number */
+	pDiskFile[10] = rand();
+
+	WriteShortLE(pDiskFile+11, NUMBYTESPERSECTOR);        /* 11-12 BPS */
+
+	if ((nTracks == 40) && (nSides == 1))
+		SPC = 1;
+	else
+		SPC = 2;
+	pDiskFile[13] = SPC;                                  /* 13 SPC */
+
+	WriteShortLE(pDiskFile+14, 1);                        /* 14-15 RES */
+	pDiskFile[16] = 2;                                    /* 16 FAT */
+
+	if (SPC==1)
+		nDir = 64;
+	else if (nSectors < 18)
+		nDir = 112;
+	else
+		nDir = 224;
+	WriteShortLE(pDiskFile+17, nDir);                     /* 17-18 DIR */
+
+	WriteShortLE(pDiskFile+19, nTracks*nSectors*nSides);  /* 19-20 SEC */
+
+	if (nSectors >= 18)
+		MediaByte = 0xF0;
+	else
+	{
+		if (nTracks <= 42)
+			MediaByte = 0xFC;
+		else
+			MediaByte = 0xF8;
+		if (nSides == 2)
+			MediaByte |= 0x01;
+	}
+	pDiskFile[21] = MediaByte;                            /* 21 MEDIA */
+
+	if (nSectors >= 18)
+		SPF = 9;
+	else if (nTracks >= 80)
+		SPF = 5;
+	else
+		SPF = 2;
+	WriteShortLE(pDiskFile+22, SPF);                      /* 22-23 SPF */
+
+	WriteShortLE(pDiskFile+24, nSectors);                 /* 24-25 SPT */
+	WriteShortLE(pDiskFile+26, nSides);                   /* 26-27 SIDE */
+	WriteShortLE(pDiskFile+28, 0);                        /* 28-29 HID */
+
+	/* Set correct media bytes in the 1st FAT: */
+	pDiskFile[512] = MediaByte;
+	pDiskFile[513] = pDiskFile[514] = 0xFF;
+	/* Set correct media bytes in the 2nd FAT: */
+	pDiskFile[512 + SPF * 512] = MediaByte;
+	pDiskFile[513 + SPF * 512] = pDiskFile[514 + SPF * 512] = 0xFF;
+
+	/* Ask if OK to overwrite, if exists? */
+	if (File_QueryOverwrite(pszFileName))
+	{
+		drive = 0;				/* drive is not used for ST/MSA/DIM, set it to 0 */
+		/* Save image to file */
+		if (MSA_FileNameIsMSA(pszFileName, true))
+			bRet = MSA_WriteDisk(drive, pszFileName, pDiskFile, nDiskSize);
+		else if (ST_FileNameIsST(pszFileName, true))
+			bRet = ST_WriteDisk(drive, pszFileName, pDiskFile, nDiskSize);
+		else if (DIM_FileNameIsDIM(pszFileName, true))
+			bRet = DIM_WriteDisk(drive, pszFileName, pDiskFile, nDiskSize);
+		else
+			Log_AlertDlg(LOG_ERROR, "Unknown floppy image filename extension!");
+
+		/* Did create successfully? */
+		if (bRet)
+		{
+			/* Say OK */
+			Log_AlertDlg(LOG_INFO, "Disk image '%s' created.", pszFileName);
+		}
+		else
+		{
+			/* Warn user we were unable to create image */
+			Log_AlertDlg(LOG_ERROR, "Unable to create disk image '%s'!", pszFileName);
+		}
+	}
+
+	/* Free image */
+	free(pDiskFile);
+	return bRet;
+}
diff --git a/src/cycInt.c b/src/cycInt.c
new file mode 100644
index 0000000..c4f6365
--- /dev/null
+++ b/src/cycInt.c
@@ -0,0 +1,497 @@
+/*
+  Hatari - cycInt.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  This code handles our table with callbacks for cycle accurate program
+  interruption. We add any pending callback handler into a table so that we do
+  not need to test for every possible interrupt event. We then scan
+  the list if used entries in the table and copy the one with the least cycle
+  count into the global 'PendingInterruptCount' variable. This is then
+  decremented by the execution loop - rather than decrement each and every
+  entry (as the others cannot occur before this one).
+  We have two methods of adding interrupts; Absolute and Relative.
+  Absolute will set values from the time of the previous interrupt (e.g., add
+  HBL every 512 cycles), and Relative will add from the current cycle time.
+  Note that interrupt may occur 'late'. I.e., if an interrupt is due in 4
+  cycles time but the current instruction takes 20 cycles we will be 16 cycles
+  late - this is handled in the adjust functions.
+
+  In order to handle both CPU and MFP interrupt events, we don't convert MFP
+  cycles to CPU cycles, because it requires some floating points approximations
+  and accumulates some errors that could lead to bad results.
+  Instead, CPU and MFP cycles are converted to 'internal' cycles with the
+  following rule :
+	- 1 CPU cycle gives  9600 internal cycles
+	- 1 MFP cycle gives 31333 internal cycle
+
+  All interrupt events are then handled in the 'internal' units and are
+  converted back to cpu or mfp units when needed. This allows very good
+  synchronisation between CPU and MFP, without the rounding errors of floating
+  points math.
+
+  Thanks to Arnaud Carre (Leonard / Oxygene) for sharing this method used in
+  Saint (and also used in sc68).
+
+  Conversions are based on these values :
+	real MFP frequency is 2457600 Hz
+	real CPU frequency is 8021247 Hz (PAL european STF), which we round to 8021248.
+
+  Then :
+	8021248 = ( 2^8 * 31333 )
+	2457600 = ( 2^15 * 3 * 5^2 )
+
+  So, the ratio 8021248 / 2457600 can be expressed as 31333 / 9600
+*/
+
+const char CycInt_fileid[] = "Hatari cycInt.c : " __DATE__ " " __TIME__;
+
+#include 
+#include 
+#include 
+
+#include "main.h"
+#include "blitter.h"
+#include "dmaSnd.h"
+#include "crossbar.h"
+#include "fdc.h"
+#include "ikbd.h"
+#include "cycInt.h"
+#include "m68000.h"
+#include "mfp.h"
+#include "midi.h"
+#include "memorySnapShot.h"
+#include "sound.h"
+#include "screen.h"
+#include "video.h"
+#include "acia.h"
+
+
+void (*PendingInterruptFunction)(void);
+int PendingInterruptCount;
+
+static int nCyclesOver;
+
+/* List of possible interrupt handlers to be store in 'PendingInterruptTable',
+ * used for 'MemorySnapShot' */
+static void (* const pIntHandlerFunctions[MAX_INTERRUPTS])(void) =
+{
+	NULL,
+	Video_InterruptHandler_VBL,
+	Video_InterruptHandler_HBL,
+	Video_InterruptHandler_EndLine,
+	MFP_InterruptHandler_TimerA,
+	MFP_InterruptHandler_TimerB,
+	MFP_InterruptHandler_TimerC,
+	MFP_InterruptHandler_TimerD,
+	ACIA_InterruptHandler_IKBD,
+	IKBD_InterruptHandler_ResetTimer,
+	IKBD_InterruptHandler_AutoSend,
+	DmaSnd_InterruptHandler_Microwire, /* Used for both STE and Falcon Microwire emulation */
+	Crossbar_InterruptHandler_25Mhz,
+	Crossbar_InterruptHandler_32Mhz,
+	FDC_InterruptHandler_Update,
+	Blitter_InterruptHandler,
+	Midi_InterruptHandler_Update,
+
+};
+
+/* Event timer structure - keeps next timer to occur in structure so don't need
+ * to check all entries */
+typedef struct
+{
+	bool bUsed;                   /* Is interrupt active? */
+	Sint64 Cycles;
+	void (*pFunction)(void);
+} INTERRUPTHANDLER;
+
+static INTERRUPTHANDLER InterruptHandlers[MAX_INTERRUPTS];
+static int ActiveInterrupt=0;
+
+static void CycInt_SetNewInterrupt(void);
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Reset interrupts, handlers
+ */
+void CycInt_Reset(void)
+{
+	int i;
+
+	/* Reset counts */
+	PendingInterruptCount = 0;
+	ActiveInterrupt = 0;
+	nCyclesOver = 0;
+
+	/* Reset interrupt table */
+	for (i=0; i= 0);
+
+	/* Update list cycle counts with current PendingInterruptCount before adding a new int, */
+	/* because CycInt_SetNewInterrupt can change the active int / PendingInterruptCount */
+	if ( ActiveInterrupt > 0 )
+		CycInt_UpdateInterrupt();
+
+	InterruptHandlers[Handler].bUsed = true;
+	InterruptHandlers[Handler].Cycles = INT_CONVERT_TO_INTERNAL((Sint64)CycleTime , CycleType) + nCyclesOver;
+
+	/* Set new active int and compute a new value for PendingInterruptCount*/
+	CycInt_SetNewInterrupt();
+
+	LOG_TRACE(TRACE_INT, "int add abs video_cyc=%d handler=%d handler_cyc=%"PRId64" pending_count=%d\n",
+	          Cycles_GetCounter(CYCLES_COUNTER_VIDEO), Handler,
+	          InterruptHandlers[Handler].Cycles, PendingInterruptCount );
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Add interrupt to occur from now.
+ */
+void CycInt_AddRelativeInterrupt(int CycleTime, int CycleType, interrupt_id Handler)
+{
+	CycInt_AddRelativeInterruptWithOffset(CycleTime, CycleType, Handler, 0);
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Add interrupt to occur from now without offset
+ */
+#if 0
+void CycInt_AddRelativeInterruptNoOffset(int CycleTime, int CycleType, interrupt_id Handler)
+{
+	/* Update list cycle counts before adding a new one, */
+	/* since CycInt_SetNewInterrupt can change the active int / PendingInterruptCount */
+	if ( ( ActiveInterrupt > 0 ) && ( PendingInterruptCount > 0 ) )
+		CycInt_UpdateInterrupt();
+
+//  nCyclesOver = 0;
+	InterruptHandlers[Handler].bUsed = true;
+	InterruptHandlers[Handler].Cycles = INT_CONVERT_TO_INTERNAL((Sint64)CycleTime , CycleType) + PendingInterruptCount;
+
+	/* Set new */
+	CycInt_SetNewInterrupt();
+
+	LOG_TRACE(TRACE_INT, "int add rel no_off video_cyc=%d handler=%d handler_cyc=%"PRId64" pending_count=%d\n",
+	               Cycles_GetCounter(CYCLES_COUNTER_VIDEO), Handler, InterruptHandlers[Handler].Cycles, PendingInterruptCount );
+}
+#endif
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Add interrupt to occur after CycleTime/CycleType + CycleOffset.
+ * CycleOffset can be used to add another delay to the resulting
+ * number of internal cycles (should be 0 most of the time, except in
+ * the MFP emulation to start timers precisely based on the number of
+ * cycles of the current instruction).
+ * This allows to restart an MFP timer just after it expired.
+ */
+void CycInt_AddRelativeInterruptWithOffset(int CycleTime, int CycleType, interrupt_id Handler, int CycleOffset)
+{
+	assert(CycleTime >= 0);
+
+	/* Update list cycle counts with current PendingInterruptCount before adding a new int, */
+	/* because CycInt_SetNewInterrupt can change the active int / PendingInterruptCount */
+	if ( ActiveInterrupt > 0 )
+		CycInt_UpdateInterrupt();
+
+	InterruptHandlers[Handler].bUsed = true;
+	InterruptHandlers[Handler].Cycles = INT_CONVERT_TO_INTERNAL((Sint64)CycleTime , CycleType) + CycleOffset;
+
+	/* Set new active int and compute a new value for PendingInterruptCount*/
+	CycInt_SetNewInterrupt();
+
+	LOG_TRACE(TRACE_INT, "int add rel offset video_cyc=%d handler=%d handler_cyc=%"PRId64" offset_cyc=%d pending_count=%d\n",
+	          Cycles_GetCounter(CYCLES_COUNTER_VIDEO), Handler,
+	          InterruptHandlers[Handler].Cycles, CycleOffset, PendingInterruptCount);
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Modify interrupt's Cycles to make it happen earlier or later.
+ * This will not restart the interrupt, but add CycleTime cycles to the
+ * current value of the counter.
+ * CycleTime can be <0 or >0
+ */
+void CycInt_ModifyInterrupt(int CycleTime, int CycleType, interrupt_id Handler)
+{
+	/* Update list cycle counts with current PendingInterruptCount before adding a new int, */
+	/* because CycInt_SetNewInterrupt can change the active int / PendingInterruptCount */
+	if ( ActiveInterrupt > 0 )
+		CycInt_UpdateInterrupt();
+
+	InterruptHandlers[Handler].Cycles += INT_CONVERT_TO_INTERNAL((Sint64)CycleTime , CycleType);
+
+	/* Set new active int and compute a new value for PendingInterruptCount*/
+	CycInt_SetNewInterrupt();
+
+	LOG_TRACE(TRACE_INT, "int modify video_cyc=%d handler=%d handler_cyc=%"PRId64" pending_count=%d\n",
+	          Cycles_GetCounter(CYCLES_COUNTER_VIDEO), Handler,
+	          InterruptHandlers[Handler].Cycles, PendingInterruptCount );
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Remove a pending interrupt from our table
+ */
+void CycInt_RemovePendingInterrupt(interrupt_id Handler)
+{
+	/* Update list cycle counts, including the handler we want to remove */
+	/* to be able to resume it later (for MFP timers) */
+	CycInt_UpdateInterrupt();
+
+	/* Stop interrupt after CycInt_UpdateInterrupt, for CycInt_ResumeStoppedInterrupt */
+	InterruptHandlers[Handler].bUsed = false;
+
+	/* Set new */
+	CycInt_SetNewInterrupt();
+
+	LOG_TRACE(TRACE_INT, "int remove pending video_cyc=%d handler=%d handler_cyc=%"PRId64" pending_count=%d\n",
+	          Cycles_GetCounter(CYCLES_COUNTER_VIDEO), Handler,
+	          InterruptHandlers[Handler].Cycles, PendingInterruptCount);
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Resume a stopped interrupt from its current cycle count (for MFP timers)
+ */
+void CycInt_ResumeStoppedInterrupt(interrupt_id Handler)
+{
+	/* Restart interrupt */
+	InterruptHandlers[Handler].bUsed = true;
+
+	/* Update list cycle counts */
+	CycInt_UpdateInterrupt();
+	/* Set new */
+	CycInt_SetNewInterrupt();
+
+	LOG_TRACE(TRACE_INT, "int resume stopped video_cyc=%d handler=%d handler_cyc=%"PRId64" pending_count=%d\n",
+	          Cycles_GetCounter(CYCLES_COUNTER_VIDEO), Handler,
+	          InterruptHandlers[Handler].Cycles, PendingInterruptCount);
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Return true if interrupt is active in list
+ */
+bool CycInt_InterruptActive(interrupt_id Handler)
+{
+	/* Is timer active? */
+	if (InterruptHandlers[Handler].bUsed)
+		return true;
+
+	return false;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Return cycles passed for an interrupt handler
+ */
+int CycInt_FindCyclesPassed(interrupt_id Handler, int CycleType)
+{
+	Sint64 CyclesPassed, CyclesFromLastInterrupt;
+
+	CyclesFromLastInterrupt = InterruptHandlers[ActiveInterrupt].Cycles - PendingInterruptCount;
+	CyclesPassed = InterruptHandlers[Handler].Cycles - CyclesFromLastInterrupt;
+
+	LOG_TRACE(TRACE_INT, "int find passed cyc video_cyc=%d handler=%d last_cyc=%"PRId64" passed_cyc=%"PRId64"\n",
+	          Cycles_GetCounter(CYCLES_COUNTER_VIDEO), Handler,
+	          CyclesFromLastInterrupt, CyclesPassed);
+
+	return INT_CONVERT_FROM_INTERNAL ( CyclesPassed , CycleType ) ;
+}
diff --git a/src/cycles.c b/src/cycles.c
new file mode 100644
index 0000000..9d5a0cc
--- /dev/null
+++ b/src/cycles.c
@@ -0,0 +1,258 @@
+/*
+  Hatari - cycles.c
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  Here we take care of cycle counters. For performance reasons we don't increase
+  all counters after each 68k instruction, but only one main counter.
+  When we need to read one of the normal counters (currently only for video
+  and sound cycles), we simply update these counters with the main counter
+  before returning the current counter value.
+*/
+
+
+/* 2007/03/xx	[NP]	Use 'CurrentInstrCycles' to get a good approximation for	*/
+/*			Cycles_GetCounterOnReadAccess and Cycles_GetCounterOnWriteAccess*/
+/*			(this should work correctly with 'move' instruction).		*/
+/* 2008/04/14	[NP]	Take nWaitStateCycles into account when computing the value of	*/
+/*			Cycles_GetCounterOnReadAccess and Cycles_GetCounterOnWriteAccess*/
+/* 2008/12/21	[NP]	Use BusMode to adjust Cycles_GetCounterOnReadAccess and		*/
+/*			Cycles_GetCounterOnWriteAccess depending on who is owning the	*/
+/*			bus (cpu, blitter).						*/
+/* 2011/03/26	[NP]	In Cycles_GetCounterOnReadAccess, add a special case for opcode	*/
+/*			$11f8 'move.b xxx.w,xxx.w' (fix MOVE.B $ffff8209.w,$26.w in	*/
+/*			'Bird Mad Girl Show' demo's loader/protection)			*/
+/* 2012/08/19	[NP]	Add a global counter CyclesGlobalClockCounter to count cycles	*/
+/*			since the last reset.						*/
+
+
+const char Cycles_fileid[] = "Hatari cycles.c : " __DATE__ " " __TIME__;
+
+#include "main.h"
+#include "m68000.h"
+#include "memorySnapShot.h"
+#include "cycles.h"
+
+
+int	nCyclesMainCounter;			/* Main cycles counter since previous Cycles_UpdateCounters() */
+
+static int nCyclesCounter[CYCLES_COUNTER_MAX];	/* Array with all counters */
+
+Uint64	CyclesGlobalClockCounter = 0;		/* Global clock counter since starting Hatari (it's never reset afterwards) */
+
+int	CurrentInstrCycles;
+int	MovepByteNbr = 0;			/* Number of the byte currently transferred in a movep (1..2 or 1..4) */
+						/* 0 means current instruction is not a movep */
+
+
+static void	Cycles_UpdateCounters(void);
+static int	Cycles_GetInternalCycleOnReadAccess(void);
+static int	Cycles_GetInternalCycleOnWriteAccess(void);
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Save/Restore snapshot of local variables ('MemorySnapShot_Store' handles type)
+ */
+void Cycles_MemorySnapShot_Capture(bool bSave)
+{
+	/* Save/Restore details */
+	MemorySnapShot_Store(&nCyclesMainCounter, sizeof(nCyclesMainCounter));
+	MemorySnapShot_Store(nCyclesCounter, sizeof(nCyclesCounter));
+	MemorySnapShot_Store(&CyclesGlobalClockCounter, sizeof(CyclesGlobalClockCounter));
+	MemorySnapShot_Store(&CurrentInstrCycles, sizeof(CurrentInstrCycles));
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Update all cycles counters with the current value of nCyclesMainCounter.
+ */
+static void Cycles_UpdateCounters(void)
+{
+	int i;
+
+	for (i = 0; i < CYCLES_COUNTER_MAX; i++)
+	{
+		nCyclesCounter[i] += nCyclesMainCounter;
+	}
+
+	nCyclesMainCounter = 0;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Set a counter to a new value.
+ */
+void Cycles_SetCounter(int nId, int nValue)
+{
+	/* Update counters first (nCyclesMainCounter must be 0 afterwards) */
+	Cycles_UpdateCounters();
+
+	/* Now set the new value: */
+	nCyclesCounter[nId] = nValue;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read a counter.
+ */
+int Cycles_GetCounter(int nId)
+{
+	/* Update counters first so we read an up-to-date value */
+	Cycles_UpdateCounters();
+
+	return nCyclesCounter[nId];
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Compute the cycles where a read actually happens inside a specific
+ * instruction type. We use some common cases, this should be handled more
+ * accurately in the cpu emulation for each opcode.
+ */
+static int Cycles_GetInternalCycleOnReadAccess(void)
+{
+	int AddCycles;
+	int Opcode;
+
+	if ( BusMode == BUS_MODE_BLITTER )
+	{
+		AddCycles = 4 + nWaitStateCycles;
+	}
+	else							/* BUS_MODE_CPU */
+	{
+		/* TODO: Find proper cycles count depending on the opcode/family of the current instruction */
+		/* (e.g. movem is not correctly handled) */
+		Opcode = M68000_CurrentOpcode;
+		//fprintf ( stderr , "opcode=%x\n" , Opcode );
+
+		/* Assume we use 'move src,dst' : access cycle depends on dst mode */
+		if ( Opcode == 0x11f8 )				/* move.b xxx.w,xxx.w (eg MOVE.B $ffff8209.w,$26.w in Bird Mad Girl Show) */
+			AddCycles = CurrentInstrCycles + nWaitStateCycles - 8;		/* read is effective before the 8 write cycles for dst */
+		else if ( OpcodeFamily == i_MVPRM )					/* eg movep.l d0,$ffc3(a1) in E605 (STE) */
+			AddCycles = 12 + MovepByteNbr * 4;				/* [NP] FIXME, it works with E605 but gives 20-32 cycles instead of 16-28 */
+											/* something must be wrong in video.c */
+			/* FIXME : this should be : AddCycles = 4 + MovepByteNbr * 4, but this breaks e605 in video.c */
+		else
+			AddCycles = CurrentInstrCycles + nWaitStateCycles;		/* assume dest is reg : read is effective at the end of the instr */
+	}
+
+	return AddCycles;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Compute the cycles where a write actually happens inside a specific
+ * instruction type. We use some common cases, this should be handled more
+ * accurately in the cpu emulation for each opcode.
+ */
+static int Cycles_GetInternalCycleOnWriteAccess(void)
+{
+	int AddCycles;
+
+	if ( BusMode == BUS_MODE_BLITTER )
+	{
+		AddCycles = 4 + nWaitStateCycles;
+	}
+	else							/* BUS_MODE_CPU */
+	{
+		/* TODO: Find proper cycles count depending on the type of the current instruction */
+		/* (e.g. movem is not correctly handled) */
+		AddCycles = CurrentInstrCycles + nWaitStateCycles;
+
+		if ( ( OpcodeFamily == i_CLR ) || ( OpcodeFamily == i_NEG ) || ( OpcodeFamily == i_NEGX ) || ( OpcodeFamily == i_NOT ) )
+			;						/* Do nothing, the write is done during the last 4 cycles */
+									/* (e.g i_CLR for bottom border removal in No Scroll / Delirious Demo 4) */
+
+		else if ( ( OpcodeFamily == i_ADD ) || ( OpcodeFamily == i_SUB ) )
+			;						/* Do nothing, the write is done during the last 4 cycles */
+									/* (eg 'add d1,(a0)' in rasters.prg by TOS Crew */
+
+		else if ( ( OpcodeFamily == i_AND ) || ( OpcodeFamily == i_OR ) || ( OpcodeFamily == i_EOR ) )
+			;						/* Do nothing, the write is done during the last 4 cycles */
+
+		else if ( ( OpcodeFamily == i_BCHG ) || ( OpcodeFamily == i_BCLR ) || ( OpcodeFamily == i_BSET ) )
+			;						/* Do nothing, the write is done during the last 4 cycles */
+
+		else
+		{
+			/* assume the behaviour of a 'move' (since this is the most */
+			/* common instr used when requiring cycle precise writes) */
+			if ( AddCycles >= 8 )
+				AddCycles -= 4;			/* last 4 cycles are for prefetch */
+		}
+	}
+
+	return AddCycles;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read a counter on CPU memory read access by taking care of the instruction
+ * type (add the needed amount of additional cycles).
+ */
+int Cycles_GetCounterOnReadAccess(int nId)
+{
+	int AddCycles;
+
+	AddCycles = Cycles_GetInternalCycleOnReadAccess();
+
+	return Cycles_GetCounter(nId) + AddCycles;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read a counter on CPU memory write access by taking care of the instruction
+ * type (add the needed amount of additional cycles).
+ */
+int Cycles_GetCounterOnWriteAccess(int nId)
+{
+	int AddCycles;
+
+	AddCycles = Cycles_GetInternalCycleOnWriteAccess();
+
+	return Cycles_GetCounter(nId) + AddCycles;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read the main clock counter on CPU memory read access by taking care of the instruction
+ * type (add the needed amount of additional cycles).
+ */
+Uint64 Cycles_GetClockCounterOnReadAccess(void)
+{
+	int AddCycles;
+
+	AddCycles = Cycles_GetInternalCycleOnReadAccess();
+
+	return CyclesGlobalClockCounter + AddCycles;
+}
+
+
+/*-----------------------------------------------------------------------*/
+/**
+ * Read the main clock counter on CPU memory write access by taking care of the instruction
+ * type (add the needed amount of additional cycles).
+ */
+Uint64 Cycles_GetClockCounterOnWriteAccess(void)
+{
+	int AddCycles;
+
+	AddCycles = Cycles_GetInternalCycleOnWriteAccess();
+
+	return CyclesGlobalClockCounter + AddCycles;
+}
+
+
+
diff --git a/src/debug/68kDisass.c b/src/debug/68kDisass.c
new file mode 100644
index 0000000..bc50800
--- /dev/null
+++ b/src/debug/68kDisass.c
@@ -0,0 +1,2723 @@
+/***
+ *	68k disassembler, written 2010 by Markus Fritze, www.sarnau.com
+ *	
+ *	This file is distributed under the GNU General Public License, version 2
+ *	or at your option any later version. Read the file gpl.txt for details.
+ ***/
+
+#include 
+#include 
+#include 
+#include 
+
+#include "config.h"
+#include "sysdeps.h"
+#include "main.h"
+#include "configuration.h"
+#include "newcpu.h"
+#ifdef WINUAE_FOR_HATARI
+#include "debug.h"
+#endif
+#include "paths.h"
+#include "profile.h"
+#include "tos.h"
+#include "68kDisass.h"
+
+#define ADDRESS_ON_PC		1
+#define USE_SYMBOLS			1
+
+typedef enum {
+	doptNoBrackets = 1,		// hide brackets around absolute addressing
+	doptOpcodesSmall = 2,	// opcodes are small letters
+	doptRegisterSmall = 4,	// register names are small letters
+	doptStackSP = 8		// stack pointer is named "SP" instead of "A7" (except for MOVEM)
+} Diss68kOptions;
+
+static Diss68kOptions	options = doptOpcodesSmall | doptRegisterSmall | doptStackSP | doptNoBrackets;
+
+/* all options */
+static const Diss68kOptions optionsMask = doptOpcodesSmall | doptRegisterSmall | doptStackSP | doptNoBrackets;
+
+// values <0 will hide the group
+static int			optionPosAddress = 0;	// current address
+static int			optionPosHexdump = 12;	// 16-bit words at this address
+static int			optionPosLabel = 35;	// label, if defined
+static int			optionPosOpcode = 47;	// opcode
+static int			optionPosOperand = 57;	// operands for the opcode
+static int			optionPosComment = 82;	// comment, if defined
+
+/***
+ *	Motorola 16-/32-Bit Microprocessor and coprocessor types
+ ***/
+#define MC68000			0x000001	// 16-/32-Bit Microprocessor
+	#define MC68EC000	0x000002	// 16-/32-Bit Embedded Controller
+	#define MC68HC000	0x000004	// Low Power 16-/32-Bit Microprocessor
+#define MC68008			0x000008	// 16-Bit Microprocessor with 8-Bit Data Bus
+#define MC68010			0x000010	// 16-/32-Bit Virtual Memory Microprocessor
+#define MC68020			0x000020	// 32-Bit Virtual Memory Microprocessor
+	#define MC68EC020	0x000040	// 32-Bit Embedded Controller (no PMMU)
+#define MC68030			0x000080	// Second-Generation 32-Bit Enhanced Microprocessor
+	#define MC68EC030	0x000100	// 32-Bit Embedded Controller (no PMMU)
+#define MC68040			0x000200	// Third-Generation 32-Bit Microprocessor
+	#define MC68LC040	0x000400	// Third-Generation 32-Bit Microprocessor (no FPU)
+	#define MC68EC040	0x000800	// 32-Bit Embedded Controller (no FPU, no PMMU)
+#define MC68330			0x001000	// CPU32 Integrated CPU32 Processor
+#define MC68340			0x002000	// CPU32 Integrated Processor with DMA
+#define MC68060			0x004000	// Fourth-Generation 32-Bit Microprocessor
+	#define MC68LC060	0x008000	// Fourth-Generation 32-Bit Microprocessor (no FPU)
+	#define MC68EC060	0x010000	// Fourth-Generation 32-Bit Microprocessor (no FPU, no PMMU)
+#define MC_CPU32		(MC68330|MC68340)
+
+#define MC_020			(MC68020|MC68EC020|MC68030|MC68EC030|MC68040|MC68LC040|MC68EC040|MC_CPU32|MC68060|MC68LC060|MC68EC060)
+#define MC_ALL			(MC68000|MC68EC000|MC68HC000|MC68008|MC68010|MC_020)
+
+#define MC68851			0x020000	// Paged Memory Management Unit
+
+#define MC68881			0x040000	// Floating-PointCoprocessor
+#define MC68882			0x080000	// Enhanced Floating-Point Coprocessor
+
+#define MC_PMMU			(MC68881|MC68882)
+#define MC_FPU			(MC68881|MC68882)
+
+static int				optionCPUTypeMask = ( MC_ALL & ~MC68040 & ~MC_CPU32 & ~MC68060 ) | MC_PMMU | MC_FPU;
+
+
+typedef enum {
+	dtNone,
+	dtByte,				// a specific number of bytes, usually 1
+	dtWord,				// one 16-bit value
+	dtLong,				// one 32-bit value
+	dtOpcode,			// an opcode of variable length
+	dtASCString,		// a 0-byte terminated ASCII string
+	dtPointer,			// a generic 32-bit pointer
+	dtFunctionPointer,	// a 32-bit pointer to a function
+	dtStringArray		// a specific number of ASCII bytes
+} Disass68kDataType;
+
+typedef struct {
+	char	*name;
+	char	*comment;
+	Disass68kDataType	type;
+	int		size;
+} disStructElement;
+
+typedef struct {
+	char	*name;				// name of the structure
+	int		size;				// size of structure
+	int		count;				// number of lines
+	disStructElement	*elements;	// array of all elements of the struct
+} disStructEntry;
+
+static int				disStructCounts;
+static disStructEntry	*disStructEntries;
+
+typedef struct {
+	long	addr;				// address of the label
+	Disass68kDataType	type;	// type of the data on the address
+	int		size;				// size of the label, references inside it are addressed via base address + offset
+	int		count;				// number of elements at this address with the given size
+	int		structIndex;		// -1 no struct to describe the element
+	char	*name;				// name of the label
+	char	*comment;			// optional comment
+} disSymbolEntry;
+
+static int				disSymbolCounts;
+static disSymbolEntry	*disSymbolEntries;
+
+
+static inline unsigned short	Disass68kGetWord(long addr)
+{
+	if ( ! valid_address ( addr , 2 ) )
+		return 0;
+
+#ifndef WINUAE_FOR_HATARI
+	return get_word(addr);
+#else
+	return get_word_debug(addr);
+#endif
+}
+
+// Load a text file into memory, count the lines and replace the LF with 0-bytes.
+static int			Disass68kLoadTextFile(const char *filename, char **filebuf)
+{
+	long	index;
+	long	fileLength;
+	int	lineCount = 0;
+	char	*fbuf;
+	FILE	*f;
+	
+	if(filebuf)
+		*filebuf = NULL;
+	f = fopen(filename, "r");
+	if (!f)
+		return 0;
+	if (fseek(f, 0, SEEK_END))
+		goto out;
+	fileLength = ftell(f);
+	if (fileLength <= 0)
+		goto out;
+	if (fseek(f, 0, SEEK_SET))
+		goto out;
+	fbuf = malloc(fileLength);
+	if(!fbuf)
+		goto out;
+	if((size_t)fileLength != fread(fbuf, sizeof(char), fileLength, f))
+	{
+		free(fbuf);
+		goto out;
+	}
+
+	for(index=0; indexname = strdup(line+1);
+			se->count = 0;
+			se->elements = malloc(sizeof(disStructElement) * lineCount);	// lineCount is way too much, but safe
+		} else if(line[0] == '}') {
+			if(se)
+			{
+				se->size = 0;
+				for(j=0; jcount; ++j)
+					se->size += se->elements[j].size;
+//				printf("%s : %d bytes\n", se->name, se->size);
+				++disStructCounts;
+				se = NULL;
+			}
+		} else if(line[0] == '#') {
+			disStructElement	dse;
+			int	val = 0;
+			int index = 2;
+			if(line[1] == 'A' || line[1] == 'B')
+			{
+				for(; isdigit((unsigned char)line[index]); ++index)
+				{
+					val *= 10;
+					val += line[index] - '0';
+				}
+			}
+			if(val == 0) val = 1;
+			dse.name = NULL;
+			switch(line[1])
+			{
+			case 'A':	dse.type = dtStringArray; dse.size = val; dse.name = strdup(line + index + 1); break;
+			case 'B':	dse.type = dtByte; dse.size = val; break;
+			case 'W':	dse.type = dtWord; dse.size = 2; break;
+			case 'L':	dse.type = dtLong; dse.size = 4; break;
+			case 'C':	dse.type = dtOpcode; dse.size = 2; break;
+			case 'f':	dse.type = dtFunctionPointer; dse.size = 4; break;
+			case 'p':	dse.type = dtPointer; dse.size = 4; break;
+			default:	dse.type = dtNone; dse.size = 0;
+					printf("Unknown type in \"%s\"\n", line); break;
+			}
+			if(!dse.name)
+				dse.name = strdup(line+3); 
+			dse.comment = NULL;
+			if(se)
+				se->elements[se->count++] = dse;
+		}
+	}
+	free(fbuf);
+}
+
+static void			Disass68kLoadSymbols(const char *filename)
+{
+	int	i,j;
+	char	*nextLine;
+	char	*line;
+	char	*fbuf = NULL;
+	int		lineCount = Disass68kLoadTextFile(filename, &fbuf);
+	if(!lineCount) return;
+	disSymbolEntries = realloc(disSymbolEntries, sizeof(disSymbolEntry) * (disSymbolCounts + lineCount));
+	if(!disSymbolEntries) { free(fbuf); return; }
+	line = fbuf;
+
+	for(i=0; iname == NULL)
+					break;
+				if(strcmp(parameterPtr[0], se->name))
+					continue;
+				size = se->size;
+				disSymbolEntries[disSymbolCounts].structIndex = j;
+			}
+		}
+		if(!size)
+			continue;
+
+		disSymbolEntries[disSymbolCounts].type = type;
+		disSymbolEntries[disSymbolCounts].size = size;
+		disSymbolEntries[disSymbolCounts].count = atol(parameterPtr[1]);
+		disSymbolEntries[disSymbolCounts].name = strdup(parameterPtr[2]);
+		disSymbolEntries[disSymbolCounts].comment = NULL;
+		if(parameterCount == 4)
+			disSymbolEntries[disSymbolCounts].comment = strdup(parameterPtr[3]);
+		++disSymbolCounts;
+	}
+	free(fbuf);
+}
+
+static void			Disass68kInit(const char *baseDirectory)
+{
+	char	filename[FILENAME_MAX];
+
+	disStructCounts = 0;
+	sprintf(filename, "%s/DisassStructs.txt", baseDirectory);
+	Disass68kLoadStructInfo(filename);
+	sprintf(filename, "%s/DisassStructs_%4.4X.txt", baseDirectory, TosVersion);
+	Disass68kLoadStructInfo(filename);
+
+	disSymbolCounts = 0;
+	sprintf(filename, "%s/DisassSymbols.txt", baseDirectory);
+	Disass68kLoadSymbols(filename);
+	sprintf(filename, "%s/DisassSymbols_%4.4X.txt", baseDirectory, TosVersion);
+	Disass68kLoadSymbols(filename);
+}
+
+
+
+static Disass68kDataType	Disass68kType(long addr, char *addressLabel, char *commentBuffer, int *count)
+{
+	int	i,j;
+
+	addressLabel[0] = 0;
+	commentBuffer[0] = 0;
+	for(i=0; iaddr;
+
+		if(offset < 0 || offset >= dse->count * dse->size)
+			continue;
+
+		// no special struct that devices this value?
+		if(dse->structIndex < 0)
+		{
+			offset = (offset + dse->size - 1) / dse->size;
+			*count = dse->count - offset;
+			if(offset == 0)	// only in the first line
+			{
+				strcpy(addressLabel, dse->name);
+				if(dse->comment)
+					strcpy(commentBuffer, dse->comment);
+			}
+			return dse->type;
+		}
+
+		*count = 1;
+		se = &disStructEntries[dse->structIndex];
+		for(j=0; jcount; ++j)
+		{
+			const disStructElement	*e = &se->elements[j];
+			if(offset < e->size)
+			{
+				if(e->type == dtStringArray)
+					*count = e->size;
+				if(j == 0)
+					strcpy(addressLabel, dse->name);
+
+				sprintf(commentBuffer, "[%s]", e->name);
+				if(e->comment)
+					strcat(commentBuffer, e->comment);
+				return e->type;
+			}
+			offset -= e->size;
+		}
+		return dse->size;
+	}
+	return dtNone;
+}
+
+/***
+ *	Lookup a symbol name
+ ***/
+static const char	*Disass68kSymbolName(long addr, int size)
+{
+	int	i;
+
+	for(i=0; iaddr;
+		int	reminder;
+
+		if(offset < 0 || offset >= dse->count * dse->size)
+			continue;
+
+		if(dse->name[0] == 0)
+			return NULL;
+
+		reminder = offset % dse->size;
+		offset /= dse->size;
+
+		strcpy(symbolName, dse->name);
+		if(offset)
+			sprintf(symbolName+strlen(symbolName), "+%d*%d", dse->size, offset);
+		if(reminder)
+			sprintf(symbolName+strlen(symbolName), "+%d", reminder);
+		return symbolName;
+	}
+	return NULL;
+}
+
+/***
+ *	return a string pointer to display a register name
+ ***/
+static const char	*Disass68kRegname(int reg)
+{
+	static char		regName[3];
+	switch(reg)
+	{
+	case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
+		sprintf(regName, "%c%d", (options & doptRegisterSmall ? 'd' : 'D'), reg);
+		break;
+
+	case 0x0F:
+		if(options & doptStackSP)	// display A7 as SP
+		{
+			if(options & doptRegisterSmall)
+				return "sp";
+			return "SP";
+		}
+	case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E:
+		sprintf(regName, "%c%d", (options & doptRegisterSmall ? 'a' : 'A'), reg & 7);
+		break;
+	}
+	return regName;
+}
+
+/***
+ *	return a string pointer to display a register name
+ ***/
+static const char	*Disass68kNumber(int val)
+{
+	static char		numString[32];
+	if(val >= -9 && val <= 9)
+	{
+		sprintf(numString, "%d", val);
+	} else {
+		// 4 characters/numbers or underscore (e.g. for cookies)
+		unsigned char c0 = (val >> 24) & 0xFF;
+		unsigned char c1 = (val >> 16) & 0xFF;
+		unsigned char c2 = (val >>  8) & 0xFF;
+		unsigned char c3 = (val >>  0) & 0xFF;
+		if((isalnum(c0) || c0 == '_') && (isalnum(c1) || c1 == '_') && (isalnum(c2) || c2 == '_') && (isalnum(c3) || c3 == '_'))
+		{
+			sprintf(numString, "'%c%c%c%c'", c0, c1, c2, c3);
+		} else {
+			sprintf(numString, "$%x", val);
+		}
+	}
+	return numString;
+}
+
+/***
+ *	Supported registers for e.g. MOVEC
+ ***/
+#define REG_CCR			-1
+#define REG_SR			-2
+#define REG_PC			-3
+#define REG_ZPC			-4
+#define REG_TT0			-8
+#define REG_TT1			-9
+#define REG_MMUSR		-10
+#define REG_USP			0x800
+#define REG_SFC			0x000
+#define REG_DFC			0x001
+#define REG_TC			0x10000
+#define REG_SRP			0x10002
+#define REG_CRP			0x10003
+#define REG_VAL			0x20000
+#define REG_CACHES_NONE	0x20010
+#define REG_CACHES_IC	0x20011
+#define REG_CACHES_DC	0x20012
+#define REG_CACHES_ICDC	0x20013
+#define REG_FPU_FPCR	0x30004
+#define REG_FPU_FPSR	0x30002
+#define REG_FPU_FPIAR	0x30001
+
+static const char *Disass68kSpecialRegister(int reg)
+{
+	static char	buf[8];
+	const char	*sp = NULL;
+	switch (reg)
+	{
+	case 0x000:		sp = "SFC"; break;
+	case 0x001:		sp = "DFC"; break;
+	case 0x002:		sp = "CACR"; break;
+	case 0x003:		sp = "TC"; break;
+	case 0x004:		sp = "ITT0"; break;	// IACR0 on an 68EC040 only
+	case 0x005:		sp = "ITT1"; break;	// IACR1 on an 68EC040 only
+	case 0x006:		sp = "DTT0"; break;	// DACR0 on an 68EC040 only
+	case 0x007:		sp = "DTT1"; break;	// DACR1 on an 68EC040 only
+	case 0x008:		sp = "BUSCR"; break;
+
+	case 0x800:		sp = "USP"; break;
+	case 0x801:		sp = "VBR"; break;
+	case 0x802:		sp = "CAAR"; break;
+	case 0x803:		sp = "MSP"; break;
+	case 0x804:		sp = "ISP"; break;
+	case 0x805:		sp = "MMUSR"; break;
+	case 0x806:		sp = "URP"; break;
+	case 0x807:		sp = "SRP"; break;
+	case 0x808:		sp = "PCR"; break;
+
+	// MMU register
+	case 0x10000:	sp = "TC"; break;
+	case 0x10001:	sp = "DRP"; break;
+	case 0x10002:	sp = "SRP"; break;
+	case 0x10003:	sp = "CRP"; break;
+	case 0x10004:	sp = "CAL"; break;
+	case 0x10005:	sp = "VAL"; break;
+	case 0x10006:	sp = "SCCR"; break;
+	case 0x10007:	sp = "ACR"; break;
+
+	case REG_CCR:	sp = "CCR"; break;
+	case REG_SR:	sp = "SR"; break;
+	case REG_PC:	sp = "PC"; break;
+	case REG_ZPC:	sp = "ZPC"; break;
+	case REG_TT0:	sp = "TT0"; break;
+	case REG_TT1:	sp = "TT1"; break;
+	case REG_MMUSR:	sp = "MMUSR"; break;
+
+	case REG_VAL:	sp = "VAL"; break;
+
+	case REG_CACHES_NONE:	sp = "NC"; break;
+	case REG_CACHES_IC:		sp = "IC"; break;
+	case REG_CACHES_DC:		sp = "DC"; break;
+	case REG_CACHES_ICDC:	sp = "IC/DC"; break;	// GCC lists this as "BC"
+
+	case REG_FPU_FPCR:		sp = "FPCR"; break;
+	case REG_FPU_FPSR:		sp = "FPSR"; break;
+	case REG_FPU_FPIAR:		sp = "FPIAR"; break;
+
+	// unknown register => unknown opcode!
+	default:		return NULL;
+	}
+
+	if(options & doptRegisterSmall)
+	{
+		char	*bp;
+		strcpy(buf, sp);
+		for (bp = buf; *bp; ++bp)
+			*bp = tolower((unsigned char)*bp);
+		return buf;
+	}
+	return sp;
+}
+
+/***
+ *	680x0 EA disassembly, supports all address modes
+ *
+ *	disassbuf = output buffer for the EA, empty string in case of an illegal EA
+ *	addr = pointer to the address, which Disass68kGetWord() will allow to read memory.
+ *		   Incremented by the function to point behind the opcode, when done
+ *	ea = 6-bit ea from the opcode
+ *  size = addressed size of the opcode in bytes (e.g. 1,2,4 for MOVE.B, MOVE.W, MOVE.L), only used for immediate addressing
+ ***/
+
+#define EA_Dn				0x00001	// Dn
+#define EA_An				0x00002	// An
+#define EA_Ani				0x00004	// (An)
+#define EA_Anip				0x00008	// (An)+
+#define EA_piAn				0x00010	// -(An)
+#define EA_dAn				0x00020	// d(An), d(An,Dn), etc.
+#define EA_PCRel			0x00040	// d(PC), d(PC,Dn), etc.
+#define EA_Abs				0x00080	// abs.w, abs.l
+#define EA_Immed			0x00100	// #
+
+#define EA_ImmedParameter	0x0200	// an immediate value as a parameter
+#define EA_ValueParameter	0x0400	// an immediate value as a parameter without the "#"
+#define EA_SpecialRegister	0x0800	// any special register e.g. SR,CCR,USP,etc
+#define EA_PCDisplacement	0x1000	// PC relative jump, like for BRA and friends
+
+#define EA_All				(EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs | EA_Immed | EA_PCRel)
+#define EA_Dest				(EA_Dn | EA_An | EA_Ani | EA_Anip | EA_piAn | EA_dAn | EA_Abs)
+
+static char		*Disass68kEA(char *disassbuf, char *commentBuffer, long *addr, long opcodeAddr, int ea, int size, int allowedEAs, int parameterValue, int disassFlag)
+{
+	unsigned short	eWord1;
+	unsigned short	eWord2;
+	int				xn,c,scale;
+	int				reg = ea & 7;
+	const char		*sp;
+	long			val;
+	char	regName[3];
+	signed long	pcoffset;
+
+	disassbuf[0] = 0;
+	switch(ea)
+	{
+	// M=000 = 0	Dn
+	// Data Register Direct Mode
+	// Dn
+	// M=001 = 1	An
+	// Address Register Direct Mode
+	// An
+	case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
+		if((allowedEAs & EA_Dn) != EA_Dn)
+			break;
+		sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
+		break;
+	case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E: case 0x0F:
+		if((allowedEAs & EA_An) != EA_An)
+			break;
+		sprintf(disassbuf, "%s", Disass68kRegname(ea & 0x0F));
+		break;
+
+	// M=010 = 2
+	// Address Register Indirect Mode
+	// (An)
+	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
+		if((allowedEAs & EA_Ani) != EA_Ani)
+			break;
+		sprintf(disassbuf, "(%s)", Disass68kRegname(reg | 8));
+		break;
+
+	// M=011 = 3
+	// Address Register Indirect with Postincrement Mode
+	// (An) +
+	case 0x18: case 0x19: case 0x1A: case 0x1B: case 0x1C: case 0x1D: case 0x1E: case 0x1F:
+		if((allowedEAs & EA_Anip) != EA_Anip)
+			break;
+		sprintf(disassbuf, "(%s)+", Disass68kRegname(reg | 8));
+		break;
+
+	// M=100 = 4
+	// Address Register Indirect with Predecrement Mode
+	// – (An)
+	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
+		if((allowedEAs & EA_piAn) != EA_piAn)
+			break;
+		sprintf(disassbuf, "-(%s)", Disass68kRegname(reg | 8));
+		break;
+
+	// M=101 = 5
+	// Address Register Indirect with Displacement Mode
+	// (d16,An)
+	case 0x28: case 0x29: case 0x2A: case 0x2B: case 0x2C: case 0x2D: case 0x2E: case 0x2F:
+		if((allowedEAs & EA_dAn) != EA_dAn)
+			break;
+		eWord1 = Disass68kGetWord(*addr); *addr += 2;
+		sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1), Disass68kRegname(reg | 8));
+		break;
+
+	// M=111 = 7, Xn/reg = 011 = 3
+	// Program Counter Indirect with Index (Base Displacement) Mode
+	// (bd, PC, Xn. SIZE*SCALE)
+	// Program Counter Memory Indirect Postindexed Mode
+	// ([bd,PC],Xn.SIZE*SCALE,od)
+	// Program Counter Memory Indirect Preindexed Mode
+	// ([bd,PC,Xn.SIZE*SCALE],od)
+	case 0x3B:
+		// This is equal to the following, except that instead of An, it is PC relative
+
+	// M=110 = 6
+	// Address Register Indirect with Index (Base Displacement) Mode
+	// (bd,An,Xn.SIZE*SCALE)
+	// Memory Indirect Postindexed Mode
+	// ([bd,An],Xn.SIZE*SCALE,od)
+	// Memory Indirect Preindexed Mode
+	// ([bd, An, Xn.SIZE*SCALE], od)
+	case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
+		eWord1 = Disass68kGetWord(*addr); *addr += 2;
+		xn = (eWord1 >> 12) & 0x0F;				// Register D0..D7/A0..A7
+		c = ((eWord1 >> 11) & 1) ? 'l' : 'w';	// Word/Long-Word Index Size 0 = Sign-Extended Word 1 = Long Word
+		scale = (eWord1 >> 9) & 3;				// Scale Factor 00 = 1 01 = 2 10 = 4 11 = 8
+
+		if(ea == 0x3B)
+		{
+			sp = Disass68kSpecialRegister(REG_PC);
+			if(!sp) return NULL;
+			strcpy(regName, sp);
+		} else {
+			sprintf(regName, "%s", Disass68kRegname(reg | 8));
+		}
+
+		if((eWord1 & 0x0100) == 0)
+		{
+			const char	*numStr;
+
+			// BRIEF EXTENSION WORD FORMAT
+			if(ea == 0x3B)
+			{
+				if((allowedEAs & EA_PCRel) != EA_PCRel)
+					break;
+			} else {
+				if((allowedEAs & EA_dAn) != EA_dAn)
+					break;
+			}
+
+			// Address Register Indirect with Index (8-Bit Displacement) Mode
+			// (d8 ,An, Xn.SIZE*SCALE)
+			numStr = Disass68kNumber(eWord1 & 0xFF);
+			if(numStr[0] == '0' && numStr[1] == 0)
+				numStr = "";
+
+			// scale is only on 68020 and later supported
+			if(scale != 0 && (optionCPUTypeMask & MC_020) == 0)
+				return NULL;
+
+			if(scale == 0)
+			{
+#if ADDRESS_ON_PC
+				if(ea == 0x3B)
+					sprintf(disassbuf, "$%lx(%s,%s.%c)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c);
+				else
+#endif
+					sprintf(disassbuf, "%s(%s,%s.%c)", numStr, regName, Disass68kRegname(xn), c);
+			} else
+			{
+#if ADDRESS_ON_PC
+				if(ea == 0x3B)
+					sprintf(disassbuf, "$%lx(%s,%s.%c*%d)", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2, Disass68kSpecialRegister(REG_PC), Disass68kRegname(xn), c, 1 << scale);
+				else
+#endif
+					sprintf(disassbuf, "%s(%s,%s.%c*%d)", numStr, regName, Disass68kRegname(xn), c, 1 << scale);
+			}
+#if USE_SYMBOLS
+			if(ea == 0x3B)
+			{
+				const char	*symStr = Disass68kSymbolName((signed char)(eWord1 & 0xFF) + opcodeAddr + 2, size);
+				if(symStr)
+				{
+					commentBuffer += strlen(commentBuffer);
+					sprintf(commentBuffer+strlen(commentBuffer), "%s", symStr);
+				}
+			}
+#endif
+#if !ADDRESS_ON_PC
+			if(ea == 0x3B)
+			{
+				commentBuffer += strlen(commentBuffer);
+				sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed char)(eWord1 & 0xFF) + opcodeAddr + 2);
+			}
+#endif
+		} else {
+			// FULL EXTENSION WORD FORMAT
+
+			int	bs = (eWord1 >> 7) & 1;		// Base Register Suppress 0 = Base Register Added 1 = Base Register Suppressed
+			int	is = (eWord1 >> 6) & 1;		// Index Suppress 0 = Evaluate and Add Index Operand 1 = Suppress Index Operand
+			int	bdSize = (eWord1 >> 4) & 3;	// Base Displacement Size 00 = Reserved 01 = Null Displacement 10 = Word Displacement 11 = Long Displacement
+			int	iis = eWord1 & 7;		// Index/Indirect Selection Indirect and Indexing Operand Determined in Conjunction with Bit 6, Index Suppress
+			bool	prefixComma;
+			long	bd, od;
+
+			// reserved, has to be 0
+			if((eWord1 & 8) != 0 || bdSize == 0 || (is && iis > 3) || iis == 4)
+				break;
+
+			// full extension format is only supported on 68020 or later
+			if((optionCPUTypeMask & MC_020) == 0)
+				return NULL;
+
+			if(ea == 0x3B)
+			{
+				if((allowedEAs & EA_PCRel) != EA_PCRel)
+					break;
+			} else {
+				if((allowedEAs & EA_dAn) != EA_dAn)
+					break;
+			}
+
+			bd = 0;
+			switch(bdSize)
+			{
+			case 3: 
+				bd = Disass68kGetWord(*addr); *addr += 2;
+				bd <<= 16;
+			case 2:
+				bd |= Disass68kGetWord(*addr); *addr += 2;
+				break;
+			default:
+				break;
+			}
+
+			prefixComma = false;
+			if(bdSize >= 2 && iis == 0)
+				sprintf(disassbuf, "%s", Disass68kNumber(bd));
+			strcat(disassbuf, "(");
+			if(iis != 0)
+			{
+				// the CPU32 doesn't support the memory indirect mode
+				if(optionCPUTypeMask & MC_CPU32)
+					return NULL;
+
+				strcat(disassbuf, "[");
+			}
+			if(bdSize >= 2 && iis != 0)
+			{
+				sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(bd));
+				prefixComma = true;
+			}
+			if(bdSize == 1 && ((bs && is && iis > 0) || (bs && iis >= 5)))
+			{
+				if(ea == 0x3B)
+				{
+					sp = Disass68kSpecialRegister(REG_ZPC);
+					if(!sp) return NULL;
+					strcat(disassbuf, sp);
+				} else {
+					strcat(disassbuf, "0");
+				}
+			}
+			if(!bs)
+			{
+				if(prefixComma)
+					strcat(disassbuf, ",");
+				strcat(disassbuf, regName);
+				prefixComma = true;
+			}
+			if(iis >= 5 && iis <= 7)
+			{
+				strcat(disassbuf, "]");
+				prefixComma = true;
+			}
+			if(!is)
+			{
+				if(prefixComma)
+					strcat(disassbuf, ",");
+				if(scale == 0)
+				{
+					sprintf(disassbuf+strlen(disassbuf), "%s.%c", Disass68kRegname(xn), c);
+				} else
+				{
+					sprintf(disassbuf+strlen(disassbuf), "%s.%c*%d", Disass68kRegname(xn), c, 1 << scale);
+				}
+			}
+			if(iis >= 1 && iis <= 3)
+			{
+				strcat(disassbuf, "]");
+				prefixComma = true;
+			}
+			od = 0;
+			switch(iis & 3)
+			{
+			case 3:
+				od = Disass68kGetWord(*addr); *addr += 2;
+				od <<= 16;
+			case 2:
+				od |= Disass68kGetWord(*addr); *addr += 2;
+				if(prefixComma)
+					strcat(disassbuf, ",");
+				sprintf(disassbuf+strlen(disassbuf), "%s", Disass68kNumber(od));
+				break;
+			default:
+				break;
+			}
+			strcat(disassbuf, ")");
+		}
+		break;
+
+	// M=111 = 7, Xn/reg = 000 = 0
+	// Absolute Short Addressing Mode
+	// (xxx).W
+	case 0x38:
+		if((allowedEAs & EA_Abs) != EA_Abs)
+			break;
+		eWord1 = Disass68kGetWord(*addr); *addr += 2;
+		val = eWord1;
+		if(eWord1 & 0x8000)
+			val |= 0xFFFF0000;
+#if USE_SYMBOLS
+		sp = Disass68kSymbolName(val, size);
+		if(sp)
+		{
+			if(options & doptNoBrackets)
+				sprintf(disassbuf, "%s.w", sp);
+			else
+				sprintf(disassbuf, "(%s).w", sp);
+			break;
+		}
+#endif
+		if(options & doptNoBrackets)
+		{
+			if(val & 0x80000000)
+				sprintf(disassbuf, "$%8.8lx.w", val);
+			else
+				sprintf(disassbuf, "$%4.4lx.w", val);
+		} else {
+			if(val & 0x80000000)
+				sprintf(disassbuf, "($%8.8lx).w", val);
+			else
+				sprintf(disassbuf, "($%4.4lx).w", val);
+		}
+		break;
+
+	// M=111 = 7, Xn/reg = 001 = 1
+	// Absolute Long Addressing Mode
+	// (xxx).L
+	case 0x39:
+		if((allowedEAs & EA_Abs) != EA_Abs)
+			break;
+		eWord1 = Disass68kGetWord(*addr); *addr += 2;
+		eWord2 = Disass68kGetWord(*addr); *addr += 2;
+#if USE_SYMBOLS
+		val = (eWord1 << 16) | eWord2;
+		sp = Disass68kSymbolName(val, size);
+		if(sp)
+		{
+			if(options & doptNoBrackets)
+				sprintf(disassbuf, "%s", sp);
+			else
+				sprintf(disassbuf, "(%s).l", sp);
+			break;
+		}
+#endif
+		if(options & doptNoBrackets)
+			sprintf(disassbuf, "%s", Disass68kNumber((eWord1 << 16) | eWord2));
+		else
+			sprintf(disassbuf, "(%s).l", Disass68kNumber((eWord1 << 16) | eWord2));
+		break;
+
+	// M=111 = 7, Xn/reg = 010 = 2
+	// Program Counter Indirect with Displacement Mode
+	// (d16,PC)
+	case 0x3A:
+		if((allowedEAs & EA_PCRel) != EA_PCRel)
+			break;
+		eWord1 = Disass68kGetWord(*addr); *addr += 2;
+		sp = Disass68kSpecialRegister(REG_PC);
+		if(!sp) return NULL;
+#if ADDRESS_ON_PC
+	#if USE_SYMBOLS
+		sp = Disass68kSymbolName(((signed short)eWord1 + *addr - 2), size);
+		if(sp)
+		{
+			sprintf(disassbuf, "%s(%s)", sp, Disass68kSpecialRegister(REG_PC));
+		} else {
+			sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
+		}
+	#else
+		sprintf(disassbuf, "$%lx(%s)", (signed short)eWord1 + *addr - 2, Disass68kSpecialRegister(REG_PC));
+	#endif
+#else
+		sprintf(disassbuf, "%s(%s)", Disass68kNumber(eWord1),sp);
+		sprintf(commentBuffer+strlen(commentBuffer), "$%lx", (signed short)eWord1 + *addr - 2);
+#endif
+		break;
+
+	// M=111 = 7, Xn/reg = 100 = 4
+	// Immediate Data
+	// #
+	case 0x3C:
+		if((allowedEAs & EA_Immed) != EA_Immed)
+			break;
+		eWord1 = Disass68kGetWord(*addr); *addr += 2;
+		goto immed;
+
+	case 0x0100:	// Immediate Value as a parameter
+		if((allowedEAs & EA_ImmedParameter) != EA_ImmedParameter)
+			break;
+		eWord1 = parameterValue;
+	immed:
+		switch(size)
+		{
+		case 1: eWord1 &= 0xFF;
+		case 2:
+#if USE_SYMBOLS
+				if(disassFlag)
+				{
+					val = eWord1;
+					if(eWord1 & 0x8000)
+						val |= 0xFFFF0000;
+					sp = Disass68kSymbolName(val, size);
+					if(sp)
+					{
+						sprintf(disassbuf, "#%s", sp);
+						break;
+					}
+				}
+#endif
+				sprintf(disassbuf, "#%s", Disass68kNumber(eWord1));
+				break;
+		case 4: eWord2 = Disass68kGetWord(*addr); *addr += 2;
+#if USE_SYMBOLS
+				if(disassFlag)
+				{
+					val = (eWord1 << 16) | eWord2;
+					sp = Disass68kSymbolName(val, size);
+					if(sp)
+					{
+						sprintf(disassbuf, "#%s", sp);
+						break;
+					}
+				}
+#endif
+				sprintf(disassbuf, "#%s", Disass68kNumber((eWord1 << 16) | eWord2));
+				break;
+		}
+		break;
+
+	case 0x0103:
+		if((allowedEAs & EA_ValueParameter) != EA_ValueParameter)
+			break;
+		sprintf(disassbuf, "%d", parameterValue);
+		break;
+
+	case 0x0101:	// Special Registers as in the parameter
+		if((allowedEAs & EA_SpecialRegister) != EA_SpecialRegister)
+			break;
+		sp = Disass68kSpecialRegister(parameterValue);
+		if(!sp) return NULL;
+		strcpy(disassbuf, sp);
+		break;
+
+	case 0x0102:	// PC relative jump, like for BRA and friends
+		if((allowedEAs & EA_PCDisplacement) != EA_PCDisplacement)
+			break;
+		pcoffset = 0;
+		switch(size)
+		{
+		case 1: pcoffset = (signed char)parameterValue;
+				break;
+		case 2: eWord1 = Disass68kGetWord(*addr); *addr += 2;
+				pcoffset = (signed short)eWord1;
+				pcoffset -= 2;
+				break;
+		case 4: eWord1 = Disass68kGetWord(*addr); *addr += 2;
+				eWord2 = Disass68kGetWord(*addr); *addr += 2;
+				pcoffset = (signed int)((eWord1 << 16) | eWord2);
+				pcoffset -= 4;
+				break;
+		}
+#if ADDRESS_ON_PC
+	#if USE_SYMBOLS
+		sp = Disass68kSymbolName((*addr + pcoffset), size);
+		if(sp)
+		{
+			strcat(disassbuf, sp);
+		} else {
+			sprintf(disassbuf, "$%lx", *addr + pcoffset);
+		}
+	#else
+		sprintf(disassbuf, "$%lx", *addr + pcoffset);
+	#endif
+#else
+		if(pcoffset < 0)
+		{
+			sprintf(disassbuf, "*-$%lx", -pcoffset - 2);
+		} else {
+			sprintf(disassbuf, "*+$%lx", pcoffset + 2);
+		}
+		sprintf(commentBuffer+strlen(commentBuffer), "$%lx", *addr + pcoffset);
+#endif
+		break;
+
+	default:	// 0x3D..0x3F are reserved
+		break;
+
+	}
+	if(disassbuf[0] == 0)
+		return NULL;
+	return disassbuf + strlen(disassbuf);
+}
+
+/***
+ *	Create a register list for the MOVEM opcode
+ ***/
+static char	*Disass68kReglist(char *buf, unsigned short reglist)
+{
+	int bit;
+	int lastBit = -99;
+	int lastBitStart = -99;
+	char	regD = options & doptRegisterSmall ? 'd' : 'D';
+	char	regA = options & doptRegisterSmall ? 'a' : 'A';
+	for(bit=0; bit<=15; ++bit)
+	{
+		// bit clear?
+		if((reglist & (1 << bit)) == 0)
+		{
+			// do we have a run? => close it!
+			if(lastBitStart >= 0 && lastBitStart != (bit - 1))
+			{
+				*buf++ = '-';
+				*buf++ = ((bit-1) >= 8) ? regA : regD;
+				*buf++ = '0' + ((bit-1) & 7);
+			}
+			lastBitStart = -1;
+			continue;
+		}
+		// reset when switching from D to A
+		if(bit == 8 && lastBitStart >= 0)
+		{
+			*buf++ = '-';
+			*buf++ = regD;
+			*buf++ = '7';
+			lastBit = 0;
+			lastBitStart = -99;
+		}
+		// separate bits, skip runs of bits to merge them later
+		if(lastBit >= 0)
+		{
+			if(lastBit == bit - 1)
+			{
+				lastBit = bit;
+				continue;
+			}
+			*buf++ = '/';
+		}
+		*buf++ = (bit >= 8) ? regA : regD;
+		*buf++ = '0' + (bit & 7);
+		lastBit = bit;
+		lastBitStart = bit;
+	}
+	if(lastBitStart >= 0 && lastBitStart != (bit - 1))
+	{
+		*buf++ = '-';
+		*buf++ = regA;
+		*buf++ = '7';
+	}
+	if(lastBit < 0)
+	{
+		*buf++ = '0';
+	}
+	*buf = 0;
+	return buf;
+}
+
+/***
+ *	Flip the bits in an unsigned short, for MOVEM RegList,-(An)
+ ***/
+static unsigned short	Disass68kFlipBits(unsigned short mask)
+{
+	unsigned short	retMask = 0;
+	int	i;
+
+	for(i=0; i<=15; ++i)
+		if(mask & (1 << i))
+			retMask |= (1 << (15-i));
+	return retMask;
+}
+
+/***
+ *	Create a register list for the MOVEM opcode
+ ***/
+static char	*Disass68kFPUReglist(char *buf, unsigned char reglist)
+{
+	int bit;
+	int lastBit = -99;
+	int lastBitStart = -99;
+	char	regFP1 = options & doptRegisterSmall ? 'f' : 'F';
+	char	regFP2 = options & doptRegisterSmall ? 'p' : 'P';
+	for(bit=0; bit<=7; ++bit)
+	{
+		// bit clear?
+		if((reglist & (1 << bit)) == 0)
+		{
+			// do we have a run? => close it!
+			if(lastBitStart >= 0 && lastBitStart != (bit - 1))
+			{
+				*buf++ = '-';
+				*buf++ = regFP1;
+				*buf++ = regFP2;
+				*buf++ = '0' + ((bit-1) & 7);
+			}
+			lastBitStart = -1;
+			continue;
+		}
+		// separate bits, skip runs of bits to merge them later
+		if(lastBit >= 0)
+		{
+			if(lastBit == bit - 1)
+			{
+				lastBit = bit;
+				continue;
+			}
+			*buf++ = '/';
+		}
+		*buf++ = regFP1;
+		*buf++ = regFP2;
+		*buf++ = '0' + (bit & 7);
+		lastBit = bit;
+		lastBitStart = bit;
+	}
+	if(lastBitStart >= 0 && lastBitStart != (bit - 1))
+	{
+		*buf++ = '-';
+		*buf++ = regFP1;
+		*buf++ = regFP2;
+		*buf++ = '7';
+	}
+	if(lastBit < 0)
+	{
+		*buf++ = '0';
+	}
+	*buf = 0;
+	return buf;
+}
+
+
+/***
+ *	List of special cases for the operands
+ ***/
+typedef enum {
+	ofNone,
+	ofEa,
+	ofDn,
+	ofAn,
+	ofAni,
+	ofI,
+	ofSpecReg,
+	ofSpecExtReg,
+	ofD16An,
+	ofDestDn,
+	ofDestAn,
+	ofExtReg,
+	ofExtAnip,
+	ofExtReg0,
+	ofExtRegA0,
+	ofExtRegD04,
+	ofExtRegA05,
+	ofFPUReglist,
+	ofFPUSRRegList,
+	ofDestEa6,
+	ofDestAbsL,
+	ofIOpcode,
+	ofCAS,
+	ofCAS2,
+	ofI3,
+	ofExtIm,
+	ofExtIm32,
+	ofExtIm4,
+	ofExtIm10,
+	ofDisp,
+	ofPiAn,
+	ofDestPiAn,
+	ofAnip,
+	ofDestAnip,
+	ofBFEa,
+	ofRegList,
+	ofExt4Dn,
+	ofFPU,
+	ofFPUMOVE,
+	ofFMOVECR,
+	ofFPU3Reg,
+	ofLineA
+} Disass68kOpcodeFormat;
+
+
+/***
+ *	The order of the table is not important (with the exception of some FPU opcodes, which are commented further down),
+ *	as each opcode should decline if it doesn't match 100%. The 68k CPU also doesn't do guessing based on the context!
+ ***/
+typedef const struct {
+	int				cpuMask;
+	unsigned long	opcodeMask[2*5];
+	signed char		operationSize[4];
+	char			op[5];
+	const char		*opcodeName;
+	int				parameter[5];
+	int				disassFlag;
+} OpcodeTableStruct;
+
+static OpcodeTableStruct	OpcodeTable[] = {
+	{ MC_ALL, {0xff00, 0x0000}, {-1,6,2,0}, {ofI,ofEa}, "ORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL, {0xf1c0, 0x0100}, {4}, {ofDestDn,ofEa}, "BTST",{0,EA_An|EA_Immed} },
+	{ MC_ALL, {0xf1c0, 0x0140}, {4}, {ofDestDn,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL, {0xf1c0, 0x0180}, {4}, {ofDestDn,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL, {0xf1c0, 0x01C0}, {4}, {ofDestDn,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL-MC68060, {0xf1f8, 0x0108}, {2}, {ofD16An,ofDestDn}, "MOVEP.W"},
+	{ MC_ALL-MC68060, {0xf1f8, 0x0148}, {4}, {ofD16An,ofDestDn}, "MOVEP.L"},
+	{ MC_ALL-MC68060, {0xf1f8, 0x0188}, {2}, {ofDestDn,ofD16An}, "MOVEP.W"},
+	{ MC_ALL-MC68060, {0xf1f8, 0x01C8}, {4}, {ofDestDn,ofD16An}, "MOVEP.L"},
+	{ MC_ALL, {0xff00, 0x0200}, {-1,6,2,0}, {ofI,ofEa}, "ANDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL, {0xff00, 0x0400}, {-1,6,2,0}, {ofI,ofEa}, "SUBI.?",{0,EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL, {0xff00, 0x0600}, {-1,6,2,0}, {ofI,ofEa}, "ADDI.?",{0,EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL, {0xffc0, 0x0800}, {1}, {ofI,ofEa}, "BTST",{0,EA_An|EA_Immed} },
+	{ MC_ALL, {0xffc0, 0x0840}, {1}, {ofI,ofEa}, "BCHG",{0,EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL, {0xffc0, 0x0880}, {1}, {ofI,ofEa}, "BCLR",{0,EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL, {0xffc0, 0x08C0}, {1}, {ofI,ofEa}, "BSET",{0,EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL, {0xff00, 0x0A00}, {-1,6,2,0}, {ofI,ofEa}, "EORI.?",{0,EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL, {0xff00, 0x0C00}, {-1,6,2,0}, {ofI,ofEa}, "CMPI.?",{0,EA_Immed|EA_An}},
+	{ MC_ALL, {0xffff, 0x003C}, {1}, {ofEa,ofSpecReg}, "ORI",{0,REG_CCR} },
+	{ MC_ALL, {0xffff, 0x007C}, {2}, {ofEa,ofSpecReg}, "ORI",{0,REG_SR} },
+	{ MC_ALL, {0xffff, 0x023C}, {1}, {ofEa,ofSpecReg}, "ANDI",{0,REG_CCR} },
+	{ MC_ALL, {0xffff, 0x027C}, {2}, {ofEa,ofSpecReg}, "ANDI",{0,REG_SR} },
+	{ MC_ALL, {0xffff, 0x0A3C}, {1}, {ofEa,ofSpecReg}, "EORI",{0,REG_CCR} },
+	{ MC_ALL, {0xffff, 0x0A7C}, {2}, {ofEa,ofSpecReg}, "EORI",{0,REG_SR} },
+	{ MC68020, {0xffc0, 0x06C0}, {1}, {ofEa}, "CALLM",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
+	{ MC68020, {0xfff0, 0x06C0}, {1}, {ofEa}, "RTM"},
+	{ MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0000}, {-1,9,2,0}, {ofEa,ofExtReg}, "CMP2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
+	{ MC_020, {0xf9c0, 0x00C0, 0x0fff,0x0800}, {-1,9,2,0}, {ofEa,ofExtReg}, "CHK2.?",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
+	{ MC_020&~MC_CPU32, {0xffc0, 0x0AC0, 0xFE38,0x0000}, {1}, {ofCAS,ofEa}, "CAS.B",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
+	{ MC_020&~MC_CPU32, {0xffc0, 0x0CC0, 0xFE38,0x0000}, {2}, {ofCAS,ofEa}, "CAS.W",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
+	{ MC_020&~MC_CPU32, {0xffc0, 0x0EC0, 0xFE38,0x0000}, {4}, {ofCAS,ofEa}, "CAS.L",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
+	{ MC_020&~MC_CPU32, {0xffff, 0x0CFC, 0x0E38,0x0000, 0x0E38,0x0000}, {2}, {ofCAS2}, "CAS2.W"},
+	{ MC_020&~MC_CPU32, {0xffff, 0x0EFC, 0x0E38,0x0000, 0x0E38,0x0000}, {4}, {ofCAS2}, "CAS2.L"},
+	{ MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0000}, {-1,6,2,0}, {ofEa,ofExtReg}, "MOVES.?",{EA_Immed|EA_PCRel|EA_An|EA_Dn,0}},
+	{ MC68010|MC_020, {0xff00, 0x0e00, 0x0fff,0x0800}, {-1,6,2,0}, {ofExtReg,ofEa}, "MOVES.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
+
+	{ MC_ALL, {0xf000, 0x1000}, {1}, {ofEa,ofDestEa6}, "MOVE.B"},
+
+	{ MC_ALL, {0xf000, 0x2000}, {4}, {ofEa,ofDestEa6}, "MOVE.L"},
+	{ MC_ALL, {0xf1c0, 0x2040}, {4}, {ofEa,ofDestAn}, "MOVEA.L",{0},1},
+
+	{ MC_ALL, {0xf000, 0x3000}, {2}, {ofEa,ofDestEa6}, "MOVE.W"},
+	{ MC_ALL, {0xf1c0, 0x3040}, {2}, {ofEa,ofDestAn}, "MOVEA.W",{0},1},
+
+	{ MC_ALL, {0xff00, 0x4000}, {-1,6,2,0}, {ofEa}, "NEGX.?",{EA_Immed|EA_PCRel|EA_An}},
+	{ MC_020, {0xf1c0, 0x4100}, {4}, {ofEa,ofDestDn}, "CHK.L", {EA_An,0}},
+	{ MC_ALL, {0xf1c0, 0x4180}, {2}, {ofEa,ofDestDn}, "CHK.W", {EA_An,0}},
+	{ MC_ALL, {0xf1c0, 0x41c0}, {4}, {ofEa,ofDestAn}, "LEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn,0},1 },
+	{ MC_ALL, {0xff00, 0x4200}, {-1,6,2,0}, {ofEa}, "CLR.?",{EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL, {0xff00, 0x4400}, {-1,6,2,0}, {ofEa}, "NEG.?",{EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL, {0xff00, 0x4600}, {-1,6,2,0}, {ofEa}, "NOT.?",{EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL, {0xffc0, 0x40c0}, {2}, {ofSpecReg,ofEa}, "MOVE",{REG_SR,EA_Immed|EA_PCRel|EA_An} },
+	{ MC_ALL, {0xffc0, 0x42c0}, {1}, {ofSpecReg,ofEa}, "MOVE",{REG_CCR,EA_Immed|EA_PCRel|EA_An} },
+	{ MC_ALL, {0xffc0, 0x44c0}, {1}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_CCR} },
+	{ MC_ALL, {0xffc0, 0x46c0}, {2}, {ofEa,ofSpecReg}, "MOVE",{EA_An,REG_SR} },
+	{ MC_ALL, {0xffc0, 0x4800}, {1}, {ofEa}, "NBCD",{EA_Immed|EA_PCRel|EA_An}},
+	{ MC_020, {0xfff8, 0x4808}, {4}, {ofEa,ofI}, "LINK.L"},
+	{ MC_ALL, {0xffc0, 0x4840}, {0}, {ofEa}, "PEA",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn},1 },
+	{ MC_ALL, {0xfff8, 0x4840}, {4}, {ofEa}, "SWAP"},
+	{ MC68010|MC_020, {0xfff8, 0x4848}, {0}, {ofIOpcode}, "BKPT",{0x07} },
+	{ MC_ALL, {0xffc0, 0x4880, 0x10000}, {2}, {ofRegList,ofEa}, "MOVEM.W",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
+	{ MC_ALL, {0xffc0, 0x48c0, 0x10000}, {4}, {ofRegList,ofEa}, "MOVEM.L",{0,EA_Dn|EA_An|EA_Immed|EA_Anip|EA_PCRel} },
+	{ MC_ALL, {0xfff8, 0x4880}, {2}, {ofEa}, "EXT.W"},
+	{ MC_ALL, {0xfff8, 0x48c0}, {4}, {ofEa}, "EXT.L"},
+	{ MC_020, {0xfff8, 0x49c0}, {4}, {ofEa}, "EXTB.L"},
+	{ MC_ALL, {0xff00, 0x4a00}, {-1,6,2,0}, {ofEa}, "TST.?"},
+	{ MC_ALL, {0xffc0, 0x4ac0}, {1}, {ofEa}, "TAS",{EA_Immed|EA_PCRel|EA_An}},
+	{ MC_CPU32, {0xffff, 0x4afa}, {0}, {ofNone}, "BGND"},
+	{ MC_ALL, {0xffff, 0x4afc}, {0}, {ofNone}, "ILLEGAL"},
+	{ MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "MULU.L", {EA_An,0}},
+	{ MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "MULS.L", {EA_An,0}},
+	{ MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0000}, {4}, {ofEa,ofExtReg}, "DIVU.L", {EA_An,0}},
+	{ MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0800}, {4}, {ofEa,ofExtReg}, "DIVS.L", {EA_An,0}},
+	{ MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULU.L", {EA_An,0,0}},
+	{ MC_020, {0xffc0, 0x4c00, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "MULS.L", {EA_An,0,0}},
+	{ MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0400}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVU.L", {EA_An,0,0}},
+	{ MC_020, {0xffc0, 0x4c40, 0x8ff8, 0x0c00}, {4}, {ofEa,ofExtReg,ofExtReg0}, "DIVS.L", {EA_An,0,0}},
+	{ MC_ALL, {0xffc0, 0x4c80, 0x10000}, {2}, {ofEa,ofRegList}, "MOVEM.W",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
+	{ MC_ALL, {0xffc0, 0x4cc0, 0x10000}, {4}, {ofEa,ofRegList}, "MOVEM.L",{EA_Dn|EA_An|EA_Immed|EA_piAn,0} },
+	{ MC_ALL, {0xfff0, 0x4e40}, {0}, {ofIOpcode}, "TRAP",{0x0f} },
+	{ MC_ALL, {0xfff8, 0x4e50}, {2}, {ofAn,ofI}, "LINK"},
+	{ MC_ALL, {0xfff8, 0x4e58}, {4}, {ofAn}, "UNLK"},
+	{ MC_ALL, {0xfff8, 0x4e60}, {4}, {ofAn,ofSpecReg}, "MOVE",{0,REG_USP} },
+	{ MC_ALL, {0xfff8, 0x4e68}, {4}, {ofSpecReg,ofAn}, "MOVE",{REG_USP,0} },
+	{ MC_ALL, {0xffff, 0x4e70}, {0}, {ofNone}, "RESET"},
+	{ MC_ALL, {0xffff, 0x4e71}, {0}, {ofNone}, "NOP"},
+	{ MC_ALL, {0xffff, 0x4e72}, {2}, {ofI}, "STOP"},
+	{ MC_ALL, {0xffff, 0x4e73}, {0}, {ofNone}, "RTE"},
+	{ MC68010|MC_020, {0xffff, 0x4e74}, {2}, {ofI}, "RTD"},
+	{ MC_ALL, {0xffff, 0x4e75}, {0}, {ofNone}, "RTS"},
+	{ MC_ALL, {0xffff, 0x4e76}, {0}, {ofNone}, "TRAPV"},
+	{ MC_ALL, {0xffff, 0x4e77}, {0}, {ofNone}, "RTR"},
+	{ MC68010|MC_020, {0xffff, 0x4e7a, 0x10000}, {4}, {ofSpecExtReg,ofExtReg}, "MOVEC"},
+	{ MC68010|MC_020, {0xffff, 0x4e7b, 0x10000}, {4}, {ofExtReg,ofSpecExtReg}, "MOVEC"},
+	{ MC_ALL, {0xffc0, 0x4e80}, {0}, {ofEa}, "JSR",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
+	{ MC_ALL, {0xffc0, 0x4ec0}, {0}, {ofEa}, "JMP",{EA_Dn|EA_An|EA_Immed|EA_Anip|EA_piAn} },
+
+	{ MC_ALL, {0xf1c0, 0x5000}, {1}, {ofI3,ofEa}, "ADDQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
+	{ MC_ALL, {0xf1c0, 0x5040}, {2}, {ofI3,ofEa}, "ADDQ.W",{0,EA_Immed|EA_PCRel} },
+	{ MC_ALL, {0xf1c0, 0x5080}, {4}, {ofI3,ofEa}, "ADDQ.L",{0,EA_Immed|EA_PCRel} },
+	{ MC_ALL, {0xf0c0, 0x50C0}, {1}, {ofEa}, "Sci",{EA_Immed|EA_PCRel|EA_An}},
+	{ MC_ALL, {0xf0f8, 0x50C8}, {2}, {ofDn,ofDisp}, "DBcd"},
+	{ MC_020, {0xf0ff, 0x50fa}, {2}, {ofI}, "TRAPci.W"},
+	{ MC_020, {0xf0ff, 0x50fb}, {4}, {ofI}, "TRAPci.L"},
+	{ MC_020, {0xf0ff, 0x50fc}, {0}, {ofNone}, "TRAPci"},
+	{ MC_ALL, {0xf1c0, 0x5100}, {1}, {ofI3,ofEa}, "SUBQ.B",{0,EA_An|EA_Immed|EA_PCRel} },
+	{ MC_ALL, {0xf1c0, 0x5140}, {2}, {ofI3,ofEa}, "SUBQ.W",{0,EA_Immed|EA_PCRel} },
+	{ MC_ALL, {0xf1c0, 0x5180}, {4}, {ofI3,ofEa}, "SUBQ.L",{0,EA_Immed|EA_PCRel} },
+
+	{ MC_ALL, {0xf0ff, 0x6000}, {2}, {ofDisp}, "Bcb"},
+	{ MC_ALL, {0xf000, 0x6000}, {1}, {ofDisp}, "Bcb.S"},
+	{ MC_020, {0xf0ff, 0x60FF}, {4}, {ofDisp}, "Bcb.L"},
+
+	{ MC_ALL, {0xf100, 0x7000}, {0}, {ofIOpcode,ofDestDn}, "MOVEQ", {0xFF,0}},
+
+	{ MC_ALL, {0xf100, 0x8000}, {-1,6,2,0}, {ofEa,ofDestDn}, "OR.?", {EA_An,0}},
+	{ MC_ALL, {0xf100, 0x8100}, {-1,6,2,0}, {ofDestDn,ofEa}, "OR.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
+	{ MC_ALL, {0xf1f8, 0x8100}, {1}, {ofDn,ofDestDn}, "SBCD"},
+	{ MC_ALL, {0xf1f8, 0x8108}, {1}, {ofPiAn,ofDestPiAn}, "SBCD"},
+	{ MC_020&~MC_CPU32, {0xf1f8, 0x8140, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "PACK"},
+	{ MC_020&~MC_CPU32, {0xf1f8, 0x8148, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "PACK"},
+	{ MC_020&~MC_CPU32, {0xf1f8, 0x8180, 0x10000}, {0}, {ofDn,ofDestDn,ofExtIm}, "UNPK"},
+	{ MC_020&~MC_CPU32, {0xf1f8, 0x8188, 0x10000}, {0}, {ofPiAn,ofDestPiAn,ofExtIm}, "UNPK"},
+	{ MC_ALL, {0xf1c0, 0x80c0}, {2}, {ofEa,ofDestDn}, "DIVU.W", {EA_An,0}},
+	{ MC_ALL, {0xf1c0, 0x81c0}, {2}, {ofEa,ofDestDn}, "DIVS.W", {EA_An,0}},
+
+	{ MC_ALL, {0xf1c0, 0x9000}, {1}, {ofEa,ofDestDn}, "SUB.B", {EA_An,0}},
+	{ MC_ALL, {0xf1c0, 0x9040}, {2}, {ofEa,ofDestDn}, "SUB.W"},
+	{ MC_ALL, {0xf1c0, 0x9080}, {4}, {ofEa,ofDestDn}, "SUB.L"},
+	{ MC_ALL, {0xf1c0, 0x90c0}, {2}, {ofEa,ofDestAn}, "SUBA.W"},
+	{ MC_ALL, {0xf1c0, 0x91c0}, {4}, {ofEa,ofDestAn}, "SUBA.L"},
+	{ MC_ALL, {0xf100, 0x9100}, {-1,6,2,0}, {ofDestDn,ofEa}, "SUB.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
+	{ MC_ALL, {0xf138, 0x9100}, {-1,6,2,0}, {ofDn,ofDestDn}, "SUBX.?"},
+	{ MC_ALL, {0xf138, 0x9108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "SUBX.?"},
+
+	{ MC_ALL, {0xf000, 0xa000}, {0}, {ofLineA}, "LINEA"},
+
+	{ MC_ALL, {0xf1c0, 0xb000}, {1}, {ofEa,ofDestDn}, "CMP.B", {EA_An,0}},
+	{ MC_ALL, {0xf1c0, 0xb040}, {2}, {ofEa,ofDestDn}, "CMP.W"},
+	{ MC_ALL, {0xf1c0, 0xb080}, {4}, {ofEa,ofDestDn}, "CMP.L"},
+	{ MC_ALL, {0xf1c0, 0xb0c0}, {2}, {ofEa,ofDestAn}, "CMPA.W"},
+	{ MC_ALL, {0xf1c0, 0xb1c0}, {4}, {ofEa,ofDestAn}, "CMPA.L"},
+	{ MC_ALL, {0xf100, 0xb100}, {-1,6,2,0}, {ofDestDn,ofEa}, "EOR.?",{0,EA_An|EA_Immed|EA_PCRel} },
+	{ MC_ALL, {0xf138, 0xb108}, {-1,6,2,0}, {ofAnip,ofDestAnip}, "CMPM.?"},
+
+	{ MC_ALL, {0xf100, 0xc000}, {-1,6,2,0}, {ofEa,ofDestDn}, "AND.?", {EA_An,0}},
+	{ MC_ALL, {0xf100, 0xc100}, {-1,6,2,0}, {ofDestDn,ofEa}, "AND.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
+	{ MC_ALL, {0xf1f8, 0xc100}, {1}, {ofDn,ofDestDn}, "ABCD"},
+	{ MC_ALL, {0xf1f8, 0xc108}, {1}, {ofPiAn,ofDestPiAn}, "ABCD"},
+	{ MC_ALL, {0xf1f8, 0xc140}, {1}, {ofDestDn,ofDn}, "EXG"},
+	{ MC_ALL, {0xf1f8, 0xc148}, {1}, {ofDestAn,ofAn}, "EXG"},
+	{ MC_ALL, {0xf1f8, 0xc188}, {1}, {ofDestDn,ofAn}, "EXG"},
+	{ MC_ALL, {0xf1c0, 0xc0c0}, {2}, {ofEa,ofDestDn}, "MULU.W", {EA_An,0}},
+	{ MC_ALL, {0xf1c0, 0xc1c0}, {2}, {ofEa,ofDestDn}, "MULS.W", {EA_An,0}},
+
+	{ MC_ALL, {0xf1c0, 0xd000}, {1}, {ofEa,ofDestDn}, "ADD.B", {EA_An,0}},
+	{ MC_ALL, {0xf1c0, 0xd040}, {2}, {ofEa,ofDestDn}, "ADD.W"},
+	{ MC_ALL, {0xf1c0, 0xd080}, {4}, {ofEa,ofDestDn}, "ADD.L"},
+	{ MC_ALL, {0xf1c0, 0xd0c0}, {2}, {ofEa,ofDestAn}, "ADDA.W"},
+	{ MC_ALL, {0xf1c0, 0xd1c0}, {4}, {ofEa,ofDestAn}, "ADDA.L"},
+	{ MC_ALL, {0xf100, 0xd100}, {-1,6,2,0}, {ofDestDn,ofEa}, "ADD.?",{0,EA_Immed|EA_PCRel|EA_An|EA_Dn}},
+	{ MC_ALL, {0xf138, 0xd100}, {-1,6,2,0}, {ofDn,ofDestDn}, "ADDX.?"},
+	{ MC_ALL, {0xf138, 0xd108}, {-1,6,2,0}, {ofPiAn,ofDestPiAn}, "ADDX.?"},
+
+	{ MC_ALL, {0xf138, 0xe000}, {-1,6,2,0}, {ofI3,ofDn}, "ASR.?"},
+	{ MC_ALL, {0xf138, 0xe008}, {-1,6,2,0}, {ofI3,ofDn}, "LSR.?"},
+	{ MC_ALL, {0xf138, 0xe010}, {-1,6,2,0}, {ofI3,ofDn}, "ROXR.?"},
+	{ MC_ALL, {0xf138, 0xe018}, {-1,6,2,0}, {ofI3,ofDn}, "ROR.?"},
+	{ MC_ALL, {0xf138, 0xe020}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASR.?"},
+	{ MC_ALL, {0xf138, 0xe028}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSR.?"},
+	{ MC_ALL, {0xf138, 0xe030}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXR.?"},
+	{ MC_ALL, {0xf138, 0xe038}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROR.?"},
+	{ MC_ALL, {0xf138, 0xe100}, {-1,6,2,0}, {ofI3,ofDn}, "ASL.?"},
+	{ MC_ALL, {0xf138, 0xe108}, {-1,6,2,0}, {ofI3,ofDn}, "LSL.?"},
+	{ MC_ALL, {0xf138, 0xe110}, {-1,6,2,0}, {ofI3,ofDn}, "ROXL.?"},
+	{ MC_ALL, {0xf138, 0xe118}, {-1,6,2,0}, {ofI3,ofDn}, "ROL.?"},
+	{ MC_ALL, {0xf138, 0xe120}, {-1,6,2,0}, {ofDestDn,ofDn}, "ASL.?"},
+	{ MC_ALL, {0xf138, 0xe128}, {-1,6,2,0}, {ofDestDn,ofDn}, "LSL.?"},
+	{ MC_ALL, {0xf138, 0xe130}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROXL.?"},
+	{ MC_ALL, {0xf138, 0xe138}, {-1,6,2,0}, {ofDestDn,ofDn}, "ROL.?"},
+	{ MC_ALL, {0xffc0, 0xe0c0}, {1}, {ofEa}, "ASR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
+	{ MC_ALL, {0xffc0, 0xe1c0}, {1}, {ofEa}, "ASL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
+	{ MC_ALL, {0xffc0, 0xe2c0}, {1}, {ofEa}, "LSR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
+	{ MC_ALL, {0xffc0, 0xe3c0}, {1}, {ofEa}, "LSL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
+	{ MC_ALL, {0xffc0, 0xe4c0}, {1}, {ofEa}, "ROXR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
+	{ MC_ALL, {0xffc0, 0xe5c0}, {1}, {ofEa}, "ROXL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
+	{ MC_ALL, {0xffc0, 0xe6c0}, {1}, {ofEa}, "ROR",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
+	{ MC_ALL, {0xffc0, 0xe7c0}, {1}, {ofEa}, "ROL",{EA_Dn|EA_An|EA_Immed|EA_PCRel} },
+	{ MC_020&~MC_CPU32, {0xffc0, 0xe8c0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFTST",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
+	{ MC_020&~MC_CPU32, {0xffc0, 0xe9c0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTU",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
+	{ MC_020&~MC_CPU32, {0xffc0, 0xeac0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCHG",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
+	{ MC_020&~MC_CPU32, {0xffc0, 0xebc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFEXTS",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
+	{ MC_020&~MC_CPU32, {0xffc0, 0xecc0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFCLR",{EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
+	{ MC_020&~MC_CPU32, {0xffc0, 0xedc0, 0x8000, 0x0000}, {1}, {ofBFEa,ofExtReg}, "BFFFO",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
+	{ MC_020&~MC_CPU32, {0xffc0, 0xeec0, 0xf000, 0x0000}, {1}, {ofBFEa}, "BFSET",{EA_An|EA_piAn|EA_Anip|EA_Immed}},
+	{ MC_020&~MC_CPU32, {0xffc0, 0xefc0, 0x8000, 0x0000}, {1}, {ofExtReg,ofBFEa}, "BFINS",{0,EA_An|EA_piAn|EA_Anip|EA_Immed|EA_PCRel} },
+
+
+	#define PMMU_COPROC_ID		0	// 0 is the standard PMMU
+
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2000}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2001}, {0}, {ofSpecReg,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2008}, {0}, {ofExtReg0,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2010}, {0}, {ofExtIm4,ofEa}, "PLOADW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2200}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2201}, {0}, {ofSpecReg,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2208}, {0}, {ofExtReg0,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff0, 0x2210}, {0}, {ofExtIm4,ofEa}, "PLOADR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+
+	{ MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0xa000}, {0}, {ofEa}, "PFLUSHR",{EA_Dn|EA_An} },
+
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0C00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT0} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0E00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x0F00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TT1} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4100}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4300}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_TC} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4800}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4900}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4A00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4B00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_SRP} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4C00}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4D00}, {0}, {ofEa,ofSpecReg}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4e00}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x4f00}, {0}, {ofSpecReg,ofEa}, "PMOVEFD",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_CRP} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6000}, {0}, {ofEa,ofSpecReg}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
+	{ MC_PMMU|MC68030, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x6200}, {0}, {ofSpecReg,ofEa}, "PMOVE",{EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel,REG_MMUSR} },
+
+	{ MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xffff, 0x2800}, {0}, {ofSpecReg,ofEa}, "PVALID",{REG_VAL,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xfff8, 0x2C00}, {0}, {ofExtRegA0,ofEa}, "PVALID",{0,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8000}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8001}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8008}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8010}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8200}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3ff, 0x8201}, {0}, {ofSpecReg,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f8, 0x8208}, {0}, {ofExtReg0,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe3f0, 0x8210}, {0}, {ofExtIm4,ofEa,ofExtIm10}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8100}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8101}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8108}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8110}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTW",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8300}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_SFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe31f, 0x8301}, {0}, {ofSpecReg,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe318, 0x8308}, {0}, {ofExtReg0,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+	{ MC_PMMU|MC68030|MC68040|MC68LC040, {0xffc0, 0xf000|(PMMU_COPROC_ID<<9), 0xe310, 0x8310}, {0}, {ofExtIm4,ofEa,ofExtIm10,ofExtRegA05}, "PTESTR",{REG_DFC,EA_Dn|EA_An|EA_Anip|EA_piAn|EA_Immed|EA_PCRel} },
+
+	{ MC_PMMU, {0xffc0, 0xf040|(PMMU_COPROC_ID<<9), 0xfff0, 0x8310}, {0}, {ofEa}, "PScp",{EA_An|EA_Immed|EA_PCRel} },
+	{ MC_PMMU, {0xfff8, 0xf048|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {2}, {ofDn,ofDisp}, "PDBcp"},
+	{ MC_PMMU, {0xffff, 0xf07A|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "PTRAPcp.W" },
+	{ MC_PMMU, {0xffff, 0xf07B|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "PTRAPcp.L" },
+	{ MC_PMMU, {0xffff, 0xf07C|(PMMU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "PTRAPcp" },
+	{ MC_PMMU, {0xfff0, 0xf080|(PMMU_COPROC_ID<<9)}, {2}, {ofDisp}, "PBcp.W"},
+	{ MC_PMMU, {0xfff0, 0xf0C0|(PMMU_COPROC_ID<<9)}, {4}, {ofDisp}, "PBcp.L"},
+	{ MC_PMMU, {0xffc0, 0xf100|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PSAVE",{EA_Dn|EA_An|EA_Anip|EA_Immed} },
+	{ MC_PMMU, {0xffc0, 0xf140|(PMMU_COPROC_ID<<9)}, {0}, {ofEa}, "PRESTORE",{EA_Dn|EA_An|EA_piAn|EA_Immed} },
+
+
+	#define MC040_COPROC_ID		3	// 3 is the code for some 68040/68060 opcodes
+
+	{ MC68040|MC68060, {0xfff8, 0xf000|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofDestAbsL}, "MOVE16"},
+	{ MC68040|MC68060, {0xfff8, 0xf008|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAnip}, "MOVE16"},
+	{ MC68040|MC68060, {0xfff8, 0xf010|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAni,ofDestAbsL}, "MOVE16"},
+	{ MC68040|MC68060, {0xfff8, 0xf018|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofDestAbsL,ofAni}, "MOVE16"},
+	{ MC68040|MC68060, {0xfff8, 0xf020|(MC040_COPROC_ID<<9), 0x8fff, 0x8000}, {0}, {ofAnip,ofExtAnip}, "MOVE16"},
+
+
+	#define CPU32_COPROC_ID		4	// 4 is the code for some CPU32 opcodes
+
+	{ MC68040|MC68060, {0xfff8, 0xf008|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_NONE} },
+	{ MC68040|MC68060, {0xfff8, 0xf048|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_DC} },
+	{ MC68040|MC68060, {0xfff8, 0xf088|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_IC} },
+	{ MC68040|MC68060, {0xfff8, 0xf0C8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVL",{REG_CACHES_ICDC} },
+
+	{ MC68040|MC68060, {0xfff8, 0xf010|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_NONE} },
+	{ MC68040|MC68060, {0xfff8, 0xf050|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_DC} },
+	{ MC68040|MC68060, {0xfff8, 0xf090|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_IC} },
+	{ MC68040|MC68060, {0xfff8, 0xf0D0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVP",{REG_CACHES_ICDC} },
+
+	{ MC68040|MC68060, {0xfff8, 0xf018|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_NONE} },
+	{ MC68040|MC68060, {0xfff8, 0xf058|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_DC} },
+	{ MC68040|MC68060, {0xfff8, 0xf098|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_IC} },
+	{ MC68040|MC68060, {0xfff8, 0xf0D8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CINVA",{REG_CACHES_ICDC} },
+
+	{ MC68040|MC68060, {0xfff8, 0xf028|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_NONE} },
+	{ MC68040|MC68060, {0xfff8, 0xf068|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_DC} },
+	{ MC68040|MC68060, {0xfff8, 0xf0A8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_IC} },
+	{ MC68040|MC68060, {0xfff8, 0xf0E8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHL",{REG_CACHES_ICDC} },
+
+	{ MC68040|MC68060, {0xfff8, 0xf030|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_NONE} },
+	{ MC68040|MC68060, {0xfff8, 0xf070|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_DC} },
+	{ MC68040|MC68060, {0xfff8, 0xf0B0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_IC} },
+	{ MC68040|MC68060, {0xfff8, 0xf0F0|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHP",{REG_CACHES_ICDC} },
+
+	{ MC68040|MC68060, {0xfff8, 0xf038|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_NONE} },
+	{ MC68040|MC68060, {0xfff8, 0xf078|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_DC} },
+	{ MC68040|MC68060, {0xfff8, 0xf0B8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_IC} },
+	{ MC68040|MC68060, {0xfff8, 0xf0F8|(CPU32_COPROC_ID<<9)}, {0}, {ofSpecReg,ofAn}, "CPUSHA",{REG_CACHES_ICDC} },
+
+	{ MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0100}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLU.?" },
+	{ MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0100}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLU.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
+	{ MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0500}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLUN.?" },
+	{ MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0500}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLUN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
+
+	{ MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f08, 0x0900}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLS.?" },
+	{ MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0900}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLS.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
+	{ MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f28, 0x0D00}, {-1,16+6,2,0}, {ofExt4Dn}, "TBLSN.?" },
+	{ MC_CPU32, {0xffc0, 0xf000|(CPU32_COPROC_ID<<9), 0x8f3f, 0x0D00}, {-1,16+6,2,0}, {ofExtReg,ofEa}, "TBLSN.?",{EA_An|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
+
+	{ MC_CPU32, {0xffff, 0xf000|(CPU32_COPROC_ID<<9), 0xffff, 0x01C0}, {2}, {ofI}, "LPSTOP" },
+
+
+	#define FPU_COPROC_ID		1	// 1 is the standard FPU, required to be 1 for the 68040 anyway
+
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0000}, {-1,16+10,3,1}, {ofFPU}, "FMOVE.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0001}, {-1,16+10,3,1}, {ofFPU}, "FINT.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0002}, {-1,16+10,3,1}, {ofFPU}, "FSINH.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0003}, {-1,16+10,3,1}, {ofFPU}, "FINTRZ.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0004}, {-1,16+10,3,1}, {ofFPU}, "FSQRT.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0006}, {-1,16+10,3,1}, {ofFPU}, "FLOGNP1.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0008}, {-1,16+10,3,1}, {ofFPU}, "FETOXM1.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0009}, {-1,16+10,3,1}, {ofFPU}, "FTANH.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000A}, {-1,16+10,3,1}, {ofFPU}, "FATAN.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000C}, {-1,16+10,3,1}, {ofFPU}, "FASIN.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000D}, {-1,16+10,3,1}, {ofFPU}, "FATANH.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000E}, {-1,16+10,3,1}, {ofFPU}, "FSIN.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x000F}, {-1,16+10,3,1}, {ofFPU}, "FTAN.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0010}, {-1,16+10,3,1}, {ofFPU}, "FETOX.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0011}, {-1,16+10,3,1}, {ofFPU}, "FTWOTOX.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0012}, {-1,16+10,3,1}, {ofFPU}, "FTENTOX.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0014}, {-1,16+10,3,1}, {ofFPU}, "FLOGN.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0015}, {-1,16+10,3,1}, {ofFPU}, "FLOG10.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0016}, {-1,16+10,3,1}, {ofFPU}, "FLOG2.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0018}, {-1,16+10,3,1}, {ofFPU}, "FABS.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0019}, {-1,16+10,3,1}, {ofFPU}, "FCOSH.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001A}, {-1,16+10,3,1}, {ofFPU}, "FNEG.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001C}, {-1,16+10,3,1}, {ofFPU}, "FACOS.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001D}, {-1,16+10,3,1}, {ofFPU}, "FCOS.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001E}, {-1,16+10,3,1}, {ofFPU}, "FGETEXP.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x001F}, {-1,16+10,3,1}, {ofFPU}, "FGETMAN.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0020}, {-1,16+10,3,1}, {ofFPU}, "FDIV.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0021}, {-1,16+10,3,1}, {ofFPU}, "FMOD.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0022}, {-1,16+10,3,1}, {ofFPU}, "FADD.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0023}, {-1,16+10,3,1}, {ofFPU}, "FMUL.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0024}, {-1,16+10,3,1}, {ofFPU}, "FSGLDIV.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0025}, {-1,16+10,3,1}, {ofFPU}, "FREM.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0026}, {-1,16+10,3,1}, {ofFPU}, "FSCALE.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0027}, {-1,16+10,3,1}, {ofFPU}, "FSGLMUL.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0028}, {-1,16+10,3,1}, {ofFPU}, "FSUB.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA078,0x0030}, {-1,16+10,3,1}, {ofFPU3Reg}, "FSINCOS.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0038}, {-1,16+10,3,1}, {ofFPU}, "FCMP.?" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x003A}, {-1,16+10,3,1}, {ofFPU}, "FTST.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0040}, {-1,16+10,3,1}, {ofFPU}, "FSMOVE.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0041}, {-1,16+10,3,1}, {ofFPU}, "FSSQRT.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0042}, {-1,16+10,3,1}, {ofFPU}, "FSADD.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0044}, {-1,16+10,3,1}, {ofFPU}, "FDMOVE.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0045}, {-1,16+10,3,1}, {ofFPU}, "FDSQRT.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0046}, {-1,16+10,3,1}, {ofFPU}, "FDADD.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0058}, {-1,16+10,3,1}, {ofFPU}, "FSABS.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005A}, {-1,16+10,3,1}, {ofFPU}, "FSNEG.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005C}, {-1,16+10,3,1}, {ofFPU}, "FDABS.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x005E}, {-1,16+10,3,1}, {ofFPU}, "FDNEG.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0060}, {-1,16+10,3,1}, {ofFPU}, "FSDIV.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0063}, {-1,16+10,3,1}, {ofFPU}, "FSMUL.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0064}, {-1,16+10,3,1}, {ofFPU}, "FDDIV.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0067}, {-1,16+10,3,1}, {ofFPU}, "FDMUL.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x0068}, {-1,16+10,3,1}, {ofFPU}, "FSSUB.?" },
+	{ MC68040,        {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xA07F,0x006C}, {-1,16+10,3,1}, {ofFPU}, "FDSUB.?" },
+	{ MC68040|MC_FPU, {0xffff, 0xf000|(FPU_COPROC_ID<<9),0xFC00,0x5C00}, {0}, {ofFMOVECR}, "FMOVECR" },
+
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE000,0x6000}, {-1,16+10,3,1}, {ofFPUMOVE}, "FMOVE.?" },
+
+	// these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8400}, {0}, {ofEa,ofSpecReg}, "FMOVE", {0,REG_FPU_FPIAR} },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x8800}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPSR} },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0x9000}, {0}, {ofEa,ofSpecReg}, "FMOVE", {EA_An,REG_FPU_FPCR} },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0x8000}, {0}, {ofEa,ofFPUSRRegList}, "FMOVEM", {EA_Dn|EA_An,0} },
+	// these 3 are special versions of MOVEM with just one register, they have to be before the FMOVEM version
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA400}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPIAR,EA_Immed|EA_PCRel} },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xA800}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPSR,EA_An|EA_Immed|EA_PCRel} },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFFFF,0xB000}, {0}, {ofSpecReg,ofEa}, "FMOVE", {REG_FPU_FPCR,EA_An|EA_Immed|EA_PCRel} },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xE3FF,0xA000}, {0}, {ofFPUSRRegList,ofEa}, "FMOVEM", {0,EA_Dn|EA_An|EA_Immed|EA_PCRel} },
+
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xC000}, {0}, {ofFPUReglist,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_Anip|EA_Immed} },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xC800}, {0}, {ofExtRegD04,ofEa}, "FMOVEM.X",{0,EA_Dn|EA_An|EA_piAn|EA_Immed} },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE00,0xE000}, {0}, {ofEa,ofFPUReglist}, "FMOVEM.X",{EA_Dn|EA_An|EA_piAn|EA_Immed,0} },
+	{ MC68040|MC_FPU, {0xffc0, 0xf000|(FPU_COPROC_ID<<9),0xFE8F,0xE800}, {0}, {ofEa,ofExtRegD04}, "FMOVEM.X",{EA_Dn|EA_An|EA_Anip|EA_Immed|EA_PCRel} },
+
+	{ MC68040|MC_FPU, {0xffc0, 0xf040|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {0}, {ofEa}, "FScf.B",{EA_An|EA_Immed|EA_PCRel} },
+	{ MC68040|MC_FPU, {0xfff8, 0xf048|(FPU_COPROC_ID<<9),0xFFC0,0x0000}, {2}, {ofDn,ofDisp}, "FDBcf" },
+	{ MC68040|MC_FPU, {0xffff, 0xf07A|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {2}, {ofExtIm32}, "FTRAPcf.W" },
+	{ MC68040|MC_FPU, {0xffff, 0xf07B|(FPU_COPROC_ID<<9), 0xfff0, 0x0000, 0x10000,0x0000}, {4}, {ofExtIm32}, "FTRAPcf.L" },
+	{ MC68040|MC_FPU, {0xffff, 0xf07C|(FPU_COPROC_ID<<9), 0xfff0, 0x0000}, {0}, {ofNone}, "FTRAPcf" },
+
+	// FNOP _has_ to be before FBcf.W, not worth to have a special case for that one
+	{ MC68040|MC_FPU, {0xffff, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {0}, {ofNone}, "FNOP" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf080|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {2}, {ofDisp}, "FBcF.W" },
+	{ MC68040|MC_FPU, {0xffc0, 0xf0c0|(FPU_COPROC_ID<<9),0xFFFF,0x0000}, {4}, {ofDisp}, "FBcF.L" },
+	{ MC68040|MC68060|MC_FPU, {0xffc0, 0xf100|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FSAVE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
+	{ MC68040|MC68060|MC_FPU, {0xffc0, 0xf140|(FPU_COPROC_ID<<9)}, {0}, {ofEa}, "FRESTORE", {EA_Dn|EA_An|EA_piAn|EA_Immed} },
+
+	{ 0 }
+};
+
+static int	Disass68k(long addr, char *labelBuffer, char *opcodeBuffer, char *operandBuffer, char *commentBuffer)
+{
+	long	baseAddr = addr;
+	int		val;
+	int		i;
+	int		count = 0;
+	char	addressLabel[256];
+	char	cmtBuffer[256];
+	Disass68kDataType	type;
+	int	index;
+	long	opcodeAddr;
+
+	labelBuffer[0] = 0;
+	opcodeBuffer[0] = 0;
+	operandBuffer[0] = 0;
+	commentBuffer[0] = 0;
+
+	type = Disass68kType(baseAddr, addressLabel, cmtBuffer, &count);
+	if(addressLabel[0])
+		sprintf(labelBuffer, "%s:", addressLabel);
+	sprintf(commentBuffer, "%s", cmtBuffer);
+	switch(type)
+	{
+	case dtByte:
+		if(count > 8)
+			count = 8;
+		strcpy(opcodeBuffer,"DC.B");
+		for (i = 0; i < count; ++i)
+		{
+			char	hbuf[16];
+			unsigned short	val;
+
+			if((i & 7) > 0)
+				strcat(operandBuffer, ",");
+			val = Disass68kGetWord(addr+(i & ~1));
+			if(i & 1)
+				val &= 0xFF;
+			else
+				val = val >> 8;
+			sprintf(hbuf,"$%2.2x", val);
+			strcat(operandBuffer, hbuf);
+		}
+		return count;
+
+	case dtWord:
+		if(count > 4)
+			count = 4;
+		strcpy(opcodeBuffer,"DC.W");
+		for (i = 0; i < count; ++i)
+		{
+			char	hbuf[16];
+			if((i & 3) > 0)
+				strcat(operandBuffer, ",");
+			sprintf(hbuf,"$%4.4x", Disass68kGetWord(addr+i*2));
+			strcat(operandBuffer, hbuf);
+		}
+		return count * 2;
+
+	case dtLong:
+		if(count > 2)
+			count = 2;
+		strcpy(opcodeBuffer,"DC.L");
+		for (i = 0; i < count; ++i)
+		{
+			char	hbuf[16];
+			if((i & 1) > 0)
+				strcat(operandBuffer, ",");
+			sprintf(hbuf,"$%8.8x", (Disass68kGetWord(addr+i*4) << 16) | Disass68kGetWord(addr+i*4+2));
+			strcat(operandBuffer, hbuf);
+		}
+		return count * 4;
+
+	case dtStringArray:
+	{
+		char	*sp;
+		strcpy(opcodeBuffer,"DC.B");
+		strcat(operandBuffer, "'");
+		sp = operandBuffer + strlen(operandBuffer);
+		for (i = 0; i < count; ++i)
+		{
+			unsigned short	val = Disass68kGetWord(addr+(i & ~1));
+			if(i & 1)
+				val &= 0xFF;
+			else
+				val = val >> 8;
+			if(val == 0)
+				break;
+			switch(val)
+			{
+			case 9: *sp++ = '\\'; *sp++ = 't'; break;
+			case 10: *sp++ = '\\'; *sp++ = 'n'; break;
+			case 13: *sp++ = '\\'; *sp++ = 'r'; break;
+			default:
+				if(val >= 0x20 && val <= 0x7E)
+					*sp++ = val;
+			}
+		}
+		*sp = 0;
+		strcat(sp, "'");
+		return count;
+	}
+
+	case dtASCString:
+	{
+		int	count = 1;
+		unsigned short	val = Disass68kGetWord(addr+0);
+		strcpy(opcodeBuffer,"DC.B");
+		if((val >> 8) == 0)
+		{
+			strcat(operandBuffer, "0");
+		} else {
+			char *sp;
+			strcat(operandBuffer, "'");
+			sp = operandBuffer + strlen(operandBuffer);
+			for(i=0; ; ++i)
+			{
+				unsigned short	val = Disass68kGetWord(addr+(i & ~1));
+				if(i & 1)
+					val &= 0xFF;
+				else
+					val = val >> 8;
+				if(val == 0)
+					break;
+				switch(val)
+				{
+				case 9: *sp++ = '\\'; *sp++ = 't'; break;
+				case 10: *sp++ = '\\'; *sp++ = 'n'; break;
+				case 13: *sp++ = '\\'; *sp++ = 'r'; break;
+				default:
+					if(val >= 0x20 && val <= 0x7E)
+						*sp++ = val;
+				}
+				++count;
+			}
+			*sp = 0;
+			strcat(sp, "',0");
+		}
+		return (count + 1) & ~1;
+	}
+
+	case dtPointer:
+	case dtFunctionPointer:
+	{
+		const char	*sp;
+		val = (Disass68kGetWord(addr) << 16) | Disass68kGetWord(addr+2);
+		sp = Disass68kSymbolName(val, 2);
+		strcpy(opcodeBuffer,"DC.L");
+		if(sp)
+			sprintf(operandBuffer,"%s", sp);
+		else
+			sprintf(operandBuffer,"$%8.8x", val);
+		return 4;
+	}
+
+	default:	break;
+	}
+
+	index = 0;
+	opcodeAddr = addr;
+more:
+	addr = opcodeAddr;
+
+	opcodeBuffer[0] = 0;
+	operandBuffer[0] = 0;
+
+	commentBuffer[0] = 0;
+	if(cmtBuffer[0])
+		sprintf(commentBuffer, "%s ", cmtBuffer);
+
+	while(1)
+	{
+		unsigned short	opcode[5];
+		unsigned int	i;
+		OpcodeTableStruct	*ots = &OpcodeTable[index++];
+		int	size;
+		char	sizeChar = 0;
+		char	*dbuf;
+		int	ea;
+		unsigned int	maxop;
+
+		if(ots->opcodeName == NULL)
+			break;
+		if((ots->cpuMask & optionCPUTypeMask) == 0)	// CPU doesn't match?
+			continue;
+
+		// search for the opcode plus up to 2 extension words
+		for(i=0; i<5; ++i)
+		{
+			if(!ots->opcodeMask[i*2])
+			{
+				opcode[i] = 0;
+				break;
+			}
+			opcode[i] = Disass68kGetWord(addr);
+			if(((ots->opcodeMask[i*2] & 0xFFFF) & opcode[i]) != ots->opcodeMask[i*2+1])
+				goto more;
+			addr += 2;
+		}
+
+		// find out the size of the opcode operand
+		size = ots->operationSize[0];
+		if(size < 0)	// custom size?
+		{
+			int	opcodeOffset = ots->operationSize[1] >> 4;
+			int	bitShiftOffset = ots->operationSize[1] & 0x0F;
+			int	sizeBitMask = (opcode[opcodeOffset] >> bitShiftOffset) & ((1 << ots->operationSize[2]) - 1);
+			switch(ots->operationSize[3])
+			{
+			case 0:	// 2 Bit Size
+					switch(sizeBitMask)
+					{
+					case 0:	size = 1; sizeChar = 'B'; break;
+					case 1:	size = 2; sizeChar = 'W'; break;
+					case 2:	size = 4; sizeChar = 'L'; break;
+					case 3: goto more;	// illegal size mask
+					}
+					break;
+			case 1:	// 3 Bit FPU Size
+					if((opcode[1] & 0x4000) == 0x0000)	// Register => Register?
+						sizeBitMask = 2;		// => 'X' Format
+					switch(sizeBitMask)
+					{
+					case 0:	size = 4; sizeChar = 'L'; break;
+					case 1:	size = 4; sizeChar = 'S'; break;
+					case 2:	size = 12; sizeChar = 'X'; break;
+					case 7: if((opcode[1] & 0xE000) != 0x6000)	// MOVE.P ,FPn{Dn-Factor}
+								goto more;	// illegal size mask
+					case 3:	size = 12; sizeChar = 'P'; break;
+					case 4:	size = 2; sizeChar = 'W'; break;
+					case 5:	size = 8; sizeChar = 'D'; break;
+					case 6:	size = 1; sizeChar = 'B'; break;
+					}
+					break;
+			}
+		}
+
+		// copy the opcode plus a necessary TAB for the operand
+		dbuf = opcodeBuffer;
+		for(i=0; ots->opcodeName[i]; ++i)
+		{
+			char	c = ots->opcodeName[i];
+			if(c == 'c')	// condition code
+			{
+				static const char	*pmmuCond[16] = { "BS", "BC", "LS", "LC",  "SS", "SC", "AS", "AC",  "WS", "WC", "IS", "IC",  "GS", "GC", "CS", "CC" };
+				static const char	*braCond[16]  = { "RA", "SR", "HI", "LS",  "CC", "CS", "NE", "EQ",  "VC", "VS", "PL", "MI",  "GE", "LT", "GT", "LE" };
+				static const char	*sccCond[16]  = {  "T",  "F", "HI", "LS",  "CC", "CS", "NE", "EQ",  "VC", "VS", "PL", "MI",  "GE", "LT", "GT", "LE" };
+				static const char	*dbCond[16]   = {  "T", "RA", "HI", "LS",  "CC", "CS", "NE", "EQ",  "VC", "VS", "PL", "MI",  "GE", "LT", "GT", "LE" };
+				static const char	*fpuCond[64]  = { "F", "EQ", "OGT", "OGE", "OLT", "OLE", "OGL", "OR", "UN", "UEQ", "UGT", "UGE", "ULT", "ULE", "NE", "T", "SF", "SEQ", "GT", "GE", "LT", "LE", "GL", "GLE", "NGLE", "NGL", "NLE", "NLT", "NGE", "NGT", "SNE", "ST" };
+				char	buf[8];
+
+				const char	*sp = NULL;
+				switch(ots->opcodeName[++i])
+				{
+				case 'p':	// PMMU conditions
+					sp = pmmuCond[opcode[1] & 0xF];
+					break;
+				case 'b':	// BRA conditions
+					sp = braCond[(opcode[0] >> 8) & 0xF];
+					break;
+				case 'i':	// Scc,TRAPcc conditions
+					sp = sccCond[(opcode[0] >> 8) & 0xF];
+					break;
+				case 'd':	// DBcc conditions
+					sp = dbCond[(opcode[0] >> 8) & 0xF];
+					break;
+				case 'F':	// FPU conditions (first word)
+					sp = fpuCond[opcode[0] & 0x3F];
+					break;
+				case 'f':	// FPU conditions (second word)
+					sp = fpuCond[opcode[1] & 0x3F];
+					break;
+				}
+				if(sp)
+				{
+					if(options & doptOpcodesSmall)
+					{
+						char	*bp;
+						strcpy(buf, sp);
+						sp = buf;
+						for (bp = buf; *bp; ++bp)
+							*bp = tolower((unsigned char)*bp);
+					}
+					strcpy(dbuf, sp);
+					dbuf += strlen(sp);
+					continue;
+				}
+				goto more;
+			}
+			if(c == '?')	// size mask
+				c = sizeChar;
+			if(options & doptOpcodesSmall)
+				c = tolower((unsigned char)c);
+			*dbuf++ = c;
+		}
+		*dbuf = 0;
+
+		// Parse the EAs for all operands
+		ea = opcode[0] & 0x3F;
+		dbuf = operandBuffer;
+
+		maxop=(sizeof(ots->op)/sizeof(ots->op[0]));
+		for(i=0; iop[i])
+			{
+			case ofNone:		// nothing
+					break;
+
+			case ofEa:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
+					break;
+
+			case ofDn:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
+					break;
+			case ofAn:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
+					break;
+			case ofAni:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x10, size, EA_Ani, 0, ots->disassFlag);
+					break;
+			case ofAnip:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
+					break;
+			case ofPiAn:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
+					break;
+			case ofD16An:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (ea & 7) | 0x28, size, EA_dAn, 0, ots->disassFlag);
+					break;
+
+			case ofI:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x3C, size, EA_Immed, 0, ots->disassFlag);
+					break;
+
+			case ofDestDn:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x00, size, EA_Dn, 0, ots->disassFlag);
+					break;
+			case ofDestAn:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x08, size, EA_An, 0, ots->disassFlag);
+					break;
+			case ofDestAnip:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
+					break;
+			case ofDestPiAn:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | 0x20, size, EA_piAn, 0, ots->disassFlag);
+					break;
+			case ofDestEa6:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[0] >> 9) & 7) | (((opcode[0] >> 6) & 0x7) << 3), size, EA_Dest-EA_An, 0, ots->disassFlag);
+					break;
+			case ofDestAbsL:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x39, size, EA_Abs, 0, ots->disassFlag);
+					break;
+
+			case ofIOpcode:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[0] & ots->parameter[i], ots->disassFlag);
+					break;
+			case ofI3:
+					val = ((opcode[0] >> 9) & 7);
+					if(!val) val = 8;
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, val, ots->disassFlag);
+					break;
+			case ofExtIm:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1], ots->disassFlag);
+					break;
+			case ofExtIm32:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, size, EA_ImmedParameter, opcode[2], ots->disassFlag);
+					break;
+			case ofExtIm4:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, opcode[1] & 0x0F, ots->disassFlag);
+					break;
+			case ofExtIm10:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, (opcode[1] >> 10) & 0x07, ots->disassFlag);
+					break;
+			case ofSpecReg:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, ots->parameter[i], ots->disassFlag);
+					break;
+			case ofSpecExtReg:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0101, size, EA_SpecialRegister, opcode[1] & 0xFFF, ots->disassFlag);
+					break;
+			case ofExtReg0:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
+					break;
+			case ofExtRegA0:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
+					break;
+			case ofExtRegD04:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 4) & 0x07) | 0x00, size, EA_Dn, 0, ots->disassFlag);
+					break;
+			case ofExtRegA05:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 5) & 0x07) | 0x08, size, EA_An, 0, ots->disassFlag);
+					break;
+			case ofExtReg:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
+					break;
+			case ofExtAnip:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 7) | 0x18, size, EA_Anip, 0, ots->disassFlag);
+					break;
+
+			case ofDisp:
+					// branch treats the displacement 0x00 and 0xFF as an indicator how many words follow
+					// This test will decline a displacement with the wrong word offset
+					if((opcode[0] & 0xF000) == 0x6000)
+					{
+						val = opcode[0] & 0xFF;
+						if(val == 0x00 && size != 2) goto more;
+						if(val == 0xFF && size != 4) goto more;
+					}
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0102, size, EA_PCDisplacement, opcode[0] & 0xFF, ots->disassFlag);
+					break;
+
+			case ofRegList:
+					val = opcode[1];
+					if((ea & 0x38) == 0x20)				// -(An) has a flipped bitmask
+						val = Disass68kFlipBits(val);
+					dbuf = Disass68kReglist(dbuf, val);
+					break;
+
+			case ofFPU:
+					{	// default FPU opcode modes
+					int	src = (opcode[1] >> 10) & 7;
+					int	dest = (opcode[1] >> 7) & 7;
+					char	regFP1 = options & doptRegisterSmall ? 'f' : 'F';
+					char	regFP2 = options & doptRegisterSmall ? 'p' : 'P';
+					if(opcode[1] & 0x4000)
+					{
+						// ,FPn
+						int	mask = EA_All - EA_An;
+						if(src != 0 && src != 4 && src != 6)	// only .B,.W and .L allow Dn as a source
+							mask -= EA_Dn;
+						dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
+						if(!dbuf) goto more;
+						*dbuf++ = ',';
+						*dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
+						*dbuf = 0;
+					} else {
+						// FPn,FPn or FPn
+
+						//  has to be 0
+						if((opcode[0] & 0x3F) != 0) goto more;
+
+						*dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
+						if(src != dest)
+						{
+							*dbuf++ = ',';
+							*dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
+						}
+						*dbuf = 0;
+					}
+					}
+					break;
+			case ofFPUMOVE:
+					{	// MOVE ,FPn{k-Factor}
+					int	src = (opcode[1] >> 10) & 7;
+					// ,FPn
+					int	mask = EA_All - EA_An;
+					char	regFP1 = options & doptRegisterSmall ? 'f' : 'F';
+					char	regFP2 = options & doptRegisterSmall ? 'p' : 'P';
+					if(src != 0 && src != 4 && src != 6)	// only .B,.W and .L allow Dn as a source
+						mask -= EA_Dn;
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
+					if(!dbuf) goto more;
+					*dbuf++ = ',';
+					*dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+((opcode[1] >> 7) & 7);
+					if(src == 3)
+					{
+						int	kFactor = opcode[1] & 0x7F;
+						if(kFactor & 0x40)
+							kFactor |= 0x80;
+						*dbuf++ = '{';
+						sprintf(dbuf, "%d", (signed char)kFactor);
+						dbuf += strlen(dbuf);
+						*dbuf++ = '}';
+					} else if(src == 7)
+					{
+						if((opcode[1] & 0x0F) != 0) goto more;
+						*dbuf++ = '{';
+						*dbuf++ = options & doptRegisterSmall ? 'd' : 'D';
+						*dbuf++ = '0' + ((opcode[1] >> 4) & 7);
+						*dbuf++ = '}';
+					} else {
+						if((opcode[1] & 0x7F) != 0) goto more;
+					}
+					*dbuf = 0;
+					}
+					break;
+			case ofFMOVECR:
+					{	// MOVECR #const,FPn
+					char	regFP1 = options & doptRegisterSmall ? 'f' : 'F';
+					char	regFP2 = options & doptRegisterSmall ? 'p' : 'P';
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 1, EA_ImmedParameter, opcode[1] & 0x7F, ots->disassFlag);
+					if(!dbuf) goto more;
+					reg = (opcode[1] >> 7) & 7;
+					*dbuf++ = ',';
+					*dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+reg;
+					*dbuf = 0;
+					switch(opcode[1] & 0x7F)	// document the well-known constants
+					{
+					case 0x00:	strcat(commentBuffer, "PI"); break;
+					case 0x0B:	strcat(commentBuffer, "Log10(2)"); break;
+					case 0x0C:	strcat(commentBuffer, "e"); break;
+					case 0x0D:	strcat(commentBuffer, "Log2(e)"); break;
+					case 0x0E:	strcat(commentBuffer, "Log10(e)"); break;
+					case 0x0F:	strcat(commentBuffer, "0.0"); break;
+					case 0x30:	strcat(commentBuffer, "1n(2)"); break;
+					case 0x31:	strcat(commentBuffer, "1n(10)"); break;
+					case 0x32:	strcat(commentBuffer, "100"); break;
+					case 0x33:	strcat(commentBuffer, "10^1"); break;
+					case 0x34:	strcat(commentBuffer, "10^2"); break;
+					case 0x35:	strcat(commentBuffer, "10^4"); break;
+					case 0x36:	strcat(commentBuffer, "10^8"); break;
+					case 0x37:	strcat(commentBuffer, "10^16"); break;
+					case 0x38:	strcat(commentBuffer, "10^32"); break;
+					case 0x39:	strcat(commentBuffer, "10^64"); break;
+					case 0x3A:	strcat(commentBuffer, "10^128"); break;
+					case 0x3B:	strcat(commentBuffer, "10^256"); break;
+					case 0x3C:	strcat(commentBuffer, "10^512"); break;
+					case 0x3D:	strcat(commentBuffer, "10^1024"); break;
+					case 0x3E:	strcat(commentBuffer, "10^2048"); break;
+					case 0x3F:	strcat(commentBuffer, "10^4096"); break;
+					}
+					}
+					break;
+			case ofFPUSRRegList:
+					{
+					int	hasReg = 0;
+					*dbuf = 0;
+					if(opcode[1] & 0x0400)
+					{
+						strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPIAR));
+						hasReg = 1;
+					}
+					if(opcode[1] & 0x0800)
+					{
+						if(hasReg) strcat(dbuf, "/");
+						strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPSR));
+						hasReg = 1;
+					}
+					if(opcode[1] & 0x1000)
+					{
+						if(hasReg) strcat(dbuf, "/");
+						strcat(dbuf, Disass68kSpecialRegister(REG_FPU_FPCR));
+						hasReg = 1;
+					}
+					if(!hasReg)
+						strcat(dbuf, "0");
+					dbuf += strlen(dbuf);
+					}
+					break;
+			case ofFPUReglist:	// FMOVEM
+					{
+					int	mask = opcode[1] & 0xFF;
+					if(opcode[1] & 0x0100)
+						mask = Disass68kFlipBits(mask) >> 8;
+					dbuf = Disass68kFPUReglist(dbuf, mask);
+					}
+					break;
+			case ofFPU3Reg:
+					{	// FSINCOS
+					int	src = (opcode[1] >> 10) & 7;
+					int	dest = (opcode[1] >> 7) & 7;
+					char	regFP1 = options & doptRegisterSmall ? 'f' : 'F';
+					char	regFP2 = options & doptRegisterSmall ? 'p' : 'P';
+					if(opcode[1] & 0x4000)
+					{
+						// ,FPn
+						int	mask = EA_All - EA_An;
+						if(src != 0 && src != 4 && src != 6)	// only .B,.W and .L allow Dn as a source
+							mask -= EA_Dn;
+						dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, mask, 0, 0);
+						if(!dbuf) goto more;
+						*dbuf++ = ',';
+						*dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
+						*dbuf++ = ',';
+						*dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
+						*dbuf = 0;
+					} else {
+						// FPn,FPn or FPn
+
+						//  has to be 0
+						if((opcode[0] & 0x3F) != 0) goto more;
+
+						*dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+src;
+						*dbuf++ = ',';
+						*dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+(opcode[1] & 7);
+						*dbuf++ = ',';
+						*dbuf++ = regFP1; *dbuf++ = regFP2; *dbuf++ = '0'+dest;
+						*dbuf = 0;
+					}
+					}
+					break;
+
+			case ofCAS:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
+					if(!dbuf) goto more;
+					*dbuf++ = ',';
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
+					break;
+			case ofCAS2:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
+					if(!dbuf) goto more;
+					*dbuf++ = ':';
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[2] & 0x07), size, EA_Dn, 0, ots->disassFlag);
+					if(!dbuf) goto more;
+					*dbuf++ = ',';
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
+					if(!dbuf) goto more;
+					*dbuf++ = ':';
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 6) & 0x07), size, EA_Dn, 0, ots->disassFlag);
+					if(!dbuf) goto more;
+					*dbuf++ = ',';
+					*dbuf++ = '(';
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
+					if(!dbuf) goto more;
+					*dbuf++ = ')';
+					*dbuf++ = ':';
+					*dbuf++ = '(';
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[2] >> 12) & 0x0F), size, EA_Dn|EA_An, 0, ots->disassFlag);
+					if(!dbuf) goto more;
+					*dbuf++ = ')';
+					*dbuf = 0;
+					break;
+			case ofExt4Dn:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[0] & 0x07), size, EA_Dn, 0, ots->disassFlag);
+					if(!dbuf) goto more;
+					*dbuf++ = ':';
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, (opcode[1] & 0x07), size, EA_Dn, 0, ots->disassFlag);
+					if(!dbuf) goto more;
+					*dbuf++ = ',';
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ((opcode[1] >> 12) & 0x07), size, EA_Dn, 0, ots->disassFlag);
+					if(!dbuf) goto more;
+					*dbuf = 0;
+					break;
+			case ofBFEa:
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, ea, size, EA_All & ~(ots->parameter[i]), 0, ots->disassFlag);
+					if(!dbuf) goto more;
+					*dbuf++ = '{';
+					val = (opcode[1] >> 6) & 0x1F;
+					if(opcode[1] & 0x0800)
+					{
+						if(val & 0x18) goto more;
+						dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
+					} else {
+						dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
+					}
+					*dbuf++ = ':';
+					val = opcode[1] & 0x1F;
+					if(opcode[1] & 0x0020)
+					{
+						if(val & 0x18) goto more;
+						dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, val & 0x07, 1, EA_Dn, val, ots->disassFlag);
+					} else {
+						if(val == 0) val = 32;
+						dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0103, 1, EA_ValueParameter, val, ots->disassFlag);
+					}
+					*dbuf++ = '}';
+					*dbuf = 0;
+					break;
+			case ofLineA:
+					{
+					int	lineAVal = opcode[0] & 0xFFF;
+					const char	*lineAStr[16] = { "Line-A Initialization",
+												  "Put pixel",
+												  "Get pixel",
+												  "Arbitrary line",
+												  "Horizontal line",
+												  "Filled rectangle",
+												  "Filled polygon",
+												  "Bit block transfer",
+												  "Text block transfer",
+												  "Show mouse",
+												  "Hide mouse",
+												  "Transform mouse",
+												  "Undraw sprite",
+												  "Draw sprite",
+												  "Copy raster form",
+												  "Seedfill"
+												  };
+					dbuf = Disass68kEA(dbuf, commentBuffer, &addr, opcodeAddr, 0x0100, 2, EA_ImmedParameter, lineAVal, ots->disassFlag);
+					if(lineAVal < 16)
+						strcat(commentBuffer, lineAStr[lineAVal]);
+					}
+					break;
+
+			default:
+					goto more;
+			}
+			if(!dbuf) goto more;
+
+			// does another operand follow => add separator
+			if ( (i+1op[i+1] != ofNone) )
+				*dbuf++ = ',';
+		}
+		return addr-baseAddr;
+	}
+
+	// unknown opcode
+	strcpy(opcodeBuffer, "DC.W");
+	sprintf(operandBuffer,"$%4.4x", Disass68kGetWord(addr));
+	return 2;
+}
+
+static void		Disass68kComposeStr(char *dbuf, const char *str, int position, int maxPos)
+{
+	int		i;
+	int		len = strlen(dbuf);
+	while(len < position) {
+		dbuf[len++] = ' ';		/* Will give harmless warning from GCC */
+	}
+	for(i=0; str[i] && (!maxPos || len+i 0) {
+		const int	addrWidth = 8;		// 6 on an ST (24 bit addressing), 8 on a TT (32 bit addressing)
+		char	lineBuffer[1024];
+
+		char	addressBuffer[32];
+		char	hexdumpBuffer[256];
+		char	labelBuffer[256];
+		char	opcodeBuffer[64];
+		char	operandBuffer[256];
+		char	commentBuffer[256];
+		int	plen, len, j;
+
+		len = Disass68k(addr, labelBuffer, opcodeBuffer, operandBuffer, commentBuffer);
+		if(!len) break;
+
+		sprintf(addressBuffer, "$%*.*x :", addrWidth,addrWidth, addr);
+
+		hexdumpBuffer[0] = 0;
+		plen = len;
+		if(plen > 80 && (!strncmp(opcodeBuffer, "DC.", 3) || !strncmp(opcodeBuffer, "dc.", 3)))
+			plen = ((optionPosLabel - optionPosHexdump) / 5) * 2;
+
+		for(j=0; j 0)
+				strcat(hexdumpBuffer, " ");
+			if(j + 2 > plen)
+			{
+				sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%2.2x", Disass68kGetWord(addr+j) >> 8);
+			} else {
+				sprintf(hexdumpBuffer+strlen(hexdumpBuffer), "%4.4x", Disass68kGetWord(addr+j));
+			}
+		}
+
+		lineBuffer[0] = 0;
+		if(optionPosAddress >= 0)
+			Disass68kComposeStr(lineBuffer, addressBuffer, optionPosAddress, 0);
+		if(optionPosHexdump >= 0)
+			Disass68kComposeStr(lineBuffer, hexdumpBuffer, optionPosHexdump, optionPosLabel);
+		if(optionPosLabel >= 0)
+			Disass68kComposeStr(lineBuffer, labelBuffer, optionPosLabel, 0);
+		if(optionPosOpcode >= 0)
+			Disass68kComposeStr(lineBuffer, opcodeBuffer, optionPosOpcode, 0);
+		if(optionPosOperand >= 0)
+		{
+			size_t	l = strlen(lineBuffer);
+			if(lineBuffer[l-1] != ' ')		// force at least one space between opcode and operand
+			{
+				lineBuffer[l++] = ' ';
+				lineBuffer[l] = 0;
+			}
+			Disass68kComposeStr(lineBuffer, operandBuffer, optionPosOperand, 0);
+		}
+		if (optionPosComment >= 0)
+		{
+			float percentage;
+			Uint32 count, cycles, i_misses, d_hits;
+			if (Profile_CpuAddressData(addr, &percentage, &count, &cycles, &i_misses, &d_hits))
+			{
+				sprintf(commentBuffer, "%5.2f%% (%u, %u, %u, %u)", percentage, count, cycles, i_misses, d_hits);
+				Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+1, 0);
+			}
+			/* show comments only if profile data is missing */
+			else if (commentBuffer[0])
+			{
+				Disass68kComposeStr(lineBuffer, " ;", optionPosComment, 0);
+				Disass68kComposeStr(lineBuffer, commentBuffer, optionPosComment+3, 0);
+			}
+		}
+		addr += len;
+		if (f)
+			fprintf(f, "%s\n", lineBuffer);
+//		if(strstr(opcodeBuffer, "RTS") || strstr(opcodeBuffer, "RTE") || strstr(opcodeBuffer, "JMP")
+//		|| strstr(opcodeBuffer, "rts") || strstr(opcodeBuffer, "rte") || strstr(opcodeBuffer, "jmp"))
+//			fprintf(f, "\n");
+    }
+    if (nextpc)
+		*nextpc = addr;
+}
+
+
+/**
+ * Calculate next PC address from given one, without output
+ * @return	next PC address
+ */
+Uint32 Disasm_GetNextPC(Uint32 pc)
+{
+	uaecptr nextpc;
+	Disass68k_loop (NULL, pc, &nextpc, 1);
+	return nextpc;
+}
+
+/**
+ * Call disassembly using the selected disassembly method,
+ * either internal UAE one, or the stand alone disassembler above,
+ * whichever is selected in Hatari configuration
+ */
+void Disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
+{
+	if (ConfigureParams.Debugger.bDisasmUAE)
+#ifdef WINUAE_FOR_HATARI
+		m68k_disasm_file (f, addr, nextpc, cnt);
+#else
+		m68k_disasm (f, addr, nextpc, cnt);
+#endif
+	else
+		Disass68k_loop (f, addr, nextpc, cnt);
+}
+
+static void Disasm_CheckOptionEngine(void)
+{
+	if (ConfigureParams.Debugger.bDisasmUAE)
+		fputs("WARNING: disassembly options are supported only for '--disasm ext'!\n", stderr);
+}
+
+/**
+ * query disassembly output column positions.
+ */
+void Disasm_GetColumns(int *pos)
+{
+	pos[DISASM_COLUMN_ADDRESS] = optionPosAddress;
+	pos[DISASM_COLUMN_HEXDUMP] = optionPosHexdump;
+	pos[DISASM_COLUMN_LABEL]   = optionPosLabel;
+	pos[DISASM_COLUMN_OPCODE]  = optionPosOpcode;
+	pos[DISASM_COLUMN_OPERAND] = optionPosOperand;
+	pos[DISASM_COLUMN_COMMENT] = optionPosComment;
+}
+
+/**
+ * set disassembly output column positions.
+ */
+void Disasm_SetColumns(int *pos)
+{
+	Disasm_CheckOptionEngine();
+	optionPosAddress = pos[DISASM_COLUMN_ADDRESS];
+	optionPosHexdump = pos[DISASM_COLUMN_HEXDUMP];
+	optionPosLabel   = pos[DISASM_COLUMN_LABEL];
+	optionPosOpcode  = pos[DISASM_COLUMN_OPCODE];
+	optionPosOperand = pos[DISASM_COLUMN_OPERAND];
+	optionPosComment = pos[DISASM_COLUMN_COMMENT];
+}
+
+/**
+ * function to disable given disassembly output 'column'.
+ * input is current column positions in 'oldcols' array and
+ * output is new column positions/values in 'newcols' array.
+ * It's safe to use same array for both.
+ */
+void Disasm_DisableColumn(int column, int *oldcols, int *newcols)
+{
+	int i, diff = 0;
+
+	assert(column >= 0 && column < DISASM_COLUMNS);
+	if (column+1 < DISASM_COLUMNS)
+		diff = oldcols[column+1] - oldcols[column];
+
+	for (i = 0; i < DISASM_COLUMNS; i++)
+	{
+		if (i && oldcols[i-1] > oldcols[i])
+		{
+			printf("WARNING: disassembly columns aren't in the expected order!\n");
+			return;
+		}
+		if (i < column)
+			newcols[i] = oldcols[i];
+		else if (i > column)
+			newcols[i] = oldcols[i] - diff;
+		else
+			newcols[column] = DISASM_COLUMN_DISABLE;
+	}
+}
+
+/**
+ * Get current disassembly output option flags
+ * @return	current output flags
+ */
+int Disasm_GetOptions(void)
+{
+	return options;
+}
+
+/**
+ * Set CPU and FPU mask used for disassembly (when changed from the UI or the options)
+ */
+void Disasm_SetCPUType ( int CPU , int FPU )
+{
+	optionCPUTypeMask = 0;
+
+	if ( ( FPU == 68881 ) || ( FPU == 68882 ) )
+		optionCPUTypeMask |= MC_FPU;
+
+	switch ( CPU )
+	{
+		case 0 :	optionCPUTypeMask |= MC68000 ; break;
+		case 1 :	optionCPUTypeMask |= MC68010 ; break;
+		case 2 :	optionCPUTypeMask |= MC68020 ; break;
+		case 3 :	optionCPUTypeMask |= MC68030 ; break;
+		case 4 :	optionCPUTypeMask |= MC68040 ; break;
+		default :	optionCPUTypeMask |= MC68000 ; break;
+	}	
+}
+
+/**
+ * Parse disasm command line option argument
+ * @return	error string (""=silent 'error') or NULL for success.
+ */
+const char *Disasm_ParseOption(const char *arg)
+{
+	if (strcasecmp(arg, "help") == 0)
+	{
+		const struct {
+			int flag;
+			const char *desc;
+		} option[] = {
+			{ doptNoBrackets, "no brackets around absolute addressing" },
+			{ doptOpcodesSmall, "opcodes in small letters" },
+			{ doptRegisterSmall, "register names in small letters" },
+			{ doptStackSP, "stack pointer as 'SP', not 'A7'" },
+			{ 0, NULL }
+		};
+		int i;
+		fputs("Disassembly settings:\n"
+		      "\tuae - use CPU core internal disassembler which has better\n"
+		      "\t      instruction support\n"
+		      "\text - use external disassembler which has nicer output\n"
+		      "\t      and supports options below\n"
+		      "\t - disassembly output option flags\n"
+		      "Flag values:\n", stderr);
+		for (i = 0; option[i].desc; i++) {
+			assert(option[i].flag == (1 << i));
+			fprintf(stderr, "\t%d: %s\n", option[i].flag, option[i].desc);
+		}
+		fprintf(stderr, "Current settings are:\n\t--disasm %s --disasm %d\n",
+			ConfigureParams.Debugger.bDisasmUAE ? "uae" : "ext",
+			ConfigureParams.Debugger.nDisasmOptions);
+		return "";
+	}	
+	if (strcasecmp(arg, "uae") == 0)
+	{
+		fputs("Selected UAE CPU core internal disassembler.\n", stderr);
+		ConfigureParams.Debugger.bDisasmUAE = true;
+		return NULL;
+	}
+	if (strcasecmp(arg, "ext") == 0)
+	{
+		fputs("Selected external disassembler.\n", stderr);
+		fprintf(stderr, "Disassembly output flags are %d.\n", options);
+		ConfigureParams.Debugger.bDisasmUAE = false;
+		return NULL;
+	}
+	if (isdigit((unsigned char)*arg))
+	{
+		int newopt = atoi(arg);
+		if ((newopt|optionsMask) != optionsMask)
+		{
+			return "unknown flags in the bitmask";
+		}
+		fprintf(stderr, "Changed CPU disassembly output flags from %d to %d.\n", options, newopt);
+		ConfigureParams.Debugger.nDisasmOptions = options = newopt;
+		Disasm_CheckOptionEngine();
+		return NULL;
+	}
+	return "invalid disasm option";
+}
diff --git a/src/debug/68kDisass.h b/src/debug/68kDisass.h
new file mode 100644
index 0000000..2bb2e72
--- /dev/null
+++ b/src/debug/68kDisass.h
@@ -0,0 +1,33 @@
+/*
+  Hatari - 68kDisass.h
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+*/
+#ifndef HATARI_68KDISASS_H
+#define HATARI_68KDISASS_H
+
+extern Uint32 Disasm_GetNextPC(Uint32 pc);
+extern void Disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt);
+
+enum {
+	DISASM_COLUMN_ADDRESS = 0,
+	DISASM_COLUMN_HEXDUMP,
+	DISASM_COLUMN_LABEL,
+	DISASM_COLUMN_OPCODE,
+	DISASM_COLUMN_OPERAND,
+	DISASM_COLUMN_COMMENT,
+	DISASM_COLUMNS			/* number of columns in disassembly output */
+};
+
+#define DISASM_COLUMN_DISABLE -1
+
+extern void Disasm_GetColumns(int *columns);
+extern void Disasm_SetColumns(int *columns);
+extern void Disasm_DisableColumn(int column, int *oldcols, int *newcols);
+
+extern const char* Disasm_ParseOption(const char *arg);
+extern int Disasm_GetOptions(void);
+void Disasm_SetCPUType ( int CPU , int FPU );
+
+#endif		/* HATARI_68KDISASS_H */
diff --git a/src/debug/CMakeLists.txt b/src/debug/CMakeLists.txt
new file mode 100644
index 0000000..34f5df4
--- /dev/null
+++ b/src/debug/CMakeLists.txt
@@ -0,0 +1,14 @@
+
+if(READLINE_FOUND)
+	include_directories(${READLINE_INCLUDE_DIR})
+endif(READLINE_FOUND)
+
+if(ENABLE_DSP_EMU)
+	set(DSPDBG_C debugdsp.c)
+endif(ENABLE_DSP_EMU)
+
+add_library(Debug
+	    log.c debugui.c breakcond.c debugcpu.c debugInfo.c
+	    ${DSPDBG_C} evaluate.c history.c symbols.c
+	    profile.c profilecpu.c profiledsp.c
+	    natfeats.c console.c 68kDisass.c)
diff --git a/src/debug/Makefile b/src/debug/Makefile
new file mode 100755
index 0000000..84f32ea
--- /dev/null
+++ b/src/debug/Makefile
@@ -0,0 +1,44 @@
+# Makefile for Hatari's debugging & tracing support.
+
+CPUDIR ?= uae-cpu
+ENABLE_DSP_EMU ?= 0
+
+# Include settings
+include ../../Makefile-wii.cnf
+
+# Additional include directories:
+INCFLAGS = -I. -I../.. -I../includes -I../$(CPUDIR) -I../falcon $(CPPFLAGS)
+
+SRCS = log.c debugui.c breakcond.c debugcpu.c debugInfo.c evaluate.c history.c symbols.c profile.c profilecpu.c profiledsp.c natfeats.c console.c 68kDisass.c
+ifeq ($(ENABLE_DSP_EMU),1)
+SRCS += debugdsp.c
+INCFLAGS += -DENABLE_DSP_EMU=1 
+endif
+
+# Set extra flags passed to the compiler
+CFLAGS += $(INCFLAGS) $(SDL_CFLAGS)
+
+
+OBJS = $(SRCS:.c=.o)
+
+all: debug.a
+
+debug.a: $(OBJS)
+	$(AR) cru $@ $^
+	$(RANLIB) $@
+
+
+clean:
+	$(RM) *.o debug.a
+
+distclean: clean
+	$(RM) Makefile.dep *~ *.bak *.orig
+
+
+# Use "make depend" to generate file dependencies:
+Makefile.dep: Makefile ../Makefile
+	$(CC) -M $(CFLAGS) $(SRCS) > Makefile.dep
+
+depend: Makefile.dep
+
+-include Makefile.dep
diff --git a/src/debug/Makefile.dep b/src/debug/Makefile.dep
new file mode 100644
index 0000000..e69de29
diff --git a/src/debug/breakcond.c b/src/debug/breakcond.c
new file mode 100644
index 0000000..63e21a5
--- /dev/null
+++ b/src/debug/breakcond.c
@@ -0,0 +1,1931 @@
+/*
+  Hatari - breakcond.c
+
+  Copyright (c) 2009-2012 by Eero Tamminen
+
+  This file is distributed under the GNU General Public License, version 2
+  or at your option any later version. Read the file gpl.txt for details.
+
+  breakcond.c - code for breakpoint conditions that can check variable
+  and memory values against each other, mask them etc. before deciding
+  whether the breakpoint should be triggered.  See BreakCond_Help()
+  for the syntax.
+*/
+const char BreakCond_fileid[] = "Hatari breakcond.c : " __DATE__ " " __TIME__;
+
+#include 
+#include 
+#include "config.h"
+#include "main.h"
+#include "file.h"
+#include "m68000.h"
+#include "memorySnapShot.h"
+#include "dsp.h"
+#include "stMemory.h"
+#include "str.h"
+#include "screen.h"	/* for defines needed by video.h */
+#include "video.h"	/* for Hatari video variable addresses */
+
+#include "debug_priv.h"
+#include "breakcond.h"
+#include "debugcpu.h"
+#include "debugdsp.h"
+#include "debugInfo.h"
+#include "debugui.h"
+#include "evaluate.h"
+#include "history.h"
+#include "symbols.h"
+#include "68kDisass.h"
+
+
+/* set to 1 to enable parsing function tracing / debug output */
+#define DEBUG 0
+
+/* needs to go through long long to handle x=32 */
+#define BITMASK(x)      ((Uint32)(((unsigned long long)1<<(x))-1))
+
+#define BC_DEFAULT_DSP_SPACE 'P'
+
+typedef enum {	
+	/* plain number */
+	VALUE_TYPE_NUMBER     = 0,
+
+	/* functions to call to get value */
+	VALUE_TYPE_FUNCTION32 = 2,
+
+	/* internal Hatari value variables */
+	VALUE_TYPE_VAR32      = 4,
+
+	/* size must match register size used in BreakCond_ParseRegister() */
+	VALUE_TYPE_REG16      = 16,
+	VALUE_TYPE_REG32      = 32
+} value_t;
+
+static inline bool is_register_type(value_t vtype) {
+	/* type used for CPU/DSP registers */
+	return (vtype == VALUE_TYPE_REG16 || vtype == VALUE_TYPE_REG32);
+}
+
+typedef struct {
+	bool is_indirect;
+	char dsp_space;	/* DSP has P, X, Y address spaces, zero if not DSP */
+	value_t valuetype;	/* Hatari value variable type */
+	union {
+		Uint32 number;
+		Uint16 (*func16)(void);
+		Uint32 (*func32)(void);
+		Uint16 *reg16;
+		Uint32 *reg32;
+	} value;
+	Uint32 bits;	/* CPU has 8/16/32 bit address widths */
+	Uint32 mask;	/*  &&  */
+} bc_value_t;
+
+typedef struct {
+	bc_value_t lvalue;
+	bc_value_t rvalue;
+	char comparison;
+	bool track;	/* track value changes */
+} bc_condition_t;
+
+typedef struct {
+	char *filename;	/* file where to read commands to do on hit */
+	int skip;	/* how many times to hit before breaking */
+	bool once;	/* remove after hit&break */
+	bool quiet;	/* no output from setting & hitting */
+	bool trace;	/* trace mode, don't break */
+	bool noinit;	/* prevent debugger inits on break */
+	bool lock;	/* tracing + show locked info */
+	bool deleted;   /* delayed delete flag */
+} bc_options_t;
+
+typedef struct {
+	char *expression;
+	bc_options_t options;
+	bc_condition_t *conditions;
+	int ccount;	/* condition count */
+	int hits;	/* how many times breakpoint hit */
+} bc_breakpoint_t;
+
+typedef struct {
+	bc_breakpoint_t *breakpoint;
+	bc_breakpoint_t *breakpoint2delete;	/* delayed delete of old alloc */
+	const char *name;
+	int count;
+	int allocated;
+	bool delayed_change;
+	const debug_reason_t reason;
+} bc_breakpoints_t;
+
+static bc_breakpoints_t CpuBreakPoints = {
+	.name = "CPU",
+	.reason = REASON_CPU_BREAKPOINT
+};
+static bc_breakpoints_t DspBreakPoints = {
+	.name = "DSP",
+	.reason = REASON_DSP_BREAKPOINT
+};
+
+
+/* forward declarations */
+static int BreakCond_DoDelayedActions(bc_breakpoints_t *bps, int triggered);
+static bool BreakCond_Remove(bc_breakpoints_t *bps, int position);
+static void BreakCond_Print(bc_breakpoint_t *bp);
+
+
+/**
+ * Save breakpoints as debugger input file
+ * return true for success, false for failure
+ */
+bool BreakCond_Save(const char *filename)
+{
+	FILE *fp;
+	int i;
+
+	if (!(CpuBreakPoints.count || DspBreakPoints.count)) {
+		if (File_Exists(filename)) {
+			if (remove(filename)) {
+				perror("ERROR");
+				return false;
+			}
+		}
+		return true;
+	}
+
+	fprintf(stderr, "Saving breakpoints to '%s'...\n", filename);
+	fp = fopen(filename, "w");
+	if (!fp) {
+		perror("ERROR");
+		return false;
+	}
+	/* save conditional breakpoints as debugger input file */
+	for (i = 0; i < CpuBreakPoints.count; i++) {
+		fprintf(fp, "b %s\n", CpuBreakPoints.breakpoint[i].expression);
+	}
+	for (i = 0; i < DspBreakPoints.count; i++) {
+		fprintf(fp, "db %s\n", DspBreakPoints.breakpoint[i].expression);
+	}
+	fclose(fp);
+	return true;
+}
+
+
+/* --------------------- debugging code ------------------- */
+
+#if DEBUG
+/* see parsing code for usage examples */
+static int _traceIndent;
+static void _spaces(void)
+{
+	int spaces = _traceIndent;
+	while(spaces-- > 0) {
+		putchar(' ');	/* fputc(' ',stdout); */
+	}
+}
+#define ENTERFUNC(args) { _traceIndent += 2; _spaces(); printf args ; fflush(stdout); }
+#define EXITFUNC(args) { _spaces(); printf args ; fflush(stdout); _traceIndent -= 2; }
+#else
+#define ENTERFUNC(args)
+#define EXITFUNC(args)
+#endif
+
+
+/* ------------- breakpoint condition checking, internals ------------- */
+
+/**
+ * Return value from given DSP memory space/address
+ */
+static Uint32 BreakCond_ReadDspMemory(Uint32 addr, const bc_value_t *bc_value)
+{
+	const char *dummy;
+	return DSP_ReadMemory(addr, bc_value->dsp_space, &dummy) & BITMASK(24);
+}
+
+/**
+ * Return value of given size read from given ST memory address
+ */
+static Uint32 BreakCond_ReadSTMemory(Uint32 addr, const bc_value_t *bc_value)
+{
+	switch (bc_value->bits) {
+	case 32:
+		return STMemory_ReadLong(addr);
+	case 16:
+		return STMemory_ReadWord(addr);
+	case 8:
+		return STMemory_ReadByte(addr);
+	default:
+		fprintf(stderr, "ERROR: unknown ST address size %d!\n", bc_value->bits);
+		abort();
+	}
+}
+
+
+/**
+ * Return Uint32 value according to given bc_value_t specification
+ */
+static Uint32 BreakCond_GetValue(const bc_value_t *bc_value)
+{
+	Uint32 value;
+
+	switch (bc_value->valuetype) {
+	case VALUE_TYPE_NUMBER:
+		value = bc_value->value.number;
+		break;
+	case VALUE_TYPE_FUNCTION32:
+		value = bc_value->value.func32();
+		break;
+	case VALUE_TYPE_REG16:
+		value = *(bc_value->value.reg16);
+		break;
+	case VALUE_TYPE_VAR32:
+	case VALUE_TYPE_REG32:
+		value = *(bc_value->value.reg32);
+		break;
+	default:
+		fprintf(stderr, "ERROR: unknown condition value size/type %d!\n", bc_value->valuetype);
+		abort();
+	}
+	if (bc_value->is_indirect) {
+		if (bc_value->dsp_space) {
+			value = BreakCond_ReadDspMemory(value, bc_value);
+		} else {
+			value = BreakCond_ReadSTMemory(value, bc_value);
+		}
+	}
+	return (value & bc_value->mask);
+}
+
+
+/**
+ * Show & update rvalue for a tracked breakpoint condition to lvalue
+ */
+static void BreakCond_UpdateTracked(bc_condition_t *condition, Uint32 value)
+{
+	Uint32 addr;
+
+	/* next monitor changes to this new value */
+	condition->rvalue.value.number = value;
+
+	if (condition->lvalue.is_indirect &&
+	    condition->lvalue.valuetype == VALUE_TYPE_NUMBER) {
+		/* simple memory address */
+		addr = condition->lvalue.value.number;
+		fprintf(stderr, "  $%x = $%x\n", addr, value);
+	} else {
+		/* register tms. */
+		fprintf(stderr, "  $%x\n", value);
+	}
+}
+
+
+/**
+ * Return true if all of the given breakpoint's conditions match
+ */
+static bool BreakCond_MatchConditions(bc_condition_t *condition, int count)
+{
+	Uint32 lvalue, rvalue;
+	bool hit = false;
+	int i;
+	
+	for (i = 0; i < count; condition++, i++) {
+
+		lvalue = BreakCond_GetValue(&(condition->lvalue));
+		rvalue = BreakCond_GetValue(&(condition->rvalue));
+
+		switch (condition->comparison) {
+		case '<':
+			hit = (lvalue < rvalue);
+			break;
+		case '>':
+			hit = (lvalue > rvalue);
+			break;
+		case '=':
+			hit = (lvalue == rvalue);
+			break;
+		case '!':
+			hit = (lvalue != rvalue);
+			break;
+		default:
+			fprintf(stderr, "ERROR: Unknown breakpoint value comparison operator '%c'!\n",
+				condition->comparison);
+			abort();
+		}
+		if (likely(!hit)) {
+			return false;
+		}
+		if (condition->track) {
+			BreakCond_UpdateTracked(condition, lvalue);
+		}
+	}
+	/* all conditions matched */
+	return true;
+}
+
+
+/**
+ * Show all breakpoints which conditions matched and return which matched
+ * @return	index to last matching (non-tracing) breakpoint,
+ *		or zero if none matched
+ */
+static int BreakCond_MatchBreakPoints(bc_breakpoints_t *bps)
+{
+	bc_breakpoint_t *bp;
+	bool changes = false;
+	int i, ret = 0;
+
+	/* array should not be changed while it's being traversed */
+	assert(likely(!bps->delayed_change));
+	bps->delayed_change = true;
+
+	bp = bps->breakpoint;
+	for (i = 0; i < bps->count; bp++, i++) {
+
+		if (BreakCond_MatchConditions(bp->conditions, bp->ccount)) {
+			bp->hits++;
+			if (bp->options.skip) {
+				if (bp->hits % bp->options.skip) {
+					/* check next */
+					continue;
+				}
+			}
+			if (!bp->options.quiet) {
+				fprintf(stderr, "%d. %s breakpoint condition(s) matched %d times.\n",
+					i+1, bps->name, bp->hits);			
+				BreakCond_Print(bp);
+			}
+			History_Mark(bps->reason);
+
+			if (bp->options.lock || bp->options.filename) {
+				bool reinit = !bp->options.noinit;
+
+				if (reinit) {
+					DebugCpu_InitSession();
+					DebugDsp_InitSession();
+				}
+
+				if (bp->options.lock) {
+					DebugInfo_ShowSessionInfo();
+				}
+				if (bp->options.filename) {
+					DebugUI_ParseFile(bp->options.filename, reinit);
+					changes = true;
+				}
+			}
+			if (bp->options.once) {
+				BreakCond_Remove(bps, i+1);
+				changes = true;
+			}
+			if (!bp->options.trace) {
+				/* index for current hit, they start from 1 */
+				ret = i + 1;
+			}
+			/* continue checking breakpoints to make sure all relevant actions get performed */
+		}
+	}
+	bps->delayed_change = false;
+	if (unlikely(changes)) {
+		ret = BreakCond_DoDelayedActions(bps, ret);
+	}
+	return ret;
+}
+
+/* ------------- breakpoint condition checking, public API ------------- */
+
+/**
+ * Return matched CPU breakpoint index or zero for no hits.
+ */
+int BreakCond_MatchCpu(void)
+{
+	return BreakCond_MatchBreakPoints(&CpuBreakPoints);
+}
+
+/**
+ * Return matched DSP breakpoint index or zero for no hits.
+ */
+int BreakCond_MatchDsp(void)
+{
+	return BreakCond_MatchBreakPoints(&DspBreakPoints);
+}
+
+/**
+ * Return number of CPU condition breakpoints
+ */
+int BreakCond_CpuBreakPointCount(void)
+{
+	return CpuBreakPoints.count;
+}
+
+/**
+ * Return number of DSP condition breakpoints
+ */
+int BreakCond_DspBreakPointCount(void)
+{
+	return DspBreakPoints.count;
+}
+
+
+/* -------------- breakpoint condition parsing, internals ------------- */
+
+/* struct for passing around breakpoint conditions parsing state */
+typedef struct {
+	int arg;		/* current arg */
+	int argc;		/* arg count */
+	const char **argv;	/* arg pointer array (+ strings) */
+	const char *error;	/* error from parsing args */
+} parser_state_t;
+
+
+/* Hatari variable name & address array items */
+typedef struct {
+	const char *name;
+	Uint32 *addr;
+	value_t vtype;
+	size_t bits;
+	const char *constraints;
+} var_addr_t;
+
+/* Accessor functions for calculated Hatari values */
+static Uint32 GetLineCycles(void)
+{
+	int dummy1, dummy2, lcycles;
+	Video_GetPosition(&dummy1, &dummy2 , &lcycles);
+	return lcycles;
+}
+static Uint32 GetFrameCycles(void)
+{
+	int dummy1, dummy2, fcycles;
+	Video_GetPosition(&fcycles, &dummy1, &dummy2);
+	return fcycles;
+}
+
+/* helpers for TOS OS call opcode accessor functions */
+#define INVALID_OPCODE 0xFFFFu
+
+static inline Uint16 getLineOpcode(Uint8 line)
+{
+	Uint32 pc;
+	Uint16 instr;
+	pc = M68000_GetPC();
+	instr = STMemory_ReadWord(pc);
+	/* for opcode X, Line-A = 0xA00X, Line-F = 0xF00X */
+	if ((instr >> 12) == line) {
+		return instr & 0xFF;
+	}
+	return INVALID_OPCODE;
+}
+static inline bool isTrap(Uint8 trap)
+{
+	Uint32 pc;
+	Uint16 instr;
+	pc = M68000_GetPC();
+	instr = STMemory_ReadWord(pc);
+	return (instr == (Uint16)0x4e40u + trap);
+}
+static inline Uint16 getControlOpcode(void)
+{
+	/* Control[] address from D1, opcode in Control[0] */
+	return STMemory_ReadWord(STMemory_ReadLong(Regs[REG_D1]));
+}
+static inline Uint16 getStackOpcode(void)
+{
+	return STMemory_ReadWord(Regs[REG_A7]);
+}
+
+/* Actual TOS OS call opcode accessor functions */
+static Uint32 GetLineAOpcode(void)
+{
+	return getLineOpcode(0xA);
+}
+static Uint32 GetLineFOpcode(void)
+{
+	return getLineOpcode(0xF);
+}
+static Uint32 GetGemdosOpcode(void)
+{
+	if (isTrap(1)) {
+		return getStackOpcode();
+	}
+	return INVALID_OPCODE;
+}
+static Uint32 GetBiosOpcode(void)
+{
+	if (isTrap(13)) {
+		return getStackOpcode();
+	}
+	return INVALID_OPCODE;
+}
+static Uint32 GetXbiosOpcode(void)
+{
+	if (isTrap(14)) {
+		return getStackOpcode();
+	}
+	return INVALID_OPCODE;
+}
+static Uint32 GetAesOpcode(void)
+{
+	if (isTrap(2)) {
+		Uint16 d0 = Regs[REG_D0];
+		if (d0 == 0xC8) {
+			return getControlOpcode();
+		} else if (d0 == 0xC9) {
+			/* same as appl_yield() */
+			return 0x11;
+		}
+	}
+	return INVALID_OPCODE;
+}
+static Uint32 GetVdiOpcode(void)
+{
+	if (isTrap(2)) {
+		Uint16 d0 = Regs[REG_D0];
+		if (d0 == 0x73) {
+			return getControlOpcode();
+		} else if (d0 == 0xFFFE) {
+			/* -2 = vq_[v]gdos() */
+			return 0xFFFE;
+		}
+	}
+	return INVALID_OPCODE;
+}
+
+static Uint32 GetNextPC(void)
+{
+	return Disasm_GetNextPC(M68000_GetPC());
+}
+
+/* sorted by variable name so that this can be bisected */
+static const var_addr_t hatari_vars[] = {
+	{ "AesOpcode", (Uint32*)GetAesOpcode, VALUE_TYPE_FUNCTION32, 16, "by default FFFF" },
+	{ "Basepage", (Uint32*)DebugInfo_GetBASEPAGE, VALUE_TYPE_FUNCTION32, 0, "invalid before Desktop is up" },
+	{ "BiosOpcode", (Uint32*)GetBiosOpcode, VALUE_TYPE_FUNCTION32, 16, "by default FFFF" },
+	{ "BSS", (Uint32*)DebugInfo_GetBSS, VALUE_TYPE_FUNCTION32, 0, "invalid before Desktop is up" },
+	{ "CpuInstr", (Uint32*)DebugCpu_InstrCount, VALUE_TYPE_FUNCTION32, 0, "CPU instructions count" },
+	{ "CpuOpcodeType", (Uint32*)DebugCpu_OpcodeType, VALUE_TYPE_FUNCTION32, 0, "CPU instruction type" },
+	{ "DATA", (Uint32*)DebugInfo_GetDATA, VALUE_TYPE_FUNCTION32, 0, "invalid before Desktop is up" },
+#if ENABLE_DSP_EMU
+	{ "DspInstr", (Uint32*)DebugDsp_InstrCount, VALUE_TYPE_FUNCTION32, 0, "DSP instructions count" },
+	{ "DspOpcodeType", (Uint32*)DebugDsp_OpcodeType, VALUE_TYPE_FUNCTION32, 0, "DSP instruction type" },
+#endif
+	{ "FrameCycles", (Uint32*)GetFrameCycles, VALUE_TYPE_FUNCTION32, 0, NULL },
+	{ "GemdosOpcode", (Uint32*)GetGemdosOpcode, VALUE_TYPE_FUNCTION32, 16, "by default FFFF" },
+	{ "HBL", (Uint32*)&nHBL, VALUE_TYPE_VAR32, sizeof(nHBL)*8, NULL },
+	{ "LineAOpcode", (Uint32*)GetLineAOpcode, VALUE_TYPE_FUNCTION32, 16, "by default FFFF" },
+	{ "LineCycles", (Uint32*)GetLineCycles, VALUE_TYPE_FUNCTION32, 0, "is always divisable by 4" },
+	{ "LineFOpcode", (Uint32*)GetLineFOpcode, VALUE_TYPE_FUNCTION32, 16, "by default FFFF" },
+	{ "NextPC", (Uint32*)GetNextPC, VALUE_TYPE_FUNCTION32, 0, NULL },
+	{ "TEXT", (Uint32*)DebugInfo_GetTEXT, VALUE_TYPE_FUNCTION32, 0, "invalid before Desktop is up" },
+	{ "TEXTEnd", (Uint32*)DebugInfo_GetTEXTEnd, VALUE_TYPE_FUNCTION32, 0, "invalid before Desktop is up" },
+	{ "VBL", (Uint32*)&nVBLs, VALUE_TYPE_VAR32, sizeof(nVBLs)*8, NULL },
+	{ "VdiOpcode", (Uint32*)GetVdiOpcode, VALUE_TYPE_FUNCTION32, 16, "by default FFFF" },
+	{ "XbiosOpcode", (Uint32*)GetXbiosOpcode, VALUE_TYPE_FUNCTION32, 16, "by default FFFF" }
+};
+
+
+/**
+ * Readline match callback for CPU variable/symbol name completion.
+ * STATE = 0 -> different text from previous one.
+ * Return next match or NULL if no matches.
+ */
+char *BreakCond_MatchCpuVariable(const char *text, int state)
+{
+	static int i, len;
+	const char *name;
+	
+	if (!state) {
+		/* first match */
+		len = strlen(text);
+		i = 0;
+	}
+	/* next match */
+	while (i < ARRAYSIZE(hatari_vars)) {
+		name = hatari_vars[i++].name;
+		if (strncasecmp(name, text, len) == 0)
+			return (strdup(name));
+	}
+	/* no variable match, check all CPU symbols */
+	return Symbols_MatchCpuAddress(text, state);
+}
+
+/**
+ * Readline match callback for DSP variable/symbol name completion.
+ * STATE = 0 -> different text from previous one.
+ * Return next match or NULL if no matches.
+ */
+char *BreakCond_MatchDspVariable(const char *text, int state)
+{
+	/* currently no DSP variables, check all DSP symbols */
+	return Symbols_MatchDspAddress(text, state);
+}
+
+
+/**
+ * If given string is a Hatari variable name, set bc_value
+ * fields accordingly and return true, otherwise return false.
+ */
+static bool BreakCond_ParseVariable(const char *name, bc_value_t *bc_value)
+{
+	const var_addr_t *hvar;
+	/* left, right, middle, direction */
+        int l, r, m, dir;
+
+	ENTERFUNC(("BreakCond_ParseVariable('%s')\n", name));
+	/* bisect */
+	l = 0;
+	r = ARRAYSIZE(hatari_vars) - 1;
+	do {
+		m = (l+r) >> 1;
+		hvar = hatari_vars + m;
+		dir = strcasecmp(name, hvar->name);
+		if (dir == 0) {
+			bc_value->value.reg32 = hvar->addr;
+			bc_value->valuetype = hvar->vtype;
+			bc_value->bits = hvar->bits;
+			assert(bc_value->bits == 32 || bc_value->valuetype !=  VALUE_TYPE_VAR32);
+			EXITFUNC(("-> true\n"));
+			return true;
+		}
+		if (dir < 0) {
+			r = m-1;
+		} else {
+			l = m+1;
+		}
+	} while (l <= r);
+	EXITFUNC(("-> false\n"));
+	return false;
+}
+
+/**
+ * If given string is a Hatari variable name, set value to given
+ * variable value and return true, otherwise return false.
+ */
+bool BreakCond_GetHatariVariable(const char *name, Uint32 *value)
+{
+	bc_value_t bc_value;
+	if (!BreakCond_ParseVariable(name, &bc_value)) {
+		return false;
+	}
+	bc_value.mask = 0xffffffff;
+	bc_value.is_indirect = false;
+	*value = BreakCond_GetValue(&bc_value);
+	return true;
+}
+
+
+/**
+ * If given string matches a suitable symbol, set bc_value
+ * fields accordingly and return true, otherwise return false.
+ */
+static bool BreakCond_ParseSymbol(const char *name, bc_value_t *bc_value)
+{
+	symtype_t symtype;
+	Uint32 addr;
+
+	ENTERFUNC(("BreakCond_ParseSymbol('%s')\n", name));
+	if (bc_value->is_indirect) {
+		/* indirect use of address makes sense only for data */
+		symtype = SYMTYPE_DATA|SYMTYPE_BSS;
+	} else {
+		/* direct value can be compared for anything */
+		symtype = SYMTYPE_ALL;
+	}
+	
+	if (bc_value->dsp_space) {
+		if (!Symbols_GetDspAddress(symtype, name, &addr)) {
+			EXITFUNC(("-> false (DSP)\n"));
+			return false;
+		}
+		/* all DSP memory values are 24-bits */
+		bc_value->bits = 24;
+		bc_value->value.number = addr;
+		bc_value->valuetype = VALUE_TYPE_NUMBER;
+		EXITFUNC(("-> true (DSP)\n"));
+		return true;
+	}
+	
+	if (!Symbols_GetCpuAddress(symtype, name, &addr)) {
+		EXITFUNC(("-> false (CPU)\n"));
+		return false;
+	}
+	if (addr & 1) {
+		/* only bytes can be at odd addresses */
+		bc_value->bits = 8;
+	} else {
+		bc_value->bits = 32;
+	}
+	bc_value->value.number = addr;
+	bc_value->valuetype = VALUE_TYPE_NUMBER;
+	EXITFUNC(("-> true (CPU)\n"));
+	return true;
+}
+
+
+/**
+ * Helper function to get CPU PC register value with static inline as Uint32
+ */
+static Uint32 GetCpuPC(void)
+{
+	return M68000_GetPC();
+}
+/**
+ * Helper function to get CPU SR register value with static inline as Uint32
+ */
+static Uint32 GetCpuSR(void)
+{
+	return M68000_GetSR();
+}
+
+/**
+ * If given string is register name (for DSP or CPU), set bc_value
+ * fields accordingly and return true, otherwise return false.
+ */
+static bool BreakCond_ParseRegister(const char *regname, bc_value_t *bc_value)
+{
+	int regsize;
+	ENTERFUNC(("BreakCond_ParseRegister('%s')\n", regname));
+	if (bc_value->dsp_space) {
+		regsize = DSP_GetRegisterAddress(regname,
+					      &(bc_value->value.reg32),
+					      &(bc_value->mask));
+		if (regsize) {
+			if (bc_value->is_indirect
+			    && toupper((unsigned char)regname[0]) != 'R') {
+				fprintf(stderr, "ERROR: only R0-R7 DSP registers can be used for indirect addressing!\n");
+				EXITFUNC(("-> false (DSP)\n"));
+				return false;
+			}
+			/* all DSP memory values are 24-bits */
+			bc_value->bits = 24;
+			bc_value->valuetype = regsize;
+			EXITFUNC(("-> true (DSP)\n"));
+			return true;
+		}
+		EXITFUNC(("-> false (DSP)\n"));
+		return false;
+	}
+	regsize = DebugCpu_GetRegisterAddress(regname, &(bc_value->value.reg32));
+	if (regsize) {
+		bc_value->bits = regsize;
+		/* valuetypes for registers are 16 & 32 */
+		bc_value->valuetype = regsize;
+		EXITFUNC(("-> true (CPU)\n"));
+		return true;
+	}
+	/* Exact UAE core 32-bit PC & 16-bit SR register values
+	 * can be gotten only through UAE accessors, not directly
+	 */
+	if (strcasecmp(regname, "PC") == 0) {
+		bc_value->bits = 32;
+		bc_value->value.func32 = GetCpuPC;
+		bc_value->valuetype = VALUE_TYPE_FUNCTION32;
+		EXITFUNC(("-> true (CPU)\n"));
+		return true;
+	}
+	if (strcasecmp(regname, "SR") == 0) {
+		bc_value->bits = 16;
+		bc_value->value.func32 = GetCpuSR;
+		bc_value->valuetype = VALUE_TYPE_FUNCTION32;
+		EXITFUNC(("-> true (CPU)\n"));
+		return true;
+	}
+	EXITFUNC(("-> false (CPU)\n"));
+	return false;
+}
+
+/**
+ * If given address is valid (for DSP or CPU), return true.
+ */
+static bool BreakCond_CheckAddress(bc_value_t *bc_value)
+{
+	Uint32 addr = bc_value->value.number;
+	int size = bc_value->bits >> 8;
+
+	ENTERFUNC(("BreakCond_CheckAddress(%x)\n", addr));
+	if (bc_value->dsp_space) {
+		if (addr+size > 0xFFFF) {
+			EXITFUNC(("-> false (DSP)\n"));
+			return false;
+		}
+		EXITFUNC(("-> true (DSP)\n"));
+		return true;
+	}
+	if (!STMemory_CheckAreaType(addr, size, ABFLAG_RAM | ABFLAG_ROM | ABFLAG_IO)) {
+		EXITFUNC(("-> false (CPU)\n"));
+		return false;
+	}
+	EXITFUNC(("-> true (CPU)\n"));
+	return true;
+}
+
+
+/**
+ * Check for and parse a condition value address space/width modifier.
+ * Modify pstate according to parsing (arg index and error string).
+ * Return false for error and true for no or successfully parsed modifier.
+ */
+static bool BreakCond_ParseAddressModifier(parser_state_t *pstate, bc_value_t *bc_value)
+{
+	char mode;
+
+	ENTERFUNC(("BreakCond_ParseAddressModifier()\n"));
+	if (pstate->arg+2 > pstate->argc ||
+	    strcmp(pstate->argv[pstate->arg], ".") != 0) {
+		if (bc_value->dsp_space && bc_value->is_indirect) {
+			pstate->error = "DSP memory addresses need to specify address space";
+			EXITFUNC(("arg:%d -> false\n", pstate->arg));
+			return false;
+		}
+		EXITFUNC(("arg:%d -> true (missing)\n", pstate->arg));
+		return true;
+	}
+	if (!bc_value->is_indirect) {
+		pstate->error = "space/width modifier makes sense only for an address (register)";
+		EXITFUNC(("arg:%d -> false\n", pstate->arg));
+		return false;
+	}
+	pstate->arg++;
+	if (bc_value->dsp_space) {
+		switch (pstate->argv[pstate->arg][0]) {
+		case 'p':
+		case 'x':
+		case 'y':
+			mode = toupper((unsigned char)pstate->argv[pstate->arg][0]);
+			break;
+		default:
+			pstate->error = "invalid address space modifier";
+			EXITFUNC(("arg:%d -> false\n", pstate->arg));
+			return false;
+		}
+	} else {
+		switch (pstate->argv[pstate->arg][0]) {
+		case 'l':
+			mode = 32;
+			break;
+		case 'w':
+			mode = 16;
+			break;
+		case 'b':
+			mode = 8;
+			break;
+		default:
+			pstate->error = "invalid address width modifier";
+			EXITFUNC(("arg:%d -> false\n", pstate->arg));
+			return false;
+		}
+	}
+	if (pstate->argv[pstate->arg][1]) {
+		pstate->error = "invalid address space/width modifier";
+		EXITFUNC(("arg:%d -> false\n", pstate->arg));
+		return false;
+	}
+	if (bc_value->dsp_space) {
+		bc_value->dsp_space = mode;
+		EXITFUNC(("arg:%d -> space:%c, true\n", pstate->arg, mode));
+	} else {
+		bc_value->bits = mode;
+		EXITFUNC(("arg:%d -> width:%d, true\n", pstate->arg, mode));
+	}
+	pstate->arg++;
+	return true;
+}
+
+
+/**
+ * Check for and parse a condition value mask.
+ * Modify pstate according to parsing (arg index and error string).
+ * Return false for error and true for no or successfully parsed modifier.
+ */
+static bool BreakCond_ParseMaskModifier(parser_state_t *pstate, bc_value_t *bc_value)
+{
+	ENTERFUNC(("BreakCond_ParseMaskModifier()\n"));
+	if (pstate->arg+2 > pstate->argc ||
+	    strcmp(pstate->argv[pstate->arg], "&") != 0) {
+		EXITFUNC(("arg:%d -> true (missing)\n", pstate->arg));
+		return true;
+	}
+	if (bc_value->valuetype == VALUE_TYPE_NUMBER &&
+	    !bc_value->is_indirect) {
+		fprintf(stderr, "WARNING: plain numbers shouldn't need masks.\n");
+	}
+	pstate->arg++;
+	if (!Eval_Number(pstate->argv[pstate->arg], &(bc_value->mask))) {
+		pstate->error = "invalid dec/hex/bin value";
+		EXITFUNC(("arg:%d -> false\n", pstate->arg));
+		return false;
+	}
+	if (bc_value->mask == 0 ||
+	    (bc_value->valuetype == VALUE_TYPE_NUMBER && !bc_value->is_indirect &&
+	     bc_value->value.number && !(bc_value->value.number & bc_value->mask))) {
+		pstate->error = "mask zeroes value";
+		EXITFUNC(("arg:%d -> false\n", pstate->arg));
+		return false;
+	}
+	EXITFUNC(("arg:%d -> true (%x)\n", pstate->arg, bc_value->mask));
+	pstate->arg++;
+	return true;
+}
+
+
+/**
+ * Parse a breakpoint condition value.
+ * Modify pstate according to parsing (arg index and error string).
+ * Return true for success and false for error.
+ */
+static bool BreakCond_ParseValue(parser_state_t *pstate, bc_value_t *bc_value)
+{
+	const char *str;
+	int skip = 1;
+
+	ENTERFUNC(("BreakCond_Value()\n"));
+	if (pstate->arg >= pstate->argc) {
+		pstate->error = "value missing";
+		EXITFUNC(("arg:%d -> false\n", pstate->arg));
+		return false;
+	}
+	/* parse indirection */
+	if (pstate->arg+3 <= pstate->argc) {
+		if (strcmp(pstate->argv[pstate->arg+0], "(") == 0 &&
+		    strcmp(pstate->argv[pstate->arg+2], ")") == 0) {
+			bc_value->is_indirect = true;
+			pstate->arg++;
+			skip = 2;
+		}
+	}
+	
+	str = pstate->argv[pstate->arg];
+	if (isalpha((unsigned char)*str) || *str == '_') {
+		/* parse direct or indirect variable/register/symbol name */
+		if (bc_value->is_indirect) {
+			/* a valid register or data symbol name? */
+			if (!BreakCond_ParseRegister(str, bc_value) &&
+			    !BreakCond_ParseSymbol(str, bc_value)) {
+				pstate->error = "invalid register/symbol name for indirection";
+				EXITFUNC(("arg:%d -> false\n", pstate->arg));
+				return false;
+			}
+		} else {
+			/* a valid Hatari variable or register name?
+			 * variables cannot be used for ST memory indirection.
+			 */
+			if (!BreakCond_ParseVariable(str, bc_value) &&
+			    !BreakCond_ParseRegister(str, bc_value) &&
+			    !BreakCond_ParseSymbol(str, bc_value)) {
+				pstate->error = "invalid variable/register/symbol name";
+				EXITFUNC(("arg:%d -> false\n", pstate->arg));
+				return false;
+			}
+		}
+	} else {
+		/* a number */
+		if (!Eval_Number(str, &(bc_value->value.number))) {
+			pstate->error = "invalid dec/hex/bin value";
+			EXITFUNC(("arg:%d -> false\n", pstate->arg));
+			return false;
+		}
+	}
+	/* memory address (indirect value) -> OK as address? */
+	if (bc_value->is_indirect &&
+	    bc_value->valuetype == VALUE_TYPE_NUMBER &&
+	    !BreakCond_CheckAddress(bc_value)) {
+		pstate->error = "invalid address";
+		EXITFUNC(("arg:%d -> false\n", pstate->arg));
+		return false;
+	}
+	pstate->arg += skip;
+
+	/* parse modifiers */
+	if (!BreakCond_ParseAddressModifier(pstate, bc_value)) {
+		EXITFUNC(("arg:%d -> false\n", pstate->arg));
+		return false;
+	}
+	if (!BreakCond_ParseMaskModifier(pstate, bc_value)) {
+		EXITFUNC(("arg:%d -> false\n", pstate->arg));
+		return false;
+	}
+	EXITFUNC(("arg:%d -> true (%s value)\n", pstate->arg,
+		  (bc_value->is_indirect ? "indirect" : "direct")));
+	return true;
+}
+
+
+/**
+ * Parse a breakpoint comparison character.
+ * Modify pstate according to parsing (arg index and error string).
+ * Return the character or nil for an error.
+ */
+static char BreakCond_ParseComparison(parser_state_t *pstate)
+{
+	const char *comparison;
+	
+	ENTERFUNC(("BreakCond_ParseComparison(), arg:%d\n", pstate->arg));
+	if (pstate->arg >= pstate->argc) {
+		pstate->error = "breakpoint comparison missing";
+		EXITFUNC(("-> false\n"));
+		return false;
+	}
+	comparison = pstate->argv[pstate->arg];
+	switch (comparison[0]) {
+	case '<':
+	case '>':
+	case '=':
+	case '!':
+		break;
+	default:
+		pstate->error = "invalid comparison character";
+		EXITFUNC(("-> false\n"));
+		return false;
+	}
+	if (comparison[1]) {
+		pstate->error = "trailing comparison character(s)";
+		EXITFUNC(("-> false\n"));
+		return false;
+	}
+
+	pstate->arg++;
+	if (pstate->arg >= pstate->argc) {
+		pstate->error = "right side missing";
+		EXITFUNC(("-> false\n"));
+		return false;
+	}
+	EXITFUNC(("-> '%c'\n", *comparison));
+	return *comparison;
+}
+
+
+/**
+ * If no value, use the other value, if that also missing, use default
+ */
+static void BreakCond_InheritDefault(Uint32 *value1, Uint32 value2, Uint32 defvalue)
+{
+	if (!*value1) {
+		if (value2) {
+			*value1 = value2;
+		} else {
+			*value1 = defvalue;
+		}
+	}
+}
+
+/**
+ * Check & ensure that the masks and address sizes are sane
+ * and allow comparison with the other side.
+ * If yes, return true, otherwise false.
+ */
+static bool BreakCond_CrossCheckValues(parser_state_t *pstate,
+				       bc_value_t *bc_value1,
+				       bc_value_t *bc_value2)
+{
+	Uint32 mask1, mask2, defbits;
+	ENTERFUNC(("BreakCond_CrossCheckValues()\n"));
+
+	/* make sure there're valid bit widths and that masks have some value */
+	if (bc_value1->dsp_space) {
+		defbits = 24;
+	} else {
+		defbits = 32;
+	}
+	BreakCond_InheritDefault(&(bc_value1->bits), bc_value2->bits, defbits);
+	BreakCond_InheritDefault(&(bc_value2->bits), bc_value1->bits, defbits);
+	BreakCond_InheritDefault(&(bc_value1->mask), bc_value2->mask, BITMASK(bc_value1->bits));
+	BreakCond_InheritDefault(&(bc_value2->mask), bc_value1->mask, BITMASK(bc_value2->bits));
+
+	/* check first value mask & bit width */
+	mask1 = BITMASK(bc_value1->bits) & bc_value1->mask;
+	
+	if (mask1 != bc_value1->mask) {
+		fprintf(stderr, "WARNING: mask 0x%x doesn't fit into %d address/register bits.\n",
+			bc_value1->mask, bc_value1->bits);
+	}
+	if (!bc_value1->dsp_space &&
+	    bc_value1->is_indirect &&
+	    (bc_value1->value.number & 1) && bc_value1->bits > 8) {
+		fprintf(stderr, "WARNING: odd CPU address 0x%x given without using byte (.b) width.\n",
+			bc_value1->value.number);
+	}
+	
+	/* cross-check both values masks */
+	mask2 = BITMASK(bc_value2->bits) & bc_value2->mask;
+
+	if ((mask1 & mask2) == 0) {
+		pstate->error = "values masks cancel each other";
+		EXITFUNC(("-> false\n"));
+		return false;
+	}
+	if (bc_value2->is_indirect ||
+	    bc_value2->value.number == 0 ||
+	    bc_value2->valuetype != VALUE_TYPE_NUMBER) {
+		EXITFUNC(("-> true (no problematic direct types)\n"));
+		return true;
+	}
+	if ((bc_value2->value.number & mask1) != bc_value2->value.number) {
+		pstate->error = "number doesn't fit the other side address width&mask";
+		EXITFUNC(("-> false\n"));
+		return false;
+	}
+	EXITFUNC(("-> true\n"));
+	return true;
+}
+
+
+/**
+ * Parse given breakpoint conditions and append them to breakpoints.
+ * Modify pstate according to parsing (arg index and error string).
+ * Return number of added conditions or zero for failure.
+ */
+static int BreakCond_ParseCondition(parser_state_t *pstate, bool bForDsp,
+				    bc_breakpoint_t *bp, int ccount)
+{
+	bc_condition_t condition;
+
+	ENTERFUNC(("BreakCond_ParseCondition(...)\n"));
+
+	/* setup condition */
+	memset(&condition, 0, sizeof(bc_condition_t));
+	if (bForDsp) {
+		/* used also for checking whether value is for DSP */
+		condition.lvalue.dsp_space = BC_DEFAULT_DSP_SPACE;
+		condition.rvalue.dsp_space = BC_DEFAULT_DSP_SPACE;
+	}
+
+	/* parse condition */
+	if (!BreakCond_ParseValue(pstate, &(condition.lvalue))) {
+		EXITFUNC(("-> 0\n"));
+		return 0;
+	}
+	condition.comparison = BreakCond_ParseComparison(pstate);
+	if (!condition.comparison) {
+		EXITFUNC(("-> 0\n"));
+		return 0;
+	}
+	if (!BreakCond_ParseValue(pstate, &(condition.rvalue))) {
+		EXITFUNC(("-> 0\n"));
+		return 0;
+	}
+	if (!(BreakCond_CrossCheckValues(pstate, &(condition.lvalue), &(condition.rvalue)) &&
+	      BreakCond_CrossCheckValues(pstate, &(condition.rvalue), &(condition.lvalue)))) {
+		EXITFUNC(("-> 0\n"));
+		return 0;
+	}
+	/* copy new condition */
+	ccount += 1;
+	bp->conditions = realloc(bp->conditions, sizeof(bc_condition_t)*(ccount));
+	if (!bp->conditions) {
+		pstate->error = "failed to allocate space for breakpoint condition";
+		EXITFUNC(("-> 0\n"));
+		return 0;
+	}
+	bp->conditions[ccount-1] = condition;
+
+	/* continue with next condition? */
+	if (pstate->arg == pstate->argc) {
+		EXITFUNC(("-> %d conditions (all args parsed)\n", ccount));
+		return ccount;
+	}
+	if (strcmp(pstate->argv[pstate->arg], "&&") != 0) {
+		pstate->error = "trailing content for breakpoint condition";
+		EXITFUNC(("-> 0\n"));
+		return 0;
+	}
+	pstate->arg++;
+
+	/* recurse conditions parsing */
+	ccount = BreakCond_ParseCondition(pstate, bForDsp, bp, ccount);
+	if (!ccount) {
+		EXITFUNC(("-> 0\n"));
+		return 0;
+	}
+	EXITFUNC(("-> %d conditions (recursed)\n", ccount));
+	return ccount;
+}
+
+
+/**
+ * Tokenize given breakpoint expression to given parser struct.
+ * Return normalized expression string that corresponds to tokenization
+ * or NULL on error. On error, pstate->error contains the error message
+ * and pstate->arg index to invalid character (instead of to token like
+ * after parsing).
+ */
+static char *BreakCond_TokenizeExpression(const char *expression,
+					  parser_state_t *pstate)
+{
+	char separator[] = {
+		'=', '!', '<', '>',  /* comparison operators */
+		'(', ')', '.', '&',  /* other separators */
+		'\0'                 /* terminator */
+	};
+	bool is_separated, has_comparison;
+	char sep, *dst, *normalized;
+	const char *src;
+	int i, tokens;
+
+	memset(pstate, 0, sizeof(parser_state_t));
+
+	/* _minimum_ safe size for normalized expression is 2x+1 */
+	normalized = malloc(2*strlen(expression)+1);
+	if (!normalized) {
+		pstate->error = "alloc failed";
+		return NULL;
+	}
+
+	/* check characters & normalize string */
+	dst = normalized;
+	is_separated = false;
+	has_comparison = false;
+	for (src = expression; *src; src++) {
+		/* discard white space in source */
+		if (isspace((unsigned char)*src)) {
+			continue;
+		}
+		/* separate tokens with single space in destination */
+		for (i = 0; (sep = separator[i]); i++) {
+			if (*src == sep) {
+				if (dst > normalized) {
+					/* don't separate boolean AND '&&' */
+					if (*src == '&' && *(src-1) == '&') {
+						dst--;
+					} else {
+						if (!is_separated) {
+							*dst++ = ' ';
+						}
+					}
+				}
+				*dst++ = *src;
+				*dst++ = ' ';
+				is_separated = true;
+				if (i < 4) {
+					has_comparison = true;
+				}
+				break;
+			}
+		}
+		/* validate & copy other characters */
+		if (!sep) {
+			/* variable/register/symbol or number prefix? */
+			if (!(isalnum((unsigned char)*src) || *src == '_' ||
+			      *src == '$' || *src == '#' || *src == '%')) {
+				pstate->error = "invalid character";
+				pstate->arg = src-expression;
+				free(normalized);
+				return NULL;
+			}
+			*dst++ = *src;
+			is_separated = false;
+		}
+	}
+	if (is_separated) {
+		dst--;	/* no trailing space */
+	}
+	*dst = '\0';
+
+	if (!has_comparison) {
+		pstate->error = "condition comparison missing";
+		pstate->arg = strlen(expression)/2;
+		free(normalized);
+		return NULL;
+	}
+
+	/* allocate exact space for tokenized string array + strings */
+	tokens = 1;
+	for (dst = normalized; *dst; dst++) {
+		if (*dst == ' ') {
+			tokens++;
+		}
+	}
+	pstate->argv = malloc(tokens*sizeof(char*)+strlen(normalized)+1);
+	if (!pstate->argv) {
+		pstate->error = "alloc failed";
+		free(normalized);
+		return NULL;
+	}
+	/* and copy/tokenize... */
+	dst = (char*)(pstate->argv) + tokens*sizeof(char*);
+	strcpy(dst, normalized);
+	pstate->argv[0] = strtok(dst, " ");
+	for (i = 1; (dst = strtok(NULL, " ")); i++) {
+		pstate->argv[i] = dst;
+	}
+	assert(i == tokens);
+	pstate->argc = tokens;
+#if DEBUG
+	fprintf(stderr, "args->");
+	for (i = 0; i < tokens; i++) {
+		fprintf(stderr, " %d: %s,", i, pstate->argv[i]);
+	}
+	fprintf(stderr, "\n");
+#endif
+	return normalized;
+}
+
+
+/**
+ * Select corrent breakpoints struct and provide name for it.
+ * Make sure there's always space for at least one additional breakpoint.
+ * Return pointer to the breakpoints struct
+ */
+static bc_breakpoints_t* BreakCond_GetListInfo(bool bForDsp)
+{
+	bc_breakpoints_t *bps;
+	if (bForDsp) {
+		bps = &DspBreakPoints;
+	} else {
+		bps = &CpuBreakPoints;
+	}
+	/* allocate (more) space for breakpoints when needed */
+	if (bps->count + 1 >= bps->allocated) {
+		if (!bps->allocated) {
+			/* initial count of available breakpoints */
+			bps->allocated = 16;
+		} else {
+			bps->allocated *= 2;
+		}
+		if (bps->delayed_change) {
+			if(bps->breakpoint2delete) {
+				/* getting second re-alloc within same breakpoint handler is really
+				 * unlikely, this would require adding dozens of new breakpoints.
+				 */
+				fprintf(stderr, "ERROR: too many new breakpoints added within single breakpoint hit!\n");
+				abort();
+			}
+			bps->breakpoint2delete = bps->breakpoint;
+			bps->breakpoint = malloc(bps->allocated * sizeof(bc_breakpoint_t));
+		} else {
+			bps->breakpoint = realloc(bps->breakpoint, bps->allocated * sizeof(bc_breakpoint_t));
+		}
+		assert(bps->breakpoint);
+	}
+	return bps;
+}
+
+
+/**
+ * Check whether any of the breakpoint conditions is such that it's
+ * intended for tracking given value changes (inequality comparison
+ * on identical values) or for retrieving the current value to break
+ * on next value change (other comparisons on identical values).
+ *
+ * On former case, mark it for tracking, on other cases, just
+ * retrieve the value.
+ */
+static void BreakCond_CheckTracking(bc_breakpoint_t *bp)
+{
+	bc_condition_t *condition;
+	bool track = false;
+	Uint32 value;
+	int i;
+
+	condition = bp->conditions;
+	for (i = 0; i < bp->ccount; condition++, i++) {
+		
+		if (memcmp(&(condition->lvalue), &(condition->rvalue), sizeof(bc_value_t)) == 0) {
+			/* set current value to right side */
+			value = BreakCond_GetValue(&(condition->rvalue));
+			condition->rvalue.value.number = value;
+			condition->rvalue.valuetype = VALUE_TYPE_NUMBER;
+			condition->rvalue.is_indirect = false;
+			/* track those changes */
+			if (condition->comparison != '=') {
+				condition->track = true;
+				track = true;
+			} else {
+				fprintf(stderr, "\t%d. condition: %c $%x\n",
+					i+1, condition->comparison, value);
+			}
+		}
+	}
+	if (track) {
+		fprintf(stderr, "-> Track value changes, show value(s) when matched.\n");
+	}
+}
+
+
+/**
+ * Parse given breakpoint expression and store it.
+ * Return true for success and false for failure.
+ */
+static bool BreakCond_Parse(const char *expression, bc_options_t *options, bool bForDsp)
+{
+	parser_state_t pstate;
+	bc_breakpoints_t *bps;
+	bc_breakpoint_t *bp;
+	char *normalized;
+	int ccount;
+
+	bps = BreakCond_GetListInfo(bForDsp);
+
+	bp = bps->breakpoint + bps->count;
+	memset(bp, 0, sizeof(bc_breakpoint_t));
+
+	normalized = BreakCond_TokenizeExpression(expression, &pstate);
+	if (normalized) {
+		bp->expression = normalized;
+		ccount = BreakCond_ParseCondition(&pstate, bForDsp, bp, 0);
+		/* fail? */
+		if (!ccount) {
+			bp->expression = NULL;
+			if (bp->conditions) {
+				/* free what was allocated by ParseCondition */
+				free(bp->conditions);
+				bp->conditions = NULL;
+			}
+		}
+		bp->ccount = ccount;
+	} else {
+		ccount = 0;
+	}
+	if (pstate.argv) {
+		free(pstate.argv);
+	}
+	if (ccount > 0) {
+		bps->count++;
+		if (!options->quiet) {
+			fprintf(stderr, "%s condition breakpoint %d with %d condition(s) added:\n\t%s\n",
+				bps->name, bps->count, ccount, bp->expression);
+			if (options->skip) {
+				fprintf(stderr, "-> Break only on every %d hit.\n", options->skip);
+			}
+			if (options->once) {
+				fprintf(stderr, "-> Once, delete after breaking.\n");
+			}
+			if (options->trace) {
+				fprintf(stderr, "-> Trace instead of breaking, but show still hits.\n");
+				if (options->lock) {
+					fprintf(stderr, "-> Show also info selected with lock command.\n");
+				}				
+				if (options->noinit) {
+					fprintf(stderr, "-> Skip debugger inits on hit.\n");
+				}				
+			}
+			if (options->filename) {
+				fprintf(stderr, "-> Execute debugger commands from '%s' file on hit.\n", options->filename);
+			}
+		}
+		BreakCond_CheckTracking(bp);
+
+		bp->options.quiet = options->quiet;
+		bp->options.skip = options->skip;
+		bp->options.once = options->once;
+		bp->options.trace = options->trace;
+		bp->options.lock = options->lock;
+		bp->options.noinit = options->noinit;
+		if (options->filename) {
+			bp->options.filename = strdup(options->filename);
+		}
+	} else {
+		if (normalized) {
+			int offset, i = 0;
+			char *s = normalized;
+			while (*s && i < pstate.arg) {
+				if (*s++ == ' ') {
+					i++;
+				}
+			}
+			offset = s - normalized;
+			/* show tokenized string and point out
+			 * the token where the error was encountered
+			 */
+			fprintf(stderr, "ERROR in tokenized string:\n'%s'\n%*c-%s\n",
+				normalized, offset+2, '^', pstate.error);
+			free(normalized);
+		} else {
+			/* show original string and point out the character
+			 * where the error was encountered
+			 */
+			fprintf(stderr, "ERROR in parsed string:\n'%s'\n%*c-%s\n",
+				expression, pstate.arg+2, '^', pstate.error);
+		}
+	}
+	return (ccount > 0);
+}
+
+
+/**
+ * print single breakpoint
+ */
+static void BreakCond_Print(bc_breakpoint_t *bp)
+{
+		fprintf(stderr, "\t%s", bp->expression);
+		if (bp->options.skip) {
+			fprintf(stderr, " :%d", bp->options.skip);
+		}
+		if (bp->options.once) {
+			fprintf(stderr, " :once");
+		}
+		if (bp->options.trace) {
+			if (bp->options.lock) {
+				fprintf(stderr, " :lock");
+			} else {
+				fprintf(stderr, " :trace");
+			}
+			if (bp->options.noinit) {
+				fprintf(stderr, " :noinit");
+			}
+		}
+		if (bp->options.filename) {
+			fprintf(stderr, " :file %s", bp->options.filename);
+		}
+		if (bp->options.deleted) {
+			fprintf(stderr, " (deleted)");
+		}
+		fprintf(stderr, "\n");
+}
+
+/**
+ * List condition breakpoints
+ */
+static void BreakCond_List(bc_breakpoints_t *bps)
+{
+	bc_breakpoint_t *bp;
+	int i;
+
+	if (!bps->count) {
+		fprintf(stderr, "No conditional %s breakpoints.\n", bps->name);
+		return;
+	}
+	fprintf(stderr, "%d conditional %s breakpoints:\n", bps->count, bps->name);
+	bp = bps->breakpoint;
+	for (i = 1; i <= bps->count; bp++, i++) {
+		fprintf(stderr, "%4d:", i);
+		BreakCond_Print(bp);
+	}
+}
+
+
+/**
+ * Remove condition breakpoint at given position
+ */
+static bool BreakCond_Remove(bc_breakpoints_t *bps, int position)
+{
+	bc_breakpoint_t *bp;
+
+	if (!bps->count) {
+		fprintf(stderr, "No (more) %s breakpoints to remove.\n", bps->name);
+		return false;
+	}
+	if (position < 1 || position > bps->count) {
+		fprintf(stderr, "ERROR: No such %s breakpoint.\n", bps->name);
+		return false;
+	}
+	bp = bps->breakpoint + (position - 1);
+	if (bps->delayed_change) {
+		bp->options.deleted = true;
+		return true;
+	}
+	if (!bp->options.quiet) {
+		fprintf(stderr, "Removed %s breakpoint %d:\n", bps->name, position);
+		BreakCond_Print(bp);
+	}
+	free(bp->expression);
+	free(bp->conditions);
+	bp->expression = NULL;
+	bp->conditions = NULL;
+
+	if (bp->options.filename) {
+		free(bp->options.filename);
+	}
+
+	if (position < bps->count) {
+		memmove(bp, bp + 1, (bps->count - position) * sizeof(bc_breakpoint_t));
+	}
+	bps->count--;
+	return true;
+}
+
+
+/**
+ * Remove all conditional breakpoints
+ */
+static void BreakCond_RemoveAll(bc_breakpoints_t *bps)
+{
+	bool removed;
+	int i;
+
+	for (i = bps->count; i > 0; i--) {
+		removed = BreakCond_Remove(bps, i);
+		ASSERT_VARIABLE(removed);
+	}
+	fprintf(stderr, "%s breakpoints: %d\n", bps->name, bps->count);
+}
+
+/**
+ * Do delayed actions (remove breakpoints and old array alloc)
+ * 
+ * If those removals affect the triggered breakpoint index, update it.
+ * 
+ * Return updated breakpoint index.
+ */
+static int BreakCond_DoDelayedActions(bc_breakpoints_t *bps, int triggered)
+{
+	bc_options_t *options;
+	bool removed;
+	int i;
+
+	assert(!bps->delayed_change);
+	if (bps->breakpoint2delete) {
+		free(bps->breakpoint2delete);
+		bps->breakpoint2delete = NULL;
+	}
+	for (i = bps->count; i > 0; i--) {
+		options = &(bps->breakpoint[i-1].options);
+		if (options->deleted) {
+			options->deleted = false;
+			removed = BreakCond_Remove(bps, i);
+			ASSERT_VARIABLE(removed);
+			if (triggered >= i) {
+				triggered--;
+			}
+		}
+	}
+	return triggered;
+}
+
+
+/**
+ * Return true if given CPU breakpoint has given CPU expression.
+ * Used by the test code.
+ */
+int BreakCond_MatchCpuExpression(int position, const char *expression)
+{
+	if (position < 1 || position > CpuBreakPoints.count) {
+		return false;
+	}
+	if (strcmp(expression, CpuBreakPoints.breakpoint[position-1].expression)) {
+		return false;
+	}
+	return true;
+}
+
+
+/**
+ * help
+ */
+static void BreakCond_Help(void)
+{
+	Uint32 value;
+	int i;
+	fputs(
+"  condition = [.mode] [& ]  [.mode]\n"
+"\n"
+"  where:\n"
+"  	value = [(]  [)]\n"
+"  	number/mask = [#|$|%]\n"
+"  	comparison = '<' | '>' | '=' | '!'\n"
+"  	addressing mode (width) = 'b' | 'w' | 'l'\n"
+"  	addressing mode (space) = 'p' | 'x' | 'y'\n"
+"\n"
+"  If the value is in parenthesis like in '($ff820)' or '(a0)', then\n"
+"  the used value will be read from the memory address pointed by it.\n"
+"\n"
+"  If the parsed value expressions on both sides of it are exactly\n"
+"  the same, right side is replaced with its current value.  For\n"
+"  inequality ('!') comparison, the breakpoint will additionally track\n"
+"  all further changes for the given address/register expression value.\n"
+"  (This is useful for tracking register and memory value changes.)\n"
+"\n"
+"  M68k addresses can have byte (b), word (w) or long (l, default) width.\n"
+"  DSP addresses belong to different address spaces: P, X or Y. Note that\n"
+"  on DSP only R0-R7 registers can be used for memory addressing.\n"
+"\n"
+"  Valid Hatari variable names (and their current values) are:\n", stderr);
+	for (i = 0; i < ARRAYSIZE(hatari_vars); i++) {
+		const var_addr_t *hvar = hatari_vars + i;
+		switch (hvar->vtype) {
+		case VALUE_TYPE_FUNCTION32:
+			value = ((Uint32(*)(void))(hvar->addr))();
+			break;
+		case VALUE_TYPE_VAR32:
+			value = *(hvar->addr);
+			break;
+		default:
+			fprintf(stderr, "ERROR: variable '%s' has unsupported type '%d'\n",
+				hvar->name, hvar->vtype);
+			continue;
+		}
+		fprintf(stderr, "  - %s ($%x)", hvar->name, value);
+		if (hvar->constraints) {
+			fprintf(stderr, ", %s\n", hvar->constraints);
+		} else {
+			fprintf(stderr, "\n");
+		}
+	}
+	fputs(
+"\n"
+"  Examples:\n"
+"  	pc = $64543  &&  ($ff820).w & 3 = (a0)  &&  d0 = %1100\n"
+"       ($ffff9202).w ! ($ffff9202).w :trace\n"
+"  	(r0).x = 1 && (r0).y = 2\n", stderr);
+}
+
+
+/* ------------- breakpoint condition parsing, public API ------------ */
+
+const char BreakCond_Description[] =
+	" [&&  ...] [: